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X86InstrInfo.h
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1 //===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the X86 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_X86_X86INSTRINFO_H
15 #define LLVM_LIB_TARGET_X86_X86INSTRINFO_H
16 
18 #include "X86InstrFMA3Info.h"
19 #include "X86RegisterInfo.h"
22 #include <vector>
23 
24 #define GET_INSTRINFO_HEADER
25 #include "X86GenInstrInfo.inc"
26 
27 namespace llvm {
28 class MachineInstrBuilder;
29 class X86RegisterInfo;
30 class X86Subtarget;
31 
32 namespace X86 {
33 
35  // For instr that was compressed from EVEX to VEX.
37 };
38 
39 // X86 specific condition code. These correspond to X86_*_COND in
40 // X86InstrInfo.td. They must be kept in synch.
41 enum CondCode {
42  COND_A = 0,
43  COND_AE = 1,
44  COND_B = 2,
45  COND_BE = 3,
46  COND_E = 4,
47  COND_G = 5,
48  COND_GE = 6,
49  COND_L = 7,
50  COND_LE = 8,
51  COND_NE = 9,
52  COND_NO = 10,
53  COND_NP = 11,
54  COND_NS = 12,
55  COND_O = 13,
56  COND_P = 14,
57  COND_S = 15,
59 
60  // Artificial condition codes. These are used by AnalyzeBranch
61  // to indicate a block terminated with two conditional branches that together
62  // form a compound condition. They occur in code using FCMP_OEQ or FCMP_UNE,
63  // which can't be represented on x86 with a single condition. These
64  // are never used in MachineInstrs and are inverses of one another.
67 
69 };
70 
71 // Turn condition code into conditional branch opcode.
72 unsigned GetCondBranchFromCond(CondCode CC);
73 
74 /// Return a pair of condition code for the given predicate and whether
75 /// the instruction operands should be swaped to match the condition code.
76 std::pair<CondCode, bool> getX86ConditionCode(CmpInst::Predicate Predicate);
77 
78 /// Return a set opcode for the given condition and whether it has
79 /// a memory operand.
80 unsigned getSETFromCond(CondCode CC, bool HasMemoryOperand = false);
81 
82 /// Return a cmov opcode for the given condition, register size in
83 /// bytes, and operand type.
84 unsigned getCMovFromCond(CondCode CC, unsigned RegBytes,
85  bool HasMemoryOperand = false);
86 
87 // Turn jCC opcode into condition code.
88 CondCode getCondFromBranchOpc(unsigned Opc);
89 
90 // Turn setCC opcode into condition code.
91 CondCode getCondFromSETOpc(unsigned Opc);
92 
93 // Turn CMov opcode into condition code.
94 CondCode getCondFromCMovOpc(unsigned Opc);
95 
96 /// GetOppositeBranchCondition - Return the inverse of the specified cond,
97 /// e.g. turning COND_E to COND_NE.
99 
100 /// Get the VPCMP immediate for the given condition.
101 unsigned getVPCMPImmForCond(ISD::CondCode CC);
102 
103 /// Get the VPCMP immediate if the opcodes are swapped.
104 unsigned getSwappedVPCMPImm(unsigned Imm);
105 
106 /// Get the VPCOM immediate if the opcodes are swapped.
107 unsigned getSwappedVPCOMImm(unsigned Imm);
108 
109 } // namespace X86
110 
111 /// isGlobalStubReference - Return true if the specified TargetFlag operand is
112 /// a reference to a stub for a global, not the global itself.
113 inline static bool isGlobalStubReference(unsigned char TargetFlag) {
114  switch (TargetFlag) {
115  case X86II::MO_DLLIMPORT: // dllimport stub.
116  case X86II::MO_GOTPCREL: // rip-relative GOT reference.
117  case X86II::MO_GOT: // normal GOT reference.
118  case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref.
119  case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref.
120  case X86II::MO_COFFSTUB: // COFF .refptr stub.
121  return true;
122  default:
123  return false;
124  }
125 }
126 
127 /// isGlobalRelativeToPICBase - Return true if the specified global value
128 /// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this
129 /// is true, the addressing mode has the PIC base register added in (e.g. EBX).
130 inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) {
131  switch (TargetFlag) {
132  case X86II::MO_GOTOFF: // isPICStyleGOT: local global.
133  case X86II::MO_GOT: // isPICStyleGOT: other global.
134  case X86II::MO_PIC_BASE_OFFSET: // Darwin local global.
135  case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global.
136  case X86II::MO_TLVP: // ??? Pretty sure..
137  return true;
138  default:
139  return false;
140  }
141 }
142 
143 inline static bool isScale(const MachineOperand &MO) {
144  return MO.isImm() && (MO.getImm() == 1 || MO.getImm() == 2 ||
145  MO.getImm() == 4 || MO.getImm() == 8);
146 }
147 
148 inline static bool isLeaMem(const MachineInstr &MI, unsigned Op) {
149  if (MI.getOperand(Op).isFI())
150  return true;
151  return Op + X86::AddrSegmentReg <= MI.getNumOperands() &&
152  MI.getOperand(Op + X86::AddrBaseReg).isReg() &&
154  MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
155  (MI.getOperand(Op + X86::AddrDisp).isImm() ||
156  MI.getOperand(Op + X86::AddrDisp).isGlobal() ||
157  MI.getOperand(Op + X86::AddrDisp).isCPI() ||
158  MI.getOperand(Op + X86::AddrDisp).isJTI());
159 }
160 
161 inline static bool isMem(const MachineInstr &MI, unsigned Op) {
162  if (MI.getOperand(Op).isFI())
163  return true;
164  return Op + X86::AddrNumOperands <= MI.getNumOperands() &&
165  MI.getOperand(Op + X86::AddrSegmentReg).isReg() && isLeaMem(MI, Op);
166 }
167 
168 class X86InstrInfo final : public X86GenInstrInfo {
169  X86Subtarget &Subtarget;
170  const X86RegisterInfo RI;
171 
172  virtual void anchor();
173 
174  bool AnalyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
175  MachineBasicBlock *&FBB,
177  SmallVectorImpl<MachineInstr *> &CondBranches,
178  bool AllowModify) const;
179 
180 public:
181  explicit X86InstrInfo(X86Subtarget &STI);
182 
183  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
184  /// such, whenever a client has an instance of instruction info, it should
185  /// always be able to get register info as well (through this method).
186  ///
187  const X86RegisterInfo &getRegisterInfo() const { return RI; }
188 
189  /// Returns the stack pointer adjustment that happens inside the frame
190  /// setup..destroy sequence (e.g. by pushes, or inside the callee).
191  int64_t getFrameAdjustment(const MachineInstr &I) const {
192  assert(isFrameInstr(I));
193  if (isFrameSetup(I))
194  return I.getOperand(2).getImm();
195  return I.getOperand(1).getImm();
196  }
197 
198  /// Sets the stack pointer adjustment made inside the frame made up by this
199  /// instruction.
200  void setFrameAdjustment(MachineInstr &I, int64_t V) const {
201  assert(isFrameInstr(I));
202  if (isFrameSetup(I))
203  I.getOperand(2).setImm(V);
204  else
205  I.getOperand(1).setImm(V);
206  }
207 
208  /// getSPAdjust - This returns the stack pointer adjustment made by
209  /// this instruction. For x86, we need to handle more complex call
210  /// sequences involving PUSHes.
211  int getSPAdjust(const MachineInstr &MI) const override;
212 
213  /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
214  /// extension instruction. That is, it's like a copy where it's legal for the
215  /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
216  /// true, then it's expected the pre-extension value is available as a subreg
217  /// of the result register. This also returns the sub-register index in
218  /// SubIdx.
219  bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
220  unsigned &DstReg, unsigned &SubIdx) const override;
221 
222  unsigned isLoadFromStackSlot(const MachineInstr &MI,
223  int &FrameIndex) const override;
224  unsigned isLoadFromStackSlot(const MachineInstr &MI,
225  int &FrameIndex,
226  unsigned &MemBytes) const override;
227  /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
228  /// stack locations as well. This uses a heuristic so it isn't
229  /// reliable for correctness.
230  unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
231  int &FrameIndex) const override;
232 
233  unsigned isStoreToStackSlot(const MachineInstr &MI,
234  int &FrameIndex) const override;
235  unsigned isStoreToStackSlot(const MachineInstr &MI,
236  int &FrameIndex,
237  unsigned &MemBytes) const override;
238  /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
239  /// stack locations as well. This uses a heuristic so it isn't
240  /// reliable for correctness.
241  unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
242  int &FrameIndex) const override;
243 
244  bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
245  AliasAnalysis *AA) const override;
246  void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
247  unsigned DestReg, unsigned SubIdx,
248  const MachineInstr &Orig,
249  const TargetRegisterInfo &TRI) const override;
250 
251  /// Given an operand within a MachineInstr, insert preceding code to put it
252  /// into the right format for a particular kind of LEA instruction. This may
253  /// involve using an appropriate super-register instead (with an implicit use
254  /// of the original) or creating a new virtual register and inserting COPY
255  /// instructions to get the data into the right class.
256  ///
257  /// Reference parameters are set to indicate how caller should add this
258  /// operand to the LEA instruction.
259  bool classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
260  unsigned LEAOpcode, bool AllowSP, unsigned &NewSrc,
261  bool &isKill, MachineOperand &ImplicitOp,
262  LiveVariables *LV) const;
263 
264  /// convertToThreeAddress - This method must be implemented by targets that
265  /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
266  /// may be able to convert a two-address instruction into a true
267  /// three-address instruction on demand. This allows the X86 target (for
268  /// example) to convert ADD and SHL instructions into LEA instructions if they
269  /// would require register copies due to two-addressness.
270  ///
271  /// This method returns a null pointer if the transformation cannot be
272  /// performed, otherwise it returns the new instruction.
273  ///
274  MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
275  MachineInstr &MI,
276  LiveVariables *LV) const override;
277 
278  /// Returns true iff the routine could find two commutable operands in the
279  /// given machine instruction.
280  /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their
281  /// input values can be re-defined in this method only if the input values
282  /// are not pre-defined, which is designated by the special value
283  /// 'CommuteAnyOperandIndex' assigned to it.
284  /// If both of indices are pre-defined and refer to some operands, then the
285  /// method simply returns true if the corresponding operands are commutable
286  /// and returns false otherwise.
287  ///
288  /// For example, calling this method this way:
289  /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
290  /// findCommutedOpIndices(MI, Op1, Op2);
291  /// can be interpreted as a query asking to find an operand that would be
292  /// commutable with the operand#1.
293  bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
294  unsigned &SrcOpIdx2) const override;
295 
296  /// Returns an adjusted FMA opcode that must be used in FMA instruction that
297  /// performs the same computations as the given \p MI but which has the
298  /// operands \p SrcOpIdx1 and \p SrcOpIdx2 commuted.
299  /// It may return 0 if it is unsafe to commute the operands.
300  /// Note that a machine instruction (instead of its opcode) is passed as the
301  /// first parameter to make it possible to analyze the instruction's uses and
302  /// commute the first operand of FMA even when it seems unsafe when you look
303  /// at the opcode. For example, it is Ok to commute the first operand of
304  /// VFMADD*SD_Int, if ONLY the lowest 64-bit element of the result is used.
305  ///
306  /// The returned FMA opcode may differ from the opcode in the given \p MI.
307  /// For example, commuting the operands #1 and #3 in the following FMA
308  /// FMA213 #1, #2, #3
309  /// results into instruction with adjusted opcode:
310  /// FMA231 #3, #2, #1
311  unsigned
312  getFMA3OpcodeToCommuteOperands(const MachineInstr &MI, unsigned SrcOpIdx1,
313  unsigned SrcOpIdx2,
314  const X86InstrFMA3Group &FMA3Group) const;
315 
316  // Branch analysis.
317  bool isUnpredicatedTerminator(const MachineInstr &MI) const override;
318  bool isUnconditionalTailCall(const MachineInstr &MI) const override;
319  bool canMakeTailCallConditional(SmallVectorImpl<MachineOperand> &Cond,
320  const MachineInstr &TailCall) const override;
321  void replaceBranchWithTailCall(MachineBasicBlock &MBB,
323  const MachineInstr &TailCall) const override;
324 
325  bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
326  MachineBasicBlock *&FBB,
328  bool AllowModify) const override;
329 
330  bool getMemOperandWithOffset(MachineInstr &LdSt, MachineOperand *&BaseOp,
331  int64_t &Offset,
332  const TargetRegisterInfo *TRI) const override;
333  bool analyzeBranchPredicate(MachineBasicBlock &MBB,
335  bool AllowModify = false) const override;
336 
337  unsigned removeBranch(MachineBasicBlock &MBB,
338  int *BytesRemoved = nullptr) const override;
339  unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
341  const DebugLoc &DL,
342  int *BytesAdded = nullptr) const override;
343  bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
344  unsigned, unsigned, int &, int &, int &) const override;
345  void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
346  const DebugLoc &DL, unsigned DstReg,
347  ArrayRef<MachineOperand> Cond, unsigned TrueReg,
348  unsigned FalseReg) const override;
349  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
350  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
351  bool KillSrc) const override;
352  void storeRegToStackSlot(MachineBasicBlock &MBB,
353  MachineBasicBlock::iterator MI, unsigned SrcReg,
354  bool isKill, int FrameIndex,
355  const TargetRegisterClass *RC,
356  const TargetRegisterInfo *TRI) const override;
357 
358  void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
360  const TargetRegisterClass *RC,
362  SmallVectorImpl<MachineInstr *> &NewMIs) const;
363 
364  void loadRegFromStackSlot(MachineBasicBlock &MBB,
365  MachineBasicBlock::iterator MI, unsigned DestReg,
366  int FrameIndex, const TargetRegisterClass *RC,
367  const TargetRegisterInfo *TRI) const override;
368 
369  void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
371  const TargetRegisterClass *RC,
373  SmallVectorImpl<MachineInstr *> &NewMIs) const;
374 
375  bool expandPostRAPseudo(MachineInstr &MI) const override;
376 
377  /// Check whether the target can fold a load that feeds a subreg operand
378  /// (or a subreg operand that feeds a store).
379  bool isSubregFoldable() const override { return true; }
380 
381  /// foldMemoryOperand - If this target supports it, fold a load or store of
382  /// the specified stack slot into the specified machine instruction for the
383  /// specified operand(s). If this is possible, the target should perform the
384  /// folding and return true, otherwise it should return false. If it folds
385  /// the instruction, it is likely that the MachineInstruction the iterator
386  /// references has been changed.
387  MachineInstr *
388  foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
389  ArrayRef<unsigned> Ops,
390  MachineBasicBlock::iterator InsertPt, int FrameIndex,
391  LiveIntervals *LIS = nullptr) const override;
392 
393  /// foldMemoryOperand - Same as the previous version except it allows folding
394  /// of any load and store from / to any address, not just from a specific
395  /// stack slot.
396  MachineInstr *foldMemoryOperandImpl(
398  MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
399  LiveIntervals *LIS = nullptr) const override;
400 
401  /// unfoldMemoryOperand - Separate a single instruction which folded a load or
402  /// a store or a load and a store into two or more instruction. If this is
403  /// possible, returns true as well as the new instructions by reference.
404  bool
405  unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg,
406  bool UnfoldLoad, bool UnfoldStore,
407  SmallVectorImpl<MachineInstr *> &NewMIs) const override;
408 
409  bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
410  SmallVectorImpl<SDNode *> &NewNodes) const override;
411 
412  /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
413  /// instruction after load / store are unfolded from an instruction of the
414  /// specified opcode. It returns zero if the specified unfolding is not
415  /// possible. If LoadRegIndex is non-null, it is filled in with the operand
416  /// index of the operand which will hold the register holding the loaded
417  /// value.
418  unsigned
419  getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore,
420  unsigned *LoadRegIndex = nullptr) const override;
421 
422  /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
423  /// to determine if two loads are loading from the same base address. It
424  /// should only return true if the base pointers are the same and the
425  /// only differences between the two addresses are the offset. It also returns
426  /// the offsets by reference.
427  bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
428  int64_t &Offset2) const override;
429 
430  /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
431  /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
432  /// should be scheduled togther. On some targets if two loads are loading from
433  /// addresses in the same cache line, it's better if they are scheduled
434  /// together. This function takes two integers that represent the load offsets
435  /// from the common base address. It returns true if it decides it's desirable
436  /// to schedule the two loads together. "NumLoads" is the number of loads that
437  /// have already been scheduled after Load1.
438  bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1,
439  int64_t Offset2,
440  unsigned NumLoads) const override;
441 
442  void getNoop(MCInst &NopInst) const override;
443 
444  bool
445  reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
446 
447  /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
448  /// instruction that defines the specified register class.
449  bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
450 
451  /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction tha
452  /// would clobber the EFLAGS condition register. Note the result may be
453  /// conservative. If it cannot definitely determine the safety after visiting
454  /// a few instructions in each direction it assumes it's not safe.
455  bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
457 
458  /// True if MI has a condition code def, e.g. EFLAGS, that is
459  /// not marked dead.
460  bool hasLiveCondCodeDef(MachineInstr &MI) const;
461 
462  /// getGlobalBaseReg - Return a virtual register initialized with the
463  /// the global base register value. Output instructions required to
464  /// initialize the register in the function entry block, if necessary.
465  ///
466  unsigned getGlobalBaseReg(MachineFunction *MF) const;
467 
468  std::pair<uint16_t, uint16_t>
469  getExecutionDomain(const MachineInstr &MI) const override;
470 
471  uint16_t getExecutionDomainCustom(const MachineInstr &MI) const;
472 
473  void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override;
474 
475  bool setExecutionDomainCustom(MachineInstr &MI, unsigned Domain) const;
476 
477  unsigned
478  getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum,
479  const TargetRegisterInfo *TRI) const override;
480  unsigned getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
481  const TargetRegisterInfo *TRI) const override;
482  void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
483  const TargetRegisterInfo *TRI) const override;
484 
485  MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
486  unsigned OpNum,
489  unsigned Size, unsigned Alignment,
490  bool AllowCommute) const;
491 
492  bool isHighLatencyDef(int opc) const override;
493 
494  bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
495  const MachineRegisterInfo *MRI,
496  const MachineInstr &DefMI, unsigned DefIdx,
497  const MachineInstr &UseMI,
498  unsigned UseIdx) const override;
499 
500  bool useMachineCombiner() const override { return true; }
501 
502  bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
503 
504  bool hasReassociableOperands(const MachineInstr &Inst,
505  const MachineBasicBlock *MBB) const override;
506 
507  void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
508  MachineInstr &NewMI1,
509  MachineInstr &NewMI2) const override;
510 
511  /// analyzeCompare - For a comparison instruction, return the source registers
512  /// in SrcReg and SrcReg2 if having two register operands, and the value it
513  /// compares against in CmpValue. Return true if the comparison instruction
514  /// can be analyzed.
515  bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
516  unsigned &SrcReg2, int &CmpMask,
517  int &CmpValue) const override;
518 
519  /// optimizeCompareInstr - Check if there exists an earlier instruction that
520  /// operates on the same source operands and sets flags in the same way as
521  /// Compare; remove Compare if possible.
522  bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
523  unsigned SrcReg2, int CmpMask, int CmpValue,
524  const MachineRegisterInfo *MRI) const override;
525 
526  /// optimizeLoadInstr - Try to remove the load by folding it to a register
527  /// operand at the use. We fold the load instructions if and only if the
528  /// def and use are in the same BB. We only look at one load and see
529  /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
530  /// defined by the load we are trying to fold. DefMI returns the machine
531  /// instruction that defines FoldAsLoadDefReg, and the function returns
532  /// the machine instruction generated due to folding.
533  MachineInstr *optimizeLoadInstr(MachineInstr &MI,
534  const MachineRegisterInfo *MRI,
535  unsigned &FoldAsLoadDefReg,
536  MachineInstr *&DefMI) const override;
537 
538  std::pair<unsigned, unsigned>
539  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
540 
542  getSerializableDirectMachineOperandTargetFlags() const override;
543 
544  virtual outliner::OutlinedFunction getOutliningCandidateInfo(
545  std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override;
546 
547  bool isFunctionSafeToOutlineFrom(MachineFunction &MF,
548  bool OutlineFromLinkOnceODRs) const override;
549 
551  getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const override;
552 
553  void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF,
554  const outliner::OutlinedFunction &OF) const override;
555 
557  insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
559  const outliner::Candidate &C) const override;
560 
561 #define GET_INSTRINFO_HELPER_DECLS
562 #include "X86GenInstrInfo.inc"
563 
564 protected:
565  /// Commutes the operands in the given instruction by changing the operands
566  /// order and/or changing the instruction's opcode and/or the immediate value
567  /// operand.
568  ///
569  /// The arguments 'CommuteOpIdx1' and 'CommuteOpIdx2' specify the operands
570  /// to be commuted.
571  ///
572  /// Do not call this method for a non-commutable instruction or
573  /// non-commutable operands.
574  /// Even though the instruction is commutable, the method may still
575  /// fail to commute the operands, null pointer is returned in such cases.
576  MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
577  unsigned CommuteOpIdx1,
578  unsigned CommuteOpIdx2) const override;
579 
580  /// If the specific machine instruction is a instruction that moves/copies
581  /// value from one register to another register return true along with
582  /// @Source machine operand and @Destination machine operand.
583  bool isCopyInstrImpl(const MachineInstr &MI, const MachineOperand *&Source,
584  const MachineOperand *&Destination) const override;
585 
586 private:
587  /// This is a helper for convertToThreeAddress for 8 and 16-bit instructions.
588  /// We use 32-bit LEA to form 3-address code by promoting to a 32-bit
589  /// super-register and then truncating back down to a 8/16-bit sub-register.
590  MachineInstr *convertToThreeAddressWithLEA(unsigned MIOpc,
592  MachineInstr &MI,
593  LiveVariables *LV) const;
594 
595  /// Handles memory folding for special case instructions, for instance those
596  /// requiring custom manipulation of the address.
597  MachineInstr *foldMemoryOperandCustom(MachineFunction &MF, MachineInstr &MI,
598  unsigned OpNum,
599  ArrayRef<MachineOperand> MOs,
601  unsigned Size, unsigned Align) const;
602 
603  /// isFrameOperand - Return true and the FrameIndex if the specified
604  /// operand and follow operands form a reference to the stack frame.
605  bool isFrameOperand(const MachineInstr &MI, unsigned int Op,
606  int &FrameIndex) const;
607 
608  /// Returns true iff the routine could find two commutable operands in the
609  /// given machine instruction with 3 vector inputs.
610  /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their
611  /// input values can be re-defined in this method only if the input values
612  /// are not pre-defined, which is designated by the special value
613  /// 'CommuteAnyOperandIndex' assigned to it.
614  /// If both of indices are pre-defined and refer to some operands, then the
615  /// method simply returns true if the corresponding operands are commutable
616  /// and returns false otherwise.
617  ///
618  /// For example, calling this method this way:
619  /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
620  /// findThreeSrcCommutedOpIndices(MI, Op1, Op2);
621  /// can be interpreted as a query asking to find an operand that would be
622  /// commutable with the operand#1.
623  ///
624  /// If IsIntrinsic is set, operand 1 will be ignored for commuting.
625  bool findThreeSrcCommutedOpIndices(const MachineInstr &MI,
626  unsigned &SrcOpIdx1,
627  unsigned &SrcOpIdx2,
628  bool IsIntrinsic = false) const;
629 };
630 
631 } // namespace llvm
632 
633 #endif
void setFrameAdjustment(MachineInstr &I, int64_t V) const
Sets the stack pointer adjustment made inside the frame made up by this instruction.
Definition: X86InstrInfo.h:200
unsigned GetCondBranchFromCond(CondCode CC)
uint64_t CallInst * C
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
static bool isScale(const MachineOperand &MO)
Definition: X86InstrInfo.h:143
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "...
Definition: X86BaseInfo.h:238
This class represents lattice values for constants.
Definition: AllocatorList.h:24
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:65
This class is used to group {132, 213, 231} forms of FMA opcodes together.
CondCode getCondFromCMovOpc(unsigned Opc)
Return condition code of a CMov opcode.
unsigned Reg
CondCode getCondFromSETOpc(unsigned Opc)
Return condition code of a SET opcode.
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:34
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...
Definition: X86BaseInfo.h:110
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
An individual sequence of instructions to be replaced with a call to an outlined function.
Represents a predicate at the MachineFunction level.
MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates that the reference is actually...
Definition: X86BaseInfo.h:210
Provide an instruction scheduling machine model to CodeGen passes.
AddrSegmentReg - The operand # of the segment in the memory operand.
Definition: X86BaseInfo.h:39
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:412
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
static bool isGlobalStubReference(unsigned char TargetFlag)
isGlobalStubReference - Return true if the specified TargetFlag operand is a reference to a stub for ...
Definition: X86InstrInfo.h:113
CondCode getCondFromBranchOpc(unsigned Opc)
unsigned getSwappedVPCMPImm(unsigned Imm)
Get the VPCMP immediate if the opcodes are swapped.
static bool isMem(const MachineInstr &MI, unsigned Op)
Definition: X86InstrInfo.h:161
static bool isGlobalRelativeToPICBase(unsigned char TargetFlag)
isGlobalRelativeToPICBase - Return true if the specified global value reference is relative to a 32-b...
Definition: X86InstrInfo.h:130
MO_GOT - On a symbol operand this indicates that the immediate is the offset to the GOT entry for the...
Definition: X86BaseInfo.h:95
unsigned getSwappedVPCOMImm(unsigned Imm)
Get the VPCOM immediate if the opcodes are swapped.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:959
static bool isLeaMem(const MachineInstr &MI, unsigned Op)
Definition: X86InstrInfo.h:148
MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the reference is actually to the "...
Definition: X86BaseInfo.h:205
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:161
BasicBlockListType::iterator iterator
AddrNumOperands - Total number of operands in a memory reference.
Definition: X86BaseInfo.h:42
MachineInstrBundleIterator< MachineInstr > iterator
std::pair< CondCode, bool > getX86ConditionCode(CmpInst::Predicate Predicate)
Return a pair of condition code for the given predicate and whether the instruction operands should b...
unsigned const MachineRegisterInfo * MRI
InstrType
Represents how an instruction should be mapped by the outliner.
MO_TLVP - On a symbol operand this indicates that the immediate is some TLS offset.
Definition: X86BaseInfo.h:216
MachineInstrBuilder & UseMI
The information necessary to create an outlined function for some class of candidate.
unsigned getVPCMPImmForCond(ISD::CondCode CC)
Get the VPCMP immediate for the given condition.
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:642
void setImm(int64_t immVal)
bool useMachineCombiner() const override
Definition: X86InstrInfo.h:500
unsigned getSETFromCond(CondCode CC, bool HasMemoryOperand=false)
Return a set opcode for the given condition and whether it has a memory operand.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Iterator for intrusive lists based on ilist_node.
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:222
MachineOperand class - Representation of each machine instruction operand.
CondCode GetOppositeBranchCondition(CondCode CC)
GetOppositeBranchCondition - Return the inverse of the specified cond, e.g.
MachineInstrBuilder MachineInstrBuilder & DefMI
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:27
int64_t getFrameAdjustment(const MachineInstr &I) const
Returns the stack pointer adjustment that happens inside the frame setup..destroy sequence (e...
Definition: X86InstrInfo.h:191
const X86RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: X86InstrInfo.h:187
Represents one node in the SelectionDAG.
int64_t getImm() const
unsigned getCMovFromCond(CondCode CC, unsigned RegBytes, bool HasMemoryOperand=false)
Return a cmov opcode for the given condition, register size in bytes, and operand type...
bool isSubregFoldable() const override
Check whether the target can fold a load that feeds a subreg operand (or a subreg operand that feeds ...
Definition: X86InstrInfo.h:379
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:64
MO_GOTOFF - On a symbol operand this indicates that the immediate is the offset to the location of th...
Definition: X86BaseInfo.h:102
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
uint32_t Size
Definition: Profile.cpp:47
bool isReg() const
isReg - Tests if this is a MO_Register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the immediate should get the value of th...
Definition: X86BaseInfo.h:88
IRTranslator LLVM IR MI
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:414
MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the reference is actually to the "__imp...
Definition: X86BaseInfo.h:200