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X86InstrInfo.h
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1 //===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the X86 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_X86_X86INSTRINFO_H
14 #define LLVM_LIB_TARGET_X86_X86INSTRINFO_H
15 
17 #include "X86InstrFMA3Info.h"
18 #include "X86RegisterInfo.h"
21 #include <vector>
22 
23 #define GET_INSTRINFO_HEADER
24 #include "X86GenInstrInfo.inc"
25 
26 namespace llvm {
27 class MachineInstrBuilder;
28 class X86RegisterInfo;
29 class X86Subtarget;
30 
31 namespace X86 {
32 
34  // For instr that was compressed from EVEX to VEX.
36 };
37 
38 // X86 specific condition code. These correspond to X86_*_COND in
39 // X86InstrInfo.td. They must be kept in synch.
40 enum CondCode {
41  COND_A = 0,
42  COND_AE = 1,
43  COND_B = 2,
44  COND_BE = 3,
45  COND_E = 4,
46  COND_G = 5,
47  COND_GE = 6,
48  COND_L = 7,
49  COND_LE = 8,
50  COND_NE = 9,
51  COND_NO = 10,
52  COND_NP = 11,
53  COND_NS = 12,
54  COND_O = 13,
55  COND_P = 14,
56  COND_S = 15,
58 
59  // Artificial condition codes. These are used by AnalyzeBranch
60  // to indicate a block terminated with two conditional branches that together
61  // form a compound condition. They occur in code using FCMP_OEQ or FCMP_UNE,
62  // which can't be represented on x86 with a single condition. These
63  // are never used in MachineInstrs and are inverses of one another.
66 
68 };
69 
70 // Turn condition code into conditional branch opcode.
71 unsigned GetCondBranchFromCond(CondCode CC);
72 
73 /// Return a pair of condition code for the given predicate and whether
74 /// the instruction operands should be swaped to match the condition code.
75 std::pair<CondCode, bool> getX86ConditionCode(CmpInst::Predicate Predicate);
76 
77 /// Return a set opcode for the given condition and whether it has
78 /// a memory operand.
79 unsigned getSETFromCond(CondCode CC, bool HasMemoryOperand = false);
80 
81 /// Return a cmov opcode for the given condition, register size in
82 /// bytes, and operand type.
83 unsigned getCMovFromCond(CondCode CC, unsigned RegBytes,
84  bool HasMemoryOperand = false);
85 
86 // Turn jCC opcode into condition code.
87 CondCode getCondFromBranchOpc(unsigned Opc);
88 
89 // Turn setCC opcode into condition code.
90 CondCode getCondFromSETOpc(unsigned Opc);
91 
92 // Turn CMov opcode into condition code.
93 CondCode getCondFromCMovOpc(unsigned Opc);
94 
95 /// GetOppositeBranchCondition - Return the inverse of the specified cond,
96 /// e.g. turning COND_E to COND_NE.
98 
99 /// Get the VPCMP immediate for the given condition.
100 unsigned getVPCMPImmForCond(ISD::CondCode CC);
101 
102 /// Get the VPCMP immediate if the opcodes are swapped.
103 unsigned getSwappedVPCMPImm(unsigned Imm);
104 
105 /// Get the VPCOM immediate if the opcodes are swapped.
106 unsigned getSwappedVPCOMImm(unsigned Imm);
107 
108 } // namespace X86
109 
110 /// isGlobalStubReference - Return true if the specified TargetFlag operand is
111 /// a reference to a stub for a global, not the global itself.
112 inline static bool isGlobalStubReference(unsigned char TargetFlag) {
113  switch (TargetFlag) {
114  case X86II::MO_DLLIMPORT: // dllimport stub.
115  case X86II::MO_GOTPCREL: // rip-relative GOT reference.
116  case X86II::MO_GOT: // normal GOT reference.
117  case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref.
118  case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref.
119  case X86II::MO_COFFSTUB: // COFF .refptr stub.
120  return true;
121  default:
122  return false;
123  }
124 }
125 
126 /// isGlobalRelativeToPICBase - Return true if the specified global value
127 /// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this
128 /// is true, the addressing mode has the PIC base register added in (e.g. EBX).
129 inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) {
130  switch (TargetFlag) {
131  case X86II::MO_GOTOFF: // isPICStyleGOT: local global.
132  case X86II::MO_GOT: // isPICStyleGOT: other global.
133  case X86II::MO_PIC_BASE_OFFSET: // Darwin local global.
134  case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global.
135  case X86II::MO_TLVP: // ??? Pretty sure..
136  return true;
137  default:
138  return false;
139  }
140 }
141 
142 inline static bool isScale(const MachineOperand &MO) {
143  return MO.isImm() && (MO.getImm() == 1 || MO.getImm() == 2 ||
144  MO.getImm() == 4 || MO.getImm() == 8);
145 }
146 
147 inline static bool isLeaMem(const MachineInstr &MI, unsigned Op) {
148  if (MI.getOperand(Op).isFI())
149  return true;
150  return Op + X86::AddrSegmentReg <= MI.getNumOperands() &&
151  MI.getOperand(Op + X86::AddrBaseReg).isReg() &&
153  MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
154  (MI.getOperand(Op + X86::AddrDisp).isImm() ||
155  MI.getOperand(Op + X86::AddrDisp).isGlobal() ||
156  MI.getOperand(Op + X86::AddrDisp).isCPI() ||
157  MI.getOperand(Op + X86::AddrDisp).isJTI());
158 }
159 
160 inline static bool isMem(const MachineInstr &MI, unsigned Op) {
161  if (MI.getOperand(Op).isFI())
162  return true;
163  return Op + X86::AddrNumOperands <= MI.getNumOperands() &&
164  MI.getOperand(Op + X86::AddrSegmentReg).isReg() && isLeaMem(MI, Op);
165 }
166 
167 class X86InstrInfo final : public X86GenInstrInfo {
168  X86Subtarget &Subtarget;
169  const X86RegisterInfo RI;
170 
171  virtual void anchor();
172 
173  bool AnalyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
174  MachineBasicBlock *&FBB,
176  SmallVectorImpl<MachineInstr *> &CondBranches,
177  bool AllowModify) const;
178 
179 public:
180  explicit X86InstrInfo(X86Subtarget &STI);
181 
182  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
183  /// such, whenever a client has an instance of instruction info, it should
184  /// always be able to get register info as well (through this method).
185  ///
186  const X86RegisterInfo &getRegisterInfo() const { return RI; }
187 
188  /// Returns the stack pointer adjustment that happens inside the frame
189  /// setup..destroy sequence (e.g. by pushes, or inside the callee).
190  int64_t getFrameAdjustment(const MachineInstr &I) const {
191  assert(isFrameInstr(I));
192  if (isFrameSetup(I))
193  return I.getOperand(2).getImm();
194  return I.getOperand(1).getImm();
195  }
196 
197  /// Sets the stack pointer adjustment made inside the frame made up by this
198  /// instruction.
199  void setFrameAdjustment(MachineInstr &I, int64_t V) const {
200  assert(isFrameInstr(I));
201  if (isFrameSetup(I))
202  I.getOperand(2).setImm(V);
203  else
204  I.getOperand(1).setImm(V);
205  }
206 
207  /// getSPAdjust - This returns the stack pointer adjustment made by
208  /// this instruction. For x86, we need to handle more complex call
209  /// sequences involving PUSHes.
210  int getSPAdjust(const MachineInstr &MI) const override;
211 
212  /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
213  /// extension instruction. That is, it's like a copy where it's legal for the
214  /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
215  /// true, then it's expected the pre-extension value is available as a subreg
216  /// of the result register. This also returns the sub-register index in
217  /// SubIdx.
218  bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
219  unsigned &DstReg, unsigned &SubIdx) const override;
220 
221  unsigned isLoadFromStackSlot(const MachineInstr &MI,
222  int &FrameIndex) const override;
223  unsigned isLoadFromStackSlot(const MachineInstr &MI,
224  int &FrameIndex,
225  unsigned &MemBytes) const override;
226  /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
227  /// stack locations as well. This uses a heuristic so it isn't
228  /// reliable for correctness.
229  unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
230  int &FrameIndex) const override;
231 
232  unsigned isStoreToStackSlot(const MachineInstr &MI,
233  int &FrameIndex) const override;
234  unsigned isStoreToStackSlot(const MachineInstr &MI,
235  int &FrameIndex,
236  unsigned &MemBytes) const override;
237  /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
238  /// stack locations as well. This uses a heuristic so it isn't
239  /// reliable for correctness.
240  unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
241  int &FrameIndex) const override;
242 
243  bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
244  AliasAnalysis *AA) const override;
245  void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
246  unsigned DestReg, unsigned SubIdx,
247  const MachineInstr &Orig,
248  const TargetRegisterInfo &TRI) const override;
249 
250  /// Given an operand within a MachineInstr, insert preceding code to put it
251  /// into the right format for a particular kind of LEA instruction. This may
252  /// involve using an appropriate super-register instead (with an implicit use
253  /// of the original) or creating a new virtual register and inserting COPY
254  /// instructions to get the data into the right class.
255  ///
256  /// Reference parameters are set to indicate how caller should add this
257  /// operand to the LEA instruction.
258  bool classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
259  unsigned LEAOpcode, bool AllowSP, unsigned &NewSrc,
260  bool &isKill, MachineOperand &ImplicitOp,
261  LiveVariables *LV) const;
262 
263  /// convertToThreeAddress - This method must be implemented by targets that
264  /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
265  /// may be able to convert a two-address instruction into a true
266  /// three-address instruction on demand. This allows the X86 target (for
267  /// example) to convert ADD and SHL instructions into LEA instructions if they
268  /// would require register copies due to two-addressness.
269  ///
270  /// This method returns a null pointer if the transformation cannot be
271  /// performed, otherwise it returns the new instruction.
272  ///
273  MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
274  MachineInstr &MI,
275  LiveVariables *LV) const override;
276 
277  /// Returns true iff the routine could find two commutable operands in the
278  /// given machine instruction.
279  /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their
280  /// input values can be re-defined in this method only if the input values
281  /// are not pre-defined, which is designated by the special value
282  /// 'CommuteAnyOperandIndex' assigned to it.
283  /// If both of indices are pre-defined and refer to some operands, then the
284  /// method simply returns true if the corresponding operands are commutable
285  /// and returns false otherwise.
286  ///
287  /// For example, calling this method this way:
288  /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
289  /// findCommutedOpIndices(MI, Op1, Op2);
290  /// can be interpreted as a query asking to find an operand that would be
291  /// commutable with the operand#1.
292  bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
293  unsigned &SrcOpIdx2) const override;
294 
295  /// Returns an adjusted FMA opcode that must be used in FMA instruction that
296  /// performs the same computations as the given \p MI but which has the
297  /// operands \p SrcOpIdx1 and \p SrcOpIdx2 commuted.
298  /// It may return 0 if it is unsafe to commute the operands.
299  /// Note that a machine instruction (instead of its opcode) is passed as the
300  /// first parameter to make it possible to analyze the instruction's uses and
301  /// commute the first operand of FMA even when it seems unsafe when you look
302  /// at the opcode. For example, it is Ok to commute the first operand of
303  /// VFMADD*SD_Int, if ONLY the lowest 64-bit element of the result is used.
304  ///
305  /// The returned FMA opcode may differ from the opcode in the given \p MI.
306  /// For example, commuting the operands #1 and #3 in the following FMA
307  /// FMA213 #1, #2, #3
308  /// results into instruction with adjusted opcode:
309  /// FMA231 #3, #2, #1
310  unsigned
311  getFMA3OpcodeToCommuteOperands(const MachineInstr &MI, unsigned SrcOpIdx1,
312  unsigned SrcOpIdx2,
313  const X86InstrFMA3Group &FMA3Group) const;
314 
315  // Branch analysis.
316  bool isUnpredicatedTerminator(const MachineInstr &MI) const override;
317  bool isUnconditionalTailCall(const MachineInstr &MI) const override;
318  bool canMakeTailCallConditional(SmallVectorImpl<MachineOperand> &Cond,
319  const MachineInstr &TailCall) const override;
320  void replaceBranchWithTailCall(MachineBasicBlock &MBB,
322  const MachineInstr &TailCall) const override;
323 
324  bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
325  MachineBasicBlock *&FBB,
327  bool AllowModify) const override;
328 
329  bool getMemOperandWithOffset(MachineInstr &LdSt, MachineOperand *&BaseOp,
330  int64_t &Offset,
331  const TargetRegisterInfo *TRI) const override;
332  bool analyzeBranchPredicate(MachineBasicBlock &MBB,
334  bool AllowModify = false) const override;
335 
336  unsigned removeBranch(MachineBasicBlock &MBB,
337  int *BytesRemoved = nullptr) const override;
338  unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
340  const DebugLoc &DL,
341  int *BytesAdded = nullptr) const override;
342  bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
343  unsigned, unsigned, int &, int &, int &) const override;
344  void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
345  const DebugLoc &DL, unsigned DstReg,
346  ArrayRef<MachineOperand> Cond, unsigned TrueReg,
347  unsigned FalseReg) const override;
348  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
349  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
350  bool KillSrc) const override;
351  void storeRegToStackSlot(MachineBasicBlock &MBB,
352  MachineBasicBlock::iterator MI, unsigned SrcReg,
353  bool isKill, int FrameIndex,
354  const TargetRegisterClass *RC,
355  const TargetRegisterInfo *TRI) const override;
356 
357  void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
359  const TargetRegisterClass *RC,
361  SmallVectorImpl<MachineInstr *> &NewMIs) const;
362 
363  void loadRegFromStackSlot(MachineBasicBlock &MBB,
364  MachineBasicBlock::iterator MI, unsigned DestReg,
365  int FrameIndex, const TargetRegisterClass *RC,
366  const TargetRegisterInfo *TRI) const override;
367 
368  void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
370  const TargetRegisterClass *RC,
372  SmallVectorImpl<MachineInstr *> &NewMIs) const;
373 
374  bool expandPostRAPseudo(MachineInstr &MI) const override;
375 
376  /// Check whether the target can fold a load that feeds a subreg operand
377  /// (or a subreg operand that feeds a store).
378  bool isSubregFoldable() const override { return true; }
379 
380  /// foldMemoryOperand - If this target supports it, fold a load or store of
381  /// the specified stack slot into the specified machine instruction for the
382  /// specified operand(s). If this is possible, the target should perform the
383  /// folding and return true, otherwise it should return false. If it folds
384  /// the instruction, it is likely that the MachineInstruction the iterator
385  /// references has been changed.
386  MachineInstr *
387  foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
388  ArrayRef<unsigned> Ops,
389  MachineBasicBlock::iterator InsertPt, int FrameIndex,
390  LiveIntervals *LIS = nullptr) const override;
391 
392  /// foldMemoryOperand - Same as the previous version except it allows folding
393  /// of any load and store from / to any address, not just from a specific
394  /// stack slot.
395  MachineInstr *foldMemoryOperandImpl(
397  MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
398  LiveIntervals *LIS = nullptr) const override;
399 
400  /// unfoldMemoryOperand - Separate a single instruction which folded a load or
401  /// a store or a load and a store into two or more instruction. If this is
402  /// possible, returns true as well as the new instructions by reference.
403  bool
404  unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg,
405  bool UnfoldLoad, bool UnfoldStore,
406  SmallVectorImpl<MachineInstr *> &NewMIs) const override;
407 
408  bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
409  SmallVectorImpl<SDNode *> &NewNodes) const override;
410 
411  /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
412  /// instruction after load / store are unfolded from an instruction of the
413  /// specified opcode. It returns zero if the specified unfolding is not
414  /// possible. If LoadRegIndex is non-null, it is filled in with the operand
415  /// index of the operand which will hold the register holding the loaded
416  /// value.
417  unsigned
418  getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore,
419  unsigned *LoadRegIndex = nullptr) const override;
420 
421  /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
422  /// to determine if two loads are loading from the same base address. It
423  /// should only return true if the base pointers are the same and the
424  /// only differences between the two addresses are the offset. It also returns
425  /// the offsets by reference.
426  bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
427  int64_t &Offset2) const override;
428 
429  /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
430  /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
431  /// should be scheduled togther. On some targets if two loads are loading from
432  /// addresses in the same cache line, it's better if they are scheduled
433  /// together. This function takes two integers that represent the load offsets
434  /// from the common base address. It returns true if it decides it's desirable
435  /// to schedule the two loads together. "NumLoads" is the number of loads that
436  /// have already been scheduled after Load1.
437  bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1,
438  int64_t Offset2,
439  unsigned NumLoads) const override;
440 
441  void getNoop(MCInst &NopInst) const override;
442 
443  bool
444  reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
445 
446  /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
447  /// instruction that defines the specified register class.
448  bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
449 
450  /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction tha
451  /// would clobber the EFLAGS condition register. Note the result may be
452  /// conservative. If it cannot definitely determine the safety after visiting
453  /// a few instructions in each direction it assumes it's not safe.
456  return MBB.computeRegisterLiveness(&RI, X86::EFLAGS, I, 4) ==
458  }
459 
460  /// True if MI has a condition code def, e.g. EFLAGS, that is
461  /// not marked dead.
462  bool hasLiveCondCodeDef(MachineInstr &MI) const;
463 
464  /// getGlobalBaseReg - Return a virtual register initialized with the
465  /// the global base register value. Output instructions required to
466  /// initialize the register in the function entry block, if necessary.
467  ///
468  unsigned getGlobalBaseReg(MachineFunction *MF) const;
469 
470  std::pair<uint16_t, uint16_t>
471  getExecutionDomain(const MachineInstr &MI) const override;
472 
473  uint16_t getExecutionDomainCustom(const MachineInstr &MI) const;
474 
475  void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override;
476 
477  bool setExecutionDomainCustom(MachineInstr &MI, unsigned Domain) const;
478 
479  unsigned
480  getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum,
481  const TargetRegisterInfo *TRI) const override;
482  unsigned getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
483  const TargetRegisterInfo *TRI) const override;
484  void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
485  const TargetRegisterInfo *TRI) const override;
486 
487  MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
488  unsigned OpNum,
491  unsigned Size, unsigned Alignment,
492  bool AllowCommute) const;
493 
494  bool isHighLatencyDef(int opc) const override;
495 
496  bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
497  const MachineRegisterInfo *MRI,
498  const MachineInstr &DefMI, unsigned DefIdx,
499  const MachineInstr &UseMI,
500  unsigned UseIdx) const override;
501 
502  bool useMachineCombiner() const override { return true; }
503 
504  bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
505 
506  bool hasReassociableOperands(const MachineInstr &Inst,
507  const MachineBasicBlock *MBB) const override;
508 
509  void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
510  MachineInstr &NewMI1,
511  MachineInstr &NewMI2) const override;
512 
513  /// analyzeCompare - For a comparison instruction, return the source registers
514  /// in SrcReg and SrcReg2 if having two register operands, and the value it
515  /// compares against in CmpValue. Return true if the comparison instruction
516  /// can be analyzed.
517  bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
518  unsigned &SrcReg2, int &CmpMask,
519  int &CmpValue) const override;
520 
521  /// optimizeCompareInstr - Check if there exists an earlier instruction that
522  /// operates on the same source operands and sets flags in the same way as
523  /// Compare; remove Compare if possible.
524  bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
525  unsigned SrcReg2, int CmpMask, int CmpValue,
526  const MachineRegisterInfo *MRI) const override;
527 
528  /// optimizeLoadInstr - Try to remove the load by folding it to a register
529  /// operand at the use. We fold the load instructions if and only if the
530  /// def and use are in the same BB. We only look at one load and see
531  /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
532  /// defined by the load we are trying to fold. DefMI returns the machine
533  /// instruction that defines FoldAsLoadDefReg, and the function returns
534  /// the machine instruction generated due to folding.
535  MachineInstr *optimizeLoadInstr(MachineInstr &MI,
536  const MachineRegisterInfo *MRI,
537  unsigned &FoldAsLoadDefReg,
538  MachineInstr *&DefMI) const override;
539 
540  std::pair<unsigned, unsigned>
541  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
542 
544  getSerializableDirectMachineOperandTargetFlags() const override;
545 
546  virtual outliner::OutlinedFunction getOutliningCandidateInfo(
547  std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override;
548 
549  bool isFunctionSafeToOutlineFrom(MachineFunction &MF,
550  bool OutlineFromLinkOnceODRs) const override;
551 
553  getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const override;
554 
555  void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF,
556  const outliner::OutlinedFunction &OF) const override;
557 
559  insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
561  const outliner::Candidate &C) const override;
562 
563 #define GET_INSTRINFO_HELPER_DECLS
564 #include "X86GenInstrInfo.inc"
565 
566 protected:
567  /// Commutes the operands in the given instruction by changing the operands
568  /// order and/or changing the instruction's opcode and/or the immediate value
569  /// operand.
570  ///
571  /// The arguments 'CommuteOpIdx1' and 'CommuteOpIdx2' specify the operands
572  /// to be commuted.
573  ///
574  /// Do not call this method for a non-commutable instruction or
575  /// non-commutable operands.
576  /// Even though the instruction is commutable, the method may still
577  /// fail to commute the operands, null pointer is returned in such cases.
578  MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
579  unsigned CommuteOpIdx1,
580  unsigned CommuteOpIdx2) const override;
581 
582  /// If the specific machine instruction is a instruction that moves/copies
583  /// value from one register to another register return true along with
584  /// @Source machine operand and @Destination machine operand.
585  bool isCopyInstrImpl(const MachineInstr &MI, const MachineOperand *&Source,
586  const MachineOperand *&Destination) const override;
587 
588 private:
589  /// This is a helper for convertToThreeAddress for 8 and 16-bit instructions.
590  /// We use 32-bit LEA to form 3-address code by promoting to a 32-bit
591  /// super-register and then truncating back down to a 8/16-bit sub-register.
592  MachineInstr *convertToThreeAddressWithLEA(unsigned MIOpc,
594  MachineInstr &MI,
595  LiveVariables *LV) const;
596 
597  /// Handles memory folding for special case instructions, for instance those
598  /// requiring custom manipulation of the address.
599  MachineInstr *foldMemoryOperandCustom(MachineFunction &MF, MachineInstr &MI,
600  unsigned OpNum,
601  ArrayRef<MachineOperand> MOs,
603  unsigned Size, unsigned Align) const;
604 
605  /// isFrameOperand - Return true and the FrameIndex if the specified
606  /// operand and follow operands form a reference to the stack frame.
607  bool isFrameOperand(const MachineInstr &MI, unsigned int Op,
608  int &FrameIndex) const;
609 
610  /// Returns true iff the routine could find two commutable operands in the
611  /// given machine instruction with 3 vector inputs.
612  /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their
613  /// input values can be re-defined in this method only if the input values
614  /// are not pre-defined, which is designated by the special value
615  /// 'CommuteAnyOperandIndex' assigned to it.
616  /// If both of indices are pre-defined and refer to some operands, then the
617  /// method simply returns true if the corresponding operands are commutable
618  /// and returns false otherwise.
619  ///
620  /// For example, calling this method this way:
621  /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
622  /// findThreeSrcCommutedOpIndices(MI, Op1, Op2);
623  /// can be interpreted as a query asking to find an operand that would be
624  /// commutable with the operand#1.
625  ///
626  /// If IsIntrinsic is set, operand 1 will be ignored for commuting.
627  bool findThreeSrcCommutedOpIndices(const MachineInstr &MI,
628  unsigned &SrcOpIdx1,
629  unsigned &SrcOpIdx2,
630  bool IsIntrinsic = false) const;
631 };
632 
633 } // namespace llvm
634 
635 #endif
void setFrameAdjustment(MachineInstr &I, int64_t V) const
Sets the stack pointer adjustment made inside the frame made up by this instruction.
Definition: X86InstrInfo.h:199
unsigned GetCondBranchFromCond(CondCode CC)
uint64_t CallInst * C
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
static bool isScale(const MachineOperand &MO)
Definition: X86InstrInfo.h:142
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "...
Definition: X86BaseInfo.h:235
AddrSegmentReg - The operand # of the segment in the memory operand.
Definition: X86BaseInfo.h:38
This class represents lattice values for constants.
Definition: AllocatorList.h:23
LivenessQueryResult computeRegisterLiveness(const TargetRegisterInfo *TRI, unsigned Reg, const_iterator Before, unsigned Neighborhood=10) const
Return whether (physical) register Reg has been defined and not killed as of just before Before...
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:64
This class is used to group {132, 213, 231} forms of FMA opcodes together.
CondCode getCondFromCMovOpc(unsigned Opc)
Return condition code of a CMov opcode.
unsigned Reg
CondCode getCondFromSETOpc(unsigned Opc)
Return condition code of a SET opcode.
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...
Definition: X86BaseInfo.h:107
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
An individual sequence of instructions to be replaced with a call to an outlined function.
Represents a predicate at the MachineFunction level.
MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates that the reference is actually...
Definition: X86BaseInfo.h:207
Provide an instruction scheduling machine model to CodeGen passes.
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:411
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
static bool isGlobalStubReference(unsigned char TargetFlag)
isGlobalStubReference - Return true if the specified TargetFlag operand is a reference to a stub for ...
Definition: X86InstrInfo.h:112
CondCode getCondFromBranchOpc(unsigned Opc)
unsigned getSwappedVPCMPImm(unsigned Imm)
Get the VPCMP immediate if the opcodes are swapped.
static bool isMem(const MachineInstr &MI, unsigned Op)
Definition: X86InstrInfo.h:160
static bool isGlobalRelativeToPICBase(unsigned char TargetFlag)
isGlobalRelativeToPICBase - Return true if the specified global value reference is relative to a 32-b...
Definition: X86InstrInfo.h:129
MO_GOT - On a symbol operand this indicates that the immediate is the offset to the GOT entry for the...
Definition: X86BaseInfo.h:92
unsigned getSwappedVPCOMImm(unsigned Imm)
Get the VPCOM immediate if the opcodes are swapped.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:965
static bool isLeaMem(const MachineInstr &MI, unsigned Op)
Definition: X86InstrInfo.h:147
MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the reference is actually to the "...
Definition: X86BaseInfo.h:202
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
BasicBlockListType::iterator iterator
MachineInstrBundleIterator< MachineInstr > iterator
std::pair< CondCode, bool > getX86ConditionCode(CmpInst::Predicate Predicate)
Return a pair of condition code for the given predicate and whether the instruction operands should b...
unsigned const MachineRegisterInfo * MRI
InstrType
Represents how an instruction should be mapped by the outliner.
MO_TLVP - On a symbol operand this indicates that the immediate is some TLS offset.
Definition: X86BaseInfo.h:213
MachineInstrBuilder & UseMI
The information necessary to create an outlined function for some class of candidate.
unsigned getVPCMPImmForCond(ISD::CondCode CC)
Get the VPCMP immediate for the given condition.
Register is known to be fully dead.
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:646
void setImm(int64_t immVal)
bool useMachineCombiner() const override
Definition: X86InstrInfo.h:502
unsigned getSETFromCond(CondCode CC, bool HasMemoryOperand=false)
Return a set opcode for the given condition and whether it has a memory operand.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Iterator for intrusive lists based on ilist_node.
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
MachineOperand class - Representation of each machine instruction operand.
CondCode GetOppositeBranchCondition(CondCode CC)
GetOppositeBranchCondition - Return the inverse of the specified cond, e.g.
MachineInstrBuilder MachineInstrBuilder & DefMI
AddrNumOperands - Total number of operands in a memory reference.
Definition: X86BaseInfo.h:41
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:26
int64_t getFrameAdjustment(const MachineInstr &I) const
Returns the stack pointer adjustment that happens inside the frame setup..destroy sequence (e...
Definition: X86InstrInfo.h:190
const X86RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: X86InstrInfo.h:186
Represents one node in the SelectionDAG.
int64_t getImm() const
unsigned getCMovFromCond(CondCode CC, unsigned RegBytes, bool HasMemoryOperand=false)
Return a cmov opcode for the given condition, register size in bytes, and operand type...
bool isSubregFoldable() const override
Check whether the target can fold a load that feeds a subreg operand (or a subreg operand that feeds ...
Definition: X86InstrInfo.h:378
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:63
MO_GOTOFF - On a symbol operand this indicates that the immediate is the offset to the location of th...
Definition: X86BaseInfo.h:99
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
uint32_t Size
Definition: Profile.cpp:46
bool isReg() const
isReg - Tests if this is a MO_Register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const
isSafeToClobberEFLAGS - Return true if it&#39;s safe insert an instruction tha would clobber the EFLAGS c...
Definition: X86InstrInfo.h:454
MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the immediate should get the value of th...
Definition: X86BaseInfo.h:85
IRTranslator LLVM IR MI
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:413
MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the reference is actually to the "__imp...
Definition: X86BaseInfo.h:197