LLVM 19.0.0git
X86InstrInfo.h
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1//===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the X86 implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_X86_X86INSTRINFO_H
14#define LLVM_LIB_TARGET_X86_X86INSTRINFO_H
15
17#include "X86InstrFMA3Info.h"
18#include "X86RegisterInfo.h"
21#include <vector>
22
23#define GET_INSTRINFO_HEADER
24#include "X86GenInstrInfo.inc"
25
26namespace llvm {
27class X86Subtarget;
28
29namespace X86 {
30
32 // For instr that was compressed from EVEX to LEGACY.
34 // For instr that was compressed from EVEX to VEX.
36 // For instr that was compressed from EVEX to EVEX.
38};
39
40/// Return a pair of condition code for the given predicate and whether
41/// the instruction operands should be swaped to match the condition code.
42std::pair<CondCode, bool> getX86ConditionCode(CmpInst::Predicate Predicate);
43
44/// Return a cmov opcode for the given register size in bytes, and operand type.
45unsigned getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand = false,
46 bool HasNDD = false);
47
48/// Return the source operand # for condition code by \p MCID. If the
49/// instruction doesn't have a condition code, return -1.
50int getCondSrcNoFromDesc(const MCInstrDesc &MCID);
51
52/// Return the condition code of the instruction. If the instruction doesn't
53/// have a condition code, return X86::COND_INVALID.
55
56// Turn JCC instruction into condition code.
58
59// Turn SETCC instruction into condition code.
61
62// Turn CMOV instruction into condition code.
64
65// Turn CFCMOV instruction into condition code.
67
68/// GetOppositeBranchCondition - Return the inverse of the specified cond,
69/// e.g. turning COND_E to COND_NE.
71
72/// Get the VPCMP immediate for the given condition.
74
75/// Get the VPCMP immediate if the opcodes are swapped.
76unsigned getSwappedVPCMPImm(unsigned Imm);
77
78/// Get the VPCOM immediate if the opcodes are swapped.
79unsigned getSwappedVPCOMImm(unsigned Imm);
80
81/// Get the VCMP immediate if the opcodes are swapped.
82unsigned getSwappedVCMPImm(unsigned Imm);
83
84/// Get the width of the vector register operand.
86
87/// Check if the instruction is X87 instruction.
89
90/// Return the index of the instruction's first address operand, if it has a
91/// memory reference, or -1 if it has none. Unlike X86II::getMemoryOperandNo(),
92/// this also works for both pseudo instructions (e.g., TCRETURNmi) as well as
93/// real instructions (e.g., JMP64m).
95
96/// Find any constant pool entry associated with a specific instruction operand.
97const Constant *getConstantFromPool(const MachineInstr &MI, unsigned OpNo);
98
99} // namespace X86
100
101/// isGlobalStubReference - Return true if the specified TargetFlag operand is
102/// a reference to a stub for a global, not the global itself.
103inline static bool isGlobalStubReference(unsigned char TargetFlag) {
104 switch (TargetFlag) {
105 case X86II::MO_DLLIMPORT: // dllimport stub.
106 case X86II::MO_GOTPCREL: // rip-relative GOT reference.
107 case X86II::MO_GOTPCREL_NORELAX: // rip-relative GOT reference.
108 case X86II::MO_GOT: // normal GOT reference.
109 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref.
110 case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref.
111 case X86II::MO_COFFSTUB: // COFF .refptr stub.
112 return true;
113 default:
114 return false;
115 }
116}
117
118/// isGlobalRelativeToPICBase - Return true if the specified global value
119/// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this
120/// is true, the addressing mode has the PIC base register added in (e.g. EBX).
121inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) {
122 switch (TargetFlag) {
123 case X86II::MO_GOTOFF: // isPICStyleGOT: local global.
124 case X86II::MO_GOT: // isPICStyleGOT: other global.
125 case X86II::MO_PIC_BASE_OFFSET: // Darwin local global.
126 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global.
127 case X86II::MO_TLVP: // ??? Pretty sure..
128 return true;
129 default:
130 return false;
131 }
132}
133
134inline static bool isScale(const MachineOperand &MO) {
135 return MO.isImm() && (MO.getImm() == 1 || MO.getImm() == 2 ||
136 MO.getImm() == 4 || MO.getImm() == 8);
137}
138
139inline static bool isLeaMem(const MachineInstr &MI, unsigned Op) {
140 if (MI.getOperand(Op).isFI())
141 return true;
142 return Op + X86::AddrSegmentReg <= MI.getNumOperands() &&
143 MI.getOperand(Op + X86::AddrBaseReg).isReg() &&
144 isScale(MI.getOperand(Op + X86::AddrScaleAmt)) &&
145 MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
146 (MI.getOperand(Op + X86::AddrDisp).isImm() ||
147 MI.getOperand(Op + X86::AddrDisp).isGlobal() ||
148 MI.getOperand(Op + X86::AddrDisp).isCPI() ||
149 MI.getOperand(Op + X86::AddrDisp).isJTI());
150}
151
152inline static bool isMem(const MachineInstr &MI, unsigned Op) {
153 if (MI.getOperand(Op).isFI())
154 return true;
155 return Op + X86::AddrNumOperands <= MI.getNumOperands() &&
156 MI.getOperand(Op + X86::AddrSegmentReg).isReg() && isLeaMem(MI, Op);
157}
158
159class X86InstrInfo final : public X86GenInstrInfo {
160 X86Subtarget &Subtarget;
161 const X86RegisterInfo RI;
162
163 virtual void anchor();
164
165 bool analyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
166 MachineBasicBlock *&FBB,
169 bool AllowModify) const;
170
171 bool foldImmediateImpl(MachineInstr &UseMI, MachineInstr *DefMI, Register Reg,
172 int64_t ImmVal, MachineRegisterInfo *MRI,
173 bool MakeChange) const;
174
175public:
176 explicit X86InstrInfo(X86Subtarget &STI);
177
178 /// Given a machine instruction descriptor, returns the register
179 /// class constraint for OpNum, or NULL. Returned register class
180 /// may be different from the definition in the TD file, e.g.
181 /// GR*RegClass (definition in TD file)
182 /// ->
183 /// GR*_NOREX2RegClass (Returned register class)
184 const TargetRegisterClass *
185 getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
186 const TargetRegisterInfo *TRI,
187 const MachineFunction &MF) const override;
188
189 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
190 /// such, whenever a client has an instance of instruction info, it should
191 /// always be able to get register info as well (through this method).
192 ///
193 const X86RegisterInfo &getRegisterInfo() const { return RI; }
194
195 /// Returns the stack pointer adjustment that happens inside the frame
196 /// setup..destroy sequence (e.g. by pushes, or inside the callee).
197 int64_t getFrameAdjustment(const MachineInstr &I) const {
198 assert(isFrameInstr(I));
199 if (isFrameSetup(I))
200 return I.getOperand(2).getImm();
201 return I.getOperand(1).getImm();
202 }
203
204 /// Sets the stack pointer adjustment made inside the frame made up by this
205 /// instruction.
206 void setFrameAdjustment(MachineInstr &I, int64_t V) const {
207 assert(isFrameInstr(I));
208 if (isFrameSetup(I))
209 I.getOperand(2).setImm(V);
210 else
211 I.getOperand(1).setImm(V);
212 }
213
214 /// getSPAdjust - This returns the stack pointer adjustment made by
215 /// this instruction. For x86, we need to handle more complex call
216 /// sequences involving PUSHes.
217 int getSPAdjust(const MachineInstr &MI) const override;
218
219 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
220 /// extension instruction. That is, it's like a copy where it's legal for the
221 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
222 /// true, then it's expected the pre-extension value is available as a subreg
223 /// of the result register. This also returns the sub-register index in
224 /// SubIdx.
225 bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg,
226 Register &DstReg, unsigned &SubIdx) const override;
227
228 /// Returns true if the instruction has no behavior (specified or otherwise)
229 /// that is based on the value of any of its register operands
230 ///
231 /// Instructions are considered data invariant even if they set EFLAGS.
232 ///
233 /// A classical example of something that is inherently not data invariant is
234 /// an indirect jump -- the destination is loaded into icache based on the
235 /// bits set in the jump destination register.
236 ///
237 /// FIXME: This should become part of our instruction tables.
238 static bool isDataInvariant(MachineInstr &MI);
239
240 /// Returns true if the instruction has no behavior (specified or otherwise)
241 /// that is based on the value loaded from memory or the value of any
242 /// non-address register operands.
243 ///
244 /// For example, if the latency of the instruction is dependent on the
245 /// particular bits set in any of the registers *or* any of the bits loaded
246 /// from memory.
247 ///
248 /// Instructions are considered data invariant even if they set EFLAGS.
249 ///
250 /// A classical example of something that is inherently not data invariant is
251 /// an indirect jump -- the destination is loaded into icache based on the
252 /// bits set in the jump destination register.
253 ///
254 /// FIXME: This should become part of our instruction tables.
255 static bool isDataInvariantLoad(MachineInstr &MI);
256
258 int &FrameIndex) const override;
260 int &FrameIndex,
261 unsigned &MemBytes) const override;
262 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
263 /// stack locations as well. This uses a heuristic so it isn't
264 /// reliable for correctness.
266 int &FrameIndex) const override;
267
269 int &FrameIndex) const override;
271 int &FrameIndex,
272 unsigned &MemBytes) const override;
273 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
274 /// stack locations as well. This uses a heuristic so it isn't
275 /// reliable for correctness.
277 int &FrameIndex) const override;
278
279 bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override;
281 Register DestReg, unsigned SubIdx,
282 const MachineInstr &Orig,
283 const TargetRegisterInfo &TRI) const override;
284
285 /// Given an operand within a MachineInstr, insert preceding code to put it
286 /// into the right format for a particular kind of LEA instruction. This may
287 /// involve using an appropriate super-register instead (with an implicit use
288 /// of the original) or creating a new virtual register and inserting COPY
289 /// instructions to get the data into the right class.
290 ///
291 /// Reference parameters are set to indicate how caller should add this
292 /// operand to the LEA instruction.
294 unsigned LEAOpcode, bool AllowSP, Register &NewSrc,
295 bool &isKill, MachineOperand &ImplicitOp,
296 LiveVariables *LV, LiveIntervals *LIS) const;
297
298 /// convertToThreeAddress - This method must be implemented by targets that
299 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
300 /// may be able to convert a two-address instruction into a true
301 /// three-address instruction on demand. This allows the X86 target (for
302 /// example) to convert ADD and SHL instructions into LEA instructions if they
303 /// would require register copies due to two-addressness.
304 ///
305 /// This method returns a null pointer if the transformation cannot be
306 /// performed, otherwise it returns the new instruction.
307 ///
309 LiveIntervals *LIS) const override;
310
311 /// Returns true iff the routine could find two commutable operands in the
312 /// given machine instruction.
313 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their
314 /// input values can be re-defined in this method only if the input values
315 /// are not pre-defined, which is designated by the special value
316 /// 'CommuteAnyOperandIndex' assigned to it.
317 /// If both of indices are pre-defined and refer to some operands, then the
318 /// method simply returns true if the corresponding operands are commutable
319 /// and returns false otherwise.
320 ///
321 /// For example, calling this method this way:
322 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
323 /// findCommutedOpIndices(MI, Op1, Op2);
324 /// can be interpreted as a query asking to find an operand that would be
325 /// commutable with the operand#1.
326 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
327 unsigned &SrcOpIdx2) const override;
328
329 /// Returns true if we have preference on the operands order in MI, the
330 /// commute decision is returned in Commute.
331 bool hasCommutePreference(MachineInstr &MI, bool &Commute) const override;
332
333 /// Returns an adjusted FMA opcode that must be used in FMA instruction that
334 /// performs the same computations as the given \p MI but which has the
335 /// operands \p SrcOpIdx1 and \p SrcOpIdx2 commuted.
336 /// It may return 0 if it is unsafe to commute the operands.
337 /// Note that a machine instruction (instead of its opcode) is passed as the
338 /// first parameter to make it possible to analyze the instruction's uses and
339 /// commute the first operand of FMA even when it seems unsafe when you look
340 /// at the opcode. For example, it is Ok to commute the first operand of
341 /// VFMADD*SD_Int, if ONLY the lowest 64-bit element of the result is used.
342 ///
343 /// The returned FMA opcode may differ from the opcode in the given \p MI.
344 /// For example, commuting the operands #1 and #3 in the following FMA
345 /// FMA213 #1, #2, #3
346 /// results into instruction with adjusted opcode:
347 /// FMA231 #3, #2, #1
348 unsigned
349 getFMA3OpcodeToCommuteOperands(const MachineInstr &MI, unsigned SrcOpIdx1,
350 unsigned SrcOpIdx2,
351 const X86InstrFMA3Group &FMA3Group) const;
352
353 // Branch analysis.
354 bool isUnconditionalTailCall(const MachineInstr &MI) const override;
356 const MachineInstr &TailCall) const override;
359 const MachineInstr &TailCall) const override;
360
362 MachineBasicBlock *&FBB,
364 bool AllowModify) const override;
365
366 int getJumpTableIndex(const MachineInstr &MI) const override;
367
368 std::optional<ExtAddrMode>
370 const TargetRegisterInfo *TRI) const override;
371
373 int64_t &ImmVal) const override;
374
376 const Register NullValueReg,
377 const TargetRegisterInfo *TRI) const override;
378
380 const MachineInstr &LdSt,
382 bool &OffsetIsScalable, LocationSize &Width,
383 const TargetRegisterInfo *TRI) const override;
386 bool AllowModify = false) const override;
387
389 int *BytesRemoved = nullptr) const override;
392 const DebugLoc &DL,
393 int *BytesAdded = nullptr) const override;
395 Register, Register, Register, int &, int &,
396 int &) const override;
398 const DebugLoc &DL, Register DstReg,
400 Register FalseReg) const override;
402 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
403 bool KillSrc) const override;
406 bool isKill, int FrameIndex,
407 const TargetRegisterClass *RC,
408 const TargetRegisterInfo *TRI,
409 Register VReg) const override;
410
413 int FrameIndex, const TargetRegisterClass *RC,
414 const TargetRegisterInfo *TRI,
415 Register VReg) const override;
416
418 unsigned Opc, Register Reg, int FrameIdx,
419 bool isKill = false) const;
420
421 bool expandPostRAPseudo(MachineInstr &MI) const override;
422
423 /// Check whether the target can fold a load that feeds a subreg operand
424 /// (or a subreg operand that feeds a store).
425 bool isSubregFoldable() const override { return true; }
426
427 /// Fold a load or store of the specified stack slot into the specified
428 /// machine instruction for the specified operand(s). If folding happens, it
429 /// is likely that the referenced instruction has been changed.
430 ///
431 /// \returns true on success.
435 MachineBasicBlock::iterator InsertPt, int FrameIndex,
436 LiveIntervals *LIS = nullptr,
437 VirtRegMap *VRM = nullptr) const override;
438
439 /// Same as the previous version except it allows folding of any load and
440 /// store from / to any address, not just from a specific stack slot.
444 LiveIntervals *LIS = nullptr) const override;
445
446 bool
448 bool UnfoldLoad, bool UnfoldStore,
449 SmallVectorImpl<MachineInstr *> &NewMIs) const override;
450
452 SmallVectorImpl<SDNode *> &NewNodes) const override;
453
454 unsigned
455 getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore,
456 unsigned *LoadRegIndex = nullptr) const override;
457
458 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
459 int64_t &Offset2) const override;
460
461 /// Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to
462 /// make it capable of identifying ENDBR intructions and prevent it from being
463 /// re-scheduled.
465 const MachineBasicBlock *MBB,
466 const MachineFunction &MF) const override;
467
468 /// This is a used by the pre-regalloc scheduler to determine (in conjunction
469 /// with areLoadsFromSameBasePtr) if two loads should be scheduled togther. On
470 /// some targets if two loads are loading from addresses in the same cache
471 /// line, it's better if they are scheduled together. This function takes two
472 /// integers that represent the load offsets from the common base address. It
473 /// returns true if it decides it's desirable to schedule the two loads
474 /// together. "NumLoads" is the number of loads that have already been
475 /// scheduled after Load1.
476 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1,
477 int64_t Offset2,
478 unsigned NumLoads) const override;
479
481 MachineBasicBlock::iterator MI) const override;
482
483 MCInst getNop() const override;
484
485 bool
487
488 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
489
490 /// True if MI has a condition code def, e.g. EFLAGS, that is
491 /// not marked dead.
493
494 /// getGlobalBaseReg - Return a virtual register initialized with the
495 /// the global base register value. Output instructions required to
496 /// initialize the register in the function entry block, if necessary.
497 ///
498 unsigned getGlobalBaseReg(MachineFunction *MF) const;
499
500 std::pair<uint16_t, uint16_t>
501 getExecutionDomain(const MachineInstr &MI) const override;
502
504
505 void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override;
506
507 bool setExecutionDomainCustom(MachineInstr &MI, unsigned Domain) const;
508
509 unsigned
510 getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum,
511 const TargetRegisterInfo *TRI) const override;
512 unsigned getUndefRegClearance(const MachineInstr &MI, unsigned OpNum,
513 const TargetRegisterInfo *TRI) const override;
514 void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
515 const TargetRegisterInfo *TRI) const override;
516
518 unsigned OpNum,
521 unsigned Size, Align Alignment,
522 bool AllowCommute) const;
523
524 bool isHighLatencyDef(int opc) const override;
525
526 bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
528 const MachineInstr &DefMI, unsigned DefIdx,
529 const MachineInstr &UseMI,
530 unsigned UseIdx) const override;
531
532 bool useMachineCombiner() const override { return true; }
533
535 bool Invert) const override;
536
537 bool hasReassociableOperands(const MachineInstr &Inst,
538 const MachineBasicBlock *MBB) const override;
539
540 void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
541 MachineInstr &NewMI1,
542 MachineInstr &NewMI2) const override;
543
544 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
545 Register &SrcReg2, int64_t &CmpMask,
546 int64_t &CmpValue) const override;
547
548 /// Check if there exists an earlier instruction that operates on the same
549 /// source operands and sets eflags in the same way as CMP and remove CMP if
550 /// possible.
551 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
552 Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
553 const MachineRegisterInfo *MRI) const override;
554
557 Register &FoldAsLoadDefReg,
558 MachineInstr *&DefMI) const override;
559
561 MachineRegisterInfo *MRI) const override;
562
563 std::pair<unsigned, unsigned>
564 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
565
568
569 std::optional<outliner::OutlinedFunction> getOutliningCandidateInfo(
570 std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override;
571
573 bool OutlineFromLinkOnceODRs) const override;
574
576 getOutliningTypeImpl(MachineBasicBlock::iterator &MIT, unsigned Flags) const override;
577
579 const outliner::OutlinedFunction &OF) const override;
580
584 outliner::Candidate &C) const override;
585
588 bool AllowSideEffects = true) const override;
589
591 StringRef &ErrInfo) const override;
592#define GET_INSTRINFO_HELPER_DECLS
593#include "X86GenInstrInfo.inc"
594
595 static bool hasLockPrefix(const MachineInstr &MI) {
596 return MI.getDesc().TSFlags & X86II::LOCK;
597 }
598
599 std::optional<ParamLoadedValue>
600 describeLoadedValue(const MachineInstr &MI, Register Reg) const override;
601
602protected:
604 unsigned CommuteOpIdx1,
605 unsigned CommuteOpIdx2) const override;
606
607 std::optional<DestSourcePair>
608 isCopyInstrImpl(const MachineInstr &MI) const override;
609
610 bool
613 bool DoRegPressureReduce) const override;
614
615 /// When getMachineCombinerPatterns() finds potential patterns,
616 /// this function generates the instructions that could replace the
617 /// original code sequence.
622 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
623
624 /// When calculate the latency of the root instruction, accumulate the
625 /// latency of the sequence to the root latency.
626 /// \param Root - Instruction that could be combined with one of its operands
627 /// For X86 instruction (vpmaddwd + vpmaddwd) -> vpdpwssd, the vpmaddwd
628 /// is not in the critical path, so the root latency only include vpmaddwd.
630 return false;
631 }
632
634 int FI) const override;
635
636private:
637 /// This is a helper for convertToThreeAddress for 8 and 16-bit instructions.
638 /// We use 32-bit LEA to form 3-address code by promoting to a 32-bit
639 /// super-register and then truncating back down to a 8/16-bit sub-register.
640 MachineInstr *convertToThreeAddressWithLEA(unsigned MIOpc, MachineInstr &MI,
641 LiveVariables *LV,
642 LiveIntervals *LIS,
643 bool Is8BitOp) const;
644
645 /// Handles memory folding for special case instructions, for instance those
646 /// requiring custom manipulation of the address.
647 MachineInstr *foldMemoryOperandCustom(MachineFunction &MF, MachineInstr &MI,
648 unsigned OpNum,
651 unsigned Size, Align Alignment) const;
652
653 MachineInstr *foldMemoryBroadcast(MachineFunction &MF, MachineInstr &MI,
654 unsigned OpNum,
657 unsigned BitsSize, bool AllowCommute) const;
658
659 /// isFrameOperand - Return true and the FrameIndex if the specified
660 /// operand and follow operands form a reference to the stack frame.
661 bool isFrameOperand(const MachineInstr &MI, unsigned int Op,
662 int &FrameIndex) const;
663
664 /// Returns true iff the routine could find two commutable operands in the
665 /// given machine instruction with 3 vector inputs.
666 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their
667 /// input values can be re-defined in this method only if the input values
668 /// are not pre-defined, which is designated by the special value
669 /// 'CommuteAnyOperandIndex' assigned to it.
670 /// If both of indices are pre-defined and refer to some operands, then the
671 /// method simply returns true if the corresponding operands are commutable
672 /// and returns false otherwise.
673 ///
674 /// For example, calling this method this way:
675 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
676 /// findThreeSrcCommutedOpIndices(MI, Op1, Op2);
677 /// can be interpreted as a query asking to find an operand that would be
678 /// commutable with the operand#1.
679 ///
680 /// If IsIntrinsic is set, operand 1 will be ignored for commuting.
681 bool findThreeSrcCommutedOpIndices(const MachineInstr &MI,
682 unsigned &SrcOpIdx1,
683 unsigned &SrcOpIdx2,
684 bool IsIntrinsic = false) const;
685
686 /// Returns true when instruction \p FlagI produces the same flags as \p OI.
687 /// The caller should pass in the results of calling analyzeCompare on \p OI:
688 /// \p SrcReg, \p SrcReg2, \p ImmMask, \p ImmValue.
689 /// If the flags match \p OI as if it had the input operands swapped then the
690 /// function succeeds and sets \p IsSwapped to true.
691 ///
692 /// Examples of OI, FlagI pairs returning true:
693 /// CMP %1, 42 and CMP %1, 42
694 /// CMP %1, %2 and %3 = SUB %1, %2
695 /// TEST %1, %1 and %2 = SUB %1, 0
696 /// CMP %1, %2 and %3 = SUB %2, %1 ; IsSwapped=true
697 bool isRedundantFlagInstr(const MachineInstr &FlagI, Register SrcReg,
698 Register SrcReg2, int64_t ImmMask, int64_t ImmValue,
699 const MachineInstr &OI, bool *IsSwapped,
700 int64_t *ImmDelta) const;
701
702 /// Commute operands of \p MI for memory fold.
703 ///
704 /// \param Idx1 the index of operand to be commuted.
705 ///
706 /// \returns the index of operand that is commuted with \p Idx1. If the method
707 /// fails to commute the operands, it will return \p Idx1.
708 unsigned commuteOperandsForFold(MachineInstr &MI, unsigned Idx1) const;
709};
710} // namespace llvm
711
712#endif
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
uint64_t Size
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
unsigned Reg
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:965
This is an important base class in LLVM.
Definition: Constant.h:41
This class represents an Operation in the Expression.
A debug info location.
Definition: DebugLoc.h:33
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:85
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Representation of each machine instruction.
Definition: MachineInstr.h:69
MachineOperand class - Representation of each machine instruction operand.
int64_t getImm() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Represents one node in the SelectionDAG.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:225
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Provide an instruction scheduling machine model to CodeGen passes.
bool accumulateInstrSeqToRootLatency(MachineInstr &Root) const override
When calculate the latency of the root instruction, accumulate the latency of the sequence to the roo...
Definition: X86InstrInfo.h:629
void getFrameIndexOperands(SmallVectorImpl< MachineOperand > &Ops, int FI) const override
bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override
Check if there exists an earlier instruction that operates on the same source operands and sets eflag...
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying...
MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const override
const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const override
Given a machine instruction descriptor, returns the register class constraint for OpNum,...
void replaceBranchWithTailCall(MachineBasicBlock &MBB, SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const override
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const override
unsigned getGlobalBaseReg(MachineFunction *MF) const
getGlobalBaseReg - Return a virtual register initialized with the the global base register value.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const override
bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
Returns true iff the routine could find two commutable operands in the given machine instruction.
bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
static bool isDataInvariantLoad(MachineInstr &MI)
Returns true if the instruction has no behavior (specified or otherwise) that is based on the value l...
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned CommuteOpIdx1, unsigned CommuteOpIdx2) const override
bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
const X86RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: X86InstrInfo.h:193
bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override
bool hasCommutePreference(MachineInstr &MI, bool &Commute) const override
Returns true if we have preference on the operands order in MI, the commute decision is returned in C...
bool hasLiveCondCodeDef(MachineInstr &MI) const
True if MI has a condition code def, e.g.
std::optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI, Register Reg) const override
bool canMakeTailCallConditional(SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
bool getMemOperandsWithOffsetWidth(const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width, const TargetRegisterInfo *TRI) const override
std::optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override
MachineInstr * convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override
convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_AD...
static bool hasLockPrefix(const MachineInstr &MI)
Definition: X86InstrInfo.h:595
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
bool expandPostRAPseudo(MachineInstr &MI) const override
bool isAssociativeAndCommutative(const MachineInstr &Inst, bool Invert) const override
MCInst getNop() const override
Return the noop instruction to use for a noop.
bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override
This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePt...
bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const override
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
Fold a load or store of the specified stack slot into the specified machine instruction for the speci...
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns, bool DoRegPressureReduce) const override
bool getConstValDefinedInReg(const MachineInstr &MI, const Register Reg, int64_t &ImmVal) const override
std::optional< ExtAddrMode > getAddrModeFromMemoryOp(const MachineInstr &MemI, const TargetRegisterInfo *TRI) const override
Register isStoreToStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override
isStoreToStackSlotPostFE - Check for post-frame ptr elimination stack locations as well.
bool isUnconditionalTailCall(const MachineInstr &MI) const override
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Register isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override
isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well.
void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override
bool useMachineCombiner() const override
Definition: X86InstrInfo.h:532
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
bool setExecutionDomainCustom(MachineInstr &MI, unsigned Domain) const
int getSPAdjust(const MachineInstr &MI) const override
getSPAdjust - This returns the stack pointer adjustment made by this instruction.
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
outliner::InstrType getOutliningTypeImpl(MachineBasicBlock::iterator &MIT, unsigned Flags) const override
int getJumpTableIndex(const MachineInstr &MI) const override
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const override
This is an architecture-specific helper function of reassociateOps.
void setFrameAdjustment(MachineInstr &I, int64_t V) const
Sets the stack pointer adjustment made inside the frame made up by this instruction.
Definition: X86InstrInfo.h:206
std::pair< uint16_t, uint16_t > getExecutionDomain(const MachineInstr &MI) const override
bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const override
isCoalescableExtInstr - Return true if the instruction is a "coalescable" extension instruction.
void loadStoreTileReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Opc, Register Reg, int FrameIdx, bool isKill=false) const
bool classifyLEAReg(MachineInstr &MI, const MachineOperand &Src, unsigned LEAOpcode, bool AllowSP, Register &NewSrc, bool &isKill, MachineOperand &ImplicitOp, LiveVariables *LV, LiveIntervals *LIS) const
Given an operand within a MachineInstr, insert preceding code to put it into the right format for a p...
bool hasReassociableOperands(const MachineInstr &Inst, const MachineBasicBlock *MBB) const override
bool analyzeBranchPredicate(MachineBasicBlock &MBB, TargetInstrInfo::MachineBranchPredicate &MBP, bool AllowModify=false) const override
static bool isDataInvariant(MachineInstr &MI)
Returns true if the instruction has no behavior (specified or otherwise) that is based on the value o...
unsigned getUndefRegClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override
Inform the BreakFalseDeps pass how many idle instructions we would like before certain undef register...
void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override
void buildClearRegister(Register Reg, MachineBasicBlock &MBB, MachineBasicBlock::iterator Iter, DebugLoc &DL, bool AllowSideEffects=true) const override
Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
int64_t getFrameAdjustment(const MachineInstr &I) const
Returns the stack pointer adjustment that happens inside the frame setup..destroy sequence (e....
Definition: X86InstrInfo.h:197
bool hasHighOperandLatency(const TargetSchedModel &SchedModel, const MachineRegisterInfo *MRI, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override
bool isSubregFoldable() const override
Check whether the target can fold a load that feeds a subreg operand (or a subreg operand that feeds ...
Definition: X86InstrInfo.h:425
uint16_t getExecutionDomainCustom(const MachineInstr &MI) const
bool isHighLatencyDef(int opc) const override
void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override
bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override
foldImmediate - 'Reg' is known to be defined by a move immediate instruction, try to fold the immedia...
void genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
When getMachineCombinerPatterns() finds potential patterns, this function generates the instructions ...
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
unsigned getFMA3OpcodeToCommuteOperands(const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2, const X86InstrFMA3Group &FMA3Group) const
Returns an adjusted FMA opcode that must be used in FMA instruction that performs the same computatio...
std::optional< outliner::OutlinedFunction > getOutliningCandidateInfo(std::vector< outliner::Candidate > &RepeatedSequenceLocs) const override
bool preservesZeroValueInReg(const MachineInstr *MI, const Register NullValueReg, const TargetRegisterInfo *TRI) const override
unsigned getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override
Inform the BreakFalseDeps pass how many idle instructions we would like before a partial register upd...
MachineInstr * optimizeLoadInstr(MachineInstr &MI, const MachineRegisterInfo *MRI, Register &FoldAsLoadDefReg, MachineInstr *&DefMI) const override
Try to remove the load by folding it to a register operand at the use.
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1523
@ MO_GOTPCREL_NORELAX
MO_GOTPCREL_NORELAX - Same as MO_GOTPCREL except that R_X86_64_GOTPCREL relocations are guaranteed to...
Definition: X86BaseInfo.h:405
@ MO_GOTOFF
MO_GOTOFF - On a symbol operand this indicates that the immediate is the offset to the location of th...
Definition: X86BaseInfo.h:395
@ MO_DARWIN_NONLAZY_PIC_BASE
MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates that the reference is actually...
Definition: X86BaseInfo.h:482
@ MO_COFFSTUB
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "....
Definition: X86BaseInfo.h:502
@ MO_DARWIN_NONLAZY
MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the reference is actually to the "...
Definition: X86BaseInfo.h:478
@ MO_GOT
MO_GOT - On a symbol operand this indicates that the immediate is the offset to the GOT entry for the...
Definition: X86BaseInfo.h:390
@ MO_TLVP
MO_TLVP - On a symbol operand this indicates that the immediate is some TLS offset.
Definition: X86BaseInfo.h:486
@ MO_DLLIMPORT
MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the reference is actually to the "__imp...
Definition: X86BaseInfo.h:474
@ MO_PIC_BASE_OFFSET
MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the immediate should get the value of th...
Definition: X86BaseInfo.h:385
@ MO_GOTPCREL
MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...
Definition: X86BaseInfo.h:401
CondCode getCondFromBranch(const MachineInstr &MI)
CondCode getCondFromCFCMov(const MachineInstr &MI)
@ AddrScaleAmt
Definition: X86BaseInfo.h:30
@ AddrSegmentReg
Definition: X86BaseInfo.h:34
@ AddrIndexReg
Definition: X86BaseInfo.h:31
@ AddrNumOperands
Definition: X86BaseInfo.h:36
CondCode getCondFromMI(const MachineInstr &MI)
Return the condition code of the instruction.
int getFirstAddrOperandIdx(const MachineInstr &MI)
Return the index of the instruction's first address operand, if it has a memory reference,...
unsigned getSwappedVCMPImm(unsigned Imm)
Get the VCMP immediate if the opcodes are swapped.
CondCode GetOppositeBranchCondition(CondCode CC)
GetOppositeBranchCondition - Return the inverse of the specified cond, e.g.
unsigned getSwappedVPCOMImm(unsigned Imm)
Get the VPCOM immediate if the opcodes are swapped.
bool isX87Instruction(MachineInstr &MI)
Check if the instruction is X87 instruction.
unsigned getVPCMPImmForCond(ISD::CondCode CC)
Get the VPCMP immediate for the given condition.
std::pair< CondCode, bool > getX86ConditionCode(CmpInst::Predicate Predicate)
Return a pair of condition code for the given predicate and whether the instruction operands should b...
CondCode getCondFromSETCC(const MachineInstr &MI)
unsigned getSwappedVPCMPImm(unsigned Imm)
Get the VPCMP immediate if the opcodes are swapped.
int getCondSrcNoFromDesc(const MCInstrDesc &MCID)
Return the source operand # for condition code by MCID.
const Constant * getConstantFromPool(const MachineInstr &MI, unsigned OpNo)
Find any constant pool entry associated with a specific instruction operand.
@ AC_EVEX_2_EVEX
Definition: X86InstrInfo.h:37
@ AC_EVEX_2_LEGACY
Definition: X86InstrInfo.h:33
unsigned getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand=false, bool HasNDD=false)
Return a cmov opcode for the given register size in bytes, and operand type.
unsigned getVectorRegisterWidth(const MCOperandInfo &Info)
Get the width of the vector register operand.
CondCode getCondFromCMov(const MachineInstr &MI)
InstrType
Represents how an instruction should be mapped by the outliner.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
static bool isGlobalStubReference(unsigned char TargetFlag)
isGlobalStubReference - Return true if the specified TargetFlag operand is a reference to a stub for ...
Definition: X86InstrInfo.h:103
@ Offset
Definition: DWP.cpp:456
static bool isGlobalRelativeToPICBase(unsigned char TargetFlag)
isGlobalRelativeToPICBase - Return true if the specified global value reference is relative to a 32-b...
Definition: X86InstrInfo.h:121
static bool isMem(const MachineInstr &MI, unsigned Op)
Definition: X86InstrInfo.h:152
MachineCombinerPattern
These are instruction patterns matched by the machine combiner pass.
static bool isScale(const MachineOperand &MO)
Definition: X86InstrInfo.h:134
static bool isLeaMem(const MachineInstr &MI, unsigned Op)
Definition: X86InstrInfo.h:139
#define N
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Represents a predicate at the MachineFunction level.
This class is used to group {132, 213, 231} forms of FMA opcodes together.
An individual sequence of instructions to be replaced with a call to an outlined function.
The information necessary to create an outlined function for some class of candidate.