LLVM  6.0.0svn
Macros | Functions
X86InstructionSelector.cpp File Reference

This file implements the targeting of the InstructionSelector class for X86. More...

#include "MCTargetDesc/X86BaseInfo.h"
#include "X86InstrBuilder.h"
#include "X86InstrInfo.h"
#include "X86RegisterBankInfo.h"
#include "X86RegisterInfo.h"
#include "X86Subtarget.h"
#include "X86TargetMachine.h"
#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
#include "llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h"
#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
#include "llvm/CodeGen/GlobalISel/Utils.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/InstrTypes.h"
#include "llvm/Support/AtomicOrdering.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/LowLevelTypeImpl.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetOpcodes.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include <cassert>
#include <cstdint>
#include <tuple>
#include "X86GenGlobalISel.inc"
Include dependency graph for X86InstructionSelector.cpp:

Go to the source code of this file.

Macros

#define DEBUG_TYPE   "X86-isel"
 
#define GET_GLOBALISEL_PREDICATE_BITSET
 
#define GET_GLOBALISEL_PREDICATES_DECL
 
#define GET_GLOBALISEL_TEMPORARIES_DECL
 
#define GET_GLOBALISEL_IMPL
 
#define GET_GLOBALISEL_PREDICATES_INIT
 
#define GET_GLOBALISEL_TEMPORARIES_INIT
 

Functions

static const TargetRegisterClassgetRegClassFromGRPhysReg (unsigned Reg)
 
static void X86SelectAddress (const MachineInstr &I, const MachineRegisterInfo &MRI, X86AddressMode &AM)
 
static unsigned getLeaOP (LLT Ty, const X86Subtarget &STI)
 

Detailed Description

This file implements the targeting of the InstructionSelector class for X86.

Todo:
This should be generated by TableGen.

Definition in file X86InstructionSelector.cpp.

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "X86-isel"

Definition at line 15 of file X86InstructionSelector.cpp.

◆ GET_GLOBALISEL_IMPL

#define GET_GLOBALISEL_IMPL

Definition at line 136 of file X86InstructionSelector.cpp.

◆ GET_GLOBALISEL_PREDICATE_BITSET

#define GET_GLOBALISEL_PREDICATE_BITSET

Definition at line 55 of file X86InstructionSelector.cpp.

◆ GET_GLOBALISEL_PREDICATES_DECL

#define GET_GLOBALISEL_PREDICATES_DECL

Definition at line 125 of file X86InstructionSelector.cpp.

◆ GET_GLOBALISEL_PREDICATES_INIT

#define GET_GLOBALISEL_PREDICATES_INIT

◆ GET_GLOBALISEL_TEMPORARIES_DECL

#define GET_GLOBALISEL_TEMPORARIES_DECL

Definition at line 129 of file X86InstructionSelector.cpp.

◆ GET_GLOBALISEL_TEMPORARIES_INIT

#define GET_GLOBALISEL_TEMPORARIES_INIT

Function Documentation

◆ getLeaOP()

static unsigned getLeaOP ( LLT  Ty,
const X86Subtarget STI 
)
static

Definition at line 509 of file X86InstructionSelector.cpp.

References llvm::addConstantPoolReference(), llvm::addDirectMem(), llvm::addFullAddress(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::cflaa::addOffset(), llvm::MachineInstr::addOperand(), llvm::MachineInstrBuilder::addReg(), llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align, assert(), llvm::X86AddressMode::Base, llvm::BuildMI(), llvm::MachineOperand::ChangeToImmediate(), llvm::MachineRegisterInfo::createGenericVirtualRegister(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::dbgs(), DEBUG, llvm::tgtok::Def, llvm::RegState::DefineNoRead, llvm::MachineInstr::eraseFromParent(), llvm::MachineOperand::getCImm(), llvm::MachineFunction::getConstantPool(), llvm::MachineConstantPool::getConstantPoolIndex(), llvm::getConstantVRegVal(), llvm::MachineFunction::getDataLayout(), llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getFPImm(), llvm::MachineOperand::getGlobal(), llvm::RegisterBank::getID(), llvm::MachineOperand::getImm(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::DataLayout::getPointerSize(), llvm::MachineOperand::getPredicate(), llvm::MachineOperand::getReg(), getRegClass(), llvm::MachineRegisterInfo::getRegClassOrNull(), llvm::X86::getSETFromCond(), llvm::LLT::getSizeInBits(), llvm::getSizeInBits(), llvm::MachineRegisterInfo::getType(), llvm::MachineRegisterInfo::getVRegDef(), llvm::X86::getX86ConditionCode(), llvm::ConstantInt::getZExtValue(), llvm::X86AddressMode::GV, llvm::X86AddressMode::GVOpFlags, I, llvm::X86AddressMode::IndexReg, llvm::MachineOperand::isCImm(), llvm::isGlobalRelativeToPICBase(), llvm::isGlobalStubReference(), llvm::MachineOperand::isImm(), llvm::MachineInstr::isImplicitDef(), llvm::isInt< 32 >(), llvm::X86Subtarget::isTarget64BitILP32(), llvm::LLT::isVector(), llvm::CodeModel::Large, llvm_unreachable, llvm::X86II::MO_GOTOFF, llvm::X86II::MO_PIC_BASE_OFFSET, MRI, llvm::X86AddressMode::Reg, llvm::MachineInstr::RemoveOperand(), selectMergeValues(), selectUnmergeValues(), llvm::MachineInstr::setDesc(), llvm::MachineOperand::setImm(), llvm::MachineRegisterInfo::setRegBank(), llvm::MachineOperand::setSubReg(), llvm::CodeModel::Small, std::swap(), TII, and llvm::SystemZISD::TM.

◆ getRegClassFromGRPhysReg()

static const TargetRegisterClass* getRegClassFromGRPhysReg ( unsigned  Reg)
static

◆ X86SelectAddress()

static void X86SelectAddress ( const MachineInstr I,
const MachineRegisterInfo MRI,
X86AddressMode AM 
)
static