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X86IntelInstPrinter.cpp
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1 //===-- X86IntelInstPrinter.cpp - Intel assembly instruction printing -----===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file includes code for rendering MCInst instances as Intel-style
11 // assembly.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "X86IntelInstPrinter.h"
17 #include "X86InstComments.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrDesc.h"
21 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/Support/Casting.h"
25 #include <cassert>
26 #include <cstdint>
27 
28 using namespace llvm;
29 
30 #define DEBUG_TYPE "asm-printer"
31 
32 #include "X86GenAsmWriter1.inc"
33 
34 void X86IntelInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
35  OS << getRegisterName(RegNo);
36 }
37 
39  StringRef Annot,
40  const MCSubtargetInfo &STI) {
41  const MCInstrDesc &Desc = MII.get(MI->getOpcode());
42  uint64_t TSFlags = Desc.TSFlags;
43  unsigned Flags = MI->getFlags();
44 
45  if ((TSFlags & X86II::LOCK) || (Flags & X86::IP_HAS_LOCK))
46  OS << "\tlock\t";
47 
48  if (Flags & X86::IP_HAS_REPEAT_NE)
49  OS << "\trepne\t";
50  else if (Flags & X86::IP_HAS_REPEAT)
51  OS << "\trep\t";
52 
53  if ((TSFlags & X86II::NOTRACK) || (Flags & X86::IP_HAS_NOTRACK))
54  OS << "\tnotrack\t";
55 
56  // In 16-bit mode, print data16 as data32.
57  if (MI->getOpcode() == X86::DATA16_PREFIX &&
58  STI.getFeatureBits()[X86::Mode16Bit]) {
59  OS << "\tdata32";
60  } else
61  printInstruction(MI, OS);
62 
63  // Next always print the annotation.
64  printAnnotation(OS, Annot);
65 
66  // If verbose assembly is enabled, we can print some informative comments.
67  if (CommentStream)
69 }
70 
72  raw_ostream &O) {
73  int64_t Imm = MI->getOperand(Op).getImm();
74  switch (Imm) {
75  default: llvm_unreachable("Invalid avxcc argument!");
76  case 0: O << "eq"; break;
77  case 1: O << "lt"; break;
78  case 2: O << "le"; break;
79  case 3: O << "unord"; break;
80  case 4: O << "neq"; break;
81  case 5: O << "nlt"; break;
82  case 6: O << "nle"; break;
83  case 7: O << "ord"; break;
84  case 8: O << "eq_uq"; break;
85  case 9: O << "nge"; break;
86  case 0xa: O << "ngt"; break;
87  case 0xb: O << "false"; break;
88  case 0xc: O << "neq_oq"; break;
89  case 0xd: O << "ge"; break;
90  case 0xe: O << "gt"; break;
91  case 0xf: O << "true"; break;
92  case 0x10: O << "eq_os"; break;
93  case 0x11: O << "lt_oq"; break;
94  case 0x12: O << "le_oq"; break;
95  case 0x13: O << "unord_s"; break;
96  case 0x14: O << "neq_us"; break;
97  case 0x15: O << "nlt_uq"; break;
98  case 0x16: O << "nle_uq"; break;
99  case 0x17: O << "ord_s"; break;
100  case 0x18: O << "eq_us"; break;
101  case 0x19: O << "nge_uq"; break;
102  case 0x1a: O << "ngt_uq"; break;
103  case 0x1b: O << "false_os"; break;
104  case 0x1c: O << "neq_os"; break;
105  case 0x1d: O << "ge_oq"; break;
106  case 0x1e: O << "gt_oq"; break;
107  case 0x1f: O << "true_us"; break;
108  }
109 }
110 
112  raw_ostream &O) {
113  int64_t Imm = MI->getOperand(Op).getImm();
114  switch (Imm) {
115  default: llvm_unreachable("Invalid xopcc argument!");
116  case 0: O << "lt"; break;
117  case 1: O << "le"; break;
118  case 2: O << "gt"; break;
119  case 3: O << "ge"; break;
120  case 4: O << "eq"; break;
121  case 5: O << "neq"; break;
122  case 6: O << "false"; break;
123  case 7: O << "true"; break;
124  }
125 }
126 
128  raw_ostream &O) {
129  int64_t Imm = MI->getOperand(Op).getImm() & 0x3;
130  switch (Imm) {
131  case 0: O << "{rn-sae}"; break;
132  case 1: O << "{rd-sae}"; break;
133  case 2: O << "{ru-sae}"; break;
134  case 3: O << "{rz-sae}"; break;
135  }
136 }
137 
138 /// printPCRelImm - This is used to print an immediate value that ends up
139 /// being encoded as a pc-relative value.
140 void X86IntelInstPrinter::printPCRelImm(const MCInst *MI, unsigned OpNo,
141  raw_ostream &O) {
142  const MCOperand &Op = MI->getOperand(OpNo);
143  if (Op.isImm())
144  O << formatImm(Op.getImm());
145  else {
146  assert(Op.isExpr() && "unknown pcrel immediate operand");
147  // If a symbolic branch target was added as a constant expression then print
148  // that address in hex.
149  const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
150  int64_t Address;
151  if (BranchTarget && BranchTarget->evaluateAsAbsolute(Address)) {
152  O << formatHex((uint64_t)Address);
153  }
154  else {
155  // Otherwise, just print the expression.
156  Op.getExpr()->print(O, &MAI);
157  }
158  }
159 }
160 
161 void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
162  raw_ostream &O) {
163  const MCOperand &Op = MI->getOperand(OpNo);
164  if (Op.isReg()) {
165  printRegName(O, Op.getReg());
166  } else if (Op.isImm()) {
167  O << formatImm((int64_t)Op.getImm());
168  } else {
169  assert(Op.isExpr() && "unknown operand kind in printOperand");
170  O << "offset ";
171  Op.getExpr()->print(O, &MAI);
172  }
173 }
174 
176  raw_ostream &O) {
177  const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg);
178  unsigned ScaleVal = MI->getOperand(Op+X86::AddrScaleAmt).getImm();
179  const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg);
180  const MCOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp);
181  const MCOperand &SegReg = MI->getOperand(Op+X86::AddrSegmentReg);
182 
183  // If this has a segment register, print it.
184  if (SegReg.getReg()) {
186  O << ':';
187  }
188 
189  O << '[';
190 
191  bool NeedPlus = false;
192  if (BaseReg.getReg()) {
193  printOperand(MI, Op+X86::AddrBaseReg, O);
194  NeedPlus = true;
195  }
196 
197  if (IndexReg.getReg()) {
198  if (NeedPlus) O << " + ";
199  if (ScaleVal != 1)
200  O << ScaleVal << '*';
201  printOperand(MI, Op+X86::AddrIndexReg, O);
202  NeedPlus = true;
203  }
204 
205  if (!DispSpec.isImm()) {
206  if (NeedPlus) O << " + ";
207  assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
208  DispSpec.getExpr()->print(O, &MAI);
209  } else {
210  int64_t DispVal = DispSpec.getImm();
211  if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
212  if (NeedPlus) {
213  if (DispVal > 0)
214  O << " + ";
215  else {
216  O << " - ";
217  DispVal = -DispVal;
218  }
219  }
220  O << formatImm(DispVal);
221  }
222  }
223 
224  O << ']';
225 }
226 
228  raw_ostream &O) {
229  const MCOperand &SegReg = MI->getOperand(Op+1);
230 
231  // If this has a segment register, print it.
232  if (SegReg.getReg()) {
233  printOperand(MI, Op+1, O);
234  O << ':';
235  }
236  O << '[';
237  printOperand(MI, Op, O);
238  O << ']';
239 }
240 
242  raw_ostream &O) {
243  // DI accesses are always ES-based.
244  O << "es:[";
245  printOperand(MI, Op, O);
246  O << ']';
247 }
248 
250  raw_ostream &O) {
251  const MCOperand &DispSpec = MI->getOperand(Op);
252  const MCOperand &SegReg = MI->getOperand(Op+1);
253 
254  // If this has a segment register, print it.
255  if (SegReg.getReg()) {
256  printOperand(MI, Op+1, O);
257  O << ':';
258  }
259 
260  O << '[';
261 
262  if (DispSpec.isImm()) {
263  O << formatImm(DispSpec.getImm());
264  } else {
265  assert(DispSpec.isExpr() && "non-immediate displacement?");
266  DispSpec.getExpr()->print(O, &MAI);
267  }
268 
269  O << ']';
270 }
271 
273  raw_ostream &O) {
274  if (MI->getOperand(Op).isExpr())
275  return MI->getOperand(Op).getExpr()->print(O, &MAI);
276 
277  O << formatImm(MI->getOperand(Op).getImm() & 0xff);
278 }
void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot, const MCSubtargetInfo &STI) override
Print the specified MCInst to the specified raw_ostream.
bool isImm() const
Definition: MCInst.h:59
void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
void printSrcIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O)
void printMemOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O)
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
void printSSEAVXCC(const MCInst *MI, unsigned Op, raw_ostream &O)
bool isReg() const
Definition: MCInst.h:58
void printInstruction(const MCInst *MI, raw_ostream &O)
void printRegName(raw_ostream &OS, unsigned RegNo) const override
Print the assembler register name.
const FeatureBitset & getFeatureBits() const
void printRoundingControl(const MCInst *MI, unsigned Op, raw_ostream &OS)
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:65
bool EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, const MCInstrInfo &MCII)
EmitAnyX86InstComments - This function decodes x86 instructions and prints newline terminated strings...
format_object< int64_t > formatImm(int64_t Value) const
Utility function to print immediates in decimal or hex.
Definition: MCInstPrinter.h:97
const MCExpr * getExpr() const
Definition: MCInst.h:96
void printXOPCC(const MCInst *MI, unsigned Op, raw_ostream &O)
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:161
int64_t getImm() const
Definition: MCInst.h:76
void print(raw_ostream &OS, const MCAsmInfo *MAI, bool InParens=false) const
Definition: MCExpr.cpp:40
unsigned getFlags() const
Definition: MCInst.h:177
bool isExpr() const
Definition: MCInst.h:61
static const char * getRegisterName(unsigned RegNo)
AddrSegmentReg - The operand # of the segment in the memory operand.
Definition: X86BaseInfo.h:39
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void printU8Imm(const MCInst *MI, unsigned Op, raw_ostream &O)
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:182
raw_ostream * CommentStream
A stream that comments can be emitted to if desired.
Definition: MCInstPrinter.h:46
void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &O)
const MCAsmInfo & MAI
Definition: MCInstPrinter.h:47
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
format_object< int64_t > formatHex(int64_t Value) const
Generic base class for all target subtargets.
const MCInstrInfo & MII
Definition: MCInstPrinter.h:48
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void printDstIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O)
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
void printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &O)
printPCRelImm - This is used to print an immediate value that ends up being encoded as a pc-relative ...
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
unsigned getOpcode() const
Definition: MCInst.h:174
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:35