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X86IntelInstPrinter.cpp
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1 //===-- X86IntelInstPrinter.cpp - Intel assembly instruction printing -----===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file includes code for rendering MCInst instances as Intel-style
11 // assembly.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "X86IntelInstPrinter.h"
17 #include "X86InstComments.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrDesc.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/Support/Casting.h"
24 #include <cassert>
25 #include <cstdint>
26 
27 using namespace llvm;
28 
29 #define DEBUG_TYPE "asm-printer"
30 
31 #include "X86GenAsmWriter1.inc"
32 
33 void X86IntelInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
34  OS << getRegisterName(RegNo);
35 }
36 
38  StringRef Annot,
39  const MCSubtargetInfo &STI) {
40  const MCInstrDesc &Desc = MII.get(MI->getOpcode());
41  uint64_t TSFlags = Desc.TSFlags;
42 
43  if (TSFlags & X86II::LOCK)
44  OS << "\tlock\n";
45 
46  printInstruction(MI, OS);
47 
48  // Next always print the annotation.
49  printAnnotation(OS, Annot);
50 
51  // If verbose assembly is enabled, we can print some informative comments.
52  if (CommentStream)
54 }
55 
57  raw_ostream &O) {
58  int64_t Imm = MI->getOperand(Op).getImm();
59  switch (Imm) {
60  default: llvm_unreachable("Invalid avxcc argument!");
61  case 0: O << "eq"; break;
62  case 1: O << "lt"; break;
63  case 2: O << "le"; break;
64  case 3: O << "unord"; break;
65  case 4: O << "neq"; break;
66  case 5: O << "nlt"; break;
67  case 6: O << "nle"; break;
68  case 7: O << "ord"; break;
69  case 8: O << "eq_uq"; break;
70  case 9: O << "nge"; break;
71  case 0xa: O << "ngt"; break;
72  case 0xb: O << "false"; break;
73  case 0xc: O << "neq_oq"; break;
74  case 0xd: O << "ge"; break;
75  case 0xe: O << "gt"; break;
76  case 0xf: O << "true"; break;
77  case 0x10: O << "eq_os"; break;
78  case 0x11: O << "lt_oq"; break;
79  case 0x12: O << "le_oq"; break;
80  case 0x13: O << "unord_s"; break;
81  case 0x14: O << "neq_us"; break;
82  case 0x15: O << "nlt_uq"; break;
83  case 0x16: O << "nle_uq"; break;
84  case 0x17: O << "ord_s"; break;
85  case 0x18: O << "eq_us"; break;
86  case 0x19: O << "nge_uq"; break;
87  case 0x1a: O << "ngt_uq"; break;
88  case 0x1b: O << "false_os"; break;
89  case 0x1c: O << "neq_os"; break;
90  case 0x1d: O << "ge_oq"; break;
91  case 0x1e: O << "gt_oq"; break;
92  case 0x1f: O << "true_us"; break;
93  }
94 }
95 
97  raw_ostream &O) {
98  int64_t Imm = MI->getOperand(Op).getImm();
99  switch (Imm) {
100  default: llvm_unreachable("Invalid xopcc argument!");
101  case 0: O << "lt"; break;
102  case 1: O << "le"; break;
103  case 2: O << "gt"; break;
104  case 3: O << "ge"; break;
105  case 4: O << "eq"; break;
106  case 5: O << "neq"; break;
107  case 6: O << "false"; break;
108  case 7: O << "true"; break;
109  }
110 }
111 
113  raw_ostream &O) {
114  int64_t Imm = MI->getOperand(Op).getImm() & 0x3;
115  switch (Imm) {
116  case 0: O << "{rn-sae}"; break;
117  case 1: O << "{rd-sae}"; break;
118  case 2: O << "{ru-sae}"; break;
119  case 3: O << "{rz-sae}"; break;
120  }
121 }
122 
123 /// printPCRelImm - This is used to print an immediate value that ends up
124 /// being encoded as a pc-relative value.
125 void X86IntelInstPrinter::printPCRelImm(const MCInst *MI, unsigned OpNo,
126  raw_ostream &O) {
127  const MCOperand &Op = MI->getOperand(OpNo);
128  if (Op.isImm())
129  O << formatImm(Op.getImm());
130  else {
131  assert(Op.isExpr() && "unknown pcrel immediate operand");
132  // If a symbolic branch target was added as a constant expression then print
133  // that address in hex.
134  const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
135  int64_t Address;
136  if (BranchTarget && BranchTarget->evaluateAsAbsolute(Address)) {
137  O << formatHex((uint64_t)Address);
138  }
139  else {
140  // Otherwise, just print the expression.
141  Op.getExpr()->print(O, &MAI);
142  }
143  }
144 }
145 
146 void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
147  raw_ostream &O) {
148  const MCOperand &Op = MI->getOperand(OpNo);
149  if (Op.isReg()) {
150  printRegName(O, Op.getReg());
151  } else if (Op.isImm()) {
152  O << formatImm((int64_t)Op.getImm());
153  } else {
154  assert(Op.isExpr() && "unknown operand kind in printOperand");
155  Op.getExpr()->print(O, &MAI);
156  }
157 }
158 
160  raw_ostream &O) {
161  const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg);
162  unsigned ScaleVal = MI->getOperand(Op+X86::AddrScaleAmt).getImm();
163  const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg);
164  const MCOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp);
165  const MCOperand &SegReg = MI->getOperand(Op+X86::AddrSegmentReg);
166 
167  // If this has a segment register, print it.
168  if (SegReg.getReg()) {
170  O << ':';
171  }
172 
173  O << '[';
174 
175  bool NeedPlus = false;
176  if (BaseReg.getReg()) {
177  printOperand(MI, Op+X86::AddrBaseReg, O);
178  NeedPlus = true;
179  }
180 
181  if (IndexReg.getReg()) {
182  if (NeedPlus) O << " + ";
183  if (ScaleVal != 1)
184  O << ScaleVal << '*';
185  printOperand(MI, Op+X86::AddrIndexReg, O);
186  NeedPlus = true;
187  }
188 
189  if (!DispSpec.isImm()) {
190  if (NeedPlus) O << " + ";
191  assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
192  DispSpec.getExpr()->print(O, &MAI);
193  } else {
194  int64_t DispVal = DispSpec.getImm();
195  if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
196  if (NeedPlus) {
197  if (DispVal > 0)
198  O << " + ";
199  else {
200  O << " - ";
201  DispVal = -DispVal;
202  }
203  }
204  O << formatImm(DispVal);
205  }
206  }
207 
208  O << ']';
209 }
210 
212  raw_ostream &O) {
213  const MCOperand &SegReg = MI->getOperand(Op+1);
214 
215  // If this has a segment register, print it.
216  if (SegReg.getReg()) {
217  printOperand(MI, Op+1, O);
218  O << ':';
219  }
220  O << '[';
221  printOperand(MI, Op, O);
222  O << ']';
223 }
224 
226  raw_ostream &O) {
227  // DI accesses are always ES-based.
228  O << "es:[";
229  printOperand(MI, Op, O);
230  O << ']';
231 }
232 
234  raw_ostream &O) {
235  const MCOperand &DispSpec = MI->getOperand(Op);
236  const MCOperand &SegReg = MI->getOperand(Op+1);
237 
238  // If this has a segment register, print it.
239  if (SegReg.getReg()) {
240  printOperand(MI, Op+1, O);
241  O << ':';
242  }
243 
244  O << '[';
245 
246  if (DispSpec.isImm()) {
247  O << formatImm(DispSpec.getImm());
248  } else {
249  assert(DispSpec.isExpr() && "non-immediate displacement?");
250  DispSpec.getExpr()->print(O, &MAI);
251  }
252 
253  O << ']';
254 }
255 
257  raw_ostream &O) {
258  if (MI->getOperand(Op).isExpr())
259  return MI->getOperand(Op).getExpr()->print(O, &MAI);
260 
261  O << formatImm(MI->getOperand(Op).getImm() & 0xff);
262 }
void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot, const MCSubtargetInfo &STI) override
Print the specified MCInst to the specified raw_ostream.
bool isImm() const
Definition: MCInst.h:59
void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
void printSrcIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O)
void printMemOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O)
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
void printSSEAVXCC(const MCInst *MI, unsigned Op, raw_ostream &O)
bool isReg() const
Definition: MCInst.h:58
void printInstruction(const MCInst *MI, raw_ostream &O)
void printRegName(raw_ostream &OS, unsigned RegNo) const override
Print the assembler register name.
void printRoundingControl(const MCInst *MI, unsigned Op, raw_ostream &OS)
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:65
format_object< int64_t > formatImm(int64_t Value) const
Utility function to print immediates in decimal or hex.
Definition: MCInstPrinter.h:97
const MCExpr * getExpr() const
Definition: MCInst.h:96
void printXOPCC(const MCInst *MI, unsigned Op, raw_ostream &O)
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:159
int64_t getImm() const
Definition: MCInst.h:76
void print(raw_ostream &OS, const MCAsmInfo *MAI, bool InParens=false) const
Definition: MCExpr.cpp:40
bool isExpr() const
Definition: MCInst.h:61
static const char * getRegisterName(unsigned RegNo)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void printU8Imm(const MCInst *MI, unsigned Op, raw_ostream &O)
AddrSegmentReg - The operand # of the segment in the memory operand.
Definition: X86BaseInfo.h:39
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:173
raw_ostream * CommentStream
A stream that comments can be emitted to if desired.
Definition: MCInstPrinter.h:46
void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &O)
const MCAsmInfo & MAI
Definition: MCInstPrinter.h:47
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
format_object< int64_t > formatHex(int64_t Value) const
MCSubtargetInfo - Generic base class for all target subtargets.
const MCInstrInfo & MII
Definition: MCInstPrinter.h:48
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void printDstIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O)
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
void printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &O)
printPCRelImm - This is used to print an immediate value that ends up being encoded as a pc-relative ...
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
unsigned getOpcode() const
Definition: MCInst.h:168
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:35
bool EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, const char *(*getRegName)(unsigned))
EmitAnyX86InstComments - This function decodes x86 instructions and prints newline terminated strings...