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X86IntelInstPrinter.cpp
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1 //===-- X86IntelInstPrinter.cpp - Intel assembly instruction printing -----===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file includes code for rendering MCInst instances as Intel-style
11 // assembly.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "X86IntelInstPrinter.h"
17 #include "X86InstComments.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrDesc.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/Support/Casting.h"
24 #include <cassert>
25 #include <cstdint>
26 
27 using namespace llvm;
28 
29 #define DEBUG_TYPE "asm-printer"
30 
31 #include "X86GenAsmWriter1.inc"
32 
33 void X86IntelInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
34  OS << getRegisterName(RegNo);
35 }
36 
38  StringRef Annot,
39  const MCSubtargetInfo &STI) {
40  const MCInstrDesc &Desc = MII.get(MI->getOpcode());
41  uint64_t TSFlags = Desc.TSFlags;
42 
43  if (TSFlags & X86II::LOCK)
44  OS << "\tlock\t";
45 
46  unsigned Flags = MI->getFlags();
47  if (Flags & X86::IP_HAS_REPEAT_NE)
48  OS << "\trepne\t";
49  else if (Flags & X86::IP_HAS_REPEAT)
50  OS << "\trep\t";
51 
52  printInstruction(MI, OS);
53 
54  // Next always print the annotation.
55  printAnnotation(OS, Annot);
56 
57  // If verbose assembly is enabled, we can print some informative comments.
58  if (CommentStream)
60 }
61 
63  raw_ostream &O) {
64  int64_t Imm = MI->getOperand(Op).getImm();
65  switch (Imm) {
66  default: llvm_unreachable("Invalid avxcc argument!");
67  case 0: O << "eq"; break;
68  case 1: O << "lt"; break;
69  case 2: O << "le"; break;
70  case 3: O << "unord"; break;
71  case 4: O << "neq"; break;
72  case 5: O << "nlt"; break;
73  case 6: O << "nle"; break;
74  case 7: O << "ord"; break;
75  case 8: O << "eq_uq"; break;
76  case 9: O << "nge"; break;
77  case 0xa: O << "ngt"; break;
78  case 0xb: O << "false"; break;
79  case 0xc: O << "neq_oq"; break;
80  case 0xd: O << "ge"; break;
81  case 0xe: O << "gt"; break;
82  case 0xf: O << "true"; break;
83  case 0x10: O << "eq_os"; break;
84  case 0x11: O << "lt_oq"; break;
85  case 0x12: O << "le_oq"; break;
86  case 0x13: O << "unord_s"; break;
87  case 0x14: O << "neq_us"; break;
88  case 0x15: O << "nlt_uq"; break;
89  case 0x16: O << "nle_uq"; break;
90  case 0x17: O << "ord_s"; break;
91  case 0x18: O << "eq_us"; break;
92  case 0x19: O << "nge_uq"; break;
93  case 0x1a: O << "ngt_uq"; break;
94  case 0x1b: O << "false_os"; break;
95  case 0x1c: O << "neq_os"; break;
96  case 0x1d: O << "ge_oq"; break;
97  case 0x1e: O << "gt_oq"; break;
98  case 0x1f: O << "true_us"; break;
99  }
100 }
101 
103  raw_ostream &O) {
104  int64_t Imm = MI->getOperand(Op).getImm();
105  switch (Imm) {
106  default: llvm_unreachable("Invalid xopcc argument!");
107  case 0: O << "lt"; break;
108  case 1: O << "le"; break;
109  case 2: O << "gt"; break;
110  case 3: O << "ge"; break;
111  case 4: O << "eq"; break;
112  case 5: O << "neq"; break;
113  case 6: O << "false"; break;
114  case 7: O << "true"; break;
115  }
116 }
117 
119  raw_ostream &O) {
120  int64_t Imm = MI->getOperand(Op).getImm() & 0x3;
121  switch (Imm) {
122  case 0: O << "{rn-sae}"; break;
123  case 1: O << "{rd-sae}"; break;
124  case 2: O << "{ru-sae}"; break;
125  case 3: O << "{rz-sae}"; break;
126  }
127 }
128 
129 /// printPCRelImm - This is used to print an immediate value that ends up
130 /// being encoded as a pc-relative value.
131 void X86IntelInstPrinter::printPCRelImm(const MCInst *MI, unsigned OpNo,
132  raw_ostream &O) {
133  const MCOperand &Op = MI->getOperand(OpNo);
134  if (Op.isImm())
135  O << formatImm(Op.getImm());
136  else {
137  assert(Op.isExpr() && "unknown pcrel immediate operand");
138  // If a symbolic branch target was added as a constant expression then print
139  // that address in hex.
140  const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
141  int64_t Address;
142  if (BranchTarget && BranchTarget->evaluateAsAbsolute(Address)) {
143  O << formatHex((uint64_t)Address);
144  }
145  else {
146  // Otherwise, just print the expression.
147  Op.getExpr()->print(O, &MAI);
148  }
149  }
150 }
151 
152 void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
153  raw_ostream &O) {
154  const MCOperand &Op = MI->getOperand(OpNo);
155  if (Op.isReg()) {
156  printRegName(O, Op.getReg());
157  } else if (Op.isImm()) {
158  O << formatImm((int64_t)Op.getImm());
159  } else {
160  assert(Op.isExpr() && "unknown operand kind in printOperand");
161  O << "offset ";
162  Op.getExpr()->print(O, &MAI);
163  }
164 }
165 
167  raw_ostream &O) {
168  const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg);
169  unsigned ScaleVal = MI->getOperand(Op+X86::AddrScaleAmt).getImm();
170  const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg);
171  const MCOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp);
172  const MCOperand &SegReg = MI->getOperand(Op+X86::AddrSegmentReg);
173 
174  // If this has a segment register, print it.
175  if (SegReg.getReg()) {
177  O << ':';
178  }
179 
180  O << '[';
181 
182  bool NeedPlus = false;
183  if (BaseReg.getReg()) {
184  printOperand(MI, Op+X86::AddrBaseReg, O);
185  NeedPlus = true;
186  }
187 
188  if (IndexReg.getReg()) {
189  if (NeedPlus) O << " + ";
190  if (ScaleVal != 1)
191  O << ScaleVal << '*';
192  printOperand(MI, Op+X86::AddrIndexReg, O);
193  NeedPlus = true;
194  }
195 
196  if (!DispSpec.isImm()) {
197  if (NeedPlus) O << " + ";
198  assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
199  DispSpec.getExpr()->print(O, &MAI);
200  } else {
201  int64_t DispVal = DispSpec.getImm();
202  if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
203  if (NeedPlus) {
204  if (DispVal > 0)
205  O << " + ";
206  else {
207  O << " - ";
208  DispVal = -DispVal;
209  }
210  }
211  O << formatImm(DispVal);
212  }
213  }
214 
215  O << ']';
216 }
217 
219  raw_ostream &O) {
220  const MCOperand &SegReg = MI->getOperand(Op+1);
221 
222  // If this has a segment register, print it.
223  if (SegReg.getReg()) {
224  printOperand(MI, Op+1, O);
225  O << ':';
226  }
227  O << '[';
228  printOperand(MI, Op, O);
229  O << ']';
230 }
231 
233  raw_ostream &O) {
234  // DI accesses are always ES-based.
235  O << "es:[";
236  printOperand(MI, Op, O);
237  O << ']';
238 }
239 
241  raw_ostream &O) {
242  const MCOperand &DispSpec = MI->getOperand(Op);
243  const MCOperand &SegReg = MI->getOperand(Op+1);
244 
245  // If this has a segment register, print it.
246  if (SegReg.getReg()) {
247  printOperand(MI, Op+1, O);
248  O << ':';
249  }
250 
251  O << '[';
252 
253  if (DispSpec.isImm()) {
254  O << formatImm(DispSpec.getImm());
255  } else {
256  assert(DispSpec.isExpr() && "non-immediate displacement?");
257  DispSpec.getExpr()->print(O, &MAI);
258  }
259 
260  O << ']';
261 }
262 
264  raw_ostream &O) {
265  if (MI->getOperand(Op).isExpr())
266  return MI->getOperand(Op).getExpr()->print(O, &MAI);
267 
268  O << formatImm(MI->getOperand(Op).getImm() & 0xff);
269 }
void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot, const MCSubtargetInfo &STI) override
Print the specified MCInst to the specified raw_ostream.
bool isImm() const
Definition: MCInst.h:59
void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
void printSrcIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O)
void printMemOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O)
AddrSegmentReg - The operand # of the segment in the memory operand.
Definition: X86BaseInfo.h:39
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
void printSSEAVXCC(const MCInst *MI, unsigned Op, raw_ostream &O)
bool isReg() const
Definition: MCInst.h:58
void printInstruction(const MCInst *MI, raw_ostream &O)
void printRegName(raw_ostream &OS, unsigned RegNo) const override
Print the assembler register name.
void printRoundingControl(const MCInst *MI, unsigned Op, raw_ostream &OS)
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:65
format_object< int64_t > formatImm(int64_t Value) const
Utility function to print immediates in decimal or hex.
Definition: MCInstPrinter.h:97
const MCExpr * getExpr() const
Definition: MCInst.h:96
void printXOPCC(const MCInst *MI, unsigned Op, raw_ostream &O)
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:159
int64_t getImm() const
Definition: MCInst.h:76
void print(raw_ostream &OS, const MCAsmInfo *MAI, bool InParens=false) const
Definition: MCExpr.cpp:40
unsigned getFlags() const
Definition: MCInst.h:175
bool isExpr() const
Definition: MCInst.h:61
static const char * getRegisterName(unsigned RegNo)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void printU8Imm(const MCInst *MI, unsigned Op, raw_ostream &O)
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:180
raw_ostream * CommentStream
A stream that comments can be emitted to if desired.
Definition: MCInstPrinter.h:46
void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &O)
const MCAsmInfo & MAI
Definition: MCInstPrinter.h:47
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
format_object< int64_t > formatHex(int64_t Value) const
MCSubtargetInfo - Generic base class for all target subtargets.
const MCInstrInfo & MII
Definition: MCInstPrinter.h:48
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void printDstIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O)
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
void printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &O)
printPCRelImm - This is used to print an immediate value that ends up being encoded as a pc-relative ...
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
unsigned getOpcode() const
Definition: MCInst.h:172
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:35
bool EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, const char *(*getRegName)(unsigned))
EmitAnyX86InstComments - This function decodes x86 instructions and prints newline terminated strings...