LLVM  9.0.0svn
X86IntelInstPrinter.cpp
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1 //===-- X86IntelInstPrinter.cpp - Intel assembly instruction printing -----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file includes code for rendering MCInst instances as Intel-style
10 // assembly.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86IntelInstPrinter.h"
16 #include "X86InstComments.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstrDesc.h"
20 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/Support/Casting.h"
24 #include <cassert>
25 #include <cstdint>
26 
27 using namespace llvm;
28 
29 #define DEBUG_TYPE "asm-printer"
30 
31 #include "X86GenAsmWriter1.inc"
32 
33 void X86IntelInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
34  OS << getRegisterName(RegNo);
35 }
36 
38  StringRef Annot,
39  const MCSubtargetInfo &STI) {
40  printInstFlags(MI, OS);
41 
42  // In 16-bit mode, print data16 as data32.
43  if (MI->getOpcode() == X86::DATA16_PREFIX &&
44  STI.getFeatureBits()[X86::Mode16Bit]) {
45  OS << "\tdata32";
46  } else
47  printInstruction(MI, OS);
48 
49  // Next always print the annotation.
50  printAnnotation(OS, Annot);
51 
52  // If verbose assembly is enabled, we can print some informative comments.
53  if (CommentStream)
55 }
56 
57 void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
58  raw_ostream &O) {
59  const MCOperand &Op = MI->getOperand(OpNo);
60  if (Op.isReg()) {
61  printRegName(O, Op.getReg());
62  } else if (Op.isImm()) {
63  O << formatImm((int64_t)Op.getImm());
64  } else {
65  assert(Op.isExpr() && "unknown operand kind in printOperand");
66  O << "offset ";
67  Op.getExpr()->print(O, &MAI);
68  }
69 }
70 
72  raw_ostream &O) {
73  const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg);
74  unsigned ScaleVal = MI->getOperand(Op+X86::AddrScaleAmt).getImm();
75  const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg);
76  const MCOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp);
77 
78  // If this has a segment register, print it.
80 
81  O << '[';
82 
83  bool NeedPlus = false;
84  if (BaseReg.getReg()) {
85  printOperand(MI, Op+X86::AddrBaseReg, O);
86  NeedPlus = true;
87  }
88 
89  if (IndexReg.getReg()) {
90  if (NeedPlus) O << " + ";
91  if (ScaleVal != 1)
92  O << ScaleVal << '*';
94  NeedPlus = true;
95  }
96 
97  if (!DispSpec.isImm()) {
98  if (NeedPlus) O << " + ";
99  assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
100  DispSpec.getExpr()->print(O, &MAI);
101  } else {
102  int64_t DispVal = DispSpec.getImm();
103  if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
104  if (NeedPlus) {
105  if (DispVal > 0)
106  O << " + ";
107  else {
108  O << " - ";
109  DispVal = -DispVal;
110  }
111  }
112  O << formatImm(DispVal);
113  }
114  }
115 
116  O << ']';
117 }
118 
120  raw_ostream &O) {
121  // If this has a segment register, print it.
122  printOptionalSegReg(MI, Op + 1, O);
123  O << '[';
124  printOperand(MI, Op, O);
125  O << ']';
126 }
127 
129  raw_ostream &O) {
130  // DI accesses are always ES-based.
131  O << "es:[";
132  printOperand(MI, Op, O);
133  O << ']';
134 }
135 
137  raw_ostream &O) {
138  const MCOperand &DispSpec = MI->getOperand(Op);
139 
140  // If this has a segment register, print it.
141  printOptionalSegReg(MI, Op + 1, O);
142 
143  O << '[';
144 
145  if (DispSpec.isImm()) {
146  O << formatImm(DispSpec.getImm());
147  } else {
148  assert(DispSpec.isExpr() && "non-immediate displacement?");
149  DispSpec.getExpr()->print(O, &MAI);
150  }
151 
152  O << ']';
153 }
154 
156  raw_ostream &O) {
157  if (MI->getOperand(Op).isExpr())
158  return MI->getOperand(Op).getExpr()->print(O, &MAI);
159 
160  O << formatImm(MI->getOperand(Op).getImm() & 0xff);
161 }
162 
164  raw_ostream &OS) {
165  const MCOperand &Op = MI->getOperand(OpNo);
166  unsigned Reg = Op.getReg();
167  // Override the default printing to print st(0) instead st.
168  if (Reg == X86::ST0)
169  OS << "st(0)";
170  else
171  printRegName(OS, Reg);
172 }
void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) override
void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot, const MCSubtargetInfo &STI) override
Print the specified MCInst to the specified raw_ostream.
bool isImm() const
Definition: MCInst.h:58
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void printSrcIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O)
void printMemOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O)
unsigned Reg
bool isReg() const
Definition: MCInst.h:57
void printInstruction(const MCInst *MI, raw_ostream &O)
void printRegName(raw_ostream &OS, unsigned RegNo) const override
Print the assembler register name.
const FeatureBitset & getFeatureBits() const
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:64
bool EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, const MCInstrInfo &MCII)
EmitAnyX86InstComments - This function decodes x86 instructions and prints newline terminated strings...
format_object< int64_t > formatImm(int64_t Value) const
Utility function to print immediates in decimal or hex.
Definition: MCInstPrinter.h:95
const MCExpr * getExpr() const
Definition: MCInst.h:95
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
void printOptionalSegReg(const MCInst *MI, unsigned OpNo, raw_ostream &O)
int64_t getImm() const
Definition: MCInst.h:75
AddrSegmentReg - The operand # of the segment in the memory operand.
Definition: X86BaseInfo.h:38
void print(raw_ostream &OS, const MCAsmInfo *MAI, bool InParens=false) const
Definition: MCExpr.cpp:41
bool isExpr() const
Definition: MCInst.h:60
static const char * getRegisterName(unsigned RegNo)
void printU8Imm(const MCInst *MI, unsigned Op, raw_ostream &O)
void printInstFlags(const MCInst *MI, raw_ostream &O)
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:179
raw_ostream * CommentStream
A stream that comments can be emitted to if desired.
Definition: MCInstPrinter.h:44
void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &O)
void printSTiRegOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS)
const MCAsmInfo & MAI
Definition: MCInstPrinter.h:45
Generic base class for all target subtargets.
const MCInstrInfo & MII
Definition: MCInstPrinter.h:46
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void printDstIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O)
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
unsigned getOpcode() const
Definition: MCInst.h:171
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:34