LLVM  9.0.0svn
X86MCCodeEmitter.cpp
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1 //===-- X86MCCodeEmitter.cpp - Convert X86 code to machine code -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the X86MCCodeEmitter class.
10 //
11 //===----------------------------------------------------------------------===//
12 
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/MC/MCCodeEmitter.h"
18 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCFixup.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/MC/MCInstrDesc.h"
23 #include "llvm/MC/MCInstrInfo.h"
24 #include "llvm/MC/MCRegisterInfo.h"
26 #include "llvm/MC/MCSymbol.h"
29 #include <cassert>
30 #include <cstdint>
31 #include <cstdlib>
32 
33 using namespace llvm;
34 
35 #define DEBUG_TYPE "mccodeemitter"
36 
37 namespace {
38 
39 class X86MCCodeEmitter : public MCCodeEmitter {
40  const MCInstrInfo &MCII;
41  MCContext &Ctx;
42 
43 public:
44  X86MCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
45  : MCII(mcii), Ctx(ctx) {
46  }
47  X86MCCodeEmitter(const X86MCCodeEmitter &) = delete;
48  X86MCCodeEmitter &operator=(const X86MCCodeEmitter &) = delete;
49  ~X86MCCodeEmitter() override = default;
50 
51  bool is64BitMode(const MCSubtargetInfo &STI) const {
52  return STI.getFeatureBits()[X86::Mode64Bit];
53  }
54 
55  bool is32BitMode(const MCSubtargetInfo &STI) const {
56  return STI.getFeatureBits()[X86::Mode32Bit];
57  }
58 
59  bool is16BitMode(const MCSubtargetInfo &STI) const {
60  return STI.getFeatureBits()[X86::Mode16Bit];
61  }
62 
63  /// Is16BitMemOperand - Return true if the specified instruction has
64  /// a 16-bit memory operand. Op specifies the operand # of the memoperand.
65  bool Is16BitMemOperand(const MCInst &MI, unsigned Op,
66  const MCSubtargetInfo &STI) const {
67  const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
68  const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
69  const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp);
70 
71  if (is16BitMode(STI) && BaseReg.getReg() == 0 &&
72  Disp.isImm() && Disp.getImm() < 0x10000)
73  return true;
74  if ((BaseReg.getReg() != 0 &&
75  X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) ||
76  (IndexReg.getReg() != 0 &&
77  X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg())))
78  return true;
79  return false;
80  }
81 
82  unsigned GetX86RegNum(const MCOperand &MO) const {
83  return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()) & 0x7;
84  }
85 
86  unsigned getX86RegEncoding(const MCInst &MI, unsigned OpNum) const {
87  return Ctx.getRegisterInfo()->getEncodingValue(
88  MI.getOperand(OpNum).getReg());
89  }
90 
91  // Does this register require a bit to be set in REX prefix.
92  bool isREXExtendedReg(const MCInst &MI, unsigned OpNum) const {
93  return (getX86RegEncoding(MI, OpNum) >> 3) & 1;
94  }
95 
96  void EmitByte(uint8_t C, unsigned &CurByte, raw_ostream &OS) const {
97  OS << (char)C;
98  ++CurByte;
99  }
100 
101  void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
102  raw_ostream &OS) const {
103  // Output the constant in little endian byte order.
104  for (unsigned i = 0; i != Size; ++i) {
105  EmitByte(Val & 255, CurByte, OS);
106  Val >>= 8;
107  }
108  }
109 
110  void EmitImmediate(const MCOperand &Disp, SMLoc Loc,
111  unsigned ImmSize, MCFixupKind FixupKind,
112  unsigned &CurByte, raw_ostream &OS,
114  int ImmOffset = 0) const;
115 
116  static uint8_t ModRMByte(unsigned Mod, unsigned RegOpcode, unsigned RM) {
117  assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
118  return RM | (RegOpcode << 3) | (Mod << 6);
119  }
120 
121  void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
122  unsigned &CurByte, raw_ostream &OS) const {
123  EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS);
124  }
125 
126  void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base,
127  unsigned &CurByte, raw_ostream &OS) const {
128  // SIB byte is in the same format as the ModRMByte.
129  EmitByte(ModRMByte(SS, Index, Base), CurByte, OS);
130  }
131 
132  void emitMemModRMByte(const MCInst &MI, unsigned Op, unsigned RegOpcodeField,
133  uint64_t TSFlags, bool Rex, unsigned &CurByte,
135  const MCSubtargetInfo &STI) const;
136 
137  void encodeInstruction(const MCInst &MI, raw_ostream &OS,
138  SmallVectorImpl<MCFixup> &Fixups,
139  const MCSubtargetInfo &STI) const override;
140 
141  void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
142  const MCInst &MI, const MCInstrDesc &Desc,
143  raw_ostream &OS) const;
144 
145  void EmitSegmentOverridePrefix(unsigned &CurByte, unsigned SegOperand,
146  const MCInst &MI, raw_ostream &OS) const;
147 
148  bool emitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
149  const MCInst &MI, const MCInstrDesc &Desc,
150  const MCSubtargetInfo &STI, raw_ostream &OS) const;
151 
152  uint8_t DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags,
153  int MemOperand, const MCInstrDesc &Desc) const;
154 
155  bool isPCRel32Branch(const MCInst &MI) const;
156 };
157 
158 } // end anonymous namespace
159 
160 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
161 /// sign-extended field.
162 static bool isDisp8(int Value) {
163  return Value == (int8_t)Value;
164 }
165 
166 /// isCDisp8 - Return true if this signed displacement fits in a 8-bit
167 /// compressed dispacement field.
168 static bool isCDisp8(uint64_t TSFlags, int Value, int& CValue) {
169  assert(((TSFlags & X86II::EncodingMask) == X86II::EVEX) &&
170  "Compressed 8-bit displacement is only valid for EVEX inst.");
171 
172  unsigned CD8_Scale =
174  if (CD8_Scale == 0) {
175  CValue = Value;
176  return isDisp8(Value);
177  }
178 
179  unsigned Mask = CD8_Scale - 1;
180  assert((CD8_Scale & Mask) == 0 && "Invalid memory object size.");
181  if (Value & Mask) // Unaligned offset
182  return false;
183  Value /= (int)CD8_Scale;
184  bool Ret = (Value == (int8_t)Value);
185 
186  if (Ret)
187  CValue = Value;
188  return Ret;
189 }
190 
191 /// getImmFixupKind - Return the appropriate fixup kind to use for an immediate
192 /// in an instruction with the specified TSFlags.
193 static MCFixupKind getImmFixupKind(uint64_t TSFlags) {
194  unsigned Size = X86II::getSizeOfImm(TSFlags);
195  bool isPCRel = X86II::isImmPCRel(TSFlags);
196 
197  if (X86II::isImmSigned(TSFlags)) {
198  switch (Size) {
199  default: llvm_unreachable("Unsupported signed fixup size!");
200  case 4: return MCFixupKind(X86::reloc_signed_4byte);
201  }
202  }
203  return MCFixup::getKindForSize(Size, isPCRel);
204 }
205 
206 /// Is32BitMemOperand - Return true if the specified instruction has
207 /// a 32-bit memory operand. Op specifies the operand # of the memoperand.
208 static bool Is32BitMemOperand(const MCInst &MI, unsigned Op) {
209  const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
210  const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
211 
212  if ((BaseReg.getReg() != 0 &&
213  X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) ||
214  (IndexReg.getReg() != 0 &&
215  X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg())))
216  return true;
217  if (BaseReg.getReg() == X86::EIP) {
218  assert(IndexReg.getReg() == 0 && "Invalid eip-based address.");
219  return true;
220  }
221  if (IndexReg.getReg() == X86::EIZ)
222  return true;
223  return false;
224 }
225 
226 /// Is64BitMemOperand - Return true if the specified instruction has
227 /// a 64-bit memory operand. Op specifies the operand # of the memoperand.
228 #ifndef NDEBUG
229 static bool Is64BitMemOperand(const MCInst &MI, unsigned Op) {
230  const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
231  const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
232 
233  if ((BaseReg.getReg() != 0 &&
234  X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) ||
235  (IndexReg.getReg() != 0 &&
236  X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg())))
237  return true;
238  return false;
239 }
240 #endif
241 
242 /// StartsWithGlobalOffsetTable - Check if this expression starts with
243 /// _GLOBAL_OFFSET_TABLE_ and if it is of the form
244 /// _GLOBAL_OFFSET_TABLE_-symbol. This is needed to support PIC on ELF
245 /// i386 as _GLOBAL_OFFSET_TABLE_ is magical. We check only simple case that
246 /// are know to be used: _GLOBAL_OFFSET_TABLE_ by itself or at the start
247 /// of a binary expression.
252 };
255  const MCExpr *RHS = nullptr;
256  if (Expr->getKind() == MCExpr::Binary) {
257  const MCBinaryExpr *BE = static_cast<const MCBinaryExpr *>(Expr);
258  Expr = BE->getLHS();
259  RHS = BE->getRHS();
260  }
261 
262  if (Expr->getKind() != MCExpr::SymbolRef)
263  return GOT_None;
264 
265  const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr);
266  const MCSymbol &S = Ref->getSymbol();
267  if (S.getName() != "_GLOBAL_OFFSET_TABLE_")
268  return GOT_None;
269  if (RHS && RHS->getKind() == MCExpr::SymbolRef)
270  return GOT_SymDiff;
271  return GOT_Normal;
272 }
273 
274 static bool HasSecRelSymbolRef(const MCExpr *Expr) {
275  if (Expr->getKind() == MCExpr::SymbolRef) {
276  const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr);
277  return Ref->getKind() == MCSymbolRefExpr::VK_SECREL;
278  }
279  return false;
280 }
281 
282 bool X86MCCodeEmitter::isPCRel32Branch(const MCInst &MI) const {
283  unsigned Opcode = MI.getOpcode();
284  const MCInstrDesc &Desc = MCII.get(Opcode);
285  if ((Opcode != X86::CALL64pcrel32 && Opcode != X86::JMP_4) ||
287  return false;
288 
289  unsigned CurOp = X86II::getOperandBias(Desc);
290  const MCOperand &Op = MI.getOperand(CurOp);
291  if (!Op.isExpr())
292  return false;
293 
295  return Ref && Ref->getKind() == MCSymbolRefExpr::VK_None;
296 }
297 
298 void X86MCCodeEmitter::
299 EmitImmediate(const MCOperand &DispOp, SMLoc Loc, unsigned Size,
300  MCFixupKind FixupKind, unsigned &CurByte, raw_ostream &OS,
301  SmallVectorImpl<MCFixup> &Fixups, int ImmOffset) const {
302  const MCExpr *Expr = nullptr;
303  if (DispOp.isImm()) {
304  // If this is a simple integer displacement that doesn't require a
305  // relocation, emit it now.
306  if (FixupKind != FK_PCRel_1 &&
307  FixupKind != FK_PCRel_2 &&
308  FixupKind != FK_PCRel_4) {
309  EmitConstant(DispOp.getImm()+ImmOffset, Size, CurByte, OS);
310  return;
311  }
312  Expr = MCConstantExpr::create(DispOp.getImm(), Ctx);
313  } else {
314  Expr = DispOp.getExpr();
315  }
316 
317  // If we have an immoffset, add it to the expression.
318  if ((FixupKind == FK_Data_4 ||
319  FixupKind == FK_Data_8 ||
322  if (Kind != GOT_None) {
323  assert(ImmOffset == 0);
324 
325  if (Size == 8) {
327  } else {
328  assert(Size == 4);
330  }
331 
332  if (Kind == GOT_Normal)
333  ImmOffset = CurByte;
334  } else if (Expr->getKind() == MCExpr::SymbolRef) {
335  if (HasSecRelSymbolRef(Expr)) {
337  }
338  } else if (Expr->getKind() == MCExpr::Binary) {
339  const MCBinaryExpr *Bin = static_cast<const MCBinaryExpr*>(Expr);
340  if (HasSecRelSymbolRef(Bin->getLHS())
341  || HasSecRelSymbolRef(Bin->getRHS())) {
343  }
344  }
345  }
346 
347  // If the fixup is pc-relative, we need to bias the value to be relative to
348  // the start of the field, not the end of the field.
349  if (FixupKind == FK_PCRel_4 ||
355  ImmOffset -= 4;
356  // If this is a pc-relative load off _GLOBAL_OFFSET_TABLE_:
357  // leaq _GLOBAL_OFFSET_TABLE_(%rip), %r15
358  // this needs to be a GOTPC32 relocation.
361  }
362  if (FixupKind == FK_PCRel_2)
363  ImmOffset -= 2;
364  if (FixupKind == FK_PCRel_1)
365  ImmOffset -= 1;
366 
367  if (ImmOffset)
368  Expr = MCBinaryExpr::createAdd(Expr, MCConstantExpr::create(ImmOffset, Ctx),
369  Ctx);
370 
371  // Emit a symbolic constant as a fixup and 4 zeros.
372  Fixups.push_back(MCFixup::create(CurByte, Expr, FixupKind, Loc));
373  EmitConstant(0, Size, CurByte, OS);
374 }
375 
376 void X86MCCodeEmitter::emitMemModRMByte(const MCInst &MI, unsigned Op,
377  unsigned RegOpcodeField,
378  uint64_t TSFlags, bool Rex,
379  unsigned &CurByte, raw_ostream &OS,
380  SmallVectorImpl<MCFixup> &Fixups,
381  const MCSubtargetInfo &STI) const {
382  const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp);
383  const MCOperand &Base = MI.getOperand(Op+X86::AddrBaseReg);
384  const MCOperand &Scale = MI.getOperand(Op+X86::AddrScaleAmt);
385  const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
386  unsigned BaseReg = Base.getReg();
387  bool HasEVEX = (TSFlags & X86II::EncodingMask) == X86II::EVEX;
388 
389  // Handle %rip relative addressing.
390  if (BaseReg == X86::RIP ||
391  BaseReg == X86::EIP) { // [disp32+rIP] in X86-64 mode
392  assert(is64BitMode(STI) && "Rip-relative addressing requires 64-bit mode");
393  assert(IndexReg.getReg() == 0 && "Invalid rip-relative address");
394  EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
395 
396  unsigned Opcode = MI.getOpcode();
397  // movq loads are handled with a special relocation form which allows the
398  // linker to eliminate some loads for GOT references which end up in the
399  // same linkage unit.
400  unsigned FixupKind = [=]() {
401  switch (Opcode) {
402  default:
404  case X86::MOV64rm:
405  assert(Rex);
407  case X86::CALL64m:
408  case X86::JMP64m:
409  case X86::TAILJMPm64:
410  case X86::TEST64mr:
411  case X86::ADC64rm:
412  case X86::ADD64rm:
413  case X86::AND64rm:
414  case X86::CMP64rm:
415  case X86::OR64rm:
416  case X86::SBB64rm:
417  case X86::SUB64rm:
418  case X86::XOR64rm:
421  }
422  }();
423 
424  // rip-relative addressing is actually relative to the *next* instruction.
425  // Since an immediate can follow the mod/rm byte for an instruction, this
426  // means that we need to bias the displacement field of the instruction with
427  // the size of the immediate field. If we have this case, add it into the
428  // expression to emit.
429  // Note: rip-relative addressing using immediate displacement values should
430  // not be adjusted, assuming it was the user's intent.
431  int ImmSize = !Disp.isImm() && X86II::hasImm(TSFlags)
432  ? X86II::getSizeOfImm(TSFlags)
433  : 0;
434 
435  EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind),
436  CurByte, OS, Fixups, -ImmSize);
437  return;
438  }
439 
440  unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U;
441 
442  // 16-bit addressing forms of the ModR/M byte have a different encoding for
443  // the R/M field and are far more limited in which registers can be used.
444  if (Is16BitMemOperand(MI, Op, STI)) {
445  if (BaseReg) {
446  // For 32-bit addressing, the row and column values in Table 2-2 are
447  // basically the same. It's AX/CX/DX/BX/SP/BP/SI/DI in that order, with
448  // some special cases. And GetX86RegNum reflects that numbering.
449  // For 16-bit addressing it's more fun, as shown in the SDM Vol 2A,
450  // Table 2-1 "16-Bit Addressing Forms with the ModR/M byte". We can only
451  // use SI/DI/BP/BX, which have "row" values 4-7 in no particular order,
452  // while values 0-3 indicate the allowed combinations (base+index) of
453  // those: 0 for BX+SI, 1 for BX+DI, 2 for BP+SI, 3 for BP+DI.
454  //
455  // R16Table[] is a lookup from the normal RegNo, to the row values from
456  // Table 2-1 for 16-bit addressing modes. Where zero means disallowed.
457  static const unsigned R16Table[] = { 0, 0, 0, 7, 0, 6, 4, 5 };
458  unsigned RMfield = R16Table[BaseRegNo];
459 
460  assert(RMfield && "invalid 16-bit base register");
461 
462  if (IndexReg.getReg()) {
463  unsigned IndexReg16 = R16Table[GetX86RegNum(IndexReg)];
464 
465  assert(IndexReg16 && "invalid 16-bit index register");
466  // We must have one of SI/DI (4,5), and one of BP/BX (6,7).
467  assert(((IndexReg16 ^ RMfield) & 2) &&
468  "invalid 16-bit base/index register combination");
469  assert(Scale.getImm() == 1 &&
470  "invalid scale for 16-bit memory reference");
471 
472  // Allow base/index to appear in either order (although GAS doesn't).
473  if (IndexReg16 & 2)
474  RMfield = (RMfield & 1) | ((7 - IndexReg16) << 1);
475  else
476  RMfield = (IndexReg16 & 1) | ((7 - RMfield) << 1);
477  }
478 
479  if (Disp.isImm() && isDisp8(Disp.getImm())) {
480  if (Disp.getImm() == 0 && RMfield != 6) {
481  // There is no displacement; just the register.
482  EmitByte(ModRMByte(0, RegOpcodeField, RMfield), CurByte, OS);
483  return;
484  }
485  // Use the [REG]+disp8 form, including for [BP] which cannot be encoded.
486  EmitByte(ModRMByte(1, RegOpcodeField, RMfield), CurByte, OS);
487  EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups);
488  return;
489  }
490  // This is the [REG]+disp16 case.
491  EmitByte(ModRMByte(2, RegOpcodeField, RMfield), CurByte, OS);
492  } else {
493  // There is no BaseReg; this is the plain [disp16] case.
494  EmitByte(ModRMByte(0, RegOpcodeField, 6), CurByte, OS);
495  }
496 
497  // Emit 16-bit displacement for plain disp16 or [REG]+disp16 cases.
498  EmitImmediate(Disp, MI.getLoc(), 2, FK_Data_2, CurByte, OS, Fixups);
499  return;
500  }
501 
502  // Determine whether a SIB byte is needed.
503  // If no BaseReg, issue a RIP relative instruction only if the MCE can
504  // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
505  // 2-7) and absolute references.
506 
507  if (// The SIB byte must be used if there is an index register.
508  IndexReg.getReg() == 0 &&
509  // The SIB byte must be used if the base is ESP/RSP/R12, all of which
510  // encode to an R/M value of 4, which indicates that a SIB byte is
511  // present.
512  BaseRegNo != N86::ESP &&
513  // If there is no base register and we're in 64-bit mode, we need a SIB
514  // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
515  (!is64BitMode(STI) || BaseReg != 0)) {
516 
517  if (BaseReg == 0) { // [disp32] in X86-32 mode
518  EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
519  EmitImmediate(Disp, MI.getLoc(), 4, FK_Data_4, CurByte, OS, Fixups);
520  return;
521  }
522 
523  // If the base is not EBP/ESP and there is no displacement, use simple
524  // indirect register encoding, this handles addresses like [EAX]. The
525  // encoding for [EBP] with no displacement means [disp32] so we handle it
526  // by emitting a displacement of 0 below.
527  if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
528  EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS);
529  return;
530  }
531 
532  // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
533  if (Disp.isImm()) {
534  if (!HasEVEX && isDisp8(Disp.getImm())) {
535  EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
536  EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups);
537  return;
538  }
539  // Try EVEX compressed 8-bit displacement first; if failed, fall back to
540  // 32-bit displacement.
541  int CDisp8 = 0;
542  if (HasEVEX && isCDisp8(TSFlags, Disp.getImm(), CDisp8)) {
543  EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
544  EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups,
545  CDisp8 - Disp.getImm());
546  return;
547  }
548  }
549 
550  // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
551  EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS);
552  unsigned Opcode = MI.getOpcode();
553  unsigned FixupKind = Opcode == X86::MOV32rm ? X86::reloc_signed_4byte_relax
555  EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind), CurByte, OS,
556  Fixups);
557  return;
558  }
559 
560  // We need a SIB byte, so start by outputting the ModR/M byte first
561  assert(IndexReg.getReg() != X86::ESP &&
562  IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
563 
564  bool ForceDisp32 = false;
565  bool ForceDisp8 = false;
566  int CDisp8 = 0;
567  int ImmOffset = 0;
568  if (BaseReg == 0) {
569  // If there is no base register, we emit the special case SIB byte with
570  // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
571  EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
572  ForceDisp32 = true;
573  } else if (!Disp.isImm()) {
574  // Emit the normal disp32 encoding.
575  EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
576  ForceDisp32 = true;
577  } else if (Disp.getImm() == 0 &&
578  // Base reg can't be anything that ends up with '5' as the base
579  // reg, it is the magic [*] nomenclature that indicates no base.
580  BaseRegNo != N86::EBP) {
581  // Emit no displacement ModR/M byte
582  EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
583  } else if (!HasEVEX && isDisp8(Disp.getImm())) {
584  // Emit the disp8 encoding.
585  EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
586  ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
587  } else if (HasEVEX && isCDisp8(TSFlags, Disp.getImm(), CDisp8)) {
588  // Emit the disp8 encoding.
589  EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
590  ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
591  ImmOffset = CDisp8 - Disp.getImm();
592  } else {
593  // Emit the normal disp32 encoding.
594  EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
595  }
596 
597  // Calculate what the SS field value should be...
598  static const unsigned SSTable[] = { ~0U, 0, 1, ~0U, 2, ~0U, ~0U, ~0U, 3 };
599  unsigned SS = SSTable[Scale.getImm()];
600 
601  if (BaseReg == 0) {
602  // Handle the SIB byte for the case where there is no base, see Intel
603  // Manual 2A, table 2-7. The displacement has already been output.
604  unsigned IndexRegNo;
605  if (IndexReg.getReg())
606  IndexRegNo = GetX86RegNum(IndexReg);
607  else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
608  IndexRegNo = 4;
609  EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS);
610  } else {
611  unsigned IndexRegNo;
612  if (IndexReg.getReg())
613  IndexRegNo = GetX86RegNum(IndexReg);
614  else
615  IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
616  EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS);
617  }
618 
619  // Do we need to output a displacement?
620  if (ForceDisp8)
621  EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups, ImmOffset);
622  else if (ForceDisp32 || Disp.getImm() != 0)
623  EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte),
624  CurByte, OS, Fixups);
625 }
626 
627 /// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix
628 /// called VEX.
629 void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
630  int MemOperand, const MCInst &MI,
631  const MCInstrDesc &Desc,
632  raw_ostream &OS) const {
633  assert(!(TSFlags & X86II::LOCK) && "Can't have LOCK VEX.");
634 
635  uint64_t Encoding = TSFlags & X86II::EncodingMask;
636  bool HasEVEX_K = TSFlags & X86II::EVEX_K;
637  bool HasVEX_4V = TSFlags & X86II::VEX_4V;
638  bool HasEVEX_RC = TSFlags & X86II::EVEX_RC;
639 
640  // VEX_R: opcode externsion equivalent to REX.R in
641  // 1's complement (inverted) form
642  //
643  // 1: Same as REX_R=0 (must be 1 in 32-bit mode)
644  // 0: Same as REX_R=1 (64 bit mode only)
645  //
646  uint8_t VEX_R = 0x1;
647  uint8_t EVEX_R2 = 0x1;
648 
649  // VEX_X: equivalent to REX.X, only used when a
650  // register is used for index in SIB Byte.
651  //
652  // 1: Same as REX.X=0 (must be 1 in 32-bit mode)
653  // 0: Same as REX.X=1 (64-bit mode only)
654  uint8_t VEX_X = 0x1;
655 
656  // VEX_B:
657  //
658  // 1: Same as REX_B=0 (ignored in 32-bit mode)
659  // 0: Same as REX_B=1 (64 bit mode only)
660  //
661  uint8_t VEX_B = 0x1;
662 
663  // VEX_W: opcode specific (use like REX.W, or used for
664  // opcode extension, or ignored, depending on the opcode byte)
665  uint8_t VEX_W = (TSFlags & X86II::VEX_W) ? 1 : 0;
666 
667  // VEX_5M (VEX m-mmmmm field):
668  //
669  // 0b00000: Reserved for future use
670  // 0b00001: implied 0F leading opcode
671  // 0b00010: implied 0F 38 leading opcode bytes
672  // 0b00011: implied 0F 3A leading opcode bytes
673  // 0b00100-0b11111: Reserved for future use
674  // 0b01000: XOP map select - 08h instructions with imm byte
675  // 0b01001: XOP map select - 09h instructions with no imm byte
676  // 0b01010: XOP map select - 0Ah instructions with imm dword
677  uint8_t VEX_5M;
678  switch (TSFlags & X86II::OpMapMask) {
679  default: llvm_unreachable("Invalid prefix!");
680  case X86II::TB: VEX_5M = 0x1; break; // 0F
681  case X86II::T8: VEX_5M = 0x2; break; // 0F 38
682  case X86II::TA: VEX_5M = 0x3; break; // 0F 3A
683  case X86II::XOP8: VEX_5M = 0x8; break;
684  case X86II::XOP9: VEX_5M = 0x9; break;
685  case X86II::XOPA: VEX_5M = 0xA; break;
686  }
687 
688  // VEX_4V (VEX vvvv field): a register specifier
689  // (in 1's complement form) or 1111 if unused.
690  uint8_t VEX_4V = 0xf;
691  uint8_t EVEX_V2 = 0x1;
692 
693  // EVEX_L2/VEX_L (Vector Length):
694  //
695  // L2 L
696  // 0 0: scalar or 128-bit vector
697  // 0 1: 256-bit vector
698  // 1 0: 512-bit vector
699  //
700  uint8_t VEX_L = (TSFlags & X86II::VEX_L) ? 1 : 0;
701  uint8_t EVEX_L2 = (TSFlags & X86II::EVEX_L2) ? 1 : 0;
702 
703  // VEX_PP: opcode extension providing equivalent
704  // functionality of a SIMD prefix
705  //
706  // 0b00: None
707  // 0b01: 66
708  // 0b10: F3
709  // 0b11: F2
710  //
711  uint8_t VEX_PP = 0;
712  switch (TSFlags & X86II::OpPrefixMask) {
713  case X86II::PD: VEX_PP = 0x1; break; // 66
714  case X86II::XS: VEX_PP = 0x2; break; // F3
715  case X86II::XD: VEX_PP = 0x3; break; // F2
716  }
717 
718  // EVEX_U
719  uint8_t EVEX_U = 1; // Always '1' so far
720 
721  // EVEX_z
722  uint8_t EVEX_z = (HasEVEX_K && (TSFlags & X86II::EVEX_Z)) ? 1 : 0;
723 
724  // EVEX_b
725  uint8_t EVEX_b = (TSFlags & X86II::EVEX_B) ? 1 : 0;
726 
727  // EVEX_rc
728  uint8_t EVEX_rc = 0;
729 
730  // EVEX_aaa
731  uint8_t EVEX_aaa = 0;
732 
733  bool EncodeRC = false;
734 
735  // Classify VEX_B, VEX_4V, VEX_R, VEX_X
736  unsigned NumOps = Desc.getNumOperands();
737  unsigned CurOp = X86II::getOperandBias(Desc);
738 
739  switch (TSFlags & X86II::FormMask) {
740  default: llvm_unreachable("Unexpected form in EmitVEXOpcodePrefix!");
741  case X86II::RawFrm:
742  break;
743  case X86II::MRMDestMem: {
744  // MRMDestMem instructions forms:
745  // MemAddr, src1(ModR/M)
746  // MemAddr, src1(VEX_4V), src2(ModR/M)
747  // MemAddr, src1(ModR/M), imm8
748  //
749  unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg);
750  VEX_B = ~(BaseRegEnc >> 3) & 1;
751  unsigned IndexRegEnc = getX86RegEncoding(MI, MemOperand+X86::AddrIndexReg);
752  VEX_X = ~(IndexRegEnc >> 3) & 1;
753  if (!HasVEX_4V) // Only needed with VSIB which don't use VVVV.
754  EVEX_V2 = ~(IndexRegEnc >> 4) & 1;
755 
756  CurOp += X86::AddrNumOperands;
757 
758  if (HasEVEX_K)
759  EVEX_aaa = getX86RegEncoding(MI, CurOp++);
760 
761  if (HasVEX_4V) {
762  unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
763  VEX_4V = ~VRegEnc & 0xf;
764  EVEX_V2 = ~(VRegEnc >> 4) & 1;
765  }
766 
767  unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
768  VEX_R = ~(RegEnc >> 3) & 1;
769  EVEX_R2 = ~(RegEnc >> 4) & 1;
770  break;
771  }
772  case X86II::MRMSrcMem: {
773  // MRMSrcMem instructions forms:
774  // src1(ModR/M), MemAddr
775  // src1(ModR/M), src2(VEX_4V), MemAddr
776  // src1(ModR/M), MemAddr, imm8
777  // src1(ModR/M), MemAddr, src2(Imm[7:4])
778  //
779  // FMA4:
780  // dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(Imm[7:4])
781  unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
782  VEX_R = ~(RegEnc >> 3) & 1;
783  EVEX_R2 = ~(RegEnc >> 4) & 1;
784 
785  if (HasEVEX_K)
786  EVEX_aaa = getX86RegEncoding(MI, CurOp++);
787 
788  if (HasVEX_4V) {
789  unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
790  VEX_4V = ~VRegEnc & 0xf;
791  EVEX_V2 = ~(VRegEnc >> 4) & 1;
792  }
793 
794  unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg);
795  VEX_B = ~(BaseRegEnc >> 3) & 1;
796  unsigned IndexRegEnc = getX86RegEncoding(MI, MemOperand+X86::AddrIndexReg);
797  VEX_X = ~(IndexRegEnc >> 3) & 1;
798  if (!HasVEX_4V) // Only needed with VSIB which don't use VVVV.
799  EVEX_V2 = ~(IndexRegEnc >> 4) & 1;
800 
801  break;
802  }
803  case X86II::MRMSrcMem4VOp3: {
804  // Instruction format for 4VOp3:
805  // src1(ModR/M), MemAddr, src3(VEX_4V)
806  unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
807  VEX_R = ~(RegEnc >> 3) & 1;
808 
809  unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg);
810  VEX_B = ~(BaseRegEnc >> 3) & 1;
811  unsigned IndexRegEnc = getX86RegEncoding(MI, MemOperand+X86::AddrIndexReg);
812  VEX_X = ~(IndexRegEnc >> 3) & 1;
813 
814  VEX_4V = ~getX86RegEncoding(MI, CurOp + X86::AddrNumOperands) & 0xf;
815  break;
816  }
817  case X86II::MRMSrcMemOp4: {
818  // dst(ModR/M.reg), src1(VEX_4V), src2(Imm[7:4]), src3(ModR/M),
819  unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
820  VEX_R = ~(RegEnc >> 3) & 1;
821 
822  unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
823  VEX_4V = ~VRegEnc & 0xf;
824 
825  unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg);
826  VEX_B = ~(BaseRegEnc >> 3) & 1;
827  unsigned IndexRegEnc = getX86RegEncoding(MI, MemOperand+X86::AddrIndexReg);
828  VEX_X = ~(IndexRegEnc >> 3) & 1;
829  break;
830  }
831  case X86II::MRM0m: case X86II::MRM1m:
832  case X86II::MRM2m: case X86II::MRM3m:
833  case X86II::MRM4m: case X86II::MRM5m:
834  case X86II::MRM6m: case X86II::MRM7m: {
835  // MRM[0-9]m instructions forms:
836  // MemAddr
837  // src1(VEX_4V), MemAddr
838  if (HasVEX_4V) {
839  unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
840  VEX_4V = ~VRegEnc & 0xf;
841  EVEX_V2 = ~(VRegEnc >> 4) & 1;
842  }
843 
844  if (HasEVEX_K)
845  EVEX_aaa = getX86RegEncoding(MI, CurOp++);
846 
847  unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg);
848  VEX_B = ~(BaseRegEnc >> 3) & 1;
849  unsigned IndexRegEnc = getX86RegEncoding(MI, MemOperand+X86::AddrIndexReg);
850  VEX_X = ~(IndexRegEnc >> 3) & 1;
851  break;
852  }
853  case X86II::MRMSrcReg: {
854  // MRMSrcReg instructions forms:
855  // dst(ModR/M), src1(VEX_4V), src2(ModR/M), src3(Imm[7:4])
856  // dst(ModR/M), src1(ModR/M)
857  // dst(ModR/M), src1(ModR/M), imm8
858  //
859  // FMA4:
860  // dst(ModR/M.reg), src1(VEX_4V), src2(Imm[7:4]), src3(ModR/M),
861  unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
862  VEX_R = ~(RegEnc >> 3) & 1;
863  EVEX_R2 = ~(RegEnc >> 4) & 1;
864 
865  if (HasEVEX_K)
866  EVEX_aaa = getX86RegEncoding(MI, CurOp++);
867 
868  if (HasVEX_4V) {
869  unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
870  VEX_4V = ~VRegEnc & 0xf;
871  EVEX_V2 = ~(VRegEnc >> 4) & 1;
872  }
873 
874  RegEnc = getX86RegEncoding(MI, CurOp++);
875  VEX_B = ~(RegEnc >> 3) & 1;
876  VEX_X = ~(RegEnc >> 4) & 1;
877 
878  if (EVEX_b) {
879  if (HasEVEX_RC) {
880  unsigned RcOperand = NumOps-1;
881  assert(RcOperand >= CurOp);
882  EVEX_rc = MI.getOperand(RcOperand).getImm() & 0x3;
883  }
884  EncodeRC = true;
885  }
886  break;
887  }
888  case X86II::MRMSrcReg4VOp3: {
889  // Instruction format for 4VOp3:
890  // src1(ModR/M), src2(ModR/M), src3(VEX_4V)
891  unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
892  VEX_R = ~(RegEnc >> 3) & 1;
893 
894  RegEnc = getX86RegEncoding(MI, CurOp++);
895  VEX_B = ~(RegEnc >> 3) & 1;
896 
897  VEX_4V = ~getX86RegEncoding(MI, CurOp++) & 0xf;
898  break;
899  }
900  case X86II::MRMSrcRegOp4: {
901  // dst(ModR/M.reg), src1(VEX_4V), src2(Imm[7:4]), src3(ModR/M),
902  unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
903  VEX_R = ~(RegEnc >> 3) & 1;
904 
905  unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
906  VEX_4V = ~VRegEnc & 0xf;
907 
908  // Skip second register source (encoded in Imm[7:4])
909  ++CurOp;
910 
911  RegEnc = getX86RegEncoding(MI, CurOp++);
912  VEX_B = ~(RegEnc >> 3) & 1;
913  VEX_X = ~(RegEnc >> 4) & 1;
914  break;
915  }
916  case X86II::MRMDestReg: {
917  // MRMDestReg instructions forms:
918  // dst(ModR/M), src(ModR/M)
919  // dst(ModR/M), src(ModR/M), imm8
920  // dst(ModR/M), src1(VEX_4V), src2(ModR/M)
921  unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
922  VEX_B = ~(RegEnc >> 3) & 1;
923  VEX_X = ~(RegEnc >> 4) & 1;
924 
925  if (HasEVEX_K)
926  EVEX_aaa = getX86RegEncoding(MI, CurOp++);
927 
928  if (HasVEX_4V) {
929  unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
930  VEX_4V = ~VRegEnc & 0xf;
931  EVEX_V2 = ~(VRegEnc >> 4) & 1;
932  }
933 
934  RegEnc = getX86RegEncoding(MI, CurOp++);
935  VEX_R = ~(RegEnc >> 3) & 1;
936  EVEX_R2 = ~(RegEnc >> 4) & 1;
937  if (EVEX_b)
938  EncodeRC = true;
939  break;
940  }
941  case X86II::MRM0r: case X86II::MRM1r:
942  case X86II::MRM2r: case X86II::MRM3r:
943  case X86II::MRM4r: case X86II::MRM5r:
944  case X86II::MRM6r: case X86II::MRM7r: {
945  // MRM0r-MRM7r instructions forms:
946  // dst(VEX_4V), src(ModR/M), imm8
947  if (HasVEX_4V) {
948  unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
949  VEX_4V = ~VRegEnc & 0xf;
950  EVEX_V2 = ~(VRegEnc >> 4) & 1;
951  }
952  if (HasEVEX_K)
953  EVEX_aaa = getX86RegEncoding(MI, CurOp++);
954 
955  unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
956  VEX_B = ~(RegEnc >> 3) & 1;
957  VEX_X = ~(RegEnc >> 4) & 1;
958  break;
959  }
960  }
961 
962  if (Encoding == X86II::VEX || Encoding == X86II::XOP) {
963  // VEX opcode prefix can have 2 or 3 bytes
964  //
965  // 3 bytes:
966  // +-----+ +--------------+ +-------------------+
967  // | C4h | | RXB | m-mmmm | | W | vvvv | L | pp |
968  // +-----+ +--------------+ +-------------------+
969  // 2 bytes:
970  // +-----+ +-------------------+
971  // | C5h | | R | vvvv | L | pp |
972  // +-----+ +-------------------+
973  //
974  // XOP uses a similar prefix:
975  // +-----+ +--------------+ +-------------------+
976  // | 8Fh | | RXB | m-mmmm | | W | vvvv | L | pp |
977  // +-----+ +--------------+ +-------------------+
978  uint8_t LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3);
979 
980  // Can we use the 2 byte VEX prefix?
981  if (Encoding == X86II::VEX && VEX_B && VEX_X && !VEX_W && (VEX_5M == 1)) {
982  EmitByte(0xC5, CurByte, OS);
983  EmitByte(LastByte | (VEX_R << 7), CurByte, OS);
984  return;
985  }
986 
987  // 3 byte VEX prefix
988  EmitByte(Encoding == X86II::XOP ? 0x8F : 0xC4, CurByte, OS);
989  EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M, CurByte, OS);
990  EmitByte(LastByte | (VEX_W << 7), CurByte, OS);
991  } else {
992  assert(Encoding == X86II::EVEX && "unknown encoding!");
993  // EVEX opcode prefix can have 4 bytes
994  //
995  // +-----+ +--------------+ +-------------------+ +------------------------+
996  // | 62h | | RXBR' | 00mm | | W | vvvv | U | pp | | z | L'L | b | v' | aaa |
997  // +-----+ +--------------+ +-------------------+ +------------------------+
998  assert((VEX_5M & 0x3) == VEX_5M
999  && "More than 2 significant bits in VEX.m-mmmm fields for EVEX!");
1000 
1001  EmitByte(0x62, CurByte, OS);
1002  EmitByte((VEX_R << 7) |
1003  (VEX_X << 6) |
1004  (VEX_B << 5) |
1005  (EVEX_R2 << 4) |
1006  VEX_5M, CurByte, OS);
1007  EmitByte((VEX_W << 7) |
1008  (VEX_4V << 3) |
1009  (EVEX_U << 2) |
1010  VEX_PP, CurByte, OS);
1011  if (EncodeRC)
1012  EmitByte((EVEX_z << 7) |
1013  (EVEX_rc << 5) |
1014  (EVEX_b << 4) |
1015  (EVEX_V2 << 3) |
1016  EVEX_aaa, CurByte, OS);
1017  else
1018  EmitByte((EVEX_z << 7) |
1019  (EVEX_L2 << 6) |
1020  (VEX_L << 5) |
1021  (EVEX_b << 4) |
1022  (EVEX_V2 << 3) |
1023  EVEX_aaa, CurByte, OS);
1024  }
1025 }
1026 
1027 /// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
1028 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
1029 /// size, and 3) use of X86-64 extended registers.
1030 uint8_t X86MCCodeEmitter::DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags,
1031  int MemOperand,
1032  const MCInstrDesc &Desc) const {
1033  uint8_t REX = 0;
1034  bool UsesHighByteReg = false;
1035 
1036  if (TSFlags & X86II::REX_W)
1037  REX |= 1 << 3; // set REX.W
1038 
1039  if (MI.getNumOperands() == 0) return REX;
1040 
1041  unsigned NumOps = MI.getNumOperands();
1042  unsigned CurOp = X86II::getOperandBias(Desc);
1043 
1044  // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
1045  for (unsigned i = CurOp; i != NumOps; ++i) {
1046  const MCOperand &MO = MI.getOperand(i);
1047  if (!MO.isReg()) continue;
1048  unsigned Reg = MO.getReg();
1049  if (Reg == X86::AH || Reg == X86::BH || Reg == X86::CH || Reg == X86::DH)
1050  UsesHighByteReg = true;
1052  // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything
1053  // that returns non-zero.
1054  REX |= 0x40; // REX fixed encoding prefix
1055  }
1056 
1057  switch (TSFlags & X86II::FormMask) {
1058  case X86II::AddRegFrm:
1059  REX |= isREXExtendedReg(MI, CurOp++) << 0; // REX.B
1060  break;
1061  case X86II::MRMSrcReg:
1062  REX |= isREXExtendedReg(MI, CurOp++) << 2; // REX.R
1063  REX |= isREXExtendedReg(MI, CurOp++) << 0; // REX.B
1064  break;
1065  case X86II::MRMSrcMem: {
1066  REX |= isREXExtendedReg(MI, CurOp++) << 2; // REX.R
1067  REX |= isREXExtendedReg(MI, MemOperand+X86::AddrBaseReg) << 0; // REX.B
1068  REX |= isREXExtendedReg(MI, MemOperand+X86::AddrIndexReg) << 1; // REX.X
1069  CurOp += X86::AddrNumOperands;
1070  break;
1071  }
1072  case X86II::MRMDestReg:
1073  REX |= isREXExtendedReg(MI, CurOp++) << 0; // REX.B
1074  REX |= isREXExtendedReg(MI, CurOp++) << 2; // REX.R
1075  break;
1076  case X86II::MRMDestMem:
1077  REX |= isREXExtendedReg(MI, MemOperand+X86::AddrBaseReg) << 0; // REX.B
1078  REX |= isREXExtendedReg(MI, MemOperand+X86::AddrIndexReg) << 1; // REX.X
1079  CurOp += X86::AddrNumOperands;
1080  REX |= isREXExtendedReg(MI, CurOp++) << 2; // REX.R
1081  break;
1082  case X86II::MRMXm:
1083  case X86II::MRM0m: case X86II::MRM1m:
1084  case X86II::MRM2m: case X86II::MRM3m:
1085  case X86II::MRM4m: case X86II::MRM5m:
1086  case X86II::MRM6m: case X86II::MRM7m:
1087  REX |= isREXExtendedReg(MI, MemOperand+X86::AddrBaseReg) << 0; // REX.B
1088  REX |= isREXExtendedReg(MI, MemOperand+X86::AddrIndexReg) << 1; // REX.X
1089  break;
1090  case X86II::MRMXr:
1091  case X86II::MRM0r: case X86II::MRM1r:
1092  case X86II::MRM2r: case X86II::MRM3r:
1093  case X86II::MRM4r: case X86II::MRM5r:
1094  case X86II::MRM6r: case X86II::MRM7r:
1095  REX |= isREXExtendedReg(MI, CurOp++) << 0; // REX.B
1096  break;
1097  }
1098  if (REX && UsesHighByteReg)
1099  report_fatal_error("Cannot encode high byte register in REX-prefixed instruction");
1100 
1101  return REX;
1102 }
1103 
1104 /// EmitSegmentOverridePrefix - Emit segment override opcode prefix as needed
1105 void X86MCCodeEmitter::EmitSegmentOverridePrefix(unsigned &CurByte,
1106  unsigned SegOperand,
1107  const MCInst &MI,
1108  raw_ostream &OS) const {
1109  // Check for explicit segment override on memory operand.
1110  switch (MI.getOperand(SegOperand).getReg()) {
1111  default: llvm_unreachable("Unknown segment register!");
1112  case 0: break;
1113  case X86::CS: EmitByte(0x2E, CurByte, OS); break;
1114  case X86::SS: EmitByte(0x36, CurByte, OS); break;
1115  case X86::DS: EmitByte(0x3E, CurByte, OS); break;
1116  case X86::ES: EmitByte(0x26, CurByte, OS); break;
1117  case X86::FS: EmitByte(0x64, CurByte, OS); break;
1118  case X86::GS: EmitByte(0x65, CurByte, OS); break;
1119  }
1120 }
1121 
1122 /// Emit all instruction prefixes prior to the opcode.
1123 ///
1124 /// MemOperand is the operand # of the start of a memory operand if present. If
1125 /// Not present, it is -1.
1126 ///
1127 /// Returns true if a REX prefix was used.
1128 bool X86MCCodeEmitter::emitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
1129  int MemOperand, const MCInst &MI,
1130  const MCInstrDesc &Desc,
1131  const MCSubtargetInfo &STI,
1132  raw_ostream &OS) const {
1133  bool Ret = false;
1134  // Emit the operand size opcode prefix as needed.
1135  if ((TSFlags & X86II::OpSizeMask) == (is16BitMode(STI) ? X86II::OpSize32
1136  : X86II::OpSize16))
1137  EmitByte(0x66, CurByte, OS);
1138 
1139  // Emit the LOCK opcode prefix.
1140  if (TSFlags & X86II::LOCK || MI.getFlags() & X86::IP_HAS_LOCK)
1141  EmitByte(0xF0, CurByte, OS);
1142 
1143  // Emit the NOTRACK opcode prefix.
1144  if (TSFlags & X86II::NOTRACK || MI.getFlags() & X86::IP_HAS_NOTRACK)
1145  EmitByte(0x3E, CurByte, OS);
1146 
1147  switch (TSFlags & X86II::OpPrefixMask) {
1148  case X86II::PD: // 66
1149  EmitByte(0x66, CurByte, OS);
1150  break;
1151  case X86II::XS: // F3
1152  EmitByte(0xF3, CurByte, OS);
1153  break;
1154  case X86II::XD: // F2
1155  EmitByte(0xF2, CurByte, OS);
1156  break;
1157  }
1158 
1159  // Handle REX prefix.
1160  // FIXME: Can this come before F2 etc to simplify emission?
1161  if (is64BitMode(STI)) {
1162  if (uint8_t REX = DetermineREXPrefix(MI, TSFlags, MemOperand, Desc)) {
1163  EmitByte(0x40 | REX, CurByte, OS);
1164  Ret = true;
1165  }
1166  } else {
1167  assert(!(TSFlags & X86II::REX_W) && "REX.W requires 64bit mode.");
1168  }
1169 
1170  // 0x0F escape code must be emitted just before the opcode.
1171  switch (TSFlags & X86II::OpMapMask) {
1172  case X86II::TB: // Two-byte opcode map
1173  case X86II::T8: // 0F 38
1174  case X86II::TA: // 0F 3A
1175  case X86II::ThreeDNow: // 0F 0F, second 0F emitted by caller.
1176  EmitByte(0x0F, CurByte, OS);
1177  break;
1178  }
1179 
1180  switch (TSFlags & X86II::OpMapMask) {
1181  case X86II::T8: // 0F 38
1182  EmitByte(0x38, CurByte, OS);
1183  break;
1184  case X86II::TA: // 0F 3A
1185  EmitByte(0x3A, CurByte, OS);
1186  break;
1187  }
1188  return Ret;
1189 }
1190 
1191 void X86MCCodeEmitter::
1192 encodeInstruction(const MCInst &MI, raw_ostream &OS,
1193  SmallVectorImpl<MCFixup> &Fixups,
1194  const MCSubtargetInfo &STI) const {
1195  unsigned Opcode = MI.getOpcode();
1196  const MCInstrDesc &Desc = MCII.get(Opcode);
1197  uint64_t TSFlags = Desc.TSFlags;
1198  unsigned Flags = MI.getFlags();
1199 
1200  // Pseudo instructions don't get encoded.
1201  if ((TSFlags & X86II::FormMask) == X86II::Pseudo)
1202  return;
1203 
1204  unsigned NumOps = Desc.getNumOperands();
1205  unsigned CurOp = X86II::getOperandBias(Desc);
1206 
1207  // Keep track of the current byte being emitted.
1208  unsigned CurByte = 0;
1209 
1210  // Encoding type for this instruction.
1211  uint64_t Encoding = TSFlags & X86II::EncodingMask;
1212 
1213  // It uses the VEX.VVVV field?
1214  bool HasVEX_4V = TSFlags & X86II::VEX_4V;
1215  bool HasVEX_I8Reg = (TSFlags & X86II::ImmMask) == X86II::Imm8Reg;
1216 
1217  // It uses the EVEX.aaa field?
1218  bool HasEVEX_K = TSFlags & X86II::EVEX_K;
1219  bool HasEVEX_RC = TSFlags & X86II::EVEX_RC;
1220 
1221  // Used if a register is encoded in 7:4 of immediate.
1222  unsigned I8RegNum = 0;
1223 
1224  // Determine where the memory operand starts, if present.
1225  int MemoryOperand = X86II::getMemoryOperandNo(TSFlags);
1226  if (MemoryOperand != -1) MemoryOperand += CurOp;
1227 
1228  // Emit segment override opcode prefix as needed.
1229  if (MemoryOperand >= 0)
1230  EmitSegmentOverridePrefix(CurByte, MemoryOperand+X86::AddrSegmentReg,
1231  MI, OS);
1232 
1233  // Emit the repeat opcode prefix as needed.
1234  if (TSFlags & X86II::REP || Flags & X86::IP_HAS_REPEAT)
1235  EmitByte(0xF3, CurByte, OS);
1236  if (Flags & X86::IP_HAS_REPEAT_NE)
1237  EmitByte(0xF2, CurByte, OS);
1238 
1239  // Emit the address size opcode prefix as needed.
1240  bool need_address_override;
1241  uint64_t AdSize = TSFlags & X86II::AdSizeMask;
1242  if ((is16BitMode(STI) && AdSize == X86II::AdSize32) ||
1243  (is32BitMode(STI) && AdSize == X86II::AdSize16) ||
1244  (is64BitMode(STI) && AdSize == X86II::AdSize32)) {
1245  need_address_override = true;
1246  } else if (MemoryOperand < 0) {
1247  need_address_override = false;
1248  } else if (is64BitMode(STI)) {
1249  assert(!Is16BitMemOperand(MI, MemoryOperand, STI));
1250  need_address_override = Is32BitMemOperand(MI, MemoryOperand);
1251  } else if (is32BitMode(STI)) {
1252  assert(!Is64BitMemOperand(MI, MemoryOperand));
1253  need_address_override = Is16BitMemOperand(MI, MemoryOperand, STI);
1254  } else {
1255  assert(is16BitMode(STI));
1256  assert(!Is64BitMemOperand(MI, MemoryOperand));
1257  need_address_override = !Is16BitMemOperand(MI, MemoryOperand, STI);
1258  }
1259 
1260  if (need_address_override)
1261  EmitByte(0x67, CurByte, OS);
1262 
1263  bool Rex = false;
1264  if (Encoding == 0)
1265  Rex = emitOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, STI, OS);
1266  else
1267  EmitVEXOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS);
1268 
1269  uint8_t BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
1270 
1271  if ((TSFlags & X86II::OpMapMask) == X86II::ThreeDNow)
1272  BaseOpcode = 0x0F; // Weird 3DNow! encoding.
1273 
1274  uint64_t Form = TSFlags & X86II::FormMask;
1275  switch (Form) {
1276  default: errs() << "FORM: " << Form << "\n";
1277  llvm_unreachable("Unknown FormMask value in X86MCCodeEmitter!");
1278  case X86II::Pseudo:
1279  llvm_unreachable("Pseudo instruction shouldn't be emitted");
1280  case X86II::RawFrmDstSrc: {
1281  unsigned siReg = MI.getOperand(1).getReg();
1282  assert(((siReg == X86::SI && MI.getOperand(0).getReg() == X86::DI) ||
1283  (siReg == X86::ESI && MI.getOperand(0).getReg() == X86::EDI) ||
1284  (siReg == X86::RSI && MI.getOperand(0).getReg() == X86::RDI)) &&
1285  "SI and DI register sizes do not match");
1286  // Emit segment override opcode prefix as needed (not for %ds).
1287  if (MI.getOperand(2).getReg() != X86::DS)
1288  EmitSegmentOverridePrefix(CurByte, 2, MI, OS);
1289  // Emit AdSize prefix as needed.
1290  if ((!is32BitMode(STI) && siReg == X86::ESI) ||
1291  (is32BitMode(STI) && siReg == X86::SI))
1292  EmitByte(0x67, CurByte, OS);
1293  CurOp += 3; // Consume operands.
1294  EmitByte(BaseOpcode, CurByte, OS);
1295  break;
1296  }
1297  case X86II::RawFrmSrc: {
1298  unsigned siReg = MI.getOperand(0).getReg();
1299  // Emit segment override opcode prefix as needed (not for %ds).
1300  if (MI.getOperand(1).getReg() != X86::DS)
1301  EmitSegmentOverridePrefix(CurByte, 1, MI, OS);
1302  // Emit AdSize prefix as needed.
1303  if ((!is32BitMode(STI) && siReg == X86::ESI) ||
1304  (is32BitMode(STI) && siReg == X86::SI))
1305  EmitByte(0x67, CurByte, OS);
1306  CurOp += 2; // Consume operands.
1307  EmitByte(BaseOpcode, CurByte, OS);
1308  break;
1309  }
1310  case X86II::RawFrmDst: {
1311  unsigned siReg = MI.getOperand(0).getReg();
1312  // Emit AdSize prefix as needed.
1313  if ((!is32BitMode(STI) && siReg == X86::EDI) ||
1314  (is32BitMode(STI) && siReg == X86::DI))
1315  EmitByte(0x67, CurByte, OS);
1316  ++CurOp; // Consume operand.
1317  EmitByte(BaseOpcode, CurByte, OS);
1318  break;
1319  }
1320  case X86II::RawFrm: {
1321  EmitByte(BaseOpcode, CurByte, OS);
1322 
1323  if (!is64BitMode(STI) || !isPCRel32Branch(MI))
1324  break;
1325 
1326  const MCOperand &Op = MI.getOperand(CurOp++);
1327  EmitImmediate(Op, MI.getLoc(), X86II::getSizeOfImm(TSFlags),
1329  Fixups);
1330  break;
1331  }
1332  case X86II::RawFrmMemOffs:
1333  // Emit segment override opcode prefix as needed.
1334  EmitSegmentOverridePrefix(CurByte, 1, MI, OS);
1335  EmitByte(BaseOpcode, CurByte, OS);
1336  EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1337  X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1338  CurByte, OS, Fixups);
1339  ++CurOp; // skip segment operand
1340  break;
1341  case X86II::RawFrmImm8:
1342  EmitByte(BaseOpcode, CurByte, OS);
1343  EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1344  X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1345  CurByte, OS, Fixups);
1346  EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1, FK_Data_1, CurByte,
1347  OS, Fixups);
1348  break;
1349  case X86II::RawFrmImm16:
1350  EmitByte(BaseOpcode, CurByte, OS);
1351  EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1352  X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1353  CurByte, OS, Fixups);
1354  EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 2, FK_Data_2, CurByte,
1355  OS, Fixups);
1356  break;
1357 
1358  case X86II::AddRegFrm:
1359  EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS);
1360  break;
1361 
1362  case X86II::MRMDestReg: {
1363  EmitByte(BaseOpcode, CurByte, OS);
1364  unsigned SrcRegNum = CurOp + 1;
1365 
1366  if (HasEVEX_K) // Skip writemask
1367  ++SrcRegNum;
1368 
1369  if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1370  ++SrcRegNum;
1371 
1372  EmitRegModRMByte(MI.getOperand(CurOp),
1373  GetX86RegNum(MI.getOperand(SrcRegNum)), CurByte, OS);
1374  CurOp = SrcRegNum + 1;
1375  break;
1376  }
1377  case X86II::MRMDestMem: {
1378  EmitByte(BaseOpcode, CurByte, OS);
1379  unsigned SrcRegNum = CurOp + X86::AddrNumOperands;
1380 
1381  if (HasEVEX_K) // Skip writemask
1382  ++SrcRegNum;
1383 
1384  if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1385  ++SrcRegNum;
1386 
1387  emitMemModRMByte(MI, CurOp, GetX86RegNum(MI.getOperand(SrcRegNum)), TSFlags,
1388  Rex, CurByte, OS, Fixups, STI);
1389  CurOp = SrcRegNum + 1;
1390  break;
1391  }
1392  case X86II::MRMSrcReg: {
1393  EmitByte(BaseOpcode, CurByte, OS);
1394  unsigned SrcRegNum = CurOp + 1;
1395 
1396  if (HasEVEX_K) // Skip writemask
1397  ++SrcRegNum;
1398 
1399  if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1400  ++SrcRegNum;
1401 
1402  EmitRegModRMByte(MI.getOperand(SrcRegNum),
1403  GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS);
1404  CurOp = SrcRegNum + 1;
1405  if (HasVEX_I8Reg)
1406  I8RegNum = getX86RegEncoding(MI, CurOp++);
1407  // do not count the rounding control operand
1408  if (HasEVEX_RC)
1409  --NumOps;
1410  break;
1411  }
1412  case X86II::MRMSrcReg4VOp3: {
1413  EmitByte(BaseOpcode, CurByte, OS);
1414  unsigned SrcRegNum = CurOp + 1;
1415 
1416  EmitRegModRMByte(MI.getOperand(SrcRegNum),
1417  GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS);
1418  CurOp = SrcRegNum + 1;
1419  ++CurOp; // Encoded in VEX.VVVV
1420  break;
1421  }
1422  case X86II::MRMSrcRegOp4: {
1423  EmitByte(BaseOpcode, CurByte, OS);
1424  unsigned SrcRegNum = CurOp + 1;
1425 
1426  // Skip 1st src (which is encoded in VEX_VVVV)
1427  ++SrcRegNum;
1428 
1429  // Capture 2nd src (which is encoded in Imm[7:4])
1430  assert(HasVEX_I8Reg && "MRMSrcRegOp4 should imply VEX_I8Reg");
1431  I8RegNum = getX86RegEncoding(MI, SrcRegNum++);
1432 
1433  EmitRegModRMByte(MI.getOperand(SrcRegNum),
1434  GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS);
1435  CurOp = SrcRegNum + 1;
1436  break;
1437  }
1438  case X86II::MRMSrcMem: {
1439  unsigned FirstMemOp = CurOp+1;
1440 
1441  if (HasEVEX_K) // Skip writemask
1442  ++FirstMemOp;
1443 
1444  if (HasVEX_4V)
1445  ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
1446 
1447  EmitByte(BaseOpcode, CurByte, OS);
1448 
1449  emitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)),
1450  TSFlags, Rex, CurByte, OS, Fixups, STI);
1451  CurOp = FirstMemOp + X86::AddrNumOperands;
1452  if (HasVEX_I8Reg)
1453  I8RegNum = getX86RegEncoding(MI, CurOp++);
1454  break;
1455  }
1456  case X86II::MRMSrcMem4VOp3: {
1457  unsigned FirstMemOp = CurOp+1;
1458 
1459  EmitByte(BaseOpcode, CurByte, OS);
1460 
1461  emitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)),
1462  TSFlags, Rex, CurByte, OS, Fixups, STI);
1463  CurOp = FirstMemOp + X86::AddrNumOperands;
1464  ++CurOp; // Encoded in VEX.VVVV.
1465  break;
1466  }
1467  case X86II::MRMSrcMemOp4: {
1468  unsigned FirstMemOp = CurOp+1;
1469 
1470  ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
1471 
1472  // Capture second register source (encoded in Imm[7:4])
1473  assert(HasVEX_I8Reg && "MRMSrcRegOp4 should imply VEX_I8Reg");
1474  I8RegNum = getX86RegEncoding(MI, FirstMemOp++);
1475 
1476  EmitByte(BaseOpcode, CurByte, OS);
1477 
1478  emitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)),
1479  TSFlags, Rex, CurByte, OS, Fixups, STI);
1480  CurOp = FirstMemOp + X86::AddrNumOperands;
1481  break;
1482  }
1483 
1484  case X86II::MRMXr:
1485  case X86II::MRM0r: case X86II::MRM1r:
1486  case X86II::MRM2r: case X86II::MRM3r:
1487  case X86II::MRM4r: case X86II::MRM5r:
1488  case X86II::MRM6r: case X86II::MRM7r:
1489  if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
1490  ++CurOp;
1491  if (HasEVEX_K) // Skip writemask
1492  ++CurOp;
1493  EmitByte(BaseOpcode, CurByte, OS);
1494  EmitRegModRMByte(MI.getOperand(CurOp++),
1495  (Form == X86II::MRMXr) ? 0 : Form-X86II::MRM0r,
1496  CurByte, OS);
1497  break;
1498 
1499  case X86II::MRMXm:
1500  case X86II::MRM0m: case X86II::MRM1m:
1501  case X86II::MRM2m: case X86II::MRM3m:
1502  case X86II::MRM4m: case X86II::MRM5m:
1503  case X86II::MRM6m: case X86II::MRM7m:
1504  if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
1505  ++CurOp;
1506  if (HasEVEX_K) // Skip writemask
1507  ++CurOp;
1508  EmitByte(BaseOpcode, CurByte, OS);
1509  emitMemModRMByte(MI, CurOp,
1510  (Form == X86II::MRMXm) ? 0 : Form - X86II::MRM0m, TSFlags,
1511  Rex, CurByte, OS, Fixups, STI);
1512  CurOp += X86::AddrNumOperands;
1513  break;
1514 
1515  case X86II::MRM_C0: case X86II::MRM_C1: case X86II::MRM_C2:
1516  case X86II::MRM_C3: case X86II::MRM_C4: case X86II::MRM_C5:
1517  case X86II::MRM_C6: case X86II::MRM_C7: case X86II::MRM_C8:
1518  case X86II::MRM_C9: case X86II::MRM_CA: case X86II::MRM_CB:
1519  case X86II::MRM_CC: case X86II::MRM_CD: case X86II::MRM_CE:
1520  case X86II::MRM_CF: case X86II::MRM_D0: case X86II::MRM_D1:
1521  case X86II::MRM_D2: case X86II::MRM_D3: case X86II::MRM_D4:
1522  case X86II::MRM_D5: case X86II::MRM_D6: case X86II::MRM_D7:
1523  case X86II::MRM_D8: case X86II::MRM_D9: case X86II::MRM_DA:
1524  case X86II::MRM_DB: case X86II::MRM_DC: case X86II::MRM_DD:
1525  case X86II::MRM_DE: case X86II::MRM_DF: case X86II::MRM_E0:
1526  case X86II::MRM_E1: case X86II::MRM_E2: case X86II::MRM_E3:
1527  case X86II::MRM_E4: case X86II::MRM_E5: case X86II::MRM_E6:
1528  case X86II::MRM_E7: case X86II::MRM_E8: case X86II::MRM_E9:
1529  case X86II::MRM_EA: case X86II::MRM_EB: case X86II::MRM_EC:
1530  case X86II::MRM_ED: case X86II::MRM_EE: case X86II::MRM_EF:
1531  case X86II::MRM_F0: case X86II::MRM_F1: case X86II::MRM_F2:
1532  case X86II::MRM_F3: case X86II::MRM_F4: case X86II::MRM_F5:
1533  case X86II::MRM_F6: case X86II::MRM_F7: case X86II::MRM_F8:
1534  case X86II::MRM_F9: case X86II::MRM_FA: case X86II::MRM_FB:
1535  case X86II::MRM_FC: case X86II::MRM_FD: case X86II::MRM_FE:
1536  case X86II::MRM_FF:
1537  EmitByte(BaseOpcode, CurByte, OS);
1538  EmitByte(0xC0 + Form - X86II::MRM_C0, CurByte, OS);
1539  break;
1540  }
1541 
1542  if (HasVEX_I8Reg) {
1543  // The last source register of a 4 operand instruction in AVX is encoded
1544  // in bits[7:4] of a immediate byte.
1545  assert(I8RegNum < 16 && "Register encoding out of range");
1546  I8RegNum <<= 4;
1547  if (CurOp != NumOps) {
1548  unsigned Val = MI.getOperand(CurOp++).getImm();
1549  assert(Val < 16 && "Immediate operand value out of range");
1550  I8RegNum |= Val;
1551  }
1552  EmitImmediate(MCOperand::createImm(I8RegNum), MI.getLoc(), 1, FK_Data_1,
1553  CurByte, OS, Fixups);
1554  } else {
1555  // If there is a remaining operand, it must be a trailing immediate. Emit it
1556  // according to the right size for the instruction. Some instructions
1557  // (SSE4a extrq and insertq) have two trailing immediates.
1558  while (CurOp != NumOps && NumOps - CurOp <= 2) {
1559  EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1560  X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1561  CurByte, OS, Fixups);
1562  }
1563  }
1564 
1565  if ((TSFlags & X86II::OpMapMask) == X86II::ThreeDNow)
1566  EmitByte(X86II::getBaseOpcodeFor(TSFlags), CurByte, OS);
1567 
1568 #ifndef NDEBUG
1569  // FIXME: Verify.
1570  if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) {
1571  errs() << "Cannot encode all operands of: ";
1572  MI.dump();
1573  errs() << '\n';
1574  abort();
1575  }
1576 #endif
1577 }
1578 
1580  const MCRegisterInfo &MRI,
1581  MCContext &Ctx) {
1582  return new X86MCCodeEmitter(MCII, Ctx);
1583 }
uint64_t CallInst * C
static bool HasSecRelSymbolRef(const MCExpr *Expr)
bool isImm() const
Definition: MCInst.h:58
MRM_XX - A mod/rm byte of exactly 0xXX.
Definition: X86BaseInfo.h:350
static bool Is64BitMemOperand(const MCInst &MI, unsigned Op)
Is64BitMemOperand - Return true if the specified instruction has a 64-bit memory operand.
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
AddrSegmentReg - The operand # of the segment in the memory operand.
Definition: X86BaseInfo.h:38
bool isX86_64NonExtLowByteReg(unsigned reg)
Definition: X86BaseInfo.h:804
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
VariantKind getKind() const
Definition: MCExpr.h:334
static bool isDisp8(int Value)
isDisp8 - Return true if this signed displacement fits in a 8-bit sign-extended field.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned Reg
static GlobalOffsetTableExprKind StartsWithGlobalOffsetTable(const MCExpr *Expr)
bool isReg() const
Definition: MCInst.h:57
const MCExpr * getLHS() const
Get the left-hand side expression of the binary operator.
Definition: MCExpr.h:560
static MCFixupKind getKindForSize(unsigned Size, bool isPCRel)
Return the generic fixup kind for a value with the given size.
Definition: MCFixup.h:131
static Lanai::Fixups FixupKind(const MCExpr *Expr)
unsigned isImmPCRel(uint64_t TSFlags)
isImmPCRel - Return true if the immediate of the specified instruction&#39;s TSFlags indicates that it is...
Definition: X86BaseInfo.h:613
XOP - Opcode prefix used by XOP instructions.
Definition: X86BaseInfo.h:525
A one-byte pc relative fixup.
Definition: MCFixup.h:27
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:210
const FeatureBitset & getFeatureBits() const
MCCodeEmitter * createX86MCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
The access may reference the value stored in memory.
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:165
A four-byte section relative fixup.
Definition: MCFixup.h:41
MRMSrcMem - This form is used for instructions that use the Mod/RM byte to specify a source...
Definition: X86BaseInfo.h:299
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:64
A four-byte fixup.
Definition: MCFixup.h:25
RawFrmDst - This form is for instructions that use the destination index register DI/EDI/RDI...
Definition: X86BaseInfo.h:268
Context object for machine code objects.
Definition: MCContext.h:62
uint8_t getBaseOpcodeFor(uint64_t TSFlags)
Definition: X86BaseInfo.h:586
const MCExpr * getRHS() const
Get the right-hand side expression of the binary operator.
Definition: MCExpr.h:563
const MCExpr * getExpr() const
Definition: MCInst.h:95
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:457
bool hasImm(uint64_t TSFlags)
Definition: X86BaseInfo.h:590
static bool isCDisp8(uint64_t TSFlags, int Value, int &CValue)
isCDisp8 - Return true if this signed displacement fits in a 8-bit compressed dispacement field...
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
int64_t getImm() const
Definition: MCInst.h:75
static MCFixupKind getImmFixupKind(uint64_t TSFlags)
getImmFixupKind - Return the appropriate fixup kind to use for an immediate in an instruction with th...
unsigned const MachineRegisterInfo * MRI
MRMSrcReg - This form is used for instructions that use the Mod/RM byte to specify a source...
Definition: X86BaseInfo.h:328
unsigned getFlags() const
Definition: MCInst.h:174
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:23
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:22
bool isExpr() const
Definition: MCInst.h:60
unsigned getOperandBias(const MCInstrDesc &Desc)
getOperandBias - compute whether all of the def operands are repeated in the uses and therefore shoul...
Definition: X86BaseInfo.h:656
unsigned getNumOperands() const
Definition: MCInst.h:181
MRM[0-7][rm] - These forms are used to represent instructions that use a Mod/RM byte, and use the middle field to hold extended opcode information.
Definition: X86BaseInfo.h:294
unsigned isImmSigned(uint64_t TSFlags)
isImmSigned - Return true if the immediate of the specified instruction&#39;s TSFlags indicates that it i...
Definition: X86BaseInfo.h:632
Binary assembler expressions.
Definition: MCExpr.h:413
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:89
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
A one-byte fixup.
Definition: MCFixup.h:23
static bool Is32BitMemOperand(const MCInst &MI, unsigned Op)
Is32BitMemOperand - Return true if the specified instruction has a 32-bit memory operand.
A two-byte pc relative fixup.
Definition: MCFixup.h:28
void dump() const
Definition: MCInst.cpp:94
A four-byte pc relative fixup.
Definition: MCFixup.h:29
const MCSymbol & getSymbol() const
Definition: MCExpr.h:332
ExprKind getKind() const
Definition: MCExpr.h:72
Raw - This form is for instructions that don&#39;t have any operands, so they are just a fixed opcode val...
Definition: X86BaseInfo.h:252
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:179
AddrNumOperands - Total number of operands in a memory reference.
Definition: X86BaseInfo.h:41
AddRegFrm - This form is used for instructions like &#39;push r32&#39; that have their one register operand a...
Definition: X86BaseInfo.h:256
The access may modify the value stored in memory.
MRMSrcRegOp4 - This form is used for instructions that use the Mod/RM byte to specify the fourth sour...
Definition: X86BaseInfo.h:338
MRMSrcMem4VOp3 - This form is used for instructions that encode operand 3 with VEX.VVVV and load from memory.
Definition: X86BaseInfo.h:304
SMLoc getLoc() const
Definition: MCInst.h:177
RawFrmMemOffs - This form is for instructions that store an absolute memory offset as an immediate wi...
Definition: X86BaseInfo.h:260
MRMSrcMemOp4 - This form is used for instructions that use the Mod/RM byte to specify the fourth sour...
Definition: X86BaseInfo.h:309
MRMDestReg - This form is used for instructions that use the Mod/RM byte to specify a destination...
Definition: X86BaseInfo.h:323
MRMSrcReg4VOp3 - This form is used for instructions that encode operand 3 with VEX.VVVV and do not load from memory.
Definition: X86BaseInfo.h:333
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
unsigned getSizeOfImm(uint64_t TSFlags)
getSizeOfImm - Decode the "size of immediate" field from the TSFlags field of the specified instructi...
Definition: X86BaseInfo.h:596
Generic base class for all target subtargets.
A eight-byte fixup.
Definition: MCFixup.h:26
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:322
References to labels and assigned expressions.
Definition: MCExpr.h:40
uint32_t Size
Definition: Profile.cpp:46
StringRef getName() const
getName - Get the symbol name.
Definition: MCSymbol.h:202
MRMXm - This form is used for instructions that use the Mod/RM byte to specify a memory source...
Definition: X86BaseInfo.h:314
RawFrmSrc - This form is for instructions that use the source index register SI/ESI/RSI with a possib...
Definition: X86BaseInfo.h:264
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
RawFrmDstSrc - This form is for instructions that use the source index register SI/ESI/RSI with a pos...
Definition: X86BaseInfo.h:273
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:294
LLVM Value Representation.
Definition: Value.h:72
Binary expressions.
Definition: MCExpr.h:38
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
MRMXr - This form is used for instructions that use the Mod/RM byte to specify a register source...
Definition: X86BaseInfo.h:343
GlobalOffsetTableExprKind
StartsWithGlobalOffsetTable - Check if this expression starts with GLOBAL_OFFSET_TABLE and if it is o...
IRTranslator LLVM IR MI
static bool isPCRel(unsigned Kind)
Represents a location in source code.
Definition: SMLoc.h:23
unsigned getOpcode() const
Definition: MCInst.h:171
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:34
ThreeDNow - This indicates that the instruction uses the wacky 0x0F 0x0F prefix for 3DNow! instructio...
Definition: X86BaseInfo.h:443
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:122
RawFrmImm16 - This is used for CALL FAR instructions, which have two immediates, the first of which i...
Definition: X86BaseInfo.h:284
A two-byte fixup.
Definition: MCFixup.h:24
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx)
Definition: MCExpr.cpp:163
RawFrmImm8 - This is used for the ENTER instruction, which has two immediates, the first of which is ...
Definition: X86BaseInfo.h:278
int getMemoryOperandNo(uint64_t TSFlags)
getMemoryOperandNo - The function returns the MCInst operand # for the first field of the memory oper...
Definition: X86BaseInfo.h:697