LLVM 19.0.0git
X86MCCodeEmitter.cpp
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1//===-- X86MCCodeEmitter.cpp - Convert X86 code to machine code -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the X86MCCodeEmitter class.
10//
11//===----------------------------------------------------------------------===//
12
18#include "llvm/MC/MCContext.h"
19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCFixup.h"
21#include "llvm/MC/MCInst.h"
22#include "llvm/MC/MCInstrDesc.h"
23#include "llvm/MC/MCInstrInfo.h"
26#include "llvm/MC/MCSymbol.h"
29#include <cassert>
30#include <cstdint>
31#include <cstdlib>
32
33using namespace llvm;
34
35#define DEBUG_TYPE "mccodeemitter"
36
37namespace {
38
39enum PrefixKind { None, REX, REX2, XOP, VEX2, VEX3, EVEX };
40
41static void emitByte(uint8_t C, SmallVectorImpl<char> &CB) { CB.push_back(C); }
42
43class X86OpcodePrefixHelper {
44 // REX (1 byte)
45 // +-----+ +------+
46 // | 40H | | WRXB |
47 // +-----+ +------+
48
49 // REX2 (2 bytes)
50 // +-----+ +-------------------+
51 // | D5H | | M | R'X'B' | WRXB |
52 // +-----+ +-------------------+
53
54 // XOP (3-byte)
55 // +-----+ +--------------+ +-------------------+
56 // | 8Fh | | RXB | m-mmmm | | W | vvvv | L | pp |
57 // +-----+ +--------------+ +-------------------+
58
59 // VEX2 (2 bytes)
60 // +-----+ +-------------------+
61 // | C5h | | R | vvvv | L | pp |
62 // +-----+ +-------------------+
63
64 // VEX3 (3 bytes)
65 // +-----+ +--------------+ +-------------------+
66 // | C4h | | RXB | m-mmmm | | W | vvvv | L | pp |
67 // +-----+ +--------------+ +-------------------+
68
69 // VEX_R: opcode externsion equivalent to REX.R in
70 // 1's complement (inverted) form
71 //
72 // 1: Same as REX_R=0 (must be 1 in 32-bit mode)
73 // 0: Same as REX_R=1 (64 bit mode only)
74
75 // VEX_X: equivalent to REX.X, only used when a
76 // register is used for index in SIB Byte.
77 //
78 // 1: Same as REX.X=0 (must be 1 in 32-bit mode)
79 // 0: Same as REX.X=1 (64-bit mode only)
80
81 // VEX_B:
82 // 1: Same as REX_B=0 (ignored in 32-bit mode)
83 // 0: Same as REX_B=1 (64 bit mode only)
84
85 // VEX_W: opcode specific (use like REX.W, or used for
86 // opcode extension, or ignored, depending on the opcode byte)
87
88 // VEX_5M (VEX m-mmmmm field):
89 //
90 // 0b00000: Reserved for future use
91 // 0b00001: implied 0F leading opcode
92 // 0b00010: implied 0F 38 leading opcode bytes
93 // 0b00011: implied 0F 3A leading opcode bytes
94 // 0b00100: Reserved for future use
95 // 0b00101: VEX MAP5
96 // 0b00110: VEX MAP6
97 // 0b00111: VEX MAP7
98 // 0b00111-0b11111: Reserved for future use
99 // 0b01000: XOP map select - 08h instructions with imm byte
100 // 0b01001: XOP map select - 09h instructions with no imm byte
101 // 0b01010: XOP map select - 0Ah instructions with imm dword
102
103 // VEX_4V (VEX vvvv field): a register specifier
104 // (in 1's complement form) or 1111 if unused.
105
106 // VEX_PP: opcode extension providing equivalent
107 // functionality of a SIMD prefix
108 // 0b00: None
109 // 0b01: 66
110 // 0b10: F3
111 // 0b11: F2
112
113 // EVEX (4 bytes)
114 // +-----+ +---------------+ +--------------------+ +------------------------+
115 // | 62h | | RXBR' | B'mmm | | W | vvvv | X' | pp | | z | L'L | b | v' | aaa |
116 // +-----+ +---------------+ +--------------------+ +------------------------+
117
118 // EVEX_L2/VEX_L (Vector Length):
119 // L2 L
120 // 0 0: scalar or 128-bit vector
121 // 0 1: 256-bit vector
122 // 1 0: 512-bit vector
123
124 // 32-Register Support in 64-bit Mode Using EVEX with Embedded REX/REX2 Bits:
125 //
126 // +----------+---------+--------+-----------+---------+--------------+
127 // | | 4 | 3 | [2:0] | Type | Common Usage |
128 // +----------+---------+--------+-----------+---------+--------------+
129 // | REG | EVEX_R' | EVEX_R | modrm.reg | GPR, VR | Dest or Src |
130 // | VVVV | EVEX_v' | EVEX.vvvv | GPR, VR | Dest or Src |
131 // | RM (VR) | EVEX_X | EVEX_B | modrm.r/m | VR | Dest or Src |
132 // | RM (GPR) | EVEX_B' | EVEX_B | modrm.r/m | GPR | Dest or Src |
133 // | BASE | EVEX_B' | EVEX_B | modrm.r/m | GPR | MA |
134 // | INDEX | EVEX_X' | EVEX_X | sib.index | GPR | MA |
135 // | VIDX | EVEX_v' | EVEX_X | sib.index | VR | VSIB MA |
136 // +----------+---------+--------+-----------+---------+--------------+
137 //
138 // * GPR - General-purpose register
139 // * VR - Vector register
140 // * VIDX - Vector index
141 // * VSIB - Vector SIB
142 // * MA - Memory addressing
143
144private:
145 unsigned W : 1;
146 unsigned R : 1;
147 unsigned X : 1;
148 unsigned B : 1;
149 unsigned M : 1;
150 unsigned R2 : 1;
151 unsigned X2 : 1;
152 unsigned B2 : 1;
153 unsigned VEX_4V : 4;
154 unsigned VEX_L : 1;
155 unsigned VEX_PP : 2;
156 unsigned VEX_5M : 5;
157 unsigned EVEX_z : 1;
158 unsigned EVEX_L2 : 1;
159 unsigned EVEX_b : 1;
160 unsigned EVEX_V2 : 1;
161 unsigned EVEX_aaa : 3;
162 PrefixKind Kind = None;
163 const MCRegisterInfo &MRI;
164
165 unsigned getRegEncoding(const MCInst &MI, unsigned OpNum) const {
166 return MRI.getEncodingValue(MI.getOperand(OpNum).getReg());
167 }
168
169 void setR(unsigned Encoding) { R = Encoding >> 3 & 1; }
170 void setR2(unsigned Encoding) {
171 R2 = Encoding >> 4 & 1;
172 assert((!R2 || (Kind <= REX2 || Kind == EVEX)) && "invalid setting");
173 }
174 void setX(unsigned Encoding) { X = Encoding >> 3 & 1; }
175 void setX2(unsigned Encoding) {
176 assert((Kind <= REX2 || Kind == EVEX) && "invalid setting");
177 X2 = Encoding >> 4 & 1;
178 }
179 void setB(unsigned Encoding) { B = Encoding >> 3 & 1; }
180 void setB2(unsigned Encoding) {
181 assert((Kind <= REX2 || Kind == EVEX) && "invalid setting");
182 B2 = Encoding >> 4 & 1;
183 }
184 void set4V(unsigned Encoding) { VEX_4V = Encoding & 0xf; }
185 void setV2(unsigned Encoding) { EVEX_V2 = Encoding >> 4 & 1; }
186
187public:
188 void setW(bool V) { W = V; }
189 void setR(const MCInst &MI, unsigned OpNum) {
190 setR(getRegEncoding(MI, OpNum));
191 }
192 void setX(const MCInst &MI, unsigned OpNum, unsigned Shift = 3) {
193 unsigned Reg = MI.getOperand(OpNum).getReg();
194 // X is used to extend vector register only when shift is not 3.
195 if (Shift != 3 && X86II::isApxExtendedReg(Reg))
196 return;
197 unsigned Encoding = MRI.getEncodingValue(Reg);
198 X = Encoding >> Shift & 1;
199 }
200 void setB(const MCInst &MI, unsigned OpNum) {
201 B = getRegEncoding(MI, OpNum) >> 3 & 1;
202 }
203 void set4V(const MCInst &MI, unsigned OpNum, bool IsImm = false) {
204 // OF, SF, ZF and CF reuse VEX_4V bits but are not reversed
205 if (IsImm)
206 set4V(~(MI.getOperand(OpNum).getImm()));
207 else
208 set4V(getRegEncoding(MI, OpNum));
209 }
210 void setL(bool V) { VEX_L = V; }
211 void setPP(unsigned V) { VEX_PP = V; }
212 void set5M(unsigned V) { VEX_5M = V; }
213 void setR2(const MCInst &MI, unsigned OpNum) {
214 setR2(getRegEncoding(MI, OpNum));
215 }
216 void setRR2(const MCInst &MI, unsigned OpNum) {
217 unsigned Encoding = getRegEncoding(MI, OpNum);
218 setR(Encoding);
219 setR2(Encoding);
220 }
221 void setM(bool V) { M = V; }
222 void setXX2(const MCInst &MI, unsigned OpNum) {
223 unsigned Reg = MI.getOperand(OpNum).getReg();
224 unsigned Encoding = MRI.getEncodingValue(Reg);
225 setX(Encoding);
226 // Index can be a vector register while X2 is used to extend GPR only.
227 if (Kind <= REX2 || X86II::isApxExtendedReg(Reg))
228 setX2(Encoding);
229 }
230 void setBB2(const MCInst &MI, unsigned OpNum) {
231 unsigned Reg = MI.getOperand(OpNum).getReg();
232 unsigned Encoding = MRI.getEncodingValue(Reg);
233 setB(Encoding);
234 // Base can be a vector register while B2 is used to extend GPR only
235 if (Kind <= REX2 || X86II::isApxExtendedReg(Reg))
236 setB2(Encoding);
237 }
238 void setZ(bool V) { EVEX_z = V; }
239 void setL2(bool V) { EVEX_L2 = V; }
240 void setEVEX_b(bool V) { EVEX_b = V; }
241 void setV2(const MCInst &MI, unsigned OpNum, bool HasVEX_4V) {
242 // Only needed with VSIB which don't use VVVV.
243 if (HasVEX_4V)
244 return;
245 unsigned Reg = MI.getOperand(OpNum).getReg();
247 return;
248 setV2(MRI.getEncodingValue(Reg));
249 }
250 void set4VV2(const MCInst &MI, unsigned OpNum) {
251 unsigned Encoding = getRegEncoding(MI, OpNum);
252 set4V(Encoding);
253 setV2(Encoding);
254 }
255 void setAAA(const MCInst &MI, unsigned OpNum) {
256 EVEX_aaa = getRegEncoding(MI, OpNum);
257 }
258 void setNF(bool V) { EVEX_aaa |= V << 2; }
259 void setSC(const MCInst &MI, unsigned OpNum) {
260 unsigned Encoding = MI.getOperand(OpNum).getImm();
261 EVEX_V2 = ~(Encoding >> 3) & 0x1;
262 EVEX_aaa = Encoding & 0x7;
263 }
264
265 X86OpcodePrefixHelper(const MCRegisterInfo &MRI)
266 : W(0), R(0), X(0), B(0), M(0), R2(0), X2(0), B2(0), VEX_4V(0), VEX_L(0),
267 VEX_PP(0), VEX_5M(0), EVEX_z(0), EVEX_L2(0), EVEX_b(0), EVEX_V2(0),
268 EVEX_aaa(0), MRI(MRI) {}
269
270 void setLowerBound(PrefixKind K) { Kind = K; }
271
272 PrefixKind determineOptimalKind() {
273 switch (Kind) {
274 case None:
275 // Not M bit here by intention b/c
276 // 1. No guarantee that REX2 is supported by arch w/o explict EGPR
277 // 2. REX2 is longer than 0FH
278 Kind = (R2 | X2 | B2) ? REX2 : (W | R | X | B) ? REX : None;
279 break;
280 case REX:
281 Kind = (R2 | X2 | B2) ? REX2 : REX;
282 break;
283 case REX2:
284 case XOP:
285 case VEX3:
286 case EVEX:
287 break;
288 case VEX2:
289 Kind = (W | X | B | (VEX_5M != 1)) ? VEX3 : VEX2;
290 break;
291 }
292 return Kind;
293 }
294
295 void emit(SmallVectorImpl<char> &CB) const {
296 uint8_t FirstPayload =
297 ((~R) & 0x1) << 7 | ((~X) & 0x1) << 6 | ((~B) & 0x1) << 5;
298 uint8_t LastPayload = ((~VEX_4V) & 0xf) << 3 | VEX_L << 2 | VEX_PP;
299 switch (Kind) {
300 case None:
301 return;
302 case REX:
303 emitByte(0x40 | W << 3 | R << 2 | X << 1 | B, CB);
304 return;
305 case REX2:
306 emitByte(0xD5, CB);
307 emitByte(M << 7 | R2 << 6 | X2 << 5 | B2 << 4 | W << 3 | R << 2 | X << 1 |
308 B,
309 CB);
310 return;
311 case VEX2:
312 emitByte(0xC5, CB);
313 emitByte(((~R) & 1) << 7 | LastPayload, CB);
314 return;
315 case VEX3:
316 case XOP:
317 emitByte(Kind == VEX3 ? 0xC4 : 0x8F, CB);
318 emitByte(FirstPayload | VEX_5M, CB);
319 emitByte(W << 7 | LastPayload, CB);
320 return;
321 case EVEX:
322 assert(VEX_5M && !(VEX_5M & 0x8) && "invalid mmm fields for EVEX!");
323 emitByte(0x62, CB);
324 emitByte(FirstPayload | ((~R2) & 0x1) << 4 | B2 << 3 | VEX_5M, CB);
325 emitByte(W << 7 | ((~VEX_4V) & 0xf) << 3 | ((~X2) & 0x1) << 2 | VEX_PP,
326 CB);
327 emitByte(EVEX_z << 7 | EVEX_L2 << 6 | VEX_L << 5 | EVEX_b << 4 |
328 ((~EVEX_V2) & 0x1) << 3 | EVEX_aaa,
329 CB);
330 return;
331 }
332 }
333};
334
335class X86MCCodeEmitter : public MCCodeEmitter {
336 const MCInstrInfo &MCII;
337 MCContext &Ctx;
338
339public:
340 X86MCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
341 : MCII(mcii), Ctx(ctx) {}
342 X86MCCodeEmitter(const X86MCCodeEmitter &) = delete;
343 X86MCCodeEmitter &operator=(const X86MCCodeEmitter &) = delete;
344 ~X86MCCodeEmitter() override = default;
345
346 void emitPrefix(const MCInst &MI, SmallVectorImpl<char> &CB,
347 const MCSubtargetInfo &STI) const override;
348
351 const MCSubtargetInfo &STI) const override;
352
353private:
354 unsigned getX86RegNum(const MCOperand &MO) const;
355
356 unsigned getX86RegEncoding(const MCInst &MI, unsigned OpNum) const;
357
358 void emitImmediate(const MCOperand &Disp, SMLoc Loc, unsigned ImmSize,
359 MCFixupKind FixupKind, uint64_t StartByte,
361 SmallVectorImpl<MCFixup> &Fixups, int ImmOffset = 0) const;
362
363 void emitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
364 SmallVectorImpl<char> &CB) const;
365
366 void emitSIBByte(unsigned SS, unsigned Index, unsigned Base,
367 SmallVectorImpl<char> &CB) const;
368
369 void emitMemModRMByte(const MCInst &MI, unsigned Op, unsigned RegOpcodeField,
370 uint64_t TSFlags, PrefixKind Kind, uint64_t StartByte,
373 const MCSubtargetInfo &STI,
374 bool ForceSIB = false) const;
375
376 PrefixKind emitPrefixImpl(unsigned &CurOp, const MCInst &MI,
377 const MCSubtargetInfo &STI,
378 SmallVectorImpl<char> &CB) const;
379
380 PrefixKind emitVEXOpcodePrefix(int MemOperand, const MCInst &MI,
381 const MCSubtargetInfo &STI,
382 SmallVectorImpl<char> &CB) const;
383
384 void emitSegmentOverridePrefix(unsigned SegOperand, const MCInst &MI,
385 SmallVectorImpl<char> &CB) const;
386
387 PrefixKind emitOpcodePrefix(int MemOperand, const MCInst &MI,
388 const MCSubtargetInfo &STI,
389 SmallVectorImpl<char> &CB) const;
390
391 PrefixKind emitREXPrefix(int MemOperand, const MCInst &MI,
392 const MCSubtargetInfo &STI,
393 SmallVectorImpl<char> &CB) const;
394};
395
396} // end anonymous namespace
397
398static uint8_t modRMByte(unsigned Mod, unsigned RegOpcode, unsigned RM) {
399 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
400 return RM | (RegOpcode << 3) | (Mod << 6);
401}
402
403static void emitConstant(uint64_t Val, unsigned Size,
405 // Output the constant in little endian byte order.
406 for (unsigned i = 0; i != Size; ++i) {
407 emitByte(Val & 255, CB);
408 Val >>= 8;
409 }
410}
411
412/// Determine if this immediate can fit in a disp8 or a compressed disp8 for
413/// EVEX instructions. \p will be set to the value to pass to the ImmOffset
414/// parameter of emitImmediate.
415static bool isDispOrCDisp8(uint64_t TSFlags, int Value, int &ImmOffset) {
416 bool HasEVEX = (TSFlags & X86II::EncodingMask) == X86II::EVEX;
417
418 unsigned CD8_Scale =
420 CD8_Scale = CD8_Scale ? 1U << (CD8_Scale - 1) : 0U;
421 if (!HasEVEX || !CD8_Scale)
422 return isInt<8>(Value);
423
424 assert(isPowerOf2_32(CD8_Scale) && "Unexpected CD8 scale!");
425 if (Value & (CD8_Scale - 1)) // Unaligned offset
426 return false;
427
428 int CDisp8 = Value / static_cast<int>(CD8_Scale);
429 if (!isInt<8>(CDisp8))
430 return false;
431
432 // ImmOffset will be added to Value in emitImmediate leaving just CDisp8.
433 ImmOffset = CDisp8 - Value;
434 return true;
435}
436
437/// \returns the appropriate fixup kind to use for an immediate in an
438/// instruction with the specified TSFlags.
440 unsigned Size = X86II::getSizeOfImm(TSFlags);
441 bool isPCRel = X86II::isImmPCRel(TSFlags);
442
443 if (X86II::isImmSigned(TSFlags)) {
444 switch (Size) {
445 default:
446 llvm_unreachable("Unsupported signed fixup size!");
447 case 4:
449 }
450 }
452}
453
455
456/// Check if this expression starts with _GLOBAL_OFFSET_TABLE_ and if it is
457/// of the form _GLOBAL_OFFSET_TABLE_-symbol. This is needed to support PIC on
458/// ELF i386 as _GLOBAL_OFFSET_TABLE_ is magical. We check only simple case that
459/// are know to be used: _GLOBAL_OFFSET_TABLE_ by itself or at the start of a
460/// binary expression.
463 const MCExpr *RHS = nullptr;
464 if (Expr->getKind() == MCExpr::Binary) {
465 const MCBinaryExpr *BE = static_cast<const MCBinaryExpr *>(Expr);
466 Expr = BE->getLHS();
467 RHS = BE->getRHS();
468 }
469
470 if (Expr->getKind() != MCExpr::SymbolRef)
471 return GOT_None;
472
473 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr *>(Expr);
474 const MCSymbol &S = Ref->getSymbol();
475 if (S.getName() != "_GLOBAL_OFFSET_TABLE_")
476 return GOT_None;
477 if (RHS && RHS->getKind() == MCExpr::SymbolRef)
478 return GOT_SymDiff;
479 return GOT_Normal;
480}
481
482static bool hasSecRelSymbolRef(const MCExpr *Expr) {
483 if (Expr->getKind() == MCExpr::SymbolRef) {
484 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr *>(Expr);
485 return Ref->getKind() == MCSymbolRefExpr::VK_SECREL;
486 }
487 return false;
488}
489
490static bool isPCRel32Branch(const MCInst &MI, const MCInstrInfo &MCII) {
491 unsigned Opcode = MI.getOpcode();
492 const MCInstrDesc &Desc = MCII.get(Opcode);
493 if ((Opcode != X86::CALL64pcrel32 && Opcode != X86::JMP_4 &&
494 Opcode != X86::JCC_4) ||
495 getImmFixupKind(Desc.TSFlags) != FK_PCRel_4)
496 return false;
497
498 unsigned CurOp = X86II::getOperandBias(Desc);
499 const MCOperand &Op = MI.getOperand(CurOp);
500 if (!Op.isExpr())
501 return false;
502
503 const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(Op.getExpr());
504 return Ref && Ref->getKind() == MCSymbolRefExpr::VK_None;
505}
506
507unsigned X86MCCodeEmitter::getX86RegNum(const MCOperand &MO) const {
508 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()) & 0x7;
509}
510
511unsigned X86MCCodeEmitter::getX86RegEncoding(const MCInst &MI,
512 unsigned OpNum) const {
513 return Ctx.getRegisterInfo()->getEncodingValue(MI.getOperand(OpNum).getReg());
514}
515
516void X86MCCodeEmitter::emitImmediate(const MCOperand &DispOp, SMLoc Loc,
517 unsigned Size, MCFixupKind FixupKind,
518 uint64_t StartByte,
521 int ImmOffset) const {
522 const MCExpr *Expr = nullptr;
523 if (DispOp.isImm()) {
524 // If this is a simple integer displacement that doesn't require a
525 // relocation, emit it now.
526 if (FixupKind != FK_PCRel_1 && FixupKind != FK_PCRel_2 &&
527 FixupKind != FK_PCRel_4) {
528 emitConstant(DispOp.getImm() + ImmOffset, Size, CB);
529 return;
530 }
531 Expr = MCConstantExpr::create(DispOp.getImm(), Ctx);
532 } else {
533 Expr = DispOp.getExpr();
534 }
535
536 // If we have an immoffset, add it to the expression.
537 if ((FixupKind == FK_Data_4 || FixupKind == FK_Data_8 ||
538 FixupKind == MCFixupKind(X86::reloc_signed_4byte))) {
540 if (Kind != GOT_None) {
541 assert(ImmOffset == 0);
542
543 if (Size == 8) {
545 } else {
546 assert(Size == 4);
548 }
549
550 if (Kind == GOT_Normal)
551 ImmOffset = static_cast<int>(CB.size() - StartByte);
552 } else if (Expr->getKind() == MCExpr::SymbolRef) {
553 if (hasSecRelSymbolRef(Expr)) {
555 }
556 } else if (Expr->getKind() == MCExpr::Binary) {
557 const MCBinaryExpr *Bin = static_cast<const MCBinaryExpr *>(Expr);
558 if (hasSecRelSymbolRef(Bin->getLHS()) ||
559 hasSecRelSymbolRef(Bin->getRHS())) {
561 }
562 }
563 }
564
565 // If the fixup is pc-relative, we need to bias the value to be relative to
566 // the start of the field, not the end of the field.
567 if (FixupKind == FK_PCRel_4 ||
568 FixupKind == MCFixupKind(X86::reloc_riprel_4byte) ||
573 ImmOffset -= 4;
574 // If this is a pc-relative load off _GLOBAL_OFFSET_TABLE_:
575 // leaq _GLOBAL_OFFSET_TABLE_(%rip), %r15
576 // this needs to be a GOTPC32 relocation.
579 }
580 if (FixupKind == FK_PCRel_2)
581 ImmOffset -= 2;
582 if (FixupKind == FK_PCRel_1)
583 ImmOffset -= 1;
584
585 if (ImmOffset)
586 Expr = MCBinaryExpr::createAdd(Expr, MCConstantExpr::create(ImmOffset, Ctx),
587 Ctx);
588
589 // Emit a symbolic constant as a fixup and 4 zeros.
590 Fixups.push_back(MCFixup::create(static_cast<uint32_t>(CB.size() - StartByte),
591 Expr, FixupKind, Loc));
592 emitConstant(0, Size, CB);
593}
594
595void X86MCCodeEmitter::emitRegModRMByte(const MCOperand &ModRMReg,
596 unsigned RegOpcodeFld,
597 SmallVectorImpl<char> &CB) const {
598 emitByte(modRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)), CB);
599}
600
601void X86MCCodeEmitter::emitSIBByte(unsigned SS, unsigned Index, unsigned Base,
602 SmallVectorImpl<char> &CB) const {
603 // SIB byte is in the same format as the modRMByte.
604 emitByte(modRMByte(SS, Index, Base), CB);
605}
606
607void X86MCCodeEmitter::emitMemModRMByte(
608 const MCInst &MI, unsigned Op, unsigned RegOpcodeField, uint64_t TSFlags,
609 PrefixKind Kind, uint64_t StartByte, SmallVectorImpl<char> &CB,
610 SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI,
611 bool ForceSIB) const {
612 const MCOperand &Disp = MI.getOperand(Op + X86::AddrDisp);
613 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg);
614 const MCOperand &Scale = MI.getOperand(Op + X86::AddrScaleAmt);
615 const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg);
616 unsigned BaseReg = Base.getReg();
617
618 // Handle %rip relative addressing.
619 if (BaseReg == X86::RIP ||
620 BaseReg == X86::EIP) { // [disp32+rIP] in X86-64 mode
621 assert(STI.hasFeature(X86::Is64Bit) &&
622 "Rip-relative addressing requires 64-bit mode");
623 assert(IndexReg.getReg() == 0 && !ForceSIB &&
624 "Invalid rip-relative address");
625 emitByte(modRMByte(0, RegOpcodeField, 5), CB);
626
627 unsigned Opcode = MI.getOpcode();
628 unsigned FixupKind = [&]() {
629 // Enable relaxed relocation only for a MCSymbolRefExpr. We cannot use a
630 // relaxed relocation if an offset is present (e.g. x@GOTPCREL+4).
631 if (!(Disp.isExpr() && isa<MCSymbolRefExpr>(Disp.getExpr())))
633
634 // Certain loads for GOT references can be relocated against the symbol
635 // directly if the symbol ends up in the same linkage unit.
636 switch (Opcode) {
637 default:
639 case X86::MOV64rm:
640 // movq loads is a subset of reloc_riprel_4byte_relax_rex. It is a
641 // special case because COFF and Mach-O don't support ELF's more
642 // flexible R_X86_64_REX_GOTPCRELX relaxation.
643 // TODO: Support new relocation for REX2.
644 assert(Kind == REX || Kind == REX2);
646 case X86::ADC32rm:
647 case X86::ADD32rm:
648 case X86::AND32rm:
649 case X86::CMP32rm:
650 case X86::MOV32rm:
651 case X86::OR32rm:
652 case X86::SBB32rm:
653 case X86::SUB32rm:
654 case X86::TEST32mr:
655 case X86::XOR32rm:
656 case X86::CALL64m:
657 case X86::JMP64m:
658 case X86::TAILJMPm64:
659 case X86::TEST64mr:
660 case X86::ADC64rm:
661 case X86::ADD64rm:
662 case X86::AND64rm:
663 case X86::CMP64rm:
664 case X86::OR64rm:
665 case X86::SBB64rm:
666 case X86::SUB64rm:
667 case X86::XOR64rm:
668 // We haven't support relocation for REX2 prefix, so temporarily use REX
669 // relocation.
670 // TODO: Support new relocation for REX2.
671 return (Kind == REX || Kind == REX2) ? X86::reloc_riprel_4byte_relax_rex
673 }
674 }();
675
676 // rip-relative addressing is actually relative to the *next* instruction.
677 // Since an immediate can follow the mod/rm byte for an instruction, this
678 // means that we need to bias the displacement field of the instruction with
679 // the size of the immediate field. If we have this case, add it into the
680 // expression to emit.
681 // Note: rip-relative addressing using immediate displacement values should
682 // not be adjusted, assuming it was the user's intent.
683 int ImmSize = !Disp.isImm() && X86II::hasImm(TSFlags)
684 ? X86II::getSizeOfImm(TSFlags)
685 : 0;
686
687 emitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind), StartByte, CB,
688 Fixups, -ImmSize);
689 return;
690 }
691
692 unsigned BaseRegNo = BaseReg ? getX86RegNum(Base) : -1U;
693
694 // 16-bit addressing forms of the ModR/M byte have a different encoding for
695 // the R/M field and are far more limited in which registers can be used.
696 if (X86_MC::is16BitMemOperand(MI, Op, STI)) {
697 if (BaseReg) {
698 // For 32-bit addressing, the row and column values in Table 2-2 are
699 // basically the same. It's AX/CX/DX/BX/SP/BP/SI/DI in that order, with
700 // some special cases. And getX86RegNum reflects that numbering.
701 // For 16-bit addressing it's more fun, as shown in the SDM Vol 2A,
702 // Table 2-1 "16-Bit Addressing Forms with the ModR/M byte". We can only
703 // use SI/DI/BP/BX, which have "row" values 4-7 in no particular order,
704 // while values 0-3 indicate the allowed combinations (base+index) of
705 // those: 0 for BX+SI, 1 for BX+DI, 2 for BP+SI, 3 for BP+DI.
706 //
707 // R16Table[] is a lookup from the normal RegNo, to the row values from
708 // Table 2-1 for 16-bit addressing modes. Where zero means disallowed.
709 static const unsigned R16Table[] = {0, 0, 0, 7, 0, 6, 4, 5};
710 unsigned RMfield = R16Table[BaseRegNo];
711
712 assert(RMfield && "invalid 16-bit base register");
713
714 if (IndexReg.getReg()) {
715 unsigned IndexReg16 = R16Table[getX86RegNum(IndexReg)];
716
717 assert(IndexReg16 && "invalid 16-bit index register");
718 // We must have one of SI/DI (4,5), and one of BP/BX (6,7).
719 assert(((IndexReg16 ^ RMfield) & 2) &&
720 "invalid 16-bit base/index register combination");
721 assert(Scale.getImm() == 1 &&
722 "invalid scale for 16-bit memory reference");
723
724 // Allow base/index to appear in either order (although GAS doesn't).
725 if (IndexReg16 & 2)
726 RMfield = (RMfield & 1) | ((7 - IndexReg16) << 1);
727 else
728 RMfield = (IndexReg16 & 1) | ((7 - RMfield) << 1);
729 }
730
731 if (Disp.isImm() && isInt<8>(Disp.getImm())) {
732 if (Disp.getImm() == 0 && RMfield != 6) {
733 // There is no displacement; just the register.
734 emitByte(modRMByte(0, RegOpcodeField, RMfield), CB);
735 return;
736 }
737 // Use the [REG]+disp8 form, including for [BP] which cannot be encoded.
738 emitByte(modRMByte(1, RegOpcodeField, RMfield), CB);
739 emitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, StartByte, CB, Fixups);
740 return;
741 }
742 // This is the [REG]+disp16 case.
743 emitByte(modRMByte(2, RegOpcodeField, RMfield), CB);
744 } else {
745 assert(IndexReg.getReg() == 0 && "Unexpected index register!");
746 // There is no BaseReg; this is the plain [disp16] case.
747 emitByte(modRMByte(0, RegOpcodeField, 6), CB);
748 }
749
750 // Emit 16-bit displacement for plain disp16 or [REG]+disp16 cases.
751 emitImmediate(Disp, MI.getLoc(), 2, FK_Data_2, StartByte, CB, Fixups);
752 return;
753 }
754
755 // Check for presence of {disp8} or {disp32} pseudo prefixes.
756 bool UseDisp8 = MI.getFlags() & X86::IP_USE_DISP8;
757 bool UseDisp32 = MI.getFlags() & X86::IP_USE_DISP32;
758
759 // We only allow no displacement if no pseudo prefix is present.
760 bool AllowNoDisp = !UseDisp8 && !UseDisp32;
761 // Disp8 is allowed unless the {disp32} prefix is present.
762 bool AllowDisp8 = !UseDisp32;
763
764 // Determine whether a SIB byte is needed.
765 if (!ForceSIB && !X86II::needSIB(BaseReg, IndexReg.getReg(),
766 STI.hasFeature(X86::Is64Bit))) {
767 if (BaseReg == 0) { // [disp32] in X86-32 mode
768 emitByte(modRMByte(0, RegOpcodeField, 5), CB);
769 emitImmediate(Disp, MI.getLoc(), 4, FK_Data_4, StartByte, CB, Fixups);
770 return;
771 }
772
773 // If the base is not EBP/ESP/R12/R13/R20/R21/R28/R29 and there is no
774 // displacement, use simple indirect register encoding, this handles
775 // addresses like [EAX]. The encoding for [EBP], [R13], [R20], [R21], [R28]
776 // or [R29] with no displacement means [disp32] so we handle it by emitting
777 // a displacement of 0 later.
778 if (BaseRegNo != N86::EBP) {
779 if (Disp.isImm() && Disp.getImm() == 0 && AllowNoDisp) {
780 emitByte(modRMByte(0, RegOpcodeField, BaseRegNo), CB);
781 return;
782 }
783
784 // If the displacement is @tlscall, treat it as a zero.
785 if (Disp.isExpr()) {
786 auto *Sym = dyn_cast<MCSymbolRefExpr>(Disp.getExpr());
787 if (Sym && Sym->getKind() == MCSymbolRefExpr::VK_TLSCALL) {
788 // This is exclusively used by call *a@tlscall(base). The relocation
789 // (R_386_TLSCALL or R_X86_64_TLSCALL) applies to the beginning.
790 Fixups.push_back(MCFixup::create(0, Sym, FK_NONE, MI.getLoc()));
791 emitByte(modRMByte(0, RegOpcodeField, BaseRegNo), CB);
792 return;
793 }
794 }
795 }
796
797 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
798 // Including a compressed disp8 for EVEX instructions that support it.
799 // This also handles the 0 displacement for [EBP], [R13], [R21] or [R29]. We
800 // can't use disp8 if the {disp32} pseudo prefix is present.
801 if (Disp.isImm() && AllowDisp8) {
802 int ImmOffset = 0;
803 if (isDispOrCDisp8(TSFlags, Disp.getImm(), ImmOffset)) {
804 emitByte(modRMByte(1, RegOpcodeField, BaseRegNo), CB);
805 emitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, StartByte, CB, Fixups,
806 ImmOffset);
807 return;
808 }
809 }
810
811 // Otherwise, emit the most general non-SIB encoding: [REG+disp32].
812 // Displacement may be 0 for [EBP], [R13], [R21], [R29] case if {disp32}
813 // pseudo prefix prevented using disp8 above.
814 emitByte(modRMByte(2, RegOpcodeField, BaseRegNo), CB);
815 unsigned Opcode = MI.getOpcode();
816 unsigned FixupKind = Opcode == X86::MOV32rm ? X86::reloc_signed_4byte_relax
818 emitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind), StartByte, CB,
819 Fixups);
820 return;
821 }
822
823 // We need a SIB byte, so start by outputting the ModR/M byte first
824 assert(IndexReg.getReg() != X86::ESP && IndexReg.getReg() != X86::RSP &&
825 "Cannot use ESP as index reg!");
826
827 bool ForceDisp32 = false;
828 bool ForceDisp8 = false;
829 int ImmOffset = 0;
830 if (BaseReg == 0) {
831 // If there is no base register, we emit the special case SIB byte with
832 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
833 BaseRegNo = 5;
834 emitByte(modRMByte(0, RegOpcodeField, 4), CB);
835 ForceDisp32 = true;
836 } else if (Disp.isImm() && Disp.getImm() == 0 && AllowNoDisp &&
837 // Base reg can't be EBP/RBP/R13/R21/R29 as that would end up with
838 // '5' as the base field, but that is the magic [*] nomenclature
839 // that indicates no base when mod=0. For these cases we'll emit a
840 // 0 displacement instead.
841 BaseRegNo != N86::EBP) {
842 // Emit no displacement ModR/M byte
843 emitByte(modRMByte(0, RegOpcodeField, 4), CB);
844 } else if (Disp.isImm() && AllowDisp8 &&
845 isDispOrCDisp8(TSFlags, Disp.getImm(), ImmOffset)) {
846 // Displacement fits in a byte or matches an EVEX compressed disp8, use
847 // disp8 encoding. This also handles EBP/R13/R21/R29 base with 0
848 // displacement unless {disp32} pseudo prefix was used.
849 emitByte(modRMByte(1, RegOpcodeField, 4), CB);
850 ForceDisp8 = true;
851 } else {
852 // Otherwise, emit the normal disp32 encoding.
853 emitByte(modRMByte(2, RegOpcodeField, 4), CB);
854 ForceDisp32 = true;
855 }
856
857 // Calculate what the SS field value should be...
858 static const unsigned SSTable[] = {~0U, 0, 1, ~0U, 2, ~0U, ~0U, ~0U, 3};
859 unsigned SS = SSTable[Scale.getImm()];
860
861 unsigned IndexRegNo = IndexReg.getReg() ? getX86RegNum(IndexReg) : 4;
862
863 emitSIBByte(SS, IndexRegNo, BaseRegNo, CB);
864
865 // Do we need to output a displacement?
866 if (ForceDisp8)
867 emitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, StartByte, CB, Fixups,
868 ImmOffset);
869 else if (ForceDisp32)
870 emitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte),
871 StartByte, CB, Fixups);
872}
873
874/// Emit all instruction prefixes.
875///
876/// \returns one of the REX, XOP, VEX2, VEX3, EVEX if any of them is used,
877/// otherwise returns None.
878PrefixKind X86MCCodeEmitter::emitPrefixImpl(unsigned &CurOp, const MCInst &MI,
879 const MCSubtargetInfo &STI,
880 SmallVectorImpl<char> &CB) const {
881 uint64_t TSFlags = MCII.get(MI.getOpcode()).TSFlags;
882 // Determine where the memory operand starts, if present.
883 int MemoryOperand = X86II::getMemoryOperandNo(TSFlags);
884 // Emit segment override opcode prefix as needed.
885 if (MemoryOperand != -1) {
886 MemoryOperand += CurOp;
887 emitSegmentOverridePrefix(MemoryOperand + X86::AddrSegmentReg, MI, CB);
888 }
889
890 // Emit the repeat opcode prefix as needed.
891 unsigned Flags = MI.getFlags();
892 if (TSFlags & X86II::REP || Flags & X86::IP_HAS_REPEAT)
893 emitByte(0xF3, CB);
894 if (Flags & X86::IP_HAS_REPEAT_NE)
895 emitByte(0xF2, CB);
896
897 // Emit the address size opcode prefix as needed.
898 if (X86_MC::needsAddressSizeOverride(MI, STI, MemoryOperand, TSFlags) ||
899 Flags & X86::IP_HAS_AD_SIZE)
900 emitByte(0x67, CB);
901
902 uint64_t Form = TSFlags & X86II::FormMask;
903 switch (Form) {
904 default:
905 break;
906 case X86II::RawFrmDstSrc: {
907 // Emit segment override opcode prefix as needed (not for %ds).
908 if (MI.getOperand(2).getReg() != X86::DS)
909 emitSegmentOverridePrefix(2, MI, CB);
910 CurOp += 3; // Consume operands.
911 break;
912 }
913 case X86II::RawFrmSrc: {
914 // Emit segment override opcode prefix as needed (not for %ds).
915 if (MI.getOperand(1).getReg() != X86::DS)
916 emitSegmentOverridePrefix(1, MI, CB);
917 CurOp += 2; // Consume operands.
918 break;
919 }
920 case X86II::RawFrmDst: {
921 ++CurOp; // Consume operand.
922 break;
923 }
925 // Emit segment override opcode prefix as needed.
926 emitSegmentOverridePrefix(1, MI, CB);
927 break;
928 }
929 }
930
931 // REX prefix is optional, but if used must be immediately before the opcode
932 // Encoding type for this instruction.
933 return (TSFlags & X86II::EncodingMask)
934 ? emitVEXOpcodePrefix(MemoryOperand, MI, STI, CB)
935 : emitOpcodePrefix(MemoryOperand, MI, STI, CB);
936}
937
938// AVX instructions are encoded using an encoding scheme that combines
939// prefix bytes, opcode extension field, operand encoding fields, and vector
940// length encoding capability into a new prefix, referred to as VEX.
941
942// The majority of the AVX-512 family of instructions (operating on
943// 512/256/128-bit vector register operands) are encoded using a new prefix
944// (called EVEX).
945
946// XOP is a revised subset of what was originally intended as SSE5. It was
947// changed to be similar but not overlapping with AVX.
948
949/// Emit XOP, VEX2, VEX3 or EVEX prefix.
950/// \returns the used prefix.
951PrefixKind
952X86MCCodeEmitter::emitVEXOpcodePrefix(int MemOperand, const MCInst &MI,
953 const MCSubtargetInfo &STI,
954 SmallVectorImpl<char> &CB) const {
955 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
956 uint64_t TSFlags = Desc.TSFlags;
957
958 assert(!(TSFlags & X86II::LOCK) && "Can't have LOCK VEX.");
959
960#ifndef NDEBUG
961 unsigned NumOps = MI.getNumOperands();
962 for (unsigned I = NumOps ? X86II::getOperandBias(Desc) : 0; I != NumOps;
963 ++I) {
964 const MCOperand &MO = MI.getOperand(I);
965 if (!MO.isReg())
966 continue;
967 unsigned Reg = MO.getReg();
968 if (Reg == X86::AH || Reg == X86::BH || Reg == X86::CH || Reg == X86::DH)
970 "Cannot encode high byte register in VEX/EVEX-prefixed instruction");
971 }
972#endif
973
974 X86OpcodePrefixHelper Prefix(*Ctx.getRegisterInfo());
975 switch (TSFlags & X86II::EncodingMask) {
976 default:
977 break;
978 case X86II::XOP:
979 Prefix.setLowerBound(XOP);
980 break;
981 case X86II::VEX:
982 // VEX can be 2 byte or 3 byte, not determined yet if not explicit
983 Prefix.setLowerBound(MI.getFlags() & X86::IP_USE_VEX3 ? VEX3 : VEX2);
984 break;
985 case X86II::EVEX:
986 Prefix.setLowerBound(EVEX);
987 break;
988 }
989
990 Prefix.setW(TSFlags & X86II::REX_W);
991 Prefix.setNF(TSFlags & X86II::EVEX_NF);
992
993 bool HasEVEX_K = TSFlags & X86II::EVEX_K;
994 bool HasVEX_4V = TSFlags & X86II::VEX_4V;
995 bool IsND = X86II::hasNewDataDest(TSFlags); // IsND implies HasVEX_4V
996 bool HasEVEX_RC = TSFlags & X86II::EVEX_RC;
997
998 switch (TSFlags & X86II::OpMapMask) {
999 default:
1000 llvm_unreachable("Invalid prefix!");
1001 case X86II::TB:
1002 Prefix.set5M(0x1); // 0F
1003 break;
1004 case X86II::T8:
1005 Prefix.set5M(0x2); // 0F 38
1006 break;
1007 case X86II::TA:
1008 Prefix.set5M(0x3); // 0F 3A
1009 break;
1010 case X86II::XOP8:
1011 Prefix.set5M(0x8);
1012 break;
1013 case X86II::XOP9:
1014 Prefix.set5M(0x9);
1015 break;
1016 case X86II::XOPA:
1017 Prefix.set5M(0xA);
1018 break;
1019 case X86II::T_MAP4:
1020 Prefix.set5M(0x4);
1021 break;
1022 case X86II::T_MAP5:
1023 Prefix.set5M(0x5);
1024 break;
1025 case X86II::T_MAP6:
1026 Prefix.set5M(0x6);
1027 break;
1028 case X86II::T_MAP7:
1029 Prefix.set5M(0x7);
1030 break;
1031 }
1032
1033 Prefix.setL(TSFlags & X86II::VEX_L);
1034 Prefix.setL2(TSFlags & X86II::EVEX_L2);
1035 if ((TSFlags & X86II::EVEX_L2) && STI.hasFeature(X86::FeatureAVX512) &&
1036 !STI.hasFeature(X86::FeatureEVEX512))
1037 report_fatal_error("ZMM registers are not supported without EVEX512");
1038 switch (TSFlags & X86II::OpPrefixMask) {
1039 case X86II::PD:
1040 Prefix.setPP(0x1); // 66
1041 break;
1042 case X86II::XS:
1043 Prefix.setPP(0x2); // F3
1044 break;
1045 case X86II::XD:
1046 Prefix.setPP(0x3); // F2
1047 break;
1048 }
1049
1050 Prefix.setZ(HasEVEX_K && (TSFlags & X86II::EVEX_Z));
1051 Prefix.setEVEX_b(TSFlags & X86II::EVEX_B);
1052
1053 bool EncodeRC = false;
1054 uint8_t EVEX_rc = 0;
1055
1056 unsigned CurOp = X86II::getOperandBias(Desc);
1057 bool HasTwoConditionalOps = TSFlags & X86II::TwoConditionalOps;
1058
1059 switch (TSFlags & X86II::FormMask) {
1060 default:
1061 llvm_unreachable("Unexpected form in emitVEXOpcodePrefix!");
1063 // src1(ModR/M), MemAddr, src2(VEX_4V)
1064 Prefix.setRR2(MI, CurOp++);
1065 Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg);
1066 Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg);
1067 CurOp += X86::AddrNumOperands;
1068 Prefix.set4VV2(MI, CurOp++);
1069 break;
1070 }
1071 case X86II::MRM_C0:
1072 case X86II::RawFrm:
1073 break;
1076 case X86II::MRMDestMem: {
1077 // MRMDestMem instructions forms:
1078 // MemAddr, src1(ModR/M)
1079 // MemAddr, src1(VEX_4V), src2(ModR/M)
1080 // MemAddr, src1(ModR/M), imm8
1081 //
1082 // NDD:
1083 // dst(VEX_4V), MemAddr, src1(ModR/M)
1084 Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg);
1085 Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg);
1086 Prefix.setV2(MI, MemOperand + X86::AddrIndexReg, HasVEX_4V);
1087
1088 if (IsND)
1089 Prefix.set4VV2(MI, CurOp++);
1090
1091 CurOp += X86::AddrNumOperands;
1092
1093 if (HasEVEX_K)
1094 Prefix.setAAA(MI, CurOp++);
1095
1096 if (!IsND && HasVEX_4V)
1097 Prefix.set4VV2(MI, CurOp++);
1098
1099 Prefix.setRR2(MI, CurOp++);
1100 if (HasTwoConditionalOps) {
1101 Prefix.set4V(MI, CurOp++, /*IsImm=*/true);
1102 Prefix.setSC(MI, CurOp++);
1103 }
1104 break;
1105 }
1106 case X86II::MRMSrcMemCC:
1108 case X86II::MRMSrcMem: {
1109 // MRMSrcMem instructions forms:
1110 // src1(ModR/M), MemAddr
1111 // src1(ModR/M), src2(VEX_4V), MemAddr
1112 // src1(ModR/M), MemAddr, imm8
1113 // src1(ModR/M), MemAddr, src2(Imm[7:4])
1114 //
1115 // FMA4:
1116 // dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(Imm[7:4])
1117 //
1118 // NDD:
1119 // dst(VEX_4V), src1(ModR/M), MemAddr
1120 if (IsND)
1121 Prefix.set4VV2(MI, CurOp++);
1122
1123 Prefix.setRR2(MI, CurOp++);
1124
1125 if (HasEVEX_K)
1126 Prefix.setAAA(MI, CurOp++);
1127
1128 if (!IsND && HasVEX_4V)
1129 Prefix.set4VV2(MI, CurOp++);
1130
1131 Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg);
1132 Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg);
1133 Prefix.setV2(MI, MemOperand + X86::AddrIndexReg, HasVEX_4V);
1134 CurOp += X86::AddrNumOperands;
1135 if (HasTwoConditionalOps) {
1136 Prefix.set4V(MI, CurOp++, /*IsImm=*/true);
1137 Prefix.setSC(MI, CurOp++);
1138 }
1139 break;
1140 }
1141 case X86II::MRMSrcMem4VOp3: {
1142 // Instruction format for 4VOp3:
1143 // src1(ModR/M), MemAddr, src3(VEX_4V)
1144 Prefix.setRR2(MI, CurOp++);
1145 Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg);
1146 Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg);
1147 Prefix.set4VV2(MI, CurOp + X86::AddrNumOperands);
1148 break;
1149 }
1150 case X86II::MRMSrcMemOp4: {
1151 // dst(ModR/M.reg), src1(VEX_4V), src2(Imm[7:4]), src3(ModR/M),
1152 Prefix.setR(MI, CurOp++);
1153 Prefix.set4V(MI, CurOp++);
1154 Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg);
1155 Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg);
1156 break;
1157 }
1158 case X86II::MRM0m:
1159 case X86II::MRM1m:
1160 case X86II::MRM2m:
1161 case X86II::MRM3m:
1162 case X86II::MRM4m:
1163 case X86II::MRM5m:
1164 case X86II::MRM6m:
1165 case X86II::MRM7m: {
1166 // MRM[0-9]m instructions forms:
1167 // MemAddr
1168 // src1(VEX_4V), MemAddr
1169 if (HasVEX_4V)
1170 Prefix.set4VV2(MI, CurOp++);
1171
1172 if (HasEVEX_K)
1173 Prefix.setAAA(MI, CurOp++);
1174
1175 Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg);
1176 Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg);
1177 Prefix.setV2(MI, MemOperand + X86::AddrIndexReg, HasVEX_4V);
1178 CurOp += X86::AddrNumOperands + 1; // Skip first imm.
1179 if (HasTwoConditionalOps) {
1180 Prefix.set4V(MI, CurOp++, /*IsImm=*/true);
1181 Prefix.setSC(MI, CurOp++);
1182 }
1183 break;
1184 }
1185 case X86II::MRMSrcRegCC:
1186 case X86II::MRMSrcReg: {
1187 // MRMSrcReg instructions forms:
1188 // dst(ModR/M), src1(VEX_4V), src2(ModR/M), src3(Imm[7:4])
1189 // dst(ModR/M), src1(ModR/M)
1190 // dst(ModR/M), src1(ModR/M), imm8
1191 //
1192 // FMA4:
1193 // dst(ModR/M.reg), src1(VEX_4V), src2(Imm[7:4]), src3(ModR/M),
1194 //
1195 // NDD:
1196 // dst(VEX_4V), src1(ModR/M.reg), src2(ModR/M)
1197 if (IsND)
1198 Prefix.set4VV2(MI, CurOp++);
1199 Prefix.setRR2(MI, CurOp++);
1200
1201 if (HasEVEX_K)
1202 Prefix.setAAA(MI, CurOp++);
1203
1204 if (!IsND && HasVEX_4V)
1205 Prefix.set4VV2(MI, CurOp++);
1206
1207 Prefix.setBB2(MI, CurOp);
1208 Prefix.setX(MI, CurOp, 4);
1209 ++CurOp;
1210
1211 if (HasTwoConditionalOps) {
1212 Prefix.set4V(MI, CurOp++, /*IsImm=*/true);
1213 Prefix.setSC(MI, CurOp++);
1214 }
1215
1216 if (TSFlags & X86II::EVEX_B) {
1217 if (HasEVEX_RC) {
1218 unsigned NumOps = Desc.getNumOperands();
1219 unsigned RcOperand = NumOps - 1;
1220 assert(RcOperand >= CurOp);
1221 EVEX_rc = MI.getOperand(RcOperand).getImm();
1222 assert(EVEX_rc <= 3 && "Invalid rounding control!");
1223 }
1224 EncodeRC = true;
1225 }
1226 break;
1227 }
1228 case X86II::MRMSrcReg4VOp3: {
1229 // Instruction format for 4VOp3:
1230 // src1(ModR/M), src2(ModR/M), src3(VEX_4V)
1231 Prefix.setRR2(MI, CurOp++);
1232 Prefix.setBB2(MI, CurOp++);
1233 Prefix.set4VV2(MI, CurOp++);
1234 break;
1235 }
1236 case X86II::MRMSrcRegOp4: {
1237 // dst(ModR/M.reg), src1(VEX_4V), src2(Imm[7:4]), src3(ModR/M),
1238 Prefix.setR(MI, CurOp++);
1239 Prefix.set4V(MI, CurOp++);
1240 // Skip second register source (encoded in Imm[7:4])
1241 ++CurOp;
1242
1243 Prefix.setB(MI, CurOp);
1244 Prefix.setX(MI, CurOp, 4);
1245 ++CurOp;
1246 break;
1247 }
1249 case X86II::MRMDestReg: {
1250 // MRMDestReg instructions forms:
1251 // dst(ModR/M), src(ModR/M)
1252 // dst(ModR/M), src(ModR/M), imm8
1253 // dst(ModR/M), src1(VEX_4V), src2(ModR/M)
1254 //
1255 // NDD:
1256 // dst(VEX_4V), src1(ModR/M), src2(ModR/M)
1257 if (IsND)
1258 Prefix.set4VV2(MI, CurOp++);
1259 Prefix.setBB2(MI, CurOp);
1260 Prefix.setX(MI, CurOp, 4);
1261 ++CurOp;
1262
1263 if (HasEVEX_K)
1264 Prefix.setAAA(MI, CurOp++);
1265
1266 if (!IsND && HasVEX_4V)
1267 Prefix.set4VV2(MI, CurOp++);
1268
1269 Prefix.setRR2(MI, CurOp++);
1270 if (HasTwoConditionalOps) {
1271 Prefix.set4V(MI, CurOp++, /*IsImm=*/true);
1272 Prefix.setSC(MI, CurOp++);
1273 }
1274 if (TSFlags & X86II::EVEX_B)
1275 EncodeRC = true;
1276 break;
1277 }
1278 case X86II::MRMr0: {
1279 // MRMr0 instructions forms:
1280 // 11:rrr:000
1281 // dst(ModR/M)
1282 Prefix.setRR2(MI, CurOp++);
1283 break;
1284 }
1285 case X86II::MRM0r:
1286 case X86II::MRM1r:
1287 case X86II::MRM2r:
1288 case X86II::MRM3r:
1289 case X86II::MRM4r:
1290 case X86II::MRM5r:
1291 case X86II::MRM6r:
1292 case X86II::MRM7r: {
1293 // MRM0r-MRM7r instructions forms:
1294 // dst(VEX_4V), src(ModR/M), imm8
1295 if (HasVEX_4V)
1296 Prefix.set4VV2(MI, CurOp++);
1297
1298 if (HasEVEX_K)
1299 Prefix.setAAA(MI, CurOp++);
1300
1301 Prefix.setBB2(MI, CurOp);
1302 Prefix.setX(MI, CurOp, 4);
1303 ++CurOp;
1304 if (HasTwoConditionalOps) {
1305 Prefix.set4V(MI, ++CurOp, /*IsImm=*/true);
1306 Prefix.setSC(MI, ++CurOp);
1307 }
1308 break;
1309 }
1310 }
1311 if (EncodeRC) {
1312 Prefix.setL(EVEX_rc & 0x1);
1313 Prefix.setL2(EVEX_rc & 0x2);
1314 }
1315 PrefixKind Kind = Prefix.determineOptimalKind();
1316 Prefix.emit(CB);
1317 return Kind;
1318}
1319
1320/// Emit REX prefix which specifies
1321/// 1) 64-bit instructions,
1322/// 2) non-default operand size, and
1323/// 3) use of X86-64 extended registers.
1324///
1325/// \returns the used prefix (REX or None).
1326PrefixKind X86MCCodeEmitter::emitREXPrefix(int MemOperand, const MCInst &MI,
1327 const MCSubtargetInfo &STI,
1328 SmallVectorImpl<char> &CB) const {
1329 if (!STI.hasFeature(X86::Is64Bit))
1330 return None;
1331 X86OpcodePrefixHelper Prefix(*Ctx.getRegisterInfo());
1332 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
1333 uint64_t TSFlags = Desc.TSFlags;
1334 Prefix.setW(TSFlags & X86II::REX_W);
1335 unsigned NumOps = MI.getNumOperands();
1336 bool UsesHighByteReg = false;
1337#ifndef NDEBUG
1338 bool HasRegOp = false;
1339#endif
1340 unsigned CurOp = NumOps ? X86II::getOperandBias(Desc) : 0;
1341 for (unsigned i = CurOp; i != NumOps; ++i) {
1342 const MCOperand &MO = MI.getOperand(i);
1343 if (MO.isReg()) {
1344#ifndef NDEBUG
1345 HasRegOp = true;
1346#endif
1347 unsigned Reg = MO.getReg();
1348 if (Reg == X86::AH || Reg == X86::BH || Reg == X86::CH || Reg == X86::DH)
1349 UsesHighByteReg = true;
1350 // If it accesses SPL, BPL, SIL, or DIL, then it requires a REX prefix.
1352 Prefix.setLowerBound(REX);
1353 } else if (MO.isExpr() && STI.getTargetTriple().isX32()) {
1354 // GOTTPOFF and TLSDESC relocations require a REX prefix to allow
1355 // linker optimizations: even if the instructions we see may not require
1356 // any prefix, they may be replaced by instructions that do. This is
1357 // handled as a special case here so that it also works for hand-written
1358 // assembly without the user needing to write REX, as with GNU as.
1359 const auto *Ref = dyn_cast<MCSymbolRefExpr>(MO.getExpr());
1360 if (Ref && (Ref->getKind() == MCSymbolRefExpr::VK_GOTTPOFF ||
1361 Ref->getKind() == MCSymbolRefExpr::VK_TLSDESC)) {
1362 Prefix.setLowerBound(REX);
1363 }
1364 }
1365 }
1367 Prefix.setLowerBound(REX2);
1368 switch (TSFlags & X86II::FormMask) {
1369 default:
1370 assert(!HasRegOp && "Unexpected form in emitREXPrefix!");
1371 break;
1372 case X86II::RawFrm:
1374 case X86II::RawFrmSrc:
1375 case X86II::RawFrmDst:
1377 break;
1378 case X86II::AddRegFrm:
1379 Prefix.setBB2(MI, CurOp++);
1380 break;
1381 case X86II::MRMSrcReg:
1382 case X86II::MRMSrcRegCC:
1383 Prefix.setRR2(MI, CurOp++);
1384 Prefix.setBB2(MI, CurOp++);
1385 break;
1386 case X86II::MRMSrcMem:
1387 case X86II::MRMSrcMemCC:
1388 Prefix.setRR2(MI, CurOp++);
1389 Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg);
1390 Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg);
1391 CurOp += X86::AddrNumOperands;
1392 break;
1393 case X86II::MRMDestReg:
1394 Prefix.setBB2(MI, CurOp++);
1395 Prefix.setRR2(MI, CurOp++);
1396 break;
1397 case X86II::MRMDestMem:
1398 Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg);
1399 Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg);
1400 CurOp += X86::AddrNumOperands;
1401 Prefix.setRR2(MI, CurOp++);
1402 break;
1403 case X86II::MRMXmCC:
1404 case X86II::MRMXm:
1405 case X86II::MRM0m:
1406 case X86II::MRM1m:
1407 case X86II::MRM2m:
1408 case X86II::MRM3m:
1409 case X86II::MRM4m:
1410 case X86II::MRM5m:
1411 case X86II::MRM6m:
1412 case X86II::MRM7m:
1413 Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg);
1414 Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg);
1415 break;
1416 case X86II::MRMXrCC:
1417 case X86II::MRMXr:
1418 case X86II::MRM0r:
1419 case X86II::MRM1r:
1420 case X86II::MRM2r:
1421 case X86II::MRM3r:
1422 case X86II::MRM4r:
1423 case X86II::MRM5r:
1424 case X86II::MRM6r:
1425 case X86II::MRM7r:
1426 Prefix.setBB2(MI, CurOp++);
1427 break;
1428 }
1429 Prefix.setM((TSFlags & X86II::OpMapMask) == X86II::TB);
1430 PrefixKind Kind = Prefix.determineOptimalKind();
1431 if (Kind && UsesHighByteReg)
1433 "Cannot encode high byte register in REX-prefixed instruction");
1434 Prefix.emit(CB);
1435 return Kind;
1436}
1437
1438/// Emit segment override opcode prefix as needed.
1439void X86MCCodeEmitter::emitSegmentOverridePrefix(
1440 unsigned SegOperand, const MCInst &MI, SmallVectorImpl<char> &CB) const {
1441 // Check for explicit segment override on memory operand.
1442 if (unsigned Reg = MI.getOperand(SegOperand).getReg())
1443 emitByte(X86::getSegmentOverridePrefixForReg(Reg), CB);
1444}
1445
1446/// Emit all instruction prefixes prior to the opcode.
1447///
1448/// \param MemOperand the operand # of the start of a memory operand if present.
1449/// If not present, it is -1.
1450///
1451/// \returns the used prefix (REX or None).
1452PrefixKind X86MCCodeEmitter::emitOpcodePrefix(int MemOperand, const MCInst &MI,
1453 const MCSubtargetInfo &STI,
1454 SmallVectorImpl<char> &CB) const {
1455 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
1456 uint64_t TSFlags = Desc.TSFlags;
1457
1458 // Emit the operand size opcode prefix as needed.
1459 if ((TSFlags & X86II::OpSizeMask) ==
1460 (STI.hasFeature(X86::Is16Bit) ? X86II::OpSize32 : X86II::OpSize16))
1461 emitByte(0x66, CB);
1462
1463 // Emit the LOCK opcode prefix.
1464 if (TSFlags & X86II::LOCK || MI.getFlags() & X86::IP_HAS_LOCK)
1465 emitByte(0xF0, CB);
1466
1467 // Emit the NOTRACK opcode prefix.
1468 if (TSFlags & X86II::NOTRACK || MI.getFlags() & X86::IP_HAS_NOTRACK)
1469 emitByte(0x3E, CB);
1470
1471 switch (TSFlags & X86II::OpPrefixMask) {
1472 case X86II::PD: // 66
1473 emitByte(0x66, CB);
1474 break;
1475 case X86II::XS: // F3
1476 emitByte(0xF3, CB);
1477 break;
1478 case X86II::XD: // F2
1479 emitByte(0xF2, CB);
1480 break;
1481 }
1482
1483 // Handle REX prefix.
1484 assert((STI.hasFeature(X86::Is64Bit) || !(TSFlags & X86II::REX_W)) &&
1485 "REX.W requires 64bit mode.");
1486 PrefixKind Kind = emitREXPrefix(MemOperand, MI, STI, CB);
1487
1488 // 0x0F escape code must be emitted just before the opcode.
1489 switch (TSFlags & X86II::OpMapMask) {
1490 case X86II::TB: // Two-byte opcode map
1491 // Encoded by M bit in REX2
1492 if (Kind == REX2)
1493 break;
1494 [[fallthrough]];
1495 case X86II::T8: // 0F 38
1496 case X86II::TA: // 0F 3A
1497 case X86II::ThreeDNow: // 0F 0F, second 0F emitted by caller.
1498 emitByte(0x0F, CB);
1499 break;
1500 }
1501
1502 switch (TSFlags & X86II::OpMapMask) {
1503 case X86II::T8: // 0F 38
1504 emitByte(0x38, CB);
1505 break;
1506 case X86II::TA: // 0F 3A
1507 emitByte(0x3A, CB);
1508 break;
1509 }
1510
1511 return Kind;
1512}
1513
1514void X86MCCodeEmitter::emitPrefix(const MCInst &MI, SmallVectorImpl<char> &CB,
1515 const MCSubtargetInfo &STI) const {
1516 unsigned Opcode = MI.getOpcode();
1517 const MCInstrDesc &Desc = MCII.get(Opcode);
1518 uint64_t TSFlags = Desc.TSFlags;
1519
1520 // Pseudo instructions don't get encoded.
1521 if (X86II::isPseudo(TSFlags))
1522 return;
1523
1524 unsigned CurOp = X86II::getOperandBias(Desc);
1525
1526 emitPrefixImpl(CurOp, MI, STI, CB);
1527}
1528
1529void X86MCCodeEmitter::encodeInstruction(const MCInst &MI,
1532 const MCSubtargetInfo &STI) const {
1533 unsigned Opcode = MI.getOpcode();
1534 const MCInstrDesc &Desc = MCII.get(Opcode);
1535 uint64_t TSFlags = Desc.TSFlags;
1536
1537 // Pseudo instructions don't get encoded.
1538 if (X86II::isPseudo(TSFlags))
1539 return;
1540
1541 unsigned NumOps = Desc.getNumOperands();
1542 unsigned CurOp = X86II::getOperandBias(Desc);
1543
1544 uint64_t StartByte = CB.size();
1545
1546 PrefixKind Kind = emitPrefixImpl(CurOp, MI, STI, CB);
1547
1548 // It uses the VEX.VVVV field?
1549 bool HasVEX_4V = TSFlags & X86II::VEX_4V;
1550 bool HasVEX_I8Reg = (TSFlags & X86II::ImmMask) == X86II::Imm8Reg;
1551
1552 // It uses the EVEX.aaa field?
1553 bool HasEVEX_K = TSFlags & X86II::EVEX_K;
1554 bool HasEVEX_RC = TSFlags & X86II::EVEX_RC;
1555
1556 // Used if a register is encoded in 7:4 of immediate.
1557 unsigned I8RegNum = 0;
1558
1559 uint8_t BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
1560
1561 if ((TSFlags & X86II::OpMapMask) == X86II::ThreeDNow)
1562 BaseOpcode = 0x0F; // Weird 3DNow! encoding.
1563
1564 unsigned OpcodeOffset = 0;
1565
1566 bool IsND = X86II::hasNewDataDest(TSFlags);
1567 bool HasTwoConditionalOps = TSFlags & X86II::TwoConditionalOps;
1568
1569 uint64_t Form = TSFlags & X86II::FormMask;
1570 switch (Form) {
1571 default:
1572 errs() << "FORM: " << Form << "\n";
1573 llvm_unreachable("Unknown FormMask value in X86MCCodeEmitter!");
1574 case X86II::Pseudo:
1575 llvm_unreachable("Pseudo instruction shouldn't be emitted");
1577 case X86II::RawFrmSrc:
1578 case X86II::RawFrmDst:
1579 case X86II::PrefixByte:
1580 emitByte(BaseOpcode, CB);
1581 break;
1582 case X86II::AddCCFrm: {
1583 // This will be added to the opcode in the fallthrough.
1584 OpcodeOffset = MI.getOperand(NumOps - 1).getImm();
1585 assert(OpcodeOffset < 16 && "Unexpected opcode offset!");
1586 --NumOps; // Drop the operand from the end.
1587 [[fallthrough]];
1588 case X86II::RawFrm:
1589 emitByte(BaseOpcode + OpcodeOffset, CB);
1590
1591 if (!STI.hasFeature(X86::Is64Bit) || !isPCRel32Branch(MI, MCII))
1592 break;
1593
1594 const MCOperand &Op = MI.getOperand(CurOp++);
1595 emitImmediate(Op, MI.getLoc(), X86II::getSizeOfImm(TSFlags),
1597 Fixups);
1598 break;
1599 }
1601 emitByte(BaseOpcode, CB);
1602 emitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1603 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1604 StartByte, CB, Fixups);
1605 ++CurOp; // skip segment operand
1606 break;
1607 case X86II::RawFrmImm8:
1608 emitByte(BaseOpcode, CB);
1609 emitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1610 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1611 StartByte, CB, Fixups);
1612 emitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1, FK_Data_1, StartByte,
1613 CB, Fixups);
1614 break;
1615 case X86II::RawFrmImm16:
1616 emitByte(BaseOpcode, CB);
1617 emitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1618 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1619 StartByte, CB, Fixups);
1620 emitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 2, FK_Data_2, StartByte,
1621 CB, Fixups);
1622 break;
1623
1624 case X86II::AddRegFrm:
1625 emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++)), CB);
1626 break;
1627
1628 case X86II::MRMDestReg: {
1629 emitByte(BaseOpcode, CB);
1630 unsigned SrcRegNum = CurOp + 1;
1631
1632 if (HasEVEX_K) // Skip writemask
1633 ++SrcRegNum;
1634
1635 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1636 ++SrcRegNum;
1637 if (IsND) // Skip the NDD operand encoded in EVEX_VVVV
1638 ++CurOp;
1639
1640 emitRegModRMByte(MI.getOperand(CurOp),
1641 getX86RegNum(MI.getOperand(SrcRegNum)), CB);
1642 CurOp = SrcRegNum + 1;
1643 break;
1644 }
1645 case X86II::MRMDestRegCC: {
1646 unsigned FirstOp = CurOp++;
1647 unsigned SecondOp = CurOp++;
1648 unsigned CC = MI.getOperand(CurOp++).getImm();
1649 emitByte(BaseOpcode + CC, CB);
1650 emitRegModRMByte(MI.getOperand(FirstOp),
1651 getX86RegNum(MI.getOperand(SecondOp)), CB);
1652 break;
1653 }
1655 unsigned CC = MI.getOperand(8).getImm();
1656 emitByte(BaseOpcode + CC, CB);
1657 unsigned SrcRegNum = CurOp + X86::AddrNumOperands;
1658 emitMemModRMByte(MI, CurOp + 1, getX86RegNum(MI.getOperand(0)), TSFlags,
1659 Kind, StartByte, CB, Fixups, STI, false);
1660 CurOp = SrcRegNum + 3; // skip reg, VEX_V4 and CC
1661 break;
1662 }
1664 case X86II::MRMDestMem: {
1665 emitByte(BaseOpcode, CB);
1666 unsigned SrcRegNum = CurOp + X86::AddrNumOperands;
1667
1668 if (HasEVEX_K) // Skip writemask
1669 ++SrcRegNum;
1670
1671 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1672 ++SrcRegNum;
1673
1674 if (IsND) // Skip new data destination
1675 ++CurOp;
1676
1677 bool ForceSIB = (Form == X86II::MRMDestMemFSIB);
1678 emitMemModRMByte(MI, CurOp, getX86RegNum(MI.getOperand(SrcRegNum)), TSFlags,
1679 Kind, StartByte, CB, Fixups, STI, ForceSIB);
1680 CurOp = SrcRegNum + 1;
1681 break;
1682 }
1683 case X86II::MRMDestMemCC: {
1684 unsigned MemOp = CurOp;
1685 CurOp = MemOp + X86::AddrNumOperands;
1686 unsigned RegOp = CurOp++;
1687 unsigned CC = MI.getOperand(CurOp++).getImm();
1688 emitByte(BaseOpcode + CC, CB);
1689 emitMemModRMByte(MI, MemOp, getX86RegNum(MI.getOperand(RegOp)), TSFlags,
1690 Kind, StartByte, CB, Fixups, STI);
1691 break;
1692 }
1693 case X86II::MRMSrcReg: {
1694 emitByte(BaseOpcode, CB);
1695 unsigned SrcRegNum = CurOp + 1;
1696
1697 if (HasEVEX_K) // Skip writemask
1698 ++SrcRegNum;
1699
1700 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1701 ++SrcRegNum;
1702
1703 if (IsND) // Skip new data destination
1704 ++CurOp;
1705
1706 emitRegModRMByte(MI.getOperand(SrcRegNum),
1707 getX86RegNum(MI.getOperand(CurOp)), CB);
1708 CurOp = SrcRegNum + 1;
1709 if (HasVEX_I8Reg)
1710 I8RegNum = getX86RegEncoding(MI, CurOp++);
1711 // do not count the rounding control operand
1712 if (HasEVEX_RC)
1713 --NumOps;
1714 break;
1715 }
1716 case X86II::MRMSrcReg4VOp3: {
1717 emitByte(BaseOpcode, CB);
1718 unsigned SrcRegNum = CurOp + 1;
1719
1720 emitRegModRMByte(MI.getOperand(SrcRegNum),
1721 getX86RegNum(MI.getOperand(CurOp)), CB);
1722 CurOp = SrcRegNum + 1;
1723 ++CurOp; // Encoded in VEX.VVVV
1724 break;
1725 }
1726 case X86II::MRMSrcRegOp4: {
1727 emitByte(BaseOpcode, CB);
1728 unsigned SrcRegNum = CurOp + 1;
1729
1730 // Skip 1st src (which is encoded in VEX_VVVV)
1731 ++SrcRegNum;
1732
1733 // Capture 2nd src (which is encoded in Imm[7:4])
1734 assert(HasVEX_I8Reg && "MRMSrcRegOp4 should imply VEX_I8Reg");
1735 I8RegNum = getX86RegEncoding(MI, SrcRegNum++);
1736
1737 emitRegModRMByte(MI.getOperand(SrcRegNum),
1738 getX86RegNum(MI.getOperand(CurOp)), CB);
1739 CurOp = SrcRegNum + 1;
1740 break;
1741 }
1742 case X86II::MRMSrcRegCC: {
1743 if (IsND) // Skip new data destination
1744 ++CurOp;
1745 unsigned FirstOp = CurOp++;
1746 unsigned SecondOp = CurOp++;
1747
1748 unsigned CC = MI.getOperand(CurOp++).getImm();
1749 emitByte(BaseOpcode + CC, CB);
1750
1751 emitRegModRMByte(MI.getOperand(SecondOp),
1752 getX86RegNum(MI.getOperand(FirstOp)), CB);
1753 break;
1754 }
1756 case X86II::MRMSrcMem: {
1757 unsigned FirstMemOp = CurOp + 1;
1758
1759 if (IsND) // Skip new data destination
1760 CurOp++;
1761
1762 if (HasEVEX_K) // Skip writemask
1763 ++FirstMemOp;
1764
1765 if (HasVEX_4V)
1766 ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
1767
1768 emitByte(BaseOpcode, CB);
1769
1770 bool ForceSIB = (Form == X86II::MRMSrcMemFSIB);
1771 emitMemModRMByte(MI, FirstMemOp, getX86RegNum(MI.getOperand(CurOp)),
1772 TSFlags, Kind, StartByte, CB, Fixups, STI, ForceSIB);
1773 CurOp = FirstMemOp + X86::AddrNumOperands;
1774 if (HasVEX_I8Reg)
1775 I8RegNum = getX86RegEncoding(MI, CurOp++);
1776 break;
1777 }
1778 case X86II::MRMSrcMem4VOp3: {
1779 unsigned FirstMemOp = CurOp + 1;
1780
1781 emitByte(BaseOpcode, CB);
1782
1783 emitMemModRMByte(MI, FirstMemOp, getX86RegNum(MI.getOperand(CurOp)),
1784 TSFlags, Kind, StartByte, CB, Fixups, STI);
1785 CurOp = FirstMemOp + X86::AddrNumOperands;
1786 ++CurOp; // Encoded in VEX.VVVV.
1787 break;
1788 }
1789 case X86II::MRMSrcMemOp4: {
1790 unsigned FirstMemOp = CurOp + 1;
1791
1792 ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
1793
1794 // Capture second register source (encoded in Imm[7:4])
1795 assert(HasVEX_I8Reg && "MRMSrcRegOp4 should imply VEX_I8Reg");
1796 I8RegNum = getX86RegEncoding(MI, FirstMemOp++);
1797
1798 emitByte(BaseOpcode, CB);
1799
1800 emitMemModRMByte(MI, FirstMemOp, getX86RegNum(MI.getOperand(CurOp)),
1801 TSFlags, Kind, StartByte, CB, Fixups, STI);
1802 CurOp = FirstMemOp + X86::AddrNumOperands;
1803 break;
1804 }
1805 case X86II::MRMSrcMemCC: {
1806 if (IsND) // Skip new data destination
1807 ++CurOp;
1808 unsigned RegOp = CurOp++;
1809 unsigned FirstMemOp = CurOp;
1810 CurOp = FirstMemOp + X86::AddrNumOperands;
1811
1812 unsigned CC = MI.getOperand(CurOp++).getImm();
1813 emitByte(BaseOpcode + CC, CB);
1814
1815 emitMemModRMByte(MI, FirstMemOp, getX86RegNum(MI.getOperand(RegOp)),
1816 TSFlags, Kind, StartByte, CB, Fixups, STI);
1817 break;
1818 }
1819
1820 case X86II::MRMXrCC: {
1821 unsigned RegOp = CurOp++;
1822
1823 unsigned CC = MI.getOperand(CurOp++).getImm();
1824 emitByte(BaseOpcode + CC, CB);
1825 emitRegModRMByte(MI.getOperand(RegOp), 0, CB);
1826 break;
1827 }
1828
1829 case X86II::MRMXr:
1830 case X86II::MRM0r:
1831 case X86II::MRM1r:
1832 case X86II::MRM2r:
1833 case X86II::MRM3r:
1834 case X86II::MRM4r:
1835 case X86II::MRM5r:
1836 case X86II::MRM6r:
1837 case X86II::MRM7r:
1838 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
1839 ++CurOp;
1840 if (HasEVEX_K) // Skip writemask
1841 ++CurOp;
1842 emitByte(BaseOpcode, CB);
1843 emitRegModRMByte(MI.getOperand(CurOp++),
1844 (Form == X86II::MRMXr) ? 0 : Form - X86II::MRM0r, CB);
1845 break;
1846 case X86II::MRMr0:
1847 emitByte(BaseOpcode, CB);
1848 emitByte(modRMByte(3, getX86RegNum(MI.getOperand(CurOp++)), 0), CB);
1849 break;
1850
1851 case X86II::MRMXmCC: {
1852 unsigned FirstMemOp = CurOp;
1853 CurOp = FirstMemOp + X86::AddrNumOperands;
1854
1855 unsigned CC = MI.getOperand(CurOp++).getImm();
1856 emitByte(BaseOpcode + CC, CB);
1857
1858 emitMemModRMByte(MI, FirstMemOp, 0, TSFlags, Kind, StartByte, CB, Fixups,
1859 STI);
1860 break;
1861 }
1862
1863 case X86II::MRMXm:
1864 case X86II::MRM0m:
1865 case X86II::MRM1m:
1866 case X86II::MRM2m:
1867 case X86II::MRM3m:
1868 case X86II::MRM4m:
1869 case X86II::MRM5m:
1870 case X86II::MRM6m:
1871 case X86II::MRM7m:
1872 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
1873 ++CurOp;
1874 if (HasEVEX_K) // Skip writemask
1875 ++CurOp;
1876 emitByte(BaseOpcode, CB);
1877 emitMemModRMByte(MI, CurOp,
1878 (Form == X86II::MRMXm) ? 0 : Form - X86II::MRM0m, TSFlags,
1879 Kind, StartByte, CB, Fixups, STI);
1880 CurOp += X86::AddrNumOperands;
1881 break;
1882
1883 case X86II::MRM0X:
1884 case X86II::MRM1X:
1885 case X86II::MRM2X:
1886 case X86II::MRM3X:
1887 case X86II::MRM4X:
1888 case X86II::MRM5X:
1889 case X86II::MRM6X:
1890 case X86II::MRM7X:
1891 emitByte(BaseOpcode, CB);
1892 emitByte(0xC0 + ((Form - X86II::MRM0X) << 3), CB);
1893 break;
1894
1895 case X86II::MRM_C0:
1896 case X86II::MRM_C1:
1897 case X86II::MRM_C2:
1898 case X86II::MRM_C3:
1899 case X86II::MRM_C4:
1900 case X86II::MRM_C5:
1901 case X86II::MRM_C6:
1902 case X86II::MRM_C7:
1903 case X86II::MRM_C8:
1904 case X86II::MRM_C9:
1905 case X86II::MRM_CA:
1906 case X86II::MRM_CB:
1907 case X86II::MRM_CC:
1908 case X86II::MRM_CD:
1909 case X86II::MRM_CE:
1910 case X86II::MRM_CF:
1911 case X86II::MRM_D0:
1912 case X86II::MRM_D1:
1913 case X86II::MRM_D2:
1914 case X86II::MRM_D3:
1915 case X86II::MRM_D4:
1916 case X86II::MRM_D5:
1917 case X86II::MRM_D6:
1918 case X86II::MRM_D7:
1919 case X86II::MRM_D8:
1920 case X86II::MRM_D9:
1921 case X86II::MRM_DA:
1922 case X86II::MRM_DB:
1923 case X86II::MRM_DC:
1924 case X86II::MRM_DD:
1925 case X86II::MRM_DE:
1926 case X86II::MRM_DF:
1927 case X86II::MRM_E0:
1928 case X86II::MRM_E1:
1929 case X86II::MRM_E2:
1930 case X86II::MRM_E3:
1931 case X86II::MRM_E4:
1932 case X86II::MRM_E5:
1933 case X86II::MRM_E6:
1934 case X86II::MRM_E7:
1935 case X86II::MRM_E8:
1936 case X86II::MRM_E9:
1937 case X86II::MRM_EA:
1938 case X86II::MRM_EB:
1939 case X86II::MRM_EC:
1940 case X86II::MRM_ED:
1941 case X86II::MRM_EE:
1942 case X86II::MRM_EF:
1943 case X86II::MRM_F0:
1944 case X86II::MRM_F1:
1945 case X86II::MRM_F2:
1946 case X86II::MRM_F3:
1947 case X86II::MRM_F4:
1948 case X86II::MRM_F5:
1949 case X86II::MRM_F6:
1950 case X86II::MRM_F7:
1951 case X86II::MRM_F8:
1952 case X86II::MRM_F9:
1953 case X86II::MRM_FA:
1954 case X86II::MRM_FB:
1955 case X86II::MRM_FC:
1956 case X86II::MRM_FD:
1957 case X86II::MRM_FE:
1958 case X86II::MRM_FF:
1959 emitByte(BaseOpcode, CB);
1960 emitByte(0xC0 + Form - X86II::MRM_C0, CB);
1961 break;
1962 }
1963
1964 if (HasVEX_I8Reg) {
1965 // The last source register of a 4 operand instruction in AVX is encoded
1966 // in bits[7:4] of a immediate byte.
1967 assert(I8RegNum < 16 && "Register encoding out of range");
1968 I8RegNum <<= 4;
1969 if (CurOp != NumOps) {
1970 unsigned Val = MI.getOperand(CurOp++).getImm();
1971 assert(Val < 16 && "Immediate operand value out of range");
1972 I8RegNum |= Val;
1973 }
1974 emitImmediate(MCOperand::createImm(I8RegNum), MI.getLoc(), 1, FK_Data_1,
1975 StartByte, CB, Fixups);
1976 } else {
1977 // If there is a remaining operand, it must be a trailing immediate. Emit it
1978 // according to the right size for the instruction. Some instructions
1979 // (SSE4a extrq and insertq) have two trailing immediates.
1980
1981 // Skip two trainling conditional operands encoded in EVEX prefix
1982 unsigned RemaningOps = NumOps - CurOp - 2 * HasTwoConditionalOps;
1983 while (RemaningOps) {
1984 emitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1985 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1986 StartByte, CB, Fixups);
1987 --RemaningOps;
1988 }
1989 CurOp += 2 * HasTwoConditionalOps;
1990 }
1991
1992 if ((TSFlags & X86II::OpMapMask) == X86II::ThreeDNow)
1993 emitByte(X86II::getBaseOpcodeFor(TSFlags), CB);
1994
1995 if (CB.size() - StartByte > 15)
1996 Ctx.reportError(MI.getLoc(), "instruction length exceeds the limit of 15");
1997#ifndef NDEBUG
1998 // FIXME: Verify.
1999 if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) {
2000 errs() << "Cannot encode all operands of: ";
2001 MI.dump();
2002 errs() << '\n';
2003 abort();
2004 }
2005#endif
2006}
2007
2009 MCContext &Ctx) {
2010 return new X86MCCodeEmitter(MCII, Ctx);
2011}
unsigned const MachineRegisterInfo * MRI
dxil metadata emit
uint64_t Size
Symbol * Sym
Definition: ELF_riscv.cpp:479
static bool isPCRel(unsigned Kind)
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
#define R2(n)
Module * Mod
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
@ None
static MCFixupKind getImmFixupKind(uint64_t TSFlags)
static bool isPCRel32Branch(const MCInst &MI, const MCInstrInfo &MCII)
static GlobalOffsetTableExprKind startsWithGlobalOffsetTable(const MCExpr *Expr)
Check if this expression starts with GLOBAL_OFFSET_TABLE and if it is of the form GLOBAL_OFFSET_TABLE...
static uint8_t modRMByte(unsigned Mod, unsigned RegOpcode, unsigned RM)
static bool isDispOrCDisp8(uint64_t TSFlags, int Value, int &ImmOffset)
Determine if this immediate can fit in a disp8 or a compressed disp8 for EVEX instructions.
GlobalOffsetTableExprKind
@ GOT_Normal
@ GOT_None
@ GOT_SymDiff
static void emitConstant(uint64_t Val, unsigned Size, SmallVectorImpl< char > &CB)
static bool hasSecRelSymbolRef(const MCExpr *Expr)
Value * RHS
This class represents an Operation in the Expression.
Binary assembler expressions.
Definition: MCExpr.h:492
const MCExpr * getLHS() const
Get the left-hand side expression of the binary operator.
Definition: MCExpr.h:639
const MCExpr * getRHS() const
Get the right-hand side expression of the binary operator.
Definition: MCExpr.h:642
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:536
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
virtual void encodeInstruction(const MCInst &Inst, SmallVectorImpl< char > &CB, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
Encode the given Inst to bytes and append to CB.
MCCodeEmitter & operator=(const MCCodeEmitter &)=delete
virtual void emitPrefix(const MCInst &Inst, SmallVectorImpl< char > &CB, const MCSubtargetInfo &STI) const
Append the prefixes of given instruction to the code buffer.
Definition: MCCodeEmitter.h:37
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition: MCExpr.cpp:194
Context object for machine code objects.
Definition: MCContext.h:76
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
@ SymbolRef
References to labels and assigned expressions.
Definition: MCExpr.h:40
@ Binary
Binary expressions.
Definition: MCExpr.h:38
ExprKind getKind() const
Definition: MCExpr.h:81
static MCFixupKind getKindForSize(unsigned Size, bool IsPCRel)
Return the generic fixup kind for a value with the given size.
Definition: MCFixup.h:109
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:87
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:63
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
int64_t getImm() const
Definition: MCInst.h:80
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
bool isImm() const
Definition: MCInst.h:62
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69
bool isReg() const
Definition: MCInst.h:61
const MCExpr * getExpr() const
Definition: MCInst.h:114
bool isExpr() const
Definition: MCInst.h:65
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
const Triple & getTargetTriple() const
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:192
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:40
StringRef getName() const
getName - Get the symbol name.
Definition: MCSymbol.h:205
void dump() const
Definition: Pass.cpp:136
Represents a location in source code.
Definition: SMLoc.h:23
size_t size() const
Definition: SmallVector.h:91
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
void push_back(const T &Elt)
Definition: SmallVector.h:426
bool isX32() const
Tests whether the target is X32.
Definition: Triple.h:1021
LLVM Value Representation.
Definition: Value.h:74
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
@ SS
Definition: X86.h:207
Reg
All possible values of the reg field in the ModR/M byte.
bool hasImm(uint64_t TSFlags)
Definition: X86BaseInfo.h:908
bool hasNewDataDest(uint64_t TSFlags)
Definition: X86BaseInfo.h:1012
@ MRM0X
MRM0X-MRM7X - Instructions that operate that have mod=11 and an opcode but ignore r/m.
Definition: X86BaseInfo.h:632
@ RawFrm
Raw - This form is for instructions that don't have any operands, so they are just a fixed opcode val...
Definition: X86BaseInfo.h:516
@ RawFrmDstSrc
RawFrmDstSrc - This form is for instructions that use the source index register SI/ESI/RSI with a pos...
Definition: X86BaseInfo.h:532
@ EVEX
EVEX - Specifies that this instruction use EVEX form which provides syntax support up to 32 512-bit r...
Definition: X86BaseInfo.h:839
@ ExplicitREX2Prefix
For instructions that require REX2 prefix even if EGPR is not used.
Definition: X86BaseInfo.h:877
@ MRMSrcMemCC
MRMSrcMemCC - This form is used for instructions that use the Mod/RM byte to specify the operands and...
Definition: X86BaseInfo.h:580
@ MRM_C0
MRM_XX (XX: C0-FF)- A mod/rm byte of exactly 0xXX.
Definition: X86BaseInfo.h:641
@ RawFrmDst
RawFrmDst - This form is for instructions that use the destination index register DI/EDI/RDI.
Definition: X86BaseInfo.h:528
@ MRMDestMem4VOp3CC
MRMDestMem4VOp3CC - This form is used for instructions that use the Mod/RM byte to specify a destinat...
Definition: X86BaseInfo.h:559
@ AddCCFrm
AddCCFrm - This form is used for Jcc that encode the condition code in the lower 4 bits of the opcode...
Definition: X86BaseInfo.h:544
@ T_MAP4
MAP4, MAP5, MAP6, MAP7 - Prefix after the 0x0F prefix.
Definition: X86BaseInfo.h:767
@ PrefixByte
PrefixByte - This form is used for instructions that represent a prefix byte like data16 or rep.
Definition: X86BaseInfo.h:547
@ MRMr0
Instructions operate on a register Reg/Opcode operand not the r/m field.
Definition: X86BaseInfo.h:561
@ MRMXm
MRMXm - This form is used for instructions that use the Mod/RM byte to specify a memory source,...
Definition: X86BaseInfo.h:587
@ MRM0r
MRM0r-MRM7r - Instructions that operate on a register r/m operand and use reg field to hold extended ...
Definition: X86BaseInfo.h:622
@ MRMDestMemFSIB
MRMDestMem - But force to use the SIB field.
Definition: X86BaseInfo.h:565
@ AddRegFrm
AddRegFrm - This form is used for instructions like 'push r32' that have their one register operand a...
Definition: X86BaseInfo.h:519
@ VEX
VEX - encoding using 0xC4/0xC5.
Definition: X86BaseInfo.h:832
@ RawFrmImm8
RawFrmImm8 - This is used for the ENTER instruction, which has two immediates, the first of which is ...
Definition: X86BaseInfo.h:536
@ TB
TB - TwoByte - Set if this instruction has a two byte opcode, which starts with a 0x0F byte before th...
Definition: X86BaseInfo.h:749
@ XOP
XOP - Opcode prefix used by XOP instructions.
Definition: X86BaseInfo.h:834
@ MRMXr
MRMXr - This form is used for instructions that use the Mod/RM byte to specify a register source,...
Definition: X86BaseInfo.h:619
@ MRMSrcMem4VOp3
MRMSrcMem4VOp3 - This form is used for instructions that encode operand 3 with VEX....
Definition: X86BaseInfo.h:574
@ XOP8
XOP8 - Prefix to include use of imm byte.
Definition: X86BaseInfo.h:754
@ MRMDestRegCC
MRMDestRegCC - This form is used for the cfcmov instructions, which use the Mod/RM byte to specify th...
Definition: X86BaseInfo.h:551
@ PD
PD - Prefix code for packed double precision vector floating point operations performed in the SSE re...
Definition: X86BaseInfo.h:735
@ MRMDestMem
MRMDestMem - This form is used for instructions that use the Mod/RM byte to specify a destination,...
Definition: X86BaseInfo.h:568
@ MRMSrcMemFSIB
MRMSrcMem - But force to use the SIB field.
Definition: X86BaseInfo.h:563
@ MRMSrcRegOp4
MRMSrcRegOp4 - This form is used for instructions that use the Mod/RM byte to specify the fourth sour...
Definition: X86BaseInfo.h:609
@ MRMXrCC
MRMXCCr - This form is used for instructions that use the Mod/RM byte to specify a register source,...
Definition: X86BaseInfo.h:616
@ T8
T8, TA - Prefix after the 0x0F prefix.
Definition: X86BaseInfo.h:751
@ MRMDestMemCC
MRMDestMemCC - This form is used for the cfcmov instructions, which use the Mod/RM byte to specify th...
Definition: X86BaseInfo.h:555
@ XOP9
XOP9 - Prefix to exclude use of imm byte.
Definition: X86BaseInfo.h:756
@ MRMXmCC
MRMXm - This form is used for instructions that use the Mod/RM byte to specify a memory source,...
Definition: X86BaseInfo.h:584
@ RawFrmImm16
RawFrmImm16 - This is used for CALL FAR instructions, which have two immediates, the first of which i...
Definition: X86BaseInfo.h:541
@ MRMSrcReg
MRMSrcReg - This form is used for instructions that use the Mod/RM byte to specify a source,...
Definition: X86BaseInfo.h:603
@ RawFrmSrc
RawFrmSrc - This form is for instructions that use the source index register SI/ESI/RSI with a possib...
Definition: X86BaseInfo.h:525
@ MRMDestReg
MRMDestReg - This form is used for instructions that use the Mod/RM byte to specify a destination,...
Definition: X86BaseInfo.h:600
@ MRMSrcMem
MRMSrcMem - This form is used for instructions that use the Mod/RM byte to specify a source,...
Definition: X86BaseInfo.h:571
@ MRMSrcMemOp4
MRMSrcMemOp4 - This form is used for instructions that use the Mod/RM byte to specify the fourth sour...
Definition: X86BaseInfo.h:577
@ Pseudo
PseudoFrm - This represents an instruction that is a pseudo instruction or one that has not been impl...
Definition: X86BaseInfo.h:513
@ CD8_Scale_Shift
The scaling factor for the AVX512's 8-bit compressed displacement.
Definition: X86BaseInfo.h:866
@ MRMSrcRegCC
MRMSrcRegCC - This form is used for instructions that use the Mod/RM byte to specify the operands and...
Definition: X86BaseInfo.h:612
@ MRM0m
MRM0m-MRM7m - Instructions that operate on a memory r/m operand and use reg field to hold extended op...
Definition: X86BaseInfo.h:590
@ ThreeDNow
ThreeDNow - This indicates that the instruction uses the wacky 0x0F 0x0F prefix for 3DNow!...
Definition: X86BaseInfo.h:765
@ XS
XS, XD - These prefix codes are for single and double precision scalar floating point operations perf...
Definition: X86BaseInfo.h:738
@ ExplicitOpPrefixMask
Definition: X86BaseInfo.h:883
@ XOPA
XOPA - Prefix to encode 0xA in VEX.MMMM of XOP instructions.
Definition: X86BaseInfo.h:758
@ MRMSrcReg4VOp3
MRMSrcReg4VOp3 - This form is used for instructions that encode operand 3 with VEX....
Definition: X86BaseInfo.h:606
@ RawFrmMemOffs
RawFrmMemOffs - This form is for instructions that store an absolute memory offset as an immediate wi...
Definition: X86BaseInfo.h:522
bool isX86_64NonExtLowByteReg(unsigned reg)
Definition: X86BaseInfo.h:1318
bool needSIB(unsigned BaseReg, unsigned IndexReg, bool In64BitMode)
Definition: X86BaseInfo.h:1334
bool isPseudo(uint64_t TSFlags)
Definition: X86BaseInfo.h:898
bool isImmPCRel(uint64_t TSFlags)
Definition: X86BaseInfo.h:934
unsigned getSizeOfImm(uint64_t TSFlags)
Decode the "size of immediate" field from the TSFlags field of the specified instruction.
Definition: X86BaseInfo.h:912
uint8_t getBaseOpcodeFor(uint64_t TSFlags)
Definition: X86BaseInfo.h:904
bool isApxExtendedReg(unsigned RegNo)
Definition: X86BaseInfo.h:1196
int getMemoryOperandNo(uint64_t TSFlags)
Definition: X86BaseInfo.h:1022
unsigned getOperandBias(const MCInstrDesc &Desc)
Compute whether all of the def operands are repeated in the uses and therefore should be skipped.
Definition: X86BaseInfo.h:979
bool isImmSigned(uint64_t TSFlags)
Definition: X86BaseInfo.h:954
bool is16BitMemOperand(const MCInst &MI, unsigned Op, const MCSubtargetInfo &STI)
bool needsAddressSizeOverride(const MCInst &MI, const MCSubtargetInfo &STI, int MemoryOperand, uint64_t TSFlags)
Returns true if this instruction needs an Address-Size override prefix.
@ AddrScaleAmt
Definition: X86BaseInfo.h:30
@ AddrSegmentReg
Definition: X86BaseInfo.h:34
@ AddrIndexReg
Definition: X86BaseInfo.h:31
@ AddrNumOperands
Definition: X86BaseInfo.h:36
@ IP_HAS_NOTRACK
Definition: X86BaseInfo.h:58
@ IP_USE_DISP8
Definition: X86BaseInfo.h:63
@ IP_HAS_AD_SIZE
Definition: X86BaseInfo.h:54
@ IP_HAS_REPEAT
Definition: X86BaseInfo.h:56
@ IP_USE_DISP32
Definition: X86BaseInfo.h:64
@ IP_HAS_REPEAT_NE
Definition: X86BaseInfo.h:55
EncodingOfSegmentOverridePrefix getSegmentOverridePrefixForReg(unsigned Reg)
Given a segment register, return the encoding of the segment override prefix for it.
Definition: X86BaseInfo.h:346
@ reloc_global_offset_table8
Definition: X86FixupKinds.h:31
@ reloc_signed_4byte_relax
Definition: X86FixupKinds.h:26
@ reloc_branch_4byte_pcrel
Definition: X86FixupKinds.h:32
@ reloc_riprel_4byte_relax
Definition: X86FixupKinds.h:19
@ reloc_signed_4byte
Definition: X86FixupKinds.h:23
@ reloc_riprel_4byte_relax_rex
Definition: X86FixupKinds.h:21
@ reloc_global_offset_table
Definition: X86FixupKinds.h:28
@ reloc_riprel_4byte_movq_load
Definition: X86FixupKinds.h:18
@ reloc_riprel_4byte
Definition: X86FixupKinds.h:17
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
MCCodeEmitter * createX86MCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:264
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:156
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
@ FK_PCRel_4
A four-byte pc relative fixup.
Definition: MCFixup.h:30
@ FK_PCRel_2
A two-byte pc relative fixup.
Definition: MCFixup.h:29
@ FK_Data_8
A eight-byte fixup.
Definition: MCFixup.h:26
@ FK_Data_1
A one-byte fixup.
Definition: MCFixup.h:23
@ FK_Data_4
A four-byte fixup.
Definition: MCFixup.h:25
@ FK_NONE
A no-op fixup.
Definition: MCFixup.h:22
@ FK_SecRel_4
A four-byte section relative fixup.
Definition: MCFixup.h:42
@ FK_PCRel_1
A one-byte pc relative fixup.
Definition: MCFixup.h:28
@ FK_Data_2
A two-byte fixup.
Definition: MCFixup.h:24
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
@ Ref
The access may reference the value stored in memory.
Description of the encoding of one expression Op.