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X86MCCodeEmitter.cpp
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1 //===-- X86MCCodeEmitter.cpp - Convert X86 code to machine code -----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the X86MCCodeEmitter class.
11 //
12 //===----------------------------------------------------------------------===//
13 
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCFixup.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/MC/MCInstrDesc.h"
24 #include "llvm/MC/MCInstrInfo.h"
25 #include "llvm/MC/MCRegisterInfo.h"
27 #include "llvm/MC/MCSymbol.h"
30 #include <cassert>
31 #include <cstdint>
32 #include <cstdlib>
33 
34 using namespace llvm;
35 
36 #define DEBUG_TYPE "mccodeemitter"
37 
38 namespace {
39 
40 class X86MCCodeEmitter : public MCCodeEmitter {
41  const MCInstrInfo &MCII;
42  MCContext &Ctx;
43 
44 public:
45  X86MCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
46  : MCII(mcii), Ctx(ctx) {
47  }
48  X86MCCodeEmitter(const X86MCCodeEmitter &) = delete;
49  X86MCCodeEmitter &operator=(const X86MCCodeEmitter &) = delete;
50  ~X86MCCodeEmitter() override = default;
51 
52  bool is64BitMode(const MCSubtargetInfo &STI) const {
53  return STI.getFeatureBits()[X86::Mode64Bit];
54  }
55 
56  bool is32BitMode(const MCSubtargetInfo &STI) const {
57  return STI.getFeatureBits()[X86::Mode32Bit];
58  }
59 
60  bool is16BitMode(const MCSubtargetInfo &STI) const {
61  return STI.getFeatureBits()[X86::Mode16Bit];
62  }
63 
64  /// Is16BitMemOperand - Return true if the specified instruction has
65  /// a 16-bit memory operand. Op specifies the operand # of the memoperand.
66  bool Is16BitMemOperand(const MCInst &MI, unsigned Op,
67  const MCSubtargetInfo &STI) const {
68  const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
69  const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
70  const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp);
71 
72  if (is16BitMode(STI) && BaseReg.getReg() == 0 &&
73  Disp.isImm() && Disp.getImm() < 0x10000)
74  return true;
75  if ((BaseReg.getReg() != 0 &&
76  X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) ||
77  (IndexReg.getReg() != 0 &&
78  X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg())))
79  return true;
80  return false;
81  }
82 
83  unsigned GetX86RegNum(const MCOperand &MO) const {
84  return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()) & 0x7;
85  }
86 
87  unsigned getX86RegEncoding(const MCInst &MI, unsigned OpNum) const {
88  return Ctx.getRegisterInfo()->getEncodingValue(
89  MI.getOperand(OpNum).getReg());
90  }
91 
92  // Does this register require a bit to be set in REX prefix.
93  bool isREXExtendedReg(const MCInst &MI, unsigned OpNum) const {
94  return (getX86RegEncoding(MI, OpNum) >> 3) & 1;
95  }
96 
97  void EmitByte(uint8_t C, unsigned &CurByte, raw_ostream &OS) const {
98  OS << (char)C;
99  ++CurByte;
100  }
101 
102  void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
103  raw_ostream &OS) const {
104  // Output the constant in little endian byte order.
105  for (unsigned i = 0; i != Size; ++i) {
106  EmitByte(Val & 255, CurByte, OS);
107  Val >>= 8;
108  }
109  }
110 
111  void EmitImmediate(const MCOperand &Disp, SMLoc Loc,
112  unsigned ImmSize, MCFixupKind FixupKind,
113  unsigned &CurByte, raw_ostream &OS,
115  int ImmOffset = 0) const;
116 
117  static uint8_t ModRMByte(unsigned Mod, unsigned RegOpcode, unsigned RM) {
118  assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
119  return RM | (RegOpcode << 3) | (Mod << 6);
120  }
121 
122  void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
123  unsigned &CurByte, raw_ostream &OS) const {
124  EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS);
125  }
126 
127  void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base,
128  unsigned &CurByte, raw_ostream &OS) const {
129  // SIB byte is in the same format as the ModRMByte.
130  EmitByte(ModRMByte(SS, Index, Base), CurByte, OS);
131  }
132 
133  void emitMemModRMByte(const MCInst &MI, unsigned Op, unsigned RegOpcodeField,
134  uint64_t TSFlags, bool Rex, unsigned &CurByte,
136  const MCSubtargetInfo &STI) const;
137 
138  void encodeInstruction(const MCInst &MI, raw_ostream &OS,
139  SmallVectorImpl<MCFixup> &Fixups,
140  const MCSubtargetInfo &STI) const override;
141 
142  void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
143  const MCInst &MI, const MCInstrDesc &Desc,
144  raw_ostream &OS) const;
145 
146  void EmitSegmentOverridePrefix(unsigned &CurByte, unsigned SegOperand,
147  const MCInst &MI, raw_ostream &OS) const;
148 
149  bool emitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
150  const MCInst &MI, const MCInstrDesc &Desc,
151  const MCSubtargetInfo &STI, raw_ostream &OS) const;
152 
153  uint8_t DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags,
154  int MemOperand, const MCInstrDesc &Desc) const;
155 };
156 
157 } // end anonymous namespace
158 
159 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
160 /// sign-extended field.
161 static bool isDisp8(int Value) {
162  return Value == (int8_t)Value;
163 }
164 
165 /// isCDisp8 - Return true if this signed displacement fits in a 8-bit
166 /// compressed dispacement field.
167 static bool isCDisp8(uint64_t TSFlags, int Value, int& CValue) {
168  assert(((TSFlags & X86II::EncodingMask) == X86II::EVEX) &&
169  "Compressed 8-bit displacement is only valid for EVEX inst.");
170 
171  unsigned CD8_Scale =
173  if (CD8_Scale == 0) {
174  CValue = Value;
175  return isDisp8(Value);
176  }
177 
178  unsigned Mask = CD8_Scale - 1;
179  assert((CD8_Scale & Mask) == 0 && "Invalid memory object size.");
180  if (Value & Mask) // Unaligned offset
181  return false;
182  Value /= (int)CD8_Scale;
183  bool Ret = (Value == (int8_t)Value);
184 
185  if (Ret)
186  CValue = Value;
187  return Ret;
188 }
189 
190 /// getImmFixupKind - Return the appropriate fixup kind to use for an immediate
191 /// in an instruction with the specified TSFlags.
192 static MCFixupKind getImmFixupKind(uint64_t TSFlags) {
193  unsigned Size = X86II::getSizeOfImm(TSFlags);
194  bool isPCRel = X86II::isImmPCRel(TSFlags);
195 
196  if (X86II::isImmSigned(TSFlags)) {
197  switch (Size) {
198  default: llvm_unreachable("Unsupported signed fixup size!");
199  case 4: return MCFixupKind(X86::reloc_signed_4byte);
200  }
201  }
202  return MCFixup::getKindForSize(Size, isPCRel);
203 }
204 
205 /// Is32BitMemOperand - Return true if the specified instruction has
206 /// a 32-bit memory operand. Op specifies the operand # of the memoperand.
207 static bool Is32BitMemOperand(const MCInst &MI, unsigned Op) {
208  const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
209  const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
210 
211  if ((BaseReg.getReg() != 0 &&
212  X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) ||
213  (IndexReg.getReg() != 0 &&
214  X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg())))
215  return true;
216  if (BaseReg.getReg() == X86::EIP) {
217  assert(IndexReg.getReg() == 0 && "Invalid eip-based address.");
218  return true;
219  }
220  return false;
221 }
222 
223 /// Is64BitMemOperand - Return true if the specified instruction has
224 /// a 64-bit memory operand. Op specifies the operand # of the memoperand.
225 #ifndef NDEBUG
226 static bool Is64BitMemOperand(const MCInst &MI, unsigned Op) {
227  const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
228  const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
229 
230  if ((BaseReg.getReg() != 0 &&
231  X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) ||
232  (IndexReg.getReg() != 0 &&
233  X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg())))
234  return true;
235  return false;
236 }
237 #endif
238 
239 /// StartsWithGlobalOffsetTable - Check if this expression starts with
240 /// _GLOBAL_OFFSET_TABLE_ and if it is of the form
241 /// _GLOBAL_OFFSET_TABLE_-symbol. This is needed to support PIC on ELF
242 /// i386 as _GLOBAL_OFFSET_TABLE_ is magical. We check only simple case that
243 /// are know to be used: _GLOBAL_OFFSET_TABLE_ by itself or at the start
244 /// of a binary expression.
249 };
252  const MCExpr *RHS = nullptr;
253  if (Expr->getKind() == MCExpr::Binary) {
254  const MCBinaryExpr *BE = static_cast<const MCBinaryExpr *>(Expr);
255  Expr = BE->getLHS();
256  RHS = BE->getRHS();
257  }
258 
259  if (Expr->getKind() != MCExpr::SymbolRef)
260  return GOT_None;
261 
262  const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr);
263  const MCSymbol &S = Ref->getSymbol();
264  if (S.getName() != "_GLOBAL_OFFSET_TABLE_")
265  return GOT_None;
266  if (RHS && RHS->getKind() == MCExpr::SymbolRef)
267  return GOT_SymDiff;
268  return GOT_Normal;
269 }
270 
271 static bool HasSecRelSymbolRef(const MCExpr *Expr) {
272  if (Expr->getKind() == MCExpr::SymbolRef) {
273  const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr);
274  return Ref->getKind() == MCSymbolRefExpr::VK_SECREL;
275  }
276  return false;
277 }
278 
279 void X86MCCodeEmitter::
280 EmitImmediate(const MCOperand &DispOp, SMLoc Loc, unsigned Size,
281  MCFixupKind FixupKind, unsigned &CurByte, raw_ostream &OS,
282  SmallVectorImpl<MCFixup> &Fixups, int ImmOffset) const {
283  const MCExpr *Expr = nullptr;
284  if (DispOp.isImm()) {
285  // If this is a simple integer displacement that doesn't require a
286  // relocation, emit it now.
287  if (FixupKind != FK_PCRel_1 &&
288  FixupKind != FK_PCRel_2 &&
289  FixupKind != FK_PCRel_4) {
290  EmitConstant(DispOp.getImm()+ImmOffset, Size, CurByte, OS);
291  return;
292  }
293  Expr = MCConstantExpr::create(DispOp.getImm(), Ctx);
294  } else {
295  Expr = DispOp.getExpr();
296  }
297 
298  // If we have an immoffset, add it to the expression.
299  if ((FixupKind == FK_Data_4 ||
300  FixupKind == FK_Data_8 ||
303  if (Kind != GOT_None) {
304  assert(ImmOffset == 0);
305 
306  if (Size == 8) {
308  } else {
309  assert(Size == 4);
311  }
312 
313  if (Kind == GOT_Normal)
314  ImmOffset = CurByte;
315  } else if (Expr->getKind() == MCExpr::SymbolRef) {
316  if (HasSecRelSymbolRef(Expr)) {
318  }
319  } else if (Expr->getKind() == MCExpr::Binary) {
320  const MCBinaryExpr *Bin = static_cast<const MCBinaryExpr*>(Expr);
321  if (HasSecRelSymbolRef(Bin->getLHS())
322  || HasSecRelSymbolRef(Bin->getRHS())) {
324  }
325  }
326  }
327 
328  // If the fixup is pc-relative, we need to bias the value to be relative to
329  // the start of the field, not the end of the field.
330  if (FixupKind == FK_PCRel_4 ||
335  ImmOffset -= 4;
336  if (FixupKind == FK_PCRel_2)
337  ImmOffset -= 2;
338  if (FixupKind == FK_PCRel_1)
339  ImmOffset -= 1;
340 
341  if (ImmOffset)
342  Expr = MCBinaryExpr::createAdd(Expr, MCConstantExpr::create(ImmOffset, Ctx),
343  Ctx);
344 
345  // Emit a symbolic constant as a fixup and 4 zeros.
346  Fixups.push_back(MCFixup::create(CurByte, Expr, FixupKind, Loc));
347  EmitConstant(0, Size, CurByte, OS);
348 }
349 
350 void X86MCCodeEmitter::emitMemModRMByte(const MCInst &MI, unsigned Op,
351  unsigned RegOpcodeField,
352  uint64_t TSFlags, bool Rex,
353  unsigned &CurByte, raw_ostream &OS,
354  SmallVectorImpl<MCFixup> &Fixups,
355  const MCSubtargetInfo &STI) const {
356  const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp);
357  const MCOperand &Base = MI.getOperand(Op+X86::AddrBaseReg);
358  const MCOperand &Scale = MI.getOperand(Op+X86::AddrScaleAmt);
359  const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
360  unsigned BaseReg = Base.getReg();
361  bool HasEVEX = (TSFlags & X86II::EncodingMask) == X86II::EVEX;
362 
363  // Handle %rip relative addressing.
364  if (BaseReg == X86::RIP ||
365  BaseReg == X86::EIP) { // [disp32+rIP] in X86-64 mode
366  assert(is64BitMode(STI) && "Rip-relative addressing requires 64-bit mode");
367  assert(IndexReg.getReg() == 0 && "Invalid rip-relative address");
368  EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
369 
370  unsigned Opcode = MI.getOpcode();
371  // movq loads are handled with a special relocation form which allows the
372  // linker to eliminate some loads for GOT references which end up in the
373  // same linkage unit.
374  unsigned FixupKind = [=]() {
375  switch (Opcode) {
376  default:
378  case X86::MOV64rm:
379  assert(Rex);
381  case X86::CALL64m:
382  case X86::JMP64m:
383  case X86::TEST64mr:
384  case X86::ADC64rm:
385  case X86::ADD64rm:
386  case X86::AND64rm:
387  case X86::CMP64rm:
388  case X86::OR64rm:
389  case X86::SBB64rm:
390  case X86::SUB64rm:
391  case X86::XOR64rm:
394  }
395  }();
396 
397  // rip-relative addressing is actually relative to the *next* instruction.
398  // Since an immediate can follow the mod/rm byte for an instruction, this
399  // means that we need to bias the displacement field of the instruction with
400  // the size of the immediate field. If we have this case, add it into the
401  // expression to emit.
402  // Note: rip-relative addressing using immediate displacement values should
403  // not be adjusted, assuming it was the user's intent.
404  int ImmSize = !Disp.isImm() && X86II::hasImm(TSFlags)
405  ? X86II::getSizeOfImm(TSFlags)
406  : 0;
407 
408  EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind),
409  CurByte, OS, Fixups, -ImmSize);
410  return;
411  }
412 
413  unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U;
414 
415  // 16-bit addressing forms of the ModR/M byte have a different encoding for
416  // the R/M field and are far more limited in which registers can be used.
417  if (Is16BitMemOperand(MI, Op, STI)) {
418  if (BaseReg) {
419  // For 32-bit addressing, the row and column values in Table 2-2 are
420  // basically the same. It's AX/CX/DX/BX/SP/BP/SI/DI in that order, with
421  // some special cases. And GetX86RegNum reflects that numbering.
422  // For 16-bit addressing it's more fun, as shown in the SDM Vol 2A,
423  // Table 2-1 "16-Bit Addressing Forms with the ModR/M byte". We can only
424  // use SI/DI/BP/BX, which have "row" values 4-7 in no particular order,
425  // while values 0-3 indicate the allowed combinations (base+index) of
426  // those: 0 for BX+SI, 1 for BX+DI, 2 for BP+SI, 3 for BP+DI.
427  //
428  // R16Table[] is a lookup from the normal RegNo, to the row values from
429  // Table 2-1 for 16-bit addressing modes. Where zero means disallowed.
430  static const unsigned R16Table[] = { 0, 0, 0, 7, 0, 6, 4, 5 };
431  unsigned RMfield = R16Table[BaseRegNo];
432 
433  assert(RMfield && "invalid 16-bit base register");
434 
435  if (IndexReg.getReg()) {
436  unsigned IndexReg16 = R16Table[GetX86RegNum(IndexReg)];
437 
438  assert(IndexReg16 && "invalid 16-bit index register");
439  // We must have one of SI/DI (4,5), and one of BP/BX (6,7).
440  assert(((IndexReg16 ^ RMfield) & 2) &&
441  "invalid 16-bit base/index register combination");
442  assert(Scale.getImm() == 1 &&
443  "invalid scale for 16-bit memory reference");
444 
445  // Allow base/index to appear in either order (although GAS doesn't).
446  if (IndexReg16 & 2)
447  RMfield = (RMfield & 1) | ((7 - IndexReg16) << 1);
448  else
449  RMfield = (IndexReg16 & 1) | ((7 - RMfield) << 1);
450  }
451 
452  if (Disp.isImm() && isDisp8(Disp.getImm())) {
453  if (Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
454  // There is no displacement; just the register.
455  EmitByte(ModRMByte(0, RegOpcodeField, RMfield), CurByte, OS);
456  return;
457  }
458  // Use the [REG]+disp8 form, including for [BP] which cannot be encoded.
459  EmitByte(ModRMByte(1, RegOpcodeField, RMfield), CurByte, OS);
460  EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups);
461  return;
462  }
463  // This is the [REG]+disp16 case.
464  EmitByte(ModRMByte(2, RegOpcodeField, RMfield), CurByte, OS);
465  } else {
466  // There is no BaseReg; this is the plain [disp16] case.
467  EmitByte(ModRMByte(0, RegOpcodeField, 6), CurByte, OS);
468  }
469 
470  // Emit 16-bit displacement for plain disp16 or [REG]+disp16 cases.
471  EmitImmediate(Disp, MI.getLoc(), 2, FK_Data_2, CurByte, OS, Fixups);
472  return;
473  }
474 
475  // Determine whether a SIB byte is needed.
476  // If no BaseReg, issue a RIP relative instruction only if the MCE can
477  // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
478  // 2-7) and absolute references.
479 
480  if (// The SIB byte must be used if there is an index register.
481  IndexReg.getReg() == 0 &&
482  // The SIB byte must be used if the base is ESP/RSP/R12, all of which
483  // encode to an R/M value of 4, which indicates that a SIB byte is
484  // present.
485  BaseRegNo != N86::ESP &&
486  // If there is no base register and we're in 64-bit mode, we need a SIB
487  // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
488  (!is64BitMode(STI) || BaseReg != 0)) {
489 
490  if (BaseReg == 0) { // [disp32] in X86-32 mode
491  EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
492  EmitImmediate(Disp, MI.getLoc(), 4, FK_Data_4, CurByte, OS, Fixups);
493  return;
494  }
495 
496  // If the base is not EBP/ESP and there is no displacement, use simple
497  // indirect register encoding, this handles addresses like [EAX]. The
498  // encoding for [EBP] with no displacement means [disp32] so we handle it
499  // by emitting a displacement of 0 below.
500  if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
501  EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS);
502  return;
503  }
504 
505  // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
506  if (Disp.isImm()) {
507  if (!HasEVEX && isDisp8(Disp.getImm())) {
508  EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
509  EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups);
510  return;
511  }
512  // Try EVEX compressed 8-bit displacement first; if failed, fall back to
513  // 32-bit displacement.
514  int CDisp8 = 0;
515  if (HasEVEX && isCDisp8(TSFlags, Disp.getImm(), CDisp8)) {
516  EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
517  EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups,
518  CDisp8 - Disp.getImm());
519  return;
520  }
521  }
522 
523  // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
524  EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS);
525  unsigned Opcode = MI.getOpcode();
526  unsigned FixupKind = Opcode == X86::MOV32rm ? X86::reloc_signed_4byte_relax
528  EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind), CurByte, OS,
529  Fixups);
530  return;
531  }
532 
533  // We need a SIB byte, so start by outputting the ModR/M byte first
534  assert(IndexReg.getReg() != X86::ESP &&
535  IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
536 
537  bool ForceDisp32 = false;
538  bool ForceDisp8 = false;
539  int CDisp8 = 0;
540  int ImmOffset = 0;
541  if (BaseReg == 0) {
542  // If there is no base register, we emit the special case SIB byte with
543  // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
544  EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
545  ForceDisp32 = true;
546  } else if (!Disp.isImm()) {
547  // Emit the normal disp32 encoding.
548  EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
549  ForceDisp32 = true;
550  } else if (Disp.getImm() == 0 &&
551  // Base reg can't be anything that ends up with '5' as the base
552  // reg, it is the magic [*] nomenclature that indicates no base.
553  BaseRegNo != N86::EBP) {
554  // Emit no displacement ModR/M byte
555  EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
556  } else if (!HasEVEX && isDisp8(Disp.getImm())) {
557  // Emit the disp8 encoding.
558  EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
559  ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
560  } else if (HasEVEX && isCDisp8(TSFlags, Disp.getImm(), CDisp8)) {
561  // Emit the disp8 encoding.
562  EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
563  ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
564  ImmOffset = CDisp8 - Disp.getImm();
565  } else {
566  // Emit the normal disp32 encoding.
567  EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
568  }
569 
570  // Calculate what the SS field value should be...
571  static const unsigned SSTable[] = { ~0U, 0, 1, ~0U, 2, ~0U, ~0U, ~0U, 3 };
572  unsigned SS = SSTable[Scale.getImm()];
573 
574  if (BaseReg == 0) {
575  // Handle the SIB byte for the case where there is no base, see Intel
576  // Manual 2A, table 2-7. The displacement has already been output.
577  unsigned IndexRegNo;
578  if (IndexReg.getReg())
579  IndexRegNo = GetX86RegNum(IndexReg);
580  else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
581  IndexRegNo = 4;
582  EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS);
583  } else {
584  unsigned IndexRegNo;
585  if (IndexReg.getReg())
586  IndexRegNo = GetX86RegNum(IndexReg);
587  else
588  IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
589  EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS);
590  }
591 
592  // Do we need to output a displacement?
593  if (ForceDisp8)
594  EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups, ImmOffset);
595  else if (ForceDisp32 || Disp.getImm() != 0)
596  EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte),
597  CurByte, OS, Fixups);
598 }
599 
600 /// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix
601 /// called VEX.
602 void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
603  int MemOperand, const MCInst &MI,
604  const MCInstrDesc &Desc,
605  raw_ostream &OS) const {
606  assert(!(TSFlags & X86II::LOCK) && "Can't have LOCK VEX.");
607 
608  uint64_t Encoding = TSFlags & X86II::EncodingMask;
609  bool HasEVEX_K = TSFlags & X86II::EVEX_K;
610  bool HasVEX_4V = TSFlags & X86II::VEX_4V;
611  bool HasEVEX_RC = TSFlags & X86II::EVEX_RC;
612 
613  // VEX_R: opcode externsion equivalent to REX.R in
614  // 1's complement (inverted) form
615  //
616  // 1: Same as REX_R=0 (must be 1 in 32-bit mode)
617  // 0: Same as REX_R=1 (64 bit mode only)
618  //
619  uint8_t VEX_R = 0x1;
620  uint8_t EVEX_R2 = 0x1;
621 
622  // VEX_X: equivalent to REX.X, only used when a
623  // register is used for index in SIB Byte.
624  //
625  // 1: Same as REX.X=0 (must be 1 in 32-bit mode)
626  // 0: Same as REX.X=1 (64-bit mode only)
627  uint8_t VEX_X = 0x1;
628 
629  // VEX_B:
630  //
631  // 1: Same as REX_B=0 (ignored in 32-bit mode)
632  // 0: Same as REX_B=1 (64 bit mode only)
633  //
634  uint8_t VEX_B = 0x1;
635 
636  // VEX_W: opcode specific (use like REX.W, or used for
637  // opcode extension, or ignored, depending on the opcode byte)
638  uint8_t VEX_W = (TSFlags & X86II::VEX_W) ? 1 : 0;
639 
640  // VEX_5M (VEX m-mmmmm field):
641  //
642  // 0b00000: Reserved for future use
643  // 0b00001: implied 0F leading opcode
644  // 0b00010: implied 0F 38 leading opcode bytes
645  // 0b00011: implied 0F 3A leading opcode bytes
646  // 0b00100-0b11111: Reserved for future use
647  // 0b01000: XOP map select - 08h instructions with imm byte
648  // 0b01001: XOP map select - 09h instructions with no imm byte
649  // 0b01010: XOP map select - 0Ah instructions with imm dword
650  uint8_t VEX_5M;
651  switch (TSFlags & X86II::OpMapMask) {
652  default: llvm_unreachable("Invalid prefix!");
653  case X86II::TB: VEX_5M = 0x1; break; // 0F
654  case X86II::T8: VEX_5M = 0x2; break; // 0F 38
655  case X86II::TA: VEX_5M = 0x3; break; // 0F 3A
656  case X86II::XOP8: VEX_5M = 0x8; break;
657  case X86II::XOP9: VEX_5M = 0x9; break;
658  case X86II::XOPA: VEX_5M = 0xA; break;
659  }
660 
661  // VEX_4V (VEX vvvv field): a register specifier
662  // (in 1's complement form) or 1111 if unused.
663  uint8_t VEX_4V = 0xf;
664  uint8_t EVEX_V2 = 0x1;
665 
666  // EVEX_L2/VEX_L (Vector Length):
667  //
668  // L2 L
669  // 0 0: scalar or 128-bit vector
670  // 0 1: 256-bit vector
671  // 1 0: 512-bit vector
672  //
673  uint8_t VEX_L = (TSFlags & X86II::VEX_L) ? 1 : 0;
674  uint8_t EVEX_L2 = (TSFlags & X86II::EVEX_L2) ? 1 : 0;
675 
676  // VEX_PP: opcode extension providing equivalent
677  // functionality of a SIMD prefix
678  //
679  // 0b00: None
680  // 0b01: 66
681  // 0b10: F3
682  // 0b11: F2
683  //
684  uint8_t VEX_PP;
685  switch (TSFlags & X86II::OpPrefixMask) {
686  default: llvm_unreachable("Invalid op prefix!");
687  case X86II::PS: VEX_PP = 0x0; break; // none
688  case X86II::PD: VEX_PP = 0x1; break; // 66
689  case X86II::XS: VEX_PP = 0x2; break; // F3
690  case X86II::XD: VEX_PP = 0x3; break; // F2
691  }
692 
693  // EVEX_U
694  uint8_t EVEX_U = 1; // Always '1' so far
695 
696  // EVEX_z
697  uint8_t EVEX_z = (HasEVEX_K && (TSFlags & X86II::EVEX_Z)) ? 1 : 0;
698 
699  // EVEX_b
700  uint8_t EVEX_b = (TSFlags & X86II::EVEX_B) ? 1 : 0;
701 
702  // EVEX_rc
703  uint8_t EVEX_rc = 0;
704 
705  // EVEX_aaa
706  uint8_t EVEX_aaa = 0;
707 
708  bool EncodeRC = false;
709 
710  // Classify VEX_B, VEX_4V, VEX_R, VEX_X
711  unsigned NumOps = Desc.getNumOperands();
712  unsigned CurOp = X86II::getOperandBias(Desc);
713 
714  switch (TSFlags & X86II::FormMask) {
715  default: llvm_unreachable("Unexpected form in EmitVEXOpcodePrefix!");
716  case X86II::RawFrm:
717  break;
718  case X86II::MRMDestMem: {
719  // MRMDestMem instructions forms:
720  // MemAddr, src1(ModR/M)
721  // MemAddr, src1(VEX_4V), src2(ModR/M)
722  // MemAddr, src1(ModR/M), imm8
723  //
724  unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg);
725  VEX_B = ~(BaseRegEnc >> 3) & 1;
726  unsigned IndexRegEnc = getX86RegEncoding(MI, MemOperand+X86::AddrIndexReg);
727  VEX_X = ~(IndexRegEnc >> 3) & 1;
728  if (!HasVEX_4V) // Only needed with VSIB which don't use VVVV.
729  EVEX_V2 = ~(IndexRegEnc >> 4) & 1;
730 
731  CurOp += X86::AddrNumOperands;
732 
733  if (HasEVEX_K)
734  EVEX_aaa = getX86RegEncoding(MI, CurOp++);
735 
736  if (HasVEX_4V) {
737  unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
738  VEX_4V = ~VRegEnc & 0xf;
739  EVEX_V2 = ~(VRegEnc >> 4) & 1;
740  }
741 
742  unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
743  VEX_R = ~(RegEnc >> 3) & 1;
744  EVEX_R2 = ~(RegEnc >> 4) & 1;
745  break;
746  }
747  case X86II::MRMSrcMem: {
748  // MRMSrcMem instructions forms:
749  // src1(ModR/M), MemAddr
750  // src1(ModR/M), src2(VEX_4V), MemAddr
751  // src1(ModR/M), MemAddr, imm8
752  // src1(ModR/M), MemAddr, src2(Imm[7:4])
753  //
754  // FMA4:
755  // dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(Imm[7:4])
756  unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
757  VEX_R = ~(RegEnc >> 3) & 1;
758  EVEX_R2 = ~(RegEnc >> 4) & 1;
759 
760  if (HasEVEX_K)
761  EVEX_aaa = getX86RegEncoding(MI, CurOp++);
762 
763  if (HasVEX_4V) {
764  unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
765  VEX_4V = ~VRegEnc & 0xf;
766  EVEX_V2 = ~(VRegEnc >> 4) & 1;
767  }
768 
769  unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg);
770  VEX_B = ~(BaseRegEnc >> 3) & 1;
771  unsigned IndexRegEnc = getX86RegEncoding(MI, MemOperand+X86::AddrIndexReg);
772  VEX_X = ~(IndexRegEnc >> 3) & 1;
773  if (!HasVEX_4V) // Only needed with VSIB which don't use VVVV.
774  EVEX_V2 = ~(IndexRegEnc >> 4) & 1;
775 
776  break;
777  }
778  case X86II::MRMSrcMem4VOp3: {
779  // Instruction format for 4VOp3:
780  // src1(ModR/M), MemAddr, src3(VEX_4V)
781  unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
782  VEX_R = ~(RegEnc >> 3) & 1;
783 
784  unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg);
785  VEX_B = ~(BaseRegEnc >> 3) & 1;
786  unsigned IndexRegEnc = getX86RegEncoding(MI, MemOperand+X86::AddrIndexReg);
787  VEX_X = ~(IndexRegEnc >> 3) & 1;
788 
789  VEX_4V = ~getX86RegEncoding(MI, CurOp + X86::AddrNumOperands) & 0xf;
790  break;
791  }
792  case X86II::MRMSrcMemOp4: {
793  // dst(ModR/M.reg), src1(VEX_4V), src2(Imm[7:4]), src3(ModR/M),
794  unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
795  VEX_R = ~(RegEnc >> 3) & 1;
796 
797  unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
798  VEX_4V = ~VRegEnc & 0xf;
799 
800  unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg);
801  VEX_B = ~(BaseRegEnc >> 3) & 1;
802  unsigned IndexRegEnc = getX86RegEncoding(MI, MemOperand+X86::AddrIndexReg);
803  VEX_X = ~(IndexRegEnc >> 3) & 1;
804  break;
805  }
806  case X86II::MRM0m: case X86II::MRM1m:
807  case X86II::MRM2m: case X86II::MRM3m:
808  case X86II::MRM4m: case X86II::MRM5m:
809  case X86II::MRM6m: case X86II::MRM7m: {
810  // MRM[0-9]m instructions forms:
811  // MemAddr
812  // src1(VEX_4V), MemAddr
813  if (HasVEX_4V) {
814  unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
815  VEX_4V = ~VRegEnc & 0xf;
816  EVEX_V2 = ~(VRegEnc >> 4) & 1;
817  }
818 
819  if (HasEVEX_K)
820  EVEX_aaa = getX86RegEncoding(MI, CurOp++);
821 
822  unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg);
823  VEX_B = ~(BaseRegEnc >> 3) & 1;
824  unsigned IndexRegEnc = getX86RegEncoding(MI, MemOperand+X86::AddrIndexReg);
825  VEX_X = ~(IndexRegEnc >> 3) & 1;
826  break;
827  }
828  case X86II::MRMSrcReg: {
829  // MRMSrcReg instructions forms:
830  // dst(ModR/M), src1(VEX_4V), src2(ModR/M), src3(Imm[7:4])
831  // dst(ModR/M), src1(ModR/M)
832  // dst(ModR/M), src1(ModR/M), imm8
833  //
834  // FMA4:
835  // dst(ModR/M.reg), src1(VEX_4V), src2(Imm[7:4]), src3(ModR/M),
836  unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
837  VEX_R = ~(RegEnc >> 3) & 1;
838  EVEX_R2 = ~(RegEnc >> 4) & 1;
839 
840  if (HasEVEX_K)
841  EVEX_aaa = getX86RegEncoding(MI, CurOp++);
842 
843  if (HasVEX_4V) {
844  unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
845  VEX_4V = ~VRegEnc & 0xf;
846  EVEX_V2 = ~(VRegEnc >> 4) & 1;
847  }
848 
849  RegEnc = getX86RegEncoding(MI, CurOp++);
850  VEX_B = ~(RegEnc >> 3) & 1;
851  VEX_X = ~(RegEnc >> 4) & 1;
852 
853  if (EVEX_b) {
854  if (HasEVEX_RC) {
855  unsigned RcOperand = NumOps-1;
856  assert(RcOperand >= CurOp);
857  EVEX_rc = MI.getOperand(RcOperand).getImm() & 0x3;
858  }
859  EncodeRC = true;
860  }
861  break;
862  }
863  case X86II::MRMSrcReg4VOp3: {
864  // Instruction format for 4VOp3:
865  // src1(ModR/M), src2(ModR/M), src3(VEX_4V)
866  unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
867  VEX_R = ~(RegEnc >> 3) & 1;
868 
869  RegEnc = getX86RegEncoding(MI, CurOp++);
870  VEX_B = ~(RegEnc >> 3) & 1;
871 
872  VEX_4V = ~getX86RegEncoding(MI, CurOp++) & 0xf;
873  break;
874  }
875  case X86II::MRMSrcRegOp4: {
876  // dst(ModR/M.reg), src1(VEX_4V), src2(Imm[7:4]), src3(ModR/M),
877  unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
878  VEX_R = ~(RegEnc >> 3) & 1;
879 
880  unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
881  VEX_4V = ~VRegEnc & 0xf;
882 
883  // Skip second register source (encoded in Imm[7:4])
884  ++CurOp;
885 
886  RegEnc = getX86RegEncoding(MI, CurOp++);
887  VEX_B = ~(RegEnc >> 3) & 1;
888  VEX_X = ~(RegEnc >> 4) & 1;
889  break;
890  }
891  case X86II::MRMDestReg: {
892  // MRMDestReg instructions forms:
893  // dst(ModR/M), src(ModR/M)
894  // dst(ModR/M), src(ModR/M), imm8
895  // dst(ModR/M), src1(VEX_4V), src2(ModR/M)
896  unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
897  VEX_B = ~(RegEnc >> 3) & 1;
898  VEX_X = ~(RegEnc >> 4) & 1;
899 
900  if (HasEVEX_K)
901  EVEX_aaa = getX86RegEncoding(MI, CurOp++);
902 
903  if (HasVEX_4V) {
904  unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
905  VEX_4V = ~VRegEnc & 0xf;
906  EVEX_V2 = ~(VRegEnc >> 4) & 1;
907  }
908 
909  RegEnc = getX86RegEncoding(MI, CurOp++);
910  VEX_R = ~(RegEnc >> 3) & 1;
911  EVEX_R2 = ~(RegEnc >> 4) & 1;
912  if (EVEX_b)
913  EncodeRC = true;
914  break;
915  }
916  case X86II::MRM0r: case X86II::MRM1r:
917  case X86II::MRM2r: case X86II::MRM3r:
918  case X86II::MRM4r: case X86II::MRM5r:
919  case X86II::MRM6r: case X86II::MRM7r: {
920  // MRM0r-MRM7r instructions forms:
921  // dst(VEX_4V), src(ModR/M), imm8
922  if (HasVEX_4V) {
923  unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
924  VEX_4V = ~VRegEnc & 0xf;
925  EVEX_V2 = ~(VRegEnc >> 4) & 1;
926  }
927  if (HasEVEX_K)
928  EVEX_aaa = getX86RegEncoding(MI, CurOp++);
929 
930  unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
931  VEX_B = ~(RegEnc >> 3) & 1;
932  VEX_X = ~(RegEnc >> 4) & 1;
933  break;
934  }
935  }
936 
937  if (Encoding == X86II::VEX || Encoding == X86II::XOP) {
938  // VEX opcode prefix can have 2 or 3 bytes
939  //
940  // 3 bytes:
941  // +-----+ +--------------+ +-------------------+
942  // | C4h | | RXB | m-mmmm | | W | vvvv | L | pp |
943  // +-----+ +--------------+ +-------------------+
944  // 2 bytes:
945  // +-----+ +-------------------+
946  // | C5h | | R | vvvv | L | pp |
947  // +-----+ +-------------------+
948  //
949  // XOP uses a similar prefix:
950  // +-----+ +--------------+ +-------------------+
951  // | 8Fh | | RXB | m-mmmm | | W | vvvv | L | pp |
952  // +-----+ +--------------+ +-------------------+
953  uint8_t LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3);
954 
955  // Can we use the 2 byte VEX prefix?
956  if (Encoding == X86II::VEX && VEX_B && VEX_X && !VEX_W && (VEX_5M == 1)) {
957  EmitByte(0xC5, CurByte, OS);
958  EmitByte(LastByte | (VEX_R << 7), CurByte, OS);
959  return;
960  }
961 
962  // 3 byte VEX prefix
963  EmitByte(Encoding == X86II::XOP ? 0x8F : 0xC4, CurByte, OS);
964  EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M, CurByte, OS);
965  EmitByte(LastByte | (VEX_W << 7), CurByte, OS);
966  } else {
967  assert(Encoding == X86II::EVEX && "unknown encoding!");
968  // EVEX opcode prefix can have 4 bytes
969  //
970  // +-----+ +--------------+ +-------------------+ +------------------------+
971  // | 62h | | RXBR' | 00mm | | W | vvvv | U | pp | | z | L'L | b | v' | aaa |
972  // +-----+ +--------------+ +-------------------+ +------------------------+
973  assert((VEX_5M & 0x3) == VEX_5M
974  && "More than 2 significant bits in VEX.m-mmmm fields for EVEX!");
975 
976  EmitByte(0x62, CurByte, OS);
977  EmitByte((VEX_R << 7) |
978  (VEX_X << 6) |
979  (VEX_B << 5) |
980  (EVEX_R2 << 4) |
981  VEX_5M, CurByte, OS);
982  EmitByte((VEX_W << 7) |
983  (VEX_4V << 3) |
984  (EVEX_U << 2) |
985  VEX_PP, CurByte, OS);
986  if (EncodeRC)
987  EmitByte((EVEX_z << 7) |
988  (EVEX_rc << 5) |
989  (EVEX_b << 4) |
990  (EVEX_V2 << 3) |
991  EVEX_aaa, CurByte, OS);
992  else
993  EmitByte((EVEX_z << 7) |
994  (EVEX_L2 << 6) |
995  (VEX_L << 5) |
996  (EVEX_b << 4) |
997  (EVEX_V2 << 3) |
998  EVEX_aaa, CurByte, OS);
999  }
1000 }
1001 
1002 /// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
1003 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
1004 /// size, and 3) use of X86-64 extended registers.
1005 uint8_t X86MCCodeEmitter::DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags,
1006  int MemOperand,
1007  const MCInstrDesc &Desc) const {
1008  uint8_t REX = 0;
1009  bool UsesHighByteReg = false;
1010 
1011  if (TSFlags & X86II::REX_W)
1012  REX |= 1 << 3; // set REX.W
1013 
1014  if (MI.getNumOperands() == 0) return REX;
1015 
1016  unsigned NumOps = MI.getNumOperands();
1017  unsigned CurOp = X86II::getOperandBias(Desc);
1018 
1019  // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
1020  for (unsigned i = CurOp; i != NumOps; ++i) {
1021  const MCOperand &MO = MI.getOperand(i);
1022  if (!MO.isReg()) continue;
1023  unsigned Reg = MO.getReg();
1024  if (Reg == X86::AH || Reg == X86::BH || Reg == X86::CH || Reg == X86::DH)
1025  UsesHighByteReg = true;
1027  // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything
1028  // that returns non-zero.
1029  REX |= 0x40; // REX fixed encoding prefix
1030  }
1031 
1032  switch (TSFlags & X86II::FormMask) {
1033  case X86II::AddRegFrm:
1034  REX |= isREXExtendedReg(MI, CurOp++) << 0; // REX.B
1035  break;
1036  case X86II::MRMSrcReg:
1037  REX |= isREXExtendedReg(MI, CurOp++) << 2; // REX.R
1038  REX |= isREXExtendedReg(MI, CurOp++) << 0; // REX.B
1039  break;
1040  case X86II::MRMSrcMem: {
1041  REX |= isREXExtendedReg(MI, CurOp++) << 2; // REX.R
1042  REX |= isREXExtendedReg(MI, MemOperand+X86::AddrBaseReg) << 0; // REX.B
1043  REX |= isREXExtendedReg(MI, MemOperand+X86::AddrIndexReg) << 1; // REX.X
1044  CurOp += X86::AddrNumOperands;
1045  break;
1046  }
1047  case X86II::MRMDestReg:
1048  REX |= isREXExtendedReg(MI, CurOp++) << 0; // REX.B
1049  REX |= isREXExtendedReg(MI, CurOp++) << 2; // REX.R
1050  break;
1051  case X86II::MRMDestMem:
1052  REX |= isREXExtendedReg(MI, MemOperand+X86::AddrBaseReg) << 0; // REX.B
1053  REX |= isREXExtendedReg(MI, MemOperand+X86::AddrIndexReg) << 1; // REX.X
1054  CurOp += X86::AddrNumOperands;
1055  REX |= isREXExtendedReg(MI, CurOp++) << 2; // REX.R
1056  break;
1057  case X86II::MRMXm:
1058  case X86II::MRM0m: case X86II::MRM1m:
1059  case X86II::MRM2m: case X86II::MRM3m:
1060  case X86II::MRM4m: case X86II::MRM5m:
1061  case X86II::MRM6m: case X86II::MRM7m:
1062  REX |= isREXExtendedReg(MI, MemOperand+X86::AddrBaseReg) << 0; // REX.B
1063  REX |= isREXExtendedReg(MI, MemOperand+X86::AddrIndexReg) << 1; // REX.X
1064  break;
1065  case X86II::MRMXr:
1066  case X86II::MRM0r: case X86II::MRM1r:
1067  case X86II::MRM2r: case X86II::MRM3r:
1068  case X86II::MRM4r: case X86II::MRM5r:
1069  case X86II::MRM6r: case X86II::MRM7r:
1070  REX |= isREXExtendedReg(MI, CurOp++) << 0; // REX.B
1071  break;
1072  }
1073  if (REX && UsesHighByteReg)
1074  report_fatal_error("Cannot encode high byte register in REX-prefixed instruction");
1075 
1076  return REX;
1077 }
1078 
1079 /// EmitSegmentOverridePrefix - Emit segment override opcode prefix as needed
1080 void X86MCCodeEmitter::EmitSegmentOverridePrefix(unsigned &CurByte,
1081  unsigned SegOperand,
1082  const MCInst &MI,
1083  raw_ostream &OS) const {
1084  // Check for explicit segment override on memory operand.
1085  switch (MI.getOperand(SegOperand).getReg()) {
1086  default: llvm_unreachable("Unknown segment register!");
1087  case 0: break;
1088  case X86::CS: EmitByte(0x2E, CurByte, OS); break;
1089  case X86::SS: EmitByte(0x36, CurByte, OS); break;
1090  case X86::DS: EmitByte(0x3E, CurByte, OS); break;
1091  case X86::ES: EmitByte(0x26, CurByte, OS); break;
1092  case X86::FS: EmitByte(0x64, CurByte, OS); break;
1093  case X86::GS: EmitByte(0x65, CurByte, OS); break;
1094  }
1095 }
1096 
1097 /// Emit all instruction prefixes prior to the opcode.
1098 ///
1099 /// MemOperand is the operand # of the start of a memory operand if present. If
1100 /// Not present, it is -1.
1101 ///
1102 /// Returns true if a REX prefix was used.
1103 bool X86MCCodeEmitter::emitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
1104  int MemOperand, const MCInst &MI,
1105  const MCInstrDesc &Desc,
1106  const MCSubtargetInfo &STI,
1107  raw_ostream &OS) const {
1108  bool Ret = false;
1109  // Emit the operand size opcode prefix as needed.
1110  if ((TSFlags & X86II::OpSizeMask) == (is16BitMode(STI) ? X86II::OpSize32
1111  : X86II::OpSize16))
1112  EmitByte(0x66, CurByte, OS);
1113 
1114  // Emit the LOCK opcode prefix.
1115  if (TSFlags & X86II::LOCK || MI.getFlags() & X86::IP_HAS_LOCK)
1116  EmitByte(0xF0, CurByte, OS);
1117 
1118  switch (TSFlags & X86II::OpPrefixMask) {
1119  case X86II::PD: // 66
1120  EmitByte(0x66, CurByte, OS);
1121  break;
1122  case X86II::XS: // F3
1123  EmitByte(0xF3, CurByte, OS);
1124  break;
1125  case X86II::XD: // F2
1126  EmitByte(0xF2, CurByte, OS);
1127  break;
1128  }
1129 
1130  // Handle REX prefix.
1131  // FIXME: Can this come before F2 etc to simplify emission?
1132  if (is64BitMode(STI)) {
1133  if (uint8_t REX = DetermineREXPrefix(MI, TSFlags, MemOperand, Desc)) {
1134  EmitByte(0x40 | REX, CurByte, OS);
1135  Ret = true;
1136  }
1137  } else {
1138  assert(!(TSFlags & X86II::REX_W) && "REX.W requires 64bit mode.");
1139  }
1140 
1141  // 0x0F escape code must be emitted just before the opcode.
1142  switch (TSFlags & X86II::OpMapMask) {
1143  case X86II::TB: // Two-byte opcode map
1144  case X86II::T8: // 0F 38
1145  case X86II::TA: // 0F 3A
1146  EmitByte(0x0F, CurByte, OS);
1147  break;
1148  }
1149 
1150  switch (TSFlags & X86II::OpMapMask) {
1151  case X86II::T8: // 0F 38
1152  EmitByte(0x38, CurByte, OS);
1153  break;
1154  case X86II::TA: // 0F 3A
1155  EmitByte(0x3A, CurByte, OS);
1156  break;
1157  }
1158  return Ret;
1159 }
1160 
1161 void X86MCCodeEmitter::
1162 encodeInstruction(const MCInst &MI, raw_ostream &OS,
1163  SmallVectorImpl<MCFixup> &Fixups,
1164  const MCSubtargetInfo &STI) const {
1165  unsigned Opcode = MI.getOpcode();
1166  const MCInstrDesc &Desc = MCII.get(Opcode);
1167  uint64_t TSFlags = Desc.TSFlags;
1168  unsigned Flags = MI.getFlags();
1169 
1170  // Pseudo instructions don't get encoded.
1171  if ((TSFlags & X86II::FormMask) == X86II::Pseudo)
1172  return;
1173 
1174  unsigned NumOps = Desc.getNumOperands();
1175  unsigned CurOp = X86II::getOperandBias(Desc);
1176 
1177  // Keep track of the current byte being emitted.
1178  unsigned CurByte = 0;
1179 
1180  // Encoding type for this instruction.
1181  uint64_t Encoding = TSFlags & X86II::EncodingMask;
1182 
1183  // It uses the VEX.VVVV field?
1184  bool HasVEX_4V = TSFlags & X86II::VEX_4V;
1185  bool HasVEX_I8Reg = (TSFlags & X86II::ImmMask) == X86II::Imm8Reg;
1186 
1187  // It uses the EVEX.aaa field?
1188  bool HasEVEX_K = TSFlags & X86II::EVEX_K;
1189  bool HasEVEX_RC = TSFlags & X86II::EVEX_RC;
1190 
1191  // Used if a register is encoded in 7:4 of immediate.
1192  unsigned I8RegNum = 0;
1193 
1194  // Determine where the memory operand starts, if present.
1195  int MemoryOperand = X86II::getMemoryOperandNo(TSFlags);
1196  if (MemoryOperand != -1) MemoryOperand += CurOp;
1197 
1198  // Emit segment override opcode prefix as needed.
1199  if (MemoryOperand >= 0)
1200  EmitSegmentOverridePrefix(CurByte, MemoryOperand+X86::AddrSegmentReg,
1201  MI, OS);
1202 
1203  // Emit the repeat opcode prefix as needed.
1204  if (TSFlags & X86II::REP || Flags & X86::IP_HAS_REPEAT)
1205  EmitByte(0xF3, CurByte, OS);
1206  if (Flags & X86::IP_HAS_REPEAT_NE)
1207  EmitByte(0xF2, CurByte, OS);
1208 
1209  // Emit the address size opcode prefix as needed.
1210  bool need_address_override;
1211  uint64_t AdSize = TSFlags & X86II::AdSizeMask;
1212  if ((is16BitMode(STI) && AdSize == X86II::AdSize32) ||
1213  (is32BitMode(STI) && AdSize == X86II::AdSize16) ||
1214  (is64BitMode(STI) && AdSize == X86II::AdSize32)) {
1215  need_address_override = true;
1216  } else if (MemoryOperand < 0) {
1217  need_address_override = false;
1218  } else if (is64BitMode(STI)) {
1219  assert(!Is16BitMemOperand(MI, MemoryOperand, STI));
1220  need_address_override = Is32BitMemOperand(MI, MemoryOperand);
1221  } else if (is32BitMode(STI)) {
1222  assert(!Is64BitMemOperand(MI, MemoryOperand));
1223  need_address_override = Is16BitMemOperand(MI, MemoryOperand, STI);
1224  } else {
1225  assert(is16BitMode(STI));
1226  assert(!Is64BitMemOperand(MI, MemoryOperand));
1227  need_address_override = !Is16BitMemOperand(MI, MemoryOperand, STI);
1228  }
1229 
1230  if (need_address_override)
1231  EmitByte(0x67, CurByte, OS);
1232 
1233  bool Rex = false;
1234  if (Encoding == 0)
1235  Rex = emitOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, STI, OS);
1236  else
1237  EmitVEXOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS);
1238 
1239  uint8_t BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
1240 
1241  if (TSFlags & X86II::Has3DNow0F0FOpcode)
1242  BaseOpcode = 0x0F; // Weird 3DNow! encoding.
1243 
1244  uint64_t Form = TSFlags & X86II::FormMask;
1245  switch (Form) {
1246  default: errs() << "FORM: " << Form << "\n";
1247  llvm_unreachable("Unknown FormMask value in X86MCCodeEmitter!");
1248  case X86II::Pseudo:
1249  llvm_unreachable("Pseudo instruction shouldn't be emitted");
1250  case X86II::RawFrmDstSrc: {
1251  unsigned siReg = MI.getOperand(1).getReg();
1252  assert(((siReg == X86::SI && MI.getOperand(0).getReg() == X86::DI) ||
1253  (siReg == X86::ESI && MI.getOperand(0).getReg() == X86::EDI) ||
1254  (siReg == X86::RSI && MI.getOperand(0).getReg() == X86::RDI)) &&
1255  "SI and DI register sizes do not match");
1256  // Emit segment override opcode prefix as needed (not for %ds).
1257  if (MI.getOperand(2).getReg() != X86::DS)
1258  EmitSegmentOverridePrefix(CurByte, 2, MI, OS);
1259  // Emit AdSize prefix as needed.
1260  if ((!is32BitMode(STI) && siReg == X86::ESI) ||
1261  (is32BitMode(STI) && siReg == X86::SI))
1262  EmitByte(0x67, CurByte, OS);
1263  CurOp += 3; // Consume operands.
1264  EmitByte(BaseOpcode, CurByte, OS);
1265  break;
1266  }
1267  case X86II::RawFrmSrc: {
1268  unsigned siReg = MI.getOperand(0).getReg();
1269  // Emit segment override opcode prefix as needed (not for %ds).
1270  if (MI.getOperand(1).getReg() != X86::DS)
1271  EmitSegmentOverridePrefix(CurByte, 1, MI, OS);
1272  // Emit AdSize prefix as needed.
1273  if ((!is32BitMode(STI) && siReg == X86::ESI) ||
1274  (is32BitMode(STI) && siReg == X86::SI))
1275  EmitByte(0x67, CurByte, OS);
1276  CurOp += 2; // Consume operands.
1277  EmitByte(BaseOpcode, CurByte, OS);
1278  break;
1279  }
1280  case X86II::RawFrmDst: {
1281  unsigned siReg = MI.getOperand(0).getReg();
1282  // Emit AdSize prefix as needed.
1283  if ((!is32BitMode(STI) && siReg == X86::EDI) ||
1284  (is32BitMode(STI) && siReg == X86::DI))
1285  EmitByte(0x67, CurByte, OS);
1286  ++CurOp; // Consume operand.
1287  EmitByte(BaseOpcode, CurByte, OS);
1288  break;
1289  }
1290  case X86II::RawFrm:
1291  EmitByte(BaseOpcode, CurByte, OS);
1292  break;
1293  case X86II::RawFrmMemOffs:
1294  // Emit segment override opcode prefix as needed.
1295  EmitSegmentOverridePrefix(CurByte, 1, MI, OS);
1296  EmitByte(BaseOpcode, CurByte, OS);
1297  EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1298  X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1299  CurByte, OS, Fixups);
1300  ++CurOp; // skip segment operand
1301  break;
1302  case X86II::RawFrmImm8:
1303  EmitByte(BaseOpcode, CurByte, OS);
1304  EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1305  X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1306  CurByte, OS, Fixups);
1307  EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1, FK_Data_1, CurByte,
1308  OS, Fixups);
1309  break;
1310  case X86II::RawFrmImm16:
1311  EmitByte(BaseOpcode, CurByte, OS);
1312  EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1313  X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1314  CurByte, OS, Fixups);
1315  EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 2, FK_Data_2, CurByte,
1316  OS, Fixups);
1317  break;
1318 
1319  case X86II::AddRegFrm:
1320  EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS);
1321  break;
1322 
1323  case X86II::MRMDestReg: {
1324  EmitByte(BaseOpcode, CurByte, OS);
1325  unsigned SrcRegNum = CurOp + 1;
1326 
1327  if (HasEVEX_K) // Skip writemask
1328  ++SrcRegNum;
1329 
1330  if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1331  ++SrcRegNum;
1332 
1333  EmitRegModRMByte(MI.getOperand(CurOp),
1334  GetX86RegNum(MI.getOperand(SrcRegNum)), CurByte, OS);
1335  CurOp = SrcRegNum + 1;
1336  break;
1337  }
1338  case X86II::MRMDestMem: {
1339  EmitByte(BaseOpcode, CurByte, OS);
1340  unsigned SrcRegNum = CurOp + X86::AddrNumOperands;
1341 
1342  if (HasEVEX_K) // Skip writemask
1343  ++SrcRegNum;
1344 
1345  if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1346  ++SrcRegNum;
1347 
1348  emitMemModRMByte(MI, CurOp, GetX86RegNum(MI.getOperand(SrcRegNum)), TSFlags,
1349  Rex, CurByte, OS, Fixups, STI);
1350  CurOp = SrcRegNum + 1;
1351  break;
1352  }
1353  case X86II::MRMSrcReg: {
1354  EmitByte(BaseOpcode, CurByte, OS);
1355  unsigned SrcRegNum = CurOp + 1;
1356 
1357  if (HasEVEX_K) // Skip writemask
1358  ++SrcRegNum;
1359 
1360  if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1361  ++SrcRegNum;
1362 
1363  EmitRegModRMByte(MI.getOperand(SrcRegNum),
1364  GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS);
1365  CurOp = SrcRegNum + 1;
1366  if (HasVEX_I8Reg)
1367  I8RegNum = getX86RegEncoding(MI, CurOp++);
1368  // do not count the rounding control operand
1369  if (HasEVEX_RC)
1370  --NumOps;
1371  break;
1372  }
1373  case X86II::MRMSrcReg4VOp3: {
1374  EmitByte(BaseOpcode, CurByte, OS);
1375  unsigned SrcRegNum = CurOp + 1;
1376 
1377  EmitRegModRMByte(MI.getOperand(SrcRegNum),
1378  GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS);
1379  CurOp = SrcRegNum + 1;
1380  ++CurOp; // Encoded in VEX.VVVV
1381  break;
1382  }
1383  case X86II::MRMSrcRegOp4: {
1384  EmitByte(BaseOpcode, CurByte, OS);
1385  unsigned SrcRegNum = CurOp + 1;
1386 
1387  // Skip 1st src (which is encoded in VEX_VVVV)
1388  ++SrcRegNum;
1389 
1390  // Capture 2nd src (which is encoded in Imm[7:4])
1391  assert(HasVEX_I8Reg && "MRMSrcRegOp4 should imply VEX_I8Reg");
1392  I8RegNum = getX86RegEncoding(MI, SrcRegNum++);
1393 
1394  EmitRegModRMByte(MI.getOperand(SrcRegNum),
1395  GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS);
1396  CurOp = SrcRegNum + 1;
1397  break;
1398  }
1399  case X86II::MRMSrcMem: {
1400  unsigned FirstMemOp = CurOp+1;
1401 
1402  if (HasEVEX_K) // Skip writemask
1403  ++FirstMemOp;
1404 
1405  if (HasVEX_4V)
1406  ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
1407 
1408  EmitByte(BaseOpcode, CurByte, OS);
1409 
1410  emitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)),
1411  TSFlags, Rex, CurByte, OS, Fixups, STI);
1412  CurOp = FirstMemOp + X86::AddrNumOperands;
1413  if (HasVEX_I8Reg)
1414  I8RegNum = getX86RegEncoding(MI, CurOp++);
1415  break;
1416  }
1417  case X86II::MRMSrcMem4VOp3: {
1418  unsigned FirstMemOp = CurOp+1;
1419 
1420  EmitByte(BaseOpcode, CurByte, OS);
1421 
1422  emitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)),
1423  TSFlags, Rex, CurByte, OS, Fixups, STI);
1424  CurOp = FirstMemOp + X86::AddrNumOperands;
1425  ++CurOp; // Encoded in VEX.VVVV.
1426  break;
1427  }
1428  case X86II::MRMSrcMemOp4: {
1429  unsigned FirstMemOp = CurOp+1;
1430 
1431  ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
1432 
1433  // Capture second register source (encoded in Imm[7:4])
1434  assert(HasVEX_I8Reg && "MRMSrcRegOp4 should imply VEX_I8Reg");
1435  I8RegNum = getX86RegEncoding(MI, FirstMemOp++);
1436 
1437  EmitByte(BaseOpcode, CurByte, OS);
1438 
1439  emitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)),
1440  TSFlags, Rex, CurByte, OS, Fixups, STI);
1441  CurOp = FirstMemOp + X86::AddrNumOperands;
1442  break;
1443  }
1444 
1445  case X86II::MRMXr:
1446  case X86II::MRM0r: case X86II::MRM1r:
1447  case X86II::MRM2r: case X86II::MRM3r:
1448  case X86II::MRM4r: case X86II::MRM5r:
1449  case X86II::MRM6r: case X86II::MRM7r:
1450  if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
1451  ++CurOp;
1452  if (HasEVEX_K) // Skip writemask
1453  ++CurOp;
1454  EmitByte(BaseOpcode, CurByte, OS);
1455  EmitRegModRMByte(MI.getOperand(CurOp++),
1456  (Form == X86II::MRMXr) ? 0 : Form-X86II::MRM0r,
1457  CurByte, OS);
1458  break;
1459 
1460  case X86II::MRMXm:
1461  case X86II::MRM0m: case X86II::MRM1m:
1462  case X86II::MRM2m: case X86II::MRM3m:
1463  case X86II::MRM4m: case X86II::MRM5m:
1464  case X86II::MRM6m: case X86II::MRM7m:
1465  if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
1466  ++CurOp;
1467  if (HasEVEX_K) // Skip writemask
1468  ++CurOp;
1469  EmitByte(BaseOpcode, CurByte, OS);
1470  emitMemModRMByte(MI, CurOp,
1471  (Form == X86II::MRMXm) ? 0 : Form - X86II::MRM0m, TSFlags,
1472  Rex, CurByte, OS, Fixups, STI);
1473  CurOp += X86::AddrNumOperands;
1474  break;
1475 
1476  case X86II::MRM_C0: case X86II::MRM_C1: case X86II::MRM_C2:
1477  case X86II::MRM_C3: case X86II::MRM_C4: case X86II::MRM_C5:
1478  case X86II::MRM_C6: case X86II::MRM_C7: case X86II::MRM_C8:
1479  case X86II::MRM_C9: case X86II::MRM_CA: case X86II::MRM_CB:
1480  case X86II::MRM_CC: case X86II::MRM_CD: case X86II::MRM_CE:
1481  case X86II::MRM_CF: case X86II::MRM_D0: case X86II::MRM_D1:
1482  case X86II::MRM_D2: case X86II::MRM_D3: case X86II::MRM_D4:
1483  case X86II::MRM_D5: case X86II::MRM_D6: case X86II::MRM_D7:
1484  case X86II::MRM_D8: case X86II::MRM_D9: case X86II::MRM_DA:
1485  case X86II::MRM_DB: case X86II::MRM_DC: case X86II::MRM_DD:
1486  case X86II::MRM_DE: case X86II::MRM_DF: case X86II::MRM_E0:
1487  case X86II::MRM_E1: case X86II::MRM_E2: case X86II::MRM_E3:
1488  case X86II::MRM_E4: case X86II::MRM_E5: case X86II::MRM_E6:
1489  case X86II::MRM_E7: case X86II::MRM_E8: case X86II::MRM_E9:
1490  case X86II::MRM_EA: case X86II::MRM_EB: case X86II::MRM_EC:
1491  case X86II::MRM_ED: case X86II::MRM_EE: case X86II::MRM_EF:
1492  case X86II::MRM_F0: case X86II::MRM_F1: case X86II::MRM_F2:
1493  case X86II::MRM_F3: case X86II::MRM_F4: case X86II::MRM_F5:
1494  case X86II::MRM_F6: case X86II::MRM_F7: case X86II::MRM_F8:
1495  case X86II::MRM_F9: case X86II::MRM_FA: case X86II::MRM_FB:
1496  case X86II::MRM_FC: case X86II::MRM_FD: case X86II::MRM_FE:
1497  case X86II::MRM_FF:
1498  EmitByte(BaseOpcode, CurByte, OS);
1499  EmitByte(0xC0 + Form - X86II::MRM_C0, CurByte, OS);
1500  break;
1501  }
1502 
1503  if (HasVEX_I8Reg) {
1504  // The last source register of a 4 operand instruction in AVX is encoded
1505  // in bits[7:4] of a immediate byte.
1506  assert(I8RegNum < 16 && "Register encoding out of range");
1507  I8RegNum <<= 4;
1508  if (CurOp != NumOps) {
1509  unsigned Val = MI.getOperand(CurOp++).getImm();
1510  assert(Val < 16 && "Immediate operand value out of range");
1511  I8RegNum |= Val;
1512  }
1513  EmitImmediate(MCOperand::createImm(I8RegNum), MI.getLoc(), 1, FK_Data_1,
1514  CurByte, OS, Fixups);
1515  } else {
1516  // If there is a remaining operand, it must be a trailing immediate. Emit it
1517  // according to the right size for the instruction. Some instructions
1518  // (SSE4a extrq and insertq) have two trailing immediates.
1519  while (CurOp != NumOps && NumOps - CurOp <= 2) {
1520  EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1521  X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1522  CurByte, OS, Fixups);
1523  }
1524  }
1525 
1526  if (TSFlags & X86II::Has3DNow0F0FOpcode)
1527  EmitByte(X86II::getBaseOpcodeFor(TSFlags), CurByte, OS);
1528 
1529 #ifndef NDEBUG
1530  // FIXME: Verify.
1531  if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) {
1532  errs() << "Cannot encode all operands of: ";
1533  MI.dump();
1534  errs() << '\n';
1535  abort();
1536  }
1537 #endif
1538 }
1539 
1541  const MCRegisterInfo &MRI,
1542  MCContext &Ctx) {
1543  return new X86MCCodeEmitter(MCII, Ctx);
1544 }
uint64_t CallInst * C
static bool HasSecRelSymbolRef(const MCExpr *Expr)
bool isImm() const
Definition: MCInst.h:59
AddrSegmentReg - The operand # of the segment in the memory operand.
Definition: X86BaseInfo.h:39
static bool Is64BitMemOperand(const MCInst &MI, unsigned Op)
Is64BitMemOperand - Return true if the specified instruction has a 64-bit memory operand.
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
MRMSrcReg4VOp3 - This form is used for instructions that encode operand 3 with VEX.VVVV and do not load from memory.
Definition: X86BaseInfo.h:329
bool isX86_64NonExtLowByteReg(unsigned reg)
Definition: X86BaseInfo.h:785
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:115
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
MRM[0-7][rm] - These forms are used to represent instructions that use a Mod/RM byte, and use the middle field to hold extended opcode information.
Definition: X86BaseInfo.h:290
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:42
VariantKind getKind() const
Definition: MCExpr.h:328
static bool isDisp8(int Value)
isDisp8 - Return true if this signed displacement fits in a 8-bit sign-extended field.
MRMXm - This form is used for instructions that use the Mod/RM byte to specify a memory source...
Definition: X86BaseInfo.h:310
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
static GlobalOffsetTableExprKind StartsWithGlobalOffsetTable(const MCExpr *Expr)
MRMSrcMem4VOp3 - This form is used for instructions that encode operand 3 with VEX.VVVV and load from memory.
Definition: X86BaseInfo.h:300
bool isReg() const
Definition: MCInst.h:58
const MCExpr * getLHS() const
Get the left-hand side expression of the binary operator.
Definition: MCExpr.h:554
RawFrmSrc - This form is for instructions that use the source index register SI/ESI/ERI with a possib...
Definition: X86BaseInfo.h:269
static MCFixupKind getKindForSize(unsigned Size, bool isPCRel)
Return the generic fixup kind for a value with the given size.
Definition: MCFixup.h:102
MRMSrcMem - This form is used for instructions that use the Mod/RM byte to specify a source...
Definition: X86BaseInfo.h:295
static Lanai::Fixups FixupKind(const MCExpr *Expr)
unsigned isImmPCRel(uint64_t TSFlags)
isImmPCRel - Return true if the immediate of the specified instruction&#39;s TSFlags indicates that it is...
Definition: X86BaseInfo.h:608
A one-byte pc relative fixup.
Definition: MCFixup.h:28
RawFrmSrc - This form is for instructions that use the source index register SI/ESI/RSI with a possib...
Definition: X86BaseInfo.h:260
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:210
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
MCCodeEmitter * createX86MCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:36
Reg
All possible values of the reg field in the ModR/M byte.
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:165
A four-byte section relative fixup.
Definition: MCFixup.h:42
RawFrmMemOffs - This form is for instructions that store an absolute memory offset as an immediate wi...
Definition: X86BaseInfo.h:256
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:65
A four-byte fixup.
Definition: MCFixup.h:26
Context object for machine code objects.
Definition: MCContext.h:61
const MCExpr * getRHS() const
Get the right-hand side expression of the binary operator.
Definition: MCExpr.h:557
AddRegFrm - This form is used for instructions like &#39;push r32&#39; that have their one register operand a...
Definition: X86BaseInfo.h:252
const MCExpr * getExpr() const
Definition: MCInst.h:96
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:451
bool hasImm(uint64_t TSFlags)
Definition: X86BaseInfo.h:585
static bool isCDisp8(uint64_t TSFlags, int Value, int &CValue)
isCDisp8 - Return true if this signed displacement fits in a 8-bit compressed dispacement field...
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:159
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
int64_t getImm() const
Definition: MCInst.h:76
static MCFixupKind getImmFixupKind(uint64_t TSFlags)
getImmFixupKind - Return the appropriate fixup kind to use for an immediate in an instruction with th...
MRMSrcRegOp4 - This form is used for instructions that use the Mod/RM byte to specify the fourth sour...
Definition: X86BaseInfo.h:334
RawFrmImm16 - This is used for CALL FAR instructions, which have two immediates, the first of which i...
Definition: X86BaseInfo.h:280
unsigned const MachineRegisterInfo * MRI
Raw - This form is for instructions that don&#39;t have any operands, so they are just a fixed opcode val...
Definition: X86BaseInfo.h:248
unsigned getFlags() const
Definition: MCInst.h:175
MRM_XX - A mod/rm byte of exactly 0xXX.
Definition: X86BaseInfo.h:346
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:22
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:23
AddrNumOperands - Total number of operands in a memory reference.
Definition: X86BaseInfo.h:42
MRMSrcReg - This form is used for instructions that use the Mod/RM byte to specify a source...
Definition: X86BaseInfo.h:324
unsigned getOperandBias(const MCInstrDesc &Desc)
getOperandBias - compute any additional adjustment needed to the offset to the start of the memory op...
Definition: X86BaseInfo.h:649
unsigned getNumOperands() const
Definition: MCInst.h:182
unsigned isImmSigned(uint64_t TSFlags)
isImmSigned - Return true if the immediate of the specified instruction&#39;s TSFlags indicates that it i...
Definition: X86BaseInfo.h:627
Binary assembler expressions.
Definition: MCExpr.h:407
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:82
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
A one-byte fixup.
Definition: MCFixup.h:24
XOP - Opcode prefix used by XOP instructions.
Definition: X86BaseInfo.h:515
static bool Is32BitMemOperand(const MCInst &MI, unsigned Op)
Is32BitMemOperand - Return true if the specified instruction has a 32-bit memory operand.
A two-byte pc relative fixup.
Definition: MCFixup.h:29
RawFrmDst - This form is for instructions that use the destination index register DI/EDI/ESI...
Definition: X86BaseInfo.h:264
void dump() const
Definition: MCInst.cpp:70
A four-byte pc relative fixup.
Definition: MCFixup.h:30
const MCSymbol & getSymbol() const
Definition: MCExpr.h:326
ExprKind getKind() const
Definition: MCExpr.h:73
RawFrmImm8 - This is used for the ENTER instruction, which has two immediates, the first of which is ...
Definition: X86BaseInfo.h:274
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:180
unsigned char getBaseOpcodeFor(uint64_t TSFlags)
Definition: X86BaseInfo.h:581
SMLoc getLoc() const
Definition: MCInst.h:178
The access may modify the value stored in memory.
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
MRMDestReg - This form is used for instructions that use the Mod/RM byte to specify a destination...
Definition: X86BaseInfo.h:319
unsigned getSizeOfImm(uint64_t TSFlags)
getSizeOfImm - Decode the "size of immediate" field from the TSFlags field of the specified instructi...
Definition: X86BaseInfo.h:591
MCSubtargetInfo - Generic base class for all target subtargets.
A eight-byte fixup.
Definition: MCFixup.h:27
References to labels and assigned expressions.
Definition: MCExpr.h:41
StringRef getName() const
getName - Get the symbol name.
Definition: MCSymbol.h:203
const unsigned Kind
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:290
LLVM Value Representation.
Definition: Value.h:73
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
Binary expressions.
Definition: MCExpr.h:39
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
The access may reference the value stored in memory.
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
GlobalOffsetTableExprKind
StartsWithGlobalOffsetTable - Check if this expression starts with GLOBAL_OFFSET_TABLE and if it is o...
IRTranslator LLVM IR MI
static bool isPCRel(unsigned Kind)
Represents a location in source code.
Definition: SMLoc.h:24
unsigned getOpcode() const
Definition: MCInst.h:172
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:35
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:123
A two-byte fixup.
Definition: MCFixup.h:25
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx)
Definition: MCExpr.cpp:159
MRMSrcMemOp4 - This form is used for instructions that use the Mod/RM byte to specify the fourth sour...
Definition: X86BaseInfo.h:305
MRMXr - This form is used for instructions that use the Mod/RM byte to specify a register source...
Definition: X86BaseInfo.h:339
int getMemoryOperandNo(uint64_t TSFlags)
getMemoryOperandNo - The function returns the MCInst operand # for the first field of the memory oper...
Definition: X86BaseInfo.h:678