LLVM  7.0.0svn
X86MCInstLower.cpp
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1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains code to lower X86 MachineInstrs to their corresponding
11 // MCInst records.
12 //
13 //===----------------------------------------------------------------------===//
14 
19 #include "Utils/X86ShuffleDecode.h"
20 #include "X86AsmPrinter.h"
21 #include "X86RegisterInfo.h"
23 #include "llvm/ADT/Optional.h"
24 #include "llvm/ADT/SmallString.h"
30 #include "llvm/CodeGen/StackMaps.h"
31 #include "llvm/IR/DataLayout.h"
32 #include "llvm/IR/GlobalValue.h"
33 #include "llvm/IR/Mangler.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCCodeEmitter.h"
36 #include "llvm/MC/MCContext.h"
37 #include "llvm/MC/MCExpr.h"
38 #include "llvm/MC/MCFixup.h"
39 #include "llvm/MC/MCInst.h"
40 #include "llvm/MC/MCInstBuilder.h"
41 #include "llvm/MC/MCSection.h"
42 #include "llvm/MC/MCSectionELF.h"
43 #include "llvm/MC/MCStreamer.h"
44 #include "llvm/MC/MCSymbol.h"
45 #include "llvm/MC/MCSymbolELF.h"
47 
48 using namespace llvm;
49 
50 namespace {
51 
52 /// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst.
53 class X86MCInstLower {
54  MCContext &Ctx;
55  const MachineFunction &MF;
56  const TargetMachine &TM;
57  const MCAsmInfo &MAI;
59 
60 public:
61  X86MCInstLower(const MachineFunction &MF, X86AsmPrinter &asmprinter);
62 
63  Optional<MCOperand> LowerMachineOperand(const MachineInstr *MI,
64  const MachineOperand &MO) const;
65  void Lower(const MachineInstr *MI, MCInst &OutMI) const;
66 
68  MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
69 
70 private:
72 };
73 
74 } // end anonymous namespace
75 
76 // Emit a minimal sequence of nops spanning NumBytes bytes.
77 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
78  const MCSubtargetInfo &STI);
79 
81  const MCSubtargetInfo &STI,
82  MCCodeEmitter *CodeEmitter) {
83  if (InShadow) {
86  raw_svector_ostream VecOS(Code);
87  CodeEmitter->encodeInstruction(Inst, VecOS, Fixups, STI);
88  CurrentShadowSize += Code.size();
89  if (CurrentShadowSize >= RequiredShadowSize)
90  InShadow = false; // The shadow is big enough. Stop counting.
91  }
92 }
93 
94 void X86AsmPrinter::StackMapShadowTracker::emitShadowPadding(
95  MCStreamer &OutStreamer, const MCSubtargetInfo &STI) {
96  if (InShadow && CurrentShadowSize < RequiredShadowSize) {
97  InShadow = false;
98  EmitNops(OutStreamer, RequiredShadowSize - CurrentShadowSize,
99  MF->getSubtarget<X86Subtarget>().is64Bit(), STI);
100  }
101 }
102 
103 void X86AsmPrinter::EmitAndCountInstruction(MCInst &Inst) {
104  OutStreamer->EmitInstruction(Inst, getSubtargetInfo(),
105  EnablePrintSchedInfo &&
106  !(Inst.getFlags() & X86::NO_SCHED_INFO));
107  SMShadowTracker.count(Inst, getSubtargetInfo(), CodeEmitter.get());
108 }
109 
110 X86MCInstLower::X86MCInstLower(const MachineFunction &mf,
111  X86AsmPrinter &asmprinter)
112  : Ctx(mf.getContext()), MF(mf), TM(mf.getTarget()), MAI(*TM.getMCAsmInfo()),
113  AsmPrinter(asmprinter) {}
114 
116  return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>();
117 }
118 
119 /// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
120 /// operand to an MCSymbol.
122  const DataLayout &DL = MF.getDataLayout();
123  assert((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) &&
124  "Isn't a symbol reference");
125 
126  MCSymbol *Sym = nullptr;
128  StringRef Suffix;
129 
130  switch (MO.getTargetFlags()) {
131  case X86II::MO_DLLIMPORT:
132  // Handle dllimport linkage.
133  Name += "__imp_";
134  break;
137  Suffix = "$non_lazy_ptr";
138  break;
139  }
140 
141  if (!Suffix.empty())
142  Name += DL.getPrivateGlobalPrefix();
143 
144  if (MO.isGlobal()) {
145  const GlobalValue *GV = MO.getGlobal();
146  AsmPrinter.getNameWithPrefix(Name, GV);
147  } else if (MO.isSymbol()) {
149  } else if (MO.isMBB()) {
150  assert(Suffix.empty());
151  Sym = MO.getMBB()->getSymbol();
152  }
153 
154  Name += Suffix;
155  if (!Sym)
156  Sym = Ctx.getOrCreateSymbol(Name);
157 
158  // If the target flags on the operand changes the name of the symbol, do that
159  // before we return the symbol.
160  switch (MO.getTargetFlags()) {
161  default:
162  break;
167  if (!StubSym.getPointer()) {
168  assert(MO.isGlobal() && "Extern symbol not handled yet");
171  !MO.getGlobal()->hasInternalLinkage());
172  }
173  break;
174  }
175  }
176 
177  return Sym;
178 }
179 
181  MCSymbol *Sym) const {
182  // FIXME: We would like an efficient form for this, so we don't have to do a
183  // lot of extra uniquing.
184  const MCExpr *Expr = nullptr;
186 
187  switch (MO.getTargetFlags()) {
188  default:
189  llvm_unreachable("Unknown target flag on GV operand");
190  case X86II::MO_NO_FLAG: // No flag.
191  // These affect the name of the symbol, not any suffix.
193  case X86II::MO_DLLIMPORT:
194  break;
195 
196  case X86II::MO_TLVP:
197  RefKind = MCSymbolRefExpr::VK_TLVP;
198  break;
201  // Subtract the pic base.
203  Expr, MCSymbolRefExpr::create(MF.getPICBaseSymbol(), Ctx), Ctx);
204  break;
205  case X86II::MO_SECREL:
206  RefKind = MCSymbolRefExpr::VK_SECREL;
207  break;
208  case X86II::MO_TLSGD:
209  RefKind = MCSymbolRefExpr::VK_TLSGD;
210  break;
211  case X86II::MO_TLSLD:
212  RefKind = MCSymbolRefExpr::VK_TLSLD;
213  break;
214  case X86II::MO_TLSLDM:
215  RefKind = MCSymbolRefExpr::VK_TLSLDM;
216  break;
217  case X86II::MO_GOTTPOFF:
219  break;
220  case X86II::MO_INDNTPOFF:
222  break;
223  case X86II::MO_TPOFF:
224  RefKind = MCSymbolRefExpr::VK_TPOFF;
225  break;
226  case X86II::MO_DTPOFF:
227  RefKind = MCSymbolRefExpr::VK_DTPOFF;
228  break;
229  case X86II::MO_NTPOFF:
230  RefKind = MCSymbolRefExpr::VK_NTPOFF;
231  break;
232  case X86II::MO_GOTNTPOFF:
234  break;
235  case X86II::MO_GOTPCREL:
237  break;
238  case X86II::MO_GOT:
239  RefKind = MCSymbolRefExpr::VK_GOT;
240  break;
241  case X86II::MO_GOTOFF:
242  RefKind = MCSymbolRefExpr::VK_GOTOFF;
243  break;
244  case X86II::MO_PLT:
245  RefKind = MCSymbolRefExpr::VK_PLT;
246  break;
247  case X86II::MO_ABS8:
249  break;
252  Expr = MCSymbolRefExpr::create(Sym, Ctx);
253  // Subtract the pic base.
255  Expr, MCSymbolRefExpr::create(MF.getPICBaseSymbol(), Ctx), Ctx);
256  if (MO.isJTI()) {
257  assert(MAI.doesSetDirectiveSuppressReloc());
258  // If .set directive is supported, use it to reduce the number of
259  // relocations the assembler will generate for differences between
260  // local labels. This is only safe when the symbols are in the same
261  // section so we are restricting it to jumptable references.
262  MCSymbol *Label = Ctx.createTempSymbol();
263  AsmPrinter.OutStreamer->EmitAssignment(Label, Expr);
264  Expr = MCSymbolRefExpr::create(Label, Ctx);
265  }
266  break;
267  }
268 
269  if (!Expr)
270  Expr = MCSymbolRefExpr::create(Sym, RefKind, Ctx);
271 
272  if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
274  Expr, MCConstantExpr::create(MO.getOffset(), Ctx), Ctx);
275  return MCOperand::createExpr(Expr);
276 }
277 
278 /// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with
279 /// a short fixed-register form.
280 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
281  unsigned ImmOp = Inst.getNumOperands() - 1;
282  assert(Inst.getOperand(0).isReg() &&
283  (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) &&
284  ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
285  Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
286  Inst.getNumOperands() == 2) &&
287  "Unexpected instruction!");
288 
289  // Check whether the destination register can be fixed.
290  unsigned Reg = Inst.getOperand(0).getReg();
291  if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
292  return;
293 
294  // If so, rewrite the instruction.
295  MCOperand Saved = Inst.getOperand(ImmOp);
296  Inst = MCInst();
297  Inst.setOpcode(Opcode);
298  Inst.addOperand(Saved);
299 }
300 
301 /// \brief If a movsx instruction has a shorter encoding for the used register
302 /// simplify the instruction to use it instead.
303 static void SimplifyMOVSX(MCInst &Inst) {
304  unsigned NewOpcode = 0;
305  unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg();
306  switch (Inst.getOpcode()) {
307  default:
308  llvm_unreachable("Unexpected instruction!");
309  case X86::MOVSX16rr8: // movsbw %al, %ax --> cbtw
310  if (Op0 == X86::AX && Op1 == X86::AL)
311  NewOpcode = X86::CBW;
312  break;
313  case X86::MOVSX32rr16: // movswl %ax, %eax --> cwtl
314  if (Op0 == X86::EAX && Op1 == X86::AX)
315  NewOpcode = X86::CWDE;
316  break;
317  case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq
318  if (Op0 == X86::RAX && Op1 == X86::EAX)
319  NewOpcode = X86::CDQE;
320  break;
321  }
322 
323  if (NewOpcode != 0) {
324  Inst = MCInst();
325  Inst.setOpcode(NewOpcode);
326  }
327 }
328 
329 /// \brief Simplify things like MOV32rm to MOV32o32a.
331  unsigned Opcode) {
332  // Don't make these simplifications in 64-bit mode; other assemblers don't
333  // perform them because they make the code larger.
334  if (Printer.getSubtarget().is64Bit())
335  return;
336 
337  bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
338  unsigned AddrBase = IsStore;
339  unsigned RegOp = IsStore ? 0 : 5;
340  unsigned AddrOp = AddrBase + 3;
341  assert(
342  Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
343  Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() &&
344  Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() &&
345  Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() &&
346  Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() &&
347  (Inst.getOperand(AddrOp).isExpr() || Inst.getOperand(AddrOp).isImm()) &&
348  "Unexpected instruction!");
349 
350  // Check whether the destination register can be fixed.
351  unsigned Reg = Inst.getOperand(RegOp).getReg();
352  if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
353  return;
354 
355  // Check whether this is an absolute address.
356  // FIXME: We know TLVP symbol refs aren't, but there should be a better way
357  // to do this here.
358  bool Absolute = true;
359  if (Inst.getOperand(AddrOp).isExpr()) {
360  const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr();
361  if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE))
362  if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
363  Absolute = false;
364  }
365 
366  if (Absolute &&
367  (Inst.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 ||
368  Inst.getOperand(AddrBase + X86::AddrScaleAmt).getImm() != 1 ||
369  Inst.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0))
370  return;
371 
372  // If so, rewrite the instruction.
373  MCOperand Saved = Inst.getOperand(AddrOp);
374  MCOperand Seg = Inst.getOperand(AddrBase + X86::AddrSegmentReg);
375  Inst = MCInst();
376  Inst.setOpcode(Opcode);
377  Inst.addOperand(Saved);
378  Inst.addOperand(Seg);
379 }
380 
381 static unsigned getRetOpcode(const X86Subtarget &Subtarget) {
382  return Subtarget.is64Bit() ? X86::RETQ : X86::RETL;
383 }
384 
386 X86MCInstLower::LowerMachineOperand(const MachineInstr *MI,
387  const MachineOperand &MO) const {
388  switch (MO.getType()) {
389  default:
390  MI->print(errs());
391  llvm_unreachable("unknown operand type");
393  // Ignore all implicit register operands.
394  if (MO.isImplicit())
395  return None;
396  return MCOperand::createReg(MO.getReg());
398  return MCOperand::createImm(MO.getImm());
404  return LowerSymbolOperand(MO, MO.getMCSymbol());
410  return LowerSymbolOperand(
413  // Ignore call clobbers.
414  return None;
415  }
416 }
417 
418 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
419  OutMI.setOpcode(MI->getOpcode());
420 
421  for (const MachineOperand &MO : MI->operands())
422  if (auto MaybeMCOp = LowerMachineOperand(MI, MO))
423  OutMI.addOperand(MaybeMCOp.getValue());
424 
425  // Handle a few special cases to eliminate operand modifiers.
426 ReSimplify:
427  switch (OutMI.getOpcode()) {
428  case X86::LEA64_32r:
429  case X86::LEA64r:
430  case X86::LEA16r:
431  case X86::LEA32r:
432  // LEA should have a segment register, but it must be empty.
433  assert(OutMI.getNumOperands() == 1 + X86::AddrNumOperands &&
434  "Unexpected # of LEA operands");
435  assert(OutMI.getOperand(1 + X86::AddrSegmentReg).getReg() == 0 &&
436  "LEA has segment specified!");
437  break;
438 
439  // Commute operands to get a smaller encoding by using VEX.R instead of VEX.B
440  // if one of the registers is extended, but other isn't.
441  case X86::VMOVZPQILo2PQIrr:
442  case X86::VMOVAPDrr:
443  case X86::VMOVAPDYrr:
444  case X86::VMOVAPSrr:
445  case X86::VMOVAPSYrr:
446  case X86::VMOVDQArr:
447  case X86::VMOVDQAYrr:
448  case X86::VMOVDQUrr:
449  case X86::VMOVDQUYrr:
450  case X86::VMOVUPDrr:
451  case X86::VMOVUPDYrr:
452  case X86::VMOVUPSrr:
453  case X86::VMOVUPSYrr: {
454  if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
456  unsigned NewOpc;
457  switch (OutMI.getOpcode()) {
458  default:
459  llvm_unreachable("Invalid opcode");
460  case X86::VMOVZPQILo2PQIrr:
461  NewOpc = X86::VMOVPQI2QIrr;
462  break;
463  case X86::VMOVAPDrr:
464  NewOpc = X86::VMOVAPDrr_REV;
465  break;
466  case X86::VMOVAPDYrr:
467  NewOpc = X86::VMOVAPDYrr_REV;
468  break;
469  case X86::VMOVAPSrr:
470  NewOpc = X86::VMOVAPSrr_REV;
471  break;
472  case X86::VMOVAPSYrr:
473  NewOpc = X86::VMOVAPSYrr_REV;
474  break;
475  case X86::VMOVDQArr:
476  NewOpc = X86::VMOVDQArr_REV;
477  break;
478  case X86::VMOVDQAYrr:
479  NewOpc = X86::VMOVDQAYrr_REV;
480  break;
481  case X86::VMOVDQUrr:
482  NewOpc = X86::VMOVDQUrr_REV;
483  break;
484  case X86::VMOVDQUYrr:
485  NewOpc = X86::VMOVDQUYrr_REV;
486  break;
487  case X86::VMOVUPDrr:
488  NewOpc = X86::VMOVUPDrr_REV;
489  break;
490  case X86::VMOVUPDYrr:
491  NewOpc = X86::VMOVUPDYrr_REV;
492  break;
493  case X86::VMOVUPSrr:
494  NewOpc = X86::VMOVUPSrr_REV;
495  break;
496  case X86::VMOVUPSYrr:
497  NewOpc = X86::VMOVUPSYrr_REV;
498  break;
499  }
500  OutMI.setOpcode(NewOpc);
501  }
502  break;
503  }
504  case X86::VMOVSDrr:
505  case X86::VMOVSSrr: {
506  if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
508  unsigned NewOpc;
509  switch (OutMI.getOpcode()) {
510  default:
511  llvm_unreachable("Invalid opcode");
512  case X86::VMOVSDrr:
513  NewOpc = X86::VMOVSDrr_REV;
514  break;
515  case X86::VMOVSSrr:
516  NewOpc = X86::VMOVSSrr_REV;
517  break;
518  }
519  OutMI.setOpcode(NewOpc);
520  }
521  break;
522  }
523 
524  // TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have register
525  // inputs modeled as normal uses instead of implicit uses. As such, truncate
526  // off all but the first operand (the callee). FIXME: Change isel.
527  case X86::TAILJMPr64:
528  case X86::TAILJMPr64_REX:
529  case X86::CALL64r:
530  case X86::CALL64pcrel32: {
531  unsigned Opcode = OutMI.getOpcode();
532  MCOperand Saved = OutMI.getOperand(0);
533  OutMI = MCInst();
534  OutMI.setOpcode(Opcode);
535  OutMI.addOperand(Saved);
536  break;
537  }
538 
539  case X86::EH_RETURN:
540  case X86::EH_RETURN64: {
541  OutMI = MCInst();
542  OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));
543  break;
544  }
545 
546  case X86::CLEANUPRET: {
547  // Replace CATCHRET with the appropriate RET.
548  OutMI = MCInst();
549  OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));
550  break;
551  }
552 
553  case X86::CATCHRET: {
554  // Replace CATCHRET with the appropriate RET.
555  const X86Subtarget &Subtarget = AsmPrinter.getSubtarget();
556  unsigned ReturnReg = Subtarget.is64Bit() ? X86::RAX : X86::EAX;
557  OutMI = MCInst();
558  OutMI.setOpcode(getRetOpcode(Subtarget));
559  OutMI.addOperand(MCOperand::createReg(ReturnReg));
560  break;
561  }
562 
563  // TAILJMPd, TAILJMPd64, TailJMPd_cc - Lower to the correct jump
564  // instruction.
565  {
566  unsigned Opcode;
567  case X86::TAILJMPr:
568  Opcode = X86::JMP32r;
569  goto SetTailJmpOpcode;
570  case X86::TAILJMPd:
571  case X86::TAILJMPd64:
572  Opcode = X86::JMP_1;
573  goto SetTailJmpOpcode;
574  case X86::TAILJMPd_CC:
575  case X86::TAILJMPd64_CC:
577  static_cast<X86::CondCode>(MI->getOperand(1).getImm()));
578  goto SetTailJmpOpcode;
579 
580  SetTailJmpOpcode:
581  MCOperand Saved = OutMI.getOperand(0);
582  OutMI = MCInst();
583  OutMI.setOpcode(Opcode);
584  OutMI.addOperand(Saved);
585  break;
586  }
587 
588  case X86::DEC16r:
589  case X86::DEC32r:
590  case X86::INC16r:
591  case X86::INC32r:
592  // If we aren't in 64-bit mode we can use the 1-byte inc/dec instructions.
593  if (!AsmPrinter.getSubtarget().is64Bit()) {
594  unsigned Opcode;
595  switch (OutMI.getOpcode()) {
596  default:
597  llvm_unreachable("Invalid opcode");
598  case X86::DEC16r:
599  Opcode = X86::DEC16r_alt;
600  break;
601  case X86::DEC32r:
602  Opcode = X86::DEC32r_alt;
603  break;
604  case X86::INC16r:
605  Opcode = X86::INC16r_alt;
606  break;
607  case X86::INC32r:
608  Opcode = X86::INC32r_alt;
609  break;
610  }
611  OutMI.setOpcode(Opcode);
612  }
613  break;
614 
615  // These are pseudo-ops for OR to help with the OR->ADD transformation. We do
616  // this with an ugly goto in case the resultant OR uses EAX and needs the
617  // short form.
618  case X86::ADD16rr_DB:
619  OutMI.setOpcode(X86::OR16rr);
620  goto ReSimplify;
621  case X86::ADD32rr_DB:
622  OutMI.setOpcode(X86::OR32rr);
623  goto ReSimplify;
624  case X86::ADD64rr_DB:
625  OutMI.setOpcode(X86::OR64rr);
626  goto ReSimplify;
627  case X86::ADD16ri_DB:
628  OutMI.setOpcode(X86::OR16ri);
629  goto ReSimplify;
630  case X86::ADD32ri_DB:
631  OutMI.setOpcode(X86::OR32ri);
632  goto ReSimplify;
633  case X86::ADD64ri32_DB:
634  OutMI.setOpcode(X86::OR64ri32);
635  goto ReSimplify;
636  case X86::ADD16ri8_DB:
637  OutMI.setOpcode(X86::OR16ri8);
638  goto ReSimplify;
639  case X86::ADD32ri8_DB:
640  OutMI.setOpcode(X86::OR32ri8);
641  goto ReSimplify;
642  case X86::ADD64ri8_DB:
643  OutMI.setOpcode(X86::OR64ri8);
644  goto ReSimplify;
645 
646  // Atomic load and store require a separate pseudo-inst because Acquire
647  // implies mayStore and Release implies mayLoad; fix these to regular MOV
648  // instructions here
649  case X86::ACQUIRE_MOV8rm:
650  OutMI.setOpcode(X86::MOV8rm);
651  goto ReSimplify;
652  case X86::ACQUIRE_MOV16rm:
653  OutMI.setOpcode(X86::MOV16rm);
654  goto ReSimplify;
655  case X86::ACQUIRE_MOV32rm:
656  OutMI.setOpcode(X86::MOV32rm);
657  goto ReSimplify;
658  case X86::ACQUIRE_MOV64rm:
659  OutMI.setOpcode(X86::MOV64rm);
660  goto ReSimplify;
661  case X86::RELEASE_MOV8mr:
662  OutMI.setOpcode(X86::MOV8mr);
663  goto ReSimplify;
664  case X86::RELEASE_MOV16mr:
665  OutMI.setOpcode(X86::MOV16mr);
666  goto ReSimplify;
667  case X86::RELEASE_MOV32mr:
668  OutMI.setOpcode(X86::MOV32mr);
669  goto ReSimplify;
670  case X86::RELEASE_MOV64mr:
671  OutMI.setOpcode(X86::MOV64mr);
672  goto ReSimplify;
673  case X86::RELEASE_MOV8mi:
674  OutMI.setOpcode(X86::MOV8mi);
675  goto ReSimplify;
676  case X86::RELEASE_MOV16mi:
677  OutMI.setOpcode(X86::MOV16mi);
678  goto ReSimplify;
679  case X86::RELEASE_MOV32mi:
680  OutMI.setOpcode(X86::MOV32mi);
681  goto ReSimplify;
682  case X86::RELEASE_MOV64mi32:
683  OutMI.setOpcode(X86::MOV64mi32);
684  goto ReSimplify;
685  case X86::RELEASE_ADD8mi:
686  OutMI.setOpcode(X86::ADD8mi);
687  goto ReSimplify;
688  case X86::RELEASE_ADD8mr:
689  OutMI.setOpcode(X86::ADD8mr);
690  goto ReSimplify;
691  case X86::RELEASE_ADD32mi:
692  OutMI.setOpcode(X86::ADD32mi);
693  goto ReSimplify;
694  case X86::RELEASE_ADD32mr:
695  OutMI.setOpcode(X86::ADD32mr);
696  goto ReSimplify;
697  case X86::RELEASE_ADD64mi32:
698  OutMI.setOpcode(X86::ADD64mi32);
699  goto ReSimplify;
700  case X86::RELEASE_ADD64mr:
701  OutMI.setOpcode(X86::ADD64mr);
702  goto ReSimplify;
703  case X86::RELEASE_AND8mi:
704  OutMI.setOpcode(X86::AND8mi);
705  goto ReSimplify;
706  case X86::RELEASE_AND8mr:
707  OutMI.setOpcode(X86::AND8mr);
708  goto ReSimplify;
709  case X86::RELEASE_AND32mi:
710  OutMI.setOpcode(X86::AND32mi);
711  goto ReSimplify;
712  case X86::RELEASE_AND32mr:
713  OutMI.setOpcode(X86::AND32mr);
714  goto ReSimplify;
715  case X86::RELEASE_AND64mi32:
716  OutMI.setOpcode(X86::AND64mi32);
717  goto ReSimplify;
718  case X86::RELEASE_AND64mr:
719  OutMI.setOpcode(X86::AND64mr);
720  goto ReSimplify;
721  case X86::RELEASE_OR8mi:
722  OutMI.setOpcode(X86::OR8mi);
723  goto ReSimplify;
724  case X86::RELEASE_OR8mr:
725  OutMI.setOpcode(X86::OR8mr);
726  goto ReSimplify;
727  case X86::RELEASE_OR32mi:
728  OutMI.setOpcode(X86::OR32mi);
729  goto ReSimplify;
730  case X86::RELEASE_OR32mr:
731  OutMI.setOpcode(X86::OR32mr);
732  goto ReSimplify;
733  case X86::RELEASE_OR64mi32:
734  OutMI.setOpcode(X86::OR64mi32);
735  goto ReSimplify;
736  case X86::RELEASE_OR64mr:
737  OutMI.setOpcode(X86::OR64mr);
738  goto ReSimplify;
739  case X86::RELEASE_XOR8mi:
740  OutMI.setOpcode(X86::XOR8mi);
741  goto ReSimplify;
742  case X86::RELEASE_XOR8mr:
743  OutMI.setOpcode(X86::XOR8mr);
744  goto ReSimplify;
745  case X86::RELEASE_XOR32mi:
746  OutMI.setOpcode(X86::XOR32mi);
747  goto ReSimplify;
748  case X86::RELEASE_XOR32mr:
749  OutMI.setOpcode(X86::XOR32mr);
750  goto ReSimplify;
751  case X86::RELEASE_XOR64mi32:
752  OutMI.setOpcode(X86::XOR64mi32);
753  goto ReSimplify;
754  case X86::RELEASE_XOR64mr:
755  OutMI.setOpcode(X86::XOR64mr);
756  goto ReSimplify;
757  case X86::RELEASE_INC8m:
758  OutMI.setOpcode(X86::INC8m);
759  goto ReSimplify;
760  case X86::RELEASE_INC16m:
761  OutMI.setOpcode(X86::INC16m);
762  goto ReSimplify;
763  case X86::RELEASE_INC32m:
764  OutMI.setOpcode(X86::INC32m);
765  goto ReSimplify;
766  case X86::RELEASE_INC64m:
767  OutMI.setOpcode(X86::INC64m);
768  goto ReSimplify;
769  case X86::RELEASE_DEC8m:
770  OutMI.setOpcode(X86::DEC8m);
771  goto ReSimplify;
772  case X86::RELEASE_DEC16m:
773  OutMI.setOpcode(X86::DEC16m);
774  goto ReSimplify;
775  case X86::RELEASE_DEC32m:
776  OutMI.setOpcode(X86::DEC32m);
777  goto ReSimplify;
778  case X86::RELEASE_DEC64m:
779  OutMI.setOpcode(X86::DEC64m);
780  goto ReSimplify;
781 
782  // We don't currently select the correct instruction form for instructions
783  // which have a short %eax, etc. form. Handle this by custom lowering, for
784  // now.
785  //
786  // Note, we are currently not handling the following instructions:
787  // MOV64ao8, MOV64o8a
788  // XCHG16ar, XCHG32ar, XCHG64ar
789  case X86::MOV8mr_NOREX:
790  case X86::MOV8mr:
791  case X86::MOV8rm_NOREX:
792  case X86::MOV8rm:
793  case X86::MOV16mr:
794  case X86::MOV16rm:
795  case X86::MOV32mr:
796  case X86::MOV32rm: {
797  unsigned NewOpc;
798  switch (OutMI.getOpcode()) {
799  default:
800  llvm_unreachable("Invalid opcode");
801  case X86::MOV8mr_NOREX:
802  case X86::MOV8mr:
803  NewOpc = X86::MOV8o32a;
804  break;
805  case X86::MOV8rm_NOREX:
806  case X86::MOV8rm:
807  NewOpc = X86::MOV8ao32;
808  break;
809  case X86::MOV16mr:
810  NewOpc = X86::MOV16o32a;
811  break;
812  case X86::MOV16rm:
813  NewOpc = X86::MOV16ao32;
814  break;
815  case X86::MOV32mr:
816  NewOpc = X86::MOV32o32a;
817  break;
818  case X86::MOV32rm:
819  NewOpc = X86::MOV32ao32;
820  break;
821  }
822  SimplifyShortMoveForm(AsmPrinter, OutMI, NewOpc);
823  break;
824  }
825 
826  case X86::ADC8ri:
827  case X86::ADC16ri:
828  case X86::ADC32ri:
829  case X86::ADC64ri32:
830  case X86::ADD8ri:
831  case X86::ADD16ri:
832  case X86::ADD32ri:
833  case X86::ADD64ri32:
834  case X86::AND8ri:
835  case X86::AND16ri:
836  case X86::AND32ri:
837  case X86::AND64ri32:
838  case X86::CMP8ri:
839  case X86::CMP16ri:
840  case X86::CMP32ri:
841  case X86::CMP64ri32:
842  case X86::OR8ri:
843  case X86::OR16ri:
844  case X86::OR32ri:
845  case X86::OR64ri32:
846  case X86::SBB8ri:
847  case X86::SBB16ri:
848  case X86::SBB32ri:
849  case X86::SBB64ri32:
850  case X86::SUB8ri:
851  case X86::SUB16ri:
852  case X86::SUB32ri:
853  case X86::SUB64ri32:
854  case X86::TEST8ri:
855  case X86::TEST16ri:
856  case X86::TEST32ri:
857  case X86::TEST64ri32:
858  case X86::XOR8ri:
859  case X86::XOR16ri:
860  case X86::XOR32ri:
861  case X86::XOR64ri32: {
862  unsigned NewOpc;
863  switch (OutMI.getOpcode()) {
864  default:
865  llvm_unreachable("Invalid opcode");
866  case X86::ADC8ri:
867  NewOpc = X86::ADC8i8;
868  break;
869  case X86::ADC16ri:
870  NewOpc = X86::ADC16i16;
871  break;
872  case X86::ADC32ri:
873  NewOpc = X86::ADC32i32;
874  break;
875  case X86::ADC64ri32:
876  NewOpc = X86::ADC64i32;
877  break;
878  case X86::ADD8ri:
879  NewOpc = X86::ADD8i8;
880  break;
881  case X86::ADD16ri:
882  NewOpc = X86::ADD16i16;
883  break;
884  case X86::ADD32ri:
885  NewOpc = X86::ADD32i32;
886  break;
887  case X86::ADD64ri32:
888  NewOpc = X86::ADD64i32;
889  break;
890  case X86::AND8ri:
891  NewOpc = X86::AND8i8;
892  break;
893  case X86::AND16ri:
894  NewOpc = X86::AND16i16;
895  break;
896  case X86::AND32ri:
897  NewOpc = X86::AND32i32;
898  break;
899  case X86::AND64ri32:
900  NewOpc = X86::AND64i32;
901  break;
902  case X86::CMP8ri:
903  NewOpc = X86::CMP8i8;
904  break;
905  case X86::CMP16ri:
906  NewOpc = X86::CMP16i16;
907  break;
908  case X86::CMP32ri:
909  NewOpc = X86::CMP32i32;
910  break;
911  case X86::CMP64ri32:
912  NewOpc = X86::CMP64i32;
913  break;
914  case X86::OR8ri:
915  NewOpc = X86::OR8i8;
916  break;
917  case X86::OR16ri:
918  NewOpc = X86::OR16i16;
919  break;
920  case X86::OR32ri:
921  NewOpc = X86::OR32i32;
922  break;
923  case X86::OR64ri32:
924  NewOpc = X86::OR64i32;
925  break;
926  case X86::SBB8ri:
927  NewOpc = X86::SBB8i8;
928  break;
929  case X86::SBB16ri:
930  NewOpc = X86::SBB16i16;
931  break;
932  case X86::SBB32ri:
933  NewOpc = X86::SBB32i32;
934  break;
935  case X86::SBB64ri32:
936  NewOpc = X86::SBB64i32;
937  break;
938  case X86::SUB8ri:
939  NewOpc = X86::SUB8i8;
940  break;
941  case X86::SUB16ri:
942  NewOpc = X86::SUB16i16;
943  break;
944  case X86::SUB32ri:
945  NewOpc = X86::SUB32i32;
946  break;
947  case X86::SUB64ri32:
948  NewOpc = X86::SUB64i32;
949  break;
950  case X86::TEST8ri:
951  NewOpc = X86::TEST8i8;
952  break;
953  case X86::TEST16ri:
954  NewOpc = X86::TEST16i16;
955  break;
956  case X86::TEST32ri:
957  NewOpc = X86::TEST32i32;
958  break;
959  case X86::TEST64ri32:
960  NewOpc = X86::TEST64i32;
961  break;
962  case X86::XOR8ri:
963  NewOpc = X86::XOR8i8;
964  break;
965  case X86::XOR16ri:
966  NewOpc = X86::XOR16i16;
967  break;
968  case X86::XOR32ri:
969  NewOpc = X86::XOR32i32;
970  break;
971  case X86::XOR64ri32:
972  NewOpc = X86::XOR64i32;
973  break;
974  }
975  SimplifyShortImmForm(OutMI, NewOpc);
976  break;
977  }
978 
979  // Try to shrink some forms of movsx.
980  case X86::MOVSX16rr8:
981  case X86::MOVSX32rr16:
982  case X86::MOVSX64rr32:
983  SimplifyMOVSX(OutMI);
984  break;
985  }
986 }
987 
988 void X86AsmPrinter::LowerTlsAddr(X86MCInstLower &MCInstLowering,
989  const MachineInstr &MI) {
990 
991  bool is64Bits = MI.getOpcode() == X86::TLS_addr64 ||
992  MI.getOpcode() == X86::TLS_base_addr64;
993 
994  bool needsPadding = MI.getOpcode() == X86::TLS_addr64;
995 
996  MCContext &context = OutStreamer->getContext();
997 
998  if (needsPadding)
999  EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
1000 
1002  switch (MI.getOpcode()) {
1003  case X86::TLS_addr32:
1004  case X86::TLS_addr64:
1006  break;
1007  case X86::TLS_base_addr32:
1009  break;
1010  case X86::TLS_base_addr64:
1012  break;
1013  default:
1014  llvm_unreachable("unexpected opcode");
1015  }
1016 
1017  MCSymbol *sym = MCInstLowering.GetSymbolFromOperand(MI.getOperand(3));
1018  const MCSymbolRefExpr *symRef = MCSymbolRefExpr::create(sym, SRVK, context);
1019 
1020  MCInst LEA;
1021  if (is64Bits) {
1022  LEA.setOpcode(X86::LEA64r);
1023  LEA.addOperand(MCOperand::createReg(X86::RDI)); // dest
1024  LEA.addOperand(MCOperand::createReg(X86::RIP)); // base
1025  LEA.addOperand(MCOperand::createImm(1)); // scale
1026  LEA.addOperand(MCOperand::createReg(0)); // index
1027  LEA.addOperand(MCOperand::createExpr(symRef)); // disp
1028  LEA.addOperand(MCOperand::createReg(0)); // seg
1029  } else if (SRVK == MCSymbolRefExpr::VK_TLSLDM) {
1030  LEA.setOpcode(X86::LEA32r);
1033  LEA.addOperand(MCOperand::createImm(1)); // scale
1034  LEA.addOperand(MCOperand::createReg(0)); // index
1035  LEA.addOperand(MCOperand::createExpr(symRef)); // disp
1036  LEA.addOperand(MCOperand::createReg(0)); // seg
1037  } else {
1038  LEA.setOpcode(X86::LEA32r);
1040  LEA.addOperand(MCOperand::createReg(0)); // base
1041  LEA.addOperand(MCOperand::createImm(1)); // scale
1042  LEA.addOperand(MCOperand::createReg(X86::EBX)); // index
1043  LEA.addOperand(MCOperand::createExpr(symRef)); // disp
1044  LEA.addOperand(MCOperand::createReg(0)); // seg
1045  }
1046  EmitAndCountInstruction(LEA);
1047 
1048  if (needsPadding) {
1049  EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
1050  EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
1051  EmitAndCountInstruction(MCInstBuilder(X86::REX64_PREFIX));
1052  }
1053 
1054  StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr";
1055  MCSymbol *tlsGetAddr = context.getOrCreateSymbol(name);
1056  const MCSymbolRefExpr *tlsRef =
1057  MCSymbolRefExpr::create(tlsGetAddr, MCSymbolRefExpr::VK_PLT, context);
1058 
1059  EmitAndCountInstruction(
1060  MCInstBuilder(is64Bits ? X86::CALL64pcrel32 : X86::CALLpcrel32)
1061  .addExpr(tlsRef));
1062 }
1063 
1064 /// \brief Emit the largest nop instruction smaller than or equal to \p NumBytes
1065 /// bytes. Return the size of nop emitted.
1066 static unsigned EmitNop(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
1067  const MCSubtargetInfo &STI) {
1068  // This works only for 64bit. For 32bit we have to do additional checking if
1069  // the CPU supports multi-byte nops.
1070  assert(Is64Bit && "EmitNops only supports X86-64");
1071 
1072  unsigned NopSize;
1073  unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;
1074  Opc = IndexReg = Displacement = SegmentReg = 0;
1075  BaseReg = X86::RAX;
1076  ScaleVal = 1;
1077  switch (NumBytes) {
1078  case 0:
1079  llvm_unreachable("Zero nops?");
1080  break;
1081  case 1:
1082  NopSize = 1;
1083  Opc = X86::NOOP;
1084  break;
1085  case 2:
1086  NopSize = 2;
1087  Opc = X86::XCHG16ar;
1088  break;
1089  case 3:
1090  NopSize = 3;
1091  Opc = X86::NOOPL;
1092  break;
1093  case 4:
1094  NopSize = 4;
1095  Opc = X86::NOOPL;
1096  Displacement = 8;
1097  break;
1098  case 5:
1099  NopSize = 5;
1100  Opc = X86::NOOPL;
1101  Displacement = 8;
1102  IndexReg = X86::RAX;
1103  break;
1104  case 6:
1105  NopSize = 6;
1106  Opc = X86::NOOPW;
1107  Displacement = 8;
1108  IndexReg = X86::RAX;
1109  break;
1110  case 7:
1111  NopSize = 7;
1112  Opc = X86::NOOPL;
1113  Displacement = 512;
1114  break;
1115  case 8:
1116  NopSize = 8;
1117  Opc = X86::NOOPL;
1118  Displacement = 512;
1119  IndexReg = X86::RAX;
1120  break;
1121  case 9:
1122  NopSize = 9;
1123  Opc = X86::NOOPW;
1124  Displacement = 512;
1125  IndexReg = X86::RAX;
1126  break;
1127  default:
1128  NopSize = 10;
1129  Opc = X86::NOOPW;
1130  Displacement = 512;
1131  IndexReg = X86::RAX;
1132  SegmentReg = X86::CS;
1133  break;
1134  }
1135 
1136  unsigned NumPrefixes = std::min(NumBytes - NopSize, 5U);
1137  NopSize += NumPrefixes;
1138  for (unsigned i = 0; i != NumPrefixes; ++i)
1139  OS.EmitBytes("\x66");
1140 
1141  switch (Opc) {
1142  default:
1143  llvm_unreachable("Unexpected opcode");
1144  break;
1145  case X86::NOOP:
1146  OS.EmitInstruction(MCInstBuilder(Opc), STI);
1147  break;
1148  case X86::XCHG16ar:
1149  OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX).addReg(X86::AX), STI);
1150  break;
1151  case X86::NOOPL:
1152  case X86::NOOPW:
1154  .addReg(BaseReg)
1155  .addImm(ScaleVal)
1156  .addReg(IndexReg)
1157  .addImm(Displacement)
1158  .addReg(SegmentReg),
1159  STI);
1160  break;
1161  }
1162  assert(NopSize <= NumBytes && "We overemitted?");
1163  return NopSize;
1164 }
1165 
1166 /// \brief Emit the optimal amount of multi-byte nops on X86.
1167 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
1168  const MCSubtargetInfo &STI) {
1169  unsigned NopsToEmit = NumBytes;
1170  (void)NopsToEmit;
1171  while (NumBytes) {
1172  NumBytes -= EmitNop(OS, NumBytes, Is64Bit, STI);
1173  assert(NopsToEmit >= NumBytes && "Emitted more than I asked for!");
1174  }
1175 }
1176 
1177 void X86AsmPrinter::LowerSTATEPOINT(const MachineInstr &MI,
1178  X86MCInstLower &MCIL) {
1179  assert(Subtarget->is64Bit() && "Statepoint currently only supports X86-64");
1180 
1181  StatepointOpers SOpers(&MI);
1182  if (unsigned PatchBytes = SOpers.getNumPatchBytes()) {
1183  EmitNops(*OutStreamer, PatchBytes, Subtarget->is64Bit(),
1184  getSubtargetInfo());
1185  } else {
1186  // Lower call target and choose correct opcode
1187  const MachineOperand &CallTarget = SOpers.getCallTarget();
1188  MCOperand CallTargetMCOp;
1189  unsigned CallOpcode;
1190  switch (CallTarget.getType()) {
1193  CallTargetMCOp = MCIL.LowerSymbolOperand(
1194  CallTarget, MCIL.GetSymbolFromOperand(CallTarget));
1195  CallOpcode = X86::CALL64pcrel32;
1196  // Currently, we only support relative addressing with statepoints.
1197  // Otherwise, we'll need a scratch register to hold the target
1198  // address. You'll fail asserts during load & relocation if this
1199  // symbol is to far away. (TODO: support non-relative addressing)
1200  break;
1202  CallTargetMCOp = MCOperand::createImm(CallTarget.getImm());
1203  CallOpcode = X86::CALL64pcrel32;
1204  // Currently, we only support relative addressing with statepoints.
1205  // Otherwise, we'll need a scratch register to hold the target
1206  // immediate. You'll fail asserts during load & relocation if this
1207  // address is to far away. (TODO: support non-relative addressing)
1208  break;
1210  // FIXME: Add retpoline support and remove this.
1211  if (Subtarget->useRetpoline())
1212  report_fatal_error("Lowering register statepoints with retpoline not "
1213  "yet implemented.");
1214  CallTargetMCOp = MCOperand::createReg(CallTarget.getReg());
1215  CallOpcode = X86::CALL64r;
1216  break;
1217  default:
1218  llvm_unreachable("Unsupported operand type in statepoint call target");
1219  break;
1220  }
1221 
1222  // Emit call
1223  MCInst CallInst;
1224  CallInst.setOpcode(CallOpcode);
1225  CallInst.addOperand(CallTargetMCOp);
1226  OutStreamer->EmitInstruction(CallInst, getSubtargetInfo());
1227  }
1228 
1229  // Record our statepoint node in the same section used by STACKMAP
1230  // and PATCHPOINT
1231  SM.recordStatepoint(MI);
1232 }
1233 
1234 void X86AsmPrinter::LowerFAULTING_OP(const MachineInstr &FaultingMI,
1235  X86MCInstLower &MCIL) {
1236  // FAULTING_LOAD_OP <def>, <faltinf type>, <MBB handler>,
1237  // <opcode>, <operands>
1238 
1239  unsigned DefRegister = FaultingMI.getOperand(0).getReg();
1241  static_cast<FaultMaps::FaultKind>(FaultingMI.getOperand(1).getImm());
1242  MCSymbol *HandlerLabel = FaultingMI.getOperand(2).getMBB()->getSymbol();
1243  unsigned Opcode = FaultingMI.getOperand(3).getImm();
1244  unsigned OperandsBeginIdx = 4;
1245 
1246  assert(FK < FaultMaps::FaultKindMax && "Invalid Faulting Kind!");
1247  FM.recordFaultingOp(FK, HandlerLabel);
1248 
1249  MCInst MI;
1250  MI.setOpcode(Opcode);
1251 
1252  if (DefRegister != X86::NoRegister)
1253  MI.addOperand(MCOperand::createReg(DefRegister));
1254 
1255  for (auto I = FaultingMI.operands_begin() + OperandsBeginIdx,
1256  E = FaultingMI.operands_end();
1257  I != E; ++I)
1258  if (auto MaybeOperand = MCIL.LowerMachineOperand(&FaultingMI, *I))
1259  MI.addOperand(MaybeOperand.getValue());
1260 
1261  OutStreamer->EmitInstruction(MI, getSubtargetInfo());
1262 }
1263 
1264 void X86AsmPrinter::LowerFENTRY_CALL(const MachineInstr &MI,
1265  X86MCInstLower &MCIL) {
1266  bool Is64Bits = Subtarget->is64Bit();
1267  MCContext &Ctx = OutStreamer->getContext();
1268  MCSymbol *fentry = Ctx.getOrCreateSymbol("__fentry__");
1269  const MCSymbolRefExpr *Op =
1271 
1272  EmitAndCountInstruction(
1273  MCInstBuilder(Is64Bits ? X86::CALL64pcrel32 : X86::CALLpcrel32)
1274  .addExpr(Op));
1275 }
1276 
1277 void X86AsmPrinter::LowerPATCHABLE_OP(const MachineInstr &MI,
1278  X86MCInstLower &MCIL) {
1279  // PATCHABLE_OP minsize, opcode, operands
1280 
1281  unsigned MinSize = MI.getOperand(0).getImm();
1282  unsigned Opcode = MI.getOperand(1).getImm();
1283 
1284  MCInst MCI;
1285  MCI.setOpcode(Opcode);
1286  for (auto &MO : make_range(MI.operands_begin() + 2, MI.operands_end()))
1287  if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO))
1288  MCI.addOperand(MaybeOperand.getValue());
1289 
1290  SmallString<256> Code;
1292  raw_svector_ostream VecOS(Code);
1293  CodeEmitter->encodeInstruction(MCI, VecOS, Fixups, getSubtargetInfo());
1294 
1295  if (Code.size() < MinSize) {
1296  if (MinSize == 2 && Opcode == X86::PUSH64r) {
1297  // This is an optimization that lets us get away without emitting a nop in
1298  // many cases.
1299  //
1300  // NB! In some cases the encoding for PUSH64r (e.g. PUSH64r %r9) takes two
1301  // bytes too, so the check on MinSize is important.
1302  MCI.setOpcode(X86::PUSH64rmr);
1303  } else {
1304  unsigned NopSize = EmitNop(*OutStreamer, MinSize, Subtarget->is64Bit(),
1305  getSubtargetInfo());
1306  assert(NopSize == MinSize && "Could not implement MinSize!");
1307  (void)NopSize;
1308  }
1309  }
1310 
1311  OutStreamer->EmitInstruction(MCI, getSubtargetInfo());
1312 }
1313 
1314 // Lower a stackmap of the form:
1315 // <id>, <shadowBytes>, ...
1316 void X86AsmPrinter::LowerSTACKMAP(const MachineInstr &MI) {
1317  SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
1318  SM.recordStackMap(MI);
1319  unsigned NumShadowBytes = MI.getOperand(1).getImm();
1320  SMShadowTracker.reset(NumShadowBytes);
1321 }
1322 
1323 // Lower a patchpoint of the form:
1324 // [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ...
1325 void X86AsmPrinter::LowerPATCHPOINT(const MachineInstr &MI,
1326  X86MCInstLower &MCIL) {
1327  assert(Subtarget->is64Bit() && "Patchpoint currently only supports X86-64");
1328 
1329  SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
1330 
1331  SM.recordPatchPoint(MI);
1332 
1333  PatchPointOpers opers(&MI);
1334  unsigned ScratchIdx = opers.getNextScratchIdx();
1335  unsigned EncodedBytes = 0;
1336  const MachineOperand &CalleeMO = opers.getCallTarget();
1337 
1338  // Check for null target. If target is non-null (i.e. is non-zero or is
1339  // symbolic) then emit a call.
1340  if (!(CalleeMO.isImm() && !CalleeMO.getImm())) {
1341  MCOperand CalleeMCOp;
1342  switch (CalleeMO.getType()) {
1343  default:
1344  /// FIXME: Add a verifier check for bad callee types.
1345  llvm_unreachable("Unrecognized callee operand type.");
1347  if (CalleeMO.getImm())
1348  CalleeMCOp = MCOperand::createImm(CalleeMO.getImm());
1349  break;
1352  CalleeMCOp = MCIL.LowerSymbolOperand(CalleeMO,
1353  MCIL.GetSymbolFromOperand(CalleeMO));
1354  break;
1355  }
1356 
1357  // Emit MOV to materialize the target address and the CALL to target.
1358  // This is encoded with 12-13 bytes, depending on which register is used.
1359  unsigned ScratchReg = MI.getOperand(ScratchIdx).getReg();
1360  if (X86II::isX86_64ExtendedReg(ScratchReg))
1361  EncodedBytes = 13;
1362  else
1363  EncodedBytes = 12;
1364 
1365  EmitAndCountInstruction(
1366  MCInstBuilder(X86::MOV64ri).addReg(ScratchReg).addOperand(CalleeMCOp));
1367  // FIXME: Add retpoline support and remove this.
1368  if (Subtarget->useRetpoline())
1370  "Lowering patchpoint with retpoline not yet implemented.");
1371  EmitAndCountInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg));
1372  }
1373 
1374  // Emit padding.
1375  unsigned NumBytes = opers.getNumPatchBytes();
1376  assert(NumBytes >= EncodedBytes &&
1377  "Patchpoint can't request size less than the length of a call.");
1378 
1379  EmitNops(*OutStreamer, NumBytes - EncodedBytes, Subtarget->is64Bit(),
1380  getSubtargetInfo());
1381 }
1382 
1383 void X86AsmPrinter::LowerPATCHABLE_EVENT_CALL(const MachineInstr &MI,
1384  X86MCInstLower &MCIL) {
1385  assert(Subtarget->is64Bit() && "XRay custom events only supports X86-64");
1386 
1387  // We want to emit the following pattern, which follows the x86 calling
1388  // convention to prepare for the trampoline call to be patched in.
1389  //
1390  // .p2align 1, ...
1391  // .Lxray_event_sled_N:
1392  // jmp +N // jump across the instrumentation sled
1393  // ... // set up arguments in register
1394  // callq __xray_CustomEvent@plt // force dependency to symbol
1395  // ...
1396  // <jump here>
1397  //
1398  // After patching, it would look something like:
1399  //
1400  // nopw (2-byte nop)
1401  // ...
1402  // callq __xrayCustomEvent // already lowered
1403  // ...
1404  //
1405  // ---
1406  // First we emit the label and the jump.
1407  auto CurSled = OutContext.createTempSymbol("xray_event_sled_", true);
1408  OutStreamer->AddComment("# XRay Custom Event Log");
1409  OutStreamer->EmitCodeAlignment(2);
1410  OutStreamer->EmitLabel(CurSled);
1411 
1412  // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as
1413  // an operand (computed as an offset from the jmp instruction).
1414  // FIXME: Find another less hacky way do force the relative jump.
1415  OutStreamer->EmitBinaryData("\xeb\x0f");
1416 
1417  // The default C calling convention will place two arguments into %rcx and
1418  // %rdx -- so we only work with those.
1419  unsigned DestRegs[] = {X86::RDI, X86::RSI};
1420  bool UsedMask[] = {false, false};
1421  // Filled out in loop.
1422  unsigned SrcRegs[] = {0, 0};
1423 
1424  // Then we put the operands in the %rdi and %rsi registers. We spill the
1425  // values in the register before we clobber them, and mark them as used in
1426  // UsedMask. In case the arguments are already in the correct register, we use
1427  // emit nops appropriately sized to keep the sled the same size in every
1428  // situation.
1429  for (unsigned I = 0; I < MI.getNumOperands(); ++I)
1430  if (auto Op = MCIL.LowerMachineOperand(&MI, MI.getOperand(I))) {
1431  assert(Op->isReg() && "Only support arguments in registers");
1432  SrcRegs[I] = Op->getReg();
1433  if (SrcRegs[I] != DestRegs[I]) {
1434  UsedMask[I] = true;
1435  EmitAndCountInstruction(
1436  MCInstBuilder(X86::PUSH64r).addReg(DestRegs[I]));
1437  } else {
1438  EmitNops(*OutStreamer, 4, Subtarget->is64Bit(), getSubtargetInfo());
1439  }
1440  }
1441 
1442  // Now that the register values are stashed, mov arguments into place.
1443  for (unsigned I = 0; I < MI.getNumOperands(); ++I)
1444  if (SrcRegs[I] != DestRegs[I])
1445  EmitAndCountInstruction(
1446  MCInstBuilder(X86::MOV64rr).addReg(DestRegs[I]).addReg(SrcRegs[I]));
1447 
1448  // We emit a hard dependency on the __xray_CustomEvent symbol, which is the
1449  // name of the trampoline to be implemented by the XRay runtime.
1450  auto TSym = OutContext.getOrCreateSymbol("__xray_CustomEvent");
1452  if (isPositionIndependent())
1454 
1455  // Emit the call instruction.
1456  EmitAndCountInstruction(MCInstBuilder(X86::CALL64pcrel32)
1457  .addOperand(MCIL.LowerSymbolOperand(TOp, TSym)));
1458 
1459  // Restore caller-saved and used registers.
1460  for (unsigned I = sizeof UsedMask; I-- > 0;)
1461  if (UsedMask[I])
1462  EmitAndCountInstruction(MCInstBuilder(X86::POP64r).addReg(DestRegs[I]));
1463  else
1464  EmitNops(*OutStreamer, 1, Subtarget->is64Bit(), getSubtargetInfo());
1465 
1466  OutStreamer->AddComment("xray custom event end.");
1467 
1468  // Record the sled version. Older versions of this sled were spelled
1469  // differently, so we let the runtime handle the different offsets we're
1470  // using.
1471  recordSled(CurSled, MI, SledKind::CUSTOM_EVENT, 1);
1472 }
1473 
1474 void X86AsmPrinter::LowerPATCHABLE_TYPED_EVENT_CALL(const MachineInstr &MI,
1475  X86MCInstLower &MCIL) {
1476  assert(Subtarget->is64Bit() && "XRay typed events only supports X86-64");
1477 
1478  // We want to emit the following pattern, which follows the x86 calling
1479  // convention to prepare for the trampoline call to be patched in.
1480  //
1481  // .p2align 1, ...
1482  // .Lxray_event_sled_N:
1483  // jmp +N // jump across the instrumentation sled
1484  // ... // set up arguments in register
1485  // callq __xray_TypedEvent@plt // force dependency to symbol
1486  // ...
1487  // <jump here>
1488  //
1489  // After patching, it would look something like:
1490  //
1491  // nopw (2-byte nop)
1492  // ...
1493  // callq __xrayTypedEvent // already lowered
1494  // ...
1495  //
1496  // ---
1497  // First we emit the label and the jump.
1498  auto CurSled = OutContext.createTempSymbol("xray_typed_event_sled_", true);
1499  OutStreamer->AddComment("# XRay Typed Event Log");
1500  OutStreamer->EmitCodeAlignment(2);
1501  OutStreamer->EmitLabel(CurSled);
1502 
1503  // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as
1504  // an operand (computed as an offset from the jmp instruction).
1505  // FIXME: Find another less hacky way do force the relative jump.
1506  OutStreamer->EmitBinaryData("\xeb\x14");
1507 
1508  // An x86-64 convention may place three arguments into %rcx, %rdx, and R8,
1509  // so we'll work with those. Or we may be called via SystemV, in which case
1510  // we don't have to do any translation.
1511  unsigned DestRegs[] = {X86::RDI, X86::RSI, X86::RDX};
1512  bool UsedMask[] = {false, false, false};
1513 
1514  // Will fill out src regs in the loop.
1515  unsigned SrcRegs[] = {0, 0, 0};
1516 
1517  // Then we put the operands in the SystemV registers. We spill the values in
1518  // the registers before we clobber them, and mark them as used in UsedMask.
1519  // In case the arguments are already in the correct register, we emit nops
1520  // appropriately sized to keep the sled the same size in every situation.
1521  for (unsigned I = 0; I < MI.getNumOperands(); ++I)
1522  if (auto Op = MCIL.LowerMachineOperand(&MI, MI.getOperand(I))) {
1523  // TODO: Is register only support adequate?
1524  assert(Op->isReg() && "Only supports arguments in registers");
1525  SrcRegs[I] = Op->getReg();
1526  if (SrcRegs[I] != DestRegs[I]) {
1527  UsedMask[I] = true;
1528  EmitAndCountInstruction(
1529  MCInstBuilder(X86::PUSH64r).addReg(DestRegs[I]));
1530  } else {
1531  EmitNops(*OutStreamer, 4, Subtarget->is64Bit(), getSubtargetInfo());
1532  }
1533  }
1534 
1535  // In the above loop we only stash all of the destination registers or emit
1536  // nops if the arguments are already in the right place. Doing the actually
1537  // moving is postponed until after all the registers are stashed so nothing
1538  // is clobbers. We've already added nops to account for the size of mov and
1539  // push if the register is in the right place, so we only have to worry about
1540  // emitting movs.
1541  for (unsigned I = 0; I < MI.getNumOperands(); ++I)
1542  if (UsedMask[I])
1543  EmitAndCountInstruction(
1544  MCInstBuilder(X86::MOV64rr).addReg(DestRegs[I]).addReg(SrcRegs[I]));
1545 
1546  // We emit a hard dependency on the __xray_TypedEvent symbol, which is the
1547  // name of the trampoline to be implemented by the XRay runtime.
1548  auto TSym = OutContext.getOrCreateSymbol("__xray_TypedEvent");
1550  if (isPositionIndependent())
1552 
1553  // Emit the call instruction.
1554  EmitAndCountInstruction(MCInstBuilder(X86::CALL64pcrel32)
1555  .addOperand(MCIL.LowerSymbolOperand(TOp, TSym)));
1556 
1557  // Restore caller-saved and used registers.
1558  for (unsigned I = sizeof UsedMask; I-- > 0;)
1559  if (UsedMask[I])
1560  EmitAndCountInstruction(MCInstBuilder(X86::POP64r).addReg(DestRegs[I]));
1561  else
1562  EmitNops(*OutStreamer, 1, Subtarget->is64Bit(), getSubtargetInfo());
1563 
1564  OutStreamer->AddComment("xray typed event end.");
1565 
1566  // Record the sled version.
1567  recordSled(CurSled, MI, SledKind::TYPED_EVENT, 0);
1568 }
1569 
1570 void X86AsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI,
1571  X86MCInstLower &MCIL) {
1572  // We want to emit the following pattern:
1573  //
1574  // .p2align 1, ...
1575  // .Lxray_sled_N:
1576  // jmp .tmpN
1577  // # 9 bytes worth of noops
1578  //
1579  // We need the 9 bytes because at runtime, we'd be patching over the full 11
1580  // bytes with the following pattern:
1581  //
1582  // mov %r10, <function id, 32-bit> // 6 bytes
1583  // call <relative offset, 32-bits> // 5 bytes
1584  //
1585  auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
1586  OutStreamer->EmitCodeAlignment(2);
1587  OutStreamer->EmitLabel(CurSled);
1588 
1589  // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as
1590  // an operand (computed as an offset from the jmp instruction).
1591  // FIXME: Find another less hacky way do force the relative jump.
1592  OutStreamer->EmitBytes("\xeb\x09");
1593  EmitNops(*OutStreamer, 9, Subtarget->is64Bit(), getSubtargetInfo());
1594  recordSled(CurSled, MI, SledKind::FUNCTION_ENTER);
1595 }
1596 
1597 void X86AsmPrinter::LowerPATCHABLE_RET(const MachineInstr &MI,
1598  X86MCInstLower &MCIL) {
1599  // Since PATCHABLE_RET takes the opcode of the return statement as an
1600  // argument, we use that to emit the correct form of the RET that we want.
1601  // i.e. when we see this:
1602  //
1603  // PATCHABLE_RET X86::RET ...
1604  //
1605  // We should emit the RET followed by sleds.
1606  //
1607  // .p2align 1, ...
1608  // .Lxray_sled_N:
1609  // ret # or equivalent instruction
1610  // # 10 bytes worth of noops
1611  //
1612  // This just makes sure that the alignment for the next instruction is 2.
1613  auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
1614  OutStreamer->EmitCodeAlignment(2);
1615  OutStreamer->EmitLabel(CurSled);
1616  unsigned OpCode = MI.getOperand(0).getImm();
1617  MCInst Ret;
1618  Ret.setOpcode(OpCode);
1619  for (auto &MO : make_range(MI.operands_begin() + 1, MI.operands_end()))
1620  if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO))
1621  Ret.addOperand(MaybeOperand.getValue());
1622  OutStreamer->EmitInstruction(Ret, getSubtargetInfo());
1623  EmitNops(*OutStreamer, 10, Subtarget->is64Bit(), getSubtargetInfo());
1624  recordSled(CurSled, MI, SledKind::FUNCTION_EXIT);
1625 }
1626 
1627 void X86AsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI,
1628  X86MCInstLower &MCIL) {
1629  // Like PATCHABLE_RET, we have the actual instruction in the operands to this
1630  // instruction so we lower that particular instruction and its operands.
1631  // Unlike PATCHABLE_RET though, we put the sled before the JMP, much like how
1632  // we do it for PATCHABLE_FUNCTION_ENTER. The sled should be very similar to
1633  // the PATCHABLE_FUNCTION_ENTER case, followed by the lowering of the actual
1634  // tail call much like how we have it in PATCHABLE_RET.
1635  auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
1636  OutStreamer->EmitCodeAlignment(2);
1637  OutStreamer->EmitLabel(CurSled);
1639 
1640  // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as
1641  // an operand (computed as an offset from the jmp instruction).
1642  // FIXME: Find another less hacky way do force the relative jump.
1643  OutStreamer->EmitBytes("\xeb\x09");
1644  EmitNops(*OutStreamer, 9, Subtarget->is64Bit(), getSubtargetInfo());
1645  OutStreamer->EmitLabel(Target);
1646  recordSled(CurSled, MI, SledKind::TAIL_CALL);
1647 
1648  unsigned OpCode = MI.getOperand(0).getImm();
1649  MCInst TC;
1650  TC.setOpcode(OpCode);
1651 
1652  // Before emitting the instruction, add a comment to indicate that this is
1653  // indeed a tail call.
1654  OutStreamer->AddComment("TAILCALL");
1655  for (auto &MO : make_range(MI.operands_begin() + 1, MI.operands_end()))
1656  if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO))
1657  TC.addOperand(MaybeOperand.getValue());
1658  OutStreamer->EmitInstruction(TC, getSubtargetInfo());
1659 }
1660 
1661 // Returns instruction preceding MBBI in MachineFunction.
1662 // If MBBI is the first instruction of the first basic block, returns null.
1665  const MachineBasicBlock *MBB = MBBI->getParent();
1666  while (MBBI == MBB->begin()) {
1667  if (MBB == &MBB->getParent()->front())
1669  MBB = MBB->getPrevNode();
1670  MBBI = MBB->end();
1671  }
1672  return --MBBI;
1673 }
1674 
1676  const MachineOperand &Op) {
1677  if (!Op.isCPI())
1678  return nullptr;
1679 
1682  const MachineConstantPoolEntry &ConstantEntry = Constants[Op.getIndex()];
1683 
1684  // Bail if this is a machine constant pool entry, we won't be able to dig out
1685  // anything useful.
1686  if (ConstantEntry.isMachineConstantPoolEntry())
1687  return nullptr;
1688 
1689  auto *C = dyn_cast<Constant>(ConstantEntry.Val.ConstVal);
1690  assert((!C || ConstantEntry.getType() == C->getType()) &&
1691  "Expected a constant of the same type!");
1692  return C;
1693 }
1694 
1695 static std::string getShuffleComment(const MachineInstr *MI, unsigned SrcOp1Idx,
1696  unsigned SrcOp2Idx, ArrayRef<int> Mask) {
1697  std::string Comment;
1698 
1699  // Compute the name for a register. This is really goofy because we have
1700  // multiple instruction printers that could (in theory) use different
1701  // names. Fortunately most people use the ATT style (outside of Windows)
1702  // and they actually agree on register naming here. Ultimately, this is
1703  // a comment, and so its OK if it isn't perfect.
1704  auto GetRegisterName = [](unsigned RegNum) -> StringRef {
1705  return X86ATTInstPrinter::getRegisterName(RegNum);
1706  };
1707 
1708  const MachineOperand &DstOp = MI->getOperand(0);
1709  const MachineOperand &SrcOp1 = MI->getOperand(SrcOp1Idx);
1710  const MachineOperand &SrcOp2 = MI->getOperand(SrcOp2Idx);
1711 
1712  StringRef DstName = DstOp.isReg() ? GetRegisterName(DstOp.getReg()) : "mem";
1713  StringRef Src1Name =
1714  SrcOp1.isReg() ? GetRegisterName(SrcOp1.getReg()) : "mem";
1715  StringRef Src2Name =
1716  SrcOp2.isReg() ? GetRegisterName(SrcOp2.getReg()) : "mem";
1717 
1718  // One source operand, fix the mask to print all elements in one span.
1719  SmallVector<int, 8> ShuffleMask(Mask.begin(), Mask.end());
1720  if (Src1Name == Src2Name)
1721  for (int i = 0, e = ShuffleMask.size(); i != e; ++i)
1722  if (ShuffleMask[i] >= e)
1723  ShuffleMask[i] -= e;
1724 
1725  raw_string_ostream CS(Comment);
1726  CS << DstName;
1727 
1728  // Handle AVX512 MASK/MASXZ write mask comments.
1729  // MASK: zmmX {%kY}
1730  // MASKZ: zmmX {%kY} {z}
1731  if (SrcOp1Idx > 1) {
1732  assert((SrcOp1Idx == 2 || SrcOp1Idx == 3) && "Unexpected writemask");
1733 
1734  const MachineOperand &WriteMaskOp = MI->getOperand(SrcOp1Idx - 1);
1735  if (WriteMaskOp.isReg()) {
1736  CS << " {%" << GetRegisterName(WriteMaskOp.getReg()) << "}";
1737 
1738  if (SrcOp1Idx == 2) {
1739  CS << " {z}";
1740  }
1741  }
1742  }
1743 
1744  CS << " = ";
1745 
1746  for (int i = 0, e = ShuffleMask.size(); i != e; ++i) {
1747  if (i != 0)
1748  CS << ",";
1749  if (ShuffleMask[i] == SM_SentinelZero) {
1750  CS << "zero";
1751  continue;
1752  }
1753 
1754  // Otherwise, it must come from src1 or src2. Print the span of elements
1755  // that comes from this src.
1756  bool isSrc1 = ShuffleMask[i] < (int)e;
1757  CS << (isSrc1 ? Src1Name : Src2Name) << '[';
1758 
1759  bool IsFirst = true;
1760  while (i != e && ShuffleMask[i] != SM_SentinelZero &&
1761  (ShuffleMask[i] < (int)e) == isSrc1) {
1762  if (!IsFirst)
1763  CS << ',';
1764  else
1765  IsFirst = false;
1766  if (ShuffleMask[i] == SM_SentinelUndef)
1767  CS << "u";
1768  else
1769  CS << ShuffleMask[i] % (int)e;
1770  ++i;
1771  }
1772  CS << ']';
1773  --i; // For loop increments element #.
1774  }
1775  CS.flush();
1776 
1777  return Comment;
1778 }
1779 
1780 static void printConstant(const Constant *COp, raw_ostream &CS) {
1781  if (isa<UndefValue>(COp)) {
1782  CS << "u";
1783  } else if (auto *CI = dyn_cast<ConstantInt>(COp)) {
1784  if (CI->getBitWidth() <= 64) {
1785  CS << CI->getZExtValue();
1786  } else {
1787  // print multi-word constant as (w0,w1)
1788  const auto &Val = CI->getValue();
1789  CS << "(";
1790  for (int i = 0, N = Val.getNumWords(); i < N; ++i) {
1791  if (i > 0)
1792  CS << ",";
1793  CS << Val.getRawData()[i];
1794  }
1795  CS << ")";
1796  }
1797  } else if (auto *CF = dyn_cast<ConstantFP>(COp)) {
1798  SmallString<32> Str;
1799  CF->getValueAPF().toString(Str);
1800  CS << Str;
1801  } else {
1802  CS << "?";
1803  }
1804 }
1805 
1806 void X86AsmPrinter::EmitSEHInstruction(const MachineInstr *MI) {
1807  assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?");
1808  assert(getSubtarget().isOSWindows() && "SEH_ instruction Windows only");
1809  const X86RegisterInfo *RI =
1810  MF->getSubtarget<X86Subtarget>().getRegisterInfo();
1811 
1812  // Use the .cv_fpo directives if we're emitting CodeView on 32-bit x86.
1813  if (EmitFPOData) {
1814  X86TargetStreamer *XTS =
1815  static_cast<X86TargetStreamer *>(OutStreamer->getTargetStreamer());
1816  switch (MI->getOpcode()) {
1817  case X86::SEH_PushReg:
1818  XTS->emitFPOPushReg(MI->getOperand(0).getImm());
1819  break;
1820  case X86::SEH_StackAlloc:
1821  XTS->emitFPOStackAlloc(MI->getOperand(0).getImm());
1822  break;
1823  case X86::SEH_SetFrame:
1824  assert(MI->getOperand(1).getImm() == 0 &&
1825  ".cv_fpo_setframe takes no offset");
1826  XTS->emitFPOSetFrame(MI->getOperand(0).getImm());
1827  break;
1828  case X86::SEH_EndPrologue:
1829  XTS->emitFPOEndPrologue();
1830  break;
1831  case X86::SEH_SaveReg:
1832  case X86::SEH_SaveXMM:
1833  case X86::SEH_PushFrame:
1834  llvm_unreachable("SEH_ directive incompatible with FPO");
1835  break;
1836  default:
1837  llvm_unreachable("expected SEH_ instruction");
1838  }
1839  return;
1840  }
1841 
1842  // Otherwise, use the .seh_ directives for all other Windows platforms.
1843  switch (MI->getOpcode()) {
1844  case X86::SEH_PushReg:
1845  OutStreamer->EmitWinCFIPushReg(
1846  RI->getSEHRegNum(MI->getOperand(0).getImm()));
1847  break;
1848 
1849  case X86::SEH_SaveReg:
1850  OutStreamer->EmitWinCFISaveReg(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1851  MI->getOperand(1).getImm());
1852  break;
1853 
1854  case X86::SEH_SaveXMM:
1855  OutStreamer->EmitWinCFISaveXMM(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1856  MI->getOperand(1).getImm());
1857  break;
1858 
1859  case X86::SEH_StackAlloc:
1860  OutStreamer->EmitWinCFIAllocStack(MI->getOperand(0).getImm());
1861  break;
1862 
1863  case X86::SEH_SetFrame:
1864  OutStreamer->EmitWinCFISetFrame(
1865  RI->getSEHRegNum(MI->getOperand(0).getImm()),
1866  MI->getOperand(1).getImm());
1867  break;
1868 
1869  case X86::SEH_PushFrame:
1870  OutStreamer->EmitWinCFIPushFrame(MI->getOperand(0).getImm());
1871  break;
1872 
1873  case X86::SEH_EndPrologue:
1874  OutStreamer->EmitWinCFIEndProlog();
1875  break;
1876 
1877  default:
1878  llvm_unreachable("expected SEH_ instruction");
1879  }
1880 }
1881 
1883  X86MCInstLower MCInstLowering(*MF, *this);
1884  const X86RegisterInfo *RI =
1885  MF->getSubtarget<X86Subtarget>().getRegisterInfo();
1886 
1887  // Add a comment about EVEX-2-VEX compression for AVX-512 instrs that
1888  // are compressed from EVEX encoding to VEX encoding.
1891  OutStreamer->AddComment("EVEX TO VEX Compression ", false);
1892  }
1893 
1894  switch (MI->getOpcode()) {
1895  case TargetOpcode::DBG_VALUE:
1896  llvm_unreachable("Should be handled target independently");
1897 
1898  // Emit nothing here but a comment if we can.
1899  case X86::Int_MemBarrier:
1900  OutStreamer->emitRawComment("MEMBARRIER");
1901  return;
1902 
1903  case X86::EH_RETURN:
1904  case X86::EH_RETURN64: {
1905  // Lower these as normal, but add some comments.
1906  unsigned Reg = MI->getOperand(0).getReg();
1907  OutStreamer->AddComment(StringRef("eh_return, addr: %") +
1909  break;
1910  }
1911  case X86::CLEANUPRET: {
1912  // Lower these as normal, but add some comments.
1913  OutStreamer->AddComment("CLEANUPRET");
1914  break;
1915  }
1916 
1917  case X86::CATCHRET: {
1918  // Lower these as normal, but add some comments.
1919  OutStreamer->AddComment("CATCHRET");
1920  break;
1921  }
1922 
1923  case X86::TAILJMPr:
1924  case X86::TAILJMPm:
1925  case X86::TAILJMPd:
1926  case X86::TAILJMPd_CC:
1927  case X86::TAILJMPr64:
1928  case X86::TAILJMPm64:
1929  case X86::TAILJMPd64:
1930  case X86::TAILJMPd64_CC:
1931  case X86::TAILJMPr64_REX:
1932  case X86::TAILJMPm64_REX:
1933  // Lower these as normal, but add some comments.
1934  OutStreamer->AddComment("TAILCALL");
1935  break;
1936 
1937  case X86::TLS_addr32:
1938  case X86::TLS_addr64:
1939  case X86::TLS_base_addr32:
1940  case X86::TLS_base_addr64:
1941  return LowerTlsAddr(MCInstLowering, *MI);
1942 
1943  case X86::MOVPC32r: {
1944  // This is a pseudo op for a two instruction sequence with a label, which
1945  // looks like:
1946  // call "L1$pb"
1947  // "L1$pb":
1948  // popl %esi
1949 
1950  // Emit the call.
1951  MCSymbol *PICBase = MF->getPICBaseSymbol();
1952  // FIXME: We would like an efficient form for this, so we don't have to do a
1953  // lot of extra uniquing.
1954  EmitAndCountInstruction(
1955  MCInstBuilder(X86::CALLpcrel32)
1956  .addExpr(MCSymbolRefExpr::create(PICBase, OutContext)));
1957 
1958  const X86FrameLowering *FrameLowering =
1959  MF->getSubtarget<X86Subtarget>().getFrameLowering();
1960  bool hasFP = FrameLowering->hasFP(*MF);
1961 
1962  // TODO: This is needed only if we require precise CFA.
1963  bool HasActiveDwarfFrame = OutStreamer->getNumFrameInfos() &&
1964  !OutStreamer->getDwarfFrameInfos().back().End;
1965 
1966  int stackGrowth = -RI->getSlotSize();
1967 
1968  if (HasActiveDwarfFrame && !hasFP) {
1969  OutStreamer->EmitCFIAdjustCfaOffset(-stackGrowth);
1970  }
1971 
1972  // Emit the label.
1973  OutStreamer->EmitLabel(PICBase);
1974 
1975  // popl $reg
1976  EmitAndCountInstruction(
1977  MCInstBuilder(X86::POP32r).addReg(MI->getOperand(0).getReg()));
1978 
1979  if (HasActiveDwarfFrame && !hasFP) {
1980  OutStreamer->EmitCFIAdjustCfaOffset(stackGrowth);
1981  }
1982  return;
1983  }
1984 
1985  case X86::ADD32ri: {
1986  // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
1988  break;
1989 
1990  // Okay, we have something like:
1991  // EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
1992 
1993  // For this, we want to print something like:
1994  // MYGLOBAL + (. - PICBASE)
1995  // However, we can't generate a ".", so just emit a new label here and refer
1996  // to it.
1997  MCSymbol *DotSym = OutContext.createTempSymbol();
1998  OutStreamer->EmitLabel(DotSym);
1999 
2000  // Now that we have emitted the label, lower the complex operand expression.
2001  MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
2002 
2003  const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext);
2004  const MCExpr *PICBase =
2006  DotExpr = MCBinaryExpr::createSub(DotExpr, PICBase, OutContext);
2007 
2008  DotExpr = MCBinaryExpr::createAdd(
2009  MCSymbolRefExpr::create(OpSym, OutContext), DotExpr, OutContext);
2010 
2011  EmitAndCountInstruction(MCInstBuilder(X86::ADD32ri)
2012  .addReg(MI->getOperand(0).getReg())
2013  .addReg(MI->getOperand(1).getReg())
2014  .addExpr(DotExpr));
2015  return;
2016  }
2017  case TargetOpcode::STATEPOINT:
2018  return LowerSTATEPOINT(*MI, MCInstLowering);
2019 
2020  case TargetOpcode::FAULTING_OP:
2021  return LowerFAULTING_OP(*MI, MCInstLowering);
2022 
2023  case TargetOpcode::FENTRY_CALL:
2024  return LowerFENTRY_CALL(*MI, MCInstLowering);
2025 
2026  case TargetOpcode::PATCHABLE_OP:
2027  return LowerPATCHABLE_OP(*MI, MCInstLowering);
2028 
2029  case TargetOpcode::STACKMAP:
2030  return LowerSTACKMAP(*MI);
2031 
2032  case TargetOpcode::PATCHPOINT:
2033  return LowerPATCHPOINT(*MI, MCInstLowering);
2034 
2035  case TargetOpcode::PATCHABLE_FUNCTION_ENTER:
2036  return LowerPATCHABLE_FUNCTION_ENTER(*MI, MCInstLowering);
2037 
2038  case TargetOpcode::PATCHABLE_RET:
2039  return LowerPATCHABLE_RET(*MI, MCInstLowering);
2040 
2041  case TargetOpcode::PATCHABLE_TAIL_CALL:
2042  return LowerPATCHABLE_TAIL_CALL(*MI, MCInstLowering);
2043 
2044  case TargetOpcode::PATCHABLE_EVENT_CALL:
2045  return LowerPATCHABLE_EVENT_CALL(*MI, MCInstLowering);
2046 
2047  case TargetOpcode::PATCHABLE_TYPED_EVENT_CALL:
2048  return LowerPATCHABLE_TYPED_EVENT_CALL(*MI, MCInstLowering);
2049 
2050  case X86::MORESTACK_RET:
2051  EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
2052  return;
2053 
2054  case X86::MORESTACK_RET_RESTORE_R10:
2055  // Return, then restore R10.
2056  EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
2057  EmitAndCountInstruction(
2058  MCInstBuilder(X86::MOV64rr).addReg(X86::R10).addReg(X86::RAX));
2059  return;
2060 
2061  case X86::SEH_PushReg:
2062  case X86::SEH_SaveReg:
2063  case X86::SEH_SaveXMM:
2064  case X86::SEH_StackAlloc:
2065  case X86::SEH_SetFrame:
2066  case X86::SEH_PushFrame:
2067  case X86::SEH_EndPrologue:
2068  EmitSEHInstruction(MI);
2069  return;
2070 
2071  case X86::SEH_Epilogue: {
2072  assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?");
2074  // Check if preceded by a call and emit nop if so.
2075  for (MBBI = PrevCrossBBInst(MBBI);
2077  MBBI = PrevCrossBBInst(MBBI)) {
2078  // Conservatively assume that pseudo instructions don't emit code and keep
2079  // looking for a call. We may emit an unnecessary nop in some cases.
2080  if (!MBBI->isPseudo()) {
2081  if (MBBI->isCall())
2082  EmitAndCountInstruction(MCInstBuilder(X86::NOOP));
2083  break;
2084  }
2085  }
2086  return;
2087  }
2088 
2089  // Lower PSHUFB and VPERMILP normally but add a comment if we can find
2090  // a constant shuffle mask. We won't be able to do this at the MC layer
2091  // because the mask isn't an immediate.
2092  case X86::PSHUFBrm:
2093  case X86::VPSHUFBrm:
2094  case X86::VPSHUFBYrm:
2095  case X86::VPSHUFBZ128rm:
2096  case X86::VPSHUFBZ128rmk:
2097  case X86::VPSHUFBZ128rmkz:
2098  case X86::VPSHUFBZ256rm:
2099  case X86::VPSHUFBZ256rmk:
2100  case X86::VPSHUFBZ256rmkz:
2101  case X86::VPSHUFBZrm:
2102  case X86::VPSHUFBZrmk:
2103  case X86::VPSHUFBZrmkz: {
2104  if (!OutStreamer->isVerboseAsm())
2105  break;
2106  unsigned SrcIdx, MaskIdx;
2107  switch (MI->getOpcode()) {
2108  default:
2109  llvm_unreachable("Invalid opcode");
2110  case X86::PSHUFBrm:
2111  case X86::VPSHUFBrm:
2112  case X86::VPSHUFBYrm:
2113  case X86::VPSHUFBZ128rm:
2114  case X86::VPSHUFBZ256rm:
2115  case X86::VPSHUFBZrm:
2116  SrcIdx = 1;
2117  MaskIdx = 5;
2118  break;
2119  case X86::VPSHUFBZ128rmkz:
2120  case X86::VPSHUFBZ256rmkz:
2121  case X86::VPSHUFBZrmkz:
2122  SrcIdx = 2;
2123  MaskIdx = 6;
2124  break;
2125  case X86::VPSHUFBZ128rmk:
2126  case X86::VPSHUFBZ256rmk:
2127  case X86::VPSHUFBZrmk:
2128  SrcIdx = 3;
2129  MaskIdx = 7;
2130  break;
2131  }
2132 
2133  assert(MI->getNumOperands() >= 6 &&
2134  "We should always have at least 6 operands!");
2135 
2136  const MachineOperand &MaskOp = MI->getOperand(MaskIdx);
2137  if (auto *C = getConstantFromPool(*MI, MaskOp)) {
2139  DecodePSHUFBMask(C, Mask);
2140  if (!Mask.empty())
2141  OutStreamer->AddComment(getShuffleComment(MI, SrcIdx, SrcIdx, Mask),
2143  }
2144  break;
2145  }
2146 
2147  case X86::VPERMILPSrm:
2148  case X86::VPERMILPSYrm:
2149  case X86::VPERMILPSZ128rm:
2150  case X86::VPERMILPSZ128rmk:
2151  case X86::VPERMILPSZ128rmkz:
2152  case X86::VPERMILPSZ256rm:
2153  case X86::VPERMILPSZ256rmk:
2154  case X86::VPERMILPSZ256rmkz:
2155  case X86::VPERMILPSZrm:
2156  case X86::VPERMILPSZrmk:
2157  case X86::VPERMILPSZrmkz:
2158  case X86::VPERMILPDrm:
2159  case X86::VPERMILPDYrm:
2160  case X86::VPERMILPDZ128rm:
2161  case X86::VPERMILPDZ128rmk:
2162  case X86::VPERMILPDZ128rmkz:
2163  case X86::VPERMILPDZ256rm:
2164  case X86::VPERMILPDZ256rmk:
2165  case X86::VPERMILPDZ256rmkz:
2166  case X86::VPERMILPDZrm:
2167  case X86::VPERMILPDZrmk:
2168  case X86::VPERMILPDZrmkz: {
2169  if (!OutStreamer->isVerboseAsm())
2170  break;
2171  unsigned SrcIdx, MaskIdx;
2172  unsigned ElSize;
2173  switch (MI->getOpcode()) {
2174  default:
2175  llvm_unreachable("Invalid opcode");
2176  case X86::VPERMILPSrm:
2177  case X86::VPERMILPSYrm:
2178  case X86::VPERMILPSZ128rm:
2179  case X86::VPERMILPSZ256rm:
2180  case X86::VPERMILPSZrm:
2181  SrcIdx = 1;
2182  MaskIdx = 5;
2183  ElSize = 32;
2184  break;
2185  case X86::VPERMILPSZ128rmkz:
2186  case X86::VPERMILPSZ256rmkz:
2187  case X86::VPERMILPSZrmkz:
2188  SrcIdx = 2;
2189  MaskIdx = 6;
2190  ElSize = 32;
2191  break;
2192  case X86::VPERMILPSZ128rmk:
2193  case X86::VPERMILPSZ256rmk:
2194  case X86::VPERMILPSZrmk:
2195  SrcIdx = 3;
2196  MaskIdx = 7;
2197  ElSize = 32;
2198  break;
2199  case X86::VPERMILPDrm:
2200  case X86::VPERMILPDYrm:
2201  case X86::VPERMILPDZ128rm:
2202  case X86::VPERMILPDZ256rm:
2203  case X86::VPERMILPDZrm:
2204  SrcIdx = 1;
2205  MaskIdx = 5;
2206  ElSize = 64;
2207  break;
2208  case X86::VPERMILPDZ128rmkz:
2209  case X86::VPERMILPDZ256rmkz:
2210  case X86::VPERMILPDZrmkz:
2211  SrcIdx = 2;
2212  MaskIdx = 6;
2213  ElSize = 64;
2214  break;
2215  case X86::VPERMILPDZ128rmk:
2216  case X86::VPERMILPDZ256rmk:
2217  case X86::VPERMILPDZrmk:
2218  SrcIdx = 3;
2219  MaskIdx = 7;
2220  ElSize = 64;
2221  break;
2222  }
2223 
2224  assert(MI->getNumOperands() >= 6 &&
2225  "We should always have at least 6 operands!");
2226 
2227  const MachineOperand &MaskOp = MI->getOperand(MaskIdx);
2228  if (auto *C = getConstantFromPool(*MI, MaskOp)) {
2230  DecodeVPERMILPMask(C, ElSize, Mask);
2231  if (!Mask.empty())
2232  OutStreamer->AddComment(getShuffleComment(MI, SrcIdx, SrcIdx, Mask),
2234  }
2235  break;
2236  }
2237 
2238  case X86::VPERMIL2PDrm:
2239  case X86::VPERMIL2PSrm:
2240  case X86::VPERMIL2PDYrm:
2241  case X86::VPERMIL2PSYrm: {
2242  if (!OutStreamer->isVerboseAsm())
2243  break;
2244  assert(MI->getNumOperands() >= 8 &&
2245  "We should always have at least 8 operands!");
2246 
2247  const MachineOperand &CtrlOp = MI->getOperand(MI->getNumOperands() - 1);
2248  if (!CtrlOp.isImm())
2249  break;
2250 
2251  unsigned ElSize;
2252  switch (MI->getOpcode()) {
2253  default:
2254  llvm_unreachable("Invalid opcode");
2255  case X86::VPERMIL2PSrm:
2256  case X86::VPERMIL2PSYrm:
2257  ElSize = 32;
2258  break;
2259  case X86::VPERMIL2PDrm:
2260  case X86::VPERMIL2PDYrm:
2261  ElSize = 64;
2262  break;
2263  }
2264 
2265  const MachineOperand &MaskOp = MI->getOperand(6);
2266  if (auto *C = getConstantFromPool(*MI, MaskOp)) {
2268  DecodeVPERMIL2PMask(C, (unsigned)CtrlOp.getImm(), ElSize, Mask);
2269  if (!Mask.empty())
2270  OutStreamer->AddComment(getShuffleComment(MI, 1, 2, Mask),
2272  }
2273  break;
2274  }
2275 
2276  case X86::VPPERMrrm: {
2277  if (!OutStreamer->isVerboseAsm())
2278  break;
2279  assert(MI->getNumOperands() >= 7 &&
2280  "We should always have at least 7 operands!");
2281 
2282  const MachineOperand &MaskOp = MI->getOperand(6);
2283  if (auto *C = getConstantFromPool(*MI, MaskOp)) {
2285  DecodeVPPERMMask(C, Mask);
2286  if (!Mask.empty())
2287  OutStreamer->AddComment(getShuffleComment(MI, 1, 2, Mask),
2289  }
2290  break;
2291  }
2292 
2293  case X86::MMX_MOVQ64rm: {
2294  if (!OutStreamer->isVerboseAsm())
2295  break;
2296  if (MI->getNumOperands() <= 4)
2297  break;
2298  if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) {
2299  std::string Comment;
2300  raw_string_ostream CS(Comment);
2301  const MachineOperand &DstOp = MI->getOperand(0);
2302  CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = ";
2303  if (auto *CF = dyn_cast<ConstantFP>(C)) {
2304  CS << "0x" << CF->getValueAPF().bitcastToAPInt().toString(16, false);
2305  OutStreamer->AddComment(CS.str(), !EnablePrintSchedInfo);
2306  }
2307  }
2308  break;
2309  }
2310 
2311 #define MOV_CASE(Prefix, Suffix) \
2312  case X86::Prefix##MOVAPD##Suffix##rm: \
2313  case X86::Prefix##MOVAPS##Suffix##rm: \
2314  case X86::Prefix##MOVUPD##Suffix##rm: \
2315  case X86::Prefix##MOVUPS##Suffix##rm: \
2316  case X86::Prefix##MOVDQA##Suffix##rm: \
2317  case X86::Prefix##MOVDQU##Suffix##rm:
2318 
2319 #define MOV_AVX512_CASE(Suffix) \
2320  case X86::VMOVDQA64##Suffix##rm: \
2321  case X86::VMOVDQA32##Suffix##rm: \
2322  case X86::VMOVDQU64##Suffix##rm: \
2323  case X86::VMOVDQU32##Suffix##rm: \
2324  case X86::VMOVDQU16##Suffix##rm: \
2325  case X86::VMOVDQU8##Suffix##rm: \
2326  case X86::VMOVAPS##Suffix##rm: \
2327  case X86::VMOVAPD##Suffix##rm: \
2328  case X86::VMOVUPS##Suffix##rm: \
2329  case X86::VMOVUPD##Suffix##rm:
2330 
2331 #define CASE_ALL_MOV_RM() \
2332  MOV_CASE(, ) /* SSE */ \
2333  MOV_CASE(V, ) /* AVX-128 */ \
2334  MOV_CASE(V, Y) /* AVX-256 */ \
2335  MOV_AVX512_CASE(Z) \
2336  MOV_AVX512_CASE(Z256) \
2337  MOV_AVX512_CASE(Z128)
2338 
2339  // For loads from a constant pool to a vector register, print the constant
2340  // loaded.
2341  CASE_ALL_MOV_RM()
2342  case X86::VBROADCASTF128:
2343  case X86::VBROADCASTI128:
2344  case X86::VBROADCASTF32X4Z256rm:
2345  case X86::VBROADCASTF32X4rm:
2346  case X86::VBROADCASTF32X8rm:
2347  case X86::VBROADCASTF64X2Z128rm:
2348  case X86::VBROADCASTF64X2rm:
2349  case X86::VBROADCASTF64X4rm:
2350  case X86::VBROADCASTI32X4Z256rm:
2351  case X86::VBROADCASTI32X4rm:
2352  case X86::VBROADCASTI32X8rm:
2353  case X86::VBROADCASTI64X2Z128rm:
2354  case X86::VBROADCASTI64X2rm:
2355  case X86::VBROADCASTI64X4rm:
2356  if (!OutStreamer->isVerboseAsm())
2357  break;
2358  if (MI->getNumOperands() <= 4)
2359  break;
2360  if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) {
2361  int NumLanes = 1;
2362  // Override NumLanes for the broadcast instructions.
2363  switch (MI->getOpcode()) {
2364  case X86::VBROADCASTF128:
2365  NumLanes = 2;
2366  break;
2367  case X86::VBROADCASTI128:
2368  NumLanes = 2;
2369  break;
2370  case X86::VBROADCASTF32X4Z256rm:
2371  NumLanes = 2;
2372  break;
2373  case X86::VBROADCASTF32X4rm:
2374  NumLanes = 4;
2375  break;
2376  case X86::VBROADCASTF32X8rm:
2377  NumLanes = 2;
2378  break;
2379  case X86::VBROADCASTF64X2Z128rm:
2380  NumLanes = 2;
2381  break;
2382  case X86::VBROADCASTF64X2rm:
2383  NumLanes = 4;
2384  break;
2385  case X86::VBROADCASTF64X4rm:
2386  NumLanes = 2;
2387  break;
2388  case X86::VBROADCASTI32X4Z256rm:
2389  NumLanes = 2;
2390  break;
2391  case X86::VBROADCASTI32X4rm:
2392  NumLanes = 4;
2393  break;
2394  case X86::VBROADCASTI32X8rm:
2395  NumLanes = 2;
2396  break;
2397  case X86::VBROADCASTI64X2Z128rm:
2398  NumLanes = 2;
2399  break;
2400  case X86::VBROADCASTI64X2rm:
2401  NumLanes = 4;
2402  break;
2403  case X86::VBROADCASTI64X4rm:
2404  NumLanes = 2;
2405  break;
2406  }
2407 
2408  std::string Comment;
2409  raw_string_ostream CS(Comment);
2410  const MachineOperand &DstOp = MI->getOperand(0);
2411  CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = ";
2412  if (auto *CDS = dyn_cast<ConstantDataSequential>(C)) {
2413  CS << "[";
2414  for (int l = 0; l != NumLanes; ++l) {
2415  for (int i = 0, NumElements = CDS->getNumElements(); i < NumElements;
2416  ++i) {
2417  if (i != 0 || l != 0)
2418  CS << ",";
2419  if (CDS->getElementType()->isIntegerTy())
2420  CS << CDS->getElementAsInteger(i);
2421  else if (CDS->getElementType()->isFloatTy())
2422  CS << CDS->getElementAsFloat(i);
2423  else if (CDS->getElementType()->isDoubleTy())
2424  CS << CDS->getElementAsDouble(i);
2425  else
2426  CS << "?";
2427  }
2428  }
2429  CS << "]";
2430  OutStreamer->AddComment(CS.str(), !EnablePrintSchedInfo);
2431  } else if (auto *CV = dyn_cast<ConstantVector>(C)) {
2432  CS << "<";
2433  for (int l = 0; l != NumLanes; ++l) {
2434  for (int i = 0, NumOperands = CV->getNumOperands(); i < NumOperands;
2435  ++i) {
2436  if (i != 0 || l != 0)
2437  CS << ",";
2438  printConstant(CV->getOperand(i), CS);
2439  }
2440  }
2441  CS << ">";
2442  OutStreamer->AddComment(CS.str(), !EnablePrintSchedInfo);
2443  }
2444  }
2445  break;
2446  case X86::VBROADCASTSSrm:
2447  case X86::VBROADCASTSSYrm:
2448  case X86::VBROADCASTSSZ128m:
2449  case X86::VBROADCASTSSZ256m:
2450  case X86::VBROADCASTSSZm:
2451  case X86::VBROADCASTSDYrm:
2452  case X86::VBROADCASTSDZ256m:
2453  case X86::VBROADCASTSDZm:
2454  case X86::VPBROADCASTBrm:
2455  case X86::VPBROADCASTBYrm:
2456  case X86::VPBROADCASTBZ128m:
2457  case X86::VPBROADCASTBZ256m:
2458  case X86::VPBROADCASTBZm:
2459  case X86::VPBROADCASTDrm:
2460  case X86::VPBROADCASTDYrm:
2461  case X86::VPBROADCASTDZ128m:
2462  case X86::VPBROADCASTDZ256m:
2463  case X86::VPBROADCASTDZm:
2464  case X86::VPBROADCASTQrm:
2465  case X86::VPBROADCASTQYrm:
2466  case X86::VPBROADCASTQZ128m:
2467  case X86::VPBROADCASTQZ256m:
2468  case X86::VPBROADCASTQZm:
2469  case X86::VPBROADCASTWrm:
2470  case X86::VPBROADCASTWYrm:
2471  case X86::VPBROADCASTWZ128m:
2472  case X86::VPBROADCASTWZ256m:
2473  case X86::VPBROADCASTWZm:
2474  if (!OutStreamer->isVerboseAsm())
2475  break;
2476  if (MI->getNumOperands() <= 4)
2477  break;
2478  if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) {
2479  int NumElts;
2480  switch (MI->getOpcode()) {
2481  default:
2482  llvm_unreachable("Invalid opcode");
2483  case X86::VBROADCASTSSrm:
2484  NumElts = 4;
2485  break;
2486  case X86::VBROADCASTSSYrm:
2487  NumElts = 8;
2488  break;
2489  case X86::VBROADCASTSSZ128m:
2490  NumElts = 4;
2491  break;
2492  case X86::VBROADCASTSSZ256m:
2493  NumElts = 8;
2494  break;
2495  case X86::VBROADCASTSSZm:
2496  NumElts = 16;
2497  break;
2498  case X86::VBROADCASTSDYrm:
2499  NumElts = 4;
2500  break;
2501  case X86::VBROADCASTSDZ256m:
2502  NumElts = 4;
2503  break;
2504  case X86::VBROADCASTSDZm:
2505  NumElts = 8;
2506  break;
2507  case X86::VPBROADCASTBrm:
2508  NumElts = 16;
2509  break;
2510  case X86::VPBROADCASTBYrm:
2511  NumElts = 32;
2512  break;
2513  case X86::VPBROADCASTBZ128m:
2514  NumElts = 16;
2515  break;
2516  case X86::VPBROADCASTBZ256m:
2517  NumElts = 32;
2518  break;
2519  case X86::VPBROADCASTBZm:
2520  NumElts = 64;
2521  break;
2522  case X86::VPBROADCASTDrm:
2523  NumElts = 4;
2524  break;
2525  case X86::VPBROADCASTDYrm:
2526  NumElts = 8;
2527  break;
2528  case X86::VPBROADCASTDZ128m:
2529  NumElts = 4;
2530  break;
2531  case X86::VPBROADCASTDZ256m:
2532  NumElts = 8;
2533  break;
2534  case X86::VPBROADCASTDZm:
2535  NumElts = 16;
2536  break;
2537  case X86::VPBROADCASTQrm:
2538  NumElts = 2;
2539  break;
2540  case X86::VPBROADCASTQYrm:
2541  NumElts = 4;
2542  break;
2543  case X86::VPBROADCASTQZ128m:
2544  NumElts = 2;
2545  break;
2546  case X86::VPBROADCASTQZ256m:
2547  NumElts = 4;
2548  break;
2549  case X86::VPBROADCASTQZm:
2550  NumElts = 8;
2551  break;
2552  case X86::VPBROADCASTWrm:
2553  NumElts = 8;
2554  break;
2555  case X86::VPBROADCASTWYrm:
2556  NumElts = 16;
2557  break;
2558  case X86::VPBROADCASTWZ128m:
2559  NumElts = 8;
2560  break;
2561  case X86::VPBROADCASTWZ256m:
2562  NumElts = 16;
2563  break;
2564  case X86::VPBROADCASTWZm:
2565  NumElts = 32;
2566  break;
2567  }
2568 
2569  std::string Comment;
2570  raw_string_ostream CS(Comment);
2571  const MachineOperand &DstOp = MI->getOperand(0);
2572  CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = ";
2573  CS << "[";
2574  for (int i = 0; i != NumElts; ++i) {
2575  if (i != 0)
2576  CS << ",";
2577  printConstant(C, CS);
2578  }
2579  CS << "]";
2580  OutStreamer->AddComment(CS.str(), !EnablePrintSchedInfo);
2581  }
2582  }
2583 
2584  MCInst TmpInst;
2585  MCInstLowering.Lower(MI, TmpInst);
2587  TmpInst.setFlags(TmpInst.getFlags() | X86::NO_SCHED_INFO);
2588 
2589  // Stackmap shadows cannot include branch targets, so we can count the bytes
2590  // in a call towards the shadow, but must ensure that the no thread returns
2591  // in to the stackmap shadow. The only way to achieve this is if the call
2592  // is at the end of the shadow.
2593  if (MI->isCall()) {
2594  // Count then size of the call towards the shadow
2595  SMShadowTracker.count(TmpInst, getSubtargetInfo(), CodeEmitter.get());
2596  // Then flush the shadow so that we fill with nops before the call, not
2597  // after it.
2598  SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
2599  // Then emit the call
2600  OutStreamer->EmitInstruction(TmpInst, getSubtargetInfo());
2601  return;
2602  }
2603 
2604  EmitAndCountInstruction(TmpInst);
2605 }
unsigned getTargetFlags() const
MO_SECREL - On a symbol operand this indicates that the immediate is the offset from beginning of sec...
Definition: X86BaseInfo.h:228
const NoneType None
Definition: None.h:24
unsigned GetCondBranchFromCond(CondCode CC)
uint64_t CallInst * C
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:493
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
bool isImm() const
Definition: MCInst.h:59
mop_iterator operands_end()
Definition: MachineInstr.h:330
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
unsigned getNextScratchIdx(unsigned StartIdx=0) const
Get the next scratch register operand index.
Definition: StackMaps.cpp:70
static const char * getRegisterName(unsigned RegNo)
virtual void EmitWinCFIPushReg(unsigned Register, SMLoc Loc=SMLoc())
Definition: MCStreamer.cpp:697
virtual bool emitFPOSetFrame(unsigned Reg, SMLoc L={})=0
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:461
MachineBasicBlock * getMBB() const
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
Definition: AsmPrinter.h:93
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:313
MCTargetOptions MCOptions
Machine level options.
void DecodeVPERMILPMask(unsigned NumElts, unsigned ScalarBits, ArrayRef< uint64_t > RawMask, SmallVectorImpl< int > &ShuffleMask)
Decode a VPERMILPD/VPERMILPS variable mask from a raw array of constants.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:115
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
PointerTy getPointer() const
static MachineOperand CreateMCSymbol(MCSymbol *Sym, unsigned char TargetFlags=0)
void setTargetFlags(unsigned F)
StringRef getPrivateGlobalPrefix() const
Definition: DataLayout.h:294
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:42
iterator begin() const
Definition: ArrayRef.h:137
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:136
MO_TLSLD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with ...
Definition: X86BaseInfo.h:136
MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate is some TLS offset from the ...
Definition: X86BaseInfo.h:222
MCContext & OutContext
This is the context for the output file that we are streaming.
Definition: AsmPrinter.h:88
static MachineModuleInfoMachO & getMachOMMI(AsmPrinter &AP)
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:137
bool EnablePrintSchedInfo
Enable print [latency:throughput] in output.
Definition: AsmPrinter.h:125
const MCSubtargetInfo & getSubtargetInfo() const
Return information about subtarget.
Definition: AsmPrinter.cpp:222
virtual void EmitWinCFISaveXMM(unsigned Register, unsigned Offset, SMLoc Loc=SMLoc())
Definition: MCStreamer.cpp:764
This provides a very simple, boring adaptor for a begin and end iterator into a range type...
unsigned getReg() const
getReg - Returns the register number.
virtual void EmitBytes(StringRef Data)
Emit the bytes in Data into the output.
Definition: MCStreamer.cpp:949
Address of indexed Jump Table for switch.
This class represents a function call, abstracting a target machine&#39;s calling convention.
bool isReg() const
Definition: MCInst.h:58
PointerIntPair< MCSymbol *, 1, bool > StubValueTy
static std::string getShuffleComment(const MachineInstr *MI, unsigned SrcOp1Idx, unsigned SrcOp2Idx, ArrayRef< int > Mask)
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:494
MachineBasicBlock reference.
MachineFunction * MF
The current machine function.
Definition: AsmPrinter.h:96
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
MachineInstrBundleIterator< const MachineInstr > const_iterator
MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...
Definition: X86BaseInfo.h:110
MO_DTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry with...
Definition: X86BaseInfo.h:179
static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, const MCSubtargetInfo &STI)
Emit the optimal amount of multi-byte nops on X86.
virtual bool emitFPOPushReg(unsigned Reg, SMLoc L={})=0
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:335
print alias Alias Set Printer
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
static MCOperand LowerSymbolOperand(const MachineOperand &MO, AsmPrinter &AP)
unsigned getSlotSize() const
virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, bool PrintSchedInfo=false)
Emit the given Instruction into the current section.
Definition: MCStreamer.cpp:887
Mask of preserved registers.
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
MCContext & getContext() const
Definition: MCStreamer.h:248
void recordSled(MCSymbol *Sled, const MachineInstr &MI, SledKind Kind, uint8_t Version=0)
CLEANUPRET - Represents a return from a cleanup block funclet.
Definition: ISDOpcodes.h:658
MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates that the reference is actually...
Definition: X86BaseInfo.h:210
bool isMachineConstantPoolEntry() const
isMachineConstantPoolEntry - Return true if the MachineConstantPoolEntry is indeed a target specific ...
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:116
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
virtual bool emitFPOStackAlloc(unsigned StackAlloc, SMLoc L={})=0
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:296
virtual void encodeInstruction(const MCInst &Inst, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
EncodeInstruction - Encode the given Inst to bytes on the output stream OS.
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:36
Name of external global symbol.
Reg
All possible values of the reg field in the ModR/M byte.
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:165
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:293
const char * getSymbolName() const
#define CASE_ALL_MOV_RM()
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:65
Context object for machine code objects.
Definition: MCContext.h:63
void recordFaultingOp(FaultKind FaultTy, const MCSymbol *HandlerLabel)
Definition: FaultMaps.cpp:31
virtual void AddComment(const Twine &T, bool EOL=true)
Add a textual comment.
Definition: MCStreamer.h:296
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:245
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:536
bool isPositionIndependent() const
Definition: AsmPrinter.cpp:199
MO_GOT - On a symbol operand this indicates that the immediate is the offset to the GOT entry for the...
Definition: X86BaseInfo.h:95
MO_GOTTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry wi...
Definition: X86BaseInfo.h:154
MO_ABS8 - On a symbol operand this indicates that the symbol is known to be an absolute symbol in ran...
Definition: X86BaseInfo.h:233
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:133
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
virtual void emitRawComment(const Twine &T, bool TabPrefix=true)
Print T and prefix it with the comment string (normally #) and optionally a tab.
Definition: MCStreamer.cpp:98
This class is a data container for one entry in a MachineConstantPool.
virtual void EmitBinaryData(StringRef Data)
Functionally identical to EmitBytes.
Definition: MCStreamer.cpp:950
const MCExpr * getExpr() const
Definition: MCInst.h:96
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:451
MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the reference is actually to the "...
Definition: X86BaseInfo.h:205
void recordStatepoint(const MachineInstr &MI)
Generate a stackmap record for a statepoint instruction.
Definition: StackMaps.cpp:395
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:161
auto count(R &&Range, const E &Element) -> typename std::iterator_traits< decltype(adl_begin(Range))>::difference_type
Wrapper function around std::count to count the number of times an element Element occurs in the give...
Definition: STLExtras.h:912
bool isX86_64ExtendedReg(unsigned RegNo)
isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or higher) register? e.g.
Definition: X86BaseInfo.h:769
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
int64_t getImm() const
Definition: MCInst.h:76
Address of a global value.
Streaming machine code generation interface.
Definition: MCStreamer.h:183
MCSymbol * createTempSymbol(bool CanBeUnnamed=true)
Create and return a new assembler temporary symbol with a unique but unspecified name.
Definition: MCContext.cpp:216
MCTargetStreamer * getTargetStreamer()
Definition: MCStreamer.h:250
bool getAsmPrinterFlag(CommentFlag Flag) const
Return whether an AsmPrinter flag is set.
Definition: MachineInstr.h:163
MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a relocation of: SYMBOL_LABEL + [...
Definition: X86BaseInfo.h:83
PointerIntPair - This class implements a pair of a pointer and small integer.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void DecodeVPPERMMask(ArrayRef< uint64_t > RawMask, SmallVectorImpl< int > &ShuffleMask)
Decode a VPPERM mask from a raw array of constants such as from BUILD_VECTOR.
MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry w...
Definition: X86BaseInfo.h:195
MO_TLVP - On a symbol operand this indicates that the immediate is some TLS offset.
Definition: X86BaseInfo.h:216
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This is an important base class in LLVM.
Definition: Constant.h:42
unsigned getFlags() const
Definition: MCInst.h:177
const GlobalValue * getGlobal() const
MO_TLSLDM - On a symbol operand this indicates that the immediate is the offset of the GOT entry with...
Definition: X86BaseInfo.h:146
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:22
void DecodeVPERMIL2PMask(unsigned NumElts, unsigned ScalarBits, unsigned M2Z, ArrayRef< uint64_t > RawMask, SmallVectorImpl< int > &ShuffleMask)
Decode a VPERMIL2PD/VPERMIL2PS variable mask from a raw array of constants.
TargetMachine & TM
Target machine description.
Definition: AsmPrinter.h:81
This class is intended to be used as a driving class for all asm writers.
Definition: AsmPrinter.h:78
void getNameWithPrefix(SmallVectorImpl< char > &Name, const GlobalValue *GV) const
Definition: AsmPrinter.cpp:422
bool hasInternalLinkage() const
Definition: GlobalValue.h:433
Address of a basic block.
bool isExpr() const
Definition: MCInst.h:61
static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst, unsigned Opcode)
Simplify things like MOV32rm to MOV32o32a.
MO_NTPOFF - On a symbol operand this indicates that the immediate is the negative thread-pointer offs...
Definition: X86BaseInfo.h:187
MI-level patchpoint operands.
Definition: StackMaps.h:77
unsigned getNumOperands() const
Definition: MCInst.h:184
int getSEHRegNum(unsigned i) const
void print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const
Print this MI to OS.
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
static const Constant * getConstantFromPool(const MachineInstr &MI, const MachineOperand &Op)
const MachineBasicBlock & front() const
virtual MCSymbol * GetCPISymbol(unsigned CPID) const
Return the symbol for the specified constant pool entry.
StubValueTy & getGVStubEntry(MCSymbol *Sym)
AddrSegmentReg - The operand # of the segment in the memory operand.
Definition: X86BaseInfo.h:39
virtual void EmitWinCFISetFrame(unsigned Register, unsigned Offset, SMLoc Loc=SMLoc())
Definition: MCStreamer.cpp:708
std::string & str()
Flushes the stream contents to the target string and returns the string&#39;s reference.
Definition: raw_ostream.h:483
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void recordPatchPoint(const MachineInstr &MI)
Generate a stackmap record for a patchpoint instruction.
Definition: StackMaps.cpp:374
MO_TLSGD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with ...
Definition: X86BaseInfo.h:126
const std::vector< MachineConstantPoolEntry > & getConstants() const
virtual void EmitWinCFIPushFrame(bool Code, SMLoc Loc=SMLoc())
Definition: MCStreamer.cpp:779
MO_TPOFF - On a symbol operand this indicates that the immediate is the thread-pointer offset for the...
Definition: X86BaseInfo.h:171
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
void setFlags(unsigned F)
Definition: MCInst.h:176
void setOpcode(unsigned Op)
Definition: MCInst.h:173
MCSymbol * GetBlockAddressSymbol(const BlockAddress *BA) const
Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block.
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
MCSymbol * getSymbol(const GlobalValue *GV) const
Definition: AsmPrinter.cpp:427
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:862
virtual void EmitWinCFIEndProlog(SMLoc Loc=SMLoc())
Definition: MCStreamer.cpp:793
virtual void EmitCodeAlignment(unsigned ByteAlignment, unsigned MaxBytesToEmit=0)
Emit nops until the byte alignment ByteAlignment is reached.
Definition: MCStreamer.cpp:962
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:182
virtual void EmitWinCFIAllocStack(unsigned Size, SMLoc Loc=SMLoc())
Definition: MCStreamer.cpp:730
iterator end() const
Definition: ArrayRef.h:138
X86 target streamer implementing x86-only assembly directives.
int64_t getImm() const
MCSymbol reference (for debug/eh info)
Target - Wrapper for Target specific information.
void recordStackMap(const MachineInstr &MI)
Generate a stackmap record for a stackmap instruction.
Definition: StackMaps.cpp:365
virtual bool emitFPOEndPrologue(SMLoc L={})=0
CATCHRET - Represents a return from a catch block funclet.
Definition: ISDOpcodes.h:654
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:142
Representation of each machine instruction.
Definition: MachineInstr.h:60
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MO_GOTOFF - On a symbol operand this indicates that the immediate is the offset to the location of th...
Definition: X86BaseInfo.h:102
static unsigned getRetOpcode(const X86Subtarget &Subtarget)
unsigned getNumFrameInfos()
Definition: MCStreamer.h:254
MCSymbol * GetJTISymbol(unsigned JTID, bool isLinkerPrivate=false) const
Return the symbol for the specified jump table entry.
MO_INDNTPOFF - On a symbol operand this indicates that the immediate is the absolute address of the G...
Definition: X86BaseInfo.h:163
virtual void EmitWinCFISaveReg(unsigned Register, unsigned Offset, SMLoc Loc=SMLoc())
Definition: MCStreamer.cpp:747
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:122
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:61
TargetOptions Options
Definition: TargetMachine.h:98
int64_t getOffset() const
Return the offset from the symbol in this operand.
const BlockAddress * getBlockAddress() const
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
Generic base class for all target subtargets.
MI-level Statepoint operands.
Definition: StackMaps.h:155
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given patchpoint should emit.
Definition: StackMaps.h:105
void EmitInstruction(const MachineInstr *MI) override
Targets should implement this to emit instructions.
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
MachineModuleInfoMachO - This is a MachineModuleInfoImpl implementation for MachO targets...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents &#39;eh_return&#39; gcc dwarf builtin...
Definition: ISDOpcodes.h:102
MO_PLT - On a symbol operand this indicates that the immediate is offset to the PLT entry of symbol n...
Definition: X86BaseInfo.h:117
void DecodePSHUFBMask(ArrayRef< uint64_t > RawMask, SmallVectorImpl< int > &ShuffleMask)
Decode a PSHUFB mask from a raw array of constants such as from BUILD_VECTOR.
union llvm::MachineConstantPoolEntry::@144 Val
The constant itself.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:467
MCSymbol * getMCSymbol() const
mop_iterator operands_begin()
Definition: MachineInstr.h:329
static const char * name
ArrayRef< MCDwarfFrameInfo > getDwarfFrameInfos() const
Definition: MCStreamer.h:255
MCSymbol * getPICBaseSymbol() const
getPICBaseSymbol - Return a function-local symbol to represent the PIC base.
static void printConstant(const Constant *COp, raw_ostream &CS)
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
virtual void EmitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
Definition: MCStreamer.cpp:321
bool useRetpoline() const
Definition: X86Subtarget.h:631
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:59
MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the immediate should get the value of th...
Definition: X86BaseInfo.h:88
void getNameWithPrefix(raw_ostream &OS, const GlobalValue *GV, bool CannotUsePrivateLabel) const
Print the appropriate prefix and the specified global variable&#39;s name.
Definition: Mangler.cpp:112
static MachineBasicBlock::const_iterator PrevCrossBBInst(MachineBasicBlock::const_iterator MBBI)
IRTranslator LLVM IR MI
const MachineOperand & getCallTarget() const
Returns the target of the underlying call.
Definition: StackMaps.h:110
void addOperand(const MCOperand &Op)
Definition: MCInst.h:186
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
Address of indexed Constant in Constant Pool.
static MCSymbol * GetSymbolFromOperand(const MachineOperand &MO, AsmPrinter &AP)
unsigned getOpcode() const
Definition: MCInst.h:174
virtual bool isVerboseAsm() const
Return true if this streamer supports verbose assembly and if it is enabled.
Definition: MCStreamer.h:273
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:298
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:35
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:123
static unsigned EmitNop(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, const MCSubtargetInfo &STI)
Emit the largest nop instruction smaller than or equal to NumBytes bytes.
const X86Subtarget & getSubtarget() const
static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode)
Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with a short fixed-register form...
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx)
Definition: MCExpr.cpp:159
virtual void EmitCFIAdjustCfaOffset(int64_t Adjustment)
Definition: MCStreamer.cpp:408
static void SimplifyMOVSX(MCInst &Inst)
If a movsx instruction has a shorter encoding for the used register simplify the instruction to use i...
AddrNumOperands - Total number of operands in a memory reference.
Definition: X86BaseInfo.h:42
uint8_t getAsmPrinterFlags() const
Return the asm printer flags bitvector.
Definition: MachineInstr.h:157
MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the reference is actually to the "__imp...
Definition: X86BaseInfo.h:200
bool isImplicit() const