52 class X86MCInstLower {
87 CurrentShadowSize += Code.
size();
88 if (CurrentShadowSize >= RequiredShadowSize)
93 void X86AsmPrinter::StackMapShadowTracker::emitShadowPadding(
95 if (InShadow && CurrentShadowSize < RequiredShadowSize) {
97 EmitNops(OutStreamer, RequiredShadowSize - CurrentShadowSize,
102 void X86AsmPrinter::EmitAndCountInstruction(
MCInst &Inst) {
104 SMShadowTracker.count(Inst, getSubtargetInfo(), CodeEmitter.get());
109 : Ctx(mf.getContext()), MF(mf),
TM(mf.getTarget()), MAI(*
TM.getMCAsmInfo()),
121 "Isn't a symbol reference");
137 Suffix =
"$non_lazy_ptr";
149 }
else if (MO.
isMBB()) {
156 Sym = Ctx.getOrCreateSymbol(Name);
167 if (!StubSym.getPointer()) {
195 const MCExpr *Expr =
nullptr;
269 assert(MAI.doesSetDirectiveSuppressReloc());
299 "Unexpected instruction!");
303 if (Reg !=
X86::AL && Reg != X86::AX && Reg !=
X86::EAX && Reg != X86::RAX)
316 unsigned NewOpcode = 0;
321 case X86::MOVSX16rr8:
322 if (Op0 == X86::AX && Op1 ==
X86::AL)
323 NewOpcode = X86::CBW;
325 case X86::MOVSX32rr16:
326 if (Op0 ==
X86::EAX && Op1 == X86::AX)
327 NewOpcode = X86::CWDE;
329 case X86::MOVSX64rr32:
330 if (Op0 == X86::RAX && Op1 ==
X86::EAX)
331 NewOpcode = X86::CDQE;
335 if (NewOpcode != 0) {
350 unsigned AddrBase = IsStore;
351 unsigned RegOp = IsStore ? 0 : 5;
352 unsigned AddrOp = AddrBase + 3;
360 "Unexpected instruction!");
364 if (Reg !=
X86::AL && Reg != X86::AX && Reg !=
X86::EAX && Reg != X86::RAX)
394 return Subtarget.
is64Bit() ? X86::RETQ : X86::RETL;
435 Opcode = X86::JMP32r;
438 Opcode = X86::JMP32m;
440 case X86::TAILJMPr64:
441 Opcode = X86::JMP64r;
443 case X86::TAILJMPm64:
444 Opcode = X86::JMP64m;
446 case X86::TAILJMPr64_REX:
447 Opcode = X86::JMP64r_REX;
449 case X86::TAILJMPm64_REX:
450 Opcode = X86::JMP64m_REX;
453 case X86::TAILJMPd64:
456 case X86::TAILJMPd_CC:
457 case X86::TAILJMPd64_CC:
469 if (
auto MaybeMCOp = LowerMachineOperand(MI, MO))
480 "Unexpected # of LEA operands");
482 "LEA has segment specified!");
487 case X86::VMOVZPQILo2PQIrr:
489 case X86::VMOVAPDYrr:
491 case X86::VMOVAPSYrr:
493 case X86::VMOVDQAYrr:
495 case X86::VMOVDQUYrr:
497 case X86::VMOVUPDYrr:
499 case X86::VMOVUPSYrr: {
505 case X86::VMOVZPQILo2PQIrr: NewOpc = X86::VMOVPQI2QIrr;
break;
506 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV;
break;
507 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV;
break;
508 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV;
break;
509 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV;
break;
510 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV;
break;
511 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV;
break;
512 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV;
break;
513 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV;
break;
514 case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV;
break;
515 case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV;
break;
516 case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV;
break;
517 case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV;
break;
524 case X86::VMOVSSrr: {
530 case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV;
break;
531 case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV;
break;
538 case X86::VPCMPBZ128rmi:
case X86::VPCMPBZ128rmik:
539 case X86::VPCMPBZ128rri:
case X86::VPCMPBZ128rrik:
540 case X86::VPCMPBZ256rmi:
case X86::VPCMPBZ256rmik:
541 case X86::VPCMPBZ256rri:
case X86::VPCMPBZ256rrik:
542 case X86::VPCMPBZrmi:
case X86::VPCMPBZrmik:
543 case X86::VPCMPBZrri:
case X86::VPCMPBZrrik:
544 case X86::VPCMPDZ128rmi:
case X86::VPCMPDZ128rmik:
545 case X86::VPCMPDZ128rmib:
case X86::VPCMPDZ128rmibk:
546 case X86::VPCMPDZ128rri:
case X86::VPCMPDZ128rrik:
547 case X86::VPCMPDZ256rmi:
case X86::VPCMPDZ256rmik:
548 case X86::VPCMPDZ256rmib:
case X86::VPCMPDZ256rmibk:
549 case X86::VPCMPDZ256rri:
case X86::VPCMPDZ256rrik:
550 case X86::VPCMPDZrmi:
case X86::VPCMPDZrmik:
551 case X86::VPCMPDZrmib:
case X86::VPCMPDZrmibk:
552 case X86::VPCMPDZrri:
case X86::VPCMPDZrrik:
553 case X86::VPCMPQZ128rmi:
case X86::VPCMPQZ128rmik:
554 case X86::VPCMPQZ128rmib:
case X86::VPCMPQZ128rmibk:
555 case X86::VPCMPQZ128rri:
case X86::VPCMPQZ128rrik:
556 case X86::VPCMPQZ256rmi:
case X86::VPCMPQZ256rmik:
557 case X86::VPCMPQZ256rmib:
case X86::VPCMPQZ256rmibk:
558 case X86::VPCMPQZ256rri:
case X86::VPCMPQZ256rrik:
559 case X86::VPCMPQZrmi:
case X86::VPCMPQZrmik:
560 case X86::VPCMPQZrmib:
case X86::VPCMPQZrmibk:
561 case X86::VPCMPQZrri:
case X86::VPCMPQZrrik:
562 case X86::VPCMPWZ128rmi:
case X86::VPCMPWZ128rmik:
563 case X86::VPCMPWZ128rri:
case X86::VPCMPWZ128rrik:
564 case X86::VPCMPWZ256rmi:
case X86::VPCMPWZ256rmik:
565 case X86::VPCMPWZ256rri:
case X86::VPCMPWZ256rrik:
566 case X86::VPCMPWZrmi:
case X86::VPCMPWZrmik:
567 case X86::VPCMPWZrri:
case X86::VPCMPWZrrik: {
572 case X86::VPCMPBZ128rmi: NewOpc = X86::VPCMPEQBZ128rm;
break;
573 case X86::VPCMPBZ128rmik: NewOpc = X86::VPCMPEQBZ128rmk;
break;
574 case X86::VPCMPBZ128rri: NewOpc = X86::VPCMPEQBZ128rr;
break;
575 case X86::VPCMPBZ128rrik: NewOpc = X86::VPCMPEQBZ128rrk;
break;
576 case X86::VPCMPBZ256rmi: NewOpc = X86::VPCMPEQBZ256rm;
break;
577 case X86::VPCMPBZ256rmik: NewOpc = X86::VPCMPEQBZ256rmk;
break;
578 case X86::VPCMPBZ256rri: NewOpc = X86::VPCMPEQBZ256rr;
break;
579 case X86::VPCMPBZ256rrik: NewOpc = X86::VPCMPEQBZ256rrk;
break;
580 case X86::VPCMPBZrmi: NewOpc = X86::VPCMPEQBZrm;
break;
581 case X86::VPCMPBZrmik: NewOpc = X86::VPCMPEQBZrmk;
break;
582 case X86::VPCMPBZrri: NewOpc = X86::VPCMPEQBZrr;
break;
583 case X86::VPCMPBZrrik: NewOpc = X86::VPCMPEQBZrrk;
break;
584 case X86::VPCMPDZ128rmi: NewOpc = X86::VPCMPEQDZ128rm;
break;
585 case X86::VPCMPDZ128rmib: NewOpc = X86::VPCMPEQDZ128rmb;
break;
586 case X86::VPCMPDZ128rmibk: NewOpc = X86::VPCMPEQDZ128rmbk;
break;
587 case X86::VPCMPDZ128rmik: NewOpc = X86::VPCMPEQDZ128rmk;
break;
588 case X86::VPCMPDZ128rri: NewOpc = X86::VPCMPEQDZ128rr;
break;
589 case X86::VPCMPDZ128rrik: NewOpc = X86::VPCMPEQDZ128rrk;
break;
590 case X86::VPCMPDZ256rmi: NewOpc = X86::VPCMPEQDZ256rm;
break;
591 case X86::VPCMPDZ256rmib: NewOpc = X86::VPCMPEQDZ256rmb;
break;
592 case X86::VPCMPDZ256rmibk: NewOpc = X86::VPCMPEQDZ256rmbk;
break;
593 case X86::VPCMPDZ256rmik: NewOpc = X86::VPCMPEQDZ256rmk;
break;
594 case X86::VPCMPDZ256rri: NewOpc = X86::VPCMPEQDZ256rr;
break;
595 case X86::VPCMPDZ256rrik: NewOpc = X86::VPCMPEQDZ256rrk;
break;
596 case X86::VPCMPDZrmi: NewOpc = X86::VPCMPEQDZrm;
break;
597 case X86::VPCMPDZrmib: NewOpc = X86::VPCMPEQDZrmb;
break;
598 case X86::VPCMPDZrmibk: NewOpc = X86::VPCMPEQDZrmbk;
break;
599 case X86::VPCMPDZrmik: NewOpc = X86::VPCMPEQDZrmk;
break;
600 case X86::VPCMPDZrri: NewOpc = X86::VPCMPEQDZrr;
break;
601 case X86::VPCMPDZrrik: NewOpc = X86::VPCMPEQDZrrk;
break;
602 case X86::VPCMPQZ128rmi: NewOpc = X86::VPCMPEQQZ128rm;
break;
603 case X86::VPCMPQZ128rmib: NewOpc = X86::VPCMPEQQZ128rmb;
break;
604 case X86::VPCMPQZ128rmibk: NewOpc = X86::VPCMPEQQZ128rmbk;
break;
605 case X86::VPCMPQZ128rmik: NewOpc = X86::VPCMPEQQZ128rmk;
break;
606 case X86::VPCMPQZ128rri: NewOpc = X86::VPCMPEQQZ128rr;
break;
607 case X86::VPCMPQZ128rrik: NewOpc = X86::VPCMPEQQZ128rrk;
break;
608 case X86::VPCMPQZ256rmi: NewOpc = X86::VPCMPEQQZ256rm;
break;
609 case X86::VPCMPQZ256rmib: NewOpc = X86::VPCMPEQQZ256rmb;
break;
610 case X86::VPCMPQZ256rmibk: NewOpc = X86::VPCMPEQQZ256rmbk;
break;
611 case X86::VPCMPQZ256rmik: NewOpc = X86::VPCMPEQQZ256rmk;
break;
612 case X86::VPCMPQZ256rri: NewOpc = X86::VPCMPEQQZ256rr;
break;
613 case X86::VPCMPQZ256rrik: NewOpc = X86::VPCMPEQQZ256rrk;
break;
614 case X86::VPCMPQZrmi: NewOpc = X86::VPCMPEQQZrm;
break;
615 case X86::VPCMPQZrmib: NewOpc = X86::VPCMPEQQZrmb;
break;
616 case X86::VPCMPQZrmibk: NewOpc = X86::VPCMPEQQZrmbk;
break;
617 case X86::VPCMPQZrmik: NewOpc = X86::VPCMPEQQZrmk;
break;
618 case X86::VPCMPQZrri: NewOpc = X86::VPCMPEQQZrr;
break;
619 case X86::VPCMPQZrrik: NewOpc = X86::VPCMPEQQZrrk;
break;
620 case X86::VPCMPWZ128rmi: NewOpc = X86::VPCMPEQWZ128rm;
break;
621 case X86::VPCMPWZ128rmik: NewOpc = X86::VPCMPEQWZ128rmk;
break;
622 case X86::VPCMPWZ128rri: NewOpc = X86::VPCMPEQWZ128rr;
break;
623 case X86::VPCMPWZ128rrik: NewOpc = X86::VPCMPEQWZ128rrk;
break;
624 case X86::VPCMPWZ256rmi: NewOpc = X86::VPCMPEQWZ256rm;
break;
625 case X86::VPCMPWZ256rmik: NewOpc = X86::VPCMPEQWZ256rmk;
break;
626 case X86::VPCMPWZ256rri: NewOpc = X86::VPCMPEQWZ256rr;
break;
627 case X86::VPCMPWZ256rrik: NewOpc = X86::VPCMPEQWZ256rrk;
break;
628 case X86::VPCMPWZrmi: NewOpc = X86::VPCMPEQWZrm;
break;
629 case X86::VPCMPWZrmik: NewOpc = X86::VPCMPEQWZrmk;
break;
630 case X86::VPCMPWZrri: NewOpc = X86::VPCMPEQWZrr;
break;
631 case X86::VPCMPWZrrik: NewOpc = X86::VPCMPEQWZrrk;
break;
643 case X86::VPCMPBZ128rmi: NewOpc = X86::VPCMPGTBZ128rm;
break;
644 case X86::VPCMPBZ128rmik: NewOpc = X86::VPCMPGTBZ128rmk;
break;
645 case X86::VPCMPBZ128rri: NewOpc = X86::VPCMPGTBZ128rr;
break;
646 case X86::VPCMPBZ128rrik: NewOpc = X86::VPCMPGTBZ128rrk;
break;
647 case X86::VPCMPBZ256rmi: NewOpc = X86::VPCMPGTBZ256rm;
break;
648 case X86::VPCMPBZ256rmik: NewOpc = X86::VPCMPGTBZ256rmk;
break;
649 case X86::VPCMPBZ256rri: NewOpc = X86::VPCMPGTBZ256rr;
break;
650 case X86::VPCMPBZ256rrik: NewOpc = X86::VPCMPGTBZ256rrk;
break;
651 case X86::VPCMPBZrmi: NewOpc = X86::VPCMPGTBZrm;
break;
652 case X86::VPCMPBZrmik: NewOpc = X86::VPCMPGTBZrmk;
break;
653 case X86::VPCMPBZrri: NewOpc = X86::VPCMPGTBZrr;
break;
654 case X86::VPCMPBZrrik: NewOpc = X86::VPCMPGTBZrrk;
break;
655 case X86::VPCMPDZ128rmi: NewOpc = X86::VPCMPGTDZ128rm;
break;
656 case X86::VPCMPDZ128rmib: NewOpc = X86::VPCMPGTDZ128rmb;
break;
657 case X86::VPCMPDZ128rmibk: NewOpc = X86::VPCMPGTDZ128rmbk;
break;
658 case X86::VPCMPDZ128rmik: NewOpc = X86::VPCMPGTDZ128rmk;
break;
659 case X86::VPCMPDZ128rri: NewOpc = X86::VPCMPGTDZ128rr;
break;
660 case X86::VPCMPDZ128rrik: NewOpc = X86::VPCMPGTDZ128rrk;
break;
661 case X86::VPCMPDZ256rmi: NewOpc = X86::VPCMPGTDZ256rm;
break;
662 case X86::VPCMPDZ256rmib: NewOpc = X86::VPCMPGTDZ256rmb;
break;
663 case X86::VPCMPDZ256rmibk: NewOpc = X86::VPCMPGTDZ256rmbk;
break;
664 case X86::VPCMPDZ256rmik: NewOpc = X86::VPCMPGTDZ256rmk;
break;
665 case X86::VPCMPDZ256rri: NewOpc = X86::VPCMPGTDZ256rr;
break;
666 case X86::VPCMPDZ256rrik: NewOpc = X86::VPCMPGTDZ256rrk;
break;
667 case X86::VPCMPDZrmi: NewOpc = X86::VPCMPGTDZrm;
break;
668 case X86::VPCMPDZrmib: NewOpc = X86::VPCMPGTDZrmb;
break;
669 case X86::VPCMPDZrmibk: NewOpc = X86::VPCMPGTDZrmbk;
break;
670 case X86::VPCMPDZrmik: NewOpc = X86::VPCMPGTDZrmk;
break;
671 case X86::VPCMPDZrri: NewOpc = X86::VPCMPGTDZrr;
break;
672 case X86::VPCMPDZrrik: NewOpc = X86::VPCMPGTDZrrk;
break;
673 case X86::VPCMPQZ128rmi: NewOpc = X86::VPCMPGTQZ128rm;
break;
674 case X86::VPCMPQZ128rmib: NewOpc = X86::VPCMPGTQZ128rmb;
break;
675 case X86::VPCMPQZ128rmibk: NewOpc = X86::VPCMPGTQZ128rmbk;
break;
676 case X86::VPCMPQZ128rmik: NewOpc = X86::VPCMPGTQZ128rmk;
break;
677 case X86::VPCMPQZ128rri: NewOpc = X86::VPCMPGTQZ128rr;
break;
678 case X86::VPCMPQZ128rrik: NewOpc = X86::VPCMPGTQZ128rrk;
break;
679 case X86::VPCMPQZ256rmi: NewOpc = X86::VPCMPGTQZ256rm;
break;
680 case X86::VPCMPQZ256rmib: NewOpc = X86::VPCMPGTQZ256rmb;
break;
681 case X86::VPCMPQZ256rmibk: NewOpc = X86::VPCMPGTQZ256rmbk;
break;
682 case X86::VPCMPQZ256rmik: NewOpc = X86::VPCMPGTQZ256rmk;
break;
683 case X86::VPCMPQZ256rri: NewOpc = X86::VPCMPGTQZ256rr;
break;
684 case X86::VPCMPQZ256rrik: NewOpc = X86::VPCMPGTQZ256rrk;
break;
685 case X86::VPCMPQZrmi: NewOpc = X86::VPCMPGTQZrm;
break;
686 case X86::VPCMPQZrmib: NewOpc = X86::VPCMPGTQZrmb;
break;
687 case X86::VPCMPQZrmibk: NewOpc = X86::VPCMPGTQZrmbk;
break;
688 case X86::VPCMPQZrmik: NewOpc = X86::VPCMPGTQZrmk;
break;
689 case X86::VPCMPQZrri: NewOpc = X86::VPCMPGTQZrr;
break;
690 case X86::VPCMPQZrrik: NewOpc = X86::VPCMPGTQZrrk;
break;
691 case X86::VPCMPWZ128rmi: NewOpc = X86::VPCMPGTWZ128rm;
break;
692 case X86::VPCMPWZ128rmik: NewOpc = X86::VPCMPGTWZ128rmk;
break;
693 case X86::VPCMPWZ128rri: NewOpc = X86::VPCMPGTWZ128rr;
break;
694 case X86::VPCMPWZ128rrik: NewOpc = X86::VPCMPGTWZ128rrk;
break;
695 case X86::VPCMPWZ256rmi: NewOpc = X86::VPCMPGTWZ256rm;
break;
696 case X86::VPCMPWZ256rmik: NewOpc = X86::VPCMPGTWZ256rmk;
break;
697 case X86::VPCMPWZ256rri: NewOpc = X86::VPCMPGTWZ256rr;
break;
698 case X86::VPCMPWZ256rrik: NewOpc = X86::VPCMPGTWZ256rrk;
break;
699 case X86::VPCMPWZrmi: NewOpc = X86::VPCMPGTWZrm;
break;
700 case X86::VPCMPWZrmik: NewOpc = X86::VPCMPGTWZrmk;
break;
701 case X86::VPCMPWZrri: NewOpc = X86::VPCMPGTWZrr;
break;
702 case X86::VPCMPWZrrik: NewOpc = X86::VPCMPGTWZrrk;
break;
718 case X86::CALL64pcrel32:
723 case X86::EH_RETURN64: {
749 case X86::TAILJMPr64:
750 case X86::TAILJMPr64_REX:
752 case X86::TAILJMPd64:
757 case X86::TAILJMPd_CC:
758 case X86::TAILJMPd64_CC:
764 case X86::TAILJMPm64:
765 case X86::TAILJMPm64_REX:
767 "Unexpected number of operands!");
780 case X86::DEC16r: Opcode = X86::DEC16r_alt;
break;
781 case X86::DEC32r: Opcode = X86::DEC32r_alt;
break;
782 case X86::INC16r: Opcode = X86::INC16r_alt;
break;
783 case X86::INC32r: Opcode = X86::INC32r_alt;
break;
796 case X86::MOV8mr_NOREX:
798 case X86::MOV8rm_NOREX:
807 case X86::MOV8mr_NOREX:
808 case X86::MOV8mr: NewOpc = X86::MOV8o32a;
break;
809 case X86::MOV8rm_NOREX:
810 case X86::MOV8rm: NewOpc = X86::MOV8ao32;
break;
811 case X86::MOV16mr: NewOpc = X86::MOV16o32a;
break;
812 case X86::MOV16rm: NewOpc = X86::MOV16ao32;
break;
813 case X86::MOV32mr: NewOpc = X86::MOV32o32a;
break;
814 case X86::MOV32rm: NewOpc = X86::MOV32ao32;
break;
820 case X86::ADC8ri:
case X86::ADC16ri:
case X86::ADC32ri:
case X86::ADC64ri32:
821 case X86::ADD8ri:
case X86::ADD16ri:
case X86::ADD32ri:
case X86::ADD64ri32:
822 case X86::AND8ri:
case X86::AND16ri:
case X86::AND32ri:
case X86::AND64ri32:
823 case X86::CMP8ri:
case X86::CMP16ri:
case X86::CMP32ri:
case X86::CMP64ri32:
824 case X86::OR8ri:
case X86::OR16ri:
case X86::OR32ri:
case X86::OR64ri32:
825 case X86::SBB8ri:
case X86::SBB16ri:
case X86::SBB32ri:
case X86::SBB64ri32:
826 case X86::SUB8ri:
case X86::SUB16ri:
case X86::SUB32ri:
case X86::SUB64ri32:
827 case X86::TEST8ri:
case X86::TEST16ri:
case X86::TEST32ri:
case X86::TEST64ri32:
828 case X86::XOR8ri:
case X86::XOR16ri:
case X86::XOR32ri:
case X86::XOR64ri32: {
832 case X86::ADC8ri: NewOpc = X86::ADC8i8;
break;
833 case X86::ADC16ri: NewOpc = X86::ADC16i16;
break;
834 case X86::ADC32ri: NewOpc = X86::ADC32i32;
break;
835 case X86::ADC64ri32: NewOpc = X86::ADC64i32;
break;
836 case X86::ADD8ri: NewOpc = X86::ADD8i8;
break;
837 case X86::ADD16ri: NewOpc = X86::ADD16i16;
break;
838 case X86::ADD32ri: NewOpc = X86::ADD32i32;
break;
839 case X86::ADD64ri32: NewOpc = X86::ADD64i32;
break;
840 case X86::AND8ri: NewOpc = X86::AND8i8;
break;
841 case X86::AND16ri: NewOpc = X86::AND16i16;
break;
842 case X86::AND32ri: NewOpc = X86::AND32i32;
break;
843 case X86::AND64ri32: NewOpc = X86::AND64i32;
break;
844 case X86::CMP8ri: NewOpc = X86::CMP8i8;
break;
845 case X86::CMP16ri: NewOpc = X86::CMP16i16;
break;
846 case X86::CMP32ri: NewOpc = X86::CMP32i32;
break;
847 case X86::CMP64ri32: NewOpc = X86::CMP64i32;
break;
848 case X86::OR8ri: NewOpc = X86::OR8i8;
break;
849 case X86::OR16ri: NewOpc = X86::OR16i16;
break;
850 case X86::OR32ri: NewOpc = X86::OR32i32;
break;
851 case X86::OR64ri32: NewOpc = X86::OR64i32;
break;
852 case X86::SBB8ri: NewOpc = X86::SBB8i8;
break;
853 case X86::SBB16ri: NewOpc = X86::SBB16i16;
break;
854 case X86::SBB32ri: NewOpc = X86::SBB32i32;
break;
855 case X86::SBB64ri32: NewOpc = X86::SBB64i32;
break;
856 case X86::SUB8ri: NewOpc = X86::SUB8i8;
break;
857 case X86::SUB16ri: NewOpc = X86::SUB16i16;
break;
858 case X86::SUB32ri: NewOpc = X86::SUB32i32;
break;
859 case X86::SUB64ri32: NewOpc = X86::SUB64i32;
break;
860 case X86::TEST8ri: NewOpc = X86::TEST8i8;
break;
861 case X86::TEST16ri: NewOpc = X86::TEST16i16;
break;
862 case X86::TEST32ri: NewOpc = X86::TEST32i32;
break;
863 case X86::TEST64ri32: NewOpc = X86::TEST64i32;
break;
864 case X86::XOR8ri: NewOpc = X86::XOR8i8;
break;
865 case X86::XOR16ri: NewOpc = X86::XOR16i16;
break;
866 case X86::XOR32ri: NewOpc = X86::XOR32i32;
break;
867 case X86::XOR64ri32: NewOpc = X86::XOR64i32;
break;
874 case X86::MOVSX16rr8:
875 case X86::MOVSX32rr16:
876 case X86::MOVSX64rr32:
882 void X86AsmPrinter::LowerTlsAddr(X86MCInstLower &MCInstLowering,
884 bool Is64Bits = MI.
getOpcode() == X86::TLS_addr64 ||
890 case X86::TLS_addr32:
891 case X86::TLS_addr64:
894 case X86::TLS_base_addr32:
897 case X86::TLS_base_addr64:
905 MCInstLowering.GetSymbolFromOperand(MI.
getOperand(3)), SRVK, Ctx);
943 EmitAndCountInstruction(
978 EmitAndCountInstruction(
992 assert(Is64Bit &&
"EmitNops only supports X86-64");
995 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;
996 IndexReg = Displacement = SegmentReg = 0;
1009 Opc = X86::XCHG16ar;
1024 IndexReg = X86::RAX;
1030 IndexReg = X86::RAX;
1041 IndexReg = X86::RAX;
1047 IndexReg = X86::RAX;
1053 IndexReg = X86::RAX;
1054 SegmentReg = X86::CS;
1058 unsigned NumPrefixes = std::min(NumBytes - NopSize, 5U);
1059 NopSize += NumPrefixes;
1060 for (
unsigned i = 0; i != NumPrefixes; ++i)
1077 .addImm(Displacement)
1078 .addReg(SegmentReg),
1082 assert(NopSize <= NumBytes &&
"We overemitted?");
1089 unsigned NopsToEmit = NumBytes;
1092 NumBytes -=
EmitNop(OS, NumBytes, Is64Bit, STI);
1093 assert(NopsToEmit >= NumBytes &&
"Emitted more than I asked for!");
1097 void X86AsmPrinter::LowerSTATEPOINT(
const MachineInstr &MI,
1098 X86MCInstLower &MCIL) {
1099 assert(Subtarget->
is64Bit() &&
"Statepoint currently only supports X86-64");
1102 if (
unsigned PatchBytes = SOpers.getNumPatchBytes()) {
1109 unsigned CallOpcode;
1110 switch (CallTarget.
getType()) {
1113 CallTargetMCOp = MCIL.LowerSymbolOperand(
1114 CallTarget, MCIL.GetSymbolFromOperand(CallTarget));
1115 CallOpcode = X86::CALL64pcrel32;
1123 CallOpcode = X86::CALL64pcrel32;
1133 "yet implemented.");
1135 CallOpcode = X86::CALL64r;
1154 void X86AsmPrinter::LowerFAULTING_OP(
const MachineInstr &FaultingMI,
1155 X86MCInstLower &MCIL) {
1164 unsigned OperandsBeginIdx = 4;
1172 if (DefRegister != X86::NoRegister)
1178 if (
auto MaybeOperand = MCIL.LowerMachineOperand(&FaultingMI, *
I))
1185 void X86AsmPrinter::LowerFENTRY_CALL(
const MachineInstr &MI,
1186 X86MCInstLower &MCIL) {
1187 bool Is64Bits = Subtarget->
is64Bit();
1193 EmitAndCountInstruction(
1194 MCInstBuilder(Is64Bits ? X86::CALL64pcrel32 : X86::CALLpcrel32)
1198 void X86AsmPrinter::LowerPATCHABLE_OP(
const MachineInstr &MI,
1199 X86MCInstLower &MCIL) {
1208 if (
auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO))
1216 if (Code.
size() < MinSize) {
1217 if (MinSize == 2 && Opcode == X86::PUSH64r) {
1225 unsigned NopSize =
EmitNop(*OutStreamer, MinSize, Subtarget->
is64Bit(),
1227 assert(NopSize == MinSize &&
"Could not implement MinSize!");
1237 void X86AsmPrinter::LowerSTACKMAP(
const MachineInstr &MI) {
1241 SMShadowTracker.reset(NumShadowBytes);
1246 void X86AsmPrinter::LowerPATCHPOINT(
const MachineInstr &MI,
1247 X86MCInstLower &MCIL) {
1248 assert(Subtarget->
is64Bit() &&
"Patchpoint currently only supports X86-64");
1256 unsigned EncodedBytes = 0;
1273 CalleeMCOp = MCIL.LowerSymbolOperand(CalleeMO,
1274 MCIL.GetSymbolFromOperand(CalleeMO));
1286 EmitAndCountInstruction(
1291 "Lowering patchpoint with retpoline not yet implemented.");
1292 EmitAndCountInstruction(
MCInstBuilder(X86::CALL64r).addReg(ScratchReg));
1297 assert(NumBytes >= EncodedBytes &&
1298 "Patchpoint can't request size less than the length of a call.");
1304 void X86AsmPrinter::LowerPATCHABLE_EVENT_CALL(
const MachineInstr &MI,
1305 X86MCInstLower &MCIL) {
1306 assert(Subtarget->
is64Bit() &&
"XRay custom events only supports X86-64");
1329 OutStreamer->
AddComment(
"# XRay Custom Event Log");
1340 unsigned DestRegs[] = {X86::RDI, X86::RSI};
1341 bool UsedMask[] = {
false,
false};
1343 unsigned SrcRegs[] = {0, 0};
1351 if (
auto Op = MCIL.LowerMachineOperand(&MI, MI.
getOperand(
I))) {
1352 assert(
Op->isReg() &&
"Only support arguments in registers");
1353 SrcRegs[
I] =
Op->getReg();
1354 if (SrcRegs[
I] != DestRegs[
I]) {
1356 EmitAndCountInstruction(
1365 if (SrcRegs[
I] != DestRegs[
I])
1366 EmitAndCountInstruction(
1367 MCInstBuilder(X86::MOV64rr).addReg(DestRegs[I]).addReg(SrcRegs[I]));
1378 .
addOperand(MCIL.LowerSymbolOperand(TOp, TSym)));
1381 for (
unsigned I =
sizeof UsedMask; I-- > 0;)
1383 EmitAndCountInstruction(
MCInstBuilder(X86::POP64r).addReg(DestRegs[I]));
1387 OutStreamer->
AddComment(
"xray custom event end.");
1395 void X86AsmPrinter::LowerPATCHABLE_TYPED_EVENT_CALL(
const MachineInstr &MI,
1396 X86MCInstLower &MCIL) {
1397 assert(Subtarget->
is64Bit() &&
"XRay typed events only supports X86-64");
1420 OutStreamer->
AddComment(
"# XRay Typed Event Log");
1432 unsigned DestRegs[] = {X86::RDI, X86::RSI, X86::RDX};
1433 bool UsedMask[] = {
false,
false,
false};
1436 unsigned SrcRegs[] = {0, 0, 0};
1443 if (
auto Op = MCIL.LowerMachineOperand(&MI, MI.
getOperand(
I))) {
1445 assert(
Op->isReg() &&
"Only supports arguments in registers");
1446 SrcRegs[
I] =
Op->getReg();
1447 if (SrcRegs[
I] != DestRegs[
I]) {
1449 EmitAndCountInstruction(
1464 EmitAndCountInstruction(
1465 MCInstBuilder(X86::MOV64rr).addReg(DestRegs[I]).addReg(SrcRegs[I]));
1476 .
addOperand(MCIL.LowerSymbolOperand(TOp, TSym)));
1479 for (
unsigned I =
sizeof UsedMask; I-- > 0;)
1481 EmitAndCountInstruction(
MCInstBuilder(X86::POP64r).addReg(DestRegs[I]));
1485 OutStreamer->
AddComment(
"xray typed event end.");
1491 void X86AsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(
const MachineInstr &MI,
1492 X86MCInstLower &MCIL) {
1518 void X86AsmPrinter::LowerPATCHABLE_RET(
const MachineInstr &MI,
1519 X86MCInstLower &MCIL) {
1541 if (
auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO))
1548 void X86AsmPrinter::LowerPATCHABLE_TAIL_CALL(
const MachineInstr &MI,
1549 X86MCInstLower &MCIL) {
1578 if (
auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO))
1588 while (MBBI == MBB->
begin()) {
1614 "Expected a constant of the same type!");
1620 std::string Comment;
1627 auto GetRegisterName = [](
unsigned RegNum) ->
StringRef {
1637 SrcOp1.
isReg() ? GetRegisterName(SrcOp1.
getReg()) :
"mem";
1639 SrcOp2.
isReg() ? GetRegisterName(SrcOp2.
getReg()) :
"mem";
1643 if (Src1Name == Src2Name)
1644 for (
int i = 0,
e = ShuffleMask.size(); i !=
e; ++i)
1645 if (ShuffleMask[i] >=
e)
1646 ShuffleMask[i] -=
e;
1654 if (SrcOp1Idx > 1) {
1655 assert((SrcOp1Idx == 2 || SrcOp1Idx == 3) &&
"Unexpected writemask");
1658 if (WriteMaskOp.
isReg()) {
1659 CS <<
" {%" << GetRegisterName(WriteMaskOp.
getReg()) <<
"}";
1661 if (SrcOp1Idx == 2) {
1669 for (
int i = 0,
e = ShuffleMask.size(); i !=
e; ++i) {
1679 bool isSrc1 = ShuffleMask[i] < (int)
e;
1680 CS << (isSrc1 ? Src1Name : Src2Name) <<
'[';
1682 bool IsFirst =
true;
1684 (ShuffleMask[i] < (
int)
e) == isSrc1) {
1692 CS << ShuffleMask[i] % (int)
e;
1726 if (isa<UndefValue>(COp)) {
1728 }
else if (
auto *CI = dyn_cast<ConstantInt>(COp)) {
1730 }
else if (
auto *CF = dyn_cast<ConstantFP>(COp)) {
1737 void X86AsmPrinter::EmitSEHInstruction(
const MachineInstr *MI) {
1746 case X86::SEH_PushReg:
1749 case X86::SEH_StackAlloc:
1752 case X86::SEH_StackAlign:
1755 case X86::SEH_SetFrame:
1757 ".cv_fpo_setframe takes no offset");
1760 case X86::SEH_EndPrologue:
1763 case X86::SEH_SaveReg:
1764 case X86::SEH_SaveXMM:
1765 case X86::SEH_PushFrame:
1776 case X86::SEH_PushReg:
1780 case X86::SEH_SaveReg:
1785 case X86::SEH_SaveXMM:
1790 case X86::SEH_StackAlloc:
1794 case X86::SEH_SetFrame:
1799 case X86::SEH_PushFrame:
1803 case X86::SEH_EndPrologue:
1813 if (Info.
RegClass == X86::VR128RegClassID ||
1814 Info.
RegClass == X86::VR128XRegClassID)
1816 if (Info.
RegClass == X86::VR256RegClassID ||
1817 Info.
RegClass == X86::VR256XRegClassID)
1819 if (Info.
RegClass == X86::VR512RegClassID)
1825 X86MCInstLower MCInstLowering(*
MF, *
this);
1833 OutStreamer->
AddComment(
"EVEX TO VEX Compression ",
false);
1837 case TargetOpcode::DBG_VALUE:
1841 case X86::Int_MemBarrier:
1846 case X86::EH_RETURN64: {
1868 case X86::TAILJMPd_CC:
1869 case X86::TAILJMPr64:
1870 case X86::TAILJMPm64:
1871 case X86::TAILJMPd64:
1872 case X86::TAILJMPd64_CC:
1873 case X86::TAILJMPr64_REX:
1874 case X86::TAILJMPm64_REX:
1879 case X86::TLS_addr32:
1880 case X86::TLS_addr64:
1881 case X86::TLS_base_addr32:
1882 case X86::TLS_base_addr64:
1883 return LowerTlsAddr(MCInstLowering, *MI);
1892 case X86::MASKPAIR16LOAD: {
1894 assert(Disp >= 0 && Disp <= INT32_MAX - 2 &&
"Unexpected displacement");
1896 Register Reg0 = RI->getSubReg(Reg, X86::sub_mask_0);
1897 Register Reg1 = RI->getSubReg(Reg, X86::sub_mask_1);
1903 auto Op = MCInstLowering.LowerMachineOperand(MI, MI->
getOperand(1 + i));
1906 EmitAndCountInstruction(MIB);
1915 auto Op = MCInstLowering.LowerMachineOperand(MI, MI->
getOperand(1 + i));
1919 EmitAndCountInstruction(MIB);
1923 case X86::MASKPAIR16STORE: {
1925 assert(Disp >= 0 && Disp <= INT32_MAX - 2 &&
"Unexpected displacement");
1927 Register Reg0 = RI->getSubReg(Reg, X86::sub_mask_0);
1928 Register Reg1 = RI->getSubReg(Reg, X86::sub_mask_1);
1935 EmitAndCountInstruction(MIB);
1943 auto Op = MCInstLowering.LowerMachineOperand(MI, MI->
getOperand(0 + i));
1948 EmitAndCountInstruction(MIB);
1952 case X86::MOVPC32r: {
1963 EmitAndCountInstruction(
1969 bool hasFP = FrameLowering->
hasFP(*
MF);
1977 if (HasActiveDwarfFrame && !hasFP) {
1985 EmitAndCountInstruction(
1988 if (HasActiveDwarfFrame && !hasFP) {
1994 case X86::ADD32ri: {
2026 case TargetOpcode::STATEPOINT:
2027 return LowerSTATEPOINT(*MI, MCInstLowering);
2029 case TargetOpcode::FAULTING_OP:
2030 return LowerFAULTING_OP(*MI, MCInstLowering);
2032 case TargetOpcode::FENTRY_CALL:
2033 return LowerFENTRY_CALL(*MI, MCInstLowering);
2035 case TargetOpcode::PATCHABLE_OP:
2036 return LowerPATCHABLE_OP(*MI, MCInstLowering);
2038 case TargetOpcode::STACKMAP:
2039 return LowerSTACKMAP(*MI);
2041 case TargetOpcode::PATCHPOINT:
2042 return LowerPATCHPOINT(*MI, MCInstLowering);
2044 case TargetOpcode::PATCHABLE_FUNCTION_ENTER:
2045 return LowerPATCHABLE_FUNCTION_ENTER(*MI, MCInstLowering);
2047 case TargetOpcode::PATCHABLE_RET:
2048 return LowerPATCHABLE_RET(*MI, MCInstLowering);
2050 case TargetOpcode::PATCHABLE_TAIL_CALL:
2051 return LowerPATCHABLE_TAIL_CALL(*MI, MCInstLowering);
2053 case TargetOpcode::PATCHABLE_EVENT_CALL:
2054 return LowerPATCHABLE_EVENT_CALL(*MI, MCInstLowering);
2056 case TargetOpcode::PATCHABLE_TYPED_EVENT_CALL:
2057 return LowerPATCHABLE_TYPED_EVENT_CALL(*MI, MCInstLowering);
2059 case X86::MORESTACK_RET:
2063 case X86::MORESTACK_RET_RESTORE_R10:
2066 EmitAndCountInstruction(
2067 MCInstBuilder(X86::MOV64rr).addReg(X86::R10).addReg(X86::RAX));
2070 case X86::SEH_PushReg:
2071 case X86::SEH_SaveReg:
2072 case X86::SEH_SaveXMM:
2073 case X86::SEH_StackAlloc:
2074 case X86::SEH_StackAlign:
2075 case X86::SEH_SetFrame:
2076 case X86::SEH_PushFrame:
2077 case X86::SEH_EndPrologue:
2078 EmitSEHInstruction(MI);
2081 case X86::SEH_Epilogue: {
2090 if (!MBBI->isPseudo()) {
2103 case X86::VPSHUFBrm:
2104 case X86::VPSHUFBYrm:
2105 case X86::VPSHUFBZ128rm:
2106 case X86::VPSHUFBZ128rmk:
2107 case X86::VPSHUFBZ128rmkz:
2108 case X86::VPSHUFBZ256rm:
2109 case X86::VPSHUFBZ256rmk:
2110 case X86::VPSHUFBZ256rmkz:
2111 case X86::VPSHUFBZrm:
2112 case X86::VPSHUFBZrmk:
2113 case X86::VPSHUFBZrmkz: {
2116 unsigned SrcIdx, MaskIdx;
2120 case X86::VPSHUFBrm:
2121 case X86::VPSHUFBYrm:
2122 case X86::VPSHUFBZ128rm:
2123 case X86::VPSHUFBZ256rm:
2124 case X86::VPSHUFBZrm:
2125 SrcIdx = 1; MaskIdx = 5;
break;
2126 case X86::VPSHUFBZ128rmkz:
2127 case X86::VPSHUFBZ256rmkz:
2128 case X86::VPSHUFBZrmkz:
2129 SrcIdx = 2; MaskIdx = 6;
break;
2130 case X86::VPSHUFBZ128rmk:
2131 case X86::VPSHUFBZ256rmk:
2132 case X86::VPSHUFBZrmk:
2133 SrcIdx = 3; MaskIdx = 7;
break;
2137 "We should always have at least 6 operands!");
2150 case X86::VPERMILPSrm:
2151 case X86::VPERMILPSYrm:
2152 case X86::VPERMILPSZ128rm:
2153 case X86::VPERMILPSZ128rmk:
2154 case X86::VPERMILPSZ128rmkz:
2155 case X86::VPERMILPSZ256rm:
2156 case X86::VPERMILPSZ256rmk:
2157 case X86::VPERMILPSZ256rmkz:
2158 case X86::VPERMILPSZrm:
2159 case X86::VPERMILPSZrmk:
2160 case X86::VPERMILPSZrmkz:
2161 case X86::VPERMILPDrm:
2162 case X86::VPERMILPDYrm:
2163 case X86::VPERMILPDZ128rm:
2164 case X86::VPERMILPDZ128rmk:
2165 case X86::VPERMILPDZ128rmkz:
2166 case X86::VPERMILPDZ256rm:
2167 case X86::VPERMILPDZ256rmk:
2168 case X86::VPERMILPDZ256rmkz:
2169 case X86::VPERMILPDZrm:
2170 case X86::VPERMILPDZrmk:
2171 case X86::VPERMILPDZrmkz: {
2174 unsigned SrcIdx, MaskIdx;
2178 case X86::VPERMILPSrm:
2179 case X86::VPERMILPSYrm:
2180 case X86::VPERMILPSZ128rm:
2181 case X86::VPERMILPSZ256rm:
2182 case X86::VPERMILPSZrm:
2183 SrcIdx = 1; MaskIdx = 5; ElSize = 32;
break;
2184 case X86::VPERMILPSZ128rmkz:
2185 case X86::VPERMILPSZ256rmkz:
2186 case X86::VPERMILPSZrmkz:
2187 SrcIdx = 2; MaskIdx = 6; ElSize = 32;
break;
2188 case X86::VPERMILPSZ128rmk:
2189 case X86::VPERMILPSZ256rmk:
2190 case X86::VPERMILPSZrmk:
2191 SrcIdx = 3; MaskIdx = 7; ElSize = 32;
break;
2192 case X86::VPERMILPDrm:
2193 case X86::VPERMILPDYrm:
2194 case X86::VPERMILPDZ128rm:
2195 case X86::VPERMILPDZ256rm:
2196 case X86::VPERMILPDZrm:
2197 SrcIdx = 1; MaskIdx = 5; ElSize = 64;
break;
2198 case X86::VPERMILPDZ128rmkz:
2199 case X86::VPERMILPDZ256rmkz:
2200 case X86::VPERMILPDZrmkz:
2201 SrcIdx = 2; MaskIdx = 6; ElSize = 64;
break;
2202 case X86::VPERMILPDZ128rmk:
2203 case X86::VPERMILPDZ256rmk:
2204 case X86::VPERMILPDZrmk:
2205 SrcIdx = 3; MaskIdx = 7; ElSize = 64;
break;
2209 "We should always have at least 6 operands!");
2222 case X86::VPERMIL2PDrm:
2223 case X86::VPERMIL2PSrm:
2224 case X86::VPERMIL2PDYrm:
2225 case X86::VPERMIL2PSYrm: {
2229 "We should always have at least 8 operands!");
2232 if (!CtrlOp.isImm())
2238 case X86::VPERMIL2PSrm:
case X86::VPERMIL2PSYrm: ElSize = 32;
break;
2239 case X86::VPERMIL2PDrm:
case X86::VPERMIL2PDYrm: ElSize = 64;
break;
2253 case X86::VPPERMrrm: {
2257 "We should always have at least 7 operands!");
2270 case X86::MMX_MOVQ64rm: {
2276 std::string Comment;
2280 if (
auto *CF = dyn_cast<ConstantFP>(
C)) {
2281 CS <<
"0x" << CF->getValueAPF().bitcastToAPInt().toString(16,
false);
2288 #define MOV_CASE(Prefix, Suffix) \ 2289 case X86::Prefix##MOVAPD##Suffix##rm: \ 2290 case X86::Prefix##MOVAPS##Suffix##rm: \ 2291 case X86::Prefix##MOVUPD##Suffix##rm: \ 2292 case X86::Prefix##MOVUPS##Suffix##rm: \ 2293 case X86::Prefix##MOVDQA##Suffix##rm: \ 2294 case X86::Prefix##MOVDQU##Suffix##rm: 2296 #define MOV_AVX512_CASE(Suffix) \ 2297 case X86::VMOVDQA64##Suffix##rm: \ 2298 case X86::VMOVDQA32##Suffix##rm: \ 2299 case X86::VMOVDQU64##Suffix##rm: \ 2300 case X86::VMOVDQU32##Suffix##rm: \ 2301 case X86::VMOVDQU16##Suffix##rm: \ 2302 case X86::VMOVDQU8##Suffix##rm: \ 2303 case X86::VMOVAPS##Suffix##rm: \ 2304 case X86::VMOVAPD##Suffix##rm: \ 2305 case X86::VMOVUPS##Suffix##rm: \ 2306 case X86::VMOVUPD##Suffix##rm: 2308 #define CASE_ALL_MOV_RM() \ 2312 MOV_AVX512_CASE(Z) \ 2313 MOV_AVX512_CASE(Z256) \ 2314 MOV_AVX512_CASE(Z128) 2319 case X86::VBROADCASTF128:
2320 case X86::VBROADCASTI128:
2321 case X86::VBROADCASTF32X4Z256rm:
2322 case X86::VBROADCASTF32X4rm:
2323 case X86::VBROADCASTF32X8rm:
2324 case X86::VBROADCASTF64X2Z128rm:
2325 case X86::VBROADCASTF64X2rm:
2326 case X86::VBROADCASTF64X4rm:
2327 case X86::VBROADCASTI32X4Z256rm:
2328 case X86::VBROADCASTI32X4rm:
2329 case X86::VBROADCASTI32X8rm:
2330 case X86::VBROADCASTI64X2Z128rm:
2331 case X86::VBROADCASTI64X2rm:
2332 case X86::VBROADCASTI64X4rm:
2341 case X86::VBROADCASTF128: NumLanes = 2;
break;
2342 case X86::VBROADCASTI128: NumLanes = 2;
break;
2343 case X86::VBROADCASTF32X4Z256rm: NumLanes = 2;
break;
2344 case X86::VBROADCASTF32X4rm: NumLanes = 4;
break;
2345 case X86::VBROADCASTF32X8rm: NumLanes = 2;
break;
2346 case X86::VBROADCASTF64X2Z128rm: NumLanes = 2;
break;
2347 case X86::VBROADCASTF64X2rm: NumLanes = 4;
break;
2348 case X86::VBROADCASTF64X4rm: NumLanes = 2;
break;
2349 case X86::VBROADCASTI32X4Z256rm: NumLanes = 2;
break;
2350 case X86::VBROADCASTI32X4rm: NumLanes = 4;
break;
2351 case X86::VBROADCASTI32X8rm: NumLanes = 2;
break;
2352 case X86::VBROADCASTI64X2Z128rm: NumLanes = 2;
break;
2353 case X86::VBROADCASTI64X2rm: NumLanes = 4;
break;
2354 case X86::VBROADCASTI64X4rm: NumLanes = 2;
break;
2357 std::string Comment;
2361 if (
auto *CDS = dyn_cast<ConstantDataSequential>(
C)) {
2363 for (
int l = 0; l != NumLanes; ++l) {
2364 for (
int i = 0, NumElements = CDS->getNumElements(); i < NumElements;
2366 if (i != 0 || l != 0)
2368 if (CDS->getElementType()->isIntegerTy())
2370 else if (CDS->getElementType()->isHalfTy() ||
2371 CDS->getElementType()->isFloatTy() ||
2372 CDS->getElementType()->isDoubleTy())
2380 }
else if (
auto *CV = dyn_cast<ConstantVector>(
C)) {
2382 for (
int l = 0; l != NumLanes; ++l) {
2383 for (
int i = 0, NumOperands = CV->getNumOperands(); i < NumOperands;
2385 if (i != 0 || l != 0)
2395 case X86::MOVDDUPrm:
2396 case X86::VMOVDDUPrm:
2397 case X86::VMOVDDUPZ128rm:
2398 case X86::VBROADCASTSSrm:
2399 case X86::VBROADCASTSSYrm:
2400 case X86::VBROADCASTSSZ128m:
2401 case X86::VBROADCASTSSZ256m:
2402 case X86::VBROADCASTSSZm:
2403 case X86::VBROADCASTSDYrm:
2404 case X86::VBROADCASTSDZ256m:
2405 case X86::VBROADCASTSDZm:
2406 case X86::VPBROADCASTBrm:
2407 case X86::VPBROADCASTBYrm:
2408 case X86::VPBROADCASTBZ128m:
2409 case X86::VPBROADCASTBZ256m:
2410 case X86::VPBROADCASTBZm:
2411 case X86::VPBROADCASTDrm:
2412 case X86::VPBROADCASTDYrm:
2413 case X86::VPBROADCASTDZ128m:
2414 case X86::VPBROADCASTDZ256m:
2415 case X86::VPBROADCASTDZm:
2416 case X86::VPBROADCASTQrm:
2417 case X86::VPBROADCASTQYrm:
2418 case X86::VPBROADCASTQZ128m:
2419 case X86::VPBROADCASTQZ256m:
2420 case X86::VPBROADCASTQZm:
2421 case X86::VPBROADCASTWrm:
2422 case X86::VPBROADCASTWYrm:
2423 case X86::VPBROADCASTWZ128m:
2424 case X86::VPBROADCASTWZ256m:
2425 case X86::VPBROADCASTWZm:
2434 case X86::MOVDDUPrm: NumElts = 2;
break;
2435 case X86::VMOVDDUPrm: NumElts = 2;
break;
2436 case X86::VMOVDDUPZ128rm: NumElts = 2;
break;
2437 case X86::VBROADCASTSSrm: NumElts = 4;
break;
2438 case X86::VBROADCASTSSYrm: NumElts = 8;
break;
2439 case X86::VBROADCASTSSZ128m: NumElts = 4;
break;
2440 case X86::VBROADCASTSSZ256m: NumElts = 8;
break;
2441 case X86::VBROADCASTSSZm: NumElts = 16;
break;
2442 case X86::VBROADCASTSDYrm: NumElts = 4;
break;
2443 case X86::VBROADCASTSDZ256m: NumElts = 4;
break;
2444 case X86::VBROADCASTSDZm: NumElts = 8;
break;
2445 case X86::VPBROADCASTBrm: NumElts = 16;
break;
2446 case X86::VPBROADCASTBYrm: NumElts = 32;
break;
2447 case X86::VPBROADCASTBZ128m: NumElts = 16;
break;
2448 case X86::VPBROADCASTBZ256m: NumElts = 32;
break;
2449 case X86::VPBROADCASTBZm: NumElts = 64;
break;
2450 case X86::VPBROADCASTDrm: NumElts = 4;
break;
2451 case X86::VPBROADCASTDYrm: NumElts = 8;
break;
2452 case X86::VPBROADCASTDZ128m: NumElts = 4;
break;
2453 case X86::VPBROADCASTDZ256m: NumElts = 8;
break;
2454 case X86::VPBROADCASTDZm: NumElts = 16;
break;
2455 case X86::VPBROADCASTQrm: NumElts = 2;
break;
2456 case X86::VPBROADCASTQYrm: NumElts = 4;
break;
2457 case X86::VPBROADCASTQZ128m: NumElts = 2;
break;
2458 case X86::VPBROADCASTQZ256m: NumElts = 4;
break;
2459 case X86::VPBROADCASTQZm: NumElts = 8;
break;
2460 case X86::VPBROADCASTWrm: NumElts = 8;
break;
2461 case X86::VPBROADCASTWYrm: NumElts = 16;
break;
2462 case X86::VPBROADCASTWZ128m: NumElts = 8;
break;
2463 case X86::VPBROADCASTWZ256m: NumElts = 16;
break;
2464 case X86::VPBROADCASTWZm: NumElts = 32;
break;
2467 std::string Comment;
2472 for (
int i = 0; i != NumElts; ++i) {
2483 MCInstLowering.Lower(MI, TmpInst);
2500 EmitAndCountInstruction(TmpInst);
unsigned getTargetFlags() const
MO_SECREL - On a symbol operand this indicates that the immediate is the offset from beginning of sec...
const MCAsmInfo * getAsmInfo() const
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
A parsed version of the target data layout string in and methods for querying it. ...
mop_iterator operands_end()
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
union llvm::MachineConstantPoolEntry::@168 Val
The constant itself.
unsigned getNextScratchIdx(unsigned StartIdx=0) const
Get the next scratch register operand index.
static const char * getRegisterName(unsigned RegNo)
uint64_t getZExtValue() const
Get zero extended value.
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "...
virtual bool emitFPOSetFrame(unsigned Reg, SMLoc L={})=0
bool isCall(QueryType Type=AnyInBundle) const
MachineBasicBlock * getMBB() const
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
MCTargetOptions MCOptions
Machine level options.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
This class represents lattice values for constants.
PointerTy getPointer() const
void setTargetFlags(unsigned F)
StringRef getPrivateGlobalPrefix() const
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
void DecodeVPPERMMask(ArrayRef< uint64_t > RawMask, const APInt &UndefElts, SmallVectorImpl< int > &ShuffleMask)
Decode a VPPERM mask from a raw array of constants such as from BUILD_VECTOR.
MO_TLSLD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with ...
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate is some TLS offset from the ...
MCContext & OutContext
This is the context for the output file that we are streaming.
static MachineModuleInfoMachO & getMachOMMI(AsmPrinter &AP)
static MCOperand createExpr(const MCExpr *Val)
unsigned getNumWords() const
Get the number of words.
const MCSubtargetInfo & getSubtargetInfo() const
Return information about subtarget.
This provides a very simple, boring adaptor for a begin and end iterator into a range type...
virtual void EmitBytes(StringRef Data)
Emit the bytes in Data into the output.
Address of indexed Jump Table for switch.
This class represents a function call, abstracting a target machine's calling convention.
PointerIntPair< MCSymbol *, 1, bool > StubValueTy
static std::string getShuffleComment(const MachineInstr *MI, unsigned SrcOp1Idx, unsigned SrcOp2Idx, ArrayRef< int > Mask)
A raw_ostream that writes to an SmallVector or SmallString.
MachineBasicBlock reference.
MachineFunction * MF
The current machine function.
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
MachineInstrBundleIterator< const MachineInstr > const_iterator
MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...
MO_DTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry with...
static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, const MCSubtargetInfo &STI)
Emit the optimal amount of multi-byte nops on X86.
virtual bool emitFPOPushReg(unsigned Reg, SMLoc L={})=0
iterator_range< mop_iterator > operands()
print alias Alias Set Printer
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
unsigned getSlotSize() const
virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
bool canRelaxRelocations() const
unsigned getBitWidth() const
Return the number of bits in the APInt.
AddrNumOperands - Total number of operands in a memory reference.
Mask of preserved registers.
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
MCContext & getContext() const
void recordSled(MCSymbol *Sled, const MachineInstr &MI, SledKind Kind, uint8_t Version=0)
CLEANUPRET - Represents a return from a cleanup block funclet.
unsigned getNumFrameInfos()
MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates that the reference is actually...
bool isMachineConstantPoolEntry() const
isMachineConstantPoolEntry - Return true if the MachineConstantPoolEntry is indeed a target specific ...
static MCOperand createReg(unsigned Reg)
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
virtual bool emitFPOStackAlloc(unsigned StackAlloc, SMLoc L={})=0
MachineModuleInfoCOFF - This is a MachineModuleInfoImpl implementation for COFF targets.
unsigned getNumOperands() const
Retuns the total number of operands.
void DecodeVPERMILPMask(unsigned NumElts, unsigned ScalarBits, ArrayRef< uint64_t > RawMask, const APInt &UndefElts, SmallVectorImpl< int > &ShuffleMask)
Decode a VPERMILPD/VPERMILPS variable mask from a raw array of constants.
virtual void encodeInstruction(const MCInst &Inst, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
EncodeInstruction - Encode the given Inst to bytes on the output stream OS.
Base class for the full range of assembler expressions which are needed for parsing.
Name of external global symbol.
Represent a reference to a symbol from inside an expression.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
virtual void EmitWinCFISetFrame(MCRegister Register, unsigned Offset, SMLoc Loc=SMLoc())
const char * getSymbolName() const
#define CASE_ALL_MOV_RM()
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
unsigned getReg() const
Returns the register number.
Context object for machine code objects.
void recordFaultingOp(FaultKind FaultTy, const MCSymbol *HandlerLabel)
virtual void AddComment(const Twine &T, bool EOL=true)
Add a textual comment.
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Type * getType() const
All values are typed, get the type of this value.
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
void toString(SmallVectorImpl< char > &Str, unsigned FormatPrecision=0, unsigned FormatMaxPadding=3, bool TruncateZero=true) const
bool isPositionIndependent() const
MO_GOT - On a symbol operand this indicates that the immediate is the offset to the GOT entry for the...
virtual void EmitWinCFISaveXMM(MCRegister Register, unsigned Offset, SMLoc Loc=SMLoc())
MO_GOTTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry wi...
MO_ABS8 - On a symbol operand this indicates that the symbol is known to be an absolute symbol in ran...
ArrayRef< MCDwarfFrameInfo > getDwarfFrameInfos() const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
virtual void EmitWinCFISaveReg(MCRegister Register, unsigned Offset, SMLoc Loc=SMLoc())
virtual void emitRawComment(const Twine &T, bool TabPrefix=true)
Print T and prefix it with the comment string (normally #) and optionally a tab.
This class is a data container for one entry in a MachineConstantPool.
virtual void EmitBinaryData(StringRef Data)
Functionally identical to EmitBytes.
const MCExpr * getExpr() const
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the reference is actually to the "...
MCInstBuilder & addOperand(const MCOperand &Op)
Add an operand.
MachineModuleInfo * MMI
This is a pointer to the current MachineModuleInfo.
void recordStatepoint(const MachineInstr &MI)
Generate a stackmap record for a statepoint instruction.
Analysis containing CSE Info
Instances of this class represent a single low-level machine instruction.
auto count(R &&Range, const E &Element) -> typename std::iterator_traits< decltype(adl_begin(Range))>::difference_type
Wrapper function around std::count to count the number of times an element Element occurs in the give...
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false)
virtual bool emitFPOStackAlign(unsigned Align, SMLoc L={})=0
bool isX86_64ExtendedReg(unsigned RegNo)
isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or higher) register? e.g.
const Constant * ConstVal
This class is intended to be used as a base class for asm properties and features specific to the tar...
Address of a global value.
Streaming machine code generation interface.
MCInstBuilder & addReg(unsigned Reg)
Add a new register operand.
MCSymbol * createTempSymbol(bool CanBeUnnamed=true)
Create and return a new assembler temporary symbol with a unique but unspecified name.
MCTargetStreamer * getTargetStreamer()
MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a relocation of: SYMBOL_LABEL + [...
PointerIntPair - This class implements a pair of a pointer and small integer.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry w...
MO_TLVP - On a symbol operand this indicates that the immediate is some TLS offset.
virtual void EmitWinCFIPushReg(MCRegister Register, SMLoc Loc=SMLoc())
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This is an important base class in LLVM.
const GlobalValue * getGlobal() const
MO_TLSLDM - On a symbol operand this indicates that the immediate is the offset of the GOT entry with...
MCCodeEmitter - Generic instruction encoding interface.
TargetMachine & TM
Target machine description.
This class is intended to be used as a driving class for all asm writers.
void getNameWithPrefix(SmallVectorImpl< char > &Name, const GlobalValue *GV) const
bool hasInternalLinkage() const
Address of a basic block.
static unsigned convertTailJumpOpcode(unsigned Opcode)
static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst, unsigned Opcode)
Simplify things like MOV32rm to MOV32o32a.
MO_NTPOFF - On a symbol operand this indicates that the immediate is the negative thread-pointer offs...
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
MI-level patchpoint operands.
unsigned getNumOperands() const
void print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const
Print this MI to OS.
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
AddrSegmentReg - The operand # of the segment in the memory operand.
static const Constant * getConstantFromPool(const MachineInstr &MI, const MachineOperand &Op)
const MachineBasicBlock & front() const
bool useRetpolineIndirectCalls() const
virtual MCSymbol * GetCPISymbol(unsigned CPID) const
Return the symbol for the specified constant pool entry.
StubValueTy & getGVStubEntry(MCSymbol *Sym)
void DecodeVPERMIL2PMask(unsigned NumElts, unsigned ScalarBits, unsigned M2Z, ArrayRef< uint64_t > RawMask, const APInt &UndefElts, SmallVectorImpl< int > &ShuffleMask)
Decode a VPERMIL2PD/VPERMIL2PS variable mask from a raw array of constants.
std::string & str()
Flushes the stream contents to the target string and returns the string's reference.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void recordPatchPoint(const MachineInstr &MI)
Generate a stackmap record for a patchpoint instruction.
MO_TLSGD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with ...
const std::vector< MachineConstantPoolEntry > & getConstants() const
virtual void EmitWinCFIPushFrame(bool Code, SMLoc Loc=SMLoc())
MO_TPOFF - On a symbol operand this indicates that the immediate is the thread-pointer offset for the...
static void printConstant(const APInt &Val, raw_ostream &CS)
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
void setOpcode(unsigned Op)
MCSymbol * GetBlockAddressSymbol(const BlockAddress *BA) const
Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block.
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
static MCOperand LowerSymbolOperand(const MachineInstr *MI, const MachineOperand &MO, AsmPrinter &AP)
MCSymbol * getSymbol(const GlobalValue *GV) const
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
virtual void EmitWinCFIEndProlog(SMLoc Loc=SMLoc())
virtual void EmitCodeAlignment(unsigned ByteAlignment, unsigned MaxBytesToEmit=0)
Emit nops until the byte alignment ByteAlignment is reached.
const MCOperand & getOperand(unsigned i) const
virtual void EmitWinCFIAllocStack(unsigned Size, SMLoc Loc=SMLoc())
X86 target streamer implementing x86-only assembly directives.
MCSymbol reference (for debug/eh info)
StubValueTy & getGVStubEntry(MCSymbol *Sym)
Target - Wrapper for Target specific information.
Class for arbitrary precision integers.
void recordStackMap(const MachineInstr &MI)
Generate a stackmap record for a stackmap instruction.
virtual bool emitFPOEndPrologue(SMLoc L={})=0
bool getRtLibUseGOT() const
Returns true if PLT should be avoided for RTLib calls.
CATCHRET - Represents a return from a catch block funclet.
const MachineBasicBlock * getParent() const
const uint64_t * getRawData() const
This function returns a pointer to the internal storage of the APInt.
Representation of each machine instruction.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MO_GOTOFF - On a symbol operand this indicates that the immediate is the offset to the location of th...
static unsigned getRetOpcode(const X86Subtarget &Subtarget)
MCSymbol * GetJTISymbol(unsigned JTID, bool isLinkerPrivate=false) const
Return the symbol for the specified jump table entry.
MO_INDNTPOFF - On a symbol operand this indicates that the immediate is the absolute address of the G...
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
int64_t getOffset() const
Return the offset from the symbol in this operand.
const BlockAddress * getBlockAddress() const
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
Generic base class for all target subtargets.
MI-level Statepoint operands.
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given patchpoint should emit.
void EmitInstruction(const MachineInstr *MI) override
Targets should implement this to emit instructions.
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
const Module * getModule() const
MachineModuleInfoMachO - This is a MachineModuleInfoImpl implementation for MachO targets...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 'eh_return' gcc dwarf builtin...
MO_PLT - On a symbol operand this indicates that the immediate is offset to the PLT entry of symbol n...
StringRef getName() const
getName - Get the symbol name.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
A raw_ostream that writes to an std::string.
MCSymbol * getMCSymbol() const
mop_iterator operands_begin()
MCSymbol * getPICBaseSymbol() const
getPICBaseSymbol - Return a function-local symbol to represent the PIC base.
const MCOperandInfo * OpInfo
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
virtual void EmitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
This class implements an extremely fast bulk output stream that can only output to a stream...
Primary interface to the complete machine description for the target machine.
MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the immediate should get the value of th...
void getNameWithPrefix(raw_ostream &OS, const GlobalValue *GV, bool CannotUsePrivateLabel) const
Print the appropriate prefix and the specified global variable's name.
static MachineBasicBlock::const_iterator PrevCrossBBInst(MachineBasicBlock::const_iterator MBBI)
const MachineOperand & getCallTarget() const
Returns the target of the underlying call.
void addOperand(const MCOperand &Op)
StringRef - Represent a constant reference to a string, i.e.
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
Address of indexed Constant in Constant Pool.
static MCSymbol * GetSymbolFromOperand(const MachineOperand &MO, AsmPrinter &AP)
Register getReg() const
getReg - Returns the register number.
This holds information about one operand of a machine instruction, indicating the register class for ...
unsigned getOpcode() const
virtual bool isVerboseAsm() const
Return true if this streamer supports verbose assembly and if it is enabled.
const MachineOperand & getOperand(unsigned i) const
Instances of this class represent operands of the MCInst class.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
static MCOperand createImm(int64_t Val)
static unsigned EmitNop(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, const MCSubtargetInfo &STI)
Emit the largest nop instruction smaller than or equal to NumBytes bytes.
const X86Subtarget & getSubtarget() const
static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode)
Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with a short fixed-register form...
virtual void EmitCFIAdjustCfaOffset(int64_t Adjustment)
static void SimplifyMOVSX(MCInst &Inst)
If a movsx instruction has a shorter encoding for the used register simplify the instruction to use i...
uint8_t getAsmPrinterFlags() const
Return the asm printer flags bitvector.
Wrapper class representing virtual and physical registers.
MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the reference is actually to the "__imp...
static MachineOperand CreateMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
void DecodePSHUFBMask(ArrayRef< uint64_t > RawMask, const APInt &UndefElts, SmallVectorImpl< int > &ShuffleMask)
Decode a PSHUFB mask from a raw array of constants such as from BUILD_VECTOR.
static unsigned getRegisterWidth(const MCOperandInfo &Info)