LLVM  8.0.0svn
X86MCInstLower.cpp
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1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains code to lower X86 MachineInstrs to their corresponding
11 // MCInst records.
12 //
13 //===----------------------------------------------------------------------===//
14 
19 #include "Utils/X86ShuffleDecode.h"
20 #include "X86AsmPrinter.h"
21 #include "X86RegisterInfo.h"
23 #include "llvm/ADT/Optional.h"
24 #include "llvm/ADT/SmallString.h"
30 #include "llvm/CodeGen/StackMaps.h"
31 #include "llvm/IR/DataLayout.h"
32 #include "llvm/IR/GlobalValue.h"
33 #include "llvm/IR/Mangler.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCCodeEmitter.h"
36 #include "llvm/MC/MCContext.h"
37 #include "llvm/MC/MCExpr.h"
38 #include "llvm/MC/MCFixup.h"
39 #include "llvm/MC/MCInst.h"
40 #include "llvm/MC/MCInstBuilder.h"
41 #include "llvm/MC/MCSection.h"
42 #include "llvm/MC/MCSectionELF.h"
43 #include "llvm/MC/MCStreamer.h"
44 #include "llvm/MC/MCSymbol.h"
45 #include "llvm/MC/MCSymbolELF.h"
47 
48 using namespace llvm;
49 
50 namespace {
51 
52 /// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst.
53 class X86MCInstLower {
54  MCContext &Ctx;
55  const MachineFunction &MF;
56  const TargetMachine &TM;
57  const MCAsmInfo &MAI;
59 
60 public:
61  X86MCInstLower(const MachineFunction &MF, X86AsmPrinter &asmprinter);
62 
63  Optional<MCOperand> LowerMachineOperand(const MachineInstr *MI,
64  const MachineOperand &MO) const;
65  void Lower(const MachineInstr *MI, MCInst &OutMI) const;
66 
68  MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
69 
70 private:
72 };
73 
74 } // end anonymous namespace
75 
76 // Emit a minimal sequence of nops spanning NumBytes bytes.
77 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
78  const MCSubtargetInfo &STI);
79 
81  const MCSubtargetInfo &STI,
82  MCCodeEmitter *CodeEmitter) {
83  if (InShadow) {
86  raw_svector_ostream VecOS(Code);
87  CodeEmitter->encodeInstruction(Inst, VecOS, Fixups, STI);
88  CurrentShadowSize += Code.size();
89  if (CurrentShadowSize >= RequiredShadowSize)
90  InShadow = false; // The shadow is big enough. Stop counting.
91  }
92 }
93 
94 void X86AsmPrinter::StackMapShadowTracker::emitShadowPadding(
95  MCStreamer &OutStreamer, const MCSubtargetInfo &STI) {
96  if (InShadow && CurrentShadowSize < RequiredShadowSize) {
97  InShadow = false;
98  EmitNops(OutStreamer, RequiredShadowSize - CurrentShadowSize,
99  MF->getSubtarget<X86Subtarget>().is64Bit(), STI);
100  }
101 }
102 
103 void X86AsmPrinter::EmitAndCountInstruction(MCInst &Inst) {
104  OutStreamer->EmitInstruction(Inst, getSubtargetInfo(),
105  EnablePrintSchedInfo &&
106  !(Inst.getFlags() & X86::NO_SCHED_INFO));
107  SMShadowTracker.count(Inst, getSubtargetInfo(), CodeEmitter.get());
108 }
109 
110 X86MCInstLower::X86MCInstLower(const MachineFunction &mf,
111  X86AsmPrinter &asmprinter)
112  : Ctx(mf.getContext()), MF(mf), TM(mf.getTarget()), MAI(*TM.getMCAsmInfo()),
113  AsmPrinter(asmprinter) {}
114 
116  return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>();
117 }
118 
119 /// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
120 /// operand to an MCSymbol.
122  const DataLayout &DL = MF.getDataLayout();
123  assert((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) &&
124  "Isn't a symbol reference");
125 
126  MCSymbol *Sym = nullptr;
128  StringRef Suffix;
129 
130  switch (MO.getTargetFlags()) {
131  case X86II::MO_DLLIMPORT:
132  // Handle dllimport linkage.
133  Name += "__imp_";
134  break;
135  case X86II::MO_COFFSTUB:
136  Name += ".refptr.";
137  break;
140  Suffix = "$non_lazy_ptr";
141  break;
142  }
143 
144  if (!Suffix.empty())
145  Name += DL.getPrivateGlobalPrefix();
146 
147  if (MO.isGlobal()) {
148  const GlobalValue *GV = MO.getGlobal();
149  AsmPrinter.getNameWithPrefix(Name, GV);
150  } else if (MO.isSymbol()) {
152  } else if (MO.isMBB()) {
153  assert(Suffix.empty());
154  Sym = MO.getMBB()->getSymbol();
155  }
156 
157  Name += Suffix;
158  if (!Sym)
159  Sym = Ctx.getOrCreateSymbol(Name);
160 
161  // If the target flags on the operand changes the name of the symbol, do that
162  // before we return the symbol.
163  switch (MO.getTargetFlags()) {
164  default:
165  break;
166  case X86II::MO_COFFSTUB: {
167  MachineModuleInfoCOFF &MMICOFF =
168  MF.getMMI().getObjFileInfo<MachineModuleInfoCOFF>();
169  MachineModuleInfoImpl::StubValueTy &StubSym = MMICOFF.getGVStubEntry(Sym);
170  if (!StubSym.getPointer()) {
171  assert(MO.isGlobal() && "Extern symbol not handled yet");
173  AsmPrinter.getSymbol(MO.getGlobal()), true);
174  }
175  break;
176  }
181  if (!StubSym.getPointer()) {
182  assert(MO.isGlobal() && "Extern symbol not handled yet");
185  !MO.getGlobal()->hasInternalLinkage());
186  }
187  break;
188  }
189  }
190 
191  return Sym;
192 }
193 
195  MCSymbol *Sym) const {
196  // FIXME: We would like an efficient form for this, so we don't have to do a
197  // lot of extra uniquing.
198  const MCExpr *Expr = nullptr;
200 
201  switch (MO.getTargetFlags()) {
202  default:
203  llvm_unreachable("Unknown target flag on GV operand");
204  case X86II::MO_NO_FLAG: // No flag.
205  // These affect the name of the symbol, not any suffix.
207  case X86II::MO_DLLIMPORT:
208  case X86II::MO_COFFSTUB:
209  break;
210 
211  case X86II::MO_TLVP:
212  RefKind = MCSymbolRefExpr::VK_TLVP;
213  break;
216  // Subtract the pic base.
218  Expr, MCSymbolRefExpr::create(MF.getPICBaseSymbol(), Ctx), Ctx);
219  break;
220  case X86II::MO_SECREL:
221  RefKind = MCSymbolRefExpr::VK_SECREL;
222  break;
223  case X86II::MO_TLSGD:
224  RefKind = MCSymbolRefExpr::VK_TLSGD;
225  break;
226  case X86II::MO_TLSLD:
227  RefKind = MCSymbolRefExpr::VK_TLSLD;
228  break;
229  case X86II::MO_TLSLDM:
230  RefKind = MCSymbolRefExpr::VK_TLSLDM;
231  break;
232  case X86II::MO_GOTTPOFF:
234  break;
235  case X86II::MO_INDNTPOFF:
237  break;
238  case X86II::MO_TPOFF:
239  RefKind = MCSymbolRefExpr::VK_TPOFF;
240  break;
241  case X86II::MO_DTPOFF:
242  RefKind = MCSymbolRefExpr::VK_DTPOFF;
243  break;
244  case X86II::MO_NTPOFF:
245  RefKind = MCSymbolRefExpr::VK_NTPOFF;
246  break;
247  case X86II::MO_GOTNTPOFF:
249  break;
250  case X86II::MO_GOTPCREL:
252  break;
253  case X86II::MO_GOT:
254  RefKind = MCSymbolRefExpr::VK_GOT;
255  break;
256  case X86II::MO_GOTOFF:
257  RefKind = MCSymbolRefExpr::VK_GOTOFF;
258  break;
259  case X86II::MO_PLT:
260  RefKind = MCSymbolRefExpr::VK_PLT;
261  break;
262  case X86II::MO_ABS8:
264  break;
267  Expr = MCSymbolRefExpr::create(Sym, Ctx);
268  // Subtract the pic base.
270  Expr, MCSymbolRefExpr::create(MF.getPICBaseSymbol(), Ctx), Ctx);
271  if (MO.isJTI()) {
272  assert(MAI.doesSetDirectiveSuppressReloc());
273  // If .set directive is supported, use it to reduce the number of
274  // relocations the assembler will generate for differences between
275  // local labels. This is only safe when the symbols are in the same
276  // section so we are restricting it to jumptable references.
277  MCSymbol *Label = Ctx.createTempSymbol();
278  AsmPrinter.OutStreamer->EmitAssignment(Label, Expr);
279  Expr = MCSymbolRefExpr::create(Label, Ctx);
280  }
281  break;
282  }
283 
284  if (!Expr)
285  Expr = MCSymbolRefExpr::create(Sym, RefKind, Ctx);
286 
287  if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
289  Expr, MCConstantExpr::create(MO.getOffset(), Ctx), Ctx);
290  return MCOperand::createExpr(Expr);
291 }
292 
293 /// Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with
294 /// a short fixed-register form.
295 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
296  unsigned ImmOp = Inst.getNumOperands() - 1;
297  assert(Inst.getOperand(0).isReg() &&
298  (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) &&
299  ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
300  Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
301  Inst.getNumOperands() == 2) &&
302  "Unexpected instruction!");
303 
304  // Check whether the destination register can be fixed.
305  unsigned Reg = Inst.getOperand(0).getReg();
306  if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
307  return;
308 
309  // If so, rewrite the instruction.
310  MCOperand Saved = Inst.getOperand(ImmOp);
311  Inst = MCInst();
312  Inst.setOpcode(Opcode);
313  Inst.addOperand(Saved);
314 }
315 
316 /// If a movsx instruction has a shorter encoding for the used register
317 /// simplify the instruction to use it instead.
318 static void SimplifyMOVSX(MCInst &Inst) {
319  unsigned NewOpcode = 0;
320  unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg();
321  switch (Inst.getOpcode()) {
322  default:
323  llvm_unreachable("Unexpected instruction!");
324  case X86::MOVSX16rr8: // movsbw %al, %ax --> cbtw
325  if (Op0 == X86::AX && Op1 == X86::AL)
326  NewOpcode = X86::CBW;
327  break;
328  case X86::MOVSX32rr16: // movswl %ax, %eax --> cwtl
329  if (Op0 == X86::EAX && Op1 == X86::AX)
330  NewOpcode = X86::CWDE;
331  break;
332  case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq
333  if (Op0 == X86::RAX && Op1 == X86::EAX)
334  NewOpcode = X86::CDQE;
335  break;
336  }
337 
338  if (NewOpcode != 0) {
339  Inst = MCInst();
340  Inst.setOpcode(NewOpcode);
341  }
342 }
343 
344 /// Simplify things like MOV32rm to MOV32o32a.
346  unsigned Opcode) {
347  // Don't make these simplifications in 64-bit mode; other assemblers don't
348  // perform them because they make the code larger.
349  if (Printer.getSubtarget().is64Bit())
350  return;
351 
352  bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
353  unsigned AddrBase = IsStore;
354  unsigned RegOp = IsStore ? 0 : 5;
355  unsigned AddrOp = AddrBase + 3;
356  assert(
357  Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
358  Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() &&
359  Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() &&
360  Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() &&
361  Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() &&
362  (Inst.getOperand(AddrOp).isExpr() || Inst.getOperand(AddrOp).isImm()) &&
363  "Unexpected instruction!");
364 
365  // Check whether the destination register can be fixed.
366  unsigned Reg = Inst.getOperand(RegOp).getReg();
367  if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
368  return;
369 
370  // Check whether this is an absolute address.
371  // FIXME: We know TLVP symbol refs aren't, but there should be a better way
372  // to do this here.
373  bool Absolute = true;
374  if (Inst.getOperand(AddrOp).isExpr()) {
375  const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr();
376  if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE))
377  if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
378  Absolute = false;
379  }
380 
381  if (Absolute &&
382  (Inst.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 ||
383  Inst.getOperand(AddrBase + X86::AddrScaleAmt).getImm() != 1 ||
384  Inst.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0))
385  return;
386 
387  // If so, rewrite the instruction.
388  MCOperand Saved = Inst.getOperand(AddrOp);
389  MCOperand Seg = Inst.getOperand(AddrBase + X86::AddrSegmentReg);
390  Inst = MCInst();
391  Inst.setOpcode(Opcode);
392  Inst.addOperand(Saved);
393  Inst.addOperand(Seg);
394 }
395 
396 static unsigned getRetOpcode(const X86Subtarget &Subtarget) {
397  return Subtarget.is64Bit() ? X86::RETQ : X86::RETL;
398 }
399 
401 X86MCInstLower::LowerMachineOperand(const MachineInstr *MI,
402  const MachineOperand &MO) const {
403  switch (MO.getType()) {
404  default:
405  MI->print(errs());
406  llvm_unreachable("unknown operand type");
408  // Ignore all implicit register operands.
409  if (MO.isImplicit())
410  return None;
411  return MCOperand::createReg(MO.getReg());
413  return MCOperand::createImm(MO.getImm());
419  return LowerSymbolOperand(MO, MO.getMCSymbol());
425  return LowerSymbolOperand(
428  // Ignore call clobbers.
429  return None;
430  }
431 }
432 
433 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
434  OutMI.setOpcode(MI->getOpcode());
435 
436  for (const MachineOperand &MO : MI->operands())
437  if (auto MaybeMCOp = LowerMachineOperand(MI, MO))
438  OutMI.addOperand(MaybeMCOp.getValue());
439 
440  // Handle a few special cases to eliminate operand modifiers.
441 ReSimplify:
442  switch (OutMI.getOpcode()) {
443  case X86::LEA64_32r:
444  case X86::LEA64r:
445  case X86::LEA16r:
446  case X86::LEA32r:
447  // LEA should have a segment register, but it must be empty.
448  assert(OutMI.getNumOperands() == 1 + X86::AddrNumOperands &&
449  "Unexpected # of LEA operands");
450  assert(OutMI.getOperand(1 + X86::AddrSegmentReg).getReg() == 0 &&
451  "LEA has segment specified!");
452  break;
453 
454  // Commute operands to get a smaller encoding by using VEX.R instead of VEX.B
455  // if one of the registers is extended, but other isn't.
456  case X86::VMOVZPQILo2PQIrr:
457  case X86::VMOVAPDrr:
458  case X86::VMOVAPDYrr:
459  case X86::VMOVAPSrr:
460  case X86::VMOVAPSYrr:
461  case X86::VMOVDQArr:
462  case X86::VMOVDQAYrr:
463  case X86::VMOVDQUrr:
464  case X86::VMOVDQUYrr:
465  case X86::VMOVUPDrr:
466  case X86::VMOVUPDYrr:
467  case X86::VMOVUPSrr:
468  case X86::VMOVUPSYrr: {
469  if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
471  unsigned NewOpc;
472  switch (OutMI.getOpcode()) {
473  default: llvm_unreachable("Invalid opcode");
474  case X86::VMOVZPQILo2PQIrr: NewOpc = X86::VMOVPQI2QIrr; break;
475  case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
476  case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
477  case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;
478  case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
479  case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;
480  case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
481  case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break;
482  case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
483  case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break;
484  case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
485  case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break;
486  case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
487  }
488  OutMI.setOpcode(NewOpc);
489  }
490  break;
491  }
492  case X86::VMOVSDrr:
493  case X86::VMOVSSrr: {
494  if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
496  unsigned NewOpc;
497  switch (OutMI.getOpcode()) {
498  default: llvm_unreachable("Invalid opcode");
499  case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break;
500  case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break;
501  }
502  OutMI.setOpcode(NewOpc);
503  }
504  break;
505  }
506 
507  // TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have register
508  // inputs modeled as normal uses instead of implicit uses. As such, truncate
509  // off all but the first operand (the callee). FIXME: Change isel.
510  case X86::TAILJMPr64:
511  case X86::TAILJMPr64_REX:
512  case X86::CALL64r:
513  case X86::CALL64pcrel32: {
514  unsigned Opcode = OutMI.getOpcode();
515  MCOperand Saved = OutMI.getOperand(0);
516  OutMI = MCInst();
517  OutMI.setOpcode(Opcode);
518  OutMI.addOperand(Saved);
519  break;
520  }
521 
522  case X86::EH_RETURN:
523  case X86::EH_RETURN64: {
524  OutMI = MCInst();
525  OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));
526  break;
527  }
528 
529  case X86::CLEANUPRET: {
530  // Replace CATCHRET with the appropriate RET.
531  OutMI = MCInst();
532  OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));
533  break;
534  }
535 
536  case X86::CATCHRET: {
537  // Replace CATCHRET with the appropriate RET.
538  const X86Subtarget &Subtarget = AsmPrinter.getSubtarget();
539  unsigned ReturnReg = Subtarget.is64Bit() ? X86::RAX : X86::EAX;
540  OutMI = MCInst();
541  OutMI.setOpcode(getRetOpcode(Subtarget));
542  OutMI.addOperand(MCOperand::createReg(ReturnReg));
543  break;
544  }
545 
546  // TAILJMPd, TAILJMPd64, TailJMPd_cc - Lower to the correct jump
547  // instruction.
548  {
549  unsigned Opcode;
550  case X86::TAILJMPr:
551  Opcode = X86::JMP32r;
552  goto SetTailJmpOpcode;
553  case X86::TAILJMPd:
554  case X86::TAILJMPd64:
555  Opcode = X86::JMP_1;
556  goto SetTailJmpOpcode;
557  case X86::TAILJMPd_CC:
558  case X86::TAILJMPd64_CC:
560  static_cast<X86::CondCode>(MI->getOperand(1).getImm()));
561  goto SetTailJmpOpcode;
562 
563  SetTailJmpOpcode:
564  MCOperand Saved = OutMI.getOperand(0);
565  OutMI = MCInst();
566  OutMI.setOpcode(Opcode);
567  OutMI.addOperand(Saved);
568  break;
569  }
570 
571  case X86::DEC16r:
572  case X86::DEC32r:
573  case X86::INC16r:
574  case X86::INC32r:
575  // If we aren't in 64-bit mode we can use the 1-byte inc/dec instructions.
576  if (!AsmPrinter.getSubtarget().is64Bit()) {
577  unsigned Opcode;
578  switch (OutMI.getOpcode()) {
579  default: llvm_unreachable("Invalid opcode");
580  case X86::DEC16r: Opcode = X86::DEC16r_alt; break;
581  case X86::DEC32r: Opcode = X86::DEC32r_alt; break;
582  case X86::INC16r: Opcode = X86::INC16r_alt; break;
583  case X86::INC32r: Opcode = X86::INC32r_alt; break;
584  }
585  OutMI.setOpcode(Opcode);
586  }
587  break;
588 
589  // These are pseudo-ops for OR to help with the OR->ADD transformation. We do
590  // this with an ugly goto in case the resultant OR uses EAX and needs the
591  // short form.
592  case X86::ADD16rr_DB: OutMI.setOpcode(X86::OR16rr); goto ReSimplify;
593  case X86::ADD32rr_DB: OutMI.setOpcode(X86::OR32rr); goto ReSimplify;
594  case X86::ADD64rr_DB: OutMI.setOpcode(X86::OR64rr); goto ReSimplify;
595  case X86::ADD16ri_DB: OutMI.setOpcode(X86::OR16ri); goto ReSimplify;
596  case X86::ADD32ri_DB: OutMI.setOpcode(X86::OR32ri); goto ReSimplify;
597  case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify;
598  case X86::ADD16ri8_DB: OutMI.setOpcode(X86::OR16ri8); goto ReSimplify;
599  case X86::ADD32ri8_DB: OutMI.setOpcode(X86::OR32ri8); goto ReSimplify;
600  case X86::ADD64ri8_DB: OutMI.setOpcode(X86::OR64ri8); goto ReSimplify;
601 
602  // We don't currently select the correct instruction form for instructions
603  // which have a short %eax, etc. form. Handle this by custom lowering, for
604  // now.
605  //
606  // Note, we are currently not handling the following instructions:
607  // MOV64ao8, MOV64o8a
608  // XCHG16ar, XCHG32ar, XCHG64ar
609  case X86::MOV8mr_NOREX:
610  case X86::MOV8mr:
611  case X86::MOV8rm_NOREX:
612  case X86::MOV8rm:
613  case X86::MOV16mr:
614  case X86::MOV16rm:
615  case X86::MOV32mr:
616  case X86::MOV32rm: {
617  unsigned NewOpc;
618  switch (OutMI.getOpcode()) {
619  default: llvm_unreachable("Invalid opcode");
620  case X86::MOV8mr_NOREX:
621  case X86::MOV8mr: NewOpc = X86::MOV8o32a; break;
622  case X86::MOV8rm_NOREX:
623  case X86::MOV8rm: NewOpc = X86::MOV8ao32; break;
624  case X86::MOV16mr: NewOpc = X86::MOV16o32a; break;
625  case X86::MOV16rm: NewOpc = X86::MOV16ao32; break;
626  case X86::MOV32mr: NewOpc = X86::MOV32o32a; break;
627  case X86::MOV32rm: NewOpc = X86::MOV32ao32; break;
628  }
629  SimplifyShortMoveForm(AsmPrinter, OutMI, NewOpc);
630  break;
631  }
632 
633  case X86::ADC8ri: case X86::ADC16ri: case X86::ADC32ri: case X86::ADC64ri32:
634  case X86::ADD8ri: case X86::ADD16ri: case X86::ADD32ri: case X86::ADD64ri32:
635  case X86::AND8ri: case X86::AND16ri: case X86::AND32ri: case X86::AND64ri32:
636  case X86::CMP8ri: case X86::CMP16ri: case X86::CMP32ri: case X86::CMP64ri32:
637  case X86::OR8ri: case X86::OR16ri: case X86::OR32ri: case X86::OR64ri32:
638  case X86::SBB8ri: case X86::SBB16ri: case X86::SBB32ri: case X86::SBB64ri32:
639  case X86::SUB8ri: case X86::SUB16ri: case X86::SUB32ri: case X86::SUB64ri32:
640  case X86::TEST8ri:case X86::TEST16ri:case X86::TEST32ri:case X86::TEST64ri32:
641  case X86::XOR8ri: case X86::XOR16ri: case X86::XOR32ri: case X86::XOR64ri32: {
642  unsigned NewOpc;
643  switch (OutMI.getOpcode()) {
644  default: llvm_unreachable("Invalid opcode");
645  case X86::ADC8ri: NewOpc = X86::ADC8i8; break;
646  case X86::ADC16ri: NewOpc = X86::ADC16i16; break;
647  case X86::ADC32ri: NewOpc = X86::ADC32i32; break;
648  case X86::ADC64ri32: NewOpc = X86::ADC64i32; break;
649  case X86::ADD8ri: NewOpc = X86::ADD8i8; break;
650  case X86::ADD16ri: NewOpc = X86::ADD16i16; break;
651  case X86::ADD32ri: NewOpc = X86::ADD32i32; break;
652  case X86::ADD64ri32: NewOpc = X86::ADD64i32; break;
653  case X86::AND8ri: NewOpc = X86::AND8i8; break;
654  case X86::AND16ri: NewOpc = X86::AND16i16; break;
655  case X86::AND32ri: NewOpc = X86::AND32i32; break;
656  case X86::AND64ri32: NewOpc = X86::AND64i32; break;
657  case X86::CMP8ri: NewOpc = X86::CMP8i8; break;
658  case X86::CMP16ri: NewOpc = X86::CMP16i16; break;
659  case X86::CMP32ri: NewOpc = X86::CMP32i32; break;
660  case X86::CMP64ri32: NewOpc = X86::CMP64i32; break;
661  case X86::OR8ri: NewOpc = X86::OR8i8; break;
662  case X86::OR16ri: NewOpc = X86::OR16i16; break;
663  case X86::OR32ri: NewOpc = X86::OR32i32; break;
664  case X86::OR64ri32: NewOpc = X86::OR64i32; break;
665  case X86::SBB8ri: NewOpc = X86::SBB8i8; break;
666  case X86::SBB16ri: NewOpc = X86::SBB16i16; break;
667  case X86::SBB32ri: NewOpc = X86::SBB32i32; break;
668  case X86::SBB64ri32: NewOpc = X86::SBB64i32; break;
669  case X86::SUB8ri: NewOpc = X86::SUB8i8; break;
670  case X86::SUB16ri: NewOpc = X86::SUB16i16; break;
671  case X86::SUB32ri: NewOpc = X86::SUB32i32; break;
672  case X86::SUB64ri32: NewOpc = X86::SUB64i32; break;
673  case X86::TEST8ri: NewOpc = X86::TEST8i8; break;
674  case X86::TEST16ri: NewOpc = X86::TEST16i16; break;
675  case X86::TEST32ri: NewOpc = X86::TEST32i32; break;
676  case X86::TEST64ri32: NewOpc = X86::TEST64i32; break;
677  case X86::XOR8ri: NewOpc = X86::XOR8i8; break;
678  case X86::XOR16ri: NewOpc = X86::XOR16i16; break;
679  case X86::XOR32ri: NewOpc = X86::XOR32i32; break;
680  case X86::XOR64ri32: NewOpc = X86::XOR64i32; break;
681  }
682  SimplifyShortImmForm(OutMI, NewOpc);
683  break;
684  }
685 
686  // Try to shrink some forms of movsx.
687  case X86::MOVSX16rr8:
688  case X86::MOVSX32rr16:
689  case X86::MOVSX64rr32:
690  SimplifyMOVSX(OutMI);
691  break;
692  }
693 }
694 
695 void X86AsmPrinter::LowerTlsAddr(X86MCInstLower &MCInstLowering,
696  const MachineInstr &MI) {
697 
698  bool is64Bits = MI.getOpcode() == X86::TLS_addr64 ||
699  MI.getOpcode() == X86::TLS_base_addr64;
700 
701  bool needsPadding = MI.getOpcode() == X86::TLS_addr64;
702 
703  MCContext &context = OutStreamer->getContext();
704 
705  if (needsPadding)
706  EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
707 
709  switch (MI.getOpcode()) {
710  case X86::TLS_addr32:
711  case X86::TLS_addr64:
713  break;
714  case X86::TLS_base_addr32:
716  break;
717  case X86::TLS_base_addr64:
719  break;
720  default:
721  llvm_unreachable("unexpected opcode");
722  }
723 
724  MCSymbol *sym = MCInstLowering.GetSymbolFromOperand(MI.getOperand(3));
725  const MCSymbolRefExpr *symRef = MCSymbolRefExpr::create(sym, SRVK, context);
726 
727  MCInst LEA;
728  if (is64Bits) {
729  LEA.setOpcode(X86::LEA64r);
730  LEA.addOperand(MCOperand::createReg(X86::RDI)); // dest
731  LEA.addOperand(MCOperand::createReg(X86::RIP)); // base
732  LEA.addOperand(MCOperand::createImm(1)); // scale
733  LEA.addOperand(MCOperand::createReg(0)); // index
734  LEA.addOperand(MCOperand::createExpr(symRef)); // disp
735  LEA.addOperand(MCOperand::createReg(0)); // seg
736  } else if (SRVK == MCSymbolRefExpr::VK_TLSLDM) {
737  LEA.setOpcode(X86::LEA32r);
740  LEA.addOperand(MCOperand::createImm(1)); // scale
741  LEA.addOperand(MCOperand::createReg(0)); // index
742  LEA.addOperand(MCOperand::createExpr(symRef)); // disp
743  LEA.addOperand(MCOperand::createReg(0)); // seg
744  } else {
745  LEA.setOpcode(X86::LEA32r);
747  LEA.addOperand(MCOperand::createReg(0)); // base
748  LEA.addOperand(MCOperand::createImm(1)); // scale
750  LEA.addOperand(MCOperand::createExpr(symRef)); // disp
751  LEA.addOperand(MCOperand::createReg(0)); // seg
752  }
753  EmitAndCountInstruction(LEA);
754 
755  if (needsPadding) {
756  EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
757  EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
758  EmitAndCountInstruction(MCInstBuilder(X86::REX64_PREFIX));
759  }
760 
761  StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr";
762  MCSymbol *tlsGetAddr = context.getOrCreateSymbol(name);
763  const MCSymbolRefExpr *tlsRef =
764  MCSymbolRefExpr::create(tlsGetAddr, MCSymbolRefExpr::VK_PLT, context);
765 
766  EmitAndCountInstruction(
767  MCInstBuilder(is64Bits ? X86::CALL64pcrel32 : X86::CALLpcrel32)
768  .addExpr(tlsRef));
769 }
770 
771 /// Emit the largest nop instruction smaller than or equal to \p NumBytes
772 /// bytes. Return the size of nop emitted.
773 static unsigned EmitNop(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
774  const MCSubtargetInfo &STI) {
775  // This works only for 64bit. For 32bit we have to do additional checking if
776  // the CPU supports multi-byte nops.
777  assert(Is64Bit && "EmitNops only supports X86-64");
778 
779  unsigned NopSize;
780  unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;
781  Opc = IndexReg = Displacement = SegmentReg = 0;
782  BaseReg = X86::RAX;
783  ScaleVal = 1;
784  switch (NumBytes) {
785  case 0:
786  llvm_unreachable("Zero nops?");
787  break;
788  case 1:
789  NopSize = 1;
790  Opc = X86::NOOP;
791  break;
792  case 2:
793  NopSize = 2;
794  Opc = X86::XCHG16ar;
795  break;
796  case 3:
797  NopSize = 3;
798  Opc = X86::NOOPL;
799  break;
800  case 4:
801  NopSize = 4;
802  Opc = X86::NOOPL;
803  Displacement = 8;
804  break;
805  case 5:
806  NopSize = 5;
807  Opc = X86::NOOPL;
808  Displacement = 8;
809  IndexReg = X86::RAX;
810  break;
811  case 6:
812  NopSize = 6;
813  Opc = X86::NOOPW;
814  Displacement = 8;
815  IndexReg = X86::RAX;
816  break;
817  case 7:
818  NopSize = 7;
819  Opc = X86::NOOPL;
820  Displacement = 512;
821  break;
822  case 8:
823  NopSize = 8;
824  Opc = X86::NOOPL;
825  Displacement = 512;
826  IndexReg = X86::RAX;
827  break;
828  case 9:
829  NopSize = 9;
830  Opc = X86::NOOPW;
831  Displacement = 512;
832  IndexReg = X86::RAX;
833  break;
834  default:
835  NopSize = 10;
836  Opc = X86::NOOPW;
837  Displacement = 512;
838  IndexReg = X86::RAX;
839  SegmentReg = X86::CS;
840  break;
841  }
842 
843  unsigned NumPrefixes = std::min(NumBytes - NopSize, 5U);
844  NopSize += NumPrefixes;
845  for (unsigned i = 0; i != NumPrefixes; ++i)
846  OS.EmitBytes("\x66");
847 
848  switch (Opc) {
849  default: llvm_unreachable("Unexpected opcode");
850  case X86::NOOP:
851  OS.EmitInstruction(MCInstBuilder(Opc), STI);
852  break;
853  case X86::XCHG16ar:
854  OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX).addReg(X86::AX), STI);
855  break;
856  case X86::NOOPL:
857  case X86::NOOPW:
859  .addReg(BaseReg)
860  .addImm(ScaleVal)
861  .addReg(IndexReg)
862  .addImm(Displacement)
863  .addReg(SegmentReg),
864  STI);
865  break;
866  }
867  assert(NopSize <= NumBytes && "We overemitted?");
868  return NopSize;
869 }
870 
871 /// Emit the optimal amount of multi-byte nops on X86.
872 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
873  const MCSubtargetInfo &STI) {
874  unsigned NopsToEmit = NumBytes;
875  (void)NopsToEmit;
876  while (NumBytes) {
877  NumBytes -= EmitNop(OS, NumBytes, Is64Bit, STI);
878  assert(NopsToEmit >= NumBytes && "Emitted more than I asked for!");
879  }
880 }
881 
882 void X86AsmPrinter::LowerSTATEPOINT(const MachineInstr &MI,
883  X86MCInstLower &MCIL) {
884  assert(Subtarget->is64Bit() && "Statepoint currently only supports X86-64");
885 
886  StatepointOpers SOpers(&MI);
887  if (unsigned PatchBytes = SOpers.getNumPatchBytes()) {
888  EmitNops(*OutStreamer, PatchBytes, Subtarget->is64Bit(),
889  getSubtargetInfo());
890  } else {
891  // Lower call target and choose correct opcode
892  const MachineOperand &CallTarget = SOpers.getCallTarget();
893  MCOperand CallTargetMCOp;
894  unsigned CallOpcode;
895  switch (CallTarget.getType()) {
898  CallTargetMCOp = MCIL.LowerSymbolOperand(
899  CallTarget, MCIL.GetSymbolFromOperand(CallTarget));
900  CallOpcode = X86::CALL64pcrel32;
901  // Currently, we only support relative addressing with statepoints.
902  // Otherwise, we'll need a scratch register to hold the target
903  // address. You'll fail asserts during load & relocation if this
904  // symbol is to far away. (TODO: support non-relative addressing)
905  break;
907  CallTargetMCOp = MCOperand::createImm(CallTarget.getImm());
908  CallOpcode = X86::CALL64pcrel32;
909  // Currently, we only support relative addressing with statepoints.
910  // Otherwise, we'll need a scratch register to hold the target
911  // immediate. You'll fail asserts during load & relocation if this
912  // address is to far away. (TODO: support non-relative addressing)
913  break;
915  // FIXME: Add retpoline support and remove this.
916  if (Subtarget->useRetpolineIndirectCalls())
917  report_fatal_error("Lowering register statepoints with retpoline not "
918  "yet implemented.");
919  CallTargetMCOp = MCOperand::createReg(CallTarget.getReg());
920  CallOpcode = X86::CALL64r;
921  break;
922  default:
923  llvm_unreachable("Unsupported operand type in statepoint call target");
924  break;
925  }
926 
927  // Emit call
929  CallInst.setOpcode(CallOpcode);
930  CallInst.addOperand(CallTargetMCOp);
931  OutStreamer->EmitInstruction(CallInst, getSubtargetInfo());
932  }
933 
934  // Record our statepoint node in the same section used by STACKMAP
935  // and PATCHPOINT
936  SM.recordStatepoint(MI);
937 }
938 
939 void X86AsmPrinter::LowerFAULTING_OP(const MachineInstr &FaultingMI,
940  X86MCInstLower &MCIL) {
941  // FAULTING_LOAD_OP <def>, <faltinf type>, <MBB handler>,
942  // <opcode>, <operands>
943 
944  unsigned DefRegister = FaultingMI.getOperand(0).getReg();
946  static_cast<FaultMaps::FaultKind>(FaultingMI.getOperand(1).getImm());
947  MCSymbol *HandlerLabel = FaultingMI.getOperand(2).getMBB()->getSymbol();
948  unsigned Opcode = FaultingMI.getOperand(3).getImm();
949  unsigned OperandsBeginIdx = 4;
950 
951  assert(FK < FaultMaps::FaultKindMax && "Invalid Faulting Kind!");
952  FM.recordFaultingOp(FK, HandlerLabel);
953 
954  MCInst MI;
955  MI.setOpcode(Opcode);
956 
957  if (DefRegister != X86::NoRegister)
958  MI.addOperand(MCOperand::createReg(DefRegister));
959 
960  for (auto I = FaultingMI.operands_begin() + OperandsBeginIdx,
961  E = FaultingMI.operands_end();
962  I != E; ++I)
963  if (auto MaybeOperand = MCIL.LowerMachineOperand(&FaultingMI, *I))
964  MI.addOperand(MaybeOperand.getValue());
965 
966  OutStreamer->EmitInstruction(MI, getSubtargetInfo());
967 }
968 
969 void X86AsmPrinter::LowerFENTRY_CALL(const MachineInstr &MI,
970  X86MCInstLower &MCIL) {
971  bool Is64Bits = Subtarget->is64Bit();
972  MCContext &Ctx = OutStreamer->getContext();
973  MCSymbol *fentry = Ctx.getOrCreateSymbol("__fentry__");
974  const MCSymbolRefExpr *Op =
976 
977  EmitAndCountInstruction(
978  MCInstBuilder(Is64Bits ? X86::CALL64pcrel32 : X86::CALLpcrel32)
979  .addExpr(Op));
980 }
981 
982 void X86AsmPrinter::LowerPATCHABLE_OP(const MachineInstr &MI,
983  X86MCInstLower &MCIL) {
984  // PATCHABLE_OP minsize, opcode, operands
985 
986  unsigned MinSize = MI.getOperand(0).getImm();
987  unsigned Opcode = MI.getOperand(1).getImm();
988 
989  MCInst MCI;
990  MCI.setOpcode(Opcode);
991  for (auto &MO : make_range(MI.operands_begin() + 2, MI.operands_end()))
992  if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO))
993  MCI.addOperand(MaybeOperand.getValue());
994 
995  SmallString<256> Code;
997  raw_svector_ostream VecOS(Code);
998  CodeEmitter->encodeInstruction(MCI, VecOS, Fixups, getSubtargetInfo());
999 
1000  if (Code.size() < MinSize) {
1001  if (MinSize == 2 && Opcode == X86::PUSH64r) {
1002  // This is an optimization that lets us get away without emitting a nop in
1003  // many cases.
1004  //
1005  // NB! In some cases the encoding for PUSH64r (e.g. PUSH64r %r9) takes two
1006  // bytes too, so the check on MinSize is important.
1007  MCI.setOpcode(X86::PUSH64rmr);
1008  } else {
1009  unsigned NopSize = EmitNop(*OutStreamer, MinSize, Subtarget->is64Bit(),
1010  getSubtargetInfo());
1011  assert(NopSize == MinSize && "Could not implement MinSize!");
1012  (void)NopSize;
1013  }
1014  }
1015 
1016  OutStreamer->EmitInstruction(MCI, getSubtargetInfo());
1017 }
1018 
1019 // Lower a stackmap of the form:
1020 // <id>, <shadowBytes>, ...
1021 void X86AsmPrinter::LowerSTACKMAP(const MachineInstr &MI) {
1022  SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
1023  SM.recordStackMap(MI);
1024  unsigned NumShadowBytes = MI.getOperand(1).getImm();
1025  SMShadowTracker.reset(NumShadowBytes);
1026 }
1027 
1028 // Lower a patchpoint of the form:
1029 // [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ...
1030 void X86AsmPrinter::LowerPATCHPOINT(const MachineInstr &MI,
1031  X86MCInstLower &MCIL) {
1032  assert(Subtarget->is64Bit() && "Patchpoint currently only supports X86-64");
1033 
1034  SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
1035 
1036  SM.recordPatchPoint(MI);
1037 
1038  PatchPointOpers opers(&MI);
1039  unsigned ScratchIdx = opers.getNextScratchIdx();
1040  unsigned EncodedBytes = 0;
1041  const MachineOperand &CalleeMO = opers.getCallTarget();
1042 
1043  // Check for null target. If target is non-null (i.e. is non-zero or is
1044  // symbolic) then emit a call.
1045  if (!(CalleeMO.isImm() && !CalleeMO.getImm())) {
1046  MCOperand CalleeMCOp;
1047  switch (CalleeMO.getType()) {
1048  default:
1049  /// FIXME: Add a verifier check for bad callee types.
1050  llvm_unreachable("Unrecognized callee operand type.");
1052  if (CalleeMO.getImm())
1053  CalleeMCOp = MCOperand::createImm(CalleeMO.getImm());
1054  break;
1057  CalleeMCOp = MCIL.LowerSymbolOperand(CalleeMO,
1058  MCIL.GetSymbolFromOperand(CalleeMO));
1059  break;
1060  }
1061 
1062  // Emit MOV to materialize the target address and the CALL to target.
1063  // This is encoded with 12-13 bytes, depending on which register is used.
1064  unsigned ScratchReg = MI.getOperand(ScratchIdx).getReg();
1065  if (X86II::isX86_64ExtendedReg(ScratchReg))
1066  EncodedBytes = 13;
1067  else
1068  EncodedBytes = 12;
1069 
1070  EmitAndCountInstruction(
1071  MCInstBuilder(X86::MOV64ri).addReg(ScratchReg).addOperand(CalleeMCOp));
1072  // FIXME: Add retpoline support and remove this.
1073  if (Subtarget->useRetpolineIndirectCalls())
1075  "Lowering patchpoint with retpoline not yet implemented.");
1076  EmitAndCountInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg));
1077  }
1078 
1079  // Emit padding.
1080  unsigned NumBytes = opers.getNumPatchBytes();
1081  assert(NumBytes >= EncodedBytes &&
1082  "Patchpoint can't request size less than the length of a call.");
1083 
1084  EmitNops(*OutStreamer, NumBytes - EncodedBytes, Subtarget->is64Bit(),
1085  getSubtargetInfo());
1086 }
1087 
1088 void X86AsmPrinter::LowerPATCHABLE_EVENT_CALL(const MachineInstr &MI,
1089  X86MCInstLower &MCIL) {
1090  assert(Subtarget->is64Bit() && "XRay custom events only supports X86-64");
1091 
1092  // We want to emit the following pattern, which follows the x86 calling
1093  // convention to prepare for the trampoline call to be patched in.
1094  //
1095  // .p2align 1, ...
1096  // .Lxray_event_sled_N:
1097  // jmp +N // jump across the instrumentation sled
1098  // ... // set up arguments in register
1099  // callq __xray_CustomEvent@plt // force dependency to symbol
1100  // ...
1101  // <jump here>
1102  //
1103  // After patching, it would look something like:
1104  //
1105  // nopw (2-byte nop)
1106  // ...
1107  // callq __xrayCustomEvent // already lowered
1108  // ...
1109  //
1110  // ---
1111  // First we emit the label and the jump.
1112  auto CurSled = OutContext.createTempSymbol("xray_event_sled_", true);
1113  OutStreamer->AddComment("# XRay Custom Event Log");
1114  OutStreamer->EmitCodeAlignment(2);
1115  OutStreamer->EmitLabel(CurSled);
1116 
1117  // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as
1118  // an operand (computed as an offset from the jmp instruction).
1119  // FIXME: Find another less hacky way do force the relative jump.
1120  OutStreamer->EmitBinaryData("\xeb\x0f");
1121 
1122  // The default C calling convention will place two arguments into %rcx and
1123  // %rdx -- so we only work with those.
1124  unsigned DestRegs[] = {X86::RDI, X86::RSI};
1125  bool UsedMask[] = {false, false};
1126  // Filled out in loop.
1127  unsigned SrcRegs[] = {0, 0};
1128 
1129  // Then we put the operands in the %rdi and %rsi registers. We spill the
1130  // values in the register before we clobber them, and mark them as used in
1131  // UsedMask. In case the arguments are already in the correct register, we use
1132  // emit nops appropriately sized to keep the sled the same size in every
1133  // situation.
1134  for (unsigned I = 0; I < MI.getNumOperands(); ++I)
1135  if (auto Op = MCIL.LowerMachineOperand(&MI, MI.getOperand(I))) {
1136  assert(Op->isReg() && "Only support arguments in registers");
1137  SrcRegs[I] = Op->getReg();
1138  if (SrcRegs[I] != DestRegs[I]) {
1139  UsedMask[I] = true;
1140  EmitAndCountInstruction(
1141  MCInstBuilder(X86::PUSH64r).addReg(DestRegs[I]));
1142  } else {
1143  EmitNops(*OutStreamer, 4, Subtarget->is64Bit(), getSubtargetInfo());
1144  }
1145  }
1146 
1147  // Now that the register values are stashed, mov arguments into place.
1148  for (unsigned I = 0; I < MI.getNumOperands(); ++I)
1149  if (SrcRegs[I] != DestRegs[I])
1150  EmitAndCountInstruction(
1151  MCInstBuilder(X86::MOV64rr).addReg(DestRegs[I]).addReg(SrcRegs[I]));
1152 
1153  // We emit a hard dependency on the __xray_CustomEvent symbol, which is the
1154  // name of the trampoline to be implemented by the XRay runtime.
1155  auto TSym = OutContext.getOrCreateSymbol("__xray_CustomEvent");
1157  if (isPositionIndependent())
1159 
1160  // Emit the call instruction.
1161  EmitAndCountInstruction(MCInstBuilder(X86::CALL64pcrel32)
1162  .addOperand(MCIL.LowerSymbolOperand(TOp, TSym)));
1163 
1164  // Restore caller-saved and used registers.
1165  for (unsigned I = sizeof UsedMask; I-- > 0;)
1166  if (UsedMask[I])
1167  EmitAndCountInstruction(MCInstBuilder(X86::POP64r).addReg(DestRegs[I]));
1168  else
1169  EmitNops(*OutStreamer, 1, Subtarget->is64Bit(), getSubtargetInfo());
1170 
1171  OutStreamer->AddComment("xray custom event end.");
1172 
1173  // Record the sled version. Older versions of this sled were spelled
1174  // differently, so we let the runtime handle the different offsets we're
1175  // using.
1176  recordSled(CurSled, MI, SledKind::CUSTOM_EVENT, 1);
1177 }
1178 
1179 void X86AsmPrinter::LowerPATCHABLE_TYPED_EVENT_CALL(const MachineInstr &MI,
1180  X86MCInstLower &MCIL) {
1181  assert(Subtarget->is64Bit() && "XRay typed events only supports X86-64");
1182 
1183  // We want to emit the following pattern, which follows the x86 calling
1184  // convention to prepare for the trampoline call to be patched in.
1185  //
1186  // .p2align 1, ...
1187  // .Lxray_event_sled_N:
1188  // jmp +N // jump across the instrumentation sled
1189  // ... // set up arguments in register
1190  // callq __xray_TypedEvent@plt // force dependency to symbol
1191  // ...
1192  // <jump here>
1193  //
1194  // After patching, it would look something like:
1195  //
1196  // nopw (2-byte nop)
1197  // ...
1198  // callq __xrayTypedEvent // already lowered
1199  // ...
1200  //
1201  // ---
1202  // First we emit the label and the jump.
1203  auto CurSled = OutContext.createTempSymbol("xray_typed_event_sled_", true);
1204  OutStreamer->AddComment("# XRay Typed Event Log");
1205  OutStreamer->EmitCodeAlignment(2);
1206  OutStreamer->EmitLabel(CurSled);
1207 
1208  // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as
1209  // an operand (computed as an offset from the jmp instruction).
1210  // FIXME: Find another less hacky way do force the relative jump.
1211  OutStreamer->EmitBinaryData("\xeb\x14");
1212 
1213  // An x86-64 convention may place three arguments into %rcx, %rdx, and R8,
1214  // so we'll work with those. Or we may be called via SystemV, in which case
1215  // we don't have to do any translation.
1216  unsigned DestRegs[] = {X86::RDI, X86::RSI, X86::RDX};
1217  bool UsedMask[] = {false, false, false};
1218 
1219  // Will fill out src regs in the loop.
1220  unsigned SrcRegs[] = {0, 0, 0};
1221 
1222  // Then we put the operands in the SystemV registers. We spill the values in
1223  // the registers before we clobber them, and mark them as used in UsedMask.
1224  // In case the arguments are already in the correct register, we emit nops
1225  // appropriately sized to keep the sled the same size in every situation.
1226  for (unsigned I = 0; I < MI.getNumOperands(); ++I)
1227  if (auto Op = MCIL.LowerMachineOperand(&MI, MI.getOperand(I))) {
1228  // TODO: Is register only support adequate?
1229  assert(Op->isReg() && "Only supports arguments in registers");
1230  SrcRegs[I] = Op->getReg();
1231  if (SrcRegs[I] != DestRegs[I]) {
1232  UsedMask[I] = true;
1233  EmitAndCountInstruction(
1234  MCInstBuilder(X86::PUSH64r).addReg(DestRegs[I]));
1235  } else {
1236  EmitNops(*OutStreamer, 4, Subtarget->is64Bit(), getSubtargetInfo());
1237  }
1238  }
1239 
1240  // In the above loop we only stash all of the destination registers or emit
1241  // nops if the arguments are already in the right place. Doing the actually
1242  // moving is postponed until after all the registers are stashed so nothing
1243  // is clobbers. We've already added nops to account for the size of mov and
1244  // push if the register is in the right place, so we only have to worry about
1245  // emitting movs.
1246  for (unsigned I = 0; I < MI.getNumOperands(); ++I)
1247  if (UsedMask[I])
1248  EmitAndCountInstruction(
1249  MCInstBuilder(X86::MOV64rr).addReg(DestRegs[I]).addReg(SrcRegs[I]));
1250 
1251  // We emit a hard dependency on the __xray_TypedEvent symbol, which is the
1252  // name of the trampoline to be implemented by the XRay runtime.
1253  auto TSym = OutContext.getOrCreateSymbol("__xray_TypedEvent");
1255  if (isPositionIndependent())
1257 
1258  // Emit the call instruction.
1259  EmitAndCountInstruction(MCInstBuilder(X86::CALL64pcrel32)
1260  .addOperand(MCIL.LowerSymbolOperand(TOp, TSym)));
1261 
1262  // Restore caller-saved and used registers.
1263  for (unsigned I = sizeof UsedMask; I-- > 0;)
1264  if (UsedMask[I])
1265  EmitAndCountInstruction(MCInstBuilder(X86::POP64r).addReg(DestRegs[I]));
1266  else
1267  EmitNops(*OutStreamer, 1, Subtarget->is64Bit(), getSubtargetInfo());
1268 
1269  OutStreamer->AddComment("xray typed event end.");
1270 
1271  // Record the sled version.
1272  recordSled(CurSled, MI, SledKind::TYPED_EVENT, 0);
1273 }
1274 
1275 void X86AsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI,
1276  X86MCInstLower &MCIL) {
1277  // We want to emit the following pattern:
1278  //
1279  // .p2align 1, ...
1280  // .Lxray_sled_N:
1281  // jmp .tmpN
1282  // # 9 bytes worth of noops
1283  //
1284  // We need the 9 bytes because at runtime, we'd be patching over the full 11
1285  // bytes with the following pattern:
1286  //
1287  // mov %r10, <function id, 32-bit> // 6 bytes
1288  // call <relative offset, 32-bits> // 5 bytes
1289  //
1290  auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
1291  OutStreamer->EmitCodeAlignment(2);
1292  OutStreamer->EmitLabel(CurSled);
1293 
1294  // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as
1295  // an operand (computed as an offset from the jmp instruction).
1296  // FIXME: Find another less hacky way do force the relative jump.
1297  OutStreamer->EmitBytes("\xeb\x09");
1298  EmitNops(*OutStreamer, 9, Subtarget->is64Bit(), getSubtargetInfo());
1299  recordSled(CurSled, MI, SledKind::FUNCTION_ENTER);
1300 }
1301 
1302 void X86AsmPrinter::LowerPATCHABLE_RET(const MachineInstr &MI,
1303  X86MCInstLower &MCIL) {
1304  // Since PATCHABLE_RET takes the opcode of the return statement as an
1305  // argument, we use that to emit the correct form of the RET that we want.
1306  // i.e. when we see this:
1307  //
1308  // PATCHABLE_RET X86::RET ...
1309  //
1310  // We should emit the RET followed by sleds.
1311  //
1312  // .p2align 1, ...
1313  // .Lxray_sled_N:
1314  // ret # or equivalent instruction
1315  // # 10 bytes worth of noops
1316  //
1317  // This just makes sure that the alignment for the next instruction is 2.
1318  auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
1319  OutStreamer->EmitCodeAlignment(2);
1320  OutStreamer->EmitLabel(CurSled);
1321  unsigned OpCode = MI.getOperand(0).getImm();
1322  MCInst Ret;
1323  Ret.setOpcode(OpCode);
1324  for (auto &MO : make_range(MI.operands_begin() + 1, MI.operands_end()))
1325  if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO))
1326  Ret.addOperand(MaybeOperand.getValue());
1327  OutStreamer->EmitInstruction(Ret, getSubtargetInfo());
1328  EmitNops(*OutStreamer, 10, Subtarget->is64Bit(), getSubtargetInfo());
1329  recordSled(CurSled, MI, SledKind::FUNCTION_EXIT);
1330 }
1331 
1332 void X86AsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI,
1333  X86MCInstLower &MCIL) {
1334  // Like PATCHABLE_RET, we have the actual instruction in the operands to this
1335  // instruction so we lower that particular instruction and its operands.
1336  // Unlike PATCHABLE_RET though, we put the sled before the JMP, much like how
1337  // we do it for PATCHABLE_FUNCTION_ENTER. The sled should be very similar to
1338  // the PATCHABLE_FUNCTION_ENTER case, followed by the lowering of the actual
1339  // tail call much like how we have it in PATCHABLE_RET.
1340  auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
1341  OutStreamer->EmitCodeAlignment(2);
1342  OutStreamer->EmitLabel(CurSled);
1344 
1345  // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as
1346  // an operand (computed as an offset from the jmp instruction).
1347  // FIXME: Find another less hacky way do force the relative jump.
1348  OutStreamer->EmitBytes("\xeb\x09");
1349  EmitNops(*OutStreamer, 9, Subtarget->is64Bit(), getSubtargetInfo());
1350  OutStreamer->EmitLabel(Target);
1351  recordSled(CurSled, MI, SledKind::TAIL_CALL);
1352 
1353  unsigned OpCode = MI.getOperand(0).getImm();
1354  MCInst TC;
1355  TC.setOpcode(OpCode);
1356 
1357  // Before emitting the instruction, add a comment to indicate that this is
1358  // indeed a tail call.
1359  OutStreamer->AddComment("TAILCALL");
1360  for (auto &MO : make_range(MI.operands_begin() + 1, MI.operands_end()))
1361  if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO))
1362  TC.addOperand(MaybeOperand.getValue());
1363  OutStreamer->EmitInstruction(TC, getSubtargetInfo());
1364 }
1365 
1366 // Returns instruction preceding MBBI in MachineFunction.
1367 // If MBBI is the first instruction of the first basic block, returns null.
1370  const MachineBasicBlock *MBB = MBBI->getParent();
1371  while (MBBI == MBB->begin()) {
1372  if (MBB == &MBB->getParent()->front())
1374  MBB = MBB->getPrevNode();
1375  MBBI = MBB->end();
1376  }
1377  return --MBBI;
1378 }
1379 
1381  const MachineOperand &Op) {
1382  if (!Op.isCPI())
1383  return nullptr;
1384 
1387  const MachineConstantPoolEntry &ConstantEntry = Constants[Op.getIndex()];
1388 
1389  // Bail if this is a machine constant pool entry, we won't be able to dig out
1390  // anything useful.
1391  if (ConstantEntry.isMachineConstantPoolEntry())
1392  return nullptr;
1393 
1394  auto *C = dyn_cast<Constant>(ConstantEntry.Val.ConstVal);
1395  assert((!C || ConstantEntry.getType() == C->getType()) &&
1396  "Expected a constant of the same type!");
1397  return C;
1398 }
1399 
1400 static std::string getShuffleComment(const MachineInstr *MI, unsigned SrcOp1Idx,
1401  unsigned SrcOp2Idx, ArrayRef<int> Mask) {
1402  std::string Comment;
1403 
1404  // Compute the name for a register. This is really goofy because we have
1405  // multiple instruction printers that could (in theory) use different
1406  // names. Fortunately most people use the ATT style (outside of Windows)
1407  // and they actually agree on register naming here. Ultimately, this is
1408  // a comment, and so its OK if it isn't perfect.
1409  auto GetRegisterName = [](unsigned RegNum) -> StringRef {
1410  return X86ATTInstPrinter::getRegisterName(RegNum);
1411  };
1412 
1413  const MachineOperand &DstOp = MI->getOperand(0);
1414  const MachineOperand &SrcOp1 = MI->getOperand(SrcOp1Idx);
1415  const MachineOperand &SrcOp2 = MI->getOperand(SrcOp2Idx);
1416 
1417  StringRef DstName = DstOp.isReg() ? GetRegisterName(DstOp.getReg()) : "mem";
1418  StringRef Src1Name =
1419  SrcOp1.isReg() ? GetRegisterName(SrcOp1.getReg()) : "mem";
1420  StringRef Src2Name =
1421  SrcOp2.isReg() ? GetRegisterName(SrcOp2.getReg()) : "mem";
1422 
1423  // One source operand, fix the mask to print all elements in one span.
1424  SmallVector<int, 8> ShuffleMask(Mask.begin(), Mask.end());
1425  if (Src1Name == Src2Name)
1426  for (int i = 0, e = ShuffleMask.size(); i != e; ++i)
1427  if (ShuffleMask[i] >= e)
1428  ShuffleMask[i] -= e;
1429 
1430  raw_string_ostream CS(Comment);
1431  CS << DstName;
1432 
1433  // Handle AVX512 MASK/MASXZ write mask comments.
1434  // MASK: zmmX {%kY}
1435  // MASKZ: zmmX {%kY} {z}
1436  if (SrcOp1Idx > 1) {
1437  assert((SrcOp1Idx == 2 || SrcOp1Idx == 3) && "Unexpected writemask");
1438 
1439  const MachineOperand &WriteMaskOp = MI->getOperand(SrcOp1Idx - 1);
1440  if (WriteMaskOp.isReg()) {
1441  CS << " {%" << GetRegisterName(WriteMaskOp.getReg()) << "}";
1442 
1443  if (SrcOp1Idx == 2) {
1444  CS << " {z}";
1445  }
1446  }
1447  }
1448 
1449  CS << " = ";
1450 
1451  for (int i = 0, e = ShuffleMask.size(); i != e; ++i) {
1452  if (i != 0)
1453  CS << ",";
1454  if (ShuffleMask[i] == SM_SentinelZero) {
1455  CS << "zero";
1456  continue;
1457  }
1458 
1459  // Otherwise, it must come from src1 or src2. Print the span of elements
1460  // that comes from this src.
1461  bool isSrc1 = ShuffleMask[i] < (int)e;
1462  CS << (isSrc1 ? Src1Name : Src2Name) << '[';
1463 
1464  bool IsFirst = true;
1465  while (i != e && ShuffleMask[i] != SM_SentinelZero &&
1466  (ShuffleMask[i] < (int)e) == isSrc1) {
1467  if (!IsFirst)
1468  CS << ',';
1469  else
1470  IsFirst = false;
1471  if (ShuffleMask[i] == SM_SentinelUndef)
1472  CS << "u";
1473  else
1474  CS << ShuffleMask[i] % (int)e;
1475  ++i;
1476  }
1477  CS << ']';
1478  --i; // For loop increments element #.
1479  }
1480  CS.flush();
1481 
1482  return Comment;
1483 }
1484 
1485 static void printConstant(const APInt &Val, raw_ostream &CS) {
1486  if (Val.getBitWidth() <= 64) {
1487  CS << Val.getZExtValue();
1488  } else {
1489  // print multi-word constant as (w0,w1)
1490  CS << "(";
1491  for (int i = 0, N = Val.getNumWords(); i < N; ++i) {
1492  if (i > 0)
1493  CS << ",";
1494  CS << Val.getRawData()[i];
1495  }
1496  CS << ")";
1497  }
1498 }
1499 
1500 static void printConstant(const APFloat &Flt, raw_ostream &CS) {
1501  SmallString<32> Str;
1502  Flt.toString(Str);
1503  CS << Str;
1504 }
1505 
1506 static void printConstant(const Constant *COp, raw_ostream &CS) {
1507  if (isa<UndefValue>(COp)) {
1508  CS << "u";
1509  } else if (auto *CI = dyn_cast<ConstantInt>(COp)) {
1510  printConstant(CI->getValue(), CS);
1511  } else if (auto *CF = dyn_cast<ConstantFP>(COp)) {
1512  printConstant(CF->getValueAPF(), CS);
1513  } else {
1514  CS << "?";
1515  }
1516 }
1517 
1518 void X86AsmPrinter::EmitSEHInstruction(const MachineInstr *MI) {
1519  assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?");
1520  assert(getSubtarget().isOSWindows() && "SEH_ instruction Windows only");
1521  const X86RegisterInfo *RI =
1522  MF->getSubtarget<X86Subtarget>().getRegisterInfo();
1523 
1524  // Use the .cv_fpo directives if we're emitting CodeView on 32-bit x86.
1525  if (EmitFPOData) {
1526  X86TargetStreamer *XTS =
1527  static_cast<X86TargetStreamer *>(OutStreamer->getTargetStreamer());
1528  switch (MI->getOpcode()) {
1529  case X86::SEH_PushReg:
1530  XTS->emitFPOPushReg(MI->getOperand(0).getImm());
1531  break;
1532  case X86::SEH_StackAlloc:
1533  XTS->emitFPOStackAlloc(MI->getOperand(0).getImm());
1534  break;
1535  case X86::SEH_StackAlign:
1536  XTS->emitFPOStackAlign(MI->getOperand(0).getImm());
1537  break;
1538  case X86::SEH_SetFrame:
1539  assert(MI->getOperand(1).getImm() == 0 &&
1540  ".cv_fpo_setframe takes no offset");
1541  XTS->emitFPOSetFrame(MI->getOperand(0).getImm());
1542  break;
1543  case X86::SEH_EndPrologue:
1544  XTS->emitFPOEndPrologue();
1545  break;
1546  case X86::SEH_SaveReg:
1547  case X86::SEH_SaveXMM:
1548  case X86::SEH_PushFrame:
1549  llvm_unreachable("SEH_ directive incompatible with FPO");
1550  break;
1551  default:
1552  llvm_unreachable("expected SEH_ instruction");
1553  }
1554  return;
1555  }
1556 
1557  // Otherwise, use the .seh_ directives for all other Windows platforms.
1558  switch (MI->getOpcode()) {
1559  case X86::SEH_PushReg:
1560  OutStreamer->EmitWinCFIPushReg(
1561  RI->getSEHRegNum(MI->getOperand(0).getImm()));
1562  break;
1563 
1564  case X86::SEH_SaveReg:
1565  OutStreamer->EmitWinCFISaveReg(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1566  MI->getOperand(1).getImm());
1567  break;
1568 
1569  case X86::SEH_SaveXMM:
1570  OutStreamer->EmitWinCFISaveXMM(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1571  MI->getOperand(1).getImm());
1572  break;
1573 
1574  case X86::SEH_StackAlloc:
1575  OutStreamer->EmitWinCFIAllocStack(MI->getOperand(0).getImm());
1576  break;
1577 
1578  case X86::SEH_SetFrame:
1579  OutStreamer->EmitWinCFISetFrame(
1580  RI->getSEHRegNum(MI->getOperand(0).getImm()),
1581  MI->getOperand(1).getImm());
1582  break;
1583 
1584  case X86::SEH_PushFrame:
1585  OutStreamer->EmitWinCFIPushFrame(MI->getOperand(0).getImm());
1586  break;
1587 
1588  case X86::SEH_EndPrologue:
1589  OutStreamer->EmitWinCFIEndProlog();
1590  break;
1591 
1592  default:
1593  llvm_unreachable("expected SEH_ instruction");
1594  }
1595 }
1596 
1598  X86MCInstLower MCInstLowering(*MF, *this);
1599  const X86RegisterInfo *RI =
1600  MF->getSubtarget<X86Subtarget>().getRegisterInfo();
1601 
1602  // Add a comment about EVEX-2-VEX compression for AVX-512 instrs that
1603  // are compressed from EVEX encoding to VEX encoding.
1606  OutStreamer->AddComment("EVEX TO VEX Compression ", false);
1607  }
1608 
1609  switch (MI->getOpcode()) {
1610  case TargetOpcode::DBG_VALUE:
1611  llvm_unreachable("Should be handled target independently");
1612 
1613  // Emit nothing here but a comment if we can.
1614  case X86::Int_MemBarrier:
1615  OutStreamer->emitRawComment("MEMBARRIER");
1616  return;
1617 
1618  case X86::EH_RETURN:
1619  case X86::EH_RETURN64: {
1620  // Lower these as normal, but add some comments.
1621  unsigned Reg = MI->getOperand(0).getReg();
1622  OutStreamer->AddComment(StringRef("eh_return, addr: %") +
1624  break;
1625  }
1626  case X86::CLEANUPRET: {
1627  // Lower these as normal, but add some comments.
1628  OutStreamer->AddComment("CLEANUPRET");
1629  break;
1630  }
1631 
1632  case X86::CATCHRET: {
1633  // Lower these as normal, but add some comments.
1634  OutStreamer->AddComment("CATCHRET");
1635  break;
1636  }
1637 
1638  case X86::TAILJMPr:
1639  case X86::TAILJMPm:
1640  case X86::TAILJMPd:
1641  case X86::TAILJMPd_CC:
1642  case X86::TAILJMPr64:
1643  case X86::TAILJMPm64:
1644  case X86::TAILJMPd64:
1645  case X86::TAILJMPd64_CC:
1646  case X86::TAILJMPr64_REX:
1647  case X86::TAILJMPm64_REX:
1648  // Lower these as normal, but add some comments.
1649  OutStreamer->AddComment("TAILCALL");
1650  break;
1651 
1652  case X86::TLS_addr32:
1653  case X86::TLS_addr64:
1654  case X86::TLS_base_addr32:
1655  case X86::TLS_base_addr64:
1656  return LowerTlsAddr(MCInstLowering, *MI);
1657 
1658  case X86::MOVPC32r: {
1659  // This is a pseudo op for a two instruction sequence with a label, which
1660  // looks like:
1661  // call "L1$pb"
1662  // "L1$pb":
1663  // popl %esi
1664 
1665  // Emit the call.
1666  MCSymbol *PICBase = MF->getPICBaseSymbol();
1667  // FIXME: We would like an efficient form for this, so we don't have to do a
1668  // lot of extra uniquing.
1669  EmitAndCountInstruction(
1670  MCInstBuilder(X86::CALLpcrel32)
1671  .addExpr(MCSymbolRefExpr::create(PICBase, OutContext)));
1672 
1673  const X86FrameLowering *FrameLowering =
1674  MF->getSubtarget<X86Subtarget>().getFrameLowering();
1675  bool hasFP = FrameLowering->hasFP(*MF);
1676 
1677  // TODO: This is needed only if we require precise CFA.
1678  bool HasActiveDwarfFrame = OutStreamer->getNumFrameInfos() &&
1679  !OutStreamer->getDwarfFrameInfos().back().End;
1680 
1681  int stackGrowth = -RI->getSlotSize();
1682 
1683  if (HasActiveDwarfFrame && !hasFP) {
1684  OutStreamer->EmitCFIAdjustCfaOffset(-stackGrowth);
1685  }
1686 
1687  // Emit the label.
1688  OutStreamer->EmitLabel(PICBase);
1689 
1690  // popl $reg
1691  EmitAndCountInstruction(
1692  MCInstBuilder(X86::POP32r).addReg(MI->getOperand(0).getReg()));
1693 
1694  if (HasActiveDwarfFrame && !hasFP) {
1695  OutStreamer->EmitCFIAdjustCfaOffset(stackGrowth);
1696  }
1697  return;
1698  }
1699 
1700  case X86::MOVGOT64r: {
1701  // Materializes the GOT for the 64-bit large code model.
1702  MCSymbol *DotSym = OutContext.createTempSymbol();
1703  OutStreamer->EmitLabel(DotSym);
1704 
1705  unsigned DstReg = MI->getOperand(0).getReg();
1706  unsigned ScratchReg = MI->getOperand(1).getReg();
1707  MCSymbol *GOTSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
1708 
1709  // .LtmpN: leaq .LtmpN(%rip), %dst
1710  const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext);
1711  EmitAndCountInstruction(MCInstBuilder(X86::LEA64r)
1712  .addReg(DstReg) // dest
1713  .addReg(X86::RIP) // base
1714  .addImm(1) // scale
1715  .addReg(0) // index
1716  .addExpr(DotExpr) // disp
1717  .addReg(0)); // seg
1718 
1719  // movq $_GLOBAL_OFFSET_TABLE_ - .LtmpN, %scratch
1720  const MCExpr *GOTSymExpr = MCSymbolRefExpr::create(GOTSym, OutContext);
1721  const MCExpr *GOTDiffExpr =
1722  MCBinaryExpr::createSub(GOTSymExpr, DotExpr, OutContext);
1723  EmitAndCountInstruction(MCInstBuilder(X86::MOV64ri)
1724  .addReg(ScratchReg) // dest
1725  .addExpr(GOTDiffExpr)); // disp
1726 
1727  // addq %scratch, %dst
1728  EmitAndCountInstruction(MCInstBuilder(X86::ADD64rr)
1729  .addReg(DstReg) // dest
1730  .addReg(DstReg) // dest
1731  .addReg(ScratchReg)); // src
1732  return;
1733  }
1734 
1735  case X86::ADD32ri: {
1736  // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
1738  break;
1739 
1740  // Okay, we have something like:
1741  // EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
1742 
1743  // For this, we want to print something like:
1744  // MYGLOBAL + (. - PICBASE)
1745  // However, we can't generate a ".", so just emit a new label here and refer
1746  // to it.
1747  MCSymbol *DotSym = OutContext.createTempSymbol();
1748  OutStreamer->EmitLabel(DotSym);
1749 
1750  // Now that we have emitted the label, lower the complex operand expression.
1751  MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
1752 
1753  const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext);
1754  const MCExpr *PICBase =
1756  DotExpr = MCBinaryExpr::createSub(DotExpr, PICBase, OutContext);
1757 
1758  DotExpr = MCBinaryExpr::createAdd(
1759  MCSymbolRefExpr::create(OpSym, OutContext), DotExpr, OutContext);
1760 
1761  EmitAndCountInstruction(MCInstBuilder(X86::ADD32ri)
1762  .addReg(MI->getOperand(0).getReg())
1763  .addReg(MI->getOperand(1).getReg())
1764  .addExpr(DotExpr));
1765  return;
1766  }
1767  case TargetOpcode::STATEPOINT:
1768  return LowerSTATEPOINT(*MI, MCInstLowering);
1769 
1770  case TargetOpcode::FAULTING_OP:
1771  return LowerFAULTING_OP(*MI, MCInstLowering);
1772 
1773  case TargetOpcode::FENTRY_CALL:
1774  return LowerFENTRY_CALL(*MI, MCInstLowering);
1775 
1776  case TargetOpcode::PATCHABLE_OP:
1777  return LowerPATCHABLE_OP(*MI, MCInstLowering);
1778 
1779  case TargetOpcode::STACKMAP:
1780  return LowerSTACKMAP(*MI);
1781 
1782  case TargetOpcode::PATCHPOINT:
1783  return LowerPATCHPOINT(*MI, MCInstLowering);
1784 
1785  case TargetOpcode::PATCHABLE_FUNCTION_ENTER:
1786  return LowerPATCHABLE_FUNCTION_ENTER(*MI, MCInstLowering);
1787 
1788  case TargetOpcode::PATCHABLE_RET:
1789  return LowerPATCHABLE_RET(*MI, MCInstLowering);
1790 
1791  case TargetOpcode::PATCHABLE_TAIL_CALL:
1792  return LowerPATCHABLE_TAIL_CALL(*MI, MCInstLowering);
1793 
1794  case TargetOpcode::PATCHABLE_EVENT_CALL:
1795  return LowerPATCHABLE_EVENT_CALL(*MI, MCInstLowering);
1796 
1797  case TargetOpcode::PATCHABLE_TYPED_EVENT_CALL:
1798  return LowerPATCHABLE_TYPED_EVENT_CALL(*MI, MCInstLowering);
1799 
1800  case X86::MORESTACK_RET:
1801  EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
1802  return;
1803 
1804  case X86::MORESTACK_RET_RESTORE_R10:
1805  // Return, then restore R10.
1806  EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
1807  EmitAndCountInstruction(
1808  MCInstBuilder(X86::MOV64rr).addReg(X86::R10).addReg(X86::RAX));
1809  return;
1810 
1811  case X86::SEH_PushReg:
1812  case X86::SEH_SaveReg:
1813  case X86::SEH_SaveXMM:
1814  case X86::SEH_StackAlloc:
1815  case X86::SEH_StackAlign:
1816  case X86::SEH_SetFrame:
1817  case X86::SEH_PushFrame:
1818  case X86::SEH_EndPrologue:
1819  EmitSEHInstruction(MI);
1820  return;
1821 
1822  case X86::SEH_Epilogue: {
1823  assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?");
1825  // Check if preceded by a call and emit nop if so.
1826  for (MBBI = PrevCrossBBInst(MBBI);
1828  MBBI = PrevCrossBBInst(MBBI)) {
1829  // Conservatively assume that pseudo instructions don't emit code and keep
1830  // looking for a call. We may emit an unnecessary nop in some cases.
1831  if (!MBBI->isPseudo()) {
1832  if (MBBI->isCall())
1833  EmitAndCountInstruction(MCInstBuilder(X86::NOOP));
1834  break;
1835  }
1836  }
1837  return;
1838  }
1839 
1840  // Lower PSHUFB and VPERMILP normally but add a comment if we can find
1841  // a constant shuffle mask. We won't be able to do this at the MC layer
1842  // because the mask isn't an immediate.
1843  case X86::PSHUFBrm:
1844  case X86::VPSHUFBrm:
1845  case X86::VPSHUFBYrm:
1846  case X86::VPSHUFBZ128rm:
1847  case X86::VPSHUFBZ128rmk:
1848  case X86::VPSHUFBZ128rmkz:
1849  case X86::VPSHUFBZ256rm:
1850  case X86::VPSHUFBZ256rmk:
1851  case X86::VPSHUFBZ256rmkz:
1852  case X86::VPSHUFBZrm:
1853  case X86::VPSHUFBZrmk:
1854  case X86::VPSHUFBZrmkz: {
1855  if (!OutStreamer->isVerboseAsm())
1856  break;
1857  unsigned SrcIdx, MaskIdx;
1858  switch (MI->getOpcode()) {
1859  default: llvm_unreachable("Invalid opcode");
1860  case X86::PSHUFBrm:
1861  case X86::VPSHUFBrm:
1862  case X86::VPSHUFBYrm:
1863  case X86::VPSHUFBZ128rm:
1864  case X86::VPSHUFBZ256rm:
1865  case X86::VPSHUFBZrm:
1866  SrcIdx = 1; MaskIdx = 5; break;
1867  case X86::VPSHUFBZ128rmkz:
1868  case X86::VPSHUFBZ256rmkz:
1869  case X86::VPSHUFBZrmkz:
1870  SrcIdx = 2; MaskIdx = 6; break;
1871  case X86::VPSHUFBZ128rmk:
1872  case X86::VPSHUFBZ256rmk:
1873  case X86::VPSHUFBZrmk:
1874  SrcIdx = 3; MaskIdx = 7; break;
1875  }
1876 
1877  assert(MI->getNumOperands() >= 6 &&
1878  "We should always have at least 6 operands!");
1879 
1880  const MachineOperand &MaskOp = MI->getOperand(MaskIdx);
1881  if (auto *C = getConstantFromPool(*MI, MaskOp)) {
1883  DecodePSHUFBMask(C, Mask);
1884  if (!Mask.empty())
1885  OutStreamer->AddComment(getShuffleComment(MI, SrcIdx, SrcIdx, Mask),
1887  }
1888  break;
1889  }
1890 
1891  case X86::VPERMILPSrm:
1892  case X86::VPERMILPSYrm:
1893  case X86::VPERMILPSZ128rm:
1894  case X86::VPERMILPSZ128rmk:
1895  case X86::VPERMILPSZ128rmkz:
1896  case X86::VPERMILPSZ256rm:
1897  case X86::VPERMILPSZ256rmk:
1898  case X86::VPERMILPSZ256rmkz:
1899  case X86::VPERMILPSZrm:
1900  case X86::VPERMILPSZrmk:
1901  case X86::VPERMILPSZrmkz:
1902  case X86::VPERMILPDrm:
1903  case X86::VPERMILPDYrm:
1904  case X86::VPERMILPDZ128rm:
1905  case X86::VPERMILPDZ128rmk:
1906  case X86::VPERMILPDZ128rmkz:
1907  case X86::VPERMILPDZ256rm:
1908  case X86::VPERMILPDZ256rmk:
1909  case X86::VPERMILPDZ256rmkz:
1910  case X86::VPERMILPDZrm:
1911  case X86::VPERMILPDZrmk:
1912  case X86::VPERMILPDZrmkz: {
1913  if (!OutStreamer->isVerboseAsm())
1914  break;
1915  unsigned SrcIdx, MaskIdx;
1916  unsigned ElSize;
1917  switch (MI->getOpcode()) {
1918  default: llvm_unreachable("Invalid opcode");
1919  case X86::VPERMILPSrm:
1920  case X86::VPERMILPSYrm:
1921  case X86::VPERMILPSZ128rm:
1922  case X86::VPERMILPSZ256rm:
1923  case X86::VPERMILPSZrm:
1924  SrcIdx = 1; MaskIdx = 5; ElSize = 32; break;
1925  case X86::VPERMILPSZ128rmkz:
1926  case X86::VPERMILPSZ256rmkz:
1927  case X86::VPERMILPSZrmkz:
1928  SrcIdx = 2; MaskIdx = 6; ElSize = 32; break;
1929  case X86::VPERMILPSZ128rmk:
1930  case X86::VPERMILPSZ256rmk:
1931  case X86::VPERMILPSZrmk:
1932  SrcIdx = 3; MaskIdx = 7; ElSize = 32; break;
1933  case X86::VPERMILPDrm:
1934  case X86::VPERMILPDYrm:
1935  case X86::VPERMILPDZ128rm:
1936  case X86::VPERMILPDZ256rm:
1937  case X86::VPERMILPDZrm:
1938  SrcIdx = 1; MaskIdx = 5; ElSize = 64; break;
1939  case X86::VPERMILPDZ128rmkz:
1940  case X86::VPERMILPDZ256rmkz:
1941  case X86::VPERMILPDZrmkz:
1942  SrcIdx = 2; MaskIdx = 6; ElSize = 64; break;
1943  case X86::VPERMILPDZ128rmk:
1944  case X86::VPERMILPDZ256rmk:
1945  case X86::VPERMILPDZrmk:
1946  SrcIdx = 3; MaskIdx = 7; ElSize = 64; break;
1947  }
1948 
1949  assert(MI->getNumOperands() >= 6 &&
1950  "We should always have at least 6 operands!");
1951 
1952  const MachineOperand &MaskOp = MI->getOperand(MaskIdx);
1953  if (auto *C = getConstantFromPool(*MI, MaskOp)) {
1955  DecodeVPERMILPMask(C, ElSize, Mask);
1956  if (!Mask.empty())
1957  OutStreamer->AddComment(getShuffleComment(MI, SrcIdx, SrcIdx, Mask),
1959  }
1960  break;
1961  }
1962 
1963  case X86::VPERMIL2PDrm:
1964  case X86::VPERMIL2PSrm:
1965  case X86::VPERMIL2PDYrm:
1966  case X86::VPERMIL2PSYrm: {
1967  if (!OutStreamer->isVerboseAsm())
1968  break;
1969  assert(MI->getNumOperands() >= 8 &&
1970  "We should always have at least 8 operands!");
1971 
1972  const MachineOperand &CtrlOp = MI->getOperand(MI->getNumOperands() - 1);
1973  if (!CtrlOp.isImm())
1974  break;
1975 
1976  unsigned ElSize;
1977  switch (MI->getOpcode()) {
1978  default: llvm_unreachable("Invalid opcode");
1979  case X86::VPERMIL2PSrm: case X86::VPERMIL2PSYrm: ElSize = 32; break;
1980  case X86::VPERMIL2PDrm: case X86::VPERMIL2PDYrm: ElSize = 64; break;
1981  }
1982 
1983  const MachineOperand &MaskOp = MI->getOperand(6);
1984  if (auto *C = getConstantFromPool(*MI, MaskOp)) {
1986  DecodeVPERMIL2PMask(C, (unsigned)CtrlOp.getImm(), ElSize, Mask);
1987  if (!Mask.empty())
1988  OutStreamer->AddComment(getShuffleComment(MI, 1, 2, Mask),
1990  }
1991  break;
1992  }
1993 
1994  case X86::VPPERMrrm: {
1995  if (!OutStreamer->isVerboseAsm())
1996  break;
1997  assert(MI->getNumOperands() >= 7 &&
1998  "We should always have at least 7 operands!");
1999 
2000  const MachineOperand &MaskOp = MI->getOperand(6);
2001  if (auto *C = getConstantFromPool(*MI, MaskOp)) {
2003  DecodeVPPERMMask(C, Mask);
2004  if (!Mask.empty())
2005  OutStreamer->AddComment(getShuffleComment(MI, 1, 2, Mask),
2007  }
2008  break;
2009  }
2010 
2011  case X86::MMX_MOVQ64rm: {
2012  if (!OutStreamer->isVerboseAsm())
2013  break;
2014  if (MI->getNumOperands() <= 4)
2015  break;
2016  if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) {
2017  std::string Comment;
2018  raw_string_ostream CS(Comment);
2019  const MachineOperand &DstOp = MI->getOperand(0);
2020  CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = ";
2021  if (auto *CF = dyn_cast<ConstantFP>(C)) {
2022  CS << "0x" << CF->getValueAPF().bitcastToAPInt().toString(16, false);
2023  OutStreamer->AddComment(CS.str(), !EnablePrintSchedInfo);
2024  }
2025  }
2026  break;
2027  }
2028 
2029 #define MOV_CASE(Prefix, Suffix) \
2030  case X86::Prefix##MOVAPD##Suffix##rm: \
2031  case X86::Prefix##MOVAPS##Suffix##rm: \
2032  case X86::Prefix##MOVUPD##Suffix##rm: \
2033  case X86::Prefix##MOVUPS##Suffix##rm: \
2034  case X86::Prefix##MOVDQA##Suffix##rm: \
2035  case X86::Prefix##MOVDQU##Suffix##rm:
2036 
2037 #define MOV_AVX512_CASE(Suffix) \
2038  case X86::VMOVDQA64##Suffix##rm: \
2039  case X86::VMOVDQA32##Suffix##rm: \
2040  case X86::VMOVDQU64##Suffix##rm: \
2041  case X86::VMOVDQU32##Suffix##rm: \
2042  case X86::VMOVDQU16##Suffix##rm: \
2043  case X86::VMOVDQU8##Suffix##rm: \
2044  case X86::VMOVAPS##Suffix##rm: \
2045  case X86::VMOVAPD##Suffix##rm: \
2046  case X86::VMOVUPS##Suffix##rm: \
2047  case X86::VMOVUPD##Suffix##rm:
2048 
2049 #define CASE_ALL_MOV_RM() \
2050  MOV_CASE(, ) /* SSE */ \
2051  MOV_CASE(V, ) /* AVX-128 */ \
2052  MOV_CASE(V, Y) /* AVX-256 */ \
2053  MOV_AVX512_CASE(Z) \
2054  MOV_AVX512_CASE(Z256) \
2055  MOV_AVX512_CASE(Z128)
2056 
2057  // For loads from a constant pool to a vector register, print the constant
2058  // loaded.
2059  CASE_ALL_MOV_RM()
2060  case X86::VBROADCASTF128:
2061  case X86::VBROADCASTI128:
2062  case X86::VBROADCASTF32X4Z256rm:
2063  case X86::VBROADCASTF32X4rm:
2064  case X86::VBROADCASTF32X8rm:
2065  case X86::VBROADCASTF64X2Z128rm:
2066  case X86::VBROADCASTF64X2rm:
2067  case X86::VBROADCASTF64X4rm:
2068  case X86::VBROADCASTI32X4Z256rm:
2069  case X86::VBROADCASTI32X4rm:
2070  case X86::VBROADCASTI32X8rm:
2071  case X86::VBROADCASTI64X2Z128rm:
2072  case X86::VBROADCASTI64X2rm:
2073  case X86::VBROADCASTI64X4rm:
2074  if (!OutStreamer->isVerboseAsm())
2075  break;
2076  if (MI->getNumOperands() <= 4)
2077  break;
2078  if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) {
2079  int NumLanes = 1;
2080  // Override NumLanes for the broadcast instructions.
2081  switch (MI->getOpcode()) {
2082  case X86::VBROADCASTF128: NumLanes = 2; break;
2083  case X86::VBROADCASTI128: NumLanes = 2; break;
2084  case X86::VBROADCASTF32X4Z256rm: NumLanes = 2; break;
2085  case X86::VBROADCASTF32X4rm: NumLanes = 4; break;
2086  case X86::VBROADCASTF32X8rm: NumLanes = 2; break;
2087  case X86::VBROADCASTF64X2Z128rm: NumLanes = 2; break;
2088  case X86::VBROADCASTF64X2rm: NumLanes = 4; break;
2089  case X86::VBROADCASTF64X4rm: NumLanes = 2; break;
2090  case X86::VBROADCASTI32X4Z256rm: NumLanes = 2; break;
2091  case X86::VBROADCASTI32X4rm: NumLanes = 4; break;
2092  case X86::VBROADCASTI32X8rm: NumLanes = 2; break;
2093  case X86::VBROADCASTI64X2Z128rm: NumLanes = 2; break;
2094  case X86::VBROADCASTI64X2rm: NumLanes = 4; break;
2095  case X86::VBROADCASTI64X4rm: NumLanes = 2; break;
2096  }
2097 
2098  std::string Comment;
2099  raw_string_ostream CS(Comment);
2100  const MachineOperand &DstOp = MI->getOperand(0);
2101  CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = ";
2102  if (auto *CDS = dyn_cast<ConstantDataSequential>(C)) {
2103  CS << "[";
2104  for (int l = 0; l != NumLanes; ++l) {
2105  for (int i = 0, NumElements = CDS->getNumElements(); i < NumElements;
2106  ++i) {
2107  if (i != 0 || l != 0)
2108  CS << ",";
2109  if (CDS->getElementType()->isIntegerTy())
2110  printConstant(CDS->getElementAsAPInt(i), CS);
2111  else if (CDS->getElementType()->isHalfTy() ||
2112  CDS->getElementType()->isFloatTy() ||
2113  CDS->getElementType()->isDoubleTy())
2114  printConstant(CDS->getElementAsAPFloat(i), CS);
2115  else
2116  CS << "?";
2117  }
2118  }
2119  CS << "]";
2120  OutStreamer->AddComment(CS.str(), !EnablePrintSchedInfo);
2121  } else if (auto *CV = dyn_cast<ConstantVector>(C)) {
2122  CS << "<";
2123  for (int l = 0; l != NumLanes; ++l) {
2124  for (int i = 0, NumOperands = CV->getNumOperands(); i < NumOperands;
2125  ++i) {
2126  if (i != 0 || l != 0)
2127  CS << ",";
2128  printConstant(CV->getOperand(i), CS);
2129  }
2130  }
2131  CS << ">";
2132  OutStreamer->AddComment(CS.str(), !EnablePrintSchedInfo);
2133  }
2134  }
2135  break;
2136  case X86::MOVDDUPrm:
2137  case X86::VMOVDDUPrm:
2138  case X86::VMOVDDUPZ128rm:
2139  case X86::VBROADCASTSSrm:
2140  case X86::VBROADCASTSSYrm:
2141  case X86::VBROADCASTSSZ128m:
2142  case X86::VBROADCASTSSZ256m:
2143  case X86::VBROADCASTSSZm:
2144  case X86::VBROADCASTSDYrm:
2145  case X86::VBROADCASTSDZ256m:
2146  case X86::VBROADCASTSDZm:
2147  case X86::VPBROADCASTBrm:
2148  case X86::VPBROADCASTBYrm:
2149  case X86::VPBROADCASTBZ128m:
2150  case X86::VPBROADCASTBZ256m:
2151  case X86::VPBROADCASTBZm:
2152  case X86::VPBROADCASTDrm:
2153  case X86::VPBROADCASTDYrm:
2154  case X86::VPBROADCASTDZ128m:
2155  case X86::VPBROADCASTDZ256m:
2156  case X86::VPBROADCASTDZm:
2157  case X86::VPBROADCASTQrm:
2158  case X86::VPBROADCASTQYrm:
2159  case X86::VPBROADCASTQZ128m:
2160  case X86::VPBROADCASTQZ256m:
2161  case X86::VPBROADCASTQZm:
2162  case X86::VPBROADCASTWrm:
2163  case X86::VPBROADCASTWYrm:
2164  case X86::VPBROADCASTWZ128m:
2165  case X86::VPBROADCASTWZ256m:
2166  case X86::VPBROADCASTWZm:
2167  if (!OutStreamer->isVerboseAsm())
2168  break;
2169  if (MI->getNumOperands() <= 4)
2170  break;
2171  if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) {
2172  int NumElts;
2173  switch (MI->getOpcode()) {
2174  default: llvm_unreachable("Invalid opcode");
2175  case X86::MOVDDUPrm: NumElts = 2; break;
2176  case X86::VMOVDDUPrm: NumElts = 2; break;
2177  case X86::VMOVDDUPZ128rm: NumElts = 2; break;
2178  case X86::VBROADCASTSSrm: NumElts = 4; break;
2179  case X86::VBROADCASTSSYrm: NumElts = 8; break;
2180  case X86::VBROADCASTSSZ128m: NumElts = 4; break;
2181  case X86::VBROADCASTSSZ256m: NumElts = 8; break;
2182  case X86::VBROADCASTSSZm: NumElts = 16; break;
2183  case X86::VBROADCASTSDYrm: NumElts = 4; break;
2184  case X86::VBROADCASTSDZ256m: NumElts = 4; break;
2185  case X86::VBROADCASTSDZm: NumElts = 8; break;
2186  case X86::VPBROADCASTBrm: NumElts = 16; break;
2187  case X86::VPBROADCASTBYrm: NumElts = 32; break;
2188  case X86::VPBROADCASTBZ128m: NumElts = 16; break;
2189  case X86::VPBROADCASTBZ256m: NumElts = 32; break;
2190  case X86::VPBROADCASTBZm: NumElts = 64; break;
2191  case X86::VPBROADCASTDrm: NumElts = 4; break;
2192  case X86::VPBROADCASTDYrm: NumElts = 8; break;
2193  case X86::VPBROADCASTDZ128m: NumElts = 4; break;
2194  case X86::VPBROADCASTDZ256m: NumElts = 8; break;
2195  case X86::VPBROADCASTDZm: NumElts = 16; break;
2196  case X86::VPBROADCASTQrm: NumElts = 2; break;
2197  case X86::VPBROADCASTQYrm: NumElts = 4; break;
2198  case X86::VPBROADCASTQZ128m: NumElts = 2; break;
2199  case X86::VPBROADCASTQZ256m: NumElts = 4; break;
2200  case X86::VPBROADCASTQZm: NumElts = 8; break;
2201  case X86::VPBROADCASTWrm: NumElts = 8; break;
2202  case X86::VPBROADCASTWYrm: NumElts = 16; break;
2203  case X86::VPBROADCASTWZ128m: NumElts = 8; break;
2204  case X86::VPBROADCASTWZ256m: NumElts = 16; break;
2205  case X86::VPBROADCASTWZm: NumElts = 32; break;
2206  }
2207 
2208  std::string Comment;
2209  raw_string_ostream CS(Comment);
2210  const MachineOperand &DstOp = MI->getOperand(0);
2211  CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = ";
2212  CS << "[";
2213  for (int i = 0; i != NumElts; ++i) {
2214  if (i != 0)
2215  CS << ",";
2216  printConstant(C, CS);
2217  }
2218  CS << "]";
2219  OutStreamer->AddComment(CS.str(), !EnablePrintSchedInfo);
2220  }
2221  }
2222 
2223  MCInst TmpInst;
2224  MCInstLowering.Lower(MI, TmpInst);
2226  TmpInst.setFlags(TmpInst.getFlags() | X86::NO_SCHED_INFO);
2227 
2228  // Stackmap shadows cannot include branch targets, so we can count the bytes
2229  // in a call towards the shadow, but must ensure that the no thread returns
2230  // in to the stackmap shadow. The only way to achieve this is if the call
2231  // is at the end of the shadow.
2232  if (MI->isCall()) {
2233  // Count then size of the call towards the shadow
2234  SMShadowTracker.count(TmpInst, getSubtargetInfo(), CodeEmitter.get());
2235  // Then flush the shadow so that we fill with nops before the call, not
2236  // after it.
2237  SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
2238  // Then emit the call
2239  OutStreamer->EmitInstruction(TmpInst, getSubtargetInfo());
2240  return;
2241  }
2242 
2243  EmitAndCountInstruction(TmpInst);
2244 }
unsigned getTargetFlags() const
MO_SECREL - On a symbol operand this indicates that the immediate is the offset from beginning of sec...
Definition: X86BaseInfo.h:228
const NoneType None
Definition: None.h:24
unsigned GetCondBranchFromCond(CondCode CC)
uint64_t CallInst * C
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:525
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
bool isImm() const
Definition: MCInst.h:59
mop_iterator operands_end()
Definition: MachineInstr.h:454
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
unsigned getNextScratchIdx(unsigned StartIdx=0) const
Get the next scratch register operand index.
Definition: StackMaps.cpp:70
static const char * getRegisterName(unsigned RegNo)
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1557
virtual void EmitWinCFIPushReg(unsigned Register, SMLoc Loc=SMLoc())
Definition: MCStreamer.cpp:723
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "...
Definition: X86BaseInfo.h:238
virtual bool emitFPOSetFrame(unsigned Reg, SMLoc L={})=0
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:633
MachineBasicBlock * getMBB() const
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
Definition: AsmPrinter.h:93
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:322
MCTargetOptions MCOptions
Machine level options.
void DecodeVPERMILPMask(unsigned NumElts, unsigned ScalarBits, ArrayRef< uint64_t > RawMask, SmallVectorImpl< int > &ShuffleMask)
Decode a VPERMILPD/VPERMILPS variable mask from a raw array of constants.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
PointerTy getPointer() const
static MachineOperand CreateMCSymbol(MCSymbol *Sym, unsigned char TargetFlags=0)
void setTargetFlags(unsigned F)
StringRef getPrivateGlobalPrefix() const
Definition: DataLayout.h:294
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:42
iterator begin() const
Definition: ArrayRef.h:137
MO_TLSLD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with ...
Definition: X86BaseInfo.h:136
MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate is some TLS offset from the ...
Definition: X86BaseInfo.h:222
MCContext & OutContext
This is the context for the output file that we are streaming.
Definition: AsmPrinter.h:88
static MachineModuleInfoMachO & getMachOMMI(AsmPrinter &AP)
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:137
unsigned getNumWords() const
Get the number of words.
Definition: APInt.h:1510
bool EnablePrintSchedInfo
Enable print [latency:throughput] in output.
Definition: AsmPrinter.h:125
const MCSubtargetInfo & getSubtargetInfo() const
Return information about subtarget.
Definition: AsmPrinter.cpp:224
virtual void EmitWinCFISaveXMM(unsigned Register, unsigned Offset, SMLoc Loc=SMLoc())
Definition: MCStreamer.cpp:790
This provides a very simple, boring adaptor for a begin and end iterator into a range type...
unsigned getReg() const
getReg - Returns the register number.
virtual void EmitBytes(StringRef Data)
Emit the bytes in Data into the output.
Definition: MCStreamer.cpp:977
Address of indexed Jump Table for switch.
This class represents a function call, abstracting a target machine&#39;s calling convention.
unsigned Reg
bool isReg() const
Definition: MCInst.h:58
PointerIntPair< MCSymbol *, 1, bool > StubValueTy
static std::string getShuffleComment(const MachineInstr *MI, unsigned SrcOp1Idx, unsigned SrcOp2Idx, ArrayRef< int > Mask)
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:510
MachineBasicBlock reference.
MachineFunction * MF
The current machine function.
Definition: AsmPrinter.h:96
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
MachineInstrBundleIterator< const MachineInstr > const_iterator
MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...
Definition: X86BaseInfo.h:110
MO_DTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry with...
Definition: X86BaseInfo.h:179
static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, const MCSubtargetInfo &STI)
Emit the optimal amount of multi-byte nops on X86.
virtual bool emitFPOPushReg(unsigned Reg, SMLoc L={})=0
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:459
print alias Alias Set Printer
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
static MCOperand LowerSymbolOperand(const MachineOperand &MO, AsmPrinter &AP)
unsigned getSlotSize() const
virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, bool PrintSchedInfo=false)
Emit the given Instruction into the current section.
Definition: MCStreamer.cpp:915
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1503
Mask of preserved registers.
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
MCContext & getContext() const
Definition: MCStreamer.h:253
void recordSled(MCSymbol *Sled, const MachineInstr &MI, SledKind Kind, uint8_t Version=0)
CLEANUPRET - Represents a return from a cleanup block funclet.
Definition: ISDOpcodes.h:659
MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates that the reference is actually...
Definition: X86BaseInfo.h:210
amdgpu Simplify well known AMD library false Value Value const Twine & Name
bool isMachineConstantPoolEntry() const
isMachineConstantPoolEntry - Return true if the MachineConstantPoolEntry is indeed a target specific ...
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:116
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
virtual bool emitFPOStackAlloc(unsigned StackAlloc, SMLoc L={})=0
MachineModuleInfoCOFF - This is a MachineModuleInfoImpl implementation for COFF targets.
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:412
virtual void encodeInstruction(const MCInst &Inst, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
EncodeInstruction - Encode the given Inst to bytes on the output stream OS.
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:36
Name of external global symbol.
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:166
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:409
const char * getSymbolName() const
#define CASE_ALL_MOV_RM()
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:65
Context object for machine code objects.
Definition: MCContext.h:63
void recordFaultingOp(FaultKind FaultTy, const MCSymbol *HandlerLabel)
Definition: FaultMaps.cpp:31
virtual void AddComment(const Twine &T, bool EOL=true)
Add a textual comment.
Definition: MCStreamer.h:306
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:245
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:545
void toString(SmallVectorImpl< char > &Str, unsigned FormatPrecision=0, unsigned FormatMaxPadding=3, bool TruncateZero=true) const
Definition: APFloat.h:1167
bool isPositionIndependent() const
Definition: AsmPrinter.cpp:201
MO_GOT - On a symbol operand this indicates that the immediate is the offset to the GOT entry for the...
Definition: X86BaseInfo.h:95
MO_GOTTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry wi...
Definition: X86BaseInfo.h:154
MO_ABS8 - On a symbol operand this indicates that the symbol is known to be an absolute symbol in ran...
Definition: X86BaseInfo.h:233
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:133
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
virtual void emitRawComment(const Twine &T, bool TabPrefix=true)
Print T and prefix it with the comment string (normally #) and optionally a tab.
Definition: MCStreamer.cpp:99
This class is a data container for one entry in a MachineConstantPool.
virtual void EmitBinaryData(StringRef Data)
Functionally identical to EmitBytes.
Definition: MCStreamer.cpp:978
const MCExpr * getExpr() const
Definition: MCInst.h:96
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:460
MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the reference is actually to the "...
Definition: X86BaseInfo.h:205
void recordStatepoint(const MachineInstr &MI)
Generate a stackmap record for a statepoint instruction.
Definition: StackMaps.cpp:394
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:161
auto count(R &&Range, const E &Element) -> typename std::iterator_traits< decltype(adl_begin(Range))>::difference_type
Wrapper function around std::count to count the number of times an element Element occurs in the give...
Definition: STLExtras.h:1108
virtual bool emitFPOStackAlign(unsigned Align, SMLoc L={})=0
bool isX86_64ExtendedReg(unsigned RegNo)
isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or higher) register? e.g.
Definition: X86BaseInfo.h:772
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
int64_t getImm() const
Definition: MCInst.h:76
AddrNumOperands - Total number of operands in a memory reference.
Definition: X86BaseInfo.h:42
AddrSegmentReg - The operand # of the segment in the memory operand.
Definition: X86BaseInfo.h:39
Address of a global value.
Streaming machine code generation interface.
Definition: MCStreamer.h:183
MCSymbol * createTempSymbol(bool CanBeUnnamed=true)
Create and return a new assembler temporary symbol with a unique but unspecified name.
Definition: MCContext.cpp:217
MCTargetStreamer * getTargetStreamer()
Definition: MCStreamer.h:260
bool getAsmPrinterFlag(CommentFlag Flag) const
Return whether an AsmPrinter flag is set.
Definition: MachineInstr.h:275
MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a relocation of: SYMBOL_LABEL + [...
Definition: X86BaseInfo.h:83
PointerIntPair - This class implements a pair of a pointer and small integer.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void DecodeVPPERMMask(ArrayRef< uint64_t > RawMask, SmallVectorImpl< int > &ShuffleMask)
Decode a VPPERM mask from a raw array of constants such as from BUILD_VECTOR.
MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry w...
Definition: X86BaseInfo.h:195
MO_TLVP - On a symbol operand this indicates that the immediate is some TLS offset.
Definition: X86BaseInfo.h:216
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This is an important base class in LLVM.
Definition: Constant.h:42
unsigned getFlags() const
Definition: MCInst.h:177
const GlobalValue * getGlobal() const
MO_TLSLDM - On a symbol operand this indicates that the immediate is the offset of the GOT entry with...
Definition: X86BaseInfo.h:146
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:22
void DecodeVPERMIL2PMask(unsigned NumElts, unsigned ScalarBits, unsigned M2Z, ArrayRef< uint64_t > RawMask, SmallVectorImpl< int > &ShuffleMask)
Decode a VPERMIL2PD/VPERMIL2PS variable mask from a raw array of constants.
TargetMachine & TM
Target machine description.
Definition: AsmPrinter.h:81
This class is intended to be used as a driving class for all asm writers.
Definition: AsmPrinter.h:78
void getNameWithPrefix(SmallVectorImpl< char > &Name, const GlobalValue *GV) const
Definition: AsmPrinter.cpp:423
bool hasInternalLinkage() const
Definition: GlobalValue.h:434
Address of a basic block.
bool isExpr() const
Definition: MCInst.h:61
static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst, unsigned Opcode)
Simplify things like MOV32rm to MOV32o32a.
MO_NTPOFF - On a symbol operand this indicates that the immediate is the negative thread-pointer offs...
Definition: X86BaseInfo.h:187
MI-level patchpoint operands.
Definition: StackMaps.h:77
unsigned getNumOperands() const
Definition: MCInst.h:184
int getSEHRegNum(unsigned i) const
void print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const
Print this MI to OS.
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
static const Constant * getConstantFromPool(const MachineInstr &MI, const MachineOperand &Op)
const MachineBasicBlock & front() const
bool useRetpolineIndirectCalls() const
Definition: X86Subtarget.h:674
size_t size() const
Definition: SmallVector.h:53
virtual MCSymbol * GetCPISymbol(unsigned CPID) const
Return the symbol for the specified constant pool entry.
StubValueTy & getGVStubEntry(MCSymbol *Sym)
virtual void EmitWinCFISetFrame(unsigned Register, unsigned Offset, SMLoc Loc=SMLoc())
Definition: MCStreamer.cpp:734
std::string & str()
Flushes the stream contents to the target string and returns the string&#39;s reference.
Definition: raw_ostream.h:499
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void recordPatchPoint(const MachineInstr &MI)
Generate a stackmap record for a patchpoint instruction.
Definition: StackMaps.cpp:373
MO_TLSGD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with ...
Definition: X86BaseInfo.h:126
union llvm::MachineConstantPoolEntry::@150 Val
The constant itself.
const std::vector< MachineConstantPoolEntry > & getConstants() const
virtual void EmitWinCFIPushFrame(bool Code, SMLoc Loc=SMLoc())
Definition: MCStreamer.cpp:805
MO_TPOFF - On a symbol operand this indicates that the immediate is the thread-pointer offset for the...
Definition: X86BaseInfo.h:171
static void printConstant(const APInt &Val, raw_ostream &CS)
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
void setFlags(unsigned F)
Definition: MCInst.h:176
void setOpcode(unsigned Op)
Definition: MCInst.h:173
MCSymbol * GetBlockAddressSymbol(const BlockAddress *BA) const
Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block.
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
MCSymbol * getSymbol(const GlobalValue *GV) const
Definition: AsmPrinter.cpp:428
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:847
virtual void EmitWinCFIEndProlog(SMLoc Loc=SMLoc())
Definition: MCStreamer.cpp:819
virtual void EmitCodeAlignment(unsigned ByteAlignment, unsigned MaxBytesToEmit=0)
Emit nops until the byte alignment ByteAlignment is reached.
Definition: MCStreamer.cpp:990
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:182
virtual void EmitWinCFIAllocStack(unsigned Size, SMLoc Loc=SMLoc())
Definition: MCStreamer.cpp:756
iterator end() const
Definition: ArrayRef.h:138
X86 target streamer implementing x86-only assembly directives.
int64_t getImm() const
MCSymbol reference (for debug/eh info)
StubValueTy & getGVStubEntry(MCSymbol *Sym)
Target - Wrapper for Target specific information.
Class for arbitrary precision integers.
Definition: APInt.h:70
void recordStackMap(const MachineInstr &MI)
Generate a stackmap record for a stackmap instruction.
Definition: StackMaps.cpp:364
virtual bool emitFPOEndPrologue(SMLoc L={})=0
CATCHRET - Represents a return from a catch block funclet.
Definition: ISDOpcodes.h:655
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:254
const uint64_t * getRawData() const
This function returns a pointer to the internal storage of the APInt.
Definition: APInt.h:675
Representation of each machine instruction.
Definition: MachineInstr.h:64
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MO_GOTOFF - On a symbol operand this indicates that the immediate is the offset to the location of th...
Definition: X86BaseInfo.h:102
static unsigned getRetOpcode(const X86Subtarget &Subtarget)
unsigned getNumFrameInfos()
Definition: MCStreamer.h:264
MCSymbol * GetJTISymbol(unsigned JTID, bool isLinkerPrivate=false) const
Return the symbol for the specified jump table entry.
MO_INDNTPOFF - On a symbol operand this indicates that the immediate is the absolute address of the G...
Definition: X86BaseInfo.h:163
virtual void EmitWinCFISaveReg(unsigned Register, unsigned Offset, SMLoc Loc=SMLoc())
Definition: MCStreamer.cpp:773
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:123
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:56
TargetOptions Options
Definition: TargetMachine.h:97
int64_t getOffset() const
Return the offset from the symbol in this operand.
const BlockAddress * getBlockAddress() const
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
Generic base class for all target subtargets.
MI-level Statepoint operands.
Definition: StackMaps.h:155
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given patchpoint should emit.
Definition: StackMaps.h:105
void EmitInstruction(const MachineInstr *MI) override
Targets should implement this to emit instructions.
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
MachineModuleInfoMachO - This is a MachineModuleInfoImpl implementation for MachO targets...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents &#39;eh_return&#39; gcc dwarf builtin...
Definition: ISDOpcodes.h:102
MO_PLT - On a symbol operand this indicates that the immediate is offset to the PLT entry of symbol n...
Definition: X86BaseInfo.h:117
void DecodePSHUFBMask(ArrayRef< uint64_t > RawMask, SmallVectorImpl< int > &ShuffleMask)
Decode a PSHUFB mask from a raw array of constants such as from BUILD_VECTOR.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:483
MCSymbol * getMCSymbol() const
mop_iterator operands_begin()
Definition: MachineInstr.h:453
static const char * name
ArrayRef< MCDwarfFrameInfo > getDwarfFrameInfos() const
Definition: MCStreamer.h:265
MCSymbol * getPICBaseSymbol() const
getPICBaseSymbol - Return a function-local symbol to represent the PIC base.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
virtual void EmitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
Definition: MCStreamer.cpp:328
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:46
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:59
MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the immediate should get the value of th...
Definition: X86BaseInfo.h:88
void getNameWithPrefix(raw_ostream &OS, const GlobalValue *GV, bool CannotUsePrivateLabel) const
Print the appropriate prefix and the specified global variable&#39;s name.
Definition: Mangler.cpp:112
static MachineBasicBlock::const_iterator PrevCrossBBInst(MachineBasicBlock::const_iterator MBBI)
IRTranslator LLVM IR MI
const MachineOperand & getCallTarget() const
Returns the target of the underlying call.
Definition: StackMaps.h:110
void addOperand(const MCOperand &Op)
Definition: MCInst.h:186
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
Address of indexed Constant in Constant Pool.
static MCSymbol * GetSymbolFromOperand(const MachineOperand &MO, AsmPrinter &AP)
unsigned getOpcode() const
Definition: MCInst.h:174
virtual bool isVerboseAsm() const
Return true if this streamer supports verbose assembly and if it is enabled.
Definition: MCStreamer.h:283
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:414
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:35
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:123
static unsigned EmitNop(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, const MCSubtargetInfo &STI)
Emit the largest nop instruction smaller than or equal to NumBytes bytes.
const X86Subtarget & getSubtarget() const
static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode)
Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with a short fixed-register form...
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx)
Definition: MCExpr.cpp:164
virtual void EmitCFIAdjustCfaOffset(int64_t Adjustment)
Definition: MCStreamer.cpp:415
static void SimplifyMOVSX(MCInst &Inst)
If a movsx instruction has a shorter encoding for the used register simplify the instruction to use i...
uint8_t getAsmPrinterFlags() const
Return the asm printer flags bitvector.
Definition: MachineInstr.h:269
MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the reference is actually to the "__imp...
Definition: X86BaseInfo.h:200
bool isImplicit() const