69 std::optional<MCOperand> LowerMachineOperand(
const MachineInstr *
MI,
107void X86AsmPrinter::StackMapShadowTracker::count(
MCInst &Inst,
114 CurrentShadowSize +=
Code.size();
115 if (CurrentShadowSize >= RequiredShadowSize)
120void X86AsmPrinter::StackMapShadowTracker::emitShadowPadding(
122 if (InShadow && CurrentShadowSize < RequiredShadowSize) {
124 emitX86Nops(OutStreamer, RequiredShadowSize - CurrentShadowSize,
129void X86AsmPrinter::EmitAndCountInstruction(
MCInst &Inst) {
136 : Ctx(mf.getContext()), MF(mf),
TM(mf.getTarget()), MAI(*
TM.getMCAsmInfo()),
152 "Isn't a symbol reference");
168 Suffix =
"$non_lazy_ptr";
173 Name +=
DL.getPrivateGlobalPrefix();
180 }
else if (MO.
isMBB()) {
187 Sym = Ctx.getOrCreateSymbol(
Name);
198 if (!StubSym.getPointer()) {
208 getMachOMMI().getGVStubEntry(
Sym);
226 const MCExpr *Expr =
nullptr;
303 assert(MAI.doesSetDirectiveSuppressReloc());
325 return Subtarget.is64Bit() ? X86::RET64 : X86::RET32;
328std::optional<MCOperand>
366 Opcode = X86::JMP32r;
369 Opcode = X86::JMP32m;
371 case X86::TAILJMPr64:
372 Opcode = X86::JMP64r;
374 case X86::TAILJMPm64:
375 Opcode = X86::JMP64m;
377 case X86::TAILJMPr64_REX:
378 Opcode = X86::JMP64r_REX;
380 case X86::TAILJMPm64_REX:
381 Opcode = X86::JMP64m_REX;
384 case X86::TAILJMPd64:
387 case X86::TAILJMPd_CC:
388 case X86::TAILJMPd64_CC:
400 if (
auto MaybeMCOp = LowerMachineOperand(
MI, MO))
403 bool In64BitMode =
AsmPrinter.getSubtarget().is64Bit();
420 "Unexpected # of LEA operands");
422 "LEA has segment specified!");
427 case X86::MULX64Hrm: {
432 case X86::MULX32Hrr: NewOpc = X86::MULX32rr;
break;
433 case X86::MULX32Hrm: NewOpc = X86::MULX32rm;
break;
434 case X86::MULX64Hrr: NewOpc = X86::MULX64rr;
break;
435 case X86::MULX64Hrm: NewOpc = X86::MULX64rm;
break;
448 case X86::CALL64pcrel32:
452 case X86::EH_RETURN64: {
457 case X86::CLEANUPRET: {
463 case X86::CATCHRET: {
466 unsigned ReturnReg = In64BitMode ? X86::RAX : X86::EAX;
475 case X86::TAILJMPr64:
476 case X86::TAILJMPr64_REX:
478 case X86::TAILJMPd64:
482 case X86::TAILJMPd_CC:
483 case X86::TAILJMPd64_CC:
488 case X86::TAILJMPm64:
489 case X86::TAILJMPm64_REX:
491 "Unexpected number of operands!");
494 case X86::MASKMOVDQU:
495 case X86::VMASKMOVDQU:
510 if (!MF.getFunction().hasOptSize() && FlagDef && FlagDef->
isDead())
519void X86AsmPrinter::LowerTlsAddr(X86MCInstLower &MCInstLowering,
527 switch (
MI.getOpcode()) {
528 case X86::TLS_addr32:
529 case X86::TLS_addr64:
530 case X86::TLS_addrX32:
533 case X86::TLS_base_addr32:
536 case X86::TLS_base_addr64:
537 case X86::TLS_base_addrX32:
540 case X86::TLS_desc32:
541 case X86::TLS_desc64:
549 MCInstLowering.GetSymbolFromOperand(
MI.getOperand(3)), SRVK, Ctx);
561 MCInstLowering.GetSymbolFromOperand(
MI.getOperand(3)),
563 EmitAndCountInstruction(
565 .addReg(Is64BitsLP64 ? X86::RAX : X86::EAX)
566 .addReg(Is64Bits ? X86::RIP : X86::EBX)
571 EmitAndCountInstruction(
573 .addReg(Is64BitsLP64 ? X86::RAX : X86::EAX)
578 }
else if (Is64Bits) {
580 if (NeedsPadding && Is64BitsLP64)
606 EmitAndCountInstruction(
641 EmitAndCountInstruction(
656 unsigned MaxNopLength = 1;
657 if (Subtarget->is64Bit()) {
660 if (Subtarget->hasFeature(X86::TuningFast7ByteNOP))
662 else if (Subtarget->hasFeature(X86::TuningFast15ByteNOP))
664 else if (Subtarget->hasFeature(X86::TuningFast11ByteNOP))
668 }
if (Subtarget->is32Bit())
672 NumBytes = std::min(NumBytes, MaxNopLength);
675 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;
676 IndexReg = Displacement = SegmentReg = 0;
734 SegmentReg = X86::CS;
738 unsigned NumPrefixes = std::min(NumBytes - NopSize, 5U);
739 NopSize += NumPrefixes;
740 for (
unsigned i = 0; i != NumPrefixes; ++i)
741 OS.emitBytes(
"\x66");
758 .addImm(Displacement)
763 assert(NopSize <= NumBytes &&
"We overemitted?");
770 unsigned NopsToEmit = NumBytes;
773 NumBytes -=
emitNop(
OS, NumBytes, Subtarget);
774 assert(NopsToEmit >= NumBytes &&
"Emitted more than I asked for!");
779 X86MCInstLower &MCIL) {
780 assert(Subtarget->is64Bit() &&
"Statepoint currently only supports X86-64");
785 if (
unsigned PatchBytes = SOpers.getNumPatchBytes()) {
792 switch (CallTarget.
getType()) {
795 CallTargetMCOp = MCIL.LowerSymbolOperand(
796 CallTarget, MCIL.GetSymbolFromOperand(CallTarget));
797 CallOpcode = X86::CALL64pcrel32;
805 CallOpcode = X86::CALL64pcrel32;
817 CallOpcode = X86::CALL64r;
827 CallInst.addOperand(CallTargetMCOp);
839void X86AsmPrinter::LowerFAULTING_OP(
const MachineInstr &FaultingMI,
840 X86MCInstLower &MCIL) {
851 unsigned OperandsBeginIdx = 4;
861 MI.setOpcode(Opcode);
863 if (DefRegister != X86::NoRegister)
868 if (
auto MaybeOperand = MCIL.LowerMachineOperand(&FaultingMI, MO))
869 MI.addOperand(*MaybeOperand);
876 X86MCInstLower &MCIL) {
877 bool Is64Bits = Subtarget->is64Bit();
883 EmitAndCountInstruction(
884 MCInstBuilder(Is64Bits ? X86::CALL64pcrel32 : X86::CALLpcrel32)
889 assert(std::next(
MI.getIterator())->isCall() &&
890 "KCFI_CHECK not followed by a call instruction");
897 int64_t PrefixNops = 0;
908 const Register AddrReg =
MI.getOperand(0).getReg();
912 unsigned TempReg = AddrReg == X86::R10 ? X86::R11D : X86::R10D;
913 EmitAndCountInstruction(
916 .addReg(X86::NoRegister)
920 .addReg(X86::NoRegister)
921 .addImm(-(PrefixNops + 4))
922 .addReg(X86::NoRegister));
925 EmitAndCountInstruction(
937void X86AsmPrinter::LowerASAN_CHECK_MEMACCESS(
const MachineInstr &
MI) {
944 const auto &
Reg =
MI.getOperand(0).getReg();
951 AccessInfo.CompileKernel, &ShadowBase,
952 &MappingScale, &OrShadowOffset);
956 std::string SymName = (
"__asan_check_" +
Name +
"_" +
Op +
"_" +
957 Twine(1ULL << AccessInfo.AccessSizeIndex) +
"_" +
962 "OrShadowOffset is not supported with optimized callbacks");
964 EmitAndCountInstruction(
971 X86MCInstLower &MCIL) {
976 auto NextMI = std::find_if(std::next(
MI.getIterator()),
977 MI.getParent()->end().getInstrIterator(),
978 [](
auto &II) { return !II.isMetaInstruction(); });
981 unsigned MinSize =
MI.getOperand(0).getImm();
983 if (NextMI !=
MI.getParent()->end() && !NextMI->isInlineAsm()) {
988 MCIL.Lower(&*NextMI, MCI);
994 if (
Code.size() < MinSize) {
995 if (MinSize == 2 && Subtarget->is32Bit() &&
997 (Subtarget->getCPU().empty() || Subtarget->getCPU() ==
"pentium3")) {
1003 MCInstBuilder(X86::MOV32rr_REV).addReg(X86::EDI).addReg(X86::EDI),
1007 assert(NopSize == MinSize &&
"Could not implement MinSize!");
1023 unsigned NumShadowBytes =
MI.getOperand(1).getImm();
1024 SMShadowTracker.reset(NumShadowBytes);
1030 X86MCInstLower &MCIL) {
1031 assert(Subtarget->is64Bit() &&
"Patchpoint currently only supports X86-64");
1043 unsigned ScratchIdx = opers.getNextScratchIdx();
1044 unsigned EncodedBytes = 0;
1061 CalleeMCOp = MCIL.LowerSymbolOperand(CalleeMO,
1062 MCIL.GetSymbolFromOperand(CalleeMO));
1068 Register ScratchReg =
MI.getOperand(ScratchIdx).getReg();
1074 EmitAndCountInstruction(
1079 "Lowering patchpoint with thunks not yet implemented.");
1080 EmitAndCountInstruction(
MCInstBuilder(X86::CALL64r).addReg(ScratchReg));
1084 unsigned NumBytes = opers.getNumPatchBytes();
1085 assert(NumBytes >= EncodedBytes &&
1086 "Patchpoint can't request size less than the length of a call.");
1091void X86AsmPrinter::LowerPATCHABLE_EVENT_CALL(
const MachineInstr &
MI,
1092 X86MCInstLower &MCIL) {
1093 assert(Subtarget->is64Bit() &&
"XRay custom events only supports X86-64");
1118 OutStreamer->AddComment(
"# XRay Custom Event Log");
1129 const Register DestRegs[] = {X86::RDI, X86::RSI};
1130 bool UsedMask[] = {
false,
false};
1139 for (
unsigned I = 0;
I <
MI.getNumOperands(); ++
I)
1140 if (
auto Op = MCIL.LowerMachineOperand(&
MI,
MI.getOperand(
I))) {
1141 assert(
Op->isReg() &&
"Only support arguments in registers");
1144 if (SrcRegs[
I] != DestRegs[
I]) {
1146 EmitAndCountInstruction(
1157 for (
unsigned I = 0;
I <
MI.getNumOperands(); ++
I)
1158 if (SrcRegs[
I] != DestRegs[
I])
1159 EmitAndCountInstruction(
1171 .
addOperand(MCIL.LowerSymbolOperand(TOp, TSym)));
1174 for (
unsigned I =
sizeof UsedMask;
I-- > 0;)
1176 EmitAndCountInstruction(
MCInstBuilder(X86::POP64r).addReg(DestRegs[
I]));
1180 OutStreamer->AddComment(
"xray custom event end.");
1188void X86AsmPrinter::LowerPATCHABLE_TYPED_EVENT_CALL(
const MachineInstr &
MI,
1189 X86MCInstLower &MCIL) {
1190 assert(Subtarget->is64Bit() &&
"XRay typed events only supports X86-64");
1215 OutStreamer->AddComment(
"# XRay Typed Event Log");
1227 const Register DestRegs[] = {X86::RDI, X86::RSI, X86::RDX};
1228 bool UsedMask[] = {
false,
false,
false};
1237 for (
unsigned I = 0;
I <
MI.getNumOperands(); ++
I)
1238 if (
auto Op = MCIL.LowerMachineOperand(&
MI,
MI.getOperand(
I))) {
1240 assert(
Op->isReg() &&
"Only supports arguments in registers");
1243 if (SrcRegs[
I] != DestRegs[
I]) {
1245 EmitAndCountInstruction(
1261 for (
unsigned I = 0;
I <
MI.getNumOperands(); ++
I)
1263 EmitAndCountInstruction(
1275 .
addOperand(MCIL.LowerSymbolOperand(TOp, TSym)));
1278 for (
unsigned I =
sizeof UsedMask;
I-- > 0;)
1280 EmitAndCountInstruction(
MCInstBuilder(X86::POP64r).addReg(DestRegs[
I]));
1290void X86AsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(
const MachineInstr &
MI,
1291 X86MCInstLower &MCIL) {
1296 if (
F.hasFnAttribute(
"patchable-function-entry")) {
1298 if (
F.getFnAttribute(
"patchable-function-entry")
1300 .getAsInteger(10, Num))
1331 X86MCInstLower &MCIL) {
1351 unsigned OpCode =
MI.getOperand(0).getImm();
1353 Ret.setOpcode(OpCode);
1355 if (
auto MaybeOperand = MCIL.LowerMachineOperand(&
MI, MO))
1356 Ret.addOperand(*MaybeOperand);
1362void X86AsmPrinter::LowerPATCHABLE_TAIL_CALL(
const MachineInstr &
MI,
1363 X86MCInstLower &MCIL) {
1385 unsigned OpCode =
MI.getOperand(0).getImm();
1394 if (
auto MaybeOperand = MCIL.LowerMachineOperand(&
MI, MO))
1427 unsigned SrcOpIdx) {
1437 CS <<
" {%" << Mask <<
"}";
1448 if (Src1Name == Src2Name)
1449 for (
int i = 0, e = ShuffleMask.
size(); i != e; ++i)
1450 if (ShuffleMask[i] >= e)
1451 ShuffleMask[i] -= e;
1453 for (
int i = 0, e = ShuffleMask.
size(); i != e; ++i) {
1463 bool isSrc1 = ShuffleMask[i] < (int)e;
1464 CS << (isSrc1 ? Src1Name : Src2Name) <<
'[';
1466 bool IsFirst =
true;
1468 (ShuffleMask[i] < (
int)e) == isSrc1) {
1476 CS << ShuffleMask[i] % (int)e;
1486 std::string Comment;
1507 bool PrintZero =
false) {
1516 CS << (PrintZero ? 0ULL : Val.
getRawData()[i]);
1523 bool PrintZero =
false) {
1529 Flt.toString(Str, 0, 0);
1535 if (isa<UndefValue>(COp)) {
1537 }
else if (
auto *CI = dyn_cast<ConstantInt>(COp)) {
1539 }
else if (
auto *CF = dyn_cast<ConstantFP>(COp)) {
1541 }
else if (
auto *CDS = dyn_cast<ConstantDataSequential>(COp)) {
1542 Type *EltTy = CDS->getElementType();
1546 unsigned E = std::min(
BitWidth / EltBits, CDS->getNumElements());
1548 for (
unsigned I = 0;
I != E; ++
I) {
1558 }
else if (
auto *CV = dyn_cast<ConstantVector>(COp)) {
1559 unsigned EltBits = CV->getType()->getScalarSizeInBits();
1560 unsigned E = std::min(
BitWidth / EltBits, CV->getNumOperands());
1562 for (
unsigned I = 0;
I != E; ++
I) {
1573 int SclWidth,
int VecWidth,
1574 const char *ShuffleComment) {
1577 std::string Comment;
1585 for (
int I = 1, E = VecWidth / SclWidth;
I < E; ++
I) {
1595 CS << ShuffleComment;
1603 std::string Comment;
1607 for (
int l = 0; l != Repeats; ++l) {
1618 int SrcEltBits,
int DstEltBits,
bool IsSext) {
1621 if (
C &&
C->getType()->getScalarSizeInBits() ==
unsigned(SrcEltBits)) {
1622 if (
auto *CDS = dyn_cast<ConstantDataSequential>(
C)) {
1623 int NumElts = CDS->getNumElements();
1624 std::string Comment;
1628 for (
int i = 0; i != NumElts; ++i) {
1631 if (CDS->getElementType()->isIntegerTy()) {
1632 APInt Elt = CDS->getElementAsAPInt(i);
1633 Elt = IsSext ? Elt.
sext(DstEltBits) : Elt.
zext(DstEltBits);
1647 int SrcEltBits,
int DstEltBits) {
1651 int SrcEltBits,
int DstEltBits) {
1652 if (
printExtend(
MI, OutStreamer, SrcEltBits, DstEltBits,
false))
1656 std::string Comment;
1663 assert((Width % DstEltBits) == 0 && (DstEltBits % SrcEltBits) == 0 &&
1664 "Illegal extension ratio");
1674 "SEH_ instruction Windows and UEFI only");
1680 switch (
MI->getOpcode()) {
1681 case X86::SEH_PushReg:
1684 case X86::SEH_StackAlloc:
1687 case X86::SEH_StackAlign:
1690 case X86::SEH_SetFrame:
1691 assert(
MI->getOperand(1).getImm() == 0 &&
1692 ".cv_fpo_setframe takes no offset");
1695 case X86::SEH_EndPrologue:
1698 case X86::SEH_SaveReg:
1699 case X86::SEH_SaveXMM:
1700 case X86::SEH_PushFrame:
1710 switch (
MI->getOpcode()) {
1711 case X86::SEH_PushReg:
1715 case X86::SEH_SaveReg:
1717 MI->getOperand(1).getImm());
1720 case X86::SEH_SaveXMM:
1722 MI->getOperand(1).getImm());
1725 case X86::SEH_StackAlloc:
1726 OutStreamer->emitWinCFIAllocStack(
MI->getOperand(0).getImm());
1729 case X86::SEH_SetFrame:
1731 MI->getOperand(1).getImm());
1734 case X86::SEH_PushFrame:
1735 OutStreamer->emitWinCFIPushFrame(
MI->getOperand(0).getImm());
1738 case X86::SEH_EndPrologue:
1749 switch (
MI->getOpcode()) {
1754 case X86::VPSHUFBrm:
1755 case X86::VPSHUFBYrm:
1756 case X86::VPSHUFBZ128rm:
1757 case X86::VPSHUFBZ128rmk:
1758 case X86::VPSHUFBZ128rmkz:
1759 case X86::VPSHUFBZ256rm:
1760 case X86::VPSHUFBZ256rmk:
1761 case X86::VPSHUFBZ256rmkz:
1762 case X86::VPSHUFBZrm:
1763 case X86::VPSHUFBZrmk:
1764 case X86::VPSHUFBZrmkz: {
1776 case X86::VPERMILPSrm:
1777 case X86::VPERMILPSYrm:
1778 case X86::VPERMILPSZ128rm:
1779 case X86::VPERMILPSZ128rmk:
1780 case X86::VPERMILPSZ128rmkz:
1781 case X86::VPERMILPSZ256rm:
1782 case X86::VPERMILPSZ256rmk:
1783 case X86::VPERMILPSZ256rmkz:
1784 case X86::VPERMILPSZrm:
1785 case X86::VPERMILPSZrmk:
1786 case X86::VPERMILPSZrmkz: {
1797 case X86::VPERMILPDrm:
1798 case X86::VPERMILPDYrm:
1799 case X86::VPERMILPDZ128rm:
1800 case X86::VPERMILPDZ128rmk:
1801 case X86::VPERMILPDZ128rmkz:
1802 case X86::VPERMILPDZ256rm:
1803 case X86::VPERMILPDZ256rmk:
1804 case X86::VPERMILPDZ256rmkz:
1805 case X86::VPERMILPDZrm:
1806 case X86::VPERMILPDZrmk:
1807 case X86::VPERMILPDZrmkz: {
1819 case X86::VPERMIL2PDrm:
1820 case X86::VPERMIL2PSrm:
1821 case X86::VPERMIL2PDYrm:
1822 case X86::VPERMIL2PSYrm: {
1824 "Unexpected number of operands!");
1827 if (!CtrlOp.
isImm())
1831 switch (
MI->getOpcode()) {
1833 case X86::VPERMIL2PSrm:
case X86::VPERMIL2PSYrm: ElSize = 32;
break;
1834 case X86::VPERMIL2PDrm:
case X86::VPERMIL2PDYrm: ElSize = 64;
break;
1847 case X86::VPPERMrrm: {
1858 case X86::MMX_MOVQ64rm: {
1860 std::string Comment;
1864 if (
auto *CF = dyn_cast<ConstantFP>(
C)) {
1865 CS <<
"0x" <<
toString(CF->getValueAPF().bitcastToAPInt(), 16,
false);
1872#define MASK_AVX512_CASE(Instr) \
1880 case X86::MOVSDrm_alt:
1881 case X86::VMOVSDrm_alt:
1882 case X86::VMOVSDZrm_alt:
1883 case X86::MOVQI2PQIrm:
1884 case X86::VMOVQI2PQIrm:
1885 case X86::VMOVQI2PQIZrm:
1890 case X86::VMOVSHZrm_alt:
1892 "mem[0],zero,zero,zero,zero,zero,zero,zero");
1898 case X86::MOVSSrm_alt:
1899 case X86::VMOVSSrm_alt:
1900 case X86::VMOVSSZrm_alt:
1901 case X86::MOVDI2PDIrm:
1902 case X86::VMOVDI2PDIrm:
1903 case X86::VMOVDI2PDIZrm:
1907#define MOV_CASE(Prefix, Suffix) \
1908 case X86::Prefix##MOVAPD##Suffix##rm: \
1909 case X86::Prefix##MOVAPS##Suffix##rm: \
1910 case X86::Prefix##MOVUPD##Suffix##rm: \
1911 case X86::Prefix##MOVUPS##Suffix##rm: \
1912 case X86::Prefix##MOVDQA##Suffix##rm: \
1913 case X86::Prefix##MOVDQU##Suffix##rm:
1915#define MOV_AVX512_CASE(Suffix, Postfix) \
1916 case X86::VMOVDQA64##Suffix##rm##Postfix: \
1917 case X86::VMOVDQA32##Suffix##rm##Postfix: \
1918 case X86::VMOVDQU64##Suffix##rm##Postfix: \
1919 case X86::VMOVDQU32##Suffix##rm##Postfix: \
1920 case X86::VMOVDQU16##Suffix##rm##Postfix: \
1921 case X86::VMOVDQU8##Suffix##rm##Postfix: \
1922 case X86::VMOVAPS##Suffix##rm##Postfix: \
1923 case X86::VMOVAPD##Suffix##rm##Postfix: \
1924 case X86::VMOVUPS##Suffix##rm##Postfix: \
1925 case X86::VMOVUPD##Suffix##rm##Postfix:
1927#define CASE_128_MOV_RM() \
1930 MOV_AVX512_CASE(Z128, ) \
1931 MOV_AVX512_CASE(Z128, k) \
1932 MOV_AVX512_CASE(Z128, kz)
1934#define CASE_256_MOV_RM() \
1936 MOV_AVX512_CASE(Z256, ) \
1937 MOV_AVX512_CASE(Z256, k) \
1938 MOV_AVX512_CASE(Z256, kz) \
1940#define CASE_512_MOV_RM() \
1941 MOV_AVX512_CASE(Z, ) \
1942 MOV_AVX512_CASE(Z, k) \
1943 MOV_AVX512_CASE(Z, kz) \
1956 case X86::VBROADCASTF128rm:
1957 case X86::VBROADCASTI128rm:
1979 case X86::MOVDDUPrm:
1980 case X86::VMOVDDUPrm:
1982 case X86::VPBROADCASTQrm:
1986 case X86::VBROADCASTSDYrm:
1988 case X86::VPBROADCASTQYrm:
1996 case X86::VBROADCASTSSrm:
1998 case X86::VPBROADCASTDrm:
2002 case X86::VBROADCASTSSYrm:
2004 case X86::VPBROADCASTDYrm:
2012 case X86::VPBROADCASTWrm:
2016 case X86::VPBROADCASTWYrm:
2023 case X86::VPBROADCASTBrm:
2027 case X86::VPBROADCASTBYrm:
2035#define MOVX_CASE(Prefix, Ext, Type, Suffix, Postfix) \
2036 case X86::Prefix##PMOV##Ext##Type##Suffix##rm##Postfix:
2038#define CASE_MOVX_RM(Ext, Type) \
2039 MOVX_CASE(, Ext, Type, , ) \
2040 MOVX_CASE(V, Ext, Type, , ) \
2041 MOVX_CASE(V, Ext, Type, Y, ) \
2042 MOVX_CASE(V, Ext, Type, Z128, ) \
2043 MOVX_CASE(V, Ext, Type, Z128, k ) \
2044 MOVX_CASE(V, Ext, Type, Z128, kz ) \
2045 MOVX_CASE(V, Ext, Type, Z256, ) \
2046 MOVX_CASE(V, Ext, Type, Z256, k ) \
2047 MOVX_CASE(V, Ext, Type, Z256, kz ) \
2048 MOVX_CASE(V, Ext, Type, Z, ) \
2049 MOVX_CASE(V, Ext, Type, Z, k ) \
2050 MOVX_CASE(V, Ext, Type, Z, kz )
2097 X86MCInstLower MCInstLowering(*
MF, *
this);
2101 if (
MI->getOpcode() == X86::OR64rm) {
2102 for (
auto &Opd :
MI->operands()) {
2103 if (Opd.isSymbol() &&
StringRef(Opd.getSymbolName()) ==
2104 "swift_async_extendedFramePointerFlags") {
2105 ShouldEmitWeakSwiftAsyncExtendedFramePointerFlags =
true;
2117 OutStreamer->AddComment(
"EVEX TO LEGACY Compression ",
false);
2119 OutStreamer->AddComment(
"EVEX TO VEX Compression ",
false);
2121 OutStreamer->AddComment(
"EVEX TO EVEX Compression ",
false);
2124 switch (
MI->getOpcode()) {
2125 case TargetOpcode::DBG_VALUE:
2128 case X86::EH_RETURN:
2129 case X86::EH_RETURN64: {
2136 case X86::CLEANUPRET: {
2142 case X86::CATCHRET: {
2149 case X86::ENDBR64: {
2158 MCInstLowering.Lower(
MI, Inst);
2159 EmitAndCountInstruction(Inst);
2167 case X86::TAILJMPd64:
2168 if (IndCSPrefix &&
MI->hasRegisterImplicitUseOperand(X86::R11))
2174 case X86::TAILJMPd_CC:
2175 case X86::TAILJMPr64:
2176 case X86::TAILJMPm64:
2177 case X86::TAILJMPd64_CC:
2178 case X86::TAILJMPr64_REX:
2179 case X86::TAILJMPm64_REX:
2184 case X86::TLS_addr32:
2185 case X86::TLS_addr64:
2186 case X86::TLS_addrX32:
2187 case X86::TLS_base_addr32:
2188 case X86::TLS_base_addr64:
2189 case X86::TLS_base_addrX32:
2190 case X86::TLS_desc32:
2191 case X86::TLS_desc64:
2192 return LowerTlsAddr(MCInstLowering, *
MI);
2194 case X86::MOVPC32r: {
2205 EmitAndCountInstruction(
2211 bool hasFP = FrameLowering->
hasFP(*
MF);
2214 bool HasActiveDwarfFrame =
OutStreamer->getNumFrameInfos() &&
2219 if (HasActiveDwarfFrame && !hasFP) {
2220 OutStreamer->emitCFIAdjustCfaOffset(-stackGrowth);
2228 EmitAndCountInstruction(
2231 if (HasActiveDwarfFrame && !hasFP) {
2237 case X86::ADD32ri: {
2253 MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(
MI->getOperand(2));
2264 .addReg(
MI->getOperand(0).getReg())
2265 .
addReg(
MI->getOperand(1).getReg())
2269 case TargetOpcode::STATEPOINT:
2270 return LowerSTATEPOINT(*
MI, MCInstLowering);
2272 case TargetOpcode::FAULTING_OP:
2273 return LowerFAULTING_OP(*
MI, MCInstLowering);
2275 case TargetOpcode::FENTRY_CALL:
2276 return LowerFENTRY_CALL(*
MI, MCInstLowering);
2278 case TargetOpcode::PATCHABLE_OP:
2279 return LowerPATCHABLE_OP(*
MI, MCInstLowering);
2281 case TargetOpcode::STACKMAP:
2282 return LowerSTACKMAP(*
MI);
2284 case TargetOpcode::PATCHPOINT:
2285 return LowerPATCHPOINT(*
MI, MCInstLowering);
2287 case TargetOpcode::PATCHABLE_FUNCTION_ENTER:
2288 return LowerPATCHABLE_FUNCTION_ENTER(*
MI, MCInstLowering);
2290 case TargetOpcode::PATCHABLE_RET:
2291 return LowerPATCHABLE_RET(*
MI, MCInstLowering);
2293 case TargetOpcode::PATCHABLE_TAIL_CALL:
2294 return LowerPATCHABLE_TAIL_CALL(*
MI, MCInstLowering);
2296 case TargetOpcode::PATCHABLE_EVENT_CALL:
2297 return LowerPATCHABLE_EVENT_CALL(*
MI, MCInstLowering);
2299 case TargetOpcode::PATCHABLE_TYPED_EVENT_CALL:
2300 return LowerPATCHABLE_TYPED_EVENT_CALL(*
MI, MCInstLowering);
2302 case X86::MORESTACK_RET:
2306 case X86::KCFI_CHECK:
2307 return LowerKCFI_CHECK(*
MI);
2309 case X86::ASAN_CHECK_MEMACCESS:
2310 return LowerASAN_CHECK_MEMACCESS(*
MI);
2312 case X86::MORESTACK_RET_RESTORE_R10:
2315 EmitAndCountInstruction(
2316 MCInstBuilder(X86::MOV64rr).addReg(X86::R10).addReg(X86::RAX));
2319 case X86::SEH_PushReg:
2320 case X86::SEH_SaveReg:
2321 case X86::SEH_SaveXMM:
2322 case X86::SEH_StackAlloc:
2323 case X86::SEH_StackAlign:
2324 case X86::SEH_SetFrame:
2325 case X86::SEH_PushFrame:
2326 case X86::SEH_EndPrologue:
2327 EmitSEHInstruction(
MI);
2330 case X86::SEH_Epilogue: {
2340 if (
MBBI->isCall() || !
MBBI->isPseudo()) {
2348 case X86::UBSAN_UD1:
2353 .addReg(X86::NoRegister)
2354 .addImm(
MI->getOperand(0).getImm())
2355 .
addReg(X86::NoRegister));
2357 case X86::CALL64pcrel32:
2358 if (IndCSPrefix &&
MI->hasRegisterImplicitUseOperand(X86::R11))
2364 MCInstLowering.Lower(
MI, TmpInst);
2381 EmitAndCountInstruction(TmpInst);
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
static MCSymbol * GetSymbolFromOperand(const MachineOperand &MO, AsmPrinter &AP)
const char LLVMTargetMachineRef TM
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallString class.
static MCOperand LowerSymbolOperand(const MachineInstr *MI, const MachineOperand &MO, AsmPrinter &AP)
static void printShuffleMask(raw_ostream &CS, StringRef Src1Name, StringRef Src2Name, ArrayRef< int > Mask)
static void emitX86Nops(MCStreamer &OS, unsigned NumBytes, const X86Subtarget *Subtarget)
Emit the optimal amount of multi-byte nops on X86.
static unsigned getRetOpcode(const X86Subtarget &Subtarget)
static void printSignExtend(const MachineInstr *MI, MCStreamer &OutStreamer, int SrcEltBits, int DstEltBits)
static unsigned convertTailJumpOpcode(unsigned Opcode)
static unsigned getSrcIdx(const MachineInstr *MI, unsigned SrcIdx)
static void printBroadcast(const MachineInstr *MI, MCStreamer &OutStreamer, int Repeats, int BitWidth)
static bool printExtend(const MachineInstr *MI, MCStreamer &OutStreamer, int SrcEltBits, int DstEltBits, bool IsSext)
static void printZeroUpperMove(const MachineInstr *MI, MCStreamer &OutStreamer, int SclWidth, int VecWidth, const char *ShuffleComment)
#define MASK_AVX512_CASE(Instr)
static void addConstantComments(const MachineInstr *MI, MCStreamer &OutStreamer)
#define CASE_256_MOV_RM()
static MachineBasicBlock::const_iterator PrevCrossBBInst(MachineBasicBlock::const_iterator MBBI)
static unsigned emitNop(MCStreamer &OS, unsigned NumBytes, const X86Subtarget *Subtarget)
Emit the largest nop instruction smaller than or equal to NumBytes bytes.
static void printDstRegisterName(raw_ostream &CS, const MachineInstr *MI, unsigned SrcOpIdx)
#define CASE_MOVX_RM(Ext, Type)
static void printConstant(const APInt &Val, raw_ostream &CS, bool PrintZero=false)
static void printZeroExtend(const MachineInstr *MI, MCStreamer &OutStreamer, int SrcEltBits, int DstEltBits)
static std::string getShuffleComment(const MachineInstr *MI, unsigned SrcOp1Idx, unsigned SrcOp2Idx, ArrayRef< int > Mask)
#define CASE_512_MOV_RM()
#define CASE_128_MOV_RM()
void toString(SmallVectorImpl< char > &Str, unsigned FormatPrecision=0, unsigned FormatMaxPadding=3, bool TruncateZero=true) const
static APFloat getZero(const fltSemantics &Sem, bool Negative=false)
Factory for Positive and Negative Zero.
Class for arbitrary precision integers.
APInt zext(unsigned width) const
Zero extend to a new width.
uint64_t getZExtValue() const
Get zero extended value.
unsigned getBitWidth() const
Return the number of bits in the APInt.
unsigned getNumWords() const
Get the number of words.
APInt sext(unsigned width) const
Sign extend to a new width.
const uint64_t * getRawData() const
This function returns a pointer to the internal storage of the APInt.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
This class is intended to be used as a driving class for all asm writers.
MCSymbol * getSymbol(const GlobalValue *GV) const
MCSymbol * CurrentFnBegin
TargetMachine & TM
Target machine description.
virtual MCSymbol * GetCPISymbol(unsigned CPID) const
Return the symbol for the specified constant pool entry.
void emitKCFITrapEntry(const MachineFunction &MF, const MCSymbol *Symbol)
MachineFunction * MF
The current machine function.
MCSymbol * GetJTISymbol(unsigned JTID, bool isLinkerPrivate=false) const
Return the symbol for the specified jump table entry.
void recordSled(MCSymbol *Sled, const MachineInstr &MI, SledKind Kind, uint8_t Version=0)
MCSymbol * getSymbolPreferLocal(const GlobalValue &GV) const
Similar to getSymbol() but preferred for references.
MachineModuleInfo * MMI
This is a pointer to the current MachineModuleInfo.
MCContext & OutContext
This is the context for the output file that we are streaming.
MCSymbol * createTempSymbol(const Twine &Name) const
bool isPositionIndependent() const
MCSymbol * CurrentPatchableFunctionEntrySym
The symbol for the entry in __patchable_function_entires.
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
void getNameWithPrefix(SmallVectorImpl< char > &Name, const GlobalValue *GV) const
MCSymbol * GetBlockAddressSymbol(const BlockAddress *BA) const
Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block.
const MCSubtargetInfo & getSubtargetInfo() const
Return information about subtarget.
StringRef getValueAsString() const
Return the attribute's value as a string.
This class represents a function call, abstracting a target machine's calling convention.
This is an important base class in LLVM.
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
void recordFaultingOp(FaultKind FaultTy, const MCSymbol *FaultingLabel, const MCSymbol *HandlerLabel)
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
bool hasInternalLinkage() const
This class is intended to be used as a base class for asm properties and features specific to the tar...
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
MCCodeEmitter - Generic instruction encoding interface.
virtual void encodeInstruction(const MCInst &Inst, SmallVectorImpl< char > &CB, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
Encode the given Inst to bytes and append to CB.
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Context object for machine code objects.
MCSymbol * createTempSymbol()
Create a temporary symbol with a unique name.
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
const MCTargetOptions * getTargetOptions() const
Base class for the full range of assembler expressions which are needed for parsing.
MCInstBuilder & addReg(unsigned Reg)
Add a new register operand.
MCInstBuilder & addExpr(const MCExpr *Val)
Add a new MCExpr operand.
Instances of this class represent a single low-level machine instruction.
unsigned getNumOperands() const
unsigned getOpcode() const
iterator insert(iterator I, const MCOperand &Op)
void setFlags(unsigned F)
void addOperand(const MCOperand Op)
void setOpcode(unsigned Op)
const MCOperand & getOperand(unsigned i) const
Instances of this class represent operands of the MCInst class.
static MCOperand createReg(unsigned Reg)
static MCOperand createExpr(const MCExpr *Val)
static MCOperand createImm(int64_t Val)
unsigned getReg() const
Returns the register number.
const char * getName(MCRegister RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register.
Streaming machine code generation interface.
virtual void AddComment(const Twine &T, bool EOL=true)
Add a textual comment.
virtual void emitRawComment(const Twine &T, bool TabPrefix=true)
Print T and prefix it with the comment string (normally #) and optionally a tab.
void setAllowAutoPadding(bool v)
bool getAllowAutoPadding() const
Generic base class for all target subtargets.
Represent a reference to a symbol from inside an expression.
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
StringRef getName() const
getName - Get the symbol name.
MachineInstrBundleIterator< const MachineInstr > const_iterator
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MCSymbol * getPICBaseSymbol() const
getPICBaseSymbol - Return a function-local symbol to represent the PIC base.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineBasicBlock & front() const
Representation of each machine instruction.
iterator_range< mop_iterator > operands()
const MachineOperand & getOperand(unsigned i) const
MachineModuleInfoCOFF - This is a MachineModuleInfoImpl implementation for COFF targets.
StubValueTy & getGVStubEntry(MCSymbol *Sym)
PointerIntPair< MCSymbol *, 1, bool > StubValueTy
MachineModuleInfoMachO - This is a MachineModuleInfoImpl implementation for MachO targets.
const Module * getModule() const
MachineOperand class - Representation of each machine instruction operand.
static MachineOperand CreateMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
const GlobalValue * getGlobal() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineBasicBlock * getMBB() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
const BlockAddress * getBlockAddress() const
unsigned getTargetFlags() const
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
const char * getSymbolName() const
Register getReg() const
getReg - Returns the register number.
void setTargetFlags(unsigned F)
MCSymbol * getMCSymbol() const
@ MO_Immediate
Immediate operand.
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
@ MO_MCSymbol
MCSymbol reference (for debug/eh info)
@ MO_GlobalAddress
Address of a global value.
@ MO_RegisterMask
Mask of preserved registers.
@ MO_BlockAddress
Address of a basic block.
@ MO_MachineBasicBlock
MachineBasicBlock reference.
@ MO_Register
Register operand.
@ MO_ExternalSymbol
Name of external global symbol.
@ MO_JumpTableIndex
Address of indexed Jump Table for switch.
int64_t getOffset() const
Return the offset from the symbol in this operand.
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
void getNameWithPrefix(raw_ostream &OS, const GlobalValue *GV, bool CannotUsePrivateLabel) const
Print the appropriate prefix and the specified global variable's name.
bool getRtLibUseGOT() const
Returns true if PLT should be avoided for RTLib calls.
Pass interface - Implemented by all 'passes'.
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
MI-level patchpoint operands.
PointerIntPair - This class implements a pair of a pointer and small integer.
PointerTy getPointer() const
Wrapper class representing virtual and physical registers.
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
void recordStatepoint(const MCSymbol &L, const MachineInstr &MI)
Generate a stackmap record for a statepoint instruction.
void recordPatchPoint(const MCSymbol &L, const MachineInstr &MI)
Generate a stackmap record for a patchpoint instruction.
void recordStackMap(const MCSymbol &L, const MachineInstr &MI)
Generate a stackmap record for a stackmap instruction.
MI-level Statepoint operands.
StringRef - Represent a constant reference to a string, i.e.
bool getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
constexpr bool empty() const
empty - Check if the string is empty.
Primary interface to the complete machine description for the target machine.
const Triple & getTargetTriple() const
const MCRegisterInfo * getMCRegisterInfo() const
MCTargetOptions MCOptions
Machine level options.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
bool isUEFI() const
Tests whether the OS is UEFI.
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
The instances of the Type class are immutable: once they are created, they are never changed.
bool isFloatTy() const
Return true if this is 'float', a 32-bit IEEE fp type.
bool isHalfTy() const
Return true if this is 'half', a 16-bit IEEE fp type.
bool isDoubleTy() const
Return true if this is 'double', a 64-bit IEEE fp type.
bool isIntegerTy() const
True if this is an instance of IntegerType.
TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
static const char * getRegisterName(MCRegister Reg)
void emitInstruction(const MachineInstr *MI) override
Targets should implement this to emit instructions.
const X86Subtarget & getSubtarget() const
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
X86MachineFunctionInfo - This class is derived from MachineFunction and contains private X86 target-s...
unsigned getSlotSize() const
bool isTargetWindowsMSVC() const
bool isTarget64BitLP64() const
Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
bool useIndirectThunkCalls() const
X86 target streamer implementing x86-only assembly directives.
virtual bool emitFPOPushReg(unsigned Reg, SMLoc L={})
virtual bool emitFPOSetFrame(unsigned Reg, SMLoc L={})
virtual bool emitFPOEndPrologue(SMLoc L={})
virtual bool emitFPOStackAlign(unsigned Align, SMLoc L={})
virtual bool emitFPOStackAlloc(unsigned StackAlloc, SMLoc L={})
This class implements an extremely fast bulk output stream that can only output to a stream.
A raw_ostream that writes to an std::string.
std::string & str()
Returns the string's reference.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
Reg
All possible values of the reg field in the ModR/M byte.
bool isKMergeMasked(uint64_t TSFlags)
bool isX86_64ExtendedReg(unsigned RegNo)
@ MO_TLSLD
MO_TLSLD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with ...
@ MO_GOTPCREL_NORELAX
MO_GOTPCREL_NORELAX - Same as MO_GOTPCREL except that R_X86_64_GOTPCREL relocations are guaranteed to...
@ MO_GOTOFF
MO_GOTOFF - On a symbol operand this indicates that the immediate is the offset to the location of th...
@ MO_DARWIN_NONLAZY_PIC_BASE
MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates that the reference is actually...
@ MO_GOT_ABSOLUTE_ADDRESS
MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a relocation of: SYMBOL_LABEL + [.
@ MO_COFFSTUB
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "....
@ MO_NTPOFF
MO_NTPOFF - On a symbol operand this indicates that the immediate is the negative thread-pointer offs...
@ MO_DARWIN_NONLAZY
MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the reference is actually to the "...
@ MO_INDNTPOFF
MO_INDNTPOFF - On a symbol operand this indicates that the immediate is the absolute address of the G...
@ MO_GOTNTPOFF
MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry w...
@ MO_TPOFF
MO_TPOFF - On a symbol operand this indicates that the immediate is the thread-pointer offset for the...
@ MO_TLVP_PIC_BASE
MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate is some TLS offset from the ...
@ MO_GOT
MO_GOT - On a symbol operand this indicates that the immediate is the offset to the GOT entry for the...
@ MO_ABS8
MO_ABS8 - On a symbol operand this indicates that the symbol is known to be an absolute symbol in ran...
@ MO_PLT
MO_PLT - On a symbol operand this indicates that the immediate is offset to the PLT entry of symbol n...
@ MO_TLSGD
MO_TLSGD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with ...
@ MO_NO_FLAG
MO_NO_FLAG - No flag for the operand.
@ MO_TLVP
MO_TLVP - On a symbol operand this indicates that the immediate is some TLS offset.
@ MO_DLLIMPORT
MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the reference is actually to the "__imp...
@ MO_GOTTPOFF
MO_GOTTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry wi...
@ MO_SECREL
MO_SECREL - On a symbol operand this indicates that the immediate is the offset from beginning of sec...
@ MO_DTPOFF
MO_DTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry with...
@ MO_PIC_BASE_OFFSET
MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the immediate should get the value of th...
@ MO_TLSLDM
MO_TLSLDM - On a symbol operand this indicates that the immediate is the offset of the GOT entry with...
@ MO_GOTPCREL
MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...
bool isKMasked(uint64_t TSFlags)
bool optimizeToFixedRegisterOrShortImmediateForm(MCInst &MI)
bool optimizeMOV(MCInst &MI, bool In64BitMode)
Simplify things like MOV32rm to MOV32o32a.
bool optimizeMOVSX(MCInst &MI)
bool optimizeVPCMPWithImmediateOneOrSix(MCInst &MI)
bool optimizeShiftRotateWithImmediateOne(MCInst &MI)
bool optimizeInstFromVEX3ToVEX2(MCInst &MI, const MCInstrDesc &Desc)
const Constant * getConstantFromPool(const MachineInstr &MI, unsigned OpNo)
Find any constant pool entry associated with a specific instruction operand.
bool optimizeINCDEC(MCInst &MI, bool In64BitMode)
unsigned getVectorRegisterWidth(const MCOperandInfo &Info)
Get the width of the vector register operand.
std::optional< const char * > toString(const std::optional< DWARFFormValue > &V)
Take an optional DWARFFormValue and try to extract a string value from it.
NodeAddr< CodeNode * > Code
This is an optimization pass for GlobalISel generic memory operations.
void DecodeZeroExtendMask(unsigned SrcScalarBits, unsigned DstScalarBits, unsigned NumDstElts, bool IsAnyExtend, SmallVectorImpl< int > &ShuffleMask)
Decode a zero extension instruction as a shuffle mask.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
void DecodeVPERMILPMask(unsigned NumElts, unsigned ScalarBits, ArrayRef< uint64_t > RawMask, const APInt &UndefElts, SmallVectorImpl< int > &ShuffleMask)
Decode a VPERMILPD/VPERMILPS variable mask from a raw array of constants.
MCRegister getX86SubSuperRegister(MCRegister Reg, unsigned Size, bool High=false)
void DecodeVPERMIL2PMask(unsigned NumElts, unsigned ScalarBits, unsigned M2Z, ArrayRef< uint64_t > RawMask, const APInt &UndefElts, SmallVectorImpl< int > &ShuffleMask)
Decode a VPERMIL2PD/VPERMIL2PS variable mask from a raw array of constants.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
void DecodeVPPERMMask(ArrayRef< uint64_t > RawMask, const APInt &UndefElts, SmallVectorImpl< int > &ShuffleMask)
Decode a VPPERM mask from a raw array of constants such as from BUILD_VECTOR.
constexpr unsigned BitWidth
void getAddressSanitizerParams(const Triple &TargetTriple, int LongSize, bool IsKasan, uint64_t *ShadowBase, int *MappingScale, bool *OrShadowOffset)
void DecodePSHUFBMask(ArrayRef< uint64_t > RawMask, const APInt &UndefElts, SmallVectorImpl< int > &ShuffleMask)
Decode a PSHUFB mask from a raw array of constants such as from BUILD_VECTOR.
A RAII helper which defines a region of instructions which can't have padding added between them for ...
void changeAndComment(bool b)
NoAutoPaddingScope(MCStreamer &OS)
const bool OldAllowAutoPadding
This struct is a compact representation of a valid (non-zero power of two) alignment.