LLVM  9.0.0svn
X86MCInstLower.cpp
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1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains code to lower X86 MachineInstrs to their corresponding
10 // MCInst records.
11 //
12 //===----------------------------------------------------------------------===//
13 
18 #include "Utils/X86ShuffleDecode.h"
19 #include "X86AsmPrinter.h"
20 #include "X86RegisterInfo.h"
22 #include "llvm/ADT/Optional.h"
23 #include "llvm/ADT/SmallString.h"
29 #include "llvm/CodeGen/StackMaps.h"
30 #include "llvm/IR/DataLayout.h"
31 #include "llvm/IR/GlobalValue.h"
32 #include "llvm/IR/Mangler.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCCodeEmitter.h"
35 #include "llvm/MC/MCContext.h"
36 #include "llvm/MC/MCExpr.h"
37 #include "llvm/MC/MCFixup.h"
38 #include "llvm/MC/MCInst.h"
39 #include "llvm/MC/MCInstBuilder.h"
40 #include "llvm/MC/MCSection.h"
41 #include "llvm/MC/MCSectionELF.h"
42 #include "llvm/MC/MCStreamer.h"
43 #include "llvm/MC/MCSymbol.h"
44 #include "llvm/MC/MCSymbolELF.h"
46 
47 using namespace llvm;
48 
49 namespace {
50 
51 /// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst.
52 class X86MCInstLower {
53  MCContext &Ctx;
54  const MachineFunction &MF;
55  const TargetMachine &TM;
56  const MCAsmInfo &MAI;
58 
59 public:
60  X86MCInstLower(const MachineFunction &MF, X86AsmPrinter &asmprinter);
61 
62  Optional<MCOperand> LowerMachineOperand(const MachineInstr *MI,
63  const MachineOperand &MO) const;
64  void Lower(const MachineInstr *MI, MCInst &OutMI) const;
65 
67  MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
68 
69 private:
71 };
72 
73 } // end anonymous namespace
74 
75 // Emit a minimal sequence of nops spanning NumBytes bytes.
76 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
77  const MCSubtargetInfo &STI);
78 
80  const MCSubtargetInfo &STI,
81  MCCodeEmitter *CodeEmitter) {
82  if (InShadow) {
85  raw_svector_ostream VecOS(Code);
86  CodeEmitter->encodeInstruction(Inst, VecOS, Fixups, STI);
87  CurrentShadowSize += Code.size();
88  if (CurrentShadowSize >= RequiredShadowSize)
89  InShadow = false; // The shadow is big enough. Stop counting.
90  }
91 }
92 
93 void X86AsmPrinter::StackMapShadowTracker::emitShadowPadding(
94  MCStreamer &OutStreamer, const MCSubtargetInfo &STI) {
95  if (InShadow && CurrentShadowSize < RequiredShadowSize) {
96  InShadow = false;
97  EmitNops(OutStreamer, RequiredShadowSize - CurrentShadowSize,
98  MF->getSubtarget<X86Subtarget>().is64Bit(), STI);
99  }
100 }
101 
102 void X86AsmPrinter::EmitAndCountInstruction(MCInst &Inst) {
103  OutStreamer->EmitInstruction(Inst, getSubtargetInfo());
104  SMShadowTracker.count(Inst, getSubtargetInfo(), CodeEmitter.get());
105 }
106 
107 X86MCInstLower::X86MCInstLower(const MachineFunction &mf,
108  X86AsmPrinter &asmprinter)
109  : Ctx(mf.getContext()), MF(mf), TM(mf.getTarget()), MAI(*TM.getMCAsmInfo()),
110  AsmPrinter(asmprinter) {}
111 
113  return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>();
114 }
115 
116 /// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
117 /// operand to an MCSymbol.
119  const DataLayout &DL = MF.getDataLayout();
120  assert((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) &&
121  "Isn't a symbol reference");
122 
123  MCSymbol *Sym = nullptr;
125  StringRef Suffix;
126 
127  switch (MO.getTargetFlags()) {
128  case X86II::MO_DLLIMPORT:
129  // Handle dllimport linkage.
130  Name += "__imp_";
131  break;
132  case X86II::MO_COFFSTUB:
133  Name += ".refptr.";
134  break;
137  Suffix = "$non_lazy_ptr";
138  break;
139  }
140 
141  if (!Suffix.empty())
142  Name += DL.getPrivateGlobalPrefix();
143 
144  if (MO.isGlobal()) {
145  const GlobalValue *GV = MO.getGlobal();
146  AsmPrinter.getNameWithPrefix(Name, GV);
147  } else if (MO.isSymbol()) {
149  } else if (MO.isMBB()) {
150  assert(Suffix.empty());
151  Sym = MO.getMBB()->getSymbol();
152  }
153 
154  Name += Suffix;
155  if (!Sym)
156  Sym = Ctx.getOrCreateSymbol(Name);
157 
158  // If the target flags on the operand changes the name of the symbol, do that
159  // before we return the symbol.
160  switch (MO.getTargetFlags()) {
161  default:
162  break;
163  case X86II::MO_COFFSTUB: {
164  MachineModuleInfoCOFF &MMICOFF =
165  MF.getMMI().getObjFileInfo<MachineModuleInfoCOFF>();
166  MachineModuleInfoImpl::StubValueTy &StubSym = MMICOFF.getGVStubEntry(Sym);
167  if (!StubSym.getPointer()) {
168  assert(MO.isGlobal() && "Extern symbol not handled yet");
170  AsmPrinter.getSymbol(MO.getGlobal()), true);
171  }
172  break;
173  }
178  if (!StubSym.getPointer()) {
179  assert(MO.isGlobal() && "Extern symbol not handled yet");
182  !MO.getGlobal()->hasInternalLinkage());
183  }
184  break;
185  }
186  }
187 
188  return Sym;
189 }
190 
192  MCSymbol *Sym) const {
193  // FIXME: We would like an efficient form for this, so we don't have to do a
194  // lot of extra uniquing.
195  const MCExpr *Expr = nullptr;
197 
198  switch (MO.getTargetFlags()) {
199  default:
200  llvm_unreachable("Unknown target flag on GV operand");
201  case X86II::MO_NO_FLAG: // No flag.
202  // These affect the name of the symbol, not any suffix.
204  case X86II::MO_DLLIMPORT:
205  case X86II::MO_COFFSTUB:
206  break;
207 
208  case X86II::MO_TLVP:
209  RefKind = MCSymbolRefExpr::VK_TLVP;
210  break;
213  // Subtract the pic base.
215  Expr, MCSymbolRefExpr::create(MF.getPICBaseSymbol(), Ctx), Ctx);
216  break;
217  case X86II::MO_SECREL:
218  RefKind = MCSymbolRefExpr::VK_SECREL;
219  break;
220  case X86II::MO_TLSGD:
221  RefKind = MCSymbolRefExpr::VK_TLSGD;
222  break;
223  case X86II::MO_TLSLD:
224  RefKind = MCSymbolRefExpr::VK_TLSLD;
225  break;
226  case X86II::MO_TLSLDM:
227  RefKind = MCSymbolRefExpr::VK_TLSLDM;
228  break;
229  case X86II::MO_GOTTPOFF:
231  break;
232  case X86II::MO_INDNTPOFF:
234  break;
235  case X86II::MO_TPOFF:
236  RefKind = MCSymbolRefExpr::VK_TPOFF;
237  break;
238  case X86II::MO_DTPOFF:
239  RefKind = MCSymbolRefExpr::VK_DTPOFF;
240  break;
241  case X86II::MO_NTPOFF:
242  RefKind = MCSymbolRefExpr::VK_NTPOFF;
243  break;
244  case X86II::MO_GOTNTPOFF:
246  break;
247  case X86II::MO_GOTPCREL:
249  break;
250  case X86II::MO_GOT:
251  RefKind = MCSymbolRefExpr::VK_GOT;
252  break;
253  case X86II::MO_GOTOFF:
254  RefKind = MCSymbolRefExpr::VK_GOTOFF;
255  break;
256  case X86II::MO_PLT:
257  RefKind = MCSymbolRefExpr::VK_PLT;
258  break;
259  case X86II::MO_ABS8:
261  break;
264  Expr = MCSymbolRefExpr::create(Sym, Ctx);
265  // Subtract the pic base.
267  Expr, MCSymbolRefExpr::create(MF.getPICBaseSymbol(), Ctx), Ctx);
268  if (MO.isJTI()) {
269  assert(MAI.doesSetDirectiveSuppressReloc());
270  // If .set directive is supported, use it to reduce the number of
271  // relocations the assembler will generate for differences between
272  // local labels. This is only safe when the symbols are in the same
273  // section so we are restricting it to jumptable references.
274  MCSymbol *Label = Ctx.createTempSymbol();
275  AsmPrinter.OutStreamer->EmitAssignment(Label, Expr);
276  Expr = MCSymbolRefExpr::create(Label, Ctx);
277  }
278  break;
279  }
280 
281  if (!Expr)
282  Expr = MCSymbolRefExpr::create(Sym, RefKind, Ctx);
283 
284  if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
286  Expr, MCConstantExpr::create(MO.getOffset(), Ctx), Ctx);
287  return MCOperand::createExpr(Expr);
288 }
289 
290 /// Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with
291 /// a short fixed-register form.
292 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
293  unsigned ImmOp = Inst.getNumOperands() - 1;
294  assert(Inst.getOperand(0).isReg() &&
295  (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) &&
296  ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
297  Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
298  Inst.getNumOperands() == 2) &&
299  "Unexpected instruction!");
300 
301  // Check whether the destination register can be fixed.
302  unsigned Reg = Inst.getOperand(0).getReg();
303  if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
304  return;
305 
306  // If so, rewrite the instruction.
307  MCOperand Saved = Inst.getOperand(ImmOp);
308  Inst = MCInst();
309  Inst.setOpcode(Opcode);
310  Inst.addOperand(Saved);
311 }
312 
313 /// If a movsx instruction has a shorter encoding for the used register
314 /// simplify the instruction to use it instead.
315 static void SimplifyMOVSX(MCInst &Inst) {
316  unsigned NewOpcode = 0;
317  unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg();
318  switch (Inst.getOpcode()) {
319  default:
320  llvm_unreachable("Unexpected instruction!");
321  case X86::MOVSX16rr8: // movsbw %al, %ax --> cbtw
322  if (Op0 == X86::AX && Op1 == X86::AL)
323  NewOpcode = X86::CBW;
324  break;
325  case X86::MOVSX32rr16: // movswl %ax, %eax --> cwtl
326  if (Op0 == X86::EAX && Op1 == X86::AX)
327  NewOpcode = X86::CWDE;
328  break;
329  case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq
330  if (Op0 == X86::RAX && Op1 == X86::EAX)
331  NewOpcode = X86::CDQE;
332  break;
333  }
334 
335  if (NewOpcode != 0) {
336  Inst = MCInst();
337  Inst.setOpcode(NewOpcode);
338  }
339 }
340 
341 /// Simplify things like MOV32rm to MOV32o32a.
343  unsigned Opcode) {
344  // Don't make these simplifications in 64-bit mode; other assemblers don't
345  // perform them because they make the code larger.
346  if (Printer.getSubtarget().is64Bit())
347  return;
348 
349  bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
350  unsigned AddrBase = IsStore;
351  unsigned RegOp = IsStore ? 0 : 5;
352  unsigned AddrOp = AddrBase + 3;
353  assert(
354  Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
355  Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() &&
356  Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() &&
357  Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() &&
358  Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() &&
359  (Inst.getOperand(AddrOp).isExpr() || Inst.getOperand(AddrOp).isImm()) &&
360  "Unexpected instruction!");
361 
362  // Check whether the destination register can be fixed.
363  unsigned Reg = Inst.getOperand(RegOp).getReg();
364  if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
365  return;
366 
367  // Check whether this is an absolute address.
368  // FIXME: We know TLVP symbol refs aren't, but there should be a better way
369  // to do this here.
370  bool Absolute = true;
371  if (Inst.getOperand(AddrOp).isExpr()) {
372  const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr();
373  if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE))
374  if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
375  Absolute = false;
376  }
377 
378  if (Absolute &&
379  (Inst.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 ||
380  Inst.getOperand(AddrBase + X86::AddrScaleAmt).getImm() != 1 ||
381  Inst.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0))
382  return;
383 
384  // If so, rewrite the instruction.
385  MCOperand Saved = Inst.getOperand(AddrOp);
386  MCOperand Seg = Inst.getOperand(AddrBase + X86::AddrSegmentReg);
387  Inst = MCInst();
388  Inst.setOpcode(Opcode);
389  Inst.addOperand(Saved);
390  Inst.addOperand(Seg);
391 }
392 
393 static unsigned getRetOpcode(const X86Subtarget &Subtarget) {
394  return Subtarget.is64Bit() ? X86::RETQ : X86::RETL;
395 }
396 
398 X86MCInstLower::LowerMachineOperand(const MachineInstr *MI,
399  const MachineOperand &MO) const {
400  switch (MO.getType()) {
401  default:
402  MI->print(errs());
403  llvm_unreachable("unknown operand type");
405  // Ignore all implicit register operands.
406  if (MO.isImplicit())
407  return None;
408  return MCOperand::createReg(MO.getReg());
410  return MCOperand::createImm(MO.getImm());
416  return LowerSymbolOperand(MO, MO.getMCSymbol());
422  return LowerSymbolOperand(
425  // Ignore call clobbers.
426  return None;
427  }
428 }
429 
430 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
431  OutMI.setOpcode(MI->getOpcode());
432 
433  for (const MachineOperand &MO : MI->operands())
434  if (auto MaybeMCOp = LowerMachineOperand(MI, MO))
435  OutMI.addOperand(MaybeMCOp.getValue());
436 
437  // Handle a few special cases to eliminate operand modifiers.
438  switch (OutMI.getOpcode()) {
439  case X86::LEA64_32r:
440  case X86::LEA64r:
441  case X86::LEA16r:
442  case X86::LEA32r:
443  // LEA should have a segment register, but it must be empty.
444  assert(OutMI.getNumOperands() == 1 + X86::AddrNumOperands &&
445  "Unexpected # of LEA operands");
446  assert(OutMI.getOperand(1 + X86::AddrSegmentReg).getReg() == 0 &&
447  "LEA has segment specified!");
448  break;
449 
450  // Commute operands to get a smaller encoding by using VEX.R instead of VEX.B
451  // if one of the registers is extended, but other isn't.
452  case X86::VMOVZPQILo2PQIrr:
453  case X86::VMOVAPDrr:
454  case X86::VMOVAPDYrr:
455  case X86::VMOVAPSrr:
456  case X86::VMOVAPSYrr:
457  case X86::VMOVDQArr:
458  case X86::VMOVDQAYrr:
459  case X86::VMOVDQUrr:
460  case X86::VMOVDQUYrr:
461  case X86::VMOVUPDrr:
462  case X86::VMOVUPDYrr:
463  case X86::VMOVUPSrr:
464  case X86::VMOVUPSYrr: {
465  if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
467  unsigned NewOpc;
468  switch (OutMI.getOpcode()) {
469  default: llvm_unreachable("Invalid opcode");
470  case X86::VMOVZPQILo2PQIrr: NewOpc = X86::VMOVPQI2QIrr; break;
471  case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
472  case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
473  case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;
474  case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
475  case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;
476  case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
477  case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break;
478  case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
479  case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break;
480  case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
481  case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break;
482  case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
483  }
484  OutMI.setOpcode(NewOpc);
485  }
486  break;
487  }
488  case X86::VMOVSDrr:
489  case X86::VMOVSSrr: {
490  if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
492  unsigned NewOpc;
493  switch (OutMI.getOpcode()) {
494  default: llvm_unreachable("Invalid opcode");
495  case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break;
496  case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break;
497  }
498  OutMI.setOpcode(NewOpc);
499  }
500  break;
501  }
502 
503  // TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have register
504  // inputs modeled as normal uses instead of implicit uses. As such, truncate
505  // off all but the first operand (the callee). FIXME: Change isel.
506  case X86::TAILJMPr64:
507  case X86::TAILJMPr64_REX:
508  case X86::CALL64r:
509  case X86::CALL64pcrel32: {
510  unsigned Opcode = OutMI.getOpcode();
511  MCOperand Saved = OutMI.getOperand(0);
512  OutMI = MCInst();
513  OutMI.setOpcode(Opcode);
514  OutMI.addOperand(Saved);
515  break;
516  }
517 
518  case X86::EH_RETURN:
519  case X86::EH_RETURN64: {
520  OutMI = MCInst();
521  OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));
522  break;
523  }
524 
525  case X86::CLEANUPRET: {
526  // Replace CLEANUPRET with the appropriate RET.
527  OutMI = MCInst();
528  OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));
529  break;
530  }
531 
532  case X86::CATCHRET: {
533  // Replace CATCHRET with the appropriate RET.
534  const X86Subtarget &Subtarget = AsmPrinter.getSubtarget();
535  unsigned ReturnReg = Subtarget.is64Bit() ? X86::RAX : X86::EAX;
536  OutMI = MCInst();
537  OutMI.setOpcode(getRetOpcode(Subtarget));
538  OutMI.addOperand(MCOperand::createReg(ReturnReg));
539  break;
540  }
541 
542  // TAILJMPd, TAILJMPd64, TailJMPd_cc - Lower to the correct jump
543  // instruction.
544  {
545  unsigned Opcode;
546  case X86::TAILJMPr:
547  Opcode = X86::JMP32r;
548  goto SetTailJmpOpcode;
549  case X86::TAILJMPd:
550  case X86::TAILJMPd64:
551  Opcode = X86::JMP_1;
552  goto SetTailJmpOpcode;
553 
554  SetTailJmpOpcode:
555  MCOperand Saved = OutMI.getOperand(0);
556  OutMI = MCInst();
557  OutMI.setOpcode(Opcode);
558  OutMI.addOperand(Saved);
559  break;
560  }
561 
562  case X86::TAILJMPd_CC:
563  case X86::TAILJMPd64_CC: {
564  MCOperand Saved = OutMI.getOperand(0);
565  MCOperand Saved2 = OutMI.getOperand(1);
566  OutMI = MCInst();
567  OutMI.setOpcode(X86::JCC_1);
568  OutMI.addOperand(Saved);
569  OutMI.addOperand(Saved2);
570  break;
571  }
572 
573  case X86::DEC16r:
574  case X86::DEC32r:
575  case X86::INC16r:
576  case X86::INC32r:
577  // If we aren't in 64-bit mode we can use the 1-byte inc/dec instructions.
578  if (!AsmPrinter.getSubtarget().is64Bit()) {
579  unsigned Opcode;
580  switch (OutMI.getOpcode()) {
581  default: llvm_unreachable("Invalid opcode");
582  case X86::DEC16r: Opcode = X86::DEC16r_alt; break;
583  case X86::DEC32r: Opcode = X86::DEC32r_alt; break;
584  case X86::INC16r: Opcode = X86::INC16r_alt; break;
585  case X86::INC32r: Opcode = X86::INC32r_alt; break;
586  }
587  OutMI.setOpcode(Opcode);
588  }
589  break;
590 
591  // We don't currently select the correct instruction form for instructions
592  // which have a short %eax, etc. form. Handle this by custom lowering, for
593  // now.
594  //
595  // Note, we are currently not handling the following instructions:
596  // MOV64ao8, MOV64o8a
597  // XCHG16ar, XCHG32ar, XCHG64ar
598  case X86::MOV8mr_NOREX:
599  case X86::MOV8mr:
600  case X86::MOV8rm_NOREX:
601  case X86::MOV8rm:
602  case X86::MOV16mr:
603  case X86::MOV16rm:
604  case X86::MOV32mr:
605  case X86::MOV32rm: {
606  unsigned NewOpc;
607  switch (OutMI.getOpcode()) {
608  default: llvm_unreachable("Invalid opcode");
609  case X86::MOV8mr_NOREX:
610  case X86::MOV8mr: NewOpc = X86::MOV8o32a; break;
611  case X86::MOV8rm_NOREX:
612  case X86::MOV8rm: NewOpc = X86::MOV8ao32; break;
613  case X86::MOV16mr: NewOpc = X86::MOV16o32a; break;
614  case X86::MOV16rm: NewOpc = X86::MOV16ao32; break;
615  case X86::MOV32mr: NewOpc = X86::MOV32o32a; break;
616  case X86::MOV32rm: NewOpc = X86::MOV32ao32; break;
617  }
618  SimplifyShortMoveForm(AsmPrinter, OutMI, NewOpc);
619  break;
620  }
621 
622  case X86::ADC8ri: case X86::ADC16ri: case X86::ADC32ri: case X86::ADC64ri32:
623  case X86::ADD8ri: case X86::ADD16ri: case X86::ADD32ri: case X86::ADD64ri32:
624  case X86::AND8ri: case X86::AND16ri: case X86::AND32ri: case X86::AND64ri32:
625  case X86::CMP8ri: case X86::CMP16ri: case X86::CMP32ri: case X86::CMP64ri32:
626  case X86::OR8ri: case X86::OR16ri: case X86::OR32ri: case X86::OR64ri32:
627  case X86::SBB8ri: case X86::SBB16ri: case X86::SBB32ri: case X86::SBB64ri32:
628  case X86::SUB8ri: case X86::SUB16ri: case X86::SUB32ri: case X86::SUB64ri32:
629  case X86::TEST8ri:case X86::TEST16ri:case X86::TEST32ri:case X86::TEST64ri32:
630  case X86::XOR8ri: case X86::XOR16ri: case X86::XOR32ri: case X86::XOR64ri32: {
631  unsigned NewOpc;
632  switch (OutMI.getOpcode()) {
633  default: llvm_unreachable("Invalid opcode");
634  case X86::ADC8ri: NewOpc = X86::ADC8i8; break;
635  case X86::ADC16ri: NewOpc = X86::ADC16i16; break;
636  case X86::ADC32ri: NewOpc = X86::ADC32i32; break;
637  case X86::ADC64ri32: NewOpc = X86::ADC64i32; break;
638  case X86::ADD8ri: NewOpc = X86::ADD8i8; break;
639  case X86::ADD16ri: NewOpc = X86::ADD16i16; break;
640  case X86::ADD32ri: NewOpc = X86::ADD32i32; break;
641  case X86::ADD64ri32: NewOpc = X86::ADD64i32; break;
642  case X86::AND8ri: NewOpc = X86::AND8i8; break;
643  case X86::AND16ri: NewOpc = X86::AND16i16; break;
644  case X86::AND32ri: NewOpc = X86::AND32i32; break;
645  case X86::AND64ri32: NewOpc = X86::AND64i32; break;
646  case X86::CMP8ri: NewOpc = X86::CMP8i8; break;
647  case X86::CMP16ri: NewOpc = X86::CMP16i16; break;
648  case X86::CMP32ri: NewOpc = X86::CMP32i32; break;
649  case X86::CMP64ri32: NewOpc = X86::CMP64i32; break;
650  case X86::OR8ri: NewOpc = X86::OR8i8; break;
651  case X86::OR16ri: NewOpc = X86::OR16i16; break;
652  case X86::OR32ri: NewOpc = X86::OR32i32; break;
653  case X86::OR64ri32: NewOpc = X86::OR64i32; break;
654  case X86::SBB8ri: NewOpc = X86::SBB8i8; break;
655  case X86::SBB16ri: NewOpc = X86::SBB16i16; break;
656  case X86::SBB32ri: NewOpc = X86::SBB32i32; break;
657  case X86::SBB64ri32: NewOpc = X86::SBB64i32; break;
658  case X86::SUB8ri: NewOpc = X86::SUB8i8; break;
659  case X86::SUB16ri: NewOpc = X86::SUB16i16; break;
660  case X86::SUB32ri: NewOpc = X86::SUB32i32; break;
661  case X86::SUB64ri32: NewOpc = X86::SUB64i32; break;
662  case X86::TEST8ri: NewOpc = X86::TEST8i8; break;
663  case X86::TEST16ri: NewOpc = X86::TEST16i16; break;
664  case X86::TEST32ri: NewOpc = X86::TEST32i32; break;
665  case X86::TEST64ri32: NewOpc = X86::TEST64i32; break;
666  case X86::XOR8ri: NewOpc = X86::XOR8i8; break;
667  case X86::XOR16ri: NewOpc = X86::XOR16i16; break;
668  case X86::XOR32ri: NewOpc = X86::XOR32i32; break;
669  case X86::XOR64ri32: NewOpc = X86::XOR64i32; break;
670  }
671  SimplifyShortImmForm(OutMI, NewOpc);
672  break;
673  }
674 
675  // Try to shrink some forms of movsx.
676  case X86::MOVSX16rr8:
677  case X86::MOVSX32rr16:
678  case X86::MOVSX64rr32:
679  SimplifyMOVSX(OutMI);
680  break;
681  }
682 }
683 
684 void X86AsmPrinter::LowerTlsAddr(X86MCInstLower &MCInstLowering,
685  const MachineInstr &MI) {
686  bool Is64Bits = MI.getOpcode() == X86::TLS_addr64 ||
687  MI.getOpcode() == X86::TLS_base_addr64;
688  MCContext &Ctx = OutStreamer->getContext();
689 
691  switch (MI.getOpcode()) {
692  case X86::TLS_addr32:
693  case X86::TLS_addr64:
695  break;
696  case X86::TLS_base_addr32:
698  break;
699  case X86::TLS_base_addr64:
701  break;
702  default:
703  llvm_unreachable("unexpected opcode");
704  }
705 
707  MCInstLowering.GetSymbolFromOperand(MI.getOperand(3)), SRVK, Ctx);
708  bool UseGot = MMI->getModule()->getRtLibUseGOT();
709 
710  if (Is64Bits) {
711  bool NeedsPadding = SRVK == MCSymbolRefExpr::VK_TLSGD;
712  if (NeedsPadding)
713  EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
714  EmitAndCountInstruction(MCInstBuilder(X86::LEA64r)
715  .addReg(X86::RDI)
716  .addReg(X86::RIP)
717  .addImm(1)
718  .addReg(0)
719  .addExpr(Sym)
720  .addReg(0));
721  const MCSymbol *TlsGetAddr = Ctx.getOrCreateSymbol("__tls_get_addr");
722  if (NeedsPadding) {
723  if (!UseGot)
724  EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
725  EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
726  EmitAndCountInstruction(MCInstBuilder(X86::REX64_PREFIX));
727  }
728  if (UseGot) {
729  const MCExpr *Expr = MCSymbolRefExpr::create(
730  TlsGetAddr, MCSymbolRefExpr::VK_GOTPCREL, Ctx);
731  EmitAndCountInstruction(MCInstBuilder(X86::CALL64m)
732  .addReg(X86::RIP)
733  .addImm(1)
734  .addReg(0)
735  .addExpr(Expr)
736  .addReg(0));
737  } else {
738  EmitAndCountInstruction(
739  MCInstBuilder(X86::CALL64pcrel32)
740  .addExpr(MCSymbolRefExpr::create(TlsGetAddr,
741  MCSymbolRefExpr::VK_PLT, Ctx)));
742  }
743  } else {
744  if (SRVK == MCSymbolRefExpr::VK_TLSGD && !UseGot) {
745  EmitAndCountInstruction(MCInstBuilder(X86::LEA32r)
746  .addReg(X86::EAX)
747  .addReg(0)
748  .addImm(1)
749  .addReg(X86::EBX)
750  .addExpr(Sym)
751  .addReg(0));
752  } else {
753  EmitAndCountInstruction(MCInstBuilder(X86::LEA32r)
754  .addReg(X86::EAX)
755  .addReg(X86::EBX)
756  .addImm(1)
757  .addReg(0)
758  .addExpr(Sym)
759  .addReg(0));
760  }
761 
762  const MCSymbol *TlsGetAddr = Ctx.getOrCreateSymbol("___tls_get_addr");
763  if (UseGot) {
764  const MCExpr *Expr =
766  EmitAndCountInstruction(MCInstBuilder(X86::CALL32m)
767  .addReg(X86::EBX)
768  .addImm(1)
769  .addReg(0)
770  .addExpr(Expr)
771  .addReg(0));
772  } else {
773  EmitAndCountInstruction(
774  MCInstBuilder(X86::CALLpcrel32)
775  .addExpr(MCSymbolRefExpr::create(TlsGetAddr,
776  MCSymbolRefExpr::VK_PLT, Ctx)));
777  }
778  }
779 }
780 
781 /// Emit the largest nop instruction smaller than or equal to \p NumBytes
782 /// bytes. Return the size of nop emitted.
783 static unsigned EmitNop(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
784  const MCSubtargetInfo &STI) {
785  // This works only for 64bit. For 32bit we have to do additional checking if
786  // the CPU supports multi-byte nops.
787  assert(Is64Bit && "EmitNops only supports X86-64");
788 
789  unsigned NopSize;
790  unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;
791  IndexReg = Displacement = SegmentReg = 0;
792  BaseReg = X86::RAX;
793  ScaleVal = 1;
794  switch (NumBytes) {
795  case 0:
796  llvm_unreachable("Zero nops?");
797  break;
798  case 1:
799  NopSize = 1;
800  Opc = X86::NOOP;
801  break;
802  case 2:
803  NopSize = 2;
804  Opc = X86::XCHG16ar;
805  break;
806  case 3:
807  NopSize = 3;
808  Opc = X86::NOOPL;
809  break;
810  case 4:
811  NopSize = 4;
812  Opc = X86::NOOPL;
813  Displacement = 8;
814  break;
815  case 5:
816  NopSize = 5;
817  Opc = X86::NOOPL;
818  Displacement = 8;
819  IndexReg = X86::RAX;
820  break;
821  case 6:
822  NopSize = 6;
823  Opc = X86::NOOPW;
824  Displacement = 8;
825  IndexReg = X86::RAX;
826  break;
827  case 7:
828  NopSize = 7;
829  Opc = X86::NOOPL;
830  Displacement = 512;
831  break;
832  case 8:
833  NopSize = 8;
834  Opc = X86::NOOPL;
835  Displacement = 512;
836  IndexReg = X86::RAX;
837  break;
838  case 9:
839  NopSize = 9;
840  Opc = X86::NOOPW;
841  Displacement = 512;
842  IndexReg = X86::RAX;
843  break;
844  default:
845  NopSize = 10;
846  Opc = X86::NOOPW;
847  Displacement = 512;
848  IndexReg = X86::RAX;
849  SegmentReg = X86::CS;
850  break;
851  }
852 
853  unsigned NumPrefixes = std::min(NumBytes - NopSize, 5U);
854  NopSize += NumPrefixes;
855  for (unsigned i = 0; i != NumPrefixes; ++i)
856  OS.EmitBytes("\x66");
857 
858  switch (Opc) {
859  default: llvm_unreachable("Unexpected opcode");
860  case X86::NOOP:
861  OS.EmitInstruction(MCInstBuilder(Opc), STI);
862  break;
863  case X86::XCHG16ar:
864  OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX).addReg(X86::AX), STI);
865  break;
866  case X86::NOOPL:
867  case X86::NOOPW:
869  .addReg(BaseReg)
870  .addImm(ScaleVal)
871  .addReg(IndexReg)
872  .addImm(Displacement)
873  .addReg(SegmentReg),
874  STI);
875  break;
876  }
877  assert(NopSize <= NumBytes && "We overemitted?");
878  return NopSize;
879 }
880 
881 /// Emit the optimal amount of multi-byte nops on X86.
882 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
883  const MCSubtargetInfo &STI) {
884  unsigned NopsToEmit = NumBytes;
885  (void)NopsToEmit;
886  while (NumBytes) {
887  NumBytes -= EmitNop(OS, NumBytes, Is64Bit, STI);
888  assert(NopsToEmit >= NumBytes && "Emitted more than I asked for!");
889  }
890 }
891 
892 void X86AsmPrinter::LowerSTATEPOINT(const MachineInstr &MI,
893  X86MCInstLower &MCIL) {
894  assert(Subtarget->is64Bit() && "Statepoint currently only supports X86-64");
895 
896  StatepointOpers SOpers(&MI);
897  if (unsigned PatchBytes = SOpers.getNumPatchBytes()) {
898  EmitNops(*OutStreamer, PatchBytes, Subtarget->is64Bit(),
899  getSubtargetInfo());
900  } else {
901  // Lower call target and choose correct opcode
902  const MachineOperand &CallTarget = SOpers.getCallTarget();
903  MCOperand CallTargetMCOp;
904  unsigned CallOpcode;
905  switch (CallTarget.getType()) {
908  CallTargetMCOp = MCIL.LowerSymbolOperand(
909  CallTarget, MCIL.GetSymbolFromOperand(CallTarget));
910  CallOpcode = X86::CALL64pcrel32;
911  // Currently, we only support relative addressing with statepoints.
912  // Otherwise, we'll need a scratch register to hold the target
913  // address. You'll fail asserts during load & relocation if this
914  // symbol is to far away. (TODO: support non-relative addressing)
915  break;
917  CallTargetMCOp = MCOperand::createImm(CallTarget.getImm());
918  CallOpcode = X86::CALL64pcrel32;
919  // Currently, we only support relative addressing with statepoints.
920  // Otherwise, we'll need a scratch register to hold the target
921  // immediate. You'll fail asserts during load & relocation if this
922  // address is to far away. (TODO: support non-relative addressing)
923  break;
925  // FIXME: Add retpoline support and remove this.
926  if (Subtarget->useRetpolineIndirectCalls())
927  report_fatal_error("Lowering register statepoints with retpoline not "
928  "yet implemented.");
929  CallTargetMCOp = MCOperand::createReg(CallTarget.getReg());
930  CallOpcode = X86::CALL64r;
931  break;
932  default:
933  llvm_unreachable("Unsupported operand type in statepoint call target");
934  break;
935  }
936 
937  // Emit call
939  CallInst.setOpcode(CallOpcode);
940  CallInst.addOperand(CallTargetMCOp);
941  OutStreamer->EmitInstruction(CallInst, getSubtargetInfo());
942  }
943 
944  // Record our statepoint node in the same section used by STACKMAP
945  // and PATCHPOINT
946  SM.recordStatepoint(MI);
947 }
948 
949 void X86AsmPrinter::LowerFAULTING_OP(const MachineInstr &FaultingMI,
950  X86MCInstLower &MCIL) {
951  // FAULTING_LOAD_OP <def>, <faltinf type>, <MBB handler>,
952  // <opcode>, <operands>
953 
954  unsigned DefRegister = FaultingMI.getOperand(0).getReg();
956  static_cast<FaultMaps::FaultKind>(FaultingMI.getOperand(1).getImm());
957  MCSymbol *HandlerLabel = FaultingMI.getOperand(2).getMBB()->getSymbol();
958  unsigned Opcode = FaultingMI.getOperand(3).getImm();
959  unsigned OperandsBeginIdx = 4;
960 
961  assert(FK < FaultMaps::FaultKindMax && "Invalid Faulting Kind!");
962  FM.recordFaultingOp(FK, HandlerLabel);
963 
964  MCInst MI;
965  MI.setOpcode(Opcode);
966 
967  if (DefRegister != X86::NoRegister)
968  MI.addOperand(MCOperand::createReg(DefRegister));
969 
970  for (auto I = FaultingMI.operands_begin() + OperandsBeginIdx,
971  E = FaultingMI.operands_end();
972  I != E; ++I)
973  if (auto MaybeOperand = MCIL.LowerMachineOperand(&FaultingMI, *I))
974  MI.addOperand(MaybeOperand.getValue());
975 
976  OutStreamer->AddComment("on-fault: " + HandlerLabel->getName());
977  OutStreamer->EmitInstruction(MI, getSubtargetInfo());
978 }
979 
980 void X86AsmPrinter::LowerFENTRY_CALL(const MachineInstr &MI,
981  X86MCInstLower &MCIL) {
982  bool Is64Bits = Subtarget->is64Bit();
983  MCContext &Ctx = OutStreamer->getContext();
984  MCSymbol *fentry = Ctx.getOrCreateSymbol("__fentry__");
985  const MCSymbolRefExpr *Op =
987 
988  EmitAndCountInstruction(
989  MCInstBuilder(Is64Bits ? X86::CALL64pcrel32 : X86::CALLpcrel32)
990  .addExpr(Op));
991 }
992 
993 void X86AsmPrinter::LowerPATCHABLE_OP(const MachineInstr &MI,
994  X86MCInstLower &MCIL) {
995  // PATCHABLE_OP minsize, opcode, operands
996 
997  unsigned MinSize = MI.getOperand(0).getImm();
998  unsigned Opcode = MI.getOperand(1).getImm();
999 
1000  MCInst MCI;
1001  MCI.setOpcode(Opcode);
1002  for (auto &MO : make_range(MI.operands_begin() + 2, MI.operands_end()))
1003  if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO))
1004  MCI.addOperand(MaybeOperand.getValue());
1005 
1006  SmallString<256> Code;
1008  raw_svector_ostream VecOS(Code);
1009  CodeEmitter->encodeInstruction(MCI, VecOS, Fixups, getSubtargetInfo());
1010 
1011  if (Code.size() < MinSize) {
1012  if (MinSize == 2 && Opcode == X86::PUSH64r) {
1013  // This is an optimization that lets us get away without emitting a nop in
1014  // many cases.
1015  //
1016  // NB! In some cases the encoding for PUSH64r (e.g. PUSH64r %r9) takes two
1017  // bytes too, so the check on MinSize is important.
1018  MCI.setOpcode(X86::PUSH64rmr);
1019  } else {
1020  unsigned NopSize = EmitNop(*OutStreamer, MinSize, Subtarget->is64Bit(),
1021  getSubtargetInfo());
1022  assert(NopSize == MinSize && "Could not implement MinSize!");
1023  (void)NopSize;
1024  }
1025  }
1026 
1027  OutStreamer->EmitInstruction(MCI, getSubtargetInfo());
1028 }
1029 
1030 // Lower a stackmap of the form:
1031 // <id>, <shadowBytes>, ...
1032 void X86AsmPrinter::LowerSTACKMAP(const MachineInstr &MI) {
1033  SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
1034  SM.recordStackMap(MI);
1035  unsigned NumShadowBytes = MI.getOperand(1).getImm();
1036  SMShadowTracker.reset(NumShadowBytes);
1037 }
1038 
1039 // Lower a patchpoint of the form:
1040 // [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ...
1041 void X86AsmPrinter::LowerPATCHPOINT(const MachineInstr &MI,
1042  X86MCInstLower &MCIL) {
1043  assert(Subtarget->is64Bit() && "Patchpoint currently only supports X86-64");
1044 
1045  SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
1046 
1047  SM.recordPatchPoint(MI);
1048 
1049  PatchPointOpers opers(&MI);
1050  unsigned ScratchIdx = opers.getNextScratchIdx();
1051  unsigned EncodedBytes = 0;
1052  const MachineOperand &CalleeMO = opers.getCallTarget();
1053 
1054  // Check for null target. If target is non-null (i.e. is non-zero or is
1055  // symbolic) then emit a call.
1056  if (!(CalleeMO.isImm() && !CalleeMO.getImm())) {
1057  MCOperand CalleeMCOp;
1058  switch (CalleeMO.getType()) {
1059  default:
1060  /// FIXME: Add a verifier check for bad callee types.
1061  llvm_unreachable("Unrecognized callee operand type.");
1063  if (CalleeMO.getImm())
1064  CalleeMCOp = MCOperand::createImm(CalleeMO.getImm());
1065  break;
1068  CalleeMCOp = MCIL.LowerSymbolOperand(CalleeMO,
1069  MCIL.GetSymbolFromOperand(CalleeMO));
1070  break;
1071  }
1072 
1073  // Emit MOV to materialize the target address and the CALL to target.
1074  // This is encoded with 12-13 bytes, depending on which register is used.
1075  unsigned ScratchReg = MI.getOperand(ScratchIdx).getReg();
1076  if (X86II::isX86_64ExtendedReg(ScratchReg))
1077  EncodedBytes = 13;
1078  else
1079  EncodedBytes = 12;
1080 
1081  EmitAndCountInstruction(
1082  MCInstBuilder(X86::MOV64ri).addReg(ScratchReg).addOperand(CalleeMCOp));
1083  // FIXME: Add retpoline support and remove this.
1084  if (Subtarget->useRetpolineIndirectCalls())
1086  "Lowering patchpoint with retpoline not yet implemented.");
1087  EmitAndCountInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg));
1088  }
1089 
1090  // Emit padding.
1091  unsigned NumBytes = opers.getNumPatchBytes();
1092  assert(NumBytes >= EncodedBytes &&
1093  "Patchpoint can't request size less than the length of a call.");
1094 
1095  EmitNops(*OutStreamer, NumBytes - EncodedBytes, Subtarget->is64Bit(),
1096  getSubtargetInfo());
1097 }
1098 
1099 void X86AsmPrinter::LowerPATCHABLE_EVENT_CALL(const MachineInstr &MI,
1100  X86MCInstLower &MCIL) {
1101  assert(Subtarget->is64Bit() && "XRay custom events only supports X86-64");
1102 
1103  // We want to emit the following pattern, which follows the x86 calling
1104  // convention to prepare for the trampoline call to be patched in.
1105  //
1106  // .p2align 1, ...
1107  // .Lxray_event_sled_N:
1108  // jmp +N // jump across the instrumentation sled
1109  // ... // set up arguments in register
1110  // callq __xray_CustomEvent@plt // force dependency to symbol
1111  // ...
1112  // <jump here>
1113  //
1114  // After patching, it would look something like:
1115  //
1116  // nopw (2-byte nop)
1117  // ...
1118  // callq __xrayCustomEvent // already lowered
1119  // ...
1120  //
1121  // ---
1122  // First we emit the label and the jump.
1123  auto CurSled = OutContext.createTempSymbol("xray_event_sled_", true);
1124  OutStreamer->AddComment("# XRay Custom Event Log");
1125  OutStreamer->EmitCodeAlignment(2);
1126  OutStreamer->EmitLabel(CurSled);
1127 
1128  // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as
1129  // an operand (computed as an offset from the jmp instruction).
1130  // FIXME: Find another less hacky way do force the relative jump.
1131  OutStreamer->EmitBinaryData("\xeb\x0f");
1132 
1133  // The default C calling convention will place two arguments into %rcx and
1134  // %rdx -- so we only work with those.
1135  unsigned DestRegs[] = {X86::RDI, X86::RSI};
1136  bool UsedMask[] = {false, false};
1137  // Filled out in loop.
1138  unsigned SrcRegs[] = {0, 0};
1139 
1140  // Then we put the operands in the %rdi and %rsi registers. We spill the
1141  // values in the register before we clobber them, and mark them as used in
1142  // UsedMask. In case the arguments are already in the correct register, we use
1143  // emit nops appropriately sized to keep the sled the same size in every
1144  // situation.
1145  for (unsigned I = 0; I < MI.getNumOperands(); ++I)
1146  if (auto Op = MCIL.LowerMachineOperand(&MI, MI.getOperand(I))) {
1147  assert(Op->isReg() && "Only support arguments in registers");
1148  SrcRegs[I] = Op->getReg();
1149  if (SrcRegs[I] != DestRegs[I]) {
1150  UsedMask[I] = true;
1151  EmitAndCountInstruction(
1152  MCInstBuilder(X86::PUSH64r).addReg(DestRegs[I]));
1153  } else {
1154  EmitNops(*OutStreamer, 4, Subtarget->is64Bit(), getSubtargetInfo());
1155  }
1156  }
1157 
1158  // Now that the register values are stashed, mov arguments into place.
1159  for (unsigned I = 0; I < MI.getNumOperands(); ++I)
1160  if (SrcRegs[I] != DestRegs[I])
1161  EmitAndCountInstruction(
1162  MCInstBuilder(X86::MOV64rr).addReg(DestRegs[I]).addReg(SrcRegs[I]));
1163 
1164  // We emit a hard dependency on the __xray_CustomEvent symbol, which is the
1165  // name of the trampoline to be implemented by the XRay runtime.
1166  auto TSym = OutContext.getOrCreateSymbol("__xray_CustomEvent");
1168  if (isPositionIndependent())
1170 
1171  // Emit the call instruction.
1172  EmitAndCountInstruction(MCInstBuilder(X86::CALL64pcrel32)
1173  .addOperand(MCIL.LowerSymbolOperand(TOp, TSym)));
1174 
1175  // Restore caller-saved and used registers.
1176  for (unsigned I = sizeof UsedMask; I-- > 0;)
1177  if (UsedMask[I])
1178  EmitAndCountInstruction(MCInstBuilder(X86::POP64r).addReg(DestRegs[I]));
1179  else
1180  EmitNops(*OutStreamer, 1, Subtarget->is64Bit(), getSubtargetInfo());
1181 
1182  OutStreamer->AddComment("xray custom event end.");
1183 
1184  // Record the sled version. Older versions of this sled were spelled
1185  // differently, so we let the runtime handle the different offsets we're
1186  // using.
1187  recordSled(CurSled, MI, SledKind::CUSTOM_EVENT, 1);
1188 }
1189 
1190 void X86AsmPrinter::LowerPATCHABLE_TYPED_EVENT_CALL(const MachineInstr &MI,
1191  X86MCInstLower &MCIL) {
1192  assert(Subtarget->is64Bit() && "XRay typed events only supports X86-64");
1193 
1194  // We want to emit the following pattern, which follows the x86 calling
1195  // convention to prepare for the trampoline call to be patched in.
1196  //
1197  // .p2align 1, ...
1198  // .Lxray_event_sled_N:
1199  // jmp +N // jump across the instrumentation sled
1200  // ... // set up arguments in register
1201  // callq __xray_TypedEvent@plt // force dependency to symbol
1202  // ...
1203  // <jump here>
1204  //
1205  // After patching, it would look something like:
1206  //
1207  // nopw (2-byte nop)
1208  // ...
1209  // callq __xrayTypedEvent // already lowered
1210  // ...
1211  //
1212  // ---
1213  // First we emit the label and the jump.
1214  auto CurSled = OutContext.createTempSymbol("xray_typed_event_sled_", true);
1215  OutStreamer->AddComment("# XRay Typed Event Log");
1216  OutStreamer->EmitCodeAlignment(2);
1217  OutStreamer->EmitLabel(CurSled);
1218 
1219  // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as
1220  // an operand (computed as an offset from the jmp instruction).
1221  // FIXME: Find another less hacky way do force the relative jump.
1222  OutStreamer->EmitBinaryData("\xeb\x14");
1223 
1224  // An x86-64 convention may place three arguments into %rcx, %rdx, and R8,
1225  // so we'll work with those. Or we may be called via SystemV, in which case
1226  // we don't have to do any translation.
1227  unsigned DestRegs[] = {X86::RDI, X86::RSI, X86::RDX};
1228  bool UsedMask[] = {false, false, false};
1229 
1230  // Will fill out src regs in the loop.
1231  unsigned SrcRegs[] = {0, 0, 0};
1232 
1233  // Then we put the operands in the SystemV registers. We spill the values in
1234  // the registers before we clobber them, and mark them as used in UsedMask.
1235  // In case the arguments are already in the correct register, we emit nops
1236  // appropriately sized to keep the sled the same size in every situation.
1237  for (unsigned I = 0; I < MI.getNumOperands(); ++I)
1238  if (auto Op = MCIL.LowerMachineOperand(&MI, MI.getOperand(I))) {
1239  // TODO: Is register only support adequate?
1240  assert(Op->isReg() && "Only supports arguments in registers");
1241  SrcRegs[I] = Op->getReg();
1242  if (SrcRegs[I] != DestRegs[I]) {
1243  UsedMask[I] = true;
1244  EmitAndCountInstruction(
1245  MCInstBuilder(X86::PUSH64r).addReg(DestRegs[I]));
1246  } else {
1247  EmitNops(*OutStreamer, 4, Subtarget->is64Bit(), getSubtargetInfo());
1248  }
1249  }
1250 
1251  // In the above loop we only stash all of the destination registers or emit
1252  // nops if the arguments are already in the right place. Doing the actually
1253  // moving is postponed until after all the registers are stashed so nothing
1254  // is clobbers. We've already added nops to account for the size of mov and
1255  // push if the register is in the right place, so we only have to worry about
1256  // emitting movs.
1257  for (unsigned I = 0; I < MI.getNumOperands(); ++I)
1258  if (UsedMask[I])
1259  EmitAndCountInstruction(
1260  MCInstBuilder(X86::MOV64rr).addReg(DestRegs[I]).addReg(SrcRegs[I]));
1261 
1262  // We emit a hard dependency on the __xray_TypedEvent symbol, which is the
1263  // name of the trampoline to be implemented by the XRay runtime.
1264  auto TSym = OutContext.getOrCreateSymbol("__xray_TypedEvent");
1266  if (isPositionIndependent())
1268 
1269  // Emit the call instruction.
1270  EmitAndCountInstruction(MCInstBuilder(X86::CALL64pcrel32)
1271  .addOperand(MCIL.LowerSymbolOperand(TOp, TSym)));
1272 
1273  // Restore caller-saved and used registers.
1274  for (unsigned I = sizeof UsedMask; I-- > 0;)
1275  if (UsedMask[I])
1276  EmitAndCountInstruction(MCInstBuilder(X86::POP64r).addReg(DestRegs[I]));
1277  else
1278  EmitNops(*OutStreamer, 1, Subtarget->is64Bit(), getSubtargetInfo());
1279 
1280  OutStreamer->AddComment("xray typed event end.");
1281 
1282  // Record the sled version.
1283  recordSled(CurSled, MI, SledKind::TYPED_EVENT, 0);
1284 }
1285 
1286 void X86AsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI,
1287  X86MCInstLower &MCIL) {
1288  // We want to emit the following pattern:
1289  //
1290  // .p2align 1, ...
1291  // .Lxray_sled_N:
1292  // jmp .tmpN
1293  // # 9 bytes worth of noops
1294  //
1295  // We need the 9 bytes because at runtime, we'd be patching over the full 11
1296  // bytes with the following pattern:
1297  //
1298  // mov %r10, <function id, 32-bit> // 6 bytes
1299  // call <relative offset, 32-bits> // 5 bytes
1300  //
1301  auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
1302  OutStreamer->EmitCodeAlignment(2);
1303  OutStreamer->EmitLabel(CurSled);
1304 
1305  // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as
1306  // an operand (computed as an offset from the jmp instruction).
1307  // FIXME: Find another less hacky way do force the relative jump.
1308  OutStreamer->EmitBytes("\xeb\x09");
1309  EmitNops(*OutStreamer, 9, Subtarget->is64Bit(), getSubtargetInfo());
1310  recordSled(CurSled, MI, SledKind::FUNCTION_ENTER);
1311 }
1312 
1313 void X86AsmPrinter::LowerPATCHABLE_RET(const MachineInstr &MI,
1314  X86MCInstLower &MCIL) {
1315  // Since PATCHABLE_RET takes the opcode of the return statement as an
1316  // argument, we use that to emit the correct form of the RET that we want.
1317  // i.e. when we see this:
1318  //
1319  // PATCHABLE_RET X86::RET ...
1320  //
1321  // We should emit the RET followed by sleds.
1322  //
1323  // .p2align 1, ...
1324  // .Lxray_sled_N:
1325  // ret # or equivalent instruction
1326  // # 10 bytes worth of noops
1327  //
1328  // This just makes sure that the alignment for the next instruction is 2.
1329  auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
1330  OutStreamer->EmitCodeAlignment(2);
1331  OutStreamer->EmitLabel(CurSled);
1332  unsigned OpCode = MI.getOperand(0).getImm();
1333  MCInst Ret;
1334  Ret.setOpcode(OpCode);
1335  for (auto &MO : make_range(MI.operands_begin() + 1, MI.operands_end()))
1336  if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO))
1337  Ret.addOperand(MaybeOperand.getValue());
1338  OutStreamer->EmitInstruction(Ret, getSubtargetInfo());
1339  EmitNops(*OutStreamer, 10, Subtarget->is64Bit(), getSubtargetInfo());
1340  recordSled(CurSled, MI, SledKind::FUNCTION_EXIT);
1341 }
1342 
1343 void X86AsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI,
1344  X86MCInstLower &MCIL) {
1345  // Like PATCHABLE_RET, we have the actual instruction in the operands to this
1346  // instruction so we lower that particular instruction and its operands.
1347  // Unlike PATCHABLE_RET though, we put the sled before the JMP, much like how
1348  // we do it for PATCHABLE_FUNCTION_ENTER. The sled should be very similar to
1349  // the PATCHABLE_FUNCTION_ENTER case, followed by the lowering of the actual
1350  // tail call much like how we have it in PATCHABLE_RET.
1351  auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
1352  OutStreamer->EmitCodeAlignment(2);
1353  OutStreamer->EmitLabel(CurSled);
1355 
1356  // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as
1357  // an operand (computed as an offset from the jmp instruction).
1358  // FIXME: Find another less hacky way do force the relative jump.
1359  OutStreamer->EmitBytes("\xeb\x09");
1360  EmitNops(*OutStreamer, 9, Subtarget->is64Bit(), getSubtargetInfo());
1361  OutStreamer->EmitLabel(Target);
1362  recordSled(CurSled, MI, SledKind::TAIL_CALL);
1363 
1364  unsigned OpCode = MI.getOperand(0).getImm();
1365  MCInst TC;
1366  TC.setOpcode(OpCode);
1367 
1368  // Before emitting the instruction, add a comment to indicate that this is
1369  // indeed a tail call.
1370  OutStreamer->AddComment("TAILCALL");
1371  for (auto &MO : make_range(MI.operands_begin() + 1, MI.operands_end()))
1372  if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO))
1373  TC.addOperand(MaybeOperand.getValue());
1374  OutStreamer->EmitInstruction(TC, getSubtargetInfo());
1375 }
1376 
1377 // Returns instruction preceding MBBI in MachineFunction.
1378 // If MBBI is the first instruction of the first basic block, returns null.
1381  const MachineBasicBlock *MBB = MBBI->getParent();
1382  while (MBBI == MBB->begin()) {
1383  if (MBB == &MBB->getParent()->front())
1385  MBB = MBB->getPrevNode();
1386  MBBI = MBB->end();
1387  }
1388  --MBBI;
1389  return MBBI;
1390 }
1391 
1393  const MachineOperand &Op) {
1394  if (!Op.isCPI() || Op.getOffset() != 0)
1395  return nullptr;
1396 
1399  const MachineConstantPoolEntry &ConstantEntry = Constants[Op.getIndex()];
1400 
1401  // Bail if this is a machine constant pool entry, we won't be able to dig out
1402  // anything useful.
1403  if (ConstantEntry.isMachineConstantPoolEntry())
1404  return nullptr;
1405 
1406  const Constant *C = ConstantEntry.Val.ConstVal;
1407  assert((!C || ConstantEntry.getType() == C->getType()) &&
1408  "Expected a constant of the same type!");
1409  return C;
1410 }
1411 
1412 static std::string getShuffleComment(const MachineInstr *MI, unsigned SrcOp1Idx,
1413  unsigned SrcOp2Idx, ArrayRef<int> Mask) {
1414  std::string Comment;
1415 
1416  // Compute the name for a register. This is really goofy because we have
1417  // multiple instruction printers that could (in theory) use different
1418  // names. Fortunately most people use the ATT style (outside of Windows)
1419  // and they actually agree on register naming here. Ultimately, this is
1420  // a comment, and so its OK if it isn't perfect.
1421  auto GetRegisterName = [](unsigned RegNum) -> StringRef {
1422  return X86ATTInstPrinter::getRegisterName(RegNum);
1423  };
1424 
1425  const MachineOperand &DstOp = MI->getOperand(0);
1426  const MachineOperand &SrcOp1 = MI->getOperand(SrcOp1Idx);
1427  const MachineOperand &SrcOp2 = MI->getOperand(SrcOp2Idx);
1428 
1429  StringRef DstName = DstOp.isReg() ? GetRegisterName(DstOp.getReg()) : "mem";
1430  StringRef Src1Name =
1431  SrcOp1.isReg() ? GetRegisterName(SrcOp1.getReg()) : "mem";
1432  StringRef Src2Name =
1433  SrcOp2.isReg() ? GetRegisterName(SrcOp2.getReg()) : "mem";
1434 
1435  // One source operand, fix the mask to print all elements in one span.
1436  SmallVector<int, 8> ShuffleMask(Mask.begin(), Mask.end());
1437  if (Src1Name == Src2Name)
1438  for (int i = 0, e = ShuffleMask.size(); i != e; ++i)
1439  if (ShuffleMask[i] >= e)
1440  ShuffleMask[i] -= e;
1441 
1442  raw_string_ostream CS(Comment);
1443  CS << DstName;
1444 
1445  // Handle AVX512 MASK/MASXZ write mask comments.
1446  // MASK: zmmX {%kY}
1447  // MASKZ: zmmX {%kY} {z}
1448  if (SrcOp1Idx > 1) {
1449  assert((SrcOp1Idx == 2 || SrcOp1Idx == 3) && "Unexpected writemask");
1450 
1451  const MachineOperand &WriteMaskOp = MI->getOperand(SrcOp1Idx - 1);
1452  if (WriteMaskOp.isReg()) {
1453  CS << " {%" << GetRegisterName(WriteMaskOp.getReg()) << "}";
1454 
1455  if (SrcOp1Idx == 2) {
1456  CS << " {z}";
1457  }
1458  }
1459  }
1460 
1461  CS << " = ";
1462 
1463  for (int i = 0, e = ShuffleMask.size(); i != e; ++i) {
1464  if (i != 0)
1465  CS << ",";
1466  if (ShuffleMask[i] == SM_SentinelZero) {
1467  CS << "zero";
1468  continue;
1469  }
1470 
1471  // Otherwise, it must come from src1 or src2. Print the span of elements
1472  // that comes from this src.
1473  bool isSrc1 = ShuffleMask[i] < (int)e;
1474  CS << (isSrc1 ? Src1Name : Src2Name) << '[';
1475 
1476  bool IsFirst = true;
1477  while (i != e && ShuffleMask[i] != SM_SentinelZero &&
1478  (ShuffleMask[i] < (int)e) == isSrc1) {
1479  if (!IsFirst)
1480  CS << ',';
1481  else
1482  IsFirst = false;
1483  if (ShuffleMask[i] == SM_SentinelUndef)
1484  CS << "u";
1485  else
1486  CS << ShuffleMask[i] % (int)e;
1487  ++i;
1488  }
1489  CS << ']';
1490  --i; // For loop increments element #.
1491  }
1492  CS.flush();
1493 
1494  return Comment;
1495 }
1496 
1497 static void printConstant(const APInt &Val, raw_ostream &CS) {
1498  if (Val.getBitWidth() <= 64) {
1499  CS << Val.getZExtValue();
1500  } else {
1501  // print multi-word constant as (w0,w1)
1502  CS << "(";
1503  for (int i = 0, N = Val.getNumWords(); i < N; ++i) {
1504  if (i > 0)
1505  CS << ",";
1506  CS << Val.getRawData()[i];
1507  }
1508  CS << ")";
1509  }
1510 }
1511 
1512 static void printConstant(const APFloat &Flt, raw_ostream &CS) {
1513  SmallString<32> Str;
1514  // Force scientific notation to distinquish from integers.
1515  Flt.toString(Str, 0, 0);
1516  CS << Str;
1517 }
1518 
1519 static void printConstant(const Constant *COp, raw_ostream &CS) {
1520  if (isa<UndefValue>(COp)) {
1521  CS << "u";
1522  } else if (auto *CI = dyn_cast<ConstantInt>(COp)) {
1523  printConstant(CI->getValue(), CS);
1524  } else if (auto *CF = dyn_cast<ConstantFP>(COp)) {
1525  printConstant(CF->getValueAPF(), CS);
1526  } else {
1527  CS << "?";
1528  }
1529 }
1530 
1531 void X86AsmPrinter::EmitSEHInstruction(const MachineInstr *MI) {
1532  assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?");
1533  assert(getSubtarget().isOSWindows() && "SEH_ instruction Windows only");
1534  const X86RegisterInfo *RI =
1535  MF->getSubtarget<X86Subtarget>().getRegisterInfo();
1536 
1537  // Use the .cv_fpo directives if we're emitting CodeView on 32-bit x86.
1538  if (EmitFPOData) {
1539  X86TargetStreamer *XTS =
1540  static_cast<X86TargetStreamer *>(OutStreamer->getTargetStreamer());
1541  switch (MI->getOpcode()) {
1542  case X86::SEH_PushReg:
1543  XTS->emitFPOPushReg(MI->getOperand(0).getImm());
1544  break;
1545  case X86::SEH_StackAlloc:
1546  XTS->emitFPOStackAlloc(MI->getOperand(0).getImm());
1547  break;
1548  case X86::SEH_StackAlign:
1549  XTS->emitFPOStackAlign(MI->getOperand(0).getImm());
1550  break;
1551  case X86::SEH_SetFrame:
1552  assert(MI->getOperand(1).getImm() == 0 &&
1553  ".cv_fpo_setframe takes no offset");
1554  XTS->emitFPOSetFrame(MI->getOperand(0).getImm());
1555  break;
1556  case X86::SEH_EndPrologue:
1557  XTS->emitFPOEndPrologue();
1558  break;
1559  case X86::SEH_SaveReg:
1560  case X86::SEH_SaveXMM:
1561  case X86::SEH_PushFrame:
1562  llvm_unreachable("SEH_ directive incompatible with FPO");
1563  break;
1564  default:
1565  llvm_unreachable("expected SEH_ instruction");
1566  }
1567  return;
1568  }
1569 
1570  // Otherwise, use the .seh_ directives for all other Windows platforms.
1571  switch (MI->getOpcode()) {
1572  case X86::SEH_PushReg:
1573  OutStreamer->EmitWinCFIPushReg(
1574  RI->getSEHRegNum(MI->getOperand(0).getImm()));
1575  break;
1576 
1577  case X86::SEH_SaveReg:
1578  OutStreamer->EmitWinCFISaveReg(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1579  MI->getOperand(1).getImm());
1580  break;
1581 
1582  case X86::SEH_SaveXMM:
1583  OutStreamer->EmitWinCFISaveXMM(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1584  MI->getOperand(1).getImm());
1585  break;
1586 
1587  case X86::SEH_StackAlloc:
1588  OutStreamer->EmitWinCFIAllocStack(MI->getOperand(0).getImm());
1589  break;
1590 
1591  case X86::SEH_SetFrame:
1592  OutStreamer->EmitWinCFISetFrame(
1593  RI->getSEHRegNum(MI->getOperand(0).getImm()),
1594  MI->getOperand(1).getImm());
1595  break;
1596 
1597  case X86::SEH_PushFrame:
1598  OutStreamer->EmitWinCFIPushFrame(MI->getOperand(0).getImm());
1599  break;
1600 
1601  case X86::SEH_EndPrologue:
1602  OutStreamer->EmitWinCFIEndProlog();
1603  break;
1604 
1605  default:
1606  llvm_unreachable("expected SEH_ instruction");
1607  }
1608 }
1609 
1610 static unsigned getRegisterWidth(const MCOperandInfo &Info) {
1611  if (Info.RegClass == X86::VR128RegClassID ||
1612  Info.RegClass == X86::VR128XRegClassID)
1613  return 128;
1614  if (Info.RegClass == X86::VR256RegClassID ||
1615  Info.RegClass == X86::VR256XRegClassID)
1616  return 256;
1617  if (Info.RegClass == X86::VR512RegClassID)
1618  return 512;
1619  llvm_unreachable("Unknown register class!");
1620 }
1621 
1623  X86MCInstLower MCInstLowering(*MF, *this);
1624  const X86RegisterInfo *RI =
1625  MF->getSubtarget<X86Subtarget>().getRegisterInfo();
1626 
1627  // Add a comment about EVEX-2-VEX compression for AVX-512 instrs that
1628  // are compressed from EVEX encoding to VEX encoding.
1631  OutStreamer->AddComment("EVEX TO VEX Compression ", false);
1632  }
1633 
1634  switch (MI->getOpcode()) {
1635  case TargetOpcode::DBG_VALUE:
1636  llvm_unreachable("Should be handled target independently");
1637 
1638  // Emit nothing here but a comment if we can.
1639  case X86::Int_MemBarrier:
1640  OutStreamer->emitRawComment("MEMBARRIER");
1641  return;
1642 
1643  case X86::EH_RETURN:
1644  case X86::EH_RETURN64: {
1645  // Lower these as normal, but add some comments.
1646  unsigned Reg = MI->getOperand(0).getReg();
1647  OutStreamer->AddComment(StringRef("eh_return, addr: %") +
1649  break;
1650  }
1651  case X86::CLEANUPRET: {
1652  // Lower these as normal, but add some comments.
1653  OutStreamer->AddComment("CLEANUPRET");
1654  break;
1655  }
1656 
1657  case X86::CATCHRET: {
1658  // Lower these as normal, but add some comments.
1659  OutStreamer->AddComment("CATCHRET");
1660  break;
1661  }
1662 
1663  case X86::TAILJMPr:
1664  case X86::TAILJMPm:
1665  case X86::TAILJMPd:
1666  case X86::TAILJMPd_CC:
1667  case X86::TAILJMPr64:
1668  case X86::TAILJMPm64:
1669  case X86::TAILJMPd64:
1670  case X86::TAILJMPd64_CC:
1671  case X86::TAILJMPr64_REX:
1672  case X86::TAILJMPm64_REX:
1673  // Lower these as normal, but add some comments.
1674  OutStreamer->AddComment("TAILCALL");
1675  break;
1676 
1677  case X86::TLS_addr32:
1678  case X86::TLS_addr64:
1679  case X86::TLS_base_addr32:
1680  case X86::TLS_base_addr64:
1681  return LowerTlsAddr(MCInstLowering, *MI);
1682 
1683  // Loading/storing mask pairs requires two kmov operations. The second one of these
1684  // needs a 2 byte displacement relative to the specified address (with 32 bit spill
1685  // size). The pairs of 1bit masks up to 16 bit masks all use the same spill size,
1686  // they all are stored using MASKPAIR16STORE, loaded using MASKPAIR16LOAD.
1687  //
1688  // The displacement value might wrap around in theory, thus the asserts in both
1689  // cases.
1690  case X86::MASKPAIR16LOAD: {
1691  int64_t Disp = MI->getOperand(1 + X86::AddrDisp).getImm();
1692  assert(Disp >= 0 && Disp <= INT32_MAX - 2 && "Unexpected displacement");
1693  const X86RegisterInfo *RI =
1694  MF->getSubtarget<X86Subtarget>().getRegisterInfo();
1695  unsigned Reg = MI->getOperand(0).getReg();
1696  unsigned Reg0 = RI->getSubReg(Reg, X86::sub_mask_0);
1697  unsigned Reg1 = RI->getSubReg(Reg, X86::sub_mask_1);
1698 
1699  // Load the first mask register
1700  MCInstBuilder MIB = MCInstBuilder(X86::KMOVWkm);
1701  MIB.addReg(Reg0);
1702  for (int i = 0; i < X86::AddrNumOperands; ++i) {
1703  auto Op = MCInstLowering.LowerMachineOperand(MI, MI->getOperand(1 + i));
1704  MIB.addOperand(Op.getValue());
1705  }
1706  EmitAndCountInstruction(MIB);
1707 
1708  // Load the second mask register of the pair
1709  MIB = MCInstBuilder(X86::KMOVWkm);
1710  MIB.addReg(Reg1);
1711  for (int i = 0; i < X86::AddrNumOperands; ++i) {
1712  if (i == X86::AddrDisp) {
1713  MIB.addImm(Disp + 2);
1714  } else {
1715  auto Op = MCInstLowering.LowerMachineOperand(MI, MI->getOperand(1 + i));
1716  MIB.addOperand(Op.getValue());
1717  }
1718  }
1719  EmitAndCountInstruction(MIB);
1720  return;
1721  }
1722 
1723  case X86::MASKPAIR16STORE: {
1724  int64_t Disp = MI->getOperand(X86::AddrDisp).getImm();
1725  assert(Disp >= 0 && Disp <= INT32_MAX - 2 && "Unexpected displacement");
1726  const X86RegisterInfo *RI =
1727  MF->getSubtarget<X86Subtarget>().getRegisterInfo();
1728  unsigned Reg = MI->getOperand(X86::AddrNumOperands).getReg();
1729  unsigned Reg0 = RI->getSubReg(Reg, X86::sub_mask_0);
1730  unsigned Reg1 = RI->getSubReg(Reg, X86::sub_mask_1);
1731 
1732  // Store the first mask register
1733  MCInstBuilder MIB = MCInstBuilder(X86::KMOVWmk);
1734  for (int i = 0; i < X86::AddrNumOperands; ++i)
1735  MIB.addOperand(MCInstLowering.LowerMachineOperand(MI, MI->getOperand(i)).getValue());
1736  MIB.addReg(Reg0);
1737  EmitAndCountInstruction(MIB);
1738 
1739  // Store the second mask register of the pair
1740  MIB = MCInstBuilder(X86::KMOVWmk);
1741  for (int i = 0; i < X86::AddrNumOperands; ++i) {
1742  if (i == X86::AddrDisp) {
1743  MIB.addImm(Disp + 2);
1744  } else {
1745  auto Op = MCInstLowering.LowerMachineOperand(MI, MI->getOperand(0 + i));
1746  MIB.addOperand(Op.getValue());
1747  }
1748  }
1749  MIB.addReg(Reg1);
1750  EmitAndCountInstruction(MIB);
1751  return;
1752  }
1753 
1754  case X86::MOVPC32r: {
1755  // This is a pseudo op for a two instruction sequence with a label, which
1756  // looks like:
1757  // call "L1$pb"
1758  // "L1$pb":
1759  // popl %esi
1760 
1761  // Emit the call.
1762  MCSymbol *PICBase = MF->getPICBaseSymbol();
1763  // FIXME: We would like an efficient form for this, so we don't have to do a
1764  // lot of extra uniquing.
1765  EmitAndCountInstruction(
1766  MCInstBuilder(X86::CALLpcrel32)
1767  .addExpr(MCSymbolRefExpr::create(PICBase, OutContext)));
1768 
1769  const X86FrameLowering *FrameLowering =
1770  MF->getSubtarget<X86Subtarget>().getFrameLowering();
1771  bool hasFP = FrameLowering->hasFP(*MF);
1772 
1773  // TODO: This is needed only if we require precise CFA.
1774  bool HasActiveDwarfFrame = OutStreamer->getNumFrameInfos() &&
1775  !OutStreamer->getDwarfFrameInfos().back().End;
1776 
1777  int stackGrowth = -RI->getSlotSize();
1778 
1779  if (HasActiveDwarfFrame && !hasFP) {
1780  OutStreamer->EmitCFIAdjustCfaOffset(-stackGrowth);
1781  }
1782 
1783  // Emit the label.
1784  OutStreamer->EmitLabel(PICBase);
1785 
1786  // popl $reg
1787  EmitAndCountInstruction(
1788  MCInstBuilder(X86::POP32r).addReg(MI->getOperand(0).getReg()));
1789 
1790  if (HasActiveDwarfFrame && !hasFP) {
1791  OutStreamer->EmitCFIAdjustCfaOffset(stackGrowth);
1792  }
1793  return;
1794  }
1795 
1796  case X86::ADD32ri: {
1797  // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
1799  break;
1800 
1801  // Okay, we have something like:
1802  // EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
1803 
1804  // For this, we want to print something like:
1805  // MYGLOBAL + (. - PICBASE)
1806  // However, we can't generate a ".", so just emit a new label here and refer
1807  // to it.
1808  MCSymbol *DotSym = OutContext.createTempSymbol();
1809  OutStreamer->EmitLabel(DotSym);
1810 
1811  // Now that we have emitted the label, lower the complex operand expression.
1812  MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
1813 
1814  const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext);
1815  const MCExpr *PICBase =
1817  DotExpr = MCBinaryExpr::createSub(DotExpr, PICBase, OutContext);
1818 
1819  DotExpr = MCBinaryExpr::createAdd(
1820  MCSymbolRefExpr::create(OpSym, OutContext), DotExpr, OutContext);
1821 
1822  EmitAndCountInstruction(MCInstBuilder(X86::ADD32ri)
1823  .addReg(MI->getOperand(0).getReg())
1824  .addReg(MI->getOperand(1).getReg())
1825  .addExpr(DotExpr));
1826  return;
1827  }
1828  case TargetOpcode::STATEPOINT:
1829  return LowerSTATEPOINT(*MI, MCInstLowering);
1830 
1831  case TargetOpcode::FAULTING_OP:
1832  return LowerFAULTING_OP(*MI, MCInstLowering);
1833 
1834  case TargetOpcode::FENTRY_CALL:
1835  return LowerFENTRY_CALL(*MI, MCInstLowering);
1836 
1837  case TargetOpcode::PATCHABLE_OP:
1838  return LowerPATCHABLE_OP(*MI, MCInstLowering);
1839 
1840  case TargetOpcode::STACKMAP:
1841  return LowerSTACKMAP(*MI);
1842 
1843  case TargetOpcode::PATCHPOINT:
1844  return LowerPATCHPOINT(*MI, MCInstLowering);
1845 
1846  case TargetOpcode::PATCHABLE_FUNCTION_ENTER:
1847  return LowerPATCHABLE_FUNCTION_ENTER(*MI, MCInstLowering);
1848 
1849  case TargetOpcode::PATCHABLE_RET:
1850  return LowerPATCHABLE_RET(*MI, MCInstLowering);
1851 
1852  case TargetOpcode::PATCHABLE_TAIL_CALL:
1853  return LowerPATCHABLE_TAIL_CALL(*MI, MCInstLowering);
1854 
1855  case TargetOpcode::PATCHABLE_EVENT_CALL:
1856  return LowerPATCHABLE_EVENT_CALL(*MI, MCInstLowering);
1857 
1858  case TargetOpcode::PATCHABLE_TYPED_EVENT_CALL:
1859  return LowerPATCHABLE_TYPED_EVENT_CALL(*MI, MCInstLowering);
1860 
1861  case X86::MORESTACK_RET:
1862  EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
1863  return;
1864 
1865  case X86::MORESTACK_RET_RESTORE_R10:
1866  // Return, then restore R10.
1867  EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
1868  EmitAndCountInstruction(
1869  MCInstBuilder(X86::MOV64rr).addReg(X86::R10).addReg(X86::RAX));
1870  return;
1871 
1872  case X86::SEH_PushReg:
1873  case X86::SEH_SaveReg:
1874  case X86::SEH_SaveXMM:
1875  case X86::SEH_StackAlloc:
1876  case X86::SEH_StackAlign:
1877  case X86::SEH_SetFrame:
1878  case X86::SEH_PushFrame:
1879  case X86::SEH_EndPrologue:
1880  EmitSEHInstruction(MI);
1881  return;
1882 
1883  case X86::SEH_Epilogue: {
1884  assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?");
1886  // Check if preceded by a call and emit nop if so.
1887  for (MBBI = PrevCrossBBInst(MBBI);
1889  MBBI = PrevCrossBBInst(MBBI)) {
1890  // Conservatively assume that pseudo instructions don't emit code and keep
1891  // looking for a call. We may emit an unnecessary nop in some cases.
1892  if (!MBBI->isPseudo()) {
1893  if (MBBI->isCall())
1894  EmitAndCountInstruction(MCInstBuilder(X86::NOOP));
1895  break;
1896  }
1897  }
1898  return;
1899  }
1900 
1901  // Lower PSHUFB and VPERMILP normally but add a comment if we can find
1902  // a constant shuffle mask. We won't be able to do this at the MC layer
1903  // because the mask isn't an immediate.
1904  case X86::PSHUFBrm:
1905  case X86::VPSHUFBrm:
1906  case X86::VPSHUFBYrm:
1907  case X86::VPSHUFBZ128rm:
1908  case X86::VPSHUFBZ128rmk:
1909  case X86::VPSHUFBZ128rmkz:
1910  case X86::VPSHUFBZ256rm:
1911  case X86::VPSHUFBZ256rmk:
1912  case X86::VPSHUFBZ256rmkz:
1913  case X86::VPSHUFBZrm:
1914  case X86::VPSHUFBZrmk:
1915  case X86::VPSHUFBZrmkz: {
1916  if (!OutStreamer->isVerboseAsm())
1917  break;
1918  unsigned SrcIdx, MaskIdx;
1919  switch (MI->getOpcode()) {
1920  default: llvm_unreachable("Invalid opcode");
1921  case X86::PSHUFBrm:
1922  case X86::VPSHUFBrm:
1923  case X86::VPSHUFBYrm:
1924  case X86::VPSHUFBZ128rm:
1925  case X86::VPSHUFBZ256rm:
1926  case X86::VPSHUFBZrm:
1927  SrcIdx = 1; MaskIdx = 5; break;
1928  case X86::VPSHUFBZ128rmkz:
1929  case X86::VPSHUFBZ256rmkz:
1930  case X86::VPSHUFBZrmkz:
1931  SrcIdx = 2; MaskIdx = 6; break;
1932  case X86::VPSHUFBZ128rmk:
1933  case X86::VPSHUFBZ256rmk:
1934  case X86::VPSHUFBZrmk:
1935  SrcIdx = 3; MaskIdx = 7; break;
1936  }
1937 
1938  assert(MI->getNumOperands() >= 6 &&
1939  "We should always have at least 6 operands!");
1940 
1941  const MachineOperand &MaskOp = MI->getOperand(MaskIdx);
1942  if (auto *C = getConstantFromPool(*MI, MaskOp)) {
1943  unsigned Width = getRegisterWidth(MI->getDesc().OpInfo[0]);
1945  DecodePSHUFBMask(C, Width, Mask);
1946  if (!Mask.empty())
1947  OutStreamer->AddComment(getShuffleComment(MI, SrcIdx, SrcIdx, Mask));
1948  }
1949  break;
1950  }
1951 
1952  case X86::VPERMILPSrm:
1953  case X86::VPERMILPSYrm:
1954  case X86::VPERMILPSZ128rm:
1955  case X86::VPERMILPSZ128rmk:
1956  case X86::VPERMILPSZ128rmkz:
1957  case X86::VPERMILPSZ256rm:
1958  case X86::VPERMILPSZ256rmk:
1959  case X86::VPERMILPSZ256rmkz:
1960  case X86::VPERMILPSZrm:
1961  case X86::VPERMILPSZrmk:
1962  case X86::VPERMILPSZrmkz:
1963  case X86::VPERMILPDrm:
1964  case X86::VPERMILPDYrm:
1965  case X86::VPERMILPDZ128rm:
1966  case X86::VPERMILPDZ128rmk:
1967  case X86::VPERMILPDZ128rmkz:
1968  case X86::VPERMILPDZ256rm:
1969  case X86::VPERMILPDZ256rmk:
1970  case X86::VPERMILPDZ256rmkz:
1971  case X86::VPERMILPDZrm:
1972  case X86::VPERMILPDZrmk:
1973  case X86::VPERMILPDZrmkz: {
1974  if (!OutStreamer->isVerboseAsm())
1975  break;
1976  unsigned SrcIdx, MaskIdx;
1977  unsigned ElSize;
1978  switch (MI->getOpcode()) {
1979  default: llvm_unreachable("Invalid opcode");
1980  case X86::VPERMILPSrm:
1981  case X86::VPERMILPSYrm:
1982  case X86::VPERMILPSZ128rm:
1983  case X86::VPERMILPSZ256rm:
1984  case X86::VPERMILPSZrm:
1985  SrcIdx = 1; MaskIdx = 5; ElSize = 32; break;
1986  case X86::VPERMILPSZ128rmkz:
1987  case X86::VPERMILPSZ256rmkz:
1988  case X86::VPERMILPSZrmkz:
1989  SrcIdx = 2; MaskIdx = 6; ElSize = 32; break;
1990  case X86::VPERMILPSZ128rmk:
1991  case X86::VPERMILPSZ256rmk:
1992  case X86::VPERMILPSZrmk:
1993  SrcIdx = 3; MaskIdx = 7; ElSize = 32; break;
1994  case X86::VPERMILPDrm:
1995  case X86::VPERMILPDYrm:
1996  case X86::VPERMILPDZ128rm:
1997  case X86::VPERMILPDZ256rm:
1998  case X86::VPERMILPDZrm:
1999  SrcIdx = 1; MaskIdx = 5; ElSize = 64; break;
2000  case X86::VPERMILPDZ128rmkz:
2001  case X86::VPERMILPDZ256rmkz:
2002  case X86::VPERMILPDZrmkz:
2003  SrcIdx = 2; MaskIdx = 6; ElSize = 64; break;
2004  case X86::VPERMILPDZ128rmk:
2005  case X86::VPERMILPDZ256rmk:
2006  case X86::VPERMILPDZrmk:
2007  SrcIdx = 3; MaskIdx = 7; ElSize = 64; break;
2008  }
2009 
2010  assert(MI->getNumOperands() >= 6 &&
2011  "We should always have at least 6 operands!");
2012 
2013  const MachineOperand &MaskOp = MI->getOperand(MaskIdx);
2014  if (auto *C = getConstantFromPool(*MI, MaskOp)) {
2015  unsigned Width = getRegisterWidth(MI->getDesc().OpInfo[0]);
2017  DecodeVPERMILPMask(C, ElSize, Width, Mask);
2018  if (!Mask.empty())
2019  OutStreamer->AddComment(getShuffleComment(MI, SrcIdx, SrcIdx, Mask));
2020  }
2021  break;
2022  }
2023 
2024  case X86::VPERMIL2PDrm:
2025  case X86::VPERMIL2PSrm:
2026  case X86::VPERMIL2PDYrm:
2027  case X86::VPERMIL2PSYrm: {
2028  if (!OutStreamer->isVerboseAsm())
2029  break;
2030  assert(MI->getNumOperands() >= 8 &&
2031  "We should always have at least 8 operands!");
2032 
2033  const MachineOperand &CtrlOp = MI->getOperand(MI->getNumOperands() - 1);
2034  if (!CtrlOp.isImm())
2035  break;
2036 
2037  unsigned ElSize;
2038  switch (MI->getOpcode()) {
2039  default: llvm_unreachable("Invalid opcode");
2040  case X86::VPERMIL2PSrm: case X86::VPERMIL2PSYrm: ElSize = 32; break;
2041  case X86::VPERMIL2PDrm: case X86::VPERMIL2PDYrm: ElSize = 64; break;
2042  }
2043 
2044  const MachineOperand &MaskOp = MI->getOperand(6);
2045  if (auto *C = getConstantFromPool(*MI, MaskOp)) {
2046  unsigned Width = getRegisterWidth(MI->getDesc().OpInfo[0]);
2048  DecodeVPERMIL2PMask(C, (unsigned)CtrlOp.getImm(), ElSize, Width, Mask);
2049  if (!Mask.empty())
2050  OutStreamer->AddComment(getShuffleComment(MI, 1, 2, Mask));
2051  }
2052  break;
2053  }
2054 
2055  case X86::VPPERMrrm: {
2056  if (!OutStreamer->isVerboseAsm())
2057  break;
2058  assert(MI->getNumOperands() >= 7 &&
2059  "We should always have at least 7 operands!");
2060 
2061  const MachineOperand &MaskOp = MI->getOperand(6);
2062  if (auto *C = getConstantFromPool(*MI, MaskOp)) {
2063  unsigned Width = getRegisterWidth(MI->getDesc().OpInfo[0]);
2065  DecodeVPPERMMask(C, Width, Mask);
2066  if (!Mask.empty())
2067  OutStreamer->AddComment(getShuffleComment(MI, 1, 2, Mask));
2068  }
2069  break;
2070  }
2071 
2072  case X86::MMX_MOVQ64rm: {
2073  if (!OutStreamer->isVerboseAsm())
2074  break;
2075  if (MI->getNumOperands() <= 4)
2076  break;
2077  if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) {
2078  std::string Comment;
2079  raw_string_ostream CS(Comment);
2080  const MachineOperand &DstOp = MI->getOperand(0);
2081  CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = ";
2082  if (auto *CF = dyn_cast<ConstantFP>(C)) {
2083  CS << "0x" << CF->getValueAPF().bitcastToAPInt().toString(16, false);
2084  OutStreamer->AddComment(CS.str());
2085  }
2086  }
2087  break;
2088  }
2089 
2090 #define MOV_CASE(Prefix, Suffix) \
2091  case X86::Prefix##MOVAPD##Suffix##rm: \
2092  case X86::Prefix##MOVAPS##Suffix##rm: \
2093  case X86::Prefix##MOVUPD##Suffix##rm: \
2094  case X86::Prefix##MOVUPS##Suffix##rm: \
2095  case X86::Prefix##MOVDQA##Suffix##rm: \
2096  case X86::Prefix##MOVDQU##Suffix##rm:
2097 
2098 #define MOV_AVX512_CASE(Suffix) \
2099  case X86::VMOVDQA64##Suffix##rm: \
2100  case X86::VMOVDQA32##Suffix##rm: \
2101  case X86::VMOVDQU64##Suffix##rm: \
2102  case X86::VMOVDQU32##Suffix##rm: \
2103  case X86::VMOVDQU16##Suffix##rm: \
2104  case X86::VMOVDQU8##Suffix##rm: \
2105  case X86::VMOVAPS##Suffix##rm: \
2106  case X86::VMOVAPD##Suffix##rm: \
2107  case X86::VMOVUPS##Suffix##rm: \
2108  case X86::VMOVUPD##Suffix##rm:
2109 
2110 #define CASE_ALL_MOV_RM() \
2111  MOV_CASE(, ) /* SSE */ \
2112  MOV_CASE(V, ) /* AVX-128 */ \
2113  MOV_CASE(V, Y) /* AVX-256 */ \
2114  MOV_AVX512_CASE(Z) \
2115  MOV_AVX512_CASE(Z256) \
2116  MOV_AVX512_CASE(Z128)
2117 
2118  // For loads from a constant pool to a vector register, print the constant
2119  // loaded.
2120  CASE_ALL_MOV_RM()
2121  case X86::VBROADCASTF128:
2122  case X86::VBROADCASTI128:
2123  case X86::VBROADCASTF32X4Z256rm:
2124  case X86::VBROADCASTF32X4rm:
2125  case X86::VBROADCASTF32X8rm:
2126  case X86::VBROADCASTF64X2Z128rm:
2127  case X86::VBROADCASTF64X2rm:
2128  case X86::VBROADCASTF64X4rm:
2129  case X86::VBROADCASTI32X4Z256rm:
2130  case X86::VBROADCASTI32X4rm:
2131  case X86::VBROADCASTI32X8rm:
2132  case X86::VBROADCASTI64X2Z128rm:
2133  case X86::VBROADCASTI64X2rm:
2134  case X86::VBROADCASTI64X4rm:
2135  if (!OutStreamer->isVerboseAsm())
2136  break;
2137  if (MI->getNumOperands() <= 4)
2138  break;
2139  if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) {
2140  int NumLanes = 1;
2141  // Override NumLanes for the broadcast instructions.
2142  switch (MI->getOpcode()) {
2143  case X86::VBROADCASTF128: NumLanes = 2; break;
2144  case X86::VBROADCASTI128: NumLanes = 2; break;
2145  case X86::VBROADCASTF32X4Z256rm: NumLanes = 2; break;
2146  case X86::VBROADCASTF32X4rm: NumLanes = 4; break;
2147  case X86::VBROADCASTF32X8rm: NumLanes = 2; break;
2148  case X86::VBROADCASTF64X2Z128rm: NumLanes = 2; break;
2149  case X86::VBROADCASTF64X2rm: NumLanes = 4; break;
2150  case X86::VBROADCASTF64X4rm: NumLanes = 2; break;
2151  case X86::VBROADCASTI32X4Z256rm: NumLanes = 2; break;
2152  case X86::VBROADCASTI32X4rm: NumLanes = 4; break;
2153  case X86::VBROADCASTI32X8rm: NumLanes = 2; break;
2154  case X86::VBROADCASTI64X2Z128rm: NumLanes = 2; break;
2155  case X86::VBROADCASTI64X2rm: NumLanes = 4; break;
2156  case X86::VBROADCASTI64X4rm: NumLanes = 2; break;
2157  }
2158 
2159  std::string Comment;
2160  raw_string_ostream CS(Comment);
2161  const MachineOperand &DstOp = MI->getOperand(0);
2162  CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = ";
2163  if (auto *CDS = dyn_cast<ConstantDataSequential>(C)) {
2164  CS << "[";
2165  for (int l = 0; l != NumLanes; ++l) {
2166  for (int i = 0, NumElements = CDS->getNumElements(); i < NumElements;
2167  ++i) {
2168  if (i != 0 || l != 0)
2169  CS << ",";
2170  if (CDS->getElementType()->isIntegerTy())
2171  printConstant(CDS->getElementAsAPInt(i), CS);
2172  else if (CDS->getElementType()->isHalfTy() ||
2173  CDS->getElementType()->isFloatTy() ||
2174  CDS->getElementType()->isDoubleTy())
2175  printConstant(CDS->getElementAsAPFloat(i), CS);
2176  else
2177  CS << "?";
2178  }
2179  }
2180  CS << "]";
2181  OutStreamer->AddComment(CS.str());
2182  } else if (auto *CV = dyn_cast<ConstantVector>(C)) {
2183  CS << "<";
2184  for (int l = 0; l != NumLanes; ++l) {
2185  for (int i = 0, NumOperands = CV->getNumOperands(); i < NumOperands;
2186  ++i) {
2187  if (i != 0 || l != 0)
2188  CS << ",";
2189  printConstant(CV->getOperand(i), CS);
2190  }
2191  }
2192  CS << ">";
2193  OutStreamer->AddComment(CS.str());
2194  }
2195  }
2196  break;
2197  case X86::MOVDDUPrm:
2198  case X86::VMOVDDUPrm:
2199  case X86::VMOVDDUPZ128rm:
2200  case X86::VBROADCASTSSrm:
2201  case X86::VBROADCASTSSYrm:
2202  case X86::VBROADCASTSSZ128m:
2203  case X86::VBROADCASTSSZ256m:
2204  case X86::VBROADCASTSSZm:
2205  case X86::VBROADCASTSDYrm:
2206  case X86::VBROADCASTSDZ256m:
2207  case X86::VBROADCASTSDZm:
2208  case X86::VPBROADCASTBrm:
2209  case X86::VPBROADCASTBYrm:
2210  case X86::VPBROADCASTBZ128m:
2211  case X86::VPBROADCASTBZ256m:
2212  case X86::VPBROADCASTBZm:
2213  case X86::VPBROADCASTDrm:
2214  case X86::VPBROADCASTDYrm:
2215  case X86::VPBROADCASTDZ128m:
2216  case X86::VPBROADCASTDZ256m:
2217  case X86::VPBROADCASTDZm:
2218  case X86::VPBROADCASTQrm:
2219  case X86::VPBROADCASTQYrm:
2220  case X86::VPBROADCASTQZ128m:
2221  case X86::VPBROADCASTQZ256m:
2222  case X86::VPBROADCASTQZm:
2223  case X86::VPBROADCASTWrm:
2224  case X86::VPBROADCASTWYrm:
2225  case X86::VPBROADCASTWZ128m:
2226  case X86::VPBROADCASTWZ256m:
2227  case X86::VPBROADCASTWZm:
2228  if (!OutStreamer->isVerboseAsm())
2229  break;
2230  if (MI->getNumOperands() <= 4)
2231  break;
2232  if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) {
2233  int NumElts;
2234  switch (MI->getOpcode()) {
2235  default: llvm_unreachable("Invalid opcode");
2236  case X86::MOVDDUPrm: NumElts = 2; break;
2237  case X86::VMOVDDUPrm: NumElts = 2; break;
2238  case X86::VMOVDDUPZ128rm: NumElts = 2; break;
2239  case X86::VBROADCASTSSrm: NumElts = 4; break;
2240  case X86::VBROADCASTSSYrm: NumElts = 8; break;
2241  case X86::VBROADCASTSSZ128m: NumElts = 4; break;
2242  case X86::VBROADCASTSSZ256m: NumElts = 8; break;
2243  case X86::VBROADCASTSSZm: NumElts = 16; break;
2244  case X86::VBROADCASTSDYrm: NumElts = 4; break;
2245  case X86::VBROADCASTSDZ256m: NumElts = 4; break;
2246  case X86::VBROADCASTSDZm: NumElts = 8; break;
2247  case X86::VPBROADCASTBrm: NumElts = 16; break;
2248  case X86::VPBROADCASTBYrm: NumElts = 32; break;
2249  case X86::VPBROADCASTBZ128m: NumElts = 16; break;
2250  case X86::VPBROADCASTBZ256m: NumElts = 32; break;
2251  case X86::VPBROADCASTBZm: NumElts = 64; break;
2252  case X86::VPBROADCASTDrm: NumElts = 4; break;
2253  case X86::VPBROADCASTDYrm: NumElts = 8; break;
2254  case X86::VPBROADCASTDZ128m: NumElts = 4; break;
2255  case X86::VPBROADCASTDZ256m: NumElts = 8; break;
2256  case X86::VPBROADCASTDZm: NumElts = 16; break;
2257  case X86::VPBROADCASTQrm: NumElts = 2; break;
2258  case X86::VPBROADCASTQYrm: NumElts = 4; break;
2259  case X86::VPBROADCASTQZ128m: NumElts = 2; break;
2260  case X86::VPBROADCASTQZ256m: NumElts = 4; break;
2261  case X86::VPBROADCASTQZm: NumElts = 8; break;
2262  case X86::VPBROADCASTWrm: NumElts = 8; break;
2263  case X86::VPBROADCASTWYrm: NumElts = 16; break;
2264  case X86::VPBROADCASTWZ128m: NumElts = 8; break;
2265  case X86::VPBROADCASTWZ256m: NumElts = 16; break;
2266  case X86::VPBROADCASTWZm: NumElts = 32; break;
2267  }
2268 
2269  std::string Comment;
2270  raw_string_ostream CS(Comment);
2271  const MachineOperand &DstOp = MI->getOperand(0);
2272  CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = ";
2273  CS << "[";
2274  for (int i = 0; i != NumElts; ++i) {
2275  if (i != 0)
2276  CS << ",";
2277  printConstant(C, CS);
2278  }
2279  CS << "]";
2280  OutStreamer->AddComment(CS.str());
2281  }
2282  }
2283 
2284  MCInst TmpInst;
2285  MCInstLowering.Lower(MI, TmpInst);
2286 
2287  // Stackmap shadows cannot include branch targets, so we can count the bytes
2288  // in a call towards the shadow, but must ensure that the no thread returns
2289  // in to the stackmap shadow. The only way to achieve this is if the call
2290  // is at the end of the shadow.
2291  if (MI->isCall()) {
2292  // Count then size of the call towards the shadow
2293  SMShadowTracker.count(TmpInst, getSubtargetInfo(), CodeEmitter.get());
2294  // Then flush the shadow so that we fill with nops before the call, not
2295  // after it.
2296  SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
2297  // Then emit the call
2298  OutStreamer->EmitInstruction(TmpInst, getSubtargetInfo());
2299  return;
2300  }
2301 
2302  EmitAndCountInstruction(TmpInst);
2303 }
unsigned getTargetFlags() const
MO_SECREL - On a symbol operand this indicates that the immediate is the offset from beginning of sec...
Definition: X86BaseInfo.h:265
const NoneType None
Definition: None.h:23
uint64_t CallInst * C
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:542
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
bool isImm() const
Definition: MCInst.h:58
mop_iterator operands_end()
Definition: MachineInstr.h:455
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
unsigned getNextScratchIdx(unsigned StartIdx=0) const
Get the next scratch register operand index.
Definition: StackMaps.cpp:69
static const char * getRegisterName(unsigned RegNo)
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1562
virtual void EmitWinCFIPushReg(unsigned Register, SMLoc Loc=SMLoc())
Definition: MCStreamer.cpp:766
AddrSegmentReg - The operand # of the segment in the memory operand.
Definition: X86BaseInfo.h:38
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "...
Definition: X86BaseInfo.h:275
virtual bool emitFPOSetFrame(unsigned Reg, SMLoc L={})=0
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:634
MachineBasicBlock * getMBB() const
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
Definition: AsmPrinter.h:93
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:321
MCTargetOptions MCOptions
Machine level options.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
PointerTy getPointer() const
static MachineOperand CreateMCSymbol(MCSymbol *Sym, unsigned char TargetFlags=0)
void setTargetFlags(unsigned F)
StringRef getPrivateGlobalPrefix() const
Definition: DataLayout.h:316
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
void DecodeVPPERMMask(ArrayRef< uint64_t > RawMask, const APInt &UndefElts, SmallVectorImpl< int > &ShuffleMask)
Decode a VPPERM mask from a raw array of constants such as from BUILD_VECTOR.
iterator begin() const
Definition: ArrayRef.h:136
MO_TLSLD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with ...
Definition: X86BaseInfo.h:173
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate is some TLS offset from the ...
Definition: X86BaseInfo.h:259
MCContext & OutContext
This is the context for the output file that we are streaming.
Definition: AsmPrinter.h:88
static MachineModuleInfoMachO & getMachOMMI(AsmPrinter &AP)
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:136
unsigned getNumWords() const
Get the number of words.
Definition: APInt.h:1515
const MCSubtargetInfo & getSubtargetInfo() const
Return information about subtarget.
Definition: AsmPrinter.cpp:227
virtual void EmitWinCFISaveXMM(unsigned Register, unsigned Offset, SMLoc Loc=SMLoc())
Definition: MCStreamer.cpp:833
This provides a very simple, boring adaptor for a begin and end iterator into a range type...
unsigned getReg() const
getReg - Returns the register number.
virtual void EmitBytes(StringRef Data)
Emit the bytes in Data into the output.
Address of indexed Jump Table for switch.
This class represents a function call, abstracting a target machine&#39;s calling convention.
unsigned Reg
bool isReg() const
Definition: MCInst.h:57
PointerIntPair< MCSymbol *, 1, bool > StubValueTy
static std::string getShuffleComment(const MachineInstr *MI, unsigned SrcOp1Idx, unsigned SrcOp2Idx, ArrayRef< int > Mask)
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:509
MachineBasicBlock reference.
MachineFunction * MF
The current machine function.
Definition: AsmPrinter.h:96
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
MachineInstrBundleIterator< const MachineInstr > const_iterator
MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...
Definition: X86BaseInfo.h:147
MO_DTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry with...
Definition: X86BaseInfo.h:216
static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, const MCSubtargetInfo &STI)
Emit the optimal amount of multi-byte nops on X86.
virtual bool emitFPOPushReg(unsigned Reg, SMLoc L={})=0
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:460
print alias Alias Set Printer
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
unsigned getSlotSize() const
virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
Definition: MCStreamer.cpp:960
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1508
Mask of preserved registers.
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
MCContext & getContext() const
Definition: MCStreamer.h:250
void recordSled(MCSymbol *Sled, const MachineInstr &MI, SledKind Kind, uint8_t Version=0)
CLEANUPRET - Represents a return from a cleanup block funclet.
Definition: ISDOpcodes.h:721
unsigned getNumFrameInfos()
Definition: MCStreamer.cpp:110
MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates that the reference is actually...
Definition: X86BaseInfo.h:247
bool isMachineConstantPoolEntry() const
isMachineConstantPoolEntry - Return true if the MachineConstantPoolEntry is indeed a target specific ...
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:115
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
virtual bool emitFPOStackAlloc(unsigned StackAlloc, SMLoc L={})=0
MachineModuleInfoCOFF - This is a MachineModuleInfoImpl implementation for COFF targets.
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:413
void DecodeVPERMILPMask(unsigned NumElts, unsigned ScalarBits, ArrayRef< uint64_t > RawMask, const APInt &UndefElts, SmallVectorImpl< int > &ShuffleMask)
Decode a VPERMILPD/VPERMILPS variable mask from a raw array of constants.
virtual void encodeInstruction(const MCInst &Inst, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
EncodeInstruction - Encode the given Inst to bytes on the output stream OS.
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
Name of external global symbol.
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:165
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:410
const char * getSymbolName() const
#define CASE_ALL_MOV_RM()
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:126
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:64
Context object for machine code objects.
Definition: MCContext.h:62
void recordFaultingOp(FaultKind FaultTy, const MCSymbol *HandlerLabel)
Definition: FaultMaps.cpp:30
virtual void AddComment(const Twine &T, bool EOL=true)
Add a textual comment.
Definition: MCStreamer.h:309
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:407
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:244
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:544
void toString(SmallVectorImpl< char > &Str, unsigned FormatPrecision=0, unsigned FormatMaxPadding=3, bool TruncateZero=true) const
Definition: APFloat.h:1177
bool isPositionIndependent() const
Definition: AsmPrinter.cpp:204
MO_GOT - On a symbol operand this indicates that the immediate is the offset to the GOT entry for the...
Definition: X86BaseInfo.h:132
MO_GOTTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry wi...
Definition: X86BaseInfo.h:191
MO_ABS8 - On a symbol operand this indicates that the symbol is known to be an absolute symbol in ran...
Definition: X86BaseInfo.h:270
ArrayRef< MCDwarfFrameInfo > getDwarfFrameInfos() const
Definition: MCStreamer.cpp:111
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
virtual void emitRawComment(const Twine &T, bool TabPrefix=true)
Print T and prefix it with the comment string (normally #) and optionally a tab.
Definition: MCStreamer.cpp:115
This class is a data container for one entry in a MachineConstantPool.
virtual void EmitBinaryData(StringRef Data)
Functionally identical to EmitBytes.
const MCExpr * getExpr() const
Definition: MCInst.h:95
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:459
MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the reference is actually to the "...
Definition: X86BaseInfo.h:242
MCInstBuilder & addOperand(const MCOperand &Op)
Add an operand.
Definition: MCInstBuilder.h:61
MachineModuleInfo * MMI
This is a pointer to the current MachineModuleInfo.
Definition: AsmPrinter.h:99
void recordStatepoint(const MachineInstr &MI)
Generate a stackmap record for a statepoint instruction.
Definition: StackMaps.cpp:393
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
auto count(R &&Range, const E &Element) -> typename std::iterator_traits< decltype(adl_begin(Range))>::difference_type
Wrapper function around std::count to count the number of times an element Element occurs in the give...
Definition: STLExtras.h:1258
virtual bool emitFPOStackAlign(unsigned Align, SMLoc L={})=0
bool isX86_64ExtendedReg(unsigned RegNo)
isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or higher) register? e.g.
Definition: X86BaseInfo.h:842
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
int64_t getImm() const
Definition: MCInst.h:75
Address of a global value.
Streaming machine code generation interface.
Definition: MCStreamer.h:188
MCInstBuilder & addReg(unsigned Reg)
Add a new register operand.
Definition: MCInstBuilder.h:31
MCSymbol * createTempSymbol(bool CanBeUnnamed=true)
Create and return a new assembler temporary symbol with a unique but unspecified name.
Definition: MCContext.cpp:220
MCTargetStreamer * getTargetStreamer()
Definition: MCStreamer.h:257
MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a relocation of: SYMBOL_LABEL + [...
Definition: X86BaseInfo.h:120
PointerIntPair - This class implements a pair of a pointer and small integer.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry w...
Definition: X86BaseInfo.h:232
MO_TLVP - On a symbol operand this indicates that the immediate is some TLS offset.
Definition: X86BaseInfo.h:253
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This is an important base class in LLVM.
Definition: Constant.h:41
const GlobalValue * getGlobal() const
MO_TLSLDM - On a symbol operand this indicates that the immediate is the offset of the GOT entry with...
Definition: X86BaseInfo.h:183
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
TargetMachine & TM
Target machine description.
Definition: AsmPrinter.h:81
This class is intended to be used as a driving class for all asm writers.
Definition: AsmPrinter.h:78
void getNameWithPrefix(SmallVectorImpl< char > &Name, const GlobalValue *GV) const
Definition: AsmPrinter.cpp:437
bool hasInternalLinkage() const
Definition: GlobalValue.h:443
Address of a basic block.
bool isExpr() const
Definition: MCInst.h:60
static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst, unsigned Opcode)
Simplify things like MOV32rm to MOV32o32a.
MO_NTPOFF - On a symbol operand this indicates that the immediate is the negative thread-pointer offs...
Definition: X86BaseInfo.h:224
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
Definition: MCInstBuilder.h:37
MI-level patchpoint operands.
Definition: StackMaps.h:76
unsigned getNumOperands() const
Definition: MCInst.h:181
int getSEHRegNum(unsigned i) const
AddrNumOperands - Total number of operands in a memory reference.
Definition: X86BaseInfo.h:41
void print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const
Print this MI to OS.
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
static const Constant * getConstantFromPool(const MachineInstr &MI, const MachineOperand &Op)
const MachineBasicBlock & front() const
bool useRetpolineIndirectCalls() const
Definition: X86Subtarget.h:699
size_t size() const
Definition: SmallVector.h:52
virtual MCSymbol * GetCPISymbol(unsigned CPID) const
Return the symbol for the specified constant pool entry.
StubValueTy & getGVStubEntry(MCSymbol *Sym)
void DecodeVPERMIL2PMask(unsigned NumElts, unsigned ScalarBits, unsigned M2Z, ArrayRef< uint64_t > RawMask, const APInt &UndefElts, SmallVectorImpl< int > &ShuffleMask)
Decode a VPERMIL2PD/VPERMIL2PS variable mask from a raw array of constants.
virtual void EmitWinCFISetFrame(unsigned Register, unsigned Offset, SMLoc Loc=SMLoc())
Definition: MCStreamer.cpp:777
std::string & str()
Flushes the stream contents to the target string and returns the string&#39;s reference.
Definition: raw_ostream.h:498
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void recordPatchPoint(const MachineInstr &MI)
Generate a stackmap record for a patchpoint instruction.
Definition: StackMaps.cpp:372
MO_TLSGD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with ...
Definition: X86BaseInfo.h:163
const std::vector< MachineConstantPoolEntry > & getConstants() const
virtual void EmitWinCFIPushFrame(bool Code, SMLoc Loc=SMLoc())
Definition: MCStreamer.cpp:848
MO_TPOFF - On a symbol operand this indicates that the immediate is the thread-pointer offset for the...
Definition: X86BaseInfo.h:208
static void printConstant(const APInt &Val, raw_ostream &CS)
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
void setOpcode(unsigned Op)
Definition: MCInst.h:170
MCSymbol * GetBlockAddressSymbol(const BlockAddress *BA) const
Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block.
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
static MCOperand LowerSymbolOperand(const MachineInstr *MI, const MachineOperand &MO, AsmPrinter &AP)
MCSymbol * getSymbol(const GlobalValue *GV) const
Definition: AsmPrinter.cpp:442
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:837
virtual void EmitWinCFIEndProlog(SMLoc Loc=SMLoc())
Definition: MCStreamer.cpp:862
virtual void EmitCodeAlignment(unsigned ByteAlignment, unsigned MaxBytesToEmit=0)
Emit nops until the byte alignment ByteAlignment is reached.
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:179
virtual void EmitWinCFIAllocStack(unsigned Size, SMLoc Loc=SMLoc())
Definition: MCStreamer.cpp:799
iterator end() const
Definition: ArrayRef.h:137
X86 target streamer implementing x86-only assembly directives.
int64_t getImm() const
MCSymbol reference (for debug/eh info)
StubValueTy & getGVStubEntry(MCSymbol *Sym)
Target - Wrapper for Target specific information.
Class for arbitrary precision integers.
Definition: APInt.h:69
void recordStackMap(const MachineInstr &MI)
Generate a stackmap record for a stackmap instruction.
Definition: StackMaps.cpp:363
virtual bool emitFPOEndPrologue(SMLoc L={})=0
bool getRtLibUseGOT() const
Returns true if PLT should be avoided for RTLib calls.
Definition: Module.cpp:550
CATCHRET - Represents a return from a catch block funclet.
Definition: ISDOpcodes.h:717
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:255
const uint64_t * getRawData() const
This function returns a pointer to the internal storage of the APInt.
Definition: APInt.h:674
Representation of each machine instruction.
Definition: MachineInstr.h:63
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MO_GOTOFF - On a symbol operand this indicates that the immediate is the offset to the location of th...
Definition: X86BaseInfo.h:139
static unsigned getRetOpcode(const X86Subtarget &Subtarget)
MCSymbol * GetJTISymbol(unsigned JTID, bool isLinkerPrivate=false) const
Return the symbol for the specified jump table entry.
MO_INDNTPOFF - On a symbol operand this indicates that the immediate is the absolute address of the G...
Definition: X86BaseInfo.h:200
virtual void EmitWinCFISaveReg(unsigned Register, unsigned Offset, SMLoc Loc=SMLoc())
Definition: MCStreamer.cpp:816
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:124
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:72
TargetOptions Options
int64_t getOffset() const
Return the offset from the symbol in this operand.
const BlockAddress * getBlockAddress() const
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
Generic base class for all target subtargets.
MI-level Statepoint operands.
Definition: StackMaps.h:154
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given patchpoint should emit.
Definition: StackMaps.h:104
void EmitInstruction(const MachineInstr *MI) override
Targets should implement this to emit instructions.
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
const Module * getModule() const
MachineModuleInfoMachO - This is a MachineModuleInfoImpl implementation for MachO targets...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents &#39;eh_return&#39; gcc dwarf builtin...
Definition: ISDOpcodes.h:101
MO_PLT - On a symbol operand this indicates that the immediate is offset to the PLT entry of symbol n...
Definition: X86BaseInfo.h:154
StringRef getName() const
getName - Get the symbol name.
Definition: MCSymbol.h:203
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:482
MCSymbol * getMCSymbol() const
mop_iterator operands_begin()
Definition: MachineInstr.h:454
MCSymbol * getPICBaseSymbol() const
getPICBaseSymbol - Return a function-local symbol to represent the PIC base.
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:175
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
virtual void EmitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
Definition: MCStreamer.cpp:351
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the immediate should get the value of th...
Definition: X86BaseInfo.h:125
void getNameWithPrefix(raw_ostream &OS, const GlobalValue *GV, bool CannotUsePrivateLabel) const
Print the appropriate prefix and the specified global variable&#39;s name.
Definition: Mangler.cpp:111
static MachineBasicBlock::const_iterator PrevCrossBBInst(MachineBasicBlock::const_iterator MBBI)
IRTranslator LLVM IR MI
const MachineOperand & getCallTarget() const
Returns the target of the underlying call.
Definition: StackMaps.h:109
void addOperand(const MCOperand &Op)
Definition: MCInst.h:183
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
Address of indexed Constant in Constant Pool.
static MCSymbol * GetSymbolFromOperand(const MachineOperand &MO, AsmPrinter &AP)
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:66
unsigned getOpcode() const
Definition: MCInst.h:171
virtual bool isVerboseAsm() const
Return true if this streamer supports verbose assembly and if it is enabled.
Definition: MCStreamer.h:286
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:415
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:34
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:122
static unsigned EmitNop(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, const MCSubtargetInfo &STI)
Emit the largest nop instruction smaller than or equal to NumBytes bytes.
const X86Subtarget & getSubtarget() const
static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode)
Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with a short fixed-register form...
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx)
Definition: MCExpr.cpp:163
virtual void EmitCFIAdjustCfaOffset(int64_t Adjustment)
Definition: MCStreamer.cpp:438
static void SimplifyMOVSX(MCInst &Inst)
If a movsx instruction has a shorter encoding for the used register simplify the instruction to use i...
uint8_t getAsmPrinterFlags() const
Return the asm printer flags bitvector.
Definition: MachineInstr.h:270
MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the reference is actually to the "__imp...
Definition: X86BaseInfo.h:237
bool isImplicit() const
void DecodePSHUFBMask(ArrayRef< uint64_t > RawMask, const APInt &UndefElts, SmallVectorImpl< int > &ShuffleMask)
Decode a PSHUFB mask from a raw array of constants such as from BUILD_VECTOR.
union llvm::MachineConstantPoolEntry::@164 Val
The constant itself.
static unsigned getRegisterWidth(const MCOperandInfo &Info)