LLVM  6.0.0svn
X86MCInstLower.cpp
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1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains code to lower X86 MachineInstrs to their corresponding
11 // MCInst records.
12 //
13 //===----------------------------------------------------------------------===//
14 
18 #include "Utils/X86ShuffleDecode.h"
19 #include "X86AsmPrinter.h"
20 #include "X86RegisterInfo.h"
22 #include "llvm/ADT/Optional.h"
23 #include "llvm/ADT/SmallString.h"
25 #include "llvm/BinaryFormat/ELF.h"
30 #include "llvm/CodeGen/StackMaps.h"
31 #include "llvm/IR/DataLayout.h"
32 #include "llvm/IR/GlobalValue.h"
33 #include "llvm/IR/Mangler.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCCodeEmitter.h"
36 #include "llvm/MC/MCContext.h"
37 #include "llvm/MC/MCExpr.h"
38 #include "llvm/MC/MCFixup.h"
39 #include "llvm/MC/MCInst.h"
40 #include "llvm/MC/MCInstBuilder.h"
41 #include "llvm/MC/MCSection.h"
42 #include "llvm/MC/MCSectionELF.h"
43 #include "llvm/MC/MCSectionMachO.h"
44 #include "llvm/MC/MCStreamer.h"
45 #include "llvm/MC/MCSymbol.h"
46 #include "llvm/MC/MCSymbolELF.h"
49 
50 using namespace llvm;
51 
52 namespace {
53 
54 /// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst.
55 class X86MCInstLower {
56  MCContext &Ctx;
57  const MachineFunction &MF;
58  const TargetMachine &TM;
59  const MCAsmInfo &MAI;
61 public:
62  X86MCInstLower(const MachineFunction &MF, X86AsmPrinter &asmprinter);
63 
64  Optional<MCOperand> LowerMachineOperand(const MachineInstr *MI,
65  const MachineOperand &MO) const;
66  void Lower(const MachineInstr *MI, MCInst &OutMI) const;
67 
69  MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
70 
71 private:
73 };
74 
75 } // end anonymous namespace
76 
77 // Emit a minimal sequence of nops spanning NumBytes bytes.
78 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
79  const MCSubtargetInfo &STI);
80 
82  const MCSubtargetInfo &STI,
83  MCCodeEmitter *CodeEmitter) {
84  if (InShadow) {
87  raw_svector_ostream VecOS(Code);
88  CodeEmitter->encodeInstruction(Inst, VecOS, Fixups, STI);
89  CurrentShadowSize += Code.size();
90  if (CurrentShadowSize >= RequiredShadowSize)
91  InShadow = false; // The shadow is big enough. Stop counting.
92  }
93 }
94 
95 void X86AsmPrinter::StackMapShadowTracker::emitShadowPadding(
96  MCStreamer &OutStreamer, const MCSubtargetInfo &STI) {
97  if (InShadow && CurrentShadowSize < RequiredShadowSize) {
98  InShadow = false;
99  EmitNops(OutStreamer, RequiredShadowSize - CurrentShadowSize,
100  MF->getSubtarget<X86Subtarget>().is64Bit(), STI);
101  }
102 }
103 
104 void X86AsmPrinter::EmitAndCountInstruction(MCInst &Inst) {
105  OutStreamer->EmitInstruction(Inst, getSubtargetInfo(), EnablePrintSchedInfo);
106  SMShadowTracker.count(Inst, getSubtargetInfo(), CodeEmitter.get());
107 }
108 
109 X86MCInstLower::X86MCInstLower(const MachineFunction &mf,
110  X86AsmPrinter &asmprinter)
111  : Ctx(mf.getContext()), MF(mf), TM(mf.getTarget()), MAI(*TM.getMCAsmInfo()),
112  AsmPrinter(asmprinter) {}
113 
115  return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>();
116 }
117 
118 
119 /// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
120 /// operand to an MCSymbol.
122 GetSymbolFromOperand(const MachineOperand &MO) const {
123  const DataLayout &DL = MF.getDataLayout();
124  assert((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) && "Isn't a symbol reference");
125 
126  MCSymbol *Sym = nullptr;
128  StringRef Suffix;
129 
130  switch (MO.getTargetFlags()) {
131  case X86II::MO_DLLIMPORT:
132  // Handle dllimport linkage.
133  Name += "__imp_";
134  break;
137  Suffix = "$non_lazy_ptr";
138  break;
139  }
140 
141  if (!Suffix.empty())
142  Name += DL.getPrivateGlobalPrefix();
143 
144  if (MO.isGlobal()) {
145  const GlobalValue *GV = MO.getGlobal();
146  AsmPrinter.getNameWithPrefix(Name, GV);
147  } else if (MO.isSymbol()) {
149  } else if (MO.isMBB()) {
150  assert(Suffix.empty());
151  Sym = MO.getMBB()->getSymbol();
152  }
153 
154  Name += Suffix;
155  if (!Sym)
156  Sym = Ctx.getOrCreateSymbol(Name);
157 
158  // If the target flags on the operand changes the name of the symbol, do that
159  // before we return the symbol.
160  switch (MO.getTargetFlags()) {
161  default: break;
166  if (!StubSym.getPointer()) {
167  assert(MO.isGlobal() && "Extern symbol not handled yet");
168  StubSym =
171  !MO.getGlobal()->hasInternalLinkage());
172  }
173  break;
174  }
175  }
176 
177  return Sym;
178 }
179 
181  MCSymbol *Sym) const {
182  // FIXME: We would like an efficient form for this, so we don't have to do a
183  // lot of extra uniquing.
184  const MCExpr *Expr = nullptr;
186 
187  switch (MO.getTargetFlags()) {
188  default: llvm_unreachable("Unknown target flag on GV operand");
189  case X86II::MO_NO_FLAG: // No flag.
190  // These affect the name of the symbol, not any suffix.
192  case X86II::MO_DLLIMPORT:
193  break;
194 
195  case X86II::MO_TLVP: RefKind = MCSymbolRefExpr::VK_TLVP; break;
198  // Subtract the pic base.
199  Expr = MCBinaryExpr::createSub(Expr,
200  MCSymbolRefExpr::create(MF.getPICBaseSymbol(),
201  Ctx),
202  Ctx);
203  break;
204  case X86II::MO_SECREL: RefKind = MCSymbolRefExpr::VK_SECREL; break;
205  case X86II::MO_TLSGD: RefKind = MCSymbolRefExpr::VK_TLSGD; break;
206  case X86II::MO_TLSLD: RefKind = MCSymbolRefExpr::VK_TLSLD; break;
207  case X86II::MO_TLSLDM: RefKind = MCSymbolRefExpr::VK_TLSLDM; break;
208  case X86II::MO_GOTTPOFF: RefKind = MCSymbolRefExpr::VK_GOTTPOFF; break;
209  case X86II::MO_INDNTPOFF: RefKind = MCSymbolRefExpr::VK_INDNTPOFF; break;
210  case X86II::MO_TPOFF: RefKind = MCSymbolRefExpr::VK_TPOFF; break;
211  case X86II::MO_DTPOFF: RefKind = MCSymbolRefExpr::VK_DTPOFF; break;
212  case X86II::MO_NTPOFF: RefKind = MCSymbolRefExpr::VK_NTPOFF; break;
213  case X86II::MO_GOTNTPOFF: RefKind = MCSymbolRefExpr::VK_GOTNTPOFF; break;
214  case X86II::MO_GOTPCREL: RefKind = MCSymbolRefExpr::VK_GOTPCREL; break;
215  case X86II::MO_GOT: RefKind = MCSymbolRefExpr::VK_GOT; break;
216  case X86II::MO_GOTOFF: RefKind = MCSymbolRefExpr::VK_GOTOFF; break;
217  case X86II::MO_PLT: RefKind = MCSymbolRefExpr::VK_PLT; break;
218  case X86II::MO_ABS8: RefKind = MCSymbolRefExpr::VK_X86_ABS8; break;
221  Expr = MCSymbolRefExpr::create(Sym, Ctx);
222  // Subtract the pic base.
223  Expr = MCBinaryExpr::createSub(Expr,
224  MCSymbolRefExpr::create(MF.getPICBaseSymbol(), Ctx),
225  Ctx);
226  if (MO.isJTI()) {
227  assert(MAI.doesSetDirectiveSuppressReloc());
228  // If .set directive is supported, use it to reduce the number of
229  // relocations the assembler will generate for differences between
230  // local labels. This is only safe when the symbols are in the same
231  // section so we are restricting it to jumptable references.
232  MCSymbol *Label = Ctx.createTempSymbol();
233  AsmPrinter.OutStreamer->EmitAssignment(Label, Expr);
234  Expr = MCSymbolRefExpr::create(Label, Ctx);
235  }
236  break;
237  }
238 
239  if (!Expr)
240  Expr = MCSymbolRefExpr::create(Sym, RefKind, Ctx);
241 
242  if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
243  Expr = MCBinaryExpr::createAdd(Expr,
245  Ctx);
246  return MCOperand::createExpr(Expr);
247 }
248 
249 
250 /// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with
251 /// a short fixed-register form.
252 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
253  unsigned ImmOp = Inst.getNumOperands() - 1;
254  assert(Inst.getOperand(0).isReg() &&
255  (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) &&
256  ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
257  Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
258  Inst.getNumOperands() == 2) && "Unexpected instruction!");
259 
260  // Check whether the destination register can be fixed.
261  unsigned Reg = Inst.getOperand(0).getReg();
262  if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
263  return;
264 
265  // If so, rewrite the instruction.
266  MCOperand Saved = Inst.getOperand(ImmOp);
267  Inst = MCInst();
268  Inst.setOpcode(Opcode);
269  Inst.addOperand(Saved);
270 }
271 
272 /// \brief If a movsx instruction has a shorter encoding for the used register
273 /// simplify the instruction to use it instead.
274 static void SimplifyMOVSX(MCInst &Inst) {
275  unsigned NewOpcode = 0;
276  unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg();
277  switch (Inst.getOpcode()) {
278  default:
279  llvm_unreachable("Unexpected instruction!");
280  case X86::MOVSX16rr8: // movsbw %al, %ax --> cbtw
281  if (Op0 == X86::AX && Op1 == X86::AL)
282  NewOpcode = X86::CBW;
283  break;
284  case X86::MOVSX32rr16: // movswl %ax, %eax --> cwtl
285  if (Op0 == X86::EAX && Op1 == X86::AX)
286  NewOpcode = X86::CWDE;
287  break;
288  case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq
289  if (Op0 == X86::RAX && Op1 == X86::EAX)
290  NewOpcode = X86::CDQE;
291  break;
292  }
293 
294  if (NewOpcode != 0) {
295  Inst = MCInst();
296  Inst.setOpcode(NewOpcode);
297  }
298 }
299 
300 /// \brief Simplify things like MOV32rm to MOV32o32a.
302  unsigned Opcode) {
303  // Don't make these simplifications in 64-bit mode; other assemblers don't
304  // perform them because they make the code larger.
305  if (Printer.getSubtarget().is64Bit())
306  return;
307 
308  bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
309  unsigned AddrBase = IsStore;
310  unsigned RegOp = IsStore ? 0 : 5;
311  unsigned AddrOp = AddrBase + 3;
312  assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
313  Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() &&
314  Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() &&
315  Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() &&
316  Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() &&
317  (Inst.getOperand(AddrOp).isExpr() ||
318  Inst.getOperand(AddrOp).isImm()) &&
319  "Unexpected instruction!");
320 
321  // Check whether the destination register can be fixed.
322  unsigned Reg = Inst.getOperand(RegOp).getReg();
323  if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
324  return;
325 
326  // Check whether this is an absolute address.
327  // FIXME: We know TLVP symbol refs aren't, but there should be a better way
328  // to do this here.
329  bool Absolute = true;
330  if (Inst.getOperand(AddrOp).isExpr()) {
331  const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr();
332  if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE))
333  if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
334  Absolute = false;
335  }
336 
337  if (Absolute &&
338  (Inst.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 ||
339  Inst.getOperand(AddrBase + X86::AddrScaleAmt).getImm() != 1 ||
340  Inst.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0))
341  return;
342 
343  // If so, rewrite the instruction.
344  MCOperand Saved = Inst.getOperand(AddrOp);
345  MCOperand Seg = Inst.getOperand(AddrBase + X86::AddrSegmentReg);
346  Inst = MCInst();
347  Inst.setOpcode(Opcode);
348  Inst.addOperand(Saved);
349  Inst.addOperand(Seg);
350 }
351 
352 static unsigned getRetOpcode(const X86Subtarget &Subtarget) {
353  return Subtarget.is64Bit() ? X86::RETQ : X86::RETL;
354 }
355 
357 X86MCInstLower::LowerMachineOperand(const MachineInstr *MI,
358  const MachineOperand &MO) const {
359  switch (MO.getType()) {
360  default:
361  MI->print(errs());
362  llvm_unreachable("unknown operand type");
364  // Ignore all implicit register operands.
365  if (MO.isImplicit())
366  return None;
367  return MCOperand::createReg(MO.getReg());
369  return MCOperand::createImm(MO.getImm());
375  return LowerSymbolOperand(MO, MO.getMCSymbol());
381  return LowerSymbolOperand(
384  // Ignore call clobbers.
385  return None;
386  }
387 }
388 
389 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
390  OutMI.setOpcode(MI->getOpcode());
391 
392  for (const MachineOperand &MO : MI->operands())
393  if (auto MaybeMCOp = LowerMachineOperand(MI, MO))
394  OutMI.addOperand(MaybeMCOp.getValue());
395 
396  // Handle a few special cases to eliminate operand modifiers.
397 ReSimplify:
398  switch (OutMI.getOpcode()) {
399  case X86::LEA64_32r:
400  case X86::LEA64r:
401  case X86::LEA16r:
402  case X86::LEA32r:
403  // LEA should have a segment register, but it must be empty.
405  "Unexpected # of LEA operands");
406  assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 &&
407  "LEA has segment specified!");
408  break;
409 
410  // Commute operands to get a smaller encoding by using VEX.R instead of VEX.B
411  // if one of the registers is extended, but other isn't.
412  case X86::VMOVZPQILo2PQIrr:
413  case X86::VMOVAPDrr:
414  case X86::VMOVAPDYrr:
415  case X86::VMOVAPSrr:
416  case X86::VMOVAPSYrr:
417  case X86::VMOVDQArr:
418  case X86::VMOVDQAYrr:
419  case X86::VMOVDQUrr:
420  case X86::VMOVDQUYrr:
421  case X86::VMOVUPDrr:
422  case X86::VMOVUPDYrr:
423  case X86::VMOVUPSrr:
424  case X86::VMOVUPSYrr: {
425  if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
427  unsigned NewOpc;
428  switch (OutMI.getOpcode()) {
429  default: llvm_unreachable("Invalid opcode");
430  case X86::VMOVZPQILo2PQIrr: NewOpc = X86::VMOVPQI2QIrr; break;
431  case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
432  case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
433  case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;
434  case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
435  case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;
436  case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
437  case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break;
438  case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
439  case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break;
440  case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
441  case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break;
442  case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
443  }
444  OutMI.setOpcode(NewOpc);
445  }
446  break;
447  }
448  case X86::VMOVSDrr:
449  case X86::VMOVSSrr: {
450  if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
452  unsigned NewOpc;
453  switch (OutMI.getOpcode()) {
454  default: llvm_unreachable("Invalid opcode");
455  case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break;
456  case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break;
457  }
458  OutMI.setOpcode(NewOpc);
459  }
460  break;
461  }
462 
463  // TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have register
464  // inputs modeled as normal uses instead of implicit uses. As such, truncate
465  // off all but the first operand (the callee). FIXME: Change isel.
466  case X86::TAILJMPr64:
467  case X86::TAILJMPr64_REX:
468  case X86::CALL64r:
469  case X86::CALL64pcrel32: {
470  unsigned Opcode = OutMI.getOpcode();
471  MCOperand Saved = OutMI.getOperand(0);
472  OutMI = MCInst();
473  OutMI.setOpcode(Opcode);
474  OutMI.addOperand(Saved);
475  break;
476  }
477 
478  case X86::EH_RETURN:
479  case X86::EH_RETURN64: {
480  OutMI = MCInst();
481  OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));
482  break;
483  }
484 
485  case X86::CLEANUPRET: {
486  // Replace CATCHRET with the appropriate RET.
487  OutMI = MCInst();
488  OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));
489  break;
490  }
491 
492  case X86::CATCHRET: {
493  // Replace CATCHRET with the appropriate RET.
494  const X86Subtarget &Subtarget = AsmPrinter.getSubtarget();
495  unsigned ReturnReg = Subtarget.is64Bit() ? X86::RAX : X86::EAX;
496  OutMI = MCInst();
497  OutMI.setOpcode(getRetOpcode(Subtarget));
498  OutMI.addOperand(MCOperand::createReg(ReturnReg));
499  break;
500  }
501 
502  // TAILJMPd, TAILJMPd64, TailJMPd_cc - Lower to the correct jump instruction.
503  { unsigned Opcode;
504  case X86::TAILJMPr: Opcode = X86::JMP32r; goto SetTailJmpOpcode;
505  case X86::TAILJMPd:
506  case X86::TAILJMPd64: Opcode = X86::JMP_1; goto SetTailJmpOpcode;
507  case X86::TAILJMPd_CC:
508  case X86::TAILJMPd64_CC:
510  static_cast<X86::CondCode>(MI->getOperand(1).getImm()));
511  goto SetTailJmpOpcode;
512 
513  SetTailJmpOpcode:
514  MCOperand Saved = OutMI.getOperand(0);
515  OutMI = MCInst();
516  OutMI.setOpcode(Opcode);
517  OutMI.addOperand(Saved);
518  break;
519  }
520 
521  case X86::DEC16r:
522  case X86::DEC32r:
523  case X86::INC16r:
524  case X86::INC32r:
525  // If we aren't in 64-bit mode we can use the 1-byte inc/dec instructions.
526  if (!AsmPrinter.getSubtarget().is64Bit()) {
527  unsigned Opcode;
528  switch (OutMI.getOpcode()) {
529  default: llvm_unreachable("Invalid opcode");
530  case X86::DEC16r: Opcode = X86::DEC16r_alt; break;
531  case X86::DEC32r: Opcode = X86::DEC32r_alt; break;
532  case X86::INC16r: Opcode = X86::INC16r_alt; break;
533  case X86::INC32r: Opcode = X86::INC32r_alt; break;
534  }
535  OutMI.setOpcode(Opcode);
536  }
537  break;
538 
539  // These are pseudo-ops for OR to help with the OR->ADD transformation. We do
540  // this with an ugly goto in case the resultant OR uses EAX and needs the
541  // short form.
542  case X86::ADD16rr_DB: OutMI.setOpcode(X86::OR16rr); goto ReSimplify;
543  case X86::ADD32rr_DB: OutMI.setOpcode(X86::OR32rr); goto ReSimplify;
544  case X86::ADD64rr_DB: OutMI.setOpcode(X86::OR64rr); goto ReSimplify;
545  case X86::ADD16ri_DB: OutMI.setOpcode(X86::OR16ri); goto ReSimplify;
546  case X86::ADD32ri_DB: OutMI.setOpcode(X86::OR32ri); goto ReSimplify;
547  case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify;
548  case X86::ADD16ri8_DB: OutMI.setOpcode(X86::OR16ri8); goto ReSimplify;
549  case X86::ADD32ri8_DB: OutMI.setOpcode(X86::OR32ri8); goto ReSimplify;
550  case X86::ADD64ri8_DB: OutMI.setOpcode(X86::OR64ri8); goto ReSimplify;
551 
552  // Atomic load and store require a separate pseudo-inst because Acquire
553  // implies mayStore and Release implies mayLoad; fix these to regular MOV
554  // instructions here
555  case X86::ACQUIRE_MOV8rm: OutMI.setOpcode(X86::MOV8rm); goto ReSimplify;
556  case X86::ACQUIRE_MOV16rm: OutMI.setOpcode(X86::MOV16rm); goto ReSimplify;
557  case X86::ACQUIRE_MOV32rm: OutMI.setOpcode(X86::MOV32rm); goto ReSimplify;
558  case X86::ACQUIRE_MOV64rm: OutMI.setOpcode(X86::MOV64rm); goto ReSimplify;
559  case X86::RELEASE_MOV8mr: OutMI.setOpcode(X86::MOV8mr); goto ReSimplify;
560  case X86::RELEASE_MOV16mr: OutMI.setOpcode(X86::MOV16mr); goto ReSimplify;
561  case X86::RELEASE_MOV32mr: OutMI.setOpcode(X86::MOV32mr); goto ReSimplify;
562  case X86::RELEASE_MOV64mr: OutMI.setOpcode(X86::MOV64mr); goto ReSimplify;
563  case X86::RELEASE_MOV8mi: OutMI.setOpcode(X86::MOV8mi); goto ReSimplify;
564  case X86::RELEASE_MOV16mi: OutMI.setOpcode(X86::MOV16mi); goto ReSimplify;
565  case X86::RELEASE_MOV32mi: OutMI.setOpcode(X86::MOV32mi); goto ReSimplify;
566  case X86::RELEASE_MOV64mi32: OutMI.setOpcode(X86::MOV64mi32); goto ReSimplify;
567  case X86::RELEASE_ADD8mi: OutMI.setOpcode(X86::ADD8mi); goto ReSimplify;
568  case X86::RELEASE_ADD8mr: OutMI.setOpcode(X86::ADD8mr); goto ReSimplify;
569  case X86::RELEASE_ADD32mi: OutMI.setOpcode(X86::ADD32mi); goto ReSimplify;
570  case X86::RELEASE_ADD32mr: OutMI.setOpcode(X86::ADD32mr); goto ReSimplify;
571  case X86::RELEASE_ADD64mi32: OutMI.setOpcode(X86::ADD64mi32); goto ReSimplify;
572  case X86::RELEASE_ADD64mr: OutMI.setOpcode(X86::ADD64mr); goto ReSimplify;
573  case X86::RELEASE_AND8mi: OutMI.setOpcode(X86::AND8mi); goto ReSimplify;
574  case X86::RELEASE_AND8mr: OutMI.setOpcode(X86::AND8mr); goto ReSimplify;
575  case X86::RELEASE_AND32mi: OutMI.setOpcode(X86::AND32mi); goto ReSimplify;
576  case X86::RELEASE_AND32mr: OutMI.setOpcode(X86::AND32mr); goto ReSimplify;
577  case X86::RELEASE_AND64mi32: OutMI.setOpcode(X86::AND64mi32); goto ReSimplify;
578  case X86::RELEASE_AND64mr: OutMI.setOpcode(X86::AND64mr); goto ReSimplify;
579  case X86::RELEASE_OR8mi: OutMI.setOpcode(X86::OR8mi); goto ReSimplify;
580  case X86::RELEASE_OR8mr: OutMI.setOpcode(X86::OR8mr); goto ReSimplify;
581  case X86::RELEASE_OR32mi: OutMI.setOpcode(X86::OR32mi); goto ReSimplify;
582  case X86::RELEASE_OR32mr: OutMI.setOpcode(X86::OR32mr); goto ReSimplify;
583  case X86::RELEASE_OR64mi32: OutMI.setOpcode(X86::OR64mi32); goto ReSimplify;
584  case X86::RELEASE_OR64mr: OutMI.setOpcode(X86::OR64mr); goto ReSimplify;
585  case X86::RELEASE_XOR8mi: OutMI.setOpcode(X86::XOR8mi); goto ReSimplify;
586  case X86::RELEASE_XOR8mr: OutMI.setOpcode(X86::XOR8mr); goto ReSimplify;
587  case X86::RELEASE_XOR32mi: OutMI.setOpcode(X86::XOR32mi); goto ReSimplify;
588  case X86::RELEASE_XOR32mr: OutMI.setOpcode(X86::XOR32mr); goto ReSimplify;
589  case X86::RELEASE_XOR64mi32: OutMI.setOpcode(X86::XOR64mi32); goto ReSimplify;
590  case X86::RELEASE_XOR64mr: OutMI.setOpcode(X86::XOR64mr); goto ReSimplify;
591  case X86::RELEASE_INC8m: OutMI.setOpcode(X86::INC8m); goto ReSimplify;
592  case X86::RELEASE_INC16m: OutMI.setOpcode(X86::INC16m); goto ReSimplify;
593  case X86::RELEASE_INC32m: OutMI.setOpcode(X86::INC32m); goto ReSimplify;
594  case X86::RELEASE_INC64m: OutMI.setOpcode(X86::INC64m); goto ReSimplify;
595  case X86::RELEASE_DEC8m: OutMI.setOpcode(X86::DEC8m); goto ReSimplify;
596  case X86::RELEASE_DEC16m: OutMI.setOpcode(X86::DEC16m); goto ReSimplify;
597  case X86::RELEASE_DEC32m: OutMI.setOpcode(X86::DEC32m); goto ReSimplify;
598  case X86::RELEASE_DEC64m: OutMI.setOpcode(X86::DEC64m); goto ReSimplify;
599 
600  // We don't currently select the correct instruction form for instructions
601  // which have a short %eax, etc. form. Handle this by custom lowering, for
602  // now.
603  //
604  // Note, we are currently not handling the following instructions:
605  // MOV64ao8, MOV64o8a
606  // XCHG16ar, XCHG32ar, XCHG64ar
607  case X86::MOV8mr_NOREX:
608  case X86::MOV8mr:
609  case X86::MOV8rm_NOREX:
610  case X86::MOV8rm:
611  case X86::MOV16mr:
612  case X86::MOV16rm:
613  case X86::MOV32mr:
614  case X86::MOV32rm: {
615  unsigned NewOpc;
616  switch (OutMI.getOpcode()) {
617  default: llvm_unreachable("Invalid opcode");
618  case X86::MOV8mr_NOREX:
619  case X86::MOV8mr: NewOpc = X86::MOV8o32a; break;
620  case X86::MOV8rm_NOREX:
621  case X86::MOV8rm: NewOpc = X86::MOV8ao32; break;
622  case X86::MOV16mr: NewOpc = X86::MOV16o32a; break;
623  case X86::MOV16rm: NewOpc = X86::MOV16ao32; break;
624  case X86::MOV32mr: NewOpc = X86::MOV32o32a; break;
625  case X86::MOV32rm: NewOpc = X86::MOV32ao32; break;
626  }
627  SimplifyShortMoveForm(AsmPrinter, OutMI, NewOpc);
628  break;
629  }
630 
631  case X86::ADC8ri: case X86::ADC16ri: case X86::ADC32ri: case X86::ADC64ri32:
632  case X86::ADD8ri: case X86::ADD16ri: case X86::ADD32ri: case X86::ADD64ri32:
633  case X86::AND8ri: case X86::AND16ri: case X86::AND32ri: case X86::AND64ri32:
634  case X86::CMP8ri: case X86::CMP16ri: case X86::CMP32ri: case X86::CMP64ri32:
635  case X86::OR8ri: case X86::OR16ri: case X86::OR32ri: case X86::OR64ri32:
636  case X86::SBB8ri: case X86::SBB16ri: case X86::SBB32ri: case X86::SBB64ri32:
637  case X86::SUB8ri: case X86::SUB16ri: case X86::SUB32ri: case X86::SUB64ri32:
638  case X86::TEST8ri:case X86::TEST16ri:case X86::TEST32ri:case X86::TEST64ri32:
639  case X86::XOR8ri: case X86::XOR16ri: case X86::XOR32ri: case X86::XOR64ri32: {
640  unsigned NewOpc;
641  switch (OutMI.getOpcode()) {
642  default: llvm_unreachable("Invalid opcode");
643  case X86::ADC8ri: NewOpc = X86::ADC8i8; break;
644  case X86::ADC16ri: NewOpc = X86::ADC16i16; break;
645  case X86::ADC32ri: NewOpc = X86::ADC32i32; break;
646  case X86::ADC64ri32: NewOpc = X86::ADC64i32; break;
647  case X86::ADD8ri: NewOpc = X86::ADD8i8; break;
648  case X86::ADD16ri: NewOpc = X86::ADD16i16; break;
649  case X86::ADD32ri: NewOpc = X86::ADD32i32; break;
650  case X86::ADD64ri32: NewOpc = X86::ADD64i32; break;
651  case X86::AND8ri: NewOpc = X86::AND8i8; break;
652  case X86::AND16ri: NewOpc = X86::AND16i16; break;
653  case X86::AND32ri: NewOpc = X86::AND32i32; break;
654  case X86::AND64ri32: NewOpc = X86::AND64i32; break;
655  case X86::CMP8ri: NewOpc = X86::CMP8i8; break;
656  case X86::CMP16ri: NewOpc = X86::CMP16i16; break;
657  case X86::CMP32ri: NewOpc = X86::CMP32i32; break;
658  case X86::CMP64ri32: NewOpc = X86::CMP64i32; break;
659  case X86::OR8ri: NewOpc = X86::OR8i8; break;
660  case X86::OR16ri: NewOpc = X86::OR16i16; break;
661  case X86::OR32ri: NewOpc = X86::OR32i32; break;
662  case X86::OR64ri32: NewOpc = X86::OR64i32; break;
663  case X86::SBB8ri: NewOpc = X86::SBB8i8; break;
664  case X86::SBB16ri: NewOpc = X86::SBB16i16; break;
665  case X86::SBB32ri: NewOpc = X86::SBB32i32; break;
666  case X86::SBB64ri32: NewOpc = X86::SBB64i32; break;
667  case X86::SUB8ri: NewOpc = X86::SUB8i8; break;
668  case X86::SUB16ri: NewOpc = X86::SUB16i16; break;
669  case X86::SUB32ri: NewOpc = X86::SUB32i32; break;
670  case X86::SUB64ri32: NewOpc = X86::SUB64i32; break;
671  case X86::TEST8ri: NewOpc = X86::TEST8i8; break;
672  case X86::TEST16ri: NewOpc = X86::TEST16i16; break;
673  case X86::TEST32ri: NewOpc = X86::TEST32i32; break;
674  case X86::TEST64ri32: NewOpc = X86::TEST64i32; break;
675  case X86::XOR8ri: NewOpc = X86::XOR8i8; break;
676  case X86::XOR16ri: NewOpc = X86::XOR16i16; break;
677  case X86::XOR32ri: NewOpc = X86::XOR32i32; break;
678  case X86::XOR64ri32: NewOpc = X86::XOR64i32; break;
679  }
680  SimplifyShortImmForm(OutMI, NewOpc);
681  break;
682  }
683 
684  // Try to shrink some forms of movsx.
685  case X86::MOVSX16rr8:
686  case X86::MOVSX32rr16:
687  case X86::MOVSX64rr32:
688  SimplifyMOVSX(OutMI);
689  break;
690  }
691 }
692 
693 void X86AsmPrinter::LowerTlsAddr(X86MCInstLower &MCInstLowering,
694  const MachineInstr &MI) {
695 
696  bool is64Bits = MI.getOpcode() == X86::TLS_addr64 ||
697  MI.getOpcode() == X86::TLS_base_addr64;
698 
699  bool needsPadding = MI.getOpcode() == X86::TLS_addr64;
700 
701  MCContext &context = OutStreamer->getContext();
702 
703  if (needsPadding)
704  EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
705 
707  switch (MI.getOpcode()) {
708  case X86::TLS_addr32:
709  case X86::TLS_addr64:
711  break;
712  case X86::TLS_base_addr32:
714  break;
715  case X86::TLS_base_addr64:
717  break;
718  default:
719  llvm_unreachable("unexpected opcode");
720  }
721 
722  MCSymbol *sym = MCInstLowering.GetSymbolFromOperand(MI.getOperand(3));
723  const MCSymbolRefExpr *symRef = MCSymbolRefExpr::create(sym, SRVK, context);
724 
725  MCInst LEA;
726  if (is64Bits) {
727  LEA.setOpcode(X86::LEA64r);
728  LEA.addOperand(MCOperand::createReg(X86::RDI)); // dest
729  LEA.addOperand(MCOperand::createReg(X86::RIP)); // base
730  LEA.addOperand(MCOperand::createImm(1)); // scale
731  LEA.addOperand(MCOperand::createReg(0)); // index
732  LEA.addOperand(MCOperand::createExpr(symRef)); // disp
733  LEA.addOperand(MCOperand::createReg(0)); // seg
734  } else if (SRVK == MCSymbolRefExpr::VK_TLSLDM) {
735  LEA.setOpcode(X86::LEA32r);
736  LEA.addOperand(MCOperand::createReg(X86::EAX)); // dest
737  LEA.addOperand(MCOperand::createReg(X86::EBX)); // base
738  LEA.addOperand(MCOperand::createImm(1)); // scale
739  LEA.addOperand(MCOperand::createReg(0)); // index
740  LEA.addOperand(MCOperand::createExpr(symRef)); // disp
741  LEA.addOperand(MCOperand::createReg(0)); // seg
742  } else {
743  LEA.setOpcode(X86::LEA32r);
744  LEA.addOperand(MCOperand::createReg(X86::EAX)); // dest
745  LEA.addOperand(MCOperand::createReg(0)); // base
746  LEA.addOperand(MCOperand::createImm(1)); // scale
747  LEA.addOperand(MCOperand::createReg(X86::EBX)); // index
748  LEA.addOperand(MCOperand::createExpr(symRef)); // disp
749  LEA.addOperand(MCOperand::createReg(0)); // seg
750  }
751  EmitAndCountInstruction(LEA);
752 
753  if (needsPadding) {
754  EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
755  EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
756  EmitAndCountInstruction(MCInstBuilder(X86::REX64_PREFIX));
757  }
758 
759  StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr";
760  MCSymbol *tlsGetAddr = context.getOrCreateSymbol(name);
761  const MCSymbolRefExpr *tlsRef =
762  MCSymbolRefExpr::create(tlsGetAddr,
764  context);
765 
766  EmitAndCountInstruction(MCInstBuilder(is64Bits ? X86::CALL64pcrel32
767  : X86::CALLpcrel32)
768  .addExpr(tlsRef));
769 }
770 
771 /// \brief Emit the largest nop instruction smaller than or equal to \p NumBytes
772 /// bytes. Return the size of nop emitted.
773 static unsigned EmitNop(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
774  const MCSubtargetInfo &STI) {
775  // This works only for 64bit. For 32bit we have to do additional checking if
776  // the CPU supports multi-byte nops.
777  assert(Is64Bit && "EmitNops only supports X86-64");
778 
779  unsigned NopSize;
780  unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;
781  Opc = IndexReg = Displacement = SegmentReg = 0;
782  BaseReg = X86::RAX;
783  ScaleVal = 1;
784  switch (NumBytes) {
785  case 0: llvm_unreachable("Zero nops?"); break;
786  case 1: NopSize = 1; Opc = X86::NOOP; break;
787  case 2: NopSize = 2; Opc = X86::XCHG16ar; break;
788  case 3: NopSize = 3; Opc = X86::NOOPL; break;
789  case 4: NopSize = 4; Opc = X86::NOOPL; Displacement = 8; break;
790  case 5: NopSize = 5; Opc = X86::NOOPL; Displacement = 8;
791  IndexReg = X86::RAX; break;
792  case 6: NopSize = 6; Opc = X86::NOOPW; Displacement = 8;
793  IndexReg = X86::RAX; break;
794  case 7: NopSize = 7; Opc = X86::NOOPL; Displacement = 512; break;
795  case 8: NopSize = 8; Opc = X86::NOOPL; Displacement = 512;
796  IndexReg = X86::RAX; break;
797  case 9: NopSize = 9; Opc = X86::NOOPW; Displacement = 512;
798  IndexReg = X86::RAX; break;
799  default: NopSize = 10; Opc = X86::NOOPW; Displacement = 512;
800  IndexReg = X86::RAX; SegmentReg = X86::CS; break;
801  }
802 
803  unsigned NumPrefixes = std::min(NumBytes - NopSize, 5U);
804  NopSize += NumPrefixes;
805  for (unsigned i = 0; i != NumPrefixes; ++i)
806  OS.EmitBytes("\x66");
807 
808  switch (Opc) {
809  default:
810  llvm_unreachable("Unexpected opcode");
811  break;
812  case X86::NOOP:
813  OS.EmitInstruction(MCInstBuilder(Opc), STI);
814  break;
815  case X86::XCHG16ar:
816  OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX), STI);
817  break;
818  case X86::NOOPL:
819  case X86::NOOPW:
821  .addReg(BaseReg)
822  .addImm(ScaleVal)
823  .addReg(IndexReg)
824  .addImm(Displacement)
825  .addReg(SegmentReg),
826  STI);
827  break;
828  }
829  assert(NopSize <= NumBytes && "We overemitted?");
830  return NopSize;
831 }
832 
833 /// \brief Emit the optimal amount of multi-byte nops on X86.
834 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
835  const MCSubtargetInfo &STI) {
836  unsigned NopsToEmit = NumBytes;
837  (void)NopsToEmit;
838  while (NumBytes) {
839  NumBytes -= EmitNop(OS, NumBytes, Is64Bit, STI);
840  assert(NopsToEmit >= NumBytes && "Emitted more than I asked for!");
841  }
842 }
843 
844 void X86AsmPrinter::LowerSTATEPOINT(const MachineInstr &MI,
845  X86MCInstLower &MCIL) {
846  assert(Subtarget->is64Bit() && "Statepoint currently only supports X86-64");
847 
848  StatepointOpers SOpers(&MI);
849  if (unsigned PatchBytes = SOpers.getNumPatchBytes()) {
850  EmitNops(*OutStreamer, PatchBytes, Subtarget->is64Bit(),
851  getSubtargetInfo());
852  } else {
853  // Lower call target and choose correct opcode
854  const MachineOperand &CallTarget = SOpers.getCallTarget();
855  MCOperand CallTargetMCOp;
856  unsigned CallOpcode;
857  switch (CallTarget.getType()) {
860  CallTargetMCOp = MCIL.LowerSymbolOperand(
861  CallTarget, MCIL.GetSymbolFromOperand(CallTarget));
862  CallOpcode = X86::CALL64pcrel32;
863  // Currently, we only support relative addressing with statepoints.
864  // Otherwise, we'll need a scratch register to hold the target
865  // address. You'll fail asserts during load & relocation if this
866  // symbol is to far away. (TODO: support non-relative addressing)
867  break;
869  CallTargetMCOp = MCOperand::createImm(CallTarget.getImm());
870  CallOpcode = X86::CALL64pcrel32;
871  // Currently, we only support relative addressing with statepoints.
872  // Otherwise, we'll need a scratch register to hold the target
873  // immediate. You'll fail asserts during load & relocation if this
874  // address is to far away. (TODO: support non-relative addressing)
875  break;
877  CallTargetMCOp = MCOperand::createReg(CallTarget.getReg());
878  CallOpcode = X86::CALL64r;
879  break;
880  default:
881  llvm_unreachable("Unsupported operand type in statepoint call target");
882  break;
883  }
884 
885  // Emit call
887  CallInst.setOpcode(CallOpcode);
888  CallInst.addOperand(CallTargetMCOp);
889  OutStreamer->EmitInstruction(CallInst, getSubtargetInfo());
890  }
891 
892  // Record our statepoint node in the same section used by STACKMAP
893  // and PATCHPOINT
894  SM.recordStatepoint(MI);
895 }
896 
897 void X86AsmPrinter::LowerFAULTING_OP(const MachineInstr &FaultingMI,
898  X86MCInstLower &MCIL) {
899  // FAULTING_LOAD_OP <def>, <faltinf type>, <MBB handler>,
900  // <opcode>, <operands>
901 
902  unsigned DefRegister = FaultingMI.getOperand(0).getReg();
904  static_cast<FaultMaps::FaultKind>(FaultingMI.getOperand(1).getImm());
905  MCSymbol *HandlerLabel = FaultingMI.getOperand(2).getMBB()->getSymbol();
906  unsigned Opcode = FaultingMI.getOperand(3).getImm();
907  unsigned OperandsBeginIdx = 4;
908 
909  assert(FK < FaultMaps::FaultKindMax && "Invalid Faulting Kind!");
910  FM.recordFaultingOp(FK, HandlerLabel);
911 
912  MCInst MI;
913  MI.setOpcode(Opcode);
914 
915  if (DefRegister != X86::NoRegister)
916  MI.addOperand(MCOperand::createReg(DefRegister));
917 
918  for (auto I = FaultingMI.operands_begin() + OperandsBeginIdx,
919  E = FaultingMI.operands_end();
920  I != E; ++I)
921  if (auto MaybeOperand = MCIL.LowerMachineOperand(&FaultingMI, *I))
922  MI.addOperand(MaybeOperand.getValue());
923 
924  OutStreamer->EmitInstruction(MI, getSubtargetInfo());
925 }
926 
927 void X86AsmPrinter::LowerFENTRY_CALL(const MachineInstr &MI,
928  X86MCInstLower &MCIL) {
929  bool Is64Bits = Subtarget->is64Bit();
930  MCContext &Ctx = OutStreamer->getContext();
931  MCSymbol *fentry = Ctx.getOrCreateSymbol("__fentry__");
932  const MCSymbolRefExpr *Op =
934 
935  EmitAndCountInstruction(
936  MCInstBuilder(Is64Bits ? X86::CALL64pcrel32 : X86::CALLpcrel32)
937  .addExpr(Op));
938 }
939 
940 void X86AsmPrinter::LowerPATCHABLE_OP(const MachineInstr &MI,
941  X86MCInstLower &MCIL) {
942  // PATCHABLE_OP minsize, opcode, operands
943 
944  unsigned MinSize = MI.getOperand(0).getImm();
945  unsigned Opcode = MI.getOperand(1).getImm();
946 
947  MCInst MCI;
948  MCI.setOpcode(Opcode);
949  for (auto &MO : make_range(MI.operands_begin() + 2, MI.operands_end()))
950  if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO))
951  MCI.addOperand(MaybeOperand.getValue());
952 
953  SmallString<256> Code;
955  raw_svector_ostream VecOS(Code);
956  CodeEmitter->encodeInstruction(MCI, VecOS, Fixups, getSubtargetInfo());
957 
958  if (Code.size() < MinSize) {
959  if (MinSize == 2 && Opcode == X86::PUSH64r) {
960  // This is an optimization that lets us get away without emitting a nop in
961  // many cases.
962  //
963  // NB! In some cases the encoding for PUSH64r (e.g. PUSH64r %R9) takes two
964  // bytes too, so the check on MinSize is important.
965  MCI.setOpcode(X86::PUSH64rmr);
966  } else {
967  unsigned NopSize = EmitNop(*OutStreamer, MinSize, Subtarget->is64Bit(),
968  getSubtargetInfo());
969  assert(NopSize == MinSize && "Could not implement MinSize!");
970  (void) NopSize;
971  }
972  }
973 
974  OutStreamer->EmitInstruction(MCI, getSubtargetInfo());
975 }
976 
977 // Lower a stackmap of the form:
978 // <id>, <shadowBytes>, ...
979 void X86AsmPrinter::LowerSTACKMAP(const MachineInstr &MI) {
980  SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
981  SM.recordStackMap(MI);
982  unsigned NumShadowBytes = MI.getOperand(1).getImm();
983  SMShadowTracker.reset(NumShadowBytes);
984 }
985 
986 // Lower a patchpoint of the form:
987 // [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ...
988 void X86AsmPrinter::LowerPATCHPOINT(const MachineInstr &MI,
989  X86MCInstLower &MCIL) {
990  assert(Subtarget->is64Bit() && "Patchpoint currently only supports X86-64");
991 
992  SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
993 
994  SM.recordPatchPoint(MI);
995 
996  PatchPointOpers opers(&MI);
997  unsigned ScratchIdx = opers.getNextScratchIdx();
998  unsigned EncodedBytes = 0;
999  const MachineOperand &CalleeMO = opers.getCallTarget();
1000 
1001  // Check for null target. If target is non-null (i.e. is non-zero or is
1002  // symbolic) then emit a call.
1003  if (!(CalleeMO.isImm() && !CalleeMO.getImm())) {
1004  MCOperand CalleeMCOp;
1005  switch (CalleeMO.getType()) {
1006  default:
1007  /// FIXME: Add a verifier check for bad callee types.
1008  llvm_unreachable("Unrecognized callee operand type.");
1010  if (CalleeMO.getImm())
1011  CalleeMCOp = MCOperand::createImm(CalleeMO.getImm());
1012  break;
1015  CalleeMCOp =
1016  MCIL.LowerSymbolOperand(CalleeMO,
1017  MCIL.GetSymbolFromOperand(CalleeMO));
1018  break;
1019  }
1020 
1021  // Emit MOV to materialize the target address and the CALL to target.
1022  // This is encoded with 12-13 bytes, depending on which register is used.
1023  unsigned ScratchReg = MI.getOperand(ScratchIdx).getReg();
1024  if (X86II::isX86_64ExtendedReg(ScratchReg))
1025  EncodedBytes = 13;
1026  else
1027  EncodedBytes = 12;
1028 
1029  EmitAndCountInstruction(
1030  MCInstBuilder(X86::MOV64ri).addReg(ScratchReg).addOperand(CalleeMCOp));
1031  EmitAndCountInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg));
1032  }
1033 
1034  // Emit padding.
1035  unsigned NumBytes = opers.getNumPatchBytes();
1036  assert(NumBytes >= EncodedBytes &&
1037  "Patchpoint can't request size less than the length of a call.");
1038 
1039  EmitNops(*OutStreamer, NumBytes - EncodedBytes, Subtarget->is64Bit(),
1040  getSubtargetInfo());
1041 }
1042 
1043 void X86AsmPrinter::LowerPATCHABLE_EVENT_CALL(const MachineInstr &MI,
1044  X86MCInstLower &MCIL) {
1045  assert(Subtarget->is64Bit() && "XRay custom events only supports X86-64");
1046 
1047  // We want to emit the following pattern, which follows the x86 calling
1048  // convention to prepare for the trampoline call to be patched in.
1049  //
1050  // .p2align 1, ...
1051  // .Lxray_event_sled_N:
1052  // jmp +N // jump across the instrumentation sled
1053  // ... // set up arguments in register
1054  // callq __xray_CustomEvent@plt // force dependency to symbol
1055  // ...
1056  // <jump here>
1057  //
1058  // After patching, it would look something like:
1059  //
1060  // nopw (2-byte nop)
1061  // ...
1062  // callq __xrayCustomEvent // already lowered
1063  // ...
1064  //
1065  // ---
1066  // First we emit the label and the jump.
1067  auto CurSled = OutContext.createTempSymbol("xray_event_sled_", true);
1068  OutStreamer->AddComment("# XRay Custom Event Log");
1069  OutStreamer->EmitCodeAlignment(2);
1070  OutStreamer->EmitLabel(CurSled);
1071 
1072  // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as
1073  // an operand (computed as an offset from the jmp instruction).
1074  // FIXME: Find another less hacky way do force the relative jump.
1075  OutStreamer->EmitBinaryData("\xeb\x0f");
1076 
1077  // The default C calling convention will place two arguments into %rcx and
1078  // %rdx -- so we only work with those.
1079  unsigned UsedRegs[] = {X86::RDI, X86::RSI};
1080  bool UsedMask[] = {false, false};
1081 
1082  // Then we put the operands in the %rdi and %rsi registers. We spill the
1083  // values in the register before we clobber them, and mark them as used in
1084  // UsedMask. In case the arguments are already in the correct register, we use
1085  // emit nops appropriately sized to keep the sled the same size in every
1086  // situation.
1087  for (unsigned I = 0; I < MI.getNumOperands(); ++I)
1088  if (auto Op = MCIL.LowerMachineOperand(&MI, MI.getOperand(I))) {
1089  assert(Op->isReg() && "Only support arguments in registers");
1090  if (Op->getReg() != UsedRegs[I]) {
1091  UsedMask[I] = true;
1092  EmitAndCountInstruction(
1093  MCInstBuilder(X86::PUSH64r).addReg(UsedRegs[I]));
1094  EmitAndCountInstruction(MCInstBuilder(X86::MOV64rr)
1095  .addReg(UsedRegs[I])
1096  .addReg(Op->getReg()));
1097  } else {
1098  EmitNops(*OutStreamer, 4, Subtarget->is64Bit(), getSubtargetInfo());
1099  }
1100  }
1101 
1102  // We emit a hard dependency on the __xray_CustomEvent symbol, which is the
1103  // name of the trampoline to be implemented by the XRay runtime.
1104  auto TSym = OutContext.getOrCreateSymbol("__xray_CustomEvent");
1106  if (isPositionIndependent())
1108 
1109  // Emit the call instruction.
1110  EmitAndCountInstruction(MCInstBuilder(X86::CALL64pcrel32)
1111  .addOperand(MCIL.LowerSymbolOperand(TOp, TSym)));
1112 
1113  // Restore caller-saved and used registers.
1114  for (unsigned I = sizeof UsedMask; I-- > 0;)
1115  if (UsedMask[I])
1116  EmitAndCountInstruction(MCInstBuilder(X86::POP64r).addReg(UsedRegs[I]));
1117  else
1118  EmitNops(*OutStreamer, 1, Subtarget->is64Bit(), getSubtargetInfo());
1119 
1120  OutStreamer->AddComment("xray custom event end.");
1121 
1122  // Record the sled version. Older versions of this sled were spelled
1123  // differently, so we let the runtime handle the different offsets we're
1124  // using.
1125  recordSled(CurSled, MI, SledKind::CUSTOM_EVENT, 1);
1126 }
1127 
1128 void X86AsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI,
1129  X86MCInstLower &MCIL) {
1130  // We want to emit the following pattern:
1131  //
1132  // .p2align 1, ...
1133  // .Lxray_sled_N:
1134  // jmp .tmpN
1135  // # 9 bytes worth of noops
1136  //
1137  // We need the 9 bytes because at runtime, we'd be patching over the full 11
1138  // bytes with the following pattern:
1139  //
1140  // mov %r10, <function id, 32-bit> // 6 bytes
1141  // call <relative offset, 32-bits> // 5 bytes
1142  //
1143  auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
1144  OutStreamer->EmitCodeAlignment(2);
1145  OutStreamer->EmitLabel(CurSled);
1146 
1147  // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as
1148  // an operand (computed as an offset from the jmp instruction).
1149  // FIXME: Find another less hacky way do force the relative jump.
1150  OutStreamer->EmitBytes("\xeb\x09");
1151  EmitNops(*OutStreamer, 9, Subtarget->is64Bit(), getSubtargetInfo());
1152  recordSled(CurSled, MI, SledKind::FUNCTION_ENTER);
1153 }
1154 
1155 void X86AsmPrinter::LowerPATCHABLE_RET(const MachineInstr &MI,
1156  X86MCInstLower &MCIL) {
1157  // Since PATCHABLE_RET takes the opcode of the return statement as an
1158  // argument, we use that to emit the correct form of the RET that we want.
1159  // i.e. when we see this:
1160  //
1161  // PATCHABLE_RET X86::RET ...
1162  //
1163  // We should emit the RET followed by sleds.
1164  //
1165  // .p2align 1, ...
1166  // .Lxray_sled_N:
1167  // ret # or equivalent instruction
1168  // # 10 bytes worth of noops
1169  //
1170  // This just makes sure that the alignment for the next instruction is 2.
1171  auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
1172  OutStreamer->EmitCodeAlignment(2);
1173  OutStreamer->EmitLabel(CurSled);
1174  unsigned OpCode = MI.getOperand(0).getImm();
1175  MCInst Ret;
1176  Ret.setOpcode(OpCode);
1177  for (auto &MO : make_range(MI.operands_begin() + 1, MI.operands_end()))
1178  if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO))
1179  Ret.addOperand(MaybeOperand.getValue());
1180  OutStreamer->EmitInstruction(Ret, getSubtargetInfo());
1181  EmitNops(*OutStreamer, 10, Subtarget->is64Bit(), getSubtargetInfo());
1182  recordSled(CurSled, MI, SledKind::FUNCTION_EXIT);
1183 }
1184 
1185 void X86AsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI, X86MCInstLower &MCIL) {
1186  // Like PATCHABLE_RET, we have the actual instruction in the operands to this
1187  // instruction so we lower that particular instruction and its operands.
1188  // Unlike PATCHABLE_RET though, we put the sled before the JMP, much like how
1189  // we do it for PATCHABLE_FUNCTION_ENTER. The sled should be very similar to
1190  // the PATCHABLE_FUNCTION_ENTER case, followed by the lowering of the actual
1191  // tail call much like how we have it in PATCHABLE_RET.
1192  auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
1193  OutStreamer->EmitCodeAlignment(2);
1194  OutStreamer->EmitLabel(CurSled);
1196 
1197  // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as
1198  // an operand (computed as an offset from the jmp instruction).
1199  // FIXME: Find another less hacky way do force the relative jump.
1200  OutStreamer->EmitBytes("\xeb\x09");
1201  EmitNops(*OutStreamer, 9, Subtarget->is64Bit(), getSubtargetInfo());
1202  OutStreamer->EmitLabel(Target);
1203  recordSled(CurSled, MI, SledKind::TAIL_CALL);
1204 
1205  unsigned OpCode = MI.getOperand(0).getImm();
1206  MCInst TC;
1207  TC.setOpcode(OpCode);
1208 
1209  // Before emitting the instruction, add a comment to indicate that this is
1210  // indeed a tail call.
1211  OutStreamer->AddComment("TAILCALL");
1212  for (auto &MO : make_range(MI.operands_begin() + 1, MI.operands_end()))
1213  if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO))
1214  TC.addOperand(MaybeOperand.getValue());
1215  OutStreamer->EmitInstruction(TC, getSubtargetInfo());
1216 }
1217 
1218 // Returns instruction preceding MBBI in MachineFunction.
1219 // If MBBI is the first instruction of the first basic block, returns null.
1222  const MachineBasicBlock *MBB = MBBI->getParent();
1223  while (MBBI == MBB->begin()) {
1224  if (MBB == &MBB->getParent()->front())
1226  MBB = MBB->getPrevNode();
1227  MBBI = MBB->end();
1228  }
1229  return --MBBI;
1230 }
1231 
1233  const MachineOperand &Op) {
1234  if (!Op.isCPI())
1235  return nullptr;
1236 
1239  const MachineConstantPoolEntry &ConstantEntry =
1240  Constants[Op.getIndex()];
1241 
1242  // Bail if this is a machine constant pool entry, we won't be able to dig out
1243  // anything useful.
1244  if (ConstantEntry.isMachineConstantPoolEntry())
1245  return nullptr;
1246 
1247  auto *C = dyn_cast<Constant>(ConstantEntry.Val.ConstVal);
1248  assert((!C || ConstantEntry.getType() == C->getType()) &&
1249  "Expected a constant of the same type!");
1250  return C;
1251 }
1252 
1253 static std::string getShuffleComment(const MachineInstr *MI,
1254  unsigned SrcOp1Idx,
1255  unsigned SrcOp2Idx,
1256  ArrayRef<int> Mask) {
1257  std::string Comment;
1258 
1259  // Compute the name for a register. This is really goofy because we have
1260  // multiple instruction printers that could (in theory) use different
1261  // names. Fortunately most people use the ATT style (outside of Windows)
1262  // and they actually agree on register naming here. Ultimately, this is
1263  // a comment, and so its OK if it isn't perfect.
1264  auto GetRegisterName = [](unsigned RegNum) -> StringRef {
1265  return X86ATTInstPrinter::getRegisterName(RegNum);
1266  };
1267 
1268  const MachineOperand &DstOp = MI->getOperand(0);
1269  const MachineOperand &SrcOp1 = MI->getOperand(SrcOp1Idx);
1270  const MachineOperand &SrcOp2 = MI->getOperand(SrcOp2Idx);
1271 
1272  StringRef DstName = DstOp.isReg() ? GetRegisterName(DstOp.getReg()) : "mem";
1273  StringRef Src1Name =
1274  SrcOp1.isReg() ? GetRegisterName(SrcOp1.getReg()) : "mem";
1275  StringRef Src2Name =
1276  SrcOp2.isReg() ? GetRegisterName(SrcOp2.getReg()) : "mem";
1277 
1278  // One source operand, fix the mask to print all elements in one span.
1279  SmallVector<int, 8> ShuffleMask(Mask.begin(), Mask.end());
1280  if (Src1Name == Src2Name)
1281  for (int i = 0, e = ShuffleMask.size(); i != e; ++i)
1282  if (ShuffleMask[i] >= e)
1283  ShuffleMask[i] -= e;
1284 
1285  raw_string_ostream CS(Comment);
1286  CS << DstName;
1287 
1288  // Handle AVX512 MASK/MASXZ write mask comments.
1289  // MASK: zmmX {%kY}
1290  // MASKZ: zmmX {%kY} {z}
1291  if (SrcOp1Idx > 1) {
1292  assert((SrcOp1Idx == 2 || SrcOp1Idx == 3) && "Unexpected writemask");
1293 
1294  const MachineOperand &WriteMaskOp = MI->getOperand(SrcOp1Idx - 1);
1295  if (WriteMaskOp.isReg()) {
1296  CS << " {%" << GetRegisterName(WriteMaskOp.getReg()) << "}";
1297 
1298  if (SrcOp1Idx == 2) {
1299  CS << " {z}";
1300  }
1301  }
1302  }
1303 
1304  CS << " = ";
1305 
1306  for (int i = 0, e = ShuffleMask.size(); i != e; ++i) {
1307  if (i != 0)
1308  CS << ",";
1309  if (ShuffleMask[i] == SM_SentinelZero) {
1310  CS << "zero";
1311  continue;
1312  }
1313 
1314  // Otherwise, it must come from src1 or src2. Print the span of elements
1315  // that comes from this src.
1316  bool isSrc1 = ShuffleMask[i] < (int)e;
1317  CS << (isSrc1 ? Src1Name : Src2Name) << '[';
1318 
1319  bool IsFirst = true;
1320  while (i != e && ShuffleMask[i] != SM_SentinelZero &&
1321  (ShuffleMask[i] < (int)e) == isSrc1) {
1322  if (!IsFirst)
1323  CS << ',';
1324  else
1325  IsFirst = false;
1326  if (ShuffleMask[i] == SM_SentinelUndef)
1327  CS << "u";
1328  else
1329  CS << ShuffleMask[i] % (int)e;
1330  ++i;
1331  }
1332  CS << ']';
1333  --i; // For loop increments element #.
1334  }
1335  CS.flush();
1336 
1337  return Comment;
1338 }
1339 
1340 static void printConstant(const Constant *COp, raw_ostream &CS) {
1341  if (isa<UndefValue>(COp)) {
1342  CS << "u";
1343  } else if (auto *CI = dyn_cast<ConstantInt>(COp)) {
1344  if (CI->getBitWidth() <= 64) {
1345  CS << CI->getZExtValue();
1346  } else {
1347  // print multi-word constant as (w0,w1)
1348  const auto &Val = CI->getValue();
1349  CS << "(";
1350  for (int i = 0, N = Val.getNumWords(); i < N; ++i) {
1351  if (i > 0)
1352  CS << ",";
1353  CS << Val.getRawData()[i];
1354  }
1355  CS << ")";
1356  }
1357  } else if (auto *CF = dyn_cast<ConstantFP>(COp)) {
1358  SmallString<32> Str;
1359  CF->getValueAPF().toString(Str);
1360  CS << Str;
1361  } else {
1362  CS << "?";
1363  }
1364 }
1365 
1367  X86MCInstLower MCInstLowering(*MF, *this);
1368  const X86RegisterInfo *RI = MF->getSubtarget<X86Subtarget>().getRegisterInfo();
1369 
1370  // Add a comment about EVEX-2-VEX compression for AVX-512 instrs that
1371  // are compressed from EVEX encoding to VEX encoding.
1373  if (MI->getAsmPrinterFlags() & AC_EVEX_2_VEX)
1374  OutStreamer->AddComment("EVEX TO VEX Compression ", false);
1375  }
1376 
1377  switch (MI->getOpcode()) {
1378  case TargetOpcode::DBG_VALUE:
1379  llvm_unreachable("Should be handled target independently");
1380 
1381  // Emit nothing here but a comment if we can.
1382  case X86::Int_MemBarrier:
1383  OutStreamer->emitRawComment("MEMBARRIER");
1384  return;
1385 
1386 
1387  case X86::EH_RETURN:
1388  case X86::EH_RETURN64: {
1389  // Lower these as normal, but add some comments.
1390  unsigned Reg = MI->getOperand(0).getReg();
1391  OutStreamer->AddComment(StringRef("eh_return, addr: %") +
1393  break;
1394  }
1395  case X86::CLEANUPRET: {
1396  // Lower these as normal, but add some comments.
1397  OutStreamer->AddComment("CLEANUPRET");
1398  break;
1399  }
1400 
1401  case X86::CATCHRET: {
1402  // Lower these as normal, but add some comments.
1403  OutStreamer->AddComment("CATCHRET");
1404  break;
1405  }
1406 
1407  case X86::TAILJMPr:
1408  case X86::TAILJMPm:
1409  case X86::TAILJMPd:
1410  case X86::TAILJMPd_CC:
1411  case X86::TAILJMPr64:
1412  case X86::TAILJMPm64:
1413  case X86::TAILJMPd64:
1414  case X86::TAILJMPd64_CC:
1415  case X86::TAILJMPr64_REX:
1416  case X86::TAILJMPm64_REX:
1417  // Lower these as normal, but add some comments.
1418  OutStreamer->AddComment("TAILCALL");
1419  break;
1420 
1421  case X86::TLS_addr32:
1422  case X86::TLS_addr64:
1423  case X86::TLS_base_addr32:
1424  case X86::TLS_base_addr64:
1425  return LowerTlsAddr(MCInstLowering, *MI);
1426 
1427  case X86::MOVPC32r: {
1428  // This is a pseudo op for a two instruction sequence with a label, which
1429  // looks like:
1430  // call "L1$pb"
1431  // "L1$pb":
1432  // popl %esi
1433 
1434  // Emit the call.
1435  MCSymbol *PICBase = MF->getPICBaseSymbol();
1436  // FIXME: We would like an efficient form for this, so we don't have to do a
1437  // lot of extra uniquing.
1438  EmitAndCountInstruction(MCInstBuilder(X86::CALLpcrel32)
1439  .addExpr(MCSymbolRefExpr::create(PICBase, OutContext)));
1440 
1441  const X86FrameLowering* FrameLowering =
1442  MF->getSubtarget<X86Subtarget>().getFrameLowering();
1443  bool hasFP = FrameLowering->hasFP(*MF);
1444 
1445  // TODO: This is needed only if we require precise CFA.
1446  bool HasActiveDwarfFrame = OutStreamer->getNumFrameInfos() &&
1447  !OutStreamer->getDwarfFrameInfos().back().End;
1448 
1449  int stackGrowth = -RI->getSlotSize();
1450 
1451  if (HasActiveDwarfFrame && !hasFP) {
1452  OutStreamer->EmitCFIAdjustCfaOffset(-stackGrowth);
1453  }
1454 
1455  // Emit the label.
1456  OutStreamer->EmitLabel(PICBase);
1457 
1458  // popl $reg
1459  EmitAndCountInstruction(MCInstBuilder(X86::POP32r)
1460  .addReg(MI->getOperand(0).getReg()));
1461 
1462  if (HasActiveDwarfFrame && !hasFP) {
1463  OutStreamer->EmitCFIAdjustCfaOffset(stackGrowth);
1464  }
1465  return;
1466  }
1467 
1468  case X86::ADD32ri: {
1469  // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
1471  break;
1472 
1473  // Okay, we have something like:
1474  // EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
1475 
1476  // For this, we want to print something like:
1477  // MYGLOBAL + (. - PICBASE)
1478  // However, we can't generate a ".", so just emit a new label here and refer
1479  // to it.
1480  MCSymbol *DotSym = OutContext.createTempSymbol();
1481  OutStreamer->EmitLabel(DotSym);
1482 
1483  // Now that we have emitted the label, lower the complex operand expression.
1484  MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
1485 
1486  const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext);
1487  const MCExpr *PICBase =
1489  DotExpr = MCBinaryExpr::createSub(DotExpr, PICBase, OutContext);
1490 
1492  DotExpr, OutContext);
1493 
1494  EmitAndCountInstruction(MCInstBuilder(X86::ADD32ri)
1495  .addReg(MI->getOperand(0).getReg())
1496  .addReg(MI->getOperand(1).getReg())
1497  .addExpr(DotExpr));
1498  return;
1499  }
1500  case TargetOpcode::STATEPOINT:
1501  return LowerSTATEPOINT(*MI, MCInstLowering);
1502 
1503  case TargetOpcode::FAULTING_OP:
1504  return LowerFAULTING_OP(*MI, MCInstLowering);
1505 
1506  case TargetOpcode::FENTRY_CALL:
1507  return LowerFENTRY_CALL(*MI, MCInstLowering);
1508 
1509  case TargetOpcode::PATCHABLE_OP:
1510  return LowerPATCHABLE_OP(*MI, MCInstLowering);
1511 
1512  case TargetOpcode::STACKMAP:
1513  return LowerSTACKMAP(*MI);
1514 
1515  case TargetOpcode::PATCHPOINT:
1516  return LowerPATCHPOINT(*MI, MCInstLowering);
1517 
1518  case TargetOpcode::PATCHABLE_FUNCTION_ENTER:
1519  return LowerPATCHABLE_FUNCTION_ENTER(*MI, MCInstLowering);
1520 
1521  case TargetOpcode::PATCHABLE_RET:
1522  return LowerPATCHABLE_RET(*MI, MCInstLowering);
1523 
1524  case TargetOpcode::PATCHABLE_TAIL_CALL:
1525  return LowerPATCHABLE_TAIL_CALL(*MI, MCInstLowering);
1526 
1527  case TargetOpcode::PATCHABLE_EVENT_CALL:
1528  return LowerPATCHABLE_EVENT_CALL(*MI, MCInstLowering);
1529 
1530  case X86::MORESTACK_RET:
1531  EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
1532  return;
1533 
1534  case X86::MORESTACK_RET_RESTORE_R10:
1535  // Return, then restore R10.
1536  EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
1537  EmitAndCountInstruction(MCInstBuilder(X86::MOV64rr)
1538  .addReg(X86::R10)
1539  .addReg(X86::RAX));
1540  return;
1541 
1542  case X86::SEH_PushReg:
1543  assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?");
1544  OutStreamer->EmitWinCFIPushReg(RI->getSEHRegNum(MI->getOperand(0).getImm()));
1545  return;
1546 
1547  case X86::SEH_SaveReg:
1548  assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?");
1549  OutStreamer->EmitWinCFISaveReg(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1550  MI->getOperand(1).getImm());
1551  return;
1552 
1553  case X86::SEH_SaveXMM:
1554  assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?");
1555  OutStreamer->EmitWinCFISaveXMM(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1556  MI->getOperand(1).getImm());
1557  return;
1558 
1559  case X86::SEH_StackAlloc:
1560  assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?");
1561  OutStreamer->EmitWinCFIAllocStack(MI->getOperand(0).getImm());
1562  return;
1563 
1564  case X86::SEH_SetFrame:
1565  assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?");
1566  OutStreamer->EmitWinCFISetFrame(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1567  MI->getOperand(1).getImm());
1568  return;
1569 
1570  case X86::SEH_PushFrame:
1571  assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?");
1572  OutStreamer->EmitWinCFIPushFrame(MI->getOperand(0).getImm());
1573  return;
1574 
1575  case X86::SEH_EndPrologue:
1576  assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?");
1577  OutStreamer->EmitWinCFIEndProlog();
1578  return;
1579 
1580  case X86::SEH_Epilogue: {
1581  assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?");
1583  // Check if preceded by a call and emit nop if so.
1584  for (MBBI = PrevCrossBBInst(MBBI);
1586  MBBI = PrevCrossBBInst(MBBI)) {
1587  // Conservatively assume that pseudo instructions don't emit code and keep
1588  // looking for a call. We may emit an unnecessary nop in some cases.
1589  if (!MBBI->isPseudo()) {
1590  if (MBBI->isCall())
1591  EmitAndCountInstruction(MCInstBuilder(X86::NOOP));
1592  break;
1593  }
1594  }
1595  return;
1596  }
1597 
1598  // Lower PSHUFB and VPERMILP normally but add a comment if we can find
1599  // a constant shuffle mask. We won't be able to do this at the MC layer
1600  // because the mask isn't an immediate.
1601  case X86::PSHUFBrm:
1602  case X86::VPSHUFBrm:
1603  case X86::VPSHUFBYrm:
1604  case X86::VPSHUFBZ128rm:
1605  case X86::VPSHUFBZ128rmk:
1606  case X86::VPSHUFBZ128rmkz:
1607  case X86::VPSHUFBZ256rm:
1608  case X86::VPSHUFBZ256rmk:
1609  case X86::VPSHUFBZ256rmkz:
1610  case X86::VPSHUFBZrm:
1611  case X86::VPSHUFBZrmk:
1612  case X86::VPSHUFBZrmkz: {
1613  if (!OutStreamer->isVerboseAsm())
1614  break;
1615  unsigned SrcIdx, MaskIdx;
1616  switch (MI->getOpcode()) {
1617  default: llvm_unreachable("Invalid opcode");
1618  case X86::PSHUFBrm:
1619  case X86::VPSHUFBrm:
1620  case X86::VPSHUFBYrm:
1621  case X86::VPSHUFBZ128rm:
1622  case X86::VPSHUFBZ256rm:
1623  case X86::VPSHUFBZrm:
1624  SrcIdx = 1; MaskIdx = 5; break;
1625  case X86::VPSHUFBZ128rmkz:
1626  case X86::VPSHUFBZ256rmkz:
1627  case X86::VPSHUFBZrmkz:
1628  SrcIdx = 2; MaskIdx = 6; break;
1629  case X86::VPSHUFBZ128rmk:
1630  case X86::VPSHUFBZ256rmk:
1631  case X86::VPSHUFBZrmk:
1632  SrcIdx = 3; MaskIdx = 7; break;
1633  }
1634 
1635  assert(MI->getNumOperands() >= 6 &&
1636  "We should always have at least 6 operands!");
1637 
1638  const MachineOperand &MaskOp = MI->getOperand(MaskIdx);
1639  if (auto *C = getConstantFromPool(*MI, MaskOp)) {
1641  DecodePSHUFBMask(C, Mask);
1642  if (!Mask.empty())
1643  OutStreamer->AddComment(getShuffleComment(MI, SrcIdx, SrcIdx, Mask),
1645  }
1646  break;
1647  }
1648 
1649  case X86::VPERMILPSrm:
1650  case X86::VPERMILPSYrm:
1651  case X86::VPERMILPSZ128rm:
1652  case X86::VPERMILPSZ128rmk:
1653  case X86::VPERMILPSZ128rmkz:
1654  case X86::VPERMILPSZ256rm:
1655  case X86::VPERMILPSZ256rmk:
1656  case X86::VPERMILPSZ256rmkz:
1657  case X86::VPERMILPSZrm:
1658  case X86::VPERMILPSZrmk:
1659  case X86::VPERMILPSZrmkz:
1660  case X86::VPERMILPDrm:
1661  case X86::VPERMILPDYrm:
1662  case X86::VPERMILPDZ128rm:
1663  case X86::VPERMILPDZ128rmk:
1664  case X86::VPERMILPDZ128rmkz:
1665  case X86::VPERMILPDZ256rm:
1666  case X86::VPERMILPDZ256rmk:
1667  case X86::VPERMILPDZ256rmkz:
1668  case X86::VPERMILPDZrm:
1669  case X86::VPERMILPDZrmk:
1670  case X86::VPERMILPDZrmkz: {
1671  if (!OutStreamer->isVerboseAsm())
1672  break;
1673  unsigned SrcIdx, MaskIdx;
1674  unsigned ElSize;
1675  switch (MI->getOpcode()) {
1676  default: llvm_unreachable("Invalid opcode");
1677  case X86::VPERMILPSrm:
1678  case X86::VPERMILPSYrm:
1679  case X86::VPERMILPSZ128rm:
1680  case X86::VPERMILPSZ256rm:
1681  case X86::VPERMILPSZrm:
1682  SrcIdx = 1; MaskIdx = 5; ElSize = 32; break;
1683  case X86::VPERMILPSZ128rmkz:
1684  case X86::VPERMILPSZ256rmkz:
1685  case X86::VPERMILPSZrmkz:
1686  SrcIdx = 2; MaskIdx = 6; ElSize = 32; break;
1687  case X86::VPERMILPSZ128rmk:
1688  case X86::VPERMILPSZ256rmk:
1689  case X86::VPERMILPSZrmk:
1690  SrcIdx = 3; MaskIdx = 7; ElSize = 32; break;
1691  case X86::VPERMILPDrm:
1692  case X86::VPERMILPDYrm:
1693  case X86::VPERMILPDZ128rm:
1694  case X86::VPERMILPDZ256rm:
1695  case X86::VPERMILPDZrm:
1696  SrcIdx = 1; MaskIdx = 5; ElSize = 64; break;
1697  case X86::VPERMILPDZ128rmkz:
1698  case X86::VPERMILPDZ256rmkz:
1699  case X86::VPERMILPDZrmkz:
1700  SrcIdx = 2; MaskIdx = 6; ElSize = 64; break;
1701  case X86::VPERMILPDZ128rmk:
1702  case X86::VPERMILPDZ256rmk:
1703  case X86::VPERMILPDZrmk:
1704  SrcIdx = 3; MaskIdx = 7; ElSize = 64; break;
1705  }
1706 
1707  assert(MI->getNumOperands() >= 6 &&
1708  "We should always have at least 6 operands!");
1709 
1710  const MachineOperand &MaskOp = MI->getOperand(MaskIdx);
1711  if (auto *C = getConstantFromPool(*MI, MaskOp)) {
1713  DecodeVPERMILPMask(C, ElSize, Mask);
1714  if (!Mask.empty())
1715  OutStreamer->AddComment(getShuffleComment(MI, SrcIdx, SrcIdx, Mask),
1717  }
1718  break;
1719  }
1720 
1721  case X86::VPERMIL2PDrm:
1722  case X86::VPERMIL2PSrm:
1723  case X86::VPERMIL2PDYrm:
1724  case X86::VPERMIL2PSYrm: {
1725  if (!OutStreamer->isVerboseAsm())
1726  break;
1727  assert(MI->getNumOperands() >= 8 &&
1728  "We should always have at least 8 operands!");
1729 
1730  const MachineOperand &CtrlOp = MI->getOperand(MI->getNumOperands() - 1);
1731  if (!CtrlOp.isImm())
1732  break;
1733 
1734  unsigned ElSize;
1735  switch (MI->getOpcode()) {
1736  default: llvm_unreachable("Invalid opcode");
1737  case X86::VPERMIL2PSrm: case X86::VPERMIL2PSYrm: ElSize = 32; break;
1738  case X86::VPERMIL2PDrm: case X86::VPERMIL2PDYrm: ElSize = 64; break;
1739  }
1740 
1741  const MachineOperand &MaskOp = MI->getOperand(6);
1742  if (auto *C = getConstantFromPool(*MI, MaskOp)) {
1744  DecodeVPERMIL2PMask(C, (unsigned)CtrlOp.getImm(), ElSize, Mask);
1745  if (!Mask.empty())
1746  OutStreamer->AddComment(getShuffleComment(MI, 1, 2, Mask),
1748  }
1749  break;
1750  }
1751 
1752  case X86::VPPERMrrm: {
1753  if (!OutStreamer->isVerboseAsm())
1754  break;
1755  assert(MI->getNumOperands() >= 7 &&
1756  "We should always have at least 7 operands!");
1757 
1758  const MachineOperand &MaskOp = MI->getOperand(6);
1759  if (auto *C = getConstantFromPool(*MI, MaskOp)) {
1761  DecodeVPPERMMask(C, Mask);
1762  if (!Mask.empty())
1763  OutStreamer->AddComment(getShuffleComment(MI, 1, 2, Mask),
1765  }
1766  break;
1767  }
1768 
1769 #define MOV_CASE(Prefix, Suffix) \
1770  case X86::Prefix##MOVAPD##Suffix##rm: \
1771  case X86::Prefix##MOVAPS##Suffix##rm: \
1772  case X86::Prefix##MOVUPD##Suffix##rm: \
1773  case X86::Prefix##MOVUPS##Suffix##rm: \
1774  case X86::Prefix##MOVDQA##Suffix##rm: \
1775  case X86::Prefix##MOVDQU##Suffix##rm:
1776 
1777 #define MOV_AVX512_CASE(Suffix) \
1778  case X86::VMOVDQA64##Suffix##rm: \
1779  case X86::VMOVDQA32##Suffix##rm: \
1780  case X86::VMOVDQU64##Suffix##rm: \
1781  case X86::VMOVDQU32##Suffix##rm: \
1782  case X86::VMOVDQU16##Suffix##rm: \
1783  case X86::VMOVDQU8##Suffix##rm: \
1784  case X86::VMOVAPS##Suffix##rm: \
1785  case X86::VMOVAPD##Suffix##rm: \
1786  case X86::VMOVUPS##Suffix##rm: \
1787  case X86::VMOVUPD##Suffix##rm:
1788 
1789 #define CASE_ALL_MOV_RM() \
1790  MOV_CASE(, ) /* SSE */ \
1791  MOV_CASE(V, ) /* AVX-128 */ \
1792  MOV_CASE(V, Y) /* AVX-256 */ \
1793  MOV_AVX512_CASE(Z) \
1794  MOV_AVX512_CASE(Z256) \
1795  MOV_AVX512_CASE(Z128)
1796 
1797  // For loads from a constant pool to a vector register, print the constant
1798  // loaded.
1799  CASE_ALL_MOV_RM()
1800  case X86::VBROADCASTF128:
1801  case X86::VBROADCASTI128:
1802  case X86::VBROADCASTF32X4Z256rm:
1803  case X86::VBROADCASTF32X4rm:
1804  case X86::VBROADCASTF32X8rm:
1805  case X86::VBROADCASTF64X2Z128rm:
1806  case X86::VBROADCASTF64X2rm:
1807  case X86::VBROADCASTF64X4rm:
1808  case X86::VBROADCASTI32X4Z256rm:
1809  case X86::VBROADCASTI32X4rm:
1810  case X86::VBROADCASTI32X8rm:
1811  case X86::VBROADCASTI64X2Z128rm:
1812  case X86::VBROADCASTI64X2rm:
1813  case X86::VBROADCASTI64X4rm:
1814  if (!OutStreamer->isVerboseAsm())
1815  break;
1816  if (MI->getNumOperands() <= 4)
1817  break;
1818  if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) {
1819  int NumLanes = 1;
1820  // Override NumLanes for the broadcast instructions.
1821  switch (MI->getOpcode()) {
1822  case X86::VBROADCASTF128: NumLanes = 2; break;
1823  case X86::VBROADCASTI128: NumLanes = 2; break;
1824  case X86::VBROADCASTF32X4Z256rm: NumLanes = 2; break;
1825  case X86::VBROADCASTF32X4rm: NumLanes = 4; break;
1826  case X86::VBROADCASTF32X8rm: NumLanes = 2; break;
1827  case X86::VBROADCASTF64X2Z128rm: NumLanes = 2; break;
1828  case X86::VBROADCASTF64X2rm: NumLanes = 4; break;
1829  case X86::VBROADCASTF64X4rm: NumLanes = 2; break;
1830  case X86::VBROADCASTI32X4Z256rm: NumLanes = 2; break;
1831  case X86::VBROADCASTI32X4rm: NumLanes = 4; break;
1832  case X86::VBROADCASTI32X8rm: NumLanes = 2; break;
1833  case X86::VBROADCASTI64X2Z128rm: NumLanes = 2; break;
1834  case X86::VBROADCASTI64X2rm: NumLanes = 4; break;
1835  case X86::VBROADCASTI64X4rm: NumLanes = 2; break;
1836  }
1837 
1838  std::string Comment;
1839  raw_string_ostream CS(Comment);
1840  const MachineOperand &DstOp = MI->getOperand(0);
1841  CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = ";
1842  if (auto *CDS = dyn_cast<ConstantDataSequential>(C)) {
1843  CS << "[";
1844  for (int l = 0; l != NumLanes; ++l) {
1845  for (int i = 0, NumElements = CDS->getNumElements(); i < NumElements; ++i) {
1846  if (i != 0 || l != 0)
1847  CS << ",";
1848  if (CDS->getElementType()->isIntegerTy())
1849  CS << CDS->getElementAsInteger(i);
1850  else if (CDS->getElementType()->isFloatTy())
1851  CS << CDS->getElementAsFloat(i);
1852  else if (CDS->getElementType()->isDoubleTy())
1853  CS << CDS->getElementAsDouble(i);
1854  else
1855  CS << "?";
1856  }
1857  }
1858  CS << "]";
1859  OutStreamer->AddComment(CS.str(), !EnablePrintSchedInfo);
1860  } else if (auto *CV = dyn_cast<ConstantVector>(C)) {
1861  CS << "<";
1862  for (int l = 0; l != NumLanes; ++l) {
1863  for (int i = 0, NumOperands = CV->getNumOperands(); i < NumOperands; ++i) {
1864  if (i != 0 || l != 0)
1865  CS << ",";
1866  printConstant(CV->getOperand(i), CS);
1867  }
1868  }
1869  CS << ">";
1870  OutStreamer->AddComment(CS.str(), !EnablePrintSchedInfo);
1871  }
1872  }
1873  break;
1874  case X86::VBROADCASTSSrm:
1875  case X86::VBROADCASTSSYrm:
1876  case X86::VBROADCASTSSZ128m:
1877  case X86::VBROADCASTSSZ256m:
1878  case X86::VBROADCASTSSZm:
1879  case X86::VBROADCASTSDYrm:
1880  case X86::VBROADCASTSDZ256m:
1881  case X86::VBROADCASTSDZm:
1882  case X86::VPBROADCASTBrm:
1883  case X86::VPBROADCASTBYrm:
1884  case X86::VPBROADCASTBZ128m:
1885  case X86::VPBROADCASTBZ256m:
1886  case X86::VPBROADCASTBZm:
1887  case X86::VPBROADCASTDrm:
1888  case X86::VPBROADCASTDYrm:
1889  case X86::VPBROADCASTDZ128m:
1890  case X86::VPBROADCASTDZ256m:
1891  case X86::VPBROADCASTDZm:
1892  case X86::VPBROADCASTQrm:
1893  case X86::VPBROADCASTQYrm:
1894  case X86::VPBROADCASTQZ128m:
1895  case X86::VPBROADCASTQZ256m:
1896  case X86::VPBROADCASTQZm:
1897  case X86::VPBROADCASTWrm:
1898  case X86::VPBROADCASTWYrm:
1899  case X86::VPBROADCASTWZ128m:
1900  case X86::VPBROADCASTWZ256m:
1901  case X86::VPBROADCASTWZm:
1902  if (!OutStreamer->isVerboseAsm())
1903  break;
1904  if (MI->getNumOperands() <= 4)
1905  break;
1906  if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) {
1907  int NumElts;
1908  switch (MI->getOpcode()) {
1909  default: llvm_unreachable("Invalid opcode");
1910  case X86::VBROADCASTSSrm: NumElts = 4; break;
1911  case X86::VBROADCASTSSYrm: NumElts = 8; break;
1912  case X86::VBROADCASTSSZ128m: NumElts = 4; break;
1913  case X86::VBROADCASTSSZ256m: NumElts = 8; break;
1914  case X86::VBROADCASTSSZm: NumElts = 16; break;
1915  case X86::VBROADCASTSDYrm: NumElts = 4; break;
1916  case X86::VBROADCASTSDZ256m: NumElts = 4; break;
1917  case X86::VBROADCASTSDZm: NumElts = 8; break;
1918  case X86::VPBROADCASTBrm: NumElts = 16; break;
1919  case X86::VPBROADCASTBYrm: NumElts = 32; break;
1920  case X86::VPBROADCASTBZ128m: NumElts = 16; break;
1921  case X86::VPBROADCASTBZ256m: NumElts = 32; break;
1922  case X86::VPBROADCASTBZm: NumElts = 64; break;
1923  case X86::VPBROADCASTDrm: NumElts = 4; break;
1924  case X86::VPBROADCASTDYrm: NumElts = 8; break;
1925  case X86::VPBROADCASTDZ128m: NumElts = 4; break;
1926  case X86::VPBROADCASTDZ256m: NumElts = 8; break;
1927  case X86::VPBROADCASTDZm: NumElts = 16; break;
1928  case X86::VPBROADCASTQrm: NumElts = 2; break;
1929  case X86::VPBROADCASTQYrm: NumElts = 4; break;
1930  case X86::VPBROADCASTQZ128m: NumElts = 2; break;
1931  case X86::VPBROADCASTQZ256m: NumElts = 4; break;
1932  case X86::VPBROADCASTQZm: NumElts = 8; break;
1933  case X86::VPBROADCASTWrm: NumElts = 8; break;
1934  case X86::VPBROADCASTWYrm: NumElts = 16; break;
1935  case X86::VPBROADCASTWZ128m: NumElts = 8; break;
1936  case X86::VPBROADCASTWZ256m: NumElts = 16; break;
1937  case X86::VPBROADCASTWZm: NumElts = 32; break;
1938  }
1939 
1940  std::string Comment;
1941  raw_string_ostream CS(Comment);
1942  const MachineOperand &DstOp = MI->getOperand(0);
1943  CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = ";
1944  CS << "[";
1945  for (int i = 0; i != NumElts; ++i) {
1946  if (i != 0)
1947  CS << ",";
1948  printConstant(C, CS);
1949  }
1950  CS << "]";
1951  OutStreamer->AddComment(CS.str(), !EnablePrintSchedInfo);
1952  }
1953  }
1954 
1955  MCInst TmpInst;
1956  MCInstLowering.Lower(MI, TmpInst);
1957 
1958  // Stackmap shadows cannot include branch targets, so we can count the bytes
1959  // in a call towards the shadow, but must ensure that the no thread returns
1960  // in to the stackmap shadow. The only way to achieve this is if the call
1961  // is at the end of the shadow.
1962  if (MI->isCall()) {
1963  // Count then size of the call towards the shadow
1964  SMShadowTracker.count(TmpInst, getSubtargetInfo(), CodeEmitter.get());
1965  // Then flush the shadow so that we fill with nops before the call, not
1966  // after it.
1967  SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
1968  // Then emit the call
1969  OutStreamer->EmitInstruction(TmpInst, getSubtargetInfo());
1970  return;
1971  }
1972 
1973  EmitAndCountInstruction(TmpInst);
1974 }
unsigned getTargetFlags() const
MO_SECREL - On a symbol operand this indicates that the immediate is the offset from beginning of sec...
Definition: X86BaseInfo.h:215
const NoneType None
Definition: None.h:24
unsigned GetCondBranchFromCond(CondCode CC)
uint64_t CallInst * C
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:415
void DecodeVPERMILPMask(MVT VT, ArrayRef< uint64_t > RawMask, SmallVectorImpl< int > &ShuffleMask)
Decode a VPERMILPD/VPERMILPS variable mask from a raw array of constants.
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:109
bool isImm() const
Definition: MCInst.h:59
mop_iterator operands_end()
Definition: MachineInstr.h:301
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
unsigned getNextScratchIdx(unsigned StartIdx=0) const
Get the next scratch register operand index.
Definition: StackMaps.cpp:70
static const char * getRegisterName(unsigned RegNo)
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:432
MachineBasicBlock * getMBB() const
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
Definition: AsmPrinter.h:93
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:305
virtual void EmitWinCFIEndProlog()
Definition: MCStreamer.cpp:706
MCTargetOptions MCOptions
Machine level options.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
PointerTy getPointer() const
static MachineOperand CreateMCSymbol(MCSymbol *Sym, unsigned char TargetFlags=0)
void setTargetFlags(unsigned F)
StringRef getPrivateGlobalPrefix() const
Definition: DataLayout.h:281
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:42
iterator begin() const
Definition: ArrayRef.h:137
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:136
MO_TLSLD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with ...
Definition: X86BaseInfo.h:123
MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate is some TLS offset from the ...
Definition: X86BaseInfo.h:209
MCContext & OutContext
This is the context for the output file that we are streaming.
Definition: AsmPrinter.h:88
static MachineModuleInfoMachO & getMachOMMI(AsmPrinter &AP)
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:137
bool EnablePrintSchedInfo
Enable print [latency:throughput] in output.
Definition: AsmPrinter.h:120
const MCSubtargetInfo & getSubtargetInfo() const
Return information about subtarget.
Definition: AsmPrinter.cpp:205
This provides a very simple, boring adaptor for a begin and end iterator into a range type...
unsigned getReg() const
getReg - Returns the register number.
virtual void EmitBytes(StringRef Data)
Emit the bytes in Data into the output.
Definition: MCStreamer.cpp:845
Address of indexed Jump Table for switch.
This class represents a function call, abstracting a target machine&#39;s calling convention.
const MachineFunction * MF
The current machine function.
Definition: AsmPrinter.h:96
bool isReg() const
Definition: MCInst.h:58
PointerIntPair< MCSymbol *, 1, bool > StubValueTy
static std::string getShuffleComment(const MachineInstr *MI, unsigned SrcOp1Idx, unsigned SrcOp2Idx, ArrayRef< int > Mask)
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:493
MachineBasicBlock reference.
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
MachineInstrBundleIterator< const MachineInstr > const_iterator
MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...
Definition: X86BaseInfo.h:97
MO_DTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry with...
Definition: X86BaseInfo.h:166
static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, const MCSubtargetInfo &STI)
Emit the optimal amount of multi-byte nops on X86.
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:306
print alias Alias Set Printer
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
unsigned getSlotSize() const
virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, bool PrintSchedInfo=false)
Emit the given Instruction into the current section.
Definition: MCStreamer.cpp:793
Mask of preserved registers.
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
MCContext & getContext() const
Definition: MCStreamer.h:227
void recordSled(MCSymbol *Sled, const MachineInstr &MI, SledKind Kind, uint8_t Version=0)
CLEANUPRET - Represents a return from a cleanup block funclet.
Definition: ISDOpcodes.h:657
MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates that the reference is actually...
Definition: X86BaseInfo.h:197
bool isMachineConstantPoolEntry() const
isMachineConstantPoolEntry - Return true if the MachineConstantPoolEntry is indeed a target specific ...
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:116
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:282
virtual void encodeInstruction(const MCInst &Inst, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
EncodeInstruction - Encode the given Inst to bytes on the output stream OS.
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:36
Name of external global symbol.
Reg
All possible values of the reg field in the ModR/M byte.
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:165
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:279
const char * getSymbolName() const
#define CASE_ALL_MOV_RM()
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:65
Context object for machine code objects.
Definition: MCContext.h:59
void recordFaultingOp(FaultKind FaultTy, const MCSymbol *HandlerLabel)
Definition: FaultMaps.cpp:31
virtual void AddComment(const Twine &T, bool EOL=true)
Add a textual comment.
Definition: MCStreamer.h:275
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:245
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:528
bool isPositionIndependent() const
Definition: AsmPrinter.cpp:183
MO_GOT - On a symbol operand this indicates that the immediate is the offset to the GOT entry for the...
Definition: X86BaseInfo.h:82
MO_GOTTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry wi...
Definition: X86BaseInfo.h:141
MO_ABS8 - On a symbol operand this indicates that the symbol is known to be an absolute symbol in ran...
Definition: X86BaseInfo.h:220
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:133
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
virtual void emitRawComment(const Twine &T, bool TabPrefix=true)
Print T and prefix it with the comment string (normally #) and optionally a tab.
Definition: MCStreamer.cpp:80
This class is a data container for one entry in a MachineConstantPool.
auto count(R &&Range, const E &Element) -> typename std::iterator_traits< decltype(std::begin(Range))>::difference_type
Wrapper function around std::count to count the number of times an element Element occurs in the give...
Definition: STLExtras.h:878
virtual void EmitBinaryData(StringRef Data)
Functionally identical to EmitBytes.
Definition: MCStreamer.cpp:846
const MCExpr * getExpr() const
Definition: MCInst.h:96
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:443
MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the reference is actually to the "...
Definition: X86BaseInfo.h:192
void recordStatepoint(const MachineInstr &MI)
Generate a stackmap record for a statepoint instruction.
Definition: StackMaps.cpp:395
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:159
bool isX86_64ExtendedReg(unsigned RegNo)
isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or higher) register? e.g.
Definition: X86BaseInfo.h:737
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
int64_t getImm() const
Definition: MCInst.h:76
Address of a global value.
Streaming machine code generation interface.
Definition: MCStreamer.h:168
MCSymbol * createTempSymbol(bool CanBeUnnamed=true)
Create and return a new assembler temporary symbol with a unique but unspecified name.
Definition: MCContext.cpp:215
MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a relocation of: SYMBOL_LABEL + [...
Definition: X86BaseInfo.h:70
PointerIntPair - This class implements a pair of a pointer and small integer.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void DecodeVPPERMMask(ArrayRef< uint64_t > RawMask, SmallVectorImpl< int > &ShuffleMask)
Decode a VPPERM mask from a raw array of constants such as from BUILD_VECTOR.
MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry w...
Definition: X86BaseInfo.h:182
MO_TLVP - On a symbol operand this indicates that the immediate is some TLS offset.
Definition: X86BaseInfo.h:203
virtual void EmitWinCFIPushReg(unsigned Register)
Definition: MCStreamer.cpp:632
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This is an important base class in LLVM.
Definition: Constant.h:42
const GlobalValue * getGlobal() const
MO_TLSLDM - On a symbol operand this indicates that the immediate is the offset of the GOT entry with...
Definition: X86BaseInfo.h:133
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:22
TargetMachine & TM
Target machine description.
Definition: AsmPrinter.h:80
This class is intended to be used as a driving class for all asm writers.
Definition: AsmPrinter.h:76
void getNameWithPrefix(SmallVectorImpl< char > &Name, const GlobalValue *GV) const
Definition: AsmPrinter.cpp:417
bool hasInternalLinkage() const
Definition: GlobalValue.h:414
Address of a basic block.
bool isExpr() const
Definition: MCInst.h:61
static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst, unsigned Opcode)
Simplify things like MOV32rm to MOV32o32a.
MO_NTPOFF - On a symbol operand this indicates that the immediate is the negative thread-pointer offs...
Definition: X86BaseInfo.h:174
MI-level patchpoint operands.
Definition: StackMaps.h:77
unsigned getNumOperands() const
Definition: MCInst.h:175
int getSEHRegNum(unsigned i) const
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
static const Constant * getConstantFromPool(const MachineInstr &MI, const MachineOperand &Op)
const MachineBasicBlock & front() const
virtual MCSymbol * GetCPISymbol(unsigned CPID) const
Return the symbol for the specified constant pool entry.
StubValueTy & getGVStubEntry(MCSymbol *Sym)
void DecodeVPERMIL2PMask(MVT VT, unsigned M2Z, ArrayRef< uint64_t > RawMask, SmallVectorImpl< int > &ShuffleMask)
Decode a VPERMIL2PD/VPERMIL2PS variable mask from a raw array of constants.
std::string & str()
Flushes the stream contents to the target string and returns the string&#39;s reference.
Definition: raw_ostream.h:482
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void recordPatchPoint(const MachineInstr &MI)
Generate a stackmap record for a patchpoint instruction.
Definition: StackMaps.cpp:374
MO_TLSGD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with ...
Definition: X86BaseInfo.h:113
const std::vector< MachineConstantPoolEntry > & getConstants() const
MO_TPOFF - On a symbol operand this indicates that the immediate is the thread-pointer offset for the...
Definition: X86BaseInfo.h:158
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
void setOpcode(unsigned Op)
Definition: MCInst.h:167
MCSymbol * GetBlockAddressSymbol(const BlockAddress *BA) const
Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block.
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
virtual void EmitWinCFISaveXMM(unsigned Register, unsigned Offset)
Definition: MCStreamer.cpp:683
static MCOperand LowerSymbolOperand(const MachineInstr *MI, const MachineOperand &MO, AsmPrinter &AP)
MCSymbol * getSymbol(const GlobalValue *GV) const
Definition: AsmPrinter.cpp:422
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:864
virtual void EmitCodeAlignment(unsigned ByteAlignment, unsigned MaxBytesToEmit=0)
Emit nops until the byte alignment ByteAlignment is reached.
Definition: MCStreamer.cpp:858
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:173
iterator end() const
Definition: ArrayRef.h:138
virtual void EmitWinCFIAllocStack(unsigned Size)
Definition: MCStreamer.cpp:658
int64_t getImm() const
MCSymbol reference (for debug/eh info)
Target - Wrapper for Target specific information.
void recordStackMap(const MachineInstr &MI)
Generate a stackmap record for a stackmap instruction.
Definition: StackMaps.cpp:365
CATCHRET - Represents a return from a catch block funclet.
Definition: ISDOpcodes.h:653
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:139
Representation of each machine instruction.
Definition: MachineInstr.h:59
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MO_GOTOFF - On a symbol operand this indicates that the immediate is the offset to the location of th...
Definition: X86BaseInfo.h:89
static unsigned getRetOpcode(const X86Subtarget &Subtarget)
unsigned getNumFrameInfos()
Definition: MCStreamer.h:233
MCSymbol * GetJTISymbol(unsigned JTID, bool isLinkerPrivate=false) const
Return the symbol for the specified jump table entry.
MO_INDNTPOFF - On a symbol operand this indicates that the immediate is the absolute address of the G...
Definition: X86BaseInfo.h:150
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:121
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:61
TargetOptions Options
Definition: TargetMachine.h:96
int64_t getOffset() const
Return the offset from the symbol in this operand.
const BlockAddress * getBlockAddress() const
AddrNumOperands - Total number of operands in a memory reference.
Definition: X86BaseInfo.h:42
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
MCSubtargetInfo - Generic base class for all target subtargets.
MI-level Statepoint operands.
Definition: StackMaps.h:155
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given patchpoint should emit.
Definition: StackMaps.h:105
void EmitInstruction(const MachineInstr *MI) override
Targets should implement this to emit instructions.
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
void print(raw_ostream &OS, bool SkipOpers=false, bool SkipDebugLoc=false, const TargetInstrInfo *TII=nullptr) const
Debugging supportPrint this MI to OS.
MachineModuleInfoMachO - This is a MachineModuleInfoImpl implementation for MachO targets...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents &#39;eh_return&#39; gcc dwarf builtin...
Definition: ISDOpcodes.h:102
MO_PLT - On a symbol operand this indicates that the immediate is offset to the PLT entry of symbol n...
Definition: X86BaseInfo.h:104
void DecodePSHUFBMask(ArrayRef< uint64_t > RawMask, SmallVectorImpl< int > &ShuffleMask)
Decode a PSHUFB mask from a raw array of constants such as from BUILD_VECTOR.
AddrSegmentReg - The operand # of the segment in the memory operand.
Definition: X86BaseInfo.h:39
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:466
MCSymbol * getMCSymbol() const
mop_iterator operands_begin()
Definition: MachineInstr.h:300
static const char * name
ArrayRef< MCDwarfFrameInfo > getDwarfFrameInfos() const
Definition: MCStreamer.h:234
MCSymbol * getPICBaseSymbol() const
getPICBaseSymbol - Return a function-local symbol to represent the PIC base.
static void printConstant(const Constant *COp, raw_ostream &CS)
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
virtual void EmitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
Definition: MCStreamer.cpp:308
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:57
MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the immediate should get the value of th...
Definition: X86BaseInfo.h:75
void getNameWithPrefix(raw_ostream &OS, const GlobalValue *GV, bool CannotUsePrivateLabel) const
Print the appropriate prefix and the specified global variable&#39;s name.
Definition: Mangler.cpp:109
static MachineBasicBlock::const_iterator PrevCrossBBInst(MachineBasicBlock::const_iterator MBBI)
virtual void EmitWinCFISaveReg(unsigned Register, unsigned Offset)
Definition: MCStreamer.cpp:671
virtual void EmitWinCFIPushFrame(bool Code)
Definition: MCStreamer.cpp:695
IRTranslator LLVM IR MI
const MachineOperand & getCallTarget() const
Returns the target of the underlying call.
Definition: StackMaps.h:110
void addOperand(const MCOperand &Op)
Definition: MCInst.h:177
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
Address of indexed Constant in Constant Pool.
static MCSymbol * GetSymbolFromOperand(const MachineOperand &MO, AsmPrinter &AP)
unsigned getOpcode() const
Definition: MCInst.h:168
virtual bool isVerboseAsm() const
Return true if this streamer supports verbose assembly and if it is enabled.
Definition: MCStreamer.h:252
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:284
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:35
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
union llvm::MachineConstantPoolEntry::@136 Val
The constant itself.
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:123
static unsigned EmitNop(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, const MCSubtargetInfo &STI)
Emit the largest nop instruction smaller than or equal to NumBytes bytes.
const X86Subtarget & getSubtarget() const
static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode)
Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with a short fixed-register form...
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx)
Definition: MCExpr.cpp:159
virtual void EmitCFIAdjustCfaOffset(int64_t Adjustment)
Definition: MCStreamer.cpp:394
static void SimplifyMOVSX(MCInst &Inst)
If a movsx instruction has a shorter encoding for the used register simplify the instruction to use i...
uint8_t getAsmPrinterFlags() const
Return the asm printer flags bitvector.
Definition: MachineInstr.h:143
MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the reference is actually to the "__imp...
Definition: X86BaseInfo.h:187
virtual void EmitWinCFISetFrame(unsigned Register, unsigned Offset)
Definition: MCStreamer.cpp:641
bool isImplicit() const