LLVM  9.0.0svn
X86MCTargetDesc.cpp
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1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides X86 specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86MCTargetDesc.h"
16 #include "X86BaseInfo.h"
17 #include "X86MCAsmInfo.h"
18 #include "llvm/ADT/APInt.h"
19 #include "llvm/ADT/Triple.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/MC/MCStreamer.h"
28 #include "llvm/Support/Host.h"
30 
31 #if _MSC_VER
32 #include <intrin.h>
33 #endif
34 
35 using namespace llvm;
36 
37 #define GET_REGINFO_MC_DESC
38 #include "X86GenRegisterInfo.inc"
39 
40 #define GET_INSTRINFO_MC_DESC
41 #define GET_INSTRINFO_MC_HELPERS
42 #include "X86GenInstrInfo.inc"
43 
44 #define GET_SUBTARGETINFO_MC_DESC
45 #include "X86GenSubtargetInfo.inc"
46 
47 std::string X86_MC::ParseX86Triple(const Triple &TT) {
48  std::string FS;
49  if (TT.getArch() == Triple::x86_64)
50  FS = "+64bit-mode,-32bit-mode,-16bit-mode";
51  else if (TT.getEnvironment() != Triple::CODE16)
52  FS = "-64bit-mode,+32bit-mode,-16bit-mode";
53  else
54  FS = "-64bit-mode,-32bit-mode,+16bit-mode";
55 
56  return FS;
57 }
58 
59 unsigned X86_MC::getDwarfRegFlavour(const Triple &TT, bool isEH) {
60  if (TT.getArch() == Triple::x86_64)
61  return DWARFFlavour::X86_64;
62 
63  if (TT.isOSDarwin())
65  if (TT.isOSCygMing())
66  // Unsupported by now, just quick fallback
69 }
70 
72  // FIXME: TableGen these.
73  for (unsigned Reg = X86::NoRegister + 1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
74  unsigned SEH = MRI->getEncodingValue(Reg);
75  MRI->mapLLVMRegToSEHReg(Reg, SEH);
76  }
77 
78  // Mapping from CodeView to MC register id.
79  static const struct {
81  MCPhysReg Reg;
82  } RegMap[] = {
84  {codeview::RegisterId::CL, X86::CL},
85  {codeview::RegisterId::DL, X86::DL},
87  {codeview::RegisterId::AH, X86::AH},
88  {codeview::RegisterId::CH, X86::CH},
89  {codeview::RegisterId::DH, X86::DH},
90  {codeview::RegisterId::BH, X86::BH},
91  {codeview::RegisterId::AX, X86::AX},
92  {codeview::RegisterId::CX, X86::CX},
93  {codeview::RegisterId::DX, X86::DX},
94  {codeview::RegisterId::BX, X86::BX},
95  {codeview::RegisterId::SP, X86::SP},
96  {codeview::RegisterId::BP, X86::BP},
98  {codeview::RegisterId::DI, X86::DI},
104  {codeview::RegisterId::EBP, X86::EBP},
107 
108  {codeview::RegisterId::EFLAGS, X86::EFLAGS},
109 
110  {codeview::RegisterId::ST0, X86::FP0},
111  {codeview::RegisterId::ST1, X86::FP1},
112  {codeview::RegisterId::ST2, X86::FP2},
113  {codeview::RegisterId::ST3, X86::FP3},
114  {codeview::RegisterId::ST4, X86::FP4},
115  {codeview::RegisterId::ST5, X86::FP5},
116  {codeview::RegisterId::ST6, X86::FP6},
117  {codeview::RegisterId::ST7, X86::FP7},
118 
119  {codeview::RegisterId::XMM0, X86::XMM0},
120  {codeview::RegisterId::XMM1, X86::XMM1},
121  {codeview::RegisterId::XMM2, X86::XMM2},
122  {codeview::RegisterId::XMM3, X86::XMM3},
123  {codeview::RegisterId::XMM4, X86::XMM4},
124  {codeview::RegisterId::XMM5, X86::XMM5},
125  {codeview::RegisterId::XMM6, X86::XMM6},
126  {codeview::RegisterId::XMM7, X86::XMM7},
127 
128  {codeview::RegisterId::XMM8, X86::XMM8},
129  {codeview::RegisterId::XMM9, X86::XMM9},
130  {codeview::RegisterId::XMM10, X86::XMM10},
131  {codeview::RegisterId::XMM11, X86::XMM11},
132  {codeview::RegisterId::XMM12, X86::XMM12},
133  {codeview::RegisterId::XMM13, X86::XMM13},
134  {codeview::RegisterId::XMM14, X86::XMM14},
135  {codeview::RegisterId::XMM15, X86::XMM15},
136 
137  {codeview::RegisterId::SIL, X86::SIL},
138  {codeview::RegisterId::DIL, X86::DIL},
139  {codeview::RegisterId::BPL, X86::BPL},
140  {codeview::RegisterId::SPL, X86::SPL},
141  {codeview::RegisterId::RAX, X86::RAX},
142  {codeview::RegisterId::RBX, X86::RBX},
143  {codeview::RegisterId::RCX, X86::RCX},
144  {codeview::RegisterId::RDX, X86::RDX},
145  {codeview::RegisterId::RSI, X86::RSI},
146  {codeview::RegisterId::RDI, X86::RDI},
147  {codeview::RegisterId::RBP, X86::RBP},
148  {codeview::RegisterId::RSP, X86::RSP},
149  {codeview::RegisterId::R8, X86::R8},
150  {codeview::RegisterId::R9, X86::R9},
151  {codeview::RegisterId::R10, X86::R10},
152  {codeview::RegisterId::R11, X86::R11},
153  {codeview::RegisterId::R12, X86::R12},
154  {codeview::RegisterId::R13, X86::R13},
155  {codeview::RegisterId::R14, X86::R14},
156  {codeview::RegisterId::R15, X86::R15},
157  {codeview::RegisterId::R8B, X86::R8B},
158  {codeview::RegisterId::R9B, X86::R9B},
159  {codeview::RegisterId::R10B, X86::R10B},
160  {codeview::RegisterId::R11B, X86::R11B},
161  {codeview::RegisterId::R12B, X86::R12B},
162  {codeview::RegisterId::R13B, X86::R13B},
163  {codeview::RegisterId::R14B, X86::R14B},
164  {codeview::RegisterId::R15B, X86::R15B},
165  {codeview::RegisterId::R8W, X86::R8W},
166  {codeview::RegisterId::R9W, X86::R9W},
167  {codeview::RegisterId::R10W, X86::R10W},
168  {codeview::RegisterId::R11W, X86::R11W},
169  {codeview::RegisterId::R12W, X86::R12W},
170  {codeview::RegisterId::R13W, X86::R13W},
171  {codeview::RegisterId::R14W, X86::R14W},
172  {codeview::RegisterId::R15W, X86::R15W},
173  {codeview::RegisterId::R8D, X86::R8D},
174  {codeview::RegisterId::R9D, X86::R9D},
175  {codeview::RegisterId::R10D, X86::R10D},
176  {codeview::RegisterId::R11D, X86::R11D},
177  {codeview::RegisterId::R12D, X86::R12D},
178  {codeview::RegisterId::R13D, X86::R13D},
179  {codeview::RegisterId::R14D, X86::R14D},
180  {codeview::RegisterId::R15D, X86::R15D},
181  {codeview::RegisterId::AMD64_YMM0, X86::YMM0},
182  {codeview::RegisterId::AMD64_YMM1, X86::YMM1},
183  {codeview::RegisterId::AMD64_YMM2, X86::YMM2},
184  {codeview::RegisterId::AMD64_YMM3, X86::YMM3},
185  {codeview::RegisterId::AMD64_YMM4, X86::YMM4},
186  {codeview::RegisterId::AMD64_YMM5, X86::YMM5},
187  {codeview::RegisterId::AMD64_YMM6, X86::YMM6},
188  {codeview::RegisterId::AMD64_YMM7, X86::YMM7},
189  {codeview::RegisterId::AMD64_YMM8, X86::YMM8},
190  {codeview::RegisterId::AMD64_YMM9, X86::YMM9},
191  {codeview::RegisterId::AMD64_YMM10, X86::YMM10},
192  {codeview::RegisterId::AMD64_YMM11, X86::YMM11},
193  {codeview::RegisterId::AMD64_YMM12, X86::YMM12},
194  {codeview::RegisterId::AMD64_YMM13, X86::YMM13},
195  {codeview::RegisterId::AMD64_YMM14, X86::YMM14},
196  {codeview::RegisterId::AMD64_YMM15, X86::YMM15},
197  {codeview::RegisterId::AMD64_YMM16, X86::YMM16},
198  {codeview::RegisterId::AMD64_YMM17, X86::YMM17},
199  {codeview::RegisterId::AMD64_YMM18, X86::YMM18},
200  {codeview::RegisterId::AMD64_YMM19, X86::YMM19},
201  {codeview::RegisterId::AMD64_YMM20, X86::YMM20},
202  {codeview::RegisterId::AMD64_YMM21, X86::YMM21},
203  {codeview::RegisterId::AMD64_YMM22, X86::YMM22},
204  {codeview::RegisterId::AMD64_YMM23, X86::YMM23},
205  {codeview::RegisterId::AMD64_YMM24, X86::YMM24},
206  {codeview::RegisterId::AMD64_YMM25, X86::YMM25},
207  {codeview::RegisterId::AMD64_YMM26, X86::YMM26},
208  {codeview::RegisterId::AMD64_YMM27, X86::YMM27},
209  {codeview::RegisterId::AMD64_YMM28, X86::YMM28},
210  {codeview::RegisterId::AMD64_YMM29, X86::YMM29},
211  {codeview::RegisterId::AMD64_YMM30, X86::YMM30},
212  {codeview::RegisterId::AMD64_YMM31, X86::YMM31},
213  {codeview::RegisterId::AMD64_ZMM0, X86::ZMM0},
214  {codeview::RegisterId::AMD64_ZMM1, X86::ZMM1},
215  {codeview::RegisterId::AMD64_ZMM2, X86::ZMM2},
216  {codeview::RegisterId::AMD64_ZMM3, X86::ZMM3},
217  {codeview::RegisterId::AMD64_ZMM4, X86::ZMM4},
218  {codeview::RegisterId::AMD64_ZMM5, X86::ZMM5},
219  {codeview::RegisterId::AMD64_ZMM6, X86::ZMM6},
220  {codeview::RegisterId::AMD64_ZMM7, X86::ZMM7},
221  {codeview::RegisterId::AMD64_ZMM8, X86::ZMM8},
222  {codeview::RegisterId::AMD64_ZMM9, X86::ZMM9},
223  {codeview::RegisterId::AMD64_ZMM10, X86::ZMM10},
224  {codeview::RegisterId::AMD64_ZMM11, X86::ZMM11},
225  {codeview::RegisterId::AMD64_ZMM12, X86::ZMM12},
226  {codeview::RegisterId::AMD64_ZMM13, X86::ZMM13},
227  {codeview::RegisterId::AMD64_ZMM14, X86::ZMM14},
228  {codeview::RegisterId::AMD64_ZMM15, X86::ZMM15},
229  {codeview::RegisterId::AMD64_ZMM16, X86::ZMM16},
230  {codeview::RegisterId::AMD64_ZMM17, X86::ZMM17},
231  {codeview::RegisterId::AMD64_ZMM18, X86::ZMM18},
232  {codeview::RegisterId::AMD64_ZMM19, X86::ZMM19},
233  {codeview::RegisterId::AMD64_ZMM20, X86::ZMM20},
234  {codeview::RegisterId::AMD64_ZMM21, X86::ZMM21},
235  {codeview::RegisterId::AMD64_ZMM22, X86::ZMM22},
236  {codeview::RegisterId::AMD64_ZMM23, X86::ZMM23},
237  {codeview::RegisterId::AMD64_ZMM24, X86::ZMM24},
238  {codeview::RegisterId::AMD64_ZMM25, X86::ZMM25},
239  {codeview::RegisterId::AMD64_ZMM26, X86::ZMM26},
240  {codeview::RegisterId::AMD64_ZMM27, X86::ZMM27},
241  {codeview::RegisterId::AMD64_ZMM28, X86::ZMM28},
242  {codeview::RegisterId::AMD64_ZMM29, X86::ZMM29},
243  {codeview::RegisterId::AMD64_ZMM30, X86::ZMM30},
244  {codeview::RegisterId::AMD64_ZMM31, X86::ZMM31},
245  {codeview::RegisterId::AMD64_K0, X86::K0},
246  {codeview::RegisterId::AMD64_K1, X86::K1},
247  {codeview::RegisterId::AMD64_K2, X86::K2},
248  {codeview::RegisterId::AMD64_K3, X86::K3},
249  {codeview::RegisterId::AMD64_K4, X86::K4},
250  {codeview::RegisterId::AMD64_K5, X86::K5},
251  {codeview::RegisterId::AMD64_K6, X86::K6},
252  {codeview::RegisterId::AMD64_K7, X86::K7},
253  {codeview::RegisterId::AMD64_XMM16, X86::XMM16},
254  {codeview::RegisterId::AMD64_XMM17, X86::XMM17},
255  {codeview::RegisterId::AMD64_XMM18, X86::XMM18},
256  {codeview::RegisterId::AMD64_XMM19, X86::XMM19},
257  {codeview::RegisterId::AMD64_XMM20, X86::XMM20},
258  {codeview::RegisterId::AMD64_XMM21, X86::XMM21},
259  {codeview::RegisterId::AMD64_XMM22, X86::XMM22},
260  {codeview::RegisterId::AMD64_XMM23, X86::XMM23},
261  {codeview::RegisterId::AMD64_XMM24, X86::XMM24},
262  {codeview::RegisterId::AMD64_XMM25, X86::XMM25},
263  {codeview::RegisterId::AMD64_XMM26, X86::XMM26},
264  {codeview::RegisterId::AMD64_XMM27, X86::XMM27},
265  {codeview::RegisterId::AMD64_XMM28, X86::XMM28},
266  {codeview::RegisterId::AMD64_XMM29, X86::XMM29},
267  {codeview::RegisterId::AMD64_XMM30, X86::XMM30},
268  {codeview::RegisterId::AMD64_XMM31, X86::XMM31},
269 
270  };
271  for (unsigned I = 0; I < array_lengthof(RegMap); ++I)
272  MRI->mapLLVMRegToCVReg(RegMap[I].Reg, static_cast<int>(RegMap[I].CVReg));
273 }
274 
276  StringRef CPU, StringRef FS) {
277  std::string ArchFS = X86_MC::ParseX86Triple(TT);
278  if (!FS.empty()) {
279  if (!ArchFS.empty())
280  ArchFS = (Twine(ArchFS) + "," + FS).str();
281  else
282  ArchFS = FS;
283  }
284 
285  std::string CPUName = CPU;
286  if (CPUName.empty())
287  CPUName = "generic";
288 
289  return createX86MCSubtargetInfoImpl(TT, CPUName, ArchFS);
290 }
291 
293  MCInstrInfo *X = new MCInstrInfo();
294  InitX86MCInstrInfo(X);
295  return X;
296 }
297 
299  unsigned RA = (TT.getArch() == Triple::x86_64)
300  ? X86::RIP // Should have dwarf #16.
301  : X86::EIP; // Should have dwarf #8.
302 
304  InitX86MCRegisterInfo(X, RA, X86_MC::getDwarfRegFlavour(TT, false),
305  X86_MC::getDwarfRegFlavour(TT, true), RA);
307  return X;
308 }
309 
311  const Triple &TheTriple) {
312  bool is64Bit = TheTriple.getArch() == Triple::x86_64;
313 
314  MCAsmInfo *MAI;
315  if (TheTriple.isOSBinFormatMachO()) {
316  if (is64Bit)
317  MAI = new X86_64MCAsmInfoDarwin(TheTriple);
318  else
319  MAI = new X86MCAsmInfoDarwin(TheTriple);
320  } else if (TheTriple.isOSBinFormatELF()) {
321  // Force the use of an ELF container.
322  MAI = new X86ELFMCAsmInfo(TheTriple);
323  } else if (TheTriple.isWindowsMSVCEnvironment() ||
324  TheTriple.isWindowsCoreCLREnvironment()) {
325  MAI = new X86MCAsmInfoMicrosoft(TheTriple);
326  } else if (TheTriple.isOSCygMing() ||
327  TheTriple.isWindowsItaniumEnvironment()) {
328  MAI = new X86MCAsmInfoGNUCOFF(TheTriple);
329  } else {
330  // The default is ELF.
331  MAI = new X86ELFMCAsmInfo(TheTriple);
332  }
333 
334  // Initialize initial frame state.
335  // Calculate amount of bytes used for return address storing
336  int stackGrowth = is64Bit ? -8 : -4;
337 
338  // Initial state of the frame pointer is esp+stackGrowth.
339  unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP;
341  nullptr, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth);
342  MAI->addInitialFrameState(Inst);
343 
344  // Add return address to move list
345  unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP;
347  nullptr, MRI.getDwarfRegNum(InstPtr, true), stackGrowth);
348  MAI->addInitialFrameState(Inst2);
349 
350  return MAI;
351 }
352 
354  unsigned SyntaxVariant,
355  const MCAsmInfo &MAI,
356  const MCInstrInfo &MII,
357  const MCRegisterInfo &MRI) {
358  if (SyntaxVariant == 0)
359  return new X86ATTInstPrinter(MAI, MII, MRI);
360  if (SyntaxVariant == 1)
361  return new X86IntelInstPrinter(MAI, MII, MRI);
362  return nullptr;
363 }
364 
366  MCContext &Ctx) {
367  // Default to the stock relocation info.
368  return llvm::createMCRelocationInfo(TheTriple, Ctx);
369 }
370 
371 namespace llvm {
372 namespace X86_MC {
373 
375  X86MCInstrAnalysis(const X86MCInstrAnalysis &) = delete;
376  X86MCInstrAnalysis &operator=(const X86MCInstrAnalysis &) = delete;
377  virtual ~X86MCInstrAnalysis() = default;
378 
379 public:
381 
382 #define GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
383 #include "X86GenSubtargetInfo.inc"
384 
385  bool clearsSuperRegisters(const MCRegisterInfo &MRI, const MCInst &Inst,
386  APInt &Mask) const override;
387  std::vector<std::pair<uint64_t, uint64_t>>
388  findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,
389  uint64_t GotSectionVA,
390  const Triple &TargetTriple) const override;
391 };
392 
393 #define GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
394 #include "X86GenSubtargetInfo.inc"
395 
397  const MCInst &Inst,
398  APInt &Mask) const {
399  const MCInstrDesc &Desc = Info->get(Inst.getOpcode());
400  unsigned NumDefs = Desc.getNumDefs();
401  unsigned NumImplicitDefs = Desc.getNumImplicitDefs();
402  assert(Mask.getBitWidth() == NumDefs + NumImplicitDefs &&
403  "Unexpected number of bits in the mask!");
404 
405  bool HasVEX = (Desc.TSFlags & X86II::EncodingMask) == X86II::VEX;
406  bool HasEVEX = (Desc.TSFlags & X86II::EncodingMask) == X86II::EVEX;
407  bool HasXOP = (Desc.TSFlags & X86II::EncodingMask) == X86II::XOP;
408 
409  const MCRegisterClass &GR32RC = MRI.getRegClass(X86::GR32RegClassID);
410  const MCRegisterClass &VR128XRC = MRI.getRegClass(X86::VR128XRegClassID);
411  const MCRegisterClass &VR256XRC = MRI.getRegClass(X86::VR256XRegClassID);
412 
413  auto ClearsSuperReg = [=](unsigned RegID) {
414  // On X86-64, a general purpose integer register is viewed as a 64-bit
415  // register internal to the processor.
416  // An update to the lower 32 bits of a 64 bit integer register is
417  // architecturally defined to zero extend the upper 32 bits.
418  if (GR32RC.contains(RegID))
419  return true;
420 
421  // Early exit if this instruction has no vex/evex/xop prefix.
422  if (!HasEVEX && !HasVEX && !HasXOP)
423  return false;
424 
425  // All VEX and EVEX encoded instructions are defined to zero the high bits
426  // of the destination register up to VLMAX (i.e. the maximum vector register
427  // width pertaining to the instruction).
428  // We assume the same behavior for XOP instructions too.
429  return VR128XRC.contains(RegID) || VR256XRC.contains(RegID);
430  };
431 
432  Mask.clearAllBits();
433  for (unsigned I = 0, E = NumDefs; I < E; ++I) {
434  const MCOperand &Op = Inst.getOperand(I);
435  if (ClearsSuperReg(Op.getReg()))
436  Mask.setBit(I);
437  }
438 
439  for (unsigned I = 0, E = NumImplicitDefs; I < E; ++I) {
440  const MCPhysReg Reg = Desc.getImplicitDefs()[I];
441  if (ClearsSuperReg(Reg))
442  Mask.setBit(NumDefs + I);
443  }
444 
445  return Mask.getBoolValue();
446 }
447 
448 static std::vector<std::pair<uint64_t, uint64_t>>
449 findX86PltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,
450  uint64_t GotPltSectionVA) {
451  // Do a lightweight parsing of PLT entries.
452  std::vector<std::pair<uint64_t, uint64_t>> Result;
453  for (uint64_t Byte = 0, End = PltContents.size(); Byte + 6 < End; ) {
454  // Recognize a jmp.
455  if (PltContents[Byte] == 0xff && PltContents[Byte + 1] == 0xa3) {
456  // The jmp instruction at the beginning of each PLT entry jumps to the
457  // address of the base of the .got.plt section plus the immediate.
458  uint32_t Imm = support::endian::read32le(PltContents.data() + Byte + 2);
459  Result.push_back(
460  std::make_pair(PltSectionVA + Byte, GotPltSectionVA + Imm));
461  Byte += 6;
462  } else if (PltContents[Byte] == 0xff && PltContents[Byte + 1] == 0x25) {
463  // The jmp instruction at the beginning of each PLT entry jumps to the
464  // immediate.
465  uint32_t Imm = support::endian::read32le(PltContents.data() + Byte + 2);
466  Result.push_back(std::make_pair(PltSectionVA + Byte, Imm));
467  Byte += 6;
468  } else
469  Byte++;
470  }
471  return Result;
472 }
473 
474 static std::vector<std::pair<uint64_t, uint64_t>>
475 findX86_64PltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents) {
476  // Do a lightweight parsing of PLT entries.
477  std::vector<std::pair<uint64_t, uint64_t>> Result;
478  for (uint64_t Byte = 0, End = PltContents.size(); Byte + 6 < End; ) {
479  // Recognize a jmp.
480  if (PltContents[Byte] == 0xff && PltContents[Byte + 1] == 0x25) {
481  // The jmp instruction at the beginning of each PLT entry jumps to the
482  // address of the next instruction plus the immediate.
483  uint32_t Imm = support::endian::read32le(PltContents.data() + Byte + 2);
484  Result.push_back(
485  std::make_pair(PltSectionVA + Byte, PltSectionVA + Byte + 6 + Imm));
486  Byte += 6;
487  } else
488  Byte++;
489  }
490  return Result;
491 }
492 
493 std::vector<std::pair<uint64_t, uint64_t>> X86MCInstrAnalysis::findPltEntries(
494  uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,
495  uint64_t GotPltSectionVA, const Triple &TargetTriple) const {
496  switch (TargetTriple.getArch()) {
497  case Triple::x86:
498  return findX86PltEntries(PltSectionVA, PltContents, GotPltSectionVA);
499  case Triple::x86_64:
500  return findX86_64PltEntries(PltSectionVA, PltContents);
501  default:
502  return {};
503  }
504 }
505 
506 } // end of namespace X86_MC
507 
508 } // end of namespace llvm
509 
511  return new X86_MC::X86MCInstrAnalysis(Info);
512 }
513 
514 // Force static initialization.
515 extern "C" void LLVMInitializeX86TargetMC() {
516  for (Target *T : {&getTheX86_32Target(), &getTheX86_64Target()}) {
517  // Register the MC asm info.
519 
520  // Register the MC instruction info.
522 
523  // Register the MC register info.
525 
526  // Register the MC subtarget info.
529 
530  // Register the MC instruction analyzer.
532 
533  // Register the code emitter.
535 
536  // Register the obj target streamer.
539 
540  // Register the asm target streamer.
542 
544 
545  // Register the MCInstPrinter.
547 
548  // Register the MC relocation info.
550  }
551 
552  // Register the asm backend.
557 }
558 
559 unsigned llvm::getX86SubSuperRegisterOrZero(unsigned Reg, unsigned Size,
560  bool High) {
561  switch (Size) {
562  default: return 0;
563  case 8:
564  if (High) {
565  switch (Reg) {
566  default: return getX86SubSuperRegisterOrZero(Reg, 64);
567  case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
568  return X86::SI;
569  case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
570  return X86::DI;
571  case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
572  return X86::BP;
573  case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
574  return X86::SP;
575  case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
576  return X86::AH;
577  case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
578  return X86::DH;
579  case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
580  return X86::CH;
581  case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
582  return X86::BH;
583  }
584  } else {
585  switch (Reg) {
586  default: return 0;
587  case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
588  return X86::AL;
589  case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
590  return X86::DL;
591  case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
592  return X86::CL;
593  case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
594  return X86::BL;
595  case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
596  return X86::SIL;
597  case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
598  return X86::DIL;
599  case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
600  return X86::BPL;
601  case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
602  return X86::SPL;
603  case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
604  return X86::R8B;
605  case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
606  return X86::R9B;
607  case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
608  return X86::R10B;
609  case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
610  return X86::R11B;
611  case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
612  return X86::R12B;
613  case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
614  return X86::R13B;
615  case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
616  return X86::R14B;
617  case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
618  return X86::R15B;
619  }
620  }
621  case 16:
622  switch (Reg) {
623  default: return 0;
624  case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
625  return X86::AX;
626  case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
627  return X86::DX;
628  case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
629  return X86::CX;
630  case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
631  return X86::BX;
632  case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
633  return X86::SI;
634  case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
635  return X86::DI;
636  case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
637  return X86::BP;
638  case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
639  return X86::SP;
640  case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
641  return X86::R8W;
642  case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
643  return X86::R9W;
644  case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
645  return X86::R10W;
646  case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
647  return X86::R11W;
648  case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
649  return X86::R12W;
650  case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
651  return X86::R13W;
652  case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
653  return X86::R14W;
654  case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
655  return X86::R15W;
656  }
657  case 32:
658  switch (Reg) {
659  default: return 0;
660  case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
661  return X86::EAX;
662  case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
663  return X86::EDX;
664  case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
665  return X86::ECX;
666  case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
667  return X86::EBX;
668  case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
669  return X86::ESI;
670  case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
671  return X86::EDI;
672  case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
673  return X86::EBP;
674  case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
675  return X86::ESP;
676  case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
677  return X86::R8D;
678  case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
679  return X86::R9D;
680  case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
681  return X86::R10D;
682  case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
683  return X86::R11D;
684  case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
685  return X86::R12D;
686  case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
687  return X86::R13D;
688  case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
689  return X86::R14D;
690  case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
691  return X86::R15D;
692  }
693  case 64:
694  switch (Reg) {
695  default: return 0;
696  case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
697  return X86::RAX;
698  case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
699  return X86::RDX;
700  case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
701  return X86::RCX;
702  case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
703  return X86::RBX;
704  case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
705  return X86::RSI;
706  case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
707  return X86::RDI;
708  case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
709  return X86::RBP;
710  case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
711  return X86::RSP;
712  case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
713  return X86::R8;
714  case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
715  return X86::R9;
716  case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
717  return X86::R10;
718  case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
719  return X86::R11;
720  case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
721  return X86::R12;
722  case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
723  return X86::R13;
724  case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
725  return X86::R14;
726  case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
727  return X86::R15;
728  }
729  }
730 }
731 
732 unsigned llvm::getX86SubSuperRegister(unsigned Reg, unsigned Size, bool High) {
733  unsigned Res = getX86SubSuperRegisterOrZero(Reg, Size, High);
734  assert(Res != 0 && "Unexpected register or VT");
735  return Res;
736 }
737 
738 
void clearAllBits()
Set every bit to 0.
Definition: APInt.h:1451
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:475
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
Definition: MCInstrDesc.h:548
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:608
static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)
RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target...
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
Definition: MCDwarf.h:489
MCTargetStreamer * createX86ObjectTargetStreamer(MCStreamer &OS, const MCSubtargetInfo &STI)
Implements X86-only directives for object files.
unsigned Reg
bool clearsSuperRegisters(const MCRegisterInfo &MRI, const MCInst &Inst, APInt &Mask) const override
Returns true if at least one of the register writes performed by.
std::vector< std::pair< uint64_t, uint64_t > > findPltEntries(uint64_t PltSectionVA, ArrayRef< uint8_t > PltContents, uint64_t GotSectionVA, const Triple &TargetTriple) const override
Returns (PLT virtual address, GOT virtual address) pairs for PLT entries.
static MCRegisterInfo * createX86MCRegisterInfo(const Triple &TT)
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.
unsigned getDwarfRegFlavour(const Triple &TT, bool isEH)
uint64_t High
static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1508
std::string ParseX86Triple(const Triple &TT)
X86MCInstrAnalysis(const MCInstrInfo *MCII)
SI optimize exec mask operations pre RA
MCAsmBackend * createX86_32AsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
void setBit(unsigned BitPosition)
Set a given bit to 1.
Definition: APInt.h:1402
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:80
bool contains(unsigned Reg) const
contains - Return true if the specified register is included in this register class.
MCCodeEmitter * createX86MCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
int getDwarfRegNum(unsigned RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
MCAsmBackend * createX86_64AsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
static void RegisterCOFFStreamer(Target &T, Target::COFFStreamerCtorTy Fn)
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:126
This file implements a class to represent arbitrary precision integral constant values and operations...
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:64
Context object for machine code objects.
Definition: MCContext.h:62
bool getBoolValue() const
Convert APInt to a boolean value.
Definition: APInt.h:477
static MCRelocationInfo * createX86MCRelocationInfo(const Triple &TheTriple, MCContext &Ctx)
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Definition: Triple.h:290
void addInitialFrameState(const MCCFIInstruction &Inst)
Definition: MCAsmInfo.h:600
void LLVMInitializeX86TargetMC()
bool isWindowsItaniumEnvironment() const
Definition: Triple.h:547
MCRegisterClass - Base class of TargetRegisterClass.
bool isWindowsCoreCLREnvironment() const
Definition: Triple.h:543
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
MCRelocationInfo * createMCRelocationInfo(const Triple &TT, MCContext &Ctx)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:55
static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
Definition: MCInstrDesc.h:545
unsigned const MachineRegisterInfo * MRI
static MCCFIInstruction createDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it...
Definition: MCDwarf.h:462
XOP - Opcode prefix used by XOP instructions.
Definition: X86BaseInfo.h:525
const MCInstrInfo * Info
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
static bool is64Bit(const char *name)
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:23
MCStreamer * createX86WinCOFFStreamer(MCContext &C, std::unique_ptr< MCAsmBackend > &&AB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&CE, bool RelaxAll, bool IncrementalLinkerCompatible)
Construct an X86 Windows COFF machine code streamer which will generate PE/COFF format object files...
MCTargetStreamer * createX86AsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, bool isVerboseAsm)
Implements X86-only directives for assembly emission.
Create MCExprs from relocations found in an object file.
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:618
static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target...
static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)
static std::vector< std::pair< uint64_t, uint64_t > > findX86_64PltEntries(uint64_t PltSectionVA, ArrayRef< uint8_t > PltContents)
const T * data() const
Definition: ArrayRef.h:145
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
MCSubtargetInfo * createX86MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Create a X86 MCSubtargetInfo instance.
unsigned getX86SubSuperRegisterOrZero(unsigned, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
void initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI)
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:179
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1043
static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.
EnvironmentType getEnvironment() const
getEnvironment - Get the parsed environment type of this triple.
Definition: Triple.h:308
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:225
unsigned getX86SubSuperRegister(unsigned, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.
Target - Wrapper for Target specific information.
Class for arbitrary precision integers.
Definition: APInt.h:69
bool isOSCygMing() const
Tests for either Cygwin or MinGW OS.
Definition: Triple.h:560
static MCAsmInfo * createX86MCAsmInfo(const MCRegisterInfo &MRI, const Triple &TheTriple)
static MCInstrInfo * createX86MCInstrInfo()
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:39
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
void mapLLVMRegToCVReg(unsigned LLVMReg, int CVReg)
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:44
static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)
RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target. ...
#define I(x, y, z)
Definition: MD5.cpp:58
uint32_t read32le(const void *P)
Definition: Endian.h:383
static std::vector< std::pair< uint64_t, uint64_t > > findX86PltEntries(uint64_t PltSectionVA, ArrayRef< uint8_t > PltContents, uint64_t GotPltSectionVA)
Generic base class for all target subtargets.
Target & getTheX86_32Target()
uint32_t Size
Definition: Profile.cpp:46
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
RegisterMCAsmInfoFn - Helper template for registering a target assembly info implementation.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
static void RegisterMCRelocationInfo(Target &T, Target::MCRelocationInfoCtorTy Fn)
RegisterMCRelocationInfo - Register an MCRelocationInfo implementation for the given target...
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
static MCInstrAnalysis * createX86MCInstrAnalysis(const MCInstrInfo *Info)
unsigned getOpcode() const
Definition: MCInst.h:171
bool isWindowsMSVCEnvironment() const
Checks if the environment could be MSVC.
Definition: Triple.h:538
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:34
static MCInstPrinter * createX86MCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
Target & getTheX86_64Target()
void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg)
mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register number mapping.
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.