LLVM  7.0.0svn
X86MCTargetDesc.cpp
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1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides X86 specific target descriptions.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86MCTargetDesc.h"
17 #include "X86BaseInfo.h"
18 #include "X86MCAsmInfo.h"
19 #include "llvm/ADT/APInt.h"
20 #include "llvm/ADT/Triple.h"
23 #include "llvm/MC/MCInstrInfo.h"
24 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/MC/MCStreamer.h"
29 #include "llvm/Support/Host.h"
31 
32 #if _MSC_VER
33 #include <intrin.h>
34 #endif
35 
36 using namespace llvm;
37 
38 #define GET_REGINFO_MC_DESC
39 #include "X86GenRegisterInfo.inc"
40 
41 #define GET_INSTRINFO_MC_DESC
42 #include "X86GenInstrInfo.inc"
43 
44 #define GET_SUBTARGETINFO_MC_DESC
45 #include "X86GenSubtargetInfo.inc"
46 
47 std::string X86_MC::ParseX86Triple(const Triple &TT) {
48  std::string FS;
49  if (TT.getArch() == Triple::x86_64)
50  FS = "+64bit-mode,-32bit-mode,-16bit-mode";
51  else if (TT.getEnvironment() != Triple::CODE16)
52  FS = "-64bit-mode,+32bit-mode,-16bit-mode";
53  else
54  FS = "-64bit-mode,-32bit-mode,+16bit-mode";
55 
56  return FS;
57 }
58 
59 unsigned X86_MC::getDwarfRegFlavour(const Triple &TT, bool isEH) {
60  if (TT.getArch() == Triple::x86_64)
61  return DWARFFlavour::X86_64;
62 
63  if (TT.isOSDarwin())
65  if (TT.isOSCygMing())
66  // Unsupported by now, just quick fallback
69 }
70 
72  // FIXME: TableGen these.
73  for (unsigned Reg = X86::NoRegister + 1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
74  unsigned SEH = MRI->getEncodingValue(Reg);
75  MRI->mapLLVMRegToSEHReg(Reg, SEH);
76  }
77 
78  // Mapping from CodeView to MC register id.
79  static const struct {
81  MCPhysReg Reg;
82  } RegMap[] = {
83  { codeview::RegisterId::CVRegAL, X86::AL},
84  { codeview::RegisterId::CVRegCL, X86::CL},
85  { codeview::RegisterId::CVRegDL, X86::DL},
86  { codeview::RegisterId::CVRegBL, X86::BL},
87  { codeview::RegisterId::CVRegAH, X86::AH},
88  { codeview::RegisterId::CVRegCH, X86::CH},
89  { codeview::RegisterId::CVRegDH, X86::DH},
90  { codeview::RegisterId::CVRegBH, X86::BH},
91  { codeview::RegisterId::CVRegAX, X86::AX},
92  { codeview::RegisterId::CVRegCX, X86::CX},
93  { codeview::RegisterId::CVRegDX, X86::DX},
94  { codeview::RegisterId::CVRegBX, X86::BX},
95  { codeview::RegisterId::CVRegSP, X86::SP},
96  { codeview::RegisterId::CVRegBP, X86::BP},
97  { codeview::RegisterId::CVRegSI, X86::SI},
98  { codeview::RegisterId::CVRegDI, X86::DI},
99  { codeview::RegisterId::CVRegEAX, X86::EAX},
100  { codeview::RegisterId::CVRegECX, X86::ECX},
101  { codeview::RegisterId::CVRegEDX, X86::EDX},
102  { codeview::RegisterId::CVRegEBX, X86::EBX},
103  { codeview::RegisterId::CVRegESP, X86::ESP},
104  { codeview::RegisterId::CVRegEBP, X86::EBP},
105  { codeview::RegisterId::CVRegESI, X86::ESI},
106  { codeview::RegisterId::CVRegEDI, X86::EDI},
107 
108  { codeview::RegisterId::CVRegEFLAGS, X86::EFLAGS},
109 
110  { codeview::RegisterId::CVRegST0, X86::FP0},
111  { codeview::RegisterId::CVRegST1, X86::FP1},
112  { codeview::RegisterId::CVRegST2, X86::FP2},
113  { codeview::RegisterId::CVRegST3, X86::FP3},
114  { codeview::RegisterId::CVRegST4, X86::FP4},
115  { codeview::RegisterId::CVRegST5, X86::FP5},
116  { codeview::RegisterId::CVRegST6, X86::FP6},
117  { codeview::RegisterId::CVRegST7, X86::FP7},
118 
119  { codeview::RegisterId::CVRegXMM0, X86::XMM0},
120  { codeview::RegisterId::CVRegXMM1, X86::XMM1},
121  { codeview::RegisterId::CVRegXMM2, X86::XMM2},
122  { codeview::RegisterId::CVRegXMM3, X86::XMM3},
123  { codeview::RegisterId::CVRegXMM4, X86::XMM4},
124  { codeview::RegisterId::CVRegXMM5, X86::XMM5},
125  { codeview::RegisterId::CVRegXMM6, X86::XMM6},
126  { codeview::RegisterId::CVRegXMM7, X86::XMM7},
127 
128  { codeview::RegisterId::CVRegXMM8, X86::XMM8},
129  { codeview::RegisterId::CVRegXMM9, X86::XMM9},
130  { codeview::RegisterId::CVRegXMM10, X86::XMM10},
131  { codeview::RegisterId::CVRegXMM11, X86::XMM11},
132  { codeview::RegisterId::CVRegXMM12, X86::XMM12},
133  { codeview::RegisterId::CVRegXMM13, X86::XMM13},
134  { codeview::RegisterId::CVRegXMM14, X86::XMM14},
135  { codeview::RegisterId::CVRegXMM15, X86::XMM15},
136 
137  { codeview::RegisterId::CVRegSIL, X86::SIL},
138  { codeview::RegisterId::CVRegDIL, X86::DIL},
139  { codeview::RegisterId::CVRegBPL, X86::BPL},
140  { codeview::RegisterId::CVRegSPL, X86::SPL},
141  { codeview::RegisterId::CVRegRAX, X86::RAX},
142  { codeview::RegisterId::CVRegRBX, X86::RBX},
143  { codeview::RegisterId::CVRegRCX, X86::RCX},
144  { codeview::RegisterId::CVRegRDX, X86::RDX},
145  { codeview::RegisterId::CVRegRSI, X86::RSI},
146  { codeview::RegisterId::CVRegRDI, X86::RDI},
147  { codeview::RegisterId::CVRegRBP, X86::RBP},
148  { codeview::RegisterId::CVRegRSP, X86::RSP},
149  { codeview::RegisterId::CVRegR8, X86::R8},
150  { codeview::RegisterId::CVRegR9, X86::R9},
151  { codeview::RegisterId::CVRegR10, X86::R10},
152  { codeview::RegisterId::CVRegR11, X86::R11},
153  { codeview::RegisterId::CVRegR12, X86::R12},
154  { codeview::RegisterId::CVRegR13, X86::R13},
155  { codeview::RegisterId::CVRegR14, X86::R14},
156  { codeview::RegisterId::CVRegR15, X86::R15},
157  { codeview::RegisterId::CVRegR8B, X86::R8B},
158  { codeview::RegisterId::CVRegR9B, X86::R9B},
159  { codeview::RegisterId::CVRegR10B, X86::R10B},
160  { codeview::RegisterId::CVRegR11B, X86::R11B},
161  { codeview::RegisterId::CVRegR12B, X86::R12B},
162  { codeview::RegisterId::CVRegR13B, X86::R13B},
163  { codeview::RegisterId::CVRegR14B, X86::R14B},
164  { codeview::RegisterId::CVRegR15B, X86::R15B},
165  { codeview::RegisterId::CVRegR8W, X86::R8W},
166  { codeview::RegisterId::CVRegR9W, X86::R9W},
167  { codeview::RegisterId::CVRegR10W, X86::R10W},
168  { codeview::RegisterId::CVRegR11W, X86::R11W},
169  { codeview::RegisterId::CVRegR12W, X86::R12W},
170  { codeview::RegisterId::CVRegR13W, X86::R13W},
171  { codeview::RegisterId::CVRegR14W, X86::R14W},
172  { codeview::RegisterId::CVRegR15W, X86::R15W},
173  { codeview::RegisterId::CVRegR8D, X86::R8D},
174  { codeview::RegisterId::CVRegR9D, X86::R9D},
175  { codeview::RegisterId::CVRegR10D, X86::R10D},
176  { codeview::RegisterId::CVRegR11D, X86::R11D},
177  { codeview::RegisterId::CVRegR12D, X86::R12D},
178  { codeview::RegisterId::CVRegR13D, X86::R13D},
179  { codeview::RegisterId::CVRegR14D, X86::R14D},
180  { codeview::RegisterId::CVRegR15D, X86::R15D},
181  { codeview::RegisterId::CVRegAMD64_YMM0, X86::YMM0},
182  { codeview::RegisterId::CVRegAMD64_YMM1, X86::YMM1},
183  { codeview::RegisterId::CVRegAMD64_YMM2, X86::YMM2},
184  { codeview::RegisterId::CVRegAMD64_YMM3, X86::YMM3},
185  { codeview::RegisterId::CVRegAMD64_YMM4, X86::YMM4},
186  { codeview::RegisterId::CVRegAMD64_YMM5, X86::YMM5},
187  { codeview::RegisterId::CVRegAMD64_YMM6, X86::YMM6},
188  { codeview::RegisterId::CVRegAMD64_YMM7, X86::YMM7},
189  { codeview::RegisterId::CVRegAMD64_YMM8, X86::YMM8},
190  { codeview::RegisterId::CVRegAMD64_YMM9, X86::YMM9},
191  { codeview::RegisterId::CVRegAMD64_YMM10, X86::YMM10},
192  { codeview::RegisterId::CVRegAMD64_YMM11, X86::YMM11},
193  { codeview::RegisterId::CVRegAMD64_YMM12, X86::YMM12},
194  { codeview::RegisterId::CVRegAMD64_YMM13, X86::YMM13},
195  { codeview::RegisterId::CVRegAMD64_YMM14, X86::YMM14},
196  { codeview::RegisterId::CVRegAMD64_YMM15, X86::YMM15},
197  };
198  for (unsigned I = 0; I < array_lengthof(RegMap); ++I)
199  MRI->mapLLVMRegToCVReg(RegMap[I].Reg, static_cast<int>(RegMap[I].CVReg));
200 }
201 
203  StringRef CPU, StringRef FS) {
204  std::string ArchFS = X86_MC::ParseX86Triple(TT);
205  if (!FS.empty()) {
206  if (!ArchFS.empty())
207  ArchFS = (Twine(ArchFS) + "," + FS).str();
208  else
209  ArchFS = FS;
210  }
211 
212  std::string CPUName = CPU;
213  if (CPUName.empty())
214  CPUName = "generic";
215 
216  return createX86MCSubtargetInfoImpl(TT, CPUName, ArchFS);
217 }
218 
220  MCInstrInfo *X = new MCInstrInfo();
221  InitX86MCInstrInfo(X);
222  return X;
223 }
224 
226  unsigned RA = (TT.getArch() == Triple::x86_64)
227  ? X86::RIP // Should have dwarf #16.
228  : X86::EIP; // Should have dwarf #8.
229 
231  InitX86MCRegisterInfo(X, RA, X86_MC::getDwarfRegFlavour(TT, false),
232  X86_MC::getDwarfRegFlavour(TT, true), RA);
234  return X;
235 }
236 
238  const Triple &TheTriple) {
239  bool is64Bit = TheTriple.getArch() == Triple::x86_64;
240 
241  MCAsmInfo *MAI;
242  if (TheTriple.isOSBinFormatMachO()) {
243  if (is64Bit)
244  MAI = new X86_64MCAsmInfoDarwin(TheTriple);
245  else
246  MAI = new X86MCAsmInfoDarwin(TheTriple);
247  } else if (TheTriple.isOSBinFormatELF()) {
248  // Force the use of an ELF container.
249  MAI = new X86ELFMCAsmInfo(TheTriple);
250  } else if (TheTriple.isWindowsMSVCEnvironment() ||
251  TheTriple.isWindowsCoreCLREnvironment()) {
252  MAI = new X86MCAsmInfoMicrosoft(TheTriple);
253  } else if (TheTriple.isOSCygMing() ||
254  TheTriple.isWindowsItaniumEnvironment()) {
255  MAI = new X86MCAsmInfoGNUCOFF(TheTriple);
256  } else {
257  // The default is ELF.
258  MAI = new X86ELFMCAsmInfo(TheTriple);
259  }
260 
261  // Initialize initial frame state.
262  // Calculate amount of bytes used for return address storing
263  int stackGrowth = is64Bit ? -8 : -4;
264 
265  // Initial state of the frame pointer is esp+stackGrowth.
266  unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP;
268  nullptr, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth);
269  MAI->addInitialFrameState(Inst);
270 
271  // Add return address to move list
272  unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP;
274  nullptr, MRI.getDwarfRegNum(InstPtr, true), stackGrowth);
275  MAI->addInitialFrameState(Inst2);
276 
277  return MAI;
278 }
279 
281  unsigned SyntaxVariant,
282  const MCAsmInfo &MAI,
283  const MCInstrInfo &MII,
284  const MCRegisterInfo &MRI) {
285  if (SyntaxVariant == 0)
286  return new X86ATTInstPrinter(MAI, MII, MRI);
287  if (SyntaxVariant == 1)
288  return new X86IntelInstPrinter(MAI, MII, MRI);
289  return nullptr;
290 }
291 
293  MCContext &Ctx) {
294  // Default to the stock relocation info.
295  return llvm::createMCRelocationInfo(TheTriple, Ctx);
296 }
297 
298 namespace llvm {
299 namespace X86_MC {
300 
302  X86MCInstrAnalysis(const X86MCInstrAnalysis &) = delete;
303  X86MCInstrAnalysis &operator=(const X86MCInstrAnalysis &) = delete;
304  virtual ~X86MCInstrAnalysis() = default;
305 
306 public:
308 
309  bool clearsSuperRegisters(const MCRegisterInfo &MRI, const MCInst &Inst,
310  APInt &Mask) const override;
311 };
312 
314  const MCInst &Inst,
315  APInt &Mask) const {
316  const MCInstrDesc &Desc = Info->get(Inst.getOpcode());
317  unsigned NumDefs = Desc.getNumDefs();
318  unsigned NumImplicitDefs = Desc.getNumImplicitDefs();
319  assert(Mask.getBitWidth() == NumDefs + NumImplicitDefs &&
320  "Unexpected number of bits in the mask!");
321 
322  bool HasVEX = (Desc.TSFlags & X86II::EncodingMask) == X86II::VEX;
323  bool HasEVEX = (Desc.TSFlags & X86II::EncodingMask) == X86II::EVEX;
324  bool HasXOP = (Desc.TSFlags & X86II::EncodingMask) == X86II::XOP;
325 
326  const MCRegisterClass &GR32RC = MRI.getRegClass(X86::GR32RegClassID);
327  const MCRegisterClass &VR128XRC = MRI.getRegClass(X86::VR128XRegClassID);
328  const MCRegisterClass &VR256XRC = MRI.getRegClass(X86::VR256XRegClassID);
329 
330  auto ClearsSuperReg = [=](unsigned RegID) {
331  // On X86-64, a general purpose integer register is viewed as a 64-bit
332  // register internal to the processor.
333  // An update to the lower 32 bits of a 64 bit integer register is
334  // architecturally defined to zero extend the upper 32 bits.
335  if (GR32RC.contains(RegID))
336  return true;
337 
338  // Early exit if this instruction has no vex/evex/xop prefix.
339  if (!HasEVEX && !HasVEX && !HasXOP)
340  return false;
341 
342  // All VEX and EVEX encoded instructions are defined to zero the high bits
343  // of the destination register up to VLMAX (i.e. the maximum vector register
344  // width pertaining to the instruction).
345  // We assume the same behavior for XOP instructions too.
346  return VR128XRC.contains(RegID) || VR256XRC.contains(RegID);
347  };
348 
349  Mask.clearAllBits();
350  for (unsigned I = 0, E = NumDefs; I < E; ++I) {
351  const MCOperand &Op = Inst.getOperand(I);
352  if (ClearsSuperReg(Op.getReg()))
353  Mask.setBit(I);
354  }
355 
356  for (unsigned I = 0, E = NumImplicitDefs; I < E; ++I) {
357  const MCPhysReg Reg = Desc.getImplicitDefs()[I];
358  if (ClearsSuperReg(Reg))
359  Mask.setBit(NumDefs + I);
360  }
361 
362  return Mask.getBoolValue();
363 }
364 
365 } // end of namespace X86_MC
366 
367 } // end of namespace llvm
368 
370  return new X86_MC::X86MCInstrAnalysis(Info);
371 }
372 
373 // Force static initialization.
374 extern "C" void LLVMInitializeX86TargetMC() {
375  for (Target *T : {&getTheX86_32Target(), &getTheX86_64Target()}) {
376  // Register the MC asm info.
378 
379  // Register the MC instruction info.
381 
382  // Register the MC register info.
384 
385  // Register the MC subtarget info.
388 
389  // Register the MC instruction analyzer.
391 
392  // Register the code emitter.
394 
395  // Register the obj target streamer.
398 
399  // Register the asm target streamer.
401 
403 
404  // Register the MCInstPrinter.
406 
407  // Register the MC relocation info.
409  }
410 
411  // Register the asm backend.
416 }
417 
418 unsigned llvm::getX86SubSuperRegisterOrZero(unsigned Reg, unsigned Size,
419  bool High) {
420  switch (Size) {
421  default: return 0;
422  case 8:
423  if (High) {
424  switch (Reg) {
425  default: return getX86SubSuperRegisterOrZero(Reg, 64);
426  case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
427  return X86::SI;
428  case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
429  return X86::DI;
430  case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
431  return X86::BP;
432  case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
433  return X86::SP;
434  case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
435  return X86::AH;
436  case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
437  return X86::DH;
438  case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
439  return X86::CH;
440  case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
441  return X86::BH;
442  }
443  } else {
444  switch (Reg) {
445  default: return 0;
446  case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
447  return X86::AL;
448  case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
449  return X86::DL;
450  case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
451  return X86::CL;
452  case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
453  return X86::BL;
454  case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
455  return X86::SIL;
456  case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
457  return X86::DIL;
458  case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
459  return X86::BPL;
460  case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
461  return X86::SPL;
462  case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
463  return X86::R8B;
464  case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
465  return X86::R9B;
466  case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
467  return X86::R10B;
468  case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
469  return X86::R11B;
470  case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
471  return X86::R12B;
472  case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
473  return X86::R13B;
474  case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
475  return X86::R14B;
476  case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
477  return X86::R15B;
478  }
479  }
480  case 16:
481  switch (Reg) {
482  default: return 0;
483  case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
484  return X86::AX;
485  case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
486  return X86::DX;
487  case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
488  return X86::CX;
489  case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
490  return X86::BX;
491  case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
492  return X86::SI;
493  case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
494  return X86::DI;
495  case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
496  return X86::BP;
497  case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
498  return X86::SP;
499  case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
500  return X86::R8W;
501  case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
502  return X86::R9W;
503  case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
504  return X86::R10W;
505  case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
506  return X86::R11W;
507  case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
508  return X86::R12W;
509  case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
510  return X86::R13W;
511  case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
512  return X86::R14W;
513  case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
514  return X86::R15W;
515  }
516  case 32:
517  switch (Reg) {
518  default: return 0;
519  case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
520  return X86::EAX;
521  case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
522  return X86::EDX;
523  case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
524  return X86::ECX;
525  case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
526  return X86::EBX;
527  case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
528  return X86::ESI;
529  case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
530  return X86::EDI;
531  case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
532  return X86::EBP;
533  case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
534  return X86::ESP;
535  case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
536  return X86::R8D;
537  case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
538  return X86::R9D;
539  case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
540  return X86::R10D;
541  case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
542  return X86::R11D;
543  case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
544  return X86::R12D;
545  case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
546  return X86::R13D;
547  case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
548  return X86::R14D;
549  case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
550  return X86::R15D;
551  }
552  case 64:
553  switch (Reg) {
554  default: return 0;
555  case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
556  return X86::RAX;
557  case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
558  return X86::RDX;
559  case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
560  return X86::RCX;
561  case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
562  return X86::RBX;
563  case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
564  return X86::RSI;
565  case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
566  return X86::RDI;
567  case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
568  return X86::RBP;
569  case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
570  return X86::RSP;
571  case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
572  return X86::R8;
573  case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
574  return X86::R9;
575  case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
576  return X86::R10;
577  case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
578  return X86::R11;
579  case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
580  return X86::R12;
581  case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
582  return X86::R13;
583  case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
584  return X86::R14;
585  case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
586  return X86::R15;
587  }
588  }
589 }
590 
591 unsigned llvm::getX86SubSuperRegister(unsigned Reg, unsigned Size, bool High) {
592  unsigned Res = getX86SubSuperRegisterOrZero(Reg, Size, High);
593  assert(Res != 0 && "Unexpected register or VT");
594  return Res;
595 }
596 
597 
void clearAllBits()
Set every bit to 0.
Definition: APInt.h:1445
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:470
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
Definition: MCInstrDesc.h:542
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:588
static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)
RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target...
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:162
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
Definition: MCDwarf.h:480
MCTargetStreamer * createX86ObjectTargetStreamer(MCStreamer &OS, const MCSubtargetInfo &STI)
Implements X86-only directives for object files.
unsigned Reg
bool clearsSuperRegisters(const MCRegisterInfo &MRI, const MCInst &Inst, APInt &Mask) const override
Returns true if at least one of the register writes performed by.
static MCRegisterInfo * createX86MCRegisterInfo(const Triple &TT)
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.
unsigned getDwarfRegFlavour(const Triple &TT, bool isEH)
uint64_t High
static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1502
std::string ParseX86Triple(const Triple &TT)
X86MCInstrAnalysis(const MCInstrInfo *MCII)
SI optimize exec mask operations pre RA
MCAsmBackend * createX86_32AsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
void setBit(unsigned BitPosition)
Set a given bit to 1.
Definition: APInt.h:1396
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
bool contains(unsigned Reg) const
contains - Return true if the specified register is included in this register class.
MCCodeEmitter * createX86MCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
int getDwarfRegNum(unsigned RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
MCAsmBackend * createX86_64AsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
static void RegisterCOFFStreamer(Target &T, Target::COFFStreamerCtorTy Fn)
This file implements a class to represent arbitrary precision integral constant values and operations...
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:65
Context object for machine code objects.
Definition: MCContext.h:63
bool getBoolValue() const
Convert APInt to a boolean value.
Definition: APInt.h:477
static MCRelocationInfo * createX86MCRelocationInfo(const Triple &TheTriple, MCContext &Ctx)
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Definition: Triple.h:285
void addInitialFrameState(const MCCFIInstruction &Inst)
Definition: MCAsmInfo.h:596
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:133
void LLVMInitializeX86TargetMC()
bool isWindowsItaniumEnvironment() const
Definition: Triple.h:538
MCRegisterClass - Base class of TargetRegisterClass.
bool isWindowsCoreCLREnvironment() const
Definition: Triple.h:534
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:161
MCRelocationInfo * createMCRelocationInfo(const Triple &TT, MCContext &Ctx)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
Definition: MCInstrDesc.h:539
unsigned const MachineRegisterInfo * MRI
static MCCFIInstruction createDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it...
Definition: MCDwarf.h:453
XOP - Opcode prefix used by XOP instructions.
Definition: X86BaseInfo.h:522
const MCInstrInfo * Info
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
static bool is64Bit(const char *name)
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
MCStreamer * createX86WinCOFFStreamer(MCContext &C, std::unique_ptr< MCAsmBackend > &&AB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&CE, bool RelaxAll, bool IncrementalLinkerCompatible)
Construct an X86 Windows COFF machine code streamer which will generate PE/COFF format object files...
MCTargetStreamer * createX86AsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, bool isVerboseAsm)
Implements X86-only directives for assembly emission.
Create MCExprs from relocations found in an object file.
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:598
static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target...
static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
MCSubtargetInfo * createX86MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Create a X86 MCSubtargetInfo instance.
unsigned getX86SubSuperRegisterOrZero(unsigned, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
void initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI)
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:182
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:787
static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.
EnvironmentType getEnvironment() const
getEnvironment - Get the parsed environment type of this triple.
Definition: Triple.h:303
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:224
unsigned getX86SubSuperRegister(unsigned, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.
Target - Wrapper for Target specific information.
Class for arbitrary precision integers.
Definition: APInt.h:69
bool isOSCygMing() const
Tests for either Cygwin or MinGW OS.
Definition: Triple.h:551
static MCAsmInfo * createX86MCAsmInfo(const MCRegisterInfo &MRI, const Triple &TheTriple)
static MCInstrInfo * createX86MCInstrInfo()
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:40
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
void mapLLVMRegToCVReg(unsigned LLVMReg, int CVReg)
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)
RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target. ...
#define I(x, y, z)
Definition: MD5.cpp:58
Generic base class for all target subtargets.
Target & getTheX86_32Target()
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
RegisterMCAsmInfoFn - Helper template for registering a target assembly info implementation.
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
static void RegisterMCRelocationInfo(Target &T, Target::MCRelocationInfoCtorTy Fn)
RegisterMCRelocationInfo - Register an MCRelocationInfo implementation for the given target...
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
static MCInstrAnalysis * createX86MCInstrAnalysis(const MCInstrInfo *Info)
unsigned getOpcode() const
Definition: MCInst.h:174
bool isWindowsMSVCEnvironment() const
Checks if the environment could be MSVC.
Definition: Triple.h:523
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:35
static MCInstPrinter * createX86MCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
Target & getTheX86_64Target()
void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg)
mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register number mapping.
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.