LLVM  8.0.0svn
X86MCTargetDesc.cpp
Go to the documentation of this file.
1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides X86 specific target descriptions.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86MCTargetDesc.h"
17 #include "X86BaseInfo.h"
18 #include "X86MCAsmInfo.h"
19 #include "llvm/ADT/APInt.h"
20 #include "llvm/ADT/Triple.h"
23 #include "llvm/MC/MCInstrInfo.h"
24 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/MC/MCStreamer.h"
29 #include "llvm/Support/Host.h"
31 
32 #if _MSC_VER
33 #include <intrin.h>
34 #endif
35 
36 using namespace llvm;
37 
38 #define GET_REGINFO_MC_DESC
39 #include "X86GenRegisterInfo.inc"
40 
41 #define GET_INSTRINFO_MC_DESC
42 #define GET_GENINSTRINFO_MC_HELPERS
43 #include "X86GenInstrInfo.inc"
44 
45 #define GET_SUBTARGETINFO_MC_DESC
46 #include "X86GenSubtargetInfo.inc"
47 
48 std::string X86_MC::ParseX86Triple(const Triple &TT) {
49  std::string FS;
50  if (TT.getArch() == Triple::x86_64)
51  FS = "+64bit-mode,-32bit-mode,-16bit-mode";
52  else if (TT.getEnvironment() != Triple::CODE16)
53  FS = "-64bit-mode,+32bit-mode,-16bit-mode";
54  else
55  FS = "-64bit-mode,-32bit-mode,+16bit-mode";
56 
57  return FS;
58 }
59 
60 unsigned X86_MC::getDwarfRegFlavour(const Triple &TT, bool isEH) {
61  if (TT.getArch() == Triple::x86_64)
62  return DWARFFlavour::X86_64;
63 
64  if (TT.isOSDarwin())
66  if (TT.isOSCygMing())
67  // Unsupported by now, just quick fallback
70 }
71 
73  // FIXME: TableGen these.
74  for (unsigned Reg = X86::NoRegister + 1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
75  unsigned SEH = MRI->getEncodingValue(Reg);
76  MRI->mapLLVMRegToSEHReg(Reg, SEH);
77  }
78 
79  // Mapping from CodeView to MC register id.
80  static const struct {
82  MCPhysReg Reg;
83  } RegMap[] = {
85  {codeview::RegisterId::CL, X86::CL},
86  {codeview::RegisterId::DL, X86::DL},
88  {codeview::RegisterId::AH, X86::AH},
89  {codeview::RegisterId::CH, X86::CH},
90  {codeview::RegisterId::DH, X86::DH},
91  {codeview::RegisterId::BH, X86::BH},
92  {codeview::RegisterId::AX, X86::AX},
93  {codeview::RegisterId::CX, X86::CX},
94  {codeview::RegisterId::DX, X86::DX},
95  {codeview::RegisterId::BX, X86::BX},
96  {codeview::RegisterId::SP, X86::SP},
97  {codeview::RegisterId::BP, X86::BP},
99  {codeview::RegisterId::DI, X86::DI},
105  {codeview::RegisterId::EBP, X86::EBP},
108 
109  {codeview::RegisterId::EFLAGS, X86::EFLAGS},
110 
111  {codeview::RegisterId::ST0, X86::FP0},
112  {codeview::RegisterId::ST1, X86::FP1},
113  {codeview::RegisterId::ST2, X86::FP2},
114  {codeview::RegisterId::ST3, X86::FP3},
115  {codeview::RegisterId::ST4, X86::FP4},
116  {codeview::RegisterId::ST5, X86::FP5},
117  {codeview::RegisterId::ST6, X86::FP6},
118  {codeview::RegisterId::ST7, X86::FP7},
119 
120  {codeview::RegisterId::XMM0, X86::XMM0},
121  {codeview::RegisterId::XMM1, X86::XMM1},
122  {codeview::RegisterId::XMM2, X86::XMM2},
123  {codeview::RegisterId::XMM3, X86::XMM3},
124  {codeview::RegisterId::XMM4, X86::XMM4},
125  {codeview::RegisterId::XMM5, X86::XMM5},
126  {codeview::RegisterId::XMM6, X86::XMM6},
127  {codeview::RegisterId::XMM7, X86::XMM7},
128 
129  {codeview::RegisterId::XMM8, X86::XMM8},
130  {codeview::RegisterId::XMM9, X86::XMM9},
131  {codeview::RegisterId::XMM10, X86::XMM10},
132  {codeview::RegisterId::XMM11, X86::XMM11},
133  {codeview::RegisterId::XMM12, X86::XMM12},
134  {codeview::RegisterId::XMM13, X86::XMM13},
135  {codeview::RegisterId::XMM14, X86::XMM14},
136  {codeview::RegisterId::XMM15, X86::XMM15},
137 
138  {codeview::RegisterId::SIL, X86::SIL},
139  {codeview::RegisterId::DIL, X86::DIL},
140  {codeview::RegisterId::BPL, X86::BPL},
141  {codeview::RegisterId::SPL, X86::SPL},
142  {codeview::RegisterId::RAX, X86::RAX},
143  {codeview::RegisterId::RBX, X86::RBX},
144  {codeview::RegisterId::RCX, X86::RCX},
145  {codeview::RegisterId::RDX, X86::RDX},
146  {codeview::RegisterId::RSI, X86::RSI},
147  {codeview::RegisterId::RDI, X86::RDI},
148  {codeview::RegisterId::RBP, X86::RBP},
149  {codeview::RegisterId::RSP, X86::RSP},
150  {codeview::RegisterId::R8, X86::R8},
151  {codeview::RegisterId::R9, X86::R9},
152  {codeview::RegisterId::R10, X86::R10},
153  {codeview::RegisterId::R11, X86::R11},
154  {codeview::RegisterId::R12, X86::R12},
155  {codeview::RegisterId::R13, X86::R13},
156  {codeview::RegisterId::R14, X86::R14},
157  {codeview::RegisterId::R15, X86::R15},
158  {codeview::RegisterId::R8B, X86::R8B},
159  {codeview::RegisterId::R9B, X86::R9B},
160  {codeview::RegisterId::R10B, X86::R10B},
161  {codeview::RegisterId::R11B, X86::R11B},
162  {codeview::RegisterId::R12B, X86::R12B},
163  {codeview::RegisterId::R13B, X86::R13B},
164  {codeview::RegisterId::R14B, X86::R14B},
165  {codeview::RegisterId::R15B, X86::R15B},
166  {codeview::RegisterId::R8W, X86::R8W},
167  {codeview::RegisterId::R9W, X86::R9W},
168  {codeview::RegisterId::R10W, X86::R10W},
169  {codeview::RegisterId::R11W, X86::R11W},
170  {codeview::RegisterId::R12W, X86::R12W},
171  {codeview::RegisterId::R13W, X86::R13W},
172  {codeview::RegisterId::R14W, X86::R14W},
173  {codeview::RegisterId::R15W, X86::R15W},
174  {codeview::RegisterId::R8D, X86::R8D},
175  {codeview::RegisterId::R9D, X86::R9D},
176  {codeview::RegisterId::R10D, X86::R10D},
177  {codeview::RegisterId::R11D, X86::R11D},
178  {codeview::RegisterId::R12D, X86::R12D},
179  {codeview::RegisterId::R13D, X86::R13D},
180  {codeview::RegisterId::R14D, X86::R14D},
181  {codeview::RegisterId::R15D, X86::R15D},
182  {codeview::RegisterId::AMD64_YMM0, X86::YMM0},
183  {codeview::RegisterId::AMD64_YMM1, X86::YMM1},
184  {codeview::RegisterId::AMD64_YMM2, X86::YMM2},
185  {codeview::RegisterId::AMD64_YMM3, X86::YMM3},
186  {codeview::RegisterId::AMD64_YMM4, X86::YMM4},
187  {codeview::RegisterId::AMD64_YMM5, X86::YMM5},
188  {codeview::RegisterId::AMD64_YMM6, X86::YMM6},
189  {codeview::RegisterId::AMD64_YMM7, X86::YMM7},
190  {codeview::RegisterId::AMD64_YMM8, X86::YMM8},
191  {codeview::RegisterId::AMD64_YMM9, X86::YMM9},
192  {codeview::RegisterId::AMD64_YMM10, X86::YMM10},
193  {codeview::RegisterId::AMD64_YMM11, X86::YMM11},
194  {codeview::RegisterId::AMD64_YMM12, X86::YMM12},
195  {codeview::RegisterId::AMD64_YMM13, X86::YMM13},
196  {codeview::RegisterId::AMD64_YMM14, X86::YMM14},
197  {codeview::RegisterId::AMD64_YMM15, X86::YMM15},
198  {codeview::RegisterId::AMD64_YMM16, X86::YMM16},
199  {codeview::RegisterId::AMD64_YMM17, X86::YMM17},
200  {codeview::RegisterId::AMD64_YMM18, X86::YMM18},
201  {codeview::RegisterId::AMD64_YMM19, X86::YMM19},
202  {codeview::RegisterId::AMD64_YMM20, X86::YMM20},
203  {codeview::RegisterId::AMD64_YMM21, X86::YMM21},
204  {codeview::RegisterId::AMD64_YMM22, X86::YMM22},
205  {codeview::RegisterId::AMD64_YMM23, X86::YMM23},
206  {codeview::RegisterId::AMD64_YMM24, X86::YMM24},
207  {codeview::RegisterId::AMD64_YMM25, X86::YMM25},
208  {codeview::RegisterId::AMD64_YMM26, X86::YMM26},
209  {codeview::RegisterId::AMD64_YMM27, X86::YMM27},
210  {codeview::RegisterId::AMD64_YMM28, X86::YMM28},
211  {codeview::RegisterId::AMD64_YMM29, X86::YMM29},
212  {codeview::RegisterId::AMD64_YMM30, X86::YMM30},
213  {codeview::RegisterId::AMD64_YMM31, X86::YMM31},
214  {codeview::RegisterId::AMD64_ZMM0, X86::ZMM0},
215  {codeview::RegisterId::AMD64_ZMM1, X86::ZMM1},
216  {codeview::RegisterId::AMD64_ZMM2, X86::ZMM2},
217  {codeview::RegisterId::AMD64_ZMM3, X86::ZMM3},
218  {codeview::RegisterId::AMD64_ZMM4, X86::ZMM4},
219  {codeview::RegisterId::AMD64_ZMM5, X86::ZMM5},
220  {codeview::RegisterId::AMD64_ZMM6, X86::ZMM6},
221  {codeview::RegisterId::AMD64_ZMM7, X86::ZMM7},
222  {codeview::RegisterId::AMD64_ZMM8, X86::ZMM8},
223  {codeview::RegisterId::AMD64_ZMM9, X86::ZMM9},
224  {codeview::RegisterId::AMD64_ZMM10, X86::ZMM10},
225  {codeview::RegisterId::AMD64_ZMM11, X86::ZMM11},
226  {codeview::RegisterId::AMD64_ZMM12, X86::ZMM12},
227  {codeview::RegisterId::AMD64_ZMM13, X86::ZMM13},
228  {codeview::RegisterId::AMD64_ZMM14, X86::ZMM14},
229  {codeview::RegisterId::AMD64_ZMM15, X86::ZMM15},
230  {codeview::RegisterId::AMD64_ZMM16, X86::ZMM16},
231  {codeview::RegisterId::AMD64_ZMM17, X86::ZMM17},
232  {codeview::RegisterId::AMD64_ZMM18, X86::ZMM18},
233  {codeview::RegisterId::AMD64_ZMM19, X86::ZMM19},
234  {codeview::RegisterId::AMD64_ZMM20, X86::ZMM20},
235  {codeview::RegisterId::AMD64_ZMM21, X86::ZMM21},
236  {codeview::RegisterId::AMD64_ZMM22, X86::ZMM22},
237  {codeview::RegisterId::AMD64_ZMM23, X86::ZMM23},
238  {codeview::RegisterId::AMD64_ZMM24, X86::ZMM24},
239  {codeview::RegisterId::AMD64_ZMM25, X86::ZMM25},
240  {codeview::RegisterId::AMD64_ZMM26, X86::ZMM26},
241  {codeview::RegisterId::AMD64_ZMM27, X86::ZMM27},
242  {codeview::RegisterId::AMD64_ZMM28, X86::ZMM28},
243  {codeview::RegisterId::AMD64_ZMM29, X86::ZMM29},
244  {codeview::RegisterId::AMD64_ZMM30, X86::ZMM30},
245  {codeview::RegisterId::AMD64_ZMM31, X86::ZMM31},
246  {codeview::RegisterId::AMD64_K0, X86::K0},
247  {codeview::RegisterId::AMD64_K1, X86::K1},
248  {codeview::RegisterId::AMD64_K2, X86::K2},
249  {codeview::RegisterId::AMD64_K3, X86::K3},
250  {codeview::RegisterId::AMD64_K4, X86::K4},
251  {codeview::RegisterId::AMD64_K5, X86::K5},
252  {codeview::RegisterId::AMD64_K6, X86::K6},
253  {codeview::RegisterId::AMD64_K7, X86::K7},
254  {codeview::RegisterId::AMD64_XMM16, X86::XMM16},
255  {codeview::RegisterId::AMD64_XMM17, X86::XMM17},
256  {codeview::RegisterId::AMD64_XMM18, X86::XMM18},
257  {codeview::RegisterId::AMD64_XMM19, X86::XMM19},
258  {codeview::RegisterId::AMD64_XMM20, X86::XMM20},
259  {codeview::RegisterId::AMD64_XMM21, X86::XMM21},
260  {codeview::RegisterId::AMD64_XMM22, X86::XMM22},
261  {codeview::RegisterId::AMD64_XMM23, X86::XMM23},
262  {codeview::RegisterId::AMD64_XMM24, X86::XMM24},
263  {codeview::RegisterId::AMD64_XMM25, X86::XMM25},
264  {codeview::RegisterId::AMD64_XMM26, X86::XMM26},
265  {codeview::RegisterId::AMD64_XMM27, X86::XMM27},
266  {codeview::RegisterId::AMD64_XMM28, X86::XMM28},
267  {codeview::RegisterId::AMD64_XMM29, X86::XMM29},
268  {codeview::RegisterId::AMD64_XMM30, X86::XMM30},
269  {codeview::RegisterId::AMD64_XMM31, X86::XMM31},
270 
271  };
272  for (unsigned I = 0; I < array_lengthof(RegMap); ++I)
273  MRI->mapLLVMRegToCVReg(RegMap[I].Reg, static_cast<int>(RegMap[I].CVReg));
274 }
275 
277  StringRef CPU, StringRef FS) {
278  std::string ArchFS = X86_MC::ParseX86Triple(TT);
279  if (!FS.empty()) {
280  if (!ArchFS.empty())
281  ArchFS = (Twine(ArchFS) + "," + FS).str();
282  else
283  ArchFS = FS;
284  }
285 
286  std::string CPUName = CPU;
287  if (CPUName.empty())
288  CPUName = "generic";
289 
290  return createX86MCSubtargetInfoImpl(TT, CPUName, ArchFS);
291 }
292 
294  MCInstrInfo *X = new MCInstrInfo();
295  InitX86MCInstrInfo(X);
296  return X;
297 }
298 
300  unsigned RA = (TT.getArch() == Triple::x86_64)
301  ? X86::RIP // Should have dwarf #16.
302  : X86::EIP; // Should have dwarf #8.
303 
305  InitX86MCRegisterInfo(X, RA, X86_MC::getDwarfRegFlavour(TT, false),
306  X86_MC::getDwarfRegFlavour(TT, true), RA);
308  return X;
309 }
310 
312  const Triple &TheTriple) {
313  bool is64Bit = TheTriple.getArch() == Triple::x86_64;
314 
315  MCAsmInfo *MAI;
316  if (TheTriple.isOSBinFormatMachO()) {
317  if (is64Bit)
318  MAI = new X86_64MCAsmInfoDarwin(TheTriple);
319  else
320  MAI = new X86MCAsmInfoDarwin(TheTriple);
321  } else if (TheTriple.isOSBinFormatELF()) {
322  // Force the use of an ELF container.
323  MAI = new X86ELFMCAsmInfo(TheTriple);
324  } else if (TheTriple.isWindowsMSVCEnvironment() ||
325  TheTriple.isWindowsCoreCLREnvironment()) {
326  MAI = new X86MCAsmInfoMicrosoft(TheTriple);
327  } else if (TheTriple.isOSCygMing() ||
328  TheTriple.isWindowsItaniumEnvironment()) {
329  MAI = new X86MCAsmInfoGNUCOFF(TheTriple);
330  } else {
331  // The default is ELF.
332  MAI = new X86ELFMCAsmInfo(TheTriple);
333  }
334 
335  // Initialize initial frame state.
336  // Calculate amount of bytes used for return address storing
337  int stackGrowth = is64Bit ? -8 : -4;
338 
339  // Initial state of the frame pointer is esp+stackGrowth.
340  unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP;
342  nullptr, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth);
343  MAI->addInitialFrameState(Inst);
344 
345  // Add return address to move list
346  unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP;
348  nullptr, MRI.getDwarfRegNum(InstPtr, true), stackGrowth);
349  MAI->addInitialFrameState(Inst2);
350 
351  return MAI;
352 }
353 
355  unsigned SyntaxVariant,
356  const MCAsmInfo &MAI,
357  const MCInstrInfo &MII,
358  const MCRegisterInfo &MRI) {
359  if (SyntaxVariant == 0)
360  return new X86ATTInstPrinter(MAI, MII, MRI);
361  if (SyntaxVariant == 1)
362  return new X86IntelInstPrinter(MAI, MII, MRI);
363  return nullptr;
364 }
365 
367  MCContext &Ctx) {
368  // Default to the stock relocation info.
369  return llvm::createMCRelocationInfo(TheTriple, Ctx);
370 }
371 
372 namespace llvm {
373 namespace X86_MC {
374 
376  X86MCInstrAnalysis(const X86MCInstrAnalysis &) = delete;
377  X86MCInstrAnalysis &operator=(const X86MCInstrAnalysis &) = delete;
378  virtual ~X86MCInstrAnalysis() = default;
379 
380 public:
382 
383 #define GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
384 #include "X86GenSubtargetInfo.inc"
385 
386  bool clearsSuperRegisters(const MCRegisterInfo &MRI, const MCInst &Inst,
387  APInt &Mask) const override;
388  std::vector<std::pair<uint64_t, uint64_t>>
389  findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,
390  uint64_t GotSectionVA,
391  const Triple &TargetTriple) const override;
392 };
393 
394 #define GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
395 #include "X86GenSubtargetInfo.inc"
396 
398  const MCInst &Inst,
399  APInt &Mask) const {
400  const MCInstrDesc &Desc = Info->get(Inst.getOpcode());
401  unsigned NumDefs = Desc.getNumDefs();
402  unsigned NumImplicitDefs = Desc.getNumImplicitDefs();
403  assert(Mask.getBitWidth() == NumDefs + NumImplicitDefs &&
404  "Unexpected number of bits in the mask!");
405 
406  bool HasVEX = (Desc.TSFlags & X86II::EncodingMask) == X86II::VEX;
407  bool HasEVEX = (Desc.TSFlags & X86II::EncodingMask) == X86II::EVEX;
408  bool HasXOP = (Desc.TSFlags & X86II::EncodingMask) == X86II::XOP;
409 
410  const MCRegisterClass &GR32RC = MRI.getRegClass(X86::GR32RegClassID);
411  const MCRegisterClass &VR128XRC = MRI.getRegClass(X86::VR128XRegClassID);
412  const MCRegisterClass &VR256XRC = MRI.getRegClass(X86::VR256XRegClassID);
413 
414  auto ClearsSuperReg = [=](unsigned RegID) {
415  // On X86-64, a general purpose integer register is viewed as a 64-bit
416  // register internal to the processor.
417  // An update to the lower 32 bits of a 64 bit integer register is
418  // architecturally defined to zero extend the upper 32 bits.
419  if (GR32RC.contains(RegID))
420  return true;
421 
422  // Early exit if this instruction has no vex/evex/xop prefix.
423  if (!HasEVEX && !HasVEX && !HasXOP)
424  return false;
425 
426  // All VEX and EVEX encoded instructions are defined to zero the high bits
427  // of the destination register up to VLMAX (i.e. the maximum vector register
428  // width pertaining to the instruction).
429  // We assume the same behavior for XOP instructions too.
430  return VR128XRC.contains(RegID) || VR256XRC.contains(RegID);
431  };
432 
433  Mask.clearAllBits();
434  for (unsigned I = 0, E = NumDefs; I < E; ++I) {
435  const MCOperand &Op = Inst.getOperand(I);
436  if (ClearsSuperReg(Op.getReg()))
437  Mask.setBit(I);
438  }
439 
440  for (unsigned I = 0, E = NumImplicitDefs; I < E; ++I) {
441  const MCPhysReg Reg = Desc.getImplicitDefs()[I];
442  if (ClearsSuperReg(Reg))
443  Mask.setBit(NumDefs + I);
444  }
445 
446  return Mask.getBoolValue();
447 }
448 
449 static std::vector<std::pair<uint64_t, uint64_t>>
450 findX86PltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,
451  uint64_t GotPltSectionVA) {
452  // Do a lightweight parsing of PLT entries.
453  std::vector<std::pair<uint64_t, uint64_t>> Result;
454  for (uint64_t Byte = 0, End = PltContents.size(); Byte + 6 < End; ) {
455  // Recognize a jmp.
456  if (PltContents[Byte] == 0xff && PltContents[Byte + 1] == 0xa3) {
457  // The jmp instruction at the beginning of each PLT entry jumps to the
458  // address of the base of the .got.plt section plus the immediate.
459  uint32_t Imm = support::endian::read32le(PltContents.data() + Byte + 2);
460  Result.push_back(
461  std::make_pair(PltSectionVA + Byte, GotPltSectionVA + Imm));
462  Byte += 6;
463  } else if (PltContents[Byte] == 0xff && PltContents[Byte + 1] == 0x25) {
464  // The jmp instruction at the beginning of each PLT entry jumps to the
465  // immediate.
466  uint32_t Imm = support::endian::read32le(PltContents.data() + Byte + 2);
467  Result.push_back(std::make_pair(PltSectionVA + Byte, Imm));
468  Byte += 6;
469  } else
470  Byte++;
471  }
472  return Result;
473 }
474 
475 static std::vector<std::pair<uint64_t, uint64_t>>
476 findX86_64PltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents) {
477  // Do a lightweight parsing of PLT entries.
478  std::vector<std::pair<uint64_t, uint64_t>> Result;
479  for (uint64_t Byte = 0, End = PltContents.size(); Byte + 6 < End; ) {
480  // Recognize a jmp.
481  if (PltContents[Byte] == 0xff && PltContents[Byte + 1] == 0x25) {
482  // The jmp instruction at the beginning of each PLT entry jumps to the
483  // address of the next instruction plus the immediate.
484  uint32_t Imm = support::endian::read32le(PltContents.data() + Byte + 2);
485  Result.push_back(
486  std::make_pair(PltSectionVA + Byte, PltSectionVA + Byte + 6 + Imm));
487  Byte += 6;
488  } else
489  Byte++;
490  }
491  return Result;
492 }
493 
494 std::vector<std::pair<uint64_t, uint64_t>> X86MCInstrAnalysis::findPltEntries(
495  uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,
496  uint64_t GotPltSectionVA, const Triple &TargetTriple) const {
497  switch (TargetTriple.getArch()) {
498  case Triple::x86:
499  return findX86PltEntries(PltSectionVA, PltContents, GotPltSectionVA);
500  case Triple::x86_64:
501  return findX86_64PltEntries(PltSectionVA, PltContents);
502  default:
503  return {};
504  }
505 }
506 
507 } // end of namespace X86_MC
508 
509 } // end of namespace llvm
510 
512  return new X86_MC::X86MCInstrAnalysis(Info);
513 }
514 
515 // Force static initialization.
516 extern "C" void LLVMInitializeX86TargetMC() {
517  for (Target *T : {&getTheX86_32Target(), &getTheX86_64Target()}) {
518  // Register the MC asm info.
520 
521  // Register the MC instruction info.
523 
524  // Register the MC register info.
526 
527  // Register the MC subtarget info.
530 
531  // Register the MC instruction analyzer.
533 
534  // Register the code emitter.
536 
537  // Register the obj target streamer.
540 
541  // Register the asm target streamer.
543 
545 
546  // Register the MCInstPrinter.
548 
549  // Register the MC relocation info.
551  }
552 
553  // Register the asm backend.
558 }
559 
560 unsigned llvm::getX86SubSuperRegisterOrZero(unsigned Reg, unsigned Size,
561  bool High) {
562  switch (Size) {
563  default: return 0;
564  case 8:
565  if (High) {
566  switch (Reg) {
567  default: return getX86SubSuperRegisterOrZero(Reg, 64);
568  case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
569  return X86::SI;
570  case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
571  return X86::DI;
572  case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
573  return X86::BP;
574  case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
575  return X86::SP;
576  case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
577  return X86::AH;
578  case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
579  return X86::DH;
580  case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
581  return X86::CH;
582  case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
583  return X86::BH;
584  }
585  } else {
586  switch (Reg) {
587  default: return 0;
588  case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
589  return X86::AL;
590  case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
591  return X86::DL;
592  case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
593  return X86::CL;
594  case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
595  return X86::BL;
596  case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
597  return X86::SIL;
598  case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
599  return X86::DIL;
600  case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
601  return X86::BPL;
602  case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
603  return X86::SPL;
604  case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
605  return X86::R8B;
606  case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
607  return X86::R9B;
608  case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
609  return X86::R10B;
610  case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
611  return X86::R11B;
612  case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
613  return X86::R12B;
614  case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
615  return X86::R13B;
616  case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
617  return X86::R14B;
618  case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
619  return X86::R15B;
620  }
621  }
622  case 16:
623  switch (Reg) {
624  default: return 0;
625  case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
626  return X86::AX;
627  case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
628  return X86::DX;
629  case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
630  return X86::CX;
631  case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
632  return X86::BX;
633  case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
634  return X86::SI;
635  case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
636  return X86::DI;
637  case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
638  return X86::BP;
639  case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
640  return X86::SP;
641  case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
642  return X86::R8W;
643  case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
644  return X86::R9W;
645  case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
646  return X86::R10W;
647  case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
648  return X86::R11W;
649  case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
650  return X86::R12W;
651  case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
652  return X86::R13W;
653  case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
654  return X86::R14W;
655  case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
656  return X86::R15W;
657  }
658  case 32:
659  switch (Reg) {
660  default: return 0;
661  case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
662  return X86::EAX;
663  case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
664  return X86::EDX;
665  case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
666  return X86::ECX;
667  case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
668  return X86::EBX;
669  case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
670  return X86::ESI;
671  case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
672  return X86::EDI;
673  case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
674  return X86::EBP;
675  case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
676  return X86::ESP;
677  case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
678  return X86::R8D;
679  case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
680  return X86::R9D;
681  case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
682  return X86::R10D;
683  case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
684  return X86::R11D;
685  case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
686  return X86::R12D;
687  case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
688  return X86::R13D;
689  case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
690  return X86::R14D;
691  case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
692  return X86::R15D;
693  }
694  case 64:
695  switch (Reg) {
696  default: return 0;
697  case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
698  return X86::RAX;
699  case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
700  return X86::RDX;
701  case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
702  return X86::RCX;
703  case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
704  return X86::RBX;
705  case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
706  return X86::RSI;
707  case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
708  return X86::RDI;
709  case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
710  return X86::RBP;
711  case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
712  return X86::RSP;
713  case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
714  return X86::R8;
715  case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
716  return X86::R9;
717  case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
718  return X86::R10;
719  case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
720  return X86::R11;
721  case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
722  return X86::R12;
723  case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
724  return X86::R13;
725  case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
726  return X86::R14;
727  case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
728  return X86::R15;
729  }
730  }
731 }
732 
733 unsigned llvm::getX86SubSuperRegister(unsigned Reg, unsigned Size, bool High) {
734  unsigned Res = getX86SubSuperRegisterOrZero(Reg, Size, High);
735  assert(Res != 0 && "Unexpected register or VT");
736  return Res;
737 }
738 
739 
void clearAllBits()
Set every bit to 0.
Definition: APInt.h:1446
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:474
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
Definition: MCInstrDesc.h:543
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:592
static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)
RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target...
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
Definition: MCDwarf.h:487
MCTargetStreamer * createX86ObjectTargetStreamer(MCStreamer &OS, const MCSubtargetInfo &STI)
Implements X86-only directives for object files.
unsigned Reg
bool clearsSuperRegisters(const MCRegisterInfo &MRI, const MCInst &Inst, APInt &Mask) const override
Returns true if at least one of the register writes performed by.
std::vector< std::pair< uint64_t, uint64_t > > findPltEntries(uint64_t PltSectionVA, ArrayRef< uint8_t > PltContents, uint64_t GotSectionVA, const Triple &TargetTriple) const override
Returns (PLT virtual address, GOT virtual address) pairs for PLT entries.
static MCRegisterInfo * createX86MCRegisterInfo(const Triple &TT)
XOP - Opcode prefix used by XOP instructions.
Definition: X86BaseInfo.h:527
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.
unsigned getDwarfRegFlavour(const Triple &TT, bool isEH)
uint64_t High
static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1503
std::string ParseX86Triple(const Triple &TT)
X86MCInstrAnalysis(const MCInstrInfo *MCII)
SI optimize exec mask operations pre RA
MCAsmBackend * createX86_32AsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
void setBit(unsigned BitPosition)
Set a given bit to 1.
Definition: APInt.h:1397
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
bool contains(unsigned Reg) const
contains - Return true if the specified register is included in this register class.
MCCodeEmitter * createX86MCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
int getDwarfRegNum(unsigned RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
MCAsmBackend * createX86_64AsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
static void RegisterCOFFStreamer(Target &T, Target::COFFStreamerCtorTy Fn)
This file implements a class to represent arbitrary precision integral constant values and operations...
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:65
Context object for machine code objects.
Definition: MCContext.h:63
bool getBoolValue() const
Convert APInt to a boolean value.
Definition: APInt.h:478
static MCRelocationInfo * createX86MCRelocationInfo(const Triple &TheTriple, MCContext &Ctx)
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Definition: Triple.h:289
void addInitialFrameState(const MCCFIInstruction &Inst)
Definition: MCAsmInfo.h:601
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:133
void LLVMInitializeX86TargetMC()
bool isWindowsItaniumEnvironment() const
Definition: Triple.h:542
MCRegisterClass - Base class of TargetRegisterClass.
bool isWindowsCoreCLREnvironment() const
Definition: Triple.h:538
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:161
MCRelocationInfo * createMCRelocationInfo(const Triple &TT, MCContext &Ctx)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
Definition: MCInstrDesc.h:540
unsigned const MachineRegisterInfo * MRI
static MCCFIInstruction createDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it...
Definition: MCDwarf.h:460
const MCInstrInfo * Info
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:149
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
static bool is64Bit(const char *name)
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
MCStreamer * createX86WinCOFFStreamer(MCContext &C, std::unique_ptr< MCAsmBackend > &&AB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&CE, bool RelaxAll, bool IncrementalLinkerCompatible)
Construct an X86 Windows COFF machine code streamer which will generate PE/COFF format object files...
MCTargetStreamer * createX86AsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, bool isVerboseAsm)
Implements X86-only directives for assembly emission.
Create MCExprs from relocations found in an object file.
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:602
static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target...
static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)
static std::vector< std::pair< uint64_t, uint64_t > > findX86_64PltEntries(uint64_t PltSectionVA, ArrayRef< uint8_t > PltContents)
const T * data() const
Definition: ArrayRef.h:146
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
MCSubtargetInfo * createX86MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Create a X86 MCSubtargetInfo instance.
unsigned getX86SubSuperRegisterOrZero(unsigned, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
void initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI)
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:182
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:900
static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.
EnvironmentType getEnvironment() const
getEnvironment - Get the parsed environment type of this triple.
Definition: Triple.h:307
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:225
unsigned getX86SubSuperRegister(unsigned, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.
Target - Wrapper for Target specific information.
Class for arbitrary precision integers.
Definition: APInt.h:70
bool isOSCygMing() const
Tests for either Cygwin or MinGW OS.
Definition: Triple.h:555
static MCAsmInfo * createX86MCAsmInfo(const MCRegisterInfo &MRI, const Triple &TheTriple)
static MCInstrInfo * createX86MCInstrInfo()
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:40
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
void mapLLVMRegToCVReg(unsigned LLVMReg, int CVReg)
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)
RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target. ...
#define I(x, y, z)
Definition: MD5.cpp:58
uint32_t read32le(const void *P)
Definition: Endian.h:369
static std::vector< std::pair< uint64_t, uint64_t > > findX86PltEntries(uint64_t PltSectionVA, ArrayRef< uint8_t > PltContents, uint64_t GotPltSectionVA)
Generic base class for all target subtargets.
Target & getTheX86_32Target()
uint32_t Size
Definition: Profile.cpp:47
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
RegisterMCAsmInfoFn - Helper template for registering a target assembly info implementation.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
static void RegisterMCRelocationInfo(Target &T, Target::MCRelocationInfoCtorTy Fn)
RegisterMCRelocationInfo - Register an MCRelocationInfo implementation for the given target...
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
static MCInstrAnalysis * createX86MCInstrAnalysis(const MCInstrInfo *Info)
unsigned getOpcode() const
Definition: MCInst.h:174
bool isWindowsMSVCEnvironment() const
Checks if the environment could be MSVC.
Definition: Triple.h:527
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:35
static MCInstPrinter * createX86MCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
Target & getTheX86_64Target()
void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg)
mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register number mapping.
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.