LLVM  7.0.0svn
X86MCTargetDesc.cpp
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1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides X86 specific target descriptions.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86MCTargetDesc.h"
17 #include "X86MCAsmInfo.h"
18 #include "llvm/ADT/Triple.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCStreamer.h"
27 #include "llvm/Support/Host.h"
29 
30 #if _MSC_VER
31 #include <intrin.h>
32 #endif
33 
34 using namespace llvm;
35 
36 #define GET_REGINFO_MC_DESC
37 #include "X86GenRegisterInfo.inc"
38 
39 #define GET_INSTRINFO_MC_DESC
40 #include "X86GenInstrInfo.inc"
41 
42 #define GET_SUBTARGETINFO_MC_DESC
43 #include "X86GenSubtargetInfo.inc"
44 
45 std::string X86_MC::ParseX86Triple(const Triple &TT) {
46  std::string FS;
47  if (TT.getArch() == Triple::x86_64)
48  FS = "+64bit-mode,-32bit-mode,-16bit-mode";
49  else if (TT.getEnvironment() != Triple::CODE16)
50  FS = "-64bit-mode,+32bit-mode,-16bit-mode";
51  else
52  FS = "-64bit-mode,-32bit-mode,+16bit-mode";
53 
54  return FS;
55 }
56 
57 unsigned X86_MC::getDwarfRegFlavour(const Triple &TT, bool isEH) {
58  if (TT.getArch() == Triple::x86_64)
59  return DWARFFlavour::X86_64;
60 
61  if (TT.isOSDarwin())
63  if (TT.isOSCygMing())
64  // Unsupported by now, just quick fallback
67 }
68 
70  // FIXME: TableGen these.
71  for (unsigned Reg = X86::NoRegister + 1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
72  unsigned SEH = MRI->getEncodingValue(Reg);
73  MRI->mapLLVMRegToSEHReg(Reg, SEH);
74  }
75 
76  // Mapping from CodeView to MC register id.
77  static const struct {
79  MCPhysReg Reg;
80  } RegMap[] = {
82  { codeview::RegisterId::CL, X86::CL},
83  { codeview::RegisterId::DL, X86::DL},
85  { codeview::RegisterId::AH, X86::AH},
86  { codeview::RegisterId::CH, X86::CH},
87  { codeview::RegisterId::DH, X86::DH},
88  { codeview::RegisterId::BH, X86::BH},
89  { codeview::RegisterId::AX, X86::AX},
90  { codeview::RegisterId::CX, X86::CX},
91  { codeview::RegisterId::DX, X86::DX},
92  { codeview::RegisterId::BX, X86::BX},
93  { codeview::RegisterId::SP, X86::SP},
94  { codeview::RegisterId::BP, X86::BP},
96  { codeview::RegisterId::DI, X86::DI},
102  { codeview::RegisterId::EBP, X86::EBP},
105 
106  { codeview::RegisterId::EFLAGS, X86::EFLAGS},
107 
108  { codeview::RegisterId::ST0, X86::FP0},
109  { codeview::RegisterId::ST1, X86::FP1},
110  { codeview::RegisterId::ST2, X86::FP2},
111  { codeview::RegisterId::ST3, X86::FP3},
112  { codeview::RegisterId::ST4, X86::FP4},
113  { codeview::RegisterId::ST5, X86::FP5},
114  { codeview::RegisterId::ST6, X86::FP6},
115  { codeview::RegisterId::ST7, X86::FP7},
116 
117  { codeview::RegisterId::XMM0, X86::XMM0},
118  { codeview::RegisterId::XMM1, X86::XMM1},
119  { codeview::RegisterId::XMM2, X86::XMM2},
120  { codeview::RegisterId::XMM3, X86::XMM3},
121  { codeview::RegisterId::XMM4, X86::XMM4},
122  { codeview::RegisterId::XMM5, X86::XMM5},
123  { codeview::RegisterId::XMM6, X86::XMM6},
124  { codeview::RegisterId::XMM7, X86::XMM7},
125 
126  { codeview::RegisterId::XMM8, X86::XMM8},
127  { codeview::RegisterId::XMM9, X86::XMM9},
128  { codeview::RegisterId::XMM10, X86::XMM10},
129  { codeview::RegisterId::XMM11, X86::XMM11},
130  { codeview::RegisterId::XMM12, X86::XMM12},
131  { codeview::RegisterId::XMM13, X86::XMM13},
132  { codeview::RegisterId::XMM14, X86::XMM14},
133  { codeview::RegisterId::XMM15, X86::XMM15},
134 
135  { codeview::RegisterId::SIL, X86::SIL},
136  { codeview::RegisterId::DIL, X86::DIL},
137  { codeview::RegisterId::BPL, X86::BPL},
138  { codeview::RegisterId::SPL, X86::SPL},
139  { codeview::RegisterId::RAX, X86::RAX},
140  { codeview::RegisterId::RBX, X86::RBX},
141  { codeview::RegisterId::RCX, X86::RCX},
142  { codeview::RegisterId::RDX, X86::RDX},
143  { codeview::RegisterId::RSI, X86::RSI},
144  { codeview::RegisterId::RDI, X86::RDI},
145  { codeview::RegisterId::RBP, X86::RBP},
146  { codeview::RegisterId::RSP, X86::RSP},
147  { codeview::RegisterId::R8, X86::R8},
148  { codeview::RegisterId::R9, X86::R9},
149  { codeview::RegisterId::R10, X86::R10},
150  { codeview::RegisterId::R11, X86::R11},
151  { codeview::RegisterId::R12, X86::R12},
152  { codeview::RegisterId::R13, X86::R13},
153  { codeview::RegisterId::R14, X86::R14},
154  { codeview::RegisterId::R15, X86::R15},
155  { codeview::RegisterId::R8B, X86::R8B},
156  { codeview::RegisterId::R9B, X86::R9B},
157  { codeview::RegisterId::R10B, X86::R10B},
158  { codeview::RegisterId::R11B, X86::R11B},
159  { codeview::RegisterId::R12B, X86::R12B},
160  { codeview::RegisterId::R13B, X86::R13B},
161  { codeview::RegisterId::R14B, X86::R14B},
162  { codeview::RegisterId::R15B, X86::R15B},
163  { codeview::RegisterId::R8W, X86::R8W},
164  { codeview::RegisterId::R9W, X86::R9W},
165  { codeview::RegisterId::R10W, X86::R10W},
166  { codeview::RegisterId::R11W, X86::R11W},
167  { codeview::RegisterId::R12W, X86::R12W},
168  { codeview::RegisterId::R13W, X86::R13W},
169  { codeview::RegisterId::R14W, X86::R14W},
170  { codeview::RegisterId::R15W, X86::R15W},
171  { codeview::RegisterId::R8D, X86::R8D},
172  { codeview::RegisterId::R9D, X86::R9D},
173  { codeview::RegisterId::R10D, X86::R10D},
174  { codeview::RegisterId::R11D, X86::R11D},
175  { codeview::RegisterId::R12D, X86::R12D},
176  { codeview::RegisterId::R13D, X86::R13D},
177  { codeview::RegisterId::R14D, X86::R14D},
178  { codeview::RegisterId::R15D, X86::R15D},
179  { codeview::RegisterId::AMD64_YMM0, X86::YMM0},
180  { codeview::RegisterId::AMD64_YMM1, X86::YMM1},
181  { codeview::RegisterId::AMD64_YMM2, X86::YMM2},
182  { codeview::RegisterId::AMD64_YMM3, X86::YMM3},
183  { codeview::RegisterId::AMD64_YMM4, X86::YMM4},
184  { codeview::RegisterId::AMD64_YMM5, X86::YMM5},
185  { codeview::RegisterId::AMD64_YMM6, X86::YMM6},
186  { codeview::RegisterId::AMD64_YMM7, X86::YMM7},
187  { codeview::RegisterId::AMD64_YMM8, X86::YMM8},
188  { codeview::RegisterId::AMD64_YMM9, X86::YMM9},
189  { codeview::RegisterId::AMD64_YMM10, X86::YMM10},
190  { codeview::RegisterId::AMD64_YMM11, X86::YMM11},
191  { codeview::RegisterId::AMD64_YMM12, X86::YMM12},
192  { codeview::RegisterId::AMD64_YMM13, X86::YMM13},
193  { codeview::RegisterId::AMD64_YMM14, X86::YMM14},
194  { codeview::RegisterId::AMD64_YMM15, X86::YMM15},
195  };
196  for (unsigned I = 0; I < array_lengthof(RegMap); ++I)
197  MRI->mapLLVMRegToCVReg(RegMap[I].Reg, static_cast<int>(RegMap[I].CVReg));
198 }
199 
201  StringRef CPU, StringRef FS) {
202  std::string ArchFS = X86_MC::ParseX86Triple(TT);
203  if (!FS.empty()) {
204  if (!ArchFS.empty())
205  ArchFS = (Twine(ArchFS) + "," + FS).str();
206  else
207  ArchFS = FS;
208  }
209 
210  std::string CPUName = CPU;
211  if (CPUName.empty())
212  CPUName = "generic";
213 
214  return createX86MCSubtargetInfoImpl(TT, CPUName, ArchFS);
215 }
216 
218  MCInstrInfo *X = new MCInstrInfo();
219  InitX86MCInstrInfo(X);
220  return X;
221 }
222 
224  unsigned RA = (TT.getArch() == Triple::x86_64)
225  ? X86::RIP // Should have dwarf #16.
226  : X86::EIP; // Should have dwarf #8.
227 
229  InitX86MCRegisterInfo(X, RA, X86_MC::getDwarfRegFlavour(TT, false),
230  X86_MC::getDwarfRegFlavour(TT, true), RA);
232  return X;
233 }
234 
236  const Triple &TheTriple) {
237  bool is64Bit = TheTriple.getArch() == Triple::x86_64;
238 
239  MCAsmInfo *MAI;
240  if (TheTriple.isOSBinFormatMachO()) {
241  if (is64Bit)
242  MAI = new X86_64MCAsmInfoDarwin(TheTriple);
243  else
244  MAI = new X86MCAsmInfoDarwin(TheTriple);
245  } else if (TheTriple.isOSBinFormatELF()) {
246  // Force the use of an ELF container.
247  MAI = new X86ELFMCAsmInfo(TheTriple);
248  } else if (TheTriple.isWindowsMSVCEnvironment() ||
249  TheTriple.isWindowsCoreCLREnvironment()) {
250  MAI = new X86MCAsmInfoMicrosoft(TheTriple);
251  } else if (TheTriple.isOSCygMing() ||
252  TheTriple.isWindowsItaniumEnvironment()) {
253  MAI = new X86MCAsmInfoGNUCOFF(TheTriple);
254  } else {
255  // The default is ELF.
256  MAI = new X86ELFMCAsmInfo(TheTriple);
257  }
258 
259  // Initialize initial frame state.
260  // Calculate amount of bytes used for return address storing
261  int stackGrowth = is64Bit ? -8 : -4;
262 
263  // Initial state of the frame pointer is esp+stackGrowth.
264  unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP;
266  nullptr, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth);
267  MAI->addInitialFrameState(Inst);
268 
269  // Add return address to move list
270  unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP;
272  nullptr, MRI.getDwarfRegNum(InstPtr, true), stackGrowth);
273  MAI->addInitialFrameState(Inst2);
274 
275  return MAI;
276 }
277 
279  unsigned SyntaxVariant,
280  const MCAsmInfo &MAI,
281  const MCInstrInfo &MII,
282  const MCRegisterInfo &MRI) {
283  if (SyntaxVariant == 0)
284  return new X86ATTInstPrinter(MAI, MII, MRI);
285  if (SyntaxVariant == 1)
286  return new X86IntelInstPrinter(MAI, MII, MRI);
287  return nullptr;
288 }
289 
291  MCContext &Ctx) {
292  // Default to the stock relocation info.
293  return llvm::createMCRelocationInfo(TheTriple, Ctx);
294 }
295 
297  return new MCInstrAnalysis(Info);
298 }
299 
300 // Force static initialization.
301 extern "C" void LLVMInitializeX86TargetMC() {
302  for (Target *T : {&getTheX86_32Target(), &getTheX86_64Target()}) {
303  // Register the MC asm info.
305 
306  // Register the MC instruction info.
308 
309  // Register the MC register info.
311 
312  // Register the MC subtarget info.
315 
316  // Register the MC instruction analyzer.
318 
319  // Register the code emitter.
321 
322  // Register the obj target streamer.
325 
326  // Register the asm target streamer.
328 
330 
331  // Register the MCInstPrinter.
333 
334  // Register the MC relocation info.
336  }
337 
338  // Register the asm backend.
343 }
344 
345 unsigned llvm::getX86SubSuperRegisterOrZero(unsigned Reg, unsigned Size,
346  bool High) {
347  switch (Size) {
348  default: return 0;
349  case 8:
350  if (High) {
351  switch (Reg) {
352  default: return getX86SubSuperRegisterOrZero(Reg, 64);
353  case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
354  return X86::SI;
355  case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
356  return X86::DI;
357  case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
358  return X86::BP;
359  case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
360  return X86::SP;
361  case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
362  return X86::AH;
363  case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
364  return X86::DH;
365  case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
366  return X86::CH;
367  case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
368  return X86::BH;
369  }
370  } else {
371  switch (Reg) {
372  default: return 0;
373  case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
374  return X86::AL;
375  case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
376  return X86::DL;
377  case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
378  return X86::CL;
379  case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
380  return X86::BL;
381  case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
382  return X86::SIL;
383  case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
384  return X86::DIL;
385  case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
386  return X86::BPL;
387  case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
388  return X86::SPL;
389  case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
390  return X86::R8B;
391  case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
392  return X86::R9B;
393  case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
394  return X86::R10B;
395  case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
396  return X86::R11B;
397  case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
398  return X86::R12B;
399  case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
400  return X86::R13B;
401  case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
402  return X86::R14B;
403  case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
404  return X86::R15B;
405  }
406  }
407  case 16:
408  switch (Reg) {
409  default: return 0;
410  case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
411  return X86::AX;
412  case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
413  return X86::DX;
414  case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
415  return X86::CX;
416  case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
417  return X86::BX;
418  case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
419  return X86::SI;
420  case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
421  return X86::DI;
422  case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
423  return X86::BP;
424  case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
425  return X86::SP;
426  case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
427  return X86::R8W;
428  case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
429  return X86::R9W;
430  case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
431  return X86::R10W;
432  case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
433  return X86::R11W;
434  case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
435  return X86::R12W;
436  case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
437  return X86::R13W;
438  case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
439  return X86::R14W;
440  case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
441  return X86::R15W;
442  }
443  case 32:
444  switch (Reg) {
445  default: return 0;
446  case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
447  return X86::EAX;
448  case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
449  return X86::EDX;
450  case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
451  return X86::ECX;
452  case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
453  return X86::EBX;
454  case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
455  return X86::ESI;
456  case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
457  return X86::EDI;
458  case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
459  return X86::EBP;
460  case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
461  return X86::ESP;
462  case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
463  return X86::R8D;
464  case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
465  return X86::R9D;
466  case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
467  return X86::R10D;
468  case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
469  return X86::R11D;
470  case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
471  return X86::R12D;
472  case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
473  return X86::R13D;
474  case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
475  return X86::R14D;
476  case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
477  return X86::R15D;
478  }
479  case 64:
480  switch (Reg) {
481  default: return 0;
482  case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
483  return X86::RAX;
484  case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
485  return X86::RDX;
486  case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
487  return X86::RCX;
488  case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
489  return X86::RBX;
490  case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
491  return X86::RSI;
492  case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
493  return X86::RDI;
494  case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
495  return X86::RBP;
496  case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
497  return X86::RSP;
498  case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
499  return X86::R8;
500  case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
501  return X86::R9;
502  case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
503  return X86::R10;
504  case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
505  return X86::R11;
506  case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
507  return X86::R12;
508  case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
509  return X86::R13;
510  case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
511  return X86::R14;
512  case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
513  return X86::R15;
514  }
515  }
516 }
517 
518 unsigned llvm::getX86SubSuperRegister(unsigned Reg, unsigned Size, bool High) {
519  unsigned Res = getX86SubSuperRegisterOrZero(Reg, Size, High);
520  assert(Res != 0 && "Unexpected register or VT");
521  return Res;
522 }
523 
524 
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:468
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:586
static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)
RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target...
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
Definition: MCDwarf.h:454
MCTargetStreamer * createX86ObjectTargetStreamer(MCStreamer &OS, const MCSubtargetInfo &STI)
Implements X86-only directives for object files.
static MCRegisterInfo * createX86MCRegisterInfo(const Triple &TT)
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.
unsigned getDwarfRegFlavour(const Triple &TT, bool isEH)
uint64_t High
static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)
std::string ParseX86Triple(const Triple &TT)
SI optimize exec mask operations pre RA
MCAsmBackend * createX86_32AsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
MCCodeEmitter * createX86MCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
Reg
All possible values of the reg field in the ModR/M byte.
int getDwarfRegNum(unsigned RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
MCAsmBackend * createX86_64AsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
static void RegisterCOFFStreamer(Target &T, Target::COFFStreamerCtorTy Fn)
MCStreamer * createX86WinCOFFStreamer(MCContext &C, std::unique_ptr< MCAsmBackend > &&AB, raw_pwrite_stream &OS, std::unique_ptr< MCCodeEmitter > &&CE, bool RelaxAll, bool IncrementalLinkerCompatible)
Construct an X86 Windows COFF machine code streamer which will generate PE/COFF format object files...
Context object for machine code objects.
Definition: MCContext.h:63
static MCRelocationInfo * createX86MCRelocationInfo(const Triple &TheTriple, MCContext &Ctx)
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Definition: Triple.h:283
void addInitialFrameState(const MCCFIInstruction &Inst)
Definition: MCAsmInfo.h:590
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:133
void LLVMInitializeX86TargetMC()
bool isWindowsItaniumEnvironment() const
Definition: Triple.h:536
bool isWindowsCoreCLREnvironment() const
Definition: Triple.h:532
MCRelocationInfo * createMCRelocationInfo(const Triple &TT, MCContext &Ctx)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.
unsigned const MachineRegisterInfo * MRI
static MCCFIInstruction createDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it...
Definition: MCDwarf.h:427
static bool is64Bit(const char *name)
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
MCTargetStreamer * createX86AsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, bool isVerboseAsm)
Implements X86-only directives for assembly emission.
Create MCExprs from relocations found in an object file.
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:596
static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target...
static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
MCSubtargetInfo * createX86MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Create a X86 MCSubtargetInfo instance.
unsigned getX86SubSuperRegisterOrZero(unsigned, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
void initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI)
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:725
static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.
EnvironmentType getEnvironment() const
getEnvironment - Get the parsed environment type of this triple.
Definition: Triple.h:301
unsigned getX86SubSuperRegister(unsigned, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.
Target - Wrapper for Target specific information.
bool isOSCygMing() const
Tests for either Cygwin or MinGW OS.
Definition: Triple.h:549
static MCAsmInfo * createX86MCAsmInfo(const MCRegisterInfo &MRI, const Triple &TheTriple)
static MCInstrInfo * createX86MCInstrInfo()
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:41
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
void mapLLVMRegToCVReg(unsigned LLVMReg, int CVReg)
static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)
RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target. ...
#define I(x, y, z)
Definition: MD5.cpp:58
Generic base class for all target subtargets.
Target & getTheX86_32Target()
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
RegisterMCAsmInfoFn - Helper template for registering a target assembly info implementation.
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
static void RegisterMCRelocationInfo(Target &T, Target::MCRelocationInfoCtorTy Fn)
RegisterMCRelocationInfo - Register an MCRelocationInfo implementation for the given target...
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
static MCInstrAnalysis * createX86MCInstrAnalysis(const MCInstrInfo *Info)
bool isWindowsMSVCEnvironment() const
Checks if the environment could be MSVC.
Definition: Triple.h:521
static MCInstPrinter * createX86MCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
Target & getTheX86_64Target()
void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg)
mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register number mapping.