LLVM  10.0.0svn
X86MCTargetDesc.h
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1 //===-- X86MCTargetDesc.h - X86 Target Descriptions -------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides X86 specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_X86_MCTARGETDESC_X86MCTARGETDESC_H
14 #define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86MCTARGETDESC_H
15 
16 #include "llvm/MC/MCRegister.h"
17 #include "llvm/MC/MCStreamer.h"
18 #include "llvm/Support/DataTypes.h"
19 #include <string>
20 
21 namespace llvm {
22 class MCAsmBackend;
23 class MCCodeEmitter;
24 class MCContext;
25 class MCInstrInfo;
26 class MCObjectTargetWriter;
27 class MCObjectWriter;
28 class MCRegisterInfo;
29 class MCSubtargetInfo;
30 class MCRelocationInfo;
31 class MCTargetOptions;
32 class Target;
33 class Triple;
34 class StringRef;
35 class raw_ostream;
36 class raw_pwrite_stream;
37 
38 /// Flavour of dwarf regnumbers
39 ///
40 namespace DWARFFlavour {
41  enum {
43  };
44 }
45 
46 /// Native X86 register numbers
47 ///
48 namespace N86 {
49  enum {
50  EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
51  };
52 }
53 
54 namespace X86_MC {
55 std::string ParseX86Triple(const Triple &TT);
56 
57 unsigned getDwarfRegFlavour(const Triple &TT, bool isEH);
58 
60 
61 
62 /// Returns true if this instruction has a LOCK prefix.
63 bool hasLockPrefix(const MCInst &MI);
64 
65 /// Create a X86 MCSubtargetInfo instance. This is exposed so Asm parser, etc.
66 /// do not need to go through TargetRegistry.
68  StringRef FS);
69 }
70 
72  const MCRegisterInfo &MRI,
73  MCContext &Ctx);
74 
76  const MCSubtargetInfo &STI,
77  const MCRegisterInfo &MRI,
78  const MCTargetOptions &Options);
80  const MCSubtargetInfo &STI,
81  const MCRegisterInfo &MRI,
82  const MCTargetOptions &Options);
83 
84 /// Implements X86-only directives for assembly emission.
87  MCInstPrinter *InstPrint,
88  bool isVerboseAsm);
89 
90 /// Implements X86-only directives for object files.
92  const MCSubtargetInfo &STI);
93 
94 /// Construct an X86 Windows COFF machine code streamer which will generate
95 /// PE/COFF format object files.
96 ///
97 /// Takes ownership of \p AB and \p CE.
99  std::unique_ptr<MCAsmBackend> &&AB,
100  std::unique_ptr<MCObjectWriter> &&OW,
101  std::unique_ptr<MCCodeEmitter> &&CE,
102  bool RelaxAll,
103  bool IncrementalLinkerCompatible);
104 
105 /// Construct an X86 Mach-O object writer.
106 std::unique_ptr<MCObjectTargetWriter>
107 createX86MachObjectWriter(bool Is64Bit, uint32_t CPUType, uint32_t CPUSubtype);
108 
109 /// Construct an X86 ELF object writer.
110 std::unique_ptr<MCObjectTargetWriter>
111 createX86ELFObjectWriter(bool IsELF64, uint8_t OSABI, uint16_t EMachine);
112 /// Construct an X86 Win COFF object writer.
113 std::unique_ptr<MCObjectTargetWriter>
114 createX86WinCOFFObjectWriter(bool Is64Bit);
115 
116 /// Returns the sub or super register of a specific X86 register.
117 /// e.g. getX86SubSuperRegister(X86::EAX, 16) returns X86::AX.
118 /// Aborts on error.
119 MCRegister getX86SubSuperRegister(MCRegister, unsigned, bool High=false);
120 
121 /// Returns the sub or super register of a specific X86 register.
122 /// Like getX86SubSuperRegister() but returns 0 on error.
124  bool High = false);
125 
126 } // End llvm namespace
127 
128 
129 // Defines symbolic names for X86 registers. This defines a mapping from
130 // register name to register number.
131 //
132 #define GET_REGINFO_ENUM
133 #include "X86GenRegisterInfo.inc"
134 
135 // Defines symbolic names for the X86 instructions.
136 //
137 #define GET_INSTRINFO_ENUM
138 #define GET_INSTRINFO_MC_HELPER_DECLS
139 #include "X86GenInstrInfo.inc"
140 
141 #define GET_SUBTARGETINFO_ENUM
142 #include "X86GenSubtargetInfo.inc"
143 
144 #endif
uint64_t CallInst * C
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:22
This class represents lattice values for constants.
Definition: AllocatorList.h:23
MCRegister getX86SubSuperRegisterOrZero(MCRegister, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
formatted_raw_ostream - A raw_ostream that wraps another one and keeps track of line and column posit...
MCTargetStreamer * createX86ObjectTargetStreamer(MCStreamer &OS, const MCSubtargetInfo &STI)
Implements X86-only directives for object files.
Target specific streamer interface.
Definition: MCStreamer.h:91
std::unique_ptr< MCObjectTargetWriter > createX86MachObjectWriter(bool Is64Bit, uint32_t CPUType, uint32_t CPUSubtype)
Construct an X86 Mach-O object writer.
unsigned getDwarfRegFlavour(const Triple &TT, bool isEH)
MCRegister getX86SubSuperRegister(MCRegister, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
uint64_t High
std::string ParseX86Triple(const Triple &TT)
MCAsmBackend * createX86_32AsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
MCCodeEmitter * createX86MCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
MCAsmBackend * createX86_64AsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Context object for machine code objects.
Definition: MCContext.h:65
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
std::unique_ptr< MCObjectTargetWriter > createX86ELFObjectWriter(bool IsELF64, uint8_t OSABI, uint16_t EMachine)
Construct an X86 ELF object writer.
std::unique_ptr< MCObjectTargetWriter > createX86WinCOFFObjectWriter(bool Is64Bit)
Construct an X86 Win COFF object writer.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Streaming machine code generation interface.
Definition: MCStreamer.h:196
unsigned const MachineRegisterInfo * MRI
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:23
MCStreamer * createX86WinCOFFStreamer(MCContext &C, std::unique_ptr< MCAsmBackend > &&AB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&CE, bool RelaxAll, bool IncrementalLinkerCompatible)
Construct an X86 Windows COFF machine code streamer which will generate PE/COFF format object files...
MCTargetStreamer * createX86AsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, bool isVerboseAsm)
Implements X86-only directives for assembly emission.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
MCSubtargetInfo * createX86MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Create a X86 MCSubtargetInfo instance.
void initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI)
Target - Wrapper for Target specific information.
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:39
Generic base class for all target subtargets.
bool hasLockPrefix(const MCInst &MI)
Returns true if this instruction has a LOCK prefix.
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:41
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48