21#define GET_TARGET_REGBANK_IMPL
22#include "X86GenRegisterBank.inc"
26#define GET_TARGET_REGBANK_INFO_IMPL
27#include "X86GenRegisterBankInfo.def"
34 assert(&X86::GPRRegBank == &RBGPR &&
"Incorrect RegBanks inizalization.");
39 "Subclass not added?");
41 "GPRs should hold up to 64-bit");
48 if (X86::GR8RegClass.hasSubClassEq(&RC) ||
49 X86::GR16RegClass.hasSubClassEq(&RC) ||
50 X86::GR32RegClass.hasSubClassEq(&RC) ||
51 X86::GR64RegClass.hasSubClassEq(&RC) ||
52 X86::LOW32_ADDR_ACCESSRegClass.hasSubClassEq(&RC) ||
53 X86::LOW32_ADDR_ACCESS_RBPRegClass.hasSubClassEq(&RC))
56 if (X86::FR32XRegClass.hasSubClassEq(&RC) ||
57 X86::FR64XRegClass.hasSubClassEq(&RC) ||
58 X86::VR128XRegClass.hasSubClassEq(&RC) ||
59 X86::VR256XRegClass.hasSubClassEq(&RC) ||
60 X86::VR512RegClass.hasSubClassEq(&RC))
63 if (X86::RFP80RegClass.hasSubClassEq(&RC) ||
64 X86::RFP32RegClass.hasSubClassEq(&RC) ||
65 X86::RFP64RegClass.hasSubClassEq(&RC))
71X86GenRegisterBankInfo::PartialMappingIdx
73 const LLT &Ty,
bool isFP) {
76 bool HasSSE1 = ST->hasSSE1();
77 bool HasSSE2 = ST->hasSSE2();
101 return HasSSE1 ? PMI_FP32 : PMI_PSR32;
103 return HasSSE2 ? PMI_FP64 : PMI_PSR64;
127void X86RegisterBankInfo::getInstrPartialMappingIdxs(
131 unsigned NumOperands =
MI.getNumOperands();
132 for (
unsigned Idx = 0;
Idx < NumOperands; ++
Idx) {
133 auto &MO =
MI.getOperand(
Idx);
134 if (!MO.isReg() || !MO.getReg())
135 OpRegBankIdx[
Idx] = PMI_None;
142bool X86RegisterBankInfo::getInstrValueMapping(
147 unsigned NumOperands =
MI.getNumOperands();
148 for (
unsigned Idx = 0;
Idx < NumOperands; ++
Idx) {
149 if (!
MI.getOperand(
Idx).isReg())
151 if (!
MI.getOperand(
Idx).getReg())
155 if (!Mapping->isValid())
158 OpdsMapping[
Idx] = Mapping;
164X86RegisterBankInfo::getSameOperandsMapping(
const MachineInstr &
MI,
169 unsigned NumOperands =
MI.getNumOperands();
170 LLT Ty =
MRI.getType(
MI.getOperand(0).getReg());
172 if (NumOperands != 3 || (Ty !=
MRI.getType(
MI.getOperand(1).getReg())) ||
173 (Ty !=
MRI.getType(
MI.getOperand(2).getReg())))
184 unsigned Opc =
MI.getOpcode();
195 case TargetOpcode::G_ADD:
196 case TargetOpcode::G_SUB:
197 case TargetOpcode::G_MUL:
198 return getSameOperandsMapping(
MI,
false);
199 case TargetOpcode::G_FADD:
200 case TargetOpcode::G_FSUB:
201 case TargetOpcode::G_FMUL:
202 case TargetOpcode::G_FDIV:
203 return getSameOperandsMapping(
MI,
true);
204 case TargetOpcode::G_SHL:
205 case TargetOpcode::G_LSHR:
206 case TargetOpcode::G_ASHR: {
207 unsigned NumOperands =
MI.getNumOperands();
208 LLT Ty =
MRI.getType(
MI.getOperand(0).getReg());
217 unsigned NumOperands =
MI.getNumOperands();
221 case TargetOpcode::G_FPEXT:
222 case TargetOpcode::G_FPTRUNC:
223 case TargetOpcode::G_FCONSTANT:
225 getInstrPartialMappingIdxs(
MI,
MRI,
true, OpRegBankIdx);
227 case TargetOpcode::G_SITOFP:
228 case TargetOpcode::G_FPTOSI: {
231 auto &Op0 =
MI.getOperand(0);
232 auto &Op1 =
MI.getOperand(1);
233 const LLT Ty0 =
MRI.getType(Op0.getReg());
234 const LLT Ty1 =
MRI.getType(Op1.getReg());
236 bool FirstArgIsFP = Opc == TargetOpcode::G_SITOFP;
237 bool SecondArgIsFP = Opc == TargetOpcode::G_FPTOSI;
242 case TargetOpcode::G_FCMP: {
243 LLT Ty1 =
MRI.getType(
MI.getOperand(2).getReg());
244 LLT Ty2 =
MRI.getType(
MI.getOperand(3).getReg());
247 "Mismatched operand sizes for G_FCMP");
251 assert((
Size == 32 ||
Size == 64) &&
"Unsupported size for G_FCMP");
254 OpRegBankIdx = {PMI_GPR8,
255 PMI_None, FpRegBank, FpRegBank};
258 case TargetOpcode::G_TRUNC:
259 case TargetOpcode::G_ANYEXT: {
260 auto &Op0 =
MI.getOperand(0);
261 auto &Op1 =
MI.getOperand(1);
262 const LLT Ty0 =
MRI.getType(Op0.getReg());
263 const LLT Ty1 =
MRI.getType(Op1.getReg());
270 Opc == TargetOpcode::G_ANYEXT;
272 getInstrPartialMappingIdxs(
MI,
MRI, isFPTrunc || isFPAnyExt,
277 getInstrPartialMappingIdxs(
MI,
MRI,
false, OpRegBankIdx);
283 if (!getInstrValueMapping(
MI, OpRegBankIdx, OpdsMapping))
303 switch (
MI.getOpcode()) {
304 case TargetOpcode::G_LOAD:
305 case TargetOpcode::G_STORE:
306 case TargetOpcode::G_IMPLICIT_DEF: {
312 unsigned NumOperands =
MI.getNumOperands();
316 getInstrPartialMappingIdxs(
MI,
MRI,
true, OpRegBankIdx);
320 if (!getInstrValueMapping(
MI, OpRegBankIdx, OpdsMapping))
unsigned const MachineRegisterInfo * MRI
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
unsigned const TargetRegisterInfo * TRI
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file declares the targeting of the RegisterBankInfo class for X86.
constexpr bool isScalar() const
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
constexpr bool isPointer() const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Helper class to build MachineInstr.
Representation of each machine instruction.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Helper class that represents how the value of an instruction may be mapped and what is the related co...
bool isValid() const
Check whether this object is valid.
Helper class used to get/create the virtual registers that will be used to replace the MachineOperand...
virtual InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const
Get the alternative mappings for MI.
const InstructionMapping & getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const
Method to get a uniquely generated InstructionMapping.
static void applyDefaultMapping(const OperandsMapper &OpdMapper)
Helper method to apply something that is like the default mapping.
const InstructionMapping & getInvalidInstructionMapping() const
Method to get a uniquely generated invalid InstructionMapping.
const RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
unsigned getMaximumSize(unsigned RegBankID) const
Get the maximum size in bits that fits in the given register bank.
TypeSize getSizeInBits(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Get the size in bits of Reg.
const ValueMapping * getOperandsMapping(Iterator Begin, Iterator End) const
Get the uniquely generated array of ValueMapping for the elements of between Begin and End.
static const unsigned DefaultMappingID
Identifier used when the related instruction mapping instance is generated by target independent code...
const InstructionMapping & getInstrMappingImpl(const MachineInstr &MI) const
Try to get the mapping of MI.
This class implements the register bank concept.
bool covers(const TargetRegisterClass &RC) const
Check whether this register bank covers RC.
unsigned getID() const
Get the identifier of this register bank.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
static PartialMappingIdx getPartialMappingIdx(const MachineInstr &MI, const LLT &Ty, bool isFP)
static const RegisterBankInfo::ValueMapping * getValueMapping(PartialMappingIdx Idx, unsigned NumOperands)
X86RegisterBankInfo(const TargetRegisterInfo &TRI)
InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const override
Get the alternative mappings for MI.
const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC, LLT) const override
Get a register bank that covers RC.
const InstructionMapping & getInstrMapping(const MachineInstr &MI) const override
Get the mapping of the different operands of MI on the register bank.
void applyMappingImpl(MachineIRBuilder &Builder, const OperandsMapper &OpdMapper) const override
See RegisterBankInfo::applyMapping.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.