LLVM  7.0.0svn
X86Subtarget.h
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1 //===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file declares the X86 specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_X86_X86SUBTARGET_H
15 #define LLVM_LIB_TARGET_X86_X86SUBTARGET_H
16 
17 #include "X86FrameLowering.h"
18 #include "X86ISelLowering.h"
19 #include "X86InstrInfo.h"
20 #include "X86SelectionDAGInfo.h"
21 #include "llvm/ADT/StringRef.h"
22 #include "llvm/ADT/Triple.h"
28 #include "llvm/IR/CallingConv.h"
31 #include <memory>
32 
33 #define GET_SUBTARGETINFO_HEADER
34 #include "X86GenSubtargetInfo.inc"
35 
36 namespace llvm {
37 
38 class GlobalValue;
39 
40 /// The X86 backend supports a number of different styles of PIC.
41 ///
42 namespace PICStyles {
43 
44 enum Style {
45  StubPIC, // Used on i386-darwin in pic mode.
46  GOT, // Used on 32 bit elf on when in pic mode.
47  RIPRel, // Used on X86-64 when in pic mode.
48  None // Set when not in pic mode.
49 };
50 
51 } // end namespace PICStyles
52 
53 class X86Subtarget final : public X86GenSubtargetInfo {
54 public:
67  };
68 
69 protected:
70  enum X86SSEEnum {
71  NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
72  };
73 
74  enum X863DNowEnum {
75  NoThreeDNow, MMX, ThreeDNow, ThreeDNowA
76  };
77 
78  /// X86 processor family: Intel Atom, and others
80 
81  /// Which PIC style to use
83 
84  const TargetMachine &TM;
85 
86  /// SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
88 
89  /// MMX, 3DNow, 3DNow Athlon, or none supported.
91 
92  /// True if the processor supports X87 instructions.
93  bool HasX87;
94 
95  /// True if this processor has NOPL instruction
96  /// (generally pentium pro+).
97  bool HasNOPL;
98 
99  /// True if this processor has conditional move instructions
100  /// (generally pentium pro+).
101  bool HasCMov;
102 
103  /// True if the processor supports X86-64 instructions.
104  bool HasX86_64;
105 
106  /// True if the processor supports POPCNT.
107  bool HasPOPCNT;
108 
109  /// True if the processor supports SSE4A instructions.
110  bool HasSSE4A;
111 
112  /// Target has AES instructions
113  bool HasAES;
114  bool HasVAES;
115 
116  /// Target has FXSAVE/FXRESTOR instructions
117  bool HasFXSR;
118 
119  /// Target has XSAVE instructions
120  bool HasXSAVE;
121 
122  /// Target has XSAVEOPT instructions
124 
125  /// Target has XSAVEC instructions
126  bool HasXSAVEC;
127 
128  /// Target has XSAVES instructions
129  bool HasXSAVES;
130 
131  /// Target has carry-less multiplication
132  bool HasPCLMUL;
134 
135  /// Target has Galois Field Arithmetic instructions
136  bool HasGFNI;
137 
138  /// Target has 3-operand fused multiply-add
139  bool HasFMA;
140 
141  /// Target has 4-operand fused multiply-add
142  bool HasFMA4;
143 
144  /// Target has XOP instructions
145  bool HasXOP;
146 
147  /// Target has TBM instructions.
148  bool HasTBM;
149 
150  /// Target has LWP instructions
151  bool HasLWP;
152 
153  /// True if the processor has the MOVBE instruction.
154  bool HasMOVBE;
155 
156  /// True if the processor has the RDRAND instruction.
157  bool HasRDRAND;
158 
159  /// Processor has 16-bit floating point conversion instructions.
160  bool HasF16C;
161 
162  /// Processor has FS/GS base insturctions.
164 
165  /// Processor has LZCNT instruction.
166  bool HasLZCNT;
167 
168  /// Processor has BMI1 instructions.
169  bool HasBMI;
170 
171  /// Processor has BMI2 instructions.
172  bool HasBMI2;
173 
174  /// Processor has VBMI instructions.
175  bool HasVBMI;
176 
177  /// Processor has VBMI2 instructions.
178  bool HasVBMI2;
179 
180  /// Processor has Integer Fused Multiply Add
181  bool HasIFMA;
182 
183  /// Processor has RTM instructions.
184  bool HasRTM;
185 
186  /// Processor has ADX instructions.
187  bool HasADX;
188 
189  /// Processor has SHA instructions.
190  bool HasSHA;
191 
192  /// Processor has PRFCHW instructions.
193  bool HasPRFCHW;
194 
195  /// Processor has RDSEED instructions.
196  bool HasRDSEED;
197 
198  /// Processor has LAHF/SAHF instructions.
200 
201  /// Processor has MONITORX/MWAITX instructions.
202  bool HasMWAITX;
203 
204  /// Processor has Cache Line Zero instruction
205  bool HasCLZERO;
206 
207  /// Processor has Prefetch with intent to Write instruction
209 
210  /// True if SHLD instructions are slow.
212 
213  /// True if the PMULLD instruction is slow compared to PMULLW/PMULHW and
214  // PMULUDQ.
216 
217  /// True if unaligned memory accesses of 16-bytes are slow.
219 
220  /// True if unaligned memory accesses of 32-bytes are slow.
222 
223  /// True if SSE operations can have unaligned memory operands.
224  /// This may require setting a configuration bit in the processor.
226 
227  /// True if this processor has the CMPXCHG16B instruction;
228  /// this is true for most x86-64 chips, but not the first AMD chips.
230 
231  /// True if the LEA instruction should be used for adjusting
232  /// the stack pointer. This is an optimization for Intel Atom processors.
234 
235  /// True if its preferable to combine to a single shuffle using a variable
236  /// mask over multiple fixed shuffles.
238 
239  /// True if there is no performance penalty to writing only the lower parts
240  /// of a YMM or ZMM register without clearing the upper part.
242 
243  /// True if gather is reasonably fast. This is true for Skylake client and
244  /// all AVX-512 CPUs.
246 
247  /// True if hardware SQRTSS instruction is at least as fast (latency) as
248  /// RSQRTSS followed by a Newton-Raphson iteration.
250 
251  /// True if hardware SQRTPS/VSQRTPS instructions are at least as fast
252  /// (throughput) as RSQRTPS/VRSQRTPS followed by a Newton-Raphson iteration.
254 
255  /// True if 8-bit divisions are significantly faster than
256  /// 32-bit divisions and should be used when possible.
258 
259  /// True if 32-bit divides are significantly faster than
260  /// 64-bit divisions and should be used when possible.
262 
263  /// True if LZCNT instruction is fast.
265 
266  /// True if SHLD based rotate is fast.
268 
269  /// True if the processor supports macrofusion.
271 
272  /// True if the processor has enhanced REP MOVSB/STOSB.
273  bool HasERMSB;
274 
275  /// True if the short functions should be padded to prevent
276  /// a stall when returning too early.
278 
279  /// True if two memory operand instructions should use a temporary register
280  /// instead.
282 
283  /// True if the LEA instruction inputs have to be ready at address generation
284  /// (AG) time.
285  bool LEAUsesAG;
286 
287  /// True if the LEA instruction with certain arguments is slow
288  bool SlowLEA;
289 
290  /// True if the LEA instruction has all three source operands: base, index,
291  /// and offset or if the LEA instruction uses base and index registers where
292  /// the base is EBP, RBP,or R13
294 
295  /// True if INC and DEC instructions are slow when writing to flags
297 
298  /// Processor has AVX-512 PreFetch Instructions
299  bool HasPFI;
300 
301  /// Processor has AVX-512 Exponential and Reciprocal Instructions
302  bool HasERI;
303 
304  /// Processor has AVX-512 Conflict Detection Instructions
305  bool HasCDI;
306 
307  /// Processor has AVX-512 population count Instructions
309 
310  /// Processor has AVX-512 Doubleword and Quadword instructions
311  bool HasDQI;
312 
313  /// Processor has AVX-512 Byte and Word instructions
314  bool HasBWI;
315 
316  /// Processor has AVX-512 Vector Length eXtenstions
317  bool HasVLX;
318 
319  /// Processor has PKU extenstions
320  bool HasPKU;
321 
322  /// Processor has AVX-512 Vector Neural Network Instructions
323  bool HasVNNI;
324 
325  /// Processor has AVX-512 Bit Algorithms instructions
326  bool HasBITALG;
327 
328  /// Processor supports MPX - Memory Protection Extensions
329  bool HasMPX;
330 
331  /// Processor supports CET SHSTK - Control-Flow Enforcement Technology
332  /// using Shadow Stack
333  bool HasSHSTK;
334 
335  /// Processor supports CET IBT - Control-Flow Enforcement Technology
336  /// using Indirect Branch Tracking
337  bool HasIBT;
338 
339  /// Processor has Software Guard Extensions
340  bool HasSGX;
341 
342  /// Processor supports Flush Cache Line instruction
344 
345  /// Processor supports Cache Line Write Back instruction
346  bool HasCLWB;
347 
348  /// Use software floating point for code generation.
350 
351  /// The minimum alignment known to hold of the stack frame on
352  /// entry to the function and which must be maintained by every function.
353  unsigned stackAlignment;
354 
355  /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
356  ///
358 
359  /// What processor and OS we're targeting.
361 
362  /// Instruction itineraries for scheduling
364 
365  /// GlobalISel related APIs.
366  std::unique_ptr<CallLowering> CallLoweringInfo;
367  std::unique_ptr<LegalizerInfo> Legalizer;
368  std::unique_ptr<RegisterBankInfo> RegBankInfo;
369  std::unique_ptr<InstructionSelector> InstSelector;
370 
371 private:
372  /// Override the stack alignment.
373  unsigned StackAlignOverride;
374 
375  /// True if compiling for 64-bit, false for 16-bit or 32-bit.
376  bool In64BitMode;
377 
378  /// True if compiling for 32-bit, false for 16-bit or 64-bit.
379  bool In32BitMode;
380 
381  /// True if compiling for 16-bit, false for 32-bit or 64-bit.
382  bool In16BitMode;
383 
384  /// Contains the Overhead of gather\scatter instructions
385  int GatherOverhead;
386  int ScatterOverhead;
387 
388  X86SelectionDAGInfo TSInfo;
389  // Ordering here is important. X86InstrInfo initializes X86RegisterInfo which
390  // X86TargetLowering needs.
391  X86InstrInfo InstrInfo;
392  X86TargetLowering TLInfo;
393  X86FrameLowering FrameLowering;
394 
395 public:
396  /// This constructor initializes the data members to match that
397  /// of the specified triple.
398  ///
399  X86Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
400  const X86TargetMachine &TM, unsigned StackAlignOverride);
401 
402  const X86TargetLowering *getTargetLowering() const override {
403  return &TLInfo;
404  }
405 
406  const X86InstrInfo *getInstrInfo() const override { return &InstrInfo; }
407 
408  const X86FrameLowering *getFrameLowering() const override {
409  return &FrameLowering;
410  }
411 
412  const X86SelectionDAGInfo *getSelectionDAGInfo() const override {
413  return &TSInfo;
414  }
415 
416  const X86RegisterInfo *getRegisterInfo() const override {
417  return &getInstrInfo()->getRegisterInfo();
418  }
419 
420  /// Returns the minimum alignment known to hold of the
421  /// stack frame on entry to the function and which must be maintained by every
422  /// function for this subtarget.
423  unsigned getStackAlignment() const { return stackAlignment; }
424 
425  /// Returns the maximum memset / memcpy size
426  /// that still makes it profitable to inline the call.
427  unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
428 
429  /// ParseSubtargetFeatures - Parses features string setting specified
430  /// subtarget options. Definition of function is auto generated by tblgen.
431  void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
432 
433  /// Methods used by Global ISel
434  const CallLowering *getCallLowering() const override;
435  const InstructionSelector *getInstructionSelector() const override;
436  const LegalizerInfo *getLegalizerInfo() const override;
437  const RegisterBankInfo *getRegBankInfo() const override;
438 
439 private:
440  /// Initialize the full set of dependencies so we can use an initializer
441  /// list for X86Subtarget.
442  X86Subtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
443  void initializeEnvironment();
444  void initSubtargetFeatures(StringRef CPU, StringRef FS);
445 
446 public:
447  /// Is this x86_64? (disregarding specific ABI / programming model)
448  bool is64Bit() const {
449  return In64BitMode;
450  }
451 
452  bool is32Bit() const {
453  return In32BitMode;
454  }
455 
456  bool is16Bit() const {
457  return In16BitMode;
458  }
459 
460  /// Is this x86_64 with the ILP32 programming model (x32 ABI)?
461  bool isTarget64BitILP32() const {
462  return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32 ||
463  TargetTriple.isOSNaCl());
464  }
465 
466  /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
467  bool isTarget64BitLP64() const {
468  return In64BitMode && (TargetTriple.getEnvironment() != Triple::GNUX32 &&
469  !TargetTriple.isOSNaCl());
470  }
471 
472  PICStyles::Style getPICStyle() const { return PICStyle; }
473  void setPICStyle(PICStyles::Style Style) { PICStyle = Style; }
474 
475  bool hasX87() const { return HasX87; }
476  bool hasNOPL() const { return HasNOPL; }
477  bool hasCMov() const { return HasCMov; }
478  bool hasSSE1() const { return X86SSELevel >= SSE1; }
479  bool hasSSE2() const { return X86SSELevel >= SSE2; }
480  bool hasSSE3() const { return X86SSELevel >= SSE3; }
481  bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
482  bool hasSSE41() const { return X86SSELevel >= SSE41; }
483  bool hasSSE42() const { return X86SSELevel >= SSE42; }
484  bool hasAVX() const { return X86SSELevel >= AVX; }
485  bool hasAVX2() const { return X86SSELevel >= AVX2; }
486  bool hasAVX512() const { return X86SSELevel >= AVX512F; }
487  bool hasFp256() const { return hasAVX(); }
488  bool hasInt256() const { return hasAVX2(); }
489  bool hasSSE4A() const { return HasSSE4A; }
490  bool hasMMX() const { return X863DNowLevel >= MMX; }
491  bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
492  bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
493  bool hasPOPCNT() const { return HasPOPCNT; }
494  bool hasAES() const { return HasAES; }
495  bool hasVAES() const { return HasVAES; }
496  bool hasFXSR() const { return HasFXSR; }
497  bool hasXSAVE() const { return HasXSAVE; }
498  bool hasXSAVEOPT() const { return HasXSAVEOPT; }
499  bool hasXSAVEC() const { return HasXSAVEC; }
500  bool hasXSAVES() const { return HasXSAVES; }
501  bool hasPCLMUL() const { return HasPCLMUL; }
502  bool hasVPCLMULQDQ() const { return HasVPCLMULQDQ; }
503  bool hasGFNI() const { return HasGFNI; }
504  // Prefer FMA4 to FMA - its better for commutation/memory folding and
505  // has equal or better performance on all supported targets.
506  bool hasFMA() const { return HasFMA; }
507  bool hasFMA4() const { return HasFMA4; }
508  bool hasAnyFMA() const { return hasFMA() || hasFMA4(); }
509  bool hasXOP() const { return HasXOP; }
510  bool hasTBM() const { return HasTBM; }
511  bool hasLWP() const { return HasLWP; }
512  bool hasMOVBE() const { return HasMOVBE; }
513  bool hasRDRAND() const { return HasRDRAND; }
514  bool hasF16C() const { return HasF16C; }
515  bool hasFSGSBase() const { return HasFSGSBase; }
516  bool hasLZCNT() const { return HasLZCNT; }
517  bool hasBMI() const { return HasBMI; }
518  bool hasBMI2() const { return HasBMI2; }
519  bool hasVBMI() const { return HasVBMI; }
520  bool hasVBMI2() const { return HasVBMI2; }
521  bool hasIFMA() const { return HasIFMA; }
522  bool hasRTM() const { return HasRTM; }
523  bool hasADX() const { return HasADX; }
524  bool hasSHA() const { return HasSHA; }
525  bool hasPRFCHW() const { return HasPRFCHW || HasPREFETCHWT1; }
526  bool hasPREFETCHWT1() const { return HasPREFETCHWT1; }
527  bool hasSSEPrefetch() const {
528  // We implicitly enable these when we have a write prefix supporting cache
529  // level OR if we have prfchw, but don't already have a read prefetch from
530  // 3dnow.
531  return hasSSE1() || (hasPRFCHW() && !has3DNow()) || hasPREFETCHWT1();
532  }
533  bool hasRDSEED() const { return HasRDSEED; }
534  bool hasLAHFSAHF() const { return HasLAHFSAHF; }
535  bool hasMWAITX() const { return HasMWAITX; }
536  bool hasCLZERO() const { return HasCLZERO; }
537  bool isSHLDSlow() const { return IsSHLDSlow; }
538  bool isPMULLDSlow() const { return IsPMULLDSlow; }
539  bool isUnalignedMem16Slow() const { return IsUAMem16Slow; }
540  bool isUnalignedMem32Slow() const { return IsUAMem32Slow; }
541  int getGatherOverhead() const { return GatherOverhead; }
542  int getScatterOverhead() const { return ScatterOverhead; }
543  bool hasSSEUnalignedMem() const { return HasSSEUnalignedMem; }
544  bool hasCmpxchg16b() const { return HasCmpxchg16b; }
545  bool useLeaForSP() const { return UseLeaForSP; }
546  bool hasFastVariableShuffle() const {
547  return HasFastVariableShuffle;
548  }
550  return HasFastPartialYMMorZMMWrite;
551  }
552  bool hasFastGather() const { return HasFastGather; }
553  bool hasFastScalarFSQRT() const { return HasFastScalarFSQRT; }
554  bool hasFastVectorFSQRT() const { return HasFastVectorFSQRT; }
555  bool hasFastLZCNT() const { return HasFastLZCNT; }
556  bool hasFastSHLDRotate() const { return HasFastSHLDRotate; }
557  bool hasMacroFusion() const { return HasMacroFusion; }
558  bool hasERMSB() const { return HasERMSB; }
559  bool hasSlowDivide32() const { return HasSlowDivide32; }
560  bool hasSlowDivide64() const { return HasSlowDivide64; }
561  bool padShortFunctions() const { return PadShortFunctions; }
562  bool slowTwoMemOps() const { return SlowTwoMemOps; }
563  bool LEAusesAG() const { return LEAUsesAG; }
564  bool slowLEA() const { return SlowLEA; }
565  bool slow3OpsLEA() const { return Slow3OpsLEA; }
566  bool slowIncDec() const { return SlowIncDec; }
567  bool hasCDI() const { return HasCDI; }
568  bool hasVPOPCNTDQ() const { return HasVPOPCNTDQ; }
569  bool hasPFI() const { return HasPFI; }
570  bool hasERI() const { return HasERI; }
571  bool hasDQI() const { return HasDQI; }
572  bool hasBWI() const { return HasBWI; }
573  bool hasVLX() const { return HasVLX; }
574  bool hasPKU() const { return HasPKU; }
575  bool hasVNNI() const { return HasVNNI; }
576  bool hasBITALG() const { return HasBITALG; }
577  bool hasMPX() const { return HasMPX; }
578  bool hasSHSTK() const { return HasSHSTK; }
579  bool hasIBT() const { return HasIBT; }
580  bool hasCLFLUSHOPT() const { return HasCLFLUSHOPT; }
581  bool hasCLWB() const { return HasCLWB; }
582 
583  bool isXRaySupported() const override { return is64Bit(); }
584 
585  X86ProcFamilyEnum getProcFamily() const { return X86ProcFamily; }
586 
587  /// TODO: to be removed later and replaced with suitable properties
588  bool isAtom() const { return X86ProcFamily == IntelAtom; }
589  bool isSLM() const { return X86ProcFamily == IntelSLM; }
590  bool useSoftFloat() const { return UseSoftFloat; }
591 
592  /// Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
593  /// no-sse2). There isn't any reason to disable it if the target processor
594  /// supports it.
595  bool hasMFence() const { return hasSSE2() || is64Bit(); }
596 
597  const Triple &getTargetTriple() const { return TargetTriple; }
598 
599  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
600  bool isTargetFreeBSD() const { return TargetTriple.isOSFreeBSD(); }
601  bool isTargetDragonFly() const { return TargetTriple.isOSDragonFly(); }
602  bool isTargetSolaris() const { return TargetTriple.isOSSolaris(); }
603  bool isTargetPS4() const { return TargetTriple.isPS4CPU(); }
604 
605  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
606  bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
607  bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
608 
609  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
610  bool isTargetKFreeBSD() const { return TargetTriple.isOSKFreeBSD(); }
611  bool isTargetGlibc() const { return TargetTriple.isOSGlibc(); }
612  bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
613  bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
614  bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
615  bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
616  bool isTargetMCU() const { return TargetTriple.isOSIAMCU(); }
617  bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
618 
619  bool isTargetWindowsMSVC() const {
620  return TargetTriple.isWindowsMSVCEnvironment();
621  }
622 
624  return TargetTriple.isKnownWindowsMSVCEnvironment();
625  }
626 
627  bool isTargetWindowsCoreCLR() const {
628  return TargetTriple.isWindowsCoreCLREnvironment();
629  }
630 
631  bool isTargetWindowsCygwin() const {
632  return TargetTriple.isWindowsCygwinEnvironment();
633  }
634 
635  bool isTargetWindowsGNU() const {
636  return TargetTriple.isWindowsGNUEnvironment();
637  }
638 
639  bool isTargetWindowsItanium() const {
640  return TargetTriple.isWindowsItaniumEnvironment();
641  }
642 
643  bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
644 
645  bool isOSWindows() const { return TargetTriple.isOSWindows(); }
646 
647  bool isTargetWin64() const { return In64BitMode && isOSWindows(); }
648 
649  bool isTargetWin32() const { return !In64BitMode && isOSWindows(); }
650 
651  bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
652  bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
653 
654  bool isPICStyleStubPIC() const {
655  return PICStyle == PICStyles::StubPIC;
656  }
657 
658  bool isPositionIndependent() const { return TM.isPositionIndependent(); }
659 
661  switch (CC) {
662  // On Win64, all these conventions just use the default convention.
663  case CallingConv::C:
664  case CallingConv::Fast:
665  case CallingConv::Swift:
671  return isTargetWin64();
672  // This convention allows using the Win64 convention on other targets.
673  case CallingConv::Win64:
674  return true;
675  // This convention allows using the SysV convention on Windows targets.
677  return false;
678  // Otherwise, who knows what this is.
679  default:
680  return false;
681  }
682  }
683 
684  /// Classify a global variable reference for the current subtarget according
685  /// to how we should reference it in a non-pcrel context.
686  unsigned char classifyLocalReference(const GlobalValue *GV) const;
687 
688  unsigned char classifyGlobalReference(const GlobalValue *GV,
689  const Module &M) const;
690  unsigned char classifyGlobalReference(const GlobalValue *GV) const;
691 
692  /// Classify a global function reference for the current subtarget.
693  unsigned char classifyGlobalFunctionReference(const GlobalValue *GV,
694  const Module &M) const;
695  unsigned char classifyGlobalFunctionReference(const GlobalValue *GV) const;
696 
697  /// Classify a blockaddress reference for the current subtarget according to
698  /// how we should reference it in a non-pcrel context.
699  unsigned char classifyBlockAddressReference() const;
700 
701  /// Return true if the subtarget allows calls to immediate address.
702  bool isLegalToCallImmediateAddr() const;
703 
704  /// Enable the MachineScheduler pass for all X86 subtargets.
705  bool enableMachineScheduler() const override { return true; }
706 
707  // TODO: Update the regression tests and return true.
708  bool supportPrintSchedInfo() const override { return false; }
709 
710  bool enableEarlyIfConversion() const override;
711 
712  /// Return the instruction itineraries based on the subtarget selection.
713  const InstrItineraryData *getInstrItineraryData() const override {
714  return &InstrItins;
715  }
716 
717  AntiDepBreakMode getAntiDepBreakMode() const override {
718  return TargetSubtargetInfo::ANTIDEP_CRITICAL;
719  }
720 
721  bool enableAdvancedRASplitCost() const override { return true; }
722 };
723 
724 } // end namespace llvm
725 
726 #endif // LLVM_LIB_TARGET_X86_X86SUBTARGET_H
bool hasAVX() const
Definition: X86Subtarget.h:484
bool HasPRFCHW
Processor has PRFCHW instructions.
Definition: X86Subtarget.h:193
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:470
bool isTargetPS4() const
Definition: X86Subtarget.h:603
bool HasFXSR
Target has FXSAVE/FXRESTOR instructions.
Definition: X86Subtarget.h:117
bool HasTBM
Target has TBM instructions.
Definition: X86Subtarget.h:148
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:448
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:43
bool HasBMI2
Processor has BMI2 instructions.
Definition: X86Subtarget.h:172
bool hasSHA() const
Definition: X86Subtarget.h:524
bool supportPrintSchedInfo() const override
Definition: X86Subtarget.h:708
bool HasSGX
Processor has Software Guard Extensions.
Definition: X86Subtarget.h:340
The C convention as implemented on Windows/x86-64 and AArch64.
Definition: CallingConv.h:154
bool hasSSE41() const
Definition: X86Subtarget.h:482
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool hasSSEPrefetch() const
Definition: X86Subtarget.h:527
Intel_OCL_BI - Calling conventions for Intel OpenCL built-ins.
Definition: CallingConv.h:140
bool isOSWindows() const
Definition: X86Subtarget.h:645
bool hasPOPCNT() const
Definition: X86Subtarget.h:493
bool hasAVX2() const
Definition: X86Subtarget.h:485
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:63
bool hasFMA() const
Definition: X86Subtarget.h:506
bool HasLAHFSAHF
Processor has LAHF/SAHF instructions.
Definition: X86Subtarget.h:199
bool hasSlowDivide64() const
Definition: X86Subtarget.h:560
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:588
const X86InstrInfo * getInstrInfo() const override
Definition: X86Subtarget.h:406
bool HasCDI
Processor has AVX-512 Conflict Detection Instructions.
Definition: X86Subtarget.h:305
bool HasAES
Target has AES instructions.
Definition: X86Subtarget.h:113
bool hasCLWB() const
Definition: X86Subtarget.h:581
bool slowLEA() const
Definition: X86Subtarget.h:564
const X86FrameLowering * getFrameLowering() const override
Definition: X86Subtarget.h:408
void setPICStyle(PICStyles::Style Style)
Definition: X86Subtarget.h:473
const TargetMachine & TM
Definition: X86Subtarget.h:84
bool HasERI
Processor has AVX-512 Exponential and Reciprocal Instructions.
Definition: X86Subtarget.h:302
bool enableMachineScheduler() const override
Enable the MachineScheduler pass for all X86 subtargets.
Definition: X86Subtarget.h:705
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
Definition: Triple.h:567
unsigned MaxInlineSizeThreshold
Max.
Definition: X86Subtarget.h:357
bool hasVBMI2() const
Definition: X86Subtarget.h:520
bool HasERMSB
True if the processor has enhanced REP MOVSB/STOSB.
Definition: X86Subtarget.h:273
bool LEAUsesAG
True if the LEA instruction inputs have to be ready at address generation (AG) time.
Definition: X86Subtarget.h:285
bool HasVPOPCNTDQ
Processor has AVX-512 population count Instructions.
Definition: X86Subtarget.h:308
bool HasFastGather
True if gather is reasonably fast.
Definition: X86Subtarget.h:245
bool HasFastScalarFSQRT
True if hardware SQRTSS instruction is at least as fast (latency) as RSQRTSS followed by a Newton-Rap...
Definition: X86Subtarget.h:249
bool hasCLZERO() const
Definition: X86Subtarget.h:536
bool IsUAMem32Slow
True if unaligned memory accesses of 32-bytes are slow.
Definition: X86Subtarget.h:221
bool HasLWP
Target has LWP instructions.
Definition: X86Subtarget.h:151
bool has3DNowA() const
Definition: X86Subtarget.h:492
bool HasPREFETCHWT1
Processor has Prefetch with intent to Write instruction.
Definition: X86Subtarget.h:208
bool isOSFuchsia() const
Definition: Triple.h:490
bool isTargetNaCl64() const
Definition: X86Subtarget.h:615
bool IsPMULLDSlow
True if the PMULLD instruction is slow compared to PMULLW/PMULHW and.
Definition: X86Subtarget.h:215
bool isWindowsCygwinEnvironment() const
Definition: Triple.h:542
bool isTargetKnownWindowsMSVC() const
Definition: X86Subtarget.h:623
bool HasRDRAND
True if the processor has the RDRAND instruction.
Definition: X86Subtarget.h:157
bool slowTwoMemOps() const
Definition: X86Subtarget.h:562
bool hasSHSTK() const
Definition: X86Subtarget.h:578
bool isTargetWindowsMSVC() const
Definition: X86Subtarget.h:619
bool HasFastPartialYMMorZMMWrite
True if there is no performance penalty to writing only the lower parts of a YMM or ZMM register with...
Definition: X86Subtarget.h:241
bool isTargetMachO() const
Definition: X86Subtarget.h:607
int getGatherOverhead() const
Definition: X86Subtarget.h:541
bool HasCLWB
Processor supports Cache Line Write Back instruction.
Definition: X86Subtarget.h:346
bool HasFMA
Target has 3-operand fused multiply-add.
Definition: X86Subtarget.h:139
bool hasXSAVE() const
Definition: X86Subtarget.h:497
bool isUnalignedMem32Slow() const
Definition: X86Subtarget.h:540
bool isPICStyleStubPIC() const
Definition: X86Subtarget.h:654
bool hasVPOPCNTDQ() const
Definition: X86Subtarget.h:568
bool HasFastVectorFSQRT
True if hardware SQRTPS/VSQRTPS instructions are at least as fast (throughput) as RSQRTPS/VRSQRTPS fo...
Definition: X86Subtarget.h:253
bool hasPREFETCHWT1() const
Definition: X86Subtarget.h:526
Holds all the information related to register banks.
bool hasLWP() const
Definition: X86Subtarget.h:511
bool HasGFNI
Target has Galois Field Arithmetic instructions.
Definition: X86Subtarget.h:136
bool isPICStyleRIPRel() const
Definition: X86Subtarget.h:652
bool HasVBMI2
Processor has VBMI2 instructions.
Definition: X86Subtarget.h:178
const InstrItineraryData * getInstrItineraryData() const override
Return the instruction itineraries based on the subtarget selection.
Definition: X86Subtarget.h:713
bool hasFMA4() const
Definition: X86Subtarget.h:507
bool padShortFunctions() const
Definition: X86Subtarget.h:561
bool isTargetSolaris() const
Definition: X86Subtarget.h:602
bool HasCLFLUSHOPT
Processor supports Flush Cache Line instruction.
Definition: X86Subtarget.h:343
bool hasAES() const
Definition: X86Subtarget.h:494
bool HasPOPCNT
True if the processor supports POPCNT.
Definition: X86Subtarget.h:107
bool HasPKU
Processor has PKU extenstions.
Definition: X86Subtarget.h:320
bool isTarget64BitLP64() const
Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
Definition: X86Subtarget.h:467
bool isKnownWindowsMSVCEnvironment() const
Checks if the environment is MSVC.
Definition: Triple.h:530
bool hasPKU() const
Definition: X86Subtarget.h:574
bool HasBITALG
Processor has AVX-512 Bit Algorithms instructions.
Definition: X86Subtarget.h:326
bool is32Bit() const
Definition: X86Subtarget.h:452
bool hasCmpxchg16b() const
Definition: X86Subtarget.h:544
bool HasSlowDivide32
True if 8-bit divisions are significantly faster than 32-bit divisions and should be used when possib...
Definition: X86Subtarget.h:257
bool hasFp256() const
Definition: X86Subtarget.h:487
bool hasFastLZCNT() const
Definition: X86Subtarget.h:555
bool HasSHSTK
Processor supports CET SHSTK - Control-Flow Enforcement Technology using Shadow Stack.
Definition: X86Subtarget.h:333
bool isOSSolaris() const
Definition: Triple.h:496
bool hasVLX() const
Definition: X86Subtarget.h:573
bool slow3OpsLEA() const
Definition: X86Subtarget.h:565
bool HasPFI
Processor has AVX-512 PreFetch Instructions.
Definition: X86Subtarget.h:299
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
Definition: X86Subtarget.h:366
bool hasFastSHLDRotate() const
Definition: X86Subtarget.h:556
bool isTargetNaCl() const
Definition: X86Subtarget.h:613
bool hasNOPL() const
Definition: X86Subtarget.h:476
bool HasIFMA
Processor has Integer Fused Multiply Add.
Definition: X86Subtarget.h:181
bool HasCmpxchg16b
True if this processor has the CMPXCHG16B instruction; this is true for most x86-64 chips...
Definition: X86Subtarget.h:229
bool isTargetCygMing() const
Definition: X86Subtarget.h:643
bool HasX87
True if the processor supports X87 instructions.
Definition: X86Subtarget.h:93
bool hasMPX() const
Definition: X86Subtarget.h:577
Itinerary data supplied by a subtarget to be used by a target.
bool isWindowsItaniumEnvironment() const
Definition: Triple.h:538
bool UseLeaForSP
True if the LEA instruction should be used for adjusting the stack pointer.
Definition: X86Subtarget.h:233
bool isWindowsGNUEnvironment() const
Definition: Triple.h:546
bool hasFSGSBase() const
Definition: X86Subtarget.h:515
X863DNowEnum X863DNowLevel
MMX, 3DNow, 3DNow Athlon, or none supported.
Definition: X86Subtarget.h:90
bool hasFastVariableShuffle() const
Definition: X86Subtarget.h:546
bool hasDQI() const
Definition: X86Subtarget.h:571
bool HasSSE4A
True if the processor supports SSE4A instructions.
Definition: X86Subtarget.h:110
bool isWindowsCoreCLREnvironment() const
Definition: Triple.h:534
bool HasLZCNT
Processor has LZCNT instruction.
Definition: X86Subtarget.h:166
bool HasF16C
Processor has 16-bit floating point conversion instructions.
Definition: X86Subtarget.h:160
bool SlowIncDec
True if INC and DEC instructions are slow when writing to flags.
Definition: X86Subtarget.h:296
bool isOSDragonFly() const
Definition: Triple.h:494
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:562
const X86TargetLowering * getTargetLowering() const override
Definition: X86Subtarget.h:402
bool hasADX() const
Definition: X86Subtarget.h:523
bool isSLM() const
Definition: X86Subtarget.h:589
bool hasSSSE3() const
Definition: X86Subtarget.h:481
bool isTargetKFreeBSD() const
Definition: X86Subtarget.h:610
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:593
bool HasMWAITX
Processor has MONITORX/MWAITX instructions.
Definition: X86Subtarget.h:202
unsigned getStackAlignment() const
Returns the minimum alignment known to hold of the stack frame on entry to the function and which mus...
Definition: X86Subtarget.h:423
bool hasGFNI() const
Definition: X86Subtarget.h:503
bool isTargetNaCl32() const
Definition: X86Subtarget.h:614
static bool is64Bit(const char *name)
bool HasADX
Processor has ADX instructions.
Definition: X86Subtarget.h:187
bool HasBWI
Processor has AVX-512 Byte and Word instructions.
Definition: X86Subtarget.h:314
bool isXRaySupported() const override
Definition: X86Subtarget.h:583
bool hasERMSB() const
Definition: X86Subtarget.h:558
bool hasMWAITX() const
Definition: X86Subtarget.h:535
bool hasIBT() const
Definition: X86Subtarget.h:579
bool hasSSEUnalignedMem() const
Definition: X86Subtarget.h:543
bool hasF16C() const
Definition: X86Subtarget.h:514
bool HasFastSHLDRotate
True if SHLD based rotate is fast.
Definition: X86Subtarget.h:267
bool hasERI() const
Definition: X86Subtarget.h:570
bool hasPCLMUL() const
Definition: X86Subtarget.h:501
bool useLeaForSP() const
Definition: X86Subtarget.h:545
bool hasMMX() const
Definition: X86Subtarget.h:490
bool hasFXSR() const
Definition: X86Subtarget.h:496
bool isTargetWindowsGNU() const
Definition: X86Subtarget.h:635
bool isPS4CPU() const
Tests whether the target is the PS4 CPU.
Definition: Triple.h:608
bool isTargetFreeBSD() const
Definition: X86Subtarget.h:600
PICStyles::Style PICStyle
Which PIC style to use.
Definition: X86Subtarget.h:82
bool isOSKFreeBSD() const
Tests whether the OS is kFreeBSD.
Definition: Triple.h:577
bool HasXOP
Target has XOP instructions.
Definition: X86Subtarget.h:145
bool SlowLEA
True if the LEA instruction with certain arguments is slow.
Definition: X86Subtarget.h:288
bool HasDQI
Processor has AVX-512 Doubleword and Quadword instructions.
Definition: X86Subtarget.h:311
bool isPositionIndependent() const
Definition: X86Subtarget.h:658
bool hasCMov() const
Definition: X86Subtarget.h:477
bool isTargetGlibc() const
Definition: X86Subtarget.h:611
X86ProcFamilyEnum getProcFamily() const
Definition: X86Subtarget.h:585
const Triple & getTargetTriple() const
Definition: X86Subtarget.h:597
bool hasVNNI() const
Definition: X86Subtarget.h:575
bool hasXOP() const
Definition: X86Subtarget.h:509
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:598
bool IsSHLDSlow
True if SHLD instructions are slow.
Definition: X86Subtarget.h:211
X86_ThisCall - Similar to X86_StdCall.
Definition: CallingConv.h:111
InstrItineraryData InstrItins
Instruction itineraries for scheduling.
Definition: X86Subtarget.h:363
bool isTargetDarwin() const
Definition: X86Subtarget.h:599
bool hasSSE42() const
Definition: X86Subtarget.h:483
bool hasX87() const
Definition: X86Subtarget.h:475
bool isTargetMCU() const
Definition: X86Subtarget.h:616
bool isPMULLDSlow() const
Definition: X86Subtarget.h:538
bool HasFSGSBase
Processor has FS/GS base insturctions.
Definition: X86Subtarget.h:163
bool hasPRFCHW() const
Definition: X86Subtarget.h:525
bool SlowTwoMemOps
True if two memory operand instructions should use a temporary register instead.
Definition: X86Subtarget.h:281
bool isTargetWin64() const
Definition: X86Subtarget.h:647
bool IsUAMem16Slow
True if unaligned memory accesses of 16-bytes are slow.
Definition: X86Subtarget.h:218
bool hasSSE3() const
Definition: X86Subtarget.h:480
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool slowIncDec() const
Definition: X86Subtarget.h:566
bool hasBMI2() const
Definition: X86Subtarget.h:518
bool hasVPCLMULQDQ() const
Definition: X86Subtarget.h:502
bool isTargetELF() const
Definition: X86Subtarget.h:605
bool isOSIAMCU() const
Definition: Triple.h:500
const X86RegisterInfo * getRegisterInfo() const override
Definition: X86Subtarget.h:416
std::unique_ptr< InstructionSelector > InstSelector
Definition: X86Subtarget.h:369
bool isUnalignedMem16Slow() const
Definition: X86Subtarget.h:539
bool HasMPX
Processor supports MPX - Memory Protection Extensions.
Definition: X86Subtarget.h:329
bool isAtom() const
TODO: to be removed later and replaced with suitable properties.
Definition: X86Subtarget.h:588
unsigned getMaxInlineSizeThreshold() const
Returns the maximum memset / memcpy size that still makes it profitable to inline the call...
Definition: X86Subtarget.h:427
bool isPICStyleGOT() const
Definition: X86Subtarget.h:651
X86ProcFamilyEnum X86ProcFamily
X86 processor family: Intel Atom, and others.
Definition: X86Subtarget.h:79
bool HasX86_64
True if the processor supports X86-64 instructions.
Definition: X86Subtarget.h:104
bool HasSSEUnalignedMem
True if SSE operations can have unaligned memory operands.
Definition: X86Subtarget.h:225
bool HasXSAVES
Target has XSAVES instructions.
Definition: X86Subtarget.h:129
bool hasFastPartialYMMorZMMWrite() const
Definition: X86Subtarget.h:549
bool LEAusesAG() const
Definition: X86Subtarget.h:563
bool has3DNow() const
Definition: X86Subtarget.h:491
bool hasRDSEED() const
Definition: X86Subtarget.h:533
bool HasSHA
Processor has SHA instructions.
Definition: X86Subtarget.h:190
bool HasBMI
Processor has BMI1 instructions.
Definition: X86Subtarget.h:169
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:572
bool hasVBMI() const
Definition: X86Subtarget.h:519
bool HasNOPL
True if this processor has NOPL instruction (generally pentium pro+).
Definition: X86Subtarget.h:97
bool hasBITALG() const
Definition: X86Subtarget.h:576
EnvironmentType getEnvironment() const
getEnvironment - Get the parsed environment type of this triple.
Definition: Triple.h:303
bool isTargetWin32() const
Definition: X86Subtarget.h:649
bool hasXSAVEC() const
Definition: X86Subtarget.h:499
bool HasVBMI
Processor has VBMI instructions.
Definition: X86Subtarget.h:175
bool isTargetAndroid() const
Definition: X86Subtarget.h:612
bool Slow3OpsLEA
True if the LEA instruction has all three source operands: base, index, and offset or if the LEA inst...
Definition: X86Subtarget.h:293
bool isOSFreeBSD() const
Definition: Triple.h:486
The C convention as specified in the x86-64 supplement to the System V ABI, used on most non-Windows ...
Definition: CallingConv.h:144
bool isTarget64BitILP32() const
Is this x86_64 with the ILP32 programming model (x32 ABI)?
Definition: X86Subtarget.h:461
bool hasFastScalarFSQRT() const
Definition: X86Subtarget.h:553
bool hasCLFLUSHOPT() const
Definition: X86Subtarget.h:580
bool hasIFMA() const
Definition: X86Subtarget.h:521
int getScatterOverhead() const
Definition: X86Subtarget.h:542
bool isOSCygMing() const
Tests for either Cygwin or MinGW OS.
Definition: Triple.h:551
bool UseSoftFloat
Use software floating point for code generation.
Definition: X86Subtarget.h:349
bool enableAdvancedRASplitCost() const override
Definition: X86Subtarget.h:721
bool hasAnyFMA() const
Definition: X86Subtarget.h:508
bool useSoftFloat() const
Definition: X86Subtarget.h:590
std::unique_ptr< RegisterBankInfo > RegBankInfo
Definition: X86Subtarget.h:368
std::unique_ptr< LegalizerInfo > Legalizer
Definition: X86Subtarget.h:367
bool hasRDRAND() const
Definition: X86Subtarget.h:513
bool HasPCLMUL
Target has carry-less multiplication.
Definition: X86Subtarget.h:132
bool hasLAHFSAHF() const
Definition: X86Subtarget.h:534
bool HasIBT
Processor supports CET IBT - Control-Flow Enforcement Technology using Indirect Branch Tracking...
Definition: X86Subtarget.h:337
Provides the logic to select generic machine instructions.
bool is16Bit() const
Definition: X86Subtarget.h:456
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:35
bool hasVAES() const
Definition: X86Subtarget.h:495
bool isOSGlibc() const
Tests whether the OS uses glibc.
Definition: Triple.h:582
const X86SelectionDAGInfo * getSelectionDAGInfo() const override
Definition: X86Subtarget.h:412
bool isTargetDragonFly() const
Definition: X86Subtarget.h:601
MSVC calling convention that passes vectors and vector aggregates in SSE registers.
Definition: CallingConv.h:158
bool HasXSAVEOPT
Target has XSAVEOPT instructions.
Definition: X86Subtarget.h:123
bool isPositionIndependent() const
bool HasFastVariableShuffle
True if its preferable to combine to a single shuffle using a variable mask over multiple fixed shuff...
Definition: X86Subtarget.h:237
bool HasMacroFusion
True if the processor supports macrofusion.
Definition: X86Subtarget.h:270
bool hasInt256() const
Definition: X86Subtarget.h:488
X86SSEEnum X86SSELevel
SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
Definition: X86Subtarget.h:87
bool isTargetCOFF() const
Definition: X86Subtarget.h:606
bool isTargetFuchsia() const
Definition: X86Subtarget.h:617
bool HasXSAVE
Target has XSAVE instructions.
Definition: X86Subtarget.h:120
bool isTargetWindowsItanium() const
Definition: X86Subtarget.h:639
bool hasSlowDivide32() const
Definition: X86Subtarget.h:559
bool hasCDI() const
Definition: X86Subtarget.h:567
bool hasPFI() const
Definition: X86Subtarget.h:569
bool HasVNNI
Processor has AVX-512 Vector Neural Network Instructions.
Definition: X86Subtarget.h:323
bool HasCMov
True if this processor has conditional move instructions (generally pentium pro+).
Definition: X86Subtarget.h:101
bool hasMOVBE() const
Definition: X86Subtarget.h:512
bool hasBMI() const
Definition: X86Subtarget.h:517
bool hasXSAVES() const
Definition: X86Subtarget.h:500
bool hasSSE1() const
Definition: X86Subtarget.h:478
bool isTargetLinux() const
Definition: X86Subtarget.h:609
bool HasFMA4
Target has 4-operand fused multiply-add.
Definition: X86Subtarget.h:142
This file describes how to lower LLVM calls to machine code calls.
bool HasRTM
Processor has RTM instructions.
Definition: X86Subtarget.h:184
bool isCallingConvWin64(CallingConv::ID CC) const
Definition: X86Subtarget.h:660
bool isSHLDSlow() const
Definition: X86Subtarget.h:537
PICStyles::Style getPICStyle() const
Definition: X86Subtarget.h:472
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:621
bool hasMacroFusion() const
Definition: X86Subtarget.h:557
X86_StdCall - stdcall is the calling conventions mostly used by the Win32 API.
Definition: CallingConv.h:87
bool isTargetWindowsCygwin() const
Definition: X86Subtarget.h:631
bool hasAVX512() const
Definition: X86Subtarget.h:486
bool hasSSE4A() const
Definition: X86Subtarget.h:489
bool HasXSAVEC
Target has XSAVEC instructions.
Definition: X86Subtarget.h:126
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:59
bool HasVLX
Processor has AVX-512 Vector Length eXtenstions.
Definition: X86Subtarget.h:317
bool HasFastLZCNT
True if LZCNT instruction is fast.
Definition: X86Subtarget.h:264
bool hasBWI() const
Definition: X86Subtarget.h:572
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
bool HasRDSEED
Processor has RDSEED instructions.
Definition: X86Subtarget.h:196
AntiDepBreakMode getAntiDepBreakMode() const override
Definition: X86Subtarget.h:717
unsigned stackAlignment
The minimum alignment known to hold of the stack frame on entry to the function and which must be mai...
Definition: X86Subtarget.h:353
bool hasFastGather() const
Definition: X86Subtarget.h:552
bool isWindowsMSVCEnvironment() const
Checks if the environment could be MSVC.
Definition: Triple.h:523
Triple TargetTriple
What processor and OS we&#39;re targeting.
Definition: X86Subtarget.h:360
bool hasTBM() const
Definition: X86Subtarget.h:510
bool hasLZCNT() const
Definition: X86Subtarget.h:516
bool hasMFence() const
Use mfence if we have SSE2 or we&#39;re on x86-64 (even if we asked for no-sse2).
Definition: X86Subtarget.h:595
bool hasXSAVEOPT() const
Definition: X86Subtarget.h:498
bool HasMOVBE
True if the processor has the MOVBE instruction.
Definition: X86Subtarget.h:154
bool PadShortFunctions
True if the short functions should be padded to prevent a stall when returning too early...
Definition: X86Subtarget.h:277
bool HasCLZERO
Processor has Cache Line Zero instruction.
Definition: X86Subtarget.h:205
bool hasSSE2() const
Definition: X86Subtarget.h:479
X86_FastCall - &#39;fast&#39; analog of X86_StdCall.
Definition: CallingConv.h:92
bool hasRTM() const
Definition: X86Subtarget.h:522
bool hasFastVectorFSQRT() const
Definition: X86Subtarget.h:554
bool HasSlowDivide64
True if 32-bit divides are significantly faster than 64-bit divisions and should be used when possibl...
Definition: X86Subtarget.h:261
bool isTargetWindowsCoreCLR() const
Definition: X86Subtarget.h:627