LLVM  6.0.0svn
X86Subtarget.h
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1 //===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file declares the X86 specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_X86_X86SUBTARGET_H
15 #define LLVM_LIB_TARGET_X86_X86SUBTARGET_H
16 
17 #include "X86FrameLowering.h"
18 #include "X86ISelLowering.h"
19 #include "X86InstrInfo.h"
20 #include "X86SelectionDAGInfo.h"
21 #include "llvm/ADT/StringRef.h"
22 #include "llvm/ADT/Triple.h"
28 #include "llvm/IR/CallingConv.h"
31 #include <memory>
32 
33 #define GET_SUBTARGETINFO_HEADER
34 #include "X86GenSubtargetInfo.inc"
35 
36 namespace llvm {
37 
38 class GlobalValue;
39 
40 /// The X86 backend supports a number of different styles of PIC.
41 ///
42 namespace PICStyles {
43 
44 enum Style {
45  StubPIC, // Used on i386-darwin in pic mode.
46  GOT, // Used on 32 bit elf on when in pic mode.
47  RIPRel, // Used on X86-64 when in pic mode.
48  None // Set when not in pic mode.
49 };
50 
51 } // end namespace PICStyles
52 
53 class X86Subtarget final : public X86GenSubtargetInfo {
54 protected:
55  enum X86SSEEnum {
56  NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
57  };
58 
59  enum X863DNowEnum {
60  NoThreeDNow, MMX, ThreeDNow, ThreeDNowA
61  };
62 
75  };
76 
77  /// X86 processor family: Intel Atom, and others
79 
80  /// Which PIC style to use
82 
83  const TargetMachine &TM;
84 
85  /// SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
87 
88  /// MMX, 3DNow, 3DNow Athlon, or none supported.
90 
91  /// True if the processor supports X87 instructions.
92  bool HasX87;
93 
94  /// True if this processor has conditional move instructions
95  /// (generally pentium pro+).
96  bool HasCMov;
97 
98  /// True if the processor supports X86-64 instructions.
99  bool HasX86_64;
100 
101  /// True if the processor supports POPCNT.
102  bool HasPOPCNT;
103 
104  /// True if the processor supports SSE4A instructions.
105  bool HasSSE4A;
106 
107  /// Target has AES instructions
108  bool HasAES;
109 
110  /// Target has FXSAVE/FXRESTOR instructions
111  bool HasFXSR;
112 
113  /// Target has XSAVE instructions
114  bool HasXSAVE;
115 
116  /// Target has XSAVEOPT instructions
118 
119  /// Target has XSAVEC instructions
120  bool HasXSAVEC;
121 
122  /// Target has XSAVES instructions
123  bool HasXSAVES;
124 
125  /// Target has carry-less multiplication
126  bool HasPCLMUL;
127 
128  /// Target has 3-operand fused multiply-add
129  bool HasFMA;
130 
131  /// Target has 4-operand fused multiply-add
132  bool HasFMA4;
133 
134  /// Target has XOP instructions
135  bool HasXOP;
136 
137  /// Target has TBM instructions.
138  bool HasTBM;
139 
140  /// Target has LWP instructions
141  bool HasLWP;
142 
143  /// True if the processor has the MOVBE instruction.
144  bool HasMOVBE;
145 
146  /// True if the processor has the RDRAND instruction.
147  bool HasRDRAND;
148 
149  /// Processor has 16-bit floating point conversion instructions.
150  bool HasF16C;
151 
152  /// Processor has FS/GS base insturctions.
154 
155  /// Processor has LZCNT instruction.
156  bool HasLZCNT;
157 
158  /// Processor has BMI1 instructions.
159  bool HasBMI;
160 
161  /// Processor has BMI2 instructions.
162  bool HasBMI2;
163 
164  /// Processor has VBMI instructions.
165  bool HasVBMI;
166 
167  /// Processor has Integer Fused Multiply Add
168  bool HasIFMA;
169 
170  /// Processor has RTM instructions.
171  bool HasRTM;
172 
173  /// Processor has ADX instructions.
174  bool HasADX;
175 
176  /// Processor has SHA instructions.
177  bool HasSHA;
178 
179  /// Processor has PRFCHW instructions.
180  bool HasPRFCHW;
181 
182  /// Processor has RDSEED instructions.
183  bool HasRDSEED;
184 
185  /// Processor has LAHF/SAHF instructions.
187 
188  /// Processor has MONITORX/MWAITX instructions.
189  bool HasMWAITX;
190 
191  /// Processor has Cache Line Zero instruction
192  bool HasCLZERO;
193 
194  /// Processor has Prefetch with intent to Write instruction
196 
197  /// True if SHLD instructions are slow.
199 
200  /// True if the PMULLD instruction is slow compared to PMULLW/PMULHW and
201  // PMULUDQ.
203 
204  /// True if unaligned memory accesses of 16-bytes are slow.
206 
207  /// True if unaligned memory accesses of 32-bytes are slow.
209 
210  /// True if SSE operations can have unaligned memory operands.
211  /// This may require setting a configuration bit in the processor.
213 
214  /// True if this processor has the CMPXCHG16B instruction;
215  /// this is true for most x86-64 chips, but not the first AMD chips.
217 
218  /// True if the LEA instruction should be used for adjusting
219  /// the stack pointer. This is an optimization for Intel Atom processors.
221 
222  /// True if there is no performance penalty to writing only the lower parts
223  /// of a YMM or ZMM register without clearing the upper part.
225 
226  /// True if hardware SQRTSS instruction is at least as fast (latency) as
227  /// RSQRTSS followed by a Newton-Raphson iteration.
229 
230  /// True if hardware SQRTPS/VSQRTPS instructions are at least as fast
231  /// (throughput) as RSQRTPS/VRSQRTPS followed by a Newton-Raphson iteration.
233 
234  /// True if 8-bit divisions are significantly faster than
235  /// 32-bit divisions and should be used when possible.
237 
238  /// True if 32-bit divides are significantly faster than
239  /// 64-bit divisions and should be used when possible.
241 
242  /// True if LZCNT instruction is fast.
244 
245  /// True if SHLD based rotate is fast.
247 
248  /// True if the processor supports macrofusion.
250 
251  /// True if the processor has enhanced REP MOVSB/STOSB.
252  bool HasERMSB;
253 
254  /// True if the short functions should be padded to prevent
255  /// a stall when returning too early.
257 
258  /// True if two memory operand instructions should use a temporary register
259  /// instead.
261 
262  /// True if the LEA instruction inputs have to be ready at address generation
263  /// (AG) time.
264  bool LEAUsesAG;
265 
266  /// True if the LEA instruction with certain arguments is slow
267  bool SlowLEA;
268 
269  /// True if the LEA instruction has all three source operands: base, index,
270  /// and offset or if the LEA instruction uses base and index registers where
271  /// the base is EBP, RBP,or R13
273 
274  /// True if INC and DEC instructions are slow when writing to flags
276 
277  /// Processor has AVX-512 PreFetch Instructions
278  bool HasPFI;
279 
280  /// Processor has AVX-512 Exponential and Reciprocal Instructions
281  bool HasERI;
282 
283  /// Processor has AVX-512 Conflict Detection Instructions
284  bool HasCDI;
285 
286  /// Processor has AVX-512 population count Instructions
288 
289  /// Processor has AVX-512 Doubleword and Quadword instructions
290  bool HasDQI;
291 
292  /// Processor has AVX-512 Byte and Word instructions
293  bool HasBWI;
294 
295  /// Processor has AVX-512 Vector Length eXtenstions
296  bool HasVLX;
297 
298  /// Processor has PKU extenstions
299  bool HasPKU;
300 
301  /// Processor supports MPX - Memory Protection Extensions
302  bool HasMPX;
303 
304  /// Processor has Software Guard Extensions
305  bool HasSGX;
306 
307  /// Processor supports Flush Cache Line instruction
309 
310  /// Processor supports Cache Line Write Back instruction
311  bool HasCLWB;
312 
313  /// Use software floating point for code generation.
315 
316  /// The minimum alignment known to hold of the stack frame on
317  /// entry to the function and which must be maintained by every function.
318  unsigned stackAlignment;
319 
320  /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
321  ///
323 
324  /// What processor and OS we're targeting.
326 
327  /// Instruction itineraries for scheduling
329 
330  /// GlobalISel related APIs.
331  std::unique_ptr<CallLowering> CallLoweringInfo;
332  std::unique_ptr<LegalizerInfo> Legalizer;
333  std::unique_ptr<RegisterBankInfo> RegBankInfo;
334  std::unique_ptr<InstructionSelector> InstSelector;
335 
336 private:
337  /// Override the stack alignment.
338  unsigned StackAlignOverride;
339 
340  /// True if compiling for 64-bit, false for 16-bit or 32-bit.
341  bool In64BitMode;
342 
343  /// True if compiling for 32-bit, false for 16-bit or 64-bit.
344  bool In32BitMode;
345 
346  /// True if compiling for 16-bit, false for 32-bit or 64-bit.
347  bool In16BitMode;
348 
349  /// Contains the Overhead of gather\scatter instructions
350  int GatherOverhead;
351  int ScatterOverhead;
352 
353  X86SelectionDAGInfo TSInfo;
354  // Ordering here is important. X86InstrInfo initializes X86RegisterInfo which
355  // X86TargetLowering needs.
356  X86InstrInfo InstrInfo;
357  X86TargetLowering TLInfo;
358  X86FrameLowering FrameLowering;
359 
360 public:
361  /// This constructor initializes the data members to match that
362  /// of the specified triple.
363  ///
364  X86Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
365  const X86TargetMachine &TM, unsigned StackAlignOverride);
366 
367  const X86TargetLowering *getTargetLowering() const override {
368  return &TLInfo;
369  }
370 
371  const X86InstrInfo *getInstrInfo() const override { return &InstrInfo; }
372 
373  const X86FrameLowering *getFrameLowering() const override {
374  return &FrameLowering;
375  }
376 
377  const X86SelectionDAGInfo *getSelectionDAGInfo() const override {
378  return &TSInfo;
379  }
380 
381  const X86RegisterInfo *getRegisterInfo() const override {
382  return &getInstrInfo()->getRegisterInfo();
383  }
384 
385  /// Returns the minimum alignment known to hold of the
386  /// stack frame on entry to the function and which must be maintained by every
387  /// function for this subtarget.
388  unsigned getStackAlignment() const { return stackAlignment; }
389 
390  /// Returns the maximum memset / memcpy size
391  /// that still makes it profitable to inline the call.
392  unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
393 
394  /// ParseSubtargetFeatures - Parses features string setting specified
395  /// subtarget options. Definition of function is auto generated by tblgen.
396  void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
397 
398  /// Methods used by Global ISel
399  const CallLowering *getCallLowering() const override;
400  const InstructionSelector *getInstructionSelector() const override;
401  const LegalizerInfo *getLegalizerInfo() const override;
402  const RegisterBankInfo *getRegBankInfo() const override;
403 
404 private:
405  /// Initialize the full set of dependencies so we can use an initializer
406  /// list for X86Subtarget.
407  X86Subtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
408  void initializeEnvironment();
409  void initSubtargetFeatures(StringRef CPU, StringRef FS);
410 
411 public:
412  /// Is this x86_64? (disregarding specific ABI / programming model)
413  bool is64Bit() const {
414  return In64BitMode;
415  }
416 
417  bool is32Bit() const {
418  return In32BitMode;
419  }
420 
421  bool is16Bit() const {
422  return In16BitMode;
423  }
424 
425  /// Is this x86_64 with the ILP32 programming model (x32 ABI)?
426  bool isTarget64BitILP32() const {
427  return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32 ||
428  TargetTriple.isOSNaCl());
429  }
430 
431  /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
432  bool isTarget64BitLP64() const {
433  return In64BitMode && (TargetTriple.getEnvironment() != Triple::GNUX32 &&
434  !TargetTriple.isOSNaCl());
435  }
436 
437  PICStyles::Style getPICStyle() const { return PICStyle; }
438  void setPICStyle(PICStyles::Style Style) { PICStyle = Style; }
439 
440  bool hasX87() const { return HasX87; }
441  bool hasCMov() const { return HasCMov; }
442  bool hasSSE1() const { return X86SSELevel >= SSE1; }
443  bool hasSSE2() const { return X86SSELevel >= SSE2; }
444  bool hasSSE3() const { return X86SSELevel >= SSE3; }
445  bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
446  bool hasSSE41() const { return X86SSELevel >= SSE41; }
447  bool hasSSE42() const { return X86SSELevel >= SSE42; }
448  bool hasAVX() const { return X86SSELevel >= AVX; }
449  bool hasAVX2() const { return X86SSELevel >= AVX2; }
450  bool hasAVX512() const { return X86SSELevel >= AVX512F; }
451  bool hasFp256() const { return hasAVX(); }
452  bool hasInt256() const { return hasAVX2(); }
453  bool hasSSE4A() const { return HasSSE4A; }
454  bool hasMMX() const { return X863DNowLevel >= MMX; }
455  bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
456  bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
457  bool hasPOPCNT() const { return HasPOPCNT; }
458  bool hasAES() const { return HasAES; }
459  bool hasFXSR() const { return HasFXSR; }
460  bool hasXSAVE() const { return HasXSAVE; }
461  bool hasXSAVEOPT() const { return HasXSAVEOPT; }
462  bool hasXSAVEC() const { return HasXSAVEC; }
463  bool hasXSAVES() const { return HasXSAVES; }
464  bool hasPCLMUL() const { return HasPCLMUL; }
465  // Prefer FMA4 to FMA - its better for commutation/memory folding and
466  // has equal or better performance on all supported targets.
467  bool hasFMA() const { return HasFMA && !HasFMA4; }
468  bool hasFMA4() const { return HasFMA4; }
469  bool hasAnyFMA() const { return hasFMA() || hasFMA4(); }
470  bool hasXOP() const { return HasXOP; }
471  bool hasTBM() const { return HasTBM; }
472  bool hasLWP() const { return HasLWP; }
473  bool hasMOVBE() const { return HasMOVBE; }
474  bool hasRDRAND() const { return HasRDRAND; }
475  bool hasF16C() const { return HasF16C; }
476  bool hasFSGSBase() const { return HasFSGSBase; }
477  bool hasLZCNT() const { return HasLZCNT; }
478  bool hasBMI() const { return HasBMI; }
479  bool hasBMI2() const { return HasBMI2; }
480  bool hasVBMI() const { return HasVBMI; }
481  bool hasIFMA() const { return HasIFMA; }
482  bool hasRTM() const { return HasRTM; }
483  bool hasADX() const { return HasADX; }
484  bool hasSHA() const { return HasSHA; }
485  bool hasPRFCHW() const { return HasPRFCHW; }
486  bool hasRDSEED() const { return HasRDSEED; }
487  bool hasLAHFSAHF() const { return HasLAHFSAHF; }
488  bool hasMWAITX() const { return HasMWAITX; }
489  bool hasCLZERO() const { return HasCLZERO; }
490  bool isSHLDSlow() const { return IsSHLDSlow; }
491  bool isPMULLDSlow() const { return IsPMULLDSlow; }
492  bool isUnalignedMem16Slow() const { return IsUAMem16Slow; }
493  bool isUnalignedMem32Slow() const { return IsUAMem32Slow; }
494  int getGatherOverhead() const { return GatherOverhead; }
495  int getScatterOverhead() const { return ScatterOverhead; }
496  bool hasSSEUnalignedMem() const { return HasSSEUnalignedMem; }
497  bool hasCmpxchg16b() const { return HasCmpxchg16b; }
498  bool useLeaForSP() const { return UseLeaForSP; }
500  return HasFastPartialYMMorZMMWrite;
501  }
502  bool hasFastScalarFSQRT() const { return HasFastScalarFSQRT; }
503  bool hasFastVectorFSQRT() const { return HasFastVectorFSQRT; }
504  bool hasFastLZCNT() const { return HasFastLZCNT; }
505  bool hasFastSHLDRotate() const { return HasFastSHLDRotate; }
506  bool hasMacroFusion() const { return HasMacroFusion; }
507  bool hasERMSB() const { return HasERMSB; }
508  bool hasSlowDivide32() const { return HasSlowDivide32; }
509  bool hasSlowDivide64() const { return HasSlowDivide64; }
510  bool padShortFunctions() const { return PadShortFunctions; }
511  bool slowTwoMemOps() const { return SlowTwoMemOps; }
512  bool LEAusesAG() const { return LEAUsesAG; }
513  bool slowLEA() const { return SlowLEA; }
514  bool slow3OpsLEA() const { return Slow3OpsLEA; }
515  bool slowIncDec() const { return SlowIncDec; }
516  bool hasCDI() const { return HasCDI; }
517  bool hasVPOPCNTDQ() const { return HasVPOPCNTDQ; }
518  bool hasPFI() const { return HasPFI; }
519  bool hasERI() const { return HasERI; }
520  bool hasDQI() const { return HasDQI; }
521  bool hasBWI() const { return HasBWI; }
522  bool hasVLX() const { return HasVLX; }
523  bool hasPKU() const { return HasPKU; }
524  bool hasMPX() const { return HasMPX; }
525  bool hasCLFLUSHOPT() const { return HasCLFLUSHOPT; }
526  bool hasCLWB() const { return HasCLWB; }
527 
528  bool isXRaySupported() const override { return is64Bit(); }
529 
530  X86ProcFamilyEnum getProcFamily() const { return X86ProcFamily; }
531 
532  /// TODO: to be removed later and replaced with suitable properties
533  bool isAtom() const { return X86ProcFamily == IntelAtom; }
534  bool isSLM() const { return X86ProcFamily == IntelSLM; }
535  bool useSoftFloat() const { return UseSoftFloat; }
536 
537  /// Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
538  /// no-sse2). There isn't any reason to disable it if the target processor
539  /// supports it.
540  bool hasMFence() const { return hasSSE2() || is64Bit(); }
541 
542  const Triple &getTargetTriple() const { return TargetTriple; }
543 
544  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
545  bool isTargetFreeBSD() const { return TargetTriple.isOSFreeBSD(); }
546  bool isTargetDragonFly() const { return TargetTriple.isOSDragonFly(); }
547  bool isTargetSolaris() const { return TargetTriple.isOSSolaris(); }
548  bool isTargetPS4() const { return TargetTriple.isPS4CPU(); }
549 
550  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
551  bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
552  bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
553 
554  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
555  bool isTargetKFreeBSD() const { return TargetTriple.isOSKFreeBSD(); }
556  bool isTargetGlibc() const { return TargetTriple.isOSGlibc(); }
557  bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
558  bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
559  bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
560  bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
561  bool isTargetMCU() const { return TargetTriple.isOSIAMCU(); }
562  bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
563 
564  bool isTargetWindowsMSVC() const {
565  return TargetTriple.isWindowsMSVCEnvironment();
566  }
567 
569  return TargetTriple.isKnownWindowsMSVCEnvironment();
570  }
571 
572  bool isTargetWindowsCoreCLR() const {
573  return TargetTriple.isWindowsCoreCLREnvironment();
574  }
575 
576  bool isTargetWindowsCygwin() const {
577  return TargetTriple.isWindowsCygwinEnvironment();
578  }
579 
580  bool isTargetWindowsGNU() const {
581  return TargetTriple.isWindowsGNUEnvironment();
582  }
583 
584  bool isTargetWindowsItanium() const {
585  return TargetTriple.isWindowsItaniumEnvironment();
586  }
587 
588  bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
589 
590  bool isOSWindows() const { return TargetTriple.isOSWindows(); }
591 
592  bool isTargetWin64() const { return In64BitMode && isOSWindows(); }
593 
594  bool isTargetWin32() const { return !In64BitMode && isOSWindows(); }
595 
596  bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
597  bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
598 
599  bool isPICStyleStubPIC() const {
600  return PICStyle == PICStyles::StubPIC;
601  }
602 
603  bool isPositionIndependent() const { return TM.isPositionIndependent(); }
604 
606  switch (CC) {
607  // On Win64, all these conventions just use the default convention.
608  case CallingConv::C:
609  case CallingConv::Fast:
610  case CallingConv::Swift:
616  return isTargetWin64();
617  // This convention allows using the Win64 convention on other targets.
618  case CallingConv::Win64:
619  return true;
620  // This convention allows using the SysV convention on Windows targets.
622  return false;
623  // Otherwise, who knows what this is.
624  default:
625  return false;
626  }
627  }
628 
629  /// Classify a global variable reference for the current subtarget according
630  /// to how we should reference it in a non-pcrel context.
631  unsigned char classifyLocalReference(const GlobalValue *GV) const;
632 
633  unsigned char classifyGlobalReference(const GlobalValue *GV,
634  const Module &M) const;
635  unsigned char classifyGlobalReference(const GlobalValue *GV) const;
636 
637  /// Classify a global function reference for the current subtarget.
638  unsigned char classifyGlobalFunctionReference(const GlobalValue *GV,
639  const Module &M) const;
640  unsigned char classifyGlobalFunctionReference(const GlobalValue *GV) const;
641 
642  /// Classify a blockaddress reference for the current subtarget according to
643  /// how we should reference it in a non-pcrel context.
644  unsigned char classifyBlockAddressReference() const;
645 
646  /// Return true if the subtarget allows calls to immediate address.
647  bool isLegalToCallImmediateAddr() const;
648 
649  /// This function returns the name of a function which has an interface
650  /// like the non-standard bzero function, if such a function exists on
651  /// the current subtarget and it is considered prefereable over
652  /// memset with zero passed as the second argument. Otherwise it
653  /// returns null.
654  const char *getBZeroEntry() const;
655 
656  /// This function returns true if the target has sincos() routine in its
657  /// compiler runtime or math libraries.
658  bool hasSinCos() const;
659 
660  /// Enable the MachineScheduler pass for all X86 subtargets.
661  bool enableMachineScheduler() const override { return true; }
662 
663  // TODO: Update the regression tests and return true.
664  bool supportPrintSchedInfo() const override { return false; }
665 
666  bool enableEarlyIfConversion() const override;
667 
668  /// Return the instruction itineraries based on the subtarget selection.
669  const InstrItineraryData *getInstrItineraryData() const override {
670  return &InstrItins;
671  }
672 
673  AntiDepBreakMode getAntiDepBreakMode() const override {
674  return TargetSubtargetInfo::ANTIDEP_CRITICAL;
675  }
676 
677  bool enableAdvancedRASplitCost() const override { return true; }
678 };
679 
680 } // end namespace llvm
681 
682 #endif // LLVM_LIB_TARGET_X86_X86SUBTARGET_H
bool hasAVX() const
Definition: X86Subtarget.h:448
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:43
bool HasPRFCHW
Processor has PRFCHW instructions.
Definition: X86Subtarget.h:180
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:470
bool isTargetPS4() const
Definition: X86Subtarget.h:548
bool HasFXSR
Target has FXSAVE/FXRESTOR instructions.
Definition: X86Subtarget.h:111
bool HasTBM
Target has TBM instructions.
Definition: X86Subtarget.h:138
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:413
bool HasBMI2
Processor has BMI2 instructions.
Definition: X86Subtarget.h:162
bool hasSHA() const
Definition: X86Subtarget.h:484
bool supportPrintSchedInfo() const override
Definition: X86Subtarget.h:664
bool HasSGX
Processor has Software Guard Extensions.
Definition: X86Subtarget.h:305
bool hasSSE41() const
Definition: X86Subtarget.h:446
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool isOSWindows() const
Definition: X86Subtarget.h:590
bool hasPOPCNT() const
Definition: X86Subtarget.h:457
bool hasAVX2() const
Definition: X86Subtarget.h:449
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:63
bool hasFMA() const
Definition: X86Subtarget.h:467
bool HasLAHFSAHF
Processor has LAHF/SAHF instructions.
Definition: X86Subtarget.h:186
bool hasSlowDivide64() const
Definition: X86Subtarget.h:509
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:588
const X86InstrInfo * getInstrInfo() const override
Definition: X86Subtarget.h:371
bool HasCDI
Processor has AVX-512 Conflict Detection Instructions.
Definition: X86Subtarget.h:284
bool HasAES
Target has AES instructions.
Definition: X86Subtarget.h:108
bool hasCLWB() const
Definition: X86Subtarget.h:526
X86_StdCall - stdcall is the calling conventions mostly used by the Win32 API.
Definition: CallingConv.h:87
bool slowLEA() const
Definition: X86Subtarget.h:513
const X86FrameLowering * getFrameLowering() const override
Definition: X86Subtarget.h:373
void setPICStyle(PICStyles::Style Style)
Definition: X86Subtarget.h:438
const TargetMachine & TM
Definition: X86Subtarget.h:83
bool HasERI
Processor has AVX-512 Exponential and Reciprocal Instructions.
Definition: X86Subtarget.h:281
bool enableMachineScheduler() const override
Enable the MachineScheduler pass for all X86 subtargets.
Definition: X86Subtarget.h:661
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
Definition: Triple.h:567
unsigned MaxInlineSizeThreshold
Max.
Definition: X86Subtarget.h:322
bool HasERMSB
True if the processor has enhanced REP MOVSB/STOSB.
Definition: X86Subtarget.h:252
bool LEAUsesAG
True if the LEA instruction inputs have to be ready at address generation (AG) time.
Definition: X86Subtarget.h:264
bool HasVPOPCNTDQ
Processor has AVX-512 population count Instructions.
Definition: X86Subtarget.h:287
X86_ThisCall - Similar to X86_StdCall.
Definition: CallingConv.h:111
bool HasFastScalarFSQRT
True if hardware SQRTSS instruction is at least as fast (latency) as RSQRTSS followed by a Newton-Rap...
Definition: X86Subtarget.h:228
bool hasCLZERO() const
Definition: X86Subtarget.h:489
bool IsUAMem32Slow
True if unaligned memory accesses of 32-bytes are slow.
Definition: X86Subtarget.h:208
bool HasLWP
Target has LWP instructions.
Definition: X86Subtarget.h:141
bool has3DNowA() const
Definition: X86Subtarget.h:456
bool isOSFuchsia() const
Definition: Triple.h:490
bool isTargetNaCl64() const
Definition: X86Subtarget.h:560
bool IsPMULLDSlow
True if the PMULLD instruction is slow compared to PMULLW/PMULHW and.
Definition: X86Subtarget.h:202
bool isWindowsCygwinEnvironment() const
Definition: Triple.h:542
bool isTargetKnownWindowsMSVC() const
Definition: X86Subtarget.h:568
bool HasRDRAND
True if the processor has the RDRAND instruction.
Definition: X86Subtarget.h:147
bool slowTwoMemOps() const
Definition: X86Subtarget.h:511
bool isTargetWindowsMSVC() const
Definition: X86Subtarget.h:564
bool HasFastPartialYMMorZMMWrite
True if there is no performance penalty to writing only the lower parts of a YMM or ZMM register with...
Definition: X86Subtarget.h:224
bool isTargetMachO() const
Definition: X86Subtarget.h:552
int getGatherOverhead() const
Definition: X86Subtarget.h:494
bool HasCLWB
Processor supports Cache Line Write Back instruction.
Definition: X86Subtarget.h:311
bool HasFMA
Target has 3-operand fused multiply-add.
Definition: X86Subtarget.h:129
bool hasXSAVE() const
Definition: X86Subtarget.h:460
bool isUnalignedMem32Slow() const
Definition: X86Subtarget.h:493
bool isPICStyleStubPIC() const
Definition: X86Subtarget.h:599
bool hasVPOPCNTDQ() const
Definition: X86Subtarget.h:517
bool HasFastVectorFSQRT
True if hardware SQRTPS/VSQRTPS instructions are at least as fast (throughput) as RSQRTPS/VRSQRTPS fo...
Definition: X86Subtarget.h:232
Holds all the information related to register banks.
bool hasLWP() const
Definition: X86Subtarget.h:472
bool isPICStyleRIPRel() const
Definition: X86Subtarget.h:597
const InstrItineraryData * getInstrItineraryData() const override
Return the instruction itineraries based on the subtarget selection.
Definition: X86Subtarget.h:669
bool hasFMA4() const
Definition: X86Subtarget.h:468
bool padShortFunctions() const
Definition: X86Subtarget.h:510
The C convention as specified in the x86-64 supplement to the System V ABI, used on most non-Windows ...
Definition: CallingConv.h:144
bool isTargetSolaris() const
Definition: X86Subtarget.h:547
bool HasCLFLUSHOPT
Processor supports Flush Cache Line instruction.
Definition: X86Subtarget.h:308
bool hasAES() const
Definition: X86Subtarget.h:458
bool HasPOPCNT
True if the processor supports POPCNT.
Definition: X86Subtarget.h:102
bool HasPKU
Processor has PKU extenstions.
Definition: X86Subtarget.h:299
bool isTarget64BitLP64() const
Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
Definition: X86Subtarget.h:432
bool isKnownWindowsMSVCEnvironment() const
Checks if the environment is MSVC.
Definition: Triple.h:530
bool hasPKU() const
Definition: X86Subtarget.h:523
bool is32Bit() const
Definition: X86Subtarget.h:417
bool hasCmpxchg16b() const
Definition: X86Subtarget.h:497
bool HasSlowDivide32
True if 8-bit divisions are significantly faster than 32-bit divisions and should be used when possib...
Definition: X86Subtarget.h:236
bool hasFp256() const
Definition: X86Subtarget.h:451
bool hasFastLZCNT() const
Definition: X86Subtarget.h:504
bool isOSSolaris() const
Definition: Triple.h:496
bool hasVLX() const
Definition: X86Subtarget.h:522
bool slow3OpsLEA() const
Definition: X86Subtarget.h:514
bool HasPFI
Processor has AVX-512 PreFetch Instructions.
Definition: X86Subtarget.h:278
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
Definition: X86Subtarget.h:331
bool hasFastSHLDRotate() const
Definition: X86Subtarget.h:505
bool isTargetNaCl() const
Definition: X86Subtarget.h:558
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:35
bool HasIFMA
Processor has Integer Fused Multiply Add.
Definition: X86Subtarget.h:168
bool HasCmpxchg16b
True if this processor has the CMPXCHG16B instruction; this is true for most x86-64 chips...
Definition: X86Subtarget.h:216
bool isTargetCygMing() const
Definition: X86Subtarget.h:588
bool HasX87
True if the processor supports X87 instructions.
Definition: X86Subtarget.h:92
bool hasMPX() const
Definition: X86Subtarget.h:524
Itinerary data supplied by a subtarget to be used by a target.
bool isWindowsItaniumEnvironment() const
Definition: Triple.h:538
bool UseLeaForSP
True if the LEA instruction should be used for adjusting the stack pointer.
Definition: X86Subtarget.h:220
bool isWindowsGNUEnvironment() const
Definition: Triple.h:546
bool hasFSGSBase() const
Definition: X86Subtarget.h:476
X863DNowEnum X863DNowLevel
MMX, 3DNow, 3DNow Athlon, or none supported.
Definition: X86Subtarget.h:89
bool hasDQI() const
Definition: X86Subtarget.h:520
bool HasSSE4A
True if the processor supports SSE4A instructions.
Definition: X86Subtarget.h:105
bool isWindowsCoreCLREnvironment() const
Definition: Triple.h:534
bool HasLZCNT
Processor has LZCNT instruction.
Definition: X86Subtarget.h:156
bool HasF16C
Processor has 16-bit floating point conversion instructions.
Definition: X86Subtarget.h:150
bool SlowIncDec
True if INC and DEC instructions are slow when writing to flags.
Definition: X86Subtarget.h:275
bool isOSDragonFly() const
Definition: Triple.h:494
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:562
const X86TargetLowering * getTargetLowering() const override
Definition: X86Subtarget.h:367
bool hasADX() const
Definition: X86Subtarget.h:483
bool isSLM() const
Definition: X86Subtarget.h:534
bool hasSSSE3() const
Definition: X86Subtarget.h:445
bool isTargetKFreeBSD() const
Definition: X86Subtarget.h:555
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:593
bool HasMWAITX
Processor has MONITORX/MWAITX instructions.
Definition: X86Subtarget.h:189
unsigned getStackAlignment() const
Returns the minimum alignment known to hold of the stack frame on entry to the function and which mus...
Definition: X86Subtarget.h:388
bool HasPFPREFETCHWT1
Processor has Prefetch with intent to Write instruction.
Definition: X86Subtarget.h:195
bool isTargetNaCl32() const
Definition: X86Subtarget.h:559
static bool is64Bit(const char *name)
MSVC calling convention that passes vectors and vector aggregates in SSE registers.
Definition: CallingConv.h:158
bool HasADX
Processor has ADX instructions.
Definition: X86Subtarget.h:174
bool HasBWI
Processor has AVX-512 Byte and Word instructions.
Definition: X86Subtarget.h:293
bool isXRaySupported() const override
Definition: X86Subtarget.h:528
bool hasERMSB() const
Definition: X86Subtarget.h:507
bool hasMWAITX() const
Definition: X86Subtarget.h:488
bool hasSSEUnalignedMem() const
Definition: X86Subtarget.h:496
bool hasF16C() const
Definition: X86Subtarget.h:475
bool HasFastSHLDRotate
True if SHLD based rotate is fast.
Definition: X86Subtarget.h:246
bool hasERI() const
Definition: X86Subtarget.h:519
bool hasPCLMUL() const
Definition: X86Subtarget.h:464
bool useLeaForSP() const
Definition: X86Subtarget.h:498
bool hasMMX() const
Definition: X86Subtarget.h:454
bool hasFXSR() const
Definition: X86Subtarget.h:459
bool isTargetWindowsGNU() const
Definition: X86Subtarget.h:580
bool isPS4CPU() const
Tests whether the target is the PS4 CPU.
Definition: Triple.h:608
bool isTargetFreeBSD() const
Definition: X86Subtarget.h:545
PICStyles::Style PICStyle
Which PIC style to use.
Definition: X86Subtarget.h:81
bool isOSKFreeBSD() const
Tests whether the OS is kFreeBSD.
Definition: Triple.h:577
bool HasXOP
Target has XOP instructions.
Definition: X86Subtarget.h:135
bool SlowLEA
True if the LEA instruction with certain arguments is slow.
Definition: X86Subtarget.h:267
bool HasDQI
Processor has AVX-512 Doubleword and Quadword instructions.
Definition: X86Subtarget.h:290
bool isPositionIndependent() const
Definition: X86Subtarget.h:603
bool hasCMov() const
Definition: X86Subtarget.h:441
bool isTargetGlibc() const
Definition: X86Subtarget.h:556
X86ProcFamilyEnum getProcFamily() const
Definition: X86Subtarget.h:530
const Triple & getTargetTriple() const
Definition: X86Subtarget.h:542
bool hasXOP() const
Definition: X86Subtarget.h:470
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:598
bool IsSHLDSlow
True if SHLD instructions are slow.
Definition: X86Subtarget.h:198
InstrItineraryData InstrItins
Instruction itineraries for scheduling.
Definition: X86Subtarget.h:328
bool isTargetDarwin() const
Definition: X86Subtarget.h:544
bool hasSSE42() const
Definition: X86Subtarget.h:447
bool hasX87() const
Definition: X86Subtarget.h:440
bool isTargetMCU() const
Definition: X86Subtarget.h:561
bool isPMULLDSlow() const
Definition: X86Subtarget.h:491
bool HasFSGSBase
Processor has FS/GS base insturctions.
Definition: X86Subtarget.h:153
bool hasPRFCHW() const
Definition: X86Subtarget.h:485
bool SlowTwoMemOps
True if two memory operand instructions should use a temporary register instead.
Definition: X86Subtarget.h:260
bool isTargetWin64() const
Definition: X86Subtarget.h:592
bool IsUAMem16Slow
True if unaligned memory accesses of 16-bytes are slow.
Definition: X86Subtarget.h:205
bool hasSSE3() const
Definition: X86Subtarget.h:444
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool slowIncDec() const
Definition: X86Subtarget.h:515
bool hasBMI2() const
Definition: X86Subtarget.h:479
bool isTargetELF() const
Definition: X86Subtarget.h:550
bool isOSIAMCU() const
Definition: Triple.h:500
const X86RegisterInfo * getRegisterInfo() const override
Definition: X86Subtarget.h:381
std::unique_ptr< InstructionSelector > InstSelector
Definition: X86Subtarget.h:334
bool isUnalignedMem16Slow() const
Definition: X86Subtarget.h:492
bool HasMPX
Processor supports MPX - Memory Protection Extensions.
Definition: X86Subtarget.h:302
bool isAtom() const
TODO: to be removed later and replaced with suitable properties.
Definition: X86Subtarget.h:533
unsigned getMaxInlineSizeThreshold() const
Returns the maximum memset / memcpy size that still makes it profitable to inline the call...
Definition: X86Subtarget.h:392
bool isPICStyleGOT() const
Definition: X86Subtarget.h:596
X86ProcFamilyEnum X86ProcFamily
X86 processor family: Intel Atom, and others.
Definition: X86Subtarget.h:78
bool HasX86_64
True if the processor supports X86-64 instructions.
Definition: X86Subtarget.h:99
bool HasSSEUnalignedMem
True if SSE operations can have unaligned memory operands.
Definition: X86Subtarget.h:212
bool HasXSAVES
Target has XSAVES instructions.
Definition: X86Subtarget.h:123
bool hasFastPartialYMMorZMMWrite() const
Definition: X86Subtarget.h:499
bool LEAusesAG() const
Definition: X86Subtarget.h:512
bool has3DNow() const
Definition: X86Subtarget.h:455
bool hasRDSEED() const
Definition: X86Subtarget.h:486
Intel_OCL_BI - Calling conventions for Intel OpenCL built-ins.
Definition: CallingConv.h:140
bool HasSHA
Processor has SHA instructions.
Definition: X86Subtarget.h:177
bool HasBMI
Processor has BMI1 instructions.
Definition: X86Subtarget.h:159
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:572
bool hasVBMI() const
Definition: X86Subtarget.h:480
EnvironmentType getEnvironment() const
getEnvironment - Get the parsed environment type of this triple.
Definition: Triple.h:303
bool isTargetWin32() const
Definition: X86Subtarget.h:594
bool hasXSAVEC() const
Definition: X86Subtarget.h:462
bool HasVBMI
Processor has VBMI instructions.
Definition: X86Subtarget.h:165
bool isTargetAndroid() const
Definition: X86Subtarget.h:557
bool Slow3OpsLEA
True if the LEA instruction has all three source operands: base, index, and offset or if the LEA inst...
Definition: X86Subtarget.h:272
bool isOSFreeBSD() const
Definition: Triple.h:486
bool isTarget64BitILP32() const
Is this x86_64 with the ILP32 programming model (x32 ABI)?
Definition: X86Subtarget.h:426
bool hasFastScalarFSQRT() const
Definition: X86Subtarget.h:502
bool hasCLFLUSHOPT() const
Definition: X86Subtarget.h:525
bool hasIFMA() const
Definition: X86Subtarget.h:481
int getScatterOverhead() const
Definition: X86Subtarget.h:495
bool isOSCygMing() const
Tests for either Cygwin or MinGW OS.
Definition: Triple.h:551
bool UseSoftFloat
Use software floating point for code generation.
Definition: X86Subtarget.h:314
bool enableAdvancedRASplitCost() const override
Definition: X86Subtarget.h:677
bool hasAnyFMA() const
Definition: X86Subtarget.h:469
bool useSoftFloat() const
Definition: X86Subtarget.h:535
std::unique_ptr< RegisterBankInfo > RegBankInfo
Definition: X86Subtarget.h:333
std::unique_ptr< LegalizerInfo > Legalizer
Definition: X86Subtarget.h:332
bool hasRDRAND() const
Definition: X86Subtarget.h:474
bool HasPCLMUL
Target has carry-less multiplication.
Definition: X86Subtarget.h:126
bool hasLAHFSAHF() const
Definition: X86Subtarget.h:487
Provides the logic to select generic machine instructions.
bool is16Bit() const
Definition: X86Subtarget.h:421
bool isOSGlibc() const
Tests whether the OS uses glibc.
Definition: Triple.h:582
const X86SelectionDAGInfo * getSelectionDAGInfo() const override
Definition: X86Subtarget.h:377
bool isTargetDragonFly() const
Definition: X86Subtarget.h:546
bool HasXSAVEOPT
Target has XSAVEOPT instructions.
Definition: X86Subtarget.h:117
bool isPositionIndependent() const
bool HasMacroFusion
True if the processor supports macrofusion.
Definition: X86Subtarget.h:249
bool hasInt256() const
Definition: X86Subtarget.h:452
X86SSEEnum X86SSELevel
SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
Definition: X86Subtarget.h:86
The C convention as implemented on Windows/x86-64 and AArch64.
Definition: CallingConv.h:154
bool isTargetCOFF() const
Definition: X86Subtarget.h:551
bool isTargetFuchsia() const
Definition: X86Subtarget.h:562
bool HasXSAVE
Target has XSAVE instructions.
Definition: X86Subtarget.h:114
bool isTargetWindowsItanium() const
Definition: X86Subtarget.h:584
bool hasSlowDivide32() const
Definition: X86Subtarget.h:508
bool hasCDI() const
Definition: X86Subtarget.h:516
bool hasPFI() const
Definition: X86Subtarget.h:518
bool HasCMov
True if this processor has conditional move instructions (generally pentium pro+).
Definition: X86Subtarget.h:96
bool hasMOVBE() const
Definition: X86Subtarget.h:473
bool hasBMI() const
Definition: X86Subtarget.h:478
bool hasXSAVES() const
Definition: X86Subtarget.h:463
bool hasSSE1() const
Definition: X86Subtarget.h:442
bool isTargetLinux() const
Definition: X86Subtarget.h:554
bool HasFMA4
Target has 4-operand fused multiply-add.
Definition: X86Subtarget.h:132
This file describes how to lower LLVM calls to machine code calls.
bool HasRTM
Processor has RTM instructions.
Definition: X86Subtarget.h:171
bool isCallingConvWin64(CallingConv::ID CC) const
Definition: X86Subtarget.h:605
bool isSHLDSlow() const
Definition: X86Subtarget.h:490
PICStyles::Style getPICStyle() const
Definition: X86Subtarget.h:437
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:621
bool hasMacroFusion() const
Definition: X86Subtarget.h:506
bool isTargetWindowsCygwin() const
Definition: X86Subtarget.h:576
bool hasAVX512() const
Definition: X86Subtarget.h:450
bool hasSSE4A() const
Definition: X86Subtarget.h:453
bool HasXSAVEC
Target has XSAVEC instructions.
Definition: X86Subtarget.h:120
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:57
bool HasVLX
Processor has AVX-512 Vector Length eXtenstions.
Definition: X86Subtarget.h:296
bool HasFastLZCNT
True if LZCNT instruction is fast.
Definition: X86Subtarget.h:243
bool hasBWI() const
Definition: X86Subtarget.h:521
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
bool HasRDSEED
Processor has RDSEED instructions.
Definition: X86Subtarget.h:183
AntiDepBreakMode getAntiDepBreakMode() const override
Definition: X86Subtarget.h:673
unsigned stackAlignment
The minimum alignment known to hold of the stack frame on entry to the function and which must be mai...
Definition: X86Subtarget.h:318
bool isWindowsMSVCEnvironment() const
Checks if the environment could be MSVC.
Definition: Triple.h:523
Triple TargetTriple
What processor and OS we&#39;re targeting.
Definition: X86Subtarget.h:325
bool hasTBM() const
Definition: X86Subtarget.h:471
bool hasLZCNT() const
Definition: X86Subtarget.h:477
bool hasMFence() const
Use mfence if we have SSE2 or we&#39;re on x86-64 (even if we asked for no-sse2).
Definition: X86Subtarget.h:540
bool hasXSAVEOPT() const
Definition: X86Subtarget.h:461
bool HasMOVBE
True if the processor has the MOVBE instruction.
Definition: X86Subtarget.h:144
bool PadShortFunctions
True if the short functions should be padded to prevent a stall when returning too early...
Definition: X86Subtarget.h:256
bool HasCLZERO
Processor has Cache Line Zero instruction.
Definition: X86Subtarget.h:192
bool hasSSE2() const
Definition: X86Subtarget.h:443
X86_FastCall - &#39;fast&#39; analog of X86_StdCall.
Definition: CallingConv.h:92
bool hasRTM() const
Definition: X86Subtarget.h:482
bool hasFastVectorFSQRT() const
Definition: X86Subtarget.h:503
bool HasSlowDivide64
True if 32-bit divides are significantly faster than 64-bit divisions and should be used when possibl...
Definition: X86Subtarget.h:240
bool isTargetWindowsCoreCLR() const
Definition: X86Subtarget.h:572