LLVM  8.0.0svn
X86Subtarget.h
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1 //===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file declares the X86 specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_X86_X86SUBTARGET_H
15 #define LLVM_LIB_TARGET_X86_X86SUBTARGET_H
16 
17 #include "X86FrameLowering.h"
18 #include "X86ISelLowering.h"
19 #include "X86InstrInfo.h"
20 #include "X86SelectionDAGInfo.h"
21 #include "llvm/ADT/StringRef.h"
22 #include "llvm/ADT/Triple.h"
28 #include "llvm/IR/CallingConv.h"
30 #include <climits>
31 #include <memory>
32 
33 #define GET_SUBTARGETINFO_HEADER
34 #include "X86GenSubtargetInfo.inc"
35 
36 namespace llvm {
37 
38 class GlobalValue;
39 
40 /// The X86 backend supports a number of different styles of PIC.
41 ///
42 namespace PICStyles {
43 
44 enum Style {
45  StubPIC, // Used on i386-darwin in pic mode.
46  GOT, // Used on 32 bit elf on when in pic mode.
47  RIPRel, // Used on X86-64 when in pic mode.
48  None // Set when not in pic mode.
49 };
50 
51 } // end namespace PICStyles
52 
53 class X86Subtarget final : public X86GenSubtargetInfo {
54 public:
55  // NOTE: Do not add anything new to this list. Coarse, CPU name based flags
56  // are not a good idea. We should be migrating away from these.
65  };
66 
67 protected:
68  enum X86SSEEnum {
69  NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
70  };
71 
72  enum X863DNowEnum {
73  NoThreeDNow, MMX, ThreeDNow, ThreeDNowA
74  };
75 
76  /// X86 processor family: Intel Atom, and others
77  X86ProcFamilyEnum X86ProcFamily = Others;
78 
79  /// Which PIC style to use
81 
82  const TargetMachine &TM;
83 
84  /// SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
85  X86SSEEnum X86SSELevel = NoSSE;
86 
87  /// MMX, 3DNow, 3DNow Athlon, or none supported.
88  X863DNowEnum X863DNowLevel = NoThreeDNow;
89 
90  /// True if the processor supports X87 instructions.
91  bool HasX87 = false;
92 
93  /// True if this processor has NOPL instruction
94  /// (generally pentium pro+).
95  bool HasNOPL = false;
96 
97  /// True if this processor has conditional move instructions
98  /// (generally pentium pro+).
99  bool HasCMov = false;
100 
101  /// True if the processor supports X86-64 instructions.
102  bool HasX86_64 = false;
103 
104  /// True if the processor supports POPCNT.
105  bool HasPOPCNT = false;
106 
107  /// True if the processor supports SSE4A instructions.
108  bool HasSSE4A = false;
109 
110  /// Target has AES instructions
111  bool HasAES = false;
112  bool HasVAES = false;
113 
114  /// Target has FXSAVE/FXRESTOR instructions
115  bool HasFXSR = false;
116 
117  /// Target has XSAVE instructions
118  bool HasXSAVE = false;
119 
120  /// Target has XSAVEOPT instructions
121  bool HasXSAVEOPT = false;
122 
123  /// Target has XSAVEC instructions
124  bool HasXSAVEC = false;
125 
126  /// Target has XSAVES instructions
127  bool HasXSAVES = false;
128 
129  /// Target has carry-less multiplication
130  bool HasPCLMUL = false;
131  bool HasVPCLMULQDQ = false;
132 
133  /// Target has Galois Field Arithmetic instructions
134  bool HasGFNI = false;
135 
136  /// Target has 3-operand fused multiply-add
137  bool HasFMA = false;
138 
139  /// Target has 4-operand fused multiply-add
140  bool HasFMA4 = false;
141 
142  /// Target has XOP instructions
143  bool HasXOP = false;
144 
145  /// Target has TBM instructions.
146  bool HasTBM = false;
147 
148  /// Target has LWP instructions
149  bool HasLWP = false;
150 
151  /// True if the processor has the MOVBE instruction.
152  bool HasMOVBE = false;
153 
154  /// True if the processor has the RDRAND instruction.
155  bool HasRDRAND = false;
156 
157  /// Processor has 16-bit floating point conversion instructions.
158  bool HasF16C = false;
159 
160  /// Processor has FS/GS base insturctions.
161  bool HasFSGSBase = false;
162 
163  /// Processor has LZCNT instruction.
164  bool HasLZCNT = false;
165 
166  /// Processor has BMI1 instructions.
167  bool HasBMI = false;
168 
169  /// Processor has BMI2 instructions.
170  bool HasBMI2 = false;
171 
172  /// Processor has VBMI instructions.
173  bool HasVBMI = false;
174 
175  /// Processor has VBMI2 instructions.
176  bool HasVBMI2 = false;
177 
178  /// Processor has Integer Fused Multiply Add
179  bool HasIFMA = false;
180 
181  /// Processor has RTM instructions.
182  bool HasRTM = false;
183 
184  /// Processor has ADX instructions.
185  bool HasADX = false;
186 
187  /// Processor has SHA instructions.
188  bool HasSHA = false;
189 
190  /// Processor has PRFCHW instructions.
191  bool HasPRFCHW = false;
192 
193  /// Processor has RDSEED instructions.
194  bool HasRDSEED = false;
195 
196  /// Processor has LAHF/SAHF instructions.
197  bool HasLAHFSAHF = false;
198 
199  /// Processor has MONITORX/MWAITX instructions.
200  bool HasMWAITX = false;
201 
202  /// Processor has Cache Line Zero instruction
203  bool HasCLZERO = false;
204 
205  /// Processor has Cache Line Demote instruction
206  bool HasCLDEMOTE = false;
207 
208  /// Processor has MOVDIRI instruction (direct store integer).
209  bool HasMOVDIRI = false;
210 
211  /// Processor has MOVDIR64B instruction (direct store 64 bytes).
212  bool HasMOVDIR64B = false;
213 
214  /// Processor has ptwrite instruction.
215  bool HasPTWRITE = false;
216 
217  /// Processor has Prefetch with intent to Write instruction
218  bool HasPREFETCHWT1 = false;
219 
220  /// True if SHLD instructions are slow.
221  bool IsSHLDSlow = false;
222 
223  /// True if the PMULLD instruction is slow compared to PMULLW/PMULHW and
224  // PMULUDQ.
225  bool IsPMULLDSlow = false;
226 
227  /// True if unaligned memory accesses of 16-bytes are slow.
228  bool IsUAMem16Slow = false;
229 
230  /// True if unaligned memory accesses of 32-bytes are slow.
231  bool IsUAMem32Slow = false;
232 
233  /// True if SSE operations can have unaligned memory operands.
234  /// This may require setting a configuration bit in the processor.
235  bool HasSSEUnalignedMem = false;
236 
237  /// True if this processor has the CMPXCHG16B instruction;
238  /// this is true for most x86-64 chips, but not the first AMD chips.
239  bool HasCmpxchg16b = false;
240 
241  /// True if the LEA instruction should be used for adjusting
242  /// the stack pointer. This is an optimization for Intel Atom processors.
243  bool UseLeaForSP = false;
244 
245  /// True if POPCNT instruction has a false dependency on the destination register.
246  bool HasPOPCNTFalseDeps = false;
247 
248  /// True if LZCNT/TZCNT instructions have a false dependency on the destination register.
249  bool HasLZCNTFalseDeps = false;
250 
251  /// True if its preferable to combine to a single shuffle using a variable
252  /// mask over multiple fixed shuffles.
253  bool HasFastVariableShuffle = false;
254 
255  /// True if there is no performance penalty to writing only the lower parts
256  /// of a YMM or ZMM register without clearing the upper part.
257  bool HasFastPartialYMMorZMMWrite = false;
258 
259  /// True if there is no performance penalty for writing NOPs with up to
260  /// 11 bytes.
261  bool HasFast11ByteNOP = false;
262 
263  /// True if there is no performance penalty for writing NOPs with up to
264  /// 15 bytes.
265  bool HasFast15ByteNOP = false;
266 
267  /// True if gather is reasonably fast. This is true for Skylake client and
268  /// all AVX-512 CPUs.
269  bool HasFastGather = false;
270 
271  /// True if hardware SQRTSS instruction is at least as fast (latency) as
272  /// RSQRTSS followed by a Newton-Raphson iteration.
273  bool HasFastScalarFSQRT = false;
274 
275  /// True if hardware SQRTPS/VSQRTPS instructions are at least as fast
276  /// (throughput) as RSQRTPS/VRSQRTPS followed by a Newton-Raphson iteration.
277  bool HasFastVectorFSQRT = false;
278 
279  /// True if 8-bit divisions are significantly faster than
280  /// 32-bit divisions and should be used when possible.
281  bool HasSlowDivide32 = false;
282 
283  /// True if 32-bit divides are significantly faster than
284  /// 64-bit divisions and should be used when possible.
285  bool HasSlowDivide64 = false;
286 
287  /// True if LZCNT instruction is fast.
288  bool HasFastLZCNT = false;
289 
290  /// True if SHLD based rotate is fast.
291  bool HasFastSHLDRotate = false;
292 
293  /// True if the processor supports macrofusion.
294  bool HasMacroFusion = false;
295 
296  /// True if the processor has enhanced REP MOVSB/STOSB.
297  bool HasERMSB = false;
298 
299  /// True if the short functions should be padded to prevent
300  /// a stall when returning too early.
301  bool PadShortFunctions = false;
302 
303  /// True if two memory operand instructions should use a temporary register
304  /// instead.
305  bool SlowTwoMemOps = false;
306 
307  /// True if the LEA instruction inputs have to be ready at address generation
308  /// (AG) time.
309  bool LEAUsesAG = false;
310 
311  /// True if the LEA instruction with certain arguments is slow
312  bool SlowLEA = false;
313 
314  /// True if the LEA instruction has all three source operands: base, index,
315  /// and offset or if the LEA instruction uses base and index registers where
316  /// the base is EBP, RBP,or R13
317  bool Slow3OpsLEA = false;
318 
319  /// True if INC and DEC instructions are slow when writing to flags
320  bool SlowIncDec = false;
321 
322  /// Processor has AVX-512 PreFetch Instructions
323  bool HasPFI = false;
324 
325  /// Processor has AVX-512 Exponential and Reciprocal Instructions
326  bool HasERI = false;
327 
328  /// Processor has AVX-512 Conflict Detection Instructions
329  bool HasCDI = false;
330 
331  /// Processor has AVX-512 population count Instructions
332  bool HasVPOPCNTDQ = false;
333 
334  /// Processor has AVX-512 Doubleword and Quadword instructions
335  bool HasDQI = false;
336 
337  /// Processor has AVX-512 Byte and Word instructions
338  bool HasBWI = false;
339 
340  /// Processor has AVX-512 Vector Length eXtenstions
341  bool HasVLX = false;
342 
343  /// Processor has PKU extenstions
344  bool HasPKU = false;
345 
346  /// Processor has AVX-512 Vector Neural Network Instructions
347  bool HasVNNI = false;
348 
349  /// Processor has AVX-512 Bit Algorithms instructions
350  bool HasBITALG = false;
351 
352  /// Processor supports MPX - Memory Protection Extensions
353  bool HasMPX = false;
354 
355  /// Processor supports CET SHSTK - Control-Flow Enforcement Technology
356  /// using Shadow Stack
357  bool HasSHSTK = false;
358 
359  /// Processor supports Invalidate Process-Context Identifier
360  bool HasINVPCID = false;
361 
362  /// Processor has Software Guard Extensions
363  bool HasSGX = false;
364 
365  /// Processor supports Flush Cache Line instruction
366  bool HasCLFLUSHOPT = false;
367 
368  /// Processor supports Cache Line Write Back instruction
369  bool HasCLWB = false;
370 
371  /// Processor supports Write Back No Invalidate instruction
372  bool HasWBNOINVD = false;
373 
374  /// Processor support RDPID instruction
375  bool HasRDPID = false;
376 
377  /// Processor supports WaitPKG instructions
378  bool HasWAITPKG = false;
379 
380  /// Processor supports PCONFIG instruction
381  bool HasPCONFIG = false;
382 
383  /// Processor has a single uop BEXTR implementation.
384  bool HasFastBEXTR = false;
385 
386  /// Try harder to combine to horizontal vector ops if they are fast.
387  bool HasFastHorizontalOps = false;
388 
389  /// Use a retpoline thunk rather than indirect calls to block speculative
390  /// execution.
391  bool UseRetpolineIndirectCalls = false;
392 
393  /// Use a retpoline thunk or remove any indirect branch to block speculative
394  /// execution.
395  bool UseRetpolineIndirectBranches = false;
396 
397  /// Deprecated flag, query `UseRetpolineIndirectCalls` and
398  /// `UseRetpolineIndirectBranches` instead.
399  bool DeprecatedUseRetpoline = false;
400 
401  /// When using a retpoline thunk, call an externally provided thunk rather
402  /// than emitting one inside the compiler.
403  bool UseRetpolineExternalThunk = false;
404 
405  /// Use software floating point for code generation.
406  bool UseSoftFloat = false;
407 
408  /// The minimum alignment known to hold of the stack frame on
409  /// entry to the function and which must be maintained by every function.
410  unsigned stackAlignment = 4;
411 
412  /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
413  ///
414  // FIXME: this is a known good value for Yonah. How about others?
415  unsigned MaxInlineSizeThreshold = 128;
416 
417  /// Indicates target prefers 256 bit instructions.
418  bool Prefer256Bit = false;
419 
420  /// Threeway branch is profitable in this subtarget.
421  bool ThreewayBranchProfitable = false;
422 
423  /// What processor and OS we're targeting.
425 
426  /// GlobalISel related APIs.
427  std::unique_ptr<CallLowering> CallLoweringInfo;
428  std::unique_ptr<LegalizerInfo> Legalizer;
429  std::unique_ptr<RegisterBankInfo> RegBankInfo;
430  std::unique_ptr<InstructionSelector> InstSelector;
431 
432 private:
433  /// Override the stack alignment.
434  unsigned StackAlignOverride;
435 
436  /// Preferred vector width from function attribute.
437  unsigned PreferVectorWidthOverride;
438 
439  /// Resolved preferred vector width from function attribute and subtarget
440  /// features.
441  unsigned PreferVectorWidth = UINT32_MAX;
442 
443  /// Required vector width from function attribute.
444  unsigned RequiredVectorWidth;
445 
446  /// True if compiling for 64-bit, false for 16-bit or 32-bit.
447  bool In64BitMode;
448 
449  /// True if compiling for 32-bit, false for 16-bit or 64-bit.
450  bool In32BitMode;
451 
452  /// True if compiling for 16-bit, false for 32-bit or 64-bit.
453  bool In16BitMode;
454 
455  /// Contains the Overhead of gather\scatter instructions
456  int GatherOverhead = 1024;
457  int ScatterOverhead = 1024;
458 
459  X86SelectionDAGInfo TSInfo;
460  // Ordering here is important. X86InstrInfo initializes X86RegisterInfo which
461  // X86TargetLowering needs.
462  X86InstrInfo InstrInfo;
463  X86TargetLowering TLInfo;
464  X86FrameLowering FrameLowering;
465 
466 public:
467  /// This constructor initializes the data members to match that
468  /// of the specified triple.
469  ///
470  X86Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
471  const X86TargetMachine &TM, unsigned StackAlignOverride,
472  unsigned PreferVectorWidthOverride,
473  unsigned RequiredVectorWidth);
474 
475  const X86TargetLowering *getTargetLowering() const override {
476  return &TLInfo;
477  }
478 
479  const X86InstrInfo *getInstrInfo() const override { return &InstrInfo; }
480 
481  const X86FrameLowering *getFrameLowering() const override {
482  return &FrameLowering;
483  }
484 
485  const X86SelectionDAGInfo *getSelectionDAGInfo() const override {
486  return &TSInfo;
487  }
488 
489  const X86RegisterInfo *getRegisterInfo() const override {
490  return &getInstrInfo()->getRegisterInfo();
491  }
492 
493  /// Returns the minimum alignment known to hold of the
494  /// stack frame on entry to the function and which must be maintained by every
495  /// function for this subtarget.
496  unsigned getStackAlignment() const { return stackAlignment; }
497 
498  /// Returns the maximum memset / memcpy size
499  /// that still makes it profitable to inline the call.
500  unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
501 
502  /// ParseSubtargetFeatures - Parses features string setting specified
503  /// subtarget options. Definition of function is auto generated by tblgen.
504  void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
505 
506  /// Methods used by Global ISel
507  const CallLowering *getCallLowering() const override;
508  const InstructionSelector *getInstructionSelector() const override;
509  const LegalizerInfo *getLegalizerInfo() const override;
510  const RegisterBankInfo *getRegBankInfo() const override;
511 
512 private:
513  /// Initialize the full set of dependencies so we can use an initializer
514  /// list for X86Subtarget.
515  X86Subtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
516  void initSubtargetFeatures(StringRef CPU, StringRef FS);
517 
518 public:
519  /// Is this x86_64? (disregarding specific ABI / programming model)
520  bool is64Bit() const {
521  return In64BitMode;
522  }
523 
524  bool is32Bit() const {
525  return In32BitMode;
526  }
527 
528  bool is16Bit() const {
529  return In16BitMode;
530  }
531 
532  /// Is this x86_64 with the ILP32 programming model (x32 ABI)?
533  bool isTarget64BitILP32() const {
534  return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32 ||
535  TargetTriple.isOSNaCl());
536  }
537 
538  /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
539  bool isTarget64BitLP64() const {
540  return In64BitMode && (TargetTriple.getEnvironment() != Triple::GNUX32 &&
541  !TargetTriple.isOSNaCl());
542  }
543 
544  PICStyles::Style getPICStyle() const { return PICStyle; }
545  void setPICStyle(PICStyles::Style Style) { PICStyle = Style; }
546 
547  bool hasX87() const { return HasX87; }
548  bool hasNOPL() const { return HasNOPL; }
549  // SSE codegen depends on cmovs, and all SSE1+ processors support them.
550  // All 64-bit processors support cmov.
551  bool hasCMov() const { return HasCMov || X86SSELevel >= SSE1 || is64Bit(); }
552  bool hasSSE1() const { return X86SSELevel >= SSE1; }
553  bool hasSSE2() const { return X86SSELevel >= SSE2; }
554  bool hasSSE3() const { return X86SSELevel >= SSE3; }
555  bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
556  bool hasSSE41() const { return X86SSELevel >= SSE41; }
557  bool hasSSE42() const { return X86SSELevel >= SSE42; }
558  bool hasAVX() const { return X86SSELevel >= AVX; }
559  bool hasAVX2() const { return X86SSELevel >= AVX2; }
560  bool hasAVX512() const { return X86SSELevel >= AVX512F; }
561  bool hasInt256() const { return hasAVX2(); }
562  bool hasSSE4A() const { return HasSSE4A; }
563  bool hasMMX() const { return X863DNowLevel >= MMX; }
564  bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
565  bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
566  bool hasPOPCNT() const { return HasPOPCNT; }
567  bool hasAES() const { return HasAES; }
568  bool hasVAES() const { return HasVAES; }
569  bool hasFXSR() const { return HasFXSR; }
570  bool hasXSAVE() const { return HasXSAVE; }
571  bool hasXSAVEOPT() const { return HasXSAVEOPT; }
572  bool hasXSAVEC() const { return HasXSAVEC; }
573  bool hasXSAVES() const { return HasXSAVES; }
574  bool hasPCLMUL() const { return HasPCLMUL; }
575  bool hasVPCLMULQDQ() const { return HasVPCLMULQDQ; }
576  bool hasGFNI() const { return HasGFNI; }
577  // Prefer FMA4 to FMA - its better for commutation/memory folding and
578  // has equal or better performance on all supported targets.
579  bool hasFMA() const { return HasFMA; }
580  bool hasFMA4() const { return HasFMA4; }
581  bool hasAnyFMA() const { return hasFMA() || hasFMA4(); }
582  bool hasXOP() const { return HasXOP; }
583  bool hasTBM() const { return HasTBM; }
584  bool hasLWP() const { return HasLWP; }
585  bool hasMOVBE() const { return HasMOVBE; }
586  bool hasRDRAND() const { return HasRDRAND; }
587  bool hasF16C() const { return HasF16C; }
588  bool hasFSGSBase() const { return HasFSGSBase; }
589  bool hasLZCNT() const { return HasLZCNT; }
590  bool hasBMI() const { return HasBMI; }
591  bool hasBMI2() const { return HasBMI2; }
592  bool hasVBMI() const { return HasVBMI; }
593  bool hasVBMI2() const { return HasVBMI2; }
594  bool hasIFMA() const { return HasIFMA; }
595  bool hasRTM() const { return HasRTM; }
596  bool hasADX() const { return HasADX; }
597  bool hasSHA() const { return HasSHA; }
598  bool hasPRFCHW() const { return HasPRFCHW || HasPREFETCHWT1; }
599  bool hasPREFETCHWT1() const { return HasPREFETCHWT1; }
600  bool hasSSEPrefetch() const {
601  // We implicitly enable these when we have a write prefix supporting cache
602  // level OR if we have prfchw, but don't already have a read prefetch from
603  // 3dnow.
604  return hasSSE1() || (hasPRFCHW() && !has3DNow()) || hasPREFETCHWT1();
605  }
606  bool hasRDSEED() const { return HasRDSEED; }
607  bool hasLAHFSAHF() const { return HasLAHFSAHF; }
608  bool hasMWAITX() const { return HasMWAITX; }
609  bool hasCLZERO() const { return HasCLZERO; }
610  bool hasCLDEMOTE() const { return HasCLDEMOTE; }
611  bool hasMOVDIRI() const { return HasMOVDIRI; }
612  bool hasMOVDIR64B() const { return HasMOVDIR64B; }
613  bool hasPTWRITE() const { return HasPTWRITE; }
614  bool isSHLDSlow() const { return IsSHLDSlow; }
615  bool isPMULLDSlow() const { return IsPMULLDSlow; }
616  bool isUnalignedMem16Slow() const { return IsUAMem16Slow; }
617  bool isUnalignedMem32Slow() const { return IsUAMem32Slow; }
618  int getGatherOverhead() const { return GatherOverhead; }
619  int getScatterOverhead() const { return ScatterOverhead; }
620  bool hasSSEUnalignedMem() const { return HasSSEUnalignedMem; }
621  bool hasCmpxchg16b() const { return HasCmpxchg16b; }
622  bool useLeaForSP() const { return UseLeaForSP; }
623  bool hasPOPCNTFalseDeps() const { return HasPOPCNTFalseDeps; }
624  bool hasLZCNTFalseDeps() const { return HasLZCNTFalseDeps; }
625  bool hasFastVariableShuffle() const {
626  return HasFastVariableShuffle;
627  }
629  return HasFastPartialYMMorZMMWrite;
630  }
631  bool hasFastGather() const { return HasFastGather; }
632  bool hasFastScalarFSQRT() const { return HasFastScalarFSQRT; }
633  bool hasFastVectorFSQRT() const { return HasFastVectorFSQRT; }
634  bool hasFastLZCNT() const { return HasFastLZCNT; }
635  bool hasFastSHLDRotate() const { return HasFastSHLDRotate; }
636  bool hasFastBEXTR() const { return HasFastBEXTR; }
637  bool hasFastHorizontalOps() const { return HasFastHorizontalOps; }
638  bool hasMacroFusion() const { return HasMacroFusion; }
639  bool hasERMSB() const { return HasERMSB; }
640  bool hasSlowDivide32() const { return HasSlowDivide32; }
641  bool hasSlowDivide64() const { return HasSlowDivide64; }
642  bool padShortFunctions() const { return PadShortFunctions; }
643  bool slowTwoMemOps() const { return SlowTwoMemOps; }
644  bool LEAusesAG() const { return LEAUsesAG; }
645  bool slowLEA() const { return SlowLEA; }
646  bool slow3OpsLEA() const { return Slow3OpsLEA; }
647  bool slowIncDec() const { return SlowIncDec; }
648  bool hasCDI() const { return HasCDI; }
649  bool hasVPOPCNTDQ() const { return HasVPOPCNTDQ; }
650  bool hasPFI() const { return HasPFI; }
651  bool hasERI() const { return HasERI; }
652  bool hasDQI() const { return HasDQI; }
653  bool hasBWI() const { return HasBWI; }
654  bool hasVLX() const { return HasVLX; }
655  bool hasPKU() const { return HasPKU; }
656  bool hasVNNI() const { return HasVNNI; }
657  bool hasBITALG() const { return HasBITALG; }
658  bool hasMPX() const { return HasMPX; }
659  bool hasSHSTK() const { return HasSHSTK; }
660  bool hasCLFLUSHOPT() const { return HasCLFLUSHOPT; }
661  bool hasCLWB() const { return HasCLWB; }
662  bool hasWBNOINVD() const { return HasWBNOINVD; }
663  bool hasRDPID() const { return HasRDPID; }
664  bool hasWAITPKG() const { return HasWAITPKG; }
665  bool hasPCONFIG() const { return HasPCONFIG; }
666  bool hasSGX() const { return HasSGX; }
667  bool threewayBranchProfitable() const { return ThreewayBranchProfitable; }
668  bool hasINVPCID() const { return HasINVPCID; }
669  bool useRetpolineIndirectCalls() const { return UseRetpolineIndirectCalls; }
671  return UseRetpolineIndirectBranches;
672  }
673  bool useRetpolineExternalThunk() const { return UseRetpolineExternalThunk; }
674 
675  unsigned getPreferVectorWidth() const { return PreferVectorWidth; }
676  unsigned getRequiredVectorWidth() const { return RequiredVectorWidth; }
677 
678  // Helper functions to determine when we should allow widening to 512-bit
679  // during codegen.
680  // TODO: Currently we're always allowing widening on CPUs without VLX,
681  // because for many cases we don't have a better option.
682  bool canExtendTo512DQ() const {
683  return hasAVX512() && (!hasVLX() || getPreferVectorWidth() >= 512);
684  }
685  bool canExtendTo512BW() const {
686  return hasBWI() && canExtendTo512DQ();
687  }
688 
689  // If there are no 512-bit vectors and we prefer not to use 512-bit registers,
690  // disable them in the legalizer.
691  bool useAVX512Regs() const {
692  return hasAVX512() && (canExtendTo512DQ() || RequiredVectorWidth > 256);
693  }
694 
695  bool useBWIRegs() const {
696  return hasBWI() && useAVX512Regs();
697  }
698 
699  bool isXRaySupported() const override { return is64Bit(); }
700 
701  X86ProcFamilyEnum getProcFamily() const { return X86ProcFamily; }
702 
703  /// TODO: to be removed later and replaced with suitable properties
704  bool isAtom() const { return X86ProcFamily == IntelAtom; }
705  bool isSLM() const { return X86ProcFamily == IntelSLM; }
706  bool isGLM() const {
707  return X86ProcFamily == IntelGLM ||
708  X86ProcFamily == IntelGLP ||
709  X86ProcFamily == IntelTRM;
710  }
711  bool useSoftFloat() const { return UseSoftFloat; }
712 
713  /// Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
714  /// no-sse2). There isn't any reason to disable it if the target processor
715  /// supports it.
716  bool hasMFence() const { return hasSSE2() || is64Bit(); }
717 
718  const Triple &getTargetTriple() const { return TargetTriple; }
719 
720  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
721  bool isTargetFreeBSD() const { return TargetTriple.isOSFreeBSD(); }
722  bool isTargetDragonFly() const { return TargetTriple.isOSDragonFly(); }
723  bool isTargetSolaris() const { return TargetTriple.isOSSolaris(); }
724  bool isTargetPS4() const { return TargetTriple.isPS4CPU(); }
725 
726  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
727  bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
728  bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
729 
730  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
731  bool isTargetKFreeBSD() const { return TargetTriple.isOSKFreeBSD(); }
732  bool isTargetGlibc() const { return TargetTriple.isOSGlibc(); }
733  bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
734  bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
735  bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
736  bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
737  bool isTargetMCU() const { return TargetTriple.isOSIAMCU(); }
738  bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
739 
740  bool isTargetWindowsMSVC() const {
741  return TargetTriple.isWindowsMSVCEnvironment();
742  }
743 
745  return TargetTriple.isKnownWindowsMSVCEnvironment();
746  }
747 
748  bool isTargetWindowsCoreCLR() const {
749  return TargetTriple.isWindowsCoreCLREnvironment();
750  }
751 
752  bool isTargetWindowsCygwin() const {
753  return TargetTriple.isWindowsCygwinEnvironment();
754  }
755 
756  bool isTargetWindowsGNU() const {
757  return TargetTriple.isWindowsGNUEnvironment();
758  }
759 
760  bool isTargetWindowsItanium() const {
761  return TargetTriple.isWindowsItaniumEnvironment();
762  }
763 
764  bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
765 
766  bool isOSWindows() const { return TargetTriple.isOSWindows(); }
767 
768  bool isTargetWin64() const { return In64BitMode && isOSWindows(); }
769 
770  bool isTargetWin32() const { return !In64BitMode && isOSWindows(); }
771 
772  bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
773  bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
774 
775  bool isPICStyleStubPIC() const {
776  return PICStyle == PICStyles::StubPIC;
777  }
778 
779  bool isPositionIndependent() const { return TM.isPositionIndependent(); }
780 
782  switch (CC) {
783  // On Win64, all these conventions just use the default convention.
784  case CallingConv::C:
785  case CallingConv::Fast:
786  case CallingConv::Swift:
792  return isTargetWin64();
793  // This convention allows using the Win64 convention on other targets.
794  case CallingConv::Win64:
795  return true;
796  // This convention allows using the SysV convention on Windows targets.
798  return false;
799  // Otherwise, who knows what this is.
800  default:
801  return false;
802  }
803  }
804 
805  /// Classify a global variable reference for the current subtarget according
806  /// to how we should reference it in a non-pcrel context.
807  unsigned char classifyLocalReference(const GlobalValue *GV) const;
808 
809  unsigned char classifyGlobalReference(const GlobalValue *GV,
810  const Module &M) const;
811  unsigned char classifyGlobalReference(const GlobalValue *GV) const;
812 
813  /// Classify a global function reference for the current subtarget.
814  unsigned char classifyGlobalFunctionReference(const GlobalValue *GV,
815  const Module &M) const;
816  unsigned char classifyGlobalFunctionReference(const GlobalValue *GV) const;
817 
818  /// Classify a blockaddress reference for the current subtarget according to
819  /// how we should reference it in a non-pcrel context.
820  unsigned char classifyBlockAddressReference() const;
821 
822  /// Return true if the subtarget allows calls to immediate address.
823  bool isLegalToCallImmediateAddr() const;
824 
825  /// If we are using retpolines, we need to expand indirectbr to avoid it
826  /// lowering to an actual indirect jump.
827  bool enableIndirectBrExpand() const override {
828  return useRetpolineIndirectBranches();
829  }
830 
831  /// Enable the MachineScheduler pass for all X86 subtargets.
832  bool enableMachineScheduler() const override { return true; }
833 
834  // TODO: Update the regression tests and return true.
835  bool supportPrintSchedInfo() const override { return false; }
836 
837  bool enableEarlyIfConversion() const override;
838 
839  AntiDepBreakMode getAntiDepBreakMode() const override {
840  return TargetSubtargetInfo::ANTIDEP_CRITICAL;
841  }
842 
843  bool enableAdvancedRASplitCost() const override { return true; }
844 };
845 
846 } // end namespace llvm
847 
848 #endif // LLVM_LIB_TARGET_X86_X86SUBTARGET_H
bool hasAVX() const
Definition: X86Subtarget.h:558
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:474
bool isTargetPS4() const
Definition: X86Subtarget.h:724
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:520
bool hasSHA() const
Definition: X86Subtarget.h:597
bool supportPrintSchedInfo() const override
Definition: X86Subtarget.h:835
bool hasSSE41() const
Definition: X86Subtarget.h:556
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool hasSSEPrefetch() const
Definition: X86Subtarget.h:600
ThreeDNow - This indicates that the instruction uses the wacky 0x0F 0x0F prefix for 3DNow! instructio...
Definition: X86BaseInfo.h:445
bool isOSWindows() const
Definition: X86Subtarget.h:766
bool hasPOPCNT() const
Definition: X86Subtarget.h:566
bool hasAVX2() const
Definition: X86Subtarget.h:559
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:64
bool hasFMA() const
Definition: X86Subtarget.h:579
bool hasWBNOINVD() const
Definition: X86Subtarget.h:662
bool hasSlowDivide64() const
Definition: X86Subtarget.h:641
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:592
bool hasRDPID() const
Definition: X86Subtarget.h:663
bool hasSGX() const
Definition: X86Subtarget.h:666
const X86InstrInfo * getInstrInfo() const override
Definition: X86Subtarget.h:479
bool hasCLWB() const
Definition: X86Subtarget.h:661
bool slowLEA() const
Definition: X86Subtarget.h:645
const X86FrameLowering * getFrameLowering() const override
Definition: X86Subtarget.h:481
MSVC calling convention that passes vectors and vector aggregates in SSE registers.
Definition: CallingConv.h:158
void setPICStyle(PICStyles::Style Style)
Definition: X86Subtarget.h:545
const TargetMachine & TM
Definition: X86Subtarget.h:82
bool enableMachineScheduler() const override
Enable the MachineScheduler pass for all X86 subtargets.
Definition: X86Subtarget.h:832
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
Definition: Triple.h:571
bool hasFastBEXTR() const
Definition: X86Subtarget.h:636
bool hasVBMI2() const
Definition: X86Subtarget.h:593
bool hasCLZERO() const
Definition: X86Subtarget.h:609
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:43
bool has3DNowA() const
Definition: X86Subtarget.h:565
bool useAVX512Regs() const
Definition: X86Subtarget.h:691
bool isOSFuchsia() const
Definition: Triple.h:494
X86_StdCall - stdcall is the calling conventions mostly used by the Win32 API.
Definition: CallingConv.h:87
Intel_OCL_BI - Calling conventions for Intel OpenCL built-ins.
Definition: CallingConv.h:140
bool isTargetNaCl64() const
Definition: X86Subtarget.h:736
bool isWindowsCygwinEnvironment() const
Definition: Triple.h:546
bool isTargetKnownWindowsMSVC() const
Definition: X86Subtarget.h:744
bool slowTwoMemOps() const
Definition: X86Subtarget.h:643
bool hasPCONFIG() const
Definition: X86Subtarget.h:665
bool hasSHSTK() const
Definition: X86Subtarget.h:659
bool isTargetWindowsMSVC() const
Definition: X86Subtarget.h:740
bool isTargetMachO() const
Definition: X86Subtarget.h:728
int getGatherOverhead() const
Definition: X86Subtarget.h:618
bool hasXSAVE() const
Definition: X86Subtarget.h:570
bool isUnalignedMem32Slow() const
Definition: X86Subtarget.h:617
bool isPICStyleStubPIC() const
Definition: X86Subtarget.h:775
bool hasVPOPCNTDQ() const
Definition: X86Subtarget.h:649
bool hasPREFETCHWT1() const
Definition: X86Subtarget.h:599
Holds all the information related to register banks.
bool hasLWP() const
Definition: X86Subtarget.h:584
bool isPICStyleRIPRel() const
Definition: X86Subtarget.h:773
bool hasFMA4() const
Definition: X86Subtarget.h:580
bool padShortFunctions() const
Definition: X86Subtarget.h:642
bool isTargetSolaris() const
Definition: X86Subtarget.h:723
X86_FastCall - &#39;fast&#39; analog of X86_StdCall.
Definition: CallingConv.h:92
bool hasAES() const
Definition: X86Subtarget.h:567
bool isTarget64BitLP64() const
Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
Definition: X86Subtarget.h:539
bool isKnownWindowsMSVCEnvironment() const
Checks if the environment is MSVC.
Definition: Triple.h:534
bool hasPKU() const
Definition: X86Subtarget.h:655
bool is32Bit() const
Definition: X86Subtarget.h:524
bool canExtendTo512DQ() const
Definition: X86Subtarget.h:682
bool hasCmpxchg16b() const
Definition: X86Subtarget.h:621
bool hasFastLZCNT() const
Definition: X86Subtarget.h:634
bool useRetpolineExternalThunk() const
Definition: X86Subtarget.h:673
bool isOSSolaris() const
Definition: Triple.h:500
bool hasVLX() const
Definition: X86Subtarget.h:654
bool slow3OpsLEA() const
Definition: X86Subtarget.h:646
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
Definition: X86Subtarget.h:427
bool hasFastSHLDRotate() const
Definition: X86Subtarget.h:635
bool isTargetNaCl() const
Definition: X86Subtarget.h:734
bool hasNOPL() const
Definition: X86Subtarget.h:548
bool isTargetCygMing() const
Definition: X86Subtarget.h:764
bool hasMOVDIRI() const
Definition: X86Subtarget.h:611
bool hasMPX() const
Definition: X86Subtarget.h:658
bool hasINVPCID() const
Definition: X86Subtarget.h:668
bool hasFastHorizontalOps() const
Definition: X86Subtarget.h:637
bool isWindowsItaniumEnvironment() const
Definition: Triple.h:542
bool isWindowsGNUEnvironment() const
Definition: Triple.h:550
bool hasFSGSBase() const
Definition: X86Subtarget.h:588
bool hasFastVariableShuffle() const
Definition: X86Subtarget.h:625
bool hasDQI() const
Definition: X86Subtarget.h:652
bool isWindowsCoreCLREnvironment() const
Definition: Triple.h:538
bool isOSDragonFly() const
Definition: Triple.h:498
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:566
const X86TargetLowering * getTargetLowering() const override
Definition: X86Subtarget.h:475
bool hasADX() const
Definition: X86Subtarget.h:596
bool isSLM() const
Definition: X86Subtarget.h:705
bool hasSSSE3() const
Definition: X86Subtarget.h:555
bool isTargetKFreeBSD() const
Definition: X86Subtarget.h:731
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:597
unsigned getStackAlignment() const
Returns the minimum alignment known to hold of the stack frame on entry to the function and which mus...
Definition: X86Subtarget.h:496
bool hasCLDEMOTE() const
Definition: X86Subtarget.h:610
bool hasGFNI() const
Definition: X86Subtarget.h:576
bool isTargetNaCl32() const
Definition: X86Subtarget.h:735
static bool is64Bit(const char *name)
bool isXRaySupported() const override
Definition: X86Subtarget.h:699
bool hasERMSB() const
Definition: X86Subtarget.h:639
bool hasMWAITX() const
Definition: X86Subtarget.h:608
bool hasSSEUnalignedMem() const
Definition: X86Subtarget.h:620
bool hasF16C() const
Definition: X86Subtarget.h:587
bool hasERI() const
Definition: X86Subtarget.h:651
bool hasPCLMUL() const
Definition: X86Subtarget.h:574
bool useLeaForSP() const
Definition: X86Subtarget.h:622
bool hasMMX() const
Definition: X86Subtarget.h:563
bool hasFXSR() const
Definition: X86Subtarget.h:569
bool isTargetWindowsGNU() const
Definition: X86Subtarget.h:756
bool isPS4CPU() const
Tests whether the target is the PS4 CPU.
Definition: Triple.h:612
bool isTargetFreeBSD() const
Definition: X86Subtarget.h:721
PICStyles::Style PICStyle
Which PIC style to use.
Definition: X86Subtarget.h:80
bool isOSKFreeBSD() const
Tests whether the OS is kFreeBSD.
Definition: Triple.h:581
The C convention as specified in the x86-64 supplement to the System V ABI, used on most non-Windows ...
Definition: CallingConv.h:144
bool isPositionIndependent() const
Definition: X86Subtarget.h:779
bool hasCMov() const
Definition: X86Subtarget.h:551
bool isTargetGlibc() const
Definition: X86Subtarget.h:732
X86ProcFamilyEnum getProcFamily() const
Definition: X86Subtarget.h:701
const Triple & getTargetTriple() const
Definition: X86Subtarget.h:718
bool hasVNNI() const
Definition: X86Subtarget.h:656
bool hasXOP() const
Definition: X86Subtarget.h:582
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:602
bool isTargetDarwin() const
Definition: X86Subtarget.h:720
bool hasSSE42() const
Definition: X86Subtarget.h:557
bool hasX87() const
Definition: X86Subtarget.h:547
bool isTargetMCU() const
Definition: X86Subtarget.h:737
bool isPMULLDSlow() const
Definition: X86Subtarget.h:615
bool useRetpolineIndirectCalls() const
Definition: X86Subtarget.h:669
bool hasPRFCHW() const
Definition: X86Subtarget.h:598
bool isTargetWin64() const
Definition: X86Subtarget.h:768
The C convention as implemented on Windows/x86-64 and AArch64.
Definition: CallingConv.h:154
bool hasSSE3() const
Definition: X86Subtarget.h:554
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool slowIncDec() const
Definition: X86Subtarget.h:647
bool hasBMI2() const
Definition: X86Subtarget.h:591
bool hasVPCLMULQDQ() const
Definition: X86Subtarget.h:575
bool isTargetELF() const
Definition: X86Subtarget.h:726
bool isOSIAMCU() const
Definition: Triple.h:504
const X86RegisterInfo * getRegisterInfo() const override
Definition: X86Subtarget.h:489
std::unique_ptr< InstructionSelector > InstSelector
Definition: X86Subtarget.h:430
bool isUnalignedMem16Slow() const
Definition: X86Subtarget.h:616
bool isAtom() const
TODO: to be removed later and replaced with suitable properties.
Definition: X86Subtarget.h:704
unsigned getMaxInlineSizeThreshold() const
Returns the maximum memset / memcpy size that still makes it profitable to inline the call...
Definition: X86Subtarget.h:500
bool isPICStyleGOT() const
Definition: X86Subtarget.h:772
bool hasMOVDIR64B() const
Definition: X86Subtarget.h:612
bool threewayBranchProfitable() const
Definition: X86Subtarget.h:667
bool hasFastPartialYMMorZMMWrite() const
Definition: X86Subtarget.h:628
bool LEAusesAG() const
Definition: X86Subtarget.h:644
bool has3DNow() const
Definition: X86Subtarget.h:564
bool hasRDSEED() const
Definition: X86Subtarget.h:606
unsigned getPreferVectorWidth() const
Definition: X86Subtarget.h:675
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:576
bool hasVBMI() const
Definition: X86Subtarget.h:592
bool hasBITALG() const
Definition: X86Subtarget.h:657
EnvironmentType getEnvironment() const
getEnvironment - Get the parsed environment type of this triple.
Definition: Triple.h:307
bool isTargetWin32() const
Definition: X86Subtarget.h:770
bool hasXSAVEC() const
Definition: X86Subtarget.h:572
bool isTargetAndroid() const
Definition: X86Subtarget.h:733
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:35
bool isOSFreeBSD() const
Definition: Triple.h:490
bool canExtendTo512BW() const
Definition: X86Subtarget.h:685
bool isTarget64BitILP32() const
Is this x86_64 with the ILP32 programming model (x32 ABI)?
Definition: X86Subtarget.h:533
bool hasFastScalarFSQRT() const
Definition: X86Subtarget.h:632
bool hasCLFLUSHOPT() const
Definition: X86Subtarget.h:660
bool hasPOPCNTFalseDeps() const
Definition: X86Subtarget.h:623
bool hasIFMA() const
Definition: X86Subtarget.h:594
int getScatterOverhead() const
Definition: X86Subtarget.h:619
bool isOSCygMing() const
Tests for either Cygwin or MinGW OS.
Definition: Triple.h:555
bool enableAdvancedRASplitCost() const override
Definition: X86Subtarget.h:843
bool hasAnyFMA() const
Definition: X86Subtarget.h:581
bool useSoftFloat() const
Definition: X86Subtarget.h:711
std::unique_ptr< RegisterBankInfo > RegBankInfo
Definition: X86Subtarget.h:429
bool useRetpolineIndirectBranches() const
Definition: X86Subtarget.h:670
std::unique_ptr< LegalizerInfo > Legalizer
Definition: X86Subtarget.h:428
bool enableIndirectBrExpand() const override
If we are using retpolines, we need to expand indirectbr to avoid it lowering to an actual indirect j...
Definition: X86Subtarget.h:827
bool hasRDRAND() const
Definition: X86Subtarget.h:586
bool hasLAHFSAHF() const
Definition: X86Subtarget.h:607
Provides the logic to select generic machine instructions.
bool is16Bit() const
Definition: X86Subtarget.h:528
bool hasVAES() const
Definition: X86Subtarget.h:568
bool isOSGlibc() const
Tests whether the OS uses glibc.
Definition: Triple.h:586
unsigned getRequiredVectorWidth() const
Definition: X86Subtarget.h:676
bool hasPTWRITE() const
Definition: X86Subtarget.h:613
bool useBWIRegs() const
Definition: X86Subtarget.h:695
const X86SelectionDAGInfo * getSelectionDAGInfo() const override
Definition: X86Subtarget.h:485
bool isTargetDragonFly() const
Definition: X86Subtarget.h:722
bool isPositionIndependent() const
bool isGLM() const
Definition: X86Subtarget.h:706
bool hasInt256() const
Definition: X86Subtarget.h:561
X86_ThisCall - Similar to X86_StdCall.
Definition: CallingConv.h:111
bool isTargetCOFF() const
Definition: X86Subtarget.h:727
bool isTargetFuchsia() const
Definition: X86Subtarget.h:738
bool isTargetWindowsItanium() const
Definition: X86Subtarget.h:760
bool hasSlowDivide32() const
Definition: X86Subtarget.h:640
bool hasCDI() const
Definition: X86Subtarget.h:648
bool hasPFI() const
Definition: X86Subtarget.h:650
bool hasMOVBE() const
Definition: X86Subtarget.h:585
bool hasBMI() const
Definition: X86Subtarget.h:590
bool hasXSAVES() const
Definition: X86Subtarget.h:573
bool hasSSE1() const
Definition: X86Subtarget.h:552
bool isTargetLinux() const
Definition: X86Subtarget.h:730
This file describes how to lower LLVM calls to machine code calls.
bool isCallingConvWin64(CallingConv::ID CC) const
Definition: X86Subtarget.h:781
bool isSHLDSlow() const
Definition: X86Subtarget.h:614
PICStyles::Style getPICStyle() const
Definition: X86Subtarget.h:544
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:625
bool hasMacroFusion() const
Definition: X86Subtarget.h:638
bool isTargetWindowsCygwin() const
Definition: X86Subtarget.h:752
bool hasAVX512() const
Definition: X86Subtarget.h:560
bool hasSSE4A() const
Definition: X86Subtarget.h:562
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:59
bool hasBWI() const
Definition: X86Subtarget.h:653
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
AntiDepBreakMode getAntiDepBreakMode() const override
Definition: X86Subtarget.h:839
bool hasFastGather() const
Definition: X86Subtarget.h:631
bool isWindowsMSVCEnvironment() const
Checks if the environment could be MSVC.
Definition: Triple.h:527
Triple TargetTriple
What processor and OS we&#39;re targeting.
Definition: X86Subtarget.h:424
bool hasTBM() const
Definition: X86Subtarget.h:583
bool hasWAITPKG() const
Definition: X86Subtarget.h:664
bool hasLZCNT() const
Definition: X86Subtarget.h:589
bool hasMFence() const
Use mfence if we have SSE2 or we&#39;re on x86-64 (even if we asked for no-sse2).
Definition: X86Subtarget.h:716
bool hasXSAVEOPT() const
Definition: X86Subtarget.h:571
bool hasSSE2() const
Definition: X86Subtarget.h:553
bool hasLZCNTFalseDeps() const
Definition: X86Subtarget.h:624
bool hasRTM() const
Definition: X86Subtarget.h:595
bool hasFastVectorFSQRT() const
Definition: X86Subtarget.h:633
bool isTargetWindowsCoreCLR() const
Definition: X86Subtarget.h:748