LLVM  9.0.0svn
X86WinAllocaExpander.cpp
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1 //===----- X86WinAllocaExpander.cpp - Expand WinAlloca pseudo instruction -===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines a pass that expands WinAlloca pseudo-instructions.
10 //
11 // It performs a conservative analysis to determine whether each allocation
12 // falls within a region of the stack that is safe to use, or whether stack
13 // probes must be emitted.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #include "X86.h"
18 #include "X86InstrBuilder.h"
19 #include "X86InstrInfo.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86Subtarget.h"
26 #include "llvm/CodeGen/Passes.h"
28 #include "llvm/IR/Function.h"
30 
31 using namespace llvm;
32 
33 namespace {
34 
35 class X86WinAllocaExpander : public MachineFunctionPass {
36 public:
37  X86WinAllocaExpander() : MachineFunctionPass(ID) {}
38 
39  bool runOnMachineFunction(MachineFunction &MF) override;
40 
41 private:
42  /// Strategies for lowering a WinAlloca.
43  enum Lowering { TouchAndSub, Sub, Probe };
44 
45  /// Deterministic-order map from WinAlloca instruction to desired lowering.
46  typedef MapVector<MachineInstr*, Lowering> LoweringMap;
47 
48  /// Compute which lowering to use for each WinAlloca instruction.
49  void computeLowerings(MachineFunction &MF, LoweringMap& Lowerings);
50 
51  /// Get the appropriate lowering based on current offset and amount.
52  Lowering getLowering(int64_t CurrentOffset, int64_t AllocaAmount);
53 
54  /// Lower a WinAlloca instruction.
55  void lower(MachineInstr* MI, Lowering L);
56 
58  const X86Subtarget *STI;
59  const TargetInstrInfo *TII;
60  const X86RegisterInfo *TRI;
61  unsigned StackPtr;
62  unsigned SlotSize;
63  int64_t StackProbeSize;
64  bool NoStackArgProbe;
65 
66  StringRef getPassName() const override { return "X86 WinAlloca Expander"; }
67  static char ID;
68 };
69 
71 
72 } // end anonymous namespace
73 
75  return new X86WinAllocaExpander();
76 }
77 
78 /// Return the allocation amount for a WinAlloca instruction, or -1 if unknown.
80  assert(MI->getOpcode() == X86::WIN_ALLOCA_32 ||
81  MI->getOpcode() == X86::WIN_ALLOCA_64);
82  assert(MI->getOperand(0).isReg());
83 
84  unsigned AmountReg = MI->getOperand(0).getReg();
85  MachineInstr *Def = MRI->getUniqueVRegDef(AmountReg);
86 
87  // Look through copies.
88  while (Def && Def->isCopy() && Def->getOperand(1).isReg())
89  Def = MRI->getUniqueVRegDef(Def->getOperand(1).getReg());
90 
91  if (!Def ||
92  (Def->getOpcode() != X86::MOV32ri && Def->getOpcode() != X86::MOV64ri) ||
93  !Def->getOperand(1).isImm())
94  return -1;
95 
96  return Def->getOperand(1).getImm();
97 }
98 
99 X86WinAllocaExpander::Lowering
100 X86WinAllocaExpander::getLowering(int64_t CurrentOffset,
101  int64_t AllocaAmount) {
102  // For a non-constant amount or a large amount, we have to probe.
103  if (AllocaAmount < 0 || AllocaAmount > StackProbeSize)
104  return Probe;
105 
106  // If it fits within the safe region of the stack, just subtract.
107  if (CurrentOffset + AllocaAmount <= StackProbeSize)
108  return Sub;
109 
110  // Otherwise, touch the current tip of the stack, then subtract.
111  return TouchAndSub;
112 }
113 
114 static bool isPushPop(const MachineInstr &MI) {
115  switch (MI.getOpcode()) {
116  case X86::PUSH32i8:
117  case X86::PUSH32r:
118  case X86::PUSH32rmm:
119  case X86::PUSH32rmr:
120  case X86::PUSHi32:
121  case X86::PUSH64i8:
122  case X86::PUSH64r:
123  case X86::PUSH64rmm:
124  case X86::PUSH64rmr:
125  case X86::PUSH64i32:
126  case X86::POP32r:
127  case X86::POP64r:
128  return true;
129  default:
130  return false;
131  }
132 }
133 
134 void X86WinAllocaExpander::computeLowerings(MachineFunction &MF,
135  LoweringMap &Lowerings) {
136  // Do a one-pass reverse post-order walk of the CFG to conservatively estimate
137  // the offset between the stack pointer and the lowest touched part of the
138  // stack, and use that to decide how to lower each WinAlloca instruction.
139 
140  // Initialize OutOffset[B], the stack offset at exit from B, to something big.
142  for (MachineBasicBlock &MBB : MF)
143  OutOffset[&MBB] = INT32_MAX;
144 
145  // Note: we don't know the offset at the start of the entry block since the
146  // prologue hasn't been inserted yet, and how much that will adjust the stack
147  // pointer depends on register spills, which have not been computed yet.
148 
149  // Compute the reverse post-order.
151 
152  for (MachineBasicBlock *MBB : RPO) {
153  int64_t Offset = -1;
154  for (MachineBasicBlock *Pred : MBB->predecessors())
155  Offset = std::max(Offset, OutOffset[Pred]);
156  if (Offset == -1) Offset = INT32_MAX;
157 
158  for (MachineInstr &MI : *MBB) {
159  if (MI.getOpcode() == X86::WIN_ALLOCA_32 ||
160  MI.getOpcode() == X86::WIN_ALLOCA_64) {
161  // A WinAlloca moves StackPtr, and potentially touches it.
162  int64_t Amount = getWinAllocaAmount(&MI, MRI);
163  Lowering L = getLowering(Offset, Amount);
164  Lowerings[&MI] = L;
165  switch (L) {
166  case Sub:
167  Offset += Amount;
168  break;
169  case TouchAndSub:
170  Offset = Amount;
171  break;
172  case Probe:
173  Offset = 0;
174  break;
175  }
176  } else if (MI.isCall() || isPushPop(MI)) {
177  // Calls, pushes and pops touch the tip of the stack.
178  Offset = 0;
179  } else if (MI.getOpcode() == X86::ADJCALLSTACKUP32 ||
180  MI.getOpcode() == X86::ADJCALLSTACKUP64) {
181  Offset -= MI.getOperand(0).getImm();
182  } else if (MI.getOpcode() == X86::ADJCALLSTACKDOWN32 ||
183  MI.getOpcode() == X86::ADJCALLSTACKDOWN64) {
184  Offset += MI.getOperand(0).getImm();
185  } else if (MI.modifiesRegister(StackPtr, TRI)) {
186  // Any other modification of SP means we've lost track of it.
187  Offset = INT32_MAX;
188  }
189  }
190 
191  OutOffset[MBB] = Offset;
192  }
193 }
194 
195 static unsigned getSubOpcode(bool Is64Bit, int64_t Amount) {
196  if (Is64Bit)
197  return isInt<8>(Amount) ? X86::SUB64ri8 : X86::SUB64ri32;
198  return isInt<8>(Amount) ? X86::SUB32ri8 : X86::SUB32ri;
199 }
200 
201 void X86WinAllocaExpander::lower(MachineInstr* MI, Lowering L) {
202  DebugLoc DL = MI->getDebugLoc();
203  MachineBasicBlock *MBB = MI->getParent();
205 
206  int64_t Amount = getWinAllocaAmount(MI, MRI);
207  if (Amount == 0) {
208  MI->eraseFromParent();
209  return;
210  }
211 
212  bool Is64Bit = STI->is64Bit();
213  assert(SlotSize == 4 || SlotSize == 8);
214  unsigned RegA = (SlotSize == 8) ? X86::RAX : X86::EAX;
215 
216  switch (L) {
217  case TouchAndSub:
218  assert(Amount >= SlotSize);
219 
220  // Use a push to touch the top of the stack.
221  BuildMI(*MBB, I, DL, TII->get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
222  .addReg(RegA, RegState::Undef);
223  Amount -= SlotSize;
224  if (!Amount)
225  break;
226 
227  // Fall through to make any remaining adjustment.
229  case Sub:
230  assert(Amount > 0);
231  if (Amount == SlotSize) {
232  // Use push to save size.
233  BuildMI(*MBB, I, DL, TII->get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
234  .addReg(RegA, RegState::Undef);
235  } else {
236  // Sub.
237  BuildMI(*MBB, I, DL, TII->get(getSubOpcode(Is64Bit, Amount)), StackPtr)
238  .addReg(StackPtr)
239  .addImm(Amount);
240  }
241  break;
242  case Probe:
243  if (!NoStackArgProbe) {
244  // The probe lowering expects the amount in RAX/EAX.
245  BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::COPY), RegA)
246  .addReg(MI->getOperand(0).getReg());
247 
248  // Do the probe.
249  STI->getFrameLowering()->emitStackProbe(*MBB->getParent(), *MBB, MI, DL,
250  /*InPrologue=*/false);
251  } else {
252  // Sub
253  BuildMI(*MBB, I, DL, TII->get(Is64Bit ? X86::SUB64rr : X86::SUB32rr),
254  StackPtr)
255  .addReg(StackPtr)
256  .addReg(MI->getOperand(0).getReg());
257  }
258  break;
259  }
260 
261  unsigned AmountReg = MI->getOperand(0).getReg();
262  MI->eraseFromParent();
263 
264  // Delete the definition of AmountReg, possibly walking a chain of copies.
265  for (;;) {
266  if (!MRI->use_empty(AmountReg))
267  break;
268  MachineInstr *AmountDef = MRI->getUniqueVRegDef(AmountReg);
269  if (!AmountDef)
270  break;
271  if (AmountDef->isCopy() && AmountDef->getOperand(1).isReg())
272  AmountReg = AmountDef->getOperand(1).isReg();
273  AmountDef->eraseFromParent();
274  break;
275  }
276 }
277 
278 bool X86WinAllocaExpander::runOnMachineFunction(MachineFunction &MF) {
280  return false;
281 
282  MRI = &MF.getRegInfo();
283  STI = &MF.getSubtarget<X86Subtarget>();
284  TII = STI->getInstrInfo();
285  TRI = STI->getRegisterInfo();
286  StackPtr = TRI->getStackRegister();
287  SlotSize = TRI->getSlotSize();
288 
289  StackProbeSize = 4096;
290  if (MF.getFunction().hasFnAttribute("stack-probe-size")) {
291  MF.getFunction()
292  .getFnAttribute("stack-probe-size")
294  .getAsInteger(0, StackProbeSize);
295  }
296  NoStackArgProbe = MF.getFunction().hasFnAttribute("no-stack-arg-probe");
297  if (NoStackArgProbe)
298  StackProbeSize = INT64_MAX;
299 
300  LoweringMap Lowerings;
301  computeLowerings(MF, Lowerings);
302  for (auto &P : Lowerings)
303  lower(P.first, P.second);
304 
305  return true;
306 }
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
This class represents lattice values for constants.
Definition: AllocatorList.h:23
Shadow Stack GC Lowering
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:382
unsigned getReg() const
getReg - Returns the register number.
constexpr bool isInt< 8 >(int64_t x)
Definition: MathExtras.h:302
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:320
This class implements a map that also provides access to all stored values in a deterministic order...
Definition: MapVector.h:37
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
X86MachineFunctionInfo - This class is derived from MachineFunction and contains private X86 target-s...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
#define INT64_MAX
Definition: DataTypes.h:77
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:408
static int64_t getWinAllocaAmount(MachineInstr *MI, MachineRegisterInfo *MRI)
Return the allocation amount for a WinAlloca instruction, or -1 if unknown.
TargetInstrInfo - Interface to description of machine instruction set.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
#define P(N)
unsigned const MachineRegisterInfo * MRI
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:284
iterator_range< pred_iterator > predecessors()
bool isCopy() const
std::enable_if< std::numeric_limits< T >::is_signed, bool >::type getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:478
int64_t getImm() const
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
const Function & getFunction() const
Return the LLVM function that this machine code represents.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:253
FunctionPass * createX86WinAllocaExpander()
Return a pass that expands WinAlloca pseudo-instructions.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:63
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:194
#define I(x, y, z)
Definition: MD5.cpp:58
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
rpo Deduce function attributes in RPO
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:250
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:330
static unsigned getSubOpcode(bool Is64Bit, int64_t Amount)
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
static bool isPushPop(const MachineInstr &MI)
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:413