LLVM  12.0.0git
XCoreISelLowering.h
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1 //===-- XCoreISelLowering.h - XCore DAG Lowering Interface ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that XCore uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_XCORE_XCOREISELLOWERING_H
15 #define LLVM_LIB_TARGET_XCORE_XCOREISELLOWERING_H
16 
17 #include "XCore.h"
20 
21 namespace llvm {
22 
23  // Forward delcarations
24  class XCoreSubtarget;
25 
26  namespace XCoreISD {
27  enum NodeType : unsigned {
28  // Start the numbering where the builtin ops and target ops leave off.
30 
31  // Branch and link (call)
32  BL,
33 
34  // pc relative address
36 
37  // dp relative address
39 
40  // cp relative address
42 
43  // Load word from stack
45 
46  // Store word to stack
48 
49  // Corresponds to retsp instruction
51 
52  // Corresponds to LADD instruction
54 
55  // Corresponds to LSUB instruction
57 
58  // Corresponds to LMUL instruction
60 
61  // Corresponds to MACCU instruction
63 
64  // Corresponds to MACCS instruction
66 
67  // Corresponds to CRC8 instruction
69 
70  // Jumptable branch.
72 
73  // Jumptable branch using long branches for each entry.
75 
76  // Offset from frame pointer to the first (possible) on-stack argument
78 
79  // Exception handler return. The stack is restored to the first
80  // followed by a jump to the second argument.
82 
83  // Memory barrier.
85  };
86  }
87 
88  //===--------------------------------------------------------------------===//
89  // TargetLowering Implementation
90  //===--------------------------------------------------------------------===//
92  {
93  public:
94  explicit XCoreTargetLowering(const TargetMachine &TM,
95  const XCoreSubtarget &Subtarget);
96 
98  bool isZExtFree(SDValue Val, EVT VT2) const override;
99 
100 
101  unsigned getJumpTableEncoding() const override;
102  MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override {
103  return MVT::i32;
104  }
105 
106  /// LowerOperation - Provide custom lowering hooks for some operations.
107  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
108 
109  /// ReplaceNodeResults - Replace the results of node with an illegal result
110  /// type with new values built out of custom code.
111  ///
112  void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
113  SelectionDAG &DAG) const override;
114 
115  /// getTargetNodeName - This method returns the name of a target specific
116  // DAG node.
117  const char *getTargetNodeName(unsigned Opcode) const override;
118 
120  EmitInstrWithCustomInserter(MachineInstr &MI,
121  MachineBasicBlock *MBB) const override;
122 
123  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
124  Type *Ty, unsigned AS,
125  Instruction *I = nullptr) const override;
126 
127  /// If a physical register, this returns the register that receives the
128  /// exception address on entry to an EH pad.
129  Register
130  getExceptionPointerRegister(const Constant *PersonalityFn) const override {
131  return XCore::R0;
132  }
133 
134  /// If a physical register, this returns the register that receives the
135  /// exception typeid on entry to a landing pad.
136  Register
137  getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
138  return XCore::R1;
139  }
140 
141  private:
142  const TargetMachine &TM;
143  const XCoreSubtarget &Subtarget;
144 
145  // Lower Operand helpers
146  SDValue LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv,
147  bool isVarArg,
149  const SDLoc &dl, SelectionDAG &DAG,
150  SmallVectorImpl<SDValue> &InVals) const;
151  SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
152  CallingConv::ID CallConv, bool isVarArg,
153  bool isTailCall,
155  const SmallVectorImpl<SDValue> &OutVals,
157  const SDLoc &dl, SelectionDAG &DAG,
158  SmallVectorImpl<SDValue> &InVals) const;
159  SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
160  SDValue getGlobalAddressWrapper(SDValue GA, const GlobalValue *GV,
161  SelectionDAG &DAG) const;
162  SDValue lowerLoadWordFromAlignedBasePlusOffset(const SDLoc &DL,
163  SDValue Chain, SDValue Base,
164  int64_t Offset,
165  SelectionDAG &DAG) const;
166 
167  // Lower Operand specifics
168  SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
169  SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
170  SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
171  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
172  SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
173  SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
174  SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
175  SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
176  SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
177  SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
178  SDValue LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
179  SDValue LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
180  SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
181  SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
183  SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
185  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
187  SDValue LowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const;
189 
190  MachineMemOperand::Flags getTargetMMOFlags(
191  const Instruction &I) const override;
192 
193  // Inline asm support
194  std::pair<unsigned, const TargetRegisterClass *>
195  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
196  StringRef Constraint, MVT VT) const override;
197 
198  // Expand specifics
199  SDValue TryExpandADDWithMul(SDNode *Op, SelectionDAG &DAG) const;
200  SDValue ExpandADDSUB(SDNode *Op, SelectionDAG &DAG) const;
201 
202  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
203 
204  void computeKnownBitsForTargetNode(const SDValue Op,
205  KnownBits &Known,
206  const APInt &DemandedElts,
207  const SelectionDAG &DAG,
208  unsigned Depth = 0) const override;
209 
210  SDValue
211  LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
213  const SDLoc &dl, SelectionDAG &DAG,
214  SmallVectorImpl<SDValue> &InVals) const override;
215 
216  SDValue
217  LowerCall(TargetLowering::CallLoweringInfo &CLI,
218  SmallVectorImpl<SDValue> &InVals) const override;
219 
220  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
222  const SmallVectorImpl<SDValue> &OutVals,
223  const SDLoc &dl, SelectionDAG &DAG) const override;
224 
225  bool
226  CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
227  bool isVarArg,
228  const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
229  LLVMContext &Context) const override;
230  bool shouldInsertFencesForAtomic(const Instruction *I) const override {
231  return true;
232  }
233  };
234 }
235 
236 #endif
static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG)
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1111
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
LLVMContext & Context
This class represents lattice values for constants.
Definition: AllocatorList.h:23
static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
Function Alias Analysis Results
unsigned const TargetRegisterInfo * TRI
virtual bool isZExtFree(Type *FromTy, Type *ToTy) const
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
MachineBasicBlock & MBB
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, const SparcSubtarget *Subtarget)
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
Machine Value Type.
static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG)
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
This is an important base class in LLVM.
Definition: Constant.h:41
static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
Extended Value Type.
Definition: ValueTypes.h:35
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:223
static SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Class for arbitrary precision integers.
Definition: APInt.h:69
amdgpu Simplify well known AMD library false FunctionCallee Callee
static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG)
Flags
Flags values. These may be or&#39;d together.
Representation of each machine instruction.
Definition: MachineInstr.h:62
#define I(x, y, z)
Definition: MD5.cpp:59
#define N
static SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG)
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG, const X86Subtarget &Subtarget)
This file describes how to lower LLVM code to machine code.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL