This is the complete list of members for llvm::AMDGPUCallLowering, including all inherited members.

addArgFlagsFromAttributes(ISD::ArgFlagsTy &Flags, const AttributeList &Attrs, unsigned OpIdx) const	llvm::CallLowering	protected
AMDGPUCallLowering(const AMDGPUTargetLowering &TLI)	llvm::AMDGPUCallLowering
areCalleeOutgoingArgsTailCallable(CallLoweringInfo &Info, MachineFunction &MF, SmallVectorImpl< ArgInfo > &OutArgs) const	llvm::AMDGPUCallLowering
CallLowering(const TargetLowering *TLI)	llvm::CallLowering	inline
CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg)	llvm::AMDGPUCallLowering	static
CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg)	llvm::AMDGPUCallLowering	static
checkReturn(CCState &CCInfo, SmallVectorImpl< BaseArgInfo > &Outs, CCAssignFn *Fn) const	llvm::CallLowering
checkReturnTypeForCallConv(MachineFunction &MF) const	llvm::CallLowering
determineAndHandleAssignments(ValueHandler &Handler, ValueAssigner &Assigner, SmallVectorImpl< ArgInfo > &Args, MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv, bool IsVarArg, ArrayRef< Register > ThisReturnRegs=std::nullopt) const	llvm::CallLowering	protected
determineAssignments(ValueAssigner &Assigner, SmallVectorImpl< ArgInfo > &Args, CCState &CCInfo) const	llvm::CallLowering	protected
doCallerAndCalleePassArgsTheSameWay(CallLoweringInfo &Info, MachineFunction &MF, SmallVectorImpl< ArgInfo > &InArgs) const	llvm::AMDGPUCallLowering
enableBigEndian() const	llvm::CallLowering	inlinevirtual
fallBackToDAGISel(const MachineFunction &MF) const	llvm::CallLowering	inlinevirtual
getAttributesForArgIdx(const CallBase &Call, unsigned ArgIdx) const	llvm::CallLowering	protected
getAttributesForReturn(const CallBase &Call) const	llvm::CallLowering	protected
getReturnInfo(CallingConv::ID CallConv, Type *RetTy, AttributeList Attrs, SmallVectorImpl< BaseArgInfo > &Outs, const DataLayout &DL) const	llvm::CallLowering
getTLI() const	llvm::CallLowering	inlineprotected
getTLI() const	llvm::CallLowering	inlineprotected
handleAssignments(ValueHandler &Handler, SmallVectorImpl< ArgInfo > &Args, CCState &CCState, SmallVectorImpl< CCValAssign > &ArgLocs, MachineIRBuilder &MIRBuilder, ArrayRef< Register > ThisReturnRegs=std::nullopt) const	llvm::CallLowering	protected
handleImplicitCallArguments(MachineIRBuilder &MIRBuilder, MachineInstrBuilder &CallInst, const GCNSubtarget &ST, const SIMachineFunctionInfo &MFI, CallingConv::ID CalleeCC, ArrayRef< std::pair< MCRegister, Register > > ImplicitArgRegs) const	llvm::AMDGPUCallLowering
insertSRetIncomingArgument(const Function &F, SmallVectorImpl< ArgInfo > &SplitArgs, Register &DemoteReg, MachineRegisterInfo &MRI, const DataLayout &DL) const	llvm::CallLowering
insertSRetLoads(MachineIRBuilder &MIRBuilder, Type *RetTy, ArrayRef< Register > VRegs, Register DemoteReg, int FI) const	llvm::CallLowering
insertSRetOutgoingArgument(MachineIRBuilder &MIRBuilder, const CallBase &CB, CallLoweringInfo &Info) const	llvm::CallLowering
insertSRetStores(MachineIRBuilder &MIRBuilder, Type *RetTy, ArrayRef< Register > VRegs, Register DemoteReg) const	llvm::CallLowering
isEligibleForTailCallOptimization(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info, SmallVectorImpl< ArgInfo > &InArgs, SmallVectorImpl< ArgInfo > &OutArgs) const	llvm::AMDGPUCallLowering
isTypeIsValidForThisReturn(EVT Ty) const	llvm::CallLowering	inlinevirtual
lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const override	llvm::AMDGPUCallLowering	virtual
llvm::CallLowering::lowerCall(MachineIRBuilder &MIRBuilder, const CallBase &Call, ArrayRef< Register > ResRegs, ArrayRef< ArrayRef< Register > > ArgRegs, Register SwiftErrorVReg, Register ConvergenceCtrlToken, std::function< unsigned()> GetCalleeReg) const	llvm::CallLowering
lowerChainCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const	llvm::AMDGPUCallLowering
lowerFormalArguments(MachineIRBuilder &B, const Function &F, ArrayRef< ArrayRef< Register > > VRegs, FunctionLoweringInfo &FLI) const override	llvm::AMDGPUCallLowering	virtual
lowerFormalArgumentsKernel(MachineIRBuilder &B, const Function &F, ArrayRef< ArrayRef< Register > > VRegs) const	llvm::AMDGPUCallLowering
lowerReturn(MachineIRBuilder &B, const Value *Val, ArrayRef< Register > VRegs, FunctionLoweringInfo &FLI) const override	llvm::AMDGPUCallLowering	virtual
llvm::CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, ArrayRef< Register > VRegs, FunctionLoweringInfo &FLI, Register SwiftErrorVReg) const	llvm::CallLowering	inlinevirtual
lowerTailCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info, SmallVectorImpl< ArgInfo > &OutArgs) const	llvm::AMDGPUCallLowering
parametersInCSRMatch(const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask, const SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< ArgInfo > &OutVals) const	llvm::CallLowering	protected
passSpecialInputs(MachineIRBuilder &MIRBuilder, CCState &CCInfo, SmallVectorImpl< std::pair< MCRegister, Register > > &ArgRegs, CallLoweringInfo &Info) const	llvm::AMDGPUCallLowering
resultsCompatible(CallLoweringInfo &Info, MachineFunction &MF, SmallVectorImpl< ArgInfo > &InArgs, ValueAssigner &CalleeAssigner, ValueAssigner &CallerAssigner) const	llvm::CallLowering	protected
setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL, const FuncInfoTy &FuncInfo) const	llvm::CallLowering	protected
splitToValueTypes(const ArgInfo &OrigArgInfo, SmallVectorImpl< ArgInfo > &SplitArgs, const DataLayout &DL, CallingConv::ID CallConv, SmallVectorImpl< uint64_t > *Offsets=nullptr) const	llvm::CallLowering	protected
supportSwiftError() const	llvm::CallLowering	inlinevirtual
~CallLowering()=default	llvm::CallLowering	virtual