LLVM 19.0.0git
llvm::AMDGPUDisassembler Member List

This is the complete list of members for llvm::AMDGPUDisassembler, including all inherited members.

AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, MCInstrInfo const *MCII)llvm::AMDGPUDisassembler
CommentStreamllvm::MCDisassemblermutable
convertDPP8Inst(MCInst &MI) constllvm::AMDGPUDisassembler
convertEXPInst(MCInst &MI) constllvm::AMDGPUDisassembler
convertFMAanyK(MCInst &MI, int ImmLitIdx) constllvm::AMDGPUDisassembler
convertMacDPPInst(MCInst &MI) constllvm::AMDGPUDisassembler
convertMIMGInst(MCInst &MI) constllvm::AMDGPUDisassembler
convertSDWAInst(MCInst &MI) constllvm::AMDGPUDisassembler
convertTrue16OpSel(MCInst &MI) constllvm::AMDGPUDisassembler
convertVINTERPInst(MCInst &MI) constllvm::AMDGPUDisassembler
convertVOP3DPPInst(MCInst &MI) constllvm::AMDGPUDisassembler
convertVOP3PDPPInst(MCInst &MI) constllvm::AMDGPUDisassembler
convertVOPCDPPInst(MCInst &MI) constllvm::AMDGPUDisassembler
createRegOperand(unsigned int RegId) constllvm::AMDGPUDisassemblerinline
createRegOperand(unsigned RegClassID, unsigned Val) constllvm::AMDGPUDisassemblerinline
createSRegOperand(unsigned SRegClassID, unsigned Val) constllvm::AMDGPUDisassemblerinline
createVGPR16Operand(unsigned RegIdx, bool IsHi) constllvm::AMDGPUDisassembler
decodeBoolReg(unsigned Val) constllvm::AMDGPUDisassembler
decodeCOMPUTE_PGM_RSRC1(uint32_t FourByteBuffer, raw_string_ostream &KdStream) constllvm::AMDGPUDisassembler
decodeCOMPUTE_PGM_RSRC2(uint32_t FourByteBuffer, raw_string_ostream &KdStream) constllvm::AMDGPUDisassembler
decodeCOMPUTE_PGM_RSRC3(uint32_t FourByteBuffer, raw_string_ostream &KdStream) constllvm::AMDGPUDisassembler
decodeDpp8FI(unsigned Val) constllvm::AMDGPUDisassembler
decodeFPImmed(unsigned ImmWidth, unsigned Imm, AMDGPU::OperandSemantics Sema)llvm::AMDGPUDisassemblerstatic
decodeIntImmed(unsigned Imm)llvm::AMDGPUDisassemblerstatic
decodeKernelDescriptor(StringRef KdName, ArrayRef< uint8_t > Bytes, uint64_t KdAddress) constllvm::AMDGPUDisassembler
decodeKernelDescriptorDirective(DataExtractor::Cursor &Cursor, ArrayRef< uint8_t > Bytes, raw_string_ostream &KdStream) constllvm::AMDGPUDisassembler
decodeLiteralConstant(bool ExtendFP64) constllvm::AMDGPUDisassembler
decodeMandatoryLiteralConstant(unsigned Imm) constllvm::AMDGPUDisassembler
decodeNonVGPRSrcOp(const OpWidthTy Width, unsigned Val, bool MandatoryLiteral=false, unsigned ImmWidth=0, AMDGPU::OperandSemantics Sema=AMDGPU::OperandSemantics::INT) constllvm::AMDGPUDisassembler
decodeSDWASrc(const OpWidthTy Width, unsigned Val, unsigned ImmWidth, AMDGPU::OperandSemantics Sema) constllvm::AMDGPUDisassembler
decodeSDWASrc16(unsigned Val) constllvm::AMDGPUDisassembler
decodeSDWASrc32(unsigned Val) constllvm::AMDGPUDisassembler
decodeSDWAVopcDst(unsigned Val) constllvm::AMDGPUDisassembler
decodeSpecialReg32(unsigned Val) constllvm::AMDGPUDisassembler
decodeSpecialReg64(unsigned Val) constllvm::AMDGPUDisassembler
decodeSplitBarrier(unsigned Val) constllvm::AMDGPUDisassembler
decodeSrcOp(const OpWidthTy Width, unsigned Val, bool MandatoryLiteral=false, unsigned ImmWidth=0, AMDGPU::OperandSemantics Sema=AMDGPU::OperandSemantics::INT) constllvm::AMDGPUDisassembler
DecodeStatus enum namellvm::MCDisassembler
decodeVOPDDstYOp(MCInst &Inst, unsigned Val) constllvm::AMDGPUDisassembler
errOperand(unsigned V, const Twine &ErrMsg) constllvm::AMDGPUDisassemblerinline
Fail enum valuellvm::MCDisassembler
getAgprClassId(const OpWidthTy Width) constllvm::AMDGPUDisassembler
getContext() constllvm::MCDisassemblerinline
getInstruction(MCInst &MI, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CS) const overridellvm::AMDGPUDisassemblervirtual
getMCII() constllvm::AMDGPUDisassemblerinline
getRegClassName(unsigned RegClassID) constllvm::AMDGPUDisassembler
getSgprClassId(const OpWidthTy Width) constllvm::AMDGPUDisassembler
getSubtargetInfo() constllvm::MCDisassemblerinline
getTtmpClassId(const OpWidthTy Width) constllvm::AMDGPUDisassembler
getTTmpIdx(unsigned Val) constllvm::AMDGPUDisassembler
getVgprClassId(const OpWidthTy Width) constllvm::AMDGPUDisassembler
hasArchitectedFlatScratch() constllvm::AMDGPUDisassembler
hasKernargPreload() constllvm::AMDGPUDisassembler
isGFX10() constllvm::AMDGPUDisassembler
isGFX10Plus() constllvm::AMDGPUDisassembler
isGFX11() constllvm::AMDGPUDisassembler
isGFX11Plus() constllvm::AMDGPUDisassembler
isGFX12() constllvm::AMDGPUDisassembler
isGFX12Plus() constllvm::AMDGPUDisassembler
isGFX9() constllvm::AMDGPUDisassembler
isGFX90A() constllvm::AMDGPUDisassembler
isGFX9Plus() constllvm::AMDGPUDisassembler
isMacDPP(MCInst &MI) constllvm::AMDGPUDisassembler
isVI() constllvm::AMDGPUDisassembler
MCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)llvm::MCDisassemblerinline
onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const overridellvm::AMDGPUDisassemblervirtual
OPW1024 enum valuellvm::AMDGPUDisassembler
OPW128 enum valuellvm::AMDGPUDisassembler
OPW16 enum valuellvm::AMDGPUDisassembler
OPW160 enum valuellvm::AMDGPUDisassembler
OPW256 enum valuellvm::AMDGPUDisassembler
OPW288 enum valuellvm::AMDGPUDisassembler
OPW32 enum valuellvm::AMDGPUDisassembler
OPW320 enum valuellvm::AMDGPUDisassembler
OPW352 enum valuellvm::AMDGPUDisassembler
OPW384 enum valuellvm::AMDGPUDisassembler
OPW512 enum valuellvm::AMDGPUDisassembler
OPW64 enum valuellvm::AMDGPUDisassembler
OPW96 enum valuellvm::AMDGPUDisassembler
OPW_FIRST_ enum valuellvm::AMDGPUDisassembler
OPW_LAST_ enum valuellvm::AMDGPUDisassembler
OpWidthTy enum namellvm::AMDGPUDisassembler
OPWV216 enum valuellvm::AMDGPUDisassembler
OPWV232 enum valuellvm::AMDGPUDisassembler
setABIVersion(unsigned Version) overridellvm::AMDGPUDisassemblervirtual
setSymbolizer(std::unique_ptr< MCSymbolizer > Symzer)llvm::MCDisassembler
SoftFail enum valuellvm::MCDisassembler
STIllvm::MCDisassemblerprotected
Success enum valuellvm::MCDisassembler
suggestBytesToSkip(ArrayRef< uint8_t > Bytes, uint64_t Address) constllvm::MCDisassemblervirtual
Symbolizerllvm::MCDisassemblerprotected
tryAddingPcLoadReferenceComment(int64_t Value, uint64_t Address) constllvm::MCDisassembler
tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) constllvm::MCDisassembler
tryDecodeInst(const uint8_t *Table, MCInst &MI, InsnType Inst, uint64_t Address, raw_ostream &Comments) constllvm::AMDGPUDisassemblerinline
tryDecodeInst(const uint8_t *Table1, const uint8_t *Table2, MCInst &MI, InsnType Inst, uint64_t Address, raw_ostream &Comments) constllvm::AMDGPUDisassemblerinline
~AMDGPUDisassembler() override=defaultllvm::AMDGPUDisassembler
~MCDisassembler()llvm::MCDisassemblervirtual