LLVM  6.0.0svn
Classes | Public Member Functions | Protected Attributes | List of all members
llvm::AMDGPUInstructionSelector Class Reference

#include "Target/AMDGPU/AMDGPUInstructionSelector.h"

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Public Member Functions

 AMDGPUInstructionSelector (const SISubtarget &STI, const AMDGPURegisterBankInfo &RBI)
 
bool select (MachineInstr &I) const override
 Select the (possibly generic) instruction I to only use target-specific opcodes. More...
 
- Public Member Functions inherited from llvm::InstructionSelector
virtual ~InstructionSelector ()=default
 

Protected Attributes

AMDGPUAS AMDGPUASI
 

Additional Inherited Members

- Public Types inherited from llvm::InstructionSelector
using I64ImmediatePredicateFn = bool(*)(int64_t)
 
using APIntImmediatePredicateFn = bool(*)(const APInt &)
 
using APFloatImmediatePredicateFn = bool(*)(const APFloat &)
 
- Protected Types inherited from llvm::InstructionSelector
using ComplexRendererFns = Optional< SmallVector< std::function< void(MachineInstrBuilder &)>, 4 > >
 
using RecordedMIVector = SmallVector< MachineInstr *, 4 >
 
using NewMIVector = SmallVector< MachineInstrBuilder, 4 >
 
- Protected Member Functions inherited from llvm::InstructionSelector
 InstructionSelector ()
 
template<class TgtInstructionSelector , class PredicateBitset , class ComplexMatcherMemFn >
bool executeMatchTable (TgtInstructionSelector &ISel, NewMIVector &OutMIs, MatcherState &State, const MatcherInfoTy< PredicateBitset, ComplexMatcherMemFn > &MatcherInfo, const int64_t *MatchTable, const TargetInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI, const PredicateBitset &AvailableFeatures) const
 Execute a given matcher table and return true if the match was successful and false otherwise. More...
 
bool constrainOperandRegToRegClass (MachineInstr &I, unsigned OpIdx, const TargetRegisterClass &RC, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) const
 Constrain a register operand of an instruction I to a specified register class. More...
 
bool constrainSelectedInstRegOperands (MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) const
 Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands to the instruction's register class. More...
 
bool isOperandImmEqual (const MachineOperand &MO, int64_t Value, const MachineRegisterInfo &MRI) const
 
bool isBaseWithConstantOffset (const MachineOperand &Root, const MachineRegisterInfo &MRI) const
 Return true if the specified operand is a G_GEP with a G_CONSTANT on the right-hand side. More...
 
bool isObviouslySafeToFold (MachineInstr &MI) const
 

Detailed Description

Definition at line 33 of file AMDGPUInstructionSelector.h.

Constructor & Destructor Documentation

◆ AMDGPUInstructionSelector()

AMDGPUInstructionSelector::AMDGPUInstructionSelector ( const SISubtarget STI,
const AMDGPURegisterBankInfo RBI 
)

Member Function Documentation

◆ select()

bool AMDGPUInstructionSelector::select ( MachineInstr I) const
overridevirtual

Select the (possibly generic) instruction I to only use target-specific opcodes.

It is OK to insert multiple instructions, but they cannot be generic pre-isel instructions.

Returns
whether selection succeeded.
Precondition
I.getParent() && I.getParent()->getParent()
Postcondition
if returns true: for I in all mutated/inserted instructions: !isPreISelGenericOpcode(I.getOpcode())

Implements llvm::InstructionSelector.

Definition at line 405 of file AMDGPUInstructionSelector.cpp.

References llvm::MachineInstr::getOpcode(), and llvm::isPreISelGenericOpcode().

Member Data Documentation

◆ AMDGPUASI

AMDGPUAS llvm::AMDGPUInstructionSelector::AMDGPUASI
protected

Definition at line 63 of file AMDGPUInstructionSelector.h.

Referenced by getSmrdOpcode().


The documentation for this class was generated from the following files: