LLVM  10.0.0svn
llvm::AMDGPURegisterBankInfo Member List

This is the complete list of members for llvm::AMDGPURegisterBankInfo, including all inherited members.

addMappingFromTable(const MachineInstr &MI, const MachineRegisterInfo &MRI, const std::array< unsigned, NumOps > RegSrcOpIdx, ArrayRef< OpRegBankEntry< NumOps >> Table) constllvm::AMDGPURegisterBankInfo
AMDGPURegisterBankInfo(const GCNSubtarget &STI)llvm::AMDGPURegisterBankInfo
applyDefaultMapping(const OperandsMapper &OpdMapper)llvm::RegisterBankInfostatic
cannotCopy(const RegisterBank &Dst, const RegisterBank &Src, unsigned Size) constllvm::RegisterBankInfoinline
constrainGenericRegister(Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)llvm::RegisterBankInfostatic
copyCost(const RegisterBank &A, const RegisterBank &B, unsigned Size) const overridellvm::AMDGPURegisterBankInfovirtual
DefaultMappingIDllvm::RegisterBankInfostatic
getBreakDownCost(const ValueMapping &ValMapping, const RegisterBank *CurBank=nullptr) const overridellvm::AMDGPURegisterBankInfovirtual
getInstrAlternativeMappings(const MachineInstr &MI) const overridellvm::AMDGPURegisterBankInfovirtual
getInstrMapping(const MachineInstr &MI) const overridellvm::AMDGPURegisterBankInfovirtual
getInstrMappingImpl(const MachineInstr &MI) constllvm::RegisterBankInfoprotected
getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) constllvm::RegisterBankInfoinline
getInvalidInstructionMapping() constllvm::RegisterBankInfoinline
getMinimalPhysRegClass(Register Reg, const TargetRegisterInfo &TRI) constllvm::RegisterBankInfoprotected
getNumRegBanks() constllvm::RegisterBankInfoinline
getOperandsMapping(Iterator Begin, Iterator End) constllvm::RegisterBankInfoprotected
getOperandsMapping(const SmallVectorImpl< const ValueMapping *> &OpdsMapping) constllvm::RegisterBankInfoprotected
getOperandsMapping(std::initializer_list< const ValueMapping *> OpdsMapping) constllvm::RegisterBankInfoprotected
getPartialMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) constllvm::RegisterBankInfoprotected
getRegBank(unsigned ID)llvm::RegisterBankInfoinlineprotected
getRegBank(unsigned ID) constllvm::RegisterBankInfoinline
getRegBank(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) constllvm::RegisterBankInfo
getRegBankFromConstraints(const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) constllvm::RegisterBankInfo
getRegBankFromRegClass(const TargetRegisterClass &RC) const overridellvm::AMDGPURegisterBankInfovirtual
getValueMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) constllvm::RegisterBankInfoprotected
getValueMapping(const PartialMapping *BreakDown, unsigned NumBreakDowns) constllvm::RegisterBankInfoprotected
InstructionMappings typedefllvm::RegisterBankInfo
InvalidMappingIDllvm::RegisterBankInfostatic
MapOfInstructionMappingsllvm::RegisterBankInfomutableprotected
MapOfOperandsMappingsllvm::RegisterBankInfomutableprotected
MapOfPartialMappingsllvm::RegisterBankInfomutableprotected
MapOfValueMappingsllvm::RegisterBankInfomutableprotected
NumRegBanksllvm::RegisterBankInfoprotected
PhysRegMinimalRCsllvm::RegisterBankInfomutableprotected
RegBanksllvm::RegisterBankInfoprotected
RegisterBankInfo(RegisterBank **RegBanks, unsigned NumRegBanks)llvm::RegisterBankInfoprotected
RegisterBankInfo()llvm::RegisterBankInfoinlineprotected
ScalarAddx2llvm::RegisterBankInfo
VectorAddllvm::RegisterBankInfo
~RegisterBankInfo()=defaultllvm::RegisterBankInfovirtual