LLVM  6.0.0svn
Public Member Functions | List of all members
llvm::ARCInstrInfo Class Reference

#include "Target/ARC/ARCInstrInfo.h"

Inheritance diagram for llvm::ARCInstrInfo:
Inheritance graph
[legend]
Collaboration diagram for llvm::ARCInstrInfo:
Collaboration graph
[legend]

Public Member Functions

 ARCInstrInfo ()
 
const ARCRegisterInfogetRegisterInfo () const
 
unsigned isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const override
 If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot. More...
 
unsigned isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const override
 If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot. More...
 
unsigned getInstSizeInBytes (const MachineInstr &MI) const override
 
bool analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
 Analyze the branching code at the end of MBB, returning true if it cannot be understood (e.g. More...
 
unsigned insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &dl, int *BytesAdded=nullptr) const override
 
unsigned removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
 
void copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &dl, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
 
void storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
 
void loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
 
bool reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
 Return the inverse opcode of the specified Branch instruction. More...
 
MachineBasicBlock::iterator loadImmediate (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Reg, uint64_t Value) const
 

Detailed Description

Definition at line 27 of file ARCInstrInfo.h.

Constructor & Destructor Documentation

◆ ARCInstrInfo()

ARCInstrInfo::ARCInstrInfo ( )

Definition at line 34 of file ARCInstrInfo.cpp.

Member Function Documentation

◆ analyzeBranch()

bool ARCInstrInfo::analyzeBranch ( MachineBasicBlock MBB,
MachineBasicBlock *&  TBB,
MachineBasicBlock *&  FBB,
SmallVectorImpl< MachineOperand > &  Cond,
bool  AllowModify 
) const
override

Analyze the branching code at the end of MBB, returning true if it cannot be understood (e.g.

it's a switch dispatch or isn't implemented for a target). Upon success, this returns false and returns with the following information in various cases:

  1. If this block ends with no branches (it just falls through to its succ) just return false, leaving TBB/FBB null.
  2. If this block ends with only an unconditional branch, it sets TBB to be the destination block.
  3. If this block ends with a conditional branch and it falls through to a successor block, it sets TBB to be the branch destination block and a list of operands that evaluate the condition. These operands can be passed to other TargetInstrInfo methods to create new branches.
  4. If this block ends with a conditional branch followed by an unconditional branch, it returns the 'true' destination in TBB, the 'false' destination in FBB, and a list of operands that evaluate the condition. These operands can be passed to other TargetInstrInfo methods to create new branches.

Note that RemoveBranch and InsertBranch must be implemented to support cases where this method returns success.

If AllowModify is true, then this routine is allowed to modify the basic block (e.g. delete instructions after the unconditional branch).

Definition at line 154 of file ARCInstrInfo.cpp.

References assert(), llvm::MachineBasicBlock::begin(), llvm::SmallVectorImpl< T >::clear(), llvm::SmallVectorBase::empty(), llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), I, llvm::isCondBranchOpcode(), isJumpOpcode(), llvm::HexagonMCInstrInfo::isPredicated(), llvm::isUncondBranchOpcode(), and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().

Referenced by getRegisterInfo().

◆ copyPhysReg()

void ARCInstrInfo::copyPhysReg ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
const DebugLoc dl,
unsigned  DestReg,
unsigned  SrcReg,
bool  KillSrc 
) const
override

◆ getInstSizeInBytes()

unsigned ARCInstrInfo::getInstSizeInBytes ( const MachineInstr MI) const
override

◆ getRegisterInfo()

const ARCRegisterInfo& llvm::ARCInstrInfo::getRegisterInfo ( ) const
inline

◆ insertBranch()

unsigned ARCInstrInfo::insertBranch ( MachineBasicBlock MBB,
MachineBasicBlock TBB,
MachineBasicBlock FBB,
ArrayRef< MachineOperand Cond,
const DebugLoc dl,
int *  BytesAdded = nullptr 
) const
override

◆ isLoadFromStackSlot()

unsigned ARCInstrInfo::isLoadFromStackSlot ( const MachineInstr MI,
int &  FrameIndex 
) const
override

If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot.

If not, return 0. This predicate must return 0 if the instruction has any side effects other than loading from the stack slot.

Definition at line 56 of file ARCInstrInfo.cpp.

References llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), isLoad(), and isZeroImm().

Referenced by getRegisterInfo().

◆ isStoreToStackSlot()

unsigned ARCInstrInfo::isStoreToStackSlot ( const MachineInstr MI,
int &  FrameIndex 
) const
override

If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot.

If not, return 0. This predicate must return 0 if the instruction has any side effects other than storing to the stack slot.

Definition at line 75 of file ARCInstrInfo.cpp.

References llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), isStore(), and isZeroImm().

Referenced by getRegisterInfo().

◆ loadImmediate()

MachineBasicBlock::iterator ARCInstrInfo::loadImmediate ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
unsigned  Reg,
uint64_t  Value 
) const

◆ loadRegFromStackSlot()

void ARCInstrInfo::loadRegFromStackSlot ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
unsigned  DestReg,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI 
) const
override

◆ removeBranch()

unsigned ARCInstrInfo::removeBranch ( MachineBasicBlock MBB,
int *  BytesRemoved = nullptr 
) const
override

◆ reverseBranchCondition()

bool ARCInstrInfo::reverseBranchCondition ( SmallVectorImpl< MachineOperand > &  Cond) const
override

Return the inverse opcode of the specified Branch instruction.

Definition at line 334 of file ARCInstrInfo.cpp.

References assert(), GetOppositeBranchCondition(), and llvm::SmallVectorTemplateCommon< T >::size().

Referenced by getRegisterInfo().

◆ storeRegToStackSlot()

void ARCInstrInfo::storeRegToStackSlot ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
unsigned  SrcReg,
bool  isKill,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI 
) const
override

The documentation for this class was generated from the following files: