LLVM  6.0.0svn
llvm::HexagonInstrInfo Member List

This is the complete list of members for llvm::HexagonInstrInfo, including all inherited members.

addLatencyToSchedule(const MachineInstr &MI1, const MachineInstr &MI2) constllvm::HexagonInstrInfo
analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const overridellvm::HexagonInstrInfo
analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const overridellvm::HexagonInstrInfo
analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst, MachineInstr *&CmpInst) const overridellvm::HexagonInstrInfo
areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA=nullptr) const overridellvm::HexagonInstrInfo
canExecuteInBundle(const MachineInstr &First, const MachineInstr &Second) constllvm::HexagonInstrInfo
changeAddrMode_abs_io(short Opc) constllvm::HexagonInstrInfo
changeAddrMode_abs_io(const MachineInstr &MI) constllvm::HexagonInstrInfoinline
changeAddrMode_io_abs(short Opc) constllvm::HexagonInstrInfo
changeAddrMode_io_abs(const MachineInstr &MI) constllvm::HexagonInstrInfoinline
changeAddrMode_io_rr(short Opc) constllvm::HexagonInstrInfo
changeAddrMode_io_rr(const MachineInstr &MI) constllvm::HexagonInstrInfoinline
changeAddrMode_rr_io(short Opc) constllvm::HexagonInstrInfo
changeAddrMode_rr_io(const MachineInstr &MI) constllvm::HexagonInstrInfoinline
changeAddrMode_rr_ur(short Opc) constllvm::HexagonInstrInfo
changeAddrMode_rr_ur(const MachineInstr &MI) constllvm::HexagonInstrInfoinline
changeAddrMode_ur_rr(short Opc) constllvm::HexagonInstrInfo
changeAddrMode_ur_rr(const MachineInstr &MI) constllvm::HexagonInstrInfoinline
copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const overridellvm::HexagonInstrInfo
CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const overridellvm::HexagonInstrInfo
CreateTargetScheduleState(const TargetSubtargetInfo &STI) const overridellvm::HexagonInstrInfo
createVR(MachineFunction *MF, MVT VT) constllvm::HexagonInstrInfo
decomposeMachineOperandsTargetFlags(unsigned TF) const overridellvm::HexagonInstrInfo
DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const overridellvm::HexagonInstrInfo
doesNotReturn(const MachineInstr &CallMI) constllvm::HexagonInstrInfo
expandPostRAPseudo(MachineInstr &MI) const overridellvm::HexagonInstrInfo
genAllInsnTimingClasses(MachineFunction &MF) constllvm::HexagonInstrInfo
getAddrMode(const MachineInstr &MI) constllvm::HexagonInstrInfo
getBaseAndOffset(const MachineInstr &MI, int &Offset, unsigned &AccessSize) constllvm::HexagonInstrInfo
getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos, unsigned &OffsetPos) const overridellvm::HexagonInstrInfo
getBranchingInstrs(MachineBasicBlock &MBB) constllvm::HexagonInstrInfo
getCExtOpNum(const MachineInstr &MI) constllvm::HexagonInstrInfo
getCompoundCandidateGroup(const MachineInstr &MI) constllvm::HexagonInstrInfo
getCompoundOpcode(const MachineInstr &GA, const MachineInstr &GB) constllvm::HexagonInstrInfo
getCondOpcode(int Opc, bool sense) constllvm::HexagonInstrInfo
getDotCurOp(const MachineInstr &MI) constllvm::HexagonInstrInfo
getDotNewOp(const MachineInstr &MI) constllvm::HexagonInstrInfo
getDotNewPredJumpOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) constllvm::HexagonInstrInfo
getDotNewPredOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) constllvm::HexagonInstrInfo
getDotOldOp(const MachineInstr &MI) constllvm::HexagonInstrInfo
getDuplexCandidateGroup(const MachineInstr &MI) constllvm::HexagonInstrInfo
getEquivalentHWInstr(const MachineInstr &MI) constllvm::HexagonInstrInfo
getFirstNonDbgInst(MachineBasicBlock *BB) constllvm::HexagonInstrInfo
getIncrementValue(const MachineInstr &MI, int &Value) const overridellvm::HexagonInstrInfo
getInlineAsmLength(const char *Str, const MCAsmInfo &MAI) const overridellvm::HexagonInstrInfo
getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const overridellvm::HexagonInstrInfo
getInstrTimingClassLatency(const InstrItineraryData *ItinData, const MachineInstr &MI) constllvm::HexagonInstrInfo
getInvertedPredicatedOpcode(const int Opc) constllvm::HexagonInstrInfo
getInvertedPredSense(SmallVectorImpl< MachineOperand > &Cond) constllvm::HexagonInstrInfo
getMaxValue(const MachineInstr &MI) constllvm::HexagonInstrInfo
getMemAccessSize(const MachineInstr &MI) constllvm::HexagonInstrInfo
getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, const TargetRegisterInfo *TRI) const overridellvm::HexagonInstrInfo
getMinValue(const MachineInstr &MI) constllvm::HexagonInstrInfo
getNonDotCurOp(const MachineInstr &MI) constllvm::HexagonInstrInfo
getNonExtOpcode(const MachineInstr &MI) constllvm::HexagonInstrInfo
getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const overridellvm::HexagonInstrInfo
getPredReg(ArrayRef< MachineOperand > Cond, unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) constllvm::HexagonInstrInfo
getPseudoInstrPair(const MachineInstr &MI) constllvm::HexagonInstrInfo
getRegForm(const MachineInstr &MI) constllvm::HexagonInstrInfo
getSerializableBitmaskMachineOperandTargetFlags() const overridellvm::HexagonInstrInfo
getSerializableDirectMachineOperandTargetFlags() const overridellvm::HexagonInstrInfo
getSize(const MachineInstr &MI) constllvm::HexagonInstrInfo
getType(const MachineInstr &MI) constllvm::HexagonInstrInfo
getUnits(const MachineInstr &MI) constllvm::HexagonInstrInfo
hasEHLabel(const MachineBasicBlock *B) constllvm::HexagonInstrInfo
hasNonExtEquivalent(const MachineInstr &MI) constllvm::HexagonInstrInfo
hasPseudoInstrPair(const MachineInstr &MI) constllvm::HexagonInstrInfo
hasUncondBranch(const MachineBasicBlock *B) constllvm::HexagonInstrInfo
HexagonInstrInfo(HexagonSubtarget &ST)llvm::HexagonInstrInfoexplicit
immediateExtend(MachineInstr &MI) constllvm::HexagonInstrInfo
insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const overridellvm::HexagonInstrInfo
insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const overridellvm::HexagonInstrInfo
invertAndChangeJumpTarget(MachineInstr &MI, MachineBasicBlock *NewTarget) constllvm::HexagonInstrInfo
isAbsoluteSet(const MachineInstr &MI) constllvm::HexagonInstrInfo
isAccumulator(const MachineInstr &MI) constllvm::HexagonInstrInfo
isComplex(const MachineInstr &MI) constllvm::HexagonInstrInfo
isCompoundBranchInstr(const MachineInstr &MI) constllvm::HexagonInstrInfo
isConstExtended(const MachineInstr &MI) constllvm::HexagonInstrInfo
isDeallocRet(const MachineInstr &MI) constllvm::HexagonInstrInfo
isDependent(const MachineInstr &ProdMI, const MachineInstr &ConsMI) constllvm::HexagonInstrInfo
isDotCurInst(const MachineInstr &MI) constllvm::HexagonInstrInfo
isDotNewInst(const MachineInstr &MI) constllvm::HexagonInstrInfo
isDuplexPair(const MachineInstr &MIa, const MachineInstr &MIb) constllvm::HexagonInstrInfo
isEarlySourceInstr(const MachineInstr &MI) constllvm::HexagonInstrInfo
isEndLoopN(unsigned Opcode) constllvm::HexagonInstrInfo
isExpr(unsigned OpType) constllvm::HexagonInstrInfo
isExtendable(const MachineInstr &MI) constllvm::HexagonInstrInfo
isExtended(const MachineInstr &MI) constllvm::HexagonInstrInfo
isFloat(const MachineInstr &MI) constllvm::HexagonInstrInfo
isHVXMemWithAIndirect(const MachineInstr &I, const MachineInstr &J) constllvm::HexagonInstrInfo
isHVXVec(const MachineInstr &MI) constllvm::HexagonInstrInfo
isIndirectCall(const MachineInstr &MI) constllvm::HexagonInstrInfo
isIndirectL4Return(const MachineInstr &MI) constllvm::HexagonInstrInfo
isJumpR(const MachineInstr &MI) constllvm::HexagonInstrInfo
isJumpWithinBranchRange(const MachineInstr &MI, unsigned offset) constllvm::HexagonInstrInfo
isLateInstrFeedsEarlyInstr(const MachineInstr &LRMI, const MachineInstr &ESMI) constllvm::HexagonInstrInfo
isLateResultInstr(const MachineInstr &MI) constllvm::HexagonInstrInfo
isLateSourceInstr(const MachineInstr &MI) constllvm::HexagonInstrInfo
isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const overridellvm::HexagonInstrInfo
isLoopN(const MachineInstr &MI) constllvm::HexagonInstrInfo
isMemOp(const MachineInstr &MI) constllvm::HexagonInstrInfo
isNewValue(const MachineInstr &MI) constllvm::HexagonInstrInfo
isNewValue(unsigned Opcode) constllvm::HexagonInstrInfo
isNewValueInst(const MachineInstr &MI) constllvm::HexagonInstrInfo
isNewValueJump(const MachineInstr &MI) constllvm::HexagonInstrInfo
isNewValueJump(unsigned Opcode) constllvm::HexagonInstrInfo
isNewValueStore(const MachineInstr &MI) constllvm::HexagonInstrInfo
isNewValueStore(unsigned Opcode) constllvm::HexagonInstrInfo
isOperandExtended(const MachineInstr &MI, unsigned OperandNum) constllvm::HexagonInstrInfo
isPostIncrement(const MachineInstr &MI) const overridellvm::HexagonInstrInfo
isPredicable(const MachineInstr &MI) const overridellvm::HexagonInstrInfo
isPredicated(const MachineInstr &MI) const overridellvm::HexagonInstrInfo
isPredicated(unsigned Opcode) constllvm::HexagonInstrInfo
isPredicatedNew(const MachineInstr &MI) constllvm::HexagonInstrInfo
isPredicatedNew(unsigned Opcode) constllvm::HexagonInstrInfo
isPredicatedTrue(const MachineInstr &MI) constllvm::HexagonInstrInfo
isPredicatedTrue(unsigned Opcode) constllvm::HexagonInstrInfo
isPredicateLate(unsigned Opcode) constllvm::HexagonInstrInfo
isPredictedTaken(unsigned Opcode) constllvm::HexagonInstrInfo
isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const overridellvm::HexagonInstrInfo
isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const overridellvm::HexagonInstrInfo
isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB, unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability) const overridellvm::HexagonInstrInfo
isSaveCalleeSavedRegsCall(const MachineInstr &MI) constllvm::HexagonInstrInfo
isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const overridellvm::HexagonInstrInfo
isSignExtendingLoad(const MachineInstr &MI) constllvm::HexagonInstrInfo
isSolo(const MachineInstr &MI) constllvm::HexagonInstrInfo
isSpillPredRegOp(const MachineInstr &MI) constllvm::HexagonInstrInfo
isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const overridellvm::HexagonInstrInfo
isTailCall(const MachineInstr &MI) const overridellvm::HexagonInstrInfo
isTC1(const MachineInstr &MI) constllvm::HexagonInstrInfo
isTC2(const MachineInstr &MI) constllvm::HexagonInstrInfo
isTC2Early(const MachineInstr &MI) constllvm::HexagonInstrInfo
isTC4x(const MachineInstr &MI) constllvm::HexagonInstrInfo
isToBeScheduledASAP(const MachineInstr &MI1, const MachineInstr &MI2) constllvm::HexagonInstrInfo
isValidAutoIncImm(const EVT VT, const int Offset) constllvm::HexagonInstrInfo
isValidOffset(unsigned Opcode, int Offset, const TargetRegisterInfo *TRI, bool Extend=true) constllvm::HexagonInstrInfo
isVecAcc(const MachineInstr &MI) constllvm::HexagonInstrInfo
isVecALU(const MachineInstr &MI) constllvm::HexagonInstrInfo
isVecUsableNextPacket(const MachineInstr &ProdMI, const MachineInstr &ConsMI) constllvm::HexagonInstrInfo
isZeroExtendingLoad(const MachineInstr &MI) constllvm::HexagonInstrInfo
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const overridellvm::HexagonInstrInfo
mayBeCurLoad(const MachineInstr &MI) constllvm::HexagonInstrInfo
mayBeNewStore(const MachineInstr &MI) constllvm::HexagonInstrInfo
nonDbgBBSize(const MachineBasicBlock *BB) constllvm::HexagonInstrInfo
nonDbgBundleSize(MachineBasicBlock::const_iterator BundleHead) constllvm::HexagonInstrInfo
predCanBeUsedAsDotNew(const MachineInstr &MI, unsigned PredReg) constllvm::HexagonInstrInfo
PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Cond) const overridellvm::HexagonInstrInfo
PredOpcodeHasJMP_c(unsigned Opcode) constllvm::HexagonInstrInfo
predOpcodeHasNot(ArrayRef< MachineOperand > Cond) constllvm::HexagonInstrInfo
producesStall(const MachineInstr &ProdMI, const MachineInstr &ConsMI) constllvm::HexagonInstrInfo
producesStall(const MachineInstr &MI, MachineBasicBlock::const_instr_iterator MII) constllvm::HexagonInstrInfo
reduceLoopCount(MachineBasicBlock &MBB, MachineInstr *IndVar, MachineInstr &Cmp, SmallVectorImpl< MachineOperand > &Cond, SmallVectorImpl< MachineInstr *> &PrevInsts, unsigned Iter, unsigned MaxIter) const overridellvm::HexagonInstrInfo
removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const overridellvm::HexagonInstrInfo
reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const overridellvm::HexagonInstrInfo
reversePrediction(unsigned Opcode) constllvm::HexagonInstrInfo
reversePredSense(MachineInstr &MI) constllvm::HexagonInstrInfo
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const overridellvm::HexagonInstrInfo
SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const overridellvm::HexagonInstrInfo
validateBranchCond(const ArrayRef< MachineOperand > &Cond) constllvm::HexagonInstrInfo