LLVM  6.0.0svn
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llvm::InstructionSelector Class Referenceabstract

Provides the logic to select generic machine instructions. More...

#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"

Inheritance diagram for llvm::InstructionSelector:
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Classes

struct  MatcherInfoTy
 
struct  MatcherState
 

Public Types

using I64ImmediatePredicateFn = bool(*)(int64_t)
 
using APIntImmediatePredicateFn = bool(*)(const APInt &)
 
using APFloatImmediatePredicateFn = bool(*)(const APFloat &)
 

Public Member Functions

virtual ~InstructionSelector ()=default
 
virtual bool select (MachineInstr &I) const =0
 Select the (possibly generic) instruction I to only use target-specific opcodes. More...
 

Protected Types

using ComplexRendererFns = Optional< SmallVector< std::function< void(MachineInstrBuilder &)>, 4 > >
 
using RecordedMIVector = SmallVector< MachineInstr *, 4 >
 
using NewMIVector = SmallVector< MachineInstrBuilder, 4 >
 

Protected Member Functions

 InstructionSelector ()
 
template<class TgtInstructionSelector , class PredicateBitset , class ComplexMatcherMemFn >
bool executeMatchTable (TgtInstructionSelector &ISel, NewMIVector &OutMIs, MatcherState &State, const MatcherInfoTy< PredicateBitset, ComplexMatcherMemFn > &MatcherInfo, const int64_t *MatchTable, const TargetInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI, const PredicateBitset &AvailableFeatures) const
 Execute a given matcher table and return true if the match was successful and false otherwise. More...
 
bool constrainOperandRegToRegClass (MachineInstr &I, unsigned OpIdx, const TargetRegisterClass &RC, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) const
 Constrain a register operand of an instruction I to a specified register class. More...
 
bool constrainSelectedInstRegOperands (MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) const
 Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands to the instruction's register class. More...
 
bool isOperandImmEqual (const MachineOperand &MO, int64_t Value, const MachineRegisterInfo &MRI) const
 
bool isBaseWithConstantOffset (const MachineOperand &Root, const MachineRegisterInfo &MRI) const
 Return true if the specified operand is a G_GEP with a G_CONSTANT on the right-hand side. More...
 
bool isObviouslySafeToFold (MachineInstr &MI) const
 

Detailed Description

Provides the logic to select generic machine instructions.

Definition at line 258 of file InstructionSelector.h.

Member Typedef Documentation

◆ APFloatImmediatePredicateFn

Definition at line 262 of file InstructionSelector.h.

◆ APIntImmediatePredicateFn

Definition at line 261 of file InstructionSelector.h.

◆ ComplexRendererFns

Definition at line 280 of file InstructionSelector.h.

◆ I64ImmediatePredicateFn

Definition at line 260 of file InstructionSelector.h.

◆ NewMIVector

Definition at line 282 of file InstructionSelector.h.

◆ RecordedMIVector

Definition at line 281 of file InstructionSelector.h.

Constructor & Destructor Documentation

◆ ~InstructionSelector()

virtual llvm::InstructionSelector::~InstructionSelector ( )
virtualdefault

◆ InstructionSelector()

InstructionSelector::InstructionSelector ( )
protecteddefault

Member Function Documentation

◆ constrainOperandRegToRegClass()

bool InstructionSelector::constrainOperandRegToRegClass ( MachineInstr I,
unsigned  OpIdx,
const TargetRegisterClass RC,
const TargetInstrInfo TII,
const TargetRegisterInfo TRI,
const RegisterBankInfo RBI 
) const
protected

Constrain a register operand of an instruction I to a specified register class.

This could involve inserting COPYs before (for uses) or after (for defs) and may replace the operand of I.

Returns
whether operand regclass constraining succeeded.

Definition at line 37 of file InstructionSelector.cpp.

References llvm::constrainRegToClass(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), and MRI.

Referenced by executeMatchTable().

◆ constrainSelectedInstRegOperands()

bool InstructionSelector::constrainSelectedInstRegOperands ( MachineInstr I,
const TargetInstrInfo TII,
const TargetRegisterInfo TRI,
const RegisterBankInfo RBI 
) const
protected

◆ executeMatchTable()

template<class TgtInstructionSelector , class PredicateBitset , class ComplexMatcherMemFn >
bool llvm::InstructionSelector::executeMatchTable ( TgtInstructionSelector &  ISel,
NewMIVector OutMIs,
MatcherState State,
const MatcherInfoTy< PredicateBitset, ComplexMatcherMemFn > &  MatcherInfo,
const int64_t *  MatchTable,
const TargetInstrInfo TII,
MachineRegisterInfo MRI,
const TargetRegisterInfo TRI,
const RegisterBankInfo RBI,
const PredicateBitset &  AvailableFeatures 
) const
protected

Execute a given matcher table and return true if the match was successful and false otherwise.

Definition at line 46 of file InstructionSelectorImpl.h.

References llvm::ARM_AM::add, llvm::InstructionSelector::MatcherInfoTy< PredicateBitset, ComplexMatcherMemFn >::APFloatImmPredicateFns, llvm::InstructionSelector::MatcherInfoTy< PredicateBitset, ComplexMatcherMemFn >::APIntImmPredicateFns, assert(), llvm::SmallVectorTemplateCommon< T >::back(), llvm::BuildMI(), llvm::InstructionSelector::MatcherInfoTy< PredicateBitset, ComplexMatcherMemFn >::ComplexPredicates, constrainOperandRegToRegClass(), constrainSelectedInstRegOperands(), llvm::dbgs(), DEBUG, llvm::SmallVectorBase::empty(), llvm::ConstantInt::equalsInt(), llvm::InstructionSelector::MatcherInfoTy< PredicateBitset, ComplexMatcherMemFn >::FeatureBitsets, llvm::MCInstrInfo::get(), llvm::MachineOperand::getCImm(), llvm::MachineFunction::getDataLayout(), llvm::MachineOperand::getIntrinsicID(), llvm::DataLayout::getPointerSizeInBits(), llvm::MachineOperand::getReg(), llvm::RegisterBankInfo::getRegBank(), llvm::RegisterBankInfo::getRegBankFromRegClass(), llvm::TargetRegisterInfo::getRegClass(), llvm::LLT::getSizeInBits(), llvm::MachineRegisterInfo::getType(), llvm::Optional< T >::getValue(), llvm::MachineRegisterInfo::getVRegDef(), llvm::GIM_CheckAPFloatImmPredicate, llvm::GIM_CheckAPIntImmPredicate, llvm::GIM_CheckComplexPattern, llvm::GIM_CheckConstantInt, llvm::GIM_CheckFeatures, llvm::GIM_CheckI64ImmPredicate, llvm::GIM_CheckIntrinsicID, llvm::GIM_CheckIsMBB, llvm::GIM_CheckIsSafeToFold, llvm::GIM_CheckIsSameOperand, llvm::GIM_CheckLiteralInt, llvm::GIM_CheckNonAtomic, llvm::GIM_CheckNumOperands, llvm::GIM_CheckOpcode, llvm::GIM_CheckPointerToAny, llvm::GIM_CheckRegBankForClass, llvm::GIM_CheckType, llvm::GIM_RecordInsn, llvm::GIM_Reject, llvm::GIM_Try, llvm::GIPFP_APFloat_Invalid, llvm::GIPFP_APInt_Invalid, llvm::GIPFP_I64_Invalid, llvm::GIR_AddImm, llvm::GIR_AddImplicitDef, llvm::GIR_AddImplicitUse, llvm::GIR_AddRegister, llvm::GIR_BuildMI, llvm::GIR_ComplexRenderer, llvm::GIR_ComplexSubOperandRenderer, llvm::GIR_ConstrainOperandRC, llvm::GIR_ConstrainSelectedInstOperands, llvm::GIR_Copy, llvm::GIR_CopyConstantAsSImm, llvm::GIR_CopySubReg, llvm::GIR_Done, llvm::GIR_EraseFromParent, llvm::GIR_MergeMemOperands, llvm::GIR_MutateOpcode, llvm::GIU_MergeMemOperands_EndOfList, llvm::Optional< T >::hasValue(), llvm::InstructionSelector::MatcherInfoTy< PredicateBitset, ComplexMatcherMemFn >::I64ImmPredicateFns, llvm::RegState::Implicit, llvm::MachineOperand::isCImm(), llvm::MachineOperand::isIntrinsicID(), isObviouslySafeToFold(), isOperandImmEqual(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::LLT::isPointer(), llvm::MachineOperand::isReg(), llvm_unreachable, llvm::InstructionSelector::MatcherState::MIs, MRI, llvm::NotAtomic, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::pop_back(), llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::SmallVectorTemplateBase< T, isPodLike >::push_back(), llvm::InstructionSelector::MatcherState::Renderers, llvm::SmallVectorTemplateCommon< T >::size(), llvm::SmallVectorTemplateCommon< T, typename >::size(), TII, and llvm::InstructionSelector::MatcherInfoTy< PredicateBitset, ComplexMatcherMemFn >::TypeObjects.

◆ isBaseWithConstantOffset()

bool InstructionSelector::isBaseWithConstantOffset ( const MachineOperand Root,
const MachineRegisterInfo MRI 
) const
protected

Return true if the specified operand is a G_GEP with a G_CONSTANT on the right-hand side.

GlobalISel's separation of pointer and integer types means that we don't need to worry about G_OR with equivalent semantics.

Definition at line 102 of file InstructionSelector.cpp.

References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getVRegDef(), and llvm::MachineOperand::isReg().

◆ isObviouslySafeToFold()

bool InstructionSelector::isObviouslySafeToFold ( MachineInstr MI) const
protected

◆ isOperandImmEqual()

bool InstructionSelector::isOperandImmEqual ( const MachineOperand MO,
int64_t  Value,
const MachineRegisterInfo MRI 
) const
protected

◆ select()

virtual bool llvm::InstructionSelector::select ( MachineInstr I) const
pure virtual

Select the (possibly generic) instruction I to only use target-specific opcodes.

It is OK to insert multiple instructions, but they cannot be generic pre-isel instructions.

Returns
whether selection succeeded.
Precondition
I.getParent() && I.getParent()->getParent()
Postcondition
if returns true: for I in all mutated/inserted instructions: !isPreISelGenericOpcode(I.getOpcode())

Implemented in llvm::AMDGPUInstructionSelector.


The documentation for this class was generated from the following files: