LLVM  7.0.0svn
Public Member Functions | List of all members
llvm::MipsSEInstrInfo Class Reference

#include "Target/Mips/MipsSEInstrInfo.h"

Inheritance diagram for llvm::MipsSEInstrInfo:
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Collaboration diagram for llvm::MipsSEInstrInfo:
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Public Member Functions

 MipsSEInstrInfo (const MipsSubtarget &STI)
 
const MipsRegisterInfogetRegisterInfo () const override
 getRegisterInfo - TargetInstrInfo is a superset of MRegister info. More...
 
unsigned isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const override
 isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot. More...
 
unsigned isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const override
 isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot. More...
 
void copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
 
bool isCopyInstr (const MachineInstr &MI, const MachineOperand *&Src, const MachineOperand *&Dest) const override
 We check for the common case of 'or', as it's MIPS' preferred instruction for GPRs but we have to check the operands to ensure that is the case. More...
 
void storeRegToStack (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const override
 
void loadRegFromStack (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const override
 
bool expandPostRAPseudo (MachineInstr &MI) const override
 
unsigned getOppositeBranchOpc (unsigned Opc) const override
 getOppositeBranchOpc - Return the inverse of the specified opcode, e.g. More...
 
void adjustStackPtr (unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
 Adjust SP by Amount bytes. More...
 
unsigned loadImmediate (int64_t Imm, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, unsigned *NewImm) const
 Emit a series of instructions to load an immediate. More...
 
- Public Member Functions inherited from llvm::MipsInstrInfo
 MipsInstrInfo (const MipsSubtarget &STI, unsigned UncondBrOpc)
 
bool analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
 Branch Analysis. More...
 
unsigned removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
 
unsigned insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
 
bool reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
 reverseBranchCondition - Return the inverse opcode of the specified Branch instruction. More...
 
BranchType analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify, SmallVectorImpl< MachineInstr *> &BranchInstrs) const
 
unsigned getEquivalentCompactForm (const MachineBasicBlock::iterator I) const
 Determine the opcode of a non-delay slot form for a branch if one exists. More...
 
bool isBranchOffsetInRange (unsigned BranchOpc, int64_t BrOffset) const override
 Determine if the branch target is in range. More...
 
bool SafeInForbiddenSlot (const MachineInstr &MI) const
 Predicate to determine if an instruction can go in a forbidden slot. More...
 
bool HasForbiddenSlot (const MachineInstr &MI) const
 Predicate to determine if an instruction has a forbidden slot. More...
 
void insertNoop (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
 Insert nop instruction when hazard condition is found. More...
 
unsigned getInstSizeInBytes (const MachineInstr &MI) const override
 Return the number of bytes of code the specified instruction may be. More...
 
void storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
 
void loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
 
MachineInstrBuilder genInstrWithNewOpc (unsigned NewOpc, MachineBasicBlock::iterator I) const
 Create an instruction which has the same operands and memory operands as MI but has a new opcode. More...
 
bool findCommutedOpIndices (MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
 
bool verifyInstruction (const MachineInstr &MI, StringRef &ErrInfo) const override
 Perform target specific instruction verification. More...
 
std::pair< unsigned, unsigneddecomposeMachineOperandsTargetFlags (unsigned TF) const override
 
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags () const override
 

Additional Inherited Members

- Public Types inherited from llvm::MipsInstrInfo
enum  BranchType {
  BT_None, BT_NoBranch, BT_Uncond, BT_Cond,
  BT_CondUncond, BT_Indirect
}
 
- Static Public Member Functions inherited from llvm::MipsInstrInfo
static const MipsInstrInfocreate (MipsSubtarget &STI)
 
- Protected Member Functions inherited from llvm::MipsInstrInfo
bool isZeroImm (const MachineOperand &op) const
 
MachineMemOperandGetMemOperand (MachineBasicBlock &MBB, int FI, MachineMemOperand::Flags Flags) const
 
- Protected Attributes inherited from llvm::MipsInstrInfo
const MipsSubtargetSubtarget
 
unsigned UncondBrOpc
 

Detailed Description

Definition at line 22 of file MipsSEInstrInfo.h.

Constructor & Destructor Documentation

◆ MipsSEInstrInfo()

MipsSEInstrInfo::MipsSEInstrInfo ( const MipsSubtarget STI)
explicit

Definition at line 28 of file MipsSEInstrInfo.cpp.

Referenced by llvm::createMipsSEInstrInfo().

Member Function Documentation

◆ adjustStackPtr()

void MipsSEInstrInfo::adjustStackPtr ( unsigned  SP,
int64_t  Amount,
MachineBasicBlock MBB,
MachineBasicBlock::iterator  I 
) const
overridevirtual

◆ copyPhysReg()

void MipsSEInstrInfo::copyPhysReg ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
const DebugLoc DL,
unsigned  DestReg,
unsigned  SrcReg,
bool  KillSrc 
) const
override

◆ expandPostRAPseudo()

bool MipsSEInstrInfo::expandPostRAPseudo ( MachineInstr MI) const
override

◆ getOppositeBranchOpc()

unsigned MipsSEInstrInfo::getOppositeBranchOpc ( unsigned  Opc) const
overridevirtual

getOppositeBranchOpc - Return the inverse of the specified opcode, e.g.

turning BEQ to BNE.

Implements llvm::MipsInstrInfo.

Definition at line 482 of file MipsSEInstrInfo.cpp.

References llvm_unreachable.

◆ getRegisterInfo()

const MipsRegisterInfo & MipsSEInstrInfo::getRegisterInfo ( ) const
overridevirtual

getRegisterInfo - TargetInstrInfo is a superset of MRegister info.

As such, whenever a client has an instance of instruction info, it should always be able to get register info as well (through this method).

Implements llvm::MipsInstrInfo.

Definition at line 32 of file MipsSEInstrInfo.cpp.

Referenced by loadImmediate().

◆ isCopyInstr()

bool MipsSEInstrInfo::isCopyInstr ( const MachineInstr MI,
const MachineOperand *&  Src,
const MachineOperand *&  Dest 
) const
override

We check for the common case of 'or', as it's MIPS' preferred instruction for GPRs but we have to check the operands to ensure that is the case.

Other move instructions for MIPS are directly identifiable.

Definition at line 220 of file MipsSEInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::isImm(), llvm::MachineInstr::isMoveReg(), isORCopyInst(), isReadOrWriteToDSPReg(), and storeRegToStack().

◆ isLoadFromStackSlot()

unsigned MipsSEInstrInfo::isLoadFromStackSlot ( const MachineInstr MI,
int &  FrameIndex 
) const
override

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot.

If not, return 0. This predicate must return 0 if the instruction has any side effects other than loading from the stack slot.

Definition at line 41 of file MipsSEInstrInfo.cpp.

References llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), llvm::MipsInstrInfo::isZeroImm(), and llvm::ARM_MB::LD.

◆ isStoreToStackSlot()

unsigned MipsSEInstrInfo::isStoreToStackSlot ( const MachineInstr MI,
int &  FrameIndex 
) const
override

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot.

If not, return 0. This predicate must return 0 if the instruction has any side effects other than storing to the stack slot.

Definition at line 63 of file MipsSEInstrInfo.cpp.

References llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), and llvm::MipsInstrInfo::isZeroImm().

◆ loadImmediate()

unsigned MipsSEInstrInfo::loadImmediate ( int64_t  Imm,
MachineBasicBlock MBB,
MachineBasicBlock::iterator  II,
const DebugLoc DL,
unsigned NewImm 
) const

Emit a series of instructions to load an immediate.

This function generates the sequence of instructions needed to get the result of adding register REG and immediate IMM.

If NewImm is a non-NULL parameter, the last instruction is not emitted, but instead its immediate operand is returned in NewImm.

Definition at line 597 of file MipsSEInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::MipsAnalyzeImmediate::Analyze(), assert(), B, llvm::SmallVectorTemplateCommon< T, typename >::begin(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::RegState::Define, llvm::SmallVectorTemplateCommon< T, typename >::end(), llvm::MipsSubtarget::getABI(), llvm::getKillRegState(), llvm::MachineBasicBlock::getParent(), llvm::MipsABIInfo::GetPtrAdduOp(), llvm::MachineOperand::getReg(), getRegClass(), llvm::MachineFunction::getRegInfo(), getRegisterInfo(), llvm::MCRegisterInfo::getSubReg(), llvm::MachineFunction::getTarget(), llvm::MipsSubtarget::hasMips32r2(), llvm::MipsSubtarget::hasMTHC1(), I, llvm::MipsSubtarget::isABI_FPXX(), llvm::MipsSubtarget::isABI_N64(), llvm::MipsSubtarget::isFP64bit(), llvm::MipsSubtarget::isGP64bit(), llvm::MachineOperand::isKill(), llvm::TargetMachine::isPositionIndependent(), llvm::RegState::Kill, llvm_unreachable, N, llvm::MCInstrDesc::NumOperands, RA, Reg, llvm::SmallVectorTemplateCommon< T, typename >::size(), llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Size, SubReg, llvm::MipsInstrInfo::Subtarget, llvm::SystemZISD::TM, TRI, llvm::RegState::Undef, and llvm::MipsSubtarget::useOddSPReg().

Referenced by adjustStackPtr(), and getLoadStoreOffsetAlign().

◆ loadRegFromStack()

void MipsSEInstrInfo::loadRegFromStack ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
unsigned  DestReg,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI,
int64_t  Offset 
) const
overridevirtual

◆ storeRegToStack()

void MipsSEInstrInfo::storeRegToStack ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
unsigned  SrcReg,
bool  isKill,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI,
int64_t  Offset 
) const
overridevirtual

The documentation for this class was generated from the following files: