LLVM  6.0.0svn
Public Types | Public Member Functions | List of all members
llvm::R600InstrInfo Class Referencefinal

#include "Target/AMDGPU/R600InstrInfo.h"

Inheritance diagram for llvm::R600InstrInfo:
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Public Types

enum  BankSwizzle {
  ALU_VEC_012_SCL_210 = 0, ALU_VEC_021_SCL_122, ALU_VEC_120_SCL_212, ALU_VEC_102_SCL_221,
  ALU_VEC_201, ALU_VEC_210
}
 

Public Member Functions

 R600InstrInfo (const R600Subtarget &)
 
const R600RegisterInfogetRegisterInfo () const
 
void copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
 
bool isLegalToSplitMBBAt (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const override
 
bool isReductionOp (unsigned opcode) const
 
bool isCubeOp (unsigned opcode) const
 
bool isALUInstr (unsigned Opcode) const
 
bool hasInstrModifiers (unsigned Opcode) const
 
bool isLDSInstr (unsigned Opcode) const
 
bool isLDSRetInstr (unsigned Opcode) const
 
bool canBeConsideredALU (const MachineInstr &MI) const
 
bool isTransOnly (unsigned Opcode) const
 
bool isTransOnly (const MachineInstr &MI) const
 
bool isVectorOnly (unsigned Opcode) const
 
bool isVectorOnly (const MachineInstr &MI) const
 
bool isExport (unsigned Opcode) const
 
bool usesVertexCache (unsigned Opcode) const
 
bool usesVertexCache (const MachineInstr &MI) const
 
bool usesTextureCache (unsigned Opcode) const
 
bool usesTextureCache (const MachineInstr &MI) const
 
bool mustBeLastInClause (unsigned Opcode) const
 
bool usesAddressRegister (MachineInstr &MI) const
 
bool definesAddressRegister (MachineInstr &MI) const
 
bool readsLDSSrcReg (const MachineInstr &MI) const
 
int getSelIdx (unsigned Opcode, unsigned SrcIdx) const
 
SmallVector< std::pair< MachineOperand *, int64_t >, 3 > getSrcs (MachineInstr &MI) const
 
unsigned isLegalUpTo (const std::vector< std::vector< std::pair< int, unsigned > > > &IGSrcs, const std::vector< R600InstrInfo::BankSwizzle > &Swz, const std::vector< std::pair< int, unsigned > > &TransSrcs, R600InstrInfo::BankSwizzle TransSwz) const
 returns how many MIs (whose inputs are represented by IGSrcs) can be packed in the same Instruction Group while meeting read port limitations given a Swz swizzle sequence. More...
 
bool FindSwizzleForVectorSlot (const std::vector< std::vector< std::pair< int, unsigned > > > &IGSrcs, std::vector< R600InstrInfo::BankSwizzle > &SwzCandidate, const std::vector< std::pair< int, unsigned > > &TransSrcs, R600InstrInfo::BankSwizzle TransSwz) const
 Enumerate all possible Swizzle sequence to find one that can meet all read port requirements. More...
 
bool fitsReadPortLimitations (const std::vector< MachineInstr *> &MIs, const DenseMap< unsigned, unsigned > &PV, std::vector< BankSwizzle > &BS, bool isLastAluTrans) const
 Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210 returns true and the first (in lexical order) BankSwizzle affectation starting from the one already provided in the Instruction Group MIs that fits Read Port limitations in BS if available. More...
 
bool fitsConstReadLimitations (const std::vector< MachineInstr *> &) const
 An instruction group can only access 2 channel pair (either [XY] or [ZW]) from KCache bank on R700+. More...
 
bool fitsConstReadLimitations (const std::vector< unsigned > &) const
 Same but using const index set instead of MI set. More...
 
bool isVector (const MachineInstr &MI) const
 Vector instructions are instructions that must fill all instruction slots within an instruction group. More...
 
bool isMov (unsigned Opcode) const
 
DFAPacketizerCreateTargetScheduleState (const TargetSubtargetInfo &) const override
 
bool reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
 
bool analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
 
unsigned insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
 
unsigned removeBranch (MachineBasicBlock &MBB, int *BytesRemvoed=nullptr) const override
 
bool isPredicated (const MachineInstr &MI) const override
 
bool isPredicable (const MachineInstr &MI) const override
 
bool isProfitableToDupForIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
 
bool isProfitableToIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
 
bool isProfitableToIfCvt (MachineBasicBlock &TMBB, unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB, unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability) const override
 
bool DefinesPredicate (MachineInstr &MI, std::vector< MachineOperand > &Pred) const override
 
bool isProfitableToUnpredicate (MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
 
bool PredicateInstruction (MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
 
unsigned int getPredicationCost (const MachineInstr &) const override
 
unsigned int getInstrLatency (const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
 
bool expandPostRAPseudo (MachineInstr &MI) const override
 
void reserveIndirectRegisters (BitVector &Reserved, const MachineFunction &MF) const
 Reserve the registers that may be accesed using indirect addressing. More...
 
unsigned calculateIndirectAddress (unsigned RegIndex, unsigned Channel) const
 Calculate the "Indirect Address" for the given RegIndex and Channel. More...
 
const TargetRegisterClassgetIndirectAddrRegClass () const
 
int getIndirectIndexBegin (const MachineFunction &MF) const
 
int getIndirectIndexEnd (const MachineFunction &MF) const
 
MachineInstrBuilder buildIndirectWrite (MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned ValueReg, unsigned Address, unsigned OffsetReg) const
 Build instruction(s) for an indirect register write. More...
 
MachineInstrBuilder buildIndirectRead (MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned ValueReg, unsigned Address, unsigned OffsetReg) const
 Build instruction(s) for an indirect register read. More...
 
unsigned getMaxAlusPerClause () const
 
MachineInstrBuilder buildDefaultInstruction (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned Opcode, unsigned DstReg, unsigned Src0Reg, unsigned Src1Reg=0) const
 buildDefaultInstruction - This function returns a MachineInstr with all the instruction modifiers initialized to their default values. More...
 
MachineInstrbuildSlotOfVectorInstruction (MachineBasicBlock &MBB, MachineInstr *MI, unsigned Slot, unsigned DstReg) const
 
MachineInstrbuildMovImm (MachineBasicBlock &BB, MachineBasicBlock::iterator I, unsigned DstReg, uint64_t Imm) const
 
MachineInstrbuildMovInstr (MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned DstReg, unsigned SrcReg) const
 
int getOperandIdx (const MachineInstr &MI, unsigned Op) const
 Get the index of Op in the MachineInstr. More...
 
int getOperandIdx (unsigned Opcode, unsigned Op) const
 Get the index of Op for the given Opcode. More...
 
void setImmOperand (MachineInstr &MI, unsigned Op, int64_t Imm) const
 Helper function for setting instruction flag values. More...
 
void addFlag (MachineInstr &MI, unsigned Operand, unsigned Flag) const
 Add one of the MO_FLAG* flags to the specified Operand. More...
 
bool isFlagSet (const MachineInstr &MI, unsigned Operand, unsigned Flag) const
 Determine if the specified Flag is set on this Operand. More...
 
MachineOperandgetFlagOp (MachineInstr &MI, unsigned SrcIdx=0, unsigned Flag=0) const
 
void clearFlag (MachineInstr &MI, unsigned Operand, unsigned Flag) const
 Clear the specified flag on the instruction. More...
 
bool isRegisterStore (const MachineInstr &MI) const
 
bool isRegisterLoad (const MachineInstr &MI) const
 
- Public Member Functions inherited from llvm::AMDGPUInstrInfo
 AMDGPUInstrInfo (const AMDGPUSubtarget &st)
 
bool shouldScheduleLoadsNear (SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override
 
int pseudoToMCOpcode (int Opcode) const
 Return a target-specific opcode if Opcode is a pseudo instruction. More...
 
int getMaskedMIMGOp (uint16_t Opcode, unsigned Channels) const
 Given a MIMG Opcode that writes all 4 channels, return the equivalent opcode that writes Channels Channels. More...
 

Additional Inherited Members

- Protected Attributes inherited from llvm::AMDGPUInstrInfo
AMDGPUAS AMDGPUASI
 

Detailed Description

Definition at line 37 of file R600InstrInfo.h.

Member Enumeration Documentation

◆ BankSwizzle

Enumerator
ALU_VEC_012_SCL_210 
ALU_VEC_021_SCL_122 
ALU_VEC_120_SCL_212 
ALU_VEC_102_SCL_221 
ALU_VEC_201 
ALU_VEC_210 

Definition at line 58 of file R600InstrInfo.h.

Constructor & Destructor Documentation

◆ R600InstrInfo()

R600InstrInfo::R600InstrInfo ( const R600Subtarget ST)
explicit

Definition at line 49 of file R600InstrInfo.cpp.

Member Function Documentation

◆ addFlag()

void R600InstrInfo::addFlag ( MachineInstr MI,
unsigned  Operand,
unsigned  Flag 
) const

◆ analyzeBranch()

bool R600InstrInfo::analyzeBranch ( MachineBasicBlock MBB,
MachineBasicBlock *&  TBB,
MachineBasicBlock *&  FBB,
SmallVectorImpl< MachineOperand > &  Cond,
bool  AllowModify 
) const
override

◆ buildDefaultInstruction()

MachineInstrBuilder R600InstrInfo::buildDefaultInstruction ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
unsigned  Opcode,
unsigned  DstReg,
unsigned  Src0Reg,
unsigned  Src1Reg = 0 
) const

buildDefaultInstruction - This function returns a MachineInstr with all the instruction modifiers initialized to their default values.

You can use this function to avoid manually specifying each instruction modifier operand when building a new instruction.

Returns
a MachineInstr with all the instruction modifiers initialized to their default values.

Definition at line 1234 of file R600InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), and llvm::MachineBasicBlock::findDebugLoc().

Referenced by buildIndirectRead(), buildIndirectWrite(), buildMovImm(), buildMovInstr(), buildSlotOfVectorInstruction(), copyPhysReg(), and llvm::R600TargetLowering::EmitInstrWithCustomInserter().

◆ buildIndirectRead()

MachineInstrBuilder R600InstrInfo::buildIndirectRead ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
unsigned  ValueReg,
unsigned  Address,
unsigned  OffsetReg 
) const

Build instruction(s) for an indirect register read.

Returns
The instruction that performs the indirect register read

Definition at line 1141 of file R600InstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), buildDefaultInstruction(), llvm::RegState::Implicit, llvm::RegState::Kill, llvm_unreachable, setImmOperand(), and write().

◆ buildIndirectWrite()

MachineInstrBuilder R600InstrInfo::buildIndirectWrite ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
unsigned  ValueReg,
unsigned  Address,
unsigned  OffsetReg 
) const

Build instruction(s) for an indirect register write.

Returns
The instruction that performs the indirect register write

Definition at line 1109 of file R600InstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::dwarf::syntax::Address, buildDefaultInstruction(), I, llvm::RegState::Implicit, llvm::RegState::Kill, llvm_unreachable, setImmOperand(), and write().

◆ buildMovImm()

MachineInstr * R600InstrInfo::buildMovImm ( MachineBasicBlock BB,
MachineBasicBlock::iterator  I,
unsigned  DstReg,
uint64_t  Imm 
) const

◆ buildMovInstr()

MachineInstr * R600InstrInfo::buildMovInstr ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
unsigned  DstReg,
unsigned  SrcReg 
) const

Definition at line 1371 of file R600InstrInfo.cpp.

References buildDefaultInstruction().

Referenced by expandPostRAPseudo().

◆ buildSlotOfVectorInstruction()

MachineInstr * R600InstrInfo::buildSlotOfVectorInstruction ( MachineBasicBlock MBB,
MachineInstr MI,
unsigned  Slot,
unsigned  DstReg 
) const

◆ calculateIndirectAddress()

unsigned R600InstrInfo::calculateIndirectAddress ( unsigned  RegIndex,
unsigned  Channel 
) const

Calculate the "Indirect Address" for the given RegIndex and Channel.

We model indirect addressing using a virtual address space that can be accesed with loads and stores. The "Indirect Address" is the memory address in this virtual address space that maps to the given RegIndex and Channel.

Definition at line 1012 of file R600InstrInfo.cpp.

References assert().

Referenced by expandPostRAPseudo().

◆ canBeConsideredALU()

bool R600InstrInfo::canBeConsideredALU ( const MachineInstr MI) const
Returns
true if this Opcode represents an ALU instruction or an instruction that will be lowered in ExpandSpecialInstrs Pass.

Definition at line 154 of file R600InstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), isALUInstr(), isCubeOp(), and isVector().

◆ clearFlag()

void R600InstrInfo::clearFlag ( MachineInstr MI,
unsigned  Operand,
unsigned  Flag 
) const

Clear the specified flag on the instruction.

Definition at line 1483 of file R600InstrInfo.cpp.

References getFlagOp(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), HAS_NATIVE_OPERANDS, NUM_MO_FLAGS, and llvm::MachineOperand::setImm().

Referenced by addFlag(), and removeBranch().

◆ copyPhysReg()

void R600InstrInfo::copyPhysReg ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
const DebugLoc DL,
unsigned  DestReg,
unsigned  SrcReg,
bool  KillSrc 
) const
override

◆ CreateTargetScheduleState()

DFAPacketizer * R600InstrInfo::CreateTargetScheduleState ( const TargetSubtargetInfo STI) const
override

◆ definesAddressRegister()

bool R600InstrInfo::definesAddressRegister ( MachineInstr MI) const

◆ DefinesPredicate()

bool R600InstrInfo::DefinesPredicate ( MachineInstr MI,
std::vector< MachineOperand > &  Pred 
) const
override

Definition at line 961 of file R600InstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), and isPredicateSetter().

◆ expandPostRAPseudo()

bool R600InstrInfo::expandPostRAPseudo ( MachineInstr MI) const
override

◆ FindSwizzleForVectorSlot()

bool R600InstrInfo::FindSwizzleForVectorSlot ( const std::vector< std::vector< std::pair< int, unsigned > > > &  IGSrcs,
std::vector< R600InstrInfo::BankSwizzle > &  SwzCandidate,
const std::vector< std::pair< int, unsigned > > &  TransSrcs,
R600InstrInfo::BankSwizzle  TransSwz 
) const

Enumerate all possible Swizzle sequence to find one that can meet all read port requirements.

Definition at line 493 of file R600InstrInfo.cpp.

References isLegalUpTo(), and NextPossibleSolution().

Referenced by fitsReadPortLimitations().

◆ fitsConstReadLimitations() [1/2]

bool R600InstrInfo::fitsConstReadLimitations ( const std::vector< MachineInstr *> &  MIs) const

An instruction group can only access 2 channel pair (either [XY] or [ZW]) from KCache bank on R700+.

This function check if MI set in input meet this limitations

Definition at line 603 of file R600InstrInfo.cpp.

References contains(), llvm::R600RegisterInfo::getHWRegChan(), llvm::MachineInstr::getOpcode(), getSrcs(), llvm::SmallSet< T, N, C >::insert(), isALUInstr(), and llvm::SmallSet< T, N, C >::size().

Referenced by llvm::R600TargetLowering::PerformDAGCombine(), and llvm::R600SchedStrategy::releaseBottomNode().

◆ fitsConstReadLimitations() [2/2]

bool R600InstrInfo::fitsConstReadLimitations ( const std::vector< unsigned > &  Consts) const

Same but using const index set instead of MI set.

Definition at line 578 of file R600InstrInfo.cpp.

References assert().

◆ fitsReadPortLimitations()

bool R600InstrInfo::fitsReadPortLimitations ( const std::vector< MachineInstr *> &  MIs,
const DenseMap< unsigned, unsigned > &  PV,
std::vector< BankSwizzle > &  BS,
bool  isLastAluTrans 
) const

Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210 returns true and the first (in lexical order) BankSwizzle affectation starting from the one already provided in the Instruction Group MIs that fits Read Port limitations in BS if available.

Otherwise returns false and undefined content in BS. isLastAluTrans should be set if the last Alu of MIs will be executed on Trans ALU. In this case, ValidTSwizzle returns the BankSwizzle value to apply to the last instruction. PV holds GPR to PV registers in the Instruction Group MIs.

Definition at line 530 of file R600InstrInfo.cpp.

References ALU_VEC_012_SCL_210, ALU_VEC_021_SCL_122, ALU_VEC_102_SCL_221, ALU_VEC_120_SCL_212, FindSwizzleForVectorSlot(), getOperandIdx(), and isConstCompatible().

◆ getFlagOp()

MachineOperand & R600InstrInfo::getFlagOp ( MachineInstr MI,
unsigned  SrcIdx = 0,
unsigned  Flag = 0 
) const
Parameters
SrcIdxThe register source to set the flag on (e.g src0, src1, src2)
FlagThe flag being set.
Returns
the operand containing the flags for this instruction.

Definition at line 1397 of file R600InstrInfo.cpp.

References assert(), GET_FLAG_OPERAND_IDX, llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getOperandIdx(), HAS_NATIVE_OPERANDS, llvm::MachineOperand::isImm(), MO_FLAG_ABS, MO_FLAG_CLAMP, MO_FLAG_LAST, MO_FLAG_MASK, MO_FLAG_NEG, MO_FLAG_NOT_LAST, R600_InstFlag::OP3, and write().

Referenced by addFlag(), and clearFlag().

◆ getIndirectAddrRegClass()

const TargetRegisterClass * R600InstrInfo::getIndirectAddrRegClass ( ) const
Returns
The register class to be used for loading and storing values from an "Indirect Address" .

Definition at line 1105 of file R600InstrInfo.cpp.

Referenced by expandPostRAPseudo(), and getIndirectIndexBegin().

◆ getIndirectIndexBegin()

int R600InstrInfo::getIndirectIndexBegin ( const MachineFunction MF) const

◆ getIndirectIndexEnd()

int R600InstrInfo::getIndirectIndexEnd ( const MachineFunction MF) const
Returns
the largest register index that will be accessed by an indirect read or write or -1 if indirect addressing is not used by this program.

Definition at line 1208 of file R600InstrInfo.cpp.

References llvm::R600FrameLowering::getFrameIndexReference(), llvm::MachineFunction::getFrameInfo(), llvm::R600Subtarget::getFrameLowering(), getIndirectIndexBegin(), llvm::MachineFrameInfo::getNumObjects(), llvm::MachineFunction::getSubtarget(), and llvm::MachineFrameInfo::hasVarSizedObjects().

Referenced by reserveIndirectRegisters().

◆ getInstrLatency()

unsigned int R600InstrInfo::getInstrLatency ( const InstrItineraryData ItinData,
const MachineInstr MI,
unsigned PredCost = nullptr 
) const
override

Definition at line 1004 of file R600InstrInfo.cpp.

◆ getMaxAlusPerClause()

unsigned R600InstrInfo::getMaxAlusPerClause ( ) const

Definition at line 1230 of file R600InstrInfo.cpp.

◆ getOperandIdx() [1/2]

int R600InstrInfo::getOperandIdx ( const MachineInstr MI,
unsigned  Op 
) const

◆ getOperandIdx() [2/2]

int R600InstrInfo::getOperandIdx ( unsigned  Opcode,
unsigned  Op 
) const

Get the index of Op for the given Opcode.

Returns
-1 if the Instruction does not contain the specified Op.

Definition at line 1381 of file R600InstrInfo.cpp.

References llvm::AMDGPU::getNamedOperandIdx().

◆ getPredicationCost()

unsigned int R600InstrInfo::getPredicationCost ( const MachineInstr ) const
override

Definition at line 1000 of file R600InstrInfo.cpp.

◆ getRegisterInfo()

const R600RegisterInfo& llvm::R600InstrInfo::getRegisterInfo ( ) const
inline

◆ getSelIdx()

int R600InstrInfo::getSelIdx ( unsigned  Opcode,
unsigned  SrcIdx 
) const
Returns
The operand Index for the Sel operand given an index to one of the instruction's src operands.

Definition at line 250 of file R600InstrInfo.cpp.

References getOperandIdx().

Referenced by llvm::R600TargetLowering::PerformDAGCombine().

◆ getSrcs()

SmallVector< std::pair< MachineOperand *, int64_t >, 3 > R600InstrInfo::getSrcs ( MachineInstr MI) const

◆ hasInstrModifiers()

bool R600InstrInfo::hasInstrModifiers ( unsigned  Opcode) const

◆ insertBranch()

unsigned R600InstrInfo::insertBranch ( MachineBasicBlock MBB,
MachineBasicBlock TBB,
MachineBasicBlock FBB,
ArrayRef< MachineOperand Cond,
const DebugLoc DL,
int *  BytesAdded = nullptr 
) const
override

◆ isALUInstr()

bool R600InstrInfo::isALUInstr ( unsigned  Opcode) const
Returns
true if this Opcode represents an ALU instruction.

Definition at line 128 of file R600InstrInfo.cpp.

References R600_InstFlag::ALU_INST.

Referenced by canBeConsideredALU(), fitsConstReadLimitations(), readsLDSSrcReg(), and llvm::R600SchedStrategy::releaseBottomNode().

◆ isCubeOp()

bool R600InstrInfo::isCubeOp ( unsigned  opcode) const

◆ isExport()

bool R600InstrInfo::isExport ( unsigned  Opcode) const

Definition at line 190 of file R600InstrInfo.cpp.

References R600_InstFlag::IS_EXPORT.

◆ isFlagSet()

bool llvm::R600InstrInfo::isFlagSet ( const MachineInstr MI,
unsigned  Operand,
unsigned  Flag 
) const

Determine if the specified Flag is set on this Operand.

◆ isLDSInstr()

bool R600InstrInfo::isLDSInstr ( unsigned  Opcode) const

◆ isLDSRetInstr()

bool R600InstrInfo::isLDSRetInstr ( unsigned  Opcode) const

◆ isLegalToSplitMBBAt()

bool R600InstrInfo::isLegalToSplitMBBAt ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MBBI 
) const
override
Returns
true if MBBI can be moved into a new basic.

Definition at line 91 of file R600InstrInfo.cpp.

References E, I, llvm::R600RegisterInfo::isPhysRegLiveAcrossClauses(), and llvm::TargetRegisterInfo::isVirtualRegister().

◆ isLegalUpTo()

unsigned R600InstrInfo::isLegalUpTo ( const std::vector< std::vector< std::pair< int, unsigned > > > &  IGSrcs,
const std::vector< R600InstrInfo::BankSwizzle > &  Swz,
const std::vector< std::pair< int, unsigned > > &  TransSrcs,
R600InstrInfo::BankSwizzle  TransSwz 
) const

returns how many MIs (whose inputs are represented by IGSrcs) can be packed in the same Instruction Group while meeting read port limitations given a Swz swizzle sequence.

Definition at line 424 of file R600InstrInfo.cpp.

References ALU_VEC_012_SCL_210, ALU_VEC_021_SCL_122, GET_REG_INDEX, getTransSwizzle(), and Swizzle().

Referenced by FindSwizzleForVectorSlot().

◆ isMov()

bool R600InstrInfo::isMov ( unsigned  Opcode) const

Definition at line 102 of file R600InstrInfo.cpp.

◆ isPredicable()

bool R600InstrInfo::isPredicable ( const MachineInstr MI) const
override

◆ isPredicated()

bool R600InstrInfo::isPredicated ( const MachineInstr MI) const
override

◆ isProfitableToDupForIfCvt()

bool R600InstrInfo::isProfitableToDupForIfCvt ( MachineBasicBlock MBB,
unsigned  NumCycles,
BranchProbability  Probability 
) const
override

Definition at line 914 of file R600InstrInfo.cpp.

◆ isProfitableToIfCvt() [1/2]

bool R600InstrInfo::isProfitableToIfCvt ( MachineBasicBlock MBB,
unsigned  NumCycles,
unsigned  ExtraPredCycles,
BranchProbability  Probability 
) const
override

Definition at line 895 of file R600InstrInfo.cpp.

◆ isProfitableToIfCvt() [2/2]

bool R600InstrInfo::isProfitableToIfCvt ( MachineBasicBlock TMBB,
unsigned  NumTCycles,
unsigned  ExtraTCycles,
MachineBasicBlock FMBB,
unsigned  NumFCycles,
unsigned  ExtraFCycles,
BranchProbability  Probability 
) const
override

Definition at line 903 of file R600InstrInfo.cpp.

◆ isProfitableToUnpredicate()

bool R600InstrInfo::isProfitableToUnpredicate ( MachineBasicBlock TMBB,
MachineBasicBlock FMBB 
) const
override

Definition at line 922 of file R600InstrInfo.cpp.

◆ isReductionOp()

bool R600InstrInfo::isReductionOp ( unsigned  opcode) const

Definition at line 113 of file R600InstrInfo.cpp.

Referenced by llvm::R600SchedStrategy::releaseBottomNode().

◆ isRegisterLoad()

bool llvm::R600InstrInfo::isRegisterLoad ( const MachineInstr MI) const
inline

◆ isRegisterStore()

bool llvm::R600InstrInfo::isRegisterStore ( const MachineInstr MI) const
inline

◆ isTransOnly() [1/2]

bool R600InstrInfo::isTransOnly ( unsigned  Opcode) const

◆ isTransOnly() [2/2]

bool R600InstrInfo::isTransOnly ( const MachineInstr MI) const

Definition at line 178 of file R600InstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), and isTransOnly().

◆ isVector()

bool R600InstrInfo::isVector ( const MachineInstr MI) const

Vector instructions are instructions that must fill all instruction slots within an instruction group.

Definition at line 52 of file R600InstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), and R600_InstFlag::VECTOR.

Referenced by canBeConsideredALU(), isPredicable(), and llvm::R600SchedStrategy::releaseBottomNode().

◆ isVectorOnly() [1/2]

bool R600InstrInfo::isVectorOnly ( unsigned  Opcode) const

Definition at line 182 of file R600InstrInfo.cpp.

Referenced by isVectorOnly(), and llvm::R600SchedStrategy::releaseBottomNode().

◆ isVectorOnly() [2/2]

bool R600InstrInfo::isVectorOnly ( const MachineInstr MI) const

Definition at line 186 of file R600InstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), and isVectorOnly().

◆ mustBeLastInClause()

bool R600InstrInfo::mustBeLastInClause ( unsigned  Opcode) const

Definition at line 215 of file R600InstrInfo.cpp.

◆ PredicateInstruction()

bool R600InstrInfo::PredicateInstruction ( MachineInstr MI,
ArrayRef< MachineOperand Pred 
) const
override

◆ readsLDSSrcReg()

bool R600InstrInfo::readsLDSSrcReg ( const MachineInstr MI) const

◆ removeBranch()

unsigned R600InstrInfo::removeBranch ( MachineBasicBlock MBB,
int *  BytesRemvoed = nullptr 
) const
override

◆ reserveIndirectRegisters()

void R600InstrInfo::reserveIndirectRegisters ( BitVector Reserved,
const MachineFunction MF 
) const

◆ reverseBranchCondition()

bool R600InstrInfo::reverseBranchCondition ( SmallVectorImpl< MachineOperand > &  Cond) const
override

◆ setImmOperand()

void R600InstrInfo::setImmOperand ( MachineInstr MI,
unsigned  Op,
int64_t  Imm 
) const

◆ usesAddressRegister()

bool R600InstrInfo::usesAddressRegister ( MachineInstr MI) const

◆ usesTextureCache() [1/2]

bool R600InstrInfo::usesTextureCache ( unsigned  Opcode) const

◆ usesTextureCache() [2/2]

bool R600InstrInfo::usesTextureCache ( const MachineInstr MI) const

◆ usesVertexCache() [1/2]

bool R600InstrInfo::usesVertexCache ( unsigned  Opcode) const

◆ usesVertexCache() [2/2]

bool R600InstrInfo::usesVertexCache ( const MachineInstr MI) const

The documentation for this class was generated from the following files: