LLVM  10.0.0svn
llvm::RISCVInstrInfo Member List

This is the complete list of members for llvm::RISCVInstrInfo, including all inherited members.

analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const overridellvm::RISCVInstrInfo
copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DstReg, unsigned SrcReg, bool KillSrc) const overridellvm::RISCVInstrInfo
getBranchDestBlock(const MachineInstr &MI) const overridellvm::RISCVInstrInfo
getInstSizeInBytes(const MachineInstr &MI) const overridellvm::RISCVInstrInfo
insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &dl, int *BytesAdded=nullptr) const overridellvm::RISCVInstrInfo
insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS=nullptr) const overridellvm::RISCVInstrInfo
isAsCheapAsAMove(const MachineInstr &MI) const overridellvm::RISCVInstrInfo
isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const overridellvm::RISCVInstrInfo
isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const overridellvm::RISCVInstrInfo
isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const overridellvm::RISCVInstrInfo
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DstReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const overridellvm::RISCVInstrInfo
movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DstReg, uint64_t Val, MachineInstr::MIFlag Flag=MachineInstr::NoFlags) constllvm::RISCVInstrInfo
removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const overridellvm::RISCVInstrInfo
reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const overridellvm::RISCVInstrInfo
RISCVInstrInfo()llvm::RISCVInstrInfo
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool IsKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const overridellvm::RISCVInstrInfo