LLVM  8.0.0svn
Public Types | Public Member Functions | Static Public Member Functions | Protected Member Functions | List of all members
llvm::SIInstrInfo Class Referencefinal

#include "Target/AMDGPU/SIInstrInfo.h"

Inheritance diagram for llvm::SIInstrInfo:
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Public Types

enum  TargetOperandFlags {
  MO_MASK = 0x7, MO_NONE = 0, MO_GOTPCREL = 1, MO_GOTPCREL32 = 2,
  MO_GOTPCREL32_LO = 2, MO_GOTPCREL32_HI = 3, MO_REL32 = 4, MO_REL32_LO = 4,
  MO_REL32_HI = 5
}
 

Public Member Functions

unsigned buildExtractSubReg (MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, unsigned SubIdx, const TargetRegisterClass *SubRC) const
 
MachineOperand buildExtractSubRegOrImm (MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, unsigned SubIdx, const TargetRegisterClass *SubRC) const
 
 SIInstrInfo (const GCNSubtarget &ST)
 
const SIRegisterInfogetRegisterInfo () const
 
bool isReallyTriviallyReMaterializable (const MachineInstr &MI, AliasAnalysis *AA) const override
 
bool areLoadsFromSameBasePtr (SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
 
bool getMemOpBaseRegImmOfs (MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, const TargetRegisterInfo *TRI) const final
 
bool shouldClusterMemOps (MachineInstr &FirstLdSt, unsigned BaseReg1, MachineInstr &SecondLdSt, unsigned BaseReg2, unsigned NumLoads) const override
 
bool shouldScheduleLoadsNear (SDNode *Load0, SDNode *Load1, int64_t Offset0, int64_t Offset1, unsigned NumLoads) const override
 
void copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
 
unsigned calculateLDSSpillAddress (MachineBasicBlock &MBB, MachineInstr &MI, RegScavenger *RS, unsigned TmpReg, unsigned Offset, unsigned Size) const
 
void materializeImmediate (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, int64_t Value) const
 
const TargetRegisterClassgetPreferredSelectRegClass (unsigned Size) const
 
unsigned insertNE (MachineBasicBlock *MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned SrcReg, int Value) const
 
unsigned insertEQ (MachineBasicBlock *MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned SrcReg, int Value) const
 
void storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
 
void loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
 
bool expandPostRAPseudo (MachineInstr &MI) const override
 
unsigned getMovOpcode (const TargetRegisterClass *DstRC) const
 
LLVM_READONLY int commuteOpcode (unsigned Opc) const
 
LLVM_READONLY int commuteOpcode (const MachineInstr &MI) const
 
bool findCommutedOpIndices (MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
 
bool findCommutedOpIndices (MCInstrDesc Desc, unsigned &SrcOpIdx0, unsigned &SrcOpIdx1) const
 
bool isBranchOffsetInRange (unsigned BranchOpc, int64_t BrOffset) const override
 
MachineBasicBlockgetBranchDestBlock (const MachineInstr &MI) const override
 
unsigned insertIndirectBranch (MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS=nullptr) const override
 
bool analyzeBranchImpl (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const
 
bool analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
 
unsigned removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
 
unsigned insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
 
bool reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
 
bool canInsertSelect (const MachineBasicBlock &MBB, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const override
 
void insertSelect (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
 
void insertVectorSelect (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const
 
unsigned getAddressSpaceForPseudoSourceKind (unsigned Kind) const override
 
bool areMemAccessesTriviallyDisjoint (MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA=nullptr) const override
 
bool isFoldableCopy (const MachineInstr &MI) const
 
bool FoldImmediate (MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const final
 
unsigned getMachineCSELookAheadLimit () const override
 
MachineInstrconvertToThreeAddress (MachineFunction::iterator &MBB, MachineInstr &MI, LiveVariables *LV) const override
 
bool isSchedulingBoundary (const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
 
bool isSALU (uint16_t Opcode) const
 
bool isVALU (uint16_t Opcode) const
 
bool isVMEM (uint16_t Opcode) const
 
bool isSOP1 (uint16_t Opcode) const
 
bool isSOP2 (uint16_t Opcode) const
 
bool isSOPC (uint16_t Opcode) const
 
bool isSOPK (uint16_t Opcode) const
 
bool isSOPP (uint16_t Opcode) const
 
bool isVOP1 (uint16_t Opcode) const
 
bool isVOP2 (uint16_t Opcode) const
 
bool isVOP3 (uint16_t Opcode) const
 
bool isSDWA (uint16_t Opcode) const
 
bool isVOPC (uint16_t Opcode) const
 
bool isMUBUF (uint16_t Opcode) const
 
bool isMTBUF (uint16_t Opcode) const
 
bool isSMRD (uint16_t Opcode) const
 
bool isBufferSMRD (const MachineInstr &MI) const
 
bool isDS (uint16_t Opcode) const
 
bool isMIMG (uint16_t Opcode) const
 
bool isGather4 (uint16_t Opcode) const
 
bool isFLAT (uint16_t Opcode) const
 
bool isEXP (uint16_t Opcode) const
 
bool isWQM (uint16_t Opcode) const
 
bool isDisableWQM (uint16_t Opcode) const
 
bool isVGPRSpill (uint16_t Opcode) const
 
bool isSGPRSpill (uint16_t Opcode) const
 
bool isDPP (uint16_t Opcode) const
 
bool isVOP3P (uint16_t Opcode) const
 
bool isVINTRP (uint16_t Opcode) const
 
bool sopkIsZext (uint16_t Opcode) const
 
bool isScalarStore (uint16_t Opcode) const
 
bool isFixedSize (uint16_t Opcode) const
 
bool hasFPClamp (uint16_t Opcode) const
 
uint64_t getClampMask (const MachineInstr &MI) const
 
bool isVGPRCopy (const MachineInstr &MI) const
 
bool hasUnwantedEffectsWhenEXECEmpty (const MachineInstr &MI) const
 Whether we must prevent this instruction from executing with EXEC = 0. More...
 
bool isInlineConstant (const APInt &Imm) const
 
bool isInlineConstant (const MachineOperand &MO, uint8_t OperandType) const
 
bool isInlineConstant (const MachineOperand &MO, const MCOperandInfo &OpInfo) const
 
bool isInlineConstant (const MachineInstr &MI, const MachineOperand &UseMO, const MachineOperand &DefMO) const
 returns true if UseMO is substituted with DefMO in MI it would be an inline immediate. More...
 
bool isInlineConstant (const MachineInstr &MI, unsigned OpIdx) const
 returns true if the operand OpIdx in MI is a valid inline immediate. More...
 
bool isInlineConstant (const MachineInstr &MI, unsigned OpIdx, const MachineOperand &MO) const
 
bool isInlineConstant (const MachineOperand &MO) const
 
bool isLiteralConstant (const MachineOperand &MO, const MCOperandInfo &OpInfo) const
 
bool isLiteralConstant (const MachineInstr &MI, int OpIdx) const
 
bool isLiteralConstantLike (const MachineOperand &MO, const MCOperandInfo &OpInfo) const
 
bool isImmOperandLegal (const MachineInstr &MI, unsigned OpNo, const MachineOperand &MO) const
 
bool hasVALU32BitEncoding (unsigned Opcode) const
 Return true if this 64-bit VALU instruction has a 32-bit encoding. More...
 
bool usesConstantBus (const MachineRegisterInfo &MRI, const MachineOperand &MO, const MCOperandInfo &OpInfo) const
 Returns true if this operand uses the constant bus. More...
 
bool hasModifiers (unsigned Opcode) const
 Return true if this instruction has any modifiers. More...
 
bool hasModifiersSet (const MachineInstr &MI, unsigned OpName) const
 
bool hasAnyModifiersSet (const MachineInstr &MI) const
 
bool canShrink (const MachineInstr &MI, const MachineRegisterInfo &MRI) const
 
MachineInstrbuildShrunkInst (MachineInstr &MI, unsigned NewOpcode) const
 
bool verifyInstruction (const MachineInstr &MI, StringRef &ErrInfo) const override
 
unsigned getVALUOp (const MachineInstr &MI) const
 
const TargetRegisterClassgetOpRegClass (const MachineInstr &MI, unsigned OpNo) const
 Return the correct register class for OpNo. More...
 
unsigned getOpSize (uint16_t Opcode, unsigned OpNo) const
 Return the size in bytes of the operand OpNo on the given. More...
 
unsigned getOpSize (const MachineInstr &MI, unsigned OpNo) const
 This form should usually be preferred since it handles operands with unknown register classes. More...
 
bool canReadVGPR (const MachineInstr &MI, unsigned OpNo) const
 
void legalizeOpWithMove (MachineInstr &MI, unsigned OpIdx) const
 Legalize the OpIndex operand of this instruction by inserting a MOV. More...
 
bool isOperandLegal (const MachineInstr &MI, unsigned OpIdx, const MachineOperand *MO=nullptr) const
 Check if MO is a legal operand if it was the OpIdx Operand for MI. More...
 
bool isLegalVSrcOperand (const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const
 Check if MO would be a valid operand for the given operand definition OpInfo. More...
 
bool isLegalRegOperand (const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const
 Check if MO (a register operand) is a legal register for the given operand description. More...
 
void legalizeOperandsVOP2 (MachineRegisterInfo &MRI, MachineInstr &MI) const
 Legalize operands in MI by either commuting it or inserting a copy of src1. More...
 
void legalizeOperandsVOP3 (MachineRegisterInfo &MRI, MachineInstr &MI) const
 Fix operands in MI to satisfy constant bus requirements. More...
 
unsigned readlaneVGPRToSGPR (unsigned SrcReg, MachineInstr &UseMI, MachineRegisterInfo &MRI) const
 Copy a value from a VGPR (SrcReg) to SGPR. More...
 
void legalizeOperandsSMRD (MachineRegisterInfo &MRI, MachineInstr &MI) const
 
void legalizeGenericOperand (MachineBasicBlock &InsertMBB, MachineBasicBlock::iterator I, const TargetRegisterClass *DstRC, MachineOperand &Op, MachineRegisterInfo &MRI, const DebugLoc &DL) const
 
void legalizeOperands (MachineInstr &MI) const
 Legalize all operands in this instruction. More...
 
void moveToVALU (MachineInstr &MI) const
 Replace this instruction's opcode with the equivalent VALU opcode. More...
 
void insertWaitStates (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, int Count) const
 
void insertNoop (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
 
void insertReturn (MachineBasicBlock &MBB) const
 
unsigned getNumWaitStates (const MachineInstr &MI) const
 Return the number of wait states that result from executing this instruction. More...
 
LLVM_READONLY MachineOperandgetNamedOperand (MachineInstr &MI, unsigned OperandName) const
 Returns the operand named Op. More...
 
LLVM_READONLY const MachineOperandgetNamedOperand (const MachineInstr &MI, unsigned OpName) const
 
int64_t getNamedImmOperand (const MachineInstr &MI, unsigned OpName) const
 Get required immediate operand. More...
 
uint64_t getDefaultRsrcDataFormat () const
 
uint64_t getScratchRsrcWords23 () const
 
bool isLowLatencyInstruction (const MachineInstr &MI) const
 
bool isHighLatencyInstruction (const MachineInstr &MI) const
 
const MCInstrDescgetMCOpcodeFromPseudo (unsigned Opcode) const
 Return the descriptor of the target-specific machine instruction that corresponds to the specified pseudo or native opcode. More...
 
unsigned isStackAccess (const MachineInstr &MI, int &FrameIndex) const
 
unsigned isSGPRStackAccess (const MachineInstr &MI, int &FrameIndex) const
 
unsigned isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const override
 
unsigned isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const override
 
unsigned getInstBundleSize (const MachineInstr &MI) const
 
unsigned getInstSizeInBytes (const MachineInstr &MI) const override
 
bool mayAccessFlatAddressSpace (const MachineInstr &MI) const
 
bool isNonUniformBranchInstr (MachineInstr &Instr) const
 
void convertNonUniformIfRegion (MachineBasicBlock *IfEntry, MachineBasicBlock *IfEnd) const
 
void convertNonUniformLoopRegion (MachineBasicBlock *LoopEntry, MachineBasicBlock *LoopEnd) const
 
std::pair< unsigned, unsigneddecomposeMachineOperandsTargetFlags (unsigned TF) const override
 
ArrayRef< std::pair< int, const char * > > getSerializableTargetIndices () const override
 
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags () const override
 
ScheduleHazardRecognizerCreateTargetPostRAHazardRecognizer (const InstrItineraryData *II, const ScheduleDAG *DAG) const override
 This is used by the post-RA scheduler (SchedulePostRAList.cpp). More...
 
ScheduleHazardRecognizerCreateTargetPostRAHazardRecognizer (const MachineFunction &MF) const override
 This is the hazard recognizer used at -O0 by the PostRAHazardRecognizer pass. More...
 
bool isBasicBlockPrologue (const MachineInstr &MI) const override
 
MachineInstrBuilder getAddNoCarry (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg) const
 Return a partially built integer add instruction without carry. More...
 
const MCInstrDescgetKillTerminatorFromPseudo (unsigned Opcode) const
 
int pseudoToMCOpcode (int Opcode) const
 Return a target-specific opcode if Opcode is a pseudo instruction. More...
 

Static Public Member Functions

static bool isSALU (const MachineInstr &MI)
 
static bool isVALU (const MachineInstr &MI)
 
static bool isVMEM (const MachineInstr &MI)
 
static bool isSOP1 (const MachineInstr &MI)
 
static bool isSOP2 (const MachineInstr &MI)
 
static bool isSOPC (const MachineInstr &MI)
 
static bool isSOPK (const MachineInstr &MI)
 
static bool isSOPP (const MachineInstr &MI)
 
static bool isVOP1 (const MachineInstr &MI)
 
static bool isVOP2 (const MachineInstr &MI)
 
static bool isVOP3 (const MachineInstr &MI)
 
static bool isSDWA (const MachineInstr &MI)
 
static bool isVOPC (const MachineInstr &MI)
 
static bool isMUBUF (const MachineInstr &MI)
 
static bool isMTBUF (const MachineInstr &MI)
 
static bool isSMRD (const MachineInstr &MI)
 
static bool isDS (const MachineInstr &MI)
 
static bool isMIMG (const MachineInstr &MI)
 
static bool isGather4 (const MachineInstr &MI)
 
static bool isFLAT (const MachineInstr &MI)
 
static bool isSegmentSpecificFLAT (const MachineInstr &MI)
 
static bool isEXP (const MachineInstr &MI)
 
static bool isWQM (const MachineInstr &MI)
 
static bool isDisableWQM (const MachineInstr &MI)
 
static bool isVGPRSpill (const MachineInstr &MI)
 
static bool isSGPRSpill (const MachineInstr &MI)
 
static bool isDPP (const MachineInstr &MI)
 
static bool isVOP3P (const MachineInstr &MI)
 
static bool isVINTRP (const MachineInstr &MI)
 
static bool isScalarUnit (const MachineInstr &MI)
 
static bool usesVM_CNT (const MachineInstr &MI)
 
static bool usesLGKM_CNT (const MachineInstr &MI)
 
static bool sopkIsZext (const MachineInstr &MI)
 
static bool isScalarStore (const MachineInstr &MI)
 
static bool isFixedSize (const MachineInstr &MI)
 
static bool hasFPClamp (const MachineInstr &MI)
 
static bool hasIntClamp (const MachineInstr &MI)
 
static bool isKillTerminator (unsigned Opcode)
 
static bool isLegalMUBUFImmOffset (unsigned Imm)
 

Protected Member Functions

bool swapSourceModifiers (MachineInstr &MI, MachineOperand &Src0, unsigned Src0OpName, MachineOperand &Src1, unsigned Src1OpName) const
 
MachineInstrcommuteInstructionImpl (MachineInstr &MI, bool NewMI, unsigned OpIdx0, unsigned OpIdx1) const override
 

Detailed Description

Definition at line 45 of file SIInstrInfo.h.

Member Enumeration Documentation

◆ TargetOperandFlags

Enumerator
MO_MASK 
MO_NONE 
MO_GOTPCREL 
MO_GOTPCREL32 
MO_GOTPCREL32_LO 
MO_GOTPCREL32_HI 
MO_REL32 
MO_REL32_LO 
MO_REL32_HI 

Definition at line 134 of file SIInstrInfo.h.

Constructor & Destructor Documentation

◆ SIInstrInfo()

SIInstrInfo::SIInstrInfo ( const GCNSubtarget ST)
explicit

Definition at line 87 of file SIInstrInfo.cpp.

Member Function Documentation

◆ analyzeBranch()

bool SIInstrInfo::analyzeBranch ( MachineBasicBlock MBB,
MachineBasicBlock *&  TBB,
MachineBasicBlock *&  FBB,
SmallVectorImpl< MachineOperand > &  Cond,
bool  AllowModify = false 
) const
override

◆ analyzeBranchImpl()

bool SIInstrInfo::analyzeBranchImpl ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
MachineBasicBlock *&  TBB,
MachineBasicBlock *&  FBB,
SmallVectorImpl< MachineOperand > &  Cond,
bool  AllowModify 
) const

◆ areLoadsFromSameBasePtr()

bool SIInstrInfo::areLoadsFromSameBasePtr ( SDNode Load1,
SDNode Load2,
int64_t &  Offset1,
int64_t &  Offset2 
) const
override

◆ areMemAccessesTriviallyDisjoint()

bool SIInstrInfo::areMemAccessesTriviallyDisjoint ( MachineInstr MIa,
MachineInstr MIb,
AliasAnalysis AA = nullptr 
) const
override

◆ buildExtractSubReg()

unsigned SIInstrInfo::buildExtractSubReg ( MachineBasicBlock::iterator  MI,
MachineRegisterInfo MRI,
MachineOperand SuperReg,
const TargetRegisterClass SuperRC,
unsigned  SubIdx,
const TargetRegisterClass SubRC 
) const

◆ buildExtractSubRegOrImm()

MachineOperand SIInstrInfo::buildExtractSubRegOrImm ( MachineBasicBlock::iterator  MI,
MachineRegisterInfo MRI,
MachineOperand SuperReg,
const TargetRegisterClass SuperRC,
unsigned  SubIdx,
const TargetRegisterClass SubRC 
) const

◆ buildShrunkInst()

MachineInstr * SIInstrInfo::buildShrunkInst ( MachineInstr MI,
unsigned  NewOpcode 
) const

◆ calculateLDSSpillAddress()

unsigned SIInstrInfo::calculateLDSSpillAddress ( MachineBasicBlock MBB,
MachineInstr MI,
RegScavenger RS,
unsigned  TmpReg,
unsigned  FrameOffset,
unsigned  Size 
) const

◆ canInsertSelect()

bool SIInstrInfo::canInsertSelect ( const MachineBasicBlock MBB,
ArrayRef< MachineOperand Cond,
unsigned  TrueReg,
unsigned  FalseReg,
int &  CondCycles,
int &  TrueCycles,
int &  FalseCycles 
) const
override

◆ canReadVGPR()

bool SIInstrInfo::canReadVGPR ( const MachineInstr MI,
unsigned  OpNo 
) const
Returns
true if it is legal for the operand at index OpNo to read a VGPR.

Definition at line 3199 of file SIInstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), and getOpRegClass().

Referenced by getOpSize(), and moveToVALU().

◆ canShrink()

bool SIInstrInfo::canShrink ( const MachineInstr MI,
const MachineRegisterInfo MRI 
) const

◆ commuteInstructionImpl()

MachineInstr * SIInstrInfo::commuteInstructionImpl ( MachineInstr MI,
bool  NewMI,
unsigned  OpIdx0,
unsigned  OpIdx1 
) const
overrideprotected

◆ commuteOpcode() [1/2]

int SIInstrInfo::commuteOpcode ( unsigned  Opc) const

◆ commuteOpcode() [2/2]

LLVM_READONLY int llvm::SIInstrInfo::commuteOpcode ( const MachineInstr MI) const
inline

◆ convertNonUniformIfRegion()

void SIInstrInfo::convertNonUniformIfRegion ( MachineBasicBlock IfEntry,
MachineBasicBlock IfEnd 
) const

◆ convertNonUniformLoopRegion()

void SIInstrInfo::convertNonUniformLoopRegion ( MachineBasicBlock LoopEntry,
MachineBasicBlock LoopEnd 
) const

◆ convertToThreeAddress()

MachineInstr * SIInstrInfo::convertToThreeAddress ( MachineFunction::iterator MBB,
MachineInstr MI,
LiveVariables LV 
) const
override

◆ copyPhysReg()

void SIInstrInfo::copyPhysReg ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
const DebugLoc DL,
unsigned  DestReg,
unsigned  SrcReg,
bool  KillSrc 
) const
override

◆ CreateTargetPostRAHazardRecognizer() [1/2]

ScheduleHazardRecognizer * SIInstrInfo::CreateTargetPostRAHazardRecognizer ( const InstrItineraryData II,
const ScheduleDAG DAG 
) const
override

This is used by the post-RA scheduler (SchedulePostRAList.cpp).

The post-RA version of misched uses CreateTargetMIHazardRecognizer.

Definition at line 5171 of file SIInstrInfo.cpp.

References llvm::ScheduleDAG::MF.

Referenced by getMCOpcodeFromPseudo().

◆ CreateTargetPostRAHazardRecognizer() [2/2]

ScheduleHazardRecognizer * SIInstrInfo::CreateTargetPostRAHazardRecognizer ( const MachineFunction MF) const
override

This is the hazard recognizer used at -O0 by the PostRAHazardRecognizer pass.

Definition at line 5179 of file SIInstrInfo.cpp.

◆ decomposeMachineOperandsTargetFlags()

std::pair< unsigned, unsigned > SIInstrInfo::decomposeMachineOperandsTargetFlags ( unsigned  TF) const
override

Definition at line 5184 of file SIInstrInfo.cpp.

References MO_MASK.

Referenced by getMCOpcodeFromPseudo().

◆ expandPostRAPseudo()

bool SIInstrInfo::expandPostRAPseudo ( MachineInstr MI) const
override

◆ findCommutedOpIndices() [1/2]

bool SIInstrInfo::findCommutedOpIndices ( MachineInstr MI,
unsigned SrcOpIdx1,
unsigned SrcOpIdx2 
) const
override

Definition at line 1422 of file SIInstrInfo.cpp.

References llvm::MachineInstr::getDesc().

Referenced by commuteOpcode(), stripExtractLoElt(), and tryAddToFoldList().

◆ findCommutedOpIndices() [2/2]

bool SIInstrInfo::findCommutedOpIndices ( MCInstrDesc  Desc,
unsigned SrcOpIdx0,
unsigned SrcOpIdx1 
) const

◆ FoldImmediate()

bool SIInstrInfo::FoldImmediate ( MachineInstr UseMI,
MachineInstr DefMI,
unsigned  Reg,
MachineRegisterInfo MRI 
) const
final

◆ getAddNoCarry()

MachineInstrBuilder SIInstrInfo::getAddNoCarry ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
const DebugLoc DL,
unsigned  DestReg 
) const

Return a partially built integer add instruction without carry.

Caller must add source operands. For pre-GFX9 it will generate unused carry destination operand. TODO: After GFX9 it should return a no-carry operation.

Definition at line 5207 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::RegState::Dead, llvm::RegState::Define, llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), and llvm::MachineRegisterInfo::setRegAllocationHint().

Referenced by calculateLDSSpillAddress(), and getMCOpcodeFromPseudo().

◆ getAddressSpaceForPseudoSourceKind()

unsigned SIInstrInfo::getAddressSpaceForPseudoSourceKind ( unsigned  Kind) const
override

◆ getBranchDestBlock()

MachineBasicBlock * SIInstrInfo::getBranchDestBlock ( const MachineInstr MI) const
override

◆ getClampMask()

uint64_t llvm::SIInstrInfo::getClampMask ( const MachineInstr MI) const
inline

◆ getDefaultRsrcDataFormat()

uint64_t SIInstrInfo::getDefaultRsrcDataFormat ( ) const

◆ getInstBundleSize()

unsigned SIInstrInfo::getInstBundleSize ( const MachineInstr MI) const

◆ getInstSizeInBytes()

unsigned SIInstrInfo::getInstSizeInBytes ( const MachineInstr MI) const
override

◆ getKillTerminatorFromPseudo()

const MCInstrDesc & SIInstrInfo::getKillTerminatorFromPseudo ( unsigned  Opcode) const

Definition at line 5232 of file SIInstrInfo.cpp.

References llvm_unreachable.

Referenced by getMCOpcodeFromPseudo(), and llvm::SITargetLowering::splitKillBlock().

◆ getMachineCSELookAheadLimit()

unsigned llvm::SIInstrInfo::getMachineCSELookAheadLimit ( ) const
inlineoverride

Definition at line 295 of file SIInstrInfo.h.

References convertToThreeAddress(), and isSchedulingBoundary().

◆ getMCOpcodeFromPseudo()

const MCInstrDesc& llvm::SIInstrInfo::getMCOpcodeFromPseudo ( unsigned  Opcode) const
inline

◆ getMemOpBaseRegImmOfs()

bool SIInstrInfo::getMemOpBaseRegImmOfs ( MachineInstr LdSt,
unsigned BaseReg,
int64_t &  Offset,
const TargetRegisterInfo TRI 
) const
final

◆ getMovOpcode()

unsigned SIInstrInfo::getMovOpcode ( const TargetRegisterClass DstRC) const

Definition at line 809 of file SIInstrInfo.cpp.

References llvm::SIRegisterInfo::isSGPRClass().

Referenced by getRegisterInfo().

◆ getNamedImmOperand()

int64_t llvm::SIInstrInfo::getNamedImmOperand ( const MachineInstr MI,
unsigned  OpName 
) const
inline

◆ getNamedOperand() [1/2]

MachineOperand * SIInstrInfo::getNamedOperand ( MachineInstr MI,
unsigned  OperandName 
) const

◆ getNamedOperand() [2/2]

LLVM_READONLY const MachineOperand* llvm::SIInstrInfo::getNamedOperand ( const MachineInstr MI,
unsigned  OpName 
) const
inline

Definition at line 817 of file SIInstrInfo.h.

References getNamedOperand().

◆ getNumWaitStates()

unsigned SIInstrInfo::getNumWaitStates ( const MachineInstr MI) const

Return the number of wait states that result from executing this instruction.

Definition at line 1161 of file SIInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), and llvm::MachineInstr::getOperand().

Referenced by llvm::GCNHazardRecognizer::AdvanceCycle(), and getOpSize().

◆ getOpRegClass()

const TargetRegisterClass * SIInstrInfo::getOpRegClass ( const MachineInstr MI,
unsigned  OpNo 
) const

Return the correct register class for OpNo.

For target-specific instructions, this will return the register class that has been defined in tablegen. For generic instructions, like REG_SEQUENCE it will return the register class of its machine operand. to infer the correct register class base on the other operands.

Definition at line 3182 of file SIInstrInfo.cpp.

References llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::MachineInstr::isVariadic(), llvm::TargetRegisterInfo::isVirtualRegister(), MRI, llvm::MCInstrDesc::OpInfo, Reg, and llvm::MCOperandInfo::RegClass.

Referenced by canReadVGPR(), getMemOpBaseRegImmOfs(), getOpSize(), hoistAndMergeSGPRInits(), isLiteralConstant(), legalizeOperands(), and moveToVALU().

◆ getOpSize() [1/2]

unsigned llvm::SIInstrInfo::getOpSize ( uint16_t  Opcode,
unsigned  OpNo 
) const
inline

Return the size in bytes of the operand OpNo on the given.

Definition at line 718 of file SIInstrInfo.h.

References assert(), llvm::MCOI::OPERAND_IMMEDIATE, llvm::MCOperandInfo::OperandType, and llvm::MCOperandInfo::RegClass.

Referenced by isInlineConstant().

◆ getOpSize() [2/2]

unsigned llvm::SIInstrInfo::getOpSize ( const MachineInstr MI,
unsigned  OpNo 
) const
inline

◆ getPreferredSelectRegClass()

const TargetRegisterClass * SIInstrInfo::getPreferredSelectRegClass ( unsigned  Size) const

Definition at line 675 of file SIInstrInfo.cpp.

Referenced by createBBSelectReg(), and getRegisterInfo().

◆ getRegisterInfo()

const SIRegisterInfo& llvm::SIInstrInfo::getRegisterInfo ( ) const
inline

◆ getScratchRsrcWords23()

uint64_t SIInstrInfo::getScratchRsrcWords23 ( ) const

◆ getSerializableDirectMachineOperandTargetFlags()

ArrayRef< std::pair< unsigned, const char * > > SIInstrInfo::getSerializableDirectMachineOperandTargetFlags ( ) const
override

◆ getSerializableTargetIndices()

ArrayRef< std::pair< int, const char * > > SIInstrInfo::getSerializableTargetIndices ( ) const
override

◆ getVALUOp()

unsigned SIInstrInfo::getVALUOp ( const MachineInstr MI) const

◆ hasAnyModifiersSet()

bool SIInstrInfo::hasAnyModifiersSet ( const MachineInstr MI) const

Definition at line 2550 of file SIInstrInfo.cpp.

References hasModifiersSet().

Referenced by FoldImmediate(), and isLiteralConstant().

◆ hasFPClamp() [1/2]

static bool llvm::SIInstrInfo::hasFPClamp ( const MachineInstr MI)
inlinestatic

◆ hasFPClamp() [2/2]

bool llvm::SIInstrInfo::hasFPClamp ( uint16_t  Opcode) const
inline

Definition at line 581 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FPClamp.

◆ hasIntClamp()

static bool llvm::SIInstrInfo::hasIntClamp ( const MachineInstr MI)
inlinestatic

◆ hasModifiers()

bool SIInstrInfo::hasModifiers ( unsigned  Opcode) const

Return true if this instruction has any modifiers.

e.g. src[012]_mod, omod, clamp.

Definition at line 2536 of file SIInstrInfo.cpp.

References llvm::AMDGPU::getNamedOperandIdx().

Referenced by isLiteralConstant().

◆ hasModifiersSet()

bool SIInstrInfo::hasModifiersSet ( const MachineInstr MI,
unsigned  OpName 
) const

◆ hasUnwantedEffectsWhenEXECEmpty()

bool SIInstrInfo::hasUnwantedEffectsWhenEXECEmpty ( const MachineInstr MI) const

Whether we must prevent this instruction from executing with EXEC = 0.

Definition at line 2368 of file SIInstrInfo.cpp.

References llvm::SIInstrFlags::EXP, llvm::MachineInstr::getOpcode(), llvm::MachineInstr::isInlineAsm(), isSMRD(), and llvm::MachineInstr::mayStore().

Referenced by isVGPRCopy().

◆ hasVALU32BitEncoding()

bool SIInstrInfo::hasVALU32BitEncoding ( unsigned  Opcode) const

Return true if this 64-bit VALU instruction has a 32-bit encoding.

This function will return false if you pass it a 32-bit instruction.

Definition at line 2528 of file SIInstrInfo.cpp.

References llvm::AMDGPU::getVOPe32(), and pseudoToMCOpcode().

Referenced by isLiteralConstant().

◆ insertBranch()

unsigned SIInstrInfo::insertBranch ( MachineBasicBlock MBB,
MachineBasicBlock TBB,
MachineBasicBlock FBB,
ArrayRef< MachineOperand Cond,
const DebugLoc DL,
int *  BytesAdded = nullptr 
) const
override

◆ insertEQ()

unsigned SIInstrInfo::insertEQ ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
const DebugLoc DL,
unsigned  SrcReg,
int  Value 
) const

◆ insertIndirectBranch()

unsigned SIInstrInfo::insertIndirectBranch ( MachineBasicBlock MBB,
MachineBasicBlock NewDestBB,
const DebugLoc DL,
int64_t  BrOffset,
RegScavenger RS = nullptr 
) const
override

◆ insertNE()

unsigned SIInstrInfo::insertNE ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
const DebugLoc DL,
unsigned  SrcReg,
int  Value 
) const

◆ insertNoop()

void SIInstrInfo::insertNoop ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI 
) const
override

Definition at line 1142 of file SIInstrInfo.cpp.

References insertWaitStates().

Referenced by getOpSize().

◆ insertReturn()

void SIInstrInfo::insertReturn ( MachineBasicBlock MBB) const

◆ insertSelect()

void SIInstrInfo::insertSelect ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
const DebugLoc DL,
unsigned  DstReg,
ArrayRef< MachineOperand Cond,
unsigned  TrueReg,
unsigned  FalseReg 
) const
override

◆ insertVectorSelect()

void SIInstrInfo::insertVectorSelect ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
const DebugLoc DL,
unsigned  DstReg,
ArrayRef< MachineOperand Cond,
unsigned  TrueReg,
unsigned  FalseReg 
) const

◆ insertWaitStates()

void SIInstrInfo::insertWaitStates ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
int  Count 
) const

◆ isBasicBlockPrologue()

bool SIInstrInfo::isBasicBlockPrologue ( const MachineInstr MI) const
override

◆ isBranchOffsetInRange()

bool SIInstrInfo::isBranchOffsetInRange ( unsigned  BranchOpc,
int64_t  BrOffset 
) const
override

Definition at line 1444 of file SIInstrInfo.cpp.

References assert(), BranchOffsetBits, and llvm::isIntN().

Referenced by commuteOpcode().

◆ isBufferSMRD()

bool SIInstrInfo::isBufferSMRD ( const MachineInstr MI) const

◆ isDisableWQM() [1/2]

static bool llvm::SIInstrInfo::isDisableWQM ( const MachineInstr MI)
inlinestatic

◆ isDisableWQM() [2/2]

bool llvm::SIInstrInfo::isDisableWQM ( uint16_t  Opcode) const
inline

Definition at line 495 of file SIInstrInfo.h.

References llvm::SIInstrFlags::DisableWQM.

◆ isDPP() [1/2]

static bool llvm::SIInstrInfo::isDPP ( const MachineInstr MI)
inlinestatic

◆ isDPP() [2/2]

bool llvm::SIInstrInfo::isDPP ( uint16_t  Opcode) const
inline

Definition at line 519 of file SIInstrInfo.h.

References llvm::SIInstrFlags::DPP.

◆ isDS() [1/2]

static bool llvm::SIInstrInfo::isDS ( const MachineInstr MI)
inlinestatic

◆ isDS() [2/2]

bool llvm::SIInstrInfo::isDS ( uint16_t  Opcode) const
inline

Definition at line 439 of file SIInstrInfo.h.

References llvm::SIInstrFlags::DS.

◆ isEXP() [1/2]

static bool llvm::SIInstrInfo::isEXP ( const MachineInstr MI)
inlinestatic

◆ isEXP() [2/2]

bool llvm::SIInstrInfo::isEXP ( uint16_t  Opcode) const
inline

Definition at line 479 of file SIInstrInfo.h.

References llvm::SIInstrFlags::EXP.

◆ isFixedSize() [1/2]

static bool llvm::SIInstrInfo::isFixedSize ( const MachineInstr MI)
inlinestatic

◆ isFixedSize() [2/2]

bool llvm::SIInstrInfo::isFixedSize ( uint16_t  Opcode) const
inline

Definition at line 573 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FIXED_SIZE.

◆ isFLAT() [1/2]

static bool llvm::SIInstrInfo::isFLAT ( const MachineInstr MI)
inlinestatic

◆ isFLAT() [2/2]

bool llvm::SIInstrInfo::isFLAT ( uint16_t  Opcode) const
inline

Definition at line 471 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FLAT.

◆ isFoldableCopy()

bool SIInstrInfo::isFoldableCopy ( const MachineInstr MI) const

◆ isGather4() [1/2]

static bool llvm::SIInstrInfo::isGather4 ( const MachineInstr MI)
inlinestatic

◆ isGather4() [2/2]

bool llvm::SIInstrInfo::isGather4 ( uint16_t  Opcode) const
inline

Definition at line 455 of file SIInstrInfo.h.

References llvm::SIInstrFlags::Gather4.

◆ isHighLatencyInstruction()

bool SIInstrInfo::isHighLatencyInstruction ( const MachineInstr MI) const

◆ isImmOperandLegal()

bool SIInstrInfo::isImmOperandLegal ( const MachineInstr MI,
unsigned  OpNo,
const MachineOperand MO 
) const

◆ isInlineConstant() [1/7]

bool SIInstrInfo::isInlineConstant ( const APInt Imm) const

◆ isInlineConstant() [2/7]

bool SIInstrInfo::isInlineConstant ( const MachineOperand MO,
uint8_t  OperandType 
) const

◆ isInlineConstant() [3/7]

bool llvm::SIInstrInfo::isInlineConstant ( const MachineOperand MO,
const MCOperandInfo OpInfo 
) const
inline

Definition at line 612 of file SIInstrInfo.h.

References isInlineConstant(), and llvm::MCOperandInfo::OperandType.

◆ isInlineConstant() [4/7]

bool llvm::SIInstrInfo::isInlineConstant ( const MachineInstr MI,
const MachineOperand UseMO,
const MachineOperand DefMO 
) const
inline

returns true if UseMO is substituted with DefMO in MI it would be an inline immediate.

Definition at line 619 of file SIInstrInfo.h.

References assert(), llvm::MachineInstr::getDesc(), llvm::MachineInstr::getOperandNo(), llvm::MachineOperand::getParent(), isInlineConstant(), MI, llvm::MCInstrDesc::NumOperands, and llvm::MCInstrDesc::OpInfo.

◆ isInlineConstant() [5/7]

bool llvm::SIInstrInfo::isInlineConstant ( const MachineInstr MI,
unsigned  OpIdx 
) const
inline

returns true if the operand OpIdx in MI is a valid inline immediate.

Definition at line 633 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::MachineInstr::getOperand(), isInlineConstant(), llvm::MCOperandInfo::OperandType, and llvm::MCInstrDesc::OpInfo.

◆ isInlineConstant() [6/7]

bool llvm::SIInstrInfo::isInlineConstant ( const MachineInstr MI,
unsigned  OpIdx,
const MachineOperand MO 
) const
inline

◆ isInlineConstant() [7/7]

bool llvm::SIInstrInfo::isInlineConstant ( const MachineOperand MO) const
inline

◆ isKillTerminator()

bool SIInstrInfo::isKillTerminator ( unsigned  Opcode)
static

Definition at line 5222 of file SIInstrInfo.cpp.

Referenced by getMCOpcodeFromPseudo(), and isSimpleIf().

◆ isLegalMUBUFImmOffset()

static bool llvm::SIInstrInfo::isLegalMUBUFImmOffset ( unsigned  Imm)
inlinestatic

◆ isLegalRegOperand()

bool SIInstrInfo::isLegalRegOperand ( const MachineRegisterInfo MRI,
const MCOperandInfo OpInfo,
const MachineOperand MO 
) const

◆ isLegalVSrcOperand()

bool SIInstrInfo::isLegalVSrcOperand ( const MachineRegisterInfo MRI,
const MCOperandInfo OpInfo,
const MachineOperand MO 
) const

Check if MO would be a valid operand for the given operand definition OpInfo.

Note this does not attempt to validate constant bus restrictions (e.g. literal constant usage).

Definition at line 3325 of file SIInstrInfo.cpp.

References assert(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), isLegalRegOperand(), llvm::MachineOperand::isReg(), and llvm::MachineOperand::isTargetIndex().

Referenced by getOpSize().

◆ isLiteralConstant() [1/2]

bool llvm::SIInstrInfo::isLiteralConstant ( const MachineOperand MO,
const MCOperandInfo OpInfo 
) const
inline

◆ isLiteralConstant() [2/2]

bool llvm::SIInstrInfo::isLiteralConstant ( const MachineInstr MI,
int  OpIdx 
) const
inline

◆ isLiteralConstantLike()

bool SIInstrInfo::isLiteralConstantLike ( const MachineOperand MO,
const MCOperandInfo OpInfo 
) const

◆ isLoadFromStackSlot()

unsigned SIInstrInfo::isLoadFromStackSlot ( const MachineInstr MI,
int &  FrameIndex 
) const
override

◆ isLowLatencyInstruction()

bool SIInstrInfo::isLowLatencyInstruction ( const MachineInstr MI) const

◆ isMIMG() [1/2]

static bool llvm::SIInstrInfo::isMIMG ( const MachineInstr MI)
inlinestatic

◆ isMIMG() [2/2]

bool llvm::SIInstrInfo::isMIMG ( uint16_t  Opcode) const
inline

Definition at line 447 of file SIInstrInfo.h.

References llvm::SIInstrFlags::MIMG.

◆ isMTBUF() [1/2]

static bool llvm::SIInstrInfo::isMTBUF ( const MachineInstr MI)
inlinestatic

◆ isMTBUF() [2/2]

bool llvm::SIInstrInfo::isMTBUF ( uint16_t  Opcode) const
inline

Definition at line 421 of file SIInstrInfo.h.

References llvm::SIInstrFlags::MTBUF.

◆ isMUBUF() [1/2]

static bool llvm::SIInstrInfo::isMUBUF ( const MachineInstr MI)
inlinestatic

◆ isMUBUF() [2/2]

bool llvm::SIInstrInfo::isMUBUF ( uint16_t  Opcode) const
inline

Definition at line 413 of file SIInstrInfo.h.

References llvm::SIInstrFlags::MUBUF.

◆ isNonUniformBranchInstr()

bool SIInstrInfo::isNonUniformBranchInstr ( MachineInstr Instr) const

Definition at line 5081 of file SIInstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

Referenced by getMCOpcodeFromPseudo().

◆ isOperandLegal()

bool SIInstrInfo::isOperandLegal ( const MachineInstr MI,
unsigned  OpIdx,
const MachineOperand MO = nullptr 
) const

◆ isReallyTriviallyReMaterializable()

bool SIInstrInfo::isReallyTriviallyReMaterializable ( const MachineInstr MI,
AliasAnalysis AA 
) const
override

Definition at line 135 of file SIInstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

Referenced by getRegisterInfo().

◆ isSALU() [1/2]

static bool llvm::SIInstrInfo::isSALU ( const MachineInstr MI)
inlinestatic

◆ isSALU() [2/2]

bool llvm::SIInstrInfo::isSALU ( uint16_t  Opcode) const
inline

Definition at line 309 of file SIInstrInfo.h.

References llvm::SIInstrFlags::SALU.

◆ isScalarStore() [1/2]

static bool llvm::SIInstrInfo::isScalarStore ( const MachineInstr MI)
inlinestatic
Returns
true if this is an s_store_dword* instruction. This is more specific than than isSMEM && mayStore.

Definition at line 561 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::SIInstrFlags::SCALAR_STORE, and llvm::MCInstrDesc::TSFlags.

◆ isScalarStore() [2/2]

bool llvm::SIInstrInfo::isScalarStore ( uint16_t  Opcode) const
inline

Definition at line 565 of file SIInstrInfo.h.

References llvm::SIInstrFlags::SCALAR_STORE.

◆ isScalarUnit()

static bool llvm::SIInstrInfo::isScalarUnit ( const MachineInstr MI)
inlinestatic

◆ isSchedulingBoundary()

bool SIInstrInfo::isSchedulingBoundary ( const MachineInstr MI,
const MachineBasicBlock MBB,
const MachineFunction MF 
) const
override

◆ isSDWA() [1/2]

static bool llvm::SIInstrInfo::isSDWA ( const MachineInstr MI)
inlinestatic

◆ isSDWA() [2/2]

bool llvm::SIInstrInfo::isSDWA ( uint16_t  Opcode) const
inline

Definition at line 397 of file SIInstrInfo.h.

References llvm::SIInstrFlags::SDWA.

◆ isSegmentSpecificFLAT()

static bool llvm::SIInstrInfo::isSegmentSpecificFLAT ( const MachineInstr MI)
inlinestatic

◆ isSGPRSpill() [1/2]

static bool llvm::SIInstrInfo::isSGPRSpill ( const MachineInstr MI)
inlinestatic

◆ isSGPRSpill() [2/2]

bool llvm::SIInstrInfo::isSGPRSpill ( uint16_t  Opcode) const
inline

Definition at line 511 of file SIInstrInfo.h.

References llvm::SIInstrFlags::SGPRSpill.

◆ isSGPRStackAccess()

unsigned SIInstrInfo::isSGPRStackAccess ( const MachineInstr MI,
int &  FrameIndex 
) const

◆ isSMRD() [1/2]

static bool llvm::SIInstrInfo::isSMRD ( const MachineInstr MI)
inlinestatic

◆ isSMRD() [2/2]

bool llvm::SIInstrInfo::isSMRD ( uint16_t  Opcode) const
inline

Definition at line 429 of file SIInstrInfo.h.

References isBufferSMRD(), and llvm::SIInstrFlags::SMRD.

◆ isSOP1() [1/2]

static bool llvm::SIInstrInfo::isSOP1 ( const MachineInstr MI)
inlinestatic

◆ isSOP1() [2/2]

bool llvm::SIInstrInfo::isSOP1 ( uint16_t  Opcode) const
inline

Definition at line 333 of file SIInstrInfo.h.

References llvm::SIInstrFlags::SOP1.

◆ isSOP2() [1/2]

static bool llvm::SIInstrInfo::isSOP2 ( const MachineInstr MI)
inlinestatic

◆ isSOP2() [2/2]

bool llvm::SIInstrInfo::isSOP2 ( uint16_t  Opcode) const
inline

Definition at line 341 of file SIInstrInfo.h.

References llvm::SIInstrFlags::SOP2.

◆ isSOPC() [1/2]

static bool llvm::SIInstrInfo::isSOPC ( const MachineInstr MI)
inlinestatic

◆ isSOPC() [2/2]

bool llvm::SIInstrInfo::isSOPC ( uint16_t  Opcode) const
inline

Definition at line 349 of file SIInstrInfo.h.

References llvm::SIInstrFlags::SOPC.

◆ isSOPK() [1/2]

static bool llvm::SIInstrInfo::isSOPK ( const MachineInstr MI)
inlinestatic

◆ isSOPK() [2/2]

bool llvm::SIInstrInfo::isSOPK ( uint16_t  Opcode) const
inline

Definition at line 357 of file SIInstrInfo.h.

References llvm::SIInstrFlags::SOPK.

◆ isSOPP() [1/2]

static bool llvm::SIInstrInfo::isSOPP ( const MachineInstr MI)
inlinestatic

◆ isSOPP() [2/2]

bool llvm::SIInstrInfo::isSOPP ( uint16_t  Opcode) const
inline

Definition at line 365 of file SIInstrInfo.h.

References llvm::SIInstrFlags::SOPP.

◆ isStackAccess()

unsigned SIInstrInfo::isStackAccess ( const MachineInstr MI,
int &  FrameIndex 
) const

◆ isStoreToStackSlot()

unsigned SIInstrInfo::isStoreToStackSlot ( const MachineInstr MI,
int &  FrameIndex 
) const
override

◆ isVALU() [1/2]

static bool llvm::SIInstrInfo::isVALU ( const MachineInstr MI)
inlinestatic

◆ isVALU() [2/2]

bool llvm::SIInstrInfo::isVALU ( uint16_t  Opcode) const
inline

Definition at line 317 of file SIInstrInfo.h.

References llvm::SIInstrFlags::VALU.

◆ isVGPRCopy()

bool llvm::SIInstrInfo::isVGPRCopy ( const MachineInstr MI) const
inline

◆ isVGPRSpill() [1/2]

static bool llvm::SIInstrInfo::isVGPRSpill ( const MachineInstr MI)
inlinestatic

◆ isVGPRSpill() [2/2]

bool llvm::SIInstrInfo::isVGPRSpill ( uint16_t  Opcode) const
inline

Definition at line 503 of file SIInstrInfo.h.

References llvm::SIInstrFlags::VGPRSpill.

◆ isVINTRP() [1/2]

static bool llvm::SIInstrInfo::isVINTRP ( const MachineInstr MI)
inlinestatic

◆ isVINTRP() [2/2]

bool llvm::SIInstrInfo::isVINTRP ( uint16_t  Opcode) const
inline

Definition at line 535 of file SIInstrInfo.h.

References llvm::SIInstrFlags::VINTRP.

◆ isVMEM() [1/2]

static bool llvm::SIInstrInfo::isVMEM ( const MachineInstr MI)
inlinestatic

◆ isVMEM() [2/2]

bool llvm::SIInstrInfo::isVMEM ( uint16_t  Opcode) const
inline

Definition at line 325 of file SIInstrInfo.h.

References isMIMG(), isMTBUF(), and isMUBUF().

◆ isVOP1() [1/2]

static bool llvm::SIInstrInfo::isVOP1 ( const MachineInstr MI)
inlinestatic

◆ isVOP1() [2/2]

bool llvm::SIInstrInfo::isVOP1 ( uint16_t  Opcode) const
inline

Definition at line 373 of file SIInstrInfo.h.

References llvm::SIInstrFlags::VOP1.

◆ isVOP2() [1/2]

static bool llvm::SIInstrInfo::isVOP2 ( const MachineInstr MI)
inlinestatic

◆ isVOP2() [2/2]

bool llvm::SIInstrInfo::isVOP2 ( uint16_t  Opcode) const
inline

Definition at line 381 of file SIInstrInfo.h.

References llvm::SIInstrFlags::VOP2.

◆ isVOP3() [1/2]

static bool llvm::SIInstrInfo::isVOP3 ( const MachineInstr MI)
inlinestatic

◆ isVOP3() [2/2]

bool llvm::SIInstrInfo::isVOP3 ( uint16_t  Opcode) const
inline

Definition at line 389 of file SIInstrInfo.h.

References llvm::SIInstrFlags::VOP3.

◆ isVOP3P() [1/2]

static bool llvm::SIInstrInfo::isVOP3P ( const MachineInstr MI)
inlinestatic

◆ isVOP3P() [2/2]

bool llvm::SIInstrInfo::isVOP3P ( uint16_t  Opcode) const
inline

Definition at line 527 of file SIInstrInfo.h.

References llvm::SIInstrFlags::VOP3P.

◆ isVOPC() [1/2]

static bool llvm::SIInstrInfo::isVOPC ( const MachineInstr MI)
inlinestatic

◆ isVOPC() [2/2]

bool llvm::SIInstrInfo::isVOPC ( uint16_t  Opcode) const
inline

Definition at line 405 of file SIInstrInfo.h.

References llvm::SIInstrFlags::VOPC.

◆ isWQM() [1/2]

static bool llvm::SIInstrInfo::isWQM ( const MachineInstr MI)
inlinestatic

◆ isWQM() [2/2]

bool llvm::SIInstrInfo::isWQM ( uint16_t  Opcode) const
inline

Definition at line 487 of file SIInstrInfo.h.

References llvm::SIInstrFlags::WQM.

◆ legalizeGenericOperand()

void SIInstrInfo::legalizeGenericOperand ( MachineBasicBlock InsertMBB,
MachineBasicBlock::iterator  I,
const TargetRegisterClass DstRC,
MachineOperand Op,
MachineRegisterInfo MRI,
const DebugLoc DL 
) const

◆ legalizeOperands()

void SIInstrInfo::legalizeOperands ( MachineInstr MI) const

Legalize all operands in this instruction.

This function may create new instruction and insert them before MI.

Definition at line 3615 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), buildExtractSubReg(), llvm::BuildMI(), llvm::MachineInstrBuilder::cloneMemRefs(), llvm::MachineRegisterInfo::createVirtualRegister(), E, llvm::AMDGPU::getAddr64Inst(), llvm::Function::getCallingConv(), llvm::MachineInstr::getDebugLoc(), getDefaultRsrcDataFormat(), llvm::MachineBasicBlock::getFirstTerminator(), llvm::MachineFunction::getFunction(), llvm::MachineOperand::getMBB(), getNamedImmOperand(), getNamedOperand(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getOpRegClass(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), I, isMIMG(), isMTBUF(), isMUBUF(), llvm::MachineOperand::isReg(), llvm::AMDGPU::isShader(), isSMRD(), llvm::TargetRegisterInfo::isVirtualRegister(), isVOP2(), isVOP3(), isVOPC(), legalizeGenericOperand(), legalizeOperandsSMRD(), legalizeOperandsVOP2(), legalizeOperandsVOP3(), MI, MRI, readlaneVGPRToSGPR(), llvm::MachineInstr::removeFromParent(), llvm::MachineOperand::setIsKill(), llvm::MachineOperand::setReg(), and llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS.

Referenced by getOpSize(), and moveToVALU().

◆ legalizeOperandsSMRD()

void SIInstrInfo::legalizeOperandsSMRD ( MachineRegisterInfo MRI,
MachineInstr MI 
) const

◆ legalizeOperandsVOP2()

void SIInstrInfo::legalizeOperandsVOP2 ( MachineRegisterInfo MRI,
MachineInstr MI 
) const

◆ legalizeOperandsVOP3()

void SIInstrInfo::legalizeOperandsVOP3 ( MachineRegisterInfo MRI,
MachineInstr MI 
) const

◆ legalizeOpWithMove()

void SIInstrInfo::legalizeOpWithMove ( MachineInstr MI,
unsigned  OpIdx 
) const

Legalize the OpIndex operand of this instruction by inserting a MOV.

For example: ADD_I32_e32 VGPR0, 15 to MOV VGPR1, 15 ADD_I32_e32 VGPR0, VGPR1

If the operand being legalized is a register, then a COPY will be used instead of MOV.

Definition at line 3211 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::BuildMI(), llvm::MachineOperand::ChangeToRegister(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MachineBasicBlock::findDebugLoc(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineFunction::getRegInfo(), I, llvm::MachineOperand::isReg(), MI, MRI, and Reg.

Referenced by getOpSize(), legalizeOperandsVOP2(), and legalizeOperandsVOP3().

◆ loadRegFromStackSlot()

void SIInstrInfo::loadRegFromStackSlot ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
unsigned  DestReg,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI 
) const
override

◆ materializeImmediate()

void SIInstrInfo::materializeImmediate ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
const DebugLoc DL,
unsigned  DestReg,
int64_t  Value 
) const

◆ mayAccessFlatAddressSpace()

bool SIInstrInfo::mayAccessFlatAddressSpace ( const MachineInstr MI) const

◆ moveToVALU()

void SIInstrInfo::moveToVALU ( MachineInstr MI) const

Replace this instruction's opcode with the equivalent VALU opcode.

This function will also move the users of MI to the VALU if necessary.

Definition at line 3913 of file SIInstrInfo.cpp.

References llvm::MCID::Add, llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstr::addImplicitDefUseOperands(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstr::addOperand(), llvm::MachineInstrBuilder::addReg(), assert(), buildExtractSubReg(), buildExtractSubRegOrImm(), llvm::BuildMI(), canReadVGPR(), llvm::MachineRegisterInfo::clearKillFlags(), llvm::MachineInstrBuilder::cloneMemRefs(), llvm::MachineOperand::CreateImm(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::RegState::Dead, llvm::tgtok::Def, llvm::RegState::Define, E, llvm::SetVector< T, Vector, Set >::empty(), llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), findImplicitSGPRRead(), llvm::MachineOperand::getCImm(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::MachineInstrBuilder::getInstr(), getNamedOperand(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getOpRegClass(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::MachineRegisterInfo::getUniqueVRegDef(), getVALUOp(), llvm::ConstantInt::getZExtValue(), I, llvm::SetVector< T, Vector, Set >::insert(), llvm::MachineOperand::isCImm(), llvm::MachineInstr::isCopy(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isImm(), isLegalMUBUFImmOffset(), llvm::MachineInstr::isMoveImmediate(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineOperand::isReg(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::RegState::Kill, legalizeGenericOperand(), legalizeOperands(), llvm_unreachable, llvm::make_range(), llvm::MachineInstr::memoperands_begin(), MI, MRI, llvm::MCInstrDesc::OpInfo, llvm::SetVector< T, Vector, Set >::pop_back_val(), llvm::SmallVectorTemplateBase< T, isPodLike >::push_back(), Reg, llvm::MCOperandInfo::RegClass, llvm::MachineInstr::RemoveOperand(), llvm::MachineRegisterInfo::replaceRegWith(), llvm::MachineInstr::setDesc(), llvm::MachineOperand::setReg(), Size, llvm::MachineRegisterInfo::use_begin(), llvm::MachineRegisterInfo::use_end(), UseMI, llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS, and llvm::SIInstrFlags::WQM.

Referenced by getOpSize(), and hoistAndMergeSGPRInits().

◆ pseudoToMCOpcode()

int SIInstrInfo::pseudoToMCOpcode ( int  Opcode) const

Return a target-specific opcode if Opcode is a pseudo instruction.

Return -1 if the target-specific opcode for the pseudo instruction does not exist. If Opcode is not a pseudo instruction, this is identity.

Definition at line 5280 of file SIInstrInfo.cpp.

References llvm::SIInstrFlags::D16Buf, llvm::AMDGPU::getMCOpcode(), GFX80, llvm::AMDGPUSubtarget::GFX9, GFX9, llvm::SIInstrFlags::renamedInGFX9, llvm::SIInstrFlags::SDWA, SDWA, SDWA9, and subtargetEncodingFamily().

Referenced by commuteOpcode(), getMCOpcodeFromPseudo(), getPermuteMask(), hasVALU32BitEncoding(), and isLegalMUBUFImmOffset().

◆ readlaneVGPRToSGPR()

unsigned SIInstrInfo::readlaneVGPRToSGPR ( unsigned  SrcReg,
MachineInstr UseMI,
MachineRegisterInfo MRI 
) const

Copy a value from a VGPR (SrcReg) to SGPR.

This function can only be used when it is know that the value in SrcReg is same across all threads in the wave.

Returns
The SGPR register that SrcReg was copied to.

Definition at line 3536 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getParent(), llvm::MachineRegisterInfo::getRegClass(), llvm::SmallVectorTemplateBase< T, isPodLike >::push_back(), and UseMI.

Referenced by getOpSize(), legalizeOperands(), and legalizeOperandsSMRD().

◆ removeBranch()

unsigned SIInstrInfo::removeBranch ( MachineBasicBlock MBB,
int *  BytesRemoved = nullptr 
) const
override

◆ reverseBranchCondition()

bool SIInstrInfo::reverseBranchCondition ( SmallVectorImpl< MachineOperand > &  Cond) const
override

Definition at line 1775 of file SIInstrInfo.cpp.

References llvm::SmallVectorBase::size().

Referenced by commuteOpcode().

◆ shouldClusterMemOps()

bool SIInstrInfo::shouldClusterMemOps ( MachineInstr FirstLdSt,
unsigned  BaseReg1,
MachineInstr SecondLdSt,
unsigned  BaseReg2,
unsigned  NumLoads 
) const
override

◆ shouldScheduleLoadsNear()

bool SIInstrInfo::shouldScheduleLoadsNear ( SDNode Load0,
SDNode Load1,
int64_t  Offset0,
int64_t  Offset1,
unsigned  NumLoads 
) const
override

Definition at line 466 of file SIInstrInfo.cpp.

References assert().

Referenced by getRegisterInfo().

◆ sopkIsZext() [1/2]

static bool llvm::SIInstrInfo::sopkIsZext ( const MachineInstr MI)
inlinestatic

◆ sopkIsZext() [2/2]

bool llvm::SIInstrInfo::sopkIsZext ( uint16_t  Opcode) const
inline

Definition at line 555 of file SIInstrInfo.h.

References llvm::SIInstrFlags::SOPK_ZEXT.

◆ storeRegToStackSlot()

void SIInstrInfo::storeRegToStackSlot ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
unsigned  SrcReg,
bool  isKill,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI 
) const
override

◆ swapSourceModifiers()

bool SIInstrInfo::swapSourceModifiers ( MachineInstr MI,
MachineOperand Src0,
unsigned  Src0OpName,
MachineOperand Src1,
unsigned  Src1OpName 
) const
protected

◆ usesConstantBus()

bool SIInstrInfo::usesConstantBus ( const MachineRegisterInfo MRI,
const MachineOperand MO,
const MCOperandInfo OpInfo 
) const

◆ usesLGKM_CNT()

static bool llvm::SIInstrInfo::usesLGKM_CNT ( const MachineInstr MI)
inlinestatic

◆ usesVM_CNT()

static bool llvm::SIInstrInfo::usesVM_CNT ( const MachineInstr MI)
inlinestatic

◆ verifyInstruction()

bool SIInstrInfo::verifyInstruction ( const MachineInstr MI,
StringRef ErrInfo 
) const
override

Definition at line 2749 of file SIInstrInfo.cpp.

References compareMachineOp(), llvm::TargetRegisterClass::contains(), DC, llvm::SIInstrFlags::DPP, llvm::AMDGPU::DPP::DPP_LAST, llvm::AMDGPU::DPP::DPP_UNUSED1, llvm::AMDGPU::DPP::DPP_UNUSED2, llvm::AMDGPU::DPP::DPP_UNUSED3, llvm::AMDGPU::DPP::DPP_UNUSED4_FIRST, llvm::AMDGPU::DPP::DPP_UNUSED4_LAST, llvm::AMDGPU::DPP::DPP_UNUSED5_FIRST, llvm::AMDGPU::DPP::DPP_UNUSED5_LAST, llvm::AMDGPU::DPP::DPP_UNUSED6_FIRST, llvm::AMDGPU::DPP::DPP_UNUSED6_LAST, llvm::AMDGPU::DPP::DPP_UNUSED7_FIRST, llvm::AMDGPU::DPP::DPP_UNUSED7_LAST, E, findImplicitSGPRRead(), llvm::MachineInstr::findTiedOperandIdx(), llvm::AMDGPU::getBasicFromSDWAOp(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), getNamedOperand(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineInstr::getNumExplicitOperands(), llvm::MCInstrDesc::getNumImplicitUses(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getNumOperands(), llvm::MCInstrDesc::getOpcode(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineInstr::getRegClassConstraint(), llvm::SIRegisterInfo::getRegClassForReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::MachineInstr::hasRegisterImplicitUseOperand(), llvm::AMDGPUSubtarget::hasSDWA(), llvm::GCNSubtarget::hasSDWAOmod(), llvm::GCNSubtarget::hasSDWAOutModsVOPC(), llvm::GCNSubtarget::hasSDWAScalar(), llvm::GCNSubtarget::hasSDWASdst(), llvm::SIRegisterInfo::hasVGPRs(), I, llvm::MachineOperand::isFI(), isFLAT(), llvm::MachineOperand::isFPImm(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isImplicit(), llvm::MachineInstr::isInlineAsm(), isInlineConstant(), llvm::isInt< 16 >(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineOperand::isReg(), llvm::MachineInstr::isRegTiedToUseOperand(), isSDWA(), isSMRD(), isSOPK(), isSubRegOf(), llvm::MachineOperand::isTied(), llvm::isUInt< 16 >(), llvm::MachineOperand::isUse(), llvm::MCInstrDesc::isVariadic(), llvm::TargetRegisterInfo::isVirtualRegister(), isVOP1(), isVOP2(), isVOP3(), isVOPC(), LLVM_FALLTHROUGH, llvm::MachineInstr::mayStore(), llvm::InlineAsm::MIOp_FirstOperand, MRI, llvm::MCOI::OPERAND_IMMEDIATE, llvm::AMDGPU::OPERAND_KIMM32, llvm::AMDGPU::OPERAND_REG_IMM_FP32, llvm::AMDGPU::OPERAND_REG_IMM_INT32, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP16, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP32, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP64, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT16, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT32, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT64, llvm::MCOI::OPERAND_REGISTER, llvm::MCOperandInfo::OperandType, llvm::MCInstrDesc::OpInfo, Reg, llvm::MCOperandInfo::RegClass, shouldReadExec(), sopkIsZext(), llvm::AMDGPU::SDWA::UNUSED_PRESERVE, and usesConstantBus().

Referenced by isLiteralConstant().


The documentation for this class was generated from the following files: