LLVM  6.0.0svn
Classes | Public Types | Public Member Functions | Protected Types | Protected Member Functions | Protected Attributes | List of all members
llvm::ScheduleDAGInstrs Class Referenceabstract

A ScheduleDAG for scheduling lists of MachineInstr. More...

#include "llvm/CodeGen/ScheduleDAGInstrs.h"

Inheritance diagram for llvm::ScheduleDAGInstrs:
Inheritance graph
[legend]
Collaboration diagram for llvm::ScheduleDAGInstrs:
Collaboration graph
[legend]

Classes

class  Value2SUsMap
 

Public Types

using SUList = std::list< SUnit * >
 A list of SUnits, used in Value2SUsMap, during DAG construction. More...
 

Public Member Functions

 ScheduleDAGInstrs (MachineFunction &mf, const MachineLoopInfo *mli, bool RemoveKillFlags=false)
 
 ~ScheduleDAGInstrs () override=default
 
const TargetSchedModelgetSchedModel () const
 Gets the machine model for instruction scheduling. More...
 
const MCSchedClassDescgetSchedClass (SUnit *SU) const
 Resolves and cache a resolved scheduling class for an SUnit. More...
 
MachineBasicBlock::iterator begin () const
 Returns an iterator to the top of the current scheduling region. More...
 
MachineBasicBlock::iterator end () const
 Returns an iterator to the bottom of the current scheduling region. More...
 
SUnitnewSUnit (MachineInstr *MI)
 Creates a new SUnit and return a ptr to it. More...
 
SUnitgetSUnit (MachineInstr *MI) const
 Returns an existing SUnit for this MI, or nullptr. More...
 
virtual bool doMBBSchedRegionsTopDown () const
 If this method returns true, handling of the scheduling regions themselves (in case of a scheduling boundary in MBB) will be done beginning with the topmost region of MBB. More...
 
virtual void startBlock (MachineBasicBlock *BB)
 Prepares to perform scheduling in the given block. More...
 
virtual void finishBlock ()
 Cleans up after scheduling in the given block. More...
 
virtual void enterRegion (MachineBasicBlock *bb, MachineBasicBlock::iterator begin, MachineBasicBlock::iterator end, unsigned regioninstrs)
 Initialize the DAG and common scheduler state for a new scheduling region. More...
 
virtual void exitRegion ()
 Called when the scheduler has finished scheduling the current region. More...
 
void buildSchedGraph (AliasAnalysis *AA, RegPressureTracker *RPTracker=nullptr, PressureDiffs *PDiffs=nullptr, LiveIntervals *LIS=nullptr, bool TrackLaneMasks=false)
 Builds SUnits for the current region. More...
 
void addSchedBarrierDeps ()
 Adds dependencies from instructions in the current list of instructions being scheduled to scheduling barrier. More...
 
virtual void schedule ()=0
 Orders nodes according to selected style. More...
 
virtual void finalizeSchedule ()
 Allow targets to perform final scheduling actions at the level of the whole MachineFunction. More...
 
void dumpNode (const SUnit *SU) const override
 
std::string getGraphNodeLabel (const SUnit *SU) const override
 Returns a label for a DAG node that points to an instruction. More...
 
std::string getDAGName () const override
 Returns a label for the region of code covered by the DAG. More...
 
void fixupKills (MachineBasicBlock &MBB)
 Fixes register kill flags that scheduling has made invalid. More...
 
- Public Member Functions inherited from llvm::ScheduleDAG
 ScheduleDAG (MachineFunction &mf)
 
virtual ~ScheduleDAG ()
 
void clearDAG ()
 Clears the DAG state (between regions). More...
 
const MCInstrDescgetInstrDesc (const SUnit *SU) const
 Returns the MCInstrDesc of this SUnit. More...
 
virtual void viewGraph (const Twine &Name, const Twine &Title)
 Pops up a GraphViz/gv window with the ScheduleDAG rendered using 'dot'. More...
 
virtual void viewGraph ()
 Out-of-line implementation with no arguments is handy for gdb. More...
 
virtual void addCustomGraphFeatures (GraphWriter< ScheduleDAG *> &) const
 Adds custom features for a visualization of the ScheduleDAG. More...
 
unsigned VerifyScheduledDAG (bool isBottomUp)
 Verifies that all SUnits were scheduled and that their state is consistent. More...
 

Protected Types

using DbgValueVector = std::vector< std::pair< MachineInstr *, MachineInstr * > >
 

Protected Member Functions

void reduceHugeMemNodeMaps (Value2SUsMap &stores, Value2SUsMap &loads, unsigned N)
 Reduces maps in FIFO order, by N SUs. More...
 
void addChainDependency (SUnit *SUa, SUnit *SUb, unsigned Latency=0)
 Adds a chain edge between SUa and SUb, but only if both AliasAnalysis and Target fail to deny the dependency. More...
 
void addChainDependencies (SUnit *SU, SUList &SUs, unsigned Latency)
 Adds dependencies as needed from all SUs in list to SU. More...
 
void addChainDependencies (SUnit *SU, Value2SUsMap &Val2SUsMap)
 Adds dependencies as needed from all SUs in map, to SU. More...
 
void addChainDependencies (SUnit *SU, Value2SUsMap &Val2SUsMap, ValueType V)
 Adds dependencies as needed to SU, from all SUs mapped to V. More...
 
void addBarrierChain (Value2SUsMap &map)
 Adds barrier chain edges from all SUs in map, and then clear the map. More...
 
void insertBarrierChain (Value2SUsMap &map)
 Inserts a barrier chain in a huge region, far below current SU. More...
 
void initSUnits ()
 Creates an SUnit for each real instruction, numbered in top-down topological order. More...
 
void addPhysRegDataDeps (SUnit *SU, unsigned OperIdx)
 MO is an operand of SU's instruction that defines a physical register. More...
 
void addPhysRegDeps (SUnit *SU, unsigned OperIdx)
 Adds register dependencies (data, anti, and output) from this SUnit to following instructions in the same scheduling region that depend the physical register referenced at OperIdx. More...
 
void addVRegDefDeps (SUnit *SU, unsigned OperIdx)
 Adds register output and data dependencies from this SUnit to instructions that occur later in the same scheduling region if they read from or write to the virtual register defined at OperIdx. More...
 
void addVRegUseDeps (SUnit *SU, unsigned OperIdx)
 Adds a register data dependency if the instruction that defines the virtual register used at OperIdx is mapped to an SUnit. More...
 
void startBlockForKills (MachineBasicBlock *BB)
 Initializes register live-range state for updating kills. More...
 
void toggleKillFlag (MachineInstr &MI, MachineOperand &MO)
 Toggles a register operand kill flag. More...
 
LaneBitmask getLaneMaskForMO (const MachineOperand &MO) const
 Returns a mask for which lanes get read/written by the given (register) machine operand. More...
 

Protected Attributes

const MachineLoopInfoMLI
 
const MachineFrameInfoMFI
 
TargetSchedModel SchedModel
 TargetSchedModel provides an interface to the machine model. More...
 
bool RemoveKillFlags
 True if the DAG builder should remove kill flags (in preparation for rescheduling). More...
 
bool CanHandleTerminators = false
 The standard DAG builder does not normally include terminators as DAG nodes because it does not create the necessary dependencies to prevent reordering. More...
 
bool TrackLaneMasks = false
 Whether lane masks should get tracked. More...
 
MachineBasicBlockBB
 The block in which to insert instructions. More...
 
MachineBasicBlock::iterator RegionBegin
 The beginning of the range to be scheduled. More...
 
MachineBasicBlock::iterator RegionEnd
 The end of the range to be scheduled. More...
 
unsigned NumRegionInstrs
 Instructions in this region (distance(RegionBegin, RegionEnd)). More...
 
DenseMap< MachineInstr *, SUnit * > MISUnitMap
 After calling BuildSchedGraph, each machine instruction in the current scheduling region is mapped to an SUnit. More...
 
Reg2SUnitsMap Defs
 Defs, Uses - Remember where defs and uses of each register are as we iterate upward through the instructions. More...
 
Reg2SUnitsMap Uses
 
VReg2SUnitMultiMap CurrentVRegDefs
 Tracks the last instruction(s) in this region defining each virtual register. More...
 
VReg2SUnitOperIdxMultiMap CurrentVRegUses
 Tracks the last instructions in this region using each virtual register. More...
 
AliasAnalysisAAForDep = nullptr
 
SUnitBarrierChain = nullptr
 Remember a generic side-effecting instruction as we proceed. More...
 
UndefValueUnknownValue
 For an unanalyzable memory access, this Value is used in maps. More...
 
DbgValueVector DbgValues
 Remember instruction that precedes DBG_VALUE. More...
 
MachineInstrFirstDbgValue = nullptr
 
LivePhysRegs LiveRegs
 Set of live physical registers for updating kill flags. More...
 

Additional Inherited Members

- Public Attributes inherited from llvm::ScheduleDAG
const TargetMachineTM
 Target processor. More...
 
const TargetInstrInfoTII
 Target instruction information. More...
 
const TargetRegisterInfoTRI
 Target processor register info. More...
 
MachineFunctionMF
 Machine function. More...
 
MachineRegisterInfoMRI
 Virtual/real register map. More...
 
std::vector< SUnitSUnits
 The scheduling units. More...
 
SUnit EntrySU
 Special node for the region entry. More...
 
SUnit ExitSU
 Special node for the region exit. More...
 
bool StressSched
 

Detailed Description

A ScheduleDAG for scheduling lists of MachineInstr.

Definition at line 119 of file ScheduleDAGInstrs.h.

Member Typedef Documentation

◆ DbgValueVector

using llvm::ScheduleDAGInstrs::DbgValueVector = std::vector<std::pair<MachineInstr *, MachineInstr *> >
protected

Definition at line 239 of file ScheduleDAGInstrs.h.

◆ SUList

using llvm::ScheduleDAGInstrs::SUList = std::list<SUnit *>

A list of SUnits, used in Value2SUsMap, during DAG construction.

Note: to gain speed it might be worth investigating an optimized implementation of this data structure, such as a singly linked list with a memory pool (SmallVector was tried but slow and SparseSet is not applicable).

Definition at line 190 of file ScheduleDAGInstrs.h.

Constructor & Destructor Documentation

◆ ScheduleDAGInstrs()

ScheduleDAGInstrs::ScheduleDAGInstrs ( MachineFunction mf,
const MachineLoopInfo mli,
bool  RemoveKillFlags = false 
)
explicit

◆ ~ScheduleDAGInstrs()

llvm::ScheduleDAGInstrs::~ScheduleDAGInstrs ( )
overridedefault

Member Function Documentation

◆ addBarrierChain()

void ScheduleDAGInstrs::addBarrierChain ( Value2SUsMap map)
protected

Adds barrier chain edges from all SUs in map, and then clear the map.

This is equivalent to insertBarrierChain(), but optimized for the common case where the new BarrierChain (a global memory object) has a higher NodeNum than all SUs in map. It is assumed BarrierChain has been set before calling this.

Definition at line 646 of file ScheduleDAGInstrs.cpp.

References assert(), BarrierChain, and I.

Referenced by buildSchedGraph().

◆ addChainDependencies() [1/3]

void llvm::ScheduleDAGInstrs::addChainDependencies ( SUnit SU,
SUList SUs,
unsigned  Latency 
)
inlineprotected

Adds dependencies as needed from all SUs in list to SU.

Definition at line 210 of file ScheduleDAGInstrs.h.

References llvm::VReg2SUnit::SU.

Referenced by addChainDependencies(), and buildSchedGraph().

◆ addChainDependencies() [2/3]

void ScheduleDAGInstrs::addChainDependencies ( SUnit SU,
Value2SUsMap Val2SUsMap 
)
protected

Adds dependencies as needed from all SUs in map, to SU.

Definition at line 630 of file ScheduleDAGInstrs.cpp.

References addChainDependencies(), and I.

◆ addChainDependencies() [3/3]

void ScheduleDAGInstrs::addChainDependencies ( SUnit SU,
Value2SUsMap Val2SUsMap,
ValueType  V 
)
protected

◆ addChainDependency()

void ScheduleDAGInstrs::addChainDependency ( SUnit SUa,
SUnit SUb,
unsigned  Latency = 0 
)
protected

Adds a chain edge between SUa and SUb, but only if both AliasAnalysis and Target fail to deny the dependency.

Definition at line 508 of file ScheduleDAGInstrs.cpp.

References AAForDep, llvm::SUnit::addPred(), llvm::SUnit::getInstr(), llvm::MachineInstr::mayAlias(), llvm::SDep::MayAliasMem, llvm::SDep::setLatency(), and UseTBAA.

◆ addPhysRegDataDeps()

void ScheduleDAGInstrs::addPhysRegDataDeps ( SUnit SU,
unsigned  OperIdx 
)
protected

◆ addPhysRegDeps()

void ScheduleDAGInstrs::addPhysRegDeps ( SUnit SU,
unsigned  OperIdx 
)
protected

◆ addSchedBarrierDeps()

void ScheduleDAGInstrs::addSchedBarrierDeps ( )

Adds dependencies from instructions in the current list of instructions being scheduled to scheduling barrier.

We want to make sure instructions which define registers that are either used by the terminator or are live-out are properly scheduled. This is especially important when the definition latency of the return value(s) are too high to be hidden by the branch or when the liveout registers used by instructions in the fallthrough block.

Definition at line 200 of file ScheduleDAGInstrs.cpp.

References addVRegUseDeps(), BB, llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::contains(), llvm::MachineBasicBlock::end(), llvm::ScheduleDAG::ExitSU, llvm::MachineInstr::getOperandNo(), llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::insert(), llvm::MachineInstr::isBarrier(), llvm::MachineInstr::isCall(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::MachineInstr::operands(), RegionEnd, llvm::SUnit::setInstr(), llvm::MachineBasicBlock::successors(), and Uses.

Referenced by buildSchedGraph().

◆ addVRegDefDeps()

void ScheduleDAGInstrs::addVRegDefDeps ( SUnit SU,
unsigned  OperIdx 
)
protected

◆ addVRegUseDeps()

void ScheduleDAGInstrs::addVRegUseDeps ( SUnit SU,
unsigned  OperIdx 
)
protected

Adds a register data dependency if the instruction that defines the virtual register used at OperIdx is mapped to an SUnit.

Add a register antidependency from this SUnit to instructions that occur later in the same scheduling region if they write the virtual register.

TODO: Handle ExitSU "uses" properly.

Definition at line 477 of file ScheduleDAGInstrs.cpp.

References llvm::SDep::Anti, CurrentVRegDefs, CurrentVRegUses, llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::end(), llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::find(), llvm::LaneBitmask::getAll(), llvm::SUnit::getInstr(), getLaneMaskForMO(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::insert(), llvm::make_range(), MI, and TrackLaneMasks.

Referenced by addSchedBarrierDeps(), and buildSchedGraph().

◆ begin()

MachineBasicBlock::iterator llvm::ScheduleDAGInstrs::begin ( ) const
inline

◆ buildSchedGraph()

void ScheduleDAGInstrs::buildSchedGraph ( AliasAnalysis AA,
RegPressureTracker RPTracker = nullptr,
PressureDiffs PDiffs = nullptr,
LiveIntervals LIS = nullptr,
bool  TrackLaneMasks = false 
)

Builds SUnits for the current region.

If RPTracker is non-null, compute register pressure as a side effect. The DAG builder is an efficient place to do it because it already visits operands.

Definition at line 690 of file ScheduleDAGInstrs.cpp.

References AAForDep, addBarrierChain(), addChainDependencies(), llvm::PressureDiffs::addInstruction(), addPhysRegDeps(), llvm::SUnit::addPred(), llvm::SUnit::addPredBarrier(), addSchedBarrierDeps(), addVRegDefDeps(), addVRegUseDeps(), llvm::RegisterOperands::adjustLaneLiveness(), llvm::SDep::Artificial, assert(), BarrierChain, CanHandleTerminators, llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::clear(), llvm::ScheduleDAG::clearDAG(), llvm::RegisterOperands::collect(), CurrentVRegDefs, CurrentVRegUses, llvm::dbgs(), DbgValues, DEBUG, Defs, llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::empty(), EnableAASchedMI, llvm::ScheduleDAG::ExitSU, FirstDbgValue, llvm::MachineFunction::getDataLayout(), llvm::LiveIntervals::getInstructionIndex(), llvm::MachineInstr::getNumOperands(), llvm::MCRegisterInfo::getNumRegs(), llvm::MachineRegisterInfo::getNumVirtRegs(), llvm::MachineInstr::getOperand(), llvm::RegPressureTracker::getPos(), getReductionSize(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getSubtarget(), getUnderlyingObjectsForInstr(), HugeRegion, llvm::PressureDiffs::init(), initSUnits(), llvm::ScheduleDAGInstrs::Value2SUsMap::insert(), llvm::MachineInstr::isDebugValue(), llvm::MachineOperand::isDef(), llvm::MachineInstr::isDereferenceableInvariantLoad(), isGlobalMemoryObject(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineInstr::isPosition(), llvm::MachineOperand::isReg(), llvm::MachineInstr::isTerminator(), llvm::MachineOperand::isUse(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::SUnit::Latency, llvm::MachineInstr::mayLoad(), llvm::MachineInstr::mayStore(), llvm::ScheduleDAG::MF, MFI, MI, MISUnitMap, llvm::ScheduleDAG::MRI, llvm::SUnit::NodeNum, llvm::SUnit::NumSuccs, llvm::MachineOperand::readsReg(), llvm::RegPressureTracker::recede(), llvm::RegPressureTracker::recedeSkipDebugValues(), reduceHugeMemNodeMaps(), RegionBegin, RegionEnd, llvm::SDep::setLatency(), llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::setUniverse(), llvm::ScheduleDAGInstrs::Value2SUsMap::size(), llvm::ARM_MB::ST, llvm::ScheduleDAG::SUnits, TrackLaneMasks, llvm::ScheduleDAG::TRI, UnknownValue, llvm::TargetSubtargetInfo::useAA(), and Uses.

Referenced by llvm::GCNIterativeScheduler::BuildDAG::BuildDAG(), and llvm::DefaultVLIWScheduler::schedule().

◆ doMBBSchedRegionsTopDown()

virtual bool llvm::ScheduleDAGInstrs::doMBBSchedRegionsTopDown ( ) const
inlinevirtual

If this method returns true, handling of the scheduling regions themselves (in case of a scheduling boundary in MBB) will be done beginning with the topmost region of MBB.

Reimplemented in llvm::ScheduleDAGMI.

Definition at line 281 of file ScheduleDAGInstrs.h.

References llvm::sys::path::begin(), and llvm::sys::path::end().

Referenced by getSchedRegions().

◆ dumpNode()

void ScheduleDAGInstrs::dumpNode ( const SUnit SU) const
overridevirtual

Implements llvm::ScheduleDAG.

Definition at line 1097 of file ScheduleDAGInstrs.cpp.

References llvm::MachineInstr::dump(), and llvm::SUnit::getInstr().

◆ end()

MachineBasicBlock::iterator llvm::ScheduleDAGInstrs::end ( ) const
inline

Returns an iterator to the bottom of the current scheduling region.

Definition at line 270 of file ScheduleDAGInstrs.h.

References MI.

Referenced by llvm::ScheduleDAGInstrs::Value2SUsMap::clearList(), llvm::createCopyConstrainDAGMutation(), enterRegion(), llvm::GCNScheduleDAGMILive::finalizeSchedule(), and llvm::GCNScheduleDAGMILive::schedule().

◆ enterRegion()

void ScheduleDAGInstrs::enterRegion ( MachineBasicBlock bb,
MachineBasicBlock::iterator  begin,
MachineBasicBlock::iterator  end,
unsigned  regioninstrs 
)
virtual

Initialize the DAG and common scheduler state for a new scheduling region.

This does not actually create the DAG, only clears it. The scheduling driver may call BuildSchedGraph multiple times per scheduling region.

Reimplemented in llvm::ScheduleDAGMILive, llvm::ScheduleDAGMI, and llvm::GCNIterativeScheduler.

Definition at line 186 of file ScheduleDAGInstrs.cpp.

References assert(), BB, begin(), end(), NumRegionInstrs, RegionBegin, and RegionEnd.

Referenced by llvm::ScheduleDAGMI::enterRegion(), getSchedRegions(), INITIALIZE_PASS(), and llvm::VLIWPacketizerList::PacketizeMIs().

◆ exitRegion()

void ScheduleDAGInstrs::exitRegion ( )
virtual

Called when the scheduler has finished scheduling the current region.

Definition at line 196 of file ScheduleDAGInstrs.cpp.

Referenced by llvm::GCNScheduleDAGMILive::finalizeSchedule(), getSchedRegions(), INITIALIZE_PASS(), and llvm::VLIWPacketizerList::PacketizeMIs().

◆ finalizeSchedule()

virtual void llvm::ScheduleDAGInstrs::finalizeSchedule ( )
inlinevirtual

Allow targets to perform final scheduling actions at the level of the whole MachineFunction.

By default does nothing.

Reimplemented in llvm::GCNScheduleDAGMILive, and llvm::GCNIterativeScheduler.

Definition at line 328 of file ScheduleDAGInstrs.h.

Referenced by getSchedRegions().

◆ finishBlock()

void ScheduleDAGInstrs::finishBlock ( )
virtual

Cleans up after scheduling in the given block.

Reimplemented in llvm::ScheduleDAGMI.

Definition at line 181 of file ScheduleDAGInstrs.cpp.

References BB.

Referenced by llvm::ScheduleDAGMI::finishBlock(), getSchedRegions(), INITIALIZE_PASS(), and llvm::VLIWPacketizerList::PacketizeMIs().

◆ fixupKills()

void ScheduleDAGInstrs::fixupKills ( MachineBasicBlock MBB)

◆ getDAGName()

std::string ScheduleDAGInstrs::getDAGName ( ) const
overridevirtual

Returns a label for the region of code covered by the DAG.

Return the basic block label.

It is not necessarilly unique because a block contains multiple scheduling regions. But it is fine for visualization.

Implements llvm::ScheduleDAG.

Definition at line 1118 of file ScheduleDAGInstrs.cpp.

References BB, and llvm::MachineBasicBlock::getFullName().

◆ getGraphNodeLabel()

std::string ScheduleDAGInstrs::getGraphNodeLabel ( const SUnit SU) const
overridevirtual

Returns a label for a DAG node that points to an instruction.

Implements llvm::ScheduleDAG.

Definition at line 1104 of file ScheduleDAGInstrs.cpp.

References llvm::ScheduleDAG::EntrySU, llvm::ScheduleDAG::ExitSU, llvm::SUnit::getInstr(), llvm::MachineInstr::print(), and llvm::raw_string_ostream::str().

◆ getLaneMaskForMO()

LaneBitmask ScheduleDAGInstrs::getLaneMaskForMO ( const MachineOperand MO) const
protected

◆ getSchedClass()

const MCSchedClassDesc* llvm::ScheduleDAGInstrs::getSchedClass ( SUnit SU) const
inline

◆ getSchedModel()

const TargetSchedModel* llvm::ScheduleDAGInstrs::getSchedModel ( ) const
inline

Gets the machine model for instruction scheduling.

Definition at line 257 of file ScheduleDAGInstrs.h.

Referenced by llvm::GenericScheduler::initialize(), and llvm::PostGenericScheduler::initialize().

◆ getSUnit()

SUnit * llvm::ScheduleDAGInstrs::getSUnit ( MachineInstr MI) const
inline

Returns an existing SUnit for this MI, or nullptr.

Definition at line 375 of file ScheduleDAGInstrs.h.

References I.

Referenced by llvm::createCopyConstrainDAGMutation().

◆ initSUnits()

void ScheduleDAGInstrs::initSUnits ( )
protected

Creates an SUnit for each real instruction, numbered in top-down topological order.

The instruction order A < B, implies that no edge exists from B to A.

Map each real instruction to its SUnit.

After initSUnits, the SUnits vector cannot be resized and the scheduler may hang onto SUnit pointers. We may relax this in the future by using SUnit IDs instead of pointers.

MachineScheduler relies on initSUnits numbering the nodes by their order in the original instruction list.

Definition at line 529 of file ScheduleDAGInstrs.cpp.

References llvm::MCProcResourceDesc::BufferSize, llvm::SUnit::getInstr(), llvm::TargetSchedModel::getProcResource(), getSchedClass(), llvm::TargetSchedModel::getWriteProcResBegin(), llvm::TargetSchedModel::getWriteProcResEnd(), llvm::TargetSchedModel::hasInstrSchedModel(), llvm::SUnit::hasReservedResource, llvm::SUnit::isCall, llvm::SUnit::isCommutable, llvm::SUnit::isUnbuffered, llvm::SUnit::Latency, llvm::make_range(), MI, MISUnitMap, newSUnit(), NumRegionInstrs, RegionBegin, RegionEnd, llvm::PPCISD::SC, SchedModel, and llvm::ScheduleDAG::SUnits.

Referenced by buildSchedGraph().

◆ insertBarrierChain()

void ScheduleDAGInstrs::insertBarrierChain ( Value2SUsMap map)
protected

Inserts a barrier chain in a huge region, far below current SU.

Adds barrier chain edges from all SUs in map with higher NodeNums than this new BarrierChain, and remove them from map. It is assumed BarrierChain has been set before calling this.

Definition at line 657 of file ScheduleDAGInstrs.cpp.

References assert(), BarrierChain, llvm::MapVector< KeyT, ValueT, MapType, VectorType >::begin(), llvm::MapVector< KeyT, ValueT, MapType, VectorType >::end(), I, llvm::SUnit::NodeNum, llvm::ScheduleDAGInstrs::Value2SUsMap::reComputeSize(), and llvm::MapVector< KeyT, ValueT, MapType, VectorType >::remove_if().

Referenced by reduceHugeMemNodeMaps().

◆ newSUnit()

SUnit * llvm::ScheduleDAGInstrs::newSUnit ( MachineInstr MI)
inline

Creates a new SUnit and return a ptr to it.

Definition at line 364 of file ScheduleDAGInstrs.h.

References assert().

Referenced by initSUnits().

◆ reduceHugeMemNodeMaps()

void ScheduleDAGInstrs::reduceHugeMemNodeMaps ( Value2SUsMap stores,
Value2SUsMap loads,
unsigned  N 
)
protected

Reduces maps in FIFO order, by N SUs.

This is better than turning every Nth memory SU into BarrierChain in buildSchedGraph(), since it avoids unnecessary edges between seen SUs above the new BarrierChain, and those below it.

Definition at line 978 of file ScheduleDAGInstrs.cpp.

References llvm::SUnit::addPredBarrier(), assert(), BarrierChain, llvm::dbgs(), DEBUG, llvm::ScheduleDAGInstrs::Value2SUsMap::dump(), I, insertBarrierChain(), N, llvm::SUnit::NodeNum, llvm::ScheduleDAGInstrs::Value2SUsMap::size(), llvm::parallel::sort(), and llvm::ScheduleDAG::SUnits.

Referenced by buildSchedGraph().

◆ schedule()

virtual void llvm::ScheduleDAGInstrs::schedule ( )
pure virtual

Orders nodes according to selected style.

Typically, a scheduling algorithm will implement schedule() without overriding enterRegion() or exitRegion().

Implemented in llvm::ScheduleDAGMILive, llvm::SIScheduleDAGMI, llvm::ScheduleDAGMI, llvm::DefaultVLIWScheduler, llvm::GCNScheduleDAGMILive, llvm::VLIWMachineScheduler, and llvm::GCNIterativeScheduler.

Referenced by getSchedRegions().

◆ startBlock()

void ScheduleDAGInstrs::startBlock ( MachineBasicBlock BB)
virtual

Prepares to perform scheduling in the given block.

Reimplemented in llvm::ScheduleDAGMI.

Definition at line 177 of file ScheduleDAGInstrs.cpp.

References BB.

Referenced by getSchedRegions(), INITIALIZE_PASS(), llvm::VLIWPacketizerList::PacketizeMIs(), and llvm::ScheduleDAGMI::startBlock().

◆ startBlockForKills()

void llvm::ScheduleDAGInstrs::startBlockForKills ( MachineBasicBlock BB)
protected

Initializes register live-range state for updating kills.

PostRA helper for rewriting kill flags.

◆ toggleKillFlag()

void llvm::ScheduleDAGInstrs::toggleKillFlag ( MachineInstr MI,
MachineOperand MO 
)
protected

Toggles a register operand kill flag.

Other adjustments may be made to the instruction if necessary. Return true if the operand has been deleted, false if not.

Member Data Documentation

◆ AAForDep

AliasAnalysis* llvm::ScheduleDAGInstrs::AAForDep = nullptr
protected

Definition at line 177 of file ScheduleDAGInstrs.h.

Referenced by addChainDependency(), and buildSchedGraph().

◆ BarrierChain

SUnit* llvm::ScheduleDAGInstrs::BarrierChain = nullptr
protected

Remember a generic side-effecting instruction as we proceed.

No other SU ever gets scheduled around it (except in the special case of a huge region that gets reduced).

Definition at line 182 of file ScheduleDAGInstrs.h.

Referenced by addBarrierChain(), buildSchedGraph(), insertBarrierChain(), and reduceHugeMemNodeMaps().

◆ BB

MachineBasicBlock* llvm::ScheduleDAGInstrs::BB
protected

◆ CanHandleTerminators

bool llvm::ScheduleDAGInstrs::CanHandleTerminators = false
protected

The standard DAG builder does not normally include terminators as DAG nodes because it does not create the necessary dependencies to prevent reordering.

A specialized scheduler can override TargetInstrInfo::isSchedulingBoundary then enable this flag to indicate it has taken responsibility for scheduling the terminator correctly.

Definition at line 136 of file ScheduleDAGInstrs.h.

Referenced by buildSchedGraph(), and llvm::DefaultVLIWScheduler::DefaultVLIWScheduler().

◆ CurrentVRegDefs

VReg2SUnitMultiMap llvm::ScheduleDAGInstrs::CurrentVRegDefs
protected

Tracks the last instruction(s) in this region defining each virtual register.

There may be multiple current definitions for a register with disjunct lanemasks.

Definition at line 173 of file ScheduleDAGInstrs.h.

Referenced by addVRegDefDeps(), addVRegUseDeps(), and buildSchedGraph().

◆ CurrentVRegUses

VReg2SUnitOperIdxMultiMap llvm::ScheduleDAGInstrs::CurrentVRegUses
protected

Tracks the last instructions in this region using each virtual register.

Definition at line 175 of file ScheduleDAGInstrs.h.

Referenced by addVRegDefDeps(), addVRegUseDeps(), and buildSchedGraph().

◆ DbgValues

DbgValueVector llvm::ScheduleDAGInstrs::DbgValues
protected

Remember instruction that precedes DBG_VALUE.

These are generated by buildSchedGraph but persist so they can be referenced when emitting the final schedule.

Definition at line 243 of file ScheduleDAGInstrs.h.

Referenced by buildSchedGraph(), llvm::GCNIterativeScheduler::detachSchedule(), and ScheduleDAGInstrs().

◆ Defs

Reg2SUnitsMap llvm::ScheduleDAGInstrs::Defs
protected

Defs, Uses - Remember where defs and uses of each register are as we iterate upward through the instructions.

This is allocated here instead of inside BuildSchedGraph to avoid the need for it to be initialized and destructed for each block.

Definition at line 167 of file ScheduleDAGInstrs.h.

Referenced by addPhysRegDeps(), and buildSchedGraph().

◆ FirstDbgValue

MachineInstr* llvm::ScheduleDAGInstrs::FirstDbgValue = nullptr
protected

◆ LiveRegs

LivePhysRegs llvm::ScheduleDAGInstrs::LiveRegs
protected

Set of live physical registers for updating kill flags.

Definition at line 247 of file ScheduleDAGInstrs.h.

Referenced by fixupKills().

◆ MFI

const MachineFrameInfo& llvm::ScheduleDAGInstrs::MFI
protected

Definition at line 122 of file ScheduleDAGInstrs.h.

Referenced by buildSchedGraph().

◆ MISUnitMap

DenseMap<MachineInstr*, SUnit*> llvm::ScheduleDAGInstrs::MISUnitMap
protected

After calling BuildSchedGraph, each machine instruction in the current scheduling region is mapped to an SUnit.

Definition at line 158 of file ScheduleDAGInstrs.h.

Referenced by buildSchedGraph(), and initSUnits().

◆ MLI

const MachineLoopInfo* llvm::ScheduleDAGInstrs::MLI
protected

Definition at line 121 of file ScheduleDAGInstrs.h.

◆ NumRegionInstrs

unsigned llvm::ScheduleDAGInstrs::NumRegionInstrs
protected

Instructions in this region (distance(RegionBegin, RegionEnd)).

Definition at line 154 of file ScheduleDAGInstrs.h.

Referenced by llvm::GCNIterativeScheduler::enterRegion(), enterRegion(), llvm::GCNScheduleDAGMILive::finalizeSchedule(), initSUnits(), and llvm::GCNScheduleDAGMILive::schedule().

◆ RegionBegin

MachineBasicBlock::iterator llvm::ScheduleDAGInstrs::RegionBegin
protected

◆ RegionEnd

MachineBasicBlock::iterator llvm::ScheduleDAGInstrs::RegionEnd
protected

◆ RemoveKillFlags

bool llvm::ScheduleDAGInstrs::RemoveKillFlags
protected

True if the DAG builder should remove kill flags (in preparation for rescheduling).

Definition at line 129 of file ScheduleDAGInstrs.h.

Referenced by addPhysRegDeps().

◆ SchedModel

TargetSchedModel llvm::ScheduleDAGInstrs::SchedModel
protected

TargetSchedModel provides an interface to the machine model.

Definition at line 125 of file ScheduleDAGInstrs.h.

Referenced by addPhysRegDataDeps(), addPhysRegDeps(), addVRegDefDeps(), initSUnits(), and ScheduleDAGInstrs().

◆ TrackLaneMasks

bool llvm::ScheduleDAGInstrs::TrackLaneMasks = false
protected

Whether lane masks should get tracked.

Definition at line 139 of file ScheduleDAGInstrs.h.

Referenced by addVRegDefDeps(), addVRegUseDeps(), and buildSchedGraph().

◆ UnknownValue

UndefValue* llvm::ScheduleDAGInstrs::UnknownValue
protected

For an unanalyzable memory access, this Value is used in maps.

Definition at line 236 of file ScheduleDAGInstrs.h.

Referenced by buildSchedGraph().

◆ Uses

Reg2SUnitsMap llvm::ScheduleDAGInstrs::Uses
protected

The documentation for this class was generated from the following files: