LLVM  6.0.0svn
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llvm::SelectionDAG Class Reference

This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representation suitable for instruction selection. More...

#include "llvm/CodeGen/SelectionDAG.h"

Collaboration diagram for llvm::SelectionDAG:
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Classes

struct  DAGNodeDeletedListener
 
struct  DAGUpdateListener
 Clients of various APIs that cause global effects on the DAG can optionally implement this interface. More...
 

Public Types

enum  OverflowKind { OFK_Never, OFK_Sometime, OFK_Always }
 Used to represent the possible overflow behavior of an operation. More...
 
using allnodes_const_iterator = ilist< SDNode >::const_iterator
 
using allnodes_iterator = ilist< SDNode >::iterator
 

Public Member Functions

 SelectionDAG (const TargetMachine &TM, CodeGenOpt::Level)
 
 SelectionDAG (const SelectionDAG &)=delete
 
SelectionDAGoperator= (const SelectionDAG &)=delete
 
 ~SelectionDAG ()
 
void init (MachineFunction &NewMF, OptimizationRemarkEmitter &NewORE, Pass *PassPtr)
 Prepare this SelectionDAG to process code in the given MachineFunction. More...
 
void clear ()
 Clear state and free memory necessary to make this SelectionDAG ready to process a new block. More...
 
MachineFunctiongetMachineFunction () const
 
const PassgetPass () const
 
const DataLayoutgetDataLayout () const
 
const TargetMachinegetTarget () const
 
const TargetSubtargetInfogetSubtarget () const
 
const TargetLoweringgetTargetLoweringInfo () const
 
const SelectionDAGTargetInfogetSelectionDAGInfo () const
 
LLVMContextgetContext () const
 
OptimizationRemarkEmittergetORE () const
 
void viewGraph (const std::string &Title)
 Pop up a GraphViz/gv window with the DAG rendered using 'dot'. More...
 
void viewGraph ()
 
void clearGraphAttrs ()
 Clear all previously defined node graph attributes. More...
 
void setGraphAttrs (const SDNode *N, const char *Attrs)
 Set graph attributes for a node. (eg. "color=red".) More...
 
const std::string getGraphAttrs (const SDNode *N) const
 Get graph attributes for a node. More...
 
void setGraphColor (const SDNode *N, const char *Color)
 Convenience for setting node color attribute. More...
 
void setSubgraphColor (SDNode *N, const char *Color)
 Convenience for setting subgraph color attribute. More...
 
allnodes_const_iterator allnodes_begin () const
 
allnodes_const_iterator allnodes_end () const
 
allnodes_iterator allnodes_begin ()
 
allnodes_iterator allnodes_end ()
 
ilist< SDNode >::size_type allnodes_size () const
 
iterator_range< allnodes_iteratorallnodes ()
 
iterator_range< allnodes_const_iteratorallnodes () const
 
const SDValuegetRoot () const
 Return the root tag of the SelectionDAG. More...
 
SDValue getEntryNode () const
 Return the token chain corresponding to the entry of the function. More...
 
const SDValuesetRoot (SDValue N)
 Set the current root tag of the SelectionDAG. More...
 
void Combine (CombineLevel Level, AliasAnalysis *AA, CodeGenOpt::Level OptLevel)
 This iterates over the nodes in the SelectionDAG, folding certain types of nodes together, or eliminating superfluous nodes. More...
 
bool LegalizeTypes ()
 This transforms the SelectionDAG into a SelectionDAG that only uses types natively supported by the target. More...
 
void Legalize ()
 This transforms the SelectionDAG into a SelectionDAG that is compatible with the target instruction selector, as indicated by the TargetLowering object. More...
 
bool LegalizeOp (SDNode *N, SmallSetVector< SDNode *, 16 > &UpdatedNodes)
 Transforms a SelectionDAG node and any operands to it into a node that is compatible with the target instruction selector, as indicated by the TargetLowering object. More...
 
bool LegalizeVectors ()
 This transforms the SelectionDAG into a SelectionDAG that only uses vector math operations supported by the target. More...
 
void RemoveDeadNodes ()
 This method deletes all unreachable nodes in the SelectionDAG. More...
 
void DeleteNode (SDNode *N)
 Remove the specified node from the system. More...
 
SDVTList getVTList (EVT VT)
 Return an SDVTList that represents the list of values specified. More...
 
SDVTList getVTList (EVT VT1, EVT VT2)
 
SDVTList getVTList (EVT VT1, EVT VT2, EVT VT3)
 
SDVTList getVTList (EVT VT1, EVT VT2, EVT VT3, EVT VT4)
 
SDVTList getVTList (ArrayRef< EVT > VTs)
 
SDValue getGlobalAddress (const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, bool isTargetGA=false, unsigned char TargetFlags=0)
 
SDValue getTargetGlobalAddress (const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
 
SDValue getFrameIndex (int FI, EVT VT, bool isTarget=false)
 
SDValue getTargetFrameIndex (int FI, EVT VT)
 
SDValue getJumpTable (int JTI, EVT VT, bool isTarget=false, unsigned char TargetFlags=0)
 
SDValue getTargetJumpTable (int JTI, EVT VT, unsigned char TargetFlags=0)
 
SDValue getConstantPool (const Constant *C, EVT VT, unsigned Align=0, int Offs=0, bool isT=false, unsigned char TargetFlags=0)
 
SDValue getTargetConstantPool (const Constant *C, EVT VT, unsigned Align=0, int Offset=0, unsigned char TargetFlags=0)
 
SDValue getConstantPool (MachineConstantPoolValue *C, EVT VT, unsigned Align=0, int Offs=0, bool isT=false, unsigned char TargetFlags=0)
 
SDValue getTargetConstantPool (MachineConstantPoolValue *C, EVT VT, unsigned Align=0, int Offset=0, unsigned char TargetFlags=0)
 
SDValue getTargetIndex (int Index, EVT VT, int64_t Offset=0, unsigned char TargetFlags=0)
 
SDValue getBasicBlock (MachineBasicBlock *MBB)
 
SDValue getBasicBlock (MachineBasicBlock *MBB, SDLoc dl)
 
SDValue getExternalSymbol (const char *Sym, EVT VT)
 
SDValue getExternalSymbol (const char *Sym, const SDLoc &dl, EVT VT)
 
SDValue getTargetExternalSymbol (const char *Sym, EVT VT, unsigned char TargetFlags=0)
 
SDValue getMCSymbol (MCSymbol *Sym, EVT VT)
 
SDValue getValueType (EVT)
 
SDValue getRegister (unsigned Reg, EVT VT)
 
SDValue getRegisterMask (const uint32_t *RegMask)
 
SDValue getEHLabel (const SDLoc &dl, SDValue Root, MCSymbol *Label)
 
SDValue getLabelNode (unsigned Opcode, const SDLoc &dl, SDValue Root, MCSymbol *Label)
 
SDValue getBlockAddress (const BlockAddress *BA, EVT VT, int64_t Offset=0, bool isTarget=false, unsigned char TargetFlags=0)
 
SDValue getTargetBlockAddress (const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned char TargetFlags=0)
 
SDValue getCopyToReg (SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
 
SDValue getCopyToReg (SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N, SDValue Glue)
 
SDValue getCopyToReg (SDValue Chain, const SDLoc &dl, SDValue Reg, SDValue N, SDValue Glue)
 
SDValue getCopyFromReg (SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
 
SDValue getCopyFromReg (SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT, SDValue Glue)
 
SDValue getCondCode (ISD::CondCode Cond)
 
SDValue getVectorShuffle (EVT VT, const SDLoc &dl, SDValue N1, SDValue N2, ArrayRef< int > Mask)
 Return an ISD::VECTOR_SHUFFLE node. More...
 
SDValue getBuildVector (EVT VT, const SDLoc &DL, ArrayRef< SDValue > Ops)
 Return an ISD::BUILD_VECTOR node. More...
 
SDValue getBuildVector (EVT VT, const SDLoc &DL, ArrayRef< SDUse > Ops)
 Return an ISD::BUILD_VECTOR node. More...
 
SDValue getSplatBuildVector (EVT VT, const SDLoc &DL, SDValue Op)
 Return a splat ISD::BUILD_VECTOR node, consisting of Op splatted to all elements. More...
 
SDValue getCommutedVectorShuffle (const ShuffleVectorSDNode &SV)
 Returns an ISD::VECTOR_SHUFFLE node semantically equivalent to the shuffle node in input but with swapped operands. More...
 
SDValue getFPExtendOrRound (SDValue Op, const SDLoc &DL, EVT VT)
 Convert Op, which must be of float type, to the float type VT, by either extending or rounding (by truncation). More...
 
SDValue getAnyExtOrTrunc (SDValue Op, const SDLoc &DL, EVT VT)
 Convert Op, which must be of integer type, to the integer type VT, by either any-extending or truncating it. More...
 
SDValue getSExtOrTrunc (SDValue Op, const SDLoc &DL, EVT VT)
 Convert Op, which must be of integer type, to the integer type VT, by either sign-extending or truncating it. More...
 
SDValue getZExtOrTrunc (SDValue Op, const SDLoc &DL, EVT VT)
 Convert Op, which must be of integer type, to the integer type VT, by either zero-extending or truncating it. More...
 
SDValue getZeroExtendInReg (SDValue Op, const SDLoc &DL, EVT SrcTy)
 Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value. More...
 
SDValue getAnyExtendVectorInReg (SDValue Op, const SDLoc &DL, EVT VT)
 Return an operation which will any-extend the low lanes of the operand into the specified vector type. More...
 
SDValue getSignExtendVectorInReg (SDValue Op, const SDLoc &DL, EVT VT)
 Return an operation which will sign extend the low lanes of the operand into the specified vector type. More...
 
SDValue getZeroExtendVectorInReg (SDValue Op, const SDLoc &DL, EVT VT)
 Return an operation which will zero extend the low lanes of the operand into the specified vector type. More...
 
SDValue getBoolExtOrTrunc (SDValue Op, const SDLoc &SL, EVT VT, EVT OpVT)
 Convert Op, which must be of integer type, to the integer type VT, by using an extension appropriate for the target's BooleanContent for type OpVT or truncating it. More...
 
SDValue getNOT (const SDLoc &DL, SDValue Val, EVT VT)
 Create a bitwise NOT operation as (XOR Val, -1). More...
 
SDValue getLogicalNOT (const SDLoc &DL, SDValue Val, EVT VT)
 Create a logical NOT operation as (XOR Val, BooleanOne). More...
 
SDValue getCALLSEQ_START (SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
 Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside CALLSEQ_START..CALLSEQ_END sequence and OutSize specifies part of the frame set up prior to the sequence. More...
 
SDValue getCALLSEQ_END (SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
 Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd). More...
 
bool isUndef (unsigned Opcode, ArrayRef< SDValue > Ops)
 Return true if the result of this operation is always undefined. More...
 
SDValue getUNDEF (EVT VT)
 Return an UNDEF node. UNDEF does not have a useful SDLoc. More...
 
SDValue getGLOBAL_OFFSET_TABLE (EVT VT)
 Return a GLOBAL_OFFSET_TABLE node. This does not have a useful SDLoc. More...
 
SDValue getNode (unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
 Gets or creates the specified node. More...
 
SDValue getNode (unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDValue > Ops, const SDNodeFlags Flags=SDNodeFlags())
 
SDValue getNode (unsigned Opcode, const SDLoc &DL, ArrayRef< EVT > ResultTys, ArrayRef< SDValue > Ops)
 
SDValue getNode (unsigned Opcode, const SDLoc &DL, SDVTList VTs, ArrayRef< SDValue > Ops)
 
SDValue getNode (unsigned Opcode, const SDLoc &DL, EVT VT)
 Gets or creates the specified node. More...
 
SDValue getNode (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N, const SDNodeFlags Flags=SDNodeFlags())
 
SDValue getNode (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, SDValue N2, const SDNodeFlags Flags=SDNodeFlags())
 
SDValue getNode (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, SDValue N2, SDValue N3)
 
SDValue getNode (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, SDValue N2, SDValue N3, SDValue N4)
 
SDValue getNode (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, SDValue N2, SDValue N3, SDValue N4, SDValue N5)
 
SDValue getNode (unsigned Opcode, const SDLoc &DL, SDVTList VTs)
 
SDValue getNode (unsigned Opcode, const SDLoc &DL, SDVTList VTs, SDValue N)
 
SDValue getNode (unsigned Opcode, const SDLoc &DL, SDVTList VTs, SDValue N1, SDValue N2)
 
SDValue getNode (unsigned Opcode, const SDLoc &DL, SDVTList VTs, SDValue N1, SDValue N2, SDValue N3)
 
SDValue getNode (unsigned Opcode, const SDLoc &DL, SDVTList VTs, SDValue N1, SDValue N2, SDValue N3, SDValue N4)
 
SDValue getNode (unsigned Opcode, const SDLoc &DL, SDVTList VTs, SDValue N1, SDValue N2, SDValue N3, SDValue N4, SDValue N5)
 
SDValue getStackArgumentTokenFactor (SDValue Chain)
 Compute a TokenFactor to force all the incoming stack arguments to be loaded from the stack. More...
 
SDValue getMemcpy (SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
 
SDValue getMemmove (SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
 
SDValue getMemset (SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool isTailCall, MachinePointerInfo DstPtrInfo)
 
SDValue getSetCC (const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
 Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SDValue. More...
 
SDValue getSelect (const SDLoc &DL, EVT VT, SDValue Cond, SDValue LHS, SDValue RHS)
 Helper function to make it easier to build Select's if you just have operands and don't want to check for vector. More...
 
SDValue getSelectCC (const SDLoc &DL, SDValue LHS, SDValue RHS, SDValue True, SDValue False, ISD::CondCode Cond)
 Helper function to make it easier to build SelectCC's if you just have an ISD::CondCode instead of an SDValue. More...
 
SDValue getVAArg (EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue SV, unsigned Align)
 VAArg produces a result and token chain, and takes a pointer and a source value as input. More...
 
SDValue getAtomicCmpSwap (unsigned Opcode, const SDLoc &dl, EVT MemVT, SDVTList VTs, SDValue Chain, SDValue Ptr, SDValue Cmp, SDValue Swp, MachinePointerInfo PtrInfo, unsigned Alignment, AtomicOrdering SuccessOrdering, AtomicOrdering FailureOrdering, SyncScope::ID SSID)
 Gets a node for an atomic cmpxchg op. More...
 
SDValue getAtomicCmpSwap (unsigned Opcode, const SDLoc &dl, EVT MemVT, SDVTList VTs, SDValue Chain, SDValue Ptr, SDValue Cmp, SDValue Swp, MachineMemOperand *MMO)
 
SDValue getAtomic (unsigned Opcode, const SDLoc &dl, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Val, const Value *PtrVal, unsigned Alignment, AtomicOrdering Ordering, SyncScope::ID SSID)
 Gets a node for an atomic op, produces result (if relevant) and chain and takes 2 operands. More...
 
SDValue getAtomic (unsigned Opcode, const SDLoc &dl, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Val, MachineMemOperand *MMO)
 
SDValue getAtomic (unsigned Opcode, const SDLoc &dl, EVT MemVT, EVT VT, SDValue Chain, SDValue Ptr, MachineMemOperand *MMO)
 Gets a node for an atomic op, produces result and chain and takes 1 operand. More...
 
SDValue getAtomic (unsigned Opcode, const SDLoc &dl, EVT MemVT, SDVTList VTList, ArrayRef< SDValue > Ops, MachineMemOperand *MMO)
 Gets a node for an atomic op, produces result and chain and takes N operands. More...
 
SDValue getMemIntrinsicNode (unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, unsigned Align=0, bool Vol=false, bool ReadMem=true, bool WriteMem=true, unsigned Size=0)
 Creates a MemIntrinsicNode that may produce a result and takes a list of operands. More...
 
SDValue getMemIntrinsicNode (unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachineMemOperand *MMO)
 
SDValue getMergeValues (ArrayRef< SDValue > Ops, const SDLoc &dl)
 Create a MERGE_VALUES node from the given operands. More...
 
SDValue getLoad (EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
 Loads are not normal binary operators: their result type is not determined by their operands, and they produce a value AND a token chain. More...
 
SDValue getLoad (EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachineMemOperand *MMO)
 
SDValue getExtLoad (ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
 
SDValue getExtLoad (ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, EVT MemVT, MachineMemOperand *MMO)
 
SDValue getIndexedLoad (SDValue OrigLoad, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
 
SDValue getLoad (ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset, MachinePointerInfo PtrInfo, EVT MemVT, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
 
SDValue getLoad (ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset, EVT MemVT, MachineMemOperand *MMO)
 
SDValue getStore (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
 Helper function to build ISD::STORE nodes. More...
 
SDValue getStore (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachineMemOperand *MMO)
 
SDValue getTruncStore (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT TVT, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
 
SDValue getTruncStore (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, EVT TVT, MachineMemOperand *MMO)
 
SDValue getIndexedStore (SDValue OrigStoe, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
 
SDValue getMemBasePlusOffset (SDValue Base, unsigned Offset, const SDLoc &DL)
 Returns sum of the base pointer and offset. More...
 
SDValue getMaskedLoad (EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Mask, SDValue Src0, EVT MemVT, MachineMemOperand *MMO, ISD::LoadExtType, bool IsExpanding=false)
 
SDValue getMaskedStore (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, SDValue Mask, EVT MemVT, MachineMemOperand *MMO, bool IsTruncating=false, bool IsCompressing=false)
 
SDValue getMaskedGather (SDVTList VTs, EVT VT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO)
 
SDValue getMaskedScatter (SDVTList VTs, EVT VT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO)
 
template<class TargetMemSDNode >
SDValue getTargetMemSDNode (SDVTList VTs, ArrayRef< SDValue > Ops, const SDLoc &dl, EVT MemVT, MachineMemOperand *MMO)
 Return (create a new or find existing) a target-specific node. More...
 
SDValue getSrcValue (const Value *v)
 Construct a node to track a Value* through the backend. More...
 
SDValue getMDNode (const MDNode *MD)
 Return an MDNodeSDNode which holds an MDNode. More...
 
SDValue getBitcast (EVT VT, SDValue V)
 Return a bitcast using the SDLoc of the value operand, and casting to the provided type. More...
 
SDValue getAddrSpaceCast (const SDLoc &dl, EVT VT, SDValue Ptr, unsigned SrcAS, unsigned DestAS)
 Return an AddrSpaceCastSDNode. More...
 
SDValue getShiftAmountOperand (EVT LHSTy, SDValue Op)
 Return the specified value casted to the target's desired shift amount type. More...
 
SDValue expandVAArg (SDNode *Node)
 Expand the specified ISD::VAARG node as the Legalize pass would. More...
 
SDValue expandVACopy (SDNode *Node)
 Expand the specified ISD::VACOPY node as the Legalize pass would. More...
 
SDNodeUpdateNodeOperands (SDNode *N, SDValue Op)
 Mutate the specified node in-place to have the specified operands. More...
 
SDNodeUpdateNodeOperands (SDNode *N, SDValue Op1, SDValue Op2)
 
SDNodeUpdateNodeOperands (SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3)
 
SDNodeUpdateNodeOperands (SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3, SDValue Op4)
 
SDNodeUpdateNodeOperands (SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3, SDValue Op4, SDValue Op5)
 
SDNodeUpdateNodeOperands (SDNode *N, ArrayRef< SDValue > Ops)
 
SDNodeSelectNodeTo (SDNode *N, unsigned TargetOpc, EVT VT)
 These are used for target selectors to mutate the specified node to have the specified return type, Target opcode, and operands. More...
 
SDNodeSelectNodeTo (SDNode *N, unsigned TargetOpc, EVT VT, SDValue Op1)
 
SDNodeSelectNodeTo (SDNode *N, unsigned TargetOpc, EVT VT, SDValue Op1, SDValue Op2)
 
SDNodeSelectNodeTo (SDNode *N, unsigned TargetOpc, EVT VT, SDValue Op1, SDValue Op2, SDValue Op3)
 
SDNodeSelectNodeTo (SDNode *N, unsigned TargetOpc, EVT VT, ArrayRef< SDValue > Ops)
 
SDNodeSelectNodeTo (SDNode *N, unsigned TargetOpc, EVT VT1, EVT VT2)
 
SDNodeSelectNodeTo (SDNode *N, unsigned TargetOpc, EVT VT1, EVT VT2, ArrayRef< SDValue > Ops)
 
SDNodeSelectNodeTo (SDNode *N, unsigned TargetOpc, EVT VT1, EVT VT2, EVT VT3, ArrayRef< SDValue > Ops)
 
SDNodeSelectNodeTo (SDNode *N, unsigned TargetOpc, EVT VT1, EVT VT2, SDValue Op1)
 
SDNodeSelectNodeTo (SDNode *N, unsigned TargetOpc, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2)
 
SDNodeSelectNodeTo (SDNode *N, unsigned TargetOpc, SDVTList VTs, ArrayRef< SDValue > Ops)
 
SDNodeMorphNodeTo (SDNode *N, unsigned Opc, SDVTList VTs, ArrayRef< SDValue > Ops)
 This mutates the specified node to have the specified return type, opcode, and operands. More...
 
SDNodemutateStrictFPToFP (SDNode *Node)
 Mutate the specified strict FP node to its non-strict equivalent, unlinking the node from its chain and dropping the metadata arguments. More...
 
MachineSDNodegetMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT)
 These are used for target selectors to create a new node with specified return type(s), MachineInstr opcode, and operands. More...
 
MachineSDNodegetMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT, SDValue Op1)
 
MachineSDNodegetMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT, SDValue Op1, SDValue Op2)
 
MachineSDNodegetMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT, SDValue Op1, SDValue Op2, SDValue Op3)
 
MachineSDNodegetMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT, ArrayRef< SDValue > Ops)
 
MachineSDNodegetMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2)
 
MachineSDNodegetMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3)
 
MachineSDNodegetMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT1, EVT VT2, ArrayRef< SDValue > Ops)
 
MachineSDNodegetMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2)
 
MachineSDNodegetMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3)
 
MachineSDNodegetMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT1, EVT VT2, EVT VT3, ArrayRef< SDValue > Ops)
 
MachineSDNodegetMachineNode (unsigned Opcode, const SDLoc &dl, ArrayRef< EVT > ResultTys, ArrayRef< SDValue > Ops)
 
MachineSDNodegetMachineNode (unsigned Opcode, const SDLoc &dl, SDVTList VTs, ArrayRef< SDValue > Ops)
 
SDValue getTargetExtractSubreg (int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand)
 A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG nodes. More...
 
SDValue getTargetInsertSubreg (int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand, SDValue Subreg)
 A convenience function for creating TargetInstrInfo::INSERT_SUBREG nodes. More...
 
SDNodegetNodeIfExists (unsigned Opcode, SDVTList VTs, ArrayRef< SDValue > Ops, const SDNodeFlags Flags=SDNodeFlags())
 Get the specified node if it's already available, or else return NULL. More...
 
SDDbgValuegetDbgValue (DIVariable *Var, DIExpression *Expr, SDNode *N, unsigned R, bool IsIndirect, const DebugLoc &DL, unsigned O)
 Creates a SDDbgValue node. More...
 
SDDbgValuegetConstantDbgValue (DIVariable *Var, DIExpression *Expr, const Value *C, const DebugLoc &DL, unsigned O)
 Creates a constant SDDbgValue node. More...
 
SDDbgValuegetFrameIndexDbgValue (DIVariable *Var, DIExpression *Expr, unsigned FI, const DebugLoc &DL, unsigned O)
 Creates a FrameIndex SDDbgValue node. More...
 
void transferDbgValues (SDValue From, SDValue To, unsigned OffsetInBits=0, unsigned SizeInBits=0, bool InvalidateDbg=true)
 Transfer debug values from one node to another, while optionally generating fragment expressions for split-up values. More...
 
void RemoveDeadNode (SDNode *N)
 Remove the specified node from the system. More...
 
void RemoveDeadNodes (SmallVectorImpl< SDNode *> &DeadNodes)
 This method deletes the unreachable nodes in the given list, and any nodes that become unreachable as a result. More...
 
void ReplaceAllUsesWith (SDValue From, SDValue Op)
 Modify anything using 'From' to use 'To' instead. More...
 
void ReplaceAllUsesWith (SDNode *From, SDNode *To)
 ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. More...
 
void ReplaceAllUsesWith (SDNode *From, const SDValue *To)
 ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. More...
 
void ReplaceAllUsesOfValueWith (SDValue From, SDValue To)
 Replace any uses of From with To, leaving uses of other values produced by From.Val alone. More...
 
void ReplaceAllUsesOfValuesWith (const SDValue *From, const SDValue *To, unsigned Num)
 Like ReplaceAllUsesOfValueWith, but for multiple values at once. More...
 
SDValue makeEquivalentMemoryOrdering (LoadSDNode *Old, SDValue New)
 If an existing load has uses of its chain, create a token factor node with that chain and the new memory node's chain and update users of the old chain to the token factor. More...
 
unsigned AssignTopologicalOrder ()
 Topological-sort the AllNodes list and a assign a unique node id for each node in the DAG based on their topological order. More...
 
void RepositionNode (allnodes_iterator Position, SDNode *N)
 Move node N in the AllNodes list to be immediately before the given iterator Position. More...
 
void AddDbgValue (SDDbgValue *DB, SDNode *SD, bool isParameter)
 Add a dbg_value SDNode. More...
 
ArrayRef< SDDbgValue * > GetDbgValues (const SDNode *SD)
 Get the debug values which reference the given SDNode. More...
 
bool hasDebugValues () const
 Return true if there are any SDDbgValue nodes associated with this SelectionDAG. More...
 
SDDbgInfo::DbgIterator DbgBegin ()
 
SDDbgInfo::DbgIterator DbgEnd ()
 
SDDbgInfo::DbgIterator ByvalParmDbgBegin ()
 
SDDbgInfo::DbgIterator ByvalParmDbgEnd ()
 
void salvageDebugInfo (SDNode &N)
 To be invoked on an SDNode that is slated to be erased. More...
 
void dump () const
 
SDValue CreateStackTemporary (EVT VT, unsigned minAlign=1)
 Create a stack temporary, suitable for holding the specified value type. More...
 
SDValue CreateStackTemporary (EVT VT1, EVT VT2)
 Create a stack temporary suitable for holding either of the specified value types. More...
 
SDValue FoldSymbolOffset (unsigned Opcode, EVT VT, const GlobalAddressSDNode *GA, const SDNode *N2)
 
SDValue FoldConstantArithmetic (unsigned Opcode, const SDLoc &DL, EVT VT, SDNode *Cst1, SDNode *Cst2)
 
SDValue FoldConstantArithmetic (unsigned Opcode, const SDLoc &DL, EVT VT, const ConstantSDNode *Cst1, const ConstantSDNode *Cst2)
 
SDValue FoldConstantVectorArithmetic (unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDValue > Ops, const SDNodeFlags Flags=SDNodeFlags())
 
SDValue FoldSetCC (EVT VT, SDValue N1, SDValue N2, ISD::CondCode Cond, const SDLoc &dl)
 Constant fold a setcc to true or false. More...
 
SDValue GetDemandedBits (SDValue V, const APInt &Mask)
 See if the specified operand can be simplified with the knowledge that only the bits specified by Mask are used. More...
 
bool SignBitIsZero (SDValue Op, unsigned Depth=0) const
 Return true if the sign bit of Op is known to be zero. More...
 
bool MaskedValueIsZero (SDValue Op, const APInt &Mask, unsigned Depth=0) const
 Return true if 'Op & Mask' is known to be zero. More...
 
void computeKnownBits (SDValue Op, KnownBits &Known, unsigned Depth=0) const
 Determine which bits of Op are known to be either zero or one and return them in Known. More...
 
void computeKnownBits (SDValue Op, KnownBits &Known, const APInt &DemandedElts, unsigned Depth=0) const
 Determine which bits of Op are known to be either zero or one and return them in Known. More...
 
OverflowKind computeOverflowKind (SDValue N0, SDValue N1) const
 Determine if the result of the addition of 2 node can overflow. More...
 
bool isKnownToBeAPowerOfTwo (SDValue Val) const
 Test if the given value is known to have exactly one bit set. More...
 
unsigned ComputeNumSignBits (SDValue Op, unsigned Depth=0) const
 Return the number of times the sign bit of the register is replicated into the other bits. More...
 
unsigned ComputeNumSignBits (SDValue Op, const APInt &DemandedElts, unsigned Depth=0) const
 Return the number of times the sign bit of the register is replicated into the other bits. More...
 
bool isBaseWithConstantOffset (SDValue Op) const
 Return true if the specified operand is an ISD::ADD with a ConstantSDNode on the right-hand side, or if it is an ISD::OR with a ConstantSDNode that is guaranteed to have the same semantics as an ADD. More...
 
bool isKnownNeverNaN (SDValue Op) const
 Test whether the given SDValue is known to never be NaN. More...
 
bool isKnownNeverZero (SDValue Op) const
 Test whether the given SDValue is known to never be positive or negative zero. More...
 
bool isEqualTo (SDValue A, SDValue B) const
 Test whether two SDValues are known to compare equal. More...
 
bool haveNoCommonBitsSet (SDValue A, SDValue B) const
 Return true if A and B have no common bits set. More...
 
SDValue UnrollVectorOp (SDNode *N, unsigned ResNE=0)
 Utility function used by legalize and lowering to "unroll" a vector operation by splitting out the scalars and operating on each element individually. More...
 
bool areNonVolatileConsecutiveLoads (LoadSDNode *LD, LoadSDNode *Base, unsigned Bytes, int Dist) const
 Return true if loads are next to each other and can be merged. More...
 
unsigned InferPtrAlignment (SDValue Ptr) const
 Infer alignment of a load / store address. More...
 
std::pair< EVT, EVTGetSplitDestVTs (const EVT &VT) const
 Compute the VTs needed for the low/hi parts of a type which is split (or expanded) into two not necessarily identical pieces. More...
 
std::pair< SDValue, SDValueSplitVector (const SDValue &N, const SDLoc &DL, const EVT &LoVT, const EVT &HiVT)
 Split the vector with EXTRACT_SUBVECTOR using the provides VTs and return the low/high part. More...
 
std::pair< SDValue, SDValueSplitVector (const SDValue &N, const SDLoc &DL)
 Split the vector with EXTRACT_SUBVECTOR and return the low/high part. More...
 
std::pair< SDValue, SDValueSplitVectorOperand (const SDNode *N, unsigned OpNo)
 Split the node's operand with EXTRACT_SUBVECTOR and return the low/high part. More...
 
void ExtractVectorElements (SDValue Op, SmallVectorImpl< SDValue > &Args, unsigned Start=0, unsigned Count=0)
 Append the extracted elements from Start to Count out of the vector Op in Args. More...
 
unsigned getEVTAlignment (EVT MemoryVT) const
 Compute the default alignment value for the given type. More...
 
SDNodeisConstantIntBuildVectorOrConstantInt (SDValue N)
 Test whether the given value is a constant int or similar node. More...
 
SDNodeisConstantFPBuildVectorOrConstantFP (SDValue N)
 Test whether the given value is a constant FP or similar node. More...
 
bool isConstantValueOfAnyType (SDValue N)
 
SDValue getConstant (uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
 Create a ConstantSDNode wrapping a constant value. More...
 
SDValue getConstant (const APInt &Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
 
SDValue getAllOnesConstant (const SDLoc &DL, EVT VT, bool IsTarget=false, bool IsOpaque=false)
 
SDValue getConstant (const ConstantInt &Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
 
SDValue getIntPtrConstant (uint64_t Val, const SDLoc &DL, bool isTarget=false)
 
SDValue getTargetConstant (uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
 
SDValue getTargetConstant (const APInt &Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
 
SDValue getTargetConstant (const ConstantInt &Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
 
SDValue getConstantFP (double Val, const SDLoc &DL, EVT VT, bool isTarget=false)
 Create a ConstantFPSDNode wrapping a constant value. More...
 
SDValue getConstantFP (const APFloat &Val, const SDLoc &DL, EVT VT, bool isTarget=false)
 
SDValue getConstantFP (const ConstantFP &CF, const SDLoc &DL, EVT VT, bool isTarget=false)
 
SDValue getTargetConstantFP (double Val, const SDLoc &DL, EVT VT)
 
SDValue getTargetConstantFP (const APFloat &Val, const SDLoc &DL, EVT VT)
 
SDValue getTargetConstantFP (const ConstantFP &Val, const SDLoc &DL, EVT VT)
 

Static Public Member Functions

static const fltSemanticsEVTToAPFloatSemantics (EVT VT)
 Returns an APFloat semantics tag appropriate for the given type. More...
 

Public Attributes

bool NewNodesMustHaveLegalTypes = false
 When true, additional steps are taken to ensure that getConstant() and similar functions return DAG nodes that have legal types. More...
 
std::map< const SDNode *, std::string > NodeGraphAttrs
 

Friends

struct DAGUpdateListener
 DAGUpdateListener is a friend so it can manipulate the listener stack. More...
 

Detailed Description

This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representation suitable for instruction selection.

This DAG is constructed as the first step of instruction selection in order to allow implementation of machine specific optimizations and code simplifications.

The representation used by the SelectionDAG is a target-independent representation, which has some similarities to the GCC RTL representation, but is significantly more simple, powerful, and is a graph form instead of a linear form.

Definition at line 209 of file SelectionDAG.h.

Member Typedef Documentation

◆ allnodes_const_iterator

Definition at line 421 of file SelectionDAG.h.

◆ allnodes_iterator

Definition at line 426 of file SelectionDAG.h.

Member Enumeration Documentation

◆ OverflowKind

Used to represent the possible overflow behavior of an operation.

Never: the operation cannot overflow. Always: the operation will always overflow. Sometime: the operation may or may not overflow.

Enumerator
OFK_Never 
OFK_Sometime 
OFK_Always 

Definition at line 1369 of file SelectionDAG.h.

Constructor & Destructor Documentation

◆ SelectionDAG() [1/2]

SelectionDAG::SelectionDAG ( const TargetMachine TM,
CodeGenOpt::Level  OL 
)
explicit

Definition at line 896 of file SelectionDAG.cpp.

References Other.

◆ SelectionDAG() [2/2]

llvm::SelectionDAG::SelectionDAG ( const SelectionDAG )
delete

◆ ~SelectionDAG()

SelectionDAG::~SelectionDAG ( )

Member Function Documentation

◆ AddDbgValue()

void SelectionDAG::AddDbgValue ( SDDbgValue DB,
SDNode SD,
bool  isParameter 
)

Add a dbg_value SDNode.

AddDbgValue - Add a dbg_value SDNode.

If SD is non-null that means the value is produced by SD.

Definition at line 7526 of file SelectionDAG.cpp.

References assert(), llvm::SDNode::getHasDebugValue(), and llvm::SDNode::setHasDebugValue().

Referenced by getUnderlyingArgReg(), llvm::SelectionDAGBuilder::resolveDanglingDebugInfo(), salvageDebugInfo(), and transferDbgValues().

◆ allnodes() [1/2]

iterator_range<allnodes_iterator> llvm::SelectionDAG::allnodes ( )
inline

◆ allnodes() [2/2]

iterator_range<allnodes_const_iterator> llvm::SelectionDAG::allnodes ( ) const
inline

Definition at line 438 of file SelectionDAG.h.

References llvm::make_range().

◆ allnodes_begin() [1/2]

allnodes_const_iterator llvm::SelectionDAG::allnodes_begin ( ) const
inline

◆ allnodes_begin() [2/2]

allnodes_iterator llvm::SelectionDAG::allnodes_begin ( )
inline

Definition at line 428 of file SelectionDAG.h.

◆ allnodes_end() [1/2]

allnodes_const_iterator llvm::SelectionDAG::allnodes_end ( ) const
inline

◆ allnodes_end() [2/2]

allnodes_iterator llvm::SelectionDAG::allnodes_end ( )
inline

Definition at line 429 of file SelectionDAG.h.

◆ allnodes_size()

ilist<SDNode>::size_type llvm::SelectionDAG::allnodes_size ( ) const
inline

◆ areNonVolatileConsecutiveLoads()

bool SelectionDAG::areNonVolatileConsecutiveLoads ( LoadSDNode LD,
LoadSDNode Base,
unsigned  Bytes,
int  Dist 
) const

Return true if loads are next to each other and can be merged.

Check that both are nonvolatile and if LD is loading 'Bytes' bytes from a location that is 'Dist' units away from the location that the 'Base' load is loading from.

Definition at line 7888 of file SelectionDAG.cpp.

References llvm::MemSDNode::getChain(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDNode::getValueType(), llvm::LSBaseSDNode::isIndexed(), llvm::MemSDNode::isVolatile(), and llvm::BaseIndexOffset::match().

Referenced by EltsFromConsecutiveLoads(), and getBuildPairElt().

◆ AssignTopologicalOrder()

unsigned SelectionDAG::AssignTopologicalOrder ( )

Topological-sort the AllNodes list and a assign a unique node id for each node in the DAG based on their topological order.

AssignTopologicalOrder - Assign a unique node id for each node in the DAG based on their topological order.

Returns the number of nodes.

It returns the maximum id and a vector of the SDNodes* in assigned order by reference.

Definition at line 7437 of file SelectionDAG.cpp.

References allnodes(), allnodes_begin(), allnodes_end(), allnodes_size(), assert(), llvm::checkForCycles(), llvm::dbgs(), llvm::SDNode::dumprFull(), E, llvm::ISD::EntryToken, llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::SDNode::getNodeId(), llvm::SDNode::getNumOperands(), I, llvm_unreachable, P, llvm::SDNode::setNodeId(), llvm::SDNode::use_begin(), and llvm::SDNode::use_end().

Referenced by reportFastISelFailure().

◆ ByvalParmDbgBegin()

SDDbgInfo::DbgIterator llvm::SelectionDAG::ByvalParmDbgBegin ( )
inline

◆ ByvalParmDbgEnd()

SDDbgInfo::DbgIterator llvm::SelectionDAG::ByvalParmDbgEnd ( )
inline

◆ clear()

void SelectionDAG::clear ( )

Clear state and free memory necessary to make this SelectionDAG ready to process a new block.

Definition at line 972 of file SelectionDAG.cpp.

References llvm::SDDbgInfo::clear(), getEntryNode(), and llvm::BumpPtrAllocatorImpl< AllocatorT, SlabSize, SizeThreshold >::Reset().

Referenced by reportFastISelFailure().

◆ clearGraphAttrs()

void SelectionDAG::clearGraphAttrs ( )

Clear all previously defined node graph attributes.

clearGraphAttrs - Clear all previously defined node graph attributes.

Intended to be used from a debugging tool (eg. gdb).

Definition at line 172 of file SelectionDAGPrinter.cpp.

References llvm::errs().

◆ Combine()

void SelectionDAG::Combine ( CombineLevel  Level,
AliasAnalysis AA,
CodeGenOpt::Level  OptLevel 
)

This iterates over the nodes in the SelectionDAG, folding certain types of nodes together, or eliminating superfluous nodes.

This is the entry point for the file.

The Level argument controls whether Combine is allowed to produce nodes and types that are illegal on the target.

This is the main entry point to this class.

Definition at line 17542 of file DAGCombiner.cpp.

Referenced by reportFastISelFailure().

◆ computeKnownBits() [1/2]

void SelectionDAG::computeKnownBits ( SDValue  Op,
KnownBits Known,
unsigned  Depth = 0 
) const

Determine which bits of Op are known to be either zero or one and return them in Known.

For vectors, the known bits are those that are shared by every vector element. Targets can implement the computeKnownBitsForTargetNode method in the TargetLowering class to allow target nodes to be understood.

For vectors, the known bits are those that are shared by every vector element.

Definition at line 2098 of file SelectionDAG.cpp.

References llvm::APInt::getAllOnesValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), and llvm::EVT::isVector().

Referenced by calculateByteProvider(), llvm::SelectionDAGISel::CheckOrMask(), combineSubToSubus(), combineVectorSignBitsTruncation(), computeKnownBits(), llvm::SparcTargetLowering::computeKnownBitsForTargetNode(), llvm::LanaiTargetLowering::computeKnownBitsForTargetNode(), llvm::AMDGPUTargetLowering::computeKnownBitsForTargetNode(), llvm::AArch64TargetLowering::computeKnownBitsForTargetNode(), llvm::ARMTargetLowering::computeKnownBitsForTargetNode(), llvm::X86TargetLowering::computeKnownBitsForTargetNode(), ComputeNumSignBits(), computeOverflowKind(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), foldMaskAndShiftToScale(), generateEquivalentSub(), getAbsolute(), haveNoCommonBitsSet(), isBitfieldPositioningOp(), isKnownToBeAPowerOfTwo(), isTruncateOf(), isWordAligned(), LowerAndToBT(), LowerTruncateVecI1(), MaskedValueIsZero(), llvm::AMDGPUTargetLowering::numBitsUnsigned(), llvm::ARMTargetLowering::PerformCMOVCombine(), llvm::ARMTargetLowering::PerformCMOVToBFICombine(), llvm::AMDGPUTargetLowering::performShlCombine(), reportFastISelFailure(), llvm::PPCTargetLowering::SelectAddressRegImm(), llvm::PPCTargetLowering::SelectAddressRegReg(), llvm::TargetLowering::SimplifyDemandedBits(), tryBitfieldInsertOpFromOr(), and tryBitfieldInsertOpFromOrAndImm().

◆ computeKnownBits() [2/2]

void SelectionDAG::computeKnownBits ( SDValue  Op,
KnownBits Known,
const APInt DemandedElts,
unsigned  Depth = 0 
) const

Determine which bits of Op are known to be either zero or one and return them in Known.

The DemandedElts argument allows us to only collect the known bits that are shared by the requested vector elements. Targets can implement the computeKnownBitsForTargetNode method in the TargetLowering class to allow target nodes to be understood.

The DemandedElts argument allows us to only collect the known bits that are shared by the requested vector elements.

Definition at line 2110 of file SelectionDAG.cpp.

References llvm::ISD::ABS, llvm::ISD::ADD, llvm::ISD::ADDC, llvm::ISD::ADDCARRY, llvm::ISD::ADDE, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::APInt::ashrInPlace(), assert(), llvm::ISD::AssertZext, llvm::ISD::BITCAST, llvm::ISD::BITREVERSE, llvm::ISD::BSWAP, llvm::ISD::BUILD_VECTOR, llvm::ISD::BUILTIN_OP_END, llvm::APInt::byteSwap(), C, llvm::APInt::clearAllBits(), llvm::APInt::clearSignBit(), computeKnownBits(), llvm::TargetLowering::computeKnownBitsForFrameIndex(), llvm::TargetLowering::computeKnownBitsForTargetNode(), llvm::computeKnownBitsFromRangeMetadata(), llvm::ISD::CONCAT_VECTORS, llvm::countLeadingZeros(), llvm::KnownBits::countMaxLeadingZeros(), llvm::KnownBits::countMaxPopulation(), llvm::KnownBits::countMaxTrailingZeros(), llvm::KnownBits::countMinLeadingOnes(), llvm::KnownBits::countMinLeadingZeros(), llvm::KnownBits::countMinTrailingZeros(), llvm::ISD::CTLZ, llvm::ISD::CTLZ_ZERO_UNDEF, llvm::ISD::CTPOP, llvm::ISD::CTTZ, llvm::ISD::CTTZ_ZERO_UNDEF, llvm::dyn_cast(), llvm::ISD::EXTRACT_ELEMENT, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::APInt::extractBits(), llvm::ISD::FGETSIGN, llvm::ISD::FrameIndex, llvm::APInt::getAllOnesValue(), llvm::ConstantSDNode::getAPIntValue(), llvm::APInt::getBitsSet(), llvm::APInt::getBitWidth(), llvm::TargetLoweringBase::getBooleanContents(), llvm::APInt::getBoolValue(), llvm::SDValue::getConstantOperandVal(), getDataLayout(), llvm::LoadSDNode::getExtensionType(), llvm::APInt::getHiBits(), llvm::APInt::getHighBitsSet(), llvm::APInt::getLowBitsSet(), llvm::ShuffleVectorSDNode::getMask(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SDValue::getNumOperands(), llvm::APInt::getOneBitSet(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::MemSDNode::getRanges(), llvm::SDValue::getResNo(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getScalarValueSizeInBits(), llvm::APInt::getSignMask(), llvm::EVT::getSizeInBits(), getValidShiftAmountConstant(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::ConstantSDNode::getZExtValue(), llvm::KnownBits::hasConflict(), if(), llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::INSERT_VECTOR_ELT, llvm::APInt::intersects(), llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::isConstOrConstSplat(), llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::DataLayout::isLittleEndian(), llvm::KnownBits::isNonNegative(), llvm::APInt::isPowerOf2(), llvm::KnownBits::isUnknown(), llvm::EVT::isVector(), llvm::ISD::isZEXTLoad(), llvm::ARM_MB::LD, LLVM_FALLTHROUGH, llvm::ISD::LOAD, llvm::Log2_32(), llvm::APInt::lshr(), llvm::APInt::lshrInPlace(), llvm::max(), llvm::ISD::MUL, llvm::ISD::NON_EXTLOAD, llvm::KnownBits::One, llvm::ISD::OR, RA, llvm::KnownBits::resetAll(), llvm::APInt::reverseBits(), llvm::ISD::SADDO, llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::APInt::setAllBits(), llvm::APInt::setBit(), llvm::APInt::setBits(), llvm::APInt::setBitsFrom(), llvm::ISD::SETCC, llvm::APInt::setHighBits(), llvm::APInt::setLowBits(), llvm::KnownBits::sext(), llvm::ISD::SHL, llvm::APInt::shl(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::SMULO, llvm::ISD::SRA, llvm::ISD::SREM, llvm::ISD::SRL, llvm::ISD::SSUBO, llvm::ISD::SUB, llvm::ISD::SUBC, llvm::ISD::TargetFrameIndex, llvm::KnownBits::trunc(), llvm::APInt::trunc(), llvm::ISD::TRUNCATE, llvm::ISD::UADDO, llvm::ISD::UDIV, llvm::APInt::ule(), llvm::APInt::ult(), llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::ISD::UMULO, llvm::ISD::UREM, llvm::ISD::USUBO, llvm::ISD::VECTOR_SHUFFLE, llvm::ISD::VSELECT, llvm::ISD::XOR, llvm::KnownBits::Zero, llvm::ISD::ZERO_EXTEND, llvm::ISD::ZERO_EXTEND_VECTOR_INREG, llvm::TargetLoweringBase::ZeroOrOneBooleanContent, llvm::KnownBits::zext(), llvm::APInt::zext(), and llvm::APInt::zextOrTrunc().

◆ ComputeNumSignBits() [1/2]

unsigned SelectionDAG::ComputeNumSignBits ( SDValue  Op,
unsigned  Depth = 0 
) const

Return the number of times the sign bit of the register is replicated into the other bits.

We know that at least 1 bit is always equal to the sign bit (itself), but other cases can give us information. For example, immediately after an "SRA X, 2", we know that the top 3 bits are all equal to each other, so we return 3. Targets can implement the ComputeNumSignBitsForTarget method in the TargetLowering class to allow target nodes to be understood.

Definition at line 2990 of file SelectionDAG.cpp.

References llvm::APInt::getAllOnesValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), and llvm::EVT::isVector().

Referenced by calculateByteProvider(), canReduceVMulWidth(), combineAndMaskToShift(), combineBitcastvxi1(), combineHorizontalPredicateResult(), combineLogicBlendIntoPBLENDV(), combineSIntToFP(), combineVectorSignBitsTruncation(), combineVSelectWithAllOnesOrZeros(), ComputeNumSignBits(), llvm::AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(), llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(), llvm::TargetLowering::expandMUL_LOHI(), ExtendUsesToFormExtLoad(), generateEquivalentSub(), getAbsolute(), getAsCarry(), getFauxShuffleMask(), isADDADDMUL(), isS16(), isTruncateOf(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), LowerMUL(), llvm::AMDGPUTargetLowering::LowerSDIVREM(), LowerTruncateVecI1(), matchVectorShuffleWithPACK(), llvm::AMDGPUTargetLowering::numBitsSigned(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), and reportFastISelFailure().

◆ ComputeNumSignBits() [2/2]

unsigned SelectionDAG::ComputeNumSignBits ( SDValue  Op,
const APInt DemandedElts,
unsigned  Depth = 0 
) const

Return the number of times the sign bit of the register is replicated into the other bits.

We know that at least 1 bit is always equal to the sign bit (itself), but other cases can give us information. For example, immediately after an "SRA X, 2", we know that the top 3 bits are all equal to each other, so we return 3. The DemandedElts argument allows us to only collect the minimum sign bits of the requested vector elements. Targets can implement the ComputeNumSignBitsForTarget method in the TargetLowering class to allow target nodes to be understood.

Definition at line 2998 of file SelectionDAG.cpp.

References llvm::ISD::ADD, llvm::ISD::ADDC, llvm::ISD::AND, assert(), llvm::ISD::AssertSext, llvm::ISD::AssertZext, llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::ISD::BUILTIN_OP_END, C, llvm::APInt::clearBit(), computeKnownBits(), ComputeNumSignBits(), llvm::TargetLowering::ComputeNumSignBitsForTargetNode(), llvm::ISD::CONCAT_VECTORS, llvm::APInt::countLeadingZeros(), llvm::dyn_cast(), llvm::ISD::EXTRACT_ELEMENT, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::APInt::getAllOnesValue(), llvm::ConstantSDNode::getAPIntValue(), llvm::APInt::getBitWidth(), llvm::TargetLoweringBase::getBooleanContents(), llvm::SDValue::getConstantOperandVal(), llvm::ShuffleVectorSDNode::getMask(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDValue::getNumOperands(), llvm::APInt::getNumSignBits(), llvm::APInt::getOneBitSet(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getResNo(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getScalarValueSizeInBits(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::ConstantSDNode::getZExtValue(), llvm::APInt::getZExtValue(), llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::isConstOrConstSplat(), isConstOrDemandedConstSplat(), llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::KnownBits::isNegative(), llvm::KnownBits::isNonNegative(), llvm::EVT::isVector(), llvm::ARM_MB::LD, llvm::APInt::lshr(), llvm::BitmaskEnumDetail::Mask(), llvm::max(), llvm::KnownBits::One, llvm::ISD::OR, llvm::ISD::ROTL, llvm::ISD::ROTR, llvm::ISD::SADDO, llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::APInt::setBit(), llvm::ISD::SETCC, llvm::ISD::SEXTLOAD, llvm::ISD::SHL, llvm::APInt::shl(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SIGN_EXTEND_VECTOR_INREG, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::SMULO, llvm::ISD::SRA, llvm::ISD::SSUBO, llvm::ISD::SUB, llvm::APInt::trunc(), llvm::ISD::TRUNCATE, llvm::ISD::UADDO, llvm::APInt::uge(), llvm::APInt::ule(), llvm::APInt::ult(), llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::ISD::UMULO, llvm::ISD::USUBO, llvm::ISD::VECTOR_SHUFFLE, llvm::ISD::VSELECT, llvm::ISD::XOR, llvm::KnownBits::Zero, llvm::TargetLoweringBase::ZeroOrNegativeOneBooleanContent, llvm::APInt::zext(), and llvm::ISD::ZEXTLOAD.

◆ computeOverflowKind()

SelectionDAG::OverflowKind SelectionDAG::computeOverflowKind ( SDValue  N0,
SDValue  N1 
) const

Determine if the result of the addition of 2 node can overflow.

Definition at line 2914 of file SelectionDAG.cpp.

References computeKnownBits(), llvm::APInt::getBoolValue(), llvm::SDValue::getOpcode(), llvm::SDValue::getResNo(), llvm::isNullConstant(), OFK_Never, OFK_Sometime, llvm::ISD::UMUL_LOHI, and llvm::KnownBits::Zero.

Referenced by getAsCarry().

◆ CreateStackTemporary() [1/2]

SDValue SelectionDAG::CreateStackTemporary ( EVT  VT,
unsigned  minAlign = 1 
)

◆ CreateStackTemporary() [2/2]

SDValue SelectionDAG::CreateStackTemporary ( EVT  VT1,
EVT  VT2 
)

◆ DbgBegin()

SDDbgInfo::DbgIterator llvm::SelectionDAG::DbgBegin ( )
inline

Definition at line 1288 of file SelectionDAG.h.

References llvm::SDDbgInfo::DbgBegin().

Referenced by llvm::ScheduleDAGSDNodes::EmitSchedule().

◆ DbgEnd()

SDDbgInfo::DbgIterator llvm::SelectionDAG::DbgEnd ( )
inline

Definition at line 1289 of file SelectionDAG.h.

References llvm::SDDbgInfo::DbgEnd().

Referenced by llvm::ScheduleDAGSDNodes::EmitSchedule().

◆ DeleteNode()

void SelectionDAG::DeleteNode ( SDNode N)

◆ dump()

LLVM_DUMP_METHOD void SelectionDAG::dump ( ) const

◆ EVTToAPFloatSemantics()

static const fltSemantics& llvm::SelectionDAG::EVTToAPFloatSemantics ( EVT  VT)
inlinestatic

◆ expandVAArg()

SDValue SelectionDAG::expandVAArg ( SDNode Node)

◆ expandVACopy()

SDValue SelectionDAG::expandVACopy ( SDNode Node)

◆ ExtractVectorElements()

void SelectionDAG::ExtractVectorElements ( SDValue  Op,
SmallVectorImpl< SDValue > &  Args,
unsigned  Start = 0,
unsigned  Count = 0 
)

◆ FoldConstantArithmetic() [1/2]

SDValue SelectionDAG::FoldConstantArithmetic ( unsigned  Opcode,
const SDLoc DL,
EVT  VT,
SDNode Cst1,
SDNode Cst2 
)

◆ FoldConstantArithmetic() [2/2]

SDValue SelectionDAG::FoldConstantArithmetic ( unsigned  Opcode,
const SDLoc DL,
EVT  VT,
const ConstantSDNode Cst1,
const ConstantSDNode Cst2 
)

◆ FoldConstantVectorArithmetic()

SDValue SelectionDAG::FoldConstantVectorArithmetic ( unsigned  Opcode,
const SDLoc DL,
EVT  VT,
ArrayRef< SDValue Ops,
const SDNodeFlags  Flags = SDNodeFlags() 
)

◆ FoldSetCC()

SDValue SelectionDAG::FoldSetCC ( EVT  VT,
SDValue  N1,
SDValue  N2,
ISD::CondCode  Cond,
const SDLoc dl 
)

◆ FoldSymbolOffset()

SDValue SelectionDAG::FoldSymbolOffset ( unsigned  Opcode,
EVT  VT,
const GlobalAddressSDNode GA,
const SDNode N2 
)

◆ getAddrSpaceCast()

SDValue SelectionDAG::getAddrSpaceCast ( const SDLoc dl,
EVT  VT,
SDValue  Ptr,
unsigned  SrcAS,
unsigned  DestAS 
)

◆ getAllOnesConstant()

SDValue llvm::SelectionDAG::getAllOnesConstant ( const SDLoc DL,
EVT  VT,
bool  IsTarget = false,
bool  IsOpaque = false 
)
inline

◆ getAnyExtendVectorInReg()

SDValue SelectionDAG::getAnyExtendVectorInReg ( SDValue  Op,
const SDLoc DL,
EVT  VT 
)

Return an operation which will any-extend the low lanes of the operand into the specified vector type.

For example, this can convert a v16i8 into a v4i32 by any-extending the low four lanes of the operand from i8 to i32.

Definition at line 1038 of file SelectionDAG.cpp.

References llvm::ISD::ANY_EXTEND_VECTOR_INREG, assert(), getNode(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), and llvm::EVT::isVector().

Referenced by combineShuffleToVectorExtend(), and isSETCCorConvertedSETCC().

◆ getAnyExtOrTrunc()

SDValue SelectionDAG::getAnyExtOrTrunc ( SDValue  Op,
const SDLoc DL,
EVT  VT 
)

◆ getAtomic() [1/4]

SDValue SelectionDAG::getAtomic ( unsigned  Opcode,
const SDLoc dl,
EVT  MemVT,
SDValue  Chain,
SDValue  Ptr,
SDValue  Val,
const Value PtrVal,
unsigned  Alignment,
AtomicOrdering  Ordering,
SyncScope::ID  SSID 
)

◆ getAtomic() [2/4]

SDValue SelectionDAG::getAtomic ( unsigned  Opcode,
const SDLoc dl,
EVT  MemVT,
SDValue  Chain,
SDValue  Ptr,
SDValue  Val,
MachineMemOperand MMO 
)

◆ getAtomic() [3/4]

SDValue SelectionDAG::getAtomic ( unsigned  Opcode,
const SDLoc dl,
EVT  MemVT,
EVT  VT,
SDValue  Chain,
SDValue  Ptr,
MachineMemOperand MMO 
)

Gets a node for an atomic op, produces result and chain and takes 1 operand.

Definition at line 5732 of file SelectionDAG.cpp.

References assert(), llvm::ISD::ATOMIC_LOAD, getAtomic(), getVTList(), and llvm::MVT::Other.

◆ getAtomic() [4/4]

SDValue SelectionDAG::getAtomic ( unsigned  Opcode,
const SDLoc dl,
EVT  MemVT,
SDVTList  VTList,
ArrayRef< SDValue Ops,
MachineMemOperand MMO 
)

◆ getAtomicCmpSwap() [1/2]

SDValue SelectionDAG::getAtomicCmpSwap ( unsigned  Opcode,
const SDLoc dl,
EVT  MemVT,
SDVTList  VTs,
SDValue  Chain,
SDValue  Ptr,
SDValue  Cmp,
SDValue  Swp,
MachinePointerInfo  PtrInfo,
unsigned  Alignment,
AtomicOrdering  SuccessOrdering,
AtomicOrdering  FailureOrdering,
SyncScope::ID  SSID 
)

Gets a node for an atomic cmpxchg op.

There are two valid Opcodes. ISD::ATOMIC_CMO_SWAP produces the value loaded and a chain result. ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS produces the value loaded, a success flag (initially i1), and a chain.

Definition at line 5640 of file SelectionDAG.cpp.

References assert(), llvm::ISD::ATOMIC_CMP_SWAP, llvm::ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, getEVTAlignment(), getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::EVT::getStoreSize(), llvm::SDValue::getValueType(), llvm::MachineMemOperand::MOLoad, llvm::MachineMemOperand::MOStore, and llvm::MachineMemOperand::MOVolatile.

Referenced by getExpandedMinMaxOps(), and getUniformBase().

◆ getAtomicCmpSwap() [2/2]

SDValue SelectionDAG::getAtomicCmpSwap ( unsigned  Opcode,
const SDLoc dl,
EVT  MemVT,
SDVTList  VTs,
SDValue  Chain,
SDValue  Ptr,
SDValue  Cmp,
SDValue  Swp,
MachineMemOperand MMO 
)

◆ getBasicBlock() [1/2]

SDValue SelectionDAG::getBasicBlock ( MachineBasicBlock MBB)

◆ getBasicBlock() [2/2]

SDValue llvm::SelectionDAG::getBasicBlock ( MachineBasicBlock MBB,
SDLoc  dl 
)

◆ getBitcast()

SDValue SelectionDAG::getBitcast ( EVT  VT,
SDValue  V 
)

Return a bitcast using the SDLoc of the value operand, and casting to the provided type.

Use getNode to set a custom SDLoc.

Definition at line 1759 of file SelectionDAG.cpp.

References llvm::ISD::BITCAST, getNode(), and llvm::SDValue::getValueType().

Referenced by llvm::X86TargetLowering::BuildFILD(), BuildSplatI(), combineAndMaskToShift(), combineBasicSADPattern(), combineBitcast(), combineBitcastForMaskedOp(), combineBitcastvxi1(), combineCompareEqual(), combineConcatVectorOfExtracts(), combineConcatVectorOfScalars(), combineExtractVectorElt(), combineExtractWithShuffle(), combineFneg(), combineHorizontalPredicateResult(), combineInsertSubvector(), combineLogicBlendIntoPBLENDV(), combineMaskedLoad(), combineMaskedStore(), combineRedundantDWordShuffle(), combineSelect(), combineShuffle(), combineShuffleOfSplat(), combineShuffleToVectorExtend(), combineStore(), combineTargetShuffle(), combineToExtendBoolVectorInReg(), combineTruncationShuffle(), combineVectorCompareAndMaskUnaryOp(), combineVectorSizedSetCCEquality(), combineVectorTruncationWithPACKUS(), combineVSelectWithAllOnesOrZeros(), combineVSZext(), combineX86ShuffleChain(), combineX86ShufflesConstants(), ConvertI1VectorToInteger(), convertIntLogicToFPLogic(), EltsFromConsecutiveLoads(), foldBitcastedFPLogic(), FoldIntToFPToInt(), getConstVector(), getCopyFromPartsVector(), getCopyToPartsVector(), getMaskNode(), getMemCmpLoad(), getMemsetValue(), getMOVL(), getOnesVector(), getScalarValueForVectorElement(), getTargetVShiftByConstNode(), getTargetVShiftNode(), getv64i1Argument(), getVShift(), getZeroVector(), haveEfficientBuildVectorPattern(), llvm::TargetLowering::IncrementMemoryAddress(), isSortedByValueNo(), isTruncateOf(), isTruncWithZeroHighBitsInput(), lower256BitVectorShuffle(), LowerAVXExtend(), LowerBITCAST(), LowerBITREVERSE_XOP(), LowerBUILD_VECTORAsVariablePermute(), lowerBuildVectorAsBroadcast(), LowerBuildVectorAsInsert(), LowerBuildVectorv16i8(), LowerBuildVectorv4x32(), LowerEXTEND_VECTOR_INREG(), LowerExtended1BitVectorLoad(), LowerExtendedLoad(), LowerEXTRACT_VECTOR_ELT_SSE4(), LowerHorizontalByteSum(), LowerIntVSETCC_AVX512(), lowerMasksToReg(), LowerMGATHER(), LowerMSCATTER(), LowerMUL(), LowerMUL_LOHI(), LowerMULH(), lowerRegToMasks(), LowerSCALAR_TO_VECTOR(), LowerScalarImmediateShift(), LowerShift(), LowerShiftParts(), LowerTruncateVecI1(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), lowerUINT_TO_FP_vXi32(), lowerV16I32VectorShuffle(), lowerV16I8VectorShuffle(), lowerV2I64VectorShuffle(), lowerV4I32VectorShuffle(), lowerV4I64VectorShuffle(), lowerV8I16GeneralSingleInputVectorShuffle(), lowerV8I32VectorShuffle(), lowerV8I64VectorShuffle(), LowerVectorAllZeroTest(), LowerVectorCTLZInRegLUT(), LowerVectorCTPOPBitmath(), LowerVectorCTPOPInRegLUT(), lowerVectorShuffle(), lowerVectorShuffleAsBitBlend(), lowerVectorShuffleAsBlend(), lowerVectorShuffleAsBlendOfPSHUFBs(), lowerVectorShuffleAsBroadcast(), lowerVectorShuffleAsByteRotate(), lowerVectorShuffleAsElementInsertion(), lowerVectorShuffleAsLanePermuteAndBlend(), lowerVectorShuffleAsPermuteAndUnpack(), lowerVectorShuffleAsShift(), lowerVectorShuffleAsSpecificZeroOrAnyExtend(), lowerVectorShuffleAsZeroOrAnyExtend(), lowerVectorShuffleByMerging128BitLanes(), lowerVectorShuffleWithPACK(), lowerVectorShuffleWithPSHUFB(), LowerVSETCC(), lowerX86FPLogicOp(), matchVectorShuffleWithPACK(), narrowExtractedVectorBinOp(), narrowExtractedVectorLoad(), Passv64i1ArgInRegs(), peekThroughBitcast(), recoverFramePointer(), reduceVMULWidth(), llvm::X86TargetLowering::ReplaceNodeResults(), splitAndLowerVectorShuffle(), truncateVectorWithPACK(), and XFormVExtractWithShuffleIntoLoad().

◆ getBlockAddress()

SDValue SelectionDAG::getBlockAddress ( const BlockAddress BA,
EVT  VT,
int64_t  Offset = 0,
bool  isTarget = false,
unsigned char  TargetFlags = 0 
)

◆ getBoolExtOrTrunc()

SDValue SelectionDAG::getBoolExtOrTrunc ( SDValue  Op,
const SDLoc SL,
EVT  VT,
EVT  OpVT 
)

Convert Op, which must be of integer type, to the integer type VT, by using an extension appropriate for the target's BooleanContent for type OpVT or truncating it.

Definition at line 1017 of file SelectionDAG.cpp.

References llvm::EVT::bitsLE(), llvm::TargetLoweringBase::getBooleanContents(), llvm::TargetLoweringBase::getExtendForContent(), getNode(), llvm::SDValue::getValueType(), and llvm::ISD::TRUNCATE.

Referenced by getAsCarry(), and llvm::TargetLowering::SimplifySetCC().

◆ getBuildVector() [1/2]

SDValue llvm::SelectionDAG::getBuildVector ( EVT  VT,
const SDLoc DL,
ArrayRef< SDValue Ops 
)
inline

Return an ISD::BUILD_VECTOR node.

The number of elements in VT, which must be a vector type, must match the number of operands in Ops. The operands must have the same type as (or, for integers, a type wider than) VT's element type.

Definition at line 712 of file SelectionDAG.h.

References llvm::ISD::BUILD_VECTOR.

Referenced by buildScalarToVector(), buildVector(), BuildVectorFromScalar(), ChangeVSETULTtoVSETULE(), combineConcatVectorOfExtracts(), combineConcatVectorOfScalars(), combineExtractSubvector(), combineShuffleOfScalars(), combineShuffleOfSplat(), combineToExtendBoolVectorInReg(), combineX86ShuffleChain(), CompactSwizzlableVector(), ConstantAddressBlock(), convertBuildVectorCastElt(), ConvertI1VectorToInteger(), convertLocVTToValVT(), createBSWAPShuffleMask(), emitRemovedIntrinsicError(), ExtendToType(), extractSubVector(), foldBitcastedFPLogic(), FoldCONCAT_VECTORS(), FoldConstantArithmetic(), FoldConstantVectorArithmetic(), GeneratePerfectShuffle(), GenerateTBL(), getBuildVectorSplat(), getConstant(), getConstVector(), getCopyFromPartsVector(), getCopyToPartsVector(), getExpandedMinMaxOps(), getFPTernOp(), getGeneralPermuteNode(), getNode(), getTargetVShiftByConstNode(), getTargetVShiftNode(), getUnderlyingArgReg(), llvm::SelectionDAGBuilder::getValueImpl(), getVectorCompareInfo(), hasOnlySelectUsers(), haveEfficientBuildVectorPattern(), isSETCCorConvertedSETCC(), IsSingleInstrConstant(), isTruncateOf(), LowerBITCAST(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), LowerBUILD_VECTORAsVariablePermute(), lowerBuildVectorToBitOp(), llvm::NVPTXTargetLowering::LowerCall(), llvm::AMDGPUTargetLowering::LowerCONCAT_VECTORS(), llvm::AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(), llvm::SITargetLowering::LowerFormalArguments(), llvm::AMDGPUTargetLowering::LowerFP64_TO_INT(), llvm::AMDGPUTargetLowering::LowerFTRUNC(), lowerMSABinaryBitImmIntr(), lowerMSABitClearImm(), lowerMSASplatZExt(), LowerShift(), llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), lowerVECTOR_SHUFFLE_VSHF(), LowerVECTOR_SHUFFLEv8i8(), LowerVectorCTLZInRegLUT(), LowerVectorCTPOPInRegLUT(), lowerVectorShuffleAsBitBlend(), lowerVectorShuffleAsBitMask(), lowerVectorShuffleAsBlend(), lowerVectorShuffleAsBlendOfPSHUFBs(), lowerVectorShuffleAsSpecificZeroOrAnyExtend(), lowerVectorShuffleWithPSHUFB(), LowerVSETCC(), narrowExtractedVectorLoad(), NormalizeBuildVector(), peekThroughBitcast(), PerformBUILD_VECTORCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::AMDGPUTargetLowering::performShlCombine(), llvm::AMDGPUTargetLowering::performSraCombine(), llvm::AMDGPUTargetLowering::performSrlCombine(), ReorganizeVector(), ReplaceINTRINSIC_W_CHAIN(), ReplaceLoadVector(), llvm::R600TargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::TargetLowering::scalarizeVectorLoad(), skipExtensionForVectorMULL(), SkipExtensionForVMULL(), splitAndLowerVectorShuffle(), llvm::AMDGPUTargetLowering::splitBinaryBitConstantOpImpl(), tryBuildVectorShuffle(), and tryToFoldExtendOfConstant().

◆ getBuildVector() [2/2]

SDValue llvm::SelectionDAG::getBuildVector ( EVT  VT,
const SDLoc DL,
ArrayRef< SDUse Ops 
)
inline

Return an ISD::BUILD_VECTOR node.

The number of elements in VT, which must be a vector type, must match the number of operands in Ops. The operands must have the same type as (or, for integers, a type wider than) VT's element type.

Definition at line 721 of file SelectionDAG.h.

References llvm::ISD::BUILD_VECTOR.

◆ getCALLSEQ_END()

SDValue llvm::SelectionDAG::getCALLSEQ_END ( SDValue  Chain,
SDValue  Op1,
SDValue  Op2,
SDValue  InGlue,
const SDLoc DL 
)
inline

◆ getCALLSEQ_START()

SDValue llvm::SelectionDAG::getCALLSEQ_START ( SDValue  Chain,
uint64_t  InSize,
uint64_t  OutSize,
const SDLoc DL 
)
inline

◆ getCommutedVectorShuffle()

SDValue SelectionDAG::getCommutedVectorShuffle ( const ShuffleVectorSDNode SV)

Returns an ISD::VECTOR_SHUFFLE node semantically equivalent to the shuffle node in input but with swapped operands.

Example: shuffle A, B, <0,5,2,7> -> shuffle B, A, <4,1,6,3>

Definition at line 1644 of file SelectionDAG.cpp.

References llvm::ShuffleVectorSDNode::commuteMask(), llvm::ShuffleVectorSDNode::getMask(), llvm::SDNode::getOperand(), llvm::SDNode::getSimpleValueType(), and getVectorShuffle().

Referenced by combineShuffleOfSplat(), and lowerVectorShuffle().

◆ getCondCode()

SDValue SelectionDAG::getCondCode ( ISD::CondCode  Cond)

◆ getConstant() [1/3]

SDValue SelectionDAG::getConstant ( uint64_t  Val,
const SDLoc DL,
EVT  VT,
bool  isTarget = false,
bool  isOpaque = false 
)

Create a ConstantSDNode wrapping a constant value.

If VT is a vector type, the constant is splatted into a BUILD_VECTOR.

If only legal types can be produced, this does the necessary transformations (e.g., if the vector element type is illegal).

Definition at line 1095 of file SelectionDAG.cpp.

References assert(), llvm::EVT::getScalarType(), and llvm::EVT::getSizeInBits().

Referenced by AddCombineBUILD_VECTORToVPADDL(), AddCombineToVPADD(), AddCombineVUZPToVPADDL(), addIPMSequence(), adjustForSubtraction(), adjustForTestUnderMask(), adjustICmpTruncate(), adjustSubwordCmp(), adjustZeroCmp(), AnalyzeReturnValues(), bitcastf32Toi32(), BuildExactSDIV(), BuildIntrinsicOp(), llvm::SITargetLowering::buildRSRC(), llvm::PPCTargetLowering::BuildSDIVPow2(), BuildSplatI(), llvm::TargetLowering::BuildUDIV(), buildVector(), BuildVectorFromScalar(), calculateByteProvider(), CallingConvSupported(), canFoldInAddressingMode(), CC_Lanai32_VarArg(), llvm::AArch64TargetLowering::CCAssignFnForReturn(), llvm::ARMTargetLowering::CCAssignFnForReturn(), ChangeVSETULTtoVSETULE(), clampDynamicVectorIndex(), combineAcrossLanesIntrinsic(), combineADC(), combineAddOrSubToADCOrSBB(), combineAndMaskToShift(), CombineBaseUpdate(), combineBitcastvxi1(), combineBrCond(), combineCMov(), combineCompareEqual(), combineExtractSubvector(), combineExtractVectorElt(), combineExtractWithShuffle(), combineHorizontalPredicateResult(), combineLoopSADPattern(), combineMaskedLoad(), combineMaskedStore(), combineMinNumMaxNum(), combineMul(), combineMulSpecial(), combineSelect(), combineSelectOfTwoConstants(), combineSetCC(), combineSetCCAtomicArith(), combineSext(), combineShiftLeft(), combineShiftRightArithmetic(), combineShiftRightLogical(), combineShuffleOfSplat(), combineSub(), combineSubToSubus(), combineTargetShuffle(), combineToExtendBoolVectorInReg(), combineVectorSizedSetCCEquality(), combineVectorTruncationWithPACKSS(), combineVectorTruncationWithPACKUS(), CombineVMOVDRRCandidateWithVecOp(), combineX86ShuffleChain(), combineZext(), ConstantAddressBlock(), constantFoldBFE(), ConvertI1VectorToInteger(), ConvertSelectToConcatVector(), convertValVTToLocVT(), createBSWAPShuffleMask(), CreateCopyOfByValArgument(), createFPCmp(), createGPRPairNode(), createLoadLR(), createPSADBW(), createStoreLR(), detectAVGPattern(), EltsFromConsecutiveLoads(), emitCLC(), EmitCMP(), emitCmp(), emitConditionalComparison(), llvm::MipsSETargetLowering::EmitInstrWithCustomInserter(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), llvm::MipsTargetLowering::EmitInstrWithCustomInserter(), EmitKTEST(), emitMemMem(), emitRemovedIntrinsicError(), emitSETCC(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemchr(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemset(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcmp(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcpy(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrlen(), EnsureStackAlignment(), Expand64BitShift(), ExpandBITCAST(), expandf64Toi32(), llvm::TargetLowering::expandFP_TO_SINT(), llvm::TargetLowering::expandMUL_LOHI(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), expandV4F32ToV2F64(), expandVAArg(), ExtendToType(), ExtendUsesToFormExtLoad(), extractF64Exponent(), findUser(), foldBitcastedFPLogic(), FoldConstantArithmetic(), FoldIntToFPToInt(), foldMaskAndShiftToExtract(), foldMaskAndShiftToScale(), foldMaskedShiftToScaledMask(), FoldSetCC(), foldXorTruncShiftIntoCmp(), fp16SrcZerosHighBits(), genConstMult(), generateEquivalentSub(), GeneratePerfectShuffle(), GenerateTBL(), getAArch64Cmp(), getAArch64XALUOOp(), getAbsolute(), llvm::MipsTargetLowering::getAddrNonPICSym64(), getARMIndexedAddressParts(), getAsCarry(), getBoundedStrlen(), getBuildVectorSplat(), getCCResult(), getConstant(), llvm::TargetLowering::getConstTrueVal(), getConstVector(), getCopyFromParts(), getCopyFromPartsVector(), llvm::RegsForValue::getCopyFromRegs(), getCopyToPartsVector(), GetDemandedBits(), getDivRemArgList(), getDUPLANEOp(), getExpandedMinMaxOps(), GetExponent(), getExtendedControlRegister(), GetFPLibCall(), getFPTernOp(), getGeneralPermuteNode(), llvm::AMDGPUTargetLowering::getHiHalf64(), getIntPtrConstant(), llvm::XCoreTargetLowering::getJumpTableEncoding(), llvm::ARMTargetLowering::getJumpTableEncoding(), getLimitedPrecisionExp2(), getLogicalNOT(), llvm::AMDGPUTargetLowering::getLoHalf64(), getMad64_32(), getMaskNode(), getMemBasePlusOffset(), getMemCmpLoad(), getMemsetStringVal(), getMemsetValue(), getMOVL(), getNode(), getNOT(), getOnesVector(), llvm::MipsTargetLowering::getOpndList(), getPermuteNode(), llvm::PPCTargetLowering::getPICJumpTableRelocBaseExpr(), llvm::AVRTargetLowering::getPostIndexedAddressParts(), llvm::AVRTargetLowering::getPreIndexedAddressParts(), GetPromotionOpcode(), getReadPerformanceCounter(), getReadTimeStampCounter(), getReductionSDNode(), getSETCC(), getShuffleScalarElt(), GetSignificand(), llvm::NVPTXTargetLowering::getSqrtEstimate(), getT2IndexedAddressParts(), llvm::ARCTargetLowering::getTargetNodeName(), llvm::SystemZTargetLowering::getTargetNodeName(), getTargetVShiftByConstNode(), getTargetVShiftNode(), getUnderlyingArgReg(), getUniformBase(), getV4X86ShuffleImm8ForMask(), llvm::SelectionDAGBuilder::getValueImpl(), getVectorCompareInfo(), llvm::TargetLowering::getVectorElementPointer(), getVShift(), getZeroExtendInReg(), getZeroVector(), hasOnlySelectUsers(), haveEfficientBuildVectorPattern(), llvm::TargetLowering::IncrementMemoryAddress(), initAccumulator(), insert1BitVector(), llvm::intCCToAVRCC(), IntCondCCodeToICC(), isADDADDMUL(), isBLACompatibleAddress(), isBoolSGPR(), isBSwapHWordElement(), isConditionalZeroOrAllOnes(), isConstantOrUndefBUILD_VECTOR(), llvm::TargetLowering::isExtendedTrueVal(), isFloatingPointZero(), llvm::PPCTargetLowering::isLegalAddressingMode(), isMemOPCandidate(), isNEONModifiedImm(), isOpcodeHandled(), llvm::ARMTargetLowering::isReadOnly(), isSaturatingConditional(), isSETCCorConvertedSETCC(), IsSingleInstrConstant(), IsSmallObject(), isTargetConstant(), isTruncateOf(), isTruncWithZeroHighBitsInput(), llvm::SITargetLowering::isTypeDesirableForOp(), isVShiftRImm(), isWordAligned(), isXor1OfSetCC(), LowerABS(), LowerADDC_ADDE_SUBC_SUBE(), LowerADDSUBCARRY(), LowerADJUST_TRAMPOLINE(), LowerAndToBT(), LowerAsSplatVectorLoad(), LowerATOMIC_FENCE(), lowerAtomicArith(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), LowerBoolVSETCC_AVX512(), llvm::LanaiTargetLowering::LowerBR_CC(), LowerBR_CC(), llvm::HexagonTargetLowering::LowerBUILD_VECTOR(), LowerBUILD_VECTORAsVariablePermute(), LowerBuildVectorv16i8(), llvm::HexagonTargetLowering::LowerCall(), llvm::SITargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), lowerCallResult(), LowerCallResult(), llvm::TargetLowering::LowerCallTo(), llvm::TargetLowering::lowerCmpEqZeroToCtlzSrl(), llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(), LowerCTLZ(), llvm::AMDGPUTargetLowering::LowerCTLZ_CTTZ(), LowerCTTZ(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), llvm::HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(), LowerDYNAMIC_STACKALLOC(), LowerEXTEND_VECTOR_INREG(), LowerExtended1BitVectorLoad(), LowerExtendedLoad(), llvm::HexagonTargetLowering::LowerEXTRACT_VECTOR(), LowerEXTRACT_VECTOR_ELT_SSE4(), LowerF128Load(), LowerF128Store(), lowerFCOPYSIGN32(), lowerFCOPYSIGN64(), LowerFGETSIGN(), llvm::R600TargetLowering::LowerFormalArguments(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_64(), llvm::AMDGPUTargetLowering::LowerFP_TO_FP16(), llvm::AMDGPUTargetLowering::LowerFROUND64(), llvm::AMDGPUTargetLowering::LowerFTRUNC(), llvm::AMDGPUTargetLowering::LowerGlobalAddress(), llvm::HexagonTargetLowering::LowerGLOBALADDRESS(), LowerHorizontalByteSum(), LowerINSERT_SUBVECTOR(), llvm::HexagonTargetLowering::LowerINSERT_VECTOR(), llvm::AMDGPUTargetLowering::LowerINT_TO_FP32(), llvm::AMDGPUTargetLowering::LowerINT_TO_FP64(), LowerInterruptReturn(), llvm::HexagonTargetLowering::LowerINTRINSIC_VOID(), LowerINTRINSIC_W_CHAIN(), LowerIntVSETCC_AVX512(), llvm::MSP430TargetLowering::LowerJumpTable(), LowerLabelRef(), llvm::MipsTargetLowering::lowerLOAD(), LowerMemOpCallTo(), lowerMSABinaryBitImmIntr(), lowerMSABitClear(), lowerMSABitClearImm(), lowerMSASplatImm(), lowerMSASplatZExt(), llvm::LanaiTargetLowering::LowerMUL(), LowerMUL(), LowerMUL_LOHI(), lowerMUL_LOHI32(), LowerMULH(), llvm::R600TargetLowering::LowerOperation(), llvm::RISCVTargetLowering::LowerOperation(), llvm::BPFTargetLowering::LowerOperation(), llvm::HexagonTargetLowering::LowerPREFETCH(), LowerPREFETCH(), llvm::SITargetLowering::LowerReturn(), llvm::NVPTXTargetLowering::LowerReturn(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::SparcTargetLowering::LowerReturn_64(), llvm::MSP430TargetLowering::LowerRETURNADDR(), llvm::HexagonTargetLowering::LowerRETURNADDR(), LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(), LowerRotate(), LowerScalarImmediateShift(), LowerSDIV_v4i16(), LowerSDIV_v4i8(), llvm::AMDGPUTargetLowering::LowerSDIVREM(), llvm::LanaiTargetLowering::LowerSELECT_CC(), LowerSELECT_CC(), llvm::LanaiTargetLowering::LowerSETCC(), llvm::MSP430TargetLowering::LowerSETCC(), llvm::LanaiTargetLowering::LowerSETCCE(), LowerSETCCE(), LowerShift(), LowerShiftParts(), llvm::LanaiTargetLowering::LowerSHL_PARTS(), llvm::LanaiTargetLowering::LowerSRL_PARTS(), LowerToTLSExecModel(), LowerTruncateVecI1(), LowerTruncatingStore(), LowerUDIV(), llvm::AMDGPUTargetLowering::LowerUDIVREM(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), lowerUINT_TO_FP_v2i32(), lowerUINT_TO_FP_vXi32(), LowerUMULO_SMULO(), lowerV16I8VectorShuffle(), lowerV2F64VectorShuffle(), lowerV2X128VectorShuffle(), lowerV4F64VectorShuffle(), lowerV4X128VectorShuffle(), lowerV8F64VectorShuffle(), LowerVASTART(), llvm::HexagonTargetLowering::LowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE_SHF(), LowerVECTOR_SHUFFLEv8i8(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTLZInRegLUT(), LowerVectorCTPOPBitmath(), LowerVectorCTPOPInRegLUT(), LowerVectorINT_TO_FP(), lowerVectorShuffleAsBitBlend(), lowerVectorShuffleAsBitMask(), lowerVectorShuffleAsBlend(), lowerVectorShuffleAsBlendOfPSHUFBs(), lowerVectorShuffleAsByteRotate(), lowerVectorShuffleAsElementInsertion(), lowerVectorShuffleAsInsertPS(), lowerVectorShuffleAsRotate(), lowerVectorShuffleAsShift(), lowerVectorShuffleAsSpecificZeroOrAnyExtend(), lowerVectorShuffleAsTruncBroadcast(), lowerVectorShuffleToEXPAND(), lowerVectorShuffleWithPSHUFB(), lowerVectorShuffleWithSHUFPD(), lowerVectorShuffleWithSSE4A(), LowerVSETCC(), LowerWRITE_REGISTER(), lowerX86CmpEqZeroToCtlzSrl(), LowerXALUO(), LowerXOR(), LowerZERO_EXTEND_AVX512(), llvm::SparcTargetLowering::makeAddress(), materializeSBB(), mayTailCallThisCC(), memsetStore(), narrowExtractedVectorBinOp(), NegateCC(), NormalizeBuildVector(), optimizeLogicalImm(), parsePhysicalReg(), Passv64i1ArgInRegs(), peekThroughBitcast(), PerformAddcSubcCombine(), PerformAddeSubeCombine(), performANDCombine(), PerformARMBUILD_VECTORCombine(), PerformBFICombine(), performBitcastCombine(), llvm::ARMTargetLowering::PerformCMOVToBFICombine(), performConcatVectorsCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), performDSPShiftCombine(), performExtendCombine(), llvm::AMDGPUTargetLowering::performFAbsCombine(), performFDivCombine(), llvm::AMDGPUTargetLowering::performFNegCombine(), performFpToIntCombine(), performIntegerAbsCombine(), PerformIntrinsicCombine(), performMulCombine(), PerformMULCombine(), performORCombine(), PerformORCombineToBFI(), performSetccAddFolding(), PerformShiftCombine(), llvm::AMDGPUTargetLowering::performShlCombine(), performSHLCombine(), PerformSHLSimplify(), llvm::AMDGPUTargetLowering::performSraCombine(), llvm::AMDGPUTargetLowering::performSrlCombine(), PerformSTORECombine(), performTBZCombine(), PerformVCVTCombine(), PerformVDIVCombine(), PerformVDUPCombine(), performXorCombine(), PrepareCall(), promoteExtBeforeAdd(), llvm::AArch64TargetLowering::ReconstructShuffle(), recoverFramePointer(), ReorganizeVector(), ReplaceLongIntrinsic(), llvm::R600TargetLowering::ReplaceNodeResults(), llvm::AVRTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), ReplaceREADCYCLECOUNTER(), resolveBuildVector(), llvm::TargetLowering::scalarizeVectorLoad(), llvm::TargetLowering::scalarizeVectorStore(), llvm::TargetLowering::ShrinkDemandedConstant(), ShrinkLoadReplaceStoreWithStore(), llvm::TargetLowering::SimplifyDemandedBits(), simplifyDivRem(), llvm::TargetLowering::SimplifySetCC(), skipExtensionForVectorMULL(), SkipExtensionForVMULL(), llvm::TargetLowering::softenSetCCOperands(), llvm::AMDGPUTargetLowering::split64BitValue(), llvm::AMDGPUTargetLowering::splitBinaryBitConstantOpImpl(), splitInt128(), splitStores(), splitStoreSplat(), llvm::AMDGPUTargetLowering::SplitVectorLoad(), llvm::AMDGPUTargetLowering::SplitVectorStore(), llvm::AMDGPUTargetLowering::storeStackInputValue(), TranslateX86CC(), truncateVecElts(), tryBuildVectorReplicate(), tryCombineShiftImm(), tryCombineToEXTR(), tryExtendDUPToExtractHigh(), tryFoldToZero(), tryFormConcatFromShuffle(), tryLowerToSLI(), TryMULWIDECombine(), tryToFoldExtendOfConstant(), UnpackFromArgumentSlot(), llvm::SelectionDAGBuilder::visitBitTestCase(), llvm::SelectionDAGBuilder::visitBitTestHeader(), llvm::SelectionDAGBuilder::visitJumpTableHeader(), llvm::SelectionDAGBuilder::visitSPDescriptorParent(), llvm::SelectionDAGBuilder::visitSwitchCase(), WidenMaskArithmetic(), WidenVector(), willShiftRightEliminate(), WinDBZCheckDenominator(), and XFormVExtractWithShuffleIntoLoad().

◆ getConstant() [2/3]

SDValue SelectionDAG::getConstant ( const APInt Val,
const SDLoc DL,
EVT  VT,
bool  isTarget = false,
bool  isOpaque = false 
)

Definition at line 1104 of file SelectionDAG.cpp.

References llvm::ConstantInt::get(), and getConstant().

◆ getConstant() [3/3]

SDValue SelectionDAG::getConstant ( const ConstantInt Val,
const SDLoc DL,
EVT  VT,
bool  isTarget = false,
bool  isOpaque = false 
)

◆ getConstantDbgValue()

SDDbgValue * SelectionDAG::getConstantDbgValue ( DIVariable Var,
DIExpression Expr,
const Value C,
const DebugLoc DL,
unsigned  O 
)

Creates a constant SDDbgValue node.

Constant.

Definition at line 7010 of file SelectionDAG.cpp.

References assert(), and llvm::SDDbgInfo::getAlloc().

Referenced by getUnderlyingArgReg().

◆ getConstantFP() [1/3]

SDValue SelectionDAG::getConstantFP ( double  Val,
const SDLoc DL,
EVT  VT,
bool  isTarget = false 
)

Create a ConstantFPSDNode wrapping a constant value.

If VT is a vector type, the constant is splatted into a BUILD_VECTOR.

If only legal types can be produced, this does the necessary transformations (e.g., if the vector element type is illegal). The forms that take a double should only be used for simple constants that can be exactly represented in VT. No checks are made.

Definition at line 1243 of file SelectionDAG.cpp.

References llvm::lltok::APFloat, llvm::APFloat::convert(), EVTToAPFloatSemantics(), llvm::MVT::f128, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::MVT::f80, llvm::EVT::getScalarType(), llvm_unreachable, llvm::MVT::ppcf128, and llvm::APFloatBase::rmNearestTiesToEven.

Referenced by llvm::X86TargetLowering::BuildFILD(), CanCombineFCOPYSIGN_EXTEND_ROUND(), combineExtractWithShuffle(), combineFneg(), combineShuffleOfSplat(), createBSWAPShuffleMask(), EltsFromConsecutiveLoads(), emitRemovedIntrinsicError(), ExpandPowI(), FoldIntToFPToInt(), getConstantFP(), getConstVector(), getEstimate(), getF32Constant(), GetFPLibCall(), getFPTernOp(), getMad64_32(), getMemsetStringVal(), getMemsetValue(), GetNegatedExpression(), getNode(), getShuffleScalarElt(), llvm::SelectionDAGBuilder::getValueImpl(), getVectorCompareInfo(), getZeroVector(), haveEfficientBuildVectorPattern(), isCanonicalized(), isFMulNegTwo(), LowerFABSorFNEG(), llvm::AMDGPUTargetLowering::LowerFCEIL(), LowerFCOPYSIGN(), llvm::AMDGPUTargetLowering::LowerFFLOOR(), llvm::AMDGPUTargetLowering::LowerFP64_TO_INT(), llvm::AMDGPUTargetLowering::LowerFRINT(), llvm::AMDGPUTargetLowering::LowerFROUND32_16(), llvm::AMDGPUTargetLowering::LowerFROUND64(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), lowerUINT_TO_FP_v2i32(), lowerUINT_TO_FP_vXi32(), peekThroughBitcast(), llvm::AMDGPUTargetLowering::performClampCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), PrepareCall(), llvm::R600TargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), and XFormVExtractWithShuffleIntoLoad().

◆ getConstantFP() [2/3]

SDValue SelectionDAG::getConstantFP ( const APFloat Val,
const SDLoc DL,
EVT  VT,
bool  isTarget = false 
)

Definition at line 1206 of file SelectionDAG.cpp.

References llvm::ConstantFP::get(), getConstantFP(), and getContext().

◆ getConstantFP() [3/3]

SDValue SelectionDAG::getConstantFP ( const ConstantFP CF,
const SDLoc DL,
EVT  VT,
bool  isTarget = false 
)

◆ getConstantPool() [1/2]

SDValue SelectionDAG::getConstantPool ( const Constant C,
EVT  VT,
unsigned  Align = 0,
int  Offs = 0,
bool  isT = false,
unsigned char  TargetFlags = 0 
)

◆ getConstantPool() [2/2]

SDValue SelectionDAG::getConstantPool ( MachineConstantPoolValue C,
EVT  VT,
unsigned  Align = 0,
int  Offs = 0,
bool  isT = false,
unsigned char  TargetFlags = 0 
)

◆ getContext()

LLVMContext* llvm::SelectionDAG::getContext ( ) const
inline

Definition at line 393 of file SelectionDAG.h.

References Context.

Referenced by AddCombineVUZPToVPADDL(), llvm::RegsForValue::AddInlineAsmOperands(), addStackMapLiveVars(), llvm::analyzeArguments(), AnalyzeReturnValues(), llvm::X86TargetLowering::BuildFILD(), buildPCRelGlobalAddress(), BuildVectorFromScalar(), calculateByteProvider(), CallingConvSupported(), canFoldInAddressingMode(), CC_Lanai32_VarArg(), llvm::AArch64TargetLowering::CCAssignFnForReturn(), llvm::ARMTargetLowering::CCAssignFnForReturn(), combineConcatVectorOfExtracts(), combineConcatVectorOfScalars(), combineFMinNumFMaxNum(), combineGatherScatter(), combineHorizontalPredicateResult(), combineInsertSubvector(), combineLoad(), combineLoopMAddPattern(), combineMaskedLoad(), combineMaskedStore(), combineMinNumMaxNum(), combineShuffleOfSplat(), combineShuffleToVectorExtend(), combineSIntToFP(), combineStore(), combineToExtendBoolVectorInReg(), combineToExtendVectorInReg(), combineUIntToFP(), combineVectorTruncation(), CombineVMOVDRRCandidateWithVecOp(), combineVSelectWithAllOnesOrZeros(), ConstantAddressBlock(), ConvertSelectToConcatVector(), createBSWAPShuffleMask(), CreateStackTemporary(), createVirtualRegs(), llvm::SelectionDAGBuilder::EmitBranchForMergedCondition(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), llvm::MipsTargetLowering::EmitInstrWithCustomInserter(), emitNonHSAIntrinsicError(), emitRemovedIntrinsicError(), llvm::ARMSelectionDAGInfo::EmitSpecializedLibcall(), llvm::HexagonSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::XCoreSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::AArch64SelectionDAGInfo::EmitTargetCodeForMemset(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(), EnsureStackAlignment(), errorUnsupported(), llvm::TargetLowering::expandFP_TO_SINT(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), expandVAArg(), extractSubVector(), fail(), FindMemType(), findUser(), foldBitcastedFPLogic(), FoldConstantArithmetic(), FoldConstantVectorArithmetic(), foldXorTruncShiftIntoCmp(), getBuildPairElt(), getConstant(), getConstantFP(), getCopyFromParts(), getCopyFromPartsVector(), llvm::SelectionDAGBuilder::getCopyFromRegs(), getCopyToParts(), getCopyToPartsVector(), getDivRemArgList(), getEstimate(), getEVTAlignment(), getExpandedMinMaxOps(), GetFPLibCall(), getFPTernOp(), llvm::ARMTargetLowering::getJumpTableEncoding(), getMemcpy(), getMemcpyLoadsAndStores(), getMemmove(), getMemmoveLoadsAndStores(), getMemset(), getMemsetStringVal(), getMemsetValue(), getMOVL(), llvm::MipsTargetLowering::getOpndList(), llvm::PPCTargetLowering::getPICJumpTableRelocBaseExpr(), GetPromotionOpcode(), GetRegistersForValue(), llvm::AVRTargetLowering::getSetCCResultType(), llvm::ARCTargetLowering::getTargetNodeName(), getUnderlyingArgReg(), getUniformBase(), llvm::SelectionDAGBuilder::getValueImpl(), getVectorCompareInfo(), hasOnlySelectUsers(), haveEfficientBuildVectorPattern(), llvm::TargetLowering::IncrementMemoryAddress(), llvm::SelectionDAGBuilder::init(), isBoolSGPR(), llvm::SITargetLowering::isEligibleForTailCallOptimization(), isNegativeOne(), isSETCCorConvertedSETCC(), IsSingleInstrConstant(), IsSmallObject(), isSortedByValueNo(), isTruncateOf(), llvm::SITargetLowering::isTypeDesirableForOp(), isWordAligned(), isXor1OfSetCC(), LowerADDC_ADDE_SUBC_SUBE(), llvm::X86TargetLowering::LowerAsmOperandForConstraint(), LowerAsSplatVectorLoad(), LowerBITCAST(), LowerBUILD_VECTORAsVariablePermute(), lowerBuildVectorAsBroadcast(), llvm::HexagonTargetLowering::LowerCall(), llvm::SITargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), lowerCallResult(), llvm::HexagonTargetLowering::LowerCallResult(), llvm::SITargetLowering::LowerCallResult(), LowerCallResult(), llvm::AMDGPUTargetLowering::LowerCTLZ_CTTZ(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), llvm::AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(), LowerExtendedLoad(), llvm::SparcTargetLowering::LowerF128_LibCallArg(), llvm::SparcTargetLowering::LowerF128Compare(), llvm::SparcTargetLowering::LowerF128Op(), llvm::AMDGPUTargetLowering::LowerFCEIL(), llvm::AMDGPUTargetLowering::LowerFFLOOR(), llvm::R600TargetLowering::LowerFormalArguments(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::SITargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerFormalArguments_64(), LowerFPOWI(), llvm::AMDGPUTargetLowering::LowerFRINT(), llvm::AMDGPUTargetLowering::LowerFROUND32_16(), llvm::AMDGPUTargetLowering::LowerFROUND64(), LowerFSINCOS(), llvm::AMDGPUTargetLowering::LowerFTRUNC(), llvm::AMDGPUTargetLowering::LowerGlobalAddress(), llvm::AMDGPUTargetLowering::LowerINT_TO_FP32(), LowerInterruptReturn(), LowerMULH(), llvm::RISCVTargetLowering::LowerOperation(), llvm::BPFTargetLowering::LowerOperation(), llvm::NVPTXTargetLowering::LowerOperation(), llvm::SelectionDAGBuilder::lowerRangeToAssertZExt(), lowerRegToMasks(), llvm::HexagonTargetLowering::LowerReturn(), llvm::SITargetLowering::LowerReturn(), llvm::SystemZTargetLowering::LowerReturn(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::SparcTargetLowering::LowerReturn_64(), llvm::AMDGPUTargetLowering::LowerSDIVREM(), llvm::TargetLowering::LowerToTLSEmulatedModel(), LowerToTLSExecModel(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), lowerUINT_TO_FP_vXi32(), llvm::AMDGPUTargetLowering::lowerUnhandledCall(), LowerVASTART(), LowerVECTOR_SHUFFLE(), LowerVectorINT_TO_FP(), LowerVSETCC(), llvm::TargetLowering::makeLibCall(), MatchingStackOffset(), mayTailCallThisCC(), narrowExtractedVectorBinOp(), narrowExtractedVectorLoad(), NormalizeBuildVector(), Passv64i1ArgInRegs(), peekThroughBitcast(), PerformARMBUILD_VECTORCombine(), PerformBUILD_VECTORCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), performExtendCombine(), PerformInsertEltCombine(), llvm::AMDGPUTargetLowering::performLoadCombine(), performSelectCombine(), llvm::AMDGPUTargetLowering::performStoreCombine(), PerformSTORECombine(), PrepareCall(), promoteToConstantPool(), llvm::AArch64TargetLowering::ReconstructShuffle(), reduceVMULWidth(), ReplaceLoadVector(), llvm::R600TargetLowering::ReplaceNodeResults(), llvm::SITargetLowering::ReplaceNodeResults(), llvm::PPCTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::SelectionDAGBuilder::ShouldEmitAsBranches(), ShrinkLoadReplaceStoreWithStore(), simplifyDivRem(), llvm::TargetLowering::SimplifySetCC(), llvm::TargetLowering::softenSetCCOperands(), splitStores(), truncateVectorWithPACK(), tryFormConcatFromShuffle(), tryToElideArgumentCopy(), UnpackFromArgumentSlot(), llvm::TargetLowering::verifyReturnAddressArgumentIsConstant(), llvm::SelectionDAGBuilder::visitBitTestCase(), llvm::SelectionDAGBuilder::visitBitTestHeader(), llvm::SelectionDAGBuilder::visitJumpTableHeader(), llvm::SelectionDAGBuilder::visitSPDescriptorParent(), llvm::SelectionDAGBuilder::visitSwitchCase(), and XFormVExtractWithShuffleIntoLoad().

◆ getCopyFromReg() [1/2]

SDValue llvm::SelectionDAG::getCopyFromReg ( SDValue  Chain,
const SDLoc dl,
unsigned  Reg,
EVT  VT 
)
inline

Definition at line 683 of file SelectionDAG.h.

References llvm::ISD::CopyFromReg, and llvm::MVT::Other.

Referenced by llvm::analyzeArguments(), AnalyzeReturnValues(), llvm::AVRDAGToDAGISel::select< ISD::BRIND >(), llvm::AVRDAGToDAGISel::select< ISD::LOAD >(), CallingConvSupported(), CC_Lanai32_VarArg(), llvm::AArch64TargetLowering::CCAssignFnForReturn(), llvm::ARMTargetLowering::CCAssignFnForReturn(), llvm::AMDGPUTargetLowering::CreateLiveInRegister(), EnsureStackAlignment(), findUnwindDestinations(), getAbsolute(), llvm::RegsForValue::getCopyFromRegs(), getDivRemArgList(), llvm::HexagonTargetLowering::GetDynamicTLSAddr(), getExtendedControlRegister(), getFRAMEADDR(), llvm::ARMTargetLowering::getJumpTableEncoding(), getMOVL(), llvm::MipsTargetLowering::getOpndList(), getReadPerformanceCounter(), getReadTimeStampCounter(), llvm::ARCTargetLowering::getTargetNodeName(), GetTLSADDR(), getUnderlyingArgReg(), getv64i1Argument(), hasOnlySelectUsers(), isADDADDMUL(), llvm::ARCTargetLowering::isLegalAddressingMode(), llvm::PPCTargetLowering::isLegalAddressingMode(), llvm::SelectionDAGISel::IsLegalToFold(), llvm::ARMTargetLowering::isReadOnly(), isSortedByValueNo(), llvm::SITargetLowering::isTypeDesirableForOp(), isXor1OfSetCC(), llvm::HexagonTargetLowering::LowerCall(), llvm::SITargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), lowerCallResult(), llvm::HexagonTargetLowering::LowerCallResult(), llvm::SITargetLowering::LowerCallResult(), LowerCallResult(), LowerCMP_SWAP(), llvm::LanaiTargetLowering::LowerDYNAMIC_STACKALLOC(), LowerDYNAMIC_STACKALLOC(), lowerFCOPYSIGN64(), llvm::R600TargetLowering::LowerFormalArguments(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::SITargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerFormalArguments_64(), llvm::LanaiTargetLowering::LowerFRAMEADDR(), llvm::MSP430TargetLowering::LowerFRAMEADDR(), llvm::HexagonTargetLowering::LowerFRAMEADDR(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), LowerINTRINSIC_W_CHAIN(), llvm::BPFTargetLowering::LowerOperation(), llvm::RISCVTargetLowering::LowerOperation(), lowerRegToMasks(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::LanaiTargetLowering::LowerRETURNADDR(), llvm::HexagonTargetLowering::LowerRETURNADDR(), LowerRETURNADDR(), llvm::MSP430TargetLowering::LowerSETCC(), LowerToTLSExecModel(), llvm::HexagonTargetLowering::LowerToTLSInitialExecModel(), llvm::HexagonTargetLowering::LowerToTLSLocalExecModel(), LowerVASTART(), LowerVectorINT_TO_FP(), mayTailCallThisCC(), llvm::X86TargetLowering::needsFixedCatchObjects(), parsePhysicalReg(), Passv64i1ArgInRegs(), performDivRemCombine(), PrepareCall(), recoverFramePointer(), llvm::X86TargetLowering::ReplaceNodeResults(), replaceZeroVectorStore(), llvm::HexagonDAGToDAGISel::SelectFrameIndex(), llvm::AVRDAGToDAGISel::SelectInlineAsmMemoryOperand(), UnpackFromArgumentSlot(), llvm::SelectionDAGBuilder::visitBitTestCase(), and llvm::SelectionDAGBuilder::visitJumpTable().

◆ getCopyFromReg() [2/2]

SDValue llvm::SelectionDAG::getCopyFromReg ( SDValue  Chain,
const SDLoc dl,
unsigned  Reg,
EVT  VT,
SDValue  Glue 
)
inline

◆ getCopyToReg() [1/3]

SDValue llvm::SelectionDAG::getCopyToReg ( SDValue  Chain,
const SDLoc dl,
unsigned  Reg,
SDValue  N 
)
inline

Definition at line 657 of file SelectionDAG.h.

References llvm::ISD::CopyToReg, llvm::SDValue::getValueType(), and llvm::MVT::Other.

Referenced by llvm::analyzeArguments(), AnalyzeReturnValues(), llvm::AVRDAGToDAGISel::select< AVRISD::CALL >(), llvm::AVRDAGToDAGISel::select< ISD::BRIND >(), llvm::AVRDAGToDAGISel::select< ISD::LOAD >(), CallingConvSupported(), CC_Lanai32_VarArg(), llvm::ARMTargetLowering::CCAssignFnForReturn(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(), findUser(), getAbsolute(), llvm::RegsForValue::getCopyToRegs(), getDivRemArgList(), getExtendedControlRegister(), llvm::ARMTargetLowering::getJumpTableEncoding(), getMOVL(), llvm::MipsTargetLowering::getOpndList(), getReadPerformanceCounter(), llvm::ARCTargetLowering::getTargetNodeName(), hasOnlySelectUsers(), isADDADDMUL(), llvm::SelectionDAGISel::IsLegalToFold(), isSortedByValueNo(), isXor1OfSetCC(), llvm::SITargetLowering::legalizeTargetIndependentNode(), llvm::HexagonTargetLowering::LowerCall(), llvm::SITargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), lowerCallResult(), llvm::HexagonTargetLowering::LowerCallResult(), LowerCallResult(), llvm::SelectionDAGBuilder::LowerCallTo(), LowerCMP_SWAP(), llvm::LanaiTargetLowering::LowerDYNAMIC_STACKALLOC(), LowerDYNAMIC_STACKALLOC(), llvm::HexagonTargetLowering::LowerEH_RETURN(), lowerFCOPYSIGN64(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), LowerInterruptReturn(), llvm::RISCVTargetLowering::LowerOperation(), llvm::BPFTargetLowering::LowerOperation(), llvm::HexagonTargetLowering::LowerReturn(), llvm::SITargetLowering::LowerReturn(), llvm::SystemZTargetLowering::LowerReturn(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::SparcTargetLowering::LowerReturn_64(), LowerSETCCE(), llvm::HexagonTargetLowering::LowerToTLSGeneralDynamicModel(), LowerToTLSGeneralDynamicModel32(), LowerToTLSLocalDynamicModel(), mayTailCallThisCC(), llvm::X86TargetLowering::needsFixedCatchObjects(), Passv64i1ArgInRegs(), llvm::SITargetLowering::PostISelFolding(), PrepareCall(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::AVRDAGToDAGISel::SelectInlineAsmMemoryOperand(), UnpackFromArgumentSlot(), llvm::SelectionDAGBuilder::visitBitTestHeader(), and llvm::SelectionDAGBuilder::visitJumpTableHeader().

◆ getCopyToReg() [2/3]

SDValue llvm::SelectionDAG::getCopyToReg ( SDValue  Chain,
const SDLoc dl,
unsigned  Reg,
SDValue  N,
SDValue  Glue 
)
inline

◆ getCopyToReg() [3/3]

SDValue llvm::SelectionDAG::getCopyToReg ( SDValue  Chain,
const SDLoc dl,
SDValue  Reg,
SDValue  N,
SDValue  Glue 
)
inline

◆ getDataLayout()

const DataLayout& llvm::SelectionDAG::getDataLayout ( ) const
inline

Definition at line 388 of file SelectionDAG.h.

References llvm::MachineFunction::getDataLayout().

Referenced by AddCombineBUILD_VECTORToVPADDL(), AddCombineToVPADD(), AddCombineVUZPToVPADDL(), addShuffleForVecExtend(), addStackMapLiveVars(), llvm::analyzeArguments(), AnalyzeReturnValues(), llvm::AVRDAGToDAGISel::select< ISD::FrameIndex >(), BuildExactSDIV(), llvm::X86TargetLowering::BuildFILD(), buildPCRelGlobalAddress(), llvm::TargetLowering::BuildUDIV(), BuildVectorFromScalar(), calculateByteProvider(), canFoldInAddressingMode(), CC_Lanai32_VarArg(), llvm::AArch64TargetLowering::CCAssignFnForReturn(), llvm::ARMTargetLowering::CCAssignFnForReturn(), combineBitcastvxi1(), combineBVOfVecSExt(), combineExtractVectorElt(), combineFMinNumFMaxNum(), combineInsertSubvector(), combineLoad(), combineShuffleOfSplat(), combineShuffleToVectorExtend(), combineStore(), combineTruncationShuffle(), combineVSelectWithAllOnesOrZeros(), computeKnownBits(), llvm::SelectionDAGBuilder::CopyValueToVirtualRegister(), createBSWAPShuffleMask(), createGPRPairNode(), CreateStackTemporary(), createVirtualRegs(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), llvm::MipsTargetLowering::EmitInstrWithCustomInserter(), EmitKTEST(), emitRemovedIntrinsicError(), llvm::ARMSelectionDAGInfo::EmitSpecializedLibcall(), llvm::HexagonSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::XCoreSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::AArch64SelectionDAGInfo::EmitTargetCodeForMemset(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(), ExpandBITCAST(), expandf64Toi32(), llvm::TargetLowering::expandFP_TO_SINT(), llvm::TargetLowering::expandMUL_LOHI(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), expandVAArg(), expandVACopy(), findUnwindDestinations(), foldBitcastedFPLogic(), foldXorTruncShiftIntoCmp(), generateEquivalentSub(), getAbsolute(), getAddressForMemoryInput(), getBuildPairElt(), getConstant(), getConstantPool(), getCopyFromParts(), getCopyFromPartsVector(), llvm::SelectionDAGBuilder::getCopyFromRegs(), getCopyToParts(), getCopyToPartsVector(), getDivRemArgList(), getEstimate(), getEVTAlignment(), getExpandedMinMaxOps(), GetExponent(), GetFPLibCall(), getFPTernOp(), llvm::SelectionDAGBuilder::getFrameIndexTy(), getGlobalAddress(), llvm::MipsDAGToDAGISel::getGlobalBaseReg(), getIntPtrConstant(), llvm::XCoreTargetLowering::getJumpTableEncoding(), llvm::ARMTargetLowering::getJumpTableEncoding(), getLimitedPrecisionExp2(), getLoadStackGuard(), getMemCmpLoad(), getMemcpy(), getMemcpyLoadsAndStores(), getMemmove(), getMemmoveLoadsAndStores(), getMemset(), getMemsetStringVal(), getMOVL(), getNextIntArgReg(), llvm::MipsTargetLowering::getOpndList(), llvm::X86TargetLowering::getPICJumpTableRelocBase(), llvm::PPCTargetLowering::getPICJumpTableRelocBase(), llvm::TargetLowering::getPICJumpTableRelocBase(), llvm::PPCTargetLowering::getPICJumpTableRelocBaseExpr(), getPPCf128HiElementSelector(), llvm::X86TargetLowering::getReturnAddressFrameIndex(), llvm::AVRTargetLowering::getSetCCResultType(), getShiftAmountOperand(), llvm::SparcTargetLowering::getSRetArgSize(), llvm::ARCTargetLowering::getTargetNodeName(), getUnderlyingArgReg(), getUniformBase(), llvm::SelectionDAGBuilder::getValueImpl(), getVectorCompareInfo(), llvm::TargetLowering::getVectorElementPointer(), getVShift(), llvm::PPC::getVSPLTImmediate(), hasExceptionPointerOrCodeUser(), hasOnlySelectUsers(), haveEfficientBuildVectorPattern(), llvm::SelectionDAGBuilder::init(), llvm::intCCToAVRCC(), isADDADDMUL(), isBLACompatibleAddress(), isExtendedBUILD_VECTOR(), isNEONModifiedImm(), IsPredicateKnownToFail(), llvm::ARMTargetLowering::isReadOnly(), isSETCCorConvertedSETCC(), IsSmallObject(), isSortedByValueNo(), isTargetConstant(), isTruncateOf(), llvm::SITargetLowering::isTypeDesirableForOp(), isVectorReductionOp(), llvm::PPC::isVMRGEOShuffleMask(), llvm::PPC::isVMRGHShuffleMask(), llvm::PPC::isVMRGLShuffleMask(), llvm::PPC::isVPKUDUMShuffleMask(), llvm::PPC::isVPKUHUMShuffleMask(), llvm::PPC::isVPKUWUMShuffleMask(), llvm::PPC::isVSLDOIShuffleMask(), isWordAligned(), isXor1OfSetCC(), LowerADDC_ADDE_SUBC_SUBE(), LowerADJUST_TRAMPOLINE(), llvm::MSP430TargetLowering::LowerBlockAddress(), llvm::HexagonTargetLowering::LowerBlockAddress(), LowerBUILD_VECTORAsVariablePermute(), lowerBuildVectorAsBroadcast(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), LowerCallResult(), llvm::SelectionDAGBuilder::LowerCallTo(), llvm::TargetLowering::LowerCallTo(), llvm::LanaiTargetLowering::LowerConstantPool(), llvm::AMDGPUTargetLowering::LowerCTLZ_CTTZ(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), llvm::HexagonTargetLowering::LowerEH_RETURN(), LowerExtendedLoad(), llvm::MSP430TargetLowering::LowerExternalSymbol(), llvm::SparcTargetLowering::LowerF128_LibCallArg(), llvm::SparcTargetLowering::LowerF128Compare(), llvm::SparcTargetLowering::LowerF128Op(), LowerF64Op(), llvm::AMDGPUTargetLowering::LowerFCEIL(), llvm::AMDGPUTargetLowering::LowerFFLOOR(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), LowerFPOWI(), llvm::AMDGPUTargetLowering::LowerFRINT(), llvm::AMDGPUTargetLowering::LowerFROUND32_16(), llvm::AMDGPUTargetLowering::LowerFROUND64(), LowerFSINCOS(), llvm::AMDGPUTargetLowering::LowerFTRUNC(), llvm::HexagonTargetLowering::LowerGLOBAL_OFFSET_TABLE(), llvm::LanaiTargetLowering::LowerGlobalAddress(), llvm::MSP430TargetLowering::LowerGlobalAddress(), llvm::AMDGPUTargetLowering::LowerGlobalAddress(), llvm::HexagonTargetLowering::LowerGLOBALADDRESS(), llvm::NVPTXTargetLowering::LowerGlobalAddress(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), LowerINSERT_SUBVECTOR(), llvm::AMDGPUTargetLowering::LowerINT_TO_FP32(), LowerINTRINSIC_W_CHAIN(), llvm::SparcTargetLowering::LowerINTRINSIC_WO_CHAIN(), llvm::LanaiTargetLowering::LowerJumpTable(), llvm::MSP430TargetLowering::LowerJumpTable(), LowerMemOpCallTo(), lowerMSABitClearImm(), LowerMUL(), LowerMUL_LOHI(), LowerMULH(), llvm::R600TargetLowering::LowerOperation(), llvm::RISCVTargetLowering::LowerOperation(), llvm::NVPTXTargetLowering::LowerOperation(), llvm::NVPTXTargetLowering::LowerReturn(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::MSP430TargetLowering::LowerRETURNADDR(), LowerRETURNADDR(), llvm::TargetLowering::LowerToTLSEmulatedModel(), LowerToTLSExecModel(), llvm::HexagonTargetLowering::LowerToTLSGeneralDynamicModel(), llvm::HexagonTargetLowering::LowerToTLSInitialExecModel(), llvm::HexagonTargetLowering::LowerToTLSLocalExecModel(), lowerUINT_TO_FP_vXi32(), llvm::LanaiTargetLowering::LowerVASTART(), llvm::MSP430TargetLowering::LowerVASTART(), LowerVASTART(), LowerVectorINT_TO_FP(), lowerVectorShuffleAsElementInsertion(), LowerWRITE_REGISTER(), llvm::SparcTargetLowering::makeAddress(), llvm::TargetLowering::makeLibCall(), mayTailCallThisCC(), narrowExtractedVectorLoad(), llvm::X86TargetLowering::needsFixedCatchObjects(), parsePhysicalReg(), Passv64i1ArgInRegs(), peekThroughBitcast(), llvm::PPCTargetLowering::PerformDAGCombine(), performMULCombine(), PerformSTORECombine(), PerformVMOVRRDCombine(), PrepareCall(), promoteToConstantPool(), recoverFramePointer(), ReplaceCMP_SWAP_64Results(), ReplaceLoadVector(), llvm::R600TargetLowering::ReplaceNodeResults(), llvm::PPCTargetLowering::ReplaceNodeResults(), llvm::TargetLowering::scalarizeVectorStore(), llvm::AVRDAGToDAGISel::SelectAddr(), llvm::PPCTargetLowering::SelectAddressRegImm(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::AVRDAGToDAGISel::selectIndexedLoad(), llvm::AVRDAGToDAGISel::SelectInlineAsmMemoryOperand(), shouldGuaranteeTCO(), ShrinkLoadReplaceStoreWithStore(), llvm::TargetLowering::SimplifyDemandedBits(), simplifyDivRem(), llvm::TargetLowering::SimplifySetCC(), SkipExtensionForVMULL(), llvm::TargetLowering::softenSetCCOperands(), tryToElideArgumentCopy(), UnpackFromArgumentSlot(), llvm::SelectionDAGBuilder::visitBitTestCase(), llvm::SelectionDAGBuilder::visitBitTestHeader(), llvm::SelectionDAGBuilder::visitJumpTable(), llvm::SelectionDAGBuilder::visitJumpTableHeader(), llvm::SelectionDAGBuilder::visitSPDescriptorParent(), WinDBZCheckDenominator(), and XFormVExtractWithShuffleIntoLoad().

◆ getDbgValue()

SDDbgValue * SelectionDAG::getDbgValue ( DIVariable Var,
DIExpression Expr,
SDNode N,
unsigned  R,
bool  IsIndirect,
const DebugLoc DL,
unsigned  O 
)

Creates a SDDbgValue node.

getDbgValue - Creates a SDDbgValue node.

SDNode

Definition at line 7000 of file SelectionDAG.cpp.

References assert(), and llvm::SDDbgInfo::getAlloc().

Referenced by getUnderlyingArgReg(), salvageDebugInfo(), and transferDbgValues().

◆ GetDbgValues()

ArrayRef<SDDbgValue*> llvm::SelectionDAG::GetDbgValues ( const SDNode SD)
inline

Get the debug values which reference the given SDNode.

Definition at line 1279 of file SelectionDAG.h.

References llvm::SDDbgInfo::getSDDbgValues().

Referenced by ProcessSDDbgValues(), salvageDebugInfo(), and transferDbgValues().

◆ GetDemandedBits()

SDValue SelectionDAG::GetDemandedBits ( SDValue  V,
const APInt Mask 
)

See if the specified operand can be simplified with the knowledge that only the bits specified by Mask are used.

If so, return the simpler operand, otherwise return a null SDValue.

(This exists alongside SimplifyDemandedBits because GetDemandedBits can simplify nodes with multiple uses more aggressively.)

Definition at line 1981 of file SelectionDAG.cpp.

References llvm::ISD::AND, llvm::ISD::ANY_EXTEND, assert(), llvm::ISD::Constant, llvm::APInt::getActiveBits(), llvm::ConstantSDNode::getAPIntValue(), llvm::APInt::getBitWidth(), getConstant(), llvm::SDValue::getNode(), getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getScalarValueSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::hasOneUse(), llvm::isConstOrConstSplat(), llvm::APInt::isSubsetOf(), llvm::BitmaskEnumDetail::Mask(), MaskedValueIsZero(), llvm::ISD::OR, llvm::ISD::SRL, llvm::APInt::trunc(), and llvm::ISD::XOR.

Referenced by combineBT(), isTruncateOf(), and peekThroughBitcast().

◆ getEHLabel()

SDValue SelectionDAG::getEHLabel ( const SDLoc dl,
SDValue  Root,
MCSymbol Label 
)

Definition at line 1682 of file SelectionDAG.cpp.

References llvm::ISD::EH_LABEL, and getLabelNode().

Referenced by llvm::SelectionDAGBuilder::lowerInvokable().

◆ getEntryNode()

SDValue llvm::SelectionDAG::getEntryNode ( ) const
inline

Return the token chain corresponding to the entry of the function.

Definition at line 446 of file SelectionDAG.h.

Referenced by llvm::AMDGPUTargetLowering::addTokenForArgument(), AnalyzeReturnValues(), llvm::AVRDAGToDAGISel::select< ISD::BRIND >(), llvm::X86TargetLowering::BuildFILD(), buildPCRelGlobalAddress(), CallingConvSupported(), CC_Lanai32_VarArg(), llvm::ARMTargetLowering::CCAssignFnForReturn(), clear(), combineExtractVectorElt(), combineShuffleOfSplat(), llvm::SITargetLowering::copyToM0(), llvm::SelectionDAGBuilder::CopyValueToVirtualRegister(), llvm::AMDGPUTargetLowering::CreateLiveInRegister(), llvm::AMDGPUTargetLowering::CreateLiveInRegisterRaw(), llvm::MipsTargetLowering::EmitInstrWithCustomInserter(), emitRemovedIntrinsicError(), findBaseOffset(), findUnwindDestinations(), getAbsolute(), llvm::MipsTargetLowering::getAddrLocal(), llvm::SelectionDAGBuilder::getCopyFromRegs(), getDivRemArgList(), getExpandedMinMaxOps(), getFLUSHW(), getFPTernOp(), getFRAMEADDR(), getInputChainForNode(), llvm::ARMTargetLowering::getJumpTableEncoding(), getMemCmpLoad(), getMOVL(), llvm::PPCTargetLowering::getPICJumpTableRelocBaseExpr(), llvm::AVRTargetLowering::getSetCCResultType(), getStackArgumentTokenFactor(), getUnderlyingArgReg(), getUniformBase(), llvm::SelectionDAGBuilder::getValueImpl(), getVectorCompareInfo(), getZeroVector(), hasOnlySelectUsers(), haveEfficientBuildVectorPattern(), isADDADDMUL(), llvm::ARCTargetLowering::isLegalAddressingMode(), llvm::PPCTargetLowering::isLegalAddressingMode(), llvm::ARMTargetLowering::isReadOnly(), IsSmallObject(), isSortedByValueNo(), llvm::SITargetLowering::isTypeDesirableForOp(), llvm::AMDGPUTargetLowering::loadStackInputValue(), LowerADDC_ADDE_SUBC_SUBE(), LowerADJUST_TRAMPOLINE(), LowerBUILD_VECTORAsVariablePermute(), lowerBuildVectorAsBroadcast(), llvm::SparcTargetLowering::LowerF128Compare(), llvm::SparcTargetLowering::LowerF128Op(), lowerFCOPYSIGN64(), llvm::SITargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), LowerFPOWI(), llvm::LanaiTargetLowering::LowerFRAMEADDR(), llvm::MSP430TargetLowering::LowerFRAMEADDR(), llvm::HexagonTargetLowering::LowerFRAMEADDR(), LowerFSINCOS(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), LowerINSERT_SUBVECTOR(), LowerINTRINSIC_W_CHAIN(), LowerMULH(), llvm::LanaiTargetLowering::LowerRETURNADDR(), llvm::MSP430TargetLowering::LowerRETURNADDR(), llvm::HexagonTargetLowering::LowerRETURNADDR(), LowerRETURNADDR(), llvm::MSP430TargetLowering::LowerSETCC(), LowerSETCCE(), LowerShiftParts(), llvm::TargetLowering::LowerToTLSEmulatedModel(), LowerToTLSExecModel(), llvm::HexagonTargetLowering::LowerToTLSGeneralDynamicModel(), LowerToTLSGeneralDynamicModel32(), LowerToTLSGeneralDynamicModel64(), llvm::HexagonTargetLowering::LowerToTLSInitialExecModel(), LowerToTLSLocalDynamicModel(), llvm::HexagonTargetLowering::LowerToTLSLocalExecModel(), lowerUINT_TO_FP_vXi32(), llvm::AMDGPUTargetLowering::lowerUnhandledCall(), LowerVectorINT_TO_FP(), llvm::SparcTargetLowering::makeAddress(), llvm::TargetLowering::makeLibCall(), mayTailCallThisCC(), llvm::X86TargetLowering::needsFixedCatchObjects(), performDivRemCombine(), llvm::SITargetLowering::PostISelFolding(), PrepareCall(), recoverFramePointer(), llvm::R600TargetLowering::ReplaceNodeResults(), replaceZeroVectorStore(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::HexagonDAGToDAGISel::SelectFrameIndex(), UnpackFromArgumentSlot(), llvm::SelectionDAGBuilder::visitBitTestCase(), llvm::SelectionDAGBuilder::visitSPDescriptorParent(), and WinDBZCheckDenominator().

◆ getEVTAlignment()

unsigned SelectionDAG::getEVTAlignment ( EVT  MemoryVT) const

◆ getExternalSymbol() [1/2]

SDValue SelectionDAG::getExternalSymbol ( const char Sym,
EVT  VT 
)

◆ getExternalSymbol() [2/2]

SDValue llvm::SelectionDAG::getExternalSymbol ( const char Sym,
const SDLoc dl,
EVT  VT 
)

◆ getExtLoad() [1/2]

SDValue SelectionDAG::getExtLoad ( ISD::LoadExtType  ExtType,
const SDLoc dl,
EVT  VT,
SDValue  Chain,
SDValue  Ptr,
MachinePointerInfo  PtrInfo,
EVT  MemVT,
unsigned  Alignment = 0,
MachineMemOperand::Flags  MMOFlags = MachineMemOperand::MONone,
const AAMDNodes AAInfo = AAMDNodes() 
)

◆ getExtLoad() [2/2]

SDValue SelectionDAG::getExtLoad ( ISD::LoadExtType  ExtType,
const SDLoc dl,
EVT  VT,
SDValue  Chain,
SDValue  Ptr,
EVT  MemVT,
MachineMemOperand MMO 
)

◆ getFPExtendOrRound()

SDValue SelectionDAG::getFPExtendOrRound ( SDValue  Op,
const SDLoc DL,
EVT  VT 
)

Convert Op, which must be of float type, to the float type VT, by either extending or rounding (by truncation).

Definition at line 993 of file SelectionDAG.cpp.

References llvm::EVT::bitsGT(), llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, getIntPtrConstant(), getNode(), and llvm::SDValue::getValueType().

Referenced by getCopyFromPartsVector().

◆ getFrameIndex()

SDValue SelectionDAG::getFrameIndex ( int  FI,
EVT  VT,
bool  isTarget = false 
)

Definition at line 1294 of file SelectionDAG.cpp.

References llvm::FoldingSetNodeID::AddInteger(), AddNodeIDNode(), E, llvm::ISD::FrameIndex, getVTList(), llvm::None, and llvm::ISD::TargetFrameIndex.

Referenced by llvm::StatepointLoweringState::allocateStackSlot(), llvm::analyzeArguments(), AnalyzeReturnValues(), llvm::X86TargetLowering::BuildFILD(), CalculateTailCallArgDest(), CallingConvSupported(), CC_Lanai32_VarArg(), llvm::AArch64TargetLowering::CCAssignFnForReturn(), CreateStackTemporary(), llvm::MipsTargetLowering::EmitInstrWithCustomInserter(), EmitTailCallStoreFPAndRetAddr(), EmitTailCallStoreRetAddr(), EnsureStackAlignment(), getAbsolute(), getAddressForMemoryInput(), getMOVL(), getNextIntArgReg(), llvm::PPCTargetLowering::getPICJumpTableRelocBaseExpr(), llvm::MSP430TargetLowering::getReturnAddressFrameIndex(), llvm::X86TargetLowering::getReturnAddressFrameIndex(), getUnderlyingArgReg(), llvm::SelectionDAGBuilder::getValueImpl(), getVectorCompareInfo(), haveEfficientBuildVectorPattern(), llvm::intCCToAVRCC(), isADDADDMUL(), isSortedByValueNo(), llvm::SITargetLowering::isTypeDesirableForOp(), isXor1OfSetCC(), llvm::AMDGPUTargetLowering::loadStackInputValue(), LowerADDC_ADDE_SUBC_SUBE(), LowerADJUST_TRAMPOLINE(), llvm::SITargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), lowerCallResult(), LowerCallResult(), llvm::TargetLowering::LowerCallTo(), llvm::SparcTargetLowering::LowerF128_LibCallArg(), llvm::SparcTargetLowering::LowerF128Op(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerFormalArguments_64(), LowerINTRINSIC_W_CHAIN(), LowerShiftParts(), llvm::MipsTargetLowering::lowerSTORE(), lowerUINT_TO_FP_vXi32(), llvm::LanaiTargetLowering::LowerVASTART(), llvm::MSP430TargetLowering::LowerVASTART(), llvm::HexagonTargetLowering::LowerVASTART(), LowerVASTART(), mayTailCallThisCC(), parsePhysicalReg(), PrepareCall(), shouldGuaranteeTCO(), UnpackFromArgumentSlot(), and llvm::SelectionDAGBuilder::visitSPDescriptorParent().

◆ getFrameIndexDbgValue()

SDDbgValue * SelectionDAG::getFrameIndexDbgValue ( DIVariable Var,
DIExpression Expr,
unsigned  FI,
const DebugLoc DL,
unsigned  O 
)

Creates a FrameIndex SDDbgValue node.

FrameIndex.

Definition at line 7020 of file SelectionDAG.cpp.

References assert(), and llvm::SDDbgInfo::getAlloc().

Referenced by getUnderlyingArgReg().

◆ getGLOBAL_OFFSET_TABLE()

SDValue llvm::SelectionDAG::getGLOBAL_OFFSET_TABLE ( EVT  VT)
inline

◆ getGlobalAddress()

SDValue SelectionDAG::getGlobalAddress ( const GlobalValue GV,
const SDLoc DL,
EVT  VT,
int64_t  offset = 0,
bool  isTargetGA = false,
unsigned char  TargetFlags = 0 
)

◆ getGraphAttrs()

const std::string SelectionDAG::getGraphAttrs ( const SDNode N) const

Get graph attributes for a node.

getGraphAttrs - Get graph attributes for a node.

(eg. "color=red".) Used from getNodeAttributes.

Definition at line 196 of file SelectionDAGPrinter.cpp.

References llvm::errs(), and I.

Referenced by llvm::DOTGraphTraits< SelectionDAG * >::getNodeAttributes().

◆ getIndexedLoad()

SDValue SelectionDAG::getIndexedLoad ( SDValue  OrigLoad,
const SDLoc dl,
SDValue  Base,
SDValue  Offset,
ISD::MemIndexedMode  AM 
)

◆ getIndexedStore()

SDValue SelectionDAG::getIndexedStore ( SDValue  OrigStoe,
const SDLoc dl,
SDValue  Base,
SDValue  Offset,
ISD::MemIndexedMode  AM 
)

◆ getIntPtrConstant()

SDValue SelectionDAG::getIntPtrConstant ( uint64_t  Val,
const SDLoc DL,
bool  isTarget = false 
)

Definition at line 1201 of file SelectionDAG.cpp.

References getConstant(), getDataLayout(), and llvm::TargetLoweringBase::getPointerTy().

Referenced by addStackMapLiveVars(), llvm::analyzeArguments(), AnalyzeReturnValues(), llvm::X86TargetLowering::BuildFILD(), buildFromShuffleMostly(), CallingConvSupported(), CC_Lanai32_VarArg(), llvm::ARMTargetLowering::CCAssignFnForReturn(), combineBVOfVecSExt(), combineCompareEqual(), combineExtractWithShuffle(), combineInsertSubvector(), combineLoopSADPattern(), combineShuffleOfSplat(), combineStore(), combineToExtendVectorInReg(), combineVectorTruncation(), combineVectorTruncationWithPACKUS(), combineVSZext(), ConvertI1VectorToInteger(), llvm::MipsTargetLowering::EmitInstrWithCustomInserter(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(), ExtendToType(), extractSubVector(), findUnwindDestinations(), foldBitcastedFPLogic(), FoldIntToFPToInt(), getAbsolute(), getCopyToParts(), getExpandedMinMaxOps(), getFPExtendOrRound(), GetFPLibCall(), getFRAMEADDR(), llvm::ARMTargetLowering::getJumpTableEncoding(), getMaskNode(), getMOVL(), getNextIntArgReg(), llvm::MipsTargetLowering::getOpndList(), getParamsForOneTrueMaskedElt(), GetPromotionOpcode(), llvm::X86TargetLowering::getRegisterByName(), llvm::ARCTargetLowering::getTargetNodeName(), insert1BitVector(), insertSubVector(), llvm::intCCToAVRCC(), isADDADDMUL(), isSortedByValueNo(), isTruncWithZeroHighBitsInput(), isXor1OfSetCC(), LowerADDC_ADDE_SUBC_SUBE(), LowerBITCAST(), LowerBITREVERSE_XOP(), LowerBUILD_VECTORAsVariablePermute(), LowerBuildVectorAsInsert(), LowerBuildVectorv16i8(), LowerBuildVectorv4x32(), llvm::HexagonTargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), LowerCONCAT_VECTORS(), LowerCONCAT_VECTORSvXi1(), lowerCTPOP16BitElements(), lowerCTPOP32BitElements(), llvm::HexagonTargetLowering::LowerEH_RETURN(), LowerExtended1BitVectorLoad(), LowerExtendedLoad(), LowerEXTRACT_VECTOR_ELT_SSE4(), LowerFABSorFNEG(), LowerFCOPYSIGN(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::LanaiTargetLowering::LowerFRAMEADDR(), LowerFSINCOS(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), lowerI128ToGR128(), LowerMGATHER(), LowerMLOAD(), LowerMULH(), llvm::NVPTXTargetLowering::LowerOperation(), lowerRegToMasks(), llvm::LanaiTargetLowering::LowerRETURNADDR(), LowerRETURNADDR(), LowerScalarVariableShift(), LowerSDIV(), llvm::AMDGPUTargetLowering::LowerSINT_TO_FP(), LowerToTLSExecModel(), LowerTruncateVecI1(), LowerTruncatingStore(), LowerUDIV(), llvm::AMDGPUTargetLowering::LowerUINT_TO_FP(), lowerUINT_TO_FP_vXi32(), LowerUMULO_SMULO(), lowerV2X128VectorShuffle(), lowerV4X128VectorShuffle(), LowerVAARG(), LowerVACOPY(), LowerVASTART(), LowerVectorINT_TO_FP(), lowerVectorShuffleAsBroadcast(), lowerVectorShuffleWithUndefHalf(), mayTailCallThisCC(), llvm::X86TargetLowering::needsFixedCatchObjects(), parsePhysicalReg(), llvm::PPCTargetLowering::PerformDAGCombine(), performMADD_MSUBCombine(), PerformSTORECombine(), PrepareCall(), PrepareTailCall(), recoverFramePointer(), reduceVMULWidth(), ReplaceLoadVector(), llvm::PPCTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), shouldGuaranteeTCO(), and splitAndLowerVectorShuffle().

◆ getJumpTable()

SDValue SelectionDAG::getJumpTable ( int  JTI,
EVT  VT,
bool  isTarget = false,
unsigned char  TargetFlags = 0 
)

◆ getLabelNode()

SDValue SelectionDAG::getLabelNode ( unsigned  Opcode,
const SDLoc dl,
SDValue  Root,
MCSymbol Label 
)

◆ getLoad() [1/4]

SDValue SelectionDAG::getLoad ( EVT  VT,
const SDLoc dl,
SDValue  Chain,
SDValue  Ptr,
MachinePointerInfo  PtrInfo,
unsigned  Alignment = 0,
MachineMemOperand::Flags  MMOFlags = MachineMemOperand::MONone,
const AAMDNodes AAInfo = AAMDNodes(),
const MDNode Ranges = nullptr 
)

Loads are not normal binary operators: their result type is not determined by their operands, and they produce a value AND a token chain.

This function will set the MOLoad flag on MMOFlags, but you can set it if you want. The MOStore flag must not be set.

Definition at line 5927 of file SelectionDAG.cpp.

References getUNDEF(), llvm::SDValue::getValueType(), llvm::ISD::NON_EXTLOAD, llvm::RegState::Undef, and llvm::ISD::UNINDEXED.

Referenced by llvm::analyzeArguments(), AnalyzeReturnValues(), bitcastf32Toi32(), llvm::X86TargetLowering::BuildFILD(), buildPCRelGlobalAddress(), BuildVectorFromScalar(), calculateByteProvider(), CalculateTailCallArgDest(), canFoldInAddressingMode(), CC_Lanai32_VarArg(), llvm::ARMTargetLowering::CCAssignFnForReturn(), combineBVOfConsecutiveLoads(), combineExtractVectorElt(), combineLoad(), combineMaskedLoadConstantMask(), combineShuffleOfSplat(), combineStore(), ConstantAddressBlock(), EltsFromConsecutiveLoads(), llvm::MipsSETargetLowering::EmitInstrWithCustomInserter(), llvm::MipsTargetLowering::EmitInstrWithCustomInserter(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(), EnsureStackAlignment(), expandf64Toi32(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), expandVAArg(), expandVACopy(), findUser(), foldBitcastedFPLogic(), getAbsolute(), llvm::MipsTargetLowering::getAddrGlobal(), llvm::MipsTargetLowering::getAddrGlobalLargeGOT(), llvm::MipsTargetLowering::getAddrLocal(), getBuildPairElt(), getExpandedMinMaxOps(), getExtLoad(), GetFPLibCall(), getFRAMEADDR(), getIndexedLoad(), llvm::XCoreTargetLowering::getJumpTableEncoding(), llvm::ARMTargetLowering::getJumpTableEncoding(), getLoad(), getMemCmpLoad(), getMemmoveLoadsAndStores(), getMOVL(), llvm::PPCTargetLowering::getPICJumpTableRelocBaseExpr(), GetPromotionOpcode(), getUnderlyingArgReg(), getVectorCompareInfo(), hasOnlySelectUsers(), isADDADDMUL(), llvm::PPCTargetLowering::isLegalAddressingMode(), llvm::ARMTargetLowering::isReadOnly(), IsSmallObject(), isSortedByValueNo(), isTruncateOf(), llvm::SITargetLowering::isTypeDesirableForOp(), isXor1OfSetCC(), llvm::AMDGPUTargetLowering::loadStackInputValue(), LowerADDC_ADDE_SUBC_SUBE(), LowerADJUST_TRAMPOLINE(), LowerAsSplatVectorLoad(), LowerBUILD_VECTORAsVariablePermute(), lowerBuildVectorAsBroadcast(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_64(), lowerCallResult(), LowerCallResult(), llvm::TargetLowering::LowerCallTo(), LowerExtended1BitVectorLoad(), LowerExtendedLoad(), LowerF128Load(), llvm::SparcTargetLowering::LowerF128Op(), llvm::R600TargetLowering::LowerFormalArguments(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerFormalArguments_64(), llvm::LanaiTargetLowering::LowerFRAMEADDR(), llvm::MSP430TargetLowering::LowerFRAMEADDR(), llvm::HexagonTargetLowering::LowerFRAMEADDR(), LowerINSERT_SUBVECTOR(), LowerINTRINSIC_W_CHAIN(), lowerMSALoadIntr(), llvm::NVPTXTargetLowering::LowerOperation(), llvm::LanaiTargetLowering::LowerRETURNADDR(), llvm::MSP430TargetLowering::LowerRETURNADDR(), llvm::HexagonTargetLowering::LowerRETURNADDR(), LowerRETURNADDR(), LowerToTLSExecModel(), llvm::HexagonTargetLowering::LowerToTLSInitialExecModel(), LowerTruncateVecI1(), lowerUINT_TO_FP_vXi32(), LowerVAARG(), LowerVASTART(), LowerVectorINT_TO_FP(), lowerVectorShuffleAsBroadcast(), llvm::SparcTargetLowering::makeAddress(), mayTailCallThisCC(), narrowExtractedVectorLoad(), parsePhysicalReg(), peekThroughBitcast(), llvm::PPCTargetLowering::PerformDAGCombine(), performIntToFpCombine(), llvm::AMDGPUTargetLowering::performLoadCombine(), PrepareCall(), reduceMaskedLoadToScalarLoad(), llvm::R600TargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), shouldGuaranteeTCO(), ShrinkLoadReplaceStoreWithStore(), simplifyDivRem(), llvm::TargetLowering::SimplifySetCC(), SkipLoadExtensionForVMULL(), UnpackFromArgumentSlot(), and llvm::SelectionDAGBuilder::visitSPDescriptorParent().

◆ getLoad() [2/4]

SDValue SelectionDAG::getLoad ( EVT  VT,
const SDLoc dl,
SDValue  Chain,
SDValue  Ptr,
MachineMemOperand MMO 
)

◆ getLoad() [3/4]

SDValue SelectionDAG::getLoad ( ISD::MemIndexedMode  AM,
ISD::LoadExtType  ExtType,
EVT  VT,
const SDLoc dl,
SDValue  Chain,
SDValue  Ptr,
SDValue  Offset,
MachinePointerInfo  PtrInfo,
EVT  MemVT,
unsigned  Alignment = 0,
MachineMemOperand::Flags  MMOFlags = MachineMemOperand::MONone,
const AAMDNodes AAInfo = AAMDNodes(),
const MDNode Ranges = nullptr 
)

◆ getLoad() [4/4]

SDValue SelectionDAG::getLoad ( ISD::MemIndexedMode  AM,
ISD::LoadExtType  ExtType,
EVT  VT,
const SDLoc dl,
SDValue  Chain,
SDValue  Ptr,
SDValue  Offset,
EVT  MemVT,
MachineMemOperand MMO 
)

◆ getLogicalNOT()

SDValue SelectionDAG::getLogicalNOT ( const SDLoc DL,
SDValue  Val,
EVT  VT 
)

◆ getMachineFunction()

MachineFunction& llvm::SelectionDAG::getMachineFunction ( ) const
inline

Definition at line 385 of file SelectionDAG.h.

Referenced by llvm::RegsForValue::AddInlineAsmOperands(), llvm::StatepointLoweringState::allocateStackSlot(), llvm::analyzeArguments(), AnalyzeReturnValues(), areCallingConvEligibleForTCO_64SVR4(), llvm::X86TargetLowering::BuildFILD(), llvm::TargetLowering::BuildSDIVPow2(), CalculateTailCallSPDiff(), CallingConvSupported(), llvm::AArch64TargetLowering::canMergeStoresTo(), llvm::X86TargetLowering::canMergeStoresTo(), CC_Lanai32_VarArg(), llvm::AArch64TargetLowering::CCAssignFnForReturn(), llvm::ARMTargetLowering::CCAssignFnForReturn(), combineFMinNumFMaxNum(), combineMul(), combineOr(), combineShuffleOfSplat(), combineStore(), ConstantAddressBlock(), ConvertSelectToConcatVector(), llvm::AMDGPUTargetLowering::CreateLiveInRegister(), CreateStackTemporary(), createVirtualRegs(), llvm::MipsTargetLowering::EmitInstrWithCustomInserter(), EmitKTEST(), emitNonHSAIntrinsicError(), emitRemovedIntrinsicError(), llvm::ARMSelectionDAGInfo::EmitSpecializedLibcall(), EmitTailCallStoreFPAndRetAddr(), EmitTailCallStoreRetAddr(), llvm::HexagonSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::AArch64SelectionDAGInfo::EmitTargetCodeForMemset(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(), EnsureStackAlignment(), llvm::BaseIndexOffset::equalBaseIndex(), errorUnsupported(), expandf64Toi32(), ExpandPowI(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), fail(), findBaseOffset(), llvm::SelectionDAGBuilder::FindMergedConditions(), FindOptimalMemOpLowering(), findUnwindDestinations(), findUser(), fixupFuncForFI(), getAbsolute(), getAddressForMemoryInput(), llvm::MipsTargetLowering::getAddrLocal(), getAtomic(), getAtomicCmpSwap(), llvm::HexagonTargetLowering::GetDynamicTLSAddr(), getExpandedMinMaxOps(), getFPTernOp(), getFRAMEADDR(), llvm::MipsTargetLowering::getGlobalReg(), llvm::DOTGraphTraits< SelectionDAG * >::getGraphName(), llvm::XCoreTargetLowering::getJumpTableEncoding(), llvm::ARMTargetLowering::getJumpTableEncoding(), getLoad(), getLoadStackGuard(), getMemCmpLoad(), getMemcpyLoadsAndStores(), getMemIntrinsicNode(), getMemmoveLoadsAndStores(), getMemsetStores(), getMOVL(), getNextIntArgReg(), llvm::MipsTargetLowering::getOpndList(), llvm::PPCTargetLowering::getPICJumpTableRelocBaseExpr(), llvm::X86TargetLowering::getRegisterByName(), GetRegistersForValue(), llvm::MSP430TargetLowering::getReturnAddressFrameIndex(), llvm::X86TargetLowering::getReturnAddressFrameIndex(), llvm::NVPTXTargetLowering::getSqrtEstimate(), llvm::SparcTargetLowering::getSRetArgSize(), getStore(), llvm::ARCTargetLowering::getTargetNodeName(), GetTLSADDR(), getTOCEntry(), getTruncStore(), getUnderlyingArgReg(), getUniformBase(), getv64i1Argument(), getVectorCompareInfo(), hasOnlySelectUsers(), hasReturnsTwiceAttr(), haveEfficientBuildVectorPattern(), InferPointerInfo(), llvm::intCCToAVRCC(), isADDADDMUL(), isCanonicalized(), isConsecutiveLSLoc(), llvm::HexagonTargetLowering::IsEligibleForTailCallOptimization(), llvm::SITargetLowering::isEligibleForTailCallOptimization(), llvm::TargetLowering::isInTailCallPosition(), llvm::ARCTargetLowering::isLegalAddressingMode(), llvm::PPCTargetLowering::isLegalAddressingMode(), llvm::ARMTargetLowering::isReadOnly(), isSortedByValueNo(), isTargetConstant(), llvm::SITargetLowering::isTypeDesirableForOp(), isXor1OfSetCC(), llvm::SITargetLowering::legalizeTargetIndependentNode(), llvm::AMDGPUTargetLowering::loadStackInputValue(), LowerADDC_ADDE_SUBC_SUBE(), LowerADJUST_TRAMPOLINE(), LowerAsSplatVectorLoad(), lowerAtomicArithWithLOCK(), LowerBUILD_VECTORAsVariablePermute(), lowerBuildVectorAsBroadcast(), llvm::HexagonTargetLowering::LowerCall(), llvm::SITargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), lowerCallResult(), llvm::HexagonTargetLowering::LowerCallResult(), llvm::SITargetLowering::LowerCallResult(), LowerCallResult(), llvm::TargetLowering::LowerCallTo(), llvm::AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(), LowerDYNAMIC_STACKALLOC(), llvm::HexagonTargetLowering::LowerEH_RETURN(), LowerEXTRACT_VECTOR_ELT_SSE4(), llvm::SparcTargetLowering::LowerF128_LibCallArg(), llvm::SparcTargetLowering::LowerF128Op(), lowerFCOPYSIGN64(), llvm::R600TargetLowering::LowerFormalArguments(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::SITargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerFormalArguments_64(), LowerFPOWI(), llvm::LanaiTargetLowering::LowerFRAMEADDR(), llvm::MSP430TargetLowering::LowerFRAMEADDR(), llvm::HexagonTargetLowering::LowerFRAMEADDR(), llvm::AMDGPUTargetLowering::LowerGlobalAddress(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), llvm::HexagonTargetLowering::LowerINLINEASM(), LowerINSERT_SUBVECTOR(), LowerInterruptReturn(), LowerINTRINSIC_W_CHAIN(), llvm::SelectionDAGBuilder::lowerInvokable(), llvm::R600TargetLowering::LowerOperation(), llvm::RISCVTargetLowering::LowerOperation(), llvm::BPFTargetLowering::LowerOperation(), llvm::SITargetLowering::LowerOperation(), llvm::NVPTXTargetLowering::LowerOperation(), lowerRegToMasks(), llvm::HexagonTargetLowering::LowerReturn(), llvm::SITargetLowering::LowerReturn(), llvm::SystemZTargetLowering::LowerReturn(), llvm::NVPTXTargetLowering::LowerReturn(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::SparcTargetLowering::LowerReturn_64(), llvm::LanaiTargetLowering::LowerRETURNADDR(), llvm::MSP430TargetLowering::LowerRETURNADDR(), llvm::HexagonTargetLowering::LowerRETURNADDR(), LowerRETURNADDR(), LowerShiftParts(), llvm::MipsTargetLowering::lowerSTORE(), llvm::TargetLowering::LowerToTLSEmulatedModel(), LowerToTLSExecModel(), LowerToTLSLocalDynamicModel(), lowerUINT_TO_FP_vXi32(), llvm::AMDGPUTargetLowering::lowerUnhandledCall(), LowerVACOPY(), llvm::LanaiTargetLowering::LowerVASTART(), llvm::MSP430TargetLowering::LowerVASTART(), llvm::HexagonTargetLowering::LowerVASTART(), LowerVASTART(), LowerVectorINT_TO_FP(), lowerVectorShuffleAsBroadcast(), LowerWRITE_REGISTER(), llvm::SparcTargetLowering::makeAddress(), MarkEHGuard(), MarkEHRegistrationNode(), MatchingStackOffset(), mayTailCallThisCC(), narrowExtractedVectorLoad(), llvm::X86TargetLowering::needsFixedCatchObjects(), parsePhysicalReg(), Passv64i1ArgInRegs(), peekThroughBitcast(), PerformADDCombineWithOperands(), llvm::PPCTargetLowering::PerformDAGCombine(), performXorCombine(), llvm::SITargetLowering::PostISelFolding(), PrepareCall(), promoteToConstantPool(), recoverFramePointer(), reduceVMULWidth(), ReplaceCMP_SWAP_128Results(), ReplaceCMP_SWAP_64Results(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::TargetLowering::CallLoweringInfo::setLibCallee(), setUsesTOCBasePtr(), shouldGuaranteeTCO(), simplifyDivRem(), spillIncomingStatepointValue(), splitStores(), llvm::AMDGPUTargetLowering::storeStackInputValue(), StoreTailCallArgumentsToStackSlot(), llvm::X86InstrInfo::unfoldMemoryOperand(), UnpackFromArgumentSlot(), and llvm::SelectionDAGBuilder::visitSPDescriptorParent().

◆ getMachineNode() [1/13]

MachineSDNode * SelectionDAG::getMachineNode ( unsigned  Opcode,
const SDLoc dl,
EVT  VT 
)

These are used for target selectors to create a new node with specified return type(s), MachineInstr opcode, and operands.

getMachineNode - These are used for target selectors to create a new node with specified return type(s), MachineInstr opcode, and operands.

Note that getMachineNode returns the resultant node. If there is already a node of the specified opcode and operands, it returns that node instead of the current one.

Definition at line 6845 of file SelectionDAG.cpp.

References getVTList(), and llvm::None.

Referenced by addStackMapLiveVars(), llvm::AVRDAGToDAGISel::select< AVRISD::CALL >(), llvm::AVRDAGToDAGISel::select< ISD::BRIND >(), llvm::AVRDAGToDAGISel::select< ISD::LOAD >(), llvm::AVRDAGToDAGISel::select< ISD::STORE >(), llvm::SITargetLowering::buildRSRC(), buildSMovImm32(), CallingConvSupported(), canLowerToLDG(), llvm::SITargetLowering::copyToM0(), createGPRPairNode(), llvm::HexagonDAGToDAGISel::DetectUseSxtw(), emitRemovedIntrinsicError(), findUser(), getAbsolute(), getExtendedControlRegister(), getLeftShift(), getLoadStackGuard(), getMachineNode(), getPrefetchNode(), getPTXCmpMode(), getScatterNode(), getTargetExtractSubreg(), getTargetInsertSubreg(), getUnderlyingArgReg(), getVectorCompareInfo(), getWmmaLdStOpcode(), isMemOPCandidate(), isPreferredADD(), llvm::SITargetLowering::legalizeTargetIndependentNode(), llvm::HexagonDAGToDAGISel::LoadInstrForLoadIntrinsic(), LowerATOMIC_FENCE(), LowerBITCAST(), LowerF128Load(), LowerF128Store(), LowerF64Op(), llvm::HexagonTargetLowering::LowerFormalArguments(), lowerI128ToGR128(), LowerMGATHER(), llvm::RISCVTargetLowering::LowerOperation(), llvm::SystemZTargetLowering::LowerOperationWrapper(), mayTailCallThisCC(), narrowIfNeeded(), optimizeLogicalImm(), performBitcastCombine(), llvm::R600TargetLowering::PerformDAGCombine(), pickOpcodeForVT(), llvm::SITargetLowering::PostISelFolding(), ReplaceBITCASTResults(), ReplaceCMP_SWAP_128Results(), ReplaceCMP_SWAP_64Results(), llvm::PPCTargetLowering::SelectAddressRegImm(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::HexagonDAGToDAGISel::SelectConstant(), llvm::HexagonDAGToDAGISel::SelectConstantFP(), llvm::HexagonDAGToDAGISel::SelectFrameIndex(), selectI64Imm(), selectI64ImmDirect(), llvm::AVRDAGToDAGISel::selectIndexedLoad(), llvm::HexagonDAGToDAGISel::SelectIndexedLoad(), llvm::HexagonDAGToDAGISel::SelectIndexedStore(), llvm::NVPTXDAGToDAGISel::SelectInlineAsmMemoryOperand(), llvm::HexagonDAGToDAGISel::SelectSHL(), llvm::HexagonDAGToDAGISel::SelectZeroExtend(), SubIdx2Lane(), tryBitfieldInsertOpFromOr(), tryBitfieldInsertOpFromOrAndImm(), llvm::X86InstrInfo::unfoldMemoryOperand(), Widen(), and llvm::SITargetLowering::wrapAddr64Rsrc().

◆ getMachineNode() [2/13]

MachineSDNode * SelectionDAG::getMachineNode ( unsigned  Opcode,
const SDLoc dl,
EVT  VT,
SDValue  Op1 
)

Definition at line 6851 of file SelectionDAG.cpp.

References getMachineNode(), and getVTList().

◆ getMachineNode() [3/13]

MachineSDNode * SelectionDAG::getMachineNode ( unsigned  Opcode,
const SDLoc dl,
EVT  VT,
SDValue  Op1,
SDValue  Op2 
)

Definition at line 6858 of file SelectionDAG.cpp.

References getMachineNode(), and getVTList().

◆ getMachineNode() [4/13]

MachineSDNode * SelectionDAG::getMachineNode ( unsigned  Opcode,
const SDLoc dl,
EVT  VT,
SDValue  Op1,
SDValue  Op2,
SDValue  Op3 
)

Definition at line 6865 of file SelectionDAG.cpp.

References getMachineNode(), and getVTList().

◆ getMachineNode() [5/13]

MachineSDNode * SelectionDAG::getMachineNode ( unsigned  Opcode,
const SDLoc dl,
EVT  VT,
ArrayRef< SDValue Ops 
)

Definition at line 6873 of file SelectionDAG.cpp.

References getMachineNode(), and getVTList().

◆ getMachineNode() [6/13]

MachineSDNode * SelectionDAG::getMachineNode ( unsigned  Opcode,
const SDLoc dl,
EVT  VT1,
EVT  VT2,
SDValue  Op1,
SDValue  Op2 
)

Definition at line 6879 of file SelectionDAG.cpp.

References getMachineNode(), and getVTList().

◆ getMachineNode() [7/13]

MachineSDNode * SelectionDAG::getMachineNode ( unsigned  Opcode,
const SDLoc dl,
EVT  VT1,
EVT  VT2,
SDValue  Op1,
SDValue  Op2,
SDValue  Op3 
)

Definition at line 6887 of file SelectionDAG.cpp.

References getMachineNode(), and getVTList().

◆ getMachineNode() [8/13]

MachineSDNode * SelectionDAG::getMachineNode ( unsigned  Opcode,
const SDLoc dl,
EVT  VT1,
EVT  VT2,
ArrayRef< SDValue Ops 
)

Definition at line 6895 of file SelectionDAG.cpp.

References getMachineNode(), and getVTList().

◆ getMachineNode() [9/13]

MachineSDNode * SelectionDAG::getMachineNode ( unsigned  Opcode,
const SDLoc dl,
EVT  VT1,
EVT  VT2,
EVT  VT3,
SDValue  Op1,
SDValue  Op2 
)

Definition at line 6902 of file SelectionDAG.cpp.

References getMachineNode(), and getVTList().

◆ getMachineNode() [10/13]

MachineSDNode * SelectionDAG::getMachineNode ( unsigned  Opcode,
const SDLoc dl,
EVT  VT1,
EVT  VT2,
EVT  VT3,
SDValue  Op1,
SDValue  Op2,
SDValue  Op3 
)

Definition at line 6910 of file SelectionDAG.cpp.

References getMachineNode(), and getVTList().

◆ getMachineNode() [11/13]

MachineSDNode * SelectionDAG::getMachineNode ( unsigned  Opcode,
const SDLoc dl,
EVT  VT1,
EVT  VT2,
EVT  VT3,
ArrayRef< SDValue Ops 
)

Definition at line 6919 of file SelectionDAG.cpp.

References getMachineNode(), and getVTList().

◆ getMachineNode() [12/13]

MachineSDNode * SelectionDAG::getMachineNode ( unsigned  Opcode,
const SDLoc dl,
ArrayRef< EVT ResultTys,
ArrayRef< SDValue Ops 
)

Definition at line 6926 of file SelectionDAG.cpp.

References getMachineNode(), and getVTList().

◆ getMachineNode() [13/13]

MachineSDNode * SelectionDAG::getMachineNode ( unsigned  Opcode,
const SDLoc dl,
SDVTList  VTs,
ArrayRef< SDValue Ops 
)

◆ getMaskedGather()

SDValue SelectionDAG::getMaskedGather ( SDVTList  VTs,
EVT  VT,
const SDLoc dl,
ArrayRef< SDValue Ops,
MachineMemOperand MMO 
)

◆ getMaskedLoad()

SDValue SelectionDAG::getMaskedLoad ( EVT  VT,
const SDLoc dl,
SDValue  Chain,
SDValue  Ptr,
SDValue  Mask,
SDValue  Src0,
EVT  MemVT,
MachineMemOperand MMO,
ISD::LoadExtType  ExtTy,
bool  IsExpanding = false 
)

◆ getMaskedScatter()

SDValue SelectionDAG::getMaskedScatter ( SDVTList  VTs,
EVT  VT,
const SDLoc dl,
ArrayRef< SDValue Ops,
MachineMemOperand MMO 
)

◆ getMaskedStore()

SDValue SelectionDAG::getMaskedStore ( SDValue  Chain,
const SDLoc dl,
SDValue  Val,
SDValue  Ptr,
SDValue  Mask,
EVT  MemVT,
MachineMemOperand MMO,
bool  IsTruncating = false,
bool  IsCompressing = false 
)

◆ getMCSymbol()

SDValue SelectionDAG::getMCSymbol ( MCSymbol Sym,
EVT  VT 
)

Definition at line 1435 of file SelectionDAG.cpp.

Referenced by getUnderlyingArgReg(), and recoverFramePointer().

◆ getMDNode()

SDValue SelectionDAG::getMDNode ( const MDNode MD)

◆ getMemBasePlusOffset()

SDValue SelectionDAG::getMemBasePlusOffset ( SDValue  Base,
unsigned  Offset,
const SDLoc DL 
)

◆ getMemcpy()

SDValue SelectionDAG::getMemcpy ( SDValue  Chain,
const SDLoc dl,
SDValue  Dst,
SDValue  Src,
SDValue  Size,
unsigned  Align,
bool  isVol,
bool  AlwaysInline,
bool  isTailCall,
MachinePointerInfo  DstPtrInfo,
MachinePointerInfo  SrcPtrInfo 
)

Definition at line 5422 of file SelectionDAG.cpp.

References llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align, llvm::AMDGPU::HSAMD::Kernel::Key::Args, assert(), checkAddrSpaceIsValidForLibcall(), llvm::dyn_cast(), llvm::SelectionDAGTargetInfo::EmitTargetCodeForMemcpy(), llvm::MachinePointerInfo::getAddrSpace(), getContext(), getDataLayout(), getExternalSymbol(), llvm::DataLayout::getIntPtrType(), llvm::TargetLoweringBase::getLibcallCallingConv(), llvm::TargetLoweringBase::getLibcallName(), getMemcpyLoadsAndStores(), llvm::SDValue::getNode(), llvm::TargetLoweringBase::getPointerTy(), llvm::EVT::getTypeForEVT(), llvm::SDValue::getValueType(), llvm::ConstantSDNode::getZExtValue(), llvm::ConstantSDNode::isNullValue(), llvm::TargetLowering::LowerCallTo(), llvm::ARMISD::MEMCPY, llvm::TargetLoweringBase::ArgListEntry::Node, llvm::TargetLowering::CallLoweringInfo::setChain(), llvm::TargetLowering::CallLoweringInfo::setDebugLoc(), llvm::TargetLowering::CallLoweringInfo::setLibCallee(), llvm::TargetLowering::CallLoweringInfo::setTailCall(), llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Size, and llvm::TargetLoweringBase::ArgListEntry::Ty.

Referenced by AnalyzeReturnValues(), CallingConvSupported(), CC_Lanai32_VarArg(), CreateCopyOfByValArgument(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemcpy(), getAbsolute(), getMemCmpLoad(), llvm::PPCTargetLowering::getPICJumpTableRelocBaseExpr(), getUnderlyingArgReg(), llvm::SITargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), lowerCallResult(), LowerCallResult(), LowerVACOPY(), mayTailCallThisCC(), and parsePhysicalReg().

◆ getMemIntrinsicNode() [1/2]

SDValue SelectionDAG::getMemIntrinsicNode ( unsigned  Opcode,
const SDLoc dl,
SDVTList  VTList,
ArrayRef< SDValue Ops,
EVT  MemVT,
MachinePointerInfo  PtrInfo,
unsigned  Align = 0,
bool  Vol = false,
bool  ReadMem = true,
bool  WriteMem = true,
unsigned  Size = 0 
)

Creates a MemIntrinsicNode that may produce a result and takes a list of operands.

Opcode may be INTRINSIC_VOID, INTRINSIC_W_CHAIN, or a target-specific opcode with a value not less than FIRST_TARGET_MEMORY_OPCODE.

Definition at line 5754 of file SelectionDAG.cpp.

References getEVTAlignment(), getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::EVT::getStoreSize(), llvm::MachineMemOperand::MOLoad, llvm::MachineMemOperand::MONone, llvm::MachineMemOperand::MOStore, and llvm::MachineMemOperand::MOVolatile.

Referenced by llvm::X86TargetLowering::BuildFILD(), CombineBaseUpdate(), combineBVOfVecSExt(), CombineVLDDUP(), createLoadLR(), createStoreLR(), EltsFromConsecutiveLoads(), emitRemovedIntrinsicError(), llvm::PPCTargetLowering::expandVSXLoadForLE(), llvm::PPCTargetLowering::expandVSXStoreForLE(), getAbsolute(), getFPTernOp(), llvm::SystemZTargetLowering::getTargetNodeName(), getTOCEntry(), getUnderlyingArgReg(), getUniformBase(), getVectorCompareInfo(), haveEfficientBuildVectorPattern(), isXor1OfSetCC(), LowerADJUST_TRAMPOLINE(), lowerAtomicArithWithLOCK(), llvm::NVPTXTargetLowering::LowerCall(), LowerCMP_SWAP(), llvm::NVPTXTargetLowering::LowerOperation(), llvm::SystemZTargetLowering::LowerOperationWrapper(), llvm::NVPTXTargetLowering::LowerReturn(), lowerUINT_TO_FP_vXi32(), llvm::PPCTargetLowering::PerformDAGCombine(), performNEONPostLDSTCombine(), performPostLD1Combine(), PerformVDUPCombine(), PrepareCall(), ReplaceINTRINSIC_W_CHAIN(), ReplaceLoadVector(), llvm::R600TargetLowering::ReplaceNodeResults(), and llvm::X86TargetLowering::ReplaceNodeResults().

◆ getMemIntrinsicNode() [2/2]

SDValue SelectionDAG::getMemIntrinsicNode ( unsigned  Opcode,
const SDLoc dl,
SDVTList  VTList,
ArrayRef< SDValue Ops,
EVT  MemVT,
MachineMemOperand MMO 
)

◆ getMemmove()

SDValue SelectionDAG::getMemmove ( SDValue  Chain,
const SDLoc dl,
SDValue  Dst,
SDValue  Src,
SDValue  Size,
unsigned  Align,
bool  isVol,
bool  isTailCall,
MachinePointerInfo  DstPtrInfo,
MachinePointerInfo  SrcPtrInfo 
)

◆ getMemset()

SDValue SelectionDAG::getMemset ( SDValue  Chain,
const SDLoc dl,
SDValue  Dst,
SDValue  Src,
SDValue  Size,
unsigned  Align,
bool  isVol,
bool  isTailCall,
MachinePointerInfo  DstPtrInfo 
)

◆ getMergeValues()

SDValue SelectionDAG::getMergeValues ( ArrayRef< SDValue Ops,
const SDLoc dl 
)

Create a MERGE_VALUES node from the given operands.

getMergeValues - Create a MERGE_VALUES node from the given operands.

Definition at line 5743 of file SelectionDAG.cpp.

References getNode(), getVTList(), llvm::ISD::MERGE_VALUES, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::SmallVectorImpl< T >::reserve(), and llvm::ArrayRef< T >::size().

Referenced by ConstantAddressBlock(), ConvertSelectToConcatVector(), llvm::MipsSETargetLowering::EmitInstrWithCustomInserter(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), emitRemovedIntrinsicError(), findUser(), getAbsolute(), getDivRemArgList(), getFPTernOp(), llvm::XCoreTargetLowering::getJumpTableEncoding(), llvm::SelectionDAGBuilder::getValueImpl(), getVectorCompareInfo(), isADDADDMUL(), llvm::SITargetLowering::isTypeDesirableForOp(), isWordAligned(), isXor1OfSetCC(), LowerADDC_ADDE_SUBC_SUBE(), llvm::NVPTXTargetLowering::LowerCall(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), lowerDSPIntr(), llvm::LanaiTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(), LowerDYNAMIC_STACKALLOC(), LowerF128Load(), lowerFCOPYSIGN64(), LowerINTRINSIC_W_CHAIN(), llvm::MipsTargetLowering::lowerLOAD(), LowerMGATHER(), LowerMLOAD(), LowerMUL_LOHI(), llvm::NVPTXTargetLowering::LowerOperation(), llvm::SelectionDAGBuilder::lowerRangeToAssertZExt(), llvm::AMDGPUTargetLowering::LowerSDIVREM(), LowerShiftParts(), llvm::LanaiTargetLowering::LowerSHL_PARTS(), llvm::LanaiTargetLowering::LowerSRL_PARTS(), llvm::AMDGPUTargetLowering::LowerUDIVREM(), lowerUINT_TO_FP_vXi32(), LowerUMULO_SMULO(), mayTailCallThisCC(), llvm::AMDGPUTargetLowering::performLoadCombine(), llvm::AMDGPUTargetLowering::performMulLoHi24Combine(), PrepareCall(), llvm::TargetLowering::scalarizeVectorLoad(), and llvm::AMDGPUTargetLowering::SplitVectorLoad().

◆ getNode() [1/16]

SDValue SelectionDAG::getNode ( unsigned  Opcode,
const SDLoc DL,
EVT  VT,
ArrayRef< SDUse Ops 
)

Gets or creates the specified node.

Definition at line 6246 of file SelectionDAG.cpp.

References llvm::ArrayRef< T >::begin(), llvm::ArrayRef< T >::end(), and llvm::ArrayRef< T >::size().

Referenced by AddCombineBUILD_VECTORToVPADDL(), AddCombineTo64bitMLAL(), AddCombineTo64BitSMLAL16(), AddCombineTo64bitUMAAL(), AddCombineToVPADD(), AddCombineVUZPToVPADDL(), addIPMSequence(), llvm::MipsSETargetLowering::addMSAFloatType(), addRequiredExtensionForVectorMULL(), AddRequiredExtensionForVMULL(), addShuffleForVecExtend(), addStackMapLiveVars(), llvm::AMDGPUTargetLowering::addTokenForArgument(), llvm::analyzeArguments(), AnalyzeReturnValues(), BuildExactSDIV(), llvm::X86TargetLowering::BuildFILD(), buildFromShuffleMostly(), BuildIntrinsicOp(), buildMergeScalars(), buildPCRelGlobalAddress(), buildScalarToVector(), llvm::PPCTargetLowering::BuildSDIVPow2(), llvm::TargetLowering::BuildUDIV(), buildVector(), BuildVectorFromScalar(), BuildVSLDOI(), calculateByteProvider(), CallingConvSupported(), CanCombineFCOPYSIGN_EXTEND_ROUND(), canFoldInAddressingMode(), CC_Lanai32_VarArg(), llvm::AArch64TargetLowering::CCAssignFnForReturn(), llvm::ARMTargetLowering::CCAssignFnForReturn(), checkVSELConstraints(), clampDynamicVectorIndex(), combineAcrossLanesIntrinsic(), combineADC(), combineAdd(), combineAddOrSubToADCOrSBB(), combineAnd(), combineAndMaskToShift(), combineANDXORWithAllOnesIntoANDNP(), CombineBaseUpdate(), combineBasicSADPattern(), combineBitcast(), combineBitcastForMaskedOp(), combineBitcastvxi1(), combineBrCond(), combineBT(), combineBVOfVecSExt(), combineCMov(), combineCompareEqual(), combineConcatVectorOfExtracts(), combineConcatVectorOfScalars(), combineExtractVectorElt(), combineExtractWithShuffle(), combineFaddFsub(), combineFAndFNotToFAndn(), combineFMA(), combineFMADDSUB(), combineFMinFMax(), llvm::AMDGPUTargetLowering::combineFMinMaxLegacy(), combineFMinNumFMaxNum(), combineFneg(), combineGatherScatter(), combineHorizontalPredicateResult(), combineIncDecVector(), combineInsertSubvector(), combineLoad(), combineLogicBlendIntoPBLENDV(), combineLoopMAddPattern(), combineLoopSADPattern(), combineMaskedLoad(), combineMaskedStore(), combineMinNumMaxNum(), combineMul(), combineMulSpecial(), combineOr(), combineOrCmpEqZeroToCtlzSrl(), combineRedundantDWordShuffle(), combineRedundantHalfShuffle(), combineSBB(), combineSelect(), combineSelectAndUse(), combineSelectOfTwoConstants(), combineSetCC(), combineSext(), combineShiftLeft(), combineShiftRightArithmetic(), combineShiftRightLogical(), combineShuffle(), combineShuffleOfConcatUndef(), combineShuffleOfSplat(), combineShuffleToAddSubOrFMAddSub(), combineSignExtendInReg(), combineSIntToFP(), combineStore(), combineSub(), combineSubToSubus(), combineTargetShuffle(), combineTestM(), combineToExtendBoolVectorInReg(), combineToExtendCMOV(), combineToExtendVectorInReg(), combineTruncate(), combineTruncatedArithmetic(), combineTruncateWithUSat(), combineUIntToFP(), combineVectorCompareAndMaskUnaryOp(), combineVectorSizedSetCCEquality(), combineVectorTruncation(), combineVectorTruncationWithPACKSS(), combineVectorTruncationWithPACKUS(), CombineVMOVDRRCandidateWithVecOp(), combineVSelectWithAllOnesOrZeros(), combineVSZext(), combineX86ShuffleChain(), combineZext(), ConstantAddressBlock(), convertBuildVectorCastElt(), ConvertI1VectorToInteger(), convertIntLogicToFPLogic(), convertLocVTToValVT(), ConvertSelectToConcatVector(), convertValVTToLocVT(), llvm::SITargetLowering::copyToM0(), createBSWAPShuffleMask(), createCMovFP(), createFPCmp(), createGPRPairNode(), createLoadLR(), createPSADBW(), createStoreLR(), createVirtualRegs(), detectAVGPattern(), distributeOpThroughSelect(), emitCLC(), EmitCMP(), emitCmp(), emitComparison(), emitConditionalComparison(), llvm::MipsSETargetLowering::EmitInstrWithCustomInserter(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), llvm::MipsTargetLowering::EmitInstrWithCustomInserter(), emitIntrinsicWithChainAndGlue(), emitIntrinsicWithGlue(), EmitKTEST(), emitMemMem(), emitRemovedIntrinsicError(), emitSETCC(), llvm::ARMSelectionDAGInfo::EmitSpecializedLibcall(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemchr(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemset(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcmp(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcpy(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrnlen(), EmitVectorComparison(), EnsureStackAlignment(), Expand64BitShift(), ExpandBITCAST(), ExpandBVWithShuffles(), expandExp(), expandExp2(), expandf64Toi32(), llvm::TargetLowering::expandFP_TO_SINT(), ExpandHorizontalBinOp(), expandLog(), expandLog10(), expandLog2(), llvm::TargetLowering::expandMUL_LOHI(), expandPow(), ExpandPowI(), ExpandREAD_REGISTER(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), expandV4F32ToV2F64(), expandVAArg(), llvm::PPCTargetLowering::expandVSXLoadForLE(), llvm::PPCTargetLowering::expandVSXStoreForLE(), ExtendToType(), ExtendUsesToFormExtLoad(), extractF64Exponent(), extractLOHI(), extractSubVector(), findBaseOffset(), findUnwindDestinations(), findUser(), foldBitcastedFPLogic(), FoldConstantArithmetic(), FoldConstantVectorArithmetic(), foldFreeOpFromSelect(), FoldIntToFPToInt(), foldMaskAndShiftToExtract(), foldMaskAndShiftToScale(), foldMaskedShiftToScaledMask(), foldVectorXorShiftIntoCmp(), foldXorTruncShiftIntoCmp(), genConstMult(), generateEquivalentSub(), GeneratePerfectShuffle(), GenerateTBL(), getAArch64Cmp(), getAArch64XALUOOp(), getAbsolute(), llvm::MipsTargetLowering::getAddrGlobal(), llvm::MipsTargetLowering::getAddrGlobalLargeGOT(), llvm::MipsTargetLowering::getAddrGPRel(), llvm::MipsTargetLowering::getAddrLocal(), llvm::MipsTargetLowering::getAddrNonPIC(), llvm::MipsTargetLowering::getAddrNonPICSym64(), getAnyExtendVectorInReg(), getAnyExtOrTrunc(), getAsCarry(), getAsNonOpaqueConstant(), getBitcast(), getBitTestCondition(), getBoolExtOrTrunc(), getBoundedStrlen(), getBuildVectorSplat(), getCCResult(), getConstant(), llvm::SelectionDAGBuilder::getControlRoot(), getCopyFromParts(), getCopyFromPartsVector(), llvm::RegsForValue::getCopyFromRegs(), getCopyToParts(), getCopyToPartsVector(), llvm::RegsForValue::getCopyToRegs(), getCTPOP16BitCounts(), llvm::DAGTypeLegalizer::getDAG(), GetDemandedBits(), getDivRem8(), getDivRemArgList(), getDUPLANEOp(), llvm::HexagonTargetLowering::GetDynamicTLSAddr(), getEstimate(), getEstimateRefinementSteps(), getExpandedMinMaxOps(), GetExponent(), getExtendedControlRegister(), getExtendInVec(), getFLUSHW(), getFPBinOp(), getFPExtendOrRound(), GetFPLibCall(), getFPTernOp(), getFRAMEADDR(), getGeneralPermuteNode(), llvm::AMDGPUTargetLowering::getHiHalf64(), getInputChainForNode(), llvm::XCoreTargetLowering::getJumpTableEncoding(), llvm::ARMTargetLowering::getJumpTableEncoding(), getLimitedPrecisionExp2(), getLogicalNOT(), llvm::AMDGPUTargetLowering::getLoHalf64(), getMad64_32(), getMaskNode(), getMemBasePlusOffset(), getMemCmpLoad(), getMemcpyLoadsAndStores(), getMemmoveLoadsAndStores(), getMemsetStringVal(), getMemsetValue(), getMergeValues(), getMOVL(), getMul24(), GetNegatedExpression(), getNextIntArgReg(), getNode(), getNOT(), llvm::MipsTargetLowering::getOpndList(), getPermuteNode(), llvm::HexagonTargetLowering::getPICJumpTableRelocBase(), llvm::X86TargetLowering::getPICJumpTableRelocBase(), llvm::PPCTargetLowering::getPICJumpTableRelocBase(), llvm::PPCTargetLowering::getPICJumpTableRelocBaseExpr(), GetPromotionOpcode(), getReadPerformanceCounter(), getReadTimeStampCounter(), llvm::AMDGPUTargetLowering::getRecipEstimate(), getReductionSDNode(), GetRegistersForValue(), llvm::SelectionDAGBuilder::getRoot(), getScalarMaskingNode(), getSETCC(), llvm::AVRTargetLowering::getSetCCResultType(), getSExtOrTrunc(), getSignExtendVectorInReg(), GetSignificand(), getSplatConstantFP(), llvm::AMDGPUTargetLowering::getSqrtEstimate(), llvm::NVPTXTargetLowering::getSqrtEstimate(), getStackArgumentTokenFactor(), llvm::BPFTargetLowering::getTargetNodeName(), llvm::ARCTargetLowering::getTargetNodeName(), llvm::SystemZTargetLowering::getTargetNodeName(), getTargetVShiftByConstNode(), getTargetVShiftNode(), GetTLSADDR(), getTOCEntry(), getUnderlyingArgReg(), getUniformBase(), getv64i1Argument(), getVAArg(), llvm::SelectionDAGBuilder::getValueImpl(), getVectorCompareInfo(), llvm::TargetLowering::getVectorElementPointer(), getVectorMaskingNode(), getVectorShuffle(), getVShift(), getZeroExtendInReg(), getZeroExtendVectorInReg(), getZeroVector(), getZExtOrTrunc(), HandleMergeInputChains(), hasOnlySelectUsers(), haveEfficientBuildVectorPattern(), llvm::TargetLowering::IncrementMemoryAddress(), initAccumulator(), insert1BitVector(), insertSubVector(), llvm::intCCToAVRCC(), isADDADDMUL(), isBoolSGPR(), isBSwapHWordElement(), isClampZeroToOne(), isConstantOrUndefBUILD_VECTOR(), isContractable(), isDivRemLibcallAvailable(), llvm::TargetLowering::isExtendedTrueVal(), isFloatingPointZero(), isFMulNegTwo(), isFusableLoadOpStorePattern(), llvm::ARCTargetLowering::isLegalAddressingMode(), llvm::PPCTargetLowering::isLegalAddressingMode(), llvm::SelectionDAGISel::IsLegalToFold(), isMemOPCandidate(), isNegativeOne(), isNEONModifiedImm(), llvm::ARMTargetLowering::isReadOnly(), isSaturatingConditional(), isSETCCorConvertedSETCC(), IsSingleInstrConstant(), isSlicingProfitable(), IsSmallObject(), isSortedByValueNo(), isSplatVector(), isTargetConstant(), isTruncateOf(), isTruncWithZeroHighBitsInput(), llvm::SITargetLowering::isTypeDesirableForOp(), isVectorReductionOp(), isVShiftRImm(), isWordAligned(), isXor1OfSetCC(), joinDwords(), lower1BitVectorShuffle(), Lower256IntArith(), Lower256IntVSETCC(), Lower512IntArith(), LowerABS(), LowerADD_SUB(), LowerADDC_ADDE_SUBC_SUBE(), LowerADDSUBCARRY(), LowerADJUST_TRAMPOLINE(), LowerAsSplatVectorLoad(), llvm::HexagonTargetLowering::LowerATOMIC_FENCE(), LowerATOMIC_FENCE(), lowerAtomicArith(), LowerAVXExtend(), LowerBITCAST(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), llvm::LanaiTargetLowering::LowerBlockAddress(), llvm::MSP430TargetLowering::LowerBlockAddress(), llvm::HexagonTargetLowering::LowerBlockAddress(), LowerBoolVSETCC_AVX512(), llvm::LanaiTargetLowering::LowerBR_CC(), llvm::MSP430TargetLowering::LowerBR_CC(), LowerBR_CC(), llvm::HexagonTargetLowering::LowerBUILD_VECTOR(), LowerBUILD_VECTORAsVariablePermute(), lowerBuildVectorAsBroadcast(), LowerBuildVectorAsInsert(), lowerBuildVectorToBitOp(), LowerBuildVectorv16i8(), LowerBuildVectorv4x32(), llvm::HexagonTargetLowering::LowerCall(), llvm::SITargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), lowerCallResult(), llvm::SITargetLowering::LowerCallResult(), LowerCallResult(), llvm::TargetLowering::LowerCallTo(), llvm::TargetLowering::lowerCmpEqZeroToCtlzSrl(), llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(), LowerCONCAT_VECTORS(), LowerCONCAT_VECTORSvXi1(), llvm::LanaiTargetLowering::LowerConstantPool(), llvm::HexagonTargetLowering::LowerConstantPool(), LowerCTLZ(), llvm::AMDGPUTargetLowering::LowerCTLZ_CTTZ(), lowerCTPOP16BitElements(), lowerCTPOP32BitElements(), LowerCTTZ(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), lowerDSPIntr(), llvm::LanaiTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(), LowerDYNAMIC_STACKALLOC(), llvm::HexagonTargetLowering::LowerEH_RETURN(), llvm::SparcTargetLowering::LowerEH_SJLJ_LONGJMP(), llvm::SparcTargetLowering::LowerEH_SJLJ_SETJMP(), LowerEXTEND_VECTOR_INREG(), LowerExtended1BitVectorLoad(), LowerExtendedLoad(), llvm::MSP430TargetLowering::LowerExternalSymbol(), llvm::HexagonTargetLowering::LowerEXTRACT_VECTOR(), LowerEXTRACT_VECTOR_ELT(), LowerEXTRACT_VECTOR_ELT_SSE4(), llvm::SparcTargetLowering::LowerF128Compare(), LowerF128Load(), LowerF128Store(), LowerF64Op(), LowerFABSorFNEG(), llvm::AMDGPUTargetLowering::LowerFCEIL(), LowerFCOPYSIGN(), lowerFCOPYSIGN32(), lowerFCOPYSIGN64(), llvm::AMDGPUTargetLowering::LowerFFLOOR(), LowerFGETSIGN(), llvm::AMDGPUTargetLowering::LowerFNEARBYINT(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::SITargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerFormalArguments_64(), llvm::AMDGPUTargetLowering::LowerFP64_TO_INT(), LowerFP_EXTEND(), llvm::AMDGPUTargetLowering::LowerFP_TO_FP16(), llvm::AMDGPUTargetLowering::LowerFP_TO_SINT(), LowerFP_TO_SINT(), lowerFP_TO_SINT_STORE(), llvm::AMDGPUTargetLowering::LowerFP_TO_UINT(), LowerFPOWI(), llvm::LanaiTargetLowering::LowerFRAMEADDR(), llvm::AMDGPUTargetLowering::LowerFREM(), llvm::AMDGPUTargetLowering::LowerFRINT(), llvm::AMDGPUTargetLowering::LowerFROUND32_16(), llvm::AMDGPUTargetLowering::LowerFROUND64(), LowerFSINCOS(), llvm::AMDGPUTargetLowering::LowerFTRUNC(), llvm::HexagonTargetLowering::LowerGLOBAL_OFFSET_TABLE(), llvm::LanaiTargetLowering::LowerGlobalAddress(), llvm::MSP430TargetLowering::LowerGlobalAddress(), llvm::HexagonTargetLowering::LowerGLOBALADDRESS(), llvm::NVPTXTargetLowering::LowerGlobalAddress(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), lowerGR128Binary(), lowerGR128ToI128(), LowerHorizontalByteSum(), lowerI128ToGR128(), LowerINSERT_SUBVECTOR(), llvm::HexagonTargetLowering::LowerINSERT_VECTOR(), llvm::AMDGPUTargetLowering::LowerINT_TO_FP32(), llvm::AMDGPUTargetLowering::LowerINT_TO_FP64(), LowerInterruptReturn(), llvm::HexagonTargetLowering::LowerINTRINSIC_VOID(), LowerINTRINSIC_W_CHAIN(), LowerIntVSETCC_AVX512(), llvm::LanaiTargetLowering::LowerJumpTable(), llvm::MSP430TargetLowering::LowerJumpTable(), llvm::HexagonTargetLowering::LowerJumpTable(), LowerLabelRef(), llvm::MipsTargetLowering::lowerLOAD(), lowerMasksToReg(), LowerMemOpCallTo(), LowerMGATHER(), LowerMLOAD(), lowerMSABinaryBitImmIntr(), lowerMSABitClear(), lowerMSABitClearImm(), lowerMSACopyIntr(), lowerMSALoadIntr(), lowerMSASplatZExt(), lowerMSAStoreIntr(), LowerMSCATTER(), LowerMSTORE(), llvm::LanaiTargetLowering::LowerMUL(), LowerMUL(), LowerMUL_LOHI(), lowerMUL_LOHI32(), LowerMULH(), llvm::R600TargetLowering::LowerOperation(), llvm::BPFTargetLowering::LowerOperation(), llvm::RISCVTargetLowering::LowerOperation(), llvm::NVPTXTargetLowering::LowerOperation(), llvm::HexagonTargetLowering::LowerPREFETCH(), LowerPREFETCH(), llvm::SelectionDAGBuilder::lowerRangeToAssertZExt(), llvm::HexagonTargetLowering::LowerREADCYCLECOUNTER(), lowerRegToMasks(), llvm::AMDGPUTargetLowering::LowerReturn(), llvm::HexagonTargetLowering::LowerReturn(), llvm::SITargetLowering::LowerReturn(), llvm::SystemZTargetLowering::LowerReturn(), llvm::NVPTXTargetLowering::LowerReturn(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::SparcTargetLowering::LowerReturn_64(), llvm::LanaiTargetLowering::LowerRETURNADDR(), llvm::MSP430TargetLowering::LowerRETURNADDR(), llvm::HexagonTargetLowering::LowerRETURNADDR(), LowerRETURNADDR(), LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(), LowerRotate(), LowerSCALAR_TO_VECTOR(), LowerScalarImmediateShift(), LowerScalarVariableShift(), LowerSDIV(), LowerSDIV_v4i16(), LowerSDIV_v4i8(), llvm::AMDGPUTargetLowering::LowerSDIVREM(), llvm::LanaiTargetLowering::LowerSELECT_CC(), llvm::MSP430TargetLowering::LowerSELECT_CC(), LowerSELECT_CC(), llvm::LanaiTargetLowering::LowerSETCC(), llvm::MSP430TargetLowering::LowerSETCC(), llvm::HexagonTargetLowering::LowerSETCC(), llvm::LanaiTargetLowering::LowerSETCCE(), LowerSETCCE(), LowerShift(), LowerShiftParts(), llvm::MSP430TargetLowering::LowerShifts(), llvm::LanaiTargetLowering::LowerSHL_PARTS(), llvm::MSP430TargetLowering::LowerSIGN_EXTEND(), LowerSIGN_EXTEND(), LowerSIGN_EXTEND_AVX512(), llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(), llvm::AMDGPUTargetLowering::LowerSINT_TO_FP(), LowerSINT_TO_FP(), llvm::LanaiTargetLowering::LowerSRL_PARTS(), llvm::MipsTargetLowering::lowerSTORE(), LowerSTORE(), lowerToAddSubOrFMAddSub(), LowerToHorizontalOp(), LowerToTLSExecModel(), llvm::HexagonTargetLowering::LowerToTLSGeneralDynamicModel(), LowerToTLSGeneralDynamicModel32(), llvm::HexagonTargetLowering::LowerToTLSInitialExecModel(), LowerToTLSLocalDynamicModel(), llvm::HexagonTargetLowering::LowerToTLSLocalExecModel(), LowerTruncateVecI1(), LowerTruncatingStore(), LowerUDIV(), llvm::AMDGPUTargetLowering::LowerUDIVREM(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), llvm::AMDGPUTargetLowering::LowerUINT_TO_FP(), lowerUINT_TO_FP_v2i32(), lowerUINT_TO_FP_vXi32(), LowerUMULO_SMULO(), lowerV16F32VectorShuffle(), lowerV16I32VectorShuffle(), lowerV16I8VectorShuffle(), lowerV2F64VectorShuffle(), lowerV2I64VectorShuffle(), lowerV2X128VectorShuffle(), lowerV4F32VectorShuffle(), lowerV4F64VectorShuffle(), lowerV4I32VectorShuffle(), lowerV4I64VectorShuffle(), lowerV4X128VectorShuffle(), lowerV8F32VectorShuffle(), lowerV8F64VectorShuffle(), lowerV8I16GeneralSingleInputVectorShuffle(), lowerV8I32VectorShuffle(), lowerV8I64VectorShuffle(), LowerVAARG(), LowerVASTART(), llvm::HexagonTargetLowering::LowerVECTOR_SHIFT(), llvm::HexagonTargetLowering::LowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE_ILVEV(), lowerVECTOR_SHUFFLE_ILVL(), lowerVECTOR_SHUFFLE_ILVOD(), lowerVECTOR_SHUFFLE_ILVR(), lowerVECTOR_SHUFFLE_PCKEV(), lowerVECTOR_SHUFFLE_PCKOD(), lowerVECTOR_SHUFFLE_SHF(), lowerVECTOR_SHUFFLE_VSHF(), LowerVECTOR_SHUFFLEv8i8(), LowerVectorAllZeroTest(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTLZInRegLUT(), LowerVectorCTPOP(), LowerVectorCTPOPBitmath(), LowerVectorCTPOPInRegLUT(), LowerVectorFP_TO_INT(), LowerVectorINT_TO_FP(), LowerVectorIntUnary(), lowerVectorShuffleAsBitBlend(), lowerVectorShuffleAsBitMask(), lowerVectorShuffleAsBlend(), lowerVectorShuffleAsBlendOfPSHUFBs(), lowerVectorShuffleAsBroadcast(), lowerVectorShuffleAsByteRotate(), lowerVectorShuffleAsElementInsertion(), lowerVectorShuffleAsInsertPS(), lowerVectorShuffleAsPermuteAndUnpack(), lowerVectorShuffleAsRotate(), lowerVectorShuffleAsShift(), lowerVectorShuffleAsSpecificZeroOrAnyExtend(), lowerVectorShuffleAsTruncBroadcast(), lowerVectorShuffleAsZeroOrAnyExtend(), lowerVectorShuffleToEXPAND(), lowerVectorShuffleWithPACK(), lowerVectorShuffleWithPERMV(), lowerVectorShuffleWithPSHUFB(), lowerVectorShuffleWithSHUFPD(), lowerVectorShuffleWithSHUFPS(), lowerVectorShuffleWithSSE4A(), lowerVectorShuffleWithUndefHalf(), lowerVectorShuffleWithUNPCK(), llvm::HexagonTargetLowering::LowerVSELECT(), lowerVSELECTtoVectorShuffle(), LowerVSETCC(), LowerWRITE_REGISTER(), lowerX86CmpEqZeroToCtlzSrl(), lowerX86FPLogicOp(), LowerXALUO(), LowerXOR(), LowerZERO_EXTEND_AVX512(), llvm::SparcTargetLowering::makeAddress(), makeEquivalentMemoryOrdering(), llvm::SparcTargetLowering::makeHiLoPair(), matchBinaryPredicate(), matchRotateSub(), materializeSBB(), mayTailCallThisCC(), minMaxOpcToMin3Max3Opc(), moveBelowOrigChain(), narrowExtractedVectorBinOp(), narrowExtractedVectorLoad(), llvm::X86TargetLowering::needsFixedCatchObjects(), NegateCC(), NormalizeBuildVector(), optimizeLogicalImm(), parsePhysicalReg(), partitionShuffleOfConcats(), Passv64i1ArgInRegs(), peekThroughBitcast(), performADDCombine(), PerformADDCombineWithOperands(), PerformAddcSubcCombine(), PerformAddeSubeCombine(), performAddSubLongCombine(), performANDCombine(), PerformANDCombine(), PerformARMBUILD_VECTORCombine(), llvm::AMDGPUTargetLowering::performAssertSZExtCombine(), PerformBFICombine(), performBitcastCombine(), llvm::ARMTargetLowering::PerformBRCONDCombine(), performBRCONDCombine(), PerformBUILD_VECTORCombine(), llvm::ARMTargetLowering::PerformCMOVCombine(), performCMovFPCombine(), llvm::ARMTargetLowering::PerformCMOVToBFICombine(), performConcatVectorsCombine(), performCONDCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::SITargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), performDivRemCombine(), performDSPShiftCombine(), performExtendCombine(), PerformExtendCombine(), llvm::AMDGPUTargetLowering::performFAbsCombine(), performFDivCombine(), llvm::AMDGPUTargetLowering::performFNegCombine(), performFpToIntCombine(), PerformInsertEltCombine(), performIntegerAbsCombine(), performIntrinsicCombine(), PerformIntrinsicCombine(), performIntToFpCombine(), llvm::AMDGPUTargetLowering::performLoadCombine(), performMADD_MSUBCombine(), performMulCombine(), PerformMULCombine(), llvm::AMDGPUTargetLowering::performMulhsCombine(), llvm::AMDGPUTargetLowering::performMulhuCombine(), llvm::AMDGPUTargetLowering::performMulLoHi24Combine(), performORCombine(), PerformORCombine(), PerformORCombineToBFI(), PerformORCombineToSMULWBT(), PerformREMCombine(), llvm::AMDGPUTargetLowering::performSelectCombine(), performSELECTCombine(), performSelectCombine(), performSetccAddFolding(), performSETCCCombine(), PerformSETCCCombine(), PerformShiftCombine(), llvm::AMDGPUTargetLowering::performShlCombine(), performSHLCombine(), PerformSHLSimplify(), llvm::AMDGPUTargetLowering::performSraCombine(), performSRACombine(), llvm::AMDGPUTargetLowering::performSrlCombine(), performSRLCombine(), llvm::AMDGPUTargetLowering::performStoreCombine(), PerformSTORECombine(), performTBZCombine(), PerformUMLALCombine(), PerformVCVTCombine(), PerformVDIVCombine(), PerformVDUPLANECombine(), PerformVECTOR_SHUFFLECombine(), performVectorCompareAndMaskUnaryOpCombine(), PerformVMOVDRRCombine(), PerformVMULCombine(), performVSELECTCombine(), performVSelectCombine(), performXORCombine(), performXorCombine(), PrepareCall(), PrepareTailCall(), promoteExtBeforeAdd(), promoteToConstantPool(), llvm::AArch64TargetLowering::ReconstructShuffle(), recoverFramePointer(), reduceMaskedLoadToScalarLoad(), reduceMaskedStoreToScalarStore(), reduceVMULWidth(), ReplaceAllUsesWith(), ReplaceBITCASTResults(), replaceInChain(), ReplaceINTRINSIC_W_CHAIN(), ReplaceLoadVector(), ReplaceLongIntrinsic(), llvm::R600TargetLowering::ReplaceNodeResults(), llvm::AVRTargetLowering::ReplaceNodeResults(), llvm::XCoreTargetLowering::ReplaceNodeResults(), llvm::SparcTargetLowering::ReplaceNodeResults(), llvm::SITargetLowering::ReplaceNodeResults(), llvm::PPCTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), ReplaceREADCYCLECOUNTER(), ReplaceReductionResults(), resolveBuildVector(), llvm::TargetLowering::scalarizeVectorLoad(), llvm::TargetLowering::scalarizeVectorStore(), llvm::HexagonDAGToDAGISel::SelectIntrinsicWOChain(), llvm::SelectionDAGBuilder::ShouldEmitAsBranches(), shouldGuaranteeTCO(), llvm::TargetLowering::ShrinkDemandedConstant(), ShrinkLoadReplaceStoreWithStore(), llvm::TargetLowering::SimplifyDemandedBits(), simplifyDivRem(), llvm::TargetLowering::SimplifySetCC(), simplifyShuffleOperandRecursively(), SkipExtensionForVMULL(), llvm::TargetLowering::softenSetCCOperands(), llvm::AMDGPUTargetLowering::split64BitValue(), splitAndLowerVectorShuffle(), llvm::AMDGPUTargetLowering::splitBinaryBitConstantOpImpl(), splitInt128(), splitStores(), splitStoreSplat(), llvm::AMDGPUTargetLowering::SplitVectorLoad(), llvm::AMDGPUTargetLowering::SplitVectorStore(), SplitVSETCC(), llvm::AMDGPUTargetLowering::storeStackInputValue(), stripModuloOnShift(), truncateVecElts(), truncateVectorWithPACK(), tryBuildVectorReplicate(), tryCombineCRC32(), tryCombineFixedPointConvert(), tryCombineLongOpWithDup(), tryCombineShiftImm(), tryCombineToBSL(), tryCombineToEXTR(), tryExtendDUPToExtractHigh(), tryFoldToZero(), tryFormConcatFromShuffle(), tryLowerToSLI(), TryMULWIDECombine(), tryToFoldExtendOfConstant(), UnpackFromArgumentSlot(), llvm::SelectionDAGBuilder::UpdateSplitBlock(), llvm::SelectionDAGBuilder::visitBitTestCase(), llvm::SelectionDAGBuilder::visitBitTestHeader(), llvm::SelectionDAGBuilder::visitJumpTable(), llvm::SelectionDAGBuilder::visitJumpTableHeader(), llvm::SelectionDAGBuilder::visitSPDescriptorParent(), llvm::SelectionDAGBuilder::visitSwitchCase(), WidenMaskArithmetic(), WidenVector(), willShiftRightEliminate(), WinDBZCheckDenominator(), and XFormVExtractWithShuffleIntoLoad().

◆ getNode() [2/16]

SDValue SelectionDAG::getNode ( unsigned  Opcode,
const SDLoc DL,
EVT  VT,
ArrayRef< SDValue Ops,
const SDNodeFlags  Flags = SDNodeFlags() 
)

◆ getNode() [3/16]

SDValue SelectionDAG::getNode ( unsigned  Opcode,
const SDLoc DL,
ArrayRef< EVT ResultTys,
ArrayRef< SDValue Ops 
)

Definition at line 6321 of file SelectionDAG.cpp.

References getNode(), and getVTList().

◆ getNode() [4/16]

SDValue SelectionDAG::getNode ( unsigned  Opcode,
const SDLoc DL,
SDVTList  VTs,
ArrayRef< SDValue Ops 
)

◆ getNode() [5/16]

SDValue SelectionDAG::getNode ( unsigned  Opcode,
const SDLoc DL,
EVT  VT 
)

Gets or creates the specified node.

Definition at line 3558 of file SelectionDAG.cpp.

References AddNodeIDNode(), E, llvm::SDLoc::getDebugLoc(), llvm::SDLoc::getIROrder(), getVTList(), NewSDValueDbgMsg(), and llvm::None.

◆ getNode() [6/16]

SDValue SelectionDAG::getNode ( unsigned  Opcode,
const SDLoc DL,
EVT  VT,
SDValue  N,
const SDNodeFlags  Flags = SDNodeFlags() 
)

Definition at line 3575 of file SelectionDAG.cpp.

References llvm::ISD::ABS, llvm::APInt::abs(), AddNodeIDNode(), llvm::ISD::ANY_EXTEND, llvm::lltok::APFloat, assert(), llvm::ISD::BITCAST, llvm::APFloat::bitcastToAPInt(), llvm::ISD::BITREVERSE, llvm::EVT::bitsGT(), llvm::EVT::bitsLE(), llvm::EVT::bitsLT(), llvm::ISD::BSWAP, llvm::APInt::byteSwap(), C, llvm::APFloat::changeSign(), llvm::APFloat::clearSign(), llvm::ISD::CONCAT_VECTORS, llvm::APFloat::convert(), llvm::APFloat::convertFromAPInt(), llvm::APFloat::convertToInteger(), llvm::APInt::countLeadingZeros(), llvm::APInt::countPopulation(), llvm::APInt::countTrailingZeros(), llvm::ISD::CTLZ, llvm::ISD::CTLZ_ZERO_UNDEF, llvm::ISD::CTPOP, llvm::ISD::CTTZ, llvm::ISD::CTTZ_ZERO_UNDEF, E, EVTToAPFloatSemantics(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f128, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::ISD::FABS, llvm::ISD::FCEIL, llvm::ISD::FFLOOR, llvm::ISD::FNEG, FoldConstantVectorArithmetic(), llvm::ISD::FP16_TO_FP, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::ISD::FP_TO_FP16, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::ISD::FSUB, llvm::ISD::FTRUNC, llvm::APInt::getBitWidth(), getConstant(), getConstantFP(), llvm::SDValue::getConstantOperandVal(), llvm::SDLoc::getDebugLoc(), llvm::SDNode::getFlags(), llvm::SDLoc::getIROrder(), llvm::SDValue::getNode(), getNode(), llvm::APInt::getNullValue(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::EVT::getSizeInBits(), getTarget(), getUNDEF(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), getVTList(), llvm::APInt::getZExtValue(), llvm::MVT::Glue, llvm::MVT::i128, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::APFloatBase::IEEEdouble(), llvm::APFloatBase::IEEEhalf(), llvm::APFloatBase::IEEEquad(), llvm::APFloatBase::IEEEsingle(), llvm::tgtok::IntVal, llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::SDValue::isUndef(), llvm::EVT::isVector(), llvm_unreachable, llvm::ISD::MERGE_VALUES, N, NewSDValueDbgMsg(), llvm::APFloatBase::opInexact, llvm::APFloatBase::opInvalidOp, llvm::APFloatBase::opOK, llvm::APInt::reverseBits(), llvm::APFloatBase::rmNearestTiesToEven, llvm::APFloatBase::rmTowardNegative, llvm::APFloatBase::rmTowardPositive, llvm::APFloatBase::rmTowardZero, llvm::APFloat::roundToIntegral(), llvm::ISD::SCALAR_TO_VECTOR, llvm::SDNode::setFlags(), llvm::APInt::sextOrTrunc(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::TokenFactor, llvm::APInt::trunc(), llvm::ISD::TRUNCATE, llvm::ISD::UINT_TO_FP, llvm::ISD::UNDEF, llvm::ISD::ZERO_EXTEND, and llvm::APInt::zextOrTrunc().

◆ getNode() [7/16]

SDValue SelectionDAG::getNode ( unsigned  Opcode,
const SDLoc DL,
EVT  VT,
SDValue  N1,
SDValue  N2,
const SDNodeFlags  Flags = SDNodeFlags() 
)

Definition at line 4213 of file SelectionDAG.cpp.

References llvm::ISD::ADD, llvm::APFloat::add(), llvm::ISD::ADDC, llvm::ISD::ADDE, AddNodeIDNode(), llvm::ISD::AND, llvm::APInt::ashrInPlace(), assert(), llvm::ISD::AssertSext, llvm::ISD::AssertZext, llvm::EVT::bitsLE(), llvm::ISD::BUILD_PAIR, llvm::ISD::BUILD_VECTOR, C, llvm::ISD::CONCAT_VECTORS, llvm::APFloat::convert(), llvm::APFloat::copySign(), llvm::APFloat::divide(), llvm::dyn_cast(), E, llvm::ISD::EntryToken, EVTToAPFloatSemantics(), llvm::ISD::EXTRACT_ELEMENT, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FADD, llvm::ISD::FCOPYSIGN, llvm::ISD::FDIV, llvm::ISD::FMUL, FoldCONCAT_VECTORS(), FoldConstantArithmetic(), llvm::ISD::FP_ROUND, llvm::ISD::FP_ROUND_INREG, llvm::ISD::FREM, llvm::ISD::FSUB, llvm::APInt::getAllOnesValue(), getAnyExtOrTrunc(), llvm::ConstantSDNode::getAPIntValue(), llvm::APInt::getBitWidth(), getBuildVector(), getConstant(), getConstantFP(), llvm::SDLoc::getDebugLoc(), llvm::SDLoc::getIROrder(), llvm::SDValue::getNode(), getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), getSExtOrTrunc(), llvm::SDValue::getSimpleValueType(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), getTarget(), getUNDEF(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), getVTList(), llvm::ConstantSDNode::getZExtValue(), llvm::MVT::Glue, llvm::TargetLoweringBase::hasFloatingPointExceptions(), llvm::MVT::i1, llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::TargetLoweringBase::isCommutativeBinOp(), llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::EVT::isSimple(), llvm::SDValue::isUndef(), llvm::EVT::isVector(), LLVM_FALLTHROUGH, llvm::Log2_32_Ceil(), llvm::APInt::lshr(), llvm::APFloat::mod(), llvm::ISD::MUL, llvm::ISD::MULHS, llvm::ISD::MULHU, llvm::APFloat::multiply(), N, NewSDValueDbgMsg(), llvm::APFloatBase::opDivByZero, llvm::APFloatBase::opInvalidOp, llvm::TargetMachine::Options, llvm::ISD::OR, llvm::MVT::Other, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::APFloatBase::rmNearestTiesToEven, llvm::ISD::ROTL, llvm::ISD::ROTR, llvm::ISD::SDIV, llvm::SDNode::setFlags(), llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::SRA, llvm::ISD::SREM, llvm::ISD::SRL, llvm::ISD::SUB, llvm::APFloat::subtract(), std::swap(), llvm::ISD::TokenFactor, llvm::APInt::trunc(), llvm::ISD::UDIV, llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::TargetOptions::UnsafeFPMath, llvm::ISD::UREM, llvm::NVPTX::PTXLdStInstCode::V2, and llvm::ISD::XOR.

◆ getNode() [8/16]

SDValue SelectionDAG::getNode ( unsigned  Opcode,
const SDLoc DL,
EVT  VT,
SDValue  N1,
SDValue  N2,
SDValue  N3 
)

◆ getNode() [9/16]

SDValue SelectionDAG::getNode ( unsigned  Opcode,
const SDLoc DL,
EVT  VT,
SDValue  N1,
SDValue  N2,
SDValue  N3,
SDValue  N4 
)

Definition at line 4827 of file SelectionDAG.cpp.

References getNode().

◆ getNode() [10/16]

SDValue SelectionDAG::getNode ( unsigned  Opcode,
const SDLoc DL,
EVT  VT,
SDValue  N1,
SDValue  N2,
SDValue  N3,
SDValue  N4,
SDValue  N5 
)

Definition at line 4833 of file SelectionDAG.cpp.

References getNode().

◆ getNode() [11/16]

SDValue SelectionDAG::getNode ( unsigned  Opcode,
const SDLoc DL,
SDVTList  VTs 
)

Definition at line 6374 of file SelectionDAG.cpp.

References getNode(), and llvm::None.

◆ getNode() [12/16]

SDValue SelectionDAG::getNode ( unsigned  Opcode,
const SDLoc DL,
SDVTList  VTs,
SDValue  N 
)

Definition at line 6379 of file SelectionDAG.cpp.

References getNode().

◆ getNode() [13/16]

SDValue SelectionDAG::getNode ( unsigned  Opcode,
const SDLoc DL,
SDVTList  VTs,
SDValue  N1,
SDValue  N2 
)

Definition at line 6385 of file SelectionDAG.cpp.

References getNode().

◆ getNode() [14/16]

SDValue SelectionDAG::getNode ( unsigned  Opcode,
const SDLoc DL,
SDVTList  VTs,
SDValue  N1,
SDValue  N2,
SDValue  N3 
)

Definition at line 6391 of file SelectionDAG.cpp.

References getNode().

◆ getNode() [15/16]

SDValue SelectionDAG::getNode ( unsigned  Opcode,
const SDLoc DL,
SDVTList  VTs,
SDValue  N1,
SDValue  N2,
SDValue  N3,
SDValue  N4 
)

Definition at line 6397 of file SelectionDAG.cpp.

References getNode().

◆ getNode() [16/16]

SDValue SelectionDAG::getNode ( unsigned  Opcode,
const SDLoc DL,
SDVTList  VTs,
SDValue  N1,
SDValue  N2,
SDValue  N3,
SDValue  N4,
SDValue  N5 
)

Definition at line 6403 of file SelectionDAG.cpp.

References getNode().

◆ getNodeIfExists()

SDNode * SelectionDAG::getNodeIfExists ( unsigned  Opcode,
SDVTList  VTList,
ArrayRef< SDValue Ops,
const SDNodeFlags  Flags = SDNodeFlags() 
)

Get the specified node if it's already available, or else return NULL.

getNodeIfExists - Get the specified node if it's already available, or else return NULL.

Definition at line 6982 of file SelectionDAG.cpp.

References AddNodeIDNode(), E, llvm::MVT::Glue, llvm::SDVTList::NumVTs, and llvm::SDVTList::VTs.

Referenced by EmitKTEST(), and matchBinaryPredicate().

◆ getNOT()

SDValue SelectionDAG::getNOT ( const SDLoc DL,
SDValue  Val,
EVT  VT 
)

◆ getORE()

OptimizationRemarkEmitter& llvm::SelectionDAG::getORE ( ) const
inline

Definition at line 394 of file SelectionDAG.h.

◆ getPass()

const Pass* llvm::SelectionDAG::getPass ( ) const
inline

◆ getRegister()

SDValue SelectionDAG::getRegister ( unsigned  Reg,
EVT  VT 
)

Definition at line 1654 of file SelectionDAG.cpp.

References llvm::FoldingSetNodeID::AddInteger(), AddNodeIDNode(), E, getVTList(), llvm::None, and llvm::ISD::Register.

Referenced by llvm::RegsForValue::AddInlineAsmOperands(), llvm::analyzeArguments(), AnalyzeReturnValues(), llvm::AVRDAGToDAGISel::select< AVRISD::CALL >(), llvm::AVRDAGToDAGISel::select< ISD::LOAD >(), CC_Lanai32_VarArg(), llvm::ARMTargetLowering::CCAssignFnForReturn(), createCMovFP(), llvm::AMDGPUTargetLowering::CreateLiveInRegister(), llvm::MipsTargetLowering::EmitInstrWithCustomInserter(), expandf64Toi32(), findUnwindDestinations(), findUser(), getAbsolute(), llvm::MipsTargetLowering::getAddrGPRel(), getAVX2GatherNode(), llvm::HexagonTargetLowering::GetDynamicTLSAddr(), getEstimate(), getGatherNode(), llvm::MipsDAGToDAGISel::getGlobalBaseReg(), llvm::MipsTargetLowering::getGlobalReg(), llvm::ARMTargetLowering::getJumpTableEncoding(), getMOVL(), llvm::MipsTargetLowering::getOpndList(), llvm::PPCTargetLowering::getPICJumpTableRelocBaseExpr(), getPrefetchNode(), getScatterNode(), llvm::ARCTargetLowering::getTargetNodeName(), getTOCEntry(), getVectorCompareInfo(), getZeroVector(), isADDADDMUL(), isFloatingPointZero(), isSaturatingConditional(), isXor1OfSetCC(), llvm::SITargetLowering::legalizeTargetIndependentNode(), LowerATOMIC_FENCE(), llvm::HexagonTargetLowering::LowerCall(), llvm::SITargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), lowerCallResult(), LowerCallResult(), llvm::SelectionDAGBuilder::LowerCallTo(), llvm::LanaiTargetLowering::LowerConstantPool(), llvm::HexagonTargetLowering::LowerEH_RETURN(), lowerFCOPYSIGN64(), llvm::LanaiTargetLowering::LowerGlobalAddress(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), LowerInterruptReturn(), llvm::SparcTargetLowering::LowerINTRINSIC_WO_CHAIN(), llvm::LanaiTargetLowering::LowerJumpTable(), LowerMemOpCallTo(), llvm::BPFTargetLowering::LowerOperation(), llvm::RISCVTargetLowering::LowerOperation(), llvm::HexagonTargetLowering::LowerReturn(), llvm::SITargetLowering::LowerReturn(), llvm::SystemZTargetLowering::LowerReturn(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::SparcTargetLowering::LowerReturn_64(), LowerSETCCE(), LowerVASTART(), mayTailCallThisCC(), llvm::X86TargetLowering::needsFixedCatchObjects(), parsePhysicalReg(), Passv64i1ArgInRegs(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), performNEONPostLDSTCombine(), performPostLD1Combine(), llvm::SITargetLowering::PostISelFolding(), PrepareCall(), llvm::PPCTargetLowering::SelectAddressRegImm(), llvm::PPCTargetLowering::SelectAddressRegRegOnly(), llvm::SelectionDAGISel::SelectCodeCommon(), and UnpackFromArgumentSlot().

◆ getRegisterMask()

SDValue SelectionDAG::getRegisterMask ( const uint32_t RegMask)

◆ getRoot()

const SDValue& llvm::SelectionDAG::getRoot ( ) const
inline

◆ getSelect()

SDValue llvm::SelectionDAG::getSelect ( const SDLoc DL,
EVT  VT,
SDValue  Cond,
SDValue  LHS,
SDValue  RHS 
)
inline

◆ getSelectCC()

SDValue llvm::SelectionDAG::getSelectCC ( const SDLoc DL,
SDValue  LHS,
SDValue  RHS,
SDValue  True,
SDValue  False,
ISD::CondCode  Cond 
)
inline

◆ getSelectionDAGInfo()

const SelectionDAGTargetInfo& llvm::SelectionDAG::getSelectionDAGInfo ( ) const
inline

Definition at line 392 of file SelectionDAG.h.

Referenced by getMemCmpLoad().

◆ getSetCC()

SDValue llvm::SelectionDAG::getSetCC ( const SDLoc DL,
EVT  VT,
SDValue  LHS,
SDValue  RHS,
ISD::CondCode  Cond 
)
inline

Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SDValue.

Definition at line 898 of file SelectionDAG.h.

References assert(), llvm::SDValue::getValueType(), llvm::EVT::isVector(), llvm::ISD::SETCC, and llvm::ISD::SETCC_INVALID.

Referenced by calculateByteProvider(), combineFMinNumFMaxNum(), combineSelect(), combineSetCC(), combineShuffleOfSplat(), combineToExtendBoolVectorInReg(), combineVectorSizedSetCCEquality(), combineVSelectWithAllOnesOrZeros(), ExtendUsesToFormExtLoad(), findUser(), FoldIntToFPToInt(), FoldSetCC(), foldXorTruncShiftIntoCmp(), getEstimate(), getExpandedMinMaxOps(), GetFPLibCall(), getFPTernOp(), getMemCmpLoad(), llvm::PPCTargetLowering::getPICJumpTableRelocBaseExpr(), GetPromotionOpcode(), haveEfficientBuildVectorPattern(), llvm::TargetLowering::isExtendedTrueVal(), isTruncateOf(), isVectorReductionOp(), llvm::NVPTXTargetLowering::LowerCall(), llvm::AMDGPUTargetLowering::LowerCTLZ_CTTZ(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), llvm::AMDGPUTargetLowering::LowerFCEIL(), llvm::AMDGPUTargetLowering::LowerFFLOOR(), llvm::AMDGPUTargetLowering::LowerFRINT(), llvm::AMDGPUTargetLowering::LowerFROUND32_16(), llvm::AMDGPUTargetLowering::LowerFROUND64(), llvm::AMDGPUTargetLowering::LowerFTRUNC(), llvm::AMDGPUTargetLowering::LowerINT_TO_FP32(), lowerMSABitClearImm(), llvm::LanaiTargetLowering::LowerSHL_PARTS(), llvm::LanaiTargetLowering::LowerSRL_PARTS(), lowerUINT_TO_FP_vXi32(), LowerUMULO_SMULO(), LowerVectorCTLZInRegLUT(), LowerVSETCC(), llvm::AMDGPUTargetLowering::performSelectCombine(), performSELECTCombine(), performVSelectCombine(), PrepareCall(), simplifyDivRem(), llvm::TargetLowering::SimplifySetCC(), llvm::SelectionDAGBuilder::visitBitTestCase(), llvm::SelectionDAGBuilder::visitBitTestHeader(), llvm::SelectionDAGBuilder::visitJumpTableHeader(), llvm::SelectionDAGBuilder::visitSPDescriptorParent(), and llvm::SelectionDAGBuilder::visitSwitchCase().

◆ getSExtOrTrunc()

SDValue SelectionDAG::getSExtOrTrunc ( SDValue  Op,
const SDLoc DL,
EVT  VT 
)

◆ getShiftAmountOperand()

SDValue SelectionDAG::getShiftAmountOperand ( EVT  LHSTy,