LLVM  12.0.0git
llvm::SystemZInstrInfo Member List

This is the complete list of members for llvm::SystemZInstrInfo, including all inherited members.

analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const overridellvm::SystemZInstrInfo
analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int &Mask, int &Value) const overridellvm::SystemZInstrInfo
areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const overridellvm::SystemZInstrInfo
canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const overridellvm::SystemZInstrInfo
commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned CommuteOpIdx1, unsigned CommuteOpIdx2) const overridellvm::SystemZInstrInfoprotected
convertToThreeAddress(MachineFunction::iterator &MFI, MachineInstr &MI, LiveVariables *LV) const overridellvm::SystemZInstrInfo
copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const overridellvm::SystemZInstrInfo
expandPostRAPseudo(MachineInstr &MBBI) const overridellvm::SystemZInstrInfo
FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const overridellvm::SystemZInstrInfo
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const overridellvm::SystemZInstrInfo
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, LiveIntervals *LIS=nullptr) const overridellvm::SystemZInstrInfo
getBranchInfo(const MachineInstr &MI) constllvm::SystemZInstrInfo
getFusedCompare(unsigned Opcode, SystemZII::FusedCompareType Type, const MachineInstr *MI=nullptr) constllvm::SystemZInstrInfo
getInstSizeInBytes(const MachineInstr &MI) const overridellvm::SystemZInstrInfo
getLoadAndTest(unsigned Opcode) constllvm::SystemZInstrInfo
getLoadAndTrap(unsigned Opcode) constllvm::SystemZInstrInfo
getLoadStoreOpcodes(const TargetRegisterClass *RC, unsigned &LoadOpcode, unsigned &StoreOpcode) constllvm::SystemZInstrInfo
getOpcodeForOffset(unsigned Opcode, int64_t Offset) constllvm::SystemZInstrInfo
getRegisterInfo() constllvm::SystemZInstrInfoinline
insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const overridellvm::SystemZInstrInfo
insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const overridellvm::SystemZInstrInfo
isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const overridellvm::SystemZInstrInfo
isPredicable(const MachineInstr &MI) const overridellvm::SystemZInstrInfo
isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const overridellvm::SystemZInstrInfo
isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const overridellvm::SystemZInstrInfo
isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumCyclesT, unsigned ExtraPredCyclesT, MachineBasicBlock &FMBB, unsigned NumCyclesF, unsigned ExtraPredCyclesF, BranchProbability Probability) const overridellvm::SystemZInstrInfo
isRxSBGMask(uint64_t Mask, unsigned BitSize, unsigned &Start, unsigned &End) constllvm::SystemZInstrInfo
isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex, int &SrcFrameIndex) const overridellvm::SystemZInstrInfo
isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const overridellvm::SystemZInstrInfo
loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned Reg, uint64_t Value) constllvm::SystemZInstrInfo
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const overridellvm::SystemZInstrInfo
PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const overridellvm::SystemZInstrInfo
prepareCompareSwapOperands(MachineBasicBlock::iterator MBBI) constllvm::SystemZInstrInfo
removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const overridellvm::SystemZInstrInfo
reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const overridellvm::SystemZInstrInfo
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const overridellvm::SystemZInstrInfo
SystemZInstrInfo(SystemZSubtarget &STI)llvm::SystemZInstrInfoexplicit
verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const overridellvm::SystemZInstrInfo