|
LLVM 19.0.0git
|
This is the complete list of members for llvm::TargetRegisterInfo, including all inherited members.
| adjustStackMapLiveOutMask(uint32_t *Mask) const | llvm::TargetRegisterInfo | inlinevirtual |
| canRealignStack(const MachineFunction &MF) const | llvm::TargetRegisterInfo | virtual |
| checkAllSuperRegsMarked(const BitVector &RegisterSet, ArrayRef< MCPhysReg > Exceptions=ArrayRef< MCPhysReg >()) const | llvm::TargetRegisterInfo | |
| composeSubRegIndexLaneMask(unsigned IdxA, LaneBitmask Mask) const | llvm::TargetRegisterInfo | inline |
| composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const | llvm::TargetRegisterInfo | inlineprotectedvirtual |
| composeSubRegIndices(unsigned a, unsigned b) const | llvm::TargetRegisterInfo | inline |
| composeSubRegIndicesImpl(unsigned, unsigned) const | llvm::TargetRegisterInfo | inlineprotectedvirtual |
| doesRegClassHavePseudoInitUndef(const TargetRegisterClass *RC) const | llvm::TargetRegisterInfo | inlinevirtual |
| dumpReg(Register Reg, unsigned SubRegIndex=0, const TargetRegisterInfo *TRI=nullptr) | llvm::TargetRegisterInfo | static |
| eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const =0 | llvm::TargetRegisterInfo | pure virtual |
| eliminateFrameIndicesBackwards() const | llvm::TargetRegisterInfo | inlinevirtual |
| explainReservedReg(const MachineFunction &MF, MCRegister PhysReg) const | llvm::TargetRegisterInfo | inlinevirtual |
| get(MCRegister RegNo) const | llvm::MCRegisterInfo | inline |
| getAllocatableClass(const TargetRegisterClass *RC) const | llvm::TargetRegisterInfo | |
| getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const | llvm::TargetRegisterInfo | |
| getCalleeSavedRegs(const MachineFunction *MF) const =0 | llvm::TargetRegisterInfo | pure virtual |
| getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const | llvm::TargetRegisterInfo | inlinevirtual |
| getCodeViewRegNum(MCRegister RegNum) const | llvm::MCRegisterInfo | |
| getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const | llvm::TargetRegisterInfo | |
| getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA, const TargetRegisterClass *RCB, unsigned SubB, unsigned &PreA, unsigned &PreB) const | llvm::TargetRegisterInfo | |
| getConstrainedRegClassForOperand(const MachineOperand &MO, const MachineRegisterInfo &MRI) const | llvm::TargetRegisterInfo | inlinevirtual |
| getCoveringLanes() const | llvm::TargetRegisterInfo | inline |
| getCoveringSubRegIndexes(const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, LaneBitmask LaneMask, SmallVectorImpl< unsigned > &Indexes) const | llvm::TargetRegisterInfo | |
| getCrossCopyRegClass(const TargetRegisterClass *RC) const | llvm::TargetRegisterInfo | inlinevirtual |
| getCSRFirstUseCost() const | llvm::TargetRegisterInfo | inlinevirtual |
| getCustomEHPadPreservedMask(const MachineFunction &MF) const | llvm::TargetRegisterInfo | inlinevirtual |
| getDwarfRegNum(MCRegister RegNum, bool isEH) const | llvm::MCRegisterInfo | |
| getDwarfRegNumFromDwarfEHRegNum(unsigned RegNum) const | llvm::MCRegisterInfo | |
| getEncodingValue(MCRegister RegNo) const | llvm::MCRegisterInfo | inline |
| getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const | llvm::TargetRegisterInfo | inlinevirtual |
| getFrameRegister(const MachineFunction &MF) const =0 | llvm::TargetRegisterInfo | pure virtual |
| getIntraCallClobberedRegs(const MachineFunction *MF) const | llvm::TargetRegisterInfo | inlinevirtual |
| getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const | llvm::TargetRegisterInfo | inlinevirtual |
| getLargestSuperClass(const TargetRegisterClass *RC) const | llvm::TargetRegisterInfo | inlinevirtual |
| getLLVMRegNum(unsigned RegNum, bool isEH) const | llvm::MCRegisterInfo | |
| getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const TargetRegisterClass *RC) const | llvm::TargetRegisterInfo | inline |
| llvm::MCRegisterInfo::getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) const | llvm::MCRegisterInfo | |
| getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const | llvm::TargetRegisterInfo | virtual |
| getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const | llvm::TargetRegisterInfo | |
| getMinimalPhysRegClassLLT(MCRegister Reg, LLT Ty=LLT()) const | llvm::TargetRegisterInfo | |
| getName(MCRegister RegNo) const | llvm::MCRegisterInfo | inline |
| getNoPreservedMask() const | llvm::TargetRegisterInfo | inlinevirtual |
| getNumRegClasses() const | llvm::TargetRegisterInfo | inline |
| getNumRegPressureSets() const =0 | llvm::TargetRegisterInfo | pure virtual |
| getNumRegs() const | llvm::MCRegisterInfo | inline |
| getNumRegUnits() const | llvm::MCRegisterInfo | inline |
| getNumSubRegIndices() const | llvm::MCRegisterInfo | inline |
| getNumSupportedRegs(const MachineFunction &) const | llvm::TargetRegisterInfo | inlinevirtual |
| getOffsetOpcodes(const StackOffset &Offset, SmallVectorImpl< uint64_t > &Ops) const | llvm::TargetRegisterInfo | virtual |
| getPhysRegBaseClass(MCRegister Reg) const | llvm::TargetRegisterInfo | inlinevirtual |
| getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const | llvm::TargetRegisterInfo | inlinevirtual |
| getProgramCounter() const | llvm::MCRegisterInfo | inline |
| getRARegister() const | llvm::MCRegisterInfo | inline |
| getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const | llvm::TargetRegisterInfo | virtual |
| getRegAsmName(MCRegister Reg) const | llvm::TargetRegisterInfo | inlinevirtual |
| getRegClass(unsigned i) const | llvm::TargetRegisterInfo | inline |
| getRegClassInfo(const TargetRegisterClass &RC) const | llvm::TargetRegisterInfo | inlineprotected |
| getRegClassName(const TargetRegisterClass *Class) const | llvm::TargetRegisterInfo | inline |
| llvm::MCRegisterInfo::getRegClassName(const MCRegisterClass *Class) const | llvm::MCRegisterInfo | inline |
| getRegClassPressureSets(const TargetRegisterClass *RC) const =0 | llvm::TargetRegisterInfo | pure virtual |
| getRegClassWeight(const TargetRegisterClass *RC) const =0 | llvm::TargetRegisterInfo | pure virtual |
| getRegisterCosts(const MachineFunction &MF) const | llvm::TargetRegisterInfo | inline |
| getRegisterCostTableIndex(const MachineFunction &MF) const | llvm::TargetRegisterInfo | inlineprotectedvirtual |
| getRegMaskNames() const =0 | llvm::TargetRegisterInfo | pure virtual |
| getRegMasks() const =0 | llvm::TargetRegisterInfo | pure virtual |
| getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const | llvm::TargetRegisterInfo | inlinevirtual |
| getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const =0 | llvm::TargetRegisterInfo | pure virtual |
| getRegPressureSetName(unsigned Idx) const =0 | llvm::TargetRegisterInfo | pure virtual |
| getRegPressureSetScore(const MachineFunction &MF, unsigned PSetID) const | llvm::TargetRegisterInfo | inlinevirtual |
| getRegSizeInBits(const TargetRegisterClass &RC) const | llvm::TargetRegisterInfo | inline |
| getRegSizeInBits(Register Reg, const MachineRegisterInfo &MRI) const | llvm::TargetRegisterInfo | |
| getRegUnitPressureSets(unsigned RegUnit) const =0 | llvm::TargetRegisterInfo | pure virtual |
| getRegUnitWeight(unsigned RegUnit) const =0 | llvm::TargetRegisterInfo | pure virtual |
| getReservedRegs(const MachineFunction &MF) const =0 | llvm::TargetRegisterInfo | pure virtual |
| getSEHRegNum(MCRegister RegNum) const | llvm::MCRegisterInfo | |
| getSpillAlign(const TargetRegisterClass &RC) const | llvm::TargetRegisterInfo | inline |
| getSpillSize(const TargetRegisterClass &RC) const | llvm::TargetRegisterInfo | inline |
| getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const | llvm::TargetRegisterInfo | inlinevirtual |
| getSubReg(MCRegister Reg, unsigned Idx) const | llvm::TargetRegisterInfo | inline |
| getSubRegIdxOffset(unsigned Idx) const | llvm::TargetRegisterInfo | |
| getSubRegIdxSize(unsigned Idx) const | llvm::TargetRegisterInfo | |
| getSubRegIndex(MCRegister RegNo, MCRegister SubRegNo) const | llvm::MCRegisterInfo | |
| getSubRegIndexLaneMask(unsigned SubIdx) const | llvm::TargetRegisterInfo | inline |
| getSubRegIndexName(unsigned SubIdx) const | llvm::TargetRegisterInfo | inline |
| getSubRegisterClass(const TargetRegisterClass *SuperRC, unsigned SubRegIdx) const | llvm::TargetRegisterInfo | inlinevirtual |
| hasRegUnit(MCRegister Reg, Register RegUnit) const | llvm::TargetRegisterInfo | inline |
| hasReservedSpillSlot(const MachineFunction &MF, Register Reg, int &FrameIdx) const | llvm::TargetRegisterInfo | inlinevirtual |
| hasStackRealignment(const MachineFunction &MF) const | llvm::TargetRegisterInfo | inline |
| InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA, unsigned PC, const MCRegisterClass *C, unsigned NC, const MCPhysReg(*RURoots)[2], unsigned NRU, const int16_t *DL, const LaneBitmask *RUMS, const char *Strings, const char *ClassStrings, const uint16_t *SubIndices, unsigned NumIndices, const uint16_t *RET) | llvm::MCRegisterInfo | inline |
| isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const | llvm::TargetRegisterInfo | inlinevirtual |
| isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const | llvm::TargetRegisterInfo | inlinevirtual |
| isCalleeSavedPhysReg(MCRegister PhysReg, const MachineFunction &MF) const | llvm::TargetRegisterInfo | virtual |
| isCallerPreservedPhysReg(MCRegister PhysReg, const MachineFunction &MF) const | llvm::TargetRegisterInfo | inlinevirtual |
| isConstantPhysReg(MCRegister PhysReg) const | llvm::TargetRegisterInfo | inlinevirtual |
| isDivergentRegClass(const TargetRegisterClass *RC) const | llvm::TargetRegisterInfo | inlinevirtual |
| isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const | llvm::TargetRegisterInfo | inlinevirtual |
| isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const | llvm::TargetRegisterInfo | inlinevirtual |
| isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const | llvm::TargetRegisterInfo | inlinevirtual |
| isInAllocatableClass(MCRegister RegNo) const | llvm::TargetRegisterInfo | inline |
| isInlineAsmReadOnlyReg(const MachineFunction &MF, unsigned PhysReg) const | llvm::TargetRegisterInfo | inlinevirtual |
| isNonallocatableRegisterCalleeSave(MCRegister Reg) const | llvm::TargetRegisterInfo | inlinevirtual |
| isSubRegister(MCRegister RegA, MCRegister RegB) const | llvm::MCRegisterInfo | inline |
| isSubRegisterEq(MCRegister RegA, MCRegister RegB) const | llvm::MCRegisterInfo | inline |
| isSuperOrSubRegisterEq(MCRegister RegA, MCRegister RegB) const | llvm::MCRegisterInfo | inline |
| isSuperRegister(MCRegister RegA, MCRegister RegB) const | llvm::MCRegisterInfo | inline |
| isSuperRegisterEq(MCRegister RegA, MCRegister RegB) const | llvm::MCRegisterInfo | inline |
| isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const | llvm::TargetRegisterInfo | inline |
| isTypeLegalForClass(const TargetRegisterClass &RC, LLT T) const | llvm::TargetRegisterInfo | inline |
| isUniformReg(const MachineRegisterInfo &MRI, const RegisterBankInfo &RBI, Register Reg) const | llvm::TargetRegisterInfo | inlinevirtual |
| legalclasstypes_begin(const TargetRegisterClass &RC) const | llvm::TargetRegisterInfo | inline |
| legalclasstypes_end(const TargetRegisterClass &RC) const | llvm::TargetRegisterInfo | inline |
| lookThruCopyLike(Register SrcReg, const MachineRegisterInfo *MRI) const | llvm::TargetRegisterInfo | virtual |
| lookThruSingleUseCopyChain(Register SrcReg, const MachineRegisterInfo *MRI) const | llvm::TargetRegisterInfo | virtual |
| mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair *Map, unsigned Size, bool isEH) | llvm::MCRegisterInfo | inline |
| mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size, bool isEH) | llvm::MCRegisterInfo | inline |
| mapLLVMRegToCVReg(MCRegister LLVMReg, int CVReg) | llvm::MCRegisterInfo | inline |
| mapLLVMRegToSEHReg(MCRegister LLVMReg, int SEHReg) | llvm::MCRegisterInfo | inline |
| markSuperRegs(BitVector &RegisterSet, MCRegister Reg) const | llvm::TargetRegisterInfo | |
| materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const | llvm::TargetRegisterInfo | inlinevirtual |
| needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const | llvm::TargetRegisterInfo | inlinevirtual |
| operator[](MCRegister RegNo) const | llvm::MCRegisterInfo | inline |
| prependOffsetExpression(const DIExpression *Expr, unsigned PrependFlags, const StackOffset &Offset) const | llvm::TargetRegisterInfo | |
| regclass_begin() const | llvm::TargetRegisterInfo | inline |
| regclass_end() const | llvm::TargetRegisterInfo | inline |
| regclass_iterator typedef | llvm::TargetRegisterInfo | |
| regclasses() const | llvm::TargetRegisterInfo | inline |
| regClassPriorityTrumpsGlobalness(const MachineFunction &MF) const | llvm::TargetRegisterInfo | inlinevirtual |
| regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const | llvm::TargetRegisterInfo | |
| regsOverlap(Register RegA, Register RegB) const | llvm::TargetRegisterInfo | inline |
| llvm::MCRegisterInfo::regsOverlap(MCRegister RegA, MCRegister RegB) const | llvm::MCRegisterInfo | |
| regunits(MCRegister Reg) const | llvm::MCRegisterInfo | inline |
| requiresFrameIndexReplacementScavenging(const MachineFunction &MF) const | llvm::TargetRegisterInfo | inlinevirtual |
| requiresFrameIndexScavenging(const MachineFunction &MF) const | llvm::TargetRegisterInfo | inlinevirtual |
| requiresRegisterScavenging(const MachineFunction &MF) const | llvm::TargetRegisterInfo | inlinevirtual |
| requiresVirtualBaseRegisters(const MachineFunction &MF) const | llvm::TargetRegisterInfo | inlinevirtual |
| resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const | llvm::TargetRegisterInfo | inlinevirtual |
| reverseComposeSubRegIndexLaneMask(unsigned IdxA, LaneBitmask LaneMask) const | llvm::TargetRegisterInfo | inline |
| reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const | llvm::TargetRegisterInfo | inlineprotectedvirtual |
| reverseLocalAssignment() const | llvm::TargetRegisterInfo | inlinevirtual |
| saveScavengerRegister(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, Register Reg) const | llvm::TargetRegisterInfo | inlinevirtual |
| shouldAnalyzePhysregInMachineLoopInfo(MCRegister R) const | llvm::TargetRegisterInfo | inlinevirtual |
| shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const | llvm::TargetRegisterInfo | inlinevirtual |
| shouldRealignStack(const MachineFunction &MF) const | llvm::TargetRegisterInfo | virtual |
| shouldRegionSplitForVirtReg(const MachineFunction &MF, const LiveInterval &VirtReg) const | llvm::TargetRegisterInfo | virtual |
| shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const | llvm::TargetRegisterInfo | virtual |
| shouldUseDeferredSpillingForVirtReg(const MachineFunction &MF, const LiveInterval &VirtReg) const | llvm::TargetRegisterInfo | inlinevirtual |
| shouldUseLastChanceRecoloringForVirtReg(const MachineFunction &MF, const LiveInterval &VirtReg) const | llvm::TargetRegisterInfo | inlinevirtual |
| sub_and_superregs_inclusive(MCRegister Reg) const | llvm::MCRegisterInfo | inline |
| subregs(MCRegister Reg) const | llvm::MCRegisterInfo | inline |
| subregs_inclusive(MCRegister Reg) const | llvm::MCRegisterInfo | inline |
| superregs(MCRegister Reg) const | llvm::MCRegisterInfo | inline |
| superregs_inclusive(MCRegister Reg) const | llvm::MCRegisterInfo | inline |
| TargetRegisterInfo(const TargetRegisterInfoDesc *ID, regclass_iterator RCB, regclass_iterator RCE, const char *const *SRINames, const SubRegCoveredBits *SubIdxRanges, const LaneBitmask *SRILaneMasks, LaneBitmask CoveringLanes, const RegClassInfo *const RCIs, const MVT::SimpleValueType *const RCVTLists, unsigned Mode=0) | llvm::TargetRegisterInfo | protected |
| trackLivenessAfterRegAlloc(const MachineFunction &MF) const | llvm::TargetRegisterInfo | inlinevirtual |
| updateRegAllocHint(Register Reg, Register NewReg, MachineFunction &MF) const | llvm::TargetRegisterInfo | inlinevirtual |
| useFPForScavengingIndex(const MachineFunction &MF) const | llvm::TargetRegisterInfo | inlinevirtual |
| vt_iterator typedef | llvm::TargetRegisterInfo | |
| ~TargetRegisterInfo() | llvm::TargetRegisterInfo | protectedvirtual |
1.9.6