LLVM  9.0.0svn
llvm::X86InstrInfo Member List

This is the complete list of members for llvm::X86InstrInfo, including all inherited members.

analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const overridellvm::X86InstrInfo
analyzeBranchPredicate(MachineBasicBlock &MBB, TargetInstrInfo::MachineBranchPredicate &MBP, bool AllowModify=false) const overridellvm::X86InstrInfo
analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const overridellvm::X86InstrInfo
areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const overridellvm::X86InstrInfo
breakPartialRegDependency(MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const overridellvm::X86InstrInfo
buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const overridellvm::X86InstrInfo
canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const overridellvm::X86InstrInfo
canMakeTailCallConditional(SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const overridellvm::X86InstrInfo
classifyLEAReg(MachineInstr &MI, const MachineOperand &Src, unsigned LEAOpcode, bool AllowSP, unsigned &NewSrc, bool &isKill, MachineOperand &ImplicitOp, LiveVariables *LV) constllvm::X86InstrInfo
commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned CommuteOpIdx1, unsigned CommuteOpIdx2) const overridellvm::X86InstrInfoprotected
convertToThreeAddress(MachineFunction::iterator &MFI, MachineInstr &MI, LiveVariables *LV) const overridellvm::X86InstrInfo
copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const overridellvm::X86InstrInfo
decomposeMachineOperandsTargetFlags(unsigned TF) const overridellvm::X86InstrInfo
expandPostRAPseudo(MachineInstr &MI) const overridellvm::X86InstrInfo
findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const overridellvm::X86InstrInfo
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr) const overridellvm::X86InstrInfo
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, LiveIntervals *LIS=nullptr) const overridellvm::X86InstrInfo
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, unsigned OpNum, ArrayRef< MachineOperand > MOs, MachineBasicBlock::iterator InsertPt, unsigned Size, unsigned Alignment, bool AllowCommute) constllvm::X86InstrInfo
getExecutionDomain(const MachineInstr &MI) const overridellvm::X86InstrInfo
getExecutionDomainCustom(const MachineInstr &MI) constllvm::X86InstrInfo
getFMA3OpcodeToCommuteOperands(const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2, const X86InstrFMA3Group &FMA3Group) constllvm::X86InstrInfo
getFrameAdjustment(const MachineInstr &I) constllvm::X86InstrInfoinline
getGlobalBaseReg(MachineFunction *MF) constllvm::X86InstrInfo
getMemOperandWithOffset(MachineInstr &LdSt, MachineOperand *&BaseOp, int64_t &Offset, const TargetRegisterInfo *TRI) const overridellvm::X86InstrInfo
getNoop(MCInst &NopInst) const overridellvm::X86InstrInfo
getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const overridellvm::X86InstrInfo
getOutliningCandidateInfo(std::vector< outliner::Candidate > &RepeatedSequenceLocs) const overridellvm::X86InstrInfovirtual
getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const overridellvm::X86InstrInfo
getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const overridellvm::X86InstrInfo
getRegisterInfo() constllvm::X86InstrInfoinline
getSerializableDirectMachineOperandTargetFlags() const overridellvm::X86InstrInfo
getSPAdjust(const MachineInstr &MI) const overridellvm::X86InstrInfo
getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum, const TargetRegisterInfo *TRI) const overridellvm::X86InstrInfo
hasHighOperandLatency(const TargetSchedModel &SchedModel, const MachineRegisterInfo *MRI, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const overridellvm::X86InstrInfo
hasLiveCondCodeDef(MachineInstr &MI) constllvm::X86InstrInfo
hasReassociableOperands(const MachineInstr &Inst, const MachineBasicBlock *MBB) const overridellvm::X86InstrInfo
insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const overridellvm::X86InstrInfo
insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, const outliner::Candidate &C) const overridellvm::X86InstrInfo
insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const overridellvm::X86InstrInfo
isAssociativeAndCommutative(const MachineInstr &Inst) const overridellvm::X86InstrInfo
isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const overridellvm::X86InstrInfo
isCopyInstrImpl(const MachineInstr &MI, const MachineOperand *&Source, const MachineOperand *&Destination) const overridellvm::X86InstrInfoprotected
isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const overridellvm::X86InstrInfo
isHighLatencyDef(int opc) const overridellvm::X86InstrInfo
isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const overridellvm::X86InstrInfo
isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const overridellvm::X86InstrInfo
isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const overridellvm::X86InstrInfo
isReallyTriviallyReMaterializable(const MachineInstr &MI, AliasAnalysis *AA) const overridellvm::X86InstrInfo
isSafeToClobberEFLAGS(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) constllvm::X86InstrInfoinline
isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const overridellvm::X86InstrInfo
isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const overridellvm::X86InstrInfo
isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const overridellvm::X86InstrInfo
isStoreToStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const overridellvm::X86InstrInfo
isSubregFoldable() const overridellvm::X86InstrInfoinline
isUnconditionalTailCall(const MachineInstr &MI) const overridellvm::X86InstrInfo
isUnpredicatedTerminator(const MachineInstr &MI) const overridellvm::X86InstrInfo
loadRegFromAddr(MachineFunction &MF, unsigned DestReg, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, ArrayRef< MachineMemOperand *> MMOs, SmallVectorImpl< MachineInstr *> &NewMIs) constllvm::X86InstrInfo
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const overridellvm::X86InstrInfo
optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const overridellvm::X86InstrInfo
optimizeLoadInstr(MachineInstr &MI, const MachineRegisterInfo *MRI, unsigned &FoldAsLoadDefReg, MachineInstr *&DefMI) const overridellvm::X86InstrInfo
reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const overridellvm::X86InstrInfo
removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const overridellvm::X86InstrInfo
replaceBranchWithTailCall(MachineBasicBlock &MBB, SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const overridellvm::X86InstrInfo
reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const overridellvm::X86InstrInfo
setExecutionDomain(MachineInstr &MI, unsigned Domain) const overridellvm::X86InstrInfo
setExecutionDomainCustom(MachineInstr &MI, unsigned Domain) constllvm::X86InstrInfo
setFrameAdjustment(MachineInstr &I, int64_t V) constllvm::X86InstrInfoinline
setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const overridellvm::X86InstrInfo
shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const overridellvm::X86InstrInfo
storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, ArrayRef< MachineMemOperand *> MMOs, SmallVectorImpl< MachineInstr *> &NewMIs) constllvm::X86InstrInfo
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const overridellvm::X86InstrInfo
unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr *> &NewMIs) const overridellvm::X86InstrInfo
unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, SmallVectorImpl< SDNode *> &NewNodes) const overridellvm::X86InstrInfo
useMachineCombiner() const overridellvm::X86InstrInfoinline
X86InstrInfo(X86Subtarget &STI)llvm::X86InstrInfoexplicit