LLVM  6.0.0svn
Public Member Functions | Protected Member Functions | List of all members
llvm::X86InstrInfo Class Referencefinal

#include "Target/X86/X86InstrInfo.h"

Inheritance diagram for llvm::X86InstrInfo:
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Public Member Functions

 X86InstrInfo (X86Subtarget &STI)
 
const X86RegisterInfogetRegisterInfo () const
 getRegisterInfo - TargetInstrInfo is a superset of MRegister info. More...
 
int64_t getFrameAdjustment (const MachineInstr &I) const
 Returns the stack pointer adjustment that happens inside the frame setup..destroy sequence (e.g. More...
 
void setFrameAdjustment (MachineInstr &I, int64_t V) const
 Sets the stack pointer adjustment made inside the frame made up by this instruction. More...
 
int getSPAdjust (const MachineInstr &MI) const override
 getSPAdjust - This returns the stack pointer adjustment made by this instruction. More...
 
bool isCoalescableExtInstr (const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override
 isCoalescableExtInstr - Return true if the instruction is a "coalescable" extension instruction. More...
 
unsigned isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const override
 
unsigned isLoadFromStackSlotPostFE (const MachineInstr &MI, int &FrameIndex) const override
 isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well. More...
 
unsigned isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const override
 
unsigned isStoreToStackSlotPostFE (const MachineInstr &MI, int &FrameIndex) const override
 isStoreToStackSlotPostFE - Check for post-frame ptr elimination stack locations as well. More...
 
bool isReallyTriviallyReMaterializable (const MachineInstr &MI, AliasAnalysis *AA) const override
 
void reMaterialize (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const override
 
bool classifyLEAReg (MachineInstr &MI, const MachineOperand &Src, unsigned LEAOpcode, bool AllowSP, unsigned &NewSrc, bool &isKill, bool &isUndef, MachineOperand &ImplicitOp, LiveVariables *LV) const
 Given an operand within a MachineInstr, insert preceding code to put it into the right format for a particular kind of LEA instruction. More...
 
MachineInstrconvertToThreeAddress (MachineFunction::iterator &MFI, MachineInstr &MI, LiveVariables *LV) const override
 convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag. More...
 
bool findCommutedOpIndices (MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
 Returns true iff the routine could find two commutable operands in the given machine instruction. More...
 
bool findFMA3CommutedOpIndices (const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2, const X86InstrFMA3Group &FMA3Group) const
 Returns true if the routine could find two commutable operands in the given FMA instruction MI. More...
 
unsigned getFMA3OpcodeToCommuteOperands (const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2, const X86InstrFMA3Group &FMA3Group) const
 Returns an adjusted FMA opcode that must be used in FMA instruction that performs the same computations as the given MI but which has the operands SrcOpIdx1 and SrcOpIdx2 commuted. More...
 
bool isUnpredicatedTerminator (const MachineInstr &MI) const override
 
bool isUnconditionalTailCall (const MachineInstr &MI) const override
 
bool canMakeTailCallConditional (SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const override
 
void replaceBranchWithTailCall (MachineBasicBlock &MBB, SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const override
 
bool analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
 
bool getMemOpBaseRegImmOfs (MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, const TargetRegisterInfo *TRI) const override
 
bool analyzeBranchPredicate (MachineBasicBlock &MBB, TargetInstrInfo::MachineBranchPredicate &MBP, bool AllowModify=false) const override
 
unsigned removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
 
unsigned insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
 
bool canInsertSelect (const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override
 
void insertSelect (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
 
void copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
 
void storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
 
void storeRegToAddr (MachineFunction &MF, unsigned SrcReg, bool isKill, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, MachineInstr::mmo_iterator MMOBegin, MachineInstr::mmo_iterator MMOEnd, SmallVectorImpl< MachineInstr *> &NewMIs) const
 
void loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
 
void loadRegFromAddr (MachineFunction &MF, unsigned DestReg, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, MachineInstr::mmo_iterator MMOBegin, MachineInstr::mmo_iterator MMOEnd, SmallVectorImpl< MachineInstr *> &NewMIs) const
 
bool expandPostRAPseudo (MachineInstr &MI) const override
 
bool isSubregFoldable () const override
 Check whether the target can fold a load that feeds a subreg operand (or a subreg operand that feeds a store). More...
 
MachineInstrfoldMemoryOperandImpl (MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr) const override
 foldMemoryOperand - If this target supports it, fold a load or store of the specified stack slot into the specified machine instruction for the specified operand(s). More...
 
MachineInstrfoldMemoryOperandImpl (MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, LiveIntervals *LIS=nullptr) const override
 foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address, not just from a specific stack slot. More...
 
bool unfoldMemoryOperand (MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr *> &NewMIs) const override
 unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a store into two or more instruction. More...
 
bool unfoldMemoryOperand (SelectionDAG &DAG, SDNode *N, SmallVectorImpl< SDNode *> &NewNodes) const override
 
unsigned getOpcodeAfterMemoryUnfold (unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const override
 getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new instruction after load / store are unfolded from an instruction of the specified opcode. More...
 
bool areLoadsFromSameBasePtr (SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
 areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address. More...
 
bool shouldScheduleLoadsNear (SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override
 shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePtr) if two loads should be scheduled togther. More...
 
void getNoop (MCInst &NopInst) const override
 Return the noop instruction to use for a noop. More...
 
bool reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
 
bool isSafeToMoveRegClassDefs (const TargetRegisterClass *RC) const override
 isSafeToMoveRegClassDefs - Return true if it's safe to move a machine instruction that defines the specified register class. More...
 
bool isSafeToClobberEFLAGS (MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const
 isSafeToClobberEFLAGS - Return true if it's safe insert an instruction tha would clobber the EFLAGS condition register. More...
 
bool hasLiveCondCodeDef (MachineInstr &MI) const
 True if MI has a condition code def, e.g. More...
 
unsigned getGlobalBaseReg (MachineFunction *MF) const
 getGlobalBaseReg - Return a virtual register initialized with the the global base register value. More...
 
std::pair< uint16_t, uint16_t > getExecutionDomain (const MachineInstr &MI) const override
 
void setExecutionDomain (MachineInstr &MI, unsigned Domain) const override
 
unsigned getPartialRegUpdateClearance (const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override
 Inform the ExecutionDepsFix pass how many idle instructions we would like before a partial register update. More...
 
unsigned getUndefRegClearance (const MachineInstr &MI, unsigned &OpNum, const TargetRegisterInfo *TRI) const override
 Inform the ExecutionDepsFix pass how many idle instructions we would like before certain undef register reads. More...
 
void breakPartialRegDependency (MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override
 
MachineInstrfoldMemoryOperandImpl (MachineFunction &MF, MachineInstr &MI, unsigned OpNum, ArrayRef< MachineOperand > MOs, MachineBasicBlock::iterator InsertPt, unsigned Size, unsigned Alignment, bool AllowCommute) const
 
bool isHighLatencyDef (int opc) const override
 
bool hasHighOperandLatency (const TargetSchedModel &SchedModel, const MachineRegisterInfo *MRI, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
 
bool useMachineCombiner () const override
 
bool isAssociativeAndCommutative (const MachineInstr &Inst) const override
 
bool hasReassociableOperands (const MachineInstr &Inst, const MachineBasicBlock *MBB) const override
 
void setSpecialOperandAttr (MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const override
 This is an architecture-specific helper function of reassociateOps. More...
 
bool analyzeCompare (const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const override
 analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue. More...
 
bool optimizeCompareInstr (MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const override
 optimizeCompareInstr - Check if there exists an earlier instruction that operates on the same source operands and sets flags in the same way as Compare; remove Compare if possible. More...
 
MachineInstroptimizeLoadInstr (MachineInstr &MI, const MachineRegisterInfo *MRI, unsigned &FoldAsLoadDefReg, MachineInstr *&DefMI) const override
 optimizeLoadInstr - Try to remove the load by folding it to a register operand at the use. More...
 
std::pair< unsigned, unsigneddecomposeMachineOperandsTargetFlags (unsigned TF) const override
 
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags () const override
 
virtual MachineOutlinerInfo getOutlininingCandidateInfo (std::vector< std::pair< MachineBasicBlock::iterator, MachineBasicBlock::iterator >> &RepeatedSequenceLocs) const override
 
bool isFunctionSafeToOutlineFrom (MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
 
llvm::X86GenInstrInfo::MachineOutlinerInstrType getOutliningType (MachineInstr &MI) const override
 
void insertOutlinerEpilogue (MachineBasicBlock &MBB, MachineFunction &MF, const MachineOutlinerInfo &MInfo) const override
 
void insertOutlinerPrologue (MachineBasicBlock &MBB, MachineFunction &MF, const MachineOutlinerInfo &MInfo) const override
 
MachineBasicBlock::iterator insertOutlinedCall (Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, const MachineOutlinerInfo &MInfo) const override
 

Protected Member Functions

MachineInstrcommuteInstructionImpl (MachineInstr &MI, bool NewMI, unsigned CommuteOpIdx1, unsigned CommuteOpIdx2) const override
 Commutes the operands in the given instruction by changing the operands order and/or changing the instruction's opcode and/or the immediate value operand. More...
 

Detailed Description

Definition at line 144 of file X86InstrInfo.h.

Constructor & Destructor Documentation

◆ X86InstrInfo()

X86InstrInfo::X86InstrInfo ( X86Subtarget STI)
explicit

Member Function Documentation

◆ analyzeBranch()

bool X86InstrInfo::analyzeBranch ( MachineBasicBlock MBB,
MachineBasicBlock *&  TBB,
MachineBasicBlock *&  FBB,
SmallVectorImpl< MachineOperand > &  Cond,
bool  AllowModify 
) const
override

Definition at line 6342 of file X86InstrInfo.cpp.

◆ analyzeBranchPredicate()

bool X86InstrInfo::analyzeBranchPredicate ( MachineBasicBlock MBB,
TargetInstrInfo::MachineBranchPredicate MBP,
bool  AllowModify = false 
) const
override

◆ analyzeCompare()

bool X86InstrInfo::analyzeCompare ( const MachineInstr MI,
unsigned SrcReg,
unsigned SrcReg2,
int &  CmpMask,
int &  CmpValue 
) const
override

analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue.

Return true if the comparison instruction can be analyzed.

Definition at line 7049 of file X86InstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), and llvm::MachineOperand::isImm().

◆ areLoadsFromSameBasePtr()

bool X86InstrInfo::areLoadsFromSameBasePtr ( SDNode Load1,
SDNode Load2,
int64_t &  Offset1,
int64_t &  Offset2 
) const
override

areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address.

It should only return true if the base pointers are the same and the only differences between the two addresses are the offset. It also returns the offsets by reference.

Definition at line 9149 of file X86InstrInfo.cpp.

References llvm::X86::AddrBaseReg, llvm::X86::AddrDisp, llvm::X86::AddrIndexReg, llvm::X86::AddrScaleAmt, llvm::X86::AddrSegmentReg, llvm::dyn_cast(), llvm::SDNode::getMachineOpcode(), llvm::SDNode::getOperand(), llvm::ConstantSDNode::getSExtValue(), I, and llvm::SDNode::isMachineOpcode().

◆ breakPartialRegDependency()

void X86InstrInfo::breakPartialRegDependency ( MachineInstr MI,
unsigned  OpNum,
const TargetRegisterInfo TRI 
) const
override

◆ canInsertSelect()

bool X86InstrInfo::canInsertSelect ( const MachineBasicBlock MBB,
ArrayRef< MachineOperand Cond,
unsigned  TrueReg,
unsigned  FalseReg,
int &  CondCycles,
int &  TrueCycles,
int &  FalseCycles 
) const
override

◆ canMakeTailCallConditional()

bool X86InstrInfo::canMakeTailCallConditional ( SmallVectorImpl< MachineOperand > &  Cond,
const MachineInstr TailCall 
) const
override

◆ classifyLEAReg()

bool X86InstrInfo::classifyLEAReg ( MachineInstr MI,
const MachineOperand Src,
unsigned  LEAOpcode,
bool  AllowSP,
unsigned NewSrc,
bool isKill,
bool isUndef,
MachineOperand ImplicitOp,
LiveVariables LV 
) const

Given an operand within a MachineInstr, insert preceding code to put it into the right format for a particular kind of LEA instruction.

This may involve using an appropriate super-register instead (with an implicit use of the original) or creating a new virtual register and inserting COPY instructions to get the data into the right class.

Reference parameters are set to indicate how caller should add this operand to the LEA instruction.

Definition at line 4347 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::addRegOffset(), llvm::addRegReg(), llvm::BuildMI(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::RegState::Define, llvm::getDeadRegState(), llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getImm(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::getKillRegState(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::LiveVariables::getVarInfo(), llvm::getX86SubSuperRegister(), llvm::X86Subtarget::is64Bit(), llvm::MachineOperand::isDead(), llvm::MachineOperand::isKill(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineOperand::isUndef(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::RegState::Kill, llvm::LiveVariables::VarInfo::Kills, llvm_unreachable, MI, llvm::LiveVariables::replaceKillInstruction(), llvm::MachineOperand::setImplicit(), and llvm::RegState::Undef.

Referenced by convertToThreeAddress().

◆ commuteInstructionImpl()

MachineInstr * X86InstrInfo::commuteInstructionImpl ( MachineInstr MI,
bool  NewMI,
unsigned  CommuteOpIdx1,
unsigned  CommuteOpIdx2 
) const
overrideprotected

Commutes the operands in the given instruction by changing the operands order and/or changing the instruction's opcode and/or the immediate value operand.

The arguments 'CommuteOpIdx1' and 'CommuteOpIdx2' specify the operands to be commuted.

Do not call this method for a non-commutable instruction or non-commutable operands. Even though the instruction is commutable, the method may still fail to commute the operands, null pointer is returned in such cases.

Definition at line 5155 of file X86InstrInfo.cpp.

References llvm::MachineFunction::CloneMachineInstr(), llvm::TargetInstrInfo::commuteInstructionImpl(), commuteVPTERNLOG(), llvm::MachineOperand::CreateImm(), getCommutedVPERMV3Opcode(), llvm::X86InstrFMA3Info::getFMA3Group(), getFMA3OpcodeToCommuteOperands(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::X86Subtarget::hasSSE2(), llvm::X86Subtarget::hasSSE41(), isCommutableVPERMV3Instruction(), llvm_unreachable, llvm::BitmaskEnumDetail::Mask(), MI, and llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Size.

◆ convertToThreeAddress()

MachineInstr * X86InstrInfo::convertToThreeAddress ( MachineFunction::iterator MFI,
MachineInstr MI,
LiveVariables LV 
) const
override

convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag.

This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag.

When this flag is set, the target may be able to convert a two-address instruction into a true three-address instruction on demand. This allows the X86 target (for example) to convert ADD and SHL instructions into LEA instructions if they would require register copies due to two-addressness.

This method returns a null pointer if the transformation cannot be performed, otherwise it returns the new instruction.

Definition at line 4523 of file X86InstrInfo.cpp.

References llvm::ARM_AM::add, llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::addOffset(), llvm::MachineInstrBuilder::addReg(), llvm::addRegReg(), assert(), llvm::BuildMI(), classifyLEAReg(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::MachineOperand::CreateReg(), llvm::MachineInstr::getDebugLoc(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::getKillRegState(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), getTruncatedShiftCount(), llvm::getUndefRegState(), hasLiveCondCodeDef(), llvm::X86Subtarget::is64Bit(), is64Bit(), llvm::MachineOperand::isDead(), llvm::MachineOperand::isKill(), isTruncatedShiftCountForLEA(), llvm::MachineOperand::isUndef(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm_unreachable, MI, and llvm::LiveVariables::replaceKillInstruction().

◆ copyPhysReg()

void X86InstrInfo::copyPhysReg ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
const DebugLoc DL,
unsigned  DestReg,
unsigned  SrcReg,
bool  KillSrc 
) const
override

◆ decomposeMachineOperandsTargetFlags()

std::pair< unsigned, unsigned > X86InstrInfo::decomposeMachineOperandsTargetFlags ( unsigned  TF) const
override

Definition at line 10562 of file X86InstrInfo.cpp.

◆ expandPostRAPseudo()

bool X86InstrInfo::expandPostRAPseudo ( MachineInstr MI) const
override

◆ findCommutedOpIndices()

bool X86InstrInfo::findCommutedOpIndices ( MachineInstr MI,
unsigned SrcOpIdx1,
unsigned SrcOpIdx2 
) const
override

Returns true iff the routine could find two commutable operands in the given machine instruction.

The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their input values can be re-defined in this method only if the input values are not pre-defined, which is designated by the special value 'CommuteAnyOperandIndex' assigned to it. If both of indices are pre-defined and refer to some operands, then the method simply returns true if the corresponding operands are commutable and returns false otherwise.

For example, calling this method this way: unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex; findCommutedOpIndices(MI, Op1, Op2); can be interpreted as a query asking to find an operand that would be commutable with the operand#1.

Definition at line 5623 of file X86InstrInfo.cpp.

References llvm::X86II::EVEX_K, llvm::X86II::EVEX_Z, llvm::TargetInstrInfo::findCommutedOpIndices(), findFMA3CommutedOpIndices(), llvm::MachineInstr::getDesc(), llvm::X86InstrFMA3Info::getFMA3Group(), llvm::MachineOperand::getImm(), llvm::MCInstrDesc::getNumDefs(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MCInstrDesc::getOperandConstraint(), llvm::X86Subtarget::hasSSE41(), llvm::MCInstrDesc::isCommutable(), llvm::MachineOperand::isReg(), llvm::MCOI::TIED_TO, and llvm::MCInstrDesc::TSFlags.

Referenced by foldMemoryOperandImpl().

◆ findFMA3CommutedOpIndices()

bool X86InstrInfo::findFMA3CommutedOpIndices ( const MachineInstr MI,
unsigned SrcOpIdx1,
unsigned SrcOpIdx2,
const X86InstrFMA3Group FMA3Group 
) const

Returns true if the routine could find two commutable operands in the given FMA instruction MI.

Otherwise, returns false.

SrcOpIdx1 and SrcOpIdx2 are INPUT and OUTPUT arguments. The output indices of the commuted operands are returned in these arguments. Also, the input values of these arguments may be preset either to indices of operands that must be commuted or be equal to a special value 'CommuteAnyOperandIndex' which means that the corresponding operand index is not set and this method is free to pick any of available commutable operands. The parameter FMA3Group keeps the reference to the group of relative FMA3 opcodes including register/memory forms of 132/213/231 opcodes.

For example, calling this method this way: unsigned Idx1 = 1, Idx2 = CommuteAnyOperandIndex; findFMA3CommutedOpIndices(MI, Idx1, Idx2, FMA3Group); can be interpreted as a query asking if the operand #1 can be swapped with any other available operand (e.g. operand #2, operand #3, etc.).

The returned FMA opcode may differ from the opcode in the given MI. For example, commuting the operands #1 and #3 in the following FMA FMA213 #1, #2, #3 results into instruction with adjusted opcode: FMA231 #3, #2, #1

Definition at line 5529 of file X86InstrInfo.cpp.

References llvm::MachineInstr::getDesc(), getFMA3OpcodeToCommuteOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::X86II::isKMasked(), llvm::X86II::isKMergeMasked(), llvm::isMem(), and llvm::MCInstrDesc::TSFlags.

Referenced by findCommutedOpIndices().

◆ foldMemoryOperandImpl() [1/3]

MachineInstr * X86InstrInfo::foldMemoryOperandImpl ( MachineFunction MF,
MachineInstr MI,
ArrayRef< unsigned Ops,
MachineBasicBlock::iterator  InsertPt,
int  FrameIndex,
LiveIntervals LIS = nullptr 
) const
override

foldMemoryOperand - If this target supports it, fold a load or store of the specified stack slot into the specified machine instruction for the specified operand(s).

If this is possible, the target should perform the folding and return true, otherwise it should return false. If it folds the instruction, it is likely that the MachineInstruction the iterator references has been changed.

Definition at line 8556 of file X86InstrInfo.cpp.

References llvm::MachineOperand::ChangeToImmediate(), llvm::MachineOperand::CreateFI(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getFunction(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getSubReg(), hasPartialRegUpdate(), llvm::MachineOperand::isDef(), NoFusing, llvm::Function::optForSize(), llvm::MachineInstr::setDesc(), and SubReg.

Referenced by computeBytesPoppedByCalleeForSRet(), and foldMemoryOperandImpl().

◆ foldMemoryOperandImpl() [2/3]

MachineInstr * X86InstrInfo::foldMemoryOperandImpl ( MachineFunction MF,
MachineInstr MI,
ArrayRef< unsigned Ops,
MachineBasicBlock::iterator  InsertPt,
MachineInstr LoadMI,
LiveIntervals LIS = nullptr 
) const
override

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address, not just from a specific stack slot.

Definition at line 8740 of file X86InstrInfo.cpp.

References llvm::X86::AddrNumOperands, llvm::SmallVectorImpl< T >::append(), C, llvm::MachineOperand::ChangeToImmediate(), llvm::MachineOperand::CreateCPI(), llvm::MachineOperand::CreateImm(), llvm::MachineOperand::CreateReg(), foldMemoryOperandImpl(), llvm::ISD::FrameIndex, llvm::VectorType::get(), getAlignment(), llvm::Constant::getAllOnesValue(), llvm::TargetMachine::getCodeModel(), llvm::MachineFunction::getConstantPool(), llvm::MachineConstantPool::getConstantPoolIndex(), llvm::Function::getContext(), llvm::MachineInstr::getDesc(), llvm::Type::getDoubleTy(), llvm::Type::getFloatTy(), llvm::MachineFunction::getFunction(), llvm::Type::getInt32Ty(), llvm::Constant::getNullValue(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getSubReg(), llvm::MachineFunction::getTarget(), llvm::MachineInstr::hasOneMemOperand(), hasPartialRegUpdate(), isLoadFromStackSlot(), isNonFoldablePartialRegisterLoad(), llvm::TargetMachine::isPositionIndependent(), llvm::CodeModel::Kernel, llvm::MachineInstr::memoperands_begin(), NoFusing, llvm::MachineInstr::operands_begin(), llvm::Function::optForSize(), llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::MachineInstr::setDesc(), and llvm::CodeModel::Small.

◆ foldMemoryOperandImpl() [3/3]

MachineInstr * X86InstrInfo::foldMemoryOperandImpl ( MachineFunction MF,
MachineInstr MI,
unsigned  OpNum,
ArrayRef< MachineOperand MOs,
MachineBasicBlock::iterator  InsertPt,
unsigned  Size,
unsigned  Alignment,
bool  AllowCommute 
) const

◆ getExecutionDomain()

std::pair< uint16_t, uint16_t > X86InstrInfo::getExecutionDomain ( const MachineInstr MI) const
override

◆ getFMA3OpcodeToCommuteOperands()

unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands ( const MachineInstr MI,
unsigned  SrcOpIdx1,
unsigned  SrcOpIdx2,
const X86InstrFMA3Group FMA3Group 
) const

Returns an adjusted FMA opcode that must be used in FMA instruction that performs the same computations as the given MI but which has the operands SrcOpIdx1 and SrcOpIdx2 commuted.

It may return 0 if it is unsafe to commute the operands. Note that a machine instruction (instead of its opcode) is passed as the first parameter to make it possible to analyze the instruction's uses and commute the first operand of FMA even when it seems unsafe when you look at the opcode. For example, it is Ok to commute the first operand of VFMADD*SD_Int, if ONLY the lowest 64-bit element of the result is used.

The returned FMA opcode may differ from the opcode in the given MI. For example, commuting the operands #1 and #3 in the following FMA FMA213 #1, #2, #3 results into instruction with adjusted opcode: FMA231 #3, #2, #1

Definition at line 4971 of file X86InstrInfo.cpp.

References llvm::MachineInstr::getDesc(), llvm::X86InstrFMA3Group::getMem132Opcode(), llvm::X86InstrFMA3Group::getMem213Opcode(), llvm::X86InstrFMA3Group::getMem231Opcode(), llvm::MachineInstr::getOpcode(), llvm::X86InstrFMA3Group::getReg132Opcode(), llvm::X86InstrFMA3Group::getReg213Opcode(), llvm::X86InstrFMA3Group::getReg231Opcode(), getThreeSrcCommuteCase(), llvm::X86InstrFMA3Group::isIntrinsic(), llvm::X86InstrFMA3Group::isRegOpcodeFromGroup(), std::swap(), and llvm::MCInstrDesc::TSFlags.

Referenced by commuteInstructionImpl(), and findFMA3CommutedOpIndices().

◆ getFrameAdjustment()

int64_t llvm::X86InstrInfo::getFrameAdjustment ( const MachineInstr I) const
inline

Returns the stack pointer adjustment that happens inside the frame setup..destroy sequence (e.g.

by pushes, or inside the callee).

Definition at line 189 of file X86InstrInfo.h.

References assert(), llvm::MachineOperand::getImm(), and llvm::MachineInstr::getOperand().

Referenced by llvm::X86FrameLowering::eliminateCallFramePseudoInstr(), and getSPAdjust().

◆ getGlobalBaseReg()

unsigned X86InstrInfo::getGlobalBaseReg ( MachineFunction MF) const

getGlobalBaseReg - Return a virtual register initialized with the the global base register value.

Return a virtual register initialized with the the global base register value.

Output instructions required to initialize the register in the function entry block, if necessary.

Output instructions required to initialize the register in the function entry block, if necessary.

TODO: Eliminate this and move the code to X86MachineFunctionInfo.

Definition at line 9405 of file X86InstrInfo.cpp.

References assert(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MachineFunction::getInfo(), llvm::MachineFunction::getRegInfo(), and llvm::PPCISD::GlobalBaseReg.

Referenced by createPHIsForCMOVsInSinkBB(), and llvm::X86TargetLowering::needsFixedCatchObjects().

◆ getMemOpBaseRegImmOfs()

bool X86InstrInfo::getMemOpBaseRegImmOfs ( MachineInstr LdSt,
unsigned BaseReg,
int64_t &  Offset,
const TargetRegisterInfo TRI 
) const
override

◆ getNoop()

void X86InstrInfo::getNoop ( MCInst NopInst) const
override

Return the noop instruction to use for a noop.

Definition at line 9957 of file X86InstrInfo.cpp.

References llvm::MCInst::setOpcode().

◆ getOpcodeAfterMemoryUnfold()

unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold ( unsigned  Opc,
bool  UnfoldLoad,
bool  UnfoldStore,
unsigned LoadRegIndex = nullptr 
) const
override

getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new instruction after load / store are unfolded from an instruction of the specified opcode.

It returns zero if the specified unfolding is not possible. If LoadRegIndex is non-null, it is filled in with the operand index of the operand which will hold the register holding the loaded value.

Definition at line 9131 of file X86InstrInfo.cpp.

References I, TB_FOLDED_LOAD, TB_FOLDED_STORE, and TB_INDEX_MASK.

◆ getOutliningType()

X86GenInstrInfo::MachineOutlinerInstrType X86InstrInfo::getOutliningType ( MachineInstr MI) const
override

◆ getOutlininingCandidateInfo()

X86GenInstrInfo::MachineOutlinerInfo X86InstrInfo::getOutlininingCandidateInfo ( std::vector< std::pair< MachineBasicBlock::iterator, MachineBasicBlock::iterator >> &  RepeatedSequenceLocs) const
overridevirtual

Definition at line 10815 of file X86InstrInfo.cpp.

References MachineOutlinerDefault, MachineOutlinerTailCall, and second.

◆ getPartialRegUpdateClearance()

unsigned X86InstrInfo::getPartialRegUpdateClearance ( const MachineInstr MI,
unsigned  OpNum,
const TargetRegisterInfo TRI 
) const
override

◆ getRegisterInfo()

const X86RegisterInfo& llvm::X86InstrInfo::getRegisterInfo ( ) const
inline

getRegisterInfo - TargetInstrInfo is a superset of MRegister info.

As such, whenever a client has an instance of instruction info, it should always be able to get register info as well (through this method).

Definition at line 185 of file X86InstrInfo.h.

Referenced by analyzeBranchPredicate(), copyPhysReg(), createPHIsForCMOVsInSinkBB(), expandPostRAPseudo(), optimizeCompareInstr(), and replaceBranchWithTailCall().

◆ getSerializableDirectMachineOperandTargetFlags()

ArrayRef< std::pair< unsigned, const char * > > X86InstrInfo::getSerializableDirectMachineOperandTargetFlags ( ) const
override

◆ getSPAdjust()

int X86InstrInfo::getSPAdjust ( const MachineInstr MI) const
override

◆ getUndefRegClearance()

unsigned X86InstrInfo::getUndefRegClearance ( const MachineInstr MI,
unsigned OpNum,
const TargetRegisterInfo TRI 
) const
override

Inform the ExecutionDepsFix pass how many idle instructions we would like before certain undef register reads.

This catches the VCVTSI2SD family of instructions:

vcvtsi2sdq rax, xmm0<undef>, xmm14

We should to be careful not to catch VXOR idioms which are presumably handled specially in the pipeline:

vxorps xmm1<undef>, xmm1<undef>, xmm1

Like getPartialRegUpdateClearance, this makes a strong assumption that the high bits that are passed-through are not live.

Definition at line 8188 of file X86InstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), hasUndefRegUpdate(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineOperand::isUndef(), and UndefRegClearance.

◆ hasHighOperandLatency()

bool X86InstrInfo::hasHighOperandLatency ( const TargetSchedModel SchedModel,
const MachineRegisterInfo MRI,
const MachineInstr DefMI,
unsigned  DefIdx,
const MachineInstr UseMI,
unsigned  UseIdx 
) const
override

Definition at line 10271 of file X86InstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), and isHighLatencyDef().

◆ hasLiveCondCodeDef()

bool X86InstrInfo::hasLiveCondCodeDef ( MachineInstr MI) const

True if MI has a condition code def, e.g.

True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.

EFLAGS, that is not marked dead.

Definition at line 4316 of file X86InstrInfo.cpp.

References llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isDead(), llvm::MachineOperand::isDef(), and llvm::MachineOperand::isReg().

Referenced by convertToThreeAddress().

◆ hasReassociableOperands()

bool X86InstrInfo::hasReassociableOperands ( const MachineInstr Inst,
const MachineBasicBlock MBB 
) const
override

◆ insertBranch()

unsigned X86InstrInfo::insertBranch ( MachineBasicBlock MBB,
MachineBasicBlock TBB,
MachineBasicBlock FBB,
ArrayRef< MachineOperand Cond,
const DebugLoc DL,
int *  BytesAdded = nullptr 
) const
override

◆ insertOutlinedCall()

MachineBasicBlock::iterator X86InstrInfo::insertOutlinedCall ( Module M,
MachineBasicBlock MBB,
MachineBasicBlock::iterator It,
MachineFunction MF,
const MachineOutlinerInfo &  MInfo 
) const
override

◆ insertOutlinerEpilogue()

void X86InstrInfo::insertOutlinerEpilogue ( MachineBasicBlock MBB,
MachineFunction MF,
const MachineOutlinerInfo &  MInfo 
) const
override

◆ insertOutlinerPrologue()

void X86InstrInfo::insertOutlinerPrologue ( MachineBasicBlock MBB,
MachineFunction MF,
const MachineOutlinerInfo &  MInfo 
) const
override

Definition at line 10918 of file X86InstrInfo.cpp.

◆ insertSelect()

void X86InstrInfo::insertSelect ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
const DebugLoc DL,
unsigned  DstReg,
ArrayRef< MachineOperand Cond,
unsigned  TrueReg,
unsigned  FalseReg 
) const
override

◆ isAssociativeAndCommutative()

bool X86InstrInfo::isAssociativeAndCommutative ( const MachineInstr Inst) const
override

◆ isCoalescableExtInstr()

bool X86InstrInfo::isCoalescableExtInstr ( const MachineInstr MI,
unsigned SrcReg,
unsigned DstReg,
unsigned SubIdx 
) const
override

isCoalescableExtInstr - Return true if the instruction is a "coalescable" extension instruction.

That is, it's like a copy where it's legal for the source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns true, then it's expected the pre-extension value is available as a subreg of the result register. This also returns the sub-register index in SubIdx.

Definition at line 3751 of file X86InstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::X86Subtarget::is64Bit(), LLVM_FALLTHROUGH, and llvm_unreachable.

◆ isFunctionSafeToOutlineFrom()

bool X86InstrInfo::isFunctionSafeToOutlineFrom ( MachineFunction MF,
bool  OutlineFromLinkOnceODRs 
) const
override

◆ isHighLatencyDef()

bool X86InstrInfo::isHighLatencyDef ( int  opc) const
override

Definition at line 9961 of file X86InstrInfo.cpp.

Referenced by hasHighOperandLatency().

◆ isLoadFromStackSlot()

unsigned X86InstrInfo::isLoadFromStackSlot ( const MachineInstr MI,
int &  FrameIndex 
) const
override

◆ isLoadFromStackSlotPostFE()

unsigned X86InstrInfo::isLoadFromStackSlotPostFE ( const MachineInstr MI,
int &  FrameIndex 
) const
override

isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well.

This uses a heuristic so it isn't reliable for correctness.

Definition at line 4032 of file X86InstrInfo.cpp.

References llvm::NVPTXISD::Dummy, llvm::MachineInstr::getOpcode(), isFrameLoadOpcode(), and isLoadFromStackSlot().

◆ isReallyTriviallyReMaterializable()

bool X86InstrInfo::isReallyTriviallyReMaterializable ( const MachineInstr MI,
AliasAnalysis AA 
) const
override

◆ isSafeToClobberEFLAGS()

bool X86InstrInfo::isSafeToClobberEFLAGS ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I 
) const

isSafeToClobberEFLAGS - Return true if it's safe insert an instruction tha would clobber the EFLAGS condition register.

Note the result may be conservative. If it cannot definitely determine the safety after visiting a few instructions in each direction it assumes it's not safe.

Definition at line 4200 of file X86InstrInfo.cpp.

References B, llvm::MachineBasicBlock::begin(), llvm::MachineOperand::clobbersPhysReg(), E, llvm::MachineBasicBlock::end(), llvm::MachineOperand::getReg(), I, llvm::MachineOperand::isDead(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isKill(), llvm::MachineBasicBlock::isLiveIn(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isRegMask(), llvm::MachineOperand::isUse(), and llvm::MachineBasicBlock::successors().

Referenced by reMaterialize().

◆ isSafeToMoveRegClassDefs()

bool X86InstrInfo::isSafeToMoveRegClassDefs ( const TargetRegisterClass RC) const
override

isSafeToMoveRegClassDefs - Return true if it's safe to move a machine instruction that defines the specified register class.

Definition at line 9392 of file X86InstrInfo.cpp.

Referenced by reverseBranchCondition().

◆ isStoreToStackSlot()

unsigned X86InstrInfo::isStoreToStackSlot ( const MachineInstr MI,
int &  FrameIndex 
) const
override

◆ isStoreToStackSlotPostFE()

unsigned X86InstrInfo::isStoreToStackSlotPostFE ( const MachineInstr MI,
int &  FrameIndex 
) const
override

isStoreToStackSlotPostFE - Check for post-frame ptr elimination stack locations as well.

This uses a heuristic so it isn't reliable for correctness.

Definition at line 4054 of file X86InstrInfo.cpp.

References llvm::NVPTXISD::Dummy, llvm::MachineInstr::getOpcode(), isFrameStoreOpcode(), and isStoreToStackSlot().

◆ isSubregFoldable()

bool llvm::X86InstrInfo::isSubregFoldable ( ) const
inlineoverride

Check whether the target can fold a load that feeds a subreg operand (or a subreg operand that feeds a store).

Definition at line 401 of file X86InstrInfo.h.

References DefMI, I, MRI, N, llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Size, and UseMI.

◆ isUnconditionalTailCall()

bool X86InstrInfo::isUnconditionalTailCall ( const MachineInstr MI) const
override

Definition at line 6071 of file X86InstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

◆ isUnpredicatedTerminator()

bool X86InstrInfo::isUnpredicatedTerminator ( const MachineInstr MI) const
override

◆ loadRegFromAddr()

void X86InstrInfo::loadRegFromAddr ( MachineFunction MF,
unsigned  DestReg,
SmallVectorImpl< MachineOperand > &  Addr,
const TargetRegisterClass RC,
MachineInstr::mmo_iterator  MMOBegin,
MachineInstr::mmo_iterator  MMOEnd,
SmallVectorImpl< MachineInstr *> &  NewMIs 
) const

◆ loadRegFromStackSlot()

void X86InstrInfo::loadRegFromStackSlot ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
unsigned  DestReg,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI 
) const
override

◆ optimizeCompareInstr()

bool X86InstrInfo::optimizeCompareInstr ( MachineInstr CmpInstr,
unsigned  SrcReg,
unsigned  SrcReg2,
int  CmpMask,
int  CmpValue,
const MachineRegisterInfo MRI 
) const
override

optimizeCompareInstr - Check if there exists an earlier instruction that operates on the same source operands and sets flags in the same way as Compare; remove Compare if possible.

Check if there exists an earlier instruction that operates on the same source operands and sets flags in the same way as Compare; remove Compare if possible.

Definition at line 7295 of file X86InstrInfo.cpp.

References assert(), llvm::X86::COND_A, llvm::X86::COND_AE, llvm::X86::COND_B, llvm::X86::COND_BE, llvm::X86::COND_E, llvm::X86::COND_G, llvm::X86::COND_GE, llvm::X86::COND_INVALID, llvm::X86::COND_L, llvm::X86::COND_LE, llvm::X86::COND_NE, llvm::X86::COND_NO, llvm::X86::COND_O, llvm::tgtok::Def, E, llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), llvm::X86::getCMovFromCond(), GetCondBranchFromCond(), getCondFromBranchOpc(), llvm::X86::getCondFromCMovOpc(), getCondFromSETOpc(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), GetOppositeBranchCondition(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), getRegisterInfo(), llvm::TargetRegisterInfo::getRegSizeInBits(), llvm::MachineInstrBundleIterator< Ty, IsReverse >::getReverse(), llvm::X86::getSETFromCond(), getSwappedCondition(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::MachineInstr::hasOneMemOperand(), I, llvm::MachineBasicBlock::insert(), llvm::MachineInstr::isBranch(), llvm::MachineOperand::isDef(), isDefConvertible(), isRedundantFlagInstr(), llvm::MachineOperand::isReg(), isUseDefConvertible(), llvm::MachineInstr::killsRegister(), llvm_unreachable, MI, llvm::MachineInstr::modifiesRegister(), llvm::MachineInstr::readsRegister(), llvm::MachineInstr::registerDefIsDead(), llvm::MachineBasicBlock::remove(), llvm::MachineInstr::RemoveOperand(), llvm::MachineBasicBlock::rend(), llvm::MachineInstr::setDesc(), llvm::MachineOperand::setIsDead(), llvm::Successor, llvm::MachineBasicBlock::successors(), and llvm::MachineRegisterInfo::use_nodbg_empty().

◆ optimizeLoadInstr()

MachineInstr * X86InstrInfo::optimizeLoadInstr ( MachineInstr MI,
const MachineRegisterInfo MRI,
unsigned FoldAsLoadDefReg,
MachineInstr *&  DefMI 
) const
override

optimizeLoadInstr - Try to remove the load by folding it to a register operand at the use.

Try to remove the load by folding it to a register operand at the use.

We fold the load instructions if and only if the def and use are in the same BB. We only look at one load and see whether it can be folded into MI. FoldAsLoadDefReg is the virtual register defined by the load we are trying to fold. DefMI returns the machine instruction that defines FoldAsLoadDefReg, and the function returns the machine instruction generated due to folding.

We fold the load instructions if load defines a virtual register, the virtual register is used once in the same BB, and the instructions in-between do not load or store, and have no side effects.

Definition at line 7587 of file X86InstrInfo.cpp.

References assert(), llvm::SmallVectorBase::empty(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineRegisterInfo::getVRegDef(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isReg(), llvm::MachineInstr::isSafeToMove(), and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().

◆ reMaterialize()

void X86InstrInfo::reMaterialize ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
unsigned  DestReg,
unsigned  SubIdx,
const MachineInstr Orig,
const TargetRegisterInfo TRI 
) const
override

◆ removeBranch()

unsigned X86InstrInfo::removeBranch ( MachineBasicBlock MBB,
int *  BytesRemoved = nullptr 
) const
override

◆ replaceBranchWithTailCall()

void X86InstrInfo::replaceBranchWithTailCall ( MachineBasicBlock MBB,
SmallVectorImpl< MachineOperand > &  Cond,
const MachineInstr TailCall 
) const
override

◆ reverseBranchCondition()

bool X86InstrInfo::reverseBranchCondition ( SmallVectorImpl< MachineOperand > &  Cond) const
override

◆ setExecutionDomain()

void X86InstrInfo::setExecutionDomain ( MachineInstr MI,
unsigned  Domain 
) const
override

◆ setFrameAdjustment()

void llvm::X86InstrInfo::setFrameAdjustment ( MachineInstr I,
int64_t  V 
) const
inline

Sets the stack pointer adjustment made inside the frame made up by this instruction.

Definition at line 198 of file X86InstrInfo.h.

References assert(), llvm::ISD::FrameIndex, llvm::MachineInstr::getOperand(), MI, llvm::MachineOperand::setImm(), and llvm::MipsISD::TailCall.

◆ setSpecialOperandAttr()

void X86InstrInfo::setSpecialOperandAttr ( MachineInstr OldMI1,
MachineInstr OldMI2,
MachineInstr NewMI1,
MachineInstr NewMI2 
) const
override

This is an architecture-specific helper function of reassociateOps.

Set special operand attributes for new instructions after reassociation.

Definition at line 10523 of file X86InstrInfo.cpp.

References assert(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isDead(), llvm::MachineOperand::isReg(), and llvm::MachineOperand::setIsDead().

◆ shouldScheduleLoadsNear()

bool X86InstrInfo::shouldScheduleLoadsNear ( SDNode Load1,
SDNode Load2,
int64_t  Offset1,
int64_t  Offset2,
unsigned  NumLoads 
) const
override

shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePtr) if two loads should be scheduled togther.

On some targets if two loads are loading from addresses in the same cache line, it's better if they are scheduled together. This function takes two integers that represent the load offsets from the common base address. It returns true if it decides it's desirable to schedule the two loads together. "NumLoads" is the number of loads that have already been scheduled after Load1.

Definition at line 9335 of file X86InstrInfo.cpp.

References assert(), llvm::MVT::f32, llvm::MVT::f64, llvm::SDNode::getMachineOpcode(), llvm::EVT::getSimpleVT(), llvm::SDNode::getValueType(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, reverseBranchCondition(), and llvm::MVT::SimpleTy.

◆ storeRegToAddr()

void X86InstrInfo::storeRegToAddr ( MachineFunction MF,
unsigned  SrcReg,
bool  isKill,
SmallVectorImpl< MachineOperand > &  Addr,
const TargetRegisterClass RC,
MachineInstr::mmo_iterator  MMOBegin,
MachineInstr::mmo_iterator  MMOEnd,
SmallVectorImpl< MachineInstr *> &  NewMIs 
) const

◆ storeRegToStackSlot()

void X86InstrInfo::storeRegToStackSlot ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
unsigned  SrcReg,
bool  isKill,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI 
) const
override

◆ unfoldMemoryOperand() [1/2]

bool X86InstrInfo::unfoldMemoryOperand ( MachineFunction MF,
MachineInstr MI,
unsigned  Reg,
bool  UnfoldLoad,
bool  UnfoldStore,
SmallVectorImpl< MachineInstr *> &  NewMIs 
) const
override

◆ unfoldMemoryOperand() [2/2]

bool X86InstrInfo::unfoldMemoryOperand ( SelectionDAG DAG,
SDNode N,
SmallVectorImpl< SDNode *> &  NewNodes 
) const
override

◆ useMachineCombiner()

bool llvm::X86InstrInfo::useMachineCombiner ( ) const
inlineoverride

Definition at line 518 of file X86InstrInfo.h.

References llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align.


The documentation for this class was generated from the following files: