LLVM  6.0.0svn
Public Member Functions | List of all members
llvm::XCoreInstrInfo Class Reference

#include "Target/XCore/XCoreInstrInfo.h"

Inheritance diagram for llvm::XCoreInstrInfo:
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Public Member Functions

 XCoreInstrInfo ()
 
const TargetRegisterInfogetRegisterInfo () const
 getRegisterInfo - TargetInstrInfo is a superset of MRegister info. More...
 
unsigned isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const override
 isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot. More...
 
unsigned isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const override
 isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot. More...
 
bool analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
 AnalyzeBranch - Analyze the branching code at the end of MBB, returning true if it cannot be understood (e.g. More...
 
unsigned insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
 
unsigned removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
 
void copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
 
void storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
 
void loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
 
bool reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
 
MachineBasicBlock::iterator loadImmediate (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Reg, uint64_t Value) const
 

Detailed Description

Definition at line 25 of file XCoreInstrInfo.h.

Constructor & Destructor Documentation

◆ XCoreInstrInfo()

XCoreInstrInfo::XCoreInstrInfo ( )

Definition at line 49 of file XCoreInstrInfo.cpp.

Member Function Documentation

◆ analyzeBranch()

bool XCoreInstrInfo::analyzeBranch ( MachineBasicBlock MBB,
MachineBasicBlock *&  TBB,
MachineBasicBlock *&  FBB,
SmallVectorImpl< MachineOperand > &  Cond,
bool  AllowModify 
) const
override

AnalyzeBranch - Analyze the branching code at the end of MBB, returning true if it cannot be understood (e.g.

it's a switch dispatch or isn't implemented for a target). Upon success, this returns false and returns with the following information in various cases:

  1. If this block ends with no branches (it just falls through to its succ) just return false, leaving TBB/FBB null.
  2. If this block ends with only an unconditional branch, it sets TBB to be the destination block.
  3. If this block ends with an conditional branch and it falls through to an successor block, it sets TBB to be the branch destination block and a list of operands that evaluate the condition. These operands can be passed to other TargetInstrInfo methods to create new branches.
  4. If this block ends with an conditional branch and an unconditional block, it returns the 'true' destination in TBB, the 'false' destination in FBB, and a list of operands that evaluate the condition. These operands can be passed to other TargetInstrInfo methods to create new branches.

Note that removeBranch and insertBranch must be implemented to support cases where this method returns success.

Definition at line 190 of file XCoreInstrInfo.cpp.

References llvm::MachineBasicBlock::begin(), llvm::XCore::COND_INVALID, llvm::MachineOperand::CreateImm(), llvm::MachineBasicBlock::end(), GetCondFromBranchOpc(), llvm::MachineBasicBlock::getLastNonDebugInstr(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), I, IsBR_JT(), IsBRU(), and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().

Referenced by getRegisterInfo().

◆ copyPhysReg()

void XCoreInstrInfo::copyPhysReg ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
const DebugLoc DL,
unsigned  DestReg,
unsigned  SrcReg,
bool  KillSrc 
) const
override

◆ getRegisterInfo()

const TargetRegisterInfo& llvm::XCoreInstrInfo::getRegisterInfo ( ) const
inline

getRegisterInfo - TargetInstrInfo is a superset of MRegister info.

As such, whenever a client has an instance of instruction info, it should always be able to get register info as well (through this method).

Definition at line 35 of file XCoreInstrInfo.h.

References analyzeBranch(), copyPhysReg(), llvm::ISD::FrameIndex, I, insertBranch(), isLoadFromStackSlot(), isStoreToStackSlot(), loadImmediate(), loadRegFromStackSlot(), MI, removeBranch(), reverseBranchCondition(), and storeRegToStackSlot().

Referenced by llvm::XCoreSubtarget::getRegisterInfo().

◆ insertBranch()

unsigned XCoreInstrInfo::insertBranch ( MachineBasicBlock MBB,
MachineBasicBlock TBB,
MachineBasicBlock FBB,
ArrayRef< MachineOperand Cond,
const DebugLoc DL,
int *  BytesAdded = nullptr 
) const
override

◆ isLoadFromStackSlot()

unsigned XCoreInstrInfo::isLoadFromStackSlot ( const MachineInstr MI,
int &  FrameIndex 
) const
override

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot.

If not, return 0. This predicate must return 0 if the instruction has any side effects other than loading from the stack slot.

Definition at line 63 of file XCoreInstrInfo.cpp.

References llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), and isZeroImm().

Referenced by getRegisterInfo().

◆ isStoreToStackSlot()

unsigned XCoreInstrInfo::isStoreToStackSlot ( const MachineInstr MI,
int &  FrameIndex 
) const
override

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot.

If not, return 0. This predicate must return 0 if the instruction has any side effects other than storing to the stack slot.

Definition at line 83 of file XCoreInstrInfo.cpp.

References llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), and isZeroImm().

Referenced by getRegisterInfo().

◆ loadImmediate()

MachineBasicBlock::iterator XCoreInstrInfo::loadImmediate ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
unsigned  Reg,
uint64_t  Value 
) const

◆ loadRegFromStackSlot()

void XCoreInstrInfo::loadRegFromStackSlot ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
unsigned  DestReg,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI 
) const
override

◆ removeBranch()

unsigned XCoreInstrInfo::removeBranch ( MachineBasicBlock MBB,
int *  BytesRemoved = nullptr 
) const
override

◆ reverseBranchCondition()

bool XCoreInstrInfo::reverseBranchCondition ( SmallVectorImpl< MachineOperand > &  Cond) const
override

◆ storeRegToStackSlot()

void XCoreInstrInfo::storeRegToStackSlot ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
unsigned  SrcReg,
bool  isKill,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI 
) const
override

The documentation for this class was generated from the following files: