LLVM  6.0.0svn
Enumerations
llvm::AMDGPUISD Namespace Reference

Enumerations

enum  NodeType : unsigned {
  FIRST_NUMBER = ISD::BUILTIN_OP_END, UMUL, BRANCH_COND, CALL,
  TC_RETURN, TRAP, IF, ELSE,
  LOOP, ENDPGM, RETURN_TO_EPILOG, RET_FLAG,
  DWORDADDR, FRACT, CLAMP, SETCC,
  SETREG, FMA_W_CHAIN, FMUL_W_CHAIN, COS_HW,
  SIN_HW, FMAX_LEGACY, FMIN_LEGACY, FMAX3,
  SMAX3, UMAX3, FMIN3, SMIN3,
  UMIN3, FMED3, SMED3, UMED3,
  URECIP, DIV_SCALE, DIV_FMAS, DIV_FIXUP,
  FMAD_FTZ, TRIG_PREOP, RCP, RSQ,
  RCP_LEGACY, RSQ_LEGACY, FMUL_LEGACY, RSQ_CLAMP,
  LDEXP, FP_CLASS, DOT4, CARRY,
  BORROW, BFE_U32, BFE_I32, BFI,
  BFM, FFBH_U32, FFBH_I32, FFBL_B32,
  MUL_U24, MUL_I24, MULHI_U24, MULHI_I24,
  MAD_U24, MAD_I24, MUL_LOHI_I24, MUL_LOHI_U24,
  TEXTURE_FETCH, EXPORT, EXPORT_DONE, R600_EXPORT,
  CONST_ADDRESS, REGISTER_LOAD, REGISTER_STORE, SAMPLE,
  SAMPLEB, SAMPLED, SAMPLEL, CVT_F32_UBYTE0,
  CVT_F32_UBYTE1, CVT_F32_UBYTE2, CVT_F32_UBYTE3, CVT_PKRTZ_F16_F32,
  FP_TO_FP16, FP16_ZEXT, BUILD_VERTICAL_VECTOR, CONST_DATA_PTR,
  INIT_EXEC, INIT_EXEC_FROM_INPUT, SENDMSG, SENDMSGHALT,
  INTERP_MOV, INTERP_P1, INTERP_P2, PC_ADD_REL_OFFSET,
  KILL, DUMMY_CHAIN, FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE, STORE_MSKOR,
  LOAD_CONSTANT, TBUFFER_STORE_FORMAT, TBUFFER_STORE_FORMAT_X3, TBUFFER_LOAD_FORMAT,
  ATOMIC_CMP_SWAP, ATOMIC_INC, ATOMIC_DEC, BUFFER_LOAD,
  BUFFER_LOAD_FORMAT, LAST_AMDGPU_ISD_NUMBER
}
 

Enumeration Type Documentation

◆ NodeType

Enumerator
FIRST_NUMBER 
UMUL 
BRANCH_COND 
CALL 
TC_RETURN 
TRAP 
IF 
ELSE 
LOOP 
ENDPGM 
RETURN_TO_EPILOG 
RET_FLAG 
DWORDADDR 
FRACT 
CLAMP 

CLAMP value between 0.0 and 1.0.

NaN clamped to 0, following clamp output modifier behavior with dx10_enable.

SETCC 
SETREG 
FMA_W_CHAIN 
FMUL_W_CHAIN 
COS_HW 
SIN_HW 
FMAX_LEGACY 
FMIN_LEGACY 
FMAX3 
SMAX3 
UMAX3 
FMIN3 
SMIN3 
UMIN3 
FMED3 
SMED3 
UMED3 
URECIP 
DIV_SCALE 
DIV_FMAS 
DIV_FIXUP 
FMAD_FTZ 
TRIG_PREOP 
RCP 
RSQ 
RCP_LEGACY 
RSQ_LEGACY 
FMUL_LEGACY 
RSQ_CLAMP 
LDEXP 
FP_CLASS 
DOT4 
CARRY 
BORROW 
BFE_U32 
BFE_I32 
BFI 
BFM 
FFBH_U32 
FFBH_I32 
FFBL_B32 
MUL_U24 
MUL_I24 
MULHI_U24 
MULHI_I24 
MAD_U24 
MAD_I24 
MUL_LOHI_I24 
MUL_LOHI_U24 
TEXTURE_FETCH 
EXPORT 
EXPORT_DONE 
R600_EXPORT 
CONST_ADDRESS 
REGISTER_LOAD 
REGISTER_STORE 
SAMPLE 
SAMPLEB 
SAMPLED 
SAMPLEL 
CVT_F32_UBYTE0 
CVT_F32_UBYTE1 
CVT_F32_UBYTE2 
CVT_F32_UBYTE3 
CVT_PKRTZ_F16_F32 
FP_TO_FP16 
FP16_ZEXT 
BUILD_VERTICAL_VECTOR 

This node is for VLIW targets and it is used to represent a vector that is stored in consecutive registers with the same channel.

For example: |X |Y|Z|W| T0|v.x| | | | T1|v.y| | | | T2|v.z| | | | T3|v.w| | | |

CONST_DATA_PTR 

Pointer to the start of the shader's constant data.

INIT_EXEC 
INIT_EXEC_FROM_INPUT 
SENDMSG 
SENDMSGHALT 
INTERP_MOV 
INTERP_P1 
INTERP_P2 
PC_ADD_REL_OFFSET 
KILL 
DUMMY_CHAIN 
FIRST_MEM_OPCODE_NUMBER 
STORE_MSKOR 
LOAD_CONSTANT 
TBUFFER_STORE_FORMAT 
TBUFFER_STORE_FORMAT_X3 
TBUFFER_LOAD_FORMAT 
ATOMIC_CMP_SWAP 
ATOMIC_INC 
ATOMIC_DEC 
BUFFER_LOAD 
BUFFER_LOAD_FORMAT 
LAST_AMDGPU_ISD_NUMBER 

Definition at line 291 of file AMDGPUISelLowering.h.