LLVM 19.0.0git
Enumerations | Functions
llvm::X86 Namespace Reference

Define some predicates that are used for node matching. More...

Enumerations

enum  ProcessorVendors : unsigned { VENDOR_DUMMY , VENDOR_OTHER }
 
enum  ProcessorTypes : unsigned { CPU_TYPE_DUMMY , CPU_TYPE_MAX }
 
enum  ProcessorSubtypes : unsigned { CPU_SUBTYPE_DUMMY , CPU_SUBTYPE_MAX }
 
enum  ProcessorFeatures { CPU_FEATURE_MAX }
 
enum  CPUKind {
  CK_None , CK_i386 , CK_i486 , CK_WinChipC6 ,
  CK_WinChip2 , CK_C3 , CK_i586 , CK_Pentium ,
  CK_PentiumMMX , CK_PentiumPro , CK_i686 , CK_Pentium2 ,
  CK_Pentium3 , CK_PentiumM , CK_C3_2 , CK_Yonah ,
  CK_Pentium4 , CK_Prescott , CK_Nocona , CK_Core2 ,
  CK_Penryn , CK_Bonnell , CK_Silvermont , CK_Goldmont ,
  CK_GoldmontPlus , CK_Tremont , CK_Gracemont , CK_Nehalem ,
  CK_Westmere , CK_SandyBridge , CK_IvyBridge , CK_Haswell ,
  CK_Broadwell , CK_SkylakeClient , CK_SkylakeServer , CK_Cascadelake ,
  CK_Cooperlake , CK_Cannonlake , CK_IcelakeClient , CK_Rocketlake ,
  CK_IcelakeServer , CK_Tigerlake , CK_SapphireRapids , CK_Alderlake ,
  CK_Raptorlake , CK_Meteorlake , CK_Arrowlake , CK_ArrowlakeS ,
  CK_Lunarlake , CK_Pantherlake , CK_Sierraforest , CK_Grandridge ,
  CK_Graniterapids , CK_GraniterapidsD , CK_Emeraldrapids , CK_Clearwaterforest ,
  CK_KNL , CK_KNM , CK_Lakemont , CK_K6 ,
  CK_K6_2 , CK_K6_3 , CK_Athlon , CK_AthlonXP ,
  CK_K8 , CK_K8SSE3 , CK_AMDFAM10 , CK_BTVER1 ,
  CK_BTVER2 , CK_BDVER1 , CK_BDVER2 , CK_BDVER3 ,
  CK_BDVER4 , CK_ZNVER1 , CK_ZNVER2 , CK_ZNVER3 ,
  CK_ZNVER4 , CK_x86_64 , CK_x86_64_v2 , CK_x86_64_v3 ,
  CK_x86_64_v4 , CK_Geode
}
 
enum  {
  BX_SI = 500 , BX_DI = 501 , BP_SI = 502 , BP_DI = 503 ,
  sib = 504 , sib64 = 505
}
 
enum  {
  AddrBaseReg = 0 , AddrScaleAmt = 1 , AddrIndexReg = 2 , AddrDisp = 3 ,
  AddrSegmentReg = 4 , AddrNumOperands = 5
}
 
enum  STATIC_ROUNDING {
  TO_NEAREST_INT = 0 , TO_NEG_INF = 1 , TO_POS_INF = 2 , TO_ZERO = 3 ,
  CUR_DIRECTION = 4 , NO_EXC = 8
}
 AVX512 static rounding constants. More...
 
enum  IPREFIXES {
  IP_NO_PREFIX = 0 , IP_HAS_OP_SIZE = 1U << 0 , IP_HAS_AD_SIZE = 1U << 1 , IP_HAS_REPEAT_NE = 1U << 2 ,
  IP_HAS_REPEAT = 1U << 3 , IP_HAS_LOCK = 1U << 4 , IP_HAS_NOTRACK = 1U << 5 , IP_USE_VEX = 1U << 6 ,
  IP_USE_VEX2 = 1U << 7 , IP_USE_VEX3 = 1U << 8 , IP_USE_EVEX = 1U << 9 , IP_USE_DISP8 = 1U << 10 ,
  IP_USE_DISP32 = 1U << 11
}
 The constants to describe instr prefixes if there are. More...
 
enum  OperandType : unsigned { OPERAND_ROUNDING_CONTROL = MCOI::OPERAND_FIRST_TARGET , OPERAND_COND_CODE }
 
enum  CondCode {
  COND_O = 0 , COND_NO = 1 , COND_B = 2 , COND_AE = 3 ,
  COND_E = 4 , COND_NE = 5 , COND_BE = 6 , COND_A = 7 ,
  COND_S = 8 , COND_NS = 9 , COND_P = 10 , COND_NP = 11 ,
  COND_L = 12 , COND_GE = 13 , COND_LE = 14 , COND_G = 15 ,
  LAST_VALID_COND = COND_G , COND_NE_OR_P , COND_E_AND_NP , COND_INVALID
}
 
enum class  FirstMacroFusionInstKind {
  Test , Cmp , And , AddSub ,
  IncDec , Invalid
}
 
enum class  SecondMacroFusionInstKind { AB , ELG , SPO , Invalid }
 
enum  AlignBranchBoundaryKind : uint8_t {
  AlignBranchNone = 0 , AlignBranchFused = 1U << 0 , AlignBranchJcc = 1U << 1 , AlignBranchJmp = 1U << 2 ,
  AlignBranchCall = 1U << 3 , AlignBranchRet = 1U << 4 , AlignBranchIndirect = 1U << 5
}
 Defines the possible values of the branch boundary alignment mask. More...
 
enum  EncodingOfSegmentOverridePrefix : uint8_t {
  CS_Encoding = 0x2E , DS_Encoding = 0x3E , ES_Encoding = 0x26 , FS_Encoding = 0x64 ,
  GS_Encoding = 0x65 , SS_Encoding = 0x36
}
 Defines the encoding values for segment override prefix. More...
 
enum  Fixups {
  reloc_riprel_4byte = FirstTargetFixupKind , reloc_riprel_4byte_movq_load , reloc_riprel_4byte_relax , reloc_riprel_4byte_relax_rex ,
  reloc_signed_4byte , reloc_signed_4byte_relax , reloc_global_offset_table , reloc_global_offset_table8 ,
  reloc_branch_4byte_pcrel , LastTargetFixupKind , NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
}
 
enum  AsmComments { AC_EVEX_2_LEGACY = MachineInstr::TAsmComments , AC_EVEX_2_VEX = AC_EVEX_2_LEGACY << 1 , AC_EVEX_2_EVEX = AC_EVEX_2_VEX << 1 }
 
enum  { MaxShuffleCombineDepth = 8 }
 
enum  RoundingMode {
  rmToNearest = 0 , rmDownward = 1 << 10 , rmUpward = 2 << 10 , rmTowardZero = 3 << 10 ,
  rmMask = 3 << 10
}
 Current rounding mode is represented in bits 11:10 of FPSR. More...
 

Functions

CPUKind parseArchX86 (StringRef CPU, bool Only64Bit=false)
 Parse CPU string into a CPUKind.
 
CPUKind parseTuneCPU (StringRef CPU, bool Only64Bit=false)
 
void fillValidCPUArchList (SmallVectorImpl< StringRef > &Values, bool Only64Bit=false)
 Provide a list of valid CPU names.
 
void fillValidTuneCPUList (SmallVectorImpl< StringRef > &Values, bool Only64Bit=false)
 Provide a list of valid -mtune names.
 
ProcessorFeatures getKeyFeature (CPUKind Kind)
 Get the key feature prioritizing target multiversioning.
 
void getFeaturesForCPU (StringRef CPU, SmallVectorImpl< StringRef > &Features, bool NeedPlus=false)
 Fill in the features that CPU supports into Features.
 
void updateImpliedFeatures (StringRef Feature, bool Enabled, StringMap< bool > &Features)
 Set or clear entries in Features that are implied to be enabled/disabled by the provided Feature.
 
char getCPUDispatchMangling (StringRef Name)
 
bool validateCPUSpecificCPUDispatch (StringRef Name)
 
std::array< uint32_t, 4 > getCpuSupportsMask (ArrayRef< StringRef > FeatureStrs)
 
unsigned getFeaturePriority (ProcessorFeatures Feat)
 
FirstMacroFusionInstKind classifyFirstOpcodeInMacroFusion (unsigned Opcode)
 
SecondMacroFusionInstKind classifySecondCondCodeInMacroFusion (X86::CondCode CC)
 
bool isMacroFused (FirstMacroFusionInstKind FirstKind, SecondMacroFusionInstKind SecondKind)
 
EncodingOfSegmentOverridePrefix getSegmentOverridePrefixForReg (unsigned Reg)
 Given a segment register, return the encoding of the segment override prefix for it.
 
bool optimizeInstFromVEX3ToVEX2 (MCInst &MI, const MCInstrDesc &Desc)
 
bool optimizeShiftRotateWithImmediateOne (MCInst &MI)
 
bool optimizeVPCMPWithImmediateOneOrSix (MCInst &MI)
 
bool optimizeMOVSX (MCInst &MI)
 
bool optimizeINCDEC (MCInst &MI, bool In64BitMode)
 
bool optimizeMOV (MCInst &MI, bool In64BitMode)
 Simplify things like MOV32rm to MOV32o32a.
 
bool optimizeToFixedRegisterOrShortImmediateForm (MCInst &MI)
 
unsigned getOpcodeForShortImmediateForm (unsigned Opcode)
 
unsigned getOpcodeForLongImmediateForm (unsigned Opcode)
 
std::pair< CondCode, boolgetX86ConditionCode (CmpInst::Predicate Predicate)
 Return a pair of condition code for the given predicate and whether the instruction operands should be swaped to match the condition code.
 
unsigned getCMovOpcode (unsigned RegBytes, bool HasMemoryOperand=false, bool HasNDD=false)
 Return a cmov opcode for the given register size in bytes, and operand type.
 
int getCondSrcNoFromDesc (const MCInstrDesc &MCID)
 Return the source operand # for condition code by MCID.
 
CondCode getCondFromMI (const MachineInstr &MI)
 Return the condition code of the instruction.
 
CondCode getCondFromBranch (const MachineInstr &MI)
 
CondCode getCondFromSETCC (const MachineInstr &MI)
 
CondCode getCondFromCMov (const MachineInstr &MI)
 
CondCode getCondFromCFCMov (const MachineInstr &MI)
 
CondCode GetOppositeBranchCondition (CondCode CC)
 GetOppositeBranchCondition - Return the inverse of the specified cond, e.g.
 
unsigned getVPCMPImmForCond (ISD::CondCode CC)
 Get the VPCMP immediate for the given condition.
 
unsigned getSwappedVPCMPImm (unsigned Imm)
 Get the VPCMP immediate if the opcodes are swapped.
 
unsigned getSwappedVPCOMImm (unsigned Imm)
 Get the VPCOM immediate if the opcodes are swapped.
 
unsigned getSwappedVCMPImm (unsigned Imm)
 Get the VCMP immediate if the opcodes are swapped.
 
unsigned getVectorRegisterWidth (const MCOperandInfo &Info)
 Get the width of the vector register operand.
 
bool isX87Instruction (MachineInstr &MI)
 Check if the instruction is X87 instruction.
 
int getFirstAddrOperandIdx (const MachineInstr &MI)
 Return the index of the instruction's first address operand, if it has a memory reference, or -1 if it has none.
 
const ConstantgetConstantFromPool (const MachineInstr &MI, unsigned OpNo)
 Find any constant pool entry associated with a specific instruction operand.
 
bool isConstantSplat (SDValue Op, APInt &SplatVal, bool AllowPartialUndefs=true)
 If Op is a constant whose elements are all the same constant or undefined, return true and return the constant value in SplatVal.
 
bool isZeroNode (SDValue Elt)
 Returns true if Elt is a constant zero or floating point constant +0.0.
 
bool isOffsetSuitableForCodeModel (int64_t Offset, CodeModel::Model M, bool hasSymbolicDisplacement)
 Returns true of the given offset can be fit into displacement field of the instruction.
 
bool isCalleePop (CallingConv::ID CallingConv, bool is64Bit, bool IsVarArg, bool GuaranteeTCO)
 Determines whether the callee is required to pop its own arguments.
 
bool mayFoldLoad (SDValue Op, const X86Subtarget &Subtarget, bool AssumeSingleUse=false)
 Check if Op is a load operation that could be folded into some other x86 instruction as a memory operand.
 
bool mayFoldLoadIntoBroadcastFromMem (SDValue Op, MVT EltVT, const X86Subtarget &Subtarget, bool AssumeSingleUse=false)
 Check if Op is a load operation that could be folded into a vector splat instruction as a memory operand.
 
bool mayFoldIntoStore (SDValue Op)
 Check if Op is a value that could be used to fold a store into some other x86 instruction as a memory operand.
 
bool mayFoldIntoZeroExtend (SDValue Op)
 Check if Op is an operation that could be folded into a zero extend x86 instruction.
 
bool isExtendedSwiftAsyncFrameSupported (const X86Subtarget &Subtarget, const MachineFunction &MF)
 True if the target supports the extended frame for async Swift functions.
 
FastISelcreateFastISel (FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
 

Detailed Description

Define some predicates that are used for node matching.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum
Enumerator
BX_SI 
BX_DI 
BP_SI 
BP_DI 
sib 
sib64 

Definition at line 1803 of file X86Disassembler.cpp.

◆ anonymous enum

anonymous enum
Enumerator
AddrBaseReg 
AddrScaleAmt 
AddrIndexReg 
AddrDisp 
AddrSegmentReg 
AddrNumOperands 

Definition at line 28 of file X86BaseInfo.h.

◆ anonymous enum

anonymous enum
Enumerator
MaxShuffleCombineDepth 

Definition at line 39223 of file X86ISelLowering.cpp.

◆ AlignBranchBoundaryKind

Defines the possible values of the branch boundary alignment mask.

Enumerator
AlignBranchNone 
AlignBranchFused 
AlignBranchJcc 
AlignBranchJmp 
AlignBranchCall 
AlignBranchRet 
AlignBranchIndirect 

Definition at line 323 of file X86BaseInfo.h.

◆ AsmComments

Enumerator
AC_EVEX_2_LEGACY 
AC_EVEX_2_VEX 
AC_EVEX_2_EVEX 

Definition at line 31 of file X86InstrInfo.h.

◆ CondCode

Enumerator
COND_O 
COND_NO 
COND_B 
COND_AE 
COND_E 
COND_NE 
COND_BE 
COND_A 
COND_S 
COND_NS 
COND_P 
COND_NP 
COND_L 
COND_GE 
COND_LE 
COND_G 
LAST_VALID_COND 
COND_NE_OR_P 
COND_E_AND_NP 
COND_INVALID 

Definition at line 75 of file X86BaseInfo.h.

◆ CPUKind

Enumerator
CK_None 
CK_i386 
CK_i486 
CK_WinChipC6 
CK_WinChip2 
CK_C3 
CK_i586 
CK_Pentium 
CK_PentiumMMX 
CK_PentiumPro 
CK_i686 
CK_Pentium2 
CK_Pentium3 
CK_PentiumM 
CK_C3_2 
CK_Yonah 
CK_Pentium4 
CK_Prescott 
CK_Nocona 
CK_Core2 
CK_Penryn 
CK_Bonnell 
CK_Silvermont 
CK_Goldmont 
CK_GoldmontPlus 
CK_Tremont 
CK_Gracemont 
CK_Nehalem 
CK_Westmere 
CK_SandyBridge 
CK_IvyBridge 
CK_Haswell 
CK_Broadwell 
CK_SkylakeClient 
CK_SkylakeServer 
CK_Cascadelake 
CK_Cooperlake 
CK_Cannonlake 
CK_IcelakeClient 
CK_Rocketlake 
CK_IcelakeServer 
CK_Tigerlake 
CK_SapphireRapids 
CK_Alderlake 
CK_Raptorlake 
CK_Meteorlake 
CK_Arrowlake 
CK_ArrowlakeS 
CK_Lunarlake 
CK_Pantherlake 
CK_Sierraforest 
CK_Grandridge 
CK_Graniterapids 
CK_GraniterapidsD 
CK_Emeraldrapids 
CK_Clearwaterforest 
CK_KNL 
CK_KNM 
CK_Lakemont 
CK_K6 
CK_K6_2 
CK_K6_3 
CK_Athlon 
CK_AthlonXP 
CK_K8 
CK_K8SSE3 
CK_AMDFAM10 
CK_BTVER1 
CK_BTVER2 
CK_BDVER1 
CK_BDVER2 
CK_BDVER3 
CK_BDVER4 
CK_ZNVER1 
CK_ZNVER2 
CK_ZNVER3 
CK_ZNVER4 
CK_x86_64 
CK_x86_64_v2 
CK_x86_64_v3 
CK_x86_64_v4 
CK_Geode 

Definition at line 67 of file X86TargetParser.h.

◆ EncodingOfSegmentOverridePrefix

Defines the encoding values for segment override prefix.

Enumerator
CS_Encoding 
DS_Encoding 
ES_Encoding 
FS_Encoding 
GS_Encoding 
SS_Encoding 

Definition at line 334 of file X86BaseInfo.h.

◆ FirstMacroFusionInstKind

Enumerator
Test 
Cmp 
And 
AddSub 
IncDec 
Invalid 

Definition at line 105 of file X86BaseInfo.h.

◆ Fixups

Enumerator
reloc_riprel_4byte 
reloc_riprel_4byte_movq_load 
reloc_riprel_4byte_relax 
reloc_riprel_4byte_relax_rex 
reloc_signed_4byte 
reloc_signed_4byte_relax 
reloc_global_offset_table 
reloc_global_offset_table8 
reloc_branch_4byte_pcrel 
LastTargetFixupKind 
NumTargetFixupKinds 

Definition at line 16 of file X86FixupKinds.h.

◆ IPREFIXES

The constants to describe instr prefixes if there are.

Enumerator
IP_NO_PREFIX 
IP_HAS_OP_SIZE 
IP_HAS_AD_SIZE 
IP_HAS_REPEAT_NE 
IP_HAS_REPEAT 
IP_HAS_LOCK 
IP_HAS_NOTRACK 
IP_USE_VEX 
IP_USE_VEX2 
IP_USE_VEX3 
IP_USE_EVEX 
IP_USE_DISP8 
IP_USE_DISP32 

Definition at line 51 of file X86BaseInfo.h.

◆ OperandType

Enumerator
OPERAND_ROUNDING_CONTROL 
OPERAND_COND_CODE 

Definition at line 67 of file X86BaseInfo.h.

◆ ProcessorFeatures

Enumerator
CPU_FEATURE_MAX 

Definition at line 58 of file X86TargetParser.h.

◆ ProcessorSubtypes

Enumerator
CPU_SUBTYPE_DUMMY 
CPU_SUBTYPE_MAX 

Definition at line 48 of file X86TargetParser.h.

◆ ProcessorTypes

Enumerator
CPU_TYPE_DUMMY 
CPU_TYPE_MAX 

Definition at line 38 of file X86TargetParser.h.

◆ ProcessorVendors

Enumerator
VENDOR_DUMMY 
VENDOR_OTHER 

Definition at line 28 of file X86TargetParser.h.

◆ RoundingMode

Current rounding mode is represented in bits 11:10 of FPSR.

These values are same as corresponding constants for rounding mode used in glibc.

Enumerator
rmToNearest 
rmDownward 
rmUpward 
rmTowardZero 
rmMask 

Definition at line 924 of file X86ISelLowering.h.

◆ SecondMacroFusionInstKind

Enumerator
AB 
ELG 
SPO 
Invalid 

Definition at line 114 of file X86BaseInfo.h.

◆ STATIC_ROUNDING

AVX512 static rounding constants.

These need to match the values in avx512fintrin.h.

Enumerator
TO_NEAREST_INT 
TO_NEG_INF 
TO_POS_INF 
TO_ZERO 
CUR_DIRECTION 
NO_EXC 

Definition at line 41 of file X86BaseInfo.h.

Function Documentation

◆ classifyFirstOpcodeInMacroFusion()

FirstMacroFusionInstKind llvm::X86::classifyFirstOpcodeInMacroFusion ( unsigned  Opcode)
inline
Returns
the type of the first instruction in macro-fusion.

Definition at line 124 of file X86BaseInfo.h.

References AddSub, And, Cmp, IncDec, Invalid, and Test.

Referenced by classifyFirst(), and isFirstMacroFusibleInst().

◆ classifySecondCondCodeInMacroFusion()

SecondMacroFusionInstKind llvm::X86::classifySecondCondCodeInMacroFusion ( X86::CondCode  CC)
inline
Returns
the type of the second instruction in macro-fusion.

Definition at line 272 of file X86BaseInfo.h.

References AB, CC, COND_A, COND_AE, COND_B, COND_BE, COND_E, COND_G, COND_GE, COND_INVALID, COND_L, COND_LE, COND_NE, COND_NO, COND_NP, COND_NS, COND_O, COND_P, COND_S, ELG, Invalid, and SPO.

Referenced by classifySecond().

◆ createFastISel()

FastISel * llvm::X86::createFastISel ( FunctionLoweringInfo funcInfo,
const TargetLibraryInfo libInfo 
)

Definition at line 4068 of file X86FastISel.cpp.

Referenced by llvm::X86TargetLowering::createFastISel().

◆ fillValidCPUArchList()

void llvm::X86::fillValidCPUArchList ( SmallVectorImpl< StringRef > &  Values,
bool  Only64Bit = false 
)

Provide a list of valid CPU names.

If Only64Bit is true, the list will only contain 64-bit capable CPUs.

Definition at line 447 of file X86TargetParser.cpp.

References llvm::SmallVectorImpl< T >::emplace_back(), P, and Processors.

◆ fillValidTuneCPUList()

void llvm::X86::fillValidTuneCPUList ( SmallVectorImpl< StringRef > &  Values,
bool  Only64Bit = false 
)

Provide a list of valid -mtune names.

Definition at line 455 of file X86TargetParser.cpp.

References llvm::SmallVectorImpl< T >::emplace_back(), llvm::is_contained(), NoTuneList, P, and Processors.

◆ getCMovOpcode()

unsigned llvm::X86::getCMovOpcode ( unsigned  RegBytes,
bool  HasMemoryOperand = false,
bool  HasNDD = false 
)

Return a cmov opcode for the given register size in bytes, and operand type.

Definition at line 3321 of file X86InstrInfo.cpp.

References GET_ND_IF_ENABLED, and llvm_unreachable.

Referenced by llvm::X86InstrInfo::insertSelect().

◆ getCondFromBranch()

X86::CondCode llvm::X86::getCondFromBranch ( const MachineInstr MI)

◆ getCondFromCFCMov()

X86::CondCode llvm::X86::getCondFromCFCMov ( const MachineInstr MI)

Definition at line 3155 of file X86InstrInfo.cpp.

References COND_INVALID, getCondFromMI(), and MI.

◆ getCondFromCMov()

X86::CondCode llvm::X86::getCondFromCMov ( const MachineInstr MI)

Definition at line 3150 of file X86InstrInfo.cpp.

References COND_INVALID, getCondFromMI(), and MI.

Referenced by packCmovGroup().

◆ getCondFromMI()

X86::CondCode llvm::X86::getCondFromMI ( const MachineInstr MI)

Return the condition code of the instruction.

If the instruction doesn't have a condition code, return X86::COND_INVALID.

Definition at line 3131 of file X86InstrInfo.cpp.

References COND_INVALID, getCondSrcNoFromDesc(), llvm::MCInstrDesc::getNumDefs(), and MI.

Referenced by getCondFromBranch(), getCondFromCFCMov(), getCondFromCMov(), getCondFromSETCC(), and llvm::X86InstrInfo::optimizeCompareInstr().

◆ getCondFromSETCC()

X86::CondCode llvm::X86::getCondFromSETCC ( const MachineInstr MI)

Definition at line 3145 of file X86InstrInfo.cpp.

References COND_INVALID, getCondFromMI(), and MI.

◆ getCondSrcNoFromDesc()

int llvm::X86::getCondSrcNoFromDesc ( const MCInstrDesc MCID)

Return the source operand # for condition code by MCID.

If the instruction doesn't have a condition code, return -1.

Definition at line 3121 of file X86InstrInfo.cpp.

References llvm::MCInstrDesc::getNumDefs(), llvm::MCInstrDesc::getNumOperands(), and llvm::MCInstrDesc::getOpcode().

Referenced by getCondFromMI().

◆ getConstantFromPool()

const Constant * llvm::X86::getConstantFromPool ( const MachineInstr MI,
unsigned  OpNo 
)

◆ getCPUDispatchMangling()

char llvm::X86::getCPUDispatchMangling ( StringRef  Name)

Definition at line 717 of file X86TargetParser.cpp.

References assert(), llvm::find_if(), I, P, and Processors.

◆ getCpuSupportsMask()

std::array< uint32_t, 4 > llvm::X86::getCpuSupportsMask ( ArrayRef< StringRef FeatureStrs)

Definition at line 732 of file X86TargetParser.cpp.

References assert().

◆ getFeaturePriority()

unsigned llvm::X86::getFeaturePriority ( ProcessorFeatures  Feat)

Definition at line 749 of file X86TargetParser.cpp.

References assert(), and llvm_unreachable.

◆ getFeaturesForCPU()

void llvm::X86::getFeaturesForCPU ( StringRef  CPU,
SmallVectorImpl< StringRef > &  Features,
bool  NeedPlus = false 
)

Fill in the features that CPU supports into Features.

"+" will be append in front of each feature if NeedPlus is true.

Definition at line 642 of file X86TargetParser.cpp.

References assert(), CPU_FEATURE_MAX, FeatureInfos, llvm::find_if(), getName(), I, P, Processors, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

◆ getFirstAddrOperandIdx()

int llvm::X86::getFirstAddrOperandIdx ( const MachineInstr MI)

Return the index of the instruction's first address operand, if it has a memory reference, or -1 if it has none.

Unlike X86II::getMemoryOperandNo(), this also works for both pseudo instructions (e.g., TCRETURNmi) as well as real instructions (e.g., JMP64m).

Definition at line 3471 of file X86InstrInfo.cpp.

References AddrNumOperands, assert(), E, llvm::X86II::getMemoryOperandNo(), llvm::X86II::getOperandBias(), I, llvm::X86II::isPseudo(), MI, llvm::none_of(), and llvm::MCOI::OPERAND_MEMORY.

Referenced by isRedundantNewDataDest().

◆ getKeyFeature()

ProcessorFeatures llvm::X86::getKeyFeature ( X86::CPUKind  Kind)

Get the key feature prioritizing target multiversioning.

Definition at line 464 of file X86TargetParser.cpp.

References assert(), llvm_unreachable, P, and Processors.

◆ getOpcodeForLongImmediateForm()

unsigned llvm::X86::getOpcodeForLongImmediateForm ( unsigned  Opcode)

Definition at line 462 of file X86EncodingOptimization.cpp.

Referenced by getRelaxedOpcode().

◆ getOpcodeForShortImmediateForm()

unsigned llvm::X86::getOpcodeForShortImmediateForm ( unsigned  Opcode)

Definition at line 451 of file X86EncodingOptimization.cpp.

◆ GetOppositeBranchCondition()

X86::CondCode llvm::X86::GetOppositeBranchCondition ( X86::CondCode  CC)

GetOppositeBranchCondition - Return the inverse of the specified cond, e.g.

Return the inverse of the specified condition, e.g.

turning COND_E to COND_NE.

Definition at line 3162 of file X86InstrInfo.cpp.

References CC, COND_A, COND_AE, COND_B, COND_BE, COND_E, COND_E_AND_NP, COND_G, COND_GE, COND_L, COND_LE, COND_NE, COND_NE_OR_P, COND_NO, COND_NP, COND_NS, COND_O, COND_P, COND_S, and llvm_unreachable.

Referenced by checkBoolTestSetCCCombine(), combineCMov(), combineOr(), combineSubSetcc(), llvm::X86InstrInfo::commuteInstructionImpl(), createPHIsForCMOVsInSinkBB(), and foldXor1SetCC().

◆ getSegmentOverridePrefixForReg()

EncodingOfSegmentOverridePrefix llvm::X86::getSegmentOverridePrefixForReg ( unsigned  Reg)
inline

Given a segment register, return the encoding of the segment override prefix for it.

Definition at line 346 of file X86BaseInfo.h.

References CS_Encoding, DS_Encoding, ES_Encoding, FS_Encoding, GS_Encoding, llvm_unreachable, Reg, and SS_Encoding.

◆ getSwappedVCMPImm()

unsigned llvm::X86::getSwappedVCMPImm ( unsigned  Imm)

Get the VCMP immediate if the opcodes are swapped.

Get the VCMP immediate if the operands are swapped.

Definition at line 3418 of file X86InstrInfo.cpp.

References llvm_unreachable.

Referenced by llvm::X86InstrInfo::commuteInstructionImpl().

◆ getSwappedVPCMPImm()

unsigned llvm::X86::getSwappedVPCMPImm ( unsigned  Imm)

Get the VPCMP immediate if the opcodes are swapped.

Get the VPCMP immediate if the operands are swapped.

Definition at line 3364 of file X86InstrInfo.cpp.

References llvm_unreachable.

Referenced by llvm::X86InstrInfo::commuteInstructionImpl().

◆ getSwappedVPCOMImm()

unsigned llvm::X86::getSwappedVPCOMImm ( unsigned  Imm)

Get the VPCOM immediate if the opcodes are swapped.

Get the VPCOM immediate if the operands are swapped.

Definition at line 3391 of file X86InstrInfo.cpp.

References llvm_unreachable.

Referenced by llvm::X86InstrInfo::commuteInstructionImpl().

◆ getVectorRegisterWidth()

unsigned llvm::X86::getVectorRegisterWidth ( const MCOperandInfo Info)

Get the width of the vector register operand.

Definition at line 3437 of file X86InstrInfo.cpp.

References Info, and llvm_unreachable.

Referenced by addConstantComments(), and printZeroExtend().

◆ getVPCMPImmForCond()

unsigned llvm::X86::getVPCMPImmForCond ( ISD::CondCode  CC)

◆ getX86ConditionCode()

std::pair< X86::CondCode, bool > llvm::X86::getX86ConditionCode ( CmpInst::Predicate  Predicate)

◆ isCalleePop()

bool llvm::X86::isCalleePop ( CallingConv::ID  CallingConv,
bool  is64Bit,
bool  IsVarArg,
bool  GuaranteeTCO 
)

Determines whether the callee is required to pop its own arguments.

Callee pop is necessary to support tail calls.

Definition at line 2925 of file X86ISelLoweringCall.cpp.

References is64Bit(), shouldGuaranteeTCO(), llvm::CallingConv::X86_FastCall, llvm::CallingConv::X86_StdCall, llvm::CallingConv::X86_ThisCall, and llvm::CallingConv::X86_VectorCall.

◆ isConstantSplat()

bool llvm::X86::isConstantSplat ( SDValue  Op,
APInt SplatVal,
bool  AllowPartialUndefs = true 
)

If Op is a constant whose elements are all the same constant or undefined, return true and return the constant value in SplatVal.

If we have undef bits that don't cover an entire element, we treat these as zero if AllowPartialUndefs is set, else we fail and return false.

Definition at line 4978 of file X86ISelLowering.cpp.

References getTargetConstantBitsFromNode(), and llvm::SmallVectorBase< Size_T >::size().

Referenced by combineAndMaskToShift(), LowerFunnelShift(), LowerRotate(), and LowerShiftByScalarImmediate().

◆ isExtendedSwiftAsyncFrameSupported()

bool llvm::X86::isExtendedSwiftAsyncFrameSupported ( const X86Subtarget Subtarget,
const MachineFunction MF 
)

True if the target supports the extended frame for async Swift functions.

Definition at line 26672 of file X86ISelLowering.cpp.

References llvm::TargetMachine::getMCAsmInfo(), llvm::MachineFunction::getTarget(), and llvm::MCAsmInfo::usesWindowsCFI().

Referenced by LowerINTRINSIC_W_CHAIN().

◆ isMacroFused()

bool llvm::X86::isMacroFused ( FirstMacroFusionInstKind  FirstKind,
SecondMacroFusionInstKind  SecondKind 
)
inline
Parameters
FirstKindkind of the first instruction in macro fusion.
SecondKindkind of the second instruction in macro fusion.
Returns
true if the two instruction can be macro fused.

Definition at line 304 of file X86BaseInfo.h.

References AB, AddSub, And, Cmp, ELG, IncDec, Invalid, llvm_unreachable, and Test.

Referenced by shouldScheduleAdjacent().

◆ isOffsetSuitableForCodeModel()

bool llvm::X86::isOffsetSuitableForCodeModel ( int64_t  Offset,
CodeModel::Model  M,
bool  hasSymbolicDisplacement 
)

Returns true of the given offset can be fit into displacement field of the instruction.

Definition at line 2712 of file X86ISelLowering.cpp.

References llvm::CodeModel::Kernel, llvm::CodeModel::Large, and llvm::Offset.

Referenced by llvm::X86TargetLowering::isLegalAddressingMode().

◆ isX87Instruction()

bool llvm::X86::isX87Instruction ( MachineInstr MI)

Check if the instruction is X87 instruction.

check if the instruction is X87 instruction

Definition at line 3456 of file X86InstrInfo.cpp.

References isX87Reg(), and MI.

Referenced by getNextFPInstruction().

◆ isZeroNode()

bool llvm::X86::isZeroNode ( SDValue  Elt)

Returns true if Elt is a constant zero or floating point constant +0.0.

Returns true if Elt is a constant zero or a floating point constant +0.0.

Definition at line 3702 of file X86ISelLowering.cpp.

References llvm::isNullConstant(), and llvm::isNullFPConstant().

Referenced by combineAdd(), combineAddOrSubToADCOrSBB(), combineSub(), computeZeroableShuffleElements(), EltsFromConsecutiveLoads(), getFauxShuffleMask(), getMaskNode(), getTargetShuffleAndZeroables(), LowerBuildVectorv4x32(), and LowerSCALAR_TO_VECTOR().

◆ mayFoldIntoStore()

bool llvm::X86::mayFoldIntoStore ( SDValue  Op)

Check if Op is a value that could be used to fold a store into some other x86 instruction as a memory operand.

Ex: pextrb $0, xmm0, (rdi).

Definition at line 2622 of file X86ISelLowering.cpp.

References llvm::ISD::isNormalStore().

Referenced by LowerEXTRACT_VECTOR_ELT_SSE4().

◆ mayFoldIntoZeroExtend()

bool llvm::X86::mayFoldIntoZeroExtend ( SDValue  Op)

Check if Op is an operation that could be folded into a zero extend x86 instruction.

Definition at line 2626 of file X86ISelLowering.cpp.

References llvm::ISD::ZERO_EXTEND.

Referenced by LowerEXTRACT_VECTOR_ELT_SSE4().

◆ mayFoldLoad()

bool llvm::X86::mayFoldLoad ( SDValue  Op,
const X86Subtarget Subtarget,
bool  AssumeSingleUse = false 
)

Check if Op is a load operation that could be folded into some other x86 instruction as a memory operand.

Example: vpaddd (rdi), xmm0, xmm0.

Definition at line 2589 of file X86ISelLowering.cpp.

References llvm::X86Subtarget::hasAVX(), and llvm::ISD::isNormalLoad().

Referenced by combineCommutableSHUFP(), combineConcatVectorOps(), combineX86ShuffleChain(), llvm::X86TargetLowering::IsDesirableToPromoteOp(), lowerShuffleAsDecomposedShuffleMerge(), lowerV2X128Shuffle(), mayFoldLoadIntoBroadcastFromMem(), and pushAddIntoCmovOfConsts().

◆ mayFoldLoadIntoBroadcastFromMem()

bool llvm::X86::mayFoldLoadIntoBroadcastFromMem ( SDValue  Op,
MVT  EltVT,
const X86Subtarget Subtarget,
bool  AssumeSingleUse = false 
)

Check if Op is a load operation that could be folded into a vector splat instruction as a memory operand.

Example: vbroadcastss 16(rdi), xmm2.

Definition at line 2608 of file X86ISelLowering.cpp.

References assert(), llvm::MVT::getScalarSizeInBits(), llvm::X86Subtarget::hasAVX(), and mayFoldLoad().

Referenced by combineConcatVectorOps(), and EltsFromConsecutiveLoads().

◆ optimizeINCDEC()

bool llvm::X86::optimizeINCDEC ( MCInst MI,
bool  In64BitMode 
)

Definition at line 311 of file X86EncodingOptimization.cpp.

References FROM_TO, and MI.

◆ optimizeInstFromVEX3ToVEX2()

bool llvm::X86::optimizeInstFromVEX3ToVEX2 ( MCInst MI,
const MCInstrDesc Desc 
)

◆ optimizeMOV()

bool llvm::X86::optimizeMOV ( MCInst MI,
bool  In64BitMode 
)

Simplify things like MOV32rm to MOV32o32a.

Definition at line 337 of file X86EncodingOptimization.cpp.

References AddrBaseReg, AddrIndexReg, AddrScaleAmt, AddrSegmentReg, FROM_TO, isARegister(), MI, Saved, and llvm::MCSymbolRefExpr::VK_TLVP.

◆ optimizeMOVSX()

bool llvm::X86::optimizeMOVSX ( MCInst MI)

Definition at line 289 of file X86EncodingOptimization.cpp.

References FROM_TO, and MI.

◆ optimizeShiftRotateWithImmediateOne()

bool llvm::X86::optimizeShiftRotateWithImmediateOne ( MCInst MI)

◆ optimizeToFixedRegisterOrShortImmediateForm()

bool llvm::X86::optimizeToFixedRegisterOrShortImmediateForm ( MCInst MI)

◆ optimizeVPCMPWithImmediateOneOrSix()

bool llvm::X86::optimizeVPCMPWithImmediateOneOrSix ( MCInst MI)

Definition at line 202 of file X86EncodingOptimization.cpp.

References FROM_TO, llvm::MCOperand::getImm(), and MI.

◆ parseArchX86()

X86::CPUKind llvm::X86::parseArchX86 ( StringRef  CPU,
bool  Only64Bit = false 
)

Parse CPU string into a CPUKind.

Will only accept 64-bit capable CPUs if Only64Bit is true.

Definition at line 432 of file X86TargetParser.cpp.

References CK_None, P, and Processors.

Referenced by parseTuneCPU().

◆ parseTuneCPU()

X86::CPUKind llvm::X86::parseTuneCPU ( StringRef  CPU,
bool  Only64Bit = false 
)

Definition at line 441 of file X86TargetParser.cpp.

References CK_None, llvm::is_contained(), NoTuneList, and parseArchX86().

◆ updateImpliedFeatures()

void llvm::X86::updateImpliedFeatures ( StringRef  Feature,
bool  Enabled,
StringMap< bool > &  Features 
)

Set or clear entries in Features that are implied to be enabled/disabled by the provided Feature.

Definition at line 692 of file X86TargetParser.cpp.

References CPU_FEATURE_MAX, Enabled, FeatureInfos, llvm::find_if(), getImpliedDisabledFeatures(), getImpliedEnabledFeatures(), getName(), and I.

◆ validateCPUSpecificCPUDispatch()

bool llvm::X86::validateCPUSpecificCPUDispatch ( StringRef  Name)

Definition at line 725 of file X86TargetParser.cpp.

References llvm::find_if(), I, Name, P, and Processors.