LLVM 19.0.0git
Enumerations
llvm::X86ISD Namespace Reference

Enumerations

enum  NodeType : unsigned {
  FIRST_NUMBER = ISD::BUILTIN_OP_END , BSF , BSR , FSHL ,
  FSHR , FAND , FOR , FXOR ,
  FANDN , CALL , NT_CALL , CALL_RVMARKER ,
  CMP , FCMP , COMI , UCOMI ,
  BT , SETCC , SELECTS , SETCC_CARRY ,
  FSETCC , FSETCCM , FSETCCM_SAE , CMOV ,
  BRCOND , NT_BRIND , RET_GLUE , IRET ,
  REP_STOS , REP_MOVS , GlobalBaseReg , Wrapper ,
  WrapperRIP , MOVQ2DQ , MOVDQ2Q , MMX_MOVD2W ,
  MMX_MOVW2D , PEXTRB , PEXTRW , INSERTPS ,
  PINSRB , PINSRW , PSHUFB , PSADBW ,
  DBPSADBW , ANDNP , BLENDI , BLENDV ,
  ADDSUB , FADD_RND , FADDS , FADDS_RND ,
  FSUB_RND , FSUBS , FSUBS_RND , FMUL_RND ,
  FMULS , FMULS_RND , FDIV_RND , FDIVS ,
  FDIVS_RND , FMAX_SAE , FMAXS_SAE , FMIN_SAE ,
  FMINS_SAE , FSQRT_RND , FSQRTS , FSQRTS_RND ,
  FGETEXP , FGETEXP_SAE , FGETEXPS , FGETEXPS_SAE ,
  VGETMANT , VGETMANT_SAE , VGETMANTS , VGETMANTS_SAE ,
  SCALEF , SCALEF_RND , SCALEFS , SCALEFS_RND ,
  HADD , HSUB , FHADD , FHSUB ,
  CONFLICT , FMAX , FMIN , FMAXC ,
  FMINC , FMAXS , FMINS , FRSQRT ,
  FRCP , RSQRT14 , RSQRT14S , RCP14 ,
  RCP14S , TLSADDR , TLSBASEADDR , TLSCALL ,
  TLSDESC , EH_RETURN , EH_SJLJ_SETJMP , EH_SJLJ_LONGJMP ,
  EH_SJLJ_SETUP_DISPATCH , TC_RETURN , VZEXT_MOVL , VTRUNC ,
  VTRUNCUS , VTRUNCS , VMTRUNC , VMTRUNCUS ,
  VMTRUNCS , VFPEXT , VFPEXT_SAE , VFPEXTS ,
  VFPEXTS_SAE , VFPROUND , VFPROUND_RND , VFPROUNDS ,
  VFPROUNDS_RND , VMFPROUND , VSHLDQ , VSRLDQ ,
  VSHL , VSRL , VSRA , VSHLV ,
  VSRLV , VSRAV , VSHLI , VSRLI ,
  VSRAI , KSHIFTL , KSHIFTR , VROTLI ,
  VROTRI , CMPP , PCMPEQ , PCMPGT ,
  PHMINPOS , MULTISHIFT , CMPM , CMPMM ,
  CMPMM_SAE , ADD , SUB , ADC ,
  SBB , SMUL , UMUL , OR ,
  XOR , AND , BEXTR , BEXTRI ,
  BZHI , PDEP , PEXT , MUL_IMM ,
  MOVMSK , PTEST , TESTP , KORTEST ,
  KTEST , KADD , PACKSS , PACKUS ,
  PALIGNR , VALIGN , PSHUFD , PSHUFHW ,
  PSHUFLW , SHUFP , VSHLD , VSHRD ,
  VSHLDV , VSHRDV , SHUF128 , MOVDDUP ,
  MOVSHDUP , MOVSLDUP , MOVLHPS , MOVHLPS ,
  MOVSD , MOVSS , MOVSH , UNPCKL ,
  UNPCKH , VPERMILPV , VPERMILPI , VPERMI ,
  VPERM2X128 , VPERMV , VPERMV3 , VPTERNLOG ,
  VFIXUPIMM , VFIXUPIMM_SAE , VFIXUPIMMS , VFIXUPIMMS_SAE ,
  VRANGE , VRANGE_SAE , VRANGES , VRANGES_SAE ,
  VREDUCE , VREDUCE_SAE , VREDUCES , VREDUCES_SAE ,
  VRNDSCALE , VRNDSCALE_SAE , VRNDSCALES , VRNDSCALES_SAE ,
  VFPCLASS , VFPCLASSS , VBROADCAST , VBROADCASTM ,
  EXTRQI , INSERTQI , VPSHA , VPSHL ,
  VPCOM , VPCOMU , VPPERM , VPERMIL2 ,
  PMULUDQ , PMULDQ , MULHRS , VPMADDUBSW ,
  VPMADDWD , VPMADD52L , VPMADD52H , VPDPBUSD ,
  VPDPBUSDS , VPDPWSSD , VPDPWSSDS , FNMADD ,
  FMSUB , FNMSUB , FMADDSUB , FMSUBADD ,
  FMADD_RND , FNMADD_RND , FMSUB_RND , FNMSUB_RND ,
  FMADDSUB_RND , FMSUBADD_RND , VFMADDC , VFMADDC_RND ,
  VFCMADDC , VFCMADDC_RND , VFMULC , VFMULC_RND ,
  VFCMULC , VFCMULC_RND , VFMADDCSH , VFMADDCSH_RND ,
  VFCMADDCSH , VFCMADDCSH_RND , VFMULCSH , VFMULCSH_RND ,
  VFCMULCSH , VFCMULCSH_RND , VPDPBSUD , VPDPBSUDS ,
  VPDPBUUD , VPDPBUUDS , VPDPBSSD , VPDPBSSDS ,
  COMPRESS , EXPAND , VPSHUFBITQMB , SINT_TO_FP_RND ,
  UINT_TO_FP_RND , SCALAR_SINT_TO_FP , SCALAR_UINT_TO_FP , SCALAR_SINT_TO_FP_RND ,
  SCALAR_UINT_TO_FP_RND , CVTP2SI , CVTP2UI , CVTP2SI_RND ,
  CVTP2UI_RND , CVTS2SI , CVTS2UI , CVTS2SI_RND ,
  CVTS2UI_RND , CVTTP2SI , CVTTP2UI , CVTTP2SI_SAE ,
  CVTTP2UI_SAE , CVTTS2SI , CVTTS2UI , CVTTS2SI_SAE ,
  CVTTS2UI_SAE , CVTSI2P , CVTUI2P , MCVTP2SI ,
  MCVTP2UI , MCVTTP2SI , MCVTTP2UI , MCVTSI2P ,
  MCVTUI2P , CVTNE2PS2BF16 , CVTNEPS2BF16 , MCVTNEPS2BF16 ,
  DPBF16PS , DYN_ALLOCA , SEG_ALLOCA , PROBED_ALLOCA ,
  MFENCE , RDRAND , RDSEED , RDPKRU ,
  WRPKRU , PCMPISTR , PCMPESTR , XTEST ,
  RSQRT28 , RSQRT28_SAE , RSQRT28S , RSQRT28S_SAE ,
  RCP28 , RCP28_SAE , RCP28S , RCP28S_SAE ,
  EXP2 , EXP2_SAE , CVTPS2PH , CVTPS2PH_SAE ,
  CVTPH2PS , CVTPH2PS_SAE , MCVTPS2PH , MCVTPS2PH_SAE ,
  GF2P8AFFINEINVQB , GF2P8AFFINEQB , GF2P8MULB , LWPINS ,
  UMWAIT , TPAUSE , ENQCMD , ENQCMDS ,
  VP2INTERSECT , TESTUI , FP80_ADD , STRICT_FCMP = ISD::FIRST_TARGET_STRICTFP_OPCODE ,
  STRICT_FCMPS , STRICT_CMPP , STRICT_CMPM , STRICT_CVTTP2SI ,
  STRICT_CVTTP2UI , STRICT_VFPEXT , STRICT_VFPROUND , STRICT_VRNDSCALE ,
  STRICT_CVTSI2P , STRICT_CVTUI2P , STRICT_FNMADD , STRICT_FMSUB ,
  STRICT_FNMSUB , STRICT_CVTPS2PH , STRICT_CVTPH2PS , STRICT_FP80_ADD ,
  LCMPXCHG_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE , LCMPXCHG8_DAG , LCMPXCHG16_DAG , LCMPXCHG16_SAVE_RBX_DAG ,
  LADD , LSUB , LOR , LXOR ,
  LAND , LBTS , LBTC , LBTR ,
  LBTS_RM , LBTC_RM , LBTR_RM , AADD ,
  AOR , AXOR , AAND , VZEXT_LOAD ,
  VEXTRACT_STORE , VBROADCAST_LOAD , SUBV_BROADCAST_LOAD , FNSTCW16m ,
  FLDCW16m , FNSTENVm , FLDENVm , FP_TO_INT_IN_MEM ,
  FILD , FIST , FLD , FST ,
  VAARG_64 , VAARG_X32 , VTRUNCSTOREUS , VTRUNCSTORES ,
  VMTRUNCSTOREUS , VMTRUNCSTORES , MGATHER , MSCATTER ,
  AESENC128KL , AESDEC128KL , AESENC256KL , AESDEC256KL ,
  AESENCWIDE128KL , AESDECWIDE128KL , AESENCWIDE256KL , AESDECWIDE256KL ,
  CMPCCXADD , VASTART_SAVE_XMM_REGS
}
 

Enumeration Type Documentation

◆ NodeType

Enumerator
FIRST_NUMBER 
BSF 

Bit scan forward.

BSR 

Bit scan reverse.

FSHL 

X86 funnel/double shift i16 instructions.

These correspond to X86::SHLDW and X86::SHRDW instructions which have different amt modulo rules to generic funnel shifts. NOTE: The operand order matches ISD::FSHL/FSHR not SHLD/SHRD.

FSHR 
FAND 

Bitwise logical AND of floating point values.

This corresponds to X86::ANDPS or X86::ANDPD.

FOR 

Bitwise logical OR of floating point values.

This corresponds to X86::ORPS or X86::ORPD.

FXOR 

Bitwise logical XOR of floating point values.

This corresponds to X86::XORPS or X86::XORPD.

FANDN 

Bitwise logical ANDNOT of floating point values.

This corresponds to X86::ANDNPS or X86::ANDNPD.

CALL 

These operations represent an abstract X86 call instruction, which includes a bunch of information.

In particular the operands of these node are:

#0 - The incoming token chain
#1 - The callee
#2 - The number of arg bytes the caller pushes on the stack.
#3 - The number of arg bytes the callee pops off the stack.
#4 - The value to pass in AL/AX/EAX (optional)
#5 - The value to pass in DL/DX/EDX (optional)

The result values of these nodes are:

#0 - The outgoing token chain
#1 - The first register result value (optional)
#2 - The second register result value (optional)
NT_CALL 

Same as call except it adds the NoTrack prefix.

CALL_RVMARKER 
CMP 

X86 compare and logical compare instructions.

FCMP 
COMI 
UCOMI 
BT 

X86 bit-test instructions.

SETCC 

X86 SetCC.

Operand 0 is condition code, and operand 1 is the EFLAGS operand, usually produced by a CMP instruction.

SELECTS 

X86 Select.

SETCC_CARRY 
FSETCC 

X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.

Operands are two FP values to compare; result is a mask of 0s or 1s. Generally DTRT for C/C++ with NaNs.

FSETCCM 

X86 FP SETCC, similar to above, but with output as an i1 mask and and a version with SAE.

FSETCCM_SAE 
CMOV 

X86 conditional moves.

Operand 0 and operand 1 are the two values to select from. Operand 2 is the condition code, and operand 3 is the flag operand produced by a CMP or TEST instruction.

BRCOND 

X86 conditional branches.

Operand 0 is the chain operand, operand 1 is the block to branch if condition is true, operand 2 is the condition code, and operand 3 is the flag operand produced by a CMP or TEST instruction.

NT_BRIND 

BRIND node with NoTrack prefix.

Operand 0 is the chain operand and operand 1 is the target address.

RET_GLUE 

Return with a glue operand.

Operand 0 is the chain operand, operand 1 is the number of bytes of stack to pop.

IRET 

Return from interrupt. Operand 0 is the number of bytes to pop.

REP_STOS 

Repeat fill, corresponds to X86::REP_STOSx.

REP_MOVS 

Repeat move, corresponds to X86::REP_MOVSx.

GlobalBaseReg 

On Darwin, this node represents the result of the popl at function entry, used for PIC code.

Wrapper 

A wrapper node for TargetConstantPool, TargetJumpTable, TargetExternalSymbol, TargetGlobalAddress, TargetGlobalTLSAddress, MCSymbol and TargetBlockAddress.

WrapperRIP 

Special wrapper used under X86-64 PIC mode for RIP relative displacements.

MOVQ2DQ 

Copies a 64-bit value from an MMX vector to the low word of an XMM vector, with the high word zero filled.

MOVDQ2Q 

Copies a 64-bit value from the low word of an XMM vector to an MMX vector.

MMX_MOVD2W 

Copies a 32-bit value from the low word of a MMX vector to a GPR.

MMX_MOVW2D 

Copies a GPR into the low 32-bit word of a MMX vector and zero out the high word.

PEXTRB 

Extract an 8-bit value from a vector and zero extend it to i32, corresponds to X86::PEXTRB.

PEXTRW 

Extract a 16-bit value from a vector and zero extend it to i32, corresponds to X86::PEXTRW.

INSERTPS 

Insert any element of a 4 x float vector into any element of a destination 4 x floatvector.

PINSRB 

Insert the lower 8-bits of a 32-bit value to a vector, corresponds to X86::PINSRB.

PINSRW 

Insert the lower 16-bits of a 32-bit value to a vector, corresponds to X86::PINSRW.

PSHUFB 

Shuffle 16 8-bit values within a vector.

PSADBW 

Compute Sum of Absolute Differences.

DBPSADBW 

Compute Double Block Packed Sum-Absolute-Differences.

ANDNP 

Bitwise Logical AND NOT of Packed FP values.

BLENDI 

Blend where the selector is an immediate.

BLENDV 

Dynamic (non-constant condition) vector blend where only the sign bits of the condition elements are used.

This is used to enforce that the condition mask is not valid for generic VSELECT optimizations. This is also used to implement the intrinsics. Operands are in VSELECT order: MASK, TRUE, FALSE

ADDSUB 

Combined add and sub on an FP vector.

FADD_RND 
FADDS 
FADDS_RND 
FSUB_RND 
FSUBS 
FSUBS_RND 
FMUL_RND 
FMULS 
FMULS_RND 
FDIV_RND 
FDIVS 
FDIVS_RND 
FMAX_SAE 
FMAXS_SAE 
FMIN_SAE 
FMINS_SAE 
FSQRT_RND 
FSQRTS 
FSQRTS_RND 
FGETEXP 
FGETEXP_SAE 
FGETEXPS 
FGETEXPS_SAE 
VGETMANT 
VGETMANT_SAE 
VGETMANTS 
VGETMANTS_SAE 
SCALEF 
SCALEF_RND 
SCALEFS 
SCALEFS_RND 
HADD 

Integer horizontal add/sub.

HSUB 
FHADD 

Floating point horizontal add/sub.

FHSUB 
CONFLICT 
FMAX 

Floating point max and min.

FMIN 
FMAXC 

Commutative FMIN and FMAX.

FMINC 
FMAXS 

Scalar intrinsic floating point max and min.

FMINS 
FRSQRT 

Floating point reciprocal-sqrt and reciprocal approximation.

Note that these typically require refinement in order to obtain suitable precision.

FRCP 
RSQRT14 
RSQRT14S 
RCP14 
RCP14S 
TLSADDR 
TLSBASEADDR 
TLSCALL 
TLSDESC 
EH_RETURN 
EH_SJLJ_SETJMP 
EH_SJLJ_LONGJMP 
EH_SJLJ_SETUP_DISPATCH 
TC_RETURN 

Tail call return.

See X86TargetLowering::LowerCall for the list of operands.

VZEXT_MOVL 
VTRUNC 
VTRUNCUS 
VTRUNCS 
VMTRUNC 
VMTRUNCUS 
VMTRUNCS 
VFPEXT 
VFPEXT_SAE 
VFPEXTS 
VFPEXTS_SAE 
VFPROUND 
VFPROUND_RND 
VFPROUNDS 
VFPROUNDS_RND 
VMFPROUND 
VSHLDQ 
VSRLDQ 
VSHL 
VSRL 
VSRA 
VSHLV 
VSRLV 
VSRAV 
VSHLI 
VSRLI 
VSRAI 
KSHIFTL 
KSHIFTR 
VROTLI 
VROTRI 
CMPP 
PCMPEQ 
PCMPGT 
PHMINPOS 
MULTISHIFT 
CMPM 

Vector comparison generating mask bits for fp and integer signed and unsigned data types.

CMPMM 
CMPMM_SAE 
ADD 
SUB 
ADC 
SBB 
SMUL 
UMUL 
OR 
XOR 
AND 
BEXTR 
BEXTRI 
BZHI 
PDEP 
PEXT 
MUL_IMM 
MOVMSK 
PTEST 
TESTP 
KORTEST 
KTEST 
KADD 
PACKSS 
PACKUS 
PALIGNR 
VALIGN 
PSHUFD 
PSHUFHW 
PSHUFLW 
SHUFP 
VSHLD 
VSHRD 
VSHLDV 
VSHRDV 
SHUF128 
MOVDDUP 
MOVSHDUP 
MOVSLDUP 
MOVLHPS 
MOVHLPS 
MOVSD 
MOVSS 
MOVSH 
UNPCKL 
UNPCKH 
VPERMILPV 
VPERMILPI 
VPERMI 
VPERM2X128 
VPERMV 
VPERMV3 
VPTERNLOG 
VFIXUPIMM 
VFIXUPIMM_SAE 
VFIXUPIMMS 
VFIXUPIMMS_SAE 
VRANGE 
VRANGE_SAE 
VRANGES 
VRANGES_SAE 
VREDUCE 
VREDUCE_SAE 
VREDUCES 
VREDUCES_SAE 
VRNDSCALE 
VRNDSCALE_SAE 
VRNDSCALES 
VRNDSCALES_SAE 
VFPCLASS 
VFPCLASSS 
VBROADCAST 
VBROADCASTM 
EXTRQI 

SSE4A Extraction and Insertion.

INSERTQI 
VPSHA 
VPSHL 
VPCOM 
VPCOMU 
VPPERM 
VPERMIL2 
PMULUDQ 
PMULDQ 
MULHRS 
VPMADDUBSW 
VPMADDWD 
VPMADD52L 
VPMADD52H 
VPDPBUSD 
VPDPBUSDS 
VPDPWSSD 
VPDPWSSDS 
FNMADD 
FMSUB 
FNMSUB 
FMADDSUB 
FMSUBADD 
FMADD_RND 
FNMADD_RND 
FMSUB_RND 
FNMSUB_RND 
FMADDSUB_RND 
FMSUBADD_RND 
VFMADDC 
VFMADDC_RND 
VFCMADDC 
VFCMADDC_RND 
VFMULC 
VFMULC_RND 
VFCMULC 
VFCMULC_RND 
VFMADDCSH 
VFMADDCSH_RND 
VFCMADDCSH 
VFCMADDCSH_RND 
VFMULCSH 
VFMULCSH_RND 
VFCMULCSH 
VFCMULCSH_RND 
VPDPBSUD 
VPDPBSUDS 
VPDPBUUD 
VPDPBUUDS 
VPDPBSSD 
VPDPBSSDS 
COMPRESS 
EXPAND 
VPSHUFBITQMB 
SINT_TO_FP_RND 
UINT_TO_FP_RND 
SCALAR_SINT_TO_FP 
SCALAR_UINT_TO_FP 
SCALAR_SINT_TO_FP_RND 
SCALAR_UINT_TO_FP_RND 
CVTP2SI 
CVTP2UI 
CVTP2SI_RND 
CVTP2UI_RND 
CVTS2SI 
CVTS2UI 
CVTS2SI_RND 
CVTS2UI_RND 
CVTTP2SI 
CVTTP2UI 
CVTTP2SI_SAE 
CVTTP2UI_SAE 
CVTTS2SI 
CVTTS2UI 
CVTTS2SI_SAE 
CVTTS2UI_SAE 
CVTSI2P 
CVTUI2P 
MCVTP2SI 
MCVTP2UI 
MCVTTP2SI 
MCVTTP2UI 
MCVTSI2P 
MCVTUI2P 
CVTNE2PS2BF16 
CVTNEPS2BF16 
MCVTNEPS2BF16 
DPBF16PS 
DYN_ALLOCA 
SEG_ALLOCA 
PROBED_ALLOCA 
MFENCE 
RDRAND 
RDSEED 
RDPKRU 
WRPKRU 
PCMPISTR 
PCMPESTR 
XTEST 
RSQRT28 
RSQRT28_SAE 
RSQRT28S 
RSQRT28S_SAE 
RCP28 
RCP28_SAE 
RCP28S 
RCP28S_SAE 
EXP2 
EXP2_SAE 
CVTPS2PH 
CVTPS2PH_SAE 
CVTPH2PS 
CVTPH2PS_SAE 
MCVTPS2PH 
MCVTPS2PH_SAE 
GF2P8AFFINEINVQB 
GF2P8AFFINEQB 
GF2P8MULB 
LWPINS 
UMWAIT 
TPAUSE 
ENQCMD 
ENQCMDS 
VP2INTERSECT 
TESTUI 
FP80_ADD 
STRICT_FCMP 

X86 strict FP compare instructions.

STRICT_FCMPS 
STRICT_CMPP 
STRICT_CMPM 

Vector comparison generating mask bits for fp and integer signed and unsigned data types.

STRICT_CVTTP2SI 
STRICT_CVTTP2UI 
STRICT_VFPEXT 
STRICT_VFPROUND 
STRICT_VRNDSCALE 
STRICT_CVTSI2P 
STRICT_CVTUI2P 
STRICT_FNMADD 
STRICT_FMSUB 
STRICT_FNMSUB 
STRICT_CVTPS2PH 
STRICT_CVTPH2PS 
STRICT_FP80_ADD 
LCMPXCHG_DAG 
LCMPXCHG8_DAG 
LCMPXCHG16_DAG 
LCMPXCHG16_SAVE_RBX_DAG 
LADD 

LOCK-prefixed arithmetic read-modify-write instructions.

EFLAGS, OUTCHAIN = LADD(INCHAIN, PTR, RHS)

LSUB 
LOR 
LXOR 
LAND 
LBTS 
LBTC 
LBTR 
LBTS_RM 
LBTC_RM 
LBTR_RM 
AADD 

RAO arithmetic instructions.

OUTCHAIN = AADD(INCHAIN, PTR, RHS)

AOR 
AXOR 
AAND 
VZEXT_LOAD 
VEXTRACT_STORE 
VBROADCAST_LOAD 
SUBV_BROADCAST_LOAD 
FNSTCW16m 
FLDCW16m 
FNSTENVm 
FLDENVm 
FP_TO_INT_IN_MEM 

This instruction implements FP_TO_SINT with the integer destination in memory and a FP reg source.

This corresponds to the X86::FIST*m instructions and the rounding mode change stuff. It has two inputs (token chain and address) and two outputs (int value and token chain). Memory VT specifies the type to store to.

FILD 

This instruction implements SINT_TO_FP with the integer source in memory and FP reg result.

This corresponds to the X86::FILD*m instructions. It has two inputs (token chain and address) and two outputs (FP value and token chain). The integer source type is specified by the memory VT.

FIST 

This instruction implements a fp->int store from FP stack slots.

This corresponds to the fist instruction. It takes a chain operand, value to store, address, and glue. The memory VT specifies the type to store as.

FLD 

This instruction implements an extending load to FP stack slots.

This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain operand, and ptr to load from. The memory VT specifies the type to load from.

FST 

This instruction implements a truncating store from FP stack slots.

This corresponds to the X86::FST32m / X86::FST64m. It takes a chain operand, value to store, address, and glue. The memory VT specifies the type to store as.

VAARG_64 

These instructions grab the address of the next argument from a va_list.

(reads and modifies the va_list in memory)

VAARG_X32 
VTRUNCSTOREUS 
VTRUNCSTORES 
VMTRUNCSTOREUS 
VMTRUNCSTORES 
MGATHER 
MSCATTER 
AESENC128KL 
AESDEC128KL 
AESENC256KL 
AESDEC256KL 
AESENCWIDE128KL 
AESDECWIDE128KL 
AESENCWIDE256KL 
AESDECWIDE256KL 
CMPCCXADD 

Compare and Add if Condition is Met.

Compare value in operand 2 with value in memory of operand 1. If condition of operand 4 is met, add value operand 3 to m32 and write new value in operand 1. Operand 2 is always updated with the original value from operand 1.

VASTART_SAVE_XMM_REGS 

Definition at line 26 of file X86ISelLowering.h.