LLVM  10.0.0svn
Public Member Functions | Static Public Member Functions | Public Attributes | List of all members
llvm::AMDGPU::SIModeRegisterDefaults Struct Reference

#include "Target/AMDGPU/Utils/AMDGPUBaseInfo.h"

Collaboration diagram for llvm::AMDGPU::SIModeRegisterDefaults:
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Public Member Functions

 SIModeRegisterDefaults ()
 
 SIModeRegisterDefaults (const Function &F)
 
bool operator== (const SIModeRegisterDefaults Other) const
 
bool isInlineCompatible (SIModeRegisterDefaults CalleeMode) const
 

Static Public Member Functions

static SIModeRegisterDefaults getDefaultForCallingConv (CallingConv::ID CC)
 

Public Attributes

bool IEEE: 1
 Floating point opcodes that support exception flag gathering quiet and propagate signaling NaN inputs per IEEE 754-2008. More...
 
bool DX10Clamp: 1
 Used by the vector ALU to force DX10-style treatment of NaNs: when set, clamp NaN to zero; otherwise, pass NaN through. More...
 

Detailed Description

Definition at line 633 of file AMDGPUBaseInfo.h.

Constructor & Destructor Documentation

◆ SIModeRegisterDefaults() [1/2]

llvm::AMDGPU::SIModeRegisterDefaults::SIModeRegisterDefaults ( )
inline

Definition at line 646 of file AMDGPUBaseInfo.h.

◆ SIModeRegisterDefaults() [2/2]

llvm::AMDGPU::SIModeRegisterDefaults::SIModeRegisterDefaults ( const Function F)

Member Function Documentation

◆ getDefaultForCallingConv()

static SIModeRegisterDefaults llvm::AMDGPU::SIModeRegisterDefaults::getDefaultForCallingConv ( CallingConv::ID  CC)
inlinestatic

Definition at line 652 of file AMDGPUBaseInfo.h.

References DX10Clamp, IEEE, llvm::AMDGPU::isCompute(), and Mode.

◆ isInlineCompatible()

bool llvm::AMDGPU::SIModeRegisterDefaults::isInlineCompatible ( SIModeRegisterDefaults  CalleeMode) const
inline

Definition at line 665 of file AMDGPUBaseInfo.h.

Referenced by llvm::GCNTTIImpl::areInlineCompatible().

◆ operator==()

bool llvm::AMDGPU::SIModeRegisterDefaults::operator== ( const SIModeRegisterDefaults  Other) const
inline

Definition at line 659 of file AMDGPUBaseInfo.h.

References DX10Clamp, llvm::FPDenormal::IEEE, and IEEE.

Member Data Documentation

◆ DX10Clamp

bool llvm::AMDGPU::SIModeRegisterDefaults::DX10Clamp

Used by the vector ALU to force DX10-style treatment of NaNs: when set, clamp NaN to zero; otherwise, pass NaN through.

Definition at line 642 of file AMDGPUBaseInfo.h.

Referenced by getDefaultForCallingConv(), getSplatConstantFP(), hasAnyNonFlatUseOfReg(), isClampZeroToOne(), llvm::SITargetLowering::isKnownNeverNaNForTargetNode(), operator==(), llvm::GCNTargetMachine::parseMachineFunctionInfo(), and llvm::yaml::SIMode::SIMode().

◆ IEEE

bool llvm::AMDGPU::SIModeRegisterDefaults::IEEE

Floating point opcodes that support exception flag gathering quiet and propagate signaling NaN inputs per IEEE 754-2008.

Min_dx10 and max_dx10 become IEEE 754- 2008 compliant due to signaling NaN propagation and quieting.

Definition at line 638 of file AMDGPUBaseInfo.h.

Referenced by findUser(), getDefaultForCallingConv(), getOModValue(), hasAnyNonFlatUseOfReg(), llvm::AMDGPULegalizerInfo::legalizeMinNumMaxNum(), operator==(), llvm::GCNTargetMachine::parseMachineFunctionInfo(), and llvm::yaml::SIMode::SIMode().


The documentation for this struct was generated from the following files: