LLVM  8.0.0svn
Public Member Functions | Static Public Member Functions | Public Attributes | Static Public Attributes | Friends | List of all members
llvm::MCSchedModel Struct Reference

Machine model for scheduling, bundling, and heuristics. More...

#include "llvm/MC/MCSchedule.h"

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Public Member Functions

bool hasExtraProcessorInfo () const
 
unsigned getProcessorID () const
 
bool hasInstrSchedModel () const
 Does this machine model include instruction-level scheduling. More...
 
const MCExtraProcessorInfogetExtraProcessorInfo () const
 
bool isComplete () const
 Return true if this machine model data for all instructions with a scheduling class (itinerary class or SchedRW list). More...
 
bool isOutOfOrder () const
 Return true if machine supports out of order execution. More...
 
unsigned getNumProcResourceKinds () const
 
const MCProcResourceDescgetProcResource (unsigned ProcResourceIdx) const
 
const MCSchedClassDescgetSchedClassDesc (unsigned SchedClassIdx) const
 
int computeInstrLatency (const MCSubtargetInfo &STI, unsigned SClass) const
 
int computeInstrLatency (const MCSubtargetInfo &STI, const MCInstrInfo &MCII, const MCInst &Inst) const
 
double getReciprocalThroughput (const MCSubtargetInfo &STI, const MCInstrInfo &MCII, const MCInst &Inst) const
 

Static Public Member Functions

static int computeInstrLatency (const MCSubtargetInfo &STI, const MCSchedClassDesc &SCDesc)
 Returns the latency value for the scheduling class. More...
 
static double getReciprocalThroughput (const MCSubtargetInfo &STI, const MCSchedClassDesc &SCDesc)
 
static double getReciprocalThroughput (unsigned SchedClass, const InstrItineraryData &IID)
 
static const MCSchedModelGetDefaultSchedModel ()
 Returns the default initialized model. More...
 

Public Attributes

unsigned IssueWidth
 
unsigned MicroOpBufferSize
 
unsigned LoopMicroOpBufferSize
 
unsigned LoadLatency
 
unsigned HighLatency
 
unsigned MispredictPenalty
 
bool PostRAScheduler
 
bool CompleteModel
 
unsigned ProcID
 
const MCProcResourceDescProcResourceTable
 
const MCSchedClassDescSchedClassTable
 
unsigned NumProcResourceKinds
 
unsigned NumSchedClasses
 
const InstrItineraryInstrItineraries
 
const MCExtraProcessorInfoExtraProcessorInfo
 

Static Public Attributes

static const unsigned DefaultIssueWidth = 1
 
static const unsigned DefaultMicroOpBufferSize = 0
 
static const unsigned DefaultLoopMicroOpBufferSize = 0
 
static const unsigned DefaultLoadLatency = 4
 
static const unsigned DefaultHighLatency = 10
 
static const unsigned DefaultMispredictPenalty = 10
 
static const MCSchedModel Default
 

Friends

class InstrItineraryData
 

Detailed Description

Machine model for scheduling, bundling, and heuristics.

The machine model directly provides basic information about the microarchitecture to the scheduler in the form of properties. It also optionally refers to scheduler resource tables and itinerary tables. Scheduler resource tables model the latency and cost for each instruction type. Itinerary tables are an independent mechanism that provides a detailed reservation table describing each cycle of instruction execution. Subtargets may define any or all of the above categories of data depending on the type of CPU and selected scheduler.

The machine independent properties defined here are used by the scheduler as an abstract machine model. A real micro-architecture has a number of buffers, queues, and stages. Declaring that a given machine-independent abstract property corresponds to a specific physical property across all subtargets can't be done. Nonetheless, the abstract model is useful. Futhermore, subtargets typically extend this model with processor specific resources to model any hardware features that can be exploited by sceduling heuristics and aren't sufficiently represented in the abstract.

The abstract pipeline is built around the notion of an "issue point". This is merely a reference point for counting machine cycles. The physical machine will have pipeline stages that delay execution. The scheduler does not model those delays because they are irrelevant as long as they are consistent. Inaccuracies arise when instructions have different execution delays relative to each other, in addition to their intrinsic latency. Those special cases can be handled by TableGen constructs such as, ReadAdvance, which reduces latency when reading data, and ResourceCycles, which consumes a processor resource when writing data for a number of abstract cycles.

TODO: One tool currently missing is the ability to add a delay to ResourceCycles. That would be easy to add and would likely cover all cases currently handled by the legacy itinerary tables.

A note on out-of-order execution and, more generally, instruction buffers. Part of the CPU pipeline is always in-order. The issue point, which is the point of reference for counting cycles, only makes sense as an in-order part of the pipeline. Other parts of the pipeline are sometimes falling behind and sometimes catching up. It's only interesting to model those other, decoupled parts of the pipeline if they may be predictably resource constrained in a way that the scheduler can exploit.

The LLVM machine model distinguishes between in-order constraints and out-of-order constraints so that the target's scheduling strategy can apply appropriate heuristics. For a well-balanced CPU pipeline, out-of-order resources would not typically be treated as a hard scheduling constraint. For example, in the GenericScheduler, a delay caused by limited out-of-order resources is not directly reflected in the number of cycles that the scheduler sees between issuing an instruction and its dependent instructions. In other words, out-of-order resources don't directly increase the latency between pairs of instructions. However, they can still be used to detect potential bottlenecks across a sequence of instructions and bias the scheduling heuristics appropriately.

Definition at line 247 of file MCSchedule.h.

Member Function Documentation

◆ computeInstrLatency() [1/3]

int MCSchedModel::computeInstrLatency ( const MCSubtargetInfo STI,
const MCSchedClassDesc SCDesc 
)
static

◆ computeInstrLatency() [2/3]

int MCSchedModel::computeInstrLatency ( const MCSubtargetInfo STI,
unsigned  SClass 
) const

◆ computeInstrLatency() [3/3]

int MCSchedModel::computeInstrLatency ( const MCSubtargetInfo STI,
const MCInstrInfo MCII,
const MCInst Inst 
) const

◆ GetDefaultSchedModel()

static const MCSchedModel& llvm::MCSchedModel::GetDefaultSchedModel ( )
inlinestatic

Returns the default initialized model.

Definition at line 377 of file MCSchedule.h.

References llvm::Default.

Referenced by llvm::MCSubtargetInfo::getSchedModelForCPU(), and llvm::MCSubtargetInfo::InitMCProcessorInfo().

◆ getExtraProcessorInfo()

const MCExtraProcessorInfo& llvm::MCSchedModel::getExtraProcessorInfo ( ) const
inline

Definition at line 325 of file MCSchedule.h.

References assert().

◆ getNumProcResourceKinds()

unsigned llvm::MCSchedModel::getNumProcResourceKinds ( ) const
inline

◆ getProcessorID()

unsigned llvm::MCSchedModel::getProcessorID ( ) const
inline

◆ getProcResource()

const MCProcResourceDesc* llvm::MCSchedModel::getProcResource ( unsigned  ProcResourceIdx) const
inline

◆ getReciprocalThroughput() [1/3]

double MCSchedModel::getReciprocalThroughput ( const MCSubtargetInfo STI,
const MCSchedClassDesc SCDesc 
)
static

◆ getReciprocalThroughput() [2/3]

double MCSchedModel::getReciprocalThroughput ( unsigned  SchedClass,
const InstrItineraryData IID 
)
static

◆ getReciprocalThroughput() [3/3]

double MCSchedModel::getReciprocalThroughput ( const MCSubtargetInfo STI,
const MCInstrInfo MCII,
const MCInst Inst 
) const

◆ getSchedClassDesc()

const MCSchedClassDesc* llvm::MCSchedModel::getSchedClassDesc ( unsigned  SchedClassIdx) const
inline

◆ hasExtraProcessorInfo()

bool llvm::MCSchedModel::hasExtraProcessorInfo ( ) const
inline

Definition at line 318 of file MCSchedule.h.

◆ hasInstrSchedModel()

bool llvm::MCSchedModel::hasInstrSchedModel ( ) const
inline

Does this machine model include instruction-level scheduling.

Definition at line 323 of file MCSchedule.h.

Referenced by getLatency(), and llvm::TargetSchedModel::hasInstrSchedModel().

◆ isComplete()

bool llvm::MCSchedModel::isComplete ( ) const
inline

Return true if this machine model data for all instructions with a scheduling class (itinerary class or SchedRW list).

Definition at line 333 of file MCSchedule.h.

Referenced by llvm::TargetSchedModel::computeOperandLatency().

◆ isOutOfOrder()

bool llvm::MCSchedModel::isOutOfOrder ( ) const
inline

Return true if machine supports out of order execution.

Definition at line 336 of file MCSchedule.h.

Referenced by llvm::TargetSchedModel::computeOutputLatency().

Friends And Related Function Documentation

◆ InstrItineraryData

friend class InstrItineraryData
friend

Definition at line 313 of file MCSchedule.h.

Member Data Documentation

◆ CompleteModel

bool llvm::MCSchedModel::CompleteModel

Definition at line 305 of file MCSchedule.h.

◆ Default

const MCSchedModel MCSchedModel::Default
static
Initial value:

Definition at line 378 of file MCSchedule.h.

◆ DefaultHighLatency

const unsigned llvm::MCSchedModel::DefaultHighLatency = 10
static

Definition at line 296 of file MCSchedule.h.

◆ DefaultIssueWidth

const unsigned llvm::MCSchedModel::DefaultIssueWidth = 1
static

Definition at line 260 of file MCSchedule.h.

Referenced by getReciprocalThroughput().

◆ DefaultLoadLatency

const unsigned llvm::MCSchedModel::DefaultLoadLatency = 4
static

◆ DefaultLoopMicroOpBufferSize

const unsigned llvm::MCSchedModel::DefaultLoopMicroOpBufferSize = 0
static

Definition at line 285 of file MCSchedule.h.

◆ DefaultMicroOpBufferSize

const unsigned llvm::MCSchedModel::DefaultMicroOpBufferSize = 0
static

Definition at line 277 of file MCSchedule.h.

◆ DefaultMispredictPenalty

const unsigned llvm::MCSchedModel::DefaultMispredictPenalty = 10
static

Definition at line 301 of file MCSchedule.h.

◆ ExtraProcessorInfo

const MCExtraProcessorInfo* llvm::MCSchedModel::ExtraProcessorInfo

Definition at line 316 of file MCSchedule.h.

◆ HighLatency

unsigned llvm::MCSchedModel::HighLatency

Definition at line 295 of file MCSchedule.h.

Referenced by llvm::TargetInstrInfo::defaultDefLatency().

◆ InstrItineraries

const InstrItinerary* llvm::MCSchedModel::InstrItineraries

◆ IssueWidth

unsigned llvm::MCSchedModel::IssueWidth

◆ LoadLatency

unsigned llvm::MCSchedModel::LoadLatency

Definition at line 288 of file MCSchedule.h.

Referenced by llvm::TargetInstrInfo::defaultDefLatency().

◆ LoopMicroOpBufferSize

unsigned llvm::MCSchedModel::LoopMicroOpBufferSize

◆ MicroOpBufferSize

unsigned llvm::MCSchedModel::MicroOpBufferSize

Definition at line 276 of file MCSchedule.h.

Referenced by llvm::TargetSchedModel::getMicroOpBufferSize().

◆ MispredictPenalty

unsigned llvm::MCSchedModel::MispredictPenalty

Definition at line 300 of file MCSchedule.h.

Referenced by llvm::ARMSubtarget::getMispredictionPenalty().

◆ NumProcResourceKinds

unsigned llvm::MCSchedModel::NumProcResourceKinds

Definition at line 310 of file MCSchedule.h.

◆ NumSchedClasses

unsigned llvm::MCSchedModel::NumSchedClasses

Definition at line 311 of file MCSchedule.h.

◆ PostRAScheduler

bool llvm::MCSchedModel::PostRAScheduler

Definition at line 303 of file MCSchedule.h.

Referenced by llvm::TargetSubtargetInfo::enablePostRAScheduler().

◆ ProcID

unsigned llvm::MCSchedModel::ProcID

Definition at line 307 of file MCSchedule.h.

◆ ProcResourceTable

const MCProcResourceDesc* llvm::MCSchedModel::ProcResourceTable

Definition at line 308 of file MCSchedule.h.

◆ SchedClassTable

const MCSchedClassDesc* llvm::MCSchedModel::SchedClassTable

Definition at line 309 of file MCSchedule.h.


The documentation for this struct was generated from the following files: