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.IX Title "LLC 1"
.TH LLC 1 "1.3" "2004-07-04" "LLVM Command Guide"
.UC
.SH "NAME"
llc \- \s-1LLVM\s0 static compiler
.SH "SYNOPSIS"
.IX Header "SYNOPSIS"
\&\fBllc\fR [\fIoptions\fR] [\fIfilename\fR]
.SH "DESCRIPTION"
.IX Header "DESCRIPTION"
The \fBllc\fR command compiles \s-1LLVM\s0 bytecode into assembly language for a
specified architecture.  The assembly language output can then be passed through
a native assembler and linker to generate native code.
.PP
The choice of architecture for the output assembly code is determined as
follows, by attempting to satisfy each of the following rules in turn (first
one wins):
.Ip "\(bu" 4
If the user has specified an architecture with the \-m option, use that
architecture.
.Ip "\(bu" 4
Examine the input \s-1LLVM\s0 bytecode file: if it is little endian and has a
pointer size of 32 bits, select the Intel \s-1IA-32\s0 architecture.  If it is big
endian and has a pointer size of 64 bits, select the SparcV9 architecture.
.Ip "\(bu" 4
If \fBllc\fR was compiled on an architecture for which it can generate code, select
the architecture upon which \fBllc\fR was compiled.
.Ip "\(bu" 4
Exit with an error message telling the user to specify the output
architecture explicitly.
.SH "OPTIONS"
.IX Header "OPTIONS"
If \fIfilename\fR is \- or omitted, \fBllc\fR reads \s-1LLVM\s0 bytecode from standard input.
Otherwise, it will read \s-1LLVM\s0 bytecode from \fIfilename\fR.
.PP
If the \fB\-o\fR option is omitted, then \fBllc\fR will send its output to standard
output if the input is from standard input.  If the \fB\-o\fR option specifies \-,
then the output will also be sent to standard output.
.PP
If no \fB\-o\fR option is specified and an input file other than \- is specified,
then \fBllc\fR creates the output filename by taking the input filename,
removing any existing \fI.bc\fR extension, and adding a \fI.s\fR suffix.
.PP
Other \fBllc\fR options are as follows:
.Ip "\fB\-f\fR" 4
.IX Item "-f"
Overwrite output files. By default, \fBllc\fR will refuse to overwrite
an output file which already exists.
.Ip "\fB\-march\fR=\fIarch\fR" 4
.IX Item "-march=arch"
Specify the architecture for which to generate assembly.  Valid
architectures are:
.RS 4
.Ip "\fIx86\fR" 4
.IX Item "x86"
Intel \s-1IA-32\s0 (Pentium and above)
.Ip "\fIsparcv9\fR" 4
.IX Item "sparcv9"
64\-bit \s-1SPARC\s0 V9
.Ip "\fIc\fR" 4
.IX Item "c"
Emit C code, not assembly
.RE
.RS 4
.RE
.Ip "\fB\-enable-correct-eh-support\fR" 4
.IX Item "-enable-correct-eh-support"
Instruct the \fB\-lowerinvoke\fR pass to insert code for correct exception handling
support.  This is expensive and is by default omitted for efficiency.
.Ip "\fB\-help\fR" 4
.IX Item "-help"
Print a summary of command line options.
.Ip "\fB\-stats\fR" 4
.IX Item "-stats"
Print statistics recorded by code-generation passes.
.Ip "\fB\-time-passes\fR" 4
.IX Item "-time-passes"
Record the amount of time needed for each pass and print a report to standard
error.
.Sh "Intel IA-32\-specific Options"
.IX Subsection "Intel IA-32-specific Options"
.Ip "\fB\*(--disable-fp-elim\fR" 4
.IX Item "disable-fp-elim"
Disable frame pointer elimination optimization.
.Ip "\fB\*(--disable-pattern-isel\fR" 4
.IX Item "disable-pattern-isel"
Use the 'simple' X86 instruction selector (the default).
.Ip "\fB\*(--print-machineinstrs\fR" 4
.IX Item "print-machineinstrs"
Print generated machine code.
.Ip "\fB\*(--regalloc\fR=\fIallocator\fR" 4
.IX Item "regalloc=allocator"
Specify the register allocator to use. The default \fIallocator\fR is \fIlocal\fR.
Valid register allocators are:
.RS 4
.Ip "\fIsimple\fR" 4
.IX Item "simple"
Very simple \*(L"always spill\*(R" register allocator
.Ip "\fIlocal\fR" 4
.IX Item "local"
Local register allocator
.Ip "\fIlinearscan\fR" 4
.IX Item "linearscan"
Linear scan global register allocator (experimental)
.RE
.RS 4
.RE
.Ip "\fB\*(--spiller\fR=\fIspiller\fR" 4
.IX Item "spiller=spiller"
Specify the spiller to use for register allocators that support it.  Currently
this option is used only by the linear scan register allocator. The default
\&\fIspiller\fR is \fIlocal\fR.  Valid spillers are:
.RS 4
.Ip "\fIsimple\fR" 4
.IX Item "simple"
Simple spiller
.Ip "\fIlocal\fR" 4
.IX Item "local"
Local spiller
.RE
.RS 4
.RE
.Sh "SPARCV9\-specific Options"
.IX Subsection "SPARCV9-specific Options"
.Ip "\fB\*(--disable-peephole\fR" 4
.IX Item "disable-peephole"
Disable peephole optimization pass.
.Ip "\fB\*(--disable-sched\fR" 4
.IX Item "disable-sched"
Disable local scheduling pass.
.Ip "\fB\*(--disable-strip\fR" 4
.IX Item "disable-strip"
The Sparc backend embeds the \s-1LLVM\s0 bytecode into the assembly output.  This
option requests that symbol names be retained; by default, they are stripped out.
.Ip "\fB\*(--enable-maps\fR" 4
.IX Item "enable-maps"
Emit LLVM-to-machine code mapping information into the assembly output.
.SH "EXIT STATUS"
.IX Header "EXIT STATUS"
If \fBllc\fR succeeds, it will exit with 0.  Otherwise, if an error occurs,
it will exit with a non-zero value.
.SH "SEE ALSO"
.IX Header "SEE ALSO"
lli
.SH "AUTHORS"
.IX Header "AUTHORS"
Maintained by the \s-1LLVM\s0 Team (http://llvm.cs.uiuc.edu).