LLVM  3.7.0
AArch64BaseInfo.h
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1 //===-- AArch64BaseInfo.h - Top level definitions for AArch64 ---*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains small standalone helper functions and enum definitions for
11 // the AArch64 target useful for the compiler back-end and the MC libraries.
12 // As such, it deliberately does not include references to LLVM core
13 // code gen types, passes, etc..
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #ifndef LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
18 #define LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
19 
20 // FIXME: Is it easiest to fix this layering violation by moving the .inc
21 // #includes from AArch64MCTargetDesc.h to here?
22 #include "MCTargetDesc/AArch64MCTargetDesc.h" // For AArch64::X0 and friends.
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/StringSwitch.h"
27 
28 namespace llvm {
29 
30 inline static unsigned getWRegFromXReg(unsigned Reg) {
31  switch (Reg) {
32  case AArch64::X0: return AArch64::W0;
33  case AArch64::X1: return AArch64::W1;
34  case AArch64::X2: return AArch64::W2;
35  case AArch64::X3: return AArch64::W3;
36  case AArch64::X4: return AArch64::W4;
37  case AArch64::X5: return AArch64::W5;
38  case AArch64::X6: return AArch64::W6;
39  case AArch64::X7: return AArch64::W7;
40  case AArch64::X8: return AArch64::W8;
41  case AArch64::X9: return AArch64::W9;
42  case AArch64::X10: return AArch64::W10;
43  case AArch64::X11: return AArch64::W11;
44  case AArch64::X12: return AArch64::W12;
45  case AArch64::X13: return AArch64::W13;
46  case AArch64::X14: return AArch64::W14;
47  case AArch64::X15: return AArch64::W15;
48  case AArch64::X16: return AArch64::W16;
49  case AArch64::X17: return AArch64::W17;
50  case AArch64::X18: return AArch64::W18;
51  case AArch64::X19: return AArch64::W19;
52  case AArch64::X20: return AArch64::W20;
53  case AArch64::X21: return AArch64::W21;
54  case AArch64::X22: return AArch64::W22;
55  case AArch64::X23: return AArch64::W23;
56  case AArch64::X24: return AArch64::W24;
57  case AArch64::X25: return AArch64::W25;
58  case AArch64::X26: return AArch64::W26;
59  case AArch64::X27: return AArch64::W27;
60  case AArch64::X28: return AArch64::W28;
61  case AArch64::FP: return AArch64::W29;
62  case AArch64::LR: return AArch64::W30;
63  case AArch64::SP: return AArch64::WSP;
64  case AArch64::XZR: return AArch64::WZR;
65  }
66  // For anything else, return it unchanged.
67  return Reg;
68 }
69 
70 inline static unsigned getXRegFromWReg(unsigned Reg) {
71  switch (Reg) {
72  case AArch64::W0: return AArch64::X0;
73  case AArch64::W1: return AArch64::X1;
74  case AArch64::W2: return AArch64::X2;
75  case AArch64::W3: return AArch64::X3;
76  case AArch64::W4: return AArch64::X4;
77  case AArch64::W5: return AArch64::X5;
78  case AArch64::W6: return AArch64::X6;
79  case AArch64::W7: return AArch64::X7;
80  case AArch64::W8: return AArch64::X8;
81  case AArch64::W9: return AArch64::X9;
82  case AArch64::W10: return AArch64::X10;
83  case AArch64::W11: return AArch64::X11;
84  case AArch64::W12: return AArch64::X12;
85  case AArch64::W13: return AArch64::X13;
86  case AArch64::W14: return AArch64::X14;
87  case AArch64::W15: return AArch64::X15;
88  case AArch64::W16: return AArch64::X16;
89  case AArch64::W17: return AArch64::X17;
90  case AArch64::W18: return AArch64::X18;
91  case AArch64::W19: return AArch64::X19;
92  case AArch64::W20: return AArch64::X20;
93  case AArch64::W21: return AArch64::X21;
94  case AArch64::W22: return AArch64::X22;
95  case AArch64::W23: return AArch64::X23;
96  case AArch64::W24: return AArch64::X24;
97  case AArch64::W25: return AArch64::X25;
98  case AArch64::W26: return AArch64::X26;
99  case AArch64::W27: return AArch64::X27;
100  case AArch64::W28: return AArch64::X28;
101  case AArch64::W29: return AArch64::FP;
102  case AArch64::W30: return AArch64::LR;
103  case AArch64::WSP: return AArch64::SP;
104  case AArch64::WZR: return AArch64::XZR;
105  }
106  // For anything else, return it unchanged.
107  return Reg;
108 }
109 
110 static inline unsigned getBRegFromDReg(unsigned Reg) {
111  switch (Reg) {
112  case AArch64::D0: return AArch64::B0;
113  case AArch64::D1: return AArch64::B1;
114  case AArch64::D2: return AArch64::B2;
115  case AArch64::D3: return AArch64::B3;
116  case AArch64::D4: return AArch64::B4;
117  case AArch64::D5: return AArch64::B5;
118  case AArch64::D6: return AArch64::B6;
119  case AArch64::D7: return AArch64::B7;
120  case AArch64::D8: return AArch64::B8;
121  case AArch64::D9: return AArch64::B9;
122  case AArch64::D10: return AArch64::B10;
123  case AArch64::D11: return AArch64::B11;
124  case AArch64::D12: return AArch64::B12;
125  case AArch64::D13: return AArch64::B13;
126  case AArch64::D14: return AArch64::B14;
127  case AArch64::D15: return AArch64::B15;
128  case AArch64::D16: return AArch64::B16;
129  case AArch64::D17: return AArch64::B17;
130  case AArch64::D18: return AArch64::B18;
131  case AArch64::D19: return AArch64::B19;
132  case AArch64::D20: return AArch64::B20;
133  case AArch64::D21: return AArch64::B21;
134  case AArch64::D22: return AArch64::B22;
135  case AArch64::D23: return AArch64::B23;
136  case AArch64::D24: return AArch64::B24;
137  case AArch64::D25: return AArch64::B25;
138  case AArch64::D26: return AArch64::B26;
139  case AArch64::D27: return AArch64::B27;
140  case AArch64::D28: return AArch64::B28;
141  case AArch64::D29: return AArch64::B29;
142  case AArch64::D30: return AArch64::B30;
143  case AArch64::D31: return AArch64::B31;
144  }
145  // For anything else, return it unchanged.
146  return Reg;
147 }
148 
149 
150 static inline unsigned getDRegFromBReg(unsigned Reg) {
151  switch (Reg) {
152  case AArch64::B0: return AArch64::D0;
153  case AArch64::B1: return AArch64::D1;
154  case AArch64::B2: return AArch64::D2;
155  case AArch64::B3: return AArch64::D3;
156  case AArch64::B4: return AArch64::D4;
157  case AArch64::B5: return AArch64::D5;
158  case AArch64::B6: return AArch64::D6;
159  case AArch64::B7: return AArch64::D7;
160  case AArch64::B8: return AArch64::D8;
161  case AArch64::B9: return AArch64::D9;
162  case AArch64::B10: return AArch64::D10;
163  case AArch64::B11: return AArch64::D11;
164  case AArch64::B12: return AArch64::D12;
165  case AArch64::B13: return AArch64::D13;
166  case AArch64::B14: return AArch64::D14;
167  case AArch64::B15: return AArch64::D15;
168  case AArch64::B16: return AArch64::D16;
169  case AArch64::B17: return AArch64::D17;
170  case AArch64::B18: return AArch64::D18;
171  case AArch64::B19: return AArch64::D19;
172  case AArch64::B20: return AArch64::D20;
173  case AArch64::B21: return AArch64::D21;
174  case AArch64::B22: return AArch64::D22;
175  case AArch64::B23: return AArch64::D23;
176  case AArch64::B24: return AArch64::D24;
177  case AArch64::B25: return AArch64::D25;
178  case AArch64::B26: return AArch64::D26;
179  case AArch64::B27: return AArch64::D27;
180  case AArch64::B28: return AArch64::D28;
181  case AArch64::B29: return AArch64::D29;
182  case AArch64::B30: return AArch64::D30;
183  case AArch64::B31: return AArch64::D31;
184  }
185  // For anything else, return it unchanged.
186  return Reg;
187 }
188 
189 namespace AArch64CC {
190 
191 // The CondCodes constants map directly to the 4-bit encoding of the condition
192 // field for predicated instructions.
193 enum CondCode { // Meaning (integer) Meaning (floating-point)
194  EQ = 0x0, // Equal Equal
195  NE = 0x1, // Not equal Not equal, or unordered
196  HS = 0x2, // Unsigned higher or same >, ==, or unordered
197  LO = 0x3, // Unsigned lower Less than
198  MI = 0x4, // Minus, negative Less than
199  PL = 0x5, // Plus, positive or zero >, ==, or unordered
200  VS = 0x6, // Overflow Unordered
201  VC = 0x7, // No overflow Not unordered
202  HI = 0x8, // Unsigned higher Greater than, or unordered
203  LS = 0x9, // Unsigned lower or same Less than or equal
204  GE = 0xa, // Greater than or equal Greater than or equal
205  LT = 0xb, // Less than Less than, or unordered
206  GT = 0xc, // Greater than Greater than
207  LE = 0xd, // Less than or equal <, ==, or unordered
208  AL = 0xe, // Always (unconditional) Always (unconditional)
209  NV = 0xf, // Always (unconditional) Always (unconditional)
210  // Note the NV exists purely to disassemble 0b1111. Execution is "always".
212 };
213 
214 inline static const char *getCondCodeName(CondCode Code) {
215  switch (Code) {
216  default: llvm_unreachable("Unknown condition code");
217  case EQ: return "eq";
218  case NE: return "ne";
219  case HS: return "hs";
220  case LO: return "lo";
221  case MI: return "mi";
222  case PL: return "pl";
223  case VS: return "vs";
224  case VC: return "vc";
225  case HI: return "hi";
226  case LS: return "ls";
227  case GE: return "ge";
228  case LT: return "lt";
229  case GT: return "gt";
230  case LE: return "le";
231  case AL: return "al";
232  case NV: return "nv";
233  }
234 }
235 
236 inline static CondCode getInvertedCondCode(CondCode Code) {
237  // To reverse a condition it's necessary to only invert the low bit:
238 
239  return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1);
240 }
241 
242 /// Given a condition code, return NZCV flags that would satisfy that condition.
243 /// The flag bits are in the format expected by the ccmp instructions.
244 /// Note that many different flag settings can satisfy a given condition code,
245 /// this function just returns one of them.
246 inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) {
247  // NZCV flags encoded as expected by ccmp instructions, ARMv8 ISA 5.5.7.
248  enum { N = 8, Z = 4, C = 2, V = 1 };
249  switch (Code) {
250  default: llvm_unreachable("Unknown condition code");
251  case EQ: return Z; // Z == 1
252  case NE: return 0; // Z == 0
253  case HS: return C; // C == 1
254  case LO: return 0; // C == 0
255  case MI: return N; // N == 1
256  case PL: return 0; // N == 0
257  case VS: return V; // V == 1
258  case VC: return 0; // V == 0
259  case HI: return C; // C == 1 && Z == 0
260  case LS: return 0; // C == 0 || Z == 1
261  case GE: return 0; // N == V
262  case LT: return N; // N != V
263  case GT: return 0; // Z == 0 && N == V
264  case LE: return Z; // Z == 1 || N != V
265  }
266 }
267 } // end namespace AArch64CC
268 
269 /// Instances of this class can perform bidirectional mapping from random
270 /// identifier strings to operand encodings. For example "MSR" takes a named
271 /// system-register which must be encoded somehow and decoded for printing. This
272 /// central location means that the information for those transformations is not
273 /// duplicated and remains in sync.
274 ///
275 /// FIXME: currently the algorithm is a completely unoptimised linear
276 /// search. Obviously this could be improved, but we would probably want to work
277 /// out just how often these instructions are emitted before working on it. It
278 /// might even be optimal to just reorder the tables for the common instructions
279 /// rather than changing the algorithm.
281  struct Mapping {
282  const char *Name;
283  uint32_t Value;
284  // Set of features this mapping is available for
285  // Zero value of FeatureBitSet means the mapping is always available
287 
288  bool isNameEqual(std::string Other,
289  const FeatureBitset& FeatureBits) const {
290  if (FeatureBitSet.any() &&
291  (FeatureBitSet & FeatureBits).none())
292  return false;
293  return Name == Other;
294  }
295 
296  bool isValueEqual(uint32_t Other,
297  const FeatureBitset& FeatureBits) const {
298  if (FeatureBitSet.any() &&
299  (FeatureBitSet & FeatureBits).none())
300  return false;
301  return Value == Other;
302  }
303  };
304 
305  template<int N>
307  : Mappings(&Mappings[0]), NumMappings(N), TooBigImm(TooBigImm) {}
308 
309  // Maps value to string, depending on availability for FeatureBits given
310  StringRef toString(uint32_t Value, const FeatureBitset& FeatureBits,
311  bool &Valid) const;
312  // Maps string to value, depending on availability for FeatureBits given
313  uint32_t fromString(StringRef Name, const FeatureBitset& FeatureBits,
314  bool &Valid) const;
315 
316  /// Many of the instructions allow an alternative assembly form consisting of
317  /// a simple immediate. Currently the only valid forms are ranges [0, N) where
318  /// N being 0 indicates no immediate syntax-form is allowed.
319  bool validImm(uint32_t Value) const;
320 protected:
322  size_t NumMappings;
323  uint32_t TooBigImm;
324 };
325 
326 namespace AArch64AT {
327  enum ATValues {
328  Invalid = -1, // Op0 Op1 CRn CRm Op2
329  S1E1R = 0x43c0, // 01 000 0111 1000 000
330  S1E2R = 0x63c0, // 01 100 0111 1000 000
331  S1E3R = 0x73c0, // 01 110 0111 1000 000
332  S1E1W = 0x43c1, // 01 000 0111 1000 001
333  S1E2W = 0x63c1, // 01 100 0111 1000 001
334  S1E3W = 0x73c1, // 01 110 0111 1000 001
335  S1E0R = 0x43c2, // 01 000 0111 1000 010
336  S1E0W = 0x43c3, // 01 000 0111 1000 011
337  S12E1R = 0x63c4, // 01 100 0111 1000 100
338  S12E1W = 0x63c5, // 01 100 0111 1000 101
339  S12E0R = 0x63c6, // 01 100 0111 1000 110
340  S12E0W = 0x63c7 // 01 100 0111 1000 111
341  };
342 
344  const static Mapping ATMappings[];
345 
346  ATMapper();
347  };
348 
349 }
350 namespace AArch64DB {
351  enum DBValues {
352  Invalid = -1,
353  OSHLD = 0x1,
354  OSHST = 0x2,
355  OSH = 0x3,
356  NSHLD = 0x5,
357  NSHST = 0x6,
358  NSH = 0x7,
359  ISHLD = 0x9,
360  ISHST = 0xa,
361  ISH = 0xb,
362  LD = 0xd,
363  ST = 0xe,
364  SY = 0xf
365  };
366 
368  const static Mapping DBarrierMappings[];
369 
370  DBarrierMapper();
371  };
372 }
373 
374 namespace AArch64DC {
375  enum DCValues {
376  Invalid = -1, // Op1 CRn CRm Op2
377  ZVA = 0x5ba1, // 01 011 0111 0100 001
378  IVAC = 0x43b1, // 01 000 0111 0110 001
379  ISW = 0x43b2, // 01 000 0111 0110 010
380  CVAC = 0x5bd1, // 01 011 0111 1010 001
381  CSW = 0x43d2, // 01 000 0111 1010 010
382  CVAU = 0x5bd9, // 01 011 0111 1011 001
383  CIVAC = 0x5bf1, // 01 011 0111 1110 001
384  CISW = 0x43f2 // 01 000 0111 1110 010
385  };
386 
388  const static Mapping DCMappings[];
389 
390  DCMapper();
391  };
392 
393 }
394 
395 namespace AArch64IC {
396  enum ICValues {
397  Invalid = -1, // Op1 CRn CRm Op2
398  IALLUIS = 0x0388, // 000 0111 0001 000
399  IALLU = 0x03a8, // 000 0111 0101 000
400  IVAU = 0x1ba9 // 011 0111 0101 001
401  };
402 
403 
405  const static Mapping ICMappings[];
406 
407  ICMapper();
408  };
409 
410  static inline bool NeedsRegister(ICValues Val) {
411  return Val == IVAU;
412  }
413 }
414 
415 namespace AArch64ISB {
416  enum ISBValues {
417  Invalid = -1,
418  SY = 0xf
419  };
421  const static Mapping ISBMappings[];
422 
423  ISBMapper();
424  };
425 }
426 
427 namespace AArch64PRFM {
428  enum PRFMValues {
429  Invalid = -1,
430  PLDL1KEEP = 0x00,
431  PLDL1STRM = 0x01,
432  PLDL2KEEP = 0x02,
433  PLDL2STRM = 0x03,
434  PLDL3KEEP = 0x04,
435  PLDL3STRM = 0x05,
436  PLIL1KEEP = 0x08,
437  PLIL1STRM = 0x09,
438  PLIL2KEEP = 0x0a,
439  PLIL2STRM = 0x0b,
440  PLIL3KEEP = 0x0c,
441  PLIL3STRM = 0x0d,
442  PSTL1KEEP = 0x10,
443  PSTL1STRM = 0x11,
444  PSTL2KEEP = 0x12,
445  PSTL2STRM = 0x13,
446  PSTL3KEEP = 0x14,
447  PSTL3STRM = 0x15
448  };
449 
451  const static Mapping PRFMMappings[];
452 
453  PRFMMapper();
454  };
455 }
456 
457 namespace AArch64PState {
459  Invalid = -1,
460  SPSel = 0x05,
461  DAIFSet = 0x1e,
462  DAIFClr = 0x1f,
463 
464  // v8.1a "Privileged Access Never" extension-specific PStates
465  PAN = 0x04,
466  };
467 
469  const static Mapping PStateMappings[];
470 
471  PStateMapper();
472  };
473 
474 }
475 
476 namespace AArch64SE {
478  Invalid = -1,
484 
489 
494  };
495 }
496 
497 namespace AArch64Layout {
499  Invalid = -1,
504 
509 
510  // Bare layout for the 128-bit vector
511  // (only show ".b", ".h", ".s", ".d" without vector number)
516  };
517 }
518 
519 inline static const char *
521  switch (Layout) {
522  case AArch64Layout::VL_8B: return ".8b";
523  case AArch64Layout::VL_4H: return ".4h";
524  case AArch64Layout::VL_2S: return ".2s";
525  case AArch64Layout::VL_1D: return ".1d";
526  case AArch64Layout::VL_16B: return ".16b";
527  case AArch64Layout::VL_8H: return ".8h";
528  case AArch64Layout::VL_4S: return ".4s";
529  case AArch64Layout::VL_2D: return ".2d";
530  case AArch64Layout::VL_B: return ".b";
531  case AArch64Layout::VL_H: return ".h";
532  case AArch64Layout::VL_S: return ".s";
533  case AArch64Layout::VL_D: return ".d";
534  default: llvm_unreachable("Unknown Vector Layout");
535  }
536 }
537 
538 inline static AArch64Layout::VectorLayout
541  .Case(".8b", AArch64Layout::VL_8B)
542  .Case(".4h", AArch64Layout::VL_4H)
543  .Case(".2s", AArch64Layout::VL_2S)
544  .Case(".1d", AArch64Layout::VL_1D)
545  .Case(".16b", AArch64Layout::VL_16B)
546  .Case(".8h", AArch64Layout::VL_8H)
547  .Case(".4s", AArch64Layout::VL_4S)
548  .Case(".2d", AArch64Layout::VL_2D)
549  .Case(".b", AArch64Layout::VL_B)
550  .Case(".h", AArch64Layout::VL_H)
551  .Case(".s", AArch64Layout::VL_S)
552  .Case(".d", AArch64Layout::VL_D)
554 }
555 
556 namespace AArch64SysReg {
558  MDCCSR_EL0 = 0x9808, // 10 011 0000 0001 000
559  DBGDTRRX_EL0 = 0x9828, // 10 011 0000 0101 000
560  MDRAR_EL1 = 0x8080, // 10 000 0001 0000 000
561  OSLSR_EL1 = 0x808c, // 10 000 0001 0001 100
562  DBGAUTHSTATUS_EL1 = 0x83f6, // 10 000 0111 1110 110
563  PMCEID0_EL0 = 0xdce6, // 11 011 1001 1100 110
564  PMCEID1_EL0 = 0xdce7, // 11 011 1001 1100 111
565  MIDR_EL1 = 0xc000, // 11 000 0000 0000 000
566  CCSIDR_EL1 = 0xc800, // 11 001 0000 0000 000
567  CLIDR_EL1 = 0xc801, // 11 001 0000 0000 001
568  CTR_EL0 = 0xd801, // 11 011 0000 0000 001
569  MPIDR_EL1 = 0xc005, // 11 000 0000 0000 101
570  REVIDR_EL1 = 0xc006, // 11 000 0000 0000 110
571  AIDR_EL1 = 0xc807, // 11 001 0000 0000 111
572  DCZID_EL0 = 0xd807, // 11 011 0000 0000 111
573  ID_PFR0_EL1 = 0xc008, // 11 000 0000 0001 000
574  ID_PFR1_EL1 = 0xc009, // 11 000 0000 0001 001
575  ID_DFR0_EL1 = 0xc00a, // 11 000 0000 0001 010
576  ID_AFR0_EL1 = 0xc00b, // 11 000 0000 0001 011
577  ID_MMFR0_EL1 = 0xc00c, // 11 000 0000 0001 100
578  ID_MMFR1_EL1 = 0xc00d, // 11 000 0000 0001 101
579  ID_MMFR2_EL1 = 0xc00e, // 11 000 0000 0001 110
580  ID_MMFR3_EL1 = 0xc00f, // 11 000 0000 0001 111
581  ID_ISAR0_EL1 = 0xc010, // 11 000 0000 0010 000
582  ID_ISAR1_EL1 = 0xc011, // 11 000 0000 0010 001
583  ID_ISAR2_EL1 = 0xc012, // 11 000 0000 0010 010
584  ID_ISAR3_EL1 = 0xc013, // 11 000 0000 0010 011
585  ID_ISAR4_EL1 = 0xc014, // 11 000 0000 0010 100
586  ID_ISAR5_EL1 = 0xc015, // 11 000 0000 0010 101
587  ID_A64PFR0_EL1 = 0xc020, // 11 000 0000 0100 000
588  ID_A64PFR1_EL1 = 0xc021, // 11 000 0000 0100 001
589  ID_A64DFR0_EL1 = 0xc028, // 11 000 0000 0101 000
590  ID_A64DFR1_EL1 = 0xc029, // 11 000 0000 0101 001
591  ID_A64AFR0_EL1 = 0xc02c, // 11 000 0000 0101 100
592  ID_A64AFR1_EL1 = 0xc02d, // 11 000 0000 0101 101
593  ID_A64ISAR0_EL1 = 0xc030, // 11 000 0000 0110 000
594  ID_A64ISAR1_EL1 = 0xc031, // 11 000 0000 0110 001
595  ID_A64MMFR0_EL1 = 0xc038, // 11 000 0000 0111 000
596  ID_A64MMFR1_EL1 = 0xc039, // 11 000 0000 0111 001
597  MVFR0_EL1 = 0xc018, // 11 000 0000 0011 000
598  MVFR1_EL1 = 0xc019, // 11 000 0000 0011 001
599  MVFR2_EL1 = 0xc01a, // 11 000 0000 0011 010
600  RVBAR_EL1 = 0xc601, // 11 000 1100 0000 001
601  RVBAR_EL2 = 0xe601, // 11 100 1100 0000 001
602  RVBAR_EL3 = 0xf601, // 11 110 1100 0000 001
603  ISR_EL1 = 0xc608, // 11 000 1100 0001 000
604  CNTPCT_EL0 = 0xdf01, // 11 011 1110 0000 001
605  CNTVCT_EL0 = 0xdf02, // 11 011 1110 0000 010
606  ID_MMFR4_EL1 = 0xc016, // 11 000 0000 0010 110
607 
608  // Trace registers
609  TRCSTATR = 0x8818, // 10 001 0000 0011 000
610  TRCIDR8 = 0x8806, // 10 001 0000 0000 110
611  TRCIDR9 = 0x880e, // 10 001 0000 0001 110
612  TRCIDR10 = 0x8816, // 10 001 0000 0010 110
613  TRCIDR11 = 0x881e, // 10 001 0000 0011 110
614  TRCIDR12 = 0x8826, // 10 001 0000 0100 110
615  TRCIDR13 = 0x882e, // 10 001 0000 0101 110
616  TRCIDR0 = 0x8847, // 10 001 0000 1000 111
617  TRCIDR1 = 0x884f, // 10 001 0000 1001 111
618  TRCIDR2 = 0x8857, // 10 001 0000 1010 111
619  TRCIDR3 = 0x885f, // 10 001 0000 1011 111
620  TRCIDR4 = 0x8867, // 10 001 0000 1100 111
621  TRCIDR5 = 0x886f, // 10 001 0000 1101 111
622  TRCIDR6 = 0x8877, // 10 001 0000 1110 111
623  TRCIDR7 = 0x887f, // 10 001 0000 1111 111
624  TRCOSLSR = 0x888c, // 10 001 0001 0001 100
625  TRCPDSR = 0x88ac, // 10 001 0001 0101 100
626  TRCDEVAFF0 = 0x8bd6, // 10 001 0111 1010 110
627  TRCDEVAFF1 = 0x8bde, // 10 001 0111 1011 110
628  TRCLSR = 0x8bee, // 10 001 0111 1101 110
629  TRCAUTHSTATUS = 0x8bf6, // 10 001 0111 1110 110
630  TRCDEVARCH = 0x8bfe, // 10 001 0111 1111 110
631  TRCDEVID = 0x8b97, // 10 001 0111 0010 111
632  TRCDEVTYPE = 0x8b9f, // 10 001 0111 0011 111
633  TRCPIDR4 = 0x8ba7, // 10 001 0111 0100 111
634  TRCPIDR5 = 0x8baf, // 10 001 0111 0101 111
635  TRCPIDR6 = 0x8bb7, // 10 001 0111 0110 111
636  TRCPIDR7 = 0x8bbf, // 10 001 0111 0111 111
637  TRCPIDR0 = 0x8bc7, // 10 001 0111 1000 111
638  TRCPIDR1 = 0x8bcf, // 10 001 0111 1001 111
639  TRCPIDR2 = 0x8bd7, // 10 001 0111 1010 111
640  TRCPIDR3 = 0x8bdf, // 10 001 0111 1011 111
641  TRCCIDR0 = 0x8be7, // 10 001 0111 1100 111
642  TRCCIDR1 = 0x8bef, // 10 001 0111 1101 111
643  TRCCIDR2 = 0x8bf7, // 10 001 0111 1110 111
644  TRCCIDR3 = 0x8bff, // 10 001 0111 1111 111
645 
646  // GICv3 registers
647  ICC_IAR1_EL1 = 0xc660, // 11 000 1100 1100 000
648  ICC_IAR0_EL1 = 0xc640, // 11 000 1100 1000 000
649  ICC_HPPIR1_EL1 = 0xc662, // 11 000 1100 1100 010
650  ICC_HPPIR0_EL1 = 0xc642, // 11 000 1100 1000 010
651  ICC_RPR_EL1 = 0xc65b, // 11 000 1100 1011 011
652  ICH_VTR_EL2 = 0xe659, // 11 100 1100 1011 001
653  ICH_EISR_EL2 = 0xe65b, // 11 100 1100 1011 011
654  ICH_ELSR_EL2 = 0xe65d // 11 100 1100 1011 101
655  };
656 
658  DBGDTRTX_EL0 = 0x9828, // 10 011 0000 0101 000
659  OSLAR_EL1 = 0x8084, // 10 000 0001 0000 100
660  PMSWINC_EL0 = 0xdce4, // 11 011 1001 1100 100
661 
662  // Trace Registers
663  TRCOSLAR = 0x8884, // 10 001 0001 0000 100
664  TRCLAR = 0x8be6, // 10 001 0111 1100 110
665 
666  // GICv3 registers
667  ICC_EOIR1_EL1 = 0xc661, // 11 000 1100 1100 001
668  ICC_EOIR0_EL1 = 0xc641, // 11 000 1100 1000 001
669  ICC_DIR_EL1 = 0xc659, // 11 000 1100 1011 001
670  ICC_SGI1R_EL1 = 0xc65d, // 11 000 1100 1011 101
671  ICC_ASGI1R_EL1 = 0xc65e, // 11 000 1100 1011 110
672  ICC_SGI0R_EL1 = 0xc65f // 11 000 1100 1011 111
673  };
674 
676  Invalid = -1, // Op0 Op1 CRn CRm Op2
677  OSDTRRX_EL1 = 0x8002, // 10 000 0000 0000 010
678  OSDTRTX_EL1 = 0x801a, // 10 000 0000 0011 010
679  TEECR32_EL1 = 0x9000, // 10 010 0000 0000 000
680  MDCCINT_EL1 = 0x8010, // 10 000 0000 0010 000
681  MDSCR_EL1 = 0x8012, // 10 000 0000 0010 010
682  DBGDTR_EL0 = 0x9820, // 10 011 0000 0100 000
683  OSECCR_EL1 = 0x8032, // 10 000 0000 0110 010
684  DBGVCR32_EL2 = 0xa038, // 10 100 0000 0111 000
685  DBGBVR0_EL1 = 0x8004, // 10 000 0000 0000 100
686  DBGBVR1_EL1 = 0x800c, // 10 000 0000 0001 100
687  DBGBVR2_EL1 = 0x8014, // 10 000 0000 0010 100
688  DBGBVR3_EL1 = 0x801c, // 10 000 0000 0011 100
689  DBGBVR4_EL1 = 0x8024, // 10 000 0000 0100 100
690  DBGBVR5_EL1 = 0x802c, // 10 000 0000 0101 100
691  DBGBVR6_EL1 = 0x8034, // 10 000 0000 0110 100
692  DBGBVR7_EL1 = 0x803c, // 10 000 0000 0111 100
693  DBGBVR8_EL1 = 0x8044, // 10 000 0000 1000 100
694  DBGBVR9_EL1 = 0x804c, // 10 000 0000 1001 100
695  DBGBVR10_EL1 = 0x8054, // 10 000 0000 1010 100
696  DBGBVR11_EL1 = 0x805c, // 10 000 0000 1011 100
697  DBGBVR12_EL1 = 0x8064, // 10 000 0000 1100 100
698  DBGBVR13_EL1 = 0x806c, // 10 000 0000 1101 100
699  DBGBVR14_EL1 = 0x8074, // 10 000 0000 1110 100
700  DBGBVR15_EL1 = 0x807c, // 10 000 0000 1111 100
701  DBGBCR0_EL1 = 0x8005, // 10 000 0000 0000 101
702  DBGBCR1_EL1 = 0x800d, // 10 000 0000 0001 101
703  DBGBCR2_EL1 = 0x8015, // 10 000 0000 0010 101
704  DBGBCR3_EL1 = 0x801d, // 10 000 0000 0011 101
705  DBGBCR4_EL1 = 0x8025, // 10 000 0000 0100 101
706  DBGBCR5_EL1 = 0x802d, // 10 000 0000 0101 101
707  DBGBCR6_EL1 = 0x8035, // 10 000 0000 0110 101
708  DBGBCR7_EL1 = 0x803d, // 10 000 0000 0111 101
709  DBGBCR8_EL1 = 0x8045, // 10 000 0000 1000 101
710  DBGBCR9_EL1 = 0x804d, // 10 000 0000 1001 101
711  DBGBCR10_EL1 = 0x8055, // 10 000 0000 1010 101
712  DBGBCR11_EL1 = 0x805d, // 10 000 0000 1011 101
713  DBGBCR12_EL1 = 0x8065, // 10 000 0000 1100 101
714  DBGBCR13_EL1 = 0x806d, // 10 000 0000 1101 101
715  DBGBCR14_EL1 = 0x8075, // 10 000 0000 1110 101
716  DBGBCR15_EL1 = 0x807d, // 10 000 0000 1111 101
717  DBGWVR0_EL1 = 0x8006, // 10 000 0000 0000 110
718  DBGWVR1_EL1 = 0x800e, // 10 000 0000 0001 110
719  DBGWVR2_EL1 = 0x8016, // 10 000 0000 0010 110
720  DBGWVR3_EL1 = 0x801e, // 10 000 0000 0011 110
721  DBGWVR4_EL1 = 0x8026, // 10 000 0000 0100 110
722  DBGWVR5_EL1 = 0x802e, // 10 000 0000 0101 110
723  DBGWVR6_EL1 = 0x8036, // 10 000 0000 0110 110
724  DBGWVR7_EL1 = 0x803e, // 10 000 0000 0111 110
725  DBGWVR8_EL1 = 0x8046, // 10 000 0000 1000 110
726  DBGWVR9_EL1 = 0x804e, // 10 000 0000 1001 110
727  DBGWVR10_EL1 = 0x8056, // 10 000 0000 1010 110
728  DBGWVR11_EL1 = 0x805e, // 10 000 0000 1011 110
729  DBGWVR12_EL1 = 0x8066, // 10 000 0000 1100 110
730  DBGWVR13_EL1 = 0x806e, // 10 000 0000 1101 110
731  DBGWVR14_EL1 = 0x8076, // 10 000 0000 1110 110
732  DBGWVR15_EL1 = 0x807e, // 10 000 0000 1111 110
733  DBGWCR0_EL1 = 0x8007, // 10 000 0000 0000 111
734  DBGWCR1_EL1 = 0x800f, // 10 000 0000 0001 111
735  DBGWCR2_EL1 = 0x8017, // 10 000 0000 0010 111
736  DBGWCR3_EL1 = 0x801f, // 10 000 0000 0011 111
737  DBGWCR4_EL1 = 0x8027, // 10 000 0000 0100 111
738  DBGWCR5_EL1 = 0x802f, // 10 000 0000 0101 111
739  DBGWCR6_EL1 = 0x8037, // 10 000 0000 0110 111
740  DBGWCR7_EL1 = 0x803f, // 10 000 0000 0111 111
741  DBGWCR8_EL1 = 0x8047, // 10 000 0000 1000 111
742  DBGWCR9_EL1 = 0x804f, // 10 000 0000 1001 111
743  DBGWCR10_EL1 = 0x8057, // 10 000 0000 1010 111
744  DBGWCR11_EL1 = 0x805f, // 10 000 0000 1011 111
745  DBGWCR12_EL1 = 0x8067, // 10 000 0000 1100 111
746  DBGWCR13_EL1 = 0x806f, // 10 000 0000 1101 111
747  DBGWCR14_EL1 = 0x8077, // 10 000 0000 1110 111
748  DBGWCR15_EL1 = 0x807f, // 10 000 0000 1111 111
749  TEEHBR32_EL1 = 0x9080, // 10 010 0001 0000 000
750  OSDLR_EL1 = 0x809c, // 10 000 0001 0011 100
751  DBGPRCR_EL1 = 0x80a4, // 10 000 0001 0100 100
752  DBGCLAIMSET_EL1 = 0x83c6, // 10 000 0111 1000 110
753  DBGCLAIMCLR_EL1 = 0x83ce, // 10 000 0111 1001 110
754  CSSELR_EL1 = 0xd000, // 11 010 0000 0000 000
755  VPIDR_EL2 = 0xe000, // 11 100 0000 0000 000
756  VMPIDR_EL2 = 0xe005, // 11 100 0000 0000 101
757  CPACR_EL1 = 0xc082, // 11 000 0001 0000 010
758  SCTLR_EL1 = 0xc080, // 11 000 0001 0000 000
759  SCTLR_EL2 = 0xe080, // 11 100 0001 0000 000
760  SCTLR_EL3 = 0xf080, // 11 110 0001 0000 000
761  ACTLR_EL1 = 0xc081, // 11 000 0001 0000 001
762  ACTLR_EL2 = 0xe081, // 11 100 0001 0000 001
763  ACTLR_EL3 = 0xf081, // 11 110 0001 0000 001
764  HCR_EL2 = 0xe088, // 11 100 0001 0001 000
765  SCR_EL3 = 0xf088, // 11 110 0001 0001 000
766  MDCR_EL2 = 0xe089, // 11 100 0001 0001 001
767  SDER32_EL3 = 0xf089, // 11 110 0001 0001 001
768  CPTR_EL2 = 0xe08a, // 11 100 0001 0001 010
769  CPTR_EL3 = 0xf08a, // 11 110 0001 0001 010
770  HSTR_EL2 = 0xe08b, // 11 100 0001 0001 011
771  HACR_EL2 = 0xe08f, // 11 100 0001 0001 111
772  MDCR_EL3 = 0xf099, // 11 110 0001 0011 001
773  TTBR0_EL1 = 0xc100, // 11 000 0010 0000 000
774  TTBR0_EL2 = 0xe100, // 11 100 0010 0000 000
775  TTBR0_EL3 = 0xf100, // 11 110 0010 0000 000
776  TTBR1_EL1 = 0xc101, // 11 000 0010 0000 001
777  TCR_EL1 = 0xc102, // 11 000 0010 0000 010
778  TCR_EL2 = 0xe102, // 11 100 0010 0000 010
779  TCR_EL3 = 0xf102, // 11 110 0010 0000 010
780  VTTBR_EL2 = 0xe108, // 11 100 0010 0001 000
781  VTCR_EL2 = 0xe10a, // 11 100 0010 0001 010
782  DACR32_EL2 = 0xe180, // 11 100 0011 0000 000
783  SPSR_EL1 = 0xc200, // 11 000 0100 0000 000
784  SPSR_EL2 = 0xe200, // 11 100 0100 0000 000
785  SPSR_EL3 = 0xf200, // 11 110 0100 0000 000
786  ELR_EL1 = 0xc201, // 11 000 0100 0000 001
787  ELR_EL2 = 0xe201, // 11 100 0100 0000 001
788  ELR_EL3 = 0xf201, // 11 110 0100 0000 001
789  SP_EL0 = 0xc208, // 11 000 0100 0001 000
790  SP_EL1 = 0xe208, // 11 100 0100 0001 000
791  SP_EL2 = 0xf208, // 11 110 0100 0001 000
792  SPSel = 0xc210, // 11 000 0100 0010 000
793  NZCV = 0xda10, // 11 011 0100 0010 000
794  DAIF = 0xda11, // 11 011 0100 0010 001
795  CurrentEL = 0xc212, // 11 000 0100 0010 010
796  SPSR_irq = 0xe218, // 11 100 0100 0011 000
797  SPSR_abt = 0xe219, // 11 100 0100 0011 001
798  SPSR_und = 0xe21a, // 11 100 0100 0011 010
799  SPSR_fiq = 0xe21b, // 11 100 0100 0011 011
800  FPCR = 0xda20, // 11 011 0100 0100 000
801  FPSR = 0xda21, // 11 011 0100 0100 001
802  DSPSR_EL0 = 0xda28, // 11 011 0100 0101 000
803  DLR_EL0 = 0xda29, // 11 011 0100 0101 001
804  IFSR32_EL2 = 0xe281, // 11 100 0101 0000 001
805  AFSR0_EL1 = 0xc288, // 11 000 0101 0001 000
806  AFSR0_EL2 = 0xe288, // 11 100 0101 0001 000
807  AFSR0_EL3 = 0xf288, // 11 110 0101 0001 000
808  AFSR1_EL1 = 0xc289, // 11 000 0101 0001 001
809  AFSR1_EL2 = 0xe289, // 11 100 0101 0001 001
810  AFSR1_EL3 = 0xf289, // 11 110 0101 0001 001
811  ESR_EL1 = 0xc290, // 11 000 0101 0010 000
812  ESR_EL2 = 0xe290, // 11 100 0101 0010 000
813  ESR_EL3 = 0xf290, // 11 110 0101 0010 000
814  FPEXC32_EL2 = 0xe298, // 11 100 0101 0011 000
815  FAR_EL1 = 0xc300, // 11 000 0110 0000 000
816  FAR_EL2 = 0xe300, // 11 100 0110 0000 000
817  FAR_EL3 = 0xf300, // 11 110 0110 0000 000
818  HPFAR_EL2 = 0xe304, // 11 100 0110 0000 100
819  PAR_EL1 = 0xc3a0, // 11 000 0111 0100 000
820  PMCR_EL0 = 0xdce0, // 11 011 1001 1100 000
821  PMCNTENSET_EL0 = 0xdce1, // 11 011 1001 1100 001
822  PMCNTENCLR_EL0 = 0xdce2, // 11 011 1001 1100 010
823  PMOVSCLR_EL0 = 0xdce3, // 11 011 1001 1100 011
824  PMSELR_EL0 = 0xdce5, // 11 011 1001 1100 101
825  PMCCNTR_EL0 = 0xdce8, // 11 011 1001 1101 000
826  PMXEVTYPER_EL0 = 0xdce9, // 11 011 1001 1101 001
827  PMXEVCNTR_EL0 = 0xdcea, // 11 011 1001 1101 010
828  PMUSERENR_EL0 = 0xdcf0, // 11 011 1001 1110 000
829  PMINTENSET_EL1 = 0xc4f1, // 11 000 1001 1110 001
830  PMINTENCLR_EL1 = 0xc4f2, // 11 000 1001 1110 010
831  PMOVSSET_EL0 = 0xdcf3, // 11 011 1001 1110 011
832  MAIR_EL1 = 0xc510, // 11 000 1010 0010 000
833  MAIR_EL2 = 0xe510, // 11 100 1010 0010 000
834  MAIR_EL3 = 0xf510, // 11 110 1010 0010 000
835  AMAIR_EL1 = 0xc518, // 11 000 1010 0011 000
836  AMAIR_EL2 = 0xe518, // 11 100 1010 0011 000
837  AMAIR_EL3 = 0xf518, // 11 110 1010 0011 000
838  VBAR_EL1 = 0xc600, // 11 000 1100 0000 000
839  VBAR_EL2 = 0xe600, // 11 100 1100 0000 000
840  VBAR_EL3 = 0xf600, // 11 110 1100 0000 000
841  RMR_EL1 = 0xc602, // 11 000 1100 0000 010
842  RMR_EL2 = 0xe602, // 11 100 1100 0000 010
843  RMR_EL3 = 0xf602, // 11 110 1100 0000 010
844  CONTEXTIDR_EL1 = 0xc681, // 11 000 1101 0000 001
845  TPIDR_EL0 = 0xde82, // 11 011 1101 0000 010
846  TPIDR_EL2 = 0xe682, // 11 100 1101 0000 010
847  TPIDR_EL3 = 0xf682, // 11 110 1101 0000 010
848  TPIDRRO_EL0 = 0xde83, // 11 011 1101 0000 011
849  TPIDR_EL1 = 0xc684, // 11 000 1101 0000 100
850  CNTFRQ_EL0 = 0xdf00, // 11 011 1110 0000 000
851  CNTVOFF_EL2 = 0xe703, // 11 100 1110 0000 011
852  CNTKCTL_EL1 = 0xc708, // 11 000 1110 0001 000
853  CNTHCTL_EL2 = 0xe708, // 11 100 1110 0001 000
854  CNTP_TVAL_EL0 = 0xdf10, // 11 011 1110 0010 000
855  CNTHP_TVAL_EL2 = 0xe710, // 11 100 1110 0010 000
856  CNTPS_TVAL_EL1 = 0xff10, // 11 111 1110 0010 000
857  CNTP_CTL_EL0 = 0xdf11, // 11 011 1110 0010 001
858  CNTHP_CTL_EL2 = 0xe711, // 11 100 1110 0010 001
859  CNTPS_CTL_EL1 = 0xff11, // 11 111 1110 0010 001
860  CNTP_CVAL_EL0 = 0xdf12, // 11 011 1110 0010 010
861  CNTHP_CVAL_EL2 = 0xe712, // 11 100 1110 0010 010
862  CNTPS_CVAL_EL1 = 0xff12, // 11 111 1110 0010 010
863  CNTV_TVAL_EL0 = 0xdf18, // 11 011 1110 0011 000
864  CNTV_CTL_EL0 = 0xdf19, // 11 011 1110 0011 001
865  CNTV_CVAL_EL0 = 0xdf1a, // 11 011 1110 0011 010
866  PMEVCNTR0_EL0 = 0xdf40, // 11 011 1110 1000 000
867  PMEVCNTR1_EL0 = 0xdf41, // 11 011 1110 1000 001
868  PMEVCNTR2_EL0 = 0xdf42, // 11 011 1110 1000 010
869  PMEVCNTR3_EL0 = 0xdf43, // 11 011 1110 1000 011
870  PMEVCNTR4_EL0 = 0xdf44, // 11 011 1110 1000 100
871  PMEVCNTR5_EL0 = 0xdf45, // 11 011 1110 1000 101
872  PMEVCNTR6_EL0 = 0xdf46, // 11 011 1110 1000 110
873  PMEVCNTR7_EL0 = 0xdf47, // 11 011 1110 1000 111
874  PMEVCNTR8_EL0 = 0xdf48, // 11 011 1110 1001 000
875  PMEVCNTR9_EL0 = 0xdf49, // 11 011 1110 1001 001
876  PMEVCNTR10_EL0 = 0xdf4a, // 11 011 1110 1001 010
877  PMEVCNTR11_EL0 = 0xdf4b, // 11 011 1110 1001 011
878  PMEVCNTR12_EL0 = 0xdf4c, // 11 011 1110 1001 100
879  PMEVCNTR13_EL0 = 0xdf4d, // 11 011 1110 1001 101
880  PMEVCNTR14_EL0 = 0xdf4e, // 11 011 1110 1001 110
881  PMEVCNTR15_EL0 = 0xdf4f, // 11 011 1110 1001 111
882  PMEVCNTR16_EL0 = 0xdf50, // 11 011 1110 1010 000
883  PMEVCNTR17_EL0 = 0xdf51, // 11 011 1110 1010 001
884  PMEVCNTR18_EL0 = 0xdf52, // 11 011 1110 1010 010
885  PMEVCNTR19_EL0 = 0xdf53, // 11 011 1110 1010 011
886  PMEVCNTR20_EL0 = 0xdf54, // 11 011 1110 1010 100
887  PMEVCNTR21_EL0 = 0xdf55, // 11 011 1110 1010 101
888  PMEVCNTR22_EL0 = 0xdf56, // 11 011 1110 1010 110
889  PMEVCNTR23_EL0 = 0xdf57, // 11 011 1110 1010 111
890  PMEVCNTR24_EL0 = 0xdf58, // 11 011 1110 1011 000
891  PMEVCNTR25_EL0 = 0xdf59, // 11 011 1110 1011 001
892  PMEVCNTR26_EL0 = 0xdf5a, // 11 011 1110 1011 010
893  PMEVCNTR27_EL0 = 0xdf5b, // 11 011 1110 1011 011
894  PMEVCNTR28_EL0 = 0xdf5c, // 11 011 1110 1011 100
895  PMEVCNTR29_EL0 = 0xdf5d, // 11 011 1110 1011 101
896  PMEVCNTR30_EL0 = 0xdf5e, // 11 011 1110 1011 110
897  PMCCFILTR_EL0 = 0xdf7f, // 11 011 1110 1111 111
898  PMEVTYPER0_EL0 = 0xdf60, // 11 011 1110 1100 000
899  PMEVTYPER1_EL0 = 0xdf61, // 11 011 1110 1100 001
900  PMEVTYPER2_EL0 = 0xdf62, // 11 011 1110 1100 010
901  PMEVTYPER3_EL0 = 0xdf63, // 11 011 1110 1100 011
902  PMEVTYPER4_EL0 = 0xdf64, // 11 011 1110 1100 100
903  PMEVTYPER5_EL0 = 0xdf65, // 11 011 1110 1100 101
904  PMEVTYPER6_EL0 = 0xdf66, // 11 011 1110 1100 110
905  PMEVTYPER7_EL0 = 0xdf67, // 11 011 1110 1100 111
906  PMEVTYPER8_EL0 = 0xdf68, // 11 011 1110 1101 000
907  PMEVTYPER9_EL0 = 0xdf69, // 11 011 1110 1101 001
908  PMEVTYPER10_EL0 = 0xdf6a, // 11 011 1110 1101 010
909  PMEVTYPER11_EL0 = 0xdf6b, // 11 011 1110 1101 011
910  PMEVTYPER12_EL0 = 0xdf6c, // 11 011 1110 1101 100
911  PMEVTYPER13_EL0 = 0xdf6d, // 11 011 1110 1101 101
912  PMEVTYPER14_EL0 = 0xdf6e, // 11 011 1110 1101 110
913  PMEVTYPER15_EL0 = 0xdf6f, // 11 011 1110 1101 111
914  PMEVTYPER16_EL0 = 0xdf70, // 11 011 1110 1110 000
915  PMEVTYPER17_EL0 = 0xdf71, // 11 011 1110 1110 001
916  PMEVTYPER18_EL0 = 0xdf72, // 11 011 1110 1110 010
917  PMEVTYPER19_EL0 = 0xdf73, // 11 011 1110 1110 011
918  PMEVTYPER20_EL0 = 0xdf74, // 11 011 1110 1110 100
919  PMEVTYPER21_EL0 = 0xdf75, // 11 011 1110 1110 101
920  PMEVTYPER22_EL0 = 0xdf76, // 11 011 1110 1110 110
921  PMEVTYPER23_EL0 = 0xdf77, // 11 011 1110 1110 111
922  PMEVTYPER24_EL0 = 0xdf78, // 11 011 1110 1111 000
923  PMEVTYPER25_EL0 = 0xdf79, // 11 011 1110 1111 001
924  PMEVTYPER26_EL0 = 0xdf7a, // 11 011 1110 1111 010
925  PMEVTYPER27_EL0 = 0xdf7b, // 11 011 1110 1111 011
926  PMEVTYPER28_EL0 = 0xdf7c, // 11 011 1110 1111 100
927  PMEVTYPER29_EL0 = 0xdf7d, // 11 011 1110 1111 101
928  PMEVTYPER30_EL0 = 0xdf7e, // 11 011 1110 1111 110
929 
930  // Trace registers
931  TRCPRGCTLR = 0x8808, // 10 001 0000 0001 000
932  TRCPROCSELR = 0x8810, // 10 001 0000 0010 000
933  TRCCONFIGR = 0x8820, // 10 001 0000 0100 000
934  TRCAUXCTLR = 0x8830, // 10 001 0000 0110 000
935  TRCEVENTCTL0R = 0x8840, // 10 001 0000 1000 000
936  TRCEVENTCTL1R = 0x8848, // 10 001 0000 1001 000
937  TRCSTALLCTLR = 0x8858, // 10 001 0000 1011 000
938  TRCTSCTLR = 0x8860, // 10 001 0000 1100 000
939  TRCSYNCPR = 0x8868, // 10 001 0000 1101 000
940  TRCCCCTLR = 0x8870, // 10 001 0000 1110 000
941  TRCBBCTLR = 0x8878, // 10 001 0000 1111 000
942  TRCTRACEIDR = 0x8801, // 10 001 0000 0000 001
943  TRCQCTLR = 0x8809, // 10 001 0000 0001 001
944  TRCVICTLR = 0x8802, // 10 001 0000 0000 010
945  TRCVIIECTLR = 0x880a, // 10 001 0000 0001 010
946  TRCVISSCTLR = 0x8812, // 10 001 0000 0010 010
947  TRCVIPCSSCTLR = 0x881a, // 10 001 0000 0011 010
948  TRCVDCTLR = 0x8842, // 10 001 0000 1000 010
949  TRCVDSACCTLR = 0x884a, // 10 001 0000 1001 010
950  TRCVDARCCTLR = 0x8852, // 10 001 0000 1010 010
951  TRCSEQEVR0 = 0x8804, // 10 001 0000 0000 100
952  TRCSEQEVR1 = 0x880c, // 10 001 0000 0001 100
953  TRCSEQEVR2 = 0x8814, // 10 001 0000 0010 100
954  TRCSEQRSTEVR = 0x8834, // 10 001 0000 0110 100
955  TRCSEQSTR = 0x883c, // 10 001 0000 0111 100
956  TRCEXTINSELR = 0x8844, // 10 001 0000 1000 100
957  TRCCNTRLDVR0 = 0x8805, // 10 001 0000 0000 101
958  TRCCNTRLDVR1 = 0x880d, // 10 001 0000 0001 101
959  TRCCNTRLDVR2 = 0x8815, // 10 001 0000 0010 101
960  TRCCNTRLDVR3 = 0x881d, // 10 001 0000 0011 101
961  TRCCNTCTLR0 = 0x8825, // 10 001 0000 0100 101
962  TRCCNTCTLR1 = 0x882d, // 10 001 0000 0101 101
963  TRCCNTCTLR2 = 0x8835, // 10 001 0000 0110 101
964  TRCCNTCTLR3 = 0x883d, // 10 001 0000 0111 101
965  TRCCNTVR0 = 0x8845, // 10 001 0000 1000 101
966  TRCCNTVR1 = 0x884d, // 10 001 0000 1001 101
967  TRCCNTVR2 = 0x8855, // 10 001 0000 1010 101
968  TRCCNTVR3 = 0x885d, // 10 001 0000 1011 101
969  TRCIMSPEC0 = 0x8807, // 10 001 0000 0000 111
970  TRCIMSPEC1 = 0x880f, // 10 001 0000 0001 111
971  TRCIMSPEC2 = 0x8817, // 10 001 0000 0010 111
972  TRCIMSPEC3 = 0x881f, // 10 001 0000 0011 111
973  TRCIMSPEC4 = 0x8827, // 10 001 0000 0100 111
974  TRCIMSPEC5 = 0x882f, // 10 001 0000 0101 111
975  TRCIMSPEC6 = 0x8837, // 10 001 0000 0110 111
976  TRCIMSPEC7 = 0x883f, // 10 001 0000 0111 111
977  TRCRSCTLR2 = 0x8890, // 10 001 0001 0010 000
978  TRCRSCTLR3 = 0x8898, // 10 001 0001 0011 000
979  TRCRSCTLR4 = 0x88a0, // 10 001 0001 0100 000
980  TRCRSCTLR5 = 0x88a8, // 10 001 0001 0101 000
981  TRCRSCTLR6 = 0x88b0, // 10 001 0001 0110 000
982  TRCRSCTLR7 = 0x88b8, // 10 001 0001 0111 000
983  TRCRSCTLR8 = 0x88c0, // 10 001 0001 1000 000
984  TRCRSCTLR9 = 0x88c8, // 10 001 0001 1001 000
985  TRCRSCTLR10 = 0x88d0, // 10 001 0001 1010 000
986  TRCRSCTLR11 = 0x88d8, // 10 001 0001 1011 000
987  TRCRSCTLR12 = 0x88e0, // 10 001 0001 1100 000
988  TRCRSCTLR13 = 0x88e8, // 10 001 0001 1101 000
989  TRCRSCTLR14 = 0x88f0, // 10 001 0001 1110 000
990  TRCRSCTLR15 = 0x88f8, // 10 001 0001 1111 000
991  TRCRSCTLR16 = 0x8881, // 10 001 0001 0000 001
992  TRCRSCTLR17 = 0x8889, // 10 001 0001 0001 001
993  TRCRSCTLR18 = 0x8891, // 10 001 0001 0010 001
994  TRCRSCTLR19 = 0x8899, // 10 001 0001 0011 001
995  TRCRSCTLR20 = 0x88a1, // 10 001 0001 0100 001
996  TRCRSCTLR21 = 0x88a9, // 10 001 0001 0101 001
997  TRCRSCTLR22 = 0x88b1, // 10 001 0001 0110 001
998  TRCRSCTLR23 = 0x88b9, // 10 001 0001 0111 001
999  TRCRSCTLR24 = 0x88c1, // 10 001 0001 1000 001
1000  TRCRSCTLR25 = 0x88c9, // 10 001 0001 1001 001
1001  TRCRSCTLR26 = 0x88d1, // 10 001 0001 1010 001
1002  TRCRSCTLR27 = 0x88d9, // 10 001 0001 1011 001
1003  TRCRSCTLR28 = 0x88e1, // 10 001 0001 1100 001
1004  TRCRSCTLR29 = 0x88e9, // 10 001 0001 1101 001
1005  TRCRSCTLR30 = 0x88f1, // 10 001 0001 1110 001
1006  TRCRSCTLR31 = 0x88f9, // 10 001 0001 1111 001
1007  TRCSSCCR0 = 0x8882, // 10 001 0001 0000 010
1008  TRCSSCCR1 = 0x888a, // 10 001 0001 0001 010
1009  TRCSSCCR2 = 0x8892, // 10 001 0001 0010 010
1010  TRCSSCCR3 = 0x889a, // 10 001 0001 0011 010
1011  TRCSSCCR4 = 0x88a2, // 10 001 0001 0100 010
1012  TRCSSCCR5 = 0x88aa, // 10 001 0001 0101 010
1013  TRCSSCCR6 = 0x88b2, // 10 001 0001 0110 010
1014  TRCSSCCR7 = 0x88ba, // 10 001 0001 0111 010
1015  TRCSSCSR0 = 0x88c2, // 10 001 0001 1000 010
1016  TRCSSCSR1 = 0x88ca, // 10 001 0001 1001 010
1017  TRCSSCSR2 = 0x88d2, // 10 001 0001 1010 010
1018  TRCSSCSR3 = 0x88da, // 10 001 0001 1011 010
1019  TRCSSCSR4 = 0x88e2, // 10 001 0001 1100 010
1020  TRCSSCSR5 = 0x88ea, // 10 001 0001 1101 010
1021  TRCSSCSR6 = 0x88f2, // 10 001 0001 1110 010
1022  TRCSSCSR7 = 0x88fa, // 10 001 0001 1111 010
1023  TRCSSPCICR0 = 0x8883, // 10 001 0001 0000 011
1024  TRCSSPCICR1 = 0x888b, // 10 001 0001 0001 011
1025  TRCSSPCICR2 = 0x8893, // 10 001 0001 0010 011
1026  TRCSSPCICR3 = 0x889b, // 10 001 0001 0011 011
1027  TRCSSPCICR4 = 0x88a3, // 10 001 0001 0100 011
1028  TRCSSPCICR5 = 0x88ab, // 10 001 0001 0101 011
1029  TRCSSPCICR6 = 0x88b3, // 10 001 0001 0110 011
1030  TRCSSPCICR7 = 0x88bb, // 10 001 0001 0111 011
1031  TRCPDCR = 0x88a4, // 10 001 0001 0100 100
1032  TRCACVR0 = 0x8900, // 10 001 0010 0000 000
1033  TRCACVR1 = 0x8910, // 10 001 0010 0010 000
1034  TRCACVR2 = 0x8920, // 10 001 0010 0100 000
1035  TRCACVR3 = 0x8930, // 10 001 0010 0110 000
1036  TRCACVR4 = 0x8940, // 10 001 0010 1000 000
1037  TRCACVR5 = 0x8950, // 10 001 0010 1010 000
1038  TRCACVR6 = 0x8960, // 10 001 0010 1100 000
1039  TRCACVR7 = 0x8970, // 10 001 0010 1110 000
1040  TRCACVR8 = 0x8901, // 10 001 0010 0000 001
1041  TRCACVR9 = 0x8911, // 10 001 0010 0010 001
1042  TRCACVR10 = 0x8921, // 10 001 0010 0100 001
1043  TRCACVR11 = 0x8931, // 10 001 0010 0110 001
1044  TRCACVR12 = 0x8941, // 10 001 0010 1000 001
1045  TRCACVR13 = 0x8951, // 10 001 0010 1010 001
1046  TRCACVR14 = 0x8961, // 10 001 0010 1100 001
1047  TRCACVR15 = 0x8971, // 10 001 0010 1110 001
1048  TRCACATR0 = 0x8902, // 10 001 0010 0000 010
1049  TRCACATR1 = 0x8912, // 10 001 0010 0010 010
1050  TRCACATR2 = 0x8922, // 10 001 0010 0100 010
1051  TRCACATR3 = 0x8932, // 10 001 0010 0110 010
1052  TRCACATR4 = 0x8942, // 10 001 0010 1000 010
1053  TRCACATR5 = 0x8952, // 10 001 0010 1010 010
1054  TRCACATR6 = 0x8962, // 10 001 0010 1100 010
1055  TRCACATR7 = 0x8972, // 10 001 0010 1110 010
1056  TRCACATR8 = 0x8903, // 10 001 0010 0000 011
1057  TRCACATR9 = 0x8913, // 10 001 0010 0010 011
1058  TRCACATR10 = 0x8923, // 10 001 0010 0100 011
1059  TRCACATR11 = 0x8933, // 10 001 0010 0110 011
1060  TRCACATR12 = 0x8943, // 10 001 0010 1000 011
1061  TRCACATR13 = 0x8953, // 10 001 0010 1010 011
1062  TRCACATR14 = 0x8963, // 10 001 0010 1100 011
1063  TRCACATR15 = 0x8973, // 10 001 0010 1110 011
1064  TRCDVCVR0 = 0x8904, // 10 001 0010 0000 100
1065  TRCDVCVR1 = 0x8924, // 10 001 0010 0100 100
1066  TRCDVCVR2 = 0x8944, // 10 001 0010 1000 100
1067  TRCDVCVR3 = 0x8964, // 10 001 0010 1100 100
1068  TRCDVCVR4 = 0x8905, // 10 001 0010 0000 101
1069  TRCDVCVR5 = 0x8925, // 10 001 0010 0100 101
1070  TRCDVCVR6 = 0x8945, // 10 001 0010 1000 101
1071  TRCDVCVR7 = 0x8965, // 10 001 0010 1100 101
1072  TRCDVCMR0 = 0x8906, // 10 001 0010 0000 110
1073  TRCDVCMR1 = 0x8926, // 10 001 0010 0100 110
1074  TRCDVCMR2 = 0x8946, // 10 001 0010 1000 110
1075  TRCDVCMR3 = 0x8966, // 10 001 0010 1100 110
1076  TRCDVCMR4 = 0x8907, // 10 001 0010 0000 111
1077  TRCDVCMR5 = 0x8927, // 10 001 0010 0100 111
1078  TRCDVCMR6 = 0x8947, // 10 001 0010 1000 111
1079  TRCDVCMR7 = 0x8967, // 10 001 0010 1100 111
1080  TRCCIDCVR0 = 0x8980, // 10 001 0011 0000 000
1081  TRCCIDCVR1 = 0x8990, // 10 001 0011 0010 000
1082  TRCCIDCVR2 = 0x89a0, // 10 001 0011 0100 000
1083  TRCCIDCVR3 = 0x89b0, // 10 001 0011 0110 000
1084  TRCCIDCVR4 = 0x89c0, // 10 001 0011 1000 000
1085  TRCCIDCVR5 = 0x89d0, // 10 001 0011 1010 000
1086  TRCCIDCVR6 = 0x89e0, // 10 001 0011 1100 000
1087  TRCCIDCVR7 = 0x89f0, // 10 001 0011 1110 000
1088  TRCVMIDCVR0 = 0x8981, // 10 001 0011 0000 001
1089  TRCVMIDCVR1 = 0x8991, // 10 001 0011 0010 001
1090  TRCVMIDCVR2 = 0x89a1, // 10 001 0011 0100 001
1091  TRCVMIDCVR3 = 0x89b1, // 10 001 0011 0110 001
1092  TRCVMIDCVR4 = 0x89c1, // 10 001 0011 1000 001
1093  TRCVMIDCVR5 = 0x89d1, // 10 001 0011 1010 001
1094  TRCVMIDCVR6 = 0x89e1, // 10 001 0011 1100 001
1095  TRCVMIDCVR7 = 0x89f1, // 10 001 0011 1110 001
1096  TRCCIDCCTLR0 = 0x8982, // 10 001 0011 0000 010
1097  TRCCIDCCTLR1 = 0x898a, // 10 001 0011 0001 010
1098  TRCVMIDCCTLR0 = 0x8992, // 10 001 0011 0010 010
1099  TRCVMIDCCTLR1 = 0x899a, // 10 001 0011 0011 010
1100  TRCITCTRL = 0x8b84, // 10 001 0111 0000 100
1101  TRCCLAIMSET = 0x8bc6, // 10 001 0111 1000 110
1102  TRCCLAIMCLR = 0x8bce, // 10 001 0111 1001 110
1103 
1104  // GICv3 registers
1105  ICC_BPR1_EL1 = 0xc663, // 11 000 1100 1100 011
1106  ICC_BPR0_EL1 = 0xc643, // 11 000 1100 1000 011
1107  ICC_PMR_EL1 = 0xc230, // 11 000 0100 0110 000
1108  ICC_CTLR_EL1 = 0xc664, // 11 000 1100 1100 100
1109  ICC_CTLR_EL3 = 0xf664, // 11 110 1100 1100 100
1110  ICC_SRE_EL1 = 0xc665, // 11 000 1100 1100 101
1111  ICC_SRE_EL2 = 0xe64d, // 11 100 1100 1001 101
1112  ICC_SRE_EL3 = 0xf665, // 11 110 1100 1100 101
1113  ICC_IGRPEN0_EL1 = 0xc666, // 11 000 1100 1100 110
1114  ICC_IGRPEN1_EL1 = 0xc667, // 11 000 1100 1100 111
1115  ICC_IGRPEN1_EL3 = 0xf667, // 11 110 1100 1100 111
1116  ICC_SEIEN_EL1 = 0xc668, // 11 000 1100 1101 000
1117  ICC_AP0R0_EL1 = 0xc644, // 11 000 1100 1000 100
1118  ICC_AP0R1_EL1 = 0xc645, // 11 000 1100 1000 101
1119  ICC_AP0R2_EL1 = 0xc646, // 11 000 1100 1000 110
1120  ICC_AP0R3_EL1 = 0xc647, // 11 000 1100 1000 111
1121  ICC_AP1R0_EL1 = 0xc648, // 11 000 1100 1001 000
1122  ICC_AP1R1_EL1 = 0xc649, // 11 000 1100 1001 001
1123  ICC_AP1R2_EL1 = 0xc64a, // 11 000 1100 1001 010
1124  ICC_AP1R3_EL1 = 0xc64b, // 11 000 1100 1001 011
1125  ICH_AP0R0_EL2 = 0xe640, // 11 100 1100 1000 000
1126  ICH_AP0R1_EL2 = 0xe641, // 11 100 1100 1000 001
1127  ICH_AP0R2_EL2 = 0xe642, // 11 100 1100 1000 010
1128  ICH_AP0R3_EL2 = 0xe643, // 11 100 1100 1000 011
1129  ICH_AP1R0_EL2 = 0xe648, // 11 100 1100 1001 000
1130  ICH_AP1R1_EL2 = 0xe649, // 11 100 1100 1001 001
1131  ICH_AP1R2_EL2 = 0xe64a, // 11 100 1100 1001 010
1132  ICH_AP1R3_EL2 = 0xe64b, // 11 100 1100 1001 011
1133  ICH_HCR_EL2 = 0xe658, // 11 100 1100 1011 000
1134  ICH_MISR_EL2 = 0xe65a, // 11 100 1100 1011 010
1135  ICH_VMCR_EL2 = 0xe65f, // 11 100 1100 1011 111
1136  ICH_VSEIR_EL2 = 0xe64c, // 11 100 1100 1001 100
1137  ICH_LR0_EL2 = 0xe660, // 11 100 1100 1100 000
1138  ICH_LR1_EL2 = 0xe661, // 11 100 1100 1100 001
1139  ICH_LR2_EL2 = 0xe662, // 11 100 1100 1100 010
1140  ICH_LR3_EL2 = 0xe663, // 11 100 1100 1100 011
1141  ICH_LR4_EL2 = 0xe664, // 11 100 1100 1100 100
1142  ICH_LR5_EL2 = 0xe665, // 11 100 1100 1100 101
1143  ICH_LR6_EL2 = 0xe666, // 11 100 1100 1100 110
1144  ICH_LR7_EL2 = 0xe667, // 11 100 1100 1100 111
1145  ICH_LR8_EL2 = 0xe668, // 11 100 1100 1101 000
1146  ICH_LR9_EL2 = 0xe669, // 11 100 1100 1101 001
1147  ICH_LR10_EL2 = 0xe66a, // 11 100 1100 1101 010
1148  ICH_LR11_EL2 = 0xe66b, // 11 100 1100 1101 011
1149  ICH_LR12_EL2 = 0xe66c, // 11 100 1100 1101 100
1150  ICH_LR13_EL2 = 0xe66d, // 11 100 1100 1101 101
1151  ICH_LR14_EL2 = 0xe66e, // 11 100 1100 1101 110
1152  ICH_LR15_EL2 = 0xe66f, // 11 100 1100 1101 111
1153 
1154  // v8.1a "Privileged Access Never" extension-specific system registers
1155  PAN = 0xc213, // 11 000 0100 0010 011
1156 
1157  // v8.1a "Limited Ordering Regions" extension-specific system registers
1158  LORSA_EL1 = 0xc520, // 11 000 1010 0100 000
1159  LOREA_EL1 = 0xc521, // 11 000 1010 0100 001
1160  LORN_EL1 = 0xc522, // 11 000 1010 0100 010
1161  LORC_EL1 = 0xc523, // 11 000 1010 0100 011
1162  LORID_EL1 = 0xc527, // 11 000 1010 0100 111
1163 
1164  // v8.1a "Virtualization host extensions" system registers
1165  TTBR1_EL2 = 0xe101, // 11 100 0010 0000 001
1166  CONTEXTIDR_EL2 = 0xe681, // 11 100 1101 0000 001
1167  CNTHV_TVAL_EL2 = 0xe718, // 11 100 1110 0011 000
1168  CNTHV_CVAL_EL2 = 0xe71a, // 11 100 1110 0011 010
1169  CNTHV_CTL_EL2 = 0xe719, // 11 100 1110 0011 001
1170  SCTLR_EL12 = 0xe880, // 11 101 0001 0000 000
1171  CPACR_EL12 = 0xe882, // 11 101 0001 0000 010
1172  TTBR0_EL12 = 0xe900, // 11 101 0010 0000 000
1173  TTBR1_EL12 = 0xe901, // 11 101 0010 0000 001
1174  TCR_EL12 = 0xe902, // 11 101 0010 0000 010
1175  AFSR0_EL12 = 0xea88, // 11 101 0101 0001 000
1176  AFSR1_EL12 = 0xea89, // 11 101 0101 0001 001
1177  ESR_EL12 = 0xea90, // 11 101 0101 0010 000
1178  FAR_EL12 = 0xeb00, // 11 101 0110 0000 000
1179  MAIR_EL12 = 0xed10, // 11 101 1010 0010 000
1180  AMAIR_EL12 = 0xed18, // 11 101 1010 0011 000
1181  VBAR_EL12 = 0xee00, // 11 101 1100 0000 000
1182  CONTEXTIDR_EL12 = 0xee81, // 11 101 1101 0000 001
1183  CNTKCTL_EL12 = 0xef08, // 11 101 1110 0001 000
1184  CNTP_TVAL_EL02 = 0xef10, // 11 101 1110 0010 000
1185  CNTP_CTL_EL02 = 0xef11, // 11 101 1110 0010 001
1186  CNTP_CVAL_EL02 = 0xef12, // 11 101 1110 0010 010
1187  CNTV_TVAL_EL02 = 0xef18, // 11 101 1110 0011 000
1188  CNTV_CTL_EL02 = 0xef19, // 11 101 1110 0011 001
1189  CNTV_CVAL_EL02 = 0xef1a, // 11 101 1110 0011 010
1190  SPSR_EL12 = 0xea00, // 11 101 0100 0000 000
1191  ELR_EL12 = 0xea01, // 11 101 0100 0000 001
1192 
1193  // Cyclone specific system registers
1195  };
1196 
1197  // Note that these do not inherit from AArch64NamedImmMapper. This class is
1198  // sufficiently different in its behaviour that I don't believe it's worth
1199  // burdening the common AArch64NamedImmMapper with abstractions only needed in
1200  // this one case.
1201  struct SysRegMapper {
1203 
1206 
1208  uint32_t fromString(StringRef Name, const FeatureBitset& FeatureBits,
1209  bool &Valid) const;
1210  std::string toString(uint32_t Bits, const FeatureBitset& FeatureBits) const;
1211  };
1212 
1215  MSRMapper();
1216  };
1217 
1220  MRSMapper();
1221  };
1222 
1223  uint32_t ParseGenericRegister(StringRef Name, bool &Valid);
1224 }
1225 
1226 namespace AArch64TLBI {
1227  enum TLBIValues {
1228  Invalid = -1, // Op0 Op1 CRn CRm Op2
1229  IPAS2E1IS = 0x6401, // 01 100 1000 0000 001
1230  IPAS2LE1IS = 0x6405, // 01 100 1000 0000 101
1231  VMALLE1IS = 0x4418, // 01 000 1000 0011 000
1232  ALLE2IS = 0x6418, // 01 100 1000 0011 000
1233  ALLE3IS = 0x7418, // 01 110 1000 0011 000
1234  VAE1IS = 0x4419, // 01 000 1000 0011 001
1235  VAE2IS = 0x6419, // 01 100 1000 0011 001
1236  VAE3IS = 0x7419, // 01 110 1000 0011 001
1237  ASIDE1IS = 0x441a, // 01 000 1000 0011 010
1238  VAAE1IS = 0x441b, // 01 000 1000 0011 011
1239  ALLE1IS = 0x641c, // 01 100 1000 0011 100
1240  VALE1IS = 0x441d, // 01 000 1000 0011 101
1241  VALE2IS = 0x641d, // 01 100 1000 0011 101
1242  VALE3IS = 0x741d, // 01 110 1000 0011 101
1243  VMALLS12E1IS = 0x641e, // 01 100 1000 0011 110
1244  VAALE1IS = 0x441f, // 01 000 1000 0011 111
1245  IPAS2E1 = 0x6421, // 01 100 1000 0100 001
1246  IPAS2LE1 = 0x6425, // 01 100 1000 0100 101
1247  VMALLE1 = 0x4438, // 01 000 1000 0111 000
1248  ALLE2 = 0x6438, // 01 100 1000 0111 000
1249  ALLE3 = 0x7438, // 01 110 1000 0111 000
1250  VAE1 = 0x4439, // 01 000 1000 0111 001
1251  VAE2 = 0x6439, // 01 100 1000 0111 001
1252  VAE3 = 0x7439, // 01 110 1000 0111 001
1253  ASIDE1 = 0x443a, // 01 000 1000 0111 010
1254  VAAE1 = 0x443b, // 01 000 1000 0111 011
1255  ALLE1 = 0x643c, // 01 100 1000 0111 100
1256  VALE1 = 0x443d, // 01 000 1000 0111 101
1257  VALE2 = 0x643d, // 01 100 1000 0111 101
1258  VALE3 = 0x743d, // 01 110 1000 0111 101
1259  VMALLS12E1 = 0x643e, // 01 100 1000 0111 110
1260  VAALE1 = 0x443f // 01 000 1000 0111 111
1261  };
1262 
1264  const static Mapping TLBIMappings[];
1265 
1266  TLBIMapper();
1267  };
1268 
1269  static inline bool NeedsRegister(TLBIValues Val) {
1270  switch (Val) {
1271  case VMALLE1IS:
1272  case ALLE2IS:
1273  case ALLE3IS:
1274  case ALLE1IS:
1275  case VMALLS12E1IS:
1276  case VMALLE1:
1277  case ALLE2:
1278  case ALLE3:
1279  case ALLE1:
1280  case VMALLS12E1:
1281  return false;
1282  default:
1283  return true;
1284  }
1285  }
1286 }
1287 
1288 namespace AArch64II {
1289  /// Target Operand Flag enum.
1290  enum TOF {
1291  //===------------------------------------------------------------------===//
1292  // AArch64 Specific MachineOperand flags.
1293 
1295 
1297 
1298  /// MO_PAGE - A symbol operand with this flag represents the pc-relative
1299  /// offset of the 4K page containing the symbol. This is used with the
1300  /// ADRP instruction.
1301  MO_PAGE = 1,
1302 
1303  /// MO_PAGEOFF - A symbol operand with this flag represents the offset of
1304  /// that symbol within a 4K page. This offset is added to the page address
1305  /// to produce the complete address.
1307 
1308  /// MO_G3 - A symbol operand with this flag (granule 3) represents the high
1309  /// 16-bits of a 64-bit address, used in a MOVZ or MOVK instruction
1310  MO_G3 = 3,
1311 
1312  /// MO_G2 - A symbol operand with this flag (granule 2) represents the bits
1313  /// 32-47 of a 64-bit address, used in a MOVZ or MOVK instruction
1314  MO_G2 = 4,
1315 
1316  /// MO_G1 - A symbol operand with this flag (granule 1) represents the bits
1317  /// 16-31 of a 64-bit address, used in a MOVZ or MOVK instruction
1318  MO_G1 = 5,
1319 
1320  /// MO_G0 - A symbol operand with this flag (granule 0) represents the bits
1321  /// 0-15 of a 64-bit address, used in a MOVZ or MOVK instruction
1322  MO_G0 = 6,
1323 
1324  /// MO_HI12 - This flag indicates that a symbol operand represents the bits
1325  /// 13-24 of a 64-bit address, used in a arithmetic immediate-shifted-left-
1326  /// by-12-bits instruction.
1327  MO_HI12 = 7,
1328 
1329  /// MO_GOT - This flag indicates that a symbol operand represents the
1330  /// address of the GOT entry for the symbol, rather than the address of
1331  /// the symbol itself.
1332  MO_GOT = 0x10,
1333 
1334  /// MO_NC - Indicates whether the linker is expected to check the symbol
1335  /// reference for overflow. For example in an ADRP/ADD pair of relocations
1336  /// the ADRP usually does check, but not the ADD.
1337  MO_NC = 0x20,
1338 
1339  /// MO_TLS - Indicates that the operand being accessed is some kind of
1340  /// thread-local symbol. On Darwin, only one type of thread-local access
1341  /// exists (pre linker-relaxation), but on ELF the TLSModel used for the
1342  /// referee will affect interpretation.
1343  MO_TLS = 0x40,
1344 
1345  /// MO_CONSTPOOL - This flag indicates that a symbol operand represents
1346  /// the address of a constant pool entry for the symbol, rather than the
1347  /// address of the symbol itself.
1349  };
1350 } // end namespace AArch64II
1351 
1352 } // end namespace llvm
1353 
1354 #endif
std::string toString(uint32_t Bits, const FeatureBitset &FeatureBits) const
MO_G3 - A symbol operand with this flag (granule 3) represents the high 16-bits of a 64-bit address...
static const Mapping PRFMMappings[]
static const Mapping DCMappings[]
static unsigned getBRegFromDReg(unsigned Reg)
MO_PAGE - A symbol operand with this flag represents the pc-relative offset of the 4K page containing...
static CondCode getInvertedCondCode(CondCode Code)
static const Mapping DBarrierMappings[]
TOF
Target Operand Flag enum.
static const Mapping PStateMappings[]
static unsigned getXRegFromWReg(unsigned Reg)
MO_G0 - A symbol operand with this flag (granule 0) represents the bits 0-15 of a 64-bit address...
Instances of this class can perform bidirectional mapping from random identifier strings to operand e...
bool isNameEqual(std::string Other, const FeatureBitset &FeatureBits) const
StringSwitch & Case(const char(&S)[N], const T &Value)
Definition: StringSwitch.h:55
static const Mapping ATMappings[]
MO_G2 - A symbol operand with this flag (granule 2) represents the bits 32-47 of a 64-bit address...
static const AArch64NamedImmMapper::Mapping MSRMappings[]
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
static bool NeedsRegister(ICValues Val)
Reg
All possible values of the reg field in the ModR/M byte.
static const char * getCondCodeName(CondCode Code)
MO_CONSTPOOL - This flag indicates that a symbol operand represents the address of a constant pool en...
ELFYAML::ELF_STO Other
Definition: ELFYAML.cpp:591
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
StringRef toString(uint32_t Value, const FeatureBitset &FeatureBits, bool &Valid) const
AArch64NamedImmMapper(const Mapping(&Mappings)[N], uint32_t TooBigImm)
const AArch64NamedImmMapper::Mapping * InstMappings
static unsigned getWRegFromXReg(unsigned Reg)
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:42
MO_G1 - A symbol operand with this flag (granule 1) represents the bits 16-31 of a 64-bit address...
static const Mapping ISBMappings[]
MO_HI12 - This flag indicates that a symbol operand represents the bits 13-24 of a 64-bit address...
static bool NeedsRegister(TLBIValues Val)
MO_TLS - Indicates that the operand being accessed is some kind of thread-local symbol.
static const Mapping ICMappings[]
uint32_t ParseGenericRegister(StringRef Name, bool &Valid)
R Default(const T &Value) const
Definition: StringSwitch.h:111
static unsigned getNZCVToSatisfyCondCode(CondCode Code)
Given a condition code, return NZCV flags that would satisfy that condition.
uint32_t fromString(StringRef Name, const FeatureBitset &FeatureBits, bool &Valid) const
static unsigned getDRegFromBReg(unsigned Reg)
static const AArch64NamedImmMapper::Mapping SysRegMappings[]
#define N
MO_PAGEOFF - A symbol operand with this flag represents the offset of that symbol within a 4K page...
uint32_t fromString(StringRef Name, const FeatureBitset &FeatureBits, bool &Valid) const
static const char * AArch64VectorLayoutToString(AArch64Layout::VectorLayout Layout)
LLVM Value Representation.
Definition: Value.h:69
static const AArch64NamedImmMapper::Mapping MRSMappings[]
static AArch64Layout::VectorLayout AArch64StringToVectorLayout(StringRef LayoutStr)
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:40
MO_NC - Indicates whether the linker is expected to check the symbol reference for overflow...
bool isValueEqual(uint32_t Other, const FeatureBitset &FeatureBits) const
static const Mapping TLBIMappings[]
bool validImm(uint32_t Value) const
Many of the instructions allow an alternative assembly form consisting of a simple immediate...