LLVM  3.7.0
CodeGen/Passes.h
Go to the documentation of this file.
1 //===-- Passes.h - Target independent code generation passes ----*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines interfaces to access the target independent code generation
11 // passes provided by the LLVM backend.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_CODEGEN_PASSES_H
16 #define LLVM_CODEGEN_PASSES_H
17 
18 #include "llvm/Pass.h"
20 #include <functional>
21 #include <string>
22 
23 namespace llvm {
24 
25 class MachineFunctionPass;
26 class PassConfigImpl;
27 class PassInfo;
28 class ScheduleDAGInstrs;
29 class TargetLowering;
30 class TargetLoweringBase;
31 class TargetRegisterClass;
32 class raw_ostream;
33 struct MachineSchedContext;
34 
35 // The old pass manager infrastructure is hidden in a legacy namespace now.
36 namespace legacy {
37 class PassManagerBase;
38 }
40 
41 /// Discriminated union of Pass ID types.
42 ///
43 /// The PassConfig API prefers dealing with IDs because they are safer and more
44 /// efficient. IDs decouple configuration from instantiation. This way, when a
45 /// pass is overriden, it isn't unnecessarily instantiated. It is also unsafe to
46 /// refer to a Pass pointer after adding it to a pass manager, which deletes
47 /// redundant pass instances.
48 ///
49 /// However, it is convient to directly instantiate target passes with
50 /// non-default ctors. These often don't have a registered PassInfo. Rather than
51 /// force all target passes to implement the pass registry boilerplate, allow
52 /// the PassConfig API to handle either type.
53 ///
54 /// AnalysisID is sadly char*, so PointerIntPair won't work.
56  union {
58  Pass *P;
59  };
60  bool IsInstance;
61 public:
62  IdentifyingPassPtr() : P(nullptr), IsInstance(false) {}
63  IdentifyingPassPtr(AnalysisID IDPtr) : ID(IDPtr), IsInstance(false) {}
64  IdentifyingPassPtr(Pass *InstancePtr) : P(InstancePtr), IsInstance(true) {}
65 
66  bool isValid() const { return P; }
67  bool isInstance() const { return IsInstance; }
68 
69  AnalysisID getID() const {
70  assert(!IsInstance && "Not a Pass ID");
71  return ID;
72  }
73  Pass *getInstance() const {
74  assert(IsInstance && "Not a Pass Instance");
75  return P;
76  }
77 };
78 
79 template <> struct isPodLike<IdentifyingPassPtr> {
80  static const bool value = true;
81 };
82 
83 /// Target-Independent Code Generator Pass Configuration Options.
84 ///
85 /// This is an ImmutablePass solely for the purpose of exposing CodeGen options
86 /// to the internals of other CodeGen passes.
88 public:
89  /// Pseudo Pass IDs. These are defined within TargetPassConfig because they
90  /// are unregistered pass IDs. They are only useful for use with
91  /// TargetPassConfig APIs to identify multiple occurrences of the same pass.
92  ///
93 
94  /// EarlyTailDuplicate - A clone of the TailDuplicate pass that runs early
95  /// during codegen, on SSA form.
96  static char EarlyTailDuplicateID;
97 
98  /// PostRAMachineLICM - A clone of the LICM pass that runs during late machine
99  /// optimization after regalloc.
100  static char PostRAMachineLICMID;
101 
102 private:
103  PassManagerBase *PM;
104  AnalysisID StartBefore, StartAfter;
105  AnalysisID StopAfter;
106  bool Started;
107  bool Stopped;
108  bool AddingMachinePasses;
109 
110 protected:
112  PassConfigImpl *Impl; // Internal data structures
113  bool Initialized; // Flagged after all passes are configured.
114 
115  // Target Pass Options
116  // Targets provide a default setting, user flags override.
117  //
119 
120  /// Default setting for -enable-tail-merge on this target.
122 
123  /// Default setting for -enable-shrink-wrap on this target.
125 
126 public:
127  TargetPassConfig(TargetMachine *tm, PassManagerBase &pm);
128  // Dummy constructor.
130 
131  ~TargetPassConfig() override;
132 
133  static char ID;
134 
135  /// Get the right type of TargetMachine for this target.
136  template<typename TMC> TMC &getTM() const {
137  return *static_cast<TMC*>(TM);
138  }
139 
140  //
141  void setInitialized() { Initialized = true; }
142 
144 
145  /// Set the StartAfter, StartBefore and StopAfter passes to allow running only
146  /// a portion of the normal code-gen pass sequence.
147  ///
148  /// If the StartAfter and StartBefore pass ID is zero, then compilation will
149  /// begin at the normal point; otherwise, clear the Started flag to indicate
150  /// that passes should not be added until the starting pass is seen. If the
151  /// Stop pass ID is zero, then compilation will continue to the end.
152  ///
153  /// This function expects that at least one of the StartAfter or the
154  /// StartBefore pass IDs is null.
155  void setStartStopPasses(AnalysisID StartBefore, AnalysisID StartAfter,
156  AnalysisID StopAfter) {
157  if (StartAfter)
158  assert(!StartBefore && "Start after and start before passes are given");
159  this->StartBefore = StartBefore;
160  this->StartAfter = StartAfter;
161  this->StopAfter = StopAfter;
162  Started = (StartAfter == nullptr) && (StartBefore == nullptr);
163  }
164 
165  void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); }
166 
167  bool getEnableTailMerge() const { return EnableTailMerge; }
168  void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); }
169 
170  /// Allow the target to override a specific pass without overriding the pass
171  /// pipeline. When passes are added to the standard pipeline at the
172  /// point where StandardID is expected, add TargetID in its place.
173  void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID);
174 
175  /// Insert InsertedPassID pass after TargetPassID pass.
176  void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID);
177 
178  /// Allow the target to enable a specific standard pass by default.
179  void enablePass(AnalysisID PassID) { substitutePass(PassID, PassID); }
180 
181  /// Allow the target to disable a specific standard pass by default.
182  void disablePass(AnalysisID PassID) {
184  }
185 
186  /// Return the pass substituted for StandardID by the target.
187  /// If no substitution exists, return StandardID.
189 
190  /// Return true if the optimized regalloc pipeline is enabled.
191  bool getOptimizeRegAlloc() const;
192 
193  /// Return true if shrink wrapping is enabled.
194  bool getEnableShrinkWrap() const;
195 
196  /// Return true if the default global register allocator is in use and
197  /// has not be overriden on the command line with '-regalloc=...'
198  bool usingDefaultRegAlloc() const;
199 
200  /// Add common target configurable passes that perform LLVM IR to IR
201  /// transforms following machine independent optimization.
202  virtual void addIRPasses();
203 
204  /// Add passes to lower exception handling for the code generator.
206 
207  /// Add pass to prepare the LLVM IR for code generation. This should be done
208  /// before exception handling preparation passes.
209  virtual void addCodeGenPrepare();
210 
211  /// Add common passes that perform LLVM IR to IR transforms in preparation for
212  /// instruction selection.
213  virtual void addISelPrepare();
214 
215  /// addInstSelector - This method should install an instruction selector pass,
216  /// which converts from LLVM code to machine instructions.
217  virtual bool addInstSelector() {
218  return true;
219  }
220 
221  /// Add the complete, standard set of LLVM CodeGen passes.
222  /// Fully developed targets will not generally override this.
223  virtual void addMachinePasses();
224 
225  /// Create an instance of ScheduleDAGInstrs to be run within the standard
226  /// MachineScheduler pass for this function and target at the current
227  /// optimization level.
228  ///
229  /// This can also be used to plug a new MachineSchedStrategy into an instance
230  /// of the standard ScheduleDAGMI:
231  /// return new ScheduleDAGMI(C, make_unique<MyStrategy>(C), /* IsPostRA= */false)
232  ///
233  /// Return NULL to select the default (generic) machine scheduler.
234  virtual ScheduleDAGInstrs *
235  createMachineScheduler(MachineSchedContext *C) const {
236  return nullptr;
237  }
238 
239  /// Similar to createMachineScheduler but used when postRA machine scheduling
240  /// is enabled.
241  virtual ScheduleDAGInstrs *
243  return nullptr;
244  }
245 
246 protected:
247  // Helper to verify the analysis is really immutable.
248  void setOpt(bool &Opt, bool Val);
249 
250  /// Methods with trivial inline returns are convenient points in the common
251  /// codegen pass pipeline where targets may insert passes. Methods with
252  /// out-of-line standard implementations are major CodeGen stages called by
253  /// addMachinePasses. Some targets may override major stages when inserting
254  /// passes is insufficient, but maintaining overriden stages is more work.
255  ///
256 
257  /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
258  /// passes (which are run just before instruction selector).
259  virtual bool addPreISel() {
260  return true;
261  }
262 
263  /// addMachineSSAOptimization - Add standard passes that optimize machine
264  /// instructions in SSA form.
265  virtual void addMachineSSAOptimization();
266 
267  /// Add passes that optimize instruction level parallelism for out-of-order
268  /// targets. These passes are run while the machine code is still in SSA
269  /// form, so they can use MachineTraceMetrics to control their heuristics.
270  ///
271  /// All passes added here should preserve the MachineDominatorTree,
272  /// MachineLoopInfo, and MachineTraceMetrics analyses.
273  virtual bool addILPOpts() {
274  return false;
275  }
276 
277  /// This method may be implemented by targets that want to run passes
278  /// immediately before register allocation.
279  virtual void addPreRegAlloc() { }
280 
281  /// createTargetRegisterAllocator - Create the register allocator pass for
282  /// this target at the current optimization level.
283  virtual FunctionPass *createTargetRegisterAllocator(bool Optimized);
284 
285  /// addFastRegAlloc - Add the minimum set of target-independent passes that
286  /// are required for fast register allocation.
287  virtual void addFastRegAlloc(FunctionPass *RegAllocPass);
288 
289  /// addOptimizedRegAlloc - Add passes related to register allocation.
290  /// LLVMTargetMachine provides standard regalloc passes for most targets.
291  virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass);
292 
293  /// addPreRewrite - Add passes to the optimized register allocation pipeline
294  /// after register allocation is complete, but before virtual registers are
295  /// rewritten to physical registers.
296  ///
297  /// These passes must preserve VirtRegMap and LiveIntervals, and when running
298  /// after RABasic or RAGreedy, they should take advantage of LiveRegMatrix.
299  /// When these passes run, VirtRegMap contains legal physreg assignments for
300  /// all virtual registers.
301  virtual bool addPreRewrite() {
302  return false;
303  }
304 
305  /// This method may be implemented by targets that want to run passes after
306  /// register allocation pass pipeline but before prolog-epilog insertion.
307  virtual void addPostRegAlloc() { }
308 
309  /// Add passes that optimize machine instructions after register allocation.
310  virtual void addMachineLateOptimization();
311 
312  /// This method may be implemented by targets that want to run passes after
313  /// prolog-epilog insertion and before the second instruction scheduling pass.
314  virtual void addPreSched2() { }
315 
316  /// addGCPasses - Add late codegen passes that analyze code for garbage
317  /// collection. This should return true if GC info should be printed after
318  /// these passes.
319  virtual bool addGCPasses();
320 
321  /// Add standard basic block placement passes.
322  virtual void addBlockPlacement();
323 
324  /// This pass may be implemented by targets that want to run passes
325  /// immediately before machine code is emitted.
326  virtual void addPreEmitPass() { }
327 
328  /// Utilities for targets to add passes to the pass manager.
329  ///
330 
331  /// Add a CodeGen pass at this point in the pipeline after checking overrides.
332  /// Return the pass that was added, or zero if no pass was added.
333  /// @p printAfter if true and adding a machine function pass add an extra
334  /// machine printer pass afterwards
335  /// @p verifyAfter if true and adding a machine function pass add an extra
336  /// machine verification pass afterwards.
337  AnalysisID addPass(AnalysisID PassID, bool verifyAfter = true,
338  bool printAfter = true);
339 
340  /// Add a pass to the PassManager if that pass is supposed to be run, as
341  /// determined by the StartAfter and StopAfter options. Takes ownership of the
342  /// pass.
343  /// @p printAfter if true and adding a machine function pass add an extra
344  /// machine printer pass afterwards
345  /// @p verifyAfter if true and adding a machine function pass add an extra
346  /// machine verification pass afterwards.
347  void addPass(Pass *P, bool verifyAfter = true, bool printAfter = true);
348 
349  /// addMachinePasses helper to create the target-selected or overriden
350  /// regalloc pass.
351  FunctionPass *createRegAllocPass(bool Optimized);
352 
353  /// printAndVerify - Add a pass to dump then verify the machine function, if
354  /// those steps are enabled.
355  ///
356  void printAndVerify(const std::string &Banner);
357 
358  /// Add a pass to print the machine function if printing is enabled.
359  void addPrintPass(const std::string &Banner);
360 
361  /// Add a pass to perform basic verification of the machine function if
362  /// verification is enabled.
363  void addVerifyPass(const std::string &Banner);
364 };
365 } // namespace llvm
366 
367 /// List of target independent CodeGen pass IDs.
368 namespace llvm {
369  FunctionPass *createAtomicExpandPass(const TargetMachine *TM);
370 
371  /// createUnreachableBlockEliminationPass - The LLVM code generator does not
372  /// work well with unreachable basic blocks (what live ranges make sense for a
373  /// block that cannot be reached?). As such, a code generator should either
374  /// not instruction select unreachable blocks, or run this pass as its
375  /// last LLVM modifying pass to clean up blocks that are not reachable from
376  /// the entry block.
378 
379  /// MachineFunctionPrinter pass - This pass prints out the machine function to
380  /// the given stream as a debugging tool.
381  MachineFunctionPass *
382  createMachineFunctionPrinterPass(raw_ostream &OS,
383  const std::string &Banner ="");
384 
385  /// MIRPrinting pass - this pass prints out the LLVM IR into the given stream
386  /// using the MIR serialization format.
387  MachineFunctionPass *createPrintMIRPass(raw_ostream &OS);
388 
389  /// createCodeGenPreparePass - Transform the code to expose more pattern
390  /// matching during instruction selection.
391  FunctionPass *createCodeGenPreparePass(const TargetMachine *TM = nullptr);
392 
393  /// AtomicExpandID -- Lowers atomic operations in terms of either cmpxchg
394  /// load-linked/store-conditional loops.
395  extern char &AtomicExpandID;
396 
397  /// MachineLoopInfo - This pass is a loop analysis pass.
398  extern char &MachineLoopInfoID;
399 
400  /// MachineDominators - This pass is a machine dominators analysis pass.
401  extern char &MachineDominatorsID;
402 
403 /// MachineDominanaceFrontier - This pass is a machine dominators analysis pass.
404  extern char &MachineDominanceFrontierID;
405 
406  /// EdgeBundles analysis - Bundle machine CFG edges.
407  extern char &EdgeBundlesID;
408 
409  /// LiveVariables pass - This pass computes the set of blocks in which each
410  /// variable is life and sets machine operand kill flags.
411  extern char &LiveVariablesID;
412 
413  /// PHIElimination - This pass eliminates machine instruction PHI nodes
414  /// by inserting copy instructions. This destroys SSA information, but is the
415  /// desired input for some register allocators. This pass is "required" by
416  /// these register allocator like this: AU.addRequiredID(PHIEliminationID);
417  extern char &PHIEliminationID;
418 
419  /// LiveIntervals - This analysis keeps track of the live ranges of virtual
420  /// and physical registers.
421  extern char &LiveIntervalsID;
422 
423  /// LiveStacks pass. An analysis keeping track of the liveness of stack slots.
424  extern char &LiveStacksID;
425 
426  /// TwoAddressInstruction - This pass reduces two-address instructions to
427  /// use two operands. This destroys SSA information but it is desired by
428  /// register allocators.
429  extern char &TwoAddressInstructionPassID;
430 
431  /// ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
432  extern char &ProcessImplicitDefsID;
433 
434  /// RegisterCoalescer - This pass merges live ranges to eliminate copies.
435  extern char &RegisterCoalescerID;
436 
437  /// MachineScheduler - This pass schedules machine instructions.
438  extern char &MachineSchedulerID;
439 
440  /// PostMachineScheduler - This pass schedules machine instructions postRA.
441  extern char &PostMachineSchedulerID;
442 
443  /// SpillPlacement analysis. Suggest optimal placement of spill code between
444  /// basic blocks.
445  extern char &SpillPlacementID;
446 
447  /// ShrinkWrap pass. Look for the best place to insert save and restore
448  // instruction and update the MachineFunctionInfo with that information.
449  extern char &ShrinkWrapID;
450 
451  /// VirtRegRewriter pass. Rewrite virtual registers to physical registers as
452  /// assigned in VirtRegMap.
453  extern char &VirtRegRewriterID;
454 
455  /// UnreachableMachineBlockElimination - This pass removes unreachable
456  /// machine basic blocks.
457  extern char &UnreachableMachineBlockElimID;
458 
459  /// DeadMachineInstructionElim - This pass removes dead machine instructions.
460  extern char &DeadMachineInstructionElimID;
461 
462  /// FastRegisterAllocation Pass - This pass register allocates as fast as
463  /// possible. It is best suited for debug code where live ranges are short.
464  ///
465  FunctionPass *createFastRegisterAllocator();
466 
467  /// BasicRegisterAllocation Pass - This pass implements a degenerate global
468  /// register allocator using the basic regalloc framework.
469  ///
470  FunctionPass *createBasicRegisterAllocator();
471 
472  /// Greedy register allocation pass - This pass implements a global register
473  /// allocator for optimized builds.
474  ///
475  FunctionPass *createGreedyRegisterAllocator();
476 
477  /// PBQPRegisterAllocation Pass - This pass implements the Partitioned Boolean
478  /// Quadratic Prograaming (PBQP) based register allocator.
479  ///
480  FunctionPass *createDefaultPBQPRegisterAllocator();
481 
482  /// PrologEpilogCodeInserter - This pass inserts prolog and epilog code,
483  /// and eliminates abstract frame references.
484  extern char &PrologEpilogCodeInserterID;
485 
486  /// ExpandPostRAPseudos - This pass expands pseudo instructions after
487  /// register allocation.
488  extern char &ExpandPostRAPseudosID;
489 
490  /// createPostRAScheduler - This pass performs post register allocation
491  /// scheduling.
492  extern char &PostRASchedulerID;
493 
494  /// BranchFolding - This pass performs machine code CFG based
495  /// optimizations to delete branches to branches, eliminate branches to
496  /// successor blocks (creating fall throughs), and eliminating branches over
497  /// branches.
498  extern char &BranchFolderPassID;
499 
500  /// MachineFunctionPrinterPass - This pass prints out MachineInstr's.
501  extern char &MachineFunctionPrinterPassID;
502 
503  /// MIRPrintingPass - this pass prints out the LLVM IR using the MIR
504  /// serialization format.
505  extern char &MIRPrintingPassID;
506 
507  /// TailDuplicate - Duplicate blocks with unconditional branches
508  /// into tails of their predecessors.
509  extern char &TailDuplicateID;
510 
511  /// MachineTraceMetrics - This pass computes critical path and CPU resource
512  /// usage in an ensemble of traces.
513  extern char &MachineTraceMetricsID;
514 
515  /// EarlyIfConverter - This pass performs if-conversion on SSA form by
516  /// inserting cmov instructions.
517  extern char &EarlyIfConverterID;
518 
519  /// This pass performs instruction combining using trace metrics to estimate
520  /// critical-path and resource depth.
521  extern char &MachineCombinerID;
522 
523  /// StackSlotColoring - This pass performs stack coloring and merging.
524  /// It merges disjoint allocas to reduce the stack size.
525  extern char &StackColoringID;
526 
527  /// IfConverter - This pass performs machine code if conversion.
528  extern char &IfConverterID;
529 
530  FunctionPass *createIfConverter(std::function<bool(const Function &)> Ftor);
531 
532  /// MachineBlockPlacement - This pass places basic blocks based on branch
533  /// probabilities.
534  extern char &MachineBlockPlacementID;
535 
536  /// MachineBlockPlacementStats - This pass collects statistics about the
537  /// basic block placement using branch probabilities and block frequency
538  /// information.
539  extern char &MachineBlockPlacementStatsID;
540 
541  /// GCLowering Pass - Used by gc.root to perform its default lowering
542  /// operations.
543  FunctionPass *createGCLoweringPass();
544 
545  /// ShadowStackGCLowering - Implements the custom lowering mechanism
546  /// used by the shadow stack GC. Only runs on functions which opt in to
547  /// the shadow stack collector.
548  FunctionPass *createShadowStackGCLoweringPass();
549 
550  /// GCMachineCodeAnalysis - Target-independent pass to mark safe points
551  /// in machine code. Must be added very late during code generation, just
552  /// prior to output, and importantly after all CFG transformations (such as
553  /// branch folding).
554  extern char &GCMachineCodeAnalysisID;
555 
556  /// Creates a pass to print GC metadata.
557  ///
558  FunctionPass *createGCInfoPrinter(raw_ostream &OS);
559 
560  /// MachineCSE - This pass performs global CSE on machine instructions.
561  extern char &MachineCSEID;
562 
563  /// ImplicitNullChecks - This pass folds null pointer checks into nearby
564  /// memory operations.
565  extern char &ImplicitNullChecksID;
566 
567  /// MachineLICM - This pass performs LICM on machine instructions.
568  extern char &MachineLICMID;
569 
570  /// MachineSinking - This pass performs sinking on machine instructions.
571  extern char &MachineSinkingID;
572 
573  /// MachineCopyPropagation - This pass performs copy propagation on
574  /// machine instructions.
575  extern char &MachineCopyPropagationID;
576 
577  /// PeepholeOptimizer - This pass performs peephole optimizations -
578  /// like extension and comparison eliminations.
579  extern char &PeepholeOptimizerID;
580 
581  /// OptimizePHIs - This pass optimizes machine instruction PHIs
582  /// to take advantage of opportunities created during DAG legalization.
583  extern char &OptimizePHIsID;
584 
585  /// StackSlotColoring - This pass performs stack slot coloring.
586  extern char &StackSlotColoringID;
587 
588  /// createStackProtectorPass - This pass adds stack protectors to functions.
589  ///
590  FunctionPass *createStackProtectorPass(const TargetMachine *TM);
591 
592  /// createMachineVerifierPass - This pass verifies cenerated machine code
593  /// instructions for correctness.
594  ///
595  FunctionPass *createMachineVerifierPass(const std::string& Banner);
596 
597  /// createDwarfEHPass - This pass mulches exception handling code into a form
598  /// adapted to code generation. Required if using dwarf exception handling.
599  FunctionPass *createDwarfEHPass(const TargetMachine *TM);
600 
601  /// createWinEHPass - Prepares personality functions used by MSVC on Windows,
602  /// in addition to the Itanium LSDA based personalities.
603  FunctionPass *createWinEHPass(const TargetMachine *TM);
604 
605  /// createSjLjEHPreparePass - This pass adapts exception handling code to use
606  /// the GCC-style builtin setjmp/longjmp (sjlj) to handling EH control flow.
607  ///
608  FunctionPass *createSjLjEHPreparePass();
609 
610  /// LocalStackSlotAllocation - This pass assigns local frame indices to stack
611  /// slots relative to one another and allocates base registers to access them
612  /// when it is estimated by the target to be out of range of normal frame
613  /// pointer or stack pointer index addressing.
614  extern char &LocalStackSlotAllocationID;
615 
616  /// ExpandISelPseudos - This pass expands pseudo-instructions.
617  extern char &ExpandISelPseudosID;
618 
619  /// createExecutionDependencyFixPass - This pass fixes execution time
620  /// problems with dependent instructions, such as switching execution
621  /// domains to match.
622  ///
623  /// The pass will examine instructions using and defining registers in RC.
624  ///
625  FunctionPass *createExecutionDependencyFixPass(const TargetRegisterClass *RC);
626 
627  /// UnpackMachineBundles - This pass unpack machine instruction bundles.
628  extern char &UnpackMachineBundlesID;
629 
630  FunctionPass *
631  createUnpackMachineBundles(std::function<bool(const Function &)> Ftor);
632 
633  /// FinalizeMachineBundles - This pass finalize machine instruction
634  /// bundles (created earlier, e.g. during pre-RA scheduling).
635  extern char &FinalizeMachineBundlesID;
636 
637  /// StackMapLiveness - This pass analyses the register live-out set of
638  /// stackmap/patchpoint intrinsics and attaches the calculated information to
639  /// the intrinsic for later emission to the StackMap.
640  extern char &StackMapLivenessID;
641 
642  /// createJumpInstrTables - This pass creates jump-instruction tables.
643  ModulePass *createJumpInstrTablesPass();
644 
645  /// createForwardControlFlowIntegrityPass - This pass adds control-flow
646  /// integrity.
648 
649  /// InterleavedAccess Pass - This pass identifies and matches interleaved
650  /// memory accesses to target specific intrinsics.
651  ///
652  FunctionPass *createInterleavedAccessPass(const TargetMachine *TM);
653 } // End llvm namespace
654 
655 /// Target machine pass initializer for passes with dependencies. Use with
656 /// INITIALIZE_TM_PASS_END.
657 #define INITIALIZE_TM_PASS_BEGIN INITIALIZE_PASS_BEGIN
658 
659 /// Target machine pass initializer for passes with dependencies. Use with
660 /// INITIALIZE_TM_PASS_BEGIN.
661 #define INITIALIZE_TM_PASS_END(passName, arg, name, cfg, analysis) \
662  PassInfo *PI = new PassInfo(name, arg, & passName ::ID, \
663  PassInfo::NormalCtor_t(callDefaultCtor< passName >), cfg, analysis, \
664  PassInfo::TargetMachineCtor_t(callTargetMachineCtor< passName >)); \
665  Registry.registerPass(*PI, true); \
666  return PI; \
667  } \
668  void llvm::initialize##passName##Pass(PassRegistry &Registry) { \
669  CALL_ONCE_INITIALIZATION(initialize##passName##PassOnce) \
670  }
671 
672 /// This initializer registers TargetMachine constructor, so the pass being
673 /// initialized can use target dependent interfaces. Please do not move this
674 /// macro to be together with INITIALIZE_PASS, which is a complete target
675 /// independent initializer, and we don't want to make libScalarOpts depend
676 /// on libCodeGen.
677 #define INITIALIZE_TM_PASS(passName, arg, name, cfg, analysis) \
678  INITIALIZE_TM_PASS_BEGIN(passName, arg, name, cfg, analysis) \
679  INITIALIZE_TM_PASS_END(passName, arg, name, cfg, analysis)
680 
681 #endif
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:82
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
void enablePass(AnalysisID PassID)
Allow the target to enable a specific standard pass by default.
void setStartStopPasses(AnalysisID StartBefore, AnalysisID StartAfter, AnalysisID StopAfter)
Set the StartAfter, StartBefore and StopAfter passes to allow running only a portion of the normal co...
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: Passes.cpp:377
void setDisableVerify(bool Disable)
char & MachineLICMID
MachineLICM - This pass performs LICM on machine instructions.
char & MachineDominatorsID
MachineDominators - This pass is a machine dominators analysis pass.
virtual bool addPreRewrite()
addPreRewrite - Add passes to the optimized register allocation pipeline after register allocation is...
char & RegisterCoalescerID
RegisterCoalescer - This pass merges live ranges to eliminate copies.
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions...
FunctionPass * createInterleavedAccessPass(const TargetMachine *TM)
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
FunctionPass * createWinEHPass(const TargetMachine *TM)
createWinEHPass - Prepares personality functions used by MSVC on Windows, in addition to the Itanium ...
static const bool value
Definition: type_traits.h:46
char & MachineSchedulerID
MachineScheduler - This pass schedules machine instructions.
char & AtomicExpandID
AtomicExpandID – Lowers atomic operations in terms of either cmpxchg load-linked/store-conditional lo...
char & ProcessImplicitDefsID
ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form...
Definition: Passes.cpp:585
char & MachineBlockPlacementStatsID
MachineBlockPlacementStats - This pass collects statistics about the basic block placement using bran...
bool getEnableShrinkWrap() const
Return true if shrink wrapping is enabled.
Definition: Passes.cpp:622
FunctionPass * createShadowStackGCLoweringPass()
ShadowStackGCLowering - Implements the custom lowering mechanism used by the shadow stack GC...
char & MachineFunctionPrinterPassID
MachineFunctionPrinterPass - This pass prints out MachineInstr's.
virtual void addPreEmitPass()
This pass may be implemented by targets that want to run passes immediately before machine code is em...
Pass * getInstance() const
FunctionPass * createMachineVerifierPass(const std::string &Banner)
createMachineVerifierPass - This pass verifies cenerated machine code instructions for correctness...
void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID)
Insert InsertedPassID pass after TargetPassID pass.
Definition: Passes.cpp:234
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
TMC & getTM() const
Get the right type of TargetMachine for this target.
FunctionPass * createGCLoweringPass()
GCLowering Pass - Used by gc.root to perform its default lowering operations.
bool getOptimizeRegAlloc() const
Return true if the optimized regalloc pipeline is enabled.
Definition: Passes.cpp:641
char & StackColoringID
StackSlotColoring - This pass performs stack coloring and merging.
IdentifyingPassPtr(Pass *InstancePtr)
FunctionPass * createAtomicExpandPass(const TargetMachine *TM)
virtual void addPreSched2()
This method may be implemented by targets that want to run passes after prolog-epilog insertion and b...
FunctionPass * createRegAllocPass(bool Optimized)
addMachinePasses helper to create the target-selected or overriden regalloc pass. ...
Definition: Passes.cpp:693
char & FinalizeMachineBundlesID
FinalizeMachineBundles - This pass finalize machine instruction bundles (created earlier, e.g.
#define false
Definition: ConvertUTF.c:65
Target-Independent Code Generator Pass Configuration Options.
CodeGenOpt::Level getOptLevel() const
char & UnreachableMachineBlockElimID
UnreachableMachineBlockElimination - This pass removes unreachable machine basic blocks.
virtual void addMachinePasses()
Add the complete, standard set of LLVM CodeGen passes.
Definition: Passes.cpp:495
IdentifyingPassPtr getPassSubstitution(AnalysisID StandardID) const
Return the pass substituted for StandardID by the target.
Definition: Passes.cpp:269
char & MachineCSEID
MachineCSE - This pass performs global CSE on machine instructions.
Definition: MachineCSE.cpp:110
char & StackSlotColoringID
StackSlotColoring - This pass performs stack slot coloring.
virtual void addPreRegAlloc()
This method may be implemented by targets that want to run passes immediately before register allocat...
FunctionPass * createIfConverter(std::function< bool(const Function &)> Ftor)
char & ExpandPostRAPseudosID
ExpandPostRAPseudos - This pass expands pseudo instructions after register allocation.
char & ExpandISelPseudosID
ExpandISelPseudos - This pass expands pseudo-instructions.
char & DeadMachineInstructionElimID
DeadMachineInstructionElim - This pass removes dead machine instructions.
void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID)
Allow the target to override a specific pass without overriding the pass pipeline.
Definition: Passes.cpp:264
FunctionPass * createUnreachableBlockEliminationPass()
createUnreachableBlockEliminationPass - The LLVM code generator does not work well with unreachable b...
char & LiveIntervalsID
LiveIntervals - This analysis keeps track of the live ranges of virtual and physical registers...
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
virtual bool addILPOpts()
Add passes that optimize instruction level parallelism for out-of-order targets.
FunctionPass * createGCInfoPrinter(raw_ostream &OS)
Creates a pass to print GC metadata.
Definition: GCMetadata.cpp:86
FunctionPass * createCodeGenPreparePass(const TargetMachine *TM=nullptr)
createCodeGenPreparePass - Transform the code to expose more pattern matching during instruction sele...
char & PHIEliminationID
PHIElimination - This pass eliminates machine instruction PHI nodes by inserting copy instructions...
char & LiveVariablesID
LiveVariables pass - This pass computes the set of blocks in which each variable is life and sets mac...
virtual FunctionPass * createTargetRegisterAllocator(bool Optimized)
createTargetRegisterAllocator - Create the register allocator pass for this target at the current opt...
Definition: Passes.cpp:677
virtual bool addGCPasses()
addGCPasses - Add late codegen passes that analyze code for garbage collection.
Definition: Passes.cpp:793
#define P(N)
#define true
Definition: ConvertUTF.c:66
ModulePass * createForwardControlFlowIntegrityPass()
createForwardControlFlowIntegrityPass - This pass adds control-flow integrity.
static char PostRAMachineLICMID
PostRAMachineLICM - A clone of the LICM pass that runs during late machine optimization after regallo...
void printAndVerify(const std::string &Banner)
printAndVerify - Add a pass to dump then verify the machine function, if those steps are enabled...
Definition: Passes.cpp:360
void disablePass(AnalysisID PassID)
Allow the target to disable a specific standard pass by default.
char & LiveStacksID
LiveStacks pass. An analysis keeping track of the liveness of stack slots.
virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass)
addOptimizedRegAlloc - Add passes related to register allocation.
Definition: Passes.cpp:726
void setEnableTailMerge(bool Enable)
virtual void addMachineLateOptimization()
Add passes that optimize machine instructions after register allocation.
Definition: Passes.cpp:777
FunctionPass * createUnpackMachineBundles(std::function< bool(const Function &)> Ftor)
virtual bool addInstSelector()
addInstSelector - This method should install an instruction selector pass, which converts from LLVM c...
FunctionPass * createDefaultPBQPRegisterAllocator()
PBQPRegisterAllocation Pass - This pass implements the Partitioned Boolean Quadratic Prograaming (PBQ...
virtual bool addPreISel()
Methods with trivial inline returns are convenient points in the common codegen pass pipeline where t...
bool getEnableTailMerge() const
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:294
virtual void addISelPrepare()
Add common passes that perform LLVM IR to IR transforms in preparation for instruction selection...
Definition: Passes.cpp:459
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
Definition: Passes.cpp:451
char & MIRPrintingPassID
MIRPrintingPass - this pass prints out the LLVM IR using the MIR serialization format.
char & UnpackMachineBundlesID
UnpackMachineBundles - This pass unpack machine instruction bundles.
char & MachineCopyPropagationID
MachineCopyPropagation - This pass performs copy propagation on machine instructions.
void addPrintPass(const std::string &Banner)
Add a pass to print the machine function if printing is enabled.
Definition: Passes.cpp:365
char & ImplicitNullChecksID
ImplicitNullChecks - This pass folds null pointer checks into nearby memory operations.
void addPassesToHandleExceptions()
Add passes to lower exception handling for the code generator.
Definition: Passes.cpp:418
char & PostRASchedulerID
createPostRAScheduler - This pass performs post register allocation scheduling.
isPodLike - This is a type trait that is used to determine whether a given type can be copied around ...
Definition: ArrayRef.h:365
FunctionPass * createStackProtectorPass(const TargetMachine *TM)
createStackProtectorPass - This pass adds stack protectors to functions.
ImmutablePass class - This class is used to provide information that does not need to be run...
Definition: Pass.h:262
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
char & StackMapLivenessID
StackMapLiveness - This pass analyses the register live-out set of stackmap/patchpoint intrinsics and...
FunctionPass * createExecutionDependencyFixPass(const TargetRegisterClass *RC)
createExecutionDependencyFixPass - This pass fixes execution time problems with dependent instruction...
char & TailDuplicateID
TailDuplicate - Duplicate blocks with unconditional branches into tails of their predecessors.
char & MachineSinkingID
MachineSinking - This pass performs sinking on machine instructions.
FunctionPass * createBasicRegisterAllocator()
BasicRegisterAllocation Pass - This pass implements a degenerate global register allocator using the ...
~TargetPassConfig() override
Definition: Passes.cpp:210
MachineFunctionPass * createMachineFunctionPrinterPass(raw_ostream &OS, const std::string &Banner="")
MachineFunctionPrinter pass - This pass prints out the machine function to the given stream as a debu...
char & MachineTraceMetricsID
MachineTraceMetrics - This pass computes critical path and CPU resource usage in an ensemble of trace...
char & OptimizePHIsID
OptimizePHIs - This pass optimizes machine instruction PHIs to take advantage of opportunities create...
char & MachineDominanceFrontierID
MachineDominanaceFrontier - This pass is a machine dominators analysis pass.
virtual void addPostRegAlloc()
This method may be implemented by targets that want to run passes after register allocation pass pipe...
char & PeepholeOptimizerID
PeepholeOptimizer - This pass performs peephole optimizations - like extension and comparison elimina...
Discriminated union of Pass ID types.
bool EnableShrinkWrap
Default setting for -enable-shrink-wrap on this target.
virtual void addFastRegAlloc(FunctionPass *RegAllocPass)
addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast registe...
Definition: Passes.cpp:716
char & PrologEpilogCodeInserterID
PrologEpilogCodeInserter - This pass inserts prolog and epilog code, and eliminates abstract frame re...
virtual ScheduleDAGInstrs * createPostMachineScheduler(MachineSchedContext *C) const
Similar to createMachineScheduler but used when postRA machine scheduling is enabled.
ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of MachineInstrs. ...
char & GCMachineCodeAnalysisID
GCMachineCodeAnalysis - Target-independent pass to mark safe points in machine code.
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
AnalysisID addPass(AnalysisID PassID, bool verifyAfter=true, bool printAfter=true)
Utilities for targets to add passes to the pass manager.
Definition: Passes.cpp:339
FunctionPass * createDwarfEHPass(const TargetMachine *TM)
createDwarfEHPass - This pass mulches exception handling code into a form adapted to code generation...
char & IfConverterID
IfConverter - This pass performs machine code if conversion.
virtual void addBlockPlacement()
Add standard basic block placement passes.
Definition: Passes.cpp:799
FunctionPass * createGreedyRegisterAllocator()
Greedy register allocation pass - This pass implements a global register allocator for optimized buil...
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
AnalysisID getID() const
char & MachineBlockPlacementID
MachineBlockPlacement - This pass places basic blocks based on branch probabilities.
char & SpillPlacementID
SpillPlacement analysis.
void setOpt(bool &Opt, bool Val)
Definition: Passes.cpp:259
const void * AnalysisID
Definition: Pass.h:47
char & EdgeBundlesID
EdgeBundles analysis - Bundle machine CFG edges.
char & TwoAddressInstructionPassID
TwoAddressInstruction - This pass reduces two-address instructions to use two operands.
void addVerifyPass(const std::string &Banner)
Add a pass to perform basic verification of the machine function if verification is enabled...
Definition: Passes.cpp:370
FunctionPass * createSjLjEHPreparePass()
createSjLjEHPreparePass - This pass adapts exception handling code to use the GCC-style builtin setjm...
static char EarlyTailDuplicateID
Pseudo Pass IDs.
FunctionPass * createFastRegisterAllocator()
FastRegisterAllocation Pass - This pass register allocates as fast as possible.
IdentifyingPassPtr(AnalysisID IDPtr)
char & VirtRegRewriterID
VirtRegRewriter pass.
Definition: VirtRegMap.cpp:181
char & BranchFolderPassID
BranchFolding - This pass performs machine code CFG based optimizations to delete branches to branche...
Primary interface to the complete machine description for the target machine.
print Print MemDeps of function
char & ShrinkWrapID
ShrinkWrap pass. Look for the best place to insert save and restore.
Definition: ShrinkWrap.cpp:178
bool usingDefaultRegAlloc() const
Return true if the default global register allocator is in use and has not be overriden on the comman...
Definition: Passes.cpp:710
char & LocalStackSlotAllocationID
LocalStackSlotAllocation - This pass assigns local frame indices to stack slots relative to one anoth...
MachineFunctionPass * createPrintMIRPass(raw_ostream &OS)
MIRPrinting pass - this pass prints out the LLVM IR into the given stream using the MIR serialization...
bool EnableTailMerge
Default setting for -enable-tail-merge on this target.
PassConfigImpl * Impl
ModulePass * createJumpInstrTablesPass()
createJumpInstrTables - This pass creates jump-instruction tables.