LLVM  3.7.0
SIPrepareScratchRegs.cpp
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1 //===-- SIPrepareScratchRegs.cpp - Use predicates for control flow --------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 ///
12 /// This pass loads scratch pointer and scratch offset into a register or a
13 /// frame index which can be used anywhere in the program. These values will
14 /// be used for spilling VGPRs.
15 ///
16 //===----------------------------------------------------------------------===//
17 
18 #include "AMDGPU.h"
19 #include "AMDGPUSubtarget.h"
20 #include "SIDefines.h"
21 #include "SIInstrInfo.h"
22 #include "SIMachineFunctionInfo.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/LLVMContext.h"
31 
32 using namespace llvm;
33 
34 namespace {
35 
36 class SIPrepareScratchRegs : public MachineFunctionPass {
37 
38 private:
39  static char ID;
40 
41 public:
42  SIPrepareScratchRegs() : MachineFunctionPass(ID) { }
43 
44  bool runOnMachineFunction(MachineFunction &MF) override;
45 
46  const char *getPassName() const override {
47  return "SI prepare scratch registers";
48  }
49 
50 };
51 
52 } // End anonymous namespace
53 
55 
57  return new SIPrepareScratchRegs();
58 }
59 
60 bool SIPrepareScratchRegs::runOnMachineFunction(MachineFunction &MF) {
62  const SIInstrInfo *TII =
63  static_cast<const SIInstrInfo *>(MF.getSubtarget().getInstrInfo());
64  const SIRegisterInfo *TRI = &TII->getRegisterInfo();
65  MachineRegisterInfo &MRI = MF.getRegInfo();
66  MachineFrameInfo *FrameInfo = MF.getFrameInfo();
67  MachineBasicBlock *Entry = MF.begin();
69  DebugLoc DL = I->getDebugLoc();
70 
71  // FIXME: If we don't have enough VGPRs for SGPR spilling we will need to
72  // run this pass.
73  if (!MFI->hasSpilledVGPRs())
74  return false;
75 
76  unsigned ScratchPtrPreloadReg =
78  unsigned ScratchOffsetPreloadReg =
80 
81  if (!Entry->isLiveIn(ScratchPtrPreloadReg))
82  Entry->addLiveIn(ScratchPtrPreloadReg);
83 
84  if (!Entry->isLiveIn(ScratchOffsetPreloadReg))
85  Entry->addLiveIn(ScratchOffsetPreloadReg);
86 
87  // Load the scratch offset.
88  unsigned ScratchOffsetReg =
89  TRI->findUnusedRegister(MRI, &AMDGPU::SGPR_32RegClass);
90  int ScratchOffsetFI = -1;
91 
92  if (ScratchOffsetReg != AMDGPU::NoRegister) {
93  // Found an SGPR to use
94  MRI.setPhysRegUsed(ScratchOffsetReg);
95  BuildMI(*Entry, I, DL, TII->get(AMDGPU::S_MOV_B32), ScratchOffsetReg)
96  .addReg(ScratchOffsetPreloadReg);
97  } else {
98  // No SGPR is available, we must spill.
99  ScratchOffsetFI = FrameInfo->CreateSpillStackObject(4,4);
100  BuildMI(*Entry, I, DL, TII->get(AMDGPU::SI_SPILL_S32_SAVE))
101  .addReg(ScratchOffsetPreloadReg)
102  .addFrameIndex(ScratchOffsetFI)
103  .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef)
104  .addReg(AMDGPU::SGPR0, RegState::Undef);
105  }
106 
107 
108  // Now that we have the scratch pointer and offset values, we need to
109  // add them to all the SI_SPILL_V* instructions.
110 
111  RegScavenger RS;
112  unsigned ScratchRsrcFI = FrameInfo->CreateSpillStackObject(16, 4);
113  RS.addScavengingFrameIndex(ScratchRsrcFI);
114 
115  for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
116  BI != BE; ++BI) {
117 
118  MachineBasicBlock &MBB = *BI;
119  // Add the scratch offset reg as a live-in so that the register scavenger
120  // doesn't re-use it.
121  if (!MBB.isLiveIn(ScratchOffsetReg) &&
122  ScratchOffsetReg != AMDGPU::NoRegister)
123  MBB.addLiveIn(ScratchOffsetReg);
124  RS.enterBasicBlock(&MBB);
125 
126  for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
127  I != E; ++I) {
128  MachineInstr &MI = *I;
129  RS.forward(I);
130  DebugLoc DL = MI.getDebugLoc();
131  if (!TII->isVGPRSpill(MI.getOpcode()))
132  continue;
133 
134  // Scratch resource
135  unsigned ScratchRsrcReg =
136  RS.scavengeRegister(&AMDGPU::SReg_128RegClass, 0);
137 
139  0xffffffff; // Size
140 
141  unsigned Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0);
142  unsigned Rsrc1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1);
143  unsigned Rsrc2 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2);
144  unsigned Rsrc3 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3);
145 
146  BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), Rsrc0)
147  .addExternalSymbol("SCRATCH_RSRC_DWORD0")
148  .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
149 
150  BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), Rsrc1)
151  .addExternalSymbol("SCRATCH_RSRC_DWORD1")
152  .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
153 
154  BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), Rsrc2)
155  .addImm(Rsrc & 0xffffffff)
156  .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
157 
158  BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), Rsrc3)
159  .addImm(Rsrc >> 32)
160  .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
161 
162  // Scratch Offset
163  if (ScratchOffsetReg == AMDGPU::NoRegister) {
164  ScratchOffsetReg = RS.scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
165  BuildMI(MBB, I, DL, TII->get(AMDGPU::SI_SPILL_S32_RESTORE),
166  ScratchOffsetReg)
167  .addFrameIndex(ScratchOffsetFI)
168  .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef)
169  .addReg(AMDGPU::SGPR0, RegState::Undef);
170  } else if (!MBB.isLiveIn(ScratchOffsetReg)) {
171  MBB.addLiveIn(ScratchOffsetReg);
172  }
173 
174  if (ScratchRsrcReg == AMDGPU::NoRegister ||
175  ScratchOffsetReg == AMDGPU::NoRegister) {
176  LLVMContext &Ctx = MF.getFunction()->getContext();
177  Ctx.emitError("ran out of SGPRs for spilling VGPRs");
178  ScratchRsrcReg = AMDGPU::SGPR0;
179  ScratchOffsetReg = AMDGPU::SGPR0;
180  }
181  MI.getOperand(2).setReg(ScratchRsrcReg);
182  MI.getOperand(2).setIsKill(true);
183  MI.getOperand(2).setIsUndef(false);
184  MI.getOperand(3).setReg(ScratchOffsetReg);
185  MI.getOperand(3).setIsUndef(false);
186  MI.getOperand(3).setIsKill(false);
187  MI.addOperand(MachineOperand::CreateReg(Rsrc0, false, true, true));
188  MI.addOperand(MachineOperand::CreateReg(Rsrc1, false, true, true));
189  MI.addOperand(MachineOperand::CreateReg(Rsrc2, false, true, true));
190  MI.addOperand(MachineOperand::CreateReg(Rsrc3, false, true, true));
191  }
192  }
193  return true;
194 }
void setPhysRegUsed(unsigned Reg)
setPhysRegUsed - Mark the specified register used in this function.
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:223
AMDGPU specific subclass of TargetSubtarget.
void setIsUndef(bool Val=true)
void addLiveIn(unsigned Reg)
Adds the specified register as a live in.
A debug info location.
Definition: DebugLoc.h:34
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false)
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
void emitError(unsigned LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
void forward()
Move the internal MBB iterator and update register states.
const uint64_t RSRC_DATA_FORMAT
Definition: SIInstrInfo.h:369
void enterBasicBlock(MachineBasicBlock *mbb)
Start tracking liveness from the begin of the specific basic block.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:267
bundle_iterator< MachineInstr, instr_iterator > iterator
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:41
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
unsigned getPreloadedValue(const MachineFunction &MF, enum PreloadedValue Value) const
Returns the physical register that Value is stored in.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:294
unsigned findUnusedRegister(const MachineRegisterInfo &MRI, const TargetRegisterClass *RC) const
Returns a register that is not used at any point in the function.
FunctionPass * createSIPrepareScratchRegs()
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
int CreateSpillStackObject(uint64_t Size, unsigned Alignment)
Create a new statically sized stack object that represents a spill slot, returning a nonnegative iden...
void setIsKill(bool Val=true)
const uint64_t RSRC_TID_ENABLE
Definition: SIInstrInfo.h:370
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const MachineInstrBuilder & addFrameIndex(int Idx) const
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:238
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)
Definition: Metadata.h:1030
Representation of each machine instruction.
Definition: MachineInstr.h:51
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
Interface definition for SIInstrInfo.
bool isLiveIn(unsigned Reg) const
isLiveIn - Return true if the specified register is in the live in set.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
void setReg(unsigned Reg)
Change the register this operand corresponds to.
#define I(x, y, z)
Definition: MD5.cpp:54
virtual const TargetInstrInfo * getInstrInfo() const
BasicBlockListType::iterator iterator
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
unsigned scavengeRegister(const TargetRegisterClass *RegClass, MachineBasicBlock::iterator I, int SPAdj)
Make a register of the specific register class available and do the appropriate bookkeeping.