LLVM  3.7.0
Thumb1InstrInfo.cpp
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1 //===-- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Thumb-1 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMSubtarget.h"
15 #include "Thumb1InstrInfo.h"
20 #include "llvm/MC/MCInst.h"
21 
22 using namespace llvm;
23 
25  : ARMBaseInstrInfo(STI), RI() {}
26 
27 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
29  NopInst.setOpcode(ARM::tMOVr);
30  NopInst.addOperand(MCOperand::createReg(ARM::R8));
31  NopInst.addOperand(MCOperand::createReg(ARM::R8));
33  NopInst.addOperand(MCOperand::createReg(0));
34 }
35 
36 unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
37  return 0;
38 }
39 
42  unsigned DestReg, unsigned SrcReg,
43  bool KillSrc) const {
44  // Need to check the arch.
45  MachineFunction &MF = *MBB.getParent();
46  const ARMSubtarget &st = MF.getSubtarget<ARMSubtarget>();
47 
48  assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
49  "Thumb1 can only copy GPR registers");
50 
51  if (st.hasV6Ops() || ARM::hGPRRegClass.contains(SrcReg)
52  || !ARM::tGPRRegClass.contains(DestReg))
53  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
54  .addReg(SrcReg, getKillRegState(KillSrc)));
55  else {
56  // FIXME: The performance consequences of this are going to be atrocious.
57  // Some things to try that should be better:
58  // * 'mov hi, $src; mov $dst, hi', with hi as either r10 or r11
59  // * 'movs $dst, $src' if cpsr isn't live
60  // See: http://lists.llvm.org/pipermail/llvm-dev/2014-August/075998.html
61 
62  // 'MOV lo, lo' is unpredictable on < v6, so use the stack to do it
63  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tPUSH)))
64  .addReg(SrcReg, getKillRegState(KillSrc));
65  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tPOP)))
66  .addReg(DestReg, getDefRegState(true));
67  }
68 }
69 
72  unsigned SrcReg, bool isKill, int FI,
73  const TargetRegisterClass *RC,
74  const TargetRegisterInfo *TRI) const {
75  assert((RC == &ARM::tGPRRegClass ||
77  isARMLowRegister(SrcReg))) && "Unknown regclass!");
78 
79  if (RC == &ARM::tGPRRegClass ||
81  isARMLowRegister(SrcReg))) {
82  DebugLoc DL;
83  if (I != MBB.end()) DL = I->getDebugLoc();
84 
85  MachineFunction &MF = *MBB.getParent();
86  MachineFrameInfo &MFI = *MF.getFrameInfo();
87  MachineMemOperand *MMO =
90  MFI.getObjectSize(FI),
91  MFI.getObjectAlignment(FI));
92  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSTRspi))
93  .addReg(SrcReg, getKillRegState(isKill))
94  .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
95  }
96 }
97 
100  unsigned DestReg, int FI,
101  const TargetRegisterClass *RC,
102  const TargetRegisterInfo *TRI) const {
103  assert((RC == &ARM::tGPRRegClass ||
105  isARMLowRegister(DestReg))) && "Unknown regclass!");
106 
107  if (RC == &ARM::tGPRRegClass ||
109  isARMLowRegister(DestReg))) {
110  DebugLoc DL;
111  if (I != MBB.end()) DL = I->getDebugLoc();
112 
113  MachineFunction &MF = *MBB.getParent();
114  MachineFrameInfo &MFI = *MF.getFrameInfo();
115  MachineMemOperand *MMO =
118  MFI.getObjectSize(FI),
119  MFI.getObjectAlignment(FI));
120  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg)
121  .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
122  }
123 }
124 
125 void
126 Thumb1InstrInfo::expandLoadStackGuard(MachineBasicBlock::iterator MI,
127  Reloc::Model RM) const {
128  if (RM == Reloc::PIC_)
129  expandLoadStackGuardBase(MI, ARM::tLDRLIT_ga_pcrel, ARM::tLDRi, RM);
130  else
131  expandLoadStackGuardBase(MI, ARM::tLDRLIT_ga_abs, ARM::tLDRi, RM);
132 }
The memory access reads data.
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
The memory access writes data.
unsigned getUnindexedOpcode(unsigned Opc) const override
bool hasV6Ops() const
Definition: ARMSubtarget.h:293
A debug info location.
Definition: DebugLoc.h:34
void getNoopForMachoTarget(MCInst &NopInst) const override
getNoopForMachoTarget - Return the noop instruction to use for a noop.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, unsigned f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
getMachineMemOperand - Allocate a new MachineMemOperand.
static MachinePointerInfo getFixedStack(int FI, int64_t offset=0)
getFixedStack - Return a MachinePointerInfo record that refers to the the specified FrameIndex...
MachineMemOperand - A description of a memory reference used in the backend.
static const MachineInstrBuilder & AddDefaultPred(const MachineInstrBuilder &MIB)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:111
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Definition: Value.cpp:317
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:150
unsigned getKillRegState(bool B)
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
unsigned getDefRegState(bool B)
bundle_iterator< MachineInstr, instr_iterator > iterator
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void setOpcode(unsigned Op)
Definition: MCInst.h:158
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static bool isARMLowRegister(unsigned Reg)
isARMLowRegister - Returns true if the register is a low register (r0-r7).
Definition: ARMBaseInfo.h:210
static bool isPhysicalRegister(unsigned Reg)
isPhysicalRegister - Return true if the specified register number is in the physical register namespa...
Thumb1InstrInfo(const ARMSubtarget &STI)
#define I(x, y, z)
Definition: MD5.cpp:54
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
void addOperand(const MCOperand &Op)
Definition: MCInst.h:168
void expandLoadStackGuardBase(MachineBasicBlock::iterator MI, unsigned LoadImmOpc, unsigned LoadOpc, Reloc::Model RM) const
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:117
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.