LLVM  3.7.0
Public Member Functions | Protected Types | Protected Member Functions | Protected Attributes | List of all members
llvm::ScheduleDAGInstrs Class Referenceabstract

ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of MachineInstrs. More...

#include <ScheduleDAGInstrs.h>

Inheritance diagram for llvm::ScheduleDAGInstrs:
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Collaboration diagram for llvm::ScheduleDAGInstrs:
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Public Member Functions

 ScheduleDAGInstrs (MachineFunction &mf, const MachineLoopInfo *mli, bool IsPostRAFlag, bool RemoveKillFlags=false, LiveIntervals *LIS=nullptr)
 
 ~ScheduleDAGInstrs () override
 
bool isPostRA () const
 
LiveIntervalsgetLIS () const
 Expose LiveIntervals for use in DAG mutators and such. More...
 
const TargetSchedModelgetSchedModel () const
 Get the machine model for instruction scheduling. More...
 
const MCSchedClassDescgetSchedClass (SUnit *SU) const
 Resolve and cache a resolved scheduling class for an SUnit. More...
 
MachineBasicBlock::iterator begin () const
 begin - Return an iterator to the top of the current scheduling region. More...
 
MachineBasicBlock::iterator end () const
 end - Return an iterator to the bottom of the current scheduling region. More...
 
SUnitnewSUnit (MachineInstr *MI)
 newSUnit - Creates a new SUnit and return a ptr to it. More...
 
SUnitgetSUnit (MachineInstr *MI) const
 getSUnit - Return an existing SUnit for this MI, or NULL. More...
 
virtual void startBlock (MachineBasicBlock *BB)
 startBlock - Prepare to perform scheduling in the given block. More...
 
virtual void finishBlock ()
 finishBlock - Clean up after scheduling in the given block. More...
 
virtual void enterRegion (MachineBasicBlock *bb, MachineBasicBlock::iterator begin, MachineBasicBlock::iterator end, unsigned regioninstrs)
 Initialize the scheduler state for the next scheduling region. More...
 
virtual void exitRegion ()
 Notify that the scheduler has finished scheduling the current region. More...
 
void buildSchedGraph (AliasAnalysis *AA, RegPressureTracker *RPTracker=nullptr, PressureDiffs *PDiffs=nullptr)
 buildSchedGraph - Build SUnits from the MachineBasicBlock that we are input. More...
 
void addSchedBarrierDeps ()
 addSchedBarrierDeps - Add dependencies from instructions in the current list of instructions being scheduled to scheduling barrier. More...
 
virtual void schedule ()=0
 schedule - Order nodes according to selected style, filling in the Sequence member. More...
 
virtual void finalizeSchedule ()
 finalizeSchedule - Allow targets to perform final scheduling actions at the level of the whole MachineFunction. More...
 
void dumpNode (const SUnit *SU) const override
 
std::string getGraphNodeLabel (const SUnit *SU) const override
 Return a label for a DAG node that points to an instruction. More...
 
std::string getDAGName () const override
 Return a label for the region of code covered by the DAG. More...
 
void fixupKills (MachineBasicBlock *MBB)
 Fix register kill flags that scheduling has made invalid. More...
 
- Public Member Functions inherited from llvm::ScheduleDAG
 ScheduleDAG (MachineFunction &mf)
 
virtual ~ScheduleDAG ()
 
void clearDAG ()
 clearDAG - clear the DAG state (between regions). More...
 
const MCInstrDescgetInstrDesc (const SUnit *SU) const
 getInstrDesc - Return the MCInstrDesc of this SUnit. More...
 
virtual void viewGraph (const Twine &Name, const Twine &Title)
 viewGraph - Pop up a GraphViz/gv window with the ScheduleDAG rendered using 'dot'. More...
 
virtual void viewGraph ()
 Out-of-line implementation with no arguments is handy for gdb. More...
 
virtual void addCustomGraphFeatures (GraphWriter< ScheduleDAG * > &) const
 addCustomGraphFeatures - Add custom features for a visualization of the ScheduleDAG. More...
 
unsigned VerifyScheduledDAG (bool isBottomUp)
 VerifyScheduledDAG - Verify that all SUnits were scheduled and that their state is consistent. More...
 

Protected Types

typedef std::vector< std::pair
< MachineInstr *, MachineInstr * > > 
DbgValueVector
 DbgValues - Remember instruction that precedes DBG_VALUE. More...
 

Protected Member Functions

void initSUnits ()
 Create an SUnit for each real instruction, numbered in top-down toplological order. More...
 
void addPhysRegDataDeps (SUnit *SU, unsigned OperIdx)
 MO is an operand of SU's instruction that defines a physical register. More...
 
void addPhysRegDeps (SUnit *SU, unsigned OperIdx)
 addPhysRegDeps - Add register dependencies (data, anti, and output) from this SUnit to following instructions in the same scheduling region that depend the physical register referenced at OperIdx. More...
 
void addVRegDefDeps (SUnit *SU, unsigned OperIdx)
 addVRegDefDeps - Add register output and data dependencies from this SUnit to instructions that occur later in the same scheduling region if they read from or write to the virtual register defined at OperIdx. More...
 
void addVRegUseDeps (SUnit *SU, unsigned OperIdx)
 addVRegUseDeps - Add a register data dependency if the instruction that defines the virtual register used at OperIdx is mapped to an SUnit. More...
 
void startBlockForKills (MachineBasicBlock *BB)
 PostRA helper for rewriting kill flags. More...
 
bool toggleKillFlag (MachineInstr *MI, MachineOperand &MO)
 Toggle a register operand kill flag. More...
 

Protected Attributes

const MachineLoopInfoMLI
 
const MachineFrameInfoMFI
 
LiveIntervalsLIS
 Live Intervals provides reaching defs in preRA scheduling. More...
 
TargetSchedModel SchedModel
 TargetSchedModel provides an interface to the machine model. More...
 
bool IsPostRA
 isPostRA flag indicates vregs cannot be present. More...
 
bool RemoveKillFlags
 True if the DAG builder should remove kill flags (in preparation for rescheduling). More...
 
bool CanHandleTerminators
 The standard DAG builder does not normally include terminators as DAG nodes because it does not create the necessary dependencies to prevent reordering. More...
 
MachineBasicBlockBB
 State specific to the current scheduling region. More...
 
MachineBasicBlock::iterator RegionBegin
 The beginning of the range to be scheduled. More...
 
MachineBasicBlock::iterator RegionEnd
 The end of the range to be scheduled. More...
 
unsigned NumRegionInstrs
 Instructions in this region (distance(RegionBegin, RegionEnd)). More...
 
DenseMap< MachineInstr *, SUnit * > MISUnitMap
 After calling BuildSchedGraph, each machine instruction in the current scheduling region is mapped to an SUnit. More...
 
VReg2UseMap VRegUses
 After calling BuildSchedGraph, each vreg used in the scheduling region is mapped to a set of SUnits. More...
 
Reg2SUnitsMap Defs
 State internal to DAG building. More...
 
Reg2SUnitsMap Uses
 
VReg2SUnitMap VRegDefs
 Track the last instruction in this region defining each virtual register. More...
 
std::vector< SUnit * > PendingLoads
 PendingLoads - Remember where unknown loads are after the most recent unknown store, as we iterate. More...
 
DbgValueVector DbgValues
 
MachineInstrFirstDbgValue
 
BitVector LiveRegs
 Set of live physical registers for updating kill flags. More...
 

Additional Inherited Members

- Public Attributes inherited from llvm::ScheduleDAG
const TargetMachineTM
 
const TargetInstrInfoTII
 
const TargetRegisterInfoTRI
 
MachineFunctionMF
 
MachineRegisterInfoMRI
 
std::vector< SUnitSUnits
 
SUnit EntrySU
 
SUnit ExitSU
 
bool StressSched
 

Detailed Description

ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of MachineInstrs.

Definition at line 76 of file ScheduleDAGInstrs.h.

Member Typedef Documentation

typedef std::vector<std::pair<MachineInstr *, MachineInstr *> > llvm::ScheduleDAGInstrs::DbgValueVector
protected

DbgValues - Remember instruction that precedes DBG_VALUE.

These are generated by buildSchedGraph but persist so they can be referenced when emitting the final schedule.

Definition at line 147 of file ScheduleDAGInstrs.h.

Constructor & Destructor Documentation

ScheduleDAGInstrs::ScheduleDAGInstrs ( MachineFunction mf,
const MachineLoopInfo mli,
bool  IsPostRAFlag,
bool  RemoveKillFlags = false,
LiveIntervals LIS = nullptr 
)
explicit
llvm::ScheduleDAGInstrs::~ScheduleDAGInstrs ( )
inlineoverride

Definition at line 161 of file ScheduleDAGInstrs.h.

Member Function Documentation

void ScheduleDAGInstrs::addPhysRegDataDeps ( SUnit SU,
unsigned  OperIdx 
)
protected
void ScheduleDAGInstrs::addPhysRegDeps ( SUnit SU,
unsigned  OperIdx 
)
protected
void ScheduleDAGInstrs::addSchedBarrierDeps ( )

addSchedBarrierDeps - Add dependencies from instructions in the current list of instructions being scheduled to scheduling barrier.

addSchedBarrierDeps - Add dependencies from instructions in the current list of instructions being scheduled to scheduling barrier by adding the exit SU to the register defs and use list.

We want to make sure instructions which define registers that are either used by the terminator or are live-out are properly scheduled. This is especially important when the definition latency of the return value(s) are too high to be hidden by the branch or when the liveout registers used by instructions in the fallthrough block.

This is because we want to make sure instructions which define registers that are either used by the terminator or are live-out are properly scheduled. This is especially important when the definition latency of the return value(s) are too high to be hidden by the branch or when the liveout registers used by instructions in the fallthrough block.

Definition at line 217 of file ScheduleDAGInstrs.cpp.

References addVRegUseDeps(), BB, llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::contains(), llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::empty(), llvm::MachineBasicBlock::end(), llvm::ScheduleDAG::ExitSU, llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), I, llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::insert(), llvm::MachineInstr::isBarrier(), llvm::MachineInstr::isCall(), llvm::MachineOperand::isDef(), llvm::TargetRegisterInfo::isPhysicalRegister(), IsPostRA, llvm::MachineOperand::isReg(), llvm::MachineOperand::readsReg(), RegionEnd, llvm::SUnit::setInstr(), llvm::SI, llvm::MachineBasicBlock::succ_begin(), llvm::MachineBasicBlock::succ_end(), llvm::ScheduleDAG::TRI, and Uses.

Referenced by buildSchedGraph().

void ScheduleDAGInstrs::addVRegDefDeps ( SUnit SU,
unsigned  OperIdx 
)
protected

addVRegDefDeps - Add register output and data dependencies from this SUnit to instructions that occur later in the same scheduling region if they read from or write to the virtual register defined at OperIdx.

TODO: Hoist loop induction variable increments. This has to be reevaluated. Generally, IV scheduling should be done before coalescing.

Definition at line 380 of file ScheduleDAGInstrs.cpp.

References llvm::SUnit::addPred(), llvm::TargetSchedModel::computeOutputLatency(), llvm::SparseSet< ValueT, KeyFunctorT, SparseT >::end(), llvm::ScheduleDAG::ExitSU, llvm::SparseSet< ValueT, KeyFunctorT, SparseT >::find(), llvm::SUnit::getInstr(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::hasOneDef(), llvm::SparseSet< ValueT, KeyFunctorT, SparseT >::insert(), llvm::AArch64CC::MI, llvm::ScheduleDAG::MRI, llvm::SDep::Output, SchedModel, llvm::SDep::setLatency(), and VRegDefs.

Referenced by buildSchedGraph().

void ScheduleDAGInstrs::addVRegUseDeps ( SUnit SU,
unsigned  OperIdx 
)
protected
MachineBasicBlock::iterator llvm::ScheduleDAGInstrs::begin ( ) const
inline

begin - Return an iterator to the top of the current scheduling region.

Definition at line 179 of file ScheduleDAGInstrs.h.

References RegionBegin.

Referenced by llvm::ScheduleDAGMI::dumpSchedule(), enterRegion(), llvm::ScheduleDAGMI::schedule(), and llvm::ScheduleDAGMILive::schedule().

void ScheduleDAGInstrs::buildSchedGraph ( AliasAnalysis AA,
RegPressureTracker RPTracker = nullptr,
PressureDiffs PDiffs = nullptr 
)

buildSchedGraph - Build SUnits from the MachineBasicBlock that we are input.

If RegPressure is non-null, compute register pressure as a side effect.

The DAG builder is an efficient place to do it because it already visits operands.

Definition at line 749 of file ScheduleDAGInstrs.cpp.

References addChainDependency(), addPhysRegDeps(), llvm::SUnit::addPred(), addSchedBarrierDeps(), addVRegDefDeps(), addVRegUseDeps(), adjustChainDeps(), llvm::SDep::Artificial, llvm::SDep::Barrier, llvm::MapVector< KeyT, ValueT, MapType, VectorType >::begin(), llvm::SmallVectorTemplateCommon< T, typename >::begin(), CanHandleTerminators, llvm::MapVector< KeyT, ValueT, MapType, VectorType >::clear(), llvm::SparseSet< ValueT, KeyFunctorT, SparseT >::clear(), llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::clear(), llvm::ScheduleDAG::clearDAG(), DbgValues, Defs, llvm::SmallVectorBase::empty(), llvm::SparseSet< ValueT, KeyFunctorT, SparseT >::empty(), llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::empty(), EnableAASchedMI, llvm::MapVector< KeyT, ValueT, MapType, VectorType >::end(), llvm::SmallVectorTemplateCommon< T, typename >::end(), llvm::ScheduleDAG::ExitSU, llvm::MapVector< KeyT, ValueT, MapType, VectorType >::find(), FirstDbgValue, llvm::TargetMachine::getDataLayout(), llvm::MachineInstr::getNumOperands(), llvm::MCRegisterInfo::getNumRegs(), llvm::MachineRegisterInfo::getNumVirtRegs(), llvm::MachineInstr::getOperand(), llvm::RegPressureTracker::getPos(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getSubtarget(), getUnderlyingObjectsForInstr(), I, llvm::ARM_PROC::IE, llvm::PressureDiffs::init(), initSUnits(), llvm::MachineInstr::isDebugValue(), llvm::MachineOperand::isDef(), isGlobalMemoryObject(), llvm::MachineInstr::isInvariantLoad(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineInstr::isPosition(), IsPostRA, llvm::MachineOperand::isReg(), llvm::MachineInstr::isTerminator(), llvm::SUnit::Latency, llvm::MayAlias, llvm::MachineInstr::mayLoad(), llvm::MachineInstr::mayStore(), llvm::ScheduleDAG::MF, MFI, llvm::AArch64CC::MI, MISUnitMap, llvm::ScheduleDAG::MRI, llvm::SUnit::NodeNum, llvm::SUnit::NumSuccs, PendingLoads, llvm::MachineOperand::readsReg(), llvm::RegPressureTracker::recede(), RegionBegin, RegionEnd, llvm::SDep::setLatency(), llvm::SparseSet< ValueT, KeyFunctorT, SparseT >::setUniverse(), llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::setUniverse(), llvm::MapVector< KeyT, ValueT, MapType, VectorType >::size(), llvm::AArch64DB::ST, llvm::ScheduleDAG::SUnits, llvm::ScheduleDAG::TM, llvm::ScheduleDAG::TRI, llvm::TargetSubtargetInfo::useAA(), Uses, VRegDefs, and VRegUses.

Referenced by llvm::ScheduleDAGMILive::buildDAGWithRegPressure(), llvm::DefaultVLIWScheduler::schedule(), and llvm::ScheduleDAGMI::schedule().

void ScheduleDAGInstrs::dumpNode ( const SUnit SU) const
overridevirtual

Implements llvm::ScheduleDAG.

Definition at line 1265 of file ScheduleDAGInstrs.cpp.

References llvm::MachineInstr::dump(), and llvm::SUnit::getInstr().

MachineBasicBlock::iterator llvm::ScheduleDAGInstrs::end ( ) const
inline

end - Return an iterator to the bottom of the current scheduling region.

Definition at line 182 of file ScheduleDAGInstrs.h.

References RegionEnd.

Referenced by llvm::ScheduleDAGMI::dumpSchedule(), and enterRegion().

void ScheduleDAGInstrs::enterRegion ( MachineBasicBlock bb,
MachineBasicBlock::iterator  begin,
MachineBasicBlock::iterator  end,
unsigned  regioninstrs 
)
virtual

Initialize the scheduler state for the next scheduling region.

Initialize the DAG and common scheduler state for the current scheduling region.

This does not actually create the DAG, only clears it. The scheduling driver may call BuildSchedGraph multiple times per scheduling region.

Reimplemented in llvm::ScheduleDAGMILive, and llvm::ScheduleDAGMI.

Definition at line 193 of file ScheduleDAGInstrs.cpp.

References BB, begin(), end(), NumRegionInstrs, RegionBegin, and RegionEnd.

Referenced by llvm::ScheduleDAGMI::enterRegion(), and llvm::VLIWPacketizerList::PacketizeMIs().

void ScheduleDAGInstrs::exitRegion ( )
virtual

Notify that the scheduler has finished scheduling the current region.

Close the current scheduling region.

Don't clear any state in case the driver wants to refer to the previous scheduling region.

Definition at line 205 of file ScheduleDAGInstrs.cpp.

Referenced by llvm::VLIWPacketizerList::PacketizeMIs().

virtual void llvm::ScheduleDAGInstrs::finalizeSchedule ( )
inlinevirtual

finalizeSchedule - Allow targets to perform final scheduling actions at the level of the whole MachineFunction.

By default does nothing.

Definition at line 229 of file ScheduleDAGInstrs.h.

void ScheduleDAGInstrs::finishBlock ( )
virtual

finishBlock - Clean up after scheduling in the given block.

Definition at line 184 of file ScheduleDAGInstrs.cpp.

References BB.

Referenced by llvm::VLIWPacketizerList::PacketizeMIs().

void ScheduleDAGInstrs::fixupKills ( MachineBasicBlock MBB)
std::string ScheduleDAGInstrs::getDAGName ( ) const
overridevirtual

Return a label for the region of code covered by the DAG.

Return the basic block label.

It is not necessarilly unique because a block contains multiple scheduling regions. But it is fine for visualization.

Implements llvm::ScheduleDAG.

Definition at line 1285 of file ScheduleDAGInstrs.cpp.

References BB, and llvm::MachineBasicBlock::getFullName().

std::string ScheduleDAGInstrs::getGraphNodeLabel ( const SUnit SU) const
overridevirtual

Return a label for a DAG node that points to an instruction.

Implements llvm::ScheduleDAG.

Definition at line 1271 of file ScheduleDAGInstrs.cpp.

References llvm::ScheduleDAG::EntrySU, llvm::ScheduleDAG::ExitSU, llvm::SUnit::getInstr(), llvm::MachineInstr::print(), and llvm::raw_string_ostream::str().

LiveIntervals* llvm::ScheduleDAGInstrs::getLIS ( ) const
inline

Expose LiveIntervals for use in DAG mutators and such.

Definition at line 166 of file ScheduleDAGInstrs.h.

References LIS.

const MCSchedClassDesc* llvm::ScheduleDAGInstrs::getSchedClass ( SUnit SU) const
inline
const TargetSchedModel* llvm::ScheduleDAGInstrs::getSchedModel ( ) const
inline

Get the machine model for instruction scheduling.

Definition at line 169 of file ScheduleDAGInstrs.h.

References SchedModel.

Referenced by llvm::ConvergingVLIWScheduler::initialize(), and llvm::PostGenericScheduler::initialize().

SUnit * llvm::ScheduleDAGInstrs::getSUnit ( MachineInstr MI) const
inline

getSUnit - Return an existing SUnit for this MI, or NULL.

Definition at line 271 of file ScheduleDAGInstrs.h.

References I, and MISUnitMap.

Referenced by addVRegUseDeps(), llvm::ScheduleDAGMILive::computeCyclicCriticalPath(), and llvm::ScheduleDAGMI::dumpSchedule().

void ScheduleDAGInstrs::initSUnits ( )
protected

Create an SUnit for each real instruction, numbered in top-down toplological order.

The instruction order A < B, implies that no edge exists from B to A.

Map each real instruction to its SUnit.

After initSUnits, the SUnits vector cannot be resized and the scheduler may hang onto SUnit pointers. We may relax this in the future by using SUnit IDs instead of pointers.

MachineScheduler relies on initSUnits numbering the nodes by their order in the original instruction list.

Definition at line 699 of file ScheduleDAGInstrs.cpp.

References llvm::MCProcResourceDesc::BufferSize, llvm::SUnit::getInstr(), llvm::TargetSchedModel::getProcResource(), getSchedClass(), llvm::TargetSchedModel::getWriteProcResBegin(), llvm::TargetSchedModel::getWriteProcResEnd(), llvm::TargetSchedModel::hasInstrSchedModel(), llvm::SUnit::hasReservedResource, I, llvm::SUnit::isCall, llvm::MachineInstr::isCall(), llvm::SUnit::isCommutable, llvm::MachineInstr::isCommutable(), llvm::MachineInstr::isDebugValue(), llvm::SUnit::isUnbuffered, llvm::SUnit::Latency, llvm::AArch64CC::MI, MISUnitMap, newSUnit(), NumRegionInstrs, RegionBegin, RegionEnd, llvm::PPCISD::SC, SchedModel, and llvm::ScheduleDAG::SUnits.

Referenced by buildSchedGraph().

bool llvm::ScheduleDAGInstrs::isPostRA ( ) const
inline

Definition at line 163 of file ScheduleDAGInstrs.h.

References IsPostRA.

SUnit * llvm::ScheduleDAGInstrs::newSUnit ( MachineInstr MI)
inline

newSUnit - Creates a new SUnit and return a ptr to it.

Definition at line 259 of file ScheduleDAGInstrs.h.

References llvm::ScheduleDAG::SUnits.

Referenced by initSUnits().

virtual void llvm::ScheduleDAGInstrs::schedule ( )
pure virtual

schedule - Order nodes according to selected style, filling in the Sequence member.

Typically, a scheduling algorithm will implement schedule() without overriding enterRegion() or exitRegion().

Implemented in llvm::ScheduleDAGMILive, llvm::ScheduleDAGMI, llvm::DefaultVLIWScheduler, and llvm::VLIWMachineScheduler.

void ScheduleDAGInstrs::startBlock ( MachineBasicBlock BB)
virtual

startBlock - Prepare to perform scheduling in the given block.

Definition at line 180 of file ScheduleDAGInstrs.cpp.

References BB.

Referenced by llvm::VLIWPacketizerList::PacketizeMIs().

void ScheduleDAGInstrs::startBlockForKills ( MachineBasicBlock BB)
protected

PostRA helper for rewriting kill flags.

Initialize register live-range state for updating kills.

Definition at line 1076 of file ScheduleDAGInstrs.cpp.

References I, llvm::MCRegisterInfo::DiffListIterator::isValid(), LiveRegs, llvm::BitVector::reset(), llvm::BitVector::set(), llvm::SI, llvm::MachineBasicBlock::succ_begin(), llvm::MachineBasicBlock::succ_end(), and llvm::ScheduleDAG::TRI.

Referenced by fixupKills().

bool ScheduleDAGInstrs::toggleKillFlag ( MachineInstr MI,
MachineOperand MO 
)
protected

Toggle a register operand kill flag.

Other adjustments may be made to the instruction if necessary. Return true if the operand has been deleted, false if not.

Definition at line 1134 of file ScheduleDAGInstrs.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::MachineOperand::getReg(), llvm::RegState::ImplicitDefine, llvm::MachineOperand::isKill(), llvm::MCRegisterInfo::DiffListIterator::isValid(), LiveRegs, llvm::ScheduleDAG::MF, llvm::MachineOperand::setIsKill(), llvm::BitVector::test(), toggleBundleKillFlag(), and llvm::ScheduleDAG::TRI.

Referenced by fixupKills().

Member Data Documentation

MachineBasicBlock* llvm::ScheduleDAGInstrs::BB
protected
bool llvm::ScheduleDAGInstrs::CanHandleTerminators
protected

The standard DAG builder does not normally include terminators as DAG nodes because it does not create the necessary dependencies to prevent reordering.

A specialized scheduler can override TargetInstrInfo::isSchedulingBoundary then enable this flag to indicate it has taken responsibility for scheduling the terminator correctly.

Definition at line 99 of file ScheduleDAGInstrs.h.

Referenced by buildSchedGraph(), and llvm::DefaultVLIWScheduler::DefaultVLIWScheduler().

DbgValueVector llvm::ScheduleDAGInstrs::DbgValues
protected
Reg2SUnitsMap llvm::ScheduleDAGInstrs::Defs
protected

State internal to DAG building.


Defs, Uses - Remember where defs and uses of each register are as we iterate upward through the instructions. This is allocated here instead of inside BuildSchedGraph to avoid the need for it to be initialized and destructed for each block.

Definition at line 132 of file ScheduleDAGInstrs.h.

Referenced by addPhysRegDeps(), and buildSchedGraph().

MachineInstr* llvm::ScheduleDAGInstrs::FirstDbgValue
protected

Definition at line 149 of file ScheduleDAGInstrs.h.

Referenced by buildSchedGraph(), and llvm::ScheduleDAGMI::placeDebugValues().

bool llvm::ScheduleDAGInstrs::IsPostRA
protected

isPostRA flag indicates vregs cannot be present.

Definition at line 88 of file ScheduleDAGInstrs.h.

Referenced by addSchedBarrierDeps(), buildSchedGraph(), isPostRA(), and ScheduleDAGInstrs().

LiveIntervals* llvm::ScheduleDAGInstrs::LIS
protected

Live Intervals provides reaching defs in preRA scheduling.

Definition at line 82 of file ScheduleDAGInstrs.h.

Referenced by addVRegUseDeps(), getLIS(), and ScheduleDAGInstrs().

BitVector llvm::ScheduleDAGInstrs::LiveRegs
protected

Set of live physical registers for updating kill flags.

Definition at line 152 of file ScheduleDAGInstrs.h.

Referenced by fixupKills(), startBlockForKills(), and toggleKillFlag().

const MachineFrameInfo* llvm::ScheduleDAGInstrs::MFI
protected

Definition at line 79 of file ScheduleDAGInstrs.h.

Referenced by buildSchedGraph().

DenseMap<MachineInstr*, SUnit*> llvm::ScheduleDAGInstrs::MISUnitMap
protected

After calling BuildSchedGraph, each machine instruction in the current scheduling region is mapped to an SUnit.

Definition at line 118 of file ScheduleDAGInstrs.h.

Referenced by buildSchedGraph(), getSUnit(), and initSUnits().

const MachineLoopInfo* llvm::ScheduleDAGInstrs::MLI
protected

Definition at line 78 of file ScheduleDAGInstrs.h.

Referenced by llvm::VLIWMachineScheduler::schedule().

unsigned llvm::ScheduleDAGInstrs::NumRegionInstrs
protected

Instructions in this region (distance(RegionBegin, RegionEnd)).

Definition at line 114 of file ScheduleDAGInstrs.h.

Referenced by enterRegion(), and initSUnits().

std::vector<SUnit *> llvm::ScheduleDAGInstrs::PendingLoads
protected

PendingLoads - Remember where unknown loads are after the most recent unknown store, as we iterate.

As with Defs and Uses, this is here to minimize construction/destruction.

Definition at line 141 of file ScheduleDAGInstrs.h.

Referenced by buildSchedGraph().

MachineBasicBlock::iterator llvm::ScheduleDAGInstrs::RegionBegin
protected
MachineBasicBlock::iterator llvm::ScheduleDAGInstrs::RegionEnd
protected
bool llvm::ScheduleDAGInstrs::RemoveKillFlags
protected

True if the DAG builder should remove kill flags (in preparation for rescheduling).

Definition at line 92 of file ScheduleDAGInstrs.h.

Referenced by addPhysRegDeps().

TargetSchedModel llvm::ScheduleDAGInstrs::SchedModel
protected
Reg2SUnitsMap llvm::ScheduleDAGInstrs::Uses
protected
VReg2SUnitMap llvm::ScheduleDAGInstrs::VRegDefs
protected

Track the last instruction in this region defining each virtual register.

Definition at line 136 of file ScheduleDAGInstrs.h.

Referenced by addVRegDefDeps(), addVRegUseDeps(), and buildSchedGraph().

VReg2UseMap llvm::ScheduleDAGInstrs::VRegUses
protected

After calling BuildSchedGraph, each vreg used in the scheduling region is mapped to a set of SUnits.

These include all local vreg uses, not just the uses for a singly defined vreg.

Definition at line 123 of file ScheduleDAGInstrs.h.

Referenced by addVRegUseDeps(), buildSchedGraph(), llvm::ScheduleDAGMILive::computeCyclicCriticalPath(), and llvm::ScheduleDAGMILive::updatePressureDiffs().


The documentation for this class was generated from the following files: