15 #ifndef LLVM_LIB_TARGET_R600_AMDGPUSUBTARGET_H
16 #define LLVM_LIB_TARGET_R600_AMDGPUSUBTARGET_H
29 #define GET_SUBTARGETINFO_HEADER
30 #include "AMDGPUGenSubtargetInfo.inc"
34 class SIMachineFunctionInfo;
67 short TexVTXClauseSize;
74 bool FlatAddressSpace;
75 bool EnableIRStructurizer;
76 bool EnablePromoteAlloca;
78 bool EnableLoadStoreOpt;
79 bool EnableUnsafeDSOffsetFolding;
80 unsigned WavefrontSize;
83 bool EnableVGPRSpilling;
92 bool EnableHugeScratchBuffer;
95 std::unique_ptr<AMDGPUTargetLowering> TLInfo;
96 std::unique_ptr<AMDGPUInstrInfo> InstrInfo;
107 return &FrameLowering;
110 return InstrInfo.get();
113 return &InstrInfo->getRegisterInfo();
129 return HasVertexCache;
133 return TexVTXClauseSize;
149 return FP32Denormals;
153 return FP64Denormals;
161 return FlatAddressSpace;
212 return EnableIRStructurizer;
216 return EnablePromoteAlloca;
224 return EnableLoadStoreOpt;
228 return EnableUnsafeDSOffsetFolding;
232 return WavefrontSize;
243 return LocalMemorySize;
264 unsigned NumRegionInstrs)
const override;
276 return EnableHugeScratchBuffer;
OSType getOS() const
getOS - Get the parsed operating system type of this triple.
bool hasCaymanISA() const
const_iterator end(StringRef path)
Get end iterator over path.
AMDGPU specific subclass of TargetSubtarget.
int getLDSBankCount() const
bool hasFastFMAF32() const
AMDGPUSubtarget & initializeSubtargetDependencies(const Triple &TT, StringRef GPU, StringRef FS)
const_iterator begin(StringRef path)
Get begin iterator over path.
bool hasVertexCache() const
int getLocalMemorySize() const
bool loadStoreOptEnabled() const
void overrideSchedPolicy(MachineSchedPolicy &Policy, MachineInstr *begin, MachineInstr *end, unsigned NumRegionInstrs) const override
bool r600ALUEncoding() const
bool hasSGPRInitBug() const
unsigned getAmdKernelCodeChipID() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const InstrItineraryData * getInstrItineraryData() const override
AMDGPUTargetLowering * getTargetLowering() const override
const AMDGPUInstrInfo * getInstrInfo() const override
unsigned getStackEntrySize() const
Interface to describe a layout of a stack frame on a AMDIL target machine.
bool hasFlatAddressSpace() const
Itinerary data supplied by a subtarget to be used by a target.
bool isIfCvtEnabled() const
Generation getGeneration() const
bool IsIRStructurizerEnabled() const
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
short getTexVTXClauseSize() const
unsigned getMaxWavesPerCU() const
bool hasFP32Denormals() const
AMDGPU::IsaVersion getIsaVersion() const
bool isPromoteAllocaEnabled() const
bool hasFP64Denormals() const
Triple - Helper class for working with autoconf configuration names.
unsigned getExplicitKernelArgOffset() const
Returns the offset in bytes from the start of the input buffer of the first explicit kernel argument...
bool enableHugeScratchBuffer() const
Interface for the AMDGPU Implementation of the Intrinsic Info class.
const AMDGPUFrameLowering * getFrameLowering() const override
bool enableSubRegLiveness() const override
Contains the definition of a TargetInstrInfo class that is common to all AMD GPUs.
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.
Representation of each machine instruction.
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
bool unsafeDSOffsetFoldingEnabled() const
R600 DAG Lowering interface definition.
Information about the stack frame layout on the AMDGPU targets.
unsigned getWavefrontSize() const
StringRef getDeviceName() const
Primary interface to the complete machine description for the target machine.
AMDGPUSubtarget(const Triple &TT, StringRef CPU, StringRef FS, TargetMachine &TM)
bool hasBCNT(unsigned Size) const
StringRef - Represent a constant reference to a string, i.e.
bool isVGPRSpillingEnabled(const SIMachineFunctionInfo *MFI) const
bool enableMachineScheduler() const override
const AMDGPURegisterInfo * getRegisterInfo() const override