15 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
16 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
24 #define GET_INSTRINFO_HEADER
25 #include "HexagonGenInstrInfo.inc"
30 class HexagonSubtarget;
32 virtual void anchor();
67 bool AllowModify)
const override;
76 unsigned &SrcReg,
unsigned &SrcReg2,
77 int &Mask,
int &
Value)
const override;
81 unsigned DestReg,
unsigned SrcReg,
82 bool KillSrc)
const override;
134 unsigned ExtraPredCycles,
138 unsigned NumTCycles,
unsigned ExtraTCycles,
140 unsigned NumFCycles,
unsigned ExtraFCycles,
150 std::vector<MachineOperand> &Pred)
const override;
166 bool isValidOffset(
unsigned Opcode,
int Offset,
bool Extend =
true)
const;
217 unsigned short OperandNum)
const;
227 unsigned &PredRegPos,
unsigned &PredRegFlags)
const;
bool isSpillPredRegOp(const MachineInstr *MI) const
bool isConditionalLoad(const MachineInstr *MI) const
bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
bool isBranch(const MachineInstr *MI) const
bool isExtendable(const MachineInstr *MI) const
bool isU6_3Immediate(const int value) const
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
int getMaxValue(const MachineInstr *MI) const
int getDotNewPredJumpOp(MachineInstr *MI, const MachineBranchProbabilityInfo *MBPI) const
bool isU6_2Immediate(const int value) const
int getMinValue(const MachineInstr *MI) const
bool isEndLoopN(Opcode_t Opcode) const
bool isU6_1Immediate(const int value) const
unsigned short getCExtOpNum(const MachineInstr *MI) const
bool PredicateInstruction(MachineInstr *MI, ArrayRef< MachineOperand > Cond) const override
bool isPostIncrement(const MachineInstr *MI) const
bool isConditionalTransfer(const MachineInstr *MI) const
bool isPredicatedNew(const MachineInstr *MI) const
bool isSchedulingBoundary(const MachineInstr *MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const override
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot...
bool isMemOp(const MachineInstr *MI) const
bool isPredicated(const MachineInstr *MI) const override
unsigned getSize(const MachineInstr *MI) const
int GetDotOldOp(const int opc) const
bool isS4_1Immediate(const int value) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
bool isNewValueJumpCandidate(const MachineInstr *MI) const
bool predOpcodeHasNot(ArrayRef< MachineOperand > Cond) const
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
const HexagonRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
unsigned getInvertedPredicatedOpcode(const int Opc) const
unsigned getAddrMode(const MachineInstr *MI) const
bundle_iterator< MachineInstr, instr_iterator > iterator
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, const BranchProbability &Probability) const override
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, const BranchProbability &Probability) const override
MVT - Machine Value Type.
unsigned RemoveBranch(MachineBasicBlock &MBB) const override
bool isNewValueStore(const MachineInstr *MI) const
bundle_iterator - MachineBasicBlock iterator that automatically skips over MIs that are inside bundle...
bool ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr *LoadMI) const override
bool isSaveCalleeSavedRegsCall(const MachineInstr *MI) const
bool isDeallocRet(const MachineInstr *MI) const
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex) const override
bool isNewValueInst(const MachineInstr *MI) const
unsigned createVR(MachineFunction *MF, MVT VT) const
bool isPredicatedTrue(const MachineInstr *MI) const
bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override
expandPostRAPseudo - This function is called for all pseudo instructions that remain after register a...
bool isConstExtended(const MachineInstr *MI) const
void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, SmallVectorImpl< MachineInstr * > &NewMIs) const
bool isConditionalStore(const MachineInstr *MI) const
int GetDotNewOp(const MachineInstr *MI) const
EVT - Extended Value Type.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool getPredReg(ArrayRef< MachineOperand > Cond, unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const
bool isU6_0Immediate(const int value) const
HexagonInstrInfo(HexagonSubtarget &ST)
bool DefinesPredicate(MachineInstr *MI, std::vector< MachineOperand > &Pred) const override
int getCondOpcode(int Opc, bool sense) const
bool isS6_Immediate(const int value) const
bool isPredicable(MachineInstr *MI) const override
int GetDotNewPredOp(MachineInstr *MI, const MachineBranchProbabilityInfo *MBPI) const
bool isExtended(const MachineInstr *MI) const
TargetSubtargetInfo - Generic base class for all target subtargets.
bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override
For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two registe...
Representation of each machine instruction.
bool isS4_3Immediate(const int value) const
bool isValidAutoIncImm(const EVT VT, const int Offset) const
unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot...
bool isConditionalALU32(const MachineInstr *MI) const
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, DebugLoc DL) const override
bool isOperandExtended(const MachineInstr *MI, unsigned short OperandNum) const
short getNonExtOpcode(const MachineInstr *MI) const
bool isS4_0Immediate(const int value) const
bool isU6_Immediate(const int value) const
bool isS8_Immediate(const int value) const
LLVM Value Representation.
void immediateExtend(MachineInstr *MI) const
immediateExtend - Changes the instruction in place to one using an immediate extender.
bool isNewValueJump(const MachineInstr *MI) const
void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, SmallVectorImpl< MachineInstr * > &NewMIs) const
bool isNewValue(const MachineInstr *MI) const
bool PredOpcodeHasJMP_c(Opcode_t Opcode) const
bool isValidOffset(unsigned Opcode, int Offset, bool Extend=true) const
bool NonExtEquivalentExists(const MachineInstr *MI) const
bool isDotNewInst(const MachineInstr *MI) const
bool isS12_Immediate(const int value) const
bool isS4_2Immediate(const int value) const
bool mayBeNewStore(const MachineInstr *MI) const