43 #define DEBUG_TYPE "ppc-instr-info"
45 #define GET_INSTRMAP_INFO
46 #define GET_INSTRINFO_CTOR_DTOR
47 #include "PPCGenInstrInfo.inc"
51 cl::desc(
"Disable analysis for CTR loops"));
57 cl::desc(
"Causes the backend to crash instead of generating a nop VSX copy"),
62 cl::desc(
"Use the old (incorrect) instruction latency calculation"));
65 void PPCInstrInfo::anchor() {}
69 Subtarget(STI), RI(STI.getTargetMachine()) {}
77 static_cast<const PPCSubtarget *
>(STI)->getDarwinDirective();
81 static_cast<const PPCSubtarget *
>(STI)->getInstrItineraryData();
102 assert(DAG->
TII &&
"No InstrInfo?");
112 unsigned *PredCost)
const {
114 return PPCGenInstrInfo::getInstrLatency(ItinData, MI, PredCost);
123 unsigned Latency = 1;
134 Latency = std::max(Latency, (
unsigned) Cycle);
143 unsigned UseIdx)
const {
144 int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
157 IsRegCR = PPC::CRRCRegClass.contains(Reg) ||
158 PPC::CRBITRCRegClass.contains(Reg);
191 unsigned &SrcReg,
unsigned &DstReg,
192 unsigned &SubIdx)
const {
194 default:
return false;
196 case PPC::EXTSW_32_64:
199 SubIdx = PPC::sub_32;
213 case PPC::RESTORE_CR:
214 case PPC::RESTORE_CRBIT:
220 case PPC::RESTORE_VRSAVE:
243 case PPC::SPILL_CRBIT:
249 case PPC::SPILL_VRSAVE:
296 bool ChangeReg0 =
false;
302 "Expecting a two-address instruction!");
321 .addImm((MB-1) & 31);
342 unsigned &SrcOpIdx2)
const {
363 default: Opcode = PPC::NOP;
break;
370 BuildMI(MBB, MI, DL,
get(Opcode));
384 bool AllowModify)
const {
385 bool isPPC64 = Subtarget.
isPPC64();
405 }
else if (LastInst->
getOpcode() == PPC::BCC) {
413 }
else if (LastInst->
getOpcode() == PPC::BC) {
421 }
else if (LastInst->
getOpcode() == PPC::BCn) {
429 }
else if (LastInst->
getOpcode() == PPC::BDNZ8 ||
440 }
else if (LastInst->
getOpcode() == PPC::BDZ8 ||
461 if (SecondLastInst && I != MBB.
begin() &&
466 if (SecondLastInst->
getOpcode() == PPC::BCC &&
476 }
else if (SecondLastInst->
getOpcode() == PPC::BC &&
486 }
else if (SecondLastInst->
getOpcode() == PPC::BCn &&
496 }
else if ((SecondLastInst->
getOpcode() == PPC::BDNZ8 ||
510 }
else if ((SecondLastInst->
getOpcode() == PPC::BDZ8 ||
528 if (SecondLastInst->
getOpcode() == PPC::B &&
548 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
549 I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
550 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() !=
PPC::BDNZ &&
551 I->getOpcode() != PPC::BDZ8 && I->getOpcode() !=
PPC::BDZ)
555 I->eraseFromParent();
559 if (I == MBB.
begin())
return 1;
561 if (I->getOpcode() != PPC::BCC &&
562 I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
563 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() !=
PPC::BDNZ &&
564 I->getOpcode() != PPC::BDZ8 && I->getOpcode() !=
PPC::BDZ)
568 I->eraseFromParent();
578 assert(TBB &&
"InsertBranch must not be told to insert a fallthrough");
579 assert((Cond.
size() == 2 || Cond.
size() == 0) &&
580 "PPC branch conditions have two components!");
582 bool isPPC64 = Subtarget.
isPPC64();
587 BuildMI(&MBB, DL,
get(PPC::B)).addMBB(TBB);
588 else if (Cond[1].
getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
589 BuildMI(&MBB, DL,
get(Cond[0].getImm() ?
591 (isPPC64 ? PPC::BDZ8 :
PPC::BDZ))).addMBB(TBB);
593 BuildMI(&MBB, DL,
get(PPC::BC)).addOperand(Cond[1]).
addMBB(TBB);
597 BuildMI(&MBB, DL,
get(PPC::BCC))
603 if (Cond[1].
getReg() == PPC::CTR || Cond[1].
getReg() == PPC::CTR8)
604 BuildMI(&MBB, DL,
get(Cond[0].getImm() ?
612 BuildMI(&MBB, DL,
get(PPC::BCC))
621 unsigned TrueReg,
unsigned FalseReg,
622 int &CondCycles,
int &TrueCycles,
int &FalseCycles)
const {
626 if (Cond.
size() != 2)
631 if (Cond[1].
getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
642 if (!PPC::GPRCRegClass.hasSubClassEq(RC) &&
643 !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) &&
644 !PPC::G8RCRegClass.hasSubClassEq(RC) &&
645 !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC))
662 unsigned TrueReg,
unsigned FalseReg)
const {
663 assert(Cond.
size() == 2 &&
664 "PPC branch conditions have two components!");
667 "Cannot insert select on target without ISEL support");
672 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
673 assert(RC &&
"TrueReg and FalseReg must have overlapping register classes");
675 bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) ||
676 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC);
678 PPC::GPRCRegClass.hasSubClassEq(RC) ||
679 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) &&
680 "isel is for regular integer GPRs only");
682 unsigned OpCode = Is64Bit ? PPC::ISEL8 : PPC::ISEL;
683 unsigned SelectPred = Cond[0].getImm();
687 switch (SelectPred) {
689 case PPC::PRED_EQ: SubIdx = PPC::sub_eq; SwapOps =
false;
break;
690 case PPC::PRED_NE: SubIdx = PPC::sub_eq; SwapOps =
true;
break;
691 case PPC::PRED_LT: SubIdx = PPC::sub_lt; SwapOps =
false;
break;
692 case PPC::PRED_GE: SubIdx = PPC::sub_lt; SwapOps =
true;
break;
693 case PPC::PRED_GT: SubIdx = PPC::sub_gt; SwapOps =
false;
break;
694 case PPC::PRED_LE: SubIdx = PPC::sub_gt; SwapOps =
true;
break;
695 case PPC::PRED_UN: SubIdx = PPC::sub_un; SwapOps =
false;
break;
696 case PPC::PRED_NU: SubIdx = PPC::sub_un; SwapOps =
true;
break;
701 unsigned FirstReg = SwapOps ? FalseReg : TrueReg,
702 SecondReg = SwapOps ? TrueReg : FalseReg;
707 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) ||
708 MRI.getRegClass(FirstReg)->contains(PPC::X0)) {
710 MRI.getRegClass(FirstReg)->
contains(PPC::X0) ?
711 &PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass;
712 unsigned OldFirstReg = FirstReg;
713 FirstReg = MRI.createVirtualRegister(FirstRC);
718 BuildMI(MBB, MI, dl,
get(OpCode), DestReg)
725 if (CRBit == PPC::CR0LT || CRBit == PPC::CR1LT ||
726 CRBit == PPC::CR2LT || CRBit == PPC::CR3LT ||
727 CRBit == PPC::CR4LT || CRBit == PPC::CR5LT ||
728 CRBit == PPC::CR6LT || CRBit == PPC::CR7LT)
730 if (CRBit == PPC::CR0GT || CRBit == PPC::CR1GT ||
731 CRBit == PPC::CR2GT || CRBit == PPC::CR3GT ||
732 CRBit == PPC::CR4GT || CRBit == PPC::CR5GT ||
733 CRBit == PPC::CR6GT || CRBit == PPC::CR7GT)
735 if (CRBit == PPC::CR0EQ || CRBit == PPC::CR1EQ ||
736 CRBit == PPC::CR2EQ || CRBit == PPC::CR3EQ ||
737 CRBit == PPC::CR4EQ || CRBit == PPC::CR5EQ ||
738 CRBit == PPC::CR6EQ || CRBit == PPC::CR7EQ)
740 if (CRBit == PPC::CR0UN || CRBit == PPC::CR1UN ||
741 CRBit == PPC::CR2UN || CRBit == PPC::CR3UN ||
742 CRBit == PPC::CR4UN || CRBit == PPC::CR5UN ||
743 CRBit == PPC::CR6UN || CRBit == PPC::CR7UN)
746 assert(Ret != 4 &&
"Invalid CR bit register");
752 unsigned DestReg,
unsigned SrcReg,
753 bool KillSrc)
const {
757 if (PPC::F8RCRegClass.
contains(DestReg) &&
758 PPC::VSRCRegClass.
contains(SrcReg)) {
766 }
else if (PPC::VRRCRegClass.
contains(DestReg) &&
767 PPC::VSRCRegClass.
contains(SrcReg)) {
775 }
else if (PPC::F8RCRegClass.
contains(SrcReg) &&
776 PPC::VSRCRegClass.
contains(DestReg)) {
784 }
else if (PPC::VRRCRegClass.
contains(SrcReg) &&
785 PPC::VSRCRegClass.
contains(DestReg)) {
796 if (PPC::CRBITRCRegClass.
contains(SrcReg) &&
797 PPC::GPRCRegClass.
contains(DestReg)) {
803 BuildMI(MBB, I, DL,
get(PPC::RLWINM), DestReg)
809 }
else if (PPC::CRRCRegClass.
contains(SrcReg) &&
810 PPC::G8RCRegClass.
contains(DestReg)) {
811 BuildMI(MBB, I, DL,
get(PPC::MFOCRF8), DestReg)
814 }
else if (PPC::CRRCRegClass.
contains(SrcReg) &&
815 PPC::GPRCRegClass.
contains(DestReg)) {
822 if (PPC::GPRCRegClass.
contains(DestReg, SrcReg))
824 else if (PPC::G8RCRegClass.
contains(DestReg, SrcReg))
826 else if (PPC::F4RCRegClass.
contains(DestReg, SrcReg))
828 else if (PPC::CRRCRegClass.
contains(DestReg, SrcReg))
830 else if (PPC::VRRCRegClass.
contains(DestReg, SrcReg))
832 else if (PPC::VSRCRegClass.
contains(DestReg, SrcReg))
842 else if (PPC::VSFRCRegClass.
contains(DestReg, SrcReg) ||
843 PPC::VSSRCRegClass.
contains(DestReg, SrcReg))
845 else if (PPC::QFRCRegClass.
contains(DestReg, SrcReg))
847 else if (PPC::QSRCRegClass.
contains(DestReg, SrcReg))
849 else if (PPC::QBRCRegClass.
contains(DestReg, SrcReg))
851 else if (PPC::CRBITRCRegClass.
contains(DestReg, SrcReg))
858 BuildMI(MBB, I, DL, MCID, DestReg)
867 unsigned SrcReg,
bool isKill,
871 bool &NonRI,
bool &SpillsVRS)
const{
876 if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
877 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
882 }
else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
883 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
888 }
else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
893 }
else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
898 }
else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
904 }
else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
910 }
else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
916 }
else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
922 }
else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
928 }
else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
934 }
else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
936 "VRSAVE only needs spill/restore on Darwin");
942 }
else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
948 }
else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
954 }
else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
970 unsigned SrcReg,
bool isKill,
int FrameIdx,
979 bool NonRI =
false, SpillsVRS =
false;
980 if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs,
990 for (
unsigned i = 0, e = NewMIs.
size(); i != e; ++i)
991 MBB.
insert(MI, NewMIs[i]);
1004 unsigned DestReg,
int FrameIdx,
1007 bool &NonRI,
bool &SpillsVRS)
const{
1011 if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1012 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1014 DestReg), FrameIdx));
1015 }
else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1016 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1019 }
else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1022 }
else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1025 }
else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1027 get(PPC::RESTORE_CR), DestReg),
1030 }
else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1032 get(PPC::RESTORE_CRBIT), DestReg),
1035 }
else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1039 }
else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1043 }
else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1047 }
else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1051 }
else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1053 "VRSAVE only needs spill/restore on Darwin");
1055 get(PPC::RESTORE_VRSAVE),
1059 }
else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1063 }
else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1067 }
else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1081 unsigned DestReg,
int FrameIdx,
1087 if (MI != MBB.
end()) DL = MI->getDebugLoc();
1092 bool NonRI =
false, SpillsVRS =
false;
1093 if (LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs,
1103 for (
unsigned i = 0, e = NewMIs.
size(); i != e; ++i)
1104 MBB.
insert(MI, NewMIs[i]);
1117 assert(Cond.
size() == 2 &&
"Invalid PPC branch opcode!");
1118 if (Cond[1].
getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
1119 Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
1131 if (DefOpc != PPC::LI && DefOpc != PPC::LI8)
1154 assert(UseIdx < UseMI->getNumOperands() &&
"Cannot find Reg in UseMI");
1155 assert(UseIdx < UseMCID.
getNumOperands() &&
"No operand description for Reg");
1161 if (UseInfo->isLookupPtrRegClass()) {
1162 if (UseInfo->RegClass != 1)
1165 if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID &&
1166 UseInfo->RegClass != PPC::G8RC_NOX0RegClassID)
1173 if (UseInfo->Constraints != 0)
1177 if (UseInfo->isLookupPtrRegClass()) {
1178 bool isPPC64 = Subtarget.
isPPC64();
1179 ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;
1181 ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ?
1182 PPC::ZERO8 : PPC::ZERO;
1197 if (
I->definesRegister(PPC::CTR) ||
I->definesRegister(PPC::CTR8))
1209 unsigned NumT,
unsigned ExtraT,
1211 unsigned NumF,
unsigned ExtraF,
1242 if (OpC == PPC::BLR || OpC == PPC::BLR8) {
1243 if (Pred[1].
getReg() == PPC::CTR8 || Pred[1].
getReg() == PPC::CTR) {
1244 bool isPPC64 = Subtarget.
isPPC64();
1245 MI->
setDesc(
get(Pred[0].getImm() ?
1246 (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR) :
1247 (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR)));
1251 .addReg(Pred[1].
getReg());
1255 .addReg(Pred[1].
getReg());
1259 .addImm(Pred[0].getImm())
1260 .addReg(Pred[1].
getReg());
1264 }
else if (OpC == PPC::B) {
1265 if (Pred[1].
getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1266 bool isPPC64 = Subtarget.
isPPC64();
1267 MI->
setDesc(
get(Pred[0].getImm() ?
1269 (isPPC64 ? PPC::BDZ8 :
PPC::BDZ)));
1276 .addReg(Pred[1].
getReg())
1284 .addReg(Pred[1].
getReg())
1292 .addImm(Pred[0].getImm())
1293 .addReg(Pred[1].
getReg())
1298 }
else if (OpC == PPC::BCTR || OpC == PPC::BCTR8 ||
1300 if (Pred[1].
getReg() == PPC::CTR8 || Pred[1].
getReg() == PPC::CTR)
1303 bool setLR = OpC ==
PPC::BCTRL || OpC == PPC::BCTRL8;
1304 bool isPPC64 = Subtarget.
isPPC64();
1307 MI->
setDesc(
get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8) :
1308 (setLR ? PPC::BCCTRL : PPC::BCCTR)));
1310 .addReg(Pred[1].
getReg());
1313 MI->
setDesc(
get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n) :
1314 (setLR ? PPC::BCCTRLn : PPC::BCCTRn)));
1316 .addReg(Pred[1].
getReg());
1320 MI->
setDesc(
get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8) :
1321 (setLR ? PPC::BCCCTRL : PPC::BCCCTR)));
1323 .addImm(Pred[0].getImm())
1324 .addReg(Pred[1].
getReg());
1333 assert(Pred1.
size() == 2 &&
"Invalid PPC first predicate");
1334 assert(Pred2.
size() == 2 &&
"Invalid PPC second predicate");
1336 if (Pred1[1].
getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR)
1338 if (Pred2[1].
getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR)
1342 if (Pred1[1].
getReg() != Pred2[1].getReg())
1363 std::vector<MachineOperand> &Pred)
const {
1371 { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass,
1372 &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass };
1415 unsigned &SrcReg,
unsigned &SrcReg2,
1416 int &Mask,
int &
Value)
const {
1420 default:
return false;
1443 unsigned SrcReg,
unsigned SrcReg2,
1444 int Mask,
int Value,
1454 if (OpC == PPC::FCMPUS || OpC == PPC::FCMPUD)
1465 bool isPPC64 = Subtarget.
isPPC64();
1466 bool is32BitSignedCompare = OpC == PPC::CMPWI || OpC == PPC::CMPW;
1467 bool is32BitUnsignedCompare = OpC == PPC::CMPLWI || OpC == PPC::CMPLW;
1468 bool is64BitUnsignedCompare = OpC == PPC::CMPLDI || OpC == PPC::CMPLD;
1472 if (!MI)
return false;
1475 bool equalityOnly =
false;
1478 if (is32BitSignedCompare) {
1480 if (MIOpC == PPC::SRAW || MIOpC == PPC::SRAWo ||
1481 MIOpC == PPC::SRAWI || MIOpC == PPC::SRAWIo ||
1482 MIOpC == PPC::EXTSB || MIOpC == PPC::EXTSBo ||
1483 MIOpC == PPC::EXTSH || MIOpC == PPC::EXTSHo ||
1484 MIOpC == PPC::EXTSW || MIOpC == PPC::EXTSWo) {
1488 }
else if (is32BitUnsignedCompare) {
1491 if (MIOpC == PPC::CNTLZW || MIOpC == PPC::CNTLZWo ||
1492 MIOpC == PPC::SLW || MIOpC == PPC::SLWo ||
1493 MIOpC == PPC::SRW || MIOpC == PPC::SRWo) {
1495 equalityOnly =
true;
1499 equalityOnly = is64BitUnsignedCompare;
1501 equalityOnly = is32BitUnsignedCompare;
1513 }
else if (UseMI->
getOpcode() == PPC::ISEL ||
1516 if (SubIdx != PPC::sub_eq)
1528 bool FoundUse =
false;
1564 for (; I != E && !noSub; --
I) {
1568 if (&*I != CmpInstr && (
1579 if ((OpC == PPC::CMPW || OpC == PPC::CMPLW ||
1580 OpC == PPC::CMPD || OpC == PPC::CMPLD) &&
1581 (IOpC == PPC::SUBF || IOpC == PPC::SUBF8) &&
1604 if (MIOpC == PPC::ANDIo || MIOpC == PPC::ANDIo8)
1607 NewOpC = PPC::getRecordFormOpcode(MIOpC);
1628 bool ShouldSwap =
false;
1635 ShouldSwap = !ShouldSwap;
1645 assert((!equalityOnly ||
1647 "Invalid predicate for equality-only optimization");
1650 }
else if (UseMI->
getOpcode() == PPC::ISEL ||
1653 assert((!equalityOnly || NewSubReg == PPC::sub_eq) &&
1654 "Invalid CR bit for equality-only optimization");
1656 if (NewSubReg == PPC::sub_lt)
1657 NewSubReg = PPC::sub_gt;
1658 else if (NewSubReg == PPC::sub_gt)
1659 NewSubReg = PPC::sub_lt;
1677 if (MIOpC != NewOpC) {
1690 *ImpDefs; ++ImpDefs)
1696 *ImpUses; ++ImpUses)
1705 for (
unsigned i = 0, e = PredsToUpdate.
size(); i < e; i++)
1706 PredsToUpdate[i].first->setImm(PredsToUpdate[i].second);
1708 for (
unsigned i = 0, e = SubRegsToUpdate.
size(); i < e; i++)
1709 SubRegsToUpdate[i].first->setSubReg(SubRegsToUpdate[i].second);
void push_back(const T &Elt)
The memory access reads data.
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
The memory access writes data.
const uint16_t * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override
int getNonRecordFormOpcode(uint16_t)
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
MachineBasicBlock * getMBB() const
bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
bool ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, unsigned Reg, MachineRegisterInfo *MRI) const override
Describe properties that are true of each instruction in the target description file.
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
A Stackmap instruction captures the location of live variables at its position in the instruction str...
const uint16_t * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction...
static cl::opt< bool > DisableCmpOpt("disable-ppc-cmp-opt", cl::desc("Disable compare instruction optimization"), cl::Hidden)
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
bool isDarwin() const
isDarwin - True if this is any darwin platform.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
hasSuperClassEq - Returns true if RC is a super-class of or equal to this class.
const char * getSymbolName() const
CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a BCTRL instruction.
const MCPhysReg * iterator
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, unsigned f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
getMachineMemOperand - Allocate a new MachineMemOperand.
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
CreateTargetHazardRecognizer - Return the hazard recognizer to use for this target when scheduling th...
static MachinePointerInfo getFixedStack(int FI, int64_t offset=0)
getFixedStack - Return a MachinePointerInfo record that refers to the the specified FrameIndex...
MachineInstr * commuteInstruction(MachineInstr *MI, bool NewMI) const override
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, const BranchProbability &Probability) const override
COPY - Target-independent register copy.
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const
Return the cycle for the given class and operand.
PPCDispatchGroupSBHazardRecognizer - This class implements a scoreboard-based hazard recognizer for P...
MachineMemOperand - A description of a memory reference used in the backend.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false)
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
use_instr_iterator use_instr_begin(unsigned RegNo) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
const TargetRegisterClass * getRegClass(unsigned Reg) const
getRegClass - Return the register class of the specified virtual register.
iterator begin() const
begin/end - Return all of the registers in this class.
Reg
All possible values of the reg field in the ModR/M byte.
const uint16_t * ImplicitUses
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
bool PredicateInstruction(MachineInstr *MI, ArrayRef< MachineOperand > Pred) const override
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
INLINEASM - Represents an inline asm block.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
defusechain_iterator - This class provides iterator support for machine operands in the function that...
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
PPCInstrInfo(PPCSubtarget &STI)
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
virtual MachineInstr * commuteInstruction(MachineInstr *MI, bool NewMI=false) const
If a target has any instructions that are commutable but require converting to different instructions...
CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based loops.
R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
getMatchingSuperReg - Return a super-register of the specified register Reg so its sub-register of in...
CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const override
Itinerary data supplied by a subtarget to be used by a target.
iterator getLastNonDebugInstr()
getLastNonDebugInstr - returns an iterator to the last non-debug instruction in the basic block...
bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
size_t size() const
size - Get the array size.
Instances of this class represent a single low-level machine instruction.
unsigned getKillRegState(bool B)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineBasicBlock * getParent() const
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
unsigned getDeadRegState(bool B)
VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
bundle_iterator< MachineInstr, instr_iterator > iterator
Patchable call instruction - this instruction represents a call to a constant address, followed by a series of NOPs.
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
int getAltVSXFMAOpcode(uint16_t Opcode)
bool isUnpredicatedTerminator(const MachineInstr *MI) const override
const MachineOperand & getOperand(unsigned i) const
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const override
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
void setImm(int64_t immVal)
MI-level patchpoint operands.
PPCHazardRecognizer970 - This class defines a finite state automata that models the dispatch logic on...
bool empty() const
empty - Check if the array is empty.
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
unsigned getSubReg() const
unsigned RemoveBranch(MachineBasicBlock &MBB) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const override
bool isPseudo() const
Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction...
static unsigned getCRFromCRBit(unsigned SrcReg)
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
bool isPredicable(MachineInstr *MI) const override
bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
void setIsKill(bool Val=true)
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
static bool MBBDefinesCTR(MachineBasicBlock &MBB)
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr *MI, unsigned *PredCost=nullptr) const override
bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
void setOpcode(unsigned Op)
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const
If specified MI is commutable, return the two operand indices that would swap value.
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
static unsigned getCRBitValue(unsigned CRBit)
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
int getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const override
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
static cl::opt< bool > VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy", cl::desc("Causes the backend to crash instead of generating a nop VSX copy"), cl::Hidden)
static cl::opt< bool > UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden, cl::desc("Use the old (incorrect) instruction latency calculation"))
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
bool isPredicated(const MachineInstr *MI) const override
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
void getNoopForMachoTarget(MCInst &NopInst) const override
getNoopForMachoTarget - Return the noop instruction to use for a noop.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
TargetSubtargetInfo - Generic base class for all target subtargets.
const PPCRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Representation of each machine instruction.
Predicate InvertPredicate(Predicate Opcode)
Invert the specified predicate. != -> ==, < -> >=.
unsigned getSchedClass() const
Return the scheduling class for this instruction.
const MachineOperand & getMetaOper(unsigned Pos)
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
void setReg(unsigned Reg)
Change the register this operand corresponds to.
static MachineOperand CreateImm(int64_t Val)
void setSubReg(unsigned subReg)
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const TargetInstrInfo * TII
virtual ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
unsigned getReg() const
getReg - Returns the register number.
const uint16_t * ImplicitDefs
unsigned GetInstSizeInBytes(const MachineInstr *MI) const
GetInstSize - Return the number of bytes of code the specified instruction may be.
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
LLVM Value Representation.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
static use_instr_iterator use_instr_end()
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
const MCOperandInfo * OpInfo
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
unsigned getDarwinDirective() const
getDarwinDirective - Returns the -m directive specified for the cpu.
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, DebugLoc DL) const override
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer to use for this target when ...
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
This holds information about one operand of a machine instruction, indicating the register class for ...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
static cl::opt< bool > DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden, cl::desc("Disable analysis for CTR loops"))
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
bool DefinesPredicate(MachineInstr *MI, std::vector< MachineOperand > &Pred) const override
bool contains(unsigned Reg) const
contains - Return true if the specified register is included in this register class.
Predicate getSwappedPredicate(Predicate Opcode)
Assume the condition register is set by MI(a,b), return the predicate if we modify the instructions s...