LLVM  3.7.0
Enumerations | Functions
llvm::PPC Namespace Reference

Define some predicates that are used for node matching. More...

Enumerations

enum  Fixups {
  fixup_ppc_br24 = FirstTargetFixupKind, fixup_ppc_brcond14, fixup_ppc_br24abs, fixup_ppc_brcond14abs,
  fixup_ppc_half16, fixup_ppc_half16ds, fixup_ppc_nofixup, LastTargetFixupKind,
  NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
}
 
enum  Predicate {
  PRED_LT = (0 << 5) | 12, PRED_LE = (1 << 5) | 4, PRED_EQ = (2 << 5) | 12, PRED_GE = (0 << 5) | 4,
  PRED_GT = (1 << 5) | 12, PRED_NE = (2 << 5) | 4, PRED_UN = (3 << 5) | 12, PRED_NU = (3 << 5) | 4,
  PRED_LT_MINUS = (0 << 5) | 14, PRED_LE_MINUS = (1 << 5) | 6, PRED_EQ_MINUS = (2 << 5) | 14, PRED_GE_MINUS = (0 << 5) | 6,
  PRED_GT_MINUS = (1 << 5) | 14, PRED_NE_MINUS = (2 << 5) | 6, PRED_UN_MINUS = (3 << 5) | 14, PRED_NU_MINUS = (3 << 5) | 6,
  PRED_LT_PLUS = (0 << 5) | 15, PRED_LE_PLUS = (1 << 5) | 7, PRED_EQ_PLUS = (2 << 5) | 15, PRED_GE_PLUS = (0 << 5) | 7,
  PRED_GT_PLUS = (1 << 5) | 15, PRED_NE_PLUS = (2 << 5) | 7, PRED_UN_PLUS = (3 << 5) | 15, PRED_NU_PLUS = (3 << 5) | 7,
  PRED_BIT_SET = 1024, PRED_BIT_UNSET = 1025
}
 Predicate - These are "(BI << 5) | BO" for various predicates. More...
 
enum  {
  DIR_NONE, DIR_32, DIR_440, DIR_601,
  DIR_602, DIR_603, DIR_7400, DIR_750,
  DIR_970, DIR_A2, DIR_E500mc, DIR_E5500,
  DIR_PWR3, DIR_PWR4, DIR_PWR5, DIR_PWR5X,
  DIR_PWR6, DIR_PWR6X, DIR_PWR7, DIR_PWR8,
  DIR_64
}
 

Functions

Predicate InvertPredicate (Predicate Opcode)
 Invert the specified predicate. != -> ==, < -> >=. More...
 
Predicate getSwappedPredicate (Predicate Opcode)
 Assume the condition register is set by MI(a,b), return the predicate if we modify the instructions such that condition register is set by MI(b,a). More...
 
int getNonRecordFormOpcode (uint16_t)
 
bool isVPKUHUMShuffleMask (ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
 isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a VPKUHUM instruction. More...
 
bool isVPKUWUMShuffleMask (ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
 isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a VPKUWUM instruction. More...
 
bool isVPKUDUMShuffleMask (ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
 isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a VPKUDUM instruction. More...
 
bool isVMRGLShuffleMask (ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG)
 isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for a VRGL* instruction with the specified unit size (1,2 or 4 bytes). More...
 
bool isVMRGHShuffleMask (ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG)
 isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for a VRGH* instruction with the specified unit size (1,2 or 4 bytes). More...
 
bool isVMRGEOShuffleMask (ShuffleVectorSDNode *N, bool CheckEven, unsigned ShuffleKind, SelectionDAG &DAG)
 isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for a VMRGEW or VMRGOW instruction More...
 
int isVSLDOIShuffleMask (SDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
 isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift amount, otherwise return -1. More...
 
bool isSplatShuffleMask (ShuffleVectorSDNode *N, unsigned EltSize)
 isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand specifies a splat of a single element that is suitable for input to VSPLTB/VSPLTH/VSPLTW. More...
 
unsigned getVSPLTImmediate (SDNode *N, unsigned EltSize, SelectionDAG &DAG)
 getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the specified isSplatShuffleMask VECTOR_SHUFFLE mask. More...
 
SDValue get_VSPLTI_elt (SDNode *N, unsigned ByteSize, SelectionDAG &DAG)
 get_VSPLTI_elt - If this is a build_vector of constants which can be formed by using a vspltis[bhw] instruction of the specified element size, return the constant being splatted. More...
 
int isQVALIGNIShuffleMask (SDNode *N)
 If this is a qvaligni shuffle mask, return the shift amount, otherwise return -1. More...
 
FastISelcreateFastISel (FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo)
 
int getAltVSXFMAOpcode (uint16_t Opcode)
 

Detailed Description

Define some predicates that are used for node matching.

Enumeration Type Documentation

anonymous enum
Enumerator
DIR_NONE 
DIR_32 
DIR_440 
DIR_601 
DIR_602 
DIR_603 
DIR_7400 
DIR_750 
DIR_970 
DIR_A2 
DIR_E500mc 
DIR_E5500 
DIR_PWR3 
DIR_PWR4 
DIR_PWR5 
DIR_PWR5X 
DIR_PWR6 
DIR_PWR6X 
DIR_PWR7 
DIR_PWR8 
DIR_64 

Definition at line 38 of file PPCSubtarget.h.

Enumerator
fixup_ppc_br24 
fixup_ppc_brcond14 

fixup_ppc_brcond14 - 14-bit PC relative relocation for conditional branches.

fixup_ppc_br24abs 

fixup_ppc_br24abs - 24-bit absolute relocation for direct branches like 'ba' and 'bla'.

fixup_ppc_brcond14abs 

fixup_ppc_brcond14abs - 14-bit absolute relocation for conditional branches.

fixup_ppc_half16 

fixup_ppc_half16 - A 16-bit fixup corresponding to lo16(_foo) or ha16(_foo) for instrs like 'li' or 'addis'.

fixup_ppc_half16ds 

fixup_ppc_half16ds - A 14-bit fixup corresponding to lo16(_foo) with implied 2 zero bits for instrs like 'std'.

fixup_ppc_nofixup 

fixup_ppc_nofixup - Not a true fixup, but ties a symbol to a call to __tls_get_addr for the TLS general and local dynamic models, or inserts the thread-pointer register number.

LastTargetFixupKind 
NumTargetFixupKinds 

Definition at line 19 of file PPCFixupKinds.h.

Predicate - These are "(BI << 5) | BO" for various predicates.

Enumerator
PRED_LT 
PRED_LE 
PRED_EQ 
PRED_GE 
PRED_GT 
PRED_NE 
PRED_UN 
PRED_NU 
PRED_LT_MINUS 
PRED_LE_MINUS 
PRED_EQ_MINUS 
PRED_GE_MINUS 
PRED_GT_MINUS 
PRED_NE_MINUS 
PRED_UN_MINUS 
PRED_NU_MINUS 
PRED_LT_PLUS 
PRED_LE_PLUS 
PRED_EQ_PLUS 
PRED_GE_PLUS 
PRED_GT_PLUS 
PRED_NE_PLUS 
PRED_UN_PLUS 
PRED_NU_PLUS 
PRED_BIT_SET 
PRED_BIT_UNSET 

Definition at line 27 of file PPCPredicates.h.

Function Documentation

FastISel * llvm::PPC::createFastISel ( FunctionLoweringInfo FuncInfo,
const TargetLibraryInfo LibInfo 
)
SDValue llvm::PPC::get_VSPLTI_elt ( SDNode N,
unsigned  ByteSize,
SelectionDAG DAG 
)

get_VSPLTI_elt - If this is a build_vector of constants which can be formed by using a vspltis[bhw] instruction of the specified element size, return the constant being splatted.

The ByteSize field indicates the number of bytes of each element [124] -> [bhw].

Definition at line 1477 of file PPCISelLowering.cpp.

References llvm::MVT::f32, llvm::FloatToBits(), llvm::SDValue::getNode(), llvm::SDNode::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetConstant(), llvm::MVT::i32, llvm::SignExtend32(), and llvm::ISD::UNDEF.

int llvm::PPC::getAltVSXFMAOpcode ( uint16_t  Opcode)
int llvm::PPC::getNonRecordFormOpcode ( uint16_t  )
Predicate llvm::PPC::getSwappedPredicate ( Predicate  Opcode)

Assume the condition register is set by MI(a,b), return the predicate if we modify the instructions such that condition register is set by MI(b,a).

Referenced by llvm::PPCInstrInfo::optimizeCompareInstr(), and llvm::ICmpInst::swapOperands().

unsigned llvm::PPC::getVSPLTImmediate ( SDNode N,
unsigned  EltSize,
SelectionDAG DAG 
)

getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the specified isSplatShuffleMask VECTOR_SHUFFLE mask.

Definition at line 1463 of file PPCISelLowering.cpp.

References llvm::SelectionDAG::getDataLayout(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::DataLayout::isLittleEndian(), isSplatShuffleMask(), and N.

Predicate llvm::PPC::InvertPredicate ( Predicate  Opcode)

Invert the specified predicate. != -> ==, < -> >=.

Referenced by llvm::PPCInstrInfo::ReverseBranchCondition().

int llvm::PPC::isQVALIGNIShuffleMask ( SDNode N)

If this is a qvaligni shuffle mask, return the shift amount, otherwise return -1.

isQVALIGNIShuffleMask - If this is a qvaligni shuffle mask, return the shift amount, otherwise return -1.

Definition at line 1580 of file PPCISelLowering.cpp.

References llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDNode::getValueType(), isConstantOrUndef(), N, llvm::MVT::v4f32, llvm::MVT::v4f64, and llvm::MVT::v4i1.

bool llvm::PPC::isSplatShuffleMask ( ShuffleVectorSDNode N,
unsigned  EltSize 
)

isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand specifies a splat of a single element that is suitable for input to VSPLTB/VSPLTH/VSPLTW.

Definition at line 1429 of file PPCISelLowering.cpp.

References llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDNode::getValueType(), and llvm::MVT::v16i8.

Referenced by getVSPLTImmediate().

bool llvm::PPC::isVMRGEOShuffleMask ( ShuffleVectorSDNode N,
bool  CheckEven,
unsigned  ShuffleKind,
SelectionDAG DAG 
)

isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for a VMRGEW or VMRGOW instruction

Determine if the specified shuffle mask is suitable for the vmrgew or vmrgow instructions.

Parameters
[in]NThe shuffle vector SD Node to analyze
[in]CheckEvenCheck for an even merge (true) or an odd merge (false)
[in]ShuffleKindIdentify the type of merge:
  • 0 = big-endian merge with two different inputs;
  • 1 = either-endian merge with two identical inputs;
  • 2 = little-endian merge with two different inputs (inputs are swapped for little-endian merges).
[in]DAGThe current SelectionDAG
Returns
true iff this shuffle mask

Definition at line 1356 of file PPCISelLowering.cpp.

References llvm::SelectionDAG::getDataLayout(), llvm::DataLayout::isLittleEndian(), and isVMerge().

bool llvm::PPC::isVMRGHShuffleMask ( ShuffleVectorSDNode N,
unsigned  UnitSize,
unsigned  ShuffleKind,
SelectionDAG DAG 
)

isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for a VRGH* instruction with the specified unit size (1,2 or 4 bytes).

isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).

The ShuffleKind distinguishes between big-endian merges with two different inputs (0), either-endian merges with two identical inputs (1), and little-endian merges with two different inputs (2). For the latter, the input operands are swapped (see PPCInstrAltivec.td).

Definition at line 1266 of file PPCISelLowering.cpp.

References llvm::SelectionDAG::getDataLayout(), llvm::DataLayout::isLittleEndian(), and isVMerge().

bool llvm::PPC::isVMRGLShuffleMask ( ShuffleVectorSDNode N,
unsigned  UnitSize,
unsigned  ShuffleKind,
SelectionDAG DAG 
)

isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for a VRGL* instruction with the specified unit size (1,2 or 4 bytes).

isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).

The ShuffleKind distinguishes between big-endian merges with two different inputs (0), either-endian merges with two identical inputs (1), and little-endian merges with two different inputs (2). For the latter, the input operands are swapped (see PPCInstrAltivec.td).

Definition at line 1241 of file PPCISelLowering.cpp.

References llvm::SelectionDAG::getDataLayout(), llvm::DataLayout::isLittleEndian(), and isVMerge().

bool llvm::PPC::isVPKUDUMShuffleMask ( ShuffleVectorSDNode N,
unsigned  ShuffleKind,
SelectionDAG DAG 
)

isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a VPKUDUM instruction.

isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a VPKUDUM instruction, AND the VPKUDUM instruction exists for the current subtarget.

The ShuffleKind distinguishes between big-endian operations with two different inputs (0), either-endian operations with two identical inputs (1), and little-endian operations with two different inputs (2). For the latter, the input operands are swapped (see PPCInstrAltivec.td).

Definition at line 1173 of file PPCISelLowering.cpp.

References llvm::SelectionDAG::getDataLayout(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SelectionDAG::getSubtarget(), llvm::PPCSubtarget::hasP8Vector(), isConstantOrUndef(), and llvm::DataLayout::isLittleEndian().

bool llvm::PPC::isVPKUHUMShuffleMask ( ShuffleVectorSDNode N,
unsigned  ShuffleKind,
SelectionDAG DAG 
)

isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a VPKUHUM instruction.

The ShuffleKind distinguishes between big-endian operations with two different inputs (0), either-endian operations with two identical inputs (1), and little-endian operations with two different inputs (2). For the latter, the input operands are swapped (see PPCInstrAltivec.td).

Definition at line 1105 of file PPCISelLowering.cpp.

References llvm::SelectionDAG::getDataLayout(), llvm::ShuffleVectorSDNode::getMaskElt(), isConstantOrUndef(), and llvm::DataLayout::isLittleEndian().

bool llvm::PPC::isVPKUWUMShuffleMask ( ShuffleVectorSDNode N,
unsigned  ShuffleKind,
SelectionDAG DAG 
)

isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a VPKUWUM instruction.

The ShuffleKind distinguishes between big-endian operations with two different inputs (0), either-endian operations with two identical inputs (1), and little-endian operations with two different inputs (2). For the latter, the input operands are swapped (see PPCInstrAltivec.td).

Definition at line 1136 of file PPCISelLowering.cpp.

References llvm::SelectionDAG::getDataLayout(), llvm::ShuffleVectorSDNode::getMaskElt(), isConstantOrUndef(), and llvm::DataLayout::isLittleEndian().

int llvm::PPC::isVSLDOIShuffleMask ( SDNode N,
unsigned  ShuffleKind,
SelectionDAG DAG 
)

isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift amount, otherwise return -1.

The ShuffleKind distinguishes between big-endian operations with two different inputs (0), either-endian operations with two identical inputs (1), and little-endian operations with two different inputs (2). For the latter, the input operands are swapped (see PPCInstrAltivec.td).

Definition at line 1385 of file PPCISelLowering.cpp.

References llvm::SelectionDAG::getDataLayout(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDNode::getValueType(), isConstantOrUndef(), llvm::DataLayout::isLittleEndian(), N, and llvm::MVT::v16i8.