LLVM  3.7.0
AArch64AdvSIMDScalarPass.cpp
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1 //===-- AArch64AdvSIMDScalar.cpp - Replace dead defs w/ zero reg --===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 // When profitable, replace GPR targeting i64 instructions with their
10 // AdvSIMD scalar equivalents. Generally speaking, "profitable" is defined
11 // as minimizing the number of cross-class register copies.
12 //===----------------------------------------------------------------------===//
13 
14 //===----------------------------------------------------------------------===//
15 // TODO: Graph based predicate heuristics.
16 // Walking the instruction list linearly will get many, perhaps most, of
17 // the cases, but to do a truly thorough job of this, we need a more
18 // wholistic approach.
19 //
20 // This optimization is very similar in spirit to the register allocator's
21 // spill placement, only here we're determining where to place cross-class
22 // register copies rather than spills. As such, a similar approach is
23 // called for.
24 //
25 // We want to build up a set of graphs of all instructions which are candidates
26 // for transformation along with instructions which generate their inputs and
27 // consume their outputs. For each edge in the graph, we assign a weight
28 // based on whether there is a copy required there (weight zero if not) and
29 // the block frequency of the block containing the defining or using
30 // instruction, whichever is less. Our optimization is then a graph problem
31 // to minimize the total weight of all the graphs, then transform instructions
32 // and add or remove copy instructions as called for to implement the
33 // solution.
34 //===----------------------------------------------------------------------===//
35 
36 #include "AArch64.h"
37 #include "AArch64InstrInfo.h"
38 #include "AArch64RegisterInfo.h"
39 #include "AArch64Subtarget.h"
40 #include "llvm/ADT/Statistic.h"
47 #include "llvm/Support/Debug.h"
49 using namespace llvm;
50 
51 #define DEBUG_TYPE "aarch64-simd-scalar"
52 
53 // Allow forcing all i64 operations with equivalent SIMD instructions to use
54 // them. For stress-testing the transformation function.
55 static cl::opt<bool>
56 TransformAll("aarch64-simd-scalar-force-all",
57  cl::desc("Force use of AdvSIMD scalar instructions everywhere"),
58  cl::init(false), cl::Hidden);
59 
60 STATISTIC(NumScalarInsnsUsed, "Number of scalar instructions used");
61 STATISTIC(NumCopiesDeleted, "Number of cross-class copies deleted");
62 STATISTIC(NumCopiesInserted, "Number of cross-class copies inserted");
63 
64 namespace {
65 class AArch64AdvSIMDScalar : public MachineFunctionPass {
67  const TargetInstrInfo *TII;
68 
69 private:
70  // isProfitableToTransform - Predicate function to determine whether an
71  // instruction should be transformed to its equivalent AdvSIMD scalar
72  // instruction. "add Xd, Xn, Xm" ==> "add Dd, Da, Db", for example.
73  bool isProfitableToTransform(const MachineInstr *MI) const;
74 
75  // transformInstruction - Perform the transformation of an instruction
76  // to its equivalant AdvSIMD scalar instruction. Update inputs and outputs
77  // to be the correct register class, minimizing cross-class copies.
78  void transformInstruction(MachineInstr *MI);
79 
80  // processMachineBasicBlock - Main optimzation loop.
81  bool processMachineBasicBlock(MachineBasicBlock *MBB);
82 
83 public:
84  static char ID; // Pass identification, replacement for typeid.
85  explicit AArch64AdvSIMDScalar() : MachineFunctionPass(ID) {}
86 
87  bool runOnMachineFunction(MachineFunction &F) override;
88 
89  const char *getPassName() const override {
90  return "AdvSIMD Scalar Operation Optimization";
91  }
92 
93  void getAnalysisUsage(AnalysisUsage &AU) const override {
94  AU.setPreservesCFG();
96  }
97 };
99 } // end anonymous namespace
100 
101 static bool isGPR64(unsigned Reg, unsigned SubReg,
102  const MachineRegisterInfo *MRI) {
103  if (SubReg)
104  return false;
106  return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass);
107  return AArch64::GPR64RegClass.contains(Reg);
108 }
109 
110 static bool isFPR64(unsigned Reg, unsigned SubReg,
111  const MachineRegisterInfo *MRI) {
113  return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) &&
114  SubReg == 0) ||
115  (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) &&
116  SubReg == AArch64::dsub);
117  // Physical register references just check the register class directly.
118  return (AArch64::FPR64RegClass.contains(Reg) && SubReg == 0) ||
119  (AArch64::FPR128RegClass.contains(Reg) && SubReg == AArch64::dsub);
120 }
121 
122 // getSrcFromCopy - Get the original source register for a GPR64 <--> FPR64
123 // copy instruction. Return zero_reg if the instruction is not a copy.
124 static unsigned getSrcFromCopy(const MachineInstr *MI,
125  const MachineRegisterInfo *MRI,
126  unsigned &SubReg) {
127  SubReg = 0;
128  // The "FMOV Xd, Dn" instruction is the typical form.
129  if (MI->getOpcode() == AArch64::FMOVDXr ||
130  MI->getOpcode() == AArch64::FMOVXDr)
131  return MI->getOperand(1).getReg();
132  // A lane zero extract "UMOV.d Xd, Vn[0]" is equivalent. We shouldn't see
133  // these at this stage, but it's easy to check for.
134  if (MI->getOpcode() == AArch64::UMOVvi64 && MI->getOperand(2).getImm() == 0) {
135  SubReg = AArch64::dsub;
136  return MI->getOperand(1).getReg();
137  }
138  // Or just a plain COPY instruction. This can be directly to/from FPR64,
139  // or it can be a dsub subreg reference to an FPR128.
140  if (MI->getOpcode() == AArch64::COPY) {
141  if (isFPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(),
142  MRI) &&
143  isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI))
144  return MI->getOperand(1).getReg();
145  if (isGPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(),
146  MRI) &&
147  isFPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(),
148  MRI)) {
149  SubReg = MI->getOperand(1).getSubReg();
150  return MI->getOperand(1).getReg();
151  }
152  }
153 
154  // Otherwise, this is some other kind of instruction.
155  return 0;
156 }
157 
158 // getTransformOpcode - For any opcode for which there is an AdvSIMD equivalent
159 // that we're considering transforming to, return that AdvSIMD opcode. For all
160 // others, return the original opcode.
161 static unsigned getTransformOpcode(unsigned Opc) {
162  switch (Opc) {
163  default:
164  break;
165  // FIXME: Lots more possibilities.
166  case AArch64::ADDXrr:
167  return AArch64::ADDv1i64;
168  case AArch64::SUBXrr:
169  return AArch64::SUBv1i64;
170  case AArch64::ANDXrr:
171  return AArch64::ANDv8i8;
172  case AArch64::EORXrr:
173  return AArch64::EORv8i8;
174  case AArch64::ORRXrr:
175  return AArch64::ORRv8i8;
176  }
177  // No AdvSIMD equivalent, so just return the original opcode.
178  return Opc;
179 }
180 
181 static bool isTransformable(const MachineInstr *MI) {
182  unsigned Opc = MI->getOpcode();
183  return Opc != getTransformOpcode(Opc);
184 }
185 
186 // isProfitableToTransform - Predicate function to determine whether an
187 // instruction should be transformed to its equivalent AdvSIMD scalar
188 // instruction. "add Xd, Xn, Xm" ==> "add Dd, Da, Db", for example.
189 bool
190 AArch64AdvSIMDScalar::isProfitableToTransform(const MachineInstr *MI) const {
191  // If this instruction isn't eligible to be transformed (no SIMD equivalent),
192  // early exit since that's the common case.
193  if (!isTransformable(MI))
194  return false;
195 
196  // Count the number of copies we'll need to add and approximate the number
197  // of copies that a transform will enable us to remove.
198  unsigned NumNewCopies = 3;
199  unsigned NumRemovableCopies = 0;
200 
201  unsigned OrigSrc0 = MI->getOperand(1).getReg();
202  unsigned OrigSrc1 = MI->getOperand(2).getReg();
203  unsigned Src0 = 0, SubReg0;
204  unsigned Src1 = 0, SubReg1;
205  if (!MRI->def_empty(OrigSrc0)) {
207  MRI->def_instr_begin(OrigSrc0);
208  assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!");
209  Src0 = getSrcFromCopy(&*Def, MRI, SubReg0);
210  // If the source was from a copy, we don't need to insert a new copy.
211  if (Src0)
212  --NumNewCopies;
213  // If there are no other users of the original source, we can delete
214  // that instruction.
215  if (Src0 && MRI->hasOneNonDBGUse(OrigSrc0))
216  ++NumRemovableCopies;
217  }
218  if (!MRI->def_empty(OrigSrc1)) {
220  MRI->def_instr_begin(OrigSrc1);
221  assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!");
222  Src1 = getSrcFromCopy(&*Def, MRI, SubReg1);
223  if (Src1)
224  --NumNewCopies;
225  // If there are no other users of the original source, we can delete
226  // that instruction.
227  if (Src1 && MRI->hasOneNonDBGUse(OrigSrc1))
228  ++NumRemovableCopies;
229  }
230 
231  // If any of the uses of the original instructions is a cross class copy,
232  // that's a copy that will be removable if we transform. Likewise, if
233  // any of the uses is a transformable instruction, it's likely the tranforms
234  // will chain, enabling us to save a copy there, too. This is an aggressive
235  // heuristic that approximates the graph based cost analysis described above.
236  unsigned Dst = MI->getOperand(0).getReg();
237  bool AllUsesAreCopies = true;
239  Use = MRI->use_instr_nodbg_begin(Dst),
240  E = MRI->use_instr_nodbg_end();
241  Use != E; ++Use) {
242  unsigned SubReg;
243  if (getSrcFromCopy(&*Use, MRI, SubReg) || isTransformable(&*Use))
244  ++NumRemovableCopies;
245  // If the use is an INSERT_SUBREG, that's still something that can
246  // directly use the FPR64, so we don't invalidate AllUsesAreCopies. It's
247  // preferable to have it use the FPR64 in most cases, as if the source
248  // vector is an IMPLICIT_DEF, the INSERT_SUBREG just goes away entirely.
249  // Ditto for a lane insert.
250  else if (Use->getOpcode() == AArch64::INSERT_SUBREG ||
251  Use->getOpcode() == AArch64::INSvi64gpr)
252  ;
253  else
254  AllUsesAreCopies = false;
255  }
256  // If all of the uses of the original destination register are copies to
257  // FPR64, then we won't end up having a new copy back to GPR64 either.
258  if (AllUsesAreCopies)
259  --NumNewCopies;
260 
261  // If a transform will not increase the number of cross-class copies required,
262  // return true.
263  if (NumNewCopies <= NumRemovableCopies)
264  return true;
265 
266  // Finally, even if we otherwise wouldn't transform, check if we're forcing
267  // transformation of everything.
268  return TransformAll;
269 }
270 
272  unsigned Dst, unsigned Src, bool IsKill) {
273  MachineInstrBuilder MIB =
274  BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII->get(AArch64::COPY),
275  Dst)
276  .addReg(Src, getKillRegState(IsKill));
277  DEBUG(dbgs() << " adding copy: " << *MIB);
278  ++NumCopiesInserted;
279  return MIB;
280 }
281 
282 // transformInstruction - Perform the transformation of an instruction
283 // to its equivalant AdvSIMD scalar instruction. Update inputs and outputs
284 // to be the correct register class, minimizing cross-class copies.
285 void AArch64AdvSIMDScalar::transformInstruction(MachineInstr *MI) {
286  DEBUG(dbgs() << "Scalar transform: " << *MI);
287 
288  MachineBasicBlock *MBB = MI->getParent();
289  unsigned OldOpc = MI->getOpcode();
290  unsigned NewOpc = getTransformOpcode(OldOpc);
291  assert(OldOpc != NewOpc && "transform an instruction to itself?!");
292 
293  // Check if we need a copy for the source registers.
294  unsigned OrigSrc0 = MI->getOperand(1).getReg();
295  unsigned OrigSrc1 = MI->getOperand(2).getReg();
296  unsigned Src0 = 0, SubReg0;
297  unsigned Src1 = 0, SubReg1;
298  if (!MRI->def_empty(OrigSrc0)) {
300  MRI->def_instr_begin(OrigSrc0);
301  assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!");
302  Src0 = getSrcFromCopy(&*Def, MRI, SubReg0);
303  // If there are no other users of the original source, we can delete
304  // that instruction.
305  if (Src0 && MRI->hasOneNonDBGUse(OrigSrc0)) {
306  assert(Src0 && "Can't delete copy w/o a valid original source!");
307  Def->eraseFromParent();
308  ++NumCopiesDeleted;
309  }
310  }
311  if (!MRI->def_empty(OrigSrc1)) {
313  MRI->def_instr_begin(OrigSrc1);
314  assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!");
315  Src1 = getSrcFromCopy(&*Def, MRI, SubReg1);
316  // If there are no other users of the original source, we can delete
317  // that instruction.
318  if (Src1 && MRI->hasOneNonDBGUse(OrigSrc1)) {
319  assert(Src1 && "Can't delete copy w/o a valid original source!");
320  Def->eraseFromParent();
321  ++NumCopiesDeleted;
322  }
323  }
324  // If we weren't able to reference the original source directly, create a
325  // copy.
326  if (!Src0) {
327  SubReg0 = 0;
328  Src0 = MRI->createVirtualRegister(&AArch64::FPR64RegClass);
329  insertCopy(TII, MI, Src0, OrigSrc0, true);
330  }
331  if (!Src1) {
332  SubReg1 = 0;
333  Src1 = MRI->createVirtualRegister(&AArch64::FPR64RegClass);
334  insertCopy(TII, MI, Src1, OrigSrc1, true);
335  }
336 
337  // Create a vreg for the destination.
338  // FIXME: No need to do this if the ultimate user expects an FPR64.
339  // Check for that and avoid the copy if possible.
340  unsigned Dst = MRI->createVirtualRegister(&AArch64::FPR64RegClass);
341 
342  // For now, all of the new instructions have the same simple three-register
343  // form, so no need to special case based on what instruction we're
344  // building.
345  BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(NewOpc), Dst)
346  .addReg(Src0, getKillRegState(true), SubReg0)
347  .addReg(Src1, getKillRegState(true), SubReg1);
348 
349  // Now copy the result back out to a GPR.
350  // FIXME: Try to avoid this if all uses could actually just use the FPR64
351  // directly.
352  insertCopy(TII, MI, MI->getOperand(0).getReg(), Dst, true);
353 
354  // Erase the old instruction.
355  MI->eraseFromParent();
356 
357  ++NumScalarInsnsUsed;
358 }
359 
360 // processMachineBasicBlock - Main optimzation loop.
361 bool AArch64AdvSIMDScalar::processMachineBasicBlock(MachineBasicBlock *MBB) {
362  bool Changed = false;
363  for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E;) {
364  MachineInstr *MI = I;
365  ++I;
366  if (isProfitableToTransform(MI)) {
367  transformInstruction(MI);
368  Changed = true;
369  }
370  }
371  return Changed;
372 }
373 
374 // runOnMachineFunction - Pass entry point from PassManager.
375 bool AArch64AdvSIMDScalar::runOnMachineFunction(MachineFunction &mf) {
376  bool Changed = false;
377  DEBUG(dbgs() << "***** AArch64AdvSIMDScalar *****\n");
378 
379  MRI = &mf.getRegInfo();
380  TII = mf.getSubtarget().getInstrInfo();
381 
382  // Just check things on a one-block-at-a-time basis.
383  for (MachineFunction::iterator I = mf.begin(), E = mf.end(); I != E; ++I)
384  if (processMachineBasicBlock(I))
385  Changed = true;
386  return Changed;
387 }
388 
389 // createAArch64AdvSIMDScalar - Factory function used by AArch64TargetMachine
390 // to add the pass to the PassManager.
392  return new AArch64AdvSIMDScalar();
393 }
STATISTIC(NumFunctions,"Total number of functions")
static unsigned getSrcFromCopy(const MachineInstr *MI, const MachineRegisterInfo *MRI, unsigned &SubReg)
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
bool hasSuperClassEq(const TargetRegisterClass *RC) const
hasSuperClassEq - Returns true if RC is a super-class of or equal to this class.
F(f)
static bool isTransformable(const MachineInstr *MI)
COPY - Target-independent register copy.
Definition: TargetOpcodes.h:86
static bool isFPR64(unsigned Reg, unsigned SubReg, const MachineRegisterInfo *MRI)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
A Use represents the edge between a Value definition and its users.
Definition: Use.h:69
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
const TargetRegisterClass * getRegClass(unsigned Reg) const
getRegClass - Return the register class of the specified virtual register.
Reg
All possible values of the reg field in the ModR/M byte.
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Definition: Value.cpp:317
defusechain_iterator - This class provides iterator support for machine operands in the function that...
int64_t getImm() const
unsigned getKillRegState(bool B)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:267
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:120
TargetInstrInfo - Interface to description of machine instruction set.
bundle_iterator< MachineInstr, instr_iterator > iterator
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:325
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
static cl::opt< bool > TransformAll("aarch64-simd-scalar-force-all", cl::desc("Force use of AdvSIMD scalar instructions everywhere"), cl::init(false), cl::Hidden)
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
INSERT_SUBREG - This instruction takes three operands: a register that has subregisters, a register providing an insert value, and a subregister index.
Definition: TargetOpcodes.h:49
Represent the analysis usage information of a pass.
FunctionPass * createAArch64AdvSIMDScalar()
static unsigned getTransformOpcode(unsigned Opc)
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:294
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
unsigned getSubReg() const
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:263
static MachineInstr * insertCopy(const TargetInstrInfo *TII, MachineInstr *MI, unsigned Dst, unsigned Src, bool IsKill)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:123
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:238
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:51
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
#define I(x, y, z)
Definition: MD5.cpp:54
unsigned getReg() const
getReg - Returns the register number.
virtual const TargetInstrInfo * getInstrInfo() const
BasicBlockListType::iterator iterator
#define DEBUG(X)
Definition: Debug.h:92
static bool isGPR64(unsigned Reg, unsigned SubReg, const MachineRegisterInfo *MRI)