LLVM  3.7.0
HexagonRegisterInfo.cpp
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1 //===-- HexagonRegisterInfo.cpp - Hexagon Register Information ------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Hexagon implementation of the TargetRegisterInfo
11 // class.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "HexagonRegisterInfo.h"
16 #include "Hexagon.h"
18 #include "HexagonSubtarget.h"
19 #include "HexagonTargetMachine.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/STLExtras.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/Type.h"
33 #include "llvm/Support/Debug.h"
39 
40 using namespace llvm;
41 
43  : HexagonGenRegisterInfo(Hexagon::R31) {}
44 
45 
47  return R == Hexagon::R0 || R == Hexagon::R1 || R == Hexagon::R2 ||
48  R == Hexagon::R3 || R == Hexagon::D0 || R == Hexagon::D1;
49 }
50 
52  return Hexagon::R16 <= Reg && Reg <= Hexagon::R27;
53 }
54 
55 
56 const MCPhysReg *
58  static const MCPhysReg CallerSavedRegsV4[] = {
59  Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
60  Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9,
61  Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,
62  Hexagon::R15, 0
63  };
64 
65  auto &HST = static_cast<const HexagonSubtarget&>(MF->getSubtarget());
66  switch (HST.getHexagonArchVersion()) {
69  return CallerSavedRegsV4;
70  }
72  "Callee saved registers requested for unknown archtecture version");
73 }
74 
75 
76 const MCPhysReg *
78  static const MCPhysReg CalleeSavedRegsV3[] = {
79  Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
80  Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
81  Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0
82  };
83 
87  return CalleeSavedRegsV3;
88  }
89  llvm_unreachable("Callee saved registers requested for unknown architecture "
90  "version");
91 }
92 
94  const {
95  BitVector Reserved(getNumRegs());
96  Reserved.set(HEXAGON_RESERVED_REG_1);
97  Reserved.set(HEXAGON_RESERVED_REG_2);
98  Reserved.set(Hexagon::R29);
99  Reserved.set(Hexagon::R30);
100  Reserved.set(Hexagon::R31);
101  Reserved.set(Hexagon::D14);
102  Reserved.set(Hexagon::D15);
103  Reserved.set(Hexagon::LC0);
104  Reserved.set(Hexagon::LC1);
105  Reserved.set(Hexagon::SA0);
106  Reserved.set(Hexagon::SA1);
107  return Reserved;
108 }
109 
110 
112  int SPAdj, unsigned FIOp,
113  RegScavenger *RS) const {
114  //
115  // Hexagon_TODO: Do we need to enforce this for Hexagon?
116  assert(SPAdj == 0 && "Unexpected");
117 
118  MachineInstr &MI = *II;
119 
120  MachineBasicBlock &MB = *MI.getParent();
121  MachineFunction &MF = *MB.getParent();
122  MachineFrameInfo &MFI = *MF.getFrameInfo();
123  auto &HST = static_cast<const HexagonSubtarget&>(MF.getSubtarget());
124  auto &HII = *HST.getInstrInfo();
125  auto &HFI = *HST.getFrameLowering();
126 
127  int FI = MI.getOperand(FIOp).getIndex();
128  int Offset = MFI.getObjectOffset(FI) + MI.getOperand(FIOp+1).getImm();
129  bool HasAlloca = MFI.hasVarSizedObjects();
130  bool HasAlign = needsStackRealignment(MF);
131 
132  // XXX: Fixed objects cannot be accessed through SP if there are aligned
133  // objects in the local frame, or if there are dynamically allocated objects.
134  // In such cases, there has to be FP available.
135  if (!HFI.hasFP(MF)) {
136  assert(!HasAlloca && !HasAlign && "This function must have frame pointer");
137  // We will not reserve space on the stack for the lr and fp registers.
138  Offset -= 8;
139  }
140 
141  unsigned SP = getStackRegister(), FP = getFrameRegister();
142  unsigned AP = 0;
143  if (MachineInstr *AI = HFI.getAlignaInstr(MF))
144  AP = AI->getOperand(0).getReg();
145  unsigned FrameSize = MFI.getStackSize();
146 
147  // Special handling of dbg_value instructions and INLINEASM.
148  if (MI.isDebugValue() || MI.isInlineAsm()) {
149  MI.getOperand(FIOp).ChangeToRegister(SP, false /*isDef*/);
150  MI.getOperand(FIOp+1).ChangeToImmediate(Offset+FrameSize);
151  return;
152  }
153 
154  bool UseFP = false, UseAP = false; // Default: use SP.
155  if (MFI.isFixedObjectIndex(FI) || MFI.isObjectPreAllocated(FI)) {
156  UseFP = HasAlloca || HasAlign;
157  } else {
158  if (HasAlloca) {
159  if (HasAlign)
160  UseAP = true;
161  else
162  UseFP = true;
163  }
164  }
165 
166  unsigned Opc = MI.getOpcode();
167  bool ValidSP = HII.isValidOffset(Opc, FrameSize+Offset);
168  bool ValidFP = HII.isValidOffset(Opc, Offset);
169 
170  // Calculate the actual offset in the instruction.
171  int64_t RealOffset = Offset;
172  if (!UseFP && !UseAP)
173  RealOffset = FrameSize+Offset;
174 
175  switch (Opc) {
176  case Hexagon::TFR_FIA:
177  MI.setDesc(HII.get(Hexagon::A2_addi));
178  MI.getOperand(FIOp).ChangeToImmediate(RealOffset);
179  MI.RemoveOperand(FIOp+1);
180  return;
181  case Hexagon::TFR_FI:
182  // Set up the instruction for updating below.
183  MI.setDesc(HII.get(Hexagon::A2_addi));
184  break;
185  }
186 
187  unsigned BP = 0;
188  bool Valid = false;
189  if (UseFP) {
190  BP = FP;
191  Valid = ValidFP;
192  } else if (UseAP) {
193  BP = AP;
194  Valid = ValidFP;
195  } else {
196  BP = SP;
197  Valid = ValidSP;
198  }
199 
200  if (Valid) {
201  MI.getOperand(FIOp).ChangeToRegister(BP, false);
202  MI.getOperand(FIOp+1).ChangeToImmediate(RealOffset);
203  return;
204  }
205 
206 #ifndef NDEBUG
207  const Function *F = MF.getFunction();
208  dbgs() << "In function ";
209  if (F) dbgs() << F->getName();
210  else dbgs() << "<?>";
211  dbgs() << ", BB#" << MB.getNumber() << "\n" << MI;
212 #endif
213  llvm_unreachable("Unhandled instruction");
214 }
215 
216 
218  return Hexagon::R31;
219 }
220 
221 
223  &MF) const {
224  const HexagonFrameLowering *TFI = getFrameLowering(MF);
225  if (TFI->hasFP(MF))
226  return Hexagon::R30;
227  return Hexagon::R29;
228 }
229 
230 
232  return Hexagon::R30;
233 }
234 
235 
237  return Hexagon::R29;
238 }
239 
240 
241 bool
243  const HexagonFrameLowering *TFI = getFrameLowering(MF);
244  return TFI->hasFP(MF);
245 }
246 
247 
248 bool
250  const MachineFrameInfo *MFI = MF.getFrameInfo();
251  return MFI->getMaxAlignment() > 8;
252 }
253 
254 
256  return Hexagon::R6;
257 }
258 
259 
260 #define GET_REGINFO_TARGET_DESC
261 #include "HexagonGenRegisterInfo.inc"
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
BitVector & set()
Definition: BitVector.h:218
#define R4(n)
#define HEXAGON_RESERVED_REG_1
const HexagonArchEnum & getHexagonArchVersion() const
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
int getNumber() const
getNumber - MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a M...
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
F(f)
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
#define HEXAGON_RESERVED_REG_2
#define R2(n)
bool isObjectPreAllocated(int ObjectIdx) const
Return true if the object was pre-allocated into the local block.
StringRef getName() const
Return a constant reference to the value's name.
Definition: Value.cpp:188
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
int64_t getImm() const
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:267
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:120
const MCPhysReg * getCallerSavedRegs(const MachineFunction *MF) const
bool isDebugValue() const
Definition: MachineInstr.h:748
unsigned getFirstCallerSavedNonParamReg() const
bundle_iterator< MachineInstr, instr_iterator > iterator
bool isEHReturnCalleeSaveReg(unsigned Reg) const
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
#define R6(n)
bool isInlineAsm() const
Definition: MachineInstr.h:760
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:123
Representation of each machine instruction.
Definition: MachineInstr.h:51
bool useFPForScavengingIndex(const MachineFunction &MF) const override
Returns true if the frame pointer is valid.
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
bool needsStackRealignment(const MachineFunction &MF) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
const HexagonInstrInfo * getInstrInfo() const override
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
bool isCalleeSaveReg(unsigned Reg) const
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...