34 struct MachineOperandWithLocation {
41 : Operand(Operand), Begin(Begin), End(End) {}
81 bool parseNamedRegister(
unsigned &
Reg);
83 bool parseRegister(
unsigned &
Reg);
84 bool parseRegisterFlag(
unsigned &
Flags);
85 bool parseSubRegisterIndex(
unsigned &SubReg);
86 bool parseRegisterOperand(
MachineOperand &Dest,
bool IsDef =
false);
97 bool getUnsigned(
unsigned &Result);
99 void initNames2InstrOpCodes();
103 bool parseInstrName(
StringRef InstrName,
unsigned &OpCode);
105 bool parseInstruction(
unsigned &OpCode);
110 void initNames2Regs();
114 bool getRegisterByName(
StringRef RegName,
unsigned &
Reg);
116 void initNames2RegMasks();
121 const uint32_t *getRegMask(
StringRef Identifier);
123 void initNames2SubRegIndices();
136 : SM(SM), MF(MF), Error(Error), Source(Source), CurrentSource(Source),
139 void MIParser::lex() {
141 CurrentSource, Token,
151 SM.getMemoryBuffer(SM.getMainFileID())->getBufferIdentifier(), 1,
163 if (Token.isRegister() || Token.isRegisterFlag()) {
164 auto Loc = Token.location();
165 if (parseRegisterOperand(MO,
true))
167 Operands.
push_back(MachineOperandWithLocation(MO, Loc, Token.location()));
169 return error(
"expected '='");
174 if (Token.isError() || parseInstruction(OpCode))
181 auto Loc = Token.location();
182 if (parseMachineOperand(MO))
184 Operands.
push_back(MachineOperandWithLocation(MO, Loc, Token.location()));
188 return error(
"expected ',' before the next machine operand");
192 const auto &MCID = MF.getSubtarget().getInstrInfo()->get(OpCode);
193 if (!MCID.isVariadic()) {
195 if (verifyImplicitOperands(Operands, MCID))
200 MI = MF.CreateMachineInstr(MCID,
DebugLoc(),
true);
201 for (
const auto &Operand : Operands)
209 return error(
"expected a machine basic block reference");
215 "expected end of string after the machine basic block reference");
219 bool MIParser::parseNamedRegister(
unsigned &
Reg) {
222 return error(
"expected a named register");
223 if (parseRegister(Reg))
227 return error(
"expected end of string after the register reference");
233 return MO.
isDef() ?
"implicit-def" :
"implicit";
242 bool MIParser::verifyImplicitOperands(
252 for (
const uint16_t *ImpDefs = MCID.
getImplicitDefs(); *ImpDefs; ++ImpDefs)
256 for (
const uint16_t *ImpUses = MCID.
getImplicitUses(); *ImpUses; ++ImpUses)
260 const auto *TRI = MF.getSubtarget().getRegisterInfo();
261 assert(TRI &&
"Expected target register info");
262 size_t I = ImplicitOperands.
size(), J = Operands.
size();
267 const auto &ImplicitOperand = ImplicitOperands[
I];
268 const auto &Operand = Operands[J].Operand;
269 if (ImplicitOperand.isIdenticalTo(Operand))
271 if (Operand.isReg() && Operand.isImplicit()) {
272 return error(Operands[J].Begin,
273 Twine(
"expected an implicit register operand '") +
285 return error(J < Operands.
size() ? Operands[J].End : Token.location(),
286 Twine(
"missing implicit register operand '") +
293 bool MIParser::parseInstruction(
unsigned &OpCode) {
295 return error(
"expected a machine instruction");
296 StringRef InstrName = Token.stringValue();
297 if (parseInstrName(InstrName, OpCode))
298 return error(
Twine(
"unknown machine instruction name '") + InstrName +
"'");
303 bool MIParser::parseRegister(
unsigned &Reg) {
304 switch (Token.kind()) {
310 if (getRegisterByName(Name, Reg))
311 return error(
Twine(
"unknown register name '") + Name +
"'");
318 const auto RegInfo = PFS.VirtualRegisterSlots.find(ID);
319 if (RegInfo == PFS.VirtualRegisterSlots.end())
320 return error(
Twine(
"use of undefined virtual register '%") +
Twine(ID) +
322 Reg = RegInfo->second;
332 bool MIParser::parseRegisterFlag(
unsigned &
Flags) {
333 switch (Token.kind()) {
358 bool MIParser::parseSubRegisterIndex(
unsigned &SubReg) {
362 return error(
"expected a subregister index after ':'");
363 auto Name = Token.stringValue();
364 SubReg = getSubRegIndex(Name);
366 return error(
Twine(
"use of unknown subregister index '") + Name +
"'");
371 bool MIParser::parseRegisterOperand(
MachineOperand &Dest,
bool IsDef) {
374 while (Token.isRegisterFlag()) {
375 if (parseRegisterFlag(Flags))
378 if (!Token.isRegister())
379 return error(
"expected a register after register flags");
380 if (parseRegister(Reg))
385 if (parseSubRegisterIndex(SubReg))
397 const APSInt &
Int = Token.integerValue();
398 if (Int.getMinSignedBits() > 64)
406 bool MIParser::getUnsigned(
unsigned &Result) {
407 assert(Token.hasIntegerValue() &&
"Expected a token with an integer value");
408 const uint64_t Limit = uint64_t(std::numeric_limits<unsigned>::max()) + 1;
409 uint64_t Val64 = Token.integerValue().getLimitedValue(Limit);
411 return error(
"expected 32-bit integer (too large)");
419 if (getUnsigned(Number))
421 auto MBBInfo = PFS.MBBSlots.find(Number);
422 if (MBBInfo == PFS.MBBSlots.end())
423 return error(
Twine(
"use of undefined machine basic block #") +
425 MBB = MBBInfo->second;
426 if (!Token.stringValue().empty() && Token.stringValue() != MBB->
getName())
427 return error(
Twine(
"the name of machine basic block #") +
Twine(Number) +
428 " isn't '" + Token.stringValue() +
"'");
442 switch (Token.kind()) {
444 auto Name = Token.stringValue();
450 return error(
Twine(
"use of undefined global value '@") + Name +
"'");
454 if (getUnsigned(GVIdx))
456 if (GVIdx >= IRSlots.GlobalValues.size())
457 return error(
Twine(
"use of undefined global value '@") +
Twine(GVIdx) +
472 switch (Token.kind()) {
481 return parseRegisterOperand(Dest);
483 return parseImmediateOperand(Dest);
485 return parseMBBOperand(Dest);
488 return parseGlobalAddressOperand(Dest);
492 if (
const auto *RegMask = getRegMask(Token.stringValue())) {
500 return error(
"expected a machine operand");
505 void MIParser::initNames2InstrOpCodes() {
506 if (!Names2InstrOpCodes.empty())
508 const auto *
TII = MF.getSubtarget().getInstrInfo();
509 assert(
TII &&
"Expected target instruction info");
510 for (
unsigned I = 0, E =
TII->getNumOpcodes(); I < E; ++
I)
511 Names2InstrOpCodes.insert(std::make_pair(
StringRef(
TII->getName(I)), I));
514 bool MIParser::parseInstrName(
StringRef InstrName,
unsigned &OpCode) {
515 initNames2InstrOpCodes();
516 auto InstrInfo = Names2InstrOpCodes.find(InstrName);
517 if (InstrInfo == Names2InstrOpCodes.end())
519 OpCode = InstrInfo->getValue();
523 void MIParser::initNames2Regs() {
524 if (!Names2Regs.empty())
527 Names2Regs.insert(std::make_pair(
"noreg", 0));
528 const auto *TRI = MF.getSubtarget().getRegisterInfo();
529 assert(TRI &&
"Expected target register info");
530 for (
unsigned I = 0, E = TRI->getNumRegs(); I < E; ++
I) {
532 Names2Regs.insert(std::make_pair(
StringRef(TRI->getName(I)).lower(),
I))
535 assert(WasInserted &&
"Expected registers to be unique case-insensitively");
539 bool MIParser::getRegisterByName(
StringRef RegName,
unsigned &Reg) {
541 auto RegInfo = Names2Regs.find(RegName);
542 if (RegInfo == Names2Regs.end())
544 Reg = RegInfo->getValue();
548 void MIParser::initNames2RegMasks() {
549 if (!Names2RegMasks.empty())
551 const auto *TRI = MF.getSubtarget().getRegisterInfo();
552 assert(TRI &&
"Expected target register info");
555 assert(RegMasks.
size() == RegMaskNames.
size());
556 for (
size_t I = 0, E = RegMasks.
size(); I < E; ++
I)
557 Names2RegMasks.insert(
558 std::make_pair(
StringRef(RegMaskNames[I]).lower(), RegMasks[I]));
561 const uint32_t *MIParser::getRegMask(
StringRef Identifier) {
562 initNames2RegMasks();
563 auto RegMaskInfo = Names2RegMasks.find(Identifier);
564 if (RegMaskInfo == Names2RegMasks.end())
566 return RegMaskInfo->getValue();
569 void MIParser::initNames2SubRegIndices() {
570 if (!Names2SubRegIndices.empty())
574 Names2SubRegIndices.insert(
578 unsigned MIParser::getSubRegIndex(
StringRef Name) {
579 initNames2SubRegIndices();
580 auto SubRegInfo = Names2SubRegIndices.find(Name);
581 if (SubRegInfo == Names2SubRegIndices.end())
583 return SubRegInfo->getValue();
590 return MIParser(SM, MF, Error, Src, PFS, IRSlots).parse(MI);
597 return MIParser(SM, MF, Error, Src, PFS, IRSlots).parseMBB(MBB);
605 return MIParser(SM, MF, Error, Src, PFS, IRSlots).parseNamedRegister(Reg);
void push_back(const T &Elt)
const uint16_t * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
A Module instance is used to store all the information related to an LLVM module. ...
bool parseMachineInstr(MachineInstr *&MI, SourceMgr &SM, MachineFunction &MF, StringRef Src, const PerFunctionMIParsingState &PFS, const SlotMapping &IRSlots, SMDiagnostic &Error)
Describe properties that are true of each instruction in the target description file.
const uint16_t * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction...
StringRef lexMIToken(StringRef Source, MIToken &Token, function_ref< void(StringRef::iterator, const Twine &)> ErrorCallback)
Consume a single machine instruction token in the given source and return the remaining source string...
std::string str() const
Return the twine contents as a std::string.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
const HexagonInstrInfo * TII
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isCall() const
Return true if the instruction is a call.
Reg
All possible values of the reg field in the ModR/M byte.
const uint16_t * ImplicitUses
static MachineOperand CreateRegMask(const uint32_t *Mask)
CreateRegMask - Creates a register mask operand referencing Mask.
static std::string getRegisterName(const TargetRegisterInfo *TRI, unsigned Reg)
unsigned getNumSubRegIndices() const
Return the number of sub-register indices understood by the target.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
static std::error_code error(DiagnosticHandlerFunction DiagnosticHandler, std::error_code EC, const Twine &Message)
size_t size() const
size - Get the array size.
Function * getFunction(StringRef Name) const
Look up the specified function in the module symbol table.
static const char * printImplicitRegisterFlag(const MachineOperand &MO)
static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset, unsigned char TargetFlags=0)
This owns the files read by a parser, handles include stacks, and handles diagnostic wrangling...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Module.h This file contains the declarations for the Module class.
StringRef getName() const
getName - Return the name of the corresponding LLVM basic block, or "(null)".
bool parseMBBReference(MachineBasicBlock *&MBB, SourceMgr &SM, MachineFunction &MF, StringRef Src, const PerFunctionMIParsingState &PFS, const SlotMapping &IRSlots, SMDiagnostic &Error)
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
const char * getSubRegIndexName(unsigned SubIdx) const
getSubRegIndexName - Return the human-readable symbolic target-specific name for the specified SubReg...
bool parseNamedRegisterReference(unsigned &Reg, SourceMgr &SM, MachineFunction &MF, StringRef Src, const PerFunctionMIParsingState &PFS, const SlotMapping &IRSlots, SMDiagnostic &Error)
This struct contains the mapping from the slot numbers to unnamed metadata nodes and global values...
Representation of each machine instruction.
static bool isPhysicalRegister(unsigned Reg)
isPhysicalRegister - Return true if the specified register number is in the physical register namespa...
static MachineOperand CreateMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0)
static MachineOperand CreateImm(int64_t Val)
const uint16_t * ImplicitDefs
Module * getParent()
Get the module that this global value is contained inside of...
A token produced by the machine instruction lexer.
const char * getName(unsigned RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register...
StringRef - Represent a constant reference to a string, i.e.
Represents a location in source code.
GlobalValue * getNamedValue(StringRef Name) const
Return the global value in the module with the specified name, of arbitrary type. ...
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...