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LLVM
3.7.0
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AArch64_AM - AArch64 Addressing Mode Stuff. More...
Enumerations | |
| enum | ShiftExtendType { InvalidShiftExtend = -1, LSL = 0, LSR, ASR, ROR, MSL, UXTB, UXTH, UXTW, UXTX, SXTB, SXTH, SXTW, SXTX } |
Functions | |
| static const char * | getShiftExtendName (AArch64_AM::ShiftExtendType ST) |
| getShiftName - Get the string encoding for the shift type. More... | |
| static AArch64_AM::ShiftExtendType | getShiftType (unsigned Imm) |
| getShiftType - Extract the shift type. More... | |
| static unsigned | getShiftValue (unsigned Imm) |
| getShiftValue - Extract the shift value. More... | |
| static unsigned | getShifterImm (AArch64_AM::ShiftExtendType ST, unsigned Imm) |
| getShifterImm - Encode the shift type and amount: imm: 6-bit shift amount shifter: 000 ==> lsl 001 ==> lsr 010 ==> asr 011 ==> ror 100 ==> msl {8-6} = shifter {5-0} = imm More... | |
| static unsigned | getArithShiftValue (unsigned Imm) |
| getArithShiftValue - get the arithmetic shift value. More... | |
| static AArch64_AM::ShiftExtendType | getExtendType (unsigned Imm) |
| getExtendType - Extract the extend type for operands of arithmetic ops. More... | |
| static AArch64_AM::ShiftExtendType | getArithExtendType (unsigned Imm) |
| unsigned | getExtendEncoding (AArch64_AM::ShiftExtendType ET) |
| Mapping from extend bits to required operation: shifter: 000 ==> uxtb 001 ==> uxth 010 ==> uxtw 011 ==> uxtx 100 ==> sxtb 101 ==> sxth 110 ==> sxtw 111 ==> sxtx. More... | |
| static unsigned | getArithExtendImm (AArch64_AM::ShiftExtendType ET, unsigned Imm) |
| getArithExtendImm - Encode the extend type and shift amount for an arithmetic instruction: imm: 3-bit extend amount {5-3} = shifter {2-0} = imm3 More... | |
| static bool | getMemDoShift (unsigned Imm) |
| getMemDoShift - Extract the "do shift" flag value for load/store instructions. More... | |
| static AArch64_AM::ShiftExtendType | getMemExtendType (unsigned Imm) |
| getExtendType - Extract the extend type for the offset operand of loads/stores. More... | |
| static unsigned | getMemExtendImm (AArch64_AM::ShiftExtendType ET, bool DoShift) |
| getExtendImm - Encode the extend type and amount for a load/store inst: doshift: should the offset be scaled by the access size shifter: 000 ==> uxtb 001 ==> uxth 010 ==> uxtw 011 ==> uxtx 100 ==> sxtb 101 ==> sxth 110 ==> sxtw 111 ==> sxtx {3-1} = shifter {0} = doshift More... | |
| static uint64_t | ror (uint64_t elt, unsigned size) |
| static bool | processLogicalImmediate (uint64_t Imm, unsigned RegSize, uint64_t &Encoding) |
| processLogicalImmediate - Determine if an immediate value can be encoded as the immediate operand of a logical instruction for the given register size. More... | |
| static bool | isLogicalImmediate (uint64_t imm, unsigned regSize) |
| isLogicalImmediate - Return true if the immediate is valid for a logical immediate instruction of the given register size. More... | |
| static uint64_t | encodeLogicalImmediate (uint64_t imm, unsigned regSize) |
| encodeLogicalImmediate - Return the encoded immediate value for a logical immediate instruction of the given register size. More... | |
| static uint64_t | decodeLogicalImmediate (uint64_t val, unsigned regSize) |
| decodeLogicalImmediate - Decode a logical immediate value in the form "N:immr:imms" (where the immr and imms fields are each 6 bits) into the integer value it represents with regSize bits. More... | |
| static bool | isValidDecodeLogicalImmediate (uint64_t val, unsigned regSize) |
| isValidDecodeLogicalImmediate - Check to see if the logical immediate value in the form "N:immr:imms" (where the immr and imms fields are each 6 bits) is a valid encoding for an integer value with regSize bits. More... | |
| static float | getFPImmFloat (unsigned Imm) |
| static int | getFP32Imm (const APInt &Imm) |
| getFP32Imm - Return an 8-bit floating-point version of the 32-bit floating-point value. More... | |
| static int | getFP32Imm (const APFloat &FPImm) |
| static int | getFP64Imm (const APInt &Imm) |
| getFP64Imm - Return an 8-bit floating-point version of the 64-bit floating-point value. More... | |
| static int | getFP64Imm (const APFloat &FPImm) |
| static bool | isAdvSIMDModImmType1 (uint64_t Imm) |
| static uint8_t | encodeAdvSIMDModImmType1 (uint64_t Imm) |
| static uint64_t | decodeAdvSIMDModImmType1 (uint8_t Imm) |
| static bool | isAdvSIMDModImmType2 (uint64_t Imm) |
| static uint8_t | encodeAdvSIMDModImmType2 (uint64_t Imm) |
| static uint64_t | decodeAdvSIMDModImmType2 (uint8_t Imm) |
| static bool | isAdvSIMDModImmType3 (uint64_t Imm) |
| static uint8_t | encodeAdvSIMDModImmType3 (uint64_t Imm) |
| static uint64_t | decodeAdvSIMDModImmType3 (uint8_t Imm) |
| static bool | isAdvSIMDModImmType4 (uint64_t Imm) |
| static uint8_t | encodeAdvSIMDModImmType4 (uint64_t Imm) |
| static uint64_t | decodeAdvSIMDModImmType4 (uint8_t Imm) |
| static bool | isAdvSIMDModImmType5 (uint64_t Imm) |
| static uint8_t | encodeAdvSIMDModImmType5 (uint64_t Imm) |
| static uint64_t | decodeAdvSIMDModImmType5 (uint8_t Imm) |
| static bool | isAdvSIMDModImmType6 (uint64_t Imm) |
| static uint8_t | encodeAdvSIMDModImmType6 (uint64_t Imm) |
| static uint64_t | decodeAdvSIMDModImmType6 (uint8_t Imm) |
| static bool | isAdvSIMDModImmType7 (uint64_t Imm) |
| static uint8_t | encodeAdvSIMDModImmType7 (uint64_t Imm) |
| static uint64_t | decodeAdvSIMDModImmType7 (uint8_t Imm) |
| static bool | isAdvSIMDModImmType8 (uint64_t Imm) |
| static uint64_t | decodeAdvSIMDModImmType8 (uint8_t Imm) |
| static uint8_t | encodeAdvSIMDModImmType8 (uint64_t Imm) |
| static bool | isAdvSIMDModImmType9 (uint64_t Imm) |
| static uint8_t | encodeAdvSIMDModImmType9 (uint64_t Imm) |
| static uint64_t | decodeAdvSIMDModImmType9 (uint8_t Imm) |
| static bool | isAdvSIMDModImmType10 (uint64_t Imm) |
| static uint8_t | encodeAdvSIMDModImmType10 (uint64_t Imm) |
| static uint64_t | decodeAdvSIMDModImmType10 (uint8_t Imm) |
| static bool | isAdvSIMDModImmType11 (uint64_t Imm) |
| static uint8_t | encodeAdvSIMDModImmType11 (uint64_t Imm) |
| static uint64_t | decodeAdvSIMDModImmType11 (uint8_t Imm) |
| static bool | isAdvSIMDModImmType12 (uint64_t Imm) |
| static uint8_t | encodeAdvSIMDModImmType12 (uint64_t Imm) |
| static uint64_t | decodeAdvSIMDModImmType12 (uint8_t Imm) |
AArch64_AM - AArch64 Addressing Mode Stuff.
| Enumerator | |
|---|---|
| InvalidShiftExtend | |
| LSL | |
| LSR | |
| ASR | |
| ROR | |
| MSL | |
| UXTB | |
| UXTH | |
| UXTW | |
| UXTX | |
| SXTB | |
| SXTH | |
| SXTW | |
| SXTX | |
Definition at line 32 of file AArch64AddressingModes.h.
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Definition at line 437 of file AArch64AddressingModes.h.
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Definition at line 618 of file AArch64AddressingModes.h.
Referenced by llvm::AArch64InstPrinter::printSIMDType10Operand().
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Definition at line 667 of file AArch64AddressingModes.h.
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Definition at line 716 of file AArch64AddressingModes.h.
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Definition at line 452 of file AArch64AddressingModes.h.
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Definition at line 467 of file AArch64AddressingModes.h.
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Definition at line 482 of file AArch64AddressingModes.h.
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Definition at line 498 of file AArch64AddressingModes.h.
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Definition at line 514 of file AArch64AddressingModes.h.
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Definition at line 529 of file AArch64AddressingModes.h.
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Definition at line 540 of file AArch64AddressingModes.h.
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Definition at line 560 of file AArch64AddressingModes.h.
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decodeLogicalImmediate - Decode a logical immediate value in the form "N:immr:imms" (where the immr and imms fields are each 6 bits) into the integer value it represents with regSize bits.
Definition at line 292 of file AArch64AddressingModes.h.
References llvm::countLeadingZeros(), N, ror(), and size.
Referenced by llvm::AArch64InstrInfo::analyzeCompare(), getUsefulBitsFromAndWithImmediate(), llvm::AArch64InstPrinter::printLogicalImm32(), and llvm::AArch64InstPrinter::printLogicalImm64().
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Definition at line 433 of file AArch64AddressingModes.h.
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Definition at line 590 of file AArch64AddressingModes.h.
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Definition at line 639 of file AArch64AddressingModes.h.
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Definition at line 688 of file AArch64AddressingModes.h.
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Definition at line 448 of file AArch64AddressingModes.h.
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Definition at line 463 of file AArch64AddressingModes.h.
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Definition at line 478 of file AArch64AddressingModes.h.
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Definition at line 494 of file AArch64AddressingModes.h.
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Definition at line 510 of file AArch64AddressingModes.h.
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Definition at line 525 of file AArch64AddressingModes.h.
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Definition at line 545 of file AArch64AddressingModes.h.
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Definition at line 556 of file AArch64AddressingModes.h.
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encodeLogicalImmediate - Return the encoded immediate value for a logical immediate instruction of the given register size.
Definition at line 281 of file AArch64AddressingModes.h.
References processLogicalImmediate().
Referenced by llvm::AArch64InstrInfo::insertSelect().
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getArithExtendImm - Encode the extend type and shift amount for an arithmetic instruction: imm: 3-bit extend amount {5-3} = shifter {2-0} = imm3
Definition at line 170 of file AArch64AddressingModes.h.
References getExtendEncoding().
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Definition at line 138 of file AArch64AddressingModes.h.
References getExtendType().
Referenced by llvm::AArch64InstPrinter::printArithExtend().
getArithShiftValue - get the arithmetic shift value.
Definition at line 118 of file AArch64AddressingModes.h.
Referenced by llvm::AArch64InstPrinter::printArithExtend().
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Mapping from extend bits to required operation: shifter: 000 ==> uxtb 001 ==> uxth 010 ==> uxtw 011 ==> uxtx 100 ==> sxtb 101 ==> sxth 110 ==> sxtw 111 ==> sxtx.
Definition at line 151 of file AArch64AddressingModes.h.
References llvm_unreachable, SXTB, SXTH, SXTW, SXTX, UXTB, UXTH, UXTW, and UXTX.
Referenced by getArithExtendImm(), and getMemExtendImm().
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getExtendType - Extract the extend type for operands of arithmetic ops.
Definition at line 123 of file AArch64AddressingModes.h.
References llvm_unreachable, SXTB, SXTH, SXTW, SXTX, UXTB, UXTH, UXTW, and UXTX.
Referenced by getArithExtendType(), and getMemExtendType().
getFP32Imm - Return an 8-bit floating-point version of the 32-bit floating-point value.
If the value cannot be represented as an 8-bit floating-point value, then return -1.
Definition at line 370 of file AArch64AddressingModes.h.
References llvm::APInt::getSExtValue(), llvm::APInt::getZExtValue(), and llvm::APInt::lshr().
Referenced by getFP32Imm(), and llvm::AArch64TargetLowering::isFPImmLegal().
Definition at line 391 of file AArch64AddressingModes.h.
References llvm::APFloat::bitcastToAPInt(), and getFP32Imm().
getFP64Imm - Return an 8-bit floating-point version of the 64-bit floating-point value.
If the value cannot be represented as an 8-bit floating-point value, then return -1.
Definition at line 398 of file AArch64AddressingModes.h.
References llvm::APInt::getSExtValue(), llvm::APInt::getZExtValue(), and llvm::APInt::lshr().
Referenced by getFP64Imm(), and llvm::AArch64TargetLowering::isFPImmLegal().
Definition at line 419 of file AArch64AddressingModes.h.
References llvm::APFloat::bitcastToAPInt(), and getFP64Imm().
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Definition at line 342 of file AArch64AddressingModes.h.
Referenced by llvm::AArch64InstPrinter::printFPImmOperand().
getMemDoShift - Extract the "do shift" flag value for load/store instructions.
Definition at line 178 of file AArch64AddressingModes.h.
Referenced by llvm::AArch64InstrInfo::isScaledAddr().
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getExtendImm - Encode the extend type and amount for a load/store inst: doshift: should the offset be scaled by the access size shifter: 000 ==> uxtb 001 ==> uxth 010 ==> uxtw 011 ==> uxtx 100 ==> sxtb 101 ==> sxth 110 ==> sxtw 111 ==> sxtx {3-1} = shifter {0} = doshift
Definition at line 200 of file AArch64AddressingModes.h.
References getExtendEncoding().
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getExtendType - Extract the extend type for the offset operand of loads/stores.
Definition at line 184 of file AArch64AddressingModes.h.
References getExtendType().
Referenced by llvm::AArch64InstrInfo::isScaledAddr().
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getShifterImm - Encode the shift type and amount: imm: 6-bit shift amount shifter: 000 ==> lsl 001 ==> lsr 010 ==> asr 011 ==> ror 100 ==> msl {8-6} = shifter {5-0} = imm
Definition at line 98 of file AArch64AddressingModes.h.
References ASR, llvm_unreachable, LSL, LSR, MSL, and ROR.
Referenced by llvm::AArch64InstrInfo::copyPhysReg(), llvm::AArch64RegisterInfo::materializeFrameBaseRegister(), tryOrrMovk(), trySequenceOfOnes(), and tryToreplicateChunks().
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getShiftName - Get the string encoding for the shift type.
Definition at line 52 of file AArch64AddressingModes.h.
References ASR, llvm_unreachable, LSL, LSR, MSL, ROR, SXTB, SXTH, SXTW, SXTX, UXTB, UXTH, UXTW, and UXTX.
Referenced by llvm::AArch64InstPrinter::printArithExtend(), and llvm::AArch64InstPrinter::printShifter().
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getShiftType - Extract the shift type.
Definition at line 73 of file AArch64AddressingModes.h.
References ASR, InvalidShiftExtend, LSL, LSR, MSL, and ROR.
Referenced by getUsefulBitsFromOrWithShiftedReg(), and llvm::AArch64InstPrinter::printShifter().
getShiftValue - Extract the shift value.
Definition at line 85 of file AArch64AddressingModes.h.
Referenced by getUsefulBitsFromOrWithShiftedReg(), isMatchingUpdateInsn(), llvm::AArch64InstPrinter::printAddSubImm(), and llvm::AArch64InstPrinter::printShifter().
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Definition at line 428 of file AArch64AddressingModes.h.
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Definition at line 570 of file AArch64AddressingModes.h.
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Definition at line 632 of file AArch64AddressingModes.h.
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Definition at line 682 of file AArch64AddressingModes.h.
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Definition at line 443 of file AArch64AddressingModes.h.
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Definition at line 458 of file AArch64AddressingModes.h.
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Definition at line 473 of file AArch64AddressingModes.h.
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Definition at line 488 of file AArch64AddressingModes.h.
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Definition at line 504 of file AArch64AddressingModes.h.
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Definition at line 520 of file AArch64AddressingModes.h.
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Definition at line 535 of file AArch64AddressingModes.h.
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Definition at line 550 of file AArch64AddressingModes.h.
isLogicalImmediate - Return true if the immediate is valid for a logical immediate instruction of the given register size.
Return false otherwise.
Definition at line 274 of file AArch64AddressingModes.h.
References processLogicalImmediate().
Referenced by llvm::AArch64TTIImpl::getIntImmCost(), and llvm::AArch64TargetLowering::shouldConvertConstantLoadToIntImm().
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isValidDecodeLogicalImmediate - Check to see if the logical immediate value in the form "N:immr:imms" (where the immr and imms fields are each 6 bits) is a valid encoding for an integer value with regSize bits.
Definition at line 320 of file AArch64AddressingModes.h.
References llvm::countLeadingZeros(), N, and size.
Referenced by DecodeLogicalImmInstruction().
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processLogicalImmediate - Determine if an immediate value can be encoded as the immediate operand of a logical instruction for the given register size.
If so, return true with "encoding" set to the encoded value in the form N:immr:imms.
Definition at line 213 of file AArch64AddressingModes.h.
References llvm::countLeadingOnes(), llvm::countTrailingOnes(), llvm::countTrailingZeros(), I, llvm::isShiftedMask_64(), and N.
Referenced by canUseOrr(), encodeLogicalImmediate(), llvm::AArch64InstrInfo::genAlternativeCodeSequence(), isLogicalImmediate(), tryOrrMovk(), and trySequenceOfOnes().
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Definition at line 205 of file AArch64AddressingModes.h.
Referenced by decodeLogicalImmediate().
1.8.6