25 #define GET_INSTRINFO_CTOR_DTOR
26 #define GET_INSTRINFO_NAMED_OPS
27 #define GET_INSTRMAP_INFO
28 #include "AMDGPUGenInstrInfo.inc"
31 void AMDGPUInstrInfo::anchor() {}
41 unsigned &SrcReg,
unsigned &DstReg,
42 unsigned &SubIdx)
const {
93 unsigned SrcReg,
bool isKill,
115 int RegOpIdx = OffsetOpIdx + 1;
117 AMDGPU::OpName::chan);
120 AMDGPU::OpName::dst);
121 unsigned RegIndex = MI->getOperand(RegOpIdx).getImm();
122 unsigned Channel = MI->getOperand(ChanOpIdx).getImm();
124 unsigned OffsetReg = MI->getOperand(OffsetOpIdx).getReg();
125 if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) {
134 AMDGPU::OpName::val);
135 unsigned RegIndex = MI->getOperand(RegOpIdx).getImm();
136 unsigned Channel = MI->getOperand(ChanOpIdx).getImm();
138 unsigned OffsetReg = MI->getOperand(OffsetOpIdx).getReg();
139 if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) {
141 MI->getOperand(ValOpIdx).getReg());
174 unsigned Reg,
bool UnfoldLoad,
190 bool UnfoldLoad,
bool UnfoldStore,
191 unsigned *LoadRegIndex)
const {
211 int64_t Offset0, int64_t Offset1,
212 unsigned NumLoads)
const {
213 assert(Offset1 > Offset0 &&
214 "Second offset should be larger than first offset!");
219 return (NumLoads <= 16 && (Offset1 - Offset0) < 64);
245 std::vector<MachineOperand> &Pred)
const {
286 unsigned Reg = LI->first;
293 for (RegIndex = 0, RegEnd = IndirectRC->
getNumRegs(); RegIndex != RegEnd;
298 Offset = std::max(Offset, (
int)RegIndex);
322 default:
return Opcode;
323 case 1:
return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_1);
324 case 2:
return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_2);
325 case 3:
return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_3);
335 return getMCOpcodeGen(Opcode, (
enum Subtarget)Gen);
365 if (MCOp == (uint16_t)-1)
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
int getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const
Given a MIMG Opcode that writes all 4 channels, return the equivalent opcode that writes Channels Cha...
bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override
unsigned getRegister(unsigned i) const
getRegister - Return the specified register in the class.
livein_iterator livein_end() const
#define AMDGPU_FLAG_REGISTER_STORE
unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const override
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
#define AMDGPU_FLAG_REGISTER_LOAD
bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override
unsigned getNumObjects() const
Return the number of objects.
AMDGPUInstrInfo(const AMDGPUSubtarget &st)
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool DefinesPredicate(MachineInstr *MI, std::vector< MachineOperand > &Pred) const override
bool hasStoreFromStackSlot(const MachineInstr *MI, const MachineMemOperand *&MMO, int &FrameIndex) const
bool ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
int pseudoToMCOpcode(int Opcode) const
Return a target-specific opcode if Opcode is a pseudo instruction.
MachineMemOperand - A description of a memory reference used in the backend.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const AMDGPUSubtarget & ST
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
bool isPredicated(const MachineInstr *MI) const override
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
virtual const AMDGPURegisterInfo & getRegisterInfo() const =0
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
static int getMCOpcode(uint16_t Opcode, unsigned Gen)
unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const override
unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const override
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
TargetRegisterInfo interface that is implemented by all hw codegen targets.
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
bool canFoldMemoryOperand(const MachineInstr *MI, ArrayRef< unsigned > Ops) const override
Generation getGeneration() const
MachineInstr * convertToThreeAddress(MachineFunction::iterator &MFI, MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const override
static enum SISubtarget AMDGPUSubtargetToSISubtarget(unsigned Gen)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
virtual unsigned calculateIndirectAddress(unsigned RegIndex, unsigned Channel) const =0
Calculate the "Indirect Address" for the given RegIndex and Channel.
bundle_iterator< MachineInstr, instr_iterator > iterator
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex) const override
bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override
virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned ValueReg, unsigned Address, unsigned OffsetReg) const =0
Build instruction(s) for an indirect register write.
bool hasLoadFromStackSlot(const MachineInstr *MI, const MachineMemOperand *&MMO, int &FrameIndex) const override
bool isRegisterLoad(const MachineInstr &MI) const
bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override
bool isPredicable(MachineInstr *MI) const override
bool enableClusterLoads() const override
virtual const TargetRegisterClass * getIndirectAddrRegClass() const =0
virtual MachineInstr * buildMovInstr(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned DstReg, unsigned SrcReg) const =0
Build a MOV instruction.
The AMDGPU TargetMachine interface definition for hw codgen targets.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetFrameLowering * getFrameLowering() const
virtual int getFrameIndexOffset(const MachineFunction &MF, int FI) const
getFrameIndexOffset - Returns the displacement from the frame register to the stack frame of the spec...
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
unsigned isStoreFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
livein_iterator livein_begin() const
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Represents one node in the SelectionDAG.
unsigned isStoreFromStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const
unsigned getNumRegs() const
getNumRegs - Return the number of registers in this class.
int getIndirectIndexEnd(const MachineFunction &MF) const
Contains the definition of a TargetInstrInfo class that is common to all AMD GPUs.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool isRegisterStore(const MachineInstr &MI) const
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
std::vector< std::pair< unsigned, unsigned > >::const_iterator livein_iterator
bool livein_empty() const
int getIndirectIndexBegin(const MachineFunction &MF) const
BasicBlockListType::iterator iterator
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex)
virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned ValueReg, unsigned Address, unsigned OffsetReg) const =0
Build instruction(s) for an indirect register read.
bool contains(unsigned Reg) const
contains - Return true if the specified register is included in this register class.