14 #ifndef LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
15 #define LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
24 #define GET_INSTRINFO_HEADER
25 #include "ARMGenInstrInfo.inc"
29 class ARMBaseRegisterInfo;
39 unsigned LoadImmOpc,
unsigned LoadOpc,
70 RegSubRegPairAndIdx &InputReg)
const override;
86 RegSubRegPair &BaseReg,
87 RegSubRegPairAndIdx &InsertedReg)
const override;
116 bool AllowModify =
false)
const override;
141 std::vector<MachineOperand> &Pred)
const override;
159 unsigned SrcReg,
bool KillSrc,
162 unsigned DestReg,
bool KillSrc,
166 DebugLoc DL,
unsigned DestReg,
unsigned SrcReg,
167 bool KillSrc)
const override;
184 unsigned DestReg,
unsigned SubIdx,
192 bool=
false)
const override;
195 unsigned SubIdx,
unsigned State,
207 int64_t &Offset2)
const override;
218 int64_t Offset1, int64_t Offset2,
219 unsigned NumLoads)
const override;
226 unsigned NumCycles,
unsigned ExtraPredCycles,
231 unsigned NumF,
unsigned ExtraF,
236 return NumCycles == 1;
247 unsigned &SrcReg2,
int &CmpMask,
248 int &CmpValue)
const override;
255 unsigned SrcReg2,
int CmpMask,
int CmpValue,
260 unsigned &TrueOp,
unsigned &FalseOp,
261 bool &Optimizable)
const override;
265 bool)
const override;
278 unsigned UseIdx)
const override;
280 SDNode *DefNode,
unsigned DefIdx,
281 SDNode *UseNode,
unsigned UseIdx)
const override;
284 std::pair<uint16_t, uint16_t>
297 unsigned getInstBundleLength(
const MachineInstr *MI)
const;
302 unsigned DefIdx,
unsigned DefAlign)
const;
306 unsigned DefIdx,
unsigned DefAlign)
const;
310 unsigned UseIdx,
unsigned UseAlign)
const;
314 unsigned UseIdx,
unsigned UseAlign)
const;
317 unsigned DefIdx,
unsigned DefAlign,
319 unsigned UseIdx,
unsigned UseAlign)
const;
321 unsigned getPredicationCost(
const MachineInstr *MI)
const override;
325 unsigned *PredCost =
nullptr)
const override;
328 SDNode *Node)
const override;
334 unsigned UseIdx)
const override;
337 unsigned DefIdx)
const override;
361 return MLxEntryMap.
count(Opcode);
368 unsigned &AddSubOpc,
bool &NegAcc,
369 bool &HasLane)
const;
375 return MLxHazardOpcodes.
count(Opcode);
395 bool isDead =
false) {
406 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
411 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
416 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd ||
417 Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
422 return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
426 return Opc == ARM::tPOP_RET || Opc == ARM::LDMIA_RET ||
427 Opc == ARM::t2LDMIA_RET || Opc == ARM::tPOP || Opc == ARM::LDMIA_UPD ||
428 Opc == ARM::t2LDMIA_UPD || Opc == ARM::VLDMDIA_UPD;
432 return Opc == ARM::tPUSH || Opc == ARM::t2STMDB_UPD ||
433 Opc == ARM::STMDB_UPD || Opc == ARM::VSTMDDB_UPD;
447 const MachineRegisterInfo &MRI);
459 unsigned DestReg,
unsigned BaseReg,
int NumBytes,
461 const ARMBaseInstrInfo &
TII,
unsigned MIFlags = 0);
465 unsigned DestReg,
unsigned BaseReg,
int NumBytes,
467 const ARMBaseInstrInfo &
TII,
unsigned MIFlags = 0);
470 unsigned DestReg,
unsigned BaseReg,
471 int NumBytes,
const TargetInstrInfo &
TII,
472 const ARMBaseRegisterInfo& MRI,
473 unsigned MIFlags = 0);
481 MachineFunction &MF, MachineInstr *
MI,
489 unsigned FrameReg,
int &Offset,
490 const ARMBaseInstrInfo &
TII);
493 unsigned FrameReg,
int &Offset,
494 const ARMBaseInstrInfo &
TII);
ARMCC::CondCodes getPredicate(const MachineInstr *MI) const
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
bool getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const override
Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
MachineInstr * duplicate(MachineInstr *Orig, MachineFunction &MF) const override
Describe properties that are true of each instruction in the target description file.
unsigned getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr *MI) const override
void emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
std::pair< uint16_t, uint16_t > getExecutionDomain(const MachineInstr *MI) const override
VFP/NEON execution domains.
bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const override
optimizeCompareInstr - Convert the instruction to set the zero flag so that we can remove a "comparis...
virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const
GetInstSize - Returns the size of the specified MachineInstr.
bool produceSameValue(const MachineInstr *MI0, const MachineInstr *MI1, const MachineRegisterInfo *MRI) const override
bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget, MachineFunction &MF, MachineInstr *MI, unsigned NumBytes)
Tries to add registers to the reglist of a given base-updating push/pop instruction to adjust the sta...
unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const override
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
static const MachineInstrBuilder & AddNoT1CC(const MachineInstrBuilder &MIB)
static const MachineInstrBuilder & AddDefaultPred(const MachineInstrBuilder &MIB)
Provide an instruction scheduling machine model to CodeGen passes.
const HexagonInstrInfo * TII
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, DebugLoc DL) const override
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const ARMBaseInstrInfo &TII)
rewriteARMFrameIndex / rewriteT2FrameIndex - Rewrite MI to access 'Offset' bytes from the FP...
Reg
All possible values of the reg field in the ModR/M byte.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override
shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction w...
bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const ARMBaseInstrInfo &TII)
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
bool isFpMLxInstruction(unsigned Opcode) const
isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS instruction.
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, const BranchProbability &Probability) const override
bool canCauseFpMLxStall(unsigned Opcode) const
canCauseFpMLxStall - Return true if an instruction of the specified opcode will cause stalls when sch...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
bool PredicateInstruction(MachineInstr *MI, ArrayRef< MachineOperand > Pred) const override
Itinerary data supplied by a subtarget to be used by a target.
unsigned getMatchingCondBranchOpcode(unsigned Opc)
static bool isCondBranchOpcode(int Opc)
unsigned getDeadRegState(bool B)
unsigned getDefRegState(bool B)
bundle_iterator< MachineInstr, instr_iterator > iterator
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are lo...
ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg)
getInstrPredicate - If instruction is predicated, returns its predicate condition, otherwise returns AL.
bool isSchedulingBoundary(const MachineInstr *MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
bundle_iterator - MachineBasicBlock iterator that automatically skips over MIs that are inside bundle...
const MachineOperand & getOperand(unsigned i) const
bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
static bool isJumpTableBranchOpcode(int Opc)
void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags=0)
void copyFromCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, bool KillSrc, const ARMSubtarget &Subtarget) const
unsigned convertAddSubFlagsOpcode(unsigned OldOpc)
Map pseudo instructions that imply an 'S' bit onto real opcodes.
MachineInstr * commuteInstruction(MachineInstr *, bool=false) const override
commuteInstruction - Handle commutable instructions.
MachineInstr * optimizeSelect(MachineInstr *MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool) const override
void breakPartialRegDependency(MachineBasicBlock::iterator, unsigned, const TargetRegisterInfo *TRI) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of instructions to materializea des...
unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const override
bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const override
analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if h...
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
static const MachineInstrBuilder & AddDefaultCC(const MachineInstrBuilder &MIB)
static bool isIndirectBranchOpcode(int Opc)
static bool isUncondBranchOpcode(int Opc)
virtual unsigned getUnindexedOpcode(unsigned Opc) const =0
unsigned RemoveBranch(MachineBasicBlock &MBB) const override
bool isSwiftFastImmShift(const MachineInstr *MI) const
Returns true if the instruction has a shift by immediate that can be executed in one cycle less...
Represents one node in the SelectionDAG.
static bool isPushOpcode(int Opc)
size_type count(const KeyT &Val) const
Return 1 if the specified key is in the map, 0 otherwise.
void copyToCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool KillSrc, const ARMSubtarget &Subtarget) const
bool isPredicable(MachineInstr *MI) const override
isPredicable - Return true if the specified instruction can be predicated.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
unsigned canFoldARMInstrIntoMOVCC(unsigned Reg, MachineInstr *&MI, const MachineRegisterInfo &MRI)
Determine if MI can be folded into an ARM MOVCC instruction, and return the opcode of the SSA instruc...
bool DefinesPredicate(MachineInstr *MI, std::vector< MachineOperand > &Pred) const override
ARMBaseInstrInfo(const ARMSubtarget &STI)
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, const BranchProbability &Probability) const override
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
TargetSubtargetInfo - Generic base class for all target subtargets.
bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, unsigned Reg, MachineRegisterInfo *MRI) const override
FoldImmediate - 'Reg' is known to be defined by a move immediate instruction, try to fold the immedia...
static bool isPopOpcode(int Opc)
Representation of each machine instruction.
bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const override
Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx.
unsigned getNumLDMAddresses(const MachineInstr *MI) const
Get the number of addresses by LDM or VLDM or zero for unknown.
bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override
bool isPredicated(const MachineInstr *MI) const override
bool getRegSequenceLikeInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const override
Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx.
int getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const override
bool analyzeSelect(const MachineInstr *MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const override
unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const override
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
virtual const ARMBaseRegisterInfo & getRegisterInfo() const =0
unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const override
BasicBlockListType::iterator iterator
const ARMSubtarget & getSubtarget() const
StringRef - Represent a constant reference to a string, i.e.
unsigned getPartialRegUpdateClearance(const MachineInstr *, unsigned, const TargetRegisterInfo *) const override
void expandLoadStackGuardBase(MachineBasicBlock::iterator MI, unsigned LoadImmOpc, unsigned LoadOpc, Reloc::Model RM) const
void setExecutionDomain(MachineInstr *MI, unsigned Domain) const override
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
static const MachineInstrBuilder & AddDefaultT1CC(const MachineInstrBuilder &MIB, bool isDead=false)
const MachineInstrBuilder & AddDReg(MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI) const
MachineInstr * convertToThreeAddress(MachineFunction::iterator &MFI, MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const override
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SubIdx, const MachineInstr *Orig, const TargetRegisterInfo &TRI) const override