27 #define DEBUG_TYPE "si-shrink-instructions"
30 "Number of 64-bit instruction reduced to 32-bit.");
32 "Number of literal constants folded into 32-bit instructions.");
52 const char *getPassName()
const override {
53 return "SI Shrink Instructions";
65 "SI Lower il Copies",
false,
false)
69 char SIShrinkInstructions::
ID = 0;
72 return new SIShrinkInstructions();
99 default:
return false;
101 case AMDGPU::V_MAC_F32_e64:
102 if (!
isVGPR(Src2, TRI, MRI) ||
107 case AMDGPU::V_CNDMASK_B32_e64:
116 if (Src1 && (!
isVGPR(Src1, TRI, MRI) || (Src1Mod && Src1Mod->
getImm() != 0)))
160 if (Src0.isReg() && !
isVGPR(&Src0, TRI, MRI))
164 if (Src0.isReg() && MRI.
hasOneUse(Src0.getReg())) {
165 unsigned Reg = Src0.getReg();
169 bool ConstantFolded =
false;
173 ConstantFolded =
true;
175 if (ConstantFolded) {
178 ++NumLiteralConstantsFolded;
195 std::vector<unsigned> I1Defs;
202 for (I = MBB.
begin(); I != MBB.
end(); I = Next) {
207 if (MI.
getOpcode() == AMDGPU::S_MOV_B32) {
212 MI.
setDesc(TII->get(AMDGPU::S_MOVK_I32));
254 if (DstReg != AMDGPU::VCC)
258 if (Op32 == AMDGPU::V_CNDMASK_B32_e32) {
265 unsigned SReg = Src2->
getReg();
270 if (SReg != AMDGPU::VCC)
288 Inst32.addOperand(*Src1);
293 Inst32.addOperand(*Src2);
295 ++NumInstructionsShrunk;
299 DEBUG(
dbgs() <<
"e32 MI = " << *Inst32 <<
'\n');
AMDGPU specific subclass of TargetSubtarget.
static bool canShrink(MachineInstr &MI, const SIInstrInfo *TII, const SIRegisterInfo &TRI, const MachineRegisterInfo &MRI)
FunctionPass * createSIShrinkInstructionsPass()
const SIRegisterInfo & getRegisterInfo() const override
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
bool hasVGPRs(const TargetRegisterClass *RC) const
MachineInstr * commuteInstruction(MachineInstr *MI, bool NewMI=false) const override
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
MachineOperand * getNamedOperand(MachineInstr &MI, unsigned OperandName) const
Returns the operand named Op.
const TargetRegisterClass * getRegClass(unsigned Reg) const
getRegClass - Return the register class of the specified virtual register.
Reg
All possible values of the reg field in the ModR/M byte.
static bool isVGPR(const MachineOperand *MO, const SIRegisterInfo &TRI, const MachineRegisterInfo &MRI)
#define DEBUG_TYPE
The pass tries to use the 32-bit encoding for instructions when possible.
INITIALIZE_PASS_BEGIN(SIShrinkInstructions, DEBUG_TYPE,"SI Lower il Copies", false, false) INITIALIZE_PASS_END(SIShrinkInstructions
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
bundle_iterator< MachineInstr, instr_iterator > iterator
STATISTIC(NumInstructionsShrunk,"Number of 64-bit instruction reduced to 32-bit.")
unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const
Return the size in bytes of the operand OpNo on the given.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const MachineOperand & getOperand(unsigned i) const
Represent the analysis usage information of a pass.
FunctionPass class - This class is used to implement most global optimizations.
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
void initializeSIShrinkInstructionsPass(PassRegistry &)
bool isLiteralConstant(const MachineOperand &MO, unsigned OpSize) const
int getVOPe32(uint16_t Opcode)
bool isVOP1(uint16_t Opcode) const
bool isInlineConstant(const APInt &Imm) const
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
bool hasVALU32BitEncoding(unsigned Opcode) const
Return true if this 64-bit VALU instruction has a 32-bit encoding.
MachineOperand class - Representation of each machine instruction operand.
void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg)
setRegAllocationHint - Specify a register allocation hint for the specified virtual register...
bool hasOneUse(unsigned RegNo) const
hasOneUse - Return true if there is exactly one instruction using the specified register.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
bool isVOP2(uint16_t Opcode) const
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
bool isUInt< 32 >(uint64_t x)
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
const TargetRegisterClass * getPhysRegClass(unsigned Reg) const
Return the 'base' register class for this register.
Representation of each machine instruction.
Interface definition for SIInstrInfo.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool isInt< 16 >(int64_t x)
unsigned getReg() const
getReg - Returns the register number.
bool isCommutable(QueryType Type=IgnoreBundle) const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged.
virtual const TargetInstrInfo * getInstrInfo() const
bool hasModifiersSet(const MachineInstr &MI, unsigned OpName) const
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
BasicBlockListType::iterator iterator
bool isVOPC(uint16_t Opcode) const
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex)
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
static void foldImmediates(MachineInstr &MI, const SIInstrInfo *TII, MachineRegisterInfo &MRI, bool TryToCommute=true)
This function checks MI for operands defined by a move immediate instruction and then folds the liter...
bool isMoveImmediate(QueryType Type=IgnoreBundle) const
Return true if this instruction is a move immediate (including conditional moves) instruction...
bool use_empty(unsigned RegNo) const
use_empty - Return true if there are no instructions using the specified register.