35 SIMCCodeEmitter(
const SIMCCodeEmitter &) =
delete;
36 void operator=(
const SIMCCodeEmitter &) =
delete;
42 bool isSrcOperand(
const MCInstrDesc &Desc,
unsigned OpNo)
const;
45 uint32_t getLitEncoding(
const MCOperand &MO,
unsigned OpSize)
const;
50 : MCII(mcii), MRI(mri), Ctx(ctx) { }
52 ~SIMCCodeEmitter()
override {}
66 unsigned getSOPPBrEncoding(
const MCInst &
MI,
unsigned OpNo,
76 return new SIMCCodeEmitter(MCII, MRI, Ctx);
79 bool SIMCCodeEmitter::isSrcOperand(
const MCInstrDesc &Desc,
80 unsigned OpNo)
const {
89 template <
typename IntTy>
91 if (Imm >= 0 && Imm <= 64)
94 if (Imm >= -16 && Imm <= -1)
164 uint32_t SIMCCodeEmitter::getLitEncoding(
const MCOperand &MO,
165 unsigned OpSize)
const {
186 uint64_t Encoding = getBinaryCodeForInstr(MI, Fixups, STI);
188 unsigned bytes = Desc.
getSize();
190 for (
unsigned i = 0; i < bytes; i++) {
191 OS.
write((uint8_t) ((Encoding >> (8 * i)) & 0xff));
201 if (!isSrcOperand(Desc, i))
209 if (getLitEncoding(Op, RC.
getSize()) != 255)
220 for (
unsigned j = 0; j < 4; j++) {
221 OS.
write((uint8_t) ((Imm >> (8 * j)) & 0xff));
229 unsigned SIMCCodeEmitter::getSOPPBrEncoding(
const MCInst &MI,
unsigned OpNo,
241 return getMachineOpValue(MI, MO, Fixups, STI);
244 uint64_t SIMCCodeEmitter::getMachineOpValue(
const MCInst &MI,
249 return MRI.getEncodingValue(MO.
getReg());
275 if (isSrcOperand(Desc, OpNo)) {
279 uint32_t Enc = getLitEncoding(MO, RC.
getSize());
280 if (Enc != ~0U && (Enc != 255 || Desc.
getSize() == 4))
283 }
else if (MO.
isImm())
fixup for offset from instruction to end of text section
void push_back(const T &Elt)
MCCodeEmitter * createSIMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
const MCSymbol & getSymbol() const
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
#define END_OF_TEXT_LABEL_NAME
Describe properties that are true of each instruction in the target description file.
fixup for global addresses with constant initializers
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Base class for the full range of assembler expressions which are needed for parsing.
Represent a reference to a symbol from inside an expression.
Context object for machine code objects.
uint8_t OperandType
Information about the type of the operand.
unsigned getReg() const
Returns the register number.
Operand with register or inline constant.
MCRegisterClass - Base class of TargetRegisterClass.
Instances of this class represent a single low-level machine instruction.
uint32_t FloatToBits(float Float)
FloatToBits - This function takes a float and returns the bit equivalent 32-bit integer.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
const MCExpr * getExpr() const
MCCodeEmitter - Generic instruction encoding interface.
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Interface to description of machine instruction set.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
static uint32_t getIntInlineImmEncoding(IntTy Imm)
unsigned getSize() const
getSize - Return the size of the register in bytes, which is also the size of a stack slot allocated ...
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
raw_ostream & write(unsigned char C)
uint64_t DoubleToBits(double Double)
DoubleToBits - This function takes a double and returns the bit equivalent 64-bit integer...
unsigned getOpcode() const
Provides AMDGPU specific target descriptions.
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
unsigned getNumOperands() const
16-bit PC relative fixup for SOPP branch instructions.
APFloat abs(APFloat X)
Returns the absolute value of the argument.
MCSubtargetInfo - Generic base class for all target subtargets.
CodeEmitter interface for R600 and SI codegen.
Operand with register or 32-bit immediate.
static uint32_t getLit64Encoding(uint64_t Val)
static uint32_t getLit32Encoding(uint32_t Val)
const ARM::ArchExtKind Kind
const MCOperandInfo * OpInfo
This class implements an extremely fast bulk output stream that can only output to a stream...
StringRef - Represent a constant reference to a string, i.e.
Instances of this class represent operands of the MCInst class.
const MCOperand & getOperand(unsigned i) const