LLVM  3.7.0
XCoreInstrInfo.cpp
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1 //===-- XCoreInstrInfo.cpp - XCore Instruction Information ----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the XCore implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "XCoreInstrInfo.h"
15 #include "XCore.h"
17 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/IR/Constants.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/MC/MCContext.h"
25 #include "llvm/Support/Debug.h"
28 
29 using namespace llvm;
30 
31 #define GET_INSTRINFO_CTOR_DTOR
32 #include "XCoreGenInstrInfo.inc"
33 
34 namespace llvm {
35 namespace XCore {
36 
37  // XCore Condition Codes
38  enum CondCode {
42  };
43 }
44 }
45 
46 // Pin the vtable to this file.
47 void XCoreInstrInfo::anchor() {}
48 
50  : XCoreGenInstrInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
51  RI() {
52 }
53 
54 static bool isZeroImm(const MachineOperand &op) {
55  return op.isImm() && op.getImm() == 0;
56 }
57 
58 /// isLoadFromStackSlot - If the specified machine instruction is a direct
59 /// load from a stack slot, return the virtual or physical register number of
60 /// the destination along with the FrameIndex of the loaded stack slot. If
61 /// not, return 0. This predicate must return 0 if the instruction has
62 /// any side effects other than loading from the stack slot.
63 unsigned
65  int Opcode = MI->getOpcode();
66  if (Opcode == XCore::LDWFI)
67  {
68  if ((MI->getOperand(1).isFI()) && // is a stack slot
69  (MI->getOperand(2).isImm()) && // the imm is zero
70  (isZeroImm(MI->getOperand(2))))
71  {
72  FrameIndex = MI->getOperand(1).getIndex();
73  return MI->getOperand(0).getReg();
74  }
75  }
76  return 0;
77 }
78 
79  /// isStoreToStackSlot - If the specified machine instruction is a direct
80  /// store to a stack slot, return the virtual or physical register number of
81  /// the source reg along with the FrameIndex of the loaded stack slot. If
82  /// not, return 0. This predicate must return 0 if the instruction has
83  /// any side effects other than storing to the stack slot.
84 unsigned
86  int &FrameIndex) const {
87  int Opcode = MI->getOpcode();
88  if (Opcode == XCore::STWFI)
89  {
90  if ((MI->getOperand(1).isFI()) && // is a stack slot
91  (MI->getOperand(2).isImm()) && // the imm is zero
92  (isZeroImm(MI->getOperand(2))))
93  {
94  FrameIndex = MI->getOperand(1).getIndex();
95  return MI->getOperand(0).getReg();
96  }
97  }
98  return 0;
99 }
100 
101 //===----------------------------------------------------------------------===//
102 // Branch Analysis
103 //===----------------------------------------------------------------------===//
104 
105 static inline bool IsBRU(unsigned BrOpc) {
106  return BrOpc == XCore::BRFU_u6
107  || BrOpc == XCore::BRFU_lu6
108  || BrOpc == XCore::BRBU_u6
109  || BrOpc == XCore::BRBU_lu6;
110 }
111 
112 static inline bool IsBRT(unsigned BrOpc) {
113  return BrOpc == XCore::BRFT_ru6
114  || BrOpc == XCore::BRFT_lru6
115  || BrOpc == XCore::BRBT_ru6
116  || BrOpc == XCore::BRBT_lru6;
117 }
118 
119 static inline bool IsBRF(unsigned BrOpc) {
120  return BrOpc == XCore::BRFF_ru6
121  || BrOpc == XCore::BRFF_lru6
122  || BrOpc == XCore::BRBF_ru6
123  || BrOpc == XCore::BRBF_lru6;
124 }
125 
126 static inline bool IsCondBranch(unsigned BrOpc) {
127  return IsBRF(BrOpc) || IsBRT(BrOpc);
128 }
129 
130 static inline bool IsBR_JT(unsigned BrOpc) {
131  return BrOpc == XCore::BR_JT
132  || BrOpc == XCore::BR_JT32;
133 }
134 
135 /// GetCondFromBranchOpc - Return the XCore CC that matches
136 /// the correspondent Branch instruction opcode.
137 static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc)
138 {
139  if (IsBRT(BrOpc)) {
140  return XCore::COND_TRUE;
141  } else if (IsBRF(BrOpc)) {
142  return XCore::COND_FALSE;
143  } else {
144  return XCore::COND_INVALID;
145  }
146 }
147 
148 /// GetCondBranchFromCond - Return the Branch instruction
149 /// opcode that matches the cc.
150 static inline unsigned GetCondBranchFromCond(XCore::CondCode CC)
151 {
152  switch (CC) {
153  default: llvm_unreachable("Illegal condition code!");
154  case XCore::COND_TRUE : return XCore::BRFT_lru6;
155  case XCore::COND_FALSE : return XCore::BRFF_lru6;
156  }
157 }
158 
159 /// GetOppositeBranchCondition - Return the inverse of the specified
160 /// condition, e.g. turning COND_E to COND_NE.
162 {
163  switch (CC) {
164  default: llvm_unreachable("Illegal condition code!");
165  case XCore::COND_TRUE : return XCore::COND_FALSE;
166  case XCore::COND_FALSE : return XCore::COND_TRUE;
167  }
168 }
169 
170 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
171 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
172 /// implemented for a target). Upon success, this returns false and returns
173 /// with the following information in various cases:
174 ///
175 /// 1. If this block ends with no branches (it just falls through to its succ)
176 /// just return false, leaving TBB/FBB null.
177 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
178 /// the destination block.
179 /// 3. If this block ends with an conditional branch and it falls through to
180 /// an successor block, it sets TBB to be the branch destination block and a
181 /// list of operands that evaluate the condition. These
182 /// operands can be passed to other TargetInstrInfo methods to create new
183 /// branches.
184 /// 4. If this block ends with an conditional branch and an unconditional
185 /// block, it returns the 'true' destination in TBB, the 'false' destination
186 /// in FBB, and a list of operands that evaluate the condition. These
187 /// operands can be passed to other TargetInstrInfo methods to create new
188 /// branches.
189 ///
190 /// Note that RemoveBranch and InsertBranch must be implemented to support
191 /// cases where this method returns success.
192 ///
193 bool
195  MachineBasicBlock *&FBB,
197  bool AllowModify) const {
198  // If the block has no terminators, it just falls into the block after it.
200  if (I == MBB.end())
201  return false;
202 
203  if (!isUnpredicatedTerminator(I))
204  return false;
205 
206  // Get the last instruction in the block.
207  MachineInstr *LastInst = I;
208 
209  // If there is only one terminator instruction, process it.
210  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
211  if (IsBRU(LastInst->getOpcode())) {
212  TBB = LastInst->getOperand(0).getMBB();
213  return false;
214  }
215 
216  XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
217  if (BranchCode == XCore::COND_INVALID)
218  return true; // Can't handle indirect branch.
219 
220  // Conditional branch
221  // Block ends with fall-through condbranch.
222 
223  TBB = LastInst->getOperand(1).getMBB();
224  Cond.push_back(MachineOperand::CreateImm(BranchCode));
225  Cond.push_back(LastInst->getOperand(0));
226  return false;
227  }
228 
229  // Get the instruction before it if it's a terminator.
230  MachineInstr *SecondLastInst = I;
231 
232  // If there are three terminators, we don't know what sort of block this is.
233  if (SecondLastInst && I != MBB.begin() &&
234  isUnpredicatedTerminator(--I))
235  return true;
236 
237  unsigned SecondLastOpc = SecondLastInst->getOpcode();
238  XCore::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc);
239 
240  // If the block ends with conditional branch followed by unconditional,
241  // handle it.
242  if (BranchCode != XCore::COND_INVALID
243  && IsBRU(LastInst->getOpcode())) {
244 
245  TBB = SecondLastInst->getOperand(1).getMBB();
246  Cond.push_back(MachineOperand::CreateImm(BranchCode));
247  Cond.push_back(SecondLastInst->getOperand(0));
248 
249  FBB = LastInst->getOperand(0).getMBB();
250  return false;
251  }
252 
253  // If the block ends with two unconditional branches, handle it. The second
254  // one is not executed, so remove it.
255  if (IsBRU(SecondLastInst->getOpcode()) &&
256  IsBRU(LastInst->getOpcode())) {
257  TBB = SecondLastInst->getOperand(0).getMBB();
258  I = LastInst;
259  if (AllowModify)
260  I->eraseFromParent();
261  return false;
262  }
263 
264  // Likewise if it ends with a branch table followed by an unconditional branch.
265  if (IsBR_JT(SecondLastInst->getOpcode()) && IsBRU(LastInst->getOpcode())) {
266  I = LastInst;
267  if (AllowModify)
268  I->eraseFromParent();
269  return true;
270  }
271 
272  // Otherwise, can't handle this.
273  return true;
274 }
275 
276 unsigned
278  MachineBasicBlock *FBB,
280  DebugLoc DL)const{
281  // Shouldn't be a fall through.
282  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
283  assert((Cond.size() == 2 || Cond.size() == 0) &&
284  "Unexpected number of components!");
285 
286  if (!FBB) { // One way branch.
287  if (Cond.empty()) {
288  // Unconditional branch
289  BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(TBB);
290  } else {
291  // Conditional branch.
292  unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
293  BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
294  .addMBB(TBB);
295  }
296  return 1;
297  }
298 
299  // Two-way Conditional branch.
300  assert(Cond.size() == 2 && "Unexpected number of components!");
301  unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
302  BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
303  .addMBB(TBB);
304  BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(FBB);
305  return 2;
306 }
307 
308 unsigned
311  if (I == MBB.end())
312  return 0;
313 
314  if (!IsBRU(I->getOpcode()) && !IsCondBranch(I->getOpcode()))
315  return 0;
316 
317  // Remove the branch.
318  I->eraseFromParent();
319 
320  I = MBB.end();
321 
322  if (I == MBB.begin()) return 1;
323  --I;
324  if (!IsCondBranch(I->getOpcode()))
325  return 1;
326 
327  // Remove the branch.
328  I->eraseFromParent();
329  return 2;
330 }
331 
334  unsigned DestReg, unsigned SrcReg,
335  bool KillSrc) const {
336  bool GRDest = XCore::GRRegsRegClass.contains(DestReg);
337  bool GRSrc = XCore::GRRegsRegClass.contains(SrcReg);
338 
339  if (GRDest && GRSrc) {
340  BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg)
341  .addReg(SrcReg, getKillRegState(KillSrc))
342  .addImm(0);
343  return;
344  }
345 
346  if (GRDest && SrcReg == XCore::SP) {
347  BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg).addImm(0);
348  return;
349  }
350 
351  if (DestReg == XCore::SP && GRSrc) {
352  BuildMI(MBB, I, DL, get(XCore::SETSP_1r))
353  .addReg(SrcReg, getKillRegState(KillSrc));
354  return;
355  }
356  llvm_unreachable("Impossible reg-to-reg copy");
357 }
358 
361  unsigned SrcReg, bool isKill,
362  int FrameIndex,
363  const TargetRegisterClass *RC,
364  const TargetRegisterInfo *TRI) const
365 {
366  DebugLoc DL;
367  if (I != MBB.end() && !I->isDebugValue())
368  DL = I->getDebugLoc();
369  MachineFunction *MF = MBB.getParent();
370  const MachineFrameInfo &MFI = *MF->getFrameInfo();
371  MachineMemOperand *MMO =
374  MFI.getObjectSize(FrameIndex),
375  MFI.getObjectAlignment(FrameIndex));
376  BuildMI(MBB, I, DL, get(XCore::STWFI))
377  .addReg(SrcReg, getKillRegState(isKill))
378  .addFrameIndex(FrameIndex)
379  .addImm(0)
380  .addMemOperand(MMO);
381 }
382 
385  unsigned DestReg, int FrameIndex,
386  const TargetRegisterClass *RC,
387  const TargetRegisterInfo *TRI) const
388 {
389  DebugLoc DL;
390  if (I != MBB.end() && !I->isDebugValue())
391  DL = I->getDebugLoc();
392  MachineFunction *MF = MBB.getParent();
393  const MachineFrameInfo &MFI = *MF->getFrameInfo();
394  MachineMemOperand *MMO =
397  MFI.getObjectSize(FrameIndex),
398  MFI.getObjectAlignment(FrameIndex));
399  BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg)
400  .addFrameIndex(FrameIndex)
401  .addImm(0)
402  .addMemOperand(MMO);
403 }
404 
405 /// ReverseBranchCondition - Return the inverse opcode of the
406 /// specified Branch instruction.
407 bool XCoreInstrInfo::
409  assert((Cond.size() == 2) &&
410  "Invalid XCore branch condition!");
411  Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm()));
412  return false;
413 }
414 
415 static inline bool isImmU6(unsigned val) {
416  return val < (1 << 6);
417 }
418 
419 static inline bool isImmU16(unsigned val) {
420  return val < (1 << 16);
421 }
422 
423 static bool isImmMskBitp(unsigned val) {
424  if (!isMask_32(val)) {
425  return false;
426  }
427  int N = Log2_32(val) + 1;
428  return (N >= 1 && N <= 8) || N == 16 || N == 24 || N == 32;
429 }
430 
432  MachineBasicBlock &MBB,
434  unsigned Reg, uint64_t Value) const {
435  DebugLoc dl;
436  if (MI != MBB.end() && !MI->isDebugValue())
437  dl = MI->getDebugLoc();
438  if (isImmMskBitp(Value)) {
439  int N = Log2_32(Value) + 1;
440  return BuildMI(MBB, MI, dl, get(XCore::MKMSK_rus), Reg)
441  .addImm(N)
442  .getInstr();
443  }
444  if (isImmU16(Value)) {
445  int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
446  return BuildMI(MBB, MI, dl, get(Opcode), Reg).addImm(Value).getInstr();
447  }
449  const Constant *C = ConstantInt::get(
450  Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Value);
451  unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
452  return BuildMI(MBB, MI, dl, get(XCore::LDWCP_lru6), Reg)
454  .getInstr();
455 }
The memory access reads data.
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
unsigned RemoveBranch(MachineBasicBlock &MBB) const override
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
The memory access writes data.
static bool IsBRT(unsigned BrOpc)
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:223
bool ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
ReverseBranchCondition - Return the inverse opcode of the specified Branch instruction.
MachineBasicBlock * getMBB() const
static bool isImmMskBitp(unsigned val)
unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const override
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot...
A debug info location.
Definition: DebugLoc.h:34
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
static XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC)
GetOppositeBranchCondition - Return the inverse of the specified condition, e.g.
#define op(i)
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, unsigned f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
getMachineMemOperand - Allocate a new MachineMemOperand.
static MachinePointerInfo getFixedStack(int FI, int64_t offset=0)
getFixedStack - Return a MachinePointerInfo record that refers to the the specified FrameIndex...
MachineMemOperand - A description of a memory reference used in the backend.
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
static bool IsBRF(unsigned BrOpc)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APInt.h:33
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, DebugLoc DL) const override
bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
AnalyzeBranch - Analyze the branching code at the end of MBB, returning true if it cannot be understo...
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: ArrayRef.h:31
iterator getLastNonDebugInstr()
getLastNonDebugInstr - returns an iterator to the last non-debug instruction in the basic block...
int64_t getImm() const
static bool IsBRU(unsigned BrOpc)
static bool isImmU16(unsigned val)
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:134
unsigned getKillRegState(bool B)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:267
bundle_iterator< MachineInstr, instr_iterator > iterator
static bool isImmU6(unsigned val)
This is an important base class in LLVM.
Definition: Constant.h:41
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
MachineBasicBlock::iterator loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Reg, uint64_t Value) const
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:129
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
static unsigned GetCondBranchFromCond(XCore::CondCode CC)
GetCondBranchFromCond - Return the Branch instruction opcode that matches the cc. ...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
MachineOperand class - Representation of each machine instruction operand.
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:582
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const MachineInstrBuilder & addFrameIndex(int Idx) const
unsigned Log2_32(uint32_t Value)
Log2_32 - This function returns the floor log base 2 of the specified value, -1 if the value is zero...
Definition: MathExtras.h:468
static bool IsCondBranch(unsigned BrOpc)
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
bool isMask_32(uint32_t Value)
isMask_32 - This function returns true if the argument is a non-empty sequence of ones starting at th...
Definition: MathExtras.h:328
unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot...
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:542
Representation of each machine instruction.
Definition: MachineInstr.h:51
static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc)
GetCondFromBranchOpc - Return the XCore CC that matches the correspondent Branch instruction opcode...
static IntegerType * getInt32Ty(LLVMContext &C)
Definition: Type.cpp:239
const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned char TargetFlags=0) const
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
static MachineOperand CreateImm(int64_t Val)
#define I(x, y, z)
Definition: MD5.cpp:54
#define N
unsigned getReg() const
getReg - Returns the register number.
LLVM Value Representation.
Definition: Value.h:69
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
static bool IsBR_JT(unsigned BrOpc)
static bool isZeroImm(const MachineOperand &op)
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
unsigned getConstantPoolIndex(const Constant *C, unsigned Alignment)
getConstantPoolIndex - Create a new entry in the constant pool or return an existing one...
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly. ...