LLVM  3.7.0
CalcSpillWeights.cpp
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1 //===------------------------ CalcSpillWeights.cpp ------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
16 #include "llvm/Support/Debug.h"
21 using namespace llvm;
22 
23 #define DEBUG_TYPE "calcspillweights"
24 
26  MachineFunction &MF,
27  const MachineLoopInfo &MLI,
28  const MachineBlockFrequencyInfo &MBFI,
30  DEBUG(dbgs() << "********** Compute Spill Weights **********\n"
31  << "********** Function: " << MF.getName() << '\n');
32 
33  MachineRegisterInfo &MRI = MF.getRegInfo();
34  VirtRegAuxInfo VRAI(MF, LIS, MLI, MBFI, norm);
35  for (unsigned i = 0, e = MRI.getNumVirtRegs(); i != e; ++i) {
37  if (MRI.reg_nodbg_empty(Reg))
38  continue;
40  }
41 }
42 
43 // Return the preferred allocation register for reg, given a COPY instruction.
44 static unsigned copyHint(const MachineInstr *mi, unsigned reg,
45  const TargetRegisterInfo &tri,
46  const MachineRegisterInfo &mri) {
47  unsigned sub, hreg, hsub;
48  if (mi->getOperand(0).getReg() == reg) {
49  sub = mi->getOperand(0).getSubReg();
50  hreg = mi->getOperand(1).getReg();
51  hsub = mi->getOperand(1).getSubReg();
52  } else {
53  sub = mi->getOperand(1).getSubReg();
54  hreg = mi->getOperand(0).getReg();
55  hsub = mi->getOperand(0).getSubReg();
56  }
57 
58  if (!hreg)
59  return 0;
60 
62  return sub == hsub ? hreg : 0;
63 
64  const TargetRegisterClass *rc = mri.getRegClass(reg);
65 
66  // Only allow physreg hints in rc.
67  if (sub == 0)
68  return rc->contains(hreg) ? hreg : 0;
69 
70  // reg:sub should match the physreg hreg.
71  return tri.getMatchingSuperReg(hreg, sub, rc);
72 }
73 
74 // Check if all values in LI are rematerializable
75 static bool isRematerializable(const LiveInterval &LI,
76  const LiveIntervals &LIS,
77  const TargetInstrInfo &TII) {
79  I != E; ++I) {
80  const VNInfo *VNI = *I;
81  if (VNI->isUnused())
82  continue;
83  if (VNI->isPHIDef())
84  return false;
85 
87  assert(MI && "Dead valno in interval");
88 
90  return false;
91  }
92  return true;
93 }
94 
95 void
97  MachineRegisterInfo &mri = MF.getRegInfo();
98  const TargetRegisterInfo &tri = *MF.getSubtarget().getRegisterInfo();
99  MachineBasicBlock *mbb = nullptr;
100  MachineLoop *loop = nullptr;
101  bool isExiting = false;
102  float totalWeight = 0;
103  unsigned numInstr = 0; // Number of instructions using li
105 
106  // Find the best physreg hint and the best virtreg hint.
107  float bestPhys = 0, bestVirt = 0;
108  unsigned hintPhys = 0, hintVirt = 0;
109 
110  // Don't recompute a target specific hint.
111  bool noHint = mri.getRegAllocationHint(li.reg).first != 0;
112 
113  // Don't recompute spill weight for an unspillable register.
114  bool Spillable = li.isSpillable();
115 
117  I = mri.reg_instr_begin(li.reg), E = mri.reg_instr_end();
118  I != E; ) {
119  MachineInstr *mi = &*(I++);
120  numInstr++;
121  if (mi->isIdentityCopy() || mi->isImplicitDef() || mi->isDebugValue())
122  continue;
123  if (!visited.insert(mi).second)
124  continue;
125 
126  float weight = 1.0f;
127  if (Spillable) {
128  // Get loop info for mi.
129  if (mi->getParent() != mbb) {
130  mbb = mi->getParent();
131  loop = Loops.getLoopFor(mbb);
132  isExiting = loop ? loop->isLoopExiting(mbb) : false;
133  }
134 
135  // Calculate instr weight.
136  bool reads, writes;
137  std::tie(reads, writes) = mi->readsWritesVirtualRegister(li.reg);
139  writes, reads, &MBFI, mi);
140 
141  // Give extra weight to what looks like a loop induction variable update.
142  if (writes && isExiting && LIS.isLiveOutOfMBB(li, mbb))
143  weight *= 3;
144 
145  totalWeight += weight;
146  }
147 
148  // Get allocation hints from copies.
149  if (noHint || !mi->isCopy())
150  continue;
151  unsigned hint = copyHint(mi, li.reg, tri, mri);
152  if (!hint)
153  continue;
154  // Force hweight onto the stack so that x86 doesn't add hidden precision,
155  // making the comparison incorrectly pass (i.e., 1 > 1 == true??).
156  //
157  // FIXME: we probably shouldn't use floats at all.
158  volatile float hweight = Hint[hint] += weight;
160  if (hweight > bestPhys && mri.isAllocatable(hint))
161  bestPhys = hweight, hintPhys = hint;
162  } else {
163  if (hweight > bestVirt)
164  bestVirt = hweight, hintVirt = hint;
165  }
166  }
167 
168  Hint.clear();
169 
170  // Always prefer the physreg hint.
171  if (unsigned hint = hintPhys ? hintPhys : hintVirt) {
172  mri.setRegAllocationHint(li.reg, 0, hint);
173  // Weakly boost the spill weight of hinted registers.
174  totalWeight *= 1.01F;
175  }
176 
177  // If the live interval was already unspillable, leave it that way.
178  if (!Spillable)
179  return;
180 
181  // Mark li as unspillable if all live ranges are tiny.
182  if (li.isZeroLength(LIS.getSlotIndexes())) {
183  li.markNotSpillable();
184  return;
185  }
186 
187  // If all of the definitions of the interval are re-materializable,
188  // it is a preferred candidate for spilling.
189  // FIXME: this gets much more complicated once we support non-trivial
190  // re-materialization.
191  if (isRematerializable(li, LIS, *MF.getSubtarget().getInstrInfo()))
192  totalWeight *= 0.5F;
193 
194  li.weight = normalize(totalWeight, li.getSize(), numInstr);
195 }
Calculate auxiliary information for a virtual register such as its spill weight and allocation hint...
const unsigned reg
Definition: LiveInterval.h:616
SlotIndex def
The index of the defining instruction.
Definition: LiveInterval.h:53
static unsigned index2VirtReg(unsigned Index)
index2VirtReg - Convert a 0-based index to a virtual register number.
vni_iterator vni_begin()
Definition: LiveInterval.h:213
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:588
bool isSpillable() const
isSpillable - Can this interval be spilled?
Definition: LiveInterval.h:716
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
bool isLiveOutOfMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const
MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...
bool isLoopExiting(const BlockT *BB) const
isLoopExiting - True if terminator in the block can branch to another block that is outside of the cu...
Definition: LoopInfo.h:152
void calculateSpillWeightsAndHints(LiveIntervals &LIS, MachineFunction &MF, const MachineLoopInfo &MLI, const MachineBlockFrequencyInfo &MBFI, VirtRegAuxInfo::NormalizingFn norm=normalizeSpillWeight)
Compute spill weights and allocation hints for all virtual register live intervals.
VNInfo - Value Number Information.
Definition: LiveInterval.h:45
static bool isRematerializable(const LiveInterval &LI, const LiveIntervals &LIS, const TargetInstrInfo &TII)
float(* NormalizingFn)(float, unsigned, unsigned)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const HexagonInstrInfo * TII
std::pair< bool, bool > readsWritesVirtualRegister(unsigned Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg...
const TargetRegisterClass * getRegClass(unsigned Reg) const
getRegClass - Return the register class of the specified virtual register.
Reg
All possible values of the reg field in the ModR/M byte.
unsigned getSize() const
getSize - Returns the sum of sizes of all the LiveRange's.
bool isUnused() const
Returns true if this value is unused.
Definition: LiveInterval.h:77
static reg_instr_iterator reg_instr_end()
defusechain_iterator - This class provides iterator support for machine operands in the function that...
static bool sub(uint64_t *dest, const uint64_t *x, const uint64_t *y, unsigned len)
Subtracts the integer array y from the integer array x.
Definition: APInt.cpp:265
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
getMatchingSuperReg - Return a super-register of the specified register Reg so its sub-register of in...
VNInfoList::const_iterator const_vni_iterator
Definition: LiveInterval.h:216
static unsigned copyHint(const MachineInstr *mi, unsigned reg, const TargetRegisterInfo &tri, const MachineRegisterInfo &mri)
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:120
TargetInstrInfo - Interface to description of machine instruction set.
bool isDebugValue() const
Definition: MachineInstr.h:748
bool isImplicitDef() const
Definition: MachineInstr.h:759
MachineLoop * getLoopFor(const MachineBasicBlock *BB) const
getLoopFor - Return the inner most loop that BB lives in.
#define rc(i)
SlotIndexes * getSlotIndexes() const
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:264
bool isCopy() const
Definition: MachineInstr.h:778
reg_instr_iterator reg_instr_begin(unsigned RegNo) const
static float getSpillWeight(bool isDef, bool isUse, const MachineBlockFrequencyInfo *MBFI, const MachineInstr *Instr)
unsigned getSubReg() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isPHIDef() const
Returns true if this value is defined by a PHI instruction (or was, PHI instructions may have been el...
Definition: LiveInterval.h:74
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
Definition: SmallPtrSet.h:299
void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg)
setRegAllocationHint - Specify a register allocation hint for the specified virtual register...
void calculateSpillWeightAndHint(LiveInterval &li)
(re)compute li's spill weight and allocation hint.
bool isIdentityCopy() const
Return true is the instruction is an identity copy.
Definition: MachineInstr.h:795
bool isTriviallyReMaterializable(const MachineInstr *MI, AliasAnalysis *AA=nullptr) const
Return true if the instruction is trivially rematerializable, meaning it has no side effects and requ...
bool isAllocatable(unsigned PhysReg) const
isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn't been...
void markNotSpillable()
markNotSpillable - Mark interval as not spillable
Definition: LiveInterval.h:721
LiveInterval & getInterval(unsigned Reg)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:123
bool isZeroLength(SlotIndexes *Indexes) const
Returns true if the live range is zero length, i.e.
Definition: LiveInterval.h:538
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:51
static bool isPhysicalRegister(unsigned Reg)
isPhysicalRegister - Return true if the specified register number is in the physical register namespa...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
#define I(x, y, z)
Definition: MD5.cpp:54
unsigned getReg() const
getReg - Returns the register number.
virtual const TargetInstrInfo * getInstrInfo() const
AliasAnalysis * getAliasAnalysis() const
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
#define DEBUG(X)
Definition: Debug.h:92
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
std::pair< unsigned, unsigned > getRegAllocationHint(unsigned VReg) const
getRegAllocationHint - Return the register allocation hint for the specified virtual register...
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
vni_iterator vni_end()
Definition: LiveInterval.h:214
bool contains(unsigned Reg) const
contains - Return true if the specified register is included in this register class.