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LLVM
3.7.0
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#include <TargetRegisterInfo.h>
Public Types | |
| typedef const MCPhysReg * | iterator |
| typedef const MCPhysReg * | const_iterator |
| typedef const MVT::SimpleValueType * | vt_iterator |
| typedef const TargetRegisterClass *const * | sc_iterator |
Public Member Functions | |
| unsigned | getID () const |
| getID() - Return the register class ID number. More... | |
| iterator | begin () const |
| begin/end - Return all of the registers in this class. More... | |
| iterator | end () const |
| unsigned | getNumRegs () const |
| getNumRegs - Return the number of registers in this class. More... | |
| unsigned | getRegister (unsigned i) const |
| getRegister - Return the specified register in the class. More... | |
| bool | contains (unsigned Reg) const |
| contains - Return true if the specified register is included in this register class. More... | |
| bool | contains (unsigned Reg1, unsigned Reg2) const |
| contains - Return true if both registers are in this class. More... | |
| unsigned | getSize () const |
| getSize - Return the size of the register in bytes, which is also the size of a stack slot allocated to hold a spilled copy of this register. More... | |
| unsigned | getAlignment () const |
| getAlignment - Return the minimum required alignment for a register of this class. More... | |
| int | getCopyCost () const |
| getCopyCost - Return the cost of copying a value between two registers in this class. More... | |
| bool | isAllocatable () const |
| isAllocatable - Return true if this register class may be used to create virtual registers. More... | |
| bool | hasType (MVT vt) const |
| hasType - return true if this TargetRegisterClass has the ValueType vt. More... | |
| vt_iterator | vt_begin () const |
| vt_begin / vt_end - Loop over all of the value types that can be represented by values in this register class. More... | |
| vt_iterator | vt_end () const |
| bool | hasSubClass (const TargetRegisterClass *RC) const |
| hasSubClass - return true if the specified TargetRegisterClass is a proper sub-class of this TargetRegisterClass. More... | |
| bool | hasSubClassEq (const TargetRegisterClass *RC) const |
| hasSubClassEq - Returns true if RC is a sub-class of or equal to this class. More... | |
| bool | hasSuperClass (const TargetRegisterClass *RC) const |
| hasSuperClass - return true if the specified TargetRegisterClass is a proper super-class of this TargetRegisterClass. More... | |
| bool | hasSuperClassEq (const TargetRegisterClass *RC) const |
| hasSuperClassEq - Returns true if RC is a super-class of or equal to this class. More... | |
| const uint32_t * | getSubClassMask () const |
| getSubClassMask - Returns a bit vector of subclasses, including this one. More... | |
| const uint16_t * | getSuperRegIndices () const |
| getSuperRegIndices - Returns a 0-terminated list of sub-register indices that project some super-register class into this register class. More... | |
| sc_iterator | getSuperClasses () const |
| getSuperClasses - Returns a NULL terminated list of super-classes. More... | |
| bool | isASubClass () const |
| isASubClass - return true if this TargetRegisterClass is a subset class of at least one other TargetRegisterClass. More... | |
| ArrayRef< MCPhysReg > | getRawAllocationOrder (const MachineFunction &MF) const |
| getRawAllocationOrder - Returns the preferred order for allocating registers from this register class in MF. More... | |
| unsigned | getLaneMask () const |
| Returns the combination of all lane masks of register in this class. More... | |
Public Attributes | |
| const MCRegisterClass * | MC |
| const vt_iterator | VTs |
| const uint32_t * | SubClassMask |
| const uint16_t * | SuperRegIndices |
| const unsigned | LaneMask |
| const uint8_t | AllocationPriority |
| Classes with a higher priority value are assigned first by register allocators using a greedy heuristic. More... | |
| const bool | HasDisjunctSubRegs |
| Whether the class supports two (or more) disjunct subregister indices. More... | |
| const sc_iterator | SuperClasses |
| ArrayRef< MCPhysReg >(* | OrderFunc )(const MachineFunction &) |
Definition at line 36 of file TargetRegisterInfo.h.
Definition at line 39 of file TargetRegisterInfo.h.
Definition at line 38 of file TargetRegisterInfo.h.
Definition at line 41 of file TargetRegisterInfo.h.
Definition at line 40 of file TargetRegisterInfo.h.
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begin/end - Return all of the registers in this class.
Definition at line 63 of file TargetRegisterInfo.h.
References llvm::MCRegisterClass::begin(), and MC.
Referenced by llvm::PPCInstrInfo::DefinesPredicate(), llvm::RegScavenger::FindUnusedReg(), llvm::SIRegisterInfo::findUnusedRegister(), getRawAllocationOrder(), llvm::BitTracker::MachineEvaluator::getRegBitWidth(), llvm::TargetLowering::getRegForInlineAsmConstraint(), GetRegistersForValue(), llvm::RegScavenger::getRegsAvailable(), and llvm::ARMBaseRegisterInfo::getReservedRegs().
contains - Return true if the specified register is included in this register class.
This does not include virtual registers.
Definition at line 78 of file TargetRegisterInfo.h.
References llvm::MCRegisterClass::contains(), and MC.
Referenced by llvm::MachineFunction::addLiveIn(), canFoldCopy(), llvm::SystemZInstrInfo::convertToThreeAddress(), copyHint(), llvm::PPCInstrInfo::DefinesPredicate(), llvm::AMDGPUInstrInfo::getIndirectIndexBegin(), llvm::TargetRegisterInfo::getMinimalPhysRegClass(), llvm::PPCInstrInfo::insertSelect(), llvm::CoalescerPair::setRegisters(), UpdateOperandRegClass(), and llvm::SIInstrInfo::verifyInstruction().
contains - Return true if both registers are in this class.
Definition at line 83 of file TargetRegisterInfo.h.
References llvm::MCRegisterClass::contains(), and MC.
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Definition at line 64 of file TargetRegisterInfo.h.
References llvm::MCRegisterClass::end(), and MC.
Referenced by llvm::PPCInstrInfo::DefinesPredicate(), llvm::RegScavenger::FindUnusedReg(), llvm::SIRegisterInfo::findUnusedRegister(), llvm::BitTracker::MachineEvaluator::getRegBitWidth(), llvm::TargetLowering::getRegForInlineAsmConstraint(), GetRegistersForValue(), llvm::RegScavenger::getRegsAvailable(), and llvm::ARMBaseRegisterInfo::getReservedRegs().
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getAlignment - Return the minimum required alignment for a register of this class.
Definition at line 93 of file TargetRegisterInfo.h.
References llvm::MCRegisterClass::getAlignment(), and MC.
Referenced by llvm::PPCFrameLowering::addScavengingSpillSlot(), llvm::HexagonFrameLowering::assignCalleeSavedSpillSlots(), llvm::X86FrameLowering::assignCalleeSavedSpillSlots(), llvm::MipsFunctionInfo::createEhDataRegsFI(), llvm::XCoreFunctionInfo::createEHSpillSlot(), llvm::XCoreFunctionInfo::createFPSpillSlot(), llvm::XCoreFunctionInfo::createLRSpillSlot(), llvm::MipsSEFrameLowering::determineCalleeSaves(), llvm::HexagonFrameLowering::determineCalleeSaves(), llvm::ARMFrameLowering::determineCalleeSaves(), llvm::AArch64FrameLowering::determineCalleeSaves(), llvm::MipsFunctionInfo::getMoveF64ViaSpillFI(), and llvm::XCoreFrameLowering::processFunctionBeforeFrameFinalized().
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getCopyCost - Return the cost of copying a value between two registers in this class.
A negative number means the register class is very expensive to copy e.g. status flag register classes.
Definition at line 98 of file TargetRegisterInfo.h.
References llvm::MCRegisterClass::getCopyCost(), and MC.
Referenced by CheckForPhysRegDependency().
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getID() - Return the register class ID number.
Definition at line 59 of file TargetRegisterInfo.h.
References llvm::MCRegisterClass::getID(), and MC.
Referenced by llvm::RegsForValue::AddInlineAsmOperands(), GetCostForDef(), llvm::X86RegisterInfo::getLargestLegalSuperClass(), llvm::ARMBaseRegisterInfo::getLargestLegalSuperClass(), llvm::MipsRegisterInfo::getRegPressureLimit(), llvm::PPCRegisterInfo::getRegPressureLimit(), llvm::X86RegisterInfo::getRegPressureLimit(), llvm::AArch64RegisterInfo::getRegPressureLimit(), llvm::ARMBaseRegisterInfo::getRegPressureLimit(), hasSubClassEq(), INITIALIZE_PASS(), llvm::ResourcePriorityQueue::rawRegPressureDelta(), llvm::ResourcePriorityQueue::regPressureDelta(), and llvm::ResourcePriorityQueue::scheduledNode().
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Returns the combination of all lane masks of register in this class.
The lane masks of the registers are the combination of all lane masks of their subregisters.
Definition at line 203 of file TargetRegisterInfo.h.
References LaneMask.
Referenced by llvm::MachineRegisterInfo::getMaxLaneMaskForVReg().
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getNumRegs - Return the number of registers in this class.
Definition at line 68 of file TargetRegisterInfo.h.
References llvm::MCRegisterClass::getNumRegs(), and MC.
Referenced by llvm::RegisterClassInfo::computePSetLimit(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::AMDGPUInstrInfo::getIndirectIndexBegin(), and getRawAllocationOrder().
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getRawAllocationOrder - Returns the preferred order for allocating registers from this register class in MF.
The raw order comes directly from the .td file and may include reserved registers that are not allocatable. Register allocators should also make sure to allocate callee-saved registers only after all the volatiles are used. The RegisterClassInfo class provides filtered allocation orders with callee-saved registers moved to the end.
The MachineFunction argument can be used to tune the allocatable registers based on the characteristics of the function, subtarget, or other criteria.
By default, this method returns all registers in the class.
Definition at line 196 of file TargetRegisterInfo.h.
References begin(), getNumRegs(), llvm::makeArrayRef(), and OrderFunc.
Referenced by getAllocatableSetForRC().
getRegister - Return the specified register in the class.
Definition at line 72 of file TargetRegisterInfo.h.
References llvm::MCRegisterClass::getRegister(), and MC.
Referenced by llvm::AMDGPUInstrInfo::expandPostRAPseudo(), llvm::AMDGPUInstrInfo::getIndirectIndexBegin(), llvm::SIRegisterInfo::getPhysRegSubReg(), and llvm::SITargetLowering::getRegForInlineAsmConstraint().
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getSize - Return the size of the register in bytes, which is also the size of a stack slot allocated to hold a spilled copy of this register.
Definition at line 89 of file TargetRegisterInfo.h.
References llvm::MCRegisterClass::getSize(), and MC.
Referenced by llvm::DwarfExpression::AddMachineRegPiece(), llvm::PPCFrameLowering::addScavengingSpillSlot(), llvm::HexagonFrameLowering::assignCalleeSavedSpillSlots(), llvm::X86FrameLowering::assignCalleeSavedSpillSlots(), llvm::MipsFunctionInfo::createEhDataRegsFI(), llvm::XCoreFunctionInfo::createEHSpillSlot(), llvm::XCoreFunctionInfo::createFPSpillSlot(), llvm::XCoreFunctionInfo::createLRSpillSlot(), llvm::MipsSEFrameLowering::determineCalleeSaves(), llvm::HexagonFrameLowering::determineCalleeSaves(), llvm::ARMFrameLowering::determineCalleeSaves(), llvm::AArch64FrameLowering::determineCalleeSaves(), llvm::MipsFrameLowering::estimateStackSize(), llvm::TargetLoweringBase::findRepresentativeClass(), llvm::TargetRegisterInfo::getCommonSuperRegClass(), llvm::X86RegisterInfo::getLargestLegalSuperClass(), getLoadStoreRegOpcode(), llvm::SIInstrInfo::getMemOpBaseRegImmOfs(), llvm::MipsFunctionInfo::getMoveF64ViaSpillFI(), llvm::SIInstrInfo::getMovOpcode(), llvm::SIInstrInfo::getOpSize(), llvm::SIRegisterInfo::getPhysRegSubReg(), llvm::BitTracker::MachineEvaluator::getRegBitWidth(), llvm::TargetInstrInfo::getStackSlotRange(), llvm::X86InstrInfo::insertSelect(), llvm::SIInstrInfo::isOperandLegal(), llvm::X86InstrInfo::loadRegFromAddr(), llvm::SIInstrInfo::loadRegFromStackSlot(), llvm::AArch64InstrInfo::loadRegFromStackSlot(), llvm::ARMBaseInstrInfo::loadRegFromStackSlot(), llvm::X86InstrInfo::loadRegFromStackSlot(), llvm::X86InstrInfo::optimizeCompareInstr(), llvm::XCoreFrameLowering::processFunctionBeforeFrameFinalized(), llvm::ARMBaseRegisterInfo::shouldCoalesce(), llvm::SIInstrInfo::splitSMRD(), llvm::X86InstrInfo::storeRegToAddr(), llvm::SIInstrInfo::storeRegToStackSlot(), llvm::AArch64InstrInfo::storeRegToStackSlot(), llvm::ARMBaseInstrInfo::storeRegToStackSlot(), llvm::X86InstrInfo::storeRegToStackSlot(), and llvm::X86InstrInfo::unfoldMemoryOperand().
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getSubClassMask - Returns a bit vector of subclasses, including this one.
The vector is indexed by class IDs, see hasSubClassEq() above for how to use it.
Definition at line 153 of file TargetRegisterInfo.h.
References SubClassMask.
Referenced by llvm::TargetRegisterInfo::getAllocatableClass(), llvm::TargetRegisterInfo::getCommonSubClass(), and llvm::TargetRegisterInfo::getMatchingSuperRegClass().
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getSuperClasses - Returns a NULL terminated list of super-classes.
The classes are ordered by ID which is also a topological ordering from large to small classes. The list does NOT include the current class.
Definition at line 172 of file TargetRegisterInfo.h.
References SuperClasses.
Referenced by llvm::X86RegisterInfo::getLargestLegalSuperClass(), and llvm::ARMBaseRegisterInfo::getLargestLegalSuperClass().
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getSuperRegIndices - Returns a 0-terminated list of sub-register indices that project some super-register class into this register class.
The list has an entry for each Idx such that:
There exists SuperRC where: For all Reg in SuperRC: this->contains(Reg:Idx)
Definition at line 165 of file TargetRegisterInfo.h.
References SuperRegIndices.
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hasSubClass - return true if the specified TargetRegisterClass is a proper sub-class of this TargetRegisterClass.
Definition at line 127 of file TargetRegisterInfo.h.
References hasSubClassEq().
Referenced by llvm::TargetRegisterInfo::getMinimalPhysRegClass(), and hasSuperClass().
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hasSubClassEq - Returns true if RC is a sub-class of or equal to this class.
Definition at line 133 of file TargetRegisterInfo.h.
References getID(), and SubClassMask.
Referenced by llvm::MachineFunction::addLiveIn(), canFoldCopy(), hasSubClass(), hasSuperClassEq(), and UpdateOperandRegClass().
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hasSuperClass - return true if the specified TargetRegisterClass is a proper super-class of this TargetRegisterClass.
Definition at line 140 of file TargetRegisterInfo.h.
References hasSubClass().
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hasSuperClassEq - Returns true if RC is a super-class of or equal to this class.
Definition at line 146 of file TargetRegisterInfo.h.
References hasSubClassEq().
Referenced by llvm::PPCInstrInfo::getOperandLatency(), isFPR64(), and isGPR64().
hasType - return true if this TargetRegisterClass has the ValueType vt.
Definition at line 106 of file TargetRegisterInfo.h.
References llvm::MVT::Other, and VTs.
Referenced by llvm::PPCTargetLowering::emitEHSjLjSetJmp(), llvm::TargetRegisterInfo::getMinimalPhysRegClass(), llvm::TargetLowering::getRegForInlineAsmConstraint(), llvm::MipsSEInstrInfo::loadRegFromStack(), and llvm::MipsSEInstrInfo::storeRegToStack().
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isAllocatable - Return true if this register class may be used to create virtual registers.
Definition at line 102 of file TargetRegisterInfo.h.
References llvm::MCRegisterClass::isAllocatable(), and MC.
Referenced by llvm::MachineRegisterInfo::createVirtualRegister(), llvm::TargetRegisterInfo::getAllocatableClass(), getAllocatableSetForRC(), and llvm::MachineRegisterInfo::setRegClass().
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isASubClass - return true if this TargetRegisterClass is a subset class of at least one other TargetRegisterClass.
Definition at line 178 of file TargetRegisterInfo.h.
References SuperClasses.
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vt_begin / vt_end - Loop over all of the value types that can be represented by values in this register class.
Definition at line 115 of file TargetRegisterInfo.h.
References VTs.
Referenced by GetRegistersForValue(), getRegTy(), llvm::TargetLoweringBase::isLegalRC(), and llvm::X86InstrInfo::unfoldMemoryOperand().
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Definition at line 119 of file TargetRegisterInfo.h.
References I, llvm::MVT::Other, and VTs.
Referenced by getRegTy(), and llvm::TargetLoweringBase::isLegalRC().
| const uint8_t llvm::TargetRegisterClass::AllocationPriority |
Classes with a higher priority value are assigned first by register allocators using a greedy heuristic.
The value is in the range [0,63].
Definition at line 51 of file TargetRegisterInfo.h.
Whether the class supports two (or more) disjunct subregister indices.
Definition at line 53 of file TargetRegisterInfo.h.
Referenced by llvm::MachineRegisterInfo::shouldTrackSubRegLiveness().
Definition at line 48 of file TargetRegisterInfo.h.
Referenced by getLaneMask().
| const MCRegisterClass* llvm::TargetRegisterClass::MC |
Definition at line 44 of file TargetRegisterInfo.h.
Referenced by begin(), contains(), end(), getAlignment(), getCopyCost(), getID(), llvm::TargetRegisterInfo::getMatchingSuperReg(), getNumRegs(), llvm::TargetRegisterInfo::getRegClassName(), getRegister(), getSize(), and isAllocatable().
| ArrayRef<MCPhysReg>(* llvm::TargetRegisterClass::OrderFunc)(const MachineFunction &) |
Definition at line 55 of file TargetRegisterInfo.h.
Referenced by getRawAllocationOrder().
| const uint32_t* llvm::TargetRegisterClass::SubClassMask |
Definition at line 46 of file TargetRegisterInfo.h.
Referenced by getSubClassMask(), and hasSubClassEq().
| const sc_iterator llvm::TargetRegisterClass::SuperClasses |
Definition at line 54 of file TargetRegisterInfo.h.
Referenced by getSuperClasses(), and isASubClass().
| const uint16_t* llvm::TargetRegisterClass::SuperRegIndices |
Definition at line 47 of file TargetRegisterInfo.h.
Referenced by getSuperRegIndices().
| const vt_iterator llvm::TargetRegisterClass::VTs |
Definition at line 45 of file TargetRegisterInfo.h.
Referenced by hasType(), vt_begin(), and vt_end().
1.8.6