55 #define DEBUG_TYPE "twoaddrinstr"
57 STATISTIC(NumTwoAddressInstrs,
"Number of two-address instructions");
58 STATISTIC(NumCommuted ,
"Number of instructions commuted to coalesce");
59 STATISTIC(NumAggrCommuted ,
"Number of instructions aggressively commuted");
60 STATISTIC(NumConvertedTo3Addr,
"Number of instructions promoted to 3-address");
61 STATISTIC(Num3AddrSunk,
"Number of 3-address instructions sunk");
62 STATISTIC(NumReSchedUps,
"Number of instructions re-scheduled up");
63 STATISTIC(NumReSchedDowns,
"Number of instructions re-scheduled down");
68 cl::desc(
"Coalesce copies by rescheduling (default=true)"),
106 bool isRevCopyChain(
unsigned FromReg,
unsigned ToReg,
int Maxlen);
108 bool noUseAfterLastDef(
unsigned Reg,
unsigned Dist,
unsigned &LastDef);
110 bool isProfitableToCommute(
unsigned regA,
unsigned regB,
unsigned regC,
114 unsigned RegB,
unsigned RegC,
unsigned Dist);
116 bool isProfitableToConv3Addr(
unsigned RegA,
unsigned RegB);
120 unsigned RegA,
unsigned RegB,
unsigned Dist);
133 unsigned SrcIdx,
unsigned DstIdx,
134 unsigned Dist,
bool shouldOnlyCommute);
136 void scanUses(
unsigned DstReg);
143 void processTiedPairs(
MachineInstr *
MI, TiedPairList&,
unsigned &Dist);
170 "Two-Address instruction pass",
false,
false)
183 bool TwoAddressInstructionPass::
184 sink3AddrInstruction(
MachineInstr *MI,
unsigned SavedReg,
191 bool SeenStore =
true;
192 if (!MI->isSafeToMove(AA, SeenStore))
198 for (
unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
202 unsigned MOReg = MO.
getReg();
205 if (MO.
isUse() && MOReg != SavedReg)
223 "Reg should not have empty live interval.");
227 if (I != LI.
end() && I->start < MBBEndIdx)
231 KillMI = LIS->getInstructionFromIndex(I->end);
235 UI = MRI->use_nodbg_begin(SavedReg),
236 UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
248 if (!KillMI || KillMI->
getParent() != MBB || KillMI == MI ||
262 unsigned NumVisited = 0;
271 for (
unsigned i = 0, e = OtherMI->
getNumOperands(); i != e; ++i) {
275 unsigned MOReg = MO.
getReg();
282 if (OtherMI == KillMI && MOReg == SavedReg)
286 else if (UseRegs.
count(MOReg))
292 assert(KillMO &&
"Didn't find kill");
297 KillMO = MI->findRegisterUseOperand(SavedReg,
false, TRI);
301 LV->replaceKillInstruction(SavedReg, KillMI, MI);
306 MBB->insert(KillPos, MI);
321 if (DefMI.getParent() != BB || DefMI.isDebugValue())
325 else if (Ret != &DefMI)
338 bool TwoAddressInstructionPass::isRevCopyChain(
unsigned FromReg,
unsigned ToReg,
340 unsigned TmpReg = FromReg;
341 for (
int i = 0; i < Maxlen; i++) {
343 if (!Def || !Def->
isCopy())
358 bool TwoAddressInstructionPass::noUseAfterLastDef(
unsigned Reg,
unsigned Dist,
361 unsigned LastUse = Dist;
367 if (DI == DistanceMap.
end())
369 if (MO.isUse() && DI->second < LastUse)
370 LastUse = DI->second;
371 if (MO.isDef() && DI->second > LastDef)
372 LastDef = DI->second;
375 return !(LastUse > LastDef && LastUse < Dist);
382 unsigned &SrcReg,
unsigned &DstReg,
383 bool &IsSrcPhys,
bool &IsDstPhys) {
420 assert(I != LI.
end() &&
"Reg must be live-in to use.");
448 bool allowFalsePositives) {
453 (allowFalsePositives || MRI->
hasOneUse(Reg)))
462 if (std::next(Begin) != MRI->
def_end())
465 bool IsSrcPhys, IsDstPhys;
466 unsigned SrcReg, DstReg;
469 if (!
isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
478 for (
unsigned i = 0, NumOps = MI.
getNumOperands(); i != NumOps; ++i) {
498 unsigned &DstReg,
bool &IsDstPhys) {
507 if (
isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) {
525 if (SI == RegMap.
end())
549 TwoAddressInstructionPass::
550 isProfitableToCommute(
unsigned regA,
unsigned regB,
unsigned regC,
597 if ((!FromRegB && CompC) || (FromRegB && !CompB && (!FromRegC || CompC)))
603 if ((!FromRegC && CompB) || (FromRegC && !CompC && (!FromRegB || CompB)))
609 unsigned LastDefC = 0;
610 if (!noUseAfterLastDef(regC, Dist, LastDefC))
615 unsigned LastDefB = 0;
616 if (!noUseAfterLastDef(regB, Dist, LastDefB))
634 if (isRevCopyChain(regC, regA, 3))
637 if (isRevCopyChain(regB, regA, 3))
642 return LastDefB && LastDefC && LastDefC > LastDefB;
648 bool TwoAddressInstructionPass::
650 unsigned RegB,
unsigned RegC,
unsigned Dist) {
652 DEBUG(
dbgs() <<
"2addr: COMMUTING : " << *MI);
655 if (NewMI ==
nullptr) {
656 DEBUG(
dbgs() <<
"2addr: COMMUTING FAILED!\n");
660 DEBUG(
dbgs() <<
"2addr: COMMUTED TO: " << *NewMI);
661 assert(NewMI == MI &&
662 "TargetInstrInfo::commuteInstruction() should not return a new "
663 "instruction unless it was requested.");
669 SrcRegMap[RegA] = FromRegC;
678 TwoAddressInstructionPass::isProfitableToConv3Addr(
unsigned RegA,
unsigned RegB){
697 unsigned RegA,
unsigned RegB,
702 assert(MBB == MFI &&
"convertToThreeAddress changed iterator reference");
706 DEBUG(
dbgs() <<
"2addr: CONVERTING 2-ADDR: " << *mi);
707 DEBUG(
dbgs() <<
"2addr: TO 3-ADDR: " << *NewMI);
711 LIS->ReplaceMachineInstrInMaps(mi, NewMI);
717 Sunk = sink3AddrInstruction(NewMI, RegB, mi);
722 DistanceMap.insert(std::make_pair(NewMI, Dist));
728 SrcRegMap.erase(RegA);
729 DstRegMap.erase(RegB);
736 TwoAddressInstructionPass::scanUses(
unsigned DstReg) {
741 unsigned Reg = DstReg;
743 NewReg, IsDstPhys)) {
744 if (IsCopy && !Processed.insert(UseMI).second)
748 if (DI != DistanceMap.
end())
756 bool isNew = SrcRegMap.insert(std::make_pair(NewReg, Reg)).second;
758 assert(SrcRegMap[NewReg] == Reg &&
"Can't map to two src registers!");
763 if (!VirtRegPairs.
empty()) {
764 unsigned ToReg = VirtRegPairs.
back();
766 while (!VirtRegPairs.
empty()) {
767 unsigned FromReg = VirtRegPairs.
back();
769 bool isNew = DstRegMap.insert(std::make_pair(FromReg, ToReg)).second;
771 assert(DstRegMap[FromReg] == ToReg &&
"Can't map to two dst registers!");
774 bool isNew = DstRegMap.insert(std::make_pair(DstReg, ToReg)).second;
776 assert(DstRegMap[DstReg] == ToReg &&
"Can't map to two dst registers!");
792 void TwoAddressInstructionPass::processCopy(
MachineInstr *MI) {
793 if (Processed.count(MI))
796 bool IsSrcPhys, IsDstPhys;
797 unsigned SrcReg, DstReg;
801 if (IsDstPhys && !IsSrcPhys)
802 DstRegMap.insert(std::make_pair(SrcReg, DstReg));
803 else if (!IsDstPhys && IsSrcPhys) {
804 bool isNew = SrcRegMap.insert(std::make_pair(DstReg, SrcReg)).second;
806 assert(SrcRegMap[DstReg] == SrcReg &&
807 "Can't map to two src physical registers!");
812 Processed.insert(MI);
819 bool TwoAddressInstructionPass::
830 if (DI == DistanceMap.
end())
838 "Reg should not have empty live interval.");
842 if (I != LI.
end() && I->start < MBBEndIdx)
846 KillMI = LIS->getInstructionFromIndex(I->end);
848 KillMI = LV->getVarInfo(Reg).findKill(MBB);
863 bool SeenStore =
true;
867 if (
TII->getInstrLatency(InstrItins, MI) > 1)
878 unsigned MOReg = MO.
getReg();
885 if (MOReg != Reg && (MO.
isKill() ||
896 while (End->isCopy() && Defs.
count(End->getOperand(1).getReg())) {
897 Defs.
insert(End->getOperand(0).getReg());
902 unsigned NumVisited = 0;
917 for (
unsigned i = 0, e = OtherMI->
getNumOperands(); i != e; ++i) {
921 unsigned MOReg = MO.
getReg();
925 if (Uses.
count(MOReg))
934 if (Defs.
count(MOReg))
936 bool isKill = MO.
isKill() ||
939 ((isKill && Uses.
count(MOReg)) || Kills.
count(MOReg)))
942 if (MOReg == Reg && !isKill)
946 assert((MOReg != Reg || OtherMI == KillMI) &&
947 "Found multiple kills of a register in a basic block");
953 while (Begin != MBB->begin() && std::prev(Begin)->isDebugValue())
964 MBB->splice(InsertPos, MBB, CopyMI);
965 LIS->handleMove(CopyMI);
972 MBB->splice(InsertPos, MBB, Begin, End);
973 DistanceMap.erase(DI);
979 LV->removeVirtualRegisterKilled(Reg, KillMI);
980 LV->addVirtualRegisterKilled(Reg, MI);
983 DEBUG(
dbgs() <<
"\trescheduled below kill: " << *KillMI);
989 bool TwoAddressInstructionPass::isDefTooClose(
unsigned Reg,
unsigned Dist,
991 for (
MachineInstr &DefMI : MRI->def_instructions(Reg)) {
992 if (DefMI.getParent() != MBB || DefMI.isCopy() || DefMI.isCopyLike())
997 if (DDI == DistanceMap.
end())
999 unsigned DefDist = DDI->second;
1000 assert(Dist > DefDist &&
"Visited def already?");
1001 if (
TII->getInstrLatency(InstrItins, &DefMI) > (Dist - DefDist))
1011 bool TwoAddressInstructionPass::
1022 if (DI == DistanceMap.
end())
1030 "Reg should not have empty live interval.");
1034 if (I != LI.
end() && I->start < MBBEndIdx)
1038 KillMI = LIS->getInstructionFromIndex(I->end);
1040 KillMI = LV->getVarInfo(Reg).findKill(MBB);
1050 bool SeenStore =
true;
1058 for (
unsigned i = 0, e = KillMI->
getNumOperands(); i != e; ++i) {
1062 unsigned MOReg = MO.
getReg();
1066 if (isDefTooClose(MOReg, DI->second, MI))
1069 if (MOReg == Reg && !isKill)
1072 if (isKill && MOReg != Reg)
1082 unsigned NumVisited = 0;
1089 if (NumVisited > 10)
1097 for (
unsigned i = 0, e = OtherMI->
getNumOperands(); i != e; ++i) {
1101 unsigned MOReg = MO.
getReg();
1105 if (Defs.
count(MOReg))
1109 if (Kills.
count(MOReg))
1112 if (OtherMI != MI && MOReg == Reg &&
1121 for (
unsigned i = 0, e = OtherDefs.
size(); i != e; ++i) {
1122 unsigned MOReg = OtherDefs[i];
1123 if (Uses.
count(MOReg))
1126 LiveDefs.
count(MOReg))
1135 while (InsertPos != MBB->begin() && std::prev(InsertPos)->isDebugValue())
1139 while (std::prev(From)->isDebugValue())
1141 MBB->splice(InsertPos, MBB, From, To);
1143 nmi = std::prev(InsertPos);
1144 DistanceMap.erase(DI);
1148 LIS->handleMove(KillMI);
1150 LV->removeVirtualRegisterKilled(Reg, KillMI);
1151 LV->addVirtualRegisterKilled(Reg, MI);
1154 DEBUG(
dbgs() <<
"\trescheduled kill: " << *KillMI);
1165 bool TwoAddressInstructionPass::
1168 unsigned SrcIdx,
unsigned DstIdx,
1169 unsigned Dist,
bool shouldOnlyCommute) {
1178 "cannot make instruction into two-address form");
1179 bool regBKilled =
isKilled(MI, regB, MRI,
TII, LIS,
true);
1185 unsigned SrcOp1, SrcOp2;
1187 unsigned regCIdx = ~0U;
1188 bool TryCommute =
false;
1189 bool AggressiveCommute =
false;
1191 TII->findCommutedOpIndices(&MI, SrcOp1, SrcOp2)) {
1192 if (SrcIdx == SrcOp1)
1194 else if (SrcIdx == SrcOp2)
1197 if (regCIdx != ~0U) {
1199 if (!regBKilled &&
isKilled(MI, regC, MRI,
TII, LIS,
false))
1203 else if (isProfitableToCommute(regA, regB, regC, &MI, Dist)) {
1205 AggressiveCommute =
true;
1218 bool Commuted =
false;
1221 if (TryCommute && commuteInstruction(mi, regB, regC, Dist)) {
1224 if (AggressiveCommute)
1230 if (shouldOnlyCommute)
1243 if (!regBKilled || isProfitableToConv3Addr(regA, regB)) {
1245 if (convertInstTo3Addr(mi, nmi, regA, regB, Dist)) {
1246 ++NumConvertedTo3Addr;
1271 if (MI.
mayLoad() && !regBKilled) {
1273 unsigned LoadRegIndex;
1283 DEBUG(
dbgs() <<
"2addr: UNFOLDING: " << MI);
1285 TRI->getAllocatableClass(
1286 TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI, *MF));
1287 unsigned Reg = MRI->createVirtualRegister(RC);
1289 if (!
TII->unfoldMemoryOperand(*MF, &MI, Reg,
1292 DEBUG(
dbgs() <<
"2addr: ABANDONING UNFOLD\n");
1295 assert(NewMIs.
size() == 2 &&
1296 "Unfolded a load into multiple instructions!");
1298 NewMIs[1]->addRegisterKilled(Reg, TRI);
1302 MBB->
insert(mi, NewMIs[0]);
1303 MBB->insert(mi, NewMIs[1]);
1305 DEBUG(
dbgs() <<
"2addr: NEW LOAD: " << *NewMIs[0]
1306 <<
"2addr: NEW INST: " << *NewMIs[1]);
1309 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA);
1310 unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB);
1312 bool TransformResult =
1313 tryInstructionTransform(NewMI, mi, NewSrcIdx, NewDstIdx, Dist,
true);
1314 (void)TransformResult;
1315 assert(!TransformResult &&
1316 "tryInstructionTransform() should return false.");
1317 if (NewMIs[1]->getOperand(NewSrcIdx).isKill()) {
1327 if (NewMIs[0]->killsRegister(MO.
getReg()))
1328 LV->replaceKillInstruction(MO.
getReg(), &
MI, NewMIs[0]);
1330 assert(NewMIs[1]->killsRegister(MO.
getReg()) &&
1331 "Kill missing after load unfold!");
1332 LV->replaceKillInstruction(MO.
getReg(), &
MI, NewMIs[1]);
1335 }
else if (LV->removeVirtualRegisterDead(MO.
getReg(), &
MI)) {
1336 if (NewMIs[1]->registerDefIsDead(MO.
getReg()))
1337 LV->addVirtualRegisterDead(MO.
getReg(), NewMIs[1]);
1339 assert(NewMIs[0]->registerDefIsDead(MO.
getReg()) &&
1340 "Dead flag missing after load unfold!");
1341 LV->addVirtualRegisterDead(MO.
getReg(), NewMIs[0]);
1346 LV->addVirtualRegisterKilled(Reg, NewMIs[1]);
1364 LIS->repairIntervalsInRange(MBB, Begin, End, OrigRegs);
1372 DEBUG(
dbgs() <<
"2addr: ABANDONING UNFOLD\n");
1373 NewMIs[0]->eraseFromParent();
1374 NewMIs[1]->eraseFromParent();
1386 bool TwoAddressInstructionPass::
1387 collectTiedOperands(
MachineInstr *MI, TiedOperandMap &TiedOperands) {
1389 bool AnyOps =
false;
1392 for (
unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) {
1393 unsigned DstIdx = 0;
1399 unsigned SrcReg = SrcMO.
getReg();
1400 unsigned DstReg = DstMO.
getReg();
1402 if (SrcReg == DstReg)
1405 assert(SrcReg && SrcMO.
isUse() &&
"two address instruction invalid");
1413 MRI->constrainRegClass(DstReg, RC);
1416 DEBUG(
dbgs() <<
"\t\trewrite undef:\t" << *MI);
1419 TiedOperands[SrcReg].push_back(std::make_pair(SrcIdx, DstIdx));
1427 TwoAddressInstructionPass::processTiedPairs(
MachineInstr *MI,
1428 TiedPairList &TiedPairs,
1430 bool IsEarlyClobber =
false;
1431 for (
unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) {
1436 bool RemovedKillFlag =
false;
1437 bool AllUsesCopied =
true;
1438 unsigned LastCopiedReg = 0;
1441 unsigned SubRegB = 0;
1442 for (
unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) {
1443 unsigned SrcIdx = TiedPairs[tpi].first;
1444 unsigned DstIdx = TiedPairs[tpi].second;
1447 unsigned RegA = DstMO.
getReg();
1458 AllUsesCopied =
false;
1461 LastCopiedReg = RegA;
1464 "cannot make instruction into two-address form");
1471 assert(i == DstIdx ||
1481 MIB.
addReg(RegB, 0, SubRegB);
1485 assert(TRI->getMatchingSuperRegClass(RC, MRI->getRegClass(RegA),
1487 "tied subregister must be a truncation");
1492 assert(TRI->getMatchingSuperReg(RegA, SubRegB, MRI->getRegClass(RegB))
1493 &&
"tied subregister must be a truncation");
1500 DistanceMap.insert(std::make_pair(PrevMI, Dist));
1501 DistanceMap[
MI] = ++Dist;
1504 LastCopyIdx = LIS->InsertMachineInstrInMaps(PrevMI).
getRegSlot();
1510 LIS->getInstructionIndex(MI).
getRegSlot(IsEarlyClobber);
1511 LI.
addSegment(LiveInterval::Segment(LastCopyIdx, endIdx, VNI));
1515 DEBUG(
dbgs() <<
"\t\tprepend:\t" << *MIB);
1519 "inconsistent operand info for 2-reg pass");
1522 RemovedKillFlag =
true;
1528 MRI->constrainRegClass(RegA, RC);
1536 SrcRegMap[RegA] = RegB;
1540 if (AllUsesCopied) {
1541 if (!IsEarlyClobber) {
1549 RemovedKillFlag =
true;
1551 MO.
setReg(LastCopiedReg);
1558 if (RemovedKillFlag && LV && LV->getVarInfo(RegB).removeKill(MI)) {
1561 LV->addVirtualRegisterKilled(RegB, PrevMI);
1567 SlotIndex MIIdx = LIS->getInstructionIndex(MI);
1569 assert(I != LI.
end() &&
"RegB must be live-in to use.");
1572 if (I->end == UseIdx)
1576 }
else if (RemovedKillFlag) {
1596 MRI = &MF->getRegInfo();
1597 TII = MF->getSubtarget().getInstrInfo();
1599 InstrItins = MF->getSubtarget().getInstrItineraryData();
1600 LV = getAnalysisIfAvailable<LiveVariables>();
1601 LIS = getAnalysisIfAvailable<LiveIntervals>();
1602 AA = &getAnalysis<AliasAnalysis>();
1605 bool MadeChange =
false;
1607 DEBUG(
dbgs() <<
"********** REWRITING TWO-ADDR INSTRS **********\n");
1609 << MF->getName() <<
'\n');
1614 TiedOperandMap TiedOperands;
1616 MBBI != MBBE; ++MBBI) {
1619 DistanceMap.clear();
1626 if (mi->isDebugValue()) {
1633 if (mi->isRegSequence())
1634 eliminateRegSequence(mi);
1636 DistanceMap.insert(std::make_pair(mi, ++Dist));
1642 if (!collectTiedOperands(mi, TiedOperands)) {
1647 ++NumTwoAddressInstrs;
1654 if (TiedOperands.size() == 1) {
1656 = TiedOperands.
begin()->second;
1657 if (TiedPairs.
size() == 1) {
1658 unsigned SrcIdx = TiedPairs[0].first;
1659 unsigned DstIdx = TiedPairs[0].second;
1660 unsigned SrcReg = mi->getOperand(SrcIdx).getReg();
1661 unsigned DstReg = mi->getOperand(DstIdx).getReg();
1662 if (SrcReg != DstReg &&
1663 tryInstructionTransform(mi, nmi, SrcIdx, DstIdx, Dist,
false)) {
1666 TiedOperands.clear();
1674 for (TiedOperandMap::iterator OI = TiedOperands.begin(),
1675 OE = TiedOperands.end(); OI != OE; ++OI) {
1676 processTiedPairs(mi, OI->second, Dist);
1677 DEBUG(
dbgs() <<
"\t\trewrite to:\t" << *mi);
1681 if (mi->isInsertSubreg()) {
1684 unsigned SubIdx = mi->getOperand(3).getImm();
1685 mi->RemoveOperand(3);
1686 assert(mi->getOperand(0).getSubReg() == 0 &&
"Unexpected subreg idx");
1687 mi->getOperand(0).setSubReg(SubIdx);
1688 mi->getOperand(0).setIsUndef(mi->getOperand(1).isUndef());
1689 mi->RemoveOperand(1);
1691 DEBUG(
dbgs() <<
"\t\tconvert to:\t" << *mi);
1696 TiedOperands.clear();
1702 MF->verify(
this,
"After two-address instruction pass");
1718 void TwoAddressInstructionPass::
1725 DEBUG(
dbgs() <<
"Illegal REG_SEQUENCE instruction:" << *MI);
1736 bool DefEmitted =
false;
1739 unsigned SrcReg = UseMO.
getReg();
1747 bool isKill = UseMO.
isKill();
1749 for (
unsigned j = i + 2; j < e; j += 2)
1774 LV->replaceKillInstruction(SrcReg, MI, CopyMI);
1776 DEBUG(
dbgs() <<
"Inserted: " << *CopyMI);
1783 DEBUG(
dbgs() <<
"Turned: " << *MI <<
" into an IMPLICIT_DEF");
1794 LIS->repairIntervalsInRange(MBB, MBBI, EndMBBI, OrigRegs);
void push_back(const T &Elt)
mop_iterator operands_end()
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
STATISTIC(NumFunctions,"Total number of functions")
static MachineInstr * getSingleDef(unsigned Reg, MachineBasicBlock *BB, const MachineRegisterInfo *MRI)
getSingleDef – return the MachineInstr* if it is the single def of the Reg in current BB...
bool isConvertibleTo3Addr(QueryType Type=IgnoreBundle) const
Return true if this is a 2-address instruction which can be changed into a 3-address instruction if n...
static unsigned getMappedReg(unsigned Reg, DenseMap< unsigned, unsigned > &RegMap)
getMappedReg - Return the physical register the specified virtual register might be mapped to...
static bool isKilled(MachineInstr &MI, unsigned Reg, const MachineRegisterInfo *MRI, const TargetInstrInfo *TII, LiveIntervals *LIS, bool allowFalsePositives)
isKilled - Test if the given register value, which is used by the given instruction, is killed by the given instruction.
use_instr_nodbg_iterator use_instr_nodbg_begin(unsigned RegNo) const
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
char & MachineDominatorsID
MachineDominators - This pass is a machine dominators analysis pass.
LiveInterval - This class represents the liveness of a register, or stack slot.
Describe properties that are true of each instruction in the target description file.
void setIsUndef(bool Val=true)
SlotIndex getInstructionIndex(const MachineInstr *instr) const
Returns the base index of the given instruction.
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
INITIALIZE_PASS_BEGIN(TwoAddressInstructionPass,"twoaddressinstruction","Two-Address instruction pass", false, false) INITIALIZE_PASS_END(TwoAddressInstructionPass
MachineOperand * findRegisterUseOperand(unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterUseOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
static cl::opt< bool > EnableRescheduling("twoaddr-reschedule", cl::desc("Coalesce copies by rescheduling (default=true)"), cl::init(true), cl::Hidden)
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
VNInfo - Value Number Information.
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
bool isNotInMIMap(const MachineInstr *Instr) const
isNotInMIMap - returns true if the specified machine instr has been removed or was never entered in t...
COPY - Target-independent register copy.
AnalysisUsage & addRequired()
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
MCInst const & instruction(MCInst const &MCB, size_t Index)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Reg
All possible values of the reg field in the ModR/M byte.
void initializeTwoAddressInstructionPassPass(PassRegistry &)
unsigned getNumOperands() const
Access to explicit operands of the instruction.
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
const HexagonRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
static bool regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI)
regsAreCompatible - Return true if the two registers are equal or aliased.
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Two Address instruction false
iterator addSegment(Segment S)
Add the specified Segment to this range, merging segments as appropriate.
bool isCopyLike() const
Return true if the instruction behaves like a copy.
AnalysisUsage & addPreservedID(const void *ID)
Itinerary data supplied by a subtarget to be used by a target.
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
SlotIndex getPrevSlot() const
Returns the previous slot in the index list.
const MachineBasicBlock * getParent() const
TargetInstrInfo - Interface to description of machine instruction set.
bool isDebugValue() const
bool isInsertSubreg() const
bool isEarlyClobber() const
IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
bundle_iterator< MachineInstr, instr_iterator > iterator
initializer< Ty > init(const Ty &Val)
bool hasAtLeastOneValue() const
bool regsOverlap(unsigned regA, unsigned regB) const
regsOverlap - Returns true if the two registers are equal or alias each other.
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
const MachineOperand & getOperand(unsigned i) const
Two Address instruction pass
Represent the analysis usage information of a pass.
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore...
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
static MachineInstr * findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB, MachineRegisterInfo *MRI, const TargetInstrInfo *TII, bool &IsCopy, unsigned &DstReg, bool &IsDstPhys)
findOnlyInterestingUse - Given a register, if has a single in-basic block use, return the use instruc...
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
#define INITIALIZE_AG_DEPENDENCY(depName)
unsigned getSubReg() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void setIsKill(bool Val=true)
iterator find(SlotIndex Pos)
find - Return an iterator pointing to the first segment that ends after Pos, or end().
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
void removeSegment(SlotIndex Start, SlotIndex End, bool RemoveDeadValNo=false)
Remove the specified segment from this range.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
Segments::const_iterator const_iterator
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII, unsigned &SrcReg, unsigned &DstReg, bool &IsSrcPhys, bool &IsDstPhys)
isCopyToReg - Return true if the specified MI is a copy instruction or a extract_subreg instruction...
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
bool hasOneUse(unsigned RegNo) const
hasOneUse - Return true if there is exactly one instruction using the specified register.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
LiveInterval & getInterval(unsigned Reg)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
bool isSubregToReg() const
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
iterator insert(iterator I, T &&Elt)
def_iterator def_begin(unsigned RegNo) const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
static bool isPhysicalRegister(unsigned Reg)
isPhysicalRegister - Return true if the specified register number is in the physical register namespa...
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
void setReg(unsigned Reg)
Change the register this operand corresponds to.
bool isCall(QueryType Type=AnyInBundle) const
void setSubReg(unsigned subReg)
iterator find(const KeyT &Val)
static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg, LiveIntervals *LIS)
isPLainlyKilled - Test if the given register value, which is used by the
char & TwoAddressInstructionPassID
TwoAddressInstruction - This pass reduces two-address instructions to use two operands.
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def...
unsigned getReg() const
getReg - Returns the register number.
VNInfo * getNextValue(SlotIndex def, VNInfo::Allocator &VNInfoAllocator)
getNextValue - Create a new value number and return it.
bool isCommutable(QueryType Type=IgnoreBundle) const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged.
static def_iterator def_end()
bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr kills the specified register.
iterator_range< def_instr_iterator > def_instructions(unsigned Reg) const
mop_iterator operands_begin()
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
BasicBlockListType::iterator iterator
Primary interface to the complete machine description for the target machine.
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
SlotIndex - An opaque wrapper around machine indexes.
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg)
isTwoAddrUse - Return true if the specified MI uses the specified register as a two-address use...