LLVM  3.7.0
X86MCInstLower.cpp
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1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains code to lower X86 MachineInstrs to their corresponding
11 // MCInst records.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "X86AsmPrinter.h"
16 #include "X86RegisterInfo.h"
19 #include "Utils/X86ShuffleDecode.h"
20 #include "llvm/ADT/Optional.h"
21 #include "llvm/ADT/SmallString.h"
26 #include "llvm/CodeGen/StackMaps.h"
27 #include "llvm/IR/DataLayout.h"
28 #include "llvm/IR/GlobalValue.h"
29 #include "llvm/IR/Mangler.h"
30 #include "llvm/MC/MCAsmInfo.h"
31 #include "llvm/MC/MCCodeEmitter.h"
32 #include "llvm/MC/MCContext.h"
33 #include "llvm/MC/MCExpr.h"
34 #include "llvm/MC/MCFixup.h"
35 #include "llvm/MC/MCInst.h"
36 #include "llvm/MC/MCInstBuilder.h"
37 #include "llvm/MC/MCStreamer.h"
38 #include "llvm/MC/MCSymbol.h"
40 using namespace llvm;
41 
42 namespace {
43 
44 /// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst.
45 class X86MCInstLower {
46  MCContext &Ctx;
47  const MachineFunction &MF;
48  const TargetMachine &TM;
49  const MCAsmInfo &MAI;
51 public:
52  X86MCInstLower(const MachineFunction &MF, X86AsmPrinter &asmprinter);
53 
54  Optional<MCOperand> LowerMachineOperand(const MachineInstr *MI,
55  const MachineOperand &MO) const;
56  void Lower(const MachineInstr *MI, MCInst &OutMI) const;
57 
59  MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
60 
61 private:
63  Mangler *getMang() const {
64  return AsmPrinter.Mang;
65  }
66 };
67 
68 } // end anonymous namespace
69 
70 // Emit a minimal sequence of nops spanning NumBytes bytes.
71 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
72  const MCSubtargetInfo &STI);
73 
74 namespace llvm {
75  X86AsmPrinter::StackMapShadowTracker::StackMapShadowTracker(TargetMachine &TM)
76  : TM(TM), InShadow(false), RequiredShadowSize(0), CurrentShadowSize(0) {}
77 
78  X86AsmPrinter::StackMapShadowTracker::~StackMapShadowTracker() {}
79 
80  void
81  X86AsmPrinter::StackMapShadowTracker::startFunction(MachineFunction &F) {
82  MF = &F;
83  CodeEmitter.reset(TM.getTarget().createMCCodeEmitter(
84  *MF->getSubtarget().getInstrInfo(),
85  *MF->getSubtarget().getRegisterInfo(), MF->getContext()));
86  }
87 
88  void X86AsmPrinter::StackMapShadowTracker::count(MCInst &Inst,
89  const MCSubtargetInfo &STI) {
90  if (InShadow) {
93  raw_svector_ostream VecOS(Code);
94  CodeEmitter->encodeInstruction(Inst, VecOS, Fixups, STI);
95  VecOS.flush();
96  CurrentShadowSize += Code.size();
97  if (CurrentShadowSize >= RequiredShadowSize)
98  InShadow = false; // The shadow is big enough. Stop counting.
99  }
100  }
101 
102  void X86AsmPrinter::StackMapShadowTracker::emitShadowPadding(
103  MCStreamer &OutStreamer, const MCSubtargetInfo &STI) {
104  if (InShadow && CurrentShadowSize < RequiredShadowSize) {
105  InShadow = false;
106  EmitNops(OutStreamer, RequiredShadowSize - CurrentShadowSize,
107  MF->getSubtarget<X86Subtarget>().is64Bit(), STI);
108  }
109  }
110 
111  void X86AsmPrinter::EmitAndCountInstruction(MCInst &Inst) {
112  OutStreamer->EmitInstruction(Inst, getSubtargetInfo());
113  SMShadowTracker.count(Inst, getSubtargetInfo());
114  }
115 } // end llvm namespace
116 
117 X86MCInstLower::X86MCInstLower(const MachineFunction &mf,
118  X86AsmPrinter &asmprinter)
119  : Ctx(mf.getContext()), MF(mf), TM(mf.getTarget()), MAI(*TM.getMCAsmInfo()),
120  AsmPrinter(asmprinter) {}
121 
123  return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>();
124 }
125 
126 
127 /// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
128 /// operand to an MCSymbol.
130 GetSymbolFromOperand(const MachineOperand &MO) const {
131  const DataLayout *DL = TM.getDataLayout();
132  assert((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) && "Isn't a symbol reference");
133 
134  MCSymbol *Sym = nullptr;
136  StringRef Suffix;
137 
138  switch (MO.getTargetFlags()) {
139  case X86II::MO_DLLIMPORT:
140  // Handle dllimport linkage.
141  Name += "__imp_";
142  break;
144  Suffix = "$stub";
145  break;
149  Suffix = "$non_lazy_ptr";
150  break;
151  }
152 
153  if (!Suffix.empty())
154  Name += DL->getPrivateGlobalPrefix();
155 
156  unsigned PrefixLen = Name.size();
157 
158  if (MO.isGlobal()) {
159  const GlobalValue *GV = MO.getGlobal();
160  AsmPrinter.getNameWithPrefix(Name, GV);
161  } else if (MO.isSymbol()) {
162  Mangler::getNameWithPrefix(Name, MO.getSymbolName(), *DL);
163  } else if (MO.isMBB()) {
164  assert(Suffix.empty());
165  Sym = MO.getMBB()->getSymbol();
166  }
167  unsigned OrigLen = Name.size() - PrefixLen;
168 
169  Name += Suffix;
170  if (!Sym)
171  Sym = Ctx.getOrCreateSymbol(Name);
172 
173  StringRef OrigName = StringRef(Name).substr(PrefixLen, OrigLen);
174 
175  // If the target flags on the operand changes the name of the symbol, do that
176  // before we return the symbol.
177  switch (MO.getTargetFlags()) {
178  default: break;
183  if (!StubSym.getPointer()) {
184  assert(MO.isGlobal() && "Extern symbol not handled yet");
185  StubSym =
188  !MO.getGlobal()->hasInternalLinkage());
189  }
190  break;
191  }
195  if (!StubSym.getPointer()) {
196  assert(MO.isGlobal() && "Extern symbol not handled yet");
197  StubSym =
200  !MO.getGlobal()->hasInternalLinkage());
201  }
202  break;
203  }
204  case X86II::MO_DARWIN_STUB: {
207  if (StubSym.getPointer())
208  return Sym;
209 
210  if (MO.isGlobal()) {
211  StubSym =
214  !MO.getGlobal()->hasInternalLinkage());
215  } else {
216  StubSym =
218  StubValueTy(Ctx.getOrCreateSymbol(OrigName), false);
219  }
220  break;
221  }
222  }
223 
224  return Sym;
225 }
226 
228  MCSymbol *Sym) const {
229  // FIXME: We would like an efficient form for this, so we don't have to do a
230  // lot of extra uniquing.
231  const MCExpr *Expr = nullptr;
232  MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None;
233 
234  switch (MO.getTargetFlags()) {
235  default: llvm_unreachable("Unknown target flag on GV operand");
236  case X86II::MO_NO_FLAG: // No flag.
237  // These affect the name of the symbol, not any suffix.
239  case X86II::MO_DLLIMPORT:
241  break;
242 
243  case X86II::MO_TLVP: RefKind = MCSymbolRefExpr::VK_TLVP; break;
245  Expr = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx);
246  // Subtract the pic base.
247  Expr = MCBinaryExpr::createSub(Expr,
248  MCSymbolRefExpr::create(MF.getPICBaseSymbol(),
249  Ctx),
250  Ctx);
251  break;
252  case X86II::MO_SECREL: RefKind = MCSymbolRefExpr::VK_SECREL; break;
253  case X86II::MO_TLSGD: RefKind = MCSymbolRefExpr::VK_TLSGD; break;
254  case X86II::MO_TLSLD: RefKind = MCSymbolRefExpr::VK_TLSLD; break;
255  case X86II::MO_TLSLDM: RefKind = MCSymbolRefExpr::VK_TLSLDM; break;
256  case X86II::MO_GOTTPOFF: RefKind = MCSymbolRefExpr::VK_GOTTPOFF; break;
257  case X86II::MO_INDNTPOFF: RefKind = MCSymbolRefExpr::VK_INDNTPOFF; break;
258  case X86II::MO_TPOFF: RefKind = MCSymbolRefExpr::VK_TPOFF; break;
259  case X86II::MO_DTPOFF: RefKind = MCSymbolRefExpr::VK_DTPOFF; break;
260  case X86II::MO_NTPOFF: RefKind = MCSymbolRefExpr::VK_NTPOFF; break;
261  case X86II::MO_GOTNTPOFF: RefKind = MCSymbolRefExpr::VK_GOTNTPOFF; break;
262  case X86II::MO_GOTPCREL: RefKind = MCSymbolRefExpr::VK_GOTPCREL; break;
263  case X86II::MO_GOT: RefKind = MCSymbolRefExpr::VK_GOT; break;
264  case X86II::MO_GOTOFF: RefKind = MCSymbolRefExpr::VK_GOTOFF; break;
265  case X86II::MO_PLT: RefKind = MCSymbolRefExpr::VK_PLT; break;
269  Expr = MCSymbolRefExpr::create(Sym, Ctx);
270  // Subtract the pic base.
271  Expr = MCBinaryExpr::createSub(Expr,
272  MCSymbolRefExpr::create(MF.getPICBaseSymbol(), Ctx),
273  Ctx);
274  if (MO.isJTI()) {
275  assert(MAI.doesSetDirectiveSuppressesReloc());
276  // If .set directive is supported, use it to reduce the number of
277  // relocations the assembler will generate for differences between
278  // local labels. This is only safe when the symbols are in the same
279  // section so we are restricting it to jumptable references.
280  MCSymbol *Label = Ctx.createTempSymbol();
281  AsmPrinter.OutStreamer->EmitAssignment(Label, Expr);
282  Expr = MCSymbolRefExpr::create(Label, Ctx);
283  }
284  break;
285  }
286 
287  if (!Expr)
288  Expr = MCSymbolRefExpr::create(Sym, RefKind, Ctx);
289 
290  if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
291  Expr = MCBinaryExpr::createAdd(Expr,
292  MCConstantExpr::create(MO.getOffset(), Ctx),
293  Ctx);
294  return MCOperand::createExpr(Expr);
295 }
296 
297 
298 /// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with
299 /// a short fixed-register form.
300 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
301  unsigned ImmOp = Inst.getNumOperands() - 1;
302  assert(Inst.getOperand(0).isReg() &&
303  (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) &&
304  ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
305  Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
306  Inst.getNumOperands() == 2) && "Unexpected instruction!");
307 
308  // Check whether the destination register can be fixed.
309  unsigned Reg = Inst.getOperand(0).getReg();
310  if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
311  return;
312 
313  // If so, rewrite the instruction.
314  MCOperand Saved = Inst.getOperand(ImmOp);
315  Inst = MCInst();
316  Inst.setOpcode(Opcode);
317  Inst.addOperand(Saved);
318 }
319 
320 /// \brief If a movsx instruction has a shorter encoding for the used register
321 /// simplify the instruction to use it instead.
322 static void SimplifyMOVSX(MCInst &Inst) {
323  unsigned NewOpcode = 0;
324  unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg();
325  switch (Inst.getOpcode()) {
326  default:
327  llvm_unreachable("Unexpected instruction!");
328  case X86::MOVSX16rr8: // movsbw %al, %ax --> cbtw
329  if (Op0 == X86::AX && Op1 == X86::AL)
330  NewOpcode = X86::CBW;
331  break;
332  case X86::MOVSX32rr16: // movswl %ax, %eax --> cwtl
333  if (Op0 == X86::EAX && Op1 == X86::AX)
334  NewOpcode = X86::CWDE;
335  break;
336  case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq
337  if (Op0 == X86::RAX && Op1 == X86::EAX)
338  NewOpcode = X86::CDQE;
339  break;
340  }
341 
342  if (NewOpcode != 0) {
343  Inst = MCInst();
344  Inst.setOpcode(NewOpcode);
345  }
346 }
347 
348 /// \brief Simplify things like MOV32rm to MOV32o32a.
350  unsigned Opcode) {
351  // Don't make these simplifications in 64-bit mode; other assemblers don't
352  // perform them because they make the code larger.
353  if (Printer.getSubtarget().is64Bit())
354  return;
355 
356  bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
357  unsigned AddrBase = IsStore;
358  unsigned RegOp = IsStore ? 0 : 5;
359  unsigned AddrOp = AddrBase + 3;
360  assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
361  Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() &&
362  Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() &&
363  Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() &&
364  Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() &&
365  (Inst.getOperand(AddrOp).isExpr() ||
366  Inst.getOperand(AddrOp).isImm()) &&
367  "Unexpected instruction!");
368 
369  // Check whether the destination register can be fixed.
370  unsigned Reg = Inst.getOperand(RegOp).getReg();
371  if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
372  return;
373 
374  // Check whether this is an absolute address.
375  // FIXME: We know TLVP symbol refs aren't, but there should be a better way
376  // to do this here.
377  bool Absolute = true;
378  if (Inst.getOperand(AddrOp).isExpr()) {
379  const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr();
380  if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE))
381  if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
382  Absolute = false;
383  }
384 
385  if (Absolute &&
386  (Inst.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 ||
387  Inst.getOperand(AddrBase + X86::AddrScaleAmt).getImm() != 1 ||
388  Inst.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0))
389  return;
390 
391  // If so, rewrite the instruction.
392  MCOperand Saved = Inst.getOperand(AddrOp);
393  MCOperand Seg = Inst.getOperand(AddrBase + X86::AddrSegmentReg);
394  Inst = MCInst();
395  Inst.setOpcode(Opcode);
396  Inst.addOperand(Saved);
397  Inst.addOperand(Seg);
398 }
399 
400 static unsigned getRetOpcode(const X86Subtarget &Subtarget) {
401  return Subtarget.is64Bit() ? X86::RETQ : X86::RETL;
402 }
403 
405 X86MCInstLower::LowerMachineOperand(const MachineInstr *MI,
406  const MachineOperand &MO) const {
407  switch (MO.getType()) {
408  default:
409  MI->dump();
410  llvm_unreachable("unknown operand type");
411  case MachineOperand::MO_Register:
412  // Ignore all implicit register operands.
413  if (MO.isImplicit())
414  return None;
415  return MCOperand::createReg(MO.getReg());
416  case MachineOperand::MO_Immediate:
417  return MCOperand::createImm(MO.getImm());
418  case MachineOperand::MO_MachineBasicBlock:
419  case MachineOperand::MO_GlobalAddress:
420  case MachineOperand::MO_ExternalSymbol:
422  case MachineOperand::MO_MCSymbol:
423  return LowerSymbolOperand(MO, MO.getMCSymbol());
424  case MachineOperand::MO_JumpTableIndex:
426  case MachineOperand::MO_ConstantPoolIndex:
428  case MachineOperand::MO_BlockAddress:
429  return LowerSymbolOperand(
431  case MachineOperand::MO_RegisterMask:
432  // Ignore call clobbers.
433  return None;
434  }
435 }
436 
437 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
438  OutMI.setOpcode(MI->getOpcode());
439 
440  for (const MachineOperand &MO : MI->operands())
441  if (auto MaybeMCOp = LowerMachineOperand(MI, MO))
442  OutMI.addOperand(MaybeMCOp.getValue());
443 
444  // Handle a few special cases to eliminate operand modifiers.
445 ReSimplify:
446  switch (OutMI.getOpcode()) {
447  case X86::LEA64_32r:
448  case X86::LEA64r:
449  case X86::LEA16r:
450  case X86::LEA32r:
451  // LEA should have a segment register, but it must be empty.
452  assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands &&
453  "Unexpected # of LEA operands");
454  assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 &&
455  "LEA has segment specified!");
456  break;
457 
458  case X86::MOV32ri64:
459  OutMI.setOpcode(X86::MOV32ri);
460  break;
461 
462  // Commute operands to get a smaller encoding by using VEX.R instead of VEX.B
463  // if one of the registers is extended, but other isn't.
464  case X86::VMOVAPDrr:
465  case X86::VMOVAPDYrr:
466  case X86::VMOVAPSrr:
467  case X86::VMOVAPSYrr:
468  case X86::VMOVDQArr:
469  case X86::VMOVDQAYrr:
470  case X86::VMOVDQUrr:
471  case X86::VMOVDQUYrr:
472  case X86::VMOVUPDrr:
473  case X86::VMOVUPDYrr:
474  case X86::VMOVUPSrr:
475  case X86::VMOVUPSYrr: {
476  if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
478  unsigned NewOpc;
479  switch (OutMI.getOpcode()) {
480  default: llvm_unreachable("Invalid opcode");
481  case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
482  case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
483  case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;
484  case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
485  case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;
486  case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
487  case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break;
488  case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
489  case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break;
490  case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
491  case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break;
492  case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
493  }
494  OutMI.setOpcode(NewOpc);
495  }
496  break;
497  }
498  case X86::VMOVSDrr:
499  case X86::VMOVSSrr: {
500  if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
502  unsigned NewOpc;
503  switch (OutMI.getOpcode()) {
504  default: llvm_unreachable("Invalid opcode");
505  case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break;
506  case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break;
507  }
508  OutMI.setOpcode(NewOpc);
509  }
510  break;
511  }
512 
513  // TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have register
514  // inputs modeled as normal uses instead of implicit uses. As such, truncate
515  // off all but the first operand (the callee). FIXME: Change isel.
516  case X86::TAILJMPr64:
517  case X86::TAILJMPr64_REX:
518  case X86::CALL64r:
519  case X86::CALL64pcrel32: {
520  unsigned Opcode = OutMI.getOpcode();
521  MCOperand Saved = OutMI.getOperand(0);
522  OutMI = MCInst();
523  OutMI.setOpcode(Opcode);
524  OutMI.addOperand(Saved);
525  break;
526  }
527 
528  case X86::EH_RETURN:
529  case X86::EH_RETURN64: {
530  OutMI = MCInst();
531  OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));
532  break;
533  }
534 
535  // TAILJMPd, TAILJMPd64 - Lower to the correct jump instructions.
536  case X86::TAILJMPr:
537  case X86::TAILJMPd:
538  case X86::TAILJMPd64: {
539  unsigned Opcode;
540  switch (OutMI.getOpcode()) {
541  default: llvm_unreachable("Invalid opcode");
542  case X86::TAILJMPr: Opcode = X86::JMP32r; break;
543  case X86::TAILJMPd:
544  case X86::TAILJMPd64: Opcode = X86::JMP_1; break;
545  }
546 
547  MCOperand Saved = OutMI.getOperand(0);
548  OutMI = MCInst();
549  OutMI.setOpcode(Opcode);
550  OutMI.addOperand(Saved);
551  break;
552  }
553 
554  case X86::DEC16r:
555  case X86::DEC32r:
556  case X86::INC16r:
557  case X86::INC32r:
558  // If we aren't in 64-bit mode we can use the 1-byte inc/dec instructions.
559  if (!AsmPrinter.getSubtarget().is64Bit()) {
560  unsigned Opcode;
561  switch (OutMI.getOpcode()) {
562  default: llvm_unreachable("Invalid opcode");
563  case X86::DEC16r: Opcode = X86::DEC16r_alt; break;
564  case X86::DEC32r: Opcode = X86::DEC32r_alt; break;
565  case X86::INC16r: Opcode = X86::INC16r_alt; break;
566  case X86::INC32r: Opcode = X86::INC32r_alt; break;
567  }
568  OutMI.setOpcode(Opcode);
569  }
570  break;
571 
572  // These are pseudo-ops for OR to help with the OR->ADD transformation. We do
573  // this with an ugly goto in case the resultant OR uses EAX and needs the
574  // short form.
575  case X86::ADD16rr_DB: OutMI.setOpcode(X86::OR16rr); goto ReSimplify;
576  case X86::ADD32rr_DB: OutMI.setOpcode(X86::OR32rr); goto ReSimplify;
577  case X86::ADD64rr_DB: OutMI.setOpcode(X86::OR64rr); goto ReSimplify;
578  case X86::ADD16ri_DB: OutMI.setOpcode(X86::OR16ri); goto ReSimplify;
579  case X86::ADD32ri_DB: OutMI.setOpcode(X86::OR32ri); goto ReSimplify;
580  case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify;
581  case X86::ADD16ri8_DB: OutMI.setOpcode(X86::OR16ri8); goto ReSimplify;
582  case X86::ADD32ri8_DB: OutMI.setOpcode(X86::OR32ri8); goto ReSimplify;
583  case X86::ADD64ri8_DB: OutMI.setOpcode(X86::OR64ri8); goto ReSimplify;
584 
585  // Atomic load and store require a separate pseudo-inst because Acquire
586  // implies mayStore and Release implies mayLoad; fix these to regular MOV
587  // instructions here
588  case X86::ACQUIRE_MOV8rm: OutMI.setOpcode(X86::MOV8rm); goto ReSimplify;
589  case X86::ACQUIRE_MOV16rm: OutMI.setOpcode(X86::MOV16rm); goto ReSimplify;
590  case X86::ACQUIRE_MOV32rm: OutMI.setOpcode(X86::MOV32rm); goto ReSimplify;
591  case X86::ACQUIRE_MOV64rm: OutMI.setOpcode(X86::MOV64rm); goto ReSimplify;
592  case X86::RELEASE_MOV8mr: OutMI.setOpcode(X86::MOV8mr); goto ReSimplify;
593  case X86::RELEASE_MOV16mr: OutMI.setOpcode(X86::MOV16mr); goto ReSimplify;
594  case X86::RELEASE_MOV32mr: OutMI.setOpcode(X86::MOV32mr); goto ReSimplify;
595  case X86::RELEASE_MOV64mr: OutMI.setOpcode(X86::MOV64mr); goto ReSimplify;
596  case X86::RELEASE_MOV8mi: OutMI.setOpcode(X86::MOV8mi); goto ReSimplify;
597  case X86::RELEASE_MOV16mi: OutMI.setOpcode(X86::MOV16mi); goto ReSimplify;
598  case X86::RELEASE_MOV32mi: OutMI.setOpcode(X86::MOV32mi); goto ReSimplify;
599  case X86::RELEASE_MOV64mi32: OutMI.setOpcode(X86::MOV64mi32); goto ReSimplify;
600  case X86::RELEASE_ADD8mi: OutMI.setOpcode(X86::ADD8mi); goto ReSimplify;
601  case X86::RELEASE_ADD32mi: OutMI.setOpcode(X86::ADD32mi); goto ReSimplify;
602  case X86::RELEASE_ADD64mi32: OutMI.setOpcode(X86::ADD64mi32); goto ReSimplify;
603  case X86::RELEASE_AND8mi: OutMI.setOpcode(X86::AND8mi); goto ReSimplify;
604  case X86::RELEASE_AND32mi: OutMI.setOpcode(X86::AND32mi); goto ReSimplify;
605  case X86::RELEASE_AND64mi32: OutMI.setOpcode(X86::AND64mi32); goto ReSimplify;
606  case X86::RELEASE_OR8mi: OutMI.setOpcode(X86::OR8mi); goto ReSimplify;
607  case X86::RELEASE_OR32mi: OutMI.setOpcode(X86::OR32mi); goto ReSimplify;
608  case X86::RELEASE_OR64mi32: OutMI.setOpcode(X86::OR64mi32); goto ReSimplify;
609  case X86::RELEASE_XOR8mi: OutMI.setOpcode(X86::XOR8mi); goto ReSimplify;
610  case X86::RELEASE_XOR32mi: OutMI.setOpcode(X86::XOR32mi); goto ReSimplify;
611  case X86::RELEASE_XOR64mi32: OutMI.setOpcode(X86::XOR64mi32); goto ReSimplify;
612  case X86::RELEASE_INC8m: OutMI.setOpcode(X86::INC8m); goto ReSimplify;
613  case X86::RELEASE_INC16m: OutMI.setOpcode(X86::INC16m); goto ReSimplify;
614  case X86::RELEASE_INC32m: OutMI.setOpcode(X86::INC32m); goto ReSimplify;
615  case X86::RELEASE_INC64m: OutMI.setOpcode(X86::INC64m); goto ReSimplify;
616  case X86::RELEASE_DEC8m: OutMI.setOpcode(X86::DEC8m); goto ReSimplify;
617  case X86::RELEASE_DEC16m: OutMI.setOpcode(X86::DEC16m); goto ReSimplify;
618  case X86::RELEASE_DEC32m: OutMI.setOpcode(X86::DEC32m); goto ReSimplify;
619  case X86::RELEASE_DEC64m: OutMI.setOpcode(X86::DEC64m); goto ReSimplify;
620 
621  // We don't currently select the correct instruction form for instructions
622  // which have a short %eax, etc. form. Handle this by custom lowering, for
623  // now.
624  //
625  // Note, we are currently not handling the following instructions:
626  // MOV64ao8, MOV64o8a
627  // XCHG16ar, XCHG32ar, XCHG64ar
628  case X86::MOV8mr_NOREX:
629  case X86::MOV8mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8o32a); break;
630  case X86::MOV8rm_NOREX:
631  case X86::MOV8rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8ao32); break;
632  case X86::MOV16mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16o32a); break;
633  case X86::MOV16rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16ao32); break;
634  case X86::MOV32mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32o32a); break;
635  case X86::MOV32rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32ao32); break;
636 
637  case X86::ADC8ri: SimplifyShortImmForm(OutMI, X86::ADC8i8); break;
638  case X86::ADC16ri: SimplifyShortImmForm(OutMI, X86::ADC16i16); break;
639  case X86::ADC32ri: SimplifyShortImmForm(OutMI, X86::ADC32i32); break;
640  case X86::ADC64ri32: SimplifyShortImmForm(OutMI, X86::ADC64i32); break;
641  case X86::ADD8ri: SimplifyShortImmForm(OutMI, X86::ADD8i8); break;
642  case X86::ADD16ri: SimplifyShortImmForm(OutMI, X86::ADD16i16); break;
643  case X86::ADD32ri: SimplifyShortImmForm(OutMI, X86::ADD32i32); break;
644  case X86::ADD64ri32: SimplifyShortImmForm(OutMI, X86::ADD64i32); break;
645  case X86::AND8ri: SimplifyShortImmForm(OutMI, X86::AND8i8); break;
646  case X86::AND16ri: SimplifyShortImmForm(OutMI, X86::AND16i16); break;
647  case X86::AND32ri: SimplifyShortImmForm(OutMI, X86::AND32i32); break;
648  case X86::AND64ri32: SimplifyShortImmForm(OutMI, X86::AND64i32); break;
649  case X86::CMP8ri: SimplifyShortImmForm(OutMI, X86::CMP8i8); break;
650  case X86::CMP16ri: SimplifyShortImmForm(OutMI, X86::CMP16i16); break;
651  case X86::CMP32ri: SimplifyShortImmForm(OutMI, X86::CMP32i32); break;
652  case X86::CMP64ri32: SimplifyShortImmForm(OutMI, X86::CMP64i32); break;
653  case X86::OR8ri: SimplifyShortImmForm(OutMI, X86::OR8i8); break;
654  case X86::OR16ri: SimplifyShortImmForm(OutMI, X86::OR16i16); break;
655  case X86::OR32ri: SimplifyShortImmForm(OutMI, X86::OR32i32); break;
656  case X86::OR64ri32: SimplifyShortImmForm(OutMI, X86::OR64i32); break;
657  case X86::SBB8ri: SimplifyShortImmForm(OutMI, X86::SBB8i8); break;
658  case X86::SBB16ri: SimplifyShortImmForm(OutMI, X86::SBB16i16); break;
659  case X86::SBB32ri: SimplifyShortImmForm(OutMI, X86::SBB32i32); break;
660  case X86::SBB64ri32: SimplifyShortImmForm(OutMI, X86::SBB64i32); break;
661  case X86::SUB8ri: SimplifyShortImmForm(OutMI, X86::SUB8i8); break;
662  case X86::SUB16ri: SimplifyShortImmForm(OutMI, X86::SUB16i16); break;
663  case X86::SUB32ri: SimplifyShortImmForm(OutMI, X86::SUB32i32); break;
664  case X86::SUB64ri32: SimplifyShortImmForm(OutMI, X86::SUB64i32); break;
665  case X86::TEST8ri: SimplifyShortImmForm(OutMI, X86::TEST8i8); break;
666  case X86::TEST16ri: SimplifyShortImmForm(OutMI, X86::TEST16i16); break;
667  case X86::TEST32ri: SimplifyShortImmForm(OutMI, X86::TEST32i32); break;
668  case X86::TEST64ri32: SimplifyShortImmForm(OutMI, X86::TEST64i32); break;
669  case X86::XOR8ri: SimplifyShortImmForm(OutMI, X86::XOR8i8); break;
670  case X86::XOR16ri: SimplifyShortImmForm(OutMI, X86::XOR16i16); break;
671  case X86::XOR32ri: SimplifyShortImmForm(OutMI, X86::XOR32i32); break;
672  case X86::XOR64ri32: SimplifyShortImmForm(OutMI, X86::XOR64i32); break;
673 
674  // Try to shrink some forms of movsx.
675  case X86::MOVSX16rr8:
676  case X86::MOVSX32rr16:
677  case X86::MOVSX64rr32:
678  SimplifyMOVSX(OutMI);
679  break;
680  }
681 }
682 
683 void X86AsmPrinter::LowerTlsAddr(X86MCInstLower &MCInstLowering,
684  const MachineInstr &MI) {
685 
686  bool is64Bits = MI.getOpcode() == X86::TLS_addr64 ||
687  MI.getOpcode() == X86::TLS_base_addr64;
688 
689  bool needsPadding = MI.getOpcode() == X86::TLS_addr64;
690 
691  MCContext &context = OutStreamer->getContext();
692 
693  if (needsPadding)
694  EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
695 
697  switch (MI.getOpcode()) {
698  case X86::TLS_addr32:
699  case X86::TLS_addr64:
701  break;
702  case X86::TLS_base_addr32:
704  break;
705  case X86::TLS_base_addr64:
707  break;
708  default:
709  llvm_unreachable("unexpected opcode");
710  }
711 
712  MCSymbol *sym = MCInstLowering.GetSymbolFromOperand(MI.getOperand(3));
713  const MCSymbolRefExpr *symRef = MCSymbolRefExpr::create(sym, SRVK, context);
714 
715  MCInst LEA;
716  if (is64Bits) {
717  LEA.setOpcode(X86::LEA64r);
718  LEA.addOperand(MCOperand::createReg(X86::RDI)); // dest
719  LEA.addOperand(MCOperand::createReg(X86::RIP)); // base
720  LEA.addOperand(MCOperand::createImm(1)); // scale
721  LEA.addOperand(MCOperand::createReg(0)); // index
722  LEA.addOperand(MCOperand::createExpr(symRef)); // disp
723  LEA.addOperand(MCOperand::createReg(0)); // seg
724  } else if (SRVK == MCSymbolRefExpr::VK_TLSLDM) {
725  LEA.setOpcode(X86::LEA32r);
726  LEA.addOperand(MCOperand::createReg(X86::EAX)); // dest
727  LEA.addOperand(MCOperand::createReg(X86::EBX)); // base
728  LEA.addOperand(MCOperand::createImm(1)); // scale
729  LEA.addOperand(MCOperand::createReg(0)); // index
730  LEA.addOperand(MCOperand::createExpr(symRef)); // disp
731  LEA.addOperand(MCOperand::createReg(0)); // seg
732  } else {
733  LEA.setOpcode(X86::LEA32r);
734  LEA.addOperand(MCOperand::createReg(X86::EAX)); // dest
735  LEA.addOperand(MCOperand::createReg(0)); // base
736  LEA.addOperand(MCOperand::createImm(1)); // scale
737  LEA.addOperand(MCOperand::createReg(X86::EBX)); // index
738  LEA.addOperand(MCOperand::createExpr(symRef)); // disp
739  LEA.addOperand(MCOperand::createReg(0)); // seg
740  }
741  EmitAndCountInstruction(LEA);
742 
743  if (needsPadding) {
744  EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
745  EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
746  EmitAndCountInstruction(MCInstBuilder(X86::REX64_PREFIX));
747  }
748 
749  StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr";
750  MCSymbol *tlsGetAddr = context.getOrCreateSymbol(name);
751  const MCSymbolRefExpr *tlsRef =
752  MCSymbolRefExpr::create(tlsGetAddr,
754  context);
755 
756  EmitAndCountInstruction(MCInstBuilder(is64Bits ? X86::CALL64pcrel32
757  : X86::CALLpcrel32)
758  .addExpr(tlsRef));
759 }
760 
761 /// \brief Emit the optimal amount of multi-byte nops on X86.
762 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, const MCSubtargetInfo &STI) {
763  // This works only for 64bit. For 32bit we have to do additional checking if
764  // the CPU supports multi-byte nops.
765  assert(Is64Bit && "EmitNops only supports X86-64");
766  while (NumBytes) {
767  unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;
768  Opc = IndexReg = Displacement = SegmentReg = 0;
769  BaseReg = X86::RAX; ScaleVal = 1;
770  switch (NumBytes) {
771  case 0: llvm_unreachable("Zero nops?"); break;
772  case 1: NumBytes -= 1; Opc = X86::NOOP; break;
773  case 2: NumBytes -= 2; Opc = X86::XCHG16ar; break;
774  case 3: NumBytes -= 3; Opc = X86::NOOPL; break;
775  case 4: NumBytes -= 4; Opc = X86::NOOPL; Displacement = 8; break;
776  case 5: NumBytes -= 5; Opc = X86::NOOPL; Displacement = 8;
777  IndexReg = X86::RAX; break;
778  case 6: NumBytes -= 6; Opc = X86::NOOPW; Displacement = 8;
779  IndexReg = X86::RAX; break;
780  case 7: NumBytes -= 7; Opc = X86::NOOPL; Displacement = 512; break;
781  case 8: NumBytes -= 8; Opc = X86::NOOPL; Displacement = 512;
782  IndexReg = X86::RAX; break;
783  case 9: NumBytes -= 9; Opc = X86::NOOPW; Displacement = 512;
784  IndexReg = X86::RAX; break;
785  default: NumBytes -= 10; Opc = X86::NOOPW; Displacement = 512;
786  IndexReg = X86::RAX; SegmentReg = X86::CS; break;
787  }
788 
789  unsigned NumPrefixes = std::min(NumBytes, 5U);
790  NumBytes -= NumPrefixes;
791  for (unsigned i = 0; i != NumPrefixes; ++i)
792  OS.EmitBytes("\x66");
793 
794  switch (Opc) {
795  default: llvm_unreachable("Unexpected opcode"); break;
796  case X86::NOOP:
797  OS.EmitInstruction(MCInstBuilder(Opc), STI);
798  break;
799  case X86::XCHG16ar:
800  OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX), STI);
801  break;
802  case X86::NOOPL:
803  case X86::NOOPW:
804  OS.EmitInstruction(MCInstBuilder(Opc).addReg(BaseReg)
805  .addImm(ScaleVal).addReg(IndexReg)
806  .addImm(Displacement).addReg(SegmentReg), STI);
807  break;
808  }
809  } // while (NumBytes)
810 }
811 
812 void X86AsmPrinter::LowerSTATEPOINT(const MachineInstr &MI,
813  X86MCInstLower &MCIL) {
814  assert(Subtarget->is64Bit() && "Statepoint currently only supports X86-64");
815 
816  StatepointOpers SOpers(&MI);
817  if (unsigned PatchBytes = SOpers.getNumPatchBytes()) {
818  EmitNops(*OutStreamer, PatchBytes, Subtarget->is64Bit(),
819  getSubtargetInfo());
820  } else {
821  // Lower call target and choose correct opcode
822  const MachineOperand &CallTarget = SOpers.getCallTarget();
823  MCOperand CallTargetMCOp;
824  unsigned CallOpcode;
825  switch (CallTarget.getType()) {
828  CallTargetMCOp = MCIL.LowerSymbolOperand(
829  CallTarget, MCIL.GetSymbolFromOperand(CallTarget));
830  CallOpcode = X86::CALL64pcrel32;
831  // Currently, we only support relative addressing with statepoints.
832  // Otherwise, we'll need a scratch register to hold the target
833  // address. You'll fail asserts during load & relocation if this
834  // symbol is to far away. (TODO: support non-relative addressing)
835  break;
837  CallTargetMCOp = MCOperand::createImm(CallTarget.getImm());
838  CallOpcode = X86::CALL64pcrel32;
839  // Currently, we only support relative addressing with statepoints.
840  // Otherwise, we'll need a scratch register to hold the target
841  // immediate. You'll fail asserts during load & relocation if this
842  // address is to far away. (TODO: support non-relative addressing)
843  break;
845  CallTargetMCOp = MCOperand::createReg(CallTarget.getReg());
846  CallOpcode = X86::CALL64r;
847  break;
848  default:
849  llvm_unreachable("Unsupported operand type in statepoint call target");
850  break;
851  }
852 
853  // Emit call
855  CallInst.setOpcode(CallOpcode);
856  CallInst.addOperand(CallTargetMCOp);
857  OutStreamer->EmitInstruction(CallInst, getSubtargetInfo());
858  }
859 
860  // Record our statepoint node in the same section used by STACKMAP
861  // and PATCHPOINT
862  SM.recordStatepoint(MI);
863 }
864 
865 void X86AsmPrinter::LowerFAULTING_LOAD_OP(const MachineInstr &MI,
866  X86MCInstLower &MCIL) {
867  // FAULTING_LOAD_OP <def>, <handler label>, <load opcode>, <load operands>
868 
869  unsigned LoadDefRegister = MI.getOperand(0).getReg();
870  MCSymbol *HandlerLabel = MI.getOperand(1).getMCSymbol();
871  unsigned LoadOpcode = MI.getOperand(2).getImm();
872  unsigned LoadOperandsBeginIdx = 3;
873 
874  FM.recordFaultingOp(FaultMaps::FaultingLoad, HandlerLabel);
875 
876  MCInst LoadMI;
877  LoadMI.setOpcode(LoadOpcode);
878  LoadMI.addOperand(MCOperand::createReg(LoadDefRegister));
879  for (auto I = MI.operands_begin() + LoadOperandsBeginIdx,
880  E = MI.operands_end();
881  I != E; ++I)
882  if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, *I))
883  LoadMI.addOperand(MaybeOperand.getValue());
884 
885  OutStreamer->EmitInstruction(LoadMI, getSubtargetInfo());
886 }
887 
888 // Lower a stackmap of the form:
889 // <id>, <shadowBytes>, ...
890 void X86AsmPrinter::LowerSTACKMAP(const MachineInstr &MI) {
891  SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
892  SM.recordStackMap(MI);
893  unsigned NumShadowBytes = MI.getOperand(1).getImm();
894  SMShadowTracker.reset(NumShadowBytes);
895 }
896 
897 // Lower a patchpoint of the form:
898 // [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ...
899 void X86AsmPrinter::LowerPATCHPOINT(const MachineInstr &MI,
900  X86MCInstLower &MCIL) {
901  assert(Subtarget->is64Bit() && "Patchpoint currently only supports X86-64");
902 
903  SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
904 
905  SM.recordPatchPoint(MI);
906 
907  PatchPointOpers opers(&MI);
908  unsigned ScratchIdx = opers.getNextScratchIdx();
909  unsigned EncodedBytes = 0;
910  const MachineOperand &CalleeMO =
911  opers.getMetaOper(PatchPointOpers::TargetPos);
912 
913  // Check for null target. If target is non-null (i.e. is non-zero or is
914  // symbolic) then emit a call.
915  if (!(CalleeMO.isImm() && !CalleeMO.getImm())) {
916  MCOperand CalleeMCOp;
917  switch (CalleeMO.getType()) {
918  default:
919  /// FIXME: Add a verifier check for bad callee types.
920  llvm_unreachable("Unrecognized callee operand type.");
922  if (CalleeMO.getImm())
923  CalleeMCOp = MCOperand::createImm(CalleeMO.getImm());
924  break;
927  CalleeMCOp =
928  MCIL.LowerSymbolOperand(CalleeMO,
929  MCIL.GetSymbolFromOperand(CalleeMO));
930  break;
931  }
932 
933  // Emit MOV to materialize the target address and the CALL to target.
934  // This is encoded with 12-13 bytes, depending on which register is used.
935  unsigned ScratchReg = MI.getOperand(ScratchIdx).getReg();
936  if (X86II::isX86_64ExtendedReg(ScratchReg))
937  EncodedBytes = 13;
938  else
939  EncodedBytes = 12;
940 
941  EmitAndCountInstruction(
942  MCInstBuilder(X86::MOV64ri).addReg(ScratchReg).addOperand(CalleeMCOp));
943  EmitAndCountInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg));
944  }
945 
946  // Emit padding.
947  unsigned NumBytes = opers.getMetaOper(PatchPointOpers::NBytesPos).getImm();
948  assert(NumBytes >= EncodedBytes &&
949  "Patchpoint can't request size less than the length of a call.");
950 
951  EmitNops(*OutStreamer, NumBytes - EncodedBytes, Subtarget->is64Bit(),
952  getSubtargetInfo());
953 }
954 
955 // Returns instruction preceding MBBI in MachineFunction.
956 // If MBBI is the first instruction of the first basic block, returns null.
959  const MachineBasicBlock *MBB = MBBI->getParent();
960  while (MBBI == MBB->begin()) {
961  if (MBB == MBB->getParent()->begin())
962  return nullptr;
963  MBB = MBB->getPrevNode();
964  MBBI = MBB->end();
965  }
966  return --MBBI;
967 }
968 
969 static const Constant *getConstantFromPool(const MachineInstr &MI,
970  const MachineOperand &Op) {
971  if (!Op.isCPI())
972  return nullptr;
973 
976  const MachineConstantPoolEntry &ConstantEntry =
977  Constants[Op.getIndex()];
978 
979  // Bail if this is a machine constant pool entry, we won't be able to dig out
980  // anything useful.
981  if (ConstantEntry.isMachineConstantPoolEntry())
982  return nullptr;
983 
984  auto *C = dyn_cast<Constant>(ConstantEntry.Val.ConstVal);
985  assert((!C || ConstantEntry.getType() == C->getType()) &&
986  "Expected a constant of the same type!");
987  return C;
988 }
989 
990 static std::string getShuffleComment(const MachineOperand &DstOp,
991  const MachineOperand &SrcOp,
992  ArrayRef<int> Mask) {
993  std::string Comment;
994 
995  // Compute the name for a register. This is really goofy because we have
996  // multiple instruction printers that could (in theory) use different
997  // names. Fortunately most people use the ATT style (outside of Windows)
998  // and they actually agree on register naming here. Ultimately, this is
999  // a comment, and so its OK if it isn't perfect.
1000  auto GetRegisterName = [](unsigned RegNum) -> StringRef {
1001  return X86ATTInstPrinter::getRegisterName(RegNum);
1002  };
1003 
1004  StringRef DstName = DstOp.isReg() ? GetRegisterName(DstOp.getReg()) : "mem";
1005  StringRef SrcName = SrcOp.isReg() ? GetRegisterName(SrcOp.getReg()) : "mem";
1006 
1007  raw_string_ostream CS(Comment);
1008  CS << DstName << " = ";
1009  bool NeedComma = false;
1010  bool InSrc = false;
1011  for (int M : Mask) {
1012  // Wrap up any prior entry...
1013  if (M == SM_SentinelZero && InSrc) {
1014  InSrc = false;
1015  CS << "]";
1016  }
1017  if (NeedComma)
1018  CS << ",";
1019  else
1020  NeedComma = true;
1021 
1022  // Print this shuffle...
1023  if (M == SM_SentinelZero) {
1024  CS << "zero";
1025  } else {
1026  if (!InSrc) {
1027  InSrc = true;
1028  CS << SrcName << "[";
1029  }
1030  if (M == SM_SentinelUndef)
1031  CS << "u";
1032  else
1033  CS << M;
1034  }
1035  }
1036  if (InSrc)
1037  CS << "]";
1038  CS.flush();
1039 
1040  return Comment;
1041 }
1042 
1044  X86MCInstLower MCInstLowering(*MF, *this);
1045  const X86RegisterInfo *RI = MF->getSubtarget<X86Subtarget>().getRegisterInfo();
1046 
1047  switch (MI->getOpcode()) {
1049  llvm_unreachable("Should be handled target independently");
1050 
1051  // Emit nothing here but a comment if we can.
1052  case X86::Int_MemBarrier:
1053  OutStreamer->emitRawComment("MEMBARRIER");
1054  return;
1055 
1056 
1057  case X86::EH_RETURN:
1058  case X86::EH_RETURN64: {
1059  // Lower these as normal, but add some comments.
1060  unsigned Reg = MI->getOperand(0).getReg();
1061  OutStreamer->AddComment(StringRef("eh_return, addr: %") +
1063  break;
1064  }
1065  case X86::TAILJMPr:
1066  case X86::TAILJMPm:
1067  case X86::TAILJMPd:
1068  case X86::TAILJMPr64:
1069  case X86::TAILJMPm64:
1070  case X86::TAILJMPd64:
1071  case X86::TAILJMPr64_REX:
1072  case X86::TAILJMPm64_REX:
1073  case X86::TAILJMPd64_REX:
1074  // Lower these as normal, but add some comments.
1075  OutStreamer->AddComment("TAILCALL");
1076  break;
1077 
1078  case X86::TLS_addr32:
1079  case X86::TLS_addr64:
1080  case X86::TLS_base_addr32:
1081  case X86::TLS_base_addr64:
1082  return LowerTlsAddr(MCInstLowering, *MI);
1083 
1084  case X86::MOVPC32r: {
1085  // This is a pseudo op for a two instruction sequence with a label, which
1086  // looks like:
1087  // call "L1$pb"
1088  // "L1$pb":
1089  // popl %esi
1090 
1091  // Emit the call.
1092  MCSymbol *PICBase = MF->getPICBaseSymbol();
1093  // FIXME: We would like an efficient form for this, so we don't have to do a
1094  // lot of extra uniquing.
1095  EmitAndCountInstruction(MCInstBuilder(X86::CALLpcrel32)
1096  .addExpr(MCSymbolRefExpr::create(PICBase, OutContext)));
1097 
1098  // Emit the label.
1099  OutStreamer->EmitLabel(PICBase);
1100 
1101  // popl $reg
1102  EmitAndCountInstruction(MCInstBuilder(X86::POP32r)
1103  .addReg(MI->getOperand(0).getReg()));
1104  return;
1105  }
1106 
1107  case X86::ADD32ri: {
1108  // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
1110  break;
1111 
1112  // Okay, we have something like:
1113  // EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
1114 
1115  // For this, we want to print something like:
1116  // MYGLOBAL + (. - PICBASE)
1117  // However, we can't generate a ".", so just emit a new label here and refer
1118  // to it.
1119  MCSymbol *DotSym = OutContext.createTempSymbol();
1120  OutStreamer->EmitLabel(DotSym);
1121 
1122  // Now that we have emitted the label, lower the complex operand expression.
1123  MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
1124 
1125  const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext);
1126  const MCExpr *PICBase =
1128  DotExpr = MCBinaryExpr::createSub(DotExpr, PICBase, OutContext);
1129 
1131  DotExpr, OutContext);
1132 
1133  EmitAndCountInstruction(MCInstBuilder(X86::ADD32ri)
1134  .addReg(MI->getOperand(0).getReg())
1135  .addReg(MI->getOperand(1).getReg())
1136  .addExpr(DotExpr));
1137  return;
1138  }
1140  return LowerSTATEPOINT(*MI, MCInstLowering);
1141 
1143  return LowerFAULTING_LOAD_OP(*MI, MCInstLowering);
1144 
1146  return LowerSTACKMAP(*MI);
1147 
1149  return LowerPATCHPOINT(*MI, MCInstLowering);
1150 
1151  case X86::MORESTACK_RET:
1152  EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
1153  return;
1154 
1155  case X86::MORESTACK_RET_RESTORE_R10:
1156  // Return, then restore R10.
1157  EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
1158  EmitAndCountInstruction(MCInstBuilder(X86::MOV64rr)
1159  .addReg(X86::R10)
1160  .addReg(X86::RAX));
1161  return;
1162 
1163  case X86::SEH_PushReg:
1164  OutStreamer->EmitWinCFIPushReg(RI->getSEHRegNum(MI->getOperand(0).getImm()));
1165  return;
1166 
1167  case X86::SEH_SaveReg:
1168  OutStreamer->EmitWinCFISaveReg(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1169  MI->getOperand(1).getImm());
1170  return;
1171 
1172  case X86::SEH_SaveXMM:
1173  OutStreamer->EmitWinCFISaveXMM(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1174  MI->getOperand(1).getImm());
1175  return;
1176 
1177  case X86::SEH_StackAlloc:
1178  OutStreamer->EmitWinCFIAllocStack(MI->getOperand(0).getImm());
1179  return;
1180 
1181  case X86::SEH_SetFrame:
1182  OutStreamer->EmitWinCFISetFrame(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1183  MI->getOperand(1).getImm());
1184  return;
1185 
1186  case X86::SEH_PushFrame:
1187  OutStreamer->EmitWinCFIPushFrame(MI->getOperand(0).getImm());
1188  return;
1189 
1190  case X86::SEH_EndPrologue:
1191  OutStreamer->EmitWinCFIEndProlog();
1192  return;
1193 
1194  case X86::SEH_Epilogue: {
1196  // Check if preceded by a call and emit nop if so.
1197  for (MBBI = PrevCrossBBInst(MBBI); MBBI; MBBI = PrevCrossBBInst(MBBI)) {
1198  // Conservatively assume that pseudo instructions don't emit code and keep
1199  // looking for a call. We may emit an unnecessary nop in some cases.
1200  if (!MBBI->isPseudo()) {
1201  if (MBBI->isCall())
1202  EmitAndCountInstruction(MCInstBuilder(X86::NOOP));
1203  break;
1204  }
1205  }
1206  return;
1207  }
1208 
1209  // Lower PSHUFB and VPERMILP normally but add a comment if we can find
1210  // a constant shuffle mask. We won't be able to do this at the MC layer
1211  // because the mask isn't an immediate.
1212  case X86::PSHUFBrm:
1213  case X86::VPSHUFBrm:
1214  case X86::VPSHUFBYrm: {
1215  if (!OutStreamer->isVerboseAsm())
1216  break;
1217  assert(MI->getNumOperands() > 5 &&
1218  "We should always have at least 5 operands!");
1219  const MachineOperand &DstOp = MI->getOperand(0);
1220  const MachineOperand &SrcOp = MI->getOperand(1);
1221  const MachineOperand &MaskOp = MI->getOperand(5);
1222 
1223  if (auto *C = getConstantFromPool(*MI, MaskOp)) {
1224  SmallVector<int, 16> Mask;
1225  DecodePSHUFBMask(C, Mask);
1226  if (!Mask.empty())
1227  OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp, Mask));
1228  }
1229  break;
1230  }
1231  case X86::VPERMILPSrm:
1232  case X86::VPERMILPDrm:
1233  case X86::VPERMILPSYrm:
1234  case X86::VPERMILPDYrm: {
1235  if (!OutStreamer->isVerboseAsm())
1236  break;
1237  assert(MI->getNumOperands() > 5 &&
1238  "We should always have at least 5 operands!");
1239  const MachineOperand &DstOp = MI->getOperand(0);
1240  const MachineOperand &SrcOp = MI->getOperand(1);
1241  const MachineOperand &MaskOp = MI->getOperand(5);
1242 
1243  if (auto *C = getConstantFromPool(*MI, MaskOp)) {
1244  SmallVector<int, 16> Mask;
1245  DecodeVPERMILPMask(C, Mask);
1246  if (!Mask.empty())
1247  OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp, Mask));
1248  }
1249  break;
1250  }
1251 
1252  // For loads from a constant pool to a vector register, print the constant
1253  // loaded.
1254  case X86::MOVAPDrm:
1255  case X86::VMOVAPDrm:
1256  case X86::VMOVAPDYrm:
1257  case X86::MOVUPDrm:
1258  case X86::VMOVUPDrm:
1259  case X86::VMOVUPDYrm:
1260  case X86::MOVAPSrm:
1261  case X86::VMOVAPSrm:
1262  case X86::VMOVAPSYrm:
1263  case X86::MOVUPSrm:
1264  case X86::VMOVUPSrm:
1265  case X86::VMOVUPSYrm:
1266  case X86::MOVDQArm:
1267  case X86::VMOVDQArm:
1268  case X86::VMOVDQAYrm:
1269  case X86::MOVDQUrm:
1270  case X86::VMOVDQUrm:
1271  case X86::VMOVDQUYrm:
1272  if (!OutStreamer->isVerboseAsm())
1273  break;
1274  if (MI->getNumOperands() > 4)
1275  if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) {
1276  std::string Comment;
1277  raw_string_ostream CS(Comment);
1278  const MachineOperand &DstOp = MI->getOperand(0);
1279  CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = ";
1280  if (auto *CDS = dyn_cast<ConstantDataSequential>(C)) {
1281  CS << "[";
1282  for (int i = 0, NumElements = CDS->getNumElements(); i < NumElements; ++i) {
1283  if (i != 0)
1284  CS << ",";
1285  if (CDS->getElementType()->isIntegerTy())
1286  CS << CDS->getElementAsInteger(i);
1287  else if (CDS->getElementType()->isFloatTy())
1288  CS << CDS->getElementAsFloat(i);
1289  else if (CDS->getElementType()->isDoubleTy())
1290  CS << CDS->getElementAsDouble(i);
1291  else
1292  CS << "?";
1293  }
1294  CS << "]";
1295  OutStreamer->AddComment(CS.str());
1296  } else if (auto *CV = dyn_cast<ConstantVector>(C)) {
1297  CS << "<";
1298  for (int i = 0, NumOperands = CV->getNumOperands(); i < NumOperands; ++i) {
1299  if (i != 0)
1300  CS << ",";
1301  Constant *COp = CV->getOperand(i);
1302  if (isa<UndefValue>(COp)) {
1303  CS << "u";
1304  } else if (auto *CI = dyn_cast<ConstantInt>(COp)) {
1305  CS << CI->getZExtValue();
1306  } else if (auto *CF = dyn_cast<ConstantFP>(COp)) {
1307  SmallString<32> Str;
1308  CF->getValueAPF().toString(Str);
1309  CS << Str;
1310  } else {
1311  CS << "?";
1312  }
1313  }
1314  CS << ">";
1315  OutStreamer->AddComment(CS.str());
1316  }
1317  }
1318  break;
1319  }
1320 
1321  MCInst TmpInst;
1322  MCInstLowering.Lower(MI, TmpInst);
1323 
1324  // Stackmap shadows cannot include branch targets, so we can count the bytes
1325  // in a call towards the shadow, but must ensure that the no thread returns
1326  // in to the stackmap shadow. The only way to achieve this is if the call
1327  // is at the end of the shadow.
1328  if (MI->isCall()) {
1329  // Count then size of the call towards the shadow
1330  SMShadowTracker.count(TmpInst, getSubtargetInfo());
1331  // Then flush the shadow so that we fill with nops before the call, not
1332  // after it.
1333  SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
1334  // Then emit the call
1335  OutStreamer->EmitInstruction(TmpInst, getSubtargetInfo());
1336  return;
1337  }
1338 
1339  EmitAndCountInstruction(TmpInst);
1340 }
MO_SECREL - On a symbol operand this indicates that the immediate is the offset from beginning of sec...
Definition: X86BaseInfo.h:216
const NoneType None
Definition: None.h:23
bool isImplicit() const
MO_DLLIMPORT - On a symbol operand, this represents that the reference to the symbol is for an import...
Definition: ARMBaseInfo.h:303
StubValueTy & getHiddenGVStubEntry(MCSymbol *Sym)
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:104
mop_iterator operands_end()
Definition: MachineInstr.h:290
virtual void AddComment(const Twine &T)
Add a textual command.
Definition: MCStreamer.h:252
const GlobalValue * getGlobal() const
static const char * getRegisterName(unsigned RegNo)
AddrSegmentReg - The operand # of the segment in the memory operand.
Definition: X86BaseInfo.h:39
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
Definition: AsmPrinter.h:83
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:315
MCSymbol * getSymbol(const GlobalValue *GV) const
Definition: AsmPrinter.cpp:339
virtual void EmitWinCFIEndProlog()
Definition: MCStreamer.cpp:550
MO_TLSLDM - Represents the offset into the global offset table at which.
Definition: MipsBaseInfo.h:64
bool isReg() const
Definition: MCInst.h:56
MachineBasicBlock * getMBB() const
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:39
MO_TLSLD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with ...
Definition: X86BaseInfo.h:113
MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate is some TLS offset from the ...
Definition: X86BaseInfo.h:210
MCContext & OutContext
This is the context for the output file that we are streaming.
Definition: AsmPrinter.h:78
static MachineModuleInfoMachO & getMachOMMI(AsmPrinter &AP)
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:129
MO_TLSGD - Represents the offset into the global offset table at which.
Definition: MipsBaseInfo.h:59
virtual void EmitBytes(StringRef Data)
Emit the bytes in Data into the output.
Definition: MCStreamer.cpp:681
A Stackmap instruction captures the location of live variables at its position in the instruction str...
CallInst - This class represents a function call, abstracting a target machine's calling convention...
const MachineFunction * MF
The current machine function.
Definition: AsmPrinter.h:86
const char * getPrivateGlobalPrefix() const
Definition: DataLayout.h:281
StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition: StringRef.h:405
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:488
const char * getSymbolName() const
F(f)
MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...
Definition: X86BaseInfo.h:87
MO_DTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry with...
Definition: X86BaseInfo.h:156
const MCSubtargetInfo & getSubtargetInfo() const
Return information about subtarget.
Definition: AsmPrinter.cpp:143
static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, const MCSubtargetInfo &STI)
Emit the optimal amount of multi-byte nops on X86.
MO_PLT - On a symbol operand, this represents an ELF PLT reference on a call operand.
Definition: ARMBaseInfo.h:294
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:295
print alias Alias Set Printer
virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
Definition: MCStreamer.cpp:639
void getNameWithPrefix(SmallVectorImpl< char > &Name, const GlobalValue *GV) const
Definition: AsmPrinter.cpp:334
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates that the reference is actually...
Definition: X86BaseInfo.h:192
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:111
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
bool hasInternalLinkage() const
Definition: GlobalValue.h:278
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:33
Name of external global symbol.
Reg
All possible values of the reg field in the ModR/M byte.
NodeTy * getPrevNode()
Get the previous node, or 0 for the list head.
Definition: ilist_node.h:58
MCSymbol * GetJTISymbol(unsigned JTID, bool isLinkerPrivate=false) const
Return the symbol for the specified jump table entry.
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:159
Number of individual test Apply this number of consecutive mutations to each input exit after the first new interesting input is found the minimized corpus is saved into the first input directory Number of jobs to run If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
virtual bool isVerboseAsm() const
Return true if this streamer supports verbose assembly and if it is enabled.
Definition: MCStreamer.h:233
#define false
Definition: ConvertUTF.c:65
MCContext & getContext() const
Definition: MCStreamer.h:210
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:271
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
Context object for machine code objects.
Definition: MCContext.h:48
void recordFaultingOp(FaultKind FaultTy, const MCSymbol *HandlerLabel)
Definition: FaultMaps.cpp:28
Mangler * Mang
Name-mangler for global names.
Definition: AsmPrinter.h:93
AddrNumOperands - Total number of operands in a memory reference.
Definition: X86BaseInfo.h:42
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:514
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Definition: SmallVector.h:57
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:63
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:294
MO_GOTTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry wi...
Definition: X86BaseInfo.h:131
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: ArrayRef.h:31
virtual void emitRawComment(const Twine &T, bool TabPrefix=true)
Print T and prefix it with the comment string (normally #) and optionally a tab.
Definition: MCStreamer.cpp:69
This class is a data container for one entry in a MachineConstantPool.
int64_t getImm() const
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:446
MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the reference is actually to the "...
Definition: X86BaseInfo.h:187
void recordStatepoint(const MachineInstr &MI)
Generate a stackmap record for a statepoint instruction.
Definition: StackMaps.cpp:371
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:150
MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates that the reference is a...
Definition: X86BaseInfo.h:198
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:267
bool isMachineConstantPoolEntry() const
isMachineConstantPoolEntry - Return true if the MachineConstantPoolEntry is indeed a target specific ...
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:120
bool isX86_64ExtendedReg(unsigned RegNo)
isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or higher) register? e.g.
Definition: X86BaseInfo.h:722
bool isImm() const
Definition: MCInst.h:57
MO_DARWIN_STUB - On a symbol operand "FOO", this indicates that the reference is actually to the "FOO...
Definition: X86BaseInfo.h:182
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:58
DBG_VALUE - a mapping of the llvm.dbg.value intrinsic.
Definition: TargetOpcodes.h:69
const MCExpr * getExpr() const
Definition: MCInst.h:93
Loading instruction that may page fault, bundled with associated information on how to handle such a ...
Address of a global value.
unsigned getTargetFlags() const
Streaming machine code generation interface.
Definition: MCStreamer.h:157
Patchable call instruction - this instruction represents a call to a constant address, followed by a series of NOPs.
MCSymbol * createTempSymbol(bool CanBeUnnamed=true)
Create and return a new assembler temporary symbol with a unique but unspecified name.
Definition: MCContext.cpp:222
MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a relocation of: SYMBOL_LABEL + [...
Definition: X86BaseInfo.h:60
PointerIntPair - This class implements a pair of a pointer and small integer.
MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry w...
Definition: X86BaseInfo.h:172
MO_TLVP - On a symbol operand this indicates that the immediate is some TLS offset.
Definition: X86BaseInfo.h:204
virtual void EmitWinCFIPushReg(unsigned Register)
Definition: MCStreamer.cpp:470
This is an important base class in LLVM.
Definition: Constant.h:41
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
void DecodePSHUFBMask(const Constant *C, SmallVectorImpl< int > &ShuffleMask)
Decode a PSHUFB mask from an IR-level vector constant.
This class is intended to be used as a driving class for all asm writers.
Definition: AsmPrinter.h:66
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
bool isExpr() const
Definition: MCInst.h:59
static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst, unsigned Opcode)
Simplify things like MOV32rm to MOV32o32a.
Value * getOperand(unsigned i) const
Definition: User.h:118
int64_t getOffset() const
Return the offset from the symbol in this operand.
MO_NTPOFF - On a symbol operand this indicates that the immediate is the negative thread-pointer offs...
Definition: X86BaseInfo.h:164
MI-level patchpoint operands.
Definition: StackMaps.h:40
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
static const Constant * getConstantFromPool(const MachineInstr &MI, const MachineOperand &Op)
MCSymbol * getSymbol() const
getSymbol - Return the MCSymbol for this basic block.
StubValueTy & getGVStubEntry(MCSymbol *Sym)
std::string & str()
Flushes the stream contents to the target string and returns the string's reference.
Definition: raw_ostream.h:480
void recordPatchPoint(const MachineInstr &MI)
Generate a stackmap record for a patchpoint instruction.
Definition: StackMaps.cpp:350
MO_TPOFF - On a symbol operand this indicates that the immediate is the thread-pointer offset for the...
Definition: X86BaseInfo.h:148
PointerTy getPointer() const
void setOpcode(unsigned Op)
Definition: MCInst.h:158
MCSymbol * getPICBaseSymbol() const
getPICBaseSymbol - Return a function-local symbol to represent the PIC base.
virtual void EmitLabel(MCSymbol *Symbol)
Emit a label for Symbol into the current section.
Definition: MCStreamer.cpp:203
virtual void EmitWinCFISaveXMM(unsigned Register, unsigned Offset)
Definition: MCStreamer.cpp:525
static MCOperand LowerSymbolOperand(const MachineInstr *MI, const MachineOperand &MO, AsmPrinter &AP)
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:861
int getSEHRegNum(unsigned i) const
const X86Subtarget & getSubtarget() const
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
virtual void EmitWinCFIAllocStack(unsigned Size)
Definition: MCStreamer.cpp:498
void dump() const
unsigned getOpcode() const
Definition: MCInst.h:159
StubValueTy & getFnStubEntry(MCSymbol *Sym)
void recordStackMap(const MachineInstr &MI)
Generate a stackmap record for a stackmap instruction.
Definition: StackMaps.cpp:342
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:285
int64_t getImm() const
Definition: MCInst.h:74
Representation of each machine instruction.
Definition: MachineInstr.h:51
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
bundle_iterator< const MachineInstr, const_instr_iterator > const_iterator
MO_GOTOFF - On a symbol operand this indicates that the immediate is the offset to the location of th...
Definition: X86BaseInfo.h:79
static std::string getShuffleComment(const MachineOperand &DstOp, const MachineOperand &SrcOp, ArrayRef< int > Mask)
static unsigned getRetOpcode(const X86Subtarget &Subtarget)
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:111
void DecodeVPERMILPMask(const Constant *C, SmallVectorImpl< int > &ShuffleMask)
Decode a VPERMILP variable mask from an IR-level vector constant.
Call instruction with associated vm state for deoptimization and list of live pointers for relocation...
unsigned getNumOperands() const
Definition: MCInst.h:166
#define I(x, y, z)
Definition: MD5.cpp:54
MCSymbol * GetBlockAddressSymbol(const BlockAddress *BA) const
Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block.
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:403
MCSymbol * getMCSymbol() const
MCSubtargetInfo - Generic base class for all target subtargets.
MI-level Statepoint operands.
Definition: StackMaps.h:94
union llvm::MachineConstantPoolEntry::@30 Val
The constant itself.
void EmitInstruction(const MachineInstr *MI) override
Targets should implement this to emit instructions.
MachineModuleInfoMachO - This is a MachineModuleInfoImpl implementation for MachO targets...
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 'eh_return' gcc dwarf builtin...
Definition: ISDOpcodes.h:97
virtual MCSymbol * GetCPISymbol(unsigned CPID) const
Return the symbol for the specified constant pool entry.
unsigned getReg() const
getReg - Returns the register number.
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:465
mop_iterator operands_begin()
Definition: MachineInstr.h:289
static const char * name
Primary interface to the complete machine description for the target machine.
MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the immediate should get the value of th...
Definition: X86BaseInfo.h:65
static MachineBasicBlock::const_iterator PrevCrossBBInst(MachineBasicBlock::const_iterator MBBI)
virtual void EmitWinCFISaveReg(unsigned Register, unsigned Offset)
Definition: MCStreamer.cpp:512
virtual void EmitWinCFIPushFrame(bool Code)
Definition: MCStreamer.cpp:538
const std::vector< MachineConstantPoolEntry > & getConstants() const
void addOperand(const MCOperand &Op)
Definition: MCInst.h:168
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:40
const BlockAddress * getBlockAddress() const
static MCSymbol * GetSymbolFromOperand(const MachineOperand &MO, AsmPrinter &AP)
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:33
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:117
static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode)
Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with a short fixed-register form...
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:164
static void SimplifyMOVSX(MCInst &Inst)
If a movsx instruction has a shorter encoding for the used register simplify the instruction to use i...
virtual void EmitWinCFISetFrame(unsigned Register, unsigned Offset)
Definition: MCStreamer.cpp:480
bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:110