LLVM  3.7.0
llvm::SIInstrInfo Member List

This is the complete list of members for llvm::SIInstrInfo, including all inherited members.

AMDGPUInstrInfo(const AMDGPUSubtarget &st)llvm::AMDGPUInstrInfoexplicit
areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const overridellvm::SIInstrInfo
areMemAccessesTriviallyDisjoint(MachineInstr *MIa, MachineInstr *MIb, AliasAnalysis *AA=nullptr) const overridellvm::SIInstrInfo
buildIndirectRead(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned ValueReg, unsigned Address, unsigned OffsetReg) const overridellvm::SIInstrInfovirtual
buildIndirectWrite(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned ValueReg, unsigned Address, unsigned OffsetReg) const overridellvm::SIInstrInfovirtual
buildMovInstr(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned DstReg, unsigned SrcReg) const overridellvm::SIInstrInfovirtual
calculateIndirectAddress(unsigned RegIndex, unsigned Channel) const overridellvm::SIInstrInfovirtual
calculateLDSSpillAddress(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, RegScavenger *RS, unsigned TmpReg, unsigned Offset, unsigned Size) const llvm::SIInstrInfo
canFoldMemoryOperand(const MachineInstr *MI, ArrayRef< unsigned > Ops) const overridellvm::AMDGPUInstrInfo
canReadVGPR(const MachineInstr &MI, unsigned OpNo) const llvm::SIInstrInfo
commuteInstruction(MachineInstr *MI, bool NewMI=false) const overridellvm::SIInstrInfo
commuteOpcode(const MachineInstr &MI) const llvm::SIInstrInfo
convertToThreeAddress(MachineFunction::iterator &MBB, MachineBasicBlock::iterator &MI, LiveVariables *LV) const overridellvm::SIInstrInfo
copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const overridellvm::SIInstrInfo
DefinesPredicate(MachineInstr *MI, std::vector< MachineOperand > &Pred) const overridellvm::AMDGPUInstrInfo
enableClusterLoads() const overridellvm::AMDGPUInstrInfo
expandPostRAPseudo(MachineBasicBlock::iterator MI) const overridellvm::SIInstrInfo
findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const overridellvm::SIInstrInfo
FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, unsigned Reg, MachineRegisterInfo *MRI) const finalllvm::SIInstrInfo
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex) const overridellvm::AMDGPUInstrInfoprotected
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr *LoadMI) const overridellvm::AMDGPUInstrInfoprotected
getDefaultRsrcDataFormat() const llvm::SIInstrInfo
getIndirectAddrRegClass() const overridellvm::SIInstrInfovirtual
getIndirectIndexBegin(const MachineFunction &MF) const llvm::AMDGPUInstrInfo
getIndirectIndexEnd(const MachineFunction &MF) const llvm::AMDGPUInstrInfo
getMachineCSELookAheadLimit() const overridellvm::SIInstrInfoinline
getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const llvm::AMDGPUInstrInfo
getMCOpcodeFromPseudo(unsigned Opcode) const llvm::AMDGPUInstrInfoinline
getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg, unsigned &Offset, const TargetRegisterInfo *TRI) const finalllvm::SIInstrInfo
getMovOpcode(const TargetRegisterClass *DstRC) const llvm::SIInstrInfo
getNamedOperand(MachineInstr &MI, unsigned OperandName) const llvm::SIInstrInfo
getNamedOperand(const MachineInstr &MI, unsigned OpName) const llvm::SIInstrInfoinline
getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const overridellvm::AMDGPUInstrInfo
getOpRegClass(const MachineInstr &MI, unsigned OpNo) const llvm::SIInstrInfo
getOpSize(uint16_t Opcode, unsigned OpNo) const llvm::SIInstrInfoinline
getOpSize(const MachineInstr &MI, unsigned OpNo) const llvm::SIInstrInfoinline
getRegisterInfo() const overridellvm::SIInstrInfoinlinevirtual
getVALUOp(const MachineInstr &MI)llvm::SIInstrInfostatic
hasLoadFromStackSlot(const MachineInstr *MI, const MachineMemOperand *&MMO, int &FrameIndex) const overridellvm::AMDGPUInstrInfo
hasModifiers(unsigned Opcode) const llvm::SIInstrInfo
hasModifiersSet(const MachineInstr &MI, unsigned OpName) const llvm::SIInstrInfo
hasStoreFromStackSlot(const MachineInstr *MI, const MachineMemOperand *&MMO, int &FrameIndex) const llvm::AMDGPUInstrInfo
hasVALU32BitEncoding(unsigned Opcode) const llvm::SIInstrInfo
insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const overridellvm::AMDGPUInstrInfo
insertNOPs(MachineBasicBlock::iterator MI, int Count) const llvm::SIInstrInfo
isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const overridellvm::AMDGPUInstrInfo
isDS(uint16_t Opcode) const llvm::SIInstrInfoinline
isFLAT(uint16_t Opcode) const llvm::SIInstrInfoinline
isImmOperandLegal(const MachineInstr *MI, unsigned OpNo, const MachineOperand &MO) const llvm::SIInstrInfo
isInlineConstant(const APInt &Imm) const llvm::SIInstrInfo
isInlineConstant(const MachineOperand &MO, unsigned OpSize) const llvm::SIInstrInfo
isLiteralConstant(const MachineOperand &MO, unsigned OpSize) const llvm::SIInstrInfo
isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const overridellvm::AMDGPUInstrInfo
isLoadFromStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const overridellvm::AMDGPUInstrInfo
isMIMG(uint16_t Opcode) const llvm::SIInstrInfoinline
isMov(unsigned Opcode) const overridellvm::SIInstrInfovirtual
isMTBUF(uint16_t Opcode) const llvm::SIInstrInfoinline
isMUBUF(uint16_t Opcode) const llvm::SIInstrInfoinline
isOperandLegal(const MachineInstr *MI, unsigned OpIdx, const MachineOperand *MO=nullptr) const llvm::SIInstrInfo
isPredicable(MachineInstr *MI) const overridellvm::AMDGPUInstrInfo
isPredicated(const MachineInstr *MI) const overridellvm::AMDGPUInstrInfo
isReallyTriviallyReMaterializable(const MachineInstr *MI, AliasAnalysis *AA) const overridellvm::SIInstrInfo
isRegisterLoad(const MachineInstr &MI) const llvm::AMDGPUInstrInfo
isRegisterStore(const MachineInstr &MI) const llvm::AMDGPUInstrInfo
isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const overridellvm::SIInstrInfo
isSALU(uint16_t Opcode) const llvm::SIInstrInfoinline
isSALUOpSupportedOnVALU(const MachineInstr &MI) const llvm::SIInstrInfo
isSMRD(uint16_t Opcode) const llvm::SIInstrInfoinline
isSOP1(uint16_t Opcode) const llvm::SIInstrInfoinline
isSOP2(uint16_t Opcode) const llvm::SIInstrInfoinline
isSOPC(uint16_t Opcode) const llvm::SIInstrInfoinline
isSOPK(uint16_t Opcode) const llvm::SIInstrInfoinline
isSOPP(uint16_t Opcode) const llvm::SIInstrInfoinline
isStoreFromStackSlot(const MachineInstr *MI, int &FrameIndex) const llvm::AMDGPUInstrInfo
isStoreFromStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const llvm::AMDGPUInstrInfo
isTriviallyReMaterializable(const MachineInstr *MI, AliasAnalysis *AA=nullptr) const llvm::SIInstrInfo
isVALU(uint16_t Opcode) const llvm::SIInstrInfoinline
isVGPRSpill(uint16_t Opcode) const llvm::SIInstrInfoinline
isVOP1(uint16_t Opcode) const llvm::SIInstrInfoinline
isVOP2(uint16_t Opcode) const llvm::SIInstrInfoinline
isVOP3(uint16_t Opcode) const llvm::SIInstrInfoinline
isVOPC(uint16_t Opcode) const llvm::SIInstrInfoinline
isWQM(uint16_t Opcode) const llvm::SIInstrInfoinline
legalizeOperands(MachineInstr *MI) const llvm::SIInstrInfo
legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const llvm::SIInstrInfo
LoadM0(MachineInstr *MoveRel, MachineBasicBlock::iterator I, unsigned SavReg, unsigned IndexReg) const llvm::SIInstrInfo
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const overridellvm::SIInstrInfo
moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const llvm::SIInstrInfo
moveToVALU(MachineInstr &MI) const llvm::SIInstrInfo
pseudoToMCOpcode(int Opcode) const llvm::AMDGPUInstrInfo
reserveIndirectRegisters(BitVector &Reserved, const MachineFunction &MF) const llvm::SIInstrInfo
ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const overridellvm::AMDGPUInstrInfo
shouldClusterLoads(MachineInstr *FirstLdSt, MachineInstr *SecondLdSt, unsigned NumLoads) const finalllvm::SIInstrInfo
shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const overridellvm::AMDGPUInstrInfo
SIInstrInfo(const AMDGPUSubtarget &st)llvm::SIInstrInfoexplicit
splitSMRD(MachineInstr *MI, const TargetRegisterClass *HalfRC, unsigned HalfImmOp, unsigned HalfSGPROp, MachineInstr *&Lo, MachineInstr *&Hi) const llvm::SIInstrInfo
STllvm::AMDGPUInstrInfoprotected
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const overridellvm::SIInstrInfo
SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const overridellvm::AMDGPUInstrInfo
unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const overridellvm::AMDGPUInstrInfo
unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, SmallVectorImpl< SDNode * > &NewNodes) const overridellvm::AMDGPUInstrInfo
usesConstantBus(const MachineRegisterInfo &MRI, const MachineOperand &MO, unsigned OpSize) const llvm::SIInstrInfo
verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const overridellvm::SIInstrInfo