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LLVM
3.7.0
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#include <HexagonMachineScheduler.h>
Public Member Functions | |
| VLIWResourceModel (const TargetSubtargetInfo &STI, const TargetSchedModel *SM) | |
| ~VLIWResourceModel () | |
| void | resetPacketState () |
| void | resetDFA () |
| void | reset () |
| bool | isResourceAvailable (SUnit *SU) |
| Check if scheduling of this SU is possible in the current packet. More... | |
| bool | reserveResources (SUnit *SU) |
| Keep track of available resources. More... | |
| unsigned | getTotalPackets () const |
Definition at line 41 of file HexagonMachineScheduler.h.
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Definition at line 57 of file HexagonMachineScheduler.h.
References llvm::DFAPacketizer::clearResources(), llvm::TargetInstrInfo::CreateTargetScheduleState(), llvm::TargetSubtargetInfo::getInstrInfo(), and llvm::TargetSchedModel::getIssueWidth().
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Definition at line 70 of file HexagonMachineScheduler.h.
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Definition at line 89 of file HexagonMachineScheduler.h.
Check if scheduling of this SU is possible in the current packet.
It is not precise (statefull), it is more like another heuristic. Many corner cases are figured empirically.
Definition at line 43 of file HexagonMachineScheduler.cpp.
References llvm::DFAPacketizer::canReserveResources(), llvm::TargetOpcode::COPY, llvm::TargetOpcode::EXTRACT_SUBREG, llvm::SUnit::getInstr(), llvm::MachineInstr::getOpcode(), I, llvm::TargetOpcode::IMPLICIT_DEF, llvm::TargetOpcode::INLINEASM, llvm::TargetOpcode::INSERT_SUBREG, llvm::TargetOpcode::REG_SEQUENCE, and llvm::TargetOpcode::SUBREG_TO_REG.
Referenced by reserveResources().
Keep track of available resources.
Definition at line 83 of file HexagonMachineScheduler.cpp.
References llvm::TargetOpcode::CFI_INSTRUCTION, llvm::DFAPacketizer::clearResources(), llvm::TargetOpcode::COPY, llvm::dbgs(), DEBUG, llvm::dump(), llvm::TargetOpcode::EH_LABEL, llvm::TargetOpcode::EXTRACT_SUBREG, llvm::SUnit::getInstr(), llvm::TargetSchedModel::getIssueWidth(), llvm::MachineInstr::getOpcode(), llvm::TargetOpcode::IMPLICIT_DEF, llvm::TargetOpcode::INLINEASM, llvm::TargetOpcode::INSERT_SUBREG, isResourceAvailable(), llvm::TargetOpcode::KILL, llvm::TargetOpcode::REG_SEQUENCE, llvm::DFAPacketizer::reserveResources(), and llvm::TargetOpcode::SUBREG_TO_REG.
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Definition at line 82 of file HexagonMachineScheduler.h.
References llvm::DFAPacketizer::clearResources().
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Definition at line 78 of file HexagonMachineScheduler.h.
References llvm::DFAPacketizer::clearResources().
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Definition at line 74 of file HexagonMachineScheduler.h.
1.8.6