16 #ifndef LLVM_LIB_CODEGEN_CRITICALANTIDEPBREAKER_H
17 #define LLVM_LIB_CODEGEN_CRITICALANTIDEPBREAKER_H
30 class RegisterClassInfo;
31 class TargetInstrInfo;
32 class TargetRegisterInfo;
51 std::vector<const TargetRegisterClass*> Classes;
54 std::multimap<unsigned, MachineOperand *> RegRefs;
55 typedef std::multimap<unsigned, MachineOperand *>::const_iterator
60 std::vector<unsigned> KillIndices;
64 std::vector<unsigned> DefIndices;
79 unsigned BreakAntiDependencies(
const std::vector<SUnit>& SUnits,
82 unsigned InsertPosIndex,
88 unsigned InsertPosIndex)
override;
91 void FinishBlock()
override;
96 bool isNewRegClobberedByRefs(RegRefIter RegRefBegin,
99 unsigned findSuitableFreeRegister(RegRefIter RegRefBegin,
100 RegRefIter RegRefEnd,
const HexagonInstrInfo * TII
This class works in conjunction with the post-RA scheduler to rename registers to break register anti...
TargetInstrInfo - Interface to description of machine instruction set.
bundle_iterator< MachineInstr, instr_iterator > iterator
#define LLVM_LIBRARY_VISIBILITY
LLVM_LIBRARY_VISIBILITY - If a class marked with this attribute is linked into a shared library...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
std::vector< std::pair< MachineInstr *, MachineInstr * > > DbgValueVector