LLVM  3.7.0
TwoAddressInstructionPass.cpp
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1 //===-- TwoAddressInstructionPass.cpp - Two-Address instruction pass ------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the TwoAddress instruction pass which is used
11 // by most register allocators. Two-Address instructions are rewritten
12 // from:
13 //
14 // A = B op C
15 //
16 // to:
17 //
18 // A = B
19 // A op= C
20 //
21 // Note that if a register allocator chooses to use this pass, that it
22 // has to be capable of handling the non-SSA nature of these rewritten
23 // virtual registers.
24 //
25 // It is also worth noting that the duplicate operand of the two
26 // address instruction is removed.
27 //
28 //===----------------------------------------------------------------------===//
29 
30 #include "llvm/CodeGen/Passes.h"
31 #include "llvm/ADT/BitVector.h"
32 #include "llvm/ADT/DenseMap.h"
33 #include "llvm/ADT/STLExtras.h"
34 #include "llvm/ADT/SmallSet.h"
35 #include "llvm/ADT/Statistic.h"
43 #include "llvm/IR/Function.h"
46 #include "llvm/Support/Debug.h"
53 using namespace llvm;
54 
55 #define DEBUG_TYPE "twoaddrinstr"
56 
57 STATISTIC(NumTwoAddressInstrs, "Number of two-address instructions");
58 STATISTIC(NumCommuted , "Number of instructions commuted to coalesce");
59 STATISTIC(NumAggrCommuted , "Number of instructions aggressively commuted");
60 STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address");
61 STATISTIC(Num3AddrSunk, "Number of 3-address instructions sunk");
62 STATISTIC(NumReSchedUps, "Number of instructions re-scheduled up");
63 STATISTIC(NumReSchedDowns, "Number of instructions re-scheduled down");
64 
65 // Temporary flag to disable rescheduling.
66 static cl::opt<bool>
67 EnableRescheduling("twoaddr-reschedule",
68  cl::desc("Coalesce copies by rescheduling (default=true)"),
69  cl::init(true), cl::Hidden);
70 
71 namespace {
72 class TwoAddressInstructionPass : public MachineFunctionPass {
73  MachineFunction *MF;
74  const TargetInstrInfo *TII;
75  const TargetRegisterInfo *TRI;
76  const InstrItineraryData *InstrItins;
78  LiveVariables *LV;
79  LiveIntervals *LIS;
80  AliasAnalysis *AA;
81  CodeGenOpt::Level OptLevel;
82 
83  // The current basic block being processed.
84  MachineBasicBlock *MBB;
85 
86  // DistanceMap - Keep track the distance of a MI from the start of the
87  // current basic block.
89 
90  // Set of already processed instructions in the current block.
92 
93  // SrcRegMap - A map from virtual registers to physical registers which are
94  // likely targets to be coalesced to due to copies from physical registers to
95  // virtual registers. e.g. v1024 = move r0.
97 
98  // DstRegMap - A map from virtual registers to physical registers which are
99  // likely targets to be coalesced to due to copies to physical registers from
100  // virtual registers. e.g. r1 = move v1024.
102 
103  bool sink3AddrInstruction(MachineInstr *MI, unsigned Reg,
105 
106  bool isRevCopyChain(unsigned FromReg, unsigned ToReg, int Maxlen);
107 
108  bool noUseAfterLastDef(unsigned Reg, unsigned Dist, unsigned &LastDef);
109 
110  bool isProfitableToCommute(unsigned regA, unsigned regB, unsigned regC,
111  MachineInstr *MI, unsigned Dist);
112 
113  bool commuteInstruction(MachineBasicBlock::iterator &mi,
114  unsigned RegB, unsigned RegC, unsigned Dist);
115 
116  bool isProfitableToConv3Addr(unsigned RegA, unsigned RegB);
117 
118  bool convertInstTo3Addr(MachineBasicBlock::iterator &mi,
120  unsigned RegA, unsigned RegB, unsigned Dist);
121 
122  bool isDefTooClose(unsigned Reg, unsigned Dist, MachineInstr *MI);
123 
124  bool rescheduleMIBelowKill(MachineBasicBlock::iterator &mi,
126  unsigned Reg);
127  bool rescheduleKillAboveMI(MachineBasicBlock::iterator &mi,
129  unsigned Reg);
130 
131  bool tryInstructionTransform(MachineBasicBlock::iterator &mi,
133  unsigned SrcIdx, unsigned DstIdx,
134  unsigned Dist, bool shouldOnlyCommute);
135 
136  void scanUses(unsigned DstReg);
137 
138  void processCopy(MachineInstr *MI);
139 
140  typedef SmallVector<std::pair<unsigned, unsigned>, 4> TiedPairList;
141  typedef SmallDenseMap<unsigned, TiedPairList> TiedOperandMap;
142  bool collectTiedOperands(MachineInstr *MI, TiedOperandMap&);
143  void processTiedPairs(MachineInstr *MI, TiedPairList&, unsigned &Dist);
144  void eliminateRegSequence(MachineBasicBlock::iterator&);
145 
146 public:
147  static char ID; // Pass identification, replacement for typeid
148  TwoAddressInstructionPass() : MachineFunctionPass(ID) {
150  }
151 
152  void getAnalysisUsage(AnalysisUsage &AU) const override {
153  AU.setPreservesCFG();
161  }
162 
163  /// runOnMachineFunction - Pass entry point.
164  bool runOnMachineFunction(MachineFunction&) override;
165 };
166 } // end anonymous namespace
167 
169 INITIALIZE_PASS_BEGIN(TwoAddressInstructionPass, "twoaddressinstruction",
170  "Two-Address instruction pass", false, false)
172 INITIALIZE_PASS_END(TwoAddressInstructionPass, "twoaddressinstruction",
173  "Two-Address instruction pass", false, false)
174 
175 char &llvm::TwoAddressInstructionPassID = TwoAddressInstructionPass::ID;
176 
177 static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg, LiveIntervals *LIS);
178 
179 /// sink3AddrInstruction - A two-address instruction has been converted to a
180 /// three-address instruction to avoid clobbering a register. Try to sink it
181 /// past the instruction that would kill the above mentioned register to reduce
182 /// register pressure.
183 bool TwoAddressInstructionPass::
184 sink3AddrInstruction(MachineInstr *MI, unsigned SavedReg,
185  MachineBasicBlock::iterator OldPos) {
186  // FIXME: Shouldn't we be trying to do this before we three-addressify the
187  // instruction? After this transformation is done, we no longer need
188  // the instruction to be in three-address form.
189 
190  // Check if it's safe to move this instruction.
191  bool SeenStore = true; // Be conservative.
192  if (!MI->isSafeToMove(AA, SeenStore))
193  return false;
194 
195  unsigned DefReg = 0;
196  SmallSet<unsigned, 4> UseRegs;
197 
198  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
199  const MachineOperand &MO = MI->getOperand(i);
200  if (!MO.isReg())
201  continue;
202  unsigned MOReg = MO.getReg();
203  if (!MOReg)
204  continue;
205  if (MO.isUse() && MOReg != SavedReg)
206  UseRegs.insert(MO.getReg());
207  if (!MO.isDef())
208  continue;
209  if (MO.isImplicit())
210  // Don't try to move it if it implicitly defines a register.
211  return false;
212  if (DefReg)
213  // For now, don't move any instructions that define multiple registers.
214  return false;
215  DefReg = MO.getReg();
216  }
217 
218  // Find the instruction that kills SavedReg.
219  MachineInstr *KillMI = nullptr;
220  if (LIS) {
221  LiveInterval &LI = LIS->getInterval(SavedReg);
222  assert(LI.end() != LI.begin() &&
223  "Reg should not have empty live interval.");
224 
225  SlotIndex MBBEndIdx = LIS->getMBBEndIdx(MBB).getPrevSlot();
226  LiveInterval::const_iterator I = LI.find(MBBEndIdx);
227  if (I != LI.end() && I->start < MBBEndIdx)
228  return false;
229 
230  --I;
231  KillMI = LIS->getInstructionFromIndex(I->end);
232  }
233  if (!KillMI) {
235  UI = MRI->use_nodbg_begin(SavedReg),
236  UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
237  MachineOperand &UseMO = *UI;
238  if (!UseMO.isKill())
239  continue;
240  KillMI = UseMO.getParent();
241  break;
242  }
243  }
244 
245  // If we find the instruction that kills SavedReg, and it is in an
246  // appropriate location, we can try to sink the current instruction
247  // past it.
248  if (!KillMI || KillMI->getParent() != MBB || KillMI == MI ||
249  KillMI == OldPos || KillMI->isTerminator())
250  return false;
251 
252  // If any of the definitions are used by another instruction between the
253  // position and the kill use, then it's not safe to sink it.
254  //
255  // FIXME: This can be sped up if there is an easy way to query whether an
256  // instruction is before or after another instruction. Then we can use
257  // MachineRegisterInfo def / use instead.
258  MachineOperand *KillMO = nullptr;
259  MachineBasicBlock::iterator KillPos = KillMI;
260  ++KillPos;
261 
262  unsigned NumVisited = 0;
263  for (MachineBasicBlock::iterator I = std::next(OldPos); I != KillPos; ++I) {
264  MachineInstr *OtherMI = I;
265  // DBG_VALUE cannot be counted against the limit.
266  if (OtherMI->isDebugValue())
267  continue;
268  if (NumVisited > 30) // FIXME: Arbitrary limit to reduce compile time cost.
269  return false;
270  ++NumVisited;
271  for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
272  MachineOperand &MO = OtherMI->getOperand(i);
273  if (!MO.isReg())
274  continue;
275  unsigned MOReg = MO.getReg();
276  if (!MOReg)
277  continue;
278  if (DefReg == MOReg)
279  return false;
280 
281  if (MO.isKill() || (LIS && isPlainlyKilled(OtherMI, MOReg, LIS))) {
282  if (OtherMI == KillMI && MOReg == SavedReg)
283  // Save the operand that kills the register. We want to unset the kill
284  // marker if we can sink MI past it.
285  KillMO = &MO;
286  else if (UseRegs.count(MOReg))
287  // One of the uses is killed before the destination.
288  return false;
289  }
290  }
291  }
292  assert(KillMO && "Didn't find kill");
293 
294  if (!LIS) {
295  // Update kill and LV information.
296  KillMO->setIsKill(false);
297  KillMO = MI->findRegisterUseOperand(SavedReg, false, TRI);
298  KillMO->setIsKill(true);
299 
300  if (LV)
301  LV->replaceKillInstruction(SavedReg, KillMI, MI);
302  }
303 
304  // Move instruction to its destination.
305  MBB->remove(MI);
306  MBB->insert(KillPos, MI);
307 
308  if (LIS)
309  LIS->handleMove(MI);
310 
311  ++Num3AddrSunk;
312  return true;
313 }
314 
315 /// getSingleDef -- return the MachineInstr* if it is the single def of the Reg
316 /// in current BB.
318  const MachineRegisterInfo *MRI) {
319  MachineInstr *Ret = nullptr;
320  for (MachineInstr &DefMI : MRI->def_instructions(Reg)) {
321  if (DefMI.getParent() != BB || DefMI.isDebugValue())
322  continue;
323  if (!Ret)
324  Ret = &DefMI;
325  else if (Ret != &DefMI)
326  return nullptr;
327  }
328  return Ret;
329 }
330 
331 /// Check if there is a reversed copy chain from FromReg to ToReg:
332 /// %Tmp1 = copy %Tmp2;
333 /// %FromReg = copy %Tmp1;
334 /// %ToReg = add %FromReg ...
335 /// %Tmp2 = copy %ToReg;
336 /// MaxLen specifies the maximum length of the copy chain the func
337 /// can walk through.
338 bool TwoAddressInstructionPass::isRevCopyChain(unsigned FromReg, unsigned ToReg,
339  int Maxlen) {
340  unsigned TmpReg = FromReg;
341  for (int i = 0; i < Maxlen; i++) {
342  MachineInstr *Def = getSingleDef(TmpReg, MBB, MRI);
343  if (!Def || !Def->isCopy())
344  return false;
345 
346  TmpReg = Def->getOperand(1).getReg();
347 
348  if (TmpReg == ToReg)
349  return true;
350  }
351  return false;
352 }
353 
354 /// noUseAfterLastDef - Return true if there are no intervening uses between the
355 /// last instruction in the MBB that defines the specified register and the
356 /// two-address instruction which is being processed. It also returns the last
357 /// def location by reference
358 bool TwoAddressInstructionPass::noUseAfterLastDef(unsigned Reg, unsigned Dist,
359  unsigned &LastDef) {
360  LastDef = 0;
361  unsigned LastUse = Dist;
362  for (MachineOperand &MO : MRI->reg_operands(Reg)) {
363  MachineInstr *MI = MO.getParent();
364  if (MI->getParent() != MBB || MI->isDebugValue())
365  continue;
366  DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
367  if (DI == DistanceMap.end())
368  continue;
369  if (MO.isUse() && DI->second < LastUse)
370  LastUse = DI->second;
371  if (MO.isDef() && DI->second > LastDef)
372  LastDef = DI->second;
373  }
374 
375  return !(LastUse > LastDef && LastUse < Dist);
376 }
377 
378 /// isCopyToReg - Return true if the specified MI is a copy instruction or
379 /// a extract_subreg instruction. It also returns the source and destination
380 /// registers and whether they are physical registers by reference.
381 static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII,
382  unsigned &SrcReg, unsigned &DstReg,
383  bool &IsSrcPhys, bool &IsDstPhys) {
384  SrcReg = 0;
385  DstReg = 0;
386  if (MI.isCopy()) {
387  DstReg = MI.getOperand(0).getReg();
388  SrcReg = MI.getOperand(1).getReg();
389  } else if (MI.isInsertSubreg() || MI.isSubregToReg()) {
390  DstReg = MI.getOperand(0).getReg();
391  SrcReg = MI.getOperand(2).getReg();
392  } else
393  return false;
394 
395  IsSrcPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
396  IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
397  return true;
398 }
399 
400 /// isPLainlyKilled - Test if the given register value, which is used by the
401 // given instruction, is killed by the given instruction.
402 static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg,
403  LiveIntervals *LIS) {
404  if (LIS && TargetRegisterInfo::isVirtualRegister(Reg) &&
405  !LIS->isNotInMIMap(MI)) {
406  // FIXME: Sometimes tryInstructionTransform() will add instructions and
407  // test whether they can be folded before keeping them. In this case it
408  // sets a kill before recursively calling tryInstructionTransform() again.
409  // If there is no interval available, we assume that this instruction is
410  // one of those. A kill flag is manually inserted on the operand so the
411  // check below will handle it.
412  LiveInterval &LI = LIS->getInterval(Reg);
413  // This is to match the kill flag version where undefs don't have kill
414  // flags.
415  if (!LI.hasAtLeastOneValue())
416  return false;
417 
418  SlotIndex useIdx = LIS->getInstructionIndex(MI);
419  LiveInterval::const_iterator I = LI.find(useIdx);
420  assert(I != LI.end() && "Reg must be live-in to use.");
421  return !I->end.isBlock() && SlotIndex::isSameInstr(I->end, useIdx);
422  }
423 
424  return MI->killsRegister(Reg);
425 }
426 
427 /// isKilled - Test if the given register value, which is used by the given
428 /// instruction, is killed by the given instruction. This looks through
429 /// coalescable copies to see if the original value is potentially not killed.
430 ///
431 /// For example, in this code:
432 ///
433 /// %reg1034 = copy %reg1024
434 /// %reg1035 = copy %reg1025<kill>
435 /// %reg1036 = add %reg1034<kill>, %reg1035<kill>
436 ///
437 /// %reg1034 is not considered to be killed, since it is copied from a
438 /// register which is not killed. Treating it as not killed lets the
439 /// normal heuristics commute the (two-address) add, which lets
440 /// coalescing eliminate the extra copy.
441 ///
442 /// If allowFalsePositives is true then likely kills are treated as kills even
443 /// if it can't be proven that they are kills.
444 static bool isKilled(MachineInstr &MI, unsigned Reg,
445  const MachineRegisterInfo *MRI,
446  const TargetInstrInfo *TII,
447  LiveIntervals *LIS,
448  bool allowFalsePositives) {
449  MachineInstr *DefMI = &MI;
450  for (;;) {
451  // All uses of physical registers are likely to be kills.
453  (allowFalsePositives || MRI->hasOneUse(Reg)))
454  return true;
455  if (!isPlainlyKilled(DefMI, Reg, LIS))
456  return false;
458  return true;
460  // If there are multiple defs, we can't do a simple analysis, so just
461  // go with what the kill flag says.
462  if (std::next(Begin) != MRI->def_end())
463  return true;
464  DefMI = Begin->getParent();
465  bool IsSrcPhys, IsDstPhys;
466  unsigned SrcReg, DstReg;
467  // If the def is something other than a copy, then it isn't going to
468  // be coalesced, so follow the kill flag.
469  if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
470  return true;
471  Reg = SrcReg;
472  }
473 }
474 
475 /// isTwoAddrUse - Return true if the specified MI uses the specified register
476 /// as a two-address use. If so, return the destination register by reference.
477 static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) {
478  for (unsigned i = 0, NumOps = MI.getNumOperands(); i != NumOps; ++i) {
479  const MachineOperand &MO = MI.getOperand(i);
480  if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
481  continue;
482  unsigned ti;
483  if (MI.isRegTiedToDefOperand(i, &ti)) {
484  DstReg = MI.getOperand(ti).getReg();
485  return true;
486  }
487  }
488  return false;
489 }
490 
491 /// findOnlyInterestingUse - Given a register, if has a single in-basic block
492 /// use, return the use instruction if it's a copy or a two-address use.
493 static
495  MachineRegisterInfo *MRI,
496  const TargetInstrInfo *TII,
497  bool &IsCopy,
498  unsigned &DstReg, bool &IsDstPhys) {
499  if (!MRI->hasOneNonDBGUse(Reg))
500  // None or more than one use.
501  return nullptr;
502  MachineInstr &UseMI = *MRI->use_instr_nodbg_begin(Reg);
503  if (UseMI.getParent() != MBB)
504  return nullptr;
505  unsigned SrcReg;
506  bool IsSrcPhys;
507  if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) {
508  IsCopy = true;
509  return &UseMI;
510  }
511  IsDstPhys = false;
512  if (isTwoAddrUse(UseMI, Reg, DstReg)) {
513  IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
514  return &UseMI;
515  }
516  return nullptr;
517 }
518 
519 /// getMappedReg - Return the physical register the specified virtual register
520 /// might be mapped to.
521 static unsigned
525  if (SI == RegMap.end())
526  return 0;
527  Reg = SI->second;
528  }
530  return Reg;
531  return 0;
532 }
533 
534 /// regsAreCompatible - Return true if the two registers are equal or aliased.
535 ///
536 static bool
537 regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) {
538  if (RegA == RegB)
539  return true;
540  if (!RegA || !RegB)
541  return false;
542  return TRI->regsOverlap(RegA, RegB);
543 }
544 
545 
546 /// isProfitableToCommute - Return true if it's potentially profitable to commute
547 /// the two-address instruction that's being processed.
548 bool
549 TwoAddressInstructionPass::
550 isProfitableToCommute(unsigned regA, unsigned regB, unsigned regC,
551  MachineInstr *MI, unsigned Dist) {
552  if (OptLevel == CodeGenOpt::None)
553  return false;
554 
555  // Determine if it's profitable to commute this two address instruction. In
556  // general, we want no uses between this instruction and the definition of
557  // the two-address register.
558  // e.g.
559  // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
560  // %reg1029<def> = MOV8rr %reg1028
561  // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
562  // insert => %reg1030<def> = MOV8rr %reg1028
563  // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
564  // In this case, it might not be possible to coalesce the second MOV8rr
565  // instruction if the first one is coalesced. So it would be profitable to
566  // commute it:
567  // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
568  // %reg1029<def> = MOV8rr %reg1028
569  // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
570  // insert => %reg1030<def> = MOV8rr %reg1029
571  // %reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>
572 
573  if (!isPlainlyKilled(MI, regC, LIS))
574  return false;
575 
576  // Ok, we have something like:
577  // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
578  // let's see if it's worth commuting it.
579 
580  // Look for situations like this:
581  // %reg1024<def> = MOV r1
582  // %reg1025<def> = MOV r0
583  // %reg1026<def> = ADD %reg1024, %reg1025
584  // r0 = MOV %reg1026
585  // Commute the ADD to hopefully eliminate an otherwise unavoidable copy.
586  unsigned ToRegA = getMappedReg(regA, DstRegMap);
587  if (ToRegA) {
588  unsigned FromRegB = getMappedReg(regB, SrcRegMap);
589  unsigned FromRegC = getMappedReg(regC, SrcRegMap);
590  bool CompB = FromRegB && regsAreCompatible(FromRegB, ToRegA, TRI);
591  bool CompC = FromRegC && regsAreCompatible(FromRegC, ToRegA, TRI);
592 
593  // Compute if any of the following are true:
594  // -RegB is not tied to a register and RegC is compatible with RegA.
595  // -RegB is tied to the wrong physical register, but RegC is.
596  // -RegB is tied to the wrong physical register, and RegC isn't tied.
597  if ((!FromRegB && CompC) || (FromRegB && !CompB && (!FromRegC || CompC)))
598  return true;
599  // Don't compute if any of the following are true:
600  // -RegC is not tied to a register and RegB is compatible with RegA.
601  // -RegC is tied to the wrong physical register, but RegB is.
602  // -RegC is tied to the wrong physical register, and RegB isn't tied.
603  if ((!FromRegC && CompB) || (FromRegC && !CompC && (!FromRegB || CompB)))
604  return false;
605  }
606 
607  // If there is a use of regC between its last def (could be livein) and this
608  // instruction, then bail.
609  unsigned LastDefC = 0;
610  if (!noUseAfterLastDef(regC, Dist, LastDefC))
611  return false;
612 
613  // If there is a use of regB between its last def (could be livein) and this
614  // instruction, then go ahead and make this transformation.
615  unsigned LastDefB = 0;
616  if (!noUseAfterLastDef(regB, Dist, LastDefB))
617  return true;
618 
619  // Look for situation like this:
620  // %reg101 = MOV %reg100
621  // %reg102 = ...
622  // %reg103 = ADD %reg102, %reg101
623  // ... = %reg103 ...
624  // %reg100 = MOV %reg103
625  // If there is a reversed copy chain from reg101 to reg103, commute the ADD
626  // to eliminate an otherwise unavoidable copy.
627  // FIXME:
628  // We can extend the logic further: If an pair of operands in an insn has
629  // been merged, the insn could be regarded as a virtual copy, and the virtual
630  // copy could also be used to construct a copy chain.
631  // To more generally minimize register copies, ideally the logic of two addr
632  // instruction pass should be integrated with register allocation pass where
633  // interference graph is available.
634  if (isRevCopyChain(regC, regA, 3))
635  return true;
636 
637  if (isRevCopyChain(regB, regA, 3))
638  return false;
639 
640  // Since there are no intervening uses for both registers, then commute
641  // if the def of regC is closer. Its live interval is shorter.
642  return LastDefB && LastDefC && LastDefC > LastDefB;
643 }
644 
645 /// commuteInstruction - Commute a two-address instruction and update the basic
646 /// block, distance map, and live variables if needed. Return true if it is
647 /// successful.
648 bool TwoAddressInstructionPass::
649 commuteInstruction(MachineBasicBlock::iterator &mi,
650  unsigned RegB, unsigned RegC, unsigned Dist) {
651  MachineInstr *MI = mi;
652  DEBUG(dbgs() << "2addr: COMMUTING : " << *MI);
653  MachineInstr *NewMI = TII->commuteInstruction(MI);
654 
655  if (NewMI == nullptr) {
656  DEBUG(dbgs() << "2addr: COMMUTING FAILED!\n");
657  return false;
658  }
659 
660  DEBUG(dbgs() << "2addr: COMMUTED TO: " << *NewMI);
661  assert(NewMI == MI &&
662  "TargetInstrInfo::commuteInstruction() should not return a new "
663  "instruction unless it was requested.");
664 
665  // Update source register map.
666  unsigned FromRegC = getMappedReg(RegC, SrcRegMap);
667  if (FromRegC) {
668  unsigned RegA = MI->getOperand(0).getReg();
669  SrcRegMap[RegA] = FromRegC;
670  }
671 
672  return true;
673 }
674 
675 /// isProfitableToConv3Addr - Return true if it is profitable to convert the
676 /// given 2-address instruction to a 3-address one.
677 bool
678 TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA,unsigned RegB){
679  // Look for situations like this:
680  // %reg1024<def> = MOV r1
681  // %reg1025<def> = MOV r0
682  // %reg1026<def> = ADD %reg1024, %reg1025
683  // r2 = MOV %reg1026
684  // Turn ADD into a 3-address instruction to avoid a copy.
685  unsigned FromRegB = getMappedReg(RegB, SrcRegMap);
686  if (!FromRegB)
687  return false;
688  unsigned ToRegA = getMappedReg(RegA, DstRegMap);
689  return (ToRegA && !regsAreCompatible(FromRegB, ToRegA, TRI));
690 }
691 
692 /// convertInstTo3Addr - Convert the specified two-address instruction into a
693 /// three address one. Return true if this transformation was successful.
694 bool
695 TwoAddressInstructionPass::convertInstTo3Addr(MachineBasicBlock::iterator &mi,
697  unsigned RegA, unsigned RegB,
698  unsigned Dist) {
699  // FIXME: Why does convertToThreeAddress() need an iterator reference?
700  MachineFunction::iterator MFI = MBB;
701  MachineInstr *NewMI = TII->convertToThreeAddress(MFI, mi, LV);
702  assert(MBB == MFI && "convertToThreeAddress changed iterator reference");
703  if (!NewMI)
704  return false;
705 
706  DEBUG(dbgs() << "2addr: CONVERTING 2-ADDR: " << *mi);
707  DEBUG(dbgs() << "2addr: TO 3-ADDR: " << *NewMI);
708  bool Sunk = false;
709 
710  if (LIS)
711  LIS->ReplaceMachineInstrInMaps(mi, NewMI);
712 
713  if (NewMI->findRegisterUseOperand(RegB, false, TRI))
714  // FIXME: Temporary workaround. If the new instruction doesn't
715  // uses RegB, convertToThreeAddress must have created more
716  // then one instruction.
717  Sunk = sink3AddrInstruction(NewMI, RegB, mi);
718 
719  MBB->erase(mi); // Nuke the old inst.
720 
721  if (!Sunk) {
722  DistanceMap.insert(std::make_pair(NewMI, Dist));
723  mi = NewMI;
724  nmi = std::next(mi);
725  }
726 
727  // Update source and destination register maps.
728  SrcRegMap.erase(RegA);
729  DstRegMap.erase(RegB);
730  return true;
731 }
732 
733 /// scanUses - Scan forward recursively for only uses, update maps if the use
734 /// is a copy or a two-address instruction.
735 void
736 TwoAddressInstructionPass::scanUses(unsigned DstReg) {
737  SmallVector<unsigned, 4> VirtRegPairs;
738  bool IsDstPhys;
739  bool IsCopy = false;
740  unsigned NewReg = 0;
741  unsigned Reg = DstReg;
742  while (MachineInstr *UseMI = findOnlyInterestingUse(Reg, MBB, MRI, TII,IsCopy,
743  NewReg, IsDstPhys)) {
744  if (IsCopy && !Processed.insert(UseMI).second)
745  break;
746 
747  DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
748  if (DI != DistanceMap.end())
749  // Earlier in the same MBB.Reached via a back edge.
750  break;
751 
752  if (IsDstPhys) {
753  VirtRegPairs.push_back(NewReg);
754  break;
755  }
756  bool isNew = SrcRegMap.insert(std::make_pair(NewReg, Reg)).second;
757  if (!isNew)
758  assert(SrcRegMap[NewReg] == Reg && "Can't map to two src registers!");
759  VirtRegPairs.push_back(NewReg);
760  Reg = NewReg;
761  }
762 
763  if (!VirtRegPairs.empty()) {
764  unsigned ToReg = VirtRegPairs.back();
765  VirtRegPairs.pop_back();
766  while (!VirtRegPairs.empty()) {
767  unsigned FromReg = VirtRegPairs.back();
768  VirtRegPairs.pop_back();
769  bool isNew = DstRegMap.insert(std::make_pair(FromReg, ToReg)).second;
770  if (!isNew)
771  assert(DstRegMap[FromReg] == ToReg &&"Can't map to two dst registers!");
772  ToReg = FromReg;
773  }
774  bool isNew = DstRegMap.insert(std::make_pair(DstReg, ToReg)).second;
775  if (!isNew)
776  assert(DstRegMap[DstReg] == ToReg && "Can't map to two dst registers!");
777  }
778 }
779 
780 /// processCopy - If the specified instruction is not yet processed, process it
781 /// if it's a copy. For a copy instruction, we find the physical registers the
782 /// source and destination registers might be mapped to. These are kept in
783 /// point-to maps used to determine future optimizations. e.g.
784 /// v1024 = mov r0
785 /// v1025 = mov r1
786 /// v1026 = add v1024, v1025
787 /// r1 = mov r1026
788 /// If 'add' is a two-address instruction, v1024, v1026 are both potentially
789 /// coalesced to r0 (from the input side). v1025 is mapped to r1. v1026 is
790 /// potentially joined with r1 on the output side. It's worthwhile to commute
791 /// 'add' to eliminate a copy.
792 void TwoAddressInstructionPass::processCopy(MachineInstr *MI) {
793  if (Processed.count(MI))
794  return;
795 
796  bool IsSrcPhys, IsDstPhys;
797  unsigned SrcReg, DstReg;
798  if (!isCopyToReg(*MI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
799  return;
800 
801  if (IsDstPhys && !IsSrcPhys)
802  DstRegMap.insert(std::make_pair(SrcReg, DstReg));
803  else if (!IsDstPhys && IsSrcPhys) {
804  bool isNew = SrcRegMap.insert(std::make_pair(DstReg, SrcReg)).second;
805  if (!isNew)
806  assert(SrcRegMap[DstReg] == SrcReg &&
807  "Can't map to two src physical registers!");
808 
809  scanUses(DstReg);
810  }
811 
812  Processed.insert(MI);
813  return;
814 }
815 
816 /// rescheduleMIBelowKill - If there is one more local instruction that reads
817 /// 'Reg' and it kills 'Reg, consider moving the instruction below the kill
818 /// instruction in order to eliminate the need for the copy.
819 bool TwoAddressInstructionPass::
820 rescheduleMIBelowKill(MachineBasicBlock::iterator &mi,
822  unsigned Reg) {
823  // Bail immediately if we don't have LV or LIS available. We use them to find
824  // kills efficiently.
825  if (!LV && !LIS)
826  return false;
827 
828  MachineInstr *MI = &*mi;
830  if (DI == DistanceMap.end())
831  // Must be created from unfolded load. Don't waste time trying this.
832  return false;
833 
834  MachineInstr *KillMI = nullptr;
835  if (LIS) {
836  LiveInterval &LI = LIS->getInterval(Reg);
837  assert(LI.end() != LI.begin() &&
838  "Reg should not have empty live interval.");
839 
840  SlotIndex MBBEndIdx = LIS->getMBBEndIdx(MBB).getPrevSlot();
841  LiveInterval::const_iterator I = LI.find(MBBEndIdx);
842  if (I != LI.end() && I->start < MBBEndIdx)
843  return false;
844 
845  --I;
846  KillMI = LIS->getInstructionFromIndex(I->end);
847  } else {
848  KillMI = LV->getVarInfo(Reg).findKill(MBB);
849  }
850  if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike())
851  // Don't mess with copies, they may be coalesced later.
852  return false;
853 
854  if (KillMI->hasUnmodeledSideEffects() || KillMI->isCall() ||
855  KillMI->isBranch() || KillMI->isTerminator())
856  // Don't move pass calls, etc.
857  return false;
858 
859  unsigned DstReg;
860  if (isTwoAddrUse(*KillMI, Reg, DstReg))
861  return false;
862 
863  bool SeenStore = true;
864  if (!MI->isSafeToMove(AA, SeenStore))
865  return false;
866 
867  if (TII->getInstrLatency(InstrItins, MI) > 1)
868  // FIXME: Needs more sophisticated heuristics.
869  return false;
870 
872  SmallSet<unsigned, 2> Kills;
874  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
875  const MachineOperand &MO = MI->getOperand(i);
876  if (!MO.isReg())
877  continue;
878  unsigned MOReg = MO.getReg();
879  if (!MOReg)
880  continue;
881  if (MO.isDef())
882  Defs.insert(MOReg);
883  else {
884  Uses.insert(MOReg);
885  if (MOReg != Reg && (MO.isKill() ||
886  (LIS && isPlainlyKilled(MI, MOReg, LIS))))
887  Kills.insert(MOReg);
888  }
889  }
890 
891  // Move the copies connected to MI down as well.
893  MachineBasicBlock::iterator AfterMI = std::next(Begin);
894 
895  MachineBasicBlock::iterator End = AfterMI;
896  while (End->isCopy() && Defs.count(End->getOperand(1).getReg())) {
897  Defs.insert(End->getOperand(0).getReg());
898  ++End;
899  }
900 
901  // Check if the reschedule will not break depedencies.
902  unsigned NumVisited = 0;
903  MachineBasicBlock::iterator KillPos = KillMI;
904  ++KillPos;
905  for (MachineBasicBlock::iterator I = End; I != KillPos; ++I) {
906  MachineInstr *OtherMI = I;
907  // DBG_VALUE cannot be counted against the limit.
908  if (OtherMI->isDebugValue())
909  continue;
910  if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.
911  return false;
912  ++NumVisited;
913  if (OtherMI->hasUnmodeledSideEffects() || OtherMI->isCall() ||
914  OtherMI->isBranch() || OtherMI->isTerminator())
915  // Don't move pass calls, etc.
916  return false;
917  for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
918  const MachineOperand &MO = OtherMI->getOperand(i);
919  if (!MO.isReg())
920  continue;
921  unsigned MOReg = MO.getReg();
922  if (!MOReg)
923  continue;
924  if (MO.isDef()) {
925  if (Uses.count(MOReg))
926  // Physical register use would be clobbered.
927  return false;
928  if (!MO.isDead() && Defs.count(MOReg))
929  // May clobber a physical register def.
930  // FIXME: This may be too conservative. It's ok if the instruction
931  // is sunken completely below the use.
932  return false;
933  } else {
934  if (Defs.count(MOReg))
935  return false;
936  bool isKill = MO.isKill() ||
937  (LIS && isPlainlyKilled(OtherMI, MOReg, LIS));
938  if (MOReg != Reg &&
939  ((isKill && Uses.count(MOReg)) || Kills.count(MOReg)))
940  // Don't want to extend other live ranges and update kills.
941  return false;
942  if (MOReg == Reg && !isKill)
943  // We can't schedule across a use of the register in question.
944  return false;
945  // Ensure that if this is register in question, its the kill we expect.
946  assert((MOReg != Reg || OtherMI == KillMI) &&
947  "Found multiple kills of a register in a basic block");
948  }
949  }
950  }
951 
952  // Move debug info as well.
953  while (Begin != MBB->begin() && std::prev(Begin)->isDebugValue())
954  --Begin;
955 
956  nmi = End;
957  MachineBasicBlock::iterator InsertPos = KillPos;
958  if (LIS) {
959  // We have to move the copies first so that the MBB is still well-formed
960  // when calling handleMove().
961  for (MachineBasicBlock::iterator MBBI = AfterMI; MBBI != End;) {
962  MachineInstr *CopyMI = MBBI;
963  ++MBBI;
964  MBB->splice(InsertPos, MBB, CopyMI);
965  LIS->handleMove(CopyMI);
966  InsertPos = CopyMI;
967  }
968  End = std::next(MachineBasicBlock::iterator(MI));
969  }
970 
971  // Copies following MI may have been moved as well.
972  MBB->splice(InsertPos, MBB, Begin, End);
973  DistanceMap.erase(DI);
974 
975  // Update live variables
976  if (LIS) {
977  LIS->handleMove(MI);
978  } else {
979  LV->removeVirtualRegisterKilled(Reg, KillMI);
980  LV->addVirtualRegisterKilled(Reg, MI);
981  }
982 
983  DEBUG(dbgs() << "\trescheduled below kill: " << *KillMI);
984  return true;
985 }
986 
987 /// isDefTooClose - Return true if the re-scheduling will put the given
988 /// instruction too close to the defs of its register dependencies.
989 bool TwoAddressInstructionPass::isDefTooClose(unsigned Reg, unsigned Dist,
990  MachineInstr *MI) {
991  for (MachineInstr &DefMI : MRI->def_instructions(Reg)) {
992  if (DefMI.getParent() != MBB || DefMI.isCopy() || DefMI.isCopyLike())
993  continue;
994  if (&DefMI == MI)
995  return true; // MI is defining something KillMI uses
996  DenseMap<MachineInstr*, unsigned>::iterator DDI = DistanceMap.find(&DefMI);
997  if (DDI == DistanceMap.end())
998  return true; // Below MI
999  unsigned DefDist = DDI->second;
1000  assert(Dist > DefDist && "Visited def already?");
1001  if (TII->getInstrLatency(InstrItins, &DefMI) > (Dist - DefDist))
1002  return true;
1003  }
1004  return false;
1005 }
1006 
1007 /// rescheduleKillAboveMI - If there is one more local instruction that reads
1008 /// 'Reg' and it kills 'Reg, consider moving the kill instruction above the
1009 /// current two-address instruction in order to eliminate the need for the
1010 /// copy.
1011 bool TwoAddressInstructionPass::
1012 rescheduleKillAboveMI(MachineBasicBlock::iterator &mi,
1014  unsigned Reg) {
1015  // Bail immediately if we don't have LV or LIS available. We use them to find
1016  // kills efficiently.
1017  if (!LV && !LIS)
1018  return false;
1019 
1020  MachineInstr *MI = &*mi;
1022  if (DI == DistanceMap.end())
1023  // Must be created from unfolded load. Don't waste time trying this.
1024  return false;
1025 
1026  MachineInstr *KillMI = nullptr;
1027  if (LIS) {
1028  LiveInterval &LI = LIS->getInterval(Reg);
1029  assert(LI.end() != LI.begin() &&
1030  "Reg should not have empty live interval.");
1031 
1032  SlotIndex MBBEndIdx = LIS->getMBBEndIdx(MBB).getPrevSlot();
1033  LiveInterval::const_iterator I = LI.find(MBBEndIdx);
1034  if (I != LI.end() && I->start < MBBEndIdx)
1035  return false;
1036 
1037  --I;
1038  KillMI = LIS->getInstructionFromIndex(I->end);
1039  } else {
1040  KillMI = LV->getVarInfo(Reg).findKill(MBB);
1041  }
1042  if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike())
1043  // Don't mess with copies, they may be coalesced later.
1044  return false;
1045 
1046  unsigned DstReg;
1047  if (isTwoAddrUse(*KillMI, Reg, DstReg))
1048  return false;
1049 
1050  bool SeenStore = true;
1051  if (!KillMI->isSafeToMove(AA, SeenStore))
1052  return false;
1053 
1054  SmallSet<unsigned, 2> Uses;
1055  SmallSet<unsigned, 2> Kills;
1056  SmallSet<unsigned, 2> Defs;
1057  SmallSet<unsigned, 2> LiveDefs;
1058  for (unsigned i = 0, e = KillMI->getNumOperands(); i != e; ++i) {
1059  const MachineOperand &MO = KillMI->getOperand(i);
1060  if (!MO.isReg())
1061  continue;
1062  unsigned MOReg = MO.getReg();
1063  if (MO.isUse()) {
1064  if (!MOReg)
1065  continue;
1066  if (isDefTooClose(MOReg, DI->second, MI))
1067  return false;
1068  bool isKill = MO.isKill() || (LIS && isPlainlyKilled(KillMI, MOReg, LIS));
1069  if (MOReg == Reg && !isKill)
1070  return false;
1071  Uses.insert(MOReg);
1072  if (isKill && MOReg != Reg)
1073  Kills.insert(MOReg);
1074  } else if (TargetRegisterInfo::isPhysicalRegister(MOReg)) {
1075  Defs.insert(MOReg);
1076  if (!MO.isDead())
1077  LiveDefs.insert(MOReg);
1078  }
1079  }
1080 
1081  // Check if the reschedule will not break depedencies.
1082  unsigned NumVisited = 0;
1083  MachineBasicBlock::iterator KillPos = KillMI;
1084  for (MachineBasicBlock::iterator I = mi; I != KillPos; ++I) {
1085  MachineInstr *OtherMI = I;
1086  // DBG_VALUE cannot be counted against the limit.
1087  if (OtherMI->isDebugValue())
1088  continue;
1089  if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.
1090  return false;
1091  ++NumVisited;
1092  if (OtherMI->hasUnmodeledSideEffects() || OtherMI->isCall() ||
1093  OtherMI->isBranch() || OtherMI->isTerminator())
1094  // Don't move pass calls, etc.
1095  return false;
1096  SmallVector<unsigned, 2> OtherDefs;
1097  for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
1098  const MachineOperand &MO = OtherMI->getOperand(i);
1099  if (!MO.isReg())
1100  continue;
1101  unsigned MOReg = MO.getReg();
1102  if (!MOReg)
1103  continue;
1104  if (MO.isUse()) {
1105  if (Defs.count(MOReg))
1106  // Moving KillMI can clobber the physical register if the def has
1107  // not been seen.
1108  return false;
1109  if (Kills.count(MOReg))
1110  // Don't want to extend other live ranges and update kills.
1111  return false;
1112  if (OtherMI != MI && MOReg == Reg &&
1113  !(MO.isKill() || (LIS && isPlainlyKilled(OtherMI, MOReg, LIS))))
1114  // We can't schedule across a use of the register in question.
1115  return false;
1116  } else {
1117  OtherDefs.push_back(MOReg);
1118  }
1119  }
1120 
1121  for (unsigned i = 0, e = OtherDefs.size(); i != e; ++i) {
1122  unsigned MOReg = OtherDefs[i];
1123  if (Uses.count(MOReg))
1124  return false;
1126  LiveDefs.count(MOReg))
1127  return false;
1128  // Physical register def is seen.
1129  Defs.erase(MOReg);
1130  }
1131  }
1132 
1133  // Move the old kill above MI, don't forget to move debug info as well.
1134  MachineBasicBlock::iterator InsertPos = mi;
1135  while (InsertPos != MBB->begin() && std::prev(InsertPos)->isDebugValue())
1136  --InsertPos;
1137  MachineBasicBlock::iterator From = KillMI;
1138  MachineBasicBlock::iterator To = std::next(From);
1139  while (std::prev(From)->isDebugValue())
1140  --From;
1141  MBB->splice(InsertPos, MBB, From, To);
1142 
1143  nmi = std::prev(InsertPos); // Backtrack so we process the moved instr.
1144  DistanceMap.erase(DI);
1145 
1146  // Update live variables
1147  if (LIS) {
1148  LIS->handleMove(KillMI);
1149  } else {
1150  LV->removeVirtualRegisterKilled(Reg, KillMI);
1151  LV->addVirtualRegisterKilled(Reg, MI);
1152  }
1153 
1154  DEBUG(dbgs() << "\trescheduled kill: " << *KillMI);
1155  return true;
1156 }
1157 
1158 /// tryInstructionTransform - For the case where an instruction has a single
1159 /// pair of tied register operands, attempt some transformations that may
1160 /// either eliminate the tied operands or improve the opportunities for
1161 /// coalescing away the register copy. Returns true if no copy needs to be
1162 /// inserted to untie mi's operands (either because they were untied, or
1163 /// because mi was rescheduled, and will be visited again later). If the
1164 /// shouldOnlyCommute flag is true, only instruction commutation is attempted.
1165 bool TwoAddressInstructionPass::
1166 tryInstructionTransform(MachineBasicBlock::iterator &mi,
1168  unsigned SrcIdx, unsigned DstIdx,
1169  unsigned Dist, bool shouldOnlyCommute) {
1170  if (OptLevel == CodeGenOpt::None)
1171  return false;
1172 
1173  MachineInstr &MI = *mi;
1174  unsigned regA = MI.getOperand(DstIdx).getReg();
1175  unsigned regB = MI.getOperand(SrcIdx).getReg();
1176 
1178  "cannot make instruction into two-address form");
1179  bool regBKilled = isKilled(MI, regB, MRI, TII, LIS, true);
1180 
1182  scanUses(regA);
1183 
1184  // Check if it is profitable to commute the operands.
1185  unsigned SrcOp1, SrcOp2;
1186  unsigned regC = 0;
1187  unsigned regCIdx = ~0U;
1188  bool TryCommute = false;
1189  bool AggressiveCommute = false;
1190  if (MI.isCommutable() && MI.getNumOperands() >= 3 &&
1191  TII->findCommutedOpIndices(&MI, SrcOp1, SrcOp2)) {
1192  if (SrcIdx == SrcOp1)
1193  regCIdx = SrcOp2;
1194  else if (SrcIdx == SrcOp2)
1195  regCIdx = SrcOp1;
1196 
1197  if (regCIdx != ~0U) {
1198  regC = MI.getOperand(regCIdx).getReg();
1199  if (!regBKilled && isKilled(MI, regC, MRI, TII, LIS, false))
1200  // If C dies but B does not, swap the B and C operands.
1201  // This makes the live ranges of A and C joinable.
1202  TryCommute = true;
1203  else if (isProfitableToCommute(regA, regB, regC, &MI, Dist)) {
1204  TryCommute = true;
1205  AggressiveCommute = true;
1206  }
1207  }
1208  }
1209 
1210  // If the instruction is convertible to 3 Addr, instead
1211  // of returning try 3 Addr transformation aggresively and
1212  // use this variable to check later. Because it might be better.
1213  // For example, we can just use `leal (%rsi,%rdi), %eax` and `ret`
1214  // instead of the following code.
1215  // addl %esi, %edi
1216  // movl %edi, %eax
1217  // ret
1218  bool Commuted = false;
1219 
1220  // If it's profitable to commute, try to do so.
1221  if (TryCommute && commuteInstruction(mi, regB, regC, Dist)) {
1222  Commuted = true;
1223  ++NumCommuted;
1224  if (AggressiveCommute)
1225  ++NumAggrCommuted;
1226  if (!MI.isConvertibleTo3Addr())
1227  return false;
1228  }
1229 
1230  if (shouldOnlyCommute)
1231  return false;
1232 
1233  // If there is one more use of regB later in the same MBB, consider
1234  // re-schedule this MI below it.
1235  if (!Commuted && EnableRescheduling && rescheduleMIBelowKill(mi, nmi, regB)) {
1236  ++NumReSchedDowns;
1237  return true;
1238  }
1239 
1240  if (MI.isConvertibleTo3Addr()) {
1241  // This instruction is potentially convertible to a true
1242  // three-address instruction. Check if it is profitable.
1243  if (!regBKilled || isProfitableToConv3Addr(regA, regB)) {
1244  // Try to convert it.
1245  if (convertInstTo3Addr(mi, nmi, regA, regB, Dist)) {
1246  ++NumConvertedTo3Addr;
1247  return true; // Done with this instruction.
1248  }
1249  }
1250  }
1251 
1252  // Return if it is commuted but 3 addr conversion is failed.
1253  if (Commuted)
1254  return false;
1255 
1256  // If there is one more use of regB later in the same MBB, consider
1257  // re-schedule it before this MI if it's legal.
1258  if (EnableRescheduling && rescheduleKillAboveMI(mi, nmi, regB)) {
1259  ++NumReSchedUps;
1260  return true;
1261  }
1262 
1263  // If this is an instruction with a load folded into it, try unfolding
1264  // the load, e.g. avoid this:
1265  // movq %rdx, %rcx
1266  // addq (%rax), %rcx
1267  // in favor of this:
1268  // movq (%rax), %rcx
1269  // addq %rdx, %rcx
1270  // because it's preferable to schedule a load than a register copy.
1271  if (MI.mayLoad() && !regBKilled) {
1272  // Determine if a load can be unfolded.
1273  unsigned LoadRegIndex;
1274  unsigned NewOpc =
1275  TII->getOpcodeAfterMemoryUnfold(MI.getOpcode(),
1276  /*UnfoldLoad=*/true,
1277  /*UnfoldStore=*/false,
1278  &LoadRegIndex);
1279  if (NewOpc != 0) {
1280  const MCInstrDesc &UnfoldMCID = TII->get(NewOpc);
1281  if (UnfoldMCID.getNumDefs() == 1) {
1282  // Unfold the load.
1283  DEBUG(dbgs() << "2addr: UNFOLDING: " << MI);
1284  const TargetRegisterClass *RC =
1285  TRI->getAllocatableClass(
1286  TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI, *MF));
1287  unsigned Reg = MRI->createVirtualRegister(RC);
1289  if (!TII->unfoldMemoryOperand(*MF, &MI, Reg,
1290  /*UnfoldLoad=*/true,/*UnfoldStore=*/false,
1291  NewMIs)) {
1292  DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
1293  return false;
1294  }
1295  assert(NewMIs.size() == 2 &&
1296  "Unfolded a load into multiple instructions!");
1297  // The load was previously folded, so this is the only use.
1298  NewMIs[1]->addRegisterKilled(Reg, TRI);
1299 
1300  // Tentatively insert the instructions into the block so that they
1301  // look "normal" to the transformation logic.
1302  MBB->insert(mi, NewMIs[0]);
1303  MBB->insert(mi, NewMIs[1]);
1304 
1305  DEBUG(dbgs() << "2addr: NEW LOAD: " << *NewMIs[0]
1306  << "2addr: NEW INST: " << *NewMIs[1]);
1307 
1308  // Transform the instruction, now that it no longer has a load.
1309  unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA);
1310  unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB);
1311  MachineBasicBlock::iterator NewMI = NewMIs[1];
1312  bool TransformResult =
1313  tryInstructionTransform(NewMI, mi, NewSrcIdx, NewDstIdx, Dist, true);
1314  (void)TransformResult;
1315  assert(!TransformResult &&
1316  "tryInstructionTransform() should return false.");
1317  if (NewMIs[1]->getOperand(NewSrcIdx).isKill()) {
1318  // Success, or at least we made an improvement. Keep the unfolded
1319  // instructions and discard the original.
1320  if (LV) {
1321  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1322  MachineOperand &MO = MI.getOperand(i);
1323  if (MO.isReg() &&
1325  if (MO.isUse()) {
1326  if (MO.isKill()) {
1327  if (NewMIs[0]->killsRegister(MO.getReg()))
1328  LV->replaceKillInstruction(MO.getReg(), &MI, NewMIs[0]);
1329  else {
1330  assert(NewMIs[1]->killsRegister(MO.getReg()) &&
1331  "Kill missing after load unfold!");
1332  LV->replaceKillInstruction(MO.getReg(), &MI, NewMIs[1]);
1333  }
1334  }
1335  } else if (LV->removeVirtualRegisterDead(MO.getReg(), &MI)) {
1336  if (NewMIs[1]->registerDefIsDead(MO.getReg()))
1337  LV->addVirtualRegisterDead(MO.getReg(), NewMIs[1]);
1338  else {
1339  assert(NewMIs[0]->registerDefIsDead(MO.getReg()) &&
1340  "Dead flag missing after load unfold!");
1341  LV->addVirtualRegisterDead(MO.getReg(), NewMIs[0]);
1342  }
1343  }
1344  }
1345  }
1346  LV->addVirtualRegisterKilled(Reg, NewMIs[1]);
1347  }
1348 
1349  SmallVector<unsigned, 4> OrigRegs;
1350  if (LIS) {
1352  MOE = MI.operands_end(); MOI != MOE; ++MOI) {
1353  if (MOI->isReg())
1354  OrigRegs.push_back(MOI->getReg());
1355  }
1356  }
1357 
1358  MI.eraseFromParent();
1359 
1360  // Update LiveIntervals.
1361  if (LIS) {
1362  MachineBasicBlock::iterator Begin(NewMIs[0]);
1363  MachineBasicBlock::iterator End(NewMIs[1]);
1364  LIS->repairIntervalsInRange(MBB, Begin, End, OrigRegs);
1365  }
1366 
1367  mi = NewMIs[1];
1368  } else {
1369  // Transforming didn't eliminate the tie and didn't lead to an
1370  // improvement. Clean up the unfolded instructions and keep the
1371  // original.
1372  DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
1373  NewMIs[0]->eraseFromParent();
1374  NewMIs[1]->eraseFromParent();
1375  }
1376  }
1377  }
1378  }
1379 
1380  return false;
1381 }
1382 
1383 // Collect tied operands of MI that need to be handled.
1384 // Rewrite trivial cases immediately.
1385 // Return true if any tied operands where found, including the trivial ones.
1386 bool TwoAddressInstructionPass::
1387 collectTiedOperands(MachineInstr *MI, TiedOperandMap &TiedOperands) {
1388  const MCInstrDesc &MCID = MI->getDesc();
1389  bool AnyOps = false;
1390  unsigned NumOps = MI->getNumOperands();
1391 
1392  for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) {
1393  unsigned DstIdx = 0;
1394  if (!MI->isRegTiedToDefOperand(SrcIdx, &DstIdx))
1395  continue;
1396  AnyOps = true;
1397  MachineOperand &SrcMO = MI->getOperand(SrcIdx);
1398  MachineOperand &DstMO = MI->getOperand(DstIdx);
1399  unsigned SrcReg = SrcMO.getReg();
1400  unsigned DstReg = DstMO.getReg();
1401  // Tied constraint already satisfied?
1402  if (SrcReg == DstReg)
1403  continue;
1404 
1405  assert(SrcReg && SrcMO.isUse() && "two address instruction invalid");
1406 
1407  // Deal with <undef> uses immediately - simply rewrite the src operand.
1408  if (SrcMO.isUndef() && !DstMO.getSubReg()) {
1409  // Constrain the DstReg register class if required.
1411  if (const TargetRegisterClass *RC = TII->getRegClass(MCID, SrcIdx,
1412  TRI, *MF))
1413  MRI->constrainRegClass(DstReg, RC);
1414  SrcMO.setReg(DstReg);
1415  SrcMO.setSubReg(0);
1416  DEBUG(dbgs() << "\t\trewrite undef:\t" << *MI);
1417  continue;
1418  }
1419  TiedOperands[SrcReg].push_back(std::make_pair(SrcIdx, DstIdx));
1420  }
1421  return AnyOps;
1422 }
1423 
1424 // Process a list of tied MI operands that all use the same source register.
1425 // The tied pairs are of the form (SrcIdx, DstIdx).
1426 void
1427 TwoAddressInstructionPass::processTiedPairs(MachineInstr *MI,
1428  TiedPairList &TiedPairs,
1429  unsigned &Dist) {
1430  bool IsEarlyClobber = false;
1431  for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) {
1432  const MachineOperand &DstMO = MI->getOperand(TiedPairs[tpi].second);
1433  IsEarlyClobber |= DstMO.isEarlyClobber();
1434  }
1435 
1436  bool RemovedKillFlag = false;
1437  bool AllUsesCopied = true;
1438  unsigned LastCopiedReg = 0;
1439  SlotIndex LastCopyIdx;
1440  unsigned RegB = 0;
1441  unsigned SubRegB = 0;
1442  for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) {
1443  unsigned SrcIdx = TiedPairs[tpi].first;
1444  unsigned DstIdx = TiedPairs[tpi].second;
1445 
1446  const MachineOperand &DstMO = MI->getOperand(DstIdx);
1447  unsigned RegA = DstMO.getReg();
1448 
1449  // Grab RegB from the instruction because it may have changed if the
1450  // instruction was commuted.
1451  RegB = MI->getOperand(SrcIdx).getReg();
1452  SubRegB = MI->getOperand(SrcIdx).getSubReg();
1453 
1454  if (RegA == RegB) {
1455  // The register is tied to multiple destinations (or else we would
1456  // not have continued this far), but this use of the register
1457  // already matches the tied destination. Leave it.
1458  AllUsesCopied = false;
1459  continue;
1460  }
1461  LastCopiedReg = RegA;
1462 
1464  "cannot make instruction into two-address form");
1465 
1466 #ifndef NDEBUG
1467  // First, verify that we don't have a use of "a" in the instruction
1468  // (a = b + a for example) because our transformation will not
1469  // work. This should never occur because we are in SSA form.
1470  for (unsigned i = 0; i != MI->getNumOperands(); ++i)
1471  assert(i == DstIdx ||
1472  !MI->getOperand(i).isReg() ||
1473  MI->getOperand(i).getReg() != RegA);
1474 #endif
1475 
1476  // Emit a copy.
1477  MachineInstrBuilder MIB = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1478  TII->get(TargetOpcode::COPY), RegA);
1479  // If this operand is folding a truncation, the truncation now moves to the
1480  // copy so that the register classes remain valid for the operands.
1481  MIB.addReg(RegB, 0, SubRegB);
1482  const TargetRegisterClass *RC = MRI->getRegClass(RegB);
1483  if (SubRegB) {
1485  assert(TRI->getMatchingSuperRegClass(RC, MRI->getRegClass(RegA),
1486  SubRegB) &&
1487  "tied subregister must be a truncation");
1488  // The superreg class will not be used to constrain the subreg class.
1489  RC = nullptr;
1490  }
1491  else {
1492  assert(TRI->getMatchingSuperReg(RegA, SubRegB, MRI->getRegClass(RegB))
1493  && "tied subregister must be a truncation");
1494  }
1495  }
1496 
1497  // Update DistanceMap.
1499  --PrevMI;
1500  DistanceMap.insert(std::make_pair(PrevMI, Dist));
1501  DistanceMap[MI] = ++Dist;
1502 
1503  if (LIS) {
1504  LastCopyIdx = LIS->InsertMachineInstrInMaps(PrevMI).getRegSlot();
1505 
1507  LiveInterval &LI = LIS->getInterval(RegA);
1508  VNInfo *VNI = LI.getNextValue(LastCopyIdx, LIS->getVNInfoAllocator());
1509  SlotIndex endIdx =
1510  LIS->getInstructionIndex(MI).getRegSlot(IsEarlyClobber);
1511  LI.addSegment(LiveInterval::Segment(LastCopyIdx, endIdx, VNI));
1512  }
1513  }
1514 
1515  DEBUG(dbgs() << "\t\tprepend:\t" << *MIB);
1516 
1517  MachineOperand &MO = MI->getOperand(SrcIdx);
1518  assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() &&
1519  "inconsistent operand info for 2-reg pass");
1520  if (MO.isKill()) {
1521  MO.setIsKill(false);
1522  RemovedKillFlag = true;
1523  }
1524 
1525  // Make sure regA is a legal regclass for the SrcIdx operand.
1528  MRI->constrainRegClass(RegA, RC);
1529  MO.setReg(RegA);
1530  // The getMatchingSuper asserts guarantee that the register class projected
1531  // by SubRegB is compatible with RegA with no subregister. So regardless of
1532  // whether the dest oper writes a subreg, the source oper should not.
1533  MO.setSubReg(0);
1534 
1535  // Propagate SrcRegMap.
1536  SrcRegMap[RegA] = RegB;
1537  }
1538 
1539 
1540  if (AllUsesCopied) {
1541  if (!IsEarlyClobber) {
1542  // Replace other (un-tied) uses of regB with LastCopiedReg.
1543  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1544  MachineOperand &MO = MI->getOperand(i);
1545  if (MO.isReg() && MO.getReg() == RegB && MO.getSubReg() == SubRegB &&
1546  MO.isUse()) {
1547  if (MO.isKill()) {
1548  MO.setIsKill(false);
1549  RemovedKillFlag = true;
1550  }
1551  MO.setReg(LastCopiedReg);
1552  MO.setSubReg(0);
1553  }
1554  }
1555  }
1556 
1557  // Update live variables for regB.
1558  if (RemovedKillFlag && LV && LV->getVarInfo(RegB).removeKill(MI)) {
1560  --PrevMI;
1561  LV->addVirtualRegisterKilled(RegB, PrevMI);
1562  }
1563 
1564  // Update LiveIntervals.
1565  if (LIS) {
1566  LiveInterval &LI = LIS->getInterval(RegB);
1567  SlotIndex MIIdx = LIS->getInstructionIndex(MI);
1568  LiveInterval::const_iterator I = LI.find(MIIdx);
1569  assert(I != LI.end() && "RegB must be live-in to use.");
1570 
1571  SlotIndex UseIdx = MIIdx.getRegSlot(IsEarlyClobber);
1572  if (I->end == UseIdx)
1573  LI.removeSegment(LastCopyIdx, UseIdx);
1574  }
1575 
1576  } else if (RemovedKillFlag) {
1577  // Some tied uses of regB matched their destination registers, so
1578  // regB is still used in this instruction, but a kill flag was
1579  // removed from a different tied use of regB, so now we need to add
1580  // a kill flag to one of the remaining uses of regB.
1581  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1582  MachineOperand &MO = MI->getOperand(i);
1583  if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {
1584  MO.setIsKill(true);
1585  break;
1586  }
1587  }
1588  }
1589 }
1590 
1591 /// runOnMachineFunction - Reduce two-address instructions to two operands.
1592 ///
1593 bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &Func) {
1594  MF = &Func;
1595  const TargetMachine &TM = MF->getTarget();
1596  MRI = &MF->getRegInfo();
1597  TII = MF->getSubtarget().getInstrInfo();
1598  TRI = MF->getSubtarget().getRegisterInfo();
1599  InstrItins = MF->getSubtarget().getInstrItineraryData();
1600  LV = getAnalysisIfAvailable<LiveVariables>();
1601  LIS = getAnalysisIfAvailable<LiveIntervals>();
1602  AA = &getAnalysis<AliasAnalysis>();
1603  OptLevel = TM.getOptLevel();
1604 
1605  bool MadeChange = false;
1606 
1607  DEBUG(dbgs() << "********** REWRITING TWO-ADDR INSTRS **********\n");
1608  DEBUG(dbgs() << "********** Function: "
1609  << MF->getName() << '\n');
1610 
1611  // This pass takes the function out of SSA form.
1612  MRI->leaveSSA();
1613 
1614  TiedOperandMap TiedOperands;
1615  for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end();
1616  MBBI != MBBE; ++MBBI) {
1617  MBB = MBBI;
1618  unsigned Dist = 0;
1619  DistanceMap.clear();
1620  SrcRegMap.clear();
1621  DstRegMap.clear();
1622  Processed.clear();
1623  for (MachineBasicBlock::iterator mi = MBB->begin(), me = MBB->end();
1624  mi != me; ) {
1625  MachineBasicBlock::iterator nmi = std::next(mi);
1626  if (mi->isDebugValue()) {
1627  mi = nmi;
1628  continue;
1629  }
1630 
1631  // Expand REG_SEQUENCE instructions. This will position mi at the first
1632  // expanded instruction.
1633  if (mi->isRegSequence())
1634  eliminateRegSequence(mi);
1635 
1636  DistanceMap.insert(std::make_pair(mi, ++Dist));
1637 
1638  processCopy(&*mi);
1639 
1640  // First scan through all the tied register uses in this instruction
1641  // and record a list of pairs of tied operands for each register.
1642  if (!collectTiedOperands(mi, TiedOperands)) {
1643  mi = nmi;
1644  continue;
1645  }
1646 
1647  ++NumTwoAddressInstrs;
1648  MadeChange = true;
1649  DEBUG(dbgs() << '\t' << *mi);
1650 
1651  // If the instruction has a single pair of tied operands, try some
1652  // transformations that may either eliminate the tied operands or
1653  // improve the opportunities for coalescing away the register copy.
1654  if (TiedOperands.size() == 1) {
1656  = TiedOperands.begin()->second;
1657  if (TiedPairs.size() == 1) {
1658  unsigned SrcIdx = TiedPairs[0].first;
1659  unsigned DstIdx = TiedPairs[0].second;
1660  unsigned SrcReg = mi->getOperand(SrcIdx).getReg();
1661  unsigned DstReg = mi->getOperand(DstIdx).getReg();
1662  if (SrcReg != DstReg &&
1663  tryInstructionTransform(mi, nmi, SrcIdx, DstIdx, Dist, false)) {
1664  // The tied operands have been eliminated or shifted further down the
1665  // block to ease elimination. Continue processing with 'nmi'.
1666  TiedOperands.clear();
1667  mi = nmi;
1668  continue;
1669  }
1670  }
1671  }
1672 
1673  // Now iterate over the information collected above.
1674  for (TiedOperandMap::iterator OI = TiedOperands.begin(),
1675  OE = TiedOperands.end(); OI != OE; ++OI) {
1676  processTiedPairs(mi, OI->second, Dist);
1677  DEBUG(dbgs() << "\t\trewrite to:\t" << *mi);
1678  }
1679 
1680  // Rewrite INSERT_SUBREG as COPY now that we no longer need SSA form.
1681  if (mi->isInsertSubreg()) {
1682  // From %reg = INSERT_SUBREG %reg, %subreg, subidx
1683  // To %reg:subidx = COPY %subreg
1684  unsigned SubIdx = mi->getOperand(3).getImm();
1685  mi->RemoveOperand(3);
1686  assert(mi->getOperand(0).getSubReg() == 0 && "Unexpected subreg idx");
1687  mi->getOperand(0).setSubReg(SubIdx);
1688  mi->getOperand(0).setIsUndef(mi->getOperand(1).isUndef());
1689  mi->RemoveOperand(1);
1690  mi->setDesc(TII->get(TargetOpcode::COPY));
1691  DEBUG(dbgs() << "\t\tconvert to:\t" << *mi);
1692  }
1693 
1694  // Clear TiedOperands here instead of at the top of the loop
1695  // since most instructions do not have tied operands.
1696  TiedOperands.clear();
1697  mi = nmi;
1698  }
1699  }
1700 
1701  if (LIS)
1702  MF->verify(this, "After two-address instruction pass");
1703 
1704  return MadeChange;
1705 }
1706 
1707 /// Eliminate a REG_SEQUENCE instruction as part of the de-ssa process.
1708 ///
1709 /// The instruction is turned into a sequence of sub-register copies:
1710 ///
1711 /// %dst = REG_SEQUENCE %v1, ssub0, %v2, ssub1
1712 ///
1713 /// Becomes:
1714 ///
1715 /// %dst:ssub0<def,undef> = COPY %v1
1716 /// %dst:ssub1<def> = COPY %v2
1717 ///
1718 void TwoAddressInstructionPass::
1719 eliminateRegSequence(MachineBasicBlock::iterator &MBBI) {
1720  MachineInstr *MI = MBBI;
1721  unsigned DstReg = MI->getOperand(0).getReg();
1722  if (MI->getOperand(0).getSubReg() ||
1724  !(MI->getNumOperands() & 1)) {
1725  DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << *MI);
1726  llvm_unreachable(nullptr);
1727  }
1728 
1729  SmallVector<unsigned, 4> OrigRegs;
1730  if (LIS) {
1731  OrigRegs.push_back(MI->getOperand(0).getReg());
1732  for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2)
1733  OrigRegs.push_back(MI->getOperand(i).getReg());
1734  }
1735 
1736  bool DefEmitted = false;
1737  for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) {
1738  MachineOperand &UseMO = MI->getOperand(i);
1739  unsigned SrcReg = UseMO.getReg();
1740  unsigned SubIdx = MI->getOperand(i+1).getImm();
1741  // Nothing needs to be inserted for <undef> operands.
1742  if (UseMO.isUndef())
1743  continue;
1744 
1745  // Defer any kill flag to the last operand using SrcReg. Otherwise, we
1746  // might insert a COPY that uses SrcReg after is was killed.
1747  bool isKill = UseMO.isKill();
1748  if (isKill)
1749  for (unsigned j = i + 2; j < e; j += 2)
1750  if (MI->getOperand(j).getReg() == SrcReg) {
1751  MI->getOperand(j).setIsKill();
1752  UseMO.setIsKill(false);
1753  isKill = false;
1754  break;
1755  }
1756 
1757  // Insert the sub-register copy.
1758  MachineInstr *CopyMI = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1759  TII->get(TargetOpcode::COPY))
1760  .addReg(DstReg, RegState::Define, SubIdx)
1761  .addOperand(UseMO);
1762 
1763  // The first def needs an <undef> flag because there is no live register
1764  // before it.
1765  if (!DefEmitted) {
1766  CopyMI->getOperand(0).setIsUndef(true);
1767  // Return an iterator pointing to the first inserted instr.
1768  MBBI = CopyMI;
1769  }
1770  DefEmitted = true;
1771 
1772  // Update LiveVariables' kill info.
1773  if (LV && isKill && !TargetRegisterInfo::isPhysicalRegister(SrcReg))
1774  LV->replaceKillInstruction(SrcReg, MI, CopyMI);
1775 
1776  DEBUG(dbgs() << "Inserted: " << *CopyMI);
1777  }
1778 
1779  MachineBasicBlock::iterator EndMBBI =
1780  std::next(MachineBasicBlock::iterator(MI));
1781 
1782  if (!DefEmitted) {
1783  DEBUG(dbgs() << "Turned: " << *MI << " into an IMPLICIT_DEF");
1785  for (int j = MI->getNumOperands() - 1, ee = 0; j > ee; --j)
1786  MI->RemoveOperand(j);
1787  } else {
1788  DEBUG(dbgs() << "Eliminated: " << *MI);
1789  MI->eraseFromParent();
1790  }
1791 
1792  // Udpate LiveIntervals.
1793  if (LIS)
1794  LIS->repairIntervalsInRange(MBB, MBBI, EndMBBI, OrigRegs);
1795 }
bool isImplicit() const
void push_back(const T &Elt)
Definition: SmallVector.h:222
mop_iterator operands_end()
Definition: MachineInstr.h:290
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:427
STATISTIC(NumFunctions,"Total number of functions")
static MachineInstr * getSingleDef(unsigned Reg, MachineBasicBlock *BB, const MachineRegisterInfo *MRI)
getSingleDef – return the MachineInstr* if it is the single def of the Reg in current BB...
bool isConvertibleTo3Addr(QueryType Type=IgnoreBundle) const
Return true if this is a 2-address instruction which can be changed into a 3-address instruction if n...
Definition: MachineInstr.h:625
static unsigned getMappedReg(unsigned Reg, DenseMap< unsigned, unsigned > &RegMap)
getMappedReg - Return the physical register the specified virtual register might be mapped to...
static bool isKilled(MachineInstr &MI, unsigned Reg, const MachineRegisterInfo *MRI, const TargetInstrInfo *TII, LiveIntervals *LIS, bool allowFalsePositives)
isKilled - Test if the given register value, which is used by the given instruction, is killed by the given instruction.
use_instr_nodbg_iterator use_instr_nodbg_begin(unsigned RegNo) const
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:191
char & MachineDominatorsID
MachineDominators - This pass is a machine dominators analysis pass.
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:588
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:138
void setIsUndef(bool Val=true)
bool isDead() const
SlotIndex getInstructionIndex(const MachineInstr *instr) const
Returns the base index of the given instruction.
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
INITIALIZE_PASS_BEGIN(TwoAddressInstructionPass,"twoaddressinstruction","Two-Address instruction pass", false, false) INITIALIZE_PASS_END(TwoAddressInstructionPass
MachineOperand * findRegisterUseOperand(unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterUseOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
Definition: MachineInstr.h:894
static cl::opt< bool > EnableRescheduling("twoaddr-reschedule", cl::desc("Coalesce copies by rescheduling (default=true)"), cl::init(true), cl::Hidden)
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:264
VNInfo - Value Number Information.
Definition: LiveInterval.h:45
bool erase(const T &V)
Definition: SmallSet.h:96
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:419
bool isNotInMIMap(const MachineInstr *Instr) const
isNotInMIMap - returns true if the specified machine instr has been removed or was never entered in t...
COPY - Target-independent register copy.
Definition: TargetOpcodes.h:86
AnalysisUsage & addRequired()
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
MCInst const & instruction(MCInst const &MCB, size_t Index)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
iterator end()
Definition: LiveInterval.h:206
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APInt.h:33
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:75
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:566
Reg
All possible values of the reg field in the ModR/M byte.
bool isUndef() const
void initializeTwoAddressInstructionPassPass(PassRegistry &)
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:271
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
const HexagonRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
static bool regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI)
regsAreCompatible - Return true if the two registers are equal or aliased.
bool isKill() const
SlotIndexes pass.
Definition: SlotIndexes.h:334
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Definition: SmallVector.h:57
Two Address instruction false
iterator addSegment(Segment S)
Add the specified Segment to this range, merging segments as appropriate.
bool isCopyLike() const
Return true if the instruction behaves like a copy.
Definition: MachineInstr.h:790
AnalysisUsage & addPreservedID(const void *ID)
Itinerary data supplied by a subtarget to be used by a target.
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
int64_t getImm() const
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:267
SlotIndex getPrevSlot() const
Returns the previous slot in the index list.
Definition: SlotIndexes.h:292
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:120
TargetInstrInfo - Interface to description of machine instruction set.
bool isDebugValue() const
Definition: MachineInstr.h:748
bool isInsertSubreg() const
Definition: MachineInstr.h:766
bool isEarlyClobber() const
IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
Definition: TargetOpcodes.h:52
bundle_iterator< MachineInstr, instr_iterator > iterator
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:325
bool hasAtLeastOneValue() const
Definition: LiveInterval.h:284
bool regsOverlap(unsigned regA, unsigned regB) const
regsOverlap - Returns true if the two registers are equal or alias each other.
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:32
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
Two Address instruction pass
bool isCopy() const
Definition: MachineInstr.h:778
Represent the analysis usage information of a pass.
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore...
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:69
static MachineInstr * findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB, MachineRegisterInfo *MRI, const TargetInstrInfo *TII, bool &IsCopy, unsigned &DstReg, bool &IsDstPhys)
findOnlyInterestingUse - Given a register, if has a single in-basic block use, return the use instruc...
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
#define INITIALIZE_AG_DEPENDENCY(depName)
Definition: PassSupport.h:72
unsigned getSubReg() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void setIsKill(bool Val=true)
iterator find(SlotIndex Pos)
find - Return an iterator pointing to the first segment that ends after Pos, or end().
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:53
bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
void removeSegment(SlotIndex Start, SlotIndex End, bool RemoveDeadValNo=false)
Remove the specified segment from this range.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
Definition: SmallPtrSet.h:299
Segments::const_iterator const_iterator
Definition: LiveInterval.h:208
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
Definition: SlotIndexes.h:206
static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII, unsigned &SrcReg, unsigned &DstReg, bool &IsSrcPhys, bool &IsDstPhys)
isCopyToReg - Return true if the specified MI is a copy instruction or a extract_subreg instruction...
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:861
bool hasOneUse(unsigned RegNo) const
hasOneUse - Return true if there is exactly one instruction using the specified register.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:263
LiveInterval & getInterval(unsigned Reg)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:123
bool isSubregToReg() const
Definition: MachineInstr.h:769
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:238
iterator insert(iterator I, T &&Elt)
Definition: SmallVector.h:481
def_iterator def_begin(unsigned RegNo) const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:51
static bool isPhysicalRegister(unsigned Reg)
isPhysicalRegister - Return true if the specified register number is in the physical register namespa...
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
void setReg(unsigned Reg)
Change the register this operand corresponds to.
#define I(x, y, z)
Definition: MD5.cpp:54
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:403
void setSubReg(unsigned subReg)
iterator find(const KeyT &Val)
Definition: DenseMap.h:124
static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg, LiveIntervals *LIS)
isPLainlyKilled - Test if the given register value, which is used by the
char & TwoAddressInstructionPassID
TwoAddressInstruction - This pass reduces two-address instructions to use two operands.
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def...
Definition: SlotIndexes.h:257
iterator begin()
Definition: LiveInterval.h:205
unsigned getReg() const
getReg - Returns the register number.
VNInfo * getNextValue(SlotIndex def, VNInfo::Allocator &VNInfoAllocator)
getNextValue - Create a new value number and return it.
Definition: LiveInterval.h:306
bool isCommutable(QueryType Type=IgnoreBundle) const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged.
Definition: MachineInstr.h:607
static def_iterator def_end()
bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr kills the specified register.
Definition: MachineInstr.h:857
iterator_range< def_instr_iterator > def_instructions(unsigned Reg) const
mop_iterator operands_begin()
Definition: MachineInstr.h:289
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
BasicBlockListType::iterator iterator
#define DEBUG(X)
Definition: Debug.h:92
Primary interface to the complete machine description for the target machine.
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:92
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg)
isTwoAddrUse - Return true if the specified MI uses the specified register as a two-address use...