LLVM  3.7.0
AMDGPUTargetTransformInfo.h
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1 //===-- AMDGPUTargetTransformInfo.h - AMDGPU specific TTI -------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file a TargetTransformInfo::Concept conforming object specific to the
11 /// AMDGPU target machine. It uses the target's detailed information to
12 /// provide more precise answers to certain TTI queries, while letting the
13 /// target independent and default TTI implementations handle the rest.
14 ///
15 //===----------------------------------------------------------------------===//
16 
17 #ifndef LLVM_LIB_TARGET_R600_AMDGPUTARGETTRANSFORMINFO_H
18 #define LLVM_LIB_TARGET_R600_AMDGPUTARGETTRANSFORMINFO_H
19 
20 #include "AMDGPU.h"
21 #include "AMDGPUTargetMachine.h"
25 
26 namespace llvm {
27 
28 class AMDGPUTTIImpl : public BasicTTIImplBase<AMDGPUTTIImpl> {
30  typedef TargetTransformInfo TTI;
31  friend BaseT;
32 
33  const AMDGPUSubtarget *ST;
34  const AMDGPUTargetLowering *TLI;
35 
36  const AMDGPUSubtarget *getST() const { return ST; }
37  const AMDGPUTargetLowering *getTLI() const { return TLI; }
38 
39 public:
41  : BaseT(TM, DL), ST(TM->getSubtargetImpl()),
42  TLI(ST->getTargetLowering()) {}
43 
44  // Provide value semantics. MSVC requires that we spell all of these out.
46  : BaseT(static_cast<const BaseT &>(Arg)), ST(Arg.ST), TLI(Arg.TLI) {}
48  : BaseT(std::move(static_cast<BaseT &>(Arg))), ST(std::move(Arg.ST)),
49  TLI(std::move(Arg.TLI)) {}
50 
51  bool hasBranchDivergence() { return true; }
52 
53  void getUnrollingPreferences(Loop *L, TTI::UnrollingPreferences &UP);
54 
56  assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
57  return ST->hasBCNT(TyWidth) ? TTI::PSK_FastHardware : TTI::PSK_Software;
58  }
59 
60  unsigned getNumberOfRegisters(bool Vector);
61  unsigned getRegisterBitWidth(bool Vector);
62  unsigned getMaxInterleaveFactor(unsigned VF);
63 };
64 
65 } // end namespace llvm
66 
67 #endif
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:104
unsigned getNumberOfRegisters(bool Vector)
void getUnrollingPreferences(Loop *L, TTI::UnrollingPreferences &UP)
AMDGPUTTIImpl(const AMDGPUTargetMachine *TM, const DataLayout &DL)
Base class which can be used to help build a TTI implementation.
Definition: BasicTTIImpl.h:40
unsigned getRegisterBitWidth(bool Vector)
unsigned getMaxInterleaveFactor(unsigned VF)
TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth)
PopcntSupportKind
Flags indicating the kind of support for population count.
This file provides a helper that implements much of the TTI interface in terms of the target-independ...
The AMDGPU TargetMachine interface definition for hw codgen targets.
AMDGPUTTIImpl(AMDGPUTTIImpl &&Arg)
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
AMDGPUTTIImpl(const AMDGPUTTIImpl &Arg)
aarch64 promote const
bool hasBCNT(unsigned Size) const
bool isPowerOf2_32(uint32_t Value)
isPowerOf2_32 - This function returns true if the argument is a power of two > 0. ...
Definition: MathExtras.h:354
This pass exposes codegen information to IR-level passes.
This file describes how to lower LLVM code to machine code.