43 assert (ArgFlags.
isSRet());
57 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
86 "Can't handle non-64 bits locations");
90 unsigned alignment = (LocVT ==
MVT::f128) ? 16 : 8;
94 if (LocVT ==
MVT::i64 && Offset < 6*8)
96 Reg = SP::I0 + Offset/8;
97 else if (LocVT ==
MVT::f64 && Offset < 16*8)
99 Reg = SP::D0 + Offset/8;
100 else if (LocVT ==
MVT::f32 && Offset < 16*8)
102 Reg = SP::F1 + Offset/4;
103 else if (LocVT ==
MVT::f128 && Offset < 16*8)
105 Reg = SP::Q0 + Offset/16;
129 assert(LocVT.
getSizeInBits() == 32 &&
"Can't handle non-32 bits locations");
132 if (LocVT ==
MVT::f32 && Offset < 16*8) {
139 if (LocVT ==
MVT::i32 && Offset < 6*8) {
141 unsigned Reg = SP::I0 + Offset/8;
158 #include "SparcGenCallingConv.inc"
164 assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7 &&
"Unexpected enum");
165 if (Reg >= SP::I0 && Reg <= SP::I7)
166 return Reg - SP::I0 + SP::O0;
177 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
178 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
205 for (
unsigned i = 0; i != RVLocs.
size(); ++i) {
207 assert(VA.
isRegLoc() &&
"Can only return in registers!");
217 unsigned RetAddrOffset = 8;
268 for (
unsigned i = 0; i != RVLocs.
size(); ++i) {
270 assert(VA.
isRegLoc() &&
"Can only return in registers!");
297 if (i+1 < RVLocs.
size() && RVLocs[i+1].getLocReg() == VA.
getLocReg()) {
357 const unsigned StackOffset = 92;
360 for (
unsigned i = 0, e = ArgLocs.size(); i != e; ++i, ++InIdx) {
363 if (Ins[InIdx].
Flags.isSRet()) {
371 false,
false,
false, 0);
393 false,
false,
false, 0);
396 &SP::IntRegsRegClass);
427 if (Offset % 8 == 0) {
434 false,
false,
false, 0);
445 false,
false,
false, 0);
453 false,
false,
false, 0);
470 false,
false,
false, 0);
479 VA.
getValVT(),
false,
false,
false,0);
500 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
502 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs);
503 const MCPhysReg *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6;
504 unsigned ArgOffset = CCInfo.getNextStackOffset();
505 if (NumAllocated == 6)
506 ArgOffset += StackOffset;
509 ArgOffset = 68+4*NumAllocated;
515 std::vector<SDValue> OutChains;
517 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
532 if (!OutChains.empty()) {
533 OutChains.push_back(Chain);
559 const unsigned ArgArea = 128;
561 for (
unsigned i = 0, e = ArgLocs.
size(); i != e; ++i) {
610 Offset += 8 - ValSize;
628 unsigned ArgOffset = CCInfo.getNextStackOffset();
638 for (; ArgOffset < 6*8; ArgOffset += 8) {
639 unsigned VReg = MF.
addLiveIn(SP::I0 + ArgOffset/8, &SP::I64RegsRegClass);
648 if (!OutChains.
empty())
671 dyn_cast<ExternalSymbolSDNode>(Callee)) {
674 const char *CalleeName = E->getSymbol();
708 unsigned ArgsSize = CCInfo.getNextStackOffset();
711 ArgsSize = (ArgsSize+7) & ~7;
717 for (
unsigned i = 0, e = Outs.
size(); i != e; ++i) {
730 Chain = DAG.
getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Align,
744 const unsigned StackOffset = 92;
745 bool hasStructRetAttr =
false;
747 for (
unsigned i = 0, realArgIdx = 0, byvalArgIdx = 0, e = ArgLocs.
size();
751 SDValue Arg = OutVals[realArgIdx];
757 Arg = ByValArgs[byvalArgIdx++];
786 hasStructRetAttr =
true;
796 if (Offset % 8 == 0) {
815 StackPtr = DAG.
getNode(
ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
882 if (!MemOpChains.
empty())
890 for (
unsigned i = 0, e = RegsToPass.
size(); i != e; ++i) {
892 Chain = DAG.
getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag);
896 unsigned SRetArgSize = (hasStructRetAttr)?
getSRetArgSize(DAG, Callee):0;
914 if (hasStructRetAttr)
916 for (
unsigned i = 0, e = RegsToPass.
size(); i != e; ++i)
918 RegsToPass[i].second.getValueType()));
922 const uint32_t *Mask =
926 assert(Mask &&
"Missing call preserved mask for calling convention");
947 for (
unsigned i = 0; i != RVLocs.
size(); ++i) {
949 RVLocs[i].getValVT(), InFlag).
getValue(1);
961 static const char *
const ABICalls[] =
962 {
"_Q_add",
"_Q_sub",
"_Q_mul",
"_Q_div",
964 "_Q_itoq",
"_Q_stoq",
"_Q_dtoq",
"_Q_utoq",
965 "_Q_lltoq",
"_Q_ulltoq",
968 for (
const char *
const *
I = ABICalls; *
I !=
nullptr; ++
I)
969 if (strcmp(CalleeName, *
I) == 0)
981 dyn_cast<ExternalSymbolSDNode>(Callee)) {
984 const char *CalleeName = E->getSymbol();
994 "Callee does not have the StructRet attribute.");
997 Type *ElementTy = Ty->getElementType();
1012 for (
unsigned i = 0, e = ArgLocs.
size(); i != e; ++i) {
1027 unsigned firstReg = (ValTy ==
MVT::f64) ? SP::D0 : SP::Q0;
1028 unsigned argSize = (ValTy ==
MVT::f64) ? 8 : 16;
1029 unsigned Offset = argSize * (VA.
getLocReg() - firstReg);
1030 assert(Offset < 16*8 &&
"Offset out of range, bad register enum?");
1034 unsigned IReg = SP::I0 + Offset/8;
1040 assert(ValTy ==
MVT::f128 &&
"Unexpected type!");
1077 unsigned ArgsSize = std::max(6*8u, CCInfo.getNextStackOffset());
1102 for (
unsigned i = 0, e = ArgLocs.
size(); i != e; ++i) {
1134 unsigned Offset = 8 * (VA.
getLocReg() - SP::I0);
1149 false,
false,
false, 0);
1152 false,
false,
false, 0);
1168 if (i+1 < ArgLocs.
size() && ArgLocs[i+1].isRegLoc() &&
1169 ArgLocs[i+1].getLocReg() == VA.
getLocReg()) {
1197 if (!MemOpChains.
empty())
1205 for (
unsigned i = 0, e = RegsToPass.
size(); i != e; ++i) {
1207 RegsToPass[i].first, RegsToPass[i].second, InGlue);
1227 for (
unsigned i = 0, e = RegsToPass.
size(); i != e; ++i)
1229 RegsToPass[i].second.getValueType()));
1233 const uint32_t *Mask =
1237 assert(Mask &&
"Missing call preserved mask for calling convention");
1266 CLI.
Ins[0].Flags.setInReg();
1268 RVInfo.AnalyzeCallResult(CLI.
Ins, RetCC_Sparc64);
1271 for (
unsigned i = 0; i != RVLocs.
size(); ++i) {
1284 if (!RV.getNode()) {
1285 RV = DAG.
getCopyFromReg(Chain, DL, Reg, RVLocs[i].getLocVT(), InGlue);
1511 if (!Subtarget->
isV9()) {
1606 if (Subtarget->
isV9()) {
1724 unsigned Depth)
const {
1725 APInt KnownZero2, KnownOne2;
1737 KnownOne &= KnownOne2;
1738 KnownZero &= KnownZero2;
1747 if (isa<ConstantSDNode>(RHS) &&
1748 cast<ConstantSDNode>(RHS)->isNullValue() &&
1757 cast<ConstantSDNode>(LHS.
getOperand(0))->isOne() &&
1758 cast<ConstantSDNode>(LHS.
getOperand(1))->isNullValue()) {
1760 SPCC = cast<ConstantSDNode>(LHS.
getOperand(2))->getZExtValue();
1772 GA->getValueType(0),
1773 GA->getOffset(), TF);
1777 CP->getValueType(0),
1779 CP->getOffset(), TF);
1789 ES->getValueType(0), TF);
1797 unsigned HiTF,
unsigned LoTF,
1904 Chain = DAG.
getCopyToReg(Chain, DL, SP::O0, Argument, InFlag);
1917 assert(Mask &&
"Missing call preserved mask for calling convention");
2002 Args.push_back(Entry);
2008 const char *LibFuncName,
2009 unsigned numArgs)
const {
2018 Type *RetTyABI = RetTy;
2027 Entry.
Node = RetPtr;
2032 Args.push_back(Entry);
2036 assert(Op->
getNumOperands() >= numArgs &&
"Not enough operands!");
2037 for (
unsigned i = 0, e = numArgs; i != e; ++i) {
2044 std::pair<SDValue, SDValue> CallInfo =
LowerCallTo(CLI);
2047 if (RetTyABI == RetTy)
2048 return CallInfo.first;
2050 assert (RetTy->
isFP128Ty() &&
"Unexpected return type!");
2052 Chain = CallInfo.second;
2060 false,
false,
false, 8);
2069 const char *LibCall =
nullptr;
2073 case SPCC::FCC_E : LibCall = is64Bit?
"_Qp_feq" :
"_Q_feq";
break;
2074 case SPCC::FCC_NE : LibCall = is64Bit?
"_Qp_fne" :
"_Q_fne";
break;
2075 case SPCC::FCC_L : LibCall = is64Bit?
"_Qp_flt" :
"_Q_flt";
break;
2076 case SPCC::FCC_G : LibCall = is64Bit?
"_Qp_fgt" :
"_Q_fgt";
break;
2077 case SPCC::FCC_LE : LibCall = is64Bit?
"_Qp_fle" :
"_Q_fle";
break;
2078 case SPCC::FCC_GE : LibCall = is64Bit?
"_Qp_fge" :
"_Q_fge";
break;
2086 case SPCC::FCC_UE : LibCall = is64Bit?
"_Qp_cmp" :
"_Q_cmp";
break;
2101 std::pair<SDValue, SDValue> CallInfo =
LowerCallTo(CLI);
2104 SDValue Result = CallInfo.first;
2302 unsigned Opc, SPCC = ~0U;
2339 unsigned Opc, SPCC = ~0U;
2392 const Value *SV = cast<SrcValueSDNode>(Node->
getOperand(2))->getValue();
2406 false,
false,
false,
2417 unsigned SPReg = SP::O6;
2424 unsigned regSpillArea = Subtarget->
is64Bit() ? 128 : 96;
2429 SDValue Ops[2] = { NewVal, Chain };
2448 unsigned FrameReg = SP::I6;
2465 unsigned Offset = (Subtarget->
is64Bit()) ? (stackBias + 112) : 56;
2471 false,
false,
false, 0);
2514 unsigned Offset = (Subtarget->
is64Bit()) ? 120 : 60;
2559 &&
"Unexpected node type");
2570 false,
false,
false, alignment);
2580 false,
false,
false, alignment);
2609 &&
"Unexpected node type");
2634 false,
false, alignment);
2644 false,
false, alignment);
2650 &&
"invalid opcode");
2699 bool hasChain =
false;
2725 SDValue Ops[2] = { Dst, Carry };
2751 SDValue Args[] = { HiLHS, LHS, HiRHS, RHS };
2755 Args, 4, isSigned, dl).first;
2771 assert(MulResult->
use_empty() &&
"Illegally typed node still in use!");
2773 SDValue Ops[2] = { BottomHalf, TopHalf } ;
2779 if (cast<AtomicSDNode>(Op)->getOrdering() <=
Monotonic)
2791 bool isV9 = Subtarget->
isV9();
2853 case SP::SELECT_CC_Int_ICC:
2854 case SP::SELECT_CC_FP_ICC:
2855 case SP::SELECT_CC_DFP_ICC:
2856 case SP::SELECT_CC_QFP_ICC:
2858 case SP::SELECT_CC_Int_FCC:
2859 case SP::SELECT_CC_FP_FCC:
2860 case SP::SELECT_CC_DFP_FCC:
2861 case SP::SELECT_CC_QFP_FCC:
2864 case SP::ATOMIC_LOAD_ADD_32:
2866 case SP::ATOMIC_LOAD_ADD_64:
2868 case SP::ATOMIC_LOAD_SUB_32:
2870 case SP::ATOMIC_LOAD_SUB_64:
2872 case SP::ATOMIC_LOAD_AND_32:
2874 case SP::ATOMIC_LOAD_AND_64:
2876 case SP::ATOMIC_LOAD_OR_32:
2878 case SP::ATOMIC_LOAD_OR_64:
2880 case SP::ATOMIC_LOAD_XOR_32:
2882 case SP::ATOMIC_LOAD_XOR_64:
2884 case SP::ATOMIC_LOAD_NAND_32:
2886 case SP::ATOMIC_LOAD_NAND_64:
2889 case SP::ATOMIC_SWAP_64:
2892 case SP::ATOMIC_LOAD_MAX_32:
2894 case SP::ATOMIC_LOAD_MAX_64:
2896 case SP::ATOMIC_LOAD_MIN_32:
2898 case SP::ATOMIC_LOAD_MIN_64:
2900 case SP::ATOMIC_LOAD_UMAX_32:
2902 case SP::ATOMIC_LOAD_UMAX_64:
2904 case SP::ATOMIC_LOAD_UMIN_32:
2906 case SP::ATOMIC_LOAD_UMIN_64:
2914 unsigned BROpcode)
const {
3003 is64Bit ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
3006 BuildMI(*MBB, MI, DL, TII.
get(is64Bit ? SP::LDXri : SP::LDri), Val0Reg)
3007 .addReg(AddrReg).
addImm(0);
3016 MF->
insert(MFI, LoopMBB);
3017 MF->
insert(MFI, DoneMBB);
3034 .addReg(Val0Reg).
addMBB(MBB)
3041 BuildMI(LoopMBB, DL, TII.
get(Opcode), UpdReg)
3043 }
else if (Opcode) {
3044 BuildMI(LoopMBB, DL, TII.
get(Opcode), UpdReg)
3045 .addReg(ValReg).
addReg(Rs2Reg);
3048 if (MI->getOpcode() == SP::ATOMIC_LOAD_NAND_32 ||
3049 MI->getOpcode() == SP::ATOMIC_LOAD_NAND_64) {
3050 unsigned TmpReg = UpdReg;
3052 BuildMI(LoopMBB, DL, TII.
get(SP::XORri), UpdReg).addReg(TmpReg).
addImm(-1);
3055 BuildMI(LoopMBB, DL, TII.
get(is64Bit ? SP::CASXrr : SP::CASrr), DestReg)
3057 .
setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
3059 BuildMI(LoopMBB, DL, TII.
get(is64Bit ? SP::BPXCC : SP::BCOND))
3074 if (Constraint.
size() == 1) {
3075 switch (Constraint[0]) {
3088 const char *constraint)
const {
3093 if (!CallOperandVal)
3097 switch (*constraint) {
3103 if (isInt<13>(
C->getSExtValue()))
3115 std::string &Constraint,
3116 std::vector<SDValue> &Ops,
3121 if (Constraint.length() > 1)
3124 char ConstraintLetter = Constraint[0];
3125 switch (ConstraintLetter) {
3129 if (isInt<13>(
C->getSExtValue())) {
3139 Ops.push_back(Result);
3145 std::pair<unsigned, const TargetRegisterClass *>
3149 if (Constraint.
size() == 1) {
3150 switch (Constraint[0]) {
3152 return std::make_pair(0U, &SP::IntRegsRegClass);
3154 }
else if (!Constraint.
empty() && Constraint.
size() <= 5
3155 && Constraint[0] ==
'{' && *(Constraint.
end()-1) ==
'}') {
3164 uint64_t intVal = 0;
3165 if (
name.substr(0, 1).equals(
"r")
3166 && !
name.substr(1).getAsInteger(10, intVal) && intVal <= 31) {
3167 const char regTypes[] = {
'g',
'o',
'l',
'i' };
3168 char regType = regTypes[intVal/8];
3169 char regIdx =
'0' + (intVal % 8);
3170 char tmp[] = {
'{', regType, regIdx,
'}', 0 };
3171 std::string newConstraint = std::string(tmp);
3196 llvm_unreachable(
"Do not know how to custom type legalize this operation!");
void setFrameAddressIsTaken(bool T)
static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
bool use_empty() const
Return true if there are no uses of this node.
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...
void push_back(const T &Elt)
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
A parsed version of the target data layout string in and methods for querying it. ...
CallLoweringInfo & setCallee(CallingConv::ID CC, Type *ResultType, SDValue Target, ArgListTy &&ArgsList, unsigned FixedArgs=-1)
SDValue getValue(unsigned R) const
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant, which is required to be operand #1) half of the integer or float value specified as operand #0.
LLVMContext * getContext() const
LLVM Argument representation.
SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N)
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, SDLoc DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd)...
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
SparcTargetLowering(TargetMachine &TM, const SparcSubtarget &STI)
static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC)
IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC condition.
size_t size() const
size - Get the string size.
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
BR_CC - Conditional branch.
LocInfo getLocInfo() const
unsigned getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const
static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI)
SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF, SelectionDAG &DAG) const
static SDValue LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG)
A Module instance is used to store all the information related to an LLVM module. ...
const TargetMachine & getTargetMachine() const
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
CallLoweringInfo & setDebugLoc(SDLoc dl)
SDValue getMergeValues(ArrayRef< SDValue > Ops, SDLoc dl)
Create a MERGE_VALUES node from the given operands.
Carry-setting nodes for multiple precision addition and subtraction.
unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain...
void computeKnownBits(SDValue Op, APInt &KnownZero, APInt &KnownOne, unsigned Depth=0) const
Determine which bits of Op are known to be either zero or one and return them in the KnownZero/KnownO...
const GlobalValue * getGlobal() const
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
SDValue LowerCall_32(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Type * getTypeForEVT(LLVMContext &Context) const
getTypeForEVT - This method returns an LLVM type corresponding to the specified EVT.
unsigned getSizeInBits() const
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
unsigned getByValSize() const
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
unsigned getNumOperands() const
Return the number of values used by this operation.
static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *fromMBB)
transferSuccessorsAndUpdatePHIs - Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor blocks which refer to fromMBB to refer to this.
const SDValue & getOperand(unsigned Num) const
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags=0)
MachineBasicBlock * expandSelectCC(MachineInstr *MI, MachineBasicBlock *BB, unsigned BROpcode) const
Value * CallOperandVal
If this is the result output operand or a clobber, this is null, otherwise it is the incoming operand...
const SparcInstrInfo * getInstrInfo() const override
unsigned getValNo() const
const SDValue & getBasePtr() const
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag=true)
Reports a serious error, calling any installed error handler.
SDValue getExternalSymbol(const char *Sym, EVT VT)
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
SDValue getMemcpy(SDValue Chain, SDLoc dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
static MachinePointerInfo getFixedStack(int FI, int64_t offset=0)
getFixedStack - Return a MachinePointerInfo record that refers to the the specified FrameIndex...
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
bool isVector() const
isVector - Return true if this is a vector value type.
SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
SDValue LowerCall_64(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const
static SDValue LowerF128_FPROUND(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI)
static SDValue LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9)
const uint32_t * getRTCallPreservedMask(CallingConv::ID CC) const
static SDValue LowerF128_FPEXTEND(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI)
const HexagonInstrInfo * TII
static void fixupVariableFloatArgs(SmallVectorImpl< CCValAssign > &ArgLocs, ArrayRef< ISD::OutputArg > Outs)
Shift and rotation operations.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
MachineFunction & getMachineFunction() const
std::pair< SDValue, SDValue > makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops, unsigned NumOps, bool isSigned, SDLoc dl, bool doesNotReturn=false, bool isReturnValueUsed=true) const
Returns a pair of (return value, chain).
CallLoweringInfo & setChain(SDValue InChain)
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
SDValue getTargetGlobalAddress(const GlobalValue *GV, SDLoc DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
void addLoc(const CCValAssign &V)
const TargetRegisterClass * getRegClass(unsigned Reg) const
getRegClass - Return the register class of the specified virtual register.
void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth=0) const override
computeKnownBitsForTargetNode - Determine which of the bits specified in Mask are known to be either ...
Reg
All possible values of the reg field in the ModR/M byte.
static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, const SparcSubtarget *Subtarget)
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) For double-word atomic operations: ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi) ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi) These correspond to the atomicrmw instruction.
Number of individual test Apply this number of consecutive mutations to each input exit after the first new interesting input is found the minimized corpus is saved into the first input directory Number of jobs to run If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
bool hasFnAttr(Attribute::AttrKind A) const
Return true if this function has the given attribute.
SDValue LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args, SDValue Arg, SDLoc DL, SelectionDAG &DAG) const
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG...
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
SmallVector< ISD::InputArg, 32 > Ins
STACKSAVE - STACKSAVE has one operand, an input chain.
static void LookThroughSetCC(SDValue &LHS, SDValue &RHS, ISD::CondCode CC, unsigned &SPCC)
SDValue getCALLSEQ_START(SDValue Chain, SDValue Op, SDLoc DL)
Return a new CALLSEQ_START node, which always must have a glue result (to ensure it's not CSE'd)...
unsigned getLocReg() const
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
SDValue getRegisterMask(const uint32_t *RegMask)
bool hasStructRetAttr() const
Determine if the function returns a structure through first pointer argument.
static SDValue LowerUMULO_SMULO(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI)
const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const
void setSRetReturnReg(unsigned Reg)
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override
This contains information for each constraint that we are lowering.
Simple integer binary arithmetic operators.
SmallVector< ISD::OutputArg, 32 > Outs
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
const SDValue & getBasePtr() const
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
static SDValue LowerF64Op(SDValue Op, SelectionDAG &DAG, unsigned opcode)
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
const DataLayout & getDataLayout() const
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
PointerType - Class to represent pointers.
const BasicBlock * getBasicBlock() const
getBasicBlock - Return the LLVM basic block that this instance corresponded to originally.
UNDEF - An undefined node.
This class is used to represent ISD::STORE nodes.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
Flag
These should be considered private to the implementation of the MCInstrDesc class.
TargetInstrInfo - Interface to description of machine instruction set.
Function * getFunction(StringRef Name) const
Look up the specified function in the module symbol table.
SDNode * getNode() const
get the SDNode which holds the desired result
IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
bundle_iterator< MachineInstr, instr_iterator > iterator
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
int getVarArgsFrameOffset() const
const MachineInstrBuilder & setMemRefs(MachineInstr::mmo_iterator b, MachineInstr::mmo_iterator e) const
CodeModel::Model getCodeModel() const
Returns the code model.
MVT - Machine Value Type.
static bool CC_Sparc64_Half(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
LLVM Basic Block Representation.
const SDValue & getOperand(unsigned i) const
The instances of the Type class are immutable: once they are created, they are never changed...
This is an important class for using LLVM in a threaded context.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
Simple binary floating point operators.
static bool CC_Sparc_Assign_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE...
static bool is64Bit(const char *name)
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector.
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
const MachineOperand & getOperand(unsigned i) const
Carry-using nodes for multiple precision addition and subtraction.
static bool hasReturnsTwiceAttr(SelectionDAG &DAG, SDValue Callee, ImmutableCallSite *CS)
INSERT_SUBREG - This instruction takes three operands: a register that has subregisters, a register providing an insert value, and a subregister index.
static mvt_range fp_valuetypes()
static SDValue LowerF128Store(SDValue Op, SelectionDAG &DAG)
unsigned getSRetReturnReg() const
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
static Type * getVoidTy(LLVMContext &C)
SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT)
SDValue getTargetConstant(uint64_t Val, SDLoc DL, EVT VT, bool isOpaque=false)
unsigned getBitWidth() const
Return the number of bits in the APInt.
static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
unsigned getOpcode() const
TRAP - Trapping instruction.
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
static SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool Immutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
SDValue LowerFormalArguments_64(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const
static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
const SDValue & getValue() const
SDValue getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes())
Bit counting operators with an undefined result for zero inputs.
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo...
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
EVT - Extended Value Type.
bool isFP128Ty() const
isFP128Ty - Return true if this is 'fp128'.
void setVarArgsFrameOffset(int Offset)
std::vector< ArgListEntry > ArgListTy
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
MachinePointerInfo - This class contains a discriminated union of information about pointers in memor...
const SDValue & getRoot() const
Return the root tag of the SelectionDAG.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
SDValue CreateStackTemporary(EVT VT, unsigned minAlign=1)
Create a stack temporary, suitable for holding the specified value type.
const SparcRegisterInfo * getRegisterInfo() const override
const MachinePointerInfo & getPointerInfo() const
unsigned getByValAlign() const
const SDValue & getOffset() const
SDValue getTargetConstantPool(const Constant *C, EVT VT, unsigned Align=0, int Offset=0, unsigned char TargetFlags=0)
TokenFactor - This node takes multiple tokens as input and produces a single token result...
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target...
EXTRACT_SUBREG - This instruction takes two operands: a register that has subregisters, and a subregister index.
CCState - This class holds information needed while lowering arguments and return values...
static PointerType * getUnqual(Type *ElementType)
PointerType::getUnqual - This constructs a pointer to an object of the specified type in the generic ...
This is the shared class of boolean and integer constants.
static bool isFP128ABICall(const char *CalleeName)
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - Return the ISD::SETCC ValueType
const char * getLibcallName(RTLIB::Libcall Call) const
Get the libcall routine name for the specified libcall.
SDValue LowerFormalArguments_32(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const
LowerFormalArguments32 - V8 uses a very simple ABI, where all values are passed in either one or two ...
uint64_t getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
void setExceptionPointerRegister(unsigned R)
If set to a physical register, this sets the register that receives the exception address on entry to...
const DataLayout * getDataLayout() const
Deprecated in 3.7, will be removed in 3.8.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
SDValue getTargetInsertSubreg(int SRIdx, SDLoc DL, EVT VT, SDValue Operand, SDValue Subreg)
A convenience function for creating TargetInstrInfo::INSERT_SUBREG nodes.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Module.h This file contains the declarations for the Module class.
CCValAssign - Represent assignment of one arg/retval to a location.
BRCOND - Conditional branch.
const SDValue & getChain() const
Byte Swap and Counting operators.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Represents one node in the SelectionDAG.
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG)
SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const
static mvt_range integer_valuetypes()
Class for arbitrary precision integers.
void setExceptionSelectorRegister(unsigned R)
If set to a physical register, this sets the register that receives the exception typeid on entry to ...
static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG)
Select(COND, TRUEVAL, FALSEVAL).
void setMinFunctionAlignment(unsigned Align)
Set the target's minimum function alignment (in log2(bytes))
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
Return the register class that should be used for the specified value type.
static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
ZERO_EXTEND - Used for integer types, zeroing the new bits.
static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC)
FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC FCC condition.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
ANY_EXTEND - Used for integer types. The high bits are undefined.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, SDLoc dl, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array...
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
uint64_t RoundUpToAlignment(uint64_t Value, uint64_t Align)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
BR_JT - Jumptable branch.
Representation of each machine instruction.
static MachinePointerInfo getGOT()
getGOT - Return a MachinePointerInfo record that refers to a GOT entry.
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the source.
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned char TargetFlags=0)
uint64_t getConstantOperandVal(unsigned i) const
SmallVector< SDValue, 32 > OutVals
Bitwise operators - logical and, logical or, logical xor.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static IntegerType * getInt32Ty(LLVMContext &C)
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
SDValue LowerReturn_64(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, SDLoc DL, SelectionDAG &DAG) const
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
static CCValAssign getCustomMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
ImmutableCallSite - establish a view to a call site for examination.
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
MachineBasicBlock * expandAtomicRMW(MachineInstr *MI, MachineBasicBlock *BB, unsigned Opcode, unsigned CondCode=0) const
void setStackPointerRegisterToSaveRestore(unsigned R)
If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
SDValue LowerReturn_32(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, SDLoc DL, SelectionDAG &DAG) const
const SDValue & getOffset() const
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
static SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
SDValue LowerF128Compare(SDValue LHS, SDValue RHS, unsigned &SPCC, SDLoc DL, SelectionDAG &DAG) const
MachineSDNode * getMachineNode(unsigned Opcode, SDLoc dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s), MachineInstr opcode, and operands.
static CCValAssign getMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
FSINCOS - Compute both fsin and fcos as a single operation.
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSS, const AllocaInst *Alloca=nullptr)
Create a new statically sized stack object, returning a nonnegative identifier to represent it...
EVT getValueType() const
Return the ValueType of the referenced return value.
SDValue getConstant(uint64_t Val, SDLoc DL, EVT VT, bool isTarget=false, bool isOpaque=false)
TLSModel::Model getTLSModel(const GlobalValue *GV) const
Returns the TLS model which should be used for the given global variable.
unsigned getReg() const
getReg - Returns the register number.
Function can return twice.
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
void insert(iterator MBBI, MachineBasicBlock *MBB)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
void setReturnAddressIsTaken(bool s)
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
SDValue getTargetExtractSubreg(int SRIdx, SDLoc DL, EVT VT, SDValue Operand)
A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG nodes.
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array...
Module * getParent()
Get the module that this global value is contained inside of...
LLVM Value Representation.
FMA - Perform a * b + c with no intermediate rounding step.
SDValue getRegister(unsigned Reg, EVT VT)
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
void setInsertFencesForAtomic(bool fence)
Set if the DAG builder should automatically insert fences and reduce the order of atomic memory opera...
SDValue getValueType(EVT)
static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
BasicBlockListType::iterator iterator
Primary interface to the complete machine description for the target machine.
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
C - The default llvm calling convention, compatible with C.
StringRef - Represent a constant reference to a string, i.e.
static SDValue getFRAMEADDR(uint64_t depth, SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
SetCC operator - This evaluates to a true value iff the condition is true.
SDValue getSetCC(SDLoc DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
int64_t getStackPointerBias() const
The 64-bit ABI uses biased stack and frame pointers, so the stack frame of the current function is th...
unsigned getLocMemOffset() const
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val) This corresponds to "store atomic" instruction.
TRUNCATE - Completely drop the high bits.
unsigned getAlignment() const
unsigned AllocateReg(unsigned Reg)
AllocateReg - Attempt to allocate one register.
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
Examine constraint string and operand type and determine a weight value.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2, FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR - Perform various unary floating point operations.
SDValue LowerF128Op(SDValue Op, SelectionDAG &DAG, const char *LibFuncName, unsigned numArgs) const
unsigned AllocateStack(unsigned Size, unsigned Align)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
void addSuccessor(MachineBasicBlock *succ, uint32_t weight=0)
addSuccessor - Add succ as a successor of this MachineBasicBlock.
Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) This corresponds to "load atomic" instruction.
static unsigned toCallerWindow(unsigned Reg)
EVT changeVectorElementTypeToInteger() const
changeVectorElementTypeToInteger - Return a vector with the same number of elements as this vector...
static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG)
SDValue getIntPtrConstant(uint64_t Val, SDLoc DL, bool isTarget=false)
bool empty() const
empty - Check if the string is empty.
static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG)
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
This class is used to represent ISD::LOAD nodes.
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary...