|
LLVM
3.7.0
|
Classes | |
| struct | IsaVersion |
Enumerations | |
| enum | TargetIndex { TI_CONSTDATA_START, TI_SCRATCH_RSRC_DWORD0, TI_SCRATCH_RSRC_DWORD1, TI_SCRATCH_RSRC_DWORD2, TI_SCRATCH_RSRC_DWORD3 } |
| enum | Fixups { fixup_si_sopp_br = FirstTargetFixupKind, fixup_si_rodata, fixup_si_end_of_text, LastTargetFixupKind, NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind } |
| enum | OperandType { OPERAND_REG_IMM32 = llvm::MCOI::OPERAND_FIRST_TARGET, OPERAND_REG_INLINE_C } |
Functions | |
| static int | getMCOpcode (uint16_t Opcode, unsigned Gen) |
| int16_t | getNamedOperandIdx (uint16_t Opcode, uint16_t NamedIndex) |
| int | getLDSNoRetOp (uint16_t Opcode) |
| int | getVOPe64 (uint16_t Opcode) |
| int | getVOPe32 (uint16_t Opcode) |
| int | getCommuteRev (uint16_t Opcode) |
| int | getCommuteOrig (uint16_t Opcode) |
| int | getAddr64Inst (uint16_t Opcode) |
| int | getAtomicRetOp (uint16_t Opcode) |
| int | getAtomicNoRetOp (uint16_t Opcode) |
| IsaVersion | getIsaVersion (const FeatureBitset &Features) |
| void | initDefaultAMDKernelCodeT (amd_kernel_code_t &Header, const FeatureBitset &Features) |
Variables | |
| const uint64_t | RSRC_DATA_FORMAT = 0xf00000000000LL |
| const uint64_t | RSRC_TID_ENABLE = 1LL << 55 |
| enum llvm::AMDGPU::Fixups |
Definition at line 17 of file AMDGPUFixupKinds.h.
| Enumerator | |
|---|---|
| OPERAND_REG_IMM32 |
Operand with register or 32-bit immediate. |
| OPERAND_REG_INLINE_C |
Operand with register or inline constant. |
Definition at line 46 of file SIDefines.h.
| int llvm::AMDGPU::getAddr64Inst | ( | uint16_t | Opcode | ) |
Referenced by llvm::SIInstrInfo::legalizeOperands().
| int llvm::AMDGPU::getAtomicNoRetOp | ( | uint16_t | Opcode | ) |
Referenced by llvm::SITargetLowering::AdjustInstrPostInstrSelection().
| int llvm::AMDGPU::getAtomicRetOp | ( | uint16_t | Opcode | ) |
| int llvm::AMDGPU::getCommuteOrig | ( | uint16_t | Opcode | ) |
Referenced by llvm::SIInstrInfo::commuteOpcode().
| int llvm::AMDGPU::getCommuteRev | ( | uint16_t | Opcode | ) |
Referenced by llvm::SIInstrInfo::commuteOpcode().
| IsaVersion llvm::AMDGPU::getIsaVersion | ( | const FeatureBitset & | Features | ) |
Definition at line 19 of file AMDGPUBaseInfo.cpp.
Referenced by llvm::AMDGPUSubtarget::getIsaVersion(), and initDefaultAMDKernelCodeT().
| int llvm::AMDGPU::getLDSNoRetOp | ( | uint16_t | Opcode | ) |
Referenced by llvm::R600TargetLowering::EmitInstrWithCustomInserter().
Definition at line 334 of file AMDGPUInstrInfo.cpp.
Referenced by llvm::AMDGPUInstrInfo::pseudoToMCOpcode().
| int16_t llvm::AMDGPU::getNamedOperandIdx | ( | uint16_t | Opcode, |
| uint16_t | NamedIndex | ||
| ) |
Referenced by llvm::SIInstrInfo::areLoadsFromSameBasePtr(), llvm::SIInstrInfo::commuteInstruction(), llvm::AMDGPUInstrInfo::expandPostRAPseudo(), llvm::SIInstrInfo::findCommutedOpIndices(), llvm::SIInstrInfo::FoldImmediate(), foldImmediates(), llvm::SIInstrInfo::getMemOpBaseRegImmOfs(), llvm::SIInstrInfo::getNamedOperand(), llvm::R600InstrInfo::getOperandIdx(), llvm::SIInstrInfo::hasModifiers(), llvm::SIInstrInfo::legalizeOperands(), nodesHaveSameOperandValue(), removeModOperands(), tryAddToFoldList(), and llvm::SIInstrInfo::verifyInstruction().
| int llvm::AMDGPU::getVOPe32 | ( | uint16_t | Opcode | ) |
Referenced by llvm::SIInstrInfo::hasVALU32BitEncoding().
| int llvm::AMDGPU::getVOPe64 | ( | uint16_t | Opcode | ) |
| void llvm::AMDGPU::initDefaultAMDKernelCodeT | ( | amd_kernel_code_t & | Header, |
| const FeatureBitset & | Features | ||
| ) |
Definition at line 36 of file AMDGPUBaseInfo.cpp.
References amd_kernel_code_s::amd_kernel_code_version_major, amd_kernel_code_s::amd_kernel_code_version_minor, amd_kernel_code_s::amd_machine_kind, amd_kernel_code_s::amd_machine_version_major, amd_kernel_code_s::amd_machine_version_minor, amd_kernel_code_s::amd_machine_version_stepping, getIsaVersion(), amd_kernel_code_s::group_segment_alignment, amd_kernel_code_s::kernarg_segment_alignment, amd_kernel_code_s::kernel_code_entry_byte_offset, llvm::AMDGPU::IsaVersion::Major, llvm::AMDGPU::IsaVersion::Minor, amd_kernel_code_s::private_segment_alignment, llvm::AMDGPU::IsaVersion::Stepping, and amd_kernel_code_s::wavefront_size.
| const uint64_t llvm::AMDGPU::RSRC_DATA_FORMAT = 0xf00000000000LL |
Definition at line 369 of file SIInstrInfo.h.
Referenced by llvm::SIInstrInfo::getDefaultRsrcDataFormat().
| const uint64_t llvm::AMDGPU::RSRC_TID_ENABLE = 1LL << 55 |
Definition at line 370 of file SIInstrInfo.h.
Referenced by llvm::SITargetLowering::buildScratchRSRC().
1.8.6