46 const char *getPassName()
const override {
47 return "SI prepare scratch registers";
57 return new SIPrepareScratchRegs();
76 unsigned ScratchPtrPreloadReg =
78 unsigned ScratchOffsetPreloadReg =
81 if (!Entry->
isLiveIn(ScratchPtrPreloadReg))
84 if (!Entry->
isLiveIn(ScratchOffsetPreloadReg))
85 Entry->
addLiveIn(ScratchOffsetPreloadReg);
88 unsigned ScratchOffsetReg =
90 int ScratchOffsetFI = -1;
92 if (ScratchOffsetReg != AMDGPU::NoRegister) {
95 BuildMI(*Entry, I, DL, TII->
get(AMDGPU::S_MOV_B32), ScratchOffsetReg)
96 .addReg(ScratchOffsetPreloadReg);
100 BuildMI(*Entry, I, DL, TII->
get(AMDGPU::SI_SPILL_S32_SAVE))
101 .addReg(ScratchOffsetPreloadReg)
121 if (!MBB.
isLiveIn(ScratchOffsetReg) &&
122 ScratchOffsetReg != AMDGPU::NoRegister)
135 unsigned ScratchRsrcReg =
141 unsigned Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0);
142 unsigned Rsrc1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1);
143 unsigned Rsrc2 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2);
144 unsigned Rsrc3 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3);
146 BuildMI(MBB, I, DL, TII->
get(AMDGPU::S_MOV_B32), Rsrc0)
147 .addExternalSymbol(
"SCRATCH_RSRC_DWORD0")
150 BuildMI(MBB, I, DL, TII->
get(AMDGPU::S_MOV_B32), Rsrc1)
151 .addExternalSymbol(
"SCRATCH_RSRC_DWORD1")
154 BuildMI(MBB, I, DL, TII->
get(AMDGPU::S_MOV_B32), Rsrc2)
155 .addImm(Rsrc & 0xffffffff)
158 BuildMI(MBB, I, DL, TII->
get(AMDGPU::S_MOV_B32), Rsrc3)
163 if (ScratchOffsetReg == AMDGPU::NoRegister) {
165 BuildMI(MBB, I, DL, TII->
get(AMDGPU::SI_SPILL_S32_RESTORE),
167 .addFrameIndex(ScratchOffsetFI)
170 }
else if (!MBB.
isLiveIn(ScratchOffsetReg)) {
174 if (ScratchRsrcReg == AMDGPU::NoRegister ||
175 ScratchOffsetReg == AMDGPU::NoRegister) {
177 Ctx.
emitError(
"ran out of SGPRs for spilling VGPRs");
178 ScratchRsrcReg = AMDGPU::SGPR0;
179 ScratchOffsetReg = AMDGPU::SGPR0;
void setPhysRegUsed(unsigned Reg)
setPhysRegUsed - Mark the specified register used in this function.
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
AMDGPU specific subclass of TargetSubtarget.
bool hasSpilledVGPRs() const
void setIsUndef(bool Val=true)
void addLiveIn(unsigned Reg)
Adds the specified register as a live in.
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false)
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
void emitError(unsigned LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
void forward()
Move the internal MBB iterator and update register states.
const uint64_t RSRC_DATA_FORMAT
void enterBasicBlock(MachineBasicBlock *mbb)
Start tracking liveness from the begin of the specific basic block.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
bundle_iterator< MachineInstr, instr_iterator > iterator
This is an important class for using LLVM in a threaded context.
const MachineOperand & getOperand(unsigned i) const
unsigned getPreloadedValue(const MachineFunction &MF, enum PreloadedValue Value) const
Returns the physical register that Value is stored in.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
FunctionPass class - This class is used to implement most global optimizations.
unsigned findUnusedRegister(const MachineRegisterInfo &MRI, const TargetRegisterClass *RC) const
Returns a register that is not used at any point in the function.
FunctionPass * createSIPrepareScratchRegs()
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
int CreateSpillStackObject(uint64_t Size, unsigned Alignment)
Create a new statically sized stack object that represents a spill slot, returning a nonnegative iden...
void setIsKill(bool Val=true)
const uint64_t RSRC_TID_ENABLE
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const MachineInstrBuilder & addFrameIndex(int Idx) const
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)
Representation of each machine instruction.
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
Interface definition for SIInstrInfo.
bool isLiveIn(unsigned Reg) const
isLiveIn - Return true if the specified register is in the live in set.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
void setReg(unsigned Reg)
Change the register this operand corresponds to.
virtual const TargetInstrInfo * getInstrInfo() const
BasicBlockListType::iterator iterator
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
unsigned scavengeRegister(const TargetRegisterClass *RegClass, MachineBasicBlock::iterator I, int SPAdj)
Make a register of the specific register class available and do the appropriate bookkeeping.