14 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINESCHEDULER_H
15 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINESCHEDULER_H
51 std::vector<SUnit*> Packet;
54 unsigned TotalPackets;
58 : SchedModel(SM), TotalPackets(0) {
63 assert(ResourcesModel &&
"Unimplemented CreateTargetScheduleState.");
71 delete ResourcesModel;
97 std::unique_ptr<MachineSchedStrategy> S)
113 struct SchedCandidate {
123 SchedCandidate(): SU(
nullptr), SCost(0) {}
127 NoCand, NodeOrder, SingleExcess, SingleCritical, SingleMax, MultiPressure,
133 struct VLIWSchedBoundary {
148 unsigned MinReadyCycle;
151 unsigned MaxMinLatency;
156 DAG(
nullptr), SchedModel(
nullptr), Available(ID, Name+
".A"),
158 CheckPending(
false), HazardRec(
nullptr), ResourceModel(
nullptr),
159 CurrCycle(0), IssueCount(0),
160 MinReadyCycle(UINT_MAX), MaxMinLatency(0) {}
162 ~VLIWSchedBoundary() {
163 delete ResourceModel;
176 bool checkHazard(
SUnit *SU);
178 void releaseNode(
SUnit *SU,
unsigned ReadyCycle);
182 void bumpNode(
SUnit *SU);
184 void releasePending();
186 void removeReady(
SUnit *SU);
188 SUnit *pickOnlyChoice();
195 VLIWSchedBoundary Top;
196 VLIWSchedBoundary Bot;
207 : DAG(nullptr), SchedModel(nullptr), Top(
TopQID,
"TopQ"),
221 return Top.ResourceModel->getTotalPackets() +
222 Bot.ResourceModel->getTotalPackets();
229 SUnit *SU, SchedCandidate &Candidate,
234 SchedCandidate &Candidate);
VLIWResourceModel(const TargetSubtargetInfo &STI, const TargetSchedModel *SM)
void schedule() override
Schedule - This is called back from ScheduleDAGInstrs::Run() when it's time to do some work...
Extend the standard ScheduleDAGMI to provide more context and override the top-level schedule() drive...
int SchedulingCost(ReadyQueue &Q, SUnit *SU, SchedCandidate &Candidate, RegPressureDelta &Delta, bool verbose)
Single point to compute overall scheduling cost.
CandResult pickNodeFromQueue(ReadyQueue &Q, const RegPressureTracker &RPTracker, SchedCandidate &Candidate)
Pick the best candidate from the top queue.
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
SUnit * pickNodeBidrectional(bool &IsTopNode)
Pick the best candidate node from either the top or bottom queue.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Provide an instruction scheduling machine model to CodeGen passes.
SUnit * pickNode(bool &IsTopNode) override
Pick the best node to balance the schedule. Implements MachineSchedStrategy.
VLIWMachineScheduler(MachineSchedContext *C, std::unique_ptr< MachineSchedStrategy > S)
void releaseTopNode(SUnit *SU) override
When all predecessor dependencies have been resolved, free this node for top-down scheduling...
virtual DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &) const
Create machine specific model for scheduling.
initializer< Ty > init(const Ty &Val)
Helpers for implementing custom MachineSchedStrategy classes.
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
Track the current register pressure at some position in the instruction stream, and remember the high...
bool isResourceAvailable(SUnit *SU)
Check if scheduling of this SU is possible in the current packet.
void traceCandidate(const char *Label, const ReadyQueue &Q, SUnit *SU, PressureChange P=PressureChange())
void schedNode(SUnit *SU, bool IsTopNode) override
Update the scheduler's state after scheduling a node.
ConvergingVLIWScheduler shrinks the unscheduled zone using heuristics to balance the schedule...
unsigned getTotalPackets() const
TargetSubtargetInfo - Generic base class for all target subtargets.
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
MachineSchedStrategy - Interface to the scheduling algorithm used by ScheduleDAGMI.
Capture a change in pressure for a single pressure set.
void postprocessDAG()
Perform platform-specific DAG postprocessing.
bool reserveResources(SUnit *SU)
Keep track of available resources.
void releaseBottomNode(SUnit *SU) override
When all successor dependencies have been resolved, free this node for bottom-up scheduling.
Store the effects of a change in pressure on things that MI scheduler cares about.
virtual const TargetInstrInfo * getInstrInfo() const
unsigned getIssueWidth() const
Maximum number of micro-ops that may be scheduled per cycle.
ConvergingVLIWScheduler()
SUnit - Scheduling unit. This is a node in the scheduling DAG.
void initialize(ScheduleDAGMI *dag) override
Initialize the strategy after building the DAG for a new region.