LLVM  3.7.0
AArch64TargetMachine.cpp
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1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "AArch64.h"
14 #include "AArch64TargetMachine.h"
17 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/IR/Function.h"
24 #include "llvm/Transforms/Scalar.h"
25 using namespace llvm;
26 
27 static cl::opt<bool>
28 EnableCCMP("aarch64-ccmp", cl::desc("Enable the CCMP formation pass"),
29  cl::init(true), cl::Hidden);
30 
31 static cl::opt<bool> EnableMCR("aarch64-mcr",
32  cl::desc("Enable the machine combiner pass"),
33  cl::init(true), cl::Hidden);
34 
35 static cl::opt<bool>
36 EnableStPairSuppress("aarch64-stp-suppress", cl::desc("Suppress STP for AArch64"),
37  cl::init(true), cl::Hidden);
38 
39 static cl::opt<bool>
40 EnableAdvSIMDScalar("aarch64-simd-scalar", cl::desc("Enable use of AdvSIMD scalar"
41  " integer instructions"), cl::init(false), cl::Hidden);
42 
43 static cl::opt<bool>
44 EnablePromoteConstant("aarch64-promote-const", cl::desc("Enable the promote "
45  "constant pass"), cl::init(true), cl::Hidden);
46 
47 static cl::opt<bool>
48 EnableCollectLOH("aarch64-collect-loh", cl::desc("Enable the pass that emits the"
49  " linker optimization hints (LOH)"), cl::init(true),
50  cl::Hidden);
51 
52 static cl::opt<bool>
53 EnableDeadRegisterElimination("aarch64-dead-def-elimination", cl::Hidden,
54  cl::desc("Enable the pass that removes dead"
55  " definitons and replaces stores to"
56  " them with stores to the zero"
57  " register"),
58  cl::init(true));
59 
60 static cl::opt<bool>
61 EnableLoadStoreOpt("aarch64-load-store-opt", cl::desc("Enable the load/store pair"
62  " optimization pass"), cl::init(true), cl::Hidden);
63 
64 static cl::opt<bool>
65 EnableAtomicTidy("aarch64-atomic-cfg-tidy", cl::Hidden,
66  cl::desc("Run SimplifyCFG after expanding atomic operations"
67  " to make use of cmpxchg flow-based information"),
68  cl::init(true));
69 
70 static cl::opt<bool>
71 EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
72  cl::desc("Run early if-conversion"),
73  cl::init(true));
74 
75 static cl::opt<bool>
76 EnableCondOpt("aarch64-condopt",
77  cl::desc("Enable the condition optimizer pass"),
78  cl::init(true), cl::Hidden);
79 
80 static cl::opt<bool>
81 EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden,
82  cl::desc("Work around Cortex-A53 erratum 835769"),
83  cl::init(false));
84 
85 static cl::opt<bool>
86 EnableGEPOpt("aarch64-gep-opt", cl::Hidden,
87  cl::desc("Enable optimizations on complex GEPs"),
88  cl::init(false));
89 
90 // FIXME: Unify control over GlobalMerge.
92 EnableGlobalMerge("aarch64-global-merge", cl::Hidden,
93  cl::desc("Enable the global merge pass"));
94 
95 extern "C" void LLVMInitializeAArch64Target() {
96  // Register the target.
100 }
101 
102 //===----------------------------------------------------------------------===//
103 // AArch64 Lowering public interface.
104 //===----------------------------------------------------------------------===//
105 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
106  if (TT.isOSBinFormatMachO())
107  return make_unique<AArch64_MachoTargetObjectFile>();
108 
109  return make_unique<AArch64_ELFTargetObjectFile>();
110 }
111 
112 // Helper function to build a DataLayout string
113 static std::string computeDataLayout(const Triple &TT, bool LittleEndian) {
114  if (TT.isOSBinFormatMachO())
115  return "e-m:o-i64:64-i128:128-n32:64-S128";
116  if (LittleEndian)
117  return "e-m:e-i64:64-i128:128-n32:64-S128";
118  return "E-m:e-i64:64-i128:128-n32:64-S128";
119 }
120 
121 /// TargetMachine ctor - Create an AArch64 architecture model.
122 ///
124  StringRef CPU, StringRef FS,
125  const TargetOptions &Options,
128  bool LittleEndian)
129  // This nested ternary is horrible, but DL needs to be properly
130  // initialized before TLInfo is constructed.
131  : LLVMTargetMachine(T, computeDataLayout(TT, LittleEndian), TT, CPU, FS,
132  Options, RM, CM, OL),
133  TLOF(createTLOF(getTargetTriple())),
134  isLittle(LittleEndian) {
135  initAsmInfo();
136 }
137 
139 
140 const AArch64Subtarget *
142  Attribute CPUAttr = F.getFnAttribute("target-cpu");
143  Attribute FSAttr = F.getFnAttribute("target-features");
144 
145  std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
146  ? CPUAttr.getValueAsString().str()
147  : TargetCPU;
148  std::string FS = !FSAttr.hasAttribute(Attribute::None)
149  ? FSAttr.getValueAsString().str()
150  : TargetFS;
151 
152  auto &I = SubtargetMap[CPU + FS];
153  if (!I) {
154  // This needs to be done before we create a new subtarget since any
155  // creation will depend on the TM and the code generation flags on the
156  // function that reside in TargetOptions.
158  I = llvm::make_unique<AArch64Subtarget>(TargetTriple, CPU, FS, *this,
159  isLittle);
160  }
161  return I.get();
162 }
163 
164 void AArch64leTargetMachine::anchor() { }
165 
167  const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
168  const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
170  : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
171 
172 void AArch64beTargetMachine::anchor() { }
173 
175  const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
176  const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
178  : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
179 
180 namespace {
181 /// AArch64 Code Generator Pass Configuration Options.
182 class AArch64PassConfig : public TargetPassConfig {
183 public:
184  AArch64PassConfig(AArch64TargetMachine *TM, PassManagerBase &PM)
185  : TargetPassConfig(TM, PM) {
186  if (TM->getOptLevel() != CodeGenOpt::None)
187  substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
188  }
189 
190  AArch64TargetMachine &getAArch64TargetMachine() const {
191  return getTM<AArch64TargetMachine>();
192  }
193 
194  void addIRPasses() override;
195  bool addPreISel() override;
196  bool addInstSelector() override;
197  bool addILPOpts() override;
198  void addPreRegAlloc() override;
199  void addPostRegAlloc() override;
200  void addPreSched2() override;
201  void addPreEmitPass() override;
202 };
203 } // namespace
204 
206  return TargetIRAnalysis([this](Function &F) {
207  return TargetTransformInfo(AArch64TTIImpl(this, F));
208  });
209 }
210 
212  return new AArch64PassConfig(this, PM);
213 }
214 
215 void AArch64PassConfig::addIRPasses() {
216  // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
217  // ourselves.
218  addPass(createAtomicExpandPass(TM));
219 
220  // Cmpxchg instructions are often used with a subsequent comparison to
221  // determine whether it succeeded. We can exploit existing control-flow in
222  // ldrex/strex loops to simplify this, but it needs tidying up.
223  if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
224  addPass(createCFGSimplificationPass());
225 
227 
228  // Match interleaved memory accesses to ldN/stN intrinsics.
229  if (TM->getOptLevel() != CodeGenOpt::None)
231 
232  if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
233  // Call SeparateConstOffsetFromGEP pass to extract constants within indices
234  // and lower a GEP with multiple indices to either arithmetic operations or
235  // multiple GEPs with single index.
237  // Call EarlyCSE pass to find and remove subexpressions in the lowered
238  // result.
239  addPass(createEarlyCSEPass());
240  // Do loop invariant code motion in case part of the lowered result is
241  // invariant.
242  addPass(createLICMPass());
243  }
244 }
245 
246 // Pass Pipeline Configuration
247 bool AArch64PassConfig::addPreISel() {
248  // Run promote constant before global merge, so that the promoted constants
249  // get a chance to be merged
250  if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
252  // FIXME: On AArch64, this depends on the type.
253  // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
254  // and the offset has to be a multiple of the related size in bytes.
255  if ((TM->getOptLevel() != CodeGenOpt::None &&
257  EnableGlobalMerge == cl::BOU_TRUE) {
258  bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
259  (EnableGlobalMerge == cl::BOU_UNSET);
260  addPass(createGlobalMergePass(TM, 4095, OnlyOptimizeForSize));
261  }
262 
263  if (TM->getOptLevel() != CodeGenOpt::None)
265 
266  return false;
267 }
268 
269 bool AArch64PassConfig::addInstSelector() {
270  addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
271 
272  // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
273  // references to _TLS_MODULE_BASE_ as possible.
274  if (TM->getTargetTriple().isOSBinFormatELF() &&
275  getOptLevel() != CodeGenOpt::None)
277 
278  return false;
279 }
280 
281 bool AArch64PassConfig::addILPOpts() {
282  if (EnableCondOpt)
284  if (EnableCCMP)
286  if (EnableMCR)
287  addPass(&MachineCombinerID);
289  addPass(&EarlyIfConverterID);
292  return true;
293 }
294 
295 void AArch64PassConfig::addPreRegAlloc() {
296  // Use AdvSIMD scalar instructions whenever profitable.
297  if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
298  addPass(createAArch64AdvSIMDScalar());
299  // The AdvSIMD pass may produce copies that can be rewritten to
300  // be register coaleascer friendly.
301  addPass(&PeepholeOptimizerID);
302  }
303 }
304 
305 void AArch64PassConfig::addPostRegAlloc() {
306  // Change dead register definitions to refer to the zero register.
307  if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
309  if (TM->getOptLevel() != CodeGenOpt::None && usingDefaultRegAlloc())
310  // Improve performance for some FP/SIMD code for A57.
312 }
313 
314 void AArch64PassConfig::addPreSched2() {
315  // Expand some pseudo instructions to allow proper scheduling.
317  // Use load/store pair instructions when possible.
318  if (TM->getOptLevel() != CodeGenOpt::None && EnableLoadStoreOpt)
320 }
321 
322 void AArch64PassConfig::addPreEmitPass() {
323  if (EnableA53Fix835769)
324  addPass(createAArch64A53Fix835769());
325  // Relax conditional branch instructions if they're otherwise out of
326  // range of their destination.
328  if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
329  TM->getTargetTriple().isOSBinFormatMachO())
330  addPass(createAArch64CollectLOHPass());
331 }
static cl::opt< cl::boolOrDefault > EnableGlobalMerge("aarch64-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"))
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:489
FunctionPass * createAArch64BranchRelaxation()
createAArch64BranchRelaxation - returns an instance of the constpool island pass. ...
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: Passes.cpp:377
const AArch64Subtarget * getSubtargetImpl(const Function &F) const override
Virtual method implemented by subclasses that returns a reference to that target's TargetSubtargetInf...
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with...
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions...
Analysis pass providing the TargetTransformInfo.
FunctionPass * createInterleavedAccessPass(const TargetMachine *TM)
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:188
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:225
F(f)
FunctionPass * createAArch64ConditionalCompares()
ModulePass * createAArch64PromoteConstantPass()
bool hasAttribute(AttrKind Val) const
Return true if the attribute is present.
Definition: Attributes.cpp:147
FunctionPass * createAArch64CollectLOHPass()
createAArch64CollectLOHPass - returns an instance of the Statistic for linker optimization pass...
static cl::opt< bool > EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden, cl::desc("Run early if-conversion"), cl::init(true))
FunctionPass * createAtomicExpandPass(const TargetMachine *TM)
No attributes have been set.
Definition: Attributes.h:66
#define false
Definition: ConvertUTF.c:65
Target-Independent Code Generator Pass Configuration Options.
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
FunctionPass * createAArch64A57FPLoadBalancing()
static cl::opt< bool > EnableCollectLOH("aarch64-collect-loh", cl::desc("Enable the pass that emits the"" linker optimization hints (LOH)"), cl::init(true), cl::Hidden)
FunctionPass * createAArch64LoadStoreOptimizationPass()
createARMLoadStoreOptimizationPass - returns an instance of the load / store optimization pass...
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
static std::string computeDataLayout(const Triple &TT, bool LittleEndian)
#define true
Definition: ConvertUTF.c:66
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:325
AArch64beTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL)
FunctionPass * createSeparateConstOffsetFromGEPPass(const TargetMachine *TM=nullptr, bool LowerGEP=false)
void LLVMInitializeAArch64Target()
static cl::opt< bool > EnableDeadRegisterElimination("aarch64-dead-def-elimination", cl::Hidden, cl::desc("Enable the pass that removes dead"" definitons and replaces stores to"" them with stores to the zero"" register"), cl::init(true))
FunctionPass * createCFGSimplificationPass(int Threshold=-1, std::function< bool(const Function &)> Ftor=nullptr)
FunctionPass * createAArch64AdvSIMDScalar()
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang","erlang-compatible garbage collector")
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Target TheARM64Target
AArch64TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool IsLittleEndian)
TargetMachine ctor - Create an AArch64 architecture model.
static cl::opt< bool > EnableGEPOpt("aarch64-gep-opt", cl::Hidden, cl::desc("Enable optimizations on complex GEPs"), cl::init(false))
FunctionPass * createEarlyCSEPass()
Definition: EarlyCSE.cpp:771
static cl::opt< bool > EnableCondOpt("aarch64-condopt", cl::desc("Enable the condition optimizer pass"), cl::init(true), cl::Hidden)
This file a TargetTransformInfo::Concept conforming object specific to the AArch64 target machine...
FunctionPass * createAArch64AddressTypePromotionPass()
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
Target TheAArch64leTarget
char & PostRASchedulerID
createPostRAScheduler - This pass performs post register allocation scheduling.
static cl::opt< bool > EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden, cl::desc("Work around Cortex-A53 erratum 835769"), cl::init(false))
Target TheAArch64beTarget
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
AArch64leTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL)
FunctionPass * createAArch64ExpandPseudoPass()
Returns an instance of the pseudo instruction expansion pass.
FunctionPass * createAArch64A53Fix835769()
FunctionPass * createAArch64StorePairSuppressPass()
static cl::opt< bool > EnablePromoteConstant("aarch64-promote-const", cl::desc("Enable the promote ""constant pass"), cl::init(true), cl::Hidden)
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
Target - Wrapper for Target specific information.
Pass * createLICMPass()
Definition: LICM.cpp:172
char & PeepholeOptimizerID
PeepholeOptimizer - This pass performs peephole optimizations - like extension and comparison elimina...
FunctionPass * createAArch64ConditionOptimizerPass()
static cl::opt< bool > EnableMCR("aarch64-mcr", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
TargetIRAnalysis getTargetIRAnalysis() override
Get the TargetIRAnalysis for this target.
FunctionPass * createAArch64ISelDag(AArch64TargetMachine &TM, CodeGenOpt::Level OptLevel)
createAArch64ISelDag - This pass converts a legalized DAG into a AArch64-specific DAG...
static cl::opt< bool > EnableAtomicTidy("aarch64-atomic-cfg-tidy", cl::Hidden, cl::desc("Run SimplifyCFG after expanding atomic operations"" to make use of cmpxchg flow-based information"), cl::init(true))
static cl::opt< bool > EnableLoadStoreOpt("aarch64-load-store-opt", cl::desc("Enable the load/store pair"" optimization pass"), cl::init(true), cl::Hidden)
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
StringMap< std::unique_ptr< AArch64Subtarget > > SubtargetMap
#define I(x, y, z)
Definition: MD5.cpp:54
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:140
static cl::opt< bool > EnableCCMP("aarch64-ccmp", cl::desc("Enable the CCMP formation pass"), cl::init(true), cl::Hidden)
RegisterTargetMachine - Helper template for registering a target machine implementation, for use in the target machine initialization function.
FunctionPass * createAArch64DeadRegisterDefinitions()
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:40
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml","ocaml 3.10-compatible collector")
static cl::opt< bool > EnableAdvSIMDScalar("aarch64-simd-scalar", cl::desc("Enable use of AdvSIMD scalar"" integer instructions"), cl::init(false), cl::Hidden)
static cl::opt< bool > EnableStPairSuppress("aarch64-stp-suppress", cl::desc("Suppress STP for AArch64"), cl::init(true), cl::Hidden)
Pass * createGlobalMergePass(const TargetMachine *TM, unsigned MaximalOffset, bool OnlyOptimizeForSize=false)
FunctionPass * createAArch64CleanupLocalDynamicTLSPass()