LLVM  3.7.0
Public Types | Public Member Functions | Static Public Member Functions | Protected Member Functions | List of all members
llvm::TargetRegisterInfo Class Referenceabstract

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDesc objects that represent all of the machine registers that the target has. More...

#include <TargetRegisterInfo.h>

Inheritance diagram for llvm::TargetRegisterInfo:
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Collaboration diagram for llvm::TargetRegisterInfo:
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Public Types

typedef const
TargetRegisterClass *const
regclass_iterator
 
- Public Types inherited from llvm::MCRegisterInfo
typedef const MCRegisterClassregclass_iterator
 

Public Member Functions

const TargetRegisterClassgetMinimalPhysRegClass (unsigned Reg, MVT VT=MVT::Other) const
 getMinimalPhysRegClass - Returns the Register Class of a physical register of the given type, picking the most sub register class of the right type that contains this physreg. More...
 
const TargetRegisterClassgetAllocatableClass (const TargetRegisterClass *RC) const
 getAllocatableClass - Return the maximal subclass of the given register class that is alloctable, or NULL. More...
 
BitVector getAllocatableSet (const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const
 getAllocatableSet - Returns a bitset indexed by register number indicating if a register is allocatable or not. More...
 
unsigned getCostPerUse (unsigned RegNo) const
 getCostPerUse - Return the additional cost of using this register instead of other registers in its class. More...
 
bool isInAllocatableClass (unsigned RegNo) const
 isInAllocatableClass - Return true if the register is in the allocation of any register class. More...
 
const char * getSubRegIndexName (unsigned SubIdx) const
 getSubRegIndexName - Return the human-readable symbolic target-specific name for the specified SubRegIndex. More...
 
unsigned getSubRegIndexLaneMask (unsigned SubIdx) const
 getSubRegIndexLaneMask - Return a bitmask representing the parts of a register that are covered by SubIdx. More...
 
unsigned getCoveringLanes () const
 The lane masks returned by getSubRegIndexLaneMask() above can only be used to determine if sub-registers overlap - they can't be used to determine if a set of sub-registers completely cover another sub-register. More...
 
bool regsOverlap (unsigned regA, unsigned regB) const
 regsOverlap - Returns true if the two registers are equal or alias each other. More...
 
bool hasRegUnit (unsigned Reg, unsigned RegUnit) const
 hasRegUnit - Returns true if Reg contains RegUnit. More...
 
virtual const MCPhysReggetCalleeSavedRegs (const MachineFunction *MF) const =0
 getCalleeSavedRegs - Return a null-terminated list of all of the callee saved registers on this target. More...
 
virtual const uint32_t * getCallPreservedMask (const MachineFunction &MF, CallingConv::ID) const
 getCallPreservedMask - Return a mask of call-preserved registers for the given calling convention on the current function. More...
 
virtual ArrayRef< const
uint32_t * > 
getRegMasks () const =0
 Return all the call-preserved register masks defined for this target. More...
 
virtual ArrayRef< const char * > getRegMaskNames () const =0
 
virtual BitVector getReservedRegs (const MachineFunction &MF) const =0
 getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times, e.g. More...
 
virtual void adjustStackMapLiveOutMask (uint32_t *Mask) const
 Prior to adding the live-out mask to a stackmap or patchpoint instruction, provide the target the opportunity to adjust it (mainly to remove pseudo-registers that should be ignored). More...
 
unsigned getMatchingSuperReg (unsigned Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
 getMatchingSuperReg - Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg. More...
 
virtual const TargetRegisterClassgetMatchingSuperRegClass (const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
 getMatchingSuperRegClass - Return a subclass of the specified register class A so that each register in it has a sub-register of the specified sub-register index which is in the specified register class B. More...
 
virtual const TargetRegisterClassgetSubClassWithSubReg (const TargetRegisterClass *RC, unsigned Idx) const
 getSubClassWithSubReg - Returns the largest legal sub-class of RC that supports the sub-register index Idx. More...
 
unsigned composeSubRegIndices (unsigned a, unsigned b) const
 composeSubRegIndices - Return the subregister index you get from composing two subregister indices. More...
 
unsigned composeSubRegIndexLaneMask (unsigned IdxA, unsigned LaneMask) const
 Transforms a LaneMask computed for one subregister to the lanemask that would have been computed when composing the subsubregisters with IdxA first. More...
 
const TargetRegisterClassgetCommonSuperRegClass (const TargetRegisterClass *RCA, unsigned SubA, const TargetRegisterClass *RCB, unsigned SubB, unsigned &PreA, unsigned &PreB) const
 getCommonSuperRegClass - Find a common super-register class if it exists. More...
 
regclass_iterator regclass_begin () const
 Register class iterators. More...
 
regclass_iterator regclass_end () const
 
unsigned getNumRegClasses () const
 
const TargetRegisterClassgetRegClass (unsigned i) const
 getRegClass - Returns the register class associated with the enumeration value. More...
 
const char * getRegClassName (const TargetRegisterClass *Class) const
 getRegClassName - Returns the name of the register class. More...
 
const TargetRegisterClassgetCommonSubClass (const TargetRegisterClass *A, const TargetRegisterClass *B) const
 getCommonSubClass - find the largest common subclass of A and B. More...
 
virtual const TargetRegisterClassgetPointerRegClass (const MachineFunction &MF, unsigned Kind=0) const
 getPointerRegClass - Returns a TargetRegisterClass used for pointer values. More...
 
virtual const TargetRegisterClassgetCrossCopyRegClass (const TargetRegisterClass *RC) const
 getCrossCopyRegClass - Returns a legal register class to copy a register in the specified class to or from. More...
 
virtual const TargetRegisterClassgetLargestLegalSuperClass (const TargetRegisterClass *RC, const MachineFunction &) const
 getLargestLegalSuperClass - Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size. More...
 
virtual unsigned getRegPressureLimit (const TargetRegisterClass *RC, MachineFunction &MF) const
 getRegPressureLimit - Return the register pressure "high water mark" for the specific register class. More...
 
virtual const RegClassWeightgetRegClassWeight (const TargetRegisterClass *RC) const =0
 Get the weight in units of pressure for this register class. More...
 
virtual unsigned getRegUnitWeight (unsigned RegUnit) const =0
 Get the weight in units of pressure for this register unit. More...
 
virtual unsigned getNumRegPressureSets () const =0
 Get the number of dimensions of register pressure. More...
 
virtual const char * getRegPressureSetName (unsigned Idx) const =0
 Get the name of this register unit pressure set. More...
 
virtual unsigned getRegPressureSetLimit (const MachineFunction &MF, unsigned Idx) const =0
 Get the register unit pressure limit for this dimension. More...
 
virtual const intgetRegClassPressureSets (const TargetRegisterClass *RC) const =0
 Get the dimensions of register pressure impacted by this register class. More...
 
virtual const intgetRegUnitPressureSets (unsigned RegUnit) const =0
 Get the dimensions of register pressure impacted by this register unit. More...
 
virtual void getRegAllocationHints (unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr) const
 Get a list of 'hint' registers that the register allocator should try first when allocating a physical register for the virtual register VirtReg. More...
 
virtual void updateRegAllocHint (unsigned Reg, unsigned NewReg, MachineFunction &MF) const
 updateRegAllocHint - A callback to allow target a chance to update register allocation hints when a register is "changed" (e.g. More...
 
virtual bool reverseLocalAssignment () const
 Allow the target to reverse allocation order of local live ranges. More...
 
virtual unsigned getCSRFirstUseCost () const
 Allow the target to override the cost of using a callee-saved register for the first time. More...
 
virtual bool requiresRegisterScavenging (const MachineFunction &MF) const
 requiresRegisterScavenging - returns true if the target requires (and can make use of) the register scavenger. More...
 
virtual bool useFPForScavengingIndex (const MachineFunction &MF) const
 useFPForScavengingIndex - returns true if the target wants to use frame pointer based accesses to spill to the scavenger emergency spill slot. More...
 
virtual bool requiresFrameIndexScavenging (const MachineFunction &MF) const
 requiresFrameIndexScavenging - returns true if the target requires post PEI scavenging of registers for materializing frame index constants. More...
 
virtual bool requiresVirtualBaseRegisters (const MachineFunction &MF) const
 requiresVirtualBaseRegisters - Returns true if the target wants the LocalStackAllocation pass to be run and virtual base registers used for more efficient stack access. More...
 
virtual bool hasReservedSpillSlot (const MachineFunction &MF, unsigned Reg, int &FrameIdx) const
 hasReservedSpillSlot - Return true if target has reserved a spill slot in the stack frame of the given function for the specified register. More...
 
virtual bool trackLivenessAfterRegAlloc (const MachineFunction &MF) const
 trackLivenessAfterRegAlloc - returns true if the live-ins should be tracked after register allocation. More...
 
virtual bool needsStackRealignment (const MachineFunction &MF) const
 needsStackRealignment - true if storage within the function requires the stack pointer to be aligned more than the normal calling convention calls for. More...
 
virtual int64_t getFrameIndexInstrOffset (const MachineInstr *MI, int Idx) const
 getFrameIndexInstrOffset - Get the offset from the referenced frame index in the instruction, if there is one. More...
 
virtual bool needsFrameBaseReg (MachineInstr *MI, int64_t Offset) const
 needsFrameBaseReg - Returns true if the instruction's frame index reference would be better served by a base register other than FP or SP. More...
 
virtual void materializeFrameBaseRegister (MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const
 materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx before insertion point I. More...
 
virtual void resolveFrameIndex (MachineInstr &MI, unsigned BaseReg, int64_t Offset) const
 resolveFrameIndex - Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead. More...
 
virtual bool isFrameOffsetLegal (const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const
 isFrameOffsetLegal - Determine whether a given base register plus offset immediate is encodable to resolve a frame index. More...
 
virtual bool saveScavengerRegister (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, unsigned Reg) const
 saveScavengerRegister - Spill the register so it can be used by the register scavenger. More...
 
virtual void eliminateFrameIndex (MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const =0
 eliminateFrameIndex - This method must be overriden to eliminate abstract frame indices from instructions which may use them. More...
 
virtual bool shouldCoalesce (MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC) const
 Subtarget Hooks. More...
 
virtual unsigned getFrameRegister (const MachineFunction &MF) const =0
 Debug information queries. More...
 
- Public Member Functions inherited from llvm::MCRegisterInfo
void InitMCRegisterInfo (const MCRegisterDesc *D, unsigned NR, unsigned RA, unsigned PC, const MCRegisterClass *C, unsigned NC, const MCPhysReg(*RURoots)[2], unsigned NRU, const MCPhysReg *DL, const unsigned *RUMS, const char *Strings, const char *ClassStrings, const uint16_t *SubIndices, unsigned NumIndices, const SubRegCoveredBits *SubIdxRanges, const uint16_t *RET)
 Initialize MCRegisterInfo, called by TableGen auto-generated routines. More...
 
void mapLLVMRegsToDwarfRegs (const DwarfLLVMRegPair *Map, unsigned Size, bool isEH)
 Used to initialize LLVM register to Dwarf register number mapping. More...
 
void mapDwarfRegsToLLVMRegs (const DwarfLLVMRegPair *Map, unsigned Size, bool isEH)
 Used to initialize Dwarf register to LLVM register number mapping. More...
 
void mapLLVMRegToSEHReg (unsigned LLVMReg, int SEHReg)
 mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register number mapping. More...
 
unsigned getRARegister () const
 This method should return the register where the return address can be found. More...
 
unsigned getProgramCounter () const
 Return the register which is the program counter. More...
 
const MCRegisterDescoperator[] (unsigned RegNo) const
 
const MCRegisterDescget (unsigned RegNo) const
 Provide a get method, equivalent to [], but more useful with a pointer to this object. More...
 
unsigned getSubReg (unsigned Reg, unsigned Idx) const
 Returns the physical register number of sub-register "Index" for physical register RegNo. More...
 
unsigned getMatchingSuperReg (unsigned Reg, unsigned SubIdx, const MCRegisterClass *RC) const
 Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg. More...
 
unsigned getSubRegIndex (unsigned RegNo, unsigned SubRegNo) const
 For a given register pair, return the sub-register index if the second register is a sub-register of the first. More...
 
unsigned getSubRegIdxSize (unsigned Idx) const
 Get the size of the bit range covered by a sub-register index. More...
 
unsigned getSubRegIdxOffset (unsigned Idx) const
 Get the offset of the bit range covered by a sub-register index. More...
 
const char * getName (unsigned RegNo) const
 Return the human-readable symbolic target-specific name for the specified physical register. More...
 
unsigned getNumRegs () const
 Return the number of registers this target has (useful for sizing arrays holding per register information) More...
 
unsigned getNumSubRegIndices () const
 Return the number of sub-register indices understood by the target. More...
 
unsigned getNumRegUnits () const
 Return the number of (native) register units in the target. More...
 
int getDwarfRegNum (unsigned RegNum, bool isEH) const
 Map a target register to an equivalent dwarf register number. More...
 
int getLLVMRegNum (unsigned RegNum, bool isEH) const
 Map a dwarf register back to a target register. More...
 
int getSEHRegNum (unsigned RegNum) const
 Map a target register to an equivalent SEH register number. More...
 
regclass_iterator regclass_begin () const
 
regclass_iterator regclass_end () const
 
unsigned getNumRegClasses () const
 
const MCRegisterClassgetRegClass (unsigned i) const
 Returns the register class associated with the enumeration value. More...
 
const char * getRegClassName (const MCRegisterClass *Class) const
 
uint16_t getEncodingValue (unsigned RegNo) const
 Returns the encoding for RegNo. More...
 
bool isSubRegister (unsigned RegA, unsigned RegB) const
 Returns true if RegB is a sub-register of RegA. More...
 
bool isSuperRegister (unsigned RegA, unsigned RegB) const
 Returns true if RegB is a super-register of RegA. More...
 
bool isSubRegisterEq (unsigned RegA, unsigned RegB) const
 Returns true if RegB is a sub-register of RegA or if RegB == RegA. More...
 
bool isSuperRegisterEq (unsigned RegA, unsigned RegB) const
 Returns true if RegB is a super-register of RegA or if RegB == RegA. More...
 

Static Public Member Functions

static bool isStackSlot (unsigned Reg)
 isStackSlot - Sometimes it is useful the be able to store a non-negative frame index in a variable that normally holds a register. More...
 
static int stackSlot2Index (unsigned Reg)
 stackSlot2Index - Compute the frame index from a register value representing a stack slot. More...
 
static unsigned index2StackSlot (int FI)
 index2StackSlot - Convert a non-negative frame index to a stack slot register value. More...
 
static bool isPhysicalRegister (unsigned Reg)
 isPhysicalRegister - Return true if the specified register number is in the physical register namespace. More...
 
static bool isVirtualRegister (unsigned Reg)
 isVirtualRegister - Return true if the specified register number is in the virtual register namespace. More...
 
static unsigned virtReg2Index (unsigned Reg)
 virtReg2Index - Convert a virtual register number to a 0-based index. More...
 
static unsigned index2VirtReg (unsigned Index)
 index2VirtReg - Convert a 0-based index to a virtual register number. More...
 
static bool isImpreciseLaneMask (unsigned LaneMask)
 Returns true if the given lane mask is imprecise. More...
 
static void dumpReg (unsigned Reg, unsigned SubRegIndex=0, const TargetRegisterInfo *TRI=nullptr)
 Debugging helper: dump register in human readable form to dbgs() stream. More...
 

Protected Member Functions

 TargetRegisterInfo (const TargetRegisterInfoDesc *ID, regclass_iterator RegClassBegin, regclass_iterator RegClassEnd, const char *const *SRINames, const unsigned *SRILaneMasks, unsigned CoveringLanes)
 
virtual ~TargetRegisterInfo ()
 
virtual unsigned composeSubRegIndicesImpl (unsigned, unsigned) const
 Overridden by TableGen in targets that have sub-registers. More...
 
virtual unsigned composeSubRegIndexLaneMaskImpl (unsigned, unsigned) const
 Overridden by TableGen in targets that have sub-registers. More...
 

Detailed Description

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDesc objects that represent all of the machine registers that the target has.

As such, we simply have to track a pointer to this array so that we can turn register number into a register descriptor.

Definition at line 228 of file TargetRegisterInfo.h.

Member Typedef Documentation

Definition at line 230 of file TargetRegisterInfo.h.

Constructor & Destructor Documentation

TargetRegisterInfo::TargetRegisterInfo ( const TargetRegisterInfoDesc ID,
regclass_iterator  RegClassBegin,
regclass_iterator  RegClassEnd,
const char *const SRINames,
const unsigned SRILaneMasks,
unsigned  CoveringLanes 
)
protected

Definition at line 24 of file TargetRegisterInfo.cpp.

TargetRegisterInfo::~TargetRegisterInfo ( )
protectedvirtual

Definition at line 35 of file TargetRegisterInfo.cpp.

Member Function Documentation

virtual void llvm::TargetRegisterInfo::adjustStackMapLiveOutMask ( uint32_t *  Mask) const
inlinevirtual

Prior to adding the live-out mask to a stackmap or patchpoint instruction, provide the target the opportunity to adjust it (mainly to remove pseudo-registers that should be ignored).

Definition at line 485 of file TargetRegisterInfo.h.

unsigned llvm::TargetRegisterInfo::composeSubRegIndexLaneMask ( unsigned  IdxA,
unsigned  LaneMask 
) const
inline

Transforms a LaneMask computed for one subregister to the lanemask that would have been computed when composing the subsubregisters with IdxA first.

See Also
composeSubRegIndices()

Definition at line 544 of file TargetRegisterInfo.h.

References composeSubRegIndexLaneMaskImpl().

virtual unsigned llvm::TargetRegisterInfo::composeSubRegIndexLaneMaskImpl ( unsigned  ,
unsigned   
) const
inlineprotectedvirtual

Overridden by TableGen in targets that have sub-registers.

Definition at line 562 of file TargetRegisterInfo.h.

References llvm_unreachable.

Referenced by composeSubRegIndexLaneMask().

unsigned llvm::TargetRegisterInfo::composeSubRegIndices ( unsigned  a,
unsigned  b 
) const
inline

composeSubRegIndices - Return the subregister index you get from composing two subregister indices.

The special null sub-register index composes as the identity.

If R:a:b is the same register as R:c, then composeSubRegIndices(a, b) returns c. Note that composeSubRegIndices does not tell you about illegal compositions. If R does not have a subreg a, or R:a does not have a subreg b, composeSubRegIndices doesn't tell you.

The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has ssub_0:S0 - ssub_3:S3 subregs. If you compose subreg indices dsub_1, ssub_0 you get ssub_2.

Definition at line 535 of file TargetRegisterInfo.h.

References composeSubRegIndicesImpl().

Referenced by getCommonSuperRegClass(), llvm::CoalescerPair::isCoalescable(), and llvm::MachineOperand::substVirtReg().

virtual unsigned llvm::TargetRegisterInfo::composeSubRegIndicesImpl ( unsigned  ,
unsigned   
) const
inlineprotectedvirtual

Overridden by TableGen in targets that have sub-registers.

Definition at line 556 of file TargetRegisterInfo.h.

References llvm_unreachable.

Referenced by composeSubRegIndices().

void TargetRegisterInfo::dumpReg ( unsigned  Reg,
unsigned  SubRegIndex = 0,
const TargetRegisterInfo TRI = nullptr 
)
static

Debugging helper: dump register in human readable form to dbgs() stream.

Definition at line 300 of file TargetRegisterInfo.cpp.

References llvm::dbgs().

virtual void llvm::TargetRegisterInfo::eliminateFrameIndex ( MachineBasicBlock::iterator  MI,
int  SPAdj,
unsigned  FIOperandNum,
RegScavenger RS = nullptr 
) const
pure virtual

eliminateFrameIndex - This method must be overriden to eliminate abstract frame indices from instructions which may use them.

The instruction referenced by the iterator contains an MO_FrameIndex operand which must be eliminated by this method. This method may modify or replace the specified instruction, as long as it keeps the iterator pointing at the finished product. SPAdj is the SP adjustment due to call frame setup instruction. FIOperandNum is the FI operand number.

Referenced by llvm::RegScavenger::scavengeRegister().

const TargetRegisterClass * TargetRegisterInfo::getAllocatableClass ( const TargetRegisterClass RC) const

getAllocatableClass - Return the maximal subclass of the given register class that is alloctable, or NULL.

Definition at line 88 of file TargetRegisterInfo.cpp.

References llvm::countTrailingZeros(), getNumRegClasses(), getRegClass(), llvm::TargetRegisterClass::getSubClassMask(), and llvm::TargetRegisterClass::isAllocatable().

Referenced by getAllocatableSet().

BitVector TargetRegisterInfo::getAllocatableSet ( const MachineFunction MF,
const TargetRegisterClass RC = nullptr 
) const

getAllocatableSet - Returns a bitset indexed by register number indicating if a register is allocatable or not.

If a register class is specified, returns the subset for the class.

Definition at line 139 of file TargetRegisterInfo.cpp.

References llvm::BitVector::flip(), getAllocatableClass(), getAllocatableSetForRC(), llvm::MCRegisterInfo::getNumRegs(), getReservedRegs(), I, regclass_begin(), regclass_end(), and llvm::Reserved.

Referenced by addLiveInRegs(), llvm::AggressiveAntiDepBreaker::AggressiveAntiDepBreaker(), and llvm::RegScavenger::scavengeRegister().

virtual const MCPhysReg* llvm::TargetRegisterInfo::getCalleeSavedRegs ( const MachineFunction MF) const
pure virtual

getCalleeSavedRegs - Return a null-terminated list of all of the callee saved registers on this target.

The register should be in the order of desired callee-save stack frame offset. The first register is closest to the incoming stack pointer if stack grows down, and vice versa.

Referenced by addPristines(), llvm::SystemZFrameLowering::determineCalleeSaves(), llvm::TargetFrameLowering::determineCalleeSaves(), DoesModifyCalleeSavedReg(), llvm::MipsFrameLowering::estimateStackSize(), llvm::MachineFrameInfo::getPristineRegs(), isACalleeSavedRegister(), llvm::RegisterClassInfo::runOnMachineFunction(), llvm::CriticalAntiDepBreaker::StartBlock(), llvm::AggressiveAntiDepBreaker::StartBlock(), and llvm::tryFoldSPUpdateIntoPushPop().

virtual const uint32_t* llvm::TargetRegisterInfo::getCallPreservedMask ( const MachineFunction MF,
CallingConv::ID   
) const
inlinevirtual

getCallPreservedMask - Return a mask of call-preserved registers for the given calling convention on the current function.

The mask should include all call-preserved aliases. This is used by the register allocator to determine which registers can be live across a call.

The mask is an array containing (TRI::getNumRegs()+31)/32 entries. A set bit indicates that all bits of the corresponding register are preserved across the function call. The bit mask is expected to be sub-register complete, i.e. if A is preserved, so are all its sub-registers.

Bits are numbered from the LSB, so the bit for physical register Reg can be found as (Mask[Reg / 32] >> Reg % 32) & 1.

A NULL pointer means that no register mask will be used, and call instructions should use implicit-def operands to indicate call clobbered registers.

Definition at line 466 of file TargetRegisterInfo.h.

Referenced by llvm::MipsTargetLowering::getOpndList(), llvm::SystemZTargetLowering::LowerCall(), and llvm::FastISel::selectPatchpoint().

const TargetRegisterClass * TargetRegisterInfo::getCommonSubClass ( const TargetRegisterClass A,
const TargetRegisterClass B 
) const
const TargetRegisterClass * TargetRegisterInfo::getCommonSuperRegClass ( const TargetRegisterClass RCA,
unsigned  SubA,
const TargetRegisterClass RCB,
unsigned  SubB,
unsigned PreA,
unsigned PreB 
) const

getCommonSuperRegClass - Find a common super-register class if it exists.

Find a register class, SuperRC and two sub-register indices, PreA and PreB, such that:

  1. PreA + SubA == PreB + SubB (using composeSubRegIndices()), and
  2. For all Reg in SuperRC: Reg:PreA in RCA and Reg:PreB in RCB, and
  3. SuperRC->getSize() >= max(RCA->getSize(), RCB->getSize()).

SuperRC will be chosen such that no super-class of SuperRC satisfies the requirements, and there is no register class with a smaller spill size that satisfies the requirements.

SubA and SubB must not be 0. Use getMatchingSuperRegClass() instead.

Either of the PreA and PreB sub-register indices may be returned as 0. In that case, the returned register class will be a sub-class of the corresponding argument register class.

The function returns NULL if no register class can be found.

Definition at line 202 of file TargetRegisterInfo.cpp.

References composeSubRegIndices(), firstCommonClass(), llvm::TargetRegisterClass::getSize(), llvm::SuperRegClassIterator::isValid(), and std::swap().

Referenced by llvm::CoalescerPair::setRegisters(), and shareSameRegisterFile().

unsigned llvm::TargetRegisterInfo::getCostPerUse ( unsigned  RegNo) const
inline

getCostPerUse - Return the additional cost of using this register instead of other registers in its class.

Definition at line 333 of file TargetRegisterInfo.h.

References llvm::TargetRegisterInfoDesc::CostPerUse.

unsigned llvm::TargetRegisterInfo::getCoveringLanes ( ) const
inline

The lane masks returned by getSubRegIndexLaneMask() above can only be used to determine if sub-registers overlap - they can't be used to determine if a set of sub-registers completely cover another sub-register.

The X86 general purpose registers have two lanes corresponding to the sub_8bit and sub_8bit_hi sub-registers. Both sub_32bit and sub_16bit have lane masks '3', but the sub_16bit sub-register doesn't fully cover the sub_32bit sub-register.

On the other hand, the ARM NEON lanes fully cover their registers: The dsub_0 sub-register is completely covered by the ssub_0 and ssub_1 lanes. This is related to the CoveredBySubRegs property on register definitions.

This function returns a bit mask of lanes that completely cover their sub-registers. More precisely, given:

Covering = getCoveringLanes(); MaskA = getSubRegIndexLaneMask(SubA); MaskB = getSubRegIndexLaneMask(SubB);

If (MaskA & ~(MaskB & Covering)) == 0, then SubA is completely covered by SubB.

Definition at line 412 of file TargetRegisterInfo.h.

virtual const TargetRegisterClass* llvm::TargetRegisterInfo::getCrossCopyRegClass ( const TargetRegisterClass RC) const
inlinevirtual

getCrossCopyRegClass - Returns a legal register class to copy a register in the specified class to or from.

If it is possible to copy the register directly without using a cross register class copy, return the specified RC. Returns NULL if it is not possible to copy between a two registers of the specified class.

Definition at line 640 of file TargetRegisterInfo.h.

virtual unsigned llvm::TargetRegisterInfo::getCSRFirstUseCost ( ) const
inlinevirtual

Allow the target to override the cost of using a callee-saved register for the first time.

Default value of 0 means we will use a callee-saved register if it is available.

Definition at line 739 of file TargetRegisterInfo.h.

virtual int64_t llvm::TargetRegisterInfo::getFrameIndexInstrOffset ( const MachineInstr MI,
int  Idx 
) const
inlinevirtual

getFrameIndexInstrOffset - Get the offset from the referenced frame index in the instruction, if there is one.

Definition at line 793 of file TargetRegisterInfo.h.

virtual unsigned llvm::TargetRegisterInfo::getFrameRegister ( const MachineFunction MF) const
pure virtual
virtual const TargetRegisterClass* llvm::TargetRegisterInfo::getLargestLegalSuperClass ( const TargetRegisterClass RC,
const MachineFunction  
) const
inlinevirtual

getLargestLegalSuperClass - Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size.

The returned register class can be used to create virtual registers which means that all its registers can be copied and spilled.

The default implementation is very conservative and doesn't allow the register allocator to inflate register classes.

Definition at line 649 of file TargetRegisterInfo.h.

Referenced by llvm::PPCRegisterInfo::getLargestLegalSuperClass(), and llvm::MachineRegisterInfo::recomputeRegClass().

unsigned llvm::TargetRegisterInfo::getMatchingSuperReg ( unsigned  Reg,
unsigned  SubIdx,
const TargetRegisterClass RC 
) const
inline
const TargetRegisterClass * TargetRegisterInfo::getMatchingSuperRegClass ( const TargetRegisterClass A,
const TargetRegisterClass B,
unsigned  Idx 
) const
virtual

getMatchingSuperRegClass - Return a subclass of the specified register class A so that each register in it has a sub-register of the specified sub-register index which is in the specified register class B.

TableGen will synthesize missing A sub-classes.

Definition at line 186 of file TargetRegisterInfo.cpp.

References firstCommonClass(), llvm::TargetRegisterClass::getSubClassMask(), and llvm::SuperRegClassIterator::isValid().

Referenced by llvm::MachineInstr::getRegClassConstraintEffect(), llvm::CoalescerPair::setRegisters(), and shareSameRegisterFile().

const TargetRegisterClass * TargetRegisterInfo::getMinimalPhysRegClass ( unsigned  reg,
MVT  VT = MVT::Other 
) const
unsigned llvm::TargetRegisterInfo::getNumRegClasses ( ) const
inline
virtual unsigned llvm::TargetRegisterInfo::getNumRegPressureSets ( ) const
pure virtual
virtual const TargetRegisterClass* llvm::TargetRegisterInfo::getPointerRegClass ( const MachineFunction MF,
unsigned  Kind = 0 
) const
inlinevirtual

getPointerRegClass - Returns a TargetRegisterClass used for pointer values.

If a target supports multiple different pointer register classes, kind specifies which one is indicated.

Definition at line 630 of file TargetRegisterInfo.h.

References llvm_unreachable.

Referenced by llvm::TargetInstrInfo::getRegClass(), and llvm::MachineInstr::getRegClassConstraint().

void TargetRegisterInfo::getRegAllocationHints ( unsigned  VirtReg,
ArrayRef< MCPhysReg Order,
SmallVectorImpl< MCPhysReg > &  Hints,
const MachineFunction MF,
const VirtRegMap VRM = nullptr 
) const
virtual

Get a list of 'hint' registers that the register allocator should try first when allocating a physical register for the virtual register VirtReg.

These registers are effectively moved to the front of the allocation order.

The Order argument is the allocation order for VirtReg's register class as returned from RegisterClassInfo::getOrder(). The hint registers must come from Order, and they must not be reserved.

The default implementation of this function can resolve target-independent hints provided to MRI::setRegAllocationHint with HintType == 0. Targets that override this function should defer to the default implementation if they have no reason to change the allocation order for VirtReg. There may be target-independent hints.

Definition at line 265 of file TargetRegisterInfo.cpp.

References llvm::ArrayRef< T >::begin(), llvm::ArrayRef< T >::end(), llvm::VirtRegMap::getPhys(), llvm::MachineRegisterInfo::getRegAllocationHint(), llvm::MachineFunction::getRegInfo(), Hint(), isPhysicalRegister(), llvm::MachineRegisterInfo::isReserved(), isVirtualRegister(), and llvm::SmallVectorTemplateBase< T, isPodLike >::push_back().

Referenced by llvm::AllocationOrder::AllocationOrder(), and llvm::ARMBaseRegisterInfo::getRegAllocationHints().

const TargetRegisterClass* llvm::TargetRegisterInfo::getRegClass ( unsigned  i) const
inline
const char* llvm::TargetRegisterInfo::getRegClassName ( const TargetRegisterClass Class) const
inline
virtual const int* llvm::TargetRegisterInfo::getRegClassPressureSets ( const TargetRegisterClass RC) const
pure virtual

Get the dimensions of register pressure impacted by this register class.

Returns a -1 terminated array of pressure set IDs.

Referenced by llvm::RegisterClassInfo::computePSetLimit(), and llvm::PSetIterator::PSetIterator().

virtual const RegClassWeight& llvm::TargetRegisterInfo::getRegClassWeight ( const TargetRegisterClass RC) const
pure virtual

Get the weight in units of pressure for this register class.

Referenced by llvm::RegisterClassInfo::computePSetLimit(), llvm::PSetIterator::PSetIterator(), and llvm::ARMBaseRegisterInfo::shouldCoalesce().

virtual ArrayRef<const char *> llvm::TargetRegisterInfo::getRegMaskNames ( ) const
pure virtual
virtual ArrayRef<const uint32_t *> llvm::TargetRegisterInfo::getRegMasks ( ) const
pure virtual

Return all the call-preserved register masks defined for this target.

virtual unsigned llvm::TargetRegisterInfo::getRegPressureLimit ( const TargetRegisterClass RC,
MachineFunction MF 
) const
inlinevirtual

getRegPressureLimit - Return the register pressure "high water mark" for the specific register class.

The scheduler is in high register pressure mode (for the specific register class) if it goes over the limit.

Note: this is the old register pressure model that relies on a manually specified representative register class per value type.

Definition at line 662 of file TargetRegisterInfo.h.

Referenced by llvm::ResourcePriorityQueue::ResourcePriorityQueue().

virtual unsigned llvm::TargetRegisterInfo::getRegPressureSetLimit ( const MachineFunction MF,
unsigned  Idx 
) const
pure virtual

Get the register unit pressure limit for this dimension.

This limit must be adjusted dynamically for reserved registers.

Referenced by llvm::RegisterClassInfo::computePSetLimit().

virtual const char* llvm::TargetRegisterInfo::getRegPressureSetName ( unsigned  Idx) const
pure virtual
virtual const int* llvm::TargetRegisterInfo::getRegUnitPressureSets ( unsigned  RegUnit) const
pure virtual

Get the dimensions of register pressure impacted by this register unit.

Returns a -1 terminated array of pressure set IDs.

Referenced by llvm::PSetIterator::PSetIterator().

virtual unsigned llvm::TargetRegisterInfo::getRegUnitWeight ( unsigned  RegUnit) const
pure virtual

Get the weight in units of pressure for this register unit.

Referenced by llvm::PSetIterator::PSetIterator().

virtual BitVector llvm::TargetRegisterInfo::getReservedRegs ( const MachineFunction MF) const
pure virtual

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times, e.g.

SP, RA. This is used by register scavenger to determine what registers are free.

Referenced by llvm::HexagonFrameLowering::assignCalleeSavedSpillSlots(), llvm::MachineRegisterInfo::freezeReservedRegs(), and getAllocatableSet().

virtual const TargetRegisterClass* llvm::TargetRegisterInfo::getSubClassWithSubReg ( const TargetRegisterClass RC,
unsigned  Idx 
) const
inlinevirtual

getSubClassWithSubReg - Returns the largest legal sub-class of RC that supports the sub-register index Idx.

If no such sub-class exists, return NULL. If all registers in RC already have an Idx sub-register, return RC.

TableGen generates a version of this function that is good enough in most cases. Targets can override if they have constraints that TableGen doesn't understand. For example, the x86 sub_8bit sub-register index is supported by the full GR32 register class in 64-bit mode, but only by the GR32_ABCD regiister class in 32-bit mode.

TableGen will synthesize missing RC sub-classes.

Definition at line 516 of file TargetRegisterInfo.h.

Referenced by llvm::FastISel::fastEmitInst_extractsubreg(), and llvm::MachineInstr::getRegClassConstraintEffect().

unsigned llvm::TargetRegisterInfo::getSubRegIndexLaneMask ( unsigned  SubIdx) const
inline

getSubRegIndexLaneMask - Return a bitmask representing the parts of a register that are covered by SubIdx.

Lane masks for sub-register indices are similar to register units for physical registers. The individual bits in a lane mask can't be assigned any specific meaning. They can be used to check if two sub-register indices overlap.

If the target has a register such that:

getSubReg(Reg, A) overlaps getSubReg(Reg, B)

then:

(getSubRegIndexLaneMask(A) & getSubRegIndexLaneMask(B)) != 0

The converse is not necessarily true. If two lane masks have a common bit, the corresponding sub-registers may not overlap, but it can be assumed that they usually will. SubIdx == 0 is allowed, it has the lane mask ~0u.

Definition at line 371 of file TargetRegisterInfo.h.

References llvm::MCRegisterInfo::getNumSubRegIndices().

Referenced by llvm::LiveIntervals::addKillFlags(), llvm::LiveRangeCalc::calculate(), and llvm::LiveIntervals::shrinkToUses().

const char* llvm::TargetRegisterInfo::getSubRegIndexName ( unsigned  SubIdx) const
inline

getSubRegIndexName - Return the human-readable symbolic target-specific name for the specified SubRegIndex.

Definition at line 345 of file TargetRegisterInfo.h.

References llvm::MCRegisterInfo::getNumSubRegIndices().

Referenced by llvm::PrintReg::print(), and llvm::MachineInstr::print().

bool llvm::TargetRegisterInfo::hasRegUnit ( unsigned  Reg,
unsigned  RegUnit 
) const
inline

hasRegUnit - Returns true if Reg contains RegUnit.

Definition at line 433 of file TargetRegisterInfo.h.

References llvm::MCRegisterInfo::DiffListIterator::isValid().

virtual bool llvm::TargetRegisterInfo::hasReservedSpillSlot ( const MachineFunction MF,
unsigned  Reg,
int FrameIdx 
) const
inlinevirtual

hasReservedSpillSlot - Return true if target has reserved a spill slot in the stack frame of the given function for the specified register.

e.g. On x86, if the frame register is required, the first fixed stack object is reserved as its spill slot. This tells PEI not to create a new stack frame object for the given register. It should be called only after processFunctionBeforeCalleeSavedScan().

Definition at line 773 of file TargetRegisterInfo.h.

static unsigned llvm::TargetRegisterInfo::index2StackSlot ( int  FI)
inlinestatic

index2StackSlot - Convert a non-negative frame index to a stack slot register value.

Definition at line 282 of file TargetRegisterInfo.h.

Referenced by llvm::LiveStacks::getOrCreateInterval().

static unsigned llvm::TargetRegisterInfo::index2VirtReg ( unsigned  Index)
inlinestatic
virtual bool llvm::TargetRegisterInfo::isFrameOffsetLegal ( const MachineInstr MI,
unsigned  BaseReg,
int64_t  Offset 
) const
inlinevirtual

isFrameOffsetLegal - Determine whether a given base register plus offset immediate is encodable to resolve a frame index.

Definition at line 824 of file TargetRegisterInfo.h.

References llvm_unreachable.

Referenced by lookupCandidateBaseReg().

static bool llvm::TargetRegisterInfo::isImpreciseLaneMask ( unsigned  LaneMask)
inlinestatic

Returns true if the given lane mask is imprecise.

LaneMasks as given by getSubRegIndexLaneMask() have a limited number of bits, so for targets with more than 31 disjunct subregister indices there may be cases where: getSubReg(Reg,A) does not overlap getSubReg(Reg,B) but we still have (getSubRegIndexLaneMask(A) & getSubRegIndexLaneMask(B)) != 0. This function returns true in those cases.

Definition at line 385 of file TargetRegisterInfo.h.

bool llvm::TargetRegisterInfo::isInAllocatableClass ( unsigned  RegNo) const
inline

isInAllocatableClass - Return true if the register is in the allocation of any register class.

Definition at line 339 of file TargetRegisterInfo.h.

References llvm::TargetRegisterInfoDesc::inAllocatableClass.

Referenced by llvm::MachineRegisterInfo::isAllocatable().

static bool llvm::TargetRegisterInfo::isPhysicalRegister ( unsigned  Reg)
inlinestatic

isPhysicalRegister - Return true if the specified register number is in the physical register namespace.

Definition at line 289 of file TargetRegisterInfo.h.

References isStackSlot().

Referenced by llvm::ARMBaseInstrInfo::AddDReg(), llvm::MachineBasicBlock::addLiveIn(), llvm::DwarfExpression::AddMachineRegPiece(), llvm::MachineInstr::addRegisterDead(), llvm::MachineInstr::addRegisterDefined(), llvm::MachineInstr::addRegisterKilled(), llvm::ScheduleDAGInstrs::addSchedBarrierDeps(), AddSubReg(), llvm::MachineOperandIteratorBase::analyzePhysReg(), llvm::VirtRegMap::assignVirt2Phys(), biasPhysRegCopy(), llvm::ARMBaseInstrInfo::breakPartialRegDependency(), llvm::ScheduleDAGInstrs::buildSchedGraph(), llvm::VirtRegAuxInfo::calculateSpillWeightAndHint(), canCompareBeNewValueJump(), canFoldCopy(), canFoldIntoMOVCC(), llvm::X86InstrInfo::classifyLEAReg(), llvm::MachineInstr::clearRegisterKills(), llvm::SelectionDAGBuilder::CopyValueToVirtualRegister(), countOperands(), definesFullReg(), llvm::finalizeBundle(), findOnlyInterestingUse(), llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::MachineInstr::findRegisterUseOperandIdx(), llvm::CoalescerPair::flip(), llvm::X86InstrInfo::foldMemoryOperandImpl(), for(), llvm::BitTracker::MachineEvaluator::getCell(), getDataDeps(), getDef(), llvm::RegisterClassInfo::getLastCalleeSavedAlias(), getMappedReg(), getMinimalPhysRegClass(), llvm::ARMBaseRegisterInfo::getRegAllocationHints(), getRegAllocationHints(), llvm::BitTracker::MachineEvaluator::getRegBitWidth(), getRegisterName(), llvm::X86InstrInfo::getUndefRegClearance(), llvm::VirtRegMap::hasKnownPreference(), llvm::CoalescerPair::isCoalescable(), llvm::MachineRegisterInfo::isConstantPhysReg(), isCopyToReg(), isEvenReg(), llvm::MachineInstr::isIdenticalTo(), isKilled(), isLocalCopy(), llvm::Thumb1InstrInfo::loadRegFromStackSlot(), llvm::Thumb2InstrInfo::loadRegFromStackSlot(), llvm::ARMBaseInstrInfo::loadRegFromStackSlot(), MIIsInTerminatorSequence(), llvm::MachineInstr::print(), llvm::ARMAsmPrinter::printOperand(), llvm::MachineRegisterInfo::replaceRegWith(), llvm::GenericScheduler::reschedulePhysRegCopies(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::MachineInstr::setPhysRegsDeadExcept(), llvm::CoalescerPair::setRegisters(), llvm::MachineBasicBlock::SplitCriticalEdge(), llvm::Thumb1InstrInfo::storeRegToStackSlot(), llvm::MachineInstr::substituteRegister(), llvm::MachineOperand::substPhysReg(), UpdateOperandRegClass(), updatePhysDepsDownwards(), updatePhysDepsUpwards(), and llvm::DwarfCompileUnit::updateSubprogramScopeDIE().

static bool llvm::TargetRegisterInfo::isStackSlot ( unsigned  Reg)
inlinestatic

isStackSlot - Sometimes it is useful the be able to store a non-negative frame index in a variable that normally holds a register.

isStackSlot() returns true if Reg is in the range used for stack slots.

Note that isVirtualRegister() and isPhysicalRegister() cannot handle stack slots, so if a variable may contains a stack slot, always check isStackSlot() first.

Definition at line 269 of file TargetRegisterInfo.h.

Referenced by isPhysicalRegister(), isVirtualRegister(), llvm::PrintReg::print(), and stackSlot2Index().

static bool llvm::TargetRegisterInfo::isVirtualRegister ( unsigned  Reg)
inlinestatic

isVirtualRegister - Return true if the specified register number is in the virtual register namespace.

Definition at line 296 of file TargetRegisterInfo.h.

References isStackSlot().

Referenced by llvm::RegsForValue::AddInlineAsmOperands(), llvm::LiveVariables::addNewBlock(), llvm::RegPressureTracker::advance(), llvm::RegAllocBase::allocatePhysRegs(), llvm::VirtRegMap::assignVirt2Phys(), llvm::VirtRegMap::assignVirt2StackSlot(), llvm::RegPressureTracker::bumpDownwardPressure(), canCombineWithMUL(), canFoldCopy(), canFoldIntoCSel(), canFoldIntoMOVCC(), CheckForPhysRegDependency(), llvm::X86InstrInfo::classifyLEAReg(), llvm::VirtRegMap::clearVirt(), llvm::ScheduleDAGMILive::computeCyclicCriticalPath(), llvm::ScheduleDAGSDNodes::computeOperandLatency(), llvm::FunctionLoweringInfo::ComputePHILiveOutRegInfo(), llvm::FastISel::constrainOperandRegClass(), llvm::LiveRegSet::contains(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), llvm::SystemZInstrInfo::convertToThreeAddress(), llvm::X86InstrInfo::convertToThreeAddress(), copyHint(), llvm::R600TargetLowering::EmitInstrWithCustomInserter(), llvm::LiveRegSet::erase(), llvm::MachineInstr::eraseFromParentAndMarkDBGValuesForRemoval(), llvm::FastISel::fastEmitInst_extractsubreg(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), llvm::RegScavenger::forward(), genMadd(), genMaddR(), getCallTargetRegOpnd(), llvm::BitTracker::MachineEvaluator::getCell(), llvm::RegsForValue::getCopyFromRegs(), llvm::MachineInstrExpressionTrait::getHashValue(), llvm::AMDGPUInstrInfo::getIndirectIndexBegin(), llvm::RegPressureTracker::getLiveRange(), getMappedReg(), llvm::MachineRegisterInfo::getMaxLaneMaskForVReg(), llvm::PPCInstrInfo::getOperandLatency(), llvm::SIInstrInfo::getOpRegClass(), llvm::ARMBaseInstrInfo::getPartialRegUpdateClearance(), llvm::X86InstrInfo::getPartialRegUpdateClearance(), llvm::VirtRegMap::getPhys(), llvm::SIRegisterInfo::getPhysRegClass(), llvm::MachineRegisterInfo::getRegAllocationHint(), getRegAllocationHints(), llvm::BitTracker::MachineEvaluator::getRegBitWidth(), llvm::MachineRegisterInfo::getSimpleHint(), llvm::VirtRegMap::getStackSlot(), llvm::LiveVariables::getVarInfo(), llvm::VirtRegMap::hasKnownPreference(), hasOnlyLiveInOpers(), hasOnlyLiveOutUses(), llvm::VirtRegMap::hasPreferredPhys(), hasVGPROperands(), hasVirtualRegDefsInBasicBlock(), INITIALIZE_PASS(), llvm::RegPressureTracker::initLiveThru(), llvm::LiveRegSet::insert(), isCVTAToLocalCombinationCandidate(), isFPR64(), isGPR64(), llvm::R600InstrInfo::isLegalToSplitMBBAt(), llvm::SIInstrInfo::isOperandLegal(), isPhysicalRegCopy(), llvm::R600RegisterInfo::isPhysRegLiveAcrossClauses(), isPlainlyKilled(), isVGPR(), llvm::SIInstrInfo::legalizeOperands(), llvm::Mips16InstrInfo::loadImmediate(), llvm::AArch64InstrInfo::loadRegFromStackSlot(), MatchingStackOffset(), llvm::BitTracker::RegisterCell::meet(), llvm::AArch64InstrInfo::optimizeCondBranch(), llvm::PrintReg::print(), llvm::PrintVRegOrUnit::print(), llvm::MachineInstr::print(), printReg(), llvm::ARMBaseInstrInfo::produceSameValue(), llvm::PSetIterator::PSetIterator(), llvm::BitTracker::MachineEvaluator::putCell(), llvm::R600InstrInfo::readsLDSSrcReg(), reassociateOps(), llvm::RegPressureTracker::recede(), regIsPICBase(), regsOverlap(), removeCopies(), llvm::LiveVariables::removeVirtualRegistersKilled(), llvm::LiveIntervals::repairIntervalsInRange(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::ThumbRegisterInfo::saveScavengerRegister(), llvm::RegScavenger::scavengeRegister(), llvm::MachineRegisterInfo::setRegAllocationHint(), llvm::CoalescerPair::setRegisters(), llvm::MachineRegisterInfo::shouldTrackSubRegLiveness(), llvm::LiveIntervals::shrinkToUses(), llvm::MachineBasicBlock::SplitCriticalEdge(), llvm::AArch64InstrInfo::storeRegToStackSlot(), llvm::MachineOperand::substVirtReg(), llvm::LiveIntervals::HMEditor::updateAllRanges(), updateOperand(), llvm::ScheduleDAGMILive::updatePressureDiffs(), llvm::ARMBaseRegisterInfo::updateRegAllocHint(), llvm::SIInstrInfo::usesConstantBus(), llvm::SIInstrInfo::verifyInstruction(), and virtReg2Index().

virtual void llvm::TargetRegisterInfo::materializeFrameBaseRegister ( MachineBasicBlock MBB,
unsigned  BaseReg,
int  FrameIdx,
int64_t  Offset 
) const
inlinevirtual

materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx before insertion point I.

Definition at line 808 of file TargetRegisterInfo.h.

References llvm_unreachable.

virtual bool llvm::TargetRegisterInfo::needsFrameBaseReg ( MachineInstr MI,
int64_t  Offset 
) const
inlinevirtual

needsFrameBaseReg - Returns true if the instruction's frame index reference would be better served by a base register other than FP or SP.

Used by LocalStackFrameAllocation to determine which frame index references it should create new base registers for.

Definition at line 802 of file TargetRegisterInfo.h.

virtual bool llvm::TargetRegisterInfo::needsStackRealignment ( const MachineFunction MF) const
inlinevirtual

needsStackRealignment - true if storage within the function requires the stack pointer to be aligned more than the normal calling convention calls for.

Definition at line 787 of file TargetRegisterInfo.h.

Referenced by llvm::MachineFrameInfo::estimateStackSize(), getMemcpyLoadsAndStores(), llvm::MipsFrameLowering::hasBP(), llvm::MipsFrameLowering::hasFP(), llvm::ARMFrameLowering::hasFP(), and llvm::AArch64FrameLowering::hasFP().

regclass_iterator llvm::TargetRegisterInfo::regclass_begin ( ) const
inline
regclass_iterator llvm::TargetRegisterInfo::regclass_end ( ) const
inline
bool llvm::TargetRegisterInfo::regsOverlap ( unsigned  regA,
unsigned  regB 
) const
inline
virtual bool llvm::TargetRegisterInfo::requiresFrameIndexScavenging ( const MachineFunction MF) const
inlinevirtual

requiresFrameIndexScavenging - returns true if the target requires post PEI scavenging of registers for materializing frame index constants.

Definition at line 756 of file TargetRegisterInfo.h.

virtual bool llvm::TargetRegisterInfo::requiresRegisterScavenging ( const MachineFunction MF) const
inlinevirtual

requiresRegisterScavenging - returns true if the target requires (and can make use of) the register scavenger.

Definition at line 743 of file TargetRegisterInfo.h.

virtual bool llvm::TargetRegisterInfo::requiresVirtualBaseRegisters ( const MachineFunction MF) const
inlinevirtual

requiresVirtualBaseRegisters - Returns true if the target wants the LocalStackAllocation pass to be run and virtual base registers used for more efficient stack access.

Definition at line 763 of file TargetRegisterInfo.h.

virtual void llvm::TargetRegisterInfo::resolveFrameIndex ( MachineInstr MI,
unsigned  BaseReg,
int64_t  Offset 
) const
inlinevirtual

resolveFrameIndex - Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead.

Definition at line 817 of file TargetRegisterInfo.h.

References llvm_unreachable.

virtual bool llvm::TargetRegisterInfo::reverseLocalAssignment ( ) const
inlinevirtual

Allow the target to reverse allocation order of local live ranges.

This will generally allocate shorter local live ranges first. For targets with many registers, this could reduce regalloc compile time by a large factor. It is disabled by default for three reasons: (1) Top-down allocation is simpler and easier to debug for targets that don't benefit from reversing the order. (2) Bottom-up allocation could result in poor evicition decisions on some targets affecting the performance of compiled code. (3) Bottom-up allocation is no longer guaranteed to optimally color.

Definition at line 734 of file TargetRegisterInfo.h.

virtual bool llvm::TargetRegisterInfo::saveScavengerRegister ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
MachineBasicBlock::iterator UseMI,
const TargetRegisterClass RC,
unsigned  Reg 
) const
inlinevirtual

saveScavengerRegister - Spill the register so it can be used by the register scavenger.

Return true if the register was spilled, false otherwise. If this function does not spill the register, the scavenger will instead spill it to the emergency spill slot.

Definition at line 835 of file TargetRegisterInfo.h.

Referenced by llvm::RegScavenger::scavengeRegister().

virtual bool llvm::TargetRegisterInfo::shouldCoalesce ( MachineInstr MI,
const TargetRegisterClass SrcRC,
unsigned  SubReg,
const TargetRegisterClass DstRC,
unsigned  DstSubReg,
const TargetRegisterClass NewRC 
) const
inlinevirtual

Subtarget Hooks.

SrcRC and DstRC will be morphed into NewRC if this returns true.

Definition at line 858 of file TargetRegisterInfo.h.

static int llvm::TargetRegisterInfo::stackSlot2Index ( unsigned  Reg)
inlinestatic

stackSlot2Index - Compute the frame index from a register value representing a stack slot.

Definition at line 275 of file TargetRegisterInfo.h.

References isStackSlot().

Referenced by llvm::PrintReg::print().

virtual bool llvm::TargetRegisterInfo::trackLivenessAfterRegAlloc ( const MachineFunction MF) const
inlinevirtual

trackLivenessAfterRegAlloc - returns true if the live-ins should be tracked after register allocation.

Definition at line 780 of file TargetRegisterInfo.h.

Referenced by llvm::BranchFolder::OptimizeFunction().

virtual void llvm::TargetRegisterInfo::updateRegAllocHint ( unsigned  Reg,
unsigned  NewReg,
MachineFunction MF 
) const
inlinevirtual

updateRegAllocHint - A callback to allow target a chance to update register allocation hints when a register is "changed" (e.g.

coalesced) to another register. e.g. On ARM, some virtual registers should target register pairs, if one of pair is coalesced to another register, the allocation hint of the other half of the pair should be changed to point to the new register.

Definition at line 720 of file TargetRegisterInfo.h.

virtual bool llvm::TargetRegisterInfo::useFPForScavengingIndex ( const MachineFunction MF) const
inlinevirtual

useFPForScavengingIndex - returns true if the target wants to use frame pointer based accesses to spill to the scavenger emergency spill slot.

Definition at line 750 of file TargetRegisterInfo.h.

static unsigned llvm::TargetRegisterInfo::virtReg2Index ( unsigned  Reg)
inlinestatic

virtReg2Index - Convert a virtual register number to a 0-based index.

The first virtual register in a function will get the index 0.

Definition at line 303 of file TargetRegisterInfo.h.

References isVirtualRegister().

Referenced by llvm::VReg2SUnit::getSparseSetIndex(), llvm::VirtReg2IndexFunctor::operator()(), llvm::PrintReg::print(), llvm::PrintVRegOrUnit::print(), printReg(), and llvm::SelectionDAGISel::runOnMachineFunction().


The documentation for this class was generated from the following files: