LLVM  3.7.0
PPCVSXFMAMutate.cpp
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1 //===--------------- PPCVSXFMAMutate.cpp - VSX FMA Mutation ---------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This pass mutates the form of VSX FMA instructions to avoid unnecessary
11 // copies.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "PPCInstrInfo.h"
17 #include "PPC.h"
18 #include "PPCInstrBuilder.h"
19 #include "PPCMachineFunctionInfo.h"
20 #include "PPCTargetMachine.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/Statistic.h"
32 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/Support/Debug.h"
38 
39 using namespace llvm;
40 
41 static cl::opt<bool> DisableVSXFMAMutate("disable-ppc-vsx-fma-mutation",
42 cl::desc("Disable VSX FMA instruction mutation"), cl::Hidden);
43 
44 #define DEBUG_TYPE "ppc-vsx-fma-mutate"
45 
46 namespace llvm { namespace PPC {
47  int getAltVSXFMAOpcode(uint16_t Opcode);
48 } }
49 
50 namespace {
51  // PPCVSXFMAMutate pass - For copies between VSX registers and non-VSX registers
52  // (Altivec and scalar floating-point registers), we need to transform the
53  // copies into subregister copies with other restrictions.
54  struct PPCVSXFMAMutate : public MachineFunctionPass {
55  static char ID;
56  PPCVSXFMAMutate() : MachineFunctionPass(ID) {
58  }
59 
60  LiveIntervals *LIS;
61  const PPCInstrInfo *TII;
62 
63 protected:
64  bool processBlock(MachineBasicBlock &MBB) {
65  bool Changed = false;
66 
68  const TargetRegisterInfo *TRI = &TII->getRegisterInfo();
69  for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
70  I != IE; ++I) {
71  MachineInstr *MI = I;
72 
73  // The default (A-type) VSX FMA form kills the addend (it is taken from
74  // the target register, which is then updated to reflect the result of
75  // the FMA). If the instruction, however, kills one of the registers
76  // used for the product, then we can use the M-form instruction (which
77  // will take that value from the to-be-defined register).
78 
79  int AltOpc = PPC::getAltVSXFMAOpcode(MI->getOpcode());
80  if (AltOpc == -1)
81  continue;
82 
83  // This pass is run after register coalescing, and so we're looking for
84  // a situation like this:
85  // ...
86  // %vreg5<def> = COPY %vreg9; VSLRC:%vreg5,%vreg9
87  // %vreg5<def,tied1> = XSMADDADP %vreg5<tied0>, %vreg17, %vreg16,
88  // %RM<imp-use>; VSLRC:%vreg5,%vreg17,%vreg16
89  // ...
90  // %vreg9<def,tied1> = XSMADDADP %vreg9<tied0>, %vreg17, %vreg19,
91  // %RM<imp-use>; VSLRC:%vreg9,%vreg17,%vreg19
92  // ...
93  // Where we can eliminate the copy by changing from the A-type to the
94  // M-type instruction. Specifically, for this example, this means:
95  // %vreg5<def,tied1> = XSMADDADP %vreg5<tied0>, %vreg17, %vreg16,
96  // %RM<imp-use>; VSLRC:%vreg5,%vreg17,%vreg16
97  // is replaced by:
98  // %vreg16<def,tied1> = XSMADDMDP %vreg16<tied0>, %vreg18, %vreg9,
99  // %RM<imp-use>; VSLRC:%vreg16,%vreg18,%vreg9
100  // and we remove: %vreg5<def> = COPY %vreg9; VSLRC:%vreg5,%vreg9
101 
102  SlotIndex FMAIdx = LIS->getInstructionIndex(MI);
103 
104  VNInfo *AddendValNo =
105  LIS->getInterval(MI->getOperand(1).getReg()).Query(FMAIdx).valueIn();
106  MachineInstr *AddendMI = LIS->getInstructionFromIndex(AddendValNo->def);
107 
108  // The addend and this instruction must be in the same block.
109 
110  if (!AddendMI || AddendMI->getParent() != MI->getParent())
111  continue;
112 
113  // The addend must be a full copy within the same register class.
114 
115  if (!AddendMI->isFullCopy())
116  continue;
117 
118  unsigned AddendSrcReg = AddendMI->getOperand(1).getReg();
119  if (TargetRegisterInfo::isVirtualRegister(AddendSrcReg)) {
120  if (MRI.getRegClass(AddendMI->getOperand(0).getReg()) !=
121  MRI.getRegClass(AddendSrcReg))
122  continue;
123  } else {
124  // If AddendSrcReg is a physical register, make sure the destination
125  // register class contains it.
126  if (!MRI.getRegClass(AddendMI->getOperand(0).getReg())
127  ->contains(AddendSrcReg))
128  continue;
129  }
130 
131  // In theory, there could be other uses of the addend copy before this
132  // fma. We could deal with this, but that would require additional
133  // logic below and I suspect it will not occur in any relevant
134  // situations. Additionally, check whether the copy source is killed
135  // prior to the fma. In order to replace the addend here with the
136  // source of the copy, it must still be live here. We can't use
137  // interval testing for a physical register, so as long as we're
138  // walking the MIs we may as well test liveness here.
139  //
140  // FIXME: There is a case that occurs in practice, like this:
141  // %vreg9<def> = COPY %F1; VSSRC:%vreg9
142  // ...
143  // %vreg6<def> = COPY %vreg9; VSSRC:%vreg6,%vreg9
144  // %vreg7<def> = COPY %vreg9; VSSRC:%vreg7,%vreg9
145  // %vreg9<def,tied1> = XSMADDASP %vreg9<tied0>, %vreg1, %vreg4; VSSRC:
146  // %vreg6<def,tied1> = XSMADDASP %vreg6<tied0>, %vreg1, %vreg2; VSSRC:
147  // %vreg7<def,tied1> = XSMADDASP %vreg7<tied0>, %vreg1, %vreg3; VSSRC:
148  // which prevents an otherwise-profitable transformation.
149  bool OtherUsers = false, KillsAddendSrc = false;
150  for (auto J = std::prev(I), JE = MachineBasicBlock::iterator(AddendMI);
151  J != JE; --J) {
152  if (J->readsVirtualRegister(AddendMI->getOperand(0).getReg())) {
153  OtherUsers = true;
154  break;
155  }
156  if (J->modifiesRegister(AddendSrcReg, TRI) ||
157  J->killsRegister(AddendSrcReg, TRI)) {
158  KillsAddendSrc = true;
159  break;
160  }
161  }
162 
163  if (OtherUsers || KillsAddendSrc)
164  continue;
165 
166  // Find one of the product operands that is killed by this instruction.
167 
168  unsigned KilledProdOp = 0, OtherProdOp = 0;
169  if (LIS->getInterval(MI->getOperand(2).getReg())
170  .Query(FMAIdx).isKill()) {
171  KilledProdOp = 2;
172  OtherProdOp = 3;
173  } else if (LIS->getInterval(MI->getOperand(3).getReg())
174  .Query(FMAIdx).isKill()) {
175  KilledProdOp = 3;
176  OtherProdOp = 2;
177  }
178 
179  // If there are no killed product operands, then this transformation is
180  // likely not profitable.
181  if (!KilledProdOp)
182  continue;
183 
184  // For virtual registers, verify that the addend source register
185  // is live here (as should have been assured above).
186  assert((!TargetRegisterInfo::isVirtualRegister(AddendSrcReg) ||
187  LIS->getInterval(AddendSrcReg).liveAt(FMAIdx)) &&
188  "Addend source register is not live!");
189 
190  // Transform: (O2 * O3) + O1 -> (O2 * O1) + O3.
191 
192  unsigned AddReg = AddendMI->getOperand(1).getReg();
193  unsigned KilledProdReg = MI->getOperand(KilledProdOp).getReg();
194  unsigned OtherProdReg = MI->getOperand(OtherProdOp).getReg();
195 
196  unsigned AddSubReg = AddendMI->getOperand(1).getSubReg();
197  unsigned KilledProdSubReg = MI->getOperand(KilledProdOp).getSubReg();
198  unsigned OtherProdSubReg = MI->getOperand(OtherProdOp).getSubReg();
199 
200  bool AddRegKill = AddendMI->getOperand(1).isKill();
201  bool KilledProdRegKill = MI->getOperand(KilledProdOp).isKill();
202  bool OtherProdRegKill = MI->getOperand(OtherProdOp).isKill();
203 
204  bool AddRegUndef = AddendMI->getOperand(1).isUndef();
205  bool KilledProdRegUndef = MI->getOperand(KilledProdOp).isUndef();
206  bool OtherProdRegUndef = MI->getOperand(OtherProdOp).isUndef();
207 
208  unsigned OldFMAReg = MI->getOperand(0).getReg();
209 
210  // The transformation doesn't work well with things like:
211  // %vreg5 = A-form-op %vreg5, %vreg11, %vreg5;
212  // so leave such things alone.
213  if (OldFMAReg == KilledProdReg)
214  continue;
215 
216  assert(OldFMAReg == AddendMI->getOperand(0).getReg() &&
217  "Addend copy not tied to old FMA output!");
218 
219  DEBUG(dbgs() << "VSX FMA Mutation:\n " << *MI;);
220 
221  MI->getOperand(0).setReg(KilledProdReg);
222  MI->getOperand(1).setReg(KilledProdReg);
223  MI->getOperand(3).setReg(AddReg);
224  MI->getOperand(2).setReg(OtherProdReg);
225 
226  MI->getOperand(0).setSubReg(KilledProdSubReg);
227  MI->getOperand(1).setSubReg(KilledProdSubReg);
228  MI->getOperand(3).setSubReg(AddSubReg);
229  MI->getOperand(2).setSubReg(OtherProdSubReg);
230 
231  MI->getOperand(1).setIsKill(KilledProdRegKill);
232  MI->getOperand(3).setIsKill(AddRegKill);
233  MI->getOperand(2).setIsKill(OtherProdRegKill);
234 
235  MI->getOperand(1).setIsUndef(KilledProdRegUndef);
236  MI->getOperand(3).setIsUndef(AddRegUndef);
237  MI->getOperand(2).setIsUndef(OtherProdRegUndef);
238 
239  MI->setDesc(TII->get(AltOpc));
240 
241  DEBUG(dbgs() << " -> " << *MI);
242 
243  // The killed product operand was killed here, so we can reuse it now
244  // for the result of the fma.
245 
246  LiveInterval &FMAInt = LIS->getInterval(OldFMAReg);
247  VNInfo *FMAValNo = FMAInt.getVNInfoAt(FMAIdx.getRegSlot());
248  for (auto UI = MRI.reg_nodbg_begin(OldFMAReg), UE = MRI.reg_nodbg_end();
249  UI != UE;) {
250  MachineOperand &UseMO = *UI;
251  MachineInstr *UseMI = UseMO.getParent();
252  ++UI;
253 
254  // Don't replace the result register of the copy we're about to erase.
255  if (UseMI == AddendMI)
256  continue;
257 
258  UseMO.setReg(KilledProdReg);
259  UseMO.setSubReg(KilledProdSubReg);
260  }
261 
262  // Extend the live intervals of the killed product operand to hold the
263  // fma result.
264 
265  LiveInterval &NewFMAInt = LIS->getInterval(KilledProdReg);
266  for (LiveInterval::iterator AI = FMAInt.begin(), AE = FMAInt.end();
267  AI != AE; ++AI) {
268  // Don't add the segment that corresponds to the original copy.
269  if (AI->valno == AddendValNo)
270  continue;
271 
272  VNInfo *NewFMAValNo =
273  NewFMAInt.getNextValue(AI->start,
274  LIS->getVNInfoAllocator());
275 
276  NewFMAInt.addSegment(LiveInterval::Segment(AI->start, AI->end,
277  NewFMAValNo));
278  }
279  DEBUG(dbgs() << " extended: " << NewFMAInt << '\n');
280 
281  FMAInt.removeValNo(FMAValNo);
282  DEBUG(dbgs() << " trimmed: " << FMAInt << '\n');
283 
284  // Remove the (now unused) copy.
285 
286  DEBUG(dbgs() << " removing: " << *AddendMI << '\n');
287  LIS->RemoveMachineInstrFromMaps(AddendMI);
288  AddendMI->eraseFromParent();
289 
290  Changed = true;
291  }
292 
293  return Changed;
294  }
295 
296 public:
297  bool runOnMachineFunction(MachineFunction &MF) override {
298  // If we don't have VSX then go ahead and return without doing
299  // anything.
300  const PPCSubtarget &STI = MF.getSubtarget<PPCSubtarget>();
301  if (!STI.hasVSX())
302  return false;
303 
304  LIS = &getAnalysis<LiveIntervals>();
305 
306  TII = STI.getInstrInfo();
307 
308  bool Changed = false;
309 
311  return Changed;
312 
313  for (MachineFunction::iterator I = MF.begin(); I != MF.end();) {
314  MachineBasicBlock &B = *I++;
315  if (processBlock(B))
316  Changed = true;
317  }
318 
319  return Changed;
320  }
321 
322  void getAnalysisUsage(AnalysisUsage &AU) const override {
325  AU.addRequired<SlotIndexes>();
328  }
329  };
330 }
331 
332 INITIALIZE_PASS_BEGIN(PPCVSXFMAMutate, DEBUG_TYPE,
333  "PowerPC VSX FMA Mutation", false, false)
337  "PowerPC VSX FMA Mutation", false, false)
338 
339 char &llvm::PPCVSXFMAMutateID = PPCVSXFMAMutate::ID;
340 
341 char PPCVSXFMAMutate::ID = 0;
343 llvm::createPPCVSXFMAMutatePass() { return new PPCVSXFMAMutate(); }
344 
345 
bool isFullCopy() const
Definition: MachineInstr.h:781
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Segments::iterator iterator
Definition: LiveInterval.h:204
SlotIndex def
The index of the defining instruction.
Definition: LiveInterval.h:53
FunctionPass * createPPCVSXFMAMutatePass()
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:588
void setIsUndef(bool Val=true)
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
char & PPCVSXFMAMutateID
VNInfo - Value Number Information.
Definition: LiveInterval.h:45
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
Definition: LiveInterval.h:392
static const MachineInstrBuilder & AddSubReg(const MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI)
AnalysisUsage & addRequired()
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:70
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
iterator end()
Definition: LiveInterval.h:206
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:75
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
const TargetRegisterClass * getRegClass(unsigned Reg) const
getRegClass - Return the register class of the specified virtual register.
bool isUndef() const
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Definition: Value.cpp:317
PowerPC VSX FMA Mutation
const HexagonRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
bool isKill() const
SlotIndexes pass.
Definition: SlotIndexes.h:334
iterator addSegment(Segment S)
Add the specified Segment to this range, merging segments as appropriate.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:267
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:120
bundle_iterator< MachineInstr, instr_iterator > iterator
void removeValNo(VNInfo *ValNo)
removeValNo - Remove all the segments defined by the specified value#.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
int getAltVSXFMAOpcode(uint16_t Opcode)
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
void initializePPCVSXFMAMutatePass(PassRegistry &)
Represent the analysis usage information of a pass.
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:294
#define DEBUG_TYPE
unsigned getSubReg() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void setIsKill(bool Val=true)
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
const PPCInstrInfo * getInstrInfo() const override
Definition: PPCSubtarget.h:163
MachineOperand class - Representation of each machine instruction operand.
static cl::opt< bool > DisableVSXFMAMutate("disable-ppc-vsx-fma-mutation", cl::desc("Disable VSX FMA instruction mutation"), cl::Hidden)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:123
PowerPC VSX FMA false
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
INITIALIZE_PASS_BEGIN(PPCVSXFMAMutate, DEBUG_TYPE,"PowerPC VSX FMA Mutation", false, false) INITIALIZE_PASS_END(PPCVSXFMAMutate
Representation of each machine instruction.
Definition: MachineInstr.h:51
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
void setReg(unsigned Reg)
Change the register this operand corresponds to.
#define I(x, y, z)
Definition: MD5.cpp:54
void setSubReg(unsigned subReg)
bool hasVSX() const
Definition: PPCSubtarget.h:224
static reg_nodbg_iterator reg_nodbg_end()
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def...
Definition: SlotIndexes.h:257
iterator begin()
Definition: LiveInterval.h:205
unsigned getReg() const
getReg - Returns the register number.
VNInfo * getNextValue(SlotIndex def, VNInfo::Allocator &VNInfoAllocator)
getNextValue - Create a new value number and return it.
Definition: LiveInterval.h:306
FMA - Perform a * b + c with no intermediate rounding step.
Definition: ISDOpcodes.h:240
BasicBlockListType::iterator iterator
#define DEBUG(X)
Definition: Debug.h:92
reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:92