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LLVM
3.7.0
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#include "Hexagon.h"#include "MCTargetDesc/HexagonBaseInfo.h"#include "MCTargetDesc/HexagonMCInstrInfo.h"#include "MCTargetDesc/HexagonMCTargetDesc.h"#include "llvm/MC/MCContext.h"#include "llvm/MC/MCDisassembler.h"#include "llvm/MC/MCExpr.h"#include "llvm/MC/MCFixedLenDisassembler.h"#include "llvm/MC/MCInst.h"#include "llvm/MC/MCInstrDesc.h"#include "llvm/MC/MCSubtargetInfo.h"#include "llvm/Support/Debug.h"#include "llvm/Support/Endian.h"#include "llvm/Support/ErrorHandling.h"#include "llvm/Support/LEB128.h"#include "llvm/Support/TargetRegistry.h"#include "llvm/Support/raw_ostream.h"#include <array>#include <vector>#include "HexagonGenDisassemblerTables.inc"Go to the source code of this file.
Macros | |
| #define | DEBUG_TYPE "hexagon-disassembler" |
Typedefs | |
| typedef llvm::MCDisassembler::DecodeStatus | DecodeStatus |
Functions | |
| static DecodeStatus | DecodeModRegsRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeCtrRegsRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeCtrRegs64RegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, void const *Decoder) |
| static unsigned | GetSubinstOpcode (unsigned IClass, unsigned inst, unsigned &op, raw_ostream &os) |
| static void | AddSubinstOperands (MCInst *MI, unsigned opcode, unsigned inst) |
| static DecodeStatus | s16ImmDecoder (MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder) |
| static DecodeStatus | s12ImmDecoder (MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder) |
| static DecodeStatus | s11_0ImmDecoder (MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder) |
| static DecodeStatus | s11_1ImmDecoder (MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder) |
| static DecodeStatus | s11_2ImmDecoder (MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder) |
| static DecodeStatus | s11_3ImmDecoder (MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder) |
| static DecodeStatus | s10ImmDecoder (MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder) |
| static DecodeStatus | s8ImmDecoder (MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder) |
| static DecodeStatus | s6_0ImmDecoder (MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder) |
| static DecodeStatus | s4_0ImmDecoder (MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder) |
| static DecodeStatus | s4_1ImmDecoder (MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder) |
| static DecodeStatus | s4_2ImmDecoder (MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder) |
| static DecodeStatus | s4_3ImmDecoder (MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeRegisterClass (MCInst &Inst, unsigned RegNo, const uint16_t Table[], size_t Size) |
| static DecodeStatus | DecodeIntRegsRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t, void const *Decoder) |
| static DecodeStatus | DecodeDoubleRegsRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t, const void *Decoder) |
| static DecodeStatus | DecodePredRegsRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t, void const *Decoder) |
| static MCDisassembler * | createHexagonDisassembler (Target const &T, MCSubtargetInfo const &STI, MCContext &Ctx) |
| void | LLVMInitializeHexagonDisassembler () |
| static unsigned | getRegFromSubinstEncoding (unsigned encoded_reg) |
| static unsigned | getDRegFromSubinstEncoding (unsigned encoded_dreg) |
Variables | |
| static const uint16_t | IntRegDecoderTable [] |
| static const uint16_t | PredRegDecoderTable [] |
| #define DEBUG_TYPE "hexagon-disassembler" |
Definition at line 34 of file HexagonDisassembler.cpp.
Definition at line 37 of file HexagonDisassembler.cpp.
| enum subInstBinaryValues |
Definition at line 478 of file HexagonDisassembler.cpp.
Definition at line 745 of file HexagonDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), getDRegFromSubinstEncoding(), and getRegFromSubinstEncoding().
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Definition at line 217 of file HexagonDisassembler.cpp.
Referenced by LLVMInitializeHexagonDisassembler().
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Definition at line 151 of file HexagonDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, Register, and llvm::MCDisassembler::Success.
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Definition at line 131 of file HexagonDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, Register, and llvm::MCDisassembler::Success.
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Definition at line 191 of file HexagonDisassembler.cpp.
References DecodeRegisterClass().
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Definition at line 120 of file HexagonDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, IntRegDecoderTable, Register, and llvm::MCDisassembler::Success.
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Definition at line 173 of file HexagonDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, Register, and llvm::MCDisassembler::Success.
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Definition at line 204 of file HexagonDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, PredRegDecoderTable, Register, and llvm::MCDisassembler::Success.
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Definition at line 111 of file HexagonDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, and llvm::MCDisassembler::Success.
Referenced by DecodeDoubleRegsRegisterClass().
Definition at line 737 of file HexagonDisassembler.cpp.
Referenced by AddSubinstOperands().
Definition at line 729 of file HexagonDisassembler.cpp.
Referenced by AddSubinstOperands().
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Definition at line 585 of file HexagonDisassembler.cpp.
References llvm::MCDisassembler::Fail, llvm::HexagonII::HSIG_A, llvm::HexagonII::HSIG_L1, llvm::HexagonII::HSIG_L2, llvm::HexagonII::HSIG_S1, llvm::HexagonII::HSIG_S2, llvm::MCDisassembler::Success, V4_SA1_addi_BITS, V4_SA1_addi_MASK, V4_SA1_addrx_BITS, V4_SA1_addrx_MASK, V4_SA1_addsp_BITS, V4_SA1_addsp_MASK, V4_SA1_and1_BITS, V4_SA1_and1_MASK, V4_SA1_clrf_BITS, V4_SA1_clrf_MASK, V4_SA1_clrfnew_BITS, V4_SA1_clrfnew_MASK, V4_SA1_clrt_BITS, V4_SA1_clrt_MASK, V4_SA1_clrtnew_BITS, V4_SA1_clrtnew_MASK, V4_SA1_cmpeqi_BITS, V4_SA1_cmpeqi_MASK, V4_SA1_combine0i_BITS, V4_SA1_combine0i_MASK, V4_SA1_combine1i_BITS, V4_SA1_combine1i_MASK, V4_SA1_combine2i_BITS, V4_SA1_combine2i_MASK, V4_SA1_combine3i_BITS, V4_SA1_combine3i_MASK, V4_SA1_combinerz_BITS, V4_SA1_combinerz_MASK, V4_SA1_combinezr_BITS, V4_SA1_combinezr_MASK, V4_SA1_dec_BITS, V4_SA1_dec_MASK, V4_SA1_inc_BITS, V4_SA1_inc_MASK, V4_SA1_seti_BITS, V4_SA1_seti_MASK, V4_SA1_setin1_BITS, V4_SA1_setin1_MASK, V4_SA1_sxtb_BITS, V4_SA1_sxtb_MASK, V4_SA1_sxth_BITS, V4_SA1_sxth_MASK, V4_SA1_tfr_BITS, V4_SA1_tfr_MASK, V4_SA1_zxtb_BITS, V4_SA1_zxtb_MASK, V4_SA1_zxth_BITS, V4_SA1_zxth_MASK, V4_SL1_loadri_io_BITS, V4_SL1_loadri_io_MASK, V4_SL1_loadrub_io_BITS, V4_SL1_loadrub_io_MASK, V4_SL2_deallocframe_BITS, V4_SL2_deallocframe_MASK, V4_SL2_jumpr31_BITS, V4_SL2_jumpr31_f_BITS, V4_SL2_jumpr31_f_MASK, V4_SL2_jumpr31_fnew_BITS, V4_SL2_jumpr31_fnew_MASK, V4_SL2_jumpr31_MASK, V4_SL2_jumpr31_t_BITS, V4_SL2_jumpr31_t_MASK, V4_SL2_jumpr31_tnew_BITS, V4_SL2_jumpr31_tnew_MASK, V4_SL2_loadrb_io_BITS, V4_SL2_loadrb_io_MASK, V4_SL2_loadrd_sp_BITS, V4_SL2_loadrd_sp_MASK, V4_SL2_loadrh_io_BITS, V4_SL2_loadrh_io_MASK, V4_SL2_loadri_sp_BITS, V4_SL2_loadri_sp_MASK, V4_SL2_loadruh_io_BITS, V4_SL2_loadruh_io_MASK, V4_SL2_return_BITS, V4_SL2_return_f_BITS, V4_SL2_return_f_MASK, V4_SL2_return_fnew_BITS, V4_SL2_return_fnew_MASK, V4_SL2_return_MASK, V4_SL2_return_t_BITS, V4_SL2_return_t_MASK, V4_SL2_return_tnew_BITS, V4_SL2_return_tnew_MASK, V4_SS1_storeb_io_BITS, V4_SS1_storeb_io_MASK, V4_SS1_storew_io_BITS, V4_SS1_storew_io_MASK, V4_SS2_allocframe_BITS, V4_SS2_allocframe_MASK, V4_SS2_storebi0_BITS, V4_SS2_storebi0_MASK, V4_SS2_storebi1_BITS, V4_SS2_storebi1_MASK, V4_SS2_stored_sp_BITS, V4_SS2_stored_sp_MASK, V4_SS2_storeh_io_BITS, V4_SS2_storeh_io_MASK, V4_SS2_storew_sp_BITS, V4_SS2_storew_sp_MASK, V4_SS2_storewi0_BITS, V4_SS2_storewi0_MASK, V4_SS2_storewi1_BITS, and V4_SS2_storewi1_MASK.
| void LLVMInitializeHexagonDisassembler | ( | ) |
Definition at line 223 of file HexagonDisassembler.cpp.
References createHexagonDisassembler(), llvm::TargetRegistry::RegisterMCDisassembler(), and llvm::TheHexagonTarget.
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Definition at line 428 of file HexagonDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), and llvm::MCDisassembler::Success.
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Definition at line 400 of file HexagonDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), and llvm::MCDisassembler::Success.
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Definition at line 407 of file HexagonDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), and llvm::MCDisassembler::Success.
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Definition at line 414 of file HexagonDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), and llvm::MCDisassembler::Success.
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Definition at line 421 of file HexagonDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), and llvm::MCDisassembler::Success.
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Definition at line 393 of file HexagonDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), and llvm::MCDisassembler::Success.
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Definition at line 386 of file HexagonDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), and llvm::MCDisassembler::Success.
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Definition at line 449 of file HexagonDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), and llvm::MCDisassembler::Success.
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Definition at line 456 of file HexagonDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), and llvm::MCDisassembler::Success.
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Definition at line 463 of file HexagonDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), and llvm::MCDisassembler::Success.
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Definition at line 470 of file HexagonDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), and llvm::MCDisassembler::Success.
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Definition at line 442 of file HexagonDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), and llvm::MCDisassembler::Success.
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Definition at line 435 of file HexagonDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), and llvm::MCDisassembler::Success.
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Definition at line 99 of file HexagonDisassembler.cpp.
Referenced by DecodeIntRegsRegisterClass().
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Definition at line 108 of file HexagonDisassembler.cpp.
Referenced by DecodePredRegsRegisterClass().
1.8.6