34 R600MCCodeEmitter(
const R600MCCodeEmitter &) =
delete;
35 void operator=(
const R600MCCodeEmitter &) =
delete;
42 : MCII(mcii), MRI(mri) { }
55 void EmitByte(
unsigned int byte,
raw_ostream &OS)
const;
60 unsigned getHWRegChan(
unsigned reg)
const;
61 unsigned getHWReg(
unsigned regNo)
const;
87 return new R600MCCodeEmitter(MCII, MRI);
100 }
else if (
IS_VTX(Desc)) {
101 uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups, STI);
104 InstWord2 |= 1 << 19;
107 Emit(InstWord01, OS);
109 Emit((uint32_t) 0, OS);
110 }
else if (
IS_TEX(Desc)) {
113 int64_t SrcSelect[4] = {
125 uint64_t Word01 = getBinaryCodeForInstr(MI, Fixups, STI);
126 uint32_t Word2 = Sampler << 15 | SrcSelect[
ELEMENT_X] << 20 |
128 SrcSelect[
ELEMENT_W] << 29 | Offsets[0] << 0 | Offsets[1] << 5 |
133 Emit((uint32_t) 0, OS);
135 uint64_t Inst = getBinaryCodeForInstr(MI, Fixups, STI);
139 uint64_t ISAOpCode = Inst & (0x3FFULL << 39);
140 Inst &= ~(0x3FFULL << 39);
141 Inst |= ISAOpCode << 1;
147 void R600MCCodeEmitter::EmitByte(
unsigned int Byte,
raw_ostream &OS)
const {
148 OS.
write((uint8_t) Byte & 0xff);
159 unsigned R600MCCodeEmitter::getHWRegChan(
unsigned reg)
const {
163 unsigned R600MCCodeEmitter::getHWReg(
unsigned RegNo)
const {
167 uint64_t R600MCCodeEmitter::getMachineOpValue(
const MCInst &MI,
173 return MRI.getEncodingValue(MO.
getReg());
174 return getHWReg(MO.
getReg());
181 #include "AMDGPUGenMCCodeEmitter.inc"
Describe properties that are true of each instruction in the target description file.
MCCodeEmitter * createR600MCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
#define HAS_NATIVE_OPERANDS(Flags)
Context object for machine code objects.
unsigned getReg() const
Returns the register number.
Instances of this class represent a single low-level machine instruction.
#define HW_REG_MASK
Defines for extracting register information from register encoding.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
MCCodeEmitter - Generic instruction encoding interface.
Interface to description of machine instruction set.
raw_ostream & write(unsigned char C)
PowerPC TLS Dynamic Call Fixup
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
BUNDLE - This instruction represents an instruction bundle.
unsigned getOpcode() const
KILL - This instruction is a noop that is used only to adjust the liveness of registers.
void write(void *memory, value_type value)
Write a value to memory with a particular endianness.
Provides AMDGPU specific target descriptions.
Adapter to write values to a stream in a particular byte order.
MCSubtargetInfo - Generic base class for all target subtargets.
CodeEmitter interface for R600 and SI codegen.
LLVM Value Representation.
This class implements an extremely fast bulk output stream that can only output to a stream...
Instances of this class represent operands of the MCInst class.
const MCOperand & getOperand(unsigned i) const