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LLVM
3.7.0
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#include "AArch64TargetMachine.h"#include "MCTargetDesc/AArch64AddressingModes.h"#include "llvm/ADT/APSInt.h"#include "llvm/CodeGen/SelectionDAGISel.h"#include "llvm/IR/Function.h"#include "llvm/IR/GlobalValue.h"#include "llvm/IR/Intrinsics.h"#include "llvm/Support/Debug.h"#include "llvm/Support/ErrorHandling.h"#include "llvm/Support/MathExtras.h"#include "llvm/Support/raw_ostream.h"#include "AArch64GenDAGISel.inc"Go to the source code of this file.
Macros | |
| #define | DEBUG_TYPE "aarch64-isel" |
Functions | |
| static bool | isIntImmediate (const SDNode *N, uint64_t &Imm) |
| isIntImmediate - This method tests to see if the node is a constant operand. More... | |
| static bool | isIntImmediate (SDValue N, uint64_t &Imm) |
| static bool | isOpcWithIntImmediate (const SDNode *N, unsigned Opc, uint64_t &Imm) |
| static AArch64_AM::ShiftExtendType | getShiftTypeForNode (SDValue N) |
| getShiftTypeForNode - Translate a shift node to the corresponding ShiftType value. More... | |
| static AArch64_AM::ShiftExtendType | getExtendTypeForNode (SDValue N, bool IsLoadStore=false) |
| getExtendTypeForNode - Translate an extend node to the corresponding ExtendType value. More... | |
| static bool | checkHighLaneIndex (SDNode *DL, SDValue &LaneOp, int &LaneIdx) |
| static bool | checkV64LaneV128 (SDValue Op0, SDValue Op1, SDValue &StdOp, SDValue &LaneOp, int &LaneIdx) |
| static SDValue | narrowIfNeeded (SelectionDAG *CurDAG, SDValue N) |
| Instructions that accept extend modifiers like UXTW expect the register being extended to be a GPR32, but the incoming DAG might be acting on a GPR64 (either via SEXT_INREG or AND). More... | |
| static bool | isWorthFoldingADDlow (SDValue N) |
| If there's a use of this ADDlow that's not itself a load/store then we'll need to create a real ADD instruction from it anyway and there's no point in folding it into the mem op. More... | |
| static SDValue | Widen (SelectionDAG *CurDAG, SDValue N) |
| static bool | isPreferredADD (int64_t ImmOff) |
| static SDValue | NarrowVector (SDValue V128Reg, SelectionDAG &DAG) |
| NarrowVector - Given a value in the V128 register class, produce the equivalent value in the V64 register class. More... | |
| static bool | isBitfieldExtractOpFromAnd (SelectionDAG *CurDAG, SDNode *N, unsigned &Opc, SDValue &Opd0, unsigned &LSB, unsigned &MSB, unsigned NumberOfIgnoredLowBits, bool BiggerPattern) |
| static bool | isSeveralBitsExtractOpFromShr (SDNode *N, unsigned &Opc, SDValue &Opd0, unsigned &LSB, unsigned &MSB) |
| static bool | isBitfieldExtractOpFromShr (SDNode *N, unsigned &Opc, SDValue &Opd0, unsigned &Immr, unsigned &Imms, bool BiggerPattern) |
| static bool | isBitfieldExtractOp (SelectionDAG *CurDAG, SDNode *N, unsigned &Opc, SDValue &Opd0, unsigned &Immr, unsigned &Imms, unsigned NumberOfIgnoredLowBits=0, bool BiggerPattern=false) |
| static bool | isBitfieldDstMask (uint64_t DstMask, APInt BitsToBeInserted, unsigned NumberOfIgnoredHighBits, EVT VT) |
| Does DstMask form a complementary pair with the mask provided by BitsToBeInserted, suitable for use in a BFI instruction. More... | |
| static void | getUsefulBits (SDValue Op, APInt &UsefulBits, unsigned Depth=0) |
| static void | getUsefulBitsFromAndWithImmediate (SDValue Op, APInt &UsefulBits, unsigned Depth) |
| static void | getUsefulBitsFromBitfieldMoveOpd (SDValue Op, APInt &UsefulBits, uint64_t Imm, uint64_t MSB, unsigned Depth) |
| static void | getUsefulBitsFromUBFM (SDValue Op, APInt &UsefulBits, unsigned Depth) |
| static void | getUsefulBitsFromOrWithShiftedReg (SDValue Op, APInt &UsefulBits, unsigned Depth) |
| static void | getUsefulBitsFromBFM (SDValue Op, SDValue Orig, APInt &UsefulBits, unsigned Depth) |
| static void | getUsefulBitsForUse (SDNode *UserNode, APInt &UsefulBits, SDValue Orig, unsigned Depth) |
| static SDValue | getLeftShift (SelectionDAG *CurDAG, SDValue Op, int ShlAmount) |
| Create a machine node performing a notional SHL of Op by ShlAmount. More... | |
| static bool | isBitfieldPositioningOp (SelectionDAG *CurDAG, SDValue Op, SDValue &Src, int &ShiftAmount, int &MaskWidth) |
| Does this tree qualify as an attempt to move a bitfield into position, essentially "(and (shl VAL, N), Mask)". More... | |
| static bool | isBitfieldInsertOpFromOr (SDNode *N, unsigned &Opc, SDValue &Dst, SDValue &Src, unsigned &ImmR, unsigned &ImmS, SelectionDAG *CurDAG) |
| static int | getIntOperandFromRegisterString (StringRef RegString) |
| #define DEBUG_TYPE "aarch64-isel" |
Definition at line 28 of file AArch64ISelDAGToDAG.cpp.
Definition at line 404 of file AArch64ISelDAGToDAG.cpp.
References llvm::AArch64ISD::DUPLANE16, llvm::AArch64ISD::DUPLANE32, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::ConstantSDNode::getSExtValue(), and llvm::ISD::INSERT_SUBVECTOR.
Referenced by checkV64LaneV128().
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Definition at line 427 of file AArch64ISelDAGToDAG.cpp.
References checkHighLaneIndex(), llvm::SDValue::getNode(), and std::swap().
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getExtendTypeForNode - Translate an extend node to the corresponding ExtendType value.
Definition at line 352 of file AArch64ISelDAGToDAG.cpp.
References llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::dyn_cast(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::ConstantSDNode::getZExtValue(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::AArch64_AM::InvalidShiftExtend, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::AArch64_AM::SXTB, llvm::AArch64_AM::SXTH, llvm::AArch64_AM::SXTW, llvm::AArch64_AM::UXTB, llvm::AArch64_AM::UXTH, llvm::AArch64_AM::UXTW, and llvm::ISD::ZERO_EXTEND.
Definition at line 2120 of file AArch64ISelDAGToDAG.cpp.
References llvm::tgtok::Field, llvm::SmallVectorTemplateCommon< T >::size(), and llvm::StringRef::split().
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Create a machine node performing a notional SHL of Op by ShlAmount.
If ShlAmount is negative, do a (logical) right-shift instead. If ShlAmount is 0, return Op unchanged.
Definition at line 1824 of file AArch64ISelDAGToDAG.cpp.
References llvm::SelectionDAG::getMachineNode(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), and llvm::SDValue::getValueType().
Referenced by isBitfieldPositioningOp().
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getShiftTypeForNode - Translate a shift node to the corresponding ShiftType value.
Definition at line 299 of file AArch64ISelDAGToDAG.cpp.
References llvm::AArch64_AM::ASR, llvm::SDValue::getOpcode(), llvm::AArch64_AM::InvalidShiftExtend, llvm::AArch64_AM::LSL, llvm::AArch64_AM::LSR, llvm::AArch64_AM::ROR, llvm::ISD::ROTR, llvm::ISD::SHL, llvm::ISD::SRA, and llvm::ISD::SRL.
Definition at line 1797 of file AArch64ISelDAGToDAG.cpp.
References llvm::APInt::flipAllBits(), llvm::APInt::getBitWidth(), llvm::SDValue::getNode(), llvm::EVT::getScalarType(), llvm::EVT::getSizeInBits(), getUsefulBitsForUse(), llvm::SDValue::getValueType(), and llvm::SDNode::uses().
Referenced by getUsefulBitsFromAndWithImmediate(), getUsefulBitsFromBFM(), getUsefulBitsFromBitfieldMoveOpd(), getUsefulBitsFromOrWithShiftedReg(), and isBitfieldInsertOpFromOr().
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Definition at line 1763 of file AArch64ISelDAGToDAG.cpp.
References llvm::SDNode::getMachineOpcode(), llvm::SDNode::getOperand(), getUsefulBitsFromAndWithImmediate(), getUsefulBitsFromBFM(), getUsefulBitsFromOrWithShiftedReg(), getUsefulBitsFromUBFM(), and llvm::SDNode::isMachineOpcode().
Referenced by getUsefulBits().
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Definition at line 1663 of file AArch64ISelDAGToDAG.cpp.
References llvm::AArch64_AM::decodeLogicalImmediate(), llvm::APInt::getBitWidth(), llvm::SDValue::getNode(), llvm::SDValue::getOperand(), and getUsefulBits().
Referenced by getUsefulBitsForUse().
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Definition at line 1737 of file AArch64ISelDAGToDAG.cpp.
References llvm::APInt::getBitWidth(), llvm::SDValue::getNode(), llvm::SDValue::getOperand(), getUsefulBits(), getUsefulBitsFromBitfieldMoveOpd(), and llvm::APInt::shl().
Referenced by getUsefulBitsForUse().
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Definition at line 1672 of file AArch64ISelDAGToDAG.cpp.
References llvm::APInt::getBitWidth(), getUsefulBits(), llvm::APInt::lshr(), and llvm::APInt::shl().
Referenced by getUsefulBitsFromBFM(), and getUsefulBitsFromUBFM().
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Definition at line 1709 of file AArch64ISelDAGToDAG.cpp.
References llvm::APInt::clearAllBits(), llvm::APInt::flipAllBits(), llvm::SDValue::getNode(), llvm::SDValue::getOperand(), llvm::AArch64_AM::getShiftType(), llvm::AArch64_AM::getShiftValue(), getUsefulBits(), llvm::APInt::lshr(), llvm::AArch64_AM::LSL, llvm::AArch64_AM::LSR, and llvm::APInt::shl().
Referenced by getUsefulBitsForUse().
Definition at line 1699 of file AArch64ISelDAGToDAG.cpp.
References llvm::SDValue::getNode(), llvm::SDValue::getOperand(), and getUsefulBitsFromBitfieldMoveOpd().
Referenced by getUsefulBitsForUse().
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Does DstMask form a complementary pair with the mask provided by BitsToBeInserted, suitable for use in a BFI instruction.
Roughly speaking, this asks whether DstMask zeroes precisely those bits that will be set by the other half.
Definition at line 1633 of file AArch64ISelDAGToDAG.cpp.
References llvm::EVT::getSizeInBits(), llvm::MVT::i32, llvm::MVT::i64, and llvm::APInt::zextOrTrunc().
Referenced by isBitfieldInsertOpFromOr().
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Definition at line 1563 of file AArch64ISelDAGToDAG.cpp.
References llvm::ISD::AND, llvm::SDNode::getMachineOpcode(), llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::MVT::i32, llvm::MVT::i64, isBitfieldExtractOpFromAnd(), isBitfieldExtractOpFromShr(), llvm::SDNode::isMachineOpcode(), llvm::ISD::SRA, and llvm::ISD::SRL.
Referenced by isBitfieldInsertOpFromOr().
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Definition at line 1360 of file AArch64ISelDAGToDAG.cpp.
References llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::dbgs(), DEBUG, llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::MVT::i32, llvm::MVT::i64, isOpcWithIntImmediate(), llvm::ISD::SRL, llvm::ISD::TRUNCATE, and Widen().
Referenced by isBitfieldExtractOp().
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Definition at line 1497 of file AArch64ISelDAGToDAG.cpp.
References llvm::dbgs(), DEBUG, llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDNode::getValueType(), llvm::MVT::i32, llvm::MVT::i64, isIntImmediate(), isOpcWithIntImmediate(), isSeveralBitsExtractOpFromShr(), llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, and llvm::ISD::TRUNCATE.
Referenced by isBitfieldExtractOp().
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Definition at line 1905 of file AArch64ISelDAGToDAG.cpp.
References llvm::ISD::AND, llvm::SelectionDAG::computeKnownBits(), llvm::APInt::countLeadingZeros(), llvm::APInt::countTrailingZeros(), llvm::APInt::getBitsSet(), llvm::APInt::getBitWidth(), llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), getUsefulBits(), llvm::SDNode::getValueType(), llvm::MVT::i32, llvm::MVT::i64, isBitfieldDstMask(), isBitfieldExtractOp(), isBitfieldPositioningOp(), isOpcWithIntImmediate(), llvm::ISD::OR, and std::swap().
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Does this tree qualify as an attempt to move a bitfield into position, essentially "(and (shl VAL, N), Mask)".
Definition at line 1854 of file AArch64ISelDAGToDAG.cpp.
References llvm::ISD::AND, llvm::SelectionDAG::computeKnownBits(), llvm::countTrailingOnes(), llvm::countTrailingZeros(), getLeftShift(), llvm::SDValue::getNode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), isOpcWithIntImmediate(), llvm::isShiftedMask_64(), and llvm::ISD::SHL.
Referenced by isBitfieldInsertOpFromOr().
isIntImmediate - This method tests to see if the node is a constant operand.
If so Imm will receive the 32-bit value.
Definition at line 193 of file AArch64ISelDAGToDAG.cpp.
Referenced by isBitfieldExtractOpFromShr(), isIntImmediate(), isOpcWithIntImmediate(), and isSeveralBitsExtractOpFromShr().
Definition at line 203 of file AArch64ISelDAGToDAG.cpp.
References llvm::SDValue::getNode(), and isIntImmediate().
Definition at line 210 of file AArch64ISelDAGToDAG.cpp.
References llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), and isIntImmediate().
Referenced by isBitfieldExtractOpFromAnd(), isBitfieldExtractOpFromShr(), isBitfieldInsertOpFromOr(), isBitfieldPositioningOp(), and isSeveralBitsExtractOpFromShr().
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Definition at line 825 of file AArch64ISelDAGToDAG.cpp.
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Definition at line 1451 of file AArch64ISelDAGToDAG.cpp.
References llvm::ISD::AND, llvm::countLeadingOnes(), llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::MVT::i32, isIntImmediate(), llvm::isMask_64(), isOpcWithIntImmediate(), and llvm::ISD::SRL.
Referenced by isBitfieldExtractOpFromShr().
If there's a use of this ADDlow that's not itself a load/store then we'll need to create a real ADD instruction from it anyway and there's no point in folding it into the mem op.
Theoretically, it shouldn't matter, but there's a single pseudo-instruction for an ADRP/ADD pair so over-aggressive folding leads to duplaicated ADRP instructions.
Definition at line 591 of file AArch64ISelDAGToDAG.cpp.
References llvm::ISD::ATOMIC_LOAD, llvm::ISD::ATOMIC_STORE, llvm::ISD::LOAD, llvm::Monotonic, llvm::ISD::STORE, and llvm::SDNode::uses().
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Instructions that accept extend modifiers like UXTW expect the register being extended to be a GPR32, but the incoming DAG might be acting on a GPR64 (either via SEXT_INREG or AND).
Extract the appropriate low bits if this is the case.
Definition at line 534 of file AArch64ISelDAGToDAG.cpp.
References llvm::TargetOpcode::EXTRACT_SUBREG, llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValueType(), and llvm::MVT::i32.
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NarrowVector - Given a value in the V128 register class, produce the equivalent value in the V64 register class.
Definition at line 1189 of file AArch64ISelDAGToDAG.cpp.
References llvm::EVT::getSimpleVT(), llvm::SelectionDAG::getTargetExtractSubreg(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), and llvm::MVT::getVectorVT().
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Definition at line 701 of file AArch64ISelDAGToDAG.cpp.
References llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getTargetConstant(), llvm::MVT::i32, llvm::MVT::i64, llvm::TargetOpcode::IMPLICIT_DEF, and llvm::TargetOpcode::INSERT_SUBREG.
Referenced by isBitfieldExtractOpFromAnd().
1.8.6