LLVM  3.7.0
Thumb1FrameLowering.cpp
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1 //===-- Thumb1FrameLowering.cpp - Thumb1 Frame Information ----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Thumb1 implementation of TargetFrameLowering class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "Thumb1FrameLowering.h"
15 #include "ARMMachineFunctionInfo.h"
21 
22 using namespace llvm;
23 
25  : ARMFrameLowering(sti) {}
26 
28  const MachineFrameInfo *FFI = MF.getFrameInfo();
29  unsigned CFSize = FFI->getMaxCallFrameSize();
30  // It's not always a good idea to include the call frame as part of the
31  // stack frame. ARM (especially Thumb) has small immediate offset to
32  // address the stack frame. So a large call frame can cause poor codegen
33  // and may even makes it impossible to scavenge a register.
34  if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
35  return false;
36 
37  return !MF.getFrameInfo()->hasVarSizedObjects();
38 }
39 
40 static void
43  const TargetInstrInfo &TII, DebugLoc dl,
44  const ThumbRegisterInfo &MRI,
45  int NumBytes, unsigned MIFlags = MachineInstr::NoFlags) {
46  emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
47  MRI, MIFlags);
48 }
49 
50 
54  const Thumb1InstrInfo &TII =
55  *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
56  const ThumbRegisterInfo *RegInfo =
57  static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
58  if (!hasReservedCallFrame(MF)) {
59  // If we have alloca, convert as follows:
60  // ADJCALLSTACKDOWN -> sub, sp, sp, amount
61  // ADJCALLSTACKUP -> add, sp, sp, amount
62  MachineInstr *Old = I;
63  DebugLoc dl = Old->getDebugLoc();
64  unsigned Amount = Old->getOperand(0).getImm();
65  if (Amount != 0) {
66  // We need to keep the stack aligned properly. To do this, we round the
67  // amount of space needed for the outgoing arguments up to the next
68  // alignment boundary.
69  unsigned Align = getStackAlignment();
70  Amount = (Amount+Align-1)/Align*Align;
71 
72  // Replace the pseudo instruction with a new instruction...
73  unsigned Opc = Old->getOpcode();
74  if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
75  emitSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount);
76  } else {
77  assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
78  emitSPUpdate(MBB, I, TII, dl, *RegInfo, Amount);
79  }
80  }
81  }
82  MBB.erase(I);
83 }
84 
86  MachineBasicBlock &MBB) const {
87  assert(&MBB == &MF.front() && "Shrink-wrapping not yet implemented");
89  MachineFrameInfo *MFI = MF.getFrameInfo();
91  MachineModuleInfo &MMI = MF.getMMI();
92  const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
93  const ThumbRegisterInfo *RegInfo =
94  static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
95  const Thumb1InstrInfo &TII =
96  *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
97 
98  unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
99  unsigned NumBytes = MFI->getStackSize();
100  assert(NumBytes >= ArgRegsSaveSize &&
101  "ArgRegsSaveSize is included in NumBytes");
102  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
103  DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
104  unsigned FramePtr = RegInfo->getFrameRegister(MF);
105  unsigned BasePtr = RegInfo->getBaseRegister();
106  int CFAOffset = 0;
107 
108  // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
109  NumBytes = (NumBytes + 3) & ~3;
110  MFI->setStackSize(NumBytes);
111 
112  // Determine the sizes of each callee-save spill areas and record which frame
113  // belongs to which callee-save spill areas.
114  unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
115  int FramePtrSpillFI = 0;
116 
117  if (ArgRegsSaveSize) {
118  emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize,
120  CFAOffset -= ArgRegsSaveSize;
121  unsigned CFIIndex = MMI.addFrameInst(
122  MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
123  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
124  .addCFIIndex(CFIIndex)
126  }
127 
128  if (!AFI->hasStackFrame()) {
129  if (NumBytes - ArgRegsSaveSize != 0) {
130  emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -(NumBytes - ArgRegsSaveSize),
132  CFAOffset -= NumBytes - ArgRegsSaveSize;
133  unsigned CFIIndex = MMI.addFrameInst(
134  MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
135  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
136  .addCFIIndex(CFIIndex)
138  }
139  return;
140  }
141 
142  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
143  unsigned Reg = CSI[i].getReg();
144  int FI = CSI[i].getFrameIdx();
145  switch (Reg) {
146  case ARM::R8:
147  case ARM::R9:
148  case ARM::R10:
149  case ARM::R11:
150  if (STI.isTargetMachO()) {
151  GPRCS2Size += 4;
152  break;
153  }
154  // fallthrough
155  case ARM::R4:
156  case ARM::R5:
157  case ARM::R6:
158  case ARM::R7:
159  case ARM::LR:
160  if (Reg == FramePtr)
161  FramePtrSpillFI = FI;
162  GPRCS1Size += 4;
163  break;
164  default:
165  DPRCSSize += 8;
166  }
167  }
168 
169  if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
170  ++MBBI;
171  if (MBBI != MBB.end())
172  dl = MBBI->getDebugLoc();
173  }
174 
175  // Determine starting offsets of spill areas.
176  unsigned DPRCSOffset = NumBytes - ArgRegsSaveSize - (GPRCS1Size + GPRCS2Size + DPRCSSize);
177  unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
178  unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
179  bool HasFP = hasFP(MF);
180  if (HasFP)
181  AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
182  NumBytes);
183  AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
184  AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
185  AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
186  NumBytes = DPRCSOffset;
187 
188  int FramePtrOffsetInBlock = 0;
189  unsigned adjustedGPRCS1Size = GPRCS1Size;
190  if (tryFoldSPUpdateIntoPushPop(STI, MF, std::prev(MBBI), NumBytes)) {
191  FramePtrOffsetInBlock = NumBytes;
192  adjustedGPRCS1Size += NumBytes;
193  NumBytes = 0;
194  }
195 
196  if (adjustedGPRCS1Size) {
197  CFAOffset -= adjustedGPRCS1Size;
198  unsigned CFIIndex = MMI.addFrameInst(
199  MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
200  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
201  .addCFIIndex(CFIIndex)
203  }
204  for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
205  E = CSI.end(); I != E; ++I) {
206  unsigned Reg = I->getReg();
207  int FI = I->getFrameIdx();
208  switch (Reg) {
209  case ARM::R8:
210  case ARM::R9:
211  case ARM::R10:
212  case ARM::R11:
213  case ARM::R12:
214  if (STI.isTargetMachO())
215  break;
216  // fallthough
217  case ARM::R0:
218  case ARM::R1:
219  case ARM::R2:
220  case ARM::R3:
221  case ARM::R4:
222  case ARM::R5:
223  case ARM::R6:
224  case ARM::R7:
225  case ARM::LR:
226  unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
227  nullptr, MRI->getDwarfRegNum(Reg, true), MFI->getObjectOffset(FI)));
228  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
229  .addCFIIndex(CFIIndex)
231  break;
232  }
233  }
234 
235 
236  // Adjust FP so it point to the stack slot that contains the previous FP.
237  if (HasFP) {
238  FramePtrOffsetInBlock += MFI->getObjectOffset(FramePtrSpillFI)
239  + GPRCS1Size + ArgRegsSaveSize;
240  AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
241  .addReg(ARM::SP).addImm(FramePtrOffsetInBlock / 4)
243  if(FramePtrOffsetInBlock) {
244  CFAOffset += FramePtrOffsetInBlock;
245  unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfa(
246  nullptr, MRI->getDwarfRegNum(FramePtr, true), CFAOffset));
247  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
248  .addCFIIndex(CFIIndex)
250  } else {
251  unsigned CFIIndex =
253  nullptr, MRI->getDwarfRegNum(FramePtr, true)));
254  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
255  .addCFIIndex(CFIIndex)
257  }
258  if (NumBytes > 508)
259  // If offset is > 508 then sp cannot be adjusted in a single instruction,
260  // try restoring from fp instead.
261  AFI->setShouldRestoreSPFromFP(true);
262  }
263 
264  if (NumBytes) {
265  // Insert it after all the callee-save spills.
266  emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
268  if (!HasFP) {
269  CFAOffset -= NumBytes;
270  unsigned CFIIndex = MMI.addFrameInst(
271  MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
272  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
273  .addCFIIndex(CFIIndex)
275  }
276  }
277 
278  if (STI.isTargetELF() && HasFP)
280  AFI->getFramePtrSpillOffset());
281 
282  AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
283  AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
284  AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
285 
286  // Thumb1 does not currently support dynamic stack realignment. Report a
287  // fatal error rather then silently generate bad code.
288  if (RegInfo->needsStackRealignment(MF))
289  report_fatal_error("Dynamic stack realignment not supported for thumb1.");
290 
291  // If we need a base pointer, set it up here. It's whatever the value
292  // of the stack pointer is at this point. Any variable size objects
293  // will be allocated after this, so we can still use the base pointer
294  // to reference locals.
295  if (RegInfo->hasBasePointer(MF))
296  AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr)
297  .addReg(ARM::SP));
298 
299  // If the frame has variable sized objects then the epilogue must restore
300  // the sp from fp. We can assume there's an FP here since hasFP already
301  // checks for hasVarSizedObjects.
302  if (MFI->hasVarSizedObjects())
303  AFI->setShouldRestoreSPFromFP(true);
304 }
305 
306 static bool isCSRestore(MachineInstr *MI, const MCPhysReg *CSRegs) {
307  if (MI->getOpcode() == ARM::tLDRspi &&
308  MI->getOperand(1).isFI() &&
309  isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs))
310  return true;
311  else if (MI->getOpcode() == ARM::tPOP) {
312  // The first two operands are predicates. The last two are
313  // imp-def and imp-use of SP. Check everything in between.
314  for (int i = 2, e = MI->getNumOperands() - 2; i != e; ++i)
315  if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
316  return false;
317  return true;
318  }
319  return false;
320 }
321 
323  MachineBasicBlock &MBB) const {
325  assert((MBBI->getOpcode() == ARM::tBX_RET ||
326  MBBI->getOpcode() == ARM::tPOP_RET) &&
327  "Can only insert epilog into returning blocks");
328  DebugLoc dl = MBBI->getDebugLoc();
329  MachineFrameInfo *MFI = MF.getFrameInfo();
331  const ThumbRegisterInfo *RegInfo =
332  static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
333  const Thumb1InstrInfo &TII =
334  *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
335 
336  unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
337  int NumBytes = (int)MFI->getStackSize();
338  assert((unsigned)NumBytes >= ArgRegsSaveSize &&
339  "ArgRegsSaveSize is included in NumBytes");
340  const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
341  unsigned FramePtr = RegInfo->getFrameRegister(MF);
342 
343  if (!AFI->hasStackFrame()) {
344  if (NumBytes - ArgRegsSaveSize != 0)
345  emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes - ArgRegsSaveSize);
346  } else {
347  // Unwind MBBI to point to first LDR / VLDRD.
348  if (MBBI != MBB.begin()) {
349  do
350  --MBBI;
351  while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
352  if (!isCSRestore(MBBI, CSRegs))
353  ++MBBI;
354  }
355 
356  // Move SP to start of FP callee save spill area.
357  NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
360  ArgRegsSaveSize);
361 
362  if (AFI->shouldRestoreSPFromFP()) {
363  NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
364  // Reset SP based on frame pointer only if the stack frame extends beyond
365  // frame pointer stack slot, the target is ELF and the function has FP, or
366  // the target uses var sized objects.
367  if (NumBytes) {
368  assert(!MFI->getPristineRegs(MF).test(ARM::R4) &&
369  "No scratch register to restore SP from FP!");
370  emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
371  TII, *RegInfo);
372  AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
373  ARM::SP)
374  .addReg(ARM::R4));
375  } else
376  AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
377  ARM::SP)
378  .addReg(FramePtr));
379  } else {
380  if (MBBI->getOpcode() == ARM::tBX_RET &&
381  &MBB.front() != MBBI &&
382  std::prev(MBBI)->getOpcode() == ARM::tPOP) {
383  MachineBasicBlock::iterator PMBBI = std::prev(MBBI);
384  if (!tryFoldSPUpdateIntoPushPop(STI, MF, PMBBI, NumBytes))
385  emitSPUpdate(MBB, PMBBI, TII, dl, *RegInfo, NumBytes);
386  } else if (!tryFoldSPUpdateIntoPushPop(STI, MF, MBBI, NumBytes))
387  emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes);
388  }
389  }
390 
391  bool IsV4PopReturn = false;
392  for (const CalleeSavedInfo &CSI : MFI->getCalleeSavedInfo())
393  if (CSI.getReg() == ARM::LR)
394  IsV4PopReturn = true;
395  IsV4PopReturn &= STI.hasV4TOps() && !STI.hasV5TOps();
396 
397  // Unlike T2 and ARM mode, the T1 pop instruction cannot restore
398  // to LR, and we can't pop the value directly to the PC since
399  // we need to update the SP after popping the value. So instead
400  // we have to emit:
401  // POP {r3}
402  // ADD sp, #offset
403  // BX r3
404  // If this would clobber a return value, then generate this sequence instead:
405  // MOV ip, r3
406  // POP {r3}
407  // ADD sp, #offset
408  // MOV lr, r3
409  // MOV r3, ip
410  // BX lr
411  if (ArgRegsSaveSize || IsV4PopReturn) {
412  // Get the last instruction, tBX_RET
413  MBBI = MBB.getLastNonDebugInstr();
414  assert (MBBI->getOpcode() == ARM::tBX_RET);
415  DebugLoc dl = MBBI->getDebugLoc();
416 
417  if (AFI->getReturnRegsCount() <= 3) {
418  // Epilogue: pop saved LR to R3 and branch off it.
419  AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)))
420  .addReg(ARM::R3, RegState::Define);
421 
422  emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, ArgRegsSaveSize);
423 
424  MachineInstrBuilder MIB =
425  BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX))
426  .addReg(ARM::R3, RegState::Kill);
427  AddDefaultPred(MIB);
428  MIB.copyImplicitOps(&*MBBI);
429  // erase the old tBX_RET instruction
430  MBB.erase(MBBI);
431  } else {
432  AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
433  .addReg(ARM::R12, RegState::Define)
434  .addReg(ARM::R3, RegState::Kill));
435 
436  AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)))
437  .addReg(ARM::R3, RegState::Define);
438 
439  emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, ArgRegsSaveSize);
440 
441  AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
442  .addReg(ARM::LR, RegState::Define)
443  .addReg(ARM::R3, RegState::Kill));
444 
445  AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
446  .addReg(ARM::R3, RegState::Define)
447  .addReg(ARM::R12, RegState::Kill));
448  // Keep the tBX_RET instruction
449  }
450  }
451 }
452 
456  const std::vector<CalleeSavedInfo> &CSI,
457  const TargetRegisterInfo *TRI) const {
458  if (CSI.empty())
459  return false;
460 
461  DebugLoc DL;
462  const TargetInstrInfo &TII = *STI.getInstrInfo();
463 
464  if (MI != MBB.end()) DL = MI->getDebugLoc();
465 
466  MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH));
467  AddDefaultPred(MIB);
468  for (unsigned i = CSI.size(); i != 0; --i) {
469  unsigned Reg = CSI[i-1].getReg();
470  bool isKill = true;
471 
472  // Add the callee-saved register as live-in unless it's LR and
473  // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress
474  // then it's already added to the function and entry block live-in sets.
475  if (Reg == ARM::LR) {
476  MachineFunction &MF = *MBB.getParent();
477  if (MF.getFrameInfo()->isReturnAddressTaken() &&
478  MF.getRegInfo().isLiveIn(Reg))
479  isKill = false;
480  }
481 
482  if (isKill)
483  MBB.addLiveIn(Reg);
484 
485  MIB.addReg(Reg, getKillRegState(isKill));
486  }
488  return true;
489 }
490 
494  const std::vector<CalleeSavedInfo> &CSI,
495  const TargetRegisterInfo *TRI) const {
496  if (CSI.empty())
497  return false;
498 
499  MachineFunction &MF = *MBB.getParent();
501  const TargetInstrInfo &TII = *STI.getInstrInfo();
502 
503  bool isVarArg = AFI->getArgRegsSaveSize() > 0;
504  DebugLoc DL = MI->getDebugLoc();
505  MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(ARM::tPOP));
506  AddDefaultPred(MIB);
507 
508  bool NumRegs = false;
509  for (unsigned i = CSI.size(); i != 0; --i) {
510  unsigned Reg = CSI[i-1].getReg();
511  if (Reg == ARM::LR) {
512  // Special epilogue for vararg functions. See emitEpilogue
513  if (isVarArg)
514  continue;
515  // ARMv4T requires BX, see emitEpilogue
516  if (STI.hasV4TOps() && !STI.hasV5TOps())
517  continue;
518  Reg = ARM::PC;
519  (*MIB).setDesc(TII.get(ARM::tPOP_RET));
520  MIB.copyImplicitOps(&*MI);
521  MI = MBB.erase(MI);
522  }
523  MIB.addReg(Reg, getDefRegState(true));
524  NumRegs = true;
525  }
526 
527  // It's illegal to emit pop instruction without operands.
528  if (NumRegs)
529  MBB.insert(MI, &*MIB);
530  else
531  MF.DeleteMachineInstr(MIB);
532 
533  return true;
534 }
bool hasV4TOps() const
Definition: ARMSubtarget.h:290
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
int getDwarfRegNum(unsigned RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
#define R4(n)
BitVector getPristineRegs(const MachineFunction &MF) const
Return a set of physical registers that are pristine.
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
unsigned getBaseRegister() const
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
Definition: MCDwarf.h:381
void addLiveIn(unsigned Reg)
Adds the specified register as a live in.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
bool isReturnAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
A debug info location.
Definition: DebugLoc.h:34
bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget, MachineFunction &MF, MachineInstr *MI, unsigned NumBytes)
Tries to add registers to the reglist of a given base-updating push/pop instruction to adjust the sta...
#define R2(n)
void setGPRCalleeSavedArea2Offset(unsigned o)
static MCCFIInstruction createDefCfaOffset(MCSymbol *L, int Offset)
.cfi_def_cfa_offset modifies a rule for computing CFA.
Definition: MCDwarf.h:368
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag=true)
Reports a serious error, calling any installed error handler.
unsigned getDPRCalleeSavedAreaSize() const
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
const ARMBaseInstrInfo * getInstrInfo() const override
Definition: ARMSubtarget.h:262
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
static const MachineInstrBuilder & AddDefaultPred(const MachineInstrBuilder &MIB)
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
DILocation * get() const
Get the underlying DILocation.
Definition: DebugLoc.cpp:22
const HexagonInstrInfo * TII
bool isTargetELF() const
Definition: ARMSubtarget.h:363
Thumb1FrameLowering(const ARMSubtarget &sti)
unsigned getFrameRegister(const MachineFunction &MF) const override
unsigned getArgRegsSaveSize() const
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
void setDPRCalleeSavedAreaOffset(unsigned o)
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:271
void setFramePtrSpillOffset(unsigned o)
const MachineBasicBlock & front() const
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
bool isLiveIn(unsigned Reg) const
int getOffsetAdjustment() const
Return the correction for frame offsets.
unsigned getReturnRegsCount() const
bool isTargetMachO() const
Definition: ARMSubtarget.h:364
iterator getLastNonDebugInstr()
getLastNonDebugInstr - returns an iterator to the last non-debug instruction in the basic block...
int64_t getImm() const
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
unsigned getKillRegState(bool B)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:267
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
TargetInstrInfo - Interface to description of machine instruction set.
unsigned getDefRegState(bool B)
bundle_iterator< MachineInstr, instr_iterator > iterator
static bool isCalleeSavedRegister(unsigned Reg, const MCPhysReg *CSRegs)
static MCCFIInstruction createDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it...
Definition: MCDwarf.h:354
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register)
.cfi_def_cfa_register modifies a rule for computing CFA.
Definition: MCDwarf.h:361
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
void setStackSize(uint64_t Size)
Set the size of the stack.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
unsigned getFramePtrSpillOffset() const
void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags=0)
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
void setGPRCalleeSavedArea2Size(unsigned s)
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required, we reserve argument space for call sites in the function immediately on entry to the current function.
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
void DeleteMachineInstr(MachineInstr *MI)
DeleteMachineInstr - Delete the given MachineInstr.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
static bool isCSRestore(MachineInstr *MI, const MCPhysReg *CSRegs)
#define R6(n)
void setGPRCalleeSavedArea1Size(unsigned s)
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
bool test(unsigned Idx) const
Definition: BitVector.h:322
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call...
void setOffsetAdjustment(int Adj)
Set the correction for frame offsets.
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
bool hasBasePointer(const MachineFunction &MF) const
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:238
Representation of each machine instruction.
Definition: MachineInstr.h:51
static void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const TargetInstrInfo &TII, DebugLoc dl, const ThumbRegisterInfo &MRI, int NumBytes, unsigned MIFlags=MachineInstr::NoFlags)
void setGPRCalleeSavedArea1Offset(unsigned o)
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool hasV5TOps() const
Definition: ARMSubtarget.h:291
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
#define I(x, y, z)
Definition: MD5.cpp:54
const ARMBaseRegisterInfo * getRegisterInfo() const override
Definition: ARMSubtarget.h:271
void setDPRCalleeSavedAreaSize(unsigned s)
const MachineInstrBuilder & copyImplicitOps(const MachineInstr *OtherMI)
Copy all the implicit operands from OtherMI onto this one.
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
unsigned getReg() const
getReg - Returns the register number.
unsigned getGPRCalleeSavedArea1Size() const
void eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
eliminateCallFramePseudoInstr - This method is called during prolog/epilog code insertion to eliminat...
static const unsigned FramePtr
MachineModuleInfo & getMMI() const
const ARMSubtarget & STI
unsigned getGPRCalleeSavedArea2Size() const
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
bool needsStackRealignment(const MachineFunction &MF) const override
MachineModuleInfo - This class contains meta information specific to a module.