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LLVM
3.7.0
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#include <ARMSubtarget.h>
Protected Types | |
| enum | ARMProcFamilyEnum { Others, CortexA5, CortexA7, CortexA8, CortexA9, CortexA12, CortexA15, CortexA17, CortexR4, CortexR4F, CortexR5, Swift, CortexA53, CortexA57, Krait } |
| enum | ARMProcClassEnum { None, AClass, RClass, MClass } |
Protected Attributes | |
| ARMProcFamilyEnum | ARMProcFamily |
| ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others. More... | |
| ARMProcClassEnum | ARMProcClass |
| ARMProcClass - ARM processor class: None, AClass, RClass or MClass. More... | |
| bool | HasV4TOps |
| HasV4TOps, HasV5TOps, HasV5TEOps, HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops - Specify whether target support specific ARM ISA variants. More... | |
| bool | HasV5TOps |
| bool | HasV5TEOps |
| bool | HasV6Ops |
| bool | HasV6MOps |
| bool | HasV6KOps |
| bool | HasV6T2Ops |
| bool | HasV7Ops |
| bool | HasV8Ops |
| bool | HasV8_1aOps |
| bool | HasVFPv2 |
| HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what floating point ISAs are supported. More... | |
| bool | HasVFPv3 |
| bool | HasVFPv4 |
| bool | HasFPARMv8 |
| bool | HasNEON |
| bool | UseNEONForSinglePrecisionFP |
| UseNEONForSinglePrecisionFP - if the NEONFP attribute has been specified. More... | |
| bool | UseMulOps |
| UseMulOps - True if non-microcoded fused integer multiply-add and multiply-subtract instructions should be used. More... | |
| bool | SlowFPVMLx |
| SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates whether the FP VML[AS] instructions are slow (if so, don't use them). More... | |
| bool | HasVMLxForwarding |
| HasVMLxForwarding - If true, NEON has special multiplier accumulator forwarding to allow mul + mla being issued back to back. More... | |
| bool | SlowFPBrcc |
| SlowFPBrcc - True if floating point compare + branch is slow. More... | |
| bool | InThumbMode |
| InThumbMode - True if compiling for Thumb, false for ARM. More... | |
| bool | UseSoftFloat |
| UseSoftFloat - True if we're using software floating point features. More... | |
| bool | HasThumb2 |
| HasThumb2 - True if Thumb2 instructions are supported. More... | |
| bool | NoARM |
| NoARM - True if subtarget does not support ARM mode execution. More... | |
| bool | IsR9Reserved |
| IsR9Reserved - True if R9 is a not available as general purpose register. More... | |
| bool | UseMovt |
| UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit imms (including global addresses). More... | |
| bool | SupportsTailCall |
| SupportsTailCall - True if the OS supports tail call. More... | |
| bool | HasFP16 |
| HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF only so far) More... | |
| bool | HasD16 |
| HasD16 - True if subtarget is limited to 16 double precision FP registers for VFPv3. More... | |
| bool | HasHardwareDivide |
| HasHardwareDivide - True if subtarget supports [su]div. More... | |
| bool | HasHardwareDivideInARM |
| HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode. More... | |
| bool | HasT2ExtractPack |
| HasT2ExtractPack - True if subtarget supports thumb2 extract/pack instructions. More... | |
| bool | HasDataBarrier |
| HasDataBarrier - True if the subtarget supports DMB / DSB data barrier instructions. More... | |
| bool | Pref32BitThumb |
| Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions over 16-bit ones. More... | |
| bool | AvoidCPSRPartialUpdate |
| AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions that partially update CPSR and add false dependency on the previous CPSR setting instruction. More... | |
| bool | AvoidMOVsShifterOperand |
| AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting movs with shifter operand (i.e. More... | |
| bool | HasRAS |
| HasRAS - Some processors perform return stack prediction. More... | |
| bool | HasMPExtension |
| HasMPExtension - True if the subtarget supports Multiprocessing extension (ARMv7 only). More... | |
| bool | HasVirtualization |
| HasVirtualization - True if the subtarget supports the Virtualization extension. More... | |
| bool | FPOnlySP |
| FPOnlySP - If true, the floating point unit only supports single precision. More... | |
| bool | HasPerfMon |
| If true, the processor supports the Performance Monitor Extensions. More... | |
| bool | HasTrustZone |
| HasTrustZone - if true, processor supports TrustZone security extensions. More... | |
| bool | HasCrypto |
| HasCrypto - if true, processor supports Cryptography extensions. More... | |
| bool | HasCRC |
| HasCRC - if true, processor supports CRC instructions. More... | |
| bool | HasZeroCycleZeroing |
| If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are particularly effective at zeroing a VFP register. More... | |
| bool | AllowsUnalignedMem |
| AllowsUnalignedMem - If true, the subtarget allows unaligned memory accesses for some types. More... | |
| bool | RestrictIT |
| RestrictIT - If true, the subtarget disallows generation of deprecated IT blocks to conform to ARMv8 rule. More... | |
| bool | Thumb2DSP |
| Thumb2DSP - If true, the subtarget supports the v7 DSP (saturating arith and such) instructions in Thumb2 code. More... | |
| bool | UseNaClTrap |
| NaCl TRAP instruction is generated instead of the regular TRAP. More... | |
| bool | GenLongCalls |
| Generate calls via indirect call instructions. More... | |
| bool | UnsafeFPMath |
| Target machine allowed unsafe FP math (such as use of NEON fp) More... | |
| unsigned | stackAlignment |
| stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function. More... | |
| std::string | CPUString |
| CPUString - String name of used CPU. More... | |
| bool | IsLittle |
| IsLittle - The target is Little Endian. More... | |
| Triple | TargetTriple |
| TargetTriple - What processor and OS we're targeting. More... | |
| MCSchedModel | SchedModel |
| SchedModel - Processor specific instruction costs. More... | |
| InstrItineraryData | InstrItins |
| Selected instruction itineraries (one entry per itinerary class.) More... | |
| const TargetOptions & | Options |
| Options passed via command line that could influence the target. More... | |
| const ARMBaseTargetMachine & | TM |
Definition at line 42 of file ARMSubtarget.h.
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| Enumerator | |
|---|---|
| None | |
| AClass | |
| RClass | |
| MClass | |
Definition at line 48 of file ARMSubtarget.h.
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| Enumerator | |
|---|---|
| Others | |
| CortexA5 | |
| CortexA7 | |
| CortexA8 | |
| CortexA9 | |
| CortexA12 | |
| CortexA15 | |
| CortexA17 | |
| CortexR4 | |
| CortexR4F | |
| CortexR5 | |
| Swift | |
| CortexA53 | |
| CortexA57 | |
| Krait | |
Definition at line 44 of file ARMSubtarget.h.
| ARMSubtarget::ARMSubtarget | ( | const Triple & | TT, |
| const std::string & | CPU, | ||
| const std::string & | FS, | ||
| const ARMBaseTargetMachine & | TM, | ||
| bool | IsLittle | ||
| ) |
This constructor initializes the data members to match that of the specified triple.
Definition at line 109 of file ARMSubtarget.cpp.
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Definition at line 422 of file ARMSubtarget.h.
References AllowsUnalignedMem.
Referenced by llvm::ARMTargetLowering::allowsMisalignedMemoryAccesses().
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Definition at line 342 of file ARMSubtarget.h.
References AvoidCPSRPartialUpdate.
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Definition at line 343 of file ARMSubtarget.h.
References AvoidMOVsShifterOperand.
| void llvm::ARMSubtarget::computeIssueWidth | ( | ) |
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Definition at line 332 of file ARMSubtarget.cpp.
References hasAnyDataBarrier(), and isThumb1Only().
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True for some subtargets at > -O0.
Definition at line 328 of file ARMSubtarget.cpp.
References hasThumb2(), and isThumb().
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Definition at line 348 of file ARMSubtarget.h.
References GenLongCalls.
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Definition at line 426 of file ARMSubtarget.h.
References CPUString.
Referenced by llvm::ARMTargetMachine::ARMTargetMachine().
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Definition at line 268 of file ARMSubtarget.h.
Referenced by llvm::ThumbRegisterInfo::eliminateFrameIndex(), and llvm::ARMFrameLowering::emitPrologue().
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Definition at line 262 of file ARMSubtarget.h.
Referenced by llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(), llvm::Thumb1FrameLowering::eliminateCallFramePseudoInstr(), llvm::ThumbRegisterInfo::eliminateFrameIndex(), llvm::Thumb1FrameLowering::emitEpilogue(), llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), llvm::Thumb1FrameLowering::emitPrologue(), llvm::ARMFrameLowering::emitPrologue(), emitThumb1LoadConstPool(), llvm::ARMTargetLowering::getSchedulingPreference(), llvm::ThumbRegisterInfo::resolveFrameIndex(), llvm::Thumb1FrameLowering::restoreCalleeSavedRegisters(), llvm::ThumbRegisterInfo::saveScavengerRegister(), and llvm::Thumb1FrameLowering::spillCalleeSavedRegisters().
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getInstrItins - Return the instruction itineraries based on subtarget selection.
Definition at line 444 of file ARMSubtarget.h.
References InstrItins.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering().
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getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size that still makes it profitable to inline the call.
Definition at line 248 of file ARMSubtarget.h.
Referenced by llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy().
| unsigned ARMSubtarget::getMispredictionPenalty | ( | ) | const |
Definition at line 319 of file ARMSubtarget.cpp.
References llvm::MCSchedModel::MispredictPenalty, and SchedModel.
Referenced by llvm::ARMBaseInstrInfo::isProfitableToIfCvt().
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Definition at line 259 of file ARMSubtarget.h.
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getStackAlignment - Returns the minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function for this subtarget.
Definition at line 451 of file ARMSubtarget.h.
References stackAlignment.
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Definition at line 265 of file ARMSubtarget.h.
Referenced by llvm::ARMSelectionDAGInfo::EmitSpecializedLibcall().
Definition at line 353 of file ARMSubtarget.h.
References TargetTriple.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), hasSinCos(), and llvm::ARMTargetLowering::LowerOperation().
| bool ARMSubtarget::GVIsIndirectSymbol | ( | const GlobalValue * | GV, |
| Reloc::Model | RelocM | ||
| ) | const |
GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
Definition at line 284 of file ARMSubtarget.cpp.
References llvm::GlobalValue::hasCommonLinkage(), llvm::GlobalValue::hasHiddenVisibility(), llvm::GlobalValue::hasLocalLinkage(), llvm::GlobalValue::isDeclarationForLinker(), llvm::GlobalValue::isStrongDefinitionForLinker(), isTargetMachO(), llvm::Reloc::PIC_, and llvm::Reloc::Static.
Referenced by llvm::ARMBaseInstrInfo::expandLoadStackGuardBase().
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Definition at line 330 of file ARMSubtarget.h.
References HasDataBarrier, hasV6Ops(), and isThumb().
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), and enableAtomicExpand().
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Definition at line 312 of file ARMSubtarget.h.
References NoARM.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), and llvm::ARMTargetMachine::ARMTargetMachine().
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Definition at line 320 of file ARMSubtarget.h.
References HasCRC.
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Definition at line 319 of file ARMSubtarget.h.
References HasCrypto.
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Definition at line 351 of file ARMSubtarget.h.
References HasD16.
Referenced by llvm::ARMBaseRegisterInfo::getReservedRegs().
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Definition at line 329 of file ARMSubtarget.h.
References HasDataBarrier.
Referenced by LowerATOMIC_FENCE(), and llvm::ARMTargetLowering::makeDMB().
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Definition at line 326 of file ARMSubtarget.h.
References HasHardwareDivide.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering().
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Definition at line 327 of file ARMSubtarget.h.
References HasHardwareDivideInARM.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering().
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Definition at line 350 of file ARMSubtarget.h.
References HasFP16.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering().
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Definition at line 317 of file ARMSubtarget.h.
References HasFPARMv8.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering().
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Definition at line 345 of file ARMSubtarget.h.
References HasMPExtension.
Referenced by LowerPREFETCH().
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Definition at line 318 of file ARMSubtarget.h.
References HasNEON.
Referenced by AddCombineToVPADDL(), llvm::ARMTargetLowering::allowsMisalignedMemoryAccesses(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMTargetLowering::canCombineStoreAndExtract(), llvm::ARMTTIImpl::getArithmeticInstrCost(), llvm::ARMTTIImpl::getCastInstrCost(), llvm::ARMTTIImpl::getCmpSelInstrCost(), llvm::ARMBaseInstrInfo::getExecutionDomain(), llvm::ARMTTIImpl::getNumberOfRegisters(), llvm::ARMTargetLowering::getOptimalMemOpType(), llvm::ARMTargetLowering::getRegClassFor(), llvm::ARMTTIImpl::getRegisterBitWidth(), LowerCTPOP(), LowerCTTZ(), LowerShift(), PerformExtendCombine(), PerformORCombine(), PerformSELECT_CCCombine(), PerformShiftCombine(), PerformVCVTCombine(), PerformVDIVCombine(), llvm::ARMBaseInstrInfo::setExecutionDomain(), and useNEONForSinglePrecisionFP().
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Definition at line 338 of file ARMSubtarget.h.
References HasPerfMon.
Referenced by ReplaceREADCYCLECOUNTER().
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Definition at line 344 of file ARMSubtarget.h.
References HasRAS.
| bool ARMSubtarget::hasSinCos | ( | ) | const |
This function returns true if the target has sincos() routine in its compiler runtime or math libraries.
Definition at line 323 of file ARMSubtarget.cpp.
References getTargetTriple(), llvm::Triple::isiOS(), and llvm::Triple::isOSVersionLT().
Referenced by llvm::ARMTargetLowering::ARMTargetLowering().
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Definition at line 328 of file ARMSubtarget.h.
References HasT2ExtractPack.
Referenced by PerformORCombine().
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Definition at line 407 of file ARMSubtarget.h.
References HasThumb2.
Referenced by enablePostRAScheduler().
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Definition at line 346 of file ARMSubtarget.h.
References Thumb2DSP.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), getArchForCPU(), and getMClassRegisterMask().
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Definition at line 339 of file ARMSubtarget.h.
References HasTrustZone.
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Definition at line 290 of file ARMSubtarget.h.
References HasV4TOps.
Referenced by llvm::Thumb1FrameLowering::emitEpilogue(), getArchForCPU(), and llvm::Thumb1FrameLowering::restoreCalleeSavedRegisters().
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Definition at line 292 of file ARMSubtarget.h.
References HasV5TEOps.
Referenced by getArchForCPU(), llvm::ARMBaseInstrInfo::loadRegFromStackSlot(), LowerPREFETCH(), and llvm::ARMBaseInstrInfo::storeRegToStackSlot().
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Definition at line 291 of file ARMSubtarget.h.
References HasV5TOps.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), llvm::Thumb1FrameLowering::emitEpilogue(), llvm::ARMAsmPrinter::EmitInstruction(), getArchForCPU(), and llvm::Thumb1FrameLowering::restoreCalleeSavedRegisters().
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Definition at line 295 of file ARMSubtarget.h.
References HasV6KOps.
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Definition at line 293 of file ARMSubtarget.h.
References HasV6Ops.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), llvm::Thumb1InstrInfo::copyPhysReg(), llvm::ARMTargetLowering::ExpandInlineAsm(), getArchForCPU(), hasAnyDataBarrier(), LowerATOMIC_FENCE(), llvm::ARMTargetLowering::makeDMB(), PerformShiftCombine(), and llvm::ARMTargetLowering::shouldAlignPointerArgs().
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Definition at line 296 of file ARMSubtarget.h.
References HasV6T2Ops.
Referenced by emitAligningInstructions(), getArchForCPU(), llvm::ARMTTIImpl::getIntImmCost(), llvm::ARMTargetLowering::LowerAsmOperandForConstraint(), LowerCTTZ(), and PerformORCombine().
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Definition at line 297 of file ARMSubtarget.h.
References HasV7Ops.
Referenced by llvm::ARMTargetLowering::allowsMisalignedMemoryAccesses(), emitAligningInstructions(), getArchForCPU(), getMClassRegisterMask(), and LowerPREFETCH().
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Definition at line 299 of file ARMSubtarget.h.
References HasV8_1aOps.
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Definition at line 298 of file ARMSubtarget.h.
References HasV8Ops.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), and getArchForCPU().
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Definition at line 314 of file ARMSubtarget.h.
References HasVFPv2.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMBaseInstrInfo::CreateTargetPostRAHazardRecognizer(), llvm::ARMTTIImpl::getFPOpCost(), isLegalAddressImmediate(), and isLegalT2AddressImmediate().
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Definition at line 315 of file ARMSubtarget.h.
References HasVFPv3.
Referenced by llvm::ARMBaseRegisterInfo::getReservedRegs(), and llvm::ARMTargetLowering::isFPImmLegal().
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Definition at line 316 of file ARMSubtarget.h.
References HasVFPv4.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering().
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Definition at line 321 of file ARMSubtarget.h.
References HasVirtualization.
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Definition at line 335 of file ARMSubtarget.h.
References HasVMLxForwarding.
Referenced by PerformVMULCombine().
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Definition at line 340 of file ARMSubtarget.h.
References HasZeroCycleZeroing.
| ARMSubtarget & ARMSubtarget::initializeSubtargetDependencies | ( | StringRef | CPU, |
| StringRef | FS | ||
| ) |
initializeSubtargetDependencies - Initializes using a CPU and feature string so that we can use initializer lists for subtarget initialization.
Definition at line 93 of file ARMSubtarget.cpp.
| bool ARMSubtarget::isAAPCS_ABI | ( | ) | const |
Definition at line 277 of file ARMSubtarget.cpp.
References llvm::ARMBaseTargetMachine::ARM_ABI_AAPCS, llvm::ARMBaseTargetMachine::ARM_ABI_UNKNOWN, llvm::ARMBaseTargetMachine::TargetABI, and TM.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering().
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Definition at line 410 of file ARMSubtarget.h.
References AClass, and ARMProcClass.
| bool ARMSubtarget::isAPCS_ABI | ( | ) | const |
Definition at line 273 of file ARMSubtarget.cpp.
References llvm::ARMBaseTargetMachine::ARM_ABI_APCS, llvm::ARMBaseTargetMachine::ARM_ABI_UNKNOWN, llvm::ARMBaseTargetMachine::TargetABI, and TM.
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Definition at line 305 of file ARMSubtarget.h.
References ARMProcFamily, and CortexA15.
Referenced by llvm::ARMBaseInstrInfo::expandPostRAPseudo(), llvm::ARMTTIImpl::getMaxInterleaveFactor(), llvm::ARMBaseInstrInfo::getPartialRegUpdateClearance(), and isLikeA9().
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Definition at line 301 of file ARMSubtarget.h.
References ARMProcFamily, and CortexA5.
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Definition at line 302 of file ARMSubtarget.h.
References ARMProcFamily, and CortexA7.
Referenced by adjustDefLatency(), llvm::ARMBaseInstrInfo::getNumMicroOps(), and llvm::ARMBaseInstrInfo::getOperandLatency().
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Definition at line 303 of file ARMSubtarget.h.
References ARMProcFamily, and CortexA8.
Referenced by adjustDefLatency(), llvm::ARMBaseInstrInfo::getExecutionDomain(), llvm::ARMBaseInstrInfo::getNumMicroOps(), and llvm::ARMBaseInstrInfo::getOperandLatency().
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Definition at line 304 of file ARMSubtarget.h.
References ARMProcFamily, and CortexA9.
Referenced by llvm::ARMBaseInstrInfo::getExecutionDomain(), and isLikeA9().
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Definition at line 307 of file ARMSubtarget.h.
References CPUString.
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Definition at line 309 of file ARMSubtarget.h.
References ARMProcFamily, and CortexR5.
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Definition at line 336 of file ARMSubtarget.h.
References SlowFPBrcc.
Referenced by canChangeToInt().
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Definition at line 337 of file ARMSubtarget.h.
References FPOnlySP.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMBaseInstrInfo::copyPhysReg(), llvm::ARMBaseInstrInfo::expandPostRAPseudo(), llvm::ARMTTIImpl::getFPOpCost(), llvm::ARMTargetLowering::isFPImmLegal(), and PerformVMOVRRDCombine().
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Definition at line 310 of file ARMSubtarget.h.
References ARMProcFamily, and Krait.
Referenced by isLikeA9().
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Definition at line 308 of file ARMSubtarget.h.
References isCortexA15(), isCortexA9(), and isKrait().
Referenced by adjustDefLatency(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMHazardRecognizer::getHazardType(), llvm::ARMBaseInstrInfo::getNumMicroOps(), and llvm::ARMBaseInstrInfo::getOperandLatency().
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Definition at line 428 of file ARMSubtarget.h.
References IsLittle.
Referenced by llvm::ARMTargetLowering::allowsMisalignedMemoryAccesses(), llvm::ARMTargetLowering::emitLoadLinked(), and llvm::ARMTargetLowering::emitStoreConditional().
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Definition at line 408 of file ARMSubtarget.h.
References ARMProcClass, and MClass.
Referenced by llvm::ARMBaseInstrInfo::copyFromCPSR(), llvm::ARMBaseInstrInfo::copyToCPSR(), getArchForCPU(), llvm::ARMBaseRegisterInfo::getCalleeSavedRegs(), isV6M(), LowerATOMIC_FENCE(), llvm::ARMTargetLowering::makeDMB(), llvm::ARMTargetLowering::shouldAlignPointerArgs(), llvm::ARMTargetLowering::shouldExpandAtomicLoadInIR(), llvm::ARMTargetLowering::shouldExpandAtomicRMWInIR(), and llvm::ARMTargetLowering::shouldExpandAtomicStoreInIR().
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Definition at line 416 of file ARMSubtarget.h.
References IsR9Reserved.
Referenced by llvm::ARMBaseRegisterInfo::getRegPressureLimit(), and llvm::ARMBaseRegisterInfo::getReservedRegs().
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Definition at line 409 of file ARMSubtarget.h.
References ARMProcClass, and RClass.
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Definition at line 306 of file ARMSubtarget.h.
References ARMProcFamily, and Swift.
Referenced by adjustDefLatency(), llvm::ARMTargetLowering::emitLeadingFence(), llvm::ARMTTIImpl::getMaxInterleaveFactor(), llvm::ARMBaseInstrInfo::getNumMicroOps(), llvm::ARMBaseInstrInfo::getOperandLatency(), llvm::ARMBaseInstrInfo::getPartialRegUpdateClearance(), llvm::ARMTTIImpl::getVectorInstrCost(), llvm::ARMBaseInstrInfo::isProfitableToUnpredicate(), and LowerATOMIC_FENCE().
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Definition at line 373 of file ARMSubtarget.h.
References llvm::Triple::EABI, llvm::Triple::EABIHF, llvm::Triple::getEnvironment(), isTargetDarwin(), isTargetWindows(), and TargetTriple.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering().
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Definition at line 396 of file ARMSubtarget.h.
References llvm::Triple::Android, llvm::Triple::getEnvironment(), and TargetTriple.
Referenced by llvm::ARMFrameLowering::adjustForSegmentedStacks().
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Definition at line 362 of file ARMSubtarget.h.
References llvm::Triple::isOSBinFormatCOFF(), and TargetTriple.
Referenced by llvm::ARMAsmPrinter::runOnMachineFunction().
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Definition at line 355 of file ARMSubtarget.h.
References llvm::Triple::isOSDarwin(), and TargetTriple.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMFrameLowering::determineCalleeSaves(), llvm::ARMFrameLowering::emitPrologue(), llvm::ARMBaseRegisterInfo::getCalleeSavedRegs(), llvm::ARMBaseRegisterInfo::getCallPreservedMask(), getFramePointerReg(), llvm::ARMBaseRegisterInfo::getThisReturnPreservedMask(), isTargetAEABI(), and isTargetEHABICompatible().
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Definition at line 381 of file ARMSubtarget.h.
References llvm::Triple::Android, llvm::Triple::EABI, llvm::Triple::EABIHF, llvm::Triple::getEnvironment(), llvm::Triple::GNUEABI, llvm::Triple::GNUEABIHF, isTargetDarwin(), isTargetWindows(), and TargetTriple.
Referenced by llvm::ARMAsmPrinter::EmitInstruction().
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Definition at line 363 of file ARMSubtarget.h.
References llvm::Triple::isOSBinFormatELF(), and TargetTriple.
Referenced by llvm::Thumb1FrameLowering::emitPrologue(), llvm::ARMFrameLowering::emitPrologue(), and llvm::ARMAsmPrinter::EmitXXStructor().
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Definition at line 390 of file ARMSubtarget.h.
References llvm::Triple::EABIHF, llvm::Triple::getEnvironment(), llvm::Triple::GNUEABIHF, isTargetWindows(), and TargetTriple.
Referenced by llvm::ARMBaseTargetMachine::ARMBaseTargetMachine().
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Definition at line 356 of file ARMSubtarget.h.
References llvm::Triple::isiOS(), and TargetTriple.
Referenced by llvm::ARMFrameLowering::hasFP().
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Definition at line 357 of file ARMSubtarget.h.
References llvm::Triple::isOSLinux(), and TargetTriple.
Referenced by llvm::ARMFrameLowering::adjustForSegmentedStacks(), and useFastISel().
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Definition at line 364 of file ARMSubtarget.h.
References llvm::Triple::isOSBinFormatMachO(), and TargetTriple.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMAsmPrinter::EmitInstruction(), llvm::ARMAsmPrinter::EmitMachineConstantPoolValue(), llvm::Thumb1FrameLowering::emitPrologue(), llvm::ARMFrameLowering::fixTCReturn(), getFramePointerReg(), GVIsIndirectSymbol(), useFastISel(), and llvm::ARMTargetLowering::useLoadStackGuardNode().
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Definition at line 358 of file ARMSubtarget.h.
References llvm::Triple::isOSNaCl(), and TargetTriple.
Referenced by useFastISel().
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Definition at line 359 of file ARMSubtarget.h.
References llvm::Triple::isOSNetBSD(), and TargetTriple.
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Definition at line 360 of file ARMSubtarget.h.
References llvm::Triple::isOSWindows(), and TargetTriple.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMFrameLowering::emitPrologue(), getFramePointerReg(), isTargetAEABI(), isTargetEHABICompatible(), isTargetHardFloat(), and useMovt().
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Definition at line 404 of file ARMSubtarget.h.
References InThumbMode.
Referenced by llvm::ARMFrameLowering::adjustForSegmentedStacks(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMBaseInstrInfo::copyFromCPSR(), llvm::ARMBaseInstrInfo::copyToCPSR(), enablePostRAScheduler(), llvm::ARMFrameLowering::fixTCReturn(), getFramePointerReg(), llvm::ARMTTIImpl::getIntImmCost(), llvm::ARMTargetLowering::getRegForInlineAsmConstraint(), llvm::ARMTargetLowering::getSingleConstraintMatchWeight(), hasAnyDataBarrier(), llvm::ARMTargetLowering::isLegalAddImmediate(), llvm::ARMTargetLowering::isLegalICmpImmediate(), llvm::ARMTargetLowering::LowerAsmOperandForConstraint(), LowerATOMIC_FENCE(), LowerPREFETCH(), llvm::ARMTargetLowering::makeDMB(), and useFastISel().
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Definition at line 405 of file ARMSubtarget.h.
References HasThumb2, and InThumbMode.
Referenced by AddCombineTo64bitMLAL(), llvm::ARMFrameLowering::adjustForSegmentedStacks(), llvm::ARMBaseInstrInfo::areLoadsFromSameBasePtr(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ThumbRegisterInfo::eliminateFrameIndex(), llvm::ThumbRegisterInfo::emitLoadConstPool(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(), enableAtomicExpand(), Expand64BitShift(), llvm::ARMTTIImpl::getFPOpCost(), getFramePointerReg(), llvm::ThumbRegisterInfo::getLargestLegalSuperClass(), llvm::ARMTTIImpl::getNumberOfRegisters(), llvm::ThumbRegisterInfo::getPointerRegClass(), llvm::ARMTargetLowering::getPostIndexedAddressParts(), llvm::ARMTargetLowering::getPreIndexedAddressParts(), llvm::ARMTargetLowering::getRegForInlineAsmConstraint(), isLegalAddressImmediate(), llvm::ARMTargetLowering::isLegalAddressingMode(), IsSingleInstrConstant(), isV6M(), llvm::ARMTargetLowering::LowerAsmOperandForConstraint(), LowerPREFETCH(), PerformANDCombine(), PerformMULCombine(), PerformORCombine(), PerformXORCombine(), llvm::ThumbRegisterInfo::resolveFrameIndex(), llvm::ThumbRegisterInfo::saveScavengerRegister(), llvm::ARMBaseInstrInfo::shouldScheduleLoadsNear(), and useFastISel().
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Definition at line 406 of file ARMSubtarget.h.
References HasThumb2, and InThumbMode.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMBaseInstrInfo::copyPhysReg(), llvm::ARMBaseInstrInfo::CreateTargetPostRAHazardRecognizer(), llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), llvm::ARMTTIImpl::getIntImmCost(), llvm::ARMBaseInstrInfo::getOperandLatency(), llvm::ARMTargetLowering::getPostIndexedAddressParts(), llvm::ARMTargetLowering::getPreIndexedAddressParts(), llvm::ARMTargetLowering::isLegalAddImmediate(), isLegalAddressImmediate(), llvm::ARMTargetLowering::isLegalAddressingMode(), llvm::ARMTargetLowering::isLegalICmpImmediate(), llvm::ARMTargetLowering::LowerAsmOperandForConstraint(), and LowerPREFETCH().
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Definition at line 412 of file ARMSubtarget.h.
References isMClass(), and isThumb1Only().
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
Definition of function is auto generated by tblgen.
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Definition at line 341 of file ARMSubtarget.h.
References Pref32BitThumb.
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Definition at line 424 of file ARMSubtarget.h.
References RestrictIT.
Referenced by llvm::ARMBaseInstrInfo::isPredicable().
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Definition at line 420 of file ARMSubtarget.h.
References SupportsTailCall.
| bool ARMSubtarget::useFastISel | ( | ) | const |
True if fast-isel is used.
Definition at line 344 of file ARMSubtarget.cpp.
References llvm::TargetOptions::EnableFastISel, isTargetLinux(), isTargetMachO(), isTargetNaCl(), isThumb(), isThumb1Only(), llvm::TargetMachine::Options, and TM.
Referenced by llvm::ARM::createFastISel().
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Definition at line 334 of file ARMSubtarget.h.
References SlowFPVMLx.
| bool ARMSubtarget::useMovt | ( | const MachineFunction & | MF | ) | const |
Definition at line 336 of file ARMSubtarget.cpp.
References llvm::MachineFunction::getFunction(), llvm::Function::hasFnAttribute(), isTargetWindows(), llvm::Attribute::MinSize, and UseMovt.
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Definition at line 333 of file ARMSubtarget.h.
References UseMulOps.
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Definition at line 347 of file ARMSubtarget.h.
References UseNaClTrap.
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Definition at line 322 of file ARMSubtarget.h.
References hasNEON(), and UseNEONForSinglePrecisionFP.
Referenced by llvm::ARMTargetLowering::findRepresentativeClass(), and PerformSELECT_CCCombine().
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Definition at line 403 of file ARMSubtarget.h.
References UseSoftFloat.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), and llvm::ARMTargetLowering::useSoftFloat().
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AllowsUnalignedMem - If true, the subtarget allows unaligned memory accesses for some types.
For details, see ARMTargetLowering::allowsMisalignedMemoryAccesses().
Definition at line 196 of file ARMSubtarget.h.
Referenced by allowsUnalignedMem().
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ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
Definition at line 56 of file ARMSubtarget.h.
Referenced by isAClass(), isMClass(), and isRClass().
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ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
Definition at line 53 of file ARMSubtarget.h.
Referenced by isCortexA15(), isCortexA5(), isCortexA7(), isCortexA8(), isCortexA9(), isCortexR5(), isKrait(), and isSwift().
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AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions that partially update CPSR and add false dependency on the previous CPSR setting instruction.
Definition at line 153 of file ARMSubtarget.h.
Referenced by avoidCPSRPartialUpdate().
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AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting movs with shifter operand (i.e.
asr, lsl, lsr).
Definition at line 157 of file ARMSubtarget.h.
Referenced by avoidMOVsShifterOperand().
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CPUString - String name of used CPU.
Definition at line 220 of file ARMSubtarget.h.
Referenced by getCPUString(), and isCortexM3().
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FPOnlySP - If true, the floating point unit only supports single precision.
Definition at line 173 of file ARMSubtarget.h.
Referenced by isFPOnlySP().
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Generate calls via indirect call instructions.
Definition at line 210 of file ARMSubtarget.h.
Referenced by genLongCalls().
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HasCRC - if true, processor supports CRC instructions.
Definition at line 187 of file ARMSubtarget.h.
Referenced by hasCRC().
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HasCrypto - if true, processor supports Cryptography extensions.
Definition at line 184 of file ARMSubtarget.h.
Referenced by hasCrypto().
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HasD16 - True if subtarget is limited to 16 double precision FP registers for VFPv3.
Definition at line 130 of file ARMSubtarget.h.
Referenced by hasD16().
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HasDataBarrier - True if the subtarget supports DMB / DSB data barrier instructions.
Definition at line 144 of file ARMSubtarget.h.
Referenced by hasAnyDataBarrier(), and hasDataBarrier().
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HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF only so far)
Definition at line 126 of file ARMSubtarget.h.
Referenced by hasFP16().
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Definition at line 77 of file ARMSubtarget.h.
Referenced by hasFPARMv8().
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HasHardwareDivide - True if subtarget supports [su]div.
Definition at line 133 of file ARMSubtarget.h.
Referenced by hasDivide().
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HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode.
Definition at line 136 of file ARMSubtarget.h.
Referenced by hasDivideInARMMode().
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HasMPExtension - True if the subtarget supports Multiprocessing extension (ARMv7 only).
Definition at line 165 of file ARMSubtarget.h.
Referenced by hasMPExtension().
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Definition at line 78 of file ARMSubtarget.h.
Referenced by hasNEON().
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If true, the processor supports the Performance Monitor Extensions.
These include a generic cycle-counter as well as more fine-grained (often implementation-specific) events.
Definition at line 178 of file ARMSubtarget.h.
Referenced by hasPerfMon().
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HasRAS - Some processors perform return stack prediction.
CodeGen should avoid issue "normal" call instructions to callees which do not return.
Definition at line 161 of file ARMSubtarget.h.
Referenced by hasRAS().
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HasT2ExtractPack - True if subtarget supports thumb2 extract/pack instructions.
Definition at line 140 of file ARMSubtarget.h.
Referenced by hasT2ExtractPack().
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HasThumb2 - True if Thumb2 instructions are supported.
Definition at line 107 of file ARMSubtarget.h.
Referenced by hasThumb2(), isThumb1Only(), and isThumb2().
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HasTrustZone - if true, processor supports TrustZone security extensions.
Definition at line 181 of file ARMSubtarget.h.
Referenced by hasTrustZone().
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HasV4TOps, HasV5TOps, HasV5TEOps, HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops - Specify whether target support specific ARM ISA variants.
Definition at line 61 of file ARMSubtarget.h.
Referenced by hasV4TOps().
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Definition at line 63 of file ARMSubtarget.h.
Referenced by hasV5TEOps().
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Definition at line 62 of file ARMSubtarget.h.
Referenced by hasV5TOps().
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Definition at line 66 of file ARMSubtarget.h.
Referenced by hasV6KOps().
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Definition at line 65 of file ARMSubtarget.h.
Referenced by hasV6MOps().
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Definition at line 64 of file ARMSubtarget.h.
Referenced by hasV6Ops().
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Definition at line 67 of file ARMSubtarget.h.
Referenced by hasV6T2Ops().
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Definition at line 68 of file ARMSubtarget.h.
Referenced by hasV7Ops().
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Definition at line 70 of file ARMSubtarget.h.
Referenced by hasV8_1aOps().
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Definition at line 69 of file ARMSubtarget.h.
Referenced by hasV8Ops().
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HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what floating point ISAs are supported.
Definition at line 74 of file ARMSubtarget.h.
Referenced by hasVFP2().
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Definition at line 75 of file ARMSubtarget.h.
Referenced by hasVFP3().
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Definition at line 76 of file ARMSubtarget.h.
Referenced by hasVFP4().
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HasVirtualization - True if the subtarget supports the Virtualization extension.
Definition at line 169 of file ARMSubtarget.h.
Referenced by hasVirtualization().
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HasVMLxForwarding - If true, NEON has special multiplier accumulator forwarding to allow mul + mla being issued back to back.
Definition at line 95 of file ARMSubtarget.h.
Referenced by hasVMLxForwarding().
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If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are particularly effective at zeroing a VFP register.
Definition at line 191 of file ARMSubtarget.h.
Referenced by hasZeroCycleZeroing().
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Selected instruction itineraries (one entry per itinerary class.)
Definition at line 232 of file ARMSubtarget.h.
Referenced by getInstrItineraryData().
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InThumbMode - True if compiling for Thumb, false for ARM.
Definition at line 101 of file ARMSubtarget.h.
Referenced by isThumb(), isThumb1Only(), and isThumb2().
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IsLittle - The target is Little Endian.
Definition at line 223 of file ARMSubtarget.h.
Referenced by isLittle().
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IsR9Reserved - True if R9 is a not available as general purpose register.
Definition at line 113 of file ARMSubtarget.h.
Referenced by isR9Reserved().
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NoARM - True if subtarget does not support ARM mode execution.
Definition at line 110 of file ARMSubtarget.h.
Referenced by hasARMOps().
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Options passed via command line that could influence the target.
Definition at line 235 of file ARMSubtarget.h.
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Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions over 16-bit ones.
Definition at line 148 of file ARMSubtarget.h.
Referenced by prefers32BitThumb().
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RestrictIT - If true, the subtarget disallows generation of deprecated IT blocks to conform to ARMv8 rule.
Definition at line 200 of file ARMSubtarget.h.
Referenced by restrictIT().
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SchedModel - Processor specific instruction costs.
Definition at line 229 of file ARMSubtarget.h.
Referenced by getMispredictionPenalty().
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SlowFPBrcc - True if floating point compare + branch is slow.
Definition at line 98 of file ARMSubtarget.h.
Referenced by isFPBrccSlow().
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SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates whether the FP VML[AS] instructions are slow (if so, don't use them).
Definition at line 91 of file ARMSubtarget.h.
Referenced by useFPVMLx().
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stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function.
Definition at line 217 of file ARMSubtarget.h.
Referenced by getStackAlignment().
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SupportsTailCall - True if the OS supports tail call.
The dynamic linker must be able to synthesize call stubs for interworking between ARM and Thumb.
Definition at line 122 of file ARMSubtarget.h.
Referenced by supportsTailCall().
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TargetTriple - What processor and OS we're targeting.
Definition at line 226 of file ARMSubtarget.h.
Referenced by getTargetTriple(), isTargetAEABI(), isTargetAndroid(), isTargetCOFF(), isTargetDarwin(), isTargetEHABICompatible(), isTargetELF(), isTargetHardFloat(), isTargetIOS(), isTargetLinux(), isTargetMachO(), isTargetNaCl(), isTargetNetBSD(), and isTargetWindows().
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Thumb2DSP - If true, the subtarget supports the v7 DSP (saturating arith and such) instructions in Thumb2 code.
Definition at line 204 of file ARMSubtarget.h.
Referenced by hasThumb2DSP().
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Definition at line 237 of file ARMSubtarget.h.
Referenced by isAAPCS_ABI(), isAPCS_ABI(), and useFastISel().
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Target machine allowed unsafe FP math (such as use of NEON fp)
Definition at line 213 of file ARMSubtarget.h.
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UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit imms (including global addresses).
Definition at line 117 of file ARMSubtarget.h.
Referenced by useMovt().
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UseMulOps - True if non-microcoded fused integer multiply-add and multiply-subtract instructions should be used.
Definition at line 87 of file ARMSubtarget.h.
Referenced by useMulOps().
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NaCl TRAP instruction is generated instead of the regular TRAP.
Definition at line 207 of file ARMSubtarget.h.
Referenced by useNaClTrap().
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UseNEONForSinglePrecisionFP - if the NEONFP attribute has been specified.
Use the method useNEONForSinglePrecisionFP() to determine if NEON should actually be used.
Definition at line 83 of file ARMSubtarget.h.
Referenced by useNEONForSinglePrecisionFP().
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UseSoftFloat - True if we're using software floating point features.
Definition at line 104 of file ARMSubtarget.h.
Referenced by useSoftFloat().
1.8.6