LLVM  3.7.0
HexagonFrameLowering.cpp
Go to the documentation of this file.
1 //===-- HexagonFrameLowering.cpp - Define frame lowering ------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //
9 //===----------------------------------------------------------------------===//
10 
11 #define DEBUG_TYPE "hexagon-pei"
12 
13 #include "HexagonFrameLowering.h"
14 #include "Hexagon.h"
15 #include "HexagonInstrInfo.h"
17 #include "HexagonRegisterInfo.h"
18 #include "HexagonSubtarget.h"
19 #include "HexagonTargetMachine.h"
20 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/STLExtras.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/Type.h"
35 #include "llvm/Support/Debug.h"
40 
41 // Hexagon stack frame layout as defined by the ABI:
42 //
43 // Incoming arguments
44 // passed via stack
45 // |
46 // |
47 // SP during function's FP during function's |
48 // +-- runtime (top of stack) runtime (bottom) --+ |
49 // | | |
50 // --++---------------------+------------------+-----------------++-+-------
51 // | parameter area for | variable-size | fixed-size |LR| arg
52 // | called functions | local objects | local objects |FP|
53 // --+----------------------+------------------+-----------------+--+-------
54 // <- size known -> <- size unknown -> <- size known ->
55 //
56 // Low address High address
57 //
58 // <--- stack growth
59 //
60 //
61 // - In any circumstances, the outgoing function arguments are always accessi-
62 // ble using the SP, and the incoming arguments are accessible using the FP.
63 // - If the local objects are not aligned, they can always be accessed using
64 // the FP.
65 // - If there are no variable-sized objects, the local objects can always be
66 // accessed using the SP, regardless whether they are aligned or not. (The
67 // alignment padding will be at the bottom of the stack (highest address),
68 // and so the offset with respect to the SP will be known at the compile-
69 // -time.)
70 //
71 // The only complication occurs if there are both, local aligned objects, and
72 // dynamically allocated (variable-sized) objects. The alignment pad will be
73 // placed between the FP and the local objects, thus preventing the use of the
74 // FP to access the local objects. At the same time, the variable-sized objects
75 // will be between the SP and the local objects, thus introducing an unknown
76 // distance from the SP to the locals.
77 //
78 // To avoid this problem, a new register is created that holds the aligned
79 // address of the bottom of the stack, referred in the sources as AP (aligned
80 // pointer). The AP will be equal to "FP-p", where "p" is the smallest pad
81 // that aligns AP to the required boundary (a maximum of the alignments of
82 // all stack objects, fixed- and variable-sized). All local objects[1] will
83 // then use AP as the base pointer.
84 // [1] The exception is with "fixed" stack objects. "Fixed" stack objects get
85 // their name from being allocated at fixed locations on the stack, relative
86 // to the FP. In the presence of dynamic allocation and local alignment, such
87 // objects can only be accessed through the FP.
88 //
89 // Illustration of the AP:
90 // FP --+
91 // |
92 // ---------------+---------------------+-----+-----------------------++-+--
93 // Rest of the | Local stack objects | Pad | Fixed stack objects |LR|
94 // stack frame | (aligned) | | (CSR, spills, etc.) |FP|
95 // ---------------+---------------------+-----+-----------------+-----+--+--
96 // |<-- Multiple of the -->|
97 // stack alignment +-- AP
98 //
99 // The AP is set up at the beginning of the function. Since it is not a dedi-
100 // cated (reserved) register, it needs to be kept live throughout the function
101 // to be available as the base register for local object accesses.
102 // Normally, an address of a stack objects is obtained by a pseudo-instruction
103 // TFR_FI. To access local objects with the AP register present, a different
104 // pseudo-instruction needs to be used: TFR_FIA. The TFR_FIA takes one extra
105 // argument compared to TFR_FI: the first input register is the AP register.
106 // This keeps the register live between its definition and its uses.
107 
108 // The AP register is originally set up using pseudo-instruction ALIGNA:
109 // AP = ALIGNA A
110 // where
111 // A - required stack alignment
112 // The alignment value must be the maximum of all alignments required by
113 // any stack object.
114 
115 // The dynamic allocation uses a pseudo-instruction ALLOCA:
116 // Rd = ALLOCA Rs, A
117 // where
118 // Rd - address of the allocated space
119 // Rs - minimum size (the actual allocated can be larger to accommodate
120 // alignment)
121 // A - required alignment
122 
123 
124 using namespace llvm;
125 
126 static cl::opt<bool> DisableDeallocRet("disable-hexagon-dealloc-ret",
127  cl::Hidden, cl::desc("Disable Dealloc Return for Hexagon target"));
128 
129 
130 static cl::opt<int> NumberScavengerSlots("number-scavenger-slots",
131  cl::Hidden, cl::desc("Set the number of scavenger slots"), cl::init(2),
133 
134 static cl::opt<int> SpillFuncThreshold("spill-func-threshold",
135  cl::Hidden, cl::desc("Specify O2(not Os) spill func threshold"),
137 
138 static cl::opt<int> SpillFuncThresholdOs("spill-func-threshold-Os",
139  cl::Hidden, cl::desc("Specify Os spill func threshold"),
141 
142 static cl::opt<bool> EnableShrinkWrapping("hexagon-shrink-frame",
144  cl::desc("Enable stack frame shrink wrapping"));
145 
146 static cl::opt<unsigned> ShrinkLimit("shrink-frame-limit", cl::init(UINT_MAX),
147  cl::Hidden, cl::ZeroOrMore, cl::desc("Max count of stack frame "
148  "shrink-wraps"));
149 
150 namespace {
151  /// Map a register pair Reg to the subregister that has the greater "number",
152  /// i.e. D3 (aka R7:6) will be mapped to R7, etc.
153  unsigned getMax32BitSubRegister(unsigned Reg, const TargetRegisterInfo &TRI,
154  bool hireg = true) {
155  if (Reg < Hexagon::D0 || Reg > Hexagon::D15)
156  return Reg;
157 
158  unsigned RegNo = 0;
159  for (MCSubRegIterator SubRegs(Reg, &TRI); SubRegs.isValid(); ++SubRegs) {
160  if (hireg) {
161  if (*SubRegs > RegNo)
162  RegNo = *SubRegs;
163  } else {
164  if (!RegNo || *SubRegs < RegNo)
165  RegNo = *SubRegs;
166  }
167  }
168  return RegNo;
169  }
170 
171  /// Returns the callee saved register with the largest id in the vector.
172  unsigned getMaxCalleeSavedReg(const std::vector<CalleeSavedInfo> &CSI,
173  const TargetRegisterInfo &TRI) {
174  assert(Hexagon::R1 > 0 &&
175  "Assume physical registers are encoded as positive integers");
176  if (CSI.empty())
177  return 0;
178 
179  unsigned Max = getMax32BitSubRegister(CSI[0].getReg(), TRI);
180  for (unsigned I = 1, E = CSI.size(); I < E; ++I) {
181  unsigned Reg = getMax32BitSubRegister(CSI[I].getReg(), TRI);
182  if (Reg > Max)
183  Max = Reg;
184  }
185  return Max;
186  }
187 
188  /// Checks if the basic block contains any instruction that needs a stack
189  /// frame to be already in place.
190  bool needsStackFrame(const MachineBasicBlock &MBB, const BitVector &CSR) {
191  for (auto &I : MBB) {
192  const MachineInstr *MI = &I;
193  if (MI->isCall())
194  return true;
195  unsigned Opc = MI->getOpcode();
196  switch (Opc) {
197  case Hexagon::ALLOCA:
198  case Hexagon::ALIGNA:
199  return true;
200  default:
201  break;
202  }
203  // Check individual operands.
204  for (const MachineOperand &MO : MI->operands()) {
205  // While the presence of a frame index does not prove that a stack
206  // frame will be required, all frame indexes should be within alloc-
207  // frame/deallocframe. Otherwise, the code that translates a frame
208  // index into an offset would have to be aware of the placement of
209  // the frame creation/destruction instructions.
210  if (MO.isFI())
211  return true;
212  if (!MO.isReg())
213  continue;
214  unsigned R = MO.getReg();
215  // Virtual registers will need scavenging, which then may require
216  // a stack slot.
218  return true;
219  if (CSR[R])
220  return true;
221  }
222  }
223  return false;
224  }
225 
226  /// Returns true if MBB has a machine instructions that indicates a tail call
227  /// in the block.
228  bool hasTailCall(const MachineBasicBlock &MBB) {
230  unsigned RetOpc = I->getOpcode();
231  return RetOpc == Hexagon::TCRETURNi || RetOpc == Hexagon::TCRETURNr;
232  }
233 
234  /// Returns true if MBB contains an instruction that returns.
235  bool hasReturn(const MachineBasicBlock &MBB) {
236  for (auto I = MBB.getFirstTerminator(), E = MBB.end(); I != E; ++I)
237  if (I->isReturn())
238  return true;
239  return false;
240  }
241 }
242 
243 
244 /// Implements shrink-wrapping of the stack frame. By default, stack frame
245 /// is created in the function entry block, and is cleaned up in every block
246 /// that returns. This function finds alternate blocks: one for the frame
247 /// setup (prolog) and one for the cleanup (epilog).
248 void HexagonFrameLowering::findShrunkPrologEpilog(MachineFunction &MF,
249  MachineBasicBlock *&PrologB, MachineBasicBlock *&EpilogB) const {
250  static unsigned ShrinkCounter = 0;
251 
252  if (ShrinkLimit.getPosition()) {
253  if (ShrinkCounter >= ShrinkLimit)
254  return;
255  ShrinkCounter++;
256  }
257 
258  auto &HST = static_cast<const HexagonSubtarget&>(MF.getSubtarget());
259  auto &HRI = *HST.getRegisterInfo();
260 
262  MDT.runOnMachineFunction(MF);
264  MPT.runOnMachineFunction(MF);
265 
266  typedef DenseMap<unsigned,unsigned> UnsignedMap;
267  UnsignedMap RPO;
269  RPOTType RPOT(&MF);
270  unsigned RPON = 0;
271  for (RPOTType::rpo_iterator I = RPOT.begin(), E = RPOT.end(); I != E; ++I)
272  RPO[(*I)->getNumber()] = RPON++;
273 
274  // Don't process functions that have loops, at least for now. Placement
275  // of prolog and epilog must take loop structure into account. For simpli-
276  // city don't do it right now.
277  for (auto &I : MF) {
278  unsigned BN = RPO[I.getNumber()];
279  for (auto SI = I.succ_begin(), SE = I.succ_end(); SI != SE; ++SI) {
280  // If found a back-edge, return.
281  if (RPO[(*SI)->getNumber()] <= BN)
282  return;
283  }
284  }
285 
286  // Collect the set of blocks that need a stack frame to execute. Scan
287  // each block for uses/defs of callee-saved registers, calls, etc.
289  BitVector CSR(Hexagon::NUM_TARGET_REGS);
290  for (const MCPhysReg *P = HRI.getCalleeSavedRegs(&MF); *P; ++P)
291  CSR[*P] = true;
292 
293  for (auto &I : MF)
294  if (needsStackFrame(I, CSR))
295  SFBlocks.push_back(&I);
296 
297  DEBUG({
298  dbgs() << "Blocks needing SF: {";
299  for (auto &B : SFBlocks)
300  dbgs() << " BB#" << B->getNumber();
301  dbgs() << " }\n";
302  });
303  // No frame needed?
304  if (SFBlocks.empty())
305  return;
306 
307  // Pick a common dominator and a common post-dominator.
308  MachineBasicBlock *DomB = SFBlocks[0];
309  for (unsigned i = 1, n = SFBlocks.size(); i < n; ++i) {
310  DomB = MDT.findNearestCommonDominator(DomB, SFBlocks[i]);
311  if (!DomB)
312  break;
313  }
314  MachineBasicBlock *PDomB = SFBlocks[0];
315  for (unsigned i = 1, n = SFBlocks.size(); i < n; ++i) {
316  PDomB = MPT.findNearestCommonDominator(PDomB, SFBlocks[i]);
317  if (!PDomB)
318  break;
319  }
320  DEBUG({
321  dbgs() << "Computed dom block: BB#";
322  if (DomB) dbgs() << DomB->getNumber();
323  else dbgs() << "<null>";
324  dbgs() << ", computed pdom block: BB#";
325  if (PDomB) dbgs() << PDomB->getNumber();
326  else dbgs() << "<null>";
327  dbgs() << "\n";
328  });
329  if (!DomB || !PDomB)
330  return;
331 
332  // Make sure that DomB dominates PDomB and PDomB post-dominates DomB.
333  if (!MDT.dominates(DomB, PDomB)) {
334  DEBUG(dbgs() << "Dom block does not dominate pdom block\n");
335  return;
336  }
337  if (!MPT.dominates(PDomB, DomB)) {
338  DEBUG(dbgs() << "PDom block does not post-dominate dom block\n");
339  return;
340  }
341 
342  // Finally, everything seems right.
343  PrologB = DomB;
344  EpilogB = PDomB;
345 }
346 
347 /// Perform most of the PEI work here:
348 /// - saving/restoring of the callee-saved registers,
349 /// - stack frame creation and destruction.
350 /// Normally, this work is distributed among various functions, but doing it
351 /// in one place allows shrink-wrapping of the stack frame.
353  MachineBasicBlock &MBB) const {
354  auto &HST = static_cast<const HexagonSubtarget&>(MF.getSubtarget());
355  auto &HRI = *HST.getRegisterInfo();
356 
357  assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
358  MachineFrameInfo *MFI = MF.getFrameInfo();
359  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
360 
361  MachineBasicBlock *PrologB = &MF.front(), *EpilogB = nullptr;
363  findShrunkPrologEpilog(MF, PrologB, EpilogB);
364 
365  insertCSRSpillsInBlock(*PrologB, CSI, HRI);
366  insertPrologueInBlock(*PrologB);
367 
368  if (EpilogB) {
369  insertCSRRestoresInBlock(*EpilogB, CSI, HRI);
370  insertEpilogueInBlock(*EpilogB);
371  } else {
372  for (auto &B : MF)
373  if (!B.empty() && B.back().isReturn())
374  insertCSRRestoresInBlock(B, CSI, HRI);
375 
376  for (auto &B : MF)
377  if (!B.empty() && B.back().isReturn())
378  insertEpilogueInBlock(B);
379  }
380 }
381 
382 
383 void HexagonFrameLowering::insertPrologueInBlock(MachineBasicBlock &MBB) const {
384  MachineFunction &MF = *MBB.getParent();
385  MachineFrameInfo *MFI = MF.getFrameInfo();
386  MachineModuleInfo &MMI = MF.getMMI();
387  MachineBasicBlock::iterator MBBI = MBB.begin();
388  auto &HTM = static_cast<const HexagonTargetMachine&>(MF.getTarget());
389  auto &HST = static_cast<const HexagonSubtarget&>(MF.getSubtarget());
390  auto &HII = *HST.getInstrInfo();
391  auto &HRI = *HST.getRegisterInfo();
392  DebugLoc dl;
393 
394  unsigned MaxAlign = std::max(MFI->getMaxAlignment(), getStackAlignment());
395 
396  // Calculate the total stack frame size.
397  // Get the number of bytes to allocate from the FrameInfo.
398  unsigned FrameSize = MFI->getStackSize();
399  // Round up the max call frame size to the max alignment on the stack.
400  unsigned MaxCFA = RoundUpToAlignment(MFI->getMaxCallFrameSize(), MaxAlign);
401  MFI->setMaxCallFrameSize(MaxCFA);
402 
403  FrameSize = MaxCFA + RoundUpToAlignment(FrameSize, MaxAlign);
404  MFI->setStackSize(FrameSize);
405 
406  bool AlignStack = (MaxAlign > getStackAlignment());
407 
408  // Check if frame moves are needed for EH.
409  bool needsFrameMoves = MMI.hasDebugInfo() ||
411 
412  // Get the number of bytes to allocate from the FrameInfo.
413  unsigned NumBytes = MFI->getStackSize();
414  unsigned SP = HRI.getStackRegister();
415  unsigned MaxCF = MFI->getMaxCallFrameSize();
416  MachineBasicBlock::iterator InsertPt = MBB.begin();
417 
418  auto *FuncInfo = MF.getInfo<HexagonMachineFunctionInfo>();
419  auto &AdjustRegs = FuncInfo->getAllocaAdjustInsts();
420 
421  for (auto MI : AdjustRegs) {
422  assert((MI->getOpcode() == Hexagon::ALLOCA) && "Expected alloca");
423  expandAlloca(MI, HII, SP, MaxCF);
424  MI->eraseFromParent();
425  }
426 
427  //
428  // Only insert ALLOCFRAME if we need to or at -O0 for the debugger. Think
429  // that this shouldn't be required, but doing so now because gcc does and
430  // gdb can't break at the start of the function without it. Will remove if
431  // this turns out to be a gdb bug.
432  //
433  bool NoOpt = (HTM.getOptLevel() == CodeGenOpt::None);
434  if (!NoOpt && !FuncInfo->hasClobberLR() && !hasFP(MF))
435  return;
436 
437  // Check for overflow.
438  // Hexagon_TODO: Ugh! hardcoding. Is there an API that can be used?
439  const unsigned int ALLOCFRAME_MAX = 16384;
440 
441  // Create a dummy memory operand to avoid allocframe from being treated as
442  // a volatile memory reference.
443  MachineMemOperand *MMO =
445  4, 4);
446 
447  if (NumBytes >= ALLOCFRAME_MAX) {
448  // Emit allocframe(#0).
449  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_allocframe))
450  .addImm(0)
451  .addMemOperand(MMO);
452 
453  // Subtract offset from frame pointer.
454  // We use a caller-saved non-parameter register for that.
455  unsigned CallerSavedReg = HRI.getFirstCallerSavedNonParamReg();
456  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::CONST32_Int_Real),
457  CallerSavedReg).addImm(NumBytes);
458  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_sub), SP)
459  .addReg(SP)
460  .addReg(CallerSavedReg);
461  } else {
462  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_allocframe))
463  .addImm(NumBytes)
464  .addMemOperand(MMO);
465  }
466 
467  if (AlignStack) {
468  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_andir), SP)
469  .addReg(SP)
470  .addImm(-int64_t(MaxAlign));
471  }
472 
473  if (needsFrameMoves) {
474  std::vector<MCCFIInstruction> Instructions = MMI.getFrameInstructions();
475  MCSymbol *FrameLabel = MMI.getContext().createTempSymbol();
476 
477  // Advance CFA. DW_CFA_def_cfa
478  unsigned DwFPReg = HRI.getDwarfRegNum(HRI.getFrameRegister(), true);
479  unsigned DwRAReg = HRI.getDwarfRegNum(HRI.getRARegister(), true);
480 
481  // CFA = FP + 8
482  unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfa(
483  FrameLabel, DwFPReg, -8));
484  BuildMI(MBB, MBBI, dl, HII.get(TargetOpcode::CFI_INSTRUCTION))
485  .addCFIIndex(CFIIndex);
486 
487  // R31 (return addr) = CFA - #4
489  FrameLabel, DwRAReg, -4));
490  BuildMI(MBB, MBBI, dl, HII.get(TargetOpcode::CFI_INSTRUCTION))
491  .addCFIIndex(CFIIndex);
492 
493  // R30 (frame ptr) = CFA - #8)
495  FrameLabel, DwFPReg, -8));
496  BuildMI(MBB, MBBI, dl, HII.get(TargetOpcode::CFI_INSTRUCTION))
497  .addCFIIndex(CFIIndex);
498 
499  unsigned int regsToMove[] = {
500  Hexagon::R1, Hexagon::R0, Hexagon::R3, Hexagon::R2,
501  Hexagon::R17, Hexagon::R16, Hexagon::R19, Hexagon::R18,
502  Hexagon::R21, Hexagon::R20, Hexagon::R23, Hexagon::R22,
503  Hexagon::R25, Hexagon::R24, Hexagon::R27, Hexagon::R26,
504  Hexagon::D0, Hexagon::D1, Hexagon::D8, Hexagon::D9, Hexagon::D10,
505  Hexagon::D11, Hexagon::D12, Hexagon::D13, Hexagon::NoRegister
506  };
507 
508  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
509 
510  for (unsigned i = 0; regsToMove[i] != Hexagon::NoRegister; ++i) {
511  for (unsigned I = 0, E = CSI.size(); I < E; ++I) {
512  if (CSI[I].getReg() == regsToMove[i]) {
513  // Subtract 8 to make room for R30 and R31, which are added above.
514  int64_t Offset = getFrameIndexOffset(MF, CSI[I].getFrameIdx()) - 8;
515 
516  if (regsToMove[i] < Hexagon::D0 || regsToMove[i] > Hexagon::D15) {
517  unsigned DwarfReg = HRI.getDwarfRegNum(regsToMove[i], true);
518  unsigned CFIIndex = MMI.addFrameInst(
520  DwarfReg, Offset));
521  BuildMI(MBB, MBBI, dl, HII.get(TargetOpcode::CFI_INSTRUCTION))
522  .addCFIIndex(CFIIndex);
523  } else {
524  // Split the double regs into subregs, and generate appropriate
525  // cfi_offsets.
526  // The only reason, we are split double regs is, llvm-mc does not
527  // understand paired registers for cfi_offset.
528  // Eg .cfi_offset r1:0, -64
529  unsigned HiReg = getMax32BitSubRegister(regsToMove[i], HRI);
530  unsigned LoReg = getMax32BitSubRegister(regsToMove[i], HRI, false);
531  unsigned HiDwarfReg = HRI.getDwarfRegNum(HiReg, true);
532  unsigned LoDwarfReg = HRI.getDwarfRegNum(LoReg, true);
533  unsigned HiCFIIndex = MMI.addFrameInst(
535  HiDwarfReg, Offset+4));
536  BuildMI(MBB, MBBI, dl, HII.get(TargetOpcode::CFI_INSTRUCTION))
537  .addCFIIndex(HiCFIIndex);
538  unsigned LoCFIIndex = MMI.addFrameInst(
540  LoDwarfReg, Offset));
541  BuildMI(MBB, MBBI, dl, HII.get(TargetOpcode::CFI_INSTRUCTION))
542  .addCFIIndex(LoCFIIndex);
543  }
544  break;
545  }
546  } // for CSI.size()
547  } // for regsToMove
548  } // needsFrameMoves
549 }
550 
551 void HexagonFrameLowering::insertEpilogueInBlock(MachineBasicBlock &MBB) const {
552  MachineFunction &MF = *MBB.getParent();
553  //
554  // Only insert deallocframe if we need to. Also at -O0. See comment
555  // in insertPrologueInBlock above.
556  //
557  if (!hasFP(MF) && MF.getTarget().getOptLevel() != CodeGenOpt::None)
558  return;
559 
560  auto &HST = static_cast<const HexagonSubtarget&>(MF.getSubtarget());
561  auto &HII = *HST.getInstrInfo();
562  auto &HRI = *HST.getRegisterInfo();
563  unsigned SP = HRI.getStackRegister();
564 
565  MachineInstr *RetI = nullptr;
566  for (auto &I : MBB) {
567  if (!I.isReturn())
568  continue;
569  RetI = &I;
570  break;
571  }
572  unsigned RetOpc = RetI ? RetI->getOpcode() : 0;
573 
574  MachineBasicBlock::iterator InsertPt = MBB.getFirstTerminator();
575  DebugLoc DL;
576  if (InsertPt != MBB.end())
577  DL = InsertPt->getDebugLoc();
578  else if (!MBB.empty())
579  DL = std::prev(MBB.end())->getDebugLoc();
580 
581  // Handle EH_RETURN.
582  if (RetOpc == Hexagon::EH_RETURN_JMPR) {
583  BuildMI(MBB, InsertPt, DL, HII.get(Hexagon::L2_deallocframe));
584  BuildMI(MBB, InsertPt, DL, HII.get(Hexagon::A2_add), SP)
585  .addReg(SP)
586  .addReg(Hexagon::R28);
587  return;
588  }
589 
590  // Check for RESTORE_DEALLOC_RET* tail call. Don't emit an extra dealloc-
591  // frame instruction if we encounter it.
592  if (RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4) {
593  MachineBasicBlock::iterator It = RetI;
594  ++It;
595  // Delete all instructions after the RESTORE (except labels).
596  while (It != MBB.end()) {
597  if (!It->isLabel())
598  It = MBB.erase(It);
599  else
600  ++It;
601  }
602  return;
603  }
604 
605  // It is possible that the restoring code is a call to a library function.
606  // All of the restore* functions include "deallocframe", so we need to make
607  // sure that we don't add an extra one.
608  bool NeedsDeallocframe = true;
609  if (!MBB.empty() && InsertPt != MBB.begin()) {
610  MachineBasicBlock::iterator PrevIt = std::prev(InsertPt);
611  unsigned COpc = PrevIt->getOpcode();
612  if (COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4)
613  NeedsDeallocframe = false;
614  }
615 
616  if (!NeedsDeallocframe)
617  return;
618  // If the returning instruction is JMPret, replace it with dealloc_return,
619  // otherwise just add deallocframe. The function could be returning via a
620  // tail call.
621  if (RetOpc != Hexagon::JMPret || DisableDeallocRet) {
622  BuildMI(MBB, InsertPt, DL, HII.get(Hexagon::L2_deallocframe));
623  return;
624  }
625  unsigned NewOpc = Hexagon::L4_return;
626  MachineInstr *NewI = BuildMI(MBB, RetI, DL, HII.get(NewOpc));
627  // Transfer the function live-out registers.
628  NewI->copyImplicitOps(MF, RetI);
629  MBB.erase(RetI);
630 }
631 
632 
634  const MachineFrameInfo *MFI = MF.getFrameInfo();
635  const HexagonMachineFunctionInfo *FuncInfo =
637  return MFI->hasCalls() || MFI->getStackSize() > 0 ||
638  FuncInfo->hasClobberLR();
639 }
640 
641 
642 enum SpillKind {
646 };
647 
648 static const char *
649 getSpillFunctionFor(unsigned MaxReg, SpillKind SpillType) {
650  const char * V4SpillToMemoryFunctions[] = {
651  "__save_r16_through_r17",
652  "__save_r16_through_r19",
653  "__save_r16_through_r21",
654  "__save_r16_through_r23",
655  "__save_r16_through_r25",
656  "__save_r16_through_r27" };
657 
658  const char * V4SpillFromMemoryFunctions[] = {
659  "__restore_r16_through_r17_and_deallocframe",
660  "__restore_r16_through_r19_and_deallocframe",
661  "__restore_r16_through_r21_and_deallocframe",
662  "__restore_r16_through_r23_and_deallocframe",
663  "__restore_r16_through_r25_and_deallocframe",
664  "__restore_r16_through_r27_and_deallocframe" };
665 
666  const char * V4SpillFromMemoryTailcallFunctions[] = {
667  "__restore_r16_through_r17_and_deallocframe_before_tailcall",
668  "__restore_r16_through_r19_and_deallocframe_before_tailcall",
669  "__restore_r16_through_r21_and_deallocframe_before_tailcall",
670  "__restore_r16_through_r23_and_deallocframe_before_tailcall",
671  "__restore_r16_through_r25_and_deallocframe_before_tailcall",
672  "__restore_r16_through_r27_and_deallocframe_before_tailcall"
673  };
674 
675  const char **SpillFunc = nullptr;
676 
677  switch(SpillType) {
678  case SK_ToMem:
679  SpillFunc = V4SpillToMemoryFunctions;
680  break;
681  case SK_FromMem:
682  SpillFunc = V4SpillFromMemoryFunctions;
683  break;
684  case SK_FromMemTailcall:
685  SpillFunc = V4SpillFromMemoryTailcallFunctions;
686  break;
687  }
688  assert(SpillFunc && "Unknown spill kind");
689 
690  // Spill all callee-saved registers up to the highest register used.
691  switch (MaxReg) {
692  case Hexagon::R17:
693  return SpillFunc[0];
694  case Hexagon::R19:
695  return SpillFunc[1];
696  case Hexagon::R21:
697  return SpillFunc[2];
698  case Hexagon::R23:
699  return SpillFunc[3];
700  case Hexagon::R25:
701  return SpillFunc[4];
702  case Hexagon::R27:
703  return SpillFunc[5];
704  default:
705  llvm_unreachable("Unhandled maximum callee save register");
706  }
707  return 0;
708 }
709 
710 /// Adds all callee-saved registers up to MaxReg to the instruction.
712  unsigned MaxReg, bool IsDef) {
713  // Add the callee-saved registers as implicit uses.
714  for (unsigned R = Hexagon::R16; R <= MaxReg; ++R) {
715  MachineOperand ImpUse = MachineOperand::CreateReg(R, IsDef, true);
716  Inst->addOperand(ImpUse);
717  }
718 }
719 
720 
722  int FI) const {
723  return MF.getFrameInfo()->getObjectOffset(FI);
724 }
725 
726 
727 bool HexagonFrameLowering::insertCSRSpillsInBlock(MachineBasicBlock &MBB,
728  const CSIVect &CSI, const HexagonRegisterInfo &HRI) const {
729  if (CSI.empty())
730  return true;
731 
733  MachineFunction &MF = *MBB.getParent();
734  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
735 
736  if (useSpillFunction(MF, CSI)) {
737  unsigned MaxReg = getMaxCalleeSavedReg(CSI, HRI);
738  const char *SpillFun = getSpillFunctionFor(MaxReg, SK_ToMem);
739  // Call spill function.
740  DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();
741  MachineInstr *SaveRegsCall =
742  BuildMI(MBB, MI, DL, TII.get(Hexagon::SAVE_REGISTERS_CALL_V4))
743  .addExternalSymbol(SpillFun);
744  // Add callee-saved registers as use.
745  addCalleeSaveRegistersAsImpOperand(SaveRegsCall, MaxReg, false);
746  // Add live in registers.
747  for (unsigned I = 0; I < CSI.size(); ++I)
748  MBB.addLiveIn(CSI[I].getReg());
749  return true;
750  }
751 
752  for (unsigned i = 0, n = CSI.size(); i < n; ++i) {
753  unsigned Reg = CSI[i].getReg();
754  // Add live in registers. We treat eh_return callee saved register r0 - r3
755  // specially. They are not really callee saved registers as they are not
756  // supposed to be killed.
757  bool IsKill = !HRI.isEHReturnCalleeSaveReg(Reg);
758  int FI = CSI[i].getFrameIdx();
759  const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg);
760  TII.storeRegToStackSlot(MBB, MI, Reg, IsKill, FI, RC, &HRI);
761  if (IsKill)
762  MBB.addLiveIn(Reg);
763  }
764  return true;
765 }
766 
767 
768 bool HexagonFrameLowering::insertCSRRestoresInBlock(MachineBasicBlock &MBB,
769  const CSIVect &CSI, const HexagonRegisterInfo &HRI) const {
770  if (CSI.empty())
771  return false;
772 
774  MachineFunction &MF = *MBB.getParent();
775  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
776 
777  if (useRestoreFunction(MF, CSI)) {
778  bool HasTC = hasTailCall(MBB) || !hasReturn(MBB);
779  unsigned MaxR = getMaxCalleeSavedReg(CSI, HRI);
781  const char *RestoreFn = getSpillFunctionFor(MaxR, Kind);
782 
783  // Call spill function.
784  DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc()
785  : MBB.getLastNonDebugInstr()->getDebugLoc();
786  MachineInstr *DeallocCall = nullptr;
787 
788  if (HasTC) {
789  unsigned ROpc = Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4;
790  DeallocCall = BuildMI(MBB, MI, DL, TII.get(ROpc))
791  .addExternalSymbol(RestoreFn);
792  } else {
793  // The block has a return.
795  assert(It->isReturn() && std::next(It) == MBB.end());
796  unsigned ROpc = Hexagon::RESTORE_DEALLOC_RET_JMP_V4;
797  DeallocCall = BuildMI(MBB, It, DL, TII.get(ROpc))
798  .addExternalSymbol(RestoreFn);
799  // Transfer the function live-out registers.
800  DeallocCall->copyImplicitOps(MF, It);
801  }
802  addCalleeSaveRegistersAsImpOperand(DeallocCall, MaxR, true);
803  return true;
804  }
805 
806  for (unsigned i = 0; i < CSI.size(); ++i) {
807  unsigned Reg = CSI[i].getReg();
808  const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg);
809  int FI = CSI[i].getFrameIdx();
810  TII.loadRegFromStackSlot(MBB, MI, Reg, FI, RC, &HRI);
811  }
812  return true;
813 }
814 
815 
818  MachineInstr &MI = *I;
819  unsigned Opc = MI.getOpcode();
820  (void)Opc; // Silence compiler warning.
821  assert((Opc == Hexagon::ADJCALLSTACKDOWN || Opc == Hexagon::ADJCALLSTACKUP) &&
822  "Cannot handle this call frame pseudo instruction");
823  MBB.erase(I);
824 }
825 
826 
828  MachineFunction &MF, RegScavenger *RS) const {
829  // If this function has uses aligned stack and also has variable sized stack
830  // objects, then we need to map all spill slots to fixed positions, so that
831  // they can be accessed through FP. Otherwise they would have to be accessed
832  // via AP, which may not be available at the particular place in the program.
833  MachineFrameInfo *MFI = MF.getFrameInfo();
834  bool HasAlloca = MFI->hasVarSizedObjects();
835  bool HasAligna = (MFI->getMaxAlignment() > getStackAlignment());
836 
837  if (!HasAlloca || !HasAligna)
838  return;
839 
840  unsigned LFS = MFI->getLocalFrameSize();
841  int Offset = -LFS;
842  for (int i = 0, e = MFI->getObjectIndexEnd(); i != e; ++i) {
843  if (!MFI->isSpillSlotObjectIndex(i) || MFI->isDeadObjectIndex(i))
844  continue;
845  int S = MFI->getObjectSize(i);
846  LFS += S;
847  Offset -= S;
848  MFI->mapLocalFrameObject(i, Offset);
849  }
850 
851  MFI->setLocalFrameSize(LFS);
852  unsigned A = MFI->getLocalFrameMaxAlign();
853  assert(A <= 8 && "Unexpected local frame alignment");
854  if (A == 0)
855  MFI->setLocalFrameMaxAlign(8);
857 }
858 
859 /// Returns true if there is no caller saved registers available.
861  const HexagonRegisterInfo &HRI) {
862  MachineRegisterInfo &MRI = MF.getRegInfo();
863  const MCPhysReg *CallerSavedRegs = HRI.getCallerSavedRegs(&MF);
864  // Check for an unused caller-saved register.
865  for ( ; *CallerSavedRegs; ++CallerSavedRegs) {
866  MCPhysReg FreeReg = *CallerSavedRegs;
867  if (MRI.isPhysRegUsed(FreeReg))
868  continue;
869 
870  // Check aliased register usage.
871  bool IsCurrentRegUsed = false;
872  for (MCRegAliasIterator AI(FreeReg, &HRI, false); AI.isValid(); ++AI)
873  if (MRI.isPhysRegUsed(*AI)) {
874  IsCurrentRegUsed = true;
875  break;
876  }
877  if (IsCurrentRegUsed)
878  continue;
879 
880  // Neither directly used nor used through an aliased register.
881  return false;
882  }
883  // All caller-saved registers are used.
884  return true;
885 }
886 
887 
888 /// Replaces the predicate spill code pseudo instructions by valid instructions.
889 bool HexagonFrameLowering::replacePredRegPseudoSpillCode(MachineFunction &MF)
890  const {
891  auto &HST = static_cast<const HexagonSubtarget&>(MF.getSubtarget());
892  auto &HII = *HST.getInstrInfo();
893  MachineRegisterInfo &MRI = MF.getRegInfo();
894  bool HasReplacedPseudoInst = false;
895  // Replace predicate spill pseudo instructions by real code.
896  // Loop over all of the basic blocks.
897  for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end();
898  MBBb != MBBe; ++MBBb) {
899  MachineBasicBlock* MBB = MBBb;
900  // Traverse the basic block.
902  for (MachineBasicBlock::iterator MII = MBB->begin(); MII != MBB->end();
903  MII = NextII) {
904  MachineInstr *MI = MII;
905  NextII = std::next(MII);
906  int Opc = MI->getOpcode();
907  if (Opc == Hexagon::STriw_pred) {
908  HasReplacedPseudoInst = true;
909  // STriw_pred FI, 0, SrcReg;
910  unsigned VirtReg = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
911  unsigned SrcReg = MI->getOperand(2).getReg();
912  bool IsOrigSrcRegKilled = MI->getOperand(2).isKill();
913 
914  assert(MI->getOperand(0).isFI() && "Expect a frame index");
915  assert(Hexagon::PredRegsRegClass.contains(SrcReg) &&
916  "Not a predicate register");
917 
918  // Insert transfer to general purpose register.
919  // VirtReg = C2_tfrpr SrcPredReg
920  BuildMI(*MBB, MII, MI->getDebugLoc(), HII.get(Hexagon::C2_tfrpr),
921  VirtReg).addReg(SrcReg, getKillRegState(IsOrigSrcRegKilled));
922 
923  // Change instruction to S2_storeri_io.
924  // S2_storeri_io FI, 0, VirtReg
925  MI->setDesc(HII.get(Hexagon::S2_storeri_io));
926  MI->getOperand(2).setReg(VirtReg);
927  MI->getOperand(2).setIsKill();
928 
929  } else if (Opc == Hexagon::LDriw_pred) {
930  // DstReg = LDriw_pred FI, 0
931  MachineOperand &M0 = MI->getOperand(0);
932  if (M0.isDead()) {
933  MBB->erase(MII);
934  continue;
935  }
936 
937  unsigned VirtReg = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
938  unsigned DestReg = MI->getOperand(0).getReg();
939 
940  assert(MI->getOperand(1).isFI() && "Expect a frame index");
941  assert(Hexagon::PredRegsRegClass.contains(DestReg) &&
942  "Not a predicate register");
943 
944  // Change instruction to L2_loadri_io.
945  // VirtReg = L2_loadri_io FI, 0
946  MI->setDesc(HII.get(Hexagon::L2_loadri_io));
947  MI->getOperand(0).setReg(VirtReg);
948 
949  // Insert transfer to general purpose register.
950  // DestReg = C2_tfrrp VirtReg
951  const MCInstrDesc &D = HII.get(Hexagon::C2_tfrrp);
952  BuildMI(*MBB, std::next(MII), MI->getDebugLoc(), D, DestReg)
953  .addReg(VirtReg, getKillRegState(true));
954  HasReplacedPseudoInst = true;
955  }
956  }
957  }
958  return HasReplacedPseudoInst;
959 }
960 
961 
963  BitVector &SavedRegs,
964  RegScavenger *RS) const {
966 
967  auto &HST = static_cast<const HexagonSubtarget&>(MF.getSubtarget());
968  auto &HRI = *HST.getRegisterInfo();
969 
970  bool HasEHReturn = MF.getInfo<HexagonMachineFunctionInfo>()->hasEHReturn();
971 
972  // If we have a function containing __builtin_eh_return we want to spill and
973  // restore all callee saved registers. Pretend that they are used.
974  if (HasEHReturn) {
975  for (const MCPhysReg *CSRegs = HRI.getCalleeSavedRegs(&MF); *CSRegs;
976  ++CSRegs)
977  SavedRegs.set(*CSRegs);
978  }
979 
980  const TargetRegisterClass &RC = Hexagon::IntRegsRegClass;
981 
982  // Replace predicate register pseudo spill code.
983  bool HasReplacedPseudoInst = replacePredRegPseudoSpillCode(MF);
984 
985  // We need to reserve a a spill slot if scavenging could potentially require
986  // spilling a scavenged register.
987  if (HasReplacedPseudoInst && needToReserveScavengingSpillSlots(MF, HRI)) {
988  MachineFrameInfo *MFI = MF.getFrameInfo();
989  for (int i=0; i < NumberScavengerSlots; i++)
991  MFI->CreateSpillStackObject(RC.getSize(), RC.getAlignment()));
992  }
993 }
994 
995 
996 #ifndef NDEBUG
997 static void dump_registers(BitVector &Regs, const TargetRegisterInfo &TRI) {
998  dbgs() << '{';
999  for (int x = Regs.find_first(); x >= 0; x = Regs.find_next(x)) {
1000  unsigned R = x;
1001  dbgs() << ' ' << PrintReg(R, &TRI);
1002  }
1003  dbgs() << " }";
1004 }
1005 #endif
1006 
1007 
1009  const TargetRegisterInfo *TRI, std::vector<CalleeSavedInfo> &CSI) const {
1010  DEBUG(dbgs() << LLVM_FUNCTION_NAME << " on "
1011  << MF.getFunction()->getName() << '\n');
1012  MachineFrameInfo *MFI = MF.getFrameInfo();
1013  BitVector SRegs(Hexagon::NUM_TARGET_REGS);
1014 
1015  // Generate a set of unique, callee-saved registers (SRegs), where each
1016  // register in the set is maximal in terms of sub-/super-register relation,
1017  // i.e. for each R in SRegs, no proper super-register of R is also in SRegs.
1018 
1019  // (1) For each callee-saved register, add that register and all of its
1020  // sub-registers to SRegs.
1021  DEBUG(dbgs() << "Initial CS registers: {");
1022  for (unsigned i = 0, n = CSI.size(); i < n; ++i) {
1023  unsigned R = CSI[i].getReg();
1024  DEBUG(dbgs() << ' ' << PrintReg(R, TRI));
1025  for (MCSubRegIterator SR(R, TRI, true); SR.isValid(); ++SR)
1026  SRegs[*SR] = true;
1027  }
1028  DEBUG(dbgs() << " }\n");
1029  DEBUG(dbgs() << "SRegs.1: "; dump_registers(SRegs, *TRI); dbgs() << "\n");
1030 
1031  // (2) For each reserved register, remove that register and all of its
1032  // sub- and super-registers from SRegs.
1033  BitVector Reserved = TRI->getReservedRegs(MF);
1034  for (int x = Reserved.find_first(); x >= 0; x = Reserved.find_next(x)) {
1035  unsigned R = x;
1036  for (MCSuperRegIterator SR(R, TRI, true); SR.isValid(); ++SR)
1037  SRegs[*SR] = false;
1038  }
1039  DEBUG(dbgs() << "Res: "; dump_registers(Reserved, *TRI); dbgs() << "\n");
1040  DEBUG(dbgs() << "SRegs.2: "; dump_registers(SRegs, *TRI); dbgs() << "\n");
1041 
1042  // (3) Collect all registers that have at least one sub-register in SRegs,
1043  // and also have no sub-registers that are reserved. These will be the can-
1044  // didates for saving as a whole instead of their individual sub-registers.
1045  // (Saving R17:16 instead of R16 is fine, but only if R17 was not reserved.)
1046  BitVector TmpSup(Hexagon::NUM_TARGET_REGS);
1047  for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1048  unsigned R = x;
1049  for (MCSuperRegIterator SR(R, TRI); SR.isValid(); ++SR)
1050  TmpSup[*SR] = true;
1051  }
1052  for (int x = TmpSup.find_first(); x >= 0; x = TmpSup.find_next(x)) {
1053  unsigned R = x;
1054  for (MCSubRegIterator SR(R, TRI, true); SR.isValid(); ++SR) {
1055  if (!Reserved[*SR])
1056  continue;
1057  TmpSup[R] = false;
1058  break;
1059  }
1060  }
1061  DEBUG(dbgs() << "TmpSup: "; dump_registers(TmpSup, *TRI); dbgs() << "\n");
1062 
1063  // (4) Include all super-registers found in (3) into SRegs.
1064  SRegs |= TmpSup;
1065  DEBUG(dbgs() << "SRegs.4: "; dump_registers(SRegs, *TRI); dbgs() << "\n");
1066 
1067  // (5) For each register R in SRegs, if any super-register of R is in SRegs,
1068  // remove R from SRegs.
1069  for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1070  unsigned R = x;
1071  for (MCSuperRegIterator SR(R, TRI); SR.isValid(); ++SR) {
1072  if (!SRegs[*SR])
1073  continue;
1074  SRegs[R] = false;
1075  break;
1076  }
1077  }
1078  DEBUG(dbgs() << "SRegs.5: "; dump_registers(SRegs, *TRI); dbgs() << "\n");
1079 
1080  // Now, for each register that has a fixed stack slot, create the stack
1081  // object for it.
1082  CSI.clear();
1083 
1085  unsigned NumFixed;
1086  int MinOffset = 0; // CS offsets are negative.
1087  const SpillSlot *FixedSlots = getCalleeSavedSpillSlots(NumFixed);
1088  for (const SpillSlot *S = FixedSlots; S != FixedSlots+NumFixed; ++S) {
1089  if (!SRegs[S->Reg])
1090  continue;
1091  const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(S->Reg);
1092  int FI = MFI->CreateFixedSpillStackObject(RC->getSize(), S->Offset);
1093  MinOffset = std::min(MinOffset, S->Offset);
1094  CSI.push_back(CalleeSavedInfo(S->Reg, FI));
1095  SRegs[S->Reg] = false;
1096  }
1097 
1098  // There can be some registers that don't have fixed slots. For example,
1099  // we need to store R0-R3 in functions with exception handling. For each
1100  // such register, create a non-fixed stack object.
1101  for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1102  unsigned R = x;
1103  const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(R);
1104  int Off = MinOffset - RC->getSize();
1105  unsigned Align = std::min(RC->getAlignment(), getStackAlignment());
1106  assert(isPowerOf2_32(Align));
1107  Off &= -Align;
1108  int FI = MFI->CreateFixedSpillStackObject(RC->getSize(), Off);
1109  MinOffset = std::min(MinOffset, Off);
1110  CSI.push_back(CalleeSavedInfo(R, FI));
1111  SRegs[R] = false;
1112  }
1113 
1114  DEBUG({
1115  dbgs() << "CS information: {";
1116  for (unsigned i = 0, n = CSI.size(); i < n; ++i) {
1117  int FI = CSI[i].getFrameIdx();
1118  int Off = MFI->getObjectOffset(FI);
1119  dbgs() << ' ' << PrintReg(CSI[i].getReg(), TRI) << ":fi#" << FI << ":sp";
1120  if (Off >= 0)
1121  dbgs() << '+';
1122  dbgs() << Off;
1123  }
1124  dbgs() << " }\n";
1125  });
1126 
1127 #ifndef NDEBUG
1128  // Verify that all registers were handled.
1129  bool MissedReg = false;
1130  for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1131  unsigned R = x;
1132  dbgs() << PrintReg(R, TRI) << ' ';
1133  MissedReg = true;
1134  }
1135  if (MissedReg)
1136  llvm_unreachable("...there are unhandled callee-saved registers!");
1137 #endif
1138 
1139  return true;
1140 }
1141 
1142 
1143 void HexagonFrameLowering::expandAlloca(MachineInstr *AI,
1144  const HexagonInstrInfo &HII, unsigned SP, unsigned CF) const {
1145  MachineBasicBlock &MB = *AI->getParent();
1146  DebugLoc DL = AI->getDebugLoc();
1147  unsigned A = AI->getOperand(2).getImm();
1148 
1149  // Have
1150  // Rd = alloca Rs, #A
1151  //
1152  // If Rs and Rd are different registers, use this sequence:
1153  // Rd = sub(r29, Rs)
1154  // r29 = sub(r29, Rs)
1155  // Rd = and(Rd, #-A) ; if necessary
1156  // r29 = and(r29, #-A) ; if necessary
1157  // Rd = add(Rd, #CF) ; CF size aligned to at most A
1158  // otherwise, do
1159  // Rd = sub(r29, Rs)
1160  // Rd = and(Rd, #-A) ; if necessary
1161  // r29 = Rd
1162  // Rd = add(Rd, #CF) ; CF size aligned to at most A
1163 
1164  MachineOperand &RdOp = AI->getOperand(0);
1165  MachineOperand &RsOp = AI->getOperand(1);
1166  unsigned Rd = RdOp.getReg(), Rs = RsOp.getReg();
1167 
1168  // Rd = sub(r29, Rs)
1169  BuildMI(MB, AI, DL, HII.get(Hexagon::A2_sub), Rd)
1170  .addReg(SP)
1171  .addReg(Rs);
1172  if (Rs != Rd) {
1173  // r29 = sub(r29, Rs)
1174  BuildMI(MB, AI, DL, HII.get(Hexagon::A2_sub), SP)
1175  .addReg(SP)
1176  .addReg(Rs);
1177  }
1178  if (A > 8) {
1179  // Rd = and(Rd, #-A)
1180  BuildMI(MB, AI, DL, HII.get(Hexagon::A2_andir), Rd)
1181  .addReg(Rd)
1182  .addImm(-int64_t(A));
1183  if (Rs != Rd)
1184  BuildMI(MB, AI, DL, HII.get(Hexagon::A2_andir), SP)
1185  .addReg(SP)
1186  .addImm(-int64_t(A));
1187  }
1188  if (Rs == Rd) {
1189  // r29 = Rd
1190  BuildMI(MB, AI, DL, HII.get(TargetOpcode::COPY), SP)
1191  .addReg(Rd);
1192  }
1193  if (CF > 0) {
1194  // Rd = add(Rd, #CF)
1195  BuildMI(MB, AI, DL, HII.get(Hexagon::A2_addi), Rd)
1196  .addReg(Rd)
1197  .addImm(CF);
1198  }
1199 }
1200 
1201 
1203  const MachineFrameInfo *MFI = MF.getFrameInfo();
1204  if (!MFI->hasVarSizedObjects())
1205  return false;
1206  unsigned MaxA = MFI->getMaxAlignment();
1207  if (MaxA <= getStackAlignment())
1208  return false;
1209  return true;
1210 }
1211 
1212 
1214  for (auto &B : MF)
1215  for (auto &I : B)
1216  if (I.getOpcode() == Hexagon::ALIGNA)
1217  return &I;
1218  return nullptr;
1219 }
1220 
1221 
1222 inline static bool isOptSize(const MachineFunction &MF) {
1223  AttributeSet AF = MF.getFunction()->getAttributes();
1226 }
1227 
1228 inline static bool isMinSize(const MachineFunction &MF) {
1229  AttributeSet AF = MF.getFunction()->getAttributes();
1231 }
1232 
1233 
1234 /// Determine whether the callee-saved register saves and restores should
1235 /// be generated via inline code. If this function returns "true", inline
1236 /// code will be generated. If this function returns "false", additional
1237 /// checks are performed, which may still lead to the inline code.
1238 bool HexagonFrameLowering::shouldInlineCSR(MachineFunction &MF,
1239  const CSIVect &CSI) const {
1241  return true;
1242  if (!isOptSize(MF) && !isMinSize(MF))
1244  return true;
1245 
1246  // Check if CSI only has double registers, and if the registers form
1247  // a contiguous block starting from D8.
1248  BitVector Regs(Hexagon::NUM_TARGET_REGS);
1249  for (unsigned i = 0, n = CSI.size(); i < n; ++i) {
1250  unsigned R = CSI[i].getReg();
1251  if (!Hexagon::DoubleRegsRegClass.contains(R))
1252  return true;
1253  Regs[R] = true;
1254  }
1255  int F = Regs.find_first();
1256  if (F != Hexagon::D8)
1257  return true;
1258  while (F >= 0) {
1259  int N = Regs.find_next(F);
1260  if (N >= 0 && N != F+1)
1261  return true;
1262  F = N;
1263  }
1264 
1265  return false;
1266 }
1267 
1268 
1269 bool HexagonFrameLowering::useSpillFunction(MachineFunction &MF,
1270  const CSIVect &CSI) const {
1271  if (shouldInlineCSR(MF, CSI))
1272  return false;
1273  unsigned NumCSI = CSI.size();
1274  if (NumCSI <= 1)
1275  return false;
1276 
1277  unsigned Threshold = isOptSize(MF) ? SpillFuncThresholdOs
1279  return Threshold < NumCSI;
1280 }
1281 
1282 
1283 bool HexagonFrameLowering::useRestoreFunction(MachineFunction &MF,
1284  const CSIVect &CSI) const {
1285  if (shouldInlineCSR(MF, CSI))
1286  return false;
1287  unsigned NumCSI = CSI.size();
1288  unsigned Threshold = isOptSize(MF) ? SpillFuncThresholdOs-1
1290  return Threshold < NumCSI;
1291 }
1292 
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
BitVector & set()
Definition: BitVector.h:218
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
Definition: BitVector.h:156
The memory access writes data.
static void addCalleeSaveRegistersAsImpOperand(MachineInstr *Inst, unsigned MaxReg, bool IsDef)
Adds all callee-saved registers up to MaxReg to the instruction.
void mapLocalFrameObject(int ObjectIndex, int64_t Offset)
Map a frame index into the local object block.
static cl::opt< int > SpillFuncThresholdOs("spill-func-threshold-Os", cl::Hidden, cl::desc("Specify Os spill func threshold"), cl::init(1), cl::ZeroOrMore)
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:39
int getNumber() const
getNumber - MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a M...
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
MachineBasicBlock * findNearestCommonDominator(MachineBasicBlock *A, MachineBasicBlock *B)
int find_next(unsigned Prev) const
find_next - Returns the index of the next set bit following the "Prev" bit.
Definition: BitVector.h:165
iterator getFirstTerminator()
getFirstTerminator - returns an iterator to the first terminator instruction of this basic block...
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:138
bool isDead() const
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
Definition: MCDwarf.h:381
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
static void dump_registers(BitVector &Regs, const TargetRegisterInfo &TRI)
void addLiveIn(unsigned Reg)
Adds the specified register as a live in.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Hexagon target-specific information for each MachineFunction.
const SpillSlot * getCalleeSavedSpillSlots(unsigned &NumEntries) const override
getCalleeSavedSpillSlots - This method returns a pointer to an array of pairs, that contains an entry...
A debug info location.
Definition: DebugLoc.h:34
F(f)
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
#define R2(n)
static cl::opt< int > SpillFuncThreshold("spill-func-threshold", cl::Hidden, cl::desc("Specify O2(not Os) spill func threshold"), cl::init(6), cl::ZeroOrMore)
bool hasAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return true if the attribute exists at the given index.
Definition: Attributes.cpp:956
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:295
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, unsigned f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
getMachineMemOperand - Allocate a new MachineMemOperand.
int getFrameIndexOffset(const MachineFunction &MF, int FI) const override
getFrameIndexOffset - Returns the displacement from the frame register to the stack frame of the spec...
StringRef getName() const
Return a constant reference to the value's name.
Definition: Value.cpp:188
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
COPY - Target-independent register copy.
Definition: TargetOpcodes.h:86
int64_t getLocalFrameSize() const
Get the size of the local object blob.
unsigned getSize() const
getSize - Return the size of the register in bytes, which is also the size of a stack slot allocated ...
MachineInstr * getAlignaInstr(MachineFunction &MF) const
MachineMemOperand - A description of a memory reference used in the backend.
void setLocalFrameSize(int64_t sz)
Set the size of the local object blob.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
void setUseLocalStackAllocationBlock(bool v)
setUseLocalStackAllocationBlock - Set whether the local allocation blob should be allocated together ...
MCSuperRegIterator enumerates all super-registers of Reg.
DILocation * get() const
Get the underlying DILocation.
Definition: DebugLoc.cpp:22
const HexagonInstrInfo * TII
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const HexagonRegisterInfo * getRegisterInfo() const override
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
Reg
All possible values of the reg field in the ModR/M byte.
static cl::opt< bool > EnableShrinkWrapping("hexagon-shrink-frame", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("Enable stack frame shrink wrapping"))
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
Number of individual test Apply this number of consecutive mutations to each input exit after the first new interesting input is found the minimized corpus is saved into the first input directory Number of jobs to run If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
bool hasDebugInfo() const
hasDebugInfo - Returns true if valid debug info is present.
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Definition: Value.cpp:317
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
PrintReg - Helper class for printing registers on a raw_ostream.
const MachineBasicBlock & front() const
const HexagonRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
bool isKill() const
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
static bool isMinSize(const MachineFunction &MF)
unsigned getLocalFrameMaxAlign() const
Return the required alignment of the local object blob.
unsigned LLVM_ATTRIBUTE_UNUSED_RESULT addFrameInst(const MCCFIInstruction &Inst)
void setLocalFrameMaxAlign(unsigned Align)
Required alignment of the local object blob, which is the strictest alignment of any object in it...
const std::vector< MCCFIInstruction > & getFrameInstructions() const
Returns a reference to a list of cfi instructions in the current function's prologue.
iterator getLastNonDebugInstr()
getLastNonDebugInstr - returns an iterator to the last non-debug instruction in the basic block...
bool needsAligna(const MachineFunction &MF) const
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
MachineBasicBlock * findNearestCommonDominator(MachineBasicBlock *A, MachineBasicBlock *B)
findNearestCommonDominator - Find nearest common dominator basic block for basic block A and B...
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
int64_t getImm() const
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
Perform most of the PEI work here:
unsigned getKillRegState(bool B)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:267
bool isSpillSlotObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a spill slot.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:120
TargetInstrInfo - Interface to description of machine instruction set.
const MCPhysReg * getCallerSavedRegs(const MachineFunction *MF) const
bundle_iterator< MachineInstr, instr_iterator > iterator
#define P(N)
static bool isOptSize(const MachineFunction &MF)
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:325
MCSymbol * createTempSymbol(bool CanBeUnnamed=true)
Create and return a new assembler temporary symbol with a unique but unspecified name.
Definition: MCContext.cpp:222
static MCCFIInstruction createDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it...
Definition: MCDwarf.h:354
static cl::opt< bool > DisableDeallocRet("disable-hexagon-dealloc-ret", cl::Hidden, cl::desc("Disable Dealloc Return for Hexagon target"))
bool isEHReturnCalleeSaveReg(unsigned Reg) const
unsigned getAlignment() const
getAlignment - Return the minimum required alignment for a register of this class.
void eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
eliminateCallFramePseudoInstr - This method is called during prolog/epilog code insertion to eliminat...
void setStackSize(uint64_t Size)
Set the size of the stack.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Load the specified register of the given register class from the specified stack frame index...
MCRegAliasIterator enumerates all registers aliasing Reg.
static const char * getSpillFunctionFor(unsigned MaxReg, SpillKind SpillType)
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS=nullptr) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
virtual void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Store the specified register of the given register class to the specified stack frame index...
int CreateSpillStackObject(uint64_t Size, unsigned Alignment)
Create a new statically sized stack object that represents a spill slot, returning a nonnegative iden...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
MCSubRegIterator enumerates all sub-registers of Reg.
MachinePointerInfo - This class contains a discriminated union of information about pointers in memor...
bool dominates(const MachineDomTreeNode *A, const MachineDomTreeNode *B) const
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
void setIsKill(bool Val=true)
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
bool isDeadObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a dead object.
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
bool hasCalls() const
Return true if the current function has any function calls.
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
const std::vector< MachineInstr * > & getAllocaAdjustInsts()
const MCContext & getContext() const
PostDominatorTree Class - Concrete subclass of DominatorTree that is used to compute the post-dominat...
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:861
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call...
bool needsUnwindTableEntry() const
True if this function needs an unwind table.
Definition: Function.h:354
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
bool assignCalleeSavedSpillSlots(MachineFunction &MF, const TargetRegisterInfo *TRI, std::vector< CalleeSavedInfo > &CSI) const override
assignCalleeSavedSpillSlots - Allows target to override spill slot assignment logic.
static cl::opt< int > NumberScavengerSlots("number-scavenger-slots", cl::Hidden, cl::desc("Set the number of scavenger slots"), cl::init(2), cl::ZeroOrMore)
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:123
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
AttributeSet getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:181
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a ...
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
getMinimalPhysRegClass - Returns the Register Class of a physical register of the given type...
static cl::opt< unsigned > ShrinkLimit("shrink-frame-limit", cl::init(UINT_MAX), cl::Hidden, cl::ZeroOrMore, cl::desc("Max count of stack frame ""shrink-wraps"))
bool runOnMachineFunction(MachineFunction &F) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:238
uint64_t RoundUpToAlignment(uint64_t Value, uint64_t Align)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
Definition: MathExtras.h:609
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:51
bundle_iterator< const MachineInstr, const_instr_iterator > const_iterator
void copyImplicitOps(MachineFunction &MF, const MachineInstr *MI)
Copy implicit register operands from specified instruction to this instruction.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
void setReg(unsigned Reg)
Change the register this operand corresponds to.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
#define I(x, y, z)
Definition: MD5.cpp:54
#define N
void setMaxCallFrameSize(unsigned S)
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:403
static bool needToReserveScavengingSpillSlots(MachineFunction &MF, const HexagonRegisterInfo &HRI)
Returns true if there is no caller saved registers available.
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
static int const Threshold
TODO: Write a new FunctionPass AliasAnalysis so that it can keep a cache.
unsigned getReg() const
getReg - Returns the register number.
const ARM::ArchExtKind Kind
virtual const TargetInstrInfo * getInstrInfo() const
const HexagonInstrInfo * getInstrInfo() const override
bool isPhysRegUsed(unsigned Reg) const
isPhysRegUsed - Return true if the specified register is used in this function.
BasicBlockListType::iterator iterator
#define DEBUG(X)
Definition: Debug.h:92
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
bool isPowerOf2_32(uint32_t Value)
isPowerOf2_32 - This function returns true if the argument is a power of two > 0. ...
Definition: MathExtras.h:354
MachineModuleInfo & getMMI() const
int getObjectIndexEnd() const
Return one past the maximum frame object index.
#define LLVM_FUNCTION_NAME
LLVM_FUNCTION_NAME
Definition: Compiler.h:318
bool dominates(const MachineDomTreeNode *A, const MachineDomTreeNode *B) const
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
MachineModuleInfo - This class contains meta information specific to a module.
Function must be optimized for size first.
Definition: Attributes.h:80