14 #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H
15 #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H
20 struct InstrItinerary;
28 class MCSubtargetInfo;
33 class raw_pwrite_stream;
42 MCRegisterInfo
const &MRI,
46 MCRegisterInfo
const &MRI,
47 const Triple &TT, StringRef CPU);
50 uint8_t OSABI, StringRef CPU);
57 #define GET_REGINFO_ENUM
58 #include "HexagonGenRegisterInfo.inc"
62 #define GET_INSTRINFO_ENUM
63 #include "HexagonGenInstrInfo.inc"
65 #define GET_SUBTARGETINFO_ENUM
66 #include "HexagonGenSubtargetInfo.inc"
MCAsmBackend * createHexagonAsmBackend(Target const &T, MCRegisterInfo const &, const Triple &TT, StringRef CPU)
MCInstrInfo * createHexagonMCInstrInfo()
MCObjectWriter * createHexagonELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI, StringRef CPU)
MCCodeEmitter * createHexagonMCCodeEmitter(MCInstrInfo const &MCII, MCRegisterInfo const &MRI, MCContext &MCT)
const InstrStage HexagonStages[]