26 assert(DwarfReg >= 0 &&
"invalid negative dwarf register number");
28 EmitOp(dwarf::DW_OP_reg0 + DwarfReg, Comment);
30 EmitOp(dwarf::DW_OP_regx, Comment);
36 assert(DwarfReg >= 0 &&
"invalid negative dwarf register number");
38 EmitOp(dwarf::DW_OP_breg0 + DwarfReg);
40 EmitOp(dwarf::DW_OP_bregx);
45 EmitOp(dwarf::DW_OP_deref);
49 assert(SizeInBits > 0 &&
"piece has size zero");
50 const unsigned SizeOfByte = 8;
51 if (OffsetInBits > 0 || SizeInBits % SizeOfByte) {
52 EmitOp(dwarf::DW_OP_bit_piece);
56 EmitOp(dwarf::DW_OP_piece);
57 unsigned ByteSize = SizeInBits / SizeOfByte;
63 EmitOp(dwarf::DW_OP_constu);
71 EmitOp(dwarf::DW_OP_fbreg);
85 unsigned PieceSizeInBits,
86 unsigned PieceOffsetInBits) {
96 AddOpPiece(PieceSizeInBits, PieceOffsetInBits);
108 AddReg(Reg,
"super-register");
109 if (PieceOffsetInBits == RegOffset) {
129 unsigned CurPos = PieceOffsetInBits;
144 Intersection.
set(Offset, Offset + Size);
145 Intersection ^= Coverage;
149 if (Reg >= 0 && Intersection.
any()) {
150 AddReg(Reg,
"sub-register");
151 AddOpPiece(Size, Offset == CurPos ? 0 : Offset);
152 CurPos = Offset + Size;
155 Coverage.
set(Offset, Offset + Size);
159 return CurPos > PieceOffsetInBits;
163 EmitOp(dwarf::DW_OP_consts);
176 EmitOp(dwarf::DW_OP_stack_value);
180 EmitOp(dwarf::DW_OP_constu);
184 EmitOp(dwarf::DW_OP_stack_value);
188 unsigned PieceOffsetInBits) {
189 if (OffsetInBits == PieceOffsetInBits)
191 assert(OffsetInBits >= PieceOffsetInBits &&
"overlapping pieces");
197 unsigned PieceOffsetInBits) {
205 bool ValidReg =
false;
206 switch (
I->getOp()) {
207 case dwarf::DW_OP_bit_piece: {
208 unsigned OffsetInBits =
I->getArg(0);
209 unsigned SizeInBits =
I->getArg(1);
214 case dwarf::DW_OP_plus: {
216 auto N =
I.getNext();
217 if (
N != E &&
N->getOp() == dwarf::DW_OP_deref) {
218 unsigned Offset =
I->getArg(0);
225 case dwarf::DW_OP_deref: {
245 unsigned PieceOffsetInBits) {
246 for (; I != E; ++
I) {
247 switch (I->
getOp()) {
248 case dwarf::DW_OP_bit_piece: {
249 unsigned OffsetInBits = I->
getArg(0);
250 unsigned SizeInBits = I->
getArg(1);
254 case dwarf::DW_OP_plus:
255 EmitOp(dwarf::DW_OP_plus_uconst);
258 case dwarf::DW_OP_deref:
259 EmitOp(dwarf::DW_OP_deref);
int getDwarfRegNum(unsigned RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
SmallBitVector - This is a 'bitvector' (really, a variable-sized bit array), optimized for the case w...
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
void AddShr(unsigned ShiftBy)
Emit a shift-right dwarf expression.
bool AddMachineRegExpression(const DIExpression *Expr, unsigned MachineReg, unsigned PieceOffsetInBits=0)
Emit an entire expression on top of a machine register location.
void AddOpPiece(unsigned SizeInBits, unsigned OffsetInBits=0)
Emit a dwarf register operation for describing.
virtual void EmitOp(uint8_t Op, const char *Comment=nullptr)=0
Output a dwarf operand and an optional assembler comment.
unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const
For a given register pair, return the sub-register index if the second register is a sub-register of ...
unsigned getSize() const
getSize - Return the size of the register in bytes, which is also the size of a stack slot allocated ...
MCSuperRegIterator enumerates all super-registers of Reg.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static void advance(T &it, size_t Val)
Reg
All possible values of the reg field in the ModR/M byte.
expr_op_iterator expr_op_begin() const
Visit the elements via ExprOperand wrappers.
static unsigned getOffsetOrZero(unsigned OffsetInBits, unsigned PieceOffsetInBits)
void AddUnsignedConstant(unsigned Value)
Emit an unsigned constant.
void AddSignedConstant(int Value)
Emit a signed constant.
uint64_t getArg(unsigned I) const
Get an argument to the operand.
void AddRegIndirect(int DwarfReg, int Offset, bool Deref=false)
Emit an (double-)indirect dwarf register operation.
MCSubRegIterator enumerates all sub-registers of Reg.
virtual void EmitUnsigned(uint64_t Value)=0
Emit a raw unsigned value.
bool AddMachineRegIndirect(unsigned MachineReg, int Offset=0)
Emit an indirect dwarf register operation for the given machine register.
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
getMinimalPhysRegClass - Returns the Register Class of a physical register of the given type...
static bool isPhysicalRegister(unsigned Reg)
isPhysicalRegister - Return true if the specified register number is in the physical register namespa...
unsigned getSubRegIdxOffset(unsigned Idx) const
Get the offset of the bit range covered by a sub-register index.
LLVM Value Representation.
bool any() const
any - Returns true if any bit is set.
virtual void EmitSigned(int64_t Value)=0
Emit a raw signed value.
An iterator for expression operands.
uint64_t getOp() const
Get the operand code.
unsigned getSubRegIdxSize(unsigned Idx) const
Get the size of the bit range covered by a sub-register index.
expr_op_iterator expr_op_end() const
void AddReg(int DwarfReg, const char *Comment=nullptr)
Emit a dwarf register operation.
const TargetRegisterInfo & TRI
bool AddMachineRegPiece(unsigned MachineReg, unsigned PieceSizeInBits=0, unsigned PieceOffsetInBits=0)
Emit a partial DWARF register operation.
void AddExpression(DIExpression::expr_op_iterator I, DIExpression::expr_op_iterator E, unsigned PieceOffsetInBits=0)
Emit a the operations remaining the DIExpressionIterator I.
virtual bool isFrameRegister(unsigned MachineReg)=0
Return whether the given machine register is the frame register in the current function.