LLVM  3.7.0
SparcMCCodeEmitter.cpp
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1 //===-- SparcMCCodeEmitter.cpp - Convert Sparc code to machine code -------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the SparcMCCodeEmitter class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "SparcMCExpr.h"
16 #include "SparcMCTargetDesc.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCSymbol.h"
24 #include "llvm/MC/MCAsmInfo.h"
26 
27 using namespace llvm;
28 
29 #define DEBUG_TYPE "mccodeemitter"
30 
31 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
32 
33 namespace {
34 class SparcMCCodeEmitter : public MCCodeEmitter {
35  SparcMCCodeEmitter(const SparcMCCodeEmitter &) = delete;
36  void operator=(const SparcMCCodeEmitter &) = delete;
37  MCContext &Ctx;
38 
39 public:
40  SparcMCCodeEmitter(MCContext &ctx): Ctx(ctx) {}
41 
42  ~SparcMCCodeEmitter() override {}
43 
44  void encodeInstruction(const MCInst &MI, raw_ostream &OS,
46  const MCSubtargetInfo &STI) const override;
47 
48  // getBinaryCodeForInstr - TableGen'erated function for getting the
49  // binary encoding for an instruction.
50  uint64_t getBinaryCodeForInstr(const MCInst &MI,
52  const MCSubtargetInfo &STI) const;
53 
54  /// getMachineOpValue - Return binary encoding of operand. If the machine
55  /// operand requires relocation, record the relocation and return zero.
56  unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
58  const MCSubtargetInfo &STI) const;
59 
60  unsigned getCallTargetOpValue(const MCInst &MI, unsigned OpNo,
62  const MCSubtargetInfo &STI) const;
63  unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
65  const MCSubtargetInfo &STI) const;
66  unsigned getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo,
68  const MCSubtargetInfo &STI) const;
69  unsigned getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo,
71  const MCSubtargetInfo &STI) const;
72 
73 };
74 } // end anonymous namespace
75 
77  const MCRegisterInfo &MRI,
78  MCContext &Ctx) {
79  return new SparcMCCodeEmitter(Ctx);
80 }
81 
82 void SparcMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
84  const MCSubtargetInfo &STI) const {
85  unsigned Bits = getBinaryCodeForInstr(MI, Fixups, STI);
86 
87  if (Ctx.getAsmInfo()->isLittleEndian()) {
88  // Output the bits in little-endian byte order.
89  support::endian::Writer<support::little>(OS).write<uint32_t>(Bits);
90  } else {
91  // Output the bits in big-endian byte order.
92  support::endian::Writer<support::big>(OS).write<uint32_t>(Bits);
93  }
94  unsigned tlsOpNo = 0;
95  switch (MI.getOpcode()) {
96  default: break;
97  case SP::TLS_CALL: tlsOpNo = 1; break;
98  case SP::TLS_ADDrr:
99  case SP::TLS_ADDXrr:
100  case SP::TLS_LDrr:
101  case SP::TLS_LDXrr: tlsOpNo = 3; break;
102  }
103  if (tlsOpNo != 0) {
104  const MCOperand &MO = MI.getOperand(tlsOpNo);
105  uint64_t op = getMachineOpValue(MI, MO, Fixups, STI);
106  assert(op == 0 && "Unexpected operand value!");
107  (void)op; // suppress warning.
108  }
109 
110  ++MCNumEmitted; // Keep track of the # of mi's emitted.
111 }
112 
113 
114 unsigned SparcMCCodeEmitter::
115 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
116  SmallVectorImpl<MCFixup> &Fixups,
117  const MCSubtargetInfo &STI) const {
118 
119  if (MO.isReg())
120  return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
121 
122  if (MO.isImm())
123  return MO.getImm();
124 
125  assert(MO.isExpr());
126  const MCExpr *Expr = MO.getExpr();
127  if (const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(Expr)) {
128  MCFixupKind Kind = (MCFixupKind)SExpr->getFixupKind();
129  Fixups.push_back(MCFixup::create(0, Expr, Kind));
130  return 0;
131  }
132 
133  int64_t Res;
134  if (Expr->evaluateAsAbsolute(Res))
135  return Res;
136 
137  llvm_unreachable("Unhandled expression!");
138  return 0;
139 }
140 
141 unsigned SparcMCCodeEmitter::
142 getCallTargetOpValue(const MCInst &MI, unsigned OpNo,
143  SmallVectorImpl<MCFixup> &Fixups,
144  const MCSubtargetInfo &STI) const {
145  const MCOperand &MO = MI.getOperand(OpNo);
146  if (MO.isReg() || MO.isImm())
147  return getMachineOpValue(MI, MO, Fixups, STI);
148 
149  if (MI.getOpcode() == SP::TLS_CALL) {
150  // No fixups for __tls_get_addr. Will emit for fixups for tls_symbol in
151  // encodeInstruction.
152 #ifndef NDEBUG
153  // Verify that the callee is actually __tls_get_addr.
154  const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(MO.getExpr());
155  assert(SExpr && SExpr->getSubExpr()->getKind() == MCExpr::SymbolRef &&
156  "Unexpected expression in TLS_CALL");
157  const MCSymbolRefExpr *SymExpr = cast<MCSymbolRefExpr>(SExpr->getSubExpr());
158  assert(SymExpr->getSymbol().getName() == "__tls_get_addr" &&
159  "Unexpected function for TLS_CALL");
160 #endif
161  return 0;
162  }
163 
165 
166  if (const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(MO.getExpr())) {
167  if (SExpr->getKind() == SparcMCExpr::VK_Sparc_WPLT30)
169  }
170 
171  Fixups.push_back(MCFixup::create(0, MO.getExpr(), fixupKind));
172 
173  return 0;
174 }
175 
176 unsigned SparcMCCodeEmitter::
177 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
178  SmallVectorImpl<MCFixup> &Fixups,
179  const MCSubtargetInfo &STI) const {
180  const MCOperand &MO = MI.getOperand(OpNo);
181  if (MO.isReg() || MO.isImm())
182  return getMachineOpValue(MI, MO, Fixups, STI);
183 
184  Fixups.push_back(MCFixup::create(0, MO.getExpr(),
186  return 0;
187 }
188 
189 unsigned SparcMCCodeEmitter::
190 getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo,
191  SmallVectorImpl<MCFixup> &Fixups,
192  const MCSubtargetInfo &STI) const {
193  const MCOperand &MO = MI.getOperand(OpNo);
194  if (MO.isReg() || MO.isImm())
195  return getMachineOpValue(MI, MO, Fixups, STI);
196 
197  Fixups.push_back(MCFixup::create(0, MO.getExpr(),
199  return 0;
200 }
201 unsigned SparcMCCodeEmitter::
202 getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo,
203  SmallVectorImpl<MCFixup> &Fixups,
204  const MCSubtargetInfo &STI) const {
205  const MCOperand &MO = MI.getOperand(OpNo);
206  if (MO.isReg() || MO.isImm())
207  return getMachineOpValue(MI, MO, Fixups, STI);
208 
209  Fixups.push_back(MCFixup::create(0, MO.getExpr(),
211  Fixups.push_back(MCFixup::create(0, MO.getExpr(),
213 
214  return 0;
215 }
216 
217 
218 
219 #include "SparcGenMCCodeEmitter.inc"
MCCodeEmitter * createSparcMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
STATISTIC(NumFunctions,"Total number of functions")
bool isReg() const
Definition: MCInst.h:56
const MCExpr * getSubExpr() const
getSubExpr - Get the child of this expression.
Definition: SparcMCExpr.h:82
ExprKind getKind() const
Definition: MCExpr.h:69
#define op(i)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APInt.h:33
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:33
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:159
Context object for machine code objects.
Definition: MCContext.h:48
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:63
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:150
fixup_sparc_br19 - 19-bit PC relative relocation for branches on icc/xcc
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
bool isImm() const
Definition: MCInst.h:57
const MCExpr * getExpr() const
Definition: MCInst.h:93
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:23
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:23
bool isExpr() const
Definition: MCInst.h:59
VariantKind getKind() const
getOpcode - Get the kind of this expression.
Definition: SparcMCExpr.h:79
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:78
fixup_sparc_bpr - 16-bit fixup for bpr
unsigned getOpcode() const
Definition: MCInst.h:159
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:285
int64_t getImm() const
Definition: MCInst.h:74
Adapter to write values to a stream in a particular byte order.
Definition: EndianStream.h:26
MCSubtargetInfo - Generic base class for all target subtargets.
References to labels and assigned expressions.
Definition: MCExpr.h:38
static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI)
getBranchTargetOpValue - Helper function to get the branch target operand, which is either an immedia...
fixup_sparc_br22 - 22-bit PC relative relocation for branches
const ARM::ArchExtKind Kind
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:38
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:33
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:164