LLVM  3.7.0
AMDGPU.h
Go to the documentation of this file.
1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 /// \file
9 //===----------------------------------------------------------------------===//
10 
11 #ifndef LLVM_LIB_TARGET_R600_AMDGPU_H
12 #define LLVM_LIB_TARGET_R600_AMDGPU_H
13 
16 
17 namespace llvm {
18 
19 class AMDGPUInstrPrinter;
20 class AMDGPUSubtarget;
21 class AMDGPUTargetMachine;
22 class FunctionPass;
23 class MCAsmInfo;
24 class raw_ostream;
25 class Target;
26 class TargetMachine;
27 
28 // R600 Passes
29 FunctionPass *createR600VectorRegMerger(TargetMachine &tm);
31 FunctionPass *createR600ExpandSpecialInstrsPass(TargetMachine &tm);
32 FunctionPass *createR600EmitClauseMarkers();
33 FunctionPass *createR600ClauseMergePass(TargetMachine &tm);
34 FunctionPass *createR600Packetizer(TargetMachine &tm);
35 FunctionPass *createR600ControlFlowFinalizer(TargetMachine &tm);
36 FunctionPass *createAMDGPUCFGStructurizerPass();
37 
38 // SI Passes
39 FunctionPass *createSITypeRewriter();
40 FunctionPass *createSIAnnotateControlFlowPass();
41 FunctionPass *createSIFoldOperandsPass();
42 FunctionPass *createSILowerI1CopiesPass();
43 FunctionPass *createSIShrinkInstructionsPass();
44 FunctionPass *createSILoadStoreOptimizerPass(TargetMachine &tm);
45 FunctionPass *createSILowerControlFlowPass(TargetMachine &tm);
47 FunctionPass *createSIFixSGPRCopiesPass(TargetMachine &tm);
48 FunctionPass *createSIFixSGPRLiveRangesPass();
49 FunctionPass *createSICodeEmitterPass(formatted_raw_ostream &OS);
50 FunctionPass *createSIInsertWaits(TargetMachine &tm);
51 FunctionPass *createSIPrepareScratchRegs();
52 
53 void initializeSIFoldOperandsPass(PassRegistry &);
54 extern char &SIFoldOperandsID;
55 
56 void initializeSILowerI1CopiesPass(PassRegistry &);
57 extern char &SILowerI1CopiesID;
58 
59 void initializeSILoadStoreOptimizerPass(PassRegistry &);
60 extern char &SILoadStoreOptimizerID;
61 
62 // Passes common to R600 and SI
63 FunctionPass *createAMDGPUPromoteAlloca(const AMDGPUSubtarget &ST);
65 FunctionPass *createAMDGPUISelDag(TargetMachine &tm);
66 ModulePass *createAMDGPUAlwaysInlinePass();
67 
70 
71 void initializeSIFixSGPRLiveRangesPass(PassRegistry&);
72 extern char &SIFixSGPRLiveRangesID;
73 
74 
75 extern Target TheAMDGPUTarget;
76 extern Target TheGCNTarget;
77 
78 namespace AMDGPU {
85 };
86 }
87 
88 #define END_OF_TEXT_LABEL_NAME "EndOfTextLabel"
89 
90 } // End namespace llvm
91 
92 namespace ShaderType {
93  enum Type {
94  PIXEL = 0,
95  VERTEX = 1,
96  GEOMETRY = 2,
97  COMPUTE = 3
98  };
99 }
100 
101 /// OpenCL uses address spaces to differentiate between
102 /// various memory regions on the hardware. On the CPU
103 /// all of the address spaces point to the same memory,
104 /// however on the GPU, each address space points to
105 /// a separate piece of memory that is unique from other
106 /// memory locations.
107 namespace AMDGPUAS {
108 enum AddressSpaces : unsigned {
109  PRIVATE_ADDRESS = 0, ///< Address space for private memory.
110  GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0).
111  CONSTANT_ADDRESS = 2, ///< Address space for constant memory
112  LOCAL_ADDRESS = 3, ///< Address space for local memory.
113  FLAT_ADDRESS = 4, ///< Address space for flat memory.
114  REGION_ADDRESS = 5, ///< Address space for region memory.
115  PARAM_D_ADDRESS = 6, ///< Address space for direct addressible parameter memory (CONST0)
116  PARAM_I_ADDRESS = 7, ///< Address space for indirect addressible parameter memory (VTX1)
117 
118  // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on this
119  // order to be able to dynamically index a constant buffer, for example:
120  //
121  // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx
122 
139  ADDRESS_NONE = 24, ///< Address space for unknown memory.
141 
142  // Some places use this if the address space can't be determined.
144 };
145 
146 } // namespace AMDGPUAS
147 
148 #endif
Pass * createAMDGPUStructurizeCFGPass()
FunctionPass * createSIAnnotateControlFlowPass()
Create the annotation pass.
Address space for unknown memory.
Definition: AMDGPU.h:139
Target TheGCNTarget
The target for GCN GPUs.
FunctionPass * createSIShrinkInstructionsPass()
char & SILoadStoreOptimizerID
Address space for local memory.
Definition: AMDGPU.h:112
FunctionPass * createAMDGPUCFGStructurizerPass()
FunctionPass * createSIInsertWaits(TargetMachine &tm)
AddressSpaces
Definition: AMDGPU.h:108
Target TheAMDGPUTarget
The target which suports all AMD GPUs.
FunctionPass * createR600TextureIntrinsicsReplacer()
void initializeSIFixSGPRLiveRangesPass(PassRegistry &)
FunctionPass * createR600ExpandSpecialInstrsPass(TargetMachine &tm)
char & SIFixControlFlowLiveIntervalsID
FunctionPass * createR600VectorRegMerger(TargetMachine &tm)
FunctionPass * createSITypeRewriter()
FunctionPass * createR600ClauseMergePass(TargetMachine &tm)
FunctionPass * createSILowerControlFlowPass(TargetMachine &tm)
FunctionPass * createSILowerI1CopiesPass()
FunctionPass * createR600ControlFlowFinalizer(TargetMachine &tm)
FunctionPass * createSILoadStoreOptimizerPass(TargetMachine &tm)
FunctionPass * createSIFixSGPRCopiesPass(TargetMachine &tm)
Address space for region memory.
Definition: AMDGPU.h:114
char & SIFoldOperandsID
Address space for constant memory.
Definition: AMDGPU.h:111
Address space for private memory.
Definition: AMDGPU.h:109
FunctionPass * createAMDGPUISelDag(TargetMachine &tm)
This pass converts a legalized DAG into a AMDGPU-specific.
FunctionPass * createR600Packetizer(TargetMachine &tm)
FunctionPass * createSIPrepareScratchRegs()
Address space for flat memory.
Definition: AMDGPU.h:113
char & SILowerI1CopiesID
aarch64 type AArch64 Type Promotion Pass
ModulePass * createAMDGPUAlwaysInlinePass()
void initializeSILoadStoreOptimizerPass(PassRegistry &)
void initializeSIFoldOperandsPass(PassRegistry &)
Address space for indirect addressible parameter memory (VTX1)
Definition: AMDGPU.h:116
FunctionPass * createSIFoldOperandsPass()
Address space for direct addressible parameter memory (CONST0)
Definition: AMDGPU.h:115
FunctionPass * createR600EmitClauseMarkers()
char & SIFixSGPRLiveRangesID
void initializeSIFixControlFlowLiveIntervalsPass(PassRegistry &)
FunctionPass * createSICodeEmitterPass(formatted_raw_ostream &OS)
FunctionPass * createSIFixControlFlowLiveIntervalsPass()
FunctionPass * createSIFixSGPRLiveRangesPass()
void initializeSILowerI1CopiesPass(PassRegistry &)
FunctionPass * createAMDGPUPromoteAlloca(const AMDGPUSubtarget &ST)
Address space for global memory (RAT0, VTX0).
Definition: AMDGPU.h:110