LLVM  3.7.0
XCoreISelLowering.h
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1 //===-- XCoreISelLowering.h - XCore DAG Lowering Interface ------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that XCore uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_XCORE_XCOREISELLOWERING_H
16 #define LLVM_LIB_TARGET_XCORE_XCOREISELLOWERING_H
17 
18 #include "XCore.h"
21 
22 namespace llvm {
23 
24  // Forward delcarations
25  class XCoreSubtarget;
26  class XCoreTargetMachine;
27 
28  namespace XCoreISD {
29  enum NodeType : unsigned {
30  // Start the numbering where the builtin ops and target ops leave off.
32 
33  // Branch and link (call)
34  BL,
35 
36  // pc relative address
38 
39  // dp relative address
41 
42  // cp relative address
44 
45  // Load word from stack
47 
48  // Store word to stack
50 
51  // Corresponds to retsp instruction
53 
54  // Corresponds to LADD instruction
56 
57  // Corresponds to LSUB instruction
59 
60  // Corresponds to LMUL instruction
62 
63  // Corresponds to MACCU instruction
65 
66  // Corresponds to MACCS instruction
68 
69  // Corresponds to CRC8 instruction
71 
72  // Jumptable branch.
74 
75  // Jumptable branch using long branches for each entry.
77 
78  // Offset from frame pointer to the first (possible) on-stack argument
80 
81  // Exception handler return. The stack is restored to the first
82  // followed by a jump to the second argument.
84 
85  // Memory barrier.
87  };
88  }
89 
90  //===--------------------------------------------------------------------===//
91  // TargetLowering Implementation
92  //===--------------------------------------------------------------------===//
94  {
95  public:
96  explicit XCoreTargetLowering(const TargetMachine &TM,
97  const XCoreSubtarget &Subtarget);
98 
100  bool isZExtFree(SDValue Val, EVT VT2) const override;
101 
102 
103  unsigned getJumpTableEncoding() const override;
104  MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override {
105  return MVT::i32;
106  }
107 
108  /// LowerOperation - Provide custom lowering hooks for some operations.
109  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
110 
111  /// ReplaceNodeResults - Replace the results of node with an illegal result
112  /// type with new values built out of custom code.
113  ///
115  SelectionDAG &DAG) const override;
116 
117  /// getTargetNodeName - This method returns the name of a target specific
118  // DAG node.
119  const char *getTargetNodeName(unsigned Opcode) const override;
120 
123  MachineBasicBlock *MBB) const override;
124 
125  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
126  Type *Ty, unsigned AS) const override;
127 
128  private:
129  const TargetMachine &TM;
130  const XCoreSubtarget &Subtarget;
131 
132  // Lower Operand helpers
133  SDValue LowerCCCArguments(SDValue Chain,
134  CallingConv::ID CallConv,
135  bool isVarArg,
137  SDLoc dl, SelectionDAG &DAG,
138  SmallVectorImpl<SDValue> &InVals) const;
139  SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
140  CallingConv::ID CallConv, bool isVarArg,
141  bool isTailCall,
143  const SmallVectorImpl<SDValue> &OutVals,
145  SDLoc dl, SelectionDAG &DAG,
146  SmallVectorImpl<SDValue> &InVals) const;
147  SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
148  SDValue getGlobalAddressWrapper(SDValue GA, const GlobalValue *GV,
149  SelectionDAG &DAG) const;
150  SDValue lowerLoadWordFromAlignedBasePlusOffset(SDLoc DL, SDValue Chain,
151  SDValue Base, int64_t Offset,
152  SelectionDAG &DAG) const;
153 
154  // Lower Operand specifics
155  SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
156  SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
157  SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
158  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
159  SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
160  SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
161  SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
162  SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
163  SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
164  SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
165  SDValue LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
166  SDValue LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
167  SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
168  SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
169  SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
170  SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
171  SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
172  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
173  SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
174  SDValue LowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const;
175  SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;
176 
177  // Inline asm support
178  std::pair<unsigned, const TargetRegisterClass *>
179  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
180  StringRef Constraint, MVT VT) const override;
181 
182  // Expand specifics
183  SDValue TryExpandADDWithMul(SDNode *Op, SelectionDAG &DAG) const;
184  SDValue ExpandADDSUB(SDNode *Op, SelectionDAG &DAG) const;
185 
186  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
187 
188  void computeKnownBitsForTargetNode(const SDValue Op,
189  APInt &KnownZero,
190  APInt &KnownOne,
191  const SelectionDAG &DAG,
192  unsigned Depth = 0) const override;
193 
194  SDValue
195  LowerFormalArguments(SDValue Chain,
196  CallingConv::ID CallConv,
197  bool isVarArg,
199  SDLoc dl, SelectionDAG &DAG,
200  SmallVectorImpl<SDValue> &InVals) const override;
201 
202  SDValue
203  LowerCall(TargetLowering::CallLoweringInfo &CLI,
204  SmallVectorImpl<SDValue> &InVals) const override;
205 
206  SDValue
207  LowerReturn(SDValue Chain,
208  CallingConv::ID CallConv, bool isVarArg,
210  const SmallVectorImpl<SDValue> &OutVals,
211  SDLoc dl, SelectionDAG &DAG) const override;
212 
213  bool
214  CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
215  bool isVarArg,
216  const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
217  LLVMContext &Context) const override;
218  };
219 }
220 
221 #endif
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:724
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:104
XCoreTargetLowering(const TargetMachine &TM, const XCoreSubtarget &Subtarget)
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
bool isZExtFree(SDValue Val, EVT VT2) const override
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicit...
virtual bool isZExtFree(Type *, Type *) const
Return true if any actual instruction that defines a value of type Ty1 implicitly zero-extends the va...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APInt.h:33
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
ReplaceNodeResults - Replace the results of node with an illegal result type with new values built ou...
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
MVT - Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:41
EVT - Extended Value Type.
Definition: ValueTypes.h:31
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:179
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Class for arbitrary precision integers.
Definition: APInt.h:73
AddrMode
ARM Addressing Modes.
Definition: ARMBaseInfo.h:235
Representation of each machine instruction.
Definition: MachineInstr.h:51
#define N
unsigned getJumpTableEncoding() const override
Return the entry encoding for a jump table in the current function.
const char * getTargetNodeName(unsigned Opcode) const override
getTargetNodeName - This method returns the name of a target specific
Primary interface to the complete machine description for the target machine.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:40
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
This file describes how to lower LLVM code to machine code.