27 #define DEBUG_TYPE "mips-isel"
34 cl::desc(
"Expand double precision loads and "
35 "stores to their single precision "
239 return Subtarget.
hasDSP() ? &Mips::ACC64DSPRegClass : &Mips::ACC64RegClass;
363 case ISD::LOAD:
return lowerLOAD(Op, DAG);
406 if (MultLo.
getNode() != MultNode)
448 if (!
SDValue(ADDENode, 0).use_empty()) {
478 if (MultLo.
getNode() != MultNode)
520 if (!
SDValue(SUBENode, 0).use_empty()) {
569 int32_t Log2IfPositive = (Mask->
getAPIntValue() + 1).exactLogBase2();
571 if (Log2IfPositive <= 0)
575 EVT ExtendTy = cast<VTSDNode>(Op0Op2)->getVT();
577 unsigned Log2 = Log2IfPositive;
580 Log2 == ExtendTySize) {
606 APInt SplatValue, SplatUndef;
607 unsigned SplatBitSize;
610 if (!Node->
isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
631 APInt SplatValue, SplatUndef;
632 unsigned SplatBitSize;
637 if (BVN->
isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs))
682 bool IsLittleEndian = !Subtarget.
isLittle();
685 bool IsConstantMask =
false;
692 if (
isVSplat(Op0Op0, Mask, IsLittleEndian)) {
696 if (
isVSplat(Op1Op0, InvMask, IsLittleEndian) &&
699 else if (
isVSplat(Op1Op1, InvMask, IsLittleEndian) &&
703 IsConstantMask =
true;
713 if (
isVSplat(Op1Op0, InvMask, IsLittleEndian) &&
716 else if (
isVSplat(Op1Op1, InvMask, IsLittleEndian) &&
720 IsConstantMask =
true;
769 if (IsConstantMask) {
815 uint64_t Floor = 1LL <<
Log2_64(C);
816 uint64_t Ceil = Log2Ceil == 64 ? 0LL : 1LL << Log2Ceil;
821 if (C - Floor <= Ceil - C) {
852 APInt SplatValue, SplatUndef;
853 unsigned SplatBitSize;
862 !BV->
isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
864 (SplatBitSize != EltSize) ||
920 EVT ExtendTy = cast<VTSDNode>(Op0Op0->
getOperand(2))->getVT();
923 if (TotalBits == 32 ||
967 default:
return false;
1020 if (Op1 == Op0Op0 && Op2 == Op0Op1)
1023 else if (Op1 == Op0Op1 && Op2 == Op0Op0)
1102 DEBUG(
dbgs() <<
"\nMipsSE DAG Combine:\n";
1104 dbgs() <<
"\n=> \n";
1119 case Mips::BPOSGE32_PSEUDO:
1120 return emitBPOSGE32(MI, BB);
1121 case Mips::SNZ_B_PSEUDO:
1122 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_B);
1123 case Mips::SNZ_H_PSEUDO:
1124 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_H);
1125 case Mips::SNZ_W_PSEUDO:
1126 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_W);
1127 case Mips::SNZ_D_PSEUDO:
1128 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_D);
1129 case Mips::SNZ_V_PSEUDO:
1130 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_V);
1131 case Mips::SZ_B_PSEUDO:
1132 return emitMSACBranchPseudo(MI, BB, Mips::BZ_B);
1133 case Mips::SZ_H_PSEUDO:
1134 return emitMSACBranchPseudo(MI, BB, Mips::BZ_H);
1135 case Mips::SZ_W_PSEUDO:
1136 return emitMSACBranchPseudo(MI, BB, Mips::BZ_W);
1137 case Mips::SZ_D_PSEUDO:
1138 return emitMSACBranchPseudo(MI, BB, Mips::BZ_D);
1139 case Mips::SZ_V_PSEUDO:
1140 return emitMSACBranchPseudo(MI, BB, Mips::BZ_V);
1141 case Mips::COPY_FW_PSEUDO:
1142 return emitCOPY_FW(MI, BB);
1143 case Mips::COPY_FD_PSEUDO:
1144 return emitCOPY_FD(MI, BB);
1145 case Mips::INSERT_FW_PSEUDO:
1146 return emitINSERT_FW(MI, BB);
1147 case Mips::INSERT_FD_PSEUDO:
1148 return emitINSERT_FD(MI, BB);
1149 case Mips::INSERT_B_VIDX_PSEUDO:
1150 case Mips::INSERT_B_VIDX64_PSEUDO:
1151 return emitINSERT_DF_VIDX(MI, BB, 1,
false);
1152 case Mips::INSERT_H_VIDX_PSEUDO:
1153 case Mips::INSERT_H_VIDX64_PSEUDO:
1154 return emitINSERT_DF_VIDX(MI, BB, 2,
false);
1155 case Mips::INSERT_W_VIDX_PSEUDO:
1156 case Mips::INSERT_W_VIDX64_PSEUDO:
1157 return emitINSERT_DF_VIDX(MI, BB, 4,
false);
1158 case Mips::INSERT_D_VIDX_PSEUDO:
1159 case Mips::INSERT_D_VIDX64_PSEUDO:
1160 return emitINSERT_DF_VIDX(MI, BB, 8,
false);
1161 case Mips::INSERT_FW_VIDX_PSEUDO:
1162 case Mips::INSERT_FW_VIDX64_PSEUDO:
1163 return emitINSERT_DF_VIDX(MI, BB, 4,
true);
1164 case Mips::INSERT_FD_VIDX_PSEUDO:
1165 case Mips::INSERT_FD_VIDX64_PSEUDO:
1166 return emitINSERT_DF_VIDX(MI, BB, 8,
true);
1167 case Mips::FILL_FW_PSEUDO:
1168 return emitFILL_FW(MI, BB);
1169 case Mips::FILL_FD_PSEUDO:
1170 return emitFILL_FD(MI, BB);
1171 case Mips::FEXP2_W_1_PSEUDO:
1172 return emitFEXP2_W_1(MI, BB);
1173 case Mips::FEXP2_D_1_PSEUDO:
1174 return emitFEXP2_D_1(MI, BB);
1178 bool MipsSETargetLowering::isEligibleForTailCallOptimization(
1179 const CCState &CCInfo,
unsigned NextStackOffset,
1193 void MipsSETargetLowering::
1195 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
1196 bool IsPICCall,
bool GlobalOrExternal,
bool InternalLinkage,
1197 bool IsCallReloc, CallLoweringInfo &CLI,
SDValue Callee,
1201 InternalLinkage, IsCallReloc, CLI, Callee,
1267 SDValue MipsSETargetLowering::lowerMulDiv(
SDValue Op,
unsigned NewOpc,
1268 bool HasLo,
bool HasHi,
1284 if (!HasLo || !HasHi)
1285 return HasLo ? Lo :
Hi;
1334 if (Opnd.getValueType() ==
MVT::i64)
1382 EVT ViaVecTy = ResVecTy;
1397 SDValue Ops[16] = { LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB,
1398 LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB };
1403 if (ViaVecTy != ResVecTy)
1416 EVT ViaVecTy = VecTy;
1417 SDValue SplatValueA = SplatValue;
1418 SDValue SplatValueB = SplatValue;
1419 SDLoc DL(SplatValue);
1436 SDValue Ops[16] = { SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1437 SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1438 SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1439 SplatValueA, SplatValueB, SplatValueA, SplatValueB };
1444 if (VecTy != ViaVecTy)
1461 APInt BitImm =
APInt(64, 1) << CImm->getAPIntValue();
1473 BitImmHiOp, BitImmLoOp, BitImmHiOp));
1501 DAG.
getNOT(DL, Bit, ResTy));
1508 << cast<ConstantSDNode>(Op->
getOperand(2))->getAPIntValue();
1514 SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(
SDValue Op,
1518 switch (cast<ConstantSDNode>(Op->
getOperand(0))->getZExtValue()) {
1521 case Intrinsic::mips_shilo:
1523 case Intrinsic::mips_dpau_h_qbl:
1525 case Intrinsic::mips_dpau_h_qbr:
1527 case Intrinsic::mips_dpsu_h_qbl:
1529 case Intrinsic::mips_dpsu_h_qbr:
1531 case Intrinsic::mips_dpa_w_ph:
1533 case Intrinsic::mips_dps_w_ph:
1535 case Intrinsic::mips_dpax_w_ph:
1537 case Intrinsic::mips_dpsx_w_ph:
1539 case Intrinsic::mips_mulsa_w_ph:
1541 case Intrinsic::mips_mult:
1543 case Intrinsic::mips_multu:
1545 case Intrinsic::mips_madd:
1547 case Intrinsic::mips_maddu:
1549 case Intrinsic::mips_msub:
1551 case Intrinsic::mips_msubu:
1553 case Intrinsic::mips_addv_b:
1554 case Intrinsic::mips_addv_h:
1555 case Intrinsic::mips_addv_w:
1556 case Intrinsic::mips_addv_d:
1559 case Intrinsic::mips_addvi_b:
1560 case Intrinsic::mips_addvi_h:
1561 case Intrinsic::mips_addvi_w:
1562 case Intrinsic::mips_addvi_d:
1565 case Intrinsic::mips_and_v:
1568 case Intrinsic::mips_andi_b:
1571 case Intrinsic::mips_bclr_b:
1572 case Intrinsic::mips_bclr_h:
1573 case Intrinsic::mips_bclr_w:
1574 case Intrinsic::mips_bclr_d:
1576 case Intrinsic::mips_bclri_b:
1577 case Intrinsic::mips_bclri_h:
1578 case Intrinsic::mips_bclri_w:
1579 case Intrinsic::mips_bclri_d:
1581 case Intrinsic::mips_binsli_b:
1582 case Intrinsic::mips_binsli_h:
1583 case Intrinsic::mips_binsli_w:
1584 case Intrinsic::mips_binsli_d: {
1594 case Intrinsic::mips_binsri_b:
1595 case Intrinsic::mips_binsri_h:
1596 case Intrinsic::mips_binsri_w:
1597 case Intrinsic::mips_binsri_d: {
1607 case Intrinsic::mips_bmnz_v:
1610 case Intrinsic::mips_bmnzi_b:
1614 case Intrinsic::mips_bmz_v:
1617 case Intrinsic::mips_bmzi_b:
1621 case Intrinsic::mips_bneg_b:
1622 case Intrinsic::mips_bneg_h:
1623 case Intrinsic::mips_bneg_w:
1624 case Intrinsic::mips_bneg_d: {
1632 case Intrinsic::mips_bnegi_b:
1633 case Intrinsic::mips_bnegi_h:
1634 case Intrinsic::mips_bnegi_w:
1635 case Intrinsic::mips_bnegi_d:
1638 case Intrinsic::mips_bnz_b:
1639 case Intrinsic::mips_bnz_h:
1640 case Intrinsic::mips_bnz_w:
1641 case Intrinsic::mips_bnz_d:
1644 case Intrinsic::mips_bnz_v:
1647 case Intrinsic::mips_bsel_v:
1652 case Intrinsic::mips_bseli_b:
1657 case Intrinsic::mips_bset_b:
1658 case Intrinsic::mips_bset_h:
1659 case Intrinsic::mips_bset_w:
1660 case Intrinsic::mips_bset_d: {
1668 case Intrinsic::mips_bseti_b:
1669 case Intrinsic::mips_bseti_h:
1670 case Intrinsic::mips_bseti_w:
1671 case Intrinsic::mips_bseti_d:
1674 case Intrinsic::mips_bz_b:
1675 case Intrinsic::mips_bz_h:
1676 case Intrinsic::mips_bz_w:
1677 case Intrinsic::mips_bz_d:
1680 case Intrinsic::mips_bz_v:
1683 case Intrinsic::mips_ceq_b:
1684 case Intrinsic::mips_ceq_h:
1685 case Intrinsic::mips_ceq_w:
1686 case Intrinsic::mips_ceq_d:
1689 case Intrinsic::mips_ceqi_b:
1690 case Intrinsic::mips_ceqi_h:
1691 case Intrinsic::mips_ceqi_w:
1692 case Intrinsic::mips_ceqi_d:
1695 case Intrinsic::mips_cle_s_b:
1696 case Intrinsic::mips_cle_s_h:
1697 case Intrinsic::mips_cle_s_w:
1698 case Intrinsic::mips_cle_s_d:
1701 case Intrinsic::mips_clei_s_b:
1702 case Intrinsic::mips_clei_s_h:
1703 case Intrinsic::mips_clei_s_w:
1704 case Intrinsic::mips_clei_s_d:
1707 case Intrinsic::mips_cle_u_b:
1708 case Intrinsic::mips_cle_u_h:
1709 case Intrinsic::mips_cle_u_w:
1710 case Intrinsic::mips_cle_u_d:
1713 case Intrinsic::mips_clei_u_b:
1714 case Intrinsic::mips_clei_u_h:
1715 case Intrinsic::mips_clei_u_w:
1716 case Intrinsic::mips_clei_u_d:
1719 case Intrinsic::mips_clt_s_b:
1720 case Intrinsic::mips_clt_s_h:
1721 case Intrinsic::mips_clt_s_w:
1722 case Intrinsic::mips_clt_s_d:
1725 case Intrinsic::mips_clti_s_b:
1726 case Intrinsic::mips_clti_s_h:
1727 case Intrinsic::mips_clti_s_w:
1728 case Intrinsic::mips_clti_s_d:
1731 case Intrinsic::mips_clt_u_b:
1732 case Intrinsic::mips_clt_u_h:
1733 case Intrinsic::mips_clt_u_w:
1734 case Intrinsic::mips_clt_u_d:
1737 case Intrinsic::mips_clti_u_b:
1738 case Intrinsic::mips_clti_u_h:
1739 case Intrinsic::mips_clti_u_w:
1740 case Intrinsic::mips_clti_u_d:
1743 case Intrinsic::mips_copy_s_b:
1744 case Intrinsic::mips_copy_s_h:
1745 case Intrinsic::mips_copy_s_w:
1747 case Intrinsic::mips_copy_s_d:
1758 case Intrinsic::mips_copy_u_b:
1759 case Intrinsic::mips_copy_u_h:
1760 case Intrinsic::mips_copy_u_w:
1762 case Intrinsic::mips_copy_u_d:
1776 case Intrinsic::mips_div_s_b:
1777 case Intrinsic::mips_div_s_h:
1778 case Intrinsic::mips_div_s_w:
1779 case Intrinsic::mips_div_s_d:
1782 case Intrinsic::mips_div_u_b:
1783 case Intrinsic::mips_div_u_h:
1784 case Intrinsic::mips_div_u_w:
1785 case Intrinsic::mips_div_u_d:
1788 case Intrinsic::mips_fadd_w:
1789 case Intrinsic::mips_fadd_d:
1793 case Intrinsic::mips_fceq_w:
1794 case Intrinsic::mips_fceq_d:
1797 case Intrinsic::mips_fcle_w:
1798 case Intrinsic::mips_fcle_d:
1801 case Intrinsic::mips_fclt_w:
1802 case Intrinsic::mips_fclt_d:
1805 case Intrinsic::mips_fcne_w:
1806 case Intrinsic::mips_fcne_d:
1809 case Intrinsic::mips_fcor_w:
1810 case Intrinsic::mips_fcor_d:
1813 case Intrinsic::mips_fcueq_w:
1814 case Intrinsic::mips_fcueq_d:
1817 case Intrinsic::mips_fcule_w:
1818 case Intrinsic::mips_fcule_d:
1821 case Intrinsic::mips_fcult_w:
1822 case Intrinsic::mips_fcult_d:
1825 case Intrinsic::mips_fcun_w:
1826 case Intrinsic::mips_fcun_d:
1829 case Intrinsic::mips_fcune_w:
1830 case Intrinsic::mips_fcune_d:
1833 case Intrinsic::mips_fdiv_w:
1834 case Intrinsic::mips_fdiv_d:
1837 case Intrinsic::mips_ffint_u_w:
1838 case Intrinsic::mips_ffint_u_d:
1841 case Intrinsic::mips_ffint_s_w:
1842 case Intrinsic::mips_ffint_s_d:
1845 case Intrinsic::mips_fill_b:
1846 case Intrinsic::mips_fill_h:
1847 case Intrinsic::mips_fill_w:
1848 case Intrinsic::mips_fill_d: {
1857 case Intrinsic::mips_fexp2_w:
1858 case Intrinsic::mips_fexp2_d: {
1864 case Intrinsic::mips_flog2_w:
1865 case Intrinsic::mips_flog2_d:
1867 case Intrinsic::mips_fmadd_w:
1868 case Intrinsic::mips_fmadd_d:
1871 case Intrinsic::mips_fmul_w:
1872 case Intrinsic::mips_fmul_d:
1875 case Intrinsic::mips_fmsub_w:
1876 case Intrinsic::mips_fmsub_d: {
1882 case Intrinsic::mips_frint_w:
1883 case Intrinsic::mips_frint_d:
1885 case Intrinsic::mips_fsqrt_w:
1886 case Intrinsic::mips_fsqrt_d:
1888 case Intrinsic::mips_fsub_w:
1889 case Intrinsic::mips_fsub_d:
1892 case Intrinsic::mips_ftrunc_u_w:
1893 case Intrinsic::mips_ftrunc_u_d:
1896 case Intrinsic::mips_ftrunc_s_w:
1897 case Intrinsic::mips_ftrunc_s_d:
1900 case Intrinsic::mips_ilvev_b:
1901 case Intrinsic::mips_ilvev_h:
1902 case Intrinsic::mips_ilvev_w:
1903 case Intrinsic::mips_ilvev_d:
1906 case Intrinsic::mips_ilvl_b:
1907 case Intrinsic::mips_ilvl_h:
1908 case Intrinsic::mips_ilvl_w:
1909 case Intrinsic::mips_ilvl_d:
1912 case Intrinsic::mips_ilvod_b:
1913 case Intrinsic::mips_ilvod_h:
1914 case Intrinsic::mips_ilvod_w:
1915 case Intrinsic::mips_ilvod_d:
1918 case Intrinsic::mips_ilvr_b:
1919 case Intrinsic::mips_ilvr_h:
1920 case Intrinsic::mips_ilvr_w:
1921 case Intrinsic::mips_ilvr_d:
1924 case Intrinsic::mips_insert_b:
1925 case Intrinsic::mips_insert_h:
1926 case Intrinsic::mips_insert_w:
1927 case Intrinsic::mips_insert_d:
1930 case Intrinsic::mips_insve_b:
1931 case Intrinsic::mips_insve_h:
1932 case Intrinsic::mips_insve_w:
1933 case Intrinsic::mips_insve_d:
1937 case Intrinsic::mips_ldi_b:
1938 case Intrinsic::mips_ldi_h:
1939 case Intrinsic::mips_ldi_w:
1940 case Intrinsic::mips_ldi_d:
1942 case Intrinsic::mips_lsa:
1943 case Intrinsic::mips_dlsa: {
1949 case Intrinsic::mips_maddv_b:
1950 case Intrinsic::mips_maddv_h:
1951 case Intrinsic::mips_maddv_w:
1952 case Intrinsic::mips_maddv_d: {
1958 case Intrinsic::mips_max_s_b:
1959 case Intrinsic::mips_max_s_h:
1960 case Intrinsic::mips_max_s_w:
1961 case Intrinsic::mips_max_s_d:
1964 case Intrinsic::mips_max_u_b:
1965 case Intrinsic::mips_max_u_h:
1966 case Intrinsic::mips_max_u_w:
1967 case Intrinsic::mips_max_u_d:
1970 case Intrinsic::mips_maxi_s_b:
1971 case Intrinsic::mips_maxi_s_h:
1972 case Intrinsic::mips_maxi_s_w:
1973 case Intrinsic::mips_maxi_s_d:
1976 case Intrinsic::mips_maxi_u_b:
1977 case Intrinsic::mips_maxi_u_h:
1978 case Intrinsic::mips_maxi_u_w:
1979 case Intrinsic::mips_maxi_u_d:
1982 case Intrinsic::mips_min_s_b:
1983 case Intrinsic::mips_min_s_h:
1984 case Intrinsic::mips_min_s_w:
1985 case Intrinsic::mips_min_s_d:
1988 case Intrinsic::mips_min_u_b:
1989 case Intrinsic::mips_min_u_h:
1990 case Intrinsic::mips_min_u_w:
1991 case Intrinsic::mips_min_u_d:
1994 case Intrinsic::mips_mini_s_b:
1995 case Intrinsic::mips_mini_s_h:
1996 case Intrinsic::mips_mini_s_w:
1997 case Intrinsic::mips_mini_s_d:
2000 case Intrinsic::mips_mini_u_b:
2001 case Intrinsic::mips_mini_u_h:
2002 case Intrinsic::mips_mini_u_w:
2003 case Intrinsic::mips_mini_u_d:
2006 case Intrinsic::mips_mod_s_b:
2007 case Intrinsic::mips_mod_s_h:
2008 case Intrinsic::mips_mod_s_w:
2009 case Intrinsic::mips_mod_s_d:
2012 case Intrinsic::mips_mod_u_b:
2013 case Intrinsic::mips_mod_u_h:
2014 case Intrinsic::mips_mod_u_w:
2015 case Intrinsic::mips_mod_u_d:
2018 case Intrinsic::mips_mulv_b:
2019 case Intrinsic::mips_mulv_h:
2020 case Intrinsic::mips_mulv_w:
2021 case Intrinsic::mips_mulv_d:
2024 case Intrinsic::mips_msubv_b:
2025 case Intrinsic::mips_msubv_h:
2026 case Intrinsic::mips_msubv_w:
2027 case Intrinsic::mips_msubv_d: {
2033 case Intrinsic::mips_nlzc_b:
2034 case Intrinsic::mips_nlzc_h:
2035 case Intrinsic::mips_nlzc_w:
2036 case Intrinsic::mips_nlzc_d:
2038 case Intrinsic::mips_nor_v: {
2043 case Intrinsic::mips_nori_b: {
2049 case Intrinsic::mips_or_v:
2052 case Intrinsic::mips_ori_b:
2055 case Intrinsic::mips_pckev_b:
2056 case Intrinsic::mips_pckev_h:
2057 case Intrinsic::mips_pckev_w:
2058 case Intrinsic::mips_pckev_d:
2061 case Intrinsic::mips_pckod_b:
2062 case Intrinsic::mips_pckod_h:
2063 case Intrinsic::mips_pckod_w:
2064 case Intrinsic::mips_pckod_d:
2067 case Intrinsic::mips_pcnt_b:
2068 case Intrinsic::mips_pcnt_h:
2069 case Intrinsic::mips_pcnt_w:
2070 case Intrinsic::mips_pcnt_d:
2072 case Intrinsic::mips_shf_b:
2073 case Intrinsic::mips_shf_h:
2074 case Intrinsic::mips_shf_w:
2077 case Intrinsic::mips_sll_b:
2078 case Intrinsic::mips_sll_h:
2079 case Intrinsic::mips_sll_w:
2080 case Intrinsic::mips_sll_d:
2083 case Intrinsic::mips_slli_b:
2084 case Intrinsic::mips_slli_h:
2085 case Intrinsic::mips_slli_w:
2086 case Intrinsic::mips_slli_d:
2089 case Intrinsic::mips_splat_b:
2090 case Intrinsic::mips_splat_h:
2091 case Intrinsic::mips_splat_w:
2092 case Intrinsic::mips_splat_d:
2100 case Intrinsic::mips_splati_b:
2101 case Intrinsic::mips_splati_h:
2102 case Intrinsic::mips_splati_w:
2103 case Intrinsic::mips_splati_d:
2107 case Intrinsic::mips_sra_b:
2108 case Intrinsic::mips_sra_h:
2109 case Intrinsic::mips_sra_w:
2110 case Intrinsic::mips_sra_d:
2113 case Intrinsic::mips_srai_b:
2114 case Intrinsic::mips_srai_h:
2115 case Intrinsic::mips_srai_w:
2116 case Intrinsic::mips_srai_d:
2119 case Intrinsic::mips_srl_b:
2120 case Intrinsic::mips_srl_h:
2121 case Intrinsic::mips_srl_w:
2122 case Intrinsic::mips_srl_d:
2125 case Intrinsic::mips_srli_b:
2126 case Intrinsic::mips_srli_h:
2127 case Intrinsic::mips_srli_w:
2128 case Intrinsic::mips_srli_d:
2131 case Intrinsic::mips_subv_b:
2132 case Intrinsic::mips_subv_h:
2133 case Intrinsic::mips_subv_w:
2134 case Intrinsic::mips_subv_d:
2137 case Intrinsic::mips_subvi_b:
2138 case Intrinsic::mips_subvi_h:
2139 case Intrinsic::mips_subvi_w:
2140 case Intrinsic::mips_subvi_d:
2143 case Intrinsic::mips_vshf_b:
2144 case Intrinsic::mips_vshf_h:
2145 case Intrinsic::mips_vshf_w:
2146 case Intrinsic::mips_vshf_d:
2149 case Intrinsic::mips_xor_v:
2152 case Intrinsic::mips_xori_b:
2174 unsigned Intr = cast<ConstantSDNode>(Op->
getOperand(1))->getZExtValue();
2178 case Intrinsic::mips_extp:
2180 case Intrinsic::mips_extpdp:
2182 case Intrinsic::mips_extr_w:
2184 case Intrinsic::mips_extr_r_w:
2186 case Intrinsic::mips_extr_rs_w:
2188 case Intrinsic::mips_extr_s_h:
2190 case Intrinsic::mips_mthlip:
2192 case Intrinsic::mips_mulsaq_s_w_ph:
2194 case Intrinsic::mips_maq_s_w_phl:
2196 case Intrinsic::mips_maq_s_w_phr:
2198 case Intrinsic::mips_maq_sa_w_phl:
2200 case Intrinsic::mips_maq_sa_w_phr:
2202 case Intrinsic::mips_dpaq_s_w_ph:
2204 case Intrinsic::mips_dpsq_s_w_ph:
2206 case Intrinsic::mips_dpaq_sa_l_w:
2208 case Intrinsic::mips_dpsq_sa_l_w:
2210 case Intrinsic::mips_dpaqx_s_w_ph:
2212 case Intrinsic::mips_dpaqx_sa_w_ph:
2214 case Intrinsic::mips_dpsqx_s_w_ph:
2216 case Intrinsic::mips_dpsqx_sa_w_ph:
2218 case Intrinsic::mips_ld_b:
2219 case Intrinsic::mips_ld_h:
2220 case Intrinsic::mips_ld_w:
2221 case Intrinsic::mips_ld_d:
2242 unsigned Intr = cast<ConstantSDNode>(Op->
getOperand(1))->getZExtValue();
2246 case Intrinsic::mips_st_b:
2247 case Intrinsic::mips_st_h:
2248 case Intrinsic::mips_st_w:
2249 case Intrinsic::mips_st_d:
2260 assert(nOps > 1 &&
"isSplatVector has 0 or 1 sized build vector");
2264 for (
unsigned int i = 1; i < nOps; ++i) {
2279 SDValue MipsSETargetLowering::
2302 if (isa<ConstantSDNode>(Op))
2304 if (isa<ConstantFPSDNode>(Op))
2334 APInt SplatValue, SplatUndef;
2335 unsigned SplatBitSize;
2345 if (SplatBitSize != 8 && SplatBitSize != 16 && SplatBitSize != 32 &&
2353 if (ResTy.isInteger() && !HasAnyUndefs && SplatValue.
isSignedIntN(10))
2358 switch (SplatBitSize) {
2379 if (ViaVecTy != ResTy)
2395 for (
unsigned i = 0; i < NumElts; ++i) {
2427 int SHFIndices[4] = { -1, -1, -1, -1 };
2429 if (Indices.
size() < 4)
2432 for (
unsigned i = 0; i < 4; ++i) {
2433 for (
unsigned j = i; j < Indices.
size(); j += 4) {
2434 int Idx = Indices[j];
2440 if (Idx < 0 || Idx >= 4)
2446 if (SHFIndices[i] == -1)
2447 SHFIndices[i] = Idx;
2451 if (!(Idx == -1 || Idx == SHFIndices[i]))
2458 for (
int i = 3; i >= 0; --i) {
2459 int Idx = SHFIndices[i];
2475 template <
typename ValType>
2478 unsigned CheckStride,
2480 ValType ExpectedIndex,
unsigned ExpectedIndexStride) {
2484 if (*I != -1 && *I != ExpectedIndex)
2486 ExpectedIndex += ExpectedIndexStride;
2490 for (
unsigned n = 0; n < CheckStride && I != End; ++n, ++
I)
2507 assert((Indices.
size() % 2) == 0);
2509 int SplatIndex = -1;
2510 for (
const auto &V : Indices) {
2517 return fitsRegularPattern<int>(Indices.begin(), 1, Indices.end(), SplatIndex,
2539 assert((Indices.
size() % 2) == 0);
2543 const auto &Begin = Indices.
begin();
2544 const auto &End = Indices.
end();
2548 if (fitsRegularPattern<int>(Begin, 2, End, 0, 2))
2550 else if (fitsRegularPattern<int>(Begin, 2, End, Indices.
size(), 2))
2557 if (fitsRegularPattern<int>(Begin + 1, 2, End, 0, 2))
2559 else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.
size(), 2))
2585 assert((Indices.
size() % 2) == 0);
2589 const auto &Begin = Indices.
begin();
2590 const auto &End = Indices.
end();
2594 if (fitsRegularPattern<int>(Begin, 2, End, 1, 2))
2596 else if (fitsRegularPattern<int>(Begin, 2, End, Indices.
size() + 1, 2))
2603 if (fitsRegularPattern<int>(Begin + 1, 2, End, 1, 2))
2605 else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.
size() + 1, 2))
2632 assert((Indices.
size() % 2) == 0);
2636 const auto &Begin = Indices.
begin();
2637 const auto &End = Indices.
end();
2641 if (fitsRegularPattern<int>(Begin, 2, End, 0, 1))
2643 else if (fitsRegularPattern<int>(Begin, 2, End, Indices.
size(), 1))
2650 if (fitsRegularPattern<int>(Begin + 1, 2, End, 0, 1))
2652 else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.
size(), 1))
2679 assert((Indices.
size() % 2) == 0);
2681 unsigned HalfSize = Indices.
size() / 2;
2684 const auto &Begin = Indices.
begin();
2685 const auto &End = Indices.
end();
2689 if (fitsRegularPattern<int>(Begin, 2, End, HalfSize, 1))
2691 else if (fitsRegularPattern<int>(Begin, 2, End, Indices.
size() + HalfSize, 1))
2698 if (fitsRegularPattern<int>(Begin + 1, 2, End, HalfSize, 1))
2700 else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.
size() + HalfSize,
2727 assert((Indices.
size() % 2) == 0);
2731 const auto &Begin = Indices.
begin();
2732 const auto &Mid = Indices.
begin() + Indices.
size() / 2;
2733 const auto &End = Indices.
end();
2735 if (fitsRegularPattern<int>(Begin, 1, Mid, 0, 2))
2737 else if (fitsRegularPattern<int>(Begin, 1, Mid, Indices.
size(), 2))
2742 if (fitsRegularPattern<int>(Mid, 1, End, 0, 2))
2744 else if (fitsRegularPattern<int>(Mid, 1, End, Indices.
size(), 2))
2770 assert((Indices.
size() % 2) == 0);
2774 const auto &Begin = Indices.
begin();
2775 const auto &Mid = Indices.
begin() + Indices.
size() / 2;
2776 const auto &End = Indices.
end();
2778 if (fitsRegularPattern<int>(Begin, 1, Mid, 1, 2))
2780 else if (fitsRegularPattern<int>(Begin, 1, Mid, Indices.
size() + 1, 2))
2785 if (fitsRegularPattern<int>(Mid, 1, End, 1, 2))
2787 else if (fitsRegularPattern<int>(Mid, 1, End, Indices.
size() + 1, 2))
2811 bool Using1stVec =
false;
2812 bool Using2ndVec =
false;
2816 for (
int i = 0; i < ResTyNumElts; ++i) {
2818 int Idx = Indices[i];
2820 if (0 <= Idx && Idx < ResTyNumElts)
2822 if (ResTyNumElts <= Idx && Idx < ResTyNumElts * 2)
2832 if (Using1stVec && Using2ndVec) {
2835 }
else if (Using1stVec)
2837 else if (Using2ndVec)
2840 llvm_unreachable(
"shuffle vector mask references neither vector operand?");
2859 if (!ResTy.is128BitVector())
2862 int ResTyNumElts = ResTy.getVectorNumElements();
2865 for (
int i = 0; i < ResTyNumElts; ++i)
2937 BuildMI(BB, DL, TII->
get(Mips::BPOSGE32)).addMBB(TBB);
2942 .addReg(Mips::ZERO).
addImm(0);
2948 .addReg(Mips::ZERO).
addImm(1);
2961 unsigned BranchOp)
const{
3009 .addReg(Mips::ZERO).
addImm(0);
3015 .addReg(Mips::ZERO).
addImm(1);
3059 &Mips::MSA128WEvensRegClass);
3061 BuildMI(*BB, MI, DL, TII->
get(Mips::SPLATI_W), Wt).addReg(Ws).
addImm(Lane);
3121 &Mips::MSA128WEvensRegClass);
3127 BuildMI(*BB, MI, DL, TII->
get(Mips::INSVE_W), Wd)
3161 BuildMI(*BB, MI, DL, TII->
get(Mips::INSVE_D), Wd)
3192 MipsSETargetLowering::emitINSERT_DF_VIDX(
MachineInstr *MI,
3194 unsigned EltSizeInBytes,
3207 unsigned EltLog2Size;
3208 unsigned InsertOp = 0;
3209 unsigned InsveOp = 0;
3210 switch (EltSizeInBytes) {
3215 InsertOp = Mips::INSERT_B;
3216 InsveOp = Mips::INSVE_B;
3217 VecRC = &Mips::MSA128BRegClass;
3221 InsertOp = Mips::INSERT_H;
3222 InsveOp = Mips::INSVE_H;
3223 VecRC = &Mips::MSA128HRegClass;
3227 InsertOp = Mips::INSERT_W;
3228 InsveOp = Mips::INSVE_W;
3229 VecRC = &Mips::MSA128WRegClass;
3233 InsertOp = Mips::INSERT_D;
3234 InsveOp = Mips::INSVE_D;
3235 VecRC = &Mips::MSA128DRegClass;
3244 .
addImm(EltSizeInBytes == 8 ? Mips::sub_64 : Mips::sub_lo);
3249 if (EltSizeInBytes != 1) {
3251 BuildMI(*BB, MI, DL, TII->
get(Mips::SLL), LaneTmp1)
3259 BuildMI(*BB, MI, DL, TII->
get(Mips::SLD_B), WdTmp1)
3267 BuildMI(*BB, MI, DL, TII->
get(InsveOp), WdTmp2)
3274 BuildMI(*BB, MI, DL, TII->
get(InsertOp), WdTmp2)
3288 BuildMI(*BB, MI, DL, TII->
get(Mips::SLD_B), Wd)
3374 BuildMI(*BB, MI, DL, TII->
get(Mips::LDI_W), Ws1).addImm(1);
3375 BuildMI(*BB, MI, DL, TII->
get(Mips::FFINT_U_W), Ws2).addReg(Ws1);
3403 BuildMI(*BB, MI, DL, TII->
get(Mips::LDI_D), Ws1).addImm(1);
3404 BuildMI(*BB, MI, DL, TII->
get(Mips::FFINT_U_D), Ws2).addReg(Ws1);
const MipsTargetLowering * createMipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
value_iterator value_begin() const
unsigned getIncomingArgSize() const
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
void push_back(const T &Elt)
BUILTIN_OP_END - This must be the last enum value in this list.
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
SDValue getValue(unsigned R) const
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant, which is required to be operand #1) half of the integer or float value specified as operand #0.
static SDValue genConstMult(SDValue X, uint64_t C, SDLoc DL, EVT VT, EVT ShiftTy, SelectionDAG &DAG)
uint64_t getZExtValue() const
Get zero extended value.
const MipsSubtarget & Subtarget
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS=0, unsigned Align=1, bool *Fast=nullptr) const override
Determine if the target supports unaligned memory accesses.
static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG)
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
SDVTList getVTList() const
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
SDValue getMergeValues(ArrayRef< SDValue > Ops, SDLoc dl)
Create a MERGE_VALUES node from the given operands.
Carry-setting nodes for multiple precision addition and subtraction.
static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Get a value with low bits set.
const MipsInstrInfo * getInstrInfo() const override
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
unsigned getInRegsParamsCount() const
unsigned getNumOperands() const
Return the number of values used by this operation.
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *fromMBB)
transferSuccessorsAndUpdatePHIs - Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor blocks which refer to fromMBB to refer to this.
const SDValue & getOperand(unsigned Num) const
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
const SDValue & getBasePtr() const
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
virtual const TargetRegisterClass * getRepRegClassFor(MVT VT) const
Return the 'representative' register class for the specified value type.
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
unsigned getResNo() const
get the index which selects a specific result in the SDNode
This SDNode is used to implement the code generator support for the llvm IR shufflevector instruction...
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
COPY - Target-independent register copy.
bool isVector() const
isVector - Return true if this is a vector value type.
SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
const HexagonInstrInfo * TII
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Shift and rotation operations.
bool systemSupportsUnalignedAccess() const
Does the system support unaligned memory access.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
static cl::opt< bool > EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden, cl::desc("MIPS: Enable tail calls."), cl::init(false))
APInt LLVM_ATTRIBUTE_UNUSED_RESULT lshr(unsigned shiftAmt) const
Logical right-shift function.
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn't supported on the target and indicate what to d...
static SDValue lowerMSABitClearImm(SDValue Op, SelectionDAG &DAG)
static bool isConstantOrUndefBUILD_VECTOR(const BuildVectorSDNode *Op)
Number of individual test Apply this number of consecutive mutations to each input exit after the first new interesting input is found the minimized corpus is saved into the first input directory Number of jobs to run If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
int getMaskElt(unsigned Idx) const
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
static SDValue lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
EVT getVectorElementType() const
getVectorElementType - Given a vector type, return the type of each element.
bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef, unsigned &SplatBitSize, bool &HasAnyUndefs, unsigned MinSplatBits=0, bool isBigEndian=false) const
Check if this is a constant splat, and if so, find the smallest element size that splats the vector...
static bool isVSplat(SDValue N, APInt &Imm, bool IsLittleEndian)
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
value_iterator value_end() const
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
static bool isVECTOR_SHUFFLE_SPLATI(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
Simple integer binary arithmetic operators.
static bool isConstantOrUndef(const SDValue Op)
const SDValue & getBasePtr() const
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
const APInt & getAPIntValue() const
TargetConstant* - Like Constant*, but the DAG does not do any folding, simplification, or lowering of the constant.
EVT getMemoryVT() const
Return the type of the in-memory value.
static SDValue lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
const DataLayout & getDataLayout() const
static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
const BasicBlock * getBasicBlock() const
getBasicBlock - Return the LLVM basic block that this instance corresponded to originally.
UNDEF - An undefined node.
This class is used to represent ISD::STORE nodes.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable...
TargetInstrInfo - Interface to description of machine instruction set.
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Get a value with high bits set.
static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
SDNode * getNode() const
get the SDNode which holds the desired result
IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
bundle_iterator< MachineInstr, instr_iterator > iterator
initializer< Ty > init(const Ty &Val)
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
static SDValue lowerVECTOR_SHUFFLE_ILVEV(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
APInt LLVM_ATTRIBUTE_UNUSED_RESULT trunc(unsigned width) const
Truncate to new width.
static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc)
MVT - Machine Value Type.
LLVM Basic Block Representation.
static SDValue getBuildVectorSplat(EVT VecTy, SDValue SplatValue, bool BigEndian, SelectionDAG &DAG)
const SDValue & getOperand(unsigned i) const
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
Simple binary floating point operators.
void setTargetDAGCombine(ISD::NodeType NT)
Targets should invoke this method for each target independent node that they want to provide a custom...
bool isNonTemporal() const
static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC)
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL...
const MachineOperand & getOperand(unsigned i) const
Carry-using nodes for multiple precision addition and subtraction.
static bool isVectorAllOnes(SDValue N)
static SDValue lowerVECTOR_SHUFFLE_PCKEV(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
INSERT_SUBREG - This instruction takes three operands: a register that has subregisters, a register providing an insert value, and a subregister index.
static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr)
bool isBeforeLegalize() const
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang","erlang-compatible garbage collector")
SDValue getTargetConstant(uint64_t Val, SDLoc DL, EVT VT, bool isOpaque=false)
unsigned getBitWidth() const
Return the number of bits in the APInt.
unsigned getOpcode() const
static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static mvt_range vector_valuetypes()
bool useSoftFloat() const
const SDValue & getValue() const
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
EVT - Extended Value Type.
static bool fitsRegularPattern(typename SmallVectorImpl< ValType >::const_iterator Begin, unsigned CheckStride, typename SmallVectorImpl< ValType >::const_iterator End, ValType ExpectedIndex, unsigned ExpectedIndexStride)
Determine whether a range fits a regular pattern of values.
MachinePointerInfo - This class contains a discriminated union of information about pointers in memor...
uint64_t getConstantOperandVal(unsigned Num) const
Helper method returns the integer value of a ConstantSDNode operand.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
static bool selectMADD(SDNode *ADDENode, SelectionDAG *CurDAG)
bool isBuildVectorAllOnes(const SDNode *N)
Node predicates.
SDValue getNOT(SDLoc DL, SDValue Val, EVT VT)
Create a bitwise NOT operation as (XOR Val, -1).
CCState - This class holds information needed while lowering arguments and return values...
static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
const MipsRegisterInfo * getRegisterInfo() const override
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG, const TargetLowering::DAGCombinerInfo &DCI, const MipsSETargetLowering *TL)
double Log2(double Value)
Log2 - This function returns the log base 2 of the specified value.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
static SDValue lowerMSABitClear(SDValue Op, SelectionDAG &DAG)
BRCOND - Conditional branch.
const SDValue & getChain() const
static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG)
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc)
Represents one node in the SelectionDAG.
bool use_empty() const
Return true if there are no nodes using value ResNo of Node.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
AAMDNodes getAAInfo() const
Returns the AA info that describes the dereference.
unsigned Log2_64_Ceil(uint64_t Value)
Log2_64_Ceil - This function returns the ceil log base 2 of the specified value, 64 if the value is z...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG, const MipsSubtarget &Subtarget)
static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG)
Class for arbitrary precision integers.
static bool isSplatVector(const BuildVectorSDNode *N)
Check if the given BuildVectorSDNode is a splat.
bool isSignedIntN(unsigned N) const
Check if this APInt has an N-bits signed integer value.
A "pseudo-class" with methods for operating on BUILD_VECTORs.
Select(COND, TRUEVAL, FALSEVAL).
static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty, SelectionDAG &DAG, const MipsSubtarget &Subtarget)
ZERO_EXTEND - Used for integer types, zeroing the new bits.
bool isPowerOf2_64(uint64_t Value)
isPowerOf2_64 - This function returns true if the argument is a power of two 0 (64 bit edition...
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
static SDValue lowerVECTOR_SHUFFLE_ILVOD(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
static SDValue lowerMSASplatZExt(SDValue Op, unsigned OpNr, SelectionDAG &DAG)
static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static bool isBitwiseInverse(SDValue N, SDValue OfNode)
static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr)
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)
bool isAllOnesValue() const
Determine if all bits are set.
Representation of each machine instruction.
static SDValue initAccumulator(SDValue In, SDLoc DL, SelectionDAG &DAG)
Bitwise operators - logical and, logical or, logical xor.
SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
bool isSingleFloat() const
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
const TargetRegisterClass * getRepRegClassFor(MVT VT) const override
Return the 'representative' register class for the specified value type.
Fast - This calling convention attempts to make calls as fast as possible (e.g.
static SDValue lowerMSABinaryBitImmIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc, SDValue Imm, bool BigEndian)
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
virtual void getOpndList(SmallVectorImpl< SDValue > &Ops, std::deque< std::pair< unsigned, SDValue > > &RegsToPass, bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const
This function fills Ops, which is the list of operands that will later be used when a function call n...
EVT getValueType() const
Return the ValueType of the referenced return value.
SDValue getConstant(uint64_t Val, SDLoc DL, EVT VT, bool isTarget=false, bool isOpaque=false)
bool is128BitVector() const
is128BitVector - Return true if this is a 128-bit vector type.
unsigned getReg() const
getReg - Returns the register number.
void insert(iterator MBBI, MachineBasicBlock *MBB)
LLVM Value Representation.
FMA - Perform a * b + c with no intermediate rounding step.
static SDValue extractLOHI(SDValue Op, SDLoc DL, SelectionDAG &DAG)
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
SDValue getValueType(EVT)
void printrWithDepth(raw_ostream &O, const SelectionDAG *G=nullptr, unsigned depth=100) const
Print a SelectionDAG node and children up to depth "depth." The given SelectionDAG allows target-spec...
static SDValue lowerVECTOR_SHUFFLE_SHF(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
BasicBlockListType::iterator iterator
static SDValue lowerVECTOR_SHUFFLE_ILVL(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
void ReplaceAllUsesOfValueWith(SDValue From, SDValue To)
Replace any uses of From with To, leaving uses of other values produced by From.Val alone...
MipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
SetCC operator - This evaluates to a true value iff the condition is true.
SDValue getSetCC(SDLoc DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except that the first operand is an imme...
void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC)
Enable MSA support for the given integer type and Register class.
static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG)
TRUNCATE - Completely drop the high bits.
unsigned getAlignment() const
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
void addSuccessor(MachineBasicBlock *succ, uint32_t weight=0)
addSuccessor - Add succ as a successor of this MachineBasicBlock.
unsigned Log2_64(uint64_t Value)
Log2_64 - This function returns the floor log base 2 of the specified value, -1 if the value is zero...
EVT changeVectorElementTypeToInteger() const
changeVectorElementTypeToInteger - Return a vector with the same number of elements as this vector...
static cl::opt< bool > NoDPLoadStore("mno-ldc1-sdc1", cl::init(false), cl::desc("Expand double precision loads and ""stores to their single precision ""counterparts"))
static SDValue lowerVECTOR_SHUFFLE_PCKOD(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
void addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC)
Enable MSA support for the given floating-point type and Register class.
MVT getSimpleVT() const
getSimpleVT - Return the SimpleValueType held in the specified simple EVT.
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
uint64_t getZExtValue() const
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
unsigned getVectorNumElements() const
getVectorNumElements - Given a vector type, return the number of elements it contains.
This class is used to represent ISD::LOAD nodes.