29 #define DEBUG_TYPE "legalize-types"
35 void DAGTypeLegalizer::ScalarizeVectorResult(
SDNode *
N,
unsigned ResNo) {
36 DEBUG(
dbgs() <<
"Scalarize node result " << ResNo <<
": ";
44 dbgs() <<
"ScalarizeVectorResult #" << ResNo <<
": ";
52 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N);
break;
58 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N);
break;
60 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));
break;
63 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N);
break;
64 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N);
break;
66 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N);
break;
67 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N);
break;
100 R = ScalarizeVecRes_UnaryOp(N);
126 R = ScalarizeVecRes_BinOp(N);
129 R = ScalarizeVecRes_TernaryOp(N);
135 SetScalarizedVector(
SDValue(N, ResNo), R);
145 SDValue DAGTypeLegalizer::ScalarizeVecRes_TernaryOp(
SDNode *N) {
153 SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(
SDNode *N,
155 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
156 return GetScalarizedVector(Op);
159 SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(
SDNode *N) {
165 SDValue DAGTypeLegalizer::ScalarizeVecRes_BUILD_VECTOR(
SDNode *N) {
175 SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(
SDNode *N) {
183 cast<CvtRndSatSDNode>(
N)->getCvtCode());
186 SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(
SDNode *N) {
192 SDValue DAGTypeLegalizer::ScalarizeVecRes_FP_ROUND(
SDNode *N) {
205 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(
SDNode *N) {
217 assert(N->
isUnindexed() &&
"Indexed vector load?");
237 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(
SDNode *N) {
251 Op = GetScalarizedVector(Op);
261 SDValue DAGTypeLegalizer::ScalarizeVecRes_InregOp(
SDNode *N) {
269 SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(
SDNode *N) {
279 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSELECT(
SDNode *N) {
302 if (ScalarBool != VecBool) {
304 switch (ScalarBool) {
325 LHS.getValueType(), Cond, LHS,
329 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(
SDNode *N) {
336 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(
SDNode *N) {
347 "Scalar/Vector type mismatch");
363 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(
SDNode *N) {
368 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
369 return GetScalarizedVector(N->
getOperand(Op));
372 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(
SDNode *N) {
375 "Operand types must be vectors");
378 EVT OpVT = LHS.getValueType();
384 LHS = GetScalarizedVector(LHS);
385 RHS = GetScalarizedVector(RHS);
403 return DAG.
getNode(ExtendCode,
DL, NVT, Res);
411 bool DAGTypeLegalizer::ScalarizeVectorOperand(
SDNode *N,
unsigned OpNo) {
412 DEBUG(
dbgs() <<
"Scalarize node operand " << OpNo <<
": ";
417 if (!Res.getNode()) {
421 dbgs() <<
"ScalarizeVectorOperand Op #" << OpNo <<
": ";
427 Res = ScalarizeVecOp_BITCAST(N);
437 Res = ScalarizeVecOp_UnaryOp(N);
440 Res = ScalarizeVecOp_CONCAT_VECTORS(N);
443 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N);
446 Res = ScalarizeVecOp_VSELECT(N);
449 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo);
452 Res = ScalarizeVecOp_FP_ROUND(N, OpNo);
458 if (!Res.getNode())
return false;
462 if (Res.getNode() ==
N)
466 "Invalid operand expansion");
468 ReplaceValueWith(
SDValue(N, 0), Res);
474 SDValue DAGTypeLegalizer::ScalarizeVecOp_BITCAST(
SDNode *N) {
482 SDValue DAGTypeLegalizer::ScalarizeVecOp_UnaryOp(
SDNode *N) {
484 "Unexpected vector type!");
495 SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(
SDNode *N) {
498 Ops[i] = GetScalarizedVector(N->
getOperand(i));
505 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(
SDNode *N) {
517 SDValue DAGTypeLegalizer::ScalarizeVecOp_VSELECT(
SDNode *N) {
528 assert(N->
isUnindexed() &&
"Indexed store of one-element vector?");
529 assert(OpNo == 1 &&
"Do not know how to scalarize this operand!");
548 SDValue DAGTypeLegalizer::ScalarizeVecOp_FP_ROUND(
SDNode *N,
unsigned OpNo) {
565 void DAGTypeLegalizer::SplitVectorResult(
SDNode *N,
unsigned ResNo) {
578 dbgs() <<
"SplitVectorResult #" << ResNo <<
": ";
587 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi);
break;
589 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi);
break;
590 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi);
break;
596 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi);
break;
601 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
604 SplitVecRes_MLOAD(cast<MaskedLoadSDNode>(N), Lo, Hi);
607 SplitVecRes_MGATHER(cast<MaskedGatherSDNode>(N), Lo, Hi);
610 SplitVecRes_SETCC(N, Lo, Hi);
613 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
646 SplitVecRes_UnaryOp(N, Lo, Hi);
652 SplitVecRes_ExtendOp(N, Lo, Hi);
681 SplitVecRes_BinOp(N, Lo, Hi);
684 SplitVecRes_TernaryOp(N, Lo, Hi);
693 void DAGTypeLegalizer::SplitVecRes_BinOp(
SDNode *N,
SDValue &Lo,
696 GetSplitVector(N->
getOperand(0), LHSLo, LHSHi);
698 GetSplitVector(N->
getOperand(1), RHSLo, RHSHi);
705 void DAGTypeLegalizer::SplitVecRes_TernaryOp(
SDNode *N,
SDValue &Lo,
708 GetSplitVector(N->
getOperand(0), Op0Lo, Op0Hi);
710 GetSplitVector(N->
getOperand(1), Op1Lo, Op1Hi);
712 GetSplitVector(N->
getOperand(2), Op2Lo, Op2Hi);
716 Op0Lo, Op1Lo, Op2Lo);
718 Op0Hi, Op1Hi, Op2Hi);
721 void DAGTypeLegalizer::SplitVecRes_BITCAST(
SDNode *N,
SDValue &Lo,
733 switch (getTypeAction(InVT)) {
747 GetExpandedOp(InOp, Lo, Hi);
758 GetSplitVector(InOp, Lo, Hi);
770 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
778 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(
SDNode *N,
SDValue &Lo,
791 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(
SDNode *N,
SDValue &Lo,
793 assert(!(N->
getNumOperands() & 1) &&
"Unsupported CONCAT_VECTORS");
796 if (NumSubvectors == 1) {
812 void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(
SDNode *N,
SDValue &Lo,
822 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
828 void DAGTypeLegalizer::SplitVecRes_INSERT_SUBVECTOR(
SDNode *N,
SDValue &Lo,
834 GetSplitVector(Vec, Lo, Hi);
844 SDValue SubVecPtr = GetVectorElementPointer(StackPtr, SubVecVT, Idx);
852 false,
false,
false, 0);
858 DAG.
getConstant(IncrementSize, dl, StackPtr.getValueType()));
862 false,
false,
false,
MinAlign(Alignment, IncrementSize));
865 void DAGTypeLegalizer::SplitVecRes_FPOWI(
SDNode *N,
SDValue &Lo,
873 void DAGTypeLegalizer::SplitVecRes_InregOp(
SDNode *N,
SDValue &Lo,
876 GetSplitVector(N->
getOperand(0), LHSLo, LHSHi);
880 std::tie(LoVT, HiVT) =
889 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(
SDNode *N,
SDValue &Lo,
895 GetSplitVector(Vec, Lo, Hi);
898 unsigned IdxVal = CIdx->getZExtValue();
900 if (IdxVal < LoNumElts)
924 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
932 false,
false,
false, 0);
936 StackPtr = DAG.
getNode(
ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
938 StackPtr.getValueType()));
942 false,
false,
false,
MinAlign(Alignment, IncrementSize));
945 void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(
SDNode *N,
SDValue &Lo,
972 EVT LoMemVT, HiMemVT;
977 isInvariant, Alignment, AAInfo);
984 HiMemVT,
isVolatile, isNonTemporal, isInvariant, Alignment,
994 ReplaceValueWith(
SDValue(LD, 1), Ch);
1011 unsigned SecondHalfAlignment =
1013 Alignment/2 : Alignment;
1016 std::tie(MaskLo, MaskHi) = DAG.
SplitVector(Mask, dl);
1019 EVT LoMemVT, HiMemVT;
1024 std::tie(Src0Lo, Src0Hi) = DAG.
SplitVector(Src0, dl);
1031 Lo = DAG.
getMaskedLoad(LoVT, dl, Ch, Ptr, MaskLo, Src0Lo, LoMemVT, MMO,
1043 Hi = DAG.
getMaskedLoad(HiVT, dl, Ch, Ptr, MaskHi, Src0Hi, HiMemVT, MMO,
1054 ReplaceValueWith(
SDValue(MLD, 1), Ch);
1070 std::tie(MaskLo, MaskHi) = DAG.
SplitVector(Mask, dl);
1073 EVT LoMemVT, HiMemVT;
1087 SDValue OpsLo[] = {Ch, Src0Lo, MaskLo, Ptr, IndexLo};
1091 SDValue OpsHi[] = {Ch, Src0Hi, MaskHi, Ptr, IndexHi};
1102 ReplaceValueWith(
SDValue(MGT, 1), Ch);
1109 "Operand types must be vectors");
1124 void DAGTypeLegalizer::SplitVecRes_UnaryOp(
SDNode *N,
SDValue &Lo,
1160 void DAGTypeLegalizer::SplitVecRes_ExtendOp(
SDNode *N,
SDValue &Lo,
1182 if ((NumElements & 1) == 0 &&
1191 EVT SplitLoVT, SplitHiVT;
1195 DEBUG(
dbgs() <<
"Split vector extend via incremental extend:";
1209 SplitVecRes_UnaryOp(N, Lo, Hi);
1217 GetSplitVector(N->
getOperand(0), Inputs[0], Inputs[1]);
1218 GetSplitVector(N->
getOperand(1), Inputs[2], Inputs[3]);
1226 for (
unsigned High = 0; High < 2; ++High) {
1233 unsigned InputUsed[2] = { -1U, -1U };
1234 unsigned FirstMaskIdx = High * NewElts;
1235 bool useBuildVector =
false;
1236 for (
unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
1238 int Idx = N->
getMaskElt(FirstMaskIdx + MaskOffset);
1241 unsigned Input = (
unsigned)Idx / NewElts;
1250 Idx -= Input * NewElts;
1255 if (InputUsed[OpNo] == Input) {
1258 }
else if (InputUsed[OpNo] == -1U) {
1260 InputUsed[OpNo] = Input;
1268 useBuildVector =
true;
1276 if (useBuildVector) {
1281 for (
unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
1283 int Idx = N->
getMaskElt(FirstMaskIdx + MaskOffset);
1286 unsigned Input = (
unsigned)Idx / NewElts;
1295 Idx -= Input * NewElts;
1305 }
else if (InputUsed[0] == -1U) {
1309 SDValue Op0 = Inputs[InputUsed[0]];
1311 SDValue Op1 = InputUsed[1] == -1U ?
1312 DAG.
getUNDEF(NewVT) : Inputs[InputUsed[1]];
1330 bool DAGTypeLegalizer::SplitVectorOperand(
SDNode *N,
unsigned OpNo) {
1340 if (!Res.getNode()) {
1344 dbgs() <<
"SplitVectorOperand Op #" << OpNo <<
": ";
1351 case ISD::SETCC: Res = SplitVecOp_VSETCC(N);
break;
1357 Res = SplitVecOp_TruncateHelper(N);
1361 Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo);
1364 Res = SplitVecOp_MSTORE(cast<MaskedStoreSDNode>(N), OpNo);
1367 Res = SplitVecOp_MSCATTER(cast<MaskedScatterSDNode>(N), OpNo);
1370 Res = SplitVecOp_MGATHER(cast<MaskedGatherSDNode>(N), OpNo);
1373 Res = SplitVecOp_VSELECT(N, OpNo);
1378 Res = SplitVecOp_TruncateHelper(N);
1380 Res = SplitVecOp_UnaryOp(N);
1385 Res = SplitVecOp_TruncateHelper(N);
1387 Res = SplitVecOp_UnaryOp(N);
1397 Res = SplitVecOp_UnaryOp(N);
1403 if (!Res.getNode())
return false;
1407 if (Res.getNode() ==
N)
1411 "Invalid operand expansion");
1413 ReplaceValueWith(
SDValue(N, 0), Res);
1417 SDValue DAGTypeLegalizer::SplitVecOp_VSELECT(
SDNode *N,
unsigned OpNo) {
1420 assert(OpNo == 0 &&
"Illegal operand must be mask");
1431 assert(Lo.getValueType() == Hi.getValueType() &&
1432 "Lo and Hi have differing types");
1436 assert(LoOpVT == HiOpVT &&
"Asymmetric vector split?");
1438 SDValue LoOp0, HiOp0, LoOp1, HiOp1, LoMask, HiMask;
1474 Lo = BitConvertToInteger(Lo);
1475 Hi = BitConvertToInteger(Hi);
1481 JoinIntegers(Lo, Hi));
1484 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(
SDNode *N) {
1493 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1495 if (IdxVal < LoElts) {
1497 "Extracted subvector crosses vector split!");
1506 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(
SDNode *N) {
1511 if (isa<ConstantSDNode>(Idx)) {
1512 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1516 GetSplitVector(Vec, Lo, Hi);
1518 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1520 if (IdxVal < LoElts)
1539 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
1557 std::tie(MaskLo, MaskHi) = DAG.
SplitVector(Mask, dl);
1560 EVT LoMemVT, HiMemVT;
1568 std::tie(IndexLo, IndexHi) = DAG.
SplitVector(Index, dl);
1570 IndexLo = IndexHi = Index;
1577 SDValue OpsLo[] = {Ch, Src0Lo, MaskLo, Ptr, IndexLo};
1587 SDValue OpsHi[] = {Ch, Src0Hi, MaskHi, Ptr, IndexHi};
1598 ReplaceValueWith(
SDValue(MGT, 1), Ch);
1602 ReplaceValueWith(
SDValue(MGT, 0), Res);
1616 EVT LoMemVT, HiMemVT;
1620 GetSplitVector(Data, DataLo, DataHi);
1622 GetSplitVector(Mask, MaskLo, MaskHi);
1626 unsigned SecondHalfAlignment =
1628 Alignment/2 : Alignment;
1667 EVT LoMemVT, HiMemVT;
1671 GetSplitVector(Data, DataLo, DataHi);
1673 GetSplitVector(Mask, MaskLo, MaskHi);
1679 PtrLo = PtrHi = Ptr;
1685 IndexLo = IndexHi = Index;
1693 SDValue OpsLo[] = {Ch, DataLo, MaskLo, PtrLo, IndexLo};
1702 SDValue OpsHi[] = {Ch, DataHi, MaskHi, PtrHi, IndexHi};
1712 assert(N->
isUnindexed() &&
"Indexed store of vector?");
1713 assert(OpNo == 1 &&
"Can only split the stored value");
1727 EVT LoMemVT, HiMemVT;
1730 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1734 LoMemVT, isVol, isNT, Alignment, AAInfo);
1737 isVol, isNT, Alignment, AAInfo);
1746 HiMemVT, isVol, isNT, Alignment, AAInfo);
1750 isVol, isNT, Alignment, AAInfo);
1755 SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(
SDNode *N) {
1766 for (
unsigned i = 0, e = Op.getValueType().getVectorNumElements();
1777 SDValue DAGTypeLegalizer::SplitVecOp_TruncateHelper(
SDNode *N) {
1803 assert(!(NumElements & 1) &&
"Splitting vector, but not in half!");
1811 if (InElementSize <= OutElementSize * 2)
1812 return SplitVecOp_UnaryOp(N);
1819 EVT HalfElementVT = IsFloat ?
1821 EVT::getIntegerVT(*DAG.getContext(), InElementSize/2);
1844 "Operand types must be vectors");
1846 SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes;
1850 unsigned PartElements = Lo0.getValueType().getVectorNumElements();
1884 void DAGTypeLegalizer::WidenVectorResult(
SDNode *N,
unsigned ResNo) {
1885 DEBUG(
dbgs() <<
"Widen node result " << ResNo <<
": ";
1897 dbgs() <<
"WidenVectorResult #" << ResNo <<
": ";
1904 case ISD::BITCAST: Res = WidenVecRes_BITCAST(N);
break;
1911 case ISD::LOAD: Res = WidenVecRes_LOAD(N);
break;
1915 case ISD::SELECT: Res = WidenVecRes_SELECT(N);
break;
1917 case ISD::SETCC: Res = WidenVecRes_SETCC(N);
break;
1918 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N);
break;
1920 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
1923 Res = WidenVecRes_MLOAD(cast<MaskedLoadSDNode>(N));
1936 Res = WidenVecRes_Binary(N);
1950 Res = WidenVecRes_BinaryCanTrap(N);
1954 Res = WidenVecRes_POWI(N);
1960 Res = WidenVecRes_Shift(N);
1973 Res = WidenVecRes_Convert(N);
1996 Res = WidenVecRes_Unary(N);
1999 Res = WidenVecRes_Ternary(N);
2005 SetWidenedVector(
SDValue(N, ResNo), Res);
2027 SDValue DAGTypeLegalizer::WidenVecRes_BinaryCanTrap(
SDNode *N) {
2036 NumElts = NumElts / 2;
2058 unsigned ConcatEnd = 0;
2066 while (CurNumElts != 0) {
2067 while (CurNumElts >= NumElts) {
2074 ConcatOps[ConcatEnd++] = DAG.
getNode(Opcode, dl, VT, EOp1, EOp2);
2076 CurNumElts -= NumElts;
2079 NumElts = NumElts / 2;
2084 for (
unsigned i = 0; i != CurNumElts; ++i, ++Idx) {
2091 ConcatOps[ConcatEnd++] = DAG.
getNode(Opcode, dl, WidenEltVT,
2099 if (ConcatEnd == 1) {
2100 VT = ConcatOps[0].getValueType();
2102 return ConcatOps[0];
2109 while (ConcatOps[ConcatEnd-1].getValueType() != MaxVT) {
2110 Idx = ConcatEnd - 1;
2111 VT = ConcatOps[Idx--].getValueType();
2112 while (Idx >= 0 && ConcatOps[Idx].getValueType() == VT)
2125 unsigned NumToInsert = ConcatEnd - Idx - 1;
2126 for (
unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) {
2131 ConcatOps[Idx+1] = VecOp;
2132 ConcatEnd = Idx + 2;
2138 unsigned RealVals = ConcatEnd - Idx - 1;
2139 unsigned SubConcatEnd = 0;
2140 unsigned SubConcatIdx = Idx + 1;
2141 while (SubConcatEnd < RealVals)
2142 SubConcatOps[SubConcatEnd++] = ConcatOps[++Idx];
2143 while (SubConcatEnd < OpsToConcat)
2144 SubConcatOps[SubConcatEnd++] = undefVec;
2146 NextVT, SubConcatOps);
2147 ConcatEnd = SubConcatIdx + 1;
2152 if (ConcatEnd == 1) {
2153 VT = ConcatOps[0].getValueType();
2155 return ConcatOps[0];
2160 if (NumOps != ConcatEnd ) {
2162 for (
unsigned j = ConcatEnd; j < NumOps; ++j)
2163 ConcatOps[j] = UndefVal;
2186 InVTNumElts = InVT.getVectorNumElements();
2187 if (InVTNumElts == WidenNumElts) {
2189 return DAG.
getNode(Opcode,
DL, WidenVT, InOp);
2200 if (WidenNumElts % InVTNumElts == 0) {
2202 unsigned NumConcat = WidenNumElts/InVTNumElts;
2206 for (
unsigned i = 1; i != NumConcat; ++i)
2210 return DAG.
getNode(Opcode,
DL, WidenVT, InVec);
2214 if (InVTNumElts % WidenNumElts == 0) {
2220 return DAG.
getNode(Opcode,
DL, WidenVT, InVal);
2228 unsigned MinElts =
std::min(InVTNumElts, WidenNumElts);
2230 for (i=0; i < MinElts; ++i) {
2235 Ops[i] = DAG.
getNode(Opcode,
DL, EltVT, Val);
2241 for (; i < WidenNumElts; ++i)
2259 EVT ShVT = ShOp.getValueType();
2261 ShOp = GetWidenedVector(ShOp);
2262 ShVT = ShOp.getValueType();
2267 if (ShVT != ShWidenVT)
2268 ShOp = ModifyToType(ShOp, ShWidenVT);
2284 .getVectorElementType(),
2291 SDValue DAGTypeLegalizer::WidenVecRes_MERGE_VALUES(
SDNode *N,
unsigned ResNo) {
2292 SDValue WidenVec = DisintegrateMERGE_VALUES(N, ResNo);
2293 return GetWidenedVector(WidenVec);
2303 switch (getTypeAction(InVT)) {
2315 InOp = GetPromotedInteger(InOp);
2317 if (WidenVT.
bitsEq(InVT))
2330 InOp = GetWidenedVector(InOp);
2332 if (WidenVT.
bitsEq(InVT))
2341 if (WidenSize % InSize == 0 && InVT !=
MVT::x86mmx) {
2346 unsigned NewNumElts = WidenSize / InSize;
2364 for (
unsigned i = 1; i < NewNumElts; ++i)
2376 return CreateStackStoreLoad(InOp, WidenVT);
2379 SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(
SDNode *N) {
2393 assert(WidenNumElts >= NumElts &&
"Shrinking vector instead of widening!");
2394 NewOps.append(WidenNumElts - NumElts, DAG.
getUNDEF(EltVT));
2399 SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(
SDNode *N) {
2407 bool InputWidened =
false;
2415 for (
unsigned i=0; i < NumOperands; ++i)
2417 for (
unsigned i = NumOperands; i != NumConcat; ++i)
2422 InputWidened =
true;
2426 for (i=1; i < NumOperands; ++i)
2430 if (i == NumOperands)
2435 if (NumOperands == 2) {
2438 for (
unsigned i = 0; i < NumInElts; ++i) {
2440 MaskOps[i + NumInElts] = i + WidenNumElts;
2454 for (
unsigned i=0; i < NumOperands; ++i) {
2457 InOp = GetWidenedVector(InOp);
2458 for (
unsigned j=0; j < NumInElts; ++j)
2464 for (; Idx < WidenNumElts; ++Idx)
2465 Ops[Idx] = UndefVal;
2469 SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(
SDNode *N) {
2484 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(
N)->getCvtCode();
2488 InOp = GetWidenedVector(InOp);
2491 if (InVTNumElts == WidenNumElts)
2502 if (WidenNumElts % InVTNumElts == 0) {
2504 unsigned NumConcat = WidenNumElts/InVTNumElts;
2508 for (
unsigned i = 1; i != NumConcat; ++i)
2516 if (InVTNumElts % WidenNumElts == 0) {
2532 unsigned MinElts =
std::min(InVTNumElts, WidenNumElts);
2534 for (i=0; i < MinElts; ++i) {
2543 for (; i < WidenNumElts; ++i)
2549 SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(
SDNode *N) {
2558 InOp = GetWidenedVector(InOp);
2563 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
2564 if (IdxVal == 0 && InVT == WidenVT)
2569 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts)
2578 for (i=0; i < NumElts; ++i)
2585 for (; i < WidenNumElts; ++i)
2590 SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(
SDNode *N) {
2604 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType);
2606 Result = GenWidenVectorLoads(LdChain, LD);
2612 if (LdChain.
size() == 1)
2613 NewChain = LdChain[0];
2619 ReplaceValueWith(
SDValue(N, 1), NewChain);
2634 Mask = GetWidenedVector(Mask);
2636 EVT BoolVT = getSetCCResultType(WidenVT);
2643 unsigned NumConcat = WidenNumElts / MaskNumElts;
2647 for (
unsigned i = 1; i != NumConcat; ++i)
2662 SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(
SDNode *N) {
2677 CondEltVT, WidenNumElts);
2679 Cond1 = GetWidenedVector(Cond1);
2687 SDValue SplitSelect = SplitVecOp_VSELECT(N, 0);
2688 SDValue Res = ModifyToType(SplitSelect, WidenVT);
2693 Cond1 = ModifyToType(Cond1, CondWidenVT);
2698 assert(InOp1.
getValueType() == WidenVT && InOp2.getValueType() == WidenVT);
2700 WidenVT, Cond1, InOp1, InOp2);
2703 SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(
SDNode *N) {
2714 "Scalar/Vector type mismatch");
2742 for (
unsigned i = 0; i != NumElts; ++i) {
2744 if (Idx < (
int)NumElts)
2745 NewMask.push_back(Idx);
2747 NewMask.push_back(Idx - NumElts + WidenNumElts);
2749 for (
unsigned i = NumElts; i != WidenNumElts; ++i)
2750 NewMask.push_back(-1);
2757 "Operands must be vectors");
2759 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2763 assert(InVT.
isVector() &&
"can not widen non-vector type");
2771 SDValue SplitVSetCC = SplitVecOp_VSETCC(N);
2772 SDValue Res = ModifyToType(SplitVSetCC, WidenVT);
2776 InOp1 = GetWidenedVector(InOp1);
2783 "Input not widened to expected type!");
2793 bool DAGTypeLegalizer::WidenVectorOperand(
SDNode *N,
unsigned OpNo) {
2794 DEBUG(
dbgs() <<
"Widen node operand " << OpNo <<
": ";
2806 dbgs() <<
"WidenVectorOperand op #" << OpNo <<
": ";
2816 case ISD::STORE: Res = WidenVecOp_STORE(N);
break;
2817 case ISD::MSTORE: Res = WidenVecOp_MSTORE(N, OpNo);
break;
2818 case ISD::SETCC: Res = WidenVecOp_SETCC(N);
break;
2823 Res = WidenVecOp_EXTEND(N);
2832 Res = WidenVecOp_Convert(N);
2837 if (!Res.getNode())
return false;
2841 if (Res.getNode() ==
N)
2846 "Invalid operand expansion");
2848 ReplaceValueWith(
SDValue(N, 0), Res);
2861 return WidenVecOp_Convert(N);
2862 InOp = GetWidenedVector(InOp);
2865 "Input wasn't widened!");
2877 FixedEltVT == InEltVT) {
2879 "Not enough elements in the fixed type for the operand!");
2881 "We can't have the same type as we started with!");
2898 return WidenVecOp_Convert(N);
2925 InOp = GetWidenedVector(InOp);
2931 for (
unsigned i=0; i < NumElts; ++i)
2948 unsigned InWidenSize = InWidenVT.getSizeInBits();
2952 unsigned NewNumElts = InWidenSize / Size;
2962 return CreateStackStoreLoad(InOp, VT);
2965 SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(
SDNode *N) {
2980 for (
unsigned i=0; i < NumOperands; ++i) {
2983 InOp = GetWidenedVector(InOp);
2984 for (
unsigned j=0; j < NumInElts; ++j)
2992 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(
SDNode *N) {
2998 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(
SDNode *N) {
3011 GenWidenVectorTruncStores(StChain, ST);
3013 GenWidenVectorStores(StChain, ST);
3015 if (StChain.size() == 1)
3021 SDValue DAGTypeLegalizer::WidenVecOp_MSTORE(
SDNode *N,
unsigned OpNo) {
3024 EVT MaskVT = Mask.getValueType();
3027 SDValue WideVal = GetWidenedVector(StVal);
3031 Mask = GetWidenedVector(Mask);
3040 unsigned NumConcat = WidenNumElts / MaskNumElts;
3044 for (
unsigned i = 1; i != NumConcat; ++i)
3049 assert(Mask.getValueType().getVectorNumElements() ==
3051 "Mask and data vectors should have the same number of elements");
3097 unsigned Width,
EVT WidenVT,
3098 unsigned Align = 0,
unsigned WidenEx = 0) {
3102 unsigned AlignInBits =
Align*8;
3105 EVT RetVT = WidenEltVT;
3106 if (Width == WidenEltWidth)
3120 (WidenWidth % MemVTWidth) == 0 &&
3122 (MemVTWidth <= Width ||
3123 (
Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
3136 (WidenWidth % MemVTWidth) == 0 &&
3138 (MemVTWidth <= Width ||
3139 (
Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
3154 unsigned Start,
unsigned End) {
3156 SDLoc dl(LdOps[Start]);
3157 EVT LdTy = LdOps[Start].getValueType();
3165 for (
unsigned i = Start + 1; i != End; ++i) {
3166 EVT NewLdTy = LdOps[i].getValueType();
3167 if (NewLdTy != LdTy) {
3205 int WidthDiff = WidenWidth - LdWidth;
3209 EVT NewVT =
FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
3217 if (LdWidth <= NewVTWidth) {
3219 unsigned NumElts = WidenWidth / NewVTWidth;
3224 if (NewVT == WidenVT)
3227 assert(WidenWidth % NewVTWidth == 0);
3228 unsigned NumConcat = WidenWidth / NewVTWidth;
3231 ConcatOps[0] = LdOp;
3232 for (
unsigned i = 1; i != NumConcat; ++i)
3233 ConcatOps[i] = UndefVal;
3241 LdWidth -= NewVTWidth;
3242 unsigned Offset = 0;
3244 while (LdWidth > 0) {
3245 unsigned Increment = NewVTWidth / 8;
3246 Offset += Increment;
3251 if (LdWidth < NewVTWidth) {
3253 NewVT =
FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
3255 L = DAG.
getLoad(NewVT, dl, Chain, BasePtr,
3257 isNonTemporal, isInvariant,
MinAlign(Align, Increment),
3264 while (size < LdOp->getValueSizeInBits(0)) {
3271 L = DAG.
getLoad(NewVT, dl, Chain, BasePtr,
3273 isNonTemporal, isInvariant,
MinAlign(Align, Increment),
3281 LdWidth -= NewVTWidth;
3285 unsigned End = LdOps.
size();
3286 if (!LdOps[0].getValueType().isVector())
3296 EVT LdTy = LdOps[i].getValueType();
3299 for (--i; i >= 0; --i) {
3300 LdTy = LdOps[i].getValueType();
3306 ConcatOps[--Idx] = LdOps[i];
3307 for (--i; i >= 0; --i) {
3308 EVT NewLdTy = LdOps[i].getValueType();
3309 if (NewLdTy != LdTy) {
3316 ConcatOps[--Idx] = LdOps[i];
3329 for (; i != End-Idx; ++i)
3330 WidenOps[i] = ConcatOps[Idx+i];
3331 for (; i != NumOps; ++i)
3332 WidenOps[i] = UndefVal;
3365 Ops[0] = DAG.
getExtLoad(ExtType, dl, EltVT, Chain, BasePtr,
3367 LdEltVT,
isVolatile, isNonTemporal, isInvariant,
3370 unsigned i = 0, Offset = Increment;
3371 for (i=1; i < NumElts; ++i, Offset += Increment) {
3376 Ops[i] = DAG.
getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr,
3385 for (; i != WidenNumElts; ++i)
3415 unsigned Offset = 0;
3416 while (StWidth != 0) {
3420 unsigned Increment = NewVTWidth / 8;
3431 StWidth -= NewVTWidth;
3432 Offset += Increment;
3437 }
while (StWidth != 0 && StWidth >= NewVTWidth);
3440 unsigned NumElts = ValWidth / NewVTWidth;
3444 Idx = Idx * ValEltWidth / NewVTWidth;
3454 StWidth -= NewVTWidth;
3455 Offset += Increment;
3459 }
while (StWidth != 0 && StWidth >= NewVTWidth);
3461 Idx = Idx * NewVTWidth / ValEltWidth;
3502 unsigned Offset = Increment;
3503 for (
unsigned i=1; i < NumElts; ++i, Offset += Increment) {
3525 "input and widen element type must match");
3534 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) {
3535 unsigned NumConcat = WidenNumElts / InNumElts;
3539 for (
unsigned i = 1; i != NumConcat; ++i)
3545 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts)
3553 unsigned MinNumElts =
std::min(WidenNumElts, InNumElts);
3555 for (Idx = 0; Idx < MinNumElts; ++Idx)
3561 for ( ; Idx < WidenNumElts; ++Idx)
3562 Ops[Idx] = UndefVal;
SDValue getTruncStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT TVT, bool isNonTemporal, bool isVolatile, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes())
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
unsigned getValueSizeInBits(unsigned ResNo) const
Returns MVT::getSizeInBits(getValueType(ResNo)).
void push_back(const T &Elt)
The memory access reads data.
SDValue getValue(unsigned R) const
const SDValue & getValue() const
The memory access writes data.
bool isTruncatingStore() const
Return true if the op does a truncation before store.
LLVMContext * getContext() const
SDValue UnrollVectorOp(SDNode *N, unsigned ResNE=0)
Utility function used by legalize and lowering to "unroll" a vector operation by splitting out the sc...
void dump() const
Dump this node, for debugging.
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an vector value) starting with the ...
LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const
Return how we should legalize values of this type, either it is already legal (return 'Legal') or we ...
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
SDValue getZeroExtendVectorInReg(SDValue Op, SDLoc DL, EVT VT)
Return an operation which will zero extend the low lanes of the operand into the specified vector typ...
unsigned getPrefTypeAlignment(Type *Ty) const
Returns the preferred stack/global alignment for the specified type.
std::pair< EVT, EVT > GetSplitDestVTs(const EVT &VT) const
Compute the VTs needed for the low/hi parts of a type which is split (or expanded) into two not neces...
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
static ISD::NodeType getExtendForContent(BooleanContent Content)
const SDValue & getSrc0() const
Type * getTypeForEVT(LLVMContext &Context) const
getTypeForEVT - This method returns an LLVM type corresponding to the specified EVT.
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
bool isUnindexed() const
Return true if this is NOT a pre/post inc/dec load/store.
unsigned getNumOperands() const
Return the number of values used by this operation.
const SDValue & getOperand(unsigned Num) const
SDValue getMaskedGather(SDVTList VTs, EVT VT, SDLoc dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO)
[US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned integers.
CvtCode
CvtCode enum - This enum defines the various converts CONVERT_RNDSAT supports.
const SDValue & getBasePtr() const
INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector with VECTOR2 inserted into VECTOR1 at the ...
static SDValue BuildVectorFromScalar(SelectionDAG &DAG, EVT VecTy, SmallVectorImpl< SDValue > &LdOps, unsigned Start, unsigned End)
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
bool bitsLT(EVT VT) const
bitsLT - Return true if this has less bits than VT.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag=true)
Reports a serious error, calling any installed error handler.
This SDNode is used to implement the code generator support for the llvm IR shufflevector instruction...
bool isVector() const
isVector - Return true if this is a vector value type.
SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
virtual bool canOpTrap(unsigned Op, EVT VT) const
Returns true if the operation can trap for the value type.
MachineMemOperand - A description of a memory reference used in the backend.
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Shift and rotation operations.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
MachineFunction & getMachineFunction() const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
MachinePointerInfo getWithOffset(int64_t O) const
EVT getScalarType() const
getScalarType - If this is a vector type, return the element type, otherwise return this...
Number of individual test Apply this number of consecutive mutations to each input exit after the first new interesting input is found the minimized corpus is saved into the first input directory Number of jobs to run If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
int getMaskElt(unsigned Idx) const
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
ISD::LoadExtType getExtensionType() const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
SDValue getAnyExtendVectorInReg(SDValue Op, SDLoc DL, EVT VT)
Return an operation which will any-extend the low lanes of the operand into the specified vector type...
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
This class is used to represent an MSTORE node.
virtual MVT getVectorIdxTy(const DataLayout &DL) const
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
EVT getVectorElementType() const
getVectorElementType - Given a vector type, return the type of each element.
load Combine Adjacent Loads
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
Simple integer binary arithmetic operators.
SDValue getVectorShuffle(EVT VT, SDLoc dl, SDValue N1, SDValue N2, const int *MaskElts)
Return an ISD::VECTOR_SHUFFLE node.
const SDValue & getBasePtr() const
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
EVT getMemoryVT() const
Return the type of the in-memory value.
const DataLayout & getDataLayout() const
UNDEF - An undefined node.
This class is used to represent ISD::STORE nodes.
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable...
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
SDNode * getNode() const
get the SDNode which holds the desired result
unsigned getStoreSize() const
getStoreSize - Return the number of bytes overwritten by a store of the specified value type...
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
SDValue getMaskedScatter(SDVTList VTs, EVT VT, SDLoc dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO)
static EVT FindMemType(SelectionDAG &DAG, const TargetLowering &TLI, unsigned Width, EVT WidenVT, unsigned Align=0, unsigned WidenEx=0)
const SDValue & getOperand(unsigned i) const
The instances of the Type class are immutable: once they are created, they are never changed...
This is an important class for using LLVM in a threaded context.
Simple binary floating point operators.
bool isNonTemporal() const
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL...
std::pair< SDValue, SDValue > SplitVectorOperand(const SDNode *N, unsigned OpNo)
Split the node's operand with EXTRACT_SUBVECTOR and return the low/high part.
unsigned getOriginalAlignment() const
Returns alignment and volatility of the memory access.
static EVT getFloatingPointVT(unsigned BitWidth)
getFloatingPointVT - Returns the EVT that represents a floating point type with the given number of b...
SDValue getTargetConstant(uint64_t Val, SDLoc DL, EVT VT, bool isOpaque=false)
unsigned getOpcode() const
const SDValue & getBasePtr() const
const SDValue & getValue() const
SDValue getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes())
Bit counting operators with an undefined result for zero inputs.
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
EVT - Extended Value Type.
const SDValue & getMask() const
bool bitsEq(EVT VT) const
bitsEq - Return true if this has the same number of bits as VT.
SDValue getMaskedLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, SDValue Mask, SDValue Src0, EVT MemVT, MachineMemOperand *MMO, ISD::LoadExtType)
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
For targets without i1 registers, this gives the nature of the high-bits of boolean values held in ty...
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements)
getVectorVT - Returns the EVT that represents a vector NumElements in length, where each element is o...
MachinePointerInfo - This class contains a discriminated union of information about pointers in memor...
SDValue getMaskedStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, SDValue Mask, EVT MemVT, MachineMemOperand *MMO, bool IsTrunc)
SDValue CreateStackTemporary(EVT VT, unsigned minAlign=1)
Create a stack temporary, suitable for holding the specified value type.
const MachinePointerInfo & getPointerInfo() const
const MDNode * getRanges() const
Returns the Ranges that describes the dereference.
bool isUNINDEXEDLoad(const SDNode *N)
Returns true if the specified node is an unindexed load.
TokenFactor - This node takes multiple tokens as input and produces a single token result...
SDValue getConvertRndSat(EVT VT, SDLoc dl, SDValue Val, SDValue DTy, SDValue STy, SDValue Rnd, SDValue Sat, ISD::CvtCode Code)
Returns the ConvertRndSat Note: Avoid using this node because it may disappear in the future and most...
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
std::pair< SDValue, SDValue > SplitVector(const SDValue &N, const SDLoc &DL, const EVT &LoVT, const EVT &HiVT)
Split the vector with EXTRACT_SUBVECTOR using the provides VTs and return the low/high part...
SDNode * UpdateNodeOperands(SDNode *N, SDValue Op)
Mutate the specified node in-place to have the specified operands.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
X = FP_ROUND_INREG(Y, VT) - This operator takes an FP register, and rounds it to a floating point val...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const
Return the ValueType of the result of SETCC operations.
const SDValue & getChain() const
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Byte Swap and Counting operators.
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
AAMDNodes getAAInfo() const
Returns the AA info that describes the dereference.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
const SDValue & getValue() const
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
Select(COND, TRUEVAL, FALSEVAL).
op_iterator op_begin() const
ZERO_EXTEND - Used for integer types, zeroing the new bits.
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
ANY_EXTEND - Used for integer types. The high bits are undefined.
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
iterator_range< value_op_iterator > op_values() const
const SDValue & getMask() const
uint64_t MinAlign(uint64_t A, uint64_t B)
MinAlign - A and B are either alignments or offsets.
Bitwise operators - logical and, logical or, logical xor.
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
op_iterator op_end() const
This class is used to represent an MSCATTER node.
const SDValue & getIndex() const
EVT getValueType() const
Return the ValueType of the referenced return value.
SDValue getConstant(uint64_t Val, SDLoc DL, EVT VT, bool isTarget=false, bool isOpaque=false)
CONVERT_RNDSAT - This operator is used to support various conversions between various types (float...
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
SDValue getSelect(SDLoc DL, EVT VT, SDValue Cond, SDValue LHS, SDValue RHS)
Helper function to make it easier to build Select's if you just have operands and don't want to check...
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
This class is used to represent an MLOAD node.
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
FMA - Perform a * b + c with no intermediate rounding step.
const SDValue & getBasePtr() const
bool isTruncatingStore() const
Return true if the op does a truncation before store.
This class is used to represent an MGATHER node.
SDValue getValueType(EVT)
const TargetLowering & getTargetLoweringInfo() const
SDValue getSignExtendVectorInReg(SDValue Op, SDLoc DL, EVT VT)
Return an operation which will sign extend the low lanes of the operand into the specified vector typ...
bool isPowerOf2_32(uint32_t Value)
isPowerOf2_32 - This function returns true if the argument is a power of two > 0. ...
SetCC operator - This evaluates to a true value iff the condition is true.
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
static bool isVolatile(Instruction *Inst)
BooleanContent
Enum that describes how the target represents true/false values.
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
TRUNCATE - Completely drop the high bits.
unsigned getAlignment() const
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2, FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR - Perform various unary floating point operations.
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
getIntegerVT - Returns the EVT that represents an integer with the given number of bits...
SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a scalar value into element 0 of the...
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
unsigned getVectorNumElements() const
getVectorNumElements - Given a vector type, return the number of elements it contains.
This class is used to represent ISD::LOAD nodes.