14 #ifndef LLVM_TARGET_TARGETSUBTARGETINFO_H
15 #define LLVM_TARGET_TARGETSUBTARGETINFO_H
24 class MachineFunction;
28 class TargetFrameLowering;
29 class TargetInstrInfo;
31 class TargetRegisterClass;
32 class TargetRegisterInfo;
33 class TargetSchedModel;
34 class TargetSelectionDAGInfo;
35 struct MachineSchedPolicy;
36 template <
typename T>
class SmallVectorImpl;
57 const unsigned *
OC,
const unsigned *FP);
142 unsigned NumRegionInstrs)
const {}
156 return CriticalPathRCs.
clear();
173 virtual bool useAA()
const;
const_iterator end(StringRef path)
Get end iterator over path.
virtual bool enableMachineScheduler() const
True if the subtarget should run MachineScheduler after aggressive coalescing.
virtual bool enableAtomicExpand() const
True if the subtarget should run the atomic expansion pass.
virtual bool enableSubRegLiveness() const
Enable tracking of subregister liveness in register allocator.
const_iterator begin(StringRef path)
Get begin iterator over path.
virtual bool enablePostRAScheduler() const
True if the subtarget should run a scheduler after register allocation.
SubtargetInfoKV - Used to provide key value pairs for CPU and arbitrary pointers. ...
virtual CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const
virtual AntiDepBreakMode getAntiDepBreakMode() const
Provide an instruction scheduling machine model to CodeGen passes.
virtual std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints() const
Return PBQPConstraint(s) for the target.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
virtual const InstrItineraryData * getInstrItineraryData() const
getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual bool enableJoinGlobalCopies() const
True if the subtarget should enable joining global copies.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
virtual void adjustSchedDependency(SUnit *def, SUnit *use, SDep &dep) const
Itinerary data supplied by a subtarget to be used by a target.
TargetSelectionDAGInfo - Targets can subclass this to parameterize the SelectionDAG lowering and inst...
TargetInstrInfo - Interface to description of machine instruction set.
SDep - Scheduling dependency.
virtual void overrideSchedPolicy(MachineSchedPolicy &Policy, MachineInstr *begin, MachineInstr *end, unsigned NumRegionInstrs) const
Override generic scheduling policy within a region.
Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...
virtual ~TargetSubtargetInfo()
virtual bool enableEarlyIfConversion() const
Enable the use of the early if conversion pass.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual bool enableMachineSchedDefaultSched() const
True if the machine scheduler should disable the TLI preference for preRA scheduling with the source ...
Triple - Helper class for working with autoconf configuration names.
virtual const TargetSelectionDAGInfo * getSelectionDAGInfo() const
virtual const TargetFrameLowering * getFrameLowering() const
Specify the latency in cpu cycles for a particular scheduling class and def index.
virtual const TargetLowering * getTargetLowering() const
virtual unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const
Resolve a SchedClass at runtime, where SchedClass identifies an MCSchedClassDesc with the isVariant p...
Information about stack frame layout on the target.
Specify the number of cycles allowed after instruction issue before a particular use operand reads it...
TargetSubtargetInfo - Generic base class for all target subtargets.
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.
Representation of each machine instruction.
These values represent a non-pipelined step in the execution of an instruction.
MCSubtargetInfo - Generic base class for all target subtargets.
virtual bool enableRALocalReassignment(CodeGenOpt::Level OptLevel) const
True if the subtarget should run the local reassignment heuristic of the register allocator...
virtual void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const
virtual const TargetInstrInfo * getInstrInfo() const
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
StringRef - Represent a constant reference to a string, i.e.
SmallVectorImpl< const TargetRegisterClass * > RegClassVector
SUnit - Scheduling unit. This is a node in the scheduling DAG.
virtual bool useAA() const
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.).