LLVM  3.7.0
Namespaces | Macros | Enumerations | Functions | Variables
AMDGPU.h File Reference
#include "llvm/Support/TargetRegistry.h"
#include "llvm/Target/TargetMachine.h"
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Namespaces

 llvm
 Compute iterated dominance frontiers using a linear time algorithm.
 
 llvm::AMDGPU
 
 ShaderType
 
 AMDGPUAS
 OpenCL uses address spaces to differentiate between various memory regions on the hardware.
 

Macros

#define END_OF_TEXT_LABEL_NAME   "EndOfTextLabel"
 

Enumerations

enum  llvm::AMDGPU::TargetIndex {
  llvm::AMDGPU::TI_CONSTDATA_START, llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD0, llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD1, llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD2,
  llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD3
}
 
enum  ShaderType::Type { ShaderType::PIXEL = 0, ShaderType::VERTEX = 1, ShaderType::GEOMETRY = 2, ShaderType::COMPUTE = 3 }
 
enum  AMDGPUAS::AddressSpaces : unsigned {
  AMDGPUAS::PRIVATE_ADDRESS = 0, AMDGPUAS::GLOBAL_ADDRESS = 1, AMDGPUAS::CONSTANT_ADDRESS = 2, AMDGPUAS::LOCAL_ADDRESS = 3,
  AMDGPUAS::FLAT_ADDRESS = 4, AMDGPUAS::REGION_ADDRESS = 5, AMDGPUAS::PARAM_D_ADDRESS = 6, AMDGPUAS::PARAM_I_ADDRESS = 7,
  AMDGPUAS::CONSTANT_BUFFER_0 = 8, AMDGPUAS::CONSTANT_BUFFER_1 = 9, AMDGPUAS::CONSTANT_BUFFER_2 = 10, AMDGPUAS::CONSTANT_BUFFER_3 = 11,
  AMDGPUAS::CONSTANT_BUFFER_4 = 12, AMDGPUAS::CONSTANT_BUFFER_5 = 13, AMDGPUAS::CONSTANT_BUFFER_6 = 14, AMDGPUAS::CONSTANT_BUFFER_7 = 15,
  AMDGPUAS::CONSTANT_BUFFER_8 = 16, AMDGPUAS::CONSTANT_BUFFER_9 = 17, AMDGPUAS::CONSTANT_BUFFER_10 = 18, AMDGPUAS::CONSTANT_BUFFER_11 = 19,
  AMDGPUAS::CONSTANT_BUFFER_12 = 20, AMDGPUAS::CONSTANT_BUFFER_13 = 21, AMDGPUAS::CONSTANT_BUFFER_14 = 22, AMDGPUAS::CONSTANT_BUFFER_15 = 23,
  AMDGPUAS::ADDRESS_NONE = 24, AMDGPUAS::LAST_ADDRESS = ADDRESS_NONE, AMDGPUAS::UNKNOWN_ADDRESS_SPACE = ~0u
}
 

Functions

FunctionPassllvm::createR600VectorRegMerger (TargetMachine &tm)
 
FunctionPassllvm::createR600TextureIntrinsicsReplacer ()
 
FunctionPassllvm::createR600ExpandSpecialInstrsPass (TargetMachine &tm)
 
FunctionPassllvm::createR600EmitClauseMarkers ()
 
FunctionPassllvm::createR600ClauseMergePass (TargetMachine &tm)
 
FunctionPassllvm::createR600Packetizer (TargetMachine &tm)
 
FunctionPassllvm::createR600ControlFlowFinalizer (TargetMachine &tm)
 
FunctionPassllvm::createAMDGPUCFGStructurizerPass ()
 
FunctionPassllvm::createSITypeRewriter ()
 
FunctionPassllvm::createSIAnnotateControlFlowPass ()
 Create the annotation pass. More...
 
FunctionPassllvm::createSIFoldOperandsPass ()
 
FunctionPassllvm::createSILowerI1CopiesPass ()
 
FunctionPassllvm::createSIShrinkInstructionsPass ()
 
FunctionPassllvm::createSILoadStoreOptimizerPass (TargetMachine &tm)
 
FunctionPassllvm::createSILowerControlFlowPass (TargetMachine &tm)
 
FunctionPassllvm::createSIFixControlFlowLiveIntervalsPass ()
 
FunctionPassllvm::createSIFixSGPRCopiesPass (TargetMachine &tm)
 
FunctionPassllvm::createSIFixSGPRLiveRangesPass ()
 
FunctionPass * llvm::createSICodeEmitterPass (formatted_raw_ostream &OS)
 
FunctionPassllvm::createSIInsertWaits (TargetMachine &tm)
 
FunctionPassllvm::createSIPrepareScratchRegs ()
 
void llvm::initializeSIFoldOperandsPass (PassRegistry &)
 
void llvm::initializeSILowerI1CopiesPass (PassRegistry &)
 
void llvm::initializeSILoadStoreOptimizerPass (PassRegistry &)
 
FunctionPassllvm::createAMDGPUPromoteAlloca (const AMDGPUSubtarget &ST)
 
Passllvm::createAMDGPUStructurizeCFGPass ()
 
FunctionPassllvm::createAMDGPUISelDag (TargetMachine &tm)
 This pass converts a legalized DAG into a AMDGPU-specific. More...
 
ModulePassllvm::createAMDGPUAlwaysInlinePass ()
 
void llvm::initializeSIFixControlFlowLiveIntervalsPass (PassRegistry &)
 
void llvm::initializeSIFixSGPRLiveRangesPass (PassRegistry &)
 

Variables

char & llvm::SIFoldOperandsID = SIFoldOperands::ID
 
char & llvm::SILowerI1CopiesID = SILowerI1Copies::ID
 
char & llvm::SILoadStoreOptimizerID = SILoadStoreOptimizer::ID
 
char & llvm::SIFixControlFlowLiveIntervalsID = SIFixControlFlowLiveIntervals::ID
 
char & llvm::SIFixSGPRLiveRangesID = SIFixSGPRLiveRanges::ID
 
Target llvm::TheAMDGPUTarget
 The target which suports all AMD GPUs. More...
 
Target llvm::TheGCNTarget
 The target for GCN GPUs. More...
 

Macro Definition Documentation

#define END_OF_TEXT_LABEL_NAME   "EndOfTextLabel"