18 #ifndef LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H
19 #define LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H
28 #define GET_INSTRINFO_HEADER
29 #include "MipsGenInstrInfo.inc"
34 virtual void anchor();
57 bool AllowModify)
const override;
110 int64_t Offset)
const = 0;
117 int64_t Offset)
const = 0;
132 unsigned Flag)
const;
135 virtual unsigned getAnalyzableBrOpc(
unsigned Opc)
const = 0;
137 void AnalyzeCondBr(
const MachineInstr *Inst,
unsigned Opc,
bool isZeroImm(const MachineOperand &op) const
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, DebugLoc DL) const override
virtual void loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const =0
virtual unsigned getOppositeBranchOpc(unsigned Opc) const =0
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
Insert nop instruction when hazard condition is found.
virtual const MipsRegisterInfo & getRegisterInfo() const =0
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Branch Analysis.
MachineMemOperand - A description of a memory reference used in the backend.
MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBrOpc)
virtual void storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const =0
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
const MipsSubtarget & Subtarget
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Flag
These should be considered private to the implementation of the MCInstrDesc class.
bundle_iterator< MachineInstr, instr_iterator > iterator
const MipsInstrInfo * createMips16InstrInfo(const MipsSubtarget &STI)
Create MipsInstrInfo objects.
bundle_iterator - MachineBasicBlock iterator that automatically skips over MIs that are inside bundle...
bool ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
ReverseBranchCondition - Return the inverse opcode of the specified Branch instruction.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
MachineOperand class - Representation of each machine instruction operand.
unsigned RemoveBranch(MachineBasicBlock &MBB) const override
Representation of each machine instruction.
const MipsInstrInfo * createMipsSEInstrInfo(const MipsSubtarget &STI)
unsigned GetInstSizeInBytes(const MachineInstr *MI) const
Return the number of bytes of code the specified instruction may be.
MachineMemOperand * GetMemOperand(MachineBasicBlock &MBB, int FI, unsigned Flag) const
static const MipsInstrInfo * create(MipsSubtarget &STI)
MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc, MachineBasicBlock::iterator I) const
Create an instruction which has the same operands and memory operands as MI but has a new opcode...
virtual void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const =0
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override