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LLVM
3.7.0
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#include <AArch64InstrInfo.h>
Definition at line 30 of file AArch64InstrInfo.h.
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Definition at line 32 of file AArch64InstrInfo.cpp.
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Definition at line 93 of file AArch64InstrInfo.cpp.
References llvm::MachineBasicBlock::begin(), llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), llvm::MachineBasicBlock::getLastNonDebugInstr(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), I, llvm::isCondBranchOpcode(), llvm::isIndirectBranchOpcode(), llvm::isUncondBranchOpcode(), and parseCondBranch().
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analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2, and the value it compares against in CmpValue.
Return true if the comparison instruction can be analyzed.
Definition at line 638 of file AArch64InstrInfo.cpp.
References llvm::AArch64_AM::decodeLogicalImmediate(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::getReg().
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Definition at line 602 of file AArch64InstrInfo.cpp.
References getMemOpBaseRegImmOfsWidth(), getRegisterInfo(), llvm::MachineInstr::hasOrderedMemoryRef(), llvm::MachineInstr::hasUnmodeledSideEffects(), and llvm::MachineInstr::mayLoadOrStore().
Referenced by mayAlias().
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Definition at line 361 of file AArch64InstrInfo.cpp.
References canFoldIntoCSel(), llvm::MachineBasicBlock::getParent(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), and llvm::ArrayRef< T >::size().
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Definition at line 1524 of file AArch64InstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), contains(), copyPhysRegTuple(), llvm::RegState::Define, llvm::getKillRegState(), llvm::TargetRegisterInfo::getMatchingSuperReg(), getRegisterInfo(), llvm::AArch64_AM::getShifterImm(), llvm::AArch64Subtarget::hasNEON(), llvm::AArch64Subtarget::hasZeroCycleRegMove(), llvm::AArch64Subtarget::hasZeroCycleZeroing(), llvm::RegState::Implicit, llvm_unreachable, llvm::AArch64_AM::LSL, llvm::AArch64SysReg::NZCV, and llvm::RegState::Undef.
| void AArch64InstrInfo::copyPhysRegTuple | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | I, | ||
| DebugLoc | DL, | ||
| unsigned | DestReg, | ||
| unsigned | SrcReg, | ||
| bool | KillSrc, | ||
| unsigned | Opcode, | ||
| llvm::ArrayRef< unsigned > | Indices | ||
| ) | const |
Definition at line 1498 of file AArch64InstrInfo.cpp.
References AddSubReg(), llvm::BuildMI(), llvm::RegState::Define, forwardCopyWillClobberTuple(), llvm::getKillRegState(), getRegisterInfo(), llvm::AArch64Subtarget::hasNEON(), and llvm::ArrayRef< T >::size().
Referenced by copyPhysReg().
| MachineInstr * AArch64InstrInfo::emitFrameIndexDebugValue | ( | MachineFunction & | MF, |
| int | FrameIx, | ||
| uint64_t | Offset, | ||
| const MDNode * | Var, | ||
| const MDNode * | Expr, | ||
| DebugLoc | DL | ||
| ) | const |
Definition at line 1467 of file AArch64InstrInfo.cpp.
References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMetadata(), llvm::BuildMI(), and llvm::TargetOpcode::DBG_VALUE.
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Definition at line 101 of file AArch64InstrInfo.h.
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Definition at line 973 of file AArch64InstrInfo.cpp.
References llvm::MachineInstrBuilder::addGlobalAddress(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::AArch64ISD::ADRP, llvm::BuildMI(), llvm::AArch64Subtarget::ClassifyGlobalReference(), llvm::MachineBasicBlock::erase(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getTarget(), llvm::RegState::Kill, llvm::CodeModel::Large, llvm::TargetOpcode::LOAD_STACK_GUARD, llvm::AArch64ISD::LOADgot, llvm::AArch64II::MO_G0, llvm::AArch64II::MO_G1, llvm::AArch64II::MO_G2, llvm::AArch64II::MO_G3, llvm::AArch64II::MO_GOT, llvm::AArch64II::MO_NC, llvm::AArch64II::MO_PAGE, llvm::AArch64II::MO_PAGEOFF, and llvm::SystemZISD::TM.
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When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could replace the original code sequence.
When getMachineCombinerPatterns() finds potential patterns, this function generates the instructions that could replace the original code sequence.
Definition at line 2663 of file AArch64InstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addOperand(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), genMadd(), genMaddR(), llvm::MCInstrInfo::get(), llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getImm(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::insert(), llvm::MachineOperand::isImm(), llvm::MachineCombinerPattern::MC_MULADDW_OP1, llvm::MachineCombinerPattern::MC_MULADDW_OP2, llvm::MachineCombinerPattern::MC_MULADDWI_OP1, llvm::MachineCombinerPattern::MC_MULADDX_OP1, llvm::MachineCombinerPattern::MC_MULADDX_OP2, llvm::MachineCombinerPattern::MC_MULADDXI_OP1, llvm::MachineCombinerPattern::MC_MULSUBW_OP1, llvm::MachineCombinerPattern::MC_MULSUBW_OP2, llvm::MachineCombinerPattern::MC_MULSUBWI_OP1, llvm::MachineCombinerPattern::MC_MULSUBX_OP1, llvm::MachineCombinerPattern::MC_MULSUBX_OP2, llvm::MachineCombinerPattern::MC_MULSUBXI_OP1, llvm::ISD::MUL, llvm::AArch64_AM::processLogicalImmediate(), and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().
| unsigned AArch64InstrInfo::GetInstSizeInBytes | ( | const MachineInstr * | MI | ) | const |
GetInstSize - Return the number of bytes of code the specified instruction may be.
This returns the maximum number of bytes.
Definition at line 38 of file AArch64InstrInfo.cpp.
References llvm::TargetOpcode::DBG_VALUE, llvm::TargetOpcode::EH_LABEL, llvm::MachineInstr::getDesc(), llvm::TargetMachine::getMCAsmInfo(), llvm::MCInstrDesc::getOpcode(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getSymbolName(), llvm::MachineFunction::getTarget(), llvm::TargetOpcode::IMPLICIT_DEF, llvm::ISD::INLINEASM, llvm::TargetOpcode::KILL, and llvm_unreachable.
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Return true when there is potentially a faster code sequence for an instruction chain ending in <Root>.
Return true when there is potentially a faster code sequence for an instruction chain ending in Root.
All potential patterns are listed in the <Patterns> array.
All potential patterns are listed in the Pattern vector. Pattern should be sorted in priority order since the pattern evaluator stops checking as soon as it finds a faster sequence.
Definition at line 2458 of file AArch64InstrInfo.cpp.
References canCombineWithMUL(), convertFlagSettingOpcode(), llvm::MachineInstr::findRegisterDefOperandIdx(), Found(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), isCombineInstrCandidate(), isCombineInstrSettingFlag(), llvm::MachineOperand::isReg(), llvm::MachineCombinerPattern::MC_MULADDW_OP1, llvm::MachineCombinerPattern::MC_MULADDW_OP2, llvm::MachineCombinerPattern::MC_MULADDWI_OP1, llvm::MachineCombinerPattern::MC_MULADDX_OP1, llvm::MachineCombinerPattern::MC_MULADDX_OP2, llvm::MachineCombinerPattern::MC_MULADDXI_OP1, llvm::MachineCombinerPattern::MC_MULSUBW_OP1, llvm::MachineCombinerPattern::MC_MULSUBW_OP2, llvm::MachineCombinerPattern::MC_MULSUBWI_OP1, llvm::MachineCombinerPattern::MC_MULSUBX_OP1, llvm::MachineCombinerPattern::MC_MULSUBX_OP2, llvm::MachineCombinerPattern::MC_MULSUBXI_OP1, llvm::AArch64SysReg::NZCV, and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().
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Definition at line 1303 of file AArch64InstrInfo.cpp.
References llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), getRegClass(), llvm::MachineOperand::isImm(), and llvm::MachineOperand::isReg().
| bool AArch64InstrInfo::getMemOpBaseRegImmOfsWidth | ( | MachineInstr * | LdSt, |
| unsigned & | BaseReg, | ||
| int & | Offset, | ||
| int & | Width, | ||
| const TargetRegisterInfo * | TRI | ||
| ) | const |
Definition at line 1329 of file AArch64InstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isImm(), and llvm::MachineOperand::isReg().
Referenced by areMemAccessesTriviallyDisjoint().
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Definition at line 2354 of file AArch64InstrInfo.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), and llvm::MCInst::setOpcode().
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getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
As such, whenever a client has an instance of instruction info, it should always be able to get register info as well (through this method).
Definition at line 46 of file AArch64InstrInfo.h.
Referenced by areMemAccessesTriviallyDisjoint(), copyPhysReg(), copyPhysRegTuple(), llvm::AArch64Subtarget::getRegisterInfo(), optimizeCompareInstr(), and optimizeCondBranch().
| bool AArch64InstrInfo::hasExtendedReg | ( | const MachineInstr * | MI | ) | const |
Returns true if there is an extendable register and that the extending value is non-zero.
Return true if this is this instruction has a non-zero immediate.
Definition at line 1069 of file AArch64InstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::isImm().
| bool AArch64InstrInfo::hasShiftedReg | ( | const MachineInstr * | MI | ) | const |
Returns true if there is a shiftable register and that the shift value is non-zero.
Return true if this is this instruction has a non-zero immediate.
Definition at line 1023 of file AArch64InstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::isImm().
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Definition at line 263 of file AArch64InstrInfo.cpp.
References llvm::MachineInstrBuilder::addMBB(), llvm::BuildMI(), and llvm::ArrayRef< T >::empty().
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Definition at line 402 of file AArch64InstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), canFoldIntoCSel(), llvm::MachineRegisterInfo::clearKillFlags(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::AArch64_AM::encodeLogicalImmediate(), llvm::AArch64CC::EQ, llvm::AArch64CC::getInvertedCondCode(), llvm::MachineBasicBlock::getParent(), getReg(), llvm::MachineFunction::getRegInfo(), llvm_unreachable, llvm::AArch64CC::NE, and llvm::ArrayRef< T >::size().
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Definition at line 538 of file AArch64InstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::isAsCheapAsAMove(), llvm::AArch64Subtarget::isCortexA53(), llvm::AArch64Subtarget::isCortexA57(), and llvm_unreachable.
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Definition at line 581 of file AArch64InstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::getReg().
| bool AArch64InstrInfo::isFPRCopy | ( | const MachineInstr * | MI | ) | const |
Does this instruction rename an FPR without modifying bits?
Definition at line 1151 of file AArch64InstrInfo.cpp.
References contains(), llvm::TargetOpcode::COPY, llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), and llvm::MachineOperand::isReg().
| bool AArch64InstrInfo::isGPRCopy | ( | const MachineInstr * | MI | ) | const |
Does this instruction rename a GPR without modifying bits?
Definition at line 1121 of file AArch64InstrInfo.cpp.
References contains(), llvm::TargetOpcode::COPY, llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::getReg().
| bool AArch64InstrInfo::isGPRZero | ( | const MachineInstr * | MI | ) | const |
Does this instruction set its full destination register to zero?
Definition at line 1097 of file AArch64InstrInfo.cpp.
References llvm::TargetOpcode::COPY, llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), and llvm::MachineOperand::isImm().
| bool AArch64InstrInfo::isLdStPairSuppressed | ( | const MachineInstr * | MI | ) | const |
Return true if pairing the given load or store is hinted to be unprofitable.
Check all MachineMemOperands for a hint to suppress pairing.
Definition at line 1279 of file AArch64InstrInfo.cpp.
References llvm::MachineInstr::memoperands(), llvm::MachineMemOperand::MOTargetNumBits, and llvm::MachineMemOperand::MOTargetStartBit.
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Definition at line 1172 of file AArch64InstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isFI(), and llvm::MachineOperand::isImm().
| bool AArch64InstrInfo::isScaledAddr | ( | const MachineInstr * | MI | ) | const |
Return true if this is load/store scales or extends its register offset.
This refers to scaling a dynamic index as opposed to scaled immediates. MI should be a memory op that allows scaled addressing.
Definition at line 1220 of file AArch64InstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::AArch64_AM::getMemDoShift(), llvm::AArch64_AM::getMemExtendType(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::AArch64_AM::UXTX.
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Definition at line 1195 of file AArch64InstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isFI(), and llvm::MachineOperand::isImm().
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Definition at line 1904 of file AArch64InstrInfo.cpp.
References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), Align(), llvm::BuildMI(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::DL, llvm::MachineBasicBlock::end(), llvm::getDefRegState(), llvm::PseudoSourceValue::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::TargetRegisterClass::getSize(), llvm::AArch64Subtarget::hasNEON(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::AArch64CC::MI, and llvm::MachineMemOperand::MOLoad.
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optimizeCompareInstr - Convert the instruction supplying the argument to the comparison into one that sets the zero bit in the flags register.
Definition at line 814 of file AArch64InstrInfo.cpp.
References llvm::MachineInstr::addRegisterDefined(), llvm::MachineOperand::clobbersPhysReg(), convertFlagSettingOpcode(), llvm::MachineInstr::definesRegister(), llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::AArch64CC::GE, llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), getRegisterInfo(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::AArch64CC::GT, I, llvm::MachineOperand::isDef(), llvm::MachineBasicBlock::isLiveIn(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isRegMask(), llvm::AArch64CC::LE, llvm::AArch64CC::LT, llvm::AArch64CC::MI, modifiesConditionCode(), llvm::AArch64SysReg::NZCV, llvm::MachineInstr::RemoveOperand(), llvm::MachineInstr::setDesc(), llvm::MachineBasicBlock::successors(), UpdateOperandRegClass(), llvm::MachineRegisterInfo::use_nodbg_empty(), llvm::AArch64CC::VC, and llvm::AArch64CC::VS.
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Replace csincr-branch sequence by simple conditional branch.
Examples: 1. csinc w9, wzr, wzr, <condition code>=""> tbnz w9, #0, 0x44 to b.<inverted condition="" code>="">
2. csinc w9, wzr, wzr, <condition code>=""> tbz w9, #0, 0x44 to b.<condition code>="">
| MI | Conditional Branch |
Definition at line 2871 of file AArch64InstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::BuildMI(), llvm::MachineInstr::eraseFromParent(), llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getImm(), llvm::AArch64CC::getInvertedCondCode(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), getRegisterInfo(), llvm::MachineRegisterInfo::getVRegDef(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm_unreachable, modifiesConditionCode(), and llvm::AArch64SysReg::NZCV.
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Definition at line 221 of file AArch64InstrInfo.cpp.
References llvm::MachineBasicBlock::begin(), llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getLastNonDebugInstr(), I, llvm::isCondBranchOpcode(), and llvm::isUncondBranchOpcode().
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Definition at line 180 of file AArch64InstrInfo.cpp.
References llvm::AArch64CC::getInvertedCondCode(), and llvm_unreachable.
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Detect opportunities for ldp/stp formation.
Only called for LdSt for which getMemOpBaseRegImmOfs returns true.
Definition at line 1428 of file AArch64InstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), and llvm::MachineInstr::getOperand().
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Definition at line 1446 of file AArch64InstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
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Definition at line 1806 of file AArch64InstrInfo.cpp.
References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), Align(), llvm::BuildMI(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::DL, llvm::MachineBasicBlock::end(), llvm::PseudoSourceValue::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::TargetRegisterClass::getSize(), llvm::AArch64Subtarget::hasNEON(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::AArch64CC::MI, and llvm::MachineMemOperand::MOStore.
| void AArch64InstrInfo::suppressLdStPair | ( | MachineInstr * | MI | ) | const |
Hint that pairing the given load or store is unprofitable.
Set a flag on the first MachineMemOperand to suppress pairing.
Definition at line 1292 of file AArch64InstrInfo.cpp.
References llvm::MachineInstr::memoperands_begin(), llvm::MachineInstr::memoperands_empty(), llvm::MachineMemOperand::MOTargetNumBits, and llvm::MachineMemOperand::MOTargetStartBit.
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useMachineCombiner - AArch64 supports MachineCombiner
useMachineCombiner - return true when a target supports MachineCombiner
Definition at line 2359 of file AArch64InstrInfo.cpp.
1.8.6