LLVM  3.7.0
Classes | Enumerations | Functions | Variables
llvm::AMDGPU Namespace Reference

Classes

struct  IsaVersion
 

Enumerations

enum  TargetIndex {
  TI_CONSTDATA_START, TI_SCRATCH_RSRC_DWORD0, TI_SCRATCH_RSRC_DWORD1, TI_SCRATCH_RSRC_DWORD2,
  TI_SCRATCH_RSRC_DWORD3
}
 
enum  Fixups {
  fixup_si_sopp_br = FirstTargetFixupKind, fixup_si_rodata, fixup_si_end_of_text, LastTargetFixupKind,
  NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
}
 
enum  OperandType { OPERAND_REG_IMM32 = llvm::MCOI::OPERAND_FIRST_TARGET, OPERAND_REG_INLINE_C }
 

Functions

static int getMCOpcode (uint16_t Opcode, unsigned Gen)
 
int16_t getNamedOperandIdx (uint16_t Opcode, uint16_t NamedIndex)
 
int getLDSNoRetOp (uint16_t Opcode)
 
int getVOPe64 (uint16_t Opcode)
 
int getVOPe32 (uint16_t Opcode)
 
int getCommuteRev (uint16_t Opcode)
 
int getCommuteOrig (uint16_t Opcode)
 
int getAddr64Inst (uint16_t Opcode)
 
int getAtomicRetOp (uint16_t Opcode)
 
int getAtomicNoRetOp (uint16_t Opcode)
 
IsaVersion getIsaVersion (const FeatureBitset &Features)
 
void initDefaultAMDKernelCodeT (amd_kernel_code_t &Header, const FeatureBitset &Features)
 

Variables

const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL
 
const uint64_t RSRC_TID_ENABLE = 1LL << 55
 

Enumeration Type Documentation

Enumerator
fixup_si_sopp_br 

16-bit PC relative fixup for SOPP branch instructions.

fixup_si_rodata 

fixup for global addresses with constant initializers

fixup_si_end_of_text 

fixup for offset from instruction to end of text section

LastTargetFixupKind 
NumTargetFixupKinds 

Definition at line 17 of file AMDGPUFixupKinds.h.

Enumerator
OPERAND_REG_IMM32 

Operand with register or 32-bit immediate.

OPERAND_REG_INLINE_C 

Operand with register or inline constant.

Definition at line 46 of file SIDefines.h.

Enumerator
TI_CONSTDATA_START 
TI_SCRATCH_RSRC_DWORD0 
TI_SCRATCH_RSRC_DWORD1 
TI_SCRATCH_RSRC_DWORD2 
TI_SCRATCH_RSRC_DWORD3 

Definition at line 79 of file AMDGPU.h.

Function Documentation

int llvm::AMDGPU::getAddr64Inst ( uint16_t  Opcode)
int llvm::AMDGPU::getAtomicNoRetOp ( uint16_t  Opcode)
int llvm::AMDGPU::getAtomicRetOp ( uint16_t  Opcode)
int llvm::AMDGPU::getCommuteOrig ( uint16_t  Opcode)
int llvm::AMDGPU::getCommuteRev ( uint16_t  Opcode)
IsaVersion llvm::AMDGPU::getIsaVersion ( const FeatureBitset &  Features)
int llvm::AMDGPU::getLDSNoRetOp ( uint16_t  Opcode)
static int llvm::AMDGPU::getMCOpcode ( uint16_t  Opcode,
unsigned  Gen 
)
static

Definition at line 334 of file AMDGPUInstrInfo.cpp.

Referenced by llvm::AMDGPUInstrInfo::pseudoToMCOpcode().

int16_t llvm::AMDGPU::getNamedOperandIdx ( uint16_t  Opcode,
uint16_t  NamedIndex 
)
int llvm::AMDGPU::getVOPe32 ( uint16_t  Opcode)
int llvm::AMDGPU::getVOPe64 ( uint16_t  Opcode)
void llvm::AMDGPU::initDefaultAMDKernelCodeT ( amd_kernel_code_t Header,
const FeatureBitset &  Features 
)

Variable Documentation

const uint64_t llvm::AMDGPU::RSRC_DATA_FORMAT = 0xf00000000000LL

Definition at line 369 of file SIInstrInfo.h.

Referenced by llvm::SIInstrInfo::getDefaultRsrcDataFormat().

const uint64_t llvm::AMDGPU::RSRC_TID_ENABLE = 1LL << 55

Definition at line 370 of file SIInstrInfo.h.

Referenced by llvm::SITargetLowering::buildScratchRSRC().