33 #define DEBUG_TYPE "instr-emitter"
61 unsigned &NumImpUses) {
69 NumImpUses = N - NumExpUses;
70 for (
unsigned I = N;
I > NumExpUses; --
I) {
71 if (isa<RegisterMaskSDNode>(Node->
getOperand(
I - 1)))
86 EmitCopyFromReg(
SDNode *Node,
unsigned ResNo,
bool IsClone,
bool IsCloned,
94 bool isNew = VRBaseMap.
insert(std::make_pair(Op, SrcReg)).second;
96 assert(isNew &&
"Node emitted out of order - early");
102 bool MatchReg =
true;
110 if (!IsClone && !IsCloned)
120 }
else if (DestReg != SrcReg)
131 if (
User->isMachineOpcode()) {
163 assert(UseRC->
hasType(VT) &&
"Incompatible phys register def and uses!");
177 VRBase).addReg(SrcReg);
183 bool isNew = VRBaseMap.
insert(std::make_pair(Op, VRBase)).second;
185 assert(isNew &&
"Node emitted out of order - early");
190 unsigned InstrEmitter::getDstOfOnlyCopyToRegUse(
SDNode *Node,
191 unsigned ResNo)
const {
206 void InstrEmitter::CreateVirtualRegisters(
SDNode *Node,
209 bool IsClone,
bool IsCloned,
212 "IMPLICIT_DEF should have been handled as a special case elsewhere!");
215 for (
unsigned i = 0; i < II.
getNumDefs(); ++i) {
243 if (!VRBase && !IsClone && !IsCloned)
263 assert(RC &&
"Isn't a register operand!");
270 if (i < NumResults) {
274 bool isNew = VRBaseMap.
insert(std::make_pair(Op, VRBase)).second;
276 assert(isNew &&
"Node emitted out of order - early");
283 unsigned InstrEmitter::getVR(
SDValue Op,
302 assert(I != VRBaseMap.
end() &&
"Node emitted out of order - late");
316 bool IsDebug,
bool IsClone,
bool IsCloned) {
319 "Chain and glue operands should occur at end of operand list!");
321 unsigned VReg = getVR(Op, VRBaseMap);
334 if (IIOpNum < II->getNumOperands())
354 !(IsClone || IsCloned);
378 bool IsDebug,
bool IsClone,
bool IsCloned) {
380 AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
381 IsDebug, IsClone, IsCloned);
396 TGA->getTargetFlags());
398 MIB.
addMBB(BBNode->getBasicBlock());
404 int Offset =
CP->getOffset();
405 unsigned Align =
CP->getAlignment();
418 if (
CP->isMachineConstantPoolEntry())
425 }
else if (
auto *SymNode = dyn_cast<MCSymbolSDNode>(Op)) {
426 MIB.
addSym(SymNode->getMCSymbol());
430 BA->getTargetFlags());
432 MIB.
addTargetIndex(TI->getIndex(), TI->getOffset(), TI->getTargetFlags());
436 "Chain and glue operands should occur at end of operand list!");
437 AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
438 IsDebug, IsClone, IsCloned);
442 unsigned InstrEmitter::ConstrainForSubReg(
unsigned VReg,
unsigned SubIdx,
459 assert(RC &&
"No legal register class for VT supports that SubIdx");
468 void InstrEmitter::EmitSubregNode(
SDNode *Node,
470 bool IsClone,
bool IsCloned) {
491 unsigned SubIdx = cast<ConstantSDNode>(Node->
getOperand(1))->getZExtValue();
495 unsigned VReg = getVR(Node->
getOperand(0), VRBaseMap);
497 unsigned SrcReg, DstReg, DefSubIdx;
500 SubIdx == DefSubIdx &&
515 VReg = ConstrainForSubReg(VReg, SubIdx,
532 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
550 assert(SRC &&
"No register class supports VT and SubIdx for INSERT_SUBREG");
565 AddOperand(MIB, N0, 0,
nullptr, VRBaseMap,
false,
568 AddOperand(MIB, N1, 0,
nullptr, VRBaseMap,
false,
571 MBB->
insert(InsertPos, MIB);
573 llvm_unreachable(
"Node is not insert_subreg, extract_subreg, or subreg_to_reg");
576 bool isNew = VRBaseMap.
insert(std::make_pair(Op, VRBase)).second;
578 assert(isNew &&
"Node emitted out of order - early");
586 InstrEmitter::EmitCopyToRegClassNode(
SDNode *Node,
588 unsigned VReg = getVR(Node->
getOperand(0), VRBaseMap);
591 unsigned DstRCIdx = cast<ConstantSDNode>(Node->
getOperand(1))->getZExtValue();
596 NewVReg).addReg(VReg);
599 bool isNew = VRBaseMap.
insert(std::make_pair(Op, NewVReg)).second;
601 assert(isNew &&
"Node emitted out of order - early");
606 void InstrEmitter::EmitRegSequence(
SDNode *Node,
608 bool IsClone,
bool IsCloned) {
609 unsigned DstRCIdx = cast<ConstantSDNode>(Node->
getOperand(0))->getZExtValue();
615 assert((NumOps & 1) == 1 &&
616 "REG_SEQUENCE must have an odd number of operands!");
617 for (
unsigned i = 1; i != NumOps; ++i) {
624 unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue();
625 unsigned SubReg = getVR(Node->
getOperand(i-1), VRBaseMap);
629 if (SRC && SRC != RC) {
635 AddOperand(MIB, Op, i+1, &II, VRBaseMap,
false,
639 MBB->
insert(InsertPos, MIB);
641 bool isNew = VRBaseMap.
insert(std::make_pair(Op, NewVReg)).second;
643 assert(isNew &&
"Node emitted out of order - early");
655 assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(DL) &&
656 "Expected inlined-at fields to agree");
679 if (I==VRBaseMap.
end())
686 if (
const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
687 if (CI->getBitWidth() > 64)
690 MIB.
addImm(CI->getSExtValue());
691 }
else if (
const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
707 assert(Offset == 0 &&
"direct value cannot have an offset");
721 EmitMachineNode(
SDNode *Node,
bool IsClone,
bool IsCloned,
729 EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned);
735 EmitCopyToRegClassNode(Node, VRBaseMap);
741 EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned);
762 NumDefs = NumResults;
767 unsigned NumImpUses = 0;
768 unsigned NodeOperands =
770 bool HasPhysRegOuts = NumResults > NumDefs && II.
getImplicitDefs()!=
nullptr;
772 unsigned NumMIOperands = NodeOperands + NumResults;
775 "Too few operands for a variadic node!");
780 "#operands for dag node doesn't match .td file!");
789 CreateVirtualRegisters(Node, MIB, II, IsClone, IsCloned, VRBaseMap);
793 bool HasOptPRefs = NumDefs > NumResults;
794 assert((!HasOptPRefs || !HasPhysRegOuts) &&
795 "Unable to cope with optional defs and phys regs defs!");
796 unsigned NumSkip = HasOptPRefs ? NumDefs - NumResults : 0;
797 for (
unsigned i = NumSkip; i != NodeOperands; ++i)
798 AddOperand(MIB, Node->
getOperand(i), i-NumSkip+NumDefs, &II,
799 VRBaseMap,
false, IsClone, IsCloned);
803 for (
unsigned i = 0; ScratchRegs[i]; ++i)
808 MIB.setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(),
809 cast<MachineSDNode>(Node)->memoperands_end());
814 MBB->
insert(InsertPos, MIB);
834 if (HasPhysRegOuts) {
835 for (
unsigned i = NumDefs; i < NumResults; ++i) {
836 unsigned Reg = II.getImplicitDefs()[i - NumDefs];
841 EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
861 for (
unsigned i = 0, e =
F->getNumOperands(); i != e; ++i)
863 unsigned Reg = R->
getReg();
871 if (!UsedRegs.
empty() || II.getImplicitDefs())
872 MIB->setPhysRegsDeadExcept(UsedRegs, *TRI);
875 if (II.hasPostISelHook())
882 EmitSpecialNode(
SDNode *Node,
bool IsClone,
bool IsCloned,
889 llvm_unreachable(
"This target-independent node should have been selected!");
891 llvm_unreachable(
"EntryToken should have been excluded from the schedule!");
901 SrcReg = getVR(SrcVal, VRBaseMap);
904 if (SrcReg == DestReg)
908 DestReg).addReg(SrcReg);
913 EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap);
917 MCSymbol *S = cast<EHLabelSDNode>(Node)->getLabel();
945 const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol();
964 cast<ConstantSDNode>(Node->
getOperand(i))->getZExtValue();
974 for (
unsigned j = 0; j != NumVals; ++j, ++i) {
985 for (
unsigned j = 0; j != NumVals; ++j, ++i) {
997 for (
unsigned j = 0; j != NumVals; ++j, ++i)
998 AddOperand(MIB, Node->
getOperand(i), 0,
nullptr, VRBaseMap,
999 false, IsClone, IsCloned);
1003 unsigned DefGroup = 0;
1005 unsigned DefIdx = GroupIdx[DefGroup] + 1;
1006 unsigned UseIdx = GroupIdx.
back() + 1;
1007 for (
unsigned j = 0; j != NumVals; ++j)
1020 for (
unsigned Reg : ECRegs) {
1023 assert(MO &&
"No def operand for clobbered register?");
1030 const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD();
1034 MBB->
insert(InsertPos, MIB);
1044 : MF(mbb->
getParent()), MRI(&MF->getRegInfo()),
1045 TII(MF->getSubtarget().getInstrInfo()),
1046 TRI(MF->getSubtarget().getRegisterInfo()),
1047 TLI(MF->getSubtarget().getTargetLowering()), MBB(mbb),
1048 InsertPos(insertpos) {}
bool hasType(MVT vt) const
hasType - return true if this TargetRegisterClass has the ValueType vt.
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
void push_back(const T &Elt)
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
unsigned getNumImplicitUses() const
Return the number of implicit uses this instruction has.
const DebugLoc & getDebugLoc() const
const uint16_t * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
InstrEmitter(MachineBasicBlock *mbb, MachineBasicBlock::iterator insertpos)
InstrEmitter - Construct an InstrEmitter and set it to start inserting at the given position in the g...
void dump() const
Dump this node, for debugging.
MachineOperand * findRegisterDefOperand(unsigned Reg, bool isDead=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
bool hasOneUse() const
Return true if there is exactly one use of this node.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
unsigned getNumOperands() const
bool hasSubClassEq(const TargetRegisterClass *RC) const
hasSubClassEq - Returns true if RC is a sub-class of or equal to this class.
unsigned getPrefTypeAlignment(Type *Ty) const
Returns the preferred stack/global alignment for the specified type.
Describe properties that are true of each instruction in the target description file.
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
A Stackmap instruction captures the location of live variables at its position in the instruction str...
const uint16_t * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction...
Completely target-dependent object reference.
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
static unsigned CountResults(SDNode *Node)
CountResults - The results of target nodes have register or immediate operands first, then an optional chain, and optional flag operands (which do not go into the machine instrs.)
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
unsigned getNumOperands() const
Return the number of values used by this operation.
unsigned getNumOperands() const
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const
getCommonSubClass - find the largest common subclass of A and B.
const SDValue & getOperand(unsigned Num) const
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
virtual void AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag...
EntryToken - This is the marker used to indicate the start of a region.
static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx)
isUseOperandTiedToDef - Return true if the flag of the inline asm operand indicates it is an use oper...
unsigned getResNo() const
get the index which selects a specific result in the SDNode
COPY - Target-independent register copy.
const unsigned MinRCSize
MinRCSize - Smallest register class we allow when constraining virtual registers. ...
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
const HexagonInstrInfo * TII
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
const TargetRegisterClass * getRegClass(unsigned i) const
getRegClass - Returns the register class associated with the enumeration value.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
CopyToReg - This node has three operands: a chain, a register number to set to this value...
const TargetRegisterClass * getRegClass(unsigned Reg) const
getRegClass - Return the register class of the specified virtual register.
Reg
All possible values of the reg field in the ModR/M byte.
unsigned getMachineOpcode() const
MDNode * getExpression() const
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
INLINEASM - Represents an inline asm block.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
void setIsEarlyClobber(bool Val=true)
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
DbgValueKind getKind() const
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
getMatchingSuperRegClass - Return a subclass of the specified register class A so that each register ...
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
virtual const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const
Returns a 0 terminated array of registers that can be safely used as scratch registers.
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
unsigned getKillRegState(bool B)
unsigned getDebugRegState(bool B)
This corresponds to the llvm.lifetime.
DBG_VALUE - a mapping of the llvm.dbg.value intrinsic.
unsigned getDefRegState(bool B)
SDNode * getNode() const
get the SDNode which holds the desired result
IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
bundle_iterator< MachineInstr, instr_iterator > iterator
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
bool erase(const KeyT &Val)
Patchable call instruction - this instruction represents a call to a constant address, followed by a series of NOPs.
MVT - Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
bool isOptionalDef() const
Set if this operand is a optional def.
const MachineOperand & getOperand(unsigned i) const
ConstantFP - Floating Point Values [float, double].
INSERT_SUBREG - This instruction takes three operands: a register that has subregisters, a register providing an insert value, and a subregister index.
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag...
const MachineInstrBuilder & addTargetIndex(unsigned Idx, int64_t Offset=0, unsigned char TargetFlags=0) const
unsigned getFrameIx() const
static unsigned getKind(unsigned Flags)
Value * getOperand(unsigned i) const
use_iterator use_begin() const
Provide iteration support to walk over all uses of an SDNode.
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
void append(in_iter in_start, in_iter in_end)
Add the specified range to the end of the SmallVector.
const TargetRegisterClass * getAllocatableClass(const TargetRegisterClass *RC) const
getAllocatableClass - Return the maximal subclass of the given register class that is alloctable...
uint64_t getConstantOperandVal(unsigned Num) const
Helper method returns the integer value of a ConstantSDNode operand.
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
REG_SEQUENCE - This variadic instruction is used to form a register that represents a consecutive seq...
bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
TokenFactor - This node takes multiple tokens as input and produces a single token result...
EXTRACT_SUBREG - This instruction takes two operands: a register that has subregisters, and a subregister index.
This is the shared class of boolean and integer constants.
uint64_t getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
const MachineInstrBuilder & addJumpTableIndex(unsigned Idx, unsigned char TargetFlags=0) const
MachineOperand class - Representation of each machine instruction operand.
SDNode * getSDNode() const
const MachineInstrBuilder & addCImm(const ConstantInt *Val) const
SDNode * getGluedUser() const
If this node has a glue value with a user, return the user (there is at most one).
bool isMachineOpcode() const
Represents one node in the SelectionDAG.
const MachineInstrBuilder & addFrameIndex(int Idx) const
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
iterator_range< use_iterator > uses()
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
getMinimalPhysRegClass - Returns the Register Class of a physical register of the given type...
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
Return the register class that should be used for the specified value type.
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned char TargetFlags=0) const
int getCopyCost() const
getCopyCost - Return the cost of copying a value between two registers in this class.
Representation of each machine instruction.
static bool isPhysicalRegister(unsigned Reg)
isPhysicalRegister - Return true if the specified register number is in the physical register namespa...
bool hasAnyUseOfValue(unsigned Value) const
Return true if there are any use of the indicated value.
static unsigned countOperands(SDNode *Node, unsigned NumExpUses, unsigned &NumImpUses)
countOperands - The inputs to target nodes have any actual inputs first, followed by an optional chai...
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned char TargetFlags=0) const
COPY_TO_REGCLASS - This instruction is a placeholder for a plain register-to-register copy into a spe...
const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned char TargetFlags=0) const
unsigned getImplRegState(bool B)
void clearKillFlags(unsigned Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
iterator find(const KeyT &Val)
DebugLoc getDebugLoc() const
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
EVT getValueType() const
Return the ValueType of the referenced return value.
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
const DebugLoc & getDebugLoc() const
Return the source location info.
const MachineInstrBuilder & addFPImm(const ConstantFP *Val) const
const Value * getConst() const
MachineInstr * EmitDbgValue(SDDbgValue *SD, DenseMap< SDValue, unsigned > &VRBaseMap)
EmitDbgValue - Generate machine instruction for a dbg_value node.
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
getSubClassWithSubReg - Returns the largest legal sub-class of RC that supports the sub-register inde...
uint64_t getOffset() const
LLVM Value Representation.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
const MCOperandInfo * OpInfo
static const Function * getParent(const Value *V)
unsigned getResNo() const
void setRegClass(unsigned Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
const TargetRegisterClass * getRegClass(const MCInstrDesc &TID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum...
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except that the first operand is an imme...
MDNode * getVariable() const
const MachineInstrBuilder & addBlockAddress(const BlockAddress *BA, int64_t Offset=0, unsigned char TargetFlags=0) const
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
MVT getSimpleValueType(unsigned ResNo) const
Return the type of a specified result as a simple type.
SDDbgValue - Holds the information from a dbg_value node through SDISel.
virtual bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const
Return true if the instruction is a "coalescable" extension instruction.
unsigned getConstantPoolIndex(const Constant *C, unsigned Alignment)
getConstantPoolIndex - Create a new entry in the constant pool or return an existing one...
This file describes how to lower LLVM code to machine code.
unsigned getMachineOpcode() const
This may only be called if isMachineOpcode returns true.
uint64_t getZExtValue() const
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.