LLVM  3.7.0
Macros | Functions
AArch64InstrInfo.cpp File Reference
#include "AArch64InstrInfo.h"
#include "AArch64MachineCombinerPattern.h"
#include "AArch64Subtarget.h"
#include "MCTargetDesc/AArch64AddressingModes.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
#include "llvm/MC/MCInst.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/TargetRegistry.h"
#include "AArch64GenInstrInfo.inc"
Include dependency graph for AArch64InstrInfo.cpp:

Go to the source code of this file.

Macros

#define GET_INSTRINFO_CTOR_DTOR
 

Functions

static void parseCondBranch (MachineInstr *LastInst, MachineBasicBlock *&Target, SmallVectorImpl< MachineOperand > &Cond)
 
static unsigned removeCopies (const MachineRegisterInfo &MRI, unsigned VReg)
 
static unsigned canFoldIntoCSel (const MachineRegisterInfo &MRI, unsigned VReg, unsigned *NewVReg=nullptr)
 
static bool UpdateOperandRegClass (MachineInstr *Instr)
 
static unsigned convertFlagSettingOpcode (const MachineInstr *MI)
 Return the opcode that does not set flags when possible - otherwise return the original opcode. More...
 
static bool modifiesConditionCode (MachineInstr *From, MachineInstr *To, const bool CheckOnlyCCWrites, const TargetRegisterInfo *TRI)
 True when condition code could be modified on the instruction trace starting at from and ending at to. More...
 
static const MachineInstrBuilderAddSubReg (const MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI)
 
static bool forwardCopyWillClobberTuple (unsigned DestReg, unsigned SrcReg, unsigned NumRegs)
 
static bool isCombineInstrSettingFlag (unsigned Opc)
 
static bool isCombineInstrCandidate32 (unsigned Opc)
 
static bool isCombineInstrCandidate64 (unsigned Opc)
 
static bool isCombineInstrCandidate (unsigned Opc)
 
static bool canCombineWithMUL (MachineBasicBlock &MBB, MachineOperand &MO, unsigned MulOpc, unsigned ZeroReg)
 
static MachineInstrgenMadd (MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineInstr &Root, SmallVectorImpl< MachineInstr * > &InsInstrs, unsigned IdxMulOpd, unsigned MaddOpc, const TargetRegisterClass *RC)
 genMadd - Generate madd instruction and combine mul and add. More...
 
static MachineInstrgenMaddR (MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineInstr &Root, SmallVectorImpl< MachineInstr * > &InsInstrs, unsigned IdxMulOpd, unsigned MaddOpc, unsigned VR, const TargetRegisterClass *RC)
 genMaddR - Generate madd instruction and combine mul and add using an extra virtual register Example - an ADD intermediate needs to be stored in a register: MUL I=A,B,0 ADD R,I,Imm ==> ORR V, ZR, Imm ==> MADD R,A,B,V More...
 

Macro Definition Documentation

#define GET_INSTRINFO_CTOR_DTOR

Definition at line 29 of file AArch64InstrInfo.cpp.

Function Documentation

static const MachineInstrBuilder& AddSubReg ( const MachineInstrBuilder MIB,
unsigned  Reg,
unsigned  SubIdx,
unsigned  State,
const TargetRegisterInfo TRI 
)
static
static bool canCombineWithMUL ( MachineBasicBlock MBB,
MachineOperand MO,
unsigned  MulOpc,
unsigned  ZeroReg 
)
static
static unsigned canFoldIntoCSel ( const MachineRegisterInfo MRI,
unsigned  VReg,
unsigned NewVReg = nullptr 
)
static
static unsigned convertFlagSettingOpcode ( const MachineInstr MI)
static

Return the opcode that does not set flags when possible - otherwise return the original opcode.

The caller is responsible to do the actual substitution and legality checking.

Definition at line 734 of file AArch64InstrInfo.cpp.

References llvm::MachineInstr::definesRegister(), and llvm::MachineInstr::getOpcode().

Referenced by llvm::AArch64InstrInfo::getMachineCombinerPatterns(), and llvm::AArch64InstrInfo::optimizeCompareInstr().

static bool forwardCopyWillClobberTuple ( unsigned  DestReg,
unsigned  SrcReg,
unsigned  NumRegs 
)
static

Definition at line 1491 of file AArch64InstrInfo.cpp.

Referenced by llvm::AArch64InstrInfo::copyPhysRegTuple().

static MachineInstr* genMadd ( MachineFunction MF,
MachineRegisterInfo MRI,
const TargetInstrInfo TII,
MachineInstr Root,
SmallVectorImpl< MachineInstr * > &  InsInstrs,
unsigned  IdxMulOpd,
unsigned  MaddOpc,
const TargetRegisterClass RC 
)
static

genMadd - Generate madd instruction and combine mul and add.

Example: MUL I=A,B,0 ADD R,I,C ==> MADD R,A,B,C

Parameters
Rootis the ADD instruction
[out]InsInstrsis a vector of machine instructions and will contain the generated madd instruction
IdxMulOpdis index of operand in Root that is the result of the MUL. In the example above IdxMulOpd is 1.
MaddOpcthe opcode fo the madd instruction

Definition at line 2576 of file AArch64InstrInfo.cpp.

References llvm::BuildMI(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::MCInstrInfo::get(), llvm::MachineInstr::getDebugLoc(), llvm::getKillRegState(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::MachineOperand::isKill(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::ISD::MUL, and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().

Referenced by llvm::AArch64InstrInfo::genAlternativeCodeSequence().

static MachineInstr* genMaddR ( MachineFunction MF,
MachineRegisterInfo MRI,
const TargetInstrInfo TII,
MachineInstr Root,
SmallVectorImpl< MachineInstr * > &  InsInstrs,
unsigned  IdxMulOpd,
unsigned  MaddOpc,
unsigned  VR,
const TargetRegisterClass RC 
)
static

genMaddR - Generate madd instruction and combine mul and add using an extra virtual register Example - an ADD intermediate needs to be stored in a register: MUL I=A,B,0 ADD R,I,Imm ==> ORR V, ZR, Imm ==> MADD R,A,B,V

Parameters
Rootis the ADD instruction
[out]InsInstrsis a vector of machine instructions and will contain the generated madd instruction
IdxMulOpdis index of operand in Root that is the result of the MUL. In the example above IdxMulOpd is 1.
MaddOpcthe opcode fo the madd instruction
VRis a virtual register that holds the value of an ADD operand (V in the example above).

Definition at line 2627 of file AArch64InstrInfo.cpp.

References llvm::BuildMI(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::MCInstrInfo::get(), llvm::MachineInstr::getDebugLoc(), llvm::getKillRegState(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::MachineOperand::isKill(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::ISD::MUL, and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().

Referenced by llvm::AArch64InstrInfo::genAlternativeCodeSequence().

static bool isCombineInstrCandidate ( unsigned  Opc)
static
static bool isCombineInstrCandidate32 ( unsigned  Opc)
static

Definition at line 2384 of file AArch64InstrInfo.cpp.

Referenced by isCombineInstrCandidate().

static bool isCombineInstrCandidate64 ( unsigned  Opc)
static

Definition at line 2403 of file AArch64InstrInfo.cpp.

Referenced by isCombineInstrCandidate().

static bool isCombineInstrSettingFlag ( unsigned  Opc)
static
static bool modifiesConditionCode ( MachineInstr From,
MachineInstr To,
const bool  CheckOnlyCCWrites,
const TargetRegisterInfo TRI 
)
static
static void parseCondBranch ( MachineInstr LastInst,
MachineBasicBlock *&  Target,
SmallVectorImpl< MachineOperand > &  Cond 
)
static
static unsigned removeCopies ( const MachineRegisterInfo MRI,
unsigned  VReg 
)
static
static bool UpdateOperandRegClass ( MachineInstr Instr)
static