26 #define DEBUG_TYPE "sparc-disassembler"
37 virtual ~SparcDisassembler() {}
53 return new SparcDisassembler(STI, Ctx);
68 SP::G0, SP::G1, SP::G2, SP::G3,
69 SP::G4, SP::G5, SP::G6, SP::G7,
70 SP::O0, SP::O1, SP::O2, SP::O3,
71 SP::O4, SP::O5, SP::O6, SP::O7,
72 SP::L0, SP::L1, SP::L2, SP::L3,
73 SP::L4, SP::L5, SP::L6, SP::L7,
74 SP::I0, SP::I1, SP::I2, SP::I3,
75 SP::I4, SP::I5, SP::I6, SP::I7 };
78 SP::F0, SP::F1, SP::F2, SP::F3,
79 SP::F4, SP::F5, SP::F6, SP::F7,
80 SP::F8, SP::F9, SP::F10, SP::F11,
81 SP::F12, SP::F13, SP::F14, SP::F15,
82 SP::F16, SP::F17, SP::F18, SP::F19,
83 SP::F20, SP::F21, SP::F22, SP::F23,
84 SP::F24, SP::F25, SP::F26, SP::F27,
85 SP::F28, SP::F29, SP::F30, SP::F31 };
88 SP::D0, SP::D16, SP::D1, SP::D17,
89 SP::D2, SP::D18, SP::D3, SP::D19,
90 SP::D4, SP::D20, SP::D5, SP::D21,
91 SP::D6, SP::D22, SP::D7, SP::D23,
92 SP::D8, SP::D24, SP::D9, SP::D25,
93 SP::D10, SP::D26, SP::D11, SP::D27,
94 SP::D12, SP::D28, SP::D13, SP::D29,
95 SP::D14, SP::D30, SP::D15, SP::D31 };
98 SP::Q0, SP::Q8, ~0U, ~0U,
99 SP::Q1, SP::Q9, ~0U, ~0U,
100 SP::Q2, SP::Q10, ~0U, ~0U,
101 SP::Q3, SP::Q11, ~0U, ~0U,
102 SP::Q4, SP::Q12, ~0U, ~0U,
103 SP::Q5, SP::Q13, ~0U, ~0U,
104 SP::Q6, SP::Q14, ~0U, ~0U,
105 SP::Q7, SP::Q15, ~0U, ~0U } ;
108 SP::FCC0, SP::FCC1, SP::FCC2, SP::FCC3 };
111 SP::Y, SP::ASR1, SP::ASR2, SP::ASR3,
112 SP::ASR4, SP::ASR5, SP::ASR6, SP::ASR7,
113 SP::ASR8, SP::ASR9, SP::ASR10, SP::ASR11,
114 SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15,
115 SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19,
116 SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23,
117 SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27,
118 SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31};
123 const void *Decoder) {
134 const void *Decoder) {
146 const void *Decoder) {
158 const void *Decoder) {
170 const void *Decoder) {
183 const void *Decoder) {
192 const void *Decoder) {
201 const void *Decoder);
203 const void *Decoder);
205 const void *Decoder);
207 const void *Decoder);
209 uint64_t
Address,
const void *Decoder);
211 uint64_t
Address,
const void *Decoder);
213 uint64_t
Address,
const void *Decoder);
215 uint64_t
Address,
const void *Decoder);
217 uint64_t
Address,
const void *Decoder);
219 uint64_t
Address,
const void *Decoder);
221 const void *Decoder);
223 const void *Decoder);
225 const void *Decoder);
227 #include "SparcGenDisassemblerTables.inc"
231 uint64_t &Size, uint32_t &Insn,
232 bool IsLittleEndian) {
234 if (Bytes.
size() < 4) {
239 Insn = IsLittleEndian
240 ? (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
242 : (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) |
254 bool isLittleEndian = getContext().getAsmInfo()->isLittleEndian();
274 const void *Decoder);
279 unsigned rd = fieldFromInstruction(insn, 25, 5);
280 unsigned rs1 = fieldFromInstruction(insn, 14, 5);
281 bool isImm = fieldFromInstruction(insn, 13, 1);
282 bool hasAsi = fieldFromInstruction(insn, 23, 1);
283 unsigned asi = fieldFromInstruction(insn, 5, 8);
287 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
289 rs2 = fieldFromInstruction(insn, 0, 5);
293 status = DecodeRD(MI, rd, Address, Decoder);
316 status = DecodeRD(MI, rd, Address, Decoder);
324 const void *Decoder) {
325 return DecodeMem(Inst, insn, Address, Decoder,
true,
330 const void *Decoder) {
331 return DecodeMem(Inst, insn, Address, Decoder,
true,
336 const void *Decoder) {
337 return DecodeMem(Inst, insn, Address, Decoder,
true,
342 const void *Decoder) {
343 return DecodeMem(Inst, insn, Address, Decoder,
true,
348 uint64_t Address,
const void *Decoder) {
349 return DecodeMem(Inst, insn, Address, Decoder,
false,
354 const void *Decoder) {
355 return DecodeMem(Inst, insn, Address, Decoder,
false,
360 uint64_t Address,
const void *Decoder) {
361 return DecodeMem(Inst, insn, Address, Decoder,
false,
366 uint64_t Address,
const void *Decoder) {
367 return DecodeMem(Inst, insn, Address, Decoder,
false,
372 uint64_t Address, uint64_t Offset,
374 const void *Decoder) {
381 uint64_t Address,
const void *Decoder) {
382 unsigned tgt = fieldFromInstruction(insn, 0, 30);
391 uint64_t Address,
const void *Decoder) {
392 unsigned tgt = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
398 const void *Decoder) {
400 unsigned rd = fieldFromInstruction(insn, 25, 5);
401 unsigned rs1 = fieldFromInstruction(insn, 14, 5);
402 unsigned isImm = fieldFromInstruction(insn, 13, 1);
406 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
408 rs2 = fieldFromInstruction(insn, 0, 5);
432 const void *Decoder) {
434 unsigned rs1 = fieldFromInstruction(insn, 14, 5);
435 unsigned isImm = fieldFromInstruction(insn, 13, 1);
439 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
441 rs2 = fieldFromInstruction(insn, 0, 5);
460 const void *Decoder) {
462 unsigned rd = fieldFromInstruction(insn, 25, 5);
463 unsigned rs1 = fieldFromInstruction(insn, 14, 5);
464 unsigned isImm = fieldFromInstruction(insn, 13, 1);
465 bool hasAsi = fieldFromInstruction(insn, 23, 1);
466 unsigned asi = fieldFromInstruction(insn, 5, 8);
470 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
472 rs2 = fieldFromInstruction(insn, 0, 5);
static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMem(MCInst &MI, unsigned insn, uint64_t Address, const void *Decoder, bool isLoad, DecodeFunc DecodeRD)
DecodeStatus
Ternary decode status.
static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder)
Superclass for all disassemblers.
static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder)
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
DecodeStatus(* DecodeFunc)(MCInst &MI, unsigned insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeDFPRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder)
static MCOperand createReg(unsigned Reg)
static DecodeStatus DecodeFPRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
MCDisassembler::DecodeStatus DecodeStatus
Reg
All possible values of the reg field in the ModR/M byte.
static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder)
Context object for machine code objects.
int decodeInstruction(InternalInstruction *insn, byteReader_t reader, const void *readerArg, dlog_t logger, void *loggerArg, const void *miiArg, uint64_t startLoc, DisassemblerMode mode)
Decode one instruction and store the decoding results in a buffer provided by the consumer...
void LLVMInitializeSparcDisassembler()
static DecodeStatus readInstruction32(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsLittleEndian)
Read four bytes from the ArrayRef and return 32 bit word.
size_t size() const
size - Get the array size.
Instances of this class represent a single low-level machine instruction.
static DecodeStatus DecodeASRRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeQFPRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSIMM13(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder)
static const unsigned FCCRegDecoderTable[]
static DecodeStatus DecodeCall(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder)
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t InstSize) const
static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address, const void *Decoder)
static const unsigned IntRegDecoderTable[]
static const unsigned FPRegDecoderTable[]
static DecodeStatus DecodeSWAP(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeI64RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static const unsigned ASRRegDecoderTable[]
static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder)
static const unsigned DFPRegDecoderTable[]
Target - Wrapper for Target specific information.
static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeJMPL(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder)
static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch, uint64_t Address, uint64_t Offset, uint64_t Width, MCInst &MI, const void *Decoder)
static const unsigned QFPRegDecoderTable[]
MCSubtargetInfo - Generic base class for all target subtargets.
static DecodeStatus DecodeFCCRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static bool isBranch(unsigned Opcode)
LLVM Value Representation.
static MCDisassembler * createSparcDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
This class implements an extremely fast bulk output stream that can only output to a stream...
void addOperand(const MCOperand &Op)
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml","ocaml 3.10-compatible collector")
std::error_code status(const Twine &path, file_status &result)
Get file status as if by POSIX stat().
static MCOperand createImm(int64_t Val)