LLVM  3.7.0
ARMBaseInstrInfo.h
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1 //===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
15 #define LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
16 
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/Support/CodeGen.h"
23 
24 #define GET_INSTRINFO_HEADER
25 #include "ARMGenInstrInfo.inc"
26 
27 namespace llvm {
28  class ARMSubtarget;
29  class ARMBaseRegisterInfo;
30 
32  const ARMSubtarget &Subtarget;
33 
34 protected:
35  // Can be only subclassed.
36  explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
37 
39  unsigned LoadImmOpc, unsigned LoadOpc,
40  Reloc::Model RM) const;
41 
42  /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
43  /// and \p DefIdx.
44  /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
45  /// the list is modeled as <Reg:SubReg, SubIdx>.
46  /// E.g., REG_SEQUENCE vreg1:sub1, sub0, vreg2, sub1 would produce
47  /// two elements:
48  /// - vreg1:sub1, sub0
49  /// - vreg2<:0>, sub1
50  ///
51  /// \returns true if it is possible to build such an input sequence
52  /// with the pair \p MI, \p DefIdx. False otherwise.
53  ///
54  /// \pre MI.isRegSequenceLike().
56  const MachineInstr &MI, unsigned DefIdx,
57  SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const override;
58 
59  /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
60  /// and \p DefIdx.
61  /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
62  /// E.g., EXTRACT_SUBREG vreg1:sub1, sub0, sub1 would produce:
63  /// - vreg1:sub1, sub0
64  ///
65  /// \returns true if it is possible to build such an input sequence
66  /// with the pair \p MI, \p DefIdx. False otherwise.
67  ///
68  /// \pre MI.isExtractSubregLike().
69  bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
70  RegSubRegPairAndIdx &InputReg) const override;
71 
72  /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
73  /// and \p DefIdx.
74  /// \p [out] BaseReg and \p [out] InsertedReg contain
75  /// the equivalent inputs of INSERT_SUBREG.
76  /// E.g., INSERT_SUBREG vreg0:sub0, vreg1:sub1, sub3 would produce:
77  /// - BaseReg: vreg0:sub0
78  /// - InsertedReg: vreg1:sub1, sub3
79  ///
80  /// \returns true if it is possible to build such an input sequence
81  /// with the pair \p MI, \p DefIdx. False otherwise.
82  ///
83  /// \pre MI.isInsertSubregLike().
84  bool
85  getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
86  RegSubRegPair &BaseReg,
87  RegSubRegPairAndIdx &InsertedReg) const override;
88 
89 public:
90  // Return whether the target has an explicit NOP encoding.
91  bool hasNOP() const;
92 
93  // Return the non-pre/post incrementing version of 'Opc'. Return 0
94  // if there is not such an opcode.
95  virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
96 
99  LiveVariables *LV) const override;
100 
101  virtual const ARMBaseRegisterInfo &getRegisterInfo() const = 0;
102  const ARMSubtarget &getSubtarget() const { return Subtarget; }
103 
106  const ScheduleDAG *DAG) const override;
107 
110  const ScheduleDAG *DAG) const override;
111 
112  // Branch analysis.
114  MachineBasicBlock *&FBB,
116  bool AllowModify = false) const override;
117  unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
120  DebugLoc DL) const override;
121 
122  bool
124 
125  // Predication support.
126  bool isPredicated(const MachineInstr *MI) const override;
127 
129  int PIdx = MI->findFirstPredOperandIdx();
130  return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
131  : ARMCC::AL;
132  }
133 
135  ArrayRef<MachineOperand> Pred) const override;
136 
138  ArrayRef<MachineOperand> Pred2) const override;
139 
141  std::vector<MachineOperand> &Pred) const override;
142 
143  bool isPredicable(MachineInstr *MI) const override;
144 
145  /// GetInstSize - Returns the size of the specified MachineInstr.
146  ///
147  virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
148 
149  unsigned isLoadFromStackSlot(const MachineInstr *MI,
150  int &FrameIndex) const override;
151  unsigned isStoreToStackSlot(const MachineInstr *MI,
152  int &FrameIndex) const override;
153  unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
154  int &FrameIndex) const override;
155  unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
156  int &FrameIndex) const override;
157 
159  unsigned SrcReg, bool KillSrc,
160  const ARMSubtarget &Subtarget) const;
162  unsigned DestReg, bool KillSrc,
163  const ARMSubtarget &Subtarget) const;
164 
166  DebugLoc DL, unsigned DestReg, unsigned SrcReg,
167  bool KillSrc) const override;
168 
171  unsigned SrcReg, bool isKill, int FrameIndex,
172  const TargetRegisterClass *RC,
173  const TargetRegisterInfo *TRI) const override;
174 
177  unsigned DestReg, int FrameIndex,
178  const TargetRegisterClass *RC,
179  const TargetRegisterInfo *TRI) const override;
180 
181  bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
182 
184  unsigned DestReg, unsigned SubIdx,
185  const MachineInstr *Orig,
186  const TargetRegisterInfo &TRI) const override;
187 
189  MachineFunction &MF) const override;
190 
192  bool=false) const override;
193 
194  const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
195  unsigned SubIdx, unsigned State,
196  const TargetRegisterInfo *TRI) const;
197 
198  bool produceSameValue(const MachineInstr *MI0, const MachineInstr *MI1,
199  const MachineRegisterInfo *MRI) const override;
200 
201  /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
202  /// determine if two loads are loading from the same base address. It should
203  /// only return true if the base pointers are the same and the only
204  /// differences between the two addresses is the offset. It also returns the
205  /// offsets by reference.
206  bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
207  int64_t &Offset2) const override;
208 
209  /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
210  /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
211  /// should be scheduled togther. On some targets if two loads are loading from
212  /// addresses in the same cache line, it's better if they are scheduled
213  /// together. This function takes two integers that represent the load offsets
214  /// from the common base address. It returns true if it decides it's desirable
215  /// to schedule the two loads together. "NumLoads" is the number of loads that
216  /// have already been scheduled after Load1.
217  bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
218  int64_t Offset1, int64_t Offset2,
219  unsigned NumLoads) const override;
220 
221  bool isSchedulingBoundary(const MachineInstr *MI,
222  const MachineBasicBlock *MBB,
223  const MachineFunction &MF) const override;
224 
226  unsigned NumCycles, unsigned ExtraPredCycles,
227  const BranchProbability &Probability) const override;
228 
229  bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT,
230  unsigned ExtraT, MachineBasicBlock &FMBB,
231  unsigned NumF, unsigned ExtraF,
232  const BranchProbability &Probability) const override;
233 
234  bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
235  const BranchProbability &Probability) const override {
236  return NumCycles == 1;
237  }
238 
240  MachineBasicBlock &FMBB) const override;
241 
242  /// analyzeCompare - For a comparison instruction, return the source registers
243  /// in SrcReg and SrcReg2 if having two register operands, and the value it
244  /// compares against in CmpValue. Return true if the comparison instruction
245  /// can be analyzed.
246  bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
247  unsigned &SrcReg2, int &CmpMask,
248  int &CmpValue) const override;
249 
250  /// optimizeCompareInstr - Convert the instruction to set the zero flag so
251  /// that we can remove a "comparison with zero"; Remove a redundant CMP
252  /// instruction if the flags can be updated in the same way by an earlier
253  /// instruction such as SUB.
254  bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
255  unsigned SrcReg2, int CmpMask, int CmpValue,
256  const MachineRegisterInfo *MRI) const override;
257 
258  bool analyzeSelect(const MachineInstr *MI,
260  unsigned &TrueOp, unsigned &FalseOp,
261  bool &Optimizable) const override;
262 
265  bool) const override;
266 
267  /// FoldImmediate - 'Reg' is known to be defined by a move immediate
268  /// instruction, try to fold the immediate into the use instruction.
269  bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
270  unsigned Reg, MachineRegisterInfo *MRI) const override;
271 
272  unsigned getNumMicroOps(const InstrItineraryData *ItinData,
273  const MachineInstr *MI) const override;
274 
275  int getOperandLatency(const InstrItineraryData *ItinData,
276  const MachineInstr *DefMI, unsigned DefIdx,
277  const MachineInstr *UseMI,
278  unsigned UseIdx) const override;
279  int getOperandLatency(const InstrItineraryData *ItinData,
280  SDNode *DefNode, unsigned DefIdx,
281  SDNode *UseNode, unsigned UseIdx) const override;
282 
283  /// VFP/NEON execution domains.
284  std::pair<uint16_t, uint16_t>
285  getExecutionDomain(const MachineInstr *MI) const override;
286  void setExecutionDomain(MachineInstr *MI, unsigned Domain) const override;
287 
288  unsigned getPartialRegUpdateClearance(const MachineInstr*, unsigned,
289  const TargetRegisterInfo*) const override;
291  const TargetRegisterInfo *TRI) const override;
292 
293  /// Get the number of addresses by LDM or VLDM or zero for unknown.
294  unsigned getNumLDMAddresses(const MachineInstr *MI) const;
295 
296 private:
297  unsigned getInstBundleLength(const MachineInstr *MI) const;
298 
299  int getVLDMDefCycle(const InstrItineraryData *ItinData,
300  const MCInstrDesc &DefMCID,
301  unsigned DefClass,
302  unsigned DefIdx, unsigned DefAlign) const;
303  int getLDMDefCycle(const InstrItineraryData *ItinData,
304  const MCInstrDesc &DefMCID,
305  unsigned DefClass,
306  unsigned DefIdx, unsigned DefAlign) const;
307  int getVSTMUseCycle(const InstrItineraryData *ItinData,
308  const MCInstrDesc &UseMCID,
309  unsigned UseClass,
310  unsigned UseIdx, unsigned UseAlign) const;
311  int getSTMUseCycle(const InstrItineraryData *ItinData,
312  const MCInstrDesc &UseMCID,
313  unsigned UseClass,
314  unsigned UseIdx, unsigned UseAlign) const;
315  int getOperandLatency(const InstrItineraryData *ItinData,
316  const MCInstrDesc &DefMCID,
317  unsigned DefIdx, unsigned DefAlign,
318  const MCInstrDesc &UseMCID,
319  unsigned UseIdx, unsigned UseAlign) const;
320 
321  unsigned getPredicationCost(const MachineInstr *MI) const override;
322 
323  unsigned getInstrLatency(const InstrItineraryData *ItinData,
324  const MachineInstr *MI,
325  unsigned *PredCost = nullptr) const override;
326 
327  int getInstrLatency(const InstrItineraryData *ItinData,
328  SDNode *Node) const override;
329 
330  bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
331  const MachineRegisterInfo *MRI,
332  const MachineInstr *DefMI, unsigned DefIdx,
333  const MachineInstr *UseMI,
334  unsigned UseIdx) const override;
335  bool hasLowDefLatency(const TargetSchedModel &SchedModel,
336  const MachineInstr *DefMI,
337  unsigned DefIdx) const override;
338 
339  /// verifyInstruction - Perform target specific instruction verification.
340  bool verifyInstruction(const MachineInstr *MI,
341  StringRef &ErrInfo) const override;
342 
343  virtual void expandLoadStackGuard(MachineBasicBlock::iterator MI,
344  Reloc::Model RM) const = 0;
345 
346 private:
347  /// Modeling special VFP / NEON fp MLA / MLS hazards.
348 
349  /// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal
350  /// MLx table.
351  DenseMap<unsigned, unsigned> MLxEntryMap;
352 
353  /// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause
354  /// stalls when scheduled together with fp MLA / MLS opcodes.
355  SmallSet<unsigned, 16> MLxHazardOpcodes;
356 
357 public:
358  /// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS
359  /// instruction.
360  bool isFpMLxInstruction(unsigned Opcode) const {
361  return MLxEntryMap.count(Opcode);
362  }
363 
364  /// isFpMLxInstruction - This version also returns the multiply opcode and the
365  /// addition / subtraction opcode to expand to. Return true for 'HasLane' for
366  /// the MLX instructions with an extra lane operand.
367  bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
368  unsigned &AddSubOpc, bool &NegAcc,
369  bool &HasLane) const;
370 
371  /// canCauseFpMLxStall - Return true if an instruction of the specified opcode
372  /// will cause stalls when scheduled after (within 4-cycle window) a fp
373  /// MLA / MLS instruction.
374  bool canCauseFpMLxStall(unsigned Opcode) const {
375  return MLxHazardOpcodes.count(Opcode);
376  }
377 
378  /// Returns true if the instruction has a shift by immediate that can be
379  /// executed in one cycle less.
380  bool isSwiftFastImmShift(const MachineInstr *MI) const;
381 };
382 
383 static inline
385  return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
386 }
387 
388 static inline
390  return MIB.addReg(0);
391 }
392 
393 static inline
395  bool isDead = false) {
396  return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
397 }
398 
399 static inline
401  return MIB.addReg(0);
402 }
403 
404 static inline
405 bool isUncondBranchOpcode(int Opc) {
406  return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
407 }
408 
409 static inline
410 bool isCondBranchOpcode(int Opc) {
411  return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
412 }
413 
414 static inline
415 bool isJumpTableBranchOpcode(int Opc) {
416  return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd ||
417  Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
418 }
419 
420 static inline
421 bool isIndirectBranchOpcode(int Opc) {
422  return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
423 }
424 
425 static inline bool isPopOpcode(int Opc) {
426  return Opc == ARM::tPOP_RET || Opc == ARM::LDMIA_RET ||
427  Opc == ARM::t2LDMIA_RET || Opc == ARM::tPOP || Opc == ARM::LDMIA_UPD ||
428  Opc == ARM::t2LDMIA_UPD || Opc == ARM::VLDMDIA_UPD;
429 }
430 
431 static inline bool isPushOpcode(int Opc) {
432  return Opc == ARM::tPUSH || Opc == ARM::t2STMDB_UPD ||
433  Opc == ARM::STMDB_UPD || Opc == ARM::VSTMDDB_UPD;
434 }
435 
436 /// getInstrPredicate - If instruction is predicated, returns its predicate
437 /// condition, otherwise returns AL. It also returns the condition code
438 /// register by reference.
439 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
440 
441 unsigned getMatchingCondBranchOpcode(unsigned Opc);
442 
443 /// Determine if MI can be folded into an ARM MOVCC instruction, and return the
444 /// opcode of the SSA instruction representing the conditional MI.
445 unsigned canFoldARMInstrIntoMOVCC(unsigned Reg,
446  MachineInstr *&MI,
447  const MachineRegisterInfo &MRI);
448 
449 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether
450 /// the instruction is encoded with an 'S' bit is determined by the optional
451 /// CPSR def operand.
452 unsigned convertAddSubFlagsOpcode(unsigned OldOpc);
453 
454 /// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
455 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
456 /// code.
457 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
458  MachineBasicBlock::iterator &MBBI, DebugLoc dl,
459  unsigned DestReg, unsigned BaseReg, int NumBytes,
460  ARMCC::CondCodes Pred, unsigned PredReg,
461  const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
462 
463 void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
464  MachineBasicBlock::iterator &MBBI, DebugLoc dl,
465  unsigned DestReg, unsigned BaseReg, int NumBytes,
466  ARMCC::CondCodes Pred, unsigned PredReg,
467  const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
468 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
469  MachineBasicBlock::iterator &MBBI, DebugLoc dl,
470  unsigned DestReg, unsigned BaseReg,
471  int NumBytes, const TargetInstrInfo &TII,
472  const ARMBaseRegisterInfo& MRI,
473  unsigned MIFlags = 0);
474 
475 /// Tries to add registers to the reglist of a given base-updating
476 /// push/pop instruction to adjust the stack by an additional
477 /// NumBytes. This can save a few bytes per function in code-size, but
478 /// obviously generates more memory traffic. As such, it only takes
479 /// effect in functions being optimised for size.
480 bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,
481  MachineFunction &MF, MachineInstr *MI,
482  unsigned NumBytes);
483 
484 /// rewriteARMFrameIndex / rewriteT2FrameIndex -
485 /// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
486 /// offset could not be handled directly in MI, and return the left-over
487 /// portion by reference.
488 bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
489  unsigned FrameReg, int &Offset,
490  const ARMBaseInstrInfo &TII);
491 
492 bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
493  unsigned FrameReg, int &Offset,
494  const ARMBaseInstrInfo &TII);
495 
496 } // End llvm namespace
497 
498 #endif
ARMCC::CondCodes getPredicate(const MachineInstr *MI) const
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
bool getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const override
Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
MachineInstr * duplicate(MachineInstr *Orig, MachineFunction &MF) const override
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:138
unsigned getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr *MI) const override
void emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
std::pair< uint16_t, uint16_t > getExecutionDomain(const MachineInstr *MI) const override
VFP/NEON execution domains.
bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const override
optimizeCompareInstr - Convert the instruction to set the zero flag so that we can remove a "comparis...
virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const
GetInstSize - Returns the size of the specified MachineInstr.
A debug info location.
Definition: DebugLoc.h:34
bool produceSameValue(const MachineInstr *MI0, const MachineInstr *MI1, const MachineRegisterInfo *MRI) const override
bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget, MachineFunction &MF, MachineInstr *MI, unsigned NumBytes)
Tries to add registers to the reglist of a given base-updating push/pop instruction to adjust the sta...
unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const override
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:242
static const MachineInstrBuilder & AddNoT1CC(const MachineInstrBuilder &MIB)
static const MachineInstrBuilder & AddDefaultPred(const MachineInstrBuilder &MIB)
Provide an instruction scheduling machine model to CodeGen passes.
const HexagonInstrInfo * TII
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, DebugLoc DL) const override
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APInt.h:33
bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const ARMBaseInstrInfo &TII)
rewriteARMFrameIndex / rewriteT2FrameIndex - Rewrite MI to access 'Offset' bytes from the FP...
Reg
All possible values of the reg field in the ModR/M byte.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override
shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction w...
bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const ARMBaseInstrInfo &TII)
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
bool isFpMLxInstruction(unsigned Opcode) const
isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS instruction.
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, const BranchProbability &Probability) const override
bool canCauseFpMLxStall(unsigned Opcode) const
canCauseFpMLxStall - Return true if an instruction of the specified opcode will cause stalls when sch...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: ArrayRef.h:31
bool PredicateInstruction(MachineInstr *MI, ArrayRef< MachineOperand > Pred) const override
Itinerary data supplied by a subtarget to be used by a target.
unsigned getMatchingCondBranchOpcode(unsigned Opc)
int64_t getImm() const
static bool isCondBranchOpcode(int Opc)
unsigned getDeadRegState(bool B)
unsigned getDefRegState(bool B)
bundle_iterator< MachineInstr, instr_iterator > iterator
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are lo...
ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg)
getInstrPredicate - If instruction is predicated, returns its predicate condition, otherwise returns AL.
bool isSchedulingBoundary(const MachineInstr *MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
bundle_iterator - MachineBasicBlock iterator that automatically skips over MIs that are inside bundle...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
static bool isJumpTableBranchOpcode(int Opc)
void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags=0)
void copyFromCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, bool KillSrc, const ARMSubtarget &Subtarget) const
unsigned convertAddSubFlagsOpcode(unsigned OldOpc)
Map pseudo instructions that imply an 'S' bit onto real opcodes.
MachineInstr * commuteInstruction(MachineInstr *, bool=false) const override
commuteInstruction - Handle commutable instructions.
MachineInstr * optimizeSelect(MachineInstr *MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool) const override
void breakPartialRegDependency(MachineBasicBlock::iterator, unsigned, const TargetRegisterInfo *TRI) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of instructions to materializea des...
unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const override
bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const override
analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if h...
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:53
static const MachineInstrBuilder & AddDefaultCC(const MachineInstrBuilder &MIB)
static bool isIndirectBranchOpcode(int Opc)
static bool isUncondBranchOpcode(int Opc)
virtual unsigned getUnindexedOpcode(unsigned Opc) const =0
unsigned RemoveBranch(MachineBasicBlock &MBB) const override
bool isSwiftFastImmShift(const MachineInstr *MI) const
Returns true if the instruction has a shift by immediate that can be executed in one cycle less...
Represents one node in the SelectionDAG.
static bool isPushOpcode(int Opc)
size_type count(const KeyT &Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Definition: DenseMap.h:119
void copyToCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool KillSrc, const ARMSubtarget &Subtarget) const
bool isPredicable(MachineInstr *MI) const override
isPredicable - Return true if the specified instruction can be predicated.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
unsigned canFoldARMInstrIntoMOVCC(unsigned Reg, MachineInstr *&MI, const MachineRegisterInfo &MRI)
Determine if MI can be folded into an ARM MOVCC instruction, and return the opcode of the SSA instruc...
bool DefinesPredicate(MachineInstr *MI, std::vector< MachineOperand > &Pred) const override
ARMBaseInstrInfo(const ARMSubtarget &STI)
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, const BranchProbability &Probability) const override
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
TargetSubtargetInfo - Generic base class for all target subtargets.
bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, unsigned Reg, MachineRegisterInfo *MRI) const override
FoldImmediate - 'Reg' is known to be defined by a move immediate instruction, try to fold the immedia...
static bool isPopOpcode(int Opc)
Representation of each machine instruction.
Definition: MachineInstr.h:51
bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const override
Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx.
unsigned getNumLDMAddresses(const MachineInstr *MI) const
Get the number of addresses by LDM or VLDM or zero for unknown.
#define I(x, y, z)
Definition: MD5.cpp:54
bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override
bool isPredicated(const MachineInstr *MI) const override
bool getRegSequenceLikeInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const override
Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx.
int getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const override
bool analyzeSelect(const MachineInstr *MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const override
unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const override
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
virtual const ARMBaseRegisterInfo & getRegisterInfo() const =0
unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const override
BasicBlockListType::iterator iterator
const ARMSubtarget & getSubtarget() const
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:40
unsigned getPartialRegUpdateClearance(const MachineInstr *, unsigned, const TargetRegisterInfo *) const override
void expandLoadStackGuardBase(MachineBasicBlock::iterator MI, unsigned LoadImmOpc, unsigned LoadOpc, Reloc::Model RM) const
void setExecutionDomain(MachineInstr *MI, unsigned Domain) const override
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
static const MachineInstrBuilder & AddDefaultT1CC(const MachineInstrBuilder &MIB, bool isDead=false)
const MachineInstrBuilder & AddDReg(MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI) const
MachineInstr * convertToThreeAddress(MachineFunction::iterator &MFI, MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const override
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SubIdx, const MachineInstr *Orig, const TargetRegisterInfo &TRI) const override