LLVM  3.7.0
TargetInstrInfo.cpp
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1 //===-- TargetInstrInfo.cpp - Target Instruction Information --------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
21 #include "llvm/CodeGen/StackMaps.h"
23 #include "llvm/IR/DataLayout.h"
24 #include "llvm/MC/MCAsmInfo.h"
33 #include <cctype>
34 using namespace llvm;
35 
37  "disable-sched-hazard", cl::Hidden, cl::init(false),
38  cl::desc("Disable hazard detection during preRA scheduling"));
39 
41 }
42 
44 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
45  const TargetRegisterInfo *TRI,
46  const MachineFunction &MF) const {
47  if (OpNum >= MCID.getNumOperands())
48  return nullptr;
49 
50  short RegClass = MCID.OpInfo[OpNum].RegClass;
51  if (MCID.OpInfo[OpNum].isLookupPtrRegClass())
52  return TRI->getPointerRegClass(MF, RegClass);
53 
54  // Instructions like INSERT_SUBREG do not have fixed register classes.
55  if (RegClass < 0)
56  return nullptr;
57 
58  // Otherwise just look it up normally.
59  return TRI->getRegClass(RegClass);
60 }
61 
62 /// insertNoop - Insert a noop into the instruction stream at the specified
63 /// point.
66  llvm_unreachable("Target didn't implement insertNoop!");
67 }
68 
69 /// Measure the specified inline asm to determine an approximation of its
70 /// length.
71 /// Comments (which run till the next SeparatorString or newline) do not
72 /// count as an instruction.
73 /// Any other non-whitespace text is considered an instruction, with
74 /// multiple instructions separated by SeparatorString or newlines.
75 /// Variable-length instructions are not handled here; this function
76 /// may be overloaded in the target code to do that.
77 unsigned TargetInstrInfo::getInlineAsmLength(const char *Str,
78  const MCAsmInfo &MAI) const {
79 
80 
81  // Count the number of instructions in the asm.
82  bool atInsnStart = true;
83  unsigned Length = 0;
84  for (; *Str; ++Str) {
85  if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
86  strlen(MAI.getSeparatorString())) == 0)
87  atInsnStart = true;
88  if (atInsnStart && !std::isspace(static_cast<unsigned char>(*Str))) {
89  Length += MAI.getMaxInstLength();
90  atInsnStart = false;
91  }
92  if (atInsnStart && strncmp(Str, MAI.getCommentString(),
93  strlen(MAI.getCommentString())) == 0)
94  atInsnStart = false;
95  }
96 
97  return Length;
98 }
99 
100 /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything
101 /// after it, replacing it with an unconditional branch to NewDest.
102 void
104  MachineBasicBlock *NewDest) const {
105  MachineBasicBlock *MBB = Tail->getParent();
106 
107  // Remove all the old successors of MBB from the CFG.
108  while (!MBB->succ_empty())
109  MBB->removeSuccessor(MBB->succ_begin());
110 
111  // Remove all the dead instructions from the end of MBB.
112  MBB->erase(Tail, MBB->end());
113 
114  // If MBB isn't immediately before MBB, insert a branch to it.
116  InsertBranch(*MBB, NewDest, nullptr, SmallVector<MachineOperand, 0>(),
117  Tail->getDebugLoc());
118  MBB->addSuccessor(NewDest);
119 }
120 
121 // commuteInstruction - The default implementation of this method just exchanges
122 // the two operands returned by findCommutedOpIndices.
124  bool NewMI) const {
125  const MCInstrDesc &MCID = MI->getDesc();
126  bool HasDef = MCID.getNumDefs();
127  if (HasDef && !MI->getOperand(0).isReg())
128  // No idea how to commute this instruction. Target should implement its own.
129  return nullptr;
130  unsigned Idx1, Idx2;
131  if (!findCommutedOpIndices(MI, Idx1, Idx2)) {
132  assert(MI->isCommutable() && "Precondition violation: MI must be commutable.");
133  return nullptr;
134  }
135 
136  assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() &&
137  "This only knows how to commute register operands so far");
138  unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0;
139  unsigned Reg1 = MI->getOperand(Idx1).getReg();
140  unsigned Reg2 = MI->getOperand(Idx2).getReg();
141  unsigned SubReg0 = HasDef ? MI->getOperand(0).getSubReg() : 0;
142  unsigned SubReg1 = MI->getOperand(Idx1).getSubReg();
143  unsigned SubReg2 = MI->getOperand(Idx2).getSubReg();
144  bool Reg1IsKill = MI->getOperand(Idx1).isKill();
145  bool Reg2IsKill = MI->getOperand(Idx2).isKill();
146  bool Reg1IsUndef = MI->getOperand(Idx1).isUndef();
147  bool Reg2IsUndef = MI->getOperand(Idx2).isUndef();
148  bool Reg1IsInternal = MI->getOperand(Idx1).isInternalRead();
149  bool Reg2IsInternal = MI->getOperand(Idx2).isInternalRead();
150  // If destination is tied to either of the commuted source register, then
151  // it must be updated.
152  if (HasDef && Reg0 == Reg1 &&
153  MI->getDesc().getOperandConstraint(Idx1, MCOI::TIED_TO) == 0) {
154  Reg2IsKill = false;
155  Reg0 = Reg2;
156  SubReg0 = SubReg2;
157  } else if (HasDef && Reg0 == Reg2 &&
158  MI->getDesc().getOperandConstraint(Idx2, MCOI::TIED_TO) == 0) {
159  Reg1IsKill = false;
160  Reg0 = Reg1;
161  SubReg0 = SubReg1;
162  }
163 
164  if (NewMI) {
165  // Create a new instruction.
166  MachineFunction &MF = *MI->getParent()->getParent();
167  MI = MF.CloneMachineInstr(MI);
168  }
169 
170  if (HasDef) {
171  MI->getOperand(0).setReg(Reg0);
172  MI->getOperand(0).setSubReg(SubReg0);
173  }
174  MI->getOperand(Idx2).setReg(Reg1);
175  MI->getOperand(Idx1).setReg(Reg2);
176  MI->getOperand(Idx2).setSubReg(SubReg1);
177  MI->getOperand(Idx1).setSubReg(SubReg2);
178  MI->getOperand(Idx2).setIsKill(Reg1IsKill);
179  MI->getOperand(Idx1).setIsKill(Reg2IsKill);
180  MI->getOperand(Idx2).setIsUndef(Reg1IsUndef);
181  MI->getOperand(Idx1).setIsUndef(Reg2IsUndef);
182  MI->getOperand(Idx2).setIsInternalRead(Reg1IsInternal);
183  MI->getOperand(Idx1).setIsInternalRead(Reg2IsInternal);
184  return MI;
185 }
186 
187 /// findCommutedOpIndices - If specified MI is commutable, return the two
188 /// operand indices that would swap value. Return true if the instruction
189 /// is not in a form which this routine understands.
191  unsigned &SrcOpIdx1,
192  unsigned &SrcOpIdx2) const {
193  assert(!MI->isBundle() &&
194  "TargetInstrInfo::findCommutedOpIndices() can't handle bundles");
195 
196  const MCInstrDesc &MCID = MI->getDesc();
197  if (!MCID.isCommutable())
198  return false;
199  // This assumes v0 = op v1, v2 and commuting would swap v1 and v2. If this
200  // is not true, then the target must implement this.
201  SrcOpIdx1 = MCID.getNumDefs();
202  SrcOpIdx2 = SrcOpIdx1 + 1;
203  if (!MI->getOperand(SrcOpIdx1).isReg() ||
204  !MI->getOperand(SrcOpIdx2).isReg())
205  // No idea.
206  return false;
207  return true;
208 }
209 
210 
211 bool
213  if (!MI->isTerminator()) return false;
214 
215  // Conditional branch is a special case.
216  if (MI->isBranch() && !MI->isBarrier())
217  return true;
218  if (!MI->isPredicable())
219  return true;
220  return !isPredicated(MI);
221 }
222 
225  bool MadeChange = false;
226 
227  assert(!MI->isBundle() &&
228  "TargetInstrInfo::PredicateInstruction() can't handle bundles");
229 
230  const MCInstrDesc &MCID = MI->getDesc();
231  if (!MI->isPredicable())
232  return false;
233 
234  for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
235  if (MCID.OpInfo[i].isPredicate()) {
236  MachineOperand &MO = MI->getOperand(i);
237  if (MO.isReg()) {
238  MO.setReg(Pred[j].getReg());
239  MadeChange = true;
240  } else if (MO.isImm()) {
241  MO.setImm(Pred[j].getImm());
242  MadeChange = true;
243  } else if (MO.isMBB()) {
244  MO.setMBB(Pred[j].getMBB());
245  MadeChange = true;
246  }
247  ++j;
248  }
249  }
250  return MadeChange;
251 }
252 
254  const MachineMemOperand *&MMO,
255  int &FrameIndex) const {
257  oe = MI->memoperands_end();
258  o != oe;
259  ++o) {
260  if ((*o)->isLoad()) {
262  dyn_cast_or_null<FixedStackPseudoSourceValue>(
263  (*o)->getPseudoValue())) {
264  FrameIndex = Value->getFrameIndex();
265  MMO = *o;
266  return true;
267  }
268  }
269  }
270  return false;
271 }
272 
274  const MachineMemOperand *&MMO,
275  int &FrameIndex) const {
277  oe = MI->memoperands_end();
278  o != oe;
279  ++o) {
280  if ((*o)->isStore()) {
282  dyn_cast_or_null<FixedStackPseudoSourceValue>(
283  (*o)->getPseudoValue())) {
284  FrameIndex = Value->getFrameIndex();
285  MMO = *o;
286  return true;
287  }
288  }
289  }
290  return false;
291 }
292 
294  unsigned SubIdx, unsigned &Size,
295  unsigned &Offset,
296  const MachineFunction &MF) const {
297  if (!SubIdx) {
298  Size = RC->getSize();
299  Offset = 0;
300  return true;
301  }
302  const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
303  unsigned BitSize = TRI->getSubRegIdxSize(SubIdx);
304  // Convert bit size to byte size to be consistent with
305  // MCRegisterClass::getSize().
306  if (BitSize % 8)
307  return false;
308 
309  int BitOffset = TRI->getSubRegIdxOffset(SubIdx);
310  if (BitOffset < 0 || BitOffset % 8)
311  return false;
312 
313  Size = BitSize /= 8;
314  Offset = (unsigned)BitOffset / 8;
315 
316  assert(RC->getSize() >= (Offset + Size) && "bad subregister range");
317 
318  if (!MF.getTarget().getDataLayout()->isLittleEndian()) {
319  Offset = RC->getSize() - (Offset + Size);
320  }
321  return true;
322 }
323 
326  unsigned DestReg,
327  unsigned SubIdx,
328  const MachineInstr *Orig,
329  const TargetRegisterInfo &TRI) const {
330  MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
331  MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI);
332  MBB.insert(I, MI);
333 }
334 
335 bool
337  const MachineInstr *MI1,
338  const MachineRegisterInfo *MRI) const {
340 }
341 
343  MachineFunction &MF) const {
344  assert(!Orig->isNotDuplicable() &&
345  "Instruction cannot be duplicated");
346  return MF.CloneMachineInstr(Orig);
347 }
348 
349 // If the COPY instruction in MI can be folded to a stack operation, return
350 // the register class to use.
352  unsigned FoldIdx) {
353  assert(MI->isCopy() && "MI must be a COPY instruction");
354  if (MI->getNumOperands() != 2)
355  return nullptr;
356  assert(FoldIdx<2 && "FoldIdx refers no nonexistent operand");
357 
358  const MachineOperand &FoldOp = MI->getOperand(FoldIdx);
359  const MachineOperand &LiveOp = MI->getOperand(1-FoldIdx);
360 
361  if (FoldOp.getSubReg() || LiveOp.getSubReg())
362  return nullptr;
363 
364  unsigned FoldReg = FoldOp.getReg();
365  unsigned LiveReg = LiveOp.getReg();
366 
367  assert(TargetRegisterInfo::isVirtualRegister(FoldReg) &&
368  "Cannot fold physregs");
369 
370  const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
371  const TargetRegisterClass *RC = MRI.getRegClass(FoldReg);
372 
374  return RC->contains(LiveOp.getReg()) ? RC : nullptr;
375 
376  if (RC->hasSubClassEq(MRI.getRegClass(LiveReg)))
377  return RC;
378 
379  // FIXME: Allow folding when register classes are memory compatible.
380  return nullptr;
381 }
382 
384  llvm_unreachable("Not a MachO target");
385 }
386 
388  ArrayRef<unsigned> Ops) const {
389  return MI->isCopy() && Ops.size() == 1 && canFoldCopy(MI, Ops[0]);
390 }
391 
394  const TargetInstrInfo &TII) {
395  unsigned StartIdx = 0;
396  switch (MI->getOpcode()) {
398  StartIdx = 2; // Skip ID, nShadowBytes.
399  break;
401  // For PatchPoint, the call args are not foldable.
402  PatchPointOpers opers(MI);
403  StartIdx = opers.getVarIdx();
404  break;
405  }
406  default:
407  llvm_unreachable("unexpected stackmap opcode");
408  }
409 
410  // Return false if any operands requested for folding are not foldable (not
411  // part of the stackmap's live values).
412  for (unsigned Op : Ops) {
413  if (Op < StartIdx)
414  return nullptr;
415  }
416 
417  MachineInstr *NewMI =
418  MF.CreateMachineInstr(TII.get(MI->getOpcode()), MI->getDebugLoc(), true);
419  MachineInstrBuilder MIB(MF, NewMI);
420 
421  // No need to fold return, the meta data, and function arguments
422  for (unsigned i = 0; i < StartIdx; ++i)
423  MIB.addOperand(MI->getOperand(i));
424 
425  for (unsigned i = StartIdx; i < MI->getNumOperands(); ++i) {
426  MachineOperand &MO = MI->getOperand(i);
427  if (std::find(Ops.begin(), Ops.end(), i) != Ops.end()) {
428  unsigned SpillSize;
429  unsigned SpillOffset;
430  // Compute the spill slot size and offset.
431  const TargetRegisterClass *RC =
432  MF.getRegInfo().getRegClass(MO.getReg());
433  bool Valid =
434  TII.getStackSlotRange(RC, MO.getSubReg(), SpillSize, SpillOffset, MF);
435  if (!Valid)
436  report_fatal_error("cannot spill patchpoint subregister operand");
438  MIB.addImm(SpillSize);
439  MIB.addFrameIndex(FrameIndex);
440  MIB.addImm(SpillOffset);
441  }
442  else
443  MIB.addOperand(MO);
444  }
445  return NewMI;
446 }
447 
448 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
449 /// slot into the specified machine instruction for the specified operand(s).
450 /// If this is possible, a new instruction is returned with the specified
451 /// operand folded, otherwise NULL is returned. The client is responsible for
452 /// removing the old instruction and adding the new one in the instruction
453 /// stream.
455  ArrayRef<unsigned> Ops,
456  int FI) const {
457  unsigned Flags = 0;
458  for (unsigned i = 0, e = Ops.size(); i != e; ++i)
459  if (MI->getOperand(Ops[i]).isDef())
461  else
462  Flags |= MachineMemOperand::MOLoad;
463 
464  MachineBasicBlock *MBB = MI->getParent();
465  assert(MBB && "foldMemoryOperand needs an inserted instruction");
466  MachineFunction &MF = *MBB->getParent();
467 
468  MachineInstr *NewMI = nullptr;
469 
470  if (MI->getOpcode() == TargetOpcode::STACKMAP ||
471  MI->getOpcode() == TargetOpcode::PATCHPOINT) {
472  // Fold stackmap/patchpoint.
473  NewMI = foldPatchpoint(MF, MI, Ops, FI, *this);
474  if (NewMI)
475  MBB->insert(MI, NewMI);
476  } else {
477  // Ask the target to do the actual folding.
478  NewMI = foldMemoryOperandImpl(MF, MI, Ops, MI, FI);
479  }
480 
481  if (NewMI) {
482  NewMI->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
483  // Add a memory operand, foldMemoryOperandImpl doesn't do that.
484  assert((!(Flags & MachineMemOperand::MOStore) ||
485  NewMI->mayStore()) &&
486  "Folded a def to a non-store!");
487  assert((!(Flags & MachineMemOperand::MOLoad) ||
488  NewMI->mayLoad()) &&
489  "Folded a use to a non-load!");
490  const MachineFrameInfo &MFI = *MF.getFrameInfo();
491  assert(MFI.getObjectOffset(FI) != -1);
492  MachineMemOperand *MMO =
494  Flags, MFI.getObjectSize(FI),
495  MFI.getObjectAlignment(FI));
496  NewMI->addMemOperand(MF, MMO);
497 
498  return NewMI;
499  }
500 
501  // Straight COPY may fold as load/store.
502  if (!MI->isCopy() || Ops.size() != 1)
503  return nullptr;
504 
505  const TargetRegisterClass *RC = canFoldCopy(MI, Ops[0]);
506  if (!RC)
507  return nullptr;
508 
509  const MachineOperand &MO = MI->getOperand(1-Ops[0]);
511  const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
512 
513  if (Flags == MachineMemOperand::MOStore)
514  storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI);
515  else
516  loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, TRI);
517  return --Pos;
518 }
519 
520 /// foldMemoryOperand - Same as the previous version except it allows folding
521 /// of any load and store from / to any address, not just from a specific
522 /// stack slot.
524  ArrayRef<unsigned> Ops,
525  MachineInstr *LoadMI) const {
526  assert(LoadMI->canFoldAsLoad() && "LoadMI isn't foldable!");
527 #ifndef NDEBUG
528  for (unsigned i = 0, e = Ops.size(); i != e; ++i)
529  assert(MI->getOperand(Ops[i]).isUse() && "Folding load into def!");
530 #endif
531  MachineBasicBlock &MBB = *MI->getParent();
532  MachineFunction &MF = *MBB.getParent();
533 
534  // Ask the target to do the actual folding.
535  MachineInstr *NewMI = nullptr;
536  int FrameIndex = 0;
537 
538  if ((MI->getOpcode() == TargetOpcode::STACKMAP ||
539  MI->getOpcode() == TargetOpcode::PATCHPOINT) &&
540  isLoadFromStackSlot(LoadMI, FrameIndex)) {
541  // Fold stackmap/patchpoint.
542  NewMI = foldPatchpoint(MF, MI, Ops, FrameIndex, *this);
543  if (NewMI)
544  NewMI = MBB.insert(MI, NewMI);
545  } else {
546  // Ask the target to do the actual folding.
547  NewMI = foldMemoryOperandImpl(MF, MI, Ops, MI, LoadMI);
548  }
549 
550  if (!NewMI) return nullptr;
551 
552  // Copy the memoperands from the load to the folded instruction.
553  if (MI->memoperands_empty()) {
554  NewMI->setMemRefs(LoadMI->memoperands_begin(),
555  LoadMI->memoperands_end());
556  }
557  else {
558  // Handle the rare case of folding multiple loads.
559  NewMI->setMemRefs(MI->memoperands_begin(),
560  MI->memoperands_end());
562  E = LoadMI->memoperands_end(); I != E; ++I) {
563  NewMI->addMemOperand(MF, *I);
564  }
565  }
566  return NewMI;
567 }
568 
569 bool TargetInstrInfo::
570 isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
571  AliasAnalysis *AA) const {
572  const MachineFunction &MF = *MI->getParent()->getParent();
573  const MachineRegisterInfo &MRI = MF.getRegInfo();
574 
575  // Remat clients assume operand 0 is the defined register.
576  if (!MI->getNumOperands() || !MI->getOperand(0).isReg())
577  return false;
578  unsigned DefReg = MI->getOperand(0).getReg();
579 
580  // A sub-register definition can only be rematerialized if the instruction
581  // doesn't read the other parts of the register. Otherwise it is really a
582  // read-modify-write operation on the full virtual register which cannot be
583  // moved safely.
585  MI->getOperand(0).getSubReg() && MI->readsVirtualRegister(DefReg))
586  return false;
587 
588  // A load from a fixed stack slot can be rematerialized. This may be
589  // redundant with subsequent checks, but it's target-independent,
590  // simple, and a common case.
591  int FrameIdx = 0;
592  if (isLoadFromStackSlot(MI, FrameIdx) &&
593  MF.getFrameInfo()->isImmutableObjectIndex(FrameIdx))
594  return true;
595 
596  // Avoid instructions obviously unsafe for remat.
597  if (MI->isNotDuplicable() || MI->mayStore() ||
599  return false;
600 
601  // Don't remat inline asm. We have no idea how expensive it is
602  // even if it's side effect free.
603  if (MI->isInlineAsm())
604  return false;
605 
606  // Avoid instructions which load from potentially varying memory.
607  if (MI->mayLoad() && !MI->isInvariantLoad(AA))
608  return false;
609 
610  // If any of the registers accessed are non-constant, conservatively assume
611  // the instruction is not rematerializable.
612  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
613  const MachineOperand &MO = MI->getOperand(i);
614  if (!MO.isReg()) continue;
615  unsigned Reg = MO.getReg();
616  if (Reg == 0)
617  continue;
618 
619  // Check for a well-behaved physical register.
621  if (MO.isUse()) {
622  // If the physreg has no defs anywhere, it's just an ambient register
623  // and we can freely move its uses. Alternatively, if it's allocatable,
624  // it could get allocated to something with a def during allocation.
625  if (!MRI.isConstantPhysReg(Reg, MF))
626  return false;
627  } else {
628  // A physreg def. We can't remat it.
629  return false;
630  }
631  continue;
632  }
633 
634  // Only allow one virtual-register def. There may be multiple defs of the
635  // same virtual register, though.
636  if (MO.isDef() && Reg != DefReg)
637  return false;
638 
639  // Don't allow any virtual-register uses. Rematting an instruction with
640  // virtual register uses would length the live ranges of the uses, which
641  // is not necessarily a good idea, certainly not "trivial".
642  if (MO.isUse())
643  return false;
644  }
645 
646  // Everything checked out.
647  return true;
648 }
649 
651  const MachineFunction *MF = MI->getParent()->getParent();
653  bool StackGrowsDown =
655 
656  unsigned FrameSetupOpcode = getCallFrameSetupOpcode();
657  unsigned FrameDestroyOpcode = getCallFrameDestroyOpcode();
658 
659  if (MI->getOpcode() != FrameSetupOpcode &&
660  MI->getOpcode() != FrameDestroyOpcode)
661  return 0;
662 
663  int SPAdj = MI->getOperand(0).getImm();
664 
665  if ((!StackGrowsDown && MI->getOpcode() == FrameSetupOpcode) ||
666  (StackGrowsDown && MI->getOpcode() == FrameDestroyOpcode))
667  SPAdj = -SPAdj;
668 
669  return SPAdj;
670 }
671 
672 /// isSchedulingBoundary - Test if the given instruction should be
673 /// considered a scheduling boundary. This primarily includes labels
674 /// and terminators.
676  const MachineBasicBlock *MBB,
677  const MachineFunction &MF) const {
678  // Terminators and labels can't be scheduled around.
679  if (MI->isTerminator() || MI->isPosition())
680  return true;
681 
682  // Don't attempt to schedule around any instruction that defines
683  // a stack-oriented pointer, as it's unlikely to be profitable. This
684  // saves compile time, because it doesn't require every single
685  // stack slot reference to depend on the instruction that does the
686  // modification.
687  const TargetLowering &TLI = *MF.getSubtarget().getTargetLowering();
688  const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
690  return true;
691 
692  return false;
693 }
694 
695 // Provide a global flag for disabling the PreRA hazard recognizer that targets
696 // may choose to honor.
698  return !DisableHazardRecognizer;
699 }
700 
701 // Default implementation of CreateTargetRAHazardRecognizer.
704  const ScheduleDAG *DAG) const {
705  // Dummy hazard recognizer allows all instructions to issue.
706  return new ScheduleHazardRecognizer();
707 }
708 
709 // Default implementation of CreateTargetMIHazardRecognizer.
712  const ScheduleDAG *DAG) const {
713  return (ScheduleHazardRecognizer *)
714  new ScoreboardHazardRecognizer(II, DAG, "misched");
715 }
716 
717 // Default implementation of CreateTargetPostRAHazardRecognizer.
720  const ScheduleDAG *DAG) const {
721  return (ScheduleHazardRecognizer *)
722  new ScoreboardHazardRecognizer(II, DAG, "post-RA-sched");
723 }
724 
725 //===----------------------------------------------------------------------===//
726 // SelectionDAG latency interface.
727 //===----------------------------------------------------------------------===//
728 
729 int
731  SDNode *DefNode, unsigned DefIdx,
732  SDNode *UseNode, unsigned UseIdx) const {
733  if (!ItinData || ItinData->isEmpty())
734  return -1;
735 
736  if (!DefNode->isMachineOpcode())
737  return -1;
738 
739  unsigned DefClass = get(DefNode->getMachineOpcode()).getSchedClass();
740  if (!UseNode->isMachineOpcode())
741  return ItinData->getOperandCycle(DefClass, DefIdx);
742  unsigned UseClass = get(UseNode->getMachineOpcode()).getSchedClass();
743  return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
744 }
745 
747  SDNode *N) const {
748  if (!ItinData || ItinData->isEmpty())
749  return 1;
750 
751  if (!N->isMachineOpcode())
752  return 1;
753 
754  return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass());
755 }
756 
757 //===----------------------------------------------------------------------===//
758 // MachineInstr latency interface.
759 //===----------------------------------------------------------------------===//
760 
761 unsigned
763  const MachineInstr *MI) const {
764  if (!ItinData || ItinData->isEmpty())
765  return 1;
766 
767  unsigned Class = MI->getDesc().getSchedClass();
768  int UOps = ItinData->Itineraries[Class].NumMicroOps;
769  if (UOps >= 0)
770  return UOps;
771 
772  // The # of u-ops is dynamically determined. The specific target should
773  // override this function to return the right number.
774  return 1;
775 }
776 
777 /// Return the default expected latency for a def based on it's opcode.
779  const MachineInstr *DefMI) const {
780  if (DefMI->isTransient())
781  return 0;
782  if (DefMI->mayLoad())
783  return SchedModel.LoadLatency;
784  if (isHighLatencyDef(DefMI->getOpcode()))
785  return SchedModel.HighLatency;
786  return 1;
787 }
788 
790  return 0;
791 }
792 
793 unsigned TargetInstrInfo::
795  const MachineInstr *MI,
796  unsigned *PredCost) const {
797  // Default to one cycle for no itinerary. However, an "empty" itinerary may
798  // still have a MinLatency property, which getStageLatency checks.
799  if (!ItinData)
800  return MI->mayLoad() ? 2 : 1;
801 
802  return ItinData->getStageLatency(MI->getDesc().getSchedClass());
803 }
804 
806  const MachineInstr *DefMI,
807  unsigned DefIdx) const {
808  const InstrItineraryData *ItinData = SchedModel.getInstrItineraries();
809  if (!ItinData || ItinData->isEmpty())
810  return false;
811 
812  unsigned DefClass = DefMI->getDesc().getSchedClass();
813  int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
814  return (DefCycle != -1 && DefCycle <= 1);
815 }
816 
817 /// Both DefMI and UseMI must be valid. By default, call directly to the
818 /// itinerary. This may be overriden by the target.
821  const MachineInstr *DefMI, unsigned DefIdx,
822  const MachineInstr *UseMI, unsigned UseIdx) const {
823  unsigned DefClass = DefMI->getDesc().getSchedClass();
824  unsigned UseClass = UseMI->getDesc().getSchedClass();
825  return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
826 }
827 
828 /// If we can determine the operand latency from the def only, without itinerary
829 /// lookup, do so. Otherwise return -1.
831  const InstrItineraryData *ItinData,
832  const MachineInstr *DefMI) const {
833 
834  // Let the target hook getInstrLatency handle missing itineraries.
835  if (!ItinData)
836  return getInstrLatency(ItinData, DefMI);
837 
838  if(ItinData->isEmpty())
839  return defaultDefLatency(ItinData->SchedModel, DefMI);
840 
841  // ...operand lookup required
842  return -1;
843 }
844 
845 /// computeOperandLatency - Compute and return the latency of the given data
846 /// dependent def and use when the operand indices are already known. UseMI may
847 /// be NULL for an unknown use.
848 ///
849 /// FindMin may be set to get the minimum vs. expected latency. Minimum
850 /// latency is used for scheduling groups, while expected latency is for
851 /// instruction cost and critical path.
852 ///
853 /// Depending on the subtarget's itinerary properties, this may or may not need
854 /// to call getOperandLatency(). For most subtargets, we don't need DefIdx or
855 /// UseIdx to compute min latency.
856 unsigned TargetInstrInfo::
858  const MachineInstr *DefMI, unsigned DefIdx,
859  const MachineInstr *UseMI, unsigned UseIdx) const {
860 
861  int DefLatency = computeDefOperandLatency(ItinData, DefMI);
862  if (DefLatency >= 0)
863  return DefLatency;
864 
865  assert(ItinData && !ItinData->isEmpty() && "computeDefOperandLatency fail");
866 
867  int OperLatency = 0;
868  if (UseMI)
869  OperLatency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);
870  else {
871  unsigned DefClass = DefMI->getDesc().getSchedClass();
872  OperLatency = ItinData->getOperandCycle(DefClass, DefIdx);
873  }
874  if (OperLatency >= 0)
875  return OperLatency;
876 
877  // No operand latency was found.
878  unsigned InstrLatency = getInstrLatency(ItinData, DefMI);
879 
880  // Expected latency is the max of the stage latency and itinerary props.
881  InstrLatency = std::max(InstrLatency,
882  defaultDefLatency(ItinData->SchedModel, DefMI));
883  return InstrLatency;
884 }
885 
887  const MachineInstr &MI, unsigned DefIdx,
888  SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
889  assert((MI.isRegSequence() ||
890  MI.isRegSequenceLike()) && "Instruction do not have the proper type");
891 
892  if (!MI.isRegSequence())
893  return getRegSequenceLikeInputs(MI, DefIdx, InputRegs);
894 
895  // We are looking at:
896  // Def = REG_SEQUENCE v0, sub0, v1, sub1, ...
897  assert(DefIdx == 0 && "REG_SEQUENCE only has one def");
898  for (unsigned OpIdx = 1, EndOpIdx = MI.getNumOperands(); OpIdx != EndOpIdx;
899  OpIdx += 2) {
900  const MachineOperand &MOReg = MI.getOperand(OpIdx);
901  const MachineOperand &MOSubIdx = MI.getOperand(OpIdx + 1);
902  assert(MOSubIdx.isImm() &&
903  "One of the subindex of the reg_sequence is not an immediate");
904  // Record Reg:SubReg, SubIdx.
905  InputRegs.push_back(RegSubRegPairAndIdx(MOReg.getReg(), MOReg.getSubReg(),
906  (unsigned)MOSubIdx.getImm()));
907  }
908  return true;
909 }
910 
912  const MachineInstr &MI, unsigned DefIdx,
913  RegSubRegPairAndIdx &InputReg) const {
914  assert((MI.isExtractSubreg() ||
915  MI.isExtractSubregLike()) && "Instruction do not have the proper type");
916 
917  if (!MI.isExtractSubreg())
918  return getExtractSubregLikeInputs(MI, DefIdx, InputReg);
919 
920  // We are looking at:
921  // Def = EXTRACT_SUBREG v0.sub1, sub0.
922  assert(DefIdx == 0 && "EXTRACT_SUBREG only has one def");
923  const MachineOperand &MOReg = MI.getOperand(1);
924  const MachineOperand &MOSubIdx = MI.getOperand(2);
925  assert(MOSubIdx.isImm() &&
926  "The subindex of the extract_subreg is not an immediate");
927 
928  InputReg.Reg = MOReg.getReg();
929  InputReg.SubReg = MOReg.getSubReg();
930  InputReg.SubIdx = (unsigned)MOSubIdx.getImm();
931  return true;
932 }
933 
935  const MachineInstr &MI, unsigned DefIdx,
936  RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const {
937  assert((MI.isInsertSubreg() ||
938  MI.isInsertSubregLike()) && "Instruction do not have the proper type");
939 
940  if (!MI.isInsertSubreg())
941  return getInsertSubregLikeInputs(MI, DefIdx, BaseReg, InsertedReg);
942 
943  // We are looking at:
944  // Def = INSERT_SEQUENCE v0, v1, sub0.
945  assert(DefIdx == 0 && "INSERT_SUBREG only has one def");
946  const MachineOperand &MOBaseReg = MI.getOperand(1);
947  const MachineOperand &MOInsertedReg = MI.getOperand(2);
948  const MachineOperand &MOSubIdx = MI.getOperand(3);
949  assert(MOSubIdx.isImm() &&
950  "One of the subindex of the reg_sequence is not an immediate");
951  BaseReg.Reg = MOBaseReg.getReg();
952  BaseReg.SubReg = MOBaseReg.getSubReg();
953 
954  InsertedReg.Reg = MOInsertedReg.getReg();
955  InsertedReg.SubReg = MOInsertedReg.getSubReg();
956  InsertedReg.SubIdx = (unsigned)MOSubIdx.getImm();
957  return true;
958 }
bool isConstantPhysReg(unsigned PhysReg, const MachineFunction &MF) const
isConstantPhysReg - Returns true if PhysReg is unallocatable and constant throughout the function...
virtual MachineInstr * duplicate(MachineInstr *Orig, MachineFunction &MF) const
Create a duplicate of the Orig instruction in MF.
virtual ScheduleHazardRecognizer * CreateTargetMIHazardRecognizer(const InstrItineraryData *, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
The memory access reads data.
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
The memory access writes data.
MachineInstr * CreateMachineInstr(const MCInstrDesc &MCID, DebugLoc DL, bool NoImp=false)
CreateMachineInstr - Allocate a new MachineInstr.
virtual bool hasStoreToStackSlot(const MachineInstr *MI, const MachineMemOperand *&MMO, int &FrameIndex) const
If the specified machine instruction has a store to a stack slot, return true along with the FrameInd...
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:427
unsigned computeOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const
Compute and return the latency of the given data dependent def and use when the operand indices are a...
virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx, unsigned &Size, unsigned &Offset, const MachineFunction &MF) const
Compute the size in bytes and offset within a stack slot of a spilled register or subregister...
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:191
virtual bool hasLoadFromStackSlot(const MachineInstr *MI, const MachineMemOperand *&MMO, int &FrameIndex) const
If the specified machine instruction has a load from a stack slot, return true along with the FrameIn...
bool usePreRAHazardRecognizer() const
Provide a global flag for disabling the PreRA hazard recognizer that targets may choose to honor...
bool hasSubClassEq(const TargetRegisterClass *RC) const
hasSubClassEq - Returns true if RC is a sub-class of or equal to this class.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:138
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:579
void setIsUndef(bool Val=true)
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
bool getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const
Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx.
A Stackmap instruction captures the location of live variables at its position in the instruction str...
bool isPredicable(QueryType Type=AllInBundle) const
Return true if this instruction has a predicate operand that controls execution.
Definition: MachineInstr.h:457
bool readsVirtualRegister(unsigned Reg) const
Return true if the MachineInstr reads the specified virtual register.
Definition: MachineInstr.h:844
virtual ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
static cl::opt< bool > DisableHazardRecognizer("disable-sched-hazard", cl::Hidden, cl::init(false), cl::desc("Disable hazard detection during preRA scheduling"))
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:264
virtual bool isSchedulingBoundary(const MachineInstr *MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const
Test if the given instruction should be considered a scheduling boundary.
virtual void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SubIdx, const MachineInstr *Orig, const TargetRegisterInfo &TRI) const
Re-issue the specified 'original' instruction at the specific location targeting a new destination re...
bool canFoldAsLoad(QueryType Type=IgnoreBundle) const
Return true for instructions that can be folded as memory operands in other instructions.
Definition: MachineInstr.h:512
unsigned getVarIdx() const
Get the operand index of the variable list of non-argument operands.
Definition: StackMaps.h:69
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, unsigned f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
getMachineMemOperand - Allocate a new MachineMemOperand.
bool isExtractSubreg() const
Definition: MachineInstr.h:784
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:419
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag=true)
Reports a serious error, calling any installed error handler.
static MachinePointerInfo getFixedStack(int FI, int64_t offset=0)
getFixedStack - Return a MachinePointerInfo record that refers to the the specified FrameIndex...
int NumMicroOps
of micro-ops, -1 means it's variable
virtual unsigned getPredicationCost(const MachineInstr *MI) const
virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel, const MachineInstr *DefMI, unsigned DefIdx) const
Compute operand latency of a def of 'Reg'.
unsigned getSize() const
getSize - Return the size of the register in bytes, which is also the size of a stack slot allocated ...
int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const
Return the cycle for the given class and operand.
MachineMemOperand - A description of a memory reference used in the backend.
unsigned getCallFrameDestroyOpcode() const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
Provide an instruction scheduling machine model to CodeGen passes.
const HexagonInstrInfo * TII
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
const InstrItinerary * Itineraries
Array of itineraries selected.
const TargetRegisterClass * getRegClass(unsigned i) const
getRegClass - Returns the register class associated with the enumeration value.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APInt.h:33
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:566
const TargetRegisterClass * getRegClass(unsigned Reg) const
getRegClass - Return the register class of the specified virtual register.
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool isUndef() const
static MachineInstr * foldPatchpoint(MachineFunction &MF, MachineInstr *MI, ArrayRef< unsigned > Ops, int FrameIndex, const TargetInstrInfo &TII)
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual bool produceSameValue(const MachineInstr *MI0, const MachineInstr *MI1, const MachineRegisterInfo *MRI=nullptr) const
Return true if two machine instructions would produce identical values.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:271
bool isKill() const
unsigned getCallFrameSetupOpcode() const
These methods return the opcode of the frame setup/destroy instructions if they exist (-1 otherwise)...
virtual MachineInstr * commuteInstruction(MachineInstr *MI, bool NewMI=false) const
If a target has any instructions that are commutable but require converting to different instructions...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: ArrayRef.h:31
bool isLittleEndian() const
Layout endianness...
Definition: DataLayout.h:217
Itinerary data supplied by a subtarget to be used by a target.
bool isImmutableObjectIndex(int ObjectIdx) const
isImmutableObjectIndex - Returns true if the specified index corresponds to an immutable object...
int64_t getImm() const
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:134
virtual unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr *MI, unsigned *PredCost=nullptr) const
Compute the instruction latency of a given instruction.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:150
bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const
Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:267
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:120
TargetInstrInfo - Interface to description of machine instruction set.
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:58
mmo_iterator memoperands_end() const
Definition: MachineInstr.h:341
bool isInsertSubreg() const
Definition: MachineInstr.h:766
bool isBundle() const
Definition: MachineInstr.h:775
bundle_iterator< MachineInstr, instr_iterator > iterator
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:325
Patchable call instruction - this instruction represents a call to a constant address, followed by a series of NOPs.
unsigned LoadLatency
Definition: MCSchedule.h:171
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
const InstrItineraryData * getInstrItineraries() const
unsigned defaultDefLatency(const MCSchedModel &SchedModel, const MachineInstr *DefMI) const
Return the default expected latency for a def based on it's opcode.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
unsigned getStageLatency(unsigned ItinClassIndx) const
Return the total stage latency of the given class.
virtual int getSPAdjust(const MachineInstr *MI) const
Returns the actual stack pointer adjustment made by an instruction as part of a call sequence...
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Load the specified register of the given register class from the specified stack frame index...
void setMBB(MachineBasicBlock *MBB)
bool isCopy() const
Definition: MachineInstr.h:778
virtual bool getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const
Target-dependent implementation of getInsertSubregInputs.
bool isPosition() const
Definition: MachineInstr.h:746
void setImm(int64_t immVal)
void setIsInternalRead(bool Val=true)
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore...
MI-level patchpoint operands.
Definition: StackMaps.h:40
bool isInvariantLoad(AliasAnalysis *AA) const
Return true if this instruction is loading from a location whose value is invariant across the functi...
virtual void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Store the specified register of the given register class to the specified stack frame index...
unsigned getStackPointerRegisterToSaveRestore() const
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save...
void removeSuccessor(MachineBasicBlock *succ)
removeSuccessor - Remove successor from the successors list of this MachineBasicBlock.
unsigned getSubReg() const
bool isNotDuplicable(QueryType Type=AnyInBundle) const
Return true if this instruction cannot be safely duplicated.
Definition: MachineInstr.h:487
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:162
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
void setIsKill(bool Val=true)
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
bool isInsertSubregLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions...
Definition: MachineInstr.h:555
virtual const TargetFrameLowering * getFrameLowering() const
void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
virtual void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
Insert a noop into the instruction stream at the specified point.
virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const
If specified MI is commutable, return the two operand indices that would swap value.
bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const
Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx.
bool isIdenticalTo(const MachineInstr *Other, MICheckType Check=CheckDefs) const
Return true if this instruction is identical to (same opcode and same operands as) the specified inst...
MachineInstr * CloneMachineInstr(const MachineInstr *Orig)
CloneMachineInstr - Create a new MachineInstr which is a copy of the 'Orig' instruction, identical in all ways except the instruction has no parent, prev, or next.
const DataLayout * getDataLayout() const
Deprecated in 3.7, will be removed in 3.8.
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:861
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
A pair composed of a register and a sub-register index.
virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr *MI) const
Return the number of u-operations the given machine instruction will be decoded to on the target cpu...
virtual const TargetLowering * getTargetLowering() const
bool isInlineAsm() const
Definition: MachineInstr.h:760
Information about stack frame layout on the target.
virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const
Returns true if the instruction is a terminator instruction that has not been predicated.
unsigned HighLatency
Definition: MCSchedule.h:179
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Represents one node in the SelectionDAG.
const MachineInstrBuilder & addFrameIndex(int Idx) const
bool isTransient() const
Return true if this is a transient instruction that is either very likely to be eliminated during reg...
Definition: MachineInstr.h:804
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
MachineInstr * foldMemoryOperand(MachineBasicBlock::iterator MI, ArrayRef< unsigned > Ops, int FrameIndex) const
Attempt to fold a load or store of the specified stack slot into the specified machine instruction fo...
bool isExtractSubregLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions...
Definition: MachineInstr.h:541
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:238
int getOperandLatency(unsigned DefClass, unsigned DefIdx, unsigned UseClass, unsigned UseIdx) const
Compute and return the use operand latency of a given itinerary class and operand index if the value ...
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const
Target-dependent implementation of getExtractSubregInputs.
Representation of each machine instruction.
Definition: MachineInstr.h:51
static bool isPhysicalRegister(unsigned Reg)
isPhysicalRegister - Return true if the specified register number is in the physical register namespa...
StackDirection getStackGrowthDirection() const
getStackGrowthDirection - Return the direction the stack grows
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:528
virtual unsigned getInlineAsmLength(const char *Str, const MCAsmInfo &MAI) const
Measure the specified inline asm to determine an approximation of its length.
MCSchedModel SchedModel
Basic machine properties.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:62
virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
If the specified machine instruction is a direct load from a stack slot, return the virtual or physic...
const char * getSeparatorString() const
Definition: MCAsmInfo.h:439
void setReg(unsigned Reg)
Change the register this operand corresponds to.
#define I(x, y, z)
Definition: MD5.cpp:54
#define N
void setSubReg(unsigned subReg)
virtual bool getRegSequenceLikeInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const
Target-dependent implementation of getRegSequenceInputs.
virtual void getNoopForMachoTarget(MCInst &NopInst) const
Return the noop instruction to use for a noop.
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
virtual int getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const
bool isLookupPtrRegClass() const
Set if this operand is a pointer value and it requires a callback to look up its register class...
Definition: MCInstrDesc.h:76
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, DebugLoc DL) const
Insert branch code into the end of the specified MachineBasicBlock.
virtual bool canFoldMemoryOperand(const MachineInstr *MI, ArrayRef< unsigned > Ops) const
Returns true for the specified load / store if folding is possible.
unsigned getSubRegIdxOffset(unsigned Idx) const
Get the offset of the bit range covered by a sub-register index.
static const TargetRegisterClass * canFoldCopy(const MachineInstr *MI, unsigned FoldIdx)
virtual ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
unsigned getReg() const
getReg - Returns the register number.
bool isCommutable(QueryType Type=IgnoreBundle) const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged.
Definition: MachineInstr.h:607
virtual bool PredicateInstruction(MachineInstr *MI, ArrayRef< MachineOperand > Pred) const
Convert the instruction into a predicated instruction.
LLVM Value Representation.
Definition: Value.h:69
unsigned getMaxInstLength() const
Definition: MCAsmInfo.h:436
int computeDefOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI) const
If we can determine the operand latency from the def only, without itinerary lookup, do so.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:185
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:149
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
BasicBlockListType::iterator iterator
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex) const
Target-dependent implementation for foldMemoryOperand.
virtual bool isPredicated(const MachineInstr *MI) const
Returns true if the instruction is already predicated.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
const TargetRegisterClass * getRegClass(const MCInstrDesc &TID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum...
FixedStackPseudoSourceValue - A specialized PseudoSourceValue for holding FixedStack values...
virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const
Delete the instruction OldInst and everything after it, replacing it with an unconditional branch to ...
unsigned getSubRegIdxSize(unsigned Idx) const
Get the size of the bit range covered by a sub-register index.
bool isRegSequence() const
Definition: MachineInstr.h:772
bool isRegSequenceLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions.
Definition: MachineInstr.h:526
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:136
bool isEmpty() const
Returns true if there are no itineraries.
const char * getCommentString() const
Definition: MCAsmInfo.h:445
void addSuccessor(MachineBasicBlock *succ, uint32_t weight=0)
addSuccessor - Add succ as a successor of this MachineBasicBlock.
virtual const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const
getPointerRegClass - Returns a TargetRegisterClass used for pointer values.
void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd)
Assign this MachineInstr's memory reference descriptor list.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
Definition: MachineInstr.h:874
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:410
virtual bool isHighLatencyDef(int opc) const
Return true if this opcode has high latency to its result.
bool isInternalRead() const
bool isMachineOpcode() const
Test if this node has a post-isel opcode, directly corresponding to a MachineInstr opcode...
This file describes how to lower LLVM code to machine code.
unsigned getMachineOpcode() const
This may only be called if isMachineOpcode returns true.
A pair composed of a pair of a register and a sub-register index, and another sub-register index...
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:340
bool contains(unsigned Reg) const
contains - Return true if the specified register is included in this register class.