27 #define DEBUG_TYPE "regalloc"
29 STATISTIC(NumAssigned ,
"Number of registers assigned");
30 STATISTIC(NumUnassigned ,
"Number of registers unassigned");
34 "Live Register Matrix",
false,
false)
41 UserTag(0), RegMaskTag(0), RegMaskVirtReg(0) {}
43 void LiveRegMatrix::getAnalysisUsage(
AnalysisUsage &AU)
const {
53 LIS = &getAnalysis<LiveIntervals>();
54 VRM = &getAnalysis<VirtRegMap>();
57 if (NumRegUnits != Matrix.
size())
59 Matrix.
init(LIUAlloc, NumRegUnits);
66 void LiveRegMatrix::releaseMemory() {
67 for (
unsigned i = 0, e = Matrix.
size(); i != e; ++i) {
75 template<
typename Callable>
77 unsigned PhysReg, Callable
Func) {
80 unsigned Unit = (*Units).first;
81 unsigned Mask = (*Units).second;
83 if (S.LaneMask & Mask) {
92 if (
Func(*Units, VRegInterval))
101 <<
" to " <<
PrintReg(PhysReg, TRI) <<
':');
102 assert(!VRM->hasPhys(VirtReg.
reg) &&
"Duplicate VirtReg assignment");
103 VRM->assignVirt2Phys(VirtReg.
reg, PhysReg);
109 Matrix[
Unit].unify(VirtReg, Range);
118 unsigned PhysReg = VRM->getPhys(VirtReg.
reg);
120 <<
" from " <<
PrintReg(PhysReg, TRI) <<
':');
121 VRM->clearVirt(VirtReg.
reg);
126 Matrix[
Unit].extract(VirtReg, Range);
136 if (!Matrix[*
Unit].empty())
147 if (RegMaskVirtReg != VirtReg.
reg || RegMaskTag != UserTag) {
148 RegMaskVirtReg = VirtReg.
reg;
149 RegMaskTag = UserTag;
150 RegMaskUsable.
clear();
157 return !RegMaskUsable.
empty() && (!PhysReg || !RegMaskUsable.
test(PhysReg));
177 Q.
init(UserTag, &VirtReg, &Matrix[RegUnit]);
void setPhysRegUsed(unsigned Reg)
setPhysRegUsed - Mark the specified register used in this function.
No interference, go ahead and assign.
bool isValid() const
Returns true if this iterator is not yet at the end.
STATISTIC(NumFunctions,"Total number of functions")
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
InterferenceKind checkInterference(LiveInterval &VirtReg, unsigned PhysReg)
Check for interference before assigning VirtReg to PhysReg.
LiveInterval - This class represents the liveness of a register, or stack slot.
PrintRegUnit - Helper class for printing register units on a raw_ostream.
A live range for subregisters.
void init(unsigned UTag, LiveInterval *VReg, LiveIntervalUnion *LIU)
bool checkRegMaskInterference(LiveInterval &LI, BitVector &UsableRegs)
checkRegMaskInterference - Test if LI is live across any register mask instructions, and compute a bit mask of physical registers that are not clobbered by any of them.
bool foreachUnit(const TargetRegisterInfo *TRI, LiveInterval &VRegInterval, unsigned PhysReg, Callable Func)
This class represents the liveness of a register, stack slot, etc.
#define INITIALIZE_PASS_DEPENDENCY(depName)
void clear()
clear - Clear all bits.
Query interferences between a single live virtual register and a live interval union.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MCRegUnitIterator enumerates a list of register units and their associated lane masks for Reg...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
A helper class for register coalescers.
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
iterator_range< subrange_iterator > subranges()
Register unit interference.
PrintReg - Helper class for printing registers on a raw_ostream.
void assign(LiveInterval &VirtReg, unsigned PhysReg)
Assign VirtReg to PhysReg.
void invalidateVirtRegs()
Invalidate cached interference queries after modifying virtual register live ranges.
SlotIndexes * getSlotIndexes() const
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
bool empty() const
empty - Tests whether there are no bits in this bitvector.
bool overlaps(const LiveRange &other) const
overlaps - Return true if the intersection of the two live ranges is not empty.
Represent the analysis usage information of a pass.
bool isPhysRegUsed(unsigned PhysReg) const
Returns true if the given PhysReg has any live intervals assigned.
void unassign(LiveInterval &VirtReg)
Unassign VirtReg from its PhysReg.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool test(unsigned Idx) const
bool checkRegUnitInterference(LiveInterval &VirtReg, unsigned PhysReg)
Check for regunit interference only.
void init(LiveIntervalUnion::Allocator &, unsigned Size)
Promote Memory to Register
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void setPreservesAll()
Set by analyses that do not transform their input at all.
unsigned getNumRegUnits() const
Return the number of (native) register units in the target.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
AnalysisUsage & addRequiredTransitive()
LiveIntervalUnion::Query & query(LiveInterval &VirtReg, unsigned RegUnit)
Query a line of the assigned virtual register matrix directly.
std::vector< uint8_t > Unit
bool checkRegMaskInterference(LiveInterval &VirtReg, unsigned PhysReg=0)
Check for regmask interference only.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
bool hasSubRanges() const
Returns true if subregister liveness information is available.
Virtual register interference.
LiveRange & getRegUnit(unsigned Unit)
getRegUnit - Return the live range for Unit.
INITIALIZE_PASS_BEGIN(LiveRegMatrix,"liveregmatrix","Live Register Matrix", false, false) INITIALIZE_PASS_END(LiveRegMatrix