LLVM  3.7.0
BPFISelLowering.cpp
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1 //===-- BPFISelLowering.cpp - BPF DAG Lowering Implementation ------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that BPF uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "BPFISelLowering.h"
16 #include "BPF.h"
17 #include "BPFTargetMachine.h"
18 #include "BPFSubtarget.h"
28 #include "llvm/Support/Debug.h"
31 #include "llvm/IR/DiagnosticInfo.h"
33 using namespace llvm;
34 
35 #define DEBUG_TYPE "bpf-lower"
36 
37 namespace {
38 
39 // Diagnostic information for unimplemented or unsupported feature reporting.
40 class DiagnosticInfoUnsupported : public DiagnosticInfo {
41 private:
42  // Debug location where this diagnostic is triggered.
43  DebugLoc DLoc;
44  const Twine &Description;
45  const Function &Fn;
46  SDValue Value;
47 
48  static int KindID;
49 
50  static int getKindID() {
51  if (KindID == 0)
53  return KindID;
54  }
55 
56 public:
57  DiagnosticInfoUnsupported(SDLoc DLoc, const Function &Fn, const Twine &Desc,
58  SDValue Value)
59  : DiagnosticInfo(getKindID(), DS_Error), DLoc(DLoc.getDebugLoc()),
60  Description(Desc), Fn(Fn), Value(Value) {}
61 
62  void print(DiagnosticPrinter &DP) const override {
63  std::string Str;
64  raw_string_ostream OS(Str);
65 
66  if (DLoc) {
67  auto DIL = DLoc.get();
68  StringRef Filename = DIL->getFilename();
69  unsigned Line = DIL->getLine();
70  unsigned Column = DIL->getColumn();
71  OS << Filename << ':' << Line << ':' << Column << ' ';
72  }
73 
74  OS << "in function " << Fn.getName() << ' ' << *Fn.getFunctionType() << '\n'
75  << Description;
76  if (Value)
77  Value->print(OS);
78  OS << '\n';
79  OS.flush();
80  DP << Str;
81  }
82 
83  static bool classof(const DiagnosticInfo *DI) {
84  return DI->getKind() == getKindID();
85  }
86 };
87 
88 int DiagnosticInfoUnsupported::KindID = 0;
89 }
90 
92  const BPFSubtarget &STI)
93  : TargetLowering(TM) {
94 
95  // Set up the register classes.
96  addRegisterClass(MVT::i64, &BPF::GPRRegClass);
97 
98  // Compute derived properties from the register classes
100 
102 
109 
111 
115 
120 
125 
130 
131  // no UNDEF allowed
133 
139 
145 
150 
151  // Extended load operations for i1 types must be promoted
152  for (MVT VT : MVT::integer_valuetypes()) {
156 
160  }
161 
163 
164  // Function alignments (log2)
167 
168  // inline memcpy() for kernel to see explicit copy
172 }
173 
175  switch (Op.getOpcode()) {
176  case ISD::BR_CC:
177  return LowerBR_CC(Op, DAG);
178  case ISD::GlobalAddress:
179  return LowerGlobalAddress(Op, DAG);
180  case ISD::SELECT_CC:
181  return LowerSELECT_CC(Op, DAG);
182  default:
183  llvm_unreachable("unimplemented operand");
184  }
185 }
186 
187 // Calling Convention Implementation
188 #include "BPFGenCallingConv.inc"
189 
190 SDValue BPFTargetLowering::LowerFormalArguments(
191  SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
193  SmallVectorImpl<SDValue> &InVals) const {
194  switch (CallConv) {
195  default:
196  llvm_unreachable("Unsupported calling convention");
197  case CallingConv::C:
198  case CallingConv::Fast:
199  break;
200  }
201 
203  MachineRegisterInfo &RegInfo = MF.getRegInfo();
204 
205  // Assign locations to all of the incoming arguments.
207  CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
208  CCInfo.AnalyzeFormalArguments(Ins, CC_BPF64);
209 
210  for (auto &VA : ArgLocs) {
211  if (VA.isRegLoc()) {
212  // Arguments passed in registers
213  EVT RegVT = VA.getLocVT();
214  switch (RegVT.getSimpleVT().SimpleTy) {
215  default: {
216  errs() << "LowerFormalArguments Unhandled argument type: "
217  << RegVT.getSimpleVT().SimpleTy << '\n';
218  llvm_unreachable(0);
219  }
220  case MVT::i64:
221  unsigned VReg = RegInfo.createVirtualRegister(&BPF::GPRRegClass);
222  RegInfo.addLiveIn(VA.getLocReg(), VReg);
223  SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT);
224 
225  // If this is an 8/16/32-bit value, it is really passed promoted to 64
226  // bits. Insert an assert[sz]ext to capture this, then truncate to the
227  // right size.
228  if (VA.getLocInfo() == CCValAssign::SExt)
229  ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
230  DAG.getValueType(VA.getValVT()));
231  else if (VA.getLocInfo() == CCValAssign::ZExt)
232  ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
233  DAG.getValueType(VA.getValVT()));
234 
235  if (VA.getLocInfo() != CCValAssign::Full)
236  ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue);
237 
238  InVals.push_back(ArgValue);
239  }
240  } else {
241  DiagnosticInfoUnsupported Err(DL, *MF.getFunction(),
242  "defined with too many args", SDValue());
243  DAG.getContext()->diagnose(Err);
244  }
245  }
246 
247  if (IsVarArg || MF.getFunction()->hasStructRetAttr()) {
248  DiagnosticInfoUnsupported Err(
249  DL, *MF.getFunction(),
250  "functions with VarArgs or StructRet are not supported", SDValue());
251  DAG.getContext()->diagnose(Err);
252  }
253 
254  return Chain;
255 }
256 
257 SDValue BPFTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
258  SmallVectorImpl<SDValue> &InVals) const {
259  SelectionDAG &DAG = CLI.DAG;
260  auto &Outs = CLI.Outs;
261  auto &OutVals = CLI.OutVals;
262  auto &Ins = CLI.Ins;
263  SDValue Chain = CLI.Chain;
264  SDValue Callee = CLI.Callee;
265  bool &IsTailCall = CLI.IsTailCall;
266  CallingConv::ID CallConv = CLI.CallConv;
267  bool IsVarArg = CLI.IsVarArg;
269 
270  // BPF target does not support tail call optimization.
271  IsTailCall = false;
272 
273  switch (CallConv) {
274  default:
275  report_fatal_error("Unsupported calling convention");
276  case CallingConv::Fast:
277  case CallingConv::C:
278  break;
279  }
280 
281  // Analyze operands of the call, assigning locations to each operand.
283  CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
284 
285  CCInfo.AnalyzeCallOperands(Outs, CC_BPF64);
286 
287  unsigned NumBytes = CCInfo.getNextStackOffset();
288 
289  if (Outs.size() >= 6) {
290  DiagnosticInfoUnsupported Err(CLI.DL, *MF.getFunction(),
291  "too many args to ", Callee);
292  DAG.getContext()->diagnose(Err);
293  }
294 
295  for (auto &Arg : Outs) {
296  ISD::ArgFlagsTy Flags = Arg.Flags;
297  if (!Flags.isByVal())
298  continue;
299 
300  DiagnosticInfoUnsupported Err(CLI.DL, *MF.getFunction(),
301  "pass by value not supported ", Callee);
302  DAG.getContext()->diagnose(Err);
303  }
304 
305  auto PtrVT = getPointerTy(MF.getDataLayout());
306  Chain = DAG.getCALLSEQ_START(
307  Chain, DAG.getConstant(NumBytes, CLI.DL, PtrVT, true), CLI.DL);
308 
310 
311  // Walk arg assignments
312  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
313  CCValAssign &VA = ArgLocs[i];
314  SDValue Arg = OutVals[i];
315 
316  // Promote the value if needed.
317  switch (VA.getLocInfo()) {
318  default:
319  llvm_unreachable("Unknown loc info");
320  case CCValAssign::Full:
321  break;
322  case CCValAssign::SExt:
323  Arg = DAG.getNode(ISD::SIGN_EXTEND, CLI.DL, VA.getLocVT(), Arg);
324  break;
325  case CCValAssign::ZExt:
326  Arg = DAG.getNode(ISD::ZERO_EXTEND, CLI.DL, VA.getLocVT(), Arg);
327  break;
328  case CCValAssign::AExt:
329  Arg = DAG.getNode(ISD::ANY_EXTEND, CLI.DL, VA.getLocVT(), Arg);
330  break;
331  }
332 
333  // Push arguments into RegsToPass vector
334  if (VA.isRegLoc())
335  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
336  else
337  llvm_unreachable("call arg pass bug");
338  }
339 
340  SDValue InFlag;
341 
342  // Build a sequence of copy-to-reg nodes chained together with token chain and
343  // flag operands which copy the outgoing args into registers. The InFlag in
344  // necessary since all emitted instructions must be stuck together.
345  for (auto &Reg : RegsToPass) {
346  Chain = DAG.getCopyToReg(Chain, CLI.DL, Reg.first, Reg.second, InFlag);
347  InFlag = Chain.getValue(1);
348  }
349 
350  // If the callee is a GlobalAddress node (quite common, every direct call is)
351  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
352  // Likewise ExternalSymbol -> TargetExternalSymbol.
353  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
354  Callee = DAG.getTargetGlobalAddress(G->getGlobal(), CLI.DL, PtrVT,
355  G->getOffset(), 0);
356  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
357  Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT, 0);
358 
359  // Returns a chain & a flag for retval copy to use.
360  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
362  Ops.push_back(Chain);
363  Ops.push_back(Callee);
364 
365  // Add argument registers to the end of the list so that they are
366  // known live into the call.
367  for (auto &Reg : RegsToPass)
368  Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
369 
370  if (InFlag.getNode())
371  Ops.push_back(InFlag);
372 
373  Chain = DAG.getNode(BPFISD::CALL, CLI.DL, NodeTys, Ops);
374  InFlag = Chain.getValue(1);
375 
376  // Create the CALLSEQ_END node.
377  Chain = DAG.getCALLSEQ_END(
378  Chain, DAG.getConstant(NumBytes, CLI.DL, PtrVT, true),
379  DAG.getConstant(0, CLI.DL, PtrVT, true), InFlag, CLI.DL);
380  InFlag = Chain.getValue(1);
381 
382  // Handle result values, copying them out of physregs into vregs that we
383  // return.
384  return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, CLI.DL, DAG,
385  InVals);
386 }
387 
388 SDValue
389 BPFTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
390  bool IsVarArg,
392  const SmallVectorImpl<SDValue> &OutVals,
393  SDLoc DL, SelectionDAG &DAG) const {
394 
395  // CCValAssign - represent the assignment of the return value to a location
398 
399  // CCState - Info about the registers and stack slot.
400  CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
401 
402  if (MF.getFunction()->getReturnType()->isAggregateType()) {
403  DiagnosticInfoUnsupported Err(DL, *MF.getFunction(),
404  "only integer returns supported", SDValue());
405  DAG.getContext()->diagnose(Err);
406  }
407 
408  // Analize return values.
409  CCInfo.AnalyzeReturn(Outs, RetCC_BPF64);
410 
411  SDValue Flag;
412  SmallVector<SDValue, 4> RetOps(1, Chain);
413 
414  // Copy the result values into the output registers.
415  for (unsigned i = 0; i != RVLocs.size(); ++i) {
416  CCValAssign &VA = RVLocs[i];
417  assert(VA.isRegLoc() && "Can only return in registers!");
418 
419  Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag);
420 
421  // Guarantee that all emitted copies are stuck together,
422  // avoiding something bad.
423  Flag = Chain.getValue(1);
424  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
425  }
426 
427  unsigned Opc = BPFISD::RET_FLAG;
428  RetOps[0] = Chain; // Update chain.
429 
430  // Add the flag if we have it.
431  if (Flag.getNode())
432  RetOps.push_back(Flag);
433 
434  return DAG.getNode(Opc, DL, MVT::Other, RetOps);
435 }
436 
437 SDValue BPFTargetLowering::LowerCallResult(
438  SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
440  SmallVectorImpl<SDValue> &InVals) const {
441 
443  // Assign locations to each value returned by this call.
445  CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
446 
447  if (Ins.size() >= 2) {
448  DiagnosticInfoUnsupported Err(DL, *MF.getFunction(),
449  "only small returns supported", SDValue());
450  DAG.getContext()->diagnose(Err);
451  }
452 
453  CCInfo.AnalyzeCallResult(Ins, RetCC_BPF64);
454 
455  // Copy all of the result registers out of their specified physreg.
456  for (auto &Val : RVLocs) {
457  Chain = DAG.getCopyFromReg(Chain, DL, Val.getLocReg(),
458  Val.getValVT(), InFlag).getValue(1);
459  InFlag = Chain.getValue(2);
460  InVals.push_back(Chain.getValue(0));
461  }
462 
463  return Chain;
464 }
465 
466 static void NegateCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC) {
467  switch (CC) {
468  default:
469  break;
470  case ISD::SETULT:
471  case ISD::SETULE:
472  case ISD::SETLT:
473  case ISD::SETLE:
475  std::swap(LHS, RHS);
476  break;
477  }
478 }
479 
480 SDValue BPFTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
481  SDValue Chain = Op.getOperand(0);
482  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
483  SDValue LHS = Op.getOperand(2);
484  SDValue RHS = Op.getOperand(3);
485  SDValue Dest = Op.getOperand(4);
486  SDLoc DL(Op);
487 
488  NegateCC(LHS, RHS, CC);
489 
490  return DAG.getNode(BPFISD::BR_CC, DL, Op.getValueType(), Chain, LHS, RHS,
491  DAG.getConstant(CC, DL, MVT::i64), Dest);
492 }
493 
494 SDValue BPFTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
495  SDValue LHS = Op.getOperand(0);
496  SDValue RHS = Op.getOperand(1);
497  SDValue TrueV = Op.getOperand(2);
498  SDValue FalseV = Op.getOperand(3);
499  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
500  SDLoc DL(Op);
501 
502  NegateCC(LHS, RHS, CC);
503 
504  SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i64);
505 
506  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
507  SDValue Ops[] = {LHS, RHS, TargetCC, TrueV, FalseV};
508 
509  return DAG.getNode(BPFISD::SELECT_CC, DL, VTs, Ops);
510 }
511 
512 const char *BPFTargetLowering::getTargetNodeName(unsigned Opcode) const {
513  switch ((BPFISD::NodeType)Opcode) {
515  break;
516  case BPFISD::RET_FLAG:
517  return "BPFISD::RET_FLAG";
518  case BPFISD::CALL:
519  return "BPFISD::CALL";
520  case BPFISD::SELECT_CC:
521  return "BPFISD::SELECT_CC";
522  case BPFISD::BR_CC:
523  return "BPFISD::BR_CC";
524  case BPFISD::Wrapper:
525  return "BPFISD::Wrapper";
526  }
527  return nullptr;
528 }
529 
530 SDValue BPFTargetLowering::LowerGlobalAddress(SDValue Op,
531  SelectionDAG &DAG) const {
532  SDLoc DL(Op);
533  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
534  SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i64);
535 
536  return DAG.getNode(BPFISD::Wrapper, DL, MVT::i64, GA);
537 }
538 
541  MachineBasicBlock *BB) const {
543  DebugLoc DL = MI->getDebugLoc();
544 
545  assert(MI->getOpcode() == BPF::Select && "Unexpected instr type to insert");
546 
547  // To "insert" a SELECT instruction, we actually have to insert the diamond
548  // control-flow pattern. The incoming instruction knows the destination vreg
549  // to set, the condition code register to branch on, the true/false values to
550  // select between, and a branch opcode to use.
551  const BasicBlock *LLVM_BB = BB->getBasicBlock();
553  ++I;
554 
555  // ThisMBB:
556  // ...
557  // TrueVal = ...
558  // jmp_XX r1, r2 goto Copy1MBB
559  // fallthrough --> Copy0MBB
560  MachineBasicBlock *ThisMBB = BB;
561  MachineFunction *F = BB->getParent();
562  MachineBasicBlock *Copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
563  MachineBasicBlock *Copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
564 
565  F->insert(I, Copy0MBB);
566  F->insert(I, Copy1MBB);
567  // Update machine-CFG edges by transferring all successors of the current
568  // block to the new block which will contain the Phi node for the select.
569  Copy1MBB->splice(Copy1MBB->begin(), BB,
570  std::next(MachineBasicBlock::iterator(MI)), BB->end());
571  Copy1MBB->transferSuccessorsAndUpdatePHIs(BB);
572  // Next, add the true and fallthrough blocks as its successors.
573  BB->addSuccessor(Copy0MBB);
574  BB->addSuccessor(Copy1MBB);
575 
576  // Insert Branch if Flag
577  unsigned LHS = MI->getOperand(1).getReg();
578  unsigned RHS = MI->getOperand(2).getReg();
579  int CC = MI->getOperand(3).getImm();
580  switch (CC) {
581  case ISD::SETGT:
582  BuildMI(BB, DL, TII.get(BPF::JSGT_rr))
583  .addReg(LHS)
584  .addReg(RHS)
585  .addMBB(Copy1MBB);
586  break;
587  case ISD::SETUGT:
588  BuildMI(BB, DL, TII.get(BPF::JUGT_rr))
589  .addReg(LHS)
590  .addReg(RHS)
591  .addMBB(Copy1MBB);
592  break;
593  case ISD::SETGE:
594  BuildMI(BB, DL, TII.get(BPF::JSGE_rr))
595  .addReg(LHS)
596  .addReg(RHS)
597  .addMBB(Copy1MBB);
598  break;
599  case ISD::SETUGE:
600  BuildMI(BB, DL, TII.get(BPF::JUGE_rr))
601  .addReg(LHS)
602  .addReg(RHS)
603  .addMBB(Copy1MBB);
604  break;
605  case ISD::SETEQ:
606  BuildMI(BB, DL, TII.get(BPF::JEQ_rr))
607  .addReg(LHS)
608  .addReg(RHS)
609  .addMBB(Copy1MBB);
610  break;
611  case ISD::SETNE:
612  BuildMI(BB, DL, TII.get(BPF::JNE_rr))
613  .addReg(LHS)
614  .addReg(RHS)
615  .addMBB(Copy1MBB);
616  break;
617  default:
618  report_fatal_error("unimplemented select CondCode " + Twine(CC));
619  }
620 
621  // Copy0MBB:
622  // %FalseValue = ...
623  // # fallthrough to Copy1MBB
624  BB = Copy0MBB;
625 
626  // Update machine-CFG edges
627  BB->addSuccessor(Copy1MBB);
628 
629  // Copy1MBB:
630  // %Result = phi [ %FalseValue, Copy0MBB ], [ %TrueValue, ThisMBB ]
631  // ...
632  BB = Copy1MBB;
633  BuildMI(*BB, BB->begin(), DL, TII.get(BPF::PHI), MI->getOperand(0).getReg())
634  .addReg(MI->getOperand(5).getReg())
635  .addMBB(Copy0MBB)
636  .addReg(MI->getOperand(4).getReg())
637  .addMBB(ThisMBB);
638 
639  MI->eraseFromParent(); // The pseudo instruction is gone now.
640  return BB;
641 }
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
SDValue getValue(unsigned R) const
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
LLVMContext * getContext() const
Definition: SelectionDAG.h:289
static void NegateCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC)
SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:522
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, SDLoc DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd)...
Definition: SelectionDAG.h:646
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:554
LocInfo getLocInfo() const
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:210
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain...
Definition: ISDOpcodes.h:585
Type * getReturnType() const
Definition: Function.cpp:233
A debug info location.
Definition: DebugLoc.h:34
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *fromMBB)
transferSuccessorsAndUpdatePHIs - Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor blocks which refer to fromMBB to refer to this.
F(f)
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags=0)
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:357
bool isRegLoc() const
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag=true)
Reports a serious error, calling any installed error handler.
StringRef getName() const
Return a constant reference to the value's name.
Definition: Value.cpp:188
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:200
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
Definition: ISDOpcodes.h:371
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:79
const HexagonInstrInfo * TII
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:283
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
SDValue getTargetGlobalAddress(const GlobalValue *GV, SDLoc DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:467
Reg
All possible values of the reg field in the ModR/M byte.
SimpleValueType SimpleTy
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
Interface for custom diagnostic printing.
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
#define G(x, y, z)
Definition: MD5.cpp:52
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
SmallVector< ISD::InputArg, 32 > Ins
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:581
SDValue getCALLSEQ_START(SDValue Chain, SDValue Op, SDLoc DL)
Return a new CALLSEQ_START node, which always must have a glue result (to ensure it's not CSE'd)...
Definition: SelectionDAG.h:637
unsigned getLocReg() const
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
bool hasStructRetAttr() const
Determine if the function returns a structure through first pointer argument.
Definition: Function.h:360
SmallVector< ISD::OutputArg, 32 > Outs
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:804
int64_t getImm() const
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
const BasicBlock * getBasicBlock() const
getBasicBlock - Return the LLVM basic block that this instance corresponded to originally.
UNDEF - An undefined node.
Definition: ISDOpcodes.h:169
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:267
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:97
TargetInstrInfo - Interface to description of machine instruction set.
SDNode * getNode() const
get the SDNode which holds the desired result
bundle_iterator< MachineInstr, instr_iterator > iterator
This is the base abstract class for diagnostic reporting in the backend.
MVT - Machine Value Type.
LLVM Basic Block Representation.
Definition: BasicBlock.h:65
const SDValue & getOperand(unsigned i) const
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
MVT getLocVT() const
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:219
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:547
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
unsigned getOpcode() const
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:57
void setPrefFunctionAlignment(unsigned Align)
Set the target's preferred function alignment.
CondCode getSetCCSwappedOperands(CondCode Operation)
getSetCCSwappedOperands - Return the operation corresponding to (Y op X) when given the operation for...
unsigned MaxStoresPerMemmove
Specify maximum bytes of store instructions per memmove call.
Bit counting operators with an undefined result for zero inputs.
Definition: ISDOpcodes.h:338
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
EVT - Extended Value Type.
Definition: ValueTypes.h:31
This structure contains all information that is necessary for lowering calls.
DebugLoc getDebugLoc()
const TargetRegisterInfo * getRegisterInfo() const override
Definition: BPFSubtarget.h:58
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
void print(raw_ostream &OS, const SelectionDAG *G=nullptr) const
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
CCState - This class holds information needed while lowering arguments and return values...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:179
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:861
CCValAssign - Represent assignment of one arg/retval to a location.
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:548
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static mvt_range integer_valuetypes()
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:576
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:342
void setMinFunctionAlignment(unsigned Align)
Set the target's minimum function alignment (in log2(bytes))
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:383
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:386
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:238
int getNextAvailablePluginDiagnosticKind()
Get the next available kind ID for a plugin diagnostic.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:542
Representation of each machine instruction.
Definition: MachineInstr.h:51
SmallVector< SDValue, 32 > OutVals
bool isAggregateType() const
isAggregateType - Return true if the type is an aggregate type.
Definition: Type.h:260
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:196
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:401
#define I(x, y, z)
Definition: MD5.cpp:54
FunctionType * getFunctionType() const
Definition: Function.cpp:227
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
unsigned MaxStoresPerMemmoveOptSize
Maximum number of store instructions that may be substituted for a call to memmove, used for functions with OpSize attribute.
unsigned MaxStoresPerMemcpyOptSize
Maximum number of store operations that may be substituted for a call to memcpy, used for functions w...
void setStackPointerRegisterToSaveRestore(unsigned R)
If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
unsigned MaxStoresPerMemcpy
Specify maximum bytes of store instructions per memcpy call.
void diagnose(const DiagnosticInfo &DI)
Report a message to the currently installed diagnostic handler.
EVT getValueType() const
Return the ValueType of the referenced return value.
SDValue getConstant(uint64_t Val, SDLoc DL, EVT VT, bool isTarget=false, bool isOpaque=false)
BPFTargetLowering(const TargetMachine &TM, const BPFSubtarget &STI)
unsigned getReg() const
getReg - Returns the register number.
void insert(iterator MBBI, MachineBasicBlock *MBB)
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:465
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
virtual const TargetInstrInfo * getInstrInfo() const
LLVM Value Representation.
Definition: Value.h:69
SDValue getRegister(unsigned Reg, EVT VT)
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
SDValue getValueType(EVT)
BasicBlockListType::iterator iterator
Primary interface to the complete machine description for the target machine.
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:40
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:365
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
unsigned MaxStoresPerMemsetOptSize
Maximum number of stores operations that may be substituted for the call to memset, used for functions with OptSize attribute.
Conversion operators.
Definition: ISDOpcodes.h:380
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:389
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
void addSuccessor(MachineBasicBlock *succ, uint32_t weight=0)
addSuccessor - Add succ as a successor of this MachineBasicBlock.
MVT getSimpleVT() const
getSimpleVT - Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:203
int getKind() const
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:314
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary...
Definition: ISDOpcodes.h:527