LLVM  3.7.0
AMDGPUSubtarget.h
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1 //=====-- AMDGPUSubtarget.h - Define Subtarget for the AMDIL ---*- C++ -*-====//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //==-----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief AMDGPU specific subclass of TargetSubtarget.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_R600_AMDGPUSUBTARGET_H
16 #define LLVM_LIB_TARGET_R600_AMDGPUSUBTARGET_H
17 #include "AMDGPU.h"
18 #include "AMDGPUFrameLowering.h"
19 #include "AMDGPUInstrInfo.h"
20 #include "AMDGPUIntrinsicInfo.h"
21 #include "AMDGPUSubtarget.h"
22 #include "R600ISelLowering.h"
23 #include "AMDKernelCodeT.h"
24 #include "Utils/AMDGPUBaseInfo.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringRef.h"
28 
29 #define GET_SUBTARGETINFO_HEADER
30 #include "AMDGPUGenSubtargetInfo.inc"
31 
32 namespace llvm {
33 
34 class SIMachineFunctionInfo;
35 
37 
38 public:
39  enum Generation {
40  R600 = 0,
47  };
48 
49  enum {
51  };
52 
53  enum {
59  };
60 
61 private:
62  std::string DevName;
63  bool Is64bit;
64  bool DumpCode;
65  bool R600ALUInst;
66  bool HasVertexCache;
67  short TexVTXClauseSize;
68  Generation Gen;
69  bool FP64;
70  bool FP64Denormals;
71  bool FP32Denormals;
72  bool FastFMAF32;
73  bool CaymanISA;
74  bool FlatAddressSpace;
75  bool EnableIRStructurizer;
76  bool EnablePromoteAlloca;
77  bool EnableIfCvt;
78  bool EnableLoadStoreOpt;
79  bool EnableUnsafeDSOffsetFolding;
80  unsigned WavefrontSize;
81  bool CFALUBug;
82  int LocalMemorySize;
83  bool EnableVGPRSpilling;
84  bool SGPRInitBug;
85  bool IsGCN;
86  bool GCN1Encoding;
87  bool GCN3Encoding;
88  bool CIInsts;
89  bool FeatureDisable;
90  int LDSBankCount;
91  unsigned IsaVersion;
92  bool EnableHugeScratchBuffer;
93 
94  AMDGPUFrameLowering FrameLowering;
95  std::unique_ptr<AMDGPUTargetLowering> TLInfo;
96  std::unique_ptr<AMDGPUInstrInfo> InstrInfo;
97  InstrItineraryData InstrItins;
98  Triple TargetTriple;
99 
100 public:
101  AMDGPUSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
102  TargetMachine &TM);
104  StringRef GPU, StringRef FS);
105 
106  const AMDGPUFrameLowering *getFrameLowering() const override {
107  return &FrameLowering;
108  }
109  const AMDGPUInstrInfo *getInstrInfo() const override {
110  return InstrInfo.get();
111  }
112  const AMDGPURegisterInfo *getRegisterInfo() const override {
113  return &InstrInfo->getRegisterInfo();
114  }
116  return TLInfo.get();
117  }
118  const InstrItineraryData *getInstrItineraryData() const override {
119  return &InstrItins;
120  }
121 
123 
124  bool is64bit() const {
125  return Is64bit;
126  }
127 
128  bool hasVertexCache() const {
129  return HasVertexCache;
130  }
131 
132  short getTexVTXClauseSize() const {
133  return TexVTXClauseSize;
134  }
135 
137  return Gen;
138  }
139 
140  bool hasHWFP64() const {
141  return FP64;
142  }
143 
144  bool hasCaymanISA() const {
145  return CaymanISA;
146  }
147 
148  bool hasFP32Denormals() const {
149  return FP32Denormals;
150  }
151 
152  bool hasFP64Denormals() const {
153  return FP64Denormals;
154  }
155 
156  bool hasFastFMAF32() const {
157  return FastFMAF32;
158  }
159 
160  bool hasFlatAddressSpace() const {
161  return FlatAddressSpace;
162  }
163 
164  bool hasBFE() const {
165  return (getGeneration() >= EVERGREEN);
166  }
167 
168  bool hasBFI() const {
169  return (getGeneration() >= EVERGREEN);
170  }
171 
172  bool hasBFM() const {
173  return hasBFE();
174  }
175 
176  bool hasBCNT(unsigned Size) const {
177  if (Size == 32)
178  return (getGeneration() >= EVERGREEN);
179 
180  if (Size == 64)
181  return (getGeneration() >= SOUTHERN_ISLANDS);
182 
183  return false;
184  }
185 
186  bool hasMulU24() const {
187  return (getGeneration() >= EVERGREEN);
188  }
189 
190  bool hasMulI24() const {
191  return (getGeneration() >= SOUTHERN_ISLANDS ||
192  hasCaymanISA());
193  }
194 
195  bool hasFFBL() const {
196  return (getGeneration() >= EVERGREEN);
197  }
198 
199  bool hasFFBH() const {
200  return (getGeneration() >= EVERGREEN);
201  }
202 
203  bool hasCARRY() const {
204  return (getGeneration() >= EVERGREEN);
205  }
206 
207  bool hasBORROW() const {
208  return (getGeneration() >= EVERGREEN);
209  }
210 
211  bool IsIRStructurizerEnabled() const {
212  return EnableIRStructurizer;
213  }
214 
215  bool isPromoteAllocaEnabled() const {
216  return EnablePromoteAlloca;
217  }
218 
219  bool isIfCvtEnabled() const {
220  return EnableIfCvt;
221  }
222 
223  bool loadStoreOptEnabled() const {
224  return EnableLoadStoreOpt;
225  }
226 
228  return EnableUnsafeDSOffsetFolding;
229  }
230 
231  unsigned getWavefrontSize() const {
232  return WavefrontSize;
233  }
234 
235  unsigned getStackEntrySize() const;
236 
237  bool hasCFAluBug() const {
238  assert(getGeneration() <= NORTHERN_ISLANDS);
239  return CFALUBug;
240  }
241 
242  int getLocalMemorySize() const {
243  return LocalMemorySize;
244  }
245 
246  bool hasSGPRInitBug() const {
247  return SGPRInitBug;
248  }
249 
250  int getLDSBankCount() const {
251  return LDSBankCount;
252  }
253 
254  unsigned getAmdKernelCodeChipID() const;
255 
257 
258  bool enableMachineScheduler() const override {
259  return true;
260  }
261 
264  unsigned NumRegionInstrs) const override;
265 
266  // Helper functions to simplify if statements
267  bool isTargetELF() const {
268  return false;
269  }
270 
272  return DevName;
273  }
274 
275  bool enableHugeScratchBuffer() const {
276  return EnableHugeScratchBuffer;
277  }
278 
279  bool dumpCode() const {
280  return DumpCode;
281  }
282  bool r600ALUEncoding() const {
283  return R600ALUInst;
284  }
285  bool isAmdHsaOS() const {
286  return TargetTriple.getOS() == Triple::AMDHSA;
287  }
288  bool isVGPRSpillingEnabled(const SIMachineFunctionInfo *MFI) const;
289 
290  unsigned getMaxWavesPerCU() const {
292  return 10;
293 
294  // FIXME: Not sure what this is for other subtagets.
295  llvm_unreachable("do not know max waves per CU for this subtarget.");
296  }
297 
298  bool enableSubRegLiveness() const override {
299  return true;
300  }
301 
302  /// \brief Returns the offset in bytes from the start of the input buffer
303  /// of the first explicit kernel argument.
304  unsigned getExplicitKernelArgOffset() const {
305  return isAmdHsaOS() ? 0 : 36;
306  }
307 
308 };
309 
310 } // End namespace llvm
311 
312 #endif
OSType getOS() const
getOS - Get the parsed operating system type of this triple.
Definition: Triple.h:251
bool hasCaymanISA() const
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:240
AMDGPU specific subclass of TargetSubtarget.
int getLDSBankCount() const
bool hasFastFMAF32() const
AMDGPUSubtarget & initializeSubtargetDependencies(const Triple &TT, StringRef GPU, StringRef FS)
const_iterator begin(StringRef path)
Get begin iterator over path.
Definition: Path.cpp:232
bool hasVertexCache() const
int getLocalMemorySize() const
bool loadStoreOptEnabled() const
void overrideSchedPolicy(MachineSchedPolicy &Policy, MachineInstr *begin, MachineInstr *end, unsigned NumRegionInstrs) const override
bool r600ALUEncoding() const
bool hasSGPRInitBug() const
unsigned getAmdKernelCodeChipID() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
const InstrItineraryData * getInstrItineraryData() const override
AMDGPUTargetLowering * getTargetLowering() const override
const AMDGPUInstrInfo * getInstrInfo() const override
unsigned getStackEntrySize() const
Interface to describe a layout of a stack frame on a AMDIL target machine.
bool hasFlatAddressSpace() const
Itinerary data supplied by a subtarget to be used by a target.
bool isIfCvtEnabled() const
Generation getGeneration() const
bool IsIRStructurizerEnabled() const
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
short getTexVTXClauseSize() const
unsigned getMaxWavesPerCU() const
bool hasCFAluBug() const
bool hasFP32Denormals() const
AMDGPU::IsaVersion getIsaVersion() const
bool isPromoteAllocaEnabled() const
bool hasFP64Denormals() const
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
unsigned getExplicitKernelArgOffset() const
Returns the offset in bytes from the start of the input buffer of the first explicit kernel argument...
bool enableHugeScratchBuffer() const
bool isTargetELF() const
Interface for the AMDGPU Implementation of the Intrinsic Info class.
bool isAmdHsaOS() const
const AMDGPUFrameLowering * getFrameLowering() const override
bool enableSubRegLiveness() const override
Contains the definition of a TargetInstrInfo class that is common to all AMD GPUs.
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.
Representation of each machine instruction.
Definition: MachineInstr.h:51
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
bool unsafeDSOffsetFoldingEnabled() const
R600 DAG Lowering interface definition.
Information about the stack frame layout on the AMDGPU targets.
unsigned getWavefrontSize() const
StringRef getDeviceName() const
Primary interface to the complete machine description for the target machine.
AMDGPUSubtarget(const Triple &TT, StringRef CPU, StringRef FS, TargetMachine &TM)
bool hasBCNT(unsigned Size) const
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:40
bool isVGPRSpillingEnabled(const SIMachineFunctionInfo *MFI) const
bool enableMachineScheduler() const override
const AMDGPURegisterInfo * getRegisterInfo() const override