32 using namespace Hexagon;
34 #define DEBUG_TYPE "hexagon-disassembler"
43 std::unique_ptr<MCInst *> CurrentBundle;
50 bool &Complete)
const;
101 Hexagon::R5,
Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9,
102 Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,
103 Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
104 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24,
105 Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29,
106 Hexagon::R30, Hexagon::R31};
109 Hexagon::P2, Hexagon::P3};
112 const uint16_t Table[],
size_t Size) {
122 void const *Decoder) {
133 const void *Decoder) {
134 static const uint16_t CtrlRegDecoderTable[] = {
135 Hexagon::SA0, Hexagon::LC0, Hexagon::SA1, Hexagon::LC1,
136 Hexagon::P3_0, Hexagon::NoRegister, Hexagon::C6, Hexagon::C7,
137 Hexagon::USR, Hexagon::PC, Hexagon::UGP, Hexagon::GP,
138 Hexagon::CS0, Hexagon::CS1, Hexagon::UPCL, Hexagon::UPCH};
140 if (RegNo >=
sizeof(CtrlRegDecoderTable) /
sizeof(CtrlRegDecoderTable[0]))
143 if (CtrlRegDecoderTable[RegNo] == Hexagon::NoRegister)
146 unsigned Register = CtrlRegDecoderTable[RegNo];
153 void const *Decoder) {
154 static const uint16_t CtrlReg64DecoderTable[] = {
155 Hexagon::C1_0, Hexagon::NoRegister, Hexagon::C3_2,
156 Hexagon::NoRegister, Hexagon::NoRegister, Hexagon::NoRegister,
157 Hexagon::C7_6, Hexagon::NoRegister, Hexagon::C9_8,
158 Hexagon::NoRegister, Hexagon::C11_10, Hexagon::NoRegister,
159 Hexagon::CS, Hexagon::NoRegister, Hexagon::UPC,
160 Hexagon::NoRegister};
162 if (RegNo >=
sizeof(CtrlReg64DecoderTable) /
sizeof(CtrlReg64DecoderTable[0]))
165 if (CtrlReg64DecoderTable[RegNo] == Hexagon::NoRegister)
168 unsigned Register = CtrlReg64DecoderTable[RegNo];
175 const void *Decoder) {
179 Register = Hexagon::M0;
182 Register = Hexagon::M1;
193 const void *Decoder) {
194 static const uint16_t DoubleRegDecoderTable[] = {
195 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,
196 Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7,
197 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11,
198 Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15};
201 sizeof(DoubleRegDecoderTable)));
206 void const *Decoder) {
215 #include "HexagonGenDisassemblerTables.inc"
220 return new HexagonDisassembler(STI, Ctx);
234 bool Complete =
false;
237 *CurrentBundle = &
MI;
240 while (Result == Success && Complete ==
false) {
244 Result = getSingleInstruction(*Inst, MI, Bytes, Address, os, cs, Complete);
266 else if (BundleSize == 1)
273 if ((Instruction & HexagonII::INST_PARSE_MASK) ==
276 unsigned duplexIClass, IClassLow, IClassHigh;
278 duplexIClass = ((Instruction >> 28) & 0xe) | ((Instruction >> 13) & 0x1);
279 switch (duplexIClass) {
349 unsigned instLow = Instruction & 0x1fff;
350 unsigned instHigh = (Instruction >> 16) & 0x1fff;
375 if ((Instruction & HexagonII::INST_PARSE_MASK) ==
387 uint64_t ,
const void *Decoder) {
388 uint64_t imm = SignExtend64<16>(tmp);
394 uint64_t ,
const void *Decoder) {
395 uint64_t imm = SignExtend64<12>(tmp);
401 uint64_t ,
const void *Decoder) {
402 uint64_t imm = SignExtend64<11>(tmp);
408 uint64_t ,
const void *Decoder) {
409 uint64_t imm = SignExtend64<12>(tmp);
415 uint64_t ,
const void *Decoder) {
416 uint64_t imm = SignExtend64<13>(tmp);
422 uint64_t ,
const void *Decoder) {
423 uint64_t imm = SignExtend64<14>(tmp);
429 uint64_t ,
const void *Decoder) {
430 uint64_t imm = SignExtend64<10>(tmp);
436 const void *Decoder) {
437 uint64_t imm = SignExtend64<8>(tmp);
443 uint64_t ,
const void *Decoder) {
444 uint64_t imm = SignExtend64<6>(tmp);
450 uint64_t ,
const void *Decoder) {
451 uint64_t imm = SignExtend64<4>(tmp);
457 uint64_t ,
const void *Decoder) {
458 uint64_t imm = SignExtend64<5>(tmp);
464 uint64_t ,
const void *Decoder) {
465 uint64_t imm = SignExtend64<6>(tmp);
471 uint64_t ,
const void *Decoder) {
472 uint64_t imm = SignExtend64<7>(tmp);
590 op = Hexagon::V4_SL1_loadri_io;
592 op = Hexagon::V4_SL1_loadrub_io;
594 os <<
"<unknown subinstruction>";
600 op = Hexagon::V4_SL2_deallocframe;
602 op = Hexagon::V4_SL2_jumpr31;
604 op = Hexagon::V4_SL2_jumpr31_f;
606 op = Hexagon::V4_SL2_jumpr31_fnew;
608 op = Hexagon::V4_SL2_jumpr31_t;
610 op = Hexagon::V4_SL2_jumpr31_tnew;
612 op = Hexagon::V4_SL2_loadrb_io;
614 op = Hexagon::V4_SL2_loadrd_sp;
616 op = Hexagon::V4_SL2_loadrh_io;
618 op = Hexagon::V4_SL2_loadri_sp;
620 op = Hexagon::V4_SL2_loadruh_io;
622 op = Hexagon::V4_SL2_return;
624 op = Hexagon::V4_SL2_return_f;
626 op = Hexagon::V4_SL2_return_fnew;
628 op = Hexagon::V4_SL2_return_t;
630 op = Hexagon::V4_SL2_return_tnew;
632 os <<
"<unknown subinstruction>";
638 op = Hexagon::V4_SA1_addi;
640 op = Hexagon::V4_SA1_addrx;
642 op = Hexagon::V4_SA1_addsp;
644 op = Hexagon::V4_SA1_and1;
646 op = Hexagon::V4_SA1_clrf;
648 op = Hexagon::V4_SA1_clrfnew;
650 op = Hexagon::V4_SA1_clrt;
652 op = Hexagon::V4_SA1_clrtnew;
654 op = Hexagon::V4_SA1_cmpeqi;
656 op = Hexagon::V4_SA1_combine0i;
658 op = Hexagon::V4_SA1_combine1i;
660 op = Hexagon::V4_SA1_combine2i;
662 op = Hexagon::V4_SA1_combine3i;
664 op = Hexagon::V4_SA1_combinerz;
666 op = Hexagon::V4_SA1_combinezr;
668 op = Hexagon::V4_SA1_dec;
670 op = Hexagon::V4_SA1_inc;
672 op = Hexagon::V4_SA1_seti;
674 op = Hexagon::V4_SA1_setin1;
676 op = Hexagon::V4_SA1_sxtb;
678 op = Hexagon::V4_SA1_sxth;
680 op = Hexagon::V4_SA1_tfr;
682 op = Hexagon::V4_SA1_zxtb;
684 op = Hexagon::V4_SA1_zxth;
686 os <<
"<unknown subinstruction>";
692 op = Hexagon::V4_SS1_storeb_io;
694 op = Hexagon::V4_SS1_storew_io;
696 os <<
"<unknown subinstruction>";
702 op = Hexagon::V4_SS2_allocframe;
704 op = Hexagon::V4_SS2_storebi0;
706 op = Hexagon::V4_SS2_storebi1;
708 op = Hexagon::V4_SS2_stored_sp;
710 op = Hexagon::V4_SS2_storeh_io;
712 op = Hexagon::V4_SS2_storew_sp;
714 op = Hexagon::V4_SS2_storewi0;
716 op = Hexagon::V4_SS2_storewi1;
718 os <<
"<unknown subinstruction>";
731 return Hexagon::R0 + encoded_reg;
732 else if (encoded_reg < 16)
733 return Hexagon::R0 + encoded_reg + 8;
734 return Hexagon::NoRegister;
738 if (encoded_dreg < 4)
739 return Hexagon::D0 + encoded_dreg;
740 else if (encoded_dreg < 8)
741 return Hexagon::D0 + encoded_dreg + 4;
742 return Hexagon::NoRegister;
749 case Hexagon::V4_SL2_deallocframe:
750 case Hexagon::V4_SL2_jumpr31:
751 case Hexagon::V4_SL2_jumpr31_f:
752 case Hexagon::V4_SL2_jumpr31_fnew:
753 case Hexagon::V4_SL2_jumpr31_t:
754 case Hexagon::V4_SL2_jumpr31_tnew:
755 case Hexagon::V4_SL2_return:
756 case Hexagon::V4_SL2_return_f:
757 case Hexagon::V4_SL2_return_fnew:
758 case Hexagon::V4_SL2_return_t:
759 case Hexagon::V4_SL2_return_tnew:
762 case Hexagon::V4_SS2_allocframe:
764 operand = ((inst & 0x1f0) >> 4) << 3;
768 case Hexagon::V4_SL1_loadri_io:
776 operand = (inst & 0xf00) >> 6;
780 case Hexagon::V4_SL1_loadrub_io:
788 operand = (inst & 0xf00) >> 8;
792 case Hexagon::V4_SL2_loadrb_io:
800 operand = (inst & 0x700) >> 8;
804 case Hexagon::V4_SL2_loadrh_io:
805 case Hexagon::V4_SL2_loadruh_io:
813 operand = ((inst & 0x700) >> 8) << 1;
817 case Hexagon::V4_SL2_loadrd_sp:
822 operand = ((inst & 0x0f8) >> 3) << 3;
826 case Hexagon::V4_SL2_loadri_sp:
831 operand = ((inst & 0x1f0) >> 4) << 2;
835 case Hexagon::V4_SA1_addi:
841 operand = SignExtend64<7>((inst & 0x7f0) >> 4);
845 case Hexagon::V4_SA1_addrx:
854 case Hexagon::V4_SA1_and1:
855 case Hexagon::V4_SA1_dec:
856 case Hexagon::V4_SA1_inc:
857 case Hexagon::V4_SA1_sxtb:
858 case Hexagon::V4_SA1_sxth:
859 case Hexagon::V4_SA1_tfr:
860 case Hexagon::V4_SA1_zxtb:
861 case Hexagon::V4_SA1_zxth:
870 case Hexagon::V4_SA1_addsp:
875 operand = ((inst & 0x3f0) >> 4) << 2;
879 case Hexagon::V4_SA1_seti:
884 operand = (inst & 0x3f0) >> 4;
888 case Hexagon::V4_SA1_clrf:
889 case Hexagon::V4_SA1_clrfnew:
890 case Hexagon::V4_SA1_clrt:
891 case Hexagon::V4_SA1_clrtnew:
892 case Hexagon::V4_SA1_setin1:
898 case Hexagon::V4_SA1_cmpeqi:
903 operand = inst & 0x3;
907 case Hexagon::V4_SA1_combine0i:
908 case Hexagon::V4_SA1_combine1i:
909 case Hexagon::V4_SA1_combine2i:
910 case Hexagon::V4_SA1_combine3i:
915 operand = (inst & 0x060) >> 5;
919 case Hexagon::V4_SA1_combinerz:
920 case Hexagon::V4_SA1_combinezr:
929 case Hexagon::V4_SS1_storeb_io:
934 operand = (inst & 0xf00) >> 8;
941 case Hexagon::V4_SS1_storew_io:
946 operand = ((inst & 0xf00) >> 8) << 2;
953 case Hexagon::V4_SS2_storebi0:
954 case Hexagon::V4_SS2_storebi1:
959 operand = inst & 0xf;
963 case Hexagon::V4_SS2_storewi0:
964 case Hexagon::V4_SS2_storewi1:
969 operand = (inst & 0xf) << 2;
973 case Hexagon::V4_SS2_stored_sp:
975 operand = SignExtend64<9>(((inst & 0x1f8) >> 3) << 3);
981 case Hexagon::V4_SS2_storeh_io:
986 operand = ((inst & 0x700) >> 8) << 1;
993 case Hexagon::V4_SS2_storew_sp:
995 operand = ((inst & 0x1f0) >> 4) << 2;
static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
value_type read(const void *memory)
Read a value of a particular endianness from memory.
DecodeStatus
Ternary decode status.
Superclass for all disassemblers.
static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t, const void *Decoder)
static DecodeStatus s11_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
static DecodeStatus s11_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
void setInnerLoop(MCInst &MCI)
static MCOperand createReg(unsigned Reg)
llvm::MCDisassembler::DecodeStatus DecodeStatus
static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo, const uint16_t Table[], size_t Size)
static DecodeStatus s11_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
static DecodeStatus s12ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
Context object for machine code objects.
static const uint16_t IntRegDecoderTable[]
static DecodeStatus s10ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
int decodeInstruction(InternalInstruction *insn, byteReader_t reader, const void *readerArg, dlog_t logger, void *loggerArg, const void *miiArg, uint64_t startLoc, DisassemblerMode mode)
Decode one instruction and store the decoding results in a buffer provided by the consumer...
ArrayRef< T > slice(unsigned N) const
slice(n) - Chop off the first N elements of the array.
size_t size() const
size - Get the array size.
static unsigned getRegFromSubinstEncoding(unsigned encoded_reg)
Instances of this class represent a single low-level machine instruction.
static unsigned getDRegFromSubinstEncoding(unsigned encoded_dreg)
static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t, void const *Decoder)
static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
static const uint16_t PredRegDecoderTable[]
static void AddSubinstOperands(MCInst *MI, unsigned opcode, unsigned inst)
static DecodeStatus s11_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
static unsigned GetSubinstOpcode(unsigned IClass, unsigned inst, unsigned &op, raw_ostream &os)
void setOuterLoop(MCInst &MCI)
static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
void LLVMInitializeHexagonDisassembler()
void setOpcode(unsigned Op)
Promote Memory to Register
BUNDLE - This instruction represents an instruction bundle.
static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
Target - Wrapper for Target specific information.
static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
static MCOperand createInst(const MCInst *Val)
static MCDisassembler * createHexagonDisassembler(Target const &T, MCSubtargetInfo const &STI, MCContext &Ctx)
static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus s16ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
MCSubtargetInfo - Generic base class for all target subtargets.
size_t bundleSize(MCInst const &MCI)
#define HEXAGON_INSTR_SIZE
static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, void const *Decoder)
This class implements an extremely fast bulk output stream that can only output to a stream...
void addOperand(const MCOperand &Op)
static DecodeStatus s8ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
Instances of this class represent operands of the MCInst class.
static MCOperand createImm(int64_t Val)
static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t, void const *Decoder)