75 printv(
unsigned r) : R(r) {}
106 unsigned n = RC.Bits.
size();
114 bool ConstRef =
false;
116 for (
unsigned i = 1, n = RC.Bits.
size(); i < n; ++i) {
121 if (!IsRef && V == SV)
137 unsigned Count = i - Start;
141 OS <<
'-' << i-1 <<
"]:";
144 << SV.
RefI.
Pos+(Count-1) <<
']';
149 SeqRef = ConstRef =
false;
153 unsigned Count = n - Start;
155 OS <<
"]:" << RC[Start];
157 OS <<
'-' << n-1 <<
"]:";
161 << SV.
RefI.
Pos+(Count-1) <<
']';
188 bool Changed =
false;
189 for (uint16_t i = 0, n = Bits.
size(); i < n; ++i) {
191 Changed |= Bits[i].meet(RCV,
BitRef(SelfR, i));
202 assert(B < W && E < W);
205 assert(B > E || E-B+1 == RC.
width());
206 assert(B <= E || E+(W-B)+1 == RC.
width());
208 for (uint16_t i = 0; i <= E-B; ++i)
211 for (uint16_t i = 0; i < W-B; ++i)
213 for (uint16_t i = 0; i <= E; ++i)
214 Bits[i] = RC[i+(W-B)];
222 assert(B < W && E < W);
225 for (uint16_t i = B; i <= E; ++i)
226 RC.Bits[i-B] = Bits[i];
231 for (uint16_t i = 0; i < W-B; ++i)
232 RC.Bits[i] = Bits[i+B];
233 for (uint16_t i = 0; i <= E; ++i)
234 RC.Bits[i+(W-B)] = Bits[i];
242 uint16_t W =
width();
249 for (uint16_t i = 0; i < W-Sh; ++i)
252 for (uint16_t i = 0; i < Sh; ++i)
253 Bits[i] = Bits[W-Sh+i];
255 for (uint16_t i = 0; i < W-Sh; ++i)
256 Bits[i+Sh] = Tmp.Bits[i];
275 for (uint16_t i = 0; i < WRC; ++i)
276 Bits[i+W] = RC.Bits[i];
282 uint16_t W =
width();
285 while (C < W && Bits[C] == V)
292 uint16_t W =
width();
295 while (C < W && Bits[W-(C+1)] == V)
302 uint16_t W = Bits.
size();
303 if (RC.Bits.
size() != W)
305 for (uint16_t i = 0; i < W; ++i)
306 if (Bits[i] != RC[i])
324 assert(VC->
begin() != VC->
end() &&
"Empty register class");
325 PhysR = *VC->
begin();
354 CellMapType::const_iterator
F = M.find(RR.
Reg);
359 return F->second.extract(M);
373 assert(RR.
Sub == 0 &&
"Unexpected sub-register in definition");
375 for (
unsigned i = 0, n = RC.
width(); i < n; ++i) {
386 uint16_t W = A.
width();
387 for (uint16_t i = 0; i < W; ++i)
388 if (!A[i].is(0) && !A[i].is(1))
398 uint16_t W = A.
width();
399 for (uint16_t i = 0; i < W; ++i) {
414 for (uint16_t i = 0; i < W; ++i) {
425 assert((
unsigned)BW == A.
getBitWidth() &&
"BitWidth overflow");
427 for (uint16_t i = 0; i < BW; ++i)
435 uint16_t W = A1.
width();
436 assert(W == A2.
width());
440 for (I = 0; I < W; ++
I) {
443 if (!V1.
num() || !V2.
num())
445 unsigned S =
bool(V1) +
bool(V2) + Carry;
456 else if (V2.
is(Carry))
469 uint16_t W = A1.
width();
470 assert(W == A2.
width());
474 for (I = 0; I < W; ++
I) {
477 if (!V1.
num() || !V2.
num())
479 unsigned S =
bool(V1) -
bool(V2) - Borrow;
504 uint16_t Z = A1.
ct(0) + A2.
ct(0);
515 uint16_t Z = A1.
ct(0) + A2.
ct(0);
525 assert(Sh <= A1.
width());
535 uint16_t W = A1.
width();
546 uint16_t W = A1.
width();
551 Res.
fill(W-Sh, W, Sign);
558 uint16_t W = A1.
width();
559 assert(W == A2.
width());
561 for (uint16_t i = 0; i < W; ++i) {
568 else if (V1.
is(0) || V2.
is(0))
581 uint16_t W = A1.
width();
582 assert(W == A2.
width());
584 for (uint16_t i = 0; i < W; ++i) {
587 if (V1.
is(1) || V2.
is(1))
604 uint16_t W = A1.
width();
605 assert(W == A2.
width());
607 for (uint16_t i = 0; i < W; ++i) {
624 uint16_t W = A1.
width();
626 for (uint16_t i = 0; i < W; ++i) {
640 uint16_t BitN)
const {
641 assert(BitN < A1.
width());
649 uint16_t BitN)
const {
650 assert(BitN < A1.
width());
659 uint16_t
C = A1.
cl(B), AW = A1.
width();
662 if ((C < AW && A1[AW-1-C].num()) || C == AW)
670 uint16_t
C = A1.
ct(B), AW = A1.
width();
673 if ((C < AW && A1[C].num()) || C == AW)
680 uint16_t FromN)
const {
681 uint16_t W = A1.
width();
686 Res.
fill(FromN, W, Sign);
692 uint16_t FromN)
const {
693 uint16_t W = A1.
width();
702 uint16_t B, uint16_t E)
const {
703 uint16_t W = A1.
width();
704 assert(B < W && E <= W);
707 uint16_t Last = (E > 0) ? E-1 : W-1;
718 assert(AtN < W1 && AtN+W2 <= W1);
728 assert(Sub == 0 &&
"Generic BitTracker::mask called for Sub != 0");
730 assert(W > 0 &&
"Cannot generate mask for empty register");
786 dbgs() <<
"Visit FI(BB#" << ThisN <<
"): " << *PI;
789 assert(MD.
getSubReg() == 0 &&
"Unexpected sub-register in definition");
797 bool Changed =
false;
799 for (
unsigned i = 1, n = PI->getNumOperands(); i < n; i += 2) {
803 dbgs() <<
" edge BB#" << PredN <<
"->BB#" << ThisN;
804 if (!EdgeExec.count(CFGEdge(PredN, ThisN))) {
806 dbgs() <<
" not executable\n";
810 RegisterRef RU = PI->getOperand(i);
811 RegisterCell ResC = ME.
getCell(RU, Map);
814 <<
" cell: " << ResC <<
"\n";
815 Changed |= DefC.
meet(ResC, DefRR.Reg);
821 <<
" cell: " << DefC <<
"\n";
823 visitUsesOf(DefRR.Reg);
831 dbgs() <<
"Visit MI(BB#" << ThisN <<
"): " << *
MI;
835 assert(!MI->
isBranch() &&
"Unexpected branch instruction");
847 <<
" cell: " << ME.
getCell(RU, Map) <<
"\n";
849 dbgs() <<
"Outputs:\n";
850 for (CellMapType::iterator
I = ResMap.begin(), E = ResMap.end();
852 RegisterRef RD(
I->first);
854 << ME.
getCell(RD, ResMap) <<
"\n";
866 assert(RD.Sub == 0 &&
"Unexpected sub-register in definition");
870 bool Changed =
false;
871 if (!Eval || !ResMap.has(RD.Reg)) {
875 if (RefC != ME.
getCell(RD, Map)) {
880 RegisterCell DefC = ME.
getCell(RD, Map);
881 RegisterCell ResC = ME.
getCell(RD, ResMap);
889 for (uint16_t i = 0, w = DefC.width(); i < w; ++i) {
890 BitValue &V = DefC[i];
913 bool FallsThrough =
true, DefaultToAll =
false;
920 dbgs() <<
"Visit BR(BB#" << ThisN <<
"): " << *
MI;
921 assert(MI->isBranch() &&
"Expecting branch instruction");
922 InstrExec.insert(MI);
923 bool Eval = ME.
evaluate(MI, Map, BTs, FallsThrough);
930 dbgs() <<
" failed to evaluate: will add all CFG successors\n";
931 }
else if (!DefaultToAll) {
934 dbgs() <<
" adding targets:";
935 for (
unsigned i = 0, n = BTs.size(); i < n; ++i)
936 dbgs() <<
" BB#" << BTs[i]->getNumber();
938 dbgs() <<
"\n falls through\n";
940 dbgs() <<
"\n does not fall through\n";
942 Targets.insert(BTs.begin(), BTs.end());
945 }
while (FallsThrough && It != End);
960 if (Next != MF.
end())
961 Targets.insert(&*Next);
968 for (
unsigned i = 0, n = Targets.size(); i < n; ++i) {
969 int TargetN = Targets[i]->getNumber();
970 FlowQ.push(CFGEdge(ThisN, TargetN));
975 void BT::visitUsesOf(
unsigned Reg) {
983 if (!InstrExec.count(UseI))
988 visitNonBranch(UseI);
990 visitBranchesFrom(UseI);
1008 assert(Map.
has(OldRR.
Reg) &&
"OldRR not present in map");
1011 uint16_t OMB = OM.
first(), OME = OM.last();
1012 uint16_t NMB = NM.
first(), NME = NM.
last();
1014 assert((OME-OMB == NME-NMB) &&
1015 "Substituting registers of different lengths");
1016 for (CellMapType::iterator
I = Map.begin(), E = Map.end();
I != E; ++
I) {
1018 for (uint16_t i = 0, w = RC.
width(); i < w; ++i) {
1036 for (EdgeSetType::iterator
I = EdgeExec.begin(), E = EdgeExec.end();
1038 if (
I->second == BN)
1054 assert(FlowQ.empty());
1062 assert(
I->getNumber() >= 0 &&
"Disconnected block");
1063 unsigned BN =
I->getNumber();
1073 FlowQ.push(CFGEdge(-1, EntryN));
1075 while (!FlowQ.empty()) {
1076 CFGEdge Edge = FlowQ.front();
1079 if (EdgeExec.count(Edge))
1081 EdgeExec.insert(Edge);
1086 while (It != End && It->isPHI()) {
1088 InstrExec.insert(PI);
1095 if (BlockScanned[Edge.second])
1097 BlockScanned[Edge.second] =
true;
1100 while (It != End && !It->isBranch()) {
1102 InstrExec.insert(MI);
1109 if (Next != MF.
end()) {
1111 int NextN = Next->getNumber();
1112 FlowQ.push(CFGEdge(ThisN, NextN));
1117 visitBranchesFrom(It);
1122 dbgs() <<
"Cells after propagation:\n";
1123 for (CellMapType::iterator
I = Map.begin(), E = Map.end();
I != E; ++
I)
virtual bool evaluate(const MachineInstr *MI, const CellMapType &Inputs, CellMapType &Outputs) const
const TargetRegisterInfo & TRI
RegisterCell & fill(uint16_t B, uint16_t E, const BitValue &V)
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
static unsigned virtReg2Index(unsigned Reg)
virtReg2Index - Convert a virtual register number to a 0-based index.
bool isInt(const RegisterCell &A) const
RegisterCell eCLR(const RegisterCell &A1, uint16_t BitN) const
int getNumber() const
getNumber - MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a M...
static RegisterCell top(uint16_t Width)
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
RegisterCell eASR(const RegisterCell &A1, uint16_t Sh) const
static RegisterCell self(unsigned Reg, uint16_t Width)
RegisterCell & rol(uint16_t Sh)
uint16_t getRegBitWidth(const RegisterRef &RR) const
RegisterCell eXOR(const RegisterCell &A1, const RegisterCell &A2) const
uint16_t ct(bool B) const
RegisterCell eAND(const RegisterCell &A1, const RegisterCell &A2) const
static use_nodbg_iterator use_nodbg_end()
COPY - Target-independent register copy.
void putCell(const RegisterRef &RR, RegisterCell RC, CellMapType &M) const
RegisterCell eXTR(const RegisterCell &A1, uint16_t B, uint16_t E) const
unsigned getSize() const
getSize - Return the size of the register in bytes, which is also the size of a stack slot allocated ...
const APInt & getValue() const
Return the constant as an APInt value reference.
uint64_t toInt(const RegisterCell &A) const
RegisterCell extract(const BitMask &M) const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
const TargetRegisterClass * getRegClass(unsigned Reg) const
getRegClass - Return the register class of the specified virtual register.
RegisterCell get(RegisterRef RR) const
iterator begin() const
begin/end - Return all of the registers in this class.
Reg
All possible values of the reg field in the ModR/M byte.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
RegisterCell eMLS(const RegisterCell &A1, const RegisterCell &A2) const
PrintReg - Helper class for printing registers on a raw_ostream.
bool is(unsigned T) const
RegisterCell eSUB(const RegisterCell &A1, const RegisterCell &A2) const
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineBasicBlock * getParent() const
bool isDebugValue() const
SuccIterator< TerminatorInst *, BasicBlock > succ_iterator
RegisterCell eSXT(const RegisterCell &A1, uint16_t FromN) const
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const MachineOperand & getOperand(unsigned i) const
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
RegisterCell eASL(const RegisterCell &A1, uint16_t Sh) const
unsigned getBitWidth() const
Return the number of bits in the APInt.
RegisterCell getCell(const RegisterRef &RR, const CellMapType &M) const
for(unsigned i=0, e=MI->getNumOperands();i!=e;++i)
void subst(RegisterRef OldRR, RegisterRef NewRR)
RegisterCell eCTB(const RegisterCell &A1, bool B, uint16_t W) const
RegisterCell eZXT(const RegisterCell &A1, uint16_t FromN) const
bool has(unsigned Reg) const
RegisterCell eCLB(const RegisterCell &A1, bool B, uint16_t W) const
succ_iterator succ_begin()
unsigned getSubReg() const
RegisterCell eADD(const RegisterCell &A1, const RegisterCell &A2) const
SetVector< const MachineBasicBlock * > BranchTargetList
REG_SEQUENCE - This variadic instruction is used to form a register that represents a consecutive seq...
RegisterCell eORL(const RegisterCell &A1, const RegisterCell &A2) const
This is the shared class of boolean and integer constants.
static BitValue self(const BitRef &Self=BitRef())
MachineOperand class - Representation of each machine instruction operand.
MachineBasicBlock * getBlockNumbered(unsigned N) const
getBlockNumbered - MachineBasicBlocks are automatically numbered when they are inserted into the mach...
RegisterCell eLSR(const RegisterCell &A1, uint16_t Sh) const
MachineRegisterInfo & MRI
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Class for arbitrary precision integers.
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
getMinimalPhysRegClass - Returns the Register Class of a physical register of the given type...
RegisterCell & insert(const RegisterCell &RC, const BitMask &M)
Representation of each machine instruction.
bundle_iterator< const MachineInstr, const_instr_iterator > const_iterator
static bool isPhysicalRegister(unsigned Reg)
isPhysicalRegister - Return true if the specified register number is in the physical register namespa...
bool isLandingPad() const
isLandingPad - Returns true if the block is a landing pad.
virtual BitMask mask(unsigned Reg, unsigned Sub) const
RegisterCell & cat(const RegisterCell &RC)
virtual bool track(const TargetRegisterClass *RC) const
BitTracker(const MachineEvaluator &E, MachineFunction &F)
uint16_t cl(bool B) const
RegisterCell eMLU(const RegisterCell &A1, const RegisterCell &A2) const
GraphT::NodeType * Eval(DominatorTreeBase< typename GraphT::NodeType > &DT, typename GraphT::NodeType *VIn, unsigned LastLinked)
RegisterCell eIMM(int64_t V, uint16_t W) const
bool operator==(const RegisterCell &RC) const
raw_ostream & operator<<(raw_ostream &OS, const APInt &I)
bool reached(const MachineBasicBlock *B) const
std::vector< MachineBasicBlock * >::const_iterator const_succ_iterator
void put(RegisterRef RR, const RegisterCell &RC)
RegisterCell eSET(const RegisterCell &A1, uint16_t BitN) const
RegisterCell eNOT(const RegisterCell &A1) const
This class implements an extremely fast bulk output stream that can only output to a stream...
bool meet(const RegisterCell &RC, unsigned SelfR)
static RegisterCell ref(const RegisterCell &C)
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const
static BitValue ref(const BitValue &V)
RegisterCell eINS(const RegisterCell &A1, const RegisterCell &A2, uint16_t AtN) const