|
| cl::opt< bool > | llvm::ForceTopDown ("misched-topdown", cl::Hidden, cl::desc("Force top-down list scheduling")) |
| |
| cl::opt< bool > | llvm::ForceBottomUp ("misched-bottomup", cl::Hidden, cl::desc("Force bottom-up list scheduling")) |
| |
| | INITIALIZE_PASS_BEGIN (MachineScheduler,"machine-scheduler","Machine Instruction Scheduler", false, false) INITIALIZE_PASS_END(MachineScheduler |
| |
| | INITIALIZE_PASS (PostMachineScheduler,"postmisched","PostRA Machine Instruction Scheduler", false, false) PostMachineScheduler |
| |
| static ScheduleDAGInstrs * | useDefaultMachineSched (MachineSchedContext *C) |
| | A dummy default scheduler factory indicates whether the scheduler is overridden on the command line. More...
|
| |
| static ScheduleDAGInstrs * | createGenericSchedLive (MachineSchedContext *C) |
| | Forward declare the standard machine scheduler. More...
|
| |
| static ScheduleDAGInstrs * | createGenericSchedPostRA (MachineSchedContext *C) |
| | Create a generic scheduler with no vreg liveness or DAG mutation passes. More...
|
| |
static
MachineBasicBlock::const_iterator | priorNonDebug (MachineBasicBlock::const_iterator I, MachineBasicBlock::const_iterator Beg) |
| | Decrement this iterator until reaching the top or a non-debug instr. More...
|
| |
| static MachineBasicBlock::iterator | priorNonDebug (MachineBasicBlock::iterator I, MachineBasicBlock::const_iterator Beg) |
| | Non-const version. More...
|
| |
static
MachineBasicBlock::const_iterator | nextIfDebug (MachineBasicBlock::const_iterator I, MachineBasicBlock::const_iterator End) |
| | If this iterator is a debug value, increment until reaching the End or a non-debug instruction. More...
|
| |
| static MachineBasicBlock::iterator | nextIfDebug (MachineBasicBlock::iterator I, MachineBasicBlock::const_iterator End) |
| | Non-const version. More...
|
| |
| static bool | isSchedBoundary (MachineBasicBlock::iterator MI, MachineBasicBlock *MBB, MachineFunction *MF, const TargetInstrInfo *TII, bool IsPostRA) |
| | Return true of the given instruction should not be included in a scheduling region. More...
|
| |
| static bool | tryLess (int TryVal, int CandVal, GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, GenericSchedulerBase::CandReason Reason) |
| | Return true if this heuristic determines order. More...
|
| |
| static bool | tryGreater (int TryVal, int CandVal, GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, GenericSchedulerBase::CandReason Reason) |
| |
| static bool | tryLatency (GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, SchedBoundary &Zone) |
| |
| static void | tracePick (const GenericSchedulerBase::SchedCandidate &Cand, bool IsTop) |
| |
| static bool | tryPressure (const PressureChange &TryP, const PressureChange &CandP, GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, GenericSchedulerBase::CandReason Reason) |
| |
| static unsigned | getWeakLeft (const SUnit *SU, bool isTop) |
| |
| static int | biasPhysRegCopy (const SUnit *SU, bool isTop) |
| | Minimize physical register live ranges. More...
|
| |
| static ScheduleDAGInstrs * | createILPMaxScheduler (MachineSchedContext *C) |
| |
| static ScheduleDAGInstrs * | createILPMinScheduler (MachineSchedContext *C) |
| |
| static ScheduleDAGInstrs * | createInstructionShuffler (MachineSchedContext *C) |
| |
|
| cl::opt< bool > | llvm::DumpCriticalPathLength ("misched-dcpl", cl::Hidden, cl::desc("Print critical path length to stdout")) |
| |
| static cl::opt< bool > | ViewMISchedDAGs ("view-misched-dags", cl::Hidden, cl::desc("Pop up a window to show MISched dags after they are processed")) |
| |
| static cl::opt< unsigned > | MISchedCutoff ("misched-cutoff", cl::Hidden, cl::desc("Stop scheduling after N instructions"), cl::init(~0U)) |
| |
| static cl::opt< std::string > | SchedOnlyFunc ("misched-only-func", cl::Hidden, cl::desc("Only schedule this function")) |
| |
| static cl::opt< unsigned > | SchedOnlyBlock ("misched-only-block", cl::Hidden, cl::desc("Only schedule this MBB#")) |
| |
| static cl::opt< bool > | EnableRegPressure ("misched-regpressure", cl::Hidden, cl::desc("Enable register pressure scheduling."), cl::init(true)) |
| |
| static cl::opt< bool > | EnableCyclicPath ("misched-cyclicpath", cl::Hidden, cl::desc("Enable cyclic critical path analysis."), cl::init(true)) |
| |
| static cl::opt< bool > | EnableLoadCluster ("misched-cluster", cl::Hidden, cl::desc("Enable load clustering."), cl::init(true)) |
| |
| static cl::opt< bool > | EnableMacroFusion ("misched-fusion", cl::Hidden, cl::desc("Enable scheduling for macro fusion."), cl::init(true)) |
| |
| static cl::opt< bool > | VerifyScheduling ("verify-misched", cl::Hidden, cl::desc("Verify machine instrs before and after machine scheduling")) |
| |
| static const unsigned | MinSubtreeSize = 8 |
| |
| machine | scheduler |
| |
| machine Machine Instruction | Scheduler |
| |
| machine Machine Instruction | false |
| |
static cl::opt
< MachineSchedRegistry::ScheduleDAGCtor,
false, RegisterPassParser
< MachineSchedRegistry > > | MachineSchedOpt ("misched", cl::init(&useDefaultMachineSched), cl::Hidden, cl::desc("Machine instruction scheduler to use")) |
| | MachineSchedOpt allows command line selection of the scheduler. More...
|
| |
| static MachineSchedRegistry | DefaultSchedRegistry ("default","Use the target's default scheduler choice.", useDefaultMachineSched) |
| |
| static cl::opt< bool > | EnableMachineSched ("enable-misched", cl::desc("Enable the machine instruction scheduling pass."), cl::init(true), cl::Hidden) |
| |
| static const unsigned | InvalidCycle = ~0U |
| |
| static MachineSchedRegistry | GenericSchedRegistry ("converge","Standard converging scheduler.", createGenericSchedLive) |
| |
| static MachineSchedRegistry | ILPMaxRegistry ("ilpmax","Schedule bottom-up for max ILP", createILPMaxScheduler) |
| |
| static MachineSchedRegistry | ILPMinRegistry ("ilpmin","Schedule bottom-up for min ILP", createILPMinScheduler) |
| |
| static MachineSchedRegistry | ShufflerRegistry ("shuffle","Shuffle machine instructions alternating directions", createInstructionShuffler) |
| |
Return true of the given instruction should not be included in a scheduling region.
MachineScheduler does not currently support scheduling across calls. To handle calls, the DAG builder needs to be modified to create register anti/output dependencies on the registers clobbered by the call's regmask operand. In PreRA scheduling, the stack pointer adjustment already prevents scheduling across calls. In PostRA scheduling, we need the isCall to enforce the boundary, but there would be no benefit to postRA scheduling across calls this late anyway.
Definition at line 383 of file MachineScheduler.cpp.
References llvm::TargetInstrInfo::isSchedulingBoundary().