16 #ifndef LLVM_TARGET_TARGETREGISTERINFO_H
17 #define LLVM_TARGET_TARGETREGISTERINFO_H
30 class MachineFunction;
32 template<
class T>
class SmallVectorImpl;
83 bool contains(
unsigned Reg1,
unsigned Reg2)
const {
233 const char *
const *SubRegIndexNames;
235 const unsigned *SubRegIndexLaneMasks;
238 unsigned CoveringLanes;
244 const char *
const *SRINames,
245 const unsigned *SRILaneMasks,
246 unsigned CoveringLanes);
270 return int(Reg) >= (1 << 30);
277 return int(Reg - (1u << 30));
283 assert(FI >= 0 &&
"Cannot hold a negative frame index.");
284 return FI + (1u << 30);
290 assert(!
isStackSlot(Reg) &&
"Not a register! Check isStackSlot() first.");
297 assert(!
isStackSlot(Reg) &&
"Not a register! Check isStackSlot() first.");
305 return Reg & ~(1u << 31);
311 return Index | (1u << 31);
347 "This is not a subregister index");
348 return SubRegIndexNames[SubIdx-1];
373 return SubRegIndexLaneMasks[SubIdx];
386 return LaneMask & 0x80000000u;
417 if (regA == regB)
return true;
425 if (*RUA == *RUB)
return true;
426 if (*RUA < *RUB) ++RUA;
435 if (*Units == RegUnit)
517 assert(Idx == 0 &&
"Target has no sub-registers");
551 static void dumpReg(
unsigned Reg,
unsigned SubRegIndex = 0,
593 unsigned &PreA,
unsigned &PreB)
const;
612 return RegClassBegin[i];
683 unsigned Idx)
const = 0;
774 int &FrameIdx)
const {
809 unsigned BaseReg,
int FrameIdx,
810 int64_t Offset)
const {
818 int64_t Offset)
const {
825 int64_t Offset)
const {
839 unsigned Reg)
const {
851 int SPAdj,
unsigned FIOperandNum,
892 const unsigned RCMaskWords;
895 const uint32_t *Mask;
902 bool IncludeSelf =
false)
903 : RCMaskWords((TRI->getNumRegClasses() + 31) / 32),
905 Idx(RC->getSuperRegIndices()),
906 Mask(RC->getSubClassMask()) {
919 const uint32_t *
getMask()
const {
return Mask; }
923 assert(
isValid() &&
"Cannot move iterator past end.");
957 : TRI(tri), Reg(reg), SubIdx(subidx) {}
bool hasType(MVT vt) const
hasType - return true if this TargetRegisterClass has the ValueType vt.
const MCPhysReg * const_iterator
virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, int &FrameIdx) const
hasReservedSpillSlot - Return true if target has reserved a spill slot in the stack frame of the give...
vt_iterator vt_end() const
PrintReg(unsigned reg, const TargetRegisterInfo *tri=nullptr, unsigned subidx=0)
TargetRegisterInfo(const TargetRegisterInfoDesc *ID, regclass_iterator RegClassBegin, regclass_iterator RegClassEnd, const char *const *SRINames, const unsigned *SRILaneMasks, unsigned CoveringLanes)
virtual unsigned getNumRegPressureSets() const =0
Get the number of dimensions of register pressure.
void print(raw_ostream &) const
static unsigned virtReg2Index(unsigned Reg)
virtReg2Index - Convert a virtual register number to a 0-based index.
virtual bool saveScavengerRegister(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, unsigned Reg) const
saveScavengerRegister - Spill the register so it can be used by the register scavenger.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
unsigned getRegister(unsigned i) const
getRegister - Return the specified register in the class.
unsigned operator()(unsigned Reg) const
static unsigned index2VirtReg(unsigned Index)
index2VirtReg - Convert a 0-based index to a virtual register number.
const uint16_t * getSuperRegIndices() const
getSuperRegIndices - Returns a 0-terminated list of sub-register indices that project some super-regi...
virtual ~TargetRegisterInfo()
bool hasSubClassEq(const TargetRegisterClass *RC) const
hasSubClassEq - Returns true if RC is a sub-class of or equal to this class.
static bool isImpreciseLaneMask(unsigned LaneMask)
Returns true if the given lane mask is imprecise.
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
static void dumpReg(unsigned Reg, unsigned SubRegIndex=0, const TargetRegisterInfo *TRI=nullptr)
Debugging helper: dump register in human readable form to dbgs() stream.
PrintRegUnit - Helper class for printing register units on a raw_ostream.
virtual bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC) const
Subtarget Hooks.
void print(raw_ostream &) const
unsigned getID() const
getID() - Return the register class ID number.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
regclass_iterator regclass_end() const
virtual unsigned getCSRFirstUseCost() const
Allow the target to override the cost of using a callee-saved register for the first time...
virtual const int * getRegClassPressureSets(const TargetRegisterClass *RC) const =0
Get the dimensions of register pressure impacted by this register class.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
hasSuperClassEq - Returns true if RC is a super-class of or equal to this class.
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const
getCommonSubClass - find the largest common subclass of A and B.
virtual const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const
getCrossCopyRegClass - Returns a legal register class to copy a register in the specified class to or...
virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const
requiresFrameIndexScavenging - returns true if the target requires post PEI scavenging of registers f...
const uint32_t * SubClassMask
const MCPhysReg * iterator
virtual unsigned getRegUnitWeight(unsigned RegUnit) const =0
Get the weight in units of pressure for this register unit.
static int stackSlot2Index(unsigned Reg)
stackSlot2Index - Compute the frame index from a register value representing a stack slot...
unsigned getSize() const
getSize - Return the size of the register in bytes, which is also the size of a stack slot allocated ...
bool isAllocatable() const
isAllocatable - Return true if this register class may be used to create virtual registers.
virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const
getFrameIndexInstrOffset - Get the offset from the referenced frame index in the instruction, if there is one.
Each TargetRegisterClass has a per register weight, and weight limit which must be less than the limi...
const uint16_t * SuperRegIndices
unsigned getNumRegClasses() const
unsigned getNumRegs() const
getNumRegs - Return the number of registers in this class.
virtual unsigned composeSubRegIndexLaneMaskImpl(unsigned, unsigned) const
Overridden by TableGen in targets that have sub-registers.
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
unsigned getSubReg() const
Returns the current sub-register index.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
virtual const char * getRegPressureSetName(unsigned Idx) const =0
Get the name of this register unit pressure set.
const TargetRegisterClass * getRegClass(unsigned i) const
getRegClass - Returns the register class associated with the enumeration value.
ArrayRef< MCPhysReg > getRawAllocationOrder(const MachineFunction &MF) const
getRawAllocationOrder - Returns the preferred order for allocating registers from this register class...
iterator begin() const
begin/end - Return all of the registers in this class.
Reg
All possible values of the reg field in the ModR/M byte.
virtual unsigned getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
PrintReg - Helper class for printing registers on a raw_ostream.
const char * getRegClassName(const MCRegisterClass *Class) const
unsigned getNumSubRegIndices() const
Return the number of sub-register indices understood by the target.
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
getMatchingSuperReg - Return a super-register of the specified register Reg so its sub-register of in...
void operator++()
Advance iterator to the next entry.
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
getMatchingSuperRegClass - Return a subclass of the specified register class A so that each register ...
const char * getRegClassName(const TargetRegisterClass *Class) const
getRegClassName - Returns the name of the register class.
virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const =0
eliminateFrameIndex - This method must be overriden to eliminate abstract frame indices from instruct...
virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const
requiresVirtualBaseRegisters - Returns true if the target wants the LocalStackAllocation pass to be r...
virtual bool useFPForScavengingIndex(const MachineFunction &MF) const
useFPForScavengingIndex - returns true if the target wants to use frame pointer based accesses to spi...
unsigned getID() const
getID() - Return the register class ID number.
BitVector getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const
getAllocatableSet - Returns a bitset indexed by register number indicating if a register is allocatab...
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
getCalleeSavedRegs - Return a null-terminated list of all of the callee saved registers on this targe...
virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const
materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx...
MCRegisterClass - Base class of TargetRegisterClass.
bool isInAllocatableClass(unsigned RegNo) const
isInAllocatableClass - Return true if the register is in the allocation of any register class...
virtual bool requiresRegisterScavenging(const MachineFunction &MF) const
requiresRegisterScavenging - returns true if the target requires (and can make use of) the register s...
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
const TargetRegisterClass * getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA, const TargetRegisterClass *RCB, unsigned SubB, unsigned &PreA, unsigned &PreB) const
getCommonSuperRegClass - Find a common super-register class if it exists.
bool hasSuperClass(const TargetRegisterClass *RC) const
hasSuperClass - return true if the specified TargetRegisterClass is a proper super-class of this Targ...
bundle_iterator< MachineInstr, instr_iterator > iterator
PrintVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *tri)
const uint8_t AllocationPriority
Classes with a higher priority value are assigned first by register allocators using a greedy heurist...
bool regsOverlap(unsigned regA, unsigned regB) const
regsOverlap - Returns true if the two registers are equal or alias each other.
regclass_iterator regclass_begin() const
Register class iterators.
bool contains(unsigned Reg1, unsigned Reg2) const
contains - Return true if both registers are in this class.
MVT - Machine Value Type.
const sc_iterator SuperClasses
virtual bool needsStackRealignment(const MachineFunction &MF) const
needsStackRealignment - true if storage within the function requires the stack pointer to be aligned ...
unsigned getAlignment() const
getAlignment - Return the minimum required alignment for a register of this class.
unsigned getSubRegIndexLaneMask(unsigned SubIdx) const
getSubRegIndexLaneMask - Return a bitmask representing the parts of a register that are covered by Su...
unsigned getCostPerUse(unsigned RegNo) const
getCostPerUse - Return the additional cost of using this register instead of other registers in its c...
bundle_iterator - MachineBasicBlock iterator that automatically skips over MIs that are inside bundle...
virtual void adjustStackMapLiveOutMask(uint32_t *Mask) const
Prior to adding the live-out mask to a stackmap or patchpoint instruction, provide the target the opp...
unsigned getRegister(unsigned i) const
getRegister - Return the specified register in the class.
unsigned getSize() const
getSize - Return the size of the register in bytes, which is also the size of a stack slot allocated ...
virtual ArrayRef< const char * > getRegMaskNames() const =0
int getCopyCost() const
getCopyCost - Return the cost of copying a value between two registers in this class.
const TargetRegisterClass *const * sc_iterator
TargetRegisterInfoDesc - Extra information, not in MCRegisterDesc, about registers.
virtual void getRegAllocationHints(unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr) const
Get a list of 'hint' registers that the register allocator should try first when allocating a physica...
const TargetRegisterClass * getAllocatableClass(const TargetRegisterClass *RC) const
getAllocatableClass - Return the maximal subclass of the given register class that is alloctable...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool hasSubClass(const TargetRegisterClass *RC) const
hasSubClass - return true if the specified TargetRegisterClass is a proper sub-class of this TargetRe...
void print(raw_ostream &) const
const bool HasDisjunctSubRegs
Whether the class supports two (or more) disjunct subregister indices.
unsigned getCoveringLanes() const
The lane masks returned by getSubRegIndexLaneMask() above can only be used to determine if sub-regist...
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg...
static bool isStackSlot(unsigned Reg)
isStackSlot - Sometimes it is useful the be able to store a non-negative frame index in a variable th...
virtual bool reverseLocalAssignment() const
Allow the target to reverse allocation order of local live ranges.
unsigned getLaneMask() const
Returns the combination of all lane masks of register in this class.
bool contains(unsigned Reg) const
contains - Return true if the specified register is included in this register class.
virtual const RegClassWeight & getRegClassWeight(const TargetRegisterClass *RC) const =0
Get the weight in units of pressure for this register class.
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const
trackLivenessAfterRegAlloc - returns true if the live-ins should be tracked after register allocation...
unsigned composeSubRegIndexLaneMask(unsigned IdxA, unsigned LaneMask) const
Transforms a LaneMask computed for one subregister to the lanemask that would have been computed when...
virtual void updateRegAllocHint(unsigned Reg, unsigned NewReg, MachineFunction &MF) const
updateRegAllocHint - A callback to allow target a chance to update register allocation hints when a r...
const MVT::SimpleValueType * vt_iterator
ArrayRef< MCPhysReg >(* OrderFunc)(const MachineFunction &)
const MCRegisterClass * MC
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a ...
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
getCallPreservedMask - Return a mask of call-preserved registers for the given calling convention on ...
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
getMinimalPhysRegClass - Returns the Register Class of a physical register of the given type...
virtual bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const
isFrameOffsetLegal - Determine whether a given base register plus offset immediate is encodable to re...
unsigned getNumRegs() const
getNumRegs - Return the number of registers in this class.
const char * getSubRegIndexName(unsigned SubIdx) const
getSubRegIndexName - Return the human-readable symbolic target-specific name for the specified SubReg...
SuperRegClassIterator(const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, bool IncludeSelf=false)
Create a SuperRegClassIterator that visits all the super-register classes of RC.
virtual unsigned composeSubRegIndicesImpl(unsigned, unsigned) const
Overridden by TableGen in targets that have sub-registers.
PrintVRegOrUnit - It is often convenient to track virtual registers and physical register units in th...
int getCopyCost() const
getCopyCost - Return the cost of copying a value between two registers in this class.
Representation of each machine instruction.
static bool isPhysicalRegister(unsigned Reg)
isPhysicalRegister - Return true if the specified register number is in the physical register namespa...
bool isASubClass() const
isASubClass - return true if this TargetRegisterClass is a subset class of at least one other TargetR...
virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const
needsFrameBaseReg - Returns true if the instruction's frame index reference would be better served by...
virtual ArrayRef< const uint32_t * > getRegMasks() const =0
Return all the call-preserved register masks defined for this target.
virtual unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const =0
Get the register unit pressure limit for this dimension.
bool isAllocatable() const
isAllocatable - Return true if this register class may be used to create virtual registers.
unsigned getAlignment() const
getAlignment - Return the minimum required alignment for a register of this class.
virtual const int * getRegUnitPressureSets(unsigned RegUnit) const =0
Get the dimensions of register pressure impacted by this register unit.
virtual void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const
resolveFrameIndex - Resolve a frame index operand of an instruction to reference the indicated base r...
raw_ostream & operator<<(raw_ostream &OS, const APInt &I)
virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const
getRegPressureLimit - Return the register pressure "high water mark" for the specific register class...
iterator begin() const
begin/end - Return all of the registers in this class.
const ARM::ArchExtKind Kind
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
getSubClassWithSubReg - Returns the largest legal sub-class of RC that supports the sub-register inde...
PrintRegUnit(unsigned unit, const TargetRegisterInfo *tri)
This class implements an extremely fast bulk output stream that can only output to a stream...
vt_iterator vt_begin() const
vt_begin / vt_end - Loop over all of the value types that can be represented by values in this regist...
const uint32_t * getMask() const
Returns the bit mask if register classes that getSubReg() projects into RC.
unsigned composeSubRegIndices(unsigned a, unsigned b) const
composeSubRegIndices - Return the subregister index you get from composing two subregister indices...
const TargetRegisterInfo * TRI
virtual const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const
getPointerRegClass - Returns a TargetRegisterClass used for pointer values.
sc_iterator getSuperClasses() const
getSuperClasses - Returns a NULL terminated list of super-classes.
static unsigned index2StackSlot(int FI)
index2StackSlot - Convert a non-negative frame index to a stack slot register value.
const uint32_t * getSubClassMask() const
getSubClassMask - Returns a bit vector of subclasses, including this one.
const TargetRegisterClass *const * regclass_iterator
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
getLargestLegalSuperClass - Returns the largest super class of RC that is legal to use in the current...
bool hasRegUnit(unsigned Reg, unsigned RegUnit) const
hasRegUnit - Returns true if Reg contains RegUnit.
bool contains(unsigned Reg) const
contains - Return true if the specified register is included in this register class.