14 #ifndef LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H
15 #define LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H
36 bool *
Fast =
nullptr)
const override;
47 EVT VT)
const override {
54 bool isEligibleForTailCallOptimization(
55 const CCState &CCInfo,
unsigned NextStackOffset,
60 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
61 bool IsPICCall,
bool GlobalOrExternal,
bool InternalLinkage,
62 bool IsCallReloc, CallLoweringInfo &CLI,
SDValue Callee,
68 SDValue lowerMulDiv(
SDValue Op,
unsigned NewOpc,
bool HasLo,
bool HasHi,
84 unsigned BranchOp)
const;
100 unsigned EltSizeInBytes,
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS=0, unsigned Align=1, bool *Fast=nullptr) const override
Determine if the target supports unaligned memory accesses.
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
MVT - Machine Value Type.
EVT - Extended Value Type.
CCState - This class holds information needed while lowering arguments and return values...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Represents one node in the SelectionDAG.
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
Representation of each machine instruction.
const TargetRegisterClass * getRepRegClassFor(MVT VT) const override
Return the 'representative' register class for the specified value type.
Fast - This calling convention attempts to make calls as fast as possible (e.g.
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
bool isShuffleMaskLegal(const SmallVectorImpl< int > &Mask, EVT VT) const override
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks.
MipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC)
Enable MSA support for the given integer type and Register class.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
void addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC)
Enable MSA support for the given floating-point type and Register class.