41 #define DEBUG_TYPE "machine-licm"
45 cl::desc(
"MachineLICM should avoid speculation"),
50 cl::desc(
"MachineLICM should hoist even cheap instructions"),
55 cl::desc(
"MachineLICM should sink instructions into "
56 "loops to avoid register spills"),
60 "Number of machine instructions hoisted out of loops");
62 "Number of instructions hoisted in low reg pressure situation");
64 "Number of high latency instructions hoisted");
66 "Number of hoisted machine instructions CSEed");
68 "Number of machine instructions hoisted out of loops post regalloc");
95 return std::find(ExitBlocks.begin(), ExitBlocks.end(), MBB) !=
122 unsigned SpeculationState;
131 explicit MachineLICM(
bool PreRA) :
147 void releaseMemory()
override {
157 struct CandidateInfo {
162 :
MI(mi),
Def(def), FI(fi) {}
167 void HoistRegionPostRA();
184 void AddToLiveIns(
unsigned Reg);
267 bool ConsiderUnseenAsDef);
272 bool ConsiderUnseenAsDef =
false);
283 std::vector<const MachineInstr*> &PrevMIs);
290 DenseMap<
unsigned, std::vector<const MachineInstr*> >::iterator &CI);
315 "Machine Loop Invariant Code Motion",
false,
false)
326 if (!CurLoop->getLoopPredecessor())
330 if (L->getLoopPredecessor())
340 Changed = FirstInLoop =
false;
349 PreRegAlloc = MRI->
isSSA();
352 DEBUG(
dbgs() <<
"******** Pre-regalloc Machine LICM: ");
354 DEBUG(
dbgs() <<
"******** Post-regalloc Machine LICM: ");
359 unsigned NumRPS = TRI->getNumRegPressureSets();
362 RegLimit.resize(NumRPS);
363 for (
unsigned i = 0, e = NumRPS; i != e; ++i)
364 RegLimit[i] = TRI->getRegPressureSetLimit(MF, i);
368 MLI = &getAnalysis<MachineLoopInfo>();
369 DT = &getAnalysis<MachineDominatorTree>();
370 AA = &getAnalysis<AliasAnalysis>();
373 while (!Worklist.empty()) {
375 CurPreheader =
nullptr;
381 Worklist.append(CurLoop->begin(), CurLoop->end());
385 CurLoop->getExitBlocks(ExitBlocks);
410 if (!(*o)->isStore() || !(*o)->getPseudoValue())
413 dyn_cast<FixedStackPseudoSourceValue>((*o)->getPseudoValue())) {
414 if (
Value->getFrameIndex() == FI)
428 bool RuledOut =
false;
429 bool HasNonInvariantUse =
false;
436 if (!StoredFIs.
count(FI) &&
437 MFI->isSpillSlotObjectIndex(FI) &&
440 HasNonInvariantUse =
true;
457 "Not expecting virtual register!");
460 if (Reg && (PhysRegDefs.
test(Reg) || PhysRegClobbers.
test(Reg)))
463 HasNonInvariantUse =
true;
469 PhysRegClobbers.
set(*AI);
489 if (PhysRegDefs.
test(*AS))
490 PhysRegClobbers.
set(*AS);
491 PhysRegDefs.
set(*AS);
493 if (PhysRegClobbers.
test(Reg))
501 if (Def && !RuledOut) {
503 if ((!HasNonInvariantUse && IsLICMCandidate(*MI)) ||
505 Candidates.
push_back(CandidateInfo(MI, Def, FI));
511 void MachineLICM::HoistRegionPostRA() {
516 unsigned NumRegs = TRI->getNumRegs();
525 const std::vector<MachineBasicBlock *> &Blocks = CurLoop->getBlocks();
526 for (
unsigned i = 0, e = Blocks.size(); i != e; ++i) {
532 if (ML && ML->
getHeader()->isLandingPad())
continue;
541 PhysRegDefs.
set(*AI);
544 SpeculationState = SpeculateUnknown;
546 MII = BB->
begin(), E = BB->
end(); MII != E; ++MII) {
548 ProcessMI(MI, PhysRegDefs, PhysRegClobbers, StoredFIs, Candidates);
555 if (TI != Preheader->
end()) {
556 for (
unsigned i = 0, e = TI->getNumOperands(); i != e; ++i) {
560 unsigned Reg = MO.
getReg();
576 for (
unsigned i = 0, e = Candidates.
size(); i != e; ++i) {
577 if (Candidates[i].FI != INT_MIN &&
578 StoredFIs.
count(Candidates[i].FI))
581 unsigned Def = Candidates[i].Def;
582 if (!PhysRegClobbers.
test(Def) && !TermRegs.test(Def)) {
589 unsigned Reg = MO.
getReg();
590 if (PhysRegDefs.
test(Reg) ||
591 PhysRegClobbers.
test(Reg)) {
599 HoistPostRA(MI, Candidates[i].Def);
606 void MachineLICM::AddToLiveIns(
unsigned Reg) {
607 const std::vector<MachineBasicBlock *> &Blocks = CurLoop->getBlocks();
608 for (
unsigned i = 0, e = Blocks.size(); i != e; ++i) {
613 MII = BB->
begin(), E = BB->
end(); MII != E; ++MII) {
618 if (MO.
getReg() == Reg || TRI->isSuperRegister(Reg, MO.
getReg()))
628 void MachineLICM::HoistPostRA(
MachineInstr *MI,
unsigned Def) {
652 if (SpeculationState != SpeculateUnknown)
653 return SpeculationState == SpeculateFalse;
655 if (BB != CurLoop->getHeader()) {
658 CurLoop->getExitingBlocks(CurrentLoopExitingBlocks);
659 for (
unsigned i = 0, e = CurrentLoopExitingBlocks.
size(); i != e; ++i)
660 if (!DT->dominates(BB, CurrentLoopExitingBlocks[i])) {
661 SpeculationState = SpeculateTrue;
666 SpeculationState = SpeculateFalse;
679 BackTrace.pop_back();
688 if (OpenChildren[Node])
692 ExitScope(Node->getBlock());
696 unsigned Left = --OpenChildren[Parent];
699 ExitScope(Parent->getBlock());
722 while (!WorkList.
empty()) {
724 assert(Node &&
"Null dominator tree node?");
730 if (ML && ML->
getHeader()->isLandingPad())
734 if (!CurLoop->contains(BB))
738 const std::vector<MachineDomTreeNode*> &Children = Node->
getChildren();
739 unsigned NumChildren = Children.size();
747 OpenChildren[Node] = NumChildren;
751 for (
int i = (
int)NumChildren-1; i >= 0; --i) {
753 ParentMap[Child] = Node;
758 if (Scopes.
size() == 0)
764 InitRegPressure(Preheader);
767 for (
unsigned i = 0, e = Scopes.
size(); i != e; ++i) {
774 SpeculationState = SpeculateUnknown;
776 MII = MBB->
begin(), E = MBB->
end(); MII != E; ) {
779 if (!Hoist(MI, Preheader))
780 UpdateRegPressure(MI);
785 ExitScopeIfDone(Node, OpenChildren, ParentMap);
789 void MachineLICM::SinkIntoLoop() {
799 if (IsLoopInvariantInst(*
I) && !HasLoopPHIUse(
I))
807 if (!MRI->hasOneDef(MO.
getReg()))
824 B = DT->findNearestCommonDominator(B, MI.
getParent());
830 if (!CanSink || !B || B == Preheader)
858 UpdateRegPressure(&MI,
true);
863 void MachineLICM::UpdateRegPressure(
const MachineInstr *MI,
864 bool ConsiderUnseenAsDef) {
865 auto Cost = calcRegisterCost(MI,
true, ConsiderUnseenAsDef);
866 for (
const auto &RPIdAndCost : Cost) {
867 unsigned Class = RPIdAndCost.first;
868 if (static_cast<int>(
RegPressure[Class]) < -RPIdAndCost.second)
876 MachineLICM::calcRegisterCost(
const MachineInstr *MI,
bool ConsiderSeen,
877 bool ConsiderUnseenAsDef) {
885 unsigned Reg = MO.
getReg();
890 bool isNew = ConsiderSeen ? RegSeen.insert(Reg).second :
false;
899 if (isNew && !isKill && ConsiderUnseenAsDef)
902 else if (!isNew && isKill)
907 const int *
PS = TRI->getRegClassPressureSets(RC);
908 for (; *PS != -1; ++
PS) {
909 if (Cost.
find(*PS) == Cost.
end())
921 assert (MI.
mayLoad() &&
"Expected MI that loads!");
925 if (PSV == PSV->getGOT() || PSV == PSV->getConstantPool())
937 bool DontMoveAcrossStore =
true;
959 bool MachineLICM::IsLoopInvariantInst(
MachineInstr &I) {
960 if (!IsLICMCandidate(I))
970 unsigned Reg = MO.
getReg();
971 if (Reg == 0)
continue;
974 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
983 }
else if (!MO.
isDead()) {
986 }
else if (CurLoop->getHeader()->isLiveIn(Reg)) {
996 assert(MRI->getVRegDef(Reg) &&
997 "Machine instr not mapped for this vreg?!");
1001 if (CurLoop->contains(MRI->getVRegDef(Reg)))
1012 bool MachineLICM::HasLoopPHIUse(
const MachineInstr *MI)
const {
1015 MI = Work.pop_back_val();
1019 unsigned Reg = MO.
getReg();
1020 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1022 for (
MachineInstr &UseMI : MRI->use_instructions(Reg)) {
1024 if (UseMI.isPHI()) {
1027 if (CurLoop->contains(&UseMI))
1037 if (UseMI.isCopy() && CurLoop->contains(&UseMI))
1038 Work.push_back(&UseMI);
1041 }
while (!Work.empty());
1048 bool MachineLICM::HasHighOperandLatency(
MachineInstr &MI,
1049 unsigned DefIdx,
unsigned Reg)
const {
1050 if (MRI->use_nodbg_empty(Reg))
1053 for (
MachineInstr &UseMI : MRI->use_nodbg_instructions(Reg)) {
1054 if (UseMI.isCopyLike())
1056 if (!CurLoop->contains(UseMI.getParent()))
1058 for (
unsigned i = 0, e = UseMI.getNumOperands(); i != e; ++i) {
1062 unsigned MOReg = MO.
getReg();
1066 if (
TII->hasHighOperandLatency(SchedModel, MRI, &MI, DefIdx, &UseMI, i))
1079 bool MachineLICM::IsCheapInstruction(
MachineInstr &MI)
const {
1083 bool isCheap =
false;
1085 for (
unsigned i = 0, e = MI.
getNumOperands(); NumDefs && i != e; ++i) {
1090 unsigned Reg = DefMO.
getReg();
1091 if (TargetRegisterInfo::isPhysicalRegister(Reg))
1094 if (!
TII->hasLowDefLatency(SchedModel, &MI, i))
1107 for (
const auto &RPIdAndCost : Cost) {
1108 if (RPIdAndCost.second <= 0)
1111 unsigned Class = RPIdAndCost.first;
1112 int Limit = RegLimit[
Class];
1119 for (
const auto &
RP : BackTrace)
1120 if (static_cast<int>(
RP[Class]) + RPIdAndCost.second >= Limit)
1130 void MachineLICM::UpdateBackTraceRegPressure(
const MachineInstr *MI) {
1133 auto Cost = calcRegisterCost(MI,
false,
1137 for (
auto &
RP : BackTrace)
1138 for (
const auto &RPIdAndCost : Cost)
1139 RP[RPIdAndCost.first] += RPIdAndCost.second;
1144 bool MachineLICM::IsProfitableToHoist(
MachineInstr &MI) {
1160 bool CheapInstr = IsCheapInstruction(MI);
1161 bool CreatesCopy = HasLoopPHIUse(&MI);
1164 if (CheapInstr && CreatesCopy) {
1165 DEBUG(
dbgs() <<
"Won't hoist cheap instr with loop PHI use: " << MI);
1171 if (
TII->isTriviallyReMaterializable(&MI, AA))
1180 unsigned Reg = MO.
getReg();
1181 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1183 if (MO.
isDef() && HasHighOperandLatency(MI, i, Reg)) {
1184 DEBUG(
dbgs() <<
"Hoist High Latency: " << MI);
1196 auto Cost = calcRegisterCost(&MI,
false,
1201 if (!CanCauseHighRegPressure(Cost, CheapInstr)) {
1202 DEBUG(
dbgs() <<
"Hoist non-reg-pressure: " << MI);
1209 DEBUG(
dbgs() <<
"Won't hoist instr with loop PHI use: " << MI);
1217 (!IsGuaranteedToExecute(MI.
getParent()) && !MayCSE(&MI))) {
1218 DEBUG(
dbgs() <<
"Won't speculate: " << MI);
1224 if (!
TII->isTriviallyReMaterializable(&MI, AA) &&
1226 DEBUG(
dbgs() <<
"Can't remat / high reg-pressure: " << MI);
1245 unsigned LoadRegIndex;
1251 if (NewOpc == 0)
return nullptr;
1257 unsigned Reg = MRI->createVirtualRegister(RC);
1261 TII->unfoldMemoryOperand(MF, MI, Reg,
1266 "unfoldMemoryOperand failed when getOpcodeAfterMemoryUnfold "
1268 assert(NewMIs.
size() == 2 &&
1269 "Unfolded a load into multiple instructions!");
1272 MBB->insert(Pos, NewMIs[0]);
1273 MBB->insert(Pos, NewMIs[1]);
1276 if (!IsLoopInvariantInst(*NewMIs[0]) || !IsProfitableToHoist(*NewMIs[0])) {
1277 NewMIs[0]->eraseFromParent();
1278 NewMIs[1]->eraseFromParent();
1283 UpdateRegPressure(NewMIs[1]);
1294 CSEMap[Opcode].push_back(MI);
1300 std::vector<const MachineInstr*> &PrevMIs) {
1301 for (
unsigned i = 0, e = PrevMIs.size(); i != e; ++i) {
1303 if (
TII->produceSameValue(MI, PrevMI, (PreRegAlloc ? MRI :
nullptr)))
1310 DenseMap<
unsigned, std::vector<const MachineInstr*> >::iterator &CI) {
1316 if (
const MachineInstr *Dup = LookForDuplicate(MI, CI->second)) {
1317 DEBUG(
dbgs() <<
"CSEing " << *MI <<
" with " << *Dup);
1327 !TargetRegisterInfo::isPhysicalRegister(MO.
getReg()) ||
1328 MO.
getReg() == Dup->getOperand(i).getReg()) &&
1329 "Instructions with different phys regs are not identical!");
1332 !TargetRegisterInfo::isPhysicalRegister(MO.
getReg()))
1337 for (
unsigned i = 0, e = Defs.
size(); i != e; ++i) {
1338 unsigned Idx = Defs[i];
1340 unsigned DupReg = Dup->getOperand(Idx).getReg();
1341 OrigRCs.
push_back(MRI->getRegClass(DupReg));
1343 if (!MRI->constrainRegClass(DupReg, MRI->getRegClass(Reg))) {
1345 for (
unsigned j = 0; j != i; ++j)
1346 MRI->setRegClass(Dup->getOperand(Defs[j]).getReg(), OrigRCs[j]);
1351 for (
unsigned i = 0, e = Defs.
size(); i != e; ++i) {
1352 unsigned Idx = Defs[i];
1354 unsigned DupReg = Dup->getOperand(Idx).getReg();
1355 MRI->replaceRegWith(Reg, DupReg);
1356 MRI->clearKillFlags(DupReg);
1371 CI = CSEMap.
find(Opcode);
1377 return LookForDuplicate(MI, CI->second) !=
nullptr;
1385 if (!IsLoopInvariantInst(*MI) || !IsProfitableToHoist(*MI)) {
1387 MI = ExtractHoistableLoad(MI);
1388 if (!MI)
return false;
1394 dbgs() <<
"Hoisting " << *
MI;
1396 dbgs() <<
" to MachineBasicBlock "
1399 dbgs() <<
" from MachineBasicBlock "
1407 InitCSEMap(Preheader);
1408 FirstInLoop =
false;
1414 CI = CSEMap.
find(Opcode);
1415 if (!EliminateCSE(MI, CI)) {
1420 UpdateBackTraceRegPressure(MI);
1428 MRI->clearKillFlags(MO.
getReg());
1432 if (CI != CSEMap.
end())
1433 CI->second.push_back(MI);
1435 CSEMap[Opcode].push_back(MI);
1449 if (CurPreheader == reinterpret_cast<MachineBasicBlock *>(-1))
1452 if (!CurPreheader) {
1453 CurPreheader = CurLoop->getLoopPreheader();
1454 if (!CurPreheader) {
1462 if (!CurPreheader) {
1468 return CurPreheader;
unsigned succ_size() const
void push_back(const T &Elt)
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
instr_iterator instr_begin()
instr_iterator instr_end()
STATISTIC(NumFunctions,"Total number of functions")
int getNumber() const
getNumber - MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a M...
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
char & MachineLICMID
MachineLICM - This pass performs LICM on machine instructions.
std::vector< unsigned >::const_iterator livein_iterator
iterator getFirstTerminator()
getFirstTerminator - returns an iterator to the first terminator instruction of this basic block...
Describe properties that are true of each instruction in the target description file.
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
INITIALIZE_PASS_BEGIN(MachineLICM,"machinelicm","Machine Loop Invariant Code Motion", false, false) INITIALIZE_PASS_END(MachineLICM
void addLiveIn(unsigned Reg)
Adds the specified register as a live in.
void setBitsNotInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsNotInMask - Add a bit to this vector for every '0' bit in Mask.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
LoopT * getParentLoop() const
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
bool canFoldAsLoad(QueryType Type=IgnoreBundle) const
Return true for instructions that can be folded as memory operands in other instructions.
Instructions::iterator instr_iterator
iterator_range< mop_iterator > operands()
BlockT * getHeader() const
livein_iterator livein_begin() const
AnalysisUsage & addRequired()
#define INITIALIZE_PASS_DEPENDENCY(depName)
MachineMemOperand - A description of a memory reference used in the backend.
Each TargetRegisterClass has a per register weight, and weight limit which must be less than the limi...
unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const override
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Provide an instruction scheduling machine model to CodeGen passes.
const HexagonInstrInfo * TII
T LLVM_ATTRIBUTE_UNUSED_RESULT pop_back_val()
static bool isOperandKill(const MachineOperand &MO, MachineRegisterInfo *MRI)
Machine Loop Invariant Code false
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Reg
All possible values of the reg field in the ModR/M byte.
MachineBasicBlock * SplitCriticalEdge(MachineBasicBlock *Succ, Pass *P)
SplitCriticalEdge - Split the critical edge from this block to the given successor block...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget's CPU.
static cl::opt< bool > AvoidSpeculation("avoid-speculation", cl::desc("MachineLICM should avoid speculation"), cl::init(true), cl::Hidden)
unsigned getNumOperands() const
Access to explicit operands of the instruction.
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Base class for the actual dominator tree node.
bool isCopyLike() const
Return true if the instruction behaves like a copy.
COFF::MachineTypes Machine
static bool isLoadFromGOTOrConstantPool(MachineInstr &MI)
isLoadFromGOTOrConstantPool - Return true if this machine instruction loads from global offset table ...
const BasicBlock * getBasicBlock() const
getBasicBlock - Return the LLVM basic block that this instance corresponded to originally.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineBasicBlock * getParent() const
TargetInstrInfo - Interface to description of machine instruction set.
bool isImplicitDef() const
mmo_iterator memoperands_end() const
bundle_iterator< MachineInstr, instr_iterator > iterator
initializer< Ty > init(const Ty &Val)
static cl::opt< bool > SinkInstsToAvoidSpills("sink-insts-to-avoid-spills", cl::desc("MachineLICM should sink instructions into ""loops to avoid register spills"), cl::init(false), cl::Hidden)
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
livein_iterator livein_end() const
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
const MachineOperand & getOperand(unsigned i) const
static cl::opt< bool > HoistCheapInsts("hoist-cheap-insts", cl::desc("MachineLICM should hoist even cheap instructions"), cl::init(false), cl::Hidden)
MCRegAliasIterator enumerates all registers aliasing Reg.
Represent the analysis usage information of a pass.
static bool InstructionStoresToFI(const MachineInstr *MI, int FI)
InstructionStoresToFI - Return true if instruction stores to the specified frame. ...
const std::vector< DomTreeNodeBase< NodeT > * > & getChildren() const
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
bool isInvariantLoad(AliasAnalysis *AA) const
Return true if this instruction is loading from a location whose value is invariant across the functi...
#define INITIALIZE_AG_DEPENDENCY(depName)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
pred_iterator pred_begin()
void initializeMachineLICMPass(PassRegistry &)
void setIsKill(bool Val=true)
This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from ...
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
bool test(unsigned Idx) const
virtual const TargetLowering * getTargetLowering() const
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
StringRef getName() const
getName - Return the name of the corresponding LLVM basic block, or "(null)".
PseudoSourceValue - Special value supplied for machine level alias analysis.
Machine Loop Invariant Code static false bool LoopIsOuterMostWithPredecessor(MachineLoop *CurLoop)
LoopIsOuterMostWithPredecessor - Test if the given loop is the outer-most loop that has a unique pred...
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
TargetSubtargetInfo - Generic base class for all target subtargets.
Representation of each machine instruction.
static bool isPhysicalRegister(unsigned Reg)
isPhysicalRegister - Return true if the specified register number is in the physical register namespa...
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
bool isLiveIn(unsigned Reg) const
isLiveIn - Return true if the specified register is in the live in set.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
iterator find(const KeyT &Val)
iterator getFirstNonPHI()
Returns a pointer to the first instruction in this block that is not a PHINode instruction.
unsigned getReg() const
getReg - Returns the register number.
Machine Loop Invariant Code Motion
virtual const TargetInstrInfo * getInstrInfo() const
LLVM Value Representation.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
static bool isExitBlock(BasicBlock *BB, const SmallVectorImpl< BasicBlock * > &ExitBlocks)
Return true if the specified block is in the list.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
FixedStackPseudoSourceValue - A specialized PseudoSourceValue for holding FixedStack values...
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
unsigned pred_size() const
This file describes how to lower LLVM code to machine code.
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.