39 #define DEBUG_TYPE "msp430-lower"
49 cl::desc(
"Hardware multiplier use mode"),
53 "Do not use hardware multiplier"),
55 "Assume hardware multiplier can be used inside interrupts"),
57 "Assume hardware multiplier cannot be used inside interrupts"),
217 if (Constraint.
size() == 1) {
218 switch (Constraint[0]) {
228 std::pair<unsigned, const TargetRegisterClass *>
231 if (Constraint.
size() == 1) {
233 switch (Constraint[0]) {
237 return std::make_pair(0U, &MSP430::GR8RegClass);
239 return std::make_pair(0U, &MSP430::GR16RegClass);
250 #include "MSP430GenCallingConv.inc"
254 template<
typename ArgT>
257 unsigned CurrentArgIndex = ~0U;
258 for (
unsigned i = 0, e = Args.
size(); i != e; i++) {
259 if (CurrentArgIndex == Args[i].OrigArgIndex) {
282 template<
typename ArgT>
299 unsigned RegsLeft = NbRegs;
300 bool UseStack =
false;
303 for (
unsigned i = 0, e = ArgsParts.
size(); i != e; i++) {
304 MVT ArgVT = Args[ValNo].VT;
314 else if (ArgFlags.
isZExt())
322 State.
HandleByVal(ValNo++, ArgVT, LocVT, LocInfo, 2, 2, ArgFlags);
326 unsigned Parts = ArgsParts[i];
328 if (!UseStack && Parts <= RegsLeft) {
329 unsigned FirstVal = ValNo;
330 for (
unsigned j = 0; j < Parts; j++) {
339 std::reverse(B, B + Parts);
342 for (
unsigned j = 0; j < Parts; j++)
343 CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State);
358 template<
typename ArgT>
366 std::reverse(RVLocs.
begin(), RVLocs.
end());
370 MSP430TargetLowering::LowerFormalArguments(
SDValue Chain,
385 return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
415 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
416 Outs, OutVals, Ins, dl, DAG, InVals);
426 MSP430TargetLowering::LowerCCCArguments(
SDValue Chain,
448 unsigned Offset = CCInfo.getNextStackOffset();
452 for (
unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
461 errs() <<
"LowerFormalArguments Unhandled argument type: "
501 errs() <<
"LowerFormalArguments Unhandled argument type: "
513 false,
false,
false, 0);
524 MSP430TargetLowering::LowerReturn(
SDValue Chain,
548 for (
unsigned i = 0; i != RVLocs.
size(); ++i) {
550 assert(VA.
isRegLoc() &&
"Can only return in registers!");
568 RetOps.push_back(Flag);
577 MSP430TargetLowering::LowerCCCCallTo(
SDValue Chain,
SDValue Callee,
593 unsigned NumBytes = CCInfo.getNextStackOffset();
604 for (
unsigned i = 0, e = ArgLocs.
size(); i != e; ++i) {
643 MemOp = DAG.
getMemcpy(Chain, dl, PtrOff, Arg, SizeNode,
661 if (!MemOpChains.
empty())
668 for (
unsigned i = 0, e = RegsToPass.
size(); i != e; ++i) {
669 Chain = DAG.
getCopyToReg(Chain, dl, RegsToPass[i].first,
670 RegsToPass[i].second, InFlag);
690 for (
unsigned i = 0, e = RegsToPass.
size(); i != e; ++i)
692 RegsToPass[i].second.getValueType()));
707 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
715 MSP430TargetLowering::LowerCallResult(
SDValue Chain,
SDValue InFlag,
729 for (
unsigned i = 0; i != RVLocs.
size(); ++i) {
731 RVLocs[i].getValVT(), InFlag).
getValue(1);
761 uint64_t ShiftAmount = cast<ConstantSDNode>(N->
getOperand(1))->getZExtValue();
768 if (Opc ==
ISD::SRL && ShiftAmount) {
775 while (ShiftAmount--)
784 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
785 int64_t Offset = cast<GlobalAddressSDNode>(Op)->
getOffset();
796 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
807 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
844 RHS = DAG.
getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
857 RHS = DAG.
getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
870 RHS = DAG.
getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
883 RHS = DAG.
getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
908 Chain, Dest, TargetCC,
Flag);
923 if (RHSC->isNullValue() && LHS.
hasOneUse() &&
941 switch (cast<ConstantSDNode>(TargetCC)->getZExtValue()) {
1000 SDValue Ops[] = {TrueV, FalseV, TargetCC, Flag};
1011 assert(VT ==
MVT::i16 &&
"Only support i16 for now!");
1022 int ReturnAddrIndex = FuncInfo->
getRAIndex();
1025 if (ReturnAddrIndex == 0) {
1044 unsigned Depth = cast<ConstantSDNode>(Op.
getOperand(0))->getZExtValue();
1070 unsigned Depth = cast<ConstantSDNode>(Op.
getOperand(0))->getZExtValue();
1076 false,
false,
false, 0);
1108 bool MSP430TargetLowering::getPostIndexedAddressParts(
SDNode *
N,
SDNode *Op,
1126 uint64_t RHSC = RHS->getZExtValue();
1127 if ((VT ==
MVT::i16 && RHSC != 2) ||
1208 Opc = MSP430::SHL8r1;
1209 RC = &MSP430::GR8RegClass;
1212 Opc = MSP430::SHL16r1;
1213 RC = &MSP430::GR16RegClass;
1216 Opc = MSP430::SAR8r1;
1217 RC = &MSP430::GR8RegClass;
1220 Opc = MSP430::SAR16r1;
1221 RC = &MSP430::GR16RegClass;
1224 Opc = MSP430::SAR8r1c;
1225 RC = &MSP430::GR8RegClass;
1228 Opc = MSP430::SAR16r1c;
1229 RC = &MSP430::GR16RegClass;
1268 .addReg(ShiftAmtSrcReg).
addImm(0);
1279 .addReg(SrcReg).
addMBB(BB)
1282 .addReg(ShiftAmtSrcReg).
addMBB(BB)
1286 BuildMI(LoopBB, dl, TII.
get(MSP430::SUB8ri), ShiftAmtReg2)
1287 .addReg(ShiftAmtReg).
addImm(1);
1295 .addReg(SrcReg).
addMBB(BB)
1307 if (Opc == MSP430::Shl8 || Opc == MSP430::Shl16 ||
1308 Opc == MSP430::Sra8 || Opc == MSP430::Sra16 ||
1309 Opc == MSP430::Srl8 || Opc == MSP430::Srl16)
1315 assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) &&
1316 "Unexpected instr type to insert");
void setFrameAddressIsTaken(bool T)
ValuesClass< DataType > LLVM_END_WITH_NULL values(const char *Arg, DataType Val, const char *Desc,...)
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...
void push_back(const T &Elt)
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
SDValue getValue(unsigned R) const
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
void setRAIndex(int Index)
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
Return with a flag operand. Operand 0 is the chain operand.
MSP430MachineFunctionInfo - This class is derived from MachineFunction and contains private MSP430 ta...
LLVMContext * getContext() const
SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N)
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, SDLoc DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd)...
size_t size() const
size - Get the string size.
BR_CC - Conditional branch.
LocInfo getLocInfo() const
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const
MSP430 conditional branches.
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
Y = RRC X, rotate right via carry.
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3 is condition code and operand 4...
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
unsigned getSizeInBits() const
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
unsigned getByValSize() const
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *fromMBB)
transferSuccessorsAndUpdatePHIs - Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor blocks which refer to fromMBB to refer to this.
const SDValue & getOperand(unsigned Num) const
static void AnalyzeVarArgs(CCState &State, const SmallVectorImpl< ISD::OutputArg > &Outs)
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags=0)
static void ParseFunctionArgs(const SmallVectorImpl< ArgT > &Args, SmallVectorImpl< unsigned > &Out)
For each argument in a function store the number of pieces it is composed of.
static std::error_code getOffset(const SymbolRef &Sym, SectionRef Sec, uint64_t &Result)
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag=true)
Reports a serious error, calling any installed error handler.
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
SDValue getMemcpy(SDValue Chain, SDLoc dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
static MachinePointerInfo getFixedStack(int FI, int64_t offset=0)
getFixedStack - Return a MachinePointerInfo record that refers to the the specified FrameIndex...
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
BlockAddress - The address of a basic block.
SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const TargetRegisterInfo * getRegisterInfo() const override
const HexagonInstrInfo * TII
Shift and rotation operations.
MSP430_INTR - Calling convention used for MSP430 interrupt routines.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MachineFunction & getMachineFunction() const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
SDValue getTargetGlobalAddress(const GlobalValue *GV, SDLoc DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
void addLoc(const CCValAssign &V)
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG...
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
SmallVector< ISD::InputArg, 32 > Ins
SDValue getCALLSEQ_START(SDValue Chain, SDValue Op, SDLoc DL)
Return a new CALLSEQ_START node, which always must have a glue result (to ensure it's not CSE'd)...
Same as RET_FLAG, but used for returning from ISRs.
unsigned getLocReg() const
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
void setVarArgsFrameIndex(int Index)
Simple integer binary arithmetic operators.
SmallVector< ISD::OutputArg, 32 > Outs
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
isTruncateFree - Return true if it's free to truncate a value of type Ty1 to type Ty2...
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
EVT getMemoryVT() const
Return the type of the in-memory value.
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
const DataLayout & getDataLayout() const
const BasicBlock * getBasicBlock() const
getBasicBlock - Return the LLVM basic block that this instance corresponded to originally.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
Flag
These should be considered private to the implementation of the MCInstrDesc class.
TargetInstrInfo - Interface to description of machine instruction set.
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
SDNode * getNode() const
get the SDNode which holds the desired result
bundle_iterator< MachineInstr, instr_iterator > iterator
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
initializer< Ty > init(const Ty &Val)
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
MVT - Machine Value Type.
LLVM Basic Block Representation.
const SDValue & getOperand(unsigned i) const
The instances of the Type class are immutable: once they are created, they are never changed...
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
static cl::opt< HWMultUseMode > HWMultMode("msp430-hwmult-mode", cl::Hidden, cl::desc("Hardware multiplier use mode"), cl::init(HWMultNoIntr), cl::values(clEnumValN(NoHWMult,"no","Do not use hardware multiplier"), clEnumValN(HWMultIntr,"interrupts","Assume hardware multiplier can be used inside interrupts"), clEnumValN(HWMultNoIntr,"use","Assume hardware multiplier cannot be used inside interrupts"), clEnumValEnd))
SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE...
const MachineOperand & getOperand(unsigned i) const
int getVarArgsFrameIndex() const
static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC, ISD::CondCode CC, SDLoc dl, SelectionDAG &DAG)
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT)
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
SetCC - Operand 0 is condition code, and operand 1 is the flag operand produced by a CMP instruction...
unsigned getOpcode() const
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
void setPrefFunctionAlignment(unsigned Align)
Set the target's preferred function alignment.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool Immutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Bit counting operators with an undefined result for zero inputs.
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
EVT - Extended Value Type.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const
MachinePointerInfo - This class contains a discriminated union of information about pointers in memor...
void HandleByVal(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, int MinSize, int MinAlign, ISD::ArgFlagsTy ArgFlags)
Allocate space on the stack large enough to pass an argument by value.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
unsigned getByValAlign() const
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned char TargetFlags=0)
TokenFactor - This node takes multiple tokens as input and produces a single token result...
SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const
CCState - This class holds information needed while lowering arguments and return values...
CMP - Compare instruction.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
MachineBasicBlock * EmitShiftInstr(MachineInstr *MI, MachineBasicBlock *BB) const
CCValAssign - Represent assignment of one arg/retval to a location.
BRCOND - Conditional branch.
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Represents one node in the SelectionDAG.
const char * getTargetNodeName(unsigned Opcode) const override
getTargetNodeName - This method returns the name of a target specific DAG node.
static mvt_range integer_valuetypes()
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
static void AnalyzeRetResult(CCState &State, const SmallVectorImpl< ISD::InputArg > &Ins)
Select(COND, TRUEVAL, FALSEVAL).
void setMinFunctionAlignment(unsigned Align)
Set the target's minimum function alignment (in log2(bytes))
bool isIntegerTy() const
isIntegerTy - True if this is an instance of IntegerType.
ZERO_EXTEND - Used for integer types, zeroing the new bits.
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
ANY_EXTEND - Used for integer types. The high bits are undefined.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
TargetLowering::ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target...
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
BR_JT - Jumptable branch.
Representation of each machine instruction.
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the source.
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned char TargetFlags=0)
SmallVector< SDValue, 32 > OutVals
Bitwise operators - logical and, logical or, logical xor.
SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
static void AnalyzeArguments(CCState &State, SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< ArgT > &Args)
Analyze incoming and outgoing function arguments.
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
Fast - This calling convention attempts to make calls as fast as possible (e.g.
void setStackPointerRegisterToSaveRestore(unsigned R)
If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const
Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol, and TargetGlobalAddress.
EVT getValueType() const
Return the ValueType of the referenced return value.
SDValue getConstant(uint64_t Val, SDLoc DL, EVT VT, bool isTarget=false, bool isOpaque=false)
bool isZExtFree(Type *Ty1, Type *Ty2) const override
isZExtFree - Return true if any actual instruction that defines a value of type Ty1 implicit zero-ext...
unsigned getReg() const
getReg - Returns the register number.
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
void insert(iterator MBBI, MachineBasicBlock *MBB)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
Y = R{R,L}A X, rotate right (left) arithmetically.
void setIntDivIsCheap(bool isCheap=true)
Tells the code generator that integer divide is expensive, and if possible, should be replaced by an ...
void setReturnAddressIsTaken(bool s)
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
unsigned getPrimitiveSizeInBits() const LLVM_READONLY
getPrimitiveSizeInBits - Return the basic size of this type if it is a primitive type.
virtual const TargetInstrInfo * getInstrInfo() const
LLVM Value Representation.
SDValue getRegister(unsigned Reg, EVT VT)
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
CALL - These operations represent an abstract call instruction, which includes a bunch of information...
SDValue getValueType(EVT)
BasicBlockListType::iterator iterator
Primary interface to the complete machine description for the target machine.
C - The default llvm calling convention, compatible with C.
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const
StringRef - Represent a constant reference to a string, i.e.
SetCC operator - This evaluates to a true value iff the condition is true.
unsigned getLocMemOffset() const
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
SHL, SRA, SRL - Non-constant shifts.
TRUNCATE - Completely drop the high bits.
unsigned getPointerSize(unsigned AS=0) const
Layout pointer size FIXME: The defaults need to be removed once all of the backends/clients are updat...
unsigned AllocateReg(unsigned Reg)
AllocateReg - Attempt to allocate one register.
static void AnalyzeReturnValues(CCState &State, SmallVectorImpl< CCValAssign > &RVLocs, const SmallVectorImpl< ArgT > &Args)
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
void addSuccessor(MachineBasicBlock *succ, uint32_t weight=0)
addSuccessor - Add succ as a successor of this MachineBasicBlock.
MSP430TargetLowering(const TargetMachine &TM, const MSP430Subtarget &STI)
MVT getSimpleVT() const
getSimpleVT - Return the SimpleValueType held in the specified simple EVT.
SDValue getIntPtrConstant(uint64_t Val, SDLoc DL, bool isTarget=false)
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
This class is used to represent ISD::LOAD nodes.
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary...