14 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
15 #define LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
22 #define GET_INSTRINFO_HEADER
23 #include "AArch64GenInstrInfo.inc"
27 class AArch64Subtarget;
28 class AArch64TargetMachine;
33 enum TargetMemOperandFlags {
53 unsigned &DstReg,
unsigned &SubIdx)
const override;
98 int &Offset,
int &Width,
104 unsigned NumLoads)
const override;
110 uint64_t Offset,
const MDNode *Var,
113 DebugLoc DL,
unsigned DestReg,
unsigned SrcReg,
114 bool KillSrc,
unsigned Opcode,
117 DebugLoc DL,
unsigned DestReg,
unsigned SrcReg,
118 bool KillSrc)
const override;
140 bool AllowModify =
false)
const override;
148 unsigned,
unsigned,
int &,
int &,
int &)
const override;
151 unsigned TrueReg,
unsigned FalseReg)
const override;
158 unsigned &SrcReg2,
int &CmpMask,
159 int &CmpValue)
const override;
163 unsigned SrcReg2,
int CmpMask,
int CmpValue,
195 DebugLoc DL,
unsigned DestReg,
unsigned SrcReg,
int Offset,
196 const TargetInstrInfo *
TII,
198 bool SetNZCV =
false);
204 unsigned FrameReg,
int &Offset,
205 const AArch64InstrInfo *
TII);
229 bool *OutUseUnscaledOp =
nullptr,
230 unsigned *OutUnscaledOp =
nullptr,
231 int *EmittableOffset =
nullptr);
bool hasExtendedReg(const MachineInstr *MI) const
Returns true if there is an extendable register and that the extending value is non-zero.
unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const override
bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const override
optimizeCompareInstr - Convert the instruction supplying the argument to the comparison into one that...
const AArch64RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex) const override
bool getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg, unsigned &Offset, const TargetRegisterInfo *TRI) const override
Offset can apply, at least partly.
void getNoopForMachoTarget(MCInst &NopInst) const override
bool ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
bool optimizeCondBranch(MachineInstr *MI) const override
Replace csincr-branch sequence by simple conditional branch.
bool isLdStPairSuppressed(const MachineInstr *MI) const
Return true if pairing the given load or store is hinted to be unprofitable.
bool getMemOpBaseRegImmOfsWidth(MachineInstr *LdSt, unsigned &BaseReg, int &Offset, int &Width, const TargetRegisterInfo *TRI) const
const HexagonInstrInfo * TII
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
bool useMachineCombiner() const override
useMachineCombiner - AArch64 supports MachineCombiner
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, DebugLoc DL) const override
int isAArch64FrameOffsetLegal(const MachineInstr &MI, int &Offset, bool *OutUseUnscaledOp=nullptr, unsigned *OutUnscaledOp=nullptr, int *EmittableOffset=nullptr)
Check if the Offset is a valid frame offset for MI.
AArch64InstrInfo(const AArch64Subtarget &STI)
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
MachineInstr * emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx, uint64_t Offset, const MDNode *Var, const MDNode *Expr, DebugLoc DL) const
bool isAsCheapAsAMove(const MachineInstr *MI) const override
bool enableClusterLoads() const override
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override
bool hasShiftedReg(const MachineInstr *MI) const
Returns true if there is a shiftable register and that the shift value is non-zero.
Instances of this class represent a single low-level machine instruction.
static bool isCondBranchOpcode(int Opc)
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern::MC_PATTERN > &Patterns) const override
Return true when there is potentially a faster code sequence for an instruction chain ending in <Root...
bundle_iterator< MachineInstr, instr_iterator > iterator
unsigned RemoveBranch(MachineBasicBlock &MBB) const override
Control flow instructions. These all have token chains.
void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, int Offset, const TargetInstrInfo *TII, MachineInstr::MIFlag=MachineInstr::NoFlags, bool SetNZCV=false)
emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg plus Offset.
bool isFPRCopy(const MachineInstr *MI) const
Does this instruction rename an FPR without modifying bits?
bundle_iterator - MachineBasicBlock iterator that automatically skips over MIs that are inside bundle...
bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const AArch64InstrInfo *TII)
rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the FP.
bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
bool isGPRZero(const MachineInstr *MI) const
Does this instruction set its full destination register to zero?
bool shouldScheduleAdjacent(MachineInstr *First, MachineInstr *Second) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override
AArch64FrameOffsetStatus
Use to report the frame offset status in isAArch64FrameOffsetLegal.
bool shouldClusterLoads(MachineInstr *FirstLdSt, MachineInstr *SecondLdSt, unsigned NumLoads) const override
Detect opportunities for ldp/stp formation.
static bool isIndirectBranchOpcode(int Opc)
void suppressLdStPair(MachineInstr *MI) const
Hint that pairing the given load or store is unprofitable.
unsigned GetInstSizeInBytes(const MachineInstr *MI) const
GetInstSize - Return the number of bytes of code the specified instruction may be.
static bool isUncondBranchOpcode(int Opc)
void copyPhysRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc, unsigned Opcode, llvm::ArrayRef< unsigned > Indices) const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
bool isGPRCopy(const MachineInstr *MI) const
Does this instruction rename a GPR without modifying bits?
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
void genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern::MC_PATTERN Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could...
bool areMemAccessesTriviallyDisjoint(MachineInstr *MIa, MachineInstr *MIb, AliasAnalysis *AA=nullptr) const override
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex) const
Target-dependent implementation for foldMemoryOperand.
unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const override
bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const override
analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2...
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
bool isScaledAddr(const MachineInstr *MI) const
Return true if this is load/store scales or extends its register offset.
bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override