LLVM  3.7.0
HexagonDisassembler.cpp
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1 //===-- HexagonDisassembler.cpp - Disassembler for Hexagon ISA ------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "Hexagon.h"
14 
15 #include "llvm/MC/MCContext.h"
16 #include "llvm/MC/MCDisassembler.h"
17 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrDesc.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/Endian.h"
25 #include "llvm/Support/LEB128.h"
28 #include <array>
29 #include <vector>
30 
31 using namespace llvm;
32 using namespace Hexagon;
33 
34 #define DEBUG_TYPE "hexagon-disassembler"
35 
36 // Pull DecodeStatus and its enum values into the global namespace.
38 
39 namespace {
40 /// \brief Hexagon disassembler for all Hexagon platforms.
41 class HexagonDisassembler : public MCDisassembler {
42 public:
43  std::unique_ptr<MCInst *> CurrentBundle;
44  HexagonDisassembler(MCSubtargetInfo const &STI, MCContext &Ctx)
45  : MCDisassembler(STI, Ctx), CurrentBundle(new MCInst *) {}
46 
47  DecodeStatus getSingleInstruction(MCInst &Instr, MCInst &MCB,
48  ArrayRef<uint8_t> Bytes, uint64_t Address,
49  raw_ostream &VStream, raw_ostream &CStream,
50  bool &Complete) const;
51  DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
52  ArrayRef<uint8_t> Bytes, uint64_t Address,
53  raw_ostream &VStream,
54  raw_ostream &CStream) const override;
55 };
56 }
57 
58 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
59  uint64_t Address,
60  const void *Decoder);
61 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
62  uint64_t Address,
63  const void *Decoder);
64 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
65  uint64_t Address,
66  void const *Decoder);
67 
68 static unsigned GetSubinstOpcode(unsigned IClass, unsigned inst, unsigned &op,
69  raw_ostream &os);
70 static void AddSubinstOperands(MCInst *MI, unsigned opcode, unsigned inst);
71 
72 static DecodeStatus s16ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
73  const void *Decoder);
74 static DecodeStatus s12ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
75  const void *Decoder);
76 static DecodeStatus s11_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
77  const void *Decoder);
78 static DecodeStatus s11_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
79  const void *Decoder);
80 static DecodeStatus s11_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
81  const void *Decoder);
82 static DecodeStatus s11_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
83  const void *Decoder);
84 static DecodeStatus s10ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
85  const void *Decoder);
86 static DecodeStatus s8ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
87  const void *Decoder);
88 static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
89  const void *Decoder);
90 static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
91  const void *Decoder);
92 static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
93  const void *Decoder);
94 static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
95  const void *Decoder);
96 static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
97  const void *Decoder);
98 
99 static const uint16_t IntRegDecoderTable[] = {
100  Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
101  Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9,
102  Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,
103  Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
104  Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24,
105  Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29,
106  Hexagon::R30, Hexagon::R31};
107 
108 static const uint16_t PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1,
109  Hexagon::P2, Hexagon::P3};
110 
111 static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo,
112  const uint16_t Table[], size_t Size) {
113  if (RegNo < Size) {
114  Inst.addOperand(MCOperand::createReg(Table[RegNo]));
116  } else
117  return MCDisassembler::Fail;
118 }
119 
120 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
121  uint64_t /*Address*/,
122  void const *Decoder) {
123  if (RegNo > 31)
124  return MCDisassembler::Fail;
125 
126  unsigned Register = IntRegDecoderTable[RegNo];
127  Inst.addOperand(MCOperand::createReg(Register));
129 }
130 
131 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
132  uint64_t /*Address*/,
133  const void *Decoder) {
134  static const uint16_t CtrlRegDecoderTable[] = {
135  Hexagon::SA0, Hexagon::LC0, Hexagon::SA1, Hexagon::LC1,
136  Hexagon::P3_0, Hexagon::NoRegister, Hexagon::C6, Hexagon::C7,
137  Hexagon::USR, Hexagon::PC, Hexagon::UGP, Hexagon::GP,
138  Hexagon::CS0, Hexagon::CS1, Hexagon::UPCL, Hexagon::UPCH};
139 
140  if (RegNo >= sizeof(CtrlRegDecoderTable) / sizeof(CtrlRegDecoderTable[0]))
141  return MCDisassembler::Fail;
142 
143  if (CtrlRegDecoderTable[RegNo] == Hexagon::NoRegister)
144  return MCDisassembler::Fail;
145 
146  unsigned Register = CtrlRegDecoderTable[RegNo];
147  Inst.addOperand(MCOperand::createReg(Register));
149 }
150 
151 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
152  uint64_t /*Address*/,
153  void const *Decoder) {
154  static const uint16_t CtrlReg64DecoderTable[] = {
155  Hexagon::C1_0, Hexagon::NoRegister, Hexagon::C3_2,
156  Hexagon::NoRegister, Hexagon::NoRegister, Hexagon::NoRegister,
157  Hexagon::C7_6, Hexagon::NoRegister, Hexagon::C9_8,
158  Hexagon::NoRegister, Hexagon::C11_10, Hexagon::NoRegister,
159  Hexagon::CS, Hexagon::NoRegister, Hexagon::UPC,
160  Hexagon::NoRegister};
161 
162  if (RegNo >= sizeof(CtrlReg64DecoderTable) / sizeof(CtrlReg64DecoderTable[0]))
163  return MCDisassembler::Fail;
164 
165  if (CtrlReg64DecoderTable[RegNo] == Hexagon::NoRegister)
166  return MCDisassembler::Fail;
167 
168  unsigned Register = CtrlReg64DecoderTable[RegNo];
169  Inst.addOperand(MCOperand::createReg(Register));
171 }
172 
173 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
174  uint64_t /*Address*/,
175  const void *Decoder) {
176  unsigned Register = 0;
177  switch (RegNo) {
178  case 0:
179  Register = Hexagon::M0;
180  break;
181  case 1:
182  Register = Hexagon::M1;
183  break;
184  default:
185  return MCDisassembler::Fail;
186  }
187  Inst.addOperand(MCOperand::createReg(Register));
189 }
190 
191 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,
192  uint64_t /*Address*/,
193  const void *Decoder) {
194  static const uint16_t DoubleRegDecoderTable[] = {
195  Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,
196  Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7,
197  Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11,
198  Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15};
199 
200  return (DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable,
201  sizeof(DoubleRegDecoderTable)));
202 }
203 
204 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
205  uint64_t /*Address*/,
206  void const *Decoder) {
207  if (RegNo > 3)
208  return MCDisassembler::Fail;
209 
210  unsigned Register = PredRegDecoderTable[RegNo];
211  Inst.addOperand(MCOperand::createReg(Register));
213 }
214 
215 #include "HexagonGenDisassemblerTables.inc"
216 
218  MCSubtargetInfo const &STI,
219  MCContext &Ctx) {
220  return new HexagonDisassembler(STI, Ctx);
221 }
222 
226 }
227 
228 DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
229  ArrayRef<uint8_t> Bytes,
230  uint64_t Address,
231  raw_ostream &os,
232  raw_ostream &cs) const {
234  bool Complete = false;
235  Size = 0;
236 
237  *CurrentBundle = &MI;
240  while (Result == Success && Complete == false) {
241  if (Bytes.size() < HEXAGON_INSTR_SIZE)
242  return MCDisassembler::Fail;
243  MCInst *Inst = new (getContext()) MCInst;
244  Result = getSingleInstruction(*Inst, MI, Bytes, Address, os, cs, Complete);
246  Size += HEXAGON_INSTR_SIZE;
247  Bytes = Bytes.slice(HEXAGON_INSTR_SIZE);
248  }
249  return Result;
250 }
251 
252 DecodeStatus HexagonDisassembler::getSingleInstruction(
253  MCInst &MI, MCInst &MCB, ArrayRef<uint8_t> Bytes, uint64_t Address,
254  raw_ostream &os, raw_ostream &cs, bool &Complete) const {
255  assert(Bytes.size() >= HEXAGON_INSTR_SIZE);
256 
257  uint32_t Instruction =
259  llvm::support::unaligned>(Bytes.data());
260 
261  auto BundleSize = HexagonMCInstrInfo::bundleSize(MCB);
262  if ((Instruction & HexagonII::INST_PARSE_MASK) ==
264  if (BundleSize == 0)
266  else if (BundleSize == 1)
268  else
269  return DecodeStatus::Fail;
270  }
271 
273  if ((Instruction & HexagonII::INST_PARSE_MASK) ==
275  // Determine the instruction class of each instruction in the duplex.
276  unsigned duplexIClass, IClassLow, IClassHigh;
277 
278  duplexIClass = ((Instruction >> 28) & 0xe) | ((Instruction >> 13) & 0x1);
279  switch (duplexIClass) {
280  default:
281  return MCDisassembler::Fail;
282  case 0:
283  IClassLow = HexagonII::HSIG_L1;
284  IClassHigh = HexagonII::HSIG_L1;
285  break;
286  case 1:
287  IClassLow = HexagonII::HSIG_L2;
288  IClassHigh = HexagonII::HSIG_L1;
289  break;
290  case 2:
291  IClassLow = HexagonII::HSIG_L2;
292  IClassHigh = HexagonII::HSIG_L2;
293  break;
294  case 3:
295  IClassLow = HexagonII::HSIG_A;
296  IClassHigh = HexagonII::HSIG_A;
297  break;
298  case 4:
299  IClassLow = HexagonII::HSIG_L1;
300  IClassHigh = HexagonII::HSIG_A;
301  break;
302  case 5:
303  IClassLow = HexagonII::HSIG_L2;
304  IClassHigh = HexagonII::HSIG_A;
305  break;
306  case 6:
307  IClassLow = HexagonII::HSIG_S1;
308  IClassHigh = HexagonII::HSIG_A;
309  break;
310  case 7:
311  IClassLow = HexagonII::HSIG_S2;
312  IClassHigh = HexagonII::HSIG_A;
313  break;
314  case 8:
315  IClassLow = HexagonII::HSIG_S1;
316  IClassHigh = HexagonII::HSIG_L1;
317  break;
318  case 9:
319  IClassLow = HexagonII::HSIG_S1;
320  IClassHigh = HexagonII::HSIG_L2;
321  break;
322  case 10:
323  IClassLow = HexagonII::HSIG_S1;
324  IClassHigh = HexagonII::HSIG_S1;
325  break;
326  case 11:
327  IClassLow = HexagonII::HSIG_S2;
328  IClassHigh = HexagonII::HSIG_S1;
329  break;
330  case 12:
331  IClassLow = HexagonII::HSIG_S2;
332  IClassHigh = HexagonII::HSIG_L1;
333  break;
334  case 13:
335  IClassLow = HexagonII::HSIG_S2;
336  IClassHigh = HexagonII::HSIG_L2;
337  break;
338  case 14:
339  IClassLow = HexagonII::HSIG_S2;
340  IClassHigh = HexagonII::HSIG_S2;
341  break;
342  }
343 
344  // Set the MCInst to be a duplex instruction. Which one doesn't matter.
345  MI.setOpcode(Hexagon::DuplexIClass0);
346 
347  // Decode each instruction in the duplex.
348  // Create an MCInst for each instruction.
349  unsigned instLow = Instruction & 0x1fff;
350  unsigned instHigh = (Instruction >> 16) & 0x1fff;
351  unsigned opLow;
352  if (GetSubinstOpcode(IClassLow, instLow, opLow, os) !=
354  return MCDisassembler::Fail;
355  unsigned opHigh;
356  if (GetSubinstOpcode(IClassHigh, instHigh, opHigh, os) !=
358  return MCDisassembler::Fail;
359  MCInst *MILow = new (getContext()) MCInst;
360  MILow->setOpcode(opLow);
361  MCInst *MIHigh = new (getContext()) MCInst;
362  MIHigh->setOpcode(opHigh);
363  AddSubinstOperands(MILow, opLow, instLow);
364  AddSubinstOperands(MIHigh, opHigh, instHigh);
365  // see ConvertToSubInst() in
366  // lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp
367 
368  // Add the duplex instruction MCInsts as operands to the passed in MCInst.
369  MCOperand OPLow = MCOperand::createInst(MILow);
370  MCOperand OPHigh = MCOperand::createInst(MIHigh);
371  MI.addOperand(OPLow);
372  MI.addOperand(OPHigh);
373  Complete = true;
374  } else {
375  if ((Instruction & HexagonII::INST_PARSE_MASK) ==
377  Complete = true;
378  // Calling the auto-generated decoder function.
379  Result =
380  decodeInstruction(DecoderTable32, MI, Instruction, Address, this, STI);
381  }
382 
383  return Result;
384 }
385 
386 static DecodeStatus s16ImmDecoder(MCInst &MI, unsigned tmp,
387  uint64_t /*Address*/, const void *Decoder) {
388  uint64_t imm = SignExtend64<16>(tmp);
391 }
392 
393 static DecodeStatus s12ImmDecoder(MCInst &MI, unsigned tmp,
394  uint64_t /*Address*/, const void *Decoder) {
395  uint64_t imm = SignExtend64<12>(tmp);
398 }
399 
400 static DecodeStatus s11_0ImmDecoder(MCInst &MI, unsigned tmp,
401  uint64_t /*Address*/, const void *Decoder) {
402  uint64_t imm = SignExtend64<11>(tmp);
405 }
406 
407 static DecodeStatus s11_1ImmDecoder(MCInst &MI, unsigned tmp,
408  uint64_t /*Address*/, const void *Decoder) {
409  uint64_t imm = SignExtend64<12>(tmp);
412 }
413 
414 static DecodeStatus s11_2ImmDecoder(MCInst &MI, unsigned tmp,
415  uint64_t /*Address*/, const void *Decoder) {
416  uint64_t imm = SignExtend64<13>(tmp);
419 }
420 
421 static DecodeStatus s11_3ImmDecoder(MCInst &MI, unsigned tmp,
422  uint64_t /*Address*/, const void *Decoder) {
423  uint64_t imm = SignExtend64<14>(tmp);
426 }
427 
428 static DecodeStatus s10ImmDecoder(MCInst &MI, unsigned tmp,
429  uint64_t /*Address*/, const void *Decoder) {
430  uint64_t imm = SignExtend64<10>(tmp);
433 }
434 
435 static DecodeStatus s8ImmDecoder(MCInst &MI, unsigned tmp, uint64_t /*Address*/,
436  const void *Decoder) {
437  uint64_t imm = SignExtend64<8>(tmp);
440 }
441 
442 static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp,
443  uint64_t /*Address*/, const void *Decoder) {
444  uint64_t imm = SignExtend64<6>(tmp);
447 }
448 
449 static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp,
450  uint64_t /*Address*/, const void *Decoder) {
451  uint64_t imm = SignExtend64<4>(tmp);
454 }
455 
456 static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp,
457  uint64_t /*Address*/, const void *Decoder) {
458  uint64_t imm = SignExtend64<5>(tmp);
461 }
462 
463 static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp,
464  uint64_t /*Address*/, const void *Decoder) {
465  uint64_t imm = SignExtend64<6>(tmp);
468 }
469 
470 static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp,
471  uint64_t /*Address*/, const void *Decoder) {
472  uint64_t imm = SignExtend64<7>(tmp);
475 }
476 
477 // These values are from HexagonGenMCCodeEmitter.inc and HexagonIsetDx.td
509  V4_SA1_dec_BITS = 0x1300,
510  V4_SA1_dec_MASK = 0x1f00,
511  V4_SA1_inc_BITS = 0x1100,
512  V4_SA1_inc_MASK = 0x1f00,
521  V4_SA1_tfr_BITS = 0x1000,
522  V4_SA1_tfr_MASK = 0x1f00,
583 };
584 
585 static unsigned GetSubinstOpcode(unsigned IClass, unsigned inst, unsigned &op,
586  raw_ostream &os) {
587  switch (IClass) {
588  case HexagonII::HSIG_L1:
590  op = Hexagon::V4_SL1_loadri_io;
591  else if ((inst & V4_SL1_loadrub_io_MASK) == V4_SL1_loadrub_io_BITS)
592  op = Hexagon::V4_SL1_loadrub_io;
593  else {
594  os << "<unknown subinstruction>";
595  return MCDisassembler::Fail;
596  }
597  break;
598  case HexagonII::HSIG_L2:
600  op = Hexagon::V4_SL2_deallocframe;
601  else if ((inst & V4_SL2_jumpr31_MASK) == V4_SL2_jumpr31_BITS)
602  op = Hexagon::V4_SL2_jumpr31;
603  else if ((inst & V4_SL2_jumpr31_f_MASK) == V4_SL2_jumpr31_f_BITS)
604  op = Hexagon::V4_SL2_jumpr31_f;
606  op = Hexagon::V4_SL2_jumpr31_fnew;
607  else if ((inst & V4_SL2_jumpr31_t_MASK) == V4_SL2_jumpr31_t_BITS)
608  op = Hexagon::V4_SL2_jumpr31_t;
610  op = Hexagon::V4_SL2_jumpr31_tnew;
611  else if ((inst & V4_SL2_loadrb_io_MASK) == V4_SL2_loadrb_io_BITS)
612  op = Hexagon::V4_SL2_loadrb_io;
613  else if ((inst & V4_SL2_loadrd_sp_MASK) == V4_SL2_loadrd_sp_BITS)
614  op = Hexagon::V4_SL2_loadrd_sp;
615  else if ((inst & V4_SL2_loadrh_io_MASK) == V4_SL2_loadrh_io_BITS)
616  op = Hexagon::V4_SL2_loadrh_io;
617  else if ((inst & V4_SL2_loadri_sp_MASK) == V4_SL2_loadri_sp_BITS)
618  op = Hexagon::V4_SL2_loadri_sp;
619  else if ((inst & V4_SL2_loadruh_io_MASK) == V4_SL2_loadruh_io_BITS)
620  op = Hexagon::V4_SL2_loadruh_io;
621  else if ((inst & V4_SL2_return_MASK) == V4_SL2_return_BITS)
622  op = Hexagon::V4_SL2_return;
623  else if ((inst & V4_SL2_return_f_MASK) == V4_SL2_return_f_BITS)
624  op = Hexagon::V4_SL2_return_f;
626  op = Hexagon::V4_SL2_return_fnew;
627  else if ((inst & V4_SL2_return_t_MASK) == V4_SL2_return_t_BITS)
628  op = Hexagon::V4_SL2_return_t;
630  op = Hexagon::V4_SL2_return_tnew;
631  else {
632  os << "<unknown subinstruction>";
633  return MCDisassembler::Fail;
634  }
635  break;
636  case HexagonII::HSIG_A:
637  if ((inst & V4_SA1_addi_MASK) == V4_SA1_addi_BITS)
638  op = Hexagon::V4_SA1_addi;
639  else if ((inst & V4_SA1_addrx_MASK) == V4_SA1_addrx_BITS)
640  op = Hexagon::V4_SA1_addrx;
641  else if ((inst & V4_SA1_addsp_MASK) == V4_SA1_addsp_BITS)
642  op = Hexagon::V4_SA1_addsp;
643  else if ((inst & V4_SA1_and1_MASK) == V4_SA1_and1_BITS)
644  op = Hexagon::V4_SA1_and1;
645  else if ((inst & V4_SA1_clrf_MASK) == V4_SA1_clrf_BITS)
646  op = Hexagon::V4_SA1_clrf;
647  else if ((inst & V4_SA1_clrfnew_MASK) == V4_SA1_clrfnew_BITS)
648  op = Hexagon::V4_SA1_clrfnew;
649  else if ((inst & V4_SA1_clrt_MASK) == V4_SA1_clrt_BITS)
650  op = Hexagon::V4_SA1_clrt;
651  else if ((inst & V4_SA1_clrtnew_MASK) == V4_SA1_clrtnew_BITS)
652  op = Hexagon::V4_SA1_clrtnew;
653  else if ((inst & V4_SA1_cmpeqi_MASK) == V4_SA1_cmpeqi_BITS)
654  op = Hexagon::V4_SA1_cmpeqi;
655  else if ((inst & V4_SA1_combine0i_MASK) == V4_SA1_combine0i_BITS)
656  op = Hexagon::V4_SA1_combine0i;
657  else if ((inst & V4_SA1_combine1i_MASK) == V4_SA1_combine1i_BITS)
658  op = Hexagon::V4_SA1_combine1i;
659  else if ((inst & V4_SA1_combine2i_MASK) == V4_SA1_combine2i_BITS)
660  op = Hexagon::V4_SA1_combine2i;
661  else if ((inst & V4_SA1_combine3i_MASK) == V4_SA1_combine3i_BITS)
662  op = Hexagon::V4_SA1_combine3i;
663  else if ((inst & V4_SA1_combinerz_MASK) == V4_SA1_combinerz_BITS)
664  op = Hexagon::V4_SA1_combinerz;
665  else if ((inst & V4_SA1_combinezr_MASK) == V4_SA1_combinezr_BITS)
666  op = Hexagon::V4_SA1_combinezr;
667  else if ((inst & V4_SA1_dec_MASK) == V4_SA1_dec_BITS)
668  op = Hexagon::V4_SA1_dec;
669  else if ((inst & V4_SA1_inc_MASK) == V4_SA1_inc_BITS)
670  op = Hexagon::V4_SA1_inc;
671  else if ((inst & V4_SA1_seti_MASK) == V4_SA1_seti_BITS)
672  op = Hexagon::V4_SA1_seti;
673  else if ((inst & V4_SA1_setin1_MASK) == V4_SA1_setin1_BITS)
674  op = Hexagon::V4_SA1_setin1;
675  else if ((inst & V4_SA1_sxtb_MASK) == V4_SA1_sxtb_BITS)
676  op = Hexagon::V4_SA1_sxtb;
677  else if ((inst & V4_SA1_sxth_MASK) == V4_SA1_sxth_BITS)
678  op = Hexagon::V4_SA1_sxth;
679  else if ((inst & V4_SA1_tfr_MASK) == V4_SA1_tfr_BITS)
680  op = Hexagon::V4_SA1_tfr;
681  else if ((inst & V4_SA1_zxtb_MASK) == V4_SA1_zxtb_BITS)
682  op = Hexagon::V4_SA1_zxtb;
683  else if ((inst & V4_SA1_zxth_MASK) == V4_SA1_zxth_BITS)
684  op = Hexagon::V4_SA1_zxth;
685  else {
686  os << "<unknown subinstruction>";
687  return MCDisassembler::Fail;
688  }
689  break;
690  case HexagonII::HSIG_S1:
692  op = Hexagon::V4_SS1_storeb_io;
693  else if ((inst & V4_SS1_storew_io_MASK) == V4_SS1_storew_io_BITS)
694  op = Hexagon::V4_SS1_storew_io;
695  else {
696  os << "<unknown subinstruction>";
697  return MCDisassembler::Fail;
698  }
699  break;
700  case HexagonII::HSIG_S2:
702  op = Hexagon::V4_SS2_allocframe;
703  else if ((inst & V4_SS2_storebi0_MASK) == V4_SS2_storebi0_BITS)
704  op = Hexagon::V4_SS2_storebi0;
705  else if ((inst & V4_SS2_storebi1_MASK) == V4_SS2_storebi1_BITS)
706  op = Hexagon::V4_SS2_storebi1;
707  else if ((inst & V4_SS2_stored_sp_MASK) == V4_SS2_stored_sp_BITS)
708  op = Hexagon::V4_SS2_stored_sp;
709  else if ((inst & V4_SS2_storeh_io_MASK) == V4_SS2_storeh_io_BITS)
710  op = Hexagon::V4_SS2_storeh_io;
711  else if ((inst & V4_SS2_storew_sp_MASK) == V4_SS2_storew_sp_BITS)
712  op = Hexagon::V4_SS2_storew_sp;
713  else if ((inst & V4_SS2_storewi0_MASK) == V4_SS2_storewi0_BITS)
714  op = Hexagon::V4_SS2_storewi0;
715  else if ((inst & V4_SS2_storewi1_MASK) == V4_SS2_storewi1_BITS)
716  op = Hexagon::V4_SS2_storewi1;
717  else {
718  os << "<unknown subinstruction>";
719  return MCDisassembler::Fail;
720  }
721  break;
722  default:
723  os << "<unknown>";
724  return MCDisassembler::Fail;
725  }
727 }
728 
729 static unsigned getRegFromSubinstEncoding(unsigned encoded_reg) {
730  if (encoded_reg < 8)
731  return Hexagon::R0 + encoded_reg;
732  else if (encoded_reg < 16)
733  return Hexagon::R0 + encoded_reg + 8;
734  return Hexagon::NoRegister;
735 }
736 
737 static unsigned getDRegFromSubinstEncoding(unsigned encoded_dreg) {
738  if (encoded_dreg < 4)
739  return Hexagon::D0 + encoded_dreg;
740  else if (encoded_dreg < 8)
741  return Hexagon::D0 + encoded_dreg + 4;
742  return Hexagon::NoRegister;
743 }
744 
745 static void AddSubinstOperands(MCInst *MI, unsigned opcode, unsigned inst) {
746  int64_t operand;
747  MCOperand Op;
748  switch (opcode) {
749  case Hexagon::V4_SL2_deallocframe:
750  case Hexagon::V4_SL2_jumpr31:
751  case Hexagon::V4_SL2_jumpr31_f:
752  case Hexagon::V4_SL2_jumpr31_fnew:
753  case Hexagon::V4_SL2_jumpr31_t:
754  case Hexagon::V4_SL2_jumpr31_tnew:
755  case Hexagon::V4_SL2_return:
756  case Hexagon::V4_SL2_return_f:
757  case Hexagon::V4_SL2_return_fnew:
758  case Hexagon::V4_SL2_return_t:
759  case Hexagon::V4_SL2_return_tnew:
760  // no operands for these instructions
761  break;
762  case Hexagon::V4_SS2_allocframe:
763  // u 8-4{5_3}
764  operand = ((inst & 0x1f0) >> 4) << 3;
765  Op = MCOperand::createImm(operand);
766  MI->addOperand(Op);
767  break;
768  case Hexagon::V4_SL1_loadri_io:
769  // Rd 3-0, Rs 7-4, u 11-8{4_2}
770  operand = getRegFromSubinstEncoding(inst & 0xf);
771  Op = MCOperand::createReg(operand);
772  MI->addOperand(Op);
773  operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
774  Op = MCOperand::createReg(operand);
775  MI->addOperand(Op);
776  operand = (inst & 0xf00) >> 6;
777  Op = MCOperand::createImm(operand);
778  MI->addOperand(Op);
779  break;
780  case Hexagon::V4_SL1_loadrub_io:
781  // Rd 3-0, Rs 7-4, u 11-8
782  operand = getRegFromSubinstEncoding(inst & 0xf);
783  Op = MCOperand::createReg(operand);
784  MI->addOperand(Op);
785  operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
786  Op = MCOperand::createReg(operand);
787  MI->addOperand(Op);
788  operand = (inst & 0xf00) >> 8;
789  Op = MCOperand::createImm(operand);
790  MI->addOperand(Op);
791  break;
792  case Hexagon::V4_SL2_loadrb_io:
793  // Rd 3-0, Rs 7-4, u 10-8
794  operand = getRegFromSubinstEncoding(inst & 0xf);
795  Op = MCOperand::createReg(operand);
796  MI->addOperand(Op);
797  operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
798  Op = MCOperand::createReg(operand);
799  MI->addOperand(Op);
800  operand = (inst & 0x700) >> 8;
801  Op = MCOperand::createImm(operand);
802  MI->addOperand(Op);
803  break;
804  case Hexagon::V4_SL2_loadrh_io:
805  case Hexagon::V4_SL2_loadruh_io:
806  // Rd 3-0, Rs 7-4, u 10-8{3_1}
807  operand = getRegFromSubinstEncoding(inst & 0xf);
808  Op = MCOperand::createReg(operand);
809  MI->addOperand(Op);
810  operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
811  Op = MCOperand::createReg(operand);
812  MI->addOperand(Op);
813  operand = ((inst & 0x700) >> 8) << 1;
814  Op = MCOperand::createImm(operand);
815  MI->addOperand(Op);
816  break;
817  case Hexagon::V4_SL2_loadrd_sp:
818  // Rdd 2-0, u 7-3{5_3}
819  operand = getDRegFromSubinstEncoding(inst & 0x7);
820  Op = MCOperand::createReg(operand);
821  MI->addOperand(Op);
822  operand = ((inst & 0x0f8) >> 3) << 3;
823  Op = MCOperand::createImm(operand);
824  MI->addOperand(Op);
825  break;
826  case Hexagon::V4_SL2_loadri_sp:
827  // Rd 3-0, u 8-4{5_2}
828  operand = getRegFromSubinstEncoding(inst & 0xf);
829  Op = MCOperand::createReg(operand);
830  MI->addOperand(Op);
831  operand = ((inst & 0x1f0) >> 4) << 2;
832  Op = MCOperand::createImm(operand);
833  MI->addOperand(Op);
834  break;
835  case Hexagon::V4_SA1_addi:
836  // Rx 3-0 (x2), s7 10-4
837  operand = getRegFromSubinstEncoding(inst & 0xf);
838  Op = MCOperand::createReg(operand);
839  MI->addOperand(Op);
840  MI->addOperand(Op);
841  operand = SignExtend64<7>((inst & 0x7f0) >> 4);
842  Op = MCOperand::createImm(operand);
843  MI->addOperand(Op);
844  break;
845  case Hexagon::V4_SA1_addrx:
846  // Rx 3-0 (x2), Rs 7-4
847  operand = getRegFromSubinstEncoding(inst & 0xf);
848  Op = MCOperand::createReg(operand);
849  MI->addOperand(Op);
850  MI->addOperand(Op);
851  operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
852  Op = MCOperand::createReg(operand);
853  MI->addOperand(Op);
854  case Hexagon::V4_SA1_and1:
855  case Hexagon::V4_SA1_dec:
856  case Hexagon::V4_SA1_inc:
857  case Hexagon::V4_SA1_sxtb:
858  case Hexagon::V4_SA1_sxth:
859  case Hexagon::V4_SA1_tfr:
860  case Hexagon::V4_SA1_zxtb:
861  case Hexagon::V4_SA1_zxth:
862  // Rd 3-0, Rs 7-4
863  operand = getRegFromSubinstEncoding(inst & 0xf);
864  Op = MCOperand::createReg(operand);
865  MI->addOperand(Op);
866  operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
867  Op = MCOperand::createReg(operand);
868  MI->addOperand(Op);
869  break;
870  case Hexagon::V4_SA1_addsp:
871  // Rd 3-0, u 9-4{6_2}
872  operand = getRegFromSubinstEncoding(inst & 0xf);
873  Op = MCOperand::createReg(operand);
874  MI->addOperand(Op);
875  operand = ((inst & 0x3f0) >> 4) << 2;
876  Op = MCOperand::createImm(operand);
877  MI->addOperand(Op);
878  break;
879  case Hexagon::V4_SA1_seti:
880  // Rd 3-0, u 9-4
881  operand = getRegFromSubinstEncoding(inst & 0xf);
882  Op = MCOperand::createReg(operand);
883  MI->addOperand(Op);
884  operand = (inst & 0x3f0) >> 4;
885  Op = MCOperand::createImm(operand);
886  MI->addOperand(Op);
887  break;
888  case Hexagon::V4_SA1_clrf:
889  case Hexagon::V4_SA1_clrfnew:
890  case Hexagon::V4_SA1_clrt:
891  case Hexagon::V4_SA1_clrtnew:
892  case Hexagon::V4_SA1_setin1:
893  // Rd 3-0
894  operand = getRegFromSubinstEncoding(inst & 0xf);
895  Op = MCOperand::createReg(operand);
896  MI->addOperand(Op);
897  break;
898  case Hexagon::V4_SA1_cmpeqi:
899  // Rs 7-4, u 1-0
900  operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
901  Op = MCOperand::createReg(operand);
902  MI->addOperand(Op);
903  operand = inst & 0x3;
904  Op = MCOperand::createImm(operand);
905  MI->addOperand(Op);
906  break;
907  case Hexagon::V4_SA1_combine0i:
908  case Hexagon::V4_SA1_combine1i:
909  case Hexagon::V4_SA1_combine2i:
910  case Hexagon::V4_SA1_combine3i:
911  // Rdd 2-0, u 6-5
912  operand = getDRegFromSubinstEncoding(inst & 0x7);
913  Op = MCOperand::createReg(operand);
914  MI->addOperand(Op);
915  operand = (inst & 0x060) >> 5;
916  Op = MCOperand::createImm(operand);
917  MI->addOperand(Op);
918  break;
919  case Hexagon::V4_SA1_combinerz:
920  case Hexagon::V4_SA1_combinezr:
921  // Rdd 2-0, Rs 7-4
922  operand = getDRegFromSubinstEncoding(inst & 0x7);
923  Op = MCOperand::createReg(operand);
924  MI->addOperand(Op);
925  operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
926  Op = MCOperand::createReg(operand);
927  MI->addOperand(Op);
928  break;
929  case Hexagon::V4_SS1_storeb_io:
930  // Rs 7-4, u 11-8, Rt 3-0
931  operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
932  Op = MCOperand::createReg(operand);
933  MI->addOperand(Op);
934  operand = (inst & 0xf00) >> 8;
935  Op = MCOperand::createImm(operand);
936  MI->addOperand(Op);
937  operand = getRegFromSubinstEncoding(inst & 0xf);
938  Op = MCOperand::createReg(operand);
939  MI->addOperand(Op);
940  break;
941  case Hexagon::V4_SS1_storew_io:
942  // Rs 7-4, u 11-8{4_2}, Rt 3-0
943  operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
944  Op = MCOperand::createReg(operand);
945  MI->addOperand(Op);
946  operand = ((inst & 0xf00) >> 8) << 2;
947  Op = MCOperand::createImm(operand);
948  MI->addOperand(Op);
949  operand = getRegFromSubinstEncoding(inst & 0xf);
950  Op = MCOperand::createReg(operand);
951  MI->addOperand(Op);
952  break;
953  case Hexagon::V4_SS2_storebi0:
954  case Hexagon::V4_SS2_storebi1:
955  // Rs 7-4, u 3-0
956  operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
957  Op = MCOperand::createReg(operand);
958  MI->addOperand(Op);
959  operand = inst & 0xf;
960  Op = MCOperand::createImm(operand);
961  MI->addOperand(Op);
962  break;
963  case Hexagon::V4_SS2_storewi0:
964  case Hexagon::V4_SS2_storewi1:
965  // Rs 7-4, u 3-0{4_2}
966  operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
967  Op = MCOperand::createReg(operand);
968  MI->addOperand(Op);
969  operand = (inst & 0xf) << 2;
970  Op = MCOperand::createImm(operand);
971  MI->addOperand(Op);
972  break;
973  case Hexagon::V4_SS2_stored_sp:
974  // s 8-3{6_3}, Rtt 2-0
975  operand = SignExtend64<9>(((inst & 0x1f8) >> 3) << 3);
976  Op = MCOperand::createImm(operand);
977  MI->addOperand(Op);
978  operand = getDRegFromSubinstEncoding(inst & 0x7);
979  Op = MCOperand::createReg(operand);
980  MI->addOperand(Op);
981  case Hexagon::V4_SS2_storeh_io:
982  // Rs 7-4, u 10-8{3_1}, Rt 3-0
983  operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
984  Op = MCOperand::createReg(operand);
985  MI->addOperand(Op);
986  operand = ((inst & 0x700) >> 8) << 1;
987  Op = MCOperand::createImm(operand);
988  MI->addOperand(Op);
989  operand = getRegFromSubinstEncoding(inst & 0xf);
990  Op = MCOperand::createReg(operand);
991  MI->addOperand(Op);
992  break;
993  case Hexagon::V4_SS2_storew_sp:
994  // u 8-4{5_2}, Rd 3-0
995  operand = ((inst & 0x1f0) >> 4) << 2;
996  Op = MCOperand::createImm(operand);
997  MI->addOperand(Op);
998  operand = getRegFromSubinstEncoding(inst & 0xf);
999  Op = MCOperand::createReg(operand);
1000  MI->addOperand(Op);
1001  break;
1002  default:
1003  // don't crash with an invalid subinstruction
1004  // llvm_unreachable("Invalid subinstruction in duplex instruction");
1005  break;
1006  }
1007 }
static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
#define R4(n)
subInstBinaryValues
value_type read(const void *memory)
Read a value of a particular endianness from memory.
Definition: Endian.h:49
DecodeStatus
Ternary decode status.
Superclass for all disassemblers.
static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t, const void *Decoder)
static DecodeStatus s11_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
#define R2(n)
#define op(i)
static DecodeStatus s11_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:111
#define Fail
llvm::MCDisassembler::DecodeStatus DecodeStatus
static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo, const uint16_t Table[], size_t Size)
static DecodeStatus s11_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
static DecodeStatus s12ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
Context object for machine code objects.
Definition: MCContext.h:48
static const uint16_t IntRegDecoderTable[]
static DecodeStatus s10ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
int decodeInstruction(InternalInstruction *insn, byteReader_t reader, const void *readerArg, dlog_t logger, void *loggerArg, const void *miiArg, uint64_t startLoc, DisassemblerMode mode)
Decode one instruction and store the decoding results in a buffer provided by the consumer...
ArrayRef< T > slice(unsigned N) const
slice(n) - Chop off the first N elements of the array.
Definition: ArrayRef.h:165
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:134
static unsigned getRegFromSubinstEncoding(unsigned encoded_reg)
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:150
static unsigned getDRegFromSubinstEncoding(unsigned encoded_dreg)
static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t, void const *Decoder)
static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
static const uint16_t PredRegDecoderTable[]
static void AddSubinstOperands(MCInst *MI, unsigned opcode, unsigned inst)
static DecodeStatus s11_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
static unsigned GetSubinstOpcode(unsigned IClass, unsigned inst, unsigned &op, raw_ostream &os)
static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
void LLVMInitializeHexagonDisassembler()
void setOpcode(unsigned Op)
Definition: MCInst.h:158
#define R6(n)
Promote Memory to Register
Definition: Mem2Reg.cpp:58
BUNDLE - This instruction represents an instruction bundle.
Definition: TargetOpcodes.h:91
static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
Target - Wrapper for Target specific information.
static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
static MCOperand createInst(const MCInst *Val)
Definition: MCInst.h:135
static MCDisassembler * createHexagonDisassembler(Target const &T, MCSubtargetInfo const &STI, MCContext &Ctx)
static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus s16ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
MCSubtargetInfo - Generic base class for all target subtargets.
size_t bundleSize(MCInst const &MCI)
#define HEXAGON_INSTR_SIZE
Definition: Hexagon.h:30
static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, void const *Decoder)
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:38
void addOperand(const MCOperand &Op)
Definition: MCInst.h:168
Target TheHexagonTarget
static DecodeStatus s8ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:33
const T * data() const
Definition: ArrayRef.h:131
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:117
static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t, void const *Decoder)