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LLVM
3.7.0
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#include <AArch64ISelLowering.h>
Public Member Functions | |
| AArch64TargetLowering (const TargetMachine &TM, const AArch64Subtarget &STI) | |
| CCAssignFn * | CCAssignFnForCall (CallingConv::ID CC, bool IsVarArg) const |
| Selects the correct CCAssignFn for a given CallingConvention value. More... | |
| void | computeKnownBitsForTargetNode (const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth=0) const override |
| computeKnownBitsForTargetNode - Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets. More... | |
| MVT | getScalarShiftAmountTy (const DataLayout &DL, EVT) const override |
| EVT is not used in-tree, but is used by out-of-tree target. More... | |
| bool | allowsMisalignedMemoryAccesses (EVT VT, unsigned AddrSpace=0, unsigned Align=1, bool *Fast=nullptr) const override |
| allowsMisalignedMemoryAccesses - Returns true if the target allows unaligned memory accesses of the specified type. More... | |
| SDValue | LowerOperation (SDValue Op, SelectionDAG &DAG) const override |
| LowerOperation - Provide custom lowering hooks for some operations. More... | |
| const char * | getTargetNodeName (unsigned Opcode) const override |
| This method returns the name of a target specific DAG node. More... | |
| SDValue | PerformDAGCombine (SDNode *N, DAGCombinerInfo &DCI) const override |
| This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for. More... | |
| unsigned | getFunctionAlignment (const Function *F) const |
| getFunctionAlignment - Return the Log2 alignment of this function. More... | |
| bool | isNoopAddrSpaceCast (unsigned SrcAS, unsigned DestAS) const override |
| Returns true if a cast between SrcAS and DestAS is a noop. More... | |
| FastISel * | createFastISel (FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override |
| createFastISel - This method returns a target specific FastISel object, or null if the target does not support "fast" ISel. More... | |
| bool | isOffsetFoldingLegal (const GlobalAddressSDNode *GA) const override |
| Return true if folding a constant offset with the given GlobalAddress is legal. More... | |
| bool | isFPImmLegal (const APFloat &Imm, EVT VT) const override |
| Returns true if the target can instruction select the specified FP immediate natively. More... | |
| bool | isShuffleMaskLegal (const SmallVectorImpl< int > &M, EVT VT) const override |
| isShuffleMaskLegal - Return true if the given shuffle mask can be codegen'd directly, or if it should be stack expanded. More... | |
| EVT | getSetCCResultType (const DataLayout &DL, LLVMContext &Context, EVT VT) const override |
| getSetCCResultType - Return the ISD::SETCC ValueType More... | |
| SDValue | ReconstructShuffle (SDValue Op, SelectionDAG &DAG) const |
| MachineBasicBlock * | EmitF128CSEL (MachineInstr *MI, MachineBasicBlock *BB) const |
| MachineBasicBlock * | EmitInstrWithCustomInserter (MachineInstr *MI, MachineBasicBlock *MBB) const override |
| This method should be implemented by targets that mark instructions with the 'usesCustomInserter' flag. More... | |
| bool | getTgtMemIntrinsic (IntrinsicInfo &Info, const CallInst &I, unsigned Intrinsic) const override |
| getTgtMemIntrinsic - Represent NEON load and store intrinsics as MemIntrinsicNodes. More... | |
| bool | isTruncateFree (Type *Ty1, Type *Ty2) const override |
| Return true if it's free to truncate a value of type Ty1 to type Ty2. More... | |
| bool | isTruncateFree (EVT VT1, EVT VT2) const override |
| bool | isProfitableToHoist (Instruction *I) const override |
| Check if it is profitable to hoist instruction in then/else to if. More... | |
| bool | isZExtFree (Type *Ty1, Type *Ty2) const override |
| Return true if any actual instruction that defines a value of type Ty1 implicitly zero-extends the value to Ty2 in the result register. More... | |
| bool | isZExtFree (EVT VT1, EVT VT2) const override |
| bool | isZExtFree (SDValue Val, EVT VT2) const override |
| Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicitly zero-extended such as ARM ldrb / ldrh or because it's folded such as X86 zero-extending loads). More... | |
| bool | hasPairedLoad (Type *LoadedType, unsigned &RequiredAligment) const override |
| Return true if the target supplies and combines to a paired load two loaded values of type LoadedType next to each other in memory. More... | |
| bool | hasPairedLoad (EVT LoadedType, unsigned &RequiredAligment) const override |
| unsigned | getMaxSupportedInterleaveFactor () const override |
| Get the maximum supported factor for interleaved memory accesses. More... | |
| bool | lowerInterleavedLoad (LoadInst *LI, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const override |
| Lower an interleaved load into a ldN intrinsic. More... | |
| bool | lowerInterleavedStore (StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const override |
| Lower an interleaved store into a stN intrinsic. More... | |
| bool | isLegalAddImmediate (int64_t) const override |
| Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register with the immediate without having to materialize the immediate into a register. More... | |
| bool | isLegalICmpImmediate (int64_t) const override |
| Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register. More... | |
| EVT | getOptimalMemOpType (uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, MachineFunction &MF) const override |
| Returns the target specific optimal type for load and store operations as a result of memset, memcpy, and memmove lowering. More... | |
| bool | isLegalAddressingMode (const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override |
| isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type. More... | |
| int | getScalingFactorCost (const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override |
| Return the cost of the scaling factor used in the addressing mode represented by AM for this target, for a load/store of the specified type. More... | |
| bool | isFMAFasterThanFMulAndFAdd (EVT VT) const override |
| isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster than a pair of fmul and fadd instructions. More... | |
| const MCPhysReg * | getScratchRegisters (CallingConv::ID CC) const override |
| Returns a 0 terminated array of registers that can be safely used as scratch registers. More... | |
| bool | isDesirableToCommuteWithShift (const SDNode *N) const override |
| Returns false if N is a bit extraction pattern of (X >> C) & Mask. More... | |
| bool | shouldConvertConstantLoadToIntImm (const APInt &Imm, Type *Ty) const override |
| Returns true if it is beneficial to convert a load of a constant to just the constant itself. More... | |
| bool | hasLoadLinkedStoreConditional () const override |
| True if AtomicExpandPass should use emitLoadLinked/emitStoreConditional and expand AtomicCmpXchgInst. More... | |
| Value * | emitLoadLinked (IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const override |
| Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type. More... | |
| Value * | emitStoreConditional (IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const override |
| Perform a store-conditional operation to Addr. More... | |
| bool | shouldExpandAtomicLoadInIR (LoadInst *LI) const override |
| Returns true if the given (atomic) load should be expanded by the IR-level AtomicExpand pass into a load-linked instruction (through emitLoadLinked()). More... | |
| bool | shouldExpandAtomicStoreInIR (StoreInst *SI) const override |
| Returns true if the given (atomic) store should be expanded by the IR-level AtomicExpand pass into an "atomic xchg" which ignores its input. More... | |
| TargetLoweringBase::AtomicRMWExpansionKind | shouldExpandAtomicRMWInIR (AtomicRMWInst *AI) const override |
| Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all. More... | |
| bool | useLoadStackGuardNode () const override |
| If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector. More... | |
| TargetLoweringBase::LegalizeTypeAction | getPreferredVectorAction (EVT VT) const override |
| Return the preferred vector type legalization action. More... | |
Public Member Functions inherited from llvm::TargetLowering | |
| TargetLowering (const TargetMachine &TM) | |
| NOTE: The TargetMachine owns TLOF. More... | |
| virtual unsigned | getJumpTableEncoding () const |
| Return the entry encoding for a jump table in the current function. More... | |
| virtual const MCExpr * | LowerCustomJumpTableEntry (const MachineJumpTableInfo *, const MachineBasicBlock *, unsigned, MCContext &) const |
| virtual SDValue | getPICJumpTableRelocBase (SDValue Table, SelectionDAG &DAG) const |
| Returns relocation base for the given PIC jumptable. More... | |
| virtual const MCExpr * | getPICJumpTableRelocBaseExpr (const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const |
| This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase, but as an MCExpr. More... | |
| bool | isInTailCallPosition (SelectionDAG &DAG, SDNode *Node, SDValue &Chain) const |
| Check whether a given call node is in tail position within its function. More... | |
| void | softenSetCCOperands (SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, SDLoc DL) const |
| SoftenSetCCOperands - Soften the operands of a comparison. More... | |
| std::pair< SDValue, SDValue > | makeLibCall (SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops, unsigned NumOps, bool isSigned, SDLoc dl, bool doesNotReturn=false, bool isReturnValueUsed=true) const |
| Returns a pair of (return value, chain). More... | |
| bool | SimplifyDemandedBits (SDValue Op, const APInt &DemandedMask, APInt &KnownZero, APInt &KnownOne, TargetLoweringOpt &TLO, unsigned Depth=0) const |
| Look at Op. More... | |
| virtual unsigned | ComputeNumSignBitsForTargetNode (SDValue Op, const SelectionDAG &DAG, unsigned Depth=0) const |
| This method can be implemented by targets that want to expose additional information about sign bits to the DAG Combiner. More... | |
| bool | isConstTrueVal (const SDNode *N) const |
| Return if the N is a constant or constant vector equal to the true value from getBooleanContents(). More... | |
| bool | isConstFalseVal (const SDNode *N) const |
| Return if the N is a constant or constant vector equal to the false value from getBooleanContents(). More... | |
| SDValue | SimplifySetCC (EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, SDLoc dl) const |
| Try to simplify a setcc built with the specified operands and cc. More... | |
| virtual bool | isGAPlusOffset (SDNode *N, const GlobalValue *&GA, int64_t &Offset) const |
| Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + offset. More... | |
| virtual bool | isTypeDesirableForOp (unsigned, EVT VT) const |
| Return true if the target has native support for the specified value type and it is 'desirable' to use the type for the given node type. More... | |
| virtual bool | isDesirableToTransformToIntegerOp (unsigned, EVT) const |
| Return true if it is profitable for dag combiner to transform a floating point op of specified opcode to a equivalent op of an integer type. More... | |
| virtual bool | IsDesirableToPromoteOp (SDValue, EVT &) const |
| This method query the target whether it is beneficial for dag combiner to promote the specified node. More... | |
| std::pair< SDValue, SDValue > | LowerCallTo (CallLoweringInfo &CLI) const |
| This function lowers an abstract call to a function into an actual call. More... | |
| virtual void | HandleByVal (CCState *, unsigned &, unsigned) const |
| Target-specific cleanup for formal ByVal parameters. More... | |
| virtual const char * | getClearCacheBuiltinName () const |
| Return the builtin name for the __builtin___clear_cache intrinsic Default is to invoke the clear cache library call. More... | |
| virtual EVT | getTypeForExtArgOrReturn (LLVMContext &Context, EVT VT, ISD::NodeType) const |
| Return the type that should be used to zero or sign extend a zeroext/signext integer argument or return value. More... | |
| virtual SDValue | prepareVolatileOrAtomicLoad (SDValue Chain, SDLoc DL, SelectionDAG &DAG) const |
| This callback is used to prepare for a volatile or atomic load. More... | |
| virtual void | LowerOperationWrapper (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const |
| This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but legal result types. More... | |
| bool | verifyReturnAddressArgumentIsConstant (SDValue Op, SelectionDAG &DAG) const |
| virtual bool | ExpandInlineAsm (CallInst *) const |
| This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to. More... | |
| virtual AsmOperandInfoVector | ParseConstraints (const DataLayout &DL, const TargetRegisterInfo *TRI, ImmutableCallSite CS) const |
| Split up the constraint string from the inline assembly value into the specific constraints and their prefixes, and also tie in the associated operand values. More... | |
| virtual ConstraintWeight | getMultipleConstraintMatchWeight (AsmOperandInfo &info, int maIndex) const |
| Examine constraint type and operand type and determine a weight value. More... | |
| virtual void | ComputeConstraintToUse (AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=nullptr) const |
| Determines the constraint code and constraint type to use for the specific AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType. More... | |
| virtual const char * | LowerXConstraint (EVT ConstraintVT) const |
| Try to replace an X constraint, which matches anything, with another that has more specific requirements based on the type of the corresponding operand. More... | |
| SDValue | BuildSDIV (SDNode *N, const APInt &Divisor, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode * > *Created) const |
| Given an ISD::SDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. More... | |
| SDValue | BuildUDIV (SDNode *N, const APInt &Divisor, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode * > *Created) const |
| Given an ISD::UDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. More... | |
| virtual SDValue | getRsqrtEstimate (SDValue Operand, DAGCombinerInfo &DCI, unsigned &RefinementSteps, bool &UseOneConstNR) const |
| Hooks for building estimates in place of slower divisions and square roots. More... | |
| virtual SDValue | getRecipEstimate (SDValue Operand, DAGCombinerInfo &DCI, unsigned &RefinementSteps) const |
| Return a reciprocal estimate value for the input operand. More... | |
| bool | expandMUL (SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT, SelectionDAG &DAG, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) const |
| Expand a MUL into two nodes. More... | |
| bool | expandFP_TO_SINT (SDNode *N, SDValue &Result, SelectionDAG &DAG) const |
| Expand float(f32) to SINT(i64) conversion. More... | |
| virtual void | AdjustInstrPostInstrSelection (MachineInstr *MI, SDNode *Node) const |
| This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag. More... | |
Public Member Functions inherited from llvm::TargetLoweringBase | |
| TargetLoweringBase (const TargetMachine &TM) | |
| NOTE: The TargetMachine owns TLOF. More... | |
| virtual | ~TargetLoweringBase () |
| const TargetMachine & | getTargetMachine () const |
| virtual bool | useSoftFloat () const |
| MVT | getPointerTy (const DataLayout &DL, uint32_t AS=0) const |
| Return the pointer type for the given address space, defaults to the pointer type from the data layout. More... | |
| EVT | getShiftAmountTy (EVT LHSTy, const DataLayout &DL) const |
| virtual MVT | getVectorIdxTy (const DataLayout &DL) const |
| Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR. More... | |
| bool | isSelectExpensive () const |
| Return true if the select operation is expensive for this target. More... | |
| virtual bool | isSelectSupported (SelectSupportKind) const |
| bool | hasMultipleConditionRegisters () const |
| Return true if multiple condition registers are available. More... | |
| bool | hasExtractBitsInsn () const |
| Return true if the target has BitExtract instructions. More... | |
| virtual bool | shouldExpandBuildVectorWithShuffles (EVT, unsigned DefinedValues) const |
| bool | isIntDivCheap () const |
| Return true if integer divide is usually cheaper than a sequence of several shifts, adds, and multiplies for this target. More... | |
| bool | isFsqrtCheap () const |
| Return true if sqrt(x) is as cheap or cheaper than 1 / rsqrt(x) More... | |
| bool | isSlowDivBypassed () const |
| Returns true if target has indicated at least one type should be bypassed. More... | |
| const DenseMap< unsigned int, unsigned int > & | getBypassSlowDivWidths () const |
| Returns map of slow types for division or remainder with corresponding fast types. More... | |
| bool | isPow2SDivCheap () const |
| Return true if pow2 sdiv is cheaper than a chain of sra/srl/add/sra. More... | |
| bool | isJumpExpensive () const |
| Return true if Flow Control is an expensive operation that should be avoided. More... | |
| bool | isPredictableSelectExpensive () const |
| Return true if selects are only cheaper than branches if the branch is unlikely to be predicted right. More... | |
| virtual bool | isLoadBitCastBeneficial (EVT, EVT) const |
| isLoadBitCastBeneficial() - Return true if the following transform is beneficial. More... | |
| virtual bool | storeOfVectorConstantIsCheap (EVT MemVT, unsigned NumElem, unsigned AddrSpace) const |
| Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the given size and type for the address space than to store the individual scalar element constants. More... | |
| virtual bool | isCheapToSpeculateCttz () const |
| Return true if it is cheap to speculate a call to intrinsic cttz. More... | |
| virtual bool | isCheapToSpeculateCtlz () const |
| Return true if it is cheap to speculate a call to intrinsic ctlz. More... | |
| bool | isMaskAndBranchFoldingLegal () const |
| Return if the target supports combining a chain like: More... | |
| bool | enableExtLdPromotion () const |
| Return true if the target wants to use the optimization that turns ext(promotableInst1(...(promotableInstN(load)))) into promotedInst1(...(promotedInstN(ext(load)))). More... | |
| virtual bool | canCombineStoreAndExtract (Type *VectorTy, Value *Idx, unsigned &Cost) const |
| Return true if the target can combine store(extractelement VectorTy, Idx). More... | |
| bool | hasFloatingPointExceptions () const |
| Return true if target supports floating point exceptions. More... | |
| virtual bool | enableAggressiveFMAFusion (EVT VT) const |
| Return true if target always beneficiates from combining into FMA for a given value type. More... | |
| virtual MVT::SimpleValueType | getCmpLibcallReturnType () const |
| Return the ValueType for comparison libcalls. More... | |
| BooleanContent | getBooleanContents (bool isVec, bool isFloat) const |
| For targets without i1 registers, this gives the nature of the high-bits of boolean values held in types wider than i1. More... | |
| BooleanContent | getBooleanContents (EVT Type) const |
| Sched::Preference | getSchedulingPreference () const |
| Return target scheduling preference. More... | |
| virtual Sched::Preference | getSchedulingPreference (SDNode *) const |
| Some scheduler, e.g. More... | |
| virtual const TargetRegisterClass * | getRegClassFor (MVT VT) const |
| Return the register class that should be used for the specified value type. More... | |
| virtual const TargetRegisterClass * | getRepRegClassFor (MVT VT) const |
| Return the 'representative' register class for the specified value type. More... | |
| virtual uint8_t | getRepRegClassCostFor (MVT VT) const |
| Return the cost of the 'representative' register class for the specified value type. More... | |
| bool | isTypeLegal (EVT VT) const |
| Return true if the target has native support for the specified value type. More... | |
| const ValueTypeActionImpl & | getValueTypeActions () const |
| LegalizeTypeAction | getTypeAction (LLVMContext &Context, EVT VT) const |
| Return how we should legalize values of this type, either it is already legal (return 'Legal') or we need to promote it to a larger type (return 'Promote'), or we need to expand it into multiple registers of smaller integer type (return 'Expand'). More... | |
| LegalizeTypeAction | getTypeAction (MVT VT) const |
| EVT | getTypeToTransformTo (LLVMContext &Context, EVT VT) const |
| For types supported by the target, this is an identity function. More... | |
| EVT | getTypeToExpandTo (LLVMContext &Context, EVT VT) const |
| For types supported by the target, this is an identity function. More... | |
| unsigned | getVectorTypeBreakdown (LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const |
| Vector types are broken down into some number of legal first class types. More... | |
| virtual bool | canOpTrap (unsigned Op, EVT VT) const |
| Returns true if the operation can trap for the value type. More... | |
| virtual bool | isVectorClearMaskLegal (const SmallVectorImpl< int > &, EVT) const |
| Similar to isShuffleMaskLegal. More... | |
| LegalizeAction | getOperationAction (unsigned Op, EVT VT) const |
| Return how this operation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More... | |
| bool | isOperationLegalOrCustom (unsigned Op, EVT VT) const |
| Return true if the specified operation is legal on this target or can be made legal with custom lowering. More... | |
| bool | isOperationLegalOrPromote (unsigned Op, EVT VT) const |
| Return true if the specified operation is legal on this target or can be made legal using promotion. More... | |
| bool | isOperationExpand (unsigned Op, EVT VT) const |
| Return true if the specified operation is illegal on this target or unlikely to be made legal with custom lowering. More... | |
| bool | isOperationLegal (unsigned Op, EVT VT) const |
| Return true if the specified operation is legal on this target. More... | |
| LegalizeAction | getLoadExtAction (unsigned ExtType, EVT ValVT, EVT MemVT) const |
| Return how this load with extension should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More... | |
| bool | isLoadExtLegal (unsigned ExtType, EVT ValVT, EVT MemVT) const |
| Return true if the specified load with extension is legal on this target. More... | |
| bool | isLoadExtLegalOrCustom (unsigned ExtType, EVT ValVT, EVT MemVT) const |
| Return true if the specified load with extension is legal or custom on this target. More... | |
| LegalizeAction | getTruncStoreAction (EVT ValVT, EVT MemVT) const |
| Return how this store with truncation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More... | |
| bool | isTruncStoreLegal (EVT ValVT, EVT MemVT) const |
| Return true if the specified store with truncation is legal on this target. More... | |
| LegalizeAction | getIndexedLoadAction (unsigned IdxMode, MVT VT) const |
| Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More... | |
| bool | isIndexedLoadLegal (unsigned IdxMode, EVT VT) const |
| Return true if the specified indexed load is legal on this target. More... | |
| LegalizeAction | getIndexedStoreAction (unsigned IdxMode, MVT VT) const |
| Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More... | |
| bool | isIndexedStoreLegal (unsigned IdxMode, EVT VT) const |
| Return true if the specified indexed load is legal on this target. More... | |
| LegalizeAction | getCondCodeAction (ISD::CondCode CC, MVT VT) const |
| Return how the condition code should be treated: either it is legal, needs to be expanded to some other code sequence, or the target has a custom expander for it. More... | |
| bool | isCondCodeLegal (ISD::CondCode CC, MVT VT) const |
| Return true if the specified condition code is legal on this target. More... | |
| MVT | getTypeToPromoteTo (unsigned Op, MVT VT) const |
| If the action for this operation is to promote, this method returns the ValueType to promote to. More... | |
| EVT | getValueType (const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const |
| Return the EVT corresponding to this LLVM type. More... | |
| MVT | getSimpleValueType (const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const |
| Return the MVT corresponding to this LLVM type. See getValueType. More... | |
| virtual unsigned | getByValTypeAlignment (Type *Ty, const DataLayout &DL) const |
| Return the desired alignment for ByVal or InAlloca aggregate function arguments in the caller parameter area. More... | |
| MVT | getRegisterType (MVT VT) const |
| Return the type of registers that this ValueType will eventually require. More... | |
| MVT | getRegisterType (LLVMContext &Context, EVT VT) const |
| Return the type of registers that this ValueType will eventually require. More... | |
| unsigned | getNumRegisters (LLVMContext &Context, EVT VT) const |
| Return the number of registers that this ValueType will eventually require. More... | |
| virtual bool | ShouldShrinkFPConstant (EVT) const |
| If true, then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime. More... | |
| virtual bool | shouldReduceLoadWidth (SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const |
| bool | hasBigEndianPartOrdering (EVT VT, const DataLayout &DL) const |
| When splitting a value of the specified type into parts, does the Lo or Hi part come first? This usually follows the endianness, except for ppcf128, where the Hi part always comes first. More... | |
| bool | hasTargetDAGCombine (ISD::NodeType NT) const |
| If true, the target has custom DAG combine transformations that it can perform for the specified node. More... | |
| unsigned | getMaxStoresPerMemset (bool OptSize) const |
| Get maximum # of store operations permitted for llvm.memset. More... | |
| unsigned | getMaxStoresPerMemcpy (bool OptSize) const |
| Get maximum # of store operations permitted for llvm.memcpy. More... | |
| unsigned | getMaxStoresPerMemmove (bool OptSize) const |
| Get maximum # of store operations permitted for llvm.memmove. More... | |
| virtual bool | isSafeMemOpType (MVT) const |
| Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline. More... | |
| bool | usesUnderscoreSetJmp () const |
| Determine if we should use _setjmp or setjmp to implement llvm.setjmp. More... | |
| bool | usesUnderscoreLongJmp () const |
| Determine if we should use _longjmp or longjmp to implement llvm.longjmp. More... | |
| int | getMinimumJumpTableEntries () const |
| Return integer threshold on number of blocks to use jump tables rather than if sequence. More... | |
| unsigned | getStackPointerRegisterToSaveRestore () const |
| If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore. More... | |
| unsigned | getExceptionPointerRegister () const |
| If a physical register, this returns the register that receives the exception address on entry to a landing pad. More... | |
| unsigned | getExceptionSelectorRegister () const |
| If a physical register, this returns the register that receives the exception typeid on entry to a landing pad. More... | |
| unsigned | getJumpBufSize () const |
| Returns the target's jmp_buf size in bytes (if never set, the default is 200) More... | |
| unsigned | getJumpBufAlignment () const |
| Returns the target's jmp_buf alignment in bytes (if never set, the default is 0) More... | |
| unsigned | getMinStackArgumentAlignment () const |
| Return the minimum stack alignment of an argument. More... | |
| unsigned | getMinFunctionAlignment () const |
| Return the minimum function alignment. More... | |
| unsigned | getPrefFunctionAlignment () const |
| Return the preferred function alignment. More... | |
| virtual unsigned | getPrefLoopAlignment (MachineLoop *ML=nullptr) const |
| Return the preferred loop alignment. More... | |
| bool | getInsertFencesForAtomic () const |
| Return whether the DAG builder should automatically insert fences and reduce ordering for atomics. More... | |
| virtual bool | getStackCookieLocation (unsigned &, unsigned &) const |
| Return true if the target stores stack protector cookies at a fixed offset in some non-standard address space, and populates the address space and offset as appropriate. More... | |
| virtual bool | shouldAlignPointerArgs (CallInst *, unsigned &, unsigned &) const |
| Return true if the pointer arguments to CI should be aligned by aligning the object whose address is being passed. More... | |
| virtual bool | shouldSignExtendTypeInLibCall (EVT Type, bool IsSigned) const |
| Returns true if arguments should be sign-extended in lib calls. More... | |
| virtual LoadInst * | lowerIdempotentRMWIntoFencedLoad (AtomicRMWInst *RMWI) const |
| On some platforms, an AtomicRMW that never actually modifies the value (such as fetch_add of 0) can be turned into a fence followed by an atomic load. More... | |
| virtual bool | shouldNormalizeToSelectSequence (LLVMContext &Context, EVT VT) const |
| Returns true if we should normalize select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely that it saves us from materializing N0 and N1 in an integer register. More... | |
| virtual bool | GetAddrModeArguments (IntrinsicInst *, SmallVectorImpl< Value * > &, Type *&, unsigned AddrSpace=0) const |
| CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the address. More... | |
| virtual bool | isVectorShiftByScalarCheap (Type *Ty) const |
| Return true if it's significantly cheaper to shift a vector by a uniform scalar than by an amount which will vary across each lane. More... | |
| virtual bool | allowTruncateForTailCall (Type *, Type *) const |
| Return true if a truncation from Ty1 to Ty2 is permitted when deciding whether a call is in tail position. More... | |
| bool | isExtFree (const Instruction *I) const |
Return true if the extension represented by I is free. More... | |
| virtual bool | isFPExtFree (EVT VT) const |
| Return true if an fpext operation is free (for instance, because single-precision floating-point numbers are implicitly extended to double-precision). More... | |
| virtual bool | isVectorLoadExtDesirable (SDValue ExtVal) const |
| Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable. More... | |
| virtual bool | isFNegFree (EVT VT) const |
| Return true if an fneg operation is free to the point where it is never worthwhile to replace it with a bitwise operation. More... | |
| virtual bool | isFAbsFree (EVT VT) const |
| Return true if an fabs operation is free to the point where it is never worthwhile to replace it with a bitwise operation. More... | |
| virtual bool | isNarrowingProfitable (EVT, EVT) const |
| Return true if it's profitable to narrow operations of type VT1 to VT2. More... | |
| virtual bool | isExtractSubvectorCheap (EVT ResVT, unsigned Index) const |
| Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index. More... | |
| void | setLibcallName (RTLIB::Libcall Call, const char *Name) |
| Rename the default libcall routine name for the specified libcall. More... | |
| const char * | getLibcallName (RTLIB::Libcall Call) const |
| Get the libcall routine name for the specified libcall. More... | |
| void | setCmpLibcallCC (RTLIB::Libcall Call, ISD::CondCode CC) |
| Override the default CondCode to be used to test the result of the comparison libcall against zero. More... | |
| ISD::CondCode | getCmpLibcallCC (RTLIB::Libcall Call) const |
| Get the CondCode that's to be used to test the result of the comparison libcall against zero. More... | |
| void | setLibcallCallingConv (RTLIB::Libcall Call, CallingConv::ID CC) |
| Set the CallingConv that should be used for the specified libcall. More... | |
| CallingConv::ID | getLibcallCallingConv (RTLIB::Libcall Call) const |
| Get the CallingConv that should be used for the specified libcall. More... | |
| int | InstructionOpcodeToISD (unsigned Opcode) const |
| Get the ISD node that corresponds to the Instruction class opcode. More... | |
| std::pair< unsigned, MVT > | getTypeLegalizationCost (const DataLayout &DL, Type *Ty) const |
| Estimate the cost of type-legalization and the legalized type. More... | |
| virtual Instruction * | emitLeadingFence (IRBuilder<> &Builder, AtomicOrdering Ord, bool IsStore, bool IsLoad) const |
| Inserts in the IR a target-specific intrinsic specifying a fence. More... | |
| virtual Instruction * | emitTrailingFence (IRBuilder<> &Builder, AtomicOrdering Ord, bool IsStore, bool IsLoad) const |
Additional Inherited Members | |
Public Types inherited from llvm::TargetLowering | |
| enum | ConstraintType { C_Register, C_RegisterClass, C_Memory, C_Other, C_Unknown } |
| enum | ConstraintWeight { CW_Invalid = -1, CW_Okay = 0, CW_Good = 1, CW_Better = 2, CW_Best = 3, CW_SpecificReg = CW_Okay, CW_Register = CW_Good, CW_Memory = CW_Better, CW_Constant = CW_Best, CW_Default = CW_Okay } |
| typedef std::vector< ArgListEntry > | ArgListTy |
| typedef std::vector < AsmOperandInfo > | AsmOperandInfoVector |
Public Types inherited from llvm::TargetLoweringBase | |
| enum | LegalizeAction { Legal, Promote, Expand, Custom } |
| This enum indicates whether operations are valid for a target, and if not, what action should be used to make them valid. More... | |
| enum | LegalizeTypeAction { TypeLegal, TypePromoteInteger, TypeExpandInteger, TypeSoftenFloat, TypeExpandFloat, TypeScalarizeVector, TypeSplitVector, TypeWidenVector, TypePromoteFloat } |
| This enum indicates whether a types are legal for a target, and if not, what action should be used to make them valid. More... | |
| enum | BooleanContent { UndefinedBooleanContent, ZeroOrOneBooleanContent, ZeroOrNegativeOneBooleanContent } |
| Enum that describes how the target represents true/false values. More... | |
| enum | SelectSupportKind { ScalarValSelect, ScalarCondVectorVal, VectorMaskSelect } |
| Enum that describes what type of support for selects the target has. More... | |
| enum | AtomicRMWExpansionKind { AtomicRMWExpansionKind::None, AtomicRMWExpansionKind::LLSC, AtomicRMWExpansionKind::CmpXChg } |
| Enum that specifies what a AtomicRMWInst is expanded to, if at all. More... | |
| typedef std::pair < LegalizeTypeAction, EVT > | LegalizeKind |
| LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it. More... | |
Static Public Member Functions inherited from llvm::TargetLoweringBase | |
| static ISD::NodeType | getExtendForContent (BooleanContent Content) |
Protected Member Functions inherited from llvm::TargetLoweringBase | |
| void | initActions () |
| Initialize all of the actions to default values. More... | |
| void | setBooleanContents (BooleanContent Ty) |
| Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type. More... | |
| void | setBooleanContents (BooleanContent IntTy, BooleanContent FloatTy) |
| Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type. More... | |
| void | setBooleanVectorContents (BooleanContent Ty) |
| Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider type. More... | |
| void | setSchedulingPreference (Sched::Preference Pref) |
| Specify the target scheduling preference. More... | |
| void | setUseUnderscoreSetJmp (bool Val) |
| Indicate whether this target prefers to use _setjmp to implement llvm.setjmp or the version without _. More... | |
| void | setUseUnderscoreLongJmp (bool Val) |
| Indicate whether this target prefers to use _longjmp to implement llvm.longjmp or the version without _. More... | |
| void | setMinimumJumpTableEntries (int Val) |
| Indicate the number of blocks to generate jump tables rather than if sequence. More... | |
| void | setStackPointerRegisterToSaveRestore (unsigned R) |
| If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore. More... | |
| void | setExceptionPointerRegister (unsigned R) |
| If set to a physical register, this sets the register that receives the exception address on entry to a landing pad. More... | |
| void | setExceptionSelectorRegister (unsigned R) |
| If set to a physical register, this sets the register that receives the exception typeid on entry to a landing pad. More... | |
| void | setSelectIsExpensive (bool isExpensive=true) |
| Tells the code generator not to expand operations into sequences that use the select operations if possible. More... | |
| void | setHasMultipleConditionRegisters (bool hasManyRegs=true) |
| Tells the code generator that the target has multiple (allocatable) condition registers that can be used to store the results of comparisons for use by selects and conditional branches. More... | |
| void | setHasExtractBitsInsn (bool hasExtractInsn=true) |
| Tells the code generator that the target has BitExtract instructions. More... | |
| void | setJumpIsExpensive (bool isExpensive=true) |
| Tells the code generator not to expand logic operations on comparison predicates into separate sequences that increase the amount of flow control. More... | |
| void | setIntDivIsCheap (bool isCheap=true) |
| Tells the code generator that integer divide is expensive, and if possible, should be replaced by an alternate sequence of instructions not containing an integer divide. More... | |
| void | setFsqrtIsCheap (bool isCheap=true) |
| Tells the code generator that fsqrt is cheap, and should not be replaced with an alternative sequence of instructions. More... | |
| void | setHasFloatingPointExceptions (bool FPExceptions=true) |
| Tells the code generator that this target supports floating point exceptions and cares about preserving floating point exception behavior. More... | |
| void | addBypassSlowDiv (unsigned int SlowBitWidth, unsigned int FastBitWidth) |
| Tells the code generator which bitwidths to bypass. More... | |
| void | setPow2SDivIsCheap (bool isCheap=true) |
| Tells the code generator that it shouldn't generate sra/srl/add/sra for a signed divide by power of two; let the target handle it. More... | |
| void | addRegisterClass (MVT VT, const TargetRegisterClass *RC) |
| Add the specified register class as an available regclass for the specified value type. More... | |
| void | clearRegisterClasses () |
| Remove all register classes. More... | |
| void | clearOperationActions () |
| Remove all operation actions. More... | |
| virtual std::pair< const TargetRegisterClass *, uint8_t > | findRepresentativeClass (const TargetRegisterInfo *TRI, MVT VT) const |
| Return the largest legal super-reg register class of the register class for the specified type and its associated "cost". More... | |
| void | computeRegisterProperties (const TargetRegisterInfo *TRI) |
| Once all of the register classes are added, this allows us to compute derived properties we expose. More... | |
| void | setOperationAction (unsigned Op, MVT VT, LegalizeAction Action) |
| Indicate that the specified operation does not work with the specified type and indicate what to do about it. More... | |
| void | setLoadExtAction (unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action) |
| Indicate that the specified load with extension does not work with the specified type and indicate what to do about it. More... | |
| void | setTruncStoreAction (MVT ValVT, MVT MemVT, LegalizeAction Action) |
| Indicate that the specified truncating store does not work with the specified type and indicate what to do about it. More... | |
| void | setIndexedLoadAction (unsigned IdxMode, MVT VT, LegalizeAction Action) |
| Indicate that the specified indexed load does or does not work with the specified type and indicate what to do abort it. More... | |
| void | setIndexedStoreAction (unsigned IdxMode, MVT VT, LegalizeAction Action) |
| Indicate that the specified indexed store does or does not work with the specified type and indicate what to do about it. More... | |
| void | setCondCodeAction (ISD::CondCode CC, MVT VT, LegalizeAction Action) |
| Indicate that the specified condition code is or isn't supported on the target and indicate what to do about it. More... | |
| void | AddPromotedToType (unsigned Opc, MVT OrigVT, MVT DestVT) |
| If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/fp until it can find one that works. More... | |
| void | setTargetDAGCombine (ISD::NodeType NT) |
| Targets should invoke this method for each target independent node that they want to provide a custom DAG combiner for by implementing the PerformDAGCombine virtual method. More... | |
| void | setJumpBufSize (unsigned Size) |
| Set the target's required jmp_buf buffer size (in bytes); default is 200. More... | |
| void | setJumpBufAlignment (unsigned Align) |
| Set the target's required jmp_buf buffer alignment (in bytes); default is 0. More... | |
| void | setMinFunctionAlignment (unsigned Align) |
| Set the target's minimum function alignment (in log2(bytes)) More... | |
| void | setPrefFunctionAlignment (unsigned Align) |
| Set the target's preferred function alignment. More... | |
| void | setPrefLoopAlignment (unsigned Align) |
| Set the target's preferred loop alignment. More... | |
| void | setMinStackArgumentAlignment (unsigned Align) |
| Set the minimum stack alignment of an argument (in log2(bytes)). More... | |
| void | setInsertFencesForAtomic (bool fence) |
| Set if the DAG builder should automatically insert fences and reduce the order of atomic memory operations to Monotonic. More... | |
| bool | isLegalRC (const TargetRegisterClass *RC) const |
| Return true if the value types that can be represented by the specified register class are all legal. More... | |
| MachineBasicBlock * | emitPatchPoint (MachineInstr *MI, MachineBasicBlock *MBB) const |
| Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that is recognized by PrologEpilogInserter. More... | |
Protected Attributes inherited from llvm::TargetLoweringBase | |
| unsigned | MaxStoresPerMemset |
| Specify maximum number of store instructions per memset call. More... | |
| unsigned | MaxStoresPerMemsetOptSize |
| Maximum number of stores operations that may be substituted for the call to memset, used for functions with OptSize attribute. More... | |
| unsigned | MaxStoresPerMemcpy |
| Specify maximum bytes of store instructions per memcpy call. More... | |
| unsigned | MaxStoresPerMemcpyOptSize |
| Maximum number of store operations that may be substituted for a call to memcpy, used for functions with OptSize attribute. More... | |
| unsigned | MaxStoresPerMemmove |
| Specify maximum bytes of store instructions per memmove call. More... | |
| unsigned | MaxStoresPerMemmoveOptSize |
| Maximum number of store instructions that may be substituted for a call to memmove, used for functions with OpSize attribute. More... | |
| bool | PredictableSelectIsExpensive |
| Tells the code generator that select is more expensive than a branch if the branch is usually predicted right. More... | |
| bool | MaskAndBranchFoldingIsLegal |
| MaskAndBranchFoldingIsLegal - Indicates if the target supports folding a mask of a single bit, a compare, and a branch into a single instruction. More... | |
| bool | EnableExtLdPromotion |
Definition at line 219 of file AArch64ISelLowering.h.
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explicit |
Definition at line 79 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::ADDC, llvm::ISD::ADDE, llvm::TargetLoweringBase::AddPromotedToType(), llvm::TargetLoweringBase::addRegisterClass(), Align(), llvm::ISD::ANY_EXTEND, llvm::ISD::BITCAST, llvm::ISD::BlockAddress, llvm::ISD::BR_CC, llvm::ISD::BR_JT, llvm::ISD::BRCOND, llvm::ISD::BSWAP, llvm::TargetLoweringBase::computeRegisterProperties(), llvm::ISD::CONCAT_VECTORS, llvm::ISD::ConstantFP, llvm::ISD::ConstantPool, llvm::ISD::CTLZ_ZERO_UNDEF, llvm::ISD::CTPOP, llvm::ISD::CTTZ_ZERO_UNDEF, llvm::TargetLoweringBase::Custom, llvm::ISD::DYNAMIC_STACKALLOC, llvm::TargetLoweringBase::EnableExtLdPromotion, llvm::TargetLoweringBase::Expand, llvm::ISD::EXTLOAD, llvm::MVT::f128, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::MVT::f80, llvm::ISD::FABS, llvm::ISD::FADD, llvm::ISD::FCEIL, llvm::ISD::FCOPYSIGN, llvm::ISD::FCOS, llvm::ISD::FDIV, llvm::ISD::FEXP, llvm::ISD::FEXP2, llvm::ISD::FFLOOR, llvm::ISD::FLOG, llvm::ISD::FLOG10, llvm::ISD::FLOG2, llvm::ISD::FMA, llvm::ISD::FMAXNUM, llvm::ISD::FMINNUM, llvm::ISD::FMUL, llvm::ISD::FNEARBYINT, llvm::ISD::FNEG, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::MVT::fp_valuetypes(), llvm::ISD::FPOW, llvm::ISD::FPOWI, llvm::ISD::FREM, llvm::ISD::FRINT, llvm::ISD::FROUND, llvm::ISD::FSIN, llvm::ISD::FSINCOS, llvm::ISD::FSQRT, llvm::ISD::FSUB, llvm::ISD::FTRUNC, llvm::TargetMachine::getCodeModel(), llvm::AArch64Subtarget::getRegisterInfo(), llvm::ISD::GlobalAddress, llvm::ISD::GlobalTLSAddress, llvm::AArch64Subtarget::hasFPARMv8(), llvm::AArch64Subtarget::hasNEON(), llvm::Sched::Hybrid, llvm::MVT::i1, llvm::MVT::i128, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, im, llvm::ISD::INSERT_VECTOR_ELT, llvm::MVT::integer_valuetypes(), llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::AArch64Subtarget::isCortexA57(), llvm::AArch64Subtarget::isTargetMachO(), llvm::ISD::JumpTable, llvm::CodeModel::Large, llvm::ISD::LAST_INDEXED_MODE, llvm::TargetLoweringBase::Legal, llvm::TargetLoweringBase::MaskAndBranchFoldingIsLegal, llvm::TargetLoweringBase::MaxStoresPerMemcpy, llvm::TargetLoweringBase::MaxStoresPerMemcpyOptSize, llvm::TargetLoweringBase::MaxStoresPerMemmove, llvm::TargetLoweringBase::MaxStoresPerMemmoveOptSize, llvm::TargetLoweringBase::MaxStoresPerMemset, llvm::TargetLoweringBase::MaxStoresPerMemsetOptSize, llvm::ISD::MUL, llvm::ISD::MULHS, llvm::ISD::MULHU, llvm::ISD::OR, llvm::MVT::Other, llvm::ISD::PRE_INC, llvm::TargetLoweringBase::PredictableSelectIsExpensive, llvm::ISD::PREFETCH, llvm::TargetLoweringBase::Promote, llvm::ISD::ROTL, llvm::ISD::SADDO, llvm::ISD::SDIVREM, llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::TargetLoweringBase::setBooleanContents(), llvm::TargetLoweringBase::setBooleanVectorContents(), llvm::ISD::SETCC, llvm::TargetLoweringBase::setExceptionPointerRegister(), llvm::TargetLoweringBase::setExceptionSelectorRegister(), llvm::TargetLoweringBase::setHasExtractBitsInsn(), llvm::TargetLoweringBase::setIndexedLoadAction(), llvm::TargetLoweringBase::setIndexedStoreAction(), llvm::TargetLoweringBase::setLoadExtAction(), llvm::TargetLoweringBase::setMinFunctionAlignment(), llvm::TargetLoweringBase::setOperationAction(), llvm::TargetLoweringBase::setSchedulingPreference(), llvm::TargetLoweringBase::setStackPointerRegisterToSaveRestore(), llvm::TargetLoweringBase::setTargetDAGCombine(), llvm::TargetLoweringBase::setTruncStoreAction(), llvm::ISD::SEXTLOAD, llvm::ISD::SHL_PARTS, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SINT_TO_FP, llvm::ISD::SMUL_LOHI, llvm::ISD::SMULO, llvm::ISD::SRA_PARTS, llvm::ISD::SREM, llvm::ISD::SRL_PARTS, llvm::ISD::SSUBO, llvm::ISD::STACKRESTORE, llvm::ISD::STACKSAVE, llvm::ISD::STORE, llvm::ISD::SUB, llvm::ISD::SUBC, llvm::ISD::SUBE, llvm::ISD::TRAP, llvm::ISD::UADDO, llvm::ISD::UDIVREM, llvm::ISD::UINT_TO_FP, llvm::ISD::UMUL_LOHI, llvm::ISD::UMULO, llvm::ISD::UREM, llvm::ISD::USUBO, llvm::MVT::v16i8, llvm::MVT::v1f64, llvm::MVT::v1i64, llvm::MVT::v2f32, llvm::MVT::v2f64, llvm::MVT::v2i16, llvm::MVT::v2i32, llvm::MVT::v2i64, llvm::MVT::v4f16, llvm::MVT::v4f32, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v4i8, llvm::MVT::v8f16, llvm::MVT::v8i16, llvm::MVT::v8i8, llvm::ISD::VAARG, llvm::ISD::VACOPY, llvm::ISD::VAEND, llvm::ISD::VASTART, llvm::MVT::vector_valuetypes(), llvm::ISD::VSELECT, llvm::ISD::XOR, llvm::ISD::ZERO_EXTEND, llvm::TargetLoweringBase::ZeroOrNegativeOneBooleanContent, llvm::TargetLoweringBase::ZeroOrOneBooleanContent, and llvm::ISD::ZEXTLOAD.
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inlineoverridevirtual |
allowsMisalignedMemoryAccesses - Returns true if the target allows unaligned memory accesses of the specified type.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 240 of file AArch64ISelLowering.h.
References llvm::CallingConv::Fast.
Referenced by getOptimalMemOpType().
| CCAssignFn * AArch64TargetLowering::CCAssignFnForCall | ( | CallingConv::ID | CC, |
| bool | IsVarArg | ||
| ) | const |
Selects the correct CCAssignFn for a given CallingConvention value.
Definition at line 2050 of file AArch64ISelLowering.cpp.
References llvm::CallingConv::C, llvm::CallingConv::Fast, llvm::CallingConv::GHC, llvm::AArch64Subtarget::isTargetDarwin(), llvm_unreachable, and llvm::CallingConv::WebKit_JS.
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overridevirtual |
computeKnownBitsForTargetNode - Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets.
Reimplemented from llvm::TargetLowering.
Definition at line 718 of file AArch64ISelLowering.cpp.
References llvm::SelectionDAG::computeKnownBits(), llvm::AArch64ISD::CSEL, llvm::APInt::getBitWidth(), llvm::APInt::getHighBitsSet(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarType(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::ConstantSDNode::getZExtValue(), llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::MVT::v16i8, llvm::MVT::v4i16, llvm::MVT::v8i16, and llvm::MVT::v8i8.
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overridevirtual |
createFastISel - This method returns a target specific FastISel object, or null if the target does not support "fast" ISel.
Reimplemented from llvm::TargetLowering.
Definition at line 784 of file AArch64ISelLowering.cpp.
References llvm::AArch64::createFastISel().
| MachineBasicBlock * AArch64TargetLowering::EmitF128CSEL | ( | MachineInstr * | MI, |
| MachineBasicBlock * | BB | ||
| ) | const |
Definition at line 916 of file AArch64ISelLowering.cpp.
References llvm::MachineBasicBlock::addLiveIn(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MachineFunction::CreateMachineBasicBlock(), llvm::DL, llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), llvm::MCInstrInfo::get(), llvm::MachineBasicBlock::getBasicBlock(), llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getImm(), llvm::AArch64Subtarget::getInstrInfo(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::insert(), llvm::MachineOperand::isKill(), llvm::AArch64SysReg::NZCV, llvm::TargetOpcode::PHI, llvm::MachineBasicBlock::splice(), TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().
Referenced by EmitInstrWithCustomInserter().
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overridevirtual |
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' flag.
These instructions are special in various ways, which require special support to insert. The specified MachineInstr is created but not inserted into any basic blocks, and this method is called to expand it into a sequence of instructions, potentially also creating new basic blocks and control flow. As long as the returned basic block is different (i.e., we created a new one), the custom inserter is free to modify the rest of MBB.
Reimplemented from llvm::TargetLowering.
Definition at line 977 of file AArch64ISelLowering.cpp.
References llvm::MachineInstr::dump(), EmitF128CSEL(), llvm::TargetLoweringBase::emitPatchPoint(), llvm::MachineInstr::getOpcode(), llvm_unreachable, llvm::TargetOpcode::PATCHPOINT, and llvm::TargetOpcode::STACKMAP.
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overridevirtual |
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type.
This may entail some non-trivial operations to truncate or reconstruct types that will be illegal in the backend. See ARMISelLowering for an example implementation.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 9226 of file AArch64ISelLowering.cpp.
References llvm::IRBuilder< preserveNames, T, Inserter >::CreateBitCast(), llvm::IRBuilder< preserveNames, T, Inserter >::CreateCall(), llvm::IRBuilder< preserveNames, T, Inserter >::CreateExtractValue(), llvm::IRBuilder< preserveNames, T, Inserter >::CreateOr(), llvm::IRBuilder< preserveNames, T, Inserter >::CreateShl(), llvm::IRBuilder< preserveNames, T, Inserter >::CreateTruncOrBitCast(), llvm::IRBuilder< preserveNames, T, Inserter >::CreateZExt(), llvm::ConstantInt::get(), llvm::Module::getContext(), llvm::Intrinsic::getDeclaration(), llvm::IRBuilderBase::GetInsertBlock(), llvm::Type::getInt8PtrTy(), llvm::BasicBlock::getParent(), llvm::GlobalValue::getParent(), llvm::Type::getPrimitiveSizeInBits(), llvm::Value::getType(), llvm::Int, and llvm::isAtLeastAcquire().
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overridevirtual |
Perform a store-conditional operation to Addr.
Return the status of the store. This should be 0 if the store succeeded, non-zero otherwise.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 9261 of file AArch64ISelLowering.cpp.
References llvm::IRBuilder< preserveNames, T, Inserter >::CreateBitCast(), llvm::IRBuilder< preserveNames, T, Inserter >::CreateCall(), llvm::IRBuilder< preserveNames, T, Inserter >::CreateLShr(), llvm::IRBuilder< preserveNames, T, Inserter >::CreateTrunc(), llvm::IRBuilder< preserveNames, T, Inserter >::CreateZExtOrBitCast(), llvm::Module::getContext(), llvm::Intrinsic::getDeclaration(), llvm::Function::getFunctionType(), llvm::IRBuilderBase::GetInsertBlock(), llvm::Type::getInt64Ty(), llvm::Type::getInt8PtrTy(), llvm::FunctionType::getParamType(), llvm::BasicBlock::getParent(), llvm::GlobalValue::getParent(), llvm::Type::getPrimitiveSizeInBits(), llvm::Value::getType(), llvm::MipsISD::Hi, llvm::Int, llvm::Type::isArrayTy(), llvm::isAtLeastRelease(), and llvm::MipsISD::Lo.
getFunctionAlignment - Return the Log2 alignment of this function.
Definition at line 2039 of file AArch64ISelLowering.cpp.
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Get the maximum supported factor for interleaved memory accesses.
Default to be the minimum interleave factor: 2.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 309 of file AArch64ISelLowering.h.
Referenced by lowerInterleavedLoad(), and lowerInterleavedStore().
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Returns the target specific optimal type for load and store operations as a result of memset, memcpy, and memmove lowering.
If DstAlign is zero that means it's safe to destination alignment can satisfy any constraint. Similarly if SrcAlign is zero it means there isn't a need to check it against alignment requirement, probably because the source does not need to be loaded. If 'IsMemset' is true, that means it's expanding a memset. If 'ZeroMemset' is true, that means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it does not need to be loaded. It returns EVT::Other if the type should be determined using generic target-independent logic.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 6860 of file AArch64ISelLowering.cpp.
References allowsMisalignedMemoryAccesses(), F(), llvm::MVT::f128, llvm::CallingConv::Fast, llvm::MachineFunction::getFunction(), llvm::Function::hasFnAttribute(), llvm::AArch64Subtarget::hasFPARMv8(), llvm::MVT::i32, llvm::MVT::i64, memOpAlign(), llvm::Attribute::NoImplicitFloat, and llvm::MVT::Other.
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Return the preferred vector type legalization action.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 9187 of file AArch64ISelLowering.cpp.
References llvm::TargetLoweringBase::getPreferredVectorAction(), llvm::EVT::getSimpleVT(), llvm::TargetLoweringBase::TypeWidenVector, llvm::MVT::v1f32, llvm::MVT::v1i16, llvm::MVT::v1i32, and llvm::MVT::v1i8.
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EVT is not used in-tree, but is used by out-of-tree target.
A documentation for this function would be nice...
Reimplemented from llvm::TargetLoweringBase.
Definition at line 778 of file AArch64ISelLowering.cpp.
References llvm::MVT::i64.
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Return the cost of the scaling factor used in the addressing mode represented by AM for this target, for a load/store of the specified type.
If the AM is supported, the return value must be >= 0. If the AM is not supported, it returns a negative value.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 6958 of file AArch64ISelLowering.cpp.
References isLegalAddressingMode(), and llvm::TargetLoweringBase::AddrMode::Scale.
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Returns a 0 terminated array of registers that can be safely used as scratch registers.
Reimplemented from llvm::TargetLowering.
Definition at line 6993 of file AArch64ISelLowering.cpp.
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getSetCCResultType - Return the ISD::SETCC ValueType
Reimplemented from llvm::TargetLoweringBase.
Definition at line 708 of file AArch64ISelLowering.cpp.
References llvm::EVT::changeVectorElementTypeToInteger(), llvm::MVT::i32, and llvm::EVT::isVector().
This method returns the name of a target specific DAG node.
Reimplemented from llvm::TargetLowering.
Definition at line 789 of file AArch64ISelLowering.cpp.
References llvm::AArch64ISD::ADC, llvm::AArch64ISD::ADCS, llvm::AArch64ISD::ADDlow, llvm::AArch64ISD::ADDS, llvm::AArch64ISD::ADRP, llvm::AArch64ISD::ANDS, llvm::AArch64ISD::BICi, llvm::AArch64ISD::BIT, llvm::AArch64ISD::BRCOND, llvm::AArch64ISD::BSL, llvm::AArch64ISD::CALL, llvm::AArch64ISD::CBNZ, llvm::AArch64ISD::CBZ, llvm::AArch64ISD::CMEQ, llvm::AArch64ISD::CMEQz, llvm::AArch64ISD::CMGE, llvm::AArch64ISD::CMGEz, llvm::AArch64ISD::CMGT, llvm::AArch64ISD::CMGTz, llvm::AArch64ISD::CMHI, llvm::AArch64ISD::CMHS, llvm::AArch64ISD::CMLEz, llvm::AArch64ISD::CMLTz, llvm::AArch64ISD::CSEL, llvm::AArch64ISD::CSINC, llvm::AArch64ISD::CSINV, llvm::AArch64ISD::CSNEG, llvm::AArch64ISD::DUP, llvm::AArch64ISD::DUPLANE16, llvm::AArch64ISD::DUPLANE32, llvm::AArch64ISD::DUPLANE64, llvm::AArch64ISD::DUPLANE8, llvm::AArch64ISD::EXT, llvm::AArch64ISD::EXTR, llvm::AArch64ISD::FCMEQ, llvm::AArch64ISD::FCMEQz, llvm::AArch64ISD::FCMGE, llvm::AArch64ISD::FCMGEz, llvm::AArch64ISD::FCMGT, llvm::AArch64ISD::FCMGTz, llvm::AArch64ISD::FCMLEz, llvm::AArch64ISD::FCMLTz, llvm::AArch64ISD::FCMP, llvm::AArch64ISD::FCSEL, llvm::AArch64ISD::FIRST_NUMBER, llvm::AArch64ISD::FMAX, llvm::AArch64ISD::FMIN, llvm::AArch64ISD::FMOV, llvm::AArch64ISD::LD1DUPpost, llvm::AArch64ISD::LD1LANEpost, llvm::AArch64ISD::LD1x2post, llvm::AArch64ISD::LD1x3post, llvm::AArch64ISD::LD1x4post, llvm::AArch64ISD::LD2DUPpost, llvm::AArch64ISD::LD2LANEpost, llvm::AArch64ISD::LD2post, llvm::AArch64ISD::LD3DUPpost, llvm::AArch64ISD::LD3LANEpost, llvm::AArch64ISD::LD3post, llvm::AArch64ISD::LD4DUPpost, llvm::AArch64ISD::LD4LANEpost, llvm::AArch64ISD::LD4post, llvm::AArch64ISD::LOADgot, llvm::AArch64ISD::MOVI, llvm::AArch64ISD::MOVIedit, llvm::AArch64ISD::MOVImsl, llvm::AArch64ISD::MOVIshift, llvm::AArch64ISD::MVNImsl, llvm::AArch64ISD::MVNIshift, llvm::AArch64ISD::NEG, llvm::AArch64ISD::NOT, llvm::AArch64ISD::NVCAST, llvm::AArch64ISD::ORRi, llvm::AArch64ISD::PREFETCH, llvm::AArch64ISD::RET_FLAG, llvm::AArch64ISD::REV16, llvm::AArch64ISD::REV32, llvm::AArch64ISD::REV64, llvm::AArch64ISD::SADDV, llvm::AArch64ISD::SBC, llvm::AArch64ISD::SBCS, llvm::AArch64ISD::SITOF, llvm::AArch64ISD::SMAXV, llvm::AArch64ISD::SMINV, llvm::AArch64ISD::SMULL, llvm::AArch64ISD::SQSHL_I, llvm::AArch64ISD::SQSHLU_I, llvm::AArch64ISD::SRSHR_I, llvm::AArch64ISD::ST1x2post, llvm::AArch64ISD::ST1x3post, llvm::AArch64ISD::ST1x4post, llvm::AArch64ISD::ST2LANEpost, llvm::AArch64ISD::ST2post, llvm::AArch64ISD::ST3LANEpost, llvm::AArch64ISD::ST3post, llvm::AArch64ISD::ST4LANEpost, llvm::AArch64ISD::ST4post, llvm::AArch64ISD::SUBS, llvm::AArch64ISD::TBNZ, llvm::AArch64ISD::TBZ, llvm::AArch64ISD::TC_RETURN, llvm::AArch64ISD::THREAD_POINTER, llvm::AArch64ISD::TLSDESC_CALLSEQ, llvm::AArch64ISD::TRN1, llvm::AArch64ISD::TRN2, llvm::AArch64ISD::UADDV, llvm::AArch64ISD::UITOF, llvm::AArch64ISD::UMAXV, llvm::AArch64ISD::UMINV, llvm::AArch64ISD::UMULL, llvm::AArch64ISD::UQSHL_I, llvm::AArch64ISD::URSHR_I, llvm::AArch64ISD::UZP1, llvm::AArch64ISD::UZP2, llvm::AArch64ISD::VASHR, llvm::AArch64ISD::VLSHR, llvm::AArch64ISD::VSHL, llvm::AArch64ISD::WrapperLarge, llvm::AArch64ISD::ZIP1, and llvm::AArch64ISD::ZIP2.
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getTgtMemIntrinsic - Represent NEON load and store intrinsics as MemIntrinsicNodes.
The associated MachineMemOperands record the alignment specified in the intrinsic calls.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 6435 of file AArch64ISelLowering.cpp.
References llvm::TargetLoweringBase::IntrinsicInfo::align, llvm::CallInst::getArgOperand(), llvm::Type::getContext(), llvm::Module::getDataLayout(), llvm::SequentialType::getElementType(), llvm::Instruction::getModule(), llvm::CallInst::getNumArgOperands(), llvm::Value::getType(), llvm::EVT::getVectorVT(), llvm::MVT::getVT(), llvm::MVT::i128, llvm::MVT::i64, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::Type::isVectorTy(), llvm::TargetLoweringBase::IntrinsicInfo::memVT, llvm::TargetLoweringBase::IntrinsicInfo::offset, llvm::TargetLoweringBase::IntrinsicInfo::opc, llvm::TargetLoweringBase::IntrinsicInfo::ptrVal, llvm::TargetLoweringBase::IntrinsicInfo::readMem, llvm::TargetLoweringBase::IntrinsicInfo::vol, and llvm::TargetLoweringBase::IntrinsicInfo::writeMem.
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True if AtomicExpandPass should use emitLoadLinked/emitStoreConditional and expand AtomicCmpXchgInst.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 9222 of file AArch64ISelLowering.cpp.
Return true if the target supplies and combines to a paired load two loaded values of type LoadedType next to each other in memory.
RequiredAlignment gives the minimal alignment constraints that must be met to be able to select this paired load.
This information is not used to generate actual paired loads, but it is used to generate a sequence of loads that is easier to combine into a paired load. For instance, something like this: a = load i64* addr b = trunc i64 a to i32 c = lshr i64 a, 32 d = trunc i64 c to i32 will be optimized into: b = load i32* addr1 d = load i32* addr2 Where addr1 = addr2 +/- sizeof(i32).
In other words, unless the target performs a post-isel load combining, this information should not be provided because it will generate more loads.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 6679 of file AArch64ISelLowering.cpp.
References llvm::Type::getPrimitiveSizeInBits(), llvm::Type::isFloatTy(), and llvm::Type::isIntegerTy().
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Reimplemented from llvm::TargetLoweringBase.
Definition at line 6689 of file AArch64ISelLowering.cpp.
References llvm::EVT::getSizeInBits(), llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), and llvm::EVT::isSimple().
Returns false if N is a bit extraction pattern of (X >> C) & Mask.
Reimplemented from llvm::TargetLowering.
Definition at line 7004 of file AArch64ISelLowering.cpp.
References llvm::ISD::AND, llvm::SDNode::getConstantOperandVal(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::MVT::i32, llvm::MVT::i64, llvm::isMask_64(), and llvm::ISD::SRL.
isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
fmuladd intrinsics will be expanded to FMAs when this method returns true, otherwise fmuladd is expanded to fmul + fadd.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 6975 of file AArch64ISelLowering.cpp.
References llvm::MVT::f64, llvm::EVT::getScalarType(), llvm::EVT::getSimpleVT(), llvm::EVT::isSimple(), and llvm::MVT::SimpleTy.
Referenced by isProfitableToHoist().
Returns true if the target can instruction select the specified FP immediate natively.
If false, the legalizer will materialize the FP immediate as a load from a constant pool.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 4195 of file AArch64ISelLowering.cpp.
References llvm::MVT::f32, llvm::MVT::f64, llvm::AArch64_AM::getFP32Imm(), llvm::AArch64_AM::getFP64Imm(), and llvm::APFloat::isPosZero().
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Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register with the immediate without having to materialize the immediate into a register.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 6890 of file AArch64ISelLowering.cpp.
Referenced by isLegalICmpImmediate().
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isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 6906 of file AArch64ISelLowering.cpp.
References llvm::TargetLoweringBase::AddrMode::BaseGV, llvm::TargetLoweringBase::AddrMode::BaseOffs, llvm::DataLayout::getTypeSizeInBits(), llvm::TargetLoweringBase::AddrMode::HasBaseReg, llvm::isPowerOf2_64(), llvm::Type::isSized(), llvm::Log2_64(), and llvm::TargetLoweringBase::AddrMode::Scale.
Referenced by getScalingFactorCost().
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Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 6898 of file AArch64ISelLowering.cpp.
References isLegalAddImmediate().
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Returns true if a cast between SrcAS and DestAS is a noop.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 262 of file AArch64ISelLowering.h.
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Return true if folding a constant offset with the given GlobalAddress is legal.
It is frequently not legal in PIC relocation models.
Reimplemented from llvm::TargetLowering.
Definition at line 4189 of file AArch64ISelLowering.cpp.
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Check if it is profitable to hoist instruction in then/else to if.
Not profitable if I and it's user can form a FMA instruction because we prefer FMSUB/FMADD.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 6567 of file AArch64ISelLowering.cpp.
References llvm::TargetOptions::AllowFPOpFusion, llvm::FPOpFusion::Fast, llvm::ISD::FMA, llvm::Module::getDataLayout(), llvm::Instruction::getModule(), llvm::Value::getNumUses(), llvm::Instruction::getOpcode(), llvm::User::getOperand(), llvm::TargetLoweringBase::getTargetMachine(), llvm::Value::getType(), llvm::TargetLoweringBase::getValueType(), isFMAFasterThanFMulAndFAdd(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::TargetMachine::Options, llvm::TargetOptions::UnsafeFPMath, and llvm::Instruction::user_back().
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isShuffleMaskLegal - Return true if the given shuffle mask can be codegen'd directly, or if it should be stack expanded.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 6152 of file AArch64ISelLowering.cpp.
References llvm::EVT::getSizeInBits(), llvm::EVT::getVectorNumElements(), llvm::EVT::is128BitVector(), llvm::EVT::is64BitVector(), isConcatMask(), isEXTMask(), isINSMask(), isREVMask(), llvm::ShuffleVectorSDNode::isSplatMask(), isTRN_v_undef_Mask(), isTRNMask(), isUZP_v_undef_Mask(), isUZPMask(), isZIP_v_undef_Mask(), isZIPMask(), and PerfectShuffleTable.
Referenced by ReconstructShuffle().
Return true if it's free to truncate a value of type Ty1 to type Ty2.
e.g. On x86 it's free to truncate a i32 value in register EAX to i16 by referencing its sub-register AX.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 6549 of file AArch64ISelLowering.cpp.
References llvm::Type::getPrimitiveSizeInBits(), and llvm::Type::isIntegerTy().
Reimplemented from llvm::TargetLoweringBase.
Definition at line 6556 of file AArch64ISelLowering.cpp.
References llvm::EVT::getSizeInBits(), llvm::EVT::isInteger(), and llvm::EVT::isVector().
Return true if any actual instruction that defines a value of type Ty1 implicitly zero-extends the value to Ty2 in the result register.
This does not necessarily include registers defined in unknown ways, such as incoming arguments, or copies from unknown virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this does not necessarily apply to truncate instructions. e.g. on x86-64, all instructions that define 32-bit values implicit zero-extend the result out to 64 bits.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 6595 of file AArch64ISelLowering.cpp.
References llvm::Type::getPrimitiveSizeInBits(), and llvm::Type::isIntegerTy().
Referenced by isZExtFree().
Reimplemented from llvm::TargetLoweringBase.
Definition at line 6602 of file AArch64ISelLowering.cpp.
References llvm::EVT::getSizeInBits(), llvm::EVT::isInteger(), and llvm::EVT::isVector().
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicitly zero-extended such as ARM ldrb / ldrh or because it's folded such as X86 zero-extending loads).
Reimplemented from llvm::TargetLoweringBase.
Definition at line 6610 of file AArch64ISelLowering.cpp.
References llvm::SDValue::getOpcode(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::isInteger(), llvm::EVT::isSimple(), llvm::EVT::isVector(), isZExtFree(), and llvm::ISD::LOAD.
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Lower an interleaved load into a ldN intrinsic.
E.g. Lower an interleaved load (Factor = 2): wide.vec = load <8 x i32>, <8 x i32>* ptr v0 = shuffle wide.vec, undef, <0, 2, 4, 6> ; Extract even elements v1 = shuffle wide.vec, undef, <1, 3, 5, 7> ; Extract odd elements
Into: ld2 = { <4 x i32>, <4 x i32> } call llvm.aarch64.neon.ld2(ptr) vec0 = extractelement { <4 x i32>, <4 x i32> } ld2, i32 0 vec1 = extractelement { <4 x i32>, <4 x i32> } ld2, i32 1
Reimplemented from llvm::TargetLoweringBase.
Definition at line 6711 of file AArch64ISelLowering.cpp.
References llvm::ArrayRef< T >::empty(), llvm::VectorType::get(), llvm::Module::getDataLayout(), llvm::Intrinsic::getDeclaration(), getMaxSupportedInterleaveFactor(), llvm::Instruction::getModule(), llvm::LoadInst::getPointerAddressSpace(), llvm::LoadInst::getPointerOperand(), llvm::Type::getPointerTo(), llvm::ShuffleVectorInst::getType(), llvm::Type::getVectorElementType(), llvm::Type::getVectorNumElements(), llvm::Type::isPointerTy(), llvm::Value::replaceAllUsesWith(), and llvm::ArrayRef< T >::size().
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Lower an interleaved store into a stN intrinsic.
E.g. Lower an interleaved store (Factor = 3): i.vec = shuffle <8 x i32> v0, <8 x i32> v1, <0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11> store <12 x i32> i.vec, <12 x i32>* ptr
Into: sub.v0 = shuffle <8 x i32> v0, <8 x i32> v1, <0, 1, 2, 3> sub.v1 = shuffle <8 x i32> v0, <8 x i32> v1, <4, 5, 6, 7> sub.v2 = shuffle <8 x i32> v0, <8 x i32> v1, <8, 9, 10, 11> call void llvm.aarch64.neon.st3(sub.v0, sub.v1, sub.v2, ptr)
Note that the new shufflevectors will be removed and we'll only generate one st3 instruction in CodeGen.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 6794 of file AArch64ISelLowering.cpp.
References llvm::IRBuilder< preserveNames, T, Inserter >::CreateBitCast(), llvm::IRBuilder< preserveNames, T, Inserter >::CreateCall(), llvm::IRBuilder< preserveNames, T, Inserter >::CreatePtrToInt(), llvm::IRBuilder< preserveNames, T, Inserter >::CreateShuffleVector(), llvm::dyn_cast(), llvm::VectorType::get(), llvm::Module::getDataLayout(), llvm::Intrinsic::getDeclaration(), llvm::DataLayout::getIntPtrType(), getMaxSupportedInterleaveFactor(), llvm::Instruction::getModule(), llvm::User::getOperand(), llvm::StoreInst::getPointerAddressSpace(), llvm::StoreInst::getPointerOperand(), llvm::Type::getPointerTo(), getSequentialMask(), llvm::Value::getType(), llvm::ShuffleVectorInst::getType(), llvm::DataLayout::getTypeAllocSizeInBits(), llvm::Type::getVectorElementType(), llvm::Type::getVectorNumElements(), llvm::Type::isPointerTy(), and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().
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LowerOperation - Provide custom lowering hooks for some operations.
Reimplemented from llvm::TargetLowering.
Definition at line 1934 of file AArch64ISelLowering.cpp.
References llvm::RTLIB::ADD_F128, llvm::ISD::ADDC, llvm::ISD::ADDE, llvm::ISD::AND, llvm::ISD::BITCAST, llvm::ISD::BlockAddress, llvm::ISD::BR_CC, llvm::ISD::BUILD_VECTOR, llvm::ISD::ConstantPool, llvm::ISD::CTPOP, llvm::RTLIB::DIV_F128, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FADD, llvm::ISD::FCOPYSIGN, llvm::ISD::FDIV, llvm::ISD::FMUL, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::ISD::FRAMEADDR, llvm::ISD::FSINCOS, llvm::ISD::FSUB, llvm::SDValue::getOpcode(), llvm::ISD::GlobalAddress, llvm::ISD::GlobalTLSAddress, llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::JumpTable, llvm_unreachable, LowerADDC_ADDE_SUBC_SUBE(), LowerBITCAST(), LowerMUL(), LowerPREFETCH(), LowerXALUO(), LowerXOR(), llvm::ISD::MUL, llvm::RTLIB::MUL_F128, llvm::ISD::OR, llvm::ISD::PREFETCH, llvm::ISD::RETURNADDR, llvm::ISD::SADDO, llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::ISD::SETCC, llvm::ISD::SHL, llvm::ISD::SHL_PARTS, llvm::ISD::SINT_TO_FP, llvm::ISD::SMULO, llvm::ISD::SRA, llvm::ISD::SRA_PARTS, llvm::ISD::SRL, llvm::ISD::SRL_PARTS, llvm::ISD::SSUBO, llvm::RTLIB::SUB_F128, llvm::ISD::SUBC, llvm::ISD::SUBE, llvm::ISD::UADDO, llvm::ISD::UINT_TO_FP, llvm::ISD::UMULO, llvm::ISD::USUBO, llvm::ISD::VAARG, llvm::ISD::VACOPY, llvm::ISD::VASTART, llvm::ISD::VECTOR_SHUFFLE, and llvm::ISD::XOR.
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This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for.
The semantics are as follows: Return Value: SDValue.Val == 0 - No change was made SDValue.Val == N - N was replaced, is dead, and is already handled. otherwise - N should be replaced by the returned Operand.
In addition, methods provided by DAGCombinerInfo may be used to perform more complex transformations.
Reimplemented from llvm::TargetLowering.
Definition at line 8948 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::ANY_EXTEND, llvm::ISD::BITCAST, llvm::AArch64ISD::BRCOND, llvm::ISD::CONCAT_VECTORS, llvm::AArch64ISD::CSEL, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::AArch64ISD::DUP, llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::ISD::MUL, llvm::AArch64ISD::NVCAST, llvm::ISD::OR, performAddSubLongCombine(), performBitcastCombine(), performBRCONDCombine(), performConcatVectorsCombine(), performCONDCombine(), performExtendCombine(), performIntrinsicCombine(), performIntToFpCombine(), performMulCombine(), performNEONPostLDSTCombine(), performNVCASTCombine(), performORCombine(), performPostLD1Combine(), performSelectCCCombine(), performSelectCombine(), performSTORECombine(), performVSelectCombine(), performXorCombine(), llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::STORE, llvm::ISD::SUB, llvm::ISD::UINT_TO_FP, llvm::ISD::VSELECT, llvm::ISD::XOR, and llvm::ISD::ZERO_EXTEND.
| SDValue AArch64TargetLowering::ReconstructShuffle | ( | SDValue | Op, |
| SelectionDAG & | DAG | ||
| ) | const |
Definition at line 4521 of file AArch64ISelLowering.cpp.
References llvm::SmallVectorTemplateCommon< T >::begin(), llvm::ISD::BITCAST, llvm::EVT::bitsLT(), llvm::ISD::BUILD_VECTOR, llvm::ISD::CONCAT_VECTORS, DEBUG, llvm::SmallVectorTemplateCommon< T >::end(), llvm::AArch64ISD::EXT, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), getExtFactor(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::EVT::getVectorVT(), llvm::MVT::i32, llvm::MVT::i64, llvm::SmallVectorImpl< T >::insert(), isShuffleMaskLegal(), fuzzer::min(), llvm::operator==(), llvm::SmallVectorTemplateCommon< T >::size(), llvm::Sched::Source, and llvm::ISD::UNDEF.
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Returns true if it is beneficial to convert a load of a constant to just the constant itself.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 7019 of file AArch64ISelLowering.cpp.
References llvm::countLeadingZeros(), llvm::Type::getPrimitiveSizeInBits(), llvm::APInt::getSExtValue(), llvm::Type::isIntegerTy(), and llvm::AArch64_AM::isLogicalImmediate().
Returns true if the given (atomic) load should be expanded by the IR-level AtomicExpand pass into a load-linked instruction (through emitLoadLinked()).
Reimplemented from llvm::TargetLoweringBase.
Definition at line 9209 of file AArch64ISelLowering.cpp.
References llvm::Type::getPrimitiveSizeInBits(), and llvm::Value::getType().
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Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
Default is to never expand.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 9216 of file AArch64ISelLowering.cpp.
References llvm::Type::getPrimitiveSizeInBits(), llvm::Value::getType(), llvm::TargetLoweringBase::LLSC, and llvm::TargetLoweringBase::None.
Returns true if the given (atomic) store should be expanded by the IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 9201 of file AArch64ISelLowering.cpp.
References llvm::Type::getPrimitiveSizeInBits(), llvm::Value::getType(), and llvm::StoreInst::getValueOperand().
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If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
Reimplemented from llvm::TargetLowering.
Definition at line 9176 of file AArch64ISelLowering.cpp.
1.8.6