24 using namespace Hexagon;
26 #define DEBUG_TYPE "hexagon-mcduplex-info"
30 std::make_pair((
unsigned)V4_SA1_addi, 0),
31 std::make_pair((
unsigned)V4_SA1_addrx, 6144),
32 std::make_pair((
unsigned)V4_SA1_addsp, 3072),
33 std::make_pair((
unsigned)V4_SA1_and1, 4608),
34 std::make_pair((
unsigned)V4_SA1_clrf, 6768),
35 std::make_pair((
unsigned)V4_SA1_clrfnew, 6736),
36 std::make_pair((
unsigned)V4_SA1_clrt, 6752),
37 std::make_pair((
unsigned)V4_SA1_clrtnew, 6720),
38 std::make_pair((
unsigned)V4_SA1_cmpeqi, 6400),
39 std::make_pair((
unsigned)V4_SA1_combine0i, 7168),
40 std::make_pair((
unsigned)V4_SA1_combine1i, 7176),
41 std::make_pair((
unsigned)V4_SA1_combine2i, 7184),
42 std::make_pair((
unsigned)V4_SA1_combine3i, 7192),
43 std::make_pair((
unsigned)V4_SA1_combinerz, 7432),
44 std::make_pair((
unsigned)V4_SA1_combinezr, 7424),
45 std::make_pair((
unsigned)V4_SA1_dec, 4864),
46 std::make_pair((
unsigned)V4_SA1_inc, 4352),
47 std::make_pair((
unsigned)V4_SA1_seti, 2048),
48 std::make_pair((
unsigned)V4_SA1_setin1, 6656),
49 std::make_pair((
unsigned)V4_SA1_sxtb, 5376),
50 std::make_pair((
unsigned)V4_SA1_sxth, 5120),
51 std::make_pair((
unsigned)V4_SA1_tfr, 4096),
52 std::make_pair((
unsigned)V4_SA1_zxtb, 5888),
53 std::make_pair((
unsigned)V4_SA1_zxth, 5632),
54 std::make_pair((
unsigned)V4_SL1_loadri_io, 0),
55 std::make_pair((
unsigned)V4_SL1_loadrub_io, 4096),
56 std::make_pair((
unsigned)V4_SL2_deallocframe, 7936),
57 std::make_pair((
unsigned)V4_SL2_jumpr31, 8128),
58 std::make_pair((
unsigned)V4_SL2_jumpr31_f, 8133),
59 std::make_pair((
unsigned)V4_SL2_jumpr31_fnew, 8135),
60 std::make_pair((
unsigned)V4_SL2_jumpr31_t, 8132),
61 std::make_pair((
unsigned)V4_SL2_jumpr31_tnew, 8134),
62 std::make_pair((
unsigned)V4_SL2_loadrb_io, 4096),
63 std::make_pair((
unsigned)V4_SL2_loadrd_sp, 7680),
64 std::make_pair((
unsigned)V4_SL2_loadrh_io, 0),
65 std::make_pair((
unsigned)V4_SL2_loadri_sp, 7168),
66 std::make_pair((
unsigned)V4_SL2_loadruh_io, 2048),
67 std::make_pair((
unsigned)V4_SL2_return, 8000),
68 std::make_pair((
unsigned)V4_SL2_return_f, 8005),
69 std::make_pair((
unsigned)V4_SL2_return_fnew, 8007),
70 std::make_pair((
unsigned)V4_SL2_return_t, 8004),
71 std::make_pair((
unsigned)V4_SL2_return_tnew, 8006),
72 std::make_pair((
unsigned)V4_SS1_storeb_io, 4096),
73 std::make_pair((
unsigned)V4_SS1_storew_io, 0),
74 std::make_pair((
unsigned)V4_SS2_allocframe, 7168),
75 std::make_pair((
unsigned)V4_SS2_storebi0, 4608),
76 std::make_pair((
unsigned)V4_SS2_storebi1, 4864),
77 std::make_pair((
unsigned)V4_SS2_stored_sp, 2560),
78 std::make_pair((
unsigned)V4_SS2_storeh_io, 0),
79 std::make_pair((
unsigned)V4_SS2_storew_sp, 2048),
80 std::make_pair((
unsigned)V4_SS2_storewi0, 4096),
81 std::make_pair((
unsigned)V4_SS2_storewi1, 4352)};
83 static std::map<unsigned, unsigned>
182 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg;
192 case Hexagon::L2_loadri_io:
211 case Hexagon::L2_loadrub_io:
231 case Hexagon::L2_loadrh_io:
232 case Hexagon::L2_loadruh_io:
243 case Hexagon::L2_loadrb_io:
253 case Hexagon::L2_loadrd_io:
265 case Hexagon::L4_return:
267 case Hexagon::L2_deallocframe:
270 case Hexagon::EH_RETURN_JMPR:
272 case Hexagon::J2_jumpr:
273 case Hexagon::JMPret:
277 if (Hexagon::R31 == DstReg) {
282 case Hexagon::J2_jumprt:
283 case Hexagon::J2_jumprf:
284 case Hexagon::J2_jumprtnew:
285 case Hexagon::J2_jumprfnew:
286 case Hexagon::JMPrett:
287 case Hexagon::JMPretf:
288 case Hexagon::JMPrettnew:
289 case Hexagon::JMPretfnew:
290 case Hexagon::JMPrettnewpt:
291 case Hexagon::JMPretfnewpt:
296 (Hexagon::R31 == DstReg)) {
300 case Hexagon::L4_return_t:
302 case Hexagon::L4_return_f:
304 case Hexagon::L4_return_tnew_pnt:
306 case Hexagon::L4_return_fnew_pnt:
308 case Hexagon::L4_return_tnew_pt:
310 case Hexagon::L4_return_fnew_pt:
313 if (Hexagon::P0 == SrcReg) {
322 case Hexagon::S2_storeri_io:
341 case Hexagon::S2_storerb_io:
360 case Hexagon::S2_storerh_io:
371 case Hexagon::S2_storerd_io:
382 case Hexagon::S4_storeiri_io:
392 case Hexagon::S4_storeirb_io:
401 case Hexagon::S2_allocframe:
425 case Hexagon::A2_addi:
436 if (DstReg == SrcReg) {
448 case Hexagon::A2_add:
458 case Hexagon::A2_andir:
468 case Hexagon::A2_tfr:
477 case Hexagon::A2_tfrsi:
484 case Hexagon::C2_cmoveit:
485 case Hexagon::C2_cmovenewit:
486 case Hexagon::C2_cmoveif:
487 case Hexagon::C2_cmovenewif:
499 case Hexagon::C2_cmpeqi:
503 if (Hexagon::P0 == DstReg &&
509 case Hexagon::A2_combineii:
510 case Hexagon::A4_combineii:
521 case Hexagon::A4_combineri:
531 case Hexagon::A4_combineir:
541 case Hexagon::A2_sxtb:
542 case Hexagon::A2_sxth:
543 case Hexagon::A2_zxtb:
544 case Hexagon::A2_zxth:
560 unsigned DstReg, SrcReg;
563 case Hexagon::A2_addi:
575 case Hexagon::A2_tfrsi:
599 MCInst const &MIa,
bool ExtendedA,
600 MCInst const &MIb,
bool ExtendedB,
601 bool bisReversable) {
608 if ((Opcode != Hexagon::A2_addi) && (Opcode != Hexagon::A2_tfrsi))
620 unsigned zeroedSubInstS0 =
622 unsigned zeroedSubInstS1 =
625 if (zeroedSubInstS0 < zeroedSubInstS1)
632 if (MIb.
getOpcode() == Hexagon::S2_allocframe)
720 case Hexagon::A2_addi:
746 case Hexagon::A2_add:
752 case Hexagon::S2_allocframe:
753 Result.
setOpcode(Hexagon::V4_SS2_allocframe);
756 case Hexagon::A2_andir:
768 case Hexagon::C2_cmpeqi:
769 Result.
setOpcode(Hexagon::V4_SA1_cmpeqi);
773 case Hexagon::A4_combineii:
774 case Hexagon::A2_combineii:
776 Result.
setOpcode(Hexagon::V4_SA1_combine1i);
783 Result.
setOpcode(Hexagon::V4_SA1_combine3i);
789 Result.
setOpcode(Hexagon::V4_SA1_combine0i);
795 Result.
setOpcode(Hexagon::V4_SA1_combine2i);
800 case Hexagon::A4_combineir:
801 Result.
setOpcode(Hexagon::V4_SA1_combinezr);
806 case Hexagon::A4_combineri:
807 Result.
setOpcode(Hexagon::V4_SA1_combinerz);
811 case Hexagon::L4_return_tnew_pnt:
812 case Hexagon::L4_return_tnew_pt:
813 Result.
setOpcode(Hexagon::V4_SL2_return_tnew);
815 case Hexagon::L4_return_fnew_pnt:
816 case Hexagon::L4_return_fnew_pt:
817 Result.
setOpcode(Hexagon::V4_SL2_return_fnew);
819 case Hexagon::L4_return_f:
820 Result.
setOpcode(Hexagon::V4_SL2_return_f);
822 case Hexagon::L4_return_t:
823 Result.
setOpcode(Hexagon::V4_SL2_return_t);
825 case Hexagon::L4_return:
826 Result.
setOpcode(Hexagon::V4_SL2_return);
828 case Hexagon::L2_deallocframe:
829 Result.
setOpcode(Hexagon::V4_SL2_deallocframe);
831 case Hexagon::EH_RETURN_JMPR:
832 case Hexagon::J2_jumpr:
833 case Hexagon::JMPret:
834 Result.
setOpcode(Hexagon::V4_SL2_jumpr31);
836 case Hexagon::J2_jumprf:
837 case Hexagon::JMPretf:
838 Result.
setOpcode(Hexagon::V4_SL2_jumpr31_f);
840 case Hexagon::J2_jumprfnew:
841 case Hexagon::JMPretfnewpt:
842 case Hexagon::JMPretfnew:
843 Result.
setOpcode(Hexagon::V4_SL2_jumpr31_fnew);
845 case Hexagon::J2_jumprt:
846 case Hexagon::JMPrett:
847 Result.
setOpcode(Hexagon::V4_SL2_jumpr31_t);
849 case Hexagon::J2_jumprtnew:
850 case Hexagon::JMPrettnewpt:
851 case Hexagon::JMPrettnew:
852 Result.
setOpcode(Hexagon::V4_SL2_jumpr31_tnew);
854 case Hexagon::L2_loadrb_io:
855 Result.
setOpcode(Hexagon::V4_SL2_loadrb_io);
860 case Hexagon::L2_loadrd_io:
861 Result.
setOpcode(Hexagon::V4_SL2_loadrd_sp);
865 case Hexagon::L2_loadrh_io:
866 Result.
setOpcode(Hexagon::V4_SL2_loadrh_io);
871 case Hexagon::L2_loadrub_io:
872 Result.
setOpcode(Hexagon::V4_SL1_loadrub_io);
877 case Hexagon::L2_loadruh_io:
878 Result.
setOpcode(Hexagon::V4_SL2_loadruh_io);
883 case Hexagon::L2_loadri_io:
885 Result.
setOpcode(Hexagon::V4_SL2_loadri_sp);
890 Result.
setOpcode(Hexagon::V4_SL1_loadri_io);
896 case Hexagon::S4_storeirb_io:
898 Result.
setOpcode(Hexagon::V4_SS2_storebi0);
903 Result.
setOpcode(Hexagon::V4_SS2_storebi1);
908 case Hexagon::S2_storerb_io:
909 Result.
setOpcode(Hexagon::V4_SS1_storeb_io);
914 case Hexagon::S2_storerd_io:
915 Result.
setOpcode(Hexagon::V4_SS2_stored_sp);
919 case Hexagon::S2_storerh_io:
920 Result.
setOpcode(Hexagon::V4_SS2_storeh_io);
925 case Hexagon::S4_storeiri_io:
927 Result.
setOpcode(Hexagon::V4_SS2_storewi0);
932 Result.
setOpcode(Hexagon::V4_SS2_storewi1);
937 Result.
setOpcode(Hexagon::V4_SS2_storew_sp);
942 case Hexagon::S2_storeri_io:
944 Result.
setOpcode(Hexagon::V4_SS2_storew_sp);
948 Result.
setOpcode(Hexagon::V4_SS1_storew_io);
954 case Hexagon::A2_sxtb:
959 case Hexagon::A2_sxth:
964 case Hexagon::A2_tfr:
969 case Hexagon::C2_cmovenewif:
970 Result.
setOpcode(Hexagon::V4_SA1_clrfnew);
973 case Hexagon::C2_cmovenewit:
974 Result.
setOpcode(Hexagon::V4_SA1_clrtnew);
977 case Hexagon::C2_cmoveif:
981 case Hexagon::C2_cmoveit:
985 case Hexagon::A2_tfrsi:
987 Result.
setOpcode(Hexagon::V4_SA1_setin1);
996 case Hexagon::A2_zxtb:
1002 case Hexagon::A2_zxth:
1013 case Hexagon::S2_storeri_io:
1014 case Hexagon::S2_storerb_io:
1015 case Hexagon::S2_storerh_io:
1016 case Hexagon::S2_storerd_io:
1017 case Hexagon::S4_storeiri_io:
1018 case Hexagon::S4_storeirb_io:
1019 case Hexagon::S2_allocframe:
1034 for (
unsigned distance = 1; distance < numInstrInPacket; ++distance) {
1037 (j < numInstrInPacket) && (k < numInstrInPacket); ++j, ++k) {
1040 bool bisReversable =
true;
1043 DEBUG(
dbgs() <<
"skip out of order write pair: " << k <<
"," << j
1045 bisReversable =
false;
1062 DEBUG(
dbgs() <<
"adding pair: " << j <<
"," << k <<
":"
1067 DEBUG(
dbgs() <<
"skipping pair: " << j <<
"," << k <<
":"
1073 if (bisReversable) {
1087 DEBUG(
dbgs() <<
"adding pair:" << k <<
"," << j <<
":"
1091 DEBUG(
dbgs() <<
"skipping pair: " << k <<
"," << j <<
":"
void push_back(const T &Elt)
bool subInstWouldBeExtended(MCInst const &potentialDuplex)
bool isDuplexPair(MCInst const &MIa, MCInst const &MIb)
Symmetrical. See if these two instructions are fit for duplex pair.
bool isIntRegForSubInst(unsigned Reg)
bool isBundle(MCInst const &MCI)
bool isDblRegForSubInst(unsigned Reg)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getReg() const
Returns the register number.
SmallVector< DuplexCandidate, 8 > getDuplexPossibilties(MCInstrInfo const &MCII, MCInst const &MCB)
Instances of this class represent a single low-level machine instruction.
bool isDuplexPairMatch(unsigned Ga, unsigned Gb)
static std::map< unsigned, unsigned > subinstOpcodeMap(opcodeData, opcodeData+sizeof(opcodeData)/sizeof(opcodeData[0]))
unsigned getDuplexCandidateGroup(MCInst const &MI)
Interface to description of machine instruction set.
static void addOps(MCInst &subInstPtr, MCInst const &Inst, unsigned opNum)
void setOpcode(unsigned Op)
size_t const bundleInstructionsOffset
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
bool isOrderedDuplexPair(MCInstrInfo const &MCII, MCInst const &MIa, bool ExtendedA, MCInst const &MIb, bool ExtendedB, bool bisReversable)
non-Symmetrical. See if these two instructions are fit for duplex pair.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
unsigned getOpcode() const
static std::pair< unsigned, unsigned > opcodeData[]
MCInst deriveSubInst(MCInst const &Inst)
bool hasExtenderForIndex(MCInst const &MCB, size_t Index)
unsigned getNumOperands() const
const MCInst * getInst() const
static bool isStoreInst(unsigned opCode)
bool isPredReg(unsigned Reg)
bool isIntReg(unsigned Reg)
void addOperand(const MCOperand &Op)
unsigned iClassOfDuplexPair(unsigned Ga, unsigned Gb)
const MCOperand & getOperand(unsigned i) const