LLVM  3.7.0
MipsSEISelLowering.cpp
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1 //===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Subclass of MipsTargetLowering specialized for mips32/64.
11 //
12 //===----------------------------------------------------------------------===//
13 #include "MipsSEISelLowering.h"
14 #include "MipsMachineFunction.h"
15 #include "MipsRegisterInfo.h"
16 #include "MipsTargetMachine.h"
19 #include "llvm/IR/Intrinsics.h"
21 #include "llvm/Support/Debug.h"
24 
25 using namespace llvm;
26 
27 #define DEBUG_TYPE "mips-isel"
28 
29 static cl::opt<bool>
30 EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden,
31  cl::desc("MIPS: Enable tail calls."), cl::init(false));
32 
33 static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
34  cl::desc("Expand double precision loads and "
35  "stores to their single precision "
36  "counterparts"));
37 
39  const MipsSubtarget &STI)
40  : MipsTargetLowering(TM, STI) {
41  // Set up the register classes
42  addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
43 
44  if (Subtarget.isGP64bit())
45  addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
46 
47  if (Subtarget.hasDSP() || Subtarget.hasMSA()) {
48  // Expand all truncating stores and extending loads.
49  for (MVT VT0 : MVT::vector_valuetypes()) {
50  for (MVT VT1 : MVT::vector_valuetypes()) {
51  setTruncStoreAction(VT0, VT1, Expand);
55  }
56  }
57  }
58 
59  if (Subtarget.hasDSP()) {
61 
62  for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
63  addRegisterClass(VecTys[i], &Mips::DSPRRegClass);
64 
65  // Expand all builtin opcodes.
66  for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
67  setOperationAction(Opc, VecTys[i], Expand);
68 
69  setOperationAction(ISD::ADD, VecTys[i], Legal);
70  setOperationAction(ISD::SUB, VecTys[i], Legal);
71  setOperationAction(ISD::LOAD, VecTys[i], Legal);
72  setOperationAction(ISD::STORE, VecTys[i], Legal);
74  }
75 
81  }
82 
83  if (Subtarget.hasDSPR2())
85 
86  if (Subtarget.hasMSA()) {
87  addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass);
88  addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass);
89  addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass);
90  addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass);
91  addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass);
92  addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass);
93  addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass);
94 
100  }
101 
102  if (!Subtarget.useSoftFloat()) {
103  addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
104 
105  // When dealing with single precision only, use libcalls
106  if (!Subtarget.isSingleFloat()) {
107  if (Subtarget.isFP64bit())
108  addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
109  else
110  addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
111  }
112  }
113 
118 
119  if (Subtarget.hasCnMips())
121  else if (Subtarget.isGP64bit())
123 
124  if (Subtarget.isGP64bit()) {
131  }
132 
135 
141 
145 
149 
150  if (NoDPLoadStore) {
153  }
154 
155  if (Subtarget.hasMips32r6()) {
156  // MIPS32r6 replaces the accumulator-based multiplies with a three register
157  // instruction
163 
164  // MIPS32r6 replaces the accumulator-based division/remainder with separate
165  // three register division and remainder instructions.
172 
173  // MIPS32r6 replaces conditional moves with an equivalent that removes the
174  // need for three GPR read ports.
178 
182 
183  assert(Subtarget.isFP64bit() && "FR=1 is required for MIPS32r6");
187 
189 
190  // Floating point > and >= are supported via < and <=
195 
200  }
201 
202  if (Subtarget.hasMips64r6()) {
203  // MIPS64r6 replaces the accumulator-based multiplies with a three register
204  // instruction
210 
211  // MIPS32r6 replaces the accumulator-based division/remainder with separate
212  // three register division and remainder instructions.
219 
220  // MIPS64r6 replaces conditional moves with an equivalent that removes the
221  // need for three GPR read ports.
225  }
226 
228 }
229 
230 const MipsTargetLowering *
232  const MipsSubtarget &STI) {
233  return new MipsSETargetLowering(TM, STI);
234 }
235 
236 const TargetRegisterClass *
238  if (VT == MVT::Untyped)
239  return Subtarget.hasDSP() ? &Mips::ACC64DSPRegClass : &Mips::ACC64RegClass;
240 
242 }
243 
244 // Enable MSA support for the given integer type and Register class.
247  addRegisterClass(Ty, RC);
248 
249  // Expand all builtin opcodes.
250  for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
251  setOperationAction(Opc, Ty, Expand);
252 
259 
277 
278  if (Ty == MVT::v4i32 || Ty == MVT::v2i64) {
283  }
284 
291 }
292 
293 // Enable MSA support for the given floating-point type and Register class.
296  addRegisterClass(Ty, RC);
297 
298  // Expand all builtin opcodes.
299  for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
300  setOperationAction(Opc, Ty, Expand);
301 
308 
309  if (Ty != MVT::v8f16) {
321 
329  }
330 }
331 
332 bool
334  unsigned,
335  unsigned,
336  bool *Fast) const {
338 
340  // MIPS32r6/MIPS64r6 is required to support unaligned access. It's
341  // implementation defined whether this is handled by hardware, software, or
342  // a hybrid of the two but it's expected that most implementations will
343  // handle the majority of cases in hardware.
344  if (Fast)
345  *Fast = true;
346  return true;
347  }
348 
349  switch (SVT) {
350  case MVT::i64:
351  case MVT::i32:
352  if (Fast)
353  *Fast = true;
354  return true;
355  default:
356  return false;
357  }
358 }
359 
361  SelectionDAG &DAG) const {
362  switch(Op.getOpcode()) {
363  case ISD::LOAD: return lowerLOAD(Op, DAG);
364  case ISD::STORE: return lowerSTORE(Op, DAG);
365  case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
366  case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
367  case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
368  case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
369  case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
370  case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
371  case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true,
372  DAG);
373  case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
374  case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG);
375  case ISD::INTRINSIC_VOID: return lowerINTRINSIC_VOID(Op, DAG);
376  case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG);
377  case ISD::BUILD_VECTOR: return lowerBUILD_VECTOR(Op, DAG);
378  case ISD::VECTOR_SHUFFLE: return lowerVECTOR_SHUFFLE(Op, DAG);
379  }
380 
381  return MipsTargetLowering::LowerOperation(Op, DAG);
382 }
383 
384 // selectMADD -
385 // Transforms a subgraph in CurDAG if the following pattern is found:
386 // (addc multLo, Lo0), (adde multHi, Hi0),
387 // where,
388 // multHi/Lo: product of multiplication
389 // Lo0: initial value of Lo register
390 // Hi0: initial value of Hi register
391 // Return true if pattern matching was successful.
392 static bool selectMADD(SDNode *ADDENode, SelectionDAG *CurDAG) {
393  // ADDENode's second operand must be a flag output of an ADDC node in order
394  // for the matching to be successful.
395  SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
396 
397  if (ADDCNode->getOpcode() != ISD::ADDC)
398  return false;
399 
400  SDValue MultHi = ADDENode->getOperand(0);
401  SDValue MultLo = ADDCNode->getOperand(0);
402  SDNode *MultNode = MultHi.getNode();
403  unsigned MultOpc = MultHi.getOpcode();
404 
405  // MultHi and MultLo must be generated by the same node,
406  if (MultLo.getNode() != MultNode)
407  return false;
408 
409  // and it must be a multiplication.
410  if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
411  return false;
412 
413  // MultLo amd MultHi must be the first and second output of MultNode
414  // respectively.
415  if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
416  return false;
417 
418  // Transform this to a MADD only if ADDENode and ADDCNode are the only users
419  // of the values of MultNode, in which case MultNode will be removed in later
420  // phases.
421  // If there exist users other than ADDENode or ADDCNode, this function returns
422  // here, which will result in MultNode being mapped to a single MULT
423  // instruction node rather than a pair of MULT and MADD instructions being
424  // produced.
425  if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
426  return false;
427 
428  SDLoc DL(ADDENode);
429 
430  // Initialize accumulator.
431  SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped,
432  ADDCNode->getOperand(1),
433  ADDENode->getOperand(1));
434 
435  // create MipsMAdd(u) node
436  MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
437 
438  SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped,
439  MultNode->getOperand(0),// Factor 0
440  MultNode->getOperand(1),// Factor 1
441  ACCIn);
442 
443  // replace uses of adde and addc here
444  if (!SDValue(ADDCNode, 0).use_empty()) {
445  SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MAdd);
446  CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), LoOut);
447  }
448  if (!SDValue(ADDENode, 0).use_empty()) {
449  SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MAdd);
450  CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), HiOut);
451  }
452 
453  return true;
454 }
455 
456 // selectMSUB -
457 // Transforms a subgraph in CurDAG if the following pattern is found:
458 // (addc Lo0, multLo), (sube Hi0, multHi),
459 // where,
460 // multHi/Lo: product of multiplication
461 // Lo0: initial value of Lo register
462 // Hi0: initial value of Hi register
463 // Return true if pattern matching was successful.
464 static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG) {
465  // SUBENode's second operand must be a flag output of an SUBC node in order
466  // for the matching to be successful.
467  SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
468 
469  if (SUBCNode->getOpcode() != ISD::SUBC)
470  return false;
471 
472  SDValue MultHi = SUBENode->getOperand(1);
473  SDValue MultLo = SUBCNode->getOperand(1);
474  SDNode *MultNode = MultHi.getNode();
475  unsigned MultOpc = MultHi.getOpcode();
476 
477  // MultHi and MultLo must be generated by the same node,
478  if (MultLo.getNode() != MultNode)
479  return false;
480 
481  // and it must be a multiplication.
482  if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
483  return false;
484 
485  // MultLo amd MultHi must be the first and second output of MultNode
486  // respectively.
487  if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
488  return false;
489 
490  // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
491  // of the values of MultNode, in which case MultNode will be removed in later
492  // phases.
493  // If there exist users other than SUBENode or SUBCNode, this function returns
494  // here, which will result in MultNode being mapped to a single MULT
495  // instruction node rather than a pair of MULT and MSUB instructions being
496  // produced.
497  if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
498  return false;
499 
500  SDLoc DL(SUBENode);
501 
502  // Initialize accumulator.
503  SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped,
504  SUBCNode->getOperand(0),
505  SUBENode->getOperand(0));
506 
507  // create MipsSub(u) node
508  MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
509 
510  SDValue MSub = CurDAG->getNode(MultOpc, DL, MVT::Glue,
511  MultNode->getOperand(0),// Factor 0
512  MultNode->getOperand(1),// Factor 1
513  ACCIn);
514 
515  // replace uses of sube and subc here
516  if (!SDValue(SUBCNode, 0).use_empty()) {
517  SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MSub);
518  CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), LoOut);
519  }
520  if (!SDValue(SUBENode, 0).use_empty()) {
521  SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MSub);
522  CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), HiOut);
523  }
524 
525  return true;
526 }
527 
530  const MipsSubtarget &Subtarget) {
531  if (DCI.isBeforeLegalize())
532  return SDValue();
533 
534  if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() &&
535  N->getValueType(0) == MVT::i32 && selectMADD(N, &DAG))
536  return SDValue(N, 0);
537 
538  return SDValue();
539 }
540 
541 // Fold zero extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT
542 //
543 // Performs the following transformations:
544 // - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to zero extension if its
545 // sign/zero-extension is completely overwritten by the new one performed by
546 // the ISD::AND.
547 // - Removes redundant zero extensions performed by an ISD::AND.
550  const MipsSubtarget &Subtarget) {
551  if (!Subtarget.hasMSA())
552  return SDValue();
553 
554  SDValue Op0 = N->getOperand(0);
555  SDValue Op1 = N->getOperand(1);
556  unsigned Op0Opcode = Op0->getOpcode();
557 
558  // (and (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d)
559  // where $d + 1 == 2^n and n == 32
560  // or $d + 1 == 2^n and n <= 32 and ZExt
561  // -> (MipsVExtractZExt $a, $b, $c)
562  if (Op0Opcode == MipsISD::VEXTRACT_SEXT_ELT ||
563  Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT) {
564  ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(Op1);
565 
566  if (!Mask)
567  return SDValue();
568 
569  int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2();
570 
571  if (Log2IfPositive <= 0)
572  return SDValue(); // Mask+1 is not a power of 2
573 
574  SDValue Op0Op2 = Op0->getOperand(2);
575  EVT ExtendTy = cast<VTSDNode>(Op0Op2)->getVT();
576  unsigned ExtendTySize = ExtendTy.getSizeInBits();
577  unsigned Log2 = Log2IfPositive;
578 
579  if ((Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT && Log2 >= ExtendTySize) ||
580  Log2 == ExtendTySize) {
581  SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 };
582  return DAG.getNode(MipsISD::VEXTRACT_ZEXT_ELT, SDLoc(Op0),
583  Op0->getVTList(),
584  makeArrayRef(Ops, Op0->getNumOperands()));
585  }
586  }
587 
588  return SDValue();
589 }
590 
591 // Determine if the specified node is a constant vector splat.
592 //
593 // Returns true and sets Imm if:
594 // * N is a ISD::BUILD_VECTOR representing a constant splat
595 //
596 // This function is quite similar to MipsSEDAGToDAGISel::selectVSplat. The
597 // differences are that it assumes the MSA has already been checked and the
598 // arbitrary requirement for a maximum of 32-bit integers isn't applied (and
599 // must not be in order for binsri.d to be selectable).
600 static bool isVSplat(SDValue N, APInt &Imm, bool IsLittleEndian) {
602 
603  if (!Node)
604  return false;
605 
606  APInt SplatValue, SplatUndef;
607  unsigned SplatBitSize;
608  bool HasAnyUndefs;
609 
610  if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
611  8, !IsLittleEndian))
612  return false;
613 
614  Imm = SplatValue;
615 
616  return true;
617 }
618 
619 // Test whether the given node is an all-ones build_vector.
620 static bool isVectorAllOnes(SDValue N) {
621  // Look through bitcasts. Endianness doesn't matter because we are looking
622  // for an all-ones value.
623  if (N->getOpcode() == ISD::BITCAST)
624  N = N->getOperand(0);
625 
627 
628  if (!BVN)
629  return false;
630 
631  APInt SplatValue, SplatUndef;
632  unsigned SplatBitSize;
633  bool HasAnyUndefs;
634 
635  // Endianness doesn't matter in this context because we are looking for
636  // an all-ones value.
637  if (BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs))
638  return SplatValue.isAllOnesValue();
639 
640  return false;
641 }
642 
643 // Test whether N is the bitwise inverse of OfNode.
644 static bool isBitwiseInverse(SDValue N, SDValue OfNode) {
645  if (N->getOpcode() != ISD::XOR)
646  return false;
647 
648  if (isVectorAllOnes(N->getOperand(0)))
649  return N->getOperand(1) == OfNode;
650 
651  if (isVectorAllOnes(N->getOperand(1)))
652  return N->getOperand(0) == OfNode;
653 
654  return false;
655 }
656 
657 // Perform combines where ISD::OR is the root node.
658 //
659 // Performs the following transformations:
660 // - (or (and $a, $mask), (and $b, $inv_mask)) => (vselect $mask, $a, $b)
661 // where $inv_mask is the bitwise inverse of $mask and the 'or' has a 128-bit
662 // vector type.
665  const MipsSubtarget &Subtarget) {
666  if (!Subtarget.hasMSA())
667  return SDValue();
668 
669  EVT Ty = N->getValueType(0);
670 
671  if (!Ty.is128BitVector())
672  return SDValue();
673 
674  SDValue Op0 = N->getOperand(0);
675  SDValue Op1 = N->getOperand(1);
676 
677  if (Op0->getOpcode() == ISD::AND && Op1->getOpcode() == ISD::AND) {
678  SDValue Op0Op0 = Op0->getOperand(0);
679  SDValue Op0Op1 = Op0->getOperand(1);
680  SDValue Op1Op0 = Op1->getOperand(0);
681  SDValue Op1Op1 = Op1->getOperand(1);
682  bool IsLittleEndian = !Subtarget.isLittle();
683 
684  SDValue IfSet, IfClr, Cond;
685  bool IsConstantMask = false;
686  APInt Mask, InvMask;
687 
688  // If Op0Op0 is an appropriate mask, try to find it's inverse in either
689  // Op1Op0, or Op1Op1. Keep track of the Cond, IfSet, and IfClr nodes, while
690  // looking.
691  // IfClr will be set if we find a valid match.
692  if (isVSplat(Op0Op0, Mask, IsLittleEndian)) {
693  Cond = Op0Op0;
694  IfSet = Op0Op1;
695 
696  if (isVSplat(Op1Op0, InvMask, IsLittleEndian) &&
697  Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
698  IfClr = Op1Op1;
699  else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) &&
700  Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
701  IfClr = Op1Op0;
702 
703  IsConstantMask = true;
704  }
705 
706  // If IfClr is not yet set, and Op0Op1 is an appropriate mask, try the same
707  // thing again using this mask.
708  // IfClr will be set if we find a valid match.
709  if (!IfClr.getNode() && isVSplat(Op0Op1, Mask, IsLittleEndian)) {
710  Cond = Op0Op1;
711  IfSet = Op0Op0;
712 
713  if (isVSplat(Op1Op0, InvMask, IsLittleEndian) &&
714  Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
715  IfClr = Op1Op1;
716  else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) &&
717  Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
718  IfClr = Op1Op0;
719 
720  IsConstantMask = true;
721  }
722 
723  // If IfClr is not yet set, try looking for a non-constant match.
724  // IfClr will be set if we find a valid match amongst the eight
725  // possibilities.
726  if (!IfClr.getNode()) {
727  if (isBitwiseInverse(Op0Op0, Op1Op0)) {
728  Cond = Op1Op0;
729  IfSet = Op1Op1;
730  IfClr = Op0Op1;
731  } else if (isBitwiseInverse(Op0Op1, Op1Op0)) {
732  Cond = Op1Op0;
733  IfSet = Op1Op1;
734  IfClr = Op0Op0;
735  } else if (isBitwiseInverse(Op0Op0, Op1Op1)) {
736  Cond = Op1Op1;
737  IfSet = Op1Op0;
738  IfClr = Op0Op1;
739  } else if (isBitwiseInverse(Op0Op1, Op1Op1)) {
740  Cond = Op1Op1;
741  IfSet = Op1Op0;
742  IfClr = Op0Op0;
743  } else if (isBitwiseInverse(Op1Op0, Op0Op0)) {
744  Cond = Op0Op0;
745  IfSet = Op0Op1;
746  IfClr = Op1Op1;
747  } else if (isBitwiseInverse(Op1Op1, Op0Op0)) {
748  Cond = Op0Op0;
749  IfSet = Op0Op1;
750  IfClr = Op1Op0;
751  } else if (isBitwiseInverse(Op1Op0, Op0Op1)) {
752  Cond = Op0Op1;
753  IfSet = Op0Op0;
754  IfClr = Op1Op1;
755  } else if (isBitwiseInverse(Op1Op1, Op0Op1)) {
756  Cond = Op0Op1;
757  IfSet = Op0Op0;
758  IfClr = Op1Op0;
759  }
760  }
761 
762  // At this point, IfClr will be set if we have a valid match.
763  if (!IfClr.getNode())
764  return SDValue();
765 
766  assert(Cond.getNode() && IfSet.getNode());
767 
768  // Fold degenerate cases.
769  if (IsConstantMask) {
770  if (Mask.isAllOnesValue())
771  return IfSet;
772  else if (Mask == 0)
773  return IfClr;
774  }
775 
776  // Transform the DAG into an equivalent VSELECT.
777  return DAG.getNode(ISD::VSELECT, SDLoc(N), Ty, Cond, IfSet, IfClr);
778  }
779 
780  return SDValue();
781 }
782 
785  const MipsSubtarget &Subtarget) {
786  if (DCI.isBeforeLegalize())
787  return SDValue();
788 
789  if (Subtarget.hasMips32() && N->getValueType(0) == MVT::i32 &&
790  selectMSUB(N, &DAG))
791  return SDValue(N, 0);
792 
793  return SDValue();
794 }
795 
796 static SDValue genConstMult(SDValue X, uint64_t C, SDLoc DL, EVT VT,
797  EVT ShiftTy, SelectionDAG &DAG) {
798  // Clear the upper (64 - VT.sizeInBits) bits.
799  C &= ((uint64_t)-1) >> (64 - VT.getSizeInBits());
800 
801  // Return 0.
802  if (C == 0)
803  return DAG.getConstant(0, DL, VT);
804 
805  // Return x.
806  if (C == 1)
807  return X;
808 
809  // If c is power of 2, return (shl x, log2(c)).
810  if (isPowerOf2_64(C))
811  return DAG.getNode(ISD::SHL, DL, VT, X,
812  DAG.getConstant(Log2_64(C), DL, ShiftTy));
813 
814  unsigned Log2Ceil = Log2_64_Ceil(C);
815  uint64_t Floor = 1LL << Log2_64(C);
816  uint64_t Ceil = Log2Ceil == 64 ? 0LL : 1LL << Log2Ceil;
817 
818  // If |c - floor_c| <= |c - ceil_c|,
819  // where floor_c = pow(2, floor(log2(c))) and ceil_c = pow(2, ceil(log2(c))),
820  // return (add constMult(x, floor_c), constMult(x, c - floor_c)).
821  if (C - Floor <= Ceil - C) {
822  SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG);
823  SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG);
824  return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1);
825  }
826 
827  // If |c - floor_c| > |c - ceil_c|,
828  // return (sub constMult(x, ceil_c), constMult(x, ceil_c - c)).
829  SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG);
830  SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG);
831  return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1);
832 }
833 
836  const MipsSETargetLowering *TL) {
837  EVT VT = N->getValueType(0);
838 
839  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
840  if (!VT.isVector())
841  return genConstMult(N->getOperand(0), C->getZExtValue(), SDLoc(N), VT,
842  TL->getScalarShiftAmountTy(DAG.getDataLayout(), VT),
843  DAG);
844 
845  return SDValue(N, 0);
846 }
847 
848 static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty,
849  SelectionDAG &DAG,
850  const MipsSubtarget &Subtarget) {
851  // See if this is a vector splat immediate node.
852  APInt SplatValue, SplatUndef;
853  unsigned SplatBitSize;
854  bool HasAnyUndefs;
855  unsigned EltSize = Ty.getVectorElementType().getSizeInBits();
857 
858  if (!Subtarget.hasDSP())
859  return SDValue();
860 
861  if (!BV ||
862  !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
863  EltSize, !Subtarget.isLittle()) ||
864  (SplatBitSize != EltSize) ||
865  (SplatValue.getZExtValue() >= EltSize))
866  return SDValue();
867 
868  SDLoc DL(N);
869  return DAG.getNode(Opc, DL, Ty, N->getOperand(0),
870  DAG.getConstant(SplatValue.getZExtValue(), DL, MVT::i32));
871 }
872 
875  const MipsSubtarget &Subtarget) {
876  EVT Ty = N->getValueType(0);
877 
878  if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
879  return SDValue();
880 
881  return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget);
882 }
883 
884 // Fold sign-extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT for MSA and fold
885 // constant splats into MipsISD::SHRA_DSP for DSPr2.
886 //
887 // Performs the following transformations:
888 // - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to sign extension if its
889 // sign/zero-extension is completely overwritten by the new one performed by
890 // the ISD::SRA and ISD::SHL nodes.
891 // - Removes redundant sign extensions performed by an ISD::SRA and ISD::SHL
892 // sequence.
893 //
894 // See performDSPShiftCombine for more information about the transformation
895 // used for DSPr2.
898  const MipsSubtarget &Subtarget) {
899  EVT Ty = N->getValueType(0);
900 
901  if (Subtarget.hasMSA()) {
902  SDValue Op0 = N->getOperand(0);
903  SDValue Op1 = N->getOperand(1);
904 
905  // (sra (shl (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d), imm:$d)
906  // where $d + sizeof($c) == 32
907  // or $d + sizeof($c) <= 32 and SExt
908  // -> (MipsVExtractSExt $a, $b, $c)
909  if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) {
910  SDValue Op0Op0 = Op0->getOperand(0);
911  ConstantSDNode *ShAmount = dyn_cast<ConstantSDNode>(Op1);
912 
913  if (!ShAmount)
914  return SDValue();
915 
916  if (Op0Op0->getOpcode() != MipsISD::VEXTRACT_SEXT_ELT &&
918  return SDValue();
919 
920  EVT ExtendTy = cast<VTSDNode>(Op0Op0->getOperand(2))->getVT();
921  unsigned TotalBits = ShAmount->getZExtValue() + ExtendTy.getSizeInBits();
922 
923  if (TotalBits == 32 ||
924  (Op0Op0->getOpcode() == MipsISD::VEXTRACT_SEXT_ELT &&
925  TotalBits <= 32)) {
926  SDValue Ops[] = { Op0Op0->getOperand(0), Op0Op0->getOperand(1),
927  Op0Op0->getOperand(2) };
928  return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, SDLoc(Op0Op0),
929  Op0Op0->getVTList(),
930  makeArrayRef(Ops, Op0Op0->getNumOperands()));
931  }
932  }
933  }
934 
935  if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget.hasDSPR2()))
936  return SDValue();
937 
938  return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget);
939 }
940 
941 
944  const MipsSubtarget &Subtarget) {
945  EVT Ty = N->getValueType(0);
946 
947  if (((Ty != MVT::v2i16) || !Subtarget.hasDSPR2()) && (Ty != MVT::v4i8))
948  return SDValue();
949 
950  return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget);
951 }
952 
953 static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) {
954  bool IsV216 = (Ty == MVT::v2i16);
955 
956  switch (CC) {
957  case ISD::SETEQ:
958  case ISD::SETNE: return true;
959  case ISD::SETLT:
960  case ISD::SETLE:
961  case ISD::SETGT:
962  case ISD::SETGE: return IsV216;
963  case ISD::SETULT:
964  case ISD::SETULE:
965  case ISD::SETUGT:
966  case ISD::SETUGE: return !IsV216;
967  default: return false;
968  }
969 }
970 
972  EVT Ty = N->getValueType(0);
973 
974  if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
975  return SDValue();
976 
977  if (!isLegalDSPCondCode(Ty, cast<CondCodeSDNode>(N->getOperand(2))->get()))
978  return SDValue();
979 
980  return DAG.getNode(MipsISD::SETCC_DSP, SDLoc(N), Ty, N->getOperand(0),
981  N->getOperand(1), N->getOperand(2));
982 }
983 
985  EVT Ty = N->getValueType(0);
986 
987  if (Ty.is128BitVector() && Ty.isInteger()) {
988  // Try the following combines:
989  // (vselect (setcc $a, $b, SETLT), $b, $a)) -> (vsmax $a, $b)
990  // (vselect (setcc $a, $b, SETLE), $b, $a)) -> (vsmax $a, $b)
991  // (vselect (setcc $a, $b, SETLT), $a, $b)) -> (vsmin $a, $b)
992  // (vselect (setcc $a, $b, SETLE), $a, $b)) -> (vsmin $a, $b)
993  // (vselect (setcc $a, $b, SETULT), $b, $a)) -> (vumax $a, $b)
994  // (vselect (setcc $a, $b, SETULE), $b, $a)) -> (vumax $a, $b)
995  // (vselect (setcc $a, $b, SETULT), $a, $b)) -> (vumin $a, $b)
996  // (vselect (setcc $a, $b, SETULE), $a, $b)) -> (vumin $a, $b)
997  // SETGT/SETGE/SETUGT/SETUGE variants of these will show up initially but
998  // will be expanded to equivalent SETLT/SETLE/SETULT/SETULE versions by the
999  // legalizer.
1000  SDValue Op0 = N->getOperand(0);
1001 
1002  if (Op0->getOpcode() != ISD::SETCC)
1003  return SDValue();
1004 
1005  ISD::CondCode CondCode = cast<CondCodeSDNode>(Op0->getOperand(2))->get();
1006  bool Signed;
1007 
1008  if (CondCode == ISD::SETLT || CondCode == ISD::SETLE)
1009  Signed = true;
1010  else if (CondCode == ISD::SETULT || CondCode == ISD::SETULE)
1011  Signed = false;
1012  else
1013  return SDValue();
1014 
1015  SDValue Op1 = N->getOperand(1);
1016  SDValue Op2 = N->getOperand(2);
1017  SDValue Op0Op0 = Op0->getOperand(0);
1018  SDValue Op0Op1 = Op0->getOperand(1);
1019 
1020  if (Op1 == Op0Op0 && Op2 == Op0Op1)
1021  return DAG.getNode(Signed ? MipsISD::VSMIN : MipsISD::VUMIN, SDLoc(N),
1022  Ty, Op1, Op2);
1023  else if (Op1 == Op0Op1 && Op2 == Op0Op0)
1024  return DAG.getNode(Signed ? MipsISD::VSMAX : MipsISD::VUMAX, SDLoc(N),
1025  Ty, Op1, Op2);
1026  } else if ((Ty == MVT::v2i16) || (Ty == MVT::v4i8)) {
1027  SDValue SetCC = N->getOperand(0);
1028 
1029  if (SetCC.getOpcode() != MipsISD::SETCC_DSP)
1030  return SDValue();
1031 
1032  return DAG.getNode(MipsISD::SELECT_CC_DSP, SDLoc(N), Ty,
1033  SetCC.getOperand(0), SetCC.getOperand(1),
1034  N->getOperand(1), N->getOperand(2), SetCC.getOperand(2));
1035  }
1036 
1037  return SDValue();
1038 }
1039 
1041  const MipsSubtarget &Subtarget) {
1042  EVT Ty = N->getValueType(0);
1043 
1044  if (Subtarget.hasMSA() && Ty.is128BitVector() && Ty.isInteger()) {
1045  // Try the following combines:
1046  // (xor (or $a, $b), (build_vector allones))
1047  // (xor (or $a, $b), (bitcast (build_vector allones)))
1048  SDValue Op0 = N->getOperand(0);
1049  SDValue Op1 = N->getOperand(1);
1050  SDValue NotOp;
1051 
1053  NotOp = Op1;
1054  else if (ISD::isBuildVectorAllOnes(Op1.getNode()))
1055  NotOp = Op0;
1056  else
1057  return SDValue();
1058 
1059  if (NotOp->getOpcode() == ISD::OR)
1060  return DAG.getNode(MipsISD::VNOR, SDLoc(N), Ty, NotOp->getOperand(0),
1061  NotOp->getOperand(1));
1062  }
1063 
1064  return SDValue();
1065 }
1066 
1067 SDValue
1069  SelectionDAG &DAG = DCI.DAG;
1070  SDValue Val;
1071 
1072  switch (N->getOpcode()) {
1073  case ISD::ADDE:
1074  return performADDECombine(N, DAG, DCI, Subtarget);
1075  case ISD::AND:
1076  Val = performANDCombine(N, DAG, DCI, Subtarget);
1077  break;
1078  case ISD::OR:
1079  Val = performORCombine(N, DAG, DCI, Subtarget);
1080  break;
1081  case ISD::SUBE:
1082  return performSUBECombine(N, DAG, DCI, Subtarget);
1083  case ISD::MUL:
1084  return performMULCombine(N, DAG, DCI, this);
1085  case ISD::SHL:
1086  return performSHLCombine(N, DAG, DCI, Subtarget);
1087  case ISD::SRA:
1088  return performSRACombine(N, DAG, DCI, Subtarget);
1089  case ISD::SRL:
1090  return performSRLCombine(N, DAG, DCI, Subtarget);
1091  case ISD::VSELECT:
1092  return performVSELECTCombine(N, DAG);
1093  case ISD::XOR:
1094  Val = performXORCombine(N, DAG, Subtarget);
1095  break;
1096  case ISD::SETCC:
1097  Val = performSETCCCombine(N, DAG);
1098  break;
1099  }
1100 
1101  if (Val.getNode()) {
1102  DEBUG(dbgs() << "\nMipsSE DAG Combine:\n";
1103  N->printrWithDepth(dbgs(), &DAG);
1104  dbgs() << "\n=> \n";
1105  Val.getNode()->printrWithDepth(dbgs(), &DAG);
1106  dbgs() << "\n");
1107  return Val;
1108  }
1109 
1111 }
1112 
1115  MachineBasicBlock *BB) const {
1116  switch (MI->getOpcode()) {
1117  default:
1119  case Mips::BPOSGE32_PSEUDO:
1120  return emitBPOSGE32(MI, BB);
1121  case Mips::SNZ_B_PSEUDO:
1122  return emitMSACBranchPseudo(MI, BB, Mips::BNZ_B);
1123  case Mips::SNZ_H_PSEUDO:
1124  return emitMSACBranchPseudo(MI, BB, Mips::BNZ_H);
1125  case Mips::SNZ_W_PSEUDO:
1126  return emitMSACBranchPseudo(MI, BB, Mips::BNZ_W);
1127  case Mips::SNZ_D_PSEUDO:
1128  return emitMSACBranchPseudo(MI, BB, Mips::BNZ_D);
1129  case Mips::SNZ_V_PSEUDO:
1130  return emitMSACBranchPseudo(MI, BB, Mips::BNZ_V);
1131  case Mips::SZ_B_PSEUDO:
1132  return emitMSACBranchPseudo(MI, BB, Mips::BZ_B);
1133  case Mips::SZ_H_PSEUDO:
1134  return emitMSACBranchPseudo(MI, BB, Mips::BZ_H);
1135  case Mips::SZ_W_PSEUDO:
1136  return emitMSACBranchPseudo(MI, BB, Mips::BZ_W);
1137  case Mips::SZ_D_PSEUDO:
1138  return emitMSACBranchPseudo(MI, BB, Mips::BZ_D);
1139  case Mips::SZ_V_PSEUDO:
1140  return emitMSACBranchPseudo(MI, BB, Mips::BZ_V);
1141  case Mips::COPY_FW_PSEUDO:
1142  return emitCOPY_FW(MI, BB);
1143  case Mips::COPY_FD_PSEUDO:
1144  return emitCOPY_FD(MI, BB);
1145  case Mips::INSERT_FW_PSEUDO:
1146  return emitINSERT_FW(MI, BB);
1147  case Mips::INSERT_FD_PSEUDO:
1148  return emitINSERT_FD(MI, BB);
1149  case Mips::INSERT_B_VIDX_PSEUDO:
1150  case Mips::INSERT_B_VIDX64_PSEUDO:
1151  return emitINSERT_DF_VIDX(MI, BB, 1, false);
1152  case Mips::INSERT_H_VIDX_PSEUDO:
1153  case Mips::INSERT_H_VIDX64_PSEUDO:
1154  return emitINSERT_DF_VIDX(MI, BB, 2, false);
1155  case Mips::INSERT_W_VIDX_PSEUDO:
1156  case Mips::INSERT_W_VIDX64_PSEUDO:
1157  return emitINSERT_DF_VIDX(MI, BB, 4, false);
1158  case Mips::INSERT_D_VIDX_PSEUDO:
1159  case Mips::INSERT_D_VIDX64_PSEUDO:
1160  return emitINSERT_DF_VIDX(MI, BB, 8, false);
1161  case Mips::INSERT_FW_VIDX_PSEUDO:
1162  case Mips::INSERT_FW_VIDX64_PSEUDO:
1163  return emitINSERT_DF_VIDX(MI, BB, 4, true);
1164  case Mips::INSERT_FD_VIDX_PSEUDO:
1165  case Mips::INSERT_FD_VIDX64_PSEUDO:
1166  return emitINSERT_DF_VIDX(MI, BB, 8, true);
1167  case Mips::FILL_FW_PSEUDO:
1168  return emitFILL_FW(MI, BB);
1169  case Mips::FILL_FD_PSEUDO:
1170  return emitFILL_FD(MI, BB);
1171  case Mips::FEXP2_W_1_PSEUDO:
1172  return emitFEXP2_W_1(MI, BB);
1173  case Mips::FEXP2_D_1_PSEUDO:
1174  return emitFEXP2_D_1(MI, BB);
1175  }
1176 }
1177 
1178 bool MipsSETargetLowering::isEligibleForTailCallOptimization(
1179  const CCState &CCInfo, unsigned NextStackOffset,
1180  const MipsFunctionInfo &FI) const {
1181  if (!EnableMipsTailCalls)
1182  return false;
1183 
1184  // Return false if either the callee or caller has a byval argument.
1185  if (CCInfo.getInRegsParamsCount() > 0 || FI.hasByvalArg())
1186  return false;
1187 
1188  // Return true if the callee's argument area is no larger than the
1189  // caller's.
1190  return NextStackOffset <= FI.getIncomingArgSize();
1191 }
1192 
1193 void MipsSETargetLowering::
1194 getOpndList(SmallVectorImpl<SDValue> &Ops,
1195  std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
1196  bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
1197  bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
1198  SDValue Chain) const {
1199  Ops.push_back(Callee);
1200  MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
1201  InternalLinkage, IsCallReloc, CLI, Callee,
1202  Chain);
1203 }
1204 
1205 SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1206  LoadSDNode &Nd = *cast<LoadSDNode>(Op);
1207 
1208  if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
1209  return MipsTargetLowering::lowerLOAD(Op, DAG);
1210 
1211  // Replace a double precision load with two i32 loads and a buildpair64.
1212  SDLoc DL(Op);
1213  SDValue Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
1214  EVT PtrVT = Ptr.getValueType();
1215 
1216  // i32 load from lower address.
1217  SDValue Lo = DAG.getLoad(MVT::i32, DL, Chain, Ptr,
1219  Nd.isNonTemporal(), Nd.isInvariant(),
1220  Nd.getAlignment());
1221 
1222  // i32 load from higher address.
1223  Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, DL, PtrVT));
1224  SDValue Hi = DAG.getLoad(MVT::i32, DL, Lo.getValue(1), Ptr,
1226  Nd.isNonTemporal(), Nd.isInvariant(),
1227  std::min(Nd.getAlignment(), 4U));
1228 
1229  if (!Subtarget.isLittle())
1230  std::swap(Lo, Hi);
1231 
1233  SDValue Ops[2] = {BP, Hi.getValue(1)};
1234  return DAG.getMergeValues(Ops, DL);
1235 }
1236 
1237 SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1238  StoreSDNode &Nd = *cast<StoreSDNode>(Op);
1239 
1240  if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
1241  return MipsTargetLowering::lowerSTORE(Op, DAG);
1242 
1243  // Replace a double precision store with two extractelement64s and i32 stores.
1244  SDLoc DL(Op);
1245  SDValue Val = Nd.getValue(), Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
1246  EVT PtrVT = Ptr.getValueType();
1248  Val, DAG.getConstant(0, DL, MVT::i32));
1250  Val, DAG.getConstant(1, DL, MVT::i32));
1251 
1252  if (!Subtarget.isLittle())
1253  std::swap(Lo, Hi);
1254 
1255  // i32 store to lower address.
1256  Chain = DAG.getStore(Chain, DL, Lo, Ptr, MachinePointerInfo(),
1257  Nd.isVolatile(), Nd.isNonTemporal(), Nd.getAlignment(),
1258  Nd.getAAInfo());
1259 
1260  // i32 store to higher address.
1261  Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, DL, PtrVT));
1262  return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(),
1263  Nd.isVolatile(), Nd.isNonTemporal(),
1264  std::min(Nd.getAlignment(), 4U), Nd.getAAInfo());
1265 }
1266 
1267 SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
1268  bool HasLo, bool HasHi,
1269  SelectionDAG &DAG) const {
1270  // MIPS32r6/MIPS64r6 removed accumulator based multiplies.
1271  assert(!Subtarget.hasMips32r6());
1272 
1273  EVT Ty = Op.getOperand(0).getValueType();
1274  SDLoc DL(Op);
1275  SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped,
1276  Op.getOperand(0), Op.getOperand(1));
1277  SDValue Lo, Hi;
1278 
1279  if (HasLo)
1280  Lo = DAG.getNode(MipsISD::MFLO, DL, Ty, Mult);
1281  if (HasHi)
1282  Hi = DAG.getNode(MipsISD::MFHI, DL, Ty, Mult);
1283 
1284  if (!HasLo || !HasHi)
1285  return HasLo ? Lo : Hi;
1286 
1287  SDValue Vals[] = { Lo, Hi };
1288  return DAG.getMergeValues(Vals, DL);
1289 }
1290 
1291 
1293  SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
1294  DAG.getConstant(0, DL, MVT::i32));
1295  SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
1296  DAG.getConstant(1, DL, MVT::i32));
1297  return DAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, InLo, InHi);
1298 }
1299 
1301  SDValue Lo = DAG.getNode(MipsISD::MFLO, DL, MVT::i32, Op);
1302  SDValue Hi = DAG.getNode(MipsISD::MFHI, DL, MVT::i32, Op);
1303  return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
1304 }
1305 
1306 // This function expands mips intrinsic nodes which have 64-bit input operands
1307 // or output values.
1308 //
1309 // out64 = intrinsic-node in64
1310 // =>
1311 // lo = copy (extract-element (in64, 0))
1312 // hi = copy (extract-element (in64, 1))
1313 // mips-specific-node
1314 // v0 = copy lo
1315 // v1 = copy hi
1316 // out64 = merge-values (v0, v1)
1317 //
1318 static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1319  SDLoc DL(Op);
1320  bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
1322  unsigned OpNo = 0;
1323 
1324  // See if Op has a chain input.
1325  if (HasChainIn)
1326  Ops.push_back(Op->getOperand(OpNo++));
1327 
1328  // The next operand is the intrinsic opcode.
1329  assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant);
1330 
1331  // See if the next operand has type i64.
1332  SDValue Opnd = Op->getOperand(++OpNo), In64;
1333 
1334  if (Opnd.getValueType() == MVT::i64)
1335  In64 = initAccumulator(Opnd, DL, DAG);
1336  else
1337  Ops.push_back(Opnd);
1338 
1339  // Push the remaining operands.
1340  for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo)
1341  Ops.push_back(Op->getOperand(OpNo));
1342 
1343  // Add In64 to the end of the list.
1344  if (In64.getNode())
1345  Ops.push_back(In64);
1346 
1347  // Scan output.
1348  SmallVector<EVT, 2> ResTys;
1349 
1350  for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end();
1351  I != E; ++I)
1352  ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I);
1353 
1354  // Create node.
1355  SDValue Val = DAG.getNode(Opc, DL, ResTys, Ops);
1356  SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val;
1357 
1358  if (!HasChainIn)
1359  return Out;
1360 
1361  assert(Val->getValueType(1) == MVT::Other);
1362  SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) };
1363  return DAG.getMergeValues(Vals, DL);
1364 }
1365 
1366 // Lower an MSA copy intrinsic into the specified SelectionDAG node
1367 static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1368  SDLoc DL(Op);
1369  SDValue Vec = Op->getOperand(1);
1370  SDValue Idx = Op->getOperand(2);
1371  EVT ResTy = Op->getValueType(0);
1372  EVT EltTy = Vec->getValueType(0).getVectorElementType();
1373 
1374  SDValue Result = DAG.getNode(Opc, DL, ResTy, Vec, Idx,
1375  DAG.getValueType(EltTy));
1376 
1377  return Result;
1378 }
1379 
1380 static SDValue lowerMSASplatZExt(SDValue Op, unsigned OpNr, SelectionDAG &DAG) {
1381  EVT ResVecTy = Op->getValueType(0);
1382  EVT ViaVecTy = ResVecTy;
1383  SDLoc DL(Op);
1384 
1385  // When ResVecTy == MVT::v2i64, LaneA is the upper 32 bits of the lane and
1386  // LaneB is the lower 32-bits. Otherwise LaneA and LaneB are alternating
1387  // lanes.
1388  SDValue LaneA;
1389  SDValue LaneB = Op->getOperand(2);
1390 
1391  if (ResVecTy == MVT::v2i64) {
1392  LaneA = DAG.getConstant(0, DL, MVT::i32);
1393  ViaVecTy = MVT::v4i32;
1394  } else
1395  LaneA = LaneB;
1396 
1397  SDValue Ops[16] = { LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB,
1398  LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB };
1399 
1400  SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy,
1401  makeArrayRef(Ops, ViaVecTy.getVectorNumElements()));
1402 
1403  if (ViaVecTy != ResVecTy)
1404  Result = DAG.getNode(ISD::BITCAST, DL, ResVecTy, Result);
1405 
1406  return Result;
1407 }
1408 
1409 static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG) {
1410  return DAG.getConstant(Op->getConstantOperandVal(ImmOp), SDLoc(Op),
1411  Op->getValueType(0));
1412 }
1413 
1414 static SDValue getBuildVectorSplat(EVT VecTy, SDValue SplatValue,
1415  bool BigEndian, SelectionDAG &DAG) {
1416  EVT ViaVecTy = VecTy;
1417  SDValue SplatValueA = SplatValue;
1418  SDValue SplatValueB = SplatValue;
1419  SDLoc DL(SplatValue);
1420 
1421  if (VecTy == MVT::v2i64) {
1422  // v2i64 BUILD_VECTOR must be performed via v4i32 so split into i32's.
1423  ViaVecTy = MVT::v4i32;
1424 
1425  SplatValueA = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValue);
1426  SplatValueB = DAG.getNode(ISD::SRL, DL, MVT::i64, SplatValue,
1427  DAG.getConstant(32, DL, MVT::i32));
1428  SplatValueB = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValueB);
1429  }
1430 
1431  // We currently hold the parts in little endian order. Swap them if
1432  // necessary.
1433  if (BigEndian)
1434  std::swap(SplatValueA, SplatValueB);
1435 
1436  SDValue Ops[16] = { SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1437  SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1438  SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1439  SplatValueA, SplatValueB, SplatValueA, SplatValueB };
1440 
1441  SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy,
1442  makeArrayRef(Ops, ViaVecTy.getVectorNumElements()));
1443 
1444  if (VecTy != ViaVecTy)
1445  Result = DAG.getNode(ISD::BITCAST, DL, VecTy, Result);
1446 
1447  return Result;
1448 }
1449 
1451  unsigned Opc, SDValue Imm,
1452  bool BigEndian) {
1453  EVT VecTy = Op->getValueType(0);
1454  SDValue Exp2Imm;
1455  SDLoc DL(Op);
1456 
1457  // The DAG Combiner can't constant fold bitcasted vectors yet so we must do it
1458  // here for now.
1459  if (VecTy == MVT::v2i64) {
1460  if (ConstantSDNode *CImm = dyn_cast<ConstantSDNode>(Imm)) {
1461  APInt BitImm = APInt(64, 1) << CImm->getAPIntValue();
1462 
1463  SDValue BitImmHiOp = DAG.getConstant(BitImm.lshr(32).trunc(32), DL,
1464  MVT::i32);
1465  SDValue BitImmLoOp = DAG.getConstant(BitImm.trunc(32), DL, MVT::i32);
1466 
1467  if (BigEndian)
1468  std::swap(BitImmLoOp, BitImmHiOp);
1469 
1470  Exp2Imm =
1471  DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
1472  DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i32, BitImmLoOp,
1473  BitImmHiOp, BitImmLoOp, BitImmHiOp));
1474  }
1475  }
1476 
1477  if (!Exp2Imm.getNode()) {
1478  // We couldnt constant fold, do a vector shift instead
1479 
1480  // Extend i32 to i64 if necessary. Sign or zero extend doesn't matter since
1481  // only values 0-63 are valid.
1482  if (VecTy == MVT::v2i64)
1483  Imm = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Imm);
1484 
1485  Exp2Imm = getBuildVectorSplat(VecTy, Imm, BigEndian, DAG);
1486 
1487  Exp2Imm = DAG.getNode(ISD::SHL, DL, VecTy, DAG.getConstant(1, DL, VecTy),
1488  Exp2Imm);
1489  }
1490 
1491  return DAG.getNode(Opc, DL, VecTy, Op->getOperand(1), Exp2Imm);
1492 }
1493 
1495  EVT ResTy = Op->getValueType(0);
1496  SDLoc DL(Op);
1497  SDValue One = DAG.getConstant(1, DL, ResTy);
1498  SDValue Bit = DAG.getNode(ISD::SHL, DL, ResTy, One, Op->getOperand(2));
1499 
1500  return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1),
1501  DAG.getNOT(DL, Bit, ResTy));
1502 }
1503 
1505  SDLoc DL(Op);
1506  EVT ResTy = Op->getValueType(0);
1507  APInt BitImm = APInt(ResTy.getVectorElementType().getSizeInBits(), 1)
1508  << cast<ConstantSDNode>(Op->getOperand(2))->getAPIntValue();
1509  SDValue BitMask = DAG.getConstant(~BitImm, DL, ResTy);
1510 
1511  return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1), BitMask);
1512 }
1513 
1514 SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
1515  SelectionDAG &DAG) const {
1516  SDLoc DL(Op);
1517 
1518  switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) {
1519  default:
1520  return SDValue();
1521  case Intrinsic::mips_shilo:
1522  return lowerDSPIntr(Op, DAG, MipsISD::SHILO);
1523  case Intrinsic::mips_dpau_h_qbl:
1524  return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL);
1525  case Intrinsic::mips_dpau_h_qbr:
1526  return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR);
1527  case Intrinsic::mips_dpsu_h_qbl:
1528  return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL);
1529  case Intrinsic::mips_dpsu_h_qbr:
1530  return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR);
1531  case Intrinsic::mips_dpa_w_ph:
1532  return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH);
1533  case Intrinsic::mips_dps_w_ph:
1534  return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH);
1535  case Intrinsic::mips_dpax_w_ph:
1536  return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH);
1537  case Intrinsic::mips_dpsx_w_ph:
1538  return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH);
1539  case Intrinsic::mips_mulsa_w_ph:
1540  return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH);
1541  case Intrinsic::mips_mult:
1542  return lowerDSPIntr(Op, DAG, MipsISD::Mult);
1543  case Intrinsic::mips_multu:
1544  return lowerDSPIntr(Op, DAG, MipsISD::Multu);
1545  case Intrinsic::mips_madd:
1546  return lowerDSPIntr(Op, DAG, MipsISD::MAdd);
1547  case Intrinsic::mips_maddu:
1548  return lowerDSPIntr(Op, DAG, MipsISD::MAddu);
1549  case Intrinsic::mips_msub:
1550  return lowerDSPIntr(Op, DAG, MipsISD::MSub);
1551  case Intrinsic::mips_msubu:
1552  return lowerDSPIntr(Op, DAG, MipsISD::MSubu);
1553  case Intrinsic::mips_addv_b:
1554  case Intrinsic::mips_addv_h:
1555  case Intrinsic::mips_addv_w:
1556  case Intrinsic::mips_addv_d:
1557  return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1558  Op->getOperand(2));
1559  case Intrinsic::mips_addvi_b:
1560  case Intrinsic::mips_addvi_h:
1561  case Intrinsic::mips_addvi_w:
1562  case Intrinsic::mips_addvi_d:
1563  return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1564  lowerMSASplatImm(Op, 2, DAG));
1565  case Intrinsic::mips_and_v:
1566  return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1567  Op->getOperand(2));
1568  case Intrinsic::mips_andi_b:
1569  return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1570  lowerMSASplatImm(Op, 2, DAG));
1571  case Intrinsic::mips_bclr_b:
1572  case Intrinsic::mips_bclr_h:
1573  case Intrinsic::mips_bclr_w:
1574  case Intrinsic::mips_bclr_d:
1575  return lowerMSABitClear(Op, DAG);
1576  case Intrinsic::mips_bclri_b:
1577  case Intrinsic::mips_bclri_h:
1578  case Intrinsic::mips_bclri_w:
1579  case Intrinsic::mips_bclri_d:
1580  return lowerMSABitClearImm(Op, DAG);
1581  case Intrinsic::mips_binsli_b:
1582  case Intrinsic::mips_binsli_h:
1583  case Intrinsic::mips_binsli_w:
1584  case Intrinsic::mips_binsli_d: {
1585  // binsli_x(IfClear, IfSet, nbits) -> (vselect LBitsMask, IfSet, IfClear)
1586  EVT VecTy = Op->getValueType(0);
1587  EVT EltTy = VecTy.getVectorElementType();
1588  APInt Mask = APInt::getHighBitsSet(EltTy.getSizeInBits(),
1589  Op->getConstantOperandVal(3));
1590  return DAG.getNode(ISD::VSELECT, DL, VecTy,
1591  DAG.getConstant(Mask, DL, VecTy, true),
1592  Op->getOperand(2), Op->getOperand(1));
1593  }
1594  case Intrinsic::mips_binsri_b:
1595  case Intrinsic::mips_binsri_h:
1596  case Intrinsic::mips_binsri_w:
1597  case Intrinsic::mips_binsri_d: {
1598  // binsri_x(IfClear, IfSet, nbits) -> (vselect RBitsMask, IfSet, IfClear)
1599  EVT VecTy = Op->getValueType(0);
1600  EVT EltTy = VecTy.getVectorElementType();
1601  APInt Mask = APInt::getLowBitsSet(EltTy.getSizeInBits(),
1602  Op->getConstantOperandVal(3));
1603  return DAG.getNode(ISD::VSELECT, DL, VecTy,
1604  DAG.getConstant(Mask, DL, VecTy, true),
1605  Op->getOperand(2), Op->getOperand(1));
1606  }
1607  case Intrinsic::mips_bmnz_v:
1608  return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1609  Op->getOperand(2), Op->getOperand(1));
1610  case Intrinsic::mips_bmnzi_b:
1611  return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1612  lowerMSASplatImm(Op, 3, DAG), Op->getOperand(2),
1613  Op->getOperand(1));
1614  case Intrinsic::mips_bmz_v:
1615  return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1616  Op->getOperand(1), Op->getOperand(2));
1617  case Intrinsic::mips_bmzi_b:
1618  return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1619  lowerMSASplatImm(Op, 3, DAG), Op->getOperand(1),
1620  Op->getOperand(2));
1621  case Intrinsic::mips_bneg_b:
1622  case Intrinsic::mips_bneg_h:
1623  case Intrinsic::mips_bneg_w:
1624  case Intrinsic::mips_bneg_d: {
1625  EVT VecTy = Op->getValueType(0);
1626  SDValue One = DAG.getConstant(1, DL, VecTy);
1627 
1628  return DAG.getNode(ISD::XOR, DL, VecTy, Op->getOperand(1),
1629  DAG.getNode(ISD::SHL, DL, VecTy, One,
1630  Op->getOperand(2)));
1631  }
1632  case Intrinsic::mips_bnegi_b:
1633  case Intrinsic::mips_bnegi_h:
1634  case Intrinsic::mips_bnegi_w:
1635  case Intrinsic::mips_bnegi_d:
1636  return lowerMSABinaryBitImmIntr(Op, DAG, ISD::XOR, Op->getOperand(2),
1637  !Subtarget.isLittle());
1638  case Intrinsic::mips_bnz_b:
1639  case Intrinsic::mips_bnz_h:
1640  case Intrinsic::mips_bnz_w:
1641  case Intrinsic::mips_bnz_d:
1642  return DAG.getNode(MipsISD::VALL_NONZERO, DL, Op->getValueType(0),
1643  Op->getOperand(1));
1644  case Intrinsic::mips_bnz_v:
1645  return DAG.getNode(MipsISD::VANY_NONZERO, DL, Op->getValueType(0),
1646  Op->getOperand(1));
1647  case Intrinsic::mips_bsel_v:
1648  // bsel_v(Mask, IfClear, IfSet) -> (vselect Mask, IfSet, IfClear)
1649  return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1650  Op->getOperand(1), Op->getOperand(3),
1651  Op->getOperand(2));
1652  case Intrinsic::mips_bseli_b:
1653  // bseli_v(Mask, IfClear, IfSet) -> (vselect Mask, IfSet, IfClear)
1654  return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1655  Op->getOperand(1), lowerMSASplatImm(Op, 3, DAG),
1656  Op->getOperand(2));
1657  case Intrinsic::mips_bset_b:
1658  case Intrinsic::mips_bset_h:
1659  case Intrinsic::mips_bset_w:
1660  case Intrinsic::mips_bset_d: {
1661  EVT VecTy = Op->getValueType(0);
1662  SDValue One = DAG.getConstant(1, DL, VecTy);
1663 
1664  return DAG.getNode(ISD::OR, DL, VecTy, Op->getOperand(1),
1665  DAG.getNode(ISD::SHL, DL, VecTy, One,
1666  Op->getOperand(2)));
1667  }
1668  case Intrinsic::mips_bseti_b:
1669  case Intrinsic::mips_bseti_h:
1670  case Intrinsic::mips_bseti_w:
1671  case Intrinsic::mips_bseti_d:
1672  return lowerMSABinaryBitImmIntr(Op, DAG, ISD::OR, Op->getOperand(2),
1673  !Subtarget.isLittle());
1674  case Intrinsic::mips_bz_b:
1675  case Intrinsic::mips_bz_h:
1676  case Intrinsic::mips_bz_w:
1677  case Intrinsic::mips_bz_d:
1678  return DAG.getNode(MipsISD::VALL_ZERO, DL, Op->getValueType(0),
1679  Op->getOperand(1));
1680  case Intrinsic::mips_bz_v:
1681  return DAG.getNode(MipsISD::VANY_ZERO, DL, Op->getValueType(0),
1682  Op->getOperand(1));
1683  case Intrinsic::mips_ceq_b:
1684  case Intrinsic::mips_ceq_h:
1685  case Intrinsic::mips_ceq_w:
1686  case Intrinsic::mips_ceq_d:
1687  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1688  Op->getOperand(2), ISD::SETEQ);
1689  case Intrinsic::mips_ceqi_b:
1690  case Intrinsic::mips_ceqi_h:
1691  case Intrinsic::mips_ceqi_w:
1692  case Intrinsic::mips_ceqi_d:
1693  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1694  lowerMSASplatImm(Op, 2, DAG), ISD::SETEQ);
1695  case Intrinsic::mips_cle_s_b:
1696  case Intrinsic::mips_cle_s_h:
1697  case Intrinsic::mips_cle_s_w:
1698  case Intrinsic::mips_cle_s_d:
1699  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1700  Op->getOperand(2), ISD::SETLE);
1701  case Intrinsic::mips_clei_s_b:
1702  case Intrinsic::mips_clei_s_h:
1703  case Intrinsic::mips_clei_s_w:
1704  case Intrinsic::mips_clei_s_d:
1705  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1706  lowerMSASplatImm(Op, 2, DAG), ISD::SETLE);
1707  case Intrinsic::mips_cle_u_b:
1708  case Intrinsic::mips_cle_u_h:
1709  case Intrinsic::mips_cle_u_w:
1710  case Intrinsic::mips_cle_u_d:
1711  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1712  Op->getOperand(2), ISD::SETULE);
1713  case Intrinsic::mips_clei_u_b:
1714  case Intrinsic::mips_clei_u_h:
1715  case Intrinsic::mips_clei_u_w:
1716  case Intrinsic::mips_clei_u_d:
1717  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1718  lowerMSASplatImm(Op, 2, DAG), ISD::SETULE);
1719  case Intrinsic::mips_clt_s_b:
1720  case Intrinsic::mips_clt_s_h:
1721  case Intrinsic::mips_clt_s_w:
1722  case Intrinsic::mips_clt_s_d:
1723  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1724  Op->getOperand(2), ISD::SETLT);
1725  case Intrinsic::mips_clti_s_b:
1726  case Intrinsic::mips_clti_s_h:
1727  case Intrinsic::mips_clti_s_w:
1728  case Intrinsic::mips_clti_s_d:
1729  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1730  lowerMSASplatImm(Op, 2, DAG), ISD::SETLT);
1731  case Intrinsic::mips_clt_u_b:
1732  case Intrinsic::mips_clt_u_h:
1733  case Intrinsic::mips_clt_u_w:
1734  case Intrinsic::mips_clt_u_d:
1735  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1736  Op->getOperand(2), ISD::SETULT);
1737  case Intrinsic::mips_clti_u_b:
1738  case Intrinsic::mips_clti_u_h:
1739  case Intrinsic::mips_clti_u_w:
1740  case Intrinsic::mips_clti_u_d:
1741  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1742  lowerMSASplatImm(Op, 2, DAG), ISD::SETULT);
1743  case Intrinsic::mips_copy_s_b:
1744  case Intrinsic::mips_copy_s_h:
1745  case Intrinsic::mips_copy_s_w:
1747  case Intrinsic::mips_copy_s_d:
1748  if (Subtarget.hasMips64())
1749  // Lower directly into VEXTRACT_SEXT_ELT since i64 is legal on Mips64.
1751  else {
1752  // Lower into the generic EXTRACT_VECTOR_ELT node and let the type
1753  // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1754  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
1755  Op->getValueType(0), Op->getOperand(1),
1756  Op->getOperand(2));
1757  }
1758  case Intrinsic::mips_copy_u_b:
1759  case Intrinsic::mips_copy_u_h:
1760  case Intrinsic::mips_copy_u_w:
1762  case Intrinsic::mips_copy_u_d:
1763  if (Subtarget.hasMips64())
1764  // Lower directly into VEXTRACT_ZEXT_ELT since i64 is legal on Mips64.
1766  else {
1767  // Lower into the generic EXTRACT_VECTOR_ELT node and let the type
1768  // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1769  // Note: When i64 is illegal, this results in copy_s.w instructions
1770  // instead of copy_u.w instructions. This makes no difference to the
1771  // behaviour since i64 is only illegal when the register file is 32-bit.
1772  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
1773  Op->getValueType(0), Op->getOperand(1),
1774  Op->getOperand(2));
1775  }
1776  case Intrinsic::mips_div_s_b:
1777  case Intrinsic::mips_div_s_h:
1778  case Intrinsic::mips_div_s_w:
1779  case Intrinsic::mips_div_s_d:
1780  return DAG.getNode(ISD::SDIV, DL, Op->getValueType(0), Op->getOperand(1),
1781  Op->getOperand(2));
1782  case Intrinsic::mips_div_u_b:
1783  case Intrinsic::mips_div_u_h:
1784  case Intrinsic::mips_div_u_w:
1785  case Intrinsic::mips_div_u_d:
1786  return DAG.getNode(ISD::UDIV, DL, Op->getValueType(0), Op->getOperand(1),
1787  Op->getOperand(2));
1788  case Intrinsic::mips_fadd_w:
1789  case Intrinsic::mips_fadd_d:
1790  return DAG.getNode(ISD::FADD, DL, Op->getValueType(0), Op->getOperand(1),
1791  Op->getOperand(2));
1792  // Don't lower mips_fcaf_[wd] since LLVM folds SETFALSE condcodes away
1793  case Intrinsic::mips_fceq_w:
1794  case Intrinsic::mips_fceq_d:
1795  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1796  Op->getOperand(2), ISD::SETOEQ);
1797  case Intrinsic::mips_fcle_w:
1798  case Intrinsic::mips_fcle_d:
1799  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1800  Op->getOperand(2), ISD::SETOLE);
1801  case Intrinsic::mips_fclt_w:
1802  case Intrinsic::mips_fclt_d:
1803  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1804  Op->getOperand(2), ISD::SETOLT);
1805  case Intrinsic::mips_fcne_w:
1806  case Intrinsic::mips_fcne_d:
1807  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1808  Op->getOperand(2), ISD::SETONE);
1809  case Intrinsic::mips_fcor_w:
1810  case Intrinsic::mips_fcor_d:
1811  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1812  Op->getOperand(2), ISD::SETO);
1813  case Intrinsic::mips_fcueq_w:
1814  case Intrinsic::mips_fcueq_d:
1815  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1816  Op->getOperand(2), ISD::SETUEQ);
1817  case Intrinsic::mips_fcule_w:
1818  case Intrinsic::mips_fcule_d:
1819  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1820  Op->getOperand(2), ISD::SETULE);
1821  case Intrinsic::mips_fcult_w:
1822  case Intrinsic::mips_fcult_d:
1823  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1824  Op->getOperand(2), ISD::SETULT);
1825  case Intrinsic::mips_fcun_w:
1826  case Intrinsic::mips_fcun_d:
1827  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1828  Op->getOperand(2), ISD::SETUO);
1829  case Intrinsic::mips_fcune_w:
1830  case Intrinsic::mips_fcune_d:
1831  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1832  Op->getOperand(2), ISD::SETUNE);
1833  case Intrinsic::mips_fdiv_w:
1834  case Intrinsic::mips_fdiv_d:
1835  return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1),
1836  Op->getOperand(2));
1837  case Intrinsic::mips_ffint_u_w:
1838  case Intrinsic::mips_ffint_u_d:
1839  return DAG.getNode(ISD::UINT_TO_FP, DL, Op->getValueType(0),
1840  Op->getOperand(1));
1841  case Intrinsic::mips_ffint_s_w:
1842  case Intrinsic::mips_ffint_s_d:
1843  return DAG.getNode(ISD::SINT_TO_FP, DL, Op->getValueType(0),
1844  Op->getOperand(1));
1845  case Intrinsic::mips_fill_b:
1846  case Intrinsic::mips_fill_h:
1847  case Intrinsic::mips_fill_w:
1848  case Intrinsic::mips_fill_d: {
1849  EVT ResTy = Op->getValueType(0);
1851  Op->getOperand(1));
1852 
1853  // If ResTy is v2i64 then the type legalizer will break this node down into
1854  // an equivalent v4i32.
1855  return DAG.getNode(ISD::BUILD_VECTOR, DL, ResTy, Ops);
1856  }
1857  case Intrinsic::mips_fexp2_w:
1858  case Intrinsic::mips_fexp2_d: {
1859  EVT ResTy = Op->getValueType(0);
1860  return DAG.getNode(
1861  ISD::FMUL, SDLoc(Op), ResTy, Op->getOperand(1),
1862  DAG.getNode(ISD::FEXP2, SDLoc(Op), ResTy, Op->getOperand(2)));
1863  }
1864  case Intrinsic::mips_flog2_w:
1865  case Intrinsic::mips_flog2_d:
1866  return DAG.getNode(ISD::FLOG2, DL, Op->getValueType(0), Op->getOperand(1));
1867  case Intrinsic::mips_fmadd_w:
1868  case Intrinsic::mips_fmadd_d:
1869  return DAG.getNode(ISD::FMA, SDLoc(Op), Op->getValueType(0),
1870  Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
1871  case Intrinsic::mips_fmul_w:
1872  case Intrinsic::mips_fmul_d:
1873  return DAG.getNode(ISD::FMUL, DL, Op->getValueType(0), Op->getOperand(1),
1874  Op->getOperand(2));
1875  case Intrinsic::mips_fmsub_w:
1876  case Intrinsic::mips_fmsub_d: {
1877  EVT ResTy = Op->getValueType(0);
1878  return DAG.getNode(ISD::FSUB, SDLoc(Op), ResTy, Op->getOperand(1),
1879  DAG.getNode(ISD::FMUL, SDLoc(Op), ResTy,
1880  Op->getOperand(2), Op->getOperand(3)));
1881  }
1882  case Intrinsic::mips_frint_w:
1883  case Intrinsic::mips_frint_d:
1884  return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1));
1885  case Intrinsic::mips_fsqrt_w:
1886  case Intrinsic::mips_fsqrt_d:
1887  return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1));
1888  case Intrinsic::mips_fsub_w:
1889  case Intrinsic::mips_fsub_d:
1890  return DAG.getNode(ISD::FSUB, DL, Op->getValueType(0), Op->getOperand(1),
1891  Op->getOperand(2));
1892  case Intrinsic::mips_ftrunc_u_w:
1893  case Intrinsic::mips_ftrunc_u_d:
1894  return DAG.getNode(ISD::FP_TO_UINT, DL, Op->getValueType(0),
1895  Op->getOperand(1));
1896  case Intrinsic::mips_ftrunc_s_w:
1897  case Intrinsic::mips_ftrunc_s_d:
1898  return DAG.getNode(ISD::FP_TO_SINT, DL, Op->getValueType(0),
1899  Op->getOperand(1));
1900  case Intrinsic::mips_ilvev_b:
1901  case Intrinsic::mips_ilvev_h:
1902  case Intrinsic::mips_ilvev_w:
1903  case Intrinsic::mips_ilvev_d:
1904  return DAG.getNode(MipsISD::ILVEV, DL, Op->getValueType(0),
1905  Op->getOperand(1), Op->getOperand(2));
1906  case Intrinsic::mips_ilvl_b:
1907  case Intrinsic::mips_ilvl_h:
1908  case Intrinsic::mips_ilvl_w:
1909  case Intrinsic::mips_ilvl_d:
1910  return DAG.getNode(MipsISD::ILVL, DL, Op->getValueType(0),
1911  Op->getOperand(1), Op->getOperand(2));
1912  case Intrinsic::mips_ilvod_b:
1913  case Intrinsic::mips_ilvod_h:
1914  case Intrinsic::mips_ilvod_w:
1915  case Intrinsic::mips_ilvod_d:
1916  return DAG.getNode(MipsISD::ILVOD, DL, Op->getValueType(0),
1917  Op->getOperand(1), Op->getOperand(2));
1918  case Intrinsic::mips_ilvr_b:
1919  case Intrinsic::mips_ilvr_h:
1920  case Intrinsic::mips_ilvr_w:
1921  case Intrinsic::mips_ilvr_d:
1922  return DAG.getNode(MipsISD::ILVR, DL, Op->getValueType(0),
1923  Op->getOperand(1), Op->getOperand(2));
1924  case Intrinsic::mips_insert_b:
1925  case Intrinsic::mips_insert_h:
1926  case Intrinsic::mips_insert_w:
1927  case Intrinsic::mips_insert_d:
1928  return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
1929  Op->getOperand(1), Op->getOperand(3), Op->getOperand(2));
1930  case Intrinsic::mips_insve_b:
1931  case Intrinsic::mips_insve_h:
1932  case Intrinsic::mips_insve_w:
1933  case Intrinsic::mips_insve_d:
1934  return DAG.getNode(MipsISD::INSVE, DL, Op->getValueType(0),
1935  Op->getOperand(1), Op->getOperand(2), Op->getOperand(3),
1936  DAG.getConstant(0, DL, MVT::i32));
1937  case Intrinsic::mips_ldi_b:
1938  case Intrinsic::mips_ldi_h:
1939  case Intrinsic::mips_ldi_w:
1940  case Intrinsic::mips_ldi_d:
1941  return lowerMSASplatImm(Op, 1, DAG);
1942  case Intrinsic::mips_lsa:
1943  case Intrinsic::mips_dlsa: {
1944  EVT ResTy = Op->getValueType(0);
1945  return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
1946  DAG.getNode(ISD::SHL, SDLoc(Op), ResTy,
1947  Op->getOperand(2), Op->getOperand(3)));
1948  }
1949  case Intrinsic::mips_maddv_b:
1950  case Intrinsic::mips_maddv_h:
1951  case Intrinsic::mips_maddv_w:
1952  case Intrinsic::mips_maddv_d: {
1953  EVT ResTy = Op->getValueType(0);
1954  return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
1955  DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
1956  Op->getOperand(2), Op->getOperand(3)));
1957  }
1958  case Intrinsic::mips_max_s_b:
1959  case Intrinsic::mips_max_s_h:
1960  case Intrinsic::mips_max_s_w:
1961  case Intrinsic::mips_max_s_d:
1962  return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0),
1963  Op->getOperand(1), Op->getOperand(2));
1964  case Intrinsic::mips_max_u_b:
1965  case Intrinsic::mips_max_u_h:
1966  case Intrinsic::mips_max_u_w:
1967  case Intrinsic::mips_max_u_d:
1968  return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0),
1969  Op->getOperand(1), Op->getOperand(2));
1970  case Intrinsic::mips_maxi_s_b:
1971  case Intrinsic::mips_maxi_s_h:
1972  case Intrinsic::mips_maxi_s_w:
1973  case Intrinsic::mips_maxi_s_d:
1974  return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0),
1975  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1976  case Intrinsic::mips_maxi_u_b:
1977  case Intrinsic::mips_maxi_u_h:
1978  case Intrinsic::mips_maxi_u_w:
1979  case Intrinsic::mips_maxi_u_d:
1980  return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0),
1981  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1982  case Intrinsic::mips_min_s_b:
1983  case Intrinsic::mips_min_s_h:
1984  case Intrinsic::mips_min_s_w:
1985  case Intrinsic::mips_min_s_d:
1986  return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0),
1987  Op->getOperand(1), Op->getOperand(2));
1988  case Intrinsic::mips_min_u_b:
1989  case Intrinsic::mips_min_u_h:
1990  case Intrinsic::mips_min_u_w:
1991  case Intrinsic::mips_min_u_d:
1992  return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0),
1993  Op->getOperand(1), Op->getOperand(2));
1994  case Intrinsic::mips_mini_s_b:
1995  case Intrinsic::mips_mini_s_h:
1996  case Intrinsic::mips_mini_s_w:
1997  case Intrinsic::mips_mini_s_d:
1998  return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0),
1999  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2000  case Intrinsic::mips_mini_u_b:
2001  case Intrinsic::mips_mini_u_h:
2002  case Intrinsic::mips_mini_u_w:
2003  case Intrinsic::mips_mini_u_d:
2004  return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0),
2005  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2006  case Intrinsic::mips_mod_s_b:
2007  case Intrinsic::mips_mod_s_h:
2008  case Intrinsic::mips_mod_s_w:
2009  case Intrinsic::mips_mod_s_d:
2010  return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1),
2011  Op->getOperand(2));
2012  case Intrinsic::mips_mod_u_b:
2013  case Intrinsic::mips_mod_u_h:
2014  case Intrinsic::mips_mod_u_w:
2015  case Intrinsic::mips_mod_u_d:
2016  return DAG.getNode(ISD::UREM, DL, Op->getValueType(0), Op->getOperand(1),
2017  Op->getOperand(2));
2018  case Intrinsic::mips_mulv_b:
2019  case Intrinsic::mips_mulv_h:
2020  case Intrinsic::mips_mulv_w:
2021  case Intrinsic::mips_mulv_d:
2022  return DAG.getNode(ISD::MUL, DL, Op->getValueType(0), Op->getOperand(1),
2023  Op->getOperand(2));
2024  case Intrinsic::mips_msubv_b:
2025  case Intrinsic::mips_msubv_h:
2026  case Intrinsic::mips_msubv_w:
2027  case Intrinsic::mips_msubv_d: {
2028  EVT ResTy = Op->getValueType(0);
2029  return DAG.getNode(ISD::SUB, SDLoc(Op), ResTy, Op->getOperand(1),
2030  DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
2031  Op->getOperand(2), Op->getOperand(3)));
2032  }
2033  case Intrinsic::mips_nlzc_b:
2034  case Intrinsic::mips_nlzc_h:
2035  case Intrinsic::mips_nlzc_w:
2036  case Intrinsic::mips_nlzc_d:
2037  return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1));
2038  case Intrinsic::mips_nor_v: {
2039  SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
2040  Op->getOperand(1), Op->getOperand(2));
2041  return DAG.getNOT(DL, Res, Res->getValueType(0));
2042  }
2043  case Intrinsic::mips_nori_b: {
2044  SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
2045  Op->getOperand(1),
2046  lowerMSASplatImm(Op, 2, DAG));
2047  return DAG.getNOT(DL, Res, Res->getValueType(0));
2048  }
2049  case Intrinsic::mips_or_v:
2050  return DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1),
2051  Op->getOperand(2));
2052  case Intrinsic::mips_ori_b:
2053  return DAG.getNode(ISD::OR, DL, Op->getValueType(0),
2054  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2055  case Intrinsic::mips_pckev_b:
2056  case Intrinsic::mips_pckev_h:
2057  case Intrinsic::mips_pckev_w:
2058  case Intrinsic::mips_pckev_d:
2059  return DAG.getNode(MipsISD::PCKEV, DL, Op->getValueType(0),
2060  Op->getOperand(1), Op->getOperand(2));
2061  case Intrinsic::mips_pckod_b:
2062  case Intrinsic::mips_pckod_h:
2063  case Intrinsic::mips_pckod_w:
2064  case Intrinsic::mips_pckod_d:
2065  return DAG.getNode(MipsISD::PCKOD, DL, Op->getValueType(0),
2066  Op->getOperand(1), Op->getOperand(2));
2067  case Intrinsic::mips_pcnt_b:
2068  case Intrinsic::mips_pcnt_h:
2069  case Intrinsic::mips_pcnt_w:
2070  case Intrinsic::mips_pcnt_d:
2071  return DAG.getNode(ISD::CTPOP, DL, Op->getValueType(0), Op->getOperand(1));
2072  case Intrinsic::mips_shf_b:
2073  case Intrinsic::mips_shf_h:
2074  case Intrinsic::mips_shf_w:
2075  return DAG.getNode(MipsISD::SHF, DL, Op->getValueType(0),
2076  Op->getOperand(2), Op->getOperand(1));
2077  case Intrinsic::mips_sll_b:
2078  case Intrinsic::mips_sll_h:
2079  case Intrinsic::mips_sll_w:
2080  case Intrinsic::mips_sll_d:
2081  return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1),
2082  Op->getOperand(2));
2083  case Intrinsic::mips_slli_b:
2084  case Intrinsic::mips_slli_h:
2085  case Intrinsic::mips_slli_w:
2086  case Intrinsic::mips_slli_d:
2087  return DAG.getNode(ISD::SHL, DL, Op->getValueType(0),
2088  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2089  case Intrinsic::mips_splat_b:
2090  case Intrinsic::mips_splat_h:
2091  case Intrinsic::mips_splat_w:
2092  case Intrinsic::mips_splat_d:
2093  // We can't lower via VECTOR_SHUFFLE because it requires constant shuffle
2094  // masks, nor can we lower via BUILD_VECTOR & EXTRACT_VECTOR_ELT because
2095  // EXTRACT_VECTOR_ELT can't extract i64's on MIPS32.
2096  // Instead we lower to MipsISD::VSHF and match from there.
2097  return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
2098  lowerMSASplatZExt(Op, 2, DAG), Op->getOperand(1),
2099  Op->getOperand(1));
2100  case Intrinsic::mips_splati_b:
2101  case Intrinsic::mips_splati_h:
2102  case Intrinsic::mips_splati_w:
2103  case Intrinsic::mips_splati_d:
2104  return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
2105  lowerMSASplatImm(Op, 2, DAG), Op->getOperand(1),
2106  Op->getOperand(1));
2107  case Intrinsic::mips_sra_b:
2108  case Intrinsic::mips_sra_h:
2109  case Intrinsic::mips_sra_w:
2110  case Intrinsic::mips_sra_d:
2111  return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1),
2112  Op->getOperand(2));
2113  case Intrinsic::mips_srai_b:
2114  case Intrinsic::mips_srai_h:
2115  case Intrinsic::mips_srai_w:
2116  case Intrinsic::mips_srai_d:
2117  return DAG.getNode(ISD::SRA, DL, Op->getValueType(0),
2118  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2119  case Intrinsic::mips_srl_b:
2120  case Intrinsic::mips_srl_h:
2121  case Intrinsic::mips_srl_w:
2122  case Intrinsic::mips_srl_d:
2123  return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), Op->getOperand(1),
2124  Op->getOperand(2));
2125  case Intrinsic::mips_srli_b:
2126  case Intrinsic::mips_srli_h:
2127  case Intrinsic::mips_srli_w:
2128  case Intrinsic::mips_srli_d:
2129  return DAG.getNode(ISD::SRL, DL, Op->getValueType(0),
2130  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2131  case Intrinsic::mips_subv_b:
2132  case Intrinsic::mips_subv_h:
2133  case Intrinsic::mips_subv_w:
2134  case Intrinsic::mips_subv_d:
2135  return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), Op->getOperand(1),
2136  Op->getOperand(2));
2137  case Intrinsic::mips_subvi_b:
2138  case Intrinsic::mips_subvi_h:
2139  case Intrinsic::mips_subvi_w:
2140  case Intrinsic::mips_subvi_d:
2141  return DAG.getNode(ISD::SUB, DL, Op->getValueType(0),
2142  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2143  case Intrinsic::mips_vshf_b:
2144  case Intrinsic::mips_vshf_h:
2145  case Intrinsic::mips_vshf_w:
2146  case Intrinsic::mips_vshf_d:
2147  return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
2148  Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
2149  case Intrinsic::mips_xor_v:
2150  return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), Op->getOperand(1),
2151  Op->getOperand(2));
2152  case Intrinsic::mips_xori_b:
2153  return DAG.getNode(ISD::XOR, DL, Op->getValueType(0),
2154  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2155  }
2156 }
2157 
2158 static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
2159  SDLoc DL(Op);
2160  SDValue ChainIn = Op->getOperand(0);
2161  SDValue Address = Op->getOperand(2);
2162  SDValue Offset = Op->getOperand(3);
2163  EVT ResTy = Op->getValueType(0);
2164  EVT PtrTy = Address->getValueType(0);
2165 
2166  Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
2167 
2168  return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(), false,
2169  false, false, 16);
2170 }
2171 
2172 SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
2173  SelectionDAG &DAG) const {
2174  unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
2175  switch (Intr) {
2176  default:
2177  return SDValue();
2178  case Intrinsic::mips_extp:
2179  return lowerDSPIntr(Op, DAG, MipsISD::EXTP);
2180  case Intrinsic::mips_extpdp:
2181  return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP);
2182  case Intrinsic::mips_extr_w:
2183  return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W);
2184  case Intrinsic::mips_extr_r_w:
2185  return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W);
2186  case Intrinsic::mips_extr_rs_w:
2187  return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W);
2188  case Intrinsic::mips_extr_s_h:
2189  return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H);
2190  case Intrinsic::mips_mthlip:
2191  return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP);
2192  case Intrinsic::mips_mulsaq_s_w_ph:
2193  return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH);
2194  case Intrinsic::mips_maq_s_w_phl:
2195  return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL);
2196  case Intrinsic::mips_maq_s_w_phr:
2197  return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR);
2198  case Intrinsic::mips_maq_sa_w_phl:
2199  return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL);
2200  case Intrinsic::mips_maq_sa_w_phr:
2201  return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR);
2202  case Intrinsic::mips_dpaq_s_w_ph:
2203  return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH);
2204  case Intrinsic::mips_dpsq_s_w_ph:
2205  return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH);
2206  case Intrinsic::mips_dpaq_sa_l_w:
2207  return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W);
2208  case Intrinsic::mips_dpsq_sa_l_w:
2209  return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W);
2210  case Intrinsic::mips_dpaqx_s_w_ph:
2211  return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH);
2212  case Intrinsic::mips_dpaqx_sa_w_ph:
2213  return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH);
2214  case Intrinsic::mips_dpsqx_s_w_ph:
2215  return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH);
2216  case Intrinsic::mips_dpsqx_sa_w_ph:
2217  return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH);
2218  case Intrinsic::mips_ld_b:
2219  case Intrinsic::mips_ld_h:
2220  case Intrinsic::mips_ld_w:
2221  case Intrinsic::mips_ld_d:
2222  return lowerMSALoadIntr(Op, DAG, Intr);
2223  }
2224 }
2225 
2226 static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
2227  SDLoc DL(Op);
2228  SDValue ChainIn = Op->getOperand(0);
2229  SDValue Value = Op->getOperand(2);
2230  SDValue Address = Op->getOperand(3);
2231  SDValue Offset = Op->getOperand(4);
2232  EVT PtrTy = Address->getValueType(0);
2233 
2234  Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
2235 
2236  return DAG.getStore(ChainIn, DL, Value, Address, MachinePointerInfo(), false,
2237  false, 16);
2238 }
2239 
2240 SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op,
2241  SelectionDAG &DAG) const {
2242  unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
2243  switch (Intr) {
2244  default:
2245  return SDValue();
2246  case Intrinsic::mips_st_b:
2247  case Intrinsic::mips_st_h:
2248  case Intrinsic::mips_st_w:
2249  case Intrinsic::mips_st_d:
2250  return lowerMSAStoreIntr(Op, DAG, Intr);
2251  }
2252 }
2253 
2254 /// \brief Check if the given BuildVectorSDNode is a splat.
2255 /// This method currently relies on DAG nodes being reused when equivalent,
2256 /// so it's possible for this to return false even when isConstantSplat returns
2257 /// true.
2258 static bool isSplatVector(const BuildVectorSDNode *N) {
2259  unsigned int nOps = N->getNumOperands();
2260  assert(nOps > 1 && "isSplatVector has 0 or 1 sized build vector");
2261 
2262  SDValue Operand0 = N->getOperand(0);
2263 
2264  for (unsigned int i = 1; i < nOps; ++i) {
2265  if (N->getOperand(i) != Operand0)
2266  return false;
2267  }
2268 
2269  return true;
2270 }
2271 
2272 // Lower ISD::EXTRACT_VECTOR_ELT into MipsISD::VEXTRACT_SEXT_ELT.
2273 //
2274 // The non-value bits resulting from ISD::EXTRACT_VECTOR_ELT are undefined. We
2275 // choose to sign-extend but we could have equally chosen zero-extend. The
2276 // DAGCombiner will fold any sign/zero extension of the ISD::EXTRACT_VECTOR_ELT
2277 // result into this node later (possibly changing it to a zero-extend in the
2278 // process).
2279 SDValue MipsSETargetLowering::
2280 lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
2281  SDLoc DL(Op);
2282  EVT ResTy = Op->getValueType(0);
2283  SDValue Op0 = Op->getOperand(0);
2284  EVT VecTy = Op0->getValueType(0);
2285 
2286  if (!VecTy.is128BitVector())
2287  return SDValue();
2288 
2289  if (ResTy.isInteger()) {
2290  SDValue Op1 = Op->getOperand(1);
2291  EVT EltTy = VecTy.getVectorElementType();
2292  return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, DL, ResTy, Op0, Op1,
2293  DAG.getValueType(EltTy));
2294  }
2295 
2296  return Op;
2297 }
2298 
2299 static bool isConstantOrUndef(const SDValue Op) {
2300  if (Op->getOpcode() == ISD::UNDEF)
2301  return true;
2302  if (isa<ConstantSDNode>(Op))
2303  return true;
2304  if (isa<ConstantFPSDNode>(Op))
2305  return true;
2306  return false;
2307 }
2308 
2310  for (unsigned i = 0; i < Op->getNumOperands(); ++i)
2311  if (isConstantOrUndef(Op->getOperand(i)))
2312  return true;
2313  return false;
2314 }
2315 
2316 // Lowers ISD::BUILD_VECTOR into appropriate SelectionDAG nodes for the
2317 // backend.
2318 //
2319 // Lowers according to the following rules:
2320 // - Constant splats are legal as-is as long as the SplatBitSize is a power of
2321 // 2 less than or equal to 64 and the value fits into a signed 10-bit
2322 // immediate
2323 // - Constant splats are lowered to bitconverted BUILD_VECTORs if SplatBitSize
2324 // is a power of 2 less than or equal to 64 and the value does not fit into a
2325 // signed 10-bit immediate
2326 // - Non-constant splats are legal as-is.
2327 // - Non-constant non-splats are lowered to sequences of INSERT_VECTOR_ELT.
2328 // - All others are illegal and must be expanded.
2329 SDValue MipsSETargetLowering::lowerBUILD_VECTOR(SDValue Op,
2330  SelectionDAG &DAG) const {
2331  BuildVectorSDNode *Node = cast<BuildVectorSDNode>(Op);
2332  EVT ResTy = Op->getValueType(0);
2333  SDLoc DL(Op);
2334  APInt SplatValue, SplatUndef;
2335  unsigned SplatBitSize;
2336  bool HasAnyUndefs;
2337 
2338  if (!Subtarget.hasMSA() || !ResTy.is128BitVector())
2339  return SDValue();
2340 
2341  if (Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
2342  HasAnyUndefs, 8,
2343  !Subtarget.isLittle()) && SplatBitSize <= 64) {
2344  // We can only cope with 8, 16, 32, or 64-bit elements
2345  if (SplatBitSize != 8 && SplatBitSize != 16 && SplatBitSize != 32 &&
2346  SplatBitSize != 64)
2347  return SDValue();
2348 
2349  // If the value fits into a simm10 then we can use ldi.[bhwd]
2350  // However, if it isn't an integer type we will have to bitcast from an
2351  // integer type first. Also, if there are any undefs, we must lower them
2352  // to defined values first.
2353  if (ResTy.isInteger() && !HasAnyUndefs && SplatValue.isSignedIntN(10))
2354  return Op;
2355 
2356  EVT ViaVecTy;
2357 
2358  switch (SplatBitSize) {
2359  default:
2360  return SDValue();
2361  case 8:
2362  ViaVecTy = MVT::v16i8;
2363  break;
2364  case 16:
2365  ViaVecTy = MVT::v8i16;
2366  break;
2367  case 32:
2368  ViaVecTy = MVT::v4i32;
2369  break;
2370  case 64:
2371  // There's no fill.d to fall back on for 64-bit values
2372  return SDValue();
2373  }
2374 
2375  // SelectionDAG::getConstant will promote SplatValue appropriately.
2376  SDValue Result = DAG.getConstant(SplatValue, DL, ViaVecTy);
2377 
2378  // Bitcast to the type we originally wanted
2379  if (ViaVecTy != ResTy)
2380  Result = DAG.getNode(ISD::BITCAST, SDLoc(Node), ResTy, Result);
2381 
2382  return Result;
2383  } else if (isSplatVector(Node))
2384  return Op;
2385  else if (!isConstantOrUndefBUILD_VECTOR(Node)) {
2386  // Use INSERT_VECTOR_ELT operations rather than expand to stores.
2387  // The resulting code is the same length as the expansion, but it doesn't
2388  // use memory operations
2389  EVT ResTy = Node->getValueType(0);
2390 
2391  assert(ResTy.isVector());
2392 
2393  unsigned NumElts = ResTy.getVectorNumElements();
2394  SDValue Vector = DAG.getUNDEF(ResTy);
2395  for (unsigned i = 0; i < NumElts; ++i) {
2396  Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector,
2397  Node->getOperand(i),
2398  DAG.getConstant(i, DL, MVT::i32));
2399  }
2400  return Vector;
2401  }
2402 
2403  return SDValue();
2404 }
2405 
2406 // Lower VECTOR_SHUFFLE into SHF (if possible).
2407 //
2408 // SHF splits the vector into blocks of four elements, then shuffles these
2409 // elements according to a <4 x i2> constant (encoded as an integer immediate).
2410 //
2411 // It is therefore possible to lower into SHF when the mask takes the form:
2412 // <a, b, c, d, a+4, b+4, c+4, d+4, a+8, b+8, c+8, d+8, ...>
2413 // When undef's appear they are treated as if they were whatever value is
2414 // necessary in order to fit the above forms.
2415 //
2416 // For example:
2417 // %2 = shufflevector <8 x i16> %0, <8 x i16> undef,
2418 // <8 x i32> <i32 3, i32 2, i32 1, i32 0,
2419 // i32 7, i32 6, i32 5, i32 4>
2420 // is lowered to:
2421 // (SHF_H $w0, $w1, 27)
2422 // where the 27 comes from:
2423 // 3 + (2 << 2) + (1 << 4) + (0 << 6)
2425  SmallVector<int, 16> Indices,
2426  SelectionDAG &DAG) {
2427  int SHFIndices[4] = { -1, -1, -1, -1 };
2428 
2429  if (Indices.size() < 4)
2430  return SDValue();
2431 
2432  for (unsigned i = 0; i < 4; ++i) {
2433  for (unsigned j = i; j < Indices.size(); j += 4) {
2434  int Idx = Indices[j];
2435 
2436  // Convert from vector index to 4-element subvector index
2437  // If an index refers to an element outside of the subvector then give up
2438  if (Idx != -1) {
2439  Idx -= 4 * (j / 4);
2440  if (Idx < 0 || Idx >= 4)
2441  return SDValue();
2442  }
2443 
2444  // If the mask has an undef, replace it with the current index.
2445  // Note that it might still be undef if the current index is also undef
2446  if (SHFIndices[i] == -1)
2447  SHFIndices[i] = Idx;
2448 
2449  // Check that non-undef values are the same as in the mask. If they
2450  // aren't then give up
2451  if (!(Idx == -1 || Idx == SHFIndices[i]))
2452  return SDValue();
2453  }
2454  }
2455 
2456  // Calculate the immediate. Replace any remaining undefs with zero
2457  APInt Imm(32, 0);
2458  for (int i = 3; i >= 0; --i) {
2459  int Idx = SHFIndices[i];
2460 
2461  if (Idx == -1)
2462  Idx = 0;
2463 
2464  Imm <<= 2;
2465  Imm |= Idx & 0x3;
2466  }
2467 
2468  SDLoc DL(Op);
2469  return DAG.getNode(MipsISD::SHF, DL, ResTy,
2470  DAG.getConstant(Imm, DL, MVT::i32), Op->getOperand(0));
2471 }
2472 
2473 /// Determine whether a range fits a regular pattern of values.
2474 /// This function accounts for the possibility of jumping over the End iterator.
2475 template <typename ValType>
2476 static bool
2478  unsigned CheckStride,
2480  ValType ExpectedIndex, unsigned ExpectedIndexStride) {
2481  auto &I = Begin;
2482 
2483  while (I != End) {
2484  if (*I != -1 && *I != ExpectedIndex)
2485  return false;
2486  ExpectedIndex += ExpectedIndexStride;
2487 
2488  // Incrementing past End is undefined behaviour so we must increment one
2489  // step at a time and check for End at each step.
2490  for (unsigned n = 0; n < CheckStride && I != End; ++n, ++I)
2491  ; // Empty loop body.
2492  }
2493  return true;
2494 }
2495 
2496 // Determine whether VECTOR_SHUFFLE is a SPLATI.
2497 //
2498 // It is a SPLATI when the mask is:
2499 // <x, x, x, ...>
2500 // where x is any valid index.
2501 //
2502 // When undef's appear in the mask they are treated as if they were whatever
2503 // value is necessary in order to fit the above form.
2504 static bool isVECTOR_SHUFFLE_SPLATI(SDValue Op, EVT ResTy,
2505  SmallVector<int, 16> Indices,
2506  SelectionDAG &DAG) {
2507  assert((Indices.size() % 2) == 0);
2508 
2509  int SplatIndex = -1;
2510  for (const auto &V : Indices) {
2511  if (V != -1) {
2512  SplatIndex = V;
2513  break;
2514  }
2515  }
2516 
2517  return fitsRegularPattern<int>(Indices.begin(), 1, Indices.end(), SplatIndex,
2518  0);
2519 }
2520 
2521 // Lower VECTOR_SHUFFLE into ILVEV (if possible).
2522 //
2523 // ILVEV interleaves the even elements from each vector.
2524 //
2525 // It is possible to lower into ILVEV when the mask consists of two of the
2526 // following forms interleaved:
2527 // <0, 2, 4, ...>
2528 // <n, n+2, n+4, ...>
2529 // where n is the number of elements in the vector.
2530 // For example:
2531 // <0, 0, 2, 2, 4, 4, ...>
2532 // <0, n, 2, n+2, 4, n+4, ...>
2533 //
2534 // When undef's appear in the mask they are treated as if they were whatever
2535 // value is necessary in order to fit the above forms.
2537  SmallVector<int, 16> Indices,
2538  SelectionDAG &DAG) {
2539  assert((Indices.size() % 2) == 0);
2540 
2541  SDValue Wt;
2542  SDValue Ws;
2543  const auto &Begin = Indices.begin();
2544  const auto &End = Indices.end();
2545 
2546  // Check even elements are taken from the even elements of one half or the
2547  // other and pick an operand accordingly.
2548  if (fitsRegularPattern<int>(Begin, 2, End, 0, 2))
2549  Wt = Op->getOperand(0);
2550  else if (fitsRegularPattern<int>(Begin, 2, End, Indices.size(), 2))
2551  Wt = Op->getOperand(1);
2552  else
2553  return SDValue();
2554 
2555  // Check odd elements are taken from the even elements of one half or the
2556  // other and pick an operand accordingly.
2557  if (fitsRegularPattern<int>(Begin + 1, 2, End, 0, 2))
2558  Ws = Op->getOperand(0);
2559  else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.size(), 2))
2560  Ws = Op->getOperand(1);
2561  else
2562  return SDValue();
2563 
2564  return DAG.getNode(MipsISD::ILVEV, SDLoc(Op), ResTy, Ws, Wt);
2565 }
2566 
2567 // Lower VECTOR_SHUFFLE into ILVOD (if possible).
2568 //
2569 // ILVOD interleaves the odd elements from each vector.
2570 //
2571 // It is possible to lower into ILVOD when the mask consists of two of the
2572 // following forms interleaved:
2573 // <1, 3, 5, ...>
2574 // <n+1, n+3, n+5, ...>
2575 // where n is the number of elements in the vector.
2576 // For example:
2577 // <1, 1, 3, 3, 5, 5, ...>
2578 // <1, n+1, 3, n+3, 5, n+5, ...>
2579 //
2580 // When undef's appear in the mask they are treated as if they were whatever
2581 // value is necessary in order to fit the above forms.
2583  SmallVector<int, 16> Indices,
2584  SelectionDAG &DAG) {
2585  assert((Indices.size() % 2) == 0);
2586 
2587  SDValue Wt;
2588  SDValue Ws;
2589  const auto &Begin = Indices.begin();
2590  const auto &End = Indices.end();
2591 
2592  // Check even elements are taken from the odd elements of one half or the
2593  // other and pick an operand accordingly.
2594  if (fitsRegularPattern<int>(Begin, 2, End, 1, 2))
2595  Wt = Op->getOperand(0);
2596  else if (fitsRegularPattern<int>(Begin, 2, End, Indices.size() + 1, 2))
2597  Wt = Op->getOperand(1);
2598  else
2599  return SDValue();
2600 
2601  // Check odd elements are taken from the odd elements of one half or the
2602  // other and pick an operand accordingly.
2603  if (fitsRegularPattern<int>(Begin + 1, 2, End, 1, 2))
2604  Ws = Op->getOperand(0);
2605  else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.size() + 1, 2))
2606  Ws = Op->getOperand(1);
2607  else
2608  return SDValue();
2609 
2610  return DAG.getNode(MipsISD::ILVOD, SDLoc(Op), ResTy, Wt, Ws);
2611 }
2612 
2613 // Lower VECTOR_SHUFFLE into ILVR (if possible).
2614 //
2615 // ILVR interleaves consecutive elements from the right (lowest-indexed) half of
2616 // each vector.
2617 //
2618 // It is possible to lower into ILVR when the mask consists of two of the
2619 // following forms interleaved:
2620 // <0, 1, 2, ...>
2621 // <n, n+1, n+2, ...>
2622 // where n is the number of elements in the vector.
2623 // For example:
2624 // <0, 0, 1, 1, 2, 2, ...>
2625 // <0, n, 1, n+1, 2, n+2, ...>
2626 //
2627 // When undef's appear in the mask they are treated as if they were whatever
2628 // value is necessary in order to fit the above forms.
2630  SmallVector<int, 16> Indices,
2631  SelectionDAG &DAG) {
2632  assert((Indices.size() % 2) == 0);
2633 
2634  SDValue Wt;
2635  SDValue Ws;
2636  const auto &Begin = Indices.begin();
2637  const auto &End = Indices.end();
2638 
2639  // Check even elements are taken from the right (lowest-indexed) elements of
2640  // one half or the other and pick an operand accordingly.
2641  if (fitsRegularPattern<int>(Begin, 2, End, 0, 1))
2642  Wt = Op->getOperand(0);
2643  else if (fitsRegularPattern<int>(Begin, 2, End, Indices.size(), 1))
2644  Wt = Op->getOperand(1);
2645  else
2646  return SDValue();
2647 
2648  // Check odd elements are taken from the right (lowest-indexed) elements of
2649  // one half or the other and pick an operand accordingly.
2650  if (fitsRegularPattern<int>(Begin + 1, 2, End, 0, 1))
2651  Ws = Op->getOperand(0);
2652  else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.size(), 1))
2653  Ws = Op->getOperand(1);
2654  else
2655  return SDValue();
2656 
2657  return DAG.getNode(MipsISD::ILVR, SDLoc(Op), ResTy, Ws, Wt);
2658 }
2659 
2660 // Lower VECTOR_SHUFFLE into ILVL (if possible).
2661 //
2662 // ILVL interleaves consecutive elements from the left (highest-indexed) half
2663 // of each vector.
2664 //
2665 // It is possible to lower into ILVL when the mask consists of two of the
2666 // following forms interleaved:
2667 // <x, x+1, x+2, ...>
2668 // <n+x, n+x+1, n+x+2, ...>
2669 // where n is the number of elements in the vector and x is half n.
2670 // For example:
2671 // <x, x, x+1, x+1, x+2, x+2, ...>
2672 // <x, n+x, x+1, n+x+1, x+2, n+x+2, ...>
2673 //
2674 // When undef's appear in the mask they are treated as if they were whatever
2675 // value is necessary in order to fit the above forms.
2677  SmallVector<int, 16> Indices,
2678  SelectionDAG &DAG) {
2679  assert((Indices.size() % 2) == 0);
2680 
2681  unsigned HalfSize = Indices.size() / 2;
2682  SDValue Wt;
2683  SDValue Ws;
2684  const auto &Begin = Indices.begin();
2685  const auto &End = Indices.end();
2686 
2687  // Check even elements are taken from the left (highest-indexed) elements of
2688  // one half or the other and pick an operand accordingly.
2689  if (fitsRegularPattern<int>(Begin, 2, End, HalfSize, 1))
2690  Wt = Op->getOperand(0);
2691  else if (fitsRegularPattern<int>(Begin, 2, End, Indices.size() + HalfSize, 1))
2692  Wt = Op->getOperand(1);
2693  else
2694  return SDValue();
2695 
2696  // Check odd elements are taken from the left (highest-indexed) elements of
2697  // one half or the other and pick an operand accordingly.
2698  if (fitsRegularPattern<int>(Begin + 1, 2, End, HalfSize, 1))
2699  Ws = Op->getOperand(0);
2700  else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.size() + HalfSize,
2701  1))
2702  Ws = Op->getOperand(1);
2703  else
2704  return SDValue();
2705 
2706  return DAG.getNode(MipsISD::ILVL, SDLoc(Op), ResTy, Ws, Wt);
2707 }
2708 
2709 // Lower VECTOR_SHUFFLE into PCKEV (if possible).
2710 //
2711 // PCKEV copies the even elements of each vector into the result vector.
2712 //
2713 // It is possible to lower into PCKEV when the mask consists of two of the
2714 // following forms concatenated:
2715 // <0, 2, 4, ...>
2716 // <n, n+2, n+4, ...>
2717 // where n is the number of elements in the vector.
2718 // For example:
2719 // <0, 2, 4, ..., 0, 2, 4, ...>
2720 // <0, 2, 4, ..., n, n+2, n+4, ...>
2721 //
2722 // When undef's appear in the mask they are treated as if they were whatever
2723 // value is necessary in order to fit the above forms.
2725  SmallVector<int, 16> Indices,
2726  SelectionDAG &DAG) {
2727  assert((Indices.size() % 2) == 0);
2728 
2729  SDValue Wt;
2730  SDValue Ws;
2731  const auto &Begin = Indices.begin();
2732  const auto &Mid = Indices.begin() + Indices.size() / 2;
2733  const auto &End = Indices.end();
2734 
2735  if (fitsRegularPattern<int>(Begin, 1, Mid, 0, 2))
2736  Wt = Op->getOperand(0);
2737  else if (fitsRegularPattern<int>(Begin, 1, Mid, Indices.size(), 2))
2738  Wt = Op->getOperand(1);
2739  else
2740  return SDValue();
2741 
2742  if (fitsRegularPattern<int>(Mid, 1, End, 0, 2))
2743  Ws = Op->getOperand(0);
2744  else if (fitsRegularPattern<int>(Mid, 1, End, Indices.size(), 2))
2745  Ws = Op->getOperand(1);
2746  else
2747  return SDValue();
2748 
2749  return DAG.getNode(MipsISD::PCKEV, SDLoc(Op), ResTy, Ws, Wt);
2750 }
2751 
2752 // Lower VECTOR_SHUFFLE into PCKOD (if possible).
2753 //
2754 // PCKOD copies the odd elements of each vector into the result vector.
2755 //
2756 // It is possible to lower into PCKOD when the mask consists of two of the
2757 // following forms concatenated:
2758 // <1, 3, 5, ...>
2759 // <n+1, n+3, n+5, ...>
2760 // where n is the number of elements in the vector.
2761 // For example:
2762 // <1, 3, 5, ..., 1, 3, 5, ...>
2763 // <1, 3, 5, ..., n+1, n+3, n+5, ...>
2764 //
2765 // When undef's appear in the mask they are treated as if they were whatever
2766 // value is necessary in order to fit the above forms.
2768  SmallVector<int, 16> Indices,
2769  SelectionDAG &DAG) {
2770  assert((Indices.size() % 2) == 0);
2771 
2772  SDValue Wt;
2773  SDValue Ws;
2774  const auto &Begin = Indices.begin();
2775  const auto &Mid = Indices.begin() + Indices.size() / 2;
2776  const auto &End = Indices.end();
2777 
2778  if (fitsRegularPattern<int>(Begin, 1, Mid, 1, 2))
2779  Wt = Op->getOperand(0);
2780  else if (fitsRegularPattern<int>(Begin, 1, Mid, Indices.size() + 1, 2))
2781  Wt = Op->getOperand(1);
2782  else
2783  return SDValue();
2784 
2785  if (fitsRegularPattern<int>(Mid, 1, End, 1, 2))
2786  Ws = Op->getOperand(0);
2787  else if (fitsRegularPattern<int>(Mid, 1, End, Indices.size() + 1, 2))
2788  Ws = Op->getOperand(1);
2789  else
2790  return SDValue();
2791 
2792  return DAG.getNode(MipsISD::PCKOD, SDLoc(Op), ResTy, Ws, Wt);
2793 }
2794 
2795 // Lower VECTOR_SHUFFLE into VSHF.
2796 //
2797 // This mostly consists of converting the shuffle indices in Indices into a
2798 // BUILD_VECTOR and adding it as an operand to the resulting VSHF. There is
2799 // also code to eliminate unused operands of the VECTOR_SHUFFLE. For example,
2800 // if the type is v8i16 and all the indices are less than 8 then the second
2801 // operand is unused and can be replaced with anything. We choose to replace it
2802 // with the used operand since this reduces the number of instructions overall.
2804  SmallVector<int, 16> Indices,
2805  SelectionDAG &DAG) {
2807  SDValue Op0;
2808  SDValue Op1;
2809  EVT MaskVecTy = ResTy.changeVectorElementTypeToInteger();
2810  EVT MaskEltTy = MaskVecTy.getVectorElementType();
2811  bool Using1stVec = false;
2812  bool Using2ndVec = false;
2813  SDLoc DL(Op);
2814  int ResTyNumElts = ResTy.getVectorNumElements();
2815 
2816  for (int i = 0; i < ResTyNumElts; ++i) {
2817  // Idx == -1 means UNDEF
2818  int Idx = Indices[i];
2819 
2820  if (0 <= Idx && Idx < ResTyNumElts)
2821  Using1stVec = true;
2822  if (ResTyNumElts <= Idx && Idx < ResTyNumElts * 2)
2823  Using2ndVec = true;
2824  }
2825 
2826  for (SmallVector<int, 16>::iterator I = Indices.begin(); I != Indices.end();
2827  ++I)
2828  Ops.push_back(DAG.getTargetConstant(*I, DL, MaskEltTy));
2829 
2830  SDValue MaskVec = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVecTy, Ops);
2831 
2832  if (Using1stVec && Using2ndVec) {
2833  Op0 = Op->getOperand(0);
2834  Op1 = Op->getOperand(1);
2835  } else if (Using1stVec)
2836  Op0 = Op1 = Op->getOperand(0);
2837  else if (Using2ndVec)
2838  Op0 = Op1 = Op->getOperand(1);
2839  else
2840  llvm_unreachable("shuffle vector mask references neither vector operand?");
2841 
2842  // VECTOR_SHUFFLE concatenates the vectors in an vectorwise fashion.
2843  // <0b00, 0b01> + <0b10, 0b11> -> <0b00, 0b01, 0b10, 0b11>
2844  // VSHF concatenates the vectors in a bitwise fashion:
2845  // <0b00, 0b01> + <0b10, 0b11> ->
2846  // 0b0100 + 0b1110 -> 0b01001110
2847  // <0b10, 0b11, 0b00, 0b01>
2848  // We must therefore swap the operands to get the correct result.
2849  return DAG.getNode(MipsISD::VSHF, DL, ResTy, MaskVec, Op1, Op0);
2850 }
2851 
2852 // Lower VECTOR_SHUFFLE into one of a number of instructions depending on the
2853 // indices in the shuffle.
2854 SDValue MipsSETargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
2855  SelectionDAG &DAG) const {
2856  ShuffleVectorSDNode *Node = cast<ShuffleVectorSDNode>(Op);
2857  EVT ResTy = Op->getValueType(0);
2858 
2859  if (!ResTy.is128BitVector())
2860  return SDValue();
2861 
2862  int ResTyNumElts = ResTy.getVectorNumElements();
2863  SmallVector<int, 16> Indices;
2864 
2865  for (int i = 0; i < ResTyNumElts; ++i)
2866  Indices.push_back(Node->getMaskElt(i));
2867 
2868  // splati.[bhwd] is preferable to the others but is matched from
2869  // MipsISD::VSHF.
2870  if (isVECTOR_SHUFFLE_SPLATI(Op, ResTy, Indices, DAG))
2871  return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, DAG);
2872  SDValue Result = lowerVECTOR_SHUFFLE_ILVEV(Op, ResTy, Indices, DAG);
2873  if (Result.getNode())
2874  return Result;
2875  Result = lowerVECTOR_SHUFFLE_ILVOD(Op, ResTy, Indices, DAG);
2876  if (Result.getNode())
2877  return Result;
2878  Result = lowerVECTOR_SHUFFLE_ILVL(Op, ResTy, Indices, DAG);
2879  if (Result.getNode())
2880  return Result;
2881  Result = lowerVECTOR_SHUFFLE_ILVR(Op, ResTy, Indices, DAG);
2882  if (Result.getNode())
2883  return Result;
2884  Result = lowerVECTOR_SHUFFLE_PCKEV(Op, ResTy, Indices, DAG);
2885  if (Result.getNode())
2886  return Result;
2887  Result = lowerVECTOR_SHUFFLE_PCKOD(Op, ResTy, Indices, DAG);
2888  if (Result.getNode())
2889  return Result;
2890  Result = lowerVECTOR_SHUFFLE_SHF(Op, ResTy, Indices, DAG);
2891  if (Result.getNode())
2892  return Result;
2893  return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, DAG);
2894 }
2895 
2896 MachineBasicBlock * MipsSETargetLowering::
2897 emitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{
2898  // $bb:
2899  // bposge32_pseudo $vr0
2900  // =>
2901  // $bb:
2902  // bposge32 $tbb
2903  // $fbb:
2904  // li $vr2, 0
2905  // b $sink
2906  // $tbb:
2907  // li $vr1, 1
2908  // $sink:
2909  // $vr0 = phi($vr2, $fbb, $vr1, $tbb)
2910 
2911  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2913  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
2914  DebugLoc DL = MI->getDebugLoc();
2915  const BasicBlock *LLVM_BB = BB->getBasicBlock();
2917  MachineFunction *F = BB->getParent();
2918  MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
2919  MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
2921  F->insert(It, FBB);
2922  F->insert(It, TBB);
2923  F->insert(It, Sink);
2924 
2925  // Transfer the remainder of BB and its successor edges to Sink.
2926  Sink->splice(Sink->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
2927  BB->end());
2929 
2930  // Add successors.
2931  BB->addSuccessor(FBB);
2932  BB->addSuccessor(TBB);
2933  FBB->addSuccessor(Sink);
2934  TBB->addSuccessor(Sink);
2935 
2936  // Insert the real bposge32 instruction to $BB.
2937  BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
2938 
2939  // Fill $FBB.
2940  unsigned VR2 = RegInfo.createVirtualRegister(RC);
2941  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
2942  .addReg(Mips::ZERO).addImm(0);
2943  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
2944 
2945  // Fill $TBB.
2946  unsigned VR1 = RegInfo.createVirtualRegister(RC);
2947  BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
2948  .addReg(Mips::ZERO).addImm(1);
2949 
2950  // Insert phi function to $Sink.
2951  BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
2952  MI->getOperand(0).getReg())
2953  .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB);
2954 
2955  MI->eraseFromParent(); // The pseudo instruction is gone now.
2956  return Sink;
2957 }
2958 
2959 MachineBasicBlock * MipsSETargetLowering::
2960 emitMSACBranchPseudo(MachineInstr *MI, MachineBasicBlock *BB,
2961  unsigned BranchOp) const{
2962  // $bb:
2963  // vany_nonzero $rd, $ws
2964  // =>
2965  // $bb:
2966  // bnz.b $ws, $tbb
2967  // b $fbb
2968  // $fbb:
2969  // li $rd1, 0
2970  // b $sink
2971  // $tbb:
2972  // li $rd2, 1
2973  // $sink:
2974  // $rd = phi($rd1, $fbb, $rd2, $tbb)
2975 
2976  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2977  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
2978  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
2979  DebugLoc DL = MI->getDebugLoc();
2980  const BasicBlock *LLVM_BB = BB->getBasicBlock();
2982  MachineFunction *F = BB->getParent();
2983  MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
2984  MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
2985  MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
2986  F->insert(It, FBB);
2987  F->insert(It, TBB);
2988  F->insert(It, Sink);
2989 
2990  // Transfer the remainder of BB and its successor edges to Sink.
2991  Sink->splice(Sink->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
2992  BB->end());
2994 
2995  // Add successors.
2996  BB->addSuccessor(FBB);
2997  BB->addSuccessor(TBB);
2998  FBB->addSuccessor(Sink);
2999  TBB->addSuccessor(Sink);
3000 
3001  // Insert the real bnz.b instruction to $BB.
3002  BuildMI(BB, DL, TII->get(BranchOp))
3003  .addReg(MI->getOperand(1).getReg())
3004  .addMBB(TBB);
3005 
3006  // Fill $FBB.
3007  unsigned RD1 = RegInfo.createVirtualRegister(RC);
3008  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1)
3009  .addReg(Mips::ZERO).addImm(0);
3010  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
3011 
3012  // Fill $TBB.
3013  unsigned RD2 = RegInfo.createVirtualRegister(RC);
3014  BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2)
3015  .addReg(Mips::ZERO).addImm(1);
3016 
3017  // Insert phi function to $Sink.
3018  BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
3019  MI->getOperand(0).getReg())
3020  .addReg(RD1).addMBB(FBB).addReg(RD2).addMBB(TBB);
3021 
3022  MI->eraseFromParent(); // The pseudo instruction is gone now.
3023  return Sink;
3024 }
3025 
3026 // Emit the COPY_FW pseudo instruction.
3027 //
3028 // copy_fw_pseudo $fd, $ws, n
3029 // =>
3030 // copy_u_w $rt, $ws, $n
3031 // mtc1 $rt, $fd
3032 //
3033 // When n is zero, the equivalent operation can be performed with (potentially)
3034 // zero instructions due to register overlaps. This optimization is never valid
3035 // for lane 1 because it would require FR=0 mode which isn't supported by MSA.
3036 MachineBasicBlock * MipsSETargetLowering::
3037 emitCOPY_FW(MachineInstr *MI, MachineBasicBlock *BB) const{
3038  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3039  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3040  DebugLoc DL = MI->getDebugLoc();
3041  unsigned Fd = MI->getOperand(0).getReg();
3042  unsigned Ws = MI->getOperand(1).getReg();
3043  unsigned Lane = MI->getOperand(2).getImm();
3044 
3045  if (Lane == 0) {
3046  unsigned Wt = Ws;
3047  if (!Subtarget.useOddSPReg()) {
3048  // We must copy to an even-numbered MSA register so that the
3049  // single-precision sub-register is also guaranteed to be even-numbered.
3050  Wt = RegInfo.createVirtualRegister(&Mips::MSA128WEvensRegClass);
3051 
3052  BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Wt).addReg(Ws);
3053  }
3054 
3055  BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
3056  } else {
3057  unsigned Wt = RegInfo.createVirtualRegister(
3058  Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass :
3059  &Mips::MSA128WEvensRegClass);
3060 
3061  BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(Lane);
3062  BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
3063  }
3064 
3065  MI->eraseFromParent(); // The pseudo instruction is gone now.
3066  return BB;
3067 }
3068 
3069 // Emit the COPY_FD pseudo instruction.
3070 //
3071 // copy_fd_pseudo $fd, $ws, n
3072 // =>
3073 // splati.d $wt, $ws, $n
3074 // copy $fd, $wt:sub_64
3075 //
3076 // When n is zero, the equivalent operation can be performed with (potentially)
3077 // zero instructions due to register overlaps. This optimization is always
3078 // valid because FR=1 mode which is the only supported mode in MSA.
3079 MachineBasicBlock * MipsSETargetLowering::
3080 emitCOPY_FD(MachineInstr *MI, MachineBasicBlock *BB) const{
3081  assert(Subtarget.isFP64bit());
3082 
3083  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3084  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3085  unsigned Fd = MI->getOperand(0).getReg();
3086  unsigned Ws = MI->getOperand(1).getReg();
3087  unsigned Lane = MI->getOperand(2).getImm() * 2;
3088  DebugLoc DL = MI->getDebugLoc();
3089 
3090  if (Lane == 0)
3091  BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_64);
3092  else {
3093  unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3094 
3095  BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wt).addReg(Ws).addImm(1);
3096  BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_64);
3097  }
3098 
3099  MI->eraseFromParent(); // The pseudo instruction is gone now.
3100  return BB;
3101 }
3102 
3103 // Emit the INSERT_FW pseudo instruction.
3104 //
3105 // insert_fw_pseudo $wd, $wd_in, $n, $fs
3106 // =>
3107 // subreg_to_reg $wt:sub_lo, $fs
3108 // insve_w $wd[$n], $wd_in, $wt[0]
3110 MipsSETargetLowering::emitINSERT_FW(MachineInstr *MI,
3111  MachineBasicBlock *BB) const {
3112  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3113  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3114  DebugLoc DL = MI->getDebugLoc();
3115  unsigned Wd = MI->getOperand(0).getReg();
3116  unsigned Wd_in = MI->getOperand(1).getReg();
3117  unsigned Lane = MI->getOperand(2).getImm();
3118  unsigned Fs = MI->getOperand(3).getReg();
3119  unsigned Wt = RegInfo.createVirtualRegister(
3120  Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass :
3121  &Mips::MSA128WEvensRegClass);
3122 
3123  BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
3124  .addImm(0)
3125  .addReg(Fs)
3126  .addImm(Mips::sub_lo);
3127  BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_W), Wd)
3128  .addReg(Wd_in)
3129  .addImm(Lane)
3130  .addReg(Wt)
3131  .addImm(0);
3132 
3133  MI->eraseFromParent(); // The pseudo instruction is gone now.
3134  return BB;
3135 }
3136 
3137 // Emit the INSERT_FD pseudo instruction.
3138 //
3139 // insert_fd_pseudo $wd, $fs, n
3140 // =>
3141 // subreg_to_reg $wt:sub_64, $fs
3142 // insve_d $wd[$n], $wd_in, $wt[0]
3144 MipsSETargetLowering::emitINSERT_FD(MachineInstr *MI,
3145  MachineBasicBlock *BB) const {
3146  assert(Subtarget.isFP64bit());
3147 
3148  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3149  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3150  DebugLoc DL = MI->getDebugLoc();
3151  unsigned Wd = MI->getOperand(0).getReg();
3152  unsigned Wd_in = MI->getOperand(1).getReg();
3153  unsigned Lane = MI->getOperand(2).getImm();
3154  unsigned Fs = MI->getOperand(3).getReg();
3155  unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3156 
3157  BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
3158  .addImm(0)
3159  .addReg(Fs)
3160  .addImm(Mips::sub_64);
3161  BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_D), Wd)
3162  .addReg(Wd_in)
3163  .addImm(Lane)
3164  .addReg(Wt)
3165  .addImm(0);
3166 
3167  MI->eraseFromParent(); // The pseudo instruction is gone now.
3168  return BB;
3169 }
3170 
3171 // Emit the INSERT_([BHWD]|F[WD])_VIDX pseudo instruction.
3172 //
3173 // For integer:
3174 // (INSERT_([BHWD]|F[WD])_PSEUDO $wd, $wd_in, $n, $rs)
3175 // =>
3176 // (SLL $lanetmp1, $lane, <log2size)
3177 // (SLD_B $wdtmp1, $wd_in, $wd_in, $lanetmp1)
3178 // (INSERT_[BHWD], $wdtmp2, $wdtmp1, 0, $rs)
3179 // (NEG $lanetmp2, $lanetmp1)
3180 // (SLD_B $wd, $wdtmp2, $wdtmp2, $lanetmp2)
3181 //
3182 // For floating point:
3183 // (INSERT_([BHWD]|F[WD])_PSEUDO $wd, $wd_in, $n, $fs)
3184 // =>
3185 // (SUBREG_TO_REG $wt, $fs, <subreg>)
3186 // (SLL $lanetmp1, $lane, <log2size)
3187 // (SLD_B $wdtmp1, $wd_in, $wd_in, $lanetmp1)
3188 // (INSVE_[WD], $wdtmp2, 0, $wdtmp1, 0)
3189 // (NEG $lanetmp2, $lanetmp1)
3190 // (SLD_B $wd, $wdtmp2, $wdtmp2, $lanetmp2)
3192 MipsSETargetLowering::emitINSERT_DF_VIDX(MachineInstr *MI,
3193  MachineBasicBlock *BB,
3194  unsigned EltSizeInBytes,
3195  bool IsFP) const {
3196  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3197  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3198  DebugLoc DL = MI->getDebugLoc();
3199  unsigned Wd = MI->getOperand(0).getReg();
3200  unsigned SrcVecReg = MI->getOperand(1).getReg();
3201  unsigned LaneReg = MI->getOperand(2).getReg();
3202  unsigned SrcValReg = MI->getOperand(3).getReg();
3203 
3204  const TargetRegisterClass *VecRC = nullptr;
3205  const TargetRegisterClass *GPRRC =
3206  Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
3207  unsigned EltLog2Size;
3208  unsigned InsertOp = 0;
3209  unsigned InsveOp = 0;
3210  switch (EltSizeInBytes) {
3211  default:
3212  llvm_unreachable("Unexpected size");
3213  case 1:
3214  EltLog2Size = 0;
3215  InsertOp = Mips::INSERT_B;
3216  InsveOp = Mips::INSVE_B;
3217  VecRC = &Mips::MSA128BRegClass;
3218  break;
3219  case 2:
3220  EltLog2Size = 1;
3221  InsertOp = Mips::INSERT_H;
3222  InsveOp = Mips::INSVE_H;
3223  VecRC = &Mips::MSA128HRegClass;
3224  break;
3225  case 4:
3226  EltLog2Size = 2;
3227  InsertOp = Mips::INSERT_W;
3228  InsveOp = Mips::INSVE_W;
3229  VecRC = &Mips::MSA128WRegClass;
3230  break;
3231  case 8:
3232  EltLog2Size = 3;
3233  InsertOp = Mips::INSERT_D;
3234  InsveOp = Mips::INSVE_D;
3235  VecRC = &Mips::MSA128DRegClass;
3236  break;
3237  }
3238 
3239  if (IsFP) {
3240  unsigned Wt = RegInfo.createVirtualRegister(VecRC);
3241  BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
3242  .addImm(0)
3243  .addReg(SrcValReg)
3244  .addImm(EltSizeInBytes == 8 ? Mips::sub_64 : Mips::sub_lo);
3245  SrcValReg = Wt;
3246  }
3247 
3248  // Convert the lane index into a byte index
3249  if (EltSizeInBytes != 1) {
3250  unsigned LaneTmp1 = RegInfo.createVirtualRegister(GPRRC);
3251  BuildMI(*BB, MI, DL, TII->get(Mips::SLL), LaneTmp1)
3252  .addReg(LaneReg)
3253  .addImm(EltLog2Size);
3254  LaneReg = LaneTmp1;
3255  }
3256 
3257  // Rotate bytes around so that the desired lane is element zero
3258  unsigned WdTmp1 = RegInfo.createVirtualRegister(VecRC);
3259  BuildMI(*BB, MI, DL, TII->get(Mips::SLD_B), WdTmp1)
3260  .addReg(SrcVecReg)
3261  .addReg(SrcVecReg)
3262  .addReg(LaneReg);
3263 
3264  unsigned WdTmp2 = RegInfo.createVirtualRegister(VecRC);
3265  if (IsFP) {
3266  // Use insve.df to insert to element zero
3267  BuildMI(*BB, MI, DL, TII->get(InsveOp), WdTmp2)
3268  .addReg(WdTmp1)
3269  .addImm(0)
3270  .addReg(SrcValReg)
3271  .addImm(0);
3272  } else {
3273  // Use insert.df to insert to element zero
3274  BuildMI(*BB, MI, DL, TII->get(InsertOp), WdTmp2)
3275  .addReg(WdTmp1)
3276  .addReg(SrcValReg)
3277  .addImm(0);
3278  }
3279 
3280  // Rotate elements the rest of the way for a full rotation.
3281  // sld.df inteprets $rt modulo the number of columns so we only need to negate
3282  // the lane index to do this.
3283  unsigned LaneTmp2 = RegInfo.createVirtualRegister(GPRRC);
3284  BuildMI(*BB, MI, DL, TII->get(Subtarget.isABI_N64() ? Mips::DSUB : Mips::SUB),
3285  LaneTmp2)
3286  .addReg(Subtarget.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO)
3287  .addReg(LaneReg);
3288  BuildMI(*BB, MI, DL, TII->get(Mips::SLD_B), Wd)
3289  .addReg(WdTmp2)
3290  .addReg(WdTmp2)
3291  .addReg(LaneTmp2);
3292 
3293  MI->eraseFromParent(); // The pseudo instruction is gone now.
3294  return BB;
3295 }
3296 
3297 // Emit the FILL_FW pseudo instruction.
3298 //
3299 // fill_fw_pseudo $wd, $fs
3300 // =>
3301 // implicit_def $wt1
3302 // insert_subreg $wt2:subreg_lo, $wt1, $fs
3303 // splati.w $wd, $wt2[0]
3305 MipsSETargetLowering::emitFILL_FW(MachineInstr *MI,
3306  MachineBasicBlock *BB) const {
3307  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3308  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3309  DebugLoc DL = MI->getDebugLoc();
3310  unsigned Wd = MI->getOperand(0).getReg();
3311  unsigned Fs = MI->getOperand(1).getReg();
3312  unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3313  unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3314 
3315  BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
3316  BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
3317  .addReg(Wt1)
3318  .addReg(Fs)
3319  .addImm(Mips::sub_lo);
3320  BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wd).addReg(Wt2).addImm(0);
3321 
3322  MI->eraseFromParent(); // The pseudo instruction is gone now.
3323  return BB;
3324 }
3325 
3326 // Emit the FILL_FD pseudo instruction.
3327 //
3328 // fill_fd_pseudo $wd, $fs
3329 // =>
3330 // implicit_def $wt1
3331 // insert_subreg $wt2:subreg_64, $wt1, $fs
3332 // splati.d $wd, $wt2[0]
3334 MipsSETargetLowering::emitFILL_FD(MachineInstr *MI,
3335  MachineBasicBlock *BB) const {
3336  assert(Subtarget.isFP64bit());
3337 
3338  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3339  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3340  DebugLoc DL = MI->getDebugLoc();
3341  unsigned Wd = MI->getOperand(0).getReg();
3342  unsigned Fs = MI->getOperand(1).getReg();
3343  unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3344  unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3345 
3346  BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
3347  BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
3348  .addReg(Wt1)
3349  .addReg(Fs)
3350  .addImm(Mips::sub_64);
3351  BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wd).addReg(Wt2).addImm(0);
3352 
3353  MI->eraseFromParent(); // The pseudo instruction is gone now.
3354  return BB;
3355 }
3356 
3357 // Emit the FEXP2_W_1 pseudo instructions.
3358 //
3359 // fexp2_w_1_pseudo $wd, $wt
3360 // =>
3361 // ldi.w $ws, 1
3362 // fexp2.w $wd, $ws, $wt
3364 MipsSETargetLowering::emitFEXP2_W_1(MachineInstr *MI,
3365  MachineBasicBlock *BB) const {
3366  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3367  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3368  const TargetRegisterClass *RC = &Mips::MSA128WRegClass;
3369  unsigned Ws1 = RegInfo.createVirtualRegister(RC);
3370  unsigned Ws2 = RegInfo.createVirtualRegister(RC);
3371  DebugLoc DL = MI->getDebugLoc();
3372 
3373  // Splat 1.0 into a vector
3374  BuildMI(*BB, MI, DL, TII->get(Mips::LDI_W), Ws1).addImm(1);
3375  BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_W), Ws2).addReg(Ws1);
3376 
3377  // Emit 1.0 * fexp2(Wt)
3378  BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_W), MI->getOperand(0).getReg())
3379  .addReg(Ws2)
3380  .addReg(MI->getOperand(1).getReg());
3381 
3382  MI->eraseFromParent(); // The pseudo instruction is gone now.
3383  return BB;
3384 }
3385 
3386 // Emit the FEXP2_D_1 pseudo instructions.
3387 //
3388 // fexp2_d_1_pseudo $wd, $wt
3389 // =>
3390 // ldi.d $ws, 1
3391 // fexp2.d $wd, $ws, $wt
3393 MipsSETargetLowering::emitFEXP2_D_1(MachineInstr *MI,
3394  MachineBasicBlock *BB) const {
3395  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3396  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3397  const TargetRegisterClass *RC = &Mips::MSA128DRegClass;
3398  unsigned Ws1 = RegInfo.createVirtualRegister(RC);
3399  unsigned Ws2 = RegInfo.createVirtualRegister(RC);
3400  DebugLoc DL = MI->getDebugLoc();
3401 
3402  // Splat 1.0 into a vector
3403  BuildMI(*BB, MI, DL, TII->get(Mips::LDI_D), Ws1).addImm(1);
3404  BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_D), Ws2).addReg(Ws1);
3405 
3406  // Emit 1.0 * fexp2(Wt)
3407  BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_D), MI->getOperand(0).getReg())
3408  .addReg(Ws2)
3409  .addReg(MI->getOperand(1).getReg());
3410 
3411  MI->eraseFromParent(); // The pseudo instruction is gone now.
3412  return BB;
3413 }
const MipsTargetLowering * createMipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
value_iterator value_begin() const
unsigned getIncomingArgSize() const
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:477
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:724
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
SDValue getValue(unsigned R) const
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant, which is required to be operand #1) half of the integer or float value specified as operand #0.
Definition: ISDOpcodes.h:175
static SDValue genConstMult(SDValue X, uint64_t C, SDLoc DL, EVT VT, EVT ShiftTy, SelectionDAG &DAG)
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1327
const MipsSubtarget & Subtarget
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS=0, unsigned Align=1, bool *Fast=nullptr) const override
Determine if the target supports unaligned memory accesses.
static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG)
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
Definition: ISDOpcodes.h:301
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
SDVTList getVTList() const
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
SDValue getMergeValues(ArrayRef< SDValue > Ops, SDLoc dl)
Create a MERGE_VALUES node from the given operands.
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:210
static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Get a value with low bits set.
Definition: APInt.h:531
const MipsInstrInfo * getInstrInfo() const override
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
unsigned getInRegsParamsCount() const
unsigned getNumOperands() const
Return the number of values used by this operation.
A debug info location.
Definition: DebugLoc.h:34
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *fromMBB)
transferSuccessorsAndUpdatePHIs - Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor blocks which refer to fromMBB to refer to this.
const SDValue & getOperand(unsigned Num) const
F(f)
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
const SDValue & getBasePtr() const
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
Definition: ISDOpcodes.h:658
virtual const TargetRegisterClass * getRepRegClassFor(MVT VT) const
Return the 'representative' register class for the specified value type.
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:357
unsigned getResNo() const
get the index which selects a specific result in the SDNode
This SDNode is used to implement the code generator support for the llvm IR shufflevector instruction...
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
bool hasMips32() const
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
Definition: ISDOpcodes.h:150
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:200
COPY - Target-independent register copy.
Definition: TargetOpcodes.h:86
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:115
SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
const HexagonInstrInfo * TII
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:308
Shift and rotation operations.
Definition: ISDOpcodes.h:332
bool systemSupportsUnalignedAccess() const
Does the system support unaligned memory access.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
static cl::opt< bool > EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden, cl::desc("MIPS: Enable tail calls."), cl::init(false))
APInt LLVM_ATTRIBUTE_UNUSED_RESULT lshr(unsigned shiftAmt) const
Logical right-shift function.
Definition: APInt.cpp:1142
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
Definition: ISDOpcodes.h:181
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APInt.h:33
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn't supported on the target and indicate what to d...
SimpleValueType SimpleTy
static SDValue lowerMSABitClearImm(SDValue Op, SelectionDAG &DAG)
static bool isConstantOrUndefBUILD_VECTOR(const BuildVectorSDNode *Op)
Number of individual test Apply this number of consecutive mutations to each input exit after the first new interesting input is found the minimized corpus is saved into the first input directory Number of jobs to run If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
int getMaskElt(unsigned Idx) const
bool hasMSA() const
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
Definition: ValueTypes.h:110
static SDValue lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
EVT getVectorElementType() const
getVectorElementType - Given a vector type, return the type of each element.
Definition: ValueTypes.h:216
bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef, unsigned &SplatBitSize, bool &HasAnyUndefs, unsigned MinSplatBits=0, bool isBigEndian=false) const
Check if this is a constant splat, and if so, find the smallest element size that splats the vector...
bool hasMips64() const
static bool isVSplat(SDValue N, APInt &Imm, bool IsLittleEndian)
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:393
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
value_iterator value_end() const
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
Definition: ISDOpcodes.h:351
static bool isVECTOR_SHUFFLE_SPLATI(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:191
static bool isConstantOrUndef(const SDValue Op)
const SDValue & getBasePtr() const
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
Definition: SelectionDAG.h:659
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:804
const APInt & getAPIntValue() const
TargetConstant* - Like Constant*, but the DAG does not do any folding, simplification, or lowering of the constant.
Definition: ISDOpcodes.h:116
EVT getMemoryVT() const
Return the type of the in-memory value.
int64_t getImm() const
static SDValue lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
Definition: ISDOpcodes.h:142
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:284
static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
const BasicBlock * getBasicBlock() const
getBasicBlock - Return the LLVM basic block that this instance corresponded to originally.
UNDEF - An undefined node.
Definition: ISDOpcodes.h:169
This class is used to represent ISD::STORE nodes.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:267
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:436
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable...
Definition: ISDOpcodes.h:262
TargetInstrInfo - Interface to description of machine instruction set.
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:247
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Get a value with high bits set.
Definition: APInt.h:513
static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
SDNode * getNode() const
get the SDNode which holds the desired result
IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
Definition: TargetOpcodes.h:52
bundle_iterator< MachineInstr, instr_iterator > iterator
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:325
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
Definition: ISDOpcodes.h:157
static SDValue lowerVECTOR_SHUFFLE_ILVEV(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
bool useOddSPReg() const
APInt LLVM_ATTRIBUTE_UNUSED_RESULT trunc(unsigned width) const
Truncate to new width.
Definition: APInt.cpp:932
static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc)
MVT - Machine Value Type.
LLVM Basic Block Representation.
Definition: BasicBlock.h:65
static SDValue getBuildVectorSplat(EVT VecTy, SDValue SplatValue, bool BigEndian, SelectionDAG &DAG)
const SDValue & getOperand(unsigned i) const
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
static volatile int One
Definition: InfiniteTest.cpp:9
Simple binary floating point operators.
Definition: ISDOpcodes.h:237
void setTargetDAGCombine(ISD::NodeType NT)
Targets should invoke this method for each target independent node that they want to provide a custom...
bool isNonTemporal() const
static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC)
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL...
Definition: ISDOpcodes.h:267
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:219
static bool isVectorAllOnes(SDValue N)
static SDValue lowerVECTOR_SHUFFLE_PCKEV(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
INSERT_SUBREG - This instruction takes three operands: a register that has subregisters, a register providing an insert value, and a subregister index.
Definition: TargetOpcodes.h:49
bool isFP64bit() const
static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr)
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang","erlang-compatible garbage collector")
SDValue getTargetConstant(uint64_t Val, SDLoc DL, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:436
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1273
unsigned getOpcode() const
static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static mvt_range vector_valuetypes()
bool useSoftFloat() const
bool isVolatile() const
const SDValue & getValue() const
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
EVT - Extended Value Type.
Definition: ValueTypes.h:31
bool hasMips32r6() const
static bool fitsRegularPattern(typename SmallVectorImpl< ValType >::const_iterator Begin, unsigned CheckStride, typename SmallVectorImpl< ValType >::const_iterator End, ValType ExpectedIndex, unsigned ExpectedIndexStride)
Determine whether a range fits a regular pattern of values.
MachinePointerInfo - This class contains a discriminated union of information about pointers in memor...
uint64_t getConstantOperandVal(unsigned Num) const
Helper method returns the integer value of a ConstantSDNode operand.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
static bool selectMADD(SDNode *ADDENode, SelectionDAG *CurDAG)
bool isBuildVectorAllOnes(const SDNode *N)
Node predicates.
SDValue getNOT(SDLoc DL, SDValue Val, EVT VT)
Create a bitwise NOT operation as (XOR Val, -1).
CCState - This class holds information needed while lowering arguments and return values...
static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
bool isABI_N64() const
const MipsRegisterInfo * getRegisterInfo() const override
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
Definition: ISDOpcodes.h:273
bool isInvariant() const
static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG, const TargetLowering::DAGCombinerInfo &DCI, const MipsSETargetLowering *TL)
double Log2(double Value)
Log2 - This function returns the log base 2 of the specified value.
Definition: MathExtras.h:457
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:179
SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:861
static SDValue lowerMSABitClear(SDValue Op, SelectionDAG &DAG)
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:548
const SDValue & getChain() const
static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG)
bool isLittle() const
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc)
Represents one node in the SelectionDAG.
bool use_empty() const
Return true if there are no nodes using value ResNo of Node.
bool hasMips64r6() const
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
AAMDNodes getAAInfo() const
Returns the AA info that describes the dereference.
unsigned Log2_64_Ceil(uint64_t Value)
Log2_64_Ceil - This function returns the ceil log base 2 of the specified value, 64 if the value is z...
Definition: MathExtras.h:487
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:123
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:576
static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG, const MipsSubtarget &Subtarget)
static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG)
Class for arbitrary precision integers.
Definition: APInt.h:73
static bool isSplatVector(const BuildVectorSDNode *N)
Check if the given BuildVectorSDNode is a splat.
bool isSignedIntN(unsigned N) const
Check if this APInt has an N-bits signed integer value.
Definition: APInt.h:378
A "pseudo-class" with methods for operating on BUILD_VECTORs.
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:342
static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty, SelectionDAG &DAG, const MipsSubtarget &Subtarget)
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:383
bool isPowerOf2_64(uint64_t Value)
isPowerOf2_64 - This function returns true if the argument is a power of two 0 (64 bit edition...
Definition: MathExtras.h:360
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:285
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
static SDValue lowerVECTOR_SHUFFLE_ILVOD(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:238
static SDValue lowerMSASplatZExt(SDValue Op, unsigned OpNr, SelectionDAG &DAG)
static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
bool isGP64bit() const
static bool isBitwiseInverse(SDValue N, SDValue OfNode)
static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr)
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)
Definition: Metadata.h:1030
bool isAllOnesValue() const
Determine if all bits are set.
Definition: APInt.h:337
Representation of each machine instruction.
Definition: MachineInstr.h:51
bool hasDSPR2() const
static SDValue initAccumulator(SDValue In, SDLoc DL, SelectionDAG &DAG)
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:321
SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:196
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
bool isSingleFloat() const
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:518
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:233
const TargetRegisterClass * getRepRegClassFor(MVT VT) const override
Return the 'representative' register class for the specified value type.
#define I(x, y, z)
Definition: MD5.cpp:54
#define N
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
static SDValue lowerMSABinaryBitImmIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc, SDValue Imm, bool BigEndian)
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
virtual void getOpndList(SmallVectorImpl< SDValue > &Ops, std::deque< std::pair< unsigned, SDValue > > &RegsToPass, bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const
This function fills Ops, which is the list of operands that will later be used when a function call n...
EVT getValueType() const
Return the ValueType of the referenced return value.
bool hasDSP() const
SDValue getConstant(uint64_t Val, SDLoc DL, EVT VT, bool isTarget=false, bool isOpaque=false)
bool is128BitVector() const
is128BitVector - Return true if this is a 128-bit vector type.
Definition: ValueTypes.h:135
unsigned getReg() const
getReg - Returns the register number.
void insert(iterator MBBI, MachineBasicBlock *MBB)
bool hasCnMips() const
LLVM Value Representation.
Definition: Value.h:69
FMA - Perform a * b + c with no intermediate rounding step.
Definition: ISDOpcodes.h:240
static SDValue extractLOHI(SDValue Op, SDLoc DL, SelectionDAG &DAG)
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
SDValue getValueType(EVT)
void printrWithDepth(raw_ostream &O, const SelectionDAG *G=nullptr, unsigned depth=100) const
Print a SelectionDAG node and children up to depth "depth." The given SelectionDAG allows target-spec...
static SDValue lowerVECTOR_SHUFFLE_SHF(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
BasicBlockListType::iterator iterator
static SDValue lowerVECTOR_SHUFFLE_ILVL(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
void ReplaceAllUsesOfValueWith(SDValue From, SDValue To)
Replace any uses of From with To, leaving uses of other values produced by From.Val alone...
#define DEBUG(X)
Definition: Debug.h:92
MipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:365
SDValue getSetCC(SDLoc DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
Definition: SelectionDAG.h:726
SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except that the first operand is an imme...
Definition: TargetOpcodes.h:58
void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC)
Enable MSA support for the given integer type and Register class.
static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG)
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:389
unsigned getAlignment() const
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
void addSuccessor(MachineBasicBlock *succ, uint32_t weight=0)
addSuccessor - Add succ as a successor of this MachineBasicBlock.
unsigned Log2_64(uint64_t Value)
Log2_64 - This function returns the floor log base 2 of the specified value, -1 if the value is zero...
Definition: MathExtras.h:474
EVT changeVectorElementTypeToInteger() const
changeVectorElementTypeToInteger - Return a vector with the same number of elements as this vector...
Definition: ValueTypes.h:80
static cl::opt< bool > NoDPLoadStore("mno-ldc1-sdc1", cl::init(false), cl::desc("Expand double precision loads and ""stores to their single precision ""counterparts"))
static SDValue lowerVECTOR_SHUFFLE_PCKOD(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
void addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC)
Enable MSA support for the given floating-point type and Register class.
MVT getSimpleVT() const
getSimpleVT - Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:203
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
uint64_t getZExtValue() const
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:314
unsigned getVectorNumElements() const
getVectorNumElements - Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:225
This class is used to represent ISD::LOAD nodes.