LLVM  3.7.0
AllocationOrder.cpp
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1 //===-- llvm/CodeGen/AllocationOrder.cpp - Allocation Order ---------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements an allocation order for virtual registers.
11 //
12 // The preferred allocation order for a virtual register depends on allocation
13 // hints and target hooks. The AllocationOrder class encapsulates all of that.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #include "AllocationOrder.h"
22 #include "llvm/Support/Debug.h"
24 
25 using namespace llvm;
26 
27 #define DEBUG_TYPE "regalloc"
28 
29 // Compare VirtRegMap::getRegAllocPref().
31  const VirtRegMap &VRM,
32  const RegisterClassInfo &RegClassInfo)
33  : Pos(0) {
34  const MachineFunction &MF = VRM.getMachineFunction();
35  const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo();
36  Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
37  TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM);
38  rewind();
39 
40  DEBUG({
41  if (!Hints.empty()) {
42  dbgs() << "hints:";
43  for (unsigned I = 0, E = Hints.size(); I != E; ++I)
44  dbgs() << ' ' << PrintReg(Hints[I], TRI);
45  dbgs() << '\n';
46  }
47  });
48 #ifndef NDEBUG
49  for (unsigned I = 0, E = Hints.size(); I != E; ++I)
50  assert(std::find(Order.begin(), Order.end(), Hints[I]) != Order.end() &&
51  "Target hint is outside allocation order.");
52 #endif
53 }
void rewind()
Start over from the beginning.
MachineFunction & getMachineFunction() const
Definition: VirtRegMap.h:80
iterator end() const
Definition: ArrayRef.h:123
const TargetRegisterClass * getRegClass(unsigned Reg) const
getRegClass - Return the register class of the specified virtual register.
ArrayRef< MCPhysReg > getOrder(const TargetRegisterClass *RC) const
getOrder - Returns the preferred allocation order for RC.
PrintReg - Helper class for printing registers on a raw_ostream.
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Definition: SmallVector.h:57
AllocationOrder(unsigned VirtReg, const VirtRegMap &VRM, const RegisterClassInfo &RegClassInfo)
Create a new AllocationOrder for VirtReg.
const TargetRegisterInfo & getTargetRegInfo() const
Definition: VirtRegMap.h:86
iterator begin() const
Definition: ArrayRef.h:122
virtual void getRegAllocationHints(unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr) const
Get a list of 'hint' registers that the register allocator should try first when allocating a physica...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:123
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
#define I(x, y, z)
Definition: MD5.cpp:54
#define DEBUG(X)
Definition: Debug.h:92