17 #define _USE_MATH_DEFINES
257 bool SITargetLowering::isLegalFlatAddressingMode(
const AddrMode &AM)
const {
260 return AM.BaseOffs == 0 && (AM.Scale == 0 || AM.Scale == 1);
282 return isLegalFlatAddressingMode(AM);
347 return isLegalFlatAddressingMode(AM);
357 bool *IsFast)
const {
376 return Align % 4 == 0;
394 unsigned SrcAlign,
bool IsMemset,
403 if (Size >= 16 && DstAlign >= 4)
406 if (Size >= 8 && DstAlign >= 4)
436 unsigned Offset,
bool Signed)
const {
467 IVT, SL, Chain, Ptr, PtrOffset, PtrInfo, MemIVT,
482 VT, SL, Chain, Ptr, PtrOffset, PtrInfo, MemVT,
505 for (
unsigned i = 0, e = Ins.
size(), PSInputNum = 0; i != e; ++i) {
512 assert((PSInputNum <= 15) &&
"Too many PS inputs!");
536 for (
unsigned j = 0; j != NumElements; ++j) {
554 CCInfo.AllocateReg(AMDGPU::VGPR0);
555 CCInfo.AllocateReg(AMDGPU::VGPR1);
566 unsigned InputPtrReg =
568 unsigned InputPtrRegLo =
570 unsigned InputPtrRegHi =
573 unsigned ScratchPtrReg =
575 unsigned ScratchPtrRegLo =
577 unsigned ScratchPtrRegHi =
580 CCInfo.AllocateReg(InputPtrRegLo);
581 CCInfo.AllocateReg(InputPtrRegHi);
582 CCInfo.AllocateReg(ScratchPtrRegLo);
583 CCInfo.AllocateReg(ScratchPtrRegHi);
584 MF.
addLiveIn(InputPtrReg, &AMDGPU::SReg_64RegClass);
585 MF.
addLiveIn(ScratchPtrReg, &AMDGPU::SReg_64RegClass);
597 for (
unsigned i = 0, e = Ins.
size(), ArgIdx = 0; i != e; ++i) {
610 EVT MemVT = Splits[i].VT;
615 SDValue Arg = LowerParameter(DAG, VT, MemVT, DL, Chain,
616 Offset, Ins[i].
Flags.isSExt());
634 assert(VA.
isRegLoc() &&
"Parameter must be in a register!");
640 Reg = TRI->getMatchingSuperReg(Reg, AMDGPU::sub0,
641 &AMDGPU::SReg_64RegClass);
642 Reg = MF.
addLiveIn(Reg, &AMDGPU::SReg_64RegClass);
661 for (
unsigned j = 1; j != NumElements; ++j) {
662 Reg = ArgLocs[ArgIdx++].getLocReg();
682 AMDGPU::SGPR_32RegClass.
begin(), AMDGPU::SGPR_32RegClass.getNumRegs()));
704 case AMDGPU::SI_RegisterStorePseudo: {
790 SDValue Result = LowerLOAD(Op, DAG);
793 "Load should return a value and a chain");
799 return LowerTrig(Op, DAG);
801 case ISD::FDIV:
return LowerFDIV(Op, DAG);
806 return LowerGlobalAddress(MFI, Op, DAG);
821 if (
I.getUse().get() != Value)
824 if (
I->getOpcode() == Opcode)
885 ArrayRef<EVT> Res(Intr->value_begin() + 1, Intr->value_end());
890 Ops.append(Intr->op_begin() + 1, Intr->op_end());
891 Ops.push_back(Target);
912 for (
unsigned i = 1, e = Intr->getNumValues() - 1; i != e; ++i) {
928 SDValue(Intr, Intr->getNumValues() - 1),
988 unsigned IntrinsicID = cast<ConstantSDNode>(Op.
getOperand(0))->getZExtValue();
990 switch (IntrinsicID) {
991 case Intrinsic::r600_read_ngroups_x:
992 return LowerParameter(DAG, VT, VT, DL, DAG.
getEntryNode(),
994 case Intrinsic::r600_read_ngroups_y:
995 return LowerParameter(DAG, VT, VT, DL, DAG.
getEntryNode(),
997 case Intrinsic::r600_read_ngroups_z:
998 return LowerParameter(DAG, VT, VT, DL, DAG.
getEntryNode(),
1000 case Intrinsic::r600_read_global_size_x:
1001 return LowerParameter(DAG, VT, VT, DL, DAG.
getEntryNode(),
1003 case Intrinsic::r600_read_global_size_y:
1004 return LowerParameter(DAG, VT, VT, DL, DAG.
getEntryNode(),
1006 case Intrinsic::r600_read_global_size_z:
1007 return LowerParameter(DAG, VT, VT, DL, DAG.
getEntryNode(),
1009 case Intrinsic::r600_read_local_size_x:
1010 return LowerParameter(DAG, VT, VT, DL, DAG.
getEntryNode(),
1012 case Intrinsic::r600_read_local_size_y:
1013 return LowerParameter(DAG, VT, VT, DL, DAG.
getEntryNode(),
1015 case Intrinsic::r600_read_local_size_z:
1016 return LowerParameter(DAG, VT, VT, DL, DAG.
getEntryNode(),
1019 case Intrinsic::AMDGPU_read_workdim:
1020 return LowerParameter(DAG, VT, VT, DL, DAG.
getEntryNode(),
1023 case Intrinsic::r600_read_tgid_x:
1026 case Intrinsic::r600_read_tgid_y:
1029 case Intrinsic::r600_read_tgid_z:
1032 case Intrinsic::r600_read_tidig_x:
1035 case Intrinsic::r600_read_tidig_y:
1038 case Intrinsic::r600_read_tidig_z:
1041 case AMDGPUIntrinsic::SI_load_const: {
1054 case AMDGPUIntrinsic::SI_sample:
1056 case AMDGPUIntrinsic::SI_sampleb:
1058 case AMDGPUIntrinsic::SI_sampled:
1060 case AMDGPUIntrinsic::SI_samplel:
1062 case AMDGPUIntrinsic::SI_vs_load_input:
1068 case AMDGPUIntrinsic::AMDGPU_fract:
1069 case AMDGPUIntrinsic::AMDIL_fraction:
1072 case AMDGPUIntrinsic::SI_fs_constant: {
1079 case AMDGPUIntrinsic::SI_fs_interp: {
1104 unsigned IntrinsicID = cast<ConstantSDNode>(Op.
getOperand(1))->getZExtValue();
1106 switch (IntrinsicID) {
1107 case AMDGPUIntrinsic::SI_sendmsg: {
1113 case AMDGPUIntrinsic::SI_tbuffer_store: {
1151 "Custom lowering for non-i32 vectors hasn't been implemented.");
1153 assert(NumElements != 2 &&
"v2 loads are supported for all address spaces.");
1159 if (NumElements <= 4)
1170 SDValue SITargetLowering::LowerSampleIntrinsic(
unsigned Opcode,
1217 CLHS->isExactlyValue(1.0)) {
1246 SDValue FastLowered = LowerFastFDIV(Op, DAG);
1287 return LowerFastFDIV(Op, DAG);
1315 NegDivScale0, Mul, DivScale1);
1347 Fma4, Fma3, Mul, Scale);
1356 return LowerFDIV32(Op, DAG);
1359 return LowerFDIV64(Op, DAG);
1371 if (VT.isVector() && VT.getVectorNumElements() > 4)
1380 if (VT.isVector() && VT.getVectorNumElements() >= 8)
1415 DAGCombinerInfo &DCI)
const {
1431 if (DCI.isAfterLegalizeVectorOps() && SrcVT ==
MVT::i32) {
1434 DCI.AddToWorklist(Cvt.
getNode());
1443 if (!DCI.isBeforeLegalize() ||
1449 assert(DCI.isBeforeLegalize() &&
"Unexpected legal type");
1454 if (!SrcVT.
isSimple() && NElts != 3)
1466 unsigned Align = Load->getAlignment();
1473 if (Align < ABIAlignment &&
1482 Load->getMemOperand());
1489 if (RegVT.isVector())
1496 unsigned EltIdx = 0;
1498 unsigned ComponentsInElt =
std::min(4u, NElts - 4 * EltIdx);
1499 for (
unsigned I = 0; I < ComponentsInElt; ++
I) {
1502 DCI.AddToWorklist(Cvt.
getNode());
1509 assert(Ops.
size() == NElts);
1524 return isUInt<12>(OffsetSize);
1530 return isUInt<20>(OffsetSize);
1532 return (OffsetSize % 4 == 0) &&
isUInt<8>(OffsetSize / 4);
1562 DAGCombinerInfo &DCI)
const {
1594 DAGCombinerInfo &DCI)
const {
1595 if (DCI.isBeforeLegalize())
1648 DAGCombinerInfo &DCI)
const {
1666 static const uint32_t MaxMask = 0x3ff;
1668 uint32_t NewMask = (CLHS->
getZExtValue() | CRHS->getZExtValue()) & MaxMask;
1678 DAGCombinerInfo &DCI)
const {
1683 if (
const ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(Mask)) {
1684 if (CMask->isNullValue())
1711 DAGCombinerInfo &DCI)
const {
1747 DAGCombinerInfo &DCI)
const {
1786 return performSetCCCombine(N, DCI);
1796 return performMin3Max3Combine(N, DCI);
1809 APInt KnownZero, KnownOne;
1813 if (TLO.ShrinkDemandedConstant(Src, Demanded) ||
1814 TLI.SimplifyDemandedBits(Src, Demanded, KnownZero, KnownOne, TLO)) {
1822 return performUCharToFloatCombine(N, DCI);
1932 SDValue NewPtr = performSHLPtrCombine(Ptr.getNode(), AS, DCI);
1943 return performAndCombine(N, DCI);
1945 return performOrCombine(N, DCI);
1947 return performClassCombine(N, DCI);
1965 uint64_t Val = Node->getZExtValue();
1973 if (Node->getValueType(0) ==
MVT::f32)
1974 return FloatToBits(Node->getValueAPF().convertToFloat());
1986 case AMDGPU::sub0:
return 0;
1987 case AMDGPU::sub1:
return 1;
1988 case AMDGPU::sub2:
return 2;
1989 case AMDGPU::sub3:
return 3;
1994 void SITargetLowering::adjustWritemask(
MachineSDNode *&Node,
1999 unsigned NewDmask = 0;
2006 if (!I->isMachineOpcode() ||
2018 for (
unsigned i = 0, Dmask = OldDmask; i <= Lane; i++) {
2021 Dmask &= ~(1 << Comp);
2029 NewDmask |= 1 << Comp;
2033 if (NewDmask == OldDmask)
2037 std::vector<SDValue> Ops;
2044 if (NewDmask && (NewDmask & (NewDmask-1)) == 0) {
2055 for (
unsigned i = 0, Idx = AMDGPU::sub0; i < 4; ++i) {
2066 case AMDGPU::sub0: Idx = AMDGPU::sub1;
break;
2067 case AMDGPU::sub1: Idx = AMDGPU::sub2;
break;
2068 case AMDGPU::sub2: Idx = AMDGPU::sub3;
break;
2077 return isa<FrameIndexSDNode>(Op);
2109 adjustWritemask(Node, DAG);
2132 unsigned BitsSet = 0;
2133 for (
unsigned i = 0; i < 4; ++i)
2134 BitsSet += Writemask & (1 << i) ? 1 : 0;
2139 case 1: RC = &AMDGPU::VGPR_32RegClass;
break;
2140 case 2: RC = &AMDGPU::VReg_64RegClass;
break;
2141 case 3: RC = &AMDGPU::VReg_96RegClass;
break;
2145 MI->
setDesc(TII->get(NewOpcode));
2152 if (NoRetAtomicOp != -1) {
2154 MI->
setDesc(TII->get(NoRetAtomicOp));
2221 uint32_t RsrcDword1,
2222 uint64_t RsrcDword2And3)
const {
2232 RsrcDword2And3 & UINT64_C(0xFFFFFFFF));
2258 return buildRSRC(DAG, DL, Ptr, 0, Rsrc);
2263 unsigned Reg,
EVT VT)
const {
2267 cast<RegisterSDNode>(VReg)->getReg(), VT);
2274 std::pair<unsigned, const TargetRegisterClass *>
2278 if (Constraint ==
"r") {
2282 return std::make_pair(0U, &AMDGPU::SGPR_64RegClass);
2284 return std::make_pair(0U, &AMDGPU::SGPR_32RegClass);
2288 if (Constraint.
size() > 1) {
2290 if (Constraint[1] ==
'v') {
2291 RC = &AMDGPU::VGPR_32RegClass;
2292 }
else if (Constraint[1] ==
's') {
2293 RC = &AMDGPU::SGPR_32RegClass;
2299 if (!Failed && Idx < RC->getNumRegs())
SDValue getTruncStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT TVT, bool isNonTemporal, bool isVolatile, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes())
bool isUInt< 8 >(uint64_t x)
std::enable_if< std::numeric_limits< T >::is_signed, bool >::type getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
static MVT getIntegerVT(unsigned BitWidth)
void push_back(const T &Elt)
BUILTIN_OP_END - This must be the last enum value in this list.
The memory access reads data.
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
A parsed version of the target data layout string in and methods for querying it. ...
Interface definition for SIRegisterInfo.
void AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const override
Assign the register class depending on the number of bits set in the writemask.
SDValue getValue(unsigned R) const
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
The memory access writes data.
int getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const
Given a MIMG Opcode that writes all 4 channels, return the equivalent opcode that writes Channels Cha...
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
unsigned getPhysRegSubReg(unsigned Reg, const TargetRegisterClass *SubRC, unsigned Channel) const
Channel This is the register channel (e.g.
CombineLevel getDAGCombineLevel()
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant, which is required to be operand #1) half of the integer or float value specified as operand #0.
bool isFMAFasterThanFMulAndFAdd(EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
LLVMContext * getContext() const
SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N)
AMDGPU specific subclass of TargetSubtarget.
uint64_t getZExtValue() const
Get zero extended value.
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
size_t size() const
size - Get the string size.
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an vector value) starting with the ...
unsigned getRegister(unsigned i) const
getRegister - Return the specified register in the class.
void legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const
Legalize target independent instructions (e.g.
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
void AnalyzeFormalArguments(CCState &State, const SmallVectorImpl< ISD::InputArg > &Ins) const
const TargetMachine & getTargetMachine() const
SDVTList getVTList() const
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, SelectionDAG &DAG) const
SDValue getMergeValues(ArrayRef< SDValue > Ops, SDLoc dl)
Create a MERGE_VALUES node from the given operands.
Carry-setting nodes for multiple precision addition and subtraction.
const TargetMachine & getTarget() const
unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
bool hasFastFMAF32() const
const GlobalValue * getGlobal() const
static PointerType * get(Type *ElementType, unsigned AddressSpace)
PointerType::get - This constructs a pointer to an object of the specified type in a numbered address...
float BitsToFloat(uint32_t Bits)
BitsToFloat - This function takes a 32-bit integer and returns the bit equivalent float...
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Type * getTypeForEVT(LLVMContext &Context) const
getTypeForEVT - This method returns an LLVM type corresponding to the specified EVT.
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
const_iterator begin(StringRef path)
Get begin iterator over path.
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
unsigned getNumOperands() const
Return the number of values used by this operation.
const SDValue & getOperand(unsigned Num) const
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
unsigned getAddressSpace() const
Return the address space of the Pointer type.
Address space for local memory.
[US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned integers.
iv Induction Variable Users
INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector with VECTOR2 inserted into VECTOR1 at the ...
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, unsigned f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
getMachineMemOperand - Allocate a new MachineMemOperand.
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
bool bitsLT(EVT VT) const
bitsLT - Return true if this has less bits than VT.
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
MachineSDNode * buildScratchRSRC(SelectionDAG &DAG, SDLoc DL, SDValue Ptr) const
A convenience struct that encapsulates a DAG, and two SDValues for returning information from TargetL...
bool isVector() const
isVector - Return true if this is a vector value type.
bool isNegative() const
Return true if the value is negative.
MachineMemOperand - A description of a memory reference used in the backend.
Pointer to the start of the shader's constant data.
const HexagonInstrInfo * TII
MachineSDNode * buildRSRC(SelectionDAG &DAG, SDLoc DL, SDValue Ptr, uint32_t RsrcDword1, uint64_t RsrcDword2And3) const
Return a resource descriptor with the 'Add TID' bit enabled The TID (Thread ID) is multipled by the s...
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
Shift and rotation operations.
unsigned getShaderType() const
SDValue ScalarizeVectorStore(SDValue Op, SelectionDAG &DAG) const
Split a vector store into a scalar store of each component.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
int getAtomicNoRetOp(uint16_t Opcode)
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
MachineFunction & getMachineFunction() const
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
int32_t analyzeImmediate(const SDNode *N) const
Analyze the possible immediate value Op.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
static unsigned SubIdx2Lane(unsigned Idx)
Helper function for adjustWritemask.
SDValue getTargetGlobalAddress(const GlobalValue *GV, SDLoc DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
CopyToReg - This node has three operands: a chain, a register number to set to this value...
virtual SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const
Helper function that adds Reg to the LiveIn list of the DAG's MachineFunction.
unsigned getAddressSpace() const
const AMDGPUInstrInfo * getInstrInfo() const override
Reg
All possible values of the reg field in the ModR/M byte.
EVT getScalarType() const
getScalarType - If this is a vector type, return the element type, otherwise return this...
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) For double-word atomic operations: ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi) ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi) These correspond to the atomicrmw instruction.
Number of individual test Apply this number of consecutive mutations to each input exit after the first new interesting input is found the minimized corpus is saved into the first input directory Number of jobs to run If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
unsigned getStoreSize() const
getStoreSize - Return the number of bytes overwritten by a store of the specified value type...
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
EVT getVectorElementType() const
getVectorElementType - Given a vector type, return the type of each element.
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
bool isShuffleMaskLegal(const SmallVectorImpl< int > &, EVT) const override
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks.
unsigned getLocReg() const
FunctionType - Class to represent function types.
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
const AMDGPUSubtarget * Subtarget
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
SDValue getTargetFrameIndex(int FI, EVT VT)
Simple integer binary arithmetic operators.
bool enableAggressiveFMAFusion(EVT VT) const override
Return true if target always beneficiates from combining into FMA for a given value type...
static unsigned minMaxOpcToMin3Max3Opc(unsigned Opc)
const SDValue & getBasePtr() const
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
static mvt_range integer_vector_valuetypes()
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
const APInt & getAPIntValue() const
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
EVT getMemoryVT() const
Return the type of the in-memory value.
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
Generation getGeneration() const
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
const DataLayout & getDataLayout() const
bool bitsLE(EVT VT) const
bitsLE - Return true if this has no more bits than VT.
PointerType - Class to represent pointers.
This class is used to represent ISD::STORE nodes.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Address space for region memory.
uint32_t FloatToBits(float Float)
FloatToBits - This function takes a float and returns the bit equivalent 32-bit integer.
const MachineBasicBlock * getParent() const
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable...
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Get a value with high bits set.
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const override
Helper function that adds Reg to the LiveIn list of the DAG's MachineFunction.
bundle_iterator< MachineInstr, instr_iterator > iterator
A self-contained host- and target-independent arbitrary-precision floating-point software implementat...
unsigned getStoreSize() const
getStoreSize - Return the number of bytes overwritten by a store of the specified value type...
Type * getParamType(unsigned i) const
Parameter type accessors.
bool isNormalLoad(const SDNode *N)
Returns true if the specified node is a non-extending and unindexed load.
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
unsigned UnsafeFPMath
UnsafeFPMath - This flag is enabled when the -enable-unsafe-fp-math flag is specified on the command ...
static bool canFoldOffset(unsigned OffsetSize, unsigned AS, const AMDGPUSubtarget &STI)
Return true if the given offset Size in bytes can be folded into the immediate offsets of a memory in...
Control flow instructions. These all have token chains.
const SDValue & getBasePtr() const
std::size_t countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the least significant bit to the most stopping at the first 1...
unsigned getVectorNumElements() const
MVT - Machine Value Type.
const SDValue & getOperand(unsigned i) const
The instances of the Type class are immutable: once they are created, they are never changed...
This is an important class for using LLVM in a threaded context.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
Address space for constant memory.
Simple binary floating point operators.
void setTargetDAGCombine(ISD::NodeType NT)
Targets should invoke this method for each target independent node that they want to provide a custom...
Address space for private memory.
SDNode * PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override
Fold the instructions after selecting them.
bool isVector() const
isVector - Return true if this is a vector value type.
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL...
const MachineOperand & getOperand(unsigned i) const
bool isBeforeLegalizeOps() const
Carry-using nodes for multiple precision addition and subtraction.
unsigned getLiveInVirtReg(unsigned PReg) const
getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in physical ...
EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, MachineFunction &MF) const override
Returns the target specific optimal type for load and store operations as a result of memset...
INSERT_SUBREG - This instruction takes three operands: a register that has subregisters, a register providing an insert value, and a subregister index.
MachineSDNode * wrapAddr64Rsrc(SelectionDAG &DAG, SDLoc DL, SDValue Ptr) const
unsigned getPreloadedValue(const MachineFunction &MF, enum PreloadedValue Value) const
Returns the physical register that Value is stored in.
SI DAG Lowering interface definition.
static mvt_range fp_valuetypes()
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
SITargetLowering(TargetMachine &tm, const AMDGPUSubtarget &STI)
This class provides iterator support for SDUse operands that use a specific SDNode.
SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT)
SDValue getSExtOrTrunc(SDValue Op, SDLoc DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either sign-extending or trunca...
bool isBeforeLegalize() const
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang","erlang-compatible garbage collector")
SDValue getTargetConstant(uint64_t Val, SDLoc DL, EVT VT, bool isOpaque=false)
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
unsigned getOpcode() const
bool hasFP32Denormals() const
uint64_t getDefaultRsrcDataFormat() const
SDValue ScalarizeVectorLoad(SDValue Op, SelectionDAG &DAG) const
Split a vector load into a scalar load of each component.
use_iterator use_begin() const
Provide iteration support to walk over all uses of an SDNode.
Address space for flat memory.
const SDValue & getValue() const
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
SDValue getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes())
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo...
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth=0) const
Return true if 'Op & Mask' is known to be zero.
void append(in_iter in_start, in_iter in_end)
Add the specified range to the end of the SmallVector.
EVT - Extended Value Type.
static UndefValue * get(Type *T)
get() - Static factory methods - Return an 'undef' object of the specified type.
const APFloat & getValueAPF() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements)
getVectorVT - Returns the EVT that represents a vector NumElements in length, where each element is o...
MachinePointerInfo - This class contains a discriminated union of information about pointers in memor...
uint64_t getConstantOperandVal(unsigned Num) const
Helper method returns the integer value of a ConstantSDNode operand.
static SDValue buildSMovImm32(SelectionDAG &DAG, SDLoc DL, uint64_t Val)
The memory access is invariant.
unsigned getExplicitKernelArgOffset() const
Returns the offset in bytes from the start of the input buffer of the first explicit kernel argument...
const uint64_t RSRC_TID_ENABLE
REG_SEQUENCE - This variadic instruction is used to form a register that represents a consecutive seq...
bool isInlineConstant(const APInt &Imm) const
bool bitsGT(EVT VT) const
bitsGT - Return true if this has more bits than VT.
TokenFactor - This node takes multiple tokens as input and produces a single token result...
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
unsigned getABITypeAlignment(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
virtual MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
EXTRACT_SUBREG - This instruction takes two operands: a register that has subregisters, and a subregister index.
CCState - This class holds information needed while lowering arguments and return values...
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT) const override
Return the preferred vector type legalization action.
bool enableHugeScratchBuffer() const
bool isInfinity() const
Return true if the value is an infinity.
bool isNegative() const
IEEE-754R isSignMinus: Returns true if and only if the current value is negative. ...
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
unsigned getVectorNumElements() const
SDNode * UpdateNodeOperands(SDNode *N, SDValue Op)
Mutate the specified node in-place to have the specified operands.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
CCValAssign - Represent assignment of one arg/retval to a location.
static EVT toIntegerVT(EVT VT)
BRCOND - Conditional branch.
An SDNode that represents everything that will be needed to construct a MachineInstr.
const SDValue & getChain() const
bool isMIMG(uint16_t Opcode) const
Byte Swap and Counting operators.
FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions and truncation for half-preci...
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
This is an abstract virtual class for memory operations.
SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
void ExtractVectorElements(SDValue Op, SmallVectorImpl< SDValue > &Args, unsigned Start=0, unsigned Count=0)
Append the extracted elements from Start to Count out of the vector Op in Args.
Represents one node in the SelectionDAG.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
static SDNode * findUser(SDValue Value, unsigned Opcode)
Helper function for LowerBRCOND.
static mvt_range integer_valuetypes()
Target - Wrapper for Target specific information.
Class for arbitrary precision integers.
bool isUInt< 32 >(uint64_t x)
Select(COND, TRUEVAL, FALSEVAL).
Interface for the AMDGPU Implementation of the Intrinsic Info class.
op_iterator op_begin() const
static use_iterator use_end()
AddrMode
ARM Addressing Modes.
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
static EVT getEquivalentLoadRegType(LLVMContext &Context, EVT VT)
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT) const
Return the preferred vector type legalization action.
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align, bool *IsFast) const override
Determine if the target supports unaligned memory accesses.
static APInt getBitsSet(unsigned numBits, unsigned loBit, unsigned hiBit)
Get a value with a block of bits set.
unsigned getAddressSpace() const
Return the address space for the associated pointer.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
Interface definition for SIInstrInfo.
Bitwise operators - logical and, logical or, logical xor.
bool hasAnyUseOfValue(unsigned Value) const
Return true if there are any use of the indicated value.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
unsigned ABIArgOffset
Start of implicit kernel args.
void legalizeOperands(MachineInstr *MI) const
Legalize all operands in this instruction.
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, SDLoc DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array...
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
void ReplaceAllUsesWith(SDValue From, SDValue Op)
Modify anything using 'From' to use 'To' instead.
COPY_TO_REGCLASS - This instruction is a placeholder for a plain register-to-register copy into a spe...
FunctionType * getFunctionType() const
unsigned ScratchOffsetReg
op_iterator op_end() const
MachineSDNode * getMachineNode(unsigned Opcode, SDLoc dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s), MachineInstr opcode, and operands.
EVT getValueType() const
Return the ValueType of the referenced return value.
static bool isFrameIndexOp(SDValue Op)
SDValue getConstant(uint64_t Val, SDLoc DL, EVT VT, bool isTarget=false, bool isOpaque=false)
void getOriginalFunctionArgs(SelectionDAG &DAG, const Function *F, const SmallVectorImpl< ISD::InputArg > &Ins, SmallVectorImpl< ISD::InputArg > &OrigIns) const
The SelectionDAGBuilder will automatically promote function arguments with illegal types...
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
unsigned getReg() const
getReg - Returns the register number.
SDValue getSelect(SDLoc DL, EVT VT, SDValue Cond, SDValue LHS, SDValue RHS)
Helper function to make it easier to build Select's if you just have operands and don't want to check...
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
bool isSimple() const
isSimple - Test if the given EVT is simple (as opposed to being extended).
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
SDValue getTargetExtractSubreg(int SRIdx, SDLoc DL, EVT VT, SDValue Operand)
A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG nodes.
LLVM Value Representation.
FMA - Perform a * b + c with no intermediate rounding step.
SDValue getRegister(unsigned Reg, EVT VT)
SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, SDLoc DL, SDValue V) const
SDValue getValueType(EVT)
bool isUInt< 16 >(uint64_t x)
bool isInfinity() const
IEEE-754R isInfinite(): Returns true if and only if the float is infinity.
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
const TargetLowering & getTargetLoweringInfo() const
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
void ReplaceAllUsesOfValueWith(SDValue From, SDValue To)
Replace any uses of From with To, leaving uses of other values produced by From.Val alone...
static EVT getEquivalentMemType(LLVMContext &Context, EVT VT)
Primary interface to the complete machine description for the target machine.
C - The default llvm calling convention, compatible with C.
void setRegClass(unsigned Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
StringRef - Represent a constant reference to a string, i.e.
FMAD - Perform a * b + c, while getting the same result as the separately rounded operations...
SetCC operator - This evaluates to a true value iff the condition is true.
unsigned getImplicitParameterOffset(const AMDGPUMachineFunction *MFI, const ImplicitParameter Param) const
Helper function that returns the byte offset of the given type of implicit parameter.
SDValue getConstantFP(double Val, SDLoc DL, EVT VT, bool isTarget=false)
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml","ocaml 3.10-compatible collector")
SDValue getSetCC(SDLoc DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
unsigned getLocMemOffset() const
MVT getVectorElementType() const
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val) This corresponds to "store atomic" instruction.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2, FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR - Perform various unary floating point operations.
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
getIntegerVT - Returns the EVT that represents an integer with the given number of bits...
Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) This corresponds to "load atomic" instruction.
EVT changeVectorElementTypeToInteger() const
changeVectorElementTypeToInteger - Return a vector with the same number of elements as this vector...
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Return true if it is beneficial to convert a load of a constant to just the constant itself...
MVT getSimpleVT() const
getSimpleVT - Return the SimpleValueType held in the specified simple EVT.
SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const
SDValue getMemIntrinsicNode(unsigned Opcode, SDLoc dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, unsigned Align=0, bool Vol=false, bool ReadMem=true, bool WriteMem=true, unsigned Size=0)
Creates a MemIntrinsicNode that may produce a result and takes a list of operands.
void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO)
unsigned getMachineOpcode() const
This may only be called if isMachineOpcode returns true.
const AMDGPURegisterInfo * getRegisterInfo() const override
Address space for global memory (RAT0, VTX0).
uint64_t getZExtValue() const
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
unsigned getVectorNumElements() const
getVectorNumElements - Given a vector type, return the number of elements it contains.
This class is used to represent ISD::LOAD nodes.