LLVM  3.7.0
PPCFrameLowering.cpp
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1 //===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the PPC implementation of TargetFrameLowering class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCFrameLowering.h"
15 #include "PPCInstrBuilder.h"
16 #include "PPCInstrInfo.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCSubtarget.h"
19 #include "PPCTargetMachine.h"
26 #include "llvm/IR/Function.h"
28 
29 using namespace llvm;
30 
31 /// VRRegNo - Map from a numbered VR register to its enum value.
32 ///
33 static const uint16_t VRRegNo[] = {
34  PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
35  PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
36  PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
37  PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
38 };
39 
40 static unsigned computeReturnSaveOffset(const PPCSubtarget &STI) {
41  if (STI.isDarwinABI())
42  return STI.isPPC64() ? 16 : 8;
43  // SVR4 ABI:
44  return STI.isPPC64() ? 16 : 4;
45 }
46 
47 static unsigned computeTOCSaveOffset(const PPCSubtarget &STI) {
48  return STI.isELFv2ABI() ? 24 : 40;
49 }
50 
51 static unsigned computeFramePointerSaveOffset(const PPCSubtarget &STI) {
52  // For the Darwin ABI:
53  // We cannot use the TOC save slot (offset +20) in the PowerPC linkage area
54  // for saving the frame pointer (if needed.) While the published ABI has
55  // not used this slot since at least MacOSX 10.2, there is older code
56  // around that does use it, and that needs to continue to work.
57  if (STI.isDarwinABI())
58  return STI.isPPC64() ? -8U : -4U;
59 
60  // SVR4 ABI: First slot in the general register save area.
61  return STI.isPPC64() ? -8U : -4U;
62 }
63 
64 static unsigned computeLinkageSize(const PPCSubtarget &STI) {
65  if (STI.isDarwinABI() || STI.isPPC64())
66  return (STI.isELFv2ABI() ? 4 : 6) * (STI.isPPC64() ? 8 : 4);
67 
68  // SVR4 ABI:
69  return 8;
70 }
71 
72 static unsigned computeBasePointerSaveOffset(const PPCSubtarget &STI) {
73  if (STI.isDarwinABI())
74  return STI.isPPC64() ? -16U : -8U;
75 
76  // SVR4 ABI: First slot in the general register save area.
77  return STI.isPPC64()
78  ? -16U
80  ? -12U
81  : -8U;
82 }
83 
85  : TargetFrameLowering(TargetFrameLowering::StackGrowsDown,
86  STI.getPlatformStackAlignment(), 0),
87  Subtarget(STI), ReturnSaveOffset(computeReturnSaveOffset(Subtarget)),
88  TOCSaveOffset(computeTOCSaveOffset(Subtarget)),
89  FramePointerSaveOffset(computeFramePointerSaveOffset(Subtarget)),
90  LinkageSize(computeLinkageSize(Subtarget)),
91  BasePointerSaveOffset(computeBasePointerSaveOffset(STI)) {}
92 
93 // With the SVR4 ABI, callee-saved registers have fixed offsets on the stack.
95  unsigned &NumEntries) const {
96  if (Subtarget.isDarwinABI()) {
97  NumEntries = 1;
98  if (Subtarget.isPPC64()) {
99  static const SpillSlot darwin64Offsets = {PPC::X31, -8};
100  return &darwin64Offsets;
101  } else {
102  static const SpillSlot darwinOffsets = {PPC::R31, -4};
103  return &darwinOffsets;
104  }
105  }
106 
107  // Early exit if not using the SVR4 ABI.
108  if (!Subtarget.isSVR4ABI()) {
109  NumEntries = 0;
110  return nullptr;
111  }
112 
113  // Note that the offsets here overlap, but this is fixed up in
114  // processFunctionBeforeFrameFinalized.
115 
116  static const SpillSlot Offsets[] = {
117  // Floating-point register save area offsets.
118  {PPC::F31, -8},
119  {PPC::F30, -16},
120  {PPC::F29, -24},
121  {PPC::F28, -32},
122  {PPC::F27, -40},
123  {PPC::F26, -48},
124  {PPC::F25, -56},
125  {PPC::F24, -64},
126  {PPC::F23, -72},
127  {PPC::F22, -80},
128  {PPC::F21, -88},
129  {PPC::F20, -96},
130  {PPC::F19, -104},
131  {PPC::F18, -112},
132  {PPC::F17, -120},
133  {PPC::F16, -128},
134  {PPC::F15, -136},
135  {PPC::F14, -144},
136 
137  // General register save area offsets.
138  {PPC::R31, -4},
139  {PPC::R30, -8},
140  {PPC::R29, -12},
141  {PPC::R28, -16},
142  {PPC::R27, -20},
143  {PPC::R26, -24},
144  {PPC::R25, -28},
145  {PPC::R24, -32},
146  {PPC::R23, -36},
147  {PPC::R22, -40},
148  {PPC::R21, -44},
149  {PPC::R20, -48},
150  {PPC::R19, -52},
151  {PPC::R18, -56},
152  {PPC::R17, -60},
153  {PPC::R16, -64},
154  {PPC::R15, -68},
155  {PPC::R14, -72},
156 
157  // CR save area offset. We map each of the nonvolatile CR fields
158  // to the slot for CR2, which is the first of the nonvolatile CR
159  // fields to be assigned, so that we only allocate one save slot.
160  // See PPCRegisterInfo::hasReservedSpillSlot() for more information.
161  {PPC::CR2, -4},
162 
163  // VRSAVE save area offset.
164  {PPC::VRSAVE, -4},
165 
166  // Vector register save area
167  {PPC::V31, -16},
168  {PPC::V30, -32},
169  {PPC::V29, -48},
170  {PPC::V28, -64},
171  {PPC::V27, -80},
172  {PPC::V26, -96},
173  {PPC::V25, -112},
174  {PPC::V24, -128},
175  {PPC::V23, -144},
176  {PPC::V22, -160},
177  {PPC::V21, -176},
178  {PPC::V20, -192}};
179 
180  static const SpillSlot Offsets64[] = {
181  // Floating-point register save area offsets.
182  {PPC::F31, -8},
183  {PPC::F30, -16},
184  {PPC::F29, -24},
185  {PPC::F28, -32},
186  {PPC::F27, -40},
187  {PPC::F26, -48},
188  {PPC::F25, -56},
189  {PPC::F24, -64},
190  {PPC::F23, -72},
191  {PPC::F22, -80},
192  {PPC::F21, -88},
193  {PPC::F20, -96},
194  {PPC::F19, -104},
195  {PPC::F18, -112},
196  {PPC::F17, -120},
197  {PPC::F16, -128},
198  {PPC::F15, -136},
199  {PPC::F14, -144},
200 
201  // General register save area offsets.
202  {PPC::X31, -8},
203  {PPC::X30, -16},
204  {PPC::X29, -24},
205  {PPC::X28, -32},
206  {PPC::X27, -40},
207  {PPC::X26, -48},
208  {PPC::X25, -56},
209  {PPC::X24, -64},
210  {PPC::X23, -72},
211  {PPC::X22, -80},
212  {PPC::X21, -88},
213  {PPC::X20, -96},
214  {PPC::X19, -104},
215  {PPC::X18, -112},
216  {PPC::X17, -120},
217  {PPC::X16, -128},
218  {PPC::X15, -136},
219  {PPC::X14, -144},
220 
221  // VRSAVE save area offset.
222  {PPC::VRSAVE, -4},
223 
224  // Vector register save area
225  {PPC::V31, -16},
226  {PPC::V30, -32},
227  {PPC::V29, -48},
228  {PPC::V28, -64},
229  {PPC::V27, -80},
230  {PPC::V26, -96},
231  {PPC::V25, -112},
232  {PPC::V24, -128},
233  {PPC::V23, -144},
234  {PPC::V22, -160},
235  {PPC::V21, -176},
236  {PPC::V20, -192}};
237 
238  if (Subtarget.isPPC64()) {
239  NumEntries = array_lengthof(Offsets64);
240 
241  return Offsets64;
242  } else {
243  NumEntries = array_lengthof(Offsets);
244 
245  return Offsets;
246  }
247 }
248 
249 /// RemoveVRSaveCode - We have found that this function does not need any code
250 /// to manipulate the VRSAVE register, even though it uses vector registers.
251 /// This can happen when the only registers used are known to be live in or out
252 /// of the function. Remove all of the VRSAVE related code from the function.
253 /// FIXME: The removal of the code results in a compile failure at -O0 when the
254 /// function contains a function call, as the GPR containing original VRSAVE
255 /// contents is spilled and reloaded around the call. Without the prolog code,
256 /// the spill instruction refers to an undefined register. This code needs
257 /// to account for all uses of that GPR.
259  MachineBasicBlock *Entry = MI->getParent();
260  MachineFunction *MF = Entry->getParent();
261 
262  // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
264  ++MBBI;
265  assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
266  MBBI->eraseFromParent();
267 
268  bool RemovedAllMTVRSAVEs = true;
269  // See if we can find and remove the MTVRSAVE instruction from all of the
270  // epilog blocks.
271  for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
272  // If last instruction is a return instruction, add an epilogue
273  if (!I->empty() && I->back().isReturn()) {
274  bool FoundIt = false;
275  for (MBBI = I->end(); MBBI != I->begin(); ) {
276  --MBBI;
277  if (MBBI->getOpcode() == PPC::MTVRSAVE) {
278  MBBI->eraseFromParent(); // remove it.
279  FoundIt = true;
280  break;
281  }
282  }
283  RemovedAllMTVRSAVEs &= FoundIt;
284  }
285  }
286 
287  // If we found and removed all MTVRSAVE instructions, remove the read of
288  // VRSAVE as well.
289  if (RemovedAllMTVRSAVEs) {
290  MBBI = MI;
291  assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
292  --MBBI;
293  assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
294  MBBI->eraseFromParent();
295  }
296 
297  // Finally, nuke the UPDATE_VRSAVE.
298  MI->eraseFromParent();
299 }
300 
301 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
302 // instruction selector. Based on the vector registers that have been used,
303 // transform this into the appropriate ORI instruction.
305  MachineFunction *MF = MI->getParent()->getParent();
306  const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
307  DebugLoc dl = MI->getDebugLoc();
308 
309  unsigned UsedRegMask = 0;
310  for (unsigned i = 0; i != 32; ++i)
311  if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
312  UsedRegMask |= 1 << (31-i);
313 
314  // Live in and live out values already must be in the mask, so don't bother
315  // marking them.
317  I = MF->getRegInfo().livein_begin(),
318  E = MF->getRegInfo().livein_end(); I != E; ++I) {
319  unsigned RegNo = TRI->getEncodingValue(I->first);
320  if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
321  UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
322  }
323 
324  // Live out registers appear as use operands on return instructions.
325  for (MachineFunction::const_iterator BI = MF->begin(), BE = MF->end();
326  UsedRegMask != 0 && BI != BE; ++BI) {
327  const MachineBasicBlock &MBB = *BI;
328  if (MBB.empty() || !MBB.back().isReturn())
329  continue;
330  const MachineInstr &Ret = MBB.back();
331  for (unsigned I = 0, E = Ret.getNumOperands(); I != E; ++I) {
332  const MachineOperand &MO = Ret.getOperand(I);
333  if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg()))
334  continue;
335  unsigned RegNo = TRI->getEncodingValue(MO.getReg());
336  UsedRegMask &= ~(1 << (31-RegNo));
337  }
338  }
339 
340  // If no registers are used, turn this into a copy.
341  if (UsedRegMask == 0) {
342  // Remove all VRSAVE code.
343  RemoveVRSaveCode(MI);
344  return;
345  }
346 
347  unsigned SrcReg = MI->getOperand(1).getReg();
348  unsigned DstReg = MI->getOperand(0).getReg();
349 
350  if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
351  if (DstReg != SrcReg)
352  BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
353  .addReg(SrcReg)
354  .addImm(UsedRegMask);
355  else
356  BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
357  .addReg(SrcReg, RegState::Kill)
358  .addImm(UsedRegMask);
359  } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
360  if (DstReg != SrcReg)
361  BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
362  .addReg(SrcReg)
363  .addImm(UsedRegMask >> 16);
364  else
365  BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
366  .addReg(SrcReg, RegState::Kill)
367  .addImm(UsedRegMask >> 16);
368  } else {
369  if (DstReg != SrcReg)
370  BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
371  .addReg(SrcReg)
372  .addImm(UsedRegMask >> 16);
373  else
374  BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
375  .addReg(SrcReg, RegState::Kill)
376  .addImm(UsedRegMask >> 16);
377 
378  BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
379  .addReg(DstReg, RegState::Kill)
380  .addImm(UsedRegMask & 0xFFFF);
381  }
382 
383  // Remove the old UPDATE_VRSAVE instruction.
384  MI->eraseFromParent();
385 }
386 
387 static bool spillsCR(const MachineFunction &MF) {
388  const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
389  return FuncInfo->isCRSpilled();
390 }
391 
392 static bool spillsVRSAVE(const MachineFunction &MF) {
393  const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
394  return FuncInfo->isVRSAVESpilled();
395 }
396 
397 static bool hasSpills(const MachineFunction &MF) {
398  const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
399  return FuncInfo->hasSpills();
400 }
401 
402 static bool hasNonRISpills(const MachineFunction &MF) {
403  const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
404  return FuncInfo->hasNonRISpills();
405 }
406 
407 /// MustSaveLR - Return true if this function requires that we save the LR
408 /// register onto the stack in the prolog and restore it in the epilog of the
409 /// function.
410 static bool MustSaveLR(const MachineFunction &MF, unsigned LR) {
411  const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
412 
413  // We need a save/restore of LR if there is any def of LR (which is
414  // defined by calls, including the PIC setup sequence), or if there is
415  // some use of the LR stack slot (e.g. for builtin_return_address).
416  // (LR comes in 32 and 64 bit versions.)
418  return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired();
419 }
420 
421 /// determineFrameLayout - Determine the size of the frame and maximum call
422 /// frame size.
424  bool UpdateMF,
425  bool UseEstimate) const {
426  MachineFrameInfo *MFI = MF.getFrameInfo();
427 
428  // Get the number of bytes to allocate from the FrameInfo
429  unsigned FrameSize =
430  UseEstimate ? MFI->estimateStackSize(MF) : MFI->getStackSize();
431 
432  // Get stack alignments. The frame must be aligned to the greatest of these:
433  unsigned TargetAlign = getStackAlignment(); // alignment required per the ABI
434  unsigned MaxAlign = MFI->getMaxAlignment(); // algmt required by data in frame
435  unsigned AlignMask = std::max(MaxAlign, TargetAlign) - 1;
436 
437  const PPCRegisterInfo *RegInfo =
438  static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
439 
440  // If we are a leaf function, and use up to 224 bytes of stack space,
441  // don't have a frame pointer, calls, or dynamic alloca then we do not need
442  // to adjust the stack pointer (we fit in the Red Zone).
443  // The 32-bit SVR4 ABI has no Red Zone. However, it can still generate
444  // stackless code if all local vars are reg-allocated.
445  bool DisableRedZone = MF.getFunction()->hasFnAttribute(Attribute::NoRedZone);
446  unsigned LR = RegInfo->getRARegister();
447  if (!DisableRedZone &&
448  (Subtarget.isPPC64() || // 32-bit SVR4, no stack-
449  !Subtarget.isSVR4ABI() || // allocated locals.
450  FrameSize == 0) &&
451  FrameSize <= 224 && // Fits in red zone.
452  !MFI->hasVarSizedObjects() && // No dynamic alloca.
453  !MFI->adjustsStack() && // No calls.
454  !MustSaveLR(MF, LR) &&
455  !RegInfo->hasBasePointer(MF)) { // No special alignment.
456  // No need for frame
457  if (UpdateMF)
458  MFI->setStackSize(0);
459  return 0;
460  }
461 
462  // Get the maximum call frame size of all the calls.
463  unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
464 
465  // Maximum call frame needs to be at least big enough for linkage area.
466  unsigned minCallFrameSize = getLinkageSize();
467  maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
468 
469  // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
470  // that allocations will be aligned.
471  if (MFI->hasVarSizedObjects())
472  maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
473 
474  // Update maximum call frame size.
475  if (UpdateMF)
476  MFI->setMaxCallFrameSize(maxCallFrameSize);
477 
478  // Include call frame size in total.
479  FrameSize += maxCallFrameSize;
480 
481  // Make sure the frame is aligned.
482  FrameSize = (FrameSize + AlignMask) & ~AlignMask;
483 
484  // Update frame info.
485  if (UpdateMF)
486  MFI->setStackSize(FrameSize);
487 
488  return FrameSize;
489 }
490 
491 // hasFP - Return true if the specified function actually has a dedicated frame
492 // pointer register.
494  const MachineFrameInfo *MFI = MF.getFrameInfo();
495  // FIXME: This is pretty much broken by design: hasFP() might be called really
496  // early, before the stack layout was calculated and thus hasFP() might return
497  // true or false here depending on the time of call.
498  return (MFI->getStackSize()) && needsFP(MF);
499 }
500 
501 // needsFP - Return true if the specified function should have a dedicated frame
502 // pointer register. This is true if the function has variable sized allocas or
503 // if frame pointer elimination is disabled.
505  const MachineFrameInfo *MFI = MF.getFrameInfo();
506 
507  // Naked functions have no stack frame pushed, so we don't have a frame
508  // pointer.
510  return false;
511 
512  return MF.getTarget().Options.DisableFramePointerElim(MF) ||
513  MFI->hasVarSizedObjects() ||
514  MFI->hasStackMap() || MFI->hasPatchPoint() ||
516  MF.getInfo<PPCFunctionInfo>()->hasFastCall());
517 }
518 
520  bool is31 = needsFP(MF);
521  unsigned FPReg = is31 ? PPC::R31 : PPC::R1;
522  unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1;
523 
524  const PPCRegisterInfo *RegInfo =
525  static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
526  bool HasBP = RegInfo->hasBasePointer(MF);
527  unsigned BPReg = HasBP ? (unsigned) RegInfo->getBaseRegister(MF) : FPReg;
528  unsigned BP8Reg = HasBP ? (unsigned) PPC::X30 : FPReg;
529 
530  for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
531  BI != BE; ++BI)
532  for (MachineBasicBlock::iterator MBBI = BI->end(); MBBI != BI->begin(); ) {
533  --MBBI;
534  for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
535  MachineOperand &MO = MBBI->getOperand(I);
536  if (!MO.isReg())
537  continue;
538 
539  switch (MO.getReg()) {
540  case PPC::FP:
541  MO.setReg(FPReg);
542  break;
543  case PPC::FP8:
544  MO.setReg(FP8Reg);
545  break;
546  case PPC::BP:
547  MO.setReg(BPReg);
548  break;
549  case PPC::BP8:
550  MO.setReg(BP8Reg);
551  break;
552 
553  }
554  }
555  }
556 }
557 
559  MachineBasicBlock &MBB) const {
560  assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
561  MachineBasicBlock::iterator MBBI = MBB.begin();
562  MachineFrameInfo *MFI = MF.getFrameInfo();
563  const PPCInstrInfo &TII =
564  *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo());
565  const PPCRegisterInfo *RegInfo =
566  static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
567 
568  MachineModuleInfo &MMI = MF.getMMI();
569  const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
570  DebugLoc dl;
571  bool needsCFI = MMI.hasDebugInfo() ||
573 
574  // Get processor type.
575  bool isPPC64 = Subtarget.isPPC64();
576  // Get the ABI.
577  bool isSVR4ABI = Subtarget.isSVR4ABI();
578  bool isELFv2ABI = Subtarget.isELFv2ABI();
579  assert((Subtarget.isDarwinABI() || isSVR4ABI) &&
580  "Currently only Darwin and SVR4 ABIs are supported for PowerPC.");
581 
582  // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
583  // process it.
584  if (!isSVR4ABI)
585  for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
586  if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
587  HandleVRSaveUpdate(MBBI, TII);
588  break;
589  }
590  }
591 
592  // Move MBBI back to the beginning of the function.
593  MBBI = MBB.begin();
594 
595  // Work out frame sizes.
596  unsigned FrameSize = determineFrameLayout(MF);
597  int NegFrameSize = -FrameSize;
598  if (!isInt<32>(NegFrameSize))
599  llvm_unreachable("Unhandled stack size!");
600 
601  if (MFI->isFrameAddressTaken())
603 
604  // Check if the link register (LR) must be saved.
606  bool MustSaveLR = FI->mustSaveLR();
607  const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
608  // Do we have a frame pointer and/or base pointer for this function?
609  bool HasFP = hasFP(MF);
610  bool HasBP = RegInfo->hasBasePointer(MF);
611 
612  unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
613  unsigned BPReg = RegInfo->getBaseRegister(MF);
614  unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
615  unsigned LRReg = isPPC64 ? PPC::LR8 : PPC::LR;
616  unsigned ScratchReg = isPPC64 ? PPC::X0 : PPC::R0;
617  unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
618  // ...(R12/X12 is volatile in both Darwin & SVR4, & can't be a function arg.)
619  const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8
620  : PPC::MFLR );
621  const MCInstrDesc& StoreInst = TII.get(isPPC64 ? PPC::STD
622  : PPC::STW );
623  const MCInstrDesc& StoreUpdtInst = TII.get(isPPC64 ? PPC::STDU
624  : PPC::STWU );
625  const MCInstrDesc& StoreUpdtIdxInst = TII.get(isPPC64 ? PPC::STDUX
626  : PPC::STWUX);
627  const MCInstrDesc& LoadImmShiftedInst = TII.get(isPPC64 ? PPC::LIS8
628  : PPC::LIS );
629  const MCInstrDesc& OrImmInst = TII.get(isPPC64 ? PPC::ORI8
630  : PPC::ORI );
631  const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8
632  : PPC::OR );
633  const MCInstrDesc& SubtractCarryingInst = TII.get(isPPC64 ? PPC::SUBFC8
634  : PPC::SUBFC);
635  const MCInstrDesc& SubtractImmCarryingInst = TII.get(isPPC64 ? PPC::SUBFIC8
636  : PPC::SUBFIC);
637 
638  // Regarding this assert: Even though LR is saved in the caller's frame (i.e.,
639  // LROffset is positive), that slot is callee-owned. Because PPC32 SVR4 has no
640  // Red Zone, an asynchronous event (a form of "callee") could claim a frame &
641  // overwrite it, so PPC32 SVR4 must claim at least a minimal frame to save LR.
642  assert((isPPC64 || !isSVR4ABI || !(!FrameSize && (MustSaveLR || HasFP))) &&
643  "FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4.");
644 
645  int LROffset = getReturnSaveOffset();
646 
647  int FPOffset = 0;
648  if (HasFP) {
649  if (isSVR4ABI) {
650  MachineFrameInfo *FFI = MF.getFrameInfo();
651  int FPIndex = FI->getFramePointerSaveIndex();
652  assert(FPIndex && "No Frame Pointer Save Slot!");
653  FPOffset = FFI->getObjectOffset(FPIndex);
654  } else {
655  FPOffset = getFramePointerSaveOffset();
656  }
657  }
658 
659  int BPOffset = 0;
660  if (HasBP) {
661  if (isSVR4ABI) {
662  MachineFrameInfo *FFI = MF.getFrameInfo();
663  int BPIndex = FI->getBasePointerSaveIndex();
664  assert(BPIndex && "No Base Pointer Save Slot!");
665  BPOffset = FFI->getObjectOffset(BPIndex);
666  } else {
667  BPOffset = getBasePointerSaveOffset();
668  }
669  }
670 
671  int PBPOffset = 0;
672  if (FI->usesPICBase()) {
673  MachineFrameInfo *FFI = MF.getFrameInfo();
674  int PBPIndex = FI->getPICBasePointerSaveIndex();
675  assert(PBPIndex && "No PIC Base Pointer Save Slot!");
676  PBPOffset = FFI->getObjectOffset(PBPIndex);
677  }
678 
679  // Get stack alignments.
680  unsigned MaxAlign = MFI->getMaxAlignment();
681  if (HasBP && MaxAlign > 1)
682  assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
683  "Invalid alignment!");
684 
685  // Frames of 32KB & larger require special handling because they cannot be
686  // indexed into with a simple STDU/STWU/STD/STW immediate offset operand.
687  bool isLargeFrame = !isInt<16>(NegFrameSize);
688 
689  if (MustSaveLR)
690  BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg);
691 
692  assert((isPPC64 || MustSaveCRs.empty()) &&
693  "Prologue CR saving supported only in 64-bit mode");
694 
695  if (!MustSaveCRs.empty()) { // will only occur for PPC64
696  // FIXME: In the ELFv2 ABI, we are not required to save all CR fields.
697  // If only one or two CR fields are clobbered, it could be more
698  // efficient to use mfocrf to selectively save just those fields.
699  MachineInstrBuilder MIB =
700  BuildMI(MBB, MBBI, dl, TII.get(PPC::MFCR8), TempReg);
701  for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
702  MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill);
703  }
704 
705  if (HasFP)
706  // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
707  BuildMI(MBB, MBBI, dl, StoreInst)
708  .addReg(FPReg)
709  .addImm(FPOffset)
710  .addReg(SPReg);
711 
712  if (FI->usesPICBase())
713  // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
714  BuildMI(MBB, MBBI, dl, StoreInst)
715  .addReg(PPC::R30)
716  .addImm(PBPOffset)
717  .addReg(SPReg);
718 
719  if (HasBP)
720  // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
721  BuildMI(MBB, MBBI, dl, StoreInst)
722  .addReg(BPReg)
723  .addImm(BPOffset)
724  .addReg(SPReg);
725 
726  if (MustSaveLR)
727  // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
728  BuildMI(MBB, MBBI, dl, StoreInst)
729  .addReg(ScratchReg)
730  .addImm(LROffset)
731  .addReg(SPReg);
732 
733  if (!MustSaveCRs.empty()) // will only occur for PPC64
734  BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
735  .addReg(TempReg, getKillRegState(true))
736  .addImm(8)
737  .addReg(SPReg);
738 
739  // Skip the rest if this is a leaf function & all spills fit in the Red Zone.
740  if (!FrameSize) return;
741 
742  // Adjust stack pointer: r1 += NegFrameSize.
743  // If there is a preferred stack alignment, align R1 now
744 
745  if (HasBP) {
746  // Save a copy of r1 as the base pointer.
747  BuildMI(MBB, MBBI, dl, OrInst, BPReg)
748  .addReg(SPReg)
749  .addReg(SPReg);
750  }
751 
752  if (HasBP && MaxAlign > 1) {
753  if (isPPC64)
754  BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), ScratchReg)
755  .addReg(SPReg)
756  .addImm(0)
757  .addImm(64 - Log2_32(MaxAlign));
758  else // PPC32...
759  BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), ScratchReg)
760  .addReg(SPReg)
761  .addImm(0)
762  .addImm(32 - Log2_32(MaxAlign))
763  .addImm(31);
764  if (!isLargeFrame) {
765  BuildMI(MBB, MBBI, dl, SubtractImmCarryingInst, ScratchReg)
766  .addReg(ScratchReg, RegState::Kill)
767  .addImm(NegFrameSize);
768  } else {
769  BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, TempReg)
770  .addImm(NegFrameSize >> 16);
771  BuildMI(MBB, MBBI, dl, OrImmInst, TempReg)
772  .addReg(TempReg, RegState::Kill)
773  .addImm(NegFrameSize & 0xFFFF);
774  BuildMI(MBB, MBBI, dl, SubtractCarryingInst, ScratchReg)
775  .addReg(ScratchReg, RegState::Kill)
776  .addReg(TempReg, RegState::Kill);
777  }
778  BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
779  .addReg(SPReg, RegState::Kill)
780  .addReg(SPReg)
781  .addReg(ScratchReg);
782 
783  } else if (!isLargeFrame) {
784  BuildMI(MBB, MBBI, dl, StoreUpdtInst, SPReg)
785  .addReg(SPReg)
786  .addImm(NegFrameSize)
787  .addReg(SPReg);
788 
789  } else {
790  BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
791  .addImm(NegFrameSize >> 16);
792  BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
793  .addReg(ScratchReg, RegState::Kill)
794  .addImm(NegFrameSize & 0xFFFF);
795  BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
796  .addReg(SPReg, RegState::Kill)
797  .addReg(SPReg)
798  .addReg(ScratchReg);
799  }
800 
801  // Add Call Frame Information for the instructions we generated above.
802  if (needsCFI) {
803  unsigned CFIIndex;
804 
805  if (HasBP) {
806  // Define CFA in terms of BP. Do this in preference to using FP/SP,
807  // because if the stack needed aligning then CFA won't be at a fixed
808  // offset from FP/SP.
809  unsigned Reg = MRI->getDwarfRegNum(BPReg, true);
810  CFIIndex = MMI.addFrameInst(
812  } else {
813  // Adjust the definition of CFA to account for the change in SP.
814  assert(NegFrameSize);
815  CFIIndex = MMI.addFrameInst(
816  MCCFIInstruction::createDefCfaOffset(nullptr, NegFrameSize));
817  }
818  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
819  .addCFIIndex(CFIIndex);
820 
821  if (HasFP) {
822  // Describe where FP was saved, at a fixed offset from CFA.
823  unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
824  CFIIndex = MMI.addFrameInst(
825  MCCFIInstruction::createOffset(nullptr, Reg, FPOffset));
826  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
827  .addCFIIndex(CFIIndex);
828  }
829 
830  if (FI->usesPICBase()) {
831  // Describe where FP was saved, at a fixed offset from CFA.
832  unsigned Reg = MRI->getDwarfRegNum(PPC::R30, true);
833  CFIIndex = MMI.addFrameInst(
834  MCCFIInstruction::createOffset(nullptr, Reg, PBPOffset));
835  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
836  .addCFIIndex(CFIIndex);
837  }
838 
839  if (HasBP) {
840  // Describe where BP was saved, at a fixed offset from CFA.
841  unsigned Reg = MRI->getDwarfRegNum(BPReg, true);
842  CFIIndex = MMI.addFrameInst(
843  MCCFIInstruction::createOffset(nullptr, Reg, BPOffset));
844  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
845  .addCFIIndex(CFIIndex);
846  }
847 
848  if (MustSaveLR) {
849  // Describe where LR was saved, at a fixed offset from CFA.
850  unsigned Reg = MRI->getDwarfRegNum(LRReg, true);
851  CFIIndex = MMI.addFrameInst(
852  MCCFIInstruction::createOffset(nullptr, Reg, LROffset));
853  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
854  .addCFIIndex(CFIIndex);
855  }
856  }
857 
858  // If there is a frame pointer, copy R1 into R31
859  if (HasFP) {
860  BuildMI(MBB, MBBI, dl, OrInst, FPReg)
861  .addReg(SPReg)
862  .addReg(SPReg);
863 
864  if (!HasBP && needsCFI) {
865  // Change the definition of CFA from SP+offset to FP+offset, because SP
866  // will change at every alloca.
867  unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
868  unsigned CFIIndex = MMI.addFrameInst(
870 
871  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
872  .addCFIIndex(CFIIndex);
873  }
874  }
875 
876  if (needsCFI) {
877  // Describe where callee saved registers were saved, at fixed offsets from
878  // CFA.
879  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
880  for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
881  unsigned Reg = CSI[I].getReg();
882  if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue;
883 
884  // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just
885  // subregisters of CR2. We just need to emit a move of CR2.
886  if (PPC::CRBITRCRegClass.contains(Reg))
887  continue;
888 
889  // For SVR4, don't emit a move for the CR spill slot if we haven't
890  // spilled CRs.
891  if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4)
892  && MustSaveCRs.empty())
893  continue;
894 
895  // For 64-bit SVR4 when we have spilled CRs, the spill location
896  // is SP+8, not a frame-relative slot.
897  if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
898  // In the ELFv1 ABI, only CR2 is noted in CFI and stands in for
899  // the whole CR word. In the ELFv2 ABI, every CR that was
900  // actually saved gets its own CFI record.
901  unsigned CRReg = isELFv2ABI? Reg : (unsigned) PPC::CR2;
902  unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
903  nullptr, MRI->getDwarfRegNum(CRReg, true), 8));
904  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
905  .addCFIIndex(CFIIndex);
906  continue;
907  }
908 
909  int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
910  unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
911  nullptr, MRI->getDwarfRegNum(Reg, true), Offset));
912  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
913  .addCFIIndex(CFIIndex);
914  }
915  }
916 }
917 
919  MachineBasicBlock &MBB) const {
921  assert(MBBI != MBB.end() && "Returning block has no terminator");
922  const PPCInstrInfo &TII =
923  *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo());
924  const PPCRegisterInfo *RegInfo =
925  static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
926 
927  unsigned RetOpcode = MBBI->getOpcode();
928  DebugLoc dl;
929 
930  assert((RetOpcode == PPC::BLR ||
931  RetOpcode == PPC::BLR8 ||
932  RetOpcode == PPC::TCRETURNri ||
933  RetOpcode == PPC::TCRETURNdi ||
934  RetOpcode == PPC::TCRETURNai ||
935  RetOpcode == PPC::TCRETURNri8 ||
936  RetOpcode == PPC::TCRETURNdi8 ||
937  RetOpcode == PPC::TCRETURNai8) &&
938  "Can only insert epilog into returning blocks");
939 
940  // Get alignment info so we know how to restore the SP.
941  const MachineFrameInfo *MFI = MF.getFrameInfo();
942 
943  // Get the number of bytes allocated from the FrameInfo.
944  int FrameSize = MFI->getStackSize();
945 
946  // Get processor type.
947  bool isPPC64 = Subtarget.isPPC64();
948  // Get the ABI.
949  bool isSVR4ABI = Subtarget.isSVR4ABI();
950 
951  // Check if the link register (LR) has been saved.
953  bool MustSaveLR = FI->mustSaveLR();
954  const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
955  // Do we have a frame pointer and/or base pointer for this function?
956  bool HasFP = hasFP(MF);
957  bool HasBP = RegInfo->hasBasePointer(MF);
958 
959  unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
960  unsigned BPReg = RegInfo->getBaseRegister(MF);
961  unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
962  unsigned ScratchReg = isPPC64 ? PPC::X0 : PPC::R0;
963  unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
964  const MCInstrDesc& MTLRInst = TII.get( isPPC64 ? PPC::MTLR8
965  : PPC::MTLR );
966  const MCInstrDesc& LoadInst = TII.get( isPPC64 ? PPC::LD
967  : PPC::LWZ );
968  const MCInstrDesc& LoadImmShiftedInst = TII.get( isPPC64 ? PPC::LIS8
969  : PPC::LIS );
970  const MCInstrDesc& OrImmInst = TII.get( isPPC64 ? PPC::ORI8
971  : PPC::ORI );
972  const MCInstrDesc& AddImmInst = TII.get( isPPC64 ? PPC::ADDI8
973  : PPC::ADDI );
974  const MCInstrDesc& AddInst = TII.get( isPPC64 ? PPC::ADD8
975  : PPC::ADD4 );
976 
977  int LROffset = getReturnSaveOffset();
978 
979  int FPOffset = 0;
980  if (HasFP) {
981  if (isSVR4ABI) {
982  MachineFrameInfo *FFI = MF.getFrameInfo();
983  int FPIndex = FI->getFramePointerSaveIndex();
984  assert(FPIndex && "No Frame Pointer Save Slot!");
985  FPOffset = FFI->getObjectOffset(FPIndex);
986  } else {
987  FPOffset = getFramePointerSaveOffset();
988  }
989  }
990 
991  int BPOffset = 0;
992  if (HasBP) {
993  if (isSVR4ABI) {
994  MachineFrameInfo *FFI = MF.getFrameInfo();
995  int BPIndex = FI->getBasePointerSaveIndex();
996  assert(BPIndex && "No Base Pointer Save Slot!");
997  BPOffset = FFI->getObjectOffset(BPIndex);
998  } else {
999  BPOffset = getBasePointerSaveOffset();
1000  }
1001  }
1002 
1003  int PBPOffset = 0;
1004  if (FI->usesPICBase()) {
1005  MachineFrameInfo *FFI = MF.getFrameInfo();
1006  int PBPIndex = FI->getPICBasePointerSaveIndex();
1007  assert(PBPIndex && "No PIC Base Pointer Save Slot!");
1008  PBPOffset = FFI->getObjectOffset(PBPIndex);
1009  }
1010 
1011  bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
1012  RetOpcode == PPC::TCRETURNdi ||
1013  RetOpcode == PPC::TCRETURNai ||
1014  RetOpcode == PPC::TCRETURNri8 ||
1015  RetOpcode == PPC::TCRETURNdi8 ||
1016  RetOpcode == PPC::TCRETURNai8;
1017 
1018  if (UsesTCRet) {
1019  int MaxTCRetDelta = FI->getTailCallSPDelta();
1020  MachineOperand &StackAdjust = MBBI->getOperand(1);
1021  assert(StackAdjust.isImm() && "Expecting immediate value.");
1022  // Adjust stack pointer.
1023  int StackAdj = StackAdjust.getImm();
1024  int Delta = StackAdj - MaxTCRetDelta;
1025  assert((Delta >= 0) && "Delta must be positive");
1026  if (MaxTCRetDelta>0)
1027  FrameSize += (StackAdj +Delta);
1028  else
1029  FrameSize += StackAdj;
1030  }
1031 
1032  // Frames of 32KB & larger require special handling because they cannot be
1033  // indexed into with a simple LD/LWZ immediate offset operand.
1034  bool isLargeFrame = !isInt<16>(FrameSize);
1035 
1036  if (FrameSize) {
1037  // In the prologue, the loaded (or persistent) stack pointer value is offset
1038  // by the STDU/STDUX/STWU/STWUX instruction. Add this offset back now.
1039 
1040  // If this function contained a fastcc call and GuaranteedTailCallOpt is
1041  // enabled (=> hasFastCall()==true) the fastcc call might contain a tail
1042  // call which invalidates the stack pointer value in SP(0). So we use the
1043  // value of R31 in this case.
1044  if (FI->hasFastCall()) {
1045  assert(HasFP && "Expecting a valid frame pointer.");
1046  if (!isLargeFrame) {
1047  BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1048  .addReg(FPReg).addImm(FrameSize);
1049  } else {
1050  BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
1051  .addImm(FrameSize >> 16);
1052  BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
1053  .addReg(ScratchReg, RegState::Kill)
1054  .addImm(FrameSize & 0xFFFF);
1055  BuildMI(MBB, MBBI, dl, AddInst)
1056  .addReg(SPReg)
1057  .addReg(FPReg)
1058  .addReg(ScratchReg);
1059  }
1060  } else if (!isLargeFrame && !HasBP && !MFI->hasVarSizedObjects()) {
1061  BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1062  .addReg(SPReg)
1063  .addImm(FrameSize);
1064  } else {
1065  BuildMI(MBB, MBBI, dl, LoadInst, SPReg)
1066  .addImm(0)
1067  .addReg(SPReg);
1068  }
1069 
1070  }
1071 
1072  if (MustSaveLR)
1073  BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)
1074  .addImm(LROffset)
1075  .addReg(SPReg);
1076 
1077  assert((isPPC64 || MustSaveCRs.empty()) &&
1078  "Epilogue CR restoring supported only in 64-bit mode");
1079 
1080  if (!MustSaveCRs.empty()) // will only occur for PPC64
1081  BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
1082  .addImm(8)
1083  .addReg(SPReg);
1084 
1085  if (HasFP)
1086  BuildMI(MBB, MBBI, dl, LoadInst, FPReg)
1087  .addImm(FPOffset)
1088  .addReg(SPReg);
1089 
1090  if (FI->usesPICBase())
1091  // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
1092  BuildMI(MBB, MBBI, dl, LoadInst)
1093  .addReg(PPC::R30)
1094  .addImm(PBPOffset)
1095  .addReg(SPReg);
1096 
1097  if (HasBP)
1098  BuildMI(MBB, MBBI, dl, LoadInst, BPReg)
1099  .addImm(BPOffset)
1100  .addReg(SPReg);
1101 
1102  if (!MustSaveCRs.empty()) // will only occur for PPC64
1103  for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
1104  BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i])
1105  .addReg(TempReg, getKillRegState(i == e-1));
1106 
1107  if (MustSaveLR)
1108  BuildMI(MBB, MBBI, dl, MTLRInst).addReg(ScratchReg);
1109 
1110  // Callee pop calling convention. Pop parameter/linkage area. Used for tail
1111  // call optimization
1113  (RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8) &&
1116  unsigned CallerAllocatedAmt = FI->getMinReservedArea();
1117 
1118  if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) {
1119  BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1120  .addReg(SPReg).addImm(CallerAllocatedAmt);
1121  } else {
1122  BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
1123  .addImm(CallerAllocatedAmt >> 16);
1124  BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
1125  .addReg(ScratchReg, RegState::Kill)
1126  .addImm(CallerAllocatedAmt & 0xFFFF);
1127  BuildMI(MBB, MBBI, dl, AddInst)
1128  .addReg(SPReg)
1129  .addReg(FPReg)
1130  .addReg(ScratchReg);
1131  }
1132  } else if (RetOpcode == PPC::TCRETURNdi) {
1133  MBBI = MBB.getLastNonDebugInstr();
1134  MachineOperand &JumpTarget = MBBI->getOperand(0);
1135  BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).
1136  addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1137  } else if (RetOpcode == PPC::TCRETURNri) {
1138  MBBI = MBB.getLastNonDebugInstr();
1139  assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
1140  BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
1141  } else if (RetOpcode == PPC::TCRETURNai) {
1142  MBBI = MBB.getLastNonDebugInstr();
1143  MachineOperand &JumpTarget = MBBI->getOperand(0);
1144  BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
1145  } else if (RetOpcode == PPC::TCRETURNdi8) {
1146  MBBI = MBB.getLastNonDebugInstr();
1147  MachineOperand &JumpTarget = MBBI->getOperand(0);
1148  BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).
1149  addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1150  } else if (RetOpcode == PPC::TCRETURNri8) {
1151  MBBI = MBB.getLastNonDebugInstr();
1152  assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
1153  BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
1154  } else if (RetOpcode == PPC::TCRETURNai8) {
1155  MBBI = MBB.getLastNonDebugInstr();
1156  MachineOperand &JumpTarget = MBBI->getOperand(0);
1157  BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
1158  }
1159 }
1160 
1162  BitVector &SavedRegs,
1163  RegScavenger *RS) const {
1164  TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
1165 
1166  const PPCRegisterInfo *RegInfo =
1167  static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
1168 
1169  // Save and clear the LR state.
1171  unsigned LR = RegInfo->getRARegister();
1172  FI->setMustSaveLR(MustSaveLR(MF, LR));
1173  SavedRegs.reset(LR);
1174 
1175  // Save R31 if necessary
1176  int FPSI = FI->getFramePointerSaveIndex();
1177  bool isPPC64 = Subtarget.isPPC64();
1178  bool isDarwinABI = Subtarget.isDarwinABI();
1179  MachineFrameInfo *MFI = MF.getFrameInfo();
1180 
1181  // If the frame pointer save index hasn't been defined yet.
1182  if (!FPSI && needsFP(MF)) {
1183  // Find out what the fix offset of the frame pointer save area.
1184  int FPOffset = getFramePointerSaveOffset();
1185  // Allocate the frame index for frame pointer save area.
1186  FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
1187  // Save the result.
1188  FI->setFramePointerSaveIndex(FPSI);
1189  }
1190 
1191  int BPSI = FI->getBasePointerSaveIndex();
1192  if (!BPSI && RegInfo->hasBasePointer(MF)) {
1193  int BPOffset = getBasePointerSaveOffset();
1194  // Allocate the frame index for the base pointer save area.
1195  BPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, BPOffset, true);
1196  // Save the result.
1197  FI->setBasePointerSaveIndex(BPSI);
1198  }
1199 
1200  // Reserve stack space for the PIC Base register (R30).
1201  // Only used in SVR4 32-bit.
1202  if (FI->usesPICBase()) {
1203  int PBPSI = FI->getPICBasePointerSaveIndex();
1204  PBPSI = MFI->CreateFixedObject(4, -8, true);
1205  FI->setPICBasePointerSaveIndex(PBPSI);
1206  }
1207 
1208  // Reserve stack space to move the linkage area to in case of a tail call.
1209  int TCSPDelta = 0;
1211  (TCSPDelta = FI->getTailCallSPDelta()) < 0) {
1212  MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true);
1213  }
1214 
1215  // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the
1216  // function uses CR 2, 3, or 4.
1217  if (!isPPC64 && !isDarwinABI &&
1218  (SavedRegs.test(PPC::CR2) ||
1219  SavedRegs.test(PPC::CR3) ||
1220  SavedRegs.test(PPC::CR4))) {
1221  int FrameIdx = MFI->CreateFixedObject((uint64_t)4, (int64_t)-4, true);
1222  FI->setCRSpillFrameIndex(FrameIdx);
1223  }
1224 }
1225 
1227  RegScavenger *RS) const {
1228  // Early exit if not using the SVR4 ABI.
1229  if (!Subtarget.isSVR4ABI()) {
1230  addScavengingSpillSlot(MF, RS);
1231  return;
1232  }
1233 
1234  // Get callee saved register information.
1235  MachineFrameInfo *FFI = MF.getFrameInfo();
1236  const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo();
1237 
1238  // Early exit if no callee saved registers are modified!
1239  if (CSI.empty() && !needsFP(MF)) {
1240  addScavengingSpillSlot(MF, RS);
1241  return;
1242  }
1243 
1244  unsigned MinGPR = PPC::R31;
1245  unsigned MinG8R = PPC::X31;
1246  unsigned MinFPR = PPC::F31;
1247  unsigned MinVR = PPC::V31;
1248 
1249  bool HasGPSaveArea = false;
1250  bool HasG8SaveArea = false;
1251  bool HasFPSaveArea = false;
1252  bool HasVRSAVESaveArea = false;
1253  bool HasVRSaveArea = false;
1254 
1259 
1260  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1261  unsigned Reg = CSI[i].getReg();
1262  if (PPC::GPRCRegClass.contains(Reg)) {
1263  HasGPSaveArea = true;
1264 
1265  GPRegs.push_back(CSI[i]);
1266 
1267  if (Reg < MinGPR) {
1268  MinGPR = Reg;
1269  }
1270  } else if (PPC::G8RCRegClass.contains(Reg)) {
1271  HasG8SaveArea = true;
1272 
1273  G8Regs.push_back(CSI[i]);
1274 
1275  if (Reg < MinG8R) {
1276  MinG8R = Reg;
1277  }
1278  } else if (PPC::F8RCRegClass.contains(Reg)) {
1279  HasFPSaveArea = true;
1280 
1281  FPRegs.push_back(CSI[i]);
1282 
1283  if (Reg < MinFPR) {
1284  MinFPR = Reg;
1285  }
1286  } else if (PPC::CRBITRCRegClass.contains(Reg) ||
1287  PPC::CRRCRegClass.contains(Reg)) {
1288  ; // do nothing, as we already know whether CRs are spilled
1289  } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
1290  HasVRSAVESaveArea = true;
1291  } else if (PPC::VRRCRegClass.contains(Reg)) {
1292  HasVRSaveArea = true;
1293 
1294  VRegs.push_back(CSI[i]);
1295 
1296  if (Reg < MinVR) {
1297  MinVR = Reg;
1298  }
1299  } else {
1300  llvm_unreachable("Unknown RegisterClass!");
1301  }
1302  }
1303 
1305  const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1306 
1307  int64_t LowerBound = 0;
1308 
1309  // Take into account stack space reserved for tail calls.
1310  int TCSPDelta = 0;
1312  (TCSPDelta = PFI->getTailCallSPDelta()) < 0) {
1313  LowerBound = TCSPDelta;
1314  }
1315 
1316  // The Floating-point register save area is right below the back chain word
1317  // of the previous stack frame.
1318  if (HasFPSaveArea) {
1319  for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) {
1320  int FI = FPRegs[i].getFrameIdx();
1321 
1322  FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1323  }
1324 
1325  LowerBound -= (31 - TRI->getEncodingValue(MinFPR) + 1) * 8;
1326  }
1327 
1328  // Check whether the frame pointer register is allocated. If so, make sure it
1329  // is spilled to the correct offset.
1330  if (needsFP(MF)) {
1331  HasGPSaveArea = true;
1332 
1333  int FI = PFI->getFramePointerSaveIndex();
1334  assert(FI && "No Frame Pointer Save Slot!");
1335 
1336  FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1337  }
1338 
1339  if (PFI->usesPICBase()) {
1340  HasGPSaveArea = true;
1341 
1342  int FI = PFI->getPICBasePointerSaveIndex();
1343  assert(FI && "No PIC Base Pointer Save Slot!");
1344 
1345  FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1346  }
1347 
1348  const PPCRegisterInfo *RegInfo =
1349  static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
1350  if (RegInfo->hasBasePointer(MF)) {
1351  HasGPSaveArea = true;
1352 
1353  int FI = PFI->getBasePointerSaveIndex();
1354  assert(FI && "No Base Pointer Save Slot!");
1355 
1356  FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1357  }
1358 
1359  // General register save area starts right below the Floating-point
1360  // register save area.
1361  if (HasGPSaveArea || HasG8SaveArea) {
1362  // Move general register save area spill slots down, taking into account
1363  // the size of the Floating-point register save area.
1364  for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) {
1365  int FI = GPRegs[i].getFrameIdx();
1366 
1367  FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1368  }
1369 
1370  // Move general register save area spill slots down, taking into account
1371  // the size of the Floating-point register save area.
1372  for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) {
1373  int FI = G8Regs[i].getFrameIdx();
1374 
1375  FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1376  }
1377 
1378  unsigned MinReg =
1379  std::min<unsigned>(TRI->getEncodingValue(MinGPR),
1380  TRI->getEncodingValue(MinG8R));
1381 
1382  if (Subtarget.isPPC64()) {
1383  LowerBound -= (31 - MinReg + 1) * 8;
1384  } else {
1385  LowerBound -= (31 - MinReg + 1) * 4;
1386  }
1387  }
1388 
1389  // For 32-bit only, the CR save area is below the general register
1390  // save area. For 64-bit SVR4, the CR save area is addressed relative
1391  // to the stack pointer and hence does not need an adjustment here.
1392  // Only CR2 (the first nonvolatile spilled) has an associated frame
1393  // index so that we have a single uniform save area.
1394  if (spillsCR(MF) && !(Subtarget.isPPC64() && Subtarget.isSVR4ABI())) {
1395  // Adjust the frame index of the CR spill slot.
1396  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1397  unsigned Reg = CSI[i].getReg();
1398 
1399  if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2)
1400  // Leave Darwin logic as-is.
1401  || (!Subtarget.isSVR4ABI() &&
1402  (PPC::CRBITRCRegClass.contains(Reg) ||
1403  PPC::CRRCRegClass.contains(Reg)))) {
1404  int FI = CSI[i].getFrameIdx();
1405 
1406  FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1407  }
1408  }
1409 
1410  LowerBound -= 4; // The CR save area is always 4 bytes long.
1411  }
1412 
1413  if (HasVRSAVESaveArea) {
1414  // FIXME SVR4: Is it actually possible to have multiple elements in CSI
1415  // which have the VRSAVE register class?
1416  // Adjust the frame index of the VRSAVE spill slot.
1417  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1418  unsigned Reg = CSI[i].getReg();
1419 
1420  if (PPC::VRSAVERCRegClass.contains(Reg)) {
1421  int FI = CSI[i].getFrameIdx();
1422 
1423  FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1424  }
1425  }
1426 
1427  LowerBound -= 4; // The VRSAVE save area is always 4 bytes long.
1428  }
1429 
1430  if (HasVRSaveArea) {
1431  // Insert alignment padding, we need 16-byte alignment.
1432  LowerBound = (LowerBound - 15) & ~(15);
1433 
1434  for (unsigned i = 0, e = VRegs.size(); i != e; ++i) {
1435  int FI = VRegs[i].getFrameIdx();
1436 
1437  FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1438  }
1439  }
1440 
1441  addScavengingSpillSlot(MF, RS);
1442 }
1443 
1444 void
1446  RegScavenger *RS) const {
1447  // Reserve a slot closest to SP or frame pointer if we have a dynalloc or
1448  // a large stack, which will require scavenging a register to materialize a
1449  // large offset.
1450 
1451  // We need to have a scavenger spill slot for spills if the frame size is
1452  // large. In case there is no free register for large-offset addressing,
1453  // this slot is used for the necessary emergency spill. Also, we need the
1454  // slot for dynamic stack allocations.
1455 
1456  // The scavenger might be invoked if the frame offset does not fit into
1457  // the 16-bit immediate. We don't know the complete frame size here
1458  // because we've not yet computed callee-saved register spills or the
1459  // needed alignment padding.
1460  unsigned StackSize = determineFrameLayout(MF, false, true);
1461  MachineFrameInfo *MFI = MF.getFrameInfo();
1462  if (MFI->hasVarSizedObjects() || spillsCR(MF) || spillsVRSAVE(MF) ||
1463  hasNonRISpills(MF) || (hasSpills(MF) && !isInt<16>(StackSize))) {
1464  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
1465  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
1466  const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
1468  RC->getAlignment(),
1469  false));
1470 
1471  // Might we have over-aligned allocas?
1472  bool HasAlVars = MFI->hasVarSizedObjects() &&
1474 
1475  // These kinds of spills might need two registers.
1476  if (spillsCR(MF) || spillsVRSAVE(MF) || HasAlVars)
1478  RC->getAlignment(),
1479  false));
1480 
1481  }
1482 }
1483 
1484 bool
1487  const std::vector<CalleeSavedInfo> &CSI,
1488  const TargetRegisterInfo *TRI) const {
1489 
1490  // Currently, this function only handles SVR4 32- and 64-bit ABIs.
1491  // Return false otherwise to maintain pre-existing behavior.
1492  if (!Subtarget.isSVR4ABI())
1493  return false;
1494 
1495  MachineFunction *MF = MBB.getParent();
1496  const PPCInstrInfo &TII =
1497  *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo());
1498  DebugLoc DL;
1499  bool CRSpilled = false;
1500  MachineInstrBuilder CRMIB;
1501 
1502  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1503  unsigned Reg = CSI[i].getReg();
1504  // Only Darwin actually uses the VRSAVE register, but it can still appear
1505  // here if, for example, @llvm.eh.unwind.init() is used. If we're not on
1506  // Darwin, ignore it.
1507  if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
1508  continue;
1509 
1510  // CR2 through CR4 are the nonvolatile CR fields.
1511  bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4;
1512 
1513  // Add the callee-saved register as live-in; it's killed at the spill.
1514  MBB.addLiveIn(Reg);
1515 
1516  if (CRSpilled && IsCRField) {
1517  CRMIB.addReg(Reg, RegState::ImplicitKill);
1518  continue;
1519  }
1520 
1521  // Insert the spill to the stack frame.
1522  if (IsCRField) {
1523  PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
1524  if (Subtarget.isPPC64()) {
1525  // The actual spill will happen at the start of the prologue.
1526  FuncInfo->addMustSaveCR(Reg);
1527  } else {
1528  CRSpilled = true;
1529  FuncInfo->setSpillsCR();
1530 
1531  // 32-bit: FP-relative. Note that we made sure CR2-CR4 all have
1532  // the same frame index in PPCRegisterInfo::hasReservedSpillSlot.
1533  CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12)
1534  .addReg(Reg, RegState::ImplicitKill);
1535 
1536  MBB.insert(MI, CRMIB);
1537  MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW))
1538  .addReg(PPC::R12,
1539  getKillRegState(true)),
1540  CSI[i].getFrameIdx()));
1541  }
1542  } else {
1543  const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1544  TII.storeRegToStackSlot(MBB, MI, Reg, true,
1545  CSI[i].getFrameIdx(), RC, TRI);
1546  }
1547  }
1548  return true;
1549 }
1550 
1551 static void
1552 restoreCRs(bool isPPC64, bool is31,
1553  bool CR2Spilled, bool CR3Spilled, bool CR4Spilled,
1555  const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) {
1556 
1557  MachineFunction *MF = MBB.getParent();
1558  const PPCInstrInfo &TII = *MF->getSubtarget<PPCSubtarget>().getInstrInfo();
1559  DebugLoc DL;
1560  unsigned RestoreOp, MoveReg;
1561 
1562  if (isPPC64)
1563  // This is handled during epilogue generation.
1564  return;
1565  else {
1566  // 32-bit: FP-relative
1567  MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ),
1568  PPC::R12),
1569  CSI[CSIIndex].getFrameIdx()));
1570  RestoreOp = PPC::MTOCRF;
1571  MoveReg = PPC::R12;
1572  }
1573 
1574  if (CR2Spilled)
1575  MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2)
1576  .addReg(MoveReg, getKillRegState(!CR3Spilled && !CR4Spilled)));
1577 
1578  if (CR3Spilled)
1579  MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3)
1580  .addReg(MoveReg, getKillRegState(!CR4Spilled)));
1581 
1582  if (CR4Spilled)
1583  MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4)
1584  .addReg(MoveReg, getKillRegState(true)));
1585 }
1586 
1587 void PPCFrameLowering::
1590  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1592  I->getOpcode() == PPC::ADJCALLSTACKUP) {
1593  // Add (actually subtract) back the amount the callee popped on return.
1594  if (int CalleeAmt = I->getOperand(1).getImm()) {
1595  bool is64Bit = Subtarget.isPPC64();
1596  CalleeAmt *= -1;
1597  unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1;
1598  unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0;
1599  unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI;
1600  unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4;
1601  unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;
1602  unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
1603  MachineInstr *MI = I;
1604  DebugLoc dl = MI->getDebugLoc();
1605 
1606  if (isInt<16>(CalleeAmt)) {
1607  BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg)
1608  .addReg(StackReg, RegState::Kill)
1609  .addImm(CalleeAmt);
1610  } else {
1612  BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
1613  .addImm(CalleeAmt >> 16);
1614  BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
1615  .addReg(TmpReg, RegState::Kill)
1616  .addImm(CalleeAmt & 0xFFFF);
1617  BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg)
1618  .addReg(StackReg, RegState::Kill)
1619  .addReg(TmpReg);
1620  }
1621  }
1622  }
1623  // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
1624  MBB.erase(I);
1625 }
1626 
1627 bool
1630  const std::vector<CalleeSavedInfo> &CSI,
1631  const TargetRegisterInfo *TRI) const {
1632 
1633  // Currently, this function only handles SVR4 32- and 64-bit ABIs.
1634  // Return false otherwise to maintain pre-existing behavior.
1635  if (!Subtarget.isSVR4ABI())
1636  return false;
1637 
1638  MachineFunction *MF = MBB.getParent();
1639  const PPCInstrInfo &TII =
1640  *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo());
1641  bool CR2Spilled = false;
1642  bool CR3Spilled = false;
1643  bool CR4Spilled = false;
1644  unsigned CSIIndex = 0;
1645 
1646  // Initialize insertion-point logic; we will be restoring in reverse
1647  // order of spill.
1648  MachineBasicBlock::iterator I = MI, BeforeI = I;
1649  bool AtStart = I == MBB.begin();
1650 
1651  if (!AtStart)
1652  --BeforeI;
1653 
1654  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1655  unsigned Reg = CSI[i].getReg();
1656 
1657  // Only Darwin actually uses the VRSAVE register, but it can still appear
1658  // here if, for example, @llvm.eh.unwind.init() is used. If we're not on
1659  // Darwin, ignore it.
1660  if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
1661  continue;
1662 
1663  if (Reg == PPC::CR2) {
1664  CR2Spilled = true;
1665  // The spill slot is associated only with CR2, which is the
1666  // first nonvolatile spilled. Save it here.
1667  CSIIndex = i;
1668  continue;
1669  } else if (Reg == PPC::CR3) {
1670  CR3Spilled = true;
1671  continue;
1672  } else if (Reg == PPC::CR4) {
1673  CR4Spilled = true;
1674  continue;
1675  } else {
1676  // When we first encounter a non-CR register after seeing at
1677  // least one CR register, restore all spilled CRs together.
1678  if ((CR2Spilled || CR3Spilled || CR4Spilled)
1679  && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
1680  bool is31 = needsFP(*MF);
1681  restoreCRs(Subtarget.isPPC64(), is31,
1682  CR2Spilled, CR3Spilled, CR4Spilled,
1683  MBB, I, CSI, CSIIndex);
1684  CR2Spilled = CR3Spilled = CR4Spilled = false;
1685  }
1686 
1687  // Default behavior for non-CR saves.
1688  const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1689  TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(),
1690  RC, TRI);
1691  assert(I != MBB.begin() &&
1692  "loadRegFromStackSlot didn't insert any code!");
1693  }
1694 
1695  // Insert in reverse order.
1696  if (AtStart)
1697  I = MBB.begin();
1698  else {
1699  I = BeforeI;
1700  ++I;
1701  }
1702  }
1703 
1704  // If we haven't yet spilled the CRs, do so now.
1705  if (CR2Spilled || CR3Spilled || CR4Spilled) {
1706  bool is31 = needsFP(*MF);
1707  restoreCRs(Subtarget.isPPC64(), is31, CR2Spilled, CR3Spilled, CR4Spilled,
1708  MBB, I, CSI, CSIIndex);
1709  }
1710 
1711  return true;
1712 }
void replaceFPWithRealFP(MachineFunction &MF) const
bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:276
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
int getDwarfRegNum(unsigned RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
const GlobalValue * getGlobal() const
const SpillSlot * getCalleeSavedSpillSlots(unsigned &NumEntries) const override
getCalleeSavedSpillSlots - This method returns a pointer to an array of pairs, that contains an entry...
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
static const unsigned GPRegs[]
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
livein_iterator livein_end() const
bool isDarwinABI() const
Definition: PPCSubtarget.h:268
const PPCTargetMachine & getTargetMachine() const
Definition: PPCSubtarget.h:173
void addMustSaveCR(unsigned Reg)
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:138
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
Definition: MCDwarf.h:381
static void RemoveVRSaveCode(MachineInstr *MI)
RemoveVRSaveCode - We have found that this function does not need any code to manipulate the VRSAVE r...
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
void addLiveIn(unsigned Reg)
Adds the specified register as a live in.
void setFramePointerSaveIndex(int Idx)
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:378
static unsigned computeTOCSaveOffset(const PPCSubtarget &STI)
static const MCPhysReg VRegs[32]
A debug info location.
Definition: DebugLoc.h:34
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
LoadInst - an instruction for reading from memory.
Definition: Instructions.h:177
void eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
eliminateCallFramePseudoInstr - This method is called during prolog/epilog code insertion to eliminat...
static MCCFIInstruction createDefCfaOffset(MCSymbol *L, int Offset)
.cfi_def_cfa_offset modifies a rule for computing CFA.
Definition: MCDwarf.h:368
Naked function.
Definition: Attributes.h:81
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:172
static void restoreCRs(bool isPPC64, bool is31, bool CR2Spilled, bool CR3Spilled, bool CR4Spilled, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI, unsigned CSIIndex)
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
unsigned getSize() const
getSize - Return the size of the register in bytes, which is also the size of a stack slot allocated ...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
DILocation * get() const
Get the underlying DILocation.
Definition: DebugLoc.cpp:22
const HexagonInstrInfo * TII
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
unsigned getMinReservedArea() const
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS=nullptr) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
bool hasDebugInfo() const
hasDebugInfo - Returns true if valid debug info is present.
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Definition: Value.cpp:317
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:271
unsigned getReturnSaveOffset() const
getReturnSaveOffset - Return the previous frame offset to save the return address.
static bool hasNonRISpills(const MachineFunction &MF)
const MachineBasicBlock & front() const
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
unsigned getBasePointerSaveOffset() const
getBasePointerSaveOffset - Return the previous frame offset to save the base pointer.
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Definition: SmallVector.h:57
static const uint16_t VRRegNo[]
VRRegNo - Map from a numbered VR register to its enum value.
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
unsigned LLVM_ATTRIBUTE_UNUSED_RESULT addFrameInst(const MCCFIInstruction &Inst)
iterator getLastNonDebugInstr()
getLastNonDebugInstr - returns an iterator to the last non-debug instruction in the basic block...
StoreInst - an instruction for storing to memory.
Definition: Instructions.h:316
int64_t getImm() const
const SmallVectorImpl< unsigned > & getMustSaveCRs() const
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
unsigned getKillRegState(bool B)
unsigned estimateStackSize(const MachineFunction &MF) const
Estimate and return the size of the stack frame.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:120
TargetInstrInfo - Interface to description of machine instruction set.
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:247
bool isELFv2ABI() const
bundle_iterator< MachineInstr, instr_iterator > iterator
bool hasStackMap() const
This method may be called any time after instruction selection is complete to determine if there is a...
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:399
static const unsigned G8Regs[]
unsigned getFramePointerSaveOffset() const
getFramePointerSaveOffset - Return the previous frame offset to save the frame pointer.
void addScavengingSpillSlot(MachineFunction &MF, RegScavenger *RS) const
unsigned getBaseRegister(const MachineFunction &MF) const
unsigned getAlignment() const
getAlignment - Return the minimum required alignment for a register of this class.
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register)
.cfi_def_cfa_register modifies a rule for computing CFA.
Definition: MCDwarf.h:361
void setStackSize(uint64_t Size)
Set the size of the stack.
static bool is64Bit(const char *name)
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
BitVector & reset()
Definition: BitVector.h:259
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
static unsigned computeReturnSaveOffset(const PPCSubtarget &STI)
unsigned GuaranteedTailCallOpt
GuaranteedTailCallOpt - This flag is enabled when -tailcallopt is specified on the commandline...
int64_t getOffset() const
Return the offset from the symbol in this operand.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool Immutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isSVR4ABI() const
Definition: PPCSubtarget.h:269
static unsigned computeBasePointerSaveOffset(const PPCSubtarget &STI)
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
const PPCRegisterInfo * getRegisterInfo() const override
Definition: PPCSubtarget.h:170
const MCContext & getContext() const
const PPCInstrInfo * getInstrInfo() const override
Definition: PPCSubtarget.h:163
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:861
bool test(unsigned Idx) const
Definition: BitVector.h:322
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call...
Information about stack frame layout on the target.
bool needsUnwindTableEntry() const
True if this function needs an unwind table.
Definition: Function.h:354
static bool spillsVRSAVE(const MachineFunction &MF)
livein_iterator livein_begin() const
static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII)
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static bool hasSpills(const MachineFunction &MF)
unsigned determineFrameLayout(MachineFunction &MF, bool UpdateMF=true, bool UseEstimate=false) const
determineFrameLayout - Determine the size of the frame and maximum call frame size.
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
unsigned Log2_32(uint32_t Value)
Log2_32 - This function returns the floor log base 2 of the specified value, -1 if the value is zero...
Definition: MathExtras.h:468
static bool spillsCR(const MachineFunction &MF)
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
getMinimalPhysRegClass - Returns the Register Class of a physical register of the given type...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:238
static bool MustSaveLR(const MachineFunction &MF, unsigned LR)
MustSaveLR - Return true if this function requires that we save the LR register onto the stack in the...
def_iterator def_begin(unsigned RegNo) const
bool needsFP(const MachineFunction &MF) const
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:227
void setPICBasePointerSaveIndex(int Idx)
Disable redzone.
Definition: Attributes.h:94
Representation of each machine instruction.
Definition: MachineInstr.h:51
bool hasPatchPoint() const
This method may be called any time after instruction selection is complete to determine if there is a...
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:217
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
PPCFrameLowering(const PPCSubtarget &STI)
void setReg(unsigned Reg)
Change the register this operand corresponds to.
#define I(x, y, z)
Definition: MD5.cpp:54
void setMaxCallFrameSize(unsigned S)
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:272
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
static unsigned computeFramePointerSaveOffset(const PPCSubtarget &STI)
int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSS, const AllocaInst *Alloca=nullptr)
Create a new statically sized stack object, returning a nonnegative identifier to represent it...
std::vector< std::pair< unsigned, unsigned > >::const_iterator livein_iterator
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
unsigned getReg() const
getReg - Returns the register number.
static def_iterator def_end()
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
bool isPhysRegUsed(unsigned Reg) const
isPhysRegUsed - Return true if the specified register is used in this function.
BasicBlockListType::iterator iterator
void setObjectOffset(int ObjectIdx, int64_t SPOffset)
Set the stack frame offset of the specified object.
bool isPowerOf2_32(uint32_t Value)
isPowerOf2_32 - This function returns true if the argument is a power of two > 0. ...
Definition: MathExtras.h:354
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
MachineModuleInfo & getMMI() const
unsigned getLinkageSize() const
getLinkageSize - Return the size of the PowerPC ABI linkage area.
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
bool hasBasePointer(const MachineFunction &MF) const
static unsigned computeLinkageSize(const PPCSubtarget &STI)
void setMustSaveLR(bool U)
MustSaveLR - This is set when the prolog/epilog inserter does its initial scan of the function...
MachineModuleInfo - This class contains meta information specific to a module.