LLVM  3.7.0
LegalizeVectorOps.cpp
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1 //===-- LegalizeVectorOps.cpp - Implement SelectionDAG::LegalizeVectors ---===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the SelectionDAG::LegalizeVectors method.
11 //
12 // The vector legalizer looks for vector operations which might need to be
13 // scalarized and legalizes them. This is a separate step from Legalize because
14 // scalarizing can introduce illegal types. For example, suppose we have an
15 // ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition
16 // on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the
17 // operation, which introduces nodes with the illegal type i64 which must be
18 // expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC;
19 // the operation must be unrolled, which introduces nodes with the illegal
20 // type i8 which must be promoted.
21 //
22 // This does not legalize vector manipulations like ISD::BUILD_VECTOR,
23 // or operations that happen to take a vector which are custom-lowered;
24 // the legalization for such operations never produces nodes
25 // with illegal types, so it's okay to put off legalizing them until
26 // SelectionDAG::Legalize runs.
27 //
28 //===----------------------------------------------------------------------===//
29 
32 using namespace llvm;
33 
34 namespace {
35 class VectorLegalizer {
36  SelectionDAG& DAG;
37  const TargetLowering &TLI;
38  bool Changed; // Keep track of whether anything changed
39 
40  /// For nodes that are of legal width, and that have more than one use, this
41  /// map indicates what regularized operand to use. This allows us to avoid
42  /// legalizing the same thing more than once.
44 
45  /// \brief Adds a node to the translation cache.
46  void AddLegalizedOperand(SDValue From, SDValue To) {
47  LegalizedNodes.insert(std::make_pair(From, To));
48  // If someone requests legalization of the new node, return itself.
49  if (From != To)
50  LegalizedNodes.insert(std::make_pair(To, To));
51  }
52 
53  /// \brief Legalizes the given node.
54  SDValue LegalizeOp(SDValue Op);
55 
56  /// \brief Assuming the node is legal, "legalize" the results.
57  SDValue TranslateLegalizeResults(SDValue Op, SDValue Result);
58 
59  /// \brief Implements unrolling a VSETCC.
60  SDValue UnrollVSETCC(SDValue Op);
61 
62  /// \brief Implement expand-based legalization of vector operations.
63  ///
64  /// This is just a high-level routine to dispatch to specific code paths for
65  /// operations to legalize them.
66  SDValue Expand(SDValue Op);
67 
68  /// \brief Implements expansion for FNEG; falls back to UnrollVectorOp if
69  /// FSUB isn't legal.
70  ///
71  /// Implements expansion for UINT_TO_FLOAT; falls back to UnrollVectorOp if
72  /// SINT_TO_FLOAT and SHR on vectors isn't legal.
73  SDValue ExpandUINT_TO_FLOAT(SDValue Op);
74 
75  /// \brief Implement expansion for SIGN_EXTEND_INREG using SRL and SRA.
76  SDValue ExpandSEXTINREG(SDValue Op);
77 
78  /// \brief Implement expansion for ANY_EXTEND_VECTOR_INREG.
79  ///
80  /// Shuffles the low lanes of the operand into place and bitcasts to the proper
81  /// type. The contents of the bits in the extended part of each element are
82  /// undef.
83  SDValue ExpandANY_EXTEND_VECTOR_INREG(SDValue Op);
84 
85  /// \brief Implement expansion for SIGN_EXTEND_VECTOR_INREG.
86  ///
87  /// Shuffles the low lanes of the operand into place, bitcasts to the proper
88  /// type, then shifts left and arithmetic shifts right to introduce a sign
89  /// extension.
90  SDValue ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op);
91 
92  /// \brief Implement expansion for ZERO_EXTEND_VECTOR_INREG.
93  ///
94  /// Shuffles the low lanes of the operand into place and blends zeros into
95  /// the remaining lanes, finally bitcasting to the proper type.
96  SDValue ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op);
97 
98  /// \brief Expand bswap of vectors into a shuffle if legal.
99  SDValue ExpandBSWAP(SDValue Op);
100 
101  /// \brief Implement vselect in terms of XOR, AND, OR when blend is not
102  /// supported by the target.
103  SDValue ExpandVSELECT(SDValue Op);
104  SDValue ExpandSELECT(SDValue Op);
105  SDValue ExpandLoad(SDValue Op);
106  SDValue ExpandStore(SDValue Op);
107  SDValue ExpandFNEG(SDValue Op);
108 
109  /// \brief Implements vector promotion.
110  ///
111  /// This is essentially just bitcasting the operands to a different type and
112  /// bitcasting the result back to the original type.
113  SDValue Promote(SDValue Op);
114 
115  /// \brief Implements [SU]INT_TO_FP vector promotion.
116  ///
117  /// This is a [zs]ext of the input operand to the next size up.
118  SDValue PromoteINT_TO_FP(SDValue Op);
119 
120  /// \brief Implements FP_TO_[SU]INT vector promotion of the result type.
121  ///
122  /// It is promoted to the next size up integer type. The result is then
123  /// truncated back to the original type.
124  SDValue PromoteFP_TO_INT(SDValue Op, bool isSigned);
125 
126 public:
127  /// \brief Begin legalizer the vector operations in the DAG.
128  bool Run();
129  VectorLegalizer(SelectionDAG& dag) :
130  DAG(dag), TLI(dag.getTargetLoweringInfo()), Changed(false) {}
131 };
132 
133 bool VectorLegalizer::Run() {
134  // Before we start legalizing vector nodes, check if there are any vectors.
135  bool HasVectors = false;
136  for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
137  E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I) {
138  // Check if the values of the nodes contain vectors. We don't need to check
139  // the operands because we are going to check their values at some point.
140  for (SDNode::value_iterator J = I->value_begin(), E = I->value_end();
141  J != E; ++J)
142  HasVectors |= J->isVector();
143 
144  // If we found a vector node we can start the legalization.
145  if (HasVectors)
146  break;
147  }
148 
149  // If this basic block has no vectors then no need to legalize vectors.
150  if (!HasVectors)
151  return false;
152 
153  // The legalize process is inherently a bottom-up recursive process (users
154  // legalize their uses before themselves). Given infinite stack space, we
155  // could just start legalizing on the root and traverse the whole graph. In
156  // practice however, this causes us to run out of stack space on large basic
157  // blocks. To avoid this problem, compute an ordering of the nodes where each
158  // node is only legalized after all of its operands are legalized.
159  DAG.AssignTopologicalOrder();
160  for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
161  E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I)
162  LegalizeOp(SDValue(I, 0));
163 
164  // Finally, it's possible the root changed. Get the new root.
165  SDValue OldRoot = DAG.getRoot();
166  assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
167  DAG.setRoot(LegalizedNodes[OldRoot]);
168 
169  LegalizedNodes.clear();
170 
171  // Remove dead nodes now.
172  DAG.RemoveDeadNodes();
173 
174  return Changed;
175 }
176 
177 SDValue VectorLegalizer::TranslateLegalizeResults(SDValue Op, SDValue Result) {
178  // Generic legalization: just pass the operand through.
179  for (unsigned i = 0, e = Op.getNode()->getNumValues(); i != e; ++i)
180  AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
181  return Result.getValue(Op.getResNo());
182 }
183 
184 SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
185  // Note that LegalizeOp may be reentered even from single-use nodes, which
186  // means that we always must cache transformed nodes.
187  DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
188  if (I != LegalizedNodes.end()) return I->second;
189 
190  SDNode* Node = Op.getNode();
191 
192  // Legalize the operands
194  for (const SDValue &Op : Node->op_values())
195  Ops.push_back(LegalizeOp(Op));
196 
197  SDValue Result = SDValue(DAG.UpdateNodeOperands(Op.getNode(), Ops), 0);
198 
199  bool HasVectorValue = false;
200  if (Op.getOpcode() == ISD::LOAD) {
201  LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
202  ISD::LoadExtType ExtType = LD->getExtensionType();
203  if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD)
204  switch (TLI.getLoadExtAction(LD->getExtensionType(), LD->getValueType(0),
205  LD->getMemoryVT())) {
206  default: llvm_unreachable("This action is not supported yet!");
208  return TranslateLegalizeResults(Op, Result);
210  if (SDValue Lowered = TLI.LowerOperation(Result, DAG)) {
211  if (Lowered == Result)
212  return TranslateLegalizeResults(Op, Lowered);
213  Changed = true;
214  if (Lowered->getNumValues() != Op->getNumValues()) {
215  // This expanded to something other than the load. Assume the
216  // lowering code took care of any chain values, and just handle the
217  // returned value.
218  assert(Result.getValue(1).use_empty() &&
219  "There are still live users of the old chain!");
220  return LegalizeOp(Lowered);
221  } else {
222  return TranslateLegalizeResults(Op, Lowered);
223  }
224  }
226  Changed = true;
227  return LegalizeOp(ExpandLoad(Op));
228  }
229  } else if (Op.getOpcode() == ISD::STORE) {
230  StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
231  EVT StVT = ST->getMemoryVT();
232  MVT ValVT = ST->getValue().getSimpleValueType();
233  if (StVT.isVector() && ST->isTruncatingStore())
234  switch (TLI.getTruncStoreAction(ValVT, StVT.getSimpleVT())) {
235  default: llvm_unreachable("This action is not supported yet!");
237  return TranslateLegalizeResults(Op, Result);
238  case TargetLowering::Custom: {
239  SDValue Lowered = TLI.LowerOperation(Result, DAG);
240  Changed = Lowered != Result;
241  return TranslateLegalizeResults(Op, Lowered);
242  }
244  Changed = true;
245  return LegalizeOp(ExpandStore(Op));
246  }
247  } else if (Op.getOpcode() == ISD::MSCATTER)
248  HasVectorValue = true;
249 
250  for (SDNode::value_iterator J = Node->value_begin(), E = Node->value_end();
251  J != E;
252  ++J)
253  HasVectorValue |= J->isVector();
254  if (!HasVectorValue)
255  return TranslateLegalizeResults(Op, Result);
256 
257  EVT QueryType;
258  switch (Op.getOpcode()) {
259  default:
260  return TranslateLegalizeResults(Op, Result);
261  case ISD::ADD:
262  case ISD::SUB:
263  case ISD::MUL:
264  case ISD::SDIV:
265  case ISD::UDIV:
266  case ISD::SREM:
267  case ISD::UREM:
268  case ISD::FADD:
269  case ISD::FSUB:
270  case ISD::FMUL:
271  case ISD::FDIV:
272  case ISD::FREM:
273  case ISD::AND:
274  case ISD::OR:
275  case ISD::XOR:
276  case ISD::SHL:
277  case ISD::SRA:
278  case ISD::SRL:
279  case ISD::ROTL:
280  case ISD::ROTR:
281  case ISD::BSWAP:
282  case ISD::CTLZ:
283  case ISD::CTTZ:
286  case ISD::CTPOP:
287  case ISD::SELECT:
288  case ISD::VSELECT:
289  case ISD::SELECT_CC:
290  case ISD::SETCC:
291  case ISD::ZERO_EXTEND:
292  case ISD::ANY_EXTEND:
293  case ISD::TRUNCATE:
294  case ISD::SIGN_EXTEND:
295  case ISD::FP_TO_SINT:
296  case ISD::FP_TO_UINT:
297  case ISD::FNEG:
298  case ISD::FABS:
299  case ISD::FMINNUM:
300  case ISD::FMAXNUM:
301  case ISD::FCOPYSIGN:
302  case ISD::FSQRT:
303  case ISD::FSIN:
304  case ISD::FCOS:
305  case ISD::FPOWI:
306  case ISD::FPOW:
307  case ISD::FLOG:
308  case ISD::FLOG2:
309  case ISD::FLOG10:
310  case ISD::FEXP:
311  case ISD::FEXP2:
312  case ISD::FCEIL:
313  case ISD::FTRUNC:
314  case ISD::FRINT:
315  case ISD::FNEARBYINT:
316  case ISD::FROUND:
317  case ISD::FFLOOR:
318  case ISD::FP_ROUND:
319  case ISD::FP_EXTEND:
320  case ISD::FMA:
325  case ISD::SMIN:
326  case ISD::SMAX:
327  case ISD::UMIN:
328  case ISD::UMAX:
329  QueryType = Node->getValueType(0);
330  break;
331  case ISD::FP_ROUND_INREG:
332  QueryType = cast<VTSDNode>(Node->getOperand(1))->getVT();
333  break;
334  case ISD::SINT_TO_FP:
335  case ISD::UINT_TO_FP:
336  QueryType = Node->getOperand(0).getValueType();
337  break;
338  case ISD::MSCATTER:
339  QueryType = cast<MaskedScatterSDNode>(Node)->getValue().getValueType();
340  break;
341  }
342 
343  switch (TLI.getOperationAction(Node->getOpcode(), QueryType)) {
345  Result = Promote(Op);
346  Changed = true;
347  break;
349  break;
350  case TargetLowering::Custom: {
351  SDValue Tmp1 = TLI.LowerOperation(Op, DAG);
352  if (Tmp1.getNode()) {
353  Result = Tmp1;
354  break;
355  }
356  // FALL THROUGH
357  }
359  Result = Expand(Op);
360  }
361 
362  // Make sure that the generated code is itself legal.
363  if (Result != Op) {
364  Result = LegalizeOp(Result);
365  Changed = true;
366  }
367 
368  // Note that LegalizeOp may be reentered even from single-use nodes, which
369  // means that we always must cache transformed nodes.
370  AddLegalizedOperand(Op, Result);
371  return Result;
372 }
373 
374 SDValue VectorLegalizer::Promote(SDValue Op) {
375  // For a few operations there is a specific concept for promotion based on
376  // the operand's type.
377  switch (Op.getOpcode()) {
378  case ISD::SINT_TO_FP:
379  case ISD::UINT_TO_FP:
380  // "Promote" the operation by extending the operand.
381  return PromoteINT_TO_FP(Op);
382  case ISD::FP_TO_UINT:
383  case ISD::FP_TO_SINT:
384  // Promote the operation by extending the operand.
385  return PromoteFP_TO_INT(Op, Op->getOpcode() == ISD::FP_TO_SINT);
386  }
387 
388  // There are currently two cases of vector promotion:
389  // 1) Bitcasting a vector of integers to a different type to a vector of the
390  // same overall length. For example, x86 promotes ISD::AND v2i32 to v1i64.
391  // 2) Extending a vector of floats to a vector of the same number of larger
392  // floats. For example, AArch64 promotes ISD::FADD on v4f16 to v4f32.
393  MVT VT = Op.getSimpleValueType();
394  assert(Op.getNode()->getNumValues() == 1 &&
395  "Can't promote a vector with multiple results!");
396  MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
397  SDLoc dl(Op);
399 
400  for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
401  if (Op.getOperand(j).getValueType().isVector())
402  if (Op.getOperand(j)
403  .getValueType()
405  .isFloatingPoint() &&
406  NVT.isVector() && NVT.getVectorElementType().isFloatingPoint())
407  Operands[j] = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Op.getOperand(j));
408  else
409  Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j));
410  else
411  Operands[j] = Op.getOperand(j);
412  }
413 
414  Op = DAG.getNode(Op.getOpcode(), dl, NVT, Operands);
415  if ((VT.isFloatingPoint() && NVT.isFloatingPoint()) ||
417  NVT.isVector() && NVT.getVectorElementType().isFloatingPoint()))
418  return DAG.getNode(ISD::FP_ROUND, dl, VT, Op, DAG.getIntPtrConstant(0, dl));
419  else
420  return DAG.getNode(ISD::BITCAST, dl, VT, Op);
421 }
422 
423 SDValue VectorLegalizer::PromoteINT_TO_FP(SDValue Op) {
424  // INT_TO_FP operations may require the input operand be promoted even
425  // when the type is otherwise legal.
426  EVT VT = Op.getOperand(0).getValueType();
427  assert(Op.getNode()->getNumValues() == 1 &&
428  "Can't promote a vector with multiple results!");
429 
430  // Normal getTypeToPromoteTo() doesn't work here, as that will promote
431  // by widening the vector w/ the same element width and twice the number
432  // of elements. We want the other way around, the same number of elements,
433  // each twice the width.
434  //
435  // Increase the bitwidth of the element to the next pow-of-two
436  // (which is greater than 8 bits).
437 
438  EVT NVT = VT.widenIntegerVectorElementType(*DAG.getContext());
439  assert(NVT.isSimple() && "Promoting to a non-simple vector type!");
440  SDLoc dl(Op);
442 
443  unsigned Opc = Op.getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND :
445  for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
446  if (Op.getOperand(j).getValueType().isVector())
447  Operands[j] = DAG.getNode(Opc, dl, NVT, Op.getOperand(j));
448  else
449  Operands[j] = Op.getOperand(j);
450  }
451 
452  return DAG.getNode(Op.getOpcode(), dl, Op.getValueType(), Operands);
453 }
454 
455 // For FP_TO_INT we promote the result type to a vector type with wider
456 // elements and then truncate the result. This is different from the default
457 // PromoteVector which uses bitcast to promote thus assumning that the
458 // promoted vector type has the same overall size.
459 SDValue VectorLegalizer::PromoteFP_TO_INT(SDValue Op, bool isSigned) {
460  assert(Op.getNode()->getNumValues() == 1 &&
461  "Can't promote a vector with multiple results!");
462  EVT VT = Op.getValueType();
463 
464  EVT NewVT;
465  unsigned NewOpc;
466  while (1) {
467  NewVT = VT.widenIntegerVectorElementType(*DAG.getContext());
468  assert(NewVT.isSimple() && "Promoting to a non-simple vector type!");
469  if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewVT)) {
470  NewOpc = ISD::FP_TO_SINT;
471  break;
472  }
473  if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewVT)) {
474  NewOpc = ISD::FP_TO_UINT;
475  break;
476  }
477  }
478 
479  SDLoc loc(Op);
480  SDValue promoted = DAG.getNode(NewOpc, SDLoc(Op), NewVT, Op.getOperand(0));
481  return DAG.getNode(ISD::TRUNCATE, SDLoc(Op), VT, promoted);
482 }
483 
484 
485 SDValue VectorLegalizer::ExpandLoad(SDValue Op) {
486  SDLoc dl(Op);
487  LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
488  SDValue Chain = LD->getChain();
489  SDValue BasePTR = LD->getBasePtr();
490  EVT SrcVT = LD->getMemoryVT();
491  ISD::LoadExtType ExtType = LD->getExtensionType();
492 
494  SmallVector<SDValue, 8> LoadChains;
495  unsigned NumElem = SrcVT.getVectorNumElements();
496 
497  EVT SrcEltVT = SrcVT.getScalarType();
498  EVT DstEltVT = Op.getNode()->getValueType(0).getScalarType();
499 
500  if (SrcVT.getVectorNumElements() > 1 && !SrcEltVT.isByteSized()) {
501  // When elements in a vector is not byte-addressable, we cannot directly
502  // load each element by advancing pointer, which could only address bytes.
503  // Instead, we load all significant words, mask bits off, and concatenate
504  // them to form each element. Finally, they are extended to destination
505  // scalar type to build the destination vector.
506  EVT WideVT = TLI.getPointerTy(DAG.getDataLayout());
507 
508  assert(WideVT.isRound() &&
509  "Could not handle the sophisticated case when the widest integer is"
510  " not power of 2.");
511  assert(WideVT.bitsGE(SrcEltVT) &&
512  "Type is not legalized?");
513 
514  unsigned WideBytes = WideVT.getStoreSize();
515  unsigned Offset = 0;
516  unsigned RemainingBytes = SrcVT.getStoreSize();
517  SmallVector<SDValue, 8> LoadVals;
518 
519  while (RemainingBytes > 0) {
520  SDValue ScalarLoad;
521  unsigned LoadBytes = WideBytes;
522 
523  if (RemainingBytes >= LoadBytes) {
524  ScalarLoad = DAG.getLoad(WideVT, dl, Chain, BasePTR,
525  LD->getPointerInfo().getWithOffset(Offset),
526  LD->isVolatile(), LD->isNonTemporal(),
527  LD->isInvariant(),
528  MinAlign(LD->getAlignment(), Offset),
529  LD->getAAInfo());
530  } else {
531  EVT LoadVT = WideVT;
532  while (RemainingBytes < LoadBytes) {
533  LoadBytes >>= 1; // Reduce the load size by half.
534  LoadVT = EVT::getIntegerVT(*DAG.getContext(), LoadBytes << 3);
535  }
536  ScalarLoad = DAG.getExtLoad(ISD::EXTLOAD, dl, WideVT, Chain, BasePTR,
537  LD->getPointerInfo().getWithOffset(Offset),
538  LoadVT, LD->isVolatile(),
539  LD->isNonTemporal(), LD->isInvariant(),
540  MinAlign(LD->getAlignment(), Offset),
541  LD->getAAInfo());
542  }
543 
544  RemainingBytes -= LoadBytes;
545  Offset += LoadBytes;
546  BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
547  DAG.getConstant(LoadBytes, dl,
548  BasePTR.getValueType()));
549 
550  LoadVals.push_back(ScalarLoad.getValue(0));
551  LoadChains.push_back(ScalarLoad.getValue(1));
552  }
553 
554  // Extract bits, pack and extend/trunc them into destination type.
555  unsigned SrcEltBits = SrcEltVT.getSizeInBits();
556  SDValue SrcEltBitMask = DAG.getConstant((1U << SrcEltBits) - 1, dl, WideVT);
557 
558  unsigned BitOffset = 0;
559  unsigned WideIdx = 0;
560  unsigned WideBits = WideVT.getSizeInBits();
561 
562  for (unsigned Idx = 0; Idx != NumElem; ++Idx) {
563  SDValue Lo, Hi, ShAmt;
564 
565  if (BitOffset < WideBits) {
566  ShAmt = DAG.getConstant(
567  BitOffset, dl, TLI.getShiftAmountTy(WideVT, DAG.getDataLayout()));
568  Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt);
569  Lo = DAG.getNode(ISD::AND, dl, WideVT, Lo, SrcEltBitMask);
570  }
571 
572  BitOffset += SrcEltBits;
573  if (BitOffset >= WideBits) {
574  WideIdx++;
575  BitOffset -= WideBits;
576  if (BitOffset > 0) {
577  ShAmt = DAG.getConstant(
578  SrcEltBits - BitOffset, dl,
579  TLI.getShiftAmountTy(WideVT, DAG.getDataLayout()));
580  Hi = DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt);
581  Hi = DAG.getNode(ISD::AND, dl, WideVT, Hi, SrcEltBitMask);
582  }
583  }
584 
585  if (Hi.getNode())
586  Lo = DAG.getNode(ISD::OR, dl, WideVT, Lo, Hi);
587 
588  switch (ExtType) {
589  default: llvm_unreachable("Unknown extended-load op!");
590  case ISD::EXTLOAD:
591  Lo = DAG.getAnyExtOrTrunc(Lo, dl, DstEltVT);
592  break;
593  case ISD::ZEXTLOAD:
594  Lo = DAG.getZExtOrTrunc(Lo, dl, DstEltVT);
595  break;
596  case ISD::SEXTLOAD:
597  ShAmt =
598  DAG.getConstant(WideBits - SrcEltBits, dl,
599  TLI.getShiftAmountTy(WideVT, DAG.getDataLayout()));
600  Lo = DAG.getNode(ISD::SHL, dl, WideVT, Lo, ShAmt);
601  Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt);
602  Lo = DAG.getSExtOrTrunc(Lo, dl, DstEltVT);
603  break;
604  }
605  Vals.push_back(Lo);
606  }
607  } else {
608  unsigned Stride = SrcVT.getScalarType().getSizeInBits()/8;
609 
610  for (unsigned Idx=0; Idx<NumElem; Idx++) {
611  SDValue ScalarLoad = DAG.getExtLoad(ExtType, dl,
613  Chain, BasePTR, LD->getPointerInfo().getWithOffset(Idx * Stride),
614  SrcVT.getScalarType(),
615  LD->isVolatile(), LD->isNonTemporal(), LD->isInvariant(),
616  MinAlign(LD->getAlignment(), Idx * Stride), LD->getAAInfo());
617 
618  BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
619  DAG.getConstant(Stride, dl, BasePTR.getValueType()));
620 
621  Vals.push_back(ScalarLoad.getValue(0));
622  LoadChains.push_back(ScalarLoad.getValue(1));
623  }
624  }
625 
626  SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
627  SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl,
628  Op.getNode()->getValueType(0), Vals);
629 
630  AddLegalizedOperand(Op.getValue(0), Value);
631  AddLegalizedOperand(Op.getValue(1), NewChain);
632 
633  return (Op.getResNo() ? NewChain : Value);
634 }
635 
636 SDValue VectorLegalizer::ExpandStore(SDValue Op) {
637  SDLoc dl(Op);
638  StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
639  SDValue Chain = ST->getChain();
640  SDValue BasePTR = ST->getBasePtr();
641  SDValue Value = ST->getValue();
642  EVT StVT = ST->getMemoryVT();
643 
644  unsigned Alignment = ST->getAlignment();
645  bool isVolatile = ST->isVolatile();
646  bool isNonTemporal = ST->isNonTemporal();
647  AAMDNodes AAInfo = ST->getAAInfo();
648 
649  unsigned NumElem = StVT.getVectorNumElements();
650  // The type of the data we want to save
651  EVT RegVT = Value.getValueType();
652  EVT RegSclVT = RegVT.getScalarType();
653  // The type of data as saved in memory.
654  EVT MemSclVT = StVT.getScalarType();
655 
656  // Cast floats into integers
657  unsigned ScalarSize = MemSclVT.getSizeInBits();
658 
659  // Round odd types to the next pow of two.
660  if (!isPowerOf2_32(ScalarSize))
661  ScalarSize = NextPowerOf2(ScalarSize);
662 
663  // Store Stride in bytes
664  unsigned Stride = ScalarSize/8;
665  // Extract each of the elements from the original vector
666  // and save them into memory individually.
668  for (unsigned Idx = 0; Idx < NumElem; Idx++) {
669  SDValue Ex = DAG.getNode(
670  ISD::EXTRACT_VECTOR_ELT, dl, RegSclVT, Value,
671  DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
672 
673  // This scalar TruncStore may be illegal, but we legalize it later.
674  SDValue Store = DAG.getTruncStore(Chain, dl, Ex, BasePTR,
675  ST->getPointerInfo().getWithOffset(Idx*Stride), MemSclVT,
676  isVolatile, isNonTemporal, MinAlign(Alignment, Idx*Stride),
677  AAInfo);
678 
679  BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
680  DAG.getConstant(Stride, dl, BasePTR.getValueType()));
681 
682  Stores.push_back(Store);
683  }
684  SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
685  AddLegalizedOperand(Op, TF);
686  return TF;
687 }
688 
689 SDValue VectorLegalizer::Expand(SDValue Op) {
690  switch (Op->getOpcode()) {
692  return ExpandSEXTINREG(Op);
694  return ExpandANY_EXTEND_VECTOR_INREG(Op);
696  return ExpandSIGN_EXTEND_VECTOR_INREG(Op);
698  return ExpandZERO_EXTEND_VECTOR_INREG(Op);
699  case ISD::BSWAP:
700  return ExpandBSWAP(Op);
701  case ISD::VSELECT:
702  return ExpandVSELECT(Op);
703  case ISD::SELECT:
704  return ExpandSELECT(Op);
705  case ISD::UINT_TO_FP:
706  return ExpandUINT_TO_FLOAT(Op);
707  case ISD::FNEG:
708  return ExpandFNEG(Op);
709  case ISD::SETCC:
710  return UnrollVSETCC(Op);
711  default:
712  return DAG.UnrollVectorOp(Op.getNode());
713  }
714 }
715 
716 SDValue VectorLegalizer::ExpandSELECT(SDValue Op) {
717  // Lower a select instruction where the condition is a scalar and the
718  // operands are vectors. Lower this select to VSELECT and implement it
719  // using XOR AND OR. The selector bit is broadcasted.
720  EVT VT = Op.getValueType();
721  SDLoc DL(Op);
722 
723  SDValue Mask = Op.getOperand(0);
724  SDValue Op1 = Op.getOperand(1);
725  SDValue Op2 = Op.getOperand(2);
726 
727  assert(VT.isVector() && !Mask.getValueType().isVector()
728  && Op1.getValueType() == Op2.getValueType() && "Invalid type");
729 
730  unsigned NumElem = VT.getVectorNumElements();
731 
732  // If we can't even use the basic vector operations of
733  // AND,OR,XOR, we will have to scalarize the op.
734  // Notice that the operation may be 'promoted' which means that it is
735  // 'bitcasted' to another type which is handled.
736  // Also, we need to be able to construct a splat vector using BUILD_VECTOR.
737  if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
738  TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
739  TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
740  TLI.getOperationAction(ISD::BUILD_VECTOR, VT) == TargetLowering::Expand)
741  return DAG.UnrollVectorOp(Op.getNode());
742 
743  // Generate a mask operand.
745 
746  // What is the size of each element in the vector mask.
747  EVT BitTy = MaskTy.getScalarType();
748 
749  Mask = DAG.getSelect(DL, BitTy, Mask,
750  DAG.getConstant(APInt::getAllOnesValue(BitTy.getSizeInBits()), DL,
751  BitTy),
752  DAG.getConstant(0, DL, BitTy));
753 
754  // Broadcast the mask so that the entire vector is all-one or all zero.
755  SmallVector<SDValue, 8> Ops(NumElem, Mask);
756  Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskTy, Ops);
757 
758  // Bitcast the operands to be the same type as the mask.
759  // This is needed when we select between FP types because
760  // the mask is a vector of integers.
761  Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1);
762  Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2);
763 
764  SDValue AllOnes = DAG.getConstant(
765  APInt::getAllOnesValue(BitTy.getSizeInBits()), DL, MaskTy);
766  SDValue NotMask = DAG.getNode(ISD::XOR, DL, MaskTy, Mask, AllOnes);
767 
768  Op1 = DAG.getNode(ISD::AND, DL, MaskTy, Op1, Mask);
769  Op2 = DAG.getNode(ISD::AND, DL, MaskTy, Op2, NotMask);
770  SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2);
771  return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
772 }
773 
774 SDValue VectorLegalizer::ExpandSEXTINREG(SDValue Op) {
775  EVT VT = Op.getValueType();
776 
777  // Make sure that the SRA and SHL instructions are available.
778  if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand ||
779  TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Expand)
780  return DAG.UnrollVectorOp(Op.getNode());
781 
782  SDLoc DL(Op);
783  EVT OrigTy = cast<VTSDNode>(Op->getOperand(1))->getVT();
784 
785  unsigned BW = VT.getScalarType().getSizeInBits();
786  unsigned OrigBW = OrigTy.getScalarType().getSizeInBits();
787  SDValue ShiftSz = DAG.getConstant(BW - OrigBW, DL, VT);
788 
789  Op = Op.getOperand(0);
790  Op = DAG.getNode(ISD::SHL, DL, VT, Op, ShiftSz);
791  return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz);
792 }
793 
794 // Generically expand a vector anyext in register to a shuffle of the relevant
795 // lanes into the appropriate locations, with other lanes left undef.
796 SDValue VectorLegalizer::ExpandANY_EXTEND_VECTOR_INREG(SDValue Op) {
797  SDLoc DL(Op);
798  EVT VT = Op.getValueType();
799  int NumElements = VT.getVectorNumElements();
800  SDValue Src = Op.getOperand(0);
801  EVT SrcVT = Src.getValueType();
802  int NumSrcElements = SrcVT.getVectorNumElements();
803 
804  // Build a base mask of undef shuffles.
805  SmallVector<int, 16> ShuffleMask;
806  ShuffleMask.resize(NumSrcElements, -1);
807 
808  // Place the extended lanes into the correct locations.
809  int ExtLaneScale = NumSrcElements / NumElements;
810  int EndianOffset = DAG.getDataLayout().isBigEndian() ? ExtLaneScale - 1 : 0;
811  for (int i = 0; i < NumElements; ++i)
812  ShuffleMask[i * ExtLaneScale + EndianOffset] = i;
813 
814  return DAG.getNode(
815  ISD::BITCAST, DL, VT,
816  DAG.getVectorShuffle(SrcVT, DL, Src, DAG.getUNDEF(SrcVT), ShuffleMask));
817 }
818 
819 SDValue VectorLegalizer::ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op) {
820  SDLoc DL(Op);
821  EVT VT = Op.getValueType();
822  SDValue Src = Op.getOperand(0);
823  EVT SrcVT = Src.getValueType();
824 
825  // First build an any-extend node which can be legalized above when we
826  // recurse through it.
827  Op = DAG.getAnyExtendVectorInReg(Src, DL, VT);
828 
829  // Now we need sign extend. Do this by shifting the elements. Even if these
830  // aren't legal operations, they have a better chance of being legalized
831  // without full scalarization than the sign extension does.
832  unsigned EltWidth = VT.getVectorElementType().getSizeInBits();
833  unsigned SrcEltWidth = SrcVT.getVectorElementType().getSizeInBits();
834  SDValue ShiftAmount = DAG.getConstant(EltWidth - SrcEltWidth, DL, VT);
835  return DAG.getNode(ISD::SRA, DL, VT,
836  DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount),
837  ShiftAmount);
838 }
839 
840 // Generically expand a vector zext in register to a shuffle of the relevant
841 // lanes into the appropriate locations, a blend of zero into the high bits,
842 // and a bitcast to the wider element type.
843 SDValue VectorLegalizer::ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op) {
844  SDLoc DL(Op);
845  EVT VT = Op.getValueType();
846  int NumElements = VT.getVectorNumElements();
847  SDValue Src = Op.getOperand(0);
848  EVT SrcVT = Src.getValueType();
849  int NumSrcElements = SrcVT.getVectorNumElements();
850 
851  // Build up a zero vector to blend into this one.
852  EVT SrcScalarVT = SrcVT.getScalarType();
853  SDValue ScalarZero = DAG.getTargetConstant(0, DL, SrcScalarVT);
854  SmallVector<SDValue, 4> BuildVectorOperands(NumSrcElements, ScalarZero);
855  SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, DL, SrcVT, BuildVectorOperands);
856 
857  // Shuffle the incoming lanes into the correct position, and pull all other
858  // lanes from the zero vector.
859  SmallVector<int, 16> ShuffleMask;
860  ShuffleMask.reserve(NumSrcElements);
861  for (int i = 0; i < NumSrcElements; ++i)
862  ShuffleMask.push_back(i);
863 
864  int ExtLaneScale = NumSrcElements / NumElements;
865  int EndianOffset = DAG.getDataLayout().isBigEndian() ? ExtLaneScale - 1 : 0;
866  for (int i = 0; i < NumElements; ++i)
867  ShuffleMask[i * ExtLaneScale + EndianOffset] = NumSrcElements + i;
868 
869  return DAG.getNode(ISD::BITCAST, DL, VT,
870  DAG.getVectorShuffle(SrcVT, DL, Zero, Src, ShuffleMask));
871 }
872 
873 SDValue VectorLegalizer::ExpandBSWAP(SDValue Op) {
874  EVT VT = Op.getValueType();
875 
876  // Generate a byte wise shuffle mask for the BSWAP.
877  SmallVector<int, 16> ShuffleMask;
878  int ScalarSizeInBytes = VT.getScalarSizeInBits() / 8;
879  for (int I = 0, E = VT.getVectorNumElements(); I != E; ++I)
880  for (int J = ScalarSizeInBytes - 1; J >= 0; --J)
881  ShuffleMask.push_back((I * ScalarSizeInBytes) + J);
882 
883  EVT ByteVT = EVT::getVectorVT(*DAG.getContext(), MVT::i8, ShuffleMask.size());
884 
885  // Only emit a shuffle if the mask is legal.
886  if (!TLI.isShuffleMaskLegal(ShuffleMask, ByteVT))
887  return DAG.UnrollVectorOp(Op.getNode());
888 
889  SDLoc DL(Op);
890  Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Op.getOperand(0));
891  Op = DAG.getVectorShuffle(ByteVT, DL, Op, DAG.getUNDEF(ByteVT),
892  ShuffleMask.data());
893  return DAG.getNode(ISD::BITCAST, DL, VT, Op);
894 }
895 
896 SDValue VectorLegalizer::ExpandVSELECT(SDValue Op) {
897  // Implement VSELECT in terms of XOR, AND, OR
898  // on platforms which do not support blend natively.
899  SDLoc DL(Op);
900 
901  SDValue Mask = Op.getOperand(0);
902  SDValue Op1 = Op.getOperand(1);
903  SDValue Op2 = Op.getOperand(2);
904 
905  EVT VT = Mask.getValueType();
906 
907  // If we can't even use the basic vector operations of
908  // AND,OR,XOR, we will have to scalarize the op.
909  // Notice that the operation may be 'promoted' which means that it is
910  // 'bitcasted' to another type which is handled.
911  // This operation also isn't safe with AND, OR, XOR when the boolean
912  // type is 0/1 as we need an all ones vector constant to mask with.
913  // FIXME: Sign extend 1 to all ones if thats legal on the target.
914  if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
915  TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
916  TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
917  TLI.getBooleanContents(Op1.getValueType()) !=
919  return DAG.UnrollVectorOp(Op.getNode());
920 
921  // If the mask and the type are different sizes, unroll the vector op. This
922  // can occur when getSetCCResultType returns something that is different in
923  // size from the operand types. For example, v4i8 = select v4i32, v4i8, v4i8.
924  if (VT.getSizeInBits() != Op1.getValueType().getSizeInBits())
925  return DAG.UnrollVectorOp(Op.getNode());
926 
927  // Bitcast the operands to be the same type as the mask.
928  // This is needed when we select between FP types because
929  // the mask is a vector of integers.
930  Op1 = DAG.getNode(ISD::BITCAST, DL, VT, Op1);
931  Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2);
932 
933  SDValue AllOnes = DAG.getConstant(
935  SDValue NotMask = DAG.getNode(ISD::XOR, DL, VT, Mask, AllOnes);
936 
937  Op1 = DAG.getNode(ISD::AND, DL, VT, Op1, Mask);
938  Op2 = DAG.getNode(ISD::AND, DL, VT, Op2, NotMask);
939  SDValue Val = DAG.getNode(ISD::OR, DL, VT, Op1, Op2);
940  return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
941 }
942 
943 SDValue VectorLegalizer::ExpandUINT_TO_FLOAT(SDValue Op) {
944  EVT VT = Op.getOperand(0).getValueType();
945  SDLoc DL(Op);
946 
947  // Make sure that the SINT_TO_FP and SRL instructions are available.
948  if (TLI.getOperationAction(ISD::SINT_TO_FP, VT) == TargetLowering::Expand ||
949  TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand)
950  return DAG.UnrollVectorOp(Op.getNode());
951 
952  EVT SVT = VT.getScalarType();
953  assert((SVT.getSizeInBits() == 64 || SVT.getSizeInBits() == 32) &&
954  "Elements in vector-UINT_TO_FP must be 32 or 64 bits wide");
955 
956  unsigned BW = SVT.getSizeInBits();
957  SDValue HalfWord = DAG.getConstant(BW/2, DL, VT);
958 
959  // Constants to clear the upper part of the word.
960  // Notice that we can also use SHL+SHR, but using a constant is slightly
961  // faster on x86.
962  uint64_t HWMask = (SVT.getSizeInBits()==64)?0x00000000FFFFFFFF:0x0000FFFF;
963  SDValue HalfWordMask = DAG.getConstant(HWMask, DL, VT);
964 
965  // Two to the power of half-word-size.
966  SDValue TWOHW = DAG.getConstantFP(1 << (BW/2), DL, Op.getValueType());
967 
968  // Clear upper part of LO, lower HI
969  SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Op.getOperand(0), HalfWord);
970  SDValue LO = DAG.getNode(ISD::AND, DL, VT, Op.getOperand(0), HalfWordMask);
971 
972  // Convert hi and lo to floats
973  // Convert the hi part back to the upper values
974  SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), HI);
975  fHI = DAG.getNode(ISD::FMUL, DL, Op.getValueType(), fHI, TWOHW);
976  SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), LO);
977 
978  // Add the two halves
979  return DAG.getNode(ISD::FADD, DL, Op.getValueType(), fHI, fLO);
980 }
981 
982 
983 SDValue VectorLegalizer::ExpandFNEG(SDValue Op) {
984  if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) {
985  SDLoc DL(Op);
986  SDValue Zero = DAG.getConstantFP(-0.0, DL, Op.getValueType());
987  return DAG.getNode(ISD::FSUB, DL, Op.getValueType(),
988  Zero, Op.getOperand(0));
989  }
990  return DAG.UnrollVectorOp(Op.getNode());
991 }
992 
993 SDValue VectorLegalizer::UnrollVSETCC(SDValue Op) {
994  EVT VT = Op.getValueType();
995  unsigned NumElems = VT.getVectorNumElements();
996  EVT EltVT = VT.getVectorElementType();
997  SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1), CC = Op.getOperand(2);
998  EVT TmpEltVT = LHS.getValueType().getVectorElementType();
999  SDLoc dl(Op);
1000  SmallVector<SDValue, 8> Ops(NumElems);
1001  for (unsigned i = 0; i < NumElems; ++i) {
1002  SDValue LHSElem = DAG.getNode(
1003  ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS,
1004  DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
1005  SDValue RHSElem = DAG.getNode(
1006  ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS,
1007  DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
1008  Ops[i] = DAG.getNode(ISD::SETCC, dl,
1009  TLI.getSetCCResultType(DAG.getDataLayout(),
1010  *DAG.getContext(), TmpEltVT),
1011  LHSElem, RHSElem, CC);
1012  Ops[i] = DAG.getSelect(dl, EltVT, Ops[i],
1013  DAG.getConstant(APInt::getAllOnesValue
1014  (EltVT.getSizeInBits()), dl, EltVT),
1015  DAG.getConstant(0, dl, EltVT));
1016  }
1017  return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
1018 }
1019 
1020 }
1021 
1023  return VectorLegalizer(*this).Run();
1024 }
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:477
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:450
SDValue getValue(unsigned R) const
static APInt getAllOnesValue(unsigned numBits)
Get the all-ones value.
Definition: APInt.h:453
ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register zero-extension of the low ...
Definition: ISDOpcodes.h:432
bool LegalizeVectors()
This transforms the SelectionDAG into a SelectionDAG that only uses vector math operations supported ...
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
unsigned getNumOperands() const
const SDValue & getOperand(unsigned Num) const
SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register sign-extension of the low ...
Definition: ISDOpcodes.h:423
[US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned integers.
Definition: ISDOpcodes.h:318
void reserve(size_type N)
Definition: SmallVector.h:401
const SDValue & getBasePtr() const
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:357
unsigned getResNo() const
get the index which selects a specific result in the SDNode
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Definition: DenseMap.h:169
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:115
bool isRound() const
isRound - Return true if the size is a power-of-two number of bytes.
Definition: ValueTypes.h:165
Shift and rotation operations.
Definition: ISDOpcodes.h:332
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
MachinePointerInfo getWithOffset(int64_t O) const
EVT getScalarType() const
getScalarType - If this is a vector type, return the element type, otherwise return this...
Definition: ValueTypes.h:210
bool bitsGE(EVT VT) const
bitsGE - Return true if this has no less bits than VT.
Definition: ValueTypes.h:183
#define false
Definition: ConvertUTF.c:65
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
EVT getVectorElementType() const
getVectorElementType - Given a vector type, return the type of each element.
Definition: ValueTypes.h:216
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:393
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
Definition: ISDOpcodes.h:351
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:191
const SDValue & getBasePtr() const
EVT getMemoryVT() const
Return the type of the in-memory value.
ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register any-extension of the low la...
Definition: ISDOpcodes.h:410
This class is used to represent ISD::STORE nodes.
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:436
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable...
Definition: ISDOpcodes.h:262
SDNode * getNode() const
get the SDNode which holds the desired result
unsigned getScalarSizeInBits() const
Definition: ValueTypes.h:239
unsigned getStoreSize() const
getStoreSize - Return the number of bytes overwritten by a store of the specified value type...
Definition: ValueTypes.h:245
MVT - Machine Value Type.
const SDValue & getOperand(unsigned i) const
Simple binary floating point operators.
Definition: ISDOpcodes.h:237
bool isNonTemporal() const
bool isVector() const
isVector - Return true if this is a vector value type.
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:780
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
unsigned getOpcode() const
SI Fold Operands
bool isVolatile() const
const SDValue & getValue() const
Bit counting operators with an undefined result for zero inputs.
Definition: ISDOpcodes.h:338
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:468
EVT - Extended Value Type.
Definition: ValueTypes.h:31
uint64_t NextPowerOf2(uint64_t A)
NextPowerOf2 - Returns the next power of two (in 64-bits) that is strictly greater than A...
Definition: MathExtras.h:582
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements)
getVectorVT - Returns the EVT that represents a vector NumElements in length, where each element is o...
Definition: ValueTypes.h:70
const MachinePointerInfo & getPointerInfo() const
TokenFactor - This node takes multiple tokens as input and produces a single token result...
Definition: ISDOpcodes.h:50
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
Definition: ISDOpcodes.h:273
bool isInvariant() const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:179
X = FP_ROUND_INREG(Y, VT) - This operator takes an FP register, and rounds it to a floating point val...
Definition: ISDOpcodes.h:465
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:861
const SDValue & getChain() const
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:548
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:335
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
bool use_empty() const
Return true if there are no nodes using value ResNo of Node.
AAMDNodes getAAInfo() const
Returns the AA info that describes the dereference.
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:342
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:383
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:386
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition: ISDOpcodes.h:250
EVT widenIntegerVectorElementType(LLVMContext &Context) const
Return a VT for an integer vector type with the size of the elements doubled.
Definition: ValueTypes.h:284
iterator_range< value_op_iterator > op_values() const
uint64_t MinAlign(uint64_t A, uint64_t B)
MinAlign - A and B are either alignments or offsets.
Definition: MathExtras.h:552
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:321
pointer data()
Return a pointer to the vector's buffer, even if empty().
Definition: SmallVector.h:134
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:401
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:518
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:233
#define I(x, y, z)
Definition: MD5.cpp:54
EVT getValueType() const
Return the ValueType of the referenced return value.
bool isByteSized() const
isByteSized - Return true if the bit size is a multiple of 8.
Definition: ValueTypes.h:160
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
Definition: ValueTypes.h:105
bool isSimple() const
isSimple - Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:94
LLVM Value Representation.
Definition: Value.h:69
FMA - Perform a * b + c with no intermediate rounding step.
Definition: ISDOpcodes.h:240
bool isTruncatingStore() const
Return true if the op does a truncation before store.
bool isPowerOf2_32(uint32_t Value)
isPowerOf2_32 - This function returns true if the argument is a power of two > 0. ...
Definition: MathExtras.h:354
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:365
MVT getVectorElementType() const
static bool isVolatile(Instruction *Inst)
Conversion operators.
Definition: ISDOpcodes.h:380
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:389
unsigned getAlignment() const
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2, FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR - Perform various unary floating point operations.
Definition: ISDOpcodes.h:506
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
getIntegerVT - Returns the EVT that represents an integer with the given number of bits...
Definition: ValueTypes.h:61
EVT changeVectorElementTypeToInteger() const
changeVectorElementTypeToInteger - Return a vector with the same number of elements as this vector...
Definition: ValueTypes.h:80
This file describes how to lower LLVM code to machine code.
unsigned getVectorNumElements() const
getVectorNumElements - Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:225
void resize(size_type N)
Definition: SmallVector.h:376
This class is used to represent ISD::LOAD nodes.