LLVM  3.7.0
R600MachineScheduler.h
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1 //===-- R600MachineScheduler.h - R600 Scheduler Interface -*- C++ -*-------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief R600 Machine Scheduler interface
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_R600_R600MACHINESCHEDULER_H
16 #define LLVM_LIB_TARGET_R600_R600MACHINESCHEDULER_H
17 
18 #include "R600InstrInfo.h"
19 #include "llvm/ADT/PriorityQueue.h"
21 #include "llvm/Support/Debug.h"
22 
23 using namespace llvm;
24 
25 namespace llvm {
26 
28 
29  const ScheduleDAGMILive *DAG;
30  const R600InstrInfo *TII;
31  const R600RegisterInfo *TRI;
33 
34  enum InstKind {
35  IDAlu,
36  IDFetch,
37  IDOther,
38  IDLast
39  };
40 
41  enum AluKind {
42  AluAny,
43  AluT_X,
44  AluT_Y,
45  AluT_Z,
46  AluT_W,
47  AluT_XYZW,
48  AluPredX,
49  AluTrans,
50  AluDiscarded, // LLVM Instructions that are going to be eliminated
51  AluLast
52  };
53 
54  std::vector<SUnit *> Available[IDLast], Pending[IDLast];
55  std::vector<SUnit *> AvailableAlus[AluLast];
56  std::vector<SUnit *> PhysicalRegCopy;
57 
58  InstKind CurInstKind;
59  int CurEmitted;
60  InstKind NextInstKind;
61 
62  unsigned AluInstCount;
63  unsigned FetchInstCount;
64 
65  int InstKindLimit[IDLast];
66 
67  int OccupedSlotsMask;
68 
69 public:
71  DAG(nullptr), TII(nullptr), TRI(nullptr), MRI(nullptr) {
72  }
73 
74  virtual ~R600SchedStrategy() {}
75 
76  void initialize(ScheduleDAGMI *dag) override;
77  SUnit *pickNode(bool &IsTopNode) override;
78  void schedNode(SUnit *SU, bool IsTopNode) override;
79  void releaseTopNode(SUnit *SU) override;
80  void releaseBottomNode(SUnit *SU) override;
81 
82 private:
83  std::vector<MachineInstr *> InstructionsGroupCandidate;
84  bool VLIW5;
85 
86  int getInstKind(SUnit *SU);
87  bool regBelongsToClass(unsigned Reg, const TargetRegisterClass *RC) const;
88  AluKind getAluKind(SUnit *SU) const;
89  void LoadAlu();
90  unsigned AvailablesAluCount() const;
91  SUnit *AttemptFillSlot (unsigned Slot, bool AnyAlu);
92  void PrepareNextSlot();
93  SUnit *PopInst(std::vector<SUnit*> &Q, bool AnyALU);
94 
95  void AssignSlot(MachineInstr *MI, unsigned Slot);
96  SUnit* pickAlu();
97  SUnit* pickOther(int QID);
98  void MoveUnits(std::vector<SUnit *> &QSrc, std::vector<SUnit *> &QDst);
99 };
100 
101 } // namespace llvm
102 
103 #endif /* R600MACHINESCHEDULER_H_ */
void schedNode(SUnit *SU, bool IsTopNode) override
Notify MachineSchedStrategy that ScheduleDAGMI has scheduled an instruction and updated scheduled/rem...
Interface definition for R600InstrInfo.
void initialize(ScheduleDAGMI *dag) override
Initialize the strategy after building the DAG for a new region.
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
void releaseBottomNode(SUnit *SU) override
When all successor dependencies have been resolved, free this node for bottom-up scheduling.
Reg
All possible values of the reg field in the ModR/M byte.
SUnit * pickNode(bool &IsTopNode) override
Pick the next node to schedule, or return NULL.
void releaseTopNode(SUnit *SU) override
When all predecessor dependencies have been resolved, free this node for top-down scheduling...
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:51
MachineSchedStrategy - Interface to the scheduling algorithm used by ScheduleDAGMI.
SUnit - Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:261