124 using namespace llvm;
126 #define DEBUG_TYPE "aarch64-collect-loh"
130 cl::desc(
"Restrict analysis to registers invovled"
136 cl::desc(
"Restrict analysis at basic block scope"),
140 "Number of simplifiable ADRP dominate by another");
142 "Number of simplifiable ADRP reachable by 2 defs");
144 "Number of simplifiable ADRP reachable by 3 defs");
146 "Number of simplifiable ADRP reachable by 4 or more defs");
148 "Number of simplifiable STR with imm reachable by ADD");
150 "Number of simplifiable STR with imm reachable by LDR");
151 STATISTIC(NumADDToSTR,
"Number of simplifiable STR reachable by ADD");
152 STATISTIC(NumLDRToSTR,
"Number of simplifiable STR reachable by LDR");
154 "Number of simplifiable LDR with imm reachable by ADD");
156 "Number of simplifiable LDR with imm reachable by LDR");
157 STATISTIC(NumADDToLDR,
"Number of simplifiable LDR reachable by ADD");
158 STATISTIC(NumLDRToLDR,
"Number of simplifiable LDR reachable by LDR");
159 STATISTIC(NumADRPToLDR,
"Number of simplifiable LDR reachable by ADRP");
160 STATISTIC(NumCplxLvl1,
"Number of complex case of level 1");
161 STATISTIC(NumTooCplxLvl1,
"Number of too complex case of level 1");
162 STATISTIC(NumCplxLvl2,
"Number of complex case of level 2");
163 STATISTIC(NumTooCplxLvl2,
"Number of too complex case of level 2");
164 STATISTIC(NumADRSimpleCandidate,
"Number of simplifiable ADRP + ADD");
165 STATISTIC(NumADRComplexCandidate,
"Number of too complex ADRP + ADD");
180 const char *getPassName()
const override {
181 return "AArch64 Collect Linker Optimization Hint (LOH)";
199 std::unique_ptr<SetOfMachineInstr[]>>
200 BlockToSetOfInstrsPerColor;
204 typedef MapVector<
const MachineBasicBlock *,
205 std::unique_ptr<const MachineInstr *[]>>
206 BlockToInstrPerColor;
223 "AArch64 Collect Linker Optimization Hint (LOH)",
false,
236 static SetOfMachineInstr &
getSet(BlockToSetOfInstrsPerColor &
sets,
239 SetOfMachineInstr *result;
240 BlockToSetOfInstrsPerColor::iterator it = sets.find(&MBB);
241 if (it != sets.end())
242 result = it->second.get();
244 result = (sets[&MBB] = make_unique<SetOfMachineInstr[]>(nbRegs)).get();
256 static SetOfMachineInstr &
getUses(InstrToInstrs *
sets,
unsigned reg,
258 return sets[reg][&
MI];
263 static const SetOfMachineInstr *
getUses(
const InstrToInstrs *
sets,
unsigned reg,
265 InstrToInstrs::const_iterator Res = sets[reg].find(&MI);
266 if (Res != sets[reg].
end())
267 return &(Res->second);
283 InstrToInstrs *ColorOpToReachedUses,
284 BlockToInstrPerColor &Gen, BlockToRegSet &
Kill,
285 BlockToSetOfInstrsPerColor &ReachableUses,
286 const MapRegToId &RegToId,
289 unsigned NbReg = RegToId.size();
292 auto &BBGen = Gen[&MBB];
293 BBGen = make_unique<const MachineInstr *[]>(NbReg);
294 std::fill(BBGen.get(), BBGen.get() + NbReg,
nullptr);
302 if (IsADRP || !ADRPMode)
306 if (!MO.isReg() || (!ADRPMode && !MO.isUse()) ||
307 (ADRPMode && (!IsADRP || !MO.isDef())))
309 unsigned CurReg = MO.getReg();
310 MapRegToId::const_iterator ItCurRegId = RegToId.find(CurReg);
311 if (ItCurRegId == RegToId.end())
313 CurReg = ItCurRegId->second;
316 if (!BBGen[CurReg] && !BBKillSet.test(CurReg))
317 getSet(ReachableUses, MBB, CurReg, NbReg).insert(&
MI);
320 getUses(ColorOpToReachedUses, CurReg, *BBGen[CurReg]).insert(&
MI);
328 const uint32_t *PreservedRegs = MO.getRegMask();
331 for (
const auto &Entry : RegToId) {
332 unsigned Reg = Entry.second;
339 BBGen[
Reg] = ADRPMode ? &
MI :
nullptr;
347 if (!MO.isReg() || !MO.isDef())
349 unsigned CurReg = MO.getReg();
350 MapRegToId::const_iterator ItCurRegId = RegToId.find(CurReg);
351 if (ItCurRegId == RegToId.end())
355 MapRegToId::const_iterator ItRegId = RegToId.find(*AI);
356 assert(ItRegId != RegToId.end() &&
357 "Sub-register of an "
358 "involved register, not recorded as involved!");
359 BBKillSet.set(ItRegId->second);
360 BBGen[ItRegId->second] = &
MI;
362 BBGen[ItCurRegId->second] = &
MI;
369 if (!ADRPMode && DummyOp && !MBB.succ_empty())
370 for (
unsigned CurReg = 0; CurReg < NbReg; ++CurReg)
372 getUses(ColorOpToReachedUses, CurReg, *BBGen[CurReg]).insert(DummyOp);
386 InstrToInstrs *ColorOpToReachedUses,
387 BlockToSetOfInstrsPerColor &
In,
388 BlockToSetOfInstrsPerColor &Out,
389 BlockToInstrPerColor &Gen, BlockToRegSet &
Kill,
390 BlockToSetOfInstrsPerColor &ReachableUses,
397 for (CurReg = 0; CurReg < NbReg; ++CurReg) {
398 SetOfMachineInstr &BBInSet =
getSet(In, MBB, CurReg, NbReg);
399 SetOfMachineInstr &BBReachableUses =
400 getSet(ReachableUses, MBB, CurReg, NbReg);
401 SetOfMachineInstr &BBOutSet =
getSet(Out, MBB, CurReg, NbReg);
402 unsigned Size = BBOutSet.size();
405 SetOfMachineInstr &PredOutSet =
getSet(Out, *PredMBB, CurReg, NbReg);
406 BBInSet.insert(PredOutSet.begin(), PredOutSet.end());
410 SetOfMachineInstr &OpReachedUses =
411 getUses(ColorOpToReachedUses, CurReg, *
MI);
412 OpReachedUses.insert(BBReachableUses.begin(), BBReachableUses.end());
415 if (!Kill[&MBB].test(CurReg))
416 BBOutSet.insert(BBInSet.begin(), BBInSet.end());
417 if (Gen[&MBB][CurReg])
418 BBOutSet.insert(Gen[&MBB][CurReg]);
419 HasChanged |= BBOutSet.size() != Size;
422 }
while (HasChanged);
437 InstrToInstrs *ColorOpToReachedUses,
438 const MapRegToId &RegToId,
bool ADRPMode =
false,
449 BlockToSetOfInstrsPerColor Out,
In, ReachableUses;
450 BlockToInstrPerColor Gen;
454 initReachingDef(MF, ColorOpToReachedUses, Gen, Kill, ReachableUses, RegToId,
460 ReachableUses, RegToId.
size());
467 const MapIdToReg &IdToReg) {
469 for (CurReg = 0; CurReg < NbReg; ++CurReg) {
470 if (ColorOpToReachedUses[CurReg].empty())
474 for (
const auto &DefsIt : ColorOpToReachedUses[CurReg]) {
496 case AArch64::ADDXri:
507 case AArch64::LDRXui:
526 case AArch64::STRBui:
527 case AArch64::STRHui:
528 case AArch64::STRWui:
529 case AArch64::STRXui:
530 case AArch64::STRSui:
531 case AArch64::STRDui:
532 case AArch64::STRQui:
549 const InstrToInstrs *ColorOpToReachedUses,
550 const MapRegToId &RegToId,
551 bool ADRPMode =
false) {
553 SetOfMachineInstr NotCandidate;
554 unsigned NbReg = RegToId.size();
555 MapRegToId::const_iterator EndIt = RegToId.end();
556 for (
unsigned CurReg = 0; CurReg < NbReg; ++CurReg) {
558 if (ColorOpToReachedUses[CurReg].empty())
561 for (
const auto &DefsIt : ColorOpToReachedUses[CurReg]) {
564 MapRegToId::const_iterator It;
572 ((It = RegToId.find((MI)->getOperand(1).
getReg())) == EndIt ||
573 It->second != CurReg))) {
574 NotCandidate.insert(MI);
578 if (!ADRPMode || MI != DefsIt.first) {
579 UseToReachingDefs[
MI].insert(DefsIt.first);
582 if (!ADRPMode && UseToReachingDefs[MI].
size() > 1)
583 NotCandidate.insert(MI);
589 DEBUG(
dbgs() <<
"Too many reaching defs: " << *Elem <<
"\n");
593 UseToReachingDefs[Elem].clear();
602 DEBUG(
dbgs() <<
"*** Compute LOH for ADRP\n");
603 for (
const auto &Entry : UseToDefs) {
604 unsigned Size = Entry.second.size();
611 DEBUG(
dbgs() <<
"Dominance check failed:\n" << *L2 <<
'\n' << *L1
615 DEBUG(
dbgs() <<
"Record AdrpAdrp:\n" << *L2 <<
'\n' << *L1 <<
'\n');
620 ++NumADRPSimpleCandidate;
624 ++NumADRPComplexCandidate2;
626 ++NumADRPComplexCandidate3;
628 ++NumADRPComplexCandidateOther;
631 assert(Size >= 1 &&
"No reaching defs for that use!");
641 case AArch64::LDRSBWui:
642 case AArch64::LDRSBXui:
643 case AArch64::LDRSHWui:
644 case AArch64::LDRSHXui:
645 case AArch64::LDRSWui:
646 case AArch64::LDRBui:
647 case AArch64::LDRHui:
648 case AArch64::LDRWui:
649 case AArch64::LDRXui:
650 case AArch64::LDRSui:
651 case AArch64::LDRDui:
652 case AArch64::LDRQui:
666 case AArch64::LDRSWui:
667 case AArch64::LDRWui:
668 case AArch64::LDRXui:
669 case AArch64::LDRSui:
670 case AArch64::LDRDui:
671 case AArch64::LDRQui:
684 const InstrToInstrs &UseToDefs,
700 if (UseToDefs.find(Def) ==
704 UseToDefs.find(Def)->second.empty())
707 Def = *UseToDefs.find(Def)->second.begin();
719 const InstrToInstrs &UseToDefs,
720 const InstrToInstrs *DefsPerColorToUses,
722 SetOfMachineInstr *InvolvedInLOHs,
723 const MapRegToId &RegToId) {
727 if (Use.
getOpcode() != AArch64::ADDXri &&
731 InstrToInstrs::const_iterator It = UseToDefs.find(&Use);
733 if (It == UseToDefs.end() || It->second.empty())
739 const SetOfMachineInstr *
Users =
742 if (Users->size() > 1) {
743 ++NumADRComplexCandidate;
746 ++NumADRSimpleCandidate;
747 assert((!InvolvedInLOHs || InvolvedInLOHs->insert(&Def)) &&
748 "ADRP already involved in LOH.");
749 assert((!InvolvedInLOHs || InvolvedInLOHs->insert(&Use)) &&
750 "ADD already involved in LOH.");
751 DEBUG(
dbgs() <<
"Record AdrpAdd\n" << Def <<
'\n' << Use <<
'\n');
766 const InstrToInstrs *DefsPerColorToUses,
769 SetOfMachineInstr *InvolvedInLOHs =
nullptr;
771 SetOfMachineInstr InvolvedInLOHsStorage;
772 InvolvedInLOHs = &InvolvedInLOHsStorage;
774 DEBUG(
dbgs() <<
"*** Compute LOH for Others\n");
783 SetOfMachineInstr PotentialCandidates;
784 SetOfMachineInstr PotentialADROpportunities;
785 for (
auto &
Use : UseToDefs) {
787 if (
Use.second.empty())
793 PotentialADROpportunities.insert(
Use.first);
796 PotentialCandidates.insert(
Use.first);
815 SetOfMachineInstr DefsOfPotentialCandidates;
817 for (
const MachineInstr *Candidate : PotentialCandidates) {
823 unsigned ImmediateDefOpc = Def->
getOpcode();
826 const SetOfMachineInstr *
Users =
829 if (Users->size() > 1) {
833 bool IsLevel2 =
true;
835 if (!PotentialCandidates.count(
MI)) {
844 PotentialADROpportunities.insert(Def);
848 Def = *UseToDefs.find(Def)->second.begin();
854 const SetOfMachineInstr *
Users =
857 if (Users->size() > 1) {
861 if (DefsOfPotentialCandidates.empty()) {
863 DefsOfPotentialCandidates = PotentialCandidates;
864 for (
const MachineInstr *Candidate : PotentialCandidates) {
865 if (!UseToDefs.find(Candidate)->second.empty())
866 DefsOfPotentialCandidates.insert(
867 *UseToDefs.find(Candidate)->second.begin());
871 for (
auto &
Use : *Users) {
872 if (!DefsOfPotentialCandidates.count(
Use)) {
884 bool IsL2Add = (ImmediateDefOpc == AArch64::ADDXri);
899 DEBUG(
dbgs() <<
"Record AdrpLdr:\n" << *L1 <<
'\n' << *Candidate
904 assert((!InvolvedInLOHs || InvolvedInLOHs->insert(L1)) &&
905 "L1 already involved in LOH.");
906 assert((!InvolvedInLOHs || InvolvedInLOHs->insert(Candidate)) &&
907 "Candidate already involved in LOH.");
910 DEBUG(
dbgs() <<
"Record Adrp" << (IsL2Add ?
"Add" :
"LdrGot")
911 <<
"Ldr:\n" << *L1 <<
'\n' << *L2 <<
'\n' << *Candidate
919 PotentialADROpportunities.remove(L2);
920 assert((!InvolvedInLOHs || InvolvedInLOHs->insert(L1)) &&
921 "L1 already involved in LOH.");
922 assert((!InvolvedInLOHs || InvolvedInLOHs->insert(L2)) &&
923 "L2 already involved in LOH.");
924 assert((!InvolvedInLOHs || InvolvedInLOHs->insert(Candidate)) &&
925 "Candidate already involved in LOH.");
928 if (Candidate->getOperand(2).getImm() == 0)
929 if (ImmediateDefOpc == AArch64::ADDXri)
933 else if (ImmediateDefOpc == AArch64::ADDXri)
934 ++NumADDToLDRWithImm;
936 ++NumLDRToLDRWithImm;
944 DEBUG(
dbgs() <<
"Record Adrp" << (IsL2Add ?
"Add" :
"LdrGot")
945 <<
"Str:\n" << *L1 <<
'\n' << *L2 <<
'\n' << *Candidate
953 PotentialADROpportunities.remove(L2);
954 assert((!InvolvedInLOHs || InvolvedInLOHs->insert(L1)) &&
955 "L1 already involved in LOH.");
956 assert((!InvolvedInLOHs || InvolvedInLOHs->insert(L2)) &&
957 "L2 already involved in LOH.");
958 assert((!InvolvedInLOHs || InvolvedInLOHs->insert(Candidate)) &&
959 "Candidate already involved in LOH.");
962 if (Candidate->getOperand(2).getImm() == 0)
963 if (ImmediateDefOpc == AArch64::ADDXri)
967 else if (ImmediateDefOpc == AArch64::ADDXri)
968 ++NumADDToSTRWithImm;
970 ++NumLDRToSTRWithImm;
978 for (
const MachineInstr *Candidate : PotentialADROpportunities)
980 InvolvedInLOHs, RegToId);
989 unsigned CurRegId = 0;
992 for (; CurRegId < NbReg; ++CurRegId) {
993 RegToId[CurRegId] = CurRegId;
994 DEBUG(IdToReg.push_back(CurRegId));
995 DEBUG(assert(IdToReg[CurRegId] == CurRegId &&
"Reg index mismatches"));
1000 DEBUG(
dbgs() <<
"** Collect Involved Register\n");
1001 for (
const auto &MBB : MF) {
1008 IOEnd =
MI.operands_end();
1009 IO != IOEnd; ++IO) {
1010 if (!IO->isReg() || !IO->isDef())
1012 unsigned CurReg = IO->getReg();
1014 if (RegToId.find(*AI) == RegToId.end()) {
1015 DEBUG(IdToReg.push_back(*AI);
1016 assert(IdToReg[CurRegId] == *AI &&
1017 "Reg index mismatches insertion index."));
1018 RegToId[*AI] = CurRegId++;
1033 assert(AArch64FI &&
"No MachineFunctionInfo for this function!");
1038 if (RegToId.empty())
1049 unsigned NbReg = RegToId.size();
1050 bool Modified =
false;
1053 InstrToInstrs *ColorOpToReachedUses =
new InstrToInstrs[NbReg];
1057 reachingDef(MF, ColorOpToReachedUses, RegToId,
true, DummyOp);
1058 DEBUG(
dbgs() <<
"ADRP reaching defs\n");
1063 InstrToInstrs ADRPToReachingDefs;
1068 delete[] ColorOpToReachedUses;
1071 ColorOpToReachedUses =
new InstrToInstrs[NbReg];
1074 reachingDef(MF, ColorOpToReachedUses, RegToId,
false, DummyOp);
1079 InstrToInstrs UsesToReachingDefs;
1083 computeOthers(UsesToReachingDefs, ColorOpToReachedUses, *AArch64FI, RegToId,
1085 delete[] ColorOpToReachedUses;
1096 return new AArch64CollectLOH();
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
void push_back(const T &Elt)
const_iterator end(StringRef path)
Get end iterator over path.
static bool isCandidateLoad(const MachineInstr *Instr)
Check whether the given instruction can be the end of a LOH chain involving a load.
MachineInstr * CreateMachineInstr(const MCInstrDesc &MCID, DebugLoc DL, bool NoImp=false)
CreateMachineInstr - Allocate a new MachineInstr.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
AArch64FunctionInfo - This class is derived from MachineFunctionInfo and contains private AArch64-spe...
STATISTIC(NumFunctions,"Total number of functions")
static SetOfMachineInstr & getUses(InstrToInstrs *sets, unsigned reg, const MachineInstr &MI)
Given a couple (reg, MI) get the corresponding set of instructions from the the given "sets"...
Address of indexed Jump Table for switch.
Adrp _v -> Add _v -> Ldr.
This class implements a map that also provides access to all stored values in a deterministic order...
iv Induction Variable Users
static void collectInvolvedReg(const MachineFunction &MF, MapRegToId &RegToId, MapIdToReg &IdToReg, const TargetRegisterInfo *TRI)
Look for every register defined by potential LOHs candidates.
aarch64 collect AArch64 Collect Linker Optimization Hint(LOH)"
FunctionPass * createAArch64CollectLOHPass()
createAArch64CollectLOHPass - returns an instance of the Statistic for linker optimization pass...
COPY - Target-independent register copy.
Adrp _v -> Ldr _v -> Ldr.
AnalysisUsage & addRequired()
#define INITIALIZE_PASS_DEPENDENCY(depName)
static cl::opt< bool > PreCollectRegister("aarch64-collect-loh-pre-collect-register", cl::Hidden, cl::desc("Restrict analysis to registers invovled"" in LOHs"), cl::init(true))
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
static bool canDefBePartOfLOH(const MachineInstr *Def)
Answer the following question: Can Def be one of the definition involved in a part of a LOH...
A Use represents the edge between a Value definition and its users.
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Reg
All possible values of the reg field in the ModR/M byte.
void initializeAArch64CollectLOHPass(PassRegistry &)
PrintReg - Helper class for printing registers on a raw_ostream.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
This class provides the core functionality of linking in LLVM.
static cl::opt< bool > BasicBlockScopeOnly("aarch64-collect-loh-bb-only", cl::Hidden, cl::desc("Restrict analysis at basic block scope"), cl::init(true))
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
TargetInstrInfo - Interface to description of machine instruction set.
Address of a global value.
initializer< Ty > init(const Ty &Val)
unsigned getTargetFlags() const
static void reachedUsesToDefs(InstrToInstrs &UseToReachingDefs, const InstrToInstrs *ColorOpToReachedUses, const MapRegToId &RegToId, bool ADRPMode=false)
Given the result of a reaching definition algorithm in ColorOpToReachedUses, Build the Use to Defs in...
static bool isCandidate(const MachineInstr *Instr, const InstrToInstrs &UseToDefs, const MachineDominatorTree *MDT)
Check whether the given instruction is a LOH candidate.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
void print(raw_ostream &OS, bool SkipOpers=false) const
static void printReachingDef(const InstrToInstrs *ColorOpToReachedUses, unsigned NbReg, const TargetRegisterInfo *TRI, const MapIdToReg &IdToReg)
print the result of the reaching definition algorithm.
const MachineOperand & getOperand(unsigned i) const
MCRegAliasIterator enumerates all registers aliasing Reg.
Represent the analysis usage information of a pass.
MCLOHType
Linker Optimization Hint Type.
Address of a basic block.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
FunctionPass class - This class is used to implement most global optimizations.
static bool supportLoadFromLiteral(const MachineInstr *Instr)
Check whether the given instruction can load a litteral.
iterator_range< pred_iterator > predecessors()
void DeleteMachineInstr(MachineInstr *MI)
DeleteMachineInstr - Delete the given MachineInstr.
static void initReachingDef(const MachineFunction &MF, InstrToInstrs *ColorOpToReachedUses, BlockToInstrPerColor &Gen, BlockToRegSet &Kill, BlockToSetOfInstrsPerColor &ReachableUses, const MapRegToId &RegToId, const MachineInstr *DummyOp, bool ADRPMode)
Initialize the reaching definition algorithm: For each basic block BB in MF, record: ...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static void reachingDef(const MachineFunction &MF, InstrToInstrs *ColorOpToReachedUses, const MapRegToId &RegToId, bool ADRPMode=false, const MachineInstr *DummyOp=nullptr)
Reaching definition algorithm.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
INITIALIZE_PASS_BEGIN(AArch64CollectLOH,"aarch64-collect-loh","AArch64 Collect Linker Optimization Hint (LOH)", false, false) INITIALIZE_PASS_END(AArch64CollectLOH
static void reachingDefAlgorithm(const MachineFunction &MF, InstrToInstrs *ColorOpToReachedUses, BlockToSetOfInstrsPerColor &In, BlockToSetOfInstrsPerColor &Out, BlockToInstrPerColor &Gen, BlockToRegSet &Kill, BlockToSetOfInstrsPerColor &ReachableUses, unsigned NbReg)
Reaching def core algorithm: while an Out has changed for each bb for each color In[bb][color] = U Ou...
Adrp _v -> Add _v -> Str.
void addLOHDirective(MCLOHType Kind, const MILOHArgs &Args)
Add a LOH directive of this Kind and this Args.
MachineOperand class - Representation of each machine instruction operand.
static void computeADRP(const InstrToInstrs &UseToDefs, AArch64FunctionInfo &AArch64FI, const MachineDominatorTree *MDT)
Based on the use to defs information (in ADRPMode), compute the opportunities of LOH ADRP-related...
aarch64 collect AArch64 Collect Linker Optimization static false SetOfMachineInstr & getSet(BlockToSetOfInstrsPerColor &sets, const MachineBasicBlock &MBB, unsigned reg, unsigned nbRegs)
Given a couple (MBB, reg) get the corresponding set of instruction from the given "sets"...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
void setPreservesAll()
Set by analyses that do not transform their input at all.
Representation of each machine instruction.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
Adrp xY, _v1 -> Adrp xY, _v2.
Adrp _v -> Ldr _v -> Str.
unsigned getReg() const
getReg - Returns the register number.
const ARM::ArchExtKind Kind
virtual const TargetInstrInfo * getInstrInfo() const
A vector that has set insertion semantics.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
static void computeOthers(const InstrToInstrs &UseToDefs, const InstrToInstrs *DefsPerColorToUses, AArch64FunctionInfo &AArch64FI, const MapRegToId &RegToId, const MachineDominatorTree *MDT)
Based on the use to defs information (in non-ADRPMode), compute the opportunities of LOH non-ADRP-rel...
Address of indexed Constant in Constant Pool.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
aarch64 collect AArch64 Collect Linker Optimization false
bool dominates(const MachineDomTreeNode *A, const MachineDomTreeNode *B) const
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
static bool registerADRCandidate(const MachineInstr &Use, const InstrToInstrs &UseToDefs, const InstrToInstrs *DefsPerColorToUses, AArch64FunctionInfo &AArch64FI, SetOfMachineInstr *InvolvedInLOHs, const MapRegToId &RegToId)
static bool isCandidateStore(const MachineInstr *Instr)
Check whether the given instruction can the end of a LOH chain involving a store. ...