LLVM  3.7.0
Public Types | Public Member Functions | List of all members
llvm::SIRegisterInfo Struct Reference

#include <SIRegisterInfo.h>

Inheritance diagram for llvm::SIRegisterInfo:
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Collaboration diagram for llvm::SIRegisterInfo:
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Public Types

enum  PreloadedValue {
  TGID_X, TGID_Y, TGID_Z, SCRATCH_WAVE_OFFSET,
  SCRATCH_PTR, INPUT_PTR, TIDIG_X, TIDIG_Y,
  TIDIG_Z
}
 

Public Member Functions

 SIRegisterInfo ()
 
BitVector getReservedRegs (const MachineFunction &MF) const override
 
unsigned getRegPressureSetLimit (const MachineFunction &MF, unsigned Idx) const override
 
bool requiresRegisterScavenging (const MachineFunction &Fn) const override
 
void eliminateFrameIndex (MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const override
 
const TargetRegisterClassgetCFGStructurizerRegClass (MVT VT) const override
 get the register class of the specified type to use in the CFGStructurizer More...
 
unsigned getHWRegIndex (unsigned Reg) const override
 
const TargetRegisterClassgetPhysRegClass (unsigned Reg) const
 Return the 'base' register class for this register. More...
 
bool isSGPRClass (const TargetRegisterClass *RC) const
 
bool isSGPRClassID (unsigned RCID) const
 
bool hasVGPRs (const TargetRegisterClass *RC) const
 
const TargetRegisterClassgetEquivalentVGPRClass (const TargetRegisterClass *SRC) const
 
const TargetRegisterClassgetSubRegClass (const TargetRegisterClass *RC, unsigned SubIdx) const
 
unsigned getPhysRegSubReg (unsigned Reg, const TargetRegisterClass *SubRC, unsigned Channel) const
 Channel This is the register channel (e.g. More...
 
bool opCanUseLiteralConstant (unsigned OpType) const
 
bool opCanUseInlineConstant (unsigned OpType) const
 
unsigned getPreloadedValue (const MachineFunction &MF, enum PreloadedValue Value) const
 Returns the physical register that Value is stored in. More...
 
unsigned getNumVGPRsAllowed (unsigned WaveCount) const
 Give the maximum number of VGPRs that can be used by WaveCount concurrent waves. More...
 
unsigned getNumSGPRsAllowed (AMDGPUSubtarget::Generation gen, unsigned WaveCount) const
 Give the maximum number of SGPRs that can be used by WaveCount concurrent waves. More...
 
unsigned findUnusedRegister (const MachineRegisterInfo &MRI, const TargetRegisterClass *RC) const
 Returns a register that is not used at any point in the function. More...
 
- Public Member Functions inherited from llvm::AMDGPURegisterInfo
 AMDGPURegisterInfo ()
 
BitVector getReservedRegs (const MachineFunction &MF) const override
 
unsigned getSubRegFromChannel (unsigned Channel) const
 
const MCPhysReggetCalleeSavedRegs (const MachineFunction *MF) const override
 
void eliminateFrameIndex (MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const override
 
unsigned getFrameRegister (const MachineFunction &MF) const override
 
unsigned getIndirectSubReg (unsigned IndirectIndex) const
 

Additional Inherited Members

- Static Public Attributes inherited from llvm::AMDGPURegisterInfo
static const MCPhysReg CalleeSavedReg = AMDGPU::NoRegister
 

Detailed Description

Definition at line 25 of file SIRegisterInfo.h.

Member Enumeration Documentation

Enumerator
TGID_X 
TGID_Y 
TGID_Z 
SCRATCH_WAVE_OFFSET 
SCRATCH_PTR 
INPUT_PTR 
TIDIG_X 
TIDIG_Y 
TIDIG_Z 

Definition at line 94 of file SIRegisterInfo.h.

Constructor & Destructor Documentation

SIRegisterInfo::SIRegisterInfo ( )

Definition at line 27 of file SIRegisterInfo.cpp.

Member Function Documentation

void SIRegisterInfo::eliminateFrameIndex ( MachineBasicBlock::iterator  MI,
int  SPAdj,
unsigned  FIOperandNum,
RegScavenger RS 
) const
override
unsigned SIRegisterInfo::findUnusedRegister ( const MachineRegisterInfo MRI,
const TargetRegisterClass RC 
) const

Returns a register that is not used at any point in the function.

If all registers are used, then this function will return

Definition at line 498 of file SIRegisterInfo.cpp.

References llvm::TargetRegisterClass::begin(), llvm::TargetRegisterClass::end(), I, and llvm::MachineRegisterInfo::isPhysRegUsed().

Referenced by llvm::SIInstrInfo::calculateLDSSpillAddress(), and llvm::SIMachineFunctionInfo::getSpilledReg().

const TargetRegisterClass * SIRegisterInfo::getCFGStructurizerRegClass ( MVT  VT) const
overridevirtual

get the register class of the specified type to use in the CFGStructurizer

Reimplemented from llvm::AMDGPURegisterInfo.

Definition at line 326 of file SIRegisterInfo.cpp.

References llvm::MVT::i32, and llvm::MVT::SimpleTy.

const TargetRegisterClass * SIRegisterInfo::getEquivalentVGPRClass ( const TargetRegisterClass SRC) const
Returns
A VGPR reg class with the same width as SRC

Definition at line 372 of file SIRegisterInfo.cpp.

References hasVGPRs().

Referenced by llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::legalizeOpWithMove(), and llvm::SIInstrInfo::moveToVALU().

unsigned SIRegisterInfo::getHWRegIndex ( unsigned  Reg) const
overridevirtual

Reimplemented from llvm::AMDGPURegisterInfo.

Definition at line 334 of file SIRegisterInfo.cpp.

Referenced by getPhysRegSubReg().

unsigned SIRegisterInfo::getNumSGPRsAllowed ( AMDGPUSubtarget::Generation  gen,
unsigned  WaveCount 
) const

Give the maximum number of SGPRs that can be used by WaveCount concurrent waves.

Definition at line 524 of file SIRegisterInfo.cpp.

References llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS.

Referenced by getRegPressureSetLimit().

unsigned SIRegisterInfo::getNumVGPRsAllowed ( unsigned  WaveCount) const

Give the maximum number of VGPRs that can be used by WaveCount concurrent waves.

Definition at line 509 of file SIRegisterInfo.cpp.

Referenced by getRegPressureSetLimit().

const TargetRegisterClass * SIRegisterInfo::getPhysRegClass ( unsigned  Reg) const

Return the 'base' register class for this register.

e.g. SGPR0 => SReg_32, VGPR => VGPR_32 SGPR0_SGPR1 -> SReg_32, etc.

Definition at line 338 of file SIRegisterInfo.cpp.

References llvm::BaseClass, and llvm::TargetRegisterInfo::isVirtualRegister().

Referenced by llvm::SIInstrInfo::getOpRegClass(), getPhysRegSubReg(), llvm::SIInstrInfo::isOperandLegal(), and isVGPR().

unsigned SIRegisterInfo::getPhysRegSubReg ( unsigned  Reg,
const TargetRegisterClass SubRC,
unsigned  Channel 
) const

Channel This is the register channel (e.g.

a value from 0-16), not the SubReg index.

Returns
The sub-register of Reg that is in Channel.

Definition at line 406 of file SIRegisterInfo.cpp.

References getHWRegIndex(), getPhysRegClass(), llvm::TargetRegisterClass::getRegister(), llvm::TargetRegisterClass::getSize(), and llvm_unreachable.

Referenced by eliminateFrameIndex(), and llvm::SITargetLowering::LowerFormalArguments().

unsigned SIRegisterInfo::getPreloadedValue ( const MachineFunction MF,
enum PreloadedValue  Value 
) const
unsigned SIRegisterInfo::getRegPressureSetLimit ( const MachineFunction MF,
unsigned  Idx 
) const
override
BitVector SIRegisterInfo::getReservedRegs ( const MachineFunction MF) const
override
const TargetRegisterClass * SIRegisterInfo::getSubRegClass ( const TargetRegisterClass RC,
unsigned  SubIdx 
) const
Returns
The register class that is used for a sub-register of RC for the given SubIdx. If SubIdx equals NoSubRegister, RC will be returned.

Definition at line 392 of file SIRegisterInfo.cpp.

References isSGPRClass().

bool SIRegisterInfo::hasVGPRs ( const TargetRegisterClass RC) const
bool llvm::SIRegisterInfo::isSGPRClass ( const TargetRegisterClass RC) const
inline
bool llvm::SIRegisterInfo::isSGPRClassID ( unsigned  RCID) const
inline
Returns
true if this class ID contains only SGPR registers

Definition at line 59 of file SIRegisterInfo.h.

References getRegClass(), and isSGPRClass().

bool SIRegisterInfo::opCanUseInlineConstant ( unsigned  OpType) const
Returns
True if operands defined with this operand type can accept an inline constant. i.e. An integer value in the range (-16, 64) or -4.0f, -2.0f, -1.0f, -0.5f, 0.0f, 0.5f, 1.0f, 2.0f, 4.0f.

Definition at line 459 of file SIRegisterInfo.cpp.

References opCanUseLiteralConstant(), and llvm::AMDGPU::OPERAND_REG_INLINE_C.

Referenced by llvm::SIInstrInfo::isImmOperandLegal().

bool SIRegisterInfo::opCanUseLiteralConstant ( unsigned  OpType) const
Returns
True if operands defined with this operand type can accept a literal constant (i.e. any 32-bit immediate).

Definition at line 455 of file SIRegisterInfo.cpp.

References llvm::AMDGPU::OPERAND_REG_IMM32.

Referenced by llvm::SIInstrInfo::isImmOperandLegal(), and opCanUseInlineConstant().

bool SIRegisterInfo::requiresRegisterScavenging ( const MachineFunction Fn) const
override

The documentation for this struct was generated from the following files: