11 #define DEBUG_TYPE "hexagon-pei"
124 using namespace llvm;
144 cl::desc(
"Enable stack frame shrink wrapping"));
155 if (Reg < Hexagon::D0 || Reg > Hexagon::D15)
161 if (*SubRegs > RegNo)
164 if (!RegNo || *SubRegs < RegNo)
172 unsigned getMaxCalleeSavedReg(
const std::vector<CalleeSavedInfo> &CSI,
174 assert(Hexagon::R1 > 0 &&
175 "Assume physical registers are encoded as positive integers");
179 unsigned Max = getMax32BitSubRegister(CSI[0].
getReg(), TRI);
180 for (
unsigned I = 1, E = CSI.size();
I < E; ++
I) {
181 unsigned Reg = getMax32BitSubRegister(CSI[
I].
getReg(), TRI);
191 for (
auto &
I : MBB) {
198 case Hexagon::ALIGNA:
214 unsigned R = MO.getReg();
230 unsigned RetOpc = I->getOpcode();
231 return RetOpc == Hexagon::TCRETURNi || RetOpc == Hexagon::TCRETURNr;
250 static unsigned ShrinkCounter = 0;
271 for (RPOTType::rpo_iterator I = RPOT.begin(), E = RPOT.end(); I != E; ++
I)
272 RPO[(*I)->getNumber()] = RPON++;
278 unsigned BN = RPO[I.getNumber()];
279 for (
auto SI = I.succ_begin(), SE = I.succ_end();
SI != SE; ++
SI) {
281 if (RPO[(*SI)->getNumber()] <= BN)
290 for (
const MCPhysReg *
P = HRI.getCalleeSavedRegs(&MF); *
P; ++
P)
294 if (needsStackFrame(I, CSR))
298 dbgs() <<
"Blocks needing SF: {";
299 for (
auto &B : SFBlocks)
300 dbgs() <<
" BB#" << B->getNumber();
304 if (SFBlocks.empty())
309 for (
unsigned i = 1, n = SFBlocks.size(); i < n; ++i) {
315 for (
unsigned i = 1, n = SFBlocks.size(); i < n; ++i) {
321 dbgs() <<
"Computed dom block: BB#";
323 else dbgs() <<
"<null>";
324 dbgs() <<
", computed pdom block: BB#";
326 else dbgs() <<
"<null>";
334 DEBUG(
dbgs() <<
"Dom block does not dominate pdom block\n");
338 DEBUG(
dbgs() <<
"PDom block does not post-dominate dom block\n");
357 assert(&MF.
front() == &MBB &&
"Shrink-wrapping not yet supported");
363 findShrunkPrologEpilog(MF, PrologB, EpilogB);
365 insertCSRSpillsInBlock(*PrologB, CSI, HRI);
366 insertPrologueInBlock(*PrologB);
369 insertCSRRestoresInBlock(*EpilogB, CSI, HRI);
370 insertEpilogueInBlock(*EpilogB);
373 if (!B.empty() && B.back().isReturn())
374 insertCSRRestoresInBlock(B, CSI, HRI);
377 if (!B.empty() && B.back().isReturn())
378 insertEpilogueInBlock(B);
414 unsigned SP = HRI.getStackRegister();
421 for (
auto MI : AdjustRegs) {
423 expandAlloca(MI, HII, SP, MaxCF);
434 if (!NoOpt && !FuncInfo->hasClobberLR() && !
hasFP(MF))
439 const unsigned int ALLOCFRAME_MAX = 16384;
447 if (NumBytes >= ALLOCFRAME_MAX) {
449 BuildMI(MBB, InsertPt, dl, HII.
get(Hexagon::S2_allocframe))
455 unsigned CallerSavedReg = HRI.getFirstCallerSavedNonParamReg();
456 BuildMI(MBB, InsertPt, dl, HII.
get(Hexagon::CONST32_Int_Real),
457 CallerSavedReg).addImm(NumBytes);
458 BuildMI(MBB, InsertPt, dl, HII.
get(Hexagon::A2_sub),
SP)
462 BuildMI(MBB, InsertPt, dl, HII.
get(Hexagon::S2_allocframe))
468 BuildMI(MBB, InsertPt, dl, HII.
get(Hexagon::A2_andir),
SP)
470 .
addImm(-int64_t(MaxAlign));
473 if (needsFrameMoves) {
478 unsigned DwFPReg = HRI.getDwarfRegNum(HRI.getFrameRegister(),
true);
479 unsigned DwRAReg = HRI.getDwarfRegNum(HRI.getRARegister(),
true);
483 FrameLabel, DwFPReg, -8));
485 .addCFIIndex(CFIIndex);
489 FrameLabel, DwRAReg, -4));
491 .addCFIIndex(CFIIndex);
495 FrameLabel, DwFPReg, -8));
497 .addCFIIndex(CFIIndex);
499 unsigned int regsToMove[] = {
500 Hexagon::R1, Hexagon::R0, Hexagon::R3,
Hexagon::R2,
501 Hexagon::R17, Hexagon::R16, Hexagon::R19, Hexagon::R18,
502 Hexagon::R21, Hexagon::R20, Hexagon::R23, Hexagon::R22,
503 Hexagon::R25, Hexagon::R24, Hexagon::R27, Hexagon::R26,
504 Hexagon::D0, Hexagon::D1, Hexagon::D8, Hexagon::D9, Hexagon::D10,
505 Hexagon::D11, Hexagon::D12, Hexagon::D13, Hexagon::NoRegister
510 for (
unsigned i = 0; regsToMove[i] != Hexagon::NoRegister; ++i) {
511 for (
unsigned I = 0, E = CSI.size(); I < E; ++
I) {
512 if (CSI[I].
getReg() == regsToMove[i]) {
516 if (regsToMove[i] < Hexagon::D0 || regsToMove[i] > Hexagon::D15) {
517 unsigned DwarfReg = HRI.getDwarfRegNum(regsToMove[i],
true);
522 .addCFIIndex(CFIIndex);
529 unsigned HiReg = getMax32BitSubRegister(regsToMove[i], HRI);
530 unsigned LoReg = getMax32BitSubRegister(regsToMove[i], HRI,
false);
531 unsigned HiDwarfReg = HRI.getDwarfRegNum(HiReg,
true);
532 unsigned LoDwarfReg = HRI.getDwarfRegNum(LoReg,
true);
535 HiDwarfReg, Offset+4));
537 .addCFIIndex(HiCFIIndex);
540 LoDwarfReg, Offset));
542 .addCFIIndex(LoCFIIndex);
563 unsigned SP = HRI.getStackRegister();
566 for (
auto &I : MBB) {
572 unsigned RetOpc = RetI ? RetI->
getOpcode() : 0;
576 if (InsertPt != MBB.end())
577 DL = InsertPt->getDebugLoc();
578 else if (!MBB.empty())
579 DL = std::prev(MBB.end())->getDebugLoc();
582 if (RetOpc == Hexagon::EH_RETURN_JMPR) {
583 BuildMI(MBB, InsertPt, DL, HII.
get(Hexagon::L2_deallocframe));
584 BuildMI(MBB, InsertPt, DL, HII.
get(Hexagon::A2_add),
SP)
592 if (RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4) {
596 while (It != MBB.end()) {
608 bool NeedsDeallocframe =
true;
609 if (!MBB.empty() && InsertPt != MBB.begin()) {
611 unsigned COpc = PrevIt->getOpcode();
612 if (COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4)
613 NeedsDeallocframe =
false;
616 if (!NeedsDeallocframe)
622 BuildMI(MBB, InsertPt, DL, HII.
get(Hexagon::L2_deallocframe));
625 unsigned NewOpc = Hexagon::L4_return;
650 const char * V4SpillToMemoryFunctions[] = {
651 "__save_r16_through_r17",
652 "__save_r16_through_r19",
653 "__save_r16_through_r21",
654 "__save_r16_through_r23",
655 "__save_r16_through_r25",
656 "__save_r16_through_r27" };
658 const char * V4SpillFromMemoryFunctions[] = {
659 "__restore_r16_through_r17_and_deallocframe",
660 "__restore_r16_through_r19_and_deallocframe",
661 "__restore_r16_through_r21_and_deallocframe",
662 "__restore_r16_through_r23_and_deallocframe",
663 "__restore_r16_through_r25_and_deallocframe",
664 "__restore_r16_through_r27_and_deallocframe" };
666 const char * V4SpillFromMemoryTailcallFunctions[] = {
667 "__restore_r16_through_r17_and_deallocframe_before_tailcall",
668 "__restore_r16_through_r19_and_deallocframe_before_tailcall",
669 "__restore_r16_through_r21_and_deallocframe_before_tailcall",
670 "__restore_r16_through_r23_and_deallocframe_before_tailcall",
671 "__restore_r16_through_r25_and_deallocframe_before_tailcall",
672 "__restore_r16_through_r27_and_deallocframe_before_tailcall"
675 const char **SpillFunc =
nullptr;
679 SpillFunc = V4SpillToMemoryFunctions;
682 SpillFunc = V4SpillFromMemoryFunctions;
685 SpillFunc = V4SpillFromMemoryTailcallFunctions;
688 assert(SpillFunc &&
"Unknown spill kind");
712 unsigned MaxReg,
bool IsDef) {
714 for (
unsigned R = Hexagon::R16; R <= MaxReg; ++R) {
736 if (useSpillFunction(MF, CSI)) {
737 unsigned MaxReg = getMaxCalleeSavedReg(CSI, HRI);
742 BuildMI(MBB, MI, DL, TII.
get(Hexagon::SAVE_REGISTERS_CALL_V4))
743 .addExternalSymbol(SpillFun);
747 for (
unsigned I = 0; I < CSI.size(); ++
I)
752 for (
unsigned i = 0, n = CSI.size(); i < n; ++i) {
753 unsigned Reg = CSI[i].getReg();
758 int FI = CSI[i].getFrameIdx();
777 if (useRestoreFunction(MF, CSI)) {
778 bool HasTC = hasTailCall(MBB) || !hasReturn(MBB);
779 unsigned MaxR = getMaxCalleeSavedReg(CSI, HRI);
789 unsigned ROpc = Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4;
790 DeallocCall =
BuildMI(MBB, MI, DL, TII.
get(ROpc))
791 .addExternalSymbol(RestoreFn);
795 assert(It->isReturn() && std::next(It) == MBB.
end());
796 unsigned ROpc = Hexagon::RESTORE_DEALLOC_RET_JMP_V4;
797 DeallocCall =
BuildMI(MBB, It, DL, TII.
get(ROpc))
798 .addExternalSymbol(RestoreFn);
806 for (
unsigned i = 0; i < CSI.size(); ++i) {
807 unsigned Reg = CSI[i].getReg();
809 int FI = CSI[i].getFrameIdx();
821 assert((Opc == Hexagon::ADJCALLSTACKDOWN || Opc == Hexagon::ADJCALLSTACKUP) &&
822 "Cannot handle this call frame pseudo instruction");
837 if (!HasAlloca || !HasAligna)
853 assert(A <= 8 &&
"Unexpected local frame alignment");
865 for ( ; *CallerSavedRegs; ++CallerSavedRegs) {
871 bool IsCurrentRegUsed =
false;
874 IsCurrentRegUsed =
true;
877 if (IsCurrentRegUsed)
889 bool HexagonFrameLowering::replacePredRegPseudoSpillCode(
MachineFunction &MF)
894 bool HasReplacedPseudoInst =
false;
898 MBBb != MBBe; ++MBBb) {
905 NextII = std::next(MII);
907 if (Opc == Hexagon::STriw_pred) {
908 HasReplacedPseudoInst =
true;
915 assert(Hexagon::PredRegsRegClass.
contains(SrcReg) &&
916 "Not a predicate register");
925 MI->
setDesc(HII.get(Hexagon::S2_storeri_io));
929 }
else if (Opc == Hexagon::LDriw_pred) {
941 assert(Hexagon::PredRegsRegClass.
contains(DestReg) &&
942 "Not a predicate register");
946 MI->
setDesc(HII.get(Hexagon::L2_loadri_io));
954 HasReplacedPseudoInst =
true;
958 return HasReplacedPseudoInst;
968 auto &HRI = *HST.getRegisterInfo();
977 SavedRegs.
set(*CSRegs);
983 bool HasReplacedPseudoInst = replacePredRegPseudoSpillCode(MF);
1013 BitVector SRegs(Hexagon::NUM_TARGET_REGS);
1021 DEBUG(
dbgs() <<
"Initial CS registers: {");
1022 for (
unsigned i = 0, n = CSI.size(); i < n; ++i) {
1023 unsigned R = CSI[i].getReg();
1034 for (
int x = Reserved.find_first(); x >= 0; x = Reserved.find_next(x)) {
1046 BitVector TmpSup(Hexagon::NUM_TARGET_REGS);
1052 for (
int x = TmpSup.find_first(); x >= 0; x = TmpSup.find_next(x)) {
1088 for (
const SpillSlot *S = FixedSlots; S != FixedSlots+NumFixed; ++S) {
1092 int FI = MFI->CreateFixedSpillStackObject(RC->
getSize(), S->Offset);
1093 MinOffset =
std::min(MinOffset, S->Offset);
1095 SRegs[S->Reg] =
false;
1104 int Off = MinOffset - RC->
getSize();
1108 int FI = MFI->CreateFixedSpillStackObject(RC->
getSize(), Off);
1109 MinOffset =
std::min(MinOffset, Off);
1115 dbgs() <<
"CS information: {";
1116 for (
unsigned i = 0, n = CSI.size(); i < n; ++i) {
1117 int FI = CSI[i].getFrameIdx();
1118 int Off = MFI->getObjectOffset(FI);
1129 bool MissedReg =
false;
1143 void HexagonFrameLowering::expandAlloca(
MachineInstr *AI,
1169 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_sub), Rd)
1174 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_sub),
SP)
1180 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_andir), Rd)
1184 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_andir),
SP)
1195 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_addi), Rd)
1216 if (I.getOpcode() == Hexagon::ALIGNA)
1239 const CSIVect &CSI)
const {
1248 BitVector Regs(Hexagon::NUM_TARGET_REGS);
1249 for (
unsigned i = 0, n = CSI.size(); i < n; ++i) {
1250 unsigned R = CSI[i].getReg();
1251 if (!Hexagon::DoubleRegsRegClass.
contains(R))
1255 int F = Regs.find_first();
1256 if (F != Hexagon::D8)
1259 int N = Regs.find_next(F);
1260 if (N >= 0 && N != F+1)
1270 const CSIVect &CSI)
const {
1271 if (shouldInlineCSR(MF, CSI))
1273 unsigned NumCSI = CSI.size();
1279 return Threshold < NumCSI;
1284 const CSIVect &CSI)
const {
1285 if (shouldInlineCSR(MF, CSI))
1287 unsigned NumCSI = CSI.size();
1290 return Threshold < NumCSI;
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
void push_back(const T &Elt)
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
The memory access writes data.
static void addCalleeSaveRegistersAsImpOperand(MachineInstr *Inst, unsigned MaxReg, bool IsDef)
Adds all callee-saved registers up to MaxReg to the instruction.
void mapLocalFrameObject(int ObjectIndex, int64_t Offset)
Map a frame index into the local object block.
static cl::opt< int > SpillFuncThresholdOs("spill-func-threshold-Os", cl::Hidden, cl::desc("Specify Os spill func threshold"), cl::init(1), cl::ZeroOrMore)
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
int getNumber() const
getNumber - MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a M...
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
MachineBasicBlock * findNearestCommonDominator(MachineBasicBlock *A, MachineBasicBlock *B)
int find_next(unsigned Prev) const
find_next - Returns the index of the next set bit following the "Prev" bit.
iterator getFirstTerminator()
getFirstTerminator - returns an iterator to the first terminator instruction of this basic block...
Describe properties that are true of each instruction in the target description file.
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
static void dump_registers(BitVector &Regs, const TargetRegisterInfo &TRI)
void addLiveIn(unsigned Reg)
Adds the specified register as a live in.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Hexagon target-specific information for each MachineFunction.
const SpillSlot * getCalleeSavedSpillSlots(unsigned &NumEntries) const override
getCalleeSavedSpillSlots - This method returns a pointer to an array of pairs, that contains an entry...
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
static cl::opt< int > SpillFuncThreshold("spill-func-threshold", cl::Hidden, cl::desc("Specify O2(not Os) spill func threshold"), cl::init(6), cl::ZeroOrMore)
bool hasAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return true if the attribute exists at the given index.
iterator_range< mop_iterator > operands()
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, unsigned f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
getMachineMemOperand - Allocate a new MachineMemOperand.
int getFrameIndexOffset(const MachineFunction &MF, int FI) const override
getFrameIndexOffset - Returns the displacement from the frame register to the stack frame of the spec...
StringRef getName() const
Return a constant reference to the value's name.
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
COPY - Target-independent register copy.
int64_t getLocalFrameSize() const
Get the size of the local object blob.
unsigned getSize() const
getSize - Return the size of the register in bytes, which is also the size of a stack slot allocated ...
MachineInstr * getAlignaInstr(MachineFunction &MF) const
MachineMemOperand - A description of a memory reference used in the backend.
void setLocalFrameSize(int64_t sz)
Set the size of the local object blob.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
void setUseLocalStackAllocationBlock(bool v)
setUseLocalStackAllocationBlock - Set whether the local allocation blob should be allocated together ...
MCSuperRegIterator enumerates all super-registers of Reg.
DILocation * get() const
Get the underlying DILocation.
const HexagonInstrInfo * TII
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const HexagonRegisterInfo * getRegisterInfo() const override
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
Reg
All possible values of the reg field in the ModR/M byte.
static cl::opt< bool > EnableShrinkWrapping("hexagon-shrink-frame", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("Enable stack frame shrink wrapping"))
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
Number of individual test Apply this number of consecutive mutations to each input exit after the first new interesting input is found the minimized corpus is saved into the first input directory Number of jobs to run If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
bool hasDebugInfo() const
hasDebugInfo - Returns true if valid debug info is present.
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
PrintReg - Helper class for printing registers on a raw_ostream.
const MachineBasicBlock & front() const
const HexagonRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
static bool isMinSize(const MachineFunction &MF)
unsigned getLocalFrameMaxAlign() const
Return the required alignment of the local object blob.
unsigned LLVM_ATTRIBUTE_UNUSED_RESULT addFrameInst(const MCCFIInstruction &Inst)
void setLocalFrameMaxAlign(unsigned Align)
Required alignment of the local object blob, which is the strictest alignment of any object in it...
const std::vector< MCCFIInstruction > & getFrameInstructions() const
Returns a reference to a list of cfi instructions in the current function's prologue.
iterator getLastNonDebugInstr()
getLastNonDebugInstr - returns an iterator to the last non-debug instruction in the basic block...
bool needsAligna(const MachineFunction &MF) const
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
MachineBasicBlock * findNearestCommonDominator(MachineBasicBlock *A, MachineBasicBlock *B)
findNearestCommonDominator - Find nearest common dominator basic block for basic block A and B...
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
Perform most of the PEI work here:
unsigned getKillRegState(bool B)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
bool isSpillSlotObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a spill slot.
const MachineBasicBlock * getParent() const
TargetInstrInfo - Interface to description of machine instruction set.
const MCPhysReg * getCallerSavedRegs(const MachineFunction *MF) const
bundle_iterator< MachineInstr, instr_iterator > iterator
static bool isOptSize(const MachineFunction &MF)
initializer< Ty > init(const Ty &Val)
MCSymbol * createTempSymbol(bool CanBeUnnamed=true)
Create and return a new assembler temporary symbol with a unique but unspecified name.
static MCCFIInstruction createDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it...
static cl::opt< bool > DisableDeallocRet("disable-hexagon-dealloc-ret", cl::Hidden, cl::desc("Disable Dealloc Return for Hexagon target"))
bool isEHReturnCalleeSaveReg(unsigned Reg) const
unsigned getAlignment() const
getAlignment - Return the minimum required alignment for a register of this class.
void eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
eliminateCallFramePseudoInstr - This method is called during prolog/epilog code insertion to eliminat...
void setStackSize(uint64_t Size)
Set the size of the stack.
const MachineOperand & getOperand(unsigned i) const
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Load the specified register of the given register class from the specified stack frame index...
MCRegAliasIterator enumerates all registers aliasing Reg.
static const char * getSpillFunctionFor(unsigned MaxReg, SpillKind SpillType)
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS=nullptr) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
virtual void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Store the specified register of the given register class to the specified stack frame index...
int CreateSpillStackObject(uint64_t Size, unsigned Alignment)
Create a new statically sized stack object that represents a spill slot, returning a nonnegative iden...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
MCSubRegIterator enumerates all sub-registers of Reg.
MachinePointerInfo - This class contains a discriminated union of information about pointers in memor...
bool dominates(const MachineDomTreeNode *A, const MachineDomTreeNode *B) const
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
void setIsKill(bool Val=true)
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
bool isDeadObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a dead object.
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
bool hasCalls() const
Return true if the current function has any function calls.
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
const std::vector< MachineInstr * > & getAllocaAdjustInsts()
const MCContext & getContext() const
PostDominatorTree Class - Concrete subclass of DominatorTree that is used to compute the post-dominat...
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call...
bool needsUnwindTableEntry() const
True if this function needs an unwind table.
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
bool assignCalleeSavedSpillSlots(MachineFunction &MF, const TargetRegisterInfo *TRI, std::vector< CalleeSavedInfo > &CSI) const override
assignCalleeSavedSpillSlots - Allows target to override spill slot assignment logic.
static cl::opt< int > NumberScavengerSlots("number-scavenger-slots", cl::Hidden, cl::desc("Set the number of scavenger slots"), cl::init(2), cl::ZeroOrMore)
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
AttributeSet getAttributes() const
Return the attribute list for this Function.
bool hasClobberLR() const
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a ...
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
getMinimalPhysRegClass - Returns the Register Class of a physical register of the given type...
static cl::opt< unsigned > ShrinkLimit("shrink-frame-limit", cl::init(UINT_MAX), cl::Hidden, cl::ZeroOrMore, cl::desc("Max count of stack frame ""shrink-wraps"))
bool runOnMachineFunction(MachineFunction &F) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
uint64_t RoundUpToAlignment(uint64_t Value, uint64_t Align)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
bundle_iterator< const MachineInstr, const_instr_iterator > const_iterator
void copyImplicitOps(MachineFunction &MF, const MachineInstr *MI)
Copy implicit register operands from specified instruction to this instruction.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
void setReg(unsigned Reg)
Change the register this operand corresponds to.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
void setMaxCallFrameSize(unsigned S)
bool isCall(QueryType Type=AnyInBundle) const
static bool needToReserveScavengingSpillSlots(MachineFunction &MF, const HexagonRegisterInfo &HRI)
Returns true if there is no caller saved registers available.
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
static int const Threshold
TODO: Write a new FunctionPass AliasAnalysis so that it can keep a cache.
unsigned getReg() const
getReg - Returns the register number.
const ARM::ArchExtKind Kind
virtual const TargetInstrInfo * getInstrInfo() const
const HexagonInstrInfo * getInstrInfo() const override
bool isPhysRegUsed(unsigned Reg) const
isPhysRegUsed - Return true if the specified register is used in this function.
BasicBlockListType::iterator iterator
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
bool isPowerOf2_32(uint32_t Value)
isPowerOf2_32 - This function returns true if the argument is a power of two > 0. ...
MachineModuleInfo & getMMI() const
int getObjectIndexEnd() const
Return one past the maximum frame object index.
#define LLVM_FUNCTION_NAME
LLVM_FUNCTION_NAME
bool dominates(const MachineDomTreeNode *A, const MachineDomTreeNode *B) const
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
MachineModuleInfo - This class contains meta information specific to a module.
Function must be optimized for size first.