LLVM  3.7.0
LiveIntervalAnalysis.h
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1 //===-- LiveIntervalAnalysis.h - Live Interval Analysis ---------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the LiveInterval analysis pass. Given some numbering of
11 // each the machine instructions (in this implemention depth-first order) an
12 // interval [i, j) is said to be a live interval for register v if there is no
13 // instruction with number j' > j such that v is live at j' and there is no
14 // instruction with number i' < i such that v is live at i'. In this
15 // implementation intervals can have holes, i.e. an interval might look like
16 // [1,20), [50,65), [1000,1001).
17 //
18 //===----------------------------------------------------------------------===//
19 
20 #ifndef LLVM_CODEGEN_LIVEINTERVALANALYSIS_H
21 #define LLVM_CODEGEN_LIVEINTERVALANALYSIS_H
22 
23 #include "llvm/ADT/IndexedMap.h"
24 #include "llvm/ADT/SmallVector.h"
29 #include "llvm/Support/Allocator.h"
32 #include <cmath>
33 #include <iterator>
34 
35 namespace llvm {
36 
37 extern cl::opt<bool> UseSegmentSetForPhysRegs;
38 
39  class AliasAnalysis;
40  class BitVector;
41  class BlockFrequency;
42  class LiveRangeCalc;
43  class LiveVariables;
44  class MachineDominatorTree;
45  class MachineLoopInfo;
46  class TargetRegisterInfo;
47  class MachineRegisterInfo;
48  class TargetInstrInfo;
49  class TargetRegisterClass;
50  class VirtRegMap;
51  class MachineBlockFrequencyInfo;
52 
54  MachineFunction* MF;
56  const TargetRegisterInfo* TRI;
57  const TargetInstrInfo* TII;
58  AliasAnalysis *AA;
59  SlotIndexes* Indexes;
60  MachineDominatorTree *DomTree;
61  LiveRangeCalc *LRCalc;
62 
63  /// Special pool allocator for VNInfo's (LiveInterval val#).
64  ///
65  VNInfo::Allocator VNInfoAllocator;
66 
67  /// Live interval pointers for all the virtual registers.
69 
70  /// RegMaskSlots - Sorted list of instructions with register mask operands.
71  /// Always use the 'r' slot, RegMasks are normal clobbers, not early
72  /// clobbers.
73  SmallVector<SlotIndex, 8> RegMaskSlots;
74 
75  /// RegMaskBits - This vector is parallel to RegMaskSlots, it holds a
76  /// pointer to the corresponding register mask. This pointer can be
77  /// recomputed as:
78  ///
79  /// MI = Indexes->getInstructionFromIndex(RegMaskSlot[N]);
80  /// unsigned OpNum = findRegMaskOperand(MI);
81  /// RegMaskBits[N] = MI->getOperand(OpNum).getRegMask();
82  ///
83  /// This is kept in a separate vector partly because some standard
84  /// libraries don't support lower_bound() with mixed objects, partly to
85  /// improve locality when searching in RegMaskSlots.
86  /// Also see the comment in LiveInterval::find().
88 
89  /// For each basic block number, keep (begin, size) pairs indexing into the
90  /// RegMaskSlots and RegMaskBits arrays.
91  /// Note that basic block numbers may not be layout contiguous, that's why
92  /// we can't just keep track of the first register mask in each basic
93  /// block.
95 
96  /// Keeps a live range set for each register unit to track fixed physreg
97  /// interference.
98  SmallVector<LiveRange*, 0> RegUnitRanges;
99 
100  public:
101  static char ID; // Pass identification, replacement for typeid
102  LiveIntervals();
103  ~LiveIntervals() override;
104 
105  // Calculate the spill weight to assign to a single instruction.
106  static float getSpillWeight(bool isDef, bool isUse,
107  const MachineBlockFrequencyInfo *MBFI,
108  const MachineInstr *Instr);
109 
111  if (hasInterval(Reg))
112  return *VirtRegIntervals[Reg];
113  else
115  }
116 
117  const LiveInterval &getInterval(unsigned Reg) const {
118  return const_cast<LiveIntervals*>(this)->getInterval(Reg);
119  }
120 
121  bool hasInterval(unsigned Reg) const {
122  return VirtRegIntervals.inBounds(Reg) && VirtRegIntervals[Reg];
123  }
124 
125  // Interval creation.
127  assert(!hasInterval(Reg) && "Interval already exists!");
128  VirtRegIntervals.grow(Reg);
129  VirtRegIntervals[Reg] = createInterval(Reg);
130  return *VirtRegIntervals[Reg];
131  }
132 
135  computeVirtRegInterval(LI);
136  return LI;
137  }
138 
139  // Interval removal.
140  void removeInterval(unsigned Reg) {
141  delete VirtRegIntervals[Reg];
142  VirtRegIntervals[Reg] = nullptr;
143  }
144 
145  /// Given a register and an instruction, adds a live segment from that
146  /// instruction to the end of its MBB.
148  MachineInstr* startInst);
149 
150  /// shrinkToUses - After removing some uses of a register, shrink its live
151  /// range to just the remaining uses. This method does not compute reaching
152  /// defs for new uses, and it doesn't remove dead defs.
153  /// Dead PHIDef values are marked as unused.
154  /// New dead machine instructions are added to the dead vector.
155  /// Return true if the interval may have been separated into multiple
156  /// connected components.
157  bool shrinkToUses(LiveInterval *li,
158  SmallVectorImpl<MachineInstr*> *dead = nullptr);
159 
160  /// Specialized version of
161  /// shrinkToUses(LiveInterval *li, SmallVectorImpl<MachineInstr*> *dead)
162  /// that works on a subregister live range and only looks at uses matching
163  /// the lane mask of the subregister range.
164  void shrinkToUses(LiveInterval::SubRange &SR, unsigned Reg);
165 
166  /// extendToIndices - Extend the live range of LI to reach all points in
167  /// Indices. The points in the Indices array must be jointly dominated by
168  /// existing defs in LI. PHI-defs are added as needed to maintain SSA form.
169  ///
170  /// If a SlotIndex in Indices is the end index of a basic block, LI will be
171  /// extended to be live out of the basic block.
172  ///
173  /// See also LiveRangeCalc::extend().
174  void extendToIndices(LiveRange &LR, ArrayRef<SlotIndex> Indices);
175 
176 
177  /// If @p LR has a live value at @p Kill, prune its live range by removing
178  /// any liveness reachable from Kill. Add live range end points to
179  /// EndPoints such that extendToIndices(LI, EndPoints) will reconstruct the
180  /// value's live range.
181  ///
182  /// Calling pruneValue() and extendToIndices() can be used to reconstruct
183  /// SSA form after adding defs to a virtual register.
185  SmallVectorImpl<SlotIndex> *EndPoints);
186 
188  return Indexes;
189  }
190 
192  return AA;
193  }
194 
195  /// isNotInMIMap - returns true if the specified machine instr has been
196  /// removed or was never entered in the map.
197  bool isNotInMIMap(const MachineInstr* Instr) const {
198  return !Indexes->hasIndex(Instr);
199  }
200 
201  /// Returns the base index of the given instruction.
203  return Indexes->getInstructionIndex(instr);
204  }
205 
206  /// Returns the instruction associated with the given index.
208  return Indexes->getInstructionFromIndex(index);
209  }
210 
211  /// Return the first index in the given basic block.
213  return Indexes->getMBBStartIdx(mbb);
214  }
215 
216  /// Return the last index in the given basic block.
218  return Indexes->getMBBEndIdx(mbb);
219  }
220 
221  bool isLiveInToMBB(const LiveRange &LR,
222  const MachineBasicBlock *mbb) const {
223  return LR.liveAt(getMBBStartIdx(mbb));
224  }
225 
226  bool isLiveOutOfMBB(const LiveRange &LR,
227  const MachineBasicBlock *mbb) const {
228  return LR.liveAt(getMBBEndIdx(mbb).getPrevSlot());
229  }
230 
232  return Indexes->getMBBFromIndex(index);
233  }
234 
236  Indexes->insertMBBInMaps(MBB);
237  assert(unsigned(MBB->getNumber()) == RegMaskBlocks.size() &&
238  "Blocks must be added in order.");
239  RegMaskBlocks.push_back(std::make_pair(RegMaskSlots.size(), 0));
240  }
241 
243  return Indexes->insertMachineInstrInMaps(MI);
244  }
245 
248  for (MachineBasicBlock::iterator I = B; I != E; ++I)
249  Indexes->insertMachineInstrInMaps(I);
250  }
251 
253  Indexes->removeMachineInstrFromMaps(MI);
254  }
255 
257  Indexes->replaceMachineInstrInMaps(MI, NewMI);
258  }
259 
262  return Indexes->findLiveInMBBs(Start, End, MBBs);
263  }
264 
265  VNInfo::Allocator& getVNInfoAllocator() { return VNInfoAllocator; }
266 
267  void getAnalysisUsage(AnalysisUsage &AU) const override;
268  void releaseMemory() override;
269 
270  /// runOnMachineFunction - pass entry point
271  bool runOnMachineFunction(MachineFunction&) override;
272 
273  /// print - Implement the dump method.
274  void print(raw_ostream &O, const Module* = nullptr) const override;
275 
276  /// intervalIsInOneMBB - If LI is confined to a single basic block, return
277  /// a pointer to that block. If LI is live in to or out of any block,
278  /// return NULL.
280 
281  /// Returns true if VNI is killed by any PHI-def values in LI.
282  /// This may conservatively return true to avoid expensive computations.
283  bool hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const;
284 
285  /// addKillFlags - Add kill flags to any instruction that kills a virtual
286  /// register.
287  void addKillFlags(const VirtRegMap*);
288 
289  /// handleMove - call this method to notify LiveIntervals that
290  /// instruction 'mi' has been moved within a basic block. This will update
291  /// the live intervals for all operands of mi. Moves between basic blocks
292  /// are not supported.
293  ///
294  /// \param UpdateFlags Update live intervals for nonallocatable physregs.
295  void handleMove(MachineInstr* MI, bool UpdateFlags = false);
296 
297  /// moveIntoBundle - Update intervals for operands of MI so that they
298  /// begin/end on the SlotIndex for BundleStart.
299  ///
300  /// \param UpdateFlags Update live intervals for nonallocatable physregs.
301  ///
302  /// Requires MI and BundleStart to have SlotIndexes, and assumes
303  /// existing liveness is accurate. BundleStart should be the first
304  /// instruction in the Bundle.
305  void handleMoveIntoBundle(MachineInstr* MI, MachineInstr* BundleStart,
306  bool UpdateFlags = false);
307 
308  /// repairIntervalsInRange - Update live intervals for instructions in a
309  /// range of iterators. It is intended for use after target hooks that may
310  /// insert or remove instructions, and is only efficient for a small number
311  /// of instructions.
312  ///
313  /// OrigRegs is a vector of registers that were originally used by the
314  /// instructions in the range between the two iterators.
315  ///
316  /// Currently, the only only changes that are supported are simple removal
317  /// and addition of uses.
321  ArrayRef<unsigned> OrigRegs);
322 
323  // Register mask functions.
324  //
325  // Machine instructions may use a register mask operand to indicate that a
326  // large number of registers are clobbered by the instruction. This is
327  // typically used for calls.
328  //
329  // For compile time performance reasons, these clobbers are not recorded in
330  // the live intervals for individual physical registers. Instead,
331  // LiveIntervalAnalysis maintains a sorted list of instructions with
332  // register mask operands.
333 
334  /// getRegMaskSlots - Returns a sorted array of slot indices of all
335  /// instructions with register mask operands.
336  ArrayRef<SlotIndex> getRegMaskSlots() const { return RegMaskSlots; }
337 
338  /// getRegMaskSlotsInBlock - Returns a sorted array of slot indices of all
339  /// instructions with register mask operands in the basic block numbered
340  /// MBBNum.
342  std::pair<unsigned, unsigned> P = RegMaskBlocks[MBBNum];
343  return getRegMaskSlots().slice(P.first, P.second);
344  }
345 
346  /// getRegMaskBits() - Returns an array of register mask pointers
347  /// corresponding to getRegMaskSlots().
348  ArrayRef<const uint32_t*> getRegMaskBits() const { return RegMaskBits; }
349 
350  /// getRegMaskBitsInBlock - Returns an array of mask pointers corresponding
351  /// to getRegMaskSlotsInBlock(MBBNum).
353  std::pair<unsigned, unsigned> P = RegMaskBlocks[MBBNum];
354  return getRegMaskBits().slice(P.first, P.second);
355  }
356 
357  /// checkRegMaskInterference - Test if LI is live across any register mask
358  /// instructions, and compute a bit mask of physical registers that are not
359  /// clobbered by any of them.
360  ///
361  /// Returns false if LI doesn't cross any register mask instructions. In
362  /// that case, the bit vector is not filled in.
364  BitVector &UsableRegs);
365 
366  // Register unit functions.
367  //
368  // Fixed interference occurs when MachineInstrs use physregs directly
369  // instead of virtual registers. This typically happens when passing
370  // arguments to a function call, or when instructions require operands in
371  // fixed registers.
372  //
373  // Each physreg has one or more register units, see MCRegisterInfo. We
374  // track liveness per register unit to handle aliasing registers more
375  // efficiently.
376 
377  /// getRegUnit - Return the live range for Unit.
378  /// It will be computed if it doesn't exist.
379  LiveRange &getRegUnit(unsigned Unit) {
380  LiveRange *LR = RegUnitRanges[Unit];
381  if (!LR) {
382  // Compute missing ranges on demand.
383  // Use segment set to speed-up initial computation of the live range.
384  RegUnitRanges[Unit] = LR = new LiveRange(UseSegmentSetForPhysRegs);
385  computeRegUnitRange(*LR, Unit);
386  }
387  return *LR;
388  }
389 
390  /// getCachedRegUnit - Return the live range for Unit if it has already
391  /// been computed, or NULL if it hasn't been computed yet.
393  return RegUnitRanges[Unit];
394  }
395 
396  const LiveRange *getCachedRegUnit(unsigned Unit) const {
397  return RegUnitRanges[Unit];
398  }
399 
400  /// Remove value numbers and related live segments starting at position
401  /// @p Pos that are part of any liverange of physical register @p Reg or one
402  /// of its subregisters.
403  void removePhysRegDefAt(unsigned Reg, SlotIndex Pos);
404 
405  /// Remove value number and related live segments of @p LI and its subranges
406  /// that start at position @p Pos.
407  void removeVRegDefAt(LiveInterval &LI, SlotIndex Pos);
408 
409  private:
410  /// Compute live intervals for all virtual registers.
411  void computeVirtRegs();
412 
413  /// Compute RegMaskSlots and RegMaskBits.
414  void computeRegMasks();
415 
416  /// Walk the values in @p LI and check for dead values:
417  /// - Dead PHIDef values are marked as unused.
418  /// - Dead operands are marked as such.
419  /// - Completely dead machine instructions are added to the @p dead vector
420  /// if it is not nullptr.
421  /// Returns true if any PHI value numbers have been removed which may
422  /// have separated the interval into multiple connected components.
423  bool computeDeadValues(LiveInterval &LI,
425 
426  static LiveInterval* createInterval(unsigned Reg);
427 
428  void printInstrs(raw_ostream &O) const;
429  void dumpInstrs() const;
430 
431  void computeLiveInRegUnits();
432  void computeRegUnitRange(LiveRange&, unsigned Unit);
433  void computeVirtRegInterval(LiveInterval&);
434 
435 
436  /// Helper function for repairIntervalsInRange(), walks backwards and
437  /// creates/modifies live segments in @p LR to match the operands found.
438  /// Only full operands or operands with subregisters matching @p LaneMask
439  /// are considered.
440  void repairOldRegInRange(MachineBasicBlock::iterator Begin,
442  const SlotIndex endIdx, LiveRange &LR,
443  unsigned Reg, unsigned LaneMask = ~0u);
444 
445  class HMEditor;
446  };
447 } // End llvm namespace
448 
449 #endif
void push_back(const T &Elt)
Definition: SmallVector.h:222
ArrayRef< SlotIndex > getRegMaskSlots() const
getRegMaskSlots - Returns a sorted array of slot indices of all instructions with register mask opera...
cl::opt< bool > UseSegmentSetForPhysRegs
void removePhysRegDefAt(unsigned Reg, SlotIndex Pos)
Remove value numbers and related live segments starting at position Pos that are part of any liverang...
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:114
int getNumber() const
getNumber - MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a M...
bool runOnMachineFunction(MachineFunction &) override
runOnMachineFunction - pass entry point
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:588
SlotIndex getInstructionIndex(const MachineInstr *instr) const
Returns the base index of the given instruction.
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const
Return the last index in the given basic block.
bool isLiveOutOfMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const
bool isLiveInToMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const
MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...
A live range for subregisters.
Definition: LiveInterval.h:595
This represents a simple continuous liveness interval for a value.
Definition: LiveInterval.h:159
VNInfo - Value Number Information.
Definition: LiveInterval.h:45
void print(raw_ostream &O, const Module *=nullptr) const override
print - Implement the dump method.
bool checkRegMaskInterference(LiveInterval &LI, BitVector &UsableRegs)
checkRegMaskInterference - Test if LI is live across any register mask instructions, and compute a bit mask of physical registers that are not clobbered by any of them.
This file defines the MallocAllocator and BumpPtrAllocator interfaces.
This class represents the liveness of a register, stack slot, etc.
Definition: LiveInterval.h:153
bool isNotInMIMap(const MachineInstr *Instr) const
isNotInMIMap - returns true if the specified machine instr has been removed or was never entered in t...
void pruneValue(LiveRange &LR, SlotIndex Kill, SmallVectorImpl< SlotIndex > *EndPoints)
If LR has a live value at Kill, prune its live range by removing any liveness reachable from Kill...
MachineBasicBlock * intervalIsInOneMBB(const LiveInterval &LI) const
intervalIsInOneMBB - If LI is confined to a single basic block, return a pointer to that block...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
ArrayRef< SlotIndex > getRegMaskSlotsInBlock(unsigned MBBNum) const
getRegMaskSlotsInBlock - Returns a sorted array of slot indices of all instructions with register mas...
ArrayRef< const uint32_t * > getRegMaskBits() const
getRegMaskBits() - Returns an array of register mask pointers corresponding to getRegMaskSlots().
VNInfo::Allocator & getVNInfoAllocator()
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APInt.h:33
bool findLiveInMBBs(SlotIndex Start, SlotIndex End, SmallVectorImpl< MachineBasicBlock * > &MBBs) const
Reg
All possible values of the reg field in the ModR/M byte.
void InsertMachineInstrRangeInMaps(MachineBasicBlock::iterator B, MachineBasicBlock::iterator E)
void insertMBBInMaps(MachineBasicBlock *MBB)
SlotIndexes pass.
Definition: SlotIndexes.h:334
bool shrinkToUses(LiveInterval *li, SmallVectorImpl< MachineInstr * > *dead=nullptr)
shrinkToUses - After removing some uses of a register, shrink its live range to just the remaining us...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: ArrayRef.h:31
LiveRange * getCachedRegUnit(unsigned Unit)
getCachedRegUnit - Return the live range for Unit if it has already been computed, or NULL if it hasn't been computed yet.
TargetInstrInfo - Interface to description of machine instruction set.
bool hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const
Returns true if VNI is killed by any PHI-def values in LI.
bundle_iterator< MachineInstr, instr_iterator > iterator
#define P(N)
void RemoveMachineInstrFromMaps(MachineInstr *MI)
SlotIndexes * getSlotIndexes() const
void insertMBBInMaps(MachineBasicBlock *mbb)
Add the given MachineBasicBlock into the maps.
Definition: SlotIndexes.h:639
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:135
bool findLiveInMBBs(SlotIndex start, SlotIndex end, SmallVectorImpl< MachineBasicBlock * > &mbbs) const
Definition: SlotIndexes.h:522
void removeInterval(unsigned Reg)
const LiveRange * getCachedRegUnit(unsigned Unit) const
bundle_iterator - MachineBasicBlock iterator that automatically skips over MIs that are inside bundle...
Represent the analysis usage information of a pass.
LiveInterval::Segment addSegmentToEndOfBlock(unsigned reg, MachineInstr *startInst)
Given a register and an instruction, adds a live segment from that instruction to the end of its MBB...
static float getSpillWeight(bool isDef, bool isUse, const MachineBlockFrequencyInfo *MBFI, const MachineInstr *Instr)
void repairIntervalsInRange(MachineBasicBlock *MBB, MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, ArrayRef< unsigned > OrigRegs)
repairIntervalsInRange - Update live intervals for instructions in a range of iterators.
void handleMove(MachineInstr *MI, bool UpdateFlags=false)
handleMove - call this method to notify LiveIntervals that instruction 'mi' has been moved within a b...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool liveAt(SlotIndex index) const
Definition: LiveInterval.h:372
SlotIndex getInstructionIndex(const MachineInstr *MI) const
Returns the base index for the given instruction.
Definition: SlotIndexes.h:414
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction for the given index, or null if the given index has no instruction associated...
Definition: SlotIndexes.h:423
ArrayRef< const uint32_t * > getRegMaskBitsInBlock(unsigned MBBNum) const
getRegMaskBitsInBlock - Returns an array of mask pointers corresponding to getRegMaskSlotsInBlock(MBB...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:861
bool hasIndex(const MachineInstr *instr) const
Returns true if the given machine instr is mapped to an index, otherwise returns false.
Definition: SlotIndexes.h:409
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
Returns the basic block which the given index falls in.
Definition: SlotIndexes.h:506
LiveInterval & getInterval(unsigned Reg)
SlotIndex InsertMachineInstrInMaps(MachineInstr *MI)
SlotIndex getMBBEndIdx(unsigned Num) const
Returns the last index in the given basic block number.
Definition: SlotIndexes.h:496
LiveInterval & createEmptyInterval(unsigned Reg)
void ReplaceMachineInstrInMaps(MachineInstr *MI, MachineInstr *NewMI)
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:51
void replaceMachineInstrInMaps(MachineInstr *mi, MachineInstr *newMI)
ReplaceMachineInstrInMaps - Replacing a machine instr with a new one in maps used by register allocat...
Definition: SlotIndexes.h:625
void addKillFlags(const VirtRegMap *)
addKillFlags - Add kill flags to any instruction that kills a virtual register.
void handleMoveIntoBundle(MachineInstr *MI, MachineInstr *BundleStart, bool UpdateFlags=false)
moveIntoBundle - Update intervals for operands of MI so that they begin/end on the SlotIndex for Bund...
#define I(x, y, z)
Definition: MD5.cpp:54
void removeMachineInstrFromMaps(MachineInstr *mi)
Remove the given machine instruction from the mapping.
Definition: SlotIndexes.h:610
SlotIndex getMBBStartIdx(unsigned Num) const
Returns the first index in the given basic block number.
Definition: SlotIndexes.h:486
bool hasInterval(unsigned Reg) const
std::vector< uint8_t > Unit
void releaseMemory() override
releaseMemory() - This member can be implemented by a pass if it wants to be able to release its memo...
AliasAnalysis * getAliasAnalysis() const
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:38
SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const
Return the first index in the given basic block.
const LiveInterval & getInterval(unsigned Reg) const
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:92
SlotIndex insertMachineInstrInMaps(MachineInstr *mi, bool Late=false)
Insert the given machine instruction into the mapping.
Definition: SlotIndexes.h:569
void extendToIndices(LiveRange &LR, ArrayRef< SlotIndex > Indices)
extendToIndices - Extend the live range of LI to reach all points in Indices.
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
LiveRange & getRegUnit(unsigned Unit)
getRegUnit - Return the live range for Unit.
LiveInterval & createAndComputeVirtRegInterval(unsigned Reg)
void removeVRegDefAt(LiveInterval &LI, SlotIndex Pos)
Remove value number and related live segments of LI and its subranges that start at position Pos...