LLVM  3.7.0
PPCInstrInfo.cpp
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1 //===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCInstrInfo.h"
16 #include "PPC.h"
17 #include "PPCHazardRecognizers.h"
18 #include "PPCInstrBuilder.h"
19 #include "PPCMachineFunctionInfo.h"
20 #include "PPCTargetMachine.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/Statistic.h"
32 #include "llvm/CodeGen/StackMaps.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCInst.h"
36 #include "llvm/Support/Debug.h"
40 
41 using namespace llvm;
42 
43 #define DEBUG_TYPE "ppc-instr-info"
44 
45 #define GET_INSTRMAP_INFO
46 #define GET_INSTRINFO_CTOR_DTOR
47 #include "PPCGenInstrInfo.inc"
48 
49 static cl::
50 opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
51  cl::desc("Disable analysis for CTR loops"));
52 
53 static cl::opt<bool> DisableCmpOpt("disable-ppc-cmp-opt",
54 cl::desc("Disable compare instruction optimization"), cl::Hidden);
55 
56 static cl::opt<bool> VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy",
57 cl::desc("Causes the backend to crash instead of generating a nop VSX copy"),
58 cl::Hidden);
59 
60 static cl::opt<bool>
61 UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden,
62  cl::desc("Use the old (incorrect) instruction latency calculation"));
63 
64 // Pin the vtable to this file.
65 void PPCInstrInfo::anchor() {}
66 
68  : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
69  Subtarget(STI), RI(STI.getTargetMachine()) {}
70 
71 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
72 /// this target when scheduling the DAG.
75  const ScheduleDAG *DAG) const {
76  unsigned Directive =
77  static_cast<const PPCSubtarget *>(STI)->getDarwinDirective();
78  if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 ||
79  Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) {
80  const InstrItineraryData *II =
81  static_cast<const PPCSubtarget *>(STI)->getInstrItineraryData();
82  return new ScoreboardHazardRecognizer(II, DAG);
83  }
84 
86 }
87 
88 /// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
89 /// to use for this target when scheduling the DAG.
92  const ScheduleDAG *DAG) const {
93  unsigned Directive =
94  DAG->MF.getSubtarget<PPCSubtarget>().getDarwinDirective();
95 
96  if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8)
97  return new PPCDispatchGroupSBHazardRecognizer(II, DAG);
98 
99  // Most subtargets use a PPC970 recognizer.
100  if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 &&
101  Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) {
102  assert(DAG->TII && "No InstrInfo?");
103 
104  return new PPCHazardRecognizer970(*DAG);
105  }
106 
107  return new ScoreboardHazardRecognizer(II, DAG);
108 }
109 
111  const MachineInstr *MI,
112  unsigned *PredCost) const {
113  if (!ItinData || UseOldLatencyCalc)
114  return PPCGenInstrInfo::getInstrLatency(ItinData, MI, PredCost);
115 
116  // The default implementation of getInstrLatency calls getStageLatency, but
117  // getStageLatency does not do the right thing for us. While we have
118  // itinerary, most cores are fully pipelined, and so the itineraries only
119  // express the first part of the pipeline, not every stage. Instead, we need
120  // to use the listed output operand cycle number (using operand 0 here, which
121  // is an output).
122 
123  unsigned Latency = 1;
124  unsigned DefClass = MI->getDesc().getSchedClass();
125  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
126  const MachineOperand &MO = MI->getOperand(i);
127  if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
128  continue;
129 
130  int Cycle = ItinData->getOperandCycle(DefClass, i);
131  if (Cycle < 0)
132  continue;
133 
134  Latency = std::max(Latency, (unsigned) Cycle);
135  }
136 
137  return Latency;
138 }
139 
141  const MachineInstr *DefMI, unsigned DefIdx,
142  const MachineInstr *UseMI,
143  unsigned UseIdx) const {
144  int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
145  UseMI, UseIdx);
146 
147  const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
148  unsigned Reg = DefMO.getReg();
149 
150  bool IsRegCR;
152  const MachineRegisterInfo *MRI =
153  &DefMI->getParent()->getParent()->getRegInfo();
154  IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) ||
155  MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass);
156  } else {
157  IsRegCR = PPC::CRRCRegClass.contains(Reg) ||
158  PPC::CRBITRCRegClass.contains(Reg);
159  }
160 
161  if (UseMI->isBranch() && IsRegCR) {
162  if (Latency < 0)
163  Latency = getInstrLatency(ItinData, DefMI);
164 
165  // On some cores, there is an additional delay between writing to a condition
166  // register, and using it from a branch.
167  unsigned Directive = Subtarget.getDarwinDirective();
168  switch (Directive) {
169  default: break;
170  case PPC::DIR_7400:
171  case PPC::DIR_750:
172  case PPC::DIR_970:
173  case PPC::DIR_E5500:
174  case PPC::DIR_PWR4:
175  case PPC::DIR_PWR5:
176  case PPC::DIR_PWR5X:
177  case PPC::DIR_PWR6:
178  case PPC::DIR_PWR6X:
179  case PPC::DIR_PWR7:
180  case PPC::DIR_PWR8:
181  Latency += 2;
182  break;
183  }
184  }
185 
186  return Latency;
187 }
188 
189 // Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
191  unsigned &SrcReg, unsigned &DstReg,
192  unsigned &SubIdx) const {
193  switch (MI.getOpcode()) {
194  default: return false;
195  case PPC::EXTSW:
196  case PPC::EXTSW_32_64:
197  SrcReg = MI.getOperand(1).getReg();
198  DstReg = MI.getOperand(0).getReg();
199  SubIdx = PPC::sub_32;
200  return true;
201  }
202 }
203 
205  int &FrameIndex) const {
206  // Note: This list must be kept consistent with LoadRegFromStackSlot.
207  switch (MI->getOpcode()) {
208  default: break;
209  case PPC::LD:
210  case PPC::LWZ:
211  case PPC::LFS:
212  case PPC::LFD:
213  case PPC::RESTORE_CR:
214  case PPC::RESTORE_CRBIT:
215  case PPC::LVX:
216  case PPC::LXVD2X:
217  case PPC::QVLFDX:
218  case PPC::QVLFSXs:
219  case PPC::QVLFDXb:
220  case PPC::RESTORE_VRSAVE:
221  // Check for the operands added by addFrameReference (the immediate is the
222  // offset which defaults to 0).
223  if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
224  MI->getOperand(2).isFI()) {
225  FrameIndex = MI->getOperand(2).getIndex();
226  return MI->getOperand(0).getReg();
227  }
228  break;
229  }
230  return 0;
231 }
232 
234  int &FrameIndex) const {
235  // Note: This list must be kept consistent with StoreRegToStackSlot.
236  switch (MI->getOpcode()) {
237  default: break;
238  case PPC::STD:
239  case PPC::STW:
240  case PPC::STFS:
241  case PPC::STFD:
242  case PPC::SPILL_CR:
243  case PPC::SPILL_CRBIT:
244  case PPC::STVX:
245  case PPC::STXVD2X:
246  case PPC::QVSTFDX:
247  case PPC::QVSTFSXs:
248  case PPC::QVSTFDXb:
249  case PPC::SPILL_VRSAVE:
250  // Check for the operands added by addFrameReference (the immediate is the
251  // offset which defaults to 0).
252  if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
253  MI->getOperand(2).isFI()) {
254  FrameIndex = MI->getOperand(2).getIndex();
255  return MI->getOperand(0).getReg();
256  }
257  break;
258  }
259  return 0;
260 }
261 
262 // commuteInstruction - We can commute rlwimi instructions, but only if the
263 // rotate amt is zero. We also have to munge the immediates a bit.
264 MachineInstr *
266  MachineFunction &MF = *MI->getParent()->getParent();
267 
268  // Normal instructions can be commuted the obvious way.
269  if (MI->getOpcode() != PPC::RLWIMI &&
270  MI->getOpcode() != PPC::RLWIMIo)
271  return TargetInstrInfo::commuteInstruction(MI, NewMI);
272  // Note that RLWIMI can be commuted as a 32-bit instruction, but not as a
273  // 64-bit instruction (so we don't handle PPC::RLWIMI8 here), because
274  // changing the relative order of the mask operands might change what happens
275  // to the high-bits of the mask (and, thus, the result).
276 
277  // Cannot commute if it has a non-zero rotate count.
278  if (MI->getOperand(3).getImm() != 0)
279  return nullptr;
280 
281  // If we have a zero rotate count, we have:
282  // M = mask(MB,ME)
283  // Op0 = (Op1 & ~M) | (Op2 & M)
284  // Change this to:
285  // M = mask((ME+1)&31, (MB-1)&31)
286  // Op0 = (Op2 & ~M) | (Op1 & M)
287 
288  // Swap op1/op2
289  unsigned Reg0 = MI->getOperand(0).getReg();
290  unsigned Reg1 = MI->getOperand(1).getReg();
291  unsigned Reg2 = MI->getOperand(2).getReg();
292  unsigned SubReg1 = MI->getOperand(1).getSubReg();
293  unsigned SubReg2 = MI->getOperand(2).getSubReg();
294  bool Reg1IsKill = MI->getOperand(1).isKill();
295  bool Reg2IsKill = MI->getOperand(2).isKill();
296  bool ChangeReg0 = false;
297  // If machine instrs are no longer in two-address forms, update
298  // destination register as well.
299  if (Reg0 == Reg1) {
300  // Must be two address instruction!
301  assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
302  "Expecting a two-address instruction!");
303  assert(MI->getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch");
304  Reg2IsKill = false;
305  ChangeReg0 = true;
306  }
307 
308  // Masks.
309  unsigned MB = MI->getOperand(4).getImm();
310  unsigned ME = MI->getOperand(5).getImm();
311 
312  if (NewMI) {
313  // Create a new instruction.
314  unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
315  bool Reg0IsDead = MI->getOperand(0).isDead();
316  return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
317  .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
318  .addReg(Reg2, getKillRegState(Reg2IsKill))
319  .addReg(Reg1, getKillRegState(Reg1IsKill))
320  .addImm((ME+1) & 31)
321  .addImm((MB-1) & 31);
322  }
323 
324  if (ChangeReg0) {
325  MI->getOperand(0).setReg(Reg2);
326  MI->getOperand(0).setSubReg(SubReg2);
327  }
328  MI->getOperand(2).setReg(Reg1);
329  MI->getOperand(1).setReg(Reg2);
330  MI->getOperand(2).setSubReg(SubReg1);
331  MI->getOperand(1).setSubReg(SubReg2);
332  MI->getOperand(2).setIsKill(Reg1IsKill);
333  MI->getOperand(1).setIsKill(Reg2IsKill);
334 
335  // Swap the mask around.
336  MI->getOperand(4).setImm((ME+1) & 31);
337  MI->getOperand(5).setImm((MB-1) & 31);
338  return MI;
339 }
340 
342  unsigned &SrcOpIdx2) const {
343  // For VSX A-Type FMA instructions, it is the first two operands that can be
344  // commuted, however, because the non-encoded tied input operand is listed
345  // first, the operands to swap are actually the second and third.
346 
347  int AltOpc = PPC::getAltVSXFMAOpcode(MI->getOpcode());
348  if (AltOpc == -1)
349  return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
350 
351  SrcOpIdx1 = 2;
352  SrcOpIdx2 = 3;
353  return true;
354 }
355 
358  // This function is used for scheduling, and the nop wanted here is the type
359  // that terminates dispatch groups on the POWER cores.
360  unsigned Directive = Subtarget.getDarwinDirective();
361  unsigned Opcode;
362  switch (Directive) {
363  default: Opcode = PPC::NOP; break;
364  case PPC::DIR_PWR6: Opcode = PPC::NOP_GT_PWR6; break;
365  case PPC::DIR_PWR7: Opcode = PPC::NOP_GT_PWR7; break;
366  case PPC::DIR_PWR8: Opcode = PPC::NOP_GT_PWR7; break; /* FIXME: Update when P8 InstrScheduling model is ready */
367  }
368 
369  DebugLoc DL;
370  BuildMI(MBB, MI, DL, get(Opcode));
371 }
372 
373 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
375  NopInst.setOpcode(PPC::NOP);
376 }
377 
378 // Branch analysis.
379 // Note: If the condition register is set to CTR or CTR8 then this is a
380 // BDNZ (imm == 1) or BDZ (imm == 0) branch.
382  MachineBasicBlock *&FBB,
384  bool AllowModify) const {
385  bool isPPC64 = Subtarget.isPPC64();
386 
387  // If the block has no terminators, it just falls into the block after it.
389  if (I == MBB.end())
390  return false;
391 
392  if (!isUnpredicatedTerminator(I))
393  return false;
394 
395  // Get the last instruction in the block.
396  MachineInstr *LastInst = I;
397 
398  // If there is only one terminator instruction, process it.
399  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
400  if (LastInst->getOpcode() == PPC::B) {
401  if (!LastInst->getOperand(0).isMBB())
402  return true;
403  TBB = LastInst->getOperand(0).getMBB();
404  return false;
405  } else if (LastInst->getOpcode() == PPC::BCC) {
406  if (!LastInst->getOperand(2).isMBB())
407  return true;
408  // Block ends with fall-through condbranch.
409  TBB = LastInst->getOperand(2).getMBB();
410  Cond.push_back(LastInst->getOperand(0));
411  Cond.push_back(LastInst->getOperand(1));
412  return false;
413  } else if (LastInst->getOpcode() == PPC::BC) {
414  if (!LastInst->getOperand(1).isMBB())
415  return true;
416  // Block ends with fall-through condbranch.
417  TBB = LastInst->getOperand(1).getMBB();
419  Cond.push_back(LastInst->getOperand(0));
420  return false;
421  } else if (LastInst->getOpcode() == PPC::BCn) {
422  if (!LastInst->getOperand(1).isMBB())
423  return true;
424  // Block ends with fall-through condbranch.
425  TBB = LastInst->getOperand(1).getMBB();
427  Cond.push_back(LastInst->getOperand(0));
428  return false;
429  } else if (LastInst->getOpcode() == PPC::BDNZ8 ||
430  LastInst->getOpcode() == PPC::BDNZ) {
431  if (!LastInst->getOperand(0).isMBB())
432  return true;
433  if (DisableCTRLoopAnal)
434  return true;
435  TBB = LastInst->getOperand(0).getMBB();
437  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
438  true));
439  return false;
440  } else if (LastInst->getOpcode() == PPC::BDZ8 ||
441  LastInst->getOpcode() == PPC::BDZ) {
442  if (!LastInst->getOperand(0).isMBB())
443  return true;
444  if (DisableCTRLoopAnal)
445  return true;
446  TBB = LastInst->getOperand(0).getMBB();
448  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
449  true));
450  return false;
451  }
452 
453  // Otherwise, don't know what this is.
454  return true;
455  }
456 
457  // Get the instruction before it if it's a terminator.
458  MachineInstr *SecondLastInst = I;
459 
460  // If there are three terminators, we don't know what sort of block this is.
461  if (SecondLastInst && I != MBB.begin() &&
463  return true;
464 
465  // If the block ends with PPC::B and PPC:BCC, handle it.
466  if (SecondLastInst->getOpcode() == PPC::BCC &&
467  LastInst->getOpcode() == PPC::B) {
468  if (!SecondLastInst->getOperand(2).isMBB() ||
469  !LastInst->getOperand(0).isMBB())
470  return true;
471  TBB = SecondLastInst->getOperand(2).getMBB();
472  Cond.push_back(SecondLastInst->getOperand(0));
473  Cond.push_back(SecondLastInst->getOperand(1));
474  FBB = LastInst->getOperand(0).getMBB();
475  return false;
476  } else if (SecondLastInst->getOpcode() == PPC::BC &&
477  LastInst->getOpcode() == PPC::B) {
478  if (!SecondLastInst->getOperand(1).isMBB() ||
479  !LastInst->getOperand(0).isMBB())
480  return true;
481  TBB = SecondLastInst->getOperand(1).getMBB();
483  Cond.push_back(SecondLastInst->getOperand(0));
484  FBB = LastInst->getOperand(0).getMBB();
485  return false;
486  } else if (SecondLastInst->getOpcode() == PPC::BCn &&
487  LastInst->getOpcode() == PPC::B) {
488  if (!SecondLastInst->getOperand(1).isMBB() ||
489  !LastInst->getOperand(0).isMBB())
490  return true;
491  TBB = SecondLastInst->getOperand(1).getMBB();
493  Cond.push_back(SecondLastInst->getOperand(0));
494  FBB = LastInst->getOperand(0).getMBB();
495  return false;
496  } else if ((SecondLastInst->getOpcode() == PPC::BDNZ8 ||
497  SecondLastInst->getOpcode() == PPC::BDNZ) &&
498  LastInst->getOpcode() == PPC::B) {
499  if (!SecondLastInst->getOperand(0).isMBB() ||
500  !LastInst->getOperand(0).isMBB())
501  return true;
502  if (DisableCTRLoopAnal)
503  return true;
504  TBB = SecondLastInst->getOperand(0).getMBB();
506  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
507  true));
508  FBB = LastInst->getOperand(0).getMBB();
509  return false;
510  } else if ((SecondLastInst->getOpcode() == PPC::BDZ8 ||
511  SecondLastInst->getOpcode() == PPC::BDZ) &&
512  LastInst->getOpcode() == PPC::B) {
513  if (!SecondLastInst->getOperand(0).isMBB() ||
514  !LastInst->getOperand(0).isMBB())
515  return true;
516  if (DisableCTRLoopAnal)
517  return true;
518  TBB = SecondLastInst->getOperand(0).getMBB();
520  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
521  true));
522  FBB = LastInst->getOperand(0).getMBB();
523  return false;
524  }
525 
526  // If the block ends with two PPC:Bs, handle it. The second one is not
527  // executed, so remove it.
528  if (SecondLastInst->getOpcode() == PPC::B &&
529  LastInst->getOpcode() == PPC::B) {
530  if (!SecondLastInst->getOperand(0).isMBB())
531  return true;
532  TBB = SecondLastInst->getOperand(0).getMBB();
533  I = LastInst;
534  if (AllowModify)
535  I->eraseFromParent();
536  return false;
537  }
538 
539  // Otherwise, can't handle this.
540  return true;
541 }
542 
545  if (I == MBB.end())
546  return 0;
547 
548  if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
549  I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
550  I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
551  I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
552  return 0;
553 
554  // Remove the branch.
555  I->eraseFromParent();
556 
557  I = MBB.end();
558 
559  if (I == MBB.begin()) return 1;
560  --I;
561  if (I->getOpcode() != PPC::BCC &&
562  I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
563  I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
564  I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
565  return 1;
566 
567  // Remove the branch.
568  I->eraseFromParent();
569  return 2;
570 }
571 
572 unsigned
574  MachineBasicBlock *FBB,
576  DebugLoc DL) const {
577  // Shouldn't be a fall through.
578  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
579  assert((Cond.size() == 2 || Cond.size() == 0) &&
580  "PPC branch conditions have two components!");
581 
582  bool isPPC64 = Subtarget.isPPC64();
583 
584  // One-way branch.
585  if (!FBB) {
586  if (Cond.empty()) // Unconditional branch
587  BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
588  else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
589  BuildMI(&MBB, DL, get(Cond[0].getImm() ?
590  (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
591  (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
592  else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
593  BuildMI(&MBB, DL, get(PPC::BC)).addOperand(Cond[1]).addMBB(TBB);
594  else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
595  BuildMI(&MBB, DL, get(PPC::BCn)).addOperand(Cond[1]).addMBB(TBB);
596  else // Conditional branch
597  BuildMI(&MBB, DL, get(PPC::BCC))
598  .addImm(Cond[0].getImm()).addOperand(Cond[1]).addMBB(TBB);
599  return 1;
600  }
601 
602  // Two-way Conditional Branch.
603  if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
604  BuildMI(&MBB, DL, get(Cond[0].getImm() ?
605  (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
606  (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
607  else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
608  BuildMI(&MBB, DL, get(PPC::BC)).addOperand(Cond[1]).addMBB(TBB);
609  else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
610  BuildMI(&MBB, DL, get(PPC::BCn)).addOperand(Cond[1]).addMBB(TBB);
611  else
612  BuildMI(&MBB, DL, get(PPC::BCC))
613  .addImm(Cond[0].getImm()).addOperand(Cond[1]).addMBB(TBB);
614  BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
615  return 2;
616 }
617 
618 // Select analysis.
621  unsigned TrueReg, unsigned FalseReg,
622  int &CondCycles, int &TrueCycles, int &FalseCycles) const {
623  if (!Subtarget.hasISEL())
624  return false;
625 
626  if (Cond.size() != 2)
627  return false;
628 
629  // If this is really a bdnz-like condition, then it cannot be turned into a
630  // select.
631  if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
632  return false;
633 
634  // Check register classes.
635  const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
636  const TargetRegisterClass *RC =
637  RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
638  if (!RC)
639  return false;
640 
641  // isel is for regular integer GPRs only.
642  if (!PPC::GPRCRegClass.hasSubClassEq(RC) &&
643  !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) &&
644  !PPC::G8RCRegClass.hasSubClassEq(RC) &&
645  !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC))
646  return false;
647 
648  // FIXME: These numbers are for the A2, how well they work for other cores is
649  // an open question. On the A2, the isel instruction has a 2-cycle latency
650  // but single-cycle throughput. These numbers are used in combination with
651  // the MispredictPenalty setting from the active SchedMachineModel.
652  CondCycles = 1;
653  TrueCycles = 1;
654  FalseCycles = 1;
655 
656  return true;
657 }
658 
661  unsigned DestReg, ArrayRef<MachineOperand> Cond,
662  unsigned TrueReg, unsigned FalseReg) const {
663  assert(Cond.size() == 2 &&
664  "PPC branch conditions have two components!");
665 
666  assert(Subtarget.hasISEL() &&
667  "Cannot insert select on target without ISEL support");
668 
669  // Get the register classes.
670  MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
671  const TargetRegisterClass *RC =
672  RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
673  assert(RC && "TrueReg and FalseReg must have overlapping register classes");
674 
675  bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) ||
676  PPC::G8RC_NOX0RegClass.hasSubClassEq(RC);
677  assert((Is64Bit ||
678  PPC::GPRCRegClass.hasSubClassEq(RC) ||
679  PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) &&
680  "isel is for regular integer GPRs only");
681 
682  unsigned OpCode = Is64Bit ? PPC::ISEL8 : PPC::ISEL;
683  unsigned SelectPred = Cond[0].getImm();
684 
685  unsigned SubIdx;
686  bool SwapOps;
687  switch (SelectPred) {
688  default: llvm_unreachable("invalid predicate for isel");
689  case PPC::PRED_EQ: SubIdx = PPC::sub_eq; SwapOps = false; break;
690  case PPC::PRED_NE: SubIdx = PPC::sub_eq; SwapOps = true; break;
691  case PPC::PRED_LT: SubIdx = PPC::sub_lt; SwapOps = false; break;
692  case PPC::PRED_GE: SubIdx = PPC::sub_lt; SwapOps = true; break;
693  case PPC::PRED_GT: SubIdx = PPC::sub_gt; SwapOps = false; break;
694  case PPC::PRED_LE: SubIdx = PPC::sub_gt; SwapOps = true; break;
695  case PPC::PRED_UN: SubIdx = PPC::sub_un; SwapOps = false; break;
696  case PPC::PRED_NU: SubIdx = PPC::sub_un; SwapOps = true; break;
697  case PPC::PRED_BIT_SET: SubIdx = 0; SwapOps = false; break;
698  case PPC::PRED_BIT_UNSET: SubIdx = 0; SwapOps = true; break;
699  }
700 
701  unsigned FirstReg = SwapOps ? FalseReg : TrueReg,
702  SecondReg = SwapOps ? TrueReg : FalseReg;
703 
704  // The first input register of isel cannot be r0. If it is a member
705  // of a register class that can be r0, then copy it first (the
706  // register allocator should eliminate the copy).
707  if (MRI.getRegClass(FirstReg)->contains(PPC::R0) ||
708  MRI.getRegClass(FirstReg)->contains(PPC::X0)) {
709  const TargetRegisterClass *FirstRC =
710  MRI.getRegClass(FirstReg)->contains(PPC::X0) ?
711  &PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass;
712  unsigned OldFirstReg = FirstReg;
713  FirstReg = MRI.createVirtualRegister(FirstRC);
714  BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg)
715  .addReg(OldFirstReg);
716  }
717 
718  BuildMI(MBB, MI, dl, get(OpCode), DestReg)
719  .addReg(FirstReg).addReg(SecondReg)
720  .addReg(Cond[1].getReg(), 0, SubIdx);
721 }
722 
723 static unsigned getCRBitValue(unsigned CRBit) {
724  unsigned Ret = 4;
725  if (CRBit == PPC::CR0LT || CRBit == PPC::CR1LT ||
726  CRBit == PPC::CR2LT || CRBit == PPC::CR3LT ||
727  CRBit == PPC::CR4LT || CRBit == PPC::CR5LT ||
728  CRBit == PPC::CR6LT || CRBit == PPC::CR7LT)
729  Ret = 3;
730  if (CRBit == PPC::CR0GT || CRBit == PPC::CR1GT ||
731  CRBit == PPC::CR2GT || CRBit == PPC::CR3GT ||
732  CRBit == PPC::CR4GT || CRBit == PPC::CR5GT ||
733  CRBit == PPC::CR6GT || CRBit == PPC::CR7GT)
734  Ret = 2;
735  if (CRBit == PPC::CR0EQ || CRBit == PPC::CR1EQ ||
736  CRBit == PPC::CR2EQ || CRBit == PPC::CR3EQ ||
737  CRBit == PPC::CR4EQ || CRBit == PPC::CR5EQ ||
738  CRBit == PPC::CR6EQ || CRBit == PPC::CR7EQ)
739  Ret = 1;
740  if (CRBit == PPC::CR0UN || CRBit == PPC::CR1UN ||
741  CRBit == PPC::CR2UN || CRBit == PPC::CR3UN ||
742  CRBit == PPC::CR4UN || CRBit == PPC::CR5UN ||
743  CRBit == PPC::CR6UN || CRBit == PPC::CR7UN)
744  Ret = 0;
745 
746  assert(Ret != 4 && "Invalid CR bit register");
747  return Ret;
748 }
749 
752  unsigned DestReg, unsigned SrcReg,
753  bool KillSrc) const {
754  // We can end up with self copies and similar things as a result of VSX copy
755  // legalization. Promote them here.
756  const TargetRegisterInfo *TRI = &getRegisterInfo();
757  if (PPC::F8RCRegClass.contains(DestReg) &&
758  PPC::VSRCRegClass.contains(SrcReg)) {
759  unsigned SuperReg =
760  TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass);
761 
762  if (VSXSelfCopyCrash && SrcReg == SuperReg)
763  llvm_unreachable("nop VSX copy");
764 
765  DestReg = SuperReg;
766  } else if (PPC::VRRCRegClass.contains(DestReg) &&
767  PPC::VSRCRegClass.contains(SrcReg)) {
768  unsigned SuperReg =
769  TRI->getMatchingSuperReg(DestReg, PPC::sub_128, &PPC::VSRCRegClass);
770 
771  if (VSXSelfCopyCrash && SrcReg == SuperReg)
772  llvm_unreachable("nop VSX copy");
773 
774  DestReg = SuperReg;
775  } else if (PPC::F8RCRegClass.contains(SrcReg) &&
776  PPC::VSRCRegClass.contains(DestReg)) {
777  unsigned SuperReg =
778  TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass);
779 
780  if (VSXSelfCopyCrash && DestReg == SuperReg)
781  llvm_unreachable("nop VSX copy");
782 
783  SrcReg = SuperReg;
784  } else if (PPC::VRRCRegClass.contains(SrcReg) &&
785  PPC::VSRCRegClass.contains(DestReg)) {
786  unsigned SuperReg =
787  TRI->getMatchingSuperReg(SrcReg, PPC::sub_128, &PPC::VSRCRegClass);
788 
789  if (VSXSelfCopyCrash && DestReg == SuperReg)
790  llvm_unreachable("nop VSX copy");
791 
792  SrcReg = SuperReg;
793  }
794 
795  // Different class register copy
796  if (PPC::CRBITRCRegClass.contains(SrcReg) &&
797  PPC::GPRCRegClass.contains(DestReg)) {
798  unsigned CRReg = getCRFromCRBit(SrcReg);
799  BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg)
800  .addReg(CRReg), getKillRegState(KillSrc);
801  // Rotate the CR bit in the CR fields to be the least significant bit and
802  // then mask with 0x1 (MB = ME = 31).
803  BuildMI(MBB, I, DL, get(PPC::RLWINM), DestReg)
804  .addReg(DestReg, RegState::Kill)
805  .addImm(TRI->getEncodingValue(CRReg) * 4 + (4 - getCRBitValue(SrcReg)))
806  .addImm(31)
807  .addImm(31);
808  return;
809  } else if (PPC::CRRCRegClass.contains(SrcReg) &&
810  PPC::G8RCRegClass.contains(DestReg)) {
811  BuildMI(MBB, I, DL, get(PPC::MFOCRF8), DestReg)
812  .addReg(SrcReg), getKillRegState(KillSrc);
813  return;
814  } else if (PPC::CRRCRegClass.contains(SrcReg) &&
815  PPC::GPRCRegClass.contains(DestReg)) {
816  BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg)
817  .addReg(SrcReg), getKillRegState(KillSrc);
818  return;
819  }
820 
821  unsigned Opc;
822  if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
823  Opc = PPC::OR;
824  else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
825  Opc = PPC::OR8;
826  else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
827  Opc = PPC::FMR;
828  else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
829  Opc = PPC::MCRF;
830  else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
831  Opc = PPC::VOR;
832  else if (PPC::VSRCRegClass.contains(DestReg, SrcReg))
833  // There are two different ways this can be done:
834  // 1. xxlor : This has lower latency (on the P7), 2 cycles, but can only
835  // issue in VSU pipeline 0.
836  // 2. xmovdp/xmovsp: This has higher latency (on the P7), 6 cycles, but
837  // can go to either pipeline.
838  // We'll always use xxlor here, because in practically all cases where
839  // copies are generated, they are close enough to some use that the
840  // lower-latency form is preferable.
841  Opc = PPC::XXLOR;
842  else if (PPC::VSFRCRegClass.contains(DestReg, SrcReg) ||
843  PPC::VSSRCRegClass.contains(DestReg, SrcReg))
844  Opc = PPC::XXLORf;
845  else if (PPC::QFRCRegClass.contains(DestReg, SrcReg))
846  Opc = PPC::QVFMR;
847  else if (PPC::QSRCRegClass.contains(DestReg, SrcReg))
848  Opc = PPC::QVFMRs;
849  else if (PPC::QBRCRegClass.contains(DestReg, SrcReg))
850  Opc = PPC::QVFMRb;
851  else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
852  Opc = PPC::CROR;
853  else
854  llvm_unreachable("Impossible reg-to-reg copy");
855 
856  const MCInstrDesc &MCID = get(Opc);
857  if (MCID.getNumOperands() == 3)
858  BuildMI(MBB, I, DL, MCID, DestReg)
859  .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
860  else
861  BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
862 }
863 
864 // This function returns true if a CR spill is necessary and false otherwise.
865 bool
866 PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
867  unsigned SrcReg, bool isKill,
868  int FrameIdx,
869  const TargetRegisterClass *RC,
871  bool &NonRI, bool &SpillsVRS) const{
872  // Note: If additional store instructions are added here,
873  // update isStoreToStackSlot.
874 
875  DebugLoc DL;
876  if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
877  PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
878  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
879  .addReg(SrcReg,
880  getKillRegState(isKill)),
881  FrameIdx));
882  } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
883  PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
884  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
885  .addReg(SrcReg,
886  getKillRegState(isKill)),
887  FrameIdx));
888  } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
889  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
890  .addReg(SrcReg,
891  getKillRegState(isKill)),
892  FrameIdx));
893  } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
894  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
895  .addReg(SrcReg,
896  getKillRegState(isKill)),
897  FrameIdx));
898  } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
899  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
900  .addReg(SrcReg,
901  getKillRegState(isKill)),
902  FrameIdx));
903  return true;
904  } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
905  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CRBIT))
906  .addReg(SrcReg,
907  getKillRegState(isKill)),
908  FrameIdx));
909  return true;
910  } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
911  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STVX))
912  .addReg(SrcReg,
913  getKillRegState(isKill)),
914  FrameIdx));
915  NonRI = true;
916  } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
917  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STXVD2X))
918  .addReg(SrcReg,
919  getKillRegState(isKill)),
920  FrameIdx));
921  NonRI = true;
922  } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
923  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STXSDX))
924  .addReg(SrcReg,
925  getKillRegState(isKill)),
926  FrameIdx));
927  NonRI = true;
928  } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
929  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STXSSPX))
930  .addReg(SrcReg,
931  getKillRegState(isKill)),
932  FrameIdx));
933  NonRI = true;
934  } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
935  assert(Subtarget.isDarwin() &&
936  "VRSAVE only needs spill/restore on Darwin");
937  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_VRSAVE))
938  .addReg(SrcReg,
939  getKillRegState(isKill)),
940  FrameIdx));
941  SpillsVRS = true;
942  } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
943  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFDX))
944  .addReg(SrcReg,
945  getKillRegState(isKill)),
946  FrameIdx));
947  NonRI = true;
948  } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
949  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFSXs))
950  .addReg(SrcReg,
951  getKillRegState(isKill)),
952  FrameIdx));
953  NonRI = true;
954  } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
955  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFDXb))
956  .addReg(SrcReg,
957  getKillRegState(isKill)),
958  FrameIdx));
959  NonRI = true;
960  } else {
961  llvm_unreachable("Unknown regclass!");
962  }
963 
964  return false;
965 }
966 
967 void
970  unsigned SrcReg, bool isKill, int FrameIdx,
971  const TargetRegisterClass *RC,
972  const TargetRegisterInfo *TRI) const {
973  MachineFunction &MF = *MBB.getParent();
975 
976  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
977  FuncInfo->setHasSpills();
978 
979  bool NonRI = false, SpillsVRS = false;
980  if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs,
981  NonRI, SpillsVRS))
982  FuncInfo->setSpillsCR();
983 
984  if (SpillsVRS)
985  FuncInfo->setSpillsVRSAVE();
986 
987  if (NonRI)
988  FuncInfo->setHasNonRISpills();
989 
990  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
991  MBB.insert(MI, NewMIs[i]);
992 
993  const MachineFrameInfo &MFI = *MF.getFrameInfo();
994  MachineMemOperand *MMO =
997  MFI.getObjectSize(FrameIdx),
998  MFI.getObjectAlignment(FrameIdx));
999  NewMIs.back()->addMemOperand(MF, MMO);
1000 }
1001 
1002 bool
1003 PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
1004  unsigned DestReg, int FrameIdx,
1005  const TargetRegisterClass *RC,
1007  bool &NonRI, bool &SpillsVRS) const{
1008  // Note: If additional load instructions are added here,
1009  // update isLoadFromStackSlot.
1010 
1011  if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1012  PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1013  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
1014  DestReg), FrameIdx));
1015  } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1016  PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1017  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
1018  FrameIdx));
1019  } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1020  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
1021  FrameIdx));
1022  } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1023  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
1024  FrameIdx));
1025  } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1026  NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
1027  get(PPC::RESTORE_CR), DestReg),
1028  FrameIdx));
1029  return true;
1030  } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1031  NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
1032  get(PPC::RESTORE_CRBIT), DestReg),
1033  FrameIdx));
1034  return true;
1035  } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1036  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LVX), DestReg),
1037  FrameIdx));
1038  NonRI = true;
1039  } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1040  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LXVD2X), DestReg),
1041  FrameIdx));
1042  NonRI = true;
1043  } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1044  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LXSDX), DestReg),
1045  FrameIdx));
1046  NonRI = true;
1047  } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1048  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LXSSPX), DestReg),
1049  FrameIdx));
1050  NonRI = true;
1051  } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1052  assert(Subtarget.isDarwin() &&
1053  "VRSAVE only needs spill/restore on Darwin");
1054  NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
1055  get(PPC::RESTORE_VRSAVE),
1056  DestReg),
1057  FrameIdx));
1058  SpillsVRS = true;
1059  } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1060  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVLFDX), DestReg),
1061  FrameIdx));
1062  NonRI = true;
1063  } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1064  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVLFSXs), DestReg),
1065  FrameIdx));
1066  NonRI = true;
1067  } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1068  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVLFDXb), DestReg),
1069  FrameIdx));
1070  NonRI = true;
1071  } else {
1072  llvm_unreachable("Unknown regclass!");
1073  }
1074 
1075  return false;
1076 }
1077 
1078 void
1081  unsigned DestReg, int FrameIdx,
1082  const TargetRegisterClass *RC,
1083  const TargetRegisterInfo *TRI) const {
1084  MachineFunction &MF = *MBB.getParent();
1086  DebugLoc DL;
1087  if (MI != MBB.end()) DL = MI->getDebugLoc();
1088 
1089  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1090  FuncInfo->setHasSpills();
1091 
1092  bool NonRI = false, SpillsVRS = false;
1093  if (LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs,
1094  NonRI, SpillsVRS))
1095  FuncInfo->setSpillsCR();
1096 
1097  if (SpillsVRS)
1098  FuncInfo->setSpillsVRSAVE();
1099 
1100  if (NonRI)
1101  FuncInfo->setHasNonRISpills();
1102 
1103  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1104  MBB.insert(MI, NewMIs[i]);
1105 
1106  const MachineFrameInfo &MFI = *MF.getFrameInfo();
1107  MachineMemOperand *MMO =
1110  MFI.getObjectSize(FrameIdx),
1111  MFI.getObjectAlignment(FrameIdx));
1112  NewMIs.back()->addMemOperand(MF, MMO);
1113 }
1114 
1115 bool PPCInstrInfo::
1117  assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
1118  if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
1119  Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
1120  else
1121  // Leave the CR# the same, but invert the condition.
1122  Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
1123  return false;
1124 }
1125 
1127  unsigned Reg, MachineRegisterInfo *MRI) const {
1128  // For some instructions, it is legal to fold ZERO into the RA register field.
1129  // A zero immediate should always be loaded with a single li.
1130  unsigned DefOpc = DefMI->getOpcode();
1131  if (DefOpc != PPC::LI && DefOpc != PPC::LI8)
1132  return false;
1133  if (!DefMI->getOperand(1).isImm())
1134  return false;
1135  if (DefMI->getOperand(1).getImm() != 0)
1136  return false;
1137 
1138  // Note that we cannot here invert the arguments of an isel in order to fold
1139  // a ZERO into what is presented as the second argument. All we have here
1140  // is the condition bit, and that might come from a CR-logical bit operation.
1141 
1142  const MCInstrDesc &UseMCID = UseMI->getDesc();
1143 
1144  // Only fold into real machine instructions.
1145  if (UseMCID.isPseudo())
1146  return false;
1147 
1148  unsigned UseIdx;
1149  for (UseIdx = 0; UseIdx < UseMI->getNumOperands(); ++UseIdx)
1150  if (UseMI->getOperand(UseIdx).isReg() &&
1151  UseMI->getOperand(UseIdx).getReg() == Reg)
1152  break;
1153 
1154  assert(UseIdx < UseMI->getNumOperands() && "Cannot find Reg in UseMI");
1155  assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg");
1156 
1157  const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx];
1158 
1159  // We can fold the zero if this register requires a GPRC_NOR0/G8RC_NOX0
1160  // register (which might also be specified as a pointer class kind).
1161  if (UseInfo->isLookupPtrRegClass()) {
1162  if (UseInfo->RegClass /* Kind */ != 1)
1163  return false;
1164  } else {
1165  if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID &&
1166  UseInfo->RegClass != PPC::G8RC_NOX0RegClassID)
1167  return false;
1168  }
1169 
1170  // Make sure this is not tied to an output register (or otherwise
1171  // constrained). This is true for ST?UX registers, for example, which
1172  // are tied to their output registers.
1173  if (UseInfo->Constraints != 0)
1174  return false;
1175 
1176  unsigned ZeroReg;
1177  if (UseInfo->isLookupPtrRegClass()) {
1178  bool isPPC64 = Subtarget.isPPC64();
1179  ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;
1180  } else {
1181  ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ?
1182  PPC::ZERO8 : PPC::ZERO;
1183  }
1184 
1185  bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
1186  UseMI->getOperand(UseIdx).setReg(ZeroReg);
1187 
1188  if (DeleteDef)
1189  DefMI->eraseFromParent();
1190 
1191  return true;
1192 }
1193 
1195  for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
1196  I != IE; ++I)
1197  if (I->definesRegister(PPC::CTR) || I->definesRegister(PPC::CTR8))
1198  return true;
1199  return false;
1200 }
1201 
1202 // We should make sure that, if we're going to predicate both sides of a
1203 // condition (a diamond), that both sides don't define the counter register. We
1204 // can predicate counter-decrement-based branches, but while that predicates
1205 // the branching, it does not predicate the counter decrement. If we tried to
1206 // merge the triangle into one predicated block, we'd decrement the counter
1207 // twice.
1209  unsigned NumT, unsigned ExtraT,
1210  MachineBasicBlock &FMBB,
1211  unsigned NumF, unsigned ExtraF,
1212  const BranchProbability &Probability) const {
1213  return !(MBBDefinesCTR(TMBB) && MBBDefinesCTR(FMBB));
1214 }
1215 
1216 
1218  // The predicated branches are identified by their type, not really by the
1219  // explicit presence of a predicate. Furthermore, some of them can be
1220  // predicated more than once. Because if conversion won't try to predicate
1221  // any instruction which already claims to be predicated (by returning true
1222  // here), always return false. In doing so, we let isPredicable() be the
1223  // final word on whether not the instruction can be (further) predicated.
1224 
1225  return false;
1226 }
1227 
1229  if (!MI->isTerminator())
1230  return false;
1231 
1232  // Conditional branch is a special case.
1233  if (MI->isBranch() && !MI->isBarrier())
1234  return true;
1235 
1236  return !isPredicated(MI);
1237 }
1238 
1240  ArrayRef<MachineOperand> Pred) const {
1241  unsigned OpC = MI->getOpcode();
1242  if (OpC == PPC::BLR || OpC == PPC::BLR8) {
1243  if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1244  bool isPPC64 = Subtarget.isPPC64();
1245  MI->setDesc(get(Pred[0].getImm() ?
1246  (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR) :
1247  (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR)));
1248  } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1249  MI->setDesc(get(PPC::BCLR));
1251  .addReg(Pred[1].getReg());
1252  } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1253  MI->setDesc(get(PPC::BCLRn));
1255  .addReg(Pred[1].getReg());
1256  } else {
1257  MI->setDesc(get(PPC::BCCLR));
1259  .addImm(Pred[0].getImm())
1260  .addReg(Pred[1].getReg());
1261  }
1262 
1263  return true;
1264  } else if (OpC == PPC::B) {
1265  if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1266  bool isPPC64 = Subtarget.isPPC64();
1267  MI->setDesc(get(Pred[0].getImm() ?
1268  (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
1269  (isPPC64 ? PPC::BDZ8 : PPC::BDZ)));
1270  } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1271  MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
1272  MI->RemoveOperand(0);
1273 
1274  MI->setDesc(get(PPC::BC));
1276  .addReg(Pred[1].getReg())
1277  .addMBB(MBB);
1278  } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1279  MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
1280  MI->RemoveOperand(0);
1281 
1282  MI->setDesc(get(PPC::BCn));
1284  .addReg(Pred[1].getReg())
1285  .addMBB(MBB);
1286  } else {
1287  MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
1288  MI->RemoveOperand(0);
1289 
1290  MI->setDesc(get(PPC::BCC));
1292  .addImm(Pred[0].getImm())
1293  .addReg(Pred[1].getReg())
1294  .addMBB(MBB);
1295  }
1296 
1297  return true;
1298  } else if (OpC == PPC::BCTR || OpC == PPC::BCTR8 ||
1299  OpC == PPC::BCTRL || OpC == PPC::BCTRL8) {
1300  if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR)
1301  llvm_unreachable("Cannot predicate bctr[l] on the ctr register");
1302 
1303  bool setLR = OpC == PPC::BCTRL || OpC == PPC::BCTRL8;
1304  bool isPPC64 = Subtarget.isPPC64();
1305 
1306  if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1307  MI->setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8) :
1308  (setLR ? PPC::BCCTRL : PPC::BCCTR)));
1310  .addReg(Pred[1].getReg());
1311  return true;
1312  } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1313  MI->setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n) :
1314  (setLR ? PPC::BCCTRLn : PPC::BCCTRn)));
1316  .addReg(Pred[1].getReg());
1317  return true;
1318  }
1319 
1320  MI->setDesc(get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8) :
1321  (setLR ? PPC::BCCCTRL : PPC::BCCCTR)));
1323  .addImm(Pred[0].getImm())
1324  .addReg(Pred[1].getReg());
1325  return true;
1326  }
1327 
1328  return false;
1329 }
1330 
1332  ArrayRef<MachineOperand> Pred2) const {
1333  assert(Pred1.size() == 2 && "Invalid PPC first predicate");
1334  assert(Pred2.size() == 2 && "Invalid PPC second predicate");
1335 
1336  if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR)
1337  return false;
1338  if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR)
1339  return false;
1340 
1341  // P1 can only subsume P2 if they test the same condition register.
1342  if (Pred1[1].getReg() != Pred2[1].getReg())
1343  return false;
1344 
1345  PPC::Predicate P1 = (PPC::Predicate) Pred1[0].getImm();
1346  PPC::Predicate P2 = (PPC::Predicate) Pred2[0].getImm();
1347 
1348  if (P1 == P2)
1349  return true;
1350 
1351  // Does P1 subsume P2, e.g. GE subsumes GT.
1352  if (P1 == PPC::PRED_LE &&
1353  (P2 == PPC::PRED_LT || P2 == PPC::PRED_EQ))
1354  return true;
1355  if (P1 == PPC::PRED_GE &&
1356  (P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ))
1357  return true;
1358 
1359  return false;
1360 }
1361 
1363  std::vector<MachineOperand> &Pred) const {
1364  // Note: At the present time, the contents of Pred from this function is
1365  // unused by IfConversion. This implementation follows ARM by pushing the
1366  // CR-defining operand. Because the 'DZ' and 'DNZ' count as types of
1367  // predicate, instructions defining CTR or CTR8 are also included as
1368  // predicate-defining instructions.
1369 
1370  const TargetRegisterClass *RCs[] =
1371  { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass,
1372  &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass };
1373 
1374  bool Found = false;
1375  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1376  const MachineOperand &MO = MI->getOperand(i);
1377  for (unsigned c = 0; c < array_lengthof(RCs) && !Found; ++c) {
1378  const TargetRegisterClass *RC = RCs[c];
1379  if (MO.isReg()) {
1380  if (MO.isDef() && RC->contains(MO.getReg())) {
1381  Pred.push_back(MO);
1382  Found = true;
1383  }
1384  } else if (MO.isRegMask()) {
1385  for (TargetRegisterClass::iterator I = RC->begin(),
1386  IE = RC->end(); I != IE; ++I)
1387  if (MO.clobbersPhysReg(*I)) {
1388  Pred.push_back(MO);
1389  Found = true;
1390  }
1391  }
1392  }
1393  }
1394 
1395  return Found;
1396 }
1397 
1399  unsigned OpC = MI->getOpcode();
1400  switch (OpC) {
1401  default:
1402  return false;
1403  case PPC::B:
1404  case PPC::BLR:
1405  case PPC::BLR8:
1406  case PPC::BCTR:
1407  case PPC::BCTR8:
1408  case PPC::BCTRL:
1409  case PPC::BCTRL8:
1410  return true;
1411  }
1412 }
1413 
1415  unsigned &SrcReg, unsigned &SrcReg2,
1416  int &Mask, int &Value) const {
1417  unsigned Opc = MI->getOpcode();
1418 
1419  switch (Opc) {
1420  default: return false;
1421  case PPC::CMPWI:
1422  case PPC::CMPLWI:
1423  case PPC::CMPDI:
1424  case PPC::CMPLDI:
1425  SrcReg = MI->getOperand(1).getReg();
1426  SrcReg2 = 0;
1427  Value = MI->getOperand(2).getImm();
1428  Mask = 0xFFFF;
1429  return true;
1430  case PPC::CMPW:
1431  case PPC::CMPLW:
1432  case PPC::CMPD:
1433  case PPC::CMPLD:
1434  case PPC::FCMPUS:
1435  case PPC::FCMPUD:
1436  SrcReg = MI->getOperand(1).getReg();
1437  SrcReg2 = MI->getOperand(2).getReg();
1438  return true;
1439  }
1440 }
1441 
1443  unsigned SrcReg, unsigned SrcReg2,
1444  int Mask, int Value,
1445  const MachineRegisterInfo *MRI) const {
1446  if (DisableCmpOpt)
1447  return false;
1448 
1449  int OpC = CmpInstr->getOpcode();
1450  unsigned CRReg = CmpInstr->getOperand(0).getReg();
1451 
1452  // FP record forms set CR1 based on the execption status bits, not a
1453  // comparison with zero.
1454  if (OpC == PPC::FCMPUS || OpC == PPC::FCMPUD)
1455  return false;
1456 
1457  // The record forms set the condition register based on a signed comparison
1458  // with zero (so says the ISA manual). This is not as straightforward as it
1459  // seems, however, because this is always a 64-bit comparison on PPC64, even
1460  // for instructions that are 32-bit in nature (like slw for example).
1461  // So, on PPC32, for unsigned comparisons, we can use the record forms only
1462  // for equality checks (as those don't depend on the sign). On PPC64,
1463  // we are restricted to equality for unsigned 64-bit comparisons and for
1464  // signed 32-bit comparisons the applicability is more restricted.
1465  bool isPPC64 = Subtarget.isPPC64();
1466  bool is32BitSignedCompare = OpC == PPC::CMPWI || OpC == PPC::CMPW;
1467  bool is32BitUnsignedCompare = OpC == PPC::CMPLWI || OpC == PPC::CMPLW;
1468  bool is64BitUnsignedCompare = OpC == PPC::CMPLDI || OpC == PPC::CMPLD;
1469 
1470  // Get the unique definition of SrcReg.
1471  MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
1472  if (!MI) return false;
1473  int MIOpC = MI->getOpcode();
1474 
1475  bool equalityOnly = false;
1476  bool noSub = false;
1477  if (isPPC64) {
1478  if (is32BitSignedCompare) {
1479  // We can perform this optimization only if MI is sign-extending.
1480  if (MIOpC == PPC::SRAW || MIOpC == PPC::SRAWo ||
1481  MIOpC == PPC::SRAWI || MIOpC == PPC::SRAWIo ||
1482  MIOpC == PPC::EXTSB || MIOpC == PPC::EXTSBo ||
1483  MIOpC == PPC::EXTSH || MIOpC == PPC::EXTSHo ||
1484  MIOpC == PPC::EXTSW || MIOpC == PPC::EXTSWo) {
1485  noSub = true;
1486  } else
1487  return false;
1488  } else if (is32BitUnsignedCompare) {
1489  // We can perform this optimization, equality only, if MI is
1490  // zero-extending.
1491  if (MIOpC == PPC::CNTLZW || MIOpC == PPC::CNTLZWo ||
1492  MIOpC == PPC::SLW || MIOpC == PPC::SLWo ||
1493  MIOpC == PPC::SRW || MIOpC == PPC::SRWo) {
1494  noSub = true;
1495  equalityOnly = true;
1496  } else
1497  return false;
1498  } else
1499  equalityOnly = is64BitUnsignedCompare;
1500  } else
1501  equalityOnly = is32BitUnsignedCompare;
1502 
1503  if (equalityOnly) {
1504  // We need to check the uses of the condition register in order to reject
1505  // non-equality comparisons.
1507  IE = MRI->use_instr_end(); I != IE; ++I) {
1508  MachineInstr *UseMI = &*I;
1509  if (UseMI->getOpcode() == PPC::BCC) {
1510  unsigned Pred = UseMI->getOperand(0).getImm();
1511  if (Pred != PPC::PRED_EQ && Pred != PPC::PRED_NE)
1512  return false;
1513  } else if (UseMI->getOpcode() == PPC::ISEL ||
1514  UseMI->getOpcode() == PPC::ISEL8) {
1515  unsigned SubIdx = UseMI->getOperand(3).getSubReg();
1516  if (SubIdx != PPC::sub_eq)
1517  return false;
1518  } else
1519  return false;
1520  }
1521  }
1522 
1523  MachineBasicBlock::iterator I = CmpInstr;
1524 
1525  // Scan forward to find the first use of the compare.
1526  for (MachineBasicBlock::iterator EL = CmpInstr->getParent()->end();
1527  I != EL; ++I) {
1528  bool FoundUse = false;
1530  JE = MRI->use_instr_end(); J != JE; ++J)
1531  if (&*J == &*I) {
1532  FoundUse = true;
1533  break;
1534  }
1535 
1536  if (FoundUse)
1537  break;
1538  }
1539 
1540  // There are two possible candidates which can be changed to set CR[01].
1541  // One is MI, the other is a SUB instruction.
1542  // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
1543  MachineInstr *Sub = nullptr;
1544  if (SrcReg2 != 0)
1545  // MI is not a candidate for CMPrr.
1546  MI = nullptr;
1547  // FIXME: Conservatively refuse to convert an instruction which isn't in the
1548  // same BB as the comparison. This is to allow the check below to avoid calls
1549  // (and other explicit clobbers); instead we should really check for these
1550  // more explicitly (in at least a few predecessors).
1551  else if (MI->getParent() != CmpInstr->getParent() || Value != 0) {
1552  // PPC does not have a record-form SUBri.
1553  return false;
1554  }
1555 
1556  // Search for Sub.
1557  const TargetRegisterInfo *TRI = &getRegisterInfo();
1558  --I;
1559 
1560  // Get ready to iterate backward from CmpInstr.
1562  B = CmpInstr->getParent()->begin();
1563 
1564  for (; I != E && !noSub; --I) {
1565  const MachineInstr &Instr = *I;
1566  unsigned IOpC = Instr.getOpcode();
1567 
1568  if (&*I != CmpInstr && (
1569  Instr.modifiesRegister(PPC::CR0, TRI) ||
1570  Instr.readsRegister(PPC::CR0, TRI)))
1571  // This instruction modifies or uses the record condition register after
1572  // the one we want to change. While we could do this transformation, it
1573  // would likely not be profitable. This transformation removes one
1574  // instruction, and so even forcing RA to generate one move probably
1575  // makes it unprofitable.
1576  return false;
1577 
1578  // Check whether CmpInstr can be made redundant by the current instruction.
1579  if ((OpC == PPC::CMPW || OpC == PPC::CMPLW ||
1580  OpC == PPC::CMPD || OpC == PPC::CMPLD) &&
1581  (IOpC == PPC::SUBF || IOpC == PPC::SUBF8) &&
1582  ((Instr.getOperand(1).getReg() == SrcReg &&
1583  Instr.getOperand(2).getReg() == SrcReg2) ||
1584  (Instr.getOperand(1).getReg() == SrcReg2 &&
1585  Instr.getOperand(2).getReg() == SrcReg))) {
1586  Sub = &*I;
1587  break;
1588  }
1589 
1590  if (I == B)
1591  // The 'and' is below the comparison instruction.
1592  return false;
1593  }
1594 
1595  // Return false if no candidates exist.
1596  if (!MI && !Sub)
1597  return false;
1598 
1599  // The single candidate is called MI.
1600  if (!MI) MI = Sub;
1601 
1602  int NewOpC = -1;
1603  MIOpC = MI->getOpcode();
1604  if (MIOpC == PPC::ANDIo || MIOpC == PPC::ANDIo8)
1605  NewOpC = MIOpC;
1606  else {
1607  NewOpC = PPC::getRecordFormOpcode(MIOpC);
1608  if (NewOpC == -1 && PPC::getNonRecordFormOpcode(MIOpC) != -1)
1609  NewOpC = MIOpC;
1610  }
1611 
1612  // FIXME: On the non-embedded POWER architectures, only some of the record
1613  // forms are fast, and we should use only the fast ones.
1614 
1615  // The defining instruction has a record form (or is already a record
1616  // form). It is possible, however, that we'll need to reverse the condition
1617  // code of the users.
1618  if (NewOpC == -1)
1619  return false;
1620 
1623 
1624  // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based on CMP
1625  // needs to be updated to be based on SUB. Push the condition code
1626  // operands to OperandsToUpdate. If it is safe to remove CmpInstr, the
1627  // condition code of these operands will be modified.
1628  bool ShouldSwap = false;
1629  if (Sub) {
1630  ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
1631  Sub->getOperand(2).getReg() == SrcReg;
1632 
1633  // The operands to subf are the opposite of sub, so only in the fixed-point
1634  // case, invert the order.
1635  ShouldSwap = !ShouldSwap;
1636  }
1637 
1638  if (ShouldSwap)
1640  I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
1641  I != IE; ++I) {
1642  MachineInstr *UseMI = &*I;
1643  if (UseMI->getOpcode() == PPC::BCC) {
1644  PPC::Predicate Pred = (PPC::Predicate) UseMI->getOperand(0).getImm();
1645  assert((!equalityOnly ||
1646  Pred == PPC::PRED_EQ || Pred == PPC::PRED_NE) &&
1647  "Invalid predicate for equality-only optimization");
1648  PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)),
1649  PPC::getSwappedPredicate(Pred)));
1650  } else if (UseMI->getOpcode() == PPC::ISEL ||
1651  UseMI->getOpcode() == PPC::ISEL8) {
1652  unsigned NewSubReg = UseMI->getOperand(3).getSubReg();
1653  assert((!equalityOnly || NewSubReg == PPC::sub_eq) &&
1654  "Invalid CR bit for equality-only optimization");
1655 
1656  if (NewSubReg == PPC::sub_lt)
1657  NewSubReg = PPC::sub_gt;
1658  else if (NewSubReg == PPC::sub_gt)
1659  NewSubReg = PPC::sub_lt;
1660 
1661  SubRegsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(3)),
1662  NewSubReg));
1663  } else // We need to abort on a user we don't understand.
1664  return false;
1665  }
1666 
1667  // Create a new virtual register to hold the value of the CR set by the
1668  // record-form instruction. If the instruction was not previously in
1669  // record form, then set the kill flag on the CR.
1670  CmpInstr->eraseFromParent();
1671 
1673  BuildMI(*MI->getParent(), std::next(MII), MI->getDebugLoc(),
1674  get(TargetOpcode::COPY), CRReg)
1675  .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0);
1676 
1677  if (MIOpC != NewOpC) {
1678  // We need to be careful here: we're replacing one instruction with
1679  // another, and we need to make sure that we get all of the right
1680  // implicit uses and defs. On the other hand, the caller may be holding
1681  // an iterator to this instruction, and so we can't delete it (this is
1682  // specifically the case if this is the instruction directly after the
1683  // compare).
1684 
1685  const MCInstrDesc &NewDesc = get(NewOpC);
1686  MI->setDesc(NewDesc);
1687 
1688  if (NewDesc.ImplicitDefs)
1689  for (const uint16_t *ImpDefs = NewDesc.getImplicitDefs();
1690  *ImpDefs; ++ImpDefs)
1691  if (!MI->definesRegister(*ImpDefs))
1692  MI->addOperand(*MI->getParent()->getParent(),
1693  MachineOperand::CreateReg(*ImpDefs, true, true));
1694  if (NewDesc.ImplicitUses)
1695  for (const uint16_t *ImpUses = NewDesc.getImplicitUses();
1696  *ImpUses; ++ImpUses)
1697  if (!MI->readsRegister(*ImpUses))
1698  MI->addOperand(*MI->getParent()->getParent(),
1699  MachineOperand::CreateReg(*ImpUses, false, true));
1700  }
1701 
1702  // Modify the condition code of operands in OperandsToUpdate.
1703  // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
1704  // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
1705  for (unsigned i = 0, e = PredsToUpdate.size(); i < e; i++)
1706  PredsToUpdate[i].first->setImm(PredsToUpdate[i].second);
1707 
1708  for (unsigned i = 0, e = SubRegsToUpdate.size(); i < e; i++)
1709  SubRegsToUpdate[i].first->setSubReg(SubRegsToUpdate[i].second);
1710 
1711  return true;
1712 }
1713 
1714 /// GetInstSize - Return the number of bytes of code the specified
1715 /// instruction may be. This returns the maximum number of bytes.
1716 ///
1718  unsigned Opcode = MI->getOpcode();
1719 
1720  if (Opcode == PPC::INLINEASM) {
1721  const MachineFunction *MF = MI->getParent()->getParent();
1722  const char *AsmStr = MI->getOperand(0).getSymbolName();
1723  return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
1724  } else if (Opcode == TargetOpcode::STACKMAP) {
1725  return MI->getOperand(1).getImm();
1726  } else if (Opcode == TargetOpcode::PATCHPOINT) {
1727  PatchPointOpers Opers(MI);
1729  } else {
1730  const MCInstrDesc &Desc = get(Opcode);
1731  return Desc.getSize();
1732  }
1733 }
1734 
bool isImplicit() const
The memory access reads data.
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
The memory access writes data.
const uint16_t * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
Definition: MCInstrDesc.h:497
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override
int getNonRecordFormOpcode(uint16_t)
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:427
static void Found()
MachineBasicBlock * getMBB() const
bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
bool ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, unsigned Reg, MachineRegisterInfo *MRI) const override
bool hasISEL() const
Definition: PPCSubtarget.h:229
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:138
bool isDead() const
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
A Stackmap instruction captures the location of live variables at its position in the instruction str...
const uint16_t * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction...
Definition: MCInstrDesc.h:475
static cl::opt< bool > DisableCmpOpt("disable-ppc-cmp-opt", cl::desc("Disable compare instruction optimization"), cl::Hidden)
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:264
bool isDarwin() const
isDarwin - True if this is any darwin platform.
Definition: PPCSubtarget.h:261
bool hasSuperClassEq(const TargetRegisterClass *RC) const
hasSuperClassEq - Returns true if RC is a super-class of or equal to this class.
const char * getSymbolName() const
A debug info location.
Definition: DebugLoc.h:34
CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a BCTRL instruction.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, unsigned f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
getMachineMemOperand - Allocate a new MachineMemOperand.
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:419
ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
CreateTargetHazardRecognizer - Return the hazard recognizer to use for this target when scheduling th...
static MachinePointerInfo getFixedStack(int FI, int64_t offset=0)
getFixedStack - Return a MachinePointerInfo record that refers to the the specified FrameIndex...
MachineInstr * commuteInstruction(MachineInstr *MI, bool NewMI) const override
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, const BranchProbability &Probability) const override
Definition: PPCInstrInfo.h:184
MachineFunction & MF
Definition: ScheduleDAG.h:563
COPY - Target-independent register copy.
Definition: TargetOpcodes.h:86
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const
Return the cycle for the given class and operand.
PPCDispatchGroupSBHazardRecognizer - This class implements a scoreboard-based hazard recognizer for P...
MachineMemOperand - A description of a memory reference used in the backend.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false)
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
use_instr_iterator use_instr_begin(unsigned RegNo) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APInt.h:33
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
const TargetRegisterClass * getRegClass(unsigned Reg) const
getRegClass - Return the register class of the specified virtual register.
iterator begin() const
begin/end - Return all of the registers in this class.
Reg
All possible values of the reg field in the ModR/M byte.
const uint16_t * ImplicitUses
Definition: MCInstrDesc.h:147
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Definition: Value.cpp:317
bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
bool PredicateInstruction(MachineInstr *MI, ArrayRef< MachineOperand > Pred) const override
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:571
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:271
defusechain_iterator - This class provides iterator support for machine operands in the function that...
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
PPCInstrInfo(PPCSubtarget &STI)
bool isKill() const
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
virtual MachineInstr * commuteInstruction(MachineInstr *MI, bool NewMI=false) const
If a target has any instructions that are commutable but require converting to different instructions...
CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based loops.
R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
getMatchingSuperReg - Return a super-register of the specified register Reg so its sub-register of in...
CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: ArrayRef.h:31
unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const override
Itinerary data supplied by a subtarget to be used by a target.
iterator getLastNonDebugInstr()
getLastNonDebugInstr - returns an iterator to the last non-debug instruction in the basic block...
bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override
int64_t getImm() const
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:134
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:150
unsigned getKillRegState(bool B)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:267
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:120
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:247
unsigned getDeadRegState(bool B)
VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
bundle_iterator< MachineInstr, instr_iterator > iterator
Patchable call instruction - this instruction represents a call to a constant address, followed by a series of NOPs.
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
int getAltVSXFMAOpcode(uint16_t Opcode)
bool isUnpredicatedTerminator(const MachineInstr *MI) const override
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Definition: MCInstrDesc.h:532
bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const override
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
void setImm(int64_t immVal)
MI-level patchpoint operands.
Definition: StackMaps.h:40
PPCHazardRecognizer970 - This class defines a finite state automata that models the dispatch logic on...
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:129
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
unsigned getSubReg() const
unsigned RemoveBranch(MachineBasicBlock &MBB) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const override
bool isPseudo() const
Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction...
Definition: MCInstrDesc.h:208
static unsigned getCRFromCRBit(unsigned SrcReg)
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:162
bool isPredicable(MachineInstr *MI) const override
bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
Definition: MachineInstr.h:866
void setIsKill(bool Val=true)
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
static bool MBBDefinesCTR(MachineBasicBlock &MBB)
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr *MI, unsigned *PredCost=nullptr) const override
bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
Definition: MachineInstr.h:836
void setOpcode(unsigned Op)
Definition: MCInst.h:158
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const
If specified MI is commutable, return the two operand indices that would swap value.
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
static unsigned getCRBitValue(unsigned CRBit)
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:861
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
int getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const override
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:27
static cl::opt< bool > VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy", cl::desc("Causes the backend to crash instead of generating a nop VSX copy"), cl::Hidden)
static cl::opt< bool > UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden, cl::desc("Use the old (incorrect) instruction latency calculation"))
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
bool isPredicated(const MachineInstr *MI) const override
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
void getNoopForMachoTarget(MCInst &NopInst) const override
getNoopForMachoTarget - Return the noop instruction to use for a noop.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:238
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
TargetSubtargetInfo - Generic base class for all target subtargets.
const PPCRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: PPCInstrInfo.h:89
Representation of each machine instruction.
Definition: MachineInstr.h:51
Predicate InvertPredicate(Predicate Opcode)
Invert the specified predicate. != -> ==, < -> >=.
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:528
const MachineOperand & getMetaOper(unsigned Pos)
Definition: StackMaps.h:61
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
void setReg(unsigned Reg)
Change the register this operand corresponds to.
static MachineOperand CreateImm(int64_t Val)
#define I(x, y, z)
Definition: MD5.cpp:54
void setSubReg(unsigned subReg)
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const TargetInstrInfo * TII
Definition: ScheduleDAG.h:561
virtual ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
unsigned getReg() const
getReg - Returns the register number.
const uint16_t * ImplicitDefs
Definition: MCInstrDesc.h:148
unsigned GetInstSizeInBytes(const MachineInstr *MI) const
GetInstSize - Return the number of bytes of code the specified instruction may be.
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
LLVM Value Representation.
Definition: Value.h:69
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
static use_instr_iterator use_instr_end()
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:185
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:149
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
unsigned getDarwinDirective() const
getDarwinDirective - Returns the -m directive specified for the cpu.
Definition: PPCSubtarget.h:152
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, DebugLoc DL) const override
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer to use for this target when ...
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:56
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
static cl::opt< bool > DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden, cl::desc("Disable analysis for CTR loops"))
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
Definition: MachineInstr.h:874
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:410
bool DefinesPredicate(MachineInstr *MI, std::vector< MachineOperand > &Pred) const override
bool contains(unsigned Reg) const
contains - Return true if the specified register is included in this register class.
Predicate getSwappedPredicate(Predicate Opcode)
Assume the condition register is set by MI(a,b), return the predicate if we modify the instructions s...