| AMDGPURegisterInfo() | llvm::AMDGPURegisterInfo | |
| CalleeSavedReg | llvm::AMDGPURegisterInfo | static |
| eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const override | llvm::SIRegisterInfo | |
| findUnusedRegister(const MachineRegisterInfo &MRI, const TargetRegisterClass *RC) const | llvm::SIRegisterInfo | |
| getCalleeSavedRegs(const MachineFunction *MF) const override | llvm::AMDGPURegisterInfo | |
| getCFGStructurizerRegClass(MVT VT) const override | llvm::SIRegisterInfo | virtual |
| getEquivalentVGPRClass(const TargetRegisterClass *SRC) const | llvm::SIRegisterInfo | |
| getFrameRegister(const MachineFunction &MF) const override | llvm::AMDGPURegisterInfo | |
| getHWRegIndex(unsigned Reg) const override | llvm::SIRegisterInfo | virtual |
| getIndirectSubReg(unsigned IndirectIndex) const | llvm::AMDGPURegisterInfo | |
| getNumSGPRsAllowed(AMDGPUSubtarget::Generation gen, unsigned WaveCount) const | llvm::SIRegisterInfo | |
| getNumVGPRsAllowed(unsigned WaveCount) const | llvm::SIRegisterInfo | |
| getPhysRegClass(unsigned Reg) const | llvm::SIRegisterInfo | |
| getPhysRegSubReg(unsigned Reg, const TargetRegisterClass *SubRC, unsigned Channel) const | llvm::SIRegisterInfo | |
| getPreloadedValue(const MachineFunction &MF, enum PreloadedValue Value) const | llvm::SIRegisterInfo | |
| getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override | llvm::SIRegisterInfo | |
| getReservedRegs(const MachineFunction &MF) const override | llvm::SIRegisterInfo | |
| getSubRegClass(const TargetRegisterClass *RC, unsigned SubIdx) const | llvm::SIRegisterInfo | |
| getSubRegFromChannel(unsigned Channel) const | llvm::AMDGPURegisterInfo | |
| hasVGPRs(const TargetRegisterClass *RC) const | llvm::SIRegisterInfo | |
| INPUT_PTR enum value | llvm::SIRegisterInfo | |
| isSGPRClass(const TargetRegisterClass *RC) const | llvm::SIRegisterInfo | inline |
| isSGPRClassID(unsigned RCID) const | llvm::SIRegisterInfo | inline |
| opCanUseInlineConstant(unsigned OpType) const | llvm::SIRegisterInfo | |
| opCanUseLiteralConstant(unsigned OpType) const | llvm::SIRegisterInfo | |
| PreloadedValue enum name | llvm::SIRegisterInfo | |
| requiresRegisterScavenging(const MachineFunction &Fn) const override | llvm::SIRegisterInfo | |
| SCRATCH_PTR enum value | llvm::SIRegisterInfo | |
| SCRATCH_WAVE_OFFSET enum value | llvm::SIRegisterInfo | |
| SIRegisterInfo() | llvm::SIRegisterInfo | |
| TGID_X enum value | llvm::SIRegisterInfo | |
| TGID_Y enum value | llvm::SIRegisterInfo | |
| TGID_Z enum value | llvm::SIRegisterInfo | |
| TIDIG_X enum value | llvm::SIRegisterInfo | |
| TIDIG_Y enum value | llvm::SIRegisterInfo | |
| TIDIG_Z enum value | llvm::SIRegisterInfo | |