62 #define DEBUG_TYPE "ppcfastisel"
81 : BaseType(RegBase), Offset(0) {
86 class PPCFastISel final :
public FastISel {
101 TII(*PPCSubTarget->getInstrInfo()),
102 TLI(*PPCSubTarget->getTargetLowering()),
107 bool fastSelectInstruction(
const Instruction *
I)
override;
108 unsigned fastMaterializeConstant(
const Constant *
C)
override;
109 unsigned fastMaterializeAlloca(
const AllocaInst *AI)
override;
112 bool fastLowerArguments()
override;
113 unsigned fastEmit_i(
MVT Ty,
MVT RetTy,
unsigned Opc, uint64_t Imm)
override;
114 unsigned fastEmitInst_ri(
unsigned MachineInstOpcode,
116 unsigned Op0,
bool Op0IsKill,
118 unsigned fastEmitInst_r(
unsigned MachineInstOpcode,
120 unsigned Op0,
bool Op0IsKill);
121 unsigned fastEmitInst_rr(
unsigned MachineInstOpcode,
123 unsigned Op0,
bool Op0IsKill,
124 unsigned Op1,
bool Op1IsKill);
126 bool fastLowerCall(CallLoweringInfo &CLI)
override;
136 bool SelectIToFP(
const Instruction *I,
bool IsSigned);
137 bool SelectFPToI(
const Instruction *I,
bool IsSigned);
138 bool SelectBinaryIntOp(
const Instruction *I,
unsigned ISDOpcode);
145 bool isTypeLegal(
Type *Ty,
MVT &VT);
146 bool isLoadTypeLegal(
Type *Ty,
MVT &VT);
147 bool isValueAvailable(
const Value *V)
const;
148 bool isVSFRCRegister(
unsigned Register)
const {
149 return MRI.getRegClass(Register)->getID() == PPC::VSFRCRegClassID;
151 bool isVSSRCRegister(
unsigned Register)
const {
152 return MRI.getRegClass(Register)->getID() == PPC::VSSRCRegClassID;
154 bool PPCEmitCmp(
const Value *Src1Value,
const Value *Src2Value,
155 bool isZExt,
unsigned DestReg);
156 bool PPCEmitLoad(
MVT VT,
unsigned &ResultReg,
Address &Addr,
158 unsigned FP64LoadOpc = PPC::LFD);
159 bool PPCEmitStore(
MVT VT,
unsigned SrcReg,
Address &Addr);
160 bool PPCComputeAddress(
const Value *Obj,
Address &Addr);
161 void PPCSimplifyAddress(
Address &Addr,
MVT VT,
bool &UseOffset,
163 bool PPCEmitIntExt(
MVT SrcVT,
unsigned SrcReg,
MVT DestVT,
164 unsigned DestReg,
bool IsZExt);
167 unsigned PPCMaterializeInt(
const Constant *C,
MVT VT,
bool UseSExt =
true);
168 unsigned PPCMaterialize32BitInt(int64_t Imm,
170 unsigned PPCMaterialize64BitInt(int64_t Imm,
173 unsigned SrcReg,
bool IsSigned);
174 unsigned PPCMoveToFPReg(
MVT VT,
unsigned SrcReg,
bool IsSigned);
186 bool finishCall(
MVT RetVT, CallLoweringInfo &CLI,
unsigned &NumBytes);
190 #include "PPCGenFastISel.inc"
196 #include "PPCGenCallingConv.inc"
202 return CC_PPC32_SVR4;
204 return CC_PPC32_SVR4_ByVal;
206 return CC_PPC32_SVR4_VarArg;
264 bool PPCFastISel::isTypeLegal(
Type *Ty,
MVT &VT) {
265 EVT Evt = TLI.getValueType(DL, Ty,
true);
273 return TLI.isTypeLegal(VT);
278 bool PPCFastISel::isLoadTypeLegal(
Type *Ty,
MVT &VT) {
279 if (isTypeLegal(Ty, VT))
return true;
290 bool PPCFastISel::isValueAvailable(
const Value *V)
const {
291 if (!isa<Instruction>(V))
294 const auto *
I = cast<Instruction>(V);
295 if (FuncInfo.MBBMap[
I->getParent()] == FuncInfo.MBB)
303 bool PPCFastISel::PPCComputeAddress(
const Value *Obj,
Address &Addr) {
304 const User *U =
nullptr;
305 unsigned Opcode = Instruction::UserOp1;
306 if (
const Instruction *
I = dyn_cast<Instruction>(Obj)) {
309 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
310 FuncInfo.MBBMap[
I->getParent()] == FuncInfo.MBB) {
311 Opcode =
I->getOpcode();
314 }
else if (
const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
315 Opcode =
C->getOpcode();
322 case Instruction::BitCast:
324 return PPCComputeAddress(U->
getOperand(0), Addr);
325 case Instruction::IntToPtr:
328 TLI.getPointerTy(DL))
329 return PPCComputeAddress(U->
getOperand(0), Addr);
331 case Instruction::PtrToInt:
333 if (TLI.getValueType(DL, U->
getType()) == TLI.getPointerTy(DL))
334 return PPCComputeAddress(U->
getOperand(0), Addr);
336 case Instruction::GetElementPtr: {
338 long TmpOffset = Addr.Offset;
344 II !=
IE; ++II, ++GTI) {
345 const Value *Op = *II;
346 if (
StructType *STy = dyn_cast<StructType>(*GTI)) {
348 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
353 if (
const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
355 TmpOffset += CI->getSExtValue() * S;
358 if (canFoldAddIntoGEP(U, Op)) {
361 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
364 Op = cast<AddOperator>(Op)->getOperand(0);
368 goto unsupported_gep;
374 Addr.Offset = TmpOffset;
375 if (PPCComputeAddress(U->
getOperand(0), Addr))
return true;
383 case Instruction::Alloca: {
386 FuncInfo.StaticAllocaMap.find(AI);
387 if (SI != FuncInfo.StaticAllocaMap.end()) {
388 Addr.BaseType = Address::FrameIndexBase;
389 Addr.Base.FI = SI->second;
403 if (Addr.Base.Reg == 0)
404 Addr.Base.Reg = getRegForValue(Obj);
408 if (Addr.Base.Reg != 0)
409 MRI.setRegClass(Addr.Base.Reg, &PPC::G8RC_and_G8RC_NOX0RegClass);
411 return Addr.Base.Reg != 0;
417 void PPCFastISel::PPCSimplifyAddress(
Address &Addr,
MVT VT,
bool &UseOffset,
418 unsigned &IndexReg) {
427 if (!UseOffset && Addr.BaseType == Address::FrameIndexBase) {
428 unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
429 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(PPC::ADDI8),
430 ResultReg).addFrameIndex(Addr.Base.FI).
addImm(0);
431 Addr.Base.Reg = ResultReg;
432 Addr.BaseType = Address::RegBase;
440 IndexReg = PPCMaterializeInt(Offset,
MVT::i64);
441 assert(IndexReg &&
"Unexpected error in PPCMaterializeInt!");
448 bool PPCFastISel::PPCEmitLoad(
MVT VT,
unsigned &ResultReg,
Address &Addr,
450 bool IsZExt,
unsigned FP64LoadOpc) {
452 bool UseOffset =
true;
462 (ResultReg ? MRI.getRegClass(ResultReg) :
464 (VT ==
MVT::f64 ? &PPC::F8RCRegClass :
465 (VT ==
MVT::f32 ? &PPC::F4RCRegClass :
466 (VT ==
MVT::i64 ? &PPC::G8RC_and_G8RC_NOX0RegClass :
467 &PPC::GPRC_and_GPRC_NOR0RegClass)))));
475 Opc = Is32BitInt ? PPC::LBZ : PPC::LBZ8;
479 (Is32BitInt ? PPC::LHZ : PPC::LHZ8) :
480 (Is32BitInt ? PPC::LHA : PPC::LHA8));
484 (Is32BitInt ? PPC::LWZ : PPC::LWZ8) :
485 (Is32BitInt ? PPC::LWA_32 : PPC::LWA));
486 if ((Opc == PPC::LWA || Opc == PPC::LWA_32) && ((Addr.Offset & 3) != 0))
492 "64-bit load with 32-bit target??");
493 UseOffset = ((Addr.Offset & 3) == 0);
505 unsigned IndexReg = 0;
506 PPCSimplifyAddress(Addr, VT, UseOffset, IndexReg);
510 bool IsVSSRC = (ResultReg != 0) && isVSSRCRegister(ResultReg);
511 bool IsVSFRC = (ResultReg != 0) && isVSFRCRegister(ResultReg);
512 bool Is32VSXLoad = IsVSSRC && Opc == PPC::LFS;
513 bool Is64VSXLoad = IsVSSRC && Opc == PPC::LFD;
514 if ((Is32VSXLoad || Is64VSXLoad) &&
515 (Addr.BaseType != Address::FrameIndexBase) && UseOffset &&
516 (Addr.Offset == 0)) {
521 ResultReg = createResultReg(UseRC);
526 if (Addr.BaseType == Address::FrameIndexBase) {
528 if (Is32VSXLoad || Is64VSXLoad)
return false;
531 FuncInfo.MF->getMachineMemOperand(
534 MFI.getObjectAlignment(Addr.Base.FI));
536 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(Opc), ResultReg)
540 }
else if (UseOffset) {
542 if (Is32VSXLoad || Is64VSXLoad)
return false;
544 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(Opc), ResultReg)
545 .addImm(Addr.Offset).
addReg(Addr.Base.Reg);
554 case PPC::LBZ: Opc = PPC::LBZX;
break;
555 case PPC::LBZ8: Opc = PPC::LBZX8;
break;
556 case PPC::LHZ: Opc = PPC::LHZX;
break;
557 case PPC::LHZ8: Opc = PPC::LHZX8;
break;
558 case PPC::LHA: Opc = PPC::LHAX;
break;
559 case PPC::LHA8: Opc = PPC::LHAX8;
break;
560 case PPC::LWZ: Opc = PPC::LWZX;
break;
561 case PPC::LWZ8: Opc = PPC::LWZX8;
break;
562 case PPC::LWA: Opc = PPC::LWAX;
break;
563 case PPC::LWA_32: Opc = PPC::LWAX_32;
break;
564 case PPC::LD: Opc = PPC::LDX;
break;
565 case PPC::LFS: Opc = IsVSSRC ? PPC::LXSSPX : PPC::LFSX;
break;
566 case PPC::LFD: Opc = IsVSFRC ? PPC::LXSDX : PPC::LFDX;
break;
568 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(Opc), ResultReg)
569 .addReg(Addr.Base.Reg).
addReg(IndexReg);
583 if (!isLoadTypeLegal(I->
getType(), VT))
588 if (!PPCComputeAddress(I->
getOperand(0), Addr))
594 unsigned AssignedReg = FuncInfo.ValueMap[
I];
596 AssignedReg ? MRI.getRegClass(AssignedReg) :
nullptr;
598 unsigned ResultReg = 0;
599 if (!PPCEmitLoad(VT, ResultReg, Addr, RC))
601 updateValueMap(I, ResultReg);
606 bool PPCFastISel::PPCEmitStore(
MVT VT,
unsigned SrcReg,
Address &Addr) {
607 assert(SrcReg &&
"Nothing to store!");
609 bool UseOffset =
true;
618 Opc = Is32BitInt ? PPC::STB : PPC::STB8;
621 Opc = Is32BitInt ? PPC::STH : PPC::STH8;
624 assert(Is32BitInt &&
"Not GPRC for i32??");
629 UseOffset = ((Addr.Offset & 3) == 0);
641 unsigned IndexReg = 0;
642 PPCSimplifyAddress(Addr, VT, UseOffset, IndexReg);
646 bool IsVSSRC = isVSSRCRegister(SrcReg);
647 bool IsVSFRC = isVSFRCRegister(SrcReg);
648 bool Is32VSXStore = IsVSSRC && Opc == PPC::STFS;
649 bool Is64VSXStore = IsVSFRC && Opc == PPC::STFD;
650 if ((Is32VSXStore || Is64VSXStore) &&
651 (Addr.BaseType != Address::FrameIndexBase) && UseOffset &&
652 (Addr.Offset == 0)) {
659 if (Addr.BaseType == Address::FrameIndexBase) {
661 if (Is32VSXStore || Is64VSXStore)
return false;
664 FuncInfo.MF->getMachineMemOperand(
667 MFI.getObjectAlignment(Addr.Base.FI));
669 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(Opc))
676 }
else if (UseOffset) {
678 if (Is32VSXStore || Is64VSXStore)
return false;
680 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(Opc))
681 .addReg(SrcReg).
addImm(Addr.Offset).
addReg(Addr.Base.Reg);
690 case PPC::STB: Opc = PPC::STBX;
break;
691 case PPC::STH : Opc = PPC::STHX;
break;
692 case PPC::STW : Opc = PPC::STWX;
break;
693 case PPC::STB8: Opc = PPC::STBX8;
break;
694 case PPC::STH8: Opc = PPC::STHX8;
break;
695 case PPC::STW8: Opc = PPC::STWX8;
break;
696 case PPC::STD: Opc = PPC::STDX;
break;
697 case PPC::STFS: Opc = IsVSSRC ? PPC::STXSSPX : PPC::STFSX;
break;
698 case PPC::STFD: Opc = IsVSFRC ? PPC::STXSDX : PPC::STFDX;
break;
701 auto MIB =
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(Opc))
709 MIB.addReg(Addr.Base.Reg).addReg(IndexReg);
711 MIB.addReg(PPC::ZERO8).addReg(Addr.Base.Reg);
718 bool PPCFastISel::SelectStore(
const Instruction *I) {
728 if (!isLoadTypeLegal(Op0->
getType(), VT))
732 SrcReg = getRegForValue(Op0);
738 if (!PPCComputeAddress(I->
getOperand(1), Addr))
741 if (!PPCEmitStore(VT, SrcReg, Addr))
748 bool PPCFastISel::SelectBranch(
const Instruction *I) {
756 if (isValueAvailable(CI)) {
764 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
769 unsigned CondReg = createResultReg(&PPC::CRRCRegClass);
771 if (!PPCEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned(),
775 BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc,
TII.get(PPC::BCC))
777 fastEmitBranch(FBB, DbgLoc);
778 FuncInfo.MBB->addSuccessor(TBB);
783 uint64_t Imm = CI->getZExtValue();
785 fastEmitBranch(Target, DbgLoc);
800 bool PPCFastISel::PPCEmitCmp(
const Value *SrcValue1,
const Value *SrcValue2,
801 bool IsZExt,
unsigned DestReg) {
803 EVT SrcEVT = TLI.getValueType(DL, Ty,
true);
808 if (SrcVT ==
MVT::i1 && PPCSubTarget->useCRBits())
820 if (
const ConstantInt *ConstInt = dyn_cast<ConstantInt>(SrcValue2)) {
823 const APInt &CIVal = ConstInt->getValue();
831 bool NeedsExt =
false;
833 default:
return false;
835 CmpOpc = PPC::FCMPUS;
838 CmpOpc = PPC::FCMPUD;
847 CmpOpc = IsZExt ? PPC::CMPLW : PPC::CMPW;
849 CmpOpc = IsZExt ? PPC::CMPLWI : PPC::CMPWI;
853 CmpOpc = IsZExt ? PPC::CMPLD : PPC::CMPD;
855 CmpOpc = IsZExt ? PPC::CMPLDI : PPC::CMPDI;
859 unsigned SrcReg1 = getRegForValue(SrcValue1);
863 unsigned SrcReg2 = 0;
865 SrcReg2 = getRegForValue(SrcValue2);
871 unsigned ExtReg = createResultReg(&PPC::GPRCRegClass);
872 if (!PPCEmitIntExt(SrcVT, SrcReg1,
MVT::i32, ExtReg, IsZExt))
877 unsigned ExtReg = createResultReg(&PPC::GPRCRegClass);
878 if (!PPCEmitIntExt(SrcVT, SrcReg2,
MVT::i32, ExtReg, IsZExt))
885 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(CmpOpc), DestReg)
886 .addReg(SrcReg1).
addReg(SrcReg2);
888 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(CmpOpc), DestReg)
889 .addReg(SrcReg1).
addImm(Imm);
895 bool PPCFastISel::SelectFPExt(
const Instruction *I) {
897 EVT SrcVT = TLI.getValueType(DL, Src->
getType(),
true);
898 EVT DestVT = TLI.getValueType(DL, I->
getType(),
true);
903 unsigned SrcReg = getRegForValue(Src);
908 updateValueMap(I, SrcReg);
913 bool PPCFastISel::SelectFPTrunc(
const Instruction *I) {
915 EVT SrcVT = TLI.getValueType(DL, Src->
getType(),
true);
916 EVT DestVT = TLI.getValueType(DL, I->
getType(),
true);
921 unsigned SrcReg = getRegForValue(Src);
926 unsigned DestReg = createResultReg(&PPC::F4RCRegClass);
927 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(PPC::FRSP), DestReg)
930 updateValueMap(I, DestReg);
941 unsigned PPCFastISel::PPCMoveToFPReg(
MVT SrcVT,
unsigned SrcReg,
946 unsigned TmpReg = createResultReg(&PPC::G8RCRegClass);
954 Addr.BaseType = Address::FrameIndexBase;
955 Addr.Base.FI = MFI.CreateStackObject(8, 8,
false);
958 if (!PPCEmitStore(
MVT::i64, SrcReg, Addr))
963 unsigned LoadOpc = PPC::LFD;
968 Addr.Offset = (PPCSubTarget->isLittleEndian()) ? 0 : 4;
969 }
else if (PPCSubTarget->hasLFIWAX()) {
971 Addr.Offset = (PPCSubTarget->isLittleEndian()) ? 0 : 4;
976 unsigned ResultReg = 0;
977 if (!PPCEmitLoad(
MVT::f64, ResultReg, Addr, RC, !IsSigned, LoadOpc))
986 bool PPCFastISel::SelectIToFP(
const Instruction *I,
bool IsSigned) {
989 if (!isTypeLegal(DstTy, DstVT))
996 EVT SrcEVT = TLI.getValueType(DL, Src->
getType(),
true);
1006 unsigned SrcReg = getRegForValue(Src);
1012 if (!IsSigned && !PPCSubTarget->hasFPCVT())
1020 if (DstVT ==
MVT::f32 && !PPCSubTarget->hasFPCVT())
1025 unsigned TmpReg = createResultReg(&PPC::G8RCRegClass);
1026 if (!PPCEmitIntExt(SrcVT, SrcReg,
MVT::i64, TmpReg, !IsSigned))
1033 unsigned FPReg = PPCMoveToFPReg(SrcVT, SrcReg, IsSigned);
1039 unsigned DestReg = createResultReg(RC);
1048 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(Opc), DestReg)
1051 updateValueMap(I, DestReg);
1060 unsigned PPCFastISel::PPCMoveToIntReg(
const Instruction *I,
MVT VT,
1061 unsigned SrcReg,
bool IsSigned) {
1067 Addr.BaseType = Address::FrameIndexBase;
1068 Addr.Base.FI = MFI.CreateStackObject(8, 8,
false);
1071 if (!PPCEmitStore(
MVT::f64, SrcReg, Addr))
1081 unsigned AssignedReg = FuncInfo.ValueMap[
I];
1083 AssignedReg ? MRI.getRegClass(AssignedReg) :
nullptr;
1085 unsigned ResultReg = 0;
1086 if (!PPCEmitLoad(VT, ResultReg, Addr, RC, !IsSigned))
1095 bool PPCFastISel::SelectFPToI(
const Instruction *I,
bool IsSigned) {
1098 if (!isTypeLegal(DstTy, DstVT))
1105 if (DstVT ==
MVT::i64 && !IsSigned && !PPCSubTarget->hasFPCVT())
1110 if (!isTypeLegal(SrcTy, SrcVT))
1116 unsigned SrcReg = getRegForValue(Src);
1124 if (InRC == &PPC::F4RCRegClass) {
1125 unsigned TmpReg = createResultReg(&PPC::F8RCRegClass);
1126 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1128 .addReg(SrcReg).
addImm(PPC::F8RCRegClassID);
1134 unsigned DestReg = createResultReg(&PPC::F8RCRegClass);
1146 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(Opc), DestReg)
1150 unsigned IntReg = PPCMoveToIntReg(I, DstVT, DestReg, IsSigned);
1154 updateValueMap(I, IntReg);
1160 bool PPCFastISel::SelectBinaryIntOp(
const Instruction *I,
unsigned ISDOpcode) {
1161 EVT DestVT = TLI.getValueType(DL, I->
getType(),
true);
1171 unsigned AssignedReg = FuncInfo.ValueMap[
I];
1173 (AssignedReg ? MRI.getRegClass(AssignedReg) :
1174 &PPC::GPRC_and_GPRC_NOR0RegClass);
1178 switch (ISDOpcode) {
1179 default:
return false;
1181 Opc = IsGPRC ? PPC::ADD4 : PPC::ADD8;
1184 Opc = IsGPRC ?
PPC::OR : PPC::OR8;
1187 Opc = IsGPRC ? PPC::SUBF : PPC::SUBF8;
1191 unsigned ResultReg = createResultReg(RC ? RC : &PPC::G8RCRegClass);
1192 unsigned SrcReg1 = getRegForValue(I->
getOperand(0));
1193 if (SrcReg1 == 0)
return false;
1197 const APInt &CIVal = ConstInt->getValue();
1206 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass);
1210 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass);
1223 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass);
1232 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass);
1239 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(Opc),
1243 updateValueMap(I, ResultReg);
1250 unsigned SrcReg2 = getRegForValue(I->
getOperand(1));
1251 if (SrcReg2 == 0)
return false;
1257 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(Opc), ResultReg)
1258 .addReg(SrcReg1).
addReg(SrcReg2);
1259 updateValueMap(I, ResultReg);
1274 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, ArgLocs, *Context);
1277 unsigned LinkageSize = PPCSubTarget->getFrameLowering()->getLinkageSize();
1278 CCInfo.AllocateStack(LinkageSize, 8);
1280 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CC_PPC64_ELF_FIS);
1283 for (
unsigned I = 0, E = ArgLocs.
size(); I != E; ++
I) {
1299 NumBytes = CCInfo.getNextStackOffset();
1307 NumBytes = std::max(NumBytes, LinkageSize + 64);
1310 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1311 TII.get(
TII.getCallFrameSetupOpcode()))
1317 unsigned NextGPR = PPC::X3;
1318 unsigned NextFPR = PPC::F1;
1321 for (
unsigned I = 0, E = ArgLocs.
size(); I != E; ++
I) {
1323 unsigned Arg = ArgRegs[VA.
getValNo()];
1335 (DestVT ==
MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1336 unsigned TmpReg = createResultReg(RC);
1337 if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg,
false))
1347 (DestVT ==
MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1348 unsigned TmpReg = createResultReg(RC);
1349 if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg,
true))
1371 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1381 bool PPCFastISel::finishCall(
MVT RetVT, CallLoweringInfo &CLI,
unsigned &NumBytes) {
1385 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1386 TII.get(
TII.getCallFrameDestroyOpcode()))
1394 CCState CCInfo(CC,
false, *FuncInfo.MF, RVLocs, *Context);
1395 CCInfo.AnalyzeCallResult(RetVT, RetCC_PPC64_ELF_FIS);
1397 assert(RVLocs.
size() == 1 &&
"No support for multi-reg return values!");
1398 assert(VA.
isRegLoc() &&
"Can only return in registers!");
1401 MVT CopyVT = DestVT;
1408 unsigned SourcePhysReg = VA.
getLocReg();
1409 unsigned ResultReg = 0;
1411 if (RetVT == CopyVT) {
1413 ResultReg = createResultReg(CpyRC);
1415 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1417 .addReg(SourcePhysReg);
1421 ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1422 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(PPC::FRSP),
1423 ResultReg).addReg(SourcePhysReg);
1430 ResultReg = createResultReg(&PPC::GPRCRegClass);
1432 SourcePhysReg -= PPC::X0 - PPC::R0;
1433 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1435 .addReg(SourcePhysReg);
1438 assert(ResultReg &&
"ResultReg unset!");
1439 CLI.InRegs.push_back(SourcePhysReg);
1440 CLI.ResultReg = ResultReg;
1441 CLI.NumResultRegs = 1;
1447 bool PPCFastISel::fastLowerCall(CallLoweringInfo &CLI) {
1449 bool IsTailCall = CLI.IsTailCall;
1450 bool IsVarArg = CLI.IsVarArg;
1451 const Value *Callee = CLI.Callee;
1454 if (!Callee && !Symbol)
1467 Type *RetTy = CLI.RetTy;
1471 else if (!isTypeLegal(RetTy, RetVT) && RetVT !=
MVT::i16 &&
1474 else if (RetVT ==
MVT::i1 && PPCSubTarget->useCRBits())
1483 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, RVLocs, *Context);
1484 CCInfo.AnalyzeCallResult(RetVT, RetCC_PPC64_ELF_FIS);
1485 if (RVLocs.
size() > 1)
1491 unsigned NumArgs = CLI.OutVals.size();
1506 for (
unsigned i = 0, ie = NumArgs; i != ie; ++i) {
1514 Value *ArgValue = CLI.OutVals[i];
1517 if (!isTypeLegal(ArgTy, ArgVT) && ArgVT !=
MVT::i16 && ArgVT !=
MVT::i8)
1523 unsigned Arg = getRegForValue(ArgValue);
1537 if (!processCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
1538 RegArgs, CC, NumBytes, IsVarArg))
1551 if (CLI.IsPatchPoint)
1552 MIB =
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(PPC::NOP));
1558 MIB =
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1559 TII.get(PPC::BL8_NOP));
1565 for (
unsigned II = 0,
IE = RegArgs.
size(); II !=
IE; ++II)
1570 PPCFuncInfo->setUsesTOCBasePtr();
1575 MIB.
addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
1580 return finishCall(RetVT, CLI, NumBytes);
1584 bool PPCFastISel::SelectRet(
const Instruction *I) {
1586 if (!FuncInfo.CanLowerReturn)
1602 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs, *Context);
1607 if (ValLocs.size() > 1)
1617 if (isa<ConstantInt>(*RV)) {
1623 unsigned SrcReg = PPCMaterializeInt(C,
MVT::i64,
1626 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1632 unsigned Reg = getRegForValue(RV);
1638 for (
unsigned i = 0; i < ValLocs.size(); ++i) {
1641 assert(VA.
isRegLoc() &&
"Can only return in registers!");
1643 unsigned SrcReg = Reg + VA.
getValNo();
1645 EVT RVEVT = TLI.getValueType(DL, RV->
getType());
1651 if (RVVT != DestVT && RVVT !=
MVT::i8 &&
1655 if (RVVT != DestVT) {
1664 (DestVT ==
MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1665 unsigned TmpReg = createResultReg(RC);
1666 if (!PPCEmitIntExt(RVVT, SrcReg, DestVT, TmpReg,
true))
1673 (DestVT ==
MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1674 unsigned TmpReg = createResultReg(RC);
1675 if (!PPCEmitIntExt(RVVT, SrcReg, DestVT, TmpReg,
false))
1683 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1691 TII.get(PPC::BLR8));
1693 for (
unsigned i = 0, e = RetRegs.
size(); i != e; ++i)
1702 bool PPCFastISel::PPCEmitIntExt(
MVT SrcVT,
unsigned SrcReg,
MVT DestVT,
1703 unsigned DestReg,
bool IsZExt) {
1713 Opc = (DestVT ==
MVT::i32) ? PPC::EXTSB : PPC::EXTSB8_32_64;
1715 Opc = (DestVT ==
MVT::i32) ? PPC::EXTSH : PPC::EXTSH8_32_64;
1717 assert(DestVT ==
MVT::i64 &&
"Signed extend from i32 to i32??");
1718 Opc = PPC::EXTSW_32_64;
1720 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(Opc), DestReg)
1729 assert(SrcVT ==
MVT::i16 &&
"Unsigned extend from i32 to i32??");
1732 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(PPC::RLWINM),
1745 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1746 TII.get(PPC::RLDICL_32_64), DestReg)
1754 bool PPCFastISel::SelectIndirectBr(
const Instruction *I) {
1755 unsigned AddrReg = getRegForValue(I->
getOperand(0));
1759 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(PPC::MTCTR8))
1761 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(PPC::BCTR8));
1764 for (
unsigned i = 0, e = IB->getNumSuccessors(); i != e; ++i)
1765 FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[IB->getSuccessor(i)]);
1771 bool PPCFastISel::SelectTrunc(
const Instruction *I) {
1773 EVT SrcVT = TLI.getValueType(DL, Src->
getType(),
true);
1774 EVT DestVT = TLI.getValueType(DL, I->
getType(),
true);
1782 unsigned SrcReg = getRegForValue(Src);
1788 unsigned ResultReg = createResultReg(&PPC::GPRCRegClass);
1789 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1791 ResultReg).addReg(SrcReg, 0, PPC::sub_32);
1795 updateValueMap(I, SrcReg);
1800 bool PPCFastISel::SelectIntExt(
const Instruction *I) {
1805 bool IsZExt = isa<ZExtInst>(
I);
1806 unsigned SrcReg = getRegForValue(Src);
1807 if (!SrcReg)
return false;
1809 EVT SrcEVT, DestEVT;
1810 SrcEVT = TLI.getValueType(DL, SrcTy,
true);
1811 DestEVT = TLI.getValueType(DL, DestTy,
true);
1824 unsigned AssignedReg = FuncInfo.ValueMap[
I];
1826 (AssignedReg ? MRI.getRegClass(AssignedReg) :
1827 (DestVT ==
MVT::i64 ? &PPC::G8RC_and_G8RC_NOX0RegClass :
1828 &PPC::GPRC_and_GPRC_NOR0RegClass));
1829 unsigned ResultReg = createResultReg(RC);
1831 if (!PPCEmitIntExt(SrcVT, SrcReg, DestVT, ResultReg, IsZExt))
1834 updateValueMap(I, ResultReg);
1840 bool PPCFastISel::fastSelectInstruction(
const Instruction *I) {
1844 return SelectLoad(I);
1846 return SelectStore(I);
1847 case Instruction::Br:
1848 return SelectBranch(I);
1849 case Instruction::IndirectBr:
1850 return SelectIndirectBr(I);
1851 case Instruction::FPExt:
1852 return SelectFPExt(I);
1853 case Instruction::FPTrunc:
1854 return SelectFPTrunc(I);
1855 case Instruction::SIToFP:
1856 return SelectIToFP(I,
true);
1857 case Instruction::UIToFP:
1858 return SelectIToFP(I,
false);
1859 case Instruction::FPToSI:
1860 return SelectFPToI(I,
true);
1861 case Instruction::FPToUI:
1862 return SelectFPToI(I,
false);
1863 case Instruction::Add:
1864 return SelectBinaryIntOp(I,
ISD::ADD);
1866 return SelectBinaryIntOp(I,
ISD::OR);
1867 case Instruction::Sub:
1868 return SelectBinaryIntOp(I,
ISD::SUB);
1870 return selectCall(I);
1872 return SelectRet(I);
1873 case Instruction::Trunc:
1874 return SelectTrunc(I);
1875 case Instruction::ZExt:
1876 case Instruction::SExt:
1877 return SelectIntExt(I);
1889 unsigned PPCFastISel::PPCMaterializeFP(
const ConstantFP *CFP,
MVT VT) {
1896 assert(Align > 0 &&
"Unexpectedly missing alignment information!");
1897 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
1898 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
1902 FuncInfo.MF->getMachineMemOperand(
1906 unsigned Opc = (VT ==
MVT::f32) ? PPC::LFS : PPC::LFD;
1907 unsigned TmpReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
1909 PPCFuncInfo->setUsesTOCBasePtr();
1912 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(PPC::LDtocCPT),
1914 .addConstantPoolIndex(Idx).
addReg(PPC::X2);
1915 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(Opc), DestReg)
1919 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(PPC::ADDIStocHA),
1924 unsigned TmpReg2 = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
1925 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(PPC::LDtocL),
1926 TmpReg2).addConstantPoolIndex(Idx).
addReg(TmpReg);
1927 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(Opc), DestReg)
1928 .addImm(0).
addReg(TmpReg2);
1930 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(Opc), DestReg)
1941 unsigned PPCFastISel::PPCMaterializeGV(
const GlobalValue *GV,
MVT VT) {
1942 assert(VT ==
MVT::i64 &&
"Non-address!");
1944 unsigned DestReg = createResultReg(RC);
1959 PPCFuncInfo->setUsesTOCBasePtr();
1962 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(PPC::LDtoc),
1964 .addGlobalAddress(GV)
1975 unsigned HighPartReg = createResultReg(RC);
1976 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(PPC::ADDIStocHA),
1986 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(PPC::LDtocL),
1987 DestReg).addGlobalAddress(GV).
addReg(HighPartReg);
1990 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(PPC::ADDItocL),
1999 unsigned PPCFastISel::PPCMaterialize32BitInt(int64_t Imm,
2001 unsigned Lo = Imm & 0xFFFF;
2002 unsigned Hi = (Imm >> 16) & 0xFFFF;
2004 unsigned ResultReg = createResultReg(RC);
2008 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2009 TII.get(IsGPRC ? PPC::LI : PPC::LI8), ResultReg)
2013 unsigned TmpReg = createResultReg(RC);
2014 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2015 TII.get(IsGPRC ? PPC::LIS : PPC::LIS8), TmpReg)
2017 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2018 TII.get(IsGPRC ? PPC::ORI : PPC::ORI8), ResultReg)
2019 .addReg(TmpReg).
addImm(Lo);
2022 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2023 TII.get(IsGPRC ? PPC::LIS : PPC::LIS8), ResultReg)
2031 unsigned PPCFastISel::PPCMaterialize64BitInt(int64_t Imm,
2033 unsigned Remainder = 0;
2039 Shift = countTrailingZeros<uint64_t>(Imm);
2040 int64_t ImmSh =
static_cast<uint64_t
>(Imm) >> Shift;
2053 unsigned TmpReg1 = PPCMaterialize32BitInt(Imm, RC);
2061 TmpReg2 = createResultReg(RC);
2062 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(PPC::RLDICR),
2063 TmpReg2).addReg(TmpReg1).
addImm(Shift).
addImm(63 - Shift);
2067 unsigned TmpReg3,
Hi,
Lo;
2068 if ((Hi = (Remainder >> 16) & 0xFFFF)) {
2069 TmpReg3 = createResultReg(RC);
2070 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(PPC::ORIS8),
2071 TmpReg3).addReg(TmpReg2).
addImm(Hi);
2075 if ((Lo = Remainder & 0xFFFF)) {
2076 unsigned ResultReg = createResultReg(RC);
2077 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(PPC::ORI8),
2078 ResultReg).addReg(TmpReg3).
addImm(Lo);
2088 unsigned PPCFastISel::PPCMaterializeInt(
const Constant *C,
MVT VT,
2092 if (VT ==
MVT::i1 && PPCSubTarget->useCRBits()) {
2094 unsigned ImmReg = createResultReg(&PPC::CRBITRCRegClass);
2095 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2096 TII.get(CI->
isZero() ? PPC::CRUNSET : PPC::CRSET), ImmReg);
2105 &PPC::GPRCRegClass);
2110 unsigned Opc = (VT ==
MVT::i64) ? PPC::LI8 : PPC::LI;
2111 unsigned ImmReg = createResultReg(RC);
2112 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(Opc), ImmReg)
2121 return PPCMaterialize64BitInt(Imm, RC);
2123 return PPCMaterialize32BitInt(Imm, RC);
2130 unsigned PPCFastISel::fastMaterializeConstant(
const Constant *C) {
2131 EVT CEVT = TLI.getValueType(DL, C->
getType(),
true);
2137 if (
const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
2138 return PPCMaterializeFP(CFP, VT);
2139 else if (
const GlobalValue *GV = dyn_cast<GlobalValue>(C))
2140 return PPCMaterializeGV(GV, VT);
2141 else if (isa<ConstantInt>(C))
2142 return PPCMaterializeInt(C, VT, VT !=
MVT::i1);
2149 unsigned PPCFastISel::fastMaterializeAlloca(
const AllocaInst *AI) {
2151 if (!FuncInfo.StaticAllocaMap.count(AI))
return 0;
2154 if (!isLoadTypeLegal(AI->
getType(), VT))
return 0;
2157 FuncInfo.StaticAllocaMap.
find(AI);
2159 if (SI != FuncInfo.StaticAllocaMap.
end()) {
2160 unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
2161 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(PPC::ADDI8),
2162 ResultReg).addFrameIndex(SI->second).
addImm(0);
2177 bool PPCFastISel::tryToFoldLoadIntoMI(
MachineInstr *
MI,
unsigned OpNo,
2181 if (!isLoadTypeLegal(LI->
getType(), VT))
2185 bool IsZExt =
false;
2191 case PPC::RLDICL_32_64: {
2194 if ((VT ==
MVT::i8 && MB <= 56) ||
2202 case PPC::RLWINM8: {
2205 if ((VT ==
MVT::i8 && MB <= 24) ||
2213 case PPC::EXTSB8_32_64:
2219 case PPC::EXTSH8_32_64: {
2226 case PPC::EXTSW_32_64: {
2235 if (!PPCComputeAddress(LI->
getOperand(0), Addr))
2240 if (!PPCEmitLoad(VT, ResultReg, Addr,
nullptr, IsZExt))
2249 bool PPCFastISel::fastLowerArguments() {
2259 unsigned PPCFastISel::fastEmit_i(
MVT Ty,
MVT VT,
unsigned Opc, uint64_t Imm) {
2266 if (VT ==
MVT::i1 && PPCSubTarget->useCRBits()) {
2267 unsigned ImmReg = createResultReg(&PPC::CRBITRCRegClass);
2268 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2269 TII.get(Imm == 0 ? PPC::CRUNSET : PPC::CRSET), ImmReg);
2278 &PPC::GPRCRegClass);
2280 return PPCMaterialize64BitInt(Imm, RC);
2282 return PPCMaterialize32BitInt(Imm, RC);
2296 unsigned PPCFastISel::fastEmitInst_ri(
unsigned MachineInstOpcode,
2298 unsigned Op0,
bool Op0IsKill,
2300 if (MachineInstOpcode == PPC::ADDI)
2301 MRI.setRegClass(Op0, &PPC::GPRC_and_GPRC_NOR0RegClass);
2302 else if (MachineInstOpcode == PPC::ADDI8)
2303 MRI.setRegClass(Op0, &PPC::G8RC_and_G8RC_NOX0RegClass);
2306 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2307 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2310 Op0, Op0IsKill, Imm);
2316 unsigned PPCFastISel::fastEmitInst_r(
unsigned MachineInstOpcode,
2318 unsigned Op0,
bool Op0IsKill) {
2320 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2321 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2329 unsigned PPCFastISel::fastEmitInst_rr(
unsigned MachineInstOpcode,
2331 unsigned Op0,
bool Op0IsKill,
2332 unsigned Op1,
bool Op1IsKill) {
2334 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2335 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2348 return new PPCFastISel(FuncInfo, LibInfo);
bool isInt< 32 >(int64_t x)
ReturnInst - Return a value (possibly void), from a function.
void push_back(const T &Elt)
The memory access reads data.
Type * getIndexedType() const
FastISel * createFastISel(FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo)
This class is the base class for the comparison instructions.
Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for unsigned integers.
The memory access writes data.
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
uint64_t getZExtValue() const
Get zero extended value.
LocInfo getLocInfo() const
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
unsigned getNumOperands() const
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
0 1 0 0 True if ordered and less than
unsigned getSizeInBits() const
bool hasAvailableExternallyLinkage() const
1 1 1 0 True if unordered or not equal
bool hasSuperClassEq(const TargetRegisterClass *RC) const
hasSuperClassEq - Returns true if RC is a super-class of or equal to this class.
const Function * getParent() const
Return the enclosing method, or null if none.
LoadInst - an instruction for reading from memory.
static MachinePointerInfo getConstantPool()
getConstantPool - Return a MachinePointerInfo record that refers to the constant pool.
static IntegerType * getInt64Ty(LLVMContext &C)
void reserve(size_type N)
unsigned getValNo() const
Newer FCFID[US] integer-to-floating-point conversion instructions for unsigned integers and single-pr...
static MachinePointerInfo getFixedStack(int FI, int64_t offset=0)
getFixedStack - Return a MachinePointerInfo record that refers to the the specified FrameIndex...
COPY - Target-independent register copy.
1 0 0 1 True if unordered or equal
unsigned fastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm)
Emit a MachineInstr with a register operand, an immediate, and a result register in the given registe...
Used to lazily calculate structure layout information for a target machine, based on the DataLayout s...
1 0 0 0 True if unordered: isnan(X) | isnan(Y)
MachineMemOperand - A description of a memory reference used in the backend.
bool hasCommonLinkage() const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
const HexagonInstrInfo * TII
StructType - Class to represent struct types.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
A Use represents the edge between a Value definition and its users.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
unsigned fastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill)
Emit a MachineInstr with one register operand and a result register in the given register class...
Reg
All possible values of the reg field in the ModR/M byte.
0 1 0 1 True if ordered and less than or equal
bool isStrongDefinitionForLinker() const
Returns true if this global's definition will be the one chosen by the linker.
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
unsigned getLocReg() const
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
ConstantExpr - a constant value that is initialized with an expression using other constant values...
void GetReturnInfo(Type *ReturnType, AttributeSet attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags...
const T & getValue() const LLVM_LVALUE_FUNCTION
Simple integer binary arithmetic operators.
BasicBlock * getSuccessor(unsigned i) const
Type * getElementType() const
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Flag
These should be considered private to the implementation of the MCInstrDesc class.
TargetInstrInfo - Interface to description of machine instruction set.
uint64_t getElementOffset(unsigned Idx) const
MVT - Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
This is an important class for using LLVM in a threaded context.
BranchInst - Conditional or Unconditional Branch instruction.
This is an important base class in LLVM.
PointerType * getType() const
getType - Overload to return most specific pointer type
bool isVector() const
isVector - Return true if this is a vector value type.
int64_t getSExtValue() const
Get sign extended value.
const MachineOperand & getOperand(unsigned i) const
IndirectBrInst - Indirect Branch Instruction.
APInt Or(const APInt &LHS, const APInt &RHS)
Bitwise OR function for APInt.
ConstantFP - Floating Point Values [float, double].
FCFID - The FCFID instruction, taking an f64 operand and producing and f64 value containing the FP re...
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Value * getOperand(unsigned i) const
0 1 1 1 True if ordered (no nans)
GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point load which sign-extends from a 32-bit inte...
Class to represent integer types.
bool isThreadLocal() const
If the value is "Thread Local", its value isn't shared by the threads.
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
1 1 1 1 Always true (always folded)
EVT - Extended Value Type.
static bool isAtomic(Instruction *I)
1 1 0 1 True if unordered, less than, or equal
0 0 1 0 True if ordered and greater than
CCState - This class holds information needed while lowering arguments and return values...
This is the shared class of boolean and integer constants.
bool isFunctionTy() const
isFunctionTy - True if this is an instance of FunctionType.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
1 1 0 0 True if unordered or less than
Type * getType() const
All values are typed, get the type of this value.
Provides information about what library functions are available for the current target.
CCValAssign - Represent assignment of one arg/retval to a location.
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Promote Memory to Register
unsigned fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill)
Emit a MachineInstr with two register operands and a result register in the given register class...
static ConstantInt * getSigned(IntegerType *Ty, int64_t V)
Return a ConstantInt with the specified value for the specified type.
bool isZero() const
This is just a convenience method to make client code smaller for a common code.
const MachineInstrBuilder & addFrameIndex(int Idx) const
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Target - Wrapper for Target specific information.
Class for arbitrary precision integers.
This file defines the FastISel class.
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned char TargetFlags=0) const
Representation of each machine instruction.
Predicate InvertPredicate(Predicate Opcode)
Invert the specified predicate. != -> ==, < -> >=.
PointerType * getType() const
Global values are always pointers.
Value * getCondition() const
static IntegerType * getInt32Ty(LLVMContext &C)
bool isDeclaration() const
Return true if the primary definition of this global value is outside of the current translation unit...
unsigned greater or equal
COPY_TO_REGCLASS - This instruction is a placeholder for a plain register-to-register copy into a spe...
const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned char TargetFlags=0) const
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
Fast - This calling convention attempts to make calls as fast as possible (e.g.
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
0 1 1 0 True if ordered and operands are unequal
iterator find(const KeyT &Val)
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool isInt< 16 >(int64_t x)
1 0 1 0 True if unordered or greater than
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
unsigned getReg() const
getReg - Returns the register number.
bool isSimple() const
isSimple - Test if the given EVT is simple (as opposed to being extended).
0 0 0 1 True if ordered and equal
LLVM Value Representation.
1 0 1 1 True if unordered, greater than, or equal
unsigned getOpcode() const
getOpcode() returns a member of one of the enums like Instruction::Add.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
bool isUInt< 16 >(uint64_t x)
Primary interface to the complete machine description for the target machine.
C - The default llvm calling convention, compatible with C.
FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 operand, producing an f64 value...
static Optional< PPC::Predicate > getComparePred(CmpInst::Predicate Pred)
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
int64_t getSExtValue() const
Return the constant as a 64-bit integer value after it has been sign extended as appropriate for the ...
0 0 1 1 True if ordered and greater than or equal
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point load which zero-extends from a 32-bit inte...
const BasicBlock * getParent() const
MVT getSimpleVT() const
getSimpleVT - Return the SimpleValueType held in the specified simple EVT.
0 0 0 0 Always false (always folded)
This file describes how to lower LLVM code to machine code.
bool isVoidTy() const
isVoidTy - Return true if this is 'void'.
AllocaInst - an instruction to allocate memory on the stack.
gep_type_iterator gep_type_begin(const User *GEP)