51 if (
getReg() == Reg)
return;
61 SmallContents.RegNo =
Reg;
67 SmallContents.RegNo =
Reg;
93 assert(
isReg() &&
"Wrong MachineOperand accessor");
94 assert((!Val || !
isDebug()) &&
"Marking a debug operation as def");
112 void MachineOperand::removeRegFromUses() {
113 if (!
isReg() || !isOnRegUseList())
119 MF->getRegInfo().removeRegOperandFromUseList(
this);
128 assert((!
isReg() || !
isTied()) &&
"Cannot change a tied operand into an imm");
137 assert((!
isReg() || !
isTied()) &&
"Cannot change a tied operand into an imm");
142 Contents.CFP = FPImm;
147 "Cannot change a tied operand into an external symbol");
152 Contents.OffsetedInfo.Val.SymbolName = SymName;
159 "Cannot change a tied operand into an MCSymbol");
171 bool isKill,
bool isDead,
bool isUndef,
177 RegInfo = &MF->getRegInfo();
180 bool WasReg =
isReg();
181 if (RegInfo && WasReg)
186 SmallContents.RegNo =
Reg;
187 SubReg_TargetFlags = 0;
193 IsInternalRead =
false;
194 IsEarlyClobber =
false;
197 Contents.Reg.Prev =
nullptr;
303 print(OS, DummyMST, TRI);
315 bool NeedComma =
false;
317 if (NeedComma) OS <<
',';
319 OS <<
"earlyclobber,";
334 if (NeedComma) OS <<
',';
339 if (NeedComma) OS <<
',';
344 if (NeedComma) OS <<
',';
349 if (NeedComma) OS <<
',';
354 if (NeedComma) OS <<
',';
362 case MachineOperand::MO_Immediate:
365 case MachineOperand::MO_CImmediate:
366 getCImm()->getValue().print(OS, false);
368 case MachineOperand::MO_FPImmediate:
369 if (getFPImm()->getType()->isFloatTy())
370 OS << getFPImm()->getValueAPF().convertToFloat();
372 OS << getFPImm()->getValueAPF().convertToDouble();
374 case MachineOperand::MO_MachineBasicBlock:
375 OS << "<BB#" << getMBB()->getNumber() << ">";
377 case MachineOperand::MO_FrameIndex:
378 OS << "<fi#" << getIndex() << '>
';
380 case MachineOperand::MO_ConstantPoolIndex:
381 OS << "<cp#" << getIndex();
382 if (getOffset()) OS << "+" << getOffset();
385 case MachineOperand::MO_TargetIndex:
386 OS << "<ti#" << getIndex();
387 if (getOffset()) OS << "+" << getOffset();
390 case MachineOperand::MO_JumpTableIndex:
391 OS << "<jt#" << getIndex() << '>
';
393 case MachineOperand::MO_GlobalAddress:
395 getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
396 if (getOffset()) OS << "+" << getOffset();
399 case MachineOperand::MO_ExternalSymbol:
400 OS << "<es:" << getSymbolName();
401 if (getOffset()) OS << "+" << getOffset();
404 case MachineOperand::MO_BlockAddress:
406 getBlockAddress()->printAsOperand(OS, /*PrintType=*/false, MST);
407 if (getOffset()) OS << "+" << getOffset();
410 case MachineOperand::MO_RegisterMask:
413 case MachineOperand::MO_RegisterLiveOut:
414 OS << "<regliveout>";
416 case MachineOperand::MO_Metadata:
418 getMetadata()->printAsOperand(OS, MST);
421 case MachineOperand::MO_MCSymbol:
422 OS << "<MCSym=" << *getMCSymbol() << '>
';
424 case MachineOperand::MO_CFIIndex:
425 OS << "<call frame instruction>";
429 if (unsigned TF = getTargetFlags())
430 OS << "[TF=" << TF << ']
';
433 //===----------------------------------------------------------------------===//
434 // MachineMemOperand Implementation
435 //===----------------------------------------------------------------------===//
439 unsigned MachinePointerInfo::getAddrSpace() const {
440 if (V.isNull() || V.is<const PseudoSourceValue*>()) return 0;
441 return cast<PointerType>(V.get<const Value*>()->getType())->getAddressSpace();
446 MachinePointerInfo MachinePointerInfo::getConstantPool() {
447 return MachinePointerInfo(PseudoSourceValue::getConstantPool());
452 MachinePointerInfo MachinePointerInfo::getFixedStack(int FI, int64_t offset) {
453 return MachinePointerInfo(PseudoSourceValue::getFixedStack(FI), offset);
456 MachinePointerInfo MachinePointerInfo::getJumpTable() {
457 return MachinePointerInfo(PseudoSourceValue::getJumpTable());
460 MachinePointerInfo MachinePointerInfo::getGOT() {
461 return MachinePointerInfo(PseudoSourceValue::getGOT());
464 MachinePointerInfo MachinePointerInfo::getStack(int64_t Offset) {
465 return MachinePointerInfo(PseudoSourceValue::getStack(), Offset);
468 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f,
469 uint64_t s, unsigned int a,
470 const AAMDNodes &AAInfo,
471 const MDNode *Ranges)
472 : PtrInfo(ptrinfo), Size(s),
473 Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)),
474 AAInfo(AAInfo), Ranges(Ranges) {
475 assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue*>() ||
476 isa<PointerType>(PtrInfo.V.get<const Value*>()->getType())) &&
477 "invalid pointer value");
478 assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
479 assert((isLoad() || isStore()) && "Not a load/store!");
484 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
485 ID.AddInteger(getOffset());
487 ID.AddPointer(getOpaqueValue());
488 ID.AddInteger(Flags);
491 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
492 // The Value and Offset may differ due to CSE. But the flags and size
493 // should be the same.
494 assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
495 assert(MMO->getSize() == getSize() && "Size mismatch!");
497 if (MMO->getBaseAlignment() >= getBaseAlignment()) {
498 // Update the alignment value.
499 Flags = (Flags & ((1 << MOMaxBits) - 1)) |
500 ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits);
501 // Also update the base and offset, because the new alignment may
502 // not be applicable with the old ones.
503 PtrInfo = MMO->PtrInfo;
509 uint64_t MachineMemOperand::getAlignment() const {
510 return MinAlign(getBaseAlignment(), getOffset());
513 void MachineMemOperand::print(raw_ostream &OS) const {
514 ModuleSlotTracker DummyMST(nullptr);
517 void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST) const {
518 assert((isLoad() || isStore()) &&
519 "SV has to be a load, store or both.");
530 // Print the address information.
532 if (const Value *V = getValue())
533 V->printAsOperand(OS, /*PrintType=*/false, MST);
534 else if (const PseudoSourceValue *PSV = getPseudoValue())
535 PSV->printCustom(OS);
539 unsigned AS = getAddrSpace();
541 OS << "(addrspace=" << AS << ')
';
543 // If the alignment of the memory reference itself differs from the alignment
544 // of the base pointer, print the base alignment explicitly, next to the base
546 if (getBaseAlignment() != getAlignment())
547 OS << "(align=" << getBaseAlignment() << ")";
549 if (getOffset() != 0)
550 OS << "+" << getOffset();
553 // Print the alignment of the reference.
554 if (getBaseAlignment() != getAlignment() || getBaseAlignment() != getSize())
555 OS << "(align=" << getAlignment() << ")";
558 if (const MDNode *TBAAInfo = getAAInfo().TBAA) {
560 if (TBAAInfo->getNumOperands() > 0)
561 TBAAInfo->getOperand(0)->printAsOperand(OS, MST);
567 // Print AA scope info.
568 if (const MDNode *ScopeInfo = getAAInfo().Scope) {
569 OS << "(alias.scope=";
570 if (ScopeInfo->getNumOperands() > 0)
571 for (unsigned i = 0, ie = ScopeInfo->getNumOperands(); i != ie; ++i) {
572 ScopeInfo->getOperand(i)->printAsOperand(OS, MST);
581 // Print AA noalias scope info.
582 if (const MDNode *NoAliasInfo = getAAInfo().NoAlias) {
584 if (NoAliasInfo->getNumOperands() > 0)
585 for (unsigned i = 0, ie = NoAliasInfo->getNumOperands(); i != ie; ++i) {
586 NoAliasInfo->getOperand(i)->printAsOperand(OS, MST);
595 // Print nontemporal info.
597 OS << "(nontemporal)";
603 //===----------------------------------------------------------------------===//
604 // MachineInstr Implementation
605 //===----------------------------------------------------------------------===//
607 void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) {
608 if (MCID->ImplicitDefs)
609 for (const uint16_t *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
610 addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
611 if (MCID->ImplicitUses)
612 for (const uint16_t *ImpUses = MCID->getImplicitUses(); *ImpUses; ++ImpUses)
613 addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
619 MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid,
620 DebugLoc dl, bool NoImp)
621 : MCID(&tid), Parent(nullptr), Operands(nullptr), NumOperands(0), Flags(0),
622 AsmPrinterFlags(0), NumMemRefs(0), MemRefs(nullptr),
623 debugLoc(std::move(dl)) {
624 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
626 // Reserve space for the expected number of operands.
627 if (unsigned NumOps = MCID->getNumOperands() +
628 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
629 CapOperands = OperandCapacity::get(NumOps);
630 Operands = MF.allocateOperandArray(CapOperands);
634 addImplicitDefUseOperands(MF);
639 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
640 : MCID(&MI.getDesc()), Parent(nullptr), Operands(nullptr), NumOperands(0),
641 Flags(0), AsmPrinterFlags(0),
642 NumMemRefs(MI.NumMemRefs), MemRefs(MI.MemRefs),
643 debugLoc(MI.getDebugLoc()) {
644 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
646 CapOperands = OperandCapacity::get(MI.getNumOperands());
647 Operands = MF.allocateOperandArray(CapOperands);
650 for (const MachineOperand &MO : MI.operands())
653 // Copy all the sensible flags.
660 MachineRegisterInfo *MachineInstr::getRegInfo() {
661 if (MachineBasicBlock *MBB = getParent())
662 return &MBB->getParent()->getRegInfo();
669 void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
670 for (MachineOperand &MO : operands())
672 MRI.removeRegOperandFromUseList(&MO);
678 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
679 for (MachineOperand &MO : operands())
681 MRI.addRegOperandToUseList(&MO);
684 void MachineInstr::addOperand(const MachineOperand &Op) {
685 MachineBasicBlock *MBB = getParent();
686 assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs");
687 MachineFunction *MF = MBB->getParent();
688 assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs");
694 static void moveOperands(MachineOperand *Dst, MachineOperand *Src,
695 unsigned NumOps, MachineRegisterInfo *MRI) {
697 return MRI->moveOperands(Dst, Src, NumOps);
699 // MachineOperand is a trivially copyable type so we can just use memmove.
700 std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));
707 void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) {
708 assert(MCID && "Cannot add operands before providing an instr descriptor");
710 // Check if we're adding one of our existing operands.
716 return addOperand(MF, CopyOp);
726 unsigned OpNo = getNumOperands();
727 bool isImpReg = Op.isReg() && Op.isImplicit();
728 if (!isImpReg && !isInlineAsm()) {
740 assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||
741 OpNo < MCID->getNumOperands() || isMetaDataOp) &&
742 "Trying to add an operand to a machine instr that is already done!");
749 OperandCapacity OldCap = CapOperands;
751 if (!OldOperands || OldCap.getSize() == getNumOperands()) {
752 CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
753 Operands = MF.allocateOperandArray(CapOperands);
760 if (OpNo != NumOperands)
766 if (OldOperands !=
Operands && OldOperands)
767 MF.deallocateOperandArray(OldCap, OldOperands);
771 NewMO->ParentMI =
this;
774 if (NewMO->
isReg()) {
776 NewMO->Contents.
Reg.Prev =
nullptr;
787 if (NewMO->
isUse()) {
788 int DefIdx = MCID->getOperandConstraint(OpNo,
MCOI::TIED_TO);
790 tieOperands(DefIdx, OpNo);
803 assert(OpNo < getNumOperands() &&
"Invalid operand number");
804 untieRegOperand(OpNo);
808 for (
unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
821 if (
unsigned N = NumOperands - 1 - OpNo)
832 unsigned OldNumMemRefs = NumMemRefs;
834 unsigned NewNum = NumMemRefs + 1;
837 std::copy(OldMemRefs, OldMemRefs + OldNumMemRefs, NewMemRefs);
838 NewMemRefs[NewNum - 1] = MO;
839 setMemRefs(NewMemRefs, NewMemRefs + NewNum);
842 bool MachineInstr::hasPropertyInBundle(
unsigned Mask, QueryType
Type)
const {
843 assert(!isBundledWithPred() &&
"Must be called on bundle header");
845 if (MII->getDesc().getFlags() & Mask) {
846 if (Type == AnyInBundle)
849 if (Type == AllInBundle && !MII->isBundle())
853 if (!MII->isBundledWithSucc())
854 return Type == AllInBundle;
872 while (++I1 != E1 && I1->isInsideBundle()) {
874 if (I2 == E2 || !I2->isInsideBundle() || !I1->isIdenticalTo(I2, Check))
880 for (
unsigned i = 0, e = getNumOperands(); i != e; ++i) {
893 if (Check == IgnoreDefs)
895 else if (Check == IgnoreVRegDefs) {
903 if (Check == CheckKillDead && MO.
isDead() != OMO.
isDead())
909 if (Check == CheckKillDead && MO.
isKill() != OMO.
isKill())
922 assert(
getParent() &&
"Not embedded in a basic block!");
927 assert(
getParent() &&
"Not embedded in a basic block!");
932 assert(
getParent() &&
"Not embedded in a basic block!");
937 assert(
getParent() &&
"Not embedded in a basic block!");
940 assert(MF &&
"Not embedded in a function!");
946 if (!MO.isReg() || !MO.isDef())
948 unsigned Reg = MO.getReg();
957 assert(
getParent() &&
"Not embedded in a basic block!");
964 unsigned NumOperands = MCID->getNumOperands();
965 if (!MCID->isVariadic())
968 for (
unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
977 assert(!isBundledWithPred() &&
"MI is already bundled with its predecessor");
978 setFlag(BundledPred);
981 assert(!Pred->isBundledWithSucc() &&
"Inconsistent bundle flags");
982 Pred->setFlag(BundledSucc);
986 assert(!isBundledWithSucc() &&
"MI is already bundled with its successor");
987 setFlag(BundledSucc);
990 assert(!Succ->isBundledWithPred() &&
"Inconsistent bundle flags");
991 Succ->setFlag(BundledPred);
995 assert(isBundledWithPred() &&
"MI isn't bundled with its predecessor");
996 clearFlag(BundledPred);
999 assert(Pred->isBundledWithSucc() &&
"Inconsistent bundle flags");
1000 Pred->clearFlag(BundledSucc);
1004 assert(isBundledWithSucc() &&
"MI isn't bundled with its successor");
1005 clearFlag(BundledSucc);
1008 assert(Succ->isBundledWithPred() &&
"Inconsistent bundle flags");
1009 Succ->clearFlag(BundledPred);
1013 if (isInlineAsm()) {
1022 assert(isInlineAsm() &&
"getInlineAsmDialect() only works for inline asms!");
1028 unsigned *GroupNo)
const {
1029 assert(isInlineAsm() &&
"Expected an inline asm instruction");
1030 assert(OpIdx < getNumOperands() &&
"OpIdx out of range");
1042 if (!FlagMO.
isImm())
1045 if (i + NumOps > OpIdx) {
1059 assert(
getParent() &&
"Can't have an MBB reference here!");
1067 if (!getOperand(OpIdx).
isReg())
1072 if (getOperand(OpIdx).
isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
1076 int FlagIdx = findInlineAsmFlagIdx(OpIdx);
1080 unsigned Flag = getOperand(FlagIdx).getImm();
1100 CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
1101 OpndIt.getOperandNo(),
Reg, CurRC,
TII, TRI);
1104 for (
unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)
1105 CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI);
1112 assert(CurRC &&
"Invalid initial register class");
1118 return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);
1126 assert(MO.
isReg() &&
1127 "Cannot get register constraints for non-register operand");
1128 assert(CurRC &&
"Invalid initial register class");
1144 while (I->isBundledWithSucc())
1154 for (
unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1158 unsigned MOReg = MO.
getReg();
1166 if (!isKill || MO.
isKill())
1175 std::pair<bool,bool>
1178 bool PartDef =
false;
1179 bool FullDef =
false;
1182 for (
unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1197 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
1208 for (
unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1216 unsigned MOReg = MO.
getReg();
1218 if (!Found && TRI && isPhys &&
1225 if (Found && (!isDead || MO.
isDead()))
1241 for (
unsigned i = 0, e = getNumOperands(); i != e; ++i)
1267 assert(DefMO.
isDef() &&
"DefIdx must be a def operand");
1268 assert(UseMO.
isUse() &&
"UseIdx must be a use operand");
1269 assert(!DefMO.
isTied() &&
"Def is already tied to another use");
1270 assert(!UseMO.
isTied() &&
"Use is already tied to another def");
1272 if (DefIdx < TiedMax)
1273 UseMO.TiedTo = DefIdx + 1;
1278 assert(isInlineAsm() &&
"DefIdx out of range");
1283 DefMO.TiedTo =
std::min(UseIdx + 1, TiedMax);
1291 assert(MO.
isTied() &&
"Operand isn't tied");
1294 if (MO.TiedTo < TiedMax)
1295 return MO.TiedTo - 1;
1298 if (!isInlineAsm()) {
1303 for (
unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
1305 if (UseMO.
isReg() && UseMO.
isUse() && UseMO.TiedTo == OpIdx + 1)
1314 unsigned OpIdxGroup = ~0u;
1319 assert(FlagMO.
isImm() &&
"Invalid tied operand on inline asm");
1320 unsigned CurGroup = GroupIdx.
size();
1324 if (OpIdx > i && OpIdx < i + NumOps)
1325 OpIdxGroup = CurGroup;
1331 unsigned Delta = i - GroupIdx[TiedGroup];
1334 if (OpIdxGroup == CurGroup)
1335 return OpIdx - Delta;
1338 if (OpIdxGroup == TiedGroup)
1339 return OpIdx + Delta;
1359 ToReg = RegInfo.
getSubReg(ToReg, SubIdx);
1383 if (mayStore() || isCall() ||
1384 (mayLoad() && hasOrderedMemoryRef())) {
1389 if (isPosition() || isDebugValue() || isTerminator() ||
1390 hasUnmodeledSideEffects())
1398 if (mayLoad() && !isInvariantLoad(AA))
1415 !hasUnmodeledSideEffects())
1420 if (memoperands_empty())
1424 for (
mmo_iterator I = memoperands_begin(), E = memoperands_end();
I != E; ++
I)
1425 if (!(*I)->isUnordered())
1443 if (memoperands_empty())
1449 E = memoperands_end();
I != E; ++
I) {
1450 if ((*I)->isVolatile())
return false;
1451 if ((*I)->isStore())
return false;
1452 if ((*I)->isInvariant())
return true;
1457 if (PSV->isConstant(MFI))
1460 if (
const Value *V = (*I)->getValue()) {
1482 assert(getNumOperands() >= 3 &&
1483 "It's illegal to have a PHI without source operands");
1485 unsigned Reg = getOperand(1).getReg();
1486 for (
unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1487 if (getOperand(i).
getReg() != Reg)
1495 if (isInlineAsm()) {
1529 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1530 dbgs() <<
" " << *
this;
1535 const Module *M =
nullptr;
1541 print(OS, MST, SkipOpers);
1545 bool SkipOpers)
const {
1564 unsigned StartOp = 0, e = getNumOperands();
1565 for (; StartOp < e && getOperand(StartOp).isReg() &&
1566 getOperand(StartOp).isDef() &&
1567 !getOperand(StartOp).isImplicit();
1569 if (StartOp != 0) OS <<
", ";
1570 getOperand(StartOp).print(OS, MST, TRI);
1571 unsigned Reg = getOperand(StartOp).getReg();
1581 OS << TII->
getName(getOpcode());
1589 bool OmittedAnyCallClobbers =
false;
1590 bool FirstOp =
true;
1591 unsigned AsmDescOp = ~0u;
1592 unsigned AsmOpCount = 0;
1602 OS <<
" [sideeffect]";
1606 OS <<
" [maystore]";
1608 OS <<
" [alignstack]";
1610 OS <<
" [attdialect]";
1612 OS <<
" [inteldialect]";
1619 for (
unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1629 if (MRI && isCall() &&
1631 unsigned Reg = MO.
getReg();
1634 bool HasAliasLive =
false;
1636 unsigned AliasReg = *AI;
1638 HasAliasLive =
true;
1642 if (!HasAliasLive) {
1643 OmittedAnyCallClobbers =
true;
1650 if (FirstOp) FirstOp =
false;
else OS <<
",";
1662 if (DIV && !DIV->getName().empty())
1663 OS <<
"!\"" << DIV->getName() <<
'\"';
1665 MO.
print(OS, MST, TRI);
1666 }
else if (TRI && (isInsertSubreg() || isRegSequence()) && MO.
isImm()) {
1668 }
else if (i == AsmDescOp && MO.
isImm()) {
1670 OS <<
'$' << AsmOpCount++;
1687 OS <<
":RC" << RCID;
1690 unsigned TiedTo = 0;
1692 OS <<
" tiedto:$" << TiedTo;
1699 MO.
print(OS, MST, TRI);
1703 if (OmittedAnyCallClobbers) {
1704 if (!FirstOp) OS <<
",";
1708 bool HaveSemi =
false;
1709 const unsigned PrintableFlags = FrameSetup;
1710 if (
Flags & PrintableFlags) {
1711 if (!HaveSemi) OS <<
";"; HaveSemi =
true;
1714 if (
Flags & FrameSetup)
1718 if (!memoperands_empty()) {
1719 if (!HaveSemi) OS <<
";"; HaveSemi =
true;
1722 for (
mmo_iterator i = memoperands_begin(), e = memoperands_end();
1724 (*i)->print(OS, MST);
1725 if (std::next(i) != e)
1731 if (MRI && !VirtRegs.
empty()) {
1732 if (!HaveSemi) OS <<
";"; HaveSemi =
true;
1733 for (
unsigned i = 0; i != VirtRegs.
size(); ++i) {
1736 <<
':' << PrintReg(VirtRegs[i]);
1737 for (
unsigned j = i+1; j != VirtRegs.
size();) {
1742 if (VirtRegs[i] != VirtRegs[j])
1743 OS <<
"," << PrintReg(VirtRegs[j]);
1750 if (isDebugValue() && getOperand(e - 2).isMetadata()) {
1751 if (!HaveSemi) OS <<
";";
1752 auto *DV = cast<DILocalVariable>(getOperand(e - 2).getMetadata());
1753 OS <<
" line no:" << DV->getLine();
1754 if (
auto *InlinedAt = debugLoc->getInlinedAt()) {
1756 if (InlinedAtDL && MF) {
1757 OS <<
" inlined @[ ";
1758 InlinedAtDL.
print(OS);
1762 if (isIndirectDebugValue())
1764 }
else if (debugLoc && MF) {
1765 if (!HaveSemi) OS <<
";";
1775 bool AddIfNotFound) {
1777 bool hasAliases = isPhysReg &&
1781 for (
unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1785 unsigned Reg = MO.
getReg();
1789 if (Reg == IncomingReg) {
1794 if (isPhysReg && isRegTiedToDefOperand(i))
1800 }
else if (hasAliases && MO.
isKill() &&
1811 while (!DeadOps.
empty()) {
1812 unsigned OpIdx = DeadOps.
back();
1814 RemoveOperand(OpIdx);
1816 getOperand(OpIdx).setIsKill(
false);
1822 if (!Found && AddIfNotFound) {
1839 unsigned OpReg = MO.
getReg();
1840 if (OpReg == Reg || (RegInfo && RegInfo->
isSuperRegister(Reg, OpReg)))
1847 bool AddIfNotFound) {
1849 bool hasAliases = isPhysReg &&
1853 for (
unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1857 unsigned MOReg = MO.
getReg();
1864 }
else if (hasAliases && MO.
isDead() &&
1875 while (!DeadOps.
empty()) {
1876 unsigned OpIdx = DeadOps.
back();
1878 RemoveOperand(OpIdx);
1880 getOperand(OpIdx).setIsDead(
false);
1886 if (Found || !AddIfNotFound)
1916 MachineOperand *MO = findRegisterDefOperand(Reg,
false, RegInfo);
1933 bool HasRegMask =
false;
1940 unsigned Reg = MO.
getReg();
1943 if (std::none_of(UsedRegs.
begin(), UsedRegs.
end(),
1953 addRegisterDefined(*
I, &TRI);
1974 unsigned LocCookie = 0;
1975 const MDNode *LocMD =
nullptr;
1976 for (
unsigned i = getNumOperands(); i != 0; --i) {
1981 mdconst::dyn_extract<ConstantInt>(LocMD->
getOperand(0))) {
1990 return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
void bundleWithPred()
Bundle this instruction with its predecessor.
void push_back(const T &Elt)
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
const GlobalValue * getGlobal() const
bool isPredicate() const
Set if this is one of the operands that made up of the predicate operand that controls an isPredicabl...
instr_iterator instr_end()
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
void setTargetFlags(unsigned F)
const ConstantFP * getFPImm() const
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
MachineBasicBlock * getMBB() const
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
A Module instance is used to store all the information related to an LLVM module. ...
bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
unsigned getNumOperands() const
Return number of MDNode operands.
void setIsDef(bool Val=true)
Change a def to a use, or a use to a def.
Describe properties that are true of each instruction in the target description file.
void setIsUndef(bool Val=true)
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
Address of indexed Jump Table for switch.
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
bool isBundle(MCInst const &MCI)
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
MachineBasicBlock reference.
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const
getCommonSubClass - find the largest common subclass of A and B.
const char * getSymbolName() const
void setIsDead(bool Val=true)
bool isSubRegister(unsigned RegA, unsigned RegB) const
Returns true if RegB is a sub-register of RegA.
union llvm::MachineOperand::@33::@35::@36 Val
Manage lifetime of a slot tracker for printing IR.
const MDNode * getMetadata() const
void reserve(size_type N)
Instructions::iterator instr_iterator
Mask of live-out registers.
iterator_range< mop_iterator > operands()
void substVirtReg(unsigned Reg, unsigned SubIdx, const TargetRegisterInfo &)
substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.
bool isMetadata() const
isMetadata - Tests if this is a MO_Metadata operand.
void markUsesInDebugValueAsUndef(unsigned Reg) const
markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the specified register as undefined wh...
void setPhysRegsDeadExcept(ArrayRef< unsigned > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx)
isUseOperandTiedToDef - Return true if the flag of the inline asm operand indicates it is an use oper...
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag=true)
Reports a serious error, calling any installed error handler.
virtual bool pointsToConstantMemory(const MemoryLocation &Loc, bool OrLocal=false)
pointsToConstantMemory - If the specified memory location is known to be constant, return true.
Mask of preserved registers.
const TargetRegisterClass * getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.
void ChangeToMCSymbol(MCSymbol *Sym)
ChangeToMCSymbol - Replace this operand with a new MC symbol operand.
void clearKillInfo()
Clears kill flags on all operands.
unsigned getBundleSize() const
Return the number of instructions inside the MI bundle, excluding the bundle header.
MachineMemOperand - A description of a memory reference used in the backend.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
const HexagonInstrInfo * TII
unsigned getCFIIndex() const
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false)
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const TargetRegisterClass * getRegClass(unsigned i) const
getRegClass - Returns the register class associated with the enumeration value.
A Use represents the edge between a Value definition and its users.
void ChangeToES(const char *SymName, unsigned char TargetFlags=0)
ChangeToES - Replace this operand with a new external symbol operand.
Target-dependent index+offset operand.
std::pair< bool, bool > readsWritesVirtualRegister(unsigned Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
const TargetRegisterClass * getRegClass(unsigned Reg) const
getRegClass - Return the register class of the specified virtual register.
Name of external global symbol.
void addRegisterDefReadUndef(unsigned Reg)
Mark all subregister defs of register Reg with the undef flag.
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
Number of individual test Apply this number of consecutive mutations to each input exit after the first new interesting input is found the minimized corpus is saved into the first input directory Number of jobs to run If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
void bundleWithSucc()
Bundle this instruction with its successor.
void print(raw_ostream &OS) const
prints source location /path/to/file.exe:line:col @[inlined at]
void eraseFromParentAndMarkDBGValuesForRemoval()
Unlink 'this' from the containing basic block and delete it.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
void setIsEarlyClobber(bool Val=true)
void unbundleFromPred()
Break bundle above this instruction.
PrintReg - Helper class for printing registers on a raw_ostream.
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Immediate >64bit operand.
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
getMatchingSuperRegClass - Return a subclass of the specified register class A so that each register ...
hash_code hash_value(const APFloat &Arg)
See friend declarations above.
const char * getRegClassName(const TargetRegisterClass *Class) const
getRegClassName - Returns the name of the register class.
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo)
Clear all kill flags affecting Reg.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
unsigned short NumOperands
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
Flag
These should be considered private to the implementation of the MCInstrDesc class.
const MachineBasicBlock * getParent() const
Function * getFunction(StringRef Name) const
Look up the specified function in the module symbol table.
TargetInstrInfo - Interface to description of machine instruction set.
bool isEarlyClobber() const
unsigned findTiedOperandIdx(unsigned OpIdx) const
Given the index of a tied register operand, find the operand it is tied to.
Address of a global value.
unsigned getTargetFlags() const
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr) const
bool regsOverlap(unsigned regA, unsigned regB) const
regsOverlap - Returns true if the two registers are equal or alias each other.
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
The instances of the Type class are immutable: once they are created, they are never changed...
void print(raw_ostream &OS, bool SkipOpers=false) const
bool isOptionalDef() const
Set if this operand is a optional def.
void clearRegisterDeads(unsigned Reg)
Clear all dead flags on operands defining register Reg.
const char * getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
int findRegisterDefOperandIdx(unsigned Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a def of the specified register or -1 if it is not found...
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const MachineOperand & getOperand(unsigned i) const
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
ConstantFP - Floating Point Values [float, double].
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag...
MCRegAliasIterator enumerates all registers aliasing Reg.
int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo=nullptr) const
Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instructio...
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
Address of a basic block.
void substPhysReg(unsigned Reg, const TargetRegisterInfo &)
substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore...
static unsigned getKind(unsigned Flags)
int64_t getOffset() const
Return the offset from the symbol in this operand.
bool isInvariantLoad(AliasAnalysis *AA) const
Return true if this instruction is loading from a location whose value is invariant across the functi...
void setOffset(int64_t Offset)
unsigned getSubReg() const
static unsigned getHashValue(const MachineInstr *const &MI)
iterator erase(iterator I)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
struct llvm::MachineOperand::@33::@34 Reg
void emitError(StringRef Msg) const
Emit an error referring to the source location of this instruction.
void eraseFromBundle()
Unlink 'this' form its basic block and delete it.
void setIsKill(bool Val=true)
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
Representation for a specific memory location.
int findRegisterUseOperandIdx(unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a use of the specific register or -1 if it is not found...
const MDOperand & getOperand(unsigned I) const
MachineInstr * removeFromBundle()
Unlink this instruction from its basic block and return it without deleting it.
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
This is the shared class of boolean and integer constants.
void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
bool isIdenticalTo(const MachineInstr *Other, MICheckType Check=CheckDefs) const
Return true if this instruction is identical to (same opcode and same operands as) the specified inst...
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
MachineOperand class - Representation of each machine instruction operand.
Module.h This file contains the declarations for the Module class.
void ChangeToFPImmediate(const ConstantFP *FPImm)
ChangeToFPImmediate - Replace this operand with a new FP immediate operand of the specified value...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
friend hash_code hash_value(const MachineOperand &MO)
MachineOperand hash_value overload.
MCSymbol reference (for debug/eh info)
void addRegisterDefined(unsigned Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
const ConstantInt * getCImm() const
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
hash_code hash_combine(const Ts &...args)
Combine values into a single hash_code.
PseudoSourceValue - Special value supplied for machine level alias analysis.
const char * getSubRegIndexName(unsigned SubIdx) const
getSubRegIndexName - Return the human-readable symbolic target-specific name for the specified SubReg...
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
hash_code hash_combine_range(InputIteratorT first, InputIteratorT last)
Compute a hash_code for a sequence of values.
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
An opaque object representing a hash code.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
static bool hasRegClassConstraint(unsigned Flag, unsigned &RC)
hasRegClassConstraint - Returns true if the flag contains a register class constraint.
bool isSuperRegister(unsigned RegA, unsigned RegB) const
Returns true if RegB is a super-register of RegA.
Representation of each machine instruction.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
static bool isPhysicalRegister(unsigned Reg)
isPhysicalRegister - Return true if the specified register number is in the physical register namespa...
void copyImplicitOps(MachineFunction &MF, const MachineInstr *MI)
Copy implicit register operands from specified instruction to this instruction.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps, MachineRegisterInfo *MRI)
Move NumOps MachineOperands from Src to Dst, with support for overlapping ranges. ...
std::error_code Check(std::error_code Err)
void setReg(unsigned Reg)
Change the register this operand corresponds to.
void setSubReg(unsigned subReg)
MCSymbol * getMCSymbol() const
MCInstrDesc const & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
Abstract Stack Frame Index.
const TargetRegisterClass * getRegClassConstraintEffectForVReg(unsigned Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ExploreBundle=false) const
Applies the constraints (def/use) implied by this MI on Reg to the given CurRC.
MachineInstr * removeFromParent()
Unlink 'this' from the containing basic block, and return it without deleting it. ...
unsigned getReg() const
getReg - Returns the register number.
bool isValid() const
isValid - Returns true until all the operands have been visited.
void unbundleFromSucc()
Break bundle below this instruction.
unsigned isConstantValuePHI() const
If the specified instruction is a PHI that always merges together the same virtual register...
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
getSubClassWithSubReg - Returns the largest legal sub-class of RC that supports the sub-register inde...
virtual const TargetInstrInfo * getInstrInfo() const
Module * getParent()
Get the module that this global value is contained inside of...
LLVM Value Representation.
Floating-point immediate operand.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
const MCOperandInfo * OpInfo
This class implements an extremely fast bulk output stream that can only output to a stream...
bool addRegisterKilled(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
StringRef - Represent a constant reference to a string, i.e.
const BlockAddress * getBlockAddress() const
unsigned composeSubRegIndices(unsigned a, unsigned b) const
composeSubRegIndices - Return the subregister index you get from composing two subregister indices...
const TargetRegisterClass * getRegClass(const MCInstrDesc &TID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum...
Address of indexed Constant in Constant Pool.
bool isStackAligningInlineAsm() const
bool isIdenticalTo(const MachineOperand &Other) const
isIdenticalTo - Return true if this operand is identical to the specified operand.
This holds information about one operand of a machine instruction, indicating the register class for ...
MachineInstr::mmo_iterator allocateMemRefsArray(unsigned long Num)
allocateMemRefsArray - Allocate an array to hold MachineMemOperand pointers.
virtual const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const
getPointerRegClass - Returns a TargetRegisterClass used for pointer values.
InlineAsm::AsmDialect getInlineAsmDialect() const
bool isInternalRead() const
bool use_empty(unsigned RegNo) const
use_empty - Return true if there are no instructions using the specified register.
Metadata reference (for debug info)
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.