31 #define DEBUG_TYPE "reg-scavenging"
36 RegUnitsAvailable.
reset(*RUI);
47 RegUnitsAvailable.
set();
70 assert((NumRegUnits == 0 || NumRegUnits == TRI->
getNumRegUnits()) &&
76 "Cannot use register scavenger with inaccurate liveness");
81 RegUnitsAvailable.
resize(NumRegUnits);
82 KillRegUnits.
resize(NumRegUnits);
83 DefRegUnits.
resize(NumRegUnits);
84 TmpRegUnits.
resize(NumRegUnits);
93 void RegScavenger::addRegUnits(
BitVector &BV,
unsigned Reg) {
98 void RegScavenger::determineKillsAndDefs() {
99 assert(Tracking &&
"Must be tracking to determine kills and defs");
102 assert(!MI->
isDebugValue() &&
"Debug values have no kills or defs");
106 KillRegUnits.
reset();
113 for (
unsigned RU = 0, RUEnd = TRI->
getNumRegUnits(); RU != RUEnd; ++RU) {
123 KillRegUnits |= TmpRegUnits;
127 unsigned Reg = MO.
getReg();
136 addRegUnits(KillRegUnits, Reg);
140 addRegUnits(KillRegUnits, Reg);
142 addRegUnits(DefRegUnits, Reg);
148 assert(Tracking &&
"Cannot unprocess because we're not tracking");
152 determineKillsAndDefs();
155 setUsed(KillRegUnits);
156 setUnused(DefRegUnits);
159 if (MBBI == MBB->
begin()) {
172 assert(MBBI != MBB->
end() &&
"Already past the end of the basic block!");
173 MBBI = std::next(MBBI);
175 assert(MBBI != MBB->
end() &&
"Already at the end of the basic block!");
181 if (
I->Restore != MI)
185 I->Restore =
nullptr;
188 if (MI->isDebugValue())
191 determineKillsAndDefs();
195 for (
unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
199 unsigned Reg = MO.
getReg();
214 bool SubUsed =
false;
220 bool SuperUsed =
false;
227 if (!SubUsed && !SuperUsed) {
239 assert((KillRegs.test(Reg) || isUnused(Reg) ||
240 isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &&
241 "Re-defining a live register!");
248 setUnused(KillRegUnits);
249 setUsed(DefRegUnits);
253 if (includeReserved && isReserved(Reg))
256 if (!RegUnitsAvailable.
test(*RUI))
294 assert(Survivor > 0 &&
"No candidates for scavenging");
297 assert(StartMI != ME &&
"MI already at terminator");
301 bool inVirtLiveRange =
false;
302 for (++MI; InstrLimit > 0 && MI != ME; ++
MI, --InstrLimit) {
303 if (MI->isDebugValue()) {
307 bool isVirtKillInsn =
false;
308 bool isVirtDefInsn =
false;
310 for (
unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
318 isVirtDefInsn =
true;
320 isVirtKillInsn =
true;
324 Candidates.
reset(*AI);
328 if (!inVirtLiveRange) RestorePointMI =
MI;
331 if (isVirtKillInsn) inVirtLiveRange =
false;
332 if (isVirtDefInsn) inVirtLiveRange =
true;
335 if (Candidates.
test(Survivor))
339 if (Candidates.
none())
345 if (MI == ME) RestorePointMI = ME;
346 assert (RestorePointMI != StartMI &&
347 "No available scavenger restore location!");
350 UseMI = RestorePointMI;
358 assert(i < MI->getNumOperands() &&
359 "Instr doesn't have FrameIndex operand!");
372 for (
unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
382 Available &= Candidates;
384 Candidates = Available;
388 unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI);
398 for (SI = 0; SI < Scavenged.
size(); ++
SI)
399 if (Scavenged[SI].Reg == 0)
402 if (SI == Scavenged.
size()) {
409 Scavenged[
SI].Reg = SReg;
416 "Cannot scavenge register without an emergency spill slot!");
427 II = std::prev(UseMI);
433 Scavenged[
SI].Restore = std::prev(UseMI);
438 DEBUG(
dbgs() <<
"Scavenged register (with spill): " << TRI->
getName(SReg) <<
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
void push_back(const T &Elt)
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
bool isValid() const
Check if the iterator is at the end of the list.
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
BitVector getPristineRegs(const MachineFunction &MF) const
Return a set of physical registers that are pristine.
virtual bool saveScavengerRegister(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, unsigned Reg) const
saveScavengerRegister - Spill the register so it can be used by the register scavenger.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
bool none() const
none - Returns true if none of the bits are set.
int find_next(unsigned Prev) const
find_next - Returns the index of the next set bit following the "Prev" bit.
std::vector< unsigned >::const_iterator livein_iterator
iterator getFirstTerminator()
getFirstTerminator - returns an iterator to the first terminator instruction of this basic block...
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
void verify(Pass *p=nullptr, const char *Banner=nullptr) const
verify - Run the current MachineFunction through the machine code verifier, useful for debugger use...
bool any() const
any - Returns true if any bit is set.
const MCPhysReg * iterator
livein_iterator livein_begin() const
void clear()
clear - Clear all bits.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MCSuperRegIterator enumerates all super-registers of Reg.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
iterator begin() const
begin/end - Return all of the registers in this class.
Reg
All possible values of the reg field in the ModR/M byte.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
void forward()
Move the internal MBB iterator and update register states.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
MCRegUnitRootIterator enumerates the root registers of a register unit.
BitVector getRegsAvailable(const TargetRegisterClass *RC)
Return all available registers in the register class in Mask.
virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const =0
eliminateFrameIndex - This method must be overriden to eliminate abstract frame indices from instruct...
void enterBasicBlock(MachineBasicBlock *mbb)
Start tracking liveness from the begin of the specific basic block.
BitVector getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const
getAllocatableSet - Returns a bitset indexed by register number indicating if a register is allocatab...
bool isDebugValue() const
bundle_iterator< MachineInstr, instr_iterator > iterator
void clearBitsNotInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
clearBitsNotInMask - Clear a bit in this vector for every '0' bit in Mask.
livein_iterator livein_end() const
const MachineOperand & getOperand(unsigned i) const
void unprocess()
Invert the behavior of forward() on the current instruction (undo the changes to the available regist...
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Load the specified register of the given register class from the specified stack frame index...
bool tracksLiveness() const
tracksLiveness - Returns true when tracking register liveness accurately.
MCRegAliasIterator enumerates all registers aliasing Reg.
static unsigned getFrameIndexOperandNum(MachineInstr *MI)
virtual void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Store the specified register of the given register class to the specified stack frame index...
MCSubRegIterator enumerates all sub-registers of Reg.
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
MachineOperand class - Representation of each machine instruction operand.
bool test(unsigned Idx) const
bool isRegUsed(unsigned Reg, bool includeReserved=true) const
Return if a specific register is currently used.
void setRegUsed(unsigned Reg)
Tell the scavenger a register is used.
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
unsigned getNumRegUnits() const
Return the number of (native) register units in the target.
Representation of each machine instruction.
unsigned FindUnusedReg(const TargetRegisterClass *RegClass) const
Find an unused register of the specified register class.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
unsigned getReg() const
getReg - Returns the register number.
virtual const TargetInstrInfo * getInstrInfo() const
void initRegState()
Allow resetting register state info for multiple passes over/within the same function.
const char * getName(unsigned RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
unsigned scavengeRegister(const TargetRegisterClass *RegClass, MachineBasicBlock::iterator I, int SPAdj)
Make a register of the specific register class available and do the appropriate bookkeeping.