LLVM  3.7.0
Functions | Variables
PPCISelLowering.cpp File Reference
#include "PPCISelLowering.h"
#include "MCTargetDesc/PPCPredicates.h"
#include "PPCCallingConv.h"
#include "PPCMachineFunctionInfo.h"
#include "PPCPerfectShuffle.h"
#include "PPCTargetMachine.h"
#include "PPCTargetObjectFile.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/ADT/Triple.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetOptions.h"
#include "PPCGenCallingConv.inc"
Include dependency graph for PPCISelLowering.cpp:

Go to the source code of this file.

Functions

static void getMaxByValAlign (Type *Ty, unsigned &MaxAlign, unsigned MaxMaxAlign)
 getMaxByValAlign - Helper for getByValTypeAlignment to determine the desired ByVal argument alignment. More...
 
static bool isFloatingPointZero (SDValue Op)
 isFloatingPointZero - Return true if this is 0.0 or -0.0. More...
 
static bool isConstantOrUndef (int Op, int Val)
 isConstantOrUndef - Op is either an undef node or a ConstantSDNode. More...
 
static bool isVMerge (ShuffleVectorSDNode *N, unsigned UnitSize, unsigned LHSStart, unsigned RHSStart)
 isVMerge - Common function, used to match vmrg* shuffles. More...
 
static bool isVMerge (ShuffleVectorSDNode *N, unsigned IndexOffset, unsigned RHSStartValue)
 Common function used to match vmrgew and vmrgow shuffles. More...
 
static bool isIntS16Immediate (SDNode *N, short &Imm)
 isIntS16Immediate - This method tests to see if the node is either a 32-bit or 64-bit immediate, and if the value can be accurately represented as a sign extension from a 16-bit value. More...
 
static bool isIntS16Immediate (SDValue Op, short &Imm)
 
static void fixupFuncForFI (SelectionDAG &DAG, int FrameIdx, EVT VT)
 
static bool GetLabelAccessInfo (const TargetMachine &TM, const PPCSubtarget &Subtarget, unsigned &HiOpFlags, unsigned &LoOpFlags, const GlobalValue *GV=nullptr)
 GetLabelAccessInfo - Return true if we should reference labels using a PICBase, set the HiOpFlags and LoOpFlags to the target MO flags. More...
 
static SDValue LowerLabelRef (SDValue HiPart, SDValue LoPart, bool isPIC, SelectionDAG &DAG)
 
static void setUsesTOCBasePtr (MachineFunction &MF)
 
static void setUsesTOCBasePtr (SelectionDAG &DAG)
 
static SDValue getTOCEntry (SelectionDAG &DAG, SDLoc dl, bool Is64Bit, SDValue GA)
 
static unsigned CalculateStackSlotSize (EVT ArgVT, ISD::ArgFlagsTy Flags, unsigned PtrByteSize)
 CalculateStackSlotSize - Calculates the size reserved for this argument on the stack. More...
 
static unsigned CalculateStackSlotAlignment (EVT ArgVT, EVT OrigVT, ISD::ArgFlagsTy Flags, unsigned PtrByteSize)
 CalculateStackSlotAlignment - Calculates the alignment of this argument on the stack. More...
 
static bool CalculateStackSlotUsed (EVT ArgVT, EVT OrigVT, ISD::ArgFlagsTy Flags, unsigned PtrByteSize, unsigned LinkageSize, unsigned ParamAreaSize, unsigned &ArgOffset, unsigned &AvailableFPRs, unsigned &AvailableVRs, bool HasQPX)
 CalculateStackSlotUsed - Return whether this argument will use its stack slot (instead of being passed in registers). More...
 
static unsigned EnsureStackAlignment (const PPCFrameLowering *Lowering, unsigned NumBytes)
 EnsureStackAlignment - Round stack frame size up from NumBytes to ensure minimum alignment required for target. More...
 
static int CalculateTailCallSPDiff (SelectionDAG &DAG, bool isTailCall, unsigned ParamSize)
 CalculateTailCallSPDiff - Get the amount the stack pointer has to be adjusted to accommodate the arguments for the tailcall. More...
 
static SDNodeisBLACompatibleAddress (SDValue Op, SelectionDAG &DAG)
 isCallCompatibleAddress - Return the immediate to use if the specified 32-bit value is representable in the immediate field of a BxA instruction. More...
 
static void StoreTailCallArgumentsToStackSlot (SelectionDAG &DAG, SDValue Chain, const SmallVectorImpl< TailCallArgumentInfo > &TailCallArgs, SmallVectorImpl< SDValue > &MemOpChains, SDLoc dl)
 StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot. More...
 
static SDValue EmitTailCallStoreFPAndRetAddr (SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue OldRetAddr, SDValue OldFP, int SPDiff, bool isPPC64, bool isDarwinABI, SDLoc dl)
 EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to the appropriate stack slot for the tail call optimized function call. More...
 
static void CalculateTailCallArgDest (SelectionDAG &DAG, MachineFunction &MF, bool isPPC64, SDValue Arg, int SPDiff, unsigned ArgOffset, SmallVectorImpl< TailCallArgumentInfo > &TailCallArguments)
 CalculateTailCallArgDest - Remember Argument for later processing. More...
 
static SDValue CreateCopyOfByValArgument (SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, SDLoc dl)
 CreateCopyOfByValArgument - Make a copy of an aggregate at address specified by "Src" to address "Dst" of size "Size". More...
 
static void LowerMemOpCallTo (SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue Arg, SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64, bool isTailCall, bool isVector, SmallVectorImpl< SDValue > &MemOpChains, SmallVectorImpl< TailCallArgumentInfo > &TailCallArguments, SDLoc dl)
 LowerMemOpCallTo - Store the argument to the stack or remember it in case of tail calls. More...
 
static void PrepareTailCall (SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain, SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes, SDValue LROp, SDValue FPOp, bool isDarwinABI, SmallVectorImpl< TailCallArgumentInfo > &TailCallArguments)
 
static bool isFunctionGlobalAddress (SDValue Callee)
 
static unsigned PrepareCall (SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag, SDValue &Chain, SDValue CallSeqStart, SDLoc dl, int SPDiff, bool isTailCall, bool IsPatchPoint, bool hasNest, SmallVectorImpl< std::pair< unsigned, SDValue > > &RegsToPass, SmallVectorImpl< SDValue > &Ops, std::vector< EVT > &NodeTys, ImmutableCallSite *CS, const PPCSubtarget &Subtarget)
 
static bool isLocalCall (const SDValue &Callee)
 
static SDValue BuildSplatI (int Val, unsigned SplatSize, EVT VT, SelectionDAG &DAG, SDLoc dl)
 BuildSplatI - Build a canonical splati of Val with an element size of SplatSize. More...
 
static SDValue BuildIntrinsicOp (unsigned IID, SDValue Op, SelectionDAG &DAG, SDLoc dl, EVT DestVT=MVT::Other)
 BuildIntrinsicOp - Return a unary operator intrinsic node with the specified intrinsic ID. More...
 
static SDValue BuildIntrinsicOp (unsigned IID, SDValue LHS, SDValue RHS, SelectionDAG &DAG, SDLoc dl, EVT DestVT=MVT::Other)
 BuildIntrinsicOp - Return a binary operator intrinsic node with the specified intrinsic ID. More...
 
static SDValue BuildIntrinsicOp (unsigned IID, SDValue Op0, SDValue Op1, SDValue Op2, SelectionDAG &DAG, SDLoc dl, EVT DestVT=MVT::Other)
 BuildIntrinsicOp - Return a ternary operator intrinsic node with the specified intrinsic ID. More...
 
static SDValue BuildVSLDOI (SDValue LHS, SDValue RHS, unsigned Amt, EVT VT, SelectionDAG &DAG, SDLoc dl)
 BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified amount. More...
 
static SDValue GeneratePerfectShuffle (unsigned PFEntry, SDValue LHS, SDValue RHS, SelectionDAG &DAG, SDLoc dl)
 GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit the specified operations to build the shuffle. More...
 
static bool getAltivecCompareInfo (SDValue Intrin, int &CompareOpc, bool &isDot, const PPCSubtarget &Subtarget)
 getAltivecCompareInfo - Given an intrinsic, return false if it is not an altivec comparison. More...
 
static InstructioncallIntrinsic (IRBuilder<> &Builder, Intrinsic::ID Id)
 
static std::string getRecipOp (const char *Base, EVT VT)
 
static bool isConsecutiveLSLoc (SDValue Loc, EVT VT, LSBaseSDNode *Base, unsigned Bytes, int Dist, SelectionDAG &DAG)
 
static bool isConsecutiveLS (SDNode *N, LSBaseSDNode *Base, unsigned Bytes, int Dist, SelectionDAG &DAG)
 
static bool findConsecutiveLoad (LoadSDNode *LD, SelectionDAG &DAG)
 

Variables

static cl::opt< boolDisablePPCFloatInVariadic ("disable-ppc-float-in-variadic", cl::desc("disable saving float registers for va_start on PPC"), cl::Hidden)
 
static cl::opt< boolDisablePPCPreinc ("disable-ppc-preinc", cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden)
 
static cl::opt< boolDisableILPPref ("disable-ppc-ilp-pref", cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden)
 
static cl::opt< boolDisablePPCUnaligned ("disable-ppc-unaligned", cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden)
 
cl::opt< boolANDIGlueBug
 
static const MCPhysReg FPR []
 FPR - The set of FP registers that should be allocated for arguments, on Darwin. More...
 
static const MCPhysReg QFPR []
 QFPR - The set of QPX registers that should be allocated for arguments. More...
 

Function Documentation

static SDValue BuildIntrinsicOp ( unsigned  IID,
SDValue  Op,
SelectionDAG DAG,
SDLoc  dl,
EVT  DestVT = MVT::Other 
)
static

BuildIntrinsicOp - Return a unary operator intrinsic node with the specified intrinsic ID.

Definition at line 6708 of file PPCISelLowering.cpp.

References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::ISD::INTRINSIC_WO_CHAIN, and llvm::MVT::Other.

Referenced by llvm::PPCTargetLowering::PerformDAGCombine().

static SDValue BuildIntrinsicOp ( unsigned  IID,
SDValue  LHS,
SDValue  RHS,
SelectionDAG DAG,
SDLoc  dl,
EVT  DestVT = MVT::Other 
)
static

BuildIntrinsicOp - Return a binary operator intrinsic node with the specified intrinsic ID.

Definition at line 6718 of file PPCISelLowering.cpp.

References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::ISD::INTRINSIC_WO_CHAIN, and llvm::MVT::Other.

static SDValue BuildIntrinsicOp ( unsigned  IID,
SDValue  Op0,
SDValue  Op1,
SDValue  Op2,
SelectionDAG DAG,
SDLoc  dl,
EVT  DestVT = MVT::Other 
)
static

BuildIntrinsicOp - Return a ternary operator intrinsic node with the specified intrinsic ID.

Definition at line 6728 of file PPCISelLowering.cpp.

References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::ISD::INTRINSIC_WO_CHAIN, and llvm::MVT::Other.

static SDValue BuildSplatI ( int  Val,
unsigned  SplatSize,
EVT  VT,
SelectionDAG DAG,
SDLoc  dl 
)
static
static SDValue BuildVSLDOI ( SDValue  LHS,
SDValue  RHS,
unsigned  Amt,
EVT  VT,
SelectionDAG DAG,
SDLoc  dl 
)
static

BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified amount.

The result has the specified value type.

Definition at line 6739 of file PPCISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getVectorShuffle(), and llvm::MVT::v16i8.

Referenced by GeneratePerfectShuffle().

static unsigned CalculateStackSlotAlignment ( EVT  ArgVT,
EVT  OrigVT,
ISD::ArgFlagsTy  Flags,
unsigned  PtrByteSize 
)
static
static unsigned CalculateStackSlotSize ( EVT  ArgVT,
ISD::ArgFlagsTy  Flags,
unsigned  PtrByteSize 
)
static

CalculateStackSlotSize - Calculates the size reserved for this argument on the stack.

Definition at line 2617 of file PPCISelLowering.cpp.

References llvm::ISD::ArgFlagsTy::getByValSize(), llvm::EVT::getStoreSize(), llvm::ISD::ArgFlagsTy::isByVal(), and llvm::ISD::ArgFlagsTy::isInConsecutiveRegs().

Referenced by CalculateStackSlotUsed().

static bool CalculateStackSlotUsed ( EVT  ArgVT,
EVT  OrigVT,
ISD::ArgFlagsTy  Flags,
unsigned  PtrByteSize,
unsigned  LinkageSize,
unsigned  ParamAreaSize,
unsigned ArgOffset,
unsigned AvailableFPRs,
unsigned AvailableVRs,
bool  HasQPX 
)
static

CalculateStackSlotUsed - Return whether this argument will use its stack slot (instead of being passed in registers).

ArgOffset, AvailableFPRs, and AvailableVRs must hold the current argument position, and will be updated to account for this argument.

Definition at line 2679 of file PPCISelLowering.cpp.

References Align(), CalculateStackSlotAlignment(), CalculateStackSlotSize(), llvm::MVT::f32, llvm::MVT::f64, llvm::ISD::ArgFlagsTy::isByVal(), llvm::ISD::ArgFlagsTy::isInConsecutiveRegsLast(), llvm::MVT::v16i8, llvm::MVT::v1i128, llvm::MVT::v2f64, llvm::MVT::v2i64, llvm::MVT::v4f32, llvm::MVT::v4f64, llvm::MVT::v4i1, llvm::MVT::v4i32, and llvm::MVT::v8i16.

static void CalculateTailCallArgDest ( SelectionDAG DAG,
MachineFunction MF,
bool  isPPC64,
SDValue  Arg,
int  SPDiff,
unsigned  ArgOffset,
SmallVectorImpl< TailCallArgumentInfo > &  TailCallArguments 
)
static
static int CalculateTailCallSPDiff ( SelectionDAG DAG,
bool  isTailCall,
unsigned  ParamSize 
)
static

CalculateTailCallSPDiff - Get the amount the stack pointer has to be adjusted to accommodate the arguments for the tailcall.

Definition at line 3802 of file PPCISelLowering.cpp.

References llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::PPCFunctionInfo::getMinReservedArea(), and llvm::PPCFunctionInfo::setTailCallSPDelta().

static Instruction* callIntrinsic ( IRBuilder<> &  Builder,
Intrinsic::ID  Id 
)
static
static SDValue CreateCopyOfByValArgument ( SDValue  Src,
SDValue  Dst,
SDValue  Chain,
ISD::ArgFlagsTy  Flags,
SelectionDAG DAG,
SDLoc  dl 
)
static

CreateCopyOfByValArgument - Make a copy of an aggregate at address specified by "Src" to address "Dst" of size "Size".

Alignment information is specified by the specific parameter attribute. The copy will be passed as a byval function parameter. Sometimes what we are copying is the end of a larger object, the part that does not fit in registers.

Definition at line 3997 of file PPCISelLowering.cpp.

References llvm::ISD::ArgFlagsTy::getByValAlign(), llvm::ISD::ArgFlagsTy::getByValSize(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMemcpy(), and llvm::MVT::i32.

static SDValue EmitTailCallStoreFPAndRetAddr ( SelectionDAG DAG,
MachineFunction MF,
SDValue  Chain,
SDValue  OldRetAddr,
SDValue  OldFP,
int  SPDiff,
bool  isPPC64,
bool  isDarwinABI,
SDLoc  dl 
)
static
static unsigned EnsureStackAlignment ( const PPCFrameLowering Lowering,
unsigned  NumBytes 
)
static

EnsureStackAlignment - Round stack frame size up from NumBytes to ensure minimum alignment required for target.

Definition at line 2734 of file PPCISelLowering.cpp.

References llvm::TargetFrameLowering::getStackAlignment().

static bool findConsecutiveLoad ( LoadSDNode LD,
SelectionDAG DAG 
)
static
static void fixupFuncForFI ( SelectionDAG DAG,
int  FrameIdx,
EVT  VT 
)
static
static SDValue GeneratePerfectShuffle ( unsigned  PFEntry,
SDValue  LHS,
SDValue  RHS,
SelectionDAG DAG,
SDLoc  dl 
)
static

GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit the specified operations to build the shuffle.

Definition at line 7042 of file PPCISelLowering.cpp.

References llvm::ISD::BITCAST, BuildVSLDOI(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVectorShuffle(), llvm_unreachable, PerfectShuffleTable, and llvm::MVT::v16i8.

static bool getAltivecCompareInfo ( SDValue  Intrin,
int CompareOpc,
bool isDot,
const PPCSubtarget Subtarget 
)
static

getAltivecCompareInfo - Given an intrinsic, return false if it is not an altivec comparison.

If it is, return true and fill in Opc/isDot with information about the intrinsic.

Definition at line 7306 of file PPCISelLowering.cpp.

References llvm::SDValue::getOperand(), and llvm::PPCSubtarget::hasP8Altivec().

Referenced by llvm::PPCTargetLowering::PerformDAGCombine().

static bool GetLabelAccessInfo ( const TargetMachine TM,
const PPCSubtarget Subtarget,
unsigned HiOpFlags,
unsigned LoOpFlags,
const GlobalValue GV = nullptr 
)
static

GetLabelAccessInfo - Return true if we should reference labels using a PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.

Definition at line 1934 of file PPCISelLowering.cpp.

References llvm::TargetMachine::getRelocationModel(), llvm::PPCSubtarget::hasLazyResolverStub(), llvm::PPCII::MO_HA, llvm::PPCII::MO_LO, llvm::PPCII::MO_NLP_FLAG, llvm::PPCII::MO_NLP_HIDDEN_FLAG, llvm::PPCII::MO_PIC_FLAG, and llvm::Reloc::PIC_.

static void getMaxByValAlign ( Type Ty,
unsigned MaxAlign,
unsigned  MaxMaxAlign 
)
static

getMaxByValAlign - Helper for getByValTypeAlignment to determine the desired ByVal argument alignment.

Definition at line 928 of file PPCISelLowering.cpp.

Referenced by llvm::PPCTargetLowering::getByValTypeAlignment().

static std::string getRecipOp ( const char *  Base,
EVT  VT 
)
static
static SDValue getTOCEntry ( SelectionDAG DAG,
SDLoc  dl,
bool  Is64Bit,
SDValue  GA 
)
static
static SDNode* isBLACompatibleAddress ( SDValue  Op,
SelectionDAG DAG 
)
static

isCallCompatibleAddress - Return the immediate to use if the specified 32-bit value is representable in the immediate field of a BxA instruction.

Definition at line 3858 of file PPCISelLowering.cpp.

References llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::SDValue::getNode(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getTargetLoweringInfo(), and llvm::ConstantSDNode::getZExtValue().

Referenced by PrepareCall().

static bool isConsecutiveLS ( SDNode N,
LSBaseSDNode Base,
unsigned  Bytes,
int  Dist,
SelectionDAG DAG 
)
static
static bool isConsecutiveLSLoc ( SDValue  Loc,
EVT  VT,
LSBaseSDNode Base,
unsigned  Bytes,
int  Dist,
SelectionDAG DAG 
)
static
static bool isConstantOrUndef ( int  Op,
int  Val 
)
static

isConstantOrUndef - Op is either an undef node or a ConstantSDNode.

Return true if Op is undef or if it matches the specified value.

Definition at line 1095 of file PPCISelLowering.cpp.

Referenced by llvm::PPC::isQVALIGNIShuffleMask(), isVMerge(), llvm::PPC::isVPKUDUMShuffleMask(), llvm::PPC::isVPKUHUMShuffleMask(), llvm::PPC::isVPKUWUMShuffleMask(), and llvm::PPC::isVSLDOIShuffleMask().

static bool isFloatingPointZero ( SDValue  Op)
static

isFloatingPointZero - Return true if this is 0.0 or -0.0.

Definition at line 1081 of file PPCISelLowering.cpp.

References llvm::HexagonISD::CP, llvm::SDValue::getNode(), llvm::SDValue::getOperand(), llvm::ISD::isEXTLoad(), and llvm::ISD::isNON_EXTLoad().

static bool isFunctionGlobalAddress ( SDValue  Callee)
static
static bool isIntS16Immediate ( SDNode N,
short &  Imm 
)
static

isIntS16Immediate - This method tests to see if the node is either a 32-bit or 64-bit immediate, and if the value can be accurately represented as a sign extension from a 16-bit value.

If so, this returns true and the immediate.

Definition at line 1616 of file PPCISelLowering.cpp.

References llvm::SDNode::getValueType(), llvm::MVT::i32, and N.

Referenced by isIntS16Immediate(), llvm::PPCTargetLowering::SelectAddressRegImm(), and llvm::PPCTargetLowering::SelectAddressRegReg().

static bool isIntS16Immediate ( SDValue  Op,
short &  Imm 
)
static

Definition at line 1626 of file PPCISelLowering.cpp.

References llvm::SDValue::getNode(), and isIntS16Immediate().

static bool isLocalCall ( const SDValue Callee)
static

Definition at line 4278 of file PPCISelLowering.cpp.

References G.

static bool isVMerge ( ShuffleVectorSDNode N,
unsigned  UnitSize,
unsigned  LHSStart,
unsigned  RHSStart 
)
static
static bool isVMerge ( ShuffleVectorSDNode N,
unsigned  IndexOffset,
unsigned  RHSStartValue 
)
static

Common function used to match vmrgew and vmrgow shuffles.

The indexOffset determines whether to look for even or odd words in the shuffle mask. This is based on the of the endianness of the target machine.

  • Little Endian:
    • Use offset of 0 to check for odd elements
    • Use offset of 4 to check for even elements
  • Big Endian:

The mask to the shuffle vector instruction specifies the indices of the elements from the two input vectors to place in the result. The elements are numbered in array-access order, starting with the first vector. These vectors are always of type v16i8, thus each vector will contain 16 elements of size

  1. More info on the shuffle vector can be found in the http://llvm.org/docs/LangRef.html#shufflevector-instruction Language Reference.

The RHSStartValue indicates whether the same input vectors are used (unary) or two different input vectors are used, based on the following:

  • If the instruction uses the same vector for both inputs, the range of the indices will be 0 to 15. In this case, the RHSStart value passed should be 0.
  • If the instruction has two different vectors then the range of the indices will be 0 to 31. In this case, the RHSStart value passed should be 16 (indices 0-15 specify elements in the first vector while indices 16 to 31 specify elements in the second vector).
Parameters
[in]NThe shuffle vector SD Node to analyze
[in]IndexOffsetSpecifies whether to look for even or odd elements
[in]RHSStartValueSpecifies the starting index for the righthand input vector to the shuffle_vector instruction
Returns
true iff this shuffle vector represents an even or odd word merge

Definition at line 1327 of file PPCISelLowering.cpp.

References llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDNode::getValueType(), isConstantOrUndef(), and llvm::MVT::v16i8.

static SDValue LowerLabelRef ( SDValue  HiPart,
SDValue  LoPart,
bool  isPIC,
SelectionDAG DAG 
)
static
static void LowerMemOpCallTo ( SelectionDAG DAG,
MachineFunction MF,
SDValue  Chain,
SDValue  Arg,
SDValue  PtrOff,
int  SPDiff,
unsigned  ArgOffset,
bool  isPPC64,
bool  isTailCall,
bool  isVector,
SmallVectorImpl< SDValue > &  MemOpChains,
SmallVectorImpl< TailCallArgumentInfo > &  TailCallArguments,
SDLoc  dl 
)
static
static unsigned PrepareCall ( SelectionDAG DAG,
SDValue Callee,
SDValue InFlag,
SDValue Chain,
SDValue  CallSeqStart,
SDLoc  dl,
int  SPDiff,
bool  isTailCall,
bool  IsPatchPoint,
bool  hasNest,
SmallVectorImpl< std::pair< unsigned, SDValue > > &  RegsToPass,
SmallVectorImpl< SDValue > &  Ops,
std::vector< EVT > &  NodeTys,
ImmutableCallSite CS,
const PPCSubtarget Subtarget 
)
static

Definition at line 4075 of file PPCISelLowering.cpp.

References llvm::ISD::ADD, llvm::PPCISD::BCTRL, llvm::PPCISD::CALL, G, llvm::CallSiteBase< FunTy, BBTy, ValTy, UserTy, InstrTy, CallTy, InvokeTy, IterTy >::getCalledValue(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getCopyToReg(), llvm::SelectionDAG::getDataLayout(), llvm::GlobalAddressSDNode::getGlobal(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getLoad(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumValues(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getRegister(), llvm::TargetMachine::getRelocationModel(), llvm::SelectionDAG::getTarget(), llvm::SelectionDAG::getTargetExternalSymbol(), llvm::SelectionDAG::getTargetGlobalAddress(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::PPCSubtarget::getTargetTriple(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::MVT::Glue, llvm::PPCSubtarget::hasInvariantFunctionDescriptors(), llvm::GlobalValue::hasLocalLinkage(), llvm::MVT::i64, isBLACompatibleAddress(), llvm::PPCSubtarget::isELFv2ABI(), isFunctionGlobalAddress(), llvm::Triple::isMacOSX(), llvm::Triple::isMacOSXVersionLT(), llvm::PPCSubtarget::isPPC64(), llvm::GlobalValue::isStrongDefinitionForLinker(), llvm::PPCSubtarget::isSVR4ABI(), llvm::PPCSubtarget::isTargetELF(), llvm::makeArrayRef(), llvm::PPCII::MO_PLT_OR_STUB, llvm::PPCISD::MTCTR, llvm::MVT::Other, llvm::Reloc::PIC_, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::SDValue::setNode(), setUsesTOCBasePtr(), and llvm::Reloc::Static.

static void PrepareTailCall ( SelectionDAG DAG,
SDValue InFlag,
SDValue Chain,
SDLoc  dl,
bool  isPPC64,
int  SPDiff,
unsigned  NumBytes,
SDValue  LROp,
SDValue  FPOp,
bool  isDarwinABI,
SmallVectorImpl< TailCallArgumentInfo > &  TailCallArguments 
)
static
static void setUsesTOCBasePtr ( MachineFunction MF)
static
static void setUsesTOCBasePtr ( SelectionDAG DAG)
static
static void StoreTailCallArgumentsToStackSlot ( SelectionDAG DAG,
SDValue  Chain,
const SmallVectorImpl< TailCallArgumentInfo > &  TailCallArgs,
SmallVectorImpl< SDValue > &  MemOpChains,
SDLoc  dl 
)
static

Variable Documentation

cl::opt<bool> ANDIGlueBug
cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref", cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden)
static
cl::opt<bool> DisablePPCFloatInVariadic("disable-ppc-float-in-variadic", cl::desc("disable saving float registers for va_start on PPC"), cl::Hidden)
static
cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc", cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden)
static
cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned", cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden)
static
const MCPhysReg FPR[]
static
Initial value:
= {PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5,
PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10,
PPC::F11, PPC::F12, PPC::F13}

FPR - The set of FP registers that should be allocated for arguments, on Darwin.

Definition at line 2606 of file PPCISelLowering.cpp.

Referenced by llvm::SystemZMachineFunctionInfo::setVarArgsFirstFPR().

const MCPhysReg QFPR[]
static
Initial value:
= {
PPC::QF1, PPC::QF2, PPC::QF3, PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7,
PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11, PPC::QF12, PPC::QF13}

QFPR - The set of QPX registers that should be allocated for arguments.

Definition at line 2611 of file PPCISelLowering.cpp.