LLVM  3.7.0
SystemZInstrInfo.h
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1 //===-- SystemZInstrInfo.h - SystemZ instruction information ----*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the SystemZ implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H
15 #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H
16 
17 #include "SystemZ.h"
18 #include "SystemZRegisterInfo.h"
20 
21 #define GET_INSTRINFO_HEADER
22 #include "SystemZGenInstrInfo.inc"
23 
24 namespace llvm {
25 
26 class SystemZTargetMachine;
27 
28 namespace SystemZII {
29 enum {
30  // See comments in SystemZInstrFormats.td.
31  SimpleBDXLoad = (1 << 0),
32  SimpleBDXStore = (1 << 1),
33  Has20BitOffset = (1 << 2),
34  HasIndex = (1 << 3),
35  Is128Bit = (1 << 4),
36  AccessSizeMask = (31 << 5),
38  CCValuesMask = (15 << 10),
40  CompareZeroCCMaskMask = (15 << 14),
42  CCMaskFirst = (1 << 18),
43  CCMaskLast = (1 << 19),
44  IsLogical = (1 << 20)
45 };
46 static inline unsigned getAccessSize(unsigned int Flags) {
47  return (Flags & AccessSizeMask) >> AccessSizeShift;
48 }
49 static inline unsigned getCCValues(unsigned int Flags) {
50  return (Flags & CCValuesMask) >> CCValuesShift;
51 }
52 static inline unsigned getCompareZeroCCMask(unsigned int Flags) {
54 }
55 
56 // SystemZ MachineOperand target flags.
57 enum {
58  // Masks out the bits for the access model.
59  MO_SYMBOL_MODIFIER = (3 << 0),
60 
61  // @GOT (aka @GOTENT)
62  MO_GOT = (1 << 0),
63 
64  // @INDNTPOFF
65  MO_INDNTPOFF = (2 << 0)
66 };
67 // Classifies a branch.
68 enum BranchType {
69  // An instruction that branches on the current value of CC.
71 
72  // An instruction that peforms a 32-bit signed comparison and branches
73  // on the result.
75 
76  // An instruction that peforms a 32-bit unsigned comparison and branches
77  // on the result.
79 
80  // An instruction that peforms a 64-bit signed comparison and branches
81  // on the result.
83 
84  // An instruction that peforms a 64-bit unsigned comparison and branches
85  // on the result.
87 
88  // An instruction that decrements a 32-bit register and branches if
89  // the result is nonzero.
91 
92  // An instruction that decrements a 64-bit register and branches if
93  // the result is nonzero.
95 };
96 // Information about a branch instruction.
97 struct Branch {
98  // The type of the branch.
100 
101  // CCMASK_<N> is set if CC might be equal to N.
102  unsigned CCValid;
103 
104  // CCMASK_<N> is set if the branch should be taken when CC == N.
105  unsigned CCMask;
106 
107  // The target of the branch.
109 
110  Branch(BranchType type, unsigned ccValid, unsigned ccMask,
111  const MachineOperand *target)
112  : Type(type), CCValid(ccValid), CCMask(ccMask), Target(target) {}
113 };
114 } // end namespace SystemZII
115 
116 class SystemZSubtarget;
118  const SystemZRegisterInfo RI;
119  SystemZSubtarget &STI;
120 
121  void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
122  void splitAdjDynAlloc(MachineBasicBlock::iterator MI) const;
123  void expandRIPseudo(MachineInstr *MI, unsigned LowOpcode,
124  unsigned HighOpcode, bool ConvertHigh) const;
125  void expandRIEPseudo(MachineInstr *MI, unsigned LowOpcode,
126  unsigned LowOpcodeK, unsigned HighOpcode) const;
127  void expandRXYPseudo(MachineInstr *MI, unsigned LowOpcode,
128  unsigned HighOpcode) const;
129  void expandZExtPseudo(MachineInstr *MI, unsigned LowOpcode,
130  unsigned Size) const;
131  void emitGRX32Move(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
132  DebugLoc DL, unsigned DestReg, unsigned SrcReg,
133  unsigned LowLowOpcode, unsigned Size, bool KillSrc) const;
134  virtual void anchor();
135 
136 public:
137  explicit SystemZInstrInfo(SystemZSubtarget &STI);
138 
139  // Override TargetInstrInfo.
140  unsigned isLoadFromStackSlot(const MachineInstr *MI,
141  int &FrameIndex) const override;
142  unsigned isStoreToStackSlot(const MachineInstr *MI,
143  int &FrameIndex) const override;
144  bool isStackSlotCopy(const MachineInstr *MI, int &DestFrameIndex,
145  int &SrcFrameIndex) const override;
146  bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
147  MachineBasicBlock *&FBB,
149  bool AllowModify) const override;
150  unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
151  unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
153  DebugLoc DL) const override;
154  bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
155  unsigned &SrcReg2, int &Mask, int &Value) const override;
156  bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
157  unsigned SrcReg2, int Mask, int Value,
158  const MachineRegisterInfo *MRI) const override;
159  bool isPredicable(MachineInstr *MI) const override;
160  bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
161  unsigned ExtraPredCycles,
162  const BranchProbability &Probability) const override;
163  bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
164  unsigned NumCyclesT, unsigned ExtraPredCyclesT,
165  MachineBasicBlock &FMBB,
166  unsigned NumCyclesF, unsigned ExtraPredCyclesF,
167  const BranchProbability &Probability) const override;
168  bool PredicateInstruction(MachineInstr *MI,
169  ArrayRef<MachineOperand> Pred) const override;
170  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
171  DebugLoc DL, unsigned DestReg, unsigned SrcReg,
172  bool KillSrc) const override;
173  void storeRegToStackSlot(MachineBasicBlock &MBB,
175  unsigned SrcReg, bool isKill, int FrameIndex,
176  const TargetRegisterClass *RC,
177  const TargetRegisterInfo *TRI) const override;
178  void loadRegFromStackSlot(MachineBasicBlock &MBB,
180  unsigned DestReg, int FrameIdx,
181  const TargetRegisterClass *RC,
182  const TargetRegisterInfo *TRI) const override;
183  MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
185  LiveVariables *LV) const override;
186  MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
187  ArrayRef<unsigned> Ops,
189  int FrameIndex) const override;
190  MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
191  ArrayRef<unsigned> Ops,
193  MachineInstr *LoadMI) const override;
194  bool expandPostRAPseudo(MachineBasicBlock::iterator MBBI) const override;
195  bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
196  override;
197 
198  // Return the SystemZRegisterInfo, which this class owns.
199  const SystemZRegisterInfo &getRegisterInfo() const { return RI; }
200 
201  // Return the size in bytes of MI.
202  uint64_t getInstSizeInBytes(const MachineInstr *MI) const;
203 
204  // Return true if MI is a conditional or unconditional branch.
205  // When returning true, set Cond to the mask of condition-code
206  // values on which the instruction will branch, and set Target
207  // to the operand that contains the branch target. This target
208  // can be a register or a basic block.
209  SystemZII::Branch getBranchInfo(const MachineInstr *MI) const;
210 
211  // Get the load and store opcodes for a given register class.
212  void getLoadStoreOpcodes(const TargetRegisterClass *RC,
213  unsigned &LoadOpcode, unsigned &StoreOpcode) const;
214 
215  // Opcode is the opcode of an instruction that has an address operand,
216  // and the caller wants to perform that instruction's operation on an
217  // address that has displacement Offset. Return the opcode of a suitable
218  // instruction (which might be Opcode itself) or 0 if no such instruction
219  // exists.
220  unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset) const;
221 
222  // If Opcode is a load instruction that has a LOAD AND TEST form,
223  // return the opcode for the testing form, otherwise return 0.
224  unsigned getLoadAndTest(unsigned Opcode) const;
225 
226  // Return true if ROTATE AND ... SELECTED BITS can be used to select bits
227  // Mask of the R2 operand, given that only the low BitSize bits of Mask are
228  // significant. Set Start and End to the I3 and I4 operands if so.
229  bool isRxSBGMask(uint64_t Mask, unsigned BitSize,
230  unsigned &Start, unsigned &End) const;
231 
232  // If Opcode is a COMPARE opcode for which an associated COMPARE AND
233  // BRANCH exists, return the opcode for the latter, otherwise return 0.
234  // MI, if nonnull, is the compare instruction.
235  unsigned getCompareAndBranch(unsigned Opcode,
236  const MachineInstr *MI = nullptr) const;
237 
238  // Emit code before MBBI in MI to move immediate value Value into
239  // physical register Reg.
240  void loadImmediate(MachineBasicBlock &MBB,
242  unsigned Reg, uint64_t Value) const;
243 };
244 } // end namespace llvm
245 
246 #endif
A debug info location.
Definition: DebugLoc.h:34
const SystemZRegisterInfo & getRegisterInfo() const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APInt.h:33
Reg
All possible values of the reg field in the ModR/M byte.
Branch(BranchType type, unsigned ccValid, unsigned ccMask, const MachineOperand *target)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: ArrayRef.h:31
const MachineOperand * Target
bundle_iterator< MachineInstr, instr_iterator > iterator
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
static unsigned getAccessSize(unsigned int Flags)
bundle_iterator - MachineBasicBlock iterator that automatically skips over MIs that are inside bundle...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static unsigned getCompareZeroCCMask(unsigned int Flags)
MachineOperand class - Representation of each machine instruction operand.
Target - Wrapper for Target specific information.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:51
static unsigned getCCValues(unsigned int Flags)
LLVM Value Representation.
Definition: Value.h:69
BasicBlockListType::iterator iterator