28 #define DEBUG_TYPE "t2-reduce-size"
30 STATISTIC(NumNarrows,
"Number of 32-bit instrs reduced to 16-bit ones");
31 STATISTIC(Num2Addrs,
"Number of 32-bit instrs reduced to 2addr 16-bit ones");
32 STATISTIC(NumLdSts,
"Number of 32-bit load / store reduced to 16-bit ones");
50 unsigned LowRegs1 : 1;
51 unsigned LowRegs2 : 1;
56 unsigned PartFlag : 1;
58 unsigned AvoidMovs: 1;
61 static const ReduceEntry ReduceTable[] = {
63 { ARM::t2ADCrr, 0, ARM::tADC, 0, 0, 0, 1, 0,0, 0,0,0 },
64 { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0,1,0 },
65 { ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0,0,0 },
66 { ARM::t2ADDSri,ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 2,2, 0,1,0 },
67 { ARM::t2ADDSrr,ARM::tADDrr, 0, 0, 0, 1, 0, 2,0, 0,1,0 },
68 { ARM::t2ANDrr, 0, ARM::tAND, 0, 0, 0, 1, 0,0, 1,0,0 },
69 { ARM::t2ASRri, ARM::tASRri, 0, 5, 0, 1, 0, 0,0, 1,0,1 },
70 { ARM::t2ASRrr, 0, ARM::tASRrr, 0, 0, 0, 1, 0,0, 1,0,1 },
71 { ARM::t2BICrr, 0, ARM::tBIC, 0, 0, 0, 1, 0,0, 1,0,0 },
74 { ARM::t2CMNzrr, ARM::tCMNz, 0, 0, 0, 1, 0, 2,0, 0,0,0 },
75 { ARM::t2CMPri, ARM::tCMPi8, 0, 8, 0, 1, 0, 2,0, 0,0,0 },
76 { ARM::t2CMPrr, ARM::tCMPhir, 0, 0, 0, 0, 0, 2,0, 0,1,0 },
77 { ARM::t2EORrr, 0, ARM::tEOR, 0, 0, 0, 1, 0,0, 1,0,0 },
80 { ARM::t2LSLri, ARM::tLSLri, 0, 5, 0, 1, 0, 0,0, 1,0,1 },
81 { ARM::t2LSLrr, 0, ARM::tLSLrr, 0, 0, 0, 1, 0,0, 1,0,1 },
82 { ARM::t2LSRri, ARM::tLSRri, 0, 5, 0, 1, 0, 0,0, 1,0,1 },
83 { ARM::t2LSRrr, 0, ARM::tLSRrr, 0, 0, 0, 1, 0,0, 1,0,1 },
84 { ARM::t2MOVi, ARM::tMOVi8, 0, 8, 0, 1, 0, 0,0, 1,0,0 },
85 { ARM::t2MOVi16,ARM::tMOVi8, 0, 8, 0, 1, 0, 0,0, 1,1,0 },
87 { ARM::t2MOVr,ARM::tMOVr, 0, 0, 0, 0, 0, 1,0, 0,0,0 },
88 { ARM::t2MUL, 0, ARM::tMUL, 0, 0, 0, 1, 0,0, 1,0,0 },
89 { ARM::t2MVNr, ARM::tMVN, 0, 0, 0, 1, 0, 0,0, 0,0,0 },
90 { ARM::t2ORRrr, 0, ARM::tORR, 0, 0, 0, 1, 0,0, 1,0,0 },
91 { ARM::t2REV, ARM::tREV, 0, 0, 0, 1, 0, 1,0, 0,0,0 },
92 { ARM::t2REV16, ARM::tREV16, 0, 0, 0, 1, 0, 1,0, 0,0,0 },
93 { ARM::t2REVSH, ARM::tREVSH, 0, 0, 0, 1, 0, 1,0, 0,0,0 },
94 { ARM::t2RORrr, 0, ARM::tROR, 0, 0, 0, 1, 0,0, 1,0,0 },
95 { ARM::t2RSBri, ARM::tRSB, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
96 { ARM::t2RSBSri,ARM::tRSB, 0, 0, 0, 1, 0, 2,0, 0,1,0 },
97 { ARM::t2SBCrr, 0, ARM::tSBC, 0, 0, 0, 1, 0,0, 0,0,0 },
98 { ARM::t2SUBri, ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 0,0, 0,0,0 },
99 { ARM::t2SUBrr, ARM::tSUBrr, 0, 0, 0, 1, 0, 0,0, 0,0,0 },
100 { ARM::t2SUBSri,ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 2,2, 0,0,0 },
101 { ARM::t2SUBSrr,ARM::tSUBrr, 0, 0, 0, 1, 0, 2,0, 0,0,0 },
102 { ARM::t2SXTB, ARM::tSXTB, 0, 0, 0, 1, 0, 1,0, 0,1,0 },
103 { ARM::t2SXTH, ARM::tSXTH, 0, 0, 0, 1, 0, 1,0, 0,1,0 },
104 { ARM::t2TSTrr, ARM::tTST, 0, 0, 0, 1, 0, 2,0, 0,0,0 },
105 { ARM::t2UXTB, ARM::tUXTB, 0, 0, 0, 1, 0, 1,0, 0,1,0 },
106 { ARM::t2UXTH, ARM::tUXTH, 0, 0, 0, 1, 0, 1,0, 0,1,0 },
110 { ARM::t2LDRi12,ARM::tLDRi, ARM::tLDRspi, 5, 8, 1, 0, 0,0, 0,1,0 },
111 { ARM::t2LDRs, ARM::tLDRr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
112 { ARM::t2LDRBi12,ARM::tLDRBi, 0, 5, 0, 1, 0, 0,0, 0,1,0 },
113 { ARM::t2LDRBs, ARM::tLDRBr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
114 { ARM::t2LDRHi12,ARM::tLDRHi, 0, 5, 0, 1, 0, 0,0, 0,1,0 },
115 { ARM::t2LDRHs, ARM::tLDRHr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
116 { ARM::t2LDRSBs,ARM::tLDRSB, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
117 { ARM::t2LDRSHs,ARM::tLDRSH, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
118 { ARM::t2STRi12,ARM::tSTRi, ARM::tSTRspi, 5, 8, 1, 0, 0,0, 0,1,0 },
119 { ARM::t2STRs, ARM::tSTRr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
120 { ARM::t2STRBi12,ARM::tSTRBi, 0, 5, 0, 1, 0, 0,0, 0,1,0 },
121 { ARM::t2STRBs, ARM::tSTRBr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
122 { ARM::t2STRHi12,ARM::tSTRHi, 0, 5, 0, 1, 0, 0,0, 0,1,0 },
123 { ARM::t2STRHs, ARM::tSTRHr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
125 { ARM::t2LDMIA, ARM::tLDMIA, 0, 0, 0, 1, 1, 1,1, 0,1,0 },
126 { ARM::t2LDMIA_RET,0, ARM::tPOP_RET, 0, 0, 1, 1, 1,1, 0,1,0 },
127 { ARM::t2LDMIA_UPD,ARM::tLDMIA_UPD,ARM::tPOP,0, 0, 1, 1, 1,1, 0,1,0 },
129 { ARM::t2STMIA_UPD,ARM::tSTMIA_UPD, 0, 0, 0, 1, 1, 1,1, 0,1,0 },
130 { ARM::t2STMDB_UPD, 0, ARM::tPUSH, 0, 0, 1, 1, 1,1, 0,1,0 }
143 const char *getPassName()
const override {
144 return "Thumb2 instruction size reduction pass";
155 bool LiveCPSR,
bool &HasCC,
bool &CCDead);
158 const ReduceEntry &Entry);
161 const ReduceEntry &Entry,
bool LiveCPSR,
bool IsSelfLoop);
166 const ReduceEntry &Entry,
bool LiveCPSR,
172 const ReduceEntry &Entry,
bool LiveCPSR,
177 bool LiveCPSR,
bool IsSelfLoop);
189 bool HighLatencyCPSR;
193 bool HighLatencyCPSR;
197 MBBInfo() : HighLatencyCPSR(
false), Visited(
false) {}
202 std::function<bool(const Function &)> PredicateFtor;
209 OptimizeSize = MinimizeSize =
false;
210 for (
unsigned i = 0, e =
array_lengthof(ReduceTable); i != e; ++i) {
211 unsigned FromOpc = ReduceTable[i].WideOpc;
212 if (!ReduceOpcodeMap.insert(std::make_pair(FromOpc, i)).second)
213 assert(
false &&
"Duplicated entries?");
219 if (*Regs == ARM::CPSR)
252 Thumb2SizeReduce::canAddPseudoFlagDep(
MachineInstr *
Use,
bool FirstInSelfLoop) {
254 if (MinimizeSize || !STI->avoidCPSRPartialUpdate())
260 return HighLatencyCPSR || FirstInSelfLoop;
264 if (!MO.isReg() || MO.isUndef() || MO.isUse())
266 unsigned Reg = MO.getReg();
267 if (Reg == 0 || Reg == ARM::CPSR)
273 if (!MO.isReg() || MO.isUndef() || MO.isDef())
275 unsigned Reg = MO.getReg();
295 Thumb2SizeReduce::VerifyPredAndCC(
MachineInstr *
MI,
const ReduceEntry &Entry,
297 bool LiveCPSR,
bool &HasCC,
bool &CCDead) {
298 if ((is2Addr && Entry.PredCC2 == 0) ||
299 (!is2Addr && Entry.PredCC1 == 0)) {
318 }
else if ((is2Addr && Entry.PredCC2 == 2) ||
319 (!is2Addr && Entry.PredCC1 == 2)) {
339 bool isPCOk = (Opc == ARM::t2LDMIA_RET || Opc == ARM::t2LDMIA_UPD);
340 bool isLROk = (Opc == ARM::t2STMDB_UPD);
341 bool isSPOk = isPCOk || isLROk;
346 unsigned Reg = MO.
getReg();
347 if (Reg == 0 || Reg == ARM::CPSR)
349 if (isPCOk && Reg == ARM::PC)
351 if (isLROk && Reg == ARM::LR)
353 if (Reg == ARM::SP) {
356 if (i == 1 && (Opc == ARM::t2LDRi12 || Opc == ARM::t2STRi12))
368 const ReduceEntry &Entry) {
373 bool HasImmOffset =
false;
374 bool HasShift =
false;
375 bool HasOffReg =
true;
376 bool isLdStMul =
false;
377 unsigned Opc = Entry.NarrowOpc1;
379 uint8_t ImmLimit = Entry.Imm1Limit;
381 switch (Entry.WideOpc) {
387 Opc = Entry.NarrowOpc2;
388 ImmLimit = Entry.Imm2Limit;
438 case ARM::t2LDMIA_RET: {
440 if (BaseReg != ARM::SP)
442 Opc = Entry.NarrowOpc2;
447 case ARM::t2LDMIA_UPD:
448 case ARM::t2STMIA_UPD:
449 case ARM::t2STMDB_UPD: {
453 if (BaseReg == ARM::SP &&
454 (Entry.WideOpc == ARM::t2LDMIA_UPD ||
455 Entry.WideOpc == ARM::t2STMDB_UPD)) {
456 Opc = Entry.NarrowOpc2;
459 (Entry.WideOpc != ARM::t2LDMIA_UPD &&
460 Entry.WideOpc != ARM::t2STMIA_UPD)) {
469 unsigned OffsetReg = 0;
470 bool OffsetKill =
false;
471 bool OffsetInternal =
false;
482 unsigned OffsetImm = 0;
485 unsigned MaxOffset = ((1 << ImmLimit) - 1) * Scale;
487 if ((OffsetImm & (Scale - 1)) || OffsetImm > MaxOffset)
500 MIB.
addImm(OffsetImm / Scale);
502 assert((!HasShift || OffsetReg) &&
"Invalid so_reg load / store address!");
519 DEBUG(
errs() <<
"Converted 32-bit: " << *MI <<
" to 16-bit: " << *MIB);
528 const ReduceEntry &Entry,
529 bool LiveCPSR,
bool IsSelfLoop) {
531 if (Opc == ARM::t2ADDri) {
535 if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, IsSelfLoop))
537 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
544 if (Imm & 3 || Imm > 1020)
556 TII->get(ARM::tADDrSPi))
565 DEBUG(
errs() <<
"Converted 32-bit: " << *MI <<
" to 16-bit: " <<*MIB);
576 return ReduceLoadStore(MBB, MI, Entry);
581 case ARM::t2ADDSrr: {
582 unsigned PredReg = 0;
586 case ARM::t2ADDSri: {
587 if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, IsSelfLoop))
592 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
604 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
610 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
618 static const ReduceEntry NarrowEntry =
619 { ARM::t2CMPrr,ARM::tCMPr, 0, 0, 0, 1, 1,2, 0, 0,1,0 };
620 if (ReduceToNarrow(MBB, MI, NarrowEntry, LiveCPSR, IsSelfLoop))
622 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
630 const ReduceEntry &Entry,
631 bool LiveCPSR,
bool IsSelfLoop) {
636 if (!MinimizeSize && !OptimizeSize && Entry.AvoidMovs &&
637 STI->avoidMOVsShifterOperand())
661 }
else if (Reg0 != Reg1) {
663 unsigned CommOpIdx1, CommOpIdx2;
664 if (!
TII->findCommutedOpIndices(MI, CommOpIdx1, CommOpIdx2) ||
673 if (Entry.Imm2Limit) {
675 unsigned Limit = (1 << Entry.Imm2Limit) - 1;
686 unsigned PredReg = 0;
688 bool SkipPred =
false;
706 if (!VerifyPredAndCC(MI, Entry,
true, Pred, LiveCPSR, HasCC, CCDead))
712 canAddPseudoFlagDep(MI, IsSelfLoop))
739 DEBUG(
errs() <<
"Converted 32-bit: " << *MI <<
" to 16-bit: " << *MIB);
748 const ReduceEntry &Entry,
749 bool LiveCPSR,
bool IsSelfLoop) {
753 if (!MinimizeSize && !OptimizeSize && Entry.AvoidMovs &&
754 STI->avoidMOVsShifterOperand())
759 unsigned Limit = ~0U;
761 Limit = (1 << Entry.Imm1Limit) - 1;
769 unsigned Reg = MO.
getReg();
770 if (!Reg || Reg == ARM::CPSR)
774 }
else if (MO.
isImm() &&
776 if (((
unsigned)MO.
getImm()) > Limit)
783 unsigned PredReg = 0;
785 bool SkipPred =
false;
802 if (!VerifyPredAndCC(MI, Entry,
false, Pred, LiveCPSR, HasCC, CCDead))
808 canAddPseudoFlagDep(MI, IsSelfLoop))
827 if ((MCID.
getOpcode() == ARM::t2RSBSri ||
832 MCID.
getOpcode() == ARM::t2UXTH) && i == 2)
836 if (SkipPred && isPred)
851 DEBUG(
errs() <<
"Converted 32-bit: " << *MI <<
" to 16-bit: " << *MIB);
863 if (MO.
getReg() != ARM::CPSR)
871 return HasDef || LiveCPSR;
878 if (MO.
getReg() != ARM::CPSR)
880 assert(LiveCPSR &&
"CPSR liveness tracking is wrong!");
891 bool LiveCPSR,
bool IsSelfLoop) {
894 if (OPI == ReduceOpcodeMap.
end())
896 const ReduceEntry &Entry = ReduceTable[OPI->second];
900 return ReduceSpecial(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
903 if (Entry.NarrowOpc2 &&
904 ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, IsSelfLoop))
908 if (Entry.NarrowOpc1 &&
909 ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop))
916 bool Modified =
false;
919 bool LiveCPSR = MBB.
isLiveIn(ARM::CPSR);
923 HighLatencyCPSR =
false;
927 const MBBInfo &PInfo = BlockInfo[Pred->getNumber()];
928 if (!PInfo.Visited) {
932 if (PInfo.HighLatencyCPSR) {
933 HighLatencyCPSR =
true;
943 for (; MII != E; MII = NextMII) {
944 NextMII = std::next(MII);
957 bool NextInSameBundle = NextMII != E && NextMII->isBundledWithPred();
959 if (ReduceMI(MBB, MI, LiveCPSR, IsSelfLoop)) {
965 if (NextInSameBundle && !NextMII->isBundledWithPred())
966 NextMII->bundleWithPred();
984 bool DefCPSR =
false;
989 HighLatencyCPSR =
false;
991 }
else if (DefCPSR) {
999 MBBInfo &Info = BlockInfo[MBB.
getNumber()];
1000 Info.HighLatencyCPSR = HighLatencyCPSR;
1001 Info.Visited =
true;
1006 if (PredicateFtor && !PredicateFtor(*MF.
getFunction()))
1010 if (STI->isThumb1Only() || STI->prefers32BitThumb())
1025 bool Modified =
false;
1027 I = RPOT.begin(), E = RPOT.end(); I != E; ++
I)
1028 Modified |= ReduceMBB(**I);
1036 return new Thumb2SizeReduce(Ftor);
static bool VerifyLowRegs(MachineInstr *MI)
bool isInsideBundle() const
Return true if MI is in a bundle (but not the first MI in a bundle).
const uint16_t * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
instr_iterator instr_begin()
bool isPredicate() const
Set if this is one of the operands that made up of the predicate operand that controls an isPredicabl...
instr_iterator instr_end()
STATISTIC(NumFunctions,"Total number of functions")
MachineOperand * findRegisterDefOperand(unsigned Reg, bool isDead=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
int getNumber() const
getNumber - MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a M...
bool hasOptionalDef() const
Set if this instruction has an optional definition, e.g.
Describe properties that are true of each instruction in the target description file.
MachineOperand * findRegisterUseOperand(unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterUseOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
unsigned getInternalReadRegState(bool B)
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
static cl::opt< int > ReduceLimit2Addr("t2-reduce-limit2", cl::init(-1), cl::Hidden)
Instructions::iterator instr_iterator
iterator_range< mop_iterator > operands()
static const MachineInstrBuilder & AddNoT1CC(const MachineInstrBuilder &MIB)
static const MachineInstrBuilder & AddDefaultPred(const MachineInstrBuilder &MIB)
unsigned getNumBlockIDs() const
getNumBlockIDs - Return the number of MBB ID's allocated.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
A Use represents the edge between a Value definition and its users.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Reg
All possible values of the reg field in the ModR/M byte.
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
unsigned getKillRegState(bool B)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
bool isDebugValue() const
mmo_iterator memoperands_end() const
initializer< Ty > init(const Ty &Val)
instr_iterator erase_instr(MachineInstr *I)
Remove an instruction from the instruction list and delete it.
bool isOptionalDef() const
Set if this operand is a optional def.
ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg)
getInstrPredicate - If instruction is predicated, returns its predicate condition, otherwise returns AL.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
const MachineOperand & getOperand(unsigned i) const
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
FunctionPass class - This class is used to implement most global optimizations.
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
iterator_range< pred_iterator > predecessors()
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
static bool UpdateCPSRUse(MachineInstr &MI, bool LiveCPSR)
std::vector< NodeType * >::reverse_iterator rpo_iterator
unsigned getOpcode() const
Return the opcode number for this descriptor.
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
static cl::opt< int > ReduceLimit("t2-reduce-limit", cl::init(-1), cl::Hidden)
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
bool isSuccessor(const MachineBasicBlock *MBB) const
isSuccessor - Return true if the specified MBB is a successor of this block.
static cl::opt< int > ReduceLimitLdSt("t2-reduce-limit3", cl::init(-1), cl::Hidden)
static bool HasImplicitCPSRDef(const MCInstrDesc &MCID)
static bool isHighLatencyCPSR(MachineInstr *Def)
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
static bool UpdateCPSRDef(MachineInstr &MI, bool LiveCPSR, bool &DefCPSR)
static bool isARMLowRegister(unsigned Reg)
isARMLowRegister - Returns true if the register is a low register (r0-r7).
Representation of each machine instruction.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
bool isLiveIn(unsigned Reg) const
isLiveIn - Return true if the specified register is in the live in set.
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
bool isCall(QueryType Type=AnyInBundle) const
iterator find(const KeyT &Val)
uint8_t getFlags() const
Return the MI flags bitvector.
unsigned getReg() const
getReg - Returns the register number.
bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr kills the specified register.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
const MCOperandInfo * OpInfo
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
print Print MemDeps of function
FunctionPass * createThumb2SizeReductionPass(std::function< bool(const Function &)> Ftor=nullptr)
createThumb2SizeReductionPass - Returns an instance of the Thumb2 size reduction pass.
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd)
Assign this MachineInstr's memory reference descriptor list.
static const MachineInstrBuilder & AddDefaultT1CC(const MachineInstrBuilder &MIB, bool isDead=false)
bool isInternalRead() const
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.