10 #define DEBUG_TYPE "hexinsert"
67 inline bool isDebug() {
81 explicit RegisterSet(
unsigned s,
bool t =
false) :
BitVector(s, t) {}
82 RegisterSet(
const RegisterSet &RS) :
BitVector(RS) {}
86 unsigned find_first()
const {
93 unsigned find_next(
unsigned Prev)
const {
100 RegisterSet &insert(
unsigned R) {
101 unsigned Idx = v2x(R);
105 RegisterSet &
remove(
unsigned R) {
106 unsigned Idx = v2x(R);
112 RegisterSet &insert(
const RegisterSet &Rs) {
115 RegisterSet &
remove(
const RegisterSet &Rs) {
119 reference operator[](
unsigned R) {
120 unsigned Idx = v2x(R);
124 bool operator[](
unsigned R)
const {
125 unsigned Idx = v2x(R);
126 assert(Idx <
size());
129 bool has(
unsigned R)
const {
130 unsigned Idx = v2x(R);
139 bool includes(
const RegisterSet &Rs)
const {
141 return !Rs.BitVector::test(*
this);
143 bool intersects(
const RegisterSet &Rs)
const {
148 void ensure(
unsigned Idx) {
150 resize(std::max(Idx+1, 32U));
152 static inline unsigned v2x(
unsigned v) {
155 static inline unsigned x2v(
unsigned x) {
165 const PrintRegSet &
P);
167 const RegisterSet &RS;
173 for (
unsigned R = P.RS.find_first(); R; R = P.RS.find_next(R))
184 struct UnsignedMap :
public DenseMap<unsigned,unsigned> {
185 UnsignedMap() : BaseType() {}
195 struct RegisterOrdering :
public UnsignedMap {
196 RegisterOrdering() : UnsignedMap() {}
197 unsigned operator[](
unsigned VR)
const {
198 const_iterator
F = find(VR);
204 bool operator() (
unsigned VR1,
unsigned VR2)
const {
205 return operator[](VR1) < operator[](VR2);
218 struct BitValueOrdering {
219 BitValueOrdering(
const RegisterOrdering &RB) : BaseOrd(RB) {}
222 const RegisterOrdering &BaseOrd;
232 if (V1.
is(0) || V2.
is(0))
236 if (V2.
is(1) || V1.
is(1))
239 unsigned Ind1 = BaseOrd[V1.
RefI.
Reg], Ind2 = BaseOrd[V2.
RefI.
Reg];
243 assert(V1.
RefI.
Pos != V2.
RefI.
Pos &&
"Bit values should be different");
252 struct CellMapShadow {
257 if (RInd >= CVect.size())
258 CVect.resize(std::max(RInd+16, 32U), 0);
268 typedef std::vector<const BitTracker::RegisterCell*> CellVectType;
277 struct RegisterCellLexCompare {
278 RegisterCellLexCompare(
const BitValueOrdering &BO, CellMapShadow &M)
279 : BitOrd(BO), CM(M) {}
280 bool operator() (
unsigned VR1,
unsigned VR2)
const;
282 const BitValueOrdering &BitOrd;
292 struct RegisterCellBitCompareSel {
293 RegisterCellBitCompareSel(
unsigned R,
unsigned B,
unsigned N,
294 const BitValueOrdering &BO, CellMapShadow &M)
295 : SelR(R), SelB(B), BitN(N), BitOrd(BO), CM(M) {}
296 bool operator() (
unsigned VR1,
unsigned VR2)
const;
298 const unsigned SelR, SelB;
300 const BitValueOrdering &BitOrd;
306 bool RegisterCellLexCompare::operator() (
unsigned VR1,
unsigned VR2)
const {
320 uint16_t W1 = RC1.
width(), W2 = RC2.width();
321 for (uint16_t i = 0, w =
std::min(W1, W2); i < w; ++i) {
324 return BitOrd(V1, V2);
330 return BitOrd.BaseOrd[VR1] < BitOrd.BaseOrd[VR2];
334 bool RegisterCellBitCompareSel::operator() (
unsigned VR1,
unsigned VR2)
const {
340 uint16_t Bit1 = (VR1 == SelR) ? SelB : BitN;
341 uint16_t Bit2 = (VR2 == SelR) ? SelB : BitN;
355 return BitOrd(V1, V2);
361 class OrderedRegisterList {
362 typedef std::vector<unsigned> ListType;
364 OrderedRegisterList(
const RegisterOrdering &RO) : Ord(RO) {}
365 void insert(
unsigned VR);
366 void remove(
unsigned VR);
367 unsigned operator[](
unsigned Idx)
const {
368 assert(Idx < Seq.size());
371 unsigned size()
const {
375 typedef ListType::iterator iterator;
376 typedef ListType::const_iterator const_iterator;
378 iterator
end() {
return Seq.
end(); }
379 const_iterator
begin()
const {
return Seq.
begin(); }
380 const_iterator
end()
const {
return Seq.
end(); }
383 unsigned idx(iterator It)
const {
return It-
begin(); }
386 const RegisterOrdering &Ord;
395 const OrderedRegisterList &RL;
401 OrderedRegisterList::const_iterator B = P.RL.begin(), E = P.RL.end();
402 for (OrderedRegisterList::const_iterator
I = B;
I != E; ++
I) {
413 void OrderedRegisterList::insert(
unsigned VR) {
414 iterator L = std::lower_bound(Seq.begin(), Seq.end(), VR, Ord);
423 iterator L = std::lower_bound(Seq.begin(), Seq.end(), VR, Ord);
424 assert(L != Seq.end());
434 IFRecord(
unsigned SR = 0,
unsigned IR = 0, uint16_t W = 0, uint16_t O = 0)
435 : SrcR(SR), InsR(
IR), Wdh(W), Off(O) {}
450 unsigned SrcR = P.IFR.SrcR, InsR = P.IFR.InsR;
452 <<
",#" << P.IFR.Wdh <<
",#" << P.IFR.Off <<
')';
456 typedef std::pair<IFRecord,RegisterSet> IFRecordWithRegSet;
473 virtual const char *getPassName()
const {
474 return "Hexagon generate \"insert\" instructions";
486 void buildOrderingMF(RegisterOrdering &RO)
const;
487 void buildOrderingBT(RegisterOrdering &RB, RegisterOrdering &RO)
const;
489 bool isConstant(
unsigned VR)
const;
490 bool isSmallConstant(
unsigned VR)
const;
491 bool isValidInsertForm(
unsigned DstR,
unsigned SrcR,
unsigned InsR,
492 uint16_t L, uint16_t S)
const;
493 bool findSelfReference(
unsigned VR)
const;
494 bool findNonSelfReference(
unsigned VR)
const;
495 void getInstrDefs(
const MachineInstr *
MI, RegisterSet &Defs)
const;
496 void getInstrUses(
const MachineInstr *
MI, RegisterSet &Uses)
const;
499 PairMapType &M)
const;
502 PairMapType &M)
const;
503 bool findRecordInsertForms(
unsigned VR, OrderedRegisterList &AVs);
505 void findRemovableRegisters(
unsigned VR, IFRecord IF,
506 RegisterSet &RMs)
const;
507 void computeRemovableRegisters();
509 void pruneEmptyLists();
510 void pruneCoveredSets(
unsigned VR);
511 void pruneUsesTooFar(
unsigned VR,
const UnsignedMap &RPO, PairMapType &M);
512 void pruneRegCopies(
unsigned VR);
513 void pruneCandidates();
514 void selectCandidates();
515 bool generateInserts();
520 typedef std::vector<IFRecordWithRegSet> IFListType;
523 void dump_map()
const;
533 RegisterOrdering BaseOrd;
534 RegisterOrdering CellOrd;
542 void HexagonGenInsert::dump_map()
const {
543 typedef IFMapType::const_iterator iterator;
544 for (iterator
I = IFMap.begin(), E = IFMap.end();
I != E; ++
I) {
546 const IFListType &LL =
I->second;
547 for (
unsigned i = 0, n = LL.size(); i < n; ++i)
548 dbgs() <<
" " << PrintIFR(LL[i].first, HRI) <<
", "
549 << PrintRegSet(LL[i].second, HRI) <<
'\n';
554 void HexagonGenInsert::buildOrderingMF(RegisterOrdering &RO)
const {
557 for (mf_iterator
A = MFN->begin(), Z = MFN->end();
A != Z; ++
A) {
559 if (!CMS->BT.reached(&B))
562 for (mb_iterator
I = B.
begin(), E = B.
end();
I != E; ++
I) {
568 assert(MO.
getSubReg() == 0 &&
"Unexpected subregister in definition");
570 RO.insert(std::make_pair(R, Index++));
581 void HexagonGenInsert::buildOrderingBT(RegisterOrdering &RB,
582 RegisterOrdering &RO)
const {
585 BitValueOrdering BVO(RB);
586 RegisterCellLexCompare LexCmp(BVO, *CMS);
587 typedef std::vector<unsigned> SortableVectorType;
588 SortableVectorType VRs;
589 for (RegisterOrdering::iterator
I = RB.begin(), E = RB.end();
I != E; ++
I)
590 VRs.push_back(
I->first);
591 std::sort(VRs.begin(), VRs.end(), LexCmp);
593 for (
unsigned i = 0, n = VRs.size(); i < n; ++i)
594 RO.insert(std::make_pair(VRs[i], i));
599 return RC == &Hexagon::IntRegsRegClass || RC == &Hexagon::DoubleRegsRegClass;
603 bool HexagonGenInsert::isConstant(
unsigned VR)
const {
605 uint16_t W = RC.
width();
606 for (uint16_t i = 0; i < W; ++i) {
608 if (BV.
is(0) || BV.
is(1))
616 bool HexagonGenInsert::isSmallConstant(
unsigned VR)
const {
618 uint16_t W = RC.
width();
621 uint64_t V = 0, B = 1;
622 for (uint16_t i = 0; i < W; ++i) {
640 bool HexagonGenInsert::isValidInsertForm(
unsigned DstR,
unsigned SrcR,
641 unsigned InsR, uint16_t L, uint16_t S)
const {
646 if (!isIntClass(DstRC) || !isIntClass(SrcRC) || !isIntClass(InsRC))
654 if (DstRC == &Hexagon::DoubleRegsRegClass)
657 if (S < 32 && S+L > 32)
663 bool HexagonGenInsert::findSelfReference(
unsigned VR)
const {
665 for (uint16_t i = 0, w = RC.
width(); i < w; ++i) {
674 bool HexagonGenInsert::findNonSelfReference(
unsigned VR)
const {
676 for (uint16_t i = 0, w = RC.
width(); i < w; ++i) {
685 void HexagonGenInsert::getInstrDefs(
const MachineInstr *MI,
686 RegisterSet &Defs)
const {
699 void HexagonGenInsert::getInstrUses(
const MachineInstr *MI,
700 RegisterSet &Uses)
const {
715 PairMapType &M)
const {
718 assert(FromB != ToB);
722 PairMapType::iterator
F = M.find(std::make_pair(FromN, ToN));
725 unsigned ToRPO = RPO.lookup(ToN);
734 if (PB == FromB || RPO.lookup(PB->
getNumber()) >= ToRPO)
736 unsigned D = PB->
size() + distance(FromB, PB, RPO, M);
742 M.insert(std::make_pair(std::make_pair(FromN, ToN), MaxD));
749 PairMapType &M)
const {
752 return std::distance(FromI, ToI);
753 unsigned D1 = std::distance(
TB->begin(), ToI);
754 unsigned D2 = distance(FB,
TB, RPO, M);
755 unsigned D3 = std::distance(FromI, FB->
end());
760 bool HexagonGenInsert::findRecordInsertForms(
unsigned VR,
761 OrderedRegisterList &AVs) {
764 <<
" AVs: " << PrintORL(AVs, HRI) <<
"\n";
769 typedef OrderedRegisterList::iterator iterator;
770 BitValueOrdering BVO(BaseOrd);
772 uint16_t W = RC.
width();
774 typedef std::pair<unsigned,uint16_t> RSRecord;
775 typedef std::vector<RSRecord> RSListType;
785 for (uint16_t S = 0; S < W; ++S) {
786 iterator B = AVs.begin(), E = AVs.end();
794 for (L = 0; L < W-S; ++L) {
797 RegisterCellBitCompareSel RCB(VR, S+L, L, BVO, *CMS);
798 iterator NewB = std::lower_bound(B, E, VR, RCB);
799 iterator NewE = std::upper_bound(NewB, E, VR, RCB);
805 for (iterator
I = B;
I != NewB; ++
I)
806 LM[L].push_back(std::make_pair(*
I, S));
807 for (iterator
I = NewE;
I != E; ++
I)
808 LM[L].push_back(std::make_pair(*
I, S));
816 assert(B == E || L == W-S);
818 for (iterator
I = B;
I != E; ++
I)
819 LM[L].push_back(std::make_pair(*
I, S));
827 dbgs() <<
"Prefixes matching register " <<
PrintReg(VR, HRI) <<
"\n";
828 for (LRSMapType::iterator
I = LM.begin(), E = LM.end();
I != E; ++
I) {
829 dbgs() <<
" L=" <<
I->first <<
':';
830 const RSListType &LL =
I->second;
831 for (
unsigned i = 0, n = LL.size(); i < n; ++i)
833 << LL[i].second <<
')';
839 bool Recorded =
false;
841 for (iterator
I = AVs.begin(), E = AVs.end();
I != E; ++
I) {
843 int FDi = -1, LDi = -1;
845 uint16_t AW = AC.
width();
846 for (uint16_t i = 0, w =
std::min(W, AW); i < w; ++i) {
857 uint16_t FD = FDi,
LD = LDi;
858 uint16_t MinL = LD-FD+1;
859 for (uint16_t L = MinL; L < W; ++L) {
860 LRSMapType::iterator F = LM.find(L);
863 RSListType &LL = F->second;
864 for (
unsigned i = 0, n = LL.size(); i < n; ++i) {
865 uint16_t S = LL[i].second;
872 uint16_t EL = L-MinL;
873 uint16_t LowS = (EL < FD) ? FD-EL : 0;
876 unsigned InsR = LL[i].first;
877 if (!isValidInsertForm(VR, SrcR, InsR, L, S))
881 <<
',' <<
PrintReg(InsR, HRI) <<
",#" << L <<
",#"
884 IFRecordWithRegSet RR(IFRecord(SrcR, InsR, L, S), RegisterSet());
885 IFMap[VR].push_back(RR);
896 OrderedRegisterList &AVs) {
902 if (!CMS->BT.reached(B))
909 RegisterSet BlockDefs, InsDefs;
913 getInstrDefs(MI, InsDefs);
920 for (
unsigned VR = InsDefs.find_first(); VR; VR = InsDefs.find_next(VR)) {
923 if (!DoConst && isConstant(VR))
929 if (findSelfReference(VR) || isSmallConstant(VR))
932 findRecordInsertForms(VR, AVs);
938 for (
unsigned VR = InsDefs.find_first(); VR; VR = InsDefs.find_next(VR))
940 BlockDefs.insert(InsDefs);
945 typedef GTN::ChildIteratorType ChildIter;
946 for (ChildIter
I = GTN::child_begin(N), E = GTN::child_end(N);
I != E; ++
I) {
948 collectInBlock(SB, AVs);
951 for (
unsigned VR = BlockDefs.find_first(); VR; VR = BlockDefs.find_next(VR))
956 void HexagonGenInsert::findRemovableRegisters(
unsigned VR, IFRecord IF,
957 RegisterSet &RMs)
const {
967 while (!Regs[S].empty()) {
969 unsigned OtherS = 1-S;
970 Regs[OtherS].clear();
971 for (
unsigned R = Regs[S].find_first(); R; R = Regs[S].find_next(R)) {
973 if (R == IF.SrcR || R == IF.InsR)
985 if (!findNonSelfReference(R))
995 getInstrUses(DefI, Regs[OtherS]);
1008 void HexagonGenInsert::computeRemovableRegisters() {
1009 for (IFMapType::iterator
I = IFMap.begin(), E = IFMap.end();
I != E; ++
I) {
1010 IFListType &LL =
I->second;
1011 for (
unsigned i = 0, n = LL.size(); i < n; ++i)
1012 findRemovableRegisters(
I->first, LL[i].first, LL[i].second);
1017 void HexagonGenInsert::pruneEmptyLists() {
1022 for (IFMapType::iterator
I = IFMap.begin(), E = IFMap.end();
I != E; ++
I) {
1023 if (
I->second.size() == 0)
1026 for (
unsigned i = 0, n = Prune.size(); i < n; ++i)
1027 IFMap.erase(Prune[i]);
1031 void HexagonGenInsert::pruneCoveredSets(
unsigned VR) {
1032 IFMapType::iterator F = IFMap.find(VR);
1033 assert(F != IFMap.end());
1034 IFListType &LL = F->second;
1044 bool DefEx = HII->isConstExtended(DefVR);
1046 for (
unsigned i = 0, n = LL.size(); i < n; ++i) {
1047 if (LL[i].second.empty())
1052 if (!DefEx || HasNE) {
1055 auto IsEmpty = [] (
const IFRecordWithRegSet &
IR) ->
bool {
1056 return IR.second.empty();
1058 auto End = std::remove_if(LL.begin(), LL.end(), IsEmpty);
1059 if (End != LL.end())
1060 LL.erase(End, LL.end());
1067 IFRecord MaxIF = LL[0].first;
1068 for (
unsigned i = 1, n = LL.size(); i < n; ++i) {
1070 const IFRecord &IF = LL[i].first;
1071 unsigned M0 = BaseOrd[MaxIF.SrcR], M1 = BaseOrd[MaxIF.InsR];
1072 unsigned R0 = BaseOrd[IF.SrcR], R1 = BaseOrd[IF.InsR];
1079 if (MaxIF.Wdh > IF.Wdh)
1081 if (MaxIF.Wdh == IF.Wdh && MaxIF.Off >= IF.Off)
1091 LL.push_back(std::make_pair(MaxIF, RegisterSet()));
1101 for (
unsigned i = 0, n = LL.size(); i < n; ) {
1102 const RegisterSet &RMi = LL[i].second;
1105 if (j != i && LL[j].second.includes(RMi))
1113 LL.erase(LL.begin()+i);
1119 void HexagonGenInsert::pruneUsesTooFar(
unsigned VR,
const UnsignedMap &RPO,
1121 IFMapType::iterator F = IFMap.find(VR);
1122 assert(F != IFMap.end());
1123 IFListType &LL = F->second;
1127 for (
unsigned i = LL.size(); i > 0; --i) {
1128 unsigned SR = LL[i-1].first.SrcR,
IR = LL[i-1].first.InsR;
1131 unsigned DSV = distance(DefS, DefV, RPO, M);
1133 unsigned DIV = distance(DefI, DefV, RPO, M);
1137 LL.erase(LL.begin()+(i-1));
1142 void HexagonGenInsert::pruneRegCopies(
unsigned VR) {
1143 IFMapType::iterator F = IFMap.find(VR);
1144 assert(F != IFMap.end());
1145 IFListType &LL = F->second;
1147 auto IsCopy = [] (
const IFRecordWithRegSet &
IR) ->
bool {
1148 return IR.first.Wdh == 32 && (
IR.first.Off == 0 ||
IR.first.Off == 32);
1150 auto End = std::remove_if(LL.begin(), LL.end(), IsCopy);
1151 if (End != LL.end())
1152 LL.erase(End, LL.end());
1156 void HexagonGenInsert::pruneCandidates() {
1161 for (IFMapType::iterator
I = IFMap.begin(), E = IFMap.end();
I != E; ++
I)
1162 pruneCoveredSets(
I->first);
1168 for (RPOTType::rpo_iterator
I = RPOT.begin(), E = RPOT.end();
I != E; ++
I)
1169 RPO[(*I)->getNumber()] = RPON++;
1173 for (IFMapType::iterator
I = IFMap.begin(), E = IFMap.end();
I != E; ++
I)
1174 pruneUsesTooFar(
I->first, RPO, Memo);
1178 for (IFMapType::iterator
I = IFMap.begin(), E = IFMap.end();
I != E; ++
I)
1179 pruneRegCopies(
I->first);
1193 IFOrdering(
const UnsignedMap &UC,
const RegisterOrdering &BO)
1194 : UseC(UC), BaseOrd(BO) {}
1195 bool operator() (
const IFRecordWithRegSet &
A,
1196 const IFRecordWithRegSet &B)
const;
1198 void stats(
const RegisterSet &Rs,
unsigned &Size,
unsigned &Zero,
1199 unsigned &Sum)
const;
1200 const UnsignedMap &UseC;
1201 const RegisterOrdering &BaseOrd;
1206 bool IFOrdering::operator() (
const IFRecordWithRegSet &
A,
1207 const IFRecordWithRegSet &B)
const {
1208 unsigned SizeA = 0, ZeroA = 0, SumA = 0;
1209 unsigned SizeB = 0, ZeroB = 0, SumB = 0;
1210 stats(A.second, SizeA, ZeroA, SumA);
1211 stats(B.second, SizeB, ZeroB, SumB);
1215 return ZeroA > ZeroB;
1217 uint64_t AvgA = SumA*SizeB, AvgB = SumB*SizeA;
1223 unsigned OSA = BaseOrd[A.first.SrcR], OSB = BaseOrd[B.first.SrcR];
1226 unsigned OIA = BaseOrd[A.first.InsR], OIB = BaseOrd[B.first.InsR];
1229 if (A.first.Wdh != B.first.Wdh)
1230 return A.first.Wdh < B.first.Wdh;
1231 return A.first.Off < B.first.Off;
1236 unsigned &Sum)
const {
1237 for (
unsigned R = Rs.find_first(); R; R = Rs.find_next(R)) {
1238 UnsignedMap::const_iterator F = UseC.find(R);
1239 assert(F != UseC.end());
1240 unsigned UC = F->second;
1249 void HexagonGenInsert::selectCandidates() {
1257 UnsignedMap UseC, RemC;
1258 IFMapType::iterator End = IFMap.end();
1260 for (IFMapType::iterator
I = IFMap.begin();
I != End; ++
I) {
1261 const IFListType &LL =
I->second;
1263 for (
unsigned i = 0, n = LL.size(); i < n; ++i)
1264 TT.insert(LL[i].second);
1265 for (
unsigned R = TT.find_first(); R; R = TT.find_next(R))
1270 for (
unsigned R = AllRMs.find_first(); R; R = AllRMs.find_next(R)) {
1276 use_iterator E = MRI->use_nodbg_end();
1277 for (use_iterator
I = MRI->use_nodbg_begin(R);
I != E; ++
I)
1279 unsigned C = UIs.size();
1282 unsigned D = RemC[R];
1283 UseC[R] = (C > D) ? C-D : 0;
1288 if (!SelectAll0 && !SelectHas0)
1296 IFOrdering IFO(UseC, BaseOrd);
1297 for (IFMapType::iterator
I = IFMap.begin();
I != End; ++
I) {
1298 IFListType &LL =
I->second;
1305 IFListType::iterator MinI = std::min_element(LL.begin(), LL.end(), IFO);
1306 assert(MinI != LL.end());
1307 IFRecordWithRegSet M = *MinI;
1318 getInstrUses(DefI, Us);
1319 bool Accept =
false;
1323 for (
unsigned R = Us.find_first(); R; R = Us.find_next(R)) {
1330 }
else if (SelectHas0) {
1332 for (
unsigned R = Us.find_first(); R; R = Us.find_next(R)) {
1349 for (IFMapType::iterator
I = IFMap.begin();
I != End; ++
I) {
1350 const IFListType &LL =
I->second;
1352 AllRMs.insert(LL[0].second);
1354 for (IFMapType::iterator
I = IFMap.begin();
I != End; ++
I) {
1355 IFListType &LL =
I->second;
1358 unsigned SR = LL[0].first.SrcR,
IR = LL[0].first.InsR;
1359 if (AllRMs[SR] || AllRMs[
IR])
1367 bool HexagonGenInsert::generateInserts() {
1371 for (IFMapType::iterator
I = IFMap.begin(), E = IFMap.end();
I != E; ++
I) {
1372 unsigned VR =
I->first;
1374 unsigned NewVR = MRI->createVirtualRegister(RC);
1381 for (IFMapType::iterator
I = IFMap.begin(), E = IFMap.end();
I != E; ++
I) {
1385 unsigned NewR = RegMap[
I->first];
1386 bool R32 = MRI->getRegClass(NewR) == &Hexagon::IntRegsRegClass;
1387 const MCInstrDesc &D = R32 ? HII->get(Hexagon::S2_insert)
1388 : HII->get(Hexagon::S2_insertp);
1389 IFRecord IF =
I->second[0].first;
1390 unsigned Wdh = IF.Wdh, Off = IF.Off;
1392 if (R32 && MRI->getRegClass(IF.InsR) == &Hexagon::DoubleRegsRegClass) {
1393 InsS = Hexagon::subreg_loreg;
1395 InsS = Hexagon::subreg_hireg;
1407 .
addReg(IF.InsR, 0, InsS)
1411 MRI->clearKillFlags(IF.SrcR);
1412 MRI->clearKillFlags(IF.InsR);
1415 for (IFMapType::iterator
I = IFMap.begin(), E = IFMap.end();
I != E; ++
I) {
1417 MRI->replaceRegWith(
I->first, RegMap[
I->first]);
1426 bool Changed =
false;
1428 for (
auto I = GTN::child_begin(N), E = GTN::child_end(N);
I != E; ++
I)
1429 Changed |= removeDeadCode(*
I);
1432 std::vector<MachineInstr*> Instrs;
1434 Instrs.push_back(&*
I);
1436 for (
auto I = Instrs.begin(), E = Instrs.end();
I != E; ++
I) {
1448 bool AllDead =
true;
1451 if (!Op->isReg() || !Op->isDef())
1453 unsigned R = Op->getReg();
1455 !MRI->use_nodbg_empty(R)) {
1465 for (
unsigned I = 0, N = Regs.
size();
I !=
N; ++
I)
1466 MRI->markUsesInDebugValueAsUndef(Regs[
I]);
1476 bool Changed =
false;
1488 HII =
ST.getInstrInfo();
1489 HRI =
ST.getRegisterInfo();
1492 MDT = &getAnalysis<MachineDominatorTree>();
1499 Changed |= removeDeadCode(MDT->getRootNode());
1503 BTLoc.trace(isDebug());
1505 CellMapShadow MS(BTLoc);
1508 buildOrderingMF(BaseOrd);
1509 buildOrderingBT(BaseOrd, CellOrd);
1512 dbgs() <<
"Cell ordering:\n";
1513 for (RegisterOrdering::iterator
I = CellOrd.begin(), E = CellOrd.end();
1515 unsigned VR =
I->first, Pos =
I->second;
1522 OrderedRegisterList AvailR(CellOrd);
1526 collectInBlock(RootB, AvailR);
1528 computeRemovableRegisters();
1532 dbgs() <<
"Candidates after collection:\n";
1545 dbgs() <<
"Candidates after pruning:\n";
1558 dbgs() <<
"Candidates after selection:\n";
1567 for (IFMapType::iterator
I = IFMap.begin(), E = IFMap.end();
I != E; ++
I) {
1572 for (
unsigned i = 0, n = Out.size(); i < n; ++i)
1573 IFMap.erase(Out[i]);
1578 Changed = generateInserts();
1586 return new HexagonGenInsert();
1595 "Hexagon generate \"insert\" instructions",
false,
false)
static cl::opt< bool > OptSelectHas0("insert-has0", cl::init(false), cl::Hidden, cl::ZeroOrMore)
void push_back(const T &Elt)
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
const_iterator end(StringRef path)
Get end iterator over path.
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
void initializeHexagonGenInsertPass(PassRegistry &)
static unsigned virtReg2Index(unsigned Reg)
virtReg2Index - Convert a virtual register number to a 0-based index.
static unsigned index2VirtReg(unsigned Index)
index2VirtReg - Convert a 0-based index to a virtual register number.
int getNumber() const
getNumber - MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a M...
std::error_code remove(const Twine &path, bool IgnoreNonExisting=true)
Remove path.
bool anyCommon(const BitVector &RHS) const
Test if any common bits are set.
int find_next(unsigned Prev) const
find_next - Returns the index of the next set bit following the "Prev" bit.
Describe properties that are true of each instruction in the target description file.
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
Hexagon generate insert false
const_iterator begin(StringRef path)
Get begin iterator over path.
bool any() const
any - Returns true if any bit is set.
Hexagon generate insert instructions
static cl::opt< bool > OptTiming("insert-timing", cl::init(false), cl::Hidden, cl::ZeroOrMore, cl::desc("Enable timing of insert generation"))
AnalysisUsage & addRequired()
#define INITIALIZE_PASS_DEPENDENCY(depName)
void clear()
clear - Clear all bits.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
NamedRegionTimer - This class is basically a combination of TimeRegion and Timer. ...
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isInt< 8 >(int64_t x)
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
Number of individual test Apply this number of consecutive mutations to each input exit after the first new interesting input is found the minimized corpus is saved into the first input directory Number of jobs to run If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
PrintReg - Helper class for printing registers on a raw_ostream.
bool is(unsigned T) const
BitVector & operator|=(const BitVector &RHS)
Base class for the actual dominator tree node.
reverse_iterator rbegin()
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
static cl::opt< bool > OptTimingDetail("insert-timing-detail", cl::init(false), cl::Hidden, cl::ZeroOrMore, cl::desc("Enable detailed timing of insert ""generation"))
const MachineBasicBlock * getParent() const
bundle_iterator< MachineInstr, instr_iterator > iterator
initializer< Ty > init(const Ty &Val)
friend const_iterator end(StringRef path)
Get end iterator over path.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
This file contains the declarations for the subclasses of Constant, which represent the different fla...
uint32_t Lo_32(uint64_t Value)
Lo_32 - This function returns the low 32 bits of a 64 bit value.
const MachineOperand & getOperand(unsigned i) const
Represent the analysis usage information of a pass.
FunctionPass class - This class is used to implement most global optimizations.
static cl::opt< unsigned > VRegDistCutoff("insert-dist-cutoff", cl::init(30U), cl::Hidden, cl::ZeroOrMore, cl::desc("Vreg distance cutoff for insert ""generation."))
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
unsigned getSubReg() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
pred_iterator pred_begin()
std::vector< MachineBasicBlock * >::const_iterator const_pred_iterator
bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
const RegisterCell & lookup(unsigned Reg) const
friend const_iterator begin(StringRef path)
Get begin iterator over path.
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
reference operator[](unsigned Idx)
bool test(unsigned Idx) const
FunctionPass * createHexagonGenInsert()
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
ConstMIOperands - Iterate over operands of a single const instruction.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
bundle_iterator< const MachineInstr, const_instr_iterator > const_iterator
static const uint16_t * lookup(unsigned opcode, unsigned domain)
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static cl::opt< bool > OptConst("insert-const", cl::init(false), cl::Hidden, cl::ZeroOrMore)
The TimerGroup class is used to group together related timers into a single report that is printed wh...
PredIterator< BasicBlock, Value::user_iterator > pred_iterator
uint32_t Hi_32(uint64_t Value)
Hi_32 - This function returns the high 32 bits of a 64 bit value.
iterator getFirstNonPHI()
Returns a pointer to the first instruction in this block that is not a PHINode instruction.
bool isInt< 16 >(int64_t x)
raw_ostream & operator<<(raw_ostream &OS, const APInt &I)
static cl::opt< unsigned > VRegIndexCutoff("insert-vreg-cutoff", cl::init(~0U), cl::Hidden, cl::ZeroOrMore, cl::desc("Vreg# cutoff for insert generation."))
unsigned getReg() const
getReg - Returns the register number.
bool isValid() const
isValid - Returns true until all the operands have been visited.
INITIALIZE_PASS_BEGIN(HexagonGenInsert,"hexinsert","Hexagon generate \"insert\" instructions", false, false) INITIALIZE_PASS_END(HexagonGenInsert
This class implements an extremely fast bulk output stream that can only output to a stream...
C - The default llvm calling convention, compatible with C.
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
static cl::opt< bool > OptSelectAll0("insert-all0", cl::init(false), cl::Hidden, cl::ZeroOrMore)
bool isRegSequence() const
#define LLVM_FUNCTION_NAME
LLVM_FUNCTION_NAME
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Statically lint checks LLVM IR
bool DebugFlag
DebugFlag - This boolean is set to true if the '-debug' command line option is specified.
bool isCurrentDebugType(const char *Type)
isCurrentDebugType - Return true if the specified string is the debug type specified on the command l...