LLVM  3.7.0
VirtRegMap.cpp
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1 //===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the VirtRegMap class.
11 //
12 // It also contains implementations of the Spiller interface, which, given a
13 // virtual register map and a machine function, eliminates all virtual
14 // references by replacing them with physical register references - adding spill
15 // code as necessary.
16 //
17 //===----------------------------------------------------------------------===//
18 
20 #include "LiveDebugVariables.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/SparseSet.h"
23 #include "llvm/ADT/Statistic.h"
30 #include "llvm/CodeGen/Passes.h"
31 #include "llvm/IR/Function.h"
33 #include "llvm/Support/Compiler.h"
34 #include "llvm/Support/Debug.h"
40 #include <algorithm>
41 using namespace llvm;
42 
43 #define DEBUG_TYPE "regalloc"
44 
45 STATISTIC(NumSpillSlots, "Number of spill slots allocated");
46 STATISTIC(NumIdCopies, "Number of identity moves eliminated after rewriting");
47 
48 //===----------------------------------------------------------------------===//
49 // VirtRegMap implementation
50 //===----------------------------------------------------------------------===//
51 
52 char VirtRegMap::ID = 0;
53 
54 INITIALIZE_PASS(VirtRegMap, "virtregmap", "Virtual Register Map", false, false)
55 
56 bool VirtRegMap::runOnMachineFunction(MachineFunction &mf) {
57  MRI = &mf.getRegInfo();
58  TII = mf.getSubtarget().getInstrInfo();
59  TRI = mf.getSubtarget().getRegisterInfo();
60  MF = &mf;
61 
62  Virt2PhysMap.clear();
63  Virt2StackSlotMap.clear();
64  Virt2SplitMap.clear();
65 
66  grow();
67  return false;
68 }
69 
71  unsigned NumRegs = MF->getRegInfo().getNumVirtRegs();
72  Virt2PhysMap.resize(NumRegs);
73  Virt2StackSlotMap.resize(NumRegs);
74  Virt2SplitMap.resize(NumRegs);
75 }
76 
77 unsigned VirtRegMap::createSpillSlot(const TargetRegisterClass *RC) {
78  int SS = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
79  RC->getAlignment());
80  ++NumSpillSlots;
81  return SS;
82 }
83 
84 bool VirtRegMap::hasPreferredPhys(unsigned VirtReg) {
85  unsigned Hint = MRI->getSimpleHint(VirtReg);
86  if (!Hint)
87  return 0;
89  Hint = getPhys(Hint);
90  return getPhys(VirtReg) == Hint;
91 }
92 
93 bool VirtRegMap::hasKnownPreference(unsigned VirtReg) {
94  std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(VirtReg);
96  return true;
98  return hasPhys(Hint.second);
99  return false;
100 }
101 
102 int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
103  assert(TargetRegisterInfo::isVirtualRegister(virtReg));
104  assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
105  "attempt to assign stack slot to already spilled register");
106  const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
107  return Virt2StackSlotMap[virtReg] = createSpillSlot(RC);
108 }
109 
110 void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int SS) {
111  assert(TargetRegisterInfo::isVirtualRegister(virtReg));
112  assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
113  "attempt to assign stack slot to already spilled register");
114  assert((SS >= 0 ||
115  (SS >= MF->getFrameInfo()->getObjectIndexBegin())) &&
116  "illegal fixed frame index");
117  Virt2StackSlotMap[virtReg] = SS;
118 }
119 
120 void VirtRegMap::print(raw_ostream &OS, const Module*) const {
121  OS << "********** REGISTER MAP **********\n";
122  for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
124  if (Virt2PhysMap[Reg] != (unsigned)VirtRegMap::NO_PHYS_REG) {
125  OS << '[' << PrintReg(Reg, TRI) << " -> "
126  << PrintReg(Virt2PhysMap[Reg], TRI) << "] "
127  << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n";
128  }
129  }
130 
131  for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
133  if (Virt2StackSlotMap[Reg] != VirtRegMap::NO_STACK_SLOT) {
134  OS << '[' << PrintReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg]
135  << "] " << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n";
136  }
137  }
138  OS << '\n';
139 }
140 
141 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
142 void VirtRegMap::dump() const {
143  print(dbgs());
144 }
145 #endif
146 
147 //===----------------------------------------------------------------------===//
148 // VirtRegRewriter
149 //===----------------------------------------------------------------------===//
150 //
151 // The VirtRegRewriter is the last of the register allocator passes.
152 // It rewrites virtual registers to physical registers as specified in the
153 // VirtRegMap analysis. It also updates live-in information on basic blocks
154 // according to LiveIntervals.
155 //
156 namespace {
157 class VirtRegRewriter : public MachineFunctionPass {
158  MachineFunction *MF;
159  const TargetMachine *TM;
160  const TargetRegisterInfo *TRI;
161  const TargetInstrInfo *TII;
162  MachineRegisterInfo *MRI;
163  SlotIndexes *Indexes;
164  LiveIntervals *LIS;
165  VirtRegMap *VRM;
166  SparseSet<unsigned> PhysRegs;
167 
168  void rewrite();
169  void addMBBLiveIns();
170  bool readsUndefSubreg(const MachineOperand &MO) const;
171 public:
172  static char ID;
173  VirtRegRewriter() : MachineFunctionPass(ID) {}
174 
175  void getAnalysisUsage(AnalysisUsage &AU) const override;
176 
177  bool runOnMachineFunction(MachineFunction&) override;
178 };
179 } // end anonymous namespace
180 
182 
183 INITIALIZE_PASS_BEGIN(VirtRegRewriter, "virtregrewriter",
184  "Virtual Register Rewriter", false, false)
191  "Virtual Register Rewriter", false, false)
192 
193 char VirtRegRewriter::ID = 0;
194 
195 void VirtRegRewriter::getAnalysisUsage(AnalysisUsage &AU) const {
196  AU.setPreservesCFG();
197  AU.addRequired<LiveIntervals>();
198  AU.addRequired<SlotIndexes>();
199  AU.addPreserved<SlotIndexes>();
200  AU.addRequired<LiveDebugVariables>();
201  AU.addRequired<LiveStacks>();
202  AU.addPreserved<LiveStacks>();
203  AU.addRequired<VirtRegMap>();
205 }
206 
207 bool VirtRegRewriter::runOnMachineFunction(MachineFunction &fn) {
208  MF = &fn;
209  TM = &MF->getTarget();
210  TRI = MF->getSubtarget().getRegisterInfo();
211  TII = MF->getSubtarget().getInstrInfo();
212  MRI = &MF->getRegInfo();
213  Indexes = &getAnalysis<SlotIndexes>();
214  LIS = &getAnalysis<LiveIntervals>();
215  VRM = &getAnalysis<VirtRegMap>();
216  DEBUG(dbgs() << "********** REWRITE VIRTUAL REGISTERS **********\n"
217  << "********** Function: "
218  << MF->getName() << '\n');
219  DEBUG(VRM->dump());
220 
221  // Add kill flags while we still have virtual registers.
222  LIS->addKillFlags(VRM);
223 
224  // Live-in lists on basic blocks are required for physregs.
225  addMBBLiveIns();
226 
227  // Rewrite virtual registers.
228  rewrite();
229 
230  // Write out new DBG_VALUE instructions.
231  getAnalysis<LiveDebugVariables>().emitDebugValues(VRM);
232 
233  // All machine operands and other references to virtual registers have been
234  // replaced. Remove the virtual registers and release all the transient data.
235  VRM->clearAllVirt();
236  MRI->clearVirtRegs();
237  return true;
238 }
239 
240 // Compute MBB live-in lists from virtual register live ranges and their
241 // assignments.
242 void VirtRegRewriter::addMBBLiveIns() {
244  for (unsigned Idx = 0, IdxE = MRI->getNumVirtRegs(); Idx != IdxE; ++Idx) {
245  unsigned VirtReg = TargetRegisterInfo::index2VirtReg(Idx);
246  if (MRI->reg_nodbg_empty(VirtReg))
247  continue;
248  LiveInterval &LI = LIS->getInterval(VirtReg);
249  if (LI.empty() || LIS->intervalIsInOneMBB(LI))
250  continue;
251  // This is a virtual register that is live across basic blocks. Its
252  // assigned PhysReg must be marked as live-in to those blocks.
253  unsigned PhysReg = VRM->getPhys(VirtReg);
254  assert(PhysReg != VirtRegMap::NO_PHYS_REG && "Unmapped virtual register.");
255 
256  if (LI.hasSubRanges()) {
257  for (LiveInterval::SubRange &S : LI.subranges()) {
258  for (const auto &Seg : S.segments) {
259  if (!Indexes->findLiveInMBBs(Seg.start, Seg.end, LiveIn))
260  continue;
261  for (MCSubRegIndexIterator SR(PhysReg, TRI); SR.isValid(); ++SR) {
262  unsigned SubReg = SR.getSubReg();
263  unsigned SubRegIndex = SR.getSubRegIndex();
264  unsigned SubRegLaneMask = TRI->getSubRegIndexLaneMask(SubRegIndex);
265  if ((SubRegLaneMask & S.LaneMask) == 0)
266  continue;
267  for (unsigned i = 0, e = LiveIn.size(); i != e; ++i) {
268  LiveIn[i]->addLiveIn(SubReg);
269  }
270  }
271  LiveIn.clear();
272  }
273  }
274  } else {
275  // Scan the segments of LI.
276  for (const auto &Seg : LI.segments) {
277  if (!Indexes->findLiveInMBBs(Seg.start, Seg.end, LiveIn))
278  continue;
279  for (unsigned i = 0, e = LiveIn.size(); i != e; ++i)
280  LiveIn[i]->addLiveIn(PhysReg);
281  LiveIn.clear();
282  }
283  }
284  }
285 
286  // Sort and unique MBB LiveIns as we've not checked if SubReg/PhysReg were in
287  // each MBB's LiveIns set before calling addLiveIn on them.
288  for (MachineBasicBlock &MBB : *MF)
289  MBB.sortUniqueLiveIns();
290 }
291 
292 /// Returns true if the given machine operand \p MO only reads undefined lanes.
293 /// The function only works for use operands with a subregister set.
294 bool VirtRegRewriter::readsUndefSubreg(const MachineOperand &MO) const {
295  // Shortcut if the operand is already marked undef.
296  if (MO.isUndef())
297  return true;
298 
299  unsigned Reg = MO.getReg();
300  const LiveInterval &LI = LIS->getInterval(Reg);
301  const MachineInstr &MI = *MO.getParent();
302  SlotIndex BaseIndex = LIS->getInstructionIndex(&MI);
303  // This code is only meant to handle reading undefined subregisters which
304  // we couldn't properly detect before.
305  assert(LI.liveAt(BaseIndex) &&
306  "Reads of completely dead register should be marked undef already");
307  unsigned SubRegIdx = MO.getSubReg();
308  unsigned UseMask = TRI->getSubRegIndexLaneMask(SubRegIdx);
309  // See if any of the relevant subregister liveranges is defined at this point.
310  for (const LiveInterval::SubRange &SR : LI.subranges()) {
311  if ((SR.LaneMask & UseMask) != 0 && SR.liveAt(BaseIndex))
312  return false;
313  }
314  return true;
315 }
316 
317 void VirtRegRewriter::rewrite() {
318  bool NoSubRegLiveness = !MRI->subRegLivenessEnabled();
319  SmallVector<unsigned, 8> SuperDeads;
320  SmallVector<unsigned, 8> SuperDefs;
321  SmallVector<unsigned, 8> SuperKills;
323 
324  // Here we have a SparseSet to hold which PhysRegs are actually encountered
325  // in the MF we are about to iterate over so that later when we call
326  // setPhysRegUsed, we are only doing it for physRegs that were actually found
327  // in the program and not for all of the possible physRegs for the given
328  // target architecture. If the target has a lot of physRegs, then for a small
329  // program there will be a significant compile time reduction here.
330  PhysRegs.clear();
331  PhysRegs.setUniverse(TRI->getNumRegs());
332 
333  // The function with uwtable should guarantee that the stack unwinder
334  // can unwind the stack to the previous frame. Thus, we can't apply the
335  // noreturn optimization if the caller function has uwtable attribute.
336  bool HasUWTable = MF->getFunction()->hasFnAttribute(Attribute::UWTable);
337 
338  for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end();
339  MBBI != MBBE; ++MBBI) {
340  DEBUG(MBBI->print(dbgs(), Indexes));
341  bool IsExitBB = MBBI->succ_empty();
343  MII = MBBI->instr_begin(), MIE = MBBI->instr_end(); MII != MIE;) {
344  MachineInstr *MI = MII;
345  ++MII;
346 
347  // Check if this instruction is a call to a noreturn function. If this
348  // is a call to noreturn function and we don't need the stack unwinding
349  // functionality (i.e. this function does not have uwtable attribute and
350  // the callee function has the nounwind attribute), then we can ignore
351  // the definitions set by this instruction.
352  if (!HasUWTable && IsExitBB && MI->isCall()) {
354  MOE = MI->operands_end(); MOI != MOE; ++MOI) {
355  MachineOperand &MO = *MOI;
356  if (!MO.isGlobal())
357  continue;
358  const Function *Func = dyn_cast<Function>(MO.getGlobal());
359  if (!Func || !Func->hasFnAttribute(Attribute::NoReturn) ||
360  // We need to keep correct unwind information
361  // even if the function will not return, since the
362  // runtime may need it.
364  continue;
365  NoReturnInsts.insert(MI);
366  break;
367  }
368  }
369 
371  MOE = MI->operands_end(); MOI != MOE; ++MOI) {
372  MachineOperand &MO = *MOI;
373 
374  // Make sure MRI knows about registers clobbered by regmasks.
375  if (MO.isRegMask())
376  MRI->addPhysRegsUsedFromRegMask(MO.getRegMask());
377 
378  // If we encounter a VirtReg or PhysReg then get at the PhysReg and add
379  // it to the physreg bitset. Later we use only the PhysRegs that were
380  // actually encountered in the MF to populate the MRI's used physregs.
381  if (MO.isReg() && MO.getReg())
382  PhysRegs.insert(
384  VRM->getPhys(MO.getReg()) :
385  MO.getReg());
386 
388  continue;
389  unsigned VirtReg = MO.getReg();
390  unsigned PhysReg = VRM->getPhys(VirtReg);
391  assert(PhysReg != VirtRegMap::NO_PHYS_REG &&
392  "Instruction uses unmapped VirtReg");
393  assert(!MRI->isReserved(PhysReg) && "Reserved register assignment");
394 
395  // Preserve semantics of sub-register operands.
396  unsigned SubReg = MO.getSubReg();
397  if (SubReg != 0) {
398  if (NoSubRegLiveness) {
399  // A virtual register kill refers to the whole register, so we may
400  // have to add <imp-use,kill> operands for the super-register. A
401  // partial redef always kills and redefines the super-register.
402  if (MO.readsReg() && (MO.isDef() || MO.isKill()))
403  SuperKills.push_back(PhysReg);
404 
405  if (MO.isDef()) {
406  // Also add implicit defs for the super-register.
407  if (MO.isDead())
408  SuperDeads.push_back(PhysReg);
409  else
410  SuperDefs.push_back(PhysReg);
411  }
412  } else {
413  if (MO.isUse()) {
414  if (readsUndefSubreg(MO))
415  // We need to add an <undef> flag if the subregister is
416  // completely undefined (and we are not adding super-register
417  // defs).
418  MO.setIsUndef(true);
419  } else if (!MO.isDead()) {
420  assert(MO.isDef());
421  // Things get tricky when we ran out of lane mask bits and
422  // merged multiple lanes into the overflow bit: In this case
423  // our subregister liveness tracking isn't precise and we can't
424  // know what subregister parts are undefined, fall back to the
425  // implicit super-register def then.
426  unsigned LaneMask = TRI->getSubRegIndexLaneMask(SubReg);
428  SuperDefs.push_back(PhysReg);
429  }
430  }
431 
432  // The <def,undef> flag only makes sense for sub-register defs, and
433  // we are substituting a full physreg. An <imp-use,kill> operand
434  // from the SuperKills list will represent the partial read of the
435  // super-register.
436  if (MO.isDef())
437  MO.setIsUndef(false);
438 
439  // PhysReg operands cannot have subregister indexes.
440  PhysReg = TRI->getSubReg(PhysReg, SubReg);
441  assert(PhysReg && "Invalid SubReg for physical register");
442  MO.setSubReg(0);
443  }
444  // Rewrite. Note we could have used MachineOperand::substPhysReg(), but
445  // we need the inlining here.
446  MO.setReg(PhysReg);
447  }
448 
449  // Add any missing super-register kills after rewriting the whole
450  // instruction.
451  while (!SuperKills.empty())
452  MI->addRegisterKilled(SuperKills.pop_back_val(), TRI, true);
453 
454  while (!SuperDeads.empty())
455  MI->addRegisterDead(SuperDeads.pop_back_val(), TRI, true);
456 
457  while (!SuperDefs.empty())
458  MI->addRegisterDefined(SuperDefs.pop_back_val(), TRI);
459 
460  DEBUG(dbgs() << "> " << *MI);
461 
462  // Finally, remove any identity copies.
463  if (MI->isIdentityCopy()) {
464  ++NumIdCopies;
465  DEBUG(dbgs() << "Deleting identity copy.\n");
466  if (Indexes)
467  Indexes->removeMachineInstrFromMaps(MI);
468  // It's safe to erase MI because MII has already been incremented.
469  MI->eraseFromParent();
470  }
471  }
472  }
473 
474  // Tell MRI about physical registers in use.
475  if (NoReturnInsts.empty()) {
477  RegI = PhysRegs.begin(), E = PhysRegs.end(); RegI != E; ++RegI)
478  if (!MRI->reg_nodbg_empty(*RegI))
479  MRI->setPhysRegUsed(*RegI);
480  } else {
482  I = PhysRegs.begin(), E = PhysRegs.end(); I != E; ++I) {
483  unsigned Reg = *I;
484  if (MRI->reg_nodbg_empty(Reg))
485  continue;
486  // Check if this register has a use that will impact the rest of the
487  // code. Uses in debug and noreturn instructions do not impact the
488  // generated code.
489  for (MachineInstr &It : MRI->reg_nodbg_instructions(Reg)) {
490  if (!NoReturnInsts.count(&It)) {
491  MRI->setPhysRegUsed(Reg);
492  break;
493  }
494  }
495  }
496  }
497 }
498 
bool hasPhys(unsigned virtReg) const
returns true if the specified virtual register is mapped to a physical register
Definition: VirtRegMap.h:92
void push_back(const T &Elt)
Definition: SmallVector.h:222
mop_iterator operands_end()
Definition: MachineInstr.h:290
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
const GlobalValue * getGlobal() const
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Definition: SmallPtrSet.h:78
STATISTIC(NumFunctions,"Total number of functions")
static unsigned index2VirtReg(unsigned Index)
index2VirtReg - Convert a 0-based index to a virtual register number.
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:114
unsigned getSimpleHint(unsigned VReg) const
getSimpleHint - Return the preferred register allocation hint, or 0 if a standard simple hint (Type =...
bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
static bool isImpreciseLaneMask(unsigned LaneMask)
Returns true if the given lane mask is imprecise.
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:588
void setIsUndef(bool Val=true)
bool isDead() const
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
size_type count(PtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
Definition: SmallPtrSet.h:276
void print(raw_ostream &OS, const Module *M=nullptr) const override
print - Print out the internal state of the pass.
Definition: VirtRegMap.cpp:120
bool isValid() const
Returns true if this iterator is not yet at the end.
A live range for subregisters.
Definition: LiveInterval.h:595
Instructions::iterator instr_iterator
bool empty() const
Definition: LiveInterval.h:353
aarch64 collect AArch64 Collect Linker Optimization Hint(LOH)"
unsigned getSize() const
getSize - Return the size of the register in bytes, which is also the size of a stack slot allocated ...
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:70
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
T LLVM_ATTRIBUTE_UNUSED_RESULT pop_back_val()
Definition: SmallVector.h:406
static unsigned addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:75
bool isReg() const
isReg - Tests if this is a MO_Register operand.
iterator_range< subrange_iterator > subranges()
Definition: LiveInterval.h:670
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
const TargetRegisterClass * getRegClass(unsigned Reg) const
getRegClass - Return the register class of the specified virtual register.
Reg
All possible values of the reg field in the ModR/M byte.
bool isUndef() const
Function must be in a unwind table.
Definition: Attributes.h:118
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
PrintReg - Helper class for printing registers on a raw_ostream.
const HexagonRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
bool isKill() const
int getObjectIndexBegin() const
Return the minimum frame object index.
SlotIndexes pass.
Definition: SlotIndexes.h:334
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Definition: SmallVector.h:57
Segments segments
Definition: LiveInterval.h:195
const char * getRegClassName(const TargetRegisterClass *Class) const
getRegClassName - Returns the name of the register class.
TargetInstrInfo - Interface to description of machine instruction set.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
unsigned getAlignment() const
getAlignment - Return the minimum required alignment for a register of this class.
Iterator that enumerates the sub-registers of a Reg and the associated sub-register indices...
bool hasPreferredPhys(unsigned VirtReg)
returns true if VirtReg is assigned to its preferred physreg.
Definition: VirtRegMap.cpp:84
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:264
Represent the analysis usage information of a pass.
Function doesn't unwind stack.
Definition: Attributes.h:96
Mark the function as not returning.
Definition: Attributes.h:95
bool hasKnownPreference(unsigned VirtReg)
returns true if VirtReg has a known preferred register.
Definition: VirtRegMap.cpp:93
unsigned getSubReg() const
int CreateSpillStackObject(uint64_t Size, unsigned Alignment)
Create a new statically sized stack object that represents a spill slot, returning a nonnegative iden...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool liveAt(SlotIndex index) const
Definition: LiveInterval.h:372
const_iterator begin() const
Definition: SparseSet.h:174
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:56
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
Definition: SmallPtrSet.h:299
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:861
Promote Memory to Register
Definition: Mem2Reg.cpp:58
bool isIdentityCopy() const
Return true is the instruction is an identity copy.
Definition: MachineInstr.h:795
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:123
void addRegisterDefined(unsigned Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:285
virtregrewriter
Definition: VirtRegMap.cpp:190
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Virtual Register Rewriter
Definition: VirtRegMap.cpp:190
Representation of each machine instruction.
Definition: MachineInstr.h:51
static bool isPhysicalRegister(unsigned Reg)
isPhysicalRegister - Return true if the specified register number is in the physical register namespa...
static char ID
Definition: VirtRegMap.h:70
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:217
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
void setReg(unsigned Reg)
Change the register this operand corresponds to.
#define I(x, y, z)
Definition: MD5.cpp:54
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:403
void setSubReg(unsigned subReg)
INITIALIZE_PASS_BEGIN(VirtRegRewriter,"virtregrewriter","Virtual Register Rewriter", false, false) INITIALIZE_PASS_END(VirtRegRewriter
unsigned getReg() const
getReg - Returns the register number.
Virtual Register false
Definition: VirtRegMap.cpp:190
mop_iterator operands_begin()
Definition: MachineInstr.h:289
MachineRegisterInfo & getRegInfo() const
Definition: VirtRegMap.h:85
char & VirtRegRewriterID
VirtRegRewriter pass.
Definition: VirtRegMap.cpp:181
BasicBlockListType::iterator iterator
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:38
void dump() const
Definition: VirtRegMap.cpp:142
#define DEBUG(X)
Definition: Debug.h:92
int assignVirt2StackSlot(unsigned virtReg)
create a mapping for the specifed virtual register to the next available stack slot ...
Definition: VirtRegMap.cpp:102
Primary interface to the complete machine description for the target machine.
bool addRegisterKilled(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
unsigned getPhys(unsigned virtReg) const
returns the physical register mapped to the specified virtual register
Definition: VirtRegMap.h:98
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register. ...
std::pair< unsigned, unsigned > getRegAllocationHint(unsigned VReg) const
getRegAllocationHint - Return the register allocation hint for the specified virtual register...
bool hasSubRanges() const
Returns true if subregister liveness information is available.
Definition: LiveInterval.h:696
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:92