LLVM  3.7.0
HexagonISelLowering.h
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1 //===-- HexagonISelLowering.h - Hexagon DAG Lowering Interface --*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that Hexagon uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
16 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
17 
18 #include "Hexagon.h"
20 #include "llvm/IR/CallingConv.h"
22 
23 namespace llvm {
24 
25 // Return true when the given node fits in a positive half word.
26 bool isPositiveHalfWord(SDNode *N);
27 
28  namespace HexagonISD {
29  enum NodeType : unsigned {
31 
33  CONST32_GP, // For marking data present in GP.
37 
41 
42  CALLv3, // A V3+ call instruction.
43  CALLv3nr, // A V3+ call instruction that doesn't return.
45 
46  RET_FLAG, // Return with a flag operand.
47  BR_JT, // Branch through jump table.
48  BARRIER, // Memory barrier.
49  JT, // Jump table.
50  CP, // Constant pool.
51 
78 
86 
88  };
89  }
90 
91  class HexagonSubtarget;
92 
94  int VarArgsFrameOffset; // Frame offset to start of varargs area.
95 
96  bool CanReturnSmallStruct(const Function* CalleeFn, unsigned& RetSize)
97  const;
98  void promoteLdStType(EVT VT, EVT PromotedLdStVT);
99  const HexagonTargetMachine &HTM;
100  const HexagonSubtarget &Subtarget;
101 
102  public:
103  explicit HexagonTargetLowering(const TargetMachine &TM,
104  const HexagonSubtarget &ST);
105 
106  /// IsEligibleForTailCallOptimization - Check whether the call is eligible
107  /// for tail call optimization. Targets which want to do tail call
108  /// optimization should implement this function.
110  CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet,
111  bool isCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs,
112  const SmallVectorImpl<SDValue> &OutVals,
113  const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const;
114 
115  bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
116  bool isTruncateFree(EVT VT1, EVT VT2) const override;
117 
118  bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
119 
120  // Should we expand the build vector with shuffles?
122  unsigned DefinedValues) const override;
123 
124  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
125  const char *getTargetNodeName(unsigned Opcode) const override;
130  SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
132  SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
133  SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const;
134  SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
136  bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl,
137  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const override;
140 
142  SmallVectorImpl<SDValue> &InVals) const override;
143  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
144  CallingConv::ID CallConv, bool isVarArg,
145  const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl,
147  const SmallVectorImpl<SDValue> &OutVals, SDValue Callee) const;
148 
149  SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
150  SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
151  SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
152  SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
155  SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
156 
157  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
158  bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs,
159  const SmallVectorImpl<SDValue> &OutVals, SDLoc dl,
160  SelectionDAG &DAG) const override;
161 
162  bool mayBeEmittedAsTailCall(CallInst *CI) const override;
164  MachineBasicBlock *BB) const override;
165 
166  SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
169  EVT VT) const override {
170  if (!VT.isVector())
171  return MVT::i1;
172  else
174  }
175 
177  SDValue &Base, SDValue &Offset,
179  SelectionDAG &DAG) const override;
180 
181  std::pair<unsigned, const TargetRegisterClass *>
183  StringRef Constraint, MVT VT) const override;
184 
185  unsigned
186  getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
187  if (ConstraintCode == "o")
189  else if (ConstraintCode == "v")
191  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
192  }
193 
194  // Intrinsics
196  /// isLegalAddressingMode - Return true if the addressing mode represented
197  /// by AM is legal for this target, for a load/store of the specified type.
198  /// The type may be VoidTy, in which case only return true if the addressing
199  /// mode is legal for a load/store of any legal type.
200  /// TODO: Handle pre/postinc as well.
201  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
202  Type *Ty, unsigned AS) const override;
203  bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
204 
205  /// isLegalICmpImmediate - Return true if the specified immediate is legal
206  /// icmp immediate, that is the target has icmp instructions which can
207  /// compare a register against the immediate without having to materialize
208  /// the immediate into a register.
209  bool isLegalICmpImmediate(int64_t Imm) const override;
210 
211  // Handling of atomic RMW instructions.
212  bool hasLoadLinkedStoreConditional() const override {
213  return true;
214  }
215  Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
216  AtomicOrdering Ord) const override;
218  Value *Addr, AtomicOrdering Ord) const override;
219  bool shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
220  bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
222  const override {
224  }
225  };
226 } // end namespace llvm
227 
228 #endif // Hexagon_ISELLOWERING_H
bool isFPImmLegal(const APFloat &Imm, EVT VT) const override
isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively...
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:724
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:104
bool shouldExpandAtomicLoadInIR(LoadInst *LI) const override
Returns true if the given (atomic) load should be expanded by the IR-level AtomicExpand pass into a l...
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
bool isLegalICmpImmediate(int64_t Imm) const override
isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register.
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
getPostIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mo...
SDValue LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals, const SmallVectorImpl< SDValue > &OutVals, SDValue Callee) const
LowerCallResult - Lower the result values of an ISD::CALL into the appropriate copies out of appropri...
CallInst - This class represents a function call, abstracting a target machine's calling convention...
SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array...
bool isPositiveHalfWord(SDNode *N)
LoadInst - an instruction for reading from memory.
Definition: Instructions.h:177
AtomicRMWInst - an instruction that atomically reads a memory location, combines it with another valu...
Definition: Instructions.h:674
SDValue LowerEXTRACT_VECTOR(SDValue Op, SelectionDAG &DAG) const
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
AtomicRMWExpansionKind
Enum that specifies what a AtomicRMWInst is expanded to, if at all.
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:115
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...
Value * emitStoreConditional(IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const override
Perform a store-conditional operation to Addr.
bool shouldExpandBuildVectorWithShuffles(EVT VT, unsigned DefinedValues) const override
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:517
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
AtomicOrdering
Definition: Instructions.h:38
StoreInst - an instruction for storing to memory.
Definition: Instructions.h:316
SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const
bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override
Return true if a truncation from Ty1 to Ty2 is permitted when deciding whether a call is in tail posi...
SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const
A self-contained host- and target-independent arbitrary-precision floating-point software implementat...
Definition: APFloat.h:122
MVT - Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:41
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override
Returns true if the given (atomic) store should be expanded by the IR-level AtomicExpand pass into an...
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const
bool mayBeEmittedAsTailCall(CallInst *CI) const override
Return true if the target may be able emit the call instruction as a tail call.
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
Return true if it's free to truncate a value of type Ty1 to type Ty2.
SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const
EVT - Extended Value Type.
Definition: ValueTypes.h:31
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements)
getVectorVT - Returns the EVT that represents a vector NumElements in length, where each element is o...
Definition: ValueTypes.h:70
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:179
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const
EVT getSetCCResultType(const DataLayout &, LLVMContext &C, EVT VT) const override
Return the ValueType of the result of SETCC operations.
AddrMode
ARM Addressing Modes.
Definition: ARMBaseInfo.h:235
Representation of each machine instruction.
Definition: MachineInstr.h:51
bool IsEligibleForTailCallOptimization(SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet, bool isCallerStructRet, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SmallVectorImpl< ISD::InputArg > &Ins, SelectionDAG &DAG) const
IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization...
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) const
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
#define N
SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const
Value * emitLoadLinked(IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const override
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type...
bool hasLoadLinkedStoreConditional() const override
True if AtomicExpandPass should use emitLoadLinked/emitStoreConditional and expand AtomicCmpXchgInst...
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const
AtomicRMWExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all...
LLVM Value Representation.
Definition: Value.h:69
Primary interface to the complete machine description for the target machine.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:40
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
LowerCall - Functions arguments are copied from virtual regs to (physical regs)/(stack frame)...
SDValue LowerINSERT_VECTOR(SDValue Op, SelectionDAG &DAG) const
SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, SDLoc dl, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array...
This file describes how to lower LLVM code to machine code.
HexagonTargetLowering(const TargetMachine &TM, const HexagonSubtarget &ST)
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:761
unsigned getVectorNumElements() const
getVectorNumElements - Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:225