LLVM  3.7.0
SIISelLowering.h
Go to the documentation of this file.
1 //===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief SI DAG Lowering interface definition
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_R600_SIISELLOWERING_H
16 #define LLVM_LIB_TARGET_R600_SIISELLOWERING_H
17 
18 #include "AMDGPUISelLowering.h"
19 #include "SIInstrInfo.h"
20 
21 namespace llvm {
22 
24  SDValue LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, SDLoc DL,
25  SDValue Chain, unsigned Offset, bool Signed) const;
26  SDValue LowerSampleIntrinsic(unsigned Opcode, const SDValue &Op,
27  SelectionDAG &DAG) const;
28  SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
29  SelectionDAG &DAG) const override;
30 
31  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
32  SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
33  SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
34  SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
35  SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
36  SDValue LowerFastFDIV(SDValue Op, SelectionDAG &DAG) const;
37  SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const;
38  SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const;
39  SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const;
40  SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG, bool Signed) const;
41  SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
42  SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
43  SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
44 
45  void adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
46 
47  SDValue performUCharToFloatCombine(SDNode *N,
48  DAGCombinerInfo &DCI) const;
49  SDValue performSHLPtrCombine(SDNode *N,
50  unsigned AS,
51  DAGCombinerInfo &DCI) const;
52  SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const;
53  SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const;
54  SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const;
55 
56  SDValue performMin3Max3Combine(SDNode *N, DAGCombinerInfo &DCI) const;
57  SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const;
58 
59  bool isLegalFlatAddressingMode(const AddrMode &AM) const;
60 public:
62 
63  bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
64  EVT /*VT*/) const override;
65 
66  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
67  unsigned AS) const override;
68 
69  bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS,
70  unsigned Align,
71  bool *IsFast) const override;
72 
73  EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
74  unsigned SrcAlign, bool IsMemset,
75  bool ZeroMemset,
76  bool MemcpyStrSrc,
77  MachineFunction &MF) const override;
78 
80  getPreferredVectorAction(EVT VT) const override;
81 
83  Type *Ty) const override;
84 
86  bool isVarArg,
88  SDLoc DL, SelectionDAG &DAG,
89  SmallVectorImpl<SDValue> &InVals) const override;
90 
92  MachineBasicBlock * BB) const override;
93  bool enableAggressiveFMAFusion(EVT VT) const override;
94  EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
95  EVT VT) const override;
96  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override;
97  bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
98  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
99  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
100  SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
102  SDNode *Node) const override;
103 
104  int32_t analyzeImmediate(const SDNode *N) const;
106  unsigned Reg, EVT VT) const override;
107  void legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const;
108 
109  MachineSDNode *wrapAddr64Rsrc(SelectionDAG &DAG, SDLoc DL, SDValue Ptr) const;
111  SDLoc DL,
112  SDValue Ptr,
113  uint32_t RsrcDword1,
114  uint64_t RsrcDword2And3) const;
116  SDLoc DL,
117  SDValue Ptr) const;
118 
119  std::pair<unsigned, const TargetRegisterClass *>
121  StringRef Constraint, MVT VT) const override;
122  SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, SDLoc DL, SDValue V) const;
123 };
124 
125 } // End namespace llvm
126 
127 #endif
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:104
void AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const override
Assign the register class depending on the number of bits set in the writemask.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
bool isFMAFasterThanFMulAndFAdd(EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
void legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const
Legalize target independent instructions (e.g.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
MachineSDNode * buildScratchRSRC(SelectionDAG &DAG, SDLoc DL, SDValue Ptr) const
MachineSDNode * buildRSRC(SelectionDAG &DAG, SDLoc DL, SDValue Ptr, uint32_t RsrcDword1, uint64_t RsrcDword2And3) const
Return a resource descriptor with the 'Add TID' bit enabled The TID (Thread ID) is multipled by the s...
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
int32_t analyzeImmediate(const SDNode *N) const
Analyze the possible immediate value Op.
Reg
All possible values of the reg field in the ModR/M byte.
bool isShuffleMaskLegal(const SmallVectorImpl< int > &, EVT) const override
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks.
bool enableAggressiveFMAFusion(EVT VT) const override
Return true if target always beneficiates from combining into FMA for a given value type...
SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const override
Helper function that adds Reg to the LiveIn list of the DAG's MachineFunction.
MVT - Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:41
SDNode * PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override
Fold the instructions after selecting them.
EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, MachineFunction &MF) const override
Returns the target specific optimal type for load and store operations as a result of memset...
MachineSDNode * wrapAddr64Rsrc(SelectionDAG &DAG, SDLoc DL, SDValue Ptr) const
SITargetLowering(TargetMachine &tm, const AMDGPUSubtarget &STI)
EVT - Extended Value Type.
Definition: ValueTypes.h:31
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT) const override
Return the preferred vector type legalization action.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:179
Interface definition of the TargetLowering class that is common to all AMD GPUs.
An SDNode that represents everything that will be needed to construct a MachineInstr.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
Class for arbitrary precision integers.
Definition: APInt.h:73
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align, bool *IsFast) const override
Determine if the target supports unaligned memory accesses.
Representation of each machine instruction.
Definition: MachineInstr.h:51
Interface definition for SIInstrInfo.
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, SDLoc DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array...
#define N
SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, SDLoc DL, SDValue V) const
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Primary interface to the complete machine description for the target machine.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:40
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Return true if it is beneficial to convert a load of a constant to just the constant itself...
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...