43 #define DEBUG_TYPE "misched"
47 cl::desc(
"Enable use of AA during MI DAG construction"));
54 bool IsPostRAFlag,
bool RemoveKillFlags,
56 :
ScheduleDAG(mf), MLI(mli), MFI(mf.getFrameInfo()), LIS(lis),
57 IsPostRA(IsPostRAFlag), RemoveKillFlags(RemoveKillFlags),
58 CanHandleTerminators(
false), FirstDbgValue(nullptr) {
59 assert((
IsPostRA ||
LIS) &&
"PreRA scheduling requires LiveIntervals");
62 "Virtual registers must be removed prior to PostRA scheduling");
72 if (
const Operator *U = dyn_cast<Operator>(V)) {
75 if (U->getOpcode() == Instruction::PtrToInt)
76 return U->getOperand(0);
83 if (U->getOpcode() != Instruction::Add ||
84 (!isa<ConstantInt>(U->getOperand(1)) &&
86 !isa<PHINode>(U->getOperand(1))))
112 if (!Visited.
insert(V).second)
122 Objects.
push_back(const_cast<Value *>(V));
124 }
while (!Working.
empty());
156 if (!PSV->isAliased(MFI)) {
170 for (
Value *V : Objs) {
196 unsigned regioninstrs) {
197 assert(bb ==
BB &&
"startBlock should set BB");
220 bool AllDepKnown = ExitMI &&
222 if (ExitMI && AllDepKnown) {
229 if (Reg == 0)
continue;
234 assert(!
IsPostRA &&
"Virtual register encountered after regalloc.");
242 assert(
Uses.
empty() &&
"Uses in set before adding deps?");
246 E = (*SI)->livein_end();
I != E; ++
I) {
258 assert(MO.
isDef() &&
"expect physreg def");
274 int UseOp =
I->OpIdx;
290 ST.adjustSchedDependency(SU, UseSU, Dep);
324 SDep Dep(SU, Kind, *Alias);
361 for (
bool isBegin = I == B; !isBegin; ) {
362 isBegin = (--
I) == B;
401 SUnit *DefSU = DefI->SU;
402 if (DefSU != SU && DefSU != &
ExitSU) {
432 assert(
LIS &&
"vreg dependencies requires LiveIntervals");
438 assert(VNI &&
"No value to read by operand");
502 for (
Value *V : Objs) {
570 assert ((MMOa->
getOffset() >= 0) &&
"Negative MachineMemOperand offset");
571 assert ((MMOb->
getOffset() >= 0) &&
"Negative MachineMemOperand offset");
590 SUnit *ExitSU,
unsigned *Depth,
592 if (!SUa || !SUb || SUb == ExitSU)
596 if (!Visited.
insert(SUb).second)
625 if (
I->isNormalMemoryOrBarrier())
636 std::set<SUnit *> &CheckList,
637 unsigned LatencyToLoad) {
644 for (std::set<SUnit *>::iterator
I = CheckList.begin(),
IE = CheckList.end();
650 Dep.
setLatency(((*I)->getInstr()->mayLoad()) ? LatencyToLoad : 0);
657 JE = (*I)->Succs.end(); J != JE; ++J)
658 if (J->isNormalMemoryOrBarrier())
669 SUnit *SUb, std::set<SUnit *> &RejectList,
670 unsigned TrueMemOrderLatency = 0,
671 bool isNormalMemory =
false) {
681 RejectList.insert(SUb);
682 DEBUG(
dbgs() <<
"\tReject chain dep between SU("
770 SUnit *BarrierChain =
nullptr, *AliasChain =
nullptr;
778 std::set<SUnit*> RejectMemNodes;
786 "Only BuildGraph should update Defs/Uses");
790 assert(
VRegDefs.
empty() &&
"Only BuildSchedGraph may access VRegDefs");
805 DbgValues.push_back(std::make_pair(DbgMI, MI));
814 assert(SU &&
"No SUnit mapped to this MI");
818 RPTracker->
recede(
nullptr, PDiff);
819 assert(RPTracker->
getPos() == std::prev(MII) &&
820 "RPTracker can't find MI");
825 "Cannot schedule terminators or labels!");
828 bool HasVRegDef =
false;
831 if (!MO.
isReg())
continue;
833 if (Reg == 0)
continue;
838 assert(!
IsPostRA &&
"Virtual register encountered!");
854 && (HasVRegDef || MI->
mayLoad())) {
869 unsigned TrueMemOrderLatency = MI->
mayStore() ? 1 : 0;
874 NonAliasMemDefs.
begin(), E = NonAliasMemDefs.
end();
I != E; ++
I) {
875 for (
unsigned i = 0, e =
I->second.size(); i != e; ++i) {
880 NonAliasMemUses.
begin(), E = NonAliasMemUses.
end();
I != E; ++
I) {
881 for (
unsigned i = 0, e =
I->second.size(); i != e; ++i) {
884 I->second[i]->addPred(Dep);
894 TrueMemOrderLatency);
895 RejectMemNodes.clear();
896 NonAliasMemDefs.
clear();
897 NonAliasMemUses.
clear();
903 unsigned ChainLatency = 0;
904 if (AliasChain->getInstr()->mayLoad())
905 ChainLatency = TrueMemOrderLatency;
907 RejectMemNodes, ChainLatency);
910 for (
unsigned k = 0, m =
PendingLoads.size(); k != m; ++k)
913 TrueMemOrderLatency);
915 AliasMemDefs.
begin(), E = AliasMemDefs.
end();
I != E; ++
I) {
916 for (
unsigned i = 0, e =
I->second.size(); i != e; ++i)
918 I->second[i], RejectMemNodes);
921 AliasMemUses.
begin(), E = AliasMemUses.
end();
I != E; ++
I) {
922 for (
unsigned i = 0, e =
I->second.size(); i != e; ++i)
924 I->second[i], RejectMemNodes, TrueMemOrderLatency);
927 TrueMemOrderLatency);
928 PendingLoads.clear();
929 AliasMemDefs.
clear();
930 AliasMemUses.
clear();
944 goto new_alias_chain;
951 bool ThisMayAlias = K->getInt();
959 ((ThisMayAlias) ? AliasMemDefs.
find(V) : NonAliasMemDefs.
find(V));
961 ((ThisMayAlias) ? AliasMemDefs.
end() : NonAliasMemDefs.
end());
963 for (
unsigned i = 0, e = I->second.
size(); i != e; ++i)
965 I->second[i], RejectMemNodes, 0,
true);
970 I->second.push_back(SU);
974 AliasMemDefs[V].
clear();
975 AliasMemDefs[V].push_back(SU);
978 NonAliasMemDefs[V].
clear();
979 NonAliasMemDefs[V].push_back(SU);
984 ((ThisMayAlias) ? AliasMemUses.
find(V) : NonAliasMemUses.
find(V));
986 ((ThisMayAlias) ? AliasMemUses.
end() : NonAliasMemUses.
end());
988 for (
unsigned i = 0, e = J->second.
size(); i != e; ++i)
990 J->second[i], RejectMemNodes,
991 TrueMemOrderLatency,
true);
998 for (
unsigned k = 0, m =
PendingLoads.size(); k != m; ++k)
1001 TrueMemOrderLatency);
1008 TrueMemOrderLatency);
1021 AliasMemDefs.
begin(), E = AliasMemDefs.
end();
I != E; ++
I)
1022 for (
unsigned i = 0, e =
I->second.size(); i != e; ++i)
1024 I->second[i], RejectMemNodes);
1033 J = Objs.
begin(), JE = Objs.
end(); J != JE; ++J) {
1035 bool ThisMayAlias = J->getInt();
1042 ((ThisMayAlias) ? AliasMemDefs.
find(V) : NonAliasMemDefs.
find(V));
1044 ((ThisMayAlias) ? AliasMemDefs.
end() : NonAliasMemDefs.
end());
1046 for (
unsigned i = 0, e = I->second.
size(); i != e; ++i)
1048 I->second[i], RejectMemNodes, 0,
true);
1050 AliasMemUses[V].push_back(SU);
1052 NonAliasMemUses[V].push_back(SU);
1058 if (MayAlias && AliasChain)
1084 E = (*SI)->livein_end();
I != E; ++
I) {
1098 bool NewKillState) {
1108 while (Begin != End) {
1110 if (!MO.isReg() || MO.isDef() || Reg != MO.getReg())
1122 if (MO.isInternalRead())
1125 if (MO.isKill() == NewKillState)
1127 MO.setIsKill(NewKillState);
1153 bool AllDead =
true;
1154 const unsigned SuperReg = MO.
getReg();
1180 unsigned Count = MBB->
size();
1194 if (!MO.
isReg())
continue;
1196 if (Reg == 0)
continue;
1197 if (!MO.
isDef())
continue;
1218 if (!killedRegs.test(Reg)) {
1234 if (MO.
isKill() != kill) {
1235 DEBUG(
dbgs() <<
"Fixing " << MO <<
" in ");
1242 while (++Begin != End)
1243 DEBUG(Begin->dump());
1247 killedRegs.set(Reg);
1266 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1301 std::vector<std::pair<const SUnit*, const SUnit*> > ConnectionPairs;
1305 unsigned ParentNodeID;
1306 unsigned SubInstrCount;
1308 RootData(
unsigned id): NodeID(
id),
1309 ParentNodeID(SchedDFSResult::InvalidSubtreeID),
1312 unsigned getSparseSetIndex()
const {
return NodeID; }
1327 return R.DFSNodeData[SU->
NodeNum].SubtreeID
1328 != SchedDFSResult::InvalidSubtreeID;
1334 R.DFSNodeData[SU->
NodeNum].InstrCount =
1353 unsigned InstrCount = R.DFSNodeData[SU->
NodeNum].InstrCount;
1355 PI = SU->
Preds.begin(), PE = SU->
Preds.end(); PI != PE; ++PI) {
1358 unsigned PredNum = PI->getSUnit()->NodeNum;
1359 if ((InstrCount - R.DFSNodeData[PredNum].InstrCount) < R.SubtreeLimit)
1363 if (R.DFSNodeData[PredNum].SubtreeID == PredNum) {
1366 if (RootSet[PredNum].ParentNodeID == SchedDFSResult::InvalidSubtreeID)
1367 RootSet[PredNum].ParentNodeID = SU->
NodeNum;
1369 else if (RootSet.
count(PredNum)) {
1374 RData.SubInstrCount += RootSet[PredNum].SubInstrCount;
1375 RootSet.
erase(PredNum);
1385 R.DFSNodeData[Succ->
NodeNum].InstrCount
1392 ConnectionPairs.push_back(std::make_pair(PredDep.
getSUnit(), Succ));
1401 &&
"number of roots should match trees");
1403 RI = RootSet.
begin(), RE = RootSet.
end(); RI != RE; ++RI) {
1404 unsigned TreeID = SubtreeClasses[RI->NodeID];
1405 if (RI->ParentNodeID != SchedDFSResult::InvalidSubtreeID)
1406 R.DFSTreeData[TreeID].ParentTreeID = SubtreeClasses[RI->ParentNodeID];
1407 R.DFSTreeData[TreeID].SubInstrCount = RI->SubInstrCount;
1413 R.SubtreeConnections.resize(SubtreeClasses.
getNumClasses());
1414 R.SubtreeConnectLevels.resize(SubtreeClasses.
getNumClasses());
1416 for (
unsigned Idx = 0, End = R.DFSNodeData.size(); Idx != End; ++Idx) {
1417 R.DFSNodeData[Idx].SubtreeID = SubtreeClasses[Idx];
1418 DEBUG(
dbgs() <<
" SU(" << Idx <<
") in tree "
1419 << R.DFSNodeData[Idx].SubtreeID <<
'\n');
1421 for (std::vector<std::pair<const SUnit*, const SUnit*> >::const_iterator
1422 I = ConnectionPairs.begin(), E = ConnectionPairs.end();
1424 unsigned PredTree = SubtreeClasses[
I->first->NodeNum];
1425 unsigned SuccTree = SubtreeClasses[
I->second->NodeNum];
1426 if (PredTree == SuccTree)
1428 unsigned Depth =
I->first->getDepth();
1438 bool CheckLimit =
true) {
1443 unsigned PredNum = PredSU->
NodeNum;
1444 if (R.DFSNodeData[PredNum].SubtreeID != PredNum)
1449 unsigned NumDataSucs = 0;
1451 SE = PredSU->Succs.end();
SI != SE; ++
SI) {
1453 if (++NumDataSucs >= 4)
1457 if (CheckLimit && R.DFSNodeData[PredNum].InstrCount > R.SubtreeLimit)
1459 R.DFSNodeData[PredNum].SubtreeID = Succ->
NodeNum;
1471 R.SubtreeConnections[FromTree];
1473 I = Connections.
begin(), E = Connections.
end();
I != E; ++
I) {
1474 if (
I->TreeID == ToTree) {
1475 I->Level = std::max(
I->Level, Depth);
1479 Connections.
push_back(SchedDFSResult::Connection(ToTree, Depth));
1480 FromTree = R.DFSTreeData[FromTree].ParentTreeID;
1481 }
while (FromTree != SchedDFSResult::InvalidSubtreeID);
1488 class SchedDAGReverseDFS {
1489 std::vector<std::pair<const SUnit*, SUnit::const_pred_iterator> > DFSStack;
1491 bool isComplete()
const {
return DFSStack.
empty(); }
1493 void follow(
const SUnit *SU) {
1494 DFSStack.push_back(std::make_pair(SU, SU->
Preds.begin()));
1496 void advance() { ++DFSStack.back().second; }
1498 const SDep *backtrack() {
1499 DFSStack.pop_back();
1500 return DFSStack.empty() ?
nullptr : std::prev(DFSStack.back().second);
1503 const SUnit *getCurr()
const {
return DFSStack.back().first; }
1508 return getCurr()->Preds.end();
1516 if (
SI->getKind() ==
SDep::Data && !
SI->getSUnit()->isBoundaryNode())
1535 SchedDAGReverseDFS DFS;
1540 while (DFS.getPred() != DFS.getPredEnd()) {
1541 const SDep &PredDep = *DFS.getPred();
1557 const SUnit *Child = DFS.getCurr();
1558 const SDep *PredDep = DFS.backtrack();
1562 if (DFS.isComplete())
1574 I = SubtreeConnections[SubtreeID].
begin(),
1575 E = SubtreeConnections[SubtreeID].
end();
I != E; ++
I) {
1576 SubtreeConnectLevels[
I->TreeID] =
1577 std::max(SubtreeConnectLevels[
I->TreeID],
I->Level);
1579 <<
" @" << SubtreeConnectLevels[
I->TreeID] <<
'\n');
1594 dbgs() << *
this <<
'\n';
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
iterator end()
Returns an iterator past this container.
SmallVector< PointerIntPair< ValueType, 1, bool >, 4 > UnderlyingObjectsVector
void push_back(const T &Elt)
static void getUnderlyingObjectsForInstr(const MachineInstr *MI, const MachineFrameInfo *MFI, UnderlyingObjectsVector &Objects, const DataLayout &DL)
getUnderlyingObjectsForInstr - If this machine instr has memory reference information and it can be t...
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
A parsed version of the target data layout string in and methods for querying it. ...
const_iterator end(StringRef path)
Get end iterator over path.
virtual void finishBlock()
finishBlock - Clean up after scheduling in the given block.
static void adjustChainDeps(AliasAnalysis *AA, const MachineFrameInfo *MFI, const DataLayout &DL, SUnit *SU, SUnit *ExitSU, std::set< SUnit * > &CheckList, unsigned LatencyToLoad)
This function assumes that "downward" from SU there exist tail/leaf of already constructed DAG...
bool joinPredSubtree(const SDep &PredDep, const SUnit *Succ, bool CheckLimit=true)
Join the predecessor subtree with the successor that is its DFS parent.
MachineBasicBlock::instr_iterator getBundleEnd(MachineInstr *MI)
Return an iterator pointing beyond the bundle containing MI.
PointerUnion< const Value *, const PseudoSourceValue * > ValueType
SlotIndex def
The index of the defining instruction.
iterator insert(const ValueT &Val)
Insert a new element at the tail of the subset list.
bool isSucc(SUnit *N)
isSucc - Test if node N is a successor of this node.
bool contains(const KeyT &Key) const
Returns true if this set contains an element identified by Key.
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds...
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
void init(unsigned N)
Initialize an array of N PressureDiffs.
Record a physical register access.
int getNumber() const
getNumber - MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a M...
std::pair< iterator, bool > insert(const ValueT &Val)
insert - Attempts to insert a new element.
void addVRegDefDeps(SUnit *SU, unsigned OperIdx)
addVRegDefDeps - Add register output and data dependencies from this SUnit to instructions that occur...
unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *DepMI) const
Output dependency latency of a pair of defs of the same register.
void buildSchedGraph(AliasAnalysis *AA, RegPressureTracker *RPTracker=nullptr, PressureDiffs *PDiffs=nullptr)
buildSchedGraph - Build SUnits from the MachineBasicBlock that we are input.
void dumpNode(const SUnit *SU) const override
size_type count(const KeyT &Key) const
count - Returns 1 if this set contains an element identified by Key, 0 otherwise. ...
std::vector< unsigned >::const_iterator livein_iterator
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
MachineInstr * getInstr() const
getInstr - Return the representative MachineInstr for this SUnit.
SlotIndex getInstructionIndex(const MachineInstr *instr) const
Returns the base index of the given instruction.
Represent the ILP of the subDAG rooted at a DAG node.
TargetSchedModel SchedModel
TargetSchedModel provides an interface to the machine model.
void init(const MCSchedModel &sm, const TargetSubtargetInfo *sti, const TargetInstrInfo *tii)
Initialize the machine model for instruction scheduling.
void compress()
compress - Compress equivalence classes by numbering them 0 .
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
bool CanHandleTerminators
The standard DAG builder does not normally include terminators as DAG nodes because it does not creat...
MachineBasicBlock::iterator begin() const
begin - Return an iterator to the top of the current scheduling region.
const_iterator begin(StringRef path)
Get begin iterator over path.
This class implements a map that also provides access to all stored values in a deterministic order...
const MCSchedClassDesc * getSchedClass(SUnit *SU) const
Resolve and cache a resolved scheduling class for an SUnit.
The two locations do not alias at all.
static cl::opt< bool > EnableAASchedMI("enable-aa-sched-mi", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Enable use of AA during MI DAG construction"))
void GetUnderlyingObjects(Value *V, SmallVectorImpl< Value * > &Objects, const DataLayout &DL, LoopInfo *LI=nullptr, unsigned MaxLookup=6)
This method is similar to GetUnderlyingObject except that it can look through phi and select instruct...
Kind
Kind - These are the different kinds of scheduling dependencies.
VNInfo - Value Number Information.
Instructions::iterator instr_iterator
unsigned NumRegionInstrs
Instructions in this region (distance(RegionBegin, RegionEnd)).
void addPhysRegDataDeps(SUnit *SU, unsigned OperIdx)
MO is an operand of SU's instruction that defines a physical register.
void fixupKills(MachineBasicBlock *MBB)
Fix register kill flags that scheduling has made invalid.
RangePair equal_range(const KeyT &K)
The bounds of the range of items sharing Key K.
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
SmallVector< SDep, 4 > Preds
virtual void startBlock(MachineBasicBlock *BB)
startBlock - Prepare to perform scheduling in the given block.
The two locations may or may not alias. This is the least precise result.
MachineBasicBlock::const_iterator getPos() const
Get the MI position corresponding to this register pressure.
bool empty() const
empty - Returns true if the set is empty.
A register anti-dependedence (aka WAR).
iterator_base< SparseMultiSet * > iterator
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
unsigned getNumSubtrees() const
The number of subtrees detected in this DAG.
std::vector< SUnit * > PendingLoads
PendingLoads - Remember where unknown loads are after the most recent unknown store, as we iterate.
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
MachineMemOperand - A description of a memory reference used in the backend.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineBasicBlock::iterator RegionEnd
The end of the range to be scheduled.
DenseMap< MachineInstr *, SUnit * > MISUnitMap
After calling BuildSchedGraph, each machine instruction in the current scheduling region is mapped to...
void addSchedBarrierDeps()
addSchedBarrierDeps - Add dependencies from instructions in the current list of instructions being sc...
const HexagonInstrInfo * TII
static void getUnderlyingObjects(const Value *V, SmallVectorImpl< Value * > &Objects, const DataLayout &DL)
getUnderlyingObjects - This is a wrapper around GetUnderlyingObjects and adds support for basic ptrto...
An individual mapping from virtual register number to SUnit.
T LLVM_ATTRIBUTE_UNUSED_RESULT pop_back_val()
void setInstr(MachineInstr *MI)
setInstr - Assign the instruction for the SUnit.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static bool hasDataSucc(const SUnit *SU)
static void advance(T &it, size_t Val)
virtual bool areMemAccessesTriviallyDisjoint(MachineInstr *MIa, MachineInstr *MIb, AliasAnalysis *AA=nullptr) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Regular data dependence (aka true-dependence).
const_iterator end() const
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Result of a LiveRange query.
std::vector< MachineBasicBlock * >::iterator succ_iterator
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
Number of individual test Apply this number of consecutive mutations to each input exit after the first new interesting input is found the minimized corpus is saved into the first input directory Number of jobs to run If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget's CPU.
const MachineFrameInfo * MFI
unsigned getNumOperands() const
Access to explicit operands of the instruction.
bool isIdentifiedObject(const Value *V)
isIdentifiedObject - Return true if this pointer refers to a distinct and identifiable object...
Compute the values of each DAG node for various metrics during DFS.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
A register output-dependence (aka WAW).
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
MachineBasicBlock::iterator RegionBegin
The beginning of the range to be scheduled.
void addVRegUseDeps(SUnit *SU, unsigned OperIdx)
addVRegUseDeps - Add a register data dependency if the instruction that defines the virtual register ...
void print(raw_ostream &OS) const
bool recede(SmallVectorImpl< unsigned > *LiveUses=nullptr, PressureDiff *PDiff=nullptr)
Recede across the previous instruction.
VReg2UseMap VRegUses
After calling BuildSchedGraph, each vreg used in the scheduling region is mapped to a set of SUnits...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
virtual void adjustSchedDependency(SUnit *def, SUnit *use, SDep &dep) const
bool IsPostRA
isPostRA flag indicates vregs cannot be present.
virtual void enterRegion(MachineBasicBlock *bb, MachineBasicBlock::iterator begin, MachineBasicBlock::iterator end, unsigned regioninstrs)
Initialize the scheduler state for the next scheduling region.
void visitPostorderNode(const SUnit *SU)
Called once for each node after all predecessors are visited.
iterator find(const KeyT &Key)
void visitPreorder(const SUnit *SU)
Initialize this node's instruction count.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
iterator erase(iterator I)
erase - Erases an existing element identified by a valid iterator.
const MachineBasicBlock * getParent() const
format_object< Ts...> format(const char *Fmt, const Ts &...Vals)
These are helper functions used to produce formatted output.
TargetInstrInfo - Interface to description of machine instruction set.
bool isDebugValue() const
static void toggleBundleKillFlag(MachineInstr *MI, unsigned Reg, bool NewKillState)
If we change a kill flag on the bundle instruction implicit register operands, then we also need to p...
SDep - Scheduling dependency.
bundle_iterator< MachineInstr, instr_iterator > iterator
initializer< Ty > init(const Ty &Val)
void clearBitsNotInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
clearBitsNotInMask - Clear a bit in this vector for every '0' bit in Mask.
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
size_type size() const
size - Returns the number of elements in the set.
void clearDAG()
clearDAG - clear the DAG state (between regions).
Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...
void print(raw_ostream &OS, bool SkipOpers=false) const
AAMDNodes getAAInfo() const
getAAInfo - Return the AA tags for the memory reference.
bool RemoveKillFlags
True if the DAG builder should remove kill flags (in preparation for rescheduling).
bool isReserved(unsigned PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
void visitCrossEdge(const SDep &PredDep, const SUnit *Succ)
Add a connection for cross edges.
Internal state used to compute SchedDFSResult.
int findRegisterDefOperandIdx(unsigned Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a def of the specified register or -1 if it is not found...
const MachineOperand & getOperand(unsigned i) const
Summarize the scheduling resources required for an instruction of a particular scheduling class...
void addConnection(unsigned FromTree, unsigned ToTree, unsigned Depth)
Called by finalize() to record a connection between trees.
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx=nullptr) const
Given the index of a register def operand, check if the register def is tied to a source operand...
void setUniverse(unsigned U)
Set the universe size which determines the largest key the set can hold.
AliasResult
The possible results of an alias query.
MCRegAliasIterator enumerates all registers aliasing Reg.
Track the current register pressure at some position in the instruction stream, and remember the high...
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore...
VReg2SUnitMap VRegDefs
Track the last instruction in this region defining each virtual register.
bool registerDefIsDead(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Returns true if the register is dead in this machine instruction.
List of PressureChanges in order of increasing, unique PSetID.
virtual void exitRegion()
Notify that the scheduler has finished scheduling the current region.
void setUniverse(unsigned U)
setUniverse - Set the universe size which determines the largest key the set can hold.
bool isInvariantLoad(AliasAnalysis *AA) const
Return true if this instruction is loading from a location whose value is invariant across the functi...
void clear()
Clears the set.
static bool MIsNeedChainEdge(AliasAnalysis *AA, const MachineFrameInfo *MFI, const DataLayout &DL, MachineInstr *MIa, MachineInstr *MIb)
This returns true if the two MIs need a chain edge betwee them.
succ_iterator succ_begin()
void join(unsigned a, unsigned b)
join - Join the equivalence classes of a and b.
bool isPointerTy() const
isPointerTy - True if this is an instance of PointerType.
MCSubRegIterator enumerates all sub-registers of Reg.
std::string & str()
Flushes the stream contents to the target string and returns the string's reference.
std::string getDAGName() const override
Return a label for the region of code covered by the DAG.
bool isVisited(const SUnit *SU) const
Return true if this node been visited by the DFS traversal.
const_iterator begin() const
ProcResIter getWriteProcResEnd(const MCSchedClassDesc *SC) const
void setIsKill(bool Val=true)
iterator find(const KeyT &Key)
Find an element by its key.
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
An unknown scheduling barrier.
std::string getFullName() const
getFullName - Return a formatted string to identify this block and its parent function.
void addPhysRegDeps(SUnit *SU, unsigned OperIdx)
addPhysRegDeps - Add register dependencies (data, anti, and output) from this SUnit to following inst...
bool hasInstrSchedModel() const
Return true if this machine model includes an instruction-level scheduling model. ...
Representation for a specific memory location.
std::string getGraphNodeLabel(const SUnit *SU) const override
Return a label for a DAG node that points to an instruction.
bool memoperands_empty() const
bool toggleKillFlag(MachineInstr *MI, MachineOperand &MO)
Toggle a register operand kill flag.
bool hasTailCall() const
Returns true if the function contains a tail call.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
const MCProcResourceDesc * getProcResource(unsigned PIdx) const
Get a processor resource by ID for convenience.
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
void compute(ArrayRef< SUnit > SUnits)
Compute various metrics for the DAG with given roots.
const DataLayout * getDataLayout() const
Deprecated in 3.7, will be removed in 3.8.
virtual AliasResult alias(const MemoryLocation &LocA, const MemoryLocation &LocB)
Alias Queries...
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
This is a utility class that provides an abstraction for the common functionality between Instruction...
Type * getType() const
All values are typed, get the type of this value.
bool test(unsigned Idx) const
Reg2SUnitsMap Defs
State internal to DAG building.
void eraseAll(const KeyT &K)
Erase all elements with the given key.
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
CHAIN = SC CHAIN, Imm128 - System call.
static unsigned iterateChainSucc(AliasAnalysis *AA, const MachineFrameInfo *MFI, const DataLayout &DL, SUnit *SUa, SUnit *SUb, SUnit *ExitSU, unsigned *Depth, SmallPtrSetImpl< const SUnit * > &Visited)
This recursive function iterates over chain deps of SUb looking for "latest" node that needs a chain ...
Nonvolatile load/Store instructions that may alias.
LiveInterval & getInterval(unsigned Reg)
bool isTransient() const
Return true if this is a transient instruction that is either very likely to be eliminated during reg...
unsigned Length
Length may either correspond to depth or height, depending on direction, and cycles or nodes dependin...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
BUNDLE - This instruction represents an instruction bundle.
const Value * getValue() const
getValue - Return the base address of the memory access.
PseudoSourceValue - Special value supplied for machine level alias analysis.
bool isIntegerTy() const
isIntegerTy - True if this is an instance of IntegerType.
MachineBasicBlock::iterator end() const
end - Return an iterator to the bottom of the current scheduling region.
ScheduleDAGInstrs(MachineFunction &mf, const MachineLoopInfo *mli, bool IsPostRAFlag, bool RemoveKillFlags=false, LiveIntervals *LIS=nullptr)
bool isBoundaryNode() const
Boundary nodes are placeholders for the boundary of the scheduling region.
void visitPostorderEdge(const SDep &PredDep, const SUnit *Succ)
Called once for each tree edge after calling visitPostOrderNode on the predecessor.
void setLatency(unsigned Lat)
setLatency - Set the latency for this edge.
**iterator erase(iterator I)
unsigned getOpcode() const
Return the opcode for this Instruction or ConstantExpr.
TargetSubtargetInfo - Generic base class for all target subtargets.
SUnit * getSUnit(MachineInstr *MI) const
getSUnit - Return an existing SUnit for this MI, or NULL.
Representation of each machine instruction.
void finalize()
Set each node's subtree ID to the representative ID and record connections between trees...
static bool isPhysicalRegister(unsigned Reg)
isPhysicalRegister - Return true if the specified register number is in the physical register namespa...
bool hasOneDef(unsigned RegNo) const
hasOneDef - Return true if there is exactly one instruction defining the specified register...
const TargetRegisterInfo * TRI
static cl::opt< bool > UseTBAA("use-tbaa-in-sched-mi", cl::Hidden, cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"))
iterator find(const KeyT &Key)
find - Find an element by its key.
bool isCall(QueryType Type=AnyInBundle) const
static void addChainDependency(AliasAnalysis *AA, const MachineFrameInfo *MFI, const DataLayout &DL, SUnit *SUa, SUnit *SUb, std::set< SUnit * > &RejectList, unsigned TrueMemOrderLatency=0, bool isNormalMemory=false)
Check whether two objects need a chain edge, if so, add it otherwise remember the rejected SU...
Kind getKind() const
getKind - Return an enum value representing the kind of the dependence.
const TargetInstrInfo * TII
raw_ostream & operator<<(raw_ostream &OS, const APInt &I)
unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx, const MachineInstr *UseMI, unsigned UseOperIdx) const
Compute operand latency based on the available machine model.
void clear()
clear - Clears the set.
unsigned getReg() const
getReg - Returns the register number.
SUnit * newSUnit(MachineInstr *MI)
newSUnit - Creates a new SUnit and return a ptr to it.
bool isCommutable(QueryType Type=IgnoreBundle) const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged.
const ARM::ArchExtKind Kind
bool addPred(const SDep &D, bool Required=true)
addPred - This adds the specified edge as a pred of the current node if not already.
A raw_ostream that writes to an std::string.
void startBlockForKills(MachineBasicBlock *BB)
PostRA helper for rewriting kill flags.
virtual const TargetInstrInfo * getInstrInfo() const
LLVM Value Representation.
int64_t getOffset() const
getOffset - For normal values, this is a byte offset added to the base address.
void initSUnits()
Create an SUnit for each real instruction, numbered in top-down toplological order.
unsigned getNumClasses() const
getNumClasses - Return the number of equivalence classes after compress() was called.
SmallVector< SDep, 4 > Succs
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
Arbitrary strong DAG edge (no real dependence).
void scheduleTree(unsigned SubtreeID)
Scheduler callback to update SubtreeConnectLevels when a tree is initially scheduled.
uint64_t getSize() const
getSize - Return the size in bytes of the memory reference.
This class implements an extremely fast bulk output stream that can only output to a stream...
MachineInstr * FirstDbgValue
static bool isGlobalMemoryObject(AliasAnalysis *AA, MachineInstr *MI)
Return true if MI is an instruction we are unable to reason about (like a call or something with unmo...
MachineBasicBlock * BB
State specific to the current scheduling region.
bool empty() const
Returns true if the set is empty.
static bool isUnsafeMemoryObject(MachineInstr *MI, const MachineFrameInfo *MFI, const DataLayout &DL)
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register. ...
VNInfo * valueIn() const
Return the value that is live-in to the instruction.
static bool isVolatile(Instruction *Inst)
MachineRegisterInfo & MRI
std::vector< SUnit > SUnits
SchedDFSImpl(SchedDFSResult &r)
ProcResIter getWriteProcResBegin(const MCSchedClassDesc *SC) const
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
static const Value * getUnderlyingObjectFromInt(const Value *V)
getUnderlyingObjectFromInt - This is the function that does the work of looking through basic ptrtoin...
std::pair< iterator, iterator > RangePair
BitVector LiveRegs
Set of live physical registers for updating kill flags.
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
LiveIntervals * LIS
Live Intervals provides reaching defs in preRA scheduling.
SUnit - Scheduling unit. This is a node in the scheduling DAG.
virtual bool useAA() const
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.).
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.