LLVM  3.7.0
MachineBasicBlock.cpp
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1 //===-- llvm/CodeGen/MachineBasicBlock.cpp ----------------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Collect the sequence of machine instructions for a basic block.
11 //
12 //===----------------------------------------------------------------------===//
13 
15 #include "llvm/ADT/SmallPtrSet.h"
16 #include "llvm/ADT/SmallString.h"
25 #include "llvm/IR/BasicBlock.h"
26 #include "llvm/IR/DataLayout.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/MC/MCContext.h"
30 #include "llvm/Support/Debug.h"
36 #include <algorithm>
37 using namespace llvm;
38 
39 #define DEBUG_TYPE "codegen"
40 
41 MachineBasicBlock::MachineBasicBlock(MachineFunction &mf, const BasicBlock *bb)
42  : BB(bb), Number(-1), xParent(&mf), Alignment(0), IsLandingPad(false),
43  AddressTaken(false), CachedMCSymbol(nullptr) {
44  Insts.Parent = this;
45 }
46 
47 MachineBasicBlock::~MachineBasicBlock() {
48 }
49 
50 /// getSymbol - Return the MCSymbol for this basic block.
51 ///
53  if (!CachedMCSymbol) {
54  const MachineFunction *MF = getParent();
55  MCContext &Ctx = MF->getContext();
56  const char *Prefix = Ctx.getAsmInfo()->getPrivateLabelPrefix();
57  CachedMCSymbol = Ctx.getOrCreateSymbol(Twine(Prefix) + "BB" +
58  Twine(MF->getFunctionNumber()) +
59  "_" + Twine(getNumber()));
60  }
61 
62  return CachedMCSymbol;
63 }
64 
65 
67  MBB.print(OS);
68  return OS;
69 }
70 
71 /// addNodeToList (MBB) - When an MBB is added to an MF, we need to update the
72 /// parent pointer of the MBB, the MBB numbering, and any instructions in the
73 /// MBB to be on the right operand list for registers.
74 ///
75 /// MBBs start out as #-1. When a MBB is added to a MachineFunction, it
76 /// gets the next available unique MBB number. If it is removed from a
77 /// MachineFunction, it goes back to being #-1.
79  MachineFunction &MF = *N->getParent();
80  N->Number = MF.addToMBBNumbering(N);
81 
82  // Make sure the instructions have their operands in the reginfo lists.
83  MachineRegisterInfo &RegInfo = MF.getRegInfo();
85  I = N->instr_begin(), E = N->instr_end(); I != E; ++I)
86  I->AddRegOperandsToUseLists(RegInfo);
87 }
88 
90  N->getParent()->removeFromMBBNumbering(N->Number);
91  N->Number = -1;
92 }
93 
94 
95 /// addNodeToList (MI) - When we add an instruction to a basic block
96 /// list, we update its parent pointer and add its operands from reg use/def
97 /// lists if appropriate.
99  assert(!N->getParent() && "machine instruction already in a basic block");
100  N->setParent(Parent);
101 
102  // Add the instruction's register operands to their corresponding
103  // use/def lists.
104  MachineFunction *MF = Parent->getParent();
105  N->AddRegOperandsToUseLists(MF->getRegInfo());
106 }
107 
108 /// removeNodeFromList (MI) - When we remove an instruction from a basic block
109 /// list, we update its parent pointer and remove its operands from reg use/def
110 /// lists if appropriate.
112  assert(N->getParent() && "machine instruction not in a basic block");
113 
114  // Remove from the use/def lists.
115  if (MachineFunction *MF = N->getParent()->getParent())
116  N->RemoveRegOperandsFromUseLists(MF->getRegInfo());
117 
118  N->setParent(nullptr);
119 }
120 
121 /// transferNodesFromList (MI) - When moving a range of instructions from one
122 /// MBB list to another, we need to update the parent pointers and the use/def
123 /// lists.
128  assert(Parent->getParent() == fromList.Parent->getParent() &&
129  "MachineInstr parent mismatch!");
130 
131  // Splice within the same MBB -> no change.
132  if (Parent == fromList.Parent) return;
133 
134  // If splicing between two blocks within the same function, just update the
135  // parent pointers.
136  for (; first != last; ++first)
137  first->setParent(Parent);
138 }
139 
141  assert(!MI->getParent() && "MI is still in a block!");
142  Parent->getParent()->DeleteMachineInstr(MI);
143 }
144 
147  while (I != E && I->isPHI())
148  ++I;
149  assert((I == E || !I->isInsideBundle()) &&
150  "First non-phi MI cannot be inside a bundle!");
151  return I;
152 }
153 
156  iterator E = end();
157  while (I != E && (I->isPHI() || I->isPosition() || I->isDebugValue()))
158  ++I;
159  // FIXME: This needs to change if we wish to bundle labels / dbg_values
160  // inside the bundle.
161  assert((I == E || !I->isInsideBundle()) &&
162  "First non-phi / non-label instruction is inside a bundle!");
163  return I;
164 }
165 
167  iterator B = begin(), E = end(), I = E;
168  while (I != B && ((--I)->isTerminator() || I->isDebugValue()))
169  ; /*noop */
170  while (I != E && !I->isTerminator())
171  ++I;
172  return I;
173 }
174 
176  instr_iterator B = instr_begin(), E = instr_end(), I = E;
177  while (I != B && ((--I)->isTerminator() || I->isDebugValue()))
178  ; /*noop */
179  while (I != E && !I->isTerminator())
180  ++I;
181  return I;
182 }
183 
185  // Skip over begin-of-block dbg_value instructions.
186  iterator I = begin(), E = end();
187  while (I != E && I->isDebugValue())
188  ++I;
189  return I;
190 }
191 
193  // Skip over end-of-block dbg_value instructions.
195  while (I != B) {
196  --I;
197  // Return instruction that starts a bundle.
198  if (I->isDebugValue() || I->isInsideBundle())
199  continue;
200  return I;
201  }
202  // The block is all debug values.
203  return end();
204 }
205 
207  // A block with a landing pad successor only has one other successor.
208  if (succ_size() > 2)
209  return nullptr;
210  for (const_succ_iterator I = succ_begin(), E = succ_end(); I != E; ++I)
211  if ((*I)->isLandingPad())
212  return *I;
213  return nullptr;
214 }
215 
216 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
218  print(dbgs());
219 }
220 #endif
221 
223  if (const BasicBlock *LBB = getBasicBlock())
224  return LBB->getName();
225  else
226  return "(null)";
227 }
228 
229 /// Return a hopefully unique identifier for this block.
230 std::string MachineBasicBlock::getFullName() const {
231  std::string Name;
232  if (getParent())
233  Name = (getParent()->getName() + ":").str();
234  if (getBasicBlock())
235  Name += getBasicBlock()->getName();
236  else
237  Name += ("BB" + Twine(getNumber())).str();
238  return Name;
239 }
240 
242  const MachineFunction *MF = getParent();
243  if (!MF) {
244  OS << "Can't print out MachineBasicBlock because parent MachineFunction"
245  << " is null\n";
246  return;
247  }
248  const Function *F = MF->getFunction();
249  const Module *M = F ? F->getParent() : nullptr;
250  ModuleSlotTracker MST(M);
251  print(OS, MST, Indexes);
252 }
253 
255  SlotIndexes *Indexes) const {
256  const MachineFunction *MF = getParent();
257  if (!MF) {
258  OS << "Can't print out MachineBasicBlock because parent MachineFunction"
259  << " is null\n";
260  return;
261  }
262 
263  if (Indexes)
264  OS << Indexes->getMBBStartIdx(this) << '\t';
265 
266  OS << "BB#" << getNumber() << ": ";
267 
268  const char *Comma = "";
269  if (const BasicBlock *LBB = getBasicBlock()) {
270  OS << Comma << "derived from LLVM BB ";
271  LBB->printAsOperand(OS, /*PrintType=*/false, MST);
272  Comma = ", ";
273  }
274  if (isLandingPad()) { OS << Comma << "EH LANDING PAD"; Comma = ", "; }
275  if (hasAddressTaken()) { OS << Comma << "ADDRESS TAKEN"; Comma = ", "; }
276  if (Alignment)
277  OS << Comma << "Align " << Alignment << " (" << (1u << Alignment)
278  << " bytes)";
279 
280  OS << '\n';
281 
282  const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
283  if (!livein_empty()) {
284  if (Indexes) OS << '\t';
285  OS << " Live Ins:";
286  for (livein_iterator I = livein_begin(),E = livein_end(); I != E; ++I)
287  OS << ' ' << PrintReg(*I, TRI);
288  OS << '\n';
289  }
290  // Print the preds of this block according to the CFG.
291  if (!pred_empty()) {
292  if (Indexes) OS << '\t';
293  OS << " Predecessors according to CFG:";
294  for (const_pred_iterator PI = pred_begin(), E = pred_end(); PI != E; ++PI)
295  OS << " BB#" << (*PI)->getNumber();
296  OS << '\n';
297  }
298 
299  for (const_instr_iterator I = instr_begin(); I != instr_end(); ++I) {
300  if (Indexes) {
301  if (Indexes->hasIndex(I))
302  OS << Indexes->getInstructionIndex(I);
303  OS << '\t';
304  }
305  OS << '\t';
306  if (I->isInsideBundle())
307  OS << " * ";
308  I->print(OS, MST);
309  }
310 
311  // Print the successors of this block according to the CFG.
312  if (!succ_empty()) {
313  if (Indexes) OS << '\t';
314  OS << " Successors according to CFG:";
315  for (const_succ_iterator SI = succ_begin(), E = succ_end(); SI != E; ++SI) {
316  OS << " BB#" << (*SI)->getNumber();
317  if (!Weights.empty())
318  OS << '(' << *getWeightIterator(SI) << ')';
319  }
320  OS << '\n';
321  }
322 }
323 
324 void MachineBasicBlock::printAsOperand(raw_ostream &OS, bool /*PrintType*/) const {
325  OS << "BB#" << getNumber();
326 }
327 
329  std::vector<unsigned>::iterator I =
330  std::find(LiveIns.begin(), LiveIns.end(), Reg);
331  if (I != LiveIns.end())
332  LiveIns.erase(I);
333 }
334 
335 bool MachineBasicBlock::isLiveIn(unsigned Reg) const {
336  livein_iterator I = std::find(livein_begin(), livein_end(), Reg);
337  return I != livein_end();
338 }
339 
340 unsigned
341 MachineBasicBlock::addLiveIn(unsigned PhysReg, const TargetRegisterClass *RC) {
342  assert(getParent() && "MBB must be inserted in function");
343  assert(TargetRegisterInfo::isPhysicalRegister(PhysReg) && "Expected physreg");
344  assert(RC && "Register class is required");
345  assert((isLandingPad() || this == &getParent()->front()) &&
346  "Only the entry block and landing pads can have physreg live ins");
347 
348  bool LiveIn = isLiveIn(PhysReg);
349  iterator I = SkipPHIsAndLabels(begin()), E = end();
352 
353  // Look for an existing copy.
354  if (LiveIn)
355  for (;I != E && I->isCopy(); ++I)
356  if (I->getOperand(1).getReg() == PhysReg) {
357  unsigned VirtReg = I->getOperand(0).getReg();
358  if (!MRI.constrainRegClass(VirtReg, RC))
359  llvm_unreachable("Incompatible live-in register class.");
360  return VirtReg;
361  }
362 
363  // No luck, create a virtual register.
364  unsigned VirtReg = MRI.createVirtualRegister(RC);
365  BuildMI(*this, I, DebugLoc(), TII.get(TargetOpcode::COPY), VirtReg)
366  .addReg(PhysReg, RegState::Kill);
367  if (!LiveIn)
368  addLiveIn(PhysReg);
369  return VirtReg;
370 }
371 
373  getParent()->splice(NewAfter, this);
374 }
375 
377  MachineFunction::iterator BBI = NewBefore;
378  getParent()->splice(++BBI, this);
379 }
380 
383  // A block with no successors has no concerns with fall-through edges.
384  if (this->succ_empty()) return;
385 
386  MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
388  DebugLoc dl; // FIXME: this is nowhere
389  bool B = TII->AnalyzeBranch(*this, TBB, FBB, Cond);
390  (void) B;
391  assert(!B && "UpdateTerminators requires analyzable predecessors!");
392  if (Cond.empty()) {
393  if (TBB) {
394  // The block has an unconditional branch. If its successor is now
395  // its layout successor, delete the branch.
396  if (isLayoutSuccessor(TBB))
397  TII->RemoveBranch(*this);
398  } else {
399  // The block has an unconditional fallthrough. If its successor is not
400  // its layout successor, insert a branch. First we have to locate the
401  // only non-landing-pad successor, as that is the fallthrough block.
402  for (succ_iterator SI = succ_begin(), SE = succ_end(); SI != SE; ++SI) {
403  if ((*SI)->isLandingPad())
404  continue;
405  assert(!TBB && "Found more than one non-landing-pad successor!");
406  TBB = *SI;
407  }
408 
409  // If there is no non-landing-pad successor, the block has no
410  // fall-through edges to be concerned with.
411  if (!TBB)
412  return;
413 
414  // Finally update the unconditional successor to be reached via a branch
415  // if it would not be reached by fallthrough.
416  if (!isLayoutSuccessor(TBB))
417  TII->InsertBranch(*this, TBB, nullptr, Cond, dl);
418  }
419  } else {
420  if (FBB) {
421  // The block has a non-fallthrough conditional branch. If one of its
422  // successors is its layout successor, rewrite it to a fallthrough
423  // conditional branch.
424  if (isLayoutSuccessor(TBB)) {
425  if (TII->ReverseBranchCondition(Cond))
426  return;
427  TII->RemoveBranch(*this);
428  TII->InsertBranch(*this, FBB, nullptr, Cond, dl);
429  } else if (isLayoutSuccessor(FBB)) {
430  TII->RemoveBranch(*this);
431  TII->InsertBranch(*this, TBB, nullptr, Cond, dl);
432  }
433  } else {
434  // Walk through the successors and find the successor which is not
435  // a landing pad and is not the conditional branch destination (in TBB)
436  // as the fallthrough successor.
437  MachineBasicBlock *FallthroughBB = nullptr;
438  for (succ_iterator SI = succ_begin(), SE = succ_end(); SI != SE; ++SI) {
439  if ((*SI)->isLandingPad() || *SI == TBB)
440  continue;
441  assert(!FallthroughBB && "Found more than one fallthrough successor.");
442  FallthroughBB = *SI;
443  }
444  if (!FallthroughBB && canFallThrough()) {
445  // We fallthrough to the same basic block as the conditional jump
446  // targets. Remove the conditional jump, leaving unconditional
447  // fallthrough.
448  // FIXME: This does not seem like a reasonable pattern to support, but it
449  // has been seen in the wild coming out of degenerate ARM test cases.
450  TII->RemoveBranch(*this);
451 
452  // Finally update the unconditional successor to be reached via a branch
453  // if it would not be reached by fallthrough.
454  if (!isLayoutSuccessor(TBB))
455  TII->InsertBranch(*this, TBB, nullptr, Cond, dl);
456  return;
457  }
458 
459  // The block has a fallthrough conditional branch.
460  if (isLayoutSuccessor(TBB)) {
461  if (TII->ReverseBranchCondition(Cond)) {
462  // We can't reverse the condition, add an unconditional branch.
463  Cond.clear();
464  TII->InsertBranch(*this, FallthroughBB, nullptr, Cond, dl);
465  return;
466  }
467  TII->RemoveBranch(*this);
468  TII->InsertBranch(*this, FallthroughBB, nullptr, Cond, dl);
469  } else if (!isLayoutSuccessor(FallthroughBB)) {
470  TII->RemoveBranch(*this);
471  TII->InsertBranch(*this, TBB, FallthroughBB, Cond, dl);
472  }
473  }
474  }
475 }
476 
478 
479  // If we see non-zero value for the first time it means we actually use Weight
480  // list, so we fill all Weights with 0's.
481  if (weight != 0 && Weights.empty())
482  Weights.resize(Successors.size());
483 
484  if (weight != 0 || !Weights.empty())
485  Weights.push_back(weight);
486 
487  Successors.push_back(succ);
488  succ->addPredecessor(this);
489  }
490 
492  succ->removePredecessor(this);
493  succ_iterator I = std::find(Successors.begin(), Successors.end(), succ);
494  assert(I != Successors.end() && "Not a current successor!");
495 
496  // If Weight list is empty it means we don't use it (disabled optimization).
497  if (!Weights.empty()) {
498  weight_iterator WI = getWeightIterator(I);
499  Weights.erase(WI);
500  }
501 
502  Successors.erase(I);
503 }
504 
507  assert(I != Successors.end() && "Not a current successor!");
508 
509  // If Weight list is empty it means we don't use it (disabled optimization).
510  if (!Weights.empty()) {
511  weight_iterator WI = getWeightIterator(I);
512  Weights.erase(WI);
513  }
514 
515  (*I)->removePredecessor(this);
516  return Successors.erase(I);
517 }
518 
520  MachineBasicBlock *New) {
521  if (Old == New)
522  return;
523 
524  succ_iterator E = succ_end();
525  succ_iterator NewI = E;
526  succ_iterator OldI = E;
527  for (succ_iterator I = succ_begin(); I != E; ++I) {
528  if (*I == Old) {
529  OldI = I;
530  if (NewI != E)
531  break;
532  }
533  if (*I == New) {
534  NewI = I;
535  if (OldI != E)
536  break;
537  }
538  }
539  assert(OldI != E && "Old is not a successor of this block");
540  Old->removePredecessor(this);
541 
542  // If New isn't already a successor, let it take Old's place.
543  if (NewI == E) {
544  New->addPredecessor(this);
545  *OldI = New;
546  return;
547  }
548 
549  // New is already a successor.
550  // Update its weight instead of adding a duplicate edge.
551  if (!Weights.empty()) {
552  weight_iterator OldWI = getWeightIterator(OldI);
553  *getWeightIterator(NewI) += *OldWI;
554  Weights.erase(OldWI);
555  }
556  Successors.erase(OldI);
557 }
558 
559 void MachineBasicBlock::addPredecessor(MachineBasicBlock *pred) {
560  Predecessors.push_back(pred);
561 }
562 
563 void MachineBasicBlock::removePredecessor(MachineBasicBlock *pred) {
564  pred_iterator I = std::find(Predecessors.begin(), Predecessors.end(), pred);
565  assert(I != Predecessors.end() && "Pred is not a predecessor of this block!");
566  Predecessors.erase(I);
567 }
568 
570  if (this == fromMBB)
571  return;
572 
573  while (!fromMBB->succ_empty()) {
574  MachineBasicBlock *Succ = *fromMBB->succ_begin();
575  uint32_t Weight = 0;
576 
577  // If Weight list is empty it means we don't use it (disabled optimization).
578  if (!fromMBB->Weights.empty())
579  Weight = *fromMBB->Weights.begin();
580 
581  addSuccessor(Succ, Weight);
582  fromMBB->removeSuccessor(Succ);
583  }
584 }
585 
586 void
588  if (this == fromMBB)
589  return;
590 
591  while (!fromMBB->succ_empty()) {
592  MachineBasicBlock *Succ = *fromMBB->succ_begin();
593  uint32_t Weight = 0;
594  if (!fromMBB->Weights.empty())
595  Weight = *fromMBB->Weights.begin();
596  addSuccessor(Succ, Weight);
597  fromMBB->removeSuccessor(Succ);
598 
599  // Fix up any PHI nodes in the successor.
601  ME = Succ->instr_end(); MI != ME && MI->isPHI(); ++MI)
602  for (unsigned i = 2, e = MI->getNumOperands()+1; i != e; i += 2) {
603  MachineOperand &MO = MI->getOperand(i);
604  if (MO.getMBB() == fromMBB)
605  MO.setMBB(this);
606  }
607  }
608 }
609 
611  return std::find(pred_begin(), pred_end(), MBB) != pred_end();
612 }
613 
615  return std::find(succ_begin(), succ_end(), MBB) != succ_end();
616 }
617 
620  return std::next(I) == MachineFunction::const_iterator(MBB);
621 }
622 
624  MachineFunction::iterator Fallthrough = this;
625  ++Fallthrough;
626  // If FallthroughBlock is off the end of the function, it can't fall through.
627  if (Fallthrough == getParent()->end())
628  return false;
629 
630  // If FallthroughBlock isn't a successor, no fallthrough is possible.
631  if (!isSuccessor(Fallthrough))
632  return false;
633 
634  // Analyze the branches, if any, at the end of the block.
635  MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
638  if (TII->AnalyzeBranch(*this, TBB, FBB, Cond)) {
639  // If we couldn't analyze the branch, examine the last instruction.
640  // If the block doesn't end in a known control barrier, assume fallthrough
641  // is possible. The isPredicated check is needed because this code can be
642  // called during IfConversion, where an instruction which is normally a
643  // Barrier is predicated and thus no longer an actual control barrier.
644  return empty() || !back().isBarrier() || TII->isPredicated(&back());
645  }
646 
647  // If there is no branch, control always falls through.
648  if (!TBB) return true;
649 
650  // If there is some explicit branch to the fallthrough block, it can obviously
651  // reach, even though the branch should get folded to fall through implicitly.
652  if (MachineFunction::iterator(TBB) == Fallthrough ||
653  MachineFunction::iterator(FBB) == Fallthrough)
654  return true;
655 
656  // If it's an unconditional branch to some block not the fall through, it
657  // doesn't fall through.
658  if (Cond.empty()) return false;
659 
660  // Otherwise, if it is conditional and has no explicit false block, it falls
661  // through.
662  return FBB == nullptr;
663 }
664 
667  // Splitting the critical edge to a landing pad block is non-trivial. Don't do
668  // it in this generic function.
669  if (Succ->isLandingPad())
670  return nullptr;
671 
672  MachineFunction *MF = getParent();
673  DebugLoc dl; // FIXME: this is nowhere
674 
675  // Performance might be harmed on HW that implements branching using exec mask
676  // where both sides of the branches are always executed.
677  if (MF->getTarget().requiresStructuredCFG())
678  return nullptr;
679 
680  // We may need to update this's terminator, but we can't do that if
681  // AnalyzeBranch fails. If this uses a jump table, we won't touch it.
682  const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
683  MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
685  if (TII->AnalyzeBranch(*this, TBB, FBB, Cond))
686  return nullptr;
687 
688  // Avoid bugpoint weirdness: A block may end with a conditional branch but
689  // jumps to the same MBB is either case. We have duplicate CFG edges in that
690  // case that we can't handle. Since this never happens in properly optimized
691  // code, just skip those edges.
692  if (TBB && TBB == FBB) {
693  DEBUG(dbgs() << "Won't split critical edge after degenerate BB#"
694  << getNumber() << '\n');
695  return nullptr;
696  }
697 
699  MF->insert(std::next(MachineFunction::iterator(this)), NMBB);
700  DEBUG(dbgs() << "Splitting critical edge:"
701  " BB#" << getNumber()
702  << " -- BB#" << NMBB->getNumber()
703  << " -- BB#" << Succ->getNumber() << '\n');
704 
707  if (LIS)
708  LIS->insertMBBInMaps(NMBB);
709  else if (Indexes)
710  Indexes->insertMBBInMaps(NMBB);
711 
712  // On some targets like Mips, branches may kill virtual registers. Make sure
713  // that LiveVariables is properly updated after updateTerminator replaces the
714  // terminators.
716 
717  // Collect a list of virtual registers killed by the terminators.
718  SmallVector<unsigned, 4> KilledRegs;
719  if (LV)
721  I != E; ++I) {
722  MachineInstr *MI = I;
724  OE = MI->operands_end(); OI != OE; ++OI) {
725  if (!OI->isReg() || OI->getReg() == 0 ||
726  !OI->isUse() || !OI->isKill() || OI->isUndef())
727  continue;
728  unsigned Reg = OI->getReg();
730  LV->getVarInfo(Reg).removeKill(MI)) {
731  KilledRegs.push_back(Reg);
732  DEBUG(dbgs() << "Removing terminator kill: " << *MI);
733  OI->setIsKill(false);
734  }
735  }
736  }
737 
738  SmallVector<unsigned, 4> UsedRegs;
739  if (LIS) {
741  I != E; ++I) {
742  MachineInstr *MI = I;
743 
745  OE = MI->operands_end(); OI != OE; ++OI) {
746  if (!OI->isReg() || OI->getReg() == 0)
747  continue;
748 
749  unsigned Reg = OI->getReg();
750  if (std::find(UsedRegs.begin(), UsedRegs.end(), Reg) == UsedRegs.end())
751  UsedRegs.push_back(Reg);
752  }
753  }
754  }
755 
756  ReplaceUsesOfBlockWith(Succ, NMBB);
757 
758  // If updateTerminator() removes instructions, we need to remove them from
759  // SlotIndexes.
760  SmallVector<MachineInstr*, 4> Terminators;
761  if (Indexes) {
763  I != E; ++I)
764  Terminators.push_back(I);
765  }
766 
768 
769  if (Indexes) {
770  SmallVector<MachineInstr*, 4> NewTerminators;
772  I != E; ++I)
773  NewTerminators.push_back(I);
774 
775  for (SmallVectorImpl<MachineInstr*>::iterator I = Terminators.begin(),
776  E = Terminators.end(); I != E; ++I) {
777  if (std::find(NewTerminators.begin(), NewTerminators.end(), *I) ==
778  NewTerminators.end())
779  Indexes->removeMachineInstrFromMaps(*I);
780  }
781  }
782 
783  // Insert unconditional "jump Succ" instruction in NMBB if necessary.
784  NMBB->addSuccessor(Succ);
785  if (!NMBB->isLayoutSuccessor(Succ)) {
786  Cond.clear();
787  MF->getSubtarget().getInstrInfo()->InsertBranch(*NMBB, Succ, nullptr, Cond,
788  dl);
789 
790  if (Indexes) {
791  for (instr_iterator I = NMBB->instr_begin(), E = NMBB->instr_end();
792  I != E; ++I) {
793  // Some instructions may have been moved to NMBB by updateTerminator(),
794  // so we first remove any instruction that already has an index.
795  if (Indexes->hasIndex(I))
796  Indexes->removeMachineInstrFromMaps(I);
797  Indexes->insertMachineInstrInMaps(I);
798  }
799  }
800  }
801 
802  // Fix PHI nodes in Succ so they refer to NMBB instead of this
804  i = Succ->instr_begin(),e = Succ->instr_end();
805  i != e && i->isPHI(); ++i)
806  for (unsigned ni = 1, ne = i->getNumOperands(); ni != ne; ni += 2)
807  if (i->getOperand(ni+1).getMBB() == this)
808  i->getOperand(ni+1).setMBB(NMBB);
809 
810  // Inherit live-ins from the successor
812  E = Succ->livein_end(); I != E; ++I)
813  NMBB->addLiveIn(*I);
814 
815  // Update LiveVariables.
816  const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
817  if (LV) {
818  // Restore kills of virtual registers that were killed by the terminators.
819  while (!KilledRegs.empty()) {
820  unsigned Reg = KilledRegs.pop_back_val();
821  for (instr_iterator I = instr_end(), E = instr_begin(); I != E;) {
822  if (!(--I)->addRegisterKilled(Reg, TRI, /* addIfNotFound= */ false))
823  continue;
825  LV->getVarInfo(Reg).Kills.push_back(I);
826  DEBUG(dbgs() << "Restored terminator kill: " << *I);
827  break;
828  }
829  }
830  // Update relevant live-through information.
831  LV->addNewBlock(NMBB, this, Succ);
832  }
833 
834  if (LIS) {
835  // After splitting the edge and updating SlotIndexes, live intervals may be
836  // in one of two situations, depending on whether this block was the last in
837  // the function. If the original block was the last in the function, all live
838  // intervals will end prior to the beginning of the new split block. If the
839  // original block was not at the end of the function, all live intervals will
840  // extend to the end of the new split block.
841 
842  bool isLastMBB =
843  std::next(MachineFunction::iterator(NMBB)) == getParent()->end();
844 
845  SlotIndex StartIndex = Indexes->getMBBEndIdx(this);
846  SlotIndex PrevIndex = StartIndex.getPrevSlot();
847  SlotIndex EndIndex = Indexes->getMBBEndIdx(NMBB);
848 
849  // Find the registers used from NMBB in PHIs in Succ.
850  SmallSet<unsigned, 8> PHISrcRegs;
852  I = Succ->instr_begin(), E = Succ->instr_end();
853  I != E && I->isPHI(); ++I) {
854  for (unsigned ni = 1, ne = I->getNumOperands(); ni != ne; ni += 2) {
855  if (I->getOperand(ni+1).getMBB() == NMBB) {
856  MachineOperand &MO = I->getOperand(ni);
857  unsigned Reg = MO.getReg();
858  PHISrcRegs.insert(Reg);
859  if (MO.isUndef())
860  continue;
861 
862  LiveInterval &LI = LIS->getInterval(Reg);
863  VNInfo *VNI = LI.getVNInfoAt(PrevIndex);
864  assert(VNI && "PHI sources should be live out of their predecessors.");
865  LI.addSegment(LiveInterval::Segment(StartIndex, EndIndex, VNI));
866  }
867  }
868  }
869 
871  for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
873  if (PHISrcRegs.count(Reg) || !LIS->hasInterval(Reg))
874  continue;
875 
876  LiveInterval &LI = LIS->getInterval(Reg);
877  if (!LI.liveAt(PrevIndex))
878  continue;
879 
880  bool isLiveOut = LI.liveAt(LIS->getMBBStartIdx(Succ));
881  if (isLiveOut && isLastMBB) {
882  VNInfo *VNI = LI.getVNInfoAt(PrevIndex);
883  assert(VNI && "LiveInterval should have VNInfo where it is live.");
884  LI.addSegment(LiveInterval::Segment(StartIndex, EndIndex, VNI));
885  } else if (!isLiveOut && !isLastMBB) {
886  LI.removeSegment(StartIndex, EndIndex);
887  }
888  }
889 
890  // Update all intervals for registers whose uses may have been modified by
891  // updateTerminator().
892  LIS->repairIntervalsInRange(this, getFirstTerminator(), end(), UsedRegs);
893  }
894 
895  if (MachineDominatorTree *MDT =
897  MDT->recordSplitCriticalEdge(this, Succ, NMBB);
898 
900  if (MachineLoop *TIL = MLI->getLoopFor(this)) {
901  // If one or the other blocks were not in a loop, the new block is not
902  // either, and thus LI doesn't need to be updated.
903  if (MachineLoop *DestLoop = MLI->getLoopFor(Succ)) {
904  if (TIL == DestLoop) {
905  // Both in the same loop, the NMBB joins loop.
906  DestLoop->addBasicBlockToLoop(NMBB, MLI->getBase());
907  } else if (TIL->contains(DestLoop)) {
908  // Edge from an outer loop to an inner loop. Add to the outer loop.
909  TIL->addBasicBlockToLoop(NMBB, MLI->getBase());
910  } else if (DestLoop->contains(TIL)) {
911  // Edge from an inner loop to an outer loop. Add to the outer loop.
912  DestLoop->addBasicBlockToLoop(NMBB, MLI->getBase());
913  } else {
914  // Edge from two loops with no containment relation. Because these
915  // are natural loops, we know that the destination block must be the
916  // header of its loop (adding a branch into a loop elsewhere would
917  // create an irreducible loop).
918  assert(DestLoop->getHeader() == Succ &&
919  "Should not create irreducible loops!");
920  if (MachineLoop *P = DestLoop->getParentLoop())
921  P->addBasicBlockToLoop(NMBB, MLI->getBase());
922  }
923  }
924  }
925 
926  return NMBB;
927 }
928 
929 /// Prepare MI to be removed from its bundle. This fixes bundle flags on MI's
930 /// neighboring instructions so the bundle won't be broken by removing MI.
931 static void unbundleSingleMI(MachineInstr *MI) {
932  // Removing the first instruction in a bundle.
933  if (MI->isBundledWithSucc() && !MI->isBundledWithPred())
934  MI->unbundleFromSucc();
935  // Removing the last instruction in a bundle.
936  if (MI->isBundledWithPred() && !MI->isBundledWithSucc())
937  MI->unbundleFromPred();
938  // If MI is not bundled, or if it is internal to a bundle, the neighbor flags
939  // are already fine.
940 }
941 
944  unbundleSingleMI(I);
945  return Insts.erase(I);
946 }
947 
949  unbundleSingleMI(MI);
952  return Insts.remove(MI);
953 }
954 
957  assert(!MI->isBundledWithPred() && !MI->isBundledWithSucc() &&
958  "Cannot insert instruction with bundle flags");
959  // Set the bundle flags when inserting inside a bundle.
960  if (I != instr_end() && I->isBundledWithPred()) {
963  }
964  return Insts.insert(I, MI);
965 }
966 
967 /// removeFromParent - This method unlinks 'this' from the containing function,
968 /// and returns it, but does not delete it.
970  assert(getParent() && "Not embedded in a function!");
971  getParent()->remove(this);
972  return this;
973 }
974 
975 
976 /// eraseFromParent - This method unlinks 'this' from the containing function,
977 /// and deletes it.
979  assert(getParent() && "Not embedded in a function!");
980  getParent()->erase(this);
981 }
982 
983 
984 /// ReplaceUsesOfBlockWith - Given a machine basic block that branched to
985 /// 'Old', change the code and CFG so that it branches to 'New' instead.
987  MachineBasicBlock *New) {
988  assert(Old != New && "Cannot replace self with self!");
989 
991  while (I != instr_begin()) {
992  --I;
993  if (!I->isTerminator()) break;
994 
995  // Scan the operands of this machine instruction, replacing any uses of Old
996  // with New.
997  for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
998  if (I->getOperand(i).isMBB() &&
999  I->getOperand(i).getMBB() == Old)
1000  I->getOperand(i).setMBB(New);
1001  }
1002 
1003  // Update the successor information.
1004  replaceSuccessor(Old, New);
1005 }
1006 
1007 /// CorrectExtraCFGEdges - Various pieces of code can cause excess edges in the
1008 /// CFG to be inserted. If we have proven that MBB can only branch to DestA and
1009 /// DestB, remove any other MBB successors from the CFG. DestA and DestB can be
1010 /// null.
1011 ///
1012 /// Besides DestA and DestB, retain other edges leading to LandingPads
1013 /// (currently there can be only one; we don't check or require that here).
1014 /// Note it is possible that DestA and/or DestB are LandingPads.
1016  MachineBasicBlock *DestB,
1017  bool isCond) {
1018  // The values of DestA and DestB frequently come from a call to the
1019  // 'TargetInstrInfo::AnalyzeBranch' method. We take our meaning of the initial
1020  // values from there.
1021  //
1022  // 1. If both DestA and DestB are null, then the block ends with no branches
1023  // (it falls through to its successor).
1024  // 2. If DestA is set, DestB is null, and isCond is false, then the block ends
1025  // with only an unconditional branch.
1026  // 3. If DestA is set, DestB is null, and isCond is true, then the block ends
1027  // with a conditional branch that falls through to a successor (DestB).
1028  // 4. If DestA and DestB is set and isCond is true, then the block ends with a
1029  // conditional branch followed by an unconditional branch. DestA is the
1030  // 'true' destination and DestB is the 'false' destination.
1031 
1032  bool Changed = false;
1033 
1034  MachineFunction::iterator FallThru =
1035  std::next(MachineFunction::iterator(this));
1036 
1037  if (!DestA && !DestB) {
1038  // Block falls through to successor.
1039  DestA = FallThru;
1040  DestB = FallThru;
1041  } else if (DestA && !DestB) {
1042  if (isCond)
1043  // Block ends in conditional jump that falls through to successor.
1044  DestB = FallThru;
1045  } else {
1046  assert(DestA && DestB && isCond &&
1047  "CFG in a bad state. Cannot correct CFG edges");
1048  }
1049 
1050  // Remove superfluous edges. I.e., those which aren't destinations of this
1051  // basic block, duplicate edges, or landing pads.
1054  while (SI != succ_end()) {
1055  const MachineBasicBlock *MBB = *SI;
1056  if (!SeenMBBs.insert(MBB).second ||
1057  (MBB != DestA && MBB != DestB && !MBB->isLandingPad())) {
1058  // This is a superfluous edge, remove it.
1059  SI = removeSuccessor(SI);
1060  Changed = true;
1061  } else {
1062  ++SI;
1063  }
1064  }
1065 
1066  return Changed;
1067 }
1068 
1069 /// findDebugLoc - find the next valid DebugLoc starting at MBBI, skipping
1070 /// any DBG_VALUE instructions. Return UnknownLoc if there is none.
1071 DebugLoc
1073  DebugLoc DL;
1074  instr_iterator E = instr_end();
1075  if (MBBI == E)
1076  return DL;
1077 
1078  // Skip debug declarations, we don't want a DebugLoc from them.
1079  while (MBBI != E && MBBI->isDebugValue())
1080  MBBI++;
1081  if (MBBI != E)
1082  DL = MBBI->getDebugLoc();
1083  return DL;
1084 }
1085 
1086 /// getSuccWeight - Return weight of the edge from this block to MBB.
1087 ///
1088 uint32_t MachineBasicBlock::getSuccWeight(const_succ_iterator Succ) const {
1089  if (Weights.empty())
1090  return 0;
1091 
1092  return *getWeightIterator(Succ);
1093 }
1094 
1095 /// Set successor weight of a given iterator.
1097  if (Weights.empty())
1098  return;
1099  *getWeightIterator(I) = weight;
1100 }
1101 
1102 /// getWeightIterator - Return wight iterator corresonding to the I successor
1103 /// iterator
1104 MachineBasicBlock::weight_iterator MachineBasicBlock::
1105 getWeightIterator(MachineBasicBlock::succ_iterator I) {
1106  assert(Weights.size() == Successors.size() && "Async weight list!");
1107  size_t index = std::distance(Successors.begin(), I);
1108  assert(index < Weights.size() && "Not a current successor!");
1109  return Weights.begin() + index;
1110 }
1111 
1112 /// getWeightIterator - Return wight iterator corresonding to the I successor
1113 /// iterator
1114 MachineBasicBlock::const_weight_iterator MachineBasicBlock::
1115 getWeightIterator(MachineBasicBlock::const_succ_iterator I) const {
1116  assert(Weights.size() == Successors.size() && "Async weight list!");
1117  const size_t index = std::distance(Successors.begin(), I);
1118  assert(index < Weights.size() && "Not a current successor!");
1119  return Weights.begin() + index;
1120 }
1121 
1122 /// Return whether (physical) register "Reg" has been <def>ined and not <kill>ed
1123 /// as of just before "MI".
1124 ///
1125 /// Search is localised to a neighborhood of
1126 /// Neighborhood instructions before (searching for defs or kills) and N
1127 /// instructions after (searching just for defs) MI.
1130  unsigned Reg, const_iterator Before,
1131  unsigned Neighborhood) const {
1132  unsigned N = Neighborhood;
1133 
1134  // Start by searching backwards from Before, looking for kills, reads or defs.
1135  const_iterator I(Before);
1136  // If this is the first insn in the block, don't search backwards.
1137  if (I != begin()) {
1138  do {
1139  --I;
1140 
1142  ConstMIOperands(I).analyzePhysReg(Reg, TRI);
1143 
1144  if (Analysis.Defines)
1145  // Outputs happen after inputs so they take precedence if both are
1146  // present.
1147  return Analysis.DefinesDead ? LQR_Dead : LQR_Live;
1148 
1149  if (Analysis.Kills || Analysis.Clobbers)
1150  // Register killed, so isn't live.
1151  return LQR_Dead;
1152 
1153  else if (Analysis.ReadsOverlap)
1154  // Defined or read without a previous kill - live.
1155  return Analysis.Reads ? LQR_Live : LQR_OverlappingLive;
1156 
1157  } while (I != begin() && --N > 0);
1158  }
1159 
1160  // Did we get to the start of the block?
1161  if (I == begin()) {
1162  // If so, the register's state is definitely defined by the live-in state.
1163  for (MCRegAliasIterator RAI(Reg, TRI, /*IncludeSelf=*/true);
1164  RAI.isValid(); ++RAI) {
1165  if (isLiveIn(*RAI))
1166  return (*RAI == Reg) ? LQR_Live : LQR_OverlappingLive;
1167  }
1168 
1169  return LQR_Dead;
1170  }
1171 
1172  N = Neighborhood;
1173 
1174  // Try searching forwards from Before, looking for reads or defs.
1175  I = const_iterator(Before);
1176  // If this is the last insn in the block, don't search forwards.
1177  if (I != end()) {
1178  for (++I; I != end() && N > 0; ++I, --N) {
1180  ConstMIOperands(I).analyzePhysReg(Reg, TRI);
1181 
1182  if (Analysis.ReadsOverlap)
1183  // Used, therefore must have been live.
1184  return (Analysis.Reads) ?
1186 
1187  else if (Analysis.Clobbers || Analysis.Defines)
1188  // Defined (but not read) therefore cannot have been live.
1189  return LQR_Dead;
1190  }
1191  }
1192 
1193  // At this point we have no idea of the liveness of the register.
1194  return LQR_Unknown;
1195 }
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:82
unsigned succ_size() const
void push_back(const T &Elt)
Definition: SmallVector.h:222
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
mop_iterator operands_end()
Definition: MachineInstr.h:290
const MCAsmInfo * getAsmInfo() const
Definition: MCContext.h:225
instr_iterator instr_begin()
void transferNodesFromList(ilist_node_traits &, ilist_iterator< NodeTy >, ilist_iterator< NodeTy >)
Definition: ilist.h:117
void removeNodeFromList(NodeTy *)
Definition: ilist.h:116
instr_iterator instr_end()
bool removeKill(MachineInstr *MI)
removeKill - Delete a kill corresponding to the specified machine instruction.
Definition: LiveVariables.h:94
MachineBasicBlock * getMBB() const
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:39
static unsigned index2VirtReg(unsigned Index)
index2VirtReg - Convert a 0-based index to a virtual register number.
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:114
int getNumber() const
getNumber - MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a M...
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
instr_iterator getFirstInstrTerminator()
getFirstInstrTerminator - Same getFirstTerminator but it ignores bundles and return an instr_iterator...
iterator getFirstNonDebugInstr()
getFirstNonDebugInstr - returns an iterator to the first non-debug instruction in the basic block...
std::vector< unsigned >::const_iterator livein_iterator
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:588
iterator getFirstTerminator()
getFirstTerminator - returns an iterator to the first terminator instruction of this basic block...
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
void removeLiveIn(unsigned Reg)
removeLiveIn - Remove the specified register from the live in set.
virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e...
void addLiveIn(unsigned Reg)
Adds the specified register as a live in.
This represents a simple continuous liveness interval for a value.
Definition: LiveInterval.h:159
void moveAfter(MachineBasicBlock *NewBefore)
A debug info location.
Definition: DebugLoc.h:34
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *fromMBB)
transferSuccessorsAndUpdatePHIs - Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor blocks which refer to fromMBB to refer to this.
F(f)
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
Manage lifetime of a slot tracker for printing IR.
virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const
Remove the branching code at the end of the specific MBB.
unsigned getFunctionNumber() const
getFunctionNumber - Return a unique ID for the current function.
VNInfo - Value Number Information.
Definition: LiveInterval.h:45
Instructions::iterator instr_iterator
MachineBasicBlock * removeFromParent()
removeFromParent - This method unlinks 'this' from the containing function, and returns it...
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
Definition: LiveInterval.h:392
bool Clobbers
Clobbers - Reg or an overlapping register is defined, or a regmask clobbers Reg.
StringRef getName() const
Return a constant reference to the value's name.
Definition: Value.cpp:188
bool DefinesDead
DefinesDead - All defs of a Reg or a super-register are dead.
COPY - Target-independent register copy.
Definition: TargetOpcodes.h:86
livein_iterator livein_begin() const
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
void ReplaceUsesOfBlockWith(MachineBasicBlock *Old, MachineBasicBlock *New)
ReplaceUsesOfBlockWith - Given a machine basic block that branched to 'Old', change the code and CFG ...
void eraseFromParent()
eraseFromParent - This method unlinks 'this' from the containing function and deletes it...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:79
const HexagonInstrInfo * TII
AnalysisType * getAnalysisIfAvailable() const
getAnalysisIfAvailable<AnalysisType>() - Subclasses use this function to get analysis information tha...
bool isPHI() const
Definition: MachineInstr.h:757
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
std::vector< MachineBasicBlock * >::iterator succ_iterator
Reg
All possible values of the reg field in the ModR/M byte.
MachineBasicBlock * SplitCriticalEdge(MachineBasicBlock *Succ, Pass *P)
SplitCriticalEdge - Split the critical edge from this block to the given successor block...
bool isUndef() const
static void unbundleSingleMI(MachineInstr *MI)
Prepare MI to be removed from its bundle.
MachineInstr * remove_instr(MachineInstr *I)
Remove the possibly bundled instruction from the instruction list without deleting it...
PhysRegInfo analyzePhysReg(unsigned Reg, const TargetRegisterInfo *TRI)
analyzePhysReg - Analyze how the current instruction or bundle uses a physical register.
#define false
Definition: ConvertUTF.c:65
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:271
Context object for machine code objects.
Definition: MCContext.h:48
bool isBundledWithSucc() const
Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle...
Definition: MachineInstr.h:221
void unbundleFromPred()
Break bundle above this instruction.
PrintReg - Helper class for printing registers on a raw_ostream.
void transferSuccessors(MachineBasicBlock *fromMBB)
transferSuccessors - Transfers all the successors from MBB to this machine basic block (i...
SlotIndexes pass.
Definition: SlotIndexes.h:334
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Definition: SmallVector.h:57
iterator addSegment(Segment S)
Add the specified Segment to this range, merging segments as appropriate.
bool canFallThrough()
canFallThrough - Return true if the block can implicitly transfer control to the block after it by fa...
iterator getLastNonDebugInstr()
getLastNonDebugInstr - returns an iterator to the last non-debug instruction in the basic block...
virtual bool ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const
Reverses the branch condition of the specified condition list, returning false on success and true if...
void printAsOperand(raw_ostream &OS, bool PrintType=true) const
MCContext & getContext() const
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
LivenessQueryResult computeRegisterLiveness(const TargetRegisterInfo *TRI, unsigned Reg, const_iterator Before, unsigned Neighborhood=10) const
Return whether (physical) register Reg has been <def>ined and not <kill>ed as of just before Before...
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
const BasicBlock * getBasicBlock() const
getBasicBlock - Return the LLVM basic block that this instance corresponded to originally.
SlotIndex getPrevSlot() const
Returns the previous slot in the index list.
Definition: SlotIndexes.h:292
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:120
TargetInstrInfo - Interface to description of machine instruction set.
static void deleteNode(NodeTy *V)
Definition: ilist.h:113
bundle_iterator< MachineInstr, instr_iterator > iterator
#define P(N)
bool Kills
There is a kill of Reg or a super-register.
iterator SkipPHIsAndLabels(iterator I)
SkipPHIsAndLabels - Return the first instruction in MBB after I that is not a PHI or a label...
void insertMBBInMaps(MachineBasicBlock *mbb)
Add the given MachineBasicBlock into the maps.
Definition: SlotIndexes.h:639
LLVM Basic Block Representation.
Definition: BasicBlock.h:65
bool ReadsOverlap
ReadsOverlap - Reg or an overlapping register is read.
livein_iterator livein_end() const
DebugLoc findDebugLoc(instr_iterator MBBI)
findDebugLoc - find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE instructions...
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:32
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:264
void setMBB(MachineBasicBlock *MBB)
iterator insert(iterator where, const NodeTy &val)
Definition: ilist.h:610
Register is known to be dead.
void setFlag(MIFlag Flag)
Set a MI flag.
Definition: MachineInstr.h:155
MCRegAliasIterator enumerates all registers aliasing Reg.
void clearFlag(MIFlag Flag)
clearFlag - Clear a MI flag.
Definition: MachineInstr.h:166
const MachineBasicBlock * getLandingPadSuccessor() const
getLandingPadSuccessor - If this block has a successor that is a landing pad, return it...
void remove(iterator MBBI)
bool isBundledWithPred() const
Return true if this instruction is part of a bundle, and it is not the first instruction in the bundl...
Definition: MachineInstr.h:217
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:69
LivenessQueryResult
Possible outcome of a register liveness query to computeRegisterLiveness()
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
Register is known to be live.
void removeSuccessor(MachineBasicBlock *succ)
removeSuccessor - Remove successor from the successors list of this MachineBasicBlock.
void moveBefore(MachineBasicBlock *NewAfter)
moveBefore/moveAfter - move 'this' block before or after the specified block.
VarInfo & getVarInfo(unsigned RegIdx)
getVarInfo - Return the VarInfo structure for the specified VIRTUAL register.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool liveAt(SlotIndex index) const
Definition: LiveInterval.h:372
MCSymbol * getSymbol() const
getSymbol - Return the MCSymbol for this basic block.
SlotIndex getInstructionIndex(const MachineInstr *MI) const
Returns the base index for the given instruction.
Definition: SlotIndexes.h:414
iterator erase(iterator where)
Definition: ilist.h:465
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
std::vector< MachineBasicBlock * >::const_iterator const_pred_iterator
const char * getPrivateLabelPrefix() const
Definition: MCAsmInfo.h:451
hexagon gen pred
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:53
void addNewBlock(MachineBasicBlock *BB, MachineBasicBlock *DomBB, MachineBasicBlock *SuccBB)
addNewBlock - Add a new basic block BB between DomBB and SuccBB.
std::string getFullName() const
getFullName - Return a formatted string to identify this block and its parent function.
std::vector< MachineInstr * > Kills
Kills - List of MachineInstruction's which are the last use of this virtual register (kill it) in the...
Definition: LiveVariables.h:89
void removeSegment(SlotIndex Start, SlotIndex End, bool RemoveDeadValNo=false)
Remove the specified segment from this range.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
Definition: SmallPtrSet.h:299
BasicBlockListType::const_iterator const_iterator
void splice(iterator InsertPt, iterator MBBI)
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:861
bool hasIndex(const MachineInstr *instr) const
Returns true if the given machine instr is mapped to an index, otherwise returns false.
Definition: SlotIndexes.h:409
void updateTerminator()
updateTerminator - Update the terminator instructions in block to account for changes to the layout...
bool isSuccessor(const MachineBasicBlock *MBB) const
isSuccessor - Return true if the specified MBB is a successor of this block.
bool Reads
Reads - Read or a super-register is read.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:123
StringRef getName() const
getName - Return the name of the corresponding LLVM basic block, or "(null)".
ConstMIOperands - Iterate over operands of a single const instruction.
void replaceSuccessor(MachineBasicBlock *Old, MachineBasicBlock *New)
replaceSuccessor - Replace successor OLD with NEW and update weight info.
Register itself is not live, but some overlapping register is.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:51
bundle_iterator< const MachineInstr, const_instr_iterator > const_iterator
static bool isPhysicalRegister(unsigned Reg)
isPhysicalRegister - Return true if the specified register number is in the physical register namespa...
bool hasAddressTaken() const
hasAddressTaken - Test whether this block is potentially the target of an indirect branch...
bool isLandingPad() const
isLandingPad - Returns true if the block is a landing pad.
block Block Frequency Analysis
void addNodeToList(NodeTy *)
Definition: ilist.h:115
bool isLiveIn(unsigned Reg) const
isLiveIn - Return true if the specified register is in the live in set.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:111
Register liveness not decidable from local neighborhood.
bool Defines
Defines - Reg or a super-register is defined.
#define I(x, y, z)
Definition: MD5.cpp:54
#define N
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, DebugLoc DL) const
Insert branch code into the end of the specified MachineBasicBlock.
iterator getFirstNonPHI()
Returns a pointer to the first instruction in this block that is not a PHINode instruction.
void setSuccWeight(succ_iterator I, uint32_t weight)
Set successor weight of a given iterator.
PhysRegInfo - Information about a physical register used by a set of operands.
void removeFromMBBNumbering(unsigned N)
removeFromMBBNumbering - Remove the specific machine basic block from our tracker, this is only really to be used by the MachineBasicBlock implementation.
SlotIndex getMBBStartIdx(unsigned Num) const
Returns the first index in the given basic block number.
Definition: SlotIndexes.h:486
raw_ostream & operator<<(raw_ostream &OS, const APInt &I)
Definition: APInt.h:1738
unsigned getReg() const
getReg - Returns the register number.
void erase(iterator MBBI)
void insert(iterator MBBI, MachineBasicBlock *MBB)
void unbundleFromSucc()
Break bundle below this instruction.
std::vector< MachineBasicBlock * >::const_iterator const_succ_iterator
virtual const TargetInstrInfo * getInstrInfo() const
unsigned addToMBBNumbering(MachineBasicBlock *MBB)
Adds the MBB to the internal numbering.
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:365
mop_iterator operands_begin()
Definition: MachineInstr.h:289
BasicBlockListType::iterator iterator
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:38
#define DEBUG(X)
Definition: Debug.h:92
virtual bool isPredicated(const MachineInstr *MI) const
Returns true if the instruction is already predicated.
bool isPredecessor(const MachineBasicBlock *MBB) const
isPredecessor - Return true if the specified MBB is a predecessor of this block.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:40
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
void print(raw_ostream &OS, SlotIndexes *=nullptr) const
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
isLayoutSuccessor - Return true if the specified MBB will be emitted immediately after this block...
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:92
bool requiresStructuredCFG() const
NodeTy * remove(iterator &IT)
Definition: ilist.h:435
void addSuccessor(MachineBasicBlock *succ, uint32_t weight=0)
addSuccessor - Add succ as a successor of this MachineBasicBlock.
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
bool CorrectExtraCFGEdges(MachineBasicBlock *DestA, MachineBasicBlock *DestB, bool isCond)
CorrectExtraCFGEdges - Various pieces of code can cause excess edges in the CFG to be inserted...
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:410