24 static bool inRange(
const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) {
25 if (
auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
26 int64_t
Value = CE->getValue();
27 return Value >= MinValue && Value <= MaxValue;
69 SMLoc StartLoc, EndLoc;
124 else if (
auto *CE = dyn_cast<MCConstantExpr>(Expr))
131 SystemZOperand(OperandKind kind,
SMLoc startLoc,
SMLoc endLoc)
132 :
Kind(kind), StartLoc(startLoc), EndLoc(endLoc) {}
135 static std::unique_ptr<SystemZOperand> createInvalid(
SMLoc StartLoc,
137 return make_unique<SystemZOperand>(KindInvalid, StartLoc, EndLoc);
139 static std::unique_ptr<SystemZOperand> createToken(
StringRef Str,
SMLoc Loc) {
140 auto Op = make_unique<SystemZOperand>(KindToken, Loc, Loc);
141 Op->Token.Data = Str.
data();
142 Op->Token.Length = Str.
size();
145 static std::unique_ptr<SystemZOperand>
147 auto Op = make_unique<SystemZOperand>(KindReg, StartLoc, EndLoc);
152 static std::unique_ptr<SystemZOperand>
153 createAccessReg(
unsigned Num,
SMLoc StartLoc,
SMLoc EndLoc) {
154 auto Op = make_unique<SystemZOperand>(KindAccessReg, StartLoc, EndLoc);
158 static std::unique_ptr<SystemZOperand>
160 auto Op = make_unique<SystemZOperand>(KindImm, StartLoc, EndLoc);
164 static std::unique_ptr<SystemZOperand>
166 const MCExpr *Disp,
unsigned Index,
const MCExpr *Length,
168 auto Op = make_unique<SystemZOperand>(KindMem, StartLoc, EndLoc);
169 Op->Mem.MemKind = MemKind;
170 Op->Mem.RegKind = RegKind;
172 Op->Mem.Index = Index;
174 Op->Mem.Length = Length;
177 static std::unique_ptr<SystemZOperand>
180 auto Op = make_unique<SystemZOperand>(KindImmTLS, StartLoc, EndLoc);
181 Op->ImmTLS.Imm = Imm;
182 Op->ImmTLS.Sym = Sym;
187 bool isToken()
const override {
188 return Kind == KindToken;
191 assert(
Kind == KindToken &&
"Not a token");
192 return StringRef(Token.Data, Token.Length);
196 bool isReg()
const override {
197 return Kind == KindReg;
200 return Kind == KindReg &&
Reg.Kind == RegKind;
202 unsigned getReg()
const override {
203 assert(
Kind == KindReg &&
"Not a register");
209 bool isAccessReg()
const {
210 return Kind == KindAccessReg;
214 bool isImm()
const override {
215 return Kind == KindImm;
217 bool isImm(int64_t MinValue, int64_t MaxValue)
const {
218 return Kind == KindImm &&
inRange(Imm, MinValue, MaxValue);
220 const MCExpr *getImm()
const {
221 assert(
Kind == KindImm &&
"Not an immediate");
226 bool isImmTLS()
const {
227 return Kind == KindImmTLS;
231 bool isMem()
const override {
232 return Kind == KindMem;
235 return (
Kind == KindMem &&
236 (Mem.MemKind == MemKind ||
239 (Mem.MemKind == BDMem && MemKind == BDXMem)));
242 return isMem(MemKind) && Mem.RegKind == RegKind;
245 return isMem(MemKind, RegKind) &&
inRange(Mem.Disp, 0, 0xfff);
248 return isMem(MemKind, RegKind) &&
inRange(Mem.Disp, -524288, 524287);
251 return isMemDisp12(BDLMem, RegKind) &&
inRange(Mem.Length, 1, 0x100);
253 void addBDVAddrOperands(
MCInst &Inst,
unsigned N)
const {
254 assert(N == 3 &&
"Invalid number of operands");
255 assert(
isMem(BDVMem) &&
"Invalid operand type");
257 addExpr(Inst, Mem.Disp);
262 SMLoc getStartLoc()
const override {
return StartLoc; }
263 SMLoc getEndLoc()
const override {
return EndLoc; }
268 void addRegOperands(
MCInst &Inst,
unsigned N)
const {
269 assert(N == 1 &&
"Invalid number of operands");
272 void addAccessRegOperands(
MCInst &Inst,
unsigned N)
const {
273 assert(N == 1 &&
"Invalid number of operands");
274 assert(
Kind == KindAccessReg &&
"Invalid operand type");
277 void addImmOperands(
MCInst &Inst,
unsigned N)
const {
278 assert(N == 1 &&
"Invalid number of operands");
279 addExpr(Inst, getImm());
281 void addBDAddrOperands(
MCInst &Inst,
unsigned N)
const {
282 assert(N == 2 &&
"Invalid number of operands");
283 assert(
isMem(BDMem) &&
"Invalid operand type");
285 addExpr(Inst, Mem.Disp);
287 void addBDXAddrOperands(
MCInst &Inst,
unsigned N)
const {
288 assert(N == 3 &&
"Invalid number of operands");
289 assert(
isMem(BDXMem) &&
"Invalid operand type");
291 addExpr(Inst, Mem.Disp);
294 void addBDLAddrOperands(
MCInst &Inst,
unsigned N)
const {
295 assert(N == 3 &&
"Invalid number of operands");
296 assert(
isMem(BDLMem) &&
"Invalid operand type");
298 addExpr(Inst, Mem.Disp);
299 addExpr(Inst, Mem.Length);
301 void addImmTLSOperands(
MCInst &Inst,
unsigned N)
const {
302 assert(N == 2 &&
"Invalid number of operands");
303 assert(
Kind == KindImmTLS &&
"Invalid operand type");
304 addExpr(Inst, ImmTLS.Imm);
306 addExpr(Inst, ImmTLS.Sym);
310 bool isGR32()
const {
return isReg(GR32Reg); }
311 bool isGRH32()
const {
return isReg(GRH32Reg); }
312 bool isGRX32()
const {
return false; }
313 bool isGR64()
const {
return isReg(GR64Reg); }
314 bool isGR128()
const {
return isReg(GR128Reg); }
315 bool isADDR32()
const {
return isReg(ADDR32Reg); }
316 bool isADDR64()
const {
return isReg(ADDR64Reg); }
317 bool isADDR128()
const {
return false; }
318 bool isFP32()
const {
return isReg(FP32Reg); }
319 bool isFP64()
const {
return isReg(FP64Reg); }
320 bool isFP128()
const {
return isReg(FP128Reg); }
321 bool isVR32()
const {
return isReg(VR32Reg); }
322 bool isVR64()
const {
return isReg(VR64Reg); }
323 bool isVF128()
const {
return false; }
324 bool isVR128()
const {
return isReg(VR128Reg); }
325 bool isBDAddr32Disp12()
const {
return isMemDisp12(BDMem, ADDR32Reg); }
326 bool isBDAddr32Disp20()
const {
return isMemDisp20(BDMem, ADDR32Reg); }
327 bool isBDAddr64Disp12()
const {
return isMemDisp12(BDMem, ADDR64Reg); }
328 bool isBDAddr64Disp20()
const {
return isMemDisp20(BDMem, ADDR64Reg); }
329 bool isBDXAddr64Disp12()
const {
return isMemDisp12(BDXMem, ADDR64Reg); }
330 bool isBDXAddr64Disp20()
const {
return isMemDisp20(BDXMem, ADDR64Reg); }
331 bool isBDLAddr64Disp12Len8()
const {
return isMemDisp12Len8(ADDR64Reg); }
332 bool isBDVAddr64Disp12()
const {
return isMemDisp12(BDVMem, ADDR64Reg); }
333 bool isU1Imm()
const {
return isImm(0, 1); }
334 bool isU2Imm()
const {
return isImm(0, 3); }
335 bool isU3Imm()
const {
return isImm(0, 7); }
336 bool isU4Imm()
const {
return isImm(0, 15); }
337 bool isU6Imm()
const {
return isImm(0, 63); }
338 bool isU8Imm()
const {
return isImm(0, 255); }
339 bool isS8Imm()
const {
return isImm(-128, 127); }
340 bool isU12Imm()
const {
return isImm(0, 4095); }
341 bool isU16Imm()
const {
return isImm(0, 65535); }
342 bool isS16Imm()
const {
return isImm(-32768, 32767); }
343 bool isU32Imm()
const {
return isImm(0, (1LL << 32) - 1); }
344 bool isS32Imm()
const {
return isImm(-(1LL << 31), (1LL << 31) - 1); }
348 #define GET_ASSEMBLER_HEADER
349 #include "SystemZGenAsmMatcher.inc"
363 SMLoc StartLoc, EndLoc;
368 bool parseRegister(
Register &
Reg, RegisterGroup Group,
const unsigned *Regs,
369 bool IsAddress =
false);
372 RegisterGroup Group,
const unsigned *Regs,
375 bool parseAddress(
unsigned &Base,
const MCExpr *&Disp,
376 unsigned &Index,
bool &IsVector,
const MCExpr *&Length,
384 int64_t MaxVal,
bool AllowTLS);
396 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
400 bool ParseDirective(
AsmToken DirectiveID)
override;
401 bool ParseRegister(
unsigned &RegNo,
SMLoc &StartLoc,
SMLoc &EndLoc)
override;
404 bool MatchAndEmitInstruction(
SMLoc IDLoc,
unsigned &Opcode,
407 bool MatchingInlineAsm)
override;
472 return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1,
false);
475 return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1,
false);
477 OperandMatchResultTy parsePCRelTLS16(
OperandVector &Operands) {
478 return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1,
true);
480 OperandMatchResultTy parsePCRelTLS32(
OperandVector &Operands) {
481 return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1,
true);
486 #define GET_REGISTER_MATCHER
487 #define GET_SUBTARGET_FEATURE_NAME
488 #define GET_MATCHER_IMPLEMENTATION
489 #include "SystemZGenAsmMatcher.inc"
491 void SystemZOperand::print(
raw_ostream &OS)
const {
496 bool SystemZAsmParser::parseRegister(
Register &
Reg) {
497 Reg.StartLoc = Parser.getTok().getLoc();
501 return Error(Parser.getTok().getLoc(),
"register expected");
506 return Error(Reg.StartLoc,
"invalid register");
511 return Error(Reg.StartLoc,
"invalid register");
516 return Error(Reg.StartLoc,
"invalid register");
519 if (Prefix ==
'r' && Reg.Num < 16)
521 else if (Prefix ==
'f' && Reg.Num < 16)
523 else if (Prefix ==
'v' && Reg.Num < 32)
525 else if (Prefix ==
'a' && Reg.Num < 16)
526 Reg.Group = RegAccess;
528 return Error(Reg.StartLoc,
"invalid register");
530 Reg.EndLoc = Parser.getTok().getLoc();
539 bool SystemZAsmParser::parseRegister(
Register &Reg, RegisterGroup Group,
540 const unsigned *Regs,
bool IsAddress) {
541 if (parseRegister(Reg))
543 if (Reg.Group != Group)
544 return Error(Reg.StartLoc,
"invalid operand for instruction");
545 if (Regs && Regs[Reg.Num] == 0)
546 return Error(Reg.StartLoc,
"invalid register pair");
547 if (Reg.Num == 0 && IsAddress)
548 return Error(Reg.StartLoc,
"%r0 used in an address");
550 Reg.Num = Regs[Reg.Num];
555 SystemZAsmParser::OperandMatchResultTy
556 SystemZAsmParser::parseRegister(
OperandVector &Operands, RegisterGroup Group,
559 return MatchOperand_NoMatch;
562 bool IsAddress = (Kind == ADDR32Reg || Kind == ADDR64Reg);
563 if (parseRegister(Reg, Group, Regs, IsAddress))
564 return MatchOperand_ParseFail;
566 Operands.
push_back(SystemZOperand::createReg(Kind, Reg.Num,
567 Reg.StartLoc, Reg.EndLoc));
568 return MatchOperand_Success;
574 bool SystemZAsmParser::parseAddress(
unsigned &Base,
const MCExpr *&Disp,
575 unsigned &Index,
bool &IsVector,
576 const MCExpr *&Length,
const unsigned *Regs,
579 if (getParser().parseExpression(Disp))
593 if (parseRegister(Reg))
595 if (Reg.Group == RegV) {
599 }
else if (Reg.Group == RegGR) {
601 return Error(Reg.StartLoc,
"%r0 used in an address");
605 Index = Regs[Reg.Num];
607 Base = Regs[Reg.Num];
609 return Error(Reg.StartLoc,
"invalid address register");
612 if (getParser().parseExpression(Length))
620 if (parseRegister(Reg, RegGR, Regs, RegKind))
627 return Error(Parser.getTok().getLoc(),
"unexpected token in address");
635 SystemZAsmParser::OperandMatchResultTy
638 SMLoc StartLoc = Parser.getTok().getLoc();
639 unsigned Base, Index;
643 if (parseAddress(Base, Disp, Index, IsVector, Length, Regs, RegKind))
644 return MatchOperand_ParseFail;
646 if (IsVector && MemKind != BDVMem) {
647 Error(StartLoc,
"invalid use of vector addressing");
648 return MatchOperand_ParseFail;
651 if (!IsVector && MemKind == BDVMem) {
652 Error(StartLoc,
"vector index required in address");
653 return MatchOperand_ParseFail;
656 if (Index && MemKind != BDXMem && MemKind != BDVMem) {
657 Error(StartLoc,
"invalid use of indexed addressing");
658 return MatchOperand_ParseFail;
661 if (Length && MemKind != BDLMem) {
662 Error(StartLoc,
"invalid use of length addressing");
663 return MatchOperand_ParseFail;
666 if (!Length && MemKind == BDLMem) {
667 Error(StartLoc,
"missing length in address");
668 return MatchOperand_ParseFail;
673 Operands.
push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp,
674 Index, Length, StartLoc,
676 return MatchOperand_Success;
679 bool SystemZAsmParser::ParseDirective(
AsmToken DirectiveID) {
683 bool SystemZAsmParser::ParseRegister(
unsigned &RegNo,
SMLoc &StartLoc,
686 if (parseRegister(Reg))
688 if (Reg.Group == RegGR)
690 else if (Reg.Group == RegFP)
692 else if (Reg.Group == RegV)
696 return Error(Reg.StartLoc,
"invalid operand for instruction");
697 StartLoc = Reg.StartLoc;
705 Operands.
push_back(SystemZOperand::createToken(Name, NameLoc));
710 if (parseOperand(Operands, Name)) {
711 Parser.eatToEndOfStatement();
718 if (parseOperand(Operands, Name)) {
719 Parser.eatToEndOfStatement();
724 SMLoc Loc = getLexer().getLoc();
725 Parser.eatToEndOfStatement();
726 return Error(Loc,
"unexpected token in argument list");
739 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
740 if (ResTy == MatchOperand_Success)
746 if (ResTy == MatchOperand_ParseFail)
755 if (parseRegister(Reg))
757 Operands.
push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc));
764 SMLoc StartLoc = Parser.getTok().getLoc();
765 unsigned Base, Index;
767 const MCExpr *Expr, *Length;
774 if (Base || Index || Length)
775 Operands.
push_back(SystemZOperand::createInvalid(StartLoc, EndLoc));
777 Operands.
push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
781 bool SystemZAsmParser::MatchAndEmitInstruction(
SMLoc IDLoc,
unsigned &Opcode,
785 bool MatchingInlineAsm) {
787 unsigned MatchResult;
789 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
791 switch (MatchResult) {
797 case Match_MissingFeature: {
798 assert(ErrorInfo &&
"Unknown missing feature!");
801 std::string Msg =
"instruction requires:";
803 for (
unsigned I = 0;
I <
sizeof(ErrorInfo) * 8 - 1; ++
I) {
804 if (ErrorInfo & Mask) {
810 return Error(IDLoc, Msg);
813 case Match_InvalidOperand: {
814 SMLoc ErrorLoc = IDLoc;
815 if (ErrorInfo != ~0ULL) {
816 if (ErrorInfo >= Operands.
size())
817 return Error(IDLoc,
"too few operands for instruction");
819 ErrorLoc = ((SystemZOperand &)*Operands[ErrorInfo]).getStartLoc();
820 if (ErrorLoc ==
SMLoc())
823 return Error(ErrorLoc,
"invalid operand for instruction");
826 case Match_MnemonicFail:
827 return Error(IDLoc,
"invalid instruction");
833 SystemZAsmParser::OperandMatchResultTy
836 return MatchOperand_NoMatch;
839 if (parseRegister(Reg, RegAccess,
nullptr))
840 return MatchOperand_ParseFail;
842 Operands.
push_back(SystemZOperand::createAccessReg(Reg.Num,
845 return MatchOperand_Success;
848 SystemZAsmParser::OperandMatchResultTy
849 SystemZAsmParser::parsePCRel(
OperandVector &Operands, int64_t MinVal,
850 int64_t MaxVal,
bool AllowTLS) {
854 SMLoc StartLoc = Parser.getTok().getLoc();
855 if (getParser().parseExpression(Expr))
856 return MatchOperand_NoMatch;
860 if (
auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
861 int64_t
Value =
CE->getValue();
863 Error(StartLoc,
"offset out of range");
864 return MatchOperand_ParseFail;
874 const MCExpr *Sym =
nullptr;
879 Error(Parser.getTok().getLoc(),
"unexpected token");
880 return MatchOperand_ParseFail;
884 StringRef Name = Parser.getTok().getString();
885 if (Name ==
"tls_gdcall")
887 else if (Name ==
"tls_ldcall")
890 Error(Parser.getTok().getLoc(),
"unknown TLS tag");
891 return MatchOperand_ParseFail;
896 Error(Parser.getTok().getLoc(),
"unexpected token");
897 return MatchOperand_ParseFail;
902 Error(Parser.getTok().getLoc(),
"unexpected token");
903 return MatchOperand_ParseFail;
906 StringRef Identifier = Parser.getTok().getString();
916 Operands.
push_back(SystemZOperand::createImmTLS(Expr, Sym,
919 Operands.
push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
921 return MatchOperand_Success;
static bool isReg(const MCInst &MI, unsigned OpNo)
std::enable_if< std::numeric_limits< T >::is_signed, bool >::type getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
void push_back(const T &Elt)
const unsigned GR32Regs[16]
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
size_t size() const
size - Get the string size.
const unsigned FP128Regs[16]
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Generic assembler parser interface, for use by target specific assembly parsers.
virtual void Initialize(MCAsmParser &Parser)
Initialize the extension for parsing using the given Parser.
static MCOperand createExpr(const MCExpr *Val)
MCTargetAsmParser - Generic interface to target specific assembly parsers.
StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
const unsigned FP32Regs[16]
virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
const unsigned VR64Regs[32]
static MCOperand createReg(unsigned Reg)
std::pair< StringRef, StringRef > getToken(StringRef Source, StringRef Delimiters=" \t\n\v\f\r")
getToken - This function extracts one token from source, ignoring any leading characters that appear ...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Base class for the full range of assembler expressions which are needed for parsing.
Reg
All possible values of the reg field in the ModR/M byte.
Target independent representation for an assembler token.
Windows NT (Windows on ARM)
const unsigned GRH32Regs[16]
MCParsedAsmOperand - This abstract class represents a source-level assembly instruction operand...
Context object for machine code objects.
const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Instances of this class represent a single low-level machine instruction.
Streaming machine code generation interface.
MCSymbol * createTempSymbol(bool CanBeUnnamed=true)
Create and return a new assembler temporary symbol with a unique but unspecified name.
static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue)
Interface to description of machine instruction set.
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang","erlang-compatible garbage collector")
virtual void EmitLabel(MCSymbol *Symbol)
Emit a label for Symbol into the current section.
void LLVMInitializeSystemZAsmParser()
const unsigned FP64Regs[16]
Promote Memory to Register
const unsigned GR128Regs[16]
const unsigned GR64Regs[16]
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
static SMLoc getFromPointer(const char *Ptr)
RegisterMCAsmParser - Helper template for registering a target specific assembly parser, for use in the target machine initialization function.
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
MCSubtargetInfo - Generic base class for all target subtargets.
const unsigned VR32Regs[32]
static bool isMem(const MachineInstr *MI, unsigned Op)
const ARM::ArchExtKind Kind
LLVM Value Representation.
This class implements an extremely fast bulk output stream that can only output to a stream...
void addOperand(const MCOperand &Op)
StringRef - Represent a constant reference to a string, i.e.
Represents a location in source code.
static const char * getSubtargetFeatureName(uint64_t Val)
static MCOperand createImm(int64_t Val)
const unsigned VR128Regs[32]