25 #define DEBUG_TYPE "asm-printer"
27 #include "ARMGenAsmWriter.inc"
34 assert((imm & ~0x1f) == 0 &&
"Invalid shift encoding");
43 unsigned ShImm,
bool UseMarkup) {
48 assert(!(ShOpc ==
ARM_AM::ror && !ShImm) &&
"Cannot have ror #0");
107 if (Opcode == ARM::t2HINT)
156 O <<
", " <<
markup(
"<imm:") <<
"#"
164 case ARM::t2STMDB_UPD:
169 if (Opcode == ARM::t2STMDB_UPD)
178 case ARM::STR_PRE_IMM:
193 case ARM::t2LDMIA_UPD:
198 if (Opcode == ARM::t2LDMIA_UPD)
207 case ARM::LDR_POST_IMM:
221 case ARM::VSTMSDB_UPD:
222 case ARM::VSTMDDB_UPD:
224 O <<
'\t' <<
"vpush";
234 case ARM::VLDMSIA_UPD:
235 case ARM::VLDMDIA_UPD:
247 bool Writeback =
true;
278 bool isStore = Opcode == ARM::STREXD || Opcode == ARM::STLEXD;
302 case ARM::t2SUBS_PC_LR: {
325 }
else if (Op.
isImm()) {
328 assert(Op.
isExpr() &&
"unknown operand kind in printOperand");
330 switch (Expr->getKind()) {
333 Expr->print(O, &
MAI);
343 Expr->print(O, &
MAI);
346 O.
write_hex(static_cast<uint32_t>(TargetAddress));
353 Expr->print(O, &
MAI);
368 O <<
markup(
"<mem:") <<
"[pc, ";
370 int32_t OffImm = (int32_t)MO1.
getImm();
371 bool isSub = OffImm < 0;
374 if (OffImm == INT32_MIN)
433 O <<
markup(
"<mem:") <<
"[";
438 O <<
", " <<
markup(
"<imm:") <<
"#"
460 O <<
markup(
"<mem:") <<
"[";
472 O <<
markup(
"<mem:") <<
"[";
507 O <<
markup(
"<imm:") <<
'#'
526 bool AlwaysPrintImm0) {
531 O <<
markup(
"<mem:") <<
'[';
545 if (AlwaysPrintImm0 || ImmOffs || (op ==
ARM_AM::sub)) {
552 template <
bool AlwaysPr
intImm0>
564 "unexpected idxmode");
582 O <<
markup(
"<imm:") <<
'#'
591 unsigned Imm = MO.
getImm();
592 O <<
markup(
"<imm:") <<
'#' << ((Imm & 256) ?
"" :
"-") << (Imm & 0xff)
602 O << (MO2.
getImm() ?
"" :
"-");
610 unsigned Imm = MO.
getImm();
611 O <<
markup(
"<imm:") <<
'#' << ((Imm & 256) ?
"" :
"-") << ((Imm & 0xff) << 2)
623 template <
bool AlwaysPr
intImm0>
635 O <<
markup(
"<mem:") <<
"[";
640 if (AlwaysPrintImm0 || ImmOffs || Op ==
ARM_AM::sub) {
642 << ImmOffs * 4 <<
markup(
">");
653 O <<
markup(
"<mem:") <<
"[";
656 O <<
":" << (MO2.
getImm() << 3);
665 O <<
markup(
"<mem:") <<
"[";
688 uint32_t v = ~MO.
getImm();
691 assert(MO.
isImm() &&
"Not a valid bf_inv_mask_imm value!");
693 <<
'#' << width <<
markup(
">");
714 bool isASR = (ShiftOp & (1 << 5)) != 0;
715 unsigned Amt = ShiftOp & 0x1f;
717 O <<
", asr " <<
markup(
"<imm:") <<
"#" << (Amt == 0 ? 32 : Amt)
720 O <<
", lsl " <<
markup(
"<imm:") <<
"#" << Amt <<
markup(
">");
730 assert(Imm > 0 && Imm < 32 &&
"Invalid PKH shift immediate value!");
731 O <<
", lsl " <<
markup(
"<imm:") <<
"#" << Imm <<
markup(
">");
741 assert(Imm > 0 && Imm <= 32 &&
"Invalid PKH shift immediate value!");
742 O <<
", asr " <<
markup(
"<imm:") <<
"#" << Imm <<
markup(
">");
786 for (
int i = 2; i >= 0; --i)
787 if (IFlags & (1 << i))
798 unsigned SpecRegRBit = Op.
getImm() >> 4;
799 unsigned Mask = Op.
getImm() & 0xf;
802 if (FeatureBits[ARM::FeatureMClass]) {
803 unsigned SYSm = Op.
getImm();
807 if (Opcode == ARM::t2MSR_M && FeatureBits[ARM::FeatureDSPThumb2]) {
839 if (Opcode == ARM::t2MSR_M && FeatureBits [ARM::HasV7Ops]) {
908 if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
947 uint32_t R = (Banked & 0x20) >> 5;
948 uint32_t SysM = Banked & 0x1f;
982 assert(!R &&
"should have dealt with SPSR regs");
983 const char *RegNames[] = {
984 "r8_usr",
"r9_usr",
"r10_usr",
"r11_usr",
"r12_usr",
"sp_usr",
"lr_usr",
985 "",
"r8_fiq",
"r9_fiq",
"r10_fiq",
"r11_fiq",
"r12_fiq",
"sp_fiq",
986 "lr_fiq",
"",
"lr_irq",
"sp_irq",
"lr_svc",
"sp_svc",
"lr_abt",
987 "sp_abt",
"lr_und",
"sp_und",
"",
"",
"",
"",
988 "lr_mon",
"sp_mon",
"elr_hyp",
"sp_hyp"};
989 const char *
Name = RegNames[SysM];
990 assert(Name[0] &&
"invalid banked register operand");
1000 if ((
unsigned)CC == 15)
1019 "Expect ARM CPSR register!");
1053 template <
unsigned scale>
1067 if (OffImm == INT32_MIN)
1069 else if (OffImm < 0)
1070 O <<
"#-" << -OffImm;
1097 unsigned CondBit0 = Firstcond & 1;
1099 assert(NumTZ <= 3 &&
"Invalid IT mask!");
1100 for (
unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
1101 bool T = ((Mask >> Pos) & 1) == CondBit0;
1120 O <<
markup(
"<mem:") <<
"[";
1122 if (
unsigned RegNum = MO2.
getReg()) {
1142 O <<
markup(
"<mem:") <<
"[";
1144 if (
unsigned ImmOffs = MO2.
getImm()) {
1192 assert(MO2.
isImm() &&
"Not a valid t2_so_reg value!");
1197 template <
bool AlwaysPr
intImm0>
1209 O <<
markup(
"<mem:") <<
"[";
1212 int32_t OffImm = (int32_t)MO2.
getImm();
1213 bool isSub = OffImm < 0;
1215 if (OffImm == INT32_MIN)
1219 }
else if (AlwaysPrintImm0 || OffImm > 0) {
1225 template <
bool AlwaysPr
intImm0>
1233 O <<
markup(
"<mem:") <<
"[";
1236 int32_t OffImm = (int32_t)MO2.
getImm();
1237 bool isSub = OffImm < 0;
1239 if (OffImm == INT32_MIN)
1242 O <<
", " <<
markup(
"<imm:") <<
"#-" << -OffImm <<
markup(
">");
1243 }
else if (AlwaysPrintImm0 || OffImm > 0) {
1244 O <<
", " <<
markup(
"<imm:") <<
"#" << OffImm <<
markup(
">");
1249 template <
bool AlwaysPr
intImm0>
1262 O <<
markup(
"<mem:") <<
"[";
1265 int32_t OffImm = (int32_t)MO2.
getImm();
1266 bool isSub = OffImm < 0;
1268 assert(((OffImm & 0x3) == 0) &&
"Not a valid immediate!");
1271 if (OffImm == INT32_MIN)
1274 O <<
", " <<
markup(
"<imm:") <<
"#-" << -OffImm <<
markup(
">");
1275 }
else if (AlwaysPrintImm0 || OffImm > 0) {
1276 O <<
", " <<
markup(
"<imm:") <<
"#" << OffImm <<
markup(
">");
1287 O <<
markup(
"<mem:") <<
"[";
1300 int32_t OffImm = (int32_t)MO1.
getImm();
1301 O <<
", " <<
markup(
"<imm:");
1302 if (OffImm == INT32_MIN)
1304 else if (OffImm < 0)
1305 O <<
"#-" << -OffImm;
1315 int32_t OffImm = (int32_t)MO1.
getImm();
1317 assert(((OffImm & 0x3) == 0) &&
"Not a valid immediate!");
1319 O <<
", " <<
markup(
"<imm:");
1320 if (OffImm == INT32_MIN)
1322 else if (OffImm < 0)
1323 O <<
"#-" << -OffImm;
1337 O <<
markup(
"<mem:") <<
"[";
1340 assert(MO2.
getReg() &&
"Invalid so_reg load / store address!");
1344 unsigned ShAmt = MO3.
getImm();
1346 assert(ShAmt <= 3 &&
"Not a valid Thumb2 addressing mode!");
1347 O <<
", lsl " <<
markup(
"<imm:") <<
"#" << ShAmt <<
markup(
">");
1366 O <<
markup(
"<imm:") <<
"#0x";
1384 assert(Imm <= 3 &&
"illegal ror immediate!");
1385 O <<
", ror " <<
markup(
"<imm:") <<
"#" << 8 * Imm <<
markup(
">");
1398 unsigned Rot = (Op.
getImm() & 0xF00) >> 7;
1400 bool PrintUnsigned =
false;
1408 PrintUnsigned =
true;
1415 O <<
"#" <<
markup(
"<imm:");
1417 O << static_cast<uint32_t>(Rotated);
void printVectorListTwoAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static uint64_t scale(uint64_t Num, uint32_t N, uint32_t D)
void printThumbAddrModeImm5S1Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrMode3OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printNoHashImmediate(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static unsigned char getAM3Offset(unsigned AM3Opc)
void printVectorListThreeAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printT2AddrModeImm8Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrModeTBB(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbAddrModeImm5S2Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printBankedRegOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static const char * getShiftOpcStr(ShiftOpc Op)
void printBitfieldInvMaskImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printT2AddrModeImm8s4Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
std::size_t countLeadingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the most significant bit to the least stopping at the first 1...
void printAddrMode7Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static unsigned rotr32(unsigned Val, unsigned Amt)
rotr32 - Rotate a 32-bit unsigned value right by a specified # bits.
void printPKHASRShiftImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static unsigned translateShiftImm(unsigned imm)
translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
void printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static unsigned getAM3IdxMode(unsigned AM3Opc)
void printThumbAddrModeSPOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static MCOperand createReg(unsigned Reg)
void printT2AddrModeImm8s4OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListThree(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListTwoSpacedAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void printT2AddrModeImm8OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printLdStmModeOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Base class for the full range of assembler expressions which are needed for parsing.
Reg
All possible values of the reg field in the ModR/M byte.
static AMSubMode getAM4SubMode(unsigned Mode)
void printFBits32(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printCoprocOptionImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printCPSIFlag(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
unsigned getReg() const
Returns the register number.
raw_ostream & write_hex(unsigned long long N)
Output N in hexadecimal, without any prefix or padding.
void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O)
void printSBitModifierOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static const char * getRegisterName(unsigned RegNo)
MCRegisterClass - Base class of TargetRegisterClass.
Instances of this class represent a single low-level machine instruction.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
This class is intended to be used as a base class for asm properties and features specific to the tar...
static unsigned getAM2IdxMode(unsigned AM2Opc)
const MCExpr * getExpr() const
void print(raw_ostream &OS, const MCAsmInfo *MAI) const
void printThumbSRImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printPostIdxImm8s4Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printMandatoryPredicateOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
std::size_t countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the least significant bit to the most stopping at the first 1...
static const char * InstSyncBOptToString(unsigned val)
void printGPRPairOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
StringRef markup(StringRef s) const
Utility functions to make adding mark ups simpler.
void printRegisterList(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
This is an important base class in LLVM.
static unsigned char getAM5Offset(unsigned AM5Opc)
void printThumbAddrModeImm5S4Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
Interface to description of machine instruction set.
void printVectorListOne(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListTwo(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrModeTBH(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorIndex(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrMode6Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printRotImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printMemBOption(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrMode5Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printSORegRegOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static const char * getAddrOpcStr(AddrOpc Op)
void printThumbAddrModeRROperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAdrLabelOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printCImmediate(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
format_object< int64_t > formatImm(int64_t Value) const
Utility function to print immediates in decimal or hex.
void printVectorListFourSpacedAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg...
static const char * ARMCondCodeToString(ARMCC::CondCodes CC)
static const char * IModToString(unsigned val)
static AddrOpc getAM2Op(unsigned AM2Opc)
void printPostIdxRegOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListFourSpaced(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void setOpcode(unsigned Op)
void printFBits16(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
bool contains(unsigned Reg) const
contains - Return true if the specified register is included in this register class.
void printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static unsigned getAM2Offset(unsigned AM2Opc)
void printVectorListThreeSpaced(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
ARMInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
uint64_t TargetAddress
Represents an address in the target process's address space.
void printPCLabel(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrMode6OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
unsigned getOpcode() const
static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc, unsigned ShImm, bool UseMarkup)
Prints the shift value with an immediate value.
static const char * MemBOptToString(unsigned val, bool HasV8)
static AddrOpc getAM3Op(unsigned AM3Opc)
static const char * IFlagsToString(unsigned val)
static int getSOImmVal(unsigned Arg)
getSOImmVal - Given a 32-bit immediate, if it is something that can fit into an shifter_operand immed...
static const char * getAMSubModeStr(AMSubMode Mode)
void printVectorListFourAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbAddrModeImm5SOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O, unsigned Scale)
bool UseMarkup
True if we are printing marked up assembly.
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
void printT2SOOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrMode2Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
unsigned getNumOperands() const
void printT2AddrModeImm0_1020s4Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
MCSubtargetInfo - Generic base class for all target subtargets.
void printVectorListFour(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
bool evaluateAsAbsolute(int64_t &Res, const MCAsmLayout &Layout, const SectionAddrMap &Addrs) const
Try to evaluate the expression to an absolute value.
void printT2AddrModeSoRegOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static AddrOpc getAM5Op(unsigned AM5Opc)
void printPostIdxImm8Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListOneAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printImmPlusOneOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrMode2OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printNEONModImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static ShiftOpc getAM2ShiftOpc(unsigned AM2Opc)
void printSetendOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static unsigned getSORegOffset(unsigned Op)
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
void printMSRMaskOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
This class implements an extremely fast bulk output stream that can only output to a stream...
void printVectorListThreeSpacedAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void addOperand(const MCOperand &Op)
StringRef - Represent a constant reference to a string, i.e.
void printPImmediate(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbITMask(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printShiftImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op, raw_ostream &O, bool AlwaysPrintImm0)
Instances of this class represent operands of the MCInst class.
void printAddrMode3Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printSORegImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static float getFPImmFloat(unsigned Imm)
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, const MCSubtargetInfo &STI) override
Print the specified MCInst to the specified raw_ostream.
void printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
const MCOperand & getOperand(unsigned i) const
void printPredicateOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printRegName(raw_ostream &OS, unsigned RegNo) const override
Print the assembler register name.
void printInstSyncBOption(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printFPImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printCPSIMod(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static ShiftOpc getSORegShOp(unsigned Op)
const MCRegisterInfo & MRI
static uint64_t decodeNEONModImm(unsigned ModImm, unsigned &EltBits)
decodeNEONModImm - Decode a NEON modified immediate value into the element value and the element size...
void printModImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)