LLVM  3.7.0
Public Member Functions | Static Public Member Functions | List of all members
llvm::SIInstrInfo Class Reference

#include <SIInstrInfo.h>

Inheritance diagram for llvm::SIInstrInfo:
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Collaboration diagram for llvm::SIInstrInfo:
[legend]

Public Member Functions

 SIInstrInfo (const AMDGPUSubtarget &st)
 
const SIRegisterInfogetRegisterInfo () const override
 
bool isReallyTriviallyReMaterializable (const MachineInstr *MI, AliasAnalysis *AA) const override
 
bool areLoadsFromSameBasePtr (SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
 
bool getMemOpBaseRegImmOfs (MachineInstr *LdSt, unsigned &BaseReg, unsigned &Offset, const TargetRegisterInfo *TRI) const final
 
bool shouldClusterLoads (MachineInstr *FirstLdSt, MachineInstr *SecondLdSt, unsigned NumLoads) const final
 
void copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
 
unsigned calculateLDSSpillAddress (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, RegScavenger *RS, unsigned TmpReg, unsigned Offset, unsigned Size) const
 
void storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
 
void loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
 
bool expandPostRAPseudo (MachineBasicBlock::iterator MI) const override
 
unsigned getMovOpcode (const TargetRegisterClass *DstRC) const
 
int commuteOpcode (const MachineInstr &MI) const
 
MachineInstrcommuteInstruction (MachineInstr *MI, bool NewMI=false) const override
 
bool findCommutedOpIndices (MachineInstr *MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
 
bool isTriviallyReMaterializable (const MachineInstr *MI, AliasAnalysis *AA=nullptr) const
 
bool areMemAccessesTriviallyDisjoint (MachineInstr *MIa, MachineInstr *MIb, AliasAnalysis *AA=nullptr) const override
 
MachineInstrbuildMovInstr (MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned DstReg, unsigned SrcReg) const override
 Build a MOV instruction. More...
 
bool isMov (unsigned Opcode) const override
 
bool isSafeToMoveRegClassDefs (const TargetRegisterClass *RC) const override
 
bool FoldImmediate (MachineInstr *UseMI, MachineInstr *DefMI, unsigned Reg, MachineRegisterInfo *MRI) const final
 
unsigned getMachineCSELookAheadLimit () const override
 
MachineInstrconvertToThreeAddress (MachineFunction::iterator &MBB, MachineBasicBlock::iterator &MI, LiveVariables *LV) const override
 
bool isSALU (uint16_t Opcode) const
 
bool isVALU (uint16_t Opcode) const
 
bool isSOP1 (uint16_t Opcode) const
 
bool isSOP2 (uint16_t Opcode) const
 
bool isSOPC (uint16_t Opcode) const
 
bool isSOPK (uint16_t Opcode) const
 
bool isSOPP (uint16_t Opcode) const
 
bool isVOP1 (uint16_t Opcode) const
 
bool isVOP2 (uint16_t Opcode) const
 
bool isVOP3 (uint16_t Opcode) const
 
bool isVOPC (uint16_t Opcode) const
 
bool isMUBUF (uint16_t Opcode) const
 
bool isMTBUF (uint16_t Opcode) const
 
bool isSMRD (uint16_t Opcode) const
 
bool isDS (uint16_t Opcode) const
 
bool isMIMG (uint16_t Opcode) const
 
bool isFLAT (uint16_t Opcode) const
 
bool isWQM (uint16_t Opcode) const
 
bool isVGPRSpill (uint16_t Opcode) const
 
bool isInlineConstant (const APInt &Imm) const
 
bool isInlineConstant (const MachineOperand &MO, unsigned OpSize) const
 
bool isLiteralConstant (const MachineOperand &MO, unsigned OpSize) const
 
bool isImmOperandLegal (const MachineInstr *MI, unsigned OpNo, const MachineOperand &MO) const
 
bool hasVALU32BitEncoding (unsigned Opcode) const
 Return true if this 64-bit VALU instruction has a 32-bit encoding. More...
 
bool usesConstantBus (const MachineRegisterInfo &MRI, const MachineOperand &MO, unsigned OpSize) const
 Returns true if this operand uses the constant bus. More...
 
bool hasModifiers (unsigned Opcode) const
 Return true if this instruction has any modifiers. More...
 
bool hasModifiersSet (const MachineInstr &MI, unsigned OpName) const
 
bool verifyInstruction (const MachineInstr *MI, StringRef &ErrInfo) const override
 
bool isSALUOpSupportedOnVALU (const MachineInstr &MI) const
 
const TargetRegisterClassgetOpRegClass (const MachineInstr &MI, unsigned OpNo) const
 Return the correct register class for OpNo. More...
 
unsigned getOpSize (uint16_t Opcode, unsigned OpNo) const
 Return the size in bytes of the operand OpNo on the given. More...
 
unsigned getOpSize (const MachineInstr &MI, unsigned OpNo) const
 This form should usually be preferred since it handles operands with unknown register classes. More...
 
bool canReadVGPR (const MachineInstr &MI, unsigned OpNo) const
 
void legalizeOpWithMove (MachineInstr *MI, unsigned OpIdx) const
 Legalize the OpIndex operand of this instruction by inserting a MOV. More...
 
bool isOperandLegal (const MachineInstr *MI, unsigned OpIdx, const MachineOperand *MO=nullptr) const
 Check if MO is a legal operand if it was the OpIdx Operand for MI. More...
 
void legalizeOperands (MachineInstr *MI) const
 Legalize all operands in this instruction. More...
 
void splitSMRD (MachineInstr *MI, const TargetRegisterClass *HalfRC, unsigned HalfImmOp, unsigned HalfSGPROp, MachineInstr *&Lo, MachineInstr *&Hi) const
 Split an SMRD instruction into two smaller loads of half the. More...
 
void moveSMRDToVALU (MachineInstr *MI, MachineRegisterInfo &MRI) const
 
void moveToVALU (MachineInstr &MI) const
 Replace this instruction's opcode with the equivalent VALU opcode. More...
 
unsigned calculateIndirectAddress (unsigned RegIndex, unsigned Channel) const override
 Calculate the "Indirect Address" for the given RegIndex and Channel. More...
 
const TargetRegisterClassgetIndirectAddrRegClass () const override
 
MachineInstrBuilder buildIndirectWrite (MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned ValueReg, unsigned Address, unsigned OffsetReg) const override
 Build instruction(s) for an indirect register write. More...
 
MachineInstrBuilder buildIndirectRead (MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned ValueReg, unsigned Address, unsigned OffsetReg) const override
 Build instruction(s) for an indirect register read. More...
 
void reserveIndirectRegisters (BitVector &Reserved, const MachineFunction &MF) const
 
void LoadM0 (MachineInstr *MoveRel, MachineBasicBlock::iterator I, unsigned SavReg, unsigned IndexReg) const
 
void insertNOPs (MachineBasicBlock::iterator MI, int Count) const
 
MachineOperandgetNamedOperand (MachineInstr &MI, unsigned OperandName) const
 Returns the operand named Op. More...
 
const MachineOperandgetNamedOperand (const MachineInstr &MI, unsigned OpName) const
 
uint64_t getDefaultRsrcDataFormat () const
 
- Public Member Functions inherited from llvm::AMDGPUInstrInfo
 AMDGPUInstrInfo (const AMDGPUSubtarget &st)
 
bool isCoalescableExtInstr (const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override
 
unsigned isLoadFromStackSlot (const MachineInstr *MI, int &FrameIndex) const override
 
unsigned isLoadFromStackSlotPostFE (const MachineInstr *MI, int &FrameIndex) const override
 
bool hasLoadFromStackSlot (const MachineInstr *MI, const MachineMemOperand *&MMO, int &FrameIndex) const override
 
unsigned isStoreFromStackSlot (const MachineInstr *MI, int &FrameIndex) const
 
unsigned isStoreFromStackSlotPostFE (const MachineInstr *MI, int &FrameIndex) const
 
bool hasStoreFromStackSlot (const MachineInstr *MI, const MachineMemOperand *&MMO, int &FrameIndex) const
 
MachineInstrconvertToThreeAddress (MachineFunction::iterator &MFI, MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const override
 
bool expandPostRAPseudo (MachineBasicBlock::iterator MI) const override
 
void storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
 
void loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
 
int getIndirectIndexBegin (const MachineFunction &MF) const
 
int getIndirectIndexEnd (const MachineFunction &MF) const
 
bool canFoldMemoryOperand (const MachineInstr *MI, ArrayRef< unsigned > Ops) const override
 
bool unfoldMemoryOperand (MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const override
 
bool unfoldMemoryOperand (SelectionDAG &DAG, SDNode *N, SmallVectorImpl< SDNode * > &NewNodes) const override
 
unsigned getOpcodeAfterMemoryUnfold (unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const override
 
bool enableClusterLoads () const override
 
bool shouldScheduleLoadsNear (SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override
 
bool ReverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
 
void insertNoop (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
 
bool isPredicated (const MachineInstr *MI) const override
 
bool SubsumesPredicate (ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
 
bool DefinesPredicate (MachineInstr *MI, std::vector< MachineOperand > &Pred) const override
 
bool isPredicable (MachineInstr *MI) const override
 
bool isSafeToMoveRegClassDefs (const TargetRegisterClass *RC) const override
 
bool isRegisterStore (const MachineInstr &MI) const
 
bool isRegisterLoad (const MachineInstr &MI) const
 
int pseudoToMCOpcode (int Opcode) const
 Return a target-specific opcode if Opcode is a pseudo instruction. More...
 
const MCInstrDescgetMCOpcodeFromPseudo (unsigned Opcode) const
 Return the descriptor of the target-specific machine instruction that corresponds to the specified pseudo or native opcode. More...
 
int getMaskedMIMGOp (uint16_t Opcode, unsigned Channels) const
 Given a MIMG Opcode that writes all 4 channels, return the equivalent opcode that writes Channels Channels. More...
 

Static Public Member Functions

static unsigned getVALUOp (const MachineInstr &MI)
 

Additional Inherited Members

- Protected Member Functions inherited from llvm::AMDGPUInstrInfo
MachineInstrfoldMemoryOperandImpl (MachineFunction &MF, MachineInstr *MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex) const override
 
MachineInstrfoldMemoryOperandImpl (MachineFunction &MF, MachineInstr *MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr *LoadMI) const override
 
- Protected Attributes inherited from llvm::AMDGPUInstrInfo
const AMDGPUSubtargetST
 

Detailed Description

Definition at line 25 of file SIInstrInfo.h.

Constructor & Destructor Documentation

SIInstrInfo::SIInstrInfo ( const AMDGPUSubtarget st)
explicit

Definition at line 30 of file SIInstrInfo.cpp.

Member Function Documentation

bool SIInstrInfo::areLoadsFromSameBasePtr ( SDNode Load1,
SDNode Load2,
int64_t &  Offset1,
int64_t &  Offset2 
) const
override
bool SIInstrInfo::areMemAccessesTriviallyDisjoint ( MachineInstr MIa,
MachineInstr MIb,
AliasAnalysis AA = nullptr 
) const
override
MachineInstrBuilder SIInstrInfo::buildIndirectRead ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
unsigned  ValueReg,
unsigned  Address,
unsigned  OffsetReg 
) const
overridevirtual
MachineInstrBuilder SIInstrInfo::buildIndirectWrite ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
unsigned  ValueReg,
unsigned  Address,
unsigned  OffsetReg 
) const
overridevirtual
MachineInstr * SIInstrInfo::buildMovInstr ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
unsigned  DstReg,
unsigned  SrcReg 
) const
overridevirtual

Build a MOV instruction.

Implements llvm::AMDGPUInstrInfo.

Definition at line 882 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), and llvm::MachineBasicBlock::findDebugLoc().

unsigned SIInstrInfo::calculateIndirectAddress ( unsigned  RegIndex,
unsigned  Channel 
) const
overridevirtual

Calculate the "Indirect Address" for the given RegIndex and Channel.

We model indirect addressing using a virtual address space that can be accesed with loads and stores. The "Indirect Address" is the memory address in this virtual address space that maps to the given RegIndex and Channel.

Implements llvm::AMDGPUInstrInfo.

Definition at line 2383 of file SIInstrInfo.cpp.

unsigned SIInstrInfo::calculateLDSSpillAddress ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
RegScavenger RS,
unsigned  TmpReg,
unsigned  FrameOffset,
unsigned  Size 
) const
bool SIInstrInfo::canReadVGPR ( const MachineInstr MI,
unsigned  OpNo 
) const
Returns
true if it is legal for the operand at index OpNo to read a VGPR.

Definition at line 1519 of file SIInstrInfo.cpp.

References llvm::TargetOpcode::COPY, llvm::MachineInstr::getOpcode(), getOpRegClass(), llvm::SIRegisterInfo::hasVGPRs(), llvm::TargetOpcode::INSERT_SUBREG, llvm::TargetOpcode::PHI, and llvm::TargetOpcode::REG_SEQUENCE.

Referenced by moveToVALU().

MachineInstr * SIInstrInfo::commuteInstruction ( MachineInstr MI,
bool  NewMI = false 
) const
override
int SIInstrInfo::commuteOpcode ( const MachineInstr MI) const
MachineInstr * SIInstrInfo::convertToThreeAddress ( MachineFunction::iterator MBB,
MachineBasicBlock::iterator MI,
LiveVariables LV 
) const
override
void SIInstrInfo::copyPhysReg ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
DebugLoc  DL,
unsigned  DestReg,
unsigned  SrcReg,
bool  KillSrc 
) const
override
bool SIInstrInfo::expandPostRAPseudo ( MachineBasicBlock::iterator  MI) const
override
bool SIInstrInfo::findCommutedOpIndices ( MachineInstr MI,
unsigned SrcOpIdx1,
unsigned SrcOpIdx2 
) const
override
bool SIInstrInfo::FoldImmediate ( MachineInstr UseMI,
MachineInstr DefMI,
unsigned  Reg,
MachineRegisterInfo MRI 
) const
final
uint64_t SIInstrInfo::getDefaultRsrcDataFormat ( ) const
const TargetRegisterClass * SIInstrInfo::getIndirectAddrRegClass ( ) const
overridevirtual
Returns
The register class to be used for loading and storing values from an "Indirect Address" .

Implements llvm::AMDGPUInstrInfo.

Definition at line 2389 of file SIInstrInfo.cpp.

unsigned llvm::SIInstrInfo::getMachineCSELookAheadLimit ( ) const
inlineoverride

Definition at line 145 of file SIInstrInfo.h.

bool SIInstrInfo::getMemOpBaseRegImmOfs ( MachineInstr LdSt,
unsigned BaseReg,
unsigned Offset,
const TargetRegisterInfo TRI 
) const
final
unsigned SIInstrInfo::getMovOpcode ( const TargetRegisterClass DstRC) const
MachineOperand * SIInstrInfo::getNamedOperand ( MachineInstr MI,
unsigned  OperandName 
) const
const MachineOperand* llvm::SIInstrInfo::getNamedOperand ( const MachineInstr MI,
unsigned  OpName 
) const
inline

Definition at line 350 of file SIInstrInfo.h.

References getNamedOperand().

const TargetRegisterClass * SIInstrInfo::getOpRegClass ( const MachineInstr MI,
unsigned  OpNo 
) const

Return the correct register class for OpNo.

For target-specific instructions, this will return the register class that has been defined in tablegen. For generic instructions, like REG_SEQUENCE it will return the register class of its machine operand. to infer the correct register class base on the other operands.

Definition at line 1502 of file SIInstrInfo.cpp.

References llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::SIRegisterInfo::getPhysRegClass(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::MachineInstr::isVariadic(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::MCInstrDesc::OpInfo, and llvm::MCOperandInfo::RegClass.

Referenced by canReadVGPR(), getMemOpBaseRegImmOfs(), getOpSize(), legalizeOperands(), and moveToVALU().

unsigned llvm::SIInstrInfo::getOpSize ( uint16_t  Opcode,
unsigned  OpNo 
) const
inline

Return the size in bytes of the operand OpNo on the given.

Definition at line 267 of file SIInstrInfo.h.

References llvm::MCOI::OPERAND_IMMEDIATE, llvm::MCOperandInfo::OperandType, and llvm::MCOperandInfo::RegClass.

Referenced by foldImmediates(), isOperandLegal(), legalizeOperands(), and verifyInstruction().

unsigned llvm::SIInstrInfo::getOpSize ( const MachineInstr MI,
unsigned  OpNo 
) const
inline

This form should usually be preferred since it handles operands with unknown register classes.

Definition at line 281 of file SIInstrInfo.h.

References getOpRegClass(), and llvm::TargetRegisterClass::getSize().

const SIRegisterInfo& llvm::SIInstrInfo::getRegisterInfo ( ) const
inlineoverridevirtual

Implements llvm::AMDGPUInstrInfo.

Definition at line 71 of file SIInstrInfo.h.

Referenced by foldImmediates().

unsigned SIInstrInfo::getVALUOp ( const MachineInstr MI)
static
bool SIInstrInfo::hasModifiers ( unsigned  Opcode) const

Return true if this instruction has any modifiers.

e.g. src[012]_mod, omod, clamp.

Definition at line 1276 of file SIInstrInfo.cpp.

References llvm::AMDGPU::getNamedOperandIdx().

bool SIInstrInfo::hasModifiersSet ( const MachineInstr MI,
unsigned  OpName 
) const
bool SIInstrInfo::hasVALU32BitEncoding ( unsigned  Opcode) const

Return true if this 64-bit VALU instruction has a 32-bit encoding.

This function will return false if you pass it a 32-bit instruction.

Definition at line 1268 of file SIInstrInfo.cpp.

References llvm::AMDGPU::getVOPe32(), and llvm::AMDGPUInstrInfo::pseudoToMCOpcode().

void SIInstrInfo::insertNOPs ( MachineBasicBlock::iterator  MI,
int  Count 
) const
bool llvm::SIInstrInfo::isDS ( uint16_t  Opcode) const
inline
bool llvm::SIInstrInfo::isFLAT ( uint16_t  Opcode) const
inline

Definition at line 215 of file SIInstrInfo.h.

References SIInstrFlags::FLAT.

Referenced by areMemAccessesTriviallyDisjoint().

bool SIInstrInfo::isImmOperandLegal ( const MachineInstr MI,
unsigned  OpNo,
const MachineOperand MO 
) const
bool SIInstrInfo::isInlineConstant ( const APInt Imm) const
bool SIInstrInfo::isInlineConstant ( const MachineOperand MO,
unsigned  OpSize 
) const
bool SIInstrInfo::isLiteralConstant ( const MachineOperand MO,
unsigned  OpSize 
) const
bool llvm::SIInstrInfo::isMIMG ( uint16_t  Opcode) const
inline
bool SIInstrInfo::isMov ( unsigned  Opcode) const
overridevirtual

Implements llvm::AMDGPUInstrInfo.

Definition at line 890 of file SIInstrInfo.cpp.

bool llvm::SIInstrInfo::isMTBUF ( uint16_t  Opcode) const
inline
bool llvm::SIInstrInfo::isMUBUF ( uint16_t  Opcode) const
inline
bool SIInstrInfo::isOperandLegal ( const MachineInstr MI,
unsigned  OpIdx,
const MachineOperand MO = nullptr 
) const
bool SIInstrInfo::isReallyTriviallyReMaterializable ( const MachineInstr MI,
AliasAnalysis AA 
) const
override

Definition at line 77 of file SIInstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

bool SIInstrInfo::isSafeToMoveRegClassDefs ( const TargetRegisterClass RC) const
override

Definition at line 902 of file SIInstrInfo.cpp.

bool llvm::SIInstrInfo::isSALU ( uint16_t  Opcode) const
inline

Definition at line 151 of file SIInstrInfo.h.

References SIInstrFlags::SALU.

bool SIInstrInfo::isSALUOpSupportedOnVALU ( const MachineInstr MI) const

Definition at line 1498 of file SIInstrInfo.cpp.

References getVALUOp().

bool llvm::SIInstrInfo::isSMRD ( uint16_t  Opcode) const
inline
bool llvm::SIInstrInfo::isSOP1 ( uint16_t  Opcode) const
inline

Definition at line 159 of file SIInstrInfo.h.

References SIInstrFlags::SOP1.

bool llvm::SIInstrInfo::isSOP2 ( uint16_t  Opcode) const
inline

Definition at line 163 of file SIInstrInfo.h.

References SIInstrFlags::SOP2.

bool llvm::SIInstrInfo::isSOPC ( uint16_t  Opcode) const
inline

Definition at line 167 of file SIInstrInfo.h.

References SIInstrFlags::SOPC.

bool llvm::SIInstrInfo::isSOPK ( uint16_t  Opcode) const
inline

Definition at line 171 of file SIInstrInfo.h.

References SIInstrFlags::SOPK.

bool llvm::SIInstrInfo::isSOPP ( uint16_t  Opcode) const
inline

Definition at line 175 of file SIInstrInfo.h.

References SIInstrFlags::SOPP.

bool SIInstrInfo::isTriviallyReMaterializable ( const MachineInstr MI,
AliasAnalysis AA = nullptr 
) const
bool llvm::SIInstrInfo::isVALU ( uint16_t  Opcode) const
inline

Definition at line 155 of file SIInstrInfo.h.

References SIInstrFlags::VALU.

Referenced by isOperandLegal().

bool llvm::SIInstrInfo::isVGPRSpill ( uint16_t  Opcode) const
inline

Definition at line 223 of file SIInstrInfo.h.

References SIInstrFlags::VGPRSpill.

bool llvm::SIInstrInfo::isVOP1 ( uint16_t  Opcode) const
inline

Definition at line 179 of file SIInstrInfo.h.

References SIInstrFlags::VOP1.

Referenced by foldImmediates(), and verifyInstruction().

bool llvm::SIInstrInfo::isVOP2 ( uint16_t  Opcode) const
inline
bool llvm::SIInstrInfo::isVOP3 ( uint16_t  Opcode) const
inline

Definition at line 187 of file SIInstrInfo.h.

References SIInstrFlags::VOP3.

Referenced by commuteInstruction(), legalizeOperands(), and verifyInstruction().

bool llvm::SIInstrInfo::isVOPC ( uint16_t  Opcode) const
inline

Definition at line 191 of file SIInstrInfo.h.

References SIInstrFlags::VOPC.

Referenced by foldImmediates(), and verifyInstruction().

bool llvm::SIInstrInfo::isWQM ( uint16_t  Opcode) const
inline

Definition at line 219 of file SIInstrInfo.h.

References SIInstrFlags::WQM.

void SIInstrInfo::legalizeOperands ( MachineInstr MI) const

Legalize all operands in this instruction.

This function may create new instruction and insert them before MI.

Definition at line 1702 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addOperand(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), commuteInstruction(), llvm::TargetOpcode::COPY, llvm::MachineRegisterInfo::createVirtualRegister(), llvm::AMDGPU::getAddr64Inst(), llvm::MachineInstr::getDebugLoc(), getDefaultRsrcDataFormat(), llvm::SIRegisterInfo::getEquivalentVGPRClass(), llvm::MachineBasicBlock::getFirstTerminator(), llvm::MachineOperand::getMBB(), getNamedOperand(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getOpRegClass(), getOpSize(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::SIRegisterInfo::hasVGPRs(), llvm::RegState::Implicit, llvm::RegState::ImplicitDefine, llvm::TargetOpcode::INSERT_SUBREG, llvm::MachineInstr::isCommutable(), isLiteralConstant(), isOperandLegal(), llvm::MachineOperand::isReg(), llvm::SIRegisterInfo::isSGPRClass(), llvm::TargetRegisterInfo::isVirtualRegister(), isVOP2(), isVOP3(), legalizeOpWithMove(), llvm::AArch64CC::MI, llvm::TargetOpcode::PHI, llvm::TargetOpcode::REG_SEQUENCE, llvm::MachineInstr::removeFromParent(), and llvm::MachineOperand::setReg().

Referenced by llvm::SITargetLowering::AdjustInstrPostInstrSelection(), and moveToVALU().

void SIInstrInfo::legalizeOpWithMove ( MachineInstr MI,
unsigned  OpIdx 
) const
void llvm::SIInstrInfo::LoadM0 ( MachineInstr MoveRel,
MachineBasicBlock::iterator  I,
unsigned  SavReg,
unsigned  IndexReg 
) const
void SIInstrInfo::loadRegFromStackSlot ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
unsigned  DestReg,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI 
) const
override
void SIInstrInfo::moveSMRDToVALU ( MachineInstr MI,
MachineRegisterInfo MRI 
) const
void SIInstrInfo::moveToVALU ( MachineInstr MI) const

Replace this instruction's opcode with the equivalent VALU opcode.

This function will also move the users of MI to the VALU if necessary.

Definition at line 2173 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addOperand(), llvm::MachineInstr::addOperand(), llvm::BuildMI(), canReadVGPR(), llvm::TargetOpcode::COPY, llvm::MachineOperand::CreateImm(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::SmallVectorBase::empty(), llvm::MachineInstr::eraseFromParent(), llvm::MachineInstr::getDebugLoc(), llvm::SIRegisterInfo::getEquivalentVGPRClass(), llvm::AMDGPUSubtarget::getGeneration(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getOpRegClass(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), getVALUOp(), llvm::SIRegisterInfo::hasVGPRs(), I, llvm::TargetOpcode::INSERT_SUBREG, llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), isSMRD(), legalizeOperands(), llvm_unreachable, moveSMRDToVALU(), llvm::TargetOpcode::PHI, llvm::SmallVectorImpl< T >::pop_back_val(), llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::TargetOpcode::REG_SEQUENCE, llvm::MachineInstr::RemoveOperand(), llvm::MachineRegisterInfo::replaceRegWith(), llvm::MachineInstr::setDesc(), llvm::AMDGPUInstrInfo::ST, llvm::MachineRegisterInfo::use_begin(), llvm::MachineRegisterInfo::use_end(), and llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS.

void SIInstrInfo::reserveIndirectRegisters ( BitVector Reserved,
const MachineFunction MF 
) const
bool SIInstrInfo::shouldClusterLoads ( MachineInstr FirstLdSt,
MachineInstr SecondLdSt,
unsigned  NumLoads 
) const
final

Definition at line 289 of file SIInstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), isDS(), isMTBUF(), isMUBUF(), and isSMRD().

void SIInstrInfo::splitSMRD ( MachineInstr MI,
const TargetRegisterClass HalfRC,
unsigned  HalfImmOp,
unsigned  HalfSGPROp,
MachineInstr *&  Lo,
MachineInstr *&  Hi 
) const
void SIInstrInfo::storeRegToStackSlot ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
unsigned  SrcReg,
bool  isKill,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI 
) const
override
bool SIInstrInfo::usesConstantBus ( const MachineRegisterInfo MRI,
const MachineOperand MO,
unsigned  OpSize 
) const
bool SIInstrInfo::verifyInstruction ( const MachineInstr MI,
StringRef ErrInfo 
) const
override

The documentation for this class was generated from the following files: