LLVM  3.7.0
Enumerations
llvm::AMDGPUISD Namespace Reference

Enumerations

enum  NodeType : unsigned {
  FIRST_NUMBER = ISD::BUILTIN_OP_END, CALL, UMUL, RET_FLAG,
  BRANCH_COND, DWORDADDR, FRACT, CLAMP,
  COS_HW, SIN_HW, FMAX_LEGACY, FMIN_LEGACY,
  FMAX3, SMAX3, UMAX3, FMIN3,
  SMIN3, UMIN3, URECIP, DIV_SCALE,
  DIV_FMAS, DIV_FIXUP, TRIG_PREOP, RCP,
  RSQ, RSQ_LEGACY, RSQ_CLAMPED, LDEXP,
  FP_CLASS, DOT4, CARRY, BORROW,
  BFE_U32, BFE_I32, BFI, BFM,
  BREV, MUL_U24, MUL_I24, MAD_U24,
  MAD_I24, TEXTURE_FETCH, EXPORT, CONST_ADDRESS,
  REGISTER_LOAD, REGISTER_STORE, LOAD_INPUT, SAMPLE,
  SAMPLEB, SAMPLED, SAMPLEL, CVT_F32_UBYTE0,
  CVT_F32_UBYTE1, CVT_F32_UBYTE2, CVT_F32_UBYTE3, BUILD_VERTICAL_VECTOR,
  CONST_DATA_PTR, SENDMSG, INTERP_MOV, INTERP_P1,
  INTERP_P2, FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE, STORE_MSKOR, LOAD_CONSTANT,
  TBUFFER_STORE_FORMAT, LAST_AMDGPU_ISD_NUMBER
}
 

Enumeration Type Documentation

Enumerator
FIRST_NUMBER 
CALL 
UMUL 
RET_FLAG 
BRANCH_COND 
DWORDADDR 
FRACT 
CLAMP 
COS_HW 
SIN_HW 
FMAX_LEGACY 
FMIN_LEGACY 
FMAX3 
SMAX3 
UMAX3 
FMIN3 
SMIN3 
UMIN3 
URECIP 
DIV_SCALE 
DIV_FMAS 
DIV_FIXUP 
TRIG_PREOP 
RCP 
RSQ 
RSQ_LEGACY 
RSQ_CLAMPED 
LDEXP 
FP_CLASS 
DOT4 
CARRY 
BORROW 
BFE_U32 
BFE_I32 
BFI 
BFM 
BREV 
MUL_U24 
MUL_I24 
MAD_U24 
MAD_I24 
TEXTURE_FETCH 
EXPORT 
CONST_ADDRESS 
REGISTER_LOAD 
REGISTER_STORE 
LOAD_INPUT 
SAMPLE 
SAMPLEB 
SAMPLED 
SAMPLEL 
CVT_F32_UBYTE0 
CVT_F32_UBYTE1 
CVT_F32_UBYTE2 
CVT_F32_UBYTE3 
BUILD_VERTICAL_VECTOR 

This node is for VLIW targets and it is used to represent a vector that is stored in consecutive registers with the same channel.

For example: |X |Y|Z|W| T0|v.x| | | | T1|v.y| | | | T2|v.z| | | | T3|v.w| | | |

CONST_DATA_PTR 

Pointer to the start of the shader's constant data.

SENDMSG 
INTERP_MOV 
INTERP_P1 
INTERP_P2 
FIRST_MEM_OPCODE_NUMBER 
STORE_MSKOR 
LOAD_CONSTANT 
TBUFFER_STORE_FORMAT 
LAST_AMDGPU_ISD_NUMBER 

Definition at line 225 of file AMDGPUISelLowering.h.