LLVM  3.7.0
Public Types | Public Member Functions | List of all members
llvm::HexagonInstrInfo Class Reference

#include <HexagonInstrInfo.h>

Inheritance diagram for llvm::HexagonInstrInfo:
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Collaboration diagram for llvm::HexagonInstrInfo:
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Public Types

typedef unsigned Opcode_t
 

Public Member Functions

 HexagonInstrInfo (HexagonSubtarget &ST)
 
const HexagonRegisterInfogetRegisterInfo () const
 getRegisterInfo - TargetInstrInfo is a superset of MRegister info. More...
 
unsigned isLoadFromStackSlot (const MachineInstr *MI, int &FrameIndex) const override
 isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot. More...
 
unsigned isStoreToStackSlot (const MachineInstr *MI, int &FrameIndex) const override
 isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot. More...
 
bool AnalyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
 
unsigned RemoveBranch (MachineBasicBlock &MBB) const override
 
unsigned InsertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, DebugLoc DL) const override
 
bool analyzeCompare (const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override
 For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue. More...
 
void copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
 
void storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
 
void storeRegToAddr (MachineFunction &MF, unsigned SrcReg, bool isKill, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, SmallVectorImpl< MachineInstr * > &NewMIs) const
 
void loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
 
void loadRegFromAddr (MachineFunction &MF, unsigned DestReg, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, SmallVectorImpl< MachineInstr * > &NewMIs) const
 
bool expandPostRAPseudo (MachineBasicBlock::iterator MI) const override
 expandPostRAPseudo - This function is called for all pseudo instructions that remain after register allocation. More...
 
MachineInstrfoldMemoryOperandImpl (MachineFunction &MF, MachineInstr *MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex) const override
 
MachineInstrfoldMemoryOperandImpl (MachineFunction &MF, MachineInstr *MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr *LoadMI) const override
 
unsigned createVR (MachineFunction *MF, MVT VT) const
 
bool isBranch (const MachineInstr *MI) const
 
bool isPredicable (MachineInstr *MI) const override
 
bool PredicateInstruction (MachineInstr *MI, ArrayRef< MachineOperand > Cond) const override
 
bool isProfitableToIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, const BranchProbability &Probability) const override
 
bool isProfitableToIfCvt (MachineBasicBlock &TMBB, unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB, unsigned NumFCycles, unsigned ExtraFCycles, const BranchProbability &Probability) const override
 
bool isPredicated (const MachineInstr *MI) const override
 
bool isPredicated (unsigned Opcode) const
 
bool isPredicatedTrue (const MachineInstr *MI) const
 
bool isPredicatedTrue (unsigned Opcode) const
 
bool isPredicatedNew (const MachineInstr *MI) const
 
bool isPredicatedNew (unsigned Opcode) const
 
bool DefinesPredicate (MachineInstr *MI, std::vector< MachineOperand > &Pred) const override
 
bool SubsumesPredicate (ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
 
bool ReverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
 
bool isProfitableToDupForIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, const BranchProbability &Probability) const override
 
DFAPacketizerCreateTargetScheduleState (const TargetSubtargetInfo &STI) const override
 
bool isSchedulingBoundary (const MachineInstr *MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
 
bool isValidOffset (unsigned Opcode, int Offset, bool Extend=true) const
 
bool isValidAutoIncImm (const EVT VT, const int Offset) const
 
bool isMemOp (const MachineInstr *MI) const
 
bool isSpillPredRegOp (const MachineInstr *MI) const
 
bool isU6_3Immediate (const int value) const
 
bool isU6_2Immediate (const int value) const
 
bool isU6_1Immediate (const int value) const
 
bool isU6_0Immediate (const int value) const
 
bool isS4_3Immediate (const int value) const
 
bool isS4_2Immediate (const int value) const
 
bool isS4_1Immediate (const int value) const
 
bool isS4_0Immediate (const int value) const
 
bool isS12_Immediate (const int value) const
 
bool isU6_Immediate (const int value) const
 
bool isS8_Immediate (const int value) const
 
bool isS6_Immediate (const int value) const
 
bool isSaveCalleeSavedRegsCall (const MachineInstr *MI) const
 
bool isConditionalTransfer (const MachineInstr *MI) const
 
bool isConditionalALU32 (const MachineInstr *MI) const
 
bool isConditionalLoad (const MachineInstr *MI) const
 
bool isConditionalStore (const MachineInstr *MI) const
 
bool isNewValueInst (const MachineInstr *MI) const
 
bool isNewValue (const MachineInstr *MI) const
 
bool isNewValue (Opcode_t Opcode) const
 
bool isDotNewInst (const MachineInstr *MI) const
 
int GetDotOldOp (const int opc) const
 
int GetDotNewOp (const MachineInstr *MI) const
 
int GetDotNewPredOp (MachineInstr *MI, const MachineBranchProbabilityInfo *MBPI) const
 
bool mayBeNewStore (const MachineInstr *MI) const
 
bool isDeallocRet (const MachineInstr *MI) const
 
unsigned getInvertedPredicatedOpcode (const int Opc) const
 
bool isExtendable (const MachineInstr *MI) const
 
bool isExtended (const MachineInstr *MI) const
 
bool isPostIncrement (const MachineInstr *MI) const
 
bool isNewValueStore (const MachineInstr *MI) const
 
bool isNewValueStore (unsigned Opcode) const
 
bool isNewValueJump (const MachineInstr *MI) const
 
bool isNewValueJump (Opcode_t Opcode) const
 
bool isNewValueJumpCandidate (const MachineInstr *MI) const
 
void immediateExtend (MachineInstr *MI) const
 immediateExtend - Changes the instruction in place to one using an immediate extender. More...
 
bool isConstExtended (const MachineInstr *MI) const
 
unsigned getSize (const MachineInstr *MI) const
 
int getDotNewPredJumpOp (MachineInstr *MI, const MachineBranchProbabilityInfo *MBPI) const
 
unsigned getAddrMode (const MachineInstr *MI) const
 
bool isOperandExtended (const MachineInstr *MI, unsigned short OperandNum) const
 
unsigned short getCExtOpNum (const MachineInstr *MI) const
 
int getMinValue (const MachineInstr *MI) const
 
int getMaxValue (const MachineInstr *MI) const
 
bool NonExtEquivalentExists (const MachineInstr *MI) const
 
short getNonExtOpcode (const MachineInstr *MI) const
 
bool PredOpcodeHasJMP_c (Opcode_t Opcode) const
 
bool predOpcodeHasNot (ArrayRef< MachineOperand > Cond) const
 
bool isEndLoopN (Opcode_t Opcode) const
 
bool getPredReg (ArrayRef< MachineOperand > Cond, unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const
 
int getCondOpcode (int Opc, bool sense) const
 

Detailed Description

Definition at line 31 of file HexagonInstrInfo.h.

Member Typedef Documentation

Definition at line 37 of file HexagonInstrInfo.h.

Constructor & Destructor Documentation

HexagonInstrInfo::HexagonInstrInfo ( HexagonSubtarget ST)
explicit

Definition at line 64 of file HexagonInstrInfo.cpp.

Member Function Documentation

bool HexagonInstrInfo::AnalyzeBranch ( MachineBasicBlock MBB,
MachineBasicBlock *&  TBB,
MachineBasicBlock *&  FBB,
SmallVectorImpl< MachineOperand > &  Cond,
bool  AllowModify 
) const
override
bool HexagonInstrInfo::analyzeCompare ( const MachineInstr MI,
unsigned SrcReg,
unsigned SrcReg2,
int Mask,
int Value 
) const
override

For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue.

Return true if the comparison instruction can be analyzed.

Definition at line 465 of file HexagonInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::getReg().

void HexagonInstrInfo::copyPhysReg ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
DebugLoc  DL,
unsigned  DestReg,
unsigned  SrcReg,
bool  KillSrc 
) const
override
DFAPacketizer * HexagonInstrInfo::CreateTargetScheduleState ( const TargetSubtargetInfo STI) const
override
unsigned HexagonInstrInfo::createVR ( MachineFunction MF,
MVT  VT 
) const
bool HexagonInstrInfo::DefinesPredicate ( MachineInstr MI,
std::vector< MachineOperand > &  Pred 
) const
override
bool HexagonInstrInfo::expandPostRAPseudo ( MachineBasicBlock::iterator  MI) const
override

expandPostRAPseudo - This function is called for all pseudo instructions that remain after register allocation.

Many pseudo instructions are created to help register allocation. This is the place to convert them into real instructions. The target can edit MI in place, or it can insert new instructions and erase MI. The function should return true if anything was changed.

Definition at line 692 of file HexagonInstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineRegisterInfo::clearKillFlags(), llvm::DL, llvm::MachineBasicBlock::erase(), llvm::HexagonRegisterInfo::getFrameRegister(), llvm::MDNode::getOperand(), llvm::MachineBasicBlock::getParent(), getRegisterInfo(), and llvm::RegState::Undef.

MachineInstr * HexagonInstrInfo::foldMemoryOperandImpl ( MachineFunction MF,
MachineInstr MI,
ArrayRef< unsigned Ops,
MachineBasicBlock::iterator  InsertPt,
int  FrameIndex 
) const
override

Definition at line 782 of file HexagonInstrInfo.cpp.

MachineInstr* llvm::HexagonInstrInfo::foldMemoryOperandImpl ( MachineFunction MF,
MachineInstr MI,
ArrayRef< unsigned Ops,
MachineBasicBlock::iterator  InsertPt,
MachineInstr LoadMI 
) const
inlineoverride

Definition at line 119 of file HexagonInstrInfo.h.

unsigned HexagonInstrInfo::getAddrMode ( const MachineInstr MI) const
unsigned short HexagonInstrInfo::getCExtOpNum ( const MachineInstr MI) const
int HexagonInstrInfo::getCondOpcode ( int  Opc,
bool  sense 
) const

Definition at line 987 of file HexagonInstrInfo.cpp.

References llvm_unreachable.

Referenced by PredicateInstruction().

int HexagonInstrInfo::GetDotNewOp ( const MachineInstr MI) const

Definition at line 1665 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), and llvm_unreachable.

int HexagonInstrInfo::getDotNewPredJumpOp ( MachineInstr MI,
const MachineBranchProbabilityInfo MBPI 
) const
int HexagonInstrInfo::GetDotNewPredOp ( MachineInstr MI,
const MachineBranchProbabilityInfo MBPI 
) const
int HexagonInstrInfo::GetDotOldOp ( const int  opc) const

Definition at line 1649 of file HexagonInstrInfo.cpp.

References isNewValueStore(), isPredicated(), and isPredicatedNew().

unsigned HexagonInstrInfo::getInvertedPredicatedOpcode ( const int  Opc) const

Definition at line 952 of file HexagonInstrInfo.cpp.

References isPredicatedTrue(), and llvm_unreachable.

Referenced by ReverseBranchCondition().

int HexagonInstrInfo::getMaxValue ( const MachineInstr MI) const
int HexagonInstrInfo::getMinValue ( const MachineInstr MI) const
short HexagonInstrInfo::getNonExtOpcode ( const MachineInstr MI) const
bool HexagonInstrInfo::getPredReg ( ArrayRef< MachineOperand Cond,
unsigned PredReg,
unsigned PredRegPos,
unsigned PredRegFlags 
) const
const HexagonRegisterInfo& llvm::HexagonInstrInfo::getRegisterInfo ( ) const
inline

getRegisterInfo - TargetInstrInfo is a superset of MRegister info.

As such, whenever a client has an instance of instruction info, it should always be able to get register info as well (through this method).

Definition at line 45 of file HexagonInstrInfo.h.

Referenced by expandPostRAPseudo(), llvm::HexagonSubtarget::getRegisterInfo(), INITIALIZE_PASS(), and llvm::VirtRegMap::runOnMachineFunction().

unsigned HexagonInstrInfo::getSize ( const MachineInstr MI) const
void HexagonInstrInfo::immediateExtend ( MachineInstr MI) const
unsigned HexagonInstrInfo::InsertBranch ( MachineBasicBlock MBB,
MachineBasicBlock TBB,
MachineBasicBlock FBB,
ArrayRef< MachineOperand Cond,
DebugLoc  DL 
) const
override
bool HexagonInstrInfo::isBranch ( const MachineInstr MI) const
bool HexagonInstrInfo::isConditionalALU32 ( const MachineInstr MI) const

Definition at line 1406 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

bool HexagonInstrInfo::isConditionalLoad ( const MachineInstr MI) const

Definition at line 1463 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

bool HexagonInstrInfo::isConditionalStore ( const MachineInstr MI) const

Definition at line 1542 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

bool HexagonInstrInfo::isConditionalTransfer ( const MachineInstr MI) const

Definition at line 1391 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

bool HexagonInstrInfo::isConstExtended ( const MachineInstr MI) const
bool HexagonInstrInfo::isDeallocRet ( const MachineInstr MI) const

Definition at line 1198 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

bool HexagonInstrInfo::isDotNewInst ( const MachineInstr MI) const

Definition at line 1635 of file HexagonInstrInfo.cpp.

References isNewValueInst(), isPredicated(), and isPredicatedNew().

bool HexagonInstrInfo::isEndLoopN ( Opcode_t  Opcode) const
bool HexagonInstrInfo::isExtendable ( const MachineInstr MI) const
bool HexagonInstrInfo::isExtended ( const MachineInstr MI) const
unsigned HexagonInstrInfo::isLoadFromStackSlot ( const MachineInstr MI,
int FrameIndex 
) const
override

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot.

If not, return 0. This predicate must return 0 if the instruction has any side effects other than loading from the stack slot.

Definition at line 73 of file HexagonInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isFI(), and llvm::MachineOperand::isImm().

bool HexagonInstrInfo::isMemOp ( const MachineInstr MI) const

Definition at line 1331 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

bool HexagonInstrInfo::isNewValue ( const MachineInstr MI) const
bool HexagonInstrInfo::isNewValue ( Opcode_t  Opcode) const
bool HexagonInstrInfo::isNewValueInst ( const MachineInstr MI) const

Definition at line 847 of file HexagonInstrInfo.cpp.

References isNewValueJump(), and isNewValueStore().

Referenced by isDotNewInst().

bool HexagonInstrInfo::isNewValueJump ( const MachineInstr MI) const

Definition at line 1619 of file HexagonInstrInfo.cpp.

References isBranch(), and isNewValue().

Referenced by AnalyzeBranch(), getPredReg(), InsertBranch(), and isNewValueInst().

bool HexagonInstrInfo::isNewValueJump ( Opcode_t  Opcode) const

Definition at line 1625 of file HexagonInstrInfo.cpp.

References isBranch(), isNewValue(), and isPredicated().

bool HexagonInstrInfo::isNewValueJumpCandidate ( const MachineInstr MI) const

Definition at line 1377 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

bool HexagonInstrInfo::isNewValueStore ( const MachineInstr MI) const
bool HexagonInstrInfo::isNewValueStore ( unsigned  Opcode) const
bool HexagonInstrInfo::isOperandExtended ( const MachineInstr MI,
unsigned short  OperandNum 
) const
bool HexagonInstrInfo::isPostIncrement ( const MachineInstr MI) const

Definition at line 1629 of file HexagonInstrInfo.cpp.

References getAddrMode(), and llvm::HexagonII::PostInc.

Referenced by GetPostIncrementOperand().

bool HexagonInstrInfo::isPredicable ( MachineInstr MI) const
override
bool HexagonInstrInfo::isPredicated ( const MachineInstr MI) const
override
bool HexagonInstrInfo::isPredicated ( unsigned  Opcode) const
bool HexagonInstrInfo::isPredicatedNew ( const MachineInstr MI) const
bool HexagonInstrInfo::isPredicatedNew ( unsigned  Opcode) const
bool HexagonInstrInfo::isPredicatedTrue ( const MachineInstr MI) const
bool HexagonInstrInfo::isPredicatedTrue ( unsigned  Opcode) const
bool HexagonInstrInfo::isProfitableToDupForIfCvt ( MachineBasicBlock MBB,
unsigned  NumCycles,
const BranchProbability Probability 
) const
override

Definition at line 1193 of file HexagonInstrInfo.cpp.

bool HexagonInstrInfo::isProfitableToIfCvt ( MachineBasicBlock MBB,
unsigned  NumCycles,
unsigned  ExtraPredCycles,
const BranchProbability Probability 
) const
override

Definition at line 1069 of file HexagonInstrInfo.cpp.

bool HexagonInstrInfo::isProfitableToIfCvt ( MachineBasicBlock TMBB,
unsigned  NumTCycles,
unsigned  ExtraTCycles,
MachineBasicBlock FMBB,
unsigned  NumFCycles,
unsigned  ExtraFCycles,
const BranchProbability Probability 
) const
override

Definition at line 1079 of file HexagonInstrInfo.cpp.

bool llvm::HexagonInstrInfo::isS12_Immediate ( const int  value) const
bool llvm::HexagonInstrInfo::isS4_0Immediate ( const int  value) const
bool llvm::HexagonInstrInfo::isS4_1Immediate ( const int  value) const
bool llvm::HexagonInstrInfo::isS4_2Immediate ( const int  value) const
bool llvm::HexagonInstrInfo::isS4_3Immediate ( const int  value) const
bool llvm::HexagonInstrInfo::isS6_Immediate ( const int  value) const
bool llvm::HexagonInstrInfo::isS8_Immediate ( const int  value) const
bool HexagonInstrInfo::isSaveCalleeSavedRegsCall ( const MachineInstr MI) const

Definition at line 867 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

bool HexagonInstrInfo::isSchedulingBoundary ( const MachineInstr MI,
const MachineBasicBlock MBB,
const MachineFunction MF 
) const
override
bool HexagonInstrInfo::isSpillPredRegOp ( const MachineInstr MI) const

Definition at line 1368 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

unsigned HexagonInstrInfo::isStoreToStackSlot ( const MachineInstr MI,
int FrameIndex 
) const
override

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot.

If not, return 0. This predicate must return 0 if the instruction has any side effects other than storing to the stack slot.

Definition at line 100 of file HexagonInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isFI(), and llvm::MachineOperand::isImm().

bool llvm::HexagonInstrInfo::isU6_0Immediate ( const int  value) const
bool llvm::HexagonInstrInfo::isU6_1Immediate ( const int  value) const
bool llvm::HexagonInstrInfo::isU6_2Immediate ( const int  value) const
bool llvm::HexagonInstrInfo::isU6_3Immediate ( const int  value) const
bool llvm::HexagonInstrInfo::isU6_Immediate ( const int  value) const
bool HexagonInstrInfo::isValidAutoIncImm ( const EVT  VT,
const int  Offset 
) const
bool HexagonInstrInfo::isValidOffset ( unsigned  Opcode,
int  Offset,
bool  Extend = true 
) const
void HexagonInstrInfo::loadRegFromAddr ( MachineFunction MF,
unsigned  DestReg,
SmallVectorImpl< MachineOperand > &  Addr,
const TargetRegisterClass RC,
SmallVectorImpl< MachineInstr * > &  NewMIs 
) const

Definition at line 685 of file HexagonInstrInfo.cpp.

References llvm_unreachable.

void HexagonInstrInfo::loadRegFromStackSlot ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MBBI,
unsigned  DestReg,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI 
) const
override
bool HexagonInstrInfo::mayBeNewStore ( const MachineInstr MI) const
bool HexagonInstrInfo::NonExtEquivalentExists ( const MachineInstr MI) const
bool HexagonInstrInfo::PredicateInstruction ( MachineInstr MI,
ArrayRef< MachineOperand Cond 
) const
override
bool HexagonInstrInfo::PredOpcodeHasJMP_c ( Opcode_t  Opcode) const

Definition at line 1976 of file HexagonInstrInfo.cpp.

Referenced by AnalyzeBranch().

bool HexagonInstrInfo::predOpcodeHasNot ( ArrayRef< MachineOperand Cond) const
unsigned HexagonInstrInfo::RemoveBranch ( MachineBasicBlock MBB) const
override
bool HexagonInstrInfo::ReverseBranchCondition ( SmallVectorImpl< MachineOperand > &  Cond) const
override
void HexagonInstrInfo::storeRegToAddr ( MachineFunction MF,
unsigned  SrcReg,
bool  isKill,
SmallVectorImpl< MachineOperand > &  Addr,
const TargetRegisterClass RC,
SmallVectorImpl< MachineInstr * > &  NewMIs 
) const

Definition at line 643 of file HexagonInstrInfo.cpp.

References llvm_unreachable.

void HexagonInstrInfo::storeRegToStackSlot ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MBBI,
unsigned  SrcReg,
bool  isKill,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI 
) const
override
bool HexagonInstrInfo::SubsumesPredicate ( ArrayRef< MachineOperand Pred1,
ArrayRef< MachineOperand Pred2 
) const
override

Definition at line 1165 of file HexagonInstrInfo.cpp.


The documentation for this class was generated from the following files: