40 const Twine &Description;
45 static int getKindID() {
52 DiagnosticInfoUnsupported(
const Function &Fn,
const Twine &Desc,
58 const Function &getFunction()
const {
return Fn; }
59 const Twine &getDescription()
const {
return Description; }
62 DP <<
"unsupported " << getDescription() <<
" in " << Fn.getName();
66 return DI->
getKind() == getKindID();
70 int DiagnosticInfoUnsupported::KindID = 0;
84 #include "AMDGPUGenCallingConv.inc"
92 assert(StoreSize % 32 == 0 &&
"Store size not a multiple of 32");
278 for (
MVT VT : ScalarIntVTs) {
332 for (
MVT VT : VectorIntTypes) {
377 for (
MVT VT : FloatVectorTypes) {
489 return (OldSize < 32);
500 return ((LScalarSize <= CastScalarSize) ||
501 (CastScalarSize >= 32) ||
552 return SrcSize == 32 && DestSize == 64;
611 FuncName =
G->getSymbol();
613 FuncName =
G->getGlobal()->getName();
615 DiagnosticInfoUnsupported NoCalls(Fn,
"call to function " + FuncName);
626 "instruction is not implemented yet!");
635 case ISD::FREM:
return LowerFREM(Op, DAG);
704 if (
const ConstantInt *CI = dyn_cast<ConstantInt>(Init)) {
712 if (
const ConstantFP *CFP = dyn_cast<ConstantFP>(Init)) {
726 for (
unsigned I = 0,
N =
ST->getNumElements();
I !=
N; ++
I) {
731 Chains.
push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
740 unsigned NumElements;
741 if (
ArrayType *AT = dyn_cast<ArrayType>(SeqTy))
742 NumElements = AT->getNumElements();
743 else if (
VectorType *VT = dyn_cast<VectorType>(SeqTy))
744 NumElements = VT->getNumElements();
750 for (
unsigned i = 0; i < NumElements; ++i) {
755 Chains.
push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
761 if (isa<UndefValue>(Init)) {
796 "Do not know what to do with an non-zero offset");
818 Type *EltType = GV->getType()->getElementType();
845 E = WorkList.
end();
I != E; ++
I) {
848 for (
unsigned i = 1; i < (*I)->getNumOperands(); ++i) {
858 DiagnosticInfoUnsupported BadInit(Fn,
859 "initializer for address space");
878 unsigned Start = cast<ConstantSDNode>(Op.
getOperand(1))->getZExtValue();
902 unsigned IntrinsicID = cast<ConstantSDNode>(Op.
getOperand(0))->getZExtValue();
906 switch (IntrinsicID) {
908 case AMDGPUIntrinsic::AMDGPU_abs:
909 case AMDGPUIntrinsic::AMDIL_abs:
911 case AMDGPUIntrinsic::AMDGPU_lrp:
914 case AMDGPUIntrinsic::AMDGPU_clamp:
915 case AMDGPUIntrinsic::AMDIL_clamp:
919 case Intrinsic::AMDGPU_div_scale: {
938 Denominator, Numerator);
941 case Intrinsic::AMDGPU_div_fmas:
946 case Intrinsic::AMDGPU_div_fixup:
950 case Intrinsic::AMDGPU_trig_preop:
954 case Intrinsic::AMDGPU_rcp:
957 case Intrinsic::AMDGPU_rsq:
960 case AMDGPUIntrinsic::AMDGPU_legacy_rsq:
963 case Intrinsic::AMDGPU_rsq_clamped:
978 case Intrinsic::AMDGPU_ldexp:
982 case AMDGPUIntrinsic::AMDGPU_imax:
985 case AMDGPUIntrinsic::AMDGPU_umax:
988 case AMDGPUIntrinsic::AMDGPU_imin:
991 case AMDGPUIntrinsic::AMDGPU_umin:
995 case AMDGPUIntrinsic::AMDGPU_umul24:
999 case AMDGPUIntrinsic::AMDGPU_imul24:
1003 case AMDGPUIntrinsic::AMDGPU_umad24:
1007 case AMDGPUIntrinsic::AMDGPU_imad24:
1011 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte0:
1014 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte1:
1017 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte2:
1020 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte3:
1023 case AMDGPUIntrinsic::AMDGPU_bfe_i32:
1029 case AMDGPUIntrinsic::AMDGPU_bfe_u32:
1035 case AMDGPUIntrinsic::AMDGPU_bfi:
1041 case AMDGPUIntrinsic::AMDGPU_bfm:
1046 case AMDGPUIntrinsic::AMDGPU_brev:
1049 case Intrinsic::AMDGPU_class:
1053 case AMDGPUIntrinsic::AMDIL_exp:
1056 case AMDGPUIntrinsic::AMDIL_round_nearest:
1058 case AMDGPUIntrinsic::AMDGPU_trunc:
1102 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
1179 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
1187 return DAG.
getNode(Opc, DL, VT, LHS, RHS);
1192 return DAG.
getNode(Opc, DL, VT, LHS, RHS);
1197 return DAG.
getNode(Opc, DL, VT, LHS, RHS);
1202 return DAG.
getNode(Opc, DL, VT, LHS, RHS);
1227 for (
unsigned i = 0; i < NumElts; ++i) {
1234 SrcValue.getWithOffset(i * MemEltSize),
1260 EVT PtrVT = BasePtr.getValueType();
1266 EVT LoMemVT, HiMemVT;
1271 std::tie(Lo, Hi) = DAG.
SplitVector(Op, SL, LoVT, HiVT);
1286 SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1299 SDValue AMDGPUTargetLowering::MergeVectorStore(
const SDValue &Op,
1308 if (!MemVT.isVector() || MemBits > 32) {
1319 unsigned MemNumElements = MemVT.getVectorNumElements();
1320 unsigned PackedSize = MemVT.getStoreSizeInBits();
1326 for (
unsigned i = 0; i < MemNumElements; ++i) {
1342 if (PackedSize < 32) {
1368 unsigned EltSize = MemEltVT.getStoreSize();
1371 for (
unsigned i = 0, e = NumElts; i != e; ++i) {
1380 SrcValue.getWithOffset(i * EltSize),
1393 EVT VT = Val.getValueType();
1406 EVT LoMemVT, HiMemVT;
1411 std::tie(Lo, Hi) = DAG.
SplitVector(Val, SL, LoVT, HiVT);
1448 assert(VT ==
MVT::i1 &&
"Only i1 non-extloads expected");
1522 SDValue Result = AMDGPUTargetLowering::MergeVectorStore(Op, DAG);
1563 MaskedValue, ShiftAmt);
1728 for (
unsigned i = 0; i < halfBitWidth; ++i) {
1729 const unsigned bitPos = halfBitWidth - i - 1;
1975 const unsigned FractBits = 52;
1976 const unsigned ExpBits = 11;
2005 const unsigned FractBits = 52;
2158 return LowerFROUND32(Op, DAG);
2161 return LowerFROUND64(Op, DAG);
2221 return LowerINT_TO_FP64(Op, DAG,
false);
2243 return LowerINT_TO_FP64(Op, DAG,
true);
2249 bool Signed)
const {
2282 return LowerFP64_TO_INT(Op, DAG,
true);
2292 return LowerFP64_TO_INT(Op, DAG,
false);
2315 for (
unsigned I = 0;
I < NElts; ++
I)
2326 APInt KnownZero, KnownOne;
2350 APInt KnownZero, KnownOne;
2356 template <
typename IntTy>
2358 uint32_t Offset, uint32_t Width,
SDLoc DL) {
2359 if (Width + Offset < 32) {
2360 uint32_t Shl =
static_cast<uint32_t
>(Src0) << (32 - Offset - Width);
2361 IntTy Result =
static_cast<IntTy
>(Shl) >> (32 - Width);
2382 DAGCombinerInfo &DCI)
const {
2383 if (!DCI.isBeforeLegalize())
2388 EVT VT = Value.getValueType();
2394 LoadSDNode *LoadVal = cast<LoadSDNode>(Value);
2413 DCI.CombineTo(LoadVal, CastLoad, NewLoad.
getValue(1),
false);
2420 DAGCombinerInfo &DCI)
const {
2447 DAGCombinerInfo &DCI)
const {
2489 return performShlCombine(N, DCI);
2492 return performMulCombine(N, DCI);
2527 "Vector handling of BFE not implemented");
2545 if (OffsetVal == 0) {
2547 unsigned SignBits = Signed ? (32 - WidthVal + 1) : (32 - WidthVal);
2550 if (OpSignBits >= SignBits)
2570 return constantFoldBFE<int32_t>(DAG,
2571 CVal->getSExtValue(),
2577 return constantFoldBFE<uint32_t>(DAG,
2578 CVal->getZExtValue(),
2584 if ((OffsetVal + WidthVal) >= 32) {
2587 BitsFrom, ShiftVal);
2593 OffsetVal + WidthVal);
2595 APInt KnownZero, KnownOne;
2599 if (TLO.ShrinkDemandedConstant(BitsFrom, Demanded) ||
2600 TLI.SimplifyDemandedBits(BitsFrom, Demanded,
2601 KnownZero, KnownOne, TLO)) {
2610 return performStoreCombine(N, DCI);
2625 for (
unsigned i = 0, e = Ins.
size(); i < e; ++i) {
2626 if (Ins[i].ArgVT == Ins[i].VT) {
2632 if (Ins[i].ArgVT.isVector() && !Ins[i].VT.isVector()) {
2634 VT = Ins[i].ArgVT.getVectorElementType();
2635 }
else if (Ins[i].VT.
isVector() && Ins[i].ArgVT.isVector() &&
2636 Ins[i].ArgVT.getVectorElementType() !=
2637 Ins[i].VT.getVectorElementType()) {
2646 Ins[i].OrigArgIndex, Ins[i].PartOffset);
2653 return CFP->isExactlyValue(1.0);
2656 return C->isAllOnesValue();
2663 return CFP->getValueAPF().isZero();
2666 return C->isNullValue();
2673 unsigned Reg,
EVT VT)
const {
2676 unsigned VirtualRegister;
2693 return ArgOffset + 4;
2698 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
2777 unsigned &RefinementSteps,
2778 bool &UseOneConstNR)
const {
2783 RefinementSteps = 0;
2795 unsigned &RefinementSteps)
const {
2805 RefinementSteps = 0;
2821 APInt Op0Zero, Op0One;
2822 APInt Op1Zero, Op1One;
2826 KnownZero = Op0Zero & Op1Zero;
2827 KnownOne = Op0One & Op1One;
2835 unsigned Depth)
const {
2848 switch (cast<ConstantSDNode>(Op.
getOperand(0))->getZExtValue()) {
2849 case AMDGPUIntrinsic::AMDGPU_imax:
2850 case AMDGPUIntrinsic::AMDGPU_umax:
2851 case AMDGPUIntrinsic::AMDGPU_imin:
2852 case AMDGPUIntrinsic::AMDGPU_umin:
2854 KnownZero, KnownOne, DAG, Depth);
2874 unsigned BitWidth = 32;
2888 unsigned Depth)
const {
2902 return std::max(SignBits, Op0SignBits);
2907 return Width ? 32 - (Width->
getZExtValue() & 0x1f) : 1;
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
SDValue getTruncStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT TVT, bool isNonTemporal, bool isVolatile, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes())
AMDGPUTargetLowering(TargetMachine &TM, const AMDGPUSubtarget &STI)
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
void push_back(const T &Elt)
A parsed version of the target data layout string in and methods for querying it. ...
SDValue getValue(unsigned R) const
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, SDLoc DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array...
CombineLevel getDAGCombineLevel()
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant, which is required to be operand #1) half of the integer or float value specified as operand #0.
LLVMContext * getContext() const
AMDGPU specific subclass of TargetSubtarget.
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG, SmallVectorImpl< SDValue > &Results) const
void dump() const
Dump this node, for debugging.
bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtType, EVT ExtVT) const override
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an vector value) starting with the ...
BR_CC - Conditional branch.
static MVT getVectorVT(MVT VT, unsigned NumElements)
static const fltSemantics IEEEdouble
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
void AnalyzeFormalArguments(CCState &State, const SmallVectorImpl< ISD::InputArg > &Ins) const
SDVTList getVTList() const
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool isCalledByLegalizer() const
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
DiagnosticSeverity
Defines the different supported severity of a diagnostic.
virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, SelectionDAG &DAG) const
SDValue getMergeValues(ArrayRef< SDValue > Ops, SDLoc dl)
Create a MERGE_VALUES node from the given operands.
Carry-setting nodes for multiple precision addition and subtraction.
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
unsigned getPrefTypeAlignment(Type *Ty) const
Returns the preferred stack/global alignment for the specified type.
void computeKnownBits(SDValue Op, APInt &KnownZero, APInt &KnownOne, unsigned Depth=0) const
Determine which bits of Op are known to be either zero or one and return them in the KnownZero/KnownO...
std::pair< EVT, EVT > GetSplitDestVTs(const EVT &VT) const
Compute the VTs needed for the low/hi parts of a type which is split (or expanded) into two not neces...
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Get a value with low bits set.
const GlobalValue * getGlobal() const
void setHasFloatingPointExceptions(bool FPExceptions=true)
Tells the code generator that this target supports floating point exceptions and cares about preservi...
static PointerType * get(Type *ElementType, unsigned AddressSpace)
PointerType::get - This constructs a pointer to an object of the specified type in a numbered address...
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
SDValue getSelectCC(SDLoc DL, SDValue LHS, SDValue RHS, SDValue True, SDValue False, ISD::CondCode Cond)
Helper function to make it easier to build SelectCC's if you just have an ISD::CondCode instead of an...
Type * getTypeForEVT(LLVMContext &Context) const
getTypeForEVT - This method returns an LLVM type corresponding to the specified EVT.
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
SDValue getZeroExtendInReg(SDValue Op, SDLoc DL, EVT SrcTy)
Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value...
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
const SDValue & getOperand(unsigned Num) const
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
static void computeKnownBitsForMinMax(const SDValue Op0, const SDValue Op1, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth)
Address space for local memory.
[US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned integers.
const MachinePointerInfo & getPointerInfo() const
SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
const Constant * getInitializer() const
getInitializer - Return the initializer for this global variable.
const SDValue & getBasePtr() const
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
bool bitsLT(EVT VT) const
bitsLT - Return true if this has less bits than VT.
bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, APInt &KnownZero, APInt &KnownOne, TargetLoweringOpt &TLO, unsigned Depth=0) const
Look at Op.
bool isAllOnesValue() const
SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
bool storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem, unsigned AS) const override
Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the give...
bool isCheapToSpeculateCttz() const override
Return true if it is cheap to speculate a call to intrinsic cttz.
A convenience struct that encapsulates a DAG, and two SDValues for returning information from TargetL...
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
APInt Not(const APInt &APIVal)
Bitwise complement function.
bool isVector() const
isVector - Return true if this is a vector value type.
SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI, unsigned &RefinementSteps, bool &UseOneConstNR) const override
Hooks for building estimates in place of slower divisions and square roots.
Used to lazily calculate structure layout information for a target machine, based on the DataLayout s...
SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const
MachineMemOperand - A description of a memory reference used in the backend.
Pointer to the start of the shader's constant data.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
int64_t getOffset() const
const StructLayout * getStructLayout(StructType *Ty) const
Returns a StructLayout object, indicating the alignment of the struct, its size, and the offsets of i...
Shift and rotation operations.
bool isNormalStore(const SDNode *N)
Returns true if the specified node is a non-truncating and unindexed store.
StructType - Class to represent struct types.
SDValue ScalarizeVectorStore(SDValue Op, SelectionDAG &DAG) const
Split a vector store into a scalar store of each component.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
MachineFunction & getMachineFunction() const
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
virtual SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const
Helper function that adds Reg to the LiveIn list of the DAG's MachineFunction.
void addLoc(const CCValAssign &V)
unsigned getAddressSpace() const
Reg
All possible values of the reg field in the ModR/M byte.
SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const
IABS(a) = SMAX(sub(0, a), a)
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const SelectionDAG &DAG, unsigned Depth=0) const override
This method can be implemented by targets that want to expose additional information about sign bits ...
MVT getScalarType() const
getScalarType - If this is a vector type, return the element type, otherwise return this...
static bool isI24(SDValue Op, SelectionDAG &DAG)
EVT getScalarType() const
getScalarType - If this is a vector type, return the element type, otherwise return this...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
bool bitsGE(EVT VT) const
bitsGE - Return true if this has no less bits than VT.
Interface for custom diagnostic printing.
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
unsigned getStoreSize() const
getStoreSize - Return the number of bytes overwritten by a store of the specified value type...
void setJumpIsExpensive(bool isExpensive=true)
Tells the code generator not to expand logic operations on comparison predicates into separate sequen...
Interface to describe a layout of a stack frame on a AMDIL target machine.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
EVT getVectorElementType() const
getVectorElementType - Given a vector type, return the type of each element.
TargetRegisterInfo interface that is implemented by all hw codegen targets.
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
load Combine Adjacent Loads
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
void setSelectIsExpensive(bool isExpensive=true)
Tells the code generator not to expand operations into sequences that use the select operations if po...
const AMDGPUSubtarget * Subtarget
bool isLiveIn(unsigned Reg) const
SDValue CombineIMinMax(SDLoc DL, EVT VT, SDValue LHS, SDValue RHS, SDValue True, SDValue False, SDValue CC, SelectionDAG &DAG) const
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
ArrayType - Class to represent array types.
Simple integer binary arithmetic operators.
static cl::opt< std::string > FuncName("cppfname", cl::desc("Specify the name of the generated function"), cl::value_desc("function name"))
void setFsqrtIsCheap(bool isCheap=true)
Tells the code generator that fsqrt is cheap, and should not be replaced with an alternative sequence...
const SDValue & getBasePtr() const
EVT getHalfSizedIntegerVT(LLVMContext &Context) const
getHalfSizedIntegerVT - Finds the smallest simple value type that is greater than or equal to half th...
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
static mvt_range integer_vector_valuetypes()
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
EVT getMemoryVT() const
Return the type of the in-memory value.
Generation getGeneration() const
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
static void simplifyI24(SDValue Op, TargetLowering::DAGCombinerInfo &DCI)
const DataLayout & getDataLayout() const
SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI, unsigned &RefinementSteps) const override
Return a reciprocal estimate value for the input operand.
PointerType - Class to represent pointers.
bool isHWTrueValue(SDValue Op) const
This class is used to represent ISD::STORE nodes.
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
This node is for VLIW targets and it is used to represent a vector that is stored in consecutive regi...
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable...
uint64_t getElementOffset(unsigned Idx) const
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Get a value with high bits set.
SDNode * getNode() const
get the SDNode which holds the desired result
A self-contained host- and target-independent arbitrary-precision floating-point software implementat...
unsigned getScalarSizeInBits() const
unsigned getStoreSize() const
getStoreSize - Return the number of bytes overwritten by a store of the specified value type...
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
bool isNormalLoad(const SDNode *N)
Returns true if the specified node is a non-extending and unindexed load.
This is the base abstract class for diagnostic reporting in the backend.
unsigned getStoreSizeInBits() const
getStoreSizeInBits - Return the number of bits overwritten by a store of the specified value type...
unsigned getVectorNumElements() const
MVT - Machine Value Type.
const SDValue & getOperand(unsigned i) const
The instances of the Type class are immutable: once they are created, they are never changed...
This is an important class for using LLVM in a threaded context.
Address space for constant memory.
Simple binary floating point operators.
void setTargetDAGCombine(ISD::NodeType NT)
Targets should invoke this method for each target independent node that they want to provide a custom...
bool isNonTemporal() const
Address space for private memory.
This is an important base class in LLVM.
bool isVector() const
isVector - Return true if this is a vector value type.
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
bool isBeforeLegalizeOps() const
Carry-using nodes for multiple precision addition and subtraction.
unsigned getLiveInVirtReg(unsigned PReg) const
getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in physical ...
ConstantFP - Floating Point Values [float, double].
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
static bool hasDefinedInitializer(const GlobalValue *GV)
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
This class provides iterator support for SDUse operands that use a specific SDNode.
SDValue getSExtOrTrunc(SDValue Op, SDLoc DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either sign-extending or trunca...
bool isBeforeLegalize() const
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang","erlang-compatible garbage collector")
SDValue getTargetConstant(uint64_t Val, SDLoc DL, EVT VT, bool isOpaque=false)
bool isLoadBitCastBeneficial(EVT, EVT) const override
isLoadBitCastBeneficial() - Return true if the following transform is beneficial. ...
unsigned getBitWidth() const
Return the number of bits in the APInt.
unsigned getOpcode() const
bool hasFP32Denormals() const
SDValue ScalarizeVectorLoad(SDValue Op, SelectionDAG &DAG) const
Split a vector load into a scalar load of each component.
use_iterator use_begin() const
Provide iteration support to walk over all uses of an SDNode.
const SDValue & getValue() const
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
Constant * getAggregateElement(unsigned Elt) const
getAggregateElement - For aggregates (struct/array/vector) return the constant that corresponds to th...
unsigned MaxStoresPerMemmove
Specify maximum bytes of store instructions per memmove call.
SDValue getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes())
Bit counting operators with an undefined result for zero inputs.
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth=0) const
Return true if 'Op & Mask' is known to be zero.
SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const
Linear Interpolation LRP(a, b, c) = muladd(a, b, (1 - a) * c)
void setPow2SDivIsCheap(bool isCheap=true)
Tells the code generator that it shouldn't generate sra/srl/add/sra for a signed divide by power of t...
EVT - Extended Value Type.
static UndefValue * get(Type *T)
get() - Static factory methods - Return an 'undef' object of the specified type.
bool isHWFalseValue(SDValue Op) const
static SDValue extractF64Exponent(SDValue Hi, SDLoc SL, SelectionDAG &DAG)
This structure contains all information that is necessary for lowering calls.
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements)
getVectorVT - Returns the EVT that represents a vector NumElements in length, where each element is o...
MachinePointerInfo - This class contains a discriminated union of information about pointers in memor...
bool isFPImmLegal(const APFloat &Imm, EVT VT) const override
Returns true if the target can instruction select the specified FP immediate natively.
void dump() const
Support for debugging, callable in GDB: V->dump()
const SDValue & getOffset() const
SequentialType - This is the superclass of the array, pointer and vector type classes.
SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const
Split a vector store into 2 stores of half the vector.
static bool isU24(SDValue Op, SelectionDAG &DAG)
void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
TokenFactor - This node takes multiple tokens as input and produces a single token result...
SDValue getNOT(SDLoc DL, SDValue Val, EVT VT)
Create a bitwise NOT operation as (XOR Val, -1).
CCState - This class holds information needed while lowering arguments and return values...
This is the shared class of boolean and integer constants.
SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const
Split a vector load into 2 loads of half the vector.
unsigned LDSSize
Number of bytes in the LDS that are being used.
bool isFAbsFree(EVT VT) const override
Return true if an fabs operation is free to the point where it is never worthwhile to replace it with...
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
uint64_t getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
std::pair< SDValue, SDValue > SplitVector(const SDValue &N, const SDLoc &DL, const EVT &LoVT, const EVT &HiVT)
Split the vector with EXTRACT_SUBVECTOR using the provides VTs and return the low/high part...
SDNode * UpdateNodeOperands(SDNode *N, SDValue Op)
Mutate the specified node in-place to have the specified operands.
unsigned getScalarSizeInBits() const LLVM_READONLY
getScalarSizeInBits - If this is a vector type, return the getPrimitiveSizeInBits value for the eleme...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Interface definition of the TargetLowering class that is common to all AMD GPUs.
static bool allocateStack(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Type * getType() const
All values are typed, get the type of this value.
virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const
Return the ValueType of the result of SETCC operations.
const SDValue & getChain() const
Byte Swap and Counting operators.
FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions and truncation for half-preci...
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
void ExtractVectorElements(SDValue Op, SmallVectorImpl< SDValue > &Args, unsigned Start=0, unsigned Count=0)
Append the extracted elements from Start to Count out of the vector Op in Args.
unsigned getStackWidth(const MachineFunction &MF) const
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Represents one node in the SelectionDAG.
const fltSemantics & getFltSemantics() const
static bool usesAllNormalStores(SDNode *LoadVal)
double BitsToDouble(uint64_t Bits)
BitsToDouble - This function takes a 64-bit integer and returns the bit equivalent double...
static mvt_range integer_valuetypes()
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
VectorType - Class to represent vector types.
int getFrameIndexOffset(const MachineFunction &MF, int FI) const override
Class for arbitrary precision integers.
bool hasInitializer() const
Definitions have initializers, declarations don't.
const Value * getValue() const
getValue - Return the base address of the memory access.
Select(COND, TRUEVAL, FALSEVAL).
Interface for the AMDGPU Implementation of the Intrinsic Info class.
static use_iterator use_end()
ZERO_EXTEND - Used for integer types, zeroing the new bits.
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
static EVT getEquivalentLoadRegType(LLVMContext &Context, EVT VT)
static APFloat getLargest(const fltSemantics &Sem, bool Negative=false)
Returns the largest finite number in the given semantics.
int getNextAvailablePluginDiagnosticKind()
Get the next available kind ID for a plugin diagnostic.
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
const AMDGPUFrameLowering * getFrameLowering() const override
std::map< const GlobalValue *, unsigned > LocalMemoryObjects
A map to keep track of local memory objects and their offsets within the local memory space...
APInt And(const APInt &LHS, const APInt &RHS)
Bitwise AND function for APInt.
static APInt getBitsSet(unsigned numBits, unsigned loBit, unsigned hiBit)
Get a value with a block of bits set.
unsigned getAddressSpace() const
Return the address space for the associated pointer.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
BR_JT - Jumptable branch.
unsigned countLeadingOnes() const
Count the number of leading one bits.
Represents a use of a SDNode.
Bitwise operators - logical and, logical or, logical xor.
bool isNarrowingProfitable(EVT VT1, EVT VT2) const override
Return true if it's profitable to narrow operations of type VT1 to VT2.
SelectSupportKind
Enum that describes what type of support for selects the target has.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
unsigned ABIArgOffset
Start of implicit kernel args.
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Information about the stack frame layout on the AMDGPU targets.
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
ArrayRef< SDUse > ops() const
bool isTruncateFree(EVT Src, EVT Dest) const override
#define NODE_NAME_CASE(node)
static CCValAssign getMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
SDValue CombineFMinMaxLegacy(SDLoc DL, EVT VT, SDValue LHS, SDValue RHS, SDValue True, SDValue False, SDValue CC, DAGCombinerInfo &DCI) const
Generate Min/Max node.
static SDValue constantFoldBFE(SelectionDAG &DAG, IntTy Src0, uint32_t Offset, uint32_t Width, SDLoc DL)
unsigned MaxStoresPerMemcpy
Specify maximum bytes of store instructions per memcpy call.
void diagnose(const DiagnosticInfo &DI)
Report a message to the currently installed diagnostic handler.
static EVT getEVT(Type *Ty, bool HandleUnknown=false)
getEVT - Return the value type corresponding to the specified type.
bool isFNegFree(EVT VT) const override
Return true if an fneg operation is free to the point where it is never worthwhile to replace it with...
int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSS, const AllocaInst *Alloca=nullptr)
Create a new statically sized stack object, returning a nonnegative identifier to represent it...
EVT getValueType() const
Return the ValueType of the referenced return value.
SDValue getConstant(uint64_t Val, SDLoc DL, EVT VT, bool isTarget=false, bool isOpaque=false)
void getOriginalFunctionArgs(SelectionDAG &DAG, const Function *F, const SmallVectorImpl< ISD::InputArg > &Ins, SmallVectorImpl< ISD::InputArg > &OrigIns) const
The SelectionDAGBuilder will automatically promote function arguments with illegal types...
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
SDValue getSelect(SDLoc DL, EVT VT, SDValue Cond, SDValue LHS, SDValue RHS)
Helper function to make it easier to build Select's if you just have operands and don't want to check...
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
void setIntDivIsCheap(bool isCheap=true)
Tells the code generator that integer divide is expensive, and if possible, should be replaced by an ...
bool atEnd() const
Return true if this iterator is at the end of uses list.
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
unsigned getPrimitiveSizeInBits() const LLVM_READONLY
getPrimitiveSizeInBits - Return the basic size of this type if it is a primitive type.
SDValue getZExtOrTrunc(SDValue Op, SDLoc DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either zero-extending or trunca...
LLVM Value Representation.
FMA - Perform a * b + c with no intermediate rounding step.
SDValue getRegister(unsigned Reg, EVT VT)
SDValue getValueType(EVT)
unsigned ComputeNumSignBits(SDValue Op, unsigned Depth=0) const
Return the number of times the sign bit of the register is replicated into the other bits...
const TargetLowering & getTargetLoweringInfo() const
void ReplaceAllUsesOfValueWith(SDValue From, SDValue To)
Replace any uses of From with To, leaving uses of other values produced by From.Val alone...
static EVT getEquivalentMemType(LLVMContext &Context, EVT VT)
Primary interface to the complete machine description for the target machine.
bool hasBCNT(unsigned Size) const
bool isZExtFree(Type *Src, Type *Dest) const override
Return true if any actual instruction that defines a value of type Ty1 implicitly zero-extends the va...
StringRef - Represent a constant reference to a string, i.e.
FMAD - Perform a * b + c, while getting the same result as the separately rounded operations...
SetCC operator - This evaluates to a true value iff the condition is true.
unsigned getImplicitParameterOffset(const AMDGPUMachineFunction *MFI, const ImplicitParameter Param) const
Helper function that returns the byte offset of the given type of implicit parameter.
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
unsigned getOrigAlign() const
SDValue getConstantFP(double Val, SDLoc DL, EVT VT, bool isTarget=false)
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml","ocaml 3.10-compatible collector")
SDValue getSetCC(SDLoc DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const
TRUNCATE - Completely drop the high bits.
unsigned getAlignment() const
bool ShouldShrinkFPConstant(EVT VT) const override
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2, FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR - Perform various unary floating point operations.
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
getIntegerVT - Returns the EVT that represents an integer with the given number of bits...
unsigned AllocateStack(unsigned Size, unsigned Align)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
MVT getVectorIdxTy(const DataLayout &) const override
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
bool PredictableSelectIsExpensive
Tells the code generator that select is more expensive than a branch if the branch is usually predict...
SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const
void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO)
bool isSelectSupported(SelectSupportKind) const override
uint64_t getZExtValue() const
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
unsigned getVectorNumElements() const
getVectorNumElements - Given a vector type, return the number of elements it contains.
This class is used to represent ISD::LOAD nodes.