23 #ifndef LLVM_TARGET_TARGETLOWERING_H
24 #define LLVM_TARGET_TARGETLOWERING_H
47 class FunctionLoweringInfo;
48 class ImmutableCallSite;
50 class MachineBasicBlock;
51 class MachineFunction;
53 class MachineJumpTableInfo;
59 template<
typename T>
class SmallVectorImpl;
61 class TargetRegisterClass;
62 class TargetLibraryInfo;
63 class TargetLoweringObjectFile;
196 return HasMultipleConditionRegisters;
223 unsigned DefinedValues)
const {
224 return DefinedValues < 3;
242 return BypassSlowDivWidths;
275 unsigned AddrSpace)
const {
313 unsigned &Cost)
const {
319 return HasFloatingPointExceptions;
354 return BooleanVectorContents;
355 return isFloat ? BooleanFloatContents : BooleanContents;
364 return SchedPreferenceInfo;
378 assert(RC &&
"This value type is not natively supported!");
397 return RepRegClassCostForVT[VT.
SimpleTy];
425 ValueTypeActions[
I] = Action;
430 return ValueTypeActions;
438 return getTypeConversion(Context, VT).first;
451 return getTypeConversion(Context, VT).second;
483 unsigned &NumIntermediates,
484 MVT &RegisterVT)
const;
619 "Table isn't big enough!");
636 "Table isn't big enough!");
638 return (
LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
654 "Table isn't big enough!");
673 "Table isn't big enough!");
675 uint32_t Shift = 2 * (VT.
SimpleTy & 0xF);
678 assert(Action !=
Promote &&
"Can't promote condition code!");
694 "This operation isn't promoted!");
697 std::map<std::pair<unsigned, MVT::SimpleValueType>,
699 PromoteToType.find(std::make_pair(Op, VT.
SimpleTy));
700 if (PTTI != PromoteToType.end())
return PTTI->second;
703 "Cannot autopromote this type, add it with AddPromotedToType.");
709 "Didn't find type to promote to!");
720 bool AllowUnknown =
false)
const {
729 if (
PointerType *PT = dyn_cast<PointerType>(Elm)) {
742 bool AllowUnknown =
false)
const {
754 return RegisterTypeForVT[VT.
SimpleTy];
767 unsigned NumIntermediates;
769 NumIntermediates, RegisterVT);
795 unsigned NumIntermediates;
801 return (BitWidth + RegWidth - 1) / RegWidth;
831 assert(
unsigned(NT >> 3) <
array_lengthof(TargetDAGCombineArray));
832 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
875 unsigned AddrSpace = 0,
877 bool * =
nullptr)
const {
893 unsigned ,
unsigned ,
912 return UseUnderscoreSetJmp;
917 return UseUnderscoreLongJmp;
923 return MinimumJumpTableEntries;
929 return StackPointerRegisterToSaveRestore;
935 return ExceptionPointerRegister;
941 return ExceptionSelectorRegister;
953 return JumpBufAlignment;
958 return MinStackArgumentAlignment;
963 return MinFunctionAlignment;
968 return PrefFunctionAlignment;
973 return PrefLoopAlignment;
979 return InsertFencesForAtomic;
1000 unsigned & )
const {
1073 bool IsLoad)
const {
1085 bool IsLoad)
const {
1161 BooleanContents = Ty;
1162 BooleanFloatContents = Ty;
1168 BooleanContents = IntTy;
1169 BooleanFloatContents = FloatTy;
1175 BooleanVectorContents = Ty;
1180 SchedPreferenceInfo = Pref;
1186 UseUnderscoreSetJmp = Val;
1192 UseUnderscoreLongJmp = Val;
1198 MinimumJumpTableEntries = Val;
1204 StackPointerRegisterToSaveRestore = R;
1210 ExceptionPointerRegister = R;
1216 ExceptionSelectorRegister = R;
1222 SelectIsExpensive = isExpensive;
1231 HasMultipleConditionRegisters = hasManyRegs;
1239 HasExtractBitsInsn = hasExtractInsn;
1259 HasFloatingPointExceptions = FPExceptions;
1264 BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
1276 AvailableRegClasses.push_back(std::make_pair(VT, RC));
1284 AvailableRegClasses.clear();
1293 virtual std::pair<const TargetRegisterClass *, uint8_t>
1304 assert(Op <
array_lengthof(OpActions[0]) &&
"Table isn't big enough!");
1313 MemVT.
isValid() &&
"Table isn't big enough!");
1321 assert(ValVT.
isValid() && MemVT.
isValid() &&
"Table isn't big enough!");
1333 (
unsigned)Action < 0xf &&
"Table isn't big enough!");
1336 IndexedModeActions[(
unsigned)VT.
SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1347 (
unsigned)Action < 0xf &&
"Table isn't big enough!");
1350 IndexedModeActions[(
unsigned)VT.
SimpleTy][IdxMode] |= ((uint8_t)Action);
1358 "Table isn't big enough!");
1362 uint32_t Shift = 2 * (VT.
SimpleTy & 0xF);
1363 CondCodeActions[CC][VT.
SimpleTy >> 4] &= ~((uint32_t)0x3 << Shift);
1364 CondCodeActions[CC][VT.
SimpleTy >> 4] |= (uint32_t)Action << Shift;
1379 assert(
unsigned(NT >> 3) <
array_lengthof(TargetDAGCombineArray));
1380 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1391 JumpBufAlignment =
Align;
1396 MinFunctionAlignment =
Align;
1403 PrefFunctionAlignment =
Align;
1411 PrefLoopAlignment =
Align;
1416 MinStackArgumentAlignment =
Align;
1422 InsertFencesForAtomic = fence;
1438 unsigned AddrSpace = 0)
const {
1468 Type *Ty,
unsigned AddrSpace)
const;
1478 Type *Ty,
unsigned AS = 0)
const {
1540 case Instruction::FPExt:
1544 case Instruction::ZExt:
1548 case Instruction::SExt:
1594 unsigned & )
const {
1599 unsigned & )
const {
1617 unsigned Factor)
const {
1628 unsigned Factor)
const {
1713 return LibcallRoutineNames[
Call];
1719 CmpLibcallCCs[
Call] = CC;
1725 return CmpLibcallCCs[
Call];
1730 LibcallCallingConvs[
Call] = CC;
1735 return LibcallCallingConvs[
Call];
1743 bool SelectIsExpensive;
1750 bool HasMultipleConditionRegisters;
1756 bool HasExtractBitsInsn;
1775 bool Pow2SDivIsCheap;
1780 bool JumpIsExpensive;
1784 bool HasFloatingPointExceptions;
1789 bool UseUnderscoreSetJmp;
1794 bool UseUnderscoreLongJmp;
1797 int MinimumJumpTableEntries;
1816 unsigned JumpBufSize;
1819 unsigned JumpBufAlignment;
1822 unsigned MinStackArgumentAlignment;
1826 unsigned MinFunctionAlignment;
1830 unsigned PrefFunctionAlignment;
1833 unsigned PrefLoopAlignment;
1838 bool InsertFencesForAtomic;
1842 unsigned StackPointerRegisterToSaveRestore;
1846 unsigned ExceptionPointerRegister;
1850 unsigned ExceptionSelectorRegister;
1911 ValueTypeActionImpl ValueTypeActions;
1917 std::vector<std::pair<MVT, const TargetRegisterClass*> > AvailableRegClasses;
2091 unsigned NumOps,
bool isSigned,
2092 SDLoc dl,
bool doesNotReturn =
false,
2093 bool isReturnValueUsed =
true)
const;
2144 TargetLoweringOpt &TLO,
unsigned Depth = 0)
const;
2152 unsigned Depth = 0)
const;
2158 unsigned Depth = 0)
const;
2199 DAGCombinerInfo &DCI,
SDLoc dl)
const;
2342 unsigned FixedArgs = -1) {
2347 (FixedArgs ==
static_cast<unsigned>(-1) ?
Args.size() : FixedArgs);
2348 Args = std::move(ArgsList);
2368 Args = std::move(ArgsList);
2425 std::pair<SDValue, SDValue>
LowerCallTo(CallLoweringInfo &CLI)
const;
2484 return "__clear_cache";
2504 return VT.
bitsLT(MinVT) ? MinVT : VT;
2512 bool isVarArg)
const {
2697 virtual std::pair<unsigned, const TargetRegisterClass *>
2702 if (ConstraintCode ==
"i")
2704 else if (ConstraintCode ==
"m")
2717 std::vector<SDValue> &Ops,
2724 bool IsAfterLegalization,
2725 std::vector<SDNode *> *Created)
const;
2727 bool IsAfterLegalization,
2728 std::vector<SDNode *> *Created)
const;
2731 std::vector<SDNode *> *Created)
const {
2755 unsigned &RefinementSteps,
2756 bool &UseOneConstNR)
const {
2769 unsigned &RefinementSteps)
const {
2830 SmallVectorImpl<ISD::OutputArg> &Outs,
2831 const TargetLowering &TLI,
const DataLayout &DL);
virtual bool enableAggressiveFMAFusion(EVT VT) const
Return true if target always beneficiates from combining into FMA for a given value type...
virtual SDValue LowerReturn(SDValue, CallingConv::ID, bool, const SmallVectorImpl< ISD::OutputArg > &, const SmallVectorImpl< SDValue > &, SDLoc, SelectionDAG &) const
This hook must be implemented to lower outgoing return values, described by the Outs array...
virtual bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const
Lower an interleaved store to target specific intrinsics.
static MVT getIntegerVT(unsigned BitWidth)
BUILTIN_OP_END - This must be the last enum value in this list.
bool LegalOperations() const
A parsed version of the target data layout string in and methods for querying it. ...
const_iterator end(StringRef path)
Get end iterator over path.
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
CallLoweringInfo & setCallee(CallingConv::ID CC, Type *ResultType, SDValue Target, ArgListTy &&ArgsList, unsigned FixedArgs=-1)
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const
Return true if the specified indexed load is legal on this target.
CombineLevel getDAGCombineLevel()
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT, SelectionDAG &DAG, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) const
Expand a MUL into two nodes.
SDValue CombineTo(SDNode *N, ArrayRef< SDValue > To, bool AddTo=true)
unsigned getMaxStoresPerMemcpy(bool OptSize) const
Get maximum # of store operations permitted for llvm.memcpy.
LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const
Return how we should legalize values of this type, either it is already legal (return 'Legal') or we ...
unsigned getPrefFunctionAlignment() const
Return the preferred function alignment.
Sign extended before/after call.
unsigned getNumRegisters(LLVMContext &Context, EVT VT) const
Return the number of registers that this ValueType will eventually require.
virtual bool storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem, unsigned AddrSpace) const
Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the give...
Force argument to be passed in register.
unsigned getNumParams() const
getNumParams - Return the number of fixed parameters this function type requires. ...
bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded)
Check to see if the specified operand of the specified instruction is a constant integer.
const TargetMachine & getTargetMachine() const
InstrTy * getInstruction() const
bool isAtLeastAcquire(AtomicOrdering Ord)
Returns true if the ordering is at least as strong as acquire (i.e.
virtual bool isCheapToSpeculateCttz() const
Return true if it is cheap to speculate a call to intrinsic cttz.
bool isCalledByLegalizer() const
void setJumpBufAlignment(unsigned Align)
Set the target's required jmp_buf buffer alignment (in bytes); default is 0.
CallLoweringInfo & setDebugLoc(SDLoc dl)
virtual bool hasLoadLinkedStoreConditional() const
True if AtomicExpandPass should use emitLoadLinked/emitStoreConditional and expand AtomicCmpXchgInst...
bool isIntDivCheap() const
Return true if integer divide is usually cheaper than a sequence of several shifts, adds, and multiplies for this target.
bool isConstTrueVal(const SDNode *N) const
Return if the N is a constant or constant vector equal to the true value from getBooleanContents().
virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL, SelectionDAG &DAG) const
This callback is used to prepare for a volatile or atomic load.
virtual bool allowTruncateForTailCall(Type *, Type *) const
Return true if a truncation from Ty1 to Ty2 is permitted when deciding whether a call is in tail posi...
bool isExtended() const
isExtended - Test if the given EVT is extended (as opposed to being simple).
virtual bool isLoadBitCastBeneficial(EVT, EVT) const
isLoadBitCastBeneficial() - Return true if the following transform is beneficial. ...
CallInst - This class represents a function call, abstracting a target machine's calling convention...
MVT getSimpleValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the MVT corresponding to this LLVM type. See getValueType.
bool usesUnderscoreSetJmp() const
Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
virtual unsigned getMaxSupportedInterleaveFactor() const
Get the maximum supported factor for interleaved memory accesses.
void setHasFloatingPointExceptions(bool FPExceptions=true)
Tells the code generator that this target supports floating point exceptions and cares about preservi...
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
virtual bool getPreIndexedAddressParts(SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const
Returns true by value, base pointer and offset pointer and addressing mode by reference if the node's...
static ISD::NodeType getExtendForContent(BooleanContent Content)
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
virtual bool isFAbsFree(EVT VT) const
Return true if an fabs operation is free to the point where it is never worthwhile to replace it with...
Type * getTypeForEVT(LLVMContext &Context) const
getTypeForEVT - This method returns an LLVM type corresponding to the specified EVT.
unsigned getSizeInBits() const
ShuffleVectorInst - This instruction constructs a fixed permutation of two input vectors.
bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded, SDLoc dl)
Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free.
virtual bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg) const
For some targets, an LLVM struct type must be broken down into multiple simple types, but the calling convention specifies that the entire struct must be passed in a block of consecutive registers.
virtual bool isLegalICmpImmediate(int64_t) const
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
CallLoweringInfo & setNoReturn(bool Value=true)
const_iterator begin(StringRef path)
Get begin iterator over path.
void clearOperationActions()
Remove all operation actions.
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
virtual bool isZExtFree(Type *, Type *) const
Return true if any actual instruction that defines a value of type Ty1 implicitly zero-extends the va...
virtual bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace=0, unsigned Align=1, bool *=nullptr) const
Determine if the target supports unaligned memory accesses.
LoadInst - an instruction for reading from memory.
bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const
Expand float(f32) to SINT(i64) conversion.
virtual bool shouldExpandBuildVectorWithShuffles(EVT, unsigned DefinedValues) const
AtomicRMWInst - an instruction that atomically reads a memory location, combines it with another valu...
virtual bool GetAddrModeArguments(IntrinsicInst *, SmallVectorImpl< Value * > &, Type *&, unsigned AddrSpace=0) const
CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the add...
std::pair< LegalizeTypeAction, EVT > LegalizeKind
LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it...
virtual bool isFPExtFree(EVT VT) const
Return true if an fpext operation is free (for instance, because single-precision floating-point numb...
Value * CallOperandVal
If this is the result output operand or a clobber, this is null, otherwise it is the incoming operand...
LegalizeAction getOperationAction(unsigned Op, EVT VT) const
Return how this operation should be treated: either it is legal, needs to be promoted to a larger siz...
virtual void HandleByVal(CCState *, unsigned &, unsigned) const
Target-specific cleanup for formal ByVal parameters.
CallLoweringInfo & setDiscardResult(bool Value=true)
SDValue BuildUDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode * > *Created) const
Given an ISD::UDIV node expressing a divide by constant, return a DAG expression to select that will ...
virtual bool isFPImmLegal(const APFloat &, EVT) const
Returns true if the target can instruction select the specified FP immediate natively.
virtual void AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag...
LegalizeTypeAction getTypeAction(MVT VT) const
virtual const TargetRegisterClass * getRepRegClassFor(MVT VT) const
Return the 'representative' register class for the specified value type.
virtual bool isTypeDesirableForOp(unsigned, EVT VT) const
Return true if the target has native support for the specified value type and it is 'desirable' to us...
virtual Sched::Preference getSchedulingPreference(SDNode *) const
Some scheduler, e.g.
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
bool bitsLT(EVT VT) const
bitsLT - Return true if this has less bits than VT.
bool isAfterLegalizeVectorOps() const
bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, APInt &KnownZero, APInt &KnownOne, TargetLoweringOpt &TLO, unsigned Depth=0) const
Look at Op.
virtual LoadInst * lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) const
On some platforms, an AtomicRMW that never actually modifies the value (such as fetch_add of 0) can b...
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag=true)
Reports a serious error, calling any installed error handler.
bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const
Return true if the specified indexed load is legal on this target.
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
A convenience struct that encapsulates a DAG, and two SDValues for returning information from TargetL...
bool enableExtLdPromotion() const
Return true if the target wants to use the optimization that turns ext(promotableInst1(...(promotableInstN(load)))) into promotedInst1(...(promotedInstN(ext(load)))).
AtomicRMWExpansionKind
Enum that specifies what a AtomicRMWInst is expanded to, if at all.
bool isVector() const
isVector - Return true if this is a vector value type.
virtual const char * LowerXConstraint(EVT ConstraintVT) const
Try to replace an X constraint, which matches anything, with another that has more specific requireme...
void setAttributes(ImmutableCallSite *CS, unsigned AttrIdx)
Set CallLoweringInfo attribute flags based on a call instruction and called function attributes...
virtual bool canOpTrap(unsigned Op, EVT VT) const
Returns true if the operation can trap for the value type.
virtual bool shouldNormalizeToSelectSequence(LLVMContext &Context, EVT VT) const
Returns true if we should normalize select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely that it saves us from materializing N0 and N1 in an integer register.
virtual const char * getTargetNodeName(unsigned Opcode) const
This method returns the name of a target specific DAG node.
virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const
This method will be invoked for all target nodes and for any target-independent nodes that the target...
bool hasMultipleConditionRegisters() const
Return true if multiple condition registers are available.
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
virtual bool isLegalAddImmediate(int64_t) const
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
virtual bool isZExtFree(EVT, EVT) const
CallLoweringInfo & setVarArg(bool Value=true)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
std::pair< SDValue, SDValue > makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops, unsigned NumOps, bool isSigned, SDLoc dl, bool doesNotReturn=false, bool isReturnValueUsed=true) const
Returns a pair of (return value, chain).
TargetLowering::ConstraintType ConstraintType
Information about the constraint code, e.g.
virtual void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth=0) const
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
CallLoweringInfo & setChain(SDValue InChain)
virtual AtomicRMWExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all...
Base class for the full range of assembler expressions which are needed for parsing.
virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast between SrcAS and DestAS is a noop.
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn't supported on the target and indicate what to d...
bool doesNotReturn() const
Determine if the call cannot return.
This file contains the simple types necessary to represent the attributes associated with functions a...
bool getInsertFencesForAtomic() const
Return whether the DAG builder should automatically insert fences and reduce ordering for atomics...
void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth)
Tells the code generator which bitwidths to bypass.
unsigned getJumpBufSize() const
Returns the target's jmp_buf size in bytes (if never set, the default is 200)
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
virtual Value * emitLoadLinked(IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type...
void setJumpIsExpensive(bool isExpensive=true)
Tells the code generator not to expand logic operations on comparison predicates into separate sequen...
SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, SDLoc dl) const
Try to simplify a setcc built with the specified operands and cc.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Sched::Preference getSchedulingPreference() const
Return target scheduling preference.
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
int InstructionOpcodeToISD(unsigned Opcode) const
Get the ISD node that corresponds to the Instruction class opcode.
bool isExtFree(const Instruction *I) const
Return true if the extension represented by I is free.
SmallVector< ISD::InputArg, 32 > Ins
virtual MVT getVectorIdxTy(const DataLayout &DL) const
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
virtual bool getPostIndexedAddressParts(SDNode *, SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const
Returns true by value, base pointer and offset pointer and addressing mode by reference if this node ...
bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const
When splitting a value of the specified type into parts, does the Lo or Hi part come first...
Context object for machine code objects.
const DenseMap< unsigned int, unsigned int > & getBypassSlowDivWidths() const
Returns map of slow types for division or remainder with corresponding fast types.
virtual bool ShouldShrinkFPConstant(EVT) const
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
virtual bool mayBeEmittedAsTailCall(CallInst *) const
Return true if the target may be able emit the call instruction as a tail call.
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
virtual bool isUsedByReturnOnly(SDNode *, SDValue &) const
Return true if result of the specified node is used by a return node only.
FunctionType - Class to represent function types.
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
void setSelectIsExpensive(bool isExpensive=true)
Tells the code generator not to expand operations into sequences that use the select operations if po...
bool usesUnderscoreLongJmp() const
Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
LLVMContext & getContext() const
getContext - Return the LLVMContext in which this type was uniqued.
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
void GetReturnInfo(Type *ReturnType, AttributeSet attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags...
virtual EVT getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT, ISD::NodeType) const
Return the type that should be used to zero or sign extend a zeroext/signext integer argument or retu...
const ValueTypeActionImpl & getValueTypeActions() const
This contains information for each constraint that we are lowering.
SmallVector< ISD::OutputArg, 32 > Outs
LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const
Return how this store with truncation should be treated: either it is legal, needs to be promoted to ...
void setFsqrtIsCheap(bool isCheap=true)
Tells the code generator that fsqrt is cheap, and should not be replaced with an alternative sequence...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
CallLoweringInfo & setZExtResult(bool Value=true)
MachineBasicBlock * emitPatchPoint(MachineInstr *MI, MachineBasicBlock *MBB) const
Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that...
StoreInst - an instruction for storing to memory.
int getMinimumJumpTableEntries() const
Return integer threshold on number of blocks to use jump tables rather than if sequence.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
virtual SDValue LowerCall(CallLoweringInfo &, SmallVectorImpl< SDValue > &) const
This hook must be implemented to lower calls into the specified DAG.
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
virtual bool isDesirableToTransformToIntegerOp(unsigned, EVT) const
Return true if it is profitable for dag combiner to transform a floating point op of specified opcode...
virtual Instruction * emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord, bool IsStore, bool IsLoad) const
Inserts in the IR a target-specific intrinsic specifying a fence.
bool isOperationLegalOrPromote(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target or can be made legal using promotion...
unsigned getNumElements() const
Return the number of elements in the Vector type.
virtual bool isSelectSupported(SelectSupportKind) const
virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const
Return true if it is beneficial to convert a load of a constant to just the constant itself...
bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const
Return true if the specified load with extension is legal or custom on this target.
virtual bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const
Type * getElementType() const
virtual const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const
Returns a 0 terminated array of registers that can be safely used as scratch registers.
LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT, EVT MemVT) const
Return how this load with extension should be treated: either it is legal, needs to be promoted to a ...
bool isLegalRC(const TargetRegisterClass *RC) const
Return true if the value types that can be represented by the specified register class are all legal...
PointerType - Class to represent pointers.
virtual bool getStackCookieLocation(unsigned &, unsigned &) const
Return true if the target stores stack protector cookies at a fixed offset in some non-standard addre...
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const
Return true if the specified store with truncation is legal on this target.
A self-contained host- and target-independent arbitrary-precision floating-point software implementat...
virtual bool isTruncateFree(EVT, EVT) const
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
bool isMatchingInputConstraint() const
Return true of this is an input operand that is a matching constraint like "4".
virtual FastISel * createFastISel(FunctionLoweringInfo &, const TargetLibraryInfo *) const
This method returns a target specific FastISel object, or null if the target does not support "fast" ...
virtual Instruction * emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord, bool IsStore, bool IsLoad) const
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
virtual bool isShuffleMaskLegal(const SmallVectorImpl< int > &, EVT) const
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks.
BooleanContent getBooleanContents(EVT Type) const
bool hasFloatingPointExceptions() const
Return true if target supports floating point exceptions.
MVT - Machine Value Type.
DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
CallLoweringInfo & setIsPatchPoint(bool Value=true)
The instances of the Type class are immutable: once they are created, they are never changed...
This is an important class for using LLVM in a threaded context.
void setJumpBufSize(unsigned Size)
Set the target's required jmp_buf buffer size (in bytes); default is 200.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
bool isFsqrtCheap() const
Return true if sqrt(x) is as cheap or cheaper than 1 / rsqrt(x)
void setTargetDAGCombine(ISD::NodeType NT)
Targets should invoke this method for each target independent node that they want to provide a custom...
bool isVectorTy() const
isVectorTy - True if this is an instance of VectorType.
virtual bool shouldExpandAtomicStoreInIR(StoreInst *SI) const
Returns true if the given (atomic) store should be expanded by the IR-level AtomicExpand pass into an...
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
virtual EVT getOptimalMemOpType(uint64_t, unsigned, unsigned, bool, bool, bool, MachineFunction &) const
Returns the target specific optimal type for load and store operations as a result of memset...
virtual unsigned getPrefLoopAlignment(MachineLoop *ML=nullptr) const
Return the preferred loop alignment.
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
LegalizeAction
This enum indicates whether operations are valid for a target, and if not, what action should be used...
unsigned getMatchedOperand() const
If this is an input matching constraint, this method returns the output operand it matches...
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
bool isMaskAndBranchFoldingLegal() const
Return if the target supports combining a chain like:
bool isBeforeLegalizeOps() const
virtual bool isSafeMemOpType(MVT) const
Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline...
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
unsigned getMaxStoresPerMemmove(bool OptSize) const
Get maximum # of store operations permitted for llvm.memmove.
virtual bool isDesirableToCommuteWithShift(const SDNode *N) const
Return true if it is profitable to move a following shift through this.
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
ConstraintInfo()
Default constructor.
void AddToWorklist(SDNode *N)
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
virtual bool isTruncateFree(Type *, Type *) const
Return true if it's free to truncate a value of type Ty1 to type Ty2.
virtual bool isFMAFasterThanFMulAndFAdd(EVT) const
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
bool isBeforeLegalize() const
virtual unsigned getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const
Return the register ID of the name passed in.
bool CombineTo(SDValue O, SDValue N)
virtual bool useSoftFloat() const
Value * getOperand(unsigned i) const
Zero extended before/after call.
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
virtual bool isNarrowingProfitable(EVT, EVT) const
Return true if it's profitable to narrow operations of type VT1 to VT2.
bool isPredictableSelectExpensive() const
Return true if selects are only cheaper than branches if the branch is unlikely to be predicted right...
void setPrefFunctionAlignment(unsigned Align)
Set the target's preferred function alignment.
virtual bool useLoadStackGuardNode() const
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
virtual SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI, unsigned &RefinementSteps) const
Return a reciprocal estimate value for the input operand.
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Vector types are broken down into some number of legal first class types.
unsigned MaxStoresPerMemmove
Specify maximum bytes of store instructions per memmove call.
bool isConstFalseVal(const SDNode *N) const
Return if the N is a constant or constant vector equal to the false value from getBooleanContents().
SDValue BuildSDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode * > *Created) const
Given an ISD::SDIV node expressing a divide by constant, return a DAG expression to select that will ...
virtual int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS=0) const
Return the cost of the scaling factor used in the addressing mode represented by AM for this target...
unsigned getStackPointerRegisterToSaveRestore() const
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save...
void setPow2SDivIsCheap(bool isCheap=true)
Tells the code generator that it shouldn't generate sra/srl/add/sra for a signed divide by power of t...
EVT - Extended Value Type.
bool isSlowDivBypassed() const
Returns true if target has indicated at least one type should be bypassed.
LegalizeTypeAction getTypeAction(MVT VT) const
std::vector< ArgListEntry > ArgListTy
unsigned getExceptionPointerRegister() const
If a physical register, this returns the register that receives the exception address on entry to a l...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const
Return the desired alignment for ByVal or InAlloca aggregate function arguments in the caller paramet...
This structure contains all information that is necessary for lowering calls.
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
For targets without i1 registers, this gives the nature of the high-bits of boolean values held in ty...
virtual bool isExtFreeImpl(const Instruction *I) const
Return true if the extension represented by I is free.
virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const
Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable...
bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const
Return true if the specified load with extension is legal on this target.
virtual SDValue LowerFormalArguments(SDValue, CallingConv::ID, bool, const SmallVectorImpl< ISD::InputArg > &, SDLoc, SelectionDAG &, SmallVectorImpl< SDValue > &) const
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array...
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements)
getVectorVT - Returns the EVT that represents a vector NumElements in length, where each element is o...
void setUseUnderscoreLongJmp(bool Val)
Indicate whether this target prefers to use _longjmp to implement llvm.longjmp or the version without...
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
AsmOperandInfo(InlineAsm::ConstraintInfo Info)
Copy constructor for copying from a ConstraintInfo.
std::string ConstraintCode
This contains the actual string for the code, like "m".
virtual SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const
Returns relocation base for the given PIC jumptable.
virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=nullptr) const
Determines the constraint code and constraint type to use for the specific AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from ...
ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const
Get the CondCode that's to be used to test the result of the comparison libcall against zero...
void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC)
Override the default CondCode to be used to test the result of the comparison libcall against zero...
void setHasExtractBitsInsn(bool hasExtractInsn=true)
Tells the code generator that the target has BitExtract instructions.
virtual ~TargetLoweringBase()
virtual void ReplaceNodeResults(SDNode *, SmallVectorImpl< SDValue > &, SelectionDAG &) const
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
void initActions()
Initialize all of the actions to default values.
std::vector< AsmOperandInfo > AsmOperandInfoVector
virtual MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
CCState - This class holds information needed while lowering arguments and return values...
virtual bool hasPairedLoad(Type *, unsigned &) const
Return true if the target supplies and combines to a paired load two loaded values of type LoadedType...
virtual unsigned getJumpTableEncoding() const
Return the entry encoding for a jump table in the current function.
bool MaskAndBranchFoldingIsLegal
MaskAndBranchFoldingIsLegal - Indicates if the target supports folding a mask of a single bit...
virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, std::vector< SDNode * > *Created) const
void RemoveFromWorklist(SDNode *N)
const char * getLibcallName(RTLIB::Libcall Call) const
Get the libcall routine name for the specified libcall.
virtual bool combineRepeatedFPDivisors(unsigned NumUsers) const
Indicate whether this target prefers to combine the given number of FDIVs with the same divisor...
LegalizeAction getIndexedStoreAction(unsigned IdxMode, MVT VT) const
Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger ...
bool paramHasAttr(unsigned i, Attribute::AttrKind A) const
Return true if the call or the callee has the given attribute.
void setExceptionPointerRegister(unsigned R)
If set to a physical register, this sets the register that receives the exception address on entry to...
virtual bool isVectorClearMaskLegal(const SmallVectorImpl< int > &, EVT) const
Similar to isShuffleMaskLegal.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
Type * getType() const
All values are typed, get the type of this value.
Provides information about what library functions are available for the current target.
virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const
Return the ValueType of the result of SETCC operations.
virtual Value * emitStoreConditional(IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const
Perform a store-conditional operation to Addr.
TargetLoweringOpt(SelectionDAG &InDAG, bool LT, bool LO)
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
void setHasMultipleConditionRegisters(bool hasManyRegs=true)
Tells the code generator that the target has multiple (allocatable) condition registers that can be u...
CallLoweringInfo & setSExtResult(bool Value=true)
virtual const MCExpr * getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const
This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase, but as an MCExpr.
virtual bool isGAPlusOffset(SDNode *N, const GlobalValue *&GA, int64_t &Offset) const
Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + offset...
Represents one node in the SelectionDAG.
virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const
Returns true if arguments should be sign-extended in lib calls.
void clearRegisterClasses()
Remove all register classes.
bool hasExtractBitsInsn() const
Return true if the target has BitExtract instructions.
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const SelectionDAG &DAG, unsigned Depth=0) const
This method can be implemented by targets that want to expose additional information about sign bits ...
bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node, SDValue &Chain) const
Check whether a given call node is in tail position within its function.
virtual bool isProfitableToHoist(Instruction *I) const
VectorType - Class to represent vector types.
void setMinimumJumpTableEntries(int Val)
Indicate the number of blocks to generate jump tables rather than if sequence.
virtual const char * getClearCacheBuiltinName() const
Return the builtin name for the __builtin___clear_cache intrinsic Default is to invoke the clear cach...
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
Target - Wrapper for Target specific information.
Class for arbitrary precision integers.
virtual bool IsDesirableToPromoteOp(SDValue, EVT &) const
This method query the target whether it is beneficial for dag combiner to promote the specified node...
void setExceptionSelectorRegister(unsigned R)
If set to a physical register, this sets the register that receives the exception typeid on entry to ...
void setMinFunctionAlignment(unsigned Align)
Set the target's minimum function alignment (in log2(bytes))
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
Return the register class that should be used for the specified value type.
void setPrefLoopAlignment(unsigned Align)
Set the target's preferred loop alignment.
ZERO_EXTEND - Used for integer types, zeroing the new bits.
AddrMode
ARM Addressing Modes.
ANY_EXTEND - Used for integer types. The high bits are undefined.
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT) const
Return the preferred vector type legalization action.
virtual bool shouldExpandAtomicLoadInIR(LoadInst *LI) const
Returns true if the given (atomic) load should be expanded by the IR-level AtomicExpand pass into a l...
virtual bool CanLowerReturn(CallingConv::ID, MachineFunction &, bool, const SmallVectorImpl< ISD::OutputArg > &, LLVMContext &) const
This hook should be implemented to check whether the return values described by the Outs array can fi...
virtual MVT::SimpleValueType getCmpLibcallReturnType() const
Return the ValueType for comparison libcalls.
CallLoweringInfo & setTailCall(bool Value=true)
MVT getRegisterType(LLVMContext &Context, EVT VT) const
Return the type of registers that this ValueType will eventually require.
Representation of each machine instruction.
SmallVector< SDValue, 32 > OutVals
bool isValid() const
isValid - Return true if this is a valid simple valuetype.
virtual bool lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const
Lower an interleaved load to target specific intrinsics.
LegalizeAction getIndexedLoadAction(unsigned IdxMode, MVT VT) const
Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger s...
virtual bool isVectorShiftByScalarCheap(Type *Ty) const
Return true if it's significantly cheaper to shift a vector by a uniform scalar than by an amount whi...
SelectSupportKind
Enum that describes what type of support for selects the target has.
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
unsigned getJumpBufAlignment() const
Returns the target's jmp_buf alignment in bytes (if never set, the default is 0)
void setTypeAction(MVT VT, LegalizeTypeAction Action)
virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AddrSpace) const
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
bool isPow2SDivCheap() const
Return true if pow2 sdiv is cheaper than a chain of sra/srl/add/sra.
virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const
EVT is not used in-tree, but is used by out-of-tree target.
unsigned getMinFunctionAlignment() const
Return the minimum function alignment.
unsigned getMaxStoresPerMemset(bool OptSize) const
Get maximum # of store operations permitted for llvm.memset.
ImmutableCallSite - establish a view to a call site for examination.
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
CallingConv::ID getCallingConv() const
getCallingConv/setCallingConv - get or set the calling convention of the call.
virtual std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const
Return the largest legal super-reg register class of the register class for the specified type and it...
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
unsigned MaxStoresPerMemmoveOptSize
Maximum number of store instructions that may be substituted for a call to memmove, used for functions with OpSize attribute.
unsigned MaxStoresPerMemcpyOptSize
Maximum number of store operations that may be substituted for a call to memcpy, used for functions w...
void setStackPointerRegisterToSaveRestore(unsigned R)
If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
FenceInst * CreateFence(AtomicOrdering Ordering, SynchronizationScope SynchScope=CrossThread, const Twine &Name="")
virtual const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *, const MachineBasicBlock *, unsigned, MCContext &) const
unsigned MaxStoresPerMemcpy
Specify maximum bytes of store instructions per memcpy call.
virtual SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI, unsigned &RefinementSteps, bool &UseOneConstNR) const
Hooks for building estimates in place of slower divisions and square roots.
virtual bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const
Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index.
static EVT getEVT(Type *Ty, bool HandleUnknown=false)
getEVT - Return the value type corresponding to the specified type.
bool isAtLeastRelease(AtomicOrdering Ord)
Returns true if the ordering is at least as strong as release (i.e.
EVT getValueType() const
Return the ValueType of the referenced return value.
CallLoweringInfo & setCallee(Type *ResultType, FunctionType *FTy, SDValue Target, ArgListTy &&ArgsList, ImmutableCallSite &Call)
bool isSelectExpensive() const
Return true if the select operation is expensive for this target.
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
virtual bool ExpandInlineAsm(CallInst *) const
This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to...
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
bool EnableExtLdPromotion
virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, unsigned) const
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
bool isFloat(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether it is a floating-point insn.
void setIntDivIsCheap(bool isCheap=true)
Tells the code generator that integer divide is expensive, and if possible, should be replaced by an ...
bool isSimple() const
isSimple - Test if the given EVT is simple (as opposed to being extended).
void setMinStackArgumentAlignment(unsigned Align)
Set the minimum stack alignment of an argument (in log2(bytes)).
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
CallLoweringInfo & setInRegister(bool Value=true)
EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
LLVM Value Representation.
void setUseUnderscoreSetJmp(bool Val)
Indicate whether this target prefers to use _setjmp to implement llvm.setjmp or the version without _...
unsigned getOpcode() const
getOpcode() returns a member of one of the enums like Instruction::Add.
void setInsertFencesForAtomic(bool fence)
Set if the DAG builder should automatically insert fences and reduce the order of atomic memory opera...
virtual bool isZExtFree(SDValue Val, EVT VT2) const
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicit...
bool hasTargetDAGCombine(ISD::NodeType NT) const
If true, the target has custom DAG combine transformations that it can perform for the specified node...
bool isOperationExpand(unsigned Op, EVT VT) const
Return true if the specified operation is illegal on this target or unlikely to be made legal with cu...
virtual ConstraintWeight getMultipleConstraintMatchWeight(AsmOperandInfo &info, int maIndex) const
Examine constraint type and operand type and determine a weight value.
CallLoweringInfo(SelectionDAG &DAG)
virtual uint8_t getRepRegClassCostFor(MVT VT) const
Return the cost of the 'representative' register class for the specified value type.
virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx, unsigned &Cost) const
Return true if the target can combine store(extractelement VectorTy, Idx).
Primary interface to the complete machine description for the target machine.
StringRef - Represent a constant reference to a string, i.e.
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
unsigned MaxStoresPerMemsetOptSize
Maximum number of stores operations that may be substituted for the call to memset, used for functions with OptSize attribute.
virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const
Return true if folding a constant offset with the given GlobalAddress is legal.
unsigned getMinStackArgumentAlignment() const
Return the minimum stack alignment of an argument.
unsigned getExceptionSelectorRegister() const
If a physical register, this returns the register that receives the exception typeid on entry to a la...
MVT ConstraintVT
The ValueType for the operand value.
BooleanContent
Enum that describes how the target represents true/false values.
EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL) const
bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const
Return true if the specified condition code is legal on this target.
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
Examine constraint string and operand type and determine a weight value.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
bool isJumpExpensive() const
Return true if Flow Control is an expensive operation that should be avoided.
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const
This callback is invoked for operations that are unsupported by the target, which are registered to u...
virtual bool isFNegFree(EVT VT) const
Return true if an fneg operation is free to the point where it is never worthwhile to replace it with...
std::pair< unsigned, MVT > getTypeLegalizationCost(const DataLayout &DL, Type *Ty) const
Estimate the cost of type-legalization and the legalized type.
virtual bool hasPairedLoad(EVT, unsigned &) const
virtual bool shouldAlignPointerArgs(CallInst *, unsigned &, unsigned &) const
Return true if the pointer arguments to CI should be aligned by aligning the object whose address is ...
void setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
virtual AsmOperandInfoVector ParseConstraints(const DataLayout &DL, const TargetRegisterInfo *TRI, ImmutableCallSite CS) const
Split up the constraint string from the inline assembly value into the specific constraints and their...
LegalizeAction getCondCodeAction(ISD::CondCode CC, MVT VT) const
Return how the condition code should be treated: either it is legal, needs to be expanded to some oth...
bool PredictableSelectIsExpensive
Tells the code generator that select is more expensive than a branch if the branch is usually predict...
virtual void LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const
This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but leg...
MVT getSimpleVT() const
getSimpleVT - Return the SimpleValueType held in the specified simple EVT.
IntrinsicInst - A useful wrapper class for inspecting calls to intrinsic functions.
void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO)
virtual bool isCheapToSpeculateCtlz() const
Return true if it is cheap to speculate a call to intrinsic ctlz.
void setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed store does or does not work with the specified type and indicate ...
MVT getTypeToPromoteTo(unsigned Op, MVT VT) const
If the action for this operation is to promote, this method returns the ValueType to promote to...
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
unsigned getVectorNumElements() const
getVectorNumElements - Given a vector type, return the number of elements it contains.
void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, SDLoc DL) const
SoftenSetCCOperands - Soften the operands of a comparison.