LLVM  3.7.0
X86Disassembler.cpp
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1 //===-- X86Disassembler.cpp - Disassembler for x86 and x86_64 -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file is part of the X86 Disassembler.
11 // It contains code to translate the data produced by the decoder into
12 // MCInsts.
13 // Documentation for the disassembler can be found in X86Disassembler.h.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #include "X86Disassembler.h"
18 #include "X86DisassemblerDecoder.h"
19 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCDisassembler.h"
21 #include "llvm/MC/MCExpr.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/MC/MCInstrInfo.h"
25 #include "llvm/Support/Debug.h"
28 
29 using namespace llvm;
30 using namespace llvm::X86Disassembler;
31 
32 #define DEBUG_TYPE "x86-disassembler"
33 
34 #define GET_REGINFO_ENUM
35 #include "X86GenRegisterInfo.inc"
36 #define GET_INSTRINFO_ENUM
37 #include "X86GenInstrInfo.inc"
38 #define GET_SUBTARGETINFO_ENUM
39 #include "X86GenSubtargetInfo.inc"
40 
41 void llvm::X86Disassembler::Debug(const char *file, unsigned line,
42  const char *s) {
43  dbgs() << file << ":" << line << ": " << s;
44 }
45 
46 const char *llvm::X86Disassembler::GetInstrName(unsigned Opcode,
47  const void *mii) {
48  const MCInstrInfo *MII = static_cast<const MCInstrInfo *>(mii);
49  return MII->getName(Opcode);
50 }
51 
52 #define debug(s) DEBUG(Debug(__FILE__, __LINE__, s));
53 
54 namespace llvm {
55 
56 // Fill-ins to make the compiler happy. These constants are never actually
57 // assigned; they are just filler to make an automatically-generated switch
58 // statement work.
59 namespace X86 {
60  enum {
61  BX_SI = 500,
62  BX_DI = 501,
63  BP_SI = 502,
64  BP_DI = 503,
65  sib = 504,
66  sib64 = 505
67  };
68 }
69 
71 
72 }
73 
74 static bool translateInstruction(MCInst &target,
75  InternalInstruction &source,
76  const MCDisassembler *Dis);
77 
79  const MCSubtargetInfo &STI,
80  MCContext &Ctx,
81  std::unique_ptr<const MCInstrInfo> MII)
82  : MCDisassembler(STI, Ctx), MII(std::move(MII)) {
83  const FeatureBitset &FB = STI.getFeatureBits();
84  if (FB[X86::Mode16Bit]) {
85  fMode = MODE_16BIT;
86  return;
87  } else if (FB[X86::Mode32Bit]) {
88  fMode = MODE_32BIT;
89  return;
90  } else if (FB[X86::Mode64Bit]) {
91  fMode = MODE_64BIT;
92  return;
93  }
94 
95  llvm_unreachable("Invalid CPU mode");
96 }
97 
98 struct Region {
100  uint64_t Base;
101  Region(ArrayRef<uint8_t> Bytes, uint64_t Base) : Bytes(Bytes), Base(Base) {}
102 };
103 
104 /// A callback function that wraps the readByte method from Region.
105 ///
106 /// @param Arg - The generic callback parameter. In this case, this should
107 /// be a pointer to a Region.
108 /// @param Byte - A pointer to the byte to be read.
109 /// @param Address - The address to be read.
110 static int regionReader(const void *Arg, uint8_t *Byte, uint64_t Address) {
111  auto *R = static_cast<const Region *>(Arg);
112  ArrayRef<uint8_t> Bytes = R->Bytes;
113  unsigned Index = Address - R->Base;
114  if (Bytes.size() <= Index)
115  return -1;
116  *Byte = Bytes[Index];
117  return 0;
118 }
119 
120 /// logger - a callback function that wraps the operator<< method from
121 /// raw_ostream.
122 ///
123 /// @param arg - The generic callback parameter. This should be a pointe
124 /// to a raw_ostream.
125 /// @param log - A string to be logged. logger() adds a newline.
126 static void logger(void* arg, const char* log) {
127  if (!arg)
128  return;
129 
130  raw_ostream &vStream = *(static_cast<raw_ostream*>(arg));
131  vStream << log << "\n";
132 }
133 
134 //
135 // Public interface for the disassembler
136 //
137 
139  MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address,
140  raw_ostream &VStream, raw_ostream &CStream) const {
141  CommentStream = &CStream;
142 
143  InternalInstruction InternalInstr;
144 
145  dlog_t LoggerFn = logger;
146  if (&VStream == &nulls())
147  LoggerFn = nullptr; // Disable logging completely if it's going to nulls().
148 
149  Region R(Bytes, Address);
150 
151  int Ret = decodeInstruction(&InternalInstr, regionReader, (const void *)&R,
152  LoggerFn, (void *)&VStream,
153  (const void *)MII.get(), Address, fMode);
154 
155  if (Ret) {
156  Size = InternalInstr.readerCursor - Address;
157  return Fail;
158  } else {
159  Size = InternalInstr.length;
160  return (!translateInstruction(Instr, InternalInstr, this)) ? Success : Fail;
161  }
162 }
163 
164 //
165 // Private code that translates from struct InternalInstructions to MCInsts.
166 //
167 
168 /// translateRegister - Translates an internal register to the appropriate LLVM
169 /// register, and appends it as an operand to an MCInst.
170 ///
171 /// @param mcInst - The MCInst to append to.
172 /// @param reg - The Reg to append.
173 static void translateRegister(MCInst &mcInst, Reg reg) {
174 #define ENTRY(x) X86::x,
175  uint8_t llvmRegnums[] = {
176  ALL_REGS
177  0
178  };
179 #undef ENTRY
180 
181  uint8_t llvmRegnum = llvmRegnums[reg];
182  mcInst.addOperand(MCOperand::createReg(llvmRegnum));
183 }
184 
185 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
186 /// immediate Value in the MCInst.
187 ///
188 /// @param Value - The immediate Value, has had any PC adjustment made by
189 /// the caller.
190 /// @param isBranch - If the instruction is a branch instruction
191 /// @param Address - The starting address of the instruction
192 /// @param Offset - The byte offset to this immediate in the instruction
193 /// @param Width - The byte width of this immediate in the instruction
194 ///
195 /// If the getOpInfo() function was set when setupForSymbolicDisassembly() was
196 /// called then that function is called to get any symbolic information for the
197 /// immediate in the instruction using the Address, Offset and Width. If that
198 /// returns non-zero then the symbolic information it returns is used to create
199 /// an MCExpr and that is added as an operand to the MCInst. If getOpInfo()
200 /// returns zero and isBranch is true then a symbol look up for immediate Value
201 /// is done and if a symbol is found an MCExpr is created with that, else
202 /// an MCExpr with the immediate Value is created. This function returns true
203 /// if it adds an operand to the MCInst and false otherwise.
204 static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,
205  uint64_t Address, uint64_t Offset,
206  uint64_t Width, MCInst &MI,
207  const MCDisassembler *Dis) {
208  return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch,
209  Offset, Width);
210 }
211 
212 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
213 /// referenced by a load instruction with the base register that is the rip.
214 /// These can often be addresses in a literal pool. The Address of the
215 /// instruction and its immediate Value are used to determine the address
216 /// being referenced in the literal pool entry. The SymbolLookUp call back will
217 /// return a pointer to a literal 'C' string if the referenced address is an
218 /// address into a section with 'C' string literals.
219 static void tryAddingPcLoadReferenceComment(uint64_t Address, uint64_t Value,
220  const void *Decoder) {
221  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
222  Dis->tryAddingPcLoadReferenceComment(Value, Address);
223 }
224 
225 static const uint8_t segmentRegnums[SEG_OVERRIDE_max] = {
226  0, // SEG_OVERRIDE_NONE
227  X86::CS,
228  X86::SS,
229  X86::DS,
230  X86::ES,
231  X86::FS,
232  X86::GS
233 };
234 
235 /// translateSrcIndex - Appends a source index operand to an MCInst.
236 ///
237 /// @param mcInst - The MCInst to append to.
238 /// @param insn - The internal instruction.
239 static bool translateSrcIndex(MCInst &mcInst, InternalInstruction &insn) {
240  unsigned baseRegNo;
241 
242  if (insn.mode == MODE_64BIT)
243  baseRegNo = insn.prefixPresent[0x67] ? X86::ESI : X86::RSI;
244  else if (insn.mode == MODE_32BIT)
245  baseRegNo = insn.prefixPresent[0x67] ? X86::SI : X86::ESI;
246  else {
247  assert(insn.mode == MODE_16BIT);
248  baseRegNo = insn.prefixPresent[0x67] ? X86::ESI : X86::SI;
249  }
250  MCOperand baseReg = MCOperand::createReg(baseRegNo);
251  mcInst.addOperand(baseReg);
252 
253  MCOperand segmentReg;
255  mcInst.addOperand(segmentReg);
256  return false;
257 }
258 
259 /// translateDstIndex - Appends a destination index operand to an MCInst.
260 ///
261 /// @param mcInst - The MCInst to append to.
262 /// @param insn - The internal instruction.
263 
264 static bool translateDstIndex(MCInst &mcInst, InternalInstruction &insn) {
265  unsigned baseRegNo;
266 
267  if (insn.mode == MODE_64BIT)
268  baseRegNo = insn.prefixPresent[0x67] ? X86::EDI : X86::RDI;
269  else if (insn.mode == MODE_32BIT)
270  baseRegNo = insn.prefixPresent[0x67] ? X86::DI : X86::EDI;
271  else {
272  assert(insn.mode == MODE_16BIT);
273  baseRegNo = insn.prefixPresent[0x67] ? X86::EDI : X86::DI;
274  }
275  MCOperand baseReg = MCOperand::createReg(baseRegNo);
276  mcInst.addOperand(baseReg);
277  return false;
278 }
279 
280 /// translateImmediate - Appends an immediate operand to an MCInst.
281 ///
282 /// @param mcInst - The MCInst to append to.
283 /// @param immediate - The immediate value to append.
284 /// @param operand - The operand, as stored in the descriptor table.
285 /// @param insn - The internal instruction.
286 static void translateImmediate(MCInst &mcInst, uint64_t immediate,
287  const OperandSpecifier &operand,
288  InternalInstruction &insn,
289  const MCDisassembler *Dis) {
290  // Sign-extend the immediate if necessary.
291 
292  OperandType type = (OperandType)operand.type;
293 
294  bool isBranch = false;
295  uint64_t pcrel = 0;
296  if (type == TYPE_RELv) {
297  isBranch = true;
298  pcrel = insn.startLocation +
299  insn.immediateOffset + insn.immediateSize;
300  switch (insn.displacementSize) {
301  default:
302  break;
303  case 1:
304  if(immediate & 0x80)
305  immediate |= ~(0xffull);
306  break;
307  case 2:
308  if(immediate & 0x8000)
309  immediate |= ~(0xffffull);
310  break;
311  case 4:
312  if(immediate & 0x80000000)
313  immediate |= ~(0xffffffffull);
314  break;
315  case 8:
316  break;
317  }
318  }
319  // By default sign-extend all X86 immediates based on their encoding.
320  else if (type == TYPE_IMM8 || type == TYPE_IMM16 || type == TYPE_IMM32 ||
321  type == TYPE_IMM64 || type == TYPE_IMMv) {
322  switch (operand.encoding) {
323  default:
324  break;
325  case ENCODING_IB:
326  if(immediate & 0x80)
327  immediate |= ~(0xffull);
328  break;
329  case ENCODING_IW:
330  if(immediate & 0x8000)
331  immediate |= ~(0xffffull);
332  break;
333  case ENCODING_ID:
334  if(immediate & 0x80000000)
335  immediate |= ~(0xffffffffull);
336  break;
337  case ENCODING_IO:
338  break;
339  }
340  } else if (type == TYPE_IMM3) {
341  // Check for immediates that printSSECC can't handle.
342  if (immediate >= 8) {
343  unsigned NewOpc;
344  switch (mcInst.getOpcode()) {
345  default: llvm_unreachable("unexpected opcode");
346  case X86::CMPPDrmi: NewOpc = X86::CMPPDrmi_alt; break;
347  case X86::CMPPDrri: NewOpc = X86::CMPPDrri_alt; break;
348  case X86::CMPPSrmi: NewOpc = X86::CMPPSrmi_alt; break;
349  case X86::CMPPSrri: NewOpc = X86::CMPPSrri_alt; break;
350  case X86::CMPSDrm: NewOpc = X86::CMPSDrm_alt; break;
351  case X86::CMPSDrr: NewOpc = X86::CMPSDrr_alt; break;
352  case X86::CMPSSrm: NewOpc = X86::CMPSSrm_alt; break;
353  case X86::CMPSSrr: NewOpc = X86::CMPSSrr_alt; break;
354  case X86::VPCOMBri: NewOpc = X86::VPCOMBri_alt; break;
355  case X86::VPCOMBmi: NewOpc = X86::VPCOMBmi_alt; break;
356  case X86::VPCOMWri: NewOpc = X86::VPCOMWri_alt; break;
357  case X86::VPCOMWmi: NewOpc = X86::VPCOMWmi_alt; break;
358  case X86::VPCOMDri: NewOpc = X86::VPCOMDri_alt; break;
359  case X86::VPCOMDmi: NewOpc = X86::VPCOMDmi_alt; break;
360  case X86::VPCOMQri: NewOpc = X86::VPCOMQri_alt; break;
361  case X86::VPCOMQmi: NewOpc = X86::VPCOMQmi_alt; break;
362  case X86::VPCOMUBri: NewOpc = X86::VPCOMUBri_alt; break;
363  case X86::VPCOMUBmi: NewOpc = X86::VPCOMUBmi_alt; break;
364  case X86::VPCOMUWri: NewOpc = X86::VPCOMUWri_alt; break;
365  case X86::VPCOMUWmi: NewOpc = X86::VPCOMUWmi_alt; break;
366  case X86::VPCOMUDri: NewOpc = X86::VPCOMUDri_alt; break;
367  case X86::VPCOMUDmi: NewOpc = X86::VPCOMUDmi_alt; break;
368  case X86::VPCOMUQri: NewOpc = X86::VPCOMUQri_alt; break;
369  case X86::VPCOMUQmi: NewOpc = X86::VPCOMUQmi_alt; break;
370  }
371  // Switch opcode to the one that doesn't get special printing.
372  mcInst.setOpcode(NewOpc);
373  }
374  } else if (type == TYPE_IMM5) {
375  // Check for immediates that printAVXCC can't handle.
376  if (immediate >= 32) {
377  unsigned NewOpc;
378  switch (mcInst.getOpcode()) {
379  default: llvm_unreachable("unexpected opcode");
380  case X86::VCMPPDrmi: NewOpc = X86::VCMPPDrmi_alt; break;
381  case X86::VCMPPDrri: NewOpc = X86::VCMPPDrri_alt; break;
382  case X86::VCMPPSrmi: NewOpc = X86::VCMPPSrmi_alt; break;
383  case X86::VCMPPSrri: NewOpc = X86::VCMPPSrri_alt; break;
384  case X86::VCMPSDrm: NewOpc = X86::VCMPSDrm_alt; break;
385  case X86::VCMPSDrr: NewOpc = X86::VCMPSDrr_alt; break;
386  case X86::VCMPSSrm: NewOpc = X86::VCMPSSrm_alt; break;
387  case X86::VCMPSSrr: NewOpc = X86::VCMPSSrr_alt; break;
388  case X86::VCMPPDYrmi: NewOpc = X86::VCMPPDYrmi_alt; break;
389  case X86::VCMPPDYrri: NewOpc = X86::VCMPPDYrri_alt; break;
390  case X86::VCMPPSYrmi: NewOpc = X86::VCMPPSYrmi_alt; break;
391  case X86::VCMPPSYrri: NewOpc = X86::VCMPPSYrri_alt; break;
392  case X86::VCMPPDZrmi: NewOpc = X86::VCMPPDZrmi_alt; break;
393  case X86::VCMPPDZrri: NewOpc = X86::VCMPPDZrri_alt; break;
394  case X86::VCMPPDZrrib: NewOpc = X86::VCMPPDZrrib_alt; break;
395  case X86::VCMPPSZrmi: NewOpc = X86::VCMPPSZrmi_alt; break;
396  case X86::VCMPPSZrri: NewOpc = X86::VCMPPSZrri_alt; break;
397  case X86::VCMPPSZrrib: NewOpc = X86::VCMPPSZrrib_alt; break;
398  case X86::VCMPSDZrm: NewOpc = X86::VCMPSDZrmi_alt; break;
399  case X86::VCMPSDZrr: NewOpc = X86::VCMPSDZrri_alt; break;
400  case X86::VCMPSSZrm: NewOpc = X86::VCMPSSZrmi_alt; break;
401  case X86::VCMPSSZrr: NewOpc = X86::VCMPSSZrri_alt; break;
402  }
403  // Switch opcode to the one that doesn't get special printing.
404  mcInst.setOpcode(NewOpc);
405  }
406  } else if (type == TYPE_AVX512ICC) {
407  if (immediate >= 8 || ((immediate & 0x3) == 3)) {
408  unsigned NewOpc;
409  switch (mcInst.getOpcode()) {
410  default: llvm_unreachable("unexpected opcode");
411  case X86::VPCMPBZ128rmi: NewOpc = X86::VPCMPBZ128rmi_alt; break;
412  case X86::VPCMPBZ128rmik: NewOpc = X86::VPCMPBZ128rmik_alt; break;
413  case X86::VPCMPBZ128rri: NewOpc = X86::VPCMPBZ128rri_alt; break;
414  case X86::VPCMPBZ128rrik: NewOpc = X86::VPCMPBZ128rrik_alt; break;
415  case X86::VPCMPBZ256rmi: NewOpc = X86::VPCMPBZ256rmi_alt; break;
416  case X86::VPCMPBZ256rmik: NewOpc = X86::VPCMPBZ256rmik_alt; break;
417  case X86::VPCMPBZ256rri: NewOpc = X86::VPCMPBZ256rri_alt; break;
418  case X86::VPCMPBZ256rrik: NewOpc = X86::VPCMPBZ256rrik_alt; break;
419  case X86::VPCMPBZrmi: NewOpc = X86::VPCMPBZrmi_alt; break;
420  case X86::VPCMPBZrmik: NewOpc = X86::VPCMPBZrmik_alt; break;
421  case X86::VPCMPBZrri: NewOpc = X86::VPCMPBZrri_alt; break;
422  case X86::VPCMPBZrrik: NewOpc = X86::VPCMPBZrrik_alt; break;
423  case X86::VPCMPDZ128rmi: NewOpc = X86::VPCMPDZ128rmi_alt; break;
424  case X86::VPCMPDZ128rmib: NewOpc = X86::VPCMPDZ128rmib_alt; break;
425  case X86::VPCMPDZ128rmibk: NewOpc = X86::VPCMPDZ128rmibk_alt; break;
426  case X86::VPCMPDZ128rmik: NewOpc = X86::VPCMPDZ128rmik_alt; break;
427  case X86::VPCMPDZ128rri: NewOpc = X86::VPCMPDZ128rri_alt; break;
428  case X86::VPCMPDZ128rrik: NewOpc = X86::VPCMPDZ128rrik_alt; break;
429  case X86::VPCMPDZ256rmi: NewOpc = X86::VPCMPDZ256rmi_alt; break;
430  case X86::VPCMPDZ256rmib: NewOpc = X86::VPCMPDZ256rmib_alt; break;
431  case X86::VPCMPDZ256rmibk: NewOpc = X86::VPCMPDZ256rmibk_alt; break;
432  case X86::VPCMPDZ256rmik: NewOpc = X86::VPCMPDZ256rmik_alt; break;
433  case X86::VPCMPDZ256rri: NewOpc = X86::VPCMPDZ256rri_alt; break;
434  case X86::VPCMPDZ256rrik: NewOpc = X86::VPCMPDZ256rrik_alt; break;
435  case X86::VPCMPDZrmi: NewOpc = X86::VPCMPDZrmi_alt; break;
436  case X86::VPCMPDZrmib: NewOpc = X86::VPCMPDZrmib_alt; break;
437  case X86::VPCMPDZrmibk: NewOpc = X86::VPCMPDZrmibk_alt; break;
438  case X86::VPCMPDZrmik: NewOpc = X86::VPCMPDZrmik_alt; break;
439  case X86::VPCMPDZrri: NewOpc = X86::VPCMPDZrri_alt; break;
440  case X86::VPCMPDZrrik: NewOpc = X86::VPCMPDZrrik_alt; break;
441  case X86::VPCMPQZ128rmi: NewOpc = X86::VPCMPQZ128rmi_alt; break;
442  case X86::VPCMPQZ128rmib: NewOpc = X86::VPCMPQZ128rmib_alt; break;
443  case X86::VPCMPQZ128rmibk: NewOpc = X86::VPCMPQZ128rmibk_alt; break;
444  case X86::VPCMPQZ128rmik: NewOpc = X86::VPCMPQZ128rmik_alt; break;
445  case X86::VPCMPQZ128rri: NewOpc = X86::VPCMPQZ128rri_alt; break;
446  case X86::VPCMPQZ128rrik: NewOpc = X86::VPCMPQZ128rrik_alt; break;
447  case X86::VPCMPQZ256rmi: NewOpc = X86::VPCMPQZ256rmi_alt; break;
448  case X86::VPCMPQZ256rmib: NewOpc = X86::VPCMPQZ256rmib_alt; break;
449  case X86::VPCMPQZ256rmibk: NewOpc = X86::VPCMPQZ256rmibk_alt; break;
450  case X86::VPCMPQZ256rmik: NewOpc = X86::VPCMPQZ256rmik_alt; break;
451  case X86::VPCMPQZ256rri: NewOpc = X86::VPCMPQZ256rri_alt; break;
452  case X86::VPCMPQZ256rrik: NewOpc = X86::VPCMPQZ256rrik_alt; break;
453  case X86::VPCMPQZrmi: NewOpc = X86::VPCMPQZrmi_alt; break;
454  case X86::VPCMPQZrmib: NewOpc = X86::VPCMPQZrmib_alt; break;
455  case X86::VPCMPQZrmibk: NewOpc = X86::VPCMPQZrmibk_alt; break;
456  case X86::VPCMPQZrmik: NewOpc = X86::VPCMPQZrmik_alt; break;
457  case X86::VPCMPQZrri: NewOpc = X86::VPCMPQZrri_alt; break;
458  case X86::VPCMPQZrrik: NewOpc = X86::VPCMPQZrrik_alt; break;
459  case X86::VPCMPUBZ128rmi: NewOpc = X86::VPCMPUBZ128rmi_alt; break;
460  case X86::VPCMPUBZ128rmik: NewOpc = X86::VPCMPUBZ128rmik_alt; break;
461  case X86::VPCMPUBZ128rri: NewOpc = X86::VPCMPUBZ128rri_alt; break;
462  case X86::VPCMPUBZ128rrik: NewOpc = X86::VPCMPUBZ128rrik_alt; break;
463  case X86::VPCMPUBZ256rmi: NewOpc = X86::VPCMPUBZ256rmi_alt; break;
464  case X86::VPCMPUBZ256rmik: NewOpc = X86::VPCMPUBZ256rmik_alt; break;
465  case X86::VPCMPUBZ256rri: NewOpc = X86::VPCMPUBZ256rri_alt; break;
466  case X86::VPCMPUBZ256rrik: NewOpc = X86::VPCMPUBZ256rrik_alt; break;
467  case X86::VPCMPUBZrmi: NewOpc = X86::VPCMPUBZrmi_alt; break;
468  case X86::VPCMPUBZrmik: NewOpc = X86::VPCMPUBZrmik_alt; break;
469  case X86::VPCMPUBZrri: NewOpc = X86::VPCMPUBZrri_alt; break;
470  case X86::VPCMPUBZrrik: NewOpc = X86::VPCMPUBZrrik_alt; break;
471  case X86::VPCMPUDZ128rmi: NewOpc = X86::VPCMPUDZ128rmi_alt; break;
472  case X86::VPCMPUDZ128rmib: NewOpc = X86::VPCMPUDZ128rmib_alt; break;
473  case X86::VPCMPUDZ128rmibk: NewOpc = X86::VPCMPUDZ128rmibk_alt; break;
474  case X86::VPCMPUDZ128rmik: NewOpc = X86::VPCMPUDZ128rmik_alt; break;
475  case X86::VPCMPUDZ128rri: NewOpc = X86::VPCMPUDZ128rri_alt; break;
476  case X86::VPCMPUDZ128rrik: NewOpc = X86::VPCMPUDZ128rrik_alt; break;
477  case X86::VPCMPUDZ256rmi: NewOpc = X86::VPCMPUDZ256rmi_alt; break;
478  case X86::VPCMPUDZ256rmib: NewOpc = X86::VPCMPUDZ256rmib_alt; break;
479  case X86::VPCMPUDZ256rmibk: NewOpc = X86::VPCMPUDZ256rmibk_alt; break;
480  case X86::VPCMPUDZ256rmik: NewOpc = X86::VPCMPUDZ256rmik_alt; break;
481  case X86::VPCMPUDZ256rri: NewOpc = X86::VPCMPUDZ256rri_alt; break;
482  case X86::VPCMPUDZ256rrik: NewOpc = X86::VPCMPUDZ256rrik_alt; break;
483  case X86::VPCMPUDZrmi: NewOpc = X86::VPCMPUDZrmi_alt; break;
484  case X86::VPCMPUDZrmib: NewOpc = X86::VPCMPUDZrmib_alt; break;
485  case X86::VPCMPUDZrmibk: NewOpc = X86::VPCMPUDZrmibk_alt; break;
486  case X86::VPCMPUDZrmik: NewOpc = X86::VPCMPUDZrmik_alt; break;
487  case X86::VPCMPUDZrri: NewOpc = X86::VPCMPUDZrri_alt; break;
488  case X86::VPCMPUDZrrik: NewOpc = X86::VPCMPUDZrrik_alt; break;
489  case X86::VPCMPUQZ128rmi: NewOpc = X86::VPCMPUQZ128rmi_alt; break;
490  case X86::VPCMPUQZ128rmib: NewOpc = X86::VPCMPUQZ128rmib_alt; break;
491  case X86::VPCMPUQZ128rmibk: NewOpc = X86::VPCMPUQZ128rmibk_alt; break;
492  case X86::VPCMPUQZ128rmik: NewOpc = X86::VPCMPUQZ128rmik_alt; break;
493  case X86::VPCMPUQZ128rri: NewOpc = X86::VPCMPUQZ128rri_alt; break;
494  case X86::VPCMPUQZ128rrik: NewOpc = X86::VPCMPUQZ128rrik_alt; break;
495  case X86::VPCMPUQZ256rmi: NewOpc = X86::VPCMPUQZ256rmi_alt; break;
496  case X86::VPCMPUQZ256rmib: NewOpc = X86::VPCMPUQZ256rmib_alt; break;
497  case X86::VPCMPUQZ256rmibk: NewOpc = X86::VPCMPUQZ256rmibk_alt; break;
498  case X86::VPCMPUQZ256rmik: NewOpc = X86::VPCMPUQZ256rmik_alt; break;
499  case X86::VPCMPUQZ256rri: NewOpc = X86::VPCMPUQZ256rri_alt; break;
500  case X86::VPCMPUQZ256rrik: NewOpc = X86::VPCMPUQZ256rrik_alt; break;
501  case X86::VPCMPUQZrmi: NewOpc = X86::VPCMPUQZrmi_alt; break;
502  case X86::VPCMPUQZrmib: NewOpc = X86::VPCMPUQZrmib_alt; break;
503  case X86::VPCMPUQZrmibk: NewOpc = X86::VPCMPUQZrmibk_alt; break;
504  case X86::VPCMPUQZrmik: NewOpc = X86::VPCMPUQZrmik_alt; break;
505  case X86::VPCMPUQZrri: NewOpc = X86::VPCMPUQZrri_alt; break;
506  case X86::VPCMPUQZrrik: NewOpc = X86::VPCMPUQZrrik_alt; break;
507  case X86::VPCMPUWZ128rmi: NewOpc = X86::VPCMPUWZ128rmi_alt; break;
508  case X86::VPCMPUWZ128rmik: NewOpc = X86::VPCMPUWZ128rmik_alt; break;
509  case X86::VPCMPUWZ128rri: NewOpc = X86::VPCMPUWZ128rri_alt; break;
510  case X86::VPCMPUWZ128rrik: NewOpc = X86::VPCMPUWZ128rrik_alt; break;
511  case X86::VPCMPUWZ256rmi: NewOpc = X86::VPCMPUWZ256rmi_alt; break;
512  case X86::VPCMPUWZ256rmik: NewOpc = X86::VPCMPUWZ256rmik_alt; break;
513  case X86::VPCMPUWZ256rri: NewOpc = X86::VPCMPUWZ256rri_alt; break;
514  case X86::VPCMPUWZ256rrik: NewOpc = X86::VPCMPUWZ256rrik_alt; break;
515  case X86::VPCMPUWZrmi: NewOpc = X86::VPCMPUWZrmi_alt; break;
516  case X86::VPCMPUWZrmik: NewOpc = X86::VPCMPUWZrmik_alt; break;
517  case X86::VPCMPUWZrri: NewOpc = X86::VPCMPUWZrri_alt; break;
518  case X86::VPCMPUWZrrik: NewOpc = X86::VPCMPUWZrrik_alt; break;
519  case X86::VPCMPWZ128rmi: NewOpc = X86::VPCMPWZ128rmi_alt; break;
520  case X86::VPCMPWZ128rmik: NewOpc = X86::VPCMPWZ128rmik_alt; break;
521  case X86::VPCMPWZ128rri: NewOpc = X86::VPCMPWZ128rri_alt; break;
522  case X86::VPCMPWZ128rrik: NewOpc = X86::VPCMPWZ128rrik_alt; break;
523  case X86::VPCMPWZ256rmi: NewOpc = X86::VPCMPWZ256rmi_alt; break;
524  case X86::VPCMPWZ256rmik: NewOpc = X86::VPCMPWZ256rmik_alt; break;
525  case X86::VPCMPWZ256rri: NewOpc = X86::VPCMPWZ256rri_alt; break;
526  case X86::VPCMPWZ256rrik: NewOpc = X86::VPCMPWZ256rrik_alt; break;
527  case X86::VPCMPWZrmi: NewOpc = X86::VPCMPWZrmi_alt; break;
528  case X86::VPCMPWZrmik: NewOpc = X86::VPCMPWZrmik_alt; break;
529  case X86::VPCMPWZrri: NewOpc = X86::VPCMPWZrri_alt; break;
530  case X86::VPCMPWZrrik: NewOpc = X86::VPCMPWZrrik_alt; break;
531  }
532  // Switch opcode to the one that doesn't get special printing.
533  mcInst.setOpcode(NewOpc);
534  }
535  }
536 
537  switch (type) {
538  case TYPE_XMM32:
539  case TYPE_XMM64:
540  case TYPE_XMM128:
541  mcInst.addOperand(MCOperand::createReg(X86::XMM0 + (immediate >> 4)));
542  return;
543  case TYPE_XMM256:
544  mcInst.addOperand(MCOperand::createReg(X86::YMM0 + (immediate >> 4)));
545  return;
546  case TYPE_XMM512:
547  mcInst.addOperand(MCOperand::createReg(X86::ZMM0 + (immediate >> 4)));
548  return;
549  case TYPE_BNDR:
550  mcInst.addOperand(MCOperand::createReg(X86::BND0 + (immediate >> 4)));
551  case TYPE_REL8:
552  isBranch = true;
553  pcrel = insn.startLocation + insn.immediateOffset + insn.immediateSize;
554  if (immediate & 0x80)
555  immediate |= ~(0xffull);
556  break;
557  case TYPE_REL16:
558  isBranch = true;
559  pcrel = insn.startLocation + insn.immediateOffset + insn.immediateSize;
560  if (immediate & 0x8000)
561  immediate |= ~(0xffffull);
562  break;
563  case TYPE_REL32:
564  case TYPE_REL64:
565  isBranch = true;
566  pcrel = insn.startLocation + insn.immediateOffset + insn.immediateSize;
567  if(immediate & 0x80000000)
568  immediate |= ~(0xffffffffull);
569  break;
570  default:
571  // operand is 64 bits wide. Do nothing.
572  break;
573  }
574 
575  if(!tryAddingSymbolicOperand(immediate + pcrel, isBranch, insn.startLocation,
576  insn.immediateOffset, insn.immediateSize,
577  mcInst, Dis))
578  mcInst.addOperand(MCOperand::createImm(immediate));
579 
580  if (type == TYPE_MOFFS8 || type == TYPE_MOFFS16 ||
581  type == TYPE_MOFFS32 || type == TYPE_MOFFS64) {
582  MCOperand segmentReg;
584  mcInst.addOperand(segmentReg);
585  }
586 }
587 
588 /// translateRMRegister - Translates a register stored in the R/M field of the
589 /// ModR/M byte to its LLVM equivalent and appends it to an MCInst.
590 /// @param mcInst - The MCInst to append to.
591 /// @param insn - The internal instruction to extract the R/M field
592 /// from.
593 /// @return - 0 on success; -1 otherwise
594 static bool translateRMRegister(MCInst &mcInst,
595  InternalInstruction &insn) {
596  if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) {
597  debug("A R/M register operand may not have a SIB byte");
598  return true;
599  }
600 
601  switch (insn.eaBase) {
602  default:
603  debug("Unexpected EA base register");
604  return true;
605  case EA_BASE_NONE:
606  debug("EA_BASE_NONE for ModR/M base");
607  return true;
608 #define ENTRY(x) case EA_BASE_##x:
610 #undef ENTRY
611  debug("A R/M register operand may not have a base; "
612  "the operand must be a register.");
613  return true;
614 #define ENTRY(x) \
615  case EA_REG_##x: \
616  mcInst.addOperand(MCOperand::createReg(X86::x)); break;
617  ALL_REGS
618 #undef ENTRY
619  }
620 
621  return false;
622 }
623 
624 /// translateRMMemory - Translates a memory operand stored in the Mod and R/M
625 /// fields of an internal instruction (and possibly its SIB byte) to a memory
626 /// operand in LLVM's format, and appends it to an MCInst.
627 ///
628 /// @param mcInst - The MCInst to append to.
629 /// @param insn - The instruction to extract Mod, R/M, and SIB fields
630 /// from.
631 /// @return - 0 on success; nonzero otherwise
632 static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn,
633  const MCDisassembler *Dis) {
634  // Addresses in an MCInst are represented as five operands:
635  // 1. basereg (register) The R/M base, or (if there is a SIB) the
636  // SIB base
637  // 2. scaleamount (immediate) 1, or (if there is a SIB) the specified
638  // scale amount
639  // 3. indexreg (register) x86_registerNONE, or (if there is a SIB)
640  // the index (which is multiplied by the
641  // scale amount)
642  // 4. displacement (immediate) 0, or the displacement if there is one
643  // 5. segmentreg (register) x86_registerNONE for now, but could be set
644  // if we have segment overrides
645 
646  MCOperand baseReg;
647  MCOperand scaleAmount;
648  MCOperand indexReg;
649  MCOperand displacement;
650  MCOperand segmentReg;
651  uint64_t pcrel = 0;
652 
653  if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) {
654  if (insn.sibBase != SIB_BASE_NONE) {
655  switch (insn.sibBase) {
656  default:
657  debug("Unexpected sibBase");
658  return true;
659 #define ENTRY(x) \
660  case SIB_BASE_##x: \
661  baseReg = MCOperand::createReg(X86::x); break;
663 #undef ENTRY
664  }
665  } else {
666  baseReg = MCOperand::createReg(0);
667  }
668 
669  // Check whether we are handling VSIB addressing mode for GATHER.
670  // If sibIndex was set to SIB_INDEX_NONE, index offset is 4 and
671  // we should use SIB_INDEX_XMM4|YMM4 for VSIB.
672  // I don't see a way to get the correct IndexReg in readSIB:
673  // We can tell whether it is VSIB or SIB after instruction ID is decoded,
674  // but instruction ID may not be decoded yet when calling readSIB.
675  uint32_t Opcode = mcInst.getOpcode();
676  bool IndexIs128 = (Opcode == X86::VGATHERDPDrm ||
677  Opcode == X86::VGATHERDPDYrm ||
678  Opcode == X86::VGATHERQPDrm ||
679  Opcode == X86::VGATHERDPSrm ||
680  Opcode == X86::VGATHERQPSrm ||
681  Opcode == X86::VPGATHERDQrm ||
682  Opcode == X86::VPGATHERDQYrm ||
683  Opcode == X86::VPGATHERQQrm ||
684  Opcode == X86::VPGATHERDDrm ||
685  Opcode == X86::VPGATHERQDrm);
686  bool IndexIs256 = (Opcode == X86::VGATHERQPDYrm ||
687  Opcode == X86::VGATHERDPSYrm ||
688  Opcode == X86::VGATHERQPSYrm ||
689  Opcode == X86::VGATHERDPDZrm ||
690  Opcode == X86::VPGATHERDQZrm ||
691  Opcode == X86::VPGATHERQQYrm ||
692  Opcode == X86::VPGATHERDDYrm ||
693  Opcode == X86::VPGATHERQDYrm);
694  bool IndexIs512 = (Opcode == X86::VGATHERQPDZrm ||
695  Opcode == X86::VGATHERDPSZrm ||
696  Opcode == X86::VGATHERQPSZrm ||
697  Opcode == X86::VPGATHERQQZrm ||
698  Opcode == X86::VPGATHERDDZrm ||
699  Opcode == X86::VPGATHERQDZrm);
700  if (IndexIs128 || IndexIs256 || IndexIs512) {
701  unsigned IndexOffset = insn.sibIndex -
702  (insn.addressSize == 8 ? SIB_INDEX_RAX:SIB_INDEX_EAX);
703  SIBIndex IndexBase = IndexIs512 ? SIB_INDEX_ZMM0 :
704  IndexIs256 ? SIB_INDEX_YMM0 : SIB_INDEX_XMM0;
705  insn.sibIndex = (SIBIndex)(IndexBase +
706  (insn.sibIndex == SIB_INDEX_NONE ? 4 : IndexOffset));
707  }
708 
709  if (insn.sibIndex != SIB_INDEX_NONE) {
710  switch (insn.sibIndex) {
711  default:
712  debug("Unexpected sibIndex");
713  return true;
714 #define ENTRY(x) \
715  case SIB_INDEX_##x: \
716  indexReg = MCOperand::createReg(X86::x); break;
719  REGS_XMM
720  REGS_YMM
721  REGS_ZMM
722 #undef ENTRY
723  }
724  } else {
725  indexReg = MCOperand::createReg(0);
726  }
727 
728  scaleAmount = MCOperand::createImm(insn.sibScale);
729  } else {
730  switch (insn.eaBase) {
731  case EA_BASE_NONE:
732  if (insn.eaDisplacement == EA_DISP_NONE) {
733  debug("EA_BASE_NONE and EA_DISP_NONE for ModR/M base");
734  return true;
735  }
736  if (insn.mode == MODE_64BIT){
737  pcrel = insn.startLocation +
740  insn.displacementOffset,
741  insn.displacement + pcrel, Dis);
742  baseReg = MCOperand::createReg(X86::RIP); // Section 2.2.1.6
743  }
744  else
745  baseReg = MCOperand::createReg(0);
746 
747  indexReg = MCOperand::createReg(0);
748  break;
749  case EA_BASE_BX_SI:
750  baseReg = MCOperand::createReg(X86::BX);
751  indexReg = MCOperand::createReg(X86::SI);
752  break;
753  case EA_BASE_BX_DI:
754  baseReg = MCOperand::createReg(X86::BX);
755  indexReg = MCOperand::createReg(X86::DI);
756  break;
757  case EA_BASE_BP_SI:
758  baseReg = MCOperand::createReg(X86::BP);
759  indexReg = MCOperand::createReg(X86::SI);
760  break;
761  case EA_BASE_BP_DI:
762  baseReg = MCOperand::createReg(X86::BP);
763  indexReg = MCOperand::createReg(X86::DI);
764  break;
765  default:
766  indexReg = MCOperand::createReg(0);
767  switch (insn.eaBase) {
768  default:
769  debug("Unexpected eaBase");
770  return true;
771  // Here, we will use the fill-ins defined above. However,
772  // BX_SI, BX_DI, BP_SI, and BP_DI are all handled above and
773  // sib and sib64 were handled in the top-level if, so they're only
774  // placeholders to keep the compiler happy.
775 #define ENTRY(x) \
776  case EA_BASE_##x: \
777  baseReg = MCOperand::createReg(X86::x); break;
779 #undef ENTRY
780 #define ENTRY(x) case EA_REG_##x:
781  ALL_REGS
782 #undef ENTRY
783  debug("A R/M memory operand may not be a register; "
784  "the base field must be a base.");
785  return true;
786  }
787  }
788 
789  scaleAmount = MCOperand::createImm(1);
790  }
791 
792  displacement = MCOperand::createImm(insn.displacement);
793 
795 
796  mcInst.addOperand(baseReg);
797  mcInst.addOperand(scaleAmount);
798  mcInst.addOperand(indexReg);
799  if(!tryAddingSymbolicOperand(insn.displacement + pcrel, false,
801  insn.displacementSize, mcInst, Dis))
802  mcInst.addOperand(displacement);
803  mcInst.addOperand(segmentReg);
804  return false;
805 }
806 
807 /// translateRM - Translates an operand stored in the R/M (and possibly SIB)
808 /// byte of an instruction to LLVM form, and appends it to an MCInst.
809 ///
810 /// @param mcInst - The MCInst to append to.
811 /// @param operand - The operand, as stored in the descriptor table.
812 /// @param insn - The instruction to extract Mod, R/M, and SIB fields
813 /// from.
814 /// @return - 0 on success; nonzero otherwise
815 static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand,
816  InternalInstruction &insn, const MCDisassembler *Dis) {
817  switch (operand.type) {
818  default:
819  debug("Unexpected type for a R/M operand");
820  return true;
821  case TYPE_R8:
822  case TYPE_R16:
823  case TYPE_R32:
824  case TYPE_R64:
825  case TYPE_Rv:
826  case TYPE_MM64:
827  case TYPE_XMM:
828  case TYPE_XMM32:
829  case TYPE_XMM64:
830  case TYPE_XMM128:
831  case TYPE_XMM256:
832  case TYPE_XMM512:
833  case TYPE_VK1:
834  case TYPE_VK8:
835  case TYPE_VK16:
836  case TYPE_DEBUGREG:
837  case TYPE_CONTROLREG:
838  case TYPE_BNDR:
839  return translateRMRegister(mcInst, insn);
840  case TYPE_M:
841  case TYPE_M8:
842  case TYPE_M16:
843  case TYPE_M32:
844  case TYPE_M64:
845  case TYPE_M128:
846  case TYPE_M256:
847  case TYPE_M512:
848  case TYPE_Mv:
849  case TYPE_M32FP:
850  case TYPE_M64FP:
851  case TYPE_M80FP:
852  case TYPE_M1616:
853  case TYPE_M1632:
854  case TYPE_M1664:
855  case TYPE_LEA:
856  return translateRMMemory(mcInst, insn, Dis);
857  }
858 }
859 
860 /// translateFPRegister - Translates a stack position on the FPU stack to its
861 /// LLVM form, and appends it to an MCInst.
862 ///
863 /// @param mcInst - The MCInst to append to.
864 /// @param stackPos - The stack position to translate.
865 static void translateFPRegister(MCInst &mcInst,
866  uint8_t stackPos) {
867  mcInst.addOperand(MCOperand::createReg(X86::ST0 + stackPos));
868 }
869 
870 /// translateMaskRegister - Translates a 3-bit mask register number to
871 /// LLVM form, and appends it to an MCInst.
872 ///
873 /// @param mcInst - The MCInst to append to.
874 /// @param maskRegNum - Number of mask register from 0 to 7.
875 /// @return - false on success; true otherwise.
876 static bool translateMaskRegister(MCInst &mcInst,
877  uint8_t maskRegNum) {
878  if (maskRegNum >= 8) {
879  debug("Invalid mask register number");
880  return true;
881  }
882 
883  mcInst.addOperand(MCOperand::createReg(X86::K0 + maskRegNum));
884  return false;
885 }
886 
887 /// translateOperand - Translates an operand stored in an internal instruction
888 /// to LLVM's format and appends it to an MCInst.
889 ///
890 /// @param mcInst - The MCInst to append to.
891 /// @param operand - The operand, as stored in the descriptor table.
892 /// @param insn - The internal instruction.
893 /// @return - false on success; true otherwise.
894 static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand,
895  InternalInstruction &insn,
896  const MCDisassembler *Dis) {
897  switch (operand.encoding) {
898  default:
899  debug("Unhandled operand encoding during translation");
900  return true;
901  case ENCODING_REG:
902  translateRegister(mcInst, insn.reg);
903  return false;
904  case ENCODING_WRITEMASK:
905  return translateMaskRegister(mcInst, insn.writemask);
907  return translateRM(mcInst, operand, insn, Dis);
908  case ENCODING_CB:
909  case ENCODING_CW:
910  case ENCODING_CD:
911  case ENCODING_CP:
912  case ENCODING_CO:
913  case ENCODING_CT:
914  debug("Translation of code offsets isn't supported.");
915  return true;
916  case ENCODING_IB:
917  case ENCODING_IW:
918  case ENCODING_ID:
919  case ENCODING_IO:
920  case ENCODING_Iv:
921  case ENCODING_Ia:
922  translateImmediate(mcInst,
923  insn.immediates[insn.numImmediatesTranslated++],
924  operand,
925  insn,
926  Dis);
927  return false;
928  case ENCODING_SI:
929  return translateSrcIndex(mcInst, insn);
930  case ENCODING_DI:
931  return translateDstIndex(mcInst, insn);
932  case ENCODING_RB:
933  case ENCODING_RW:
934  case ENCODING_RD:
935  case ENCODING_RO:
936  case ENCODING_Rv:
937  translateRegister(mcInst, insn.opcodeRegister);
938  return false;
939  case ENCODING_FP:
940  translateFPRegister(mcInst, insn.modRM & 7);
941  return false;
942  case ENCODING_VVVV:
943  translateRegister(mcInst, insn.vvvv);
944  return false;
945  case ENCODING_DUP:
946  return translateOperand(mcInst, insn.operands[operand.type - TYPE_DUP0],
947  insn, Dis);
948  }
949 }
950 
951 /// translateInstruction - Translates an internal instruction and all its
952 /// operands to an MCInst.
953 ///
954 /// @param mcInst - The MCInst to populate with the instruction's data.
955 /// @param insn - The internal instruction.
956 /// @return - false on success; true otherwise.
957 static bool translateInstruction(MCInst &mcInst,
958  InternalInstruction &insn,
959  const MCDisassembler *Dis) {
960  if (!insn.spec) {
961  debug("Instruction has no specification");
962  return true;
963  }
964 
965  mcInst.setOpcode(insn.instructionID);
966  // If when reading the prefix bytes we determined the overlapping 0xf2 or 0xf3
967  // prefix bytes should be disassembled as xrelease and xacquire then set the
968  // opcode to those instead of the rep and repne opcodes.
969  if (insn.xAcquireRelease) {
970  if(mcInst.getOpcode() == X86::REP_PREFIX)
971  mcInst.setOpcode(X86::XRELEASE_PREFIX);
972  else if(mcInst.getOpcode() == X86::REPNE_PREFIX)
973  mcInst.setOpcode(X86::XACQUIRE_PREFIX);
974  }
975 
976  insn.numImmediatesTranslated = 0;
977 
978  for (const auto &Op : insn.operands) {
979  if (Op.encoding != ENCODING_NONE) {
980  if (translateOperand(mcInst, Op, insn, Dis)) {
981  return true;
982  }
983  }
984  }
985 
986  return false;
987 }
988 
990  const MCSubtargetInfo &STI,
991  MCContext &Ctx) {
992  std::unique_ptr<const MCInstrInfo> MII(T.createMCInstrInfo());
993  return new X86Disassembler::X86GenericDisassembler(STI, Ctx, std::move(MII));
994 }
995 
996 extern "C" void LLVMInitializeX86Disassembler() {
997  // Register the disassembler.
1002 }
X86GenericDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, std::unique_ptr< const MCInstrInfo > MII)
DecodeStatus
Ternary decode status.
Superclass for all disassemblers.
raw_ostream * CommentStream
#define ALL_REGS
static void translateImmediate(MCInst &mcInst, uint64_t immediate, const OperandSpecifier &operand, InternalInstruction &insn, const MCDisassembler *Dis)
translateImmediate - Appends an immediate operand to an MCInst.
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
MCInstrInfo * createMCInstrInfo() const
createMCInstrInfo - Create a MCInstrInfo implementation.
SIBIndex
All possible values of the SIB index field.
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:111
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
Target TheX86_64Target
Reg
All possible values of the reg field in the ModR/M byte.
Number of individual test Apply this number of consecutive mutations to each input exit after the first new interesting input is found the minimized corpus is saved into the first input directory Number of jobs to run If Reload the main corpus periodically to get new units discovered by other processes Read the given input file
#define ALL_EA_BASES
static bool translateInstruction(MCInst &target, InternalInstruction &source, const MCDisassembler *Dis)
translateInstruction - Translates an internal instruction and all its operands to an MCInst...
#define EA_BASES_64BIT
static void translateFPRegister(MCInst &mcInst, uint8_t stackPos)
translateFPRegister - Translates a stack position on the FPU stack to its LLVM form, and appends it to an MCInst.
Context object for machine code objects.
Definition: MCContext.h:48
static void translateRegister(MCInst &mcInst, Reg reg)
translateRegister - Translates an internal register to the appropriate LLVM register, and appends it as an operand to an MCInst.
static void tryAddingPcLoadReferenceComment(uint64_t Address, uint64_t Value, const void *Decoder)
tryAddingPcLoadReferenceComment - trys to add a comment as to what is being referenced by a load inst...
int decodeInstruction(InternalInstruction *insn, byteReader_t reader, const void *readerArg, dlog_t logger, void *loggerArg, const void *miiArg, uint64_t startLoc, DisassemblerMode mode)
Decode one instruction and store the decoding results in a buffer provided by the consumer...
static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand, InternalInstruction &insn, const MCDisassembler *Dis)
translateOperand - Translates an operand stored in an internal instruction to LLVM's format and appen...
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:134
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:150
The specification for how to extract and interpret one operand.
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
static bool translateSrcIndex(MCInst &mcInst, InternalInstruction &insn)
translateSrcIndex - Appends a source index operand to an MCInst.
static int regionReader(const void *Arg, uint8_t *Byte, uint64_t Address)
A callback function that wraps the readByte method from Region.
const char * getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
Definition: MCInstrInfo.h:51
#define ALL_SIB_BASES
#define CASE_ENCODING_RM
const char * GetInstrName(unsigned Opcode, const void *mii)
Target TheX86_32Target
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
Region(ArrayRef< uint8_t > Bytes, uint64_t Base)
static const uint8_t segmentRegnums[SEG_OVERRIDE_max]
void Debug(const char *file, unsigned line, const char *s)
Print a message to debugs()
The x86 internal instruction, which is produced by the decoder.
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t InstSize) const
void setOpcode(unsigned Op)
Definition: MCInst.h:158
static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand, InternalInstruction &insn, const MCDisassembler *Dis)
translateRM - Translates an operand stored in the R/M (and possibly SIB) byte of an instruction to LL...
ArrayRef< uint8_t > Bytes
static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn, const MCDisassembler *Dis)
translateRMMemory - Translates a memory operand stored in the Mod and R/M fields of an internal instr...
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
void(* dlog_t)(void *arg, const char *log)
Type for the logging function that the consumer can provide to get debugging output from the decoder...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:123
void LLVMInitializeX86Disassembler()
#define debug(s)
unsigned getOpcode() const
Definition: MCInst.h:159
Target - Wrapper for Target specific information.
#define REGS_ZMM
static bool translateDstIndex(MCInst &mcInst, InternalInstruction &insn)
translateDstIndex - Appends a destination index operand to an MCInst.
static bool translateRMRegister(MCInst &mcInst, InternalInstruction &insn)
translateRMRegister - Translates a register stored in the R/M field of the ModR/M byte to its LLVM eq...
OperandType
Types of operands to CF instructions.
static MCDisassembler * createX86Disassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
MCSubtargetInfo - Generic base class for all target subtargets.
#define REGS_XMM
static void logger(void *arg, const char *log)
logger - a callback function that wraps the operator<< method from raw_ostream.
static bool isBranch(unsigned Opcode)
LLVM Value Representation.
Definition: Value.h:69
raw_ostream & nulls()
This returns a reference to a raw_ostream which simply discards output.
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:38
void addOperand(const MCOperand &Op)
Definition: MCInst.h:168
static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch, uint64_t Address, uint64_t Offset, uint64_t Width, MCInst &MI, const MCDisassembler *Dis)
tryAddingSymbolicOperand - trys to add a symbolic operand in place of the immediate Value in the MCIn...
#define REGS_YMM
#define EA_BASES_32BIT
uint64_t Base
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:33
void tryAddingPcLoadReferenceComment(int64_t Value, uint64_t Address) const
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:117
Generic disassembler for all X86 platforms.
static bool translateMaskRegister(MCInst &mcInst, uint8_t maskRegNum)
translateMaskRegister - Translates a 3-bit mask register number to LLVM form, and appends it to an MC...
DecodeStatus getInstruction(MCInst &instr, uint64_t &size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &vStream, raw_ostream &cStream) const override
Returns the disassembly of a single instruction.