LLVM  3.7.0
Passes.cpp
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1 //===-- Passes.cpp - Target independent code generation passes ------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines interfaces to access the target independent code
11 // generation passes provided by the LLVM backend.
12 //
13 //===---------------------------------------------------------------------===//
14 
15 #include "llvm/CodeGen/Passes.h"
16 #include "llvm/Analysis/Passes.h"
21 #include "llvm/IR/Verifier.h"
22 #include "llvm/MC/MCAsmInfo.h"
24 #include "llvm/Support/Debug.h"
28 #include "llvm/Transforms/Scalar.h"
30 
31 using namespace llvm;
32 
33 static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden,
34  cl::desc("Disable Post Regalloc"));
35 static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
36  cl::desc("Disable branch folding"));
37 static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
38  cl::desc("Disable tail duplication"));
39 static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
40  cl::desc("Disable pre-register allocation tail duplication"));
41 static cl::opt<bool> DisableBlockPlacement("disable-block-placement",
42  cl::Hidden, cl::desc("Disable probability-driven block placement"));
43 static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
44  cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
45 static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
46  cl::desc("Disable Stack Slot Coloring"));
47 static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
48  cl::desc("Disable Machine Dead Code Elimination"));
49 static cl::opt<bool> DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden,
50  cl::desc("Disable Early If-conversion"));
51 static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
52  cl::desc("Disable Machine LICM"));
53 static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
54  cl::desc("Disable Machine Common Subexpression Elimination"));
56  EnableShrinkWrapOpt("enable-shrink-wrap", cl::Hidden,
57  cl::desc("enable the shrink-wrapping pass"));
59  "optimize-regalloc", cl::Hidden,
60  cl::desc("Enable optimized register allocation compilation path."));
61 static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
62  cl::Hidden,
63  cl::desc("Disable Machine LICM"));
64 static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
65  cl::desc("Disable Machine Sinking"));
66 static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
67  cl::desc("Disable Loop Strength Reduction Pass"));
68 static cl::opt<bool> DisableConstantHoisting("disable-constant-hoisting",
69  cl::Hidden, cl::desc("Disable ConstantHoisting"));
70 static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
71  cl::desc("Disable Codegen Prepare"));
72 static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
73  cl::desc("Disable Copy Propagation pass"));
74 static cl::opt<bool> DisablePartialLibcallInlining("disable-partial-libcall-inlining",
75  cl::Hidden, cl::desc("Disable Partial Libcall Inlining"));
77  "enable-implicit-null-checks",
78  cl::desc("Fold null checks into faulting memory operations"),
79  cl::init(false));
80 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
81  cl::desc("Print LLVM IR produced by the loop-reduce pass"));
82 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
83  cl::desc("Print LLVM IR input to isel pass"));
84 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
85  cl::desc("Dump garbage collector data"));
86 static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
87  cl::desc("Verify generated machine code"),
88  cl::init(false),
90 
92 PrintMachineInstrs("print-machineinstrs", cl::ValueOptional,
93  cl::desc("Print machine instrs"),
94  cl::value_desc("pass-name"), cl::init("option-unspecified"));
95 
96 // Temporary option to allow experimenting with MachineScheduler as a post-RA
97 // scheduler. Targets can "properly" enable this with
98 // substitutePass(&PostRASchedulerID, &PostMachineSchedulerID); Ideally it
99 // wouldn't be part of the standard pass pipeline, and the target would just add
100 // a PostRA scheduling pass wherever it wants.
101 static cl::opt<bool> MISchedPostRA("misched-postra", cl::Hidden,
102  cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"));
103 
104 // Experimental option to run live interval analysis early.
105 static cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden,
106  cl::desc("Run live interval analysis earlier in the pipeline"));
107 
108 static cl::opt<bool> UseCFLAA("use-cfl-aa-in-codegen",
109  cl::init(false), cl::Hidden,
110  cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"));
111 
112 /// Allow standard passes to be disabled by command line options. This supports
113 /// simple binary flags that either suppress the pass or do nothing.
114 /// i.e. -disable-mypass=false has no effect.
115 /// These should be converted to boolOrDefault in order to use applyOverride.
117  bool Override) {
118  if (Override)
119  return IdentifyingPassPtr();
120  return PassID;
121 }
122 
123 /// Allow standard passes to be disabled by the command line, regardless of who
124 /// is adding the pass.
125 ///
126 /// StandardID is the pass identified in the standard pass pipeline and provided
127 /// to addPass(). It may be a target-specific ID in the case that the target
128 /// directly adds its own pass, but in that case we harmlessly fall through.
129 ///
130 /// TargetID is the pass that the target has configured to override StandardID.
131 ///
132 /// StandardID may be a pseudo ID. In that case TargetID is the name of the real
133 /// pass to run. This allows multiple options to control a single pass depending
134 /// on where in the pipeline that pass is added.
136  IdentifyingPassPtr TargetID) {
137  if (StandardID == &PostRASchedulerID)
138  return applyDisable(TargetID, DisablePostRA);
139 
140  if (StandardID == &BranchFolderPassID)
141  return applyDisable(TargetID, DisableBranchFold);
142 
143  if (StandardID == &TailDuplicateID)
144  return applyDisable(TargetID, DisableTailDuplicate);
145 
146  if (StandardID == &TargetPassConfig::EarlyTailDuplicateID)
147  return applyDisable(TargetID, DisableEarlyTailDup);
148 
149  if (StandardID == &MachineBlockPlacementID)
150  return applyDisable(TargetID, DisableBlockPlacement);
151 
152  if (StandardID == &StackSlotColoringID)
153  return applyDisable(TargetID, DisableSSC);
154 
155  if (StandardID == &DeadMachineInstructionElimID)
156  return applyDisable(TargetID, DisableMachineDCE);
157 
158  if (StandardID == &EarlyIfConverterID)
159  return applyDisable(TargetID, DisableEarlyIfConversion);
160 
161  if (StandardID == &MachineLICMID)
162  return applyDisable(TargetID, DisableMachineLICM);
163 
164  if (StandardID == &MachineCSEID)
165  return applyDisable(TargetID, DisableMachineCSE);
166 
167  if (StandardID == &TargetPassConfig::PostRAMachineLICMID)
168  return applyDisable(TargetID, DisablePostRAMachineLICM);
169 
170  if (StandardID == &MachineSinkingID)
171  return applyDisable(TargetID, DisableMachineSink);
172 
173  if (StandardID == &MachineCopyPropagationID)
174  return applyDisable(TargetID, DisableCopyProp);
175 
176  return TargetID;
177 }
178 
179 //===---------------------------------------------------------------------===//
180 /// TargetPassConfig
181 //===---------------------------------------------------------------------===//
182 
183 INITIALIZE_PASS(TargetPassConfig, "targetpassconfig",
184  "Target Pass Configuration", false, false)
185 char TargetPassConfig::ID = 0;
186 
187 // Pseudo Pass IDs.
188 char TargetPassConfig::EarlyTailDuplicateID = 0;
189 char TargetPassConfig::PostRAMachineLICMID = 0;
190 
191 namespace llvm {
193 public:
194  // List of passes explicitly substituted by this target. Normally this is
195  // empty, but it is a convenient way to suppress or replace specific passes
196  // that are part of a standard pass pipeline without overridding the entire
197  // pipeline. This mechanism allows target options to inherit a standard pass's
198  // user interface. For example, a target may disable a standard pass by
199  // default by substituting a pass ID of zero, and the user may still enable
200  // that standard pass with an explicit command line option.
202 
203  /// Store the pairs of <AnalysisID, AnalysisID> of which the second pass
204  /// is inserted after each instance of the first one.
206 };
207 } // namespace llvm
208 
209 // Out of line virtual method.
211  delete Impl;
212 }
213 
214 // Out of line constructor provides default values for pass options and
215 // registers all common codegen passes.
217  : ImmutablePass(ID), PM(&pm), StartBefore(nullptr), StartAfter(nullptr),
218  StopAfter(nullptr), Started(true), Stopped(false),
219  AddingMachinePasses(false), TM(tm), Impl(nullptr), Initialized(false),
220  DisableVerify(false), EnableTailMerge(true), EnableShrinkWrap(false) {
221 
222  Impl = new PassConfigImpl();
223 
224  // Register all target independent codegen passes to activate their PassIDs,
225  // including this pass itself.
227 
228  // Substitute Pseudo Pass IDs for real ones.
231 }
232 
233 /// Insert InsertedPassID pass after TargetPassID.
235  IdentifyingPassPtr InsertedPassID) {
236  assert(((!InsertedPassID.isInstance() &&
237  TargetPassID != InsertedPassID.getID()) ||
238  (InsertedPassID.isInstance() &&
239  TargetPassID != InsertedPassID.getInstance()->getPassID())) &&
240  "Insert a pass after itself!");
241  std::pair<AnalysisID, IdentifyingPassPtr> P(TargetPassID, InsertedPassID);
242  Impl->InsertedPasses.push_back(P);
243 }
244 
245 /// createPassConfig - Create a pass configuration object to be used by
246 /// addPassToEmitX methods for generating a pipeline of CodeGen passes.
247 ///
248 /// Targets may override this to extend TargetPassConfig.
250  return new TargetPassConfig(this, PM);
251 }
252 
254  : ImmutablePass(ID), PM(nullptr) {
255  llvm_unreachable("TargetPassConfig should not be constructed on-the-fly");
256 }
257 
258 // Helper to verify the analysis is really immutable.
259 void TargetPassConfig::setOpt(bool &Opt, bool Val) {
260  assert(!Initialized && "PassConfig is immutable");
261  Opt = Val;
262 }
263 
265  IdentifyingPassPtr TargetID) {
266  Impl->TargetPasses[StandardID] = TargetID;
267 }
268 
271  I = Impl->TargetPasses.find(ID);
272  if (I == Impl->TargetPasses.end())
273  return ID;
274  return I->second;
275 }
276 
277 /// Add a pass to the PassManager if that pass is supposed to be run. If the
278 /// Started/Stopped flags indicate either that the compilation should start at
279 /// a later pass or that it should stop after an earlier pass, then do not add
280 /// the pass. Finally, compare the current pass against the StartAfter
281 /// and StopAfter options and change the Started/Stopped flags accordingly.
282 void TargetPassConfig::addPass(Pass *P, bool verifyAfter, bool printAfter) {
283  assert(!Initialized && "PassConfig is immutable");
284 
285  // Cache the Pass ID here in case the pass manager finds this pass is
286  // redundant with ones already scheduled / available, and deletes it.
287  // Fundamentally, once we add the pass to the manager, we no longer own it
288  // and shouldn't reference it.
289  AnalysisID PassID = P->getPassID();
290 
291  if (StartBefore == PassID)
292  Started = true;
293  if (Started && !Stopped) {
294  std::string Banner;
295  // Construct banner message before PM->add() as that may delete the pass.
296  if (AddingMachinePasses && (printAfter || verifyAfter))
297  Banner = std::string("After ") + std::string(P->getPassName());
298  PM->add(P);
299  if (AddingMachinePasses) {
300  if (printAfter)
301  addPrintPass(Banner);
302  if (verifyAfter)
303  addVerifyPass(Banner);
304  }
305 
306  // Add the passes after the pass P if there is any.
307  for (SmallVectorImpl<std::pair<AnalysisID, IdentifyingPassPtr> >::iterator
308  I = Impl->InsertedPasses.begin(),
309  E = Impl->InsertedPasses.end();
310  I != E; ++I) {
311  if ((*I).first == PassID) {
312  assert((*I).second.isValid() && "Illegal Pass ID!");
313  Pass *NP;
314  if ((*I).second.isInstance())
315  NP = (*I).second.getInstance();
316  else {
317  NP = Pass::createPass((*I).second.getID());
318  assert(NP && "Pass ID not registered");
319  }
320  addPass(NP, false, false);
321  }
322  }
323  } else {
324  delete P;
325  }
326  if (StopAfter == PassID)
327  Stopped = true;
328  if (StartAfter == PassID)
329  Started = true;
330  if (Stopped && !Started)
331  report_fatal_error("Cannot stop compilation after pass that is not run");
332 }
333 
334 /// Add a CodeGen pass at this point in the pipeline after checking for target
335 /// and command line overrides.
336 ///
337 /// addPass cannot return a pointer to the pass instance because is internal the
338 /// PassManager and the instance we create here may already be freed.
340  bool printAfter) {
341  IdentifyingPassPtr TargetID = getPassSubstitution(PassID);
342  IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID);
343  if (!FinalPtr.isValid())
344  return nullptr;
345 
346  Pass *P;
347  if (FinalPtr.isInstance())
348  P = FinalPtr.getInstance();
349  else {
350  P = Pass::createPass(FinalPtr.getID());
351  if (!P)
352  llvm_unreachable("Pass ID not registered");
353  }
354  AnalysisID FinalID = P->getPassID();
355  addPass(P, verifyAfter, printAfter); // Ends the lifetime of P.
356 
357  return FinalID;
358 }
359 
360 void TargetPassConfig::printAndVerify(const std::string &Banner) {
361  addPrintPass(Banner);
362  addVerifyPass(Banner);
363 }
364 
365 void TargetPassConfig::addPrintPass(const std::string &Banner) {
366  if (TM->shouldPrintMachineCode())
367  PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));
368 }
369 
370 void TargetPassConfig::addVerifyPass(const std::string &Banner) {
371  if (VerifyMachineCode)
372  PM->add(createMachineVerifierPass(Banner));
373 }
374 
375 /// Add common target configurable passes that perform LLVM IR to IR transforms
376 /// following machine independent optimization.
378  // Basic AliasAnalysis support.
379  // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
380  // BasicAliasAnalysis wins if they disagree. This is intended to help
381  // support "obvious" type-punning idioms.
382  if (UseCFLAA)
387 
388  // Before running any passes, run the verifier to determine if the input
389  // coming from the front-end and/or optimizer is valid.
390  if (!DisableVerify)
392 
393  // Run loop strength reduction before anything else.
394  if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
396  if (PrintLSR)
397  addPass(createPrintFunctionPass(dbgs(), "\n\n*** Code after LSR ***\n"));
398  }
399 
400  // Run GC lowering passes for builtin collectors
401  // TODO: add a pass insertion point here
404 
405  // Make sure that no unreachable blocks are instruction selected.
407 
408  // Prepare expensive constants for SelectionDAG.
411 
414 }
415 
416 /// Turn exception handling constructs into something the code generators can
417 /// handle.
419  switch (TM->getMCAsmInfo()->getExceptionHandlingType()) {
421  // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
422  // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
423  // catch info can get misplaced when a selector ends up more than one block
424  // removed from the parent invoke(s). This could happen when a landing
425  // pad is shared by multiple invokes and is also a target of a normal
426  // edge from elsewhere.
428  // FALLTHROUGH
432  break;
434  // We support using both GCC-style and MSVC-style exceptions on Windows, so
435  // add both preparation passes. Each pass will only actually run if it
436  // recognizes the personality function.
439  break;
442 
443  // The lower invoke pass may create unreachable code. Remove it.
445  break;
446  }
447 }
448 
449 /// Add pass to prepare the LLVM IR for code generation. This should be done
450 /// before exception handling preparation passes.
455 }
456 
457 /// Add common passes that perform LLVM IR to IR transforms in preparation for
458 /// instruction selection.
460  addPreISel();
461 
462  // Add both the safe stack and the stack protection passes: each of them will
463  // only protect functions that have corresponding attributes.
466 
467  if (PrintISelInput)
469  dbgs(), "\n\n*** Final LLVM Code input to ISel ***\n"));
470 
471  // All passes which modify the LLVM IR are now complete; run the verifier
472  // to ensure that the IR is valid.
473  if (!DisableVerify)
475 }
476 
477 /// Add the complete set of target-independent postISel code generator passes.
478 ///
479 /// This can be read as the standard order of major LLVM CodeGen stages. Stages
480 /// with nontrivial configuration or multiple passes are broken out below in
481 /// add%Stage routines.
482 ///
483 /// Any TargetPassConfig::addXX routine may be overriden by the Target. The
484 /// addPre/Post methods with empty header implementations allow injecting
485 /// target-specific fixups just before or after major stages. Additionally,
486 /// targets have the flexibility to change pass order within a stage by
487 /// overriding default implementation of add%Stage routines below. Each
488 /// technique has maintainability tradeoffs because alternate pass orders are
489 /// not well supported. addPre/Post works better if the target pass is easily
490 /// tied to a common pass. But if it has subtle dependencies on multiple passes,
491 /// the target should override the stage instead.
492 ///
493 /// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
494 /// before/after any target-independent pass. But it's currently overkill.
496  AddingMachinePasses = true;
497 
498  // Insert a machine instr printer pass after the specified pass.
499  // If -print-machineinstrs specified, print machineinstrs after all passes.
500  if (StringRef(PrintMachineInstrs.getValue()).equals(""))
501  TM->Options.PrintMachineCode = true;
502  else if (!StringRef(PrintMachineInstrs.getValue())
503  .equals("option-unspecified")) {
505  const PassInfo *TPI = PR->getPassInfo(PrintMachineInstrs.getValue());
506  const PassInfo *IPI = PR->getPassInfo(StringRef("machineinstr-printer"));
507  assert (TPI && IPI && "Pass ID not registered!");
508  const char *TID = (const char *)(TPI->getTypeInfo());
509  const char *IID = (const char *)(IPI->getTypeInfo());
510  insertPass(TID, IID);
511  }
512 
513  // Print the instruction selected machine code...
514  printAndVerify("After Instruction Selection");
515 
516  // Expand pseudo-instructions emitted by ISel.
518 
519  // Add passes that optimize machine instructions in SSA form.
520  if (getOptLevel() != CodeGenOpt::None) {
522  } else {
523  // If the target requests it, assign local variables to stack slots relative
524  // to one another and simplify frame index references where possible.
526  }
527 
528  // Run pre-ra passes.
529  addPreRegAlloc();
530 
531  // Run register allocation and passes that are tightly coupled with it,
532  // including phi elimination and scheduling.
533  if (getOptimizeRegAlloc())
535  else
537 
538  // Run post-ra passes.
539  addPostRegAlloc();
540 
541  // Insert prolog/epilog code. Eliminate abstract frame index references...
542  if (getEnableShrinkWrap())
545 
546  /// Add passes that optimize machine instructions after register allocation.
547  if (getOptLevel() != CodeGenOpt::None)
549 
550  // Expand pseudo instructions before second scheduling pass.
552 
553  // Run pre-sched2 passes.
554  addPreSched2();
555 
558 
559  // Second pass scheduler.
560  if (getOptLevel() != CodeGenOpt::None) {
561  if (MISchedPostRA)
563  else
565  }
566 
567  // GC
568  if (addGCPasses()) {
569  if (PrintGCInfo)
570  addPass(createGCInfoPrinter(dbgs()), false, false);
571  }
572 
573  // Basic block placement.
574  if (getOptLevel() != CodeGenOpt::None)
576 
577  addPreEmitPass();
578 
579  addPass(&StackMapLivenessID, false);
580 
581  AddingMachinePasses = false;
582 }
583 
584 /// Add passes that optimize machine instructions in SSA form.
586  // Pre-ra tail duplication.
588 
589  // Optimize PHIs before DCE: removing dead PHI cycles may make more
590  // instructions dead.
591  addPass(&OptimizePHIsID, false);
592 
593  // This pass merges large allocas. StackSlotColoring is a different pass
594  // which merges spill slots.
595  addPass(&StackColoringID, false);
596 
597  // If the target requests it, assign local variables to stack slots relative
598  // to one another and simplify frame index references where possible.
600 
601  // With optimization, dead code should already be eliminated. However
602  // there is one known exception: lowered code for arguments that are only
603  // used by tail calls, where the tail calls reuse the incoming stack
604  // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
606 
607  // Allow targets to insert passes that improve instruction level parallelism,
608  // like if-conversion. Such passes will typically need dominator trees and
609  // loop info, just like LICM and CSE below.
610  addILPOpts();
611 
612  addPass(&MachineLICMID, false);
613  addPass(&MachineCSEID, false);
615 
616  addPass(&PeepholeOptimizerID, false);
617  // Clean-up the dead code that may have been generated by peephole
618  // rewriting.
620 }
621 
623  switch (EnableShrinkWrapOpt) {
624  case cl::BOU_UNSET:
626  // If EnableShrinkWrap is set, it takes precedence on whatever the
627  // target sets. The rational is that we assume we want to test
628  // something related to shrink-wrapping.
629  case cl::BOU_TRUE:
630  return true;
631  case cl::BOU_FALSE:
632  return false;
633  }
634  llvm_unreachable("Invalid shrink-wrapping state");
635 }
636 
637 //===---------------------------------------------------------------------===//
638 /// Register Allocation Pass Configuration
639 //===---------------------------------------------------------------------===//
640 
642  switch (OptimizeRegAlloc) {
643  case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None;
644  case cl::BOU_TRUE: return true;
645  case cl::BOU_FALSE: return false;
646  }
647  llvm_unreachable("Invalid optimize-regalloc state");
648 }
649 
650 /// RegisterRegAlloc's global Registry tracks allocator registration.
652 
653 /// A dummy default pass factory indicates whether the register allocator is
654 /// overridden on the command line.
655 static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
656 static RegisterRegAlloc
657 defaultRegAlloc("default",
658  "pick register allocator based on -O option",
660 
661 /// -regalloc=... command line option.
664 RegAlloc("regalloc",
666  cl::desc("Register allocator to use"));
667 
668 
669 /// Instantiate the default register allocator pass for this target for either
670 /// the optimized or unoptimized allocation path. This will be added to the pass
671 /// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
672 /// in the optimized case.
673 ///
674 /// A target that uses the standard regalloc pass order for fast or optimized
675 /// allocation may still override this for per-target regalloc
676 /// selection. But -regalloc=... always takes precedence.
678  if (Optimized)
680  else
682 }
683 
684 /// Find and instantiate the register allocation pass requested by this target
685 /// at the current optimization level. Different register allocators are
686 /// defined as separate passes because they may require different analysis.
687 ///
688 /// This helper ensures that the regalloc= option is always available,
689 /// even for targets that override the default allocator.
690 ///
691 /// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs,
692 /// this can be folded into addPass.
695 
696  // Initialize the global default.
697  if (!Ctor) {
698  Ctor = RegAlloc;
700  }
701  if (Ctor != useDefaultRegisterAllocator)
702  return Ctor();
703 
704  // With no -regalloc= override, ask the target for a regalloc pass.
705  return createTargetRegisterAllocator(Optimized);
706 }
707 
708 /// Return true if the default global register allocator is in use and
709 /// has not be overriden on the command line with '-regalloc=...'
711  return RegAlloc.getNumOccurrences() == 0;
712 }
713 
714 /// Add the minimum set of target-independent passes that are required for
715 /// register allocation. No coalescing or scheduling.
717  addPass(&PHIEliminationID, false);
719 
720  addPass(RegAllocPass);
721 }
722 
723 /// Add standard target-independent passes that are tightly coupled with
724 /// optimized register allocation, including coalescing, machine instruction
725 /// scheduling, and register allocation itself.
728 
729  // LiveVariables currently requires pure SSA form.
730  //
731  // FIXME: Once TwoAddressInstruction pass no longer uses kill flags,
732  // LiveVariables can be removed completely, and LiveIntervals can be directly
733  // computed. (We still either need to regenerate kill flags after regalloc, or
734  // preferably fix the scavenger to not depend on them).
735  addPass(&LiveVariablesID, false);
736 
737  // Edge splitting is smarter with machine loop info.
738  addPass(&MachineLoopInfoID, false);
739  addPass(&PHIEliminationID, false);
740 
741  // Eventually, we want to run LiveIntervals before PHI elimination.
742  if (EarlyLiveIntervals)
743  addPass(&LiveIntervalsID, false);
744 
747 
748  // PreRA instruction scheduling.
750 
751  // Add the selected register allocation pass.
752  addPass(RegAllocPass);
753 
754  // Allow targets to change the register assignments before rewriting.
755  addPreRewrite();
756 
757  // Finally rewrite virtual registers.
759 
760  // Perform stack slot coloring and post-ra machine LICM.
761  //
762  // FIXME: Re-enable coloring with register when it's capable of adding
763  // kill markers.
765 
766  // Run post-ra machine LICM to hoist reloads / remats.
767  //
768  // FIXME: can this move into MachineLateOptimization?
770 }
771 
772 //===---------------------------------------------------------------------===//
773 /// Post RegAlloc Pass Configuration
774 //===---------------------------------------------------------------------===//
775 
776 /// Add passes that optimize machine instructions after register allocation.
778  // Branch folding must be run after regalloc and prolog/epilog insertion.
780 
781  // Tail duplication.
782  // Note that duplicating tail just increases code size and degrades
783  // performance for targets that require Structured Control Flow.
784  // In addition it can also make CFG irreducible. Thus we disable it.
785  if (!TM->requiresStructuredCFG())
787 
788  // Copy propagation.
790 }
791 
792 /// Add standard GC passes.
795  return true;
796 }
797 
798 /// Add standard basic block placement passes.
800  if (addPass(&MachineBlockPlacementID, false)) {
801  // Run a separate pass to collect block placement statistics.
804  }
805 }
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:82
static cl::opt< cl::boolOrDefault > OptimizeRegAlloc("optimize-regalloc", cl::Hidden, cl::desc("Enable optimized register allocation compilation path."))
unsigned PrintMachineCode
PrintMachineCode - This flag is enabled when the -print-machineinstrs option is specified on the comm...
Definition: TargetOptions.h:83
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Pass * createLoopStrengthReducePass()
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: Passes.cpp:377
AnalysisID getPassID() const
getPassID - Return the PassID number that corresponds to this pass.
Definition: Pass.h:104
FunctionPass * createSafeStackPass()
This pass splits the stack into a safe stack and an unsafe stack to protect against stack-based overf...
Definition: SafeStack.cpp:609
static cl::opt< bool > DisablePartialLibcallInlining("disable-partial-libcall-inlining", cl::Hidden, cl::desc("Disable Partial Libcall Inlining"))
char & MachineLICMID
MachineLICM - This pass performs LICM on machine instructions.
DWARF-like instruction based exceptions.
virtual bool addPreRewrite()
addPreRewrite - Add passes to the optimized register allocation pipeline after register allocation is...
FunctionPass * createPrintFunctionPass(raw_ostream &OS, const std::string &Banner="")
Create and return a pass that prints functions to the specified raw_ostream as they are processed...
FunctionPass * createVerifierPass(bool FatalErrors=true)
Create a verifier pass.
Definition: Verifier.cpp:3703
char & RegisterCoalescerID
RegisterCoalescer - This pass merges live ranges to eliminate copies.
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions...
FunctionPass *(* FunctionPassCtor)()
virtual const char * getPassName() const
getPassName - Return a nice clean name for a pass.
Definition: Pass.cpp:61
static void setDefault(FunctionPassCtor C)
FunctionPass * createWinEHPass(const TargetMachine *TM)
createWinEHPass - Prepares personality functions used by MSVC on Windows, in addition to the Itanium ...
const void * getTypeInfo() const
getTypeInfo - Return the id object for the pass...
Definition: PassInfo.h:78
char & MachineSchedulerID
MachineScheduler - This pass schedules machine instructions.
setjmp/longjmp based exceptions
RegisterPassParser class - Handle the addition of new machine passes.
static MachinePassRegistry Registry
RegisterRegAlloc's global Registry tracks allocator registration.
char & ProcessImplicitDefsID
ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form...
Definition: Passes.cpp:585
char & MachineBlockPlacementStatsID
MachineBlockPlacementStats - This pass collects statistics about the basic block placement using bran...
bool getEnableShrinkWrap() const
Return true if shrink wrapping is enabled.
Definition: Passes.cpp:622
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag=true)
Reports a serious error, calling any installed error handler.
FunctionPass * createShadowStackGCLoweringPass()
ShadowStackGCLowering - Implements the custom lowering mechanism used by the shadow stack GC...
virtual TargetPassConfig * createPassConfig(PassManagerBase &PM)
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
Definition: Passes.cpp:249
static cl::opt< bool > DisableLSR("disable-lsr", cl::Hidden, cl::desc("Disable Loop Strength Reduction Pass"))
static cl::opt< bool > DisableEarlyTailDup("disable-early-taildup", cl::Hidden, cl::desc("Disable pre-register allocation tail duplication"))
virtual void addPreEmitPass()
This pass may be implemented by targets that want to run passes immediately before machine code is em...
Pass * getInstance() const
FunctionPass * createMachineVerifierPass(const std::string &Banner)
createMachineVerifierPass - This pass verifies cenerated machine code instructions for correctness...
void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID)
Insert InsertedPassID pass after TargetPassID pass.
Definition: Passes.cpp:234
static cl::opt< bool > VerifyMachineCode("verify-machineinstrs", cl::Hidden, cl::desc("Verify generated machine code"), cl::init(false), cl::ZeroOrMore)
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
FunctionPass * createGCLoweringPass()
GCLowering Pass - Used by gc.root to perform its default lowering operations.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
bool getOptimizeRegAlloc() const
Return true if the optimized regalloc pipeline is enabled.
Definition: Passes.cpp:641
char & StackColoringID
StackSlotColoring - This pass performs stack coloring and merging.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APInt.h:33
static cl::opt< bool > DisableBlockPlacement("disable-block-placement", cl::Hidden, cl::desc("Disable probability-driven block placement"))
virtual void addPreSched2()
This method may be implemented by targets that want to run passes after prolog-epilog insertion and b...
static RegisterRegAlloc defaultRegAlloc("default","pick register allocator based on -O option", useDefaultRegisterAllocator)
FunctionPass * createRegAllocPass(bool Optimized)
addMachinePasses helper to create the target-selected or overriden regalloc pass. ...
Definition: Passes.cpp:693
static IdentifyingPassPtr overridePass(AnalysisID StandardID, IdentifyingPassPtr TargetID)
Allow standard passes to be disabled by the command line, regardless of who is adding the pass...
Definition: Passes.cpp:135
#define false
Definition: ConvertUTF.c:65
Target-Independent Code Generator Pass Configuration Options.
CodeGenOpt::Level getOptLevel() const
virtual void addMachinePasses()
Add the complete, standard set of LLVM CodeGen passes.
Definition: Passes.cpp:495
IdentifyingPassPtr getPassSubstitution(AnalysisID StandardID) const
Return the pass substituted for StandardID by the target.
Definition: Passes.cpp:269
char & MachineCSEID
MachineCSE - This pass performs global CSE on machine instructions.
Definition: MachineCSE.cpp:110
static cl::opt< bool > EnableBlockPlacementStats("enable-block-placement-stats", cl::Hidden, cl::desc("Collect probability-driven block placement stats"))
char & StackSlotColoringID
StackSlotColoring - This pass performs stack slot coloring.
virtual void addPreRegAlloc()
This method may be implemented by targets that want to run passes immediately before register allocat...
char & ExpandPostRAPseudosID
ExpandPostRAPseudos - This pass expands pseudo instructions after register allocation.
ImmutablePass * createBasicAliasAnalysisPass()
char & ExpandISelPseudosID
ExpandISelPseudos - This pass expands pseudo-instructions.
char & DeadMachineInstructionElimID
DeadMachineInstructionElim - This pass removes dead machine instructions.
ImmutablePass * createScopedNoAliasAAPass()
static cl::opt< cl::boolOrDefault > EnableShrinkWrapOpt("enable-shrink-wrap", cl::Hidden, cl::desc("enable the shrink-wrapping pass"))
void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID)
Allow the target to override a specific pass without overriding the pass pipeline.
Definition: Passes.cpp:264
FunctionPass * createUnreachableBlockEliminationPass()
createUnreachableBlockEliminationPass - The LLVM code generator does not work well with unreachable b...
RegisterRegAlloc class - Track the registration of register allocators.
MachinePassRegistry - Track the registration of machine passes.
char & LiveIntervalsID
LiveIntervals - This analysis keeps track of the live ranges of virtual and physical registers...
virtual bool addILPOpts()
Add passes that optimize instruction level parallelism for out-of-order targets.
ImmutablePass * createCFLAliasAnalysisPass()
static cl::opt< bool > MISchedPostRA("misched-postra", cl::Hidden, cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"))
FunctionPass * createGCInfoPrinter(raw_ostream &OS)
Creates a pass to print GC metadata.
Definition: GCMetadata.cpp:86
static cl::opt< bool > DisablePostRA("disable-post-ra", cl::Hidden, cl::desc("Disable Post Regalloc"))
FunctionPass * createCodeGenPreparePass(const TargetMachine *TM=nullptr)
createCodeGenPreparePass - Transform the code to expose more pattern matching during instruction sele...
DenseMap< AnalysisID, IdentifyingPassPtr > TargetPasses
Definition: Passes.cpp:201
char & PHIEliminationID
PHIElimination - This pass eliminates machine instruction PHI nodes by inserting copy instructions...
char & LiveVariablesID
LiveVariables pass - This pass computes the set of blocks in which each variable is life and sets mac...
virtual FunctionPass * createTargetRegisterAllocator(bool Optimized)
createTargetRegisterAllocator - Create the register allocator pass for this target at the current opt...
Definition: Passes.cpp:677
virtual bool addGCPasses()
addGCPasses - Add late codegen passes that analyze code for garbage collection.
Definition: Passes.cpp:793
#define P(N)
#define true
Definition: ConvertUTF.c:66
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:325
ImmutablePass * createTypeBasedAliasAnalysisPass()
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
static char PostRAMachineLICMID
PostRAMachineLICM - A clone of the LICM pass that runs during late machine optimization after regallo...
void printAndVerify(const std::string &Banner)
printAndVerify - Add a pass to dump then verify the machine function, if those steps are enabled...
Definition: Passes.cpp:360
virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass)
addOptimizedRegAlloc - Add passes related to register allocation.
Definition: Passes.cpp:726
virtual void addMachineLateOptimization()
Add passes that optimize machine instructions after register allocation.
Definition: Passes.cpp:777
virtual bool addPreISel()
Methods with trivial inline returns are convenient points in the common codegen pass pipeline where t...
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:294
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:511
virtual void addISelPrepare()
Add common passes that perform LLVM IR to IR transforms in preparation for instruction selection...
Definition: Passes.cpp:459
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
Definition: Passes.cpp:451
static FunctionPass * useDefaultRegisterAllocator()
A dummy default pass factory indicates whether the register allocator is overridden on the command li...
Definition: Passes.cpp:655
static cl::opt< RegisterRegAlloc::FunctionPassCtor, false, RegisterPassParser< RegisterRegAlloc > > RegAlloc("regalloc", cl::init(&useDefaultRegisterAllocator), cl::desc("Register allocator to use"))
-regalloc=... command line option.
static cl::opt< bool > DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden, cl::desc("Disable Early If-conversion"))
PassInfo class - An instance of this class exists for every pass known by the system, and can be obtained from a live Pass by calling its getPassInfo() method.
Definition: PassInfo.h:30
char & MachineCopyPropagationID
MachineCopyPropagation - This pass performs copy propagation on machine instructions.
void addPrintPass(const std::string &Banner)
Add a pass to print the machine function if printing is enabled.
Definition: Passes.cpp:365
static cl::opt< bool > DisablePostRAMachineLICM("disable-postra-machine-licm", cl::Hidden, cl::desc("Disable Machine LICM"))
char & ImplicitNullChecksID
ImplicitNullChecks - This pass folds null pointer checks into nearby memory operations.
void addPassesToHandleExceptions()
Add passes to lower exception handling for the code generator.
Definition: Passes.cpp:418
static cl::opt< bool > PrintLSR("print-lsr-output", cl::Hidden, cl::desc("Print LLVM IR produced by the loop-reduce pass"))
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:56
char & PostRASchedulerID
createPostRAScheduler - This pass performs post register allocation scheduling.
static FunctionPassCtor getDefault()
FunctionPass * createStackProtectorPass(const TargetMachine *TM)
createStackProtectorPass - This pass adds stack protectors to functions.
ImmutablePass class - This class is used to provide information that does not need to be run...
Definition: Pass.h:262
static cl::opt< bool > EnableImplicitNullChecks("enable-implicit-null-checks", cl::desc("Fold null checks into faulting memory operations"), cl::init(false))
char & StackMapLivenessID
StackMapLiveness - This pass analyses the register live-out set of stackmap/patchpoint intrinsics and...
static cl::opt< bool > DisableBranchFold("disable-branch-fold", cl::Hidden, cl::desc("Disable branch folding"))
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:861
char & TailDuplicateID
TailDuplicate - Duplicate blocks with unconditional branches into tails of their predecessors.
char & MachineSinkingID
MachineSinking - This pass performs sinking on machine instructions.
static cl::opt< bool > DisableSSC("disable-ssc", cl::Hidden, cl::desc("Disable Stack Slot Coloring"))
~TargetPassConfig() override
Definition: Passes.cpp:210
MachineFunctionPass * createMachineFunctionPrinterPass(raw_ostream &OS, const std::string &Banner="")
MachineFunctionPrinter pass - This pass prints out the machine function to the given stream as a debu...
ModulePass * createRewriteSymbolsPass()
char & OptimizePHIsID
OptimizePHIs - This pass optimizes machine instruction PHIs to take advantage of opportunities create...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:123
virtual void addPostRegAlloc()
This method may be implemented by targets that want to run passes after register allocation pass pipe...
char & PeepholeOptimizerID
PeepholeOptimizer - This pass performs peephole optimizations - like extension and comparison elimina...
Discriminated union of Pass ID types.
bool EnableShrinkWrap
Default setting for -enable-shrink-wrap on this target.
virtual void addFastRegAlloc(FunctionPass *RegAllocPass)
addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast registe...
Definition: Passes.cpp:716
char & PrologEpilogCodeInserterID
PrologEpilogCodeInserter - This pass inserts prolog and epilog code, and eliminates abstract frame re...
FunctionPass * createPartiallyInlineLibCallsPass()
char & GCMachineCodeAnalysisID
GCMachineCodeAnalysis - Target-independent pass to mark safe points in machine code.
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
AnalysisID addPass(AnalysisID PassID, bool verifyAfter=true, bool printAfter=true)
Utilities for targets to add passes to the pass manager.
Definition: Passes.cpp:339
FunctionPass * createDwarfEHPass(const TargetMachine *TM)
createDwarfEHPass - This pass mulches exception handling code into a form adapted to code generation...
static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID, bool Override)
Allow standard passes to be disabled by command line options.
Definition: Passes.cpp:116
static cl::opt< bool > EarlyLiveIntervals("early-live-intervals", cl::Hidden, cl::desc("Run live interval analysis earlier in the pipeline"))
virtual void addBlockPlacement()
Add standard basic block placement passes.
Definition: Passes.cpp:799
static cl::opt< bool > DisableCopyProp("disable-copyprop", cl::Hidden, cl::desc("Disable Copy Propagation pass"))
FunctionPass * createGreedyRegisterAllocator()
Greedy register allocation pass - This pass implements a global register allocator for optimized buil...
AnalysisID getID() const
#define I(x, y, z)
Definition: MD5.cpp:54
FunctionPass * createLowerInvokePass()
char & MachineBlockPlacementID
MachineBlockPlacement - This pass places basic blocks based on branch probabilities.
static cl::opt< bool > DisableMachineSink("disable-machine-sink", cl::Hidden, cl::desc("Disable Machine Sinking"))
static cl::opt< bool > PrintISelInput("print-isel-input", cl::Hidden, cl::desc("Print LLVM IR input to isel pass"))
cl::opt< std::string > StopAfter("stop-after", cl::desc("Stop compilation after a specific pass"), cl::value_desc("pass-name"), cl::init(""))
cl::opt< std::string > StartAfter("start-after", cl::desc("Resume compilation after a specific pass"), cl::value_desc("pass-name"), cl::init(""))
void setOpt(bool &Opt, bool Val)
Definition: Passes.cpp:259
static cl::opt< std::string > PrintMachineInstrs("print-machineinstrs", cl::ValueOptional, cl::desc("Print machine instrs"), cl::value_desc("pass-name"), cl::init("option-unspecified"))
static cl::opt< bool > PrintGCInfo("print-gc", cl::Hidden, cl::desc("Dump garbage collector data"))
const void * AnalysisID
Definition: Pass.h:47
bool shouldPrintMachineCode() const
static cl::opt< bool > DisableMachineCSE("disable-machine-cse", cl::Hidden, cl::desc("Disable Machine Common Subexpression Elimination"))
const PassInfo * getPassInfo(const void *TI) const
getPassInfo - Look up a pass' corresponding PassInfo, indexed by the pass' type identifier (&MyPass::...
This file defines passes to print out IR in various granularities.
char & TwoAddressInstructionPassID
TwoAddressInstruction - This pass reduces two-address instructions to use two operands.
void addVerifyPass(const std::string &Banner)
Add a pass to perform basic verification of the machine function if verification is enabled...
Definition: Passes.cpp:370
FunctionPass * createSjLjEHPreparePass()
createSjLjEHPreparePass - This pass adapts exception handling code to use the GCC-style builtin setjm...
static cl::opt< bool > DisableMachineDCE("disable-machine-dce", cl::Hidden, cl::desc("Disable Machine Dead Code Elimination"))
static cl::opt< bool > DisableConstantHoisting("disable-constant-hoisting", cl::Hidden, cl::desc("Disable ConstantHoisting"))
SmallVector< std::pair< AnalysisID, IdentifyingPassPtr >, 4 > InsertedPasses
Store the pairs of <AnalysisID, AnalysisID> of which the second pass is inserted after each instance ...
Definition: Passes.cpp:205
static char EarlyTailDuplicateID
Pseudo Pass IDs.
static Pass * createPass(AnalysisID ID)
Definition: Pass.cpp:195
void initializeCodeGen(PassRegistry &)
initializeCodeGen - Initialize all passes linked into the CodeGen library.
Definition: CodeGen.cpp:22
FunctionPass * createFastRegisterAllocator()
FastRegisterAllocation Pass - This pass register allocates as fast as possible.
char & VirtRegRewriterID
VirtRegRewriter pass.
Definition: VirtRegMap.cpp:181
static cl::opt< bool > UseCFLAA("use-cfl-aa-in-codegen", cl::init(false), cl::Hidden, cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"))
char & BranchFolderPassID
BranchFolding - This pass performs machine code CFG based optimizations to delete branches to branche...
Primary interface to the complete machine description for the target machine.
char & ShrinkWrapID
ShrinkWrap pass. Look for the best place to insert save and restore.
Definition: ShrinkWrap.cpp:178
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:40
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:41
No exception support.
static cl::opt< bool > DisableMachineLICM("disable-machine-licm", cl::Hidden, cl::desc("Disable Machine LICM"))
static cl::opt< bool > DisableTailDuplicate("disable-tail-duplicate", cl::Hidden, cl::desc("Disable tail duplication"))
bool usingDefaultRegAlloc() const
Return true if the default global register allocator is in use and has not be overriden on the comman...
Definition: Passes.cpp:710
static cl::opt< bool > DisableCGP("disable-cgp", cl::Hidden, cl::desc("Disable Codegen Prepare"))
char & LocalStackSlotAllocationID
LocalStackSlotAllocation - This pass assigns local frame indices to stack slots relative to one anoth...
bool requiresStructuredCFG() const
PassConfigImpl * Impl
FunctionPass * createConstantHoistingPass()