LLVM  3.7.0
HexagonSplitConst32AndConst64.cpp
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1 //=== HexagonSplitConst32AndConst64.cpp - split CONST32/Const64 into HI/LO ===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // When the compiler is invoked with no small data, for instance, with the -G0
11 // command line option, then all CONST32_* opcodes should be broken down into
12 // appropriate LO and HI instructions. This splitting is done by this pass.
13 // The only reason this is not done in the DAG lowering itself is that there
14 // is no simple way of getting the register allocator to allot the same hard
15 // register to the result of LO and HI instructions. This pass is always
16 // scheduled after register allocation.
17 //
18 //===----------------------------------------------------------------------===//
19 
21 #include "HexagonSubtarget.h"
22 #include "HexagonTargetMachine.h"
24 #include "llvm/ADT/Statistic.h"
31 #include "llvm/CodeGen/Passes.h"
36 #include "llvm/Support/Compiler.h"
37 #include "llvm/Support/Debug.h"
42 #include <map>
43 
44 using namespace llvm;
45 
46 #define DEBUG_TYPE "xfer"
47 
48 namespace llvm {
51 }
52 
53 namespace {
54 
55 class HexagonSplitConst32AndConst64 : public MachineFunctionPass {
56  public:
57  static char ID;
58  HexagonSplitConst32AndConst64() : MachineFunctionPass(ID) {}
59 
60  const char *getPassName() const override {
61  return "Hexagon Split Const32s and Const64s";
62  }
63  bool runOnMachineFunction(MachineFunction &Fn) override;
64 };
65 
66 
68 
69 
70 bool HexagonSplitConst32AndConst64::runOnMachineFunction(MachineFunction &Fn) {
71 
72  const HexagonTargetObjectFile &TLOF =
73  *static_cast<const HexagonTargetObjectFile *>(
75  if (TLOF.IsSmallDataEnabled())
76  return true;
77 
80 
81  // Loop over all of the basic blocks
82  for (MachineFunction::iterator MBBb = Fn.begin(), MBBe = Fn.end();
83  MBBb != MBBe; ++MBBb) {
84  MachineBasicBlock* MBB = MBBb;
85  // Traverse the basic block
87  MachineBasicBlock::iterator MIE = MBB->end ();
88  while (MII != MIE) {
89  MachineInstr *MI = MII;
90  int Opc = MI->getOpcode();
91  if (Opc == Hexagon::CONST32_Int_Real &&
92  MI->getOperand(1).isBlockAddress()) {
93  int DestReg = MI->getOperand(0).getReg();
94  MachineOperand &Symbol = MI->getOperand (1);
95 
96  BuildMI (*MBB, MII, MI->getDebugLoc(),
97  TII->get(Hexagon::LO), DestReg).addOperand(Symbol);
98  BuildMI (*MBB, MII, MI->getDebugLoc(),
99  TII->get(Hexagon::HI), DestReg).addOperand(Symbol);
100  // MBB->erase returns the iterator to the next instruction, which is the
101  // one we want to process next
102  MII = MBB->erase (MI);
103  continue;
104  }
105 
106  else if (Opc == Hexagon::CONST32_Int_Real ||
107  Opc == Hexagon::CONST32_Float_Real) {
108  int DestReg = MI->getOperand(0).getReg();
109 
110  // We have to convert an FP immediate into its corresponding integer
111  // representation
112  int64_t ImmValue;
113  if (Opc == Hexagon::CONST32_Float_Real) {
114  APFloat Val = MI->getOperand(1).getFPImm()->getValueAPF();
115  ImmValue = *Val.bitcastToAPInt().getRawData();
116  }
117  else
118  ImmValue = MI->getOperand(1).getImm();
119 
120  BuildMI(*MBB, MII, MI->getDebugLoc(),
121  TII->get(Hexagon::A2_tfrsi), DestReg).addImm(ImmValue);
122  MII = MBB->erase (MI);
123  continue;
124  }
125  else if (Opc == Hexagon::CONST64_Int_Real ||
126  Opc == Hexagon::CONST64_Float_Real) {
127  int DestReg = MI->getOperand(0).getReg();
128 
129  // We have to convert an FP immediate into its corresponding integer
130  // representation
131  int64_t ImmValue;
132  if (Opc == Hexagon::CONST64_Float_Real) {
133  APFloat Val = MI->getOperand(1).getFPImm()->getValueAPF();
134  ImmValue = *Val.bitcastToAPInt().getRawData();
135  }
136  else
137  ImmValue = MI->getOperand(1).getImm();
138 
139  unsigned DestLo = TRI->getSubReg(DestReg, Hexagon::subreg_loreg);
140  unsigned DestHi = TRI->getSubReg(DestReg, Hexagon::subreg_hireg);
141 
142  int32_t LowWord = (ImmValue & 0xFFFFFFFF);
143  int32_t HighWord = (ImmValue >> 32) & 0xFFFFFFFF;
144 
145  BuildMI(*MBB, MII, MI->getDebugLoc(),
146  TII->get(Hexagon::A2_tfrsi), DestLo).addImm(LowWord);
147  BuildMI (*MBB, MII, MI->getDebugLoc(),
148  TII->get(Hexagon::A2_tfrsi), DestHi).addImm(HighWord);
149  MII = MBB->erase (MI);
150  continue;
151  }
152  ++MII;
153  }
154  }
155 
156  return true;
157 }
158 
159 }
160 
161 //===----------------------------------------------------------------------===//
162 // Public Constructor Functions
163 //===----------------------------------------------------------------------===//
164 
165 FunctionPass *
167  return new HexagonSplitConst32AndConst64();
168 }
void initializeHexagonSplitConst32AndConst64Pass(PassRegistry &)
const ConstantFP * getFPImm() const
bool isBlockAddress() const
isBlockAddress - Tests if this is a MO_BlockAddress operand.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
virtual TargetLoweringObjectFile * getObjFileLowering() const
int64_t getImm() const
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:267
TargetInstrInfo - Interface to description of machine instruction set.
bundle_iterator< MachineInstr, instr_iterator > iterator
A self-contained host- and target-independent arbitrary-precision floating-point software implementat...
Definition: APFloat.h:122
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:294
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
MachineOperand class - Representation of each machine instruction operand.
APInt bitcastToAPInt() const
Definition: APFloat.cpp:3084
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:238
Representation of each machine instruction.
Definition: MachineInstr.h:51
FunctionPass * createHexagonSplitConst32AndConst64()
const uint64_t * getRawData() const
This function returns a pointer to the internal storage of the APInt.
Definition: APInt.h:573
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const APFloat & getValueAPF() const
Definition: Constants.h:270
unsigned getReg() const
getReg - Returns the register number.
virtual const TargetInstrInfo * getInstrInfo() const
BasicBlockListType::iterator iterator
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:41