63 #define DEBUG_TYPE "isel"
65 STATISTIC(NumFastIselFailures,
"Number of instructions fast isel failed on");
66 STATISTIC(NumFastIselSuccess,
"Number of instructions fast isel selected");
67 STATISTIC(NumFastIselBlocks,
"Number of blocks selected entirely by fast isel");
68 STATISTIC(NumDAGBlocks,
"Number of blocks selected using DAG");
69 STATISTIC(NumDAGIselRetries,
"Number of times dag isel has to try another path");
70 STATISTIC(NumEntryBlocks,
"Number of entry blocks encountered");
72 "Number of entry blocks where fast isel failed to lower arguments");
77 cl::desc(
"Enable extra verbose messages in the \"fast\" "
78 "instruction selector"));
81 STATISTIC(NumFastIselFailRet,
"Fast isel fails on Ret");
82 STATISTIC(NumFastIselFailBr,
"Fast isel fails on Br");
83 STATISTIC(NumFastIselFailSwitch,
"Fast isel fails on Switch");
84 STATISTIC(NumFastIselFailIndirectBr,
"Fast isel fails on IndirectBr");
85 STATISTIC(NumFastIselFailInvoke,
"Fast isel fails on Invoke");
86 STATISTIC(NumFastIselFailResume,
"Fast isel fails on Resume");
87 STATISTIC(NumFastIselFailUnreachable,
"Fast isel fails on Unreachable");
90 STATISTIC(NumFastIselFailAdd,
"Fast isel fails on Add");
91 STATISTIC(NumFastIselFailFAdd,
"Fast isel fails on FAdd");
92 STATISTIC(NumFastIselFailSub,
"Fast isel fails on Sub");
93 STATISTIC(NumFastIselFailFSub,
"Fast isel fails on FSub");
94 STATISTIC(NumFastIselFailMul,
"Fast isel fails on Mul");
95 STATISTIC(NumFastIselFailFMul,
"Fast isel fails on FMul");
96 STATISTIC(NumFastIselFailUDiv,
"Fast isel fails on UDiv");
97 STATISTIC(NumFastIselFailSDiv,
"Fast isel fails on SDiv");
98 STATISTIC(NumFastIselFailFDiv,
"Fast isel fails on FDiv");
99 STATISTIC(NumFastIselFailURem,
"Fast isel fails on URem");
100 STATISTIC(NumFastIselFailSRem,
"Fast isel fails on SRem");
101 STATISTIC(NumFastIselFailFRem,
"Fast isel fails on FRem");
104 STATISTIC(NumFastIselFailAnd,
"Fast isel fails on And");
105 STATISTIC(NumFastIselFailOr,
"Fast isel fails on Or");
106 STATISTIC(NumFastIselFailXor,
"Fast isel fails on Xor");
109 STATISTIC(NumFastIselFailAlloca,
"Fast isel fails on Alloca");
110 STATISTIC(NumFastIselFailLoad,
"Fast isel fails on Load");
111 STATISTIC(NumFastIselFailStore,
"Fast isel fails on Store");
112 STATISTIC(NumFastIselFailAtomicCmpXchg,
"Fast isel fails on AtomicCmpXchg");
113 STATISTIC(NumFastIselFailAtomicRMW,
"Fast isel fails on AtomicRWM");
114 STATISTIC(NumFastIselFailFence,
"Fast isel fails on Frence");
115 STATISTIC(NumFastIselFailGetElementPtr,
"Fast isel fails on GetElementPtr");
118 STATISTIC(NumFastIselFailTrunc,
"Fast isel fails on Trunc");
119 STATISTIC(NumFastIselFailZExt,
"Fast isel fails on ZExt");
120 STATISTIC(NumFastIselFailSExt,
"Fast isel fails on SExt");
121 STATISTIC(NumFastIselFailFPTrunc,
"Fast isel fails on FPTrunc");
122 STATISTIC(NumFastIselFailFPExt,
"Fast isel fails on FPExt");
123 STATISTIC(NumFastIselFailFPToUI,
"Fast isel fails on FPToUI");
124 STATISTIC(NumFastIselFailFPToSI,
"Fast isel fails on FPToSI");
125 STATISTIC(NumFastIselFailUIToFP,
"Fast isel fails on UIToFP");
126 STATISTIC(NumFastIselFailSIToFP,
"Fast isel fails on SIToFP");
127 STATISTIC(NumFastIselFailIntToPtr,
"Fast isel fails on IntToPtr");
128 STATISTIC(NumFastIselFailPtrToInt,
"Fast isel fails on PtrToInt");
129 STATISTIC(NumFastIselFailBitCast,
"Fast isel fails on BitCast");
132 STATISTIC(NumFastIselFailICmp,
"Fast isel fails on ICmp");
133 STATISTIC(NumFastIselFailFCmp,
"Fast isel fails on FCmp");
134 STATISTIC(NumFastIselFailPHI,
"Fast isel fails on PHI");
135 STATISTIC(NumFastIselFailSelect,
"Fast isel fails on Select");
136 STATISTIC(NumFastIselFailCall,
"Fast isel fails on Call");
137 STATISTIC(NumFastIselFailShl,
"Fast isel fails on Shl");
138 STATISTIC(NumFastIselFailLShr,
"Fast isel fails on LShr");
139 STATISTIC(NumFastIselFailAShr,
"Fast isel fails on AShr");
140 STATISTIC(NumFastIselFailVAArg,
"Fast isel fails on VAArg");
141 STATISTIC(NumFastIselFailExtractElement,
"Fast isel fails on ExtractElement");
142 STATISTIC(NumFastIselFailInsertElement,
"Fast isel fails on InsertElement");
143 STATISTIC(NumFastIselFailShuffleVector,
"Fast isel fails on ShuffleVector");
144 STATISTIC(NumFastIselFailExtractValue,
"Fast isel fails on ExtractValue");
145 STATISTIC(NumFastIselFailInsertValue,
"Fast isel fails on InsertValue");
146 STATISTIC(NumFastIselFailLandingPad,
"Fast isel fails on LandingPad");
149 STATISTIC(NumFastIselFailIntrinsicCall,
"Fast isel fails on Intrinsic call");
150 STATISTIC(NumFastIselFailSAddWithOverflow,
151 "Fast isel fails on sadd.with.overflow");
152 STATISTIC(NumFastIselFailUAddWithOverflow,
153 "Fast isel fails on uadd.with.overflow");
154 STATISTIC(NumFastIselFailSSubWithOverflow,
155 "Fast isel fails on ssub.with.overflow");
156 STATISTIC(NumFastIselFailUSubWithOverflow,
157 "Fast isel fails on usub.with.overflow");
158 STATISTIC(NumFastIselFailSMulWithOverflow,
159 "Fast isel fails on smul.with.overflow");
160 STATISTIC(NumFastIselFailUMulWithOverflow,
161 "Fast isel fails on umul.with.overflow");
162 STATISTIC(NumFastIselFailFrameaddress,
"Fast isel fails on Frameaddress");
163 STATISTIC(NumFastIselFailSqrt,
"Fast isel fails on sqrt call");
164 STATISTIC(NumFastIselFailStackMap,
"Fast isel fails on StackMap call");
165 STATISTIC(NumFastIselFailPatchPoint,
"Fast isel fails on PatchPoint call");
170 cl::desc(
"Enable verbose messages in the \"fast\" "
171 "instruction selector"));
174 cl::desc(
"Enable abort calls when \"fast\" instruction selection "
175 "fails to lower an instruction: 0 disable the abort, 1 will "
176 "abort but for args, calls and terminators, 2 will also "
177 "abort for argument lowering, and 3 will never fallback "
178 "to SelectionDAG."));
182 cl::desc(
"use Machine Branch Probability Info"),
188 cl::desc(
"Only display the basic block whose name "
189 "matches this for all view-*-dags options"));
192 cl::desc(
"Pop up a window to show dags before the first "
193 "dag combine pass"));
196 cl::desc(
"Pop up a window to show dags before legalize types"));
199 cl::desc(
"Pop up a window to show dags before legalize"));
202 cl::desc(
"Pop up a window to show dags before the second "
203 "dag combine pass"));
206 cl::desc(
"Pop up a window to show dags before the post legalize types"
207 " dag combine pass"));
210 cl::desc(
"Pop up a window to show isel dags as they are selected"));
213 cl::desc(
"Pop up a window to show sched dags as they are processed"));
216 cl::desc(
"Pop up a window to show SUnit dags after they are processed"));
242 cl::desc(
"Instruction schedulers available (before register"
262 if (NewOptLevel == SavedOptLevel)
269 DEBUG(
dbgs() <<
"\nChanging optimization level for Function "
271 DEBUG(
dbgs() <<
"\tBefore: -O" << SavedOptLevel
272 <<
" ; After: -O" << NewOptLevel <<
"\n");
278 DEBUG(
dbgs() <<
"\nRestoring optimization level for Function "
281 <<
" ; After: -O" << SavedOptLevel <<
"\n");
307 "Unknown sched type!");
325 dbgs() <<
"If a target marks an instruction with "
326 "'usesCustomInserter', it must implement "
327 "TargetLowering::EmitInstrWithCustomInserter!";
335 "If a target marks an instruction with 'hasPostISelHook', "
336 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
397 if (!CE || !CE->
canTrap())
continue;
418 "-fast-isel-verbose requires -fast-isel");
420 "-fast-isel-abort > 0 requires -fast-isel");
440 AA = &getAnalysis<AliasAnalysis>();
441 LibInfo = &getAnalysis<TargetLibraryInfoWrapperPass>().getTLI();
442 GFI = Fn.
hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) :
nullptr;
452 FuncInfo->
BPI = &getAnalysis<BranchProbabilityInfo>();
460 SelectAllBasicBlocks(Fn);
474 LiveInMap.
insert(std::make_pair(LI->first, LI->second));
491 DEBUG(
dbgs() <<
"Dropping debug info for dead vreg"
497 if (LDI != LiveInMap.
end()) {
498 assert(!hasFI &&
"There's no handling of frame pointer updating here yet "
507 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
508 "Expected inlined-at fields to agree");
511 IsIndirect, LDI->second, Offset, Variable, Expr);
523 CopyUseMI = UseMI;
continue;
526 CopyUseMI =
nullptr;
break;
533 CopyUseMI->getOperand(0).getReg(), Offset, Variable, Expr);
542 for (
const auto &MBB : *
MF) {
543 if (MFI->
hasCalls() && MF->hasInlineAsm())
546 for (
const auto &
MI : MBB) {
549 MI.isStackAligningInlineAsm()) {
552 if (
MI.isInlineAsm()) {
553 MF->setHasInlineAsm(
true);
567 unsigned From =
I->first;
568 unsigned To =
I->second;
600 DEBUG(
dbgs() <<
"*** MachineFunction at end of ISel ***\n");
623 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
636 if (!VisitedNodes.
insert(N).second)
661 }
while (!Worklist.
empty());
664 void SelectionDAGISel::CodeGenAndEmitDAG() {
665 std::string GroupName;
667 GroupName =
"Instruction Selection and Scheduling";
668 std::string BlockName;
669 int BlockNumber = -1;
671 bool MatchFilterBB =
false; (void)MatchFilterBB;
687 DEBUG(
dbgs() <<
"Initial selection DAG: BB#" << BlockNumber
688 <<
" '" << BlockName <<
"'\n";
CurDAG->
dump());
699 DEBUG(
dbgs() <<
"Optimized lowered selection DAG: BB#" << BlockNumber
700 <<
" '" << BlockName <<
"'\n";
CurDAG->
dump());
713 DEBUG(
dbgs() <<
"Type-legalized selection DAG: BB#" << BlockNumber
714 <<
" '" << BlockName <<
"'\n";
CurDAG->
dump());
729 DEBUG(
dbgs() <<
"Optimized type-legalized selection DAG: BB#" << BlockNumber
730 <<
" '" << BlockName <<
"'\n";
CurDAG->
dump());
755 DEBUG(
dbgs() <<
"Optimized vector-legalized selection DAG: BB#"
756 << BlockNumber <<
" '" << BlockName <<
"'\n";
CurDAG->
dump());
767 DEBUG(
dbgs() <<
"Legalized selection DAG: BB#" << BlockNumber
768 <<
" '" << BlockName <<
"'\n";
CurDAG->
dump());
779 DEBUG(
dbgs() <<
"Optimized legalized selection DAG: BB#" << BlockNumber
780 <<
" '" << BlockName <<
"'\n";
CurDAG->
dump());
783 ComputeLiveOutVRegInfo();
792 DoInstructionSelection();
795 DEBUG(
dbgs() <<
"Selected selection DAG: BB#" << BlockNumber
796 <<
" '" << BlockName <<
"'\n";
CurDAG->
dump());
824 if (FirstMBB != LastMBB)
845 :
SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
857 void SelectionDAGISel::DoInstructionSelection() {
858 DEBUG(
dbgs() <<
"===== Instruction selection begins: BB#"
878 ISelUpdater ISU(*
CurDAG, ISelPosition);
885 SDNode *Node = --ISelPosition;
914 DEBUG(
dbgs() <<
"===== Instruction selection ends:\n");
921 bool SelectionDAGISel::PrepareEHLandingPad() {
955 if (ActionsCall && ActionsCall->
getIntrinsicID() == Intrinsic::eh_actions) {
963 InvokeBB->addSuccessor(ClauseBB);
972 InvokeBB->removeSuccessor(MBB);
995 !isa<TerminatorInst>(
I) &&
996 !isa<DbgInfoIntrinsic>(I) &&
997 !isa<LandingPadInst>(
I) &&
1008 default: assert (0 &&
"<Invalid operator> ");
1012 case Instruction::Br: NumFastIselFailBr++;
return;
1013 case Instruction::Switch: NumFastIselFailSwitch++;
return;
1014 case Instruction::IndirectBr: NumFastIselFailIndirectBr++;
return;
1015 case Instruction::Invoke: NumFastIselFailInvoke++;
return;
1016 case Instruction::Resume: NumFastIselFailResume++;
return;
1017 case Instruction::Unreachable: NumFastIselFailUnreachable++;
return;
1020 case Instruction::Add: NumFastIselFailAdd++;
return;
1021 case Instruction::FAdd: NumFastIselFailFAdd++;
return;
1022 case Instruction::Sub: NumFastIselFailSub++;
return;
1023 case Instruction::FSub: NumFastIselFailFSub++;
return;
1024 case Instruction::Mul: NumFastIselFailMul++;
return;
1025 case Instruction::FMul: NumFastIselFailFMul++;
return;
1026 case Instruction::UDiv: NumFastIselFailUDiv++;
return;
1027 case Instruction::SDiv: NumFastIselFailSDiv++;
return;
1028 case Instruction::FDiv: NumFastIselFailFDiv++;
return;
1029 case Instruction::URem: NumFastIselFailURem++;
return;
1030 case Instruction::SRem: NumFastIselFailSRem++;
return;
1031 case Instruction::FRem: NumFastIselFailFRem++;
return;
1039 case Instruction::Alloca: NumFastIselFailAlloca++;
return;
1042 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++;
return;
1043 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++;
return;
1044 case Instruction::Fence: NumFastIselFailFence++;
return;
1045 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++;
return;
1048 case Instruction::Trunc: NumFastIselFailTrunc++;
return;
1049 case Instruction::ZExt: NumFastIselFailZExt++;
return;
1050 case Instruction::SExt: NumFastIselFailSExt++;
return;
1051 case Instruction::FPTrunc: NumFastIselFailFPTrunc++;
return;
1052 case Instruction::FPExt: NumFastIselFailFPExt++;
return;
1053 case Instruction::FPToUI: NumFastIselFailFPToUI++;
return;
1054 case Instruction::FPToSI: NumFastIselFailFPToSI++;
return;
1055 case Instruction::UIToFP: NumFastIselFailUIToFP++;
return;
1056 case Instruction::SIToFP: NumFastIselFailSIToFP++;
return;
1057 case Instruction::IntToPtr: NumFastIselFailIntToPtr++;
return;
1058 case Instruction::PtrToInt: NumFastIselFailPtrToInt++;
return;
1059 case Instruction::BitCast: NumFastIselFailBitCast++;
return;
1062 case Instruction::ICmp: NumFastIselFailICmp++;
return;
1063 case Instruction::FCmp: NumFastIselFailFCmp++;
return;
1067 if (
auto const *Intrinsic = dyn_cast<IntrinsicInst>(I)) {
1068 switch (Intrinsic->getIntrinsicID()) {
1070 NumFastIselFailIntrinsicCall++;
return;
1071 case Intrinsic::sadd_with_overflow:
1072 NumFastIselFailSAddWithOverflow++;
return;
1073 case Intrinsic::uadd_with_overflow:
1074 NumFastIselFailUAddWithOverflow++;
return;
1075 case Intrinsic::ssub_with_overflow:
1076 NumFastIselFailSSubWithOverflow++;
return;
1077 case Intrinsic::usub_with_overflow:
1078 NumFastIselFailUSubWithOverflow++;
return;
1079 case Intrinsic::smul_with_overflow:
1080 NumFastIselFailSMulWithOverflow++;
return;
1081 case Intrinsic::umul_with_overflow:
1082 NumFastIselFailUMulWithOverflow++;
return;
1083 case Intrinsic::frameaddress:
1084 NumFastIselFailFrameaddress++;
return;
1085 case Intrinsic::sqrt:
1086 NumFastIselFailSqrt++;
return;
1087 case Intrinsic::experimental_stackmap:
1088 NumFastIselFailStackMap++;
return;
1089 case Intrinsic::experimental_patchpoint_void:
1090 case Intrinsic::experimental_patchpoint_i64:
1091 NumFastIselFailPatchPoint++;
return;
1094 NumFastIselFailCall++;
1097 case Instruction::Shl: NumFastIselFailShl++;
return;
1098 case Instruction::LShr: NumFastIselFailLShr++;
return;
1099 case Instruction::AShr: NumFastIselFailAShr++;
return;
1100 case Instruction::VAArg: NumFastIselFailVAArg++;
return;
1102 case Instruction::InsertElement: NumFastIselFailInsertElement++;
return;
1103 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++;
return;
1104 case Instruction::ExtractValue: NumFastIselFailExtractValue++;
return;
1105 case Instruction::InsertValue: NumFastIselFailInsertValue++;
return;
1106 case Instruction::LandingPad: NumFastIselFailLandingPad++;
return;
1111 void SelectionDAGISel::SelectAllBasicBlocks(
const Function &Fn) {
1120 I = RPOT.begin(), E = RPOT.end();
I != E; ++
I) {
1124 bool AllPredsVisited =
true;
1128 AllPredsVisited =
false;
1133 if (AllPredsVisited) {
1157 if (!PrepareEHLandingPad())
1172 ++NumFastIselFailLowerArguments;
1180 CodeGenAndEmitDAG();
1192 unsigned NumFastIselRemaining = std::distance(Begin, End);
1194 for (; BI != Begin; --BI) {
1199 --NumFastIselRemaining;
1209 --NumFastIselRemaining;
1210 ++NumFastIselSuccess;
1215 while (BeforeInst != Begin) {
1220 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1225 --NumFastIselRemaining;
1226 ++NumFastIselSuccess;
1237 if (isa<CallInst>(Inst)) {
1240 dbgs() <<
"FastISel missed call: ";
1254 bool HadTailCall =
false;
1256 SelectBasicBlock(Inst, BI, HadTailCall);
1268 unsigned RemainingNow = std::distance(Begin, BI);
1269 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1270 NumFastIselRemaining = RemainingNow;
1276 if (isa<TerminatorInst>(Inst)) {
1278 dbgs() <<
"FastISel missed terminator: ";
1282 dbgs() <<
"FastISel miss: ";
1291 NumFastIselFailures += NumFastIselRemaining;
1307 ++NumFastIselBlocks;
1314 SelectBasicBlock(Begin, BI, HadTailCall);
1364 &&
"Should have a copy implying we should have 2 arguments.");
1368 if (!OPI2->
isReg() ||
1393 if (SplitPoint == BB->
begin())
1401 SplitPoint = Previous;
1402 if (Previous == Start)
1411 SelectionDAGISel::FinishBasicBlock() {
1413 DEBUG(
dbgs() <<
"Total amount of phi nodes to update: "
1416 dbgs() <<
"Node " << i <<
" : ("
1424 assert(
PHI->isPHI() &&
1425 "This is not a machine PHI node that we are updating!");
1446 SuccessMBB->
splice(SuccessMBB->
end(), ParentMBB,
1456 CodeGenAndEmitDAG();
1460 if (!FailureMBB->
size()) {
1466 CodeGenAndEmitDAG();
1483 CodeGenAndEmitDAG();
1486 uint32_t UnhandledWeight = 0;
1487 for (
unsigned j = 0, ej =
SDB->
BitTestCases[i].Cases.size(); j != ej; ++j)
1514 CodeGenAndEmitDAG();
1522 assert(
PHI->isPHI() &&
1523 "This is not a machine PHI node that we are updating!");
1545 for (
unsigned i = 0, e =
SDB->
JTCases.size(); i != e; ++i) {
1556 CodeGenAndEmitDAG();
1566 CodeGenAndEmitDAG();
1573 assert(
PHI->isPHI() &&
1574 "This is not a machine PHI node that we are updating!");
1603 CodeGenAndEmitDAG();
1613 for (
unsigned i = 0, e = Succs.
size(); i != e; ++i) {
1621 MBBI != MBBE && MBBI->isPHI(); ++MBBI) {
1624 for (
unsigned pn = 0; ; ++pn) {
1626 "Didn't find PHI entry!");
1665 int64_t DesiredMaskS)
const {
1670 if (ActualMask == DesiredMask)
1679 APInt NeededMask = DesiredMask & ~ActualMask;
1694 int64_t DesiredMaskS)
const {
1699 if (ActualMask == DesiredMask)
1708 APInt NeededMask = DesiredMask & ~ActualMask;
1710 APInt KnownZero, KnownOne;
1714 if ((NeededMask & KnownOne) == NeededMask)
1727 std::vector<SDValue> InOps;
1736 if (InOps[e-1].getValueType() ==
MVT::Glue)
1740 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1743 Ops.insert(Ops.end(), InOps.begin()+i,
1748 "Memory operand with multiple values?");
1750 unsigned TiedToOperand;
1754 Flags = cast<ConstantSDNode>(InOps[CurOp])->getZExtValue();
1755 for (; TiedToOperand; --TiedToOperand) {
1757 Flags = cast<ConstantSDNode>(InOps[CurOp])->getZExtValue();
1762 std::vector<SDValue> SelOps;
1773 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1779 if (e != InOps.size())
1780 Ops.push_back(InOps.back());
1801 bool IgnoreChains) {
1815 if (!Visited.
insert(Use).second)
1820 if (Op.getValueType() ==
MVT::Other && IgnoreChains)
1823 SDNode *N = Op.getNode();
1825 if (Use == ImmedUse || Use == Root)
1832 if (
findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1850 bool IgnoreChains) {
1909 IgnoreChains =
false;
1917 SDNode *SelectionDAGISel::Select_INLINEASM(
SDNode *N) {
1930 *SelectionDAGISel::Select_READ_REGISTER(
SDNode *Op) {
1944 *SelectionDAGISel::Select_WRITE_REGISTER(
SDNode *Op) {
1965 GetVBR(uint64_t Val,
const unsigned char *MatcherTable,
unsigned &Idx) {
1966 assert(Val >= 128 &&
"Not a VBR");
1972 NextBits = MatcherTable[Idx++];
1973 Val |= (NextBits&127) << Shift;
1975 }
while (NextBits & 128);
1983 void SelectionDAGISel::
1984 UpdateChainsAndGlue(
SDNode *NodeToMatch,
SDValue InputChain,
1988 bool isMorphNodeTo) {
1993 if (!ChainNodesMatched.
empty()) {
1994 assert(InputChain.
getNode() &&
1995 "Matched input chains but didn't produce a chain");
1998 for (
unsigned i = 0, e = ChainNodesMatched.
size(); i != e; ++i) {
1999 SDNode *ChainNode = ChainNodesMatched[i];
2007 if (ChainNode == NodeToMatch && isMorphNodeTo)
2018 !std::count(NowDeadNodes.
begin(), NowDeadNodes.
end(), ChainNode))
2027 for (
unsigned i = 0, e = GlueResultNodesMatched.
size(); i != e; ++i) {
2028 SDNode *FRN = GlueResultNodesMatched[i];
2035 "Doesn't have a glue result");
2041 !std::count(NowDeadNodes.
begin(), NowDeadNodes.
end(), FRN))
2046 if (!NowDeadNodes.
empty())
2049 DEBUG(
dbgs() <<
"ISEL: Match complete!\n");
2074 E = ChainedNode->
use_end(); UI != E; ++UI) {
2076 if (UI.getUse().getValueType() !=
MVT::Other)
continue;
2086 unsigned UserOpcode = User->
getOpcode();
2112 if (!std::count(ChainedNodesInPattern.
begin(),
2113 ChainedNodesInPattern.
end(), User))
2151 switch (
WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
2192 for (
unsigned i = 0, e = ChainNodesMatched.
size(); i != e; ++i) {
2201 for (
unsigned i = 0, e = ChainNodesMatched.
size(); i != e; ++i) {
2204 SDNode *N = ChainNodesMatched[i];
2206 if (std::count(InteriorChainedNodes.
begin(),InteriorChainedNodes.
end(),
N))
2210 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
2219 if (!std::count(ChainNodesMatched.
begin(), ChainNodesMatched.
end(),
2225 if (InputChains.
size() == 1)
2226 return InputChains[0];
2232 SDNode *SelectionDAGISel::
2241 int OldGlueResultNo = -1, OldChainResultNo = -1;
2245 OldGlueResultNo = NTMNumResults-1;
2246 if (NTMNumResults != 1 &&
2248 OldChainResultNo = NTMNumResults-2;
2250 OldChainResultNo = NTMNumResults-1;
2268 (
unsigned)OldGlueResultNo != ResNumResults-1)
2270 SDValue(Res, ResNumResults-1));
2272 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
2276 if ((EmitNodeInfo &
OPFL_Chain) && OldChainResultNo != -1 &&
2277 (
unsigned)OldChainResultNo != ResNumResults-1)
2279 SDValue(Res, ResNumResults-1));
2291 CheckSame(
const unsigned char *MatcherTable,
unsigned &MatcherIndex,
2295 unsigned RecNo = MatcherTable[MatcherIndex++];
2296 assert(RecNo < RecordedNodes.size() &&
"Invalid CheckSame");
2297 return N == RecordedNodes[RecNo].first;
2327 CheckOpcode(
const unsigned char *MatcherTable,
unsigned &MatcherIndex,
2329 uint16_t Opc = MatcherTable[MatcherIndex++];
2330 Opc |= (
unsigned short)MatcherTable[MatcherIndex++] << 8;
2357 return cast<CondCodeSDNode>(
N)->
get() ==
2365 if (cast<VTSDNode>(N)->getVT() == VT)
2375 int64_t Val = MatcherTable[MatcherIndex++];
2377 Val =
GetVBR(Val, MatcherTable, MatcherIndex);
2385 SDValue N,
unsigned ChildNo) {
2392 CheckAndImm(
const unsigned char *MatcherTable,
unsigned &MatcherIndex,
2394 int64_t Val = MatcherTable[MatcherIndex++];
2396 Val =
GetVBR(Val, MatcherTable, MatcherIndex);
2405 CheckOrImm(
const unsigned char *MatcherTable,
unsigned &MatcherIndex,
2407 int64_t Val = MatcherTable[MatcherIndex++];
2409 Val =
GetVBR(Val, MatcherTable, MatcherIndex);
2428 switch (Table[Index++]) {
2433 Result = !
::CheckSame(Table, Index, N, RecordedNodes);
2504 unsigned NumRecordedNodes;
2507 unsigned NumMatchedMemRefs;
2510 SDValue InputChain, InputGlue;
2513 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2529 RecordedNodes(
RN), MatchScopes(MS) { }
2542 for (
auto &
I : RecordedNodes)
2543 if (
I.first.getNode() ==
N)
2546 for (
auto &
I : MatchScopes)
2547 for (
auto &J :
I.NodeStack)
2548 if (J.getNode() ==
N)
2556 unsigned TableSize) {
2593 case ISD::UNDEF:
return Select_UNDEF(NodeToMatch);
2601 NodeStack.push_back(N);
2619 SDValue InputChain, InputGlue;
2628 DEBUG(
dbgs() <<
"ISEL: Starting pattern match on root node: ";
2636 unsigned MatcherIndex = 0;
2638 if (!OpcodeOffset.empty()) {
2640 if (N.
getOpcode() < OpcodeOffset.size())
2641 MatcherIndex = OpcodeOffset[N.
getOpcode()];
2642 DEBUG(
dbgs() <<
" Initial Opcode index to " << MatcherIndex <<
"\n");
2651 unsigned CaseSize = MatcherTable[Idx++];
2653 CaseSize =
GetVBR(CaseSize, MatcherTable, Idx);
2654 if (CaseSize == 0)
break;
2657 uint16_t Opc = MatcherTable[Idx++];
2658 Opc |= (
unsigned short)MatcherTable[Idx++] << 8;
2659 if (Opc >= OpcodeOffset.size())
2660 OpcodeOffset.resize((Opc+1)*2);
2661 OpcodeOffset[Opc] = Idx;
2666 if (N.
getOpcode() < OpcodeOffset.size())
2667 MatcherIndex = OpcodeOffset[N.
getOpcode()];
2671 assert(MatcherIndex < TableSize &&
"Invalid index");
2673 unsigned CurrentOpcodeIndex = MatcherIndex;
2686 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2687 if (NumToSkip & 128)
2688 NumToSkip =
GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2690 if (NumToSkip == 0) {
2695 FailIndex = MatcherIndex+NumToSkip;
2697 unsigned MatcherIndexOfPredicate = MatcherIndex;
2698 (void)MatcherIndexOfPredicate;
2705 Result, *
this, RecordedNodes);
2709 DEBUG(
dbgs() <<
" Skipped scope entry (due to false predicate) at "
2710 <<
"index " << MatcherIndexOfPredicate
2711 <<
", continuing at " << FailIndex <<
"\n");
2712 ++NumDAGIselRetries;
2716 MatcherIndex = FailIndex;
2720 if (FailIndex == 0)
break;
2724 MatchScope NewEntry;
2725 NewEntry.FailIndex = FailIndex;
2726 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2727 NewEntry.NumRecordedNodes = RecordedNodes.
size();
2728 NewEntry.NumMatchedMemRefs = MatchedMemRefs.
size();
2729 NewEntry.InputChain = InputChain;
2730 NewEntry.InputGlue = InputGlue;
2731 NewEntry.HasChainNodesMatched = !ChainNodesMatched.
empty();
2732 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.
empty();
2738 SDNode *Parent =
nullptr;
2739 if (NodeStack.size() > 1)
2740 Parent = NodeStack[NodeStack.size()-2].getNode();
2741 RecordedNodes.
push_back(std::make_pair(N, Parent));
2758 MatchedMemRefs.
push_back(cast<MemSDNode>(N)->getMemOperand());
2769 unsigned ChildNo = MatcherTable[MatcherIndex++];
2773 NodeStack.push_back(N);
2779 NodeStack.pop_back();
2780 assert(!NodeStack.empty() &&
"Node stack imbalance!");
2781 N = NodeStack.back();
2785 if (!::
CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes))
break;
2790 if (!::
CheckChildSame(MatcherTable, MatcherIndex, N, RecordedNodes,
2804 unsigned CPNum = MatcherTable[MatcherIndex++];
2805 unsigned RecNo = MatcherTable[MatcherIndex++];
2806 assert(RecNo < RecordedNodes.
size() &&
"Invalid CheckComplexPat");
2810 std::unique_ptr<MatchStateUpdater> MSU;
2812 MSU.reset(
new MatchStateUpdater(*
CurDAG, RecordedNodes,
2816 RecordedNodes[RecNo].first, CPNum,
2822 if (!::
CheckOpcode(MatcherTable, MatcherIndex, N.getNode()))
break;
2832 unsigned CurNodeOpcode = N.getOpcode();
2833 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2837 CaseSize = MatcherTable[MatcherIndex++];
2839 CaseSize =
GetVBR(CaseSize, MatcherTable, MatcherIndex);
2840 if (CaseSize == 0)
break;
2842 uint16_t Opc = MatcherTable[MatcherIndex++];
2843 Opc |= (
unsigned short)MatcherTable[MatcherIndex++] << 8;
2846 if (CurNodeOpcode == Opc)
2850 MatcherIndex += CaseSize;
2854 if (CaseSize == 0)
break;
2857 DEBUG(
dbgs() <<
" OpcodeSwitch from " << SwitchStart
2858 <<
" to " << MatcherIndex <<
"\n");
2863 MVT CurNodeVT = N.getSimpleValueType();
2864 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2868 CaseSize = MatcherTable[MatcherIndex++];
2870 CaseSize =
GetVBR(CaseSize, MatcherTable, MatcherIndex);
2871 if (CaseSize == 0)
break;
2878 if (CurNodeVT == CaseVT)
2882 MatcherIndex += CaseSize;
2886 if (CaseSize == 0)
break;
2889 DEBUG(
dbgs() <<
" TypeSwitch[" <<
EVT(CurNodeVT).getEVTString()
2890 <<
"] from " << SwitchStart <<
" to " << MatcherIndex<<
'\n');
2911 if (!::
CheckInteger(MatcherTable, MatcherIndex, N))
break;
2920 if (!::
CheckAndImm(MatcherTable, MatcherIndex, N, *
this))
break;
2923 if (!::
CheckOrImm(MatcherTable, MatcherIndex, N, *
this))
break;
2927 assert(NodeStack.size() != 1 &&
"No parent node");
2930 bool HasMultipleUses =
false;
2931 for (
unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2932 if (!NodeStack[i].hasOneUse()) {
2933 HasMultipleUses =
true;
2936 if (HasMultipleUses)
break;
2952 int64_t Val = MatcherTable[MatcherIndex++];
2954 Val =
GetVBR(Val, MatcherTable, MatcherIndex);
2955 RecordedNodes.
push_back(std::pair<SDValue, SDNode*>(
2963 unsigned RegNo = MatcherTable[MatcherIndex++];
2964 RecordedNodes.
push_back(std::pair<SDValue, SDNode*>(
2974 unsigned RegNo = MatcherTable[MatcherIndex++];
2975 RegNo |= MatcherTable[MatcherIndex++] << 8;
2976 RecordedNodes.
push_back(std::pair<SDValue, SDNode*>(
2983 unsigned RecNo = MatcherTable[MatcherIndex++];
2984 assert(RecNo < RecordedNodes.
size() &&
"Invalid EmitConvertToTarget");
2985 SDValue Imm = RecordedNodes[RecNo].first;
2988 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue();
2992 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2994 Imm.getValueType(),
true);
2997 RecordedNodes.
push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
3004 assert(!InputChain.
getNode() &&
3005 "EmitMergeInputChains should be the first chain producing node");
3006 assert(ChainNodesMatched.
empty() &&
3007 "Should only have one EmitMergeInputChains per match");
3011 assert(RecNo < RecordedNodes.
size() &&
"Invalid EmitMergeInputChains");
3012 ChainNodesMatched.
push_back(RecordedNodes[RecNo].first.getNode());
3016 if (ChainNodesMatched.
back() != NodeToMatch &&
3017 !RecordedNodes[RecNo].first.hasOneUse()) {
3018 ChainNodesMatched.
clear();
3031 assert(!InputChain.
getNode() &&
3032 "EmitMergeInputChains should be the first chain producing node");
3039 unsigned NumChains = MatcherTable[MatcherIndex++];
3040 assert(NumChains != 0 &&
"Can't TF zero chains");
3042 assert(ChainNodesMatched.
empty() &&
3043 "Should only have one EmitMergeInputChains per match");
3046 for (
unsigned i = 0; i != NumChains; ++i) {
3047 unsigned RecNo = MatcherTable[MatcherIndex++];
3048 assert(RecNo < RecordedNodes.
size() &&
"Invalid EmitMergeInputChains");
3049 ChainNodesMatched.
push_back(RecordedNodes[RecNo].first.getNode());
3053 if (ChainNodesMatched.
back() != NodeToMatch &&
3054 !RecordedNodes[RecNo].first.hasOneUse()) {
3055 ChainNodesMatched.
clear();
3061 if (ChainNodesMatched.
empty())
3074 unsigned RecNo = MatcherTable[MatcherIndex++];
3075 assert(RecNo < RecordedNodes.
size() &&
"Invalid EmitCopyToReg");
3076 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
3082 DestPhysReg, RecordedNodes[RecNo].first,
3085 InputGlue = InputChain.
getValue(1);
3090 unsigned XFormNo = MatcherTable[MatcherIndex++];
3091 unsigned RecNo = MatcherTable[MatcherIndex++];
3092 assert(RecNo < RecordedNodes.
size() &&
"Invalid EmitNodeXForm");
3094 RecordedNodes.
push_back(std::pair<SDValue,SDNode*>(Res,
nullptr));
3100 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
3101 TargetOpc |= (
unsigned short)MatcherTable[MatcherIndex++] << 8;
3102 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
3104 unsigned NumVTs = MatcherTable[MatcherIndex++];
3106 for (
unsigned i = 0; i != NumVTs; ++i) {
3114 if (EmitNodeInfo & OPFL_Chain)
3116 if (EmitNodeInfo & OPFL_GlueOutput)
3122 if (VTs.
size() == 1)
3124 else if (VTs.
size() == 2)
3130 unsigned NumOps = MatcherTable[MatcherIndex++];
3132 for (
unsigned i = 0; i != NumOps; ++i) {
3133 unsigned RecNo = MatcherTable[MatcherIndex++];
3135 RecNo =
GetVBR(RecNo, MatcherTable, MatcherIndex);
3137 assert(RecNo < RecordedNodes.
size() &&
"Invalid EmitNode");
3138 Ops.
push_back(RecordedNodes[RecNo].first);
3145 FirstOpToCopy += (EmitNodeInfo &
OPFL_Chain) ? 1 : 0;
3147 "Invalid variadic node");
3150 for (
unsigned i = FirstOpToCopy, e = NodeToMatch->
getNumOperands();
3159 if (EmitNodeInfo & OPFL_Chain)
3173 for (
unsigned i = 0, e = VTs.
size(); i != e; ++i) {
3180 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops, EmitNodeInfo);
3184 DEBUG(
dbgs() <<
"Node was eliminated by CSE\n");
3190 if (EmitNodeInfo & OPFL_GlueOutput) {
3192 if (EmitNodeInfo & OPFL_Chain)
3194 }
else if (EmitNodeInfo & OPFL_Chain)
3207 bool mayLoad = MCID.
mayLoad();
3210 unsigned NumMemRefs = 0;
3212 MatchedMemRefs.
begin(), E = MatchedMemRefs.
end();
I != E; ++
I) {
3213 if ((*I)->isLoad()) {
3216 }
else if ((*I)->isStore()) {
3229 MatchedMemRefs.
begin(), E = MatchedMemRefs.
end();
I != E; ++
I) {
3230 if ((*I)->isLoad()) {
3233 }
else if ((*I)->isStore()) {
3241 cast<MachineSDNode>(Res)
3242 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
3252 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3253 InputGlue, GlueResultNodesMatched,
true);
3261 unsigned NumNodes = MatcherTable[MatcherIndex++];
3264 for (
unsigned i = 0; i != NumNodes; ++i) {
3265 unsigned RecNo = MatcherTable[MatcherIndex++];
3267 RecNo =
GetVBR(RecNo, MatcherTable, MatcherIndex);
3269 assert(RecNo < RecordedNodes.
size() &&
"Invalid MarkGlueResults");
3270 GlueResultNodesMatched.
push_back(RecordedNodes[RecNo].first.getNode());
3279 unsigned NumResults = MatcherTable[MatcherIndex++];
3281 for (
unsigned i = 0; i != NumResults; ++i) {
3282 unsigned ResSlot = MatcherTable[MatcherIndex++];
3284 ResSlot =
GetVBR(ResSlot, MatcherTable, MatcherIndex);
3286 assert(ResSlot < RecordedNodes.
size() &&
"Invalid CompleteMatch");
3287 SDValue Res = RecordedNodes[ResSlot].first;
3289 assert(i < NodeToMatch->getNumValues() &&
3292 "Invalid number of results to complete!");
3293 assert((NodeToMatch->
getValueType(i) == Res.getValueType() ||
3297 Res.getValueType().getSizeInBits()) &&
3298 "invalid replacement");
3304 GlueResultNodesMatched.
push_back(NodeToMatch);
3307 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3308 InputGlue, GlueResultNodesMatched,
false);
3311 "Didn't replace all uses of the node?");
3322 DEBUG(
dbgs() <<
" Match failed at index " << CurrentOpcodeIndex <<
"\n");
3323 ++NumDAGIselRetries;
3325 if (MatchScopes.
empty()) {
3326 CannotYetSelect(NodeToMatch);
3332 MatchScope &LastScope = MatchScopes.
back();
3333 RecordedNodes.
resize(LastScope.NumRecordedNodes);
3335 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
3336 N = NodeStack.back();
3338 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.
size())
3339 MatchedMemRefs.
resize(LastScope.NumMatchedMemRefs);
3340 MatcherIndex = LastScope.FailIndex;
3342 DEBUG(
dbgs() <<
" Continuing at " << MatcherIndex <<
"\n");
3344 InputChain = LastScope.InputChain;
3345 InputGlue = LastScope.InputGlue;
3346 if (!LastScope.HasChainNodesMatched)
3347 ChainNodesMatched.
clear();
3348 if (!LastScope.HasGlueResultNodesMatched)
3349 GlueResultNodesMatched.
clear();
3354 unsigned NumToSkip = MatcherTable[MatcherIndex++];
3355 if (NumToSkip & 128)
3356 NumToSkip =
GetVBR(NumToSkip, MatcherTable, MatcherIndex);
3360 if (NumToSkip != 0) {
3361 LastScope.FailIndex = MatcherIndex+NumToSkip;
3374 void SelectionDAGISel::CannotYetSelect(
SDNode *N) {
3377 Msg <<
"Cannot select: ";
3383 Msg <<
"\nIn function: " <<
MF->
getName();
3387 cast<ConstantSDNode>(N->
getOperand(HasInputChain))->getZExtValue();
3391 Msg <<
"target intrinsic %" <<
TII->
getName(iid);
3393 Msg <<
"unknown intrinsic #" << iid;
SDNode * MorphNodeTo(SDNode *N, unsigned Opc, SDVTList VTs, ArrayRef< SDValue > Ops)
This mutates the specified node to have the specified return type, opcode, and operands.
bool use_empty() const
Return true if there are no uses of this node.
std::vector< BitTestBlock > BitTestCases
BitTestCases - Vector of BitTestBlock structures used to communicate SwitchInst code generation infor...
void push_back(const T &Elt)
SelectionDAGBuilder * SDB
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N, const SelectionDAGISel &SDISel)
A parsed version of the target data layout string in and methods for querying it. ...
mop_iterator operands_end()
SDValue getValue(unsigned R) const
bool hasPostISelHook(QueryType Type=IgnoreBundle) const
Return true if this instruction requires adjustment after instruction selection by calling a target h...
static SDNode * findGlueUse(SDNode *N)
findGlueUse - Return use of MVT::Glue value produced by the specified SDNode.
void EmitLiveInCopies(MachineBasicBlock *EntryMBB, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII)
EmitLiveInCopies - Emit copies to initialize livein virtual registers into the given entry block...
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N)
virtual bool enableMachineScheduler() const
True if the subtarget should run MachineScheduler after aggressive coalescing.
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
static int getNumFixedFromVariadicInfo(unsigned Flags)
getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the number of fixed arity values ...
bool LegalizeTypes()
This transforms the SelectionDAG into a SelectionDAG that only uses types natively supported by the t...
SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N)
void dump() const
Dump this node, for debugging.
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N, const TargetLowering *TLI, const DataLayout &DL)
DELETED_NODE - This is an illegal value that is used to catch errors.
STATISTIC(NumFunctions,"Total number of functions")
MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used to reference metadata in the IR...
static unsigned virtReg2Index(unsigned Reg)
virtReg2Index - Convert a virtual register number to a 0-based index.
livein_iterator livein_end() const
static cl::opt< bool > ViewISelDAGs("view-isel-dags", cl::Hidden, cl::desc("Pop up a window to show isel dags as they are selected"))
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
unsigned EnableFastISel
EnableFastISel - This flag enables fast-path instruction selection which trades away generated code q...
int getNumber() const
getNumber - MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a M...
void setIsLandingPad(bool V=true)
setIsLandingPad - Indicates the block is a landing pad.
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
static MachineBasicBlock::iterator FindSplitPointForStackProtector(MachineBasicBlock *BB, DebugLoc DL)
Find the split point at which to splice the end of BB into its success stack protector check machine ...
Intrinsic::ID getIntrinsicID() const
getIntrinsicID - Return the intrinsic ID of this intrinsic.
void setCallSiteLandingPad(MCSymbol *Sym, ArrayRef< unsigned > Sites)
setCallSiteLandingPad - Map the landing pad's EH symbol to the call site indexes. ...
void ReplaceUses(SDValue F, SDValue T)
ReplaceUses - replace all uses of the old node F with the use of the new node T.
const DIExpression * getDebugExpression() const
Return the complex address expression referenced by this DBG_VALUE instruction.
ScheduleDAGSDNodes *(* FunctionPassCtor)(SelectionDAGISel *, CodeGenOpt::Level)
bool isReturn() const
Return true if the instruction is a return.
SelectionDAGBuilder - This is the common target-independent lowering implementation that is parameter...
bool mayStore() const
Return true if this instruction could possibly modify memory.
iterator getFirstTerminator()
getFirstTerminator - returns an iterator to the first terminator instruction of this basic block...
static unsigned getFlagWord(unsigned Kind, unsigned NumOps)
Describe properties that are true of each instruction in the target description file.
void initializeTargetLibraryInfoWrapperPassPass(PassRegistry &)
Clients of various APIs that cause global effects on the DAG can optionally implement this interface...
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
bool LegalizeVectors()
This transforms the SelectionDAG into a SelectionDAG that only uses vector math operations supported ...
void computeKnownBits(SDValue Op, APInt &KnownZero, APInt &KnownOne, unsigned Depth=0) const
Determine which bits of Op are known to be either zero or one and return them in the KnownZero/KnownO...
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
void addLiveIn(unsigned Reg)
Adds the specified register as a live in.
iterator insertAfter(iterator I, MachineInstr *MI)
Insert MI into the instruction list after I.
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, const SelectionDAGISel &SDISel)
CheckPatternPredicate - Implements OP_CheckPatternPredicate.
void visitJumpTableHeader(JumpTable &JT, JumpTableHeader &JTH, MachineBasicBlock *SwitchBB)
visitJumpTableHeader - This function emits necessary code to produce index in the JumpTable from swit...
bool NewNodesMustHaveLegalTypes
When true, additional steps are taken to ensure that getConstant() and similar functions return DAG n...
TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or anything else with this node...
std::string str() const
str - Get the contents as an std::string.
unsigned getNumOperands() const
Return the number of values used by this operation.
const Function * getParent() const
Return the enclosing method, or null if none.
unsigned getNumOperands() const
unsigned getValueSizeInBits() const
Returns the size of the value in bits.
const SDValue & getOperand(unsigned Num) const
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
unsigned GetSuccessorNumber(BasicBlock *BB, BasicBlock *Succ)
Search for the specified successor of basic block BB and return its position in the terminator instru...
RegisterPassParser class - Handle the addition of new machine passes.
void setNodeId(int Id)
Set unique node id.
const SDValue & setRoot(SDValue N)
Set the current root tag of the SelectionDAG.
void viewGraph(const std::string &Title)
Pop up a GraphViz/gv window with the DAG rendered using 'dot'.
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N, const TargetLowering *TLI, const DataLayout &DL, unsigned ChildNo)
DebugLoc getCurDebugLoc() const
virtual void AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag...
EntryToken - This is the marker used to indicate the start of a region.
static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx)
isUseOperandTiedToDef - Return true if the flag of the inline asm operand indicates it is an use oper...
const TargetLibraryInfo * LibInfo
void set(const Function &Fn, MachineFunction &MF, SelectionDAG *DAG)
set - Initialize this FunctionLoweringInfo with the given Function and its associated MachineFunction...
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag=true)
Reports a serious error, calling any installed error handler.
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
StringRef getName() const
Return a constant reference to the value's name.
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
iterator begin()
Instruction iterator methods.
void initializeBranchProbabilityInfoPass(PassRegistry &)
bool selectInstruction(const Instruction *I)
Do "fast" instruction selection for the given LLVM IR instruction and append the generated machine in...
static bool isFoldedOrDeadInstruction(const Instruction *I, FunctionLoweringInfo *FuncInfo)
isFoldedOrDeadInstruction - Return true if the specified instruction is side-effect free and is eithe...
StackProtectorDescriptor SPDescriptor
A StackProtectorDescriptor structure used to communicate stack protector information in between Selec...
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
bool isVector() const
isVector - Return true if this is a vector value type.
void visitSPDescriptorParent(StackProtectorDescriptor &SPD, MachineBasicBlock *ParentBB)
Codegen a new tail for a stack protector check ParentMBB which has had its tail spliced into a stack ...
SDValue getRoot()
getRoot - Return the current virtual root of the Selection DAG, flushing any PendingLoad items...
void clear()
Clear state and free memory necessary to make this SelectionDAG ready to process a new block...
AnalysisUsage & addRequired()
void setLastLocalValue(MachineInstr *I)
Update the position of the last instruction emitted for materializing constants for use in the curren...
MachineMemOperand - A description of a memory reference used in the backend.
void setOptLevel(CodeGenOpt::Level Level) const
Overrides the optimization level.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static bool findNonImmUse(SDNode *Use, SDNode *Def, SDNode *ImmedUse, SDNode *Root, SmallPtrSetImpl< SDNode * > &Visited, bool IgnoreChains)
findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS, int64_t DesiredMaskS) const
CheckAndMask - The isel is trying to match something like (and X, 255).
void visitSwitchCase(CaseBlock &CB, MachineBasicBlock *SwitchBB)
visitSwitchCase - Emits the necessary code to represent a single node in the binary search tree resul...
Option class for critical edge splitting.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, CodeGenOpt::Level OptLevel, bool IgnoreChains=false)
IsLegalToFold - Returns true if the specific operand node N of U can be folded during instruction sel...
T LLVM_ATTRIBUTE_UNUSED_RESULT pop_back_val()
NamedRegionTimer - This class is basically a combination of TimeRegion and Timer. ...
void AddLiveOutRegInfo(unsigned Reg, unsigned NumSignBits, const APInt &KnownZero, const APInt &KnownOne)
AddLiveOutRegInfo - Adds LiveOutInfo for a register.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
A Use represents the edge between a Value definition and its users.
static SDValue HandleMergeInputChains(SmallVectorImpl< SDNode * > &ChainNodesMatched, SelectionDAG *CurDAG)
HandleMergeInputChains - This implements the OPC_EmitMergeInputChains operation for when the pattern ...
void visitJumpTable(JumpTable &JT)
visitJumpTable - Emit JumpTable node in the current MBB
use_instr_iterator use_instr_begin(unsigned RegNo) const
const TargetLowering * TLI
#define LLVM_ATTRIBUTE_ALWAYS_INLINE
LLVM_ATTRIBUTE_ALWAYS_INLINE - On compilers where we have a directive to do so, mark a method "always...
bool isCall() const
Return true if the instruction is a call.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
CopyToReg - This node has three operands: a chain, a register number to set to this value...
Instruction * getFirstNonPHI()
Returns a pointer to the first instruction in this block that is not a PHINode instruction.
static MachinePassRegistry Registry
RegisterScheduler class - Track the registration of instruction schedulers.
const TargetRegisterClass * getRegClass(unsigned Reg) const
getRegClass - Return the register class of the specified virtual register.
void freezeReservedRegs(const MachineFunction &)
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
Reg
All possible values of the reg field in the ModR/M byte.
SDNode * SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, unsigned TableSize)
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
An analysis pass which caches information about the entire Module.
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDNode *N)
static ConstantInt * ExtractElement(Constant *V, Constant *Idx)
virtual unsigned getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Sched::Preference getSchedulingPreference() const
Return target scheduling preference.
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
INLINEASM - Represents an inline asm block.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
unsigned DAGSize
DAGSize - Size of DAG being instruction selected.
static cl::opt< bool > EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, cl::desc("Enable verbose messages in the \"fast\" ""instruction selector"))
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
defusechain_iterator - This class provides iterator support for machine operands in the function that...
unsigned AssignTopologicalOrder()
Topological-sort the AllNodes list and a assign a unique node id for each node in the DAG based on th...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
ConstantExpr - a constant value that is initialized with an expression using other constant values...
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
ScheduleDAGSDNodes * createHybridListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level)
createHybridListDAGScheduler - This creates a bottom up register pressure aware list scheduler that m...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
void initializeAliasAnalysisAnalysisGroup(PassRegistry &)
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
const APInt & getAPIntValue() const
MachinePassRegistry - Track the registration of machine passes.
void addPersonality(MachineBasicBlock *LandingPad, const Function *Personality)
addPersonality - Provide the personality function for the exception information.
TargetConstant* - Like Constant*, but the DAG does not do any folding, simplification, or lowering of the constant.
~SelectionDAGISel() override
static LLVM_ATTRIBUTE_ALWAYS_INLINE uint64_t GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx)
GetVBR - decode a vbr encoding whose top bit is set.
ScheduleDAGSDNodes * createSourceListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level OptLevel)
createBURRListDAGScheduler - This creates a bottom up list scheduler that schedules nodes in source c...
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
void init(MachineFunction &mf)
Prepare this SelectionDAG to process code in the given MachineFunction.
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
const DataLayout & getDataLayout() const
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
const BasicBlock * getBasicBlock() const
getBasicBlock - Return the LLVM basic block that this instance corresponded to originally.
UNDEF - An undefined node.
unsigned getNumIncomingValues() const
getNumIncomingValues - Return the number of incoming edges
const MachineBasicBlock * getParent() const
This corresponds to the llvm.lifetime.
MachineRegisterInfo * RegInfo
void clear()
clear - Clear out all the function-specific state.
bool isDebugValue() const
bool isImplicitDef() const
DBG_VALUE - a mapping of the llvm.dbg.value intrinsic.
unsigned getNumSuccessors() const
Return the number of successors that this terminator has.
SDNode * getNode() const
get the SDNode which holds the desired result
IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
static cl::opt< RegisterScheduler::FunctionPassCtor, false, RegisterPassParser< RegisterScheduler > > ISHeuristic("pre-RA-sched", cl::init(&createDefaultScheduler), cl::Hidden, cl::desc("Instruction schedulers available (before register"" allocation):"))
ISHeuristic command line option for instruction schedulers.
bundle_iterator< MachineInstr, instr_iterator > iterator
virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const
IsProfitableToFold - Returns true if it's profitable to fold the specific operand node N of U during ...
BasicBlock * SplitCriticalEdge(TerminatorInst *TI, unsigned SuccNum, const CriticalEdgeSplittingOptions &Options=CriticalEdgeSplittingOptions())
SplitCriticalEdge - If this edge is a critical edge, insert a new node to split the critical edge...
CriticalEdgeSplittingOptions & setMergeIdenticalEdges()
initializer< Ty > init(const Ty &Val)
virtual FastISel * createFastISel(FunctionLoweringInfo &, const TargetLibraryInfo *) const
This method returns a target specific FastISel object, or null if the target does not support "fast" ...
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
CodeGenOpt::Level OptLevel
ScheduleDAGSDNodes - A ScheduleDAG for scheduling SDNode-based DAGs.
LandingPadInst - The landingpad instruction holds all of the information necessary to generate correc...
READ_REGISTER, WRITE_REGISTER - This node represents llvm.register on the DAG, which implements the n...
static cl::opt< int > EnableFastISelAbort("fast-isel-abort", cl::Hidden, cl::desc("Enable abort calls when \"fast\" instruction selection ""fails to lower an instruction: 0 disable the abort, 1 will ""abort but for args, calls and terminators, 2 will also ""abort for argument lowering, and 3 will never fallback ""to SelectionDAG."))
std::vector< std::pair< MachineInstr *, unsigned > > PHINodesToUpdate
PHINodesToUpdate - A list of phi instructions whose operand list will be updated after processing the...
virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const
CheckNodePredicate - This function is generated by tblgen in the target.
Constant * stripPointerCasts()
bool intersects(const APInt &RHS) const
This operation tests if there are any pairs of corresponding bits between this APInt and RHS that are...
ScheduleDAGSDNodes * createVLIWDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level OptLevel)
createVLIWDAGScheduler - Scheduler for VLIW targets.
bool HasTailCall
HasTailCall - This is set to true if a call in the current block has been translated as a tail call...
static void setDefault(FunctionPassCtor C)
void Legalize()
This transforms the SelectionDAG into a SelectionDAG that is compatible with the target instruction s...
ScheduleDAGSDNodes * createDefaultScheduler(SelectionDAGISel *IS, CodeGenOpt::Level OptLevel)
createDefaultScheduler - This creates an instruction scheduler appropriate for the target...
MVT - Machine Value Type.
LLVM Basic Block Representation.
const SDValue & getOperand(unsigned i) const
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
bool canTrap() const
canTrap - Return true if evaluation of this constant could trap.
ScheduleDAGSDNodes * createBURRListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level OptLevel)
createBURRListDAGScheduler - This creates a bottom up register usage reduction list scheduler...
void Combine(CombineLevel Level, AliasAnalysis &AA, CodeGenOpt::Level OptLevel)
This iterates over the nodes in the SelectionDAG, folding certain types of nodes together, or eliminating superfluous nodes.
void removeDeadCode(MachineBasicBlock::iterator I, MachineBasicBlock::iterator E)
Remove all dead instructions between the I and E.
const char * getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
bool isIndirectDebugValue() const
A DBG_VALUE is indirect iff the first operand is a register and the second operand is an immediate...
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const MachineOperand & getOperand(unsigned i) const
APInt Or(const APInt &LHS, const APInt &RHS)
Bitwise OR function for APInt.
ConstantFP - Floating Point Values [float, double].
LandingPadInst * getLandingPadInst()
Return the landingpad instruction associated with the landing pad.
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
APInt Xor(const APInt &LHS, const APInt &RHS)
Bitwise XOR function for APInt.
Interval::pred_iterator pred_begin(Interval *I)
pred_begin/pred_end - define methods so that Intervals may be used just like BasicBlocks can with the...
EHPersonality getPersonalityType()
Classify the personality function amongst known EH styles.
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag...
void RemoveDeadNodes()
This method deletes all unreachable nodes in the SelectionDAG.
Represent the analysis usage information of a pass.
This class provides iterator support for SDUse operands that use a specific SDNode.
BasicBlock * getIncomingBlock(unsigned i) const
getIncomingBlock - Return incoming basic block number i.
SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT)
void visitBitTestCase(BitTestBlock &BB, MachineBasicBlock *NextMBB, uint32_t BranchWeightToNext, unsigned Reg, BitTestCase &B, MachineBasicBlock *SwitchBB)
visitBitTestCase - this function produces one "bit test"
bool tryToFoldLoad(const LoadInst *LI, const Instruction *FoldInst)
We're checking to see if we can fold LI into FoldInst.
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckChildInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N, unsigned ChildNo)
static unsigned getMemoryConstraintID(unsigned Flag)
void printrFull(raw_ostream &O, const SelectionDAG *G=nullptr) const
Print a SelectionDAG node and all children down to the leaves.
bool lowerArguments()
Do "fast" instruction selection for function arguments and append the machine instructions to the cur...
SDValue getTargetConstant(uint64_t Val, SDLoc DL, EVT VT, bool isOpaque=false)
virtual unsigned getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const
Return the register ID of the name passed in.
static void collectFailStats(const Instruction *I)
unsigned getOpcode() const
static cl::opt< bool > UseMBPI("use-mbpi", cl::desc("use Machine Branch Probability Info"), cl::init(true), cl::Hidden)
static void SplitCriticalSideEffectEdges(Function &Fn, AliasAnalysis *AA)
SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that may trap on it...
for(unsigned i=0, e=MI->getNumOperands();i!=e;++i)
Interval::pred_iterator pred_end(Interval *I)
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
MCSymbol * addLandingPad(MachineBasicBlock *LandingPad)
addLandingPad - Add a new panding pad.
void setHasInlineAsm(bool B)
Set a flag that indicates that the function contains inline assembly.
virtual void PostprocessISelDAG()
PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection...
void RemoveDeadNode(SDNode *N)
Remove the specified node from the system.
static cl::opt< bool > ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, cl::desc("Pop up a window to show dags before the second ""dag combine pass"))
use_iterator use_begin() const
Provide iteration support to walk over all uses of an SDNode.
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth=0) const
Return true if 'Op & Mask' is known to be zero.
unsigned ExceptionPointerVirtReg
If the current MBB is a landing pad, the exception pointer and exception selector registers are copie...
SmallPtrSet< const BasicBlock *, 4 > VisitedBBs
VisitedBBs - The set of basic blocks visited thus far by instruction selection.
static bool isMemKind(unsigned Flag)
EVT - Extended Value Type.
unsigned getExceptionPointerRegister() const
If a physical register, this returns the register that receives the exception address on entry to a l...
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N, const SelectionDAGISel &SDISel)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
pred_iterator pred_begin()
void ComputePHILiveOutRegInfo(const PHINode *)
ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination register based on the LiveOutI...
HANDLENODE node - Used as a handle for various purposes.
const SDValue & getRoot() const
Return the root tag of the SelectionDAG.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
MachineBasicBlock * MBB
MBB - The current block.
bool mayWriteToMemory() const
mayWriteToMemory - Return true if this instruction may modify memory.
std::vector< NodeType * >::reverse_iterator rpo_iterator
virtual bool enableMachineSchedDefaultSched() const
True if the machine scheduler should disable the TLI preference for preRA scheduling with the source ...
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
void dump() const
Support for debugging, callable in GDB: V->dump()
TargetIntrinsicInfo - Interface to description of machine instruction set.
static cl::opt< bool > ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, cl::desc("Pop up a window to show dags before the first ""dag combine pass"))
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N)
void recomputeInsertPt()
Reset InsertPt to prepare for inserting instructions into the current block.
virtual SDNode * Select(SDNode *N)=0
Select - Main hook targets implement to select a node.
bool hasCalls() const
Return true if the current function has any function calls.
TokenFactor - This node takes multiple tokens as input and produces a single token result...
void visitSPDescriptorFailure(StackProtectorDescriptor &SPD)
Codegen the failure basic block for a stack protector check.
const MDOperand & getOperand(unsigned I) const
virtual MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
const DILocalVariable * getDebugVariable() const
Return the debug variable referenced by this DBG_VALUE instruction.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
This is the shared class of boolean and integer constants.
ScheduleDAGSDNodes * createILPListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level)
createILPListDAGScheduler - This creates a bottom up register pressure aware list scheduler that trie...
allnodes_const_iterator allnodes_begin() const
Value * getIncomingValue(unsigned i) const
getIncomingValue - Return incoming value number x
static FunctionPassCtor getDefault()
DenseMap< unsigned, unsigned > RegFixups
RegFixups - Registers which need to be replaced after isel is done.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
SDNode * SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT)
These are used for target selectors to mutate the specified node to have the specified return type...
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
SmallVector< MachineInstr *, 8 > ArgDbgValues
ArgDbgValues - A list of DBG_VALUE instructions created during isel for function arguments that are i...
Module.h This file contains the declarations for the Module class.
Type * getType() const
All values are typed, get the type of this value.
void clear()
clear - Clear out the current SelectionDAG and the associated state and prepare this SelectionDAGBuil...
virtual const TargetLowering * getTargetLowering() const
void setFastISel(bool Enable)
SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL=CodeGenOpt::Default)
bool isSuccessor(const MachineBasicBlock *MBB) const
isSuccessor - Return true if the specified MBB is a successor of this block.
void visit(const Instruction &I)
bool mayLoad() const
Return true if this instruction could possibly read memory.
livein_iterator livein_begin() const
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, const SelectionDAGISel &SDISel, SDNode *N)
CheckNodePredicate - Implements OP_CheckNodePredicate.
Represents one node in the SelectionDAG.
const BasicBlock & getEntryBlock() const
virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N, unsigned PatternNo, SmallVectorImpl< std::pair< SDValue, SDNode * > > &Result)
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
void UpdateSplitBlock(MachineBasicBlock *First, MachineBasicBlock *Last)
UpdateSplitBlock - When an MBB was split during scheduling, update the references that need to refer ...
static cl::opt< bool > ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, cl::desc("Pop up a window to show dags before legalize types"))
unsigned CreateRegs(Type *Ty)
CreateRegs - Allocate the appropriate number of virtual registers of the correctly promoted or expand...
void startNewBlock()
Set the current block to which generated machine instructions will be appended, and clear the local C...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
static cl::opt< bool > ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, cl::desc("Pop up a window to show dags before legalize"))
StringRef getName() const
getName - Return the name of the corresponding LLVM basic block, or "(null)".
Class for arbitrary precision integers.
static bool MIIsInTerminatorSequence(const MachineInstr *MI)
Given that the input MI is before a partial terminator sequence TSeq, return true if M + TSeq also a ...
static unsigned IsPredicateKnownToFail(const unsigned char *Table, unsigned Index, SDValue N, bool &Result, const SelectionDAGISel &SDISel, SmallVectorImpl< std::pair< SDValue, SDNode * > > &RecordedNodes)
IsPredicateKnownToFail - If we know how and can do so without pushing a scope, evaluate the current n...
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
BranchProbabilityInfo * BPI
machine Machine Instruction Scheduler
Function must not be optimized.
int64_t getSExtValue() const
op_iterator op_begin() const
This file defines the FastISel class.
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
Return the register class that should be used for the specified value type.
static use_iterator use_end()
std::vector< JumpTableBlock > JTCases
JTCases - Vector of JumpTable structures used to communicate SwitchInst code generation information...
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
bool hasGC() const
hasGC/getGC/setGC/clearGC - The name of the garbage collection algorithm to use during code generatio...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
void replaceRegWith(unsigned FromReg, unsigned ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckChildSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N, const SmallVectorImpl< std::pair< SDValue, SDNode * > > &RecordedNodes, unsigned ChildNo)
CheckChildSame - Implements OP_CheckChildXSame.
iterator_range< value_op_iterator > op_values() const
APInt And(const APInt &LHS, const APInt &RHS)
Bitwise AND function for APInt.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
TargetSubtargetInfo - Generic base class for all target subtargets.
Representation of each machine instruction.
static ChainResult WalkChainUsers(const SDNode *ChainedNode, SmallVectorImpl< SDNode * > &ChainedNodesInPattern, SmallVectorImpl< SDNode * > &InteriorChainedNodes)
WalkChainUsers - Walk down the users of the specified chained node that is part of the pattern we're ...
static bool isPhysicalRegister(unsigned Reg)
isPhysicalRegister - Return true if the specified register number is in the physical register namespa...
Represents a use of a SDNode.
unsigned ExceptionSelectorVirtReg
Analysis pass providing branch probability information.
Bitwise operators - logical and, logical or, logical xor.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
std::string getName(ID id, ArrayRef< Type * > Tys=None)
Return the LLVM name for an intrinsic, such as "llvm.ppc.altivec.lvx".
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Constant * getPersonalityFn() const
virtual const TargetIntrinsicInfo * getIntrinsicInfo() const
If intrinsic information is available, return it. If not, return null.
void SelectInlineAsmMemoryOperands(std::vector< SDValue > &Ops, SDLoc DL)
SelectInlineAsmMemoryOperands - Calls to this are automatically generated by tblgen.
virtual void viewGraph(const Twine &Name, const Twine &Title)
viewGraph - Pop up a GraphViz/gv window with the ScheduleDAG rendered using 'dot'.
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
void ReplaceAllUsesWith(SDValue From, SDValue Op)
Modify anything using 'From' to use 'To' instead.
void initializeGCModuleInfoPass(PassRegistry &)
static cl::opt< bool > ViewSUnitDAGs("view-sunit-dags", cl::Hidden, cl::desc("Pop up a window to show SUnit dags after they are processed"))
TerminatorInst * getTerminator()
Returns the terminator instruction if the block is well formed or null if the block is not well forme...
bool isLandingPad() const
Return true if this basic block is a landing pad.
bool hasOneUse() const
Return true if there is exactly one user of this value.
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
bool callsFunctionThatReturnsTwice() const
callsFunctionThatReturnsTwice - Return true if the function has a call to setjmp or other function th...
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
void clearKillFlags(unsigned Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
iterator find(const KeyT &Val)
MachineBasicBlock::iterator InsertPt
MBB - The current insert position inside the current block.
op_iterator op_end() const
void Run(SelectionDAG *dag, MachineBasicBlock *bb)
Run - perform scheduling.
MachineSDNode * getMachineNode(unsigned Opcode, SDLoc dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s), MachineInstr opcode, and operands.
OptLevelChanger(SelectionDAGISel &ISel, CodeGenOpt::Level NewOptLevel)
iterator getFirstNonPHI()
Returns a pointer to the first instruction in this block that is not a PHINode instruction.
bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS, int64_t DesiredMaskS) const
CheckOrMask - The isel is trying to match something like (or X, 255).
int getNodeId() const
Return the unique node id.
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
EVT getValueType() const
Return the ValueType of the referenced return value.
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, std::vector< SDValue > &OutOps)
SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode...
SDValue getConstant(uint64_t Val, SDLoc DL, EVT VT, bool isTarget=false, bool isOpaque=false)
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N, const TargetLowering *TLI, const DataLayout &DL)
std::vector< std::pair< unsigned, unsigned > >::const_iterator livein_iterator
unsigned getReg() const
getReg - Returns the register number.
const MDNode * getMD() const
virtual bool CheckPatternPredicate(unsigned PredNo) const
CheckPatternPredicate - This function is generated by tblgen in the target.
This class is used to form a handle around another node that is persistent and is updated across invo...
A raw_ostream that writes to an std::string.
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
void InvalidatePHILiveOutRegInfo(const PHINode *PN)
InvalidatePHILiveOutRegInfo - Invalidates a PHI's LiveOutInfo, to be called when a block is visited b...
virtual const TargetInstrInfo * getInstrInfo() const
SDValue getRegister(unsigned Reg, EVT VT)
succ_range successors(BasicBlock *BB)
mop_iterator operands_begin()
void init(GCFunctionInfo *gfi, AliasAnalysis &aa, const TargetLibraryInfo *li)
unsigned getOpcode() const
getOpcode() returns a member of one of the enums like Instruction::Add.
virtual MachineBasicBlock * EmitSchedule(MachineBasicBlock::iterator &InsertPos)
EmitSchedule - Insert MachineInstrs into the MachineBasicBlock according to the order specified in Se...
static use_instr_iterator use_instr_end()
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N, const SmallVectorImpl< std::pair< SDValue, SDNode * > > &RecordedNodes)
CheckSame - Implements OP_CheckSame.
unsigned ComputeNumSignBits(SDValue Op, unsigned Depth=0) const
Return the number of times the sign bit of the register is replicated into the other bits...
static cl::opt< bool > ViewSchedDAGs("view-sched-dags", cl::Hidden, cl::desc("Pop up a window to show sched dags as they are processed"))
std::vector< CaseBlock > SwitchCases
SwitchCases - Vector of CaseBlock structures used to communicate SwitchInst code generation informati...
void ReplaceAllUsesOfValueWith(SDValue From, SDValue To)
Replace any uses of From with To, leaving uses of other values produced by From.Val alone...
Primary interface to the complete machine description for the target machine.
DenseMap< const BasicBlock *, MachineBasicBlock * > MBBMap
MBBMap - A mapping from LLVM basic blocks to their machine code entry.
SDValue getControlRoot()
getControlRoot - Similar to getRoot, but instead of flushing all the PendingLoad items, flush all the PendingExports items.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
MachineModuleInfo & getMMI() const
void clearDanglingDebugInfo()
clearDanglingDebugInfo - Clear the dangling debug information map.
virtual void PreprocessISelDAG()
PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts...
SDValue getConstantFP(double Val, SDLoc DL, EVT VT, bool isTarget=false)
static cl::opt< bool > EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden, cl::desc("Enable extra verbose messages in the \"fast\" ""instruction selector"))
DenseMap< MachineBasicBlock *, SmallVector< unsigned, 4 > > LPadToCallSiteMap
LPadToCallSiteMap - Map a landing pad to the call site indexes.
unsigned getExceptionSelectorRegister() const
If a physical register, this returns the register that receives the exception typeid on entry to a la...
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
iterator getFirstInsertionPt()
Returns an iterator to the first instruction in this block that is suitable for inserting a non-PHI i...
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
bool TimePassesIsEnabled
If the user specifies the -time-passes argument on an LLVM tool command line then the value of this b...
SDNode * getUser()
This returns the SDNode that contains this Use.
virtual bool ComplexPatternFuncMutatesDAG() const
Return true if complex patterns for this target can mutate the DAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
static cl::opt< std::string > FilterDAGBasicBlockName("filter-view-dags", cl::Hidden, cl::desc("Only display the basic block whose name ""matches this for all view-*-dags options"))
const TargetInstrInfo * TII
DenseMap< const Value *, unsigned > ValueMap
ValueMap - Since we emit code for the function a basic block at a time, we must remember which virtua...
MachineInstr::mmo_iterator allocateMemRefsArray(unsigned long Num)
allocateMemRefsArray - Allocate an array to hold MachineMemOperand pointers.
void visitBitTestHeader(BitTestBlock &B, MachineBasicBlock *SwitchBB)
visitBitTestHeader - This function emits necessary code to produce value suitable for "bit tests" ...
const BasicBlock * getParent() const
bool isExportedInst(const Value *V)
isExportedInst - Return true if the specified value is an instruction exported from its block...
unsigned getResNo() const
Convenience function for get().getResNo().
bool isMSVCEHPersonality(EHPersonality Pers)
Returns true if this is an MSVC personality function.
FunctionLoweringInfo * FuncInfo
static cl::opt< bool > ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, cl::desc("Pop up a window to show dags before the post legalize types"" dag combine pass"))
static RegisterScheduler defaultListDAGScheduler("default","Best scheduler for the target", createDefaultScheduler)
bool isMachineOpcode() const
Test if this node has a post-isel opcode, directly corresponding to a MachineInstr opcode...
IntrinsicInst - A useful wrapper class for inspecting calls to intrinsic functions.
This file describes how to lower LLVM code to machine code.
virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo)
bool isVoidTy() const
isVoidTy - Return true if this is 'void'.
bool use_empty(unsigned RegNo) const
use_empty - Return true if there are no instructions using the specified register.
This class is used by SelectionDAGISel to temporarily override the optimization level on a per-functi...