LLVM  3.7.0
MipsMCTargetDesc.h
Go to the documentation of this file.
1 //===-- MipsMCTargetDesc.h - Mips Target Descriptions -----------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides Mips specific target descriptions.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCTARGETDESC_H
15 #define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCTARGETDESC_H
16 
17 #include "llvm/Support/DataTypes.h"
18 
19 namespace llvm {
20 class MCAsmBackend;
21 class MCCodeEmitter;
22 class MCContext;
23 class MCInstrInfo;
24 class MCObjectWriter;
25 class MCRegisterInfo;
26 class MCSubtargetInfo;
27 class StringRef;
28 class Target;
29 class Triple;
30 class raw_ostream;
32 
33 extern Target TheMipsTarget;
37 
39  const MCRegisterInfo &MRI,
40  MCContext &Ctx);
42  const MCRegisterInfo &MRI,
43  MCContext &Ctx);
44 
46  const MCRegisterInfo &MRI,
47  const Triple &TT, StringRef CPU);
49  const MCRegisterInfo &MRI,
50  const Triple &TT, StringRef CPU);
52  const MCRegisterInfo &MRI,
53  const Triple &TT, StringRef CPU);
55  const MCRegisterInfo &MRI,
56  const Triple &TT, StringRef CPU);
57 
59  bool IsLittleEndian, bool Is64Bit);
60 
61 namespace MIPS_MC {
62 StringRef selectMipsCPU(const Triple &TT, StringRef CPU);
63 }
64 
65 } // End llvm namespace
66 
67 // Defines symbolic names for Mips registers. This defines a mapping from
68 // register name to register number.
69 #define GET_REGINFO_ENUM
70 #include "MipsGenRegisterInfo.inc"
71 
72 // Defines symbolic names for the Mips instructions.
73 #define GET_INSTRINFO_ENUM
74 #include "MipsGenInstrInfo.inc"
75 
76 #define GET_SUBTARGETINFO_ENUM
77 #include "MipsGenSubtargetInfo.inc"
78 
79 #endif
MCAsmBackend * createMipsAsmBackendEL32(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU)
Defines the object file and target independent interfaces used by the assembler backend to write nati...
Context object for machine code objects.
Definition: MCContext.h:48
Target TheMips64elTarget
MCAsmBackend * createMipsAsmBackendEB32(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU)
MCCodeEmitter * createMipsMCCodeEmitterEL(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
Target TheMips64Target
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:23
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
StringRef selectMipsCPU(const Triple &TT, StringRef CPU)
Select the Mips CPU for the given triple and cpu name.
MCObjectWriter * createMipsELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI, bool IsLittleEndian, bool Is64Bit)
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
MCAsmBackend * createMipsAsmBackendEL64(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU)
Target - Wrapper for Target specific information.
MCCodeEmitter * createMipsMCCodeEmitterEB(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
MCAsmBackend * createMipsAsmBackendEB64(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU)
Target TheMipselTarget
An abstract base class for streams implementations that also support a pwrite operation.
Definition: raw_ostream.h:321
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:34
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:40
Target TheMipsTarget