LLVM  3.7.0
HexagonBitTracker.cpp
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1 //===--- HexagonBitTracker.cpp --------------------------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
11 #include "llvm/IR/Module.h"
12 #include "llvm/Support/Debug.h"
14 
15 #include "Hexagon.h"
16 #include "HexagonInstrInfo.h"
17 #include "HexagonRegisterInfo.h"
18 #include "HexagonTargetMachine.h"
19 #include "HexagonBitTracker.h"
20 
21 using namespace llvm;
22 
23 typedef BitTracker BT;
24 
27  const HexagonInstrInfo &tii,
28  MachineFunction &mf)
29  : MachineEvaluator(tri, mri), MF(mf), MFI(*mf.getFrameInfo()), TII(tii) {
30  // Populate the VRX map (VR to extension-type).
31  // Go over all the formal parameters of the function. If a given parameter
32  // P is sign- or zero-extended, locate the virtual register holding that
33  // parameter and create an entry in the VRX map indicating the type of ex-
34  // tension (and the source type).
35  // This is a bit complicated to do accurately, since the memory layout in-
36  // formation is necessary to precisely determine whether an aggregate para-
37  // meter will be passed in a register or in memory. What is given in MRI
38  // is the association between the physical register that is live-in (i.e.
39  // holds an argument), and the virtual register that this value will be
40  // copied into. This, by itself, is not sufficient to map back the virtual
41  // register to a formal parameter from Function (since consecutive live-ins
42  // from MRI may not correspond to consecutive formal parameters from Func-
43  // tion). To avoid the complications with in-memory arguments, only consi-
44  // der the initial sequence of formal parameters that are known to be
45  // passed via registers.
46  unsigned AttrIdx = 0;
47  unsigned InVirtReg, InPhysReg = 0;
48  const Function &F = *MF.getFunction();
49  typedef Function::const_arg_iterator arg_iterator;
50  for (arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
51  AttrIdx++;
52  const Argument &Arg = *I;
53  Type *ATy = Arg.getType();
54  unsigned Width = 0;
55  if (ATy->isIntegerTy())
56  Width = ATy->getIntegerBitWidth();
57  else if (ATy->isPointerTy())
58  Width = 32;
59  // If pointer size is not set through target data, it will default to
60  // Module::AnyPointerSize.
61  if (Width == 0 || Width > 64)
62  break;
63  InPhysReg = getNextPhysReg(InPhysReg, Width);
64  if (!InPhysReg)
65  break;
66  InVirtReg = getVirtRegFor(InPhysReg);
67  if (!InVirtReg)
68  continue;
69  AttributeSet Attrs = F.getAttributes();
70  if (Attrs.hasAttribute(AttrIdx, Attribute::SExt))
71  VRX.insert(std::make_pair(InVirtReg, ExtType(ExtType::SExt, Width)));
72  else if (Attrs.hasAttribute(AttrIdx, Attribute::ZExt))
73  VRX.insert(std::make_pair(InVirtReg, ExtType(ExtType::ZExt, Width)));
74  }
75 }
76 
77 
78 BT::BitMask HexagonEvaluator::mask(unsigned Reg, unsigned Sub) const {
79  if (Sub == 0)
80  return MachineEvaluator::mask(Reg, 0);
81  using namespace Hexagon;
82  const TargetRegisterClass *RC = MRI.getRegClass(Reg);
83  unsigned ID = RC->getID();
84  uint16_t RW = getRegBitWidth(RegisterRef(Reg, Sub));
85  switch (ID) {
86  case DoubleRegsRegClassID:
87  return (Sub == subreg_loreg) ? BT::BitMask(0, RW-1)
88  : BT::BitMask(RW, 2*RW-1);
89  default:
90  break;
91  }
92 #ifndef NDEBUG
93  dbgs() << PrintReg(Reg, &TRI, Sub) << '\n';
94 #endif
95  llvm_unreachable("Unexpected register/subregister");
96 }
97 
98 
99 namespace {
100  struct RegisterRefs : public std::vector<BT::RegisterRef> {
101  typedef std::vector<BT::RegisterRef> Base;
102  RegisterRefs(const MachineInstr *MI);
103  const BT::RegisterRef &operator[](unsigned n) const {
104  // The main purpose of this operator is to assert with bad argument.
105  assert(n < size());
106  return Base::operator[](n);
107  }
108  };
109 
110  RegisterRefs::RegisterRefs(const MachineInstr *MI)
111  : Base(MI->getNumOperands()) {
112  for (unsigned i = 0, n = size(); i < n; ++i) {
113  const MachineOperand &MO = MI->getOperand(i);
114  if (MO.isReg())
115  at(i) = BT::RegisterRef(MO);
116  // For indices that don't correspond to registers, the entry will
117  // remain constructed via the default constructor.
118  }
119  }
120 }
121 
122 
124  const CellMapType &Inputs, CellMapType &Outputs) const {
125  unsigned NumDefs = 0;
126 
127  // Sanity verification: there should not be any defs with subregisters.
128  for (unsigned i = 0, n = MI->getNumOperands(); i < n; ++i) {
129  const MachineOperand &MO = MI->getOperand(i);
130  if (!MO.isReg() || !MO.isDef())
131  continue;
132  NumDefs++;
133  assert(MO.getSubReg() == 0);
134  }
135 
136  if (NumDefs == 0)
137  return false;
138 
139  if (MI->mayLoad())
140  return evaluateLoad(MI, Inputs, Outputs);
141 
142  // Check COPY instructions that copy formal parameters into virtual
143  // registers. Such parameters can be sign- or zero-extended at the
144  // call site, and we should take advantage of this knowledge. The MRI
145  // keeps a list of pairs of live-in physical and virtual registers,
146  // which provides information about which virtual registers will hold
147  // the argument values. The function will still contain instructions
148  // defining those virtual registers, and in practice those are COPY
149  // instructions from a physical to a virtual register. In such cases,
150  // applying the argument extension to the virtual register can be seen
151  // as simply mirroring the extension that had already been applied to
152  // the physical register at the call site. If the defining instruction
153  // was not a COPY, it would not be clear how to mirror that extension
154  // on the callee's side. For that reason, only check COPY instructions
155  // for potential extensions.
156  if (MI->isCopy()) {
157  if (evaluateFormalCopy(MI, Inputs, Outputs))
158  return true;
159  }
160 
161  // Beyond this point, if any operand is a global, skip that instruction.
162  // The reason is that certain instructions that can take an immediate
163  // operand can also have a global symbol in that operand. To avoid
164  // checking what kind of operand a given instruction has individually
165  // for each instruction, do it here. Global symbols as operands gene-
166  // rally do not provide any useful information.
167  for (unsigned i = 0, n = MI->getNumOperands(); i < n; ++i) {
168  const MachineOperand &MO = MI->getOperand(i);
169  if (MO.isGlobal() || MO.isBlockAddress() || MO.isSymbol() || MO.isJTI() ||
170  MO.isCPI())
171  return false;
172  }
173 
174  RegisterRefs Reg(MI);
175  unsigned Opc = MI->getOpcode();
176  using namespace Hexagon;
177  #define op(i) MI->getOperand(i)
178  #define rc(i) RegisterCell::ref(getCell(Reg[i],Inputs))
179  #define im(i) MI->getOperand(i).getImm()
180 
181  // If the instruction has no register operands, skip it.
182  if (Reg.size() == 0)
183  return false;
184 
185  // Record result for register in operand 0.
186  auto rr0 = [this,Reg] (const BT::RegisterCell &Val, CellMapType &Outputs)
187  -> bool {
188  putCell(Reg[0], Val, Outputs);
189  return true;
190  };
191  // Get the cell corresponding to the N-th operand.
192  auto cop = [this,Reg,MI,Inputs] (unsigned N, uint16_t W)
193  -> BT::RegisterCell {
194  const MachineOperand &Op = MI->getOperand(N);
195  if (Op.isImm())
196  return eIMM(Op.getImm(), W);
197  if (!Op.isReg())
198  return RegisterCell::self(0, W);
199  assert(getRegBitWidth(Reg[N]) == W && "Register width mismatch");
200  return rc(N);
201  };
202  // Extract RW low bits of the cell.
203  auto lo = [this] (const BT::RegisterCell &RC, uint16_t RW)
204  -> BT::RegisterCell {
205  assert(RW <= RC.width());
206  return eXTR(RC, 0, RW);
207  };
208  // Extract RW high bits of the cell.
209  auto hi = [this] (const BT::RegisterCell &RC, uint16_t RW)
210  -> BT::RegisterCell {
211  uint16_t W = RC.width();
212  assert(RW <= W);
213  return eXTR(RC, W-RW, W);
214  };
215  // Extract N-th halfword (counting from the least significant position).
216  auto half = [this] (const BT::RegisterCell &RC, unsigned N)
217  -> BT::RegisterCell {
218  assert(N*16+16 <= RC.width());
219  return eXTR(RC, N*16, N*16+16);
220  };
221  // Shuffle bits (pick even/odd from cells and merge into result).
222  auto shuffle = [this] (const BT::RegisterCell &Rs, const BT::RegisterCell &Rt,
223  uint16_t BW, bool Odd) -> BT::RegisterCell {
224  uint16_t I = Odd, Ws = Rs.width();
225  assert(Ws == Rt.width());
226  RegisterCell RC = eXTR(Rt, I*BW, I*BW+BW).cat(eXTR(Rs, I*BW, I*BW+BW));
227  I += 2;
228  while (I*BW < Ws) {
229  RC.cat(eXTR(Rt, I*BW, I*BW+BW)).cat(eXTR(Rs, I*BW, I*BW+BW));
230  I += 2;
231  }
232  return RC;
233  };
234 
235  // The bitwidth of the 0th operand. In most (if not all) of the
236  // instructions below, the 0th operand is the defined register.
237  // Pre-compute the bitwidth here, because it is needed in many cases
238  // cases below.
239  uint16_t W0 = (Reg[0].Reg != 0) ? getRegBitWidth(Reg[0]) : 0;
240 
241  switch (Opc) {
242  // Transfer immediate:
243 
244  case A2_tfrsi:
245  case A2_tfrpi:
246  case CONST32:
247  case CONST32_Float_Real:
248  case CONST32_Int_Real:
249  case CONST64_Float_Real:
250  case CONST64_Int_Real:
251  return rr0(eIMM(im(1), W0), Outputs);
252  case TFR_PdFalse:
253  return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::Zero), Outputs);
254  case TFR_PdTrue:
255  return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::One), Outputs);
256  case TFR_FI: {
257  int FI = op(1).getIndex();
258  int Off = op(2).getImm();
259  unsigned A = MFI.getObjectAlignment(FI) + std::abs(Off);
260  unsigned L = Log2_32(A);
261  RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0);
262  RC.fill(0, L, BT::BitValue::Zero);
263  return rr0(RC, Outputs);
264  }
265 
266  // Transfer register:
267 
268  case A2_tfr:
269  case A2_tfrp:
270  case C2_pxfer_map:
271  return rr0(rc(1), Outputs);
272  case C2_tfrpr: {
273  uint16_t RW = W0;
274  uint16_t PW = 8; // XXX Pred size: getRegBitWidth(Reg[1]);
275  assert(PW <= RW);
276  RegisterCell PC = eXTR(rc(1), 0, PW);
277  RegisterCell RC = RegisterCell(RW).insert(PC, BT::BitMask(0, PW-1));
278  RC.fill(PW, RW, BT::BitValue::Zero);
279  return rr0(RC, Outputs);
280  }
281  case C2_tfrrp: {
282  RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0);
283  W0 = 8; // XXX Pred size
284  return rr0(eINS(RC, eXTR(rc(1), 0, W0), 0), Outputs);
285  }
286 
287  // Arithmetic:
288 
289  case A2_abs:
290  case A2_absp:
291  // TODO
292  break;
293 
294  case A2_addsp: {
295  uint16_t W1 = getRegBitWidth(Reg[1]);
296  assert(W0 == 64 && W1 == 32);
297  RegisterCell CW = RegisterCell(W0).insert(rc(1), BT::BitMask(0, W1-1));
298  RegisterCell RC = eADD(eSXT(CW, W1), rc(2));
299  return rr0(RC, Outputs);
300  }
301  case A2_add:
302  case A2_addp:
303  return rr0(eADD(rc(1), rc(2)), Outputs);
304  case A2_addi:
305  return rr0(eADD(rc(1), eIMM(im(2), W0)), Outputs);
306  case S4_addi_asl_ri: {
307  RegisterCell RC = eADD(eIMM(im(1), W0), eASL(rc(2), im(3)));
308  return rr0(RC, Outputs);
309  }
310  case S4_addi_lsr_ri: {
311  RegisterCell RC = eADD(eIMM(im(1), W0), eLSR(rc(2), im(3)));
312  return rr0(RC, Outputs);
313  }
314  case S4_addaddi: {
315  RegisterCell RC = eADD(rc(1), eADD(rc(2), eIMM(im(3), W0)));
316  return rr0(RC, Outputs);
317  }
318  case M4_mpyri_addi: {
319  RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
320  RegisterCell RC = eADD(eIMM(im(1), W0), lo(M, W0));
321  return rr0(RC, Outputs);
322  }
323  case M4_mpyrr_addi: {
324  RegisterCell M = eMLS(rc(2), rc(3));
325  RegisterCell RC = eADD(eIMM(im(1), W0), lo(M, W0));
326  return rr0(RC, Outputs);
327  }
328  case M4_mpyri_addr_u2: {
329  RegisterCell M = eMLS(eIMM(im(2), W0), rc(3));
330  RegisterCell RC = eADD(rc(1), lo(M, W0));
331  return rr0(RC, Outputs);
332  }
333  case M4_mpyri_addr: {
334  RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
335  RegisterCell RC = eADD(rc(1), lo(M, W0));
336  return rr0(RC, Outputs);
337  }
338  case M4_mpyrr_addr: {
339  RegisterCell M = eMLS(rc(2), rc(3));
340  RegisterCell RC = eADD(rc(1), lo(M, W0));
341  return rr0(RC, Outputs);
342  }
343  case S4_subaddi: {
344  RegisterCell RC = eADD(rc(1), eSUB(eIMM(im(2), W0), rc(3)));
345  return rr0(RC, Outputs);
346  }
347  case M2_accii: {
348  RegisterCell RC = eADD(rc(1), eADD(rc(2), eIMM(im(3), W0)));
349  return rr0(RC, Outputs);
350  }
351  case M2_acci: {
352  RegisterCell RC = eADD(rc(1), eADD(rc(2), rc(3)));
353  return rr0(RC, Outputs);
354  }
355  case M2_subacc: {
356  RegisterCell RC = eADD(rc(1), eSUB(rc(2), rc(3)));
357  return rr0(RC, Outputs);
358  }
359  case S2_addasl_rrri: {
360  RegisterCell RC = eADD(rc(1), eASL(rc(2), im(3)));
361  return rr0(RC, Outputs);
362  }
363  case C4_addipc: {
364  RegisterCell RPC = RegisterCell::self(Reg[0].Reg, W0);
365  RPC.fill(0, 2, BT::BitValue::Zero);
366  return rr0(eADD(RPC, eIMM(im(2), W0)), Outputs);
367  }
368  case A2_sub:
369  case A2_subp:
370  return rr0(eSUB(rc(1), rc(2)), Outputs);
371  case A2_subri:
372  return rr0(eSUB(eIMM(im(1), W0), rc(2)), Outputs);
373  case S4_subi_asl_ri: {
374  RegisterCell RC = eSUB(eIMM(im(1), W0), eASL(rc(2), im(3)));
375  return rr0(RC, Outputs);
376  }
377  case S4_subi_lsr_ri: {
378  RegisterCell RC = eSUB(eIMM(im(1), W0), eLSR(rc(2), im(3)));
379  return rr0(RC, Outputs);
380  }
381  case M2_naccii: {
382  RegisterCell RC = eSUB(rc(1), eADD(rc(2), eIMM(im(3), W0)));
383  return rr0(RC, Outputs);
384  }
385  case M2_nacci: {
386  RegisterCell RC = eSUB(rc(1), eADD(rc(2), rc(3)));
387  return rr0(RC, Outputs);
388  }
389  // 32-bit negation is done by "Rd = A2_subri 0, Rs"
390  case A2_negp:
391  return rr0(eSUB(eIMM(0, W0), rc(1)), Outputs);
392 
393  case M2_mpy_up: {
394  RegisterCell M = eMLS(rc(1), rc(2));
395  return rr0(hi(M, W0), Outputs);
396  }
397  case M2_dpmpyss_s0:
398  return rr0(eMLS(rc(1), rc(2)), Outputs);
399  case M2_dpmpyss_acc_s0:
400  return rr0(eADD(rc(1), eMLS(rc(2), rc(3))), Outputs);
401  case M2_dpmpyss_nac_s0:
402  return rr0(eSUB(rc(1), eMLS(rc(2), rc(3))), Outputs);
403  case M2_mpyi: {
404  RegisterCell M = eMLS(rc(1), rc(2));
405  return rr0(lo(M, W0), Outputs);
406  }
407  case M2_macsip: {
408  RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
409  RegisterCell RC = eADD(rc(1), lo(M, W0));
410  return rr0(RC, Outputs);
411  }
412  case M2_macsin: {
413  RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
414  RegisterCell RC = eSUB(rc(1), lo(M, W0));
415  return rr0(RC, Outputs);
416  }
417  case M2_maci: {
418  RegisterCell M = eMLS(rc(2), rc(3));
419  RegisterCell RC = eADD(rc(1), lo(M, W0));
420  return rr0(RC, Outputs);
421  }
422  case M2_mpysmi: {
423  RegisterCell M = eMLS(rc(1), eIMM(im(2), W0));
424  return rr0(lo(M, 32), Outputs);
425  }
426  case M2_mpysin: {
427  RegisterCell M = eMLS(rc(1), eIMM(-im(2), W0));
428  return rr0(lo(M, 32), Outputs);
429  }
430  case M2_mpysip: {
431  RegisterCell M = eMLS(rc(1), eIMM(im(2), W0));
432  return rr0(lo(M, 32), Outputs);
433  }
434  case M2_mpyu_up: {
435  RegisterCell M = eMLU(rc(1), rc(2));
436  return rr0(hi(M, W0), Outputs);
437  }
438  case M2_dpmpyuu_s0:
439  return rr0(eMLU(rc(1), rc(2)), Outputs);
440  case M2_dpmpyuu_acc_s0:
441  return rr0(eADD(rc(1), eMLU(rc(2), rc(3))), Outputs);
442  case M2_dpmpyuu_nac_s0:
443  return rr0(eSUB(rc(1), eMLU(rc(2), rc(3))), Outputs);
444  //case M2_mpysu_up:
445 
446  // Logical/bitwise:
447 
448  case A2_andir:
449  return rr0(eAND(rc(1), eIMM(im(2), W0)), Outputs);
450  case A2_and:
451  case A2_andp:
452  return rr0(eAND(rc(1), rc(2)), Outputs);
453  case A4_andn:
454  case A4_andnp:
455  return rr0(eAND(rc(1), eNOT(rc(2))), Outputs);
456  case S4_andi_asl_ri: {
457  RegisterCell RC = eAND(eIMM(im(1), W0), eASL(rc(2), im(3)));
458  return rr0(RC, Outputs);
459  }
460  case S4_andi_lsr_ri: {
461  RegisterCell RC = eAND(eIMM(im(1), W0), eLSR(rc(2), im(3)));
462  return rr0(RC, Outputs);
463  }
464  case M4_and_and:
465  return rr0(eAND(rc(1), eAND(rc(2), rc(3))), Outputs);
466  case M4_and_andn:
467  return rr0(eAND(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
468  case M4_and_or:
469  return rr0(eAND(rc(1), eORL(rc(2), rc(3))), Outputs);
470  case M4_and_xor:
471  return rr0(eAND(rc(1), eXOR(rc(2), rc(3))), Outputs);
472  case A2_orir:
473  return rr0(eORL(rc(1), eIMM(im(2), W0)), Outputs);
474  case A2_or:
475  case A2_orp:
476  return rr0(eORL(rc(1), rc(2)), Outputs);
477  case A4_orn:
478  case A4_ornp:
479  return rr0(eORL(rc(1), eNOT(rc(2))), Outputs);
480  case S4_ori_asl_ri: {
481  RegisterCell RC = eORL(eIMM(im(1), W0), eASL(rc(2), im(3)));
482  return rr0(RC, Outputs);
483  }
484  case S4_ori_lsr_ri: {
485  RegisterCell RC = eORL(eIMM(im(1), W0), eLSR(rc(2), im(3)));
486  return rr0(RC, Outputs);
487  }
488  case M4_or_and:
489  return rr0(eORL(rc(1), eAND(rc(2), rc(3))), Outputs);
490  case M4_or_andn:
491  return rr0(eORL(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
492  case S4_or_andi:
493  case S4_or_andix: {
494  RegisterCell RC = eORL(rc(1), eAND(rc(2), eIMM(im(3), W0)));
495  return rr0(RC, Outputs);
496  }
497  case S4_or_ori: {
498  RegisterCell RC = eORL(rc(1), eORL(rc(2), eIMM(im(3), W0)));
499  return rr0(RC, Outputs);
500  }
501  case M4_or_or:
502  return rr0(eORL(rc(1), eORL(rc(2), rc(3))), Outputs);
503  case M4_or_xor:
504  return rr0(eORL(rc(1), eXOR(rc(2), rc(3))), Outputs);
505  case A2_xor:
506  case A2_xorp:
507  return rr0(eXOR(rc(1), rc(2)), Outputs);
508  case M4_xor_and:
509  return rr0(eXOR(rc(1), eAND(rc(2), rc(3))), Outputs);
510  case M4_xor_andn:
511  return rr0(eXOR(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
512  case M4_xor_or:
513  return rr0(eXOR(rc(1), eORL(rc(2), rc(3))), Outputs);
514  case M4_xor_xacc:
515  return rr0(eXOR(rc(1), eXOR(rc(2), rc(3))), Outputs);
516  case A2_not:
517  case A2_notp:
518  return rr0(eNOT(rc(1)), Outputs);
519 
520  case S2_asl_i_r:
521  case S2_asl_i_p:
522  return rr0(eASL(rc(1), im(2)), Outputs);
523  case A2_aslh:
524  return rr0(eASL(rc(1), 16), Outputs);
525  case S2_asl_i_r_acc:
526  case S2_asl_i_p_acc:
527  return rr0(eADD(rc(1), eASL(rc(2), im(3))), Outputs);
528  case S2_asl_i_r_nac:
529  case S2_asl_i_p_nac:
530  return rr0(eSUB(rc(1), eASL(rc(2), im(3))), Outputs);
531  case S2_asl_i_r_and:
532  case S2_asl_i_p_and:
533  return rr0(eAND(rc(1), eASL(rc(2), im(3))), Outputs);
534  case S2_asl_i_r_or:
535  case S2_asl_i_p_or:
536  return rr0(eORL(rc(1), eASL(rc(2), im(3))), Outputs);
537  case S2_asl_i_r_xacc:
538  case S2_asl_i_p_xacc:
539  return rr0(eXOR(rc(1), eASL(rc(2), im(3))), Outputs);
540  case S2_asl_i_vh:
541  case S2_asl_i_vw:
542  // TODO
543  break;
544 
545  case S2_asr_i_r:
546  case S2_asr_i_p:
547  return rr0(eASR(rc(1), im(2)), Outputs);
548  case A2_asrh:
549  return rr0(eASR(rc(1), 16), Outputs);
550  case S2_asr_i_r_acc:
551  case S2_asr_i_p_acc:
552  return rr0(eADD(rc(1), eASR(rc(2), im(3))), Outputs);
553  case S2_asr_i_r_nac:
554  case S2_asr_i_p_nac:
555  return rr0(eSUB(rc(1), eASR(rc(2), im(3))), Outputs);
556  case S2_asr_i_r_and:
557  case S2_asr_i_p_and:
558  return rr0(eAND(rc(1), eASR(rc(2), im(3))), Outputs);
559  case S2_asr_i_r_or:
560  case S2_asr_i_p_or:
561  return rr0(eORL(rc(1), eASR(rc(2), im(3))), Outputs);
562  case S2_asr_i_r_rnd: {
563  // The input is first sign-extended to 64 bits, then the output
564  // is truncated back to 32 bits.
565  assert(W0 == 32);
566  RegisterCell XC = eSXT(rc(1).cat(eIMM(0, W0)), W0);
567  RegisterCell RC = eASR(eADD(eASR(XC, im(2)), eIMM(1, 2*W0)), 1);
568  return rr0(eXTR(RC, 0, W0), Outputs);
569  }
570  case S2_asr_i_r_rnd_goodsyntax: {
571  int64_t S = im(2);
572  if (S == 0)
573  return rr0(rc(1), Outputs);
574  // Result: S2_asr_i_r_rnd Rs, u5-1
575  RegisterCell XC = eSXT(rc(1).cat(eIMM(0, W0)), W0);
576  RegisterCell RC = eLSR(eADD(eASR(XC, S-1), eIMM(1, 2*W0)), 1);
577  return rr0(eXTR(RC, 0, W0), Outputs);
578  }
579  case S2_asr_r_vh:
580  case S2_asr_i_vw:
581  case S2_asr_i_svw_trun:
582  // TODO
583  break;
584 
585  case S2_lsr_i_r:
586  case S2_lsr_i_p:
587  return rr0(eLSR(rc(1), im(2)), Outputs);
588  case S2_lsr_i_r_acc:
589  case S2_lsr_i_p_acc:
590  return rr0(eADD(rc(1), eLSR(rc(2), im(3))), Outputs);
591  case S2_lsr_i_r_nac:
592  case S2_lsr_i_p_nac:
593  return rr0(eSUB(rc(1), eLSR(rc(2), im(3))), Outputs);
594  case S2_lsr_i_r_and:
595  case S2_lsr_i_p_and:
596  return rr0(eAND(rc(1), eLSR(rc(2), im(3))), Outputs);
597  case S2_lsr_i_r_or:
598  case S2_lsr_i_p_or:
599  return rr0(eORL(rc(1), eLSR(rc(2), im(3))), Outputs);
600  case S2_lsr_i_r_xacc:
601  case S2_lsr_i_p_xacc:
602  return rr0(eXOR(rc(1), eLSR(rc(2), im(3))), Outputs);
603 
604  case S2_clrbit_i: {
605  RegisterCell RC = rc(1);
606  RC[im(2)] = BT::BitValue::Zero;
607  return rr0(RC, Outputs);
608  }
609  case S2_setbit_i: {
610  RegisterCell RC = rc(1);
611  RC[im(2)] = BT::BitValue::One;
612  return rr0(RC, Outputs);
613  }
614  case S2_togglebit_i: {
615  RegisterCell RC = rc(1);
616  uint16_t BX = im(2);
617  RC[BX] = RC[BX].is(0) ? BT::BitValue::One
618  : RC[BX].is(1) ? BT::BitValue::Zero
619  : BT::BitValue::self();
620  return rr0(RC, Outputs);
621  }
622 
623  case A4_bitspliti: {
624  uint16_t W1 = getRegBitWidth(Reg[1]);
625  uint16_t BX = im(2);
626  // Res.uw[1] = Rs[bx+1:], Res.uw[0] = Rs[0:bx]
627  const BT::BitValue Zero = BT::BitValue::Zero;
628  RegisterCell RZ = RegisterCell(W0).fill(BX, W1, Zero)
629  .fill(W1+(W1-BX), W0, Zero);
630  RegisterCell BF1 = eXTR(rc(1), 0, BX), BF2 = eXTR(rc(1), BX, W1);
631  RegisterCell RC = eINS(eINS(RZ, BF1, 0), BF2, W1);
632  return rr0(RC, Outputs);
633  }
634  case S4_extract:
635  case S4_extractp:
636  case S2_extractu:
637  case S2_extractup: {
638  uint16_t Wd = im(2), Of = im(3);
639  assert(Wd <= W0);
640  if (Wd == 0)
641  return rr0(eIMM(0, W0), Outputs);
642  // If the width extends beyond the register size, pad the register
643  // with 0 bits.
644  RegisterCell Pad = (Wd+Of > W0) ? rc(1).cat(eIMM(0, Wd+Of-W0)) : rc(1);
645  RegisterCell Ext = eXTR(Pad, Of, Wd+Of);
646  // Ext is short, need to extend it with 0s or sign bit.
647  RegisterCell RC = RegisterCell(W0).insert(Ext, BT::BitMask(0, Wd-1));
648  if (Opc == S2_extractu || Opc == S2_extractup)
649  return rr0(eZXT(RC, Wd), Outputs);
650  return rr0(eSXT(RC, Wd), Outputs);
651  }
652  case S2_insert:
653  case S2_insertp: {
654  uint16_t Wd = im(3), Of = im(4);
655  assert(Wd < W0 && Of < W0);
656  // If Wd+Of exceeds W0, the inserted bits are truncated.
657  if (Wd+Of > W0)
658  Wd = W0-Of;
659  if (Wd == 0)
660  return rr0(rc(1), Outputs);
661  return rr0(eINS(rc(1), eXTR(rc(2), 0, Wd), Of), Outputs);
662  }
663 
664  // Bit permutations:
665 
666  case A2_combineii:
667  case A4_combineii:
668  case A4_combineir:
669  case A4_combineri:
670  case A2_combinew:
671  assert(W0 % 2 == 0);
672  return rr0(cop(2, W0/2).cat(cop(1, W0/2)), Outputs);
673  case A2_combine_ll:
674  case A2_combine_lh:
675  case A2_combine_hl:
676  case A2_combine_hh: {
677  assert(W0 == 32);
678  assert(getRegBitWidth(Reg[1]) == 32 && getRegBitWidth(Reg[2]) == 32);
679  // Low half in the output is 0 for _ll and _hl, 1 otherwise:
680  unsigned LoH = !(Opc == A2_combine_ll || Opc == A2_combine_hl);
681  // High half in the output is 0 for _ll and _lh, 1 otherwise:
682  unsigned HiH = !(Opc == A2_combine_ll || Opc == A2_combine_lh);
683  RegisterCell R1 = rc(1);
684  RegisterCell R2 = rc(2);
685  RegisterCell RC = half(R2, LoH).cat(half(R1, HiH));
686  return rr0(RC, Outputs);
687  }
688  case S2_packhl: {
689  assert(W0 == 64);
690  assert(getRegBitWidth(Reg[1]) == 32 && getRegBitWidth(Reg[2]) == 32);
691  RegisterCell R1 = rc(1);
692  RegisterCell R2 = rc(2);
693  RegisterCell RC = half(R2, 0).cat(half(R1, 0)).cat(half(R2, 1))
694  .cat(half(R1, 1));
695  return rr0(RC, Outputs);
696  }
697  case S2_shuffeb: {
698  RegisterCell RC = shuffle(rc(1), rc(2), 8, false);
699  return rr0(RC, Outputs);
700  }
701  case S2_shuffeh: {
702  RegisterCell RC = shuffle(rc(1), rc(2), 16, false);
703  return rr0(RC, Outputs);
704  }
705  case S2_shuffob: {
706  RegisterCell RC = shuffle(rc(1), rc(2), 8, true);
707  return rr0(RC, Outputs);
708  }
709  case S2_shuffoh: {
710  RegisterCell RC = shuffle(rc(1), rc(2), 16, true);
711  return rr0(RC, Outputs);
712  }
713  case C2_mask: {
714  uint16_t WR = W0;
715  uint16_t WP = 8; // XXX Pred size: getRegBitWidth(Reg[1]);
716  assert(WR == 64 && WP == 8);
717  RegisterCell R1 = rc(1);
718  RegisterCell RC(WR);
719  for (uint16_t i = 0; i < WP; ++i) {
720  const BT::BitValue &V = R1[i];
721  BT::BitValue F = (V.is(0) || V.is(1)) ? V : BT::BitValue::self();
722  RC.fill(i*8, i*8+8, F);
723  }
724  return rr0(RC, Outputs);
725  }
726 
727  // Mux:
728 
729  case C2_muxii:
730  case C2_muxir:
731  case C2_muxri:
732  case C2_mux: {
733  BT::BitValue PC0 = rc(1)[0];
734  RegisterCell R2 = cop(2, W0);
735  RegisterCell R3 = cop(3, W0);
736  if (PC0.is(0) || PC0.is(1))
737  return rr0(RegisterCell::ref(PC0 ? R2 : R3), Outputs);
738  R2.meet(R3, Reg[0].Reg);
739  return rr0(R2, Outputs);
740  }
741  case C2_vmux:
742  // TODO
743  break;
744 
745  // Sign- and zero-extension:
746 
747  case A2_sxtb:
748  return rr0(eSXT(rc(1), 8), Outputs);
749  case A2_sxth:
750  return rr0(eSXT(rc(1), 16), Outputs);
751  case A2_sxtw: {
752  uint16_t W1 = getRegBitWidth(Reg[1]);
753  assert(W0 == 64 && W1 == 32);
754  RegisterCell RC = eSXT(rc(1).cat(eIMM(0, W1)), W1);
755  return rr0(RC, Outputs);
756  }
757  case A2_zxtb:
758  return rr0(eZXT(rc(1), 8), Outputs);
759  case A2_zxth:
760  return rr0(eZXT(rc(1), 16), Outputs);
761 
762  // Bit count:
763 
764  case S2_cl0:
765  case S2_cl0p:
766  // Always produce a 32-bit result.
767  return rr0(eCLB(rc(1), 0/*bit*/, 32), Outputs);
768  case S2_cl1:
769  case S2_cl1p:
770  return rr0(eCLB(rc(1), 1/*bit*/, 32), Outputs);
771  case S2_clb:
772  case S2_clbp: {
773  uint16_t W1 = getRegBitWidth(Reg[1]);
774  RegisterCell R1 = rc(1);
775  BT::BitValue TV = R1[W1-1];
776  if (TV.is(0) || TV.is(1))
777  return rr0(eCLB(R1, TV, 32), Outputs);
778  break;
779  }
780  case S2_ct0:
781  case S2_ct0p:
782  return rr0(eCTB(rc(1), 0/*bit*/, 32), Outputs);
783  case S2_ct1:
784  case S2_ct1p:
785  return rr0(eCTB(rc(1), 1/*bit*/, 32), Outputs);
786  case S5_popcountp:
787  // TODO
788  break;
789 
790  case C2_all8: {
791  RegisterCell P1 = rc(1);
792  bool Has0 = false, All1 = true;
793  for (uint16_t i = 0; i < 8/*XXX*/; ++i) {
794  if (!P1[i].is(1))
795  All1 = false;
796  if (!P1[i].is(0))
797  continue;
798  Has0 = true;
799  break;
800  }
801  if (!Has0 && !All1)
802  break;
803  RegisterCell RC(W0);
804  RC.fill(0, W0, (All1 ? BT::BitValue::One : BT::BitValue::Zero));
805  return rr0(RC, Outputs);
806  }
807  case C2_any8: {
808  RegisterCell P1 = rc(1);
809  bool Has1 = false, All0 = true;
810  for (uint16_t i = 0; i < 8/*XXX*/; ++i) {
811  if (!P1[i].is(0))
812  All0 = false;
813  if (!P1[i].is(1))
814  continue;
815  Has1 = true;
816  break;
817  }
818  if (!Has1 && !All0)
819  break;
820  RegisterCell RC(W0);
821  RC.fill(0, W0, (Has1 ? BT::BitValue::One : BT::BitValue::Zero));
822  return rr0(RC, Outputs);
823  }
824  case C2_and:
825  return rr0(eAND(rc(1), rc(2)), Outputs);
826  case C2_andn:
827  return rr0(eAND(rc(1), eNOT(rc(2))), Outputs);
828  case C2_not:
829  return rr0(eNOT(rc(1)), Outputs);
830  case C2_or:
831  return rr0(eORL(rc(1), rc(2)), Outputs);
832  case C2_orn:
833  return rr0(eORL(rc(1), eNOT(rc(2))), Outputs);
834  case C2_xor:
835  return rr0(eXOR(rc(1), rc(2)), Outputs);
836  case C4_and_and:
837  return rr0(eAND(rc(1), eAND(rc(2), rc(3))), Outputs);
838  case C4_and_andn:
839  return rr0(eAND(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
840  case C4_and_or:
841  return rr0(eAND(rc(1), eORL(rc(2), rc(3))), Outputs);
842  case C4_and_orn:
843  return rr0(eAND(rc(1), eORL(rc(2), eNOT(rc(3)))), Outputs);
844  case C4_or_and:
845  return rr0(eORL(rc(1), eAND(rc(2), rc(3))), Outputs);
846  case C4_or_andn:
847  return rr0(eORL(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
848  case C4_or_or:
849  return rr0(eORL(rc(1), eORL(rc(2), rc(3))), Outputs);
850  case C4_or_orn:
851  return rr0(eORL(rc(1), eORL(rc(2), eNOT(rc(3)))), Outputs);
852  case C2_bitsclr:
853  case C2_bitsclri:
854  case C2_bitsset:
855  case C4_nbitsclr:
856  case C4_nbitsclri:
857  case C4_nbitsset:
858  // TODO
859  break;
860  case S2_tstbit_i:
861  case S4_ntstbit_i: {
862  BT::BitValue V = rc(1)[im(2)];
863  if (V.is(0) || V.is(1)) {
864  // If instruction is S2_tstbit_i, test for 1, otherwise test for 0.
865  bool TV = (Opc == S2_tstbit_i);
867  return rr0(RegisterCell(W0).fill(0, W0, F), Outputs);
868  }
869  break;
870  }
871 
872  default:
873  return MachineEvaluator::evaluate(MI, Inputs, Outputs);
874  }
875  #undef im
876  #undef rc
877  #undef op
878  return false;
879 }
880 
881 
883  const CellMapType &Inputs, BranchTargetList &Targets,
884  bool &FallsThru) const {
885  // We need to evaluate one branch at a time. TII::AnalyzeBranch checks
886  // all the branches in a basic block at once, so we cannot use it.
887  unsigned Opc = BI->getOpcode();
888  bool SimpleBranch = false;
889  bool Negated = false;
890  switch (Opc) {
891  case Hexagon::J2_jumpf:
892  case Hexagon::J2_jumpfnew:
893  case Hexagon::J2_jumpfnewpt:
894  Negated = true;
895  case Hexagon::J2_jumpt:
896  case Hexagon::J2_jumptnew:
897  case Hexagon::J2_jumptnewpt:
898  // Simple branch: if([!]Pn) jump ...
899  // i.e. Op0 = predicate, Op1 = branch target.
900  SimpleBranch = true;
901  break;
902  case Hexagon::J2_jump:
903  Targets.insert(BI->getOperand(0).getMBB());
904  FallsThru = false;
905  return true;
906  default:
907  // If the branch is of unknown type, assume that all successors are
908  // executable.
909  return false;
910  }
911 
912  if (!SimpleBranch)
913  return false;
914 
915  // BI is a conditional branch if we got here.
916  RegisterRef PR = BI->getOperand(0);
917  RegisterCell PC = getCell(PR, Inputs);
918  const BT::BitValue &Test = PC[0];
919 
920  // If the condition is neither true nor false, then it's unknown.
921  if (!Test.is(0) && !Test.is(1))
922  return false;
923 
924  // "Test.is(!Negated)" means "branch condition is true".
925  if (!Test.is(!Negated)) {
926  // Condition known to be false.
927  FallsThru = true;
928  return true;
929  }
930 
931  Targets.insert(BI->getOperand(1).getMBB());
932  FallsThru = false;
933  return true;
934 }
935 
936 
937 bool HexagonEvaluator::evaluateLoad(const MachineInstr *MI,
938  const CellMapType &Inputs, CellMapType &Outputs) const {
939  if (TII.isPredicated(MI))
940  return false;
941  assert(MI->mayLoad() && "A load that mayn't?");
942  unsigned Opc = MI->getOpcode();
943 
944  uint16_t BitNum;
945  bool SignEx;
946  using namespace Hexagon;
947 
948  switch (Opc) {
949  default:
950  return false;
951 
952 #if 0
953  // memb_fifo
954  case L2_loadalignb_pbr:
955  case L2_loadalignb_pcr:
956  case L2_loadalignb_pi:
957  // memh_fifo
958  case L2_loadalignh_pbr:
959  case L2_loadalignh_pcr:
960  case L2_loadalignh_pi:
961  // membh
962  case L2_loadbsw2_pbr:
963  case L2_loadbsw2_pci:
964  case L2_loadbsw2_pcr:
965  case L2_loadbsw2_pi:
966  case L2_loadbsw4_pbr:
967  case L2_loadbsw4_pci:
968  case L2_loadbsw4_pcr:
969  case L2_loadbsw4_pi:
970  // memubh
971  case L2_loadbzw2_pbr:
972  case L2_loadbzw2_pci:
973  case L2_loadbzw2_pcr:
974  case L2_loadbzw2_pi:
975  case L2_loadbzw4_pbr:
976  case L2_loadbzw4_pci:
977  case L2_loadbzw4_pcr:
978  case L2_loadbzw4_pi:
979 #endif
980 
981  case L2_loadrbgp:
982  case L2_loadrb_io:
983  case L2_loadrb_pbr:
984  case L2_loadrb_pci:
985  case L2_loadrb_pcr:
986  case L2_loadrb_pi:
987  case L4_loadrb_abs:
988  case L4_loadrb_ap:
989  case L4_loadrb_rr:
990  case L4_loadrb_ur:
991  BitNum = 8;
992  SignEx = true;
993  break;
994 
995  case L2_loadrubgp:
996  case L2_loadrub_io:
997  case L2_loadrub_pbr:
998  case L2_loadrub_pci:
999  case L2_loadrub_pcr:
1000  case L2_loadrub_pi:
1001  case L4_loadrub_abs:
1002  case L4_loadrub_ap:
1003  case L4_loadrub_rr:
1004  case L4_loadrub_ur:
1005  BitNum = 8;
1006  SignEx = false;
1007  break;
1008 
1009  case L2_loadrhgp:
1010  case L2_loadrh_io:
1011  case L2_loadrh_pbr:
1012  case L2_loadrh_pci:
1013  case L2_loadrh_pcr:
1014  case L2_loadrh_pi:
1015  case L4_loadrh_abs:
1016  case L4_loadrh_ap:
1017  case L4_loadrh_rr:
1018  case L4_loadrh_ur:
1019  BitNum = 16;
1020  SignEx = true;
1021  break;
1022 
1023  case L2_loadruhgp:
1024  case L2_loadruh_io:
1025  case L2_loadruh_pbr:
1026  case L2_loadruh_pci:
1027  case L2_loadruh_pcr:
1028  case L2_loadruh_pi:
1029  case L4_loadruh_rr:
1030  case L4_loadruh_abs:
1031  case L4_loadruh_ap:
1032  case L4_loadruh_ur:
1033  BitNum = 16;
1034  SignEx = false;
1035  break;
1036 
1037  case L2_loadrigp:
1038  case L2_loadri_io:
1039  case L2_loadri_pbr:
1040  case L2_loadri_pci:
1041  case L2_loadri_pcr:
1042  case L2_loadri_pi:
1043  case L2_loadw_locked:
1044  case L4_loadri_abs:
1045  case L4_loadri_ap:
1046  case L4_loadri_rr:
1047  case L4_loadri_ur:
1048  case LDriw_pred:
1049  BitNum = 32;
1050  SignEx = true;
1051  break;
1052 
1053  case L2_loadrdgp:
1054  case L2_loadrd_io:
1055  case L2_loadrd_pbr:
1056  case L2_loadrd_pci:
1057  case L2_loadrd_pcr:
1058  case L2_loadrd_pi:
1059  case L4_loadd_locked:
1060  case L4_loadrd_abs:
1061  case L4_loadrd_ap:
1062  case L4_loadrd_rr:
1063  case L4_loadrd_ur:
1064  BitNum = 64;
1065  SignEx = true;
1066  break;
1067  }
1068 
1069  const MachineOperand &MD = MI->getOperand(0);
1070  assert(MD.isReg() && MD.isDef());
1071  RegisterRef RD = MD;
1072 
1073  uint16_t W = getRegBitWidth(RD);
1074  assert(W >= BitNum && BitNum > 0);
1075  RegisterCell Res(W);
1076 
1077  for (uint16_t i = 0; i < BitNum; ++i)
1078  Res[i] = BT::BitValue::self(BT::BitRef(RD.Reg, i));
1079 
1080  if (SignEx) {
1081  const BT::BitValue &Sign = Res[BitNum-1];
1082  for (uint16_t i = BitNum; i < W; ++i)
1083  Res[i] = BT::BitValue::ref(Sign);
1084  } else {
1085  for (uint16_t i = BitNum; i < W; ++i)
1086  Res[i] = BT::BitValue::Zero;
1087  }
1088 
1089  putCell(RD, Res, Outputs);
1090  return true;
1091 }
1092 
1093 
1094 bool HexagonEvaluator::evaluateFormalCopy(const MachineInstr *MI,
1095  const CellMapType &Inputs, CellMapType &Outputs) const {
1096  // If MI defines a formal parameter, but is not a copy (loads are handled
1097  // in evaluateLoad), then it's not clear what to do.
1098  assert(MI->isCopy());
1099 
1100  RegisterRef RD = MI->getOperand(0);
1101  RegisterRef RS = MI->getOperand(1);
1102  assert(RD.Sub == 0);
1104  return false;
1105  RegExtMap::const_iterator F = VRX.find(RD.Reg);
1106  if (F == VRX.end())
1107  return false;
1108 
1109  uint16_t EW = F->second.Width;
1110  // Store RD's cell into the map. This will associate the cell with a virtual
1111  // register, and make zero-/sign-extends possible (otherwise we would be ex-
1112  // tending "self" bit values, which will have no effect, since "self" values
1113  // cannot be references to anything).
1114  putCell(RD, getCell(RS, Inputs), Outputs);
1115 
1116  RegisterCell Res;
1117  // Read RD's cell from the outputs instead of RS's cell from the inputs:
1118  if (F->second.Type == ExtType::SExt)
1119  Res = eSXT(getCell(RD, Outputs), EW);
1120  else if (F->second.Type == ExtType::ZExt)
1121  Res = eZXT(getCell(RD, Outputs), EW);
1122 
1123  putCell(RD, Res, Outputs);
1124  return true;
1125 }
1126 
1127 
1128 unsigned HexagonEvaluator::getNextPhysReg(unsigned PReg, unsigned Width) const {
1129  using namespace Hexagon;
1130  bool Is64 = DoubleRegsRegClass.contains(PReg);
1131  assert(PReg == 0 || Is64 || IntRegsRegClass.contains(PReg));
1132 
1133  static const unsigned Phys32[] = { R0, R1, R2, R3, R4, R5 };
1134  static const unsigned Phys64[] = { D0, D1, D2 };
1135  const unsigned Num32 = sizeof(Phys32)/sizeof(unsigned);
1136  const unsigned Num64 = sizeof(Phys64)/sizeof(unsigned);
1137 
1138  // Return the first parameter register of the required width.
1139  if (PReg == 0)
1140  return (Width <= 32) ? Phys32[0] : Phys64[0];
1141 
1142  // Set Idx32, Idx64 in such a way that Idx+1 would give the index of the
1143  // next register.
1144  unsigned Idx32 = 0, Idx64 = 0;
1145  if (!Is64) {
1146  while (Idx32 < Num32) {
1147  if (Phys32[Idx32] == PReg)
1148  break;
1149  Idx32++;
1150  }
1151  Idx64 = Idx32/2;
1152  } else {
1153  while (Idx64 < Num64) {
1154  if (Phys64[Idx64] == PReg)
1155  break;
1156  Idx64++;
1157  }
1158  Idx32 = Idx64*2+1;
1159  }
1160 
1161  if (Width <= 32)
1162  return (Idx32+1 < Num32) ? Phys32[Idx32+1] : 0;
1163  return (Idx64+1 < Num64) ? Phys64[Idx64+1] : 0;
1164 }
1165 
1166 
1167 unsigned HexagonEvaluator::getVirtRegFor(unsigned PReg) const {
1168  typedef MachineRegisterInfo::livein_iterator iterator;
1169  for (iterator I = MRI.livein_begin(), E = MRI.livein_end(); I != E; ++I) {
1170  if (I->first == PReg)
1171  return I->second;
1172  }
1173  return 0;
1174 }
#define R4(n)
LLVM Argument representation.
Definition: Argument.h:35
const TargetRegisterInfo & TRI
Definition: BitTracker.h:443
RegisterCell & fill(uint16_t B, uint16_t E, const BitValue &V)
Definition: BitTracker.cpp:261
Sign extended before/after call.
Definition: Attributes.h:105
livein_iterator livein_end() const
MachineBasicBlock * getMBB() const
RegisterCell eASR(const RegisterCell &A1, uint16_t Sh) const
Definition: BitTracker.cpp:544
static RegisterCell self(unsigned Reg, uint16_t Width)
Definition: BitTracker.h:321
bool isBlockAddress() const
isBlockAddress - Tests if this is a MO_BlockAddress operand.
arg_iterator arg_end()
Definition: Function.h:480
F(f)
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
BitTracker::BitMask mask(unsigned Reg, unsigned Sub) const override
uint16_t getRegBitWidth(const RegisterRef &RR) const
Definition: BitTracker.cpp:312
MachineFrameInfo & MFI
#define R2(n)
RegisterCell eXOR(const RegisterCell &A1, const RegisterCell &A2) const
Definition: BitTracker.cpp:602
const HexagonInstrInfo & TII
#define op(i)
bool hasAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return true if the attribute exists at the given index.
Definition: Attributes.cpp:956
RegisterCell eAND(const RegisterCell &A1, const RegisterCell &A2) const
Definition: BitTracker.cpp:556
HexagonEvaluator(const HexagonRegisterInfo &tri, MachineRegisterInfo &mri, const HexagonInstrInfo &tii, MachineFunction &mf)
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Definition: DenseMap.h:169
void putCell(const RegisterRef &RR, RegisterCell RC, CellMapType &M) const
Definition: BitTracker.cpp:366
RegisterCell eXTR(const RegisterCell &A1, uint16_t B, uint16_t E) const
Definition: BitTracker.cpp:701
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
const HexagonInstrInfo * TII
bool isPredicated(const MachineInstr *MI) const override
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:566
const TargetRegisterClass * getRegClass(unsigned Reg) const
getRegClass - Return the register class of the specified virtual register.
Reg
All possible values of the reg field in the ModR/M byte.
#define im(i)
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:271
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
RegisterCell eMLS(const RegisterCell &A1, const RegisterCell &A2) const
Definition: BitTracker.cpp:501
PrintReg - Helper class for printing registers on a raw_ostream.
bool is(unsigned T) const
Definition: BitTracker.h:162
bool insert(const value_type &X)
Insert a new element into the SetVector.
Definition: SetVector.h:102
RegisterCell eSUB(const RegisterCell &A1, const RegisterCell &A2) const
Definition: BitTracker.cpp:467
int64_t getImm() const
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:267
#define rc(i)
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
RegisterCell eSXT(const RegisterCell &A1, uint16_t FromN) const
Definition: BitTracker.cpp:679
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
RegisterCell eASL(const RegisterCell &A1, uint16_t Sh) const
Definition: BitTracker.cpp:523
bool isCopy() const
Definition: MachineInstr.h:778
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
RegisterCell getCell(const RegisterRef &RR, const CellMapType &M) const
Definition: BitTracker.cpp:338
Zero extended before/after call.
Definition: Attributes.h:119
arg_iterator arg_begin()
Definition: Function.h:472
RegisterCell eCTB(const RegisterCell &A1, bool B, uint16_t W) const
Definition: BitTracker.cpp:668
RegisterCell eZXT(const RegisterCell &A1, uint16_t FromN) const
Definition: BitTracker.cpp:691
RegisterCell eCLB(const RegisterCell &A1, bool B, uint16_t W) const
Definition: BitTracker.cpp:657
unsigned getSubReg() const
bool isPointerTy() const
isPointerTy - True if this is an instance of PointerType.
Definition: Type.h:217
RegisterCell eADD(const RegisterCell &A1, const RegisterCell &A2) const
Definition: BitTracker.cpp:433
MachineFunction & MF
RegisterCell eORL(const RegisterCell &A1, const RegisterCell &A2) const
Definition: BitTracker.cpp:579
unsigned getIntegerBitWidth() const
Definition: Type.cpp:176
static BitValue self(const BitRef &Self=BitRef())
Definition: BitTracker.h:234
MachineOperand class - Representation of each machine instruction operand.
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
Module.h This file contains the declarations for the Module class.
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:222
RegisterCell eLSR(const RegisterCell &A1, uint16_t Sh) const
Definition: BitTracker.cpp:533
livein_iterator livein_begin() const
MachineRegisterInfo & MRI
Definition: BitTracker.h:444
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:123
unsigned Log2_32(uint32_t Value)
Log2_32 - This function returns the floor log base 2 of the specified value, -1 if the value is zero...
Definition: MathExtras.h:468
AttributeSet getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:181
bool isIntegerTy() const
isIntegerTy - True if this is an instance of IntegerType.
Definition: Type.h:193
RegisterCell & insert(const RegisterCell &RC, const BitMask &M)
Definition: BitTracker.cpp:198
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:51
static bool isPhysicalRegister(unsigned Reg)
isPhysicalRegister - Return true if the specified register number is in the physical register namespa...
RegisterCell & cat(const RegisterCell &RC)
Definition: BitTracker.cpp:270
BitTracker::RegisterRef RegisterRef
#define I(x, y, z)
Definition: MD5.cpp:54
#define N
RegisterCell eMLU(const RegisterCell &A1, const RegisterCell &A2) const
Definition: BitTracker.cpp:512
APFloat abs(APFloat X)
Returns the absolute value of the argument.
Definition: APFloat.h:651
iterator end()
Definition: DenseMap.h:68
iterator find(const KeyT &Val)
Definition: DenseMap.h:124
bool evaluate(const MachineInstr *MI, const CellMapType &Inputs, CellMapType &Outputs) const override
void size_t size
RegisterCell eIMM(int64_t V, uint16_t W) const
Definition: BitTracker.cpp:411
BitTracker::CellMapType CellMapType
std::vector< std::pair< unsigned, unsigned > >::const_iterator livein_iterator
A vector that has set insertion semantics.
Definition: SetVector.h:37
RegisterCell eNOT(const RegisterCell &A1) const
Definition: BitTracker.cpp:623
bool meet(const RegisterCell &RC, unsigned SelfR)
Definition: BitTracker.cpp:184
static RegisterCell ref(const RegisterCell &C)
Definition: BitTracker.h:339
BitTracker::RegisterCell RegisterCell
BitTracker BT
static BitValue ref(const BitValue &V)
Definition: BitTracker.h:224
RegisterCell eINS(const RegisterCell &A1, const RegisterCell &A2, uint16_t AtN) const
Definition: BitTracker.cpp:714