15 #ifndef LLVM_MC_MCINSTRDESC_H
16 #define LLVM_MC_MCINSTRDESC_H
18 #include "llvm/Support/DataTypes.h"
24 class MCSubtargetInfo;
165 (
OpInfo[OpNum].Constraints & (1 << Constraint))) {
166 unsigned Pos = 16 + Constraint * 4;
175 std::string &Info)
const;
513 for (; *ImpUses; ++ImpUses)
540 if (
OpInfo[i].isPredicate())
550 bool hasDefOfPhysReg(
const MCInst &
MI,
unsigned Reg,
bool isIndirectBranch() const
Return true if this is an indirect branch, such as a branch through a register.
unsigned getNumImplicitUses() const
Return the number of implicit uses this instruction has.
const uint16_t * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
bool isPredicate() const
Set if this is one of the operands that made up of the predicate operand that controls an isPredicabl...
bool canFoldAsLoad() const
Return true for instructions that can be folded as memory operands in other instructions.
bool isCommutable() const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged.
unsigned getFlags() const
Return flags of this instruction.
bool isAsCheapAsAMove() const
Returns true if this instruction has the same cost (or less) than a move instruction.
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
bool(* ComplexDeprecationInfo)(MCInst &, const MCSubtargetInfo &, std::string &)
uint8_t Flags
These are flags from the MCOI::OperandFlags enum.
bool hasOptionalDef() const
Set if this instruction has an optional definition, e.g.
bool hasImplicitUseOfPhysReg(unsigned Reg) const
Return true if this instruction implicitly uses the specified physical register.
bool isReturn() const
Return true if the instruction is a return.
bool mayStore() const
Return true if this instruction could possibly modify memory.
Describe properties that are true of each instruction in the target description file.
const uint16_t * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction...
bool isRematerializable() const
Returns true if this instruction is a candidate for remat.
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
bool hasPostISelHook() const
Return true if this instruction requires adjustment after instruction selection by calling a target h...
bool isInsertSubregLike() const
Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions...
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
bool isCall() const
Return true if the instruction is a call.
Reg
All possible values of the reg field in the ModR/M byte.
const uint16_t * ImplicitUses
bool isTerminator() const
Returns true if this instruction part of the terminator for a basic block.
bool isBitcast() const
Return true if this instruction is a bitcast instruction.
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
uint8_t OperandType
Information about the type of the operand.
bool isRegSequenceLike() const
Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions.
bool hasExtraDefRegAllocReq() const
Returns true if this instruction def operands have special register allocation requirements that are ...
bool isBarrier() const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
bool isUnconditionalBranch() const
Return true if this is a branch which always transfers control flow to some other block...
uint32_t Constraints
The lower 16 bits are used to specify which constraints are set.
Instances of this class represent a single low-level machine instruction.
bool isConvertibleTo3Addr() const
Return true if this is a 2-address instruction which can be changed into a 3-address instruction if n...
unsigned short NumOperands
Flag
These should be considered private to the implementation of the MCInstrDesc class.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
bool isOptionalDef() const
Set if this operand is a optional def.
int64_t DeprecatedFeature
OperandFlags
These are flags set on operands, but should be considered private, all access should go through the M...
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
bool isCompare() const
Return true if this instruction is a comparison.
bool isNotDuplicable() const
Return true if this instruction cannot be safely duplicated.
bool isPseudo() const
Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction...
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
unsigned getOpcode() const
Return the opcode number for this descriptor.
bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const
Return true if this is a branch or an instruction which directly writes to the program counter...
bool mayLoad() const
Return true if this instruction could possibly read memory.
bool usesCustomInsertionHook() const
Return true if this instruction requires custom insertion support when the DAG scheduler is inserting...
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by other flags.
unsigned getSchedClass() const
Return the scheduling class for this instruction.
OperandType
Operands are tagged with one of the values of this enum.
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
MCSubtargetInfo - Generic base class for all target subtargets.
bool hasDelaySlot() const
Returns true if the specified instruction has a delay slot which must be filled by the code generator...
bool isExtractSubregLike() const
Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions...
bool isLookupPtrRegClass() const
Set if this operand is a pointer value and it requires a callback to look up its register class...
bool isSelect() const
Return true if this is a select instruction.
const uint16_t * ImplicitDefs
bool isMoveImmediate() const
Return true if this instruction is a move immediate (including conditional moves) instruction...
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
const MCOperandInfo * OpInfo
bool hasImplicitDefOfPhysReg(unsigned Reg, const MCRegisterInfo *MRI=nullptr) const
Return true if this instruction implicitly defines the specified physical register.
bool hasExtraSrcRegAllocReq() const
Returns true if this instruction source operands have special register allocation requirements that a...
This holds information about one operand of a machine instruction, indicating the register class for ...
unsigned short SchedClass
bool getDeprecatedInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info) const
Returns true if a certain instruction is deprecated and if so returns the reason in Info...
bool isConditionalBranch() const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
bool isConvergent() const
Return true if this instruction is convergent.