LLVM  3.7.0
X86InstrInfo.h
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1 //===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the X86 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_X86_X86INSTRINFO_H
15 #define LLVM_LIB_TARGET_X86_X86INSTRINFO_H
16 
18 #include "X86RegisterInfo.h"
19 #include "llvm/ADT/DenseMap.h"
21 
22 #define GET_INSTRINFO_HEADER
23 #include "X86GenInstrInfo.inc"
24 
25 namespace llvm {
26  class X86RegisterInfo;
27  class X86Subtarget;
28 
29  namespace MachineCombinerPattern {
30  enum MC_PATTERN : int {
31  // These are commutative variants for reassociating a computation chain
32  // of the form:
33  // B = A op X (Prev)
34  // C = B op Y (Root)
39  };
40  } // end namespace MachineCombinerPattern
41 
42 namespace X86 {
43  // X86 specific condition code. These correspond to X86_*_COND in
44  // X86InstrInfo.td. They must be kept in synch.
45  enum CondCode {
46  COND_A = 0,
47  COND_AE = 1,
48  COND_B = 2,
49  COND_BE = 3,
50  COND_E = 4,
51  COND_G = 5,
52  COND_GE = 6,
53  COND_L = 7,
54  COND_LE = 8,
55  COND_NE = 9,
56  COND_NO = 10,
57  COND_NP = 11,
58  COND_NS = 12,
59  COND_O = 13,
60  COND_P = 14,
61  COND_S = 15,
63 
64  // Artificial condition codes. These are used by AnalyzeBranch
65  // to indicate a block terminated with two conditional branches to
66  // the same location. This occurs in code using FCMP_OEQ or FCMP_UNE,
67  // which can't be represented on x86 with a single condition. These
68  // are never used in MachineInstrs.
71 
73  };
74 
75  // Turn condition code into conditional branch opcode.
76  unsigned GetCondBranchFromCond(CondCode CC);
77 
78  /// \brief Return a set opcode for the given condition and whether it has
79  /// a memory operand.
80  unsigned getSETFromCond(CondCode CC, bool HasMemoryOperand = false);
81 
82  /// \brief Return a cmov opcode for the given condition, register size in
83  /// bytes, and operand type.
84  unsigned getCMovFromCond(CondCode CC, unsigned RegBytes,
85  bool HasMemoryOperand = false);
86 
87  // Turn CMov opcode into condition code.
88  CondCode getCondFromCMovOpc(unsigned Opc);
89 
90  /// GetOppositeBranchCondition - Return the inverse of the specified cond,
91  /// e.g. turning COND_E to COND_NE.
93 } // end namespace X86;
94 
95 
96 /// isGlobalStubReference - Return true if the specified TargetFlag operand is
97 /// a reference to a stub for a global, not the global itself.
98 inline static bool isGlobalStubReference(unsigned char TargetFlag) {
99  switch (TargetFlag) {
100  case X86II::MO_DLLIMPORT: // dllimport stub.
101  case X86II::MO_GOTPCREL: // rip-relative GOT reference.
102  case X86II::MO_GOT: // normal GOT reference.
103  case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref.
104  case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref.
105  case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Hidden $non_lazy_ptr ref.
106  return true;
107  default:
108  return false;
109  }
110 }
111 
112 /// isGlobalRelativeToPICBase - Return true if the specified global value
113 /// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this
114 /// is true, the addressing mode has the PIC base register added in (e.g. EBX).
115 inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) {
116  switch (TargetFlag) {
117  case X86II::MO_GOTOFF: // isPICStyleGOT: local global.
118  case X86II::MO_GOT: // isPICStyleGOT: other global.
119  case X86II::MO_PIC_BASE_OFFSET: // Darwin local global.
120  case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global.
121  case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Darwin/32 hidden global.
122  case X86II::MO_TLVP: // ??? Pretty sure..
123  return true;
124  default:
125  return false;
126  }
127 }
128 
129 inline static bool isScale(const MachineOperand &MO) {
130  return MO.isImm() &&
131  (MO.getImm() == 1 || MO.getImm() == 2 ||
132  MO.getImm() == 4 || MO.getImm() == 8);
133 }
134 
135 inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) {
136  if (MI->getOperand(Op).isFI()) return true;
137  return Op+X86::AddrSegmentReg <= MI->getNumOperands() &&
138  MI->getOperand(Op+X86::AddrBaseReg).isReg() &&
140  MI->getOperand(Op+X86::AddrIndexReg).isReg() &&
141  (MI->getOperand(Op+X86::AddrDisp).isImm() ||
142  MI->getOperand(Op+X86::AddrDisp).isGlobal() ||
143  MI->getOperand(Op+X86::AddrDisp).isCPI() ||
144  MI->getOperand(Op+X86::AddrDisp).isJTI());
145 }
146 
147 inline static bool isMem(const MachineInstr *MI, unsigned Op) {
148  if (MI->getOperand(Op).isFI()) return true;
149  return Op+X86::AddrNumOperands <= MI->getNumOperands() &&
151  isLeaMem(MI, Op);
152 }
153 
154 class X86InstrInfo final : public X86GenInstrInfo {
155  X86Subtarget &Subtarget;
156  const X86RegisterInfo RI;
157 
158  /// RegOp2MemOpTable3Addr, RegOp2MemOpTable0, RegOp2MemOpTable1,
159  /// RegOp2MemOpTable2, RegOp2MemOpTable3 - Load / store folding opcode maps.
160  ///
161  typedef DenseMap<unsigned,
162  std::pair<unsigned, unsigned> > RegOp2MemOpTableType;
163  RegOp2MemOpTableType RegOp2MemOpTable2Addr;
164  RegOp2MemOpTableType RegOp2MemOpTable0;
165  RegOp2MemOpTableType RegOp2MemOpTable1;
166  RegOp2MemOpTableType RegOp2MemOpTable2;
167  RegOp2MemOpTableType RegOp2MemOpTable3;
168  RegOp2MemOpTableType RegOp2MemOpTable4;
169 
170  /// MemOp2RegOpTable - Load / store unfolding opcode map.
171  ///
172  typedef DenseMap<unsigned,
173  std::pair<unsigned, unsigned> > MemOp2RegOpTableType;
174  MemOp2RegOpTableType MemOp2RegOpTable;
175 
176  static void AddTableEntry(RegOp2MemOpTableType &R2MTable,
177  MemOp2RegOpTableType &M2RTable,
178  unsigned RegOp, unsigned MemOp, unsigned Flags);
179 
180  virtual void anchor();
181 
182  bool AnalyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
183  MachineBasicBlock *&FBB,
185  SmallVectorImpl<MachineInstr *> &CondBranches,
186  bool AllowModify) const;
187 
188 public:
189  explicit X86InstrInfo(X86Subtarget &STI);
190 
191  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
192  /// such, whenever a client has an instance of instruction info, it should
193  /// always be able to get register info as well (through this method).
194  ///
195  const X86RegisterInfo &getRegisterInfo() const { return RI; }
196 
197  /// getSPAdjust - This returns the stack pointer adjustment made by
198  /// this instruction. For x86, we need to handle more complex call
199  /// sequences involving PUSHes.
200  int getSPAdjust(const MachineInstr *MI) const override;
201 
202  /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
203  /// extension instruction. That is, it's like a copy where it's legal for the
204  /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
205  /// true, then it's expected the pre-extension value is available as a subreg
206  /// of the result register. This also returns the sub-register index in
207  /// SubIdx.
209  unsigned &SrcReg, unsigned &DstReg,
210  unsigned &SubIdx) const override;
211 
212  unsigned isLoadFromStackSlot(const MachineInstr *MI,
213  int &FrameIndex) const override;
214  /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
215  /// stack locations as well. This uses a heuristic so it isn't
216  /// reliable for correctness.
217  unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
218  int &FrameIndex) const override;
219 
220  unsigned isStoreToStackSlot(const MachineInstr *MI,
221  int &FrameIndex) const override;
222  /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
223  /// stack locations as well. This uses a heuristic so it isn't
224  /// reliable for correctness.
225  unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
226  int &FrameIndex) const override;
227 
229  AliasAnalysis *AA) const override;
231  unsigned DestReg, unsigned SubIdx,
232  const MachineInstr *Orig,
233  const TargetRegisterInfo &TRI) const override;
234 
235  /// Given an operand within a MachineInstr, insert preceding code to put it
236  /// into the right format for a particular kind of LEA instruction. This may
237  /// involve using an appropriate super-register instead (with an implicit use
238  /// of the original) or creating a new virtual register and inserting COPY
239  /// instructions to get the data into the right class.
240  ///
241  /// Reference parameters are set to indicate how caller should add this
242  /// operand to the LEA instruction.
243  bool classifyLEAReg(MachineInstr *MI, const MachineOperand &Src,
244  unsigned LEAOpcode, bool AllowSP,
245  unsigned &NewSrc, bool &isKill,
246  bool &isUndef, MachineOperand &ImplicitOp) const;
247 
248  /// convertToThreeAddress - This method must be implemented by targets that
249  /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
250  /// may be able to convert a two-address instruction into a true
251  /// three-address instruction on demand. This allows the X86 target (for
252  /// example) to convert ADD and SHL instructions into LEA instructions if they
253  /// would require register copies due to two-addressness.
254  ///
255  /// This method returns a null pointer if the transformation cannot be
256  /// performed, otherwise it returns the new instruction.
257  ///
260  LiveVariables *LV) const override;
261 
262  /// commuteInstruction - We have a few instructions that must be hacked on to
263  /// commute them.
264  ///
265  MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const override;
266 
267  bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
268  unsigned &SrcOpIdx2) const override;
269 
270  // Branch analysis.
271  bool isUnpredicatedTerminator(const MachineInstr* MI) const override;
273  MachineBasicBlock *&FBB,
275  bool AllowModify) const override;
276 
277  bool getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
278  unsigned &Offset,
279  const TargetRegisterInfo *TRI) const override;
282  bool AllowModify = false) const override;
283 
284  unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
287  DebugLoc DL) const override;
289  unsigned, unsigned, int&, int&, int&) const override;
292  unsigned DstReg, ArrayRef<MachineOperand> Cond,
293  unsigned TrueReg, unsigned FalseReg) const override;
294  void copyPhysReg(MachineBasicBlock &MBB,
296  unsigned DestReg, unsigned SrcReg,
297  bool KillSrc) const override;
300  unsigned SrcReg, bool isKill, int FrameIndex,
301  const TargetRegisterClass *RC,
302  const TargetRegisterInfo *TRI) const override;
303 
304  void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
306  const TargetRegisterClass *RC,
309  SmallVectorImpl<MachineInstr*> &NewMIs) const;
310 
313  unsigned DestReg, int FrameIndex,
314  const TargetRegisterClass *RC,
315  const TargetRegisterInfo *TRI) const override;
316 
317  void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
319  const TargetRegisterClass *RC,
322  SmallVectorImpl<MachineInstr*> &NewMIs) const;
323 
325 
326  /// foldMemoryOperand - If this target supports it, fold a load or store of
327  /// the specified stack slot into the specified machine instruction for the
328  /// specified operand(s). If this is possible, the target should perform the
329  /// folding and return true, otherwise it should return false. If it folds
330  /// the instruction, it is likely that the MachineInstruction the iterator
331  /// references has been changed.
333  ArrayRef<unsigned> Ops,
335  int FrameIndex) const override;
336 
337  /// foldMemoryOperand - Same as the previous version except it allows folding
338  /// of any load and store from / to any address, not just from a specific
339  /// stack slot.
341  ArrayRef<unsigned> Ops,
343  MachineInstr *LoadMI) const override;
344 
345  /// canFoldMemoryOperand - Returns true if the specified load / store is
346  /// folding is possible.
347  bool canFoldMemoryOperand(const MachineInstr *,
348  ArrayRef<unsigned>) const override;
349 
350  /// unfoldMemoryOperand - Separate a single instruction which folded a load or
351  /// a store or a load and a store into two or more instruction. If this is
352  /// possible, returns true as well as the new instructions by reference.
354  unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
355  SmallVectorImpl<MachineInstr*> &NewMIs) const override;
356 
358  SmallVectorImpl<SDNode*> &NewNodes) const override;
359 
360  /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
361  /// instruction after load / store are unfolded from an instruction of the
362  /// specified opcode. It returns zero if the specified unfolding is not
363  /// possible. If LoadRegIndex is non-null, it is filled in with the operand
364  /// index of the operand which will hold the register holding the loaded
365  /// value.
366  unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
367  bool UnfoldLoad, bool UnfoldStore,
368  unsigned *LoadRegIndex = nullptr) const override;
369 
370  /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
371  /// to determine if two loads are loading from the same base address. It
372  /// should only return true if the base pointers are the same and the
373  /// only differences between the two addresses are the offset. It also returns
374  /// the offsets by reference.
375  bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
376  int64_t &Offset2) const override;
377 
378  /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
379  /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
380  /// be scheduled togther. On some targets if two loads are loading from
381  /// addresses in the same cache line, it's better if they are scheduled
382  /// together. This function takes two integers that represent the load offsets
383  /// from the common base address. It returns true if it decides it's desirable
384  /// to schedule the two loads together. "NumLoads" is the number of loads that
385  /// have already been scheduled after Load1.
386  bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
387  int64_t Offset1, int64_t Offset2,
388  unsigned NumLoads) const override;
389 
391  MachineInstr *Second) const override;
392 
393  void getNoopForMachoTarget(MCInst &NopInst) const override;
394 
395  bool
397 
398  /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
399  /// instruction that defines the specified register class.
400  bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
401 
402  /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction tha
403  /// would clobber the EFLAGS condition register. Note the result may be
404  /// conservative. If it cannot definitely determine the safety after visiting
405  /// a few instructions in each direction it assumes it's not safe.
408 
409  static bool isX86_64ExtendedReg(const MachineOperand &MO) {
410  if (!MO.isReg()) return false;
411  return X86II::isX86_64ExtendedReg(MO.getReg());
412  }
413 
414  /// getGlobalBaseReg - Return a virtual register initialized with the
415  /// the global base register value. Output instructions required to
416  /// initialize the register in the function entry block, if necessary.
417  ///
418  unsigned getGlobalBaseReg(MachineFunction *MF) const;
419 
420  std::pair<uint16_t, uint16_t>
421  getExecutionDomain(const MachineInstr *MI) const override;
422 
423  void setExecutionDomain(MachineInstr *MI, unsigned Domain) const override;
424 
425  unsigned
426  getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
427  const TargetRegisterInfo *TRI) const override;
428  unsigned getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum,
429  const TargetRegisterInfo *TRI) const override;
431  const TargetRegisterInfo *TRI) const override;
432 
434  unsigned OpNum,
437  unsigned Size, unsigned Alignment,
438  bool AllowCommute) const;
439 
440  void
442  const MCSymbolRefExpr *BranchTarget) const override;
443 
444  void getTrap(MCInst &MI) const override;
445 
446  unsigned getJumpInstrTableEntryBound() const override;
447 
448  bool isHighLatencyDef(int opc) const override;
449 
450  bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
451  const MachineRegisterInfo *MRI,
452  const MachineInstr *DefMI, unsigned DefIdx,
453  const MachineInstr *UseMI,
454  unsigned UseIdx) const override;
455 
456 
457  bool useMachineCombiner() const override {
458  return true;
459  }
460 
461  /// Return true when there is potentially a faster code sequence
462  /// for an instruction chain ending in <Root>. All potential patterns are
463  /// output in the <Pattern> array.
465  MachineInstr &Root,
467 
468  /// When getMachineCombinerPatterns() finds a pattern, this function generates
469  /// the instructions that could replace the original code sequence.
474  DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
475 
476  /// analyzeCompare - For a comparison instruction, return the source registers
477  /// in SrcReg and SrcReg2 if having two register operands, and the value it
478  /// compares against in CmpValue. Return true if the comparison instruction
479  /// can be analyzed.
480  bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
481  unsigned &SrcReg2, int &CmpMask,
482  int &CmpValue) const override;
483 
484  /// optimizeCompareInstr - Check if there exists an earlier instruction that
485  /// operates on the same source operands and sets flags in the same way as
486  /// Compare; remove Compare if possible.
487  bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
488  unsigned SrcReg2, int CmpMask, int CmpValue,
489  const MachineRegisterInfo *MRI) const override;
490 
491  /// optimizeLoadInstr - Try to remove the load by folding it to a register
492  /// operand at the use. We fold the load instructions if and only if the
493  /// def and use are in the same BB. We only look at one load and see
494  /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
495  /// defined by the load we are trying to fold. DefMI returns the machine
496  /// instruction that defines FoldAsLoadDefReg, and the function returns
497  /// the machine instruction generated due to folding.
499  const MachineRegisterInfo *MRI,
500  unsigned &FoldAsLoadDefReg,
501  MachineInstr *&DefMI) const override;
502 
503 private:
504  MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc,
507  LiveVariables *LV) const;
508 
509  /// isFrameOperand - Return true and the FrameIndex if the specified
510  /// operand and follow operands form a reference to the stack frame.
511  bool isFrameOperand(const MachineInstr *MI, unsigned int Op,
512  int &FrameIndex) const;
513 };
514 
515 } // End llvm namespace
516 
517 #endif
const X86RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: X86InstrInfo.h:195
unsigned GetCondBranchFromCond(CondCode CC)
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SubIdx, const MachineInstr *Orig, const TargetRegisterInfo &TRI) const override
static bool isScale(const MachineOperand &MO)
Definition: X86InstrInfo.h:129
AddrSegmentReg - The operand # of the segment in the memory operand.
Definition: X86BaseInfo.h:39
void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, MachineInstr::mmo_iterator MMOBegin, MachineInstr::mmo_iterator MMOEnd, SmallVectorImpl< MachineInstr * > &NewMIs) const
bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are lo...
void setExecutionDomain(MachineInstr *MI, unsigned Domain) const override
CondCode getCondFromCMovOpc(unsigned Opc)
Return condition code of a CMov opcode.
bool isHighLatencyDef(int opc) const override
unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const override
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex) const override
foldMemoryOperand - If this target supports it, fold a load or store of the specified stack slot into...
A debug info location.
Definition: DebugLoc.h:34
MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...
Definition: X86BaseInfo.h:87
unsigned getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum, const TargetRegisterInfo *TRI) const override
Inform the ExeDepsFix pass how many idle instructions we would like before certain undef register rea...
int getSPAdjust(const MachineInstr *MI) const override
getSPAdjust - This returns the stack pointer adjustment made by this instruction. ...
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern::MC_PATTERN > &P) const override
Return true when there is potentially a faster code sequence for an instruction chain ending in <Root...
Represents a predicate at the MachineFunction level.
MachineInstr * optimizeLoadInstr(MachineInstr *MI, const MachineRegisterInfo *MRI, unsigned &FoldAsLoadDefReg, MachineInstr *&DefMI) const override
optimizeLoadInstr - Try to remove the load by folding it to a register operand at the use...
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates that the reference is actually...
Definition: X86BaseInfo.h:192
MachineMemOperand - A description of a memory reference used in the backend.
unsigned getJumpInstrTableEntryBound() const override
Provide an instruction scheduling machine model to CodeGen passes.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isUnpredicatedTerminator(const MachineInstr *MI) const override
void getTrap(MCInst &MI) const override
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APInt.h:33
bool isReg() const
isReg - Tests if this is a MO_Register operand.
static bool isGlobalStubReference(unsigned char TargetFlag)
isGlobalStubReference - Return true if the specified TargetFlag operand is a reference to a stub for ...
Definition: X86InstrInfo.h:98
Reg
All possible values of the reg field in the ModR/M byte.
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:159
bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override
isCoalescableExtInstr - Return true if the instruction is a "coalescable" extension instruction...
bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override
isSafeToMoveRegClassDefs - Return true if it's safe to move a machine instruction that defines the sp...
static bool isLeaMem(const MachineInstr *MI, unsigned Op)
Definition: X86InstrInfo.h:135
bool hasHighOperandLatency(const TargetSchedModel &SchedModel, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const override
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:271
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
static bool isGlobalRelativeToPICBase(unsigned char TargetFlag)
isGlobalRelativeToPICBase - Return true if the specified global value reference is relative to a 32-b...
Definition: X86InstrInfo.h:115
AddrNumOperands - Total number of operands in a memory reference.
Definition: X86BaseInfo.h:42
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const override
isStoreToStackSlotPostFE - Check for post-frame ptr elimination stack locations as well...
MO_GOT - On a symbol operand this indicates that the immediate is the offset to the GOT entry for the...
Definition: X86BaseInfo.h:72
bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override
shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction w...
bool getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg, unsigned &Offset, const TargetRegisterInfo *TRI) const override
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: ArrayRef.h:31
bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const override
optimizeCompareInstr - Check if there exists an earlier instruction that operates on the same source ...
int64_t getImm() const
MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the reference is actually to the "...
Definition: X86BaseInfo.h:187
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:150
MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates that the reference is a...
Definition: X86BaseInfo.h:198
bool isX86_64ExtendedReg(unsigned RegNo)
isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or higher) register? e.g.
Definition: X86BaseInfo.h:722
void genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern::MC_PATTERN P, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
When getMachineCombinerPatterns() finds a pattern, this function generates the instructions that coul...
#define P(N)
void breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override
bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const override
analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if h...
void getUnconditionalBranch(MCInst &Branch, const MCSymbolRefExpr *BranchTarget) const override
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
std::pair< uint16_t, uint16_t > getExecutionDomain(const MachineInstr *MI) const override
unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const override
isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well...
MO_TLVP - On a symbol operand this indicates that the immediate is some TLS offset.
Definition: X86BaseInfo.h:204
bundle_iterator - MachineBasicBlock iterator that automatically skips over MIs that are inside bundle...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
static bool isX86_64ExtendedReg(const MachineOperand &MO)
Definition: X86InstrInfo.h:409
X86InstrInfo(X86Subtarget &STI)
unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const override
bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const override
unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a st...
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
bool useMachineCombiner() const override
Definition: X86InstrInfo.h:457
unsigned RemoveBranch(MachineBasicBlock &MBB) const override
bool classifyLEAReg(MachineInstr *MI, const MachineOperand &Src, unsigned LEAOpcode, bool AllowSP, unsigned &NewSrc, bool &isKill, bool &isUndef, MachineOperand &ImplicitOp) const
Given an operand within a MachineInstr, insert preceding code to put it into the right format for a p...
unsigned getSETFromCond(CondCode CC, bool HasMemoryOperand=false)
Return a set opcode for the given condition and whether it has a memory operand.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const
isSafeToClobberEFLAGS - Return true if it's safe insert an instruction tha would clobber the EFLAGS c...
bool shouldScheduleAdjacent(MachineInstr *First, MachineInstr *Second) const override
bool canFoldMemoryOperand(const MachineInstr *, ArrayRef< unsigned >) const override
canFoldMemoryOperand - Returns true if the specified load / store is folding is possible.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:179
MachineOperand class - Representation of each machine instruction operand.
CondCode GetOppositeBranchCondition(CondCode CC)
GetOppositeBranchCondition - Return the inverse of the specified cond, e.g.
unsigned getGlobalBaseReg(MachineFunction *MF) const
getGlobalBaseReg - Return a virtual register initialized with the the global base register value...
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, DebugLoc DL) const override
Represents one node in the SelectionDAG.
void getNoopForMachoTarget(MCInst &NopInst) const override
Return the noop instruction to use for a noop.
MachineInstr * commuteInstruction(MachineInstr *MI, bool NewMI) const override
commuteInstruction - We have a few instructions that must be hacked on to commute them...
MachineInstr * convertToThreeAddress(MachineFunction::iterator &MFI, MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const override
convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_AD...
unsigned getCMovFromCond(CondCode CC, unsigned RegBytes, bool HasMemoryOperand=false)
Return a cmov opcode for the given condition, register size in bytes, and operand type...
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Representation of each machine instruction.
Definition: MachineInstr.h:51
MO_GOTOFF - On a symbol operand this indicates that the immediate is the offset to the location of th...
Definition: X86BaseInfo.h:79
bool AnalyzeBranchPredicate(MachineBasicBlock &MBB, TargetInstrInfo::MachineBranchPredicate &MBP, bool AllowModify=false) const override
unsigned getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override
Inform the ExeDepsFix pass how many idle instructions we would like before a partial register update...
#define I(x, y, z)
Definition: MD5.cpp:54
#define N
static bool isMem(const MachineInstr *MI, unsigned Op)
Definition: X86InstrInfo.h:147
void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, MachineInstr::mmo_iterator MMOBegin, MachineInstr::mmo_iterator MMOEnd, SmallVectorImpl< MachineInstr * > &NewMIs) const
unsigned getReg() const
getReg - Returns the register number.
BasicBlockListType::iterator iterator
MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the immediate should get the value of th...
Definition: X86BaseInfo.h:65
bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override
unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const override
getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new instruction after load / store ar...
MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the reference is actually to the "__imp...
Definition: X86BaseInfo.h:177
bool isReallyTriviallyReMaterializable(const MachineInstr *MI, AliasAnalysis *AA) const override
bool ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override