LLVM  3.7.0
ARMCallingConv.h
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1 //=== ARMCallingConv.h - ARM Custom Calling Convention Routines -*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the custom routines for the ARM Calling Convention that
11 // aren't done by tablegen.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_ARM_ARMCALLINGCONV_H
16 #define LLVM_LIB_TARGET_ARM_ARMCALLINGCONV_H
17 
18 #include "ARM.h"
19 #include "ARMBaseInstrInfo.h"
20 #include "ARMSubtarget.h"
22 #include "llvm/IR/CallingConv.h"
24 
25 namespace llvm {
26 
27 // APCS f64 is in register pairs, possibly split to stack
28 static bool f64AssignAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
29  CCValAssign::LocInfo &LocInfo,
30  CCState &State, bool CanFail) {
31  static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
32 
33  // Try to get the first register.
34  if (unsigned Reg = State.AllocateReg(RegList))
35  State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
36  else {
37  // For the 2nd half of a v2f64, do not fail.
38  if (CanFail)
39  return false;
40 
41  // Put the whole thing on the stack.
42  State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
43  State.AllocateStack(8, 4),
44  LocVT, LocInfo));
45  return true;
46  }
47 
48  // Try to get the second register.
49  if (unsigned Reg = State.AllocateReg(RegList))
50  State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
51  else
52  State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
53  State.AllocateStack(4, 4),
54  LocVT, LocInfo));
55  return true;
56 }
57 
58 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
59  CCValAssign::LocInfo &LocInfo,
60  ISD::ArgFlagsTy &ArgFlags,
61  CCState &State) {
62  if (!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
63  return false;
64  if (LocVT == MVT::v2f64 &&
65  !f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
66  return false;
67  return true; // we handled it
68 }
69 
70 // AAPCS f64 is in aligned register pairs
71 static bool f64AssignAAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
72  CCValAssign::LocInfo &LocInfo,
73  CCState &State, bool CanFail) {
74  static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 };
75  static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 };
76  static const MCPhysReg ShadowRegList[] = { ARM::R0, ARM::R1 };
77  static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
78 
79  unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList);
80  if (Reg == 0) {
81 
82  // If we had R3 unallocated only, now we still must to waste it.
83  Reg = State.AllocateReg(GPRArgRegs);
84  assert((!Reg || Reg == ARM::R3) && "Wrong GPRs usage for f64");
85 
86  // For the 2nd half of a v2f64, do not just fail.
87  if (CanFail)
88  return false;
89 
90  // Put the whole thing on the stack.
91  State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
92  State.AllocateStack(8, 8),
93  LocVT, LocInfo));
94  return true;
95  }
96 
97  unsigned i;
98  for (i = 0; i < 2; ++i)
99  if (HiRegList[i] == Reg)
100  break;
101 
102  unsigned T = State.AllocateReg(LoRegList[i]);
103  (void)T;
104  assert(T == LoRegList[i] && "Could not allocate register");
105 
106  State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
107  State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
108  LocVT, LocInfo));
109  return true;
110 }
111 
112 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
113  CCValAssign::LocInfo &LocInfo,
114  ISD::ArgFlagsTy &ArgFlags,
115  CCState &State) {
116  if (!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
117  return false;
118  if (LocVT == MVT::v2f64 &&
119  !f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
120  return false;
121  return true; // we handled it
122 }
123 
124 static bool f64RetAssign(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
125  CCValAssign::LocInfo &LocInfo, CCState &State) {
126  static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 };
127  static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 };
128 
129  unsigned Reg = State.AllocateReg(HiRegList, LoRegList);
130  if (Reg == 0)
131  return false; // we didn't handle it
132 
133  unsigned i;
134  for (i = 0; i < 2; ++i)
135  if (HiRegList[i] == Reg)
136  break;
137 
138  State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
139  State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
140  LocVT, LocInfo));
141  return true;
142 }
143 
144 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
145  CCValAssign::LocInfo &LocInfo,
146  ISD::ArgFlagsTy &ArgFlags,
147  CCState &State) {
148  if (!f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
149  return false;
150  if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
151  return false;
152  return true; // we handled it
153 }
154 
155 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
156  CCValAssign::LocInfo &LocInfo,
157  ISD::ArgFlagsTy &ArgFlags,
158  CCState &State) {
159  return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags,
160  State);
161 }
162 
163 static const uint16_t RRegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
164 
165 static const uint16_t SRegList[] = { ARM::S0, ARM::S1, ARM::S2, ARM::S3,
166  ARM::S4, ARM::S5, ARM::S6, ARM::S7,
167  ARM::S8, ARM::S9, ARM::S10, ARM::S11,
168  ARM::S12, ARM::S13, ARM::S14, ARM::S15 };
169 static const uint16_t DRegList[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3,
170  ARM::D4, ARM::D5, ARM::D6, ARM::D7 };
171 static const uint16_t QRegList[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3 };
172 
173 
174 // Allocate part of an AAPCS HFA or HVA. We assume that each member of the HA
175 // has InConsecutiveRegs set, and that the last member also has
176 // InConsecutiveRegsLast set. We must process all members of the HA before
177 // we can allocate it, as we need to know the total number of registers that
178 // will be needed in order to (attempt to) allocate a contiguous block.
179 static bool CC_ARM_AAPCS_Custom_Aggregate(unsigned &ValNo, MVT &ValVT,
180  MVT &LocVT,
181  CCValAssign::LocInfo &LocInfo,
182  ISD::ArgFlagsTy &ArgFlags,
183  CCState &State) {
184  SmallVectorImpl<CCValAssign> &PendingMembers = State.getPendingLocs();
185 
186  // AAPCS HFAs must have 1-4 elements, all of the same type
187  if (PendingMembers.size() > 0)
188  assert(PendingMembers[0].getLocVT() == LocVT);
189 
190  // Add the argument to the list to be allocated once we know the size of the
191  // aggregate. Store the type's required alignmnent as extra info for later: in
192  // the [N x i64] case all trace has been removed by the time we actually get
193  // to do allocation.
194  PendingMembers.push_back(CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo,
195  ArgFlags.getOrigAlign()));
196 
197  if (!ArgFlags.isInConsecutiveRegsLast())
198  return true;
199 
200  // Try to allocate a contiguous block of registers, each of the correct
201  // size to hold one member.
202  unsigned Align = std::min(PendingMembers[0].getExtraInfo(), 8U);
203 
204  ArrayRef<uint16_t> RegList;
205  switch (LocVT.SimpleTy) {
206  case MVT::i32: {
207  RegList = RRegList;
208  unsigned RegIdx = State.getFirstUnallocated(RegList);
209 
210  // First consume all registers that would give an unaligned object. Whether
211  // we go on stack or in regs, no-one will be using them in future.
212  unsigned RegAlign = RoundUpToAlignment(Align, 4) / 4;
213  while (RegIdx % RegAlign != 0 && RegIdx < RegList.size())
214  State.AllocateReg(RegList[RegIdx++]);
215 
216  break;
217  }
218  case MVT::f32:
219  RegList = SRegList;
220  break;
221  case MVT::f64:
222  RegList = DRegList;
223  break;
224  case MVT::v2f64:
225  RegList = QRegList;
226  break;
227  default:
228  llvm_unreachable("Unexpected member type for block aggregate");
229  break;
230  }
231 
232  unsigned RegResult = State.AllocateRegBlock(RegList, PendingMembers.size());
233  if (RegResult) {
234  for (SmallVectorImpl<CCValAssign>::iterator It = PendingMembers.begin();
235  It != PendingMembers.end(); ++It) {
236  It->convertToReg(RegResult);
237  State.addLoc(*It);
238  ++RegResult;
239  }
240  PendingMembers.clear();
241  return true;
242  }
243 
244  // Register allocation failed, we'll be needing the stack
245  unsigned Size = LocVT.getSizeInBits() / 8;
246  if (LocVT == MVT::i32 && State.getNextStackOffset() == 0) {
247  // If nothing else has used the stack until this point, a non-HFA aggregate
248  // can be split between regs and stack.
249  unsigned RegIdx = State.getFirstUnallocated(RegList);
250  for (auto &It : PendingMembers) {
251  if (RegIdx >= RegList.size())
252  It.convertToMem(State.AllocateStack(Size, Size));
253  else
254  It.convertToReg(State.AllocateReg(RegList[RegIdx++]));
255 
256  State.addLoc(It);
257  }
258  PendingMembers.clear();
259  return true;
260  } else if (LocVT != MVT::i32)
261  RegList = SRegList;
262 
263  // Mark all regs as unavailable (AAPCS rule C.2.vfp for VFP, C.6 for core)
264  for (auto Reg : RegList)
265  State.AllocateReg(Reg);
266 
267  for (auto &It : PendingMembers) {
268  It.convertToMem(State.AllocateStack(Size, Align));
269  State.addLoc(It);
270 
271  // After the first item has been allocated, the rest are packed as tightly
272  // as possible. (E.g. an incoming i64 would have starting Align of 8, but
273  // we'll be allocating a bunch of i32 slots).
274  Align = Size;
275  }
276 
277  // All pending members have now been allocated
278  PendingMembers.clear();
279 
280  // This will be allocated by the last member of the aggregate
281  return true;
282 }
283 
284 } // End llvm namespace
285 
286 #endif
static CCValAssign getPending(unsigned ValNo, MVT ValVT, MVT LocVT, LocInfo HTP, unsigned ExtraInfo=0)
static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
unsigned getSizeInBits() const
#define R2(n)
static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
static bool f64AssignAAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, CCState &State, bool CanFail)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APInt.h:33
void addLoc(const CCValAssign &V)
Reg
All possible values of the reg field in the ModR/M byte.
SimpleValueType SimpleTy
Number of individual test Apply this number of consecutive mutations to each input exit after the first new interesting input is found the minimized corpus is saved into the first input directory Number of jobs to run If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
static bool f64AssignAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, CCState &State, bool CanFail)
SmallVectorImpl< llvm::CCValAssign > & getPendingLocs()
static const uint16_t QRegList[]
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: ArrayRef.h:31
bool isInConsecutiveRegsLast() const
static const uint16_t RRegList[]
static const MCPhysReg GPRArgRegs[]
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:134
unsigned AllocateRegBlock(ArrayRef< uint16_t > Regs, unsigned RegsRequired)
AllocateRegBlock - Attempt to allocate a block of RegsRequired consecutive registers.
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set, or Regs.size() if they are all allocated.
MVT - Machine Value Type.
static bool f64RetAssign(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, CCState &State)
static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
unsigned getNextStackOffset() const
static bool CC_ARM_AAPCS_Custom_Aggregate(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
CCState - This class holds information needed while lowering arguments and return values...
static const uint16_t SRegList[]
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
uint64_t RoundUpToAlignment(uint64_t Value, uint64_t Align)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
Definition: MathExtras.h:609
static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
static CCValAssign getCustomMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
static const uint16_t DRegList[]
unsigned getOrigAlign() const
unsigned AllocateReg(unsigned Reg)
AllocateReg - Attempt to allocate one register.
unsigned AllocateStack(unsigned Size, unsigned Align)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.