LLVM  3.7.0
llvm::X86InstrInfo Member List

This is the complete list of members for llvm::X86InstrInfo, including all inherited members.

AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const overridellvm::X86InstrInfo
AnalyzeBranchPredicate(MachineBasicBlock &MBB, TargetInstrInfo::MachineBranchPredicate &MBP, bool AllowModify=false) const overridellvm::X86InstrInfo
analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const overridellvm::X86InstrInfo
areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const overridellvm::X86InstrInfo
breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum, const TargetRegisterInfo *TRI) const overridellvm::X86InstrInfo
canFoldMemoryOperand(const MachineInstr *, ArrayRef< unsigned >) const overridellvm::X86InstrInfo
canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const overridellvm::X86InstrInfo
classifyLEAReg(MachineInstr *MI, const MachineOperand &Src, unsigned LEAOpcode, bool AllowSP, unsigned &NewSrc, bool &isKill, bool &isUndef, MachineOperand &ImplicitOp) const llvm::X86InstrInfo
commuteInstruction(MachineInstr *MI, bool NewMI) const overridellvm::X86InstrInfo
convertToThreeAddress(MachineFunction::iterator &MFI, MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const overridellvm::X86InstrInfo
copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const overridellvm::X86InstrInfo
expandPostRAPseudo(MachineBasicBlock::iterator MI) const overridellvm::X86InstrInfo
findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const overridellvm::X86InstrInfo
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex) const overridellvm::X86InstrInfo
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr *LoadMI) const overridellvm::X86InstrInfo
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, unsigned OpNum, ArrayRef< MachineOperand > MOs, MachineBasicBlock::iterator InsertPt, unsigned Size, unsigned Alignment, bool AllowCommute) const llvm::X86InstrInfo
genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern::MC_PATTERN P, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const overridellvm::X86InstrInfo
getExecutionDomain(const MachineInstr *MI) const overridellvm::X86InstrInfo
getGlobalBaseReg(MachineFunction *MF) const llvm::X86InstrInfo
getJumpInstrTableEntryBound() const overridellvm::X86InstrInfo
getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern::MC_PATTERN > &P) const overridellvm::X86InstrInfo
getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg, unsigned &Offset, const TargetRegisterInfo *TRI) const overridellvm::X86InstrInfo
getNoopForMachoTarget(MCInst &NopInst) const overridellvm::X86InstrInfo
getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const overridellvm::X86InstrInfo
getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum, const TargetRegisterInfo *TRI) const overridellvm::X86InstrInfo
getRegisterInfo() const llvm::X86InstrInfoinline
getSPAdjust(const MachineInstr *MI) const overridellvm::X86InstrInfo
getTrap(MCInst &MI) const overridellvm::X86InstrInfo
getUnconditionalBranch(MCInst &Branch, const MCSymbolRefExpr *BranchTarget) const overridellvm::X86InstrInfo
getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum, const TargetRegisterInfo *TRI) const overridellvm::X86InstrInfo
hasHighOperandLatency(const TargetSchedModel &SchedModel, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const overridellvm::X86InstrInfo
InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, DebugLoc DL) const overridellvm::X86InstrInfo
insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const overridellvm::X86InstrInfo
isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const overridellvm::X86InstrInfo
isHighLatencyDef(int opc) const overridellvm::X86InstrInfo
isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const overridellvm::X86InstrInfo
isLoadFromStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const overridellvm::X86InstrInfo
isReallyTriviallyReMaterializable(const MachineInstr *MI, AliasAnalysis *AA) const overridellvm::X86InstrInfo
isSafeToClobberEFLAGS(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const llvm::X86InstrInfo
isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const overridellvm::X86InstrInfo
isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const overridellvm::X86InstrInfo
isStoreToStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const overridellvm::X86InstrInfo
isUnpredicatedTerminator(const MachineInstr *MI) const overridellvm::X86InstrInfo
isX86_64ExtendedReg(const MachineOperand &MO)llvm::X86InstrInfoinlinestatic
loadRegFromAddr(MachineFunction &MF, unsigned DestReg, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, MachineInstr::mmo_iterator MMOBegin, MachineInstr::mmo_iterator MMOEnd, SmallVectorImpl< MachineInstr * > &NewMIs) const llvm::X86InstrInfo
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const overridellvm::X86InstrInfo
optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const overridellvm::X86InstrInfo
optimizeLoadInstr(MachineInstr *MI, const MachineRegisterInfo *MRI, unsigned &FoldAsLoadDefReg, MachineInstr *&DefMI) const overridellvm::X86InstrInfo
reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SubIdx, const MachineInstr *Orig, const TargetRegisterInfo &TRI) const overridellvm::X86InstrInfo
RemoveBranch(MachineBasicBlock &MBB) const overridellvm::X86InstrInfo
ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const overridellvm::X86InstrInfo
setExecutionDomain(MachineInstr *MI, unsigned Domain) const overridellvm::X86InstrInfo
shouldScheduleAdjacent(MachineInstr *First, MachineInstr *Second) const overridellvm::X86InstrInfo
shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const overridellvm::X86InstrInfo
storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, MachineInstr::mmo_iterator MMOBegin, MachineInstr::mmo_iterator MMOEnd, SmallVectorImpl< MachineInstr * > &NewMIs) const llvm::X86InstrInfo
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const overridellvm::X86InstrInfo
unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const overridellvm::X86InstrInfo
unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, SmallVectorImpl< SDNode * > &NewNodes) const overridellvm::X86InstrInfo
useMachineCombiner() const overridellvm::X86InstrInfoinline
X86InstrInfo(X86Subtarget &STI)llvm::X86InstrInfoexplicit