32 #define DEBUG_TYPE "hexagon-instrinfo"
34 #define GET_INSTRINFO_CTOR_DTOR
35 #define GET_INSTRMAP_INFO
36 #include "HexagonGenInstrInfo.inc"
37 #include "HexagonGenDFAPacketizer.inc"
62 void HexagonInstrInfo::anchor() {}
66 RI(), Subtarget(ST) {}
79 case Hexagon::L2_loadri_io:
80 case Hexagon::L2_loadrd_io:
81 case Hexagon::L2_loadrh_io:
82 case Hexagon::L2_loadrb_io:
83 case Hexagon::L2_loadrub_io:
104 case Hexagon::S2_storeri_io:
105 case Hexagon::S2_storerd_io:
106 case Hexagon::S2_storerh_io:
107 case Hexagon::S2_storerb_io:
127 if (EndLoopOp == Hexagon::ENDLOOP0) {
128 LOOPi = Hexagon::J2_loop0i;
129 LOOPr = Hexagon::J2_loop0r;
131 LOOPi = Hexagon::J2_loop1i;
132 LOOPr = Hexagon::J2_loop1r;
137 PE = BB->
pred_end(); PB != PE; ++PB) {
139 if (!Visited.
insert(*PB).second)
144 E = (*PB)->instr_rend();
I != E; ++
I) {
145 int Opc =
I->getOpcode();
146 if (Opc == LOOPi || Opc == LOOPr)
149 if (Opc == EndLoopOp)
165 Opcode_t BccOpc = Hexagon::J2_jumpt;
167 assert(TBB &&
"InsertBranch must not be told to insert a fallthrough");
172 if (!Cond.
empty() && Cond[0].isImm())
173 BccOpc = Cond[0].getImm();
188 if (NewTBB == NextBB) {
196 int EndLoopOp = Cond[0].getImm();
197 assert(Cond[1].isMBB());
202 assert(Loop != 0 &&
"Inserting an ENDLOOP without a LOOP");
207 assert((Cond.
size() == 3) &&
"Only supporting rr/ri version of nvjump");
213 if (Cond[2].
isReg()) {
217 }
else if(Cond[2].isImm()) {
219 addImm(Cond[2].getImm()).
addMBB(TBB);
223 assert((Cond.
size() == 2) &&
"Malformed cond vector");
230 assert((!Cond.
empty()) &&
231 "Cond. cannot be empty when multiple branchings are required");
233 "NV-jump cannot be inserted with another branch");
236 int EndLoopOp = Cond[0].getImm();
237 assert(Cond[1].isMBB());
242 assert(Loop != 0 &&
"Inserting an ENDLOOP without a LOOP");
280 bool AllowModify)
const {
312 while (I->isDebugValue()) {
318 bool JumpToBlock = I->getOpcode() == Hexagon::J2_jump &&
319 I->getOperand(0).isMBB();
321 if (AllowModify && JumpToBlock &&
323 DEBUG(
dbgs()<<
"\nErasing the jump to successor block\n";);
324 I->eraseFromParent();
330 if (!isUnpredicatedTerminator(I))
338 if (&*I != LastInst && !I->
isBundle() && isUnpredicatedTerminator(I)) {
351 int SecLastOpcode = SecondLastInst ? SecondLastInst->
getOpcode() : 0;
354 if (LastOpcode == Hexagon::J2_jump && !LastInst->
getOperand(0).
isMBB())
356 if (SecLastOpcode == Hexagon::J2_jump &&
364 if (LastInst && !SecondLastInst) {
365 if (LastOpcode == Hexagon::J2_jump) {
375 if (LastOpcodeHasJMP_c) {
390 <<
" with one jump\n";);
397 if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) {
406 if (SecLastOpcodeHasNVJump &&
408 (LastOpcode == Hexagon::J2_jump)) {
419 if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) {
428 if (
isEndLoopN(SecLastOpcode) && LastOpcode == Hexagon::J2_jump) {
436 <<
" with two jumps";);
445 while (I != MBB.
begin()) {
447 if (I->isDebugValue())
452 if (Count && (I->getOpcode() == Hexagon::J2_jump))
466 unsigned &SrcReg,
unsigned &SrcReg2,
467 int &Mask,
int &
Value)
const {
472 case Hexagon::C2_cmpeq:
473 case Hexagon::C2_cmpeqp:
474 case Hexagon::C2_cmpgt:
475 case Hexagon::C2_cmpgtp:
476 case Hexagon::C2_cmpgtu:
477 case Hexagon::C2_cmpgtup:
478 case Hexagon::C4_cmpneq:
479 case Hexagon::C4_cmplte:
480 case Hexagon::C4_cmplteu:
481 case Hexagon::C2_cmpeqi:
482 case Hexagon::C2_cmpgti:
483 case Hexagon::C2_cmpgtui:
484 case Hexagon::C4_cmpneqi:
485 case Hexagon::C4_cmplteui:
486 case Hexagon::C4_cmpltei:
490 case Hexagon::A4_cmpbeq:
491 case Hexagon::A4_cmpbgt:
492 case Hexagon::A4_cmpbgtu:
493 case Hexagon::A4_cmpbeqi:
494 case Hexagon::A4_cmpbgti:
495 case Hexagon::A4_cmpbgtui:
499 case Hexagon::A4_cmpheq:
500 case Hexagon::A4_cmphgt:
501 case Hexagon::A4_cmphgtu:
502 case Hexagon::A4_cmpheqi:
503 case Hexagon::A4_cmphgti:
504 case Hexagon::A4_cmphgtui:
512 case Hexagon::C2_cmpeq:
513 case Hexagon::C2_cmpeqp:
514 case Hexagon::C2_cmpgt:
515 case Hexagon::C2_cmpgtp:
516 case Hexagon::C2_cmpgtu:
517 case Hexagon::C2_cmpgtup:
518 case Hexagon::A4_cmpbeq:
519 case Hexagon::A4_cmpbgt:
520 case Hexagon::A4_cmpbgtu:
521 case Hexagon::A4_cmpheq:
522 case Hexagon::A4_cmphgt:
523 case Hexagon::A4_cmphgtu:
524 case Hexagon::C4_cmpneq:
525 case Hexagon::C4_cmplte:
526 case Hexagon::C4_cmplteu:
530 case Hexagon::C2_cmpeqi:
531 case Hexagon::C2_cmpgtui:
532 case Hexagon::C2_cmpgti:
533 case Hexagon::C4_cmpneqi:
534 case Hexagon::C4_cmplteui:
535 case Hexagon::C4_cmpltei:
536 case Hexagon::A4_cmpbeqi:
537 case Hexagon::A4_cmpbgti:
538 case Hexagon::A4_cmpbgtui:
539 case Hexagon::A4_cmpheqi:
540 case Hexagon::A4_cmphgti:
541 case Hexagon::A4_cmphgtui:
553 unsigned DestReg,
unsigned SrcReg,
554 bool KillSrc)
const {
555 if (Hexagon::IntRegsRegClass.
contains(SrcReg, DestReg)) {
556 BuildMI(MBB, I, DL,
get(Hexagon::A2_tfr), DestReg).
addReg(SrcReg);
559 if (Hexagon::DoubleRegsRegClass.
contains(SrcReg, DestReg)) {
560 BuildMI(MBB, I, DL,
get(Hexagon::A2_tfrp), DestReg).
addReg(SrcReg);
563 if (Hexagon::PredRegsRegClass.
contains(SrcReg, DestReg)) {
565 BuildMI(MBB, I, DL,
get(Hexagon::C2_or),
569 if (Hexagon::DoubleRegsRegClass.
contains(DestReg) &&
570 Hexagon::IntRegsRegClass.
contains(SrcReg)) {
572 if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) {
574 BuildMI(MBB, I, DL,
get(Hexagon::A2_tfrsi), (RI.getSubReg(DestReg,
575 Hexagon::subreg_hireg))).
addImm(0);
578 BuildMI(MBB, I, DL,
get(Hexagon::A2_tfr), (RI.getSubReg(DestReg,
579 Hexagon::subreg_loreg))).
addReg(SrcReg);
580 BuildMI(MBB, I, DL,
get(Hexagon::A2_tfrsi), (RI.getSubReg(DestReg,
581 Hexagon::subreg_hireg))).
addImm(0);
585 if (Hexagon::CtrRegsRegClass.
contains(DestReg) &&
586 Hexagon::IntRegsRegClass.
contains(SrcReg)) {
587 BuildMI(MBB, I, DL,
get(Hexagon::A2_tfrrcr), DestReg).
addReg(SrcReg);
590 if (Hexagon::PredRegsRegClass.
contains(SrcReg) &&
591 Hexagon::IntRegsRegClass.
contains(DestReg)) {
592 BuildMI(MBB, I, DL,
get(Hexagon::C2_tfrpr), DestReg).
596 if (Hexagon::IntRegsRegClass.
contains(SrcReg) &&
597 Hexagon::PredRegsRegClass.
contains(DestReg)) {
598 BuildMI(MBB, I, DL,
get(Hexagon::C2_tfrrp), DestReg).
609 unsigned SrcReg,
bool isKill,
int FI,
625 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
626 BuildMI(MBB, I, DL,
get(Hexagon::S2_storeri_io))
629 }
else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
630 BuildMI(MBB, I, DL,
get(Hexagon::S2_storerd_io))
633 }
else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
634 BuildMI(MBB, I, DL,
get(Hexagon::STriw_pred))
656 unsigned DestReg,
int FI,
670 if (RC == &Hexagon::IntRegsRegClass) {
671 BuildMI(MBB, I, DL,
get(Hexagon::L2_loadri_io), DestReg)
673 }
else if (RC == &Hexagon::DoubleRegsRegClass) {
674 BuildMI(MBB, I, DL,
get(Hexagon::L2_loadrd_io), DestReg)
676 }
else if (RC == &Hexagon::PredRegsRegClass) {
677 BuildMI(MBB, I, DL,
get(Hexagon::LDriw_pred), DestReg)
697 unsigned Opc = MI->getOpcode();
700 case Hexagon::ALIGNA:
703 .addImm(-MI->getOperand(1).getImm());
706 case Hexagon::TFR_PdTrue: {
707 unsigned Reg = MI->getOperand(0).getReg();
708 BuildMI(MBB, MI, DL,
get(Hexagon::C2_orn), Reg)
714 case Hexagon::TFR_PdFalse: {
715 unsigned Reg = MI->getOperand(0).getReg();
716 BuildMI(MBB, MI, DL,
get(Hexagon::C2_andn), Reg)
722 case Hexagon::VMULW: {
724 unsigned DstReg = MI->getOperand(0).getReg();
725 unsigned Src1Reg = MI->getOperand(1).getReg();
726 unsigned Src2Reg = MI->getOperand(2).getReg();
727 unsigned Src1SubHi = TRI.getSubReg(Src1Reg, Hexagon::subreg_hireg);
728 unsigned Src1SubLo = TRI.getSubReg(Src1Reg, Hexagon::subreg_loreg);
729 unsigned Src2SubHi = TRI.getSubReg(Src2Reg, Hexagon::subreg_hireg);
730 unsigned Src2SubLo = TRI.getSubReg(Src2Reg, Hexagon::subreg_loreg);
731 BuildMI(MBB, MI, MI->getDebugLoc(),
get(Hexagon::M2_mpyi),
732 TRI.getSubReg(DstReg, Hexagon::subreg_hireg)).addReg(Src1SubHi)
734 BuildMI(MBB, MI, MI->getDebugLoc(),
get(Hexagon::M2_mpyi),
735 TRI.getSubReg(DstReg, Hexagon::subreg_loreg)).addReg(Src1SubLo)
744 case Hexagon::VMULW_ACC: {
746 unsigned DstReg = MI->getOperand(0).getReg();
747 unsigned Src1Reg = MI->getOperand(1).getReg();
748 unsigned Src2Reg = MI->getOperand(2).getReg();
749 unsigned Src3Reg = MI->getOperand(3).getReg();
750 unsigned Src1SubHi = TRI.getSubReg(Src1Reg, Hexagon::subreg_hireg);
751 unsigned Src1SubLo = TRI.getSubReg(Src1Reg, Hexagon::subreg_loreg);
752 unsigned Src2SubHi = TRI.getSubReg(Src2Reg, Hexagon::subreg_hireg);
753 unsigned Src2SubLo = TRI.getSubReg(Src2Reg, Hexagon::subreg_loreg);
754 unsigned Src3SubHi = TRI.getSubReg(Src3Reg, Hexagon::subreg_hireg);
755 unsigned Src3SubLo = TRI.getSubReg(Src3Reg, Hexagon::subreg_loreg);
756 BuildMI(MBB, MI, MI->getDebugLoc(),
get(Hexagon::M2_maci),
757 TRI.getSubReg(DstReg, Hexagon::subreg_hireg)).addReg(Src1SubHi)
759 BuildMI(MBB, MI, MI->getDebugLoc(),
get(Hexagon::M2_maci),
760 TRI.getSubReg(DstReg, Hexagon::subreg_loreg)).addReg(Src1SubLo)
771 case Hexagon::TCRETURNi:
772 MI->setDesc(
get(Hexagon::J2_jump));
774 case Hexagon::TCRETURNr:
775 MI->setDesc(
get(Hexagon::J2_jumpr));
794 TRC = &Hexagon::PredRegsRegClass;
796 TRC = &Hexagon::IntRegsRegClass;
798 TRC = &Hexagon::DoubleRegsRegClass;
817 case Hexagon::TFR_FI:
863 const uint64_t
F =
get(Opcode).TSFlags;
868 return MI->
getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4;
880 case Hexagon::A2_tfrsi:
883 case Hexagon::S2_storerd_io:
886 case Hexagon::S2_storeri_io:
887 case Hexagon::S2_storerinew_io:
890 case Hexagon::S2_storerh_io:
891 case Hexagon::S2_storerhnew_io:
894 case Hexagon::S2_storerb_io:
895 case Hexagon::S2_storerbnew_io:
898 case Hexagon::L2_loadrd_io:
901 case Hexagon::L2_loadri_io:
904 case Hexagon::L2_loadrh_io:
905 case Hexagon::L2_loadruh_io:
908 case Hexagon::L2_loadrb_io:
909 case Hexagon::L2_loadrub_io:
912 case Hexagon::L2_loadrd_pi:
915 case Hexagon::L2_loadri_pi:
918 case Hexagon::L2_loadrh_pi:
919 case Hexagon::L2_loadruh_pi:
922 case Hexagon::L2_loadrb_pi:
923 case Hexagon::L2_loadrub_pi:
926 case Hexagon::S4_storeirb_io:
927 case Hexagon::S4_storeirh_io:
928 case Hexagon::S4_storeiri_io:
932 case Hexagon::A2_addi:
935 case Hexagon::A2_aslh:
936 case Hexagon::A2_asrh:
937 case Hexagon::A2_sxtb:
938 case Hexagon::A2_sxth:
939 case Hexagon::A2_zxtb:
940 case Hexagon::A2_zxth:
955 : Hexagon::getTruePredOpcode(Opc);
956 if (InvPredOpcode >= 0)
957 return InvPredOpcode;
961 case Hexagon::C2_ccombinewt:
962 return Hexagon::C2_ccombinewf;
963 case Hexagon::C2_ccombinewf:
964 return Hexagon::C2_ccombinewt;
967 case Hexagon::L4_return_t:
968 return Hexagon::L4_return_f;
969 case Hexagon::L4_return_f:
970 return Hexagon::L4_return_t;
982 const uint64_t
F =
get(Opcode).TSFlags;
988 enum Hexagon::PredSense inPredSense;
989 inPredSense = invertPredicate ? Hexagon::PredSense_false :
990 Hexagon::PredSense_true;
991 int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
998 case Hexagon::TFRI_f:
999 return !invertPredicate ? Hexagon::TFRI_cPt_f :
1000 Hexagon::TFRI_cNotPt_f;
1001 case Hexagon::A2_combinew:
1002 return !invertPredicate ? Hexagon::C2_ccombinewt :
1003 Hexagon::C2_ccombinewf;
1006 case Hexagon::L4_return:
1007 return !invertPredicate ? Hexagon::L4_return_t:
1008 Hexagon::L4_return_f;
1022 assert (
isPredicable(MI) &&
"Expected predicable instruction");
1035 while (NOp < NumOps) {
1043 unsigned PredReg, PredRegPos, PredRegFlags;
1044 bool GotPredReg =
getPredReg(Cond, PredReg, PredRegPos, PredRegFlags);
1047 T.
addReg(PredReg, PredRegFlags);
1048 while (NOp < NumOps)
1071 unsigned ExtraPredCycles,
1080 unsigned NumTCycles,
1081 unsigned ExtraTCycles,
1083 unsigned NumFCycles,
1084 unsigned ExtraFCycles,
1102 const uint64_t
F =
get(Opcode).TSFlags;
1116 const uint64_t
F =
get(Opcode).TSFlags;
1132 const uint64_t
F =
get(Opcode).TSFlags;
1148 std::vector<MachineOperand> &Pred)
const {
1153 if (RC == &Hexagon::PredRegsRegClass) {
1180 assert(Cond[0].isImm() &&
"First entry in the cond vector not imm-val");
1181 Opcode_t opcode = Cond[0].getImm();
1183 assert(
get(opcode).
isBranch() &&
"Should be a branching condition.");
1187 Cond[0].setImm(NewOpcode);
1195 return (NumInstrs <= 4);
1200 default:
return false;
1201 case Hexagon::L4_return:
1202 case Hexagon::L4_return_t:
1203 case Hexagon::L4_return_f:
1204 case Hexagon::L4_return_tnew_pnt:
1205 case Hexagon::L4_return_fnew_pnt:
1206 case Hexagon::L4_return_tnew_pt:
1207 case Hexagon::L4_return_fnew_pt:
1214 bool Extend)
const {
1225 case Hexagon::J2_loop0i:
1226 case Hexagon::J2_loop1i:
1227 return isUInt<10>(Offset);
1234 case Hexagon::L2_loadri_io:
1235 case Hexagon::S2_storeri_io:
1239 case Hexagon::L2_loadrd_io:
1240 case Hexagon::S2_storerd_io:
1244 case Hexagon::L2_loadrh_io:
1245 case Hexagon::L2_loadruh_io:
1246 case Hexagon::S2_storerh_io:
1250 case Hexagon::L2_loadrb_io:
1251 case Hexagon::S2_storerb_io:
1252 case Hexagon::L2_loadrub_io:
1256 case Hexagon::A2_addi:
1260 case Hexagon::L4_iadd_memopw_io:
1261 case Hexagon::L4_isub_memopw_io:
1262 case Hexagon::L4_add_memopw_io:
1263 case Hexagon::L4_sub_memopw_io:
1264 case Hexagon::L4_and_memopw_io:
1265 case Hexagon::L4_or_memopw_io:
1266 return (0 <= Offset && Offset <= 255);
1268 case Hexagon::L4_iadd_memoph_io:
1269 case Hexagon::L4_isub_memoph_io:
1270 case Hexagon::L4_add_memoph_io:
1271 case Hexagon::L4_sub_memoph_io:
1272 case Hexagon::L4_and_memoph_io:
1273 case Hexagon::L4_or_memoph_io:
1274 return (0 <= Offset && Offset <= 127);
1276 case Hexagon::L4_iadd_memopb_io:
1277 case Hexagon::L4_isub_memopb_io:
1278 case Hexagon::L4_add_memopb_io:
1279 case Hexagon::L4_sub_memopb_io:
1280 case Hexagon::L4_and_memopb_io:
1281 case Hexagon::L4_or_memopb_io:
1282 return (0 <= Offset && Offset <= 63);
1286 case Hexagon::STriw_pred:
1287 case Hexagon::LDriw_pred:
1290 case Hexagon::TFR_FI:
1291 case Hexagon::TFR_FIA:
1297 "Please define it in the above switch statement!");
1310 (Offset & 0x7) == 0);
1315 (Offset & 0x3) == 0);
1320 (Offset & 0x1) == 0);
1336 default:
return false;
1337 case Hexagon::L4_iadd_memopw_io:
1338 case Hexagon::L4_isub_memopw_io:
1339 case Hexagon::L4_add_memopw_io:
1340 case Hexagon::L4_sub_memopw_io:
1341 case Hexagon::L4_and_memopw_io:
1342 case Hexagon::L4_or_memopw_io:
1343 case Hexagon::L4_iadd_memoph_io:
1344 case Hexagon::L4_isub_memoph_io:
1345 case Hexagon::L4_add_memoph_io:
1346 case Hexagon::L4_sub_memoph_io:
1347 case Hexagon::L4_and_memoph_io:
1348 case Hexagon::L4_or_memoph_io:
1349 case Hexagon::L4_iadd_memopb_io:
1350 case Hexagon::L4_isub_memopb_io:
1351 case Hexagon::L4_add_memopb_io:
1352 case Hexagon::L4_sub_memopb_io:
1353 case Hexagon::L4_and_memopb_io:
1354 case Hexagon::L4_or_memopb_io:
1355 case Hexagon::L4_ior_memopb_io:
1356 case Hexagon::L4_ior_memoph_io:
1357 case Hexagon::L4_ior_memopw_io:
1358 case Hexagon::L4_iand_memopb_io:
1359 case Hexagon::L4_iand_memoph_io:
1360 case Hexagon::L4_iand_memopw_io:
1370 default:
return false;
1371 case Hexagon::STriw_pred :
1372 case Hexagon::LDriw_pred :
1379 default:
return false;
1380 case Hexagon::C2_cmpeq:
1381 case Hexagon::C2_cmpeqi:
1382 case Hexagon::C2_cmpgt:
1383 case Hexagon::C2_cmpgti:
1384 case Hexagon::C2_cmpgtu:
1385 case Hexagon::C2_cmpgtui:
1393 default:
return false;
1394 case Hexagon::A2_tfrt:
1395 case Hexagon::A2_tfrf:
1396 case Hexagon::C2_cmoveit:
1397 case Hexagon::C2_cmoveif:
1398 case Hexagon::A2_tfrtnew:
1399 case Hexagon::A2_tfrfnew:
1400 case Hexagon::C2_cmovenewit:
1401 case Hexagon::C2_cmovenewif:
1409 default:
return false;
1410 case Hexagon::A2_paddf:
1411 case Hexagon::A2_paddfnew:
1412 case Hexagon::A2_paddt:
1413 case Hexagon::A2_paddtnew:
1414 case Hexagon::A2_pandf:
1415 case Hexagon::A2_pandfnew:
1416 case Hexagon::A2_pandt:
1417 case Hexagon::A2_pandtnew:
1418 case Hexagon::A4_paslhf:
1419 case Hexagon::A4_paslhfnew:
1420 case Hexagon::A4_paslht:
1421 case Hexagon::A4_paslhtnew:
1422 case Hexagon::A4_pasrhf:
1423 case Hexagon::A4_pasrhfnew:
1424 case Hexagon::A4_pasrht:
1425 case Hexagon::A4_pasrhtnew:
1426 case Hexagon::A2_porf:
1427 case Hexagon::A2_porfnew:
1428 case Hexagon::A2_port:
1429 case Hexagon::A2_portnew:
1430 case Hexagon::A2_psubf:
1431 case Hexagon::A2_psubfnew:
1432 case Hexagon::A2_psubt:
1433 case Hexagon::A2_psubtnew:
1434 case Hexagon::A2_pxorf:
1435 case Hexagon::A2_pxorfnew:
1436 case Hexagon::A2_pxort:
1437 case Hexagon::A2_pxortnew:
1438 case Hexagon::A4_psxthf:
1439 case Hexagon::A4_psxthfnew:
1440 case Hexagon::A4_psxtht:
1441 case Hexagon::A4_psxthtnew:
1442 case Hexagon::A4_psxtbf:
1443 case Hexagon::A4_psxtbfnew:
1444 case Hexagon::A4_psxtbt:
1445 case Hexagon::A4_psxtbtnew:
1446 case Hexagon::A4_pzxtbf:
1447 case Hexagon::A4_pzxtbfnew:
1448 case Hexagon::A4_pzxtbt:
1449 case Hexagon::A4_pzxtbtnew:
1450 case Hexagon::A4_pzxthf:
1451 case Hexagon::A4_pzxthfnew:
1452 case Hexagon::A4_pzxtht:
1453 case Hexagon::A4_pzxthtnew:
1454 case Hexagon::A2_paddit:
1455 case Hexagon::A2_paddif:
1456 case Hexagon::C2_ccombinewt:
1457 case Hexagon::C2_ccombinewf:
1466 default:
return false;
1467 case Hexagon::L2_ploadrdt_io :
1468 case Hexagon::L2_ploadrdf_io:
1469 case Hexagon::L2_ploadrit_io:
1470 case Hexagon::L2_ploadrif_io:
1471 case Hexagon::L2_ploadrht_io:
1472 case Hexagon::L2_ploadrhf_io:
1473 case Hexagon::L2_ploadrbt_io:
1474 case Hexagon::L2_ploadrbf_io:
1475 case Hexagon::L2_ploadruht_io:
1476 case Hexagon::L2_ploadruhf_io:
1477 case Hexagon::L2_ploadrubt_io:
1478 case Hexagon::L2_ploadrubf_io:
1479 case Hexagon::L2_ploadrdt_pi:
1480 case Hexagon::L2_ploadrdf_pi:
1481 case Hexagon::L2_ploadrit_pi:
1482 case Hexagon::L2_ploadrif_pi:
1483 case Hexagon::L2_ploadrht_pi:
1484 case Hexagon::L2_ploadrhf_pi:
1485 case Hexagon::L2_ploadrbt_pi:
1486 case Hexagon::L2_ploadrbf_pi:
1487 case Hexagon::L2_ploadruht_pi:
1488 case Hexagon::L2_ploadruhf_pi:
1489 case Hexagon::L2_ploadrubt_pi:
1490 case Hexagon::L2_ploadrubf_pi:
1491 case Hexagon::L4_ploadrdt_rr:
1492 case Hexagon::L4_ploadrdf_rr:
1493 case Hexagon::L4_ploadrbt_rr:
1494 case Hexagon::L4_ploadrbf_rr:
1495 case Hexagon::L4_ploadrubt_rr:
1496 case Hexagon::L4_ploadrubf_rr:
1497 case Hexagon::L4_ploadrht_rr:
1498 case Hexagon::L4_ploadrhf_rr:
1499 case Hexagon::L4_ploadruht_rr:
1500 case Hexagon::L4_ploadruhf_rr:
1501 case Hexagon::L4_ploadrit_rr:
1502 case Hexagon::L4_ploadrif_rr:
1545 default:
return false;
1546 case Hexagon::S4_storeirbt_io:
1547 case Hexagon::S4_storeirbf_io:
1548 case Hexagon::S4_pstorerbt_rr:
1549 case Hexagon::S4_pstorerbf_rr:
1550 case Hexagon::S2_pstorerbt_io:
1551 case Hexagon::S2_pstorerbf_io:
1552 case Hexagon::S2_pstorerbt_pi:
1553 case Hexagon::S2_pstorerbf_pi:
1554 case Hexagon::S2_pstorerdt_io:
1555 case Hexagon::S2_pstorerdf_io:
1556 case Hexagon::S4_pstorerdt_rr:
1557 case Hexagon::S4_pstorerdf_rr:
1558 case Hexagon::S2_pstorerdt_pi:
1559 case Hexagon::S2_pstorerdf_pi:
1560 case Hexagon::S2_pstorerht_io:
1561 case Hexagon::S2_pstorerhf_io:
1562 case Hexagon::S4_storeirht_io:
1563 case Hexagon::S4_storeirhf_io:
1564 case Hexagon::S4_pstorerht_rr:
1565 case Hexagon::S4_pstorerhf_rr:
1566 case Hexagon::S2_pstorerht_pi:
1567 case Hexagon::S2_pstorerhf_pi:
1568 case Hexagon::S2_pstorerit_io:
1569 case Hexagon::S2_pstorerif_io:
1570 case Hexagon::S4_storeirit_io:
1571 case Hexagon::S4_storeirif_io:
1572 case Hexagon::S4_pstorerit_rr:
1573 case Hexagon::S4_pstorerif_rr:
1574 case Hexagon::S2_pstorerit_pi:
1575 case Hexagon::S2_pstorerif_pi:
1578 case Hexagon::S4_pstorerdt_abs:
1579 case Hexagon::S4_pstorerdf_abs:
1580 case Hexagon::S4_pstorerbt_abs:
1581 case Hexagon::S4_pstorerbf_abs:
1582 case Hexagon::S4_pstorerht_abs:
1583 case Hexagon::S4_pstorerhf_abs:
1584 case Hexagon::S4_pstorerit_abs:
1585 case Hexagon::S4_pstorerif_abs:
1652 NewOp = Hexagon::getPredOldOpcode(NewOp);
1653 assert(NewOp >= 0 &&
1654 "Couldn't change predicate new instruction to its old form.");
1658 NewOp = Hexagon::getNonNVStore(NewOp);
1659 assert(NewOp >= 0 &&
"Couldn't change new-value store to its old form.");
1666 int NVOpcode = Hexagon::getNewValueOpcode(MI->
getOpcode());
1672 case Hexagon::S4_storerb_ur:
1673 return Hexagon::S4_storerbnew_ur;
1675 case Hexagon::S4_storerh_ur:
1676 return Hexagon::S4_storerhnew_ur;
1678 case Hexagon::S4_storeri_ur:
1679 return Hexagon::S4_storerinew_ur;
1681 case Hexagon::S2_storerb_pci:
1682 return Hexagon::S2_storerb_pci;
1684 case Hexagon::S2_storeri_pci:
1685 return Hexagon::S2_storeri_pci;
1687 case Hexagon::S2_storerh_pci:
1688 return Hexagon::S2_storerh_pci;
1690 case Hexagon::S2_storerd_pci:
1691 return Hexagon::S2_storerd_pci;
1693 case Hexagon::S2_storerf_pci:
1694 return Hexagon::S2_storerf_pci;
1704 int NewOpcode = Hexagon::getPredNewOpcode(MI->
getOpcode());
1711 case Hexagon::J2_jumpt:
1712 case Hexagon::J2_jumpf:
1715 case Hexagon::J2_jumprt:
1716 return Hexagon::J2_jumptnewpt;
1718 case Hexagon::J2_jumprf:
1719 return Hexagon::J2_jumprfnewpt;
1721 case Hexagon::JMPrett:
1722 return Hexagon::J2_jumprtnewpt;
1724 case Hexagon::JMPretf:
1725 return Hexagon::J2_jumprfnewpt;
1729 case Hexagon::C2_ccombinewt:
1730 return Hexagon::C2_ccombinewnewt;
1731 case Hexagon::C2_ccombinewf:
1732 return Hexagon::C2_ccombinewnewf;
1747 "Instruction must be extendable");
1753 "Branch with unknown extendable field type");
1817 assert(MO.
isImm() &&
"Extendable operand must be Immediate type");
1821 int ImmValue = MO.
getImm();
1823 return (ImmValue < MinValue || ImmValue > MaxValue);
1866 case Hexagon::J2_jumpt:
1867 return taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
1868 case Hexagon::J2_jumpf:
1869 return taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
1877 unsigned short OperandNum)
const {
1899 return -1U << (bits - 1);
1913 return ~(-1U << (bits - 1));
1915 return ~(-1U << bits);
1925 if (Hexagon::getRegForm(MI->
getOpcode()) >= 0)
1935 NonExtOpcode = Hexagon::getBasedWithImmOffset(MI->
getOpcode());
1941 NonExtOpcode = Hexagon::getBaseWithRegOffset(MI->
getOpcode());
1946 if (NonExtOpcode < 0)
1958 short NonExtOpcode = Hexagon::getRegForm(MI->
getOpcode());
1959 if (NonExtOpcode >= 0)
1960 return NonExtOpcode;
1966 return Hexagon::getBasedWithImmOffset(MI->
getOpcode());
1968 return Hexagon::getBaseWithRegOffset(MI->
getOpcode());
1977 return (Opcode == Hexagon::J2_jumpt) ||
1978 (Opcode == Hexagon::J2_jumpf) ||
1979 (Opcode == Hexagon::J2_jumptnewpt) ||
1980 (Opcode == Hexagon::J2_jumpfnewpt) ||
1981 (Opcode == Hexagon::J2_jumpt) ||
1982 (Opcode == Hexagon::J2_jumpf);
1992 return (Opcode == Hexagon::ENDLOOP0 ||
1993 Opcode == Hexagon::ENDLOOP1);
1997 unsigned &PredReg,
unsigned &PredRegPos,
1998 unsigned &PredRegFlags)
const {
2001 assert(Cond.
size() == 2);
2003 DEBUG(
dbgs() <<
"No predregs for new-value jumps/endloop");
2006 PredReg = Cond[1].getReg();
2010 if (Cond[1].isImplicit())
2012 if (Cond[1].isUndef())
static bool isReg(const MCInst &MI, unsigned OpNo)
bool isSpillPredRegOp(const MachineInstr *MI) const
void push_back(const T &Elt)
bool isConditionalLoad(const MachineInstr *MI) const
The memory access reads data.
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
mop_iterator operands_end()
bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
The memory access writes data.
instr_iterator instr_begin()
const int Hexagon_MEMH_OFFSET_MAX
instr_iterator instr_end()
const int Hexagon_ADDI_OFFSET_MAX
unsigned getFrameRegister(const MachineFunction &MF) const override
const int Hexagon_MEMH_OFFSET_MIN
bool isBranch(const MachineInstr *MI) const
bool isExtendable(const MachineInstr *MI) const
MachineBasicBlock * getMBB() const
int getNumber() const
getNumber - MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a M...
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override
bool mayStore() const
Return true if this instruction could possibly modify memory.
iterator getFirstTerminator()
getFirstTerminator - returns an iterator to the first terminator instruction of this basic block...
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
Describe properties that are true of each instruction in the target description file.
int getMaxValue(const MachineInstr *MI) const
int getDotNewPredJumpOp(MachineInstr *MI, const MachineBranchProbabilityInfo *MBPI) const
const int Hexagon_ADDI_OFFSET_MIN
bool isBlockAddress() const
isBlockAddress - Tests if this is a MO_BlockAddress operand.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
int getMinValue(const MachineInstr *MI) const
bool isEndLoopN(Opcode_t Opcode) const
const int Hexagon_MEMD_OFFSET_MAX
Instructions::iterator instr_iterator
unsigned short getCExtOpNum(const MachineInstr *MI) const
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, unsigned f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
getMachineMemOperand - Allocate a new MachineMemOperand.
bool PredicateInstruction(MachineInstr *MI, ArrayRef< MachineOperand > Cond) const override
bool isPostIncrement(const MachineInstr *MI) const
bool isConditionalTransfer(const MachineInstr *MI) const
bool isPredicatedNew(const MachineInstr *MI) const
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
bool isSchedulingBoundary(const MachineInstr *MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
MachineMemOperand - A description of a memory reference used in the backend.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const override
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot...
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
bool isMemOp(const MachineInstr *MI) const
bool isPredicated(const MachineInstr *MI) const override
unsigned getSize(const MachineInstr *MI) const
int GetDotOldOp(const int opc) const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isInt< 8 >(int64_t x)
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
bool isNewValueJumpCandidate(const MachineInstr *MI) const
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool isTerminator() const
Returns true if this instruction part of the terminator for a basic block.
bool predOpcodeHasNot(ArrayRef< MachineOperand > Cond) const
const int Hexagon_MEMH_AUTOINC_MIN
static const PseudoSourceValue * getFixedStack(int FI)
A pseudo source value referencing a fixed stack frame entry, e.g., a spill slot.
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
const int Hexagon_MEMB_AUTOINC_MAX
virtual const InstrItineraryData * getInstrItineraryData() const
getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget...
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
INLINEASM - Represents an inline asm block.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
const HexagonRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
std::reverse_iterator< instr_iterator > reverse_instr_iterator
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
const int Hexagon_MEMD_AUTOINC_MIN
Itinerary data supplied by a subtarget to be used by a target.
std::vector< MachineBasicBlock * >::iterator pred_iterator
unsigned getInvertedPredicatedOpcode(const int Opc) const
unsigned getUndefRegState(bool B)
size_t size() const
size - Get the array size.
const int Hexagon_MEMW_AUTOINC_MAX
unsigned getAddrMode(const MachineInstr *MI) const
unsigned getKillRegState(bool B)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const int Hexagon_MEMD_OFFSET_MIN
const MachineBasicBlock * getParent() const
bool isDebugValue() const
bundle_iterator< MachineInstr, instr_iterator > iterator
unsigned getTargetFlags() const
const int Hexagon_MEMW_OFFSET_MAX
Constants for Hexagon instructions.
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, const BranchProbability &Probability) const override
const int Hexagon_MEMH_AUTOINC_MAX
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, const BranchProbability &Probability) const override
MVT - Machine Value Type.
unsigned RemoveBranch(MachineBasicBlock &MBB) const override
bool isNewValueStore(const MachineInstr *MI) const
DebugLoc findDebugLoc(instr_iterator MBBI)
findDebugLoc - find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE instructions...
const MachineOperand & getOperand(unsigned i) const
bool ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
void setMBB(MachineBasicBlock *MBB)
bool isSaveCalleeSavedRegsCall(const MachineInstr *MI) const
bool isDeallocRet(const MachineInstr *MI) const
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex) const override
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
bool isNewValueInst(const MachineInstr *MI) const
unsigned createVR(MachineFunction *MF, MVT VT) const
bool isPredicatedTrue(const MachineInstr *MI) const
bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override
expandPostRAPseudo - This function is called for all pseudo instructions that remain after register a...
bool isConstExtended(const MachineInstr *MI) const
void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, SmallVectorImpl< MachineInstr * > &NewMIs) const
bool isConditionalStore(const MachineInstr *MI) const
bool empty() const
empty - Check if the array is empty.
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
int GetDotNewOp(const MachineInstr *MI) const
EVT - Extended Value Type.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
pred_iterator pred_begin()
bool getPredReg(ArrayRef< MachineOperand > Cond, unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const
MachinePointerInfo - This class contains a discriminated union of information about pointers in memor...
const MDOperand & getOperand(unsigned I) const
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
const int Hexagon_MEMW_AUTOINC_MIN
HexagonInstrInfo(HexagonSubtarget &ST)
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
static MachineInstr * findLoopInstr(MachineBasicBlock *BB, int EndLoopOp, SmallPtrSet< MachineBasicBlock *, 8 > &Visited)
bool DefinesPredicate(MachineInstr *MI, std::vector< MachineOperand > &Pred) const override
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
int getCondOpcode(int Opc, bool sense) const
bool mayLoad() const
Return true if this instruction could possibly read memory.
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const MachineInstrBuilder & addFrameIndex(int Idx) const
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
bool isPredicable(MachineInstr *MI) const override
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
int GetDotNewPredOp(MachineInstr *MI, const MachineBranchProbabilityInfo *MBPI) const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
TargetSubtargetInfo - Generic base class for all target subtargets.
bool isExtended(const MachineInstr *MI) const
bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override
For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two registe...
Representation of each machine instruction.
void addTargetFlag(unsigned F)
const int Hexagon_MEMB_OFFSET_MAX
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool isValidAutoIncImm(const EVT VT, const int Offset) const
unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot...
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
static MachineOperand CreateImm(int64_t Val)
void clearKillFlags(unsigned Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
bool isConditionalALU32(const MachineInstr *MI) const
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, DebugLoc DL) const override
const int Hexagon_MEMW_OFFSET_MIN
bool isOperandExtended(const MachineInstr *MI, unsigned short OperandNum) const
short getNonExtOpcode(const MachineInstr *MI) const
unsigned getReg() const
getReg - Returns the register number.
#define HEXAGON_INSTR_SIZE
LLVM Value Representation.
mop_iterator operands_begin()
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
void immediateExtend(MachineInstr *MI) const
immediateExtend - Changes the instruction in place to one using an immediate extender.
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
bool isNewValueJump(const MachineInstr *MI) const
BasicBlockListType::iterator iterator
void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, SmallVectorImpl< MachineInstr * > &NewMIs) const
bool isNewValue(const MachineInstr *MI) const
bool PredOpcodeHasJMP_c(Opcode_t Opcode) const
const int Hexagon_MEMD_AUTOINC_MAX
BranchProbability getEdgeProbability(const MachineBasicBlock *Src, const MachineBasicBlock *Dst) const
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
isLayoutSuccessor - Return true if the specified MBB will be emitted immediately after this block...
bool isValidOffset(unsigned Opcode, int Offset, bool Extend=true) const
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
const int Hexagon_MEMB_AUTOINC_MIN
bool NonExtEquivalentExists(const MachineInstr *MI) const
bool isDotNewInst(const MachineInstr *MI) const
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
const int Hexagon_MEMB_OFFSET_MIN
bool mayBeNewStore(const MachineInstr *MI) const