LLVM  3.7.0
ScheduleDAGSDNodes.h
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1 //===---- ScheduleDAGSDNodes.h - SDNode Scheduling --------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the ScheduleDAGSDNodes class, which implements
11 // scheduling for an SDNode-based dependency graph.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_CODEGEN_SELECTIONDAG_SCHEDULEDAGSDNODES_H
16 #define LLVM_LIB_CODEGEN_SELECTIONDAG_SCHEDULEDAGSDNODES_H
17 
20 
21 namespace llvm {
22  /// ScheduleDAGSDNodes - A ScheduleDAG for scheduling SDNode-based DAGs.
23  ///
24  /// Edges between SUnits are initially based on edges in the SelectionDAG,
25  /// and additional edges can be added by the schedulers as heuristics.
26  /// SDNodes such as Constants, Registers, and a few others that are not
27  /// interesting to schedulers are not allocated SUnits.
28  ///
29  /// SDNodes with MVT::Glue operands are grouped along with the flagged
30  /// nodes into a single SUnit so that they are scheduled together.
31  ///
32  /// SDNode-based scheduling graphs do not use SDep::Anti or SDep::Output
33  /// edges. Physical register dependence information is not carried in
34  /// the DAG and must be handled explicitly by schedulers.
35  ///
37  public:
39  SelectionDAG *DAG; // DAG of the current basic block
41 
42  /// The schedule. Null SUnit*'s represent noop instructions.
43  std::vector<SUnit*> Sequence;
44 
45  explicit ScheduleDAGSDNodes(MachineFunction &mf);
46 
47  ~ScheduleDAGSDNodes() override {}
48 
49  /// Run - perform scheduling.
50  ///
51  void Run(SelectionDAG *dag, MachineBasicBlock *bb);
52 
53  /// isPassiveNode - Return true if the node is a non-scheduled leaf.
54  ///
55  static bool isPassiveNode(SDNode *Node) {
56  if (isa<ConstantSDNode>(Node)) return true;
57  if (isa<ConstantFPSDNode>(Node)) return true;
58  if (isa<RegisterSDNode>(Node)) return true;
59  if (isa<RegisterMaskSDNode>(Node)) return true;
60  if (isa<GlobalAddressSDNode>(Node)) return true;
61  if (isa<BasicBlockSDNode>(Node)) return true;
62  if (isa<FrameIndexSDNode>(Node)) return true;
63  if (isa<ConstantPoolSDNode>(Node)) return true;
64  if (isa<TargetIndexSDNode>(Node)) return true;
65  if (isa<JumpTableSDNode>(Node)) return true;
66  if (isa<ExternalSymbolSDNode>(Node)) return true;
67  if (isa<MCSymbolSDNode>(Node)) return true;
68  if (isa<BlockAddressSDNode>(Node)) return true;
69  if (Node->getOpcode() == ISD::EntryToken ||
70  isa<MDNodeSDNode>(Node)) return true;
71  return false;
72  }
73 
74  /// NewSUnit - Creates a new SUnit and return a ptr to it.
75  ///
77 
78  /// Clone - Creates a clone of the specified SUnit. It does not copy the
79  /// predecessors / successors info nor the temporary scheduling states.
80  ///
81  SUnit *Clone(SUnit *N);
82 
83  /// BuildSchedGraph - Build the SUnit graph from the selection dag that we
84  /// are input. This SUnit graph is similar to the SelectionDAG, but
85  /// excludes nodes that aren't interesting to scheduling, and represents
86  /// flagged together nodes with a single SUnit.
88 
89  /// InitVRegCycleFlag - Set isVRegCycle if this node's single use is
90  /// CopyToReg and its only active data operands are CopyFromReg within a
91  /// single block loop.
92  ///
93  void InitVRegCycleFlag(SUnit *SU);
94 
95  /// InitNumRegDefsLeft - Determine the # of regs defined by this node.
96  ///
97  void InitNumRegDefsLeft(SUnit *SU);
98 
99  /// computeLatency - Compute node latency.
100  ///
101  virtual void computeLatency(SUnit *SU);
102 
103  virtual void computeOperandLatency(SDNode *Def, SDNode *Use,
104  unsigned OpIdx, SDep& dep) const;
105 
106  /// Schedule - Order nodes according to selected style, filling
107  /// in the Sequence member.
108  ///
109  virtual void Schedule() = 0;
110 
111  /// VerifyScheduledSequence - Verify that all SUnits are scheduled and
112  /// consistent with the Sequence of scheduled instructions.
113  void VerifyScheduledSequence(bool isBottomUp);
114 
115  /// EmitSchedule - Insert MachineInstrs into the MachineBasicBlock
116  /// according to the order specified in Sequence.
117  ///
118  virtual MachineBasicBlock*
120 
121  void dumpNode(const SUnit *SU) const override;
122 
123  void dumpSchedule() const;
124 
125  std::string getGraphNodeLabel(const SUnit *SU) const override;
126 
127  std::string getDAGName() const override;
128 
129  virtual void getCustomGraphFeatures(GraphWriter<ScheduleDAG*> &GW) const;
130 
131  /// RegDefIter - In place iteration over the values defined by an
132  /// SUnit. This does not need copies of the iterator or any other STLisms.
133  /// The iterator creates itself, rather than being provided by the SchedDAG.
134  class RegDefIter {
135  const ScheduleDAGSDNodes *SchedDAG;
136  const SDNode *Node;
137  unsigned DefIdx;
138  unsigned NodeNumDefs;
139  MVT ValueType;
140  public:
141  RegDefIter(const SUnit *SU, const ScheduleDAGSDNodes *SD);
142 
143  bool IsValid() const { return Node != nullptr; }
144 
145  MVT GetValue() const {
146  assert(IsValid() && "bad iterator");
147  return ValueType;
148  }
149 
150  const SDNode *GetNode() const {
151  return Node;
152  }
153 
154  unsigned GetIdx() const {
155  return DefIdx-1;
156  }
157 
158  void Advance();
159  private:
160  void InitNodeNumDefs();
161  };
162 
163  protected:
164  /// ForceUnitLatencies - Return true if all scheduling edges should be given
165  /// a latency value of one. The default is to return false; schedulers may
166  /// override this as needed.
167  virtual bool forceUnitLatencies() const { return false; }
168 
169  private:
170  /// ClusterNeighboringLoads - Cluster loads from "near" addresses into
171  /// combined SUnits.
172  void ClusterNeighboringLoads(SDNode *Node);
173  /// ClusterNodes - Cluster certain nodes which should be scheduled together.
174  ///
175  void ClusterNodes();
176 
177  /// BuildSchedUnits, AddSchedEdges - Helper functions for BuildSchedGraph.
178  void BuildSchedUnits();
179  void AddSchedEdges();
180 
181  void EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap,
182  MachineBasicBlock::iterator InsertPos);
183  };
184 }
185 
186 #endif
virtual void computeOperandLatency(SDNode *Def, SDNode *Use, unsigned OpIdx, SDep &dep) const
virtual void getCustomGraphFeatures(GraphWriter< ScheduleDAG * > &GW) const
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
EntryToken - This is the marker used to indicate the start of a region.
Definition: ISDOpcodes.h:45
void InitNumRegDefsLeft(SUnit *SU)
InitNumRegDefsLeft - Determine the # of regs defined by this node.
A Use represents the edge between a Value definition and its users.
Definition: Use.h:69
ScheduleDAGSDNodes(MachineFunction &mf)
void InitVRegCycleFlag(SUnit *SU)
InitVRegCycleFlag - Set isVRegCycle if this node's single use is CopyToReg and its only active data o...
std::string getDAGName() const override
Return the basic block label.
Itinerary data supplied by a subtarget to be used by a target.
SUnit * Clone(SUnit *N)
Clone - Creates a clone of the specified SUnit.
void dumpNode(const SUnit *SU) const override
SDep - Scheduling dependency.
Definition: ScheduleDAG.h:45
ScheduleDAGSDNodes - A ScheduleDAG for scheduling SDNode-based DAGs.
std::vector< SUnit * > Sequence
The schedule. Null SUnit*'s represent noop instructions.
SUnit * newSUnit(SDNode *N)
NewSUnit - Creates a new SUnit and return a ptr to it.
MVT - Machine Value Type.
bundle_iterator - MachineBasicBlock iterator that automatically skips over MIs that are inside bundle...
const InstrItineraryData * InstrItins
virtual void computeLatency(SUnit *SU)
computeLatency - Compute node latency.
RegDefIter - In place iteration over the values defined by an SUnit.
MachineBasicBlock * BB
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:179
Represents one node in the SelectionDAG.
std::string getGraphNodeLabel(const SUnit *SU) const override
getGraphNodeLabel - Return a label for an SUnit node in a visualization of the ScheduleDAG.
static bool isPassiveNode(SDNode *Node)
isPassiveNode - Return true if the node is a non-scheduled leaf.
RegDefIter(const SUnit *SU, const ScheduleDAGSDNodes *SD)
void BuildSchedGraph(AliasAnalysis *AA)
BuildSchedGraph - Build the SUnit graph from the selection dag that we are input. ...
#define N
void Run(SelectionDAG *dag, MachineBasicBlock *bb)
Run - perform scheduling.
virtual MachineBasicBlock * EmitSchedule(MachineBasicBlock::iterator &InsertPos)
EmitSchedule - Insert MachineInstrs into the MachineBasicBlock according to the order specified in Se...
virtual bool forceUnitLatencies() const
ForceUnitLatencies - Return true if all scheduling edges should be given a latency value of one...
virtual void Schedule()=0
Schedule - Order nodes according to selected style, filling in the Sequence member.
SUnit - Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:261
void VerifyScheduledSequence(bool isBottomUp)
VerifyScheduledSequence - Verify that all SUnits are scheduled and consistent with the Sequence of sc...