LLVM  3.7.0
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llvm::ConvergingVLIWScheduler Class Reference

ConvergingVLIWScheduler shrinks the unscheduled zone using heuristics to balance the schedule. More...

#include <HexagonMachineScheduler.h>

Inheritance diagram for llvm::ConvergingVLIWScheduler:
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Collaboration diagram for llvm::ConvergingVLIWScheduler:
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Public Types

enum  { TopQID = 1, BotQID = 2, LogMaxQID = 2 }
 SUnit::NodeQueueId: 0 (none), 1 (top), 2 (bot), 3 (both) More...
 

Public Member Functions

 ConvergingVLIWScheduler ()
 
void initialize (ScheduleDAGMI *dag) override
 Initialize the strategy after building the DAG for a new region. More...
 
SUnitpickNode (bool &IsTopNode) override
 Pick the best node to balance the schedule. Implements MachineSchedStrategy. More...
 
void schedNode (SUnit *SU, bool IsTopNode) override
 Update the scheduler's state after scheduling a node. More...
 
void releaseTopNode (SUnit *SU) override
 When all predecessor dependencies have been resolved, free this node for top-down scheduling. More...
 
void releaseBottomNode (SUnit *SU) override
 When all successor dependencies have been resolved, free this node for bottom-up scheduling. More...
 
unsigned ReportPackets ()
 
- Public Member Functions inherited from llvm::MachineSchedStrategy
virtual ~MachineSchedStrategy ()
 
virtual void initPolicy (MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, unsigned NumRegionInstrs)
 Optionally override the per-region scheduling policy. More...
 
virtual bool shouldTrackPressure () const
 Check if pressure tracking is needed before building the DAG and initializing this strategy. More...
 
virtual void registerRoots ()
 Notify this strategy that all roots have been released (including those that depend on EntrySU or ExitSU). More...
 
virtual void scheduleTree (unsigned SubtreeID)
 Scheduler callback to notify that a new subtree is scheduled. More...
 

Protected Member Functions

SUnitpickNodeBidrectional (bool &IsTopNode)
 Pick the best candidate node from either the top or bottom queue. More...
 
int SchedulingCost (ReadyQueue &Q, SUnit *SU, SchedCandidate &Candidate, RegPressureDelta &Delta, bool verbose)
 Single point to compute overall scheduling cost. More...
 
CandResult pickNodeFromQueue (ReadyQueue &Q, const RegPressureTracker &RPTracker, SchedCandidate &Candidate)
 Pick the best candidate from the top queue. More...
 
void traceCandidate (const char *Label, const ReadyQueue &Q, SUnit *SU, PressureChange P=PressureChange())
 

Detailed Description

ConvergingVLIWScheduler shrinks the unscheduled zone using heuristics to balance the schedule.

Definition at line 109 of file HexagonMachineScheduler.h.

Member Enumeration Documentation

anonymous enum

SUnit::NodeQueueId: 0 (none), 1 (top), 2 (bot), 3 (both)

Enumerator
TopQID 
BotQID 
LogMaxQID 

Definition at line 200 of file HexagonMachineScheduler.h.

Constructor & Destructor Documentation

llvm::ConvergingVLIWScheduler::ConvergingVLIWScheduler ( )
inline

Definition at line 206 of file HexagonMachineScheduler.h.

Member Function Documentation

void ConvergingVLIWScheduler::initialize ( ScheduleDAGMI DAG)
overridevirtual
SUnit * ConvergingVLIWScheduler::pickNode ( bool IsTopNode)
overridevirtual
SUnit * ConvergingVLIWScheduler::pickNodeBidrectional ( bool IsTopNode)
protected

Pick the best candidate node from either the top or bottom queue.

Definition at line 581 of file HexagonMachineScheduler.cpp.

References llvm::ScheduleDAGMILive::getBotRPTracker(), llvm::ScheduleDAGMILive::getTopRPTracker(), and pickNodeFromQueue().

Referenced by pickNode().

ConvergingVLIWScheduler::CandResult ConvergingVLIWScheduler::pickNodeFromQueue ( ReadyQueue Q,
const RegPressureTracker RPTracker,
SchedCandidate &  Candidate 
)
protected

Pick the best candidate from the top queue.

TODO: getMaxPressureDelta results can be mostly cached for each SUnit during DAG building. To adjust for the current scheduling location we need to maintain the number of vreg uses remaining to be top-scheduled.

Definition at line 536 of file HexagonMachineScheduler.cpp.

References llvm::ReadyQueue::begin(), DEBUG, llvm::ReadyQueue::dump(), llvm::ReadyQueue::end(), llvm::ScheduleDAGMILive::getRegionCriticalPSets(), llvm::ScheduleDAGMILive::getRegPressure(), I, llvm::RegisterPressure::MaxSetPressure, SchedulingCost(), and traceCandidate().

Referenced by pickNode(), and pickNodeBidrectional().

void ConvergingVLIWScheduler::releaseBottomNode ( SUnit SU)
overridevirtual

When all successor dependencies have been resolved, free this node for bottom-up scheduling.

Implements llvm::MachineSchedStrategy.

Definition at line 241 of file HexagonMachineScheduler.cpp.

References llvm::SUnit::BotReadyCycle, llvm::SUnit::getInstr(), I, llvm::SUnit::isScheduled, and llvm::SUnit::Succs.

void ConvergingVLIWScheduler::releaseTopNode ( SUnit SU)
overridevirtual

When all predecessor dependencies have been resolved, free this node for top-down scheduling.

Implements llvm::MachineSchedStrategy.

Definition at line 224 of file HexagonMachineScheduler.cpp.

References I, llvm::SUnit::isScheduled, llvm::SUnit::Preds, and llvm::SUnit::TopReadyCycle.

unsigned llvm::ConvergingVLIWScheduler::ReportPackets ( )
inline

Definition at line 220 of file HexagonMachineScheduler.h.

void ConvergingVLIWScheduler::schedNode ( SUnit SU,
bool  IsTopNode 
)
overridevirtual

Update the scheduler's state after scheduling a node.

This is the same node that was just returned by pickNode(). However, VLIWMachineScheduler needs to update it's state based on the current cycle before MachineSchedStrategy does.

Implements llvm::MachineSchedStrategy.

Definition at line 687 of file HexagonMachineScheduler.cpp.

References llvm::SUnit::BotReadyCycle, and llvm::SUnit::TopReadyCycle.

int ConvergingVLIWScheduler::SchedulingCost ( ReadyQueue Q,
SUnit SU,
SchedCandidate &  Candidate,
RegPressureDelta Delta,
bool  verbose 
)
protected
void ConvergingVLIWScheduler::traceCandidate ( const char *  Label,
const ReadyQueue Q,
SUnit SU,
PressureChange  P = PressureChange() 
)
protected

The documentation for this class was generated from the following files: