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LLVM
3.7.0
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#include <SIRegisterInfo.h>
Public Types | |
| enum | PreloadedValue { TGID_X, TGID_Y, TGID_Z, SCRATCH_WAVE_OFFSET, SCRATCH_PTR, INPUT_PTR, TIDIG_X, TIDIG_Y, TIDIG_Z } |
Additional Inherited Members | |
Static Public Attributes inherited from llvm::AMDGPURegisterInfo | |
| static const MCPhysReg | CalleeSavedReg = AMDGPU::NoRegister |
Definition at line 25 of file SIRegisterInfo.h.
| Enumerator | |
|---|---|
| TGID_X | |
| TGID_Y | |
| TGID_Z | |
| SCRATCH_WAVE_OFFSET | |
| SCRATCH_PTR | |
| INPUT_PTR | |
| TIDIG_X | |
| TIDIG_Y | |
| TIDIG_Z | |
Definition at line 94 of file SIRegisterInfo.h.
| SIRegisterInfo::SIRegisterInfo | ( | ) |
Definition at line 27 of file SIRegisterInfo.cpp.
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override |
Definition at line 192 of file SIRegisterInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineOperand::ChangeToImmediate(), llvm::MachineOperand::ChangeToRegister(), llvm::LLVMContext::emitError(), llvm::MachineInstr::eraseFromParent(), llvm::Function::getContext(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getFunction(), llvm::AMDGPUSubtarget::getGeneration(), llvm::MachineOperand::getIndex(), llvm::MachineFunction::getInfo(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::AMDGPUInstrInfo::getMCOpcodeFromPseudo(), llvm::SIInstrInfo::getNamedOperand(), getNumSubRegsForSpillOp(), llvm::MachineBasicBlock::getParent(), getPhysRegSubReg(), llvm::MachineOperand::getReg(), llvm::SIMachineFunctionInfo::getSpilledReg(), llvm::MachineFunction::getSubtarget(), llvm::RegState::ImplicitDefine, llvm::SIInstrInfo::insertNOPs(), llvm::SIInstrInfo::isImmOperandLegal(), llvm::SIMachineFunctionInfo::SpilledReg::Lane, llvm::RegScavenger::scavengeRegister(), llvm::AMDGPUSubtarget::SEA_ISLANDS, llvm::AMDGPUSubtarget::SOUTHERN_ISLANDS, and llvm::SIMachineFunctionInfo::SpilledReg::VGPR.
| unsigned SIRegisterInfo::findUnusedRegister | ( | const MachineRegisterInfo & | MRI, |
| const TargetRegisterClass * | RC | ||
| ) | const |
Returns a register that is not used at any point in the function.
If all registers are used, then this function will return
Definition at line 498 of file SIRegisterInfo.cpp.
References llvm::TargetRegisterClass::begin(), llvm::TargetRegisterClass::end(), I, and llvm::MachineRegisterInfo::isPhysRegUsed().
Referenced by llvm::SIInstrInfo::calculateLDSSpillAddress(), and llvm::SIMachineFunctionInfo::getSpilledReg().
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overridevirtual |
get the register class of the specified type to use in the CFGStructurizer
Reimplemented from llvm::AMDGPURegisterInfo.
Definition at line 326 of file SIRegisterInfo.cpp.
References llvm::MVT::i32, and llvm::MVT::SimpleTy.
| const TargetRegisterClass * SIRegisterInfo::getEquivalentVGPRClass | ( | const TargetRegisterClass * | SRC | ) | const |
SRC Definition at line 372 of file SIRegisterInfo.cpp.
References hasVGPRs().
Referenced by llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::legalizeOpWithMove(), and llvm::SIInstrInfo::moveToVALU().
Reimplemented from llvm::AMDGPURegisterInfo.
Definition at line 334 of file SIRegisterInfo.cpp.
Referenced by getPhysRegSubReg().
| unsigned SIRegisterInfo::getNumSGPRsAllowed | ( | AMDGPUSubtarget::Generation | gen, |
| unsigned | WaveCount | ||
| ) | const |
Give the maximum number of SGPRs that can be used by WaveCount concurrent waves.
Definition at line 524 of file SIRegisterInfo.cpp.
References llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS.
Referenced by getRegPressureSetLimit().
Give the maximum number of VGPRs that can be used by WaveCount concurrent waves.
Definition at line 509 of file SIRegisterInfo.cpp.
Referenced by getRegPressureSetLimit().
| const TargetRegisterClass * SIRegisterInfo::getPhysRegClass | ( | unsigned | Reg | ) | const |
Return the 'base' register class for this register.
e.g. SGPR0 => SReg_32, VGPR => VGPR_32 SGPR0_SGPR1 -> SReg_32, etc.
Definition at line 338 of file SIRegisterInfo.cpp.
References llvm::BaseClass, and llvm::TargetRegisterInfo::isVirtualRegister().
Referenced by llvm::SIInstrInfo::getOpRegClass(), getPhysRegSubReg(), llvm::SIInstrInfo::isOperandLegal(), and isVGPR().
| unsigned SIRegisterInfo::getPhysRegSubReg | ( | unsigned | Reg, |
| const TargetRegisterClass * | SubRC, | ||
| unsigned | Channel | ||
| ) | const |
Channel This is the register channel (e.g.
a value from 0-16), not the SubReg index.
Definition at line 406 of file SIRegisterInfo.cpp.
References getHWRegIndex(), getPhysRegClass(), llvm::TargetRegisterClass::getRegister(), llvm::TargetRegisterClass::getSize(), and llvm_unreachable.
Referenced by eliminateFrameIndex(), and llvm::SITargetLowering::LowerFormalArguments().
| unsigned SIRegisterInfo::getPreloadedValue | ( | const MachineFunction & | MF, |
| enum PreloadedValue | Value | ||
| ) | const |
Returns the physical register that Value is stored in.
Definition at line 466 of file SIRegisterInfo.cpp.
References ShaderType::COMPUTE, llvm::MachineFunction::getInfo(), llvm::AMDGPUMachineFunction::getShaderType(), INPUT_PTR, llvm_unreachable, llvm::SIMachineFunctionInfo::NumUserSGPRs, SCRATCH_PTR, SCRATCH_WAVE_OFFSET, llvm::SIMachineFunctionInfo::ScratchOffsetReg, TGID_X, TGID_Y, TGID_Z, TIDIG_X, TIDIG_Y, and TIDIG_Z.
Referenced by llvm::SITargetLowering::LowerFormalArguments().
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override |
Definition at line 67 of file SIRegisterInfo.cpp.
References llvm::AMDGPUSubtarget::getGeneration(), llvm::AMDGPUSubtarget::getMaxWavesPerCU(), getNumSGPRsAllowed(), getNumVGPRsAllowed(), llvm::MachineFunction::getSubtarget(), I, and isSGPRClass().
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override |
Definition at line 29 of file SIRegisterInfo.cpp.
References llvm::AMDGPUSubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG, llvm::MachineFunction::getSubtarget(), llvm::AMDGPUSubtarget::hasSGPRInitBug(), llvm::MCRegAliasIterator::isValid(), llvm::Reserved, and llvm::BitVector::set().
| const TargetRegisterClass * SIRegisterInfo::getSubRegClass | ( | const TargetRegisterClass * | RC, |
| unsigned | SubIdx | ||
| ) | const |
RC for the given SubIdx. If SubIdx equals NoSubRegister, RC will be returned. Definition at line 392 of file SIRegisterInfo.cpp.
References isSGPRClass().
| bool SIRegisterInfo::hasVGPRs | ( | const TargetRegisterClass * | RC | ) | const |
Definition at line 363 of file SIRegisterInfo.cpp.
Referenced by llvm::SIInstrInfo::canReadVGPR(), getEquivalentVGPRClass(), hasVGPROperands(), isSGPRClass(), isVGPR(), llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::loadRegFromStackSlot(), llvm::SIInstrInfo::moveToVALU(), and llvm::SIInstrInfo::storeRegToStackSlot().
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inline |
Definition at line 51 of file SIRegisterInfo.h.
References hasVGPRs().
Referenced by llvm::SIInstrInfo::FoldImmediate(), llvm::SIInstrInfo::getMovOpcode(), getRegPressureSetLimit(), getSubRegClass(), isSGPRClassID(), llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::legalizeOpWithMove(), llvm::SIInstrInfo::loadRegFromStackSlot(), llvm::SIInstrInfo::storeRegToStackSlot(), and llvm::SIInstrInfo::usesConstantBus().
Definition at line 59 of file SIRegisterInfo.h.
References getRegClass(), and isSGPRClass().
Definition at line 459 of file SIRegisterInfo.cpp.
References opCanUseLiteralConstant(), and llvm::AMDGPU::OPERAND_REG_INLINE_C.
Referenced by llvm::SIInstrInfo::isImmOperandLegal().
Definition at line 455 of file SIRegisterInfo.cpp.
References llvm::AMDGPU::OPERAND_REG_IMM32.
Referenced by llvm::SIInstrInfo::isImmOperandLegal(), and opCanUseInlineConstant().
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override |
Definition at line 98 of file SIRegisterInfo.cpp.
References llvm::MachineFunction::getFrameInfo(), and llvm::MachineFrameInfo::hasStackObjects().
1.8.6