80 #define DEBUG_TYPE "sgpr-copies"
91 unsigned SubReg)
const;
95 unsigned SubReg)
const;
104 const char *getPassName()
const override {
105 return "SI Fix SGPR copies";
115 return new SIFixSGPRCopies(tm);
138 unsigned SubReg)
const {
148 switch (
I->getOpcode()) {
150 RC = TRI->getCommonSubClass(RC, inferRegClassFromUses(TRI, MRI,
151 I->getOperand(0).getReg(),
152 I->getOperand(0).getSubReg()));
164 unsigned SubReg)
const {
178 bool SIFixSGPRCopies::isVGPRToSGPRCopy(
const MachineInstr &Copy,
197 MRI.
getRegClass(SrcReg) == &AMDGPU::VReg_1RegClass)
218 DEBUG(
dbgs() <<
"Fixing VGPR -> SGPR copy:\n");
231 unsigned Reg = Op.
getReg();
233 = inferRegClassFromDef(TRI, MRI, Reg, Op.
getSubReg());
240 if (TRI->getCommonSubClass(RC, &AMDGPU::VGPR_32RegClass)) {
275 bool SGPRBranch =
false;
284 bool HasBreakDef =
false;
295 case AMDGPU::SI_BREAK:
296 case AMDGPU::SI_IF_BREAK:
297 case AMDGPU::SI_ELSE_BREAK:
307 if (!SGPRBranch && !HasBreakDef)
316 DEBUG(
dbgs() <<
"Fixing REG_SEQUENCE: " << MI);
328 DEBUG(
dbgs() <<
" Fixing INSERT_SUBREG: " << MI);
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
AMDGPU specific subclass of TargetSubtarget.
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
void moveToVALU(MachineInstr &MI) const
Replace this instruction's opcode with the equivalent VALU opcode.
bool hasVGPRs(const TargetRegisterClass *RC) const
static bool hasVGPROperands(const MachineInstr &MI, const SIRegisterInfo *TRI)
COPY - Target-independent register copy.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
use_instr_iterator use_instr_begin(unsigned RegNo) const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
const TargetRegisterClass * getRegClass(unsigned Reg) const
getRegClass - Return the register class of the specified virtual register.
bool isSGPRClass(const TargetRegisterClass *RC) const
Reg
All possible values of the reg field in the ModR/M byte.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
defusechain_iterator - This class provides iterator support for machine operands in the function that...
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
FunctionPass * createSIFixSGPRCopiesPass(TargetMachine &tm)
const MachineBasicBlock * getParent() const
bundle_iterator< MachineInstr, instr_iterator > iterator
void print(raw_ostream &OS, bool SkipOpers=false) const
const MachineOperand & getOperand(unsigned i) const
INSERT_SUBREG - This instruction takes three operands: a register that has subregisters, a register providing an insert value, and a subregister index.
FunctionPass class - This class is used to implement most global optimizations.
unsigned getSubReg() const
REG_SEQUENCE - This variadic instruction is used to form a register that represents a consecutive seq...
MachineOperand class - Representation of each machine instruction operand.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
const TargetRegisterClass * getSubRegClass(const TargetRegisterClass *RC, unsigned SubIdx) const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
const TargetRegisterClass * getPhysRegClass(unsigned Reg) const
Return the 'base' register class for this register.
Representation of each machine instruction.
Interface definition for SIInstrInfo.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
unsigned getReg() const
getReg - Returns the register number.
virtual const TargetInstrInfo * getInstrInfo() const
static use_instr_iterator use_instr_end()
BasicBlockListType::iterator iterator
Primary interface to the complete machine description for the target machine.
const TargetRegisterClass * getOpRegClass(const MachineInstr &MI, unsigned OpNo) const
Return the correct register class for OpNo.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.