LLVM  3.7.0
Public Member Functions | Protected Member Functions | Protected Attributes | List of all members
llvm::ScheduleDAGMI Class Reference

ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions according to the given MachineSchedStrategy without much extra book-keeping. More...

#include <MachineScheduler.h>

Inheritance diagram for llvm::ScheduleDAGMI:
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Collaboration diagram for llvm::ScheduleDAGMI:
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Public Member Functions

 ScheduleDAGMI (MachineSchedContext *C, std::unique_ptr< MachineSchedStrategy > S, bool IsPostRA)
 
 ~ScheduleDAGMI () override
 
virtual bool hasVRegLiveness () const
 Return true if this DAG supports VReg liveness and RegPressure. More...
 
void addMutation (std::unique_ptr< ScheduleDAGMutation > Mutation)
 Add a postprocessing step to the DAG builder. More...
 
bool canAddEdge (SUnit *SuccSU, SUnit *PredSU)
 True if an edge can be added from PredSU to SuccSU without creating a cycle. More...
 
bool addEdge (SUnit *SuccSU, const SDep &PredDep)
 Add a DAG edge to the given SU with the given predecessor dependence data. More...
 
MachineBasicBlock::iterator top () const
 
MachineBasicBlock::iterator bottom () const
 
void enterRegion (MachineBasicBlock *bb, MachineBasicBlock::iterator begin, MachineBasicBlock::iterator end, unsigned regioninstrs) override
 Implement the ScheduleDAGInstrs interface for handling the next scheduling region. More...
 
void schedule () override
 Implement ScheduleDAGInstrs interface for scheduling a sequence of reorderable instructions. More...
 
void moveInstruction (MachineInstr *MI, MachineBasicBlock::iterator InsertPos)
 Change the position of an instruction within the basic block and update live ranges and region boundary iterators. More...
 
const SUnitgetNextClusterPred () const
 
const SUnitgetNextClusterSucc () const
 
void viewGraph (const Twine &Name, const Twine &Title) override
 viewGraph - Pop up a ghostview window with the reachable parts of the DAG rendered using 'dot'. More...
 
void viewGraph () override
 Out-of-line implementation with no arguments is handy for gdb. More...
 
- Public Member Functions inherited from llvm::ScheduleDAGInstrs
 ScheduleDAGInstrs (MachineFunction &mf, const MachineLoopInfo *mli, bool IsPostRAFlag, bool RemoveKillFlags=false, LiveIntervals *LIS=nullptr)
 
 ~ScheduleDAGInstrs () override
 
bool isPostRA () const
 
LiveIntervalsgetLIS () const
 Expose LiveIntervals for use in DAG mutators and such. More...
 
const TargetSchedModelgetSchedModel () const
 Get the machine model for instruction scheduling. More...
 
const MCSchedClassDescgetSchedClass (SUnit *SU) const
 Resolve and cache a resolved scheduling class for an SUnit. More...
 
MachineBasicBlock::iterator begin () const
 begin - Return an iterator to the top of the current scheduling region. More...
 
MachineBasicBlock::iterator end () const
 end - Return an iterator to the bottom of the current scheduling region. More...
 
SUnitnewSUnit (MachineInstr *MI)
 newSUnit - Creates a new SUnit and return a ptr to it. More...
 
SUnitgetSUnit (MachineInstr *MI) const
 getSUnit - Return an existing SUnit for this MI, or NULL. More...
 
virtual void startBlock (MachineBasicBlock *BB)
 startBlock - Prepare to perform scheduling in the given block. More...
 
virtual void finishBlock ()
 finishBlock - Clean up after scheduling in the given block. More...
 
virtual void exitRegion ()
 Notify that the scheduler has finished scheduling the current region. More...
 
void buildSchedGraph (AliasAnalysis *AA, RegPressureTracker *RPTracker=nullptr, PressureDiffs *PDiffs=nullptr)
 buildSchedGraph - Build SUnits from the MachineBasicBlock that we are input. More...
 
void addSchedBarrierDeps ()
 addSchedBarrierDeps - Add dependencies from instructions in the current list of instructions being scheduled to scheduling barrier. More...
 
virtual void finalizeSchedule ()
 finalizeSchedule - Allow targets to perform final scheduling actions at the level of the whole MachineFunction. More...
 
void dumpNode (const SUnit *SU) const override
 
std::string getGraphNodeLabel (const SUnit *SU) const override
 Return a label for a DAG node that points to an instruction. More...
 
std::string getDAGName () const override
 Return a label for the region of code covered by the DAG. More...
 
void fixupKills (MachineBasicBlock *MBB)
 Fix register kill flags that scheduling has made invalid. More...
 
- Public Member Functions inherited from llvm::ScheduleDAG
 ScheduleDAG (MachineFunction &mf)
 
virtual ~ScheduleDAG ()
 
void clearDAG ()
 clearDAG - clear the DAG state (between regions). More...
 
const MCInstrDescgetInstrDesc (const SUnit *SU) const
 getInstrDesc - Return the MCInstrDesc of this SUnit. More...
 
virtual void addCustomGraphFeatures (GraphWriter< ScheduleDAG * > &) const
 addCustomGraphFeatures - Add custom features for a visualization of the ScheduleDAG. More...
 
unsigned VerifyScheduledDAG (bool isBottomUp)
 VerifyScheduledDAG - Verify that all SUnits were scheduled and that their state is consistent. More...
 

Protected Member Functions

void postprocessDAG ()
 Apply each ScheduleDAGMutation step in order. More...
 
void initQueues (ArrayRef< SUnit * > TopRoots, ArrayRef< SUnit * > BotRoots)
 Release ExitSU predecessors and setup scheduler queues. More...
 
void updateQueues (SUnit *SU, bool IsTopNode)
 Update scheduler DAG and queues after scheduling an instruction. More...
 
void placeDebugValues ()
 Reinsert debug_values recorded in ScheduleDAGInstrs::DbgValues. More...
 
void dumpSchedule () const
 dump the scheduled Sequence. More...
 
bool checkSchedLimit ()
 
void findRootsAndBiasEdges (SmallVectorImpl< SUnit * > &TopRoots, SmallVectorImpl< SUnit * > &BotRoots)
 
void releaseSucc (SUnit *SU, SDep *SuccEdge)
 ReleaseSucc - Decrement the NumPredsLeft count of a successor. More...
 
void releaseSuccessors (SUnit *SU)
 releaseSuccessors - Call releaseSucc on each of SU's successors. More...
 
void releasePred (SUnit *SU, SDep *PredEdge)
 ReleasePred - Decrement the NumSuccsLeft count of a predecessor. More...
 
void releasePredecessors (SUnit *SU)
 releasePredecessors - Call releasePred on each of SU's predecessors. More...
 
- Protected Member Functions inherited from llvm::ScheduleDAGInstrs
void initSUnits ()
 Create an SUnit for each real instruction, numbered in top-down toplological order. More...
 
void addPhysRegDataDeps (SUnit *SU, unsigned OperIdx)
 MO is an operand of SU's instruction that defines a physical register. More...
 
void addPhysRegDeps (SUnit *SU, unsigned OperIdx)
 addPhysRegDeps - Add register dependencies (data, anti, and output) from this SUnit to following instructions in the same scheduling region that depend the physical register referenced at OperIdx. More...
 
void addVRegDefDeps (SUnit *SU, unsigned OperIdx)
 addVRegDefDeps - Add register output and data dependencies from this SUnit to instructions that occur later in the same scheduling region if they read from or write to the virtual register defined at OperIdx. More...
 
void addVRegUseDeps (SUnit *SU, unsigned OperIdx)
 addVRegUseDeps - Add a register data dependency if the instruction that defines the virtual register used at OperIdx is mapped to an SUnit. More...
 
void startBlockForKills (MachineBasicBlock *BB)
 PostRA helper for rewriting kill flags. More...
 
bool toggleKillFlag (MachineInstr *MI, MachineOperand &MO)
 Toggle a register operand kill flag. More...
 

Protected Attributes

AliasAnalysisAA
 
std::unique_ptr
< MachineSchedStrategy
SchedImpl
 
ScheduleDAGTopologicalSort Topo
 Topo - A topological ordering for SUnits which permits fast IsReachable and similar queries. More...
 
std::vector< std::unique_ptr
< ScheduleDAGMutation > > 
Mutations
 Ordered list of DAG postprocessing steps. More...
 
MachineBasicBlock::iterator CurrentTop
 The top of the unscheduled zone. More...
 
MachineBasicBlock::iterator CurrentBottom
 The bottom of the unscheduled zone. More...
 
const SUnitNextClusterPred
 Record the next node in a scheduled cluster. More...
 
const SUnitNextClusterSucc
 
unsigned NumInstrsScheduled
 The number of instructions scheduled so far. More...
 
- Protected Attributes inherited from llvm::ScheduleDAGInstrs
const MachineLoopInfoMLI
 
const MachineFrameInfoMFI
 
LiveIntervalsLIS
 Live Intervals provides reaching defs in preRA scheduling. More...
 
TargetSchedModel SchedModel
 TargetSchedModel provides an interface to the machine model. More...
 
bool IsPostRA
 isPostRA flag indicates vregs cannot be present. More...
 
bool RemoveKillFlags
 True if the DAG builder should remove kill flags (in preparation for rescheduling). More...
 
bool CanHandleTerminators
 The standard DAG builder does not normally include terminators as DAG nodes because it does not create the necessary dependencies to prevent reordering. More...
 
MachineBasicBlockBB
 State specific to the current scheduling region. More...
 
MachineBasicBlock::iterator RegionBegin
 The beginning of the range to be scheduled. More...
 
MachineBasicBlock::iterator RegionEnd
 The end of the range to be scheduled. More...
 
unsigned NumRegionInstrs
 Instructions in this region (distance(RegionBegin, RegionEnd)). More...
 
DenseMap< MachineInstr *, SUnit * > MISUnitMap
 After calling BuildSchedGraph, each machine instruction in the current scheduling region is mapped to an SUnit. More...
 
VReg2UseMap VRegUses
 After calling BuildSchedGraph, each vreg used in the scheduling region is mapped to a set of SUnits. More...
 
Reg2SUnitsMap Defs
 State internal to DAG building. More...
 
Reg2SUnitsMap Uses
 
VReg2SUnitMap VRegDefs
 Track the last instruction in this region defining each virtual register. More...
 
std::vector< SUnit * > PendingLoads
 PendingLoads - Remember where unknown loads are after the most recent unknown store, as we iterate. More...
 
DbgValueVector DbgValues
 
MachineInstrFirstDbgValue
 
BitVector LiveRegs
 Set of live physical registers for updating kill flags. More...
 

Additional Inherited Members

- Public Attributes inherited from llvm::ScheduleDAG
const TargetMachineTM
 
const TargetInstrInfoTII
 
const TargetRegisterInfoTRI
 
MachineFunctionMF
 
MachineRegisterInfoMRI
 
std::vector< SUnitSUnits
 
SUnit EntrySU
 
SUnit ExitSU
 
bool StressSched
 
- Protected Types inherited from llvm::ScheduleDAGInstrs
typedef std::vector< std::pair
< MachineInstr *, MachineInstr * > > 
DbgValueVector
 DbgValues - Remember instruction that precedes DBG_VALUE. More...
 

Detailed Description

ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions according to the given MachineSchedStrategy without much extra book-keeping.

This is the common functionality between PreRA and PostRA MachineScheduler.

Definition at line 222 of file MachineScheduler.h.

Constructor & Destructor Documentation

llvm::ScheduleDAGMI::ScheduleDAGMI ( MachineSchedContext C,
std::unique_ptr< MachineSchedStrategy S,
bool  IsPostRA 
)
inline

Definition at line 250 of file MachineScheduler.h.

References NumInstrsScheduled.

ScheduleDAGMI::~ScheduleDAGMI ( )
override

Definition at line 515 of file MachineScheduler.cpp.

Member Function Documentation

bool ScheduleDAGMI::addEdge ( SUnit SuccSU,
const SDep PredDep 
)

Add a DAG edge to the given SU with the given predecessor dependence data.

Returns
true if the edge may be added without creating a cycle OR if an equivalent edge already existed (false indicates failure).

Definition at line 522 of file MachineScheduler.cpp.

References llvm::SUnit::addPred(), llvm::ScheduleDAGTopologicalSort::AddPred(), llvm::ScheduleDAG::ExitSU, llvm::SDep::getSUnit(), llvm::SDep::isArtificial(), llvm::ScheduleDAGTopologicalSort::IsReachable(), and Topo.

void llvm::ScheduleDAGMI::addMutation ( std::unique_ptr< ScheduleDAGMutation Mutation)
inline

Add a postprocessing step to the DAG builder.

Mutations are applied in the order that they are added after normal DAG building and before MachineSchedStrategy initialization.

ScheduleDAGMI takes ownership of the Mutation object.

Definition at line 272 of file MachineScheduler.h.

References Mutations.

Referenced by createGenericSchedLive().

MachineBasicBlock::iterator llvm::ScheduleDAGMI::bottom ( ) const
inline
bool ScheduleDAGMI::canAddEdge ( SUnit SuccSU,
SUnit PredSU 
)

True if an edge can be added from PredSU to SuccSU without creating a cycle.

Definition at line 518 of file MachineScheduler.cpp.

References llvm::ScheduleDAG::ExitSU, llvm::ScheduleDAGTopologicalSort::IsReachable(), and Topo.

bool ScheduleDAGMI::checkSchedLimit ( )
protected
void ScheduleDAGMI::dumpSchedule ( ) const
protected
void ScheduleDAGMI::enterRegion ( MachineBasicBlock bb,
MachineBasicBlock::iterator  begin,
MachineBasicBlock::iterator  end,
unsigned  regioninstrs 
)
overridevirtual

Implement the ScheduleDAGInstrs interface for handling the next scheduling region.

enterRegion - Called back from MachineScheduler::runOnMachineFunction after crossing a scheduling boundary.

This covers all instructions in a block, while schedule() may only cover a subset.

[begin, end) includes all instructions in the region, including the boundary itself and single-instruction regions that don't get scheduled.

Reimplemented from llvm::ScheduleDAGInstrs.

Reimplemented in llvm::ScheduleDAGMILive.

Definition at line 617 of file MachineScheduler.cpp.

References llvm::ScheduleDAGInstrs::enterRegion(), and SchedImpl.

Referenced by llvm::ScheduleDAGMILive::enterRegion().

void ScheduleDAGMI::findRootsAndBiasEdges ( SmallVectorImpl< SUnit * > &  TopRoots,
SmallVectorImpl< SUnit * > &  BotRoots 
)
protected
const SUnit* llvm::ScheduleDAGMI::getNextClusterPred ( ) const
inline

Definition at line 306 of file MachineScheduler.h.

References NextClusterPred.

Referenced by llvm::GenericScheduler::tryCandidate().

const SUnit* llvm::ScheduleDAGMI::getNextClusterSucc ( ) const
inline

Definition at line 308 of file MachineScheduler.h.

References NextClusterSucc.

Referenced by llvm::GenericScheduler::tryCandidate().

virtual bool llvm::ScheduleDAGMI::hasVRegLiveness ( ) const
inlinevirtual
void ScheduleDAGMI::initQueues ( ArrayRef< SUnit * >  TopRoots,
ArrayRef< SUnit * >  BotRoots 
)
protected
void ScheduleDAGMI::moveInstruction ( MachineInstr MI,
MachineBasicBlock::iterator  InsertPos 
)

Change the position of an instruction within the basic block and update live ranges and region boundary iterators.

This is normally called from the main scheduler loop but may also be invoked by the scheduling strategy to perform additional code motion.

Definition at line 629 of file MachineScheduler.cpp.

References llvm::ScheduleDAGInstrs::BB, llvm::AArch64CC::MI, llvm::ScheduleDAGInstrs::RegionBegin, and llvm::MachineBasicBlock::splice().

Referenced by llvm::GenericScheduler::reschedulePhysRegCopies(), schedule(), and llvm::ScheduleDAGMILive::scheduleMI().

void ScheduleDAGMI::placeDebugValues ( )
protected
void ScheduleDAGMI::postprocessDAG ( )
protected

Apply each ScheduleDAGMutation step in order.

This allows different instances of ScheduleDAGMI to perform custom DAG postprocessing.

Definition at line 732 of file MachineScheduler.cpp.

References Mutations.

Referenced by schedule(), and llvm::ScheduleDAGMILive::schedule().

void ScheduleDAGMI::releasePred ( SUnit SU,
SDep PredEdge 
)
protected

ReleasePred - Decrement the NumSuccsLeft count of a predecessor.

When NumSuccsLeft reaches zero, release the predecessor node.

FIXME: Adjust PredSU height based on MinLatency.

Definition at line 578 of file MachineScheduler.cpp.

References llvm::SUnit::BotReadyCycle, llvm::dbgs(), llvm::SUnit::dump(), llvm::ScheduleDAG::EntrySU, llvm::SDep::getLatency(), llvm::SDep::getSUnit(), llvm::SDep::isCluster(), llvm::SDep::isWeak(), llvm_unreachable, NextClusterPred, llvm::SUnit::NumSuccsLeft, SchedImpl, and llvm::SUnit::WeakSuccsLeft.

Referenced by releasePredecessors().

void ScheduleDAGMI::releasePredecessors ( SUnit SU)
protected

releasePredecessors - Call releasePred on each of SU's predecessors.

Definition at line 606 of file MachineScheduler.cpp.

References I, llvm::SUnit::Preds, and releasePred().

Referenced by initQueues(), and updateQueues().

void ScheduleDAGMI::releaseSucc ( SUnit SU,
SDep SuccEdge 
)
protected

ReleaseSucc - Decrement the NumPredsLeft count of a successor.

When NumPredsLeft reaches zero, release the successor node.

FIXME: Adjust SuccSU height based on MinLatency.

Definition at line 539 of file MachineScheduler.cpp.

References llvm::dbgs(), llvm::SUnit::dump(), llvm::ScheduleDAG::ExitSU, llvm::SDep::getLatency(), llvm::SDep::getSUnit(), llvm::SDep::isCluster(), llvm::SDep::isWeak(), llvm_unreachable, NextClusterSucc, llvm::SUnit::NumPredsLeft, SchedImpl, llvm::SUnit::TopReadyCycle, and llvm::SUnit::WeakPredsLeft.

Referenced by releaseSuccessors().

void ScheduleDAGMI::releaseSuccessors ( SUnit SU)
protected

releaseSuccessors - Call releaseSucc on each of SU's successors.

Definition at line 567 of file MachineScheduler.cpp.

References I, releaseSucc(), and llvm::SUnit::Succs.

Referenced by initQueues(), and updateQueues().

void ScheduleDAGMI::schedule ( )
overridevirtual

Implement ScheduleDAGInstrs interface for scheduling a sequence of reorderable instructions.

Per-region scheduling driver, called back from MachineScheduler::runOnMachineFunction.

This is a simplified driver that does not consider liveness or register pressure. It is useful for PostRA scheduling and potentially other custom schedulers.

Implements llvm::ScheduleDAGInstrs.

Reimplemented in llvm::ScheduleDAGMILive, and llvm::VLIWMachineScheduler.

Definition at line 662 of file MachineScheduler.cpp.

References llvm::ScheduleDAGInstrs::begin(), llvm::ScheduleDAGInstrs::buildSchedGraph(), checkSchedLimit(), CurrentBottom, CurrentTop, llvm::dbgs(), DEBUG, dumpSchedule(), findRootsAndBiasEdges(), llvm::ScheduleDAGTopologicalSort::InitDAGTopologicalSorting(), initQueues(), llvm::AArch64CC::MI, moveInstruction(), nextIfDebug(), placeDebugValues(), postprocessDAG(), priorNonDebug(), SchedImpl, llvm::ScheduleDAG::SUnits, Topo, updateQueues(), viewGraph(), and ViewMISchedDAGs.

MachineBasicBlock::iterator llvm::ScheduleDAGMI::top ( ) const
inline
void ScheduleDAGMI::updateQueues ( SUnit SU,
bool  IsTopNode 
)
protected

Update scheduler DAG and queues after scheduling an instruction.

Update scheduler queues after scheduling an instruction.

Definition at line 791 of file MachineScheduler.cpp.

References llvm::SUnit::isScheduled, releasePredecessors(), and releaseSuccessors().

Referenced by llvm::VLIWMachineScheduler::schedule(), schedule(), and llvm::ScheduleDAGMILive::schedule().

void ScheduleDAGMI::viewGraph ( const Twine Name,
const Twine Title 
)
overridevirtual

viewGraph - Pop up a ghostview window with the reachable parts of the DAG rendered using 'dot'.

Reimplemented from llvm::ScheduleDAG.

Definition at line 3311 of file MachineScheduler.cpp.

References llvm::errs(), and llvm::ViewGraph().

void ScheduleDAGMI::viewGraph ( )
overridevirtual

Out-of-line implementation with no arguments is handy for gdb.

Reimplemented from llvm::ScheduleDAG.

Definition at line 3321 of file MachineScheduler.cpp.

Referenced by schedule(), and llvm::ScheduleDAGMILive::schedule().

Member Data Documentation

AliasAnalysis* llvm::ScheduleDAGMI::AA
protected

Definition at line 224 of file MachineScheduler.h.

MachineBasicBlock::iterator llvm::ScheduleDAGMI::CurrentBottom
protected
MachineBasicBlock::iterator llvm::ScheduleDAGMI::CurrentTop
protected
std::vector<std::unique_ptr<ScheduleDAGMutation> > llvm::ScheduleDAGMI::Mutations
protected

Ordered list of DAG postprocessing steps.

Definition at line 232 of file MachineScheduler.h.

Referenced by addMutation(), and postprocessDAG().

const SUnit* llvm::ScheduleDAGMI::NextClusterPred
protected

Record the next node in a scheduled cluster.

Definition at line 241 of file MachineScheduler.h.

Referenced by getNextClusterPred(), initQueues(), and releasePred().

const SUnit* llvm::ScheduleDAGMI::NextClusterSucc
protected

Definition at line 242 of file MachineScheduler.h.

Referenced by getNextClusterSucc(), initQueues(), and releaseSucc().

unsigned llvm::ScheduleDAGMI::NumInstrsScheduled
protected

The number of instructions scheduled so far.

Used to cut off the scheduler at the point determined by misched-cutoff.

Definition at line 247 of file MachineScheduler.h.

Referenced by checkSchedLimit(), and ScheduleDAGMI().

std::unique_ptr<MachineSchedStrategy> llvm::ScheduleDAGMI::SchedImpl
protected
ScheduleDAGTopologicalSort llvm::ScheduleDAGMI::Topo
protected

Topo - A topological ordering for SUnits which permits fast IsReachable and similar queries.

Definition at line 229 of file MachineScheduler.h.

Referenced by addEdge(), canAddEdge(), schedule(), and llvm::ScheduleDAGMILive::schedule().


The documentation for this class was generated from the following files: