43 #define DEBUG_TYPE "x86-instr-info"
45 #define GET_INSTRINFO_CTOR_DTOR
46 #include "X86GenInstrInfo.inc"
50 cl::desc(
"Disable fusing of spill code into instructions"));
53 cl::desc(
"Print instructions that the allocator wants to"
54 " fuse, but the X86 backend currently can't"),
58 cl::desc(
"Re-materialize load from stub in PIC mode"),
101 void X86InstrInfo::anchor() {}
105 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64 : X86::ADJCALLSTACKDOWN32),
106 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64 : X86::ADJCALLSTACKUP32)),
107 Subtarget(STI), RI(STI.getTargetTriple()) {
110 { X86::ADC32ri, X86::ADC32mi, 0 },
111 { X86::ADC32ri8, X86::ADC32mi8, 0 },
112 { X86::ADC32rr, X86::ADC32mr, 0 },
113 { X86::ADC64ri32, X86::ADC64mi32, 0 },
114 { X86::ADC64ri8, X86::ADC64mi8, 0 },
115 { X86::ADC64rr, X86::ADC64mr, 0 },
116 { X86::ADD16ri, X86::ADD16mi, 0 },
117 { X86::ADD16ri8, X86::ADD16mi8, 0 },
120 { X86::ADD16rr, X86::ADD16mr, 0 },
122 { X86::ADD32ri, X86::ADD32mi, 0 },
123 { X86::ADD32ri8, X86::ADD32mi8, 0 },
126 { X86::ADD32rr, X86::ADD32mr, 0 },
128 { X86::ADD64ri32, X86::ADD64mi32, 0 },
129 { X86::ADD64ri8, X86::ADD64mi8, 0 },
132 { X86::ADD64rr, X86::ADD64mr, 0 },
134 { X86::ADD8ri, X86::ADD8mi, 0 },
135 { X86::ADD8rr, X86::ADD8mr, 0 },
136 { X86::AND16ri, X86::AND16mi, 0 },
137 { X86::AND16ri8, X86::AND16mi8, 0 },
138 { X86::AND16rr, X86::AND16mr, 0 },
139 { X86::AND32ri, X86::AND32mi, 0 },
140 { X86::AND32ri8, X86::AND32mi8, 0 },
141 { X86::AND32rr, X86::AND32mr, 0 },
142 { X86::AND64ri32, X86::AND64mi32, 0 },
143 { X86::AND64ri8, X86::AND64mi8, 0 },
144 { X86::AND64rr, X86::AND64mr, 0 },
145 { X86::AND8ri, X86::AND8mi, 0 },
146 { X86::AND8rr, X86::AND8mr, 0 },
147 { X86::DEC16r, X86::DEC16m, 0 },
148 { X86::DEC32r, X86::DEC32m, 0 },
149 { X86::DEC64r, X86::DEC64m, 0 },
150 { X86::DEC8r, X86::DEC8m, 0 },
151 { X86::INC16r, X86::INC16m, 0 },
152 { X86::INC32r, X86::INC32m, 0 },
153 { X86::INC64r, X86::INC64m, 0 },
154 { X86::INC8r, X86::INC8m, 0 },
155 { X86::NEG16r, X86::NEG16m, 0 },
156 { X86::NEG32r, X86::NEG32m, 0 },
157 { X86::NEG64r, X86::NEG64m, 0 },
158 { X86::NEG8r, X86::NEG8m, 0 },
159 { X86::NOT16r, X86::NOT16m, 0 },
160 { X86::NOT32r, X86::NOT32m, 0 },
161 { X86::NOT64r, X86::NOT64m, 0 },
162 { X86::NOT8r, X86::NOT8m, 0 },
163 { X86::OR16ri, X86::OR16mi, 0 },
164 { X86::OR16ri8, X86::OR16mi8, 0 },
165 { X86::OR16rr, X86::OR16mr, 0 },
166 { X86::OR32ri, X86::OR32mi, 0 },
167 { X86::OR32ri8, X86::OR32mi8, 0 },
168 { X86::OR32rr, X86::OR32mr, 0 },
169 { X86::OR64ri32, X86::OR64mi32, 0 },
170 { X86::OR64ri8, X86::OR64mi8, 0 },
171 { X86::OR64rr, X86::OR64mr, 0 },
172 { X86::OR8ri, X86::OR8mi, 0 },
173 { X86::OR8rr, X86::OR8mr, 0 },
174 { X86::ROL16r1, X86::ROL16m1, 0 },
175 { X86::ROL16rCL, X86::ROL16mCL, 0 },
176 { X86::ROL16ri, X86::ROL16mi, 0 },
177 { X86::ROL32r1, X86::ROL32m1, 0 },
178 { X86::ROL32rCL, X86::ROL32mCL, 0 },
179 { X86::ROL32ri, X86::ROL32mi, 0 },
180 { X86::ROL64r1, X86::ROL64m1, 0 },
181 { X86::ROL64rCL, X86::ROL64mCL, 0 },
182 { X86::ROL64ri, X86::ROL64mi, 0 },
183 { X86::ROL8r1, X86::ROL8m1, 0 },
184 { X86::ROL8rCL, X86::ROL8mCL, 0 },
185 { X86::ROL8ri, X86::ROL8mi, 0 },
186 { X86::ROR16r1, X86::ROR16m1, 0 },
187 { X86::ROR16rCL, X86::ROR16mCL, 0 },
188 { X86::ROR16ri, X86::ROR16mi, 0 },
189 { X86::ROR32r1, X86::ROR32m1, 0 },
190 { X86::ROR32rCL, X86::ROR32mCL, 0 },
191 { X86::ROR32ri, X86::ROR32mi, 0 },
192 { X86::ROR64r1, X86::ROR64m1, 0 },
193 { X86::ROR64rCL, X86::ROR64mCL, 0 },
194 { X86::ROR64ri, X86::ROR64mi, 0 },
195 { X86::ROR8r1, X86::ROR8m1, 0 },
196 { X86::ROR8rCL, X86::ROR8mCL, 0 },
197 { X86::ROR8ri, X86::ROR8mi, 0 },
198 { X86::SAR16r1, X86::SAR16m1, 0 },
199 { X86::SAR16rCL, X86::SAR16mCL, 0 },
200 { X86::SAR16ri, X86::SAR16mi, 0 },
201 { X86::SAR32r1, X86::SAR32m1, 0 },
202 { X86::SAR32rCL, X86::SAR32mCL, 0 },
203 { X86::SAR32ri, X86::SAR32mi, 0 },
204 { X86::SAR64r1, X86::SAR64m1, 0 },
205 { X86::SAR64rCL, X86::SAR64mCL, 0 },
206 { X86::SAR64ri, X86::SAR64mi, 0 },
207 { X86::SAR8r1, X86::SAR8m1, 0 },
208 { X86::SAR8rCL, X86::SAR8mCL, 0 },
209 { X86::SAR8ri, X86::SAR8mi, 0 },
210 { X86::SBB32ri, X86::SBB32mi, 0 },
211 { X86::SBB32ri8, X86::SBB32mi8, 0 },
212 { X86::SBB32rr, X86::SBB32mr, 0 },
213 { X86::SBB64ri32, X86::SBB64mi32, 0 },
214 { X86::SBB64ri8, X86::SBB64mi8, 0 },
215 { X86::SBB64rr, X86::SBB64mr, 0 },
216 { X86::SHL16rCL, X86::SHL16mCL, 0 },
217 { X86::SHL16ri, X86::SHL16mi, 0 },
218 { X86::SHL32rCL, X86::SHL32mCL, 0 },
219 { X86::SHL32ri, X86::SHL32mi, 0 },
220 { X86::SHL64rCL, X86::SHL64mCL, 0 },
221 { X86::SHL64ri, X86::SHL64mi, 0 },
222 { X86::SHL8rCL, X86::SHL8mCL, 0 },
223 { X86::SHL8ri, X86::SHL8mi, 0 },
224 { X86::SHLD16rrCL, X86::SHLD16mrCL, 0 },
225 { X86::SHLD16rri8, X86::SHLD16mri8, 0 },
226 { X86::SHLD32rrCL, X86::SHLD32mrCL, 0 },
227 { X86::SHLD32rri8, X86::SHLD32mri8, 0 },
228 { X86::SHLD64rrCL, X86::SHLD64mrCL, 0 },
229 { X86::SHLD64rri8, X86::SHLD64mri8, 0 },
230 { X86::SHR16r1, X86::SHR16m1, 0 },
231 { X86::SHR16rCL, X86::SHR16mCL, 0 },
232 { X86::SHR16ri, X86::SHR16mi, 0 },
233 { X86::SHR32r1, X86::SHR32m1, 0 },
234 { X86::SHR32rCL, X86::SHR32mCL, 0 },
235 { X86::SHR32ri, X86::SHR32mi, 0 },
236 { X86::SHR64r1, X86::SHR64m1, 0 },
237 { X86::SHR64rCL, X86::SHR64mCL, 0 },
238 { X86::SHR64ri, X86::SHR64mi, 0 },
239 { X86::SHR8r1, X86::SHR8m1, 0 },
240 { X86::SHR8rCL, X86::SHR8mCL, 0 },
241 { X86::SHR8ri, X86::SHR8mi, 0 },
242 { X86::SHRD16rrCL, X86::SHRD16mrCL, 0 },
243 { X86::SHRD16rri8, X86::SHRD16mri8, 0 },
244 { X86::SHRD32rrCL, X86::SHRD32mrCL, 0 },
245 { X86::SHRD32rri8, X86::SHRD32mri8, 0 },
246 { X86::SHRD64rrCL, X86::SHRD64mrCL, 0 },
247 { X86::SHRD64rri8, X86::SHRD64mri8, 0 },
248 { X86::SUB16ri, X86::SUB16mi, 0 },
249 { X86::SUB16ri8, X86::SUB16mi8, 0 },
250 { X86::SUB16rr, X86::SUB16mr, 0 },
251 { X86::SUB32ri, X86::SUB32mi, 0 },
252 { X86::SUB32ri8, X86::SUB32mi8, 0 },
253 { X86::SUB32rr, X86::SUB32mr, 0 },
254 { X86::SUB64ri32, X86::SUB64mi32, 0 },
255 { X86::SUB64ri8, X86::SUB64mi8, 0 },
256 { X86::SUB64rr, X86::SUB64mr, 0 },
257 { X86::SUB8ri, X86::SUB8mi, 0 },
258 { X86::SUB8rr, X86::SUB8mr, 0 },
259 { X86::XOR16ri, X86::XOR16mi, 0 },
260 { X86::XOR16ri8, X86::XOR16mi8, 0 },
261 { X86::XOR16rr, X86::XOR16mr, 0 },
262 { X86::XOR32ri, X86::XOR32mi, 0 },
263 { X86::XOR32ri8, X86::XOR32mi8, 0 },
264 { X86::XOR32rr, X86::XOR32mr, 0 },
265 { X86::XOR64ri32, X86::XOR64mi32, 0 },
266 { X86::XOR64ri8, X86::XOR64mi8, 0 },
267 { X86::XOR64rr, X86::XOR64mr, 0 },
268 { X86::XOR8ri, X86::XOR8mi, 0 },
269 { X86::XOR8rr, X86::XOR8mr, 0 }
273 AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
274 Entry.RegOp, Entry.MemOp,
425 AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
426 Entry.RegOp, Entry.MemOp,
TB_INDEX_0 | Entry.Flags);
430 { X86::BSF16rr, X86::BSF16rm, 0 },
431 { X86::BSF32rr, X86::BSF32rm, 0 },
432 { X86::BSF64rr, X86::BSF64rm, 0 },
433 { X86::BSR16rr, X86::BSR16rm, 0 },
434 { X86::BSR32rr, X86::BSR32rm, 0 },
435 { X86::BSR64rr, X86::BSR64rm, 0 },
436 { X86::CMP16rr, X86::CMP16rm, 0 },
437 { X86::CMP32rr, X86::CMP32rm, 0 },
438 { X86::CMP64rr, X86::CMP64rm, 0 },
439 { X86::CMP8rr, X86::CMP8rm, 0 },
440 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
441 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
442 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
443 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
444 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
445 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
446 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
447 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
448 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
449 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
450 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
451 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
452 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
453 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
454 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
455 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
456 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
457 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
458 { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 },
459 { X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 },
460 { X86::CVTSS2SI64rr, X86::CVTSS2SI64rm, 0 },
461 { X86::CVTSS2SIrr, X86::CVTSS2SIrm, 0 },
468 { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm,
TB_ALIGN_16 },
469 { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm,
TB_ALIGN_16 },
470 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
471 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
472 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
473 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
474 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
475 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
476 { X86::MOV16rr, X86::MOV16rm, 0 },
477 { X86::MOV32rr, X86::MOV32rm, 0 },
478 { X86::MOV64rr, X86::MOV64rm, 0 },
479 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
480 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
481 { X86::MOV8rr, X86::MOV8rm, 0 },
484 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
485 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
486 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
490 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
491 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
492 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
493 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
494 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
495 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
497 { X86::MOVUPSrr, X86::MOVUPSrm, 0 },
498 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 },
499 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm,
TB_ALIGN_16 },
500 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
501 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
502 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
503 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
507 { X86::PCMPESTRIrr, X86::PCMPESTRIrm,
TB_ALIGN_16 },
508 { X86::PCMPESTRM128rr, X86::PCMPESTRM128rm,
TB_ALIGN_16 },
509 { X86::PCMPISTRIrr, X86::PCMPISTRIrm,
TB_ALIGN_16 },
510 { X86::PCMPISTRM128rr, X86::PCMPISTRM128rm,
TB_ALIGN_16 },
511 { X86::PHMINPOSUWrr128, X86::PHMINPOSUWrm128,
TB_ALIGN_16 },
529 { X86::RCPSSr, X86::RCPSSm, 0 },
530 { X86::RCPSSr_Int, X86::RCPSSm_Int, 0 },
534 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
535 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
538 { X86::SQRTSDr, X86::SQRTSDm, 0 },
539 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
540 { X86::SQRTSSr, X86::SQRTSSm, 0 },
541 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
542 { X86::TEST16rr, X86::TEST16rm, 0 },
543 { X86::TEST32rr, X86::TEST32rm, 0 },
544 { X86::TEST64rr, X86::TEST64rm, 0 },
545 { X86::TEST8rr, X86::TEST8rm, 0 },
547 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
548 { X86::UCOMISSrr, X86::UCOMISSrm, 0 },
551 { X86::MMX_CVTPD2PIirr, X86::MMX_CVTPD2PIirm, 0 },
552 { X86::MMX_CVTPI2PDirr, X86::MMX_CVTPI2PDirm, 0 },
553 { X86::MMX_CVTPS2PIirr, X86::MMX_CVTPS2PIirm, 0 },
554 { X86::MMX_CVTTPD2PIirr, X86::MMX_CVTTPD2PIirm, 0 },
555 { X86::MMX_CVTTPS2PIirr, X86::MMX_CVTTPS2PIirm, 0 },
556 { X86::MMX_MOVD64to64rr, X86::MMX_MOVQ64rm, 0 },
557 { X86::MMX_PABSBrr64, X86::MMX_PABSBrm64, 0 },
558 { X86::MMX_PABSDrr64, X86::MMX_PABSDrm64, 0 },
559 { X86::MMX_PABSWrr64, X86::MMX_PABSWrm64, 0 },
560 { X86::MMX_PSHUFWri, X86::MMX_PSHUFWmi, 0 },
563 { X86::PF2IDrr, X86::PF2IDrm, 0 },
564 { X86::PF2IWrr, X86::PF2IWrm, 0 },
565 { X86::PFRCPrr, X86::PFRCPrm, 0 },
566 { X86::PFRSQRTrr, X86::PFRSQRTrm, 0 },
567 { X86::PI2FDrr, X86::PI2FDrm, 0 },
568 { X86::PI2FWrr, X86::PI2FWrm, 0 },
569 { X86::PSWAPDrr, X86::PSWAPDrm, 0 },
572 { X86::Int_VCOMISDrr, X86::Int_VCOMISDrm, 0 },
573 { X86::Int_VCOMISSrr, X86::Int_VCOMISSrm, 0 },
574 { X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, 0 },
575 { X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, 0 },
576 { X86::VCVTTSD2SI64rr, X86::VCVTTSD2SI64rm, 0 },
577 { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
578 { X86::VCVTTSD2SIrr, X86::VCVTTSD2SIrm, 0 },
579 { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm, 0 },
580 { X86::VCVTTSS2SI64rr, X86::VCVTTSS2SI64rm, 0 },
581 { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
582 { X86::VCVTTSS2SIrr, X86::VCVTTSS2SIrm, 0 },
583 { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm, 0 },
584 { X86::VCVTSD2SI64rr, X86::VCVTSD2SI64rm, 0 },
585 { X86::VCVTSD2SIrr, X86::VCVTSD2SIrm, 0 },
586 { X86::VCVTSS2SI64rr, X86::VCVTSS2SI64rm, 0 },
587 { X86::VCVTSS2SIrr, X86::VCVTSS2SIrm, 0 },
588 { X86::VCVTDQ2PDrr, X86::VCVTDQ2PDrm, 0 },
589 { X86::VCVTDQ2PSrr, X86::VCVTDQ2PSrm, 0 },
590 { X86::VCVTPD2DQrr, X86::VCVTPD2DQXrm, 0 },
591 { X86::VCVTPD2PSrr, X86::VCVTPD2PSXrm, 0 },
592 { X86::VCVTPS2DQrr, X86::VCVTPS2DQrm, 0 },
593 { X86::VCVTPS2PDrr, X86::VCVTPS2PDrm, 0 },
594 { X86::VCVTTPD2DQrr, X86::VCVTTPD2DQXrm, 0 },
595 { X86::VCVTTPS2DQrr, X86::VCVTTPS2DQrm, 0 },
596 { X86::VMOV64toPQIrr, X86::VMOVQI2PQIrm, 0 },
597 { X86::VMOV64toSDrr, X86::VMOV64toSDrm, 0 },
600 { X86::VMOVDDUPrr, X86::VMOVDDUPrm, 0 },
601 { X86::VMOVDI2PDIrr, X86::VMOVDI2PDIrm, 0 },
602 { X86::VMOVDI2SSrr, X86::VMOVDI2SSrm, 0 },
604 { X86::VMOVSLDUPrr, X86::VMOVSLDUPrm, 0 },
605 { X86::VMOVSHDUPrr, X86::VMOVSHDUPrm, 0 },
606 { X86::VMOVUPDrr, X86::VMOVUPDrm, 0 },
607 { X86::VMOVUPSrr, X86::VMOVUPSrm, 0 },
608 { X86::VMOVZQI2PQIrr, X86::VMOVZQI2PQIrm, 0 },
609 { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm,
TB_ALIGN_16 },
610 { X86::VPABSBrr128, X86::VPABSBrm128, 0 },
611 { X86::VPABSDrr128, X86::VPABSDrm128, 0 },
612 { X86::VPABSWrr128, X86::VPABSWrm128, 0 },
613 { X86::VPCMPESTRIrr, X86::VPCMPESTRIrm, 0 },
614 { X86::VPCMPESTRM128rr, X86::VPCMPESTRM128rm, 0 },
615 { X86::VPCMPISTRIrr, X86::VPCMPISTRIrm, 0 },
616 { X86::VPCMPISTRM128rr, X86::VPCMPISTRM128rm, 0 },
617 { X86::VPHMINPOSUWrr128, X86::VPHMINPOSUWrm128, 0 },
618 { X86::VPERMILPDri, X86::VPERMILPDmi, 0 },
619 { X86::VPERMILPSri, X86::VPERMILPSmi, 0 },
620 { X86::VPMOVSXBDrr, X86::VPMOVSXBDrm, 0 },
621 { X86::VPMOVSXBQrr, X86::VPMOVSXBQrm, 0 },
622 { X86::VPMOVSXBWrr, X86::VPMOVSXBWrm, 0 },
623 { X86::VPMOVSXDQrr, X86::VPMOVSXDQrm, 0 },
624 { X86::VPMOVSXWDrr, X86::VPMOVSXWDrm, 0 },
625 { X86::VPMOVSXWQrr, X86::VPMOVSXWQrm, 0 },
626 { X86::VPMOVZXBDrr, X86::VPMOVZXBDrm, 0 },
627 { X86::VPMOVZXBQrr, X86::VPMOVZXBQrm, 0 },
628 { X86::VPMOVZXBWrr, X86::VPMOVZXBWrm, 0 },
629 { X86::VPMOVZXDQrr, X86::VPMOVZXDQrm, 0 },
630 { X86::VPMOVZXWDrr, X86::VPMOVZXWDrm, 0 },
631 { X86::VPMOVZXWQrr, X86::VPMOVZXWQrm, 0 },
632 { X86::VPSHUFDri, X86::VPSHUFDmi, 0 },
633 { X86::VPSHUFHWri, X86::VPSHUFHWmi, 0 },
634 { X86::VPSHUFLWri, X86::VPSHUFLWmi, 0 },
635 { X86::VPTESTrr, X86::VPTESTrm, 0 },
636 { X86::VRCPPSr, X86::VRCPPSm, 0 },
637 { X86::VROUNDPDr, X86::VROUNDPDm, 0 },
638 { X86::VROUNDPSr, X86::VROUNDPSm, 0 },
639 { X86::VRSQRTPSr, X86::VRSQRTPSm, 0 },
640 { X86::VSQRTPDr, X86::VSQRTPDm, 0 },
641 { X86::VSQRTPSr, X86::VSQRTPSm, 0 },
642 { X86::VTESTPDrr, X86::VTESTPDrm, 0 },
643 { X86::VTESTPSrr, X86::VTESTPSrm, 0 },
644 { X86::VUCOMISDrr, X86::VUCOMISDrm, 0 },
645 { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 },
648 { X86::VCVTDQ2PDYrr, X86::VCVTDQ2PDYrm, 0 },
649 { X86::VCVTDQ2PSYrr, X86::VCVTDQ2PSYrm, 0 },
650 { X86::VCVTPD2DQYrr, X86::VCVTPD2DQYrm, 0 },
651 { X86::VCVTPD2PSYrr, X86::VCVTPD2PSYrm, 0 },
652 { X86::VCVTPS2DQYrr, X86::VCVTPS2DQYrm, 0 },
653 { X86::VCVTPS2PDYrr, X86::VCVTPS2PDYrm, 0 },
654 { X86::VCVTTPD2DQYrr, X86::VCVTTPD2DQYrm, 0 },
655 { X86::VCVTTPS2DQYrr, X86::VCVTTPS2DQYrm, 0 },
658 { X86::VMOVDDUPYrr, X86::VMOVDDUPYrm, 0 },
660 { X86::VMOVSLDUPYrr, X86::VMOVSLDUPYrm, 0 },
661 { X86::VMOVSHDUPYrr, X86::VMOVSHDUPYrm, 0 },
662 { X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 },
663 { X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 },
664 { X86::VPERMILPDYri, X86::VPERMILPDYmi, 0 },
665 { X86::VPERMILPSYri, X86::VPERMILPSYmi, 0 },
666 { X86::VPTESTYrr, X86::VPTESTYrm, 0 },
667 { X86::VRCPPSYr, X86::VRCPPSYm, 0 },
668 { X86::VROUNDYPDr, X86::VROUNDYPDm, 0 },
669 { X86::VROUNDYPSr, X86::VROUNDYPSm, 0 },
670 { X86::VRSQRTPSYr, X86::VRSQRTPSYm, 0 },
671 { X86::VSQRTPDYr, X86::VSQRTPDYm, 0 },
672 { X86::VSQRTPSYr, X86::VSQRTPSYm, 0 },
673 { X86::VTESTPDYrr, X86::VTESTPDYrm, 0 },
674 { X86::VTESTPSYrr, X86::VTESTPSYrm, 0 },
684 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm,
TB_NO_REVERSE },
685 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm,
TB_NO_REVERSE },
686 { X86::VPABSBrr256, X86::VPABSBrm256, 0 },
687 { X86::VPABSDrr256, X86::VPABSDrm256, 0 },
688 { X86::VPABSWrr256, X86::VPABSWrm256, 0 },
689 { X86::VPBROADCASTBrr, X86::VPBROADCASTBrm, 0 },
690 { X86::VPBROADCASTBYrr, X86::VPBROADCASTBYrm, 0 },
691 { X86::VPBROADCASTDrr, X86::VPBROADCASTDrm, 0 },
692 { X86::VPBROADCASTDYrr, X86::VPBROADCASTDYrm, 0 },
693 { X86::VPBROADCASTQrr, X86::VPBROADCASTQrm, 0 },
694 { X86::VPBROADCASTQYrr, X86::VPBROADCASTQYrm, 0 },
695 { X86::VPBROADCASTWrr, X86::VPBROADCASTWrm, 0 },
696 { X86::VPBROADCASTWYrr, X86::VPBROADCASTWYrm, 0 },
697 { X86::VPERMPDYri, X86::VPERMPDYmi, 0 },
698 { X86::VPERMQYri, X86::VPERMQYmi, 0 },
699 { X86::VPMOVSXBDYrr, X86::VPMOVSXBDYrm, 0 },
700 { X86::VPMOVSXBQYrr, X86::VPMOVSXBQYrm, 0 },
701 { X86::VPMOVSXBWYrr, X86::VPMOVSXBWYrm, 0 },
702 { X86::VPMOVSXDQYrr, X86::VPMOVSXDQYrm, 0 },
703 { X86::VPMOVSXWDYrr, X86::VPMOVSXWDYrm, 0 },
704 { X86::VPMOVSXWQYrr, X86::VPMOVSXWQYrm, 0 },
705 { X86::VPMOVZXBDYrr, X86::VPMOVZXBDYrm, 0 },
706 { X86::VPMOVZXBQYrr, X86::VPMOVZXBQYrm, 0 },
707 { X86::VPMOVZXBWYrr, X86::VPMOVZXBWYrm, 0 },
708 { X86::VPMOVZXDQYrr, X86::VPMOVZXDQYrm, 0 },
709 { X86::VPMOVZXWDYrr, X86::VPMOVZXWDYrm, 0 },
710 { X86::VPMOVZXWQYrr, X86::VPMOVZXWQYrm, 0 },
711 { X86::VPSHUFDYri, X86::VPSHUFDYmi, 0 },
712 { X86::VPSHUFHWYri, X86::VPSHUFHWYmi, 0 },
713 { X86::VPSHUFLWYri, X86::VPSHUFLWYmi, 0 },
716 { X86::VFRCZPDrr, X86::VFRCZPDrm, 0 },
717 { X86::VFRCZPDrrY, X86::VFRCZPDrmY, 0 },
718 { X86::VFRCZPSrr, X86::VFRCZPSrm, 0 },
719 { X86::VFRCZPSrrY, X86::VFRCZPSrmY, 0 },
720 { X86::VFRCZSDrr, X86::VFRCZSDrm, 0 },
721 { X86::VFRCZSSrr, X86::VFRCZSSrm, 0 },
722 { X86::VPHADDBDrr, X86::VPHADDBDrm, 0 },
723 { X86::VPHADDBQrr, X86::VPHADDBQrm, 0 },
724 { X86::VPHADDBWrr, X86::VPHADDBWrm, 0 },
725 { X86::VPHADDDQrr, X86::VPHADDDQrm, 0 },
726 { X86::VPHADDWDrr, X86::VPHADDWDrm, 0 },
727 { X86::VPHADDWQrr, X86::VPHADDWQrm, 0 },
728 { X86::VPHADDUBDrr, X86::VPHADDUBDrm, 0 },
729 { X86::VPHADDUBQrr, X86::VPHADDUBQrm, 0 },
730 { X86::VPHADDUBWrr, X86::VPHADDUBWrm, 0 },
731 { X86::VPHADDUDQrr, X86::VPHADDUDQrm, 0 },
732 { X86::VPHADDUWDrr, X86::VPHADDUWDrm, 0 },
733 { X86::VPHADDUWQrr, X86::VPHADDUWQrm, 0 },
734 { X86::VPHSUBBWrr, X86::VPHSUBBWrm, 0 },
735 { X86::VPHSUBDQrr, X86::VPHSUBDQrm, 0 },
736 { X86::VPHSUBWDrr, X86::VPHSUBWDrm, 0 },
737 { X86::VPROTBri, X86::VPROTBmi, 0 },
738 { X86::VPROTBrr, X86::VPROTBmr, 0 },
739 { X86::VPROTDri, X86::VPROTDmi, 0 },
740 { X86::VPROTDrr, X86::VPROTDmr, 0 },
741 { X86::VPROTQri, X86::VPROTQmi, 0 },
742 { X86::VPROTQrr, X86::VPROTQmr, 0 },
743 { X86::VPROTWri, X86::VPROTWmi, 0 },
744 { X86::VPROTWrr, X86::VPROTWmr, 0 },
745 { X86::VPSHABrr, X86::VPSHABmr, 0 },
746 { X86::VPSHADrr, X86::VPSHADmr, 0 },
747 { X86::VPSHAQrr, X86::VPSHAQmr, 0 },
748 { X86::VPSHAWrr, X86::VPSHAWmr, 0 },
749 { X86::VPSHLBrr, X86::VPSHLBmr, 0 },
750 { X86::VPSHLDrr, X86::VPSHLDmr, 0 },
751 { X86::VPSHLQrr, X86::VPSHLQmr, 0 },
752 { X86::VPSHLWrr, X86::VPSHLWmr, 0 },
755 { X86::BEXTR32rr, X86::BEXTR32rm, 0 },
756 { X86::BEXTR64rr, X86::BEXTR64rm, 0 },
757 { X86::BEXTRI32ri, X86::BEXTRI32mi, 0 },
758 { X86::BEXTRI64ri, X86::BEXTRI64mi, 0 },
759 { X86::BLCFILL32rr, X86::BLCFILL32rm, 0 },
760 { X86::BLCFILL64rr, X86::BLCFILL64rm, 0 },
761 { X86::BLCI32rr, X86::BLCI32rm, 0 },
762 { X86::BLCI64rr, X86::BLCI64rm, 0 },
763 { X86::BLCIC32rr, X86::BLCIC32rm, 0 },
764 { X86::BLCIC64rr, X86::BLCIC64rm, 0 },
765 { X86::BLCMSK32rr, X86::BLCMSK32rm, 0 },
766 { X86::BLCMSK64rr, X86::BLCMSK64rm, 0 },
767 { X86::BLCS32rr, X86::BLCS32rm, 0 },
768 { X86::BLCS64rr, X86::BLCS64rm, 0 },
769 { X86::BLSFILL32rr, X86::BLSFILL32rm, 0 },
770 { X86::BLSFILL64rr, X86::BLSFILL64rm, 0 },
771 { X86::BLSI32rr, X86::BLSI32rm, 0 },
772 { X86::BLSI64rr, X86::BLSI64rm, 0 },
773 { X86::BLSIC32rr, X86::BLSIC32rm, 0 },
774 { X86::BLSIC64rr, X86::BLSIC64rm, 0 },
775 { X86::BLSMSK32rr, X86::BLSMSK32rm, 0 },
776 { X86::BLSMSK64rr, X86::BLSMSK64rm, 0 },
777 { X86::BLSR32rr, X86::BLSR32rm, 0 },
778 { X86::BLSR64rr, X86::BLSR64rm, 0 },
779 { X86::BZHI32rr, X86::BZHI32rm, 0 },
780 { X86::BZHI64rr, X86::BZHI64rm, 0 },
781 { X86::LZCNT16rr, X86::LZCNT16rm, 0 },
782 { X86::LZCNT32rr, X86::LZCNT32rm, 0 },
783 { X86::LZCNT64rr, X86::LZCNT64rm, 0 },
784 { X86::POPCNT16rr, X86::POPCNT16rm, 0 },
785 { X86::POPCNT32rr, X86::POPCNT32rm, 0 },
786 { X86::POPCNT64rr, X86::POPCNT64rm, 0 },
787 { X86::RORX32ri, X86::RORX32mi, 0 },
788 { X86::RORX64ri, X86::RORX64mi, 0 },
789 { X86::SARX32rr, X86::SARX32rm, 0 },
790 { X86::SARX64rr, X86::SARX64rm, 0 },
791 { X86::SHRX32rr, X86::SHRX32rm, 0 },
792 { X86::SHRX64rr, X86::SHRX64rm, 0 },
793 { X86::SHLX32rr, X86::SHLX32rm, 0 },
794 { X86::SHLX64rr, X86::SHLX64rm, 0 },
795 { X86::T1MSKC32rr, X86::T1MSKC32rm, 0 },
796 { X86::T1MSKC64rr, X86::T1MSKC64rm, 0 },
797 { X86::TZCNT16rr, X86::TZCNT16rm, 0 },
798 { X86::TZCNT32rr, X86::TZCNT32rm, 0 },
799 { X86::TZCNT64rr, X86::TZCNT64rm, 0 },
800 { X86::TZMSK32rr, X86::TZMSK32rm, 0 },
801 { X86::TZMSK64rr, X86::TZMSK64rm, 0 },
804 { X86::VMOV64toPQIZrr, X86::VMOVQI2PQIZrm, 0 },
805 { X86::VMOVDI2SSZrr, X86::VMOVDI2SSZrm, 0 },
808 { X86::VMOVDQA32Zrr, X86::VMOVDQA32Zrm,
TB_ALIGN_64 },
809 { X86::VMOVDQA64Zrr, X86::VMOVDQA64Zrm,
TB_ALIGN_64 },
810 { X86::VMOVDQU8Zrr, X86::VMOVDQU8Zrm, 0 },
811 { X86::VMOVDQU16Zrr, X86::VMOVDQU16Zrm, 0 },
812 { X86::VMOVDQU32Zrr, X86::VMOVDQU32Zrm, 0 },
813 { X86::VMOVDQU64Zrr, X86::VMOVDQU64Zrm, 0 },
814 { X86::VMOVUPDZrr, X86::VMOVUPDZrm, 0 },
815 { X86::VMOVUPSZrr, X86::VMOVUPSZrm, 0 },
816 { X86::VPABSDZrr, X86::VPABSDZrm, 0 },
817 { X86::VPABSQZrr, X86::VPABSQZrm, 0 },
822 { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256rm,
TB_ALIGN_32 },
823 { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256rm,
TB_ALIGN_32 },
824 { X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256rm,
TB_ALIGN_32 },
825 { X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256rm,
TB_ALIGN_32 },
826 { X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256rm, 0 },
827 { X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256rm, 0 },
828 { X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256rm, 0 },
829 { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256rm, 0 },
830 { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256rm, 0 },
831 { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256rm, 0 },
832 { X86::VBROADCASTSSZ256r, X86::VBROADCASTSSZ256m,
TB_NO_REVERSE },
833 { X86::VBROADCASTSDZ256r, X86::VBROADCASTSDZ256m,
TB_NO_REVERSE },
836 { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128rm,
TB_ALIGN_16 },
837 { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128rm,
TB_ALIGN_16 },
838 { X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128rm,
TB_ALIGN_16 },
839 { X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128rm,
TB_ALIGN_16 },
840 { X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128rm, 0 },
841 { X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128rm, 0 },
842 { X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128rm, 0 },
843 { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128rm, 0 },
844 { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128rm, 0 },
845 { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128rm, 0 },
846 { X86::VBROADCASTSSZ128r, X86::VBROADCASTSSZ128m,
TB_NO_REVERSE },
849 { X86::VCVTPH2PSrr, X86::VCVTPH2PSrm, 0 },
850 { X86::VCVTPH2PSYrr, X86::VCVTPH2PSYrm, 0 },
854 { X86::AESKEYGENASSIST128rr, X86::AESKEYGENASSIST128rm,
TB_ALIGN_16 },
855 { X86::VAESIMCrr, X86::VAESIMCrm, 0 },
856 { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, 0 }
860 AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
861 Entry.RegOp, Entry.MemOp,
867 { X86::ADC32rr, X86::ADC32rm, 0 },
868 { X86::ADC64rr, X86::ADC64rm, 0 },
869 { X86::ADD16rr, X86::ADD16rm, 0 },
871 { X86::ADD32rr, X86::ADD32rm, 0 },
873 { X86::ADD64rr, X86::ADD64rm, 0 },
875 { X86::ADD8rr, X86::ADD8rm, 0 },
878 { X86::ADDSDrr, X86::ADDSDrm, 0 },
879 { X86::ADDSDrr_Int, X86::ADDSDrm_Int, 0 },
880 { X86::ADDSSrr, X86::ADDSSrm, 0 },
881 { X86::ADDSSrr_Int, X86::ADDSSrm_Int, 0 },
884 { X86::AND16rr, X86::AND16rm, 0 },
885 { X86::AND32rr, X86::AND32rm, 0 },
886 { X86::AND64rr, X86::AND64rm, 0 },
887 { X86::AND8rr, X86::AND8rm, 0 },
894 { X86::BLENDVPDrr0, X86::BLENDVPDrm0,
TB_ALIGN_16 },
895 { X86::BLENDVPSrr0, X86::BLENDVPSrm0,
TB_ALIGN_16 },
896 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
897 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
898 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
899 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
900 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
901 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
902 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
903 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
904 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
905 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
906 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
907 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
908 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
909 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
910 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
911 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
912 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
913 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
914 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
915 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
916 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
917 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
918 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
919 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
920 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
921 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
922 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
923 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
924 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
925 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
926 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
927 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
928 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
929 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
930 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
931 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
932 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
933 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
934 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
935 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
936 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
937 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
938 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
939 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
940 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
941 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
942 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
943 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
946 { X86::CMPSDrr, X86::CMPSDrm, 0 },
947 { X86::CMPSSrr, X86::CMPSSrm, 0 },
948 { X86::CRC32r32r32, X86::CRC32r32m32, 0 },
949 { X86::CRC32r64r64, X86::CRC32r64m64, 0 },
952 { X86::DIVSDrr, X86::DIVSDrm, 0 },
953 { X86::DIVSDrr_Int, X86::DIVSDrm_Int, 0 },
954 { X86::DIVSSrr, X86::DIVSSrm, 0 },
955 { X86::DIVSSrr_Int, X86::DIVSSrm_Int, 0 },
975 { X86::IMUL16rr, X86::IMUL16rm, 0 },
976 { X86::IMUL32rr, X86::IMUL32rm, 0 },
977 { X86::IMUL64rr, X86::IMUL64rm, 0 },
978 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
979 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
980 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
981 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
982 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
983 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
984 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
985 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
988 { X86::MAXSDrr, X86::MAXSDrm, 0 },
989 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 },
990 { X86::MAXSSrr, X86::MAXSSrm, 0 },
991 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 },
994 { X86::MINSDrr, X86::MINSDrm, 0 },
995 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 },
996 { X86::MINSSrr, X86::MINSSrm, 0 },
997 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 },
1001 { X86::MULSDrr, X86::MULSDrm, 0 },
1002 { X86::MULSDrr_Int, X86::MULSDrm_Int, 0 },
1003 { X86::MULSSrr, X86::MULSSrm, 0 },
1004 { X86::MULSSrr_Int, X86::MULSSrm_Int, 0 },
1005 { X86::OR16rr, X86::OR16rm, 0 },
1006 { X86::OR32rr, X86::OR32rm, 0 },
1007 { X86::OR64rr, X86::OR64rm, 0 },
1008 { X86::OR8rr, X86::OR8rm, 0 },
1011 { X86::PACKSSDWrr, X86::PACKSSDWrm,
TB_ALIGN_16 },
1012 { X86::PACKSSWBrr, X86::PACKSSWBrm,
TB_ALIGN_16 },
1013 { X86::PACKUSDWrr, X86::PACKUSDWrm,
TB_ALIGN_16 },
1014 { X86::PACKUSWBrr, X86::PACKUSWBrm,
TB_ALIGN_16 },
1023 { X86::PALIGNR128rr, X86::PALIGNR128rm,
TB_ALIGN_16 },
1028 { X86::PBLENDVBrr0, X86::PBLENDVBrm0,
TB_ALIGN_16 },
1029 { X86::PBLENDWrri, X86::PBLENDWrmi,
TB_ALIGN_16 },
1030 { X86::PCLMULQDQrr, X86::PCLMULQDQrm,
TB_ALIGN_16 },
1041 { X86::PHADDSWrr128, X86::PHADDSWrm128,
TB_ALIGN_16 },
1043 { X86::PHSUBSWrr128, X86::PHSUBSWrm128,
TB_ALIGN_16 },
1045 { X86::PINSRBrr, X86::PINSRBrm, 0 },
1046 { X86::PINSRDrr, X86::PINSRDrm, 0 },
1047 { X86::PINSRQrr, X86::PINSRQrm, 0 },
1048 { X86::PINSRWrri, X86::PINSRWrmi, 0 },
1049 { X86::PMADDUBSWrr128, X86::PMADDUBSWrm128,
TB_ALIGN_16 },
1064 { X86::PMULHRSWrr128, X86::PMULHRSWrm128,
TB_ALIGN_16 },
1092 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm,
TB_ALIGN_16 },
1093 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm,
TB_ALIGN_16 },
1094 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm,
TB_ALIGN_16 },
1095 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm,
TB_ALIGN_16 },
1096 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm,
TB_ALIGN_16 },
1097 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm,
TB_ALIGN_16 },
1098 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm,
TB_ALIGN_16 },
1099 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm,
TB_ALIGN_16 },
1101 { X86::ROUNDSDr, X86::ROUNDSDm, 0 },
1102 { X86::ROUNDSSr, X86::ROUNDSSm, 0 },
1103 { X86::SBB32rr, X86::SBB32rm, 0 },
1104 { X86::SBB64rr, X86::SBB64rm, 0 },
1107 { X86::SUB16rr, X86::SUB16rm, 0 },
1108 { X86::SUB32rr, X86::SUB32rm, 0 },
1109 { X86::SUB64rr, X86::SUB64rm, 0 },
1110 { X86::SUB8rr, X86::SUB8rm, 0 },
1113 { X86::SUBSDrr, X86::SUBSDrm, 0 },
1114 { X86::SUBSDrr_Int, X86::SUBSDrm_Int, 0 },
1115 { X86::SUBSSrr, X86::SUBSSrm, 0 },
1116 { X86::SUBSSrr_Int, X86::SUBSSrm_Int, 0 },
1118 { X86::UNPCKHPDrr, X86::UNPCKHPDrm,
TB_ALIGN_16 },
1119 { X86::UNPCKHPSrr, X86::UNPCKHPSrm,
TB_ALIGN_16 },
1120 { X86::UNPCKLPDrr, X86::UNPCKLPDrm,
TB_ALIGN_16 },
1121 { X86::UNPCKLPSrr, X86::UNPCKLPSrm,
TB_ALIGN_16 },
1122 { X86::XOR16rr, X86::XOR16rm, 0 },
1123 { X86::XOR32rr, X86::XOR32rm, 0 },
1124 { X86::XOR64rr, X86::XOR64rm, 0 },
1125 { X86::XOR8rr, X86::XOR8rm, 0 },
1130 { X86::MMX_CVTPI2PSirr, X86::MMX_CVTPI2PSirm, 0 },
1131 { X86::MMX_PACKSSDWirr, X86::MMX_PACKSSDWirm, 0 },
1132 { X86::MMX_PACKSSWBirr, X86::MMX_PACKSSWBirm, 0 },
1133 { X86::MMX_PACKUSWBirr, X86::MMX_PACKUSWBirm, 0 },
1134 { X86::MMX_PADDBirr, X86::MMX_PADDBirm, 0 },
1135 { X86::MMX_PADDDirr, X86::MMX_PADDDirm, 0 },
1136 { X86::MMX_PADDQirr, X86::MMX_PADDQirm, 0 },
1137 { X86::MMX_PADDSBirr, X86::MMX_PADDSBirm, 0 },
1138 { X86::MMX_PADDSWirr, X86::MMX_PADDSWirm, 0 },
1139 { X86::MMX_PADDUSBirr, X86::MMX_PADDUSBirm, 0 },
1140 { X86::MMX_PADDUSWirr, X86::MMX_PADDUSWirm, 0 },
1141 { X86::MMX_PADDWirr, X86::MMX_PADDWirm, 0 },
1142 { X86::MMX_PALIGNR64irr, X86::MMX_PALIGNR64irm, 0 },
1143 { X86::MMX_PANDNirr, X86::MMX_PANDNirm, 0 },
1144 { X86::MMX_PANDirr, X86::MMX_PANDirm, 0 },
1145 { X86::MMX_PAVGBirr, X86::MMX_PAVGBirm, 0 },
1146 { X86::MMX_PAVGWirr, X86::MMX_PAVGWirm, 0 },
1147 { X86::MMX_PCMPEQBirr, X86::MMX_PCMPEQBirm, 0 },
1148 { X86::MMX_PCMPEQDirr, X86::MMX_PCMPEQDirm, 0 },
1149 { X86::MMX_PCMPEQWirr, X86::MMX_PCMPEQWirm, 0 },
1150 { X86::MMX_PCMPGTBirr, X86::MMX_PCMPGTBirm, 0 },
1151 { X86::MMX_PCMPGTDirr, X86::MMX_PCMPGTDirm, 0 },
1152 { X86::MMX_PCMPGTWirr, X86::MMX_PCMPGTWirm, 0 },
1153 { X86::MMX_PHADDSWrr64, X86::MMX_PHADDSWrm64, 0 },
1154 { X86::MMX_PHADDWrr64, X86::MMX_PHADDWrm64, 0 },
1155 { X86::MMX_PHADDrr64, X86::MMX_PHADDrm64, 0 },
1156 { X86::MMX_PHSUBDrr64, X86::MMX_PHSUBDrm64, 0 },
1157 { X86::MMX_PHSUBSWrr64, X86::MMX_PHSUBSWrm64, 0 },
1158 { X86::MMX_PHSUBWrr64, X86::MMX_PHSUBWrm64, 0 },
1159 { X86::MMX_PINSRWirri, X86::MMX_PINSRWirmi, 0 },
1160 { X86::MMX_PMADDUBSWrr64, X86::MMX_PMADDUBSWrm64, 0 },
1161 { X86::MMX_PMADDWDirr, X86::MMX_PMADDWDirm, 0 },
1162 { X86::MMX_PMAXSWirr, X86::MMX_PMAXSWirm, 0 },
1163 { X86::MMX_PMAXUBirr, X86::MMX_PMAXUBirm, 0 },
1164 { X86::MMX_PMINSWirr, X86::MMX_PMINSWirm, 0 },
1165 { X86::MMX_PMINUBirr, X86::MMX_PMINUBirm, 0 },
1166 { X86::MMX_PMULHRSWrr64, X86::MMX_PMULHRSWrm64, 0 },
1167 { X86::MMX_PMULHUWirr, X86::MMX_PMULHUWirm, 0 },
1168 { X86::MMX_PMULHWirr, X86::MMX_PMULHWirm, 0 },
1169 { X86::MMX_PMULLWirr, X86::MMX_PMULLWirm, 0 },
1170 { X86::MMX_PMULUDQirr, X86::MMX_PMULUDQirm, 0 },
1171 { X86::MMX_PORirr, X86::MMX_PORirm, 0 },
1172 { X86::MMX_PSADBWirr, X86::MMX_PSADBWirm, 0 },
1173 { X86::MMX_PSHUFBrr64, X86::MMX_PSHUFBrm64, 0 },
1174 { X86::MMX_PSIGNBrr64, X86::MMX_PSIGNBrm64, 0 },
1175 { X86::MMX_PSIGNDrr64, X86::MMX_PSIGNDrm64, 0 },
1176 { X86::MMX_PSIGNWrr64, X86::MMX_PSIGNWrm64, 0 },
1177 { X86::MMX_PSLLDrr, X86::MMX_PSLLDrm, 0 },
1178 { X86::MMX_PSLLQrr, X86::MMX_PSLLQrm, 0 },
1179 { X86::MMX_PSLLWrr, X86::MMX_PSLLWrm, 0 },
1180 { X86::MMX_PSRADrr, X86::MMX_PSRADrm, 0 },
1181 { X86::MMX_PSRAWrr, X86::MMX_PSRAWrm, 0 },
1182 { X86::MMX_PSRLDrr, X86::MMX_PSRLDrm, 0 },
1183 { X86::MMX_PSRLQrr, X86::MMX_PSRLQrm, 0 },
1184 { X86::MMX_PSRLWrr, X86::MMX_PSRLWrm, 0 },
1185 { X86::MMX_PSUBBirr, X86::MMX_PSUBBirm, 0 },
1186 { X86::MMX_PSUBDirr, X86::MMX_PSUBDirm, 0 },
1187 { X86::MMX_PSUBQirr, X86::MMX_PSUBQirm, 0 },
1188 { X86::MMX_PSUBSBirr, X86::MMX_PSUBSBirm, 0 },
1189 { X86::MMX_PSUBSWirr, X86::MMX_PSUBSWirm, 0 },
1190 { X86::MMX_PSUBUSBirr, X86::MMX_PSUBUSBirm, 0 },
1191 { X86::MMX_PSUBUSWirr, X86::MMX_PSUBUSWirm, 0 },
1192 { X86::MMX_PSUBWirr, X86::MMX_PSUBWirm, 0 },
1193 { X86::MMX_PUNPCKHBWirr, X86::MMX_PUNPCKHBWirm, 0 },
1194 { X86::MMX_PUNPCKHDQirr, X86::MMX_PUNPCKHDQirm, 0 },
1195 { X86::MMX_PUNPCKHWDirr, X86::MMX_PUNPCKHWDirm, 0 },
1196 { X86::MMX_PUNPCKLBWirr, X86::MMX_PUNPCKLBWirm, 0 },
1197 { X86::MMX_PUNPCKLDQirr, X86::MMX_PUNPCKLDQirm, 0 },
1198 { X86::MMX_PUNPCKLWDirr, X86::MMX_PUNPCKLWDirm, 0 },
1199 { X86::MMX_PXORirr, X86::MMX_PXORirm, 0 },
1202 { X86::PAVGUSBrr, X86::PAVGUSBrm, 0 },
1203 { X86::PFACCrr, X86::PFACCrm, 0 },
1204 { X86::PFADDrr, X86::PFADDrm, 0 },
1205 { X86::PFCMPEQrr, X86::PFCMPEQrm, 0 },
1206 { X86::PFCMPGErr, X86::PFCMPGErm, 0 },
1207 { X86::PFCMPGTrr, X86::PFCMPGTrm, 0 },
1208 { X86::PFMAXrr, X86::PFMAXrm, 0 },
1209 { X86::PFMINrr, X86::PFMINrm, 0 },
1210 { X86::PFMULrr, X86::PFMULrm, 0 },
1211 { X86::PFNACCrr, X86::PFNACCrm, 0 },
1212 { X86::PFPNACCrr, X86::PFPNACCrm, 0 },
1213 { X86::PFRCPIT1rr, X86::PFRCPIT1rm, 0 },
1214 { X86::PFRCPIT2rr, X86::PFRCPIT2rm, 0 },
1215 { X86::PFRSQIT1rr, X86::PFRSQIT1rm, 0 },
1216 { X86::PFSUBrr, X86::PFSUBrm, 0 },
1217 { X86::PFSUBRrr, X86::PFSUBRrm, 0 },
1218 { X86::PMULHRWrr, X86::PMULHRWrm, 0 },
1221 { X86::VCVTSD2SSrr, X86::VCVTSD2SSrm, 0 },
1222 { X86::Int_VCVTSD2SSrr, X86::Int_VCVTSD2SSrm, 0 },
1223 { X86::VCVTSI2SD64rr, X86::VCVTSI2SD64rm, 0 },
1224 { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm, 0 },
1225 { X86::VCVTSI2SDrr, X86::VCVTSI2SDrm, 0 },
1226 { X86::Int_VCVTSI2SDrr, X86::Int_VCVTSI2SDrm, 0 },
1227 { X86::VCVTSI2SS64rr, X86::VCVTSI2SS64rm, 0 },
1228 { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm, 0 },
1229 { X86::VCVTSI2SSrr, X86::VCVTSI2SSrm, 0 },
1230 { X86::Int_VCVTSI2SSrr, X86::Int_VCVTSI2SSrm, 0 },
1231 { X86::VCVTSS2SDrr, X86::VCVTSS2SDrm, 0 },
1232 { X86::Int_VCVTSS2SDrr, X86::Int_VCVTSS2SDrm, 0 },
1233 { X86::VRCPSSr, X86::VRCPSSm, 0 },
1234 { X86::VRCPSSr_Int, X86::VRCPSSm_Int, 0 },
1235 { X86::VRSQRTSSr, X86::VRSQRTSSm, 0 },
1236 { X86::VRSQRTSSr_Int, X86::VRSQRTSSm_Int, 0 },
1237 { X86::VSQRTSDr, X86::VSQRTSDm, 0 },
1238 { X86::VSQRTSDr_Int, X86::VSQRTSDm_Int, 0 },
1239 { X86::VSQRTSSr, X86::VSQRTSSm, 0 },
1240 { X86::VSQRTSSr_Int, X86::VSQRTSSm_Int, 0 },
1241 { X86::VADDPDrr, X86::VADDPDrm, 0 },
1242 { X86::VADDPSrr, X86::VADDPSrm, 0 },
1243 { X86::VADDSDrr, X86::VADDSDrm, 0 },
1244 { X86::VADDSDrr_Int, X86::VADDSDrm_Int, 0 },
1245 { X86::VADDSSrr, X86::VADDSSrm, 0 },
1246 { X86::VADDSSrr_Int, X86::VADDSSrm_Int, 0 },
1247 { X86::VADDSUBPDrr, X86::VADDSUBPDrm, 0 },
1248 { X86::VADDSUBPSrr, X86::VADDSUBPSrm, 0 },
1249 { X86::VANDNPDrr, X86::VANDNPDrm, 0 },
1250 { X86::VANDNPSrr, X86::VANDNPSrm, 0 },
1251 { X86::VANDPDrr, X86::VANDPDrm, 0 },
1252 { X86::VANDPSrr, X86::VANDPSrm, 0 },
1253 { X86::VBLENDPDrri, X86::VBLENDPDrmi, 0 },
1254 { X86::VBLENDPSrri, X86::VBLENDPSrmi, 0 },
1255 { X86::VBLENDVPDrr, X86::VBLENDVPDrm, 0 },
1256 { X86::VBLENDVPSrr, X86::VBLENDVPSrm, 0 },
1257 { X86::VCMPPDrri, X86::VCMPPDrmi, 0 },
1258 { X86::VCMPPSrri, X86::VCMPPSrmi, 0 },
1259 { X86::VCMPSDrr, X86::VCMPSDrm, 0 },
1260 { X86::VCMPSSrr, X86::VCMPSSrm, 0 },
1261 { X86::VDIVPDrr, X86::VDIVPDrm, 0 },
1262 { X86::VDIVPSrr, X86::VDIVPSrm, 0 },
1263 { X86::VDIVSDrr, X86::VDIVSDrm, 0 },
1264 { X86::VDIVSDrr_Int, X86::VDIVSDrm_Int, 0 },
1265 { X86::VDIVSSrr, X86::VDIVSSrm, 0 },
1266 { X86::VDIVSSrr_Int, X86::VDIVSSrm_Int, 0 },
1267 { X86::VDPPDrri, X86::VDPPDrmi, 0 },
1268 { X86::VDPPSrri, X86::VDPPSrmi, 0 },
1272 { X86::VFvANDNPDrr, X86::VFvANDNPDrm, 0 },
1273 { X86::VFvANDNPSrr, X86::VFvANDNPSrm, 0 },
1274 { X86::VFvANDPDrr, X86::VFvANDPDrm, 0 },
1275 { X86::VFvANDPSrr, X86::VFvANDPSrm, 0 },
1276 { X86::VFvORPDrr, X86::VFvORPDrm, 0 },
1277 { X86::VFvORPSrr, X86::VFvORPSrm, 0 },
1278 { X86::VFvXORPDrr, X86::VFvXORPDrm, 0 },
1279 { X86::VFvXORPSrr, X86::VFvXORPSrm, 0 },
1280 { X86::VHADDPDrr, X86::VHADDPDrm, 0 },
1281 { X86::VHADDPSrr, X86::VHADDPSrm, 0 },
1282 { X86::VHSUBPDrr, X86::VHSUBPDrm, 0 },
1283 { X86::VHSUBPSrr, X86::VHSUBPSrm, 0 },
1284 { X86::Int_VCMPSDrr, X86::Int_VCMPSDrm, 0 },
1285 { X86::Int_VCMPSSrr, X86::Int_VCMPSSrm, 0 },
1286 { X86::VMAXPDrr, X86::VMAXPDrm, 0 },
1287 { X86::VMAXPSrr, X86::VMAXPSrm, 0 },
1288 { X86::VMAXSDrr, X86::VMAXSDrm, 0 },
1289 { X86::VMAXSDrr_Int, X86::VMAXSDrm_Int, 0 },
1290 { X86::VMAXSSrr, X86::VMAXSSrm, 0 },
1291 { X86::VMAXSSrr_Int, X86::VMAXSSrm_Int, 0 },
1292 { X86::VMINPDrr, X86::VMINPDrm, 0 },
1293 { X86::VMINPSrr, X86::VMINPSrm, 0 },
1294 { X86::VMINSDrr, X86::VMINSDrm, 0 },
1295 { X86::VMINSDrr_Int, X86::VMINSDrm_Int, 0 },
1296 { X86::VMINSSrr, X86::VMINSSrm, 0 },
1297 { X86::VMINSSrr_Int, X86::VMINSSrm_Int, 0 },
1298 { X86::VMPSADBWrri, X86::VMPSADBWrmi, 0 },
1299 { X86::VMULPDrr, X86::VMULPDrm, 0 },
1300 { X86::VMULPSrr, X86::VMULPSrm, 0 },
1301 { X86::VMULSDrr, X86::VMULSDrm, 0 },
1302 { X86::VMULSDrr_Int, X86::VMULSDrm_Int, 0 },
1303 { X86::VMULSSrr, X86::VMULSSrm, 0 },
1304 { X86::VMULSSrr_Int, X86::VMULSSrm_Int, 0 },
1305 { X86::VORPDrr, X86::VORPDrm, 0 },
1306 { X86::VORPSrr, X86::VORPSrm, 0 },
1307 { X86::VPACKSSDWrr, X86::VPACKSSDWrm, 0 },
1308 { X86::VPACKSSWBrr, X86::VPACKSSWBrm, 0 },
1309 { X86::VPACKUSDWrr, X86::VPACKUSDWrm, 0 },
1310 { X86::VPACKUSWBrr, X86::VPACKUSWBrm, 0 },
1311 { X86::VPADDBrr, X86::VPADDBrm, 0 },
1312 { X86::VPADDDrr, X86::VPADDDrm, 0 },
1313 { X86::VPADDQrr, X86::VPADDQrm, 0 },
1314 { X86::VPADDSBrr, X86::VPADDSBrm, 0 },
1315 { X86::VPADDSWrr, X86::VPADDSWrm, 0 },
1316 { X86::VPADDUSBrr, X86::VPADDUSBrm, 0 },
1317 { X86::VPADDUSWrr, X86::VPADDUSWrm, 0 },
1318 { X86::VPADDWrr, X86::VPADDWrm, 0 },
1319 { X86::VPALIGNR128rr, X86::VPALIGNR128rm, 0 },
1320 { X86::VPANDNrr, X86::VPANDNrm, 0 },
1321 { X86::VPANDrr, X86::VPANDrm, 0 },
1322 { X86::VPAVGBrr, X86::VPAVGBrm, 0 },
1323 { X86::VPAVGWrr, X86::VPAVGWrm, 0 },
1324 { X86::VPBLENDVBrr, X86::VPBLENDVBrm, 0 },
1325 { X86::VPBLENDWrri, X86::VPBLENDWrmi, 0 },
1326 { X86::VPCLMULQDQrr, X86::VPCLMULQDQrm, 0 },
1327 { X86::VPCMPEQBrr, X86::VPCMPEQBrm, 0 },
1328 { X86::VPCMPEQDrr, X86::VPCMPEQDrm, 0 },
1329 { X86::VPCMPEQQrr, X86::VPCMPEQQrm, 0 },
1330 { X86::VPCMPEQWrr, X86::VPCMPEQWrm, 0 },
1331 { X86::VPCMPGTBrr, X86::VPCMPGTBrm, 0 },
1332 { X86::VPCMPGTDrr, X86::VPCMPGTDrm, 0 },
1333 { X86::VPCMPGTQrr, X86::VPCMPGTQrm, 0 },
1334 { X86::VPCMPGTWrr, X86::VPCMPGTWrm, 0 },
1335 { X86::VPHADDDrr, X86::VPHADDDrm, 0 },
1336 { X86::VPHADDSWrr128, X86::VPHADDSWrm128, 0 },
1337 { X86::VPHADDWrr, X86::VPHADDWrm, 0 },
1338 { X86::VPHSUBDrr, X86::VPHSUBDrm, 0 },
1339 { X86::VPHSUBSWrr128, X86::VPHSUBSWrm128, 0 },
1340 { X86::VPHSUBWrr, X86::VPHSUBWrm, 0 },
1341 { X86::VPERMILPDrr, X86::VPERMILPDrm, 0 },
1342 { X86::VPERMILPSrr, X86::VPERMILPSrm, 0 },
1343 { X86::VPINSRBrr, X86::VPINSRBrm, 0 },
1344 { X86::VPINSRDrr, X86::VPINSRDrm, 0 },
1345 { X86::VPINSRQrr, X86::VPINSRQrm, 0 },
1346 { X86::VPINSRWrri, X86::VPINSRWrmi, 0 },
1347 { X86::VPMADDUBSWrr128, X86::VPMADDUBSWrm128, 0 },
1348 { X86::VPMADDWDrr, X86::VPMADDWDrm, 0 },
1349 { X86::VPMAXSWrr, X86::VPMAXSWrm, 0 },
1350 { X86::VPMAXUBrr, X86::VPMAXUBrm, 0 },
1351 { X86::VPMINSWrr, X86::VPMINSWrm, 0 },
1352 { X86::VPMINUBrr, X86::VPMINUBrm, 0 },
1353 { X86::VPMINSBrr, X86::VPMINSBrm, 0 },
1354 { X86::VPMINSDrr, X86::VPMINSDrm, 0 },
1355 { X86::VPMINUDrr, X86::VPMINUDrm, 0 },
1356 { X86::VPMINUWrr, X86::VPMINUWrm, 0 },
1357 { X86::VPMAXSBrr, X86::VPMAXSBrm, 0 },
1358 { X86::VPMAXSDrr, X86::VPMAXSDrm, 0 },
1359 { X86::VPMAXUDrr, X86::VPMAXUDrm, 0 },
1360 { X86::VPMAXUWrr, X86::VPMAXUWrm, 0 },
1361 { X86::VPMULDQrr, X86::VPMULDQrm, 0 },
1362 { X86::VPMULHRSWrr128, X86::VPMULHRSWrm128, 0 },
1363 { X86::VPMULHUWrr, X86::VPMULHUWrm, 0 },
1364 { X86::VPMULHWrr, X86::VPMULHWrm, 0 },
1365 { X86::VPMULLDrr, X86::VPMULLDrm, 0 },
1366 { X86::VPMULLWrr, X86::VPMULLWrm, 0 },
1367 { X86::VPMULUDQrr, X86::VPMULUDQrm, 0 },
1368 { X86::VPORrr, X86::VPORrm, 0 },
1369 { X86::VPSADBWrr, X86::VPSADBWrm, 0 },
1370 { X86::VPSHUFBrr, X86::VPSHUFBrm, 0 },
1371 { X86::VPSIGNBrr, X86::VPSIGNBrm, 0 },
1372 { X86::VPSIGNWrr, X86::VPSIGNWrm, 0 },
1373 { X86::VPSIGNDrr, X86::VPSIGNDrm, 0 },
1374 { X86::VPSLLDrr, X86::VPSLLDrm, 0 },
1375 { X86::VPSLLQrr, X86::VPSLLQrm, 0 },
1376 { X86::VPSLLWrr, X86::VPSLLWrm, 0 },
1377 { X86::VPSRADrr, X86::VPSRADrm, 0 },
1378 { X86::VPSRAWrr, X86::VPSRAWrm, 0 },
1379 { X86::VPSRLDrr, X86::VPSRLDrm, 0 },
1380 { X86::VPSRLQrr, X86::VPSRLQrm, 0 },
1381 { X86::VPSRLWrr, X86::VPSRLWrm, 0 },
1382 { X86::VPSUBBrr, X86::VPSUBBrm, 0 },
1383 { X86::VPSUBDrr, X86::VPSUBDrm, 0 },
1384 { X86::VPSUBQrr, X86::VPSUBQrm, 0 },
1385 { X86::VPSUBSBrr, X86::VPSUBSBrm, 0 },
1386 { X86::VPSUBSWrr, X86::VPSUBSWrm, 0 },
1387 { X86::VPSUBUSBrr, X86::VPSUBUSBrm, 0 },
1388 { X86::VPSUBUSWrr, X86::VPSUBUSWrm, 0 },
1389 { X86::VPSUBWrr, X86::VPSUBWrm, 0 },
1390 { X86::VPUNPCKHBWrr, X86::VPUNPCKHBWrm, 0 },
1391 { X86::VPUNPCKHDQrr, X86::VPUNPCKHDQrm, 0 },
1392 { X86::VPUNPCKHQDQrr, X86::VPUNPCKHQDQrm, 0 },
1393 { X86::VPUNPCKHWDrr, X86::VPUNPCKHWDrm, 0 },
1394 { X86::VPUNPCKLBWrr, X86::VPUNPCKLBWrm, 0 },
1395 { X86::VPUNPCKLDQrr, X86::VPUNPCKLDQrm, 0 },
1396 { X86::VPUNPCKLQDQrr, X86::VPUNPCKLQDQrm, 0 },
1397 { X86::VPUNPCKLWDrr, X86::VPUNPCKLWDrm, 0 },
1398 { X86::VPXORrr, X86::VPXORrm, 0 },
1399 { X86::VROUNDSDr, X86::VROUNDSDm, 0 },
1400 { X86::VROUNDSSr, X86::VROUNDSSm, 0 },
1401 { X86::VSHUFPDrri, X86::VSHUFPDrmi, 0 },
1402 { X86::VSHUFPSrri, X86::VSHUFPSrmi, 0 },
1403 { X86::VSUBPDrr, X86::VSUBPDrm, 0 },
1404 { X86::VSUBPSrr, X86::VSUBPSrm, 0 },
1405 { X86::VSUBSDrr, X86::VSUBSDrm, 0 },
1406 { X86::VSUBSDrr_Int, X86::VSUBSDrm_Int, 0 },
1407 { X86::VSUBSSrr, X86::VSUBSSrm, 0 },
1408 { X86::VSUBSSrr_Int, X86::VSUBSSrm_Int, 0 },
1409 { X86::VUNPCKHPDrr, X86::VUNPCKHPDrm, 0 },
1410 { X86::VUNPCKHPSrr, X86::VUNPCKHPSrm, 0 },
1411 { X86::VUNPCKLPDrr, X86::VUNPCKLPDrm, 0 },
1412 { X86::VUNPCKLPSrr, X86::VUNPCKLPSrm, 0 },
1413 { X86::VXORPDrr, X86::VXORPDrm, 0 },
1414 { X86::VXORPSrr, X86::VXORPSrm, 0 },
1417 { X86::VADDPDYrr, X86::VADDPDYrm, 0 },
1418 { X86::VADDPSYrr, X86::VADDPSYrm, 0 },
1419 { X86::VADDSUBPDYrr, X86::VADDSUBPDYrm, 0 },
1420 { X86::VADDSUBPSYrr, X86::VADDSUBPSYrm, 0 },
1421 { X86::VANDNPDYrr, X86::VANDNPDYrm, 0 },
1422 { X86::VANDNPSYrr, X86::VANDNPSYrm, 0 },
1423 { X86::VANDPDYrr, X86::VANDPDYrm, 0 },
1424 { X86::VANDPSYrr, X86::VANDPSYrm, 0 },
1425 { X86::VBLENDPDYrri, X86::VBLENDPDYrmi, 0 },
1426 { X86::VBLENDPSYrri, X86::VBLENDPSYrmi, 0 },
1427 { X86::VBLENDVPDYrr, X86::VBLENDVPDYrm, 0 },
1428 { X86::VBLENDVPSYrr, X86::VBLENDVPSYrm, 0 },
1429 { X86::VCMPPDYrri, X86::VCMPPDYrmi, 0 },
1430 { X86::VCMPPSYrri, X86::VCMPPSYrmi, 0 },
1431 { X86::VDIVPDYrr, X86::VDIVPDYrm, 0 },
1432 { X86::VDIVPSYrr, X86::VDIVPSYrm, 0 },
1433 { X86::VDPPSYrri, X86::VDPPSYrmi, 0 },
1434 { X86::VHADDPDYrr, X86::VHADDPDYrm, 0 },
1435 { X86::VHADDPSYrr, X86::VHADDPSYrm, 0 },
1436 { X86::VHSUBPDYrr, X86::VHSUBPDYrm, 0 },
1437 { X86::VHSUBPSYrr, X86::VHSUBPSYrm, 0 },
1438 { X86::VINSERTF128rr, X86::VINSERTF128rm, 0 },
1439 { X86::VMAXPDYrr, X86::VMAXPDYrm, 0 },
1440 { X86::VMAXPSYrr, X86::VMAXPSYrm, 0 },
1441 { X86::VMINPDYrr, X86::VMINPDYrm, 0 },
1442 { X86::VMINPSYrr, X86::VMINPSYrm, 0 },
1443 { X86::VMULPDYrr, X86::VMULPDYrm, 0 },
1444 { X86::VMULPSYrr, X86::VMULPSYrm, 0 },
1445 { X86::VORPDYrr, X86::VORPDYrm, 0 },
1446 { X86::VORPSYrr, X86::VORPSYrm, 0 },
1447 { X86::VPERM2F128rr, X86::VPERM2F128rm, 0 },
1448 { X86::VPERMILPDYrr, X86::VPERMILPDYrm, 0 },
1449 { X86::VPERMILPSYrr, X86::VPERMILPSYrm, 0 },
1450 { X86::VSHUFPDYrri, X86::VSHUFPDYrmi, 0 },
1451 { X86::VSHUFPSYrri, X86::VSHUFPSYrmi, 0 },
1452 { X86::VSUBPDYrr, X86::VSUBPDYrm, 0 },
1453 { X86::VSUBPSYrr, X86::VSUBPSYrm, 0 },
1454 { X86::VUNPCKHPDYrr, X86::VUNPCKHPDYrm, 0 },
1455 { X86::VUNPCKHPSYrr, X86::VUNPCKHPSYrm, 0 },
1456 { X86::VUNPCKLPDYrr, X86::VUNPCKLPDYrm, 0 },
1457 { X86::VUNPCKLPSYrr, X86::VUNPCKLPSYrm, 0 },
1458 { X86::VXORPDYrr, X86::VXORPDYrm, 0 },
1459 { X86::VXORPSYrr, X86::VXORPSYrm, 0 },
1462 { X86::VINSERTI128rr, X86::VINSERTI128rm, 0 },
1463 { X86::VPACKSSDWYrr, X86::VPACKSSDWYrm, 0 },
1464 { X86::VPACKSSWBYrr, X86::VPACKSSWBYrm, 0 },
1465 { X86::VPACKUSDWYrr, X86::VPACKUSDWYrm, 0 },
1466 { X86::VPACKUSWBYrr, X86::VPACKUSWBYrm, 0 },
1467 { X86::VPADDBYrr, X86::VPADDBYrm, 0 },
1468 { X86::VPADDDYrr, X86::VPADDDYrm, 0 },
1469 { X86::VPADDQYrr, X86::VPADDQYrm, 0 },
1470 { X86::VPADDSBYrr, X86::VPADDSBYrm, 0 },
1471 { X86::VPADDSWYrr, X86::VPADDSWYrm, 0 },
1472 { X86::VPADDUSBYrr, X86::VPADDUSBYrm, 0 },
1473 { X86::VPADDUSWYrr, X86::VPADDUSWYrm, 0 },
1474 { X86::VPADDWYrr, X86::VPADDWYrm, 0 },
1475 { X86::VPALIGNR256rr, X86::VPALIGNR256rm, 0 },
1476 { X86::VPANDNYrr, X86::VPANDNYrm, 0 },
1477 { X86::VPANDYrr, X86::VPANDYrm, 0 },
1478 { X86::VPAVGBYrr, X86::VPAVGBYrm, 0 },
1479 { X86::VPAVGWYrr, X86::VPAVGWYrm, 0 },
1480 { X86::VPBLENDDrri, X86::VPBLENDDrmi, 0 },
1481 { X86::VPBLENDDYrri, X86::VPBLENDDYrmi, 0 },
1482 { X86::VPBLENDVBYrr, X86::VPBLENDVBYrm, 0 },
1483 { X86::VPBLENDWYrri, X86::VPBLENDWYrmi, 0 },
1484 { X86::VPCMPEQBYrr, X86::VPCMPEQBYrm, 0 },
1485 { X86::VPCMPEQDYrr, X86::VPCMPEQDYrm, 0 },
1486 { X86::VPCMPEQQYrr, X86::VPCMPEQQYrm, 0 },
1487 { X86::VPCMPEQWYrr, X86::VPCMPEQWYrm, 0 },
1488 { X86::VPCMPGTBYrr, X86::VPCMPGTBYrm, 0 },
1489 { X86::VPCMPGTDYrr, X86::VPCMPGTDYrm, 0 },
1490 { X86::VPCMPGTQYrr, X86::VPCMPGTQYrm, 0 },
1491 { X86::VPCMPGTWYrr, X86::VPCMPGTWYrm, 0 },
1492 { X86::VPERM2I128rr, X86::VPERM2I128rm, 0 },
1493 { X86::VPERMDYrr, X86::VPERMDYrm, 0 },
1494 { X86::VPERMPSYrr, X86::VPERMPSYrm, 0 },
1495 { X86::VPHADDDYrr, X86::VPHADDDYrm, 0 },
1496 { X86::VPHADDSWrr256, X86::VPHADDSWrm256, 0 },
1497 { X86::VPHADDWYrr, X86::VPHADDWYrm, 0 },
1498 { X86::VPHSUBDYrr, X86::VPHSUBDYrm, 0 },
1499 { X86::VPHSUBSWrr256, X86::VPHSUBSWrm256, 0 },
1500 { X86::VPHSUBWYrr, X86::VPHSUBWYrm, 0 },
1501 { X86::VPMADDUBSWrr256, X86::VPMADDUBSWrm256, 0 },
1502 { X86::VPMADDWDYrr, X86::VPMADDWDYrm, 0 },
1503 { X86::VPMAXSWYrr, X86::VPMAXSWYrm, 0 },
1504 { X86::VPMAXUBYrr, X86::VPMAXUBYrm, 0 },
1505 { X86::VPMINSWYrr, X86::VPMINSWYrm, 0 },
1506 { X86::VPMINUBYrr, X86::VPMINUBYrm, 0 },
1507 { X86::VPMINSBYrr, X86::VPMINSBYrm, 0 },
1508 { X86::VPMINSDYrr, X86::VPMINSDYrm, 0 },
1509 { X86::VPMINUDYrr, X86::VPMINUDYrm, 0 },
1510 { X86::VPMINUWYrr, X86::VPMINUWYrm, 0 },
1511 { X86::VPMAXSBYrr, X86::VPMAXSBYrm, 0 },
1512 { X86::VPMAXSDYrr, X86::VPMAXSDYrm, 0 },
1513 { X86::VPMAXUDYrr, X86::VPMAXUDYrm, 0 },
1514 { X86::VPMAXUWYrr, X86::VPMAXUWYrm, 0 },
1515 { X86::VMPSADBWYrri, X86::VMPSADBWYrmi, 0 },
1516 { X86::VPMULDQYrr, X86::VPMULDQYrm, 0 },
1517 { X86::VPMULHRSWrr256, X86::VPMULHRSWrm256, 0 },
1518 { X86::VPMULHUWYrr, X86::VPMULHUWYrm, 0 },
1519 { X86::VPMULHWYrr, X86::VPMULHWYrm, 0 },
1520 { X86::VPMULLDYrr, X86::VPMULLDYrm, 0 },
1521 { X86::VPMULLWYrr, X86::VPMULLWYrm, 0 },
1522 { X86::VPMULUDQYrr, X86::VPMULUDQYrm, 0 },
1523 { X86::VPORYrr, X86::VPORYrm, 0 },
1524 { X86::VPSADBWYrr, X86::VPSADBWYrm, 0 },
1525 { X86::VPSHUFBYrr, X86::VPSHUFBYrm, 0 },
1526 { X86::VPSIGNBYrr, X86::VPSIGNBYrm, 0 },
1527 { X86::VPSIGNWYrr, X86::VPSIGNWYrm, 0 },
1528 { X86::VPSIGNDYrr, X86::VPSIGNDYrm, 0 },
1529 { X86::VPSLLDYrr, X86::VPSLLDYrm, 0 },
1530 { X86::VPSLLQYrr, X86::VPSLLQYrm, 0 },
1531 { X86::VPSLLWYrr, X86::VPSLLWYrm, 0 },
1532 { X86::VPSLLVDrr, X86::VPSLLVDrm, 0 },
1533 { X86::VPSLLVDYrr, X86::VPSLLVDYrm, 0 },
1534 { X86::VPSLLVQrr, X86::VPSLLVQrm, 0 },
1535 { X86::VPSLLVQYrr, X86::VPSLLVQYrm, 0 },
1536 { X86::VPSRADYrr, X86::VPSRADYrm, 0 },
1537 { X86::VPSRAWYrr, X86::VPSRAWYrm, 0 },
1538 { X86::VPSRAVDrr, X86::VPSRAVDrm, 0 },
1539 { X86::VPSRAVDYrr, X86::VPSRAVDYrm, 0 },
1540 { X86::VPSRLDYrr, X86::VPSRLDYrm, 0 },
1541 { X86::VPSRLQYrr, X86::VPSRLQYrm, 0 },
1542 { X86::VPSRLWYrr, X86::VPSRLWYrm, 0 },
1543 { X86::VPSRLVDrr, X86::VPSRLVDrm, 0 },
1544 { X86::VPSRLVDYrr, X86::VPSRLVDYrm, 0 },
1545 { X86::VPSRLVQrr, X86::VPSRLVQrm, 0 },
1546 { X86::VPSRLVQYrr, X86::VPSRLVQYrm, 0 },
1547 { X86::VPSUBBYrr, X86::VPSUBBYrm, 0 },
1548 { X86::VPSUBDYrr, X86::VPSUBDYrm, 0 },
1549 { X86::VPSUBQYrr, X86::VPSUBQYrm, 0 },
1550 { X86::VPSUBSBYrr, X86::VPSUBSBYrm, 0 },
1551 { X86::VPSUBSWYrr, X86::VPSUBSWYrm, 0 },
1552 { X86::VPSUBUSBYrr, X86::VPSUBUSBYrm, 0 },
1553 { X86::VPSUBUSWYrr, X86::VPSUBUSWYrm, 0 },
1554 { X86::VPSUBWYrr, X86::VPSUBWYrm, 0 },
1555 { X86::VPUNPCKHBWYrr, X86::VPUNPCKHBWYrm, 0 },
1556 { X86::VPUNPCKHDQYrr, X86::VPUNPCKHDQYrm, 0 },
1557 { X86::VPUNPCKHQDQYrr, X86::VPUNPCKHQDQYrm, 0 },
1558 { X86::VPUNPCKHWDYrr, X86::VPUNPCKHWDYrm, 0 },
1559 { X86::VPUNPCKLBWYrr, X86::VPUNPCKLBWYrm, 0 },
1560 { X86::VPUNPCKLDQYrr, X86::VPUNPCKLDQYrm, 0 },
1561 { X86::VPUNPCKLQDQYrr, X86::VPUNPCKLQDQYrm, 0 },
1562 { X86::VPUNPCKLWDYrr, X86::VPUNPCKLWDYrm, 0 },
1563 { X86::VPXORYrr, X86::VPXORYrm, 0 },
1590 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4mr,
TB_ALIGN_NONE },
1591 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4mr,
TB_ALIGN_NONE },
1592 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4mrY,
TB_ALIGN_NONE },
1593 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4mrY,
TB_ALIGN_NONE },
1594 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4mr,
TB_ALIGN_NONE },
1595 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4mr,
TB_ALIGN_NONE },
1596 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4mrY,
TB_ALIGN_NONE },
1597 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4mrY,
TB_ALIGN_NONE },
1600 { X86::VPCMOVrr, X86::VPCMOVmr, 0 },
1601 { X86::VPCMOVrrY, X86::VPCMOVmrY, 0 },
1602 { X86::VPCOMBri, X86::VPCOMBmi, 0 },
1603 { X86::VPCOMDri, X86::VPCOMDmi, 0 },
1604 { X86::VPCOMQri, X86::VPCOMQmi, 0 },
1605 { X86::VPCOMWri, X86::VPCOMWmi, 0 },
1606 { X86::VPCOMUBri, X86::VPCOMUBmi, 0 },
1607 { X86::VPCOMUDri, X86::VPCOMUDmi, 0 },
1608 { X86::VPCOMUQri, X86::VPCOMUQmi, 0 },
1609 { X86::VPCOMUWri, X86::VPCOMUWmi, 0 },
1610 { X86::VPERMIL2PDrr, X86::VPERMIL2PDmr, 0 },
1611 { X86::VPERMIL2PDrrY, X86::VPERMIL2PDmrY, 0 },
1612 { X86::VPERMIL2PSrr, X86::VPERMIL2PSmr, 0 },
1613 { X86::VPERMIL2PSrrY, X86::VPERMIL2PSmrY, 0 },
1614 { X86::VPMACSDDrr, X86::VPMACSDDrm, 0 },
1615 { X86::VPMACSDQHrr, X86::VPMACSDQHrm, 0 },
1616 { X86::VPMACSDQLrr, X86::VPMACSDQLrm, 0 },
1617 { X86::VPMACSSDDrr, X86::VPMACSSDDrm, 0 },
1618 { X86::VPMACSSDQHrr, X86::VPMACSSDQHrm, 0 },
1619 { X86::VPMACSSDQLrr, X86::VPMACSSDQLrm, 0 },
1620 { X86::VPMACSSWDrr, X86::VPMACSSWDrm, 0 },
1621 { X86::VPMACSSWWrr, X86::VPMACSSWWrm, 0 },
1622 { X86::VPMACSWDrr, X86::VPMACSWDrm, 0 },
1623 { X86::VPMACSWWrr, X86::VPMACSWWrm, 0 },
1624 { X86::VPMADCSSWDrr, X86::VPMADCSSWDrm, 0 },
1625 { X86::VPMADCSWDrr, X86::VPMADCSWDrm, 0 },
1626 { X86::VPPERMrr, X86::VPPERMmr, 0 },
1627 { X86::VPROTBrr, X86::VPROTBrm, 0 },
1628 { X86::VPROTDrr, X86::VPROTDrm, 0 },
1629 { X86::VPROTQrr, X86::VPROTQrm, 0 },
1630 { X86::VPROTWrr, X86::VPROTWrm, 0 },
1631 { X86::VPSHABrr, X86::VPSHABrm, 0 },
1632 { X86::VPSHADrr, X86::VPSHADrm, 0 },
1633 { X86::VPSHAQrr, X86::VPSHAQrm, 0 },
1634 { X86::VPSHAWrr, X86::VPSHAWrm, 0 },
1635 { X86::VPSHLBrr, X86::VPSHLBrm, 0 },
1636 { X86::VPSHLDrr, X86::VPSHLDrm, 0 },
1637 { X86::VPSHLQrr, X86::VPSHLQrm, 0 },
1638 { X86::VPSHLWrr, X86::VPSHLWrm, 0 },
1641 { X86::ANDN32rr, X86::ANDN32rm, 0 },
1642 { X86::ANDN64rr, X86::ANDN64rm, 0 },
1643 { X86::MULX32rr, X86::MULX32rm, 0 },
1644 { X86::MULX64rr, X86::MULX64rm, 0 },
1645 { X86::PDEP32rr, X86::PDEP32rm, 0 },
1646 { X86::PDEP64rr, X86::PDEP64rm, 0 },
1647 { X86::PEXT32rr, X86::PEXT32rm, 0 },
1648 { X86::PEXT64rr, X86::PEXT64rm, 0 },
1651 { X86::VADDPSZrr, X86::VADDPSZrm, 0 },
1652 { X86::VADDPDZrr, X86::VADDPDZrm, 0 },
1653 { X86::VSUBPSZrr, X86::VSUBPSZrm, 0 },
1654 { X86::VSUBPDZrr, X86::VSUBPDZrm, 0 },
1655 { X86::VMULPSZrr, X86::VMULPSZrm, 0 },
1656 { X86::VMULPDZrr, X86::VMULPDZrm, 0 },
1657 { X86::VDIVPSZrr, X86::VDIVPSZrm, 0 },
1658 { X86::VDIVPDZrr, X86::VDIVPDZrm, 0 },
1659 { X86::VMINPSZrr, X86::VMINPSZrm, 0 },
1660 { X86::VMINPDZrr, X86::VMINPDZrm, 0 },
1661 { X86::VMAXPSZrr, X86::VMAXPSZrm, 0 },
1662 { X86::VMAXPDZrr, X86::VMAXPDZrm, 0 },
1663 { X86::VPADDDZrr, X86::VPADDDZrm, 0 },
1664 { X86::VPADDQZrr, X86::VPADDQZrm, 0 },
1665 { X86::VPERMPDZri, X86::VPERMPDZmi, 0 },
1666 { X86::VPERMPSZrr, X86::VPERMPSZrm, 0 },
1667 { X86::VPMAXSDZrr, X86::VPMAXSDZrm, 0 },
1668 { X86::VPMAXSQZrr, X86::VPMAXSQZrm, 0 },
1669 { X86::VPMAXUDZrr, X86::VPMAXUDZrm, 0 },
1670 { X86::VPMAXUQZrr, X86::VPMAXUQZrm, 0 },
1671 { X86::VPMINSDZrr, X86::VPMINSDZrm, 0 },
1672 { X86::VPMINSQZrr, X86::VPMINSQZrm, 0 },
1673 { X86::VPMINUDZrr, X86::VPMINUDZrm, 0 },
1674 { X86::VPMINUQZrr, X86::VPMINUQZrm, 0 },
1675 { X86::VPMULDQZrr, X86::VPMULDQZrm, 0 },
1676 { X86::VPSLLVDZrr, X86::VPSLLVDZrm, 0 },
1677 { X86::VPSLLVQZrr, X86::VPSLLVQZrm, 0 },
1678 { X86::VPSRAVDZrr, X86::VPSRAVDZrm, 0 },
1679 { X86::VPSRLVDZrr, X86::VPSRLVDZrm, 0 },
1680 { X86::VPSRLVQZrr, X86::VPSRLVQZrm, 0 },
1681 { X86::VPSUBDZrr, X86::VPSUBDZrm, 0 },
1682 { X86::VPSUBQZrr, X86::VPSUBQZrm, 0 },
1683 { X86::VSHUFPDZrri, X86::VSHUFPDZrmi, 0 },
1684 { X86::VSHUFPSZrri, X86::VSHUFPSZrmi, 0 },
1685 { X86::VALIGNQZrri, X86::VALIGNQZrmi, 0 },
1686 { X86::VALIGNDZrri, X86::VALIGNDZrmi, 0 },
1687 { X86::VPMULUDQZrr, X86::VPMULUDQZrm, 0 },
1688 { X86::VBROADCASTSSZrkz, X86::VBROADCASTSSZmkz,
TB_NO_REVERSE },
1689 { X86::VBROADCASTSDZrkz, X86::VBROADCASTSDZmkz,
TB_NO_REVERSE },
1692 { X86::VBROADCASTSSZ256rkz, X86::VBROADCASTSSZ256mkz,
TB_NO_REVERSE },
1693 { X86::VBROADCASTSDZ256rkz, X86::VBROADCASTSDZ256mkz,
TB_NO_REVERSE },
1694 { X86::VBROADCASTSSZ128rkz, X86::VBROADCASTSSZ128mkz,
TB_NO_REVERSE },
1697 { X86::VADDPDZ128rr, X86::VADDPDZ128rm, 0 },
1698 { X86::VADDPDZ256rr, X86::VADDPDZ256rm, 0 },
1699 { X86::VADDPSZ128rr, X86::VADDPSZ128rm, 0 },
1700 { X86::VADDPSZ256rr, X86::VADDPSZ256rm, 0 },
1703 { X86::AESDECLASTrr, X86::AESDECLASTrm,
TB_ALIGN_16 },
1705 { X86::AESENCLASTrr, X86::AESENCLASTrm,
TB_ALIGN_16 },
1707 { X86::VAESDECLASTrr, X86::VAESDECLASTrm, 0 },
1708 { X86::VAESDECrr, X86::VAESDECrm, 0 },
1709 { X86::VAESENCLASTrr, X86::VAESENCLASTrm, 0 },
1710 { X86::VAESENCrr, X86::VAESENCrm, 0 },
1713 { X86::SHA1MSG1rr, X86::SHA1MSG1rm,
TB_ALIGN_16 },
1714 { X86::SHA1MSG2rr, X86::SHA1MSG2rm,
TB_ALIGN_16 },
1715 { X86::SHA1NEXTErr, X86::SHA1NEXTErm,
TB_ALIGN_16 },
1716 { X86::SHA1RNDS4rri, X86::SHA1RNDS4rmi,
TB_ALIGN_16 },
1717 { X86::SHA256MSG1rr, X86::SHA256MSG1rm,
TB_ALIGN_16 },
1718 { X86::SHA256MSG2rr, X86::SHA256MSG2rm,
TB_ALIGN_16 },
1719 { X86::SHA256RNDS2rr, X86::SHA256RNDS2rm,
TB_ALIGN_16 }
1723 AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
1724 Entry.RegOp, Entry.MemOp,
1744 { X86::VFMADDPSr231rY, X86::VFMADDPSr231mY,
TB_ALIGN_NONE },
1745 { X86::VFMADDPDr231rY, X86::VFMADDPDr231mY,
TB_ALIGN_NONE },
1746 { X86::VFMADDPSr132rY, X86::VFMADDPSr132mY,
TB_ALIGN_NONE },
1747 { X86::VFMADDPDr132rY, X86::VFMADDPDr132mY,
TB_ALIGN_NONE },
1748 { X86::VFMADDPSr213rY, X86::VFMADDPSr213mY,
TB_ALIGN_NONE },
1749 { X86::VFMADDPDr213rY, X86::VFMADDPDr213mY,
TB_ALIGN_NONE },
1751 { X86::VFNMADDSSr231r, X86::VFNMADDSSr231m,
TB_ALIGN_NONE },
1752 { X86::VFNMADDSDr231r, X86::VFNMADDSDr231m,
TB_ALIGN_NONE },
1753 { X86::VFNMADDSSr132r, X86::VFNMADDSSr132m,
TB_ALIGN_NONE },
1754 { X86::VFNMADDSDr132r, X86::VFNMADDSDr132m,
TB_ALIGN_NONE },
1755 { X86::VFNMADDSSr213r, X86::VFNMADDSSr213m,
TB_ALIGN_NONE },
1756 { X86::VFNMADDSDr213r, X86::VFNMADDSDr213m,
TB_ALIGN_NONE },
1758 { X86::VFNMADDPSr231r, X86::VFNMADDPSr231m,
TB_ALIGN_NONE },
1759 { X86::VFNMADDPDr231r, X86::VFNMADDPDr231m,
TB_ALIGN_NONE },
1760 { X86::VFNMADDPSr132r, X86::VFNMADDPSr132m,
TB_ALIGN_NONE },
1761 { X86::VFNMADDPDr132r, X86::VFNMADDPDr132m,
TB_ALIGN_NONE },
1762 { X86::VFNMADDPSr213r, X86::VFNMADDPSr213m,
TB_ALIGN_NONE },
1763 { X86::VFNMADDPDr213r, X86::VFNMADDPDr213m,
TB_ALIGN_NONE },
1764 { X86::VFNMADDPSr231rY, X86::VFNMADDPSr231mY,
TB_ALIGN_NONE },
1765 { X86::VFNMADDPDr231rY, X86::VFNMADDPDr231mY,
TB_ALIGN_NONE },
1766 { X86::VFNMADDPSr132rY, X86::VFNMADDPSr132mY,
TB_ALIGN_NONE },
1767 { X86::VFNMADDPDr132rY, X86::VFNMADDPDr132mY,
TB_ALIGN_NONE },
1768 { X86::VFNMADDPSr213rY, X86::VFNMADDPSr213mY,
TB_ALIGN_NONE },
1769 { X86::VFNMADDPDr213rY, X86::VFNMADDPDr213mY,
TB_ALIGN_NONE },
1784 { X86::VFMSUBPSr231rY, X86::VFMSUBPSr231mY,
TB_ALIGN_NONE },
1785 { X86::VFMSUBPDr231rY, X86::VFMSUBPDr231mY,
TB_ALIGN_NONE },
1786 { X86::VFMSUBPSr132rY, X86::VFMSUBPSr132mY,
TB_ALIGN_NONE },
1787 { X86::VFMSUBPDr132rY, X86::VFMSUBPDr132mY,
TB_ALIGN_NONE },
1788 { X86::VFMSUBPSr213rY, X86::VFMSUBPSr213mY,
TB_ALIGN_NONE },
1789 { X86::VFMSUBPDr213rY, X86::VFMSUBPDr213mY,
TB_ALIGN_NONE },
1791 { X86::VFNMSUBSSr231r, X86::VFNMSUBSSr231m,
TB_ALIGN_NONE },
1792 { X86::VFNMSUBSDr231r, X86::VFNMSUBSDr231m,
TB_ALIGN_NONE },
1793 { X86::VFNMSUBSSr132r, X86::VFNMSUBSSr132m,
TB_ALIGN_NONE },
1794 { X86::VFNMSUBSDr132r, X86::VFNMSUBSDr132m,
TB_ALIGN_NONE },
1795 { X86::VFNMSUBSSr213r, X86::VFNMSUBSSr213m,
TB_ALIGN_NONE },
1796 { X86::VFNMSUBSDr213r, X86::VFNMSUBSDr213m,
TB_ALIGN_NONE },
1798 { X86::VFNMSUBPSr231r, X86::VFNMSUBPSr231m,
TB_ALIGN_NONE },
1799 { X86::VFNMSUBPDr231r, X86::VFNMSUBPDr231m,
TB_ALIGN_NONE },
1800 { X86::VFNMSUBPSr132r, X86::VFNMSUBPSr132m,
TB_ALIGN_NONE },
1801 { X86::VFNMSUBPDr132r, X86::VFNMSUBPDr132m,
TB_ALIGN_NONE },
1802 { X86::VFNMSUBPSr213r, X86::VFNMSUBPSr213m,
TB_ALIGN_NONE },
1803 { X86::VFNMSUBPDr213r, X86::VFNMSUBPDr213m,
TB_ALIGN_NONE },
1804 { X86::VFNMSUBPSr231rY, X86::VFNMSUBPSr231mY,
TB_ALIGN_NONE },
1805 { X86::VFNMSUBPDr231rY, X86::VFNMSUBPDr231mY,
TB_ALIGN_NONE },
1806 { X86::VFNMSUBPSr132rY, X86::VFNMSUBPSr132mY,
TB_ALIGN_NONE },
1807 { X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr132mY,
TB_ALIGN_NONE },
1808 { X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr213mY,
TB_ALIGN_NONE },
1809 { X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr213mY,
TB_ALIGN_NONE },
1811 { X86::VFMADDSUBPSr231r, X86::VFMADDSUBPSr231m,
TB_ALIGN_NONE },
1812 { X86::VFMADDSUBPDr231r, X86::VFMADDSUBPDr231m,
TB_ALIGN_NONE },
1813 { X86::VFMADDSUBPSr132r, X86::VFMADDSUBPSr132m,
TB_ALIGN_NONE },
1814 { X86::VFMADDSUBPDr132r, X86::VFMADDSUBPDr132m,
TB_ALIGN_NONE },
1815 { X86::VFMADDSUBPSr213r, X86::VFMADDSUBPSr213m,
TB_ALIGN_NONE },
1816 { X86::VFMADDSUBPDr213r, X86::VFMADDSUBPDr213m,
TB_ALIGN_NONE },
1817 { X86::VFMADDSUBPSr231rY, X86::VFMADDSUBPSr231mY,
TB_ALIGN_NONE },
1818 { X86::VFMADDSUBPDr231rY, X86::VFMADDSUBPDr231mY,
TB_ALIGN_NONE },
1819 { X86::VFMADDSUBPSr132rY, X86::VFMADDSUBPSr132mY,
TB_ALIGN_NONE },
1820 { X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr132mY,
TB_ALIGN_NONE },
1821 { X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr213mY,
TB_ALIGN_NONE },
1822 { X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr213mY,
TB_ALIGN_NONE },
1824 { X86::VFMSUBADDPSr231r, X86::VFMSUBADDPSr231m,
TB_ALIGN_NONE },
1825 { X86::VFMSUBADDPDr231r, X86::VFMSUBADDPDr231m,
TB_ALIGN_NONE },
1826 { X86::VFMSUBADDPSr132r, X86::VFMSUBADDPSr132m,
TB_ALIGN_NONE },
1827 { X86::VFMSUBADDPDr132r, X86::VFMSUBADDPDr132m,
TB_ALIGN_NONE },
1828 { X86::VFMSUBADDPSr213r, X86::VFMSUBADDPSr213m,
TB_ALIGN_NONE },
1829 { X86::VFMSUBADDPDr213r, X86::VFMSUBADDPDr213m,
TB_ALIGN_NONE },
1830 { X86::VFMSUBADDPSr231rY, X86::VFMSUBADDPSr231mY,
TB_ALIGN_NONE },
1831 { X86::VFMSUBADDPDr231rY, X86::VFMSUBADDPDr231mY,
TB_ALIGN_NONE },
1832 { X86::VFMSUBADDPSr132rY, X86::VFMSUBADDPSr132mY,
TB_ALIGN_NONE },
1833 { X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr132mY,
TB_ALIGN_NONE },
1834 { X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr213mY,
TB_ALIGN_NONE },
1835 { X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr213mY,
TB_ALIGN_NONE },
1862 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4rm,
TB_ALIGN_NONE },
1863 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4rm,
TB_ALIGN_NONE },
1864 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4rmY,
TB_ALIGN_NONE },
1865 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4rmY,
TB_ALIGN_NONE },
1866 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4rm,
TB_ALIGN_NONE },
1867 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4rm,
TB_ALIGN_NONE },
1868 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4rmY,
TB_ALIGN_NONE },
1869 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4rmY,
TB_ALIGN_NONE },
1872 { X86::VPCMOVrr, X86::VPCMOVrm, 0 },
1873 { X86::VPCMOVrrY, X86::VPCMOVrmY, 0 },
1874 { X86::VPERMIL2PDrr, X86::VPERMIL2PDrm, 0 },
1875 { X86::VPERMIL2PDrrY, X86::VPERMIL2PDrmY, 0 },
1876 { X86::VPERMIL2PSrr, X86::VPERMIL2PSrm, 0 },
1877 { X86::VPERMIL2PSrrY, X86::VPERMIL2PSrmY, 0 },
1878 { X86::VPPERMrr, X86::VPPERMrm, 0 },
1881 { X86::VPERMI2Drr, X86::VPERMI2Drm, 0 },
1882 { X86::VPERMI2Qrr, X86::VPERMI2Qrm, 0 },
1883 { X86::VPERMI2PSrr, X86::VPERMI2PSrm, 0 },
1884 { X86::VPERMI2PDrr, X86::VPERMI2PDrm, 0 },
1885 { X86::VBLENDMPDZrr, X86::VBLENDMPDZrm, 0 },
1886 { X86::VBLENDMPSZrr, X86::VBLENDMPSZrm, 0 },
1887 { X86::VPBLENDMDZrr, X86::VPBLENDMDZrm, 0 },
1888 { X86::VPBLENDMQZrr, X86::VPBLENDMQZrm, 0 },
1889 { X86::VBROADCASTSSZrk, X86::VBROADCASTSSZmk,
TB_NO_REVERSE },
1890 { X86::VBROADCASTSDZrk, X86::VBROADCASTSDZmk,
TB_NO_REVERSE },
1891 { X86::VBROADCASTSSZ256rk, X86::VBROADCASTSSZ256mk,
TB_NO_REVERSE },
1892 { X86::VBROADCASTSDZ256rk, X86::VBROADCASTSDZ256mk,
TB_NO_REVERSE },
1893 { X86::VBROADCASTSSZ128rk, X86::VBROADCASTSSZ128mk,
TB_NO_REVERSE },
1895 { X86::VADDPSZrrkz, X86::VADDPSZrmkz, 0 },
1896 { X86::VADDPDZrrkz, X86::VADDPDZrmkz, 0 },
1897 { X86::VSUBPSZrrkz, X86::VSUBPSZrmkz, 0 },
1898 { X86::VSUBPDZrrkz, X86::VSUBPDZrmkz, 0 },
1899 { X86::VMULPSZrrkz, X86::VMULPSZrmkz, 0 },
1900 { X86::VMULPDZrrkz, X86::VMULPDZrmkz, 0 },
1901 { X86::VDIVPSZrrkz, X86::VDIVPSZrmkz, 0 },
1902 { X86::VDIVPDZrrkz, X86::VDIVPDZrmkz, 0 },
1903 { X86::VMINPSZrrkz, X86::VMINPSZrmkz, 0 },
1904 { X86::VMINPDZrrkz, X86::VMINPDZrmkz, 0 },
1905 { X86::VMAXPSZrrkz, X86::VMAXPSZrmkz, 0 },
1906 { X86::VMAXPDZrrkz, X86::VMAXPDZrmkz, 0 },
1908 { X86::VADDPSZ256rrkz, X86::VADDPSZ256rmkz, 0 },
1909 { X86::VADDPDZ256rrkz, X86::VADDPDZ256rmkz, 0 },
1910 { X86::VSUBPSZ256rrkz, X86::VSUBPSZ256rmkz, 0 },
1911 { X86::VSUBPDZ256rrkz, X86::VSUBPDZ256rmkz, 0 },
1912 { X86::VMULPSZ256rrkz, X86::VMULPSZ256rmkz, 0 },
1913 { X86::VMULPDZ256rrkz, X86::VMULPDZ256rmkz, 0 },
1914 { X86::VDIVPSZ256rrkz, X86::VDIVPSZ256rmkz, 0 },
1915 { X86::VDIVPDZ256rrkz, X86::VDIVPDZ256rmkz, 0 },
1916 { X86::VMINPSZ256rrkz, X86::VMINPSZ256rmkz, 0 },
1917 { X86::VMINPDZ256rrkz, X86::VMINPDZ256rmkz, 0 },
1918 { X86::VMAXPSZ256rrkz, X86::VMAXPSZ256rmkz, 0 },
1919 { X86::VMAXPDZ256rrkz, X86::VMAXPDZ256rmkz, 0 },
1921 { X86::VADDPSZ128rrkz, X86::VADDPSZ128rmkz, 0 },
1922 { X86::VADDPDZ128rrkz, X86::VADDPDZ128rmkz, 0 },
1923 { X86::VSUBPSZ128rrkz, X86::VSUBPSZ128rmkz, 0 },
1924 { X86::VSUBPDZ128rrkz, X86::VSUBPDZ128rmkz, 0 },
1925 { X86::VMULPSZ128rrkz, X86::VMULPSZ128rmkz, 0 },
1926 { X86::VMULPDZ128rrkz, X86::VMULPDZ128rmkz, 0 },
1927 { X86::VDIVPSZ128rrkz, X86::VDIVPSZ128rmkz, 0 },
1928 { X86::VDIVPDZ128rrkz, X86::VDIVPDZ128rmkz, 0 },
1929 { X86::VMINPSZ128rrkz, X86::VMINPSZ128rmkz, 0 },
1930 { X86::VMINPDZ128rrkz, X86::VMINPDZ128rmkz, 0 },
1931 { X86::VMAXPSZ128rrkz, X86::VMAXPSZ128rmkz, 0 },
1932 { X86::VMAXPDZ128rrkz, X86::VMAXPDZ128rmkz, 0 }
1936 AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
1937 Entry.RegOp, Entry.MemOp,
1944 { X86::VADDPSZrrk, X86::VADDPSZrmk, 0 },
1945 { X86::VADDPDZrrk, X86::VADDPDZrmk, 0 },
1946 { X86::VSUBPSZrrk, X86::VSUBPSZrmk, 0 },
1947 { X86::VSUBPDZrrk, X86::VSUBPDZrmk, 0 },
1948 { X86::VMULPSZrrk, X86::VMULPSZrmk, 0 },
1949 { X86::VMULPDZrrk, X86::VMULPDZrmk, 0 },
1950 { X86::VDIVPSZrrk, X86::VDIVPSZrmk, 0 },
1951 { X86::VDIVPDZrrk, X86::VDIVPDZrmk, 0 },
1952 { X86::VMINPSZrrk, X86::VMINPSZrmk, 0 },
1953 { X86::VMINPDZrrk, X86::VMINPDZrmk, 0 },
1954 { X86::VMAXPSZrrk, X86::VMAXPSZrmk, 0 },
1955 { X86::VMAXPDZrrk, X86::VMAXPDZrmk, 0 },
1957 { X86::VADDPSZ256rrk, X86::VADDPSZ256rmk, 0 },
1958 { X86::VADDPDZ256rrk, X86::VADDPDZ256rmk, 0 },
1959 { X86::VSUBPSZ256rrk, X86::VSUBPSZ256rmk, 0 },
1960 { X86::VSUBPDZ256rrk, X86::VSUBPDZ256rmk, 0 },
1961 { X86::VMULPSZ256rrk, X86::VMULPSZ256rmk, 0 },
1962 { X86::VMULPDZ256rrk, X86::VMULPDZ256rmk, 0 },
1963 { X86::VDIVPSZ256rrk, X86::VDIVPSZ256rmk, 0 },
1964 { X86::VDIVPDZ256rrk, X86::VDIVPDZ256rmk, 0 },
1965 { X86::VMINPSZ256rrk, X86::VMINPSZ256rmk, 0 },
1966 { X86::VMINPDZ256rrk, X86::VMINPDZ256rmk, 0 },
1967 { X86::VMAXPSZ256rrk, X86::VMAXPSZ256rmk, 0 },
1968 { X86::VMAXPDZ256rrk, X86::VMAXPDZ256rmk, 0 },
1970 { X86::VADDPSZ128rrk, X86::VADDPSZ128rmk, 0 },
1971 { X86::VADDPDZ128rrk, X86::VADDPDZ128rmk, 0 },
1972 { X86::VSUBPSZ128rrk, X86::VSUBPSZ128rmk, 0 },
1973 { X86::VSUBPDZ128rrk, X86::VSUBPDZ128rmk, 0 },
1974 { X86::VMULPSZ128rrk, X86::VMULPSZ128rmk, 0 },
1975 { X86::VMULPDZ128rrk, X86::VMULPDZ128rmk, 0 },
1976 { X86::VDIVPSZ128rrk, X86::VDIVPSZ128rmk, 0 },
1977 { X86::VDIVPDZ128rrk, X86::VDIVPDZ128rmk, 0 },
1978 { X86::VMINPSZ128rrk, X86::VMINPSZ128rmk, 0 },
1979 { X86::VMINPDZ128rrk, X86::VMINPDZ128rmk, 0 },
1980 { X86::VMAXPSZ128rrk, X86::VMAXPSZ128rmk, 0 },
1981 { X86::VMAXPDZ128rrk, X86::VMAXPDZ128rmk, 0 }
1985 AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
1986 Entry.RegOp, Entry.MemOp,
1993 X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
1994 MemOp2RegOpTableType &M2RTable,
1995 unsigned RegOp,
unsigned MemOp,
unsigned Flags) {
1997 assert(!R2MTable.count(RegOp) &&
"Duplicate entry!");
1998 R2MTable[RegOp] = std::make_pair(MemOp, Flags);
2001 assert(!M2RTable.count(MemOp) &&
2002 "Duplicated entries in unfolding maps?");
2003 M2RTable[MemOp] = std::make_pair(RegOp, Flags);
2009 unsigned &SrcReg,
unsigned &DstReg,
2010 unsigned &SubIdx)
const {
2013 case X86::MOVSX16rr8:
2014 case X86::MOVZX16rr8:
2015 case X86::MOVSX32rr8:
2016 case X86::MOVZX32rr8:
2017 case X86::MOVSX64rr8:
2022 case X86::MOVSX32rr16:
2023 case X86::MOVZX32rr16:
2024 case X86::MOVSX64rr16:
2025 case X86::MOVSX64rr32: {
2033 case X86::MOVSX16rr8:
2034 case X86::MOVZX16rr8:
2035 case X86::MOVSX32rr8:
2036 case X86::MOVZX32rr8:
2037 case X86::MOVSX64rr8:
2038 SubIdx = X86::sub_8bit;
2040 case X86::MOVSX32rr16:
2041 case X86::MOVZX32rr16:
2042 case X86::MOVSX64rr16:
2043 SubIdx = X86::sub_16bit;
2045 case X86::MOVSX64rr32:
2046 SubIdx = X86::sub_32bit;
2059 if (MI->
getOpcode() == getCallFrameSetupOpcode() ||
2060 MI->
getOpcode() == getCallFrameDestroyOpcode()) {
2067 if (MI->
getOpcode() == getCallFrameSetupOpcode())
2079 for (
auto E = MBB->
end();
I != E; ++
I) {
2080 if (
I->getOpcode() == getCallFrameDestroyOpcode() ||
2087 if (
I->getOpcode() != getCallFrameDestroyOpcode())
2090 return -(
I->getOperand(1).getImm());
2100 case X86::PUSH32rmm:
2101 case X86::PUSH32rmr:
2109 bool X86InstrInfo::isFrameOperand(
const MachineInstr *
MI,
unsigned int Op,
2140 case X86::VMOVAPSrm:
2141 case X86::VMOVAPDrm:
2142 case X86::VMOVDQArm:
2143 case X86::VMOVUPSYrm:
2144 case X86::VMOVAPSYrm:
2145 case X86::VMOVUPDYrm:
2146 case X86::VMOVAPDYrm:
2147 case X86::VMOVDQUYrm:
2148 case X86::VMOVDQAYrm:
2149 case X86::MMX_MOVD64rm:
2150 case X86::MMX_MOVQ64rm:
2151 case X86::VMOVAPSZrm:
2152 case X86::VMOVUPSZrm:
2164 case X86::ST_FpP64m:
2172 case X86::VMOVAPSmr:
2173 case X86::VMOVAPDmr:
2174 case X86::VMOVDQAmr:
2175 case X86::VMOVUPSYmr:
2176 case X86::VMOVAPSYmr:
2177 case X86::VMOVUPDYmr:
2178 case X86::VMOVAPDYmr:
2179 case X86::VMOVDQUYmr:
2180 case X86::VMOVDQAYmr:
2181 case X86::VMOVUPSZmr:
2182 case X86::VMOVAPSZmr:
2183 case X86::MMX_MOVD64mr:
2184 case X86::MMX_MOVQ64mr:
2185 case X86::MMX_MOVNTQmr:
2192 int &FrameIndex)
const {
2200 int &FrameIndex)
const {
2207 return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
2213 int &FrameIndex)
const {
2216 isFrameOperand(MI, 0, FrameIndex))
2222 int &FrameIndex)
const {
2229 return hasStoreToStackSlot(MI, Dummy, FrameIndex);
2239 bool isPICBase =
false;
2243 if (DefMI->
getOpcode() != X86::MOVPC32r)
2245 assert(!isPICBase &&
"More than one PIC base?");
2270 case X86::VMOVAPSrm:
2271 case X86::VMOVUPSrm:
2272 case X86::VMOVAPDrm:
2273 case X86::VMOVDQArm:
2274 case X86::VMOVDQUrm:
2275 case X86::VMOVAPSYrm:
2276 case X86::VMOVUPSYrm:
2277 case X86::VMOVAPDYrm:
2278 case X86::VMOVDQAYrm:
2279 case X86::VMOVDQUYrm:
2280 case X86::MMX_MOVD64rm:
2281 case X86::MMX_MOVQ64rm:
2282 case X86::FsVMOVAPSrm:
2283 case X86::FsVMOVAPDrm:
2284 case X86::FsMOVAPSrm:
2285 case X86::FsMOVAPDrm: {
2293 if (BaseReg == 0 || BaseReg == X86::RIP)
2339 for (
unsigned i = 0; Iter != E && i < 4; ++i) {
2340 bool SeenDef =
false;
2341 for (
unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2347 if (MO.
getReg() == X86::EFLAGS) {
2359 while (Iter != E && Iter->isDebugValue())
2368 if ((*SI)->isLiveIn(X86::EFLAGS))
2375 for (
unsigned i = 0; i < 4; ++i) {
2383 while (Iter != B && Iter->isDebugValue())
2386 bool SawKill =
false;
2387 for (
unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2395 if (MO.
isKill()) SawKill =
true;
2411 unsigned DestReg,
unsigned SubIdx,
2444 unsigned ShiftAmtOperandIdx) {
2448 return Imm & ShiftCountMask;
2459 return ShAmt < 4 && ShAmt > 0;
2463 unsigned Opc,
bool AllowSP,
2464 unsigned &NewSrc,
bool &isKill,
bool &isUndef,
2469 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
2471 RC = Opc != X86::LEA32r ?
2472 &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
2474 unsigned SrcReg = Src.
getReg();
2478 if (Opc != X86::LEA64_32r) {
2537 X86InstrInfo::convertToThreeAddressWithLEA(
unsigned MIOpc,
2549 unsigned Opc, leaInReg;
2551 Opc = X86::LEA64_32r;
2572 get(Opc), leaOutReg);
2575 case X86::SHL16ri: {
2589 case X86::ADD16ri_DB:
2590 case X86::ADD16ri8_DB:
2594 case X86::ADD16rr_DB: {
2597 unsigned leaInReg2 = 0;
2602 addRegReg(MIB, leaInReg,
true, leaInReg,
false);
2615 addRegReg(MIB, leaInReg,
true, leaInReg2,
true);
2617 if (LV && isKill2 && InsMI2)
2673 bool DisableLEA16 =
true;
2678 default:
return nullptr;
2679 case X86::SHL64ri: {
2680 assert(MI->
getNumOperands() >= 3 &&
"Unknown shift instruction!");
2687 &X86::GR64_NOSPRegClass))
2695 case X86::SHL32ri: {
2696 assert(MI->
getNumOperands() >= 3 &&
"Unknown shift instruction!");
2700 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2703 bool isKill, isUndef;
2707 SrcReg, isKill, isUndef, ImplicitOp))
2715 if (ImplicitOp.
getReg() != 0)
2721 case X86::SHL16ri: {
2722 assert(MI->
getNumOperands() >= 3 &&
"Unknown shift instruction!");
2727 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) :
nullptr;
2736 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
2737 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2738 bool isKill, isUndef;
2742 SrcReg, isKill, isUndef, ImplicitOp))
2748 if (ImplicitOp.
getReg() != 0)
2756 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2765 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
2766 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2768 bool isKill, isUndef;
2772 SrcReg, isKill, isUndef, ImplicitOp))
2778 if (ImplicitOp.
getReg() != 0)
2787 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2794 case X86::ADD64rr_DB:
2796 case X86::ADD32rr_DB: {
2799 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
2802 Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2804 bool isKill, isUndef;
2808 SrcReg, isKill, isUndef, ImplicitOp))
2812 bool isKill2, isUndef2;
2816 SrcReg2, isKill2, isUndef2, ImplicitOp2))
2821 if (ImplicitOp.
getReg() != 0)
2823 if (ImplicitOp2.
getReg() != 0)
2826 NewMI =
addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
2829 NewMI->getOperand(1).setIsUndef(isUndef);
2830 NewMI->getOperand(3).setIsUndef(isUndef2);
2837 case X86::ADD16rr_DB: {
2839 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2851 NewMI->getOperand(1).setIsUndef(isUndef);
2852 NewMI->getOperand(3).setIsUndef(isUndef2);
2858 case X86::ADD64ri32:
2860 case X86::ADD64ri32_DB:
2861 case X86::ADD64ri8_DB:
2869 case X86::ADD32ri_DB:
2870 case X86::ADD32ri8_DB: {
2872 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2874 bool isKill, isUndef;
2878 SrcReg, isKill, isUndef, ImplicitOp))
2884 if (ImplicitOp.
getReg() != 0)
2892 case X86::ADD16ri_DB:
2893 case X86::ADD16ri8_DB:
2895 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2904 if (!NewMI)
return nullptr;
2913 MFI->insert(MBBI, NewMI);
2922 case X86::SHRD16rri8:
2923 case X86::SHLD16rri8:
2924 case X86::SHRD32rri8:
2925 case X86::SHLD32rri8:
2926 case X86::SHRD64rri8:
2927 case X86::SHLD64rri8:{
2932 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8;
break;
2933 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8;
break;
2934 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8;
break;
2935 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8;
break;
2936 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8;
break;
2937 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8;
break;
2949 case X86::BLENDPDrri:
2950 case X86::BLENDPSrri:
2951 case X86::PBLENDWrri:
2952 case X86::VBLENDPDrri:
2953 case X86::VBLENDPSrri:
2954 case X86::VBLENDPDYrri:
2955 case X86::VBLENDPSYrri:
2956 case X86::VPBLENDDrri:
2957 case X86::VPBLENDWrri:
2958 case X86::VPBLENDDYrri:
2959 case X86::VPBLENDWYrri:{
2963 case X86::BLENDPDrri: Mask = 0x03;
break;
2964 case X86::BLENDPSrri: Mask = 0x0F;
break;
2965 case X86::PBLENDWrri: Mask = 0xFF;
break;
2966 case X86::VBLENDPDrri: Mask = 0x03;
break;
2967 case X86::VBLENDPSrri: Mask = 0x0F;
break;
2968 case X86::VBLENDPDYrri: Mask = 0x0F;
break;
2969 case X86::VBLENDPSYrri: Mask = 0xFF;
break;
2970 case X86::VPBLENDDrri: Mask = 0x0F;
break;
2971 case X86::VPBLENDWrri: Mask = 0xFF;
break;
2972 case X86::VPBLENDDYrri: Mask = 0xFF;
break;
2973 case X86::VPBLENDWYrri: Mask = 0xFF;
break;
2985 case X86::PCLMULQDQrr:
2986 case X86::VPCLMULQDQrr:{
2990 unsigned Src1Hi = Imm & 0x01;
2991 unsigned Src2Hi = Imm & 0x10;
3002 case X86::VCMPPDrri:
3003 case X86::VCMPPSrri:
3004 case X86::VCMPPDYrri:
3005 case X86::VCMPPSYrri: {
3024 case X86::VPCOMBri:
case X86::VPCOMUBri:
3025 case X86::VPCOMDri:
case X86::VPCOMUDri:
3026 case X86::VPCOMQri:
case X86::VPCOMUQri:
3027 case X86::VPCOMWri:
case X86::VPCOMUWri: {
3031 case 0x00: Imm = 0x02;
break;
3032 case 0x01: Imm = 0x03;
break;
3033 case 0x02: Imm = 0x00;
break;
3034 case 0x03: Imm = 0x01;
break;
3050 case X86::CMOVB16rr:
case X86::CMOVB32rr:
case X86::CMOVB64rr:
3051 case X86::CMOVAE16rr:
case X86::CMOVAE32rr:
case X86::CMOVAE64rr:
3052 case X86::CMOVE16rr:
case X86::CMOVE32rr:
case X86::CMOVE64rr:
3053 case X86::CMOVNE16rr:
case X86::CMOVNE32rr:
case X86::CMOVNE64rr:
3054 case X86::CMOVBE16rr:
case X86::CMOVBE32rr:
case X86::CMOVBE64rr:
3055 case X86::CMOVA16rr:
case X86::CMOVA32rr:
case X86::CMOVA64rr:
3056 case X86::CMOVL16rr:
case X86::CMOVL32rr:
case X86::CMOVL64rr:
3057 case X86::CMOVGE16rr:
case X86::CMOVGE32rr:
case X86::CMOVGE64rr:
3058 case X86::CMOVLE16rr:
case X86::CMOVLE32rr:
case X86::CMOVLE64rr:
3059 case X86::CMOVG16rr:
case X86::CMOVG32rr:
case X86::CMOVG64rr:
3060 case X86::CMOVS16rr:
case X86::CMOVS32rr:
case X86::CMOVS64rr:
3061 case X86::CMOVNS16rr:
case X86::CMOVNS32rr:
case X86::CMOVNS64rr:
3062 case X86::CMOVP16rr:
case X86::CMOVP32rr:
case X86::CMOVP64rr:
3063 case X86::CMOVNP16rr:
case X86::CMOVNP32rr:
case X86::CMOVNP64rr:
3064 case X86::CMOVO16rr:
case X86::CMOVO32rr:
case X86::CMOVO64rr:
3065 case X86::CMOVNO16rr:
case X86::CMOVNO32rr:
case X86::CMOVNO64rr: {
3069 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr;
break;
3070 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr;
break;
3071 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr;
break;
3072 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr;
break;
3073 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr;
break;
3074 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr;
break;
3075 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr;
break;
3076 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr;
break;
3077 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr;
break;
3078 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr;
break;
3079 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr;
break;
3080 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr;
break;
3081 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr;
break;
3082 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr;
break;
3083 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr;
break;
3084 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr;
break;
3085 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr;
break;
3086 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr;
break;
3087 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr;
break;
3088 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr;
break;
3089 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr;
break;
3090 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr;
break;
3091 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr;
break;
3092 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr;
break;
3093 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr;
break;
3094 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr;
break;
3095 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr;
break;
3096 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr;
break;
3097 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr;
break;
3098 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr;
break;
3099 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr;
break;
3100 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr;
break;
3101 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr;
break;
3102 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr;
break;
3103 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr;
break;
3104 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr;
break;
3105 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr;
break;
3106 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr;
break;
3107 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr;
break;
3108 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr;
break;
3109 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr;
break;
3110 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr;
break;
3111 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr;
break;
3112 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr;
break;
3113 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr;
break;
3114 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr;
break;
3115 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr;
break;
3116 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr;
break;
3132 unsigned &SrcOpIdx2)
const {
3136 case X86::VCMPPDrri:
3137 case X86::VCMPPSrri:
3138 case X86::VCMPPDYrri:
3139 case X86::VCMPPSYrri: {
3154 case X86::VFMADDPDr231r:
3155 case X86::VFMADDPSr231r:
3156 case X86::VFMADDSDr231r:
3157 case X86::VFMADDSSr231r:
3158 case X86::VFMSUBPDr231r:
3159 case X86::VFMSUBPSr231r:
3160 case X86::VFMSUBSDr231r:
3161 case X86::VFMSUBSSr231r:
3162 case X86::VFNMADDPDr231r:
3163 case X86::VFNMADDPSr231r:
3164 case X86::VFNMADDSDr231r:
3165 case X86::VFNMADDSSr231r:
3166 case X86::VFNMSUBPDr231r:
3167 case X86::VFNMSUBPSr231r:
3168 case X86::VFNMSUBSDr231r:
3169 case X86::VFNMSUBSSr231r:
3170 case X86::VFMADDPDr231rY:
3171 case X86::VFMADDPSr231rY:
3172 case X86::VFMSUBPDr231rY:
3173 case X86::VFMSUBPSr231rY:
3174 case X86::VFNMADDPDr231rY:
3175 case X86::VFNMADDPSr231rY:
3176 case X86::VFNMSUBPDr231rY:
3177 case X86::VFNMSUBPSr231rY:
3212 case X86::SETAr:
case X86::SETAm:
return X86::COND_A;
3213 case X86::SETAEr:
case X86::SETAEm:
return X86::COND_AE;
3214 case X86::SETBr:
case X86::SETBm:
return X86::COND_B;
3215 case X86::SETBEr:
case X86::SETBEm:
return X86::COND_BE;
3216 case X86::SETEr:
case X86::SETEm:
return X86::COND_E;
3217 case X86::SETGr:
case X86::SETGm:
return X86::COND_G;
3218 case X86::SETGEr:
case X86::SETGEm:
return X86::COND_GE;
3219 case X86::SETLr:
case X86::SETLm:
return X86::COND_L;
3220 case X86::SETLEr:
case X86::SETLEm:
return X86::COND_LE;
3221 case X86::SETNEr:
case X86::SETNEm:
return X86::COND_NE;
3222 case X86::SETNOr:
case X86::SETNOm:
return X86::COND_NO;
3223 case X86::SETNPr:
case X86::SETNPm:
return X86::COND_NP;
3224 case X86::SETNSr:
case X86::SETNSm:
return X86::COND_NS;
3225 case X86::SETOr:
case X86::SETOm:
return X86::COND_O;
3226 case X86::SETPr:
case X86::SETPm:
return X86::COND_P;
3227 case X86::SETSr:
case X86::SETSm:
return X86::COND_S;
3235 case X86::CMOVA16rm:
case X86::CMOVA16rr:
case X86::CMOVA32rm:
3236 case X86::CMOVA32rr:
case X86::CMOVA64rm:
case X86::CMOVA64rr:
3238 case X86::CMOVAE16rm:
case X86::CMOVAE16rr:
case X86::CMOVAE32rm:
3239 case X86::CMOVAE32rr:
case X86::CMOVAE64rm:
case X86::CMOVAE64rr:
3241 case X86::CMOVB16rm:
case X86::CMOVB16rr:
case X86::CMOVB32rm:
3242 case X86::CMOVB32rr:
case X86::CMOVB64rm:
case X86::CMOVB64rr:
3244 case X86::CMOVBE16rm:
case X86::CMOVBE16rr:
case X86::CMOVBE32rm:
3245 case X86::CMOVBE32rr:
case X86::CMOVBE64rm:
case X86::CMOVBE64rr:
3247 case X86::CMOVE16rm:
case X86::CMOVE16rr:
case X86::CMOVE32rm:
3248 case X86::CMOVE32rr:
case X86::CMOVE64rm:
case X86::CMOVE64rr:
3250 case X86::CMOVG16rm:
case X86::CMOVG16rr:
case X86::CMOVG32rm:
3251 case X86::CMOVG32rr:
case X86::CMOVG64rm:
case X86::CMOVG64rr:
3253 case X86::CMOVGE16rm:
case X86::CMOVGE16rr:
case X86::CMOVGE32rm:
3254 case X86::CMOVGE32rr:
case X86::CMOVGE64rm:
case X86::CMOVGE64rr:
3256 case X86::CMOVL16rm:
case X86::CMOVL16rr:
case X86::CMOVL32rm:
3257 case X86::CMOVL32rr:
case X86::CMOVL64rm:
case X86::CMOVL64rr:
3259 case X86::CMOVLE16rm:
case X86::CMOVLE16rr:
case X86::CMOVLE32rm:
3260 case X86::CMOVLE32rr:
case X86::CMOVLE64rm:
case X86::CMOVLE64rr:
3262 case X86::CMOVNE16rm:
case X86::CMOVNE16rr:
case X86::CMOVNE32rm:
3263 case X86::CMOVNE32rr:
case X86::CMOVNE64rm:
case X86::CMOVNE64rr:
3265 case X86::CMOVNO16rm:
case X86::CMOVNO16rr:
case X86::CMOVNO32rm:
3266 case X86::CMOVNO32rr:
case X86::CMOVNO64rm:
case X86::CMOVNO64rr:
3268 case X86::CMOVNP16rm:
case X86::CMOVNP16rr:
case X86::CMOVNP32rm:
3269 case X86::CMOVNP32rr:
case X86::CMOVNP64rm:
case X86::CMOVNP64rr:
3271 case X86::CMOVNS16rm:
case X86::CMOVNS16rr:
case X86::CMOVNS32rm:
3272 case X86::CMOVNS32rr:
case X86::CMOVNS64rm:
case X86::CMOVNS64rr:
3274 case X86::CMOVO16rm:
case X86::CMOVO16rr:
case X86::CMOVO32rm:
3275 case X86::CMOVO32rr:
case X86::CMOVO64rm:
case X86::CMOVO64rr:
3277 case X86::CMOVP16rm:
case X86::CMOVP16rr:
case X86::CMOVP32rm:
3278 case X86::CMOVP32rr:
case X86::CMOVP64rm:
case X86::CMOVP64rr:
3280 case X86::CMOVS16rm:
case X86::CMOVS16rr:
case X86::CMOVS32rm:
3281 case X86::CMOVS32rr:
case X86::CMOVS64rm:
case X86::CMOVS64rr:
3353 static const uint16_t Opc[16][2] = {
3354 { X86::SETAr, X86::SETAm },
3355 { X86::SETAEr, X86::SETAEm },
3356 { X86::SETBr, X86::SETBm },
3357 { X86::SETBEr, X86::SETBEm },
3358 { X86::SETEr, X86::SETEm },
3359 { X86::SETGr, X86::SETGm },
3360 { X86::SETGEr, X86::SETGEm },
3361 { X86::SETLr, X86::SETLm },
3362 { X86::SETLEr, X86::SETLEm },
3363 { X86::SETNEr, X86::SETNEm },
3364 { X86::SETNOr, X86::SETNOm },
3365 { X86::SETNPr, X86::SETNPm },
3366 { X86::SETNSr, X86::SETNSm },
3367 { X86::SETOr, X86::SETOm },
3368 { X86::SETPr, X86::SETPm },
3369 { X86::SETSr, X86::SETSm }
3372 assert(CC <=
LAST_VALID_COND &&
"Can only handle standard cond codes");
3373 return Opc[CC][HasMemoryOperand ? 1 : 0];
3379 bool HasMemoryOperand) {
3380 static const uint16_t Opc[32][3] = {
3381 { X86::CMOVA16rr, X86::CMOVA32rr, X86::CMOVA64rr },
3382 { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
3383 { X86::CMOVB16rr, X86::CMOVB32rr, X86::CMOVB64rr },
3384 { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
3385 { X86::CMOVE16rr, X86::CMOVE32rr, X86::CMOVE64rr },
3386 { X86::CMOVG16rr, X86::CMOVG32rr, X86::CMOVG64rr },
3387 { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
3388 { X86::CMOVL16rr, X86::CMOVL32rr, X86::CMOVL64rr },
3389 { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
3390 { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
3391 { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
3392 { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
3393 { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
3394 { X86::CMOVO16rr, X86::CMOVO32rr, X86::CMOVO64rr },
3395 { X86::CMOVP16rr, X86::CMOVP32rr, X86::CMOVP64rr },
3396 { X86::CMOVS16rr, X86::CMOVS32rr, X86::CMOVS64rr },
3397 { X86::CMOVA16rm, X86::CMOVA32rm, X86::CMOVA64rm },
3398 { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
3399 { X86::CMOVB16rm, X86::CMOVB32rm, X86::CMOVB64rm },
3400 { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
3401 { X86::CMOVE16rm, X86::CMOVE32rm, X86::CMOVE64rm },
3402 { X86::CMOVG16rm, X86::CMOVG32rm, X86::CMOVG64rm },
3403 { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
3404 { X86::CMOVL16rm, X86::CMOVL32rm, X86::CMOVL64rm },
3405 { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
3406 { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
3407 { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
3408 { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
3409 { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
3410 { X86::CMOVO16rm, X86::CMOVO32rm, X86::CMOVO64rm },
3411 { X86::CMOVP16rm, X86::CMOVP32rm, X86::CMOVP64rm },
3412 { X86::CMOVS16rm, X86::CMOVS32rm, X86::CMOVS64rm }
3415 assert(CC < 16 &&
"Can only handle standard cond codes");
3416 unsigned Idx = HasMemoryOperand ? 16+CC : CC;
3419 case 2:
return Opc[Idx][0];
3420 case 4:
return Opc[Idx][1];
3421 case 8:
return Opc[Idx][2];
3436 bool X86InstrInfo::AnalyzeBranchImpl(
3445 while (I != MBB.
begin()) {
3447 if (I->isDebugValue())
3461 if (I->getOpcode() == X86::JMP_1) {
3465 TBB = I->getOperand(0).getMBB();
3470 while (std::next(I) != MBB.
end())
3481 UnCondBrIter = MBB.
end();
3486 TBB = I->getOperand(0).getMBB();
3498 if (AllowModify && UnCondBrIter != MBB.
end() &&
3522 .
addMBB(UnCondBrIter->getOperand(0).getMBB());
3527 UnCondBrIter->eraseFromParent();
3530 UnCondBrIter = MBB.
end();
3536 TBB = I->getOperand(0).getMBB();
3545 assert(Cond.
size() == 1);
3550 if (TBB != I->getOperand(0).getMBB())
3555 if (OldBranchCode == BranchCode)
3575 Cond[0].setImm(BranchCode);
3586 bool AllowModify)
const {
3588 return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
3592 MachineBranchPredicate &MBP,
3593 bool AllowModify)
const {
3594 using namespace std::placeholders;
3598 if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
3602 if (Cond.
size() != 1)
3605 assert(MBP.TrueDest &&
"expected!");
3613 bool SingleUseCondition =
true;
3615 for (
auto I = std::next(MBB.
rbegin()), E = MBB.
rend(); I != E; ++
I) {
3616 if (I->modifiesRegister(X86::EFLAGS, TRI)) {
3621 if (I->readsRegister(X86::EFLAGS, TRI))
3622 SingleUseCondition =
false;
3628 if (SingleUseCondition) {
3630 if (Succ->isLiveIn(X86::EFLAGS))
3631 SingleUseCondition =
false;
3634 MBP.ConditionDef = ConditionDef;
3635 MBP.SingleUseCondition = SingleUseCondition;
3642 const unsigned TestOpcode =
3643 Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
3645 if (ConditionDef->getOpcode() == TestOpcode &&
3646 ConditionDef->getNumOperands() == 3 &&
3647 ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
3649 MBP.LHS = ConditionDef->getOperand(0);
3664 while (I != MBB.
begin()) {
3666 if (I->isDebugValue())
3668 if (I->getOpcode() != X86::JMP_1 &&
3672 I->eraseFromParent();
3685 assert(TBB &&
"InsertBranch must not be told to insert a fallthrough");
3686 assert((Cond.
size() == 1 || Cond.
size() == 0) &&
3687 "X86 branch conditions have one component!");
3691 assert(!FBB &&
"Unconditional branch with multiple successors!");
3731 unsigned TrueReg,
unsigned FalseReg,
3732 int &CondCycles,
int &TrueCycles,
int &FalseCycles)
const {
3736 if (Cond.
size() != 1)
3750 if (X86::GR16RegClass.hasSubClassEq(RC) ||
3751 X86::GR32RegClass.hasSubClassEq(RC) ||
3752 X86::GR64RegClass.hasSubClassEq(RC)) {
3768 unsigned TrueReg,
unsigned FalseReg)
const {
3770 assert(Cond.
size() == 1 &&
"Invalid Cond array");
3779 return X86::GR8_ABCD_HRegClass.contains(Reg);
3791 bool HasAVX = Subtarget.
hasAVX();
3793 if (X86::GR64RegClass.
contains(DestReg)) {
3794 if (X86::VR128XRegClass.
contains(SrcReg))
3796 return HasAVX512 ? X86::VMOVPQIto64Zrr: (HasAVX ? X86::VMOVPQIto64rr :
3798 if (X86::VR64RegClass.
contains(SrcReg))
3800 return X86::MMX_MOVD64from64rr;
3801 }
else if (X86::GR64RegClass.
contains(SrcReg)) {
3803 if (X86::VR128XRegClass.
contains(DestReg))
3804 return HasAVX512 ? X86::VMOV64toPQIZrr: (HasAVX ? X86::VMOV64toPQIrr :
3807 if (X86::VR64RegClass.
contains(DestReg))
3808 return X86::MMX_MOVD64to64rr;
3814 if (X86::GR32RegClass.
contains(DestReg) && X86::FR32XRegClass.contains(SrcReg))
3816 return HasAVX512 ? X86::VMOVSS2DIZrr : (HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr);
3818 if (X86::FR32XRegClass.
contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
3820 return HasAVX512 ? X86::VMOVDI2SSZrr : (HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr);
3825 return X86::VK8RegClass.contains(Reg) ||
3826 X86::VK16RegClass.contains(Reg) ||
3827 X86::VK32RegClass.contains(Reg) ||
3828 X86::VK64RegClass.contains(Reg) ||
3829 X86::VK1RegClass.contains(Reg);
3833 if (X86::VR128XRegClass.
contains(DestReg, SrcReg) ||
3834 X86::VR256XRegClass.
contains(DestReg, SrcReg) ||
3835 X86::VR512RegClass.
contains(DestReg, SrcReg)) {
3838 return X86::VMOVAPSZrr;
3842 return X86::KMOVWkk;
3844 (X86::GR32RegClass.
contains(SrcReg) ||
3845 X86::GR16RegClass.
contains(SrcReg) ||
3846 X86::GR8RegClass.
contains(SrcReg))) {
3848 return X86::KMOVWkr;
3850 if ((X86::GR32RegClass.
contains(DestReg) ||
3851 X86::GR16RegClass.
contains(DestReg) ||
3852 X86::GR8RegClass.
contains(DestReg)) &&
3855 return X86::KMOVWrk;
3862 unsigned DestReg,
unsigned SrcReg,
3863 bool KillSrc)
const {
3865 bool HasAVX = Subtarget.
hasAVX();
3868 if (X86::GR64RegClass.
contains(DestReg, SrcReg))
3870 else if (X86::GR32RegClass.
contains(DestReg, SrcReg))
3872 else if (X86::GR16RegClass.
contains(DestReg, SrcReg))
3874 else if (X86::GR8RegClass.
contains(DestReg, SrcReg)) {
3879 Opc = X86::MOV8rr_NOREX;
3881 assert(X86::GR8_NOREXRegClass.
contains(SrcReg, DestReg) &&
3882 "8-bit H register can not be copied outside GR8_NOREX");
3886 else if (X86::VR64RegClass.
contains(DestReg, SrcReg))
3887 Opc = X86::MMX_MOVQ64rr;
3890 else if (X86::VR128RegClass.
contains(DestReg, SrcReg))
3891 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
3892 else if (X86::VR256RegClass.
contains(DestReg, SrcReg))
3893 Opc = X86::VMOVAPSYrr;
3898 BuildMI(MBB, MI, DL,
get(Opc), DestReg)
3906 if (SrcReg == X86::EFLAGS) {
3907 if (X86::GR64RegClass.
contains(DestReg)) {
3908 BuildMI(MBB, MI, DL,
get(X86::PUSHF64));
3909 BuildMI(MBB, MI, DL,
get(X86::POP64r), DestReg);
3912 if (X86::GR32RegClass.
contains(DestReg)) {
3913 BuildMI(MBB, MI, DL,
get(X86::PUSHF32));
3914 BuildMI(MBB, MI, DL,
get(X86::POP32r), DestReg);
3918 if (DestReg == X86::EFLAGS) {
3919 if (X86::GR64RegClass.
contains(SrcReg)) {
3920 BuildMI(MBB, MI, DL,
get(X86::PUSH64r))
3922 BuildMI(MBB, MI, DL,
get(X86::POPF64));
3925 if (X86::GR32RegClass.
contains(SrcReg)) {
3926 BuildMI(MBB, MI, DL,
get(X86::PUSH32r))
3928 BuildMI(MBB, MI, DL,
get(X86::POPF32));
3933 DEBUG(
dbgs() <<
"Cannot copy " << RI.getName(SrcReg)
3934 <<
" to " << RI.getName(DestReg) <<
'\n');
3940 bool isStackAligned,
3944 if (X86::VK8RegClass.hasSubClassEq(RC) ||
3945 X86::VK16RegClass.hasSubClassEq(RC))
3946 return load ? X86::KMOVWkm : X86::KMOVWmk;
3947 if (RC->
getSize() == 4 && X86::FR32XRegClass.hasSubClassEq(RC))
3948 return load ? X86::VMOVSSZrm : X86::VMOVSSZmr;
3949 if (RC->
getSize() == 8 && X86::FR64XRegClass.hasSubClassEq(RC))
3950 return load ? X86::VMOVSDZrm : X86::VMOVSDZmr;
3951 if (X86::VR512RegClass.hasSubClassEq(RC))
3952 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3955 bool HasAVX = STI.
hasAVX();
3960 assert(X86::GR8RegClass.hasSubClassEq(RC) &&
"Unknown 1-byte regclass");
3964 if (
isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
3965 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
3966 return load ? X86::MOV8rm : X86::MOV8mr;
3968 assert(X86::GR16RegClass.hasSubClassEq(RC) &&
"Unknown 2-byte regclass");
3969 return load ? X86::MOV16rm : X86::MOV16mr;
3971 if (X86::GR32RegClass.hasSubClassEq(RC))
3972 return load ? X86::MOV32rm : X86::MOV32mr;
3973 if (X86::FR32RegClass.hasSubClassEq(RC))
3975 (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
3976 (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
3977 if (X86::RFP32RegClass.hasSubClassEq(RC))
3978 return load ? X86::LD_Fp32m : X86::ST_Fp32m;
3981 if (X86::GR64RegClass.hasSubClassEq(RC))
3982 return load ? X86::MOV64rm : X86::MOV64mr;
3983 if (X86::FR64RegClass.hasSubClassEq(RC))
3985 (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
3986 (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
3987 if (X86::VR64RegClass.hasSubClassEq(RC))
3988 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
3989 if (X86::RFP64RegClass.hasSubClassEq(RC))
3990 return load ? X86::LD_Fp64m : X86::ST_Fp64m;
3993 assert(X86::RFP80RegClass.hasSubClassEq(RC) &&
"Unknown 10-byte regclass");
3994 return load ? X86::LD_Fp80m : X86::ST_FpP80m;
3996 assert((X86::VR128RegClass.hasSubClassEq(RC) ||
3997 X86::VR128XRegClass.hasSubClassEq(RC))&&
"Unknown 16-byte regclass");
4001 (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) :
4002 (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
4005 (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) :
4006 (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
4009 assert((X86::VR256RegClass.hasSubClassEq(RC) ||
4010 X86::VR256XRegClass.hasSubClassEq(RC)) &&
"Unknown 32-byte regclass");
4013 return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
4015 return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
4017 assert(X86::VR512RegClass.hasSubClassEq(RC) &&
"Unknown 64-byte regclass");
4019 return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
4021 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
4030 if (MemRefBegin < 0)
4046 if (!DispMO.
isImm())
4049 Offset = DispMO.
getImm();
4057 bool isStackAligned,
4065 bool isStackAligned,
4072 unsigned SrcReg,
bool isKill,
int FrameIdx,
4077 "Stack slot too small for store");
4078 unsigned Alignment = std::max<uint32_t>(RC->
getSize(), 16);
4095 unsigned Alignment = std::max<uint32_t>(RC->
getSize(), 16);
4096 bool isAligned = MMOBegin != MMOEnd &&
4101 for (
unsigned i = 0, e = Addr.
size(); i != e; ++i)
4111 unsigned DestReg,
int FrameIdx,
4115 unsigned Alignment = std::max<uint32_t>(RC->
getSize(), 16);
4130 unsigned Alignment = std::max<uint32_t>(RC->
getSize(), 16);
4131 bool isAligned = MMOBegin != MMOEnd &&
4136 for (
unsigned i = 0, e = Addr.
size(); i != e; ++i)
4144 int &CmpMask,
int &CmpValue)
const {
4147 case X86::CMP64ri32:
4178 case X86::SUB64ri32:
4221 unsigned SrcReg2,
int ImmValue,
4223 if (((FlagI->
getOpcode() == X86::CMP64rr &&
4237 if (((FlagI->
getOpcode() == X86::CMP64ri32 &&
4261 default:
return false;
4265 case X86::SAR8ri:
case X86::SAR16ri:
case X86::SAR32ri:
case X86::SAR64ri:
4266 case X86::SHR8ri:
case X86::SHR16ri:
case X86::SHR32ri:
case X86::SHR64ri:
4271 case X86::SHL8ri:
case X86::SHL16ri:
case X86::SHL32ri:
case X86::SHL64ri:{
4277 case X86::SHRD16rri8:
case X86::SHRD32rri8:
case X86::SHRD64rri8:
4278 case X86::SHLD16rri8:
case X86::SHLD32rri8:
case X86::SHLD64rri8:
4281 case X86::SUB64ri32:
case X86::SUB64ri8:
case X86::SUB32ri:
4282 case X86::SUB32ri8:
case X86::SUB16ri:
case X86::SUB16ri8:
4283 case X86::SUB8ri:
case X86::SUB64rr:
case X86::SUB32rr:
4284 case X86::SUB16rr:
case X86::SUB8rr:
case X86::SUB64rm:
4285 case X86::SUB32rm:
case X86::SUB16rm:
case X86::SUB8rm:
4286 case X86::DEC64r:
case X86::DEC32r:
case X86::DEC16r:
case X86::DEC8r:
4287 case X86::ADD64ri32:
case X86::ADD64ri8:
case X86::ADD32ri:
4288 case X86::ADD32ri8:
case X86::ADD16ri:
case X86::ADD16ri8:
4289 case X86::ADD8ri:
case X86::ADD64rr:
case X86::ADD32rr:
4290 case X86::ADD16rr:
case X86::ADD8rr:
case X86::ADD64rm:
4291 case X86::ADD32rm:
case X86::ADD16rm:
case X86::ADD8rm:
4292 case X86::INC64r:
case X86::INC32r:
case X86::INC16r:
case X86::INC8r:
4293 case X86::AND64ri32:
case X86::AND64ri8:
case X86::AND32ri:
4294 case X86::AND32ri8:
case X86::AND16ri:
case X86::AND16ri8:
4295 case X86::AND8ri:
case X86::AND64rr:
case X86::AND32rr:
4296 case X86::AND16rr:
case X86::AND8rr:
case X86::AND64rm:
4297 case X86::AND32rm:
case X86::AND16rm:
case X86::AND8rm:
4298 case X86::XOR64ri32:
case X86::XOR64ri8:
case X86::XOR32ri:
4299 case X86::XOR32ri8:
case X86::XOR16ri:
case X86::XOR16ri8:
4300 case X86::XOR8ri:
case X86::XOR64rr:
case X86::XOR32rr:
4301 case X86::XOR16rr:
case X86::XOR8rr:
case X86::XOR64rm:
4302 case X86::XOR32rm:
case X86::XOR16rm:
case X86::XOR8rm:
4303 case X86::OR64ri32:
case X86::OR64ri8:
case X86::OR32ri:
4304 case X86::OR32ri8:
case X86::OR16ri:
case X86::OR16ri8:
4305 case X86::OR8ri:
case X86::OR64rr:
case X86::OR32rr:
4306 case X86::OR16rr:
case X86::OR8rr:
case X86::OR64rm:
4307 case X86::OR32rm:
case X86::OR16rm:
case X86::OR8rm:
4308 case X86::NEG8r:
case X86::NEG16r:
case X86::NEG32r:
case X86::NEG64r:
4309 case X86::SAR8r1:
case X86::SAR16r1:
case X86::SAR32r1:
case X86::SAR64r1:
4310 case X86::SHR8r1:
case X86::SHR16r1:
case X86::SHR32r1:
case X86::SHR64r1:
4311 case X86::SHL8r1:
case X86::SHL16r1:
case X86::SHL32r1:
case X86::SHL64r1:
4312 case X86::ADC32ri:
case X86::ADC32ri8:
4313 case X86::ADC32rr:
case X86::ADC64ri32:
4314 case X86::ADC64ri8:
case X86::ADC64rr:
4315 case X86::SBB32ri:
case X86::SBB32ri8:
4316 case X86::SBB32rr:
case X86::SBB64ri32:
4317 case X86::SBB64ri8:
case X86::SBB64rr:
4318 case X86::ANDN32rr:
case X86::ANDN32rm:
4319 case X86::ANDN64rr:
case X86::ANDN64rm:
4320 case X86::BEXTR32rr:
case X86::BEXTR64rr:
4321 case X86::BEXTR32rm:
case X86::BEXTR64rm:
4322 case X86::BLSI32rr:
case X86::BLSI32rm:
4323 case X86::BLSI64rr:
case X86::BLSI64rm:
4324 case X86::BLSMSK32rr:
case X86::BLSMSK32rm:
4325 case X86::BLSMSK64rr:
case X86::BLSMSK64rm:
4326 case X86::BLSR32rr:
case X86::BLSR32rm:
4327 case X86::BLSR64rr:
case X86::BLSR64rm:
4328 case X86::BZHI32rr:
case X86::BZHI32rm:
4329 case X86::BZHI64rr:
case X86::BZHI64rm:
4330 case X86::LZCNT16rr:
case X86::LZCNT16rm:
4331 case X86::LZCNT32rr:
case X86::LZCNT32rm:
4332 case X86::LZCNT64rr:
case X86::LZCNT64rm:
4333 case X86::POPCNT16rr:
case X86::POPCNT16rm:
4334 case X86::POPCNT32rr:
case X86::POPCNT32rm:
4335 case X86::POPCNT64rr:
case X86::POPCNT64rm:
4336 case X86::TZCNT16rr:
case X86::TZCNT16rm:
4337 case X86::TZCNT32rr:
case X86::TZCNT32rm:
4338 case X86::TZCNT64rr:
case X86::TZCNT64rm:
4347 case X86::LZCNT16rr:
case X86::LZCNT16rm:
4348 case X86::LZCNT32rr:
case X86::LZCNT32rm:
4349 case X86::LZCNT64rr:
case X86::LZCNT64rm:
4351 case X86::POPCNT16rr:
case X86::POPCNT16rm:
4352 case X86::POPCNT32rr:
case X86::POPCNT32rm:
4353 case X86::POPCNT64rr:
case X86::POPCNT64rm:
4355 case X86::TZCNT16rr:
case X86::TZCNT16rm:
4356 case X86::TZCNT32rr:
case X86::TZCNT32rm:
4357 case X86::TZCNT64rr:
case X86::TZCNT64rm:
4367 int CmpMask,
int CmpValue,
4370 unsigned NewOpcode = 0;
4373 case X86::SUB64ri32:
4393 case X86::SUB64rm: NewOpcode = X86::CMP64rm;
break;
4394 case X86::SUB32rm: NewOpcode = X86::CMP32rm;
break;
4395 case X86::SUB16rm: NewOpcode = X86::CMP16rm;
break;
4396 case X86::SUB8rm: NewOpcode = X86::CMP8rm;
break;
4397 case X86::SUB64rr: NewOpcode = X86::CMP64rr;
break;
4398 case X86::SUB32rr: NewOpcode = X86::CMP32rr;
break;
4399 case X86::SUB16rr: NewOpcode = X86::CMP16rr;
break;
4400 case X86::SUB8rr: NewOpcode = X86::CMP8rr;
break;
4401 case X86::SUB64ri32: NewOpcode = X86::CMP64ri32;
break;
4402 case X86::SUB64ri8: NewOpcode = X86::CMP64ri8;
break;
4403 case X86::SUB32ri: NewOpcode = X86::CMP32ri;
break;
4404 case X86::SUB32ri8: NewOpcode = X86::CMP32ri8;
break;
4405 case X86::SUB16ri: NewOpcode = X86::CMP16ri;
break;
4406 case X86::SUB16ri8: NewOpcode = X86::CMP16ri8;
break;
4407 case X86::SUB8ri: NewOpcode = X86::CMP8ri;
break;
4409 CmpInstr->
setDesc(
get(NewOpcode));
4412 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
4413 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
4420 if (!MI)
return false;
4427 bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0);
4434 bool ShouldUpdateCC =
false;
4443 J->getOperand(1).getReg() == SrcReg) {
4444 assert(J->definesRegister(X86::EFLAGS) &&
"Must be an EFLAGS def!");
4445 ShouldUpdateCC =
true;
4473 for (; RI != RE; ++RI) {
4489 if (!Movr0Inst && Instr->
getOpcode() == X86::MOV32r0 &&
4501 if (!IsCmpZero && !Sub)
4504 bool IsSwapped = (SrcReg2 != 0 && Sub->
getOperand(1).
getReg() == SrcReg2 &&
4511 bool IsSafe =
false;
4514 for (++I; I != E; ++
I) {
4515 const MachineInstr &Instr = *
I;
4519 if (!UseEFLAGS && ModifyEFLAGS) {
4524 if (!UseEFLAGS && !ModifyEFLAGS)
4529 bool OpcIsSET =
false;
4530 if (IsCmpZero || IsSwapped) {
4567 }
else if (IsSwapped) {
4575 if ((ShouldUpdateCC || IsSwapped) && NewCC != OldCC) {
4592 OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
4594 if (ModifyEFLAGS || Instr.
killsRegister(X86::EFLAGS, TRI)) {
4603 if ((IsCmpZero || IsSwapped) && !IsSafe) {
4607 if ((*SI)->isLiveIn(X86::EFLAGS))
4612 Sub = IsCmpZero ? MI : Sub;
4620 for (; InsertI != InsertE; ++InsertI) {
4621 MachineInstr *Instr = &*InsertI;
4630 if (InsertI == InsertE)
4636 for (; i != e; ++i) {
4643 assert(i != e &&
"Unable to locate a def EFLAGS operand");
4648 for (
unsigned i = 0, e = OpsToUpdate.size(); i < e; i++)
4649 OpsToUpdate[i].first->setDesc(
get(OpsToUpdate[i].second));
4659 unsigned &FoldAsLoadDefReg,
4661 if (FoldAsLoadDefReg == 0)
4665 FoldAsLoadDefReg = 0;
4677 unsigned SrcOperandId = 0;
4678 bool FoundSrcOperand =
false;
4684 if (Reg != FoldAsLoadDefReg)
4691 FoundSrcOperand =
true;
4693 if (!FoundSrcOperand)
4697 MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandId, DefMI);
4699 FoldAsLoadDefReg = 0;
4715 assert(Desc.
getNumOperands() == 3 &&
"Expected two-addr instruction.");
4751 bool HasAVX = Subtarget.
hasAVX();
4753 switch (MI->getOpcode()) {
4758 case X86::SETB_C16r:
4760 case X86::SETB_C32r:
4762 case X86::SETB_C64r:
4769 assert(HasAVX &&
"AVX not supported");
4771 case X86::AVX512_512_SET0:
4773 case X86::V_SETALLONES:
4774 return Expand2AddrUndef(MIB,
get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
4775 case X86::AVX2_SETALLONES:
4777 case X86::TEST8ri_NOREX:
4778 MI->setDesc(
get(X86::TEST8ri));
4792 unsigned NumAddrOps = MOs.
size();
4793 for (
unsigned i = 0; i != NumAddrOps; ++i)
4813 for (
unsigned i = 0; i != NumOps; ++i) {
4817 for (
unsigned i = NumOps+2, e = MI->
getNumOperands(); i != e; ++i) {
4823 MBB->
insert(InsertPt, NewMI);
4840 assert(MO.
isReg() &&
"Expected to fold into reg operand!");
4848 MBB->
insert(InsertPt, NewMI);
4866 unsigned Size,
unsigned Align,
bool AllowCommute)
const {
4868 std::pair<unsigned,unsigned> > *OpcodeTablePtr =
nullptr;
4870 bool isTwoAddrFold =
false;
4874 if (isCallRegIndirect &&
4879 bool isTwoAddr = NumOps > 1 &&
4892 if (isTwoAddr && NumOps >= 2 && OpNum < 2 &&
4896 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
4897 isTwoAddrFold =
true;
4898 }
else if (OpNum == 0) {
4900 NewMI =
MakeM0Inst(*
this, X86::MOV32mi, MOs, InsertPt, MI);
4905 OpcodeTablePtr = &RegOp2MemOpTable0;
4906 }
else if (OpNum == 1) {
4907 OpcodeTablePtr = &RegOp2MemOpTable1;
4908 }
else if (OpNum == 2) {
4909 OpcodeTablePtr = &RegOp2MemOpTable2;
4910 }
else if (OpNum == 3) {
4911 OpcodeTablePtr = &RegOp2MemOpTable3;
4912 }
else if (OpNum == 4) {
4913 OpcodeTablePtr = &RegOp2MemOpTable4;
4917 if (OpcodeTablePtr) {
4921 if (I != OpcodeTablePtr->
end()) {
4922 unsigned Opcode = I->second.first;
4924 if (Align < MinAlign)
4926 bool NarrowToMOV32rm =
false;
4929 if (Size < RCSize) {
4932 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
4939 Opcode = X86::MOV32rm;
4940 NarrowToMOV32rm =
true;
4947 NewMI =
FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *
this);
4949 if (NarrowToMOV32rm) {
4966 unsigned OriginalOpIdx = OpNum, CommuteOpIdx1, CommuteOpIdx2;
4979 if ((HasDef && Reg0 == Reg1 && Tied0) ||
4980 (HasDef && Reg0 == Reg2 && Tied1))
4983 if ((CommuteOpIdx1 == OriginalOpIdx) ||
4984 (CommuteOpIdx2 == OriginalOpIdx)) {
4990 if (CommutedMI != MI) {
4997 unsigned CommuteOp =
4998 (CommuteOpIdx1 == OriginalOpIdx ? CommuteOpIdx2 : CommuteOpIdx1);
5007 if (!UncommutedMI) {
5011 if (UncommutedMI != MI) {
5025 dbgs() <<
"We failed to fuse operand " << OpNum <<
" in " << *
MI;
5047 case X86::CVTSI2SSrr:
5048 case X86::CVTSI2SSrm:
5049 case X86::CVTSI2SS64rr:
5050 case X86::CVTSI2SS64rm:
5051 case X86::CVTSI2SDrr:
5052 case X86::CVTSI2SDrm:
5053 case X86::CVTSI2SD64rr:
5054 case X86::CVTSI2SD64rm:
5055 case X86::CVTSD2SSrr:
5056 case X86::CVTSD2SSrm:
5057 case X86::Int_CVTSD2SSrr:
5058 case X86::Int_CVTSD2SSrm:
5059 case X86::CVTSS2SDrr:
5060 case X86::CVTSS2SDrm:
5061 case X86::Int_CVTSS2SDrr:
5062 case X86::Int_CVTSS2SDrm:
5065 case X86::RCPSSr_Int:
5066 case X86::RCPSSm_Int:
5069 case X86::ROUNDSDr_Int:
5072 case X86::ROUNDSSr_Int:
5075 case X86::RSQRTSSr_Int:
5076 case X86::RSQRTSSm_Int:
5079 case X86::SQRTSSr_Int:
5080 case X86::SQRTSSm_Int:
5083 case X86::SQRTSDr_Int:
5084 case X86::SQRTSDm_Int:
5120 case X86::VCVTSI2SSrr:
5121 case X86::VCVTSI2SSrm:
5122 case X86::Int_VCVTSI2SSrr:
5123 case X86::Int_VCVTSI2SSrm:
5124 case X86::VCVTSI2SS64rr:
5125 case X86::VCVTSI2SS64rm:
5126 case X86::Int_VCVTSI2SS64rr:
5127 case X86::Int_VCVTSI2SS64rm:
5128 case X86::VCVTSI2SDrr:
5129 case X86::VCVTSI2SDrm:
5130 case X86::Int_VCVTSI2SDrr:
5131 case X86::Int_VCVTSI2SDrm:
5132 case X86::VCVTSI2SD64rr:
5133 case X86::VCVTSI2SD64rm:
5134 case X86::Int_VCVTSI2SD64rr:
5135 case X86::Int_VCVTSI2SD64rm:
5136 case X86::VCVTSD2SSrr:
5137 case X86::VCVTSD2SSrm:
5138 case X86::Int_VCVTSD2SSrr:
5139 case X86::Int_VCVTSD2SSrm:
5140 case X86::VCVTSS2SDrr:
5141 case X86::VCVTSS2SDrm:
5142 case X86::Int_VCVTSS2SDrr:
5143 case X86::Int_VCVTSS2SDrm:
5146 case X86::VRCPSSm_Int:
5147 case X86::VROUNDSDr:
5148 case X86::VROUNDSDm:
5149 case X86::VROUNDSDr_Int:
5150 case X86::VROUNDSSr:
5151 case X86::VROUNDSSm:
5152 case X86::VROUNDSSr_Int:
5153 case X86::VRSQRTSSr:
5154 case X86::VRSQRTSSm:
5155 case X86::VRSQRTSSm_Int:
5158 case X86::VSQRTSSm_Int:
5161 case X86::VSQRTSDm_Int:
5163 case X86::VCVTSD2SSZrr:
5164 case X86::VCVTSD2SSZrm:
5165 case X86::VCVTSS2SDZrr:
5166 case X86::VCVTSS2SDZrm:
5207 unsigned Reg = MI->getOperand(OpNum).getReg();
5209 if (MI->killsRegister(Reg, TRI))
5211 if (X86::VR128RegClass.
contains(Reg)) {
5214 bool HasAVX = Subtarget.
hasAVX();
5215 unsigned Opc = HasAVX ? X86::VXORPSrr : X86::XORPSrr;
5216 BuildMI(*MI->getParent(),
MI, MI->getDebugLoc(),
get(Opc), Reg)
5218 }
else if (X86::VR256RegClass.
contains(Reg)) {
5221 unsigned XReg = TRI->
getSubReg(Reg, X86::sub_xmm);
5222 BuildMI(*MI->getParent(),
MI, MI->getDebugLoc(),
get(X86::VXORPSrr), XReg)
5250 if (Ops.
size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5251 unsigned NewOpc = 0;
5252 unsigned RCSize = 0;
5254 default:
return nullptr;
5255 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1;
break;
5256 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2;
break;
5257 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4;
break;
5258 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8;
break;
5267 }
else if (Ops.
size() != 1)
5272 Size, Alignment,
true);
5297 if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm) && RegSize > 4) {
5302 case X86::ADDSSrr_Int:
case X86::VADDSSrr_Int:
5303 case X86::DIVSSrr_Int:
case X86::VDIVSSrr_Int:
5304 case X86::MULSSrr_Int:
case X86::VMULSSrr_Int:
5305 case X86::SUBSSrr_Int:
case X86::VSUBSSrr_Int:
5312 if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm) && RegSize > 8) {
5317 case X86::ADDSDrr_Int:
case X86::VADDSDrr_Int:
5318 case X86::DIVSDrr_Int:
case X86::VDIVSDrr_Int:
5319 case X86::MULSDrr_Int:
case X86::VMULSDrr_Int:
5320 case X86::SUBSDrr_Int:
case X86::VSUBSDrr_Int:
5352 unsigned Alignment = 0;
5357 case X86::AVX2_SETALLONES:
5362 case X86::V_SETALLONES:
5374 if (Ops.
size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5375 unsigned NewOpc = 0;
5377 default:
return nullptr;
5378 case X86::TEST8rr: NewOpc = X86::CMP8ri;
break;
5379 case X86::TEST16rr: NewOpc = X86::CMP16ri8;
break;
5380 case X86::TEST32rr: NewOpc = X86::CMP32ri8;
break;
5381 case X86::TEST64rr: NewOpc = X86::CMP64ri8;
break;
5386 }
else if (Ops.
size() != 1)
5397 case X86::V_SETALLONES:
5398 case X86::AVX2_SETALLONES:
5401 case X86::FsFLD0SS: {
5411 unsigned PICBase = 0;
5427 if (Opc == X86::FsFLD0SS)
5429 else if (Opc == X86::FsFLD0SD)
5431 else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0)
5436 bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES);
5460 0, Alignment,
true);
5468 if (Ops.
size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5470 default:
return false;
5485 if (Ops.
size() != 1)
5488 unsigned OpNum = Ops[0];
5491 bool isTwoAddr = NumOps > 1 &&
5498 std::pair<unsigned,unsigned> > *OpcodeTablePtr =
nullptr;
5499 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
5500 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
5501 }
else if (OpNum == 0) {
5502 if (Opc == X86::MOV32r0)
5505 OpcodeTablePtr = &RegOp2MemOpTable0;
5506 }
else if (OpNum == 1) {
5507 OpcodeTablePtr = &RegOp2MemOpTable1;
5508 }
else if (OpNum == 2) {
5509 OpcodeTablePtr = &RegOp2MemOpTable2;
5510 }
else if (OpNum == 3) {
5511 OpcodeTablePtr = &RegOp2MemOpTable3;
5514 if (OpcodeTablePtr && OpcodeTablePtr->count(Opc))
5520 unsigned Reg,
bool UnfoldLoad,
bool UnfoldStore,
5524 if (I == MemOp2RegOpTable.
end())
5526 unsigned Opc = I->second.first;
5530 if (UnfoldLoad && !FoldedLoad)
5532 UnfoldLoad &= FoldedLoad;
5533 if (UnfoldStore && !FoldedStore)
5535 UnfoldStore &= FoldedStore;
5540 RC == &X86::VR128RegClass &&
5565 MachineInstr::mmo_iterator> MMOs =
5568 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
5585 for (
unsigned i = 0, e = BeforeOps.
size(); i != e; ++i)
5589 for (
unsigned i = 0, e = AfterOps.
size(); i != e; ++i)
5591 for (
unsigned i = 0, e = ImpOps.
size(); i != e; ++i) {
5603 case X86::CMP64ri32:
5617 case X86::CMP64ri32: NewOpc = X86::TEST64rr;
break;
5619 case X86::CMP32ri: NewOpc = X86::TEST32rr;
break;
5621 case X86::CMP16ri: NewOpc = X86::TEST16rr;
break;
5622 case X86::CMP8ri: NewOpc = X86::TEST8rr;
break;
5635 MachineInstr::mmo_iterator> MMOs =
5638 storeRegToAddr(MF, Reg,
true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
5652 if (I == MemOp2RegOpTable.
end())
5654 unsigned Opc = I->second.first;
5661 unsigned NumDefs = MCID.
NumDefs;
5662 std::vector<SDValue> AddrOps;
5663 std::vector<SDValue> BeforeOps;
5664 std::vector<SDValue> AfterOps;
5667 for (
unsigned i = 0; i != NumOps-1; ++i) {
5670 AddrOps.push_back(Op);
5671 else if (i < Index-NumDefs)
5672 BeforeOps.push_back(Op);
5673 else if (i > Index-NumDefs)
5674 AfterOps.push_back(Op);
5677 AddrOps.push_back(Chain);
5684 MachineInstr::mmo_iterator> MMOs =
5686 cast<MachineSDNode>(N)->memoperands_end());
5687 if (!(*MMOs.first) &&
5688 RC == &X86::VR128RegClass &&
5692 unsigned Alignment = RC->
getSize() == 32 ? 32 : 16;
5693 bool isAligned = (*MMOs.first) &&
5694 (*MMOs.first)->getAlignment() >= Alignment;
5700 cast<MachineSDNode>(
Load)->setMemRefs(MMOs.first, MMOs.second);
5704 std::vector<EVT> VTs;
5710 for (
unsigned i = 0, e = N->
getNumValues(); i != e; ++i) {
5716 BeforeOps.push_back(
SDValue(Load, 0));
5717 BeforeOps.insert(BeforeOps.end(), AfterOps.begin(), AfterOps.end());
5724 AddrOps.push_back(
SDValue(NewNode, 0));
5725 AddrOps.push_back(Chain);
5727 MachineInstr::mmo_iterator> MMOs =
5729 cast<MachineSDNode>(N)->memoperands_end());
5730 if (!(*MMOs.first) &&
5731 RC == &X86::VR128RegClass &&
5735 unsigned Alignment = RC->
getSize() == 32 ? 32 : 16;
5736 bool isAligned = (*MMOs.first) &&
5737 (*MMOs.first)->getAlignment() >= Alignment;
5744 cast<MachineSDNode>(
Store)->setMemRefs(MMOs.first, MMOs.second);
5751 bool UnfoldLoad,
bool UnfoldStore,
5752 unsigned *LoadRegIndex)
const {
5754 MemOp2RegOpTable.
find(Opc);
5755 if (I == MemOp2RegOpTable.
end())
5759 if (UnfoldLoad && !FoldedLoad)
5761 if (UnfoldStore && !FoldedStore)
5765 return I->second.first;
5770 int64_t &Offset1, int64_t &Offset2)
const {
5776 default:
return false;
5786 case X86::MMX_MOVD64rm:
5787 case X86::MMX_MOVQ64rm:
5788 case X86::FsMOVAPSrm:
5789 case X86::FsMOVAPDrm:
5798 case X86::FsVMOVAPSrm:
5799 case X86::FsVMOVAPDrm:
5800 case X86::VMOVAPSrm:
5801 case X86::VMOVUPSrm:
5802 case X86::VMOVAPDrm:
5803 case X86::VMOVDQArm:
5804 case X86::VMOVDQUrm:
5805 case X86::VMOVAPSYrm:
5806 case X86::VMOVUPSYrm:
5807 case X86::VMOVAPDYrm:
5808 case X86::VMOVDQAYrm:
5809 case X86::VMOVDQUYrm:
5813 default:
return false;
5823 case X86::MMX_MOVD64rm:
5824 case X86::MMX_MOVQ64rm:
5825 case X86::FsMOVAPSrm:
5826 case X86::FsMOVAPDrm:
5835 case X86::FsVMOVAPSrm:
5836 case X86::FsVMOVAPDrm:
5837 case X86::VMOVAPSrm:
5838 case X86::VMOVUPSrm:
5839 case X86::VMOVAPDrm:
5840 case X86::VMOVDQArm:
5841 case X86::VMOVDQUrm:
5842 case X86::VMOVAPSYrm:
5843 case X86::VMOVUPSYrm:
5844 case X86::VMOVAPDYrm:
5845 case X86::VMOVDQAYrm:
5846 case X86::VMOVDQUYrm:
5860 if (cast<ConstantSDNode>(Load1->
getOperand(1))->getZExtValue() != 1)
5864 if (isa<ConstantSDNode>(Load1->
getOperand(3)) &&
5866 Offset1 = cast<ConstantSDNode>(Load1->
getOperand(3))->getSExtValue();
5867 Offset2 = cast<ConstantSDNode>(Load2->
getOperand(3))->getSExtValue();
5875 int64_t Offset1, int64_t Offset2,
5876 unsigned NumLoads)
const {
5877 assert(Offset2 > Offset1);
5878 if ((Offset2 - Offset1) / 8 > 64)
5891 case X86::MMX_MOVD64rm:
5892 case X86::MMX_MOVQ64rm:
5904 }
else if (NumLoads) {
5959 FuseKind = FuseTest;
5972 case X86::TEST32i32:
5973 case X86::TEST64i32:
5974 case X86::TEST64ri32:
5979 case X86::TEST8ri_NOREX:
5991 case X86::AND64ri32:
6011 case X86::CMP64ri32:
6022 case X86::ADD16ri8_DB:
6023 case X86::ADD16ri_DB:
6026 case X86::ADD16rr_DB:
6030 case X86::ADD32ri8_DB:
6031 case X86::ADD32ri_DB:
6034 case X86::ADD32rr_DB:
6036 case X86::ADD64ri32:
6037 case X86::ADD64ri32_DB:
6039 case X86::ADD64ri8_DB:
6042 case X86::ADD64rr_DB:
6060 case X86::SUB64ri32:
6068 return FuseKind == FuseCmp || FuseKind == FuseInc;
6077 return FuseKind == FuseInc;
6083 assert(Cond.
size() == 1 &&
"Invalid X86 branch condition!");
6095 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
6096 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
6106 assert(!Subtarget.
is64Bit() &&
6107 "X86-64 PIC uses RIP relative addressing");
6111 if (GlobalBaseReg != 0)
6118 X86FI->setGlobalBaseReg(GlobalBaseReg);
6127 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr },
6128 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm },
6129 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr },
6130 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr },
6131 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm },
6132 { X86::MOVLPSmr, X86::MOVLPDmr, X86::MOVPQI2QImr },
6133 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr },
6134 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm },
6135 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr },
6136 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm },
6137 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
6138 { X86::ORPSrm, X86::ORPDrm, X86::PORrm },
6139 { X86::ORPSrr, X86::ORPDrr, X86::PORrr },
6140 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
6141 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
6143 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr },
6144 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm },
6145 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr },
6146 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr },
6147 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm },
6148 { X86::VMOVLPSmr, X86::VMOVLPDmr, X86::VMOVPQI2QImr },
6149 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
6150 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm },
6151 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr },
6152 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm },
6153 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr },
6154 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm },
6155 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr },
6156 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm },
6157 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr },
6159 { X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr },
6160 { X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm },
6161 { X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr },
6162 { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr },
6163 { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm },
6164 { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr }
6169 { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNYrm },
6170 { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNYrr },
6171 { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDYrm },
6172 { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDYrr },
6173 { X86::VORPSYrm, X86::VORPDYrm, X86::VPORYrm },
6174 { X86::VORPSYrr, X86::VORPDYrr, X86::VPORYrr },
6175 { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORYrm },
6176 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORYrr },
6177 { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
6178 { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
6179 { X86::VINSERTF128rm, X86::VINSERTF128rm, X86::VINSERTI128rm },
6180 { X86::VINSERTF128rr, X86::VINSERTF128rr, X86::VINSERTI128rr },
6181 { X86::VPERM2F128rm, X86::VPERM2F128rm, X86::VPERM2I128rm },
6182 { X86::VPERM2F128rr, X86::VPERM2F128rr, X86::VPERM2I128rr },
6183 { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
6184 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
6185 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
6186 { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
6187 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
6188 { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm}
6194 static const uint16_t *
lookup(
unsigned opcode,
unsigned domain) {
6195 for (
unsigned i = 0, e =
array_lengthof(ReplaceableInstrs); i != e; ++i)
6196 if (ReplaceableInstrs[i][domain-1] == opcode)
6197 return ReplaceableInstrs[i];
6201 static const uint16_t *
lookupAVX2(
unsigned opcode,
unsigned domain) {
6202 for (
unsigned i = 0, e =
array_lengthof(ReplaceableInstrsAVX2); i != e; ++i)
6203 if (ReplaceableInstrsAVX2[i][domain-1] == opcode)
6204 return ReplaceableInstrsAVX2[i];
6208 std::pair<uint16_t, uint16_t>
6211 bool hasAVX2 = Subtarget.
hasAVX2();
6212 uint16_t validDomains = 0;
6216 validDomains = hasAVX2 ? 0xe : 0x6;
6217 return std::make_pair(domain, validDomains);
6221 assert(Domain>0 && Domain<4 &&
"Invalid execution domain");
6223 assert(dom &&
"Not an SSE instruction");
6226 assert((Subtarget.
hasAVX2() || Domain < 3) &&
6227 "256-bit vector operations only available in AVX2");
6230 assert(table &&
"Cannot change domain");
6231 MI->
setDesc(
get(table[Domain-1]));
6267 default:
return false;
6269 case X86::DIVSDrm_Int:
6271 case X86::DIVSDrr_Int:
6273 case X86::DIVSSrm_Int:
6275 case X86::DIVSSrr_Int:
6281 case X86::SQRTSDm_Int:
6283 case X86::SQRTSDr_Int:
6285 case X86::SQRTSSm_Int:
6287 case X86::SQRTSSr_Int:
6290 case X86::VDIVSDrm_Int:
6292 case X86::VDIVSDrr_Int:
6294 case X86::VDIVSSrm_Int:
6296 case X86::VDIVSSrr_Int:
6302 case X86::VSQRTSDm_Int:
6305 case X86::VSQRTSSm_Int:
6307 case X86::VSQRTPDZm:
6308 case X86::VSQRTPDZr:
6309 case X86::VSQRTPSZm:
6310 case X86::VSQRTPSZr:
6311 case X86::VSQRTSDZm:
6312 case X86::VSQRTSDZm_Int:
6313 case X86::VSQRTSDZr:
6314 case X86::VSQRTSSZm_Int:
6315 case X86::VSQRTSSZr:
6316 case X86::VSQRTSSZm:
6317 case X86::VDIVSDZrm:
6318 case X86::VDIVSDZrr:
6319 case X86::VDIVSSZrm:
6320 case X86::VDIVSSZrr:
6322 case X86::VGATHERQPSZrm:
6323 case X86::VGATHERQPDZrm:
6324 case X86::VGATHERDPDZrm:
6325 case X86::VGATHERDPSZrm:
6326 case X86::VPGATHERQDZrm:
6327 case X86::VPGATHERQQZrm:
6328 case X86::VPGATHERDDZrm:
6329 case X86::VPGATHERDQZrm:
6330 case X86::VSCATTERQPDZmr:
6331 case X86::VSCATTERQPSZmr:
6332 case X86::VSCATTERDPDZmr:
6333 case X86::VSCATTERDPSZmr:
6334 case X86::VPSCATTERQDZmr:
6335 case X86::VPSCATTERQQZmr:
6336 case X86::VPSCATTERDDZmr:
6337 case X86::VPSCATTERDQZmr:
6352 assert(Inst.
getNumOperands() == 3 &&
"Reassociation needs binary operators");
6377 unsigned AssocOpcode = Inst.
getOpcode();
6492 unsigned OpIdx[4][4] = {
6505 unsigned RegA = OpA.
getReg();
6506 unsigned RegB = OpB.
getReg();
6507 unsigned RegX = OpX.
getReg();
6508 unsigned RegY = OpY.
getReg();
6509 unsigned RegC = OpC.
getReg();
6526 InstrIdxForVirtReg.
insert(std::make_pair(NewVR, 0));
6529 bool KillA = OpA.
isKill();
6530 bool KillX = OpX.
isKill();
6531 bool KillY = OpY.
isKill();
6570 assert(Prev &&
"Unknown pattern for machine combiner");
6572 reassociateOps(Root, *Prev, Pattern, InsInstrs, DelInstrs, InstIdxForVirtReg);
6601 if (GlobalBaseReg == 0)
6619 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
6633 const char *getPassName()
const override {
6634 return "X86 PIC Global Base Reg Initialization";
6671 bool Changed =
false;
6676 switch (I->getOpcode()) {
6677 case X86::TLS_base_addr32:
6678 case X86::TLS_base_addr64:
6680 I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg);
6682 I = SetRegister(I, &TLSBaseAddrReg);
6693 Changed |= VisitNode(*I, TLSBaseAddrReg);
6702 unsigned TLSBaseAddrReg) {
6711 is64Bit ? X86::RAX : X86::EAX)
6712 .addReg(TLSBaseAddrReg);
6725 const bool is64Bit = STI.
is64Bit();
6731 ? &X86::GR64RegClass
6732 : &X86::GR32RegClass);
6739 .addReg(is64Bit ? X86::RAX : X86::EAX);
6744 const char *getPassName()
const override {
6745 return "Local Dynamic TLS Access Clean-up";
static MachineInstr * MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode, ArrayRef< MachineOperand > MOs, MachineBasicBlock::iterator InsertPt, MachineInstr *MI)
const X86RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
unsigned GetCondBranchFromCond(CondCode CC)
void push_back(const T &Elt)
The memory access reads data.
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
static bool hasUndefRegUpdate(unsigned Opcode)
static Type * getDoubleTy(LLVMContext &C)
MachineInstr * CreateMachineInstr(const MCInstrDesc &MCID, DebugLoc DL, bool NoImp=false)
CreateMachineInstr - Allocate a new MachineInstr.
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SubIdx, const MachineInstr *Orig, const TargetRegisterInfo &TRI) const override
static MachineInstr * FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode, ArrayRef< MachineOperand > MOs, MachineBasicBlock::iterator InsertPt, MachineInstr *MI, const TargetInstrInfo &TII)
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI)
Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, MachineInstr::mmo_iterator MMOBegin, MachineInstr::mmo_iterator MMOEnd, SmallVectorImpl< MachineInstr * > &NewMIs) const
static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg, const X86Subtarget &Subtarget)
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are lo...
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
const X86InstrInfo * getInstrInfo() const override
static MCOperand createExpr(const MCExpr *Val)
void setExecutionDomain(MachineInstr *MI, unsigned Domain) const override
CondCode getCondFromCMovOpc(unsigned Opc)
Return condition code of a CMov opcode.
MachineDomTreeNode * getRootNode() const
static void addOperands(MachineInstrBuilder &MIB, ArrayRef< MachineOperand > MOs)
const X86FrameLowering * getFrameLowering() const override
Describe properties that are true of each instruction in the target description file.
static MachineInstr * FuseInst(MachineFunction &MF, unsigned Opcode, unsigned OpNo, ArrayRef< MachineOperand > MOs, MachineBasicBlock::iterator InsertPt, MachineInstr *MI, const TargetInstrInfo &TII)
bool isHighLatencyDef(int opc) const override
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const override
bool isPredicable(QueryType Type=AllInBundle) const
Return true if this instruction has a predicate operand that controls execution.
bool readsVirtualRegister(unsigned Reg) const
Return true if the MachineInstr reads the specified virtual register.
static cl::opt< bool > ReMatPICStubLoad("remat-pic-stub-load", cl::desc("Re-materialize load from stub in PIC mode"), cl::init(false), cl::Hidden)
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex) const override
foldMemoryOperand - If this target supports it, fold a load or store of the specified stack slot into...
bool use_nodbg_empty(unsigned RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register...
static X86::CondCode getCondFromBranchOpc(unsigned BrOpc)
static unsigned getLoadRegOpcode(unsigned DestReg, const TargetRegisterClass *RC, bool isStackAligned, const X86Subtarget &STI)
static void reassociateOps(MachineInstr &Root, MachineInstr &Prev, MachineCombinerPattern::MC_PATTERN Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg)
Attempt the following reassociation to reduce critical path length: B = A op X (Prev) C = B op Y (Roo...
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
unsigned getNumOperands() const
Return the number of values used by this operation.
int getOperandBias(const MCInstrDesc &Desc)
getOperandBias - compute any additional adjustment needed to the offset to the start of the memory op...
const SDValue & getOperand(unsigned Num) const
void setIsDead(bool Val=true)
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...
unsigned getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum, const TargetRegisterInfo *TRI) const override
Inform the ExeDepsFix pass how many idle instructions we would like before certain undef register rea...
int getSPAdjust(const MachineInstr *MI) const override
getSPAdjust - This returns the stack pointer adjustment made by this instruction. ...
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern::MC_PATTERN > &P) const override
Return true when there is potentially a faster code sequence for an instruction chain ending in <Root...
iterator_range< succ_iterator > successors()
static Constant * getNullValue(Type *Ty)
GlobalBaseReg - On Darwin, this node represents the result of the mflr at function entry...
X86MachineFunctionInfo - This class is derived from MachineFunction and contains private X86 target-s...
COPY - Target-independent register copy.
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
MachineInstr * optimizeLoadInstr(MachineInstr *MI, const MachineRegisterInfo *MRI, unsigned &FoldAsLoadDefReg, MachineInstr *&DefMI) const override
optimizeLoadInstr - Try to remove the load by folding it to a register operand at the use...
unsigned getSize() const
getSize - Return the size of the register in bytes, which is also the size of a stack slot allocated ...
AnalysisUsage & addRequired()
void eraseFromParent()
eraseFromParent - This method unlinks 'this' from the containing function and deletes it...
MachineMemOperand - A description of a memory reference used in the backend.
unsigned getJumpInstrTableEntryBound() const override
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static unsigned getLoadStoreRegOpcode(unsigned Reg, const TargetRegisterClass *RC, bool isStackAligned, const X86Subtarget &STI, bool load)
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Provide an instruction scheduling machine model to CodeGen passes.
std::vector< DomTreeNodeBase< NodeT > * >::iterator iterator
const HexagonInstrInfo * TII
static Type * getFloatTy(LLVMContext &C)
NodeTy * getNextNode()
Get the next node, or 0 for the list tail.
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false)
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isUnpredicatedTerminator(const MachineInstr *MI) const override
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
MachineFunction & getMachineFunction() const
void getTrap(MCInst &MI) const override
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void setImplicit(bool Val=true)
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
static bool hasPartialRegUpdate(unsigned Opcode)
Return true for all instructions that only update the first 32 or 64-bits of the destination register...
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
const TargetRegisterClass * getRegClass(unsigned Reg) const
getRegClass - Return the register class of the specified virtual register.
std::vector< MachineBasicBlock * >::iterator succ_iterator
Reg
All possible values of the reg field in the ModR/M byte.
MachineMemOperand ** mmo_iterator
void replaceKillInstruction(unsigned Reg, MachineInstr *OldMI, MachineInstr *NewMI)
replaceKillInstruction - Update register kill info by replacing a kill instruction with a new one...
unsigned getNumLocalDynamicTLSAccesses() const
Represent a reference to a symbol from inside an expression.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
Number of individual test Apply this number of consecutive mutations to each input exit after the first new interesting input is found the minimized corpus is saved into the first input directory Number of jobs to run If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
std::pair< MachineInstr::mmo_iterator, MachineInstr::mmo_iterator > extractLoadMemRefs(MachineInstr::mmo_iterator Begin, MachineInstr::mmo_iterator End)
extractLoadMemRefs - Allocate an array and populate it with just the load information from the given ...
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override
isCoalescableExtInstr - Return true if the instruction is a "coalescable" extension instruction...
bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override
isSafeToMoveRegClassDefs - Return true if it's safe to move a machine instruction that defines the sp...
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
bool hasHighOperandLatency(const TargetSchedModel &SchedModel, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const override
unsigned getNumOperands() const
Access to explicit operands of the instruction.
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
defusechain_iterator - This class provides iterator support for machine operands in the function that...
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
const MachineBasicBlock & front() const
AddrNumOperands - Total number of operands in a memory reference.
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const override
isStoreToStackSlotPostFE - Check for post-frame ptr elimination stack locations as well...
static X86::CondCode getCondFromSETOpc(unsigned Opc)
Return condition code of a SET opcode.
bool canRealignStack(const MachineFunction &MF) const
bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override
shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction w...
virtual MachineInstr * commuteInstruction(MachineInstr *MI, bool NewMI=false) const
If a target has any instructions that are commutable but require converting to different instructions...
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
static def_instr_iterator def_instr_end()
bool getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg, unsigned &Offset, const TargetRegisterInfo *TRI) const override
Base class for the actual dominator tree node.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
uint64_t getAlignment() const
getAlignment - Return the minimum known alignment in bytes of the actual memory reference.
bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const override
optimizeCompareInstr - Check if there exists an earlier instruction that operates on the same source ...
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
unsigned getX86SubSuperRegister(unsigned Reg, MVT::SimpleValueType VT, bool High)
Returns the sub or super register of a specific X86 register.
unsigned getUndefRegState(bool B)
LivenessQueryResult computeRegisterLiveness(const TargetRegisterInfo *TRI, unsigned Reg, const_iterator Before, unsigned Neighborhood=10) const
Return whether (physical) register Reg has been <def>ined and not <kill>ed as of just before Before...
size_t size() const
size - Get the array size.
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
reverse_iterator rbegin()
Instances of this class represent a single low-level machine instruction.
unsigned getKillRegState(bool B)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
Flag
These should be considered private to the implementation of the MCInstrDesc class.
const MachineBasicBlock * getParent() const
TargetInstrInfo - Interface to description of machine instruction set.
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
static bool hasVirtualRegDefsInBasicBlock(const MachineInstr &Inst, const MachineBasicBlock *MBB)
unsigned getDeadRegState(bool B)
mmo_iterator memoperands_end() const
unsigned getGlobalBaseReg() const
unsigned getDefRegState(bool B)
void genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern::MC_PATTERN P, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
When getMachineCombinerPatterns() finds a pattern, this function generates the instructions that coul...
IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
bundle_iterator< MachineInstr, instr_iterator > iterator
static bool isFrameLoadOpcode(int Opcode)
initializer< Ty > init(const Ty &Val)
unsigned getTargetFlags() const
const MachineInstrBuilder & setMemRefs(MachineInstr::mmo_iterator b, MachineInstr::mmo_iterator e) const
unsigned UnsafeFPMath
UnsafeFPMath - This flag is enabled when the -enable-unsafe-fp-math flag is specified on the command ...
void breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override
static bool isAssociativeAndCommutative(unsigned Opcode)
bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const override
analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if h...
static bool isDefConvertible(MachineInstr *MI)
Check whether the definition can be converted to remove a comparison against zero.
void getUnconditionalBranch(MCInst &Branch, const MCSymbolRefExpr *BranchTarget) const override
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
std::pair< uint16_t, uint16_t > getExecutionDomain(const MachineInstr *MI) const override
static bool isTruncatedShiftCountForLEA(unsigned ShAmt)
Check whether the given shift count is appropriate can be represented by a LEA instruction.
MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a relocation of: SYMBOL_LABEL + [...
static MachineOperand CreateCPI(unsigned Idx, int Offset, unsigned char TargetFlags=0)
CodeModel::Model getCodeModel() const
Returns the code model.
The instances of the Type class are immutable: once they are created, they are never changed...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
static const uint16_t ReplaceableInstrs[][3]
FunctionPass * createX86GlobalBaseRegPass()
createX86GlobalBaseRegPass - This pass initializes a global base register for PIC on x86-32...
unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const override
isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well...
This is an important base class in LLVM.
static void expandLoadStackGuard(MachineInstrBuilder &MIB, const TargetInstrInfo &TII)
static bool is64Bit(const char *name)
DebugLoc findDebugLoc(instr_iterator MBBI)
findDebugLoc - find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE instructions...
const MachineOperand & getOperand(unsigned i) const
unsigned get512BitSuperRegister(unsigned Reg)
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
static cl::opt< bool > PrintFailedFusing("print-failed-fuse-candidates", cl::desc("Print instructions that the allocator wants to"" fuse, but the X86 backend currently can't"), cl::Hidden)
This pseudo-instruction loads the stack guard value.
Represent the analysis usage information of a pass.
static const MachineInstrBuilder & addRegOffset(const MachineInstrBuilder &MIB, unsigned Reg, bool isKill, int Offset)
addRegOffset - This function is used to add a memory reference of the form [Reg + Offset]...
X86InstrInfo(X86Subtarget &STI)
static bool MaskRegClassContains(unsigned Reg)
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
void setImm(int64_t immVal)
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
TRAP - Trapping instruction.
FunctionPass class - This class is used to implement most global optimizations.
bool registerDefIsDead(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Returns true if the register is dead in this machine instruction.
unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const override
bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const override
unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a st...
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
bool empty() const
empty - Check if the array is empty.
static unsigned getTruncatedShiftCount(MachineInstr *MI, unsigned ShiftAmtOperandIdx)
Check whether the shift count for a machine operand is non-zero.
bool isInvariantLoad(AliasAnalysis *AA) const
Return true if this instruction is loading from a location whose value is invariant across the functi...
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
LivenessQueryResult
Possible outcome of a register liveness query to computeRegisterLiveness()
static Constant * getAllOnesValue(Type *Ty)
Get the all ones value.
unsigned RemoveBranch(MachineBasicBlock &MBB) const override
bool classifyLEAReg(MachineInstr *MI, const MachineOperand &Src, unsigned LEAOpcode, bool AllowSP, unsigned &NewSrc, bool &isKill, bool &isUndef, MachineOperand &ImplicitOp) const
Given an operand within a MachineInstr, insert preceding code to put it into the right format for a p...
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
Register is known to be live.
bool isPICStyleGOT() const
static unsigned GetCondBranchFromCond(XCore::CondCode CC)
GetCondBranchFromCond - Return the Branch instruction opcode that matches the cc. ...
succ_iterator succ_begin()
void append(in_iter in_start, in_iter in_end)
Add the specified range to the end of the SmallVector.
unsigned getSETFromCond(CondCode CC, bool HasMemoryOperand=false)
Return a set opcode for the given condition and whether it has a memory operand.
unsigned getSubReg() const
EVT - Extended Value Type.
VarInfo & getVarInfo(unsigned RegIdx)
getVarInfo - Return the VarInfo structure for the specified VIRTUAL register.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
The memory access is invariant.
static bool isHReg(unsigned Reg)
Test if the given register is a physical h register.
void setIsKill(bool Val=true)
bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const
isSafeToClobberEFLAGS - Return true if it's safe insert an instruction tha would clobber the EFLAGS c...
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
static unsigned getRegClass(bool IsVgpr, unsigned RegWidth)
bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
bool shouldScheduleAdjacent(MachineInstr *First, MachineInstr *Second) const override
std::vector< MachineInstr * > Kills
Kills - List of MachineInstruction's which are the last use of this virtual register (kill it) in the...
bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
virtual const TargetFrameLowering * getFrameLowering() const
static bool isRedundantFlagInstr(MachineInstr *FlagI, unsigned SrcReg, unsigned SrcReg2, int ImmValue, MachineInstr *OI)
Check whether the first instruction, whose only purpose is to update flags, can be made redundant...
void setOpcode(unsigned Op)
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const
If specified MI is commutable, return the two operand indices that would swap value.
bool canFoldMemoryOperand(const MachineInstr *, ArrayRef< unsigned >) const override
canFoldMemoryOperand - Returns true if the specified load / store is folding is possible.
MachineInstr * CloneMachineInstr(const MachineInstr *Orig)
CloneMachineInstr - Create a new MachineInstr which is a copy of the 'Orig' instruction, identical in all ways except the instruction has no parent, prev, or next.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
static unsigned copyPhysRegOpcode_AVX512(unsigned &DestReg, unsigned &SrcReg)
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
CondCode GetOppositeBranchCondition(CondCode CC)
GetOppositeBranchCondition - Return the inverse of the specified cond, e.g.
static const MachineInstrBuilder & addRegReg(const MachineInstrBuilder &MIB, unsigned Reg1, bool isKill1, unsigned Reg2, bool isKill2)
addRegReg - This function is used to add a memory reference of the form: [Reg + Reg].
Information about stack frame layout on the target.
unsigned getGlobalBaseReg(MachineFunction *MF) const
getGlobalBaseReg - Return a virtual register initialized with the the global base register value...
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, DebugLoc DL) const override
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Represents one node in the SelectionDAG.
MachineInstr * remove(MachineInstr *I)
Remove the unbundled instruction from the instruction list without deleting it.
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
void getNoopForMachoTarget(MCInst &NopInst) const override
Return the noop instruction to use for a noop.
MachineInstr * commuteInstruction(MachineInstr *MI, bool NewMI) const override
commuteInstruction - We have a few instructions that must be hacked on to commute them...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
MachineInstr * convertToThreeAddress(MachineFunction::iterator &MFI, MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const override
convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_AD...
void setDebugLoc(DebugLoc dl)
Replace current source information with new such.
static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI, const MachineInstr &UserMI, const MachineFunction &MF)
Check if LoadMI is a partial register load that we can't fold into MI because the latter uses content...
unsigned getCMovFromCond(CondCode CC, unsigned RegBytes, bool HasMemoryOperand=false)
Return a cmov opcode for the given condition, register size in bytes, and operand type...
bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI)
bool isUnalignedMemAccessFast() const
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned char TargetFlags=0) const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
static MachinePointerInfo getGOT()
getGOT - Return a MachinePointerInfo record that refers to a GOT entry.
Representation of each machine instruction.
uint64_t MinAlign(uint64_t A, uint64_t B)
MinAlign - A and B are either alignments or offsets.
bundle_iterator< const MachineInstr, const_instr_iterator > const_iterator
static const uint16_t * lookup(unsigned opcode, unsigned domain)
static bool isPhysicalRegister(unsigned Reg)
isPhysicalRegister - Return true if the specified register number is in the physical register namespa...
static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC)
bool AnalyzeBranchPredicate(MachineBasicBlock &MBB, TargetInstrInfo::MachineBranchPredicate &MBP, bool AllowModify=false) const override
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
def_instr_iterator def_instr_begin(unsigned RegNo) const
bool isLiveIn(unsigned Reg) const
isLiveIn - Return true if the specified register is in the live in set.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static IntegerType * getInt32Ty(LLVMContext &C)
static const MachineInstrBuilder & addOffset(const MachineInstrBuilder &MIB, int Offset)
static unsigned getStoreRegOpcode(unsigned SrcReg, const TargetRegisterClass *RC, bool isStackAligned, const X86Subtarget &STI)
Register liveness not decidable from local neighborhood.
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned char TargetFlags=0) const
unsigned getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override
Inform the ExeDepsFix pass how many idle instructions we would like before a partial register update...
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
void setReg(unsigned Reg)
Change the register this operand corresponds to.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
static MachineOperand CreateImm(int64_t Val)
bool isCall(QueryType Type=AnyInBundle) const
void setSubReg(unsigned subReg)
iterator find(const KeyT &Val)
bool needsStackRealignment(const MachineFunction &MF) const override
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
MachineSDNode * getMachineNode(unsigned Opcode, SDLoc dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s), MachineInstr opcode, and operands.
virtual bool canFoldMemoryOperand(const MachineInstr *MI, ArrayRef< unsigned > Ops) const
Returns true for the specified load / store if folding is possible.
void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, MachineInstr::mmo_iterator MMOBegin, MachineInstr::mmo_iterator MMOEnd, SmallVectorImpl< MachineInstr * > &NewMIs) const
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
unsigned getReg() const
getReg - Returns the register number.
std::pair< MachineInstr::mmo_iterator, MachineInstr::mmo_iterator > extractStoreMemRefs(MachineInstr::mmo_iterator Begin, MachineInstr::mmo_iterator End)
extractStoreMemRefs - Allocate an array and populate it with just the store information from the give...
bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr kills the specified register.
static X86::CondCode isUseDefConvertible(MachineInstr *MI)
Check whether the use can be converted to remove a comparison against zero.
static const uint16_t ReplaceableInstrsAVX2[][3]
int getMemoryOperandNo(uint64_t TSFlags, unsigned Opcode)
getMemoryOperandNo - The function returns the MCInst operand # for the first field of the memory oper...
virtual const TargetInstrInfo * getInstrInfo() const
std::reverse_iterator< iterator > reverse_iterator
mop_iterator operands_begin()
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
static VectorType * get(Type *ElementType, unsigned NumElements)
VectorType::get - This static method is the primary way to construct an VectorType.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
static bool hasLiveCondCodeDef(MachineInstr *MI)
True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
BasicBlockListType::iterator iterator
bool addRegisterKilled(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
bool callRegIndirect() const
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
void addOperand(const MCOperand &Op)
vt_iterator vt_begin() const
vt_begin / vt_end - Loop over all of the value types that can be represented by values in this regist...
static bool isFrameStoreOpcode(int Opcode)
bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register. ...
static const uint16_t * lookupAVX2(unsigned opcode, unsigned domain)
static X86::CondCode getSwappedCondition(X86::CondCode CC)
Assuming the flags are set by MI(a,b), return the condition code if we modify the instructions such t...
static bool isReassocCandidate(const MachineInstr &Inst, bool &Commuted)
Return true if the input instruction is part of a chain of dependent ops that are suitable for reasso...
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
isLayoutSuccessor - Return true if the specified MBB will be emitted immediately after this block...
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
static bool hasReassocSibling(const MachineInstr &Inst, bool &Commuted)
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
FunctionPass * createCleanupLocalDynamicTLSPass()
createCleanupLocalDynamicTLSPass() - This pass combines multiple accesses to local-dynamic TLS variab...
static bool Expand2AddrUndef(MachineInstrBuilder &MIB, const MCInstrDesc &Desc)
Expand a single-def pseudo instruction to a two-addr instruction with two undef reads of the register...
bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override
unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const override
getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new instruction after load / store ar...
static MachineOperand CreateFI(int Idx)
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
unsigned getConstantPoolIndex(const Constant *C, unsigned Alignment)
getConstantPoolIndex - Create a new entry in the constant pool or return an existing one...
bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
MVT getSimpleVT() const
getSimpleVT - Return the SimpleValueType held in the specified simple EVT.
static cl::opt< bool > NoFusing("disable-spill-fusing", cl::desc("Disable fusing of spill code into instructions"))
bool isMachineOpcode() const
Test if this node has a post-isel opcode, directly corresponding to a MachineInstr opcode...
unsigned getMachineOpcode() const
This may only be called if isMachineOpcode returns true.
bool isReallyTriviallyReMaterializable(const MachineInstr *MI, AliasAnalysis *AA) const override
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
bool ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly. ...