LLVM  3.7.0
AMDGPUSubtarget.cpp
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1 //===-- AMDGPUSubtarget.cpp - AMDGPU Subtarget Information ----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief Implements the AMDGPU specific subclass of TargetSubtarget.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUSubtarget.h"
16 #include "R600ISelLowering.h"
17 #include "R600InstrInfo.h"
18 #include "R600MachineScheduler.h"
19 #include "SIISelLowering.h"
20 #include "SIInstrInfo.h"
21 #include "SIMachineFunctionInfo.h"
22 #include "llvm/ADT/SmallString.h"
24 
25 using namespace llvm;
26 
27 #define DEBUG_TYPE "amdgpu-subtarget"
28 
29 #define GET_SUBTARGETINFO_ENUM
30 #define GET_SUBTARGETINFO_TARGET_DESC
31 #define GET_SUBTARGETINFO_CTOR
32 #include "AMDGPUGenSubtargetInfo.inc"
33 
36  StringRef GPU, StringRef FS) {
37  // Determine default and user-specified characteristics
38  // On SI+, we want FP64 denormals to be on by default. FP32 denormals can be
39  // enabled, but some instructions do not respect them and they run at the
40  // double precision rate, so don't enable by default.
41  //
42  // We want to be able to turn these off, but making this a subtarget feature
43  // for SI has the unhelpful behavior that it unsets everything else if you
44  // disable it.
45 
46  SmallString<256> FullFS("+promote-alloca,+fp64-denormals,");
47  FullFS += FS;
48 
49  if (GPU == "" && TT.getArch() == Triple::amdgcn)
50  GPU = "SI";
51 
52  ParseSubtargetFeatures(GPU, FullFS);
53 
54  // FIXME: I don't think think Evergreen has any useful support for
55  // denormals, but should be checked. Should we issue a warning somewhere
56  // if someone tries to enable these?
58  FP32Denormals = false;
59  FP64Denormals = false;
60  }
61  return *this;
62 }
63 
66  : AMDGPUGenSubtargetInfo(TT, GPU, FS), DevName(GPU), Is64bit(false),
67  DumpCode(false), R600ALUInst(false), HasVertexCache(false),
68  TexVTXClauseSize(0), Gen(AMDGPUSubtarget::R600), FP64(false),
69  FP64Denormals(false), FP32Denormals(false), FastFMAF32(false),
70  CaymanISA(false), FlatAddressSpace(false), EnableIRStructurizer(true),
71  EnablePromoteAlloca(false), EnableIfCvt(true), EnableLoadStoreOpt(false),
72  EnableUnsafeDSOffsetFolding(false),
73  WavefrontSize(0), CFALUBug(false), LocalMemorySize(0),
74  EnableVGPRSpilling(false), SGPRInitBug(false), IsGCN(false),
75  GCN1Encoding(false), GCN3Encoding(false), CIInsts(false), LDSBankCount(0),
76  IsaVersion(ISAVersion0_0_0), EnableHugeScratchBuffer(false),
77  FrameLowering(TargetFrameLowering::StackGrowsUp,
78  64 * 16, // Maximum stack alignment (long16)
79  0),
80  InstrItins(getInstrItineraryForCPU(GPU)), TargetTriple(TT) {
81 
83 
85  InstrInfo.reset(new R600InstrInfo(*this));
86  TLInfo.reset(new R600TargetLowering(TM, *this));
87  } else {
88  InstrInfo.reset(new SIInstrInfo(*this));
89  TLInfo.reset(new SITargetLowering(TM, *this));
90  }
91 }
92 
94  assert(getGeneration() <= NORTHERN_ISLANDS);
95  switch(getWavefrontSize()) {
96  case 16:
97  return 8;
98  case 32:
99  return hasCaymanISA() ? 4 : 8;
100  case 64:
101  return 4;
102  default:
103  llvm_unreachable("Illegal wavefront size.");
104  }
105 }
106 
108  switch(getGeneration()) {
109  default: llvm_unreachable("ChipID unknown");
110  case SEA_ISLANDS: return 12;
111  }
112 }
113 
115  return AMDGPU::getIsaVersion(getFeatureBits());
116 }
117 
119  const SIMachineFunctionInfo *MFI) const {
120  return MFI->getShaderType() == ShaderType::COMPUTE || EnableVGPRSpilling;
121 }
122 
125  MachineInstr *end,
126  unsigned NumRegionInstrs) const {
127  if (getGeneration() >= SOUTHERN_ISLANDS) {
128 
129  // Track register pressure so the scheduler can try to decrease
130  // pressure once register usage is above the threshold defined by
131  // SIRegisterInfo::getRegPressureSetLimit()
132  Policy.ShouldTrackPressure = true;
133 
134  // Enabling both top down and bottom up scheduling seems to give us less
135  // register spills than just using one of these approaches on its own.
136  Policy.OnlyTopDown = false;
137  Policy.OnlyBottomUp = false;
138  }
139 }
140 
bool hasCaymanISA() const
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:240
AMDGPU specific subclass of TargetSubtarget.
Interface definition for R600InstrInfo.
AMDGPUSubtarget & initializeSubtargetDependencies(const Triple &TT, StringRef GPU, StringRef FS)
const_iterator begin(StringRef path)
Get begin iterator over path.
Definition: Path.cpp:232
R600 Machine Scheduler interface.
void overrideSchedPolicy(MachineSchedPolicy &Policy, MachineInstr *begin, MachineInstr *end, unsigned NumRegionInstrs) const override
unsigned getAmdKernelCodeChipID() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
unsigned getStackEntrySize() const
#define false
Definition: ConvertUTF.c:65
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Definition: Triple.h:242
Generation getGeneration() const
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
#define true
Definition: ConvertUTF.c:66
IsaVersion getIsaVersion(const FeatureBitset &Features)
SI DAG Lowering interface definition.
AMDGPU::IsaVersion getIsaVersion() const
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
Information about stack frame layout on the target.
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.
Representation of each machine instruction.
Definition: MachineInstr.h:51
static cl::opt< bool > EnableLoadStoreOpt("aarch64-load-store-opt", cl::desc("Enable the load/store pair"" optimization pass"), cl::init(true), cl::Hidden)
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
Interface definition for SIInstrInfo.
R600 DAG Lowering interface definition.
unsigned getWavefrontSize() const
Primary interface to the complete machine description for the target machine.
AMDGPUSubtarget(const Triple &TT, StringRef CPU, StringRef FS, TargetMachine &TM)
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:40
bool isVGPRSpillingEnabled(const SIMachineFunctionInfo *MFI) const