LLVM  3.7.0
RegAllocBase.cpp
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1 //===-- RegAllocBase.cpp - Register Allocator Base Class ------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the RegAllocBase class which provides common functionality
11 // for LiveIntervalUnion-based register allocators.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "RegAllocBase.h"
16 #include "Spiller.h"
17 #include "llvm/ADT/Statistic.h"
25 #ifndef NDEBUG
27 #endif
29 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/Timer.h"
34 
35 using namespace llvm;
36 
37 #define DEBUG_TYPE "regalloc"
38 
39 STATISTIC(NumNewQueued , "Number of new live ranges queued");
40 
41 // Temporary verification option until we can put verification inside
42 // MachineVerifier.
45  cl::desc("Verify during register allocation"));
46 
47 const char RegAllocBase::TimerGroupName[] = "Register Allocation";
48 bool RegAllocBase::VerifyEnabled = false;
49 
50 //===----------------------------------------------------------------------===//
51 // RegAllocBase Implementation
52 //===----------------------------------------------------------------------===//
53 
54 // Pin the vtable to this file.
55 void RegAllocBase::anchor() {}
56 
58  LiveIntervals &lis,
59  LiveRegMatrix &mat) {
60  TRI = &vrm.getTargetRegInfo();
61  MRI = &vrm.getRegInfo();
62  VRM = &vrm;
63  LIS = &lis;
64  Matrix = &mat;
67 }
68 
69 // Visit all the live registers. If they are already assigned to a physical
70 // register, unify them with the corresponding LiveIntervalUnion, otherwise push
71 // them on the priority queue for later assignment.
72 void RegAllocBase::seedLiveRegs() {
74  for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
76  if (MRI->reg_nodbg_empty(Reg))
77  continue;
78  enqueue(&LIS->getInterval(Reg));
79  }
80 }
81 
82 // Top-level driver to manage the queue of unassigned VirtRegs and call the
83 // selectOrSplit implementation.
85  seedLiveRegs();
86 
87  // Continue assigning vregs one at a time to available physical registers.
88  while (LiveInterval *VirtReg = dequeue()) {
89  assert(!VRM->hasPhys(VirtReg->reg) && "Register already assigned");
90 
91  // Unused registers can appear when the spiller coalesces snippets.
92  if (MRI->reg_nodbg_empty(VirtReg->reg)) {
93  DEBUG(dbgs() << "Dropping unused " << *VirtReg << '\n');
94  aboutToRemoveInterval(*VirtReg);
95  LIS->removeInterval(VirtReg->reg);
96  continue;
97  }
98 
99  // Invalidate all interference queries, live ranges could have changed.
101 
102  // selectOrSplit requests the allocator to return an available physical
103  // register if possible and populate a list of new live intervals that
104  // result from splitting.
105  DEBUG(dbgs() << "\nselectOrSplit "
106  << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg))
107  << ':' << *VirtReg << " w=" << VirtReg->weight << '\n');
108  typedef SmallVector<unsigned, 4> VirtRegVec;
109  VirtRegVec SplitVRegs;
110  unsigned AvailablePhysReg = selectOrSplit(*VirtReg, SplitVRegs);
111 
112  if (AvailablePhysReg == ~0u) {
113  // selectOrSplit failed to find a register!
114  // Probably caused by an inline asm.
115  MachineInstr *MI = nullptr;
117  I = MRI->reg_instr_begin(VirtReg->reg), E = MRI->reg_instr_end();
118  I != E; ) {
119  MachineInstr *TmpMI = &*(I++);
120  if (TmpMI->isInlineAsm()) {
121  MI = TmpMI;
122  break;
123  }
124  }
125  if (MI)
126  MI->emitError("inline assembly requires more registers than available");
127  else
128  report_fatal_error("ran out of registers during register allocation");
129  // Keep going after reporting the error.
130  VRM->assignVirt2Phys(VirtReg->reg,
131  RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front());
132  continue;
133  }
134 
135  if (AvailablePhysReg)
136  Matrix->assign(*VirtReg, AvailablePhysReg);
137 
138  for (VirtRegVec::iterator I = SplitVRegs.begin(), E = SplitVRegs.end();
139  I != E; ++I) {
140  LiveInterval *SplitVirtReg = &LIS->getInterval(*I);
141  assert(!VRM->hasPhys(SplitVirtReg->reg) && "Register already assigned");
142  if (MRI->reg_nodbg_empty(SplitVirtReg->reg)) {
143  DEBUG(dbgs() << "not queueing unused " << *SplitVirtReg << '\n');
144  aboutToRemoveInterval(*SplitVirtReg);
145  LIS->removeInterval(SplitVirtReg->reg);
146  continue;
147  }
148  DEBUG(dbgs() << "queuing new interval: " << *SplitVirtReg << "\n");
149  assert(TargetRegisterInfo::isVirtualRegister(SplitVirtReg->reg) &&
150  "expect split value in virtual register");
151  enqueue(SplitVirtReg);
152  ++NumNewQueued;
153  }
154  }
155 }
bool hasPhys(unsigned virtReg) const
returns true if the specified virtual register is mapped to a physical register
Definition: VirtRegMap.h:92
const unsigned reg
Definition: LiveInterval.h:616
STATISTIC(NumFunctions,"Total number of functions")
MachineFunction & getMachineFunction() const
Definition: VirtRegMap.h:80
static unsigned index2VirtReg(unsigned Index)
index2VirtReg - Convert a 0-based index to a virtual register number.
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:588
LiveRegMatrix * Matrix
Definition: RegAllocBase.h:65
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
virtual unsigned selectOrSplit(LiveInterval &VirtReg, SmallVectorImpl< unsigned > &splitLVRs)=0
void assignVirt2Phys(unsigned virtReg, unsigned physReg)
creates a mapping for the specified virtual register to the specified physical register ...
Definition: VirtRegMap.h:105
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag=true)
Reports a serious error, calling any installed error handler.
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
NamedRegionTimer - This class is basically a combination of TimeRegion and Timer. ...
Definition: Timer.h:147
const TargetRegisterClass * getRegClass(unsigned Reg) const
getRegClass - Return the register class of the specified virtual register.
void freezeReservedRegs(const MachineFunction &)
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
Reg
All possible values of the reg field in the ModR/M byte.
ArrayRef< MCPhysReg > getOrder(const TargetRegisterClass *RC) const
getOrder - Returns the preferred allocation order for RC.
static reg_instr_iterator reg_instr_end()
defusechain_iterator - This class provides iterator support for machine operands in the function that...
void assign(LiveInterval &VirtReg, unsigned PhysReg)
Assign VirtReg to PhysReg.
#define T
const char * getRegClassName(const TargetRegisterClass *Class) const
getRegClassName - Returns the name of the register class.
void invalidateVirtRegs()
Invalidate cached interference queries after modifying virtual register live ranges.
Definition: LiveRegMatrix.h:79
VirtRegMap * VRM
Definition: RegAllocBase.h:63
void removeInterval(unsigned Reg)
const TargetRegisterInfo & getTargetRegInfo() const
Definition: VirtRegMap.h:86
reg_instr_iterator reg_instr_begin(unsigned RegNo) const
void runOnMachineFunction(const MachineFunction &MF)
runOnFunction - Prepare to answer questions about MF.
void init(VirtRegMap &vrm, LiveIntervals &lis, LiveRegMatrix &mat)
static const char TimerGroupName[]
Definition: RegAllocBase.h:97
LiveIntervals * LIS
Definition: RegAllocBase.h:64
void emitError(StringRef Msg) const
Emit an error referring to the source location of this instruction.
virtual void enqueue(LiveInterval *LI)=0
enqueue - Add VirtReg to the priority queue of unassigned registers.
bool isInlineAsm() const
Definition: MachineInstr.h:760
LiveInterval & getInterval(unsigned Reg)
static cl::opt< bool, true > VerifyRegAlloc("verify-regalloc", cl::location(RegAllocBase::VerifyEnabled), cl::desc("Verify during register allocation"))
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:123
virtual void aboutToRemoveInterval(LiveInterval &LI)
Method called when the allocator is about to remove a LiveInterval.
Definition: RegAllocBase.h:100
Representation of each machine instruction.
Definition: MachineInstr.h:51
static bool VerifyEnabled
VerifyEnabled - True when -verify-regalloc is given.
Definition: RegAllocBase.h:104
const TargetRegisterInfo * TRI
Definition: RegAllocBase.h:61
#define I(x, y, z)
Definition: MD5.cpp:54
MachineRegisterInfo & getRegInfo() const
Definition: VirtRegMap.h:85
#define DEBUG(X)
Definition: Debug.h:92
RegisterClassInfo RegClassInfo
Definition: RegAllocBase.h:66
bool TimePassesIsEnabled
If the user specifies the -time-passes argument on an LLVM tool command line then the value of this b...
Definition: IRReader.cpp:26
MachineRegisterInfo * MRI
Definition: RegAllocBase.h:62
LocationClass< Ty > location(Ty &L)
Definition: CommandLine.h:340
bool reg_nodbg_empty(unsigned RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions...
virtual LiveInterval * dequeue()=0
dequeue - Return the next unassigned register, or NULL.