24 #define DEBUG_TYPE "pre-RA-sched"
26 bool PPCDispatchGroupSBHazardRecognizer::isLoadAfterStore(
SUnit *SU) {
28 if (isBCTRAfterSet(SU))
40 for (
unsigned i = 0, ie = (
unsigned) SU->
Preds.size(); i != ie; ++i) {
42 if (!PredMCID || !PredMCID->
mayStore())
45 if (!SU->
Preds[i].isNormalMemory() && !SU->
Preds[i].isBarrier())
48 for (
unsigned j = 0, je = CurGroup.size(); j != je; ++j)
49 if (SU->
Preds[i].getSUnit() == CurGroup[j])
56 bool PPCDispatchGroupSBHazardRecognizer::isBCTRAfterSet(
SUnit *SU) {
66 for (
unsigned i = 0, ie = (
unsigned) SU->
Preds.size(); i != ie; ++i) {
68 if (!PredMCID || PredMCID->
getSchedClass() != PPC::Sched::IIC_SprMTSPR)
71 if (SU->
Preds[i].isCtrl())
74 for (
unsigned j = 0, je = CurGroup.size(); j != je; ++j)
75 if (SU->
Preds[i].getSUnit() == CurGroup[j])
87 bool PPCDispatchGroupSBHazardRecognizer::mustComeFirst(
const MCInstrDesc *MCID,
97 case PPC::Sched::IIC_IntDivW:
98 case PPC::Sched::IIC_IntDivD:
99 case PPC::Sched::IIC_LdStLoadUpd:
100 case PPC::Sched::IIC_LdStLDU:
101 case PPC::Sched::IIC_LdStLFDU:
102 case PPC::Sched::IIC_LdStLFDUX:
103 case PPC::Sched::IIC_LdStLHA:
104 case PPC::Sched::IIC_LdStLHAU:
105 case PPC::Sched::IIC_LdStLWA:
106 case PPC::Sched::IIC_LdStSTDU:
107 case PPC::Sched::IIC_LdStSTFDU:
110 case PPC::Sched::IIC_LdStLoadUpdX:
111 case PPC::Sched::IIC_LdStLDUX:
112 case PPC::Sched::IIC_LdStLHAUX:
113 case PPC::Sched::IIC_LdStLWARX:
114 case PPC::Sched::IIC_LdStLDARX:
115 case PPC::Sched::IIC_LdStSTDUX:
116 case PPC::Sched::IIC_LdStSTDCX:
117 case PPC::Sched::IIC_LdStSTWCX:
118 case PPC::Sched::IIC_BrMCRX:
132 case PPC::Sched::IIC_BrCR:
133 case PPC::Sched::IIC_SprMFCR:
134 case PPC::Sched::IIC_SprMFCRF:
135 case PPC::Sched::IIC_SprMTSPR:
142 if (Stalls == 0 && isLoadAfterStore(SU))
151 if (MCID && mustComeFirst(MCID, NSlots) && CurSlots)
161 if (isLoadAfterStore(SU) && CurSlots < 6) {
178 if (CurSlots == 5 || (MCID->
isBranch() && CurBranches == 1)) {
180 CurSlots = CurBranches = 0;
182 DEBUG(
dbgs() <<
"**** Adding to dispatch group: SU(" <<
187 bool MustBeFirst = mustComeFirst(MCID, NSlots);
191 if (MustBeFirst && CurSlots) {
192 CurSlots = CurBranches = 0;
197 CurGroup.push_back(SU);
217 CurSlots = CurBranches = 0;
229 CurSlots = CurBranches = 0;
231 CurGroup.push_back(
nullptr);
267 void PPCHazardRecognizer970::EndDispatchGroup() {
268 DEBUG(
errs() <<
"=== Start of dispatch group\n");
278 PPCHazardRecognizer970::GetInstrType(
unsigned Opcode,
279 bool &isFirst,
bool &isSingle,
281 bool &isLoad,
bool &isStore) {
287 uint64_t TSFlags = MCID.
TSFlags;
297 bool PPCHazardRecognizer970::
298 isLoadOfStoredAddress(uint64_t LoadSize, int64_t LoadOffset,
299 const Value *LoadValue)
const {
300 for (
unsigned i = 0, e = NumStores; i != e; ++i) {
302 if (LoadValue == StoreValue[i] && LoadOffset == StoreOffset[i])
307 if (StoreValue[i] == LoadValue) {
310 if (StoreOffset[i] < LoadOffset) {
311 if (int64_t(StoreOffset[i]+StoreSize[i]) > LoadOffset)
return true;
313 if (int64_t(LoadOffset+LoadSize) > StoreOffset[i])
return true;
326 assert(Stalls == 0 &&
"PPC hazards don't support scoreboard lookahead");
334 bool isFirst, isSingle, isCracked, isLoad, isStore;
336 GetInstrType(Opcode, isFirst, isSingle, isCracked,
342 if (NumIssued != 0 && (isFirst || isSingle))
348 if (isCracked && NumIssued > 2)
359 if (NumIssued == 4)
return Hazard;
363 if (NumIssued >= 2)
return Hazard;
377 if (isLoadOfStoredAddress(MO->
getSize(),
392 bool isFirst, isSingle, isCracked, isLoad, isStore;
394 GetInstrType(Opcode, isFirst, isSingle, isCracked,
399 if (Opcode ==
PPC::MTCTR || Opcode == PPC::MTCTR8) HasCTRSet =
true;
402 if (isStore && NumStores < 4 && !MI->memoperands_empty()) {
404 StoreSize[NumStores] = MO->
getSize();
405 StoreOffset[NumStores] = MO->
getOffset();
406 StoreValue[NumStores] = MO->
getValue();
424 assert(NumIssued < 5 &&
"Illegal dispatch group!");
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
int getNonRecordFormOpcode(uint16_t)
PPCHazardRecognizer970(const ScheduleDAG &DAG)
PPC970_Cracked - This instruction is cracked into two pieces, requiring two dispatch pipes to be avai...
bool mayStore() const
Return true if this instruction could possibly modify memory.
Describe properties that are true of each instruction in the target description file.
MachineInstr * getInstr() const
getInstr - Return the representative MachineInstr for this SUnit.
void RecedeCycle() override
RecedeCycle - This callback is invoked whenever the next bottom-up instruction to be scheduled cannot...
unsigned PreEmitNoops(SUnit *SU) override
PreEmitNoops - This callback is invoked prior to emitting an instruction.
These are the various PPC970 execution unit pipelines.
CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a BCTRL instruction.
SmallVector< SDep, 4 > Preds
MachineMemOperand - A description of a memory reference used in the backend.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
HazardType getHazardType(SUnit *SU, int Stalls) override
getHazardType - We return hazard for any non-branch instruction that would terminate the dispatch gro...
void EmitInstruction(SUnit *SU) override
EmitInstruction - This callback is invoked when an instruction is emitted, to advance the hazard stat...
void AdvanceCycle() override
AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled cannot...
void EmitNoop() override
EmitNoop - This callback is invoked when a noop was added to the instruction stream.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
bool isDebugValue() const
void Reset() override
Reset - This callback is invoked when a new block of instructions is about to be schedule.
HazardType getHazardType(SUnit *SU, int Stalls) override
getHazardType - Return the hazard type of emitting this node.
PPC970_First - This instruction starts a new dispatch group, so it will always be the first one in th...
CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a MTCTR instruction.
void EmitInstruction(SUnit *SU) override
EmitInstruction - This callback is invoked when an instruction is emitted, to advance the hazard stat...
PPC970_Single - This instruction starts a new dispatch group and terminates it, so it will be the sol...
virtual bool ShouldPreferAnother(SUnit *)
ShouldPreferAnother - This callback may be invoked if getHazardType returns NoHazard.
void Reset() override
Reset - This callback is invoked when a new block of instructions is about to be schedule.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
unsigned getOpcode() const
Return the opcode number for this descriptor.
void AdvanceCycle() override
AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled cannot...
bool memoperands_empty() const
void Reset() override
Reset - This callback is invoked when a new block of instructions is about to be schedule.
bool mayLoad() const
Return true if this instruction could possibly read memory.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
const Value * getValue() const
getValue - Return the base address of the memory access.
virtual unsigned PreEmitNoops(SUnit *)
PreEmitNoops - This callback is invoked prior to emitting an instruction.
bool ShouldPreferAnother(SUnit *SU) override
ShouldPreferAnother - This callback may be invoked if getHazardType returns NoHazard.
Representation of each machine instruction.
unsigned getSchedClass() const
Return the scheduling class for this instruction.
void AdvanceCycle() override
AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled cannot...
const TargetInstrInfo * TII
virtual void dumpNode(const SUnit *SU) const =0
LLVM Value Representation.
void EmitInstruction(SUnit *SU) override
EmitInstruction - This callback is invoked when an instruction is emitted, to advance the hazard stat...
int64_t getOffset() const
getOffset - For normal values, this is a byte offset added to the base address.
uint64_t getSize() const
getSize - Return the size in bytes of the memory reference.
const MCInstrDesc * getInstrDesc(const SUnit *SU) const
getInstrDesc - Return the MCInstrDesc of this SUnit.
HazardType getHazardType(SUnit *SU, int Stalls) override
getHazardType - Return the hazard type of emitting this node.
SUnit - Scheduling unit. This is a node in the scheduling DAG.
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.