LLVM  3.7.0
Public Member Functions | List of all members
llvm::VLIWMachineScheduler Class Reference

Extend the standard ScheduleDAGMI to provide more context and override the top-level schedule() driver. More...

#include <HexagonMachineScheduler.h>

Inheritance diagram for llvm::VLIWMachineScheduler:
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Collaboration diagram for llvm::VLIWMachineScheduler:
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Public Member Functions

 VLIWMachineScheduler (MachineSchedContext *C, std::unique_ptr< MachineSchedStrategy > S)
 
void schedule () override
 Schedule - This is called back from ScheduleDAGInstrs::Run() when it's time to do some work. More...
 
void postprocessDAG ()
 Perform platform-specific DAG postprocessing. More...
 
- Public Member Functions inherited from llvm::ScheduleDAGMILive
 ScheduleDAGMILive (MachineSchedContext *C, std::unique_ptr< MachineSchedStrategy > S)
 
 ~ScheduleDAGMILive () override
 
bool hasVRegLiveness () const override
 Return true if this DAG supports VReg liveness and RegPressure. More...
 
bool isTrackingPressure () const
 Return true if register pressure tracking is enabled. More...
 
const IntervalPressuregetTopPressure () const
 Get current register pressure for the top scheduled instructions. More...
 
const RegPressureTrackergetTopRPTracker () const
 
const IntervalPressuregetBotPressure () const
 Get current register pressure for the bottom scheduled instructions. More...
 
const RegPressureTrackergetBotRPTracker () const
 
const IntervalPressuregetRegPressure () const
 Get register pressure for the entire scheduling region before scheduling. More...
 
const std::vector
< PressureChange > & 
getRegionCriticalPSets () const
 
PressureDiffgetPressureDiff (const SUnit *SU)
 
void computeDFSResult ()
 Compute a DFSResult after DAG building is complete, and before any queue comparisons. More...
 
const SchedDFSResultgetDFSResult () const
 Return a non-null DFS result if the scheduling strategy initialized it. More...
 
BitVectorgetScheduledTrees ()
 
void enterRegion (MachineBasicBlock *bb, MachineBasicBlock::iterator begin, MachineBasicBlock::iterator end, unsigned regioninstrs) override
 Implement the ScheduleDAGInstrs interface for handling the next scheduling region. More...
 
unsigned computeCyclicCriticalPath ()
 Compute the cyclic critical path through the DAG. More...
 
- Public Member Functions inherited from llvm::ScheduleDAGMI
 ScheduleDAGMI (MachineSchedContext *C, std::unique_ptr< MachineSchedStrategy > S, bool IsPostRA)
 
 ~ScheduleDAGMI () override
 
void addMutation (std::unique_ptr< ScheduleDAGMutation > Mutation)
 Add a postprocessing step to the DAG builder. More...
 
bool canAddEdge (SUnit *SuccSU, SUnit *PredSU)
 True if an edge can be added from PredSU to SuccSU without creating a cycle. More...
 
bool addEdge (SUnit *SuccSU, const SDep &PredDep)
 Add a DAG edge to the given SU with the given predecessor dependence data. More...
 
MachineBasicBlock::iterator top () const
 
MachineBasicBlock::iterator bottom () const
 
void moveInstruction (MachineInstr *MI, MachineBasicBlock::iterator InsertPos)
 Change the position of an instruction within the basic block and update live ranges and region boundary iterators. More...
 
const SUnitgetNextClusterPred () const
 
const SUnitgetNextClusterSucc () const
 
void viewGraph (const Twine &Name, const Twine &Title) override
 viewGraph - Pop up a ghostview window with the reachable parts of the DAG rendered using 'dot'. More...
 
void viewGraph () override
 Out-of-line implementation with no arguments is handy for gdb. More...
 
- Public Member Functions inherited from llvm::ScheduleDAGInstrs
 ScheduleDAGInstrs (MachineFunction &mf, const MachineLoopInfo *mli, bool IsPostRAFlag, bool RemoveKillFlags=false, LiveIntervals *LIS=nullptr)
 
 ~ScheduleDAGInstrs () override
 
bool isPostRA () const
 
LiveIntervalsgetLIS () const
 Expose LiveIntervals for use in DAG mutators and such. More...
 
const TargetSchedModelgetSchedModel () const
 Get the machine model for instruction scheduling. More...
 
const MCSchedClassDescgetSchedClass (SUnit *SU) const
 Resolve and cache a resolved scheduling class for an SUnit. More...
 
MachineBasicBlock::iterator begin () const
 begin - Return an iterator to the top of the current scheduling region. More...
 
MachineBasicBlock::iterator end () const
 end - Return an iterator to the bottom of the current scheduling region. More...
 
SUnitnewSUnit (MachineInstr *MI)
 newSUnit - Creates a new SUnit and return a ptr to it. More...
 
SUnitgetSUnit (MachineInstr *MI) const
 getSUnit - Return an existing SUnit for this MI, or NULL. More...
 
virtual void startBlock (MachineBasicBlock *BB)
 startBlock - Prepare to perform scheduling in the given block. More...
 
virtual void finishBlock ()
 finishBlock - Clean up after scheduling in the given block. More...
 
virtual void exitRegion ()
 Notify that the scheduler has finished scheduling the current region. More...
 
void buildSchedGraph (AliasAnalysis *AA, RegPressureTracker *RPTracker=nullptr, PressureDiffs *PDiffs=nullptr)
 buildSchedGraph - Build SUnits from the MachineBasicBlock that we are input. More...
 
void addSchedBarrierDeps ()
 addSchedBarrierDeps - Add dependencies from instructions in the current list of instructions being scheduled to scheduling barrier. More...
 
virtual void finalizeSchedule ()
 finalizeSchedule - Allow targets to perform final scheduling actions at the level of the whole MachineFunction. More...
 
void dumpNode (const SUnit *SU) const override
 
std::string getGraphNodeLabel (const SUnit *SU) const override
 Return a label for a DAG node that points to an instruction. More...
 
std::string getDAGName () const override
 Return a label for the region of code covered by the DAG. More...
 
void fixupKills (MachineBasicBlock *MBB)
 Fix register kill flags that scheduling has made invalid. More...
 
- Public Member Functions inherited from llvm::ScheduleDAG
 ScheduleDAG (MachineFunction &mf)
 
virtual ~ScheduleDAG ()
 
void clearDAG ()
 clearDAG - clear the DAG state (between regions). More...
 
const MCInstrDescgetInstrDesc (const SUnit *SU) const
 getInstrDesc - Return the MCInstrDesc of this SUnit. More...
 
virtual void addCustomGraphFeatures (GraphWriter< ScheduleDAG * > &) const
 addCustomGraphFeatures - Add custom features for a visualization of the ScheduleDAG. More...
 
unsigned VerifyScheduledDAG (bool isBottomUp)
 VerifyScheduledDAG - Verify that all SUnits were scheduled and that their state is consistent. More...
 

Additional Inherited Members

- Public Attributes inherited from llvm::ScheduleDAG
const TargetMachineTM
 
const TargetInstrInfoTII
 
const TargetRegisterInfoTRI
 
MachineFunctionMF
 
MachineRegisterInfoMRI
 
std::vector< SUnitSUnits
 
SUnit EntrySU
 
SUnit ExitSU
 
bool StressSched
 
- Protected Types inherited from llvm::ScheduleDAGInstrs
typedef std::vector< std::pair
< MachineInstr *, MachineInstr * > > 
DbgValueVector
 DbgValues - Remember instruction that precedes DBG_VALUE. More...
 
- Protected Member Functions inherited from llvm::ScheduleDAGMILive
void buildDAGWithRegPressure ()
 Call ScheduleDAGInstrs::buildSchedGraph with register pressure tracking enabled. More...
 
void scheduleMI (SUnit *SU, bool IsTopNode)
 Move an instruction and update register pressure. More...
 
void initRegPressure ()
 
void updatePressureDiffs (ArrayRef< unsigned > LiveUses)
 Update the PressureDiff array for liveness after scheduling this instruction. More...
 
void updateScheduledPressure (const SUnit *SU, const std::vector< unsigned > &NewMaxPressure)
 
- Protected Member Functions inherited from llvm::ScheduleDAGMI
void postprocessDAG ()
 Apply each ScheduleDAGMutation step in order. More...
 
void initQueues (ArrayRef< SUnit * > TopRoots, ArrayRef< SUnit * > BotRoots)
 Release ExitSU predecessors and setup scheduler queues. More...
 
void updateQueues (SUnit *SU, bool IsTopNode)
 Update scheduler DAG and queues after scheduling an instruction. More...
 
void placeDebugValues ()
 Reinsert debug_values recorded in ScheduleDAGInstrs::DbgValues. More...
 
void dumpSchedule () const
 dump the scheduled Sequence. More...
 
bool checkSchedLimit ()
 
void findRootsAndBiasEdges (SmallVectorImpl< SUnit * > &TopRoots, SmallVectorImpl< SUnit * > &BotRoots)
 
void releaseSucc (SUnit *SU, SDep *SuccEdge)
 ReleaseSucc - Decrement the NumPredsLeft count of a successor. More...
 
void releaseSuccessors (SUnit *SU)
 releaseSuccessors - Call releaseSucc on each of SU's successors. More...
 
void releasePred (SUnit *SU, SDep *PredEdge)
 ReleasePred - Decrement the NumSuccsLeft count of a predecessor. More...
 
void releasePredecessors (SUnit *SU)
 releasePredecessors - Call releasePred on each of SU's predecessors. More...
 
- Protected Member Functions inherited from llvm::ScheduleDAGInstrs
void initSUnits ()
 Create an SUnit for each real instruction, numbered in top-down toplological order. More...
 
void addPhysRegDataDeps (SUnit *SU, unsigned OperIdx)
 MO is an operand of SU's instruction that defines a physical register. More...
 
void addPhysRegDeps (SUnit *SU, unsigned OperIdx)
 addPhysRegDeps - Add register dependencies (data, anti, and output) from this SUnit to following instructions in the same scheduling region that depend the physical register referenced at OperIdx. More...
 
void addVRegDefDeps (SUnit *SU, unsigned OperIdx)
 addVRegDefDeps - Add register output and data dependencies from this SUnit to instructions that occur later in the same scheduling region if they read from or write to the virtual register defined at OperIdx. More...
 
void addVRegUseDeps (SUnit *SU, unsigned OperIdx)
 addVRegUseDeps - Add a register data dependency if the instruction that defines the virtual register used at OperIdx is mapped to an SUnit. More...
 
void startBlockForKills (MachineBasicBlock *BB)
 PostRA helper for rewriting kill flags. More...
 
bool toggleKillFlag (MachineInstr *MI, MachineOperand &MO)
 Toggle a register operand kill flag. More...
 
- Protected Attributes inherited from llvm::ScheduleDAGMILive
RegisterClassInfoRegClassInfo
 
SchedDFSResultDFSResult
 Information about DAG subtrees. More...
 
BitVector ScheduledTrees
 
MachineBasicBlock::iterator LiveRegionEnd
 
PressureDiffs SUPressureDiffs
 
bool ShouldTrackPressure
 Register pressure in this region computed by initRegPressure. More...
 
IntervalPressure RegPressure
 
RegPressureTracker RPTracker
 
std::vector< PressureChangeRegionCriticalPSets
 List of pressure sets that exceed the target's pressure limit before scheduling, listed in increasing set ID order. More...
 
IntervalPressure TopPressure
 The top of the unscheduled zone. More...
 
RegPressureTracker TopRPTracker
 
IntervalPressure BotPressure
 The bottom of the unscheduled zone. More...
 
RegPressureTracker BotRPTracker
 
- Protected Attributes inherited from llvm::ScheduleDAGMI
AliasAnalysisAA
 
std::unique_ptr
< MachineSchedStrategy
SchedImpl
 
ScheduleDAGTopologicalSort Topo
 Topo - A topological ordering for SUnits which permits fast IsReachable and similar queries. More...
 
std::vector< std::unique_ptr
< ScheduleDAGMutation > > 
Mutations
 Ordered list of DAG postprocessing steps. More...
 
MachineBasicBlock::iterator CurrentTop
 The top of the unscheduled zone. More...
 
MachineBasicBlock::iterator CurrentBottom
 The bottom of the unscheduled zone. More...
 
const SUnitNextClusterPred
 Record the next node in a scheduled cluster. More...
 
const SUnitNextClusterSucc
 
unsigned NumInstrsScheduled
 The number of instructions scheduled so far. More...
 
- Protected Attributes inherited from llvm::ScheduleDAGInstrs
const MachineLoopInfoMLI
 
const MachineFrameInfoMFI
 
LiveIntervalsLIS
 Live Intervals provides reaching defs in preRA scheduling. More...
 
TargetSchedModel SchedModel
 TargetSchedModel provides an interface to the machine model. More...
 
bool IsPostRA
 isPostRA flag indicates vregs cannot be present. More...
 
bool RemoveKillFlags
 True if the DAG builder should remove kill flags (in preparation for rescheduling). More...
 
bool CanHandleTerminators
 The standard DAG builder does not normally include terminators as DAG nodes because it does not create the necessary dependencies to prevent reordering. More...
 
MachineBasicBlockBB
 State specific to the current scheduling region. More...
 
MachineBasicBlock::iterator RegionBegin
 The beginning of the range to be scheduled. More...
 
MachineBasicBlock::iterator RegionEnd
 The end of the range to be scheduled. More...
 
unsigned NumRegionInstrs
 Instructions in this region (distance(RegionBegin, RegionEnd)). More...
 
DenseMap< MachineInstr *, SUnit * > MISUnitMap
 After calling BuildSchedGraph, each machine instruction in the current scheduling region is mapped to an SUnit. More...
 
VReg2UseMap VRegUses
 After calling BuildSchedGraph, each vreg used in the scheduling region is mapped to a set of SUnits. More...
 
Reg2SUnitsMap Defs
 State internal to DAG building. More...
 
Reg2SUnitsMap Uses
 
VReg2SUnitMap VRegDefs
 Track the last instruction in this region defining each virtual register. More...
 
std::vector< SUnit * > PendingLoads
 PendingLoads - Remember where unknown loads are after the most recent unknown store, as we iterate. More...
 
DbgValueVector DbgValues
 
MachineInstrFirstDbgValue
 
BitVector LiveRegs
 Set of live physical registers for updating kill flags. More...
 

Detailed Description

Extend the standard ScheduleDAGMI to provide more context and override the top-level schedule() driver.

Definition at line 94 of file HexagonMachineScheduler.h.

Constructor & Destructor Documentation

llvm::VLIWMachineScheduler::VLIWMachineScheduler ( MachineSchedContext C,
std::unique_ptr< MachineSchedStrategy S 
)
inline

Definition at line 96 of file HexagonMachineScheduler.h.

Member Function Documentation

void VLIWMachineScheduler::postprocessDAG ( )

Perform platform-specific DAG postprocessing.

Platform-specific modifications to DAG.

Definition at line 24 of file HexagonMachineScheduler.cpp.

References llvm::SDep::Barrier, and llvm::ScheduleDAG::SUnits.

Referenced by schedule().

void VLIWMachineScheduler::schedule ( )
overridevirtual

The documentation for this class was generated from the following files: