LLVM  3.7.0
RegisterScavenging.cpp
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1 //===-- RegisterScavenging.cpp - Machine register scavenging --------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the machine register scavenger. It can provide
11 // information, such as unused registers, at any point in a machine basic block.
12 // It also provides a mechanism to make registers available by evicting them to
13 // spill slots.
14 //
15 //===----------------------------------------------------------------------===//
16 
23 #include "llvm/Support/Debug.h"
29 using namespace llvm;
30 
31 #define DEBUG_TYPE "reg-scavenging"
32 
33 /// setUsed - Set the register units of this register as used.
34 void RegScavenger::setRegUsed(unsigned Reg) {
35  for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI)
36  RegUnitsAvailable.reset(*RUI);
37 }
38 
41  IE = Scavenged.end(); I != IE; ++I) {
42  I->Reg = 0;
43  I->Restore = nullptr;
44  }
45 
46  // All register units start out unused.
47  RegUnitsAvailable.set();
48 
49  if (!MBB)
50  return;
51 
52  // Live-in registers are in use.
54  E = MBB->livein_end(); I != E; ++I)
55  setRegUsed(*I);
56 
57  // Pristine CSRs are also unavailable.
58  const MachineFunction &MF = *MBB->getParent();
59  BitVector PR = MF.getFrameInfo()->getPristineRegs(MF);
60  for (int I = PR.find_first(); I>0; I = PR.find_next(I))
61  setRegUsed(I);
62 }
63 
65  MachineFunction &MF = *mbb->getParent();
66  TII = MF.getSubtarget().getInstrInfo();
67  TRI = MF.getSubtarget().getRegisterInfo();
68  MRI = &MF.getRegInfo();
69 
70  assert((NumRegUnits == 0 || NumRegUnits == TRI->getNumRegUnits()) &&
71  "Target changed?");
72 
73  // It is not possible to use the register scavenger after late optimization
74  // passes that don't preserve accurate liveness information.
75  assert(MRI->tracksLiveness() &&
76  "Cannot use register scavenger with inaccurate liveness");
77 
78  // Self-initialize.
79  if (!MBB) {
80  NumRegUnits = TRI->getNumRegUnits();
81  RegUnitsAvailable.resize(NumRegUnits);
82  KillRegUnits.resize(NumRegUnits);
83  DefRegUnits.resize(NumRegUnits);
84  TmpRegUnits.resize(NumRegUnits);
85  }
86 
87  MBB = mbb;
88  initRegState();
89 
90  Tracking = false;
91 }
92 
93 void RegScavenger::addRegUnits(BitVector &BV, unsigned Reg) {
94  for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI)
95  BV.set(*RUI);
96 }
97 
98 void RegScavenger::determineKillsAndDefs() {
99  assert(Tracking && "Must be tracking to determine kills and defs");
100 
101  MachineInstr *MI = MBBI;
102  assert(!MI->isDebugValue() && "Debug values have no kills or defs");
103 
104  // Find out which registers are early clobbered, killed, defined, and marked
105  // def-dead in this instruction.
106  KillRegUnits.reset();
107  DefRegUnits.reset();
108  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
109  const MachineOperand &MO = MI->getOperand(i);
110  if (MO.isRegMask()) {
111 
112  TmpRegUnits.clear();
113  for (unsigned RU = 0, RUEnd = TRI->getNumRegUnits(); RU != RUEnd; ++RU) {
114  for (MCRegUnitRootIterator RURI(RU, TRI); RURI.isValid(); ++RURI) {
115  if (MO.clobbersPhysReg(*RURI)) {
116  TmpRegUnits.set(RU);
117  break;
118  }
119  }
120  }
121 
122  // Apply the mask.
123  KillRegUnits |= TmpRegUnits;
124  }
125  if (!MO.isReg())
126  continue;
127  unsigned Reg = MO.getReg();
128  if (!Reg || TargetRegisterInfo::isVirtualRegister(Reg) || isReserved(Reg))
129  continue;
130 
131  if (MO.isUse()) {
132  // Ignore undef uses.
133  if (MO.isUndef())
134  continue;
135  if (MO.isKill())
136  addRegUnits(KillRegUnits, Reg);
137  } else {
138  assert(MO.isDef());
139  if (MO.isDead())
140  addRegUnits(KillRegUnits, Reg);
141  else
142  addRegUnits(DefRegUnits, Reg);
143  }
144  }
145 }
146 
148  assert(Tracking && "Cannot unprocess because we're not tracking");
149 
150  MachineInstr *MI = MBBI;
151  if (!MI->isDebugValue()) {
152  determineKillsAndDefs();
153 
154  // Commit the changes.
155  setUsed(KillRegUnits);
156  setUnused(DefRegUnits);
157  }
158 
159  if (MBBI == MBB->begin()) {
160  MBBI = MachineBasicBlock::iterator(nullptr);
161  Tracking = false;
162  } else
163  --MBBI;
164 }
165 
167  // Move ptr forward.
168  if (!Tracking) {
169  MBBI = MBB->begin();
170  Tracking = true;
171  } else {
172  assert(MBBI != MBB->end() && "Already past the end of the basic block!");
173  MBBI = std::next(MBBI);
174  }
175  assert(MBBI != MBB->end() && "Already at the end of the basic block!");
176 
177  MachineInstr *MI = MBBI;
178 
180  IE = Scavenged.end(); I != IE; ++I) {
181  if (I->Restore != MI)
182  continue;
183 
184  I->Reg = 0;
185  I->Restore = nullptr;
186  }
187 
188  if (MI->isDebugValue())
189  return;
190 
191  determineKillsAndDefs();
192 
193  // Verify uses and defs.
194 #ifndef NDEBUG
195  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
196  const MachineOperand &MO = MI->getOperand(i);
197  if (!MO.isReg())
198  continue;
199  unsigned Reg = MO.getReg();
200  if (!Reg || TargetRegisterInfo::isVirtualRegister(Reg) || isReserved(Reg))
201  continue;
202  if (MO.isUse()) {
203  if (MO.isUndef())
204  continue;
205  if (!isRegUsed(Reg)) {
206  // Check if it's partial live: e.g.
207  // D0 = insert_subreg D0<undef>, S0
208  // ... D0
209  // The problem is the insert_subreg could be eliminated. The use of
210  // D0 is using a partially undef value. This is not *incorrect* since
211  // S1 is can be freely clobbered.
212  // Ideally we would like a way to model this, but leaving the
213  // insert_subreg around causes both correctness and performance issues.
214  bool SubUsed = false;
215  for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
216  if (isRegUsed(*SubRegs)) {
217  SubUsed = true;
218  break;
219  }
220  bool SuperUsed = false;
221  for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
222  if (isRegUsed(*SR)) {
223  SuperUsed = true;
224  break;
225  }
226  }
227  if (!SubUsed && !SuperUsed) {
228  MBB->getParent()->verify(nullptr, "In Register Scavenger");
229  llvm_unreachable("Using an undefined register!");
230  }
231  (void)SubUsed;
232  (void)SuperUsed;
233  }
234  } else {
235  assert(MO.isDef());
236 #if 0
237  // FIXME: Enable this once we've figured out how to correctly transfer
238  // implicit kills during codegen passes like the coalescer.
239  assert((KillRegs.test(Reg) || isUnused(Reg) ||
240  isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &&
241  "Re-defining a live register!");
242 #endif
243  }
244  }
245 #endif // NDEBUG
246 
247  // Commit the changes.
248  setUnused(KillRegUnits);
249  setUsed(DefRegUnits);
250 }
251 
252 bool RegScavenger::isRegUsed(unsigned Reg, bool includeReserved) const {
253  if (includeReserved && isReserved(Reg))
254  return true;
255  for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI)
256  if (!RegUnitsAvailable.test(*RUI))
257  return true;
258  return false;
259 }
260 
262  for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
263  I != E; ++I)
264  if (!isRegUsed(*I)) {
265  DEBUG(dbgs() << "Scavenger found unused reg: " << TRI->getName(*I) <<
266  "\n");
267  return *I;
268  }
269  return 0;
270 }
271 
272 /// getRegsAvailable - Return all available registers in the register class
273 /// in Mask.
275  BitVector Mask(TRI->getNumRegs());
276  for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
277  I != E; ++I)
278  if (!isRegUsed(*I))
279  Mask.set(*I);
280  return Mask;
281 }
282 
283 /// findSurvivorReg - Return the candidate register that is unused for the
284 /// longest after StartMII. UseMI is set to the instruction where the search
285 /// stopped.
286 ///
287 /// No more than InstrLimit instructions are inspected.
288 ///
289 unsigned RegScavenger::findSurvivorReg(MachineBasicBlock::iterator StartMI,
290  BitVector &Candidates,
291  unsigned InstrLimit,
293  int Survivor = Candidates.find_first();
294  assert(Survivor > 0 && "No candidates for scavenging");
295 
297  assert(StartMI != ME && "MI already at terminator");
298  MachineBasicBlock::iterator RestorePointMI = StartMI;
299  MachineBasicBlock::iterator MI = StartMI;
300 
301  bool inVirtLiveRange = false;
302  for (++MI; InstrLimit > 0 && MI != ME; ++MI, --InstrLimit) {
303  if (MI->isDebugValue()) {
304  ++InstrLimit; // Don't count debug instructions
305  continue;
306  }
307  bool isVirtKillInsn = false;
308  bool isVirtDefInsn = false;
309  // Remove any candidates touched by instruction.
310  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
311  const MachineOperand &MO = MI->getOperand(i);
312  if (MO.isRegMask())
313  Candidates.clearBitsNotInMask(MO.getRegMask());
314  if (!MO.isReg() || MO.isUndef() || !MO.getReg())
315  continue;
317  if (MO.isDef())
318  isVirtDefInsn = true;
319  else if (MO.isKill())
320  isVirtKillInsn = true;
321  continue;
322  }
323  for (MCRegAliasIterator AI(MO.getReg(), TRI, true); AI.isValid(); ++AI)
324  Candidates.reset(*AI);
325  }
326  // If we're not in a virtual reg's live range, this is a valid
327  // restore point.
328  if (!inVirtLiveRange) RestorePointMI = MI;
329 
330  // Update whether we're in the live range of a virtual register
331  if (isVirtKillInsn) inVirtLiveRange = false;
332  if (isVirtDefInsn) inVirtLiveRange = true;
333 
334  // Was our survivor untouched by this instruction?
335  if (Candidates.test(Survivor))
336  continue;
337 
338  // All candidates gone?
339  if (Candidates.none())
340  break;
341 
342  Survivor = Candidates.find_first();
343  }
344  // If we ran off the end, that's where we want to restore.
345  if (MI == ME) RestorePointMI = ME;
346  assert (RestorePointMI != StartMI &&
347  "No available scavenger restore location!");
348 
349  // We ran out of candidates, so stop the search.
350  UseMI = RestorePointMI;
351  return Survivor;
352 }
353 
354 static unsigned getFrameIndexOperandNum(MachineInstr *MI) {
355  unsigned i = 0;
356  while (!MI->getOperand(i).isFI()) {
357  ++i;
358  assert(i < MI->getNumOperands() &&
359  "Instr doesn't have FrameIndex operand!");
360  }
361  return i;
362 }
363 
366  int SPAdj) {
367  // Consider all allocatable registers in the register class initially
368  BitVector Candidates =
369  TRI->getAllocatableSet(*I->getParent()->getParent(), RC);
370 
371  // Exclude all the registers being used by the instruction.
372  for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
373  MachineOperand &MO = I->getOperand(i);
374  if (MO.isReg() && MO.getReg() != 0 && !(MO.isUse() && MO.isUndef()) &&
376  Candidates.reset(MO.getReg());
377  }
378 
379  // Try to find a register that's unused if there is one, as then we won't
380  // have to spill.
381  BitVector Available = getRegsAvailable(RC);
382  Available &= Candidates;
383  if (Available.any())
384  Candidates = Available;
385 
386  // Find the register whose use is furthest away.
388  unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI);
389 
390  // If we found an unused register there is no reason to spill it.
391  if (!isRegUsed(SReg)) {
392  DEBUG(dbgs() << "Scavenged register: " << TRI->getName(SReg) << "\n");
393  return SReg;
394  }
395 
396  // Find an available scavenging slot.
397  unsigned SI;
398  for (SI = 0; SI < Scavenged.size(); ++SI)
399  if (Scavenged[SI].Reg == 0)
400  break;
401 
402  if (SI == Scavenged.size()) {
403  // We need to scavenge a register but have no spill slot, the target
404  // must know how to do it (if not, we'll assert below).
405  Scavenged.push_back(ScavengedInfo());
406  }
407 
408  // Avoid infinite regress
409  Scavenged[SI].Reg = SReg;
410 
411  // If the target knows how to save/restore the register, let it do so;
412  // otherwise, use the emergency stack spill slot.
413  if (!TRI->saveScavengerRegister(*MBB, I, UseMI, RC, SReg)) {
414  // Spill the scavenged register before I.
415  assert(Scavenged[SI].FrameIndex >= 0 &&
416  "Cannot scavenge register without an emergency spill slot!");
417  TII->storeRegToStackSlot(*MBB, I, SReg, true, Scavenged[SI].FrameIndex,
418  RC, TRI);
419  MachineBasicBlock::iterator II = std::prev(I);
420 
421  unsigned FIOperandNum = getFrameIndexOperandNum(II);
422  TRI->eliminateFrameIndex(II, SPAdj, FIOperandNum, this);
423 
424  // Restore the scavenged register before its use (or first terminator).
425  TII->loadRegFromStackSlot(*MBB, UseMI, SReg, Scavenged[SI].FrameIndex,
426  RC, TRI);
427  II = std::prev(UseMI);
428 
429  FIOperandNum = getFrameIndexOperandNum(II);
430  TRI->eliminateFrameIndex(II, SPAdj, FIOperandNum, this);
431  }
432 
433  Scavenged[SI].Restore = std::prev(UseMI);
434 
435  // Doing this here leads to infinite regress.
436  // Scavenged[SI].Reg = SReg;
437 
438  DEBUG(dbgs() << "Scavenged register (with spill): " << TRI->getName(SReg) <<
439  "\n");
440 
441  return SReg;
442 }
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Definition: BitVector.h:192
void push_back(const T &Elt)
Definition: SmallVector.h:222
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
BitVector & set()
Definition: BitVector.h:218
bool isValid() const
Check if the iterator is at the end of the list.
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
Definition: BitVector.h:156
BitVector getPristineRegs(const MachineFunction &MF) const
Return a set of physical registers that are pristine.
virtual bool saveScavengerRegister(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, unsigned Reg) const
saveScavengerRegister - Spill the register so it can be used by the register scavenger.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
bool none() const
none - Returns true if none of the bits are set.
Definition: BitVector.h:150
int find_next(unsigned Prev) const
find_next - Returns the index of the next set bit following the "Prev" bit.
Definition: BitVector.h:165
std::vector< unsigned >::const_iterator livein_iterator
iterator getFirstTerminator()
getFirstTerminator - returns an iterator to the first terminator instruction of this basic block...
bool isDead() const
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
void verify(Pass *p=nullptr, const char *Banner=nullptr) const
verify - Run the current MachineFunction through the machine code verifier, useful for debugger use...
bool any() const
any - Returns true if any bit is set.
Definition: BitVector.h:129
livein_iterator livein_begin() const
void clear()
clear - Clear all bits.
Definition: BitVector.h:187
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MCSuperRegIterator enumerates all super-registers of Reg.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APInt.h:33
bool isReg() const
isReg - Tests if this is a MO_Register operand.
iterator begin() const
begin/end - Return all of the registers in this class.
Reg
All possible values of the reg field in the ModR/M byte.
bool isUndef() const
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:271
void forward()
Move the internal MBB iterator and update register states.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
bool isKill() const
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
MCRegUnitRootIterator enumerates the root registers of a register unit.
BitVector getRegsAvailable(const TargetRegisterClass *RC)
Return all available registers in the register class in Mask.
virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const =0
eliminateFrameIndex - This method must be overriden to eliminate abstract frame indices from instruct...
void enterBasicBlock(MachineBasicBlock *mbb)
Start tracking liveness from the begin of the specific basic block.
BitVector getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const
getAllocatableSet - Returns a bitset indexed by register number indicating if a register is allocatab...
bool isDebugValue() const
Definition: MachineInstr.h:748
bundle_iterator< MachineInstr, instr_iterator > iterator
void clearBitsNotInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
clearBitsNotInMask - Clear a bit in this vector for every '0' bit in Mask.
Definition: BitVector.h:499
livein_iterator livein_end() const
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
void unprocess()
Invert the behavior of forward() on the current instruction (undo the changes to the available regist...
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Load the specified register of the given register class from the specified stack frame index...
bool tracksLiveness() const
tracksLiveness - Returns true when tracking register liveness accurately.
MCRegAliasIterator enumerates all registers aliasing Reg.
BitVector & reset()
Definition: BitVector.h:259
static unsigned getFrameIndexOperandNum(MachineInstr *MI)
virtual void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Store the specified register of the given register class to the specified stack frame index...
MCSubRegIterator enumerates all sub-registers of Reg.
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
MachineOperand class - Representation of each machine instruction operand.
bool test(unsigned Idx) const
Definition: BitVector.h:322
bool isRegUsed(unsigned Reg, bool includeReserved=true) const
Return if a specific register is currently used.
void setRegUsed(unsigned Reg)
Tell the scavenger a register is used.
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:123
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
unsigned getNumRegUnits() const
Return the number of (native) register units in the target.
Representation of each machine instruction.
Definition: MachineInstr.h:51
unsigned FindUnusedReg(const TargetRegisterClass *RegClass) const
Find an unused register of the specified register class.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
#define I(x, y, z)
Definition: MD5.cpp:54
unsigned getReg() const
getReg - Returns the register number.
virtual const TargetInstrInfo * getInstrInfo() const
void initRegState()
Allow resetting register state info for multiple passes over/within the same function.
#define DEBUG(X)
Definition: Debug.h:92
const char * getName(unsigned RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
unsigned scavengeRegister(const TargetRegisterClass *RegClass, MachineBasicBlock::iterator I, int SPAdj)
Make a register of the specific register class available and do the appropriate bookkeeping.