29 #define DEBUG_TYPE "mccodeemitter"
33 X86MCCodeEmitter(
const X86MCCodeEmitter &) =
delete;
34 void operator=(
const X86MCCodeEmitter &) =
delete;
39 : MCII(mcii), Ctx(ctx) {
42 ~X86MCCodeEmitter()
override {}
58 bool Is16BitMemOperand(
const MCInst &
MI,
unsigned Op,
64 if (is16BitMode(STI) && BaseReg.
getReg() == 0 &&
67 if ((BaseReg.
getReg() != 0 &&
68 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.
getReg())) ||
70 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.
getReg())))
75 unsigned GetX86RegNum(
const MCOperand &MO)
const {
76 return Ctx.getRegisterInfo()->getEncodingValue(MO.
getReg()) & 0x7;
88 unsigned char getVEXRegisterEncoding(
const MCInst &MI,
89 unsigned OpNum)
const {
91 unsigned SrcRegNum = GetX86RegNum(MI.
getOperand(OpNum));
97 return (~SrcRegNum) & 0xf;
100 unsigned char getWriteMaskRegisterEncoding(
const MCInst &MI,
101 unsigned OpNum)
const {
103 "Invalid mask register as write-mask!");
104 unsigned MaskRegNum = GetX86RegNum(MI.
getOperand(OpNum));
108 void EmitByte(
unsigned char C,
unsigned &CurByte,
raw_ostream &OS)
const {
113 void EmitConstant(uint64_t Val,
unsigned Size,
unsigned &CurByte,
116 for (
unsigned i = 0; i != Size; ++i) {
117 EmitByte(Val & 255, CurByte, OS);
126 int ImmOffset = 0)
const;
128 inline static unsigned char ModRMByte(
unsigned Mod,
unsigned RegOpcode,
130 assert(Mod < 4 && RegOpcode < 8 && RM < 8 &&
"ModRM Fields out of range!");
131 return RM | (RegOpcode << 3) | (Mod << 6);
134 void EmitRegModRMByte(
const MCOperand &ModRMReg,
unsigned RegOpcodeFld,
136 EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS);
139 void EmitSIBByte(
unsigned SS,
unsigned Index,
unsigned Base,
142 EmitByte(ModRMByte(SS, Index, Base), CurByte, OS);
146 void EmitMemModRMByte(
const MCInst &MI,
unsigned Op,
147 unsigned RegOpcodeField,
148 uint64_t TSFlags,
unsigned &CurByte,
raw_ostream &OS,
156 void EmitVEXOpcodePrefix(uint64_t TSFlags,
unsigned &CurByte,
int MemOperand,
160 void EmitSegmentOverridePrefix(
unsigned &CurByte,
unsigned SegOperand,
163 void EmitOpcodePrefix(uint64_t TSFlags,
unsigned &CurByte,
int MemOperand,
174 return new X86MCCodeEmitter(MCII, Ctx);
180 return Value == (
signed char)Value;
187 "Compressed 8-bit displacement is only valid for EVEX inst.");
191 if (CD8_Scale == 0) {
196 unsigned Mask = CD8_Scale - 1;
197 assert((CD8_Scale & Mask) == 0 &&
"Invalid memory object size.");
200 Value /= (
int)CD8_Scale;
201 bool Ret = (Value == (
signed char)Value);
229 if ((BaseReg.
getReg() != 0 &&
230 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.
getReg())) ||
231 (IndexReg.
getReg() != 0 &&
232 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.
getReg())))
244 if ((BaseReg.
getReg() != 0 &&
245 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.
getReg())) ||
246 (IndexReg.
getReg() != 0 &&
247 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.
getReg())))
266 const MCExpr *RHS =
nullptr;
278 if (S.
getName() !=
"_GLOBAL_OFFSET_TABLE_")
293 void X86MCCodeEmitter::
297 const MCExpr *Expr =
nullptr;
298 if (DispOp.
isImm()) {
304 EmitConstant(DispOp.
getImm()+ImmOffset, Size, CurByte, OS);
318 assert(ImmOffset == 0);
359 EmitConstant(0, Size, CurByte, OS);
362 void X86MCCodeEmitter::EmitMemModRMByte(
const MCInst &
MI,
unsigned Op,
363 unsigned RegOpcodeField,
364 uint64_t TSFlags,
unsigned &CurByte,
372 unsigned BaseReg = Base.
getReg();
376 if (BaseReg == X86::RIP) {
377 assert(is64BitMode(STI) &&
"Rip-relative addressing requires 64-bit mode");
378 assert(IndexReg.
getReg() == 0 &&
"Invalid rip-relative address");
379 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
397 CurByte, OS,
Fixups, -ImmSize);
401 unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U;
405 if (Is16BitMemOperand(MI, Op, STI)) {
418 static const unsigned R16Table[] = { 0, 0, 0, 7, 0, 6, 4, 5 };
419 unsigned RMfield = R16Table[BaseRegNo];
421 assert(RMfield &&
"invalid 16-bit base register");
424 unsigned IndexReg16 = R16Table[GetX86RegNum(IndexReg)];
426 assert(IndexReg16 &&
"invalid 16-bit index register");
428 assert(((IndexReg16 ^ RMfield) & 2) &&
429 "invalid 16-bit base/index register combination");
430 assert(Scale.
getImm() == 1 &&
431 "invalid scale for 16-bit memory reference");
435 RMfield = (RMfield & 1) | ((7 - IndexReg16) << 1);
437 RMfield = (IndexReg16 & 1) | ((7 - RMfield) << 1);
443 EmitByte(ModRMByte(0, RegOpcodeField, RMfield), CurByte, OS);
447 EmitByte(ModRMByte(1, RegOpcodeField, RMfield), CurByte, OS);
452 EmitByte(ModRMByte(2, RegOpcodeField, RMfield), CurByte, OS);
455 EmitByte(ModRMByte(0, RegOpcodeField, 6), CurByte, OS);
476 (!is64BitMode(STI) || BaseReg != 0)) {
479 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
489 EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS);
496 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
504 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
512 EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS);
519 assert(IndexReg.
getReg() != X86::ESP &&
520 IndexReg.
getReg() != X86::RSP &&
"Cannot use ESP as index reg!");
522 bool ForceDisp32 =
false;
523 bool ForceDisp8 =
false;
529 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
531 }
else if (!Disp.
isImm()) {
533 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
535 }
else if (Disp.
getImm() == 0 &&
540 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
543 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
547 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
549 ImmOffset = CDisp8 - Disp.
getImm();
552 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
556 static const unsigned SSTable[] = { ~0U, 0, 1, ~0U, 2, ~0U, ~0U, ~0U, 3 };
557 unsigned SS = SSTable[Scale.
getImm()];
564 IndexRegNo = GetX86RegNum(IndexReg);
567 EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS);
571 IndexRegNo = GetX86RegNum(IndexReg);
574 EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS);
580 else if (ForceDisp32 || Disp.
getImm() != 0)
587 void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags,
unsigned &CurByte,
588 int MemOperand,
const MCInst &MI,
591 assert(!(TSFlags &
X86II::LOCK) &&
"Can't have LOCK VEX.");
606 unsigned char VEX_R = 0x1;
607 unsigned char EVEX_R2 = 0x1;
614 unsigned char VEX_X = 0x1;
621 unsigned char VEX_B = 0x1;
625 unsigned char VEX_W = 0;
637 unsigned char VEX_5M = 0;
641 unsigned char VEX_4V = 0xf;
642 unsigned char EVEX_V2 = 0x1;
649 unsigned char VEX_L = 0;
660 unsigned char VEX_PP = 0;
663 unsigned char EVEX_U = 1;
666 unsigned char EVEX_z = 0;
669 unsigned char EVEX_b = 0;
672 unsigned char EVEX_rc = 0;
675 unsigned char EVEX_aaa = 0;
677 bool EncodeRC =
false;
737 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
740 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
772 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
775 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
807 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
814 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
840 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
843 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
858 VEX_4V = getVEXRegisterEncoding(MI, CurOp++);
861 unsigned RcOperand = NumOps-1;
862 assert(RcOperand >= CurOp);
880 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
883 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
903 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
909 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
934 unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3);
937 if (Encoding ==
X86II::VEX && VEX_B && VEX_X && !VEX_W && (VEX_5M == 1)) {
938 EmitByte(0xC5, CurByte, OS);
939 EmitByte(LastByte | (VEX_R << 7), CurByte, OS);
944 EmitByte(Encoding ==
X86II::XOP ? 0x8F : 0xC4, CurByte, OS);
945 EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M, CurByte, OS);
946 EmitByte(LastByte | (VEX_W << 7), CurByte, OS);
948 assert(Encoding ==
X86II::EVEX &&
"unknown encoding!");
954 assert((VEX_5M & 0x3) == VEX_5M
955 &&
"More than 2 significant bits in VEX.m-mmmm fields for EVEX!");
959 EmitByte(0x62, CurByte, OS);
960 EmitByte((VEX_R << 7) |
964 VEX_5M, CurByte, OS);
965 EmitByte((VEX_W << 7) |
968 VEX_PP, CurByte, OS);
970 EmitByte((EVEX_z << 7) |
974 EVEX_aaa, CurByte, OS);
976 EmitByte((EVEX_z << 7) |
981 EVEX_aaa, CurByte, OS);
998 bool isTwoAddr = NumOps > 1 &&
1002 unsigned i = isTwoAddr ? 1 : 0;
1003 for (; i != NumOps; ++i) {
1005 if (!MO.
isReg())
continue;
1014 switch (TSFlags & X86II::FormMask) {
1019 i = isTwoAddr ? 2 : 1;
1020 for (; i != NumOps; ++i) {
1031 i = isTwoAddr ? 2 : 1;
1032 for (; i != NumOps; ++i) {
1049 i = isTwoAddr ? 1 : 0;
1054 for (; i != e; ++i) {
1068 i = isTwoAddr ? 2 : 1;
1069 for (
unsigned e = NumOps; i != e; ++i) {
1080 void X86MCCodeEmitter::EmitSegmentOverridePrefix(
unsigned &CurByte,
1081 unsigned SegOperand,
1088 case X86::CS: EmitByte(0x2E, CurByte, OS);
break;
1089 case X86::SS: EmitByte(0x36, CurByte, OS);
break;
1090 case X86::DS: EmitByte(0x3E, CurByte, OS);
break;
1091 case X86::ES: EmitByte(0x26, CurByte, OS);
break;
1092 case X86::FS: EmitByte(0x64, CurByte, OS);
break;
1093 case X86::GS: EmitByte(0x65, CurByte, OS);
break;
1101 void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags,
unsigned &CurByte,
1102 int MemOperand,
const MCInst &MI,
1110 EmitByte(0x66, CurByte, OS);
1114 EmitByte(0xF0, CurByte, OS);
1116 switch (TSFlags & X86II::OpPrefixMask) {
1118 EmitByte(0x66, CurByte, OS);
1121 EmitByte(0xF3, CurByte, OS);
1124 EmitByte(0xF2, CurByte, OS);
1130 if (is64BitMode(STI)) {
1132 EmitByte(0x40 | REX, CurByte, OS);
1136 switch (TSFlags & X86II::OpMapMask) {
1140 EmitByte(0x0F, CurByte, OS);
1144 switch (TSFlags & X86II::OpMapMask) {
1146 EmitByte(0x38, CurByte, OS);
1149 EmitByte(0x3A, CurByte, OS);
1154 void X86MCCodeEmitter::
1160 uint64_t TSFlags = Desc.
TSFlags;
1170 unsigned CurByte = 0;
1179 const unsigned MemOp4_I8IMMOperand = 2;
1187 if (MemoryOperand != -1) MemoryOperand += CurOp;
1190 if (MemoryOperand >= 0)
1196 EmitByte(0xF3, CurByte, OS);
1199 bool need_address_override;
1204 need_address_override =
true;
1205 }
else if (MemoryOperand < 0) {
1206 need_address_override =
false;
1207 }
else if (is64BitMode(STI)) {
1208 assert(!Is16BitMemOperand(MI, MemoryOperand, STI));
1210 }
else if (is32BitMode(STI)) {
1212 need_address_override = Is16BitMemOperand(MI, MemoryOperand, STI);
1214 assert(is16BitMode(STI));
1216 need_address_override = !Is16BitMemOperand(MI, MemoryOperand, STI);
1219 if (need_address_override)
1220 EmitByte(0x67, CurByte, OS);
1223 EmitOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, STI, OS);
1225 EmitVEXOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS);
1232 unsigned SrcRegNum = 0;
1233 switch (TSFlags & X86II::FormMask) {
1243 "SI and DI register sizes do not match");
1246 EmitSegmentOverridePrefix(CurByte, 2, MI, OS);
1248 if ((!is32BitMode(STI) && siReg == X86::ESI) ||
1249 (is32BitMode(STI) && siReg == X86::SI))
1250 EmitByte(0x67, CurByte, OS);
1252 EmitByte(BaseOpcode, CurByte, OS);
1259 EmitSegmentOverridePrefix(CurByte, 1, MI, OS);
1261 if ((!is32BitMode(STI) && siReg == X86::ESI) ||
1262 (is32BitMode(STI) && siReg == X86::SI))
1263 EmitByte(0x67, CurByte, OS);
1265 EmitByte(BaseOpcode, CurByte, OS);
1271 if ((!is32BitMode(STI) && siReg == X86::EDI) ||
1272 (is32BitMode(STI) && siReg == X86::DI))
1273 EmitByte(0x67, CurByte, OS);
1275 EmitByte(BaseOpcode, CurByte, OS);
1279 EmitByte(BaseOpcode, CurByte, OS);
1283 EmitSegmentOverridePrefix(CurByte, 1, MI, OS);
1284 EmitByte(BaseOpcode, CurByte, OS);
1291 EmitByte(BaseOpcode, CurByte, OS);
1299 EmitByte(BaseOpcode, CurByte, OS);
1308 EmitByte(BaseOpcode + GetX86RegNum(MI.
getOperand(CurOp++)), CurByte, OS);
1312 EmitByte(BaseOpcode, CurByte, OS);
1313 SrcRegNum = CurOp + 1;
1322 GetX86RegNum(MI.
getOperand(SrcRegNum)), CurByte, OS);
1323 CurOp = SrcRegNum + 1;
1327 EmitByte(BaseOpcode, CurByte, OS);
1336 EmitMemModRMByte(MI, CurOp,
1338 TSFlags, CurByte, OS, Fixups, STI);
1339 CurOp = SrcRegNum + 1;
1343 EmitByte(BaseOpcode, CurByte, OS);
1344 SrcRegNum = CurOp + 1;
1356 GetX86RegNum(MI.
getOperand(CurOp)), CurByte, OS);
1359 CurOp = HasMemOp4 ? SrcRegNum : SrcRegNum + 1;
1369 unsigned FirstMemOp = CurOp+1;
1383 EmitByte(BaseOpcode, CurByte, OS);
1385 EmitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.
getOperand(CurOp)),
1386 TSFlags, CurByte, OS, Fixups, STI);
1387 CurOp += AddrOperands + 1;
1402 EmitByte(BaseOpcode, CurByte, OS);
1419 EmitByte(BaseOpcode, CurByte, OS);
1422 TSFlags, CurByte, OS, Fixups, STI);
1448 EmitByte(BaseOpcode, CurByte, OS);
1458 while (CurOp != NumOps && NumOps - CurOp <= 2) {
1465 unsigned RegNum = GetX86RegNum(MO) << 4;
1470 if (CurOp != NumOps) {
1473 unsigned Val = MIMM.
getImm();
1474 assert(Val < 16 &&
"Immediate operand value out of range");
1487 if (TSFlags & X86II::Has3DNow0F0FOpcode)
1492 if ( CurOp != NumOps) {
1493 errs() <<
"Cannot encode all operands of: ";
static bool HasSecRelSymbolRef(const MCExpr *Expr)
void push_back(const T &Elt)
MRMX[rm] - The forms are used to represent instructions that use a Mod/RM byte, and don't use the mid...
static bool Is64BitMemOperand(const MCInst &MI, unsigned Op)
Is64BitMemOperand - Return true if the specified instruction has a 64-bit memory operand.
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
AddrSegmentReg - The operand # of the segment in the memory operand.
bool isX86_64NonExtLowByteReg(unsigned reg)
const MCSymbol & getSymbol() const
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
static bool isDisp8(int Value)
isDisp8 - Return true if this signed displacement fits in a 8-bit sign-extended field.
RawFrmSrc - This form is for instructions that use the source index register SI/ESI/ERI with a possib...
Describe properties that are true of each instruction in the target description file.
RawFrmSrc - This form is for instructions that use the source index register SI/ESI/RSI with a possib...
static GlobalOffsetTableExprKind StartsWithGlobalOffsetTable(const MCExpr *Expr)
MRMDestMem - This form is used for instructions that use the Mod/RM byte to specify a destination...
static MCFixupKind getKindForSize(unsigned Size, bool isPCRel)
Return the generic fixup kind for a value with the given size.
int getOperandBias(const MCInstrDesc &Desc)
getOperandBias - compute any additional adjustment needed to the offset to the start of the memory op...
unsigned isImmPCRel(uint64_t TSFlags)
isImmPCRel - Return true if the immediate of the specified instruction's TSFlags indicates that it is...
A one-byte pc relative fixup.
MCCodeEmitter * createX86MCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Base class for the full range of assembler expressions which are needed for parsing.
Reg
All possible values of the reg field in the ModR/M byte.
Represent a reference to a symbol from inside an expression.
A four-byte section relative fixup.
Context object for machine code objects.
AddrNumOperands - Total number of operands in a memory reference.
unsigned getReg() const
Returns the register number.
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
bool hasImm(uint64_t TSFlags)
static bool isCDisp8(uint64_t TSFlags, int Value, int &CValue)
isCDisp8 - Return true if this signed displacement fits in a 8-bit compressed dispacement field...
Instances of this class represent a single low-level machine instruction.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
bool isX86_64ExtendedReg(unsigned RegNo)
isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or higher) register? e.g.
const MCExpr * getExpr() const
static MCFixupKind getImmFixupKind(uint64_t TSFlags)
getImmFixupKind - Return the appropriate fixup kind to use for an immediate in an instruction with th...
const MCExpr * getLHS() const
Get the left-hand side expression of the binary operator.
MRM[0-7][rm] - These forms are used to represent instructions that use a Mod/RM byte, and use the middle field to hold extended opcode information.
MRMDestReg - This form is used for instructions that use the Mod/RM byte to specify a destination...
MCCodeEmitter - Generic instruction encoding interface.
Interface to description of machine instruction set.
XOP - Opcode prefix used by XOP instructions.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
unsigned isImmSigned(uint64_t TSFlags)
isImmSigned - Return true if the immediate of the specified instruction's TSFlags indicates that it i...
Binary assembler expressions.
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
static bool Is32BitMemOperand(const MCInst &MI, unsigned Op)
Is32BitMemOperand - Return true if the specified instruction has a 32-bit memory operand.
static bool is32ExtendedReg(unsigned RegNo)
is32ExtendedReg - Is the MemoryOperand a 32 extended (zmm16 or higher) registers? e...
A two-byte pc relative fixup.
MRMSrcReg - This form is used for instructions that use the Mod/RM byte to specify a source...
static unsigned DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags, const MCInstrDesc &Desc)
DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64 REX prefix which specifi...
A four-byte pc relative fixup.
RawFrmImm16 - This is used for CALL FAR instructions, which have two immediates, the first of which i...
unsigned char getBaseOpcodeFor(uint64_t TSFlags)
Raw - This form is for instructions that don't have any operands, so they are just a fixed opcode val...
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
unsigned getOpcode() const
AddRegFrm - This form is used for instructions like 'push r32' that have their one register operand a...
const MCExpr * getRHS() const
Get the right-hand side expression of the binary operator.
RawFrmImm8 - This is used for the ENTER instruction, which has two immediates, the first of which is ...
StringRef getName() const
getName - Get the symbol name.
MRMSrcMem - This form is used for instructions that use the Mod/RM byte to specify a source...
unsigned getSizeOfImm(uint64_t TSFlags)
getSizeOfImm - Decode the "size of immediate" field from the TSFlags field of the specified instructi...
unsigned getNumOperands() const
MCSubtargetInfo - Generic base class for all target subtargets.
References to labels and assigned expressions.
RawFrmDst - This form is for instructions that use the destination index register DI/EDI/ESI...
VariantKind getKind() const
const ARM::ArchExtKind Kind
int getMemoryOperandNo(uint64_t TSFlags, unsigned Opcode)
getMemoryOperandNo - The function returns the MCInst operand # for the first field of the memory oper...
LLVM Value Representation.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
RawFrmMemOffs - This form is for instructions that store an absolute memory offset as an immediate wi...
This class implements an extremely fast bulk output stream that can only output to a stream...
GlobalOffsetTableExprKind
StartsWithGlobalOffsetTable - Check if this expression starts with GLOBAL_OFFSET_TABLE and if it is o...
Represents a location in source code.
Instances of this class represent operands of the MCInst class.
static MCOperand createImm(int64_t Val)
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx)
const MCOperand & getOperand(unsigned i) const