LLVM  3.7.0
SparcISelLowering.cpp
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1 //===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the interfaces that Sparc uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "SparcISelLowering.h"
18 #include "SparcRegisterInfo.h"
19 #include "SparcTargetMachine.h"
20 #include "SparcTargetObjectFile.h"
28 #include "llvm/IR/DerivedTypes.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/Module.h"
32 using namespace llvm;
33 
34 
35 //===----------------------------------------------------------------------===//
36 // Calling Convention Implementation
37 //===----------------------------------------------------------------------===//
38 
39 static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT,
40  MVT &LocVT, CCValAssign::LocInfo &LocInfo,
41  ISD::ArgFlagsTy &ArgFlags, CCState &State)
42 {
43  assert (ArgFlags.isSRet());
44 
45  // Assign SRet argument.
46  State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
47  0,
48  LocVT, LocInfo));
49  return true;
50 }
51 
52 static bool CC_Sparc_Assign_f64(unsigned &ValNo, MVT &ValVT,
53  MVT &LocVT, CCValAssign::LocInfo &LocInfo,
54  ISD::ArgFlagsTy &ArgFlags, CCState &State)
55 {
56  static const MCPhysReg RegList[] = {
57  SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
58  };
59  // Try to get first reg.
60  if (unsigned Reg = State.AllocateReg(RegList)) {
61  State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
62  } else {
63  // Assign whole thing in stack.
64  State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
65  State.AllocateStack(8,4),
66  LocVT, LocInfo));
67  return true;
68  }
69 
70  // Try to get second reg.
71  if (unsigned Reg = State.AllocateReg(RegList))
72  State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
73  else
74  State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
75  State.AllocateStack(4,4),
76  LocVT, LocInfo));
77  return true;
78 }
79 
80 // Allocate a full-sized argument for the 64-bit ABI.
81 static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT,
82  MVT &LocVT, CCValAssign::LocInfo &LocInfo,
83  ISD::ArgFlagsTy &ArgFlags, CCState &State) {
84  assert((LocVT == MVT::f32 || LocVT == MVT::f128
85  || LocVT.getSizeInBits() == 64) &&
86  "Can't handle non-64 bits locations");
87 
88  // Stack space is allocated for all arguments starting from [%fp+BIAS+128].
89  unsigned size = (LocVT == MVT::f128) ? 16 : 8;
90  unsigned alignment = (LocVT == MVT::f128) ? 16 : 8;
91  unsigned Offset = State.AllocateStack(size, alignment);
92  unsigned Reg = 0;
93 
94  if (LocVT == MVT::i64 && Offset < 6*8)
95  // Promote integers to %i0-%i5.
96  Reg = SP::I0 + Offset/8;
97  else if (LocVT == MVT::f64 && Offset < 16*8)
98  // Promote doubles to %d0-%d30. (Which LLVM calls D0-D15).
99  Reg = SP::D0 + Offset/8;
100  else if (LocVT == MVT::f32 && Offset < 16*8)
101  // Promote floats to %f1, %f3, ...
102  Reg = SP::F1 + Offset/4;
103  else if (LocVT == MVT::f128 && Offset < 16*8)
104  // Promote long doubles to %q0-%q28. (Which LLVM calls Q0-Q7).
105  Reg = SP::Q0 + Offset/16;
106 
107  // Promote to register when possible, otherwise use the stack slot.
108  if (Reg) {
109  State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
110  return true;
111  }
112 
113  // This argument goes on the stack in an 8-byte slot.
114  // When passing floats, LocVT is smaller than 8 bytes. Adjust the offset to
115  // the right-aligned float. The first 4 bytes of the stack slot are undefined.
116  if (LocVT == MVT::f32)
117  Offset += 4;
118 
119  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
120  return true;
121 }
122 
123 // Allocate a half-sized argument for the 64-bit ABI.
124 //
125 // This is used when passing { float, int } structs by value in registers.
126 static bool CC_Sparc64_Half(unsigned &ValNo, MVT &ValVT,
127  MVT &LocVT, CCValAssign::LocInfo &LocInfo,
128  ISD::ArgFlagsTy &ArgFlags, CCState &State) {
129  assert(LocVT.getSizeInBits() == 32 && "Can't handle non-32 bits locations");
130  unsigned Offset = State.AllocateStack(4, 4);
131 
132  if (LocVT == MVT::f32 && Offset < 16*8) {
133  // Promote floats to %f0-%f31.
134  State.addLoc(CCValAssign::getReg(ValNo, ValVT, SP::F0 + Offset/4,
135  LocVT, LocInfo));
136  return true;
137  }
138 
139  if (LocVT == MVT::i32 && Offset < 6*8) {
140  // Promote integers to %i0-%i5, using half the register.
141  unsigned Reg = SP::I0 + Offset/8;
142  LocVT = MVT::i64;
143  LocInfo = CCValAssign::AExt;
144 
145  // Set the Custom bit if this i32 goes in the high bits of a register.
146  if (Offset % 8 == 0)
147  State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg,
148  LocVT, LocInfo));
149  else
150  State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
151  return true;
152  }
153 
154  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
155  return true;
156 }
157 
158 #include "SparcGenCallingConv.inc"
159 
160 // The calling conventions in SparcCallingConv.td are described in terms of the
161 // callee's register window. This function translates registers to the
162 // corresponding caller window %o register.
163 static unsigned toCallerWindow(unsigned Reg) {
164  assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7 && "Unexpected enum");
165  if (Reg >= SP::I0 && Reg <= SP::I7)
166  return Reg - SP::I0 + SP::O0;
167  return Reg;
168 }
169 
170 SDValue
172  CallingConv::ID CallConv, bool IsVarArg,
174  const SmallVectorImpl<SDValue> &OutVals,
175  SDLoc DL, SelectionDAG &DAG) const {
176  if (Subtarget->is64Bit())
177  return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
178  return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
179 }
180 
181 SDValue
183  CallingConv::ID CallConv, bool IsVarArg,
185  const SmallVectorImpl<SDValue> &OutVals,
186  SDLoc DL, SelectionDAG &DAG) const {
188 
189  // CCValAssign - represent the assignment of the return value to locations.
191 
192  // CCState - Info about the registers and stack slot.
193  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
194  *DAG.getContext());
195 
196  // Analyze return values.
197  CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32);
198 
199  SDValue Flag;
200  SmallVector<SDValue, 4> RetOps(1, Chain);
201  // Make room for the return address offset.
202  RetOps.push_back(SDValue());
203 
204  // Copy the result values into the output registers.
205  for (unsigned i = 0; i != RVLocs.size(); ++i) {
206  CCValAssign &VA = RVLocs[i];
207  assert(VA.isRegLoc() && "Can only return in registers!");
208 
209  Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(),
210  OutVals[i], Flag);
211 
212  // Guarantee that all emitted copies are stuck together with flags.
213  Flag = Chain.getValue(1);
214  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
215  }
216 
217  unsigned RetAddrOffset = 8; // Call Inst + Delay Slot
218  // If the function returns a struct, copy the SRetReturnReg to I0
219  if (MF.getFunction()->hasStructRetAttr()) {
221  unsigned Reg = SFI->getSRetReturnReg();
222  if (!Reg)
223  llvm_unreachable("sret virtual register not created in the entry block");
224  auto PtrVT = getPointerTy(DAG.getDataLayout());
225  SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, PtrVT);
226  Chain = DAG.getCopyToReg(Chain, DL, SP::I0, Val, Flag);
227  Flag = Chain.getValue(1);
228  RetOps.push_back(DAG.getRegister(SP::I0, PtrVT));
229  RetAddrOffset = 12; // CallInst + Delay Slot + Unimp
230  }
231 
232  RetOps[0] = Chain; // Update chain.
233  RetOps[1] = DAG.getConstant(RetAddrOffset, DL, MVT::i32);
234 
235  // Add the flag if we have it.
236  if (Flag.getNode())
237  RetOps.push_back(Flag);
238 
239  return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, RetOps);
240 }
241 
242 // Lower return values for the 64-bit ABI.
243 // Return values are passed the exactly the same way as function arguments.
244 SDValue
246  CallingConv::ID CallConv, bool IsVarArg,
248  const SmallVectorImpl<SDValue> &OutVals,
249  SDLoc DL, SelectionDAG &DAG) const {
250  // CCValAssign - represent the assignment of the return value to locations.
252 
253  // CCState - Info about the registers and stack slot.
254  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
255  *DAG.getContext());
256 
257  // Analyze return values.
258  CCInfo.AnalyzeReturn(Outs, RetCC_Sparc64);
259 
260  SDValue Flag;
261  SmallVector<SDValue, 4> RetOps(1, Chain);
262 
263  // The second operand on the return instruction is the return address offset.
264  // The return address is always %i7+8 with the 64-bit ABI.
265  RetOps.push_back(DAG.getConstant(8, DL, MVT::i32));
266 
267  // Copy the result values into the output registers.
268  for (unsigned i = 0; i != RVLocs.size(); ++i) {
269  CCValAssign &VA = RVLocs[i];
270  assert(VA.isRegLoc() && "Can only return in registers!");
271  SDValue OutVal = OutVals[i];
272 
273  // Integer return values must be sign or zero extended by the callee.
274  switch (VA.getLocInfo()) {
275  case CCValAssign::Full: break;
276  case CCValAssign::SExt:
277  OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal);
278  break;
279  case CCValAssign::ZExt:
280  OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal);
281  break;
282  case CCValAssign::AExt:
283  OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal);
284  break;
285  default:
286  llvm_unreachable("Unknown loc info!");
287  }
288 
289  // The custom bit on an i32 return value indicates that it should be passed
290  // in the high bits of the register.
291  if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
292  OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal,
293  DAG.getConstant(32, DL, MVT::i32));
294 
295  // The next value may go in the low bits of the same register.
296  // Handle both at once.
297  if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) {
298  SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, OutVals[i+1]);
299  OutVal = DAG.getNode(ISD::OR, DL, MVT::i64, OutVal, NV);
300  // Skip the next value, it's already done.
301  ++i;
302  }
303  }
304 
305  Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag);
306 
307  // Guarantee that all emitted copies are stuck together with flags.
308  Flag = Chain.getValue(1);
309  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
310  }
311 
312  RetOps[0] = Chain; // Update chain.
313 
314  // Add the flag if we have it.
315  if (Flag.getNode())
316  RetOps.push_back(Flag);
317 
318  return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, RetOps);
319 }
320 
323  CallingConv::ID CallConv,
324  bool IsVarArg,
326  SDLoc DL,
327  SelectionDAG &DAG,
328  SmallVectorImpl<SDValue> &InVals) const {
329  if (Subtarget->is64Bit())
330  return LowerFormalArguments_64(Chain, CallConv, IsVarArg, Ins,
331  DL, DAG, InVals);
332  return LowerFormalArguments_32(Chain, CallConv, IsVarArg, Ins,
333  DL, DAG, InVals);
334 }
335 
336 /// LowerFormalArguments32 - V8 uses a very simple ABI, where all values are
337 /// passed in either one or two GPRs, including FP values. TODO: we should
338 /// pass FP values in FP registers for fastcc functions.
341  CallingConv::ID CallConv,
342  bool isVarArg,
344  SDLoc dl,
345  SelectionDAG &DAG,
346  SmallVectorImpl<SDValue> &InVals) const {
348  MachineRegisterInfo &RegInfo = MF.getRegInfo();
350 
351  // Assign locations to all of the incoming arguments.
353  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
354  *DAG.getContext());
355  CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32);
356 
357  const unsigned StackOffset = 92;
358 
359  unsigned InIdx = 0;
360  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i, ++InIdx) {
361  CCValAssign &VA = ArgLocs[i];
362 
363  if (Ins[InIdx].Flags.isSRet()) {
364  if (InIdx != 0)
365  report_fatal_error("sparc only supports sret on the first parameter");
366  // Get SRet from [%fp+64].
367  int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, 64, true);
368  SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
369  SDValue Arg = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
371  false, false, false, 0);
372  InVals.push_back(Arg);
373  continue;
374  }
375 
376  if (VA.isRegLoc()) {
377  if (VA.needsCustom()) {
378  assert(VA.getLocVT() == MVT::f64);
379  unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
380  MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi);
381  SDValue HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32);
382 
383  assert(i+1 < e);
384  CCValAssign &NextVA = ArgLocs[++i];
385 
386  SDValue LoVal;
387  if (NextVA.isMemLoc()) {
388  int FrameIdx = MF.getFrameInfo()->
389  CreateFixedObject(4, StackOffset+NextVA.getLocMemOffset(),true);
390  SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
391  LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
393  false, false, false, 0);
394  } else {
395  unsigned loReg = MF.addLiveIn(NextVA.getLocReg(),
396  &SP::IntRegsRegClass);
397  LoVal = DAG.getCopyFromReg(Chain, dl, loReg, MVT::i32);
398  }
399  SDValue WholeValue =
400  DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
401  WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue);
402  InVals.push_back(WholeValue);
403  continue;
404  }
405  unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
406  MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg);
407  SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
408  if (VA.getLocVT() == MVT::f32)
409  Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg);
410  else if (VA.getLocVT() != MVT::i32) {
411  Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg,
412  DAG.getValueType(VA.getLocVT()));
413  Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg);
414  }
415  InVals.push_back(Arg);
416  continue;
417  }
418 
419  assert(VA.isMemLoc());
420 
421  unsigned Offset = VA.getLocMemOffset()+StackOffset;
422  auto PtrVT = getPointerTy(DAG.getDataLayout());
423 
424  if (VA.needsCustom()) {
425  assert(VA.getValVT() == MVT::f64);
426  // If it is double-word aligned, just load.
427  if (Offset % 8 == 0) {
428  int FI = MF.getFrameInfo()->CreateFixedObject(8,
429  Offset,
430  true);
431  SDValue FIPtr = DAG.getFrameIndex(FI, PtrVT);
432  SDValue Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr,
434  false,false, false, 0);
435  InVals.push_back(Load);
436  continue;
437  }
438 
439  int FI = MF.getFrameInfo()->CreateFixedObject(4,
440  Offset,
441  true);
442  SDValue FIPtr = DAG.getFrameIndex(FI, PtrVT);
443  SDValue HiVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
445  false, false, false, 0);
446  int FI2 = MF.getFrameInfo()->CreateFixedObject(4,
447  Offset+4,
448  true);
449  SDValue FIPtr2 = DAG.getFrameIndex(FI2, PtrVT);
450 
451  SDValue LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr2,
453  false, false, false, 0);
454 
455  SDValue WholeValue =
456  DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
457  WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue);
458  InVals.push_back(WholeValue);
459  continue;
460  }
461 
462  int FI = MF.getFrameInfo()->CreateFixedObject(4,
463  Offset,
464  true);
465  SDValue FIPtr = DAG.getFrameIndex(FI, PtrVT);
466  SDValue Load ;
467  if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) {
468  Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr,
470  false, false, false, 0);
471  } else {
473  // Sparc is big endian, so add an offset based on the ObjectVT.
474  unsigned Offset = 4-std::max(1U, VA.getValVT().getSizeInBits()/8);
475  FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr,
476  DAG.getConstant(Offset, dl, MVT::i32));
477  Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Chain, FIPtr,
479  VA.getValVT(), false, false, false,0);
480  Load = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Load);
481  }
482  InVals.push_back(Load);
483  }
484 
485  if (MF.getFunction()->hasStructRetAttr()) {
486  // Copy the SRet Argument to SRetReturnReg.
488  unsigned Reg = SFI->getSRetReturnReg();
489  if (!Reg) {
490  Reg = MF.getRegInfo().createVirtualRegister(&SP::IntRegsRegClass);
491  SFI->setSRetReturnReg(Reg);
492  }
493  SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
494  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
495  }
496 
497  // Store remaining ArgRegs to the stack if this is a varargs function.
498  if (isVarArg) {
499  static const MCPhysReg ArgRegs[] = {
500  SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
501  };
502  unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs);
503  const MCPhysReg *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6;
504  unsigned ArgOffset = CCInfo.getNextStackOffset();
505  if (NumAllocated == 6)
506  ArgOffset += StackOffset;
507  else {
508  assert(!ArgOffset);
509  ArgOffset = 68+4*NumAllocated;
510  }
511 
512  // Remember the vararg offset for the va_start implementation.
513  FuncInfo->setVarArgsFrameOffset(ArgOffset);
514 
515  std::vector<SDValue> OutChains;
516 
517  for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
518  unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
519  MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
520  SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32);
521 
522  int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset,
523  true);
524  SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
525 
526  OutChains.push_back(DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr,
528  false, false, 0));
529  ArgOffset += 4;
530  }
531 
532  if (!OutChains.empty()) {
533  OutChains.push_back(Chain);
534  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
535  }
536  }
537 
538  return Chain;
539 }
540 
541 // Lower formal arguments for the 64 bit ABI.
544  CallingConv::ID CallConv,
545  bool IsVarArg,
547  SDLoc DL,
548  SelectionDAG &DAG,
549  SmallVectorImpl<SDValue> &InVals) const {
551 
552  // Analyze arguments according to CC_Sparc64.
554  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
555  *DAG.getContext());
556  CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc64);
557 
558  // The argument array begins at %fp+BIAS+128, after the register save area.
559  const unsigned ArgArea = 128;
560 
561  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
562  CCValAssign &VA = ArgLocs[i];
563  if (VA.isRegLoc()) {
564  // This argument is passed in a register.
565  // All integer register arguments are promoted by the caller to i64.
566 
567  // Create a virtual register for the promoted live-in value.
568  unsigned VReg = MF.addLiveIn(VA.getLocReg(),
569  getRegClassFor(VA.getLocVT()));
570  SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT());
571 
572  // Get the high bits for i32 struct elements.
573  if (VA.getValVT() == MVT::i32 && VA.needsCustom())
574  Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg,
575  DAG.getConstant(32, DL, MVT::i32));
576 
577  // The caller promoted the argument, so insert an Assert?ext SDNode so we
578  // won't promote the value again in this function.
579  switch (VA.getLocInfo()) {
580  case CCValAssign::SExt:
581  Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg,
582  DAG.getValueType(VA.getValVT()));
583  break;
584  case CCValAssign::ZExt:
585  Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg,
586  DAG.getValueType(VA.getValVT()));
587  break;
588  default:
589  break;
590  }
591 
592  // Truncate the register down to the argument type.
593  if (VA.isExtInLoc())
594  Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
595 
596  InVals.push_back(Arg);
597  continue;
598  }
599 
600  // The registers are exhausted. This argument was passed on the stack.
601  assert(VA.isMemLoc());
602  // The CC_Sparc64_Full/Half functions compute stack offsets relative to the
603  // beginning of the arguments area at %fp+BIAS+128.
604  unsigned Offset = VA.getLocMemOffset() + ArgArea;
605  unsigned ValSize = VA.getValVT().getSizeInBits() / 8;
606  // Adjust offset for extended arguments, SPARC is big-endian.
607  // The caller will have written the full slot with extended bytes, but we
608  // prefer our own extending loads.
609  if (VA.isExtInLoc())
610  Offset += 8 - ValSize;
611  int FI = MF.getFrameInfo()->CreateFixedObject(ValSize, Offset, true);
612  InVals.push_back(DAG.getLoad(
613  VA.getValVT(), DL, Chain,
615  MachinePointerInfo::getFixedStack(FI), false, false, false, 0));
616  }
617 
618  if (!IsVarArg)
619  return Chain;
620 
621  // This function takes variable arguments, some of which may have been passed
622  // in registers %i0-%i5. Variable floating point arguments are never passed
623  // in floating point registers. They go on %i0-%i5 or on the stack like
624  // integer arguments.
625  //
626  // The va_start intrinsic needs to know the offset to the first variable
627  // argument.
628  unsigned ArgOffset = CCInfo.getNextStackOffset();
630  // Skip the 128 bytes of register save area.
631  FuncInfo->setVarArgsFrameOffset(ArgOffset + ArgArea +
632  Subtarget->getStackPointerBias());
633 
634  // Save the variable arguments that were passed in registers.
635  // The caller is required to reserve stack space for 6 arguments regardless
636  // of how many arguments were actually passed.
637  SmallVector<SDValue, 8> OutChains;
638  for (; ArgOffset < 6*8; ArgOffset += 8) {
639  unsigned VReg = MF.addLiveIn(SP::I0 + ArgOffset/8, &SP::I64RegsRegClass);
640  SDValue VArg = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
641  int FI = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset + ArgArea, true);
642  auto PtrVT = getPointerTy(MF.getDataLayout());
643  OutChains.push_back(
644  DAG.getStore(Chain, DL, VArg, DAG.getFrameIndex(FI, PtrVT),
645  MachinePointerInfo::getFixedStack(FI), false, false, 0));
646  }
647 
648  if (!OutChains.empty())
649  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
650 
651  return Chain;
652 }
653 
654 SDValue
656  SmallVectorImpl<SDValue> &InVals) const {
657  if (Subtarget->is64Bit())
658  return LowerCall_64(CLI, InVals);
659  return LowerCall_32(CLI, InVals);
660 }
661 
662 static bool hasReturnsTwiceAttr(SelectionDAG &DAG, SDValue Callee,
663  ImmutableCallSite *CS) {
664  if (CS)
666 
667  const Function *CalleeFn = nullptr;
668  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
669  CalleeFn = dyn_cast<Function>(G->getGlobal());
670  } else if (ExternalSymbolSDNode *E =
671  dyn_cast<ExternalSymbolSDNode>(Callee)) {
672  const Function *Fn = DAG.getMachineFunction().getFunction();
673  const Module *M = Fn->getParent();
674  const char *CalleeName = E->getSymbol();
675  CalleeFn = M->getFunction(CalleeName);
676  }
677 
678  if (!CalleeFn)
679  return false;
680  return CalleeFn->hasFnAttribute(Attribute::ReturnsTwice);
681 }
682 
683 // Lower a call for the 32-bit ABI.
684 SDValue
686  SmallVectorImpl<SDValue> &InVals) const {
687  SelectionDAG &DAG = CLI.DAG;
688  SDLoc &dl = CLI.DL;
690  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
692  SDValue Chain = CLI.Chain;
693  SDValue Callee = CLI.Callee;
694  bool &isTailCall = CLI.IsTailCall;
695  CallingConv::ID CallConv = CLI.CallConv;
696  bool isVarArg = CLI.IsVarArg;
697 
698  // Sparc target does not yet support tail call optimization.
699  isTailCall = false;
700 
701  // Analyze operands of the call, assigning locations to each operand.
703  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
704  *DAG.getContext());
705  CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32);
706 
707  // Get the size of the outgoing arguments stack space requirement.
708  unsigned ArgsSize = CCInfo.getNextStackOffset();
709 
710  // Keep stack frames 8-byte aligned.
711  ArgsSize = (ArgsSize+7) & ~7;
712 
714 
715  // Create local copies for byval args.
716  SmallVector<SDValue, 8> ByValArgs;
717  for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
718  ISD::ArgFlagsTy Flags = Outs[i].Flags;
719  if (!Flags.isByVal())
720  continue;
721 
722  SDValue Arg = OutVals[i];
723  unsigned Size = Flags.getByValSize();
724  unsigned Align = Flags.getByValAlign();
725 
726  int FI = MFI->CreateStackObject(Size, Align, false);
727  SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
728  SDValue SizeNode = DAG.getConstant(Size, dl, MVT::i32);
729 
730  Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Align,
731  false, // isVolatile,
732  (Size <= 32), // AlwaysInline if size <= 32,
733  false, // isTailCall
735  ByValArgs.push_back(FIPtr);
736  }
737 
738  Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, dl, true),
739  dl);
740 
742  SmallVector<SDValue, 8> MemOpChains;
743 
744  const unsigned StackOffset = 92;
745  bool hasStructRetAttr = false;
746  // Walk the register/memloc assignments, inserting copies/loads.
747  for (unsigned i = 0, realArgIdx = 0, byvalArgIdx = 0, e = ArgLocs.size();
748  i != e;
749  ++i, ++realArgIdx) {
750  CCValAssign &VA = ArgLocs[i];
751  SDValue Arg = OutVals[realArgIdx];
752 
753  ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
754 
755  // Use local copy if it is a byval arg.
756  if (Flags.isByVal())
757  Arg = ByValArgs[byvalArgIdx++];
758 
759  // Promote the value if needed.
760  switch (VA.getLocInfo()) {
761  default: llvm_unreachable("Unknown loc info!");
762  case CCValAssign::Full: break;
763  case CCValAssign::SExt:
764  Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
765  break;
766  case CCValAssign::ZExt:
767  Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
768  break;
769  case CCValAssign::AExt:
770  Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
771  break;
772  case CCValAssign::BCvt:
773  Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
774  break;
775  }
776 
777  if (Flags.isSRet()) {
778  assert(VA.needsCustom());
779  // store SRet argument in %sp+64
780  SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
781  SDValue PtrOff = DAG.getIntPtrConstant(64, dl);
782  PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
783  MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
785  false, false, 0));
786  hasStructRetAttr = true;
787  continue;
788  }
789 
790  if (VA.needsCustom()) {
791  assert(VA.getLocVT() == MVT::f64);
792 
793  if (VA.isMemLoc()) {
794  unsigned Offset = VA.getLocMemOffset() + StackOffset;
795  // if it is double-word aligned, just store.
796  if (Offset % 8 == 0) {
797  SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
798  SDValue PtrOff = DAG.getIntPtrConstant(Offset, dl);
799  PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
800  MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
802  false, false, 0));
803  continue;
804  }
805  }
806 
808  SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
809  Arg, StackPtr, MachinePointerInfo(),
810  false, false, 0);
811  // Sparc is big-endian, so the high part comes first.
812  SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr,
813  MachinePointerInfo(), false, false, false, 0);
814  // Increment the pointer to the other half.
815  StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
816  DAG.getIntPtrConstant(4, dl));
817  // Load the low part.
818  SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr,
819  MachinePointerInfo(), false, false, false, 0);
820 
821  if (VA.isRegLoc()) {
822  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Hi));
823  assert(i+1 != e);
824  CCValAssign &NextVA = ArgLocs[++i];
825  if (NextVA.isRegLoc()) {
826  RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Lo));
827  } else {
828  // Store the low part in stack.
829  unsigned Offset = NextVA.getLocMemOffset() + StackOffset;
830  SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
831  SDValue PtrOff = DAG.getIntPtrConstant(Offset, dl);
832  PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
833  MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff,
835  false, false, 0));
836  }
837  } else {
838  unsigned Offset = VA.getLocMemOffset() + StackOffset;
839  // Store the high part.
840  SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
841  SDValue PtrOff = DAG.getIntPtrConstant(Offset, dl);
842  PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
843  MemOpChains.push_back(DAG.getStore(Chain, dl, Hi, PtrOff,
845  false, false, 0));
846  // Store the low part.
847  PtrOff = DAG.getIntPtrConstant(Offset + 4, dl);
848  PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
849  MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff,
851  false, false, 0));
852  }
853  continue;
854  }
855 
856  // Arguments that can be passed on register must be kept at
857  // RegsToPass vector
858  if (VA.isRegLoc()) {
859  if (VA.getLocVT() != MVT::f32) {
860  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
861  continue;
862  }
863  Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
864  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
865  continue;
866  }
867 
868  assert(VA.isMemLoc());
869 
870  // Create a store off the stack pointer for this argument.
871  SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
872  SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() + StackOffset,
873  dl);
874  PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
875  MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
877  false, false, 0));
878  }
879 
880 
881  // Emit all stores, make sure the occur before any copies into physregs.
882  if (!MemOpChains.empty())
883  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
884 
885  // Build a sequence of copy-to-reg nodes chained together with token
886  // chain and flag operands which copy the outgoing args into registers.
887  // The InFlag in necessary since all emitted instructions must be
888  // stuck together.
889  SDValue InFlag;
890  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
891  unsigned Reg = toCallerWindow(RegsToPass[i].first);
892  Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag);
893  InFlag = Chain.getValue(1);
894  }
895 
896  unsigned SRetArgSize = (hasStructRetAttr)? getSRetArgSize(DAG, Callee):0;
897  bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CS);
898 
899  // If the callee is a GlobalAddress node (quite common, every direct call is)
900  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
901  // Likewise ExternalSymbol -> TargetExternalSymbol.
902  unsigned TF = ((getTargetMachine().getRelocationModel() == Reloc::PIC_)
904  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
905  Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32, 0, TF);
906  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
907  Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32, TF);
908 
909  // Returns a chain & a flag for retval copy to use
910  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
912  Ops.push_back(Chain);
913  Ops.push_back(Callee);
914  if (hasStructRetAttr)
915  Ops.push_back(DAG.getTargetConstant(SRetArgSize, dl, MVT::i32));
916  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
917  Ops.push_back(DAG.getRegister(toCallerWindow(RegsToPass[i].first),
918  RegsToPass[i].second.getValueType()));
919 
920  // Add a register mask operand representing the call-preserved registers.
921  const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
922  const uint32_t *Mask =
923  ((hasReturnsTwice)
924  ? TRI->getRTCallPreservedMask(CallConv)
925  : TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv));
926  assert(Mask && "Missing call preserved mask for calling convention");
927  Ops.push_back(DAG.getRegisterMask(Mask));
928 
929  if (InFlag.getNode())
930  Ops.push_back(InFlag);
931 
932  Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, Ops);
933  InFlag = Chain.getValue(1);
934 
935  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, dl, true),
936  DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
937  InFlag = Chain.getValue(1);
938 
939  // Assign locations to each value returned by this call.
941  CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
942  *DAG.getContext());
943 
944  RVInfo.AnalyzeCallResult(Ins, RetCC_Sparc32);
945 
946  // Copy all of the result registers out of their specified physreg.
947  for (unsigned i = 0; i != RVLocs.size(); ++i) {
948  Chain = DAG.getCopyFromReg(Chain, dl, toCallerWindow(RVLocs[i].getLocReg()),
949  RVLocs[i].getValVT(), InFlag).getValue(1);
950  InFlag = Chain.getValue(2);
951  InVals.push_back(Chain.getValue(0));
952  }
953 
954  return Chain;
955 }
956 
957 // This functions returns true if CalleeName is a ABI function that returns
958 // a long double (fp128).
959 static bool isFP128ABICall(const char *CalleeName)
960 {
961  static const char *const ABICalls[] =
962  { "_Q_add", "_Q_sub", "_Q_mul", "_Q_div",
963  "_Q_sqrt", "_Q_neg",
964  "_Q_itoq", "_Q_stoq", "_Q_dtoq", "_Q_utoq",
965  "_Q_lltoq", "_Q_ulltoq",
966  nullptr
967  };
968  for (const char * const *I = ABICalls; *I != nullptr; ++I)
969  if (strcmp(CalleeName, *I) == 0)
970  return true;
971  return false;
972 }
973 
974 unsigned
976 {
977  const Function *CalleeFn = nullptr;
978  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
979  CalleeFn = dyn_cast<Function>(G->getGlobal());
980  } else if (ExternalSymbolSDNode *E =
981  dyn_cast<ExternalSymbolSDNode>(Callee)) {
982  const Function *Fn = DAG.getMachineFunction().getFunction();
983  const Module *M = Fn->getParent();
984  const char *CalleeName = E->getSymbol();
985  CalleeFn = M->getFunction(CalleeName);
986  if (!CalleeFn && isFP128ABICall(CalleeName))
987  return 16; // Return sizeof(fp128)
988  }
989 
990  if (!CalleeFn)
991  return 0;
992 
993  assert(CalleeFn->hasStructRetAttr() &&
994  "Callee does not have the StructRet attribute.");
995 
996  PointerType *Ty = cast<PointerType>(CalleeFn->arg_begin()->getType());
997  Type *ElementTy = Ty->getElementType();
998  return DAG.getDataLayout().getTypeAllocSize(ElementTy);
999 }
1000 
1001 
1002 // Fixup floating point arguments in the ... part of a varargs call.
1003 //
1004 // The SPARC v9 ABI requires that floating point arguments are treated the same
1005 // as integers when calling a varargs function. This does not apply to the
1006 // fixed arguments that are part of the function's prototype.
1007 //
1008 // This function post-processes a CCValAssign array created by
1009 // AnalyzeCallOperands().
1011  ArrayRef<ISD::OutputArg> Outs) {
1012  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1013  const CCValAssign &VA = ArgLocs[i];
1014  MVT ValTy = VA.getLocVT();
1015  // FIXME: What about f32 arguments? C promotes them to f64 when calling
1016  // varargs functions.
1017  if (!VA.isRegLoc() || (ValTy != MVT::f64 && ValTy != MVT::f128))
1018  continue;
1019  // The fixed arguments to a varargs function still go in FP registers.
1020  if (Outs[VA.getValNo()].IsFixed)
1021  continue;
1022 
1023  // This floating point argument should be reassigned.
1024  CCValAssign NewVA;
1025 
1026  // Determine the offset into the argument array.
1027  unsigned firstReg = (ValTy == MVT::f64) ? SP::D0 : SP::Q0;
1028  unsigned argSize = (ValTy == MVT::f64) ? 8 : 16;
1029  unsigned Offset = argSize * (VA.getLocReg() - firstReg);
1030  assert(Offset < 16*8 && "Offset out of range, bad register enum?");
1031 
1032  if (Offset < 6*8) {
1033  // This argument should go in %i0-%i5.
1034  unsigned IReg = SP::I0 + Offset/8;
1035  if (ValTy == MVT::f64)
1036  // Full register, just bitconvert into i64.
1037  NewVA = CCValAssign::getReg(VA.getValNo(), VA.getValVT(),
1038  IReg, MVT::i64, CCValAssign::BCvt);
1039  else {
1040  assert(ValTy == MVT::f128 && "Unexpected type!");
1041  // Full register, just bitconvert into i128 -- We will lower this into
1042  // two i64s in LowerCall_64.
1043  NewVA = CCValAssign::getCustomReg(VA.getValNo(), VA.getValVT(),
1044  IReg, MVT::i128, CCValAssign::BCvt);
1045  }
1046  } else {
1047  // This needs to go to memory, we're out of integer registers.
1048  NewVA = CCValAssign::getMem(VA.getValNo(), VA.getValVT(),
1049  Offset, VA.getLocVT(), VA.getLocInfo());
1050  }
1051  ArgLocs[i] = NewVA;
1052  }
1053 }
1054 
1055 // Lower a call for the 64-bit ABI.
1056 SDValue
1058  SmallVectorImpl<SDValue> &InVals) const {
1059  SelectionDAG &DAG = CLI.DAG;
1060  SDLoc DL = CLI.DL;
1061  SDValue Chain = CLI.Chain;
1062  auto PtrVT = getPointerTy(DAG.getDataLayout());
1063 
1064  // Sparc target does not yet support tail call optimization.
1065  CLI.IsTailCall = false;
1066 
1067  // Analyze operands of the call, assigning locations to each operand.
1069  CCState CCInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), ArgLocs,
1070  *DAG.getContext());
1071  CCInfo.AnalyzeCallOperands(CLI.Outs, CC_Sparc64);
1072 
1073  // Get the size of the outgoing arguments stack space requirement.
1074  // The stack offset computed by CC_Sparc64 includes all arguments.
1075  // Called functions expect 6 argument words to exist in the stack frame, used
1076  // or not.
1077  unsigned ArgsSize = std::max(6*8u, CCInfo.getNextStackOffset());
1078 
1079  // Keep stack frames 16-byte aligned.
1080  ArgsSize = RoundUpToAlignment(ArgsSize, 16);
1081 
1082  // Varargs calls require special treatment.
1083  if (CLI.IsVarArg)
1084  fixupVariableFloatArgs(ArgLocs, CLI.Outs);
1085 
1086  // Adjust the stack pointer to make room for the arguments.
1087  // FIXME: Use hasReservedCallFrame to avoid %sp adjustments around all calls
1088  // with more than 6 arguments.
1089  Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, DL, true),
1090  DL);
1091 
1092  // Collect the set of registers to pass to the function and their values.
1093  // This will be emitted as a sequence of CopyToReg nodes glued to the call
1094  // instruction.
1096 
1097  // Collect chains from all the memory opeations that copy arguments to the
1098  // stack. They must follow the stack pointer adjustment above and precede the
1099  // call instruction itself.
1100  SmallVector<SDValue, 8> MemOpChains;
1101 
1102  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1103  const CCValAssign &VA = ArgLocs[i];
1104  SDValue Arg = CLI.OutVals[i];
1105 
1106  // Promote the value if needed.
1107  switch (VA.getLocInfo()) {
1108  default:
1109  llvm_unreachable("Unknown location info!");
1110  case CCValAssign::Full:
1111  break;
1112  case CCValAssign::SExt:
1113  Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
1114  break;
1115  case CCValAssign::ZExt:
1116  Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
1117  break;
1118  case CCValAssign::AExt:
1119  Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
1120  break;
1121  case CCValAssign::BCvt:
1122  // fixupVariableFloatArgs() may create bitcasts from f128 to i128. But
1123  // SPARC does not support i128 natively. Lower it into two i64, see below.
1124  if (!VA.needsCustom() || VA.getValVT() != MVT::f128
1125  || VA.getLocVT() != MVT::i128)
1126  Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
1127  break;
1128  }
1129 
1130  if (VA.isRegLoc()) {
1131  if (VA.needsCustom() && VA.getValVT() == MVT::f128
1132  && VA.getLocVT() == MVT::i128) {
1133  // Store and reload into the interger register reg and reg+1.
1134  unsigned Offset = 8 * (VA.getLocReg() - SP::I0);
1135  unsigned StackOffset = Offset + Subtarget->getStackPointerBias() + 128;
1136  SDValue StackPtr = DAG.getRegister(SP::O6, PtrVT);
1137  SDValue HiPtrOff = DAG.getIntPtrConstant(StackOffset, DL);
1138  HiPtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, HiPtrOff);
1139  SDValue LoPtrOff = DAG.getIntPtrConstant(StackOffset + 8, DL);
1140  LoPtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, LoPtrOff);
1141 
1142  // Store to %sp+BIAS+128+Offset
1143  SDValue Store = DAG.getStore(Chain, DL, Arg, HiPtrOff,
1145  false, false, 0);
1146  // Load into Reg and Reg+1
1147  SDValue Hi64 = DAG.getLoad(MVT::i64, DL, Store, HiPtrOff,
1149  false, false, false, 0);
1150  SDValue Lo64 = DAG.getLoad(MVT::i64, DL, Store, LoPtrOff,
1152  false, false, false, 0);
1153  RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()),
1154  Hi64));
1155  RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()+1),
1156  Lo64));
1157  continue;
1158  }
1159 
1160  // The custom bit on an i32 return value indicates that it should be
1161  // passed in the high bits of the register.
1162  if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
1163  Arg = DAG.getNode(ISD::SHL, DL, MVT::i64, Arg,
1164  DAG.getConstant(32, DL, MVT::i32));
1165 
1166  // The next value may go in the low bits of the same register.
1167  // Handle both at once.
1168  if (i+1 < ArgLocs.size() && ArgLocs[i+1].isRegLoc() &&
1169  ArgLocs[i+1].getLocReg() == VA.getLocReg()) {
1171  CLI.OutVals[i+1]);
1172  Arg = DAG.getNode(ISD::OR, DL, MVT::i64, Arg, NV);
1173  // Skip the next value, it's already done.
1174  ++i;
1175  }
1176  }
1177  RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()), Arg));
1178  continue;
1179  }
1180 
1181  assert(VA.isMemLoc());
1182 
1183  // Create a store off the stack pointer for this argument.
1184  SDValue StackPtr = DAG.getRegister(SP::O6, PtrVT);
1185  // The argument area starts at %fp+BIAS+128 in the callee frame,
1186  // %sp+BIAS+128 in ours.
1187  SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() +
1188  Subtarget->getStackPointerBias() +
1189  128, DL);
1190  PtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, PtrOff);
1191  MemOpChains.push_back(DAG.getStore(Chain, DL, Arg, PtrOff,
1193  false, false, 0));
1194  }
1195 
1196  // Emit all stores, make sure they occur before the call.
1197  if (!MemOpChains.empty())
1198  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
1199 
1200  // Build a sequence of CopyToReg nodes glued together with token chain and
1201  // glue operands which copy the outgoing args into registers. The InGlue is
1202  // necessary since all emitted instructions must be stuck together in order
1203  // to pass the live physical registers.
1204  SDValue InGlue;
1205  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1206  Chain = DAG.getCopyToReg(Chain, DL,
1207  RegsToPass[i].first, RegsToPass[i].second, InGlue);
1208  InGlue = Chain.getValue(1);
1209  }
1210 
1211  // If the callee is a GlobalAddress node (quite common, every direct call is)
1212  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1213  // Likewise ExternalSymbol -> TargetExternalSymbol.
1214  SDValue Callee = CLI.Callee;
1215  bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CS);
1216  unsigned TF = ((getTargetMachine().getRelocationModel() == Reloc::PIC_)
1218  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1219  Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, PtrVT, 0, TF);
1220  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
1221  Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT, TF);
1222 
1223  // Build the operands for the call instruction itself.
1225  Ops.push_back(Chain);
1226  Ops.push_back(Callee);
1227  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1228  Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1229  RegsToPass[i].second.getValueType()));
1230 
1231  // Add a register mask operand representing the call-preserved registers.
1232  const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
1233  const uint32_t *Mask =
1234  ((hasReturnsTwice) ? TRI->getRTCallPreservedMask(CLI.CallConv)
1236  CLI.CallConv));
1237  assert(Mask && "Missing call preserved mask for calling convention");
1238  Ops.push_back(DAG.getRegisterMask(Mask));
1239 
1240  // Make sure the CopyToReg nodes are glued to the call instruction which
1241  // consumes the registers.
1242  if (InGlue.getNode())
1243  Ops.push_back(InGlue);
1244 
1245  // Now the call itself.
1246  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1247  Chain = DAG.getNode(SPISD::CALL, DL, NodeTys, Ops);
1248  InGlue = Chain.getValue(1);
1249 
1250  // Revert the stack pointer immediately after the call.
1251  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, DL, true),
1252  DAG.getIntPtrConstant(0, DL, true), InGlue, DL);
1253  InGlue = Chain.getValue(1);
1254 
1255  // Now extract the return values. This is more or less the same as
1256  // LowerFormalArguments_64.
1257 
1258  // Assign locations to each value returned by this call.
1260  CCState RVInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), RVLocs,
1261  *DAG.getContext());
1262 
1263  // Set inreg flag manually for codegen generated library calls that
1264  // return float.
1265  if (CLI.Ins.size() == 1 && CLI.Ins[0].VT == MVT::f32 && CLI.CS == nullptr)
1266  CLI.Ins[0].Flags.setInReg();
1267 
1268  RVInfo.AnalyzeCallResult(CLI.Ins, RetCC_Sparc64);
1269 
1270  // Copy all of the result registers out of their specified physreg.
1271  for (unsigned i = 0; i != RVLocs.size(); ++i) {
1272  CCValAssign &VA = RVLocs[i];
1273  unsigned Reg = toCallerWindow(VA.getLocReg());
1274 
1275  // When returning 'inreg {i32, i32 }', two consecutive i32 arguments can
1276  // reside in the same register in the high and low bits. Reuse the
1277  // CopyFromReg previous node to avoid duplicate copies.
1278  SDValue RV;
1279  if (RegisterSDNode *SrcReg = dyn_cast<RegisterSDNode>(Chain.getOperand(1)))
1280  if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg)
1281  RV = Chain.getValue(0);
1282 
1283  // But usually we'll create a new CopyFromReg for a different register.
1284  if (!RV.getNode()) {
1285  RV = DAG.getCopyFromReg(Chain, DL, Reg, RVLocs[i].getLocVT(), InGlue);
1286  Chain = RV.getValue(1);
1287  InGlue = Chain.getValue(2);
1288  }
1289 
1290  // Get the high bits for i32 struct elements.
1291  if (VA.getValVT() == MVT::i32 && VA.needsCustom())
1292  RV = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), RV,
1293  DAG.getConstant(32, DL, MVT::i32));
1294 
1295  // The callee promoted the return value, so insert an Assert?ext SDNode so
1296  // we won't promote the value again in this function.
1297  switch (VA.getLocInfo()) {
1298  case CCValAssign::SExt:
1299  RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV,
1300  DAG.getValueType(VA.getValVT()));
1301  break;
1302  case CCValAssign::ZExt:
1303  RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV,
1304  DAG.getValueType(VA.getValVT()));
1305  break;
1306  default:
1307  break;
1308  }
1309 
1310  // Truncate the register down to the return value type.
1311  if (VA.isExtInLoc())
1312  RV = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), RV);
1313 
1314  InVals.push_back(RV);
1315  }
1316 
1317  return Chain;
1318 }
1319 
1320 //===----------------------------------------------------------------------===//
1321 // TargetLowering Implementation
1322 //===----------------------------------------------------------------------===//
1323 
1324 /// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
1325 /// condition.
1327  switch (CC) {
1328  default: llvm_unreachable("Unknown integer condition code!");
1329  case ISD::SETEQ: return SPCC::ICC_E;
1330  case ISD::SETNE: return SPCC::ICC_NE;
1331  case ISD::SETLT: return SPCC::ICC_L;
1332  case ISD::SETGT: return SPCC::ICC_G;
1333  case ISD::SETLE: return SPCC::ICC_LE;
1334  case ISD::SETGE: return SPCC::ICC_GE;
1335  case ISD::SETULT: return SPCC::ICC_CS;
1336  case ISD::SETULE: return SPCC::ICC_LEU;
1337  case ISD::SETUGT: return SPCC::ICC_GU;
1338  case ISD::SETUGE: return SPCC::ICC_CC;
1339  }
1340 }
1341 
1342 /// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
1343 /// FCC condition.
1345  switch (CC) {
1346  default: llvm_unreachable("Unknown fp condition code!");
1347  case ISD::SETEQ:
1348  case ISD::SETOEQ: return SPCC::FCC_E;
1349  case ISD::SETNE:
1350  case ISD::SETUNE: return SPCC::FCC_NE;
1351  case ISD::SETLT:
1352  case ISD::SETOLT: return SPCC::FCC_L;
1353  case ISD::SETGT:
1354  case ISD::SETOGT: return SPCC::FCC_G;
1355  case ISD::SETLE:
1356  case ISD::SETOLE: return SPCC::FCC_LE;
1357  case ISD::SETGE:
1358  case ISD::SETOGE: return SPCC::FCC_GE;
1359  case ISD::SETULT: return SPCC::FCC_UL;
1360  case ISD::SETULE: return SPCC::FCC_ULE;
1361  case ISD::SETUGT: return SPCC::FCC_UG;
1362  case ISD::SETUGE: return SPCC::FCC_UGE;
1363  case ISD::SETUO: return SPCC::FCC_U;
1364  case ISD::SETO: return SPCC::FCC_O;
1365  case ISD::SETONE: return SPCC::FCC_LG;
1366  case ISD::SETUEQ: return SPCC::FCC_UE;
1367  }
1368 }
1369 
1371  const SparcSubtarget &STI)
1372  : TargetLowering(TM), Subtarget(&STI) {
1373  auto &DL = *TM.getDataLayout();
1374 
1375  // Set up the register classes.
1376  addRegisterClass(MVT::i32, &SP::IntRegsRegClass);
1377  addRegisterClass(MVT::f32, &SP::FPRegsRegClass);
1378  addRegisterClass(MVT::f64, &SP::DFPRegsRegClass);
1379  addRegisterClass(MVT::f128, &SP::QFPRegsRegClass);
1380  if (Subtarget->is64Bit())
1381  addRegisterClass(MVT::i64, &SP::I64RegsRegClass);
1382 
1383  // Turn FP extload into load/fextend
1384  for (MVT VT : MVT::fp_valuetypes()) {
1387  }
1388 
1389  // Sparc doesn't have i1 sign extending load
1390  for (MVT VT : MVT::integer_valuetypes())
1392 
1393  // Turn FP truncstore into trunc + store.
1397 
1398  // Custom legalize GlobalAddress nodes into LO/HI parts.
1403 
1404  // Sparc doesn't have sext_inreg, replace them with shl/sra
1408 
1409  // Sparc has no REM or DIVREM operations.
1414 
1415  // ... nor does SparcV9.
1416  if (Subtarget->is64Bit()) {
1421  }
1422 
1423  // Custom expand fp<->sint
1428 
1429  // Custom Expand fp<->uint
1434 
1437 
1438  // Sparc has no select or setcc: expand to SELECT_CC.
1443 
1448 
1449  // Sparc doesn't have BRCOND either, it has BR_CC.
1457 
1462 
1463  if (Subtarget->is64Bit()) {
1474 
1476  Subtarget->usePopc() ? Legal : Expand);
1485  }
1486 
1487  // ATOMICs.
1488  // FIXME: We insert fences for each atomics and generate sub-optimal code
1489  // for PSO/TSO. Also, implement other atomicrmw operations.
1490 
1492 
1495  (Subtarget->isV9() ? Legal: Expand));
1496 
1497 
1499 
1500  // Custom Lower Atomic LOAD/STORE
1503 
1504  if (Subtarget->is64Bit()) {
1509  }
1510 
1511  if (!Subtarget->isV9()) {
1512  // SparcV8 does not have FNEGD and FABSD.
1515  }
1516 
1545 
1549 
1550  // FIXME: Sparc provides these multiplies, but we don't have them yet.
1553 
1554  if (Subtarget->is64Bit()) {
1559 
1562 
1566  }
1567 
1568  // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1570  // VAARG needs to be lowered to not do unaligned accesses for doubles.
1572 
1574 
1575  // Use the default implementation.
1581 
1584 
1586 
1588  Subtarget->usePopc() ? Legal : Expand);
1589 
1590  if (Subtarget->isV9() && Subtarget->hasHardQuad()) {
1593  } else {
1596  }
1597 
1598  if (Subtarget->hasHardQuad()) {
1606  if (Subtarget->isV9()) {
1609  } else {
1612  }
1613 
1614  if (!Subtarget->is64Bit()) {
1619  }
1620 
1621  } else {
1622  // Custom legalize f128 operations.
1623 
1631 
1635 
1636  // Setup Runtime library names.
1637  if (Subtarget->is64Bit()) {
1638  setLibcallName(RTLIB::ADD_F128, "_Qp_add");
1639  setLibcallName(RTLIB::SUB_F128, "_Qp_sub");
1640  setLibcallName(RTLIB::MUL_F128, "_Qp_mul");
1641  setLibcallName(RTLIB::DIV_F128, "_Qp_div");
1642  setLibcallName(RTLIB::SQRT_F128, "_Qp_sqrt");
1655  } else {
1656  setLibcallName(RTLIB::ADD_F128, "_Q_add");
1657  setLibcallName(RTLIB::SUB_F128, "_Q_sub");
1658  setLibcallName(RTLIB::MUL_F128, "_Q_mul");
1659  setLibcallName(RTLIB::DIV_F128, "_Q_div");
1660  setLibcallName(RTLIB::SQRT_F128, "_Q_sqrt");
1673  }
1674  }
1675 
1677 
1679 }
1680 
1681 const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
1682  switch ((SPISD::NodeType)Opcode) {
1683  case SPISD::FIRST_NUMBER: break;
1684  case SPISD::CMPICC: return "SPISD::CMPICC";
1685  case SPISD::CMPFCC: return "SPISD::CMPFCC";
1686  case SPISD::BRICC: return "SPISD::BRICC";
1687  case SPISD::BRXCC: return "SPISD::BRXCC";
1688  case SPISD::BRFCC: return "SPISD::BRFCC";
1689  case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
1690  case SPISD::SELECT_XCC: return "SPISD::SELECT_XCC";
1691  case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
1692  case SPISD::Hi: return "SPISD::Hi";
1693  case SPISD::Lo: return "SPISD::Lo";
1694  case SPISD::FTOI: return "SPISD::FTOI";
1695  case SPISD::ITOF: return "SPISD::ITOF";
1696  case SPISD::FTOX: return "SPISD::FTOX";
1697  case SPISD::XTOF: return "SPISD::XTOF";
1698  case SPISD::CALL: return "SPISD::CALL";
1699  case SPISD::RET_FLAG: return "SPISD::RET_FLAG";
1700  case SPISD::GLOBAL_BASE_REG: return "SPISD::GLOBAL_BASE_REG";
1701  case SPISD::FLUSHW: return "SPISD::FLUSHW";
1702  case SPISD::TLS_ADD: return "SPISD::TLS_ADD";
1703  case SPISD::TLS_LD: return "SPISD::TLS_LD";
1704  case SPISD::TLS_CALL: return "SPISD::TLS_CALL";
1705  }
1706  return nullptr;
1707 }
1708 
1710  EVT VT) const {
1711  if (!VT.isVector())
1712  return MVT::i32;
1714 }
1715 
1716 /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
1717 /// be zero. Op is expected to be a target specific node. Used by DAG
1718 /// combiner.
1720  (const SDValue Op,
1721  APInt &KnownZero,
1722  APInt &KnownOne,
1723  const SelectionDAG &DAG,
1724  unsigned Depth) const {
1725  APInt KnownZero2, KnownOne2;
1726  KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
1727 
1728  switch (Op.getOpcode()) {
1729  default: break;
1730  case SPISD::SELECT_ICC:
1731  case SPISD::SELECT_XCC:
1732  case SPISD::SELECT_FCC:
1733  DAG.computeKnownBits(Op.getOperand(1), KnownZero, KnownOne, Depth+1);
1734  DAG.computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1);
1735 
1736  // Only known if known in both the LHS and RHS.
1737  KnownOne &= KnownOne2;
1738  KnownZero &= KnownZero2;
1739  break;
1740  }
1741 }
1742 
1743 // Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
1744 // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
1745 static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
1746  ISD::CondCode CC, unsigned &SPCC) {
1747  if (isa<ConstantSDNode>(RHS) &&
1748  cast<ConstantSDNode>(RHS)->isNullValue() &&
1749  CC == ISD::SETNE &&
1750  (((LHS.getOpcode() == SPISD::SELECT_ICC ||
1751  LHS.getOpcode() == SPISD::SELECT_XCC) &&
1752  LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
1753  (LHS.getOpcode() == SPISD::SELECT_FCC &&
1754  LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
1755  isa<ConstantSDNode>(LHS.getOperand(0)) &&
1756  isa<ConstantSDNode>(LHS.getOperand(1)) &&
1757  cast<ConstantSDNode>(LHS.getOperand(0))->isOne() &&
1758  cast<ConstantSDNode>(LHS.getOperand(1))->isNullValue()) {
1759  SDValue CMPCC = LHS.getOperand(3);
1760  SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue();
1761  LHS = CMPCC.getOperand(0);
1762  RHS = CMPCC.getOperand(1);
1763  }
1764 }
1765 
1766 // Convert to a target node and set target flags.
1768  SelectionDAG &DAG) const {
1769  if (const GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op))
1770  return DAG.getTargetGlobalAddress(GA->getGlobal(),
1771  SDLoc(GA),
1772  GA->getValueType(0),
1773  GA->getOffset(), TF);
1774 
1775  if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op))
1776  return DAG.getTargetConstantPool(CP->getConstVal(),
1777  CP->getValueType(0),
1778  CP->getAlignment(),
1779  CP->getOffset(), TF);
1780 
1781  if (const BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op))
1782  return DAG.getTargetBlockAddress(BA->getBlockAddress(),
1783  Op.getValueType(),
1784  0,
1785  TF);
1786 
1787  if (const ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op))
1788  return DAG.getTargetExternalSymbol(ES->getSymbol(),
1789  ES->getValueType(0), TF);
1790 
1791  llvm_unreachable("Unhandled address SDNode");
1792 }
1793 
1794 // Split Op into high and low parts according to HiTF and LoTF.
1795 // Return an ADD node combining the parts.
1797  unsigned HiTF, unsigned LoTF,
1798  SelectionDAG &DAG) const {
1799  SDLoc DL(Op);
1800  EVT VT = Op.getValueType();
1801  SDValue Hi = DAG.getNode(SPISD::Hi, DL, VT, withTargetFlags(Op, HiTF, DAG));
1802  SDValue Lo = DAG.getNode(SPISD::Lo, DL, VT, withTargetFlags(Op, LoTF, DAG));
1803  return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo);
1804 }
1805 
1806 // Build SDNodes for producing an address from a GlobalAddress, ConstantPool,
1807 // or ExternalSymbol SDNode.
1809  SDLoc DL(Op);
1810  EVT VT = getPointerTy(DAG.getDataLayout());
1811 
1812  // Handle PIC mode first.
1814  // This is the pic32 code model, the GOT is known to be smaller than 4GB.
1817  SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, VT);
1818  SDValue AbsAddr = DAG.getNode(ISD::ADD, DL, VT, GlobalBase, HiLo);
1819  // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this
1820  // function has calls.
1822  MFI->setHasCalls(true);
1823  return DAG.getLoad(VT, DL, DAG.getEntryNode(), AbsAddr,
1824  MachinePointerInfo::getGOT(), false, false, false, 0);
1825  }
1826 
1827  // This is one of the absolute code models.
1828  switch(getTargetMachine().getCodeModel()) {
1829  default:
1830  llvm_unreachable("Unsupported absolute code model");
1831  case CodeModel::Small:
1832  // abs32.
1835  case CodeModel::Medium: {
1836  // abs44.
1839  H44 = DAG.getNode(ISD::SHL, DL, VT, H44, DAG.getConstant(12, DL, MVT::i32));
1841  L44 = DAG.getNode(SPISD::Lo, DL, VT, L44);
1842  return DAG.getNode(ISD::ADD, DL, VT, H44, L44);
1843  }
1844  case CodeModel::Large: {
1845  // abs64.
1848  Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(32, DL, MVT::i32));
1851  return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo);
1852  }
1853  }
1854 }
1855 
1857  SelectionDAG &DAG) const {
1858  return makeAddress(Op, DAG);
1859 }
1860 
1862  SelectionDAG &DAG) const {
1863  return makeAddress(Op, DAG);
1864 }
1865 
1867  SelectionDAG &DAG) const {
1868  return makeAddress(Op, DAG);
1869 }
1870 
1872  SelectionDAG &DAG) const {
1873 
1874  GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1875  SDLoc DL(GA);
1876  const GlobalValue *GV = GA->getGlobal();
1877  EVT PtrVT = getPointerTy(DAG.getDataLayout());
1878 
1880 
1881  if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
1882  unsigned HiTF = ((model == TLSModel::GeneralDynamic)
1885  unsigned LoTF = ((model == TLSModel::GeneralDynamic)
1888  unsigned addTF = ((model == TLSModel::GeneralDynamic)
1891  unsigned callTF = ((model == TLSModel::GeneralDynamic)
1894 
1895  SDValue HiLo = makeHiLoPair(Op, HiTF, LoTF, DAG);
1896  SDValue Base = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, PtrVT);
1897  SDValue Argument = DAG.getNode(SPISD::TLS_ADD, DL, PtrVT, Base, HiLo,
1898  withTargetFlags(Op, addTF, DAG));
1899 
1900  SDValue Chain = DAG.getEntryNode();
1901  SDValue InFlag;
1902 
1903  Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(1, DL, true), DL);
1904  Chain = DAG.getCopyToReg(Chain, DL, SP::O0, Argument, InFlag);
1905  InFlag = Chain.getValue(1);
1906  SDValue Callee = DAG.getTargetExternalSymbol("__tls_get_addr", PtrVT);
1907  SDValue Symbol = withTargetFlags(Op, callTF, DAG);
1908 
1909  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1911  Ops.push_back(Chain);
1912  Ops.push_back(Callee);
1913  Ops.push_back(Symbol);
1914  Ops.push_back(DAG.getRegister(SP::O0, PtrVT));
1915  const uint32_t *Mask = Subtarget->getRegisterInfo()->getCallPreservedMask(
1917  assert(Mask && "Missing call preserved mask for calling convention");
1918  Ops.push_back(DAG.getRegisterMask(Mask));
1919  Ops.push_back(InFlag);
1920  Chain = DAG.getNode(SPISD::TLS_CALL, DL, NodeTys, Ops);
1921  InFlag = Chain.getValue(1);
1922  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(1, DL, true),
1923  DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
1924  InFlag = Chain.getValue(1);
1925  SDValue Ret = DAG.getCopyFromReg(Chain, DL, SP::O0, PtrVT, InFlag);
1926 
1927  if (model != TLSModel::LocalDynamic)
1928  return Ret;
1929 
1930  SDValue Hi = DAG.getNode(SPISD::Hi, DL, PtrVT,
1932  SDValue Lo = DAG.getNode(SPISD::Lo, DL, PtrVT,
1934  HiLo = DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo);
1935  return DAG.getNode(SPISD::TLS_ADD, DL, PtrVT, Ret, HiLo,
1937  }
1938 
1939  if (model == TLSModel::InitialExec) {
1940  unsigned ldTF = ((PtrVT == MVT::i64)? SparcMCExpr::VK_Sparc_TLS_IE_LDX
1942 
1943  SDValue Base = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, PtrVT);
1944 
1945  // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this
1946  // function has calls.
1948  MFI->setHasCalls(true);
1949 
1950  SDValue TGA = makeHiLoPair(Op,
1953  SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Base, TGA);
1954  SDValue Offset = DAG.getNode(SPISD::TLS_LD,
1955  DL, PtrVT, Ptr,
1956  withTargetFlags(Op, ldTF, DAG));
1957  return DAG.getNode(SPISD::TLS_ADD, DL, PtrVT,
1958  DAG.getRegister(SP::G7, PtrVT), Offset,
1959  withTargetFlags(Op,
1961  }
1962 
1963  assert(model == TLSModel::LocalExec);
1964  SDValue Hi = DAG.getNode(SPISD::Hi, DL, PtrVT,
1966  SDValue Lo = DAG.getNode(SPISD::Lo, DL, PtrVT,
1968  SDValue Offset = DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo);
1969 
1970  return DAG.getNode(ISD::ADD, DL, PtrVT,
1971  DAG.getRegister(SP::G7, PtrVT), Offset);
1972 }
1973 
1974 SDValue
1976  SDValue Arg, SDLoc DL,
1977  SelectionDAG &DAG) const {
1979  EVT ArgVT = Arg.getValueType();
1980  Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1981 
1982  ArgListEntry Entry;
1983  Entry.Node = Arg;
1984  Entry.Ty = ArgTy;
1985 
1986  if (ArgTy->isFP128Ty()) {
1987  // Create a stack object and pass the pointer to the library function.
1988  int FI = MFI->CreateStackObject(16, 8, false);
1989  SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
1990  Chain = DAG.getStore(Chain,
1991  DL,
1992  Entry.Node,
1993  FIPtr,
1995  false,
1996  false,
1997  8);
1998 
1999  Entry.Node = FIPtr;
2000  Entry.Ty = PointerType::getUnqual(ArgTy);
2001  }
2002  Args.push_back(Entry);
2003  return Chain;
2004 }
2005 
2006 SDValue
2008  const char *LibFuncName,
2009  unsigned numArgs) const {
2010 
2011  ArgListTy Args;
2012 
2014  auto PtrVT = getPointerTy(DAG.getDataLayout());
2015 
2016  SDValue Callee = DAG.getExternalSymbol(LibFuncName, PtrVT);
2017  Type *RetTy = Op.getValueType().getTypeForEVT(*DAG.getContext());
2018  Type *RetTyABI = RetTy;
2019  SDValue Chain = DAG.getEntryNode();
2020  SDValue RetPtr;
2021 
2022  if (RetTy->isFP128Ty()) {
2023  // Create a Stack Object to receive the return value of type f128.
2024  ArgListEntry Entry;
2025  int RetFI = MFI->CreateStackObject(16, 8, false);
2026  RetPtr = DAG.getFrameIndex(RetFI, PtrVT);
2027  Entry.Node = RetPtr;
2028  Entry.Ty = PointerType::getUnqual(RetTy);
2029  if (!Subtarget->is64Bit())
2030  Entry.isSRet = true;
2031  Entry.isReturned = false;
2032  Args.push_back(Entry);
2033  RetTyABI = Type::getVoidTy(*DAG.getContext());
2034  }
2035 
2036  assert(Op->getNumOperands() >= numArgs && "Not enough operands!");
2037  for (unsigned i = 0, e = numArgs; i != e; ++i) {
2038  Chain = LowerF128_LibCallArg(Chain, Args, Op.getOperand(i), SDLoc(Op), DAG);
2039  }
2041  CLI.setDebugLoc(SDLoc(Op)).setChain(Chain)
2042  .setCallee(CallingConv::C, RetTyABI, Callee, std::move(Args), 0);
2043 
2044  std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
2045 
2046  // chain is in second result.
2047  if (RetTyABI == RetTy)
2048  return CallInfo.first;
2049 
2050  assert (RetTy->isFP128Ty() && "Unexpected return type!");
2051 
2052  Chain = CallInfo.second;
2053 
2054  // Load RetPtr to get the return value.
2055  return DAG.getLoad(Op.getValueType(),
2056  SDLoc(Op),
2057  Chain,
2058  RetPtr,
2060  false, false, false, 8);
2061 }
2062 
2063 SDValue
2065  unsigned &SPCC,
2066  SDLoc DL,
2067  SelectionDAG &DAG) const {
2068 
2069  const char *LibCall = nullptr;
2070  bool is64Bit = Subtarget->is64Bit();
2071  switch(SPCC) {
2072  default: llvm_unreachable("Unhandled conditional code!");
2073  case SPCC::FCC_E : LibCall = is64Bit? "_Qp_feq" : "_Q_feq"; break;
2074  case SPCC::FCC_NE : LibCall = is64Bit? "_Qp_fne" : "_Q_fne"; break;
2075  case SPCC::FCC_L : LibCall = is64Bit? "_Qp_flt" : "_Q_flt"; break;
2076  case SPCC::FCC_G : LibCall = is64Bit? "_Qp_fgt" : "_Q_fgt"; break;
2077  case SPCC::FCC_LE : LibCall = is64Bit? "_Qp_fle" : "_Q_fle"; break;
2078  case SPCC::FCC_GE : LibCall = is64Bit? "_Qp_fge" : "_Q_fge"; break;
2079  case SPCC::FCC_UL :
2080  case SPCC::FCC_ULE:
2081  case SPCC::FCC_UG :
2082  case SPCC::FCC_UGE:
2083  case SPCC::FCC_U :
2084  case SPCC::FCC_O :
2085  case SPCC::FCC_LG :
2086  case SPCC::FCC_UE : LibCall = is64Bit? "_Qp_cmp" : "_Q_cmp"; break;
2087  }
2088 
2089  auto PtrVT = getPointerTy(DAG.getDataLayout());
2090  SDValue Callee = DAG.getExternalSymbol(LibCall, PtrVT);
2091  Type *RetTy = Type::getInt32Ty(*DAG.getContext());
2092  ArgListTy Args;
2093  SDValue Chain = DAG.getEntryNode();
2094  Chain = LowerF128_LibCallArg(Chain, Args, LHS, DL, DAG);
2095  Chain = LowerF128_LibCallArg(Chain, Args, RHS, DL, DAG);
2096 
2098  CLI.setDebugLoc(DL).setChain(Chain)
2099  .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
2100 
2101  std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
2102 
2103  // result is in first, and chain is in second result.
2104  SDValue Result = CallInfo.first;
2105 
2106  switch(SPCC) {
2107  default: {
2108  SDValue RHS = DAG.getTargetConstant(0, DL, Result.getValueType());
2109  SPCC = SPCC::ICC_NE;
2110  return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2111  }
2112  case SPCC::FCC_UL : {
2113  SDValue Mask = DAG.getTargetConstant(1, DL, Result.getValueType());
2114  Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2115  SDValue RHS = DAG.getTargetConstant(0, DL, Result.getValueType());
2116  SPCC = SPCC::ICC_NE;
2117  return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2118  }
2119  case SPCC::FCC_ULE: {
2120  SDValue RHS = DAG.getTargetConstant(2, DL, Result.getValueType());
2121  SPCC = SPCC::ICC_NE;
2122  return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2123  }
2124  case SPCC::FCC_UG : {
2125  SDValue RHS = DAG.getTargetConstant(1, DL, Result.getValueType());
2126  SPCC = SPCC::ICC_G;
2127  return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2128  }
2129  case SPCC::FCC_UGE: {
2130  SDValue RHS = DAG.getTargetConstant(1, DL, Result.getValueType());
2131  SPCC = SPCC::ICC_NE;
2132  return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2133  }
2134 
2135  case SPCC::FCC_U : {
2136  SDValue RHS = DAG.getTargetConstant(3, DL, Result.getValueType());
2137  SPCC = SPCC::ICC_E;
2138  return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2139  }
2140  case SPCC::FCC_O : {
2141  SDValue RHS = DAG.getTargetConstant(3, DL, Result.getValueType());
2142  SPCC = SPCC::ICC_NE;
2143  return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2144  }
2145  case SPCC::FCC_LG : {
2146  SDValue Mask = DAG.getTargetConstant(3, DL, Result.getValueType());
2147  Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2148  SDValue RHS = DAG.getTargetConstant(0, DL, Result.getValueType());
2149  SPCC = SPCC::ICC_NE;
2150  return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2151  }
2152  case SPCC::FCC_UE : {
2153  SDValue Mask = DAG.getTargetConstant(3, DL, Result.getValueType());
2154  Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2155  SDValue RHS = DAG.getTargetConstant(0, DL, Result.getValueType());
2156  SPCC = SPCC::ICC_E;
2157  return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2158  }
2159  }
2160 }
2161 
2162 static SDValue
2164  const SparcTargetLowering &TLI) {
2165 
2166  if (Op.getOperand(0).getValueType() == MVT::f64)
2167  return TLI.LowerF128Op(Op, DAG,
2169 
2170  if (Op.getOperand(0).getValueType() == MVT::f32)
2171  return TLI.LowerF128Op(Op, DAG,
2173 
2174  llvm_unreachable("fpextend with non-float operand!");
2175  return SDValue();
2176 }
2177 
2178 static SDValue
2180  const SparcTargetLowering &TLI) {
2181  // FP_ROUND on f64 and f32 are legal.
2182  if (Op.getOperand(0).getValueType() != MVT::f128)
2183  return Op;
2184 
2185  if (Op.getValueType() == MVT::f64)
2186  return TLI.LowerF128Op(Op, DAG,
2188  if (Op.getValueType() == MVT::f32)
2189  return TLI.LowerF128Op(Op, DAG,
2191 
2192  llvm_unreachable("fpround to non-float!");
2193  return SDValue();
2194 }
2195 
2197  const SparcTargetLowering &TLI,
2198  bool hasHardQuad) {
2199  SDLoc dl(Op);
2200  EVT VT = Op.getValueType();
2201  assert(VT == MVT::i32 || VT == MVT::i64);
2202 
2203  // Expand f128 operations to fp128 abi calls.
2204  if (Op.getOperand(0).getValueType() == MVT::f128
2205  && (!hasHardQuad || !TLI.isTypeLegal(VT))) {
2206  const char *libName = TLI.getLibcallName(VT == MVT::i32
2209  return TLI.LowerF128Op(Op, DAG, libName, 1);
2210  }
2211 
2212  // Expand if the resulting type is illegal.
2213  if (!TLI.isTypeLegal(VT))
2214  return SDValue();
2215 
2216  // Otherwise, Convert the fp value to integer in an FP register.
2217  if (VT == MVT::i32)
2218  Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0));
2219  else
2220  Op = DAG.getNode(SPISD::FTOX, dl, MVT::f64, Op.getOperand(0));
2221 
2222  return DAG.getNode(ISD::BITCAST, dl, VT, Op);
2223 }
2224 
2226  const SparcTargetLowering &TLI,
2227  bool hasHardQuad) {
2228  SDLoc dl(Op);
2229  EVT OpVT = Op.getOperand(0).getValueType();
2230  assert(OpVT == MVT::i32 || (OpVT == MVT::i64));
2231 
2232  EVT floatVT = (OpVT == MVT::i32) ? MVT::f32 : MVT::f64;
2233 
2234  // Expand f128 operations to fp128 ABI calls.
2235  if (Op.getValueType() == MVT::f128
2236  && (!hasHardQuad || !TLI.isTypeLegal(OpVT))) {
2237  const char *libName = TLI.getLibcallName(OpVT == MVT::i32
2240  return TLI.LowerF128Op(Op, DAG, libName, 1);
2241  }
2242 
2243  // Expand if the operand type is illegal.
2244  if (!TLI.isTypeLegal(OpVT))
2245  return SDValue();
2246 
2247  // Otherwise, Convert the int value to FP in an FP register.
2248  SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, floatVT, Op.getOperand(0));
2249  unsigned opcode = (OpVT == MVT::i32)? SPISD::ITOF : SPISD::XTOF;
2250  return DAG.getNode(opcode, dl, Op.getValueType(), Tmp);
2251 }
2252 
2254  const SparcTargetLowering &TLI,
2255  bool hasHardQuad) {
2256  SDLoc dl(Op);
2257  EVT VT = Op.getValueType();
2258 
2259  // Expand if it does not involve f128 or the target has support for
2260  // quad floating point instructions and the resulting type is legal.
2261  if (Op.getOperand(0).getValueType() != MVT::f128 ||
2262  (hasHardQuad && TLI.isTypeLegal(VT)))
2263  return SDValue();
2264 
2265  assert(VT == MVT::i32 || VT == MVT::i64);
2266 
2267  return TLI.LowerF128Op(Op, DAG,
2268  TLI.getLibcallName(VT == MVT::i32
2271  1);
2272 }
2273 
2275  const SparcTargetLowering &TLI,
2276  bool hasHardQuad) {
2277  SDLoc dl(Op);
2278  EVT OpVT = Op.getOperand(0).getValueType();
2279  assert(OpVT == MVT::i32 || OpVT == MVT::i64);
2280 
2281  // Expand if it does not involve f128 or the target has support for
2282  // quad floating point instructions and the operand type is legal.
2283  if (Op.getValueType() != MVT::f128 || (hasHardQuad && TLI.isTypeLegal(OpVT)))
2284  return SDValue();
2285 
2286  return TLI.LowerF128Op(Op, DAG,
2287  TLI.getLibcallName(OpVT == MVT::i32
2290  1);
2291 }
2292 
2294  const SparcTargetLowering &TLI,
2295  bool hasHardQuad) {
2296  SDValue Chain = Op.getOperand(0);
2297  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2298  SDValue LHS = Op.getOperand(2);
2299  SDValue RHS = Op.getOperand(3);
2300  SDValue Dest = Op.getOperand(4);
2301  SDLoc dl(Op);
2302  unsigned Opc, SPCC = ~0U;
2303 
2304  // If this is a br_cc of a "setcc", and if the setcc got lowered into
2305  // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
2306  LookThroughSetCC(LHS, RHS, CC, SPCC);
2307 
2308  // Get the condition flag.
2309  SDValue CompareFlag;
2310  if (LHS.getValueType().isInteger()) {
2311  CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS);
2312  if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
2313  // 32-bit compares use the icc flags, 64-bit uses the xcc flags.
2314  Opc = LHS.getValueType() == MVT::i32 ? SPISD::BRICC : SPISD::BRXCC;
2315  } else {
2316  if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
2317  if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2318  CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
2319  Opc = SPISD::BRICC;
2320  } else {
2321  CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
2322  if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2323  Opc = SPISD::BRFCC;
2324  }
2325  }
2326  return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest,
2327  DAG.getConstant(SPCC, dl, MVT::i32), CompareFlag);
2328 }
2329 
2331  const SparcTargetLowering &TLI,
2332  bool hasHardQuad) {
2333  SDValue LHS = Op.getOperand(0);
2334  SDValue RHS = Op.getOperand(1);
2335  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2336  SDValue TrueVal = Op.getOperand(2);
2337  SDValue FalseVal = Op.getOperand(3);
2338  SDLoc dl(Op);
2339  unsigned Opc, SPCC = ~0U;
2340 
2341  // If this is a select_cc of a "setcc", and if the setcc got lowered into
2342  // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
2343  LookThroughSetCC(LHS, RHS, CC, SPCC);
2344 
2345  SDValue CompareFlag;
2346  if (LHS.getValueType().isInteger()) {
2347  CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS);
2348  Opc = LHS.getValueType() == MVT::i32 ?
2350  if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
2351  } else {
2352  if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
2353  if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2354  CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
2355  Opc = SPISD::SELECT_ICC;
2356  } else {
2357  CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
2358  Opc = SPISD::SELECT_FCC;
2359  if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2360  }
2361  }
2362  return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal,
2363  DAG.getConstant(SPCC, dl, MVT::i32), CompareFlag);
2364 }
2365 
2367  const SparcTargetLowering &TLI) {
2368  MachineFunction &MF = DAG.getMachineFunction();
2370  auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
2371 
2372  // Need frame address to find the address of VarArgsFrameIndex.
2374 
2375  // vastart just stores the address of the VarArgsFrameIndex slot into the
2376  // memory location argument.
2377  SDLoc DL(Op);
2378  SDValue Offset =
2379  DAG.getNode(ISD::ADD, DL, PtrVT, DAG.getRegister(SP::I6, PtrVT),
2380  DAG.getIntPtrConstant(FuncInfo->getVarArgsFrameOffset(), DL));
2381  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2382  return DAG.getStore(Op.getOperand(0), DL, Offset, Op.getOperand(1),
2383  MachinePointerInfo(SV), false, false, 0);
2384 }
2385 
2387  SDNode *Node = Op.getNode();
2388  EVT VT = Node->getValueType(0);
2389  SDValue InChain = Node->getOperand(0);
2390  SDValue VAListPtr = Node->getOperand(1);
2391  EVT PtrVT = VAListPtr.getValueType();
2392  const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2393  SDLoc DL(Node);
2394  SDValue VAList = DAG.getLoad(PtrVT, DL, InChain, VAListPtr,
2395  MachinePointerInfo(SV), false, false, false, 0);
2396  // Increment the pointer, VAList, to the next vaarg.
2397  SDValue NextPtr = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
2398  DAG.getIntPtrConstant(VT.getSizeInBits()/8,
2399  DL));
2400  // Store the incremented VAList to the legalized pointer.
2401  InChain = DAG.getStore(VAList.getValue(1), DL, NextPtr,
2402  VAListPtr, MachinePointerInfo(SV), false, false, 0);
2403  // Load the actual argument out of the pointer VAList.
2404  // We can't count on greater alignment than the word size.
2405  return DAG.getLoad(VT, DL, InChain, VAList, MachinePointerInfo(),
2406  false, false, false,
2407  std::min(PtrVT.getSizeInBits(), VT.getSizeInBits())/8);
2408 }
2409 
2411  const SparcSubtarget *Subtarget) {
2412  SDValue Chain = Op.getOperand(0); // Legalize the chain.
2413  SDValue Size = Op.getOperand(1); // Legalize the size.
2414  EVT VT = Size->getValueType(0);
2415  SDLoc dl(Op);
2416 
2417  unsigned SPReg = SP::O6;
2418  SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
2419  SDValue NewSP = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
2420  Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain
2421 
2422  // The resultant pointer is actually 16 words from the bottom of the stack,
2423  // to provide a register spill area.
2424  unsigned regSpillArea = Subtarget->is64Bit() ? 128 : 96;
2425  regSpillArea += Subtarget->getStackPointerBias();
2426 
2427  SDValue NewVal = DAG.getNode(ISD::ADD, dl, VT, NewSP,
2428  DAG.getConstant(regSpillArea, dl, VT));
2429  SDValue Ops[2] = { NewVal, Chain };
2430  return DAG.getMergeValues(Ops, dl);
2431 }
2432 
2433 
2435  SDLoc dl(Op);
2436  SDValue Chain = DAG.getNode(SPISD::FLUSHW,
2437  dl, MVT::Other, DAG.getEntryNode());
2438  return Chain;
2439 }
2440 
2441 static SDValue getFRAMEADDR(uint64_t depth, SDValue Op, SelectionDAG &DAG,
2442  const SparcSubtarget *Subtarget) {
2444  MFI->setFrameAddressIsTaken(true);
2445 
2446  EVT VT = Op.getValueType();
2447  SDLoc dl(Op);
2448  unsigned FrameReg = SP::I6;
2449  unsigned stackBias = Subtarget->getStackPointerBias();
2450 
2451  SDValue FrameAddr;
2452 
2453  if (depth == 0) {
2454  FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
2455  if (Subtarget->is64Bit())
2456  FrameAddr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr,
2457  DAG.getIntPtrConstant(stackBias, dl));
2458  return FrameAddr;
2459  }
2460 
2461  // flush first to make sure the windowed registers' values are in stack
2462  SDValue Chain = getFLUSHW(Op, DAG);
2463  FrameAddr = DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
2464 
2465  unsigned Offset = (Subtarget->is64Bit()) ? (stackBias + 112) : 56;
2466 
2467  while (depth--) {
2468  SDValue Ptr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr,
2469  DAG.getIntPtrConstant(Offset, dl));
2470  FrameAddr = DAG.getLoad(VT, dl, Chain, Ptr, MachinePointerInfo(),
2471  false, false, false, 0);
2472  }
2473  if (Subtarget->is64Bit())
2474  FrameAddr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr,
2475  DAG.getIntPtrConstant(stackBias, dl));
2476  return FrameAddr;
2477 }
2478 
2479 
2481  const SparcSubtarget *Subtarget) {
2482 
2483  uint64_t depth = Op.getConstantOperandVal(0);
2484 
2485  return getFRAMEADDR(depth, Op, DAG, Subtarget);
2486 
2487 }
2488 
2490  const SparcTargetLowering &TLI,
2491  const SparcSubtarget *Subtarget) {
2492  MachineFunction &MF = DAG.getMachineFunction();
2493  MachineFrameInfo *MFI = MF.getFrameInfo();
2494  MFI->setReturnAddressIsTaken(true);
2495 
2496  if (TLI.verifyReturnAddressArgumentIsConstant(Op, DAG))
2497  return SDValue();
2498 
2499  EVT VT = Op.getValueType();
2500  SDLoc dl(Op);
2501  uint64_t depth = Op.getConstantOperandVal(0);
2502 
2503  SDValue RetAddr;
2504  if (depth == 0) {
2505  auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
2506  unsigned RetReg = MF.addLiveIn(SP::I7, TLI.getRegClassFor(PtrVT));
2507  RetAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RetReg, VT);
2508  return RetAddr;
2509  }
2510 
2511  // Need frame address to find return address of the caller.
2512  SDValue FrameAddr = getFRAMEADDR(depth - 1, Op, DAG, Subtarget);
2513 
2514  unsigned Offset = (Subtarget->is64Bit()) ? 120 : 60;
2515  SDValue Ptr = DAG.getNode(ISD::ADD,
2516  dl, VT,
2517  FrameAddr,
2518  DAG.getIntPtrConstant(Offset, dl));
2519  RetAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), Ptr,
2520  MachinePointerInfo(), false, false, false, 0);
2521 
2522  return RetAddr;
2523 }
2524 
2525 static SDValue LowerF64Op(SDValue Op, SelectionDAG &DAG, unsigned opcode)
2526 {
2527  SDLoc dl(Op);
2528 
2529  assert(Op.getValueType() == MVT::f64 && "LowerF64Op called on non-double!");
2530  assert(opcode == ISD::FNEG || opcode == ISD::FABS);
2531 
2532  // Lower fneg/fabs on f64 to fneg/fabs on f32.
2533  // fneg f64 => fneg f32:sub_even, fmov f32:sub_odd.
2534  // fabs f64 => fabs f32:sub_even, fmov f32:sub_odd.
2535 
2536  SDValue SrcReg64 = Op.getOperand(0);
2537  SDValue Hi32 = DAG.getTargetExtractSubreg(SP::sub_even, dl, MVT::f32,
2538  SrcReg64);
2539  SDValue Lo32 = DAG.getTargetExtractSubreg(SP::sub_odd, dl, MVT::f32,
2540  SrcReg64);
2541 
2542  Hi32 = DAG.getNode(opcode, dl, MVT::f32, Hi32);
2543 
2545  dl, MVT::f64), 0);
2546  DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64,
2547  DstReg64, Hi32);
2548  DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64,
2549  DstReg64, Lo32);
2550  return DstReg64;
2551 }
2552 
2553 // Lower a f128 load into two f64 loads.
2555 {
2556  SDLoc dl(Op);
2557  LoadSDNode *LdNode = dyn_cast<LoadSDNode>(Op.getNode());
2558  assert(LdNode && LdNode->getOffset().getOpcode() == ISD::UNDEF
2559  && "Unexpected node type");
2560 
2561  unsigned alignment = LdNode->getAlignment();
2562  if (alignment > 8)
2563  alignment = 8;
2564 
2565  SDValue Hi64 = DAG.getLoad(MVT::f64,
2566  dl,
2567  LdNode->getChain(),
2568  LdNode->getBasePtr(),
2569  LdNode->getPointerInfo(),
2570  false, false, false, alignment);
2571  EVT addrVT = LdNode->getBasePtr().getValueType();
2572  SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT,
2573  LdNode->getBasePtr(),
2574  DAG.getConstant(8, dl, addrVT));
2575  SDValue Lo64 = DAG.getLoad(MVT::f64,
2576  dl,
2577  LdNode->getChain(),
2578  LoPtr,
2579  LdNode->getPointerInfo(),
2580  false, false, false, alignment);
2581 
2582  SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, dl, MVT::i32);
2583  SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, dl, MVT::i32);
2584 
2586  dl, MVT::f128);
2587  InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
2588  MVT::f128,
2589  SDValue(InFP128, 0),
2590  Hi64,
2591  SubRegEven);
2592  InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
2593  MVT::f128,
2594  SDValue(InFP128, 0),
2595  Lo64,
2596  SubRegOdd);
2597  SDValue OutChains[2] = { SDValue(Hi64.getNode(), 1),
2598  SDValue(Lo64.getNode(), 1) };
2599  SDValue OutChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
2600  SDValue Ops[2] = {SDValue(InFP128,0), OutChain};
2601  return DAG.getMergeValues(Ops, dl);
2602 }
2603 
2604 // Lower a f128 store into two f64 stores.
2606  SDLoc dl(Op);
2607  StoreSDNode *StNode = dyn_cast<StoreSDNode>(Op.getNode());
2608  assert(StNode && StNode->getOffset().getOpcode() == ISD::UNDEF
2609  && "Unexpected node type");
2610  SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, dl, MVT::i32);
2611  SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, dl, MVT::i32);
2612 
2614  dl,
2615  MVT::f64,
2616  StNode->getValue(),
2617  SubRegEven);
2619  dl,
2620  MVT::f64,
2621  StNode->getValue(),
2622  SubRegOdd);
2623 
2624  unsigned alignment = StNode->getAlignment();
2625  if (alignment > 8)
2626  alignment = 8;
2627 
2628  SDValue OutChains[2];
2629  OutChains[0] = DAG.getStore(StNode->getChain(),
2630  dl,
2631  SDValue(Hi64, 0),
2632  StNode->getBasePtr(),
2634  false, false, alignment);
2635  EVT addrVT = StNode->getBasePtr().getValueType();
2636  SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT,
2637  StNode->getBasePtr(),
2638  DAG.getConstant(8, dl, addrVT));
2639  OutChains[1] = DAG.getStore(StNode->getChain(),
2640  dl,
2641  SDValue(Lo64, 0),
2642  LoPtr,
2644  false, false, alignment);
2645  return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
2646 }
2647 
2648 static SDValue LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9) {
2649  assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS)
2650  && "invalid opcode");
2651 
2652  if (Op.getValueType() == MVT::f64)
2653  return LowerF64Op(Op, DAG, Op.getOpcode());
2654  if (Op.getValueType() != MVT::f128)
2655  return Op;
2656 
2657  // Lower fabs/fneg on f128 to fabs/fneg on f64
2658  // fabs/fneg f128 => fabs/fneg f64:sub_even64, fmov f64:sub_odd64
2659 
2660  SDLoc dl(Op);
2661  SDValue SrcReg128 = Op.getOperand(0);
2662  SDValue Hi64 = DAG.getTargetExtractSubreg(SP::sub_even64, dl, MVT::f64,
2663  SrcReg128);
2664  SDValue Lo64 = DAG.getTargetExtractSubreg(SP::sub_odd64, dl, MVT::f64,
2665  SrcReg128);
2666  if (isV9)
2667  Hi64 = DAG.getNode(Op.getOpcode(), dl, MVT::f64, Hi64);
2668  else
2669  Hi64 = LowerF64Op(Hi64, DAG, Op.getOpcode());
2670 
2672  dl, MVT::f128), 0);
2673  DstReg128 = DAG.getTargetInsertSubreg(SP::sub_even64, dl, MVT::f128,
2674  DstReg128, Hi64);
2675  DstReg128 = DAG.getTargetInsertSubreg(SP::sub_odd64, dl, MVT::f128,
2676  DstReg128, Lo64);
2677  return DstReg128;
2678 }
2679 
2681 
2682  if (Op.getValueType() != MVT::i64)
2683  return Op;
2684 
2685  SDLoc dl(Op);
2686  SDValue Src1 = Op.getOperand(0);
2687  SDValue Src1Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1);
2688  SDValue Src1Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src1,
2689  DAG.getConstant(32, dl, MVT::i64));
2690  Src1Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1Hi);
2691 
2692  SDValue Src2 = Op.getOperand(1);
2693  SDValue Src2Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2);
2694  SDValue Src2Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src2,
2695  DAG.getConstant(32, dl, MVT::i64));
2696  Src2Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2Hi);
2697 
2698 
2699  bool hasChain = false;
2700  unsigned hiOpc = Op.getOpcode();
2701  switch (Op.getOpcode()) {
2702  default: llvm_unreachable("Invalid opcode");
2703  case ISD::ADDC: hiOpc = ISD::ADDE; break;
2704  case ISD::ADDE: hasChain = true; break;
2705  case ISD::SUBC: hiOpc = ISD::SUBE; break;
2706  case ISD::SUBE: hasChain = true; break;
2707  }
2708  SDValue Lo;
2709  SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Glue);
2710  if (hasChain) {
2711  Lo = DAG.getNode(Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo,
2712  Op.getOperand(2));
2713  } else {
2714  Lo = DAG.getNode(Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo);
2715  }
2716  SDValue Hi = DAG.getNode(hiOpc, dl, VTs, Src1Hi, Src2Hi, Lo.getValue(1));
2717  SDValue Carry = Hi.getValue(1);
2718 
2719  Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Lo);
2720  Hi = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Hi);
2721  Hi = DAG.getNode(ISD::SHL, dl, MVT::i64, Hi,
2722  DAG.getConstant(32, dl, MVT::i64));
2723 
2724  SDValue Dst = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, Lo);
2725  SDValue Ops[2] = { Dst, Carry };
2726  return DAG.getMergeValues(Ops, dl);
2727 }
2728 
2729 // Custom lower UMULO/SMULO for SPARC. This code is similar to ExpandNode()
2730 // in LegalizeDAG.cpp except the order of arguments to the library function.
2732  const SparcTargetLowering &TLI)
2733 {
2734  unsigned opcode = Op.getOpcode();
2735  assert((opcode == ISD::UMULO || opcode == ISD::SMULO) && "Invalid Opcode.");
2736 
2737  bool isSigned = (opcode == ISD::SMULO);
2738  EVT VT = MVT::i64;
2739  EVT WideVT = MVT::i128;
2740  SDLoc dl(Op);
2741  SDValue LHS = Op.getOperand(0);
2742 
2743  if (LHS.getValueType() != VT)
2744  return Op;
2745 
2746  SDValue ShiftAmt = DAG.getConstant(63, dl, VT);
2747 
2748  SDValue RHS = Op.getOperand(1);
2749  SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, LHS, ShiftAmt);
2750  SDValue HiRHS = DAG.getNode(ISD::SRA, dl, MVT::i64, RHS, ShiftAmt);
2751  SDValue Args[] = { HiLHS, LHS, HiRHS, RHS };
2752 
2753  SDValue MulResult = TLI.makeLibCall(DAG,
2754  RTLIB::MUL_I128, WideVT,
2755  Args, 4, isSigned, dl).first;
2756  SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT,
2757  MulResult, DAG.getIntPtrConstant(0, dl));
2758  SDValue TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT,
2759  MulResult, DAG.getIntPtrConstant(1, dl));
2760  if (isSigned) {
2761  SDValue Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, ShiftAmt);
2762  TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, Tmp1, ISD::SETNE);
2763  } else {
2764  TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, DAG.getConstant(0, dl, VT),
2765  ISD::SETNE);
2766  }
2767  // MulResult is a node with an illegal type. Because such things are not
2768  // generally permitted during this phase of legalization, ensure that
2769  // nothing is left using the node. The above EXTRACT_ELEMENT nodes should have
2770  // been folded.
2771  assert(MulResult->use_empty() && "Illegally typed node still in use!");
2772 
2773  SDValue Ops[2] = { BottomHalf, TopHalf } ;
2774  return DAG.getMergeValues(Ops, dl);
2775 }
2776 
2778  // Monotonic load/stores are legal.
2779  if (cast<AtomicSDNode>(Op)->getOrdering() <= Monotonic)
2780  return Op;
2781 
2782  // Otherwise, expand with a fence.
2783  return SDValue();
2784 }
2785 
2786 
2789 
2790  bool hasHardQuad = Subtarget->hasHardQuad();
2791  bool isV9 = Subtarget->isV9();
2792 
2793  switch (Op.getOpcode()) {
2794  default: llvm_unreachable("Should not custom lower this!");
2795 
2796  case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG, *this,
2797  Subtarget);
2798  case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG,
2799  Subtarget);
2800  case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
2801  case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
2802  case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
2803  case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2804  case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG, *this,
2805  hasHardQuad);
2806  case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG, *this,
2807  hasHardQuad);
2808  case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG, *this,
2809  hasHardQuad);
2810  case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG, *this,
2811  hasHardQuad);
2812  case ISD::BR_CC: return LowerBR_CC(Op, DAG, *this,
2813  hasHardQuad);
2814  case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, *this,
2815  hasHardQuad);
2816  case ISD::VASTART: return LowerVASTART(Op, DAG, *this);
2817  case ISD::VAARG: return LowerVAARG(Op, DAG);
2818  case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG,
2819  Subtarget);
2820 
2821  case ISD::LOAD: return LowerF128Load(Op, DAG);
2822  case ISD::STORE: return LowerF128Store(Op, DAG);
2823  case ISD::FADD: return LowerF128Op(Op, DAG,
2825  case ISD::FSUB: return LowerF128Op(Op, DAG,
2827  case ISD::FMUL: return LowerF128Op(Op, DAG,
2829  case ISD::FDIV: return LowerF128Op(Op, DAG,
2831  case ISD::FSQRT: return LowerF128Op(Op, DAG,
2833  case ISD::FABS:
2834  case ISD::FNEG: return LowerFNEGorFABS(Op, DAG, isV9);
2835  case ISD::FP_EXTEND: return LowerF128_FPEXTEND(Op, DAG, *this);
2836  case ISD::FP_ROUND: return LowerF128_FPROUND(Op, DAG, *this);
2837  case ISD::ADDC:
2838  case ISD::ADDE:
2839  case ISD::SUBC:
2840  case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
2841  case ISD::UMULO:
2842  case ISD::SMULO: return LowerUMULO_SMULO(Op, DAG, *this);
2843  case ISD::ATOMIC_LOAD:
2844  case ISD::ATOMIC_STORE: return LowerATOMIC_LOAD_STORE(Op, DAG);
2845  }
2846 }
2847 
2850  MachineBasicBlock *BB) const {
2851  switch (MI->getOpcode()) {
2852  default: llvm_unreachable("Unknown SELECT_CC!");
2853  case SP::SELECT_CC_Int_ICC:
2854  case SP::SELECT_CC_FP_ICC:
2855  case SP::SELECT_CC_DFP_ICC:
2856  case SP::SELECT_CC_QFP_ICC:
2857  return expandSelectCC(MI, BB, SP::BCOND);
2858  case SP::SELECT_CC_Int_FCC:
2859  case SP::SELECT_CC_FP_FCC:
2860  case SP::SELECT_CC_DFP_FCC:
2861  case SP::SELECT_CC_QFP_FCC:
2862  return expandSelectCC(MI, BB, SP::FBCOND);
2863 
2864  case SP::ATOMIC_LOAD_ADD_32:
2865  return expandAtomicRMW(MI, BB, SP::ADDrr);
2866  case SP::ATOMIC_LOAD_ADD_64:
2867  return expandAtomicRMW(MI, BB, SP::ADDXrr);
2868  case SP::ATOMIC_LOAD_SUB_32:
2869  return expandAtomicRMW(MI, BB, SP::SUBrr);
2870  case SP::ATOMIC_LOAD_SUB_64:
2871  return expandAtomicRMW(MI, BB, SP::SUBXrr);
2872  case SP::ATOMIC_LOAD_AND_32:
2873  return expandAtomicRMW(MI, BB, SP::ANDrr);
2874  case SP::ATOMIC_LOAD_AND_64:
2875  return expandAtomicRMW(MI, BB, SP::ANDXrr);
2876  case SP::ATOMIC_LOAD_OR_32:
2877  return expandAtomicRMW(MI, BB, SP::ORrr);
2878  case SP::ATOMIC_LOAD_OR_64:
2879  return expandAtomicRMW(MI, BB, SP::ORXrr);
2880  case SP::ATOMIC_LOAD_XOR_32:
2881  return expandAtomicRMW(MI, BB, SP::XORrr);
2882  case SP::ATOMIC_LOAD_XOR_64:
2883  return expandAtomicRMW(MI, BB, SP::XORXrr);
2884  case SP::ATOMIC_LOAD_NAND_32:
2885  return expandAtomicRMW(MI, BB, SP::ANDrr);
2886  case SP::ATOMIC_LOAD_NAND_64:
2887  return expandAtomicRMW(MI, BB, SP::ANDXrr);
2888 
2889  case SP::ATOMIC_SWAP_64:
2890  return expandAtomicRMW(MI, BB, 0);
2891 
2892  case SP::ATOMIC_LOAD_MAX_32:
2893  return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_G);
2894  case SP::ATOMIC_LOAD_MAX_64:
2895  return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_G);
2896  case SP::ATOMIC_LOAD_MIN_32:
2897  return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_LE);
2898  case SP::ATOMIC_LOAD_MIN_64:
2899  return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_LE);
2900  case SP::ATOMIC_LOAD_UMAX_32:
2901  return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_GU);
2902  case SP::ATOMIC_LOAD_UMAX_64:
2903  return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_GU);
2904  case SP::ATOMIC_LOAD_UMIN_32:
2905  return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_LEU);
2906  case SP::ATOMIC_LOAD_UMIN_64:
2907  return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_LEU);
2908  }
2909 }
2910 
2913  MachineBasicBlock *BB,
2914  unsigned BROpcode) const {
2915  const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
2916  DebugLoc dl = MI->getDebugLoc();
2917  unsigned CC = (SPCC::CondCodes)MI->getOperand(3).getImm();
2918 
2919  // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
2920  // control-flow pattern. The incoming instruction knows the destination vreg
2921  // to set, the condition code register to branch on, the true/false values to
2922  // select between, and a branch opcode to use.
2923  const BasicBlock *LLVM_BB = BB->getBasicBlock();
2924  MachineFunction::iterator It = BB;
2925  ++It;
2926 
2927  // thisMBB:
2928  // ...
2929  // TrueVal = ...
2930  // [f]bCC copy1MBB
2931  // fallthrough --> copy0MBB
2932  MachineBasicBlock *thisMBB = BB;
2933  MachineFunction *F = BB->getParent();
2934  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
2935  MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
2936  F->insert(It, copy0MBB);
2937  F->insert(It, sinkMBB);
2938 
2939  // Transfer the remainder of BB and its successor edges to sinkMBB.
2940  sinkMBB->splice(sinkMBB->begin(), BB,
2941  std::next(MachineBasicBlock::iterator(MI)),
2942  BB->end());
2943  sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
2944 
2945  // Add the true and fallthrough blocks as its successors.
2946  BB->addSuccessor(copy0MBB);
2947  BB->addSuccessor(sinkMBB);
2948 
2949  BuildMI(BB, dl, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
2950 
2951  // copy0MBB:
2952  // %FalseValue = ...
2953  // # fallthrough to sinkMBB
2954  BB = copy0MBB;
2955 
2956  // Update machine-CFG edges
2957  BB->addSuccessor(sinkMBB);
2958 
2959  // sinkMBB:
2960  // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
2961  // ...
2962  BB = sinkMBB;
2963  BuildMI(*BB, BB->begin(), dl, TII.get(SP::PHI), MI->getOperand(0).getReg())
2964  .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
2965  .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
2966 
2967  MI->eraseFromParent(); // The pseudo instruction is gone now.
2968  return BB;
2969 }
2970 
2973  MachineBasicBlock *MBB,
2974  unsigned Opcode,
2975  unsigned CondCode) const {
2976  const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
2977  MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
2978  DebugLoc DL = MI->getDebugLoc();
2979 
2980  // MI is an atomic read-modify-write instruction of the form:
2981  //
2982  // rd = atomicrmw<op> addr, rs2
2983  //
2984  // All three operands are registers.
2985  unsigned DestReg = MI->getOperand(0).getReg();
2986  unsigned AddrReg = MI->getOperand(1).getReg();
2987  unsigned Rs2Reg = MI->getOperand(2).getReg();
2988 
2989  // SelectionDAG has already inserted memory barriers before and after MI, so
2990  // we simply have to implement the operatiuon in terms of compare-and-swap.
2991  //
2992  // %val0 = load %addr
2993  // loop:
2994  // %val = phi %val0, %dest
2995  // %upd = op %val, %rs2
2996  // %dest = cas %addr, %val, %upd
2997  // cmp %val, %dest
2998  // bne loop
2999  // done:
3000  //
3001  bool is64Bit = SP::I64RegsRegClass.hasSubClassEq(MRI.getRegClass(DestReg));
3002  const TargetRegisterClass *ValueRC =
3003  is64Bit ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
3004  unsigned Val0Reg = MRI.createVirtualRegister(ValueRC);
3005 
3006  BuildMI(*MBB, MI, DL, TII.get(is64Bit ? SP::LDXri : SP::LDri), Val0Reg)
3007  .addReg(AddrReg).addImm(0);
3008 
3009  // Split the basic block MBB before MI and insert the loop block in the hole.
3010  MachineFunction::iterator MFI = MBB;
3011  const BasicBlock *LLVM_BB = MBB->getBasicBlock();
3012  MachineFunction *MF = MBB->getParent();
3013  MachineBasicBlock *LoopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3014  MachineBasicBlock *DoneMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3015  ++MFI;
3016  MF->insert(MFI, LoopMBB);
3017  MF->insert(MFI, DoneMBB);
3018 
3019  // Move MI and following instructions to DoneMBB.
3020  DoneMBB->splice(DoneMBB->begin(), MBB, MI, MBB->end());
3021  DoneMBB->transferSuccessorsAndUpdatePHIs(MBB);
3022 
3023  // Connect the CFG again.
3024  MBB->addSuccessor(LoopMBB);
3025  LoopMBB->addSuccessor(LoopMBB);
3026  LoopMBB->addSuccessor(DoneMBB);
3027 
3028  // Build the loop block.
3029  unsigned ValReg = MRI.createVirtualRegister(ValueRC);
3030  // Opcode == 0 means try to write Rs2Reg directly (ATOMIC_SWAP).
3031  unsigned UpdReg = (Opcode ? MRI.createVirtualRegister(ValueRC) : Rs2Reg);
3032 
3033  BuildMI(LoopMBB, DL, TII.get(SP::PHI), ValReg)
3034  .addReg(Val0Reg).addMBB(MBB)
3035  .addReg(DestReg).addMBB(LoopMBB);
3036 
3037  if (CondCode) {
3038  // This is one of the min/max operations. We need a CMPrr followed by a
3039  // MOVXCC/MOVICC.
3040  BuildMI(LoopMBB, DL, TII.get(SP::CMPrr)).addReg(ValReg).addReg(Rs2Reg);
3041  BuildMI(LoopMBB, DL, TII.get(Opcode), UpdReg)
3042  .addReg(ValReg).addReg(Rs2Reg).addImm(CondCode);
3043  } else if (Opcode) {
3044  BuildMI(LoopMBB, DL, TII.get(Opcode), UpdReg)
3045  .addReg(ValReg).addReg(Rs2Reg);
3046  }
3047 
3048  if (MI->getOpcode() == SP::ATOMIC_LOAD_NAND_32 ||
3049  MI->getOpcode() == SP::ATOMIC_LOAD_NAND_64) {
3050  unsigned TmpReg = UpdReg;
3051  UpdReg = MRI.createVirtualRegister(ValueRC);
3052  BuildMI(LoopMBB, DL, TII.get(SP::XORri), UpdReg).addReg(TmpReg).addImm(-1);
3053  }
3054 
3055  BuildMI(LoopMBB, DL, TII.get(is64Bit ? SP::CASXrr : SP::CASrr), DestReg)
3056  .addReg(AddrReg).addReg(ValReg).addReg(UpdReg)
3057  .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
3058  BuildMI(LoopMBB, DL, TII.get(SP::CMPrr)).addReg(ValReg).addReg(DestReg);
3059  BuildMI(LoopMBB, DL, TII.get(is64Bit ? SP::BPXCC : SP::BCOND))
3060  .addMBB(LoopMBB).addImm(SPCC::ICC_NE);
3061 
3062  MI->eraseFromParent();
3063  return DoneMBB;
3064 }
3065 
3066 //===----------------------------------------------------------------------===//
3067 // Sparc Inline Assembly Support
3068 //===----------------------------------------------------------------------===//
3069 
3070 /// getConstraintType - Given a constraint letter, return the type of
3071 /// constraint it is for this target.
3074  if (Constraint.size() == 1) {
3075  switch (Constraint[0]) {
3076  default: break;
3077  case 'r': return C_RegisterClass;
3078  case 'I': // SIMM13
3079  return C_Other;
3080  }
3081  }
3082 
3083  return TargetLowering::getConstraintType(Constraint);
3084 }
3085 
3088  const char *constraint) const {
3089  ConstraintWeight weight = CW_Invalid;
3090  Value *CallOperandVal = info.CallOperandVal;
3091  // If we don't have a value, we can't do a match,
3092  // but allow it at the lowest weight.
3093  if (!CallOperandVal)
3094  return CW_Default;
3095 
3096  // Look at the constraint type.
3097  switch (*constraint) {
3098  default:
3099  weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3100  break;
3101  case 'I': // SIMM13
3102  if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
3103  if (isInt<13>(C->getSExtValue()))
3104  weight = CW_Constant;
3105  }
3106  break;
3107  }
3108  return weight;
3109 }
3110 
3111 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3112 /// vector. If it is invalid, don't add anything to Ops.
3115  std::string &Constraint,
3116  std::vector<SDValue> &Ops,
3117  SelectionDAG &DAG) const {
3118  SDValue Result(nullptr, 0);
3119 
3120  // Only support length 1 constraints for now.
3121  if (Constraint.length() > 1)
3122  return;
3123 
3124  char ConstraintLetter = Constraint[0];
3125  switch (ConstraintLetter) {
3126  default: break;
3127  case 'I':
3128  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3129  if (isInt<13>(C->getSExtValue())) {
3130  Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
3131  Op.getValueType());
3132  break;
3133  }
3134  return;
3135  }
3136  }
3137 
3138  if (Result.getNode()) {
3139  Ops.push_back(Result);
3140  return;
3141  }
3142  TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3143 }
3144 
3145 std::pair<unsigned, const TargetRegisterClass *>
3147  StringRef Constraint,
3148  MVT VT) const {
3149  if (Constraint.size() == 1) {
3150  switch (Constraint[0]) {
3151  case 'r':
3152  return std::make_pair(0U, &SP::IntRegsRegClass);
3153  }
3154  } else if (!Constraint.empty() && Constraint.size() <= 5
3155  && Constraint[0] == '{' && *(Constraint.end()-1) == '}') {
3156  // constraint = '{r<d>}'
3157  // Remove the braces from around the name.
3158  StringRef name(Constraint.data()+1, Constraint.size()-2);
3159  // Handle register aliases:
3160  // r0-r7 -> g0-g7
3161  // r8-r15 -> o0-o7
3162  // r16-r23 -> l0-l7
3163  // r24-r31 -> i0-i7
3164  uint64_t intVal = 0;
3165  if (name.substr(0, 1).equals("r")
3166  && !name.substr(1).getAsInteger(10, intVal) && intVal <= 31) {
3167  const char regTypes[] = { 'g', 'o', 'l', 'i' };
3168  char regType = regTypes[intVal/8];
3169  char regIdx = '0' + (intVal % 8);
3170  char tmp[] = { '{', regType, regIdx, '}', 0 };
3171  std::string newConstraint = std::string(tmp);
3172  return TargetLowering::getRegForInlineAsmConstraint(TRI, newConstraint,
3173  VT);
3174  }
3175  }
3176 
3177  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3178 }
3179 
3180 bool
3182  // The Sparc target isn't yet aware of offsets.
3183  return false;
3184 }
3185 
3187  SmallVectorImpl<SDValue>& Results,
3188  SelectionDAG &DAG) const {
3189 
3190  SDLoc dl(N);
3191 
3193 
3194  switch (N->getOpcode()) {
3195  default:
3196  llvm_unreachable("Do not know how to custom type legalize this operation!");
3197 
3198  case ISD::FP_TO_SINT:
3199  case ISD::FP_TO_UINT:
3200  // Custom lower only if it involves f128 or i64.
3201  if (N->getOperand(0).getValueType() != MVT::f128
3202  || N->getValueType(0) != MVT::i64)
3203  return;
3204  libCall = ((N->getOpcode() == ISD::FP_TO_SINT)
3207 
3208  Results.push_back(LowerF128Op(SDValue(N, 0),
3209  DAG,
3210  getLibcallName(libCall),
3211  1));
3212  return;
3213 
3214  case ISD::SINT_TO_FP:
3215  case ISD::UINT_TO_FP:
3216  // Custom lower only if it involves f128 or i64.
3217  if (N->getValueType(0) != MVT::f128
3218  || N->getOperand(0).getValueType() != MVT::i64)
3219  return;
3220 
3221  libCall = ((N->getOpcode() == ISD::SINT_TO_FP)
3224 
3225  Results.push_back(LowerF128Op(SDValue(N, 0),
3226  DAG,
3227  getLibcallName(libCall),
3228  1));
3229  return;
3230  }
3231 }
void setFrameAddressIsTaken(bool T)
static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:477
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:450
bool use_empty() const
Return true if there are no uses of this node.
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:104
CallLoweringInfo & setCallee(CallingConv::ID CC, Type *ResultType, SDValue Target, ArgListTy &&ArgsList, unsigned FixedArgs=-1)
SDValue getValue(unsigned R) const
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
MVT getValVT() const
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant, which is required to be operand #1) half of the integer or float value specified as operand #0.
Definition: ISDOpcodes.h:175
LLVMContext * getContext() const
Definition: SelectionDAG.h:289
LLVM Argument representation.
Definition: Argument.h:35
SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:522
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, SDLoc DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd)...
Definition: SelectionDAG.h:646
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
SparcTargetLowering(TargetMachine &TM, const SparcSubtarget &STI)
static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC)
IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC condition.
size_t size() const
size - Get the string size.
Definition: StringRef.h:113
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:554
LocInfo getLocInfo() const
unsigned getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const
static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI)
SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF, SelectionDAG &DAG) const
static SDValue LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG)
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:114
const TargetMachine & getTargetMachine() const
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
CallLoweringInfo & setDebugLoc(SDLoc dl)
SDValue getMergeValues(ArrayRef< SDValue > Ops, SDLoc dl)
Create a MERGE_VALUES node from the given operands.
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:210
unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain...
Definition: ISDOpcodes.h:585
void computeKnownBits(SDValue Op, APInt &KnownZero, APInt &KnownOne, unsigned Depth=0) const
Determine which bits of Op are known to be either zero or one and return them in the KnownZero/KnownO...
const GlobalValue * getGlobal() const
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
SDValue LowerCall_32(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Type * getTypeForEVT(LLVMContext &Context) const
getTypeForEVT - This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:181
unsigned getSizeInBits() const
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
unsigned getByValSize() const
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
unsigned getNumOperands() const
Return the number of values used by this operation.
static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
A debug info location.
Definition: DebugLoc.h:34
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *fromMBB)
transferSuccessorsAndUpdatePHIs - Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor blocks which refer to fromMBB to refer to this.
const SDValue & getOperand(unsigned Num) const
F(f)
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags=0)
MachineBasicBlock * expandSelectCC(MachineInstr *MI, MachineBasicBlock *BB, unsigned BROpcode) const
Value * CallOperandVal
If this is the result output operand or a clobber, this is null, otherwise it is the incoming operand...
const SparcInstrInfo * getInstrInfo() const override
unsigned getValNo() const
const SDValue & getBasePtr() const
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
Definition: ISDOpcodes.h:658
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:357
bool isRegLoc() const
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag=true)
Reports a serious error, calling any installed error handler.
SDValue getExternalSymbol(const char *Sym, EVT VT)
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
SDValue getMemcpy(SDValue Chain, SDLoc dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
static MachinePointerInfo getFixedStack(int FI, int64_t offset=0)
getFixedStack - Return a MachinePointerInfo record that refers to the the specified FrameIndex...
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:200
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
Definition: ISDOpcodes.h:371
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:115
lazy value info
SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
SDValue LowerCall_64(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const
static SDValue LowerF128_FPROUND(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI)
static SDValue LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9)
const uint32_t * getRTCallPreservedMask(CallingConv::ID CC) const
static SDValue LowerF128_FPEXTEND(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI)
const HexagonInstrInfo * TII
static void fixupVariableFloatArgs(SmallVectorImpl< CCValAssign > &ArgLocs, ArrayRef< ISD::OutputArg > Outs)
Shift and rotation operations.
Definition: ISDOpcodes.h:332
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:283
std::pair< SDValue, SDValue > makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops, unsigned NumOps, bool isSigned, SDLoc dl, bool doesNotReturn=false, bool isReturnValueUsed=true) const
Returns a pair of (return value, chain).
CallLoweringInfo & setChain(SDValue InChain)
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
Definition: ISDOpcodes.h:181
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
SDValue getTargetGlobalAddress(const GlobalValue *GV, SDLoc DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:467
void addLoc(const CCValAssign &V)
const TargetRegisterClass * getRegClass(unsigned Reg) const
getRegClass - Return the register class of the specified virtual register.
void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth=0) const override
computeKnownBitsForTargetNode - Determine which of the bits specified in Mask are known to be either ...
Reg
All possible values of the reg field in the ModR/M byte.
static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, const SparcSubtarget *Subtarget)
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) For double-word atomic operations: ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi) ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi) These correspond to the atomicrmw instruction.
Definition: ISDOpcodes.h:687
Number of individual test Apply this number of consecutive mutations to each input exit after the first new interesting input is found the minimized corpus is saved into the first input directory Number of jobs to run If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
bool hasFnAttr(Attribute::AttrKind A) const
Return true if this function has the given attribute.
Definition: CallSite.h:237
SDValue LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args, SDValue Arg, SDLoc DL, SelectionDAG &DAG) const
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG...
Definition: ISDOpcodes.h:73
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
#define G(x, y, z)
Definition: MD5.cpp:52
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
Definition: ValueTypes.h:110
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
SmallVector< ISD::InputArg, 32 > Ins
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:581
static void LookThroughSetCC(SDValue &LHS, SDValue &RHS, ISD::CondCode CC, unsigned &SPCC)
SDValue getCALLSEQ_START(SDValue Chain, SDValue Op, SDLoc DL)
Return a new CALLSEQ_START node, which always must have a glue result (to ensure it's not CSE'd)...
Definition: SelectionDAG.h:637
unsigned getLocReg() const
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:393
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Definition: SmallVector.h:57
SDValue getRegisterMask(const uint32_t *RegMask)
bool hasStructRetAttr() const
Determine if the function returns a structure through first pointer argument.
Definition: Function.h:360
static SDValue LowerUMULO_SMULO(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI)
const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
Definition: StringRef.h:107
SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override
This contains information for each constraint that we are lowering.
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:191
SmallVector< ISD::OutputArg, 32 > Outs
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: ArrayRef.h:31
const SDValue & getBasePtr() const
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:804
int64_t getImm() const
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
static SDValue LowerF64Op(SDValue Op, SelectionDAG &DAG, unsigned opcode)
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:284
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
PointerType - Class to represent pointers.
Definition: DerivedTypes.h:449
const BasicBlock * getBasicBlock() const
getBasicBlock - Return the LLVM basic block that this instance corresponded to originally.
UNDEF - An undefined node.
Definition: ISDOpcodes.h:169
This class is used to represent ISD::STORE nodes.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:267
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:436
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:97
TargetInstrInfo - Interface to description of machine instruction set.
Function * getFunction(StringRef Name) const
Look up the specified function in the module symbol table.
Definition: Module.cpp:188
SDNode * getNode() const
get the SDNode which holds the desired result
IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
Definition: TargetOpcodes.h:52
bundle_iterator< MachineInstr, instr_iterator > iterator
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
const MachineInstrBuilder & setMemRefs(MachineInstr::mmo_iterator b, MachineInstr::mmo_iterator e) const
CodeModel::Model getCodeModel() const
Returns the code model.
MVT - Machine Value Type.
static bool CC_Sparc64_Half(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
LLVM Basic Block Representation.
Definition: BasicBlock.h:65
const SDValue & getOperand(unsigned i) const
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:41
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
Simple binary floating point operators.
Definition: ISDOpcodes.h:237
bool isExtInLoc() const
MVT getLocVT() const
static bool CC_Sparc_Assign_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE...
Definition: ISDOpcodes.h:607
static bool is64Bit(const char *name)
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector.
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:780
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:219
static bool hasReturnsTwiceAttr(SelectionDAG &DAG, SDValue Callee, ImmutableCallSite *CS)
INSERT_SUBREG - This instruction takes three operands: a register that has subregisters, a register providing an insert value, and a subregister index.
Definition: TargetOpcodes.h:49
static mvt_range fp_valuetypes()
static SDValue LowerF128Store(SDValue Op, SelectionDAG &DAG)
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
static Type * getVoidTy(LLVMContext &C)
Definition: Type.cpp:225
SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:547
SDValue getTargetConstant(uint64_t Val, SDLoc DL, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:436
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1273
static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
unsigned getOpcode() const
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:644
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:57
arg_iterator arg_begin()
Definition: Function.h:472
static SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool Immutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:598
SDValue LowerFormalArguments_64(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const
static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
const SDValue & getValue() const
SDValue getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes())
Bit counting operators with an undefined result for zero inputs.
Definition: ISDOpcodes.h:338
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo...
Definition: ISDOpcodes.h:673
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:468
EVT - Extended Value Type.
Definition: ValueTypes.h:31
bool isFP128Ty() const
isFP128Ty - Return true if this is 'fp128'.
Definition: Type.h:152
std::vector< ArgListEntry > ArgListTy
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
MachinePointerInfo - This class contains a discriminated union of information about pointers in memor...
const SDValue & getRoot() const
Return the root tag of the SelectionDAG.
Definition: SelectionDAG.h:335
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
SDValue CreateStackTemporary(EVT VT, unsigned minAlign=1)
Create a stack temporary, suitable for holding the specified value type.
bool needsCustom() const
const SparcRegisterInfo * getRegisterInfo() const override
const MachinePointerInfo & getPointerInfo() const
unsigned getByValAlign() const
const SDValue & getOffset() const
SDValue getTargetConstantPool(const Constant *C, EVT VT, unsigned Align=0, int Offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:484
TokenFactor - This node takes multiple tokens as input and produces a single token result...
Definition: ISDOpcodes.h:50
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target...
bool hasHardQuad() const
EXTRACT_SUBREG - This instruction takes two operands: a register that has subregisters, and a subregister index.
Definition: TargetOpcodes.h:41
bool usePopc() const
CCState - This class holds information needed while lowering arguments and return values...
static PointerType * getUnqual(Type *ElementType)
PointerType::getUnqual - This constructs a pointer to an object of the specified type in the generic ...
Definition: DerivedTypes.h:460
This is the shared class of boolean and integer constants.
Definition: Constants.h:47
static bool isFP128ABICall(const char *CalleeName)
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - Return the ISD::SETCC ValueType
const char * getLibcallName(RTLIB::Libcall Call) const
Get the libcall routine name for the specified libcall.
SDValue LowerFormalArguments_32(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const
LowerFormalArguments32 - V8 uses a very simple ABI, where all values are passed in either one or two ...
uint64_t getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:388
void setExceptionPointerRegister(unsigned R)
If set to a physical register, this sets the register that receives the exception address on entry to...
const DataLayout * getDataLayout() const
Deprecated in 3.7, will be removed in 3.8.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:179
SDValue getTargetInsertSubreg(int SRIdx, SDLoc DL, EVT VT, SDValue Operand, SDValue Subreg)
A convenience function for creating TargetInstrInfo::INSERT_SUBREG nodes.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:861
Module.h This file contains the declarations for the Module class.
CCValAssign - Represent assignment of one arg/retval to a location.
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:548
const SDValue & getChain() const
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:335
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Represents one node in the SelectionDAG.
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG)
SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const
static mvt_range integer_valuetypes()
Class for arbitrary precision integers.
Definition: APInt.h:73
void setExceptionSelectorRegister(unsigned R)
If set to a physical register, this sets the register that receives the exception typeid on entry to ...
static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG)
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:342
void setMinFunctionAlignment(unsigned Align)
Set the target's minimum function alignment (in log2(bytes))
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
Return the register class that should be used for the specified value type.
static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:383
static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC)
FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC FCC condition.
bool isMemLoc() const
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:285
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:386
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:238
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, SDLoc dl, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array...
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition: ISDOpcodes.h:250
uint64_t RoundUpToAlignment(uint64_t Value, uint64_t Align)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
Definition: MathExtras.h:609
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:542
Representation of each machine instruction.
Definition: MachineInstr.h:51
static MachinePointerInfo getGOT()
getGOT - Return a MachinePointerInfo record that refers to a GOT entry.
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the source.
Definition: ISDOpcodes.h:603
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:516
uint64_t getConstantOperandVal(unsigned i) const
SmallVector< SDValue, 32 > OutVals
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:321
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:217
CondCodes
Definition: Sparc.h:42
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static IntegerType * getInt32Ty(LLVMContext &C)
Definition: Type.cpp:239
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:196
SDValue LowerReturn_64(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, SDLoc DL, SelectionDAG &DAG) const
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:401
static CCValAssign getCustomMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:518
ImmutableCallSite - establish a view to a call site for examination.
Definition: CallSite.h:418
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:233
#define I(x, y, z)
Definition: MD5.cpp:54
#define N
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
MachineBasicBlock * expandAtomicRMW(MachineInstr *MI, MachineBasicBlock *BB, unsigned Opcode, unsigned CondCode=0) const
void setStackPointerRegisterToSaveRestore(unsigned R)
If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
SDValue LowerReturn_32(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, SDLoc DL, SelectionDAG &DAG) const
void size_t size
const SDValue & getOffset() const
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
static SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
SDValue LowerF128Compare(SDValue LHS, SDValue RHS, unsigned &SPCC, SDLoc DL, SelectionDAG &DAG) const
MachineSDNode * getMachineNode(unsigned Opcode, SDLoc dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s), MachineInstr opcode, and operands.
Same for multiplication.
Definition: ISDOpcodes.h:234
static CCValAssign getMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
FSINCOS - Compute both fsin and fcos as a single operation.
Definition: ISDOpcodes.h:512
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
Definition: ISDOpcodes.h:166
int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSS, const AllocaInst *Alloca=nullptr)
Create a new statically sized stack object, returning a nonnegative identifier to represent it...
EVT getValueType() const
Return the ValueType of the referenced return value.
SDValue getConstant(uint64_t Val, SDLoc DL, EVT VT, bool isTarget=false, bool isOpaque=false)
TLSModel::Model getTLSModel(const GlobalValue *GV) const
Returns the TLS model which should be used for the given global variable.
unsigned getReg() const
getReg - Returns the register number.
Function can return twice.
Definition: Attributes.h:104
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
void insert(iterator MBBI, MachineBasicBlock *MBB)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
void setReturnAddressIsTaken(bool s)
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
SDValue getTargetExtractSubreg(int SRIdx, SDLoc DL, EVT VT, SDValue Operand)
A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG nodes.
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array...
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:365
LLVM Value Representation.
Definition: Value.h:69
FMA - Perform a * b + c with no intermediate rounding step.
Definition: ISDOpcodes.h:240
SDValue getRegister(unsigned Reg, EVT VT)
static const char * name
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
void setInsertFencesForAtomic(bool fence)
Set if the DAG builder should automatically insert fences and reduce the order of atomic memory opera...
SDValue getValueType(EVT)
static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
bool isV9() const
iterator end() const
Definition: StringRef.h:92
BasicBlockListType::iterator iterator
bool is64Bit() const
Primary interface to the complete machine description for the target machine.
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:40
static SDValue getFRAMEADDR(uint64_t depth, SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:365
SDValue getSetCC(SDLoc DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
Definition: SelectionDAG.h:726
int64_t getStackPointerBias() const
The 64-bit ABI uses biased stack and frame pointers, so the stack frame of the current function is th...
unsigned getLocMemOffset() const
Conversion operators.
Definition: ISDOpcodes.h:380
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:338
OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val) This corresponds to "store atomic" instruction.
Definition: ISDOpcodes.h:666
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:389
unsigned getAlignment() const
unsigned AllocateReg(unsigned Reg)
AllocateReg - Attempt to allocate one register.
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
Examine constraint string and operand type and determine a weight value.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2, FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR - Perform various unary floating point operations.
Definition: ISDOpcodes.h:506
SDValue LowerF128Op(SDValue Op, SelectionDAG &DAG, const char *LibFuncName, unsigned numArgs) const
unsigned AllocateStack(unsigned Size, unsigned Align)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
void addSuccessor(MachineBasicBlock *succ, uint32_t weight=0)
addSuccessor - Add succ as a successor of this MachineBasicBlock.
Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) This corresponds to "load atomic" instruction.
Definition: ISDOpcodes.h:662
static unsigned toCallerWindow(unsigned Reg)
EVT changeVectorElementTypeToInteger() const
changeVectorElementTypeToInteger - Return a vector with the same number of elements as this vector...
Definition: ValueTypes.h:80
static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG)
SDValue getIntPtrConstant(uint64_t Val, SDLoc DL, bool isTarget=false)
bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:110
static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG)
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:314
BRIND - Indirect branch.
Definition: ISDOpcodes.h:538
This class is used to represent ISD::LOAD nodes.
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary...
Definition: ISDOpcodes.h:527