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HexagonMCInstrInfo.cpp
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1 //===- HexagonMCInstrInfo.cpp - Hexagon sub-class of MCInst ---------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This class extends MCInstrInfo to allow Hexagon specific MCInstr queries
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "HexagonMCInstrInfo.h"
15 
16 #include "Hexagon.h"
17 #include "HexagonBaseInfo.h"
18 
19 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCInstrInfo.h"
22 
23 namespace llvm {
24 iterator_range<MCInst::const_iterator>
26  assert(isBundle(MCI));
28  MCI.begin() + bundleInstructionsOffset, MCI.end());
29 }
30 
33  return (MCI.size() - bundleInstructionsOffset);
34  else
35  return (1);
36 }
37 
39  assert(HexagonMCInstrInfo::isExtendable(MCII, MCI) ||
41  MCOperand &exOp =
43  // If the extended value is a constant, then use it for the extended and
44  // for the extender instructions, masking off the lower 6 bits and
45  // including the assumed bits.
46  if (exOp.isImm()) {
47  unsigned Shift = HexagonMCInstrInfo::getExtentAlignment(MCII, MCI);
48  int64_t Bits = exOp.getImm();
49  exOp.setImm((Bits & 0x3f) << Shift);
50  }
51 }
52 
54  MCInst const &inst0,
55  MCInst const &inst1) {
56  assert((iClass <= 0xf) && "iClass must have range of 0 to 0xf");
57  MCInst *duplexInst = new (Context) MCInst;
58  duplexInst->setOpcode(Hexagon::DuplexIClass0 + iClass);
59 
60  MCInst *SubInst0 = new (Context) MCInst(deriveSubInst(inst0));
61  MCInst *SubInst1 = new (Context) MCInst(deriveSubInst(inst1));
62  duplexInst->addOperand(MCOperand::createInst(SubInst0));
63  duplexInst->addOperand(MCOperand::createInst(SubInst1));
64  return duplexInst;
65 }
66 
68  size_t Index) {
69  assert(Index <= bundleSize(MCB));
70  if (Index == 0)
71  return nullptr;
72  MCInst const *Inst =
73  MCB.getOperand(Index + bundleInstructionsOffset - 1).getInst();
74  if (isImmext(*Inst))
75  return Inst;
76  return nullptr;
77 }
78 
81  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
82 
85 }
86 
88  MCInst const &MCI) {
89  uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
91 }
92 
93 // Return constant extended operand number.
94 unsigned short HexagonMCInstrInfo::getCExtOpNum(MCInstrInfo const &MCII,
95  MCInst const &MCI) {
96  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
98 }
99 
101  MCInst const &MCI) {
102  return (MCII.get(MCI.getOpcode()));
103 }
104 
106  MCInst const &MCI) {
107  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
109 }
110 
111 MCOperand const &
113  MCInst const &MCI) {
114  unsigned O = HexagonMCInstrInfo::getExtendableOp(MCII, MCI);
115  MCOperand const &MO = MCI.getOperand(O);
116 
117  assert((HexagonMCInstrInfo::isExtendable(MCII, MCI) ||
118  HexagonMCInstrInfo::isExtended(MCII, MCI)) &&
119  (MO.isImm() || MO.isExpr()));
120  return (MO);
121 }
122 
124  MCInst const &MCI) {
125  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
127 }
128 
130  MCInst const &MCI) {
131  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
133 }
134 
135 // Return the max value that a constant extendable operand can have
136 // without being extended.
138  MCInst const &MCI) {
139  uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
140  unsigned isSigned =
142  unsigned bits = (F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask;
143 
144  if (isSigned) // if value is signed
145  return ~(-1U << (bits - 1));
146  else
147  return ~(-1U << bits);
148 }
149 
150 // Return the min value that a constant extendable operand can have
151 // without being extended.
153  MCInst const &MCI) {
154  uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
155  unsigned isSigned =
157  unsigned bits = (F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask;
158 
159  if (isSigned) // if value is signed
160  return -1U << (bits - 1);
161  else
162  return 0;
163 }
164 
165 char const *HexagonMCInstrInfo::getName(MCInstrInfo const &MCII,
166  MCInst const &MCI) {
167  return MCII.getName(MCI.getOpcode());
168 }
169 
171  MCInst const &MCI) {
172  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
174 }
175 
177  MCInst const &MCI) {
178  uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
179  unsigned const O =
181  MCOperand const &MCO = MCI.getOperand(O);
182 
183  assert((HexagonMCInstrInfo::isNewValue(MCII, MCI) ||
184  HexagonMCInstrInfo::hasNewValue(MCII, MCI)) &&
185  MCO.isReg());
186  return (MCO);
187 }
188 
190  MCInst const &MCI) {
191  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
192 
195 
196  switch (Target) {
197  default:
198  return Hexagon::ArchV4;
200  return Hexagon::ArchV5;
201  }
202 }
203 
204 // Return the Hexagon ISA class for the insn.
206  MCInst const &MCI) {
207  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
208 
209  return ((F >> HexagonII::TypePos) & HexagonII::TypeMask);
210 }
211 
213  MCSubtargetInfo const &STI,
214  MCInst const &MCI) {
215 
217  int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
218  return ((II[SchedClass].FirstStage + HexagonStages)->getUnits());
219 }
220 
223  return false;
224 
225  for (const auto &I : HexagonMCInstrInfo::bundleInstructions(MCI)) {
226  auto MI = I.getInst();
227  if (isImmext(*MI))
228  return true;
229  }
230 
231  return false;
232 }
233 
234 bool HexagonMCInstrInfo::hasExtenderForIndex(MCInst const &MCB, size_t Index) {
235  return extenderForIndex(MCB, Index) != nullptr;
236 }
237 
238 // Return whether the instruction is a legal new-value producer.
240  MCInst const &MCI) {
241  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
243 }
244 
245 MCInst const &HexagonMCInstrInfo::instruction(MCInst const &MCB, size_t Index) {
246  assert(isBundle(MCB));
247  assert(Index < HEXAGON_PACKET_SIZE);
248  return *MCB.getOperand(bundleInstructionsOffset + Index).getInst();
249 }
250 
252  auto Result = Hexagon::BUNDLE == MCI.getOpcode();
253  assert(!Result || (MCI.size() > 0 && MCI.getOperand(0).isImm()));
254  return Result;
255 }
256 
257 // Return whether the insn is an actual insn.
258 bool HexagonMCInstrInfo::isCanon(MCInstrInfo const &MCII, MCInst const &MCI) {
259  return (!HexagonMCInstrInfo::getDesc(MCII, MCI).isPseudo() &&
260  !HexagonMCInstrInfo::isPrefix(MCII, MCI) &&
262 }
263 
265  return ((Reg >= Hexagon::D0 && Reg <= Hexagon::D3) ||
266  (Reg >= Hexagon::D8 && Reg <= Hexagon::D11));
267 }
268 
269 bool HexagonMCInstrInfo::isDuplex(MCInstrInfo const &MCII, MCInst const &MCI) {
271 }
272 
273 // Return whether the instruction needs to be constant extended.
274 // 1) Always return true if the instruction has 'isExtended' flag set.
275 //
276 // isExtendable:
277 // 2) For immediate extended operands, return true only if the value is
278 // out-of-range.
279 // 3) For global address, always return true.
280 
282  MCInst const &MCI) {
283  if (HexagonMCInstrInfo::isExtended(MCII, MCI))
284  return true;
285 
286  if (!HexagonMCInstrInfo::isExtendable(MCII, MCI))
287  return false;
288 
289  short ExtOpNum = HexagonMCInstrInfo::getCExtOpNum(MCII, MCI);
290  int MinValue = HexagonMCInstrInfo::getMinValue(MCII, MCI);
291  int MaxValue = HexagonMCInstrInfo::getMaxValue(MCII, MCI);
292  MCOperand const &MO = MCI.getOperand(ExtOpNum);
293 
294  // We could be using an instruction with an extendable immediate and shoehorn
295  // a global address into it. If it is a global address it will be constant
296  // extended. We do this for COMBINE.
297  // We currently only handle isGlobal() because it is the only kind of
298  // object we are going to end up with here for now.
299  // In the future we probably should add isSymbol(), etc.
300  if (MO.isExpr())
301  return true;
302 
303  // If the extendable operand is not 'Immediate' type, the instruction should
304  // have 'isExtended' flag set.
305  assert(MO.isImm() && "Extendable operand must be Immediate type");
306 
307  int ImmValue = MO.getImm();
308  return (ImmValue < MinValue || ImmValue > MaxValue);
309 }
310 
312  MCInst const &MCI) {
313  uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
315 }
316 
318  MCInst const &MCI) {
319  uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
321 }
322 
323 bool HexagonMCInstrInfo::isFloat(MCInstrInfo const &MCII, MCInst const &MCI) {
324  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
325  return ((F >> HexagonII::FPPos) & HexagonII::FPMask);
326 }
327 
329  auto Op = MCI.getOpcode();
330  return (Op == Hexagon::A4_ext_b || Op == Hexagon::A4_ext_c ||
331  Op == Hexagon::A4_ext_g || Op == Hexagon::A4_ext);
332 }
333 
335  assert(isBundle(MCI));
336  int64_t Flags = MCI.getOperand(0).getImm();
337  return (Flags & innerLoopMask) != 0;
338 }
339 
341  return (Reg >= Hexagon::R0 && Reg <= Hexagon::R31);
342 }
343 
345  return ((Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
346  (Reg >= Hexagon::R16 && Reg <= Hexagon::R23));
347 }
348 
349 // Return whether the insn is a new-value consumer.
351  MCInst const &MCI) {
352  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
354 }
355 
356 // Return whether the operand can be constant extended.
358  MCInst const &MCI,
359  unsigned short OperandNum) {
360  uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
362  OperandNum;
363 }
364 
366  assert(isBundle(MCI));
367  int64_t Flags = MCI.getOperand(0).getImm();
368  return (Flags & outerLoopMask) != 0;
369 }
370 
372  MCInst const &MCI) {
373  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
375 }
376 
378  MCInst const &MCI) {
379  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
380  return (
382 }
383 
385  return (Reg >= Hexagon::P0 && Reg <= Hexagon::P3_0);
386 }
387 
388 bool HexagonMCInstrInfo::isPrefix(MCInstrInfo const &MCII, MCInst const &MCI) {
389  return (HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypePREFIX);
390 }
391 
392 bool HexagonMCInstrInfo::isSolo(MCInstrInfo const &MCII, MCInst const &MCI) {
393  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
394  return ((F >> HexagonII::SoloPos) & HexagonII::SoloMask);
395 }
396 
397 bool HexagonMCInstrInfo::isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI) {
398  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
400 }
401 
403  MCInst const &MCI) {
404  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
406 }
407 
409  MCInst Nop;
410  Nop.setOpcode(Hexagon::A2_nop);
411  assert(isBundle(MCB));
412  while ((HexagonMCInstrInfo::isInnerLoop(MCB) &&
416  MCB.addOperand(MCOperand::createInst(new MCInst(Nop)));
417 }
418 
420  MCInst const &MCI) {
422  return false;
423 
424  unsigned SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
425  switch (SchedClass) {
426  case Hexagon::Sched::ALU32_3op_tc_2_SLOT0123:
427  case Hexagon::Sched::ALU64_tc_2_SLOT23:
428  case Hexagon::Sched::ALU64_tc_3x_SLOT23:
429  case Hexagon::Sched::M_tc_2_SLOT23:
430  case Hexagon::Sched::M_tc_3x_SLOT23:
431  case Hexagon::Sched::S_2op_tc_2_SLOT23:
432  case Hexagon::Sched::S_3op_tc_2_SLOT23:
433  case Hexagon::Sched::S_3op_tc_3x_SLOT23:
434  return true;
435  }
436  return false;
437 }
438 
440  DuplexCandidate Candidate) {
441  assert(Candidate.packetIndexI < MCB.size());
442  assert(Candidate.packetIndexJ < MCB.size());
443  assert(isBundle(MCB));
444  MCInst *Duplex =
445  deriveDuplex(Context, Candidate.iClass,
446  *MCB.getOperand(Candidate.packetIndexJ).getInst(),
447  *MCB.getOperand(Candidate.packetIndexI).getInst());
448  assert(Duplex != nullptr);
449  MCB.getOperand(Candidate.packetIndexI).setInst(Duplex);
450  MCB.erase(MCB.begin() + Candidate.packetIndexJ);
451 }
452 
454  assert(isBundle(MCI));
455  MCOperand &Operand = MCI.getOperand(0);
456  Operand.setImm(Operand.getImm() | innerLoopMask);
457 }
458 
460  assert(isBundle(MCI));
461  MCOperand &Operand = MCI.getOperand(0);
462  Operand.setImm(Operand.getImm() | outerLoopMask);
463 }
464 }
bool isSoloAin1(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn can be packaged only with an A-type insn in slot #1.
#define HEXAGON_PACKET_INNER_SIZE
Definition: Hexagon.h:36
bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
iterator end()
Definition: MCInst.h:177
iterator begin()
Definition: MCInst.h:175
unsigned short getNewValueOp(MCInstrInfo const &MCII, MCInst const &MCI)
MCInst const * extenderForIndex(MCInst const &MCB, size_t Index)
bool isReg() const
Definition: MCInst.h:56
unsigned getBitCount(MCInstrInfo const &MCII, MCInst const &MCI)
void clampExtended(MCInstrInfo const &MCII, MCInst &MCI)
void setInst(const MCInst *Val)
Definition: MCInst.h:106
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:138
bool isIntRegForSubInst(unsigned Reg)
bool isBundle(MCInst const &MCI)
bool isSolo(MCInstrInfo const &MCII, MCInst const &MCI)
F(f)
bool isDblRegForSubInst(unsigned Reg)
bool isOuterLoop(MCInst const &MCI)
bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
bool isImmext(MCInst const &MCI)
MCInst const & instruction(MCInst const &MCB, size_t Index)
#define HEXAGON_PACKET_SIZE
Definition: Hexagon.h:33
void erase(iterator I)
Definition: MCInst.h:173
Reg
All possible values of the reg field in the ModR/M byte.
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget's CPU.
void replaceDuplex(MCContext &Context, MCInst &MCB, DuplexCandidate Candidate)
Context object for machine code objects.
Definition: MCContext.h:48
bool isOperandExtended(MCInstrInfo const &MCII, MCInst const &MCI, unsigned short OperandNum)
int getMaxValue(MCInstrInfo const &MCII, MCInst const &MCI)
const InstrItinerary * InstrItineraries
Definition: MCSchedule.h:198
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:150
bool isPrefix(MCInstrInfo const &MCII, MCInst const &MCI)
bool isImm() const
Definition: MCInst.h:57
void setImm(int64_t Val)
Definition: MCInst.h:78
int getMinValue(MCInstrInfo const &MCII, MCInst const &MCI)
char const * getName(MCInstrInfo const &MCII, MCInst const &MCI)
const char * getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
Definition: MCInstrInfo.h:51
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
bool isExpr() const
Definition: MCInst.h:59
iterator_range< MCInst::const_iterator > bundleInstructions(MCInst const &MCI)
bool prefersSlot3(MCInstrInfo const &MCII, MCInst const &MCI)
bool isCanon(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI)
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
size_t size() const
Definition: MCInst.h:174
void setOpcode(unsigned Op)
Definition: MCInst.h:158
size_t const bundleInstructionsOffset
bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)
HexagonII::MemAccessSize getAccessSize(MCInstrInfo const &MCII, MCInst const &MCI)
BUNDLE - This instruction represents an instruction bundle.
Definition: TargetOpcodes.h:91
A range adaptor for a pair of iterators.
unsigned getOpcode() const
Definition: MCInst.h:159
Target - Wrapper for Target specific information.
bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI)
int64_t getImm() const
Definition: MCInst.h:74
bool isExtended(MCInstrInfo const &MCII, MCInst const &MCI)
#define HEXAGON_PACKET_OUTER_SIZE
Definition: Hexagon.h:37
static MCOperand createInst(const MCInst *Val)
Definition: MCInst.h:135
MCInst deriveSubInst(MCInst const &Inst)
bool isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn can be packaged only with A and X-type insns.
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:528
bool hasExtenderForIndex(MCInst const &MCB, size_t Index)
#define I(x, y, z)
Definition: MD5.cpp:54
MCSubtargetInfo - Generic base class for all target subtargets.
const InstrStage HexagonStages[]
const MCInst * getInst() const
Definition: MCInst.h:102
MCInstrDesc const & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
size_t bundleSize(MCInst const &MCI)
int getSubTarget(MCInstrInfo const &MCII, MCInst const &MCI)
bool hasImmExt(MCInst const &MCI)
bool isInnerLoop(MCInst const &MCI)
bool isFloat(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether it is a floating-point insn.
An itinerary represents the scheduling information for an instruction.
unsigned getUnits(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Return the slots used by the insn.
bool isConstExtended(MCInstrInfo const &MCII, MCInst const &MCI)
void addOperand(const MCOperand &Op)
Definition: MCInst.h:168
MCInst * deriveDuplex(MCContext &Context, unsigned iClass, MCInst const &inst0, MCInst const &inst1)
bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned short getCExtOpNum(MCInstrInfo const &MCII, MCInst const &MCI)
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:33
bool isPredicatedTrue(MCInstrInfo const &MCII, MCInst const &MCI)
MCOperand const & getExtendableOperand(MCInstrInfo const &MCII, MCInst const &MCI)
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:164
MCOperand const & getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI)