15 #ifndef LLVM_CODEGEN_SCHEDULEDAGINSTRS_H
16 #define LLVM_CODEGEN_SCHEDULEDAGINSTRS_H
26 class MachineFrameInfo;
27 class MachineLoopInfo;
28 class MachineDominatorTree;
30 class RegPressureTracker;
60 typedef SparseMultiSet<PhysRegSUOper, llvm::identity<unsigned>, uint16_t>
146 typedef std::vector<std::pair<MachineInstr *, MachineInstr *> >
200 unsigned regioninstrs);
264 assert((Addr ==
nullptr || Addr == &
SUnits[0]) &&
265 "SUnits std::vector reallocated on the fly!");
virtual void finishBlock()
finishBlock - Clean up after scheduling in the given block.
const MCSchedClassDesc * resolveSchedClass(const MachineInstr *MI) const
Return the MCSchedClassDesc for this instruction.
unsigned getSparseSetIndex() const
static unsigned virtReg2Index(unsigned Reg)
virtReg2Index - Convert a virtual register number to a 0-based index.
Record a physical register access.
void addVRegDefDeps(SUnit *SU, unsigned OperIdx)
addVRegDefDeps - Add register output and data dependencies from this SUnit to instructions that occur...
void buildSchedGraph(AliasAnalysis *AA, RegPressureTracker *RPTracker=nullptr, PressureDiffs *PDiffs=nullptr)
buildSchedGraph - Build SUnits from the MachineBasicBlock that we are input.
void dumpNode(const SUnit *SU) const override
MachineInstr * getInstr() const
getInstr - Return the representative MachineInstr for this SUnit.
TargetSchedModel SchedModel
TargetSchedModel provides an interface to the machine model.
bool CanHandleTerminators
The standard DAG builder does not normally include terminators as DAG nodes because it does not creat...
MachineBasicBlock::iterator begin() const
begin - Return an iterator to the top of the current scheduling region.
const MCSchedClassDesc * getSchedClass(SUnit *SU) const
Resolve and cache a resolved scheduling class for an SUnit.
unsigned NumRegionInstrs
Instructions in this region (distance(RegionBegin, RegionEnd)).
void addPhysRegDataDeps(SUnit *SU, unsigned OperIdx)
MO is an operand of SU's instruction that defines a physical register.
void fixupKills(MachineBasicBlock *MBB)
Fix register kill flags that scheduling has made invalid.
virtual void startBlock(MachineBasicBlock *BB)
startBlock - Prepare to perform scheduling in the given block.
const TargetSchedModel * getSchedModel() const
Get the machine model for instruction scheduling.
std::vector< SUnit * > PendingLoads
PendingLoads - Remember where unknown loads are after the most recent unknown store, as we iterate.
MachineBasicBlock::iterator RegionEnd
The end of the range to be scheduled.
DenseMap< MachineInstr *, SUnit * > MISUnitMap
After calling BuildSchedGraph, each machine instruction in the current scheduling region is mapped to...
VReg2SUnit(unsigned reg, SUnit *su)
void addSchedBarrierDeps()
addSchedBarrierDeps - Add dependencies from instructions in the current list of instructions being sc...
Provide an instruction scheduling machine model to CodeGen passes.
An individual mapping from virtual register number to SUnit.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
const MachineFrameInfo * MFI
MachineBasicBlock::iterator RegionBegin
The beginning of the range to be scheduled.
void addVRegUseDeps(SUnit *SU, unsigned OperIdx)
addVRegUseDeps - Add a register data dependency if the instruction that defines the virtual register ...
VReg2UseMap VRegUses
After calling BuildSchedGraph, each vreg used in the scheduling region is mapped to a set of SUnits...
bool IsPostRA
isPostRA flag indicates vregs cannot be present.
virtual void enterRegion(MachineBasicBlock *bb, MachineBasicBlock::iterator begin, MachineBasicBlock::iterator end, unsigned regioninstrs)
Initialize the scheduler state for the next scheduling region.
bundle_iterator< MachineInstr, instr_iterator > iterator
bool RemoveKillFlags
True if the DAG builder should remove kill flags (in preparation for rescheduling).
bundle_iterator - MachineBasicBlock iterator that automatically skips over MIs that are inside bundle...
Summarize the scheduling resources required for an instruction of a particular scheduling class...
Track the current register pressure at some position in the instruction stream, and remember the high...
VReg2SUnitMap VRegDefs
Track the last instruction in this region defining each virtual register.
virtual void exitRegion()
Notify that the scheduler has finished scheduling the current region.
const MCSchedClassDesc * SchedClass
LiveIntervals * getLIS() const
Expose LiveIntervals for use in DAG mutators and such.
std::string getDAGName() const override
Return a label for the region of code covered by the DAG.
void addPhysRegDeps(SUnit *SU, unsigned OperIdx)
addPhysRegDeps - Add register dependencies (data, anti, and output) from this SUnit to following inst...
bool hasInstrSchedModel() const
Return true if this machine model includes an instruction-level scheduling model. ...
std::string getGraphNodeLabel(const SUnit *SU) const override
Return a label for a DAG node that points to an instruction.
PhysRegSUOper(SUnit *su, int op, unsigned R)
bool toggleKillFlag(MachineInstr *MI, MachineOperand &MO)
Toggle a register operand kill flag.
MachineOperand class - Representation of each machine instruction operand.
Reg2SUnitsMap Defs
State internal to DAG building.
const MachineLoopInfo * MLI
virtual void finalizeSchedule()
finalizeSchedule - Allow targets to perform final scheduling actions at the level of the whole Machin...
virtual void schedule()=0
schedule - Order nodes according to selected style, filling in the Sequence member.
MachineBasicBlock::iterator end() const
end - Return an iterator to the bottom of the current scheduling region.
ScheduleDAGInstrs(MachineFunction &mf, const MachineLoopInfo *mli, bool IsPostRAFlag, bool RemoveKillFlags=false, LiveIntervals *LIS=nullptr)
SUnit * getSUnit(MachineInstr *MI) const
getSUnit - Return an existing SUnit for this MI, or NULL.
ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of MachineInstrs. ...
Representation of each machine instruction.
SparseMultiSet< VReg2SUnit, VirtReg2IndexFunctor > VReg2UseMap
Track local uses of virtual registers.
unsigned getSparseSetIndex() const
SUnit * newSUnit(MachineInstr *MI)
newSUnit - Creates a new SUnit and return a ptr to it.
void startBlockForKills(MachineBasicBlock *BB)
PostRA helper for rewriting kill flags.
SparseSet< VReg2SUnit, VirtReg2IndexFunctor > VReg2SUnitMap
Use SparseSet as a SparseMap by relying on the fact that it never compares ValueT's, only unsigned keys.
void initSUnits()
Create an SUnit for each real instruction, numbered in top-down toplological order.
SparseMultiSet< PhysRegSUOper, llvm::identity< unsigned >, uint16_t > Reg2SUnitsMap
Use a SparseMultiSet to track physical registers.
MachineInstr * FirstDbgValue
MachineBasicBlock * BB
State specific to the current scheduling region.
std::vector< SUnit > SUnits
BitVector LiveRegs
Set of live physical registers for updating kill flags.
LiveIntervals * LIS
Live Intervals provides reaching defs in preRA scheduling.
std::vector< std::pair< MachineInstr *, MachineInstr * > > DbgValueVector
DbgValues - Remember instruction that precedes DBG_VALUE.
SUnit - Scheduling unit. This is a node in the scheduling DAG.
~ScheduleDAGInstrs() override