43 #define DEBUG_TYPE "regalloc"
45 STATISTIC(NumSpillSlots,
"Number of spill slots allocated");
46 STATISTIC(NumIdCopies,
"Number of identity moves eliminated after rewriting");
58 TII = mf.getSubtarget().getInstrInfo();
63 Virt2StackSlotMap.clear();
64 Virt2SplitMap.clear();
72 Virt2PhysMap.resize(NumRegs);
73 Virt2StackSlotMap.resize(NumRegs);
74 Virt2SplitMap.resize(NumRegs);
105 "attempt to assign stack slot to already spilled register");
107 return Virt2StackSlotMap[virtReg] = createSpillSlot(RC);
113 "attempt to assign stack slot to already spilled register");
116 "illegal fixed frame index");
117 Virt2StackSlotMap[virtReg] =
SS;
121 OS <<
"********** REGISTER MAP **********\n";
125 OS <<
'[' <<
PrintReg(Reg, TRI) <<
" -> "
126 <<
PrintReg(Virt2PhysMap[Reg], TRI) <<
"] "
134 OS <<
'[' <<
PrintReg(Reg, TRI) <<
" -> fi#" << Virt2StackSlotMap[
Reg]
141 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
169 void addMBBLiveIns();
184 "Virtual Register Rewriter",
false,
false)
193 char VirtRegRewriter::
ID = 0;
195 void VirtRegRewriter::getAnalysisUsage(
AnalysisUsage &AU)
const {
196 AU.setPreservesCFG();
209 TM = &MF->getTarget();
210 TRI = MF->getSubtarget().getRegisterInfo();
211 TII = MF->getSubtarget().getInstrInfo();
212 MRI = &MF->getRegInfo();
213 Indexes = &getAnalysis<SlotIndexes>();
214 LIS = &getAnalysis<LiveIntervals>();
215 VRM = &getAnalysis<VirtRegMap>();
216 DEBUG(
dbgs() <<
"********** REWRITE VIRTUAL REGISTERS **********\n"
217 <<
"********** Function: "
218 << MF->getName() <<
'\n');
222 LIS->addKillFlags(VRM);
231 getAnalysis<LiveDebugVariables>().emitDebugValues(VRM);
236 MRI->clearVirtRegs();
242 void VirtRegRewriter::addMBBLiveIns() {
244 for (
unsigned Idx = 0, IdxE = MRI->getNumVirtRegs(); Idx != IdxE; ++Idx) {
246 if (MRI->reg_nodbg_empty(VirtReg))
249 if (LI.
empty() || LIS->intervalIsInOneMBB(LI))
253 unsigned PhysReg = VRM->getPhys(VirtReg);
258 for (
const auto &Seg : S.segments) {
259 if (!Indexes->findLiveInMBBs(Seg.start, Seg.end, LiveIn))
262 unsigned SubReg = SR.getSubReg();
263 unsigned SubRegIndex = SR.getSubRegIndex();
264 unsigned SubRegLaneMask = TRI->getSubRegIndexLaneMask(SubRegIndex);
265 if ((SubRegLaneMask & S.LaneMask) == 0)
267 for (
unsigned i = 0, e = LiveIn.
size(); i != e; ++i) {
268 LiveIn[i]->addLiveIn(SubReg);
276 for (
const auto &Seg : LI.
segments) {
277 if (!Indexes->findLiveInMBBs(Seg.start, Seg.end, LiveIn))
279 for (
unsigned i = 0, e = LiveIn.
size(); i != e; ++i)
289 MBB.sortUniqueLiveIns();
294 bool VirtRegRewriter::readsUndefSubreg(
const MachineOperand &MO)
const {
302 SlotIndex BaseIndex = LIS->getInstructionIndex(&MI);
305 assert(LI.
liveAt(BaseIndex) &&
306 "Reads of completely dead register should be marked undef already");
308 unsigned UseMask = TRI->getSubRegIndexLaneMask(SubRegIdx);
311 if ((SR.LaneMask & UseMask) != 0 && SR.liveAt(BaseIndex))
317 void VirtRegRewriter::rewrite() {
318 bool NoSubRegLiveness = !MRI->subRegLivenessEnabled();
331 PhysRegs.setUniverse(TRI->getNumRegs());
339 MBBI != MBBE; ++MBBI) {
341 bool IsExitBB = MBBI->succ_empty();
343 MII = MBBI->instr_begin(), MIE = MBBI->instr_end(); MII != MIE;) {
352 if (!HasUWTable && IsExitBB && MI->
isCall()) {
376 MRI->addPhysRegsUsedFromRegMask(MO.
getRegMask());
384 VRM->getPhys(MO.
getReg()) :
389 unsigned VirtReg = MO.
getReg();
390 unsigned PhysReg = VRM->getPhys(VirtReg);
392 "Instruction uses unmapped VirtReg");
393 assert(!MRI->isReserved(PhysReg) &&
"Reserved register assignment");
398 if (NoSubRegLiveness) {
414 if (readsUndefSubreg(MO))
419 }
else if (!MO.
isDead()) {
426 unsigned LaneMask = TRI->getSubRegIndexLaneMask(SubReg);
440 PhysReg = TRI->getSubReg(PhysReg, SubReg);
441 assert(PhysReg &&
"Invalid SubReg for physical register");
451 while (!SuperKills.
empty())
454 while (!SuperDeads.
empty())
457 while (!SuperDefs.
empty())
465 DEBUG(
dbgs() <<
"Deleting identity copy.\n");
467 Indexes->removeMachineInstrFromMaps(MI);
475 if (NoReturnInsts.
empty()) {
477 RegI = PhysRegs.
begin(), E = PhysRegs.end(); RegI != E; ++RegI)
478 if (!MRI->reg_nodbg_empty(*RegI))
479 MRI->setPhysRegUsed(*RegI);
482 I = PhysRegs.begin(), E = PhysRegs.end();
I != E; ++
I) {
484 if (MRI->reg_nodbg_empty(Reg))
489 for (
MachineInstr &It : MRI->reg_nodbg_instructions(Reg)) {
490 if (!NoReturnInsts.
count(&It)) {
491 MRI->setPhysRegUsed(Reg);
bool hasPhys(unsigned virtReg) const
returns true if the specified virtual register is mapped to a physical register
void push_back(const T &Elt)
mop_iterator operands_end()
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
const GlobalValue * getGlobal() const
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
STATISTIC(NumFunctions,"Total number of functions")
static unsigned index2VirtReg(unsigned Index)
index2VirtReg - Convert a 0-based index to a virtual register number.
A Module instance is used to store all the information related to an LLVM module. ...
unsigned getSimpleHint(unsigned VReg) const
getSimpleHint - Return the preferred register allocation hint, or 0 if a standard simple hint (Type =...
bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
static bool isImpreciseLaneMask(unsigned LaneMask)
Returns true if the given lane mask is imprecise.
LiveInterval - This class represents the liveness of a register, or stack slot.
void setIsUndef(bool Val=true)
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
size_type count(PtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
void print(raw_ostream &OS, const Module *M=nullptr) const override
print - Print out the internal state of the pass.
bool isValid() const
Returns true if this iterator is not yet at the end.
A live range for subregisters.
Instructions::iterator instr_iterator
aarch64 collect AArch64 Collect Linker Optimization Hint(LOH)"
unsigned getSize() const
getSize - Return the size of the register in bytes, which is also the size of a stack slot allocated ...
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
#define INITIALIZE_PASS_DEPENDENCY(depName)
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
T LLVM_ATTRIBUTE_UNUSED_RESULT pop_back_val()
static unsigned addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
iterator_range< subrange_iterator > subranges()
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
const TargetRegisterClass * getRegClass(unsigned Reg) const
getRegClass - Return the register class of the specified virtual register.
Reg
All possible values of the reg field in the ModR/M byte.
Function must be in a unwind table.
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
PrintReg - Helper class for printing registers on a raw_ostream.
const HexagonRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
int getObjectIndexBegin() const
Return the minimum frame object index.
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
const char * getRegClassName(const TargetRegisterClass *Class) const
getRegClassName - Returns the name of the register class.
TargetInstrInfo - Interface to description of machine instruction set.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
unsigned getAlignment() const
getAlignment - Return the minimum required alignment for a register of this class.
Iterator that enumerates the sub-registers of a Reg and the associated sub-register indices...
bool hasPreferredPhys(unsigned VirtReg)
returns true if VirtReg is assigned to its preferred physreg.
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Represent the analysis usage information of a pass.
Function doesn't unwind stack.
Mark the function as not returning.
bool hasKnownPreference(unsigned VirtReg)
returns true if VirtReg has a known preferred register.
unsigned getSubReg() const
int CreateSpillStackObject(uint64_t Size, unsigned Alignment)
Create a new statically sized stack object that represents a spill slot, returning a nonnegative iden...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool liveAt(SlotIndex index) const
const_iterator begin() const
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Promote Memory to Register
bool isIdentityCopy() const
Return true is the instruction is an identity copy.
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void addRegisterDefined(unsigned Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Virtual Register Rewriter
Representation of each machine instruction.
static bool isPhysicalRegister(unsigned Reg)
isPhysicalRegister - Return true if the specified register number is in the physical register namespa...
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
void setReg(unsigned Reg)
Change the register this operand corresponds to.
bool isCall(QueryType Type=AnyInBundle) const
void setSubReg(unsigned subReg)
INITIALIZE_PASS_BEGIN(VirtRegRewriter,"virtregrewriter","Virtual Register Rewriter", false, false) INITIALIZE_PASS_END(VirtRegRewriter
unsigned getReg() const
getReg - Returns the register number.
mop_iterator operands_begin()
MachineRegisterInfo & getRegInfo() const
char & VirtRegRewriterID
VirtRegRewriter pass.
BasicBlockListType::iterator iterator
This class implements an extremely fast bulk output stream that can only output to a stream...
int assignVirt2StackSlot(unsigned virtReg)
create a mapping for the specifed virtual register to the next available stack slot ...
Primary interface to the complete machine description for the target machine.
bool addRegisterKilled(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
unsigned getPhys(unsigned virtReg) const
returns the physical register mapped to the specified virtual register
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register. ...
std::pair< unsigned, unsigned > getRegAllocationHint(unsigned VReg) const
getRegAllocationHint - Return the register allocation hint for the specified virtual register...
bool hasSubRanges() const
Returns true if subregister liveness information is available.
SlotIndex - An opaque wrapper around machine indexes.