47 #define DEBUG_TYPE "reginfo"
49 #define GET_REGINFO_TARGET_DESC
50 #include "PPCGenRegisterInfo.inc"
54 cl::desc(
"Enable use of a base pointer for complex stack frames"));
58 cl::desc(
"Force the use of a base pointer in every function"));
63 TM.isPPC64() ? 0 : 1),
65 ImmToIdxMap[
PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
66 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
67 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
68 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
69 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
70 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
71 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
72 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
73 ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32;
76 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
77 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
78 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
79 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
80 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8;
92 return &PPC::G8RC_NOX0RegClass;
93 return &PPC::GPRC_NOR0RegClass;
97 return &PPC::G8RCRegClass;
98 return &PPC::GPRCRegClass;
106 return CSR_64_AllRegs_VSX_SaveList;
108 return CSR_64_AllRegs_Altivec_SaveList;
109 return CSR_64_AllRegs_SaveList;
114 ? (Subtarget.
hasAltivec() ? CSR_Darwin64_Altivec_SaveList
115 : CSR_Darwin64_SaveList)
116 : (Subtarget.
hasAltivec() ? CSR_Darwin32_Altivec_SaveList
117 : CSR_Darwin32_SaveList);
124 ? (SaveR2 ? CSR_SVR464_R2_Altivec_SaveList
125 : CSR_SVR464_Altivec_SaveList)
126 : (SaveR2 ? CSR_SVR464_R2_SaveList : CSR_SVR464_SaveList))
127 : (Subtarget.
hasAltivec() ? CSR_SVR432_Altivec_SaveList
128 : CSR_SVR432_SaveList);
137 return CSR_64_AllRegs_VSX_RegMask;
139 return CSR_64_AllRegs_Altivec_RegMask;
140 return CSR_64_AllRegs_RegMask;
145 : CSR_Darwin64_RegMask)
146 : (Subtarget.
hasAltivec() ? CSR_Darwin32_Altivec_RegMask
147 : CSR_Darwin32_RegMask);
150 : CSR_SVR464_RegMask)
151 : (Subtarget.
hasAltivec() ? CSR_SVR432_Altivec_RegMask
152 : CSR_SVR432_RegMask);
157 return CSR_NoRegs_RegMask;
161 for (
unsigned PseudoReg : {PPC::ZERO, PPC::ZERO8,
PPC::RM})
162 Mask[PseudoReg / 32] &= ~(1u << (PseudoReg % 32));
172 Reserved.
set(PPC::ZERO);
173 Reserved.
set(PPC::ZERO8);
177 Reserved.
set(PPC::FP);
178 Reserved.
set(PPC::FP8);
182 Reserved.
set(PPC::BP);
183 Reserved.
set(PPC::BP8);
187 Reserved.
set(PPC::CTR);
188 Reserved.
set(PPC::CTR8);
190 Reserved.
set(PPC::R1);
191 Reserved.
set(PPC::LR);
192 Reserved.
set(PPC::LR8);
196 Reserved.
set(PPC::VRSAVE);
201 Reserved.
set(PPC::R13);
206 Reserved.
set(PPC::R13);
208 Reserved.
set(PPC::X1);
209 Reserved.
set(PPC::X13);
211 if (TFI->needsFP(MF))
212 Reserved.
set(PPC::X31);
215 Reserved.
set(PPC::X30);
226 Reserved.
set(PPC::X2);
232 if (TFI->needsFP(MF))
233 Reserved.
set(PPC::R31);
238 Reserved.
set(PPC::R29);
240 Reserved.
set(PPC::R30);
245 Reserved.
set(PPC::R30);
250 IE = PPC::VRRCRegClass.end();
I !=
IE; ++
I)
259 const unsigned DefaultSafety = 1;
261 switch (RC->
getID()) {
264 case PPC::G8RC_NOX0RegClassID:
265 case PPC::GPRC_NOR0RegClassID:
266 case PPC::G8RCRegClassID:
267 case PPC::GPRCRegClassID: {
268 unsigned FP = TFI->
hasFP(MF) ? 1 : 0;
269 return 32 - FP - DefaultSafety;
271 case PPC::F8RCRegClassID:
272 case PPC::F4RCRegClassID:
273 case PPC::QFRCRegClassID:
274 case PPC::QSRCRegClassID:
275 case PPC::QBRCRegClassID:
276 case PPC::VRRCRegClassID:
277 case PPC::VFRCRegClassID:
278 case PPC::VSLRCRegClassID:
279 case PPC::VSHRCRegClassID:
280 return 32 - DefaultSafety;
281 case PPC::VSRCRegClassID:
282 case PPC::VSFRCRegClassID:
283 case PPC::VSSRCRegClassID:
284 return 64 - DefaultSafety;
285 case PPC::CRRCRegClassID:
286 return 8 - DefaultSafety;
298 if (RC == &PPC::F8RCRegClass)
299 return &PPC::VSFRCRegClass;
300 else if (RC == &PPC::VRRCRegClass)
301 return &PPC::VSRCRegClass;
302 else if (RC == &PPC::F4RCRegClass && Subtarget.
hasP8Vector())
303 return &PPC::VSSRCRegClass;
345 assert((maxCallFrameSize & (MaxAlign-1)) == 0 &&
346 "Maximum call-frame size not sufficiently aligned");
358 if (MaxAlign < TargetAlign &&
isInt<16>(FrameSize)) {
378 if (MaxAlign > TargetAlign) {
379 unsigned UnalNegSizeReg = NegSizeReg;
384 BuildMI(MBB, II, dl, TII.
get(PPC::LI8), NegSizeReg)
385 .addImm(~(MaxAlign-1));
387 unsigned NegSizeReg1 = NegSizeReg;
389 BuildMI(MBB, II, dl, TII.
get(PPC::AND8), NegSizeReg)
392 KillNegSizeReg =
true;
395 BuildMI(MBB, II, dl, TII.
get(PPC::STDUX), PPC::X1)
401 .
addImm(maxCallFrameSize);
403 if (MaxAlign > TargetAlign) {
404 unsigned UnalNegSizeReg = NegSizeReg;
409 BuildMI(MBB, II, dl, TII.
get(PPC::LI), NegSizeReg)
410 .addImm(~(MaxAlign-1));
412 unsigned NegSizeReg1 = NegSizeReg;
417 KillNegSizeReg =
true;
420 BuildMI(MBB, II, dl, TII.
get(PPC::STWUX), PPC::R1)
426 .
addImm(maxCallFrameSize);
466 if (SrcReg != PPC::CR0) {
471 BuildMI(MBB, II, dl, TII.
get(LP64 ? PPC::RLWINM8 : PPC::RLWINM),
Reg)
473 .
addImm(getEncodingValue(SrcReg) * 4)
504 "RESTORE_CR does not define its destination");
511 if (DestReg != PPC::CR0) {
515 unsigned ShiftBits = getEncodingValue(DestReg)*4;
517 BuildMI(MBB, II, dl, TII.
get(LP64 ? PPC::RLWINM8 : PPC::RLWINM),
Reg)
522 BuildMI(MBB, II, dl, TII.
get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg)
560 BuildMI(MBB, II, dl, TII.
get(LP64 ? PPC::RLWINM8 : PPC::RLWINM),
Reg)
562 .
addImm(getEncodingValue(SrcReg))
591 "RESTORE_CRBIT does not define its destination");
602 unsigned ShiftBits = getEncodingValue(DestReg);
604 BuildMI(MBB, II, dl, TII.
get(LP64 ? PPC::RLWIMI8 : PPC::RLWIMI), RegO)
606 .
addImm(ShiftBits ? 32-ShiftBits : 0)
609 BuildMI(MBB, II, dl, TII.
get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF),
662 "RESTORE_VRSAVE does not define its destination");
667 BuildMI(MBB, II, dl, TII.
get(PPC::MTVRSAVEv), DestReg)
676 unsigned Reg,
int &FrameIdx)
const {
683 if (Subtarget.
isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) {
713 unsigned FIOperandNum) {
715 unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2;
717 OffsetOperandNo = FIOperandNum - 1;
720 OffsetOperandNo = FIOperandNum + 1;
722 return OffsetOperandNo;
727 int SPAdj,
unsigned FIOperandNum,
729 assert(SPAdj == 0 &&
"Unexpected");
757 if (FPSI && FrameIndex == FPSI &&
764 if (OpC == PPC::SPILL_CR) {
767 }
else if (OpC == PPC::RESTORE_CR) {
770 }
else if (OpC == PPC::SPILL_CRBIT) {
773 }
else if (OpC == PPC::RESTORE_CRBIT) {
776 }
else if (OpC == PPC::SPILL_VRSAVE) {
779 }
else if (OpC == PPC::RESTORE_VRSAVE) {
817 "This should be handled in a target-independent way");
818 if (!noImmForm && ((
isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0)) ||
836 BuildMI(MBB, II, dl, TII.
get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi)
837 .addImm(Offset >> 16);
838 BuildMI(MBB, II, dl, TII.
get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
846 unsigned OperandBase;
851 assert(ImmToIdxMap.
count(OpC) &&
852 "No indexed form of load or store available!");
853 unsigned NewOpcode = ImmToIdxMap.
find(OpC)->second;
854 MI.
setDesc(TII.get(NewOpcode));
857 OperandBase = OffsetOperandNo;
869 return TFI->
hasFP(MF) ? PPC::R31 : PPC::R1;
871 return TFI->
hasFP(MF) ? PPC::X31 : PPC::X1;
925 assert(Offset < 0 &&
"Local offset must be negative");
937 if (!ImmToIdxMap.
count(OpC))
941 if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) &&
970 unsigned BaseReg,
int FrameIdx,
971 int64_t Offset)
const {
972 unsigned ADDriOpc = TM.
isPPC64() ? PPC::ADDI8 : PPC::ADDI;
976 if (Ins != MBB->
end())
977 DL = Ins->getDebugLoc();
986 BuildMI(*MBB, Ins, DL, MCID, BaseReg)
991 int64_t Offset)
const {
992 unsigned FIOperandNum = 0;
996 "Instr doesn't have FrameIndex operand!");
1011 TII.getRegClass(MCID, FIOperandNum,
this, MF));
1016 int64_t Offset)
const {
1017 unsigned FIOperandNum = 0;
1020 assert(FIOperandNum < MI->getNumOperands() &&
1021 "Instr doesn't have FrameIndex operand!");
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
BitVector getReservedRegs(const MachineFunction &MF) const override
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const override
Alignment of stack for function (3 bits) stored as log2 of alignment with +1 bias 0 means unaligned (...
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
Returns true if the instruction's frame index reference would be better served by a base register oth...
Describe properties that are true of each instruction in the target description file.
The following two target-specific nodes are used for calls through function pointers in the 64-bit SV...
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
bool hasInlineAsm() const
Returns true if the function contains any inline assembly.
A Stackmap instruction captures the location of live variables at its position in the instruction str...
unsigned getID() const
getID() - Return the register class ID number.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
const_iterator begin(StringRef path)
Get begin iterator over path.
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
void lowerVRSAVERestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
const MCPhysReg * iterator
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
DILocation * get() const
Get the underlying DILocation.
const HexagonInstrInfo * TII
static unsigned getOffsetONFromFION(const MachineInstr &MI, unsigned FIOperandNum)
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
unsigned getFrameRegister(const MachineFunction &MF) const override
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
void lowerVRSAVESpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
void lowerCRRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
int getFramePointerSaveIndex() const
void adjustStackMapLiveOutMask(uint32_t *Mask) const override
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
unsigned getKillRegState(bool B)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
const MachineBasicBlock * getParent() const
TargetInstrInfo - Interface to description of machine instruction set.
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
DBG_VALUE - a mapping of the llvm.dbg.value intrinsic.
IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const override
Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx at the beginning of the basic ...
bundle_iterator< MachineInstr, instr_iterator > iterator
initializer< Ty > init(const Ty &Val)
Patchable call instruction - this instruction represents a call to a constant address, followed by a series of NOPs.
unsigned getBaseRegister(const MachineFunction &MF) const
static bool is64Bit(const char *name)
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const MachineOperand & getOperand(unsigned i) const
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
PPCTargetMachine - Common code between 32-bit and 64-bit PowerPC targets.
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override
PPCRegisterInfo(const PPCTargetMachine &TM)
static unsigned getCRFromCRBit(unsigned SrcReg)
bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
void lowerDynamicAlloc(MachineBasicBlock::iterator II) const
lowerDynamicAlloc - Generate the code for allocating an object in the current frame.
const uint32_t * getNoPreservedMask() const
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
static cl::opt< bool > AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(false), cl::desc("Force the use of a base pointer in every function"))
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
static bool usesIXAddr(const MachineInstr &MI)
const PPCInstrInfo * getInstrInfo() const override
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call...
bool isAllocatable(unsigned PhysReg) const
isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn't been...
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
unsigned determineFrameLayout(MachineFunction &MF, bool UpdateMF=true, bool UseEstimate=false) const
determineFrameLayout - Determine the size of the frame and maximum call frame size.
const MachineInstrBuilder & addFrameIndex(int Idx) const
size_type count(const KeyT &Val) const
Return 1 if the specified key is in the map, 0 otherwise.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
void lowerCRBitRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
KILL - This instruction is a noop that is used only to adjust the liveness of registers.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
getPointerRegClass - Return the register class to use to hold pointers.
iterator find(const KeyT &Val)
bool canRealignStack(const MachineFunction &MF) const
bool isInt< 16 >(int64_t x)
void lowerCRSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
lowerCRSpilling - Generate the code for spilling a CR register.
bool needsStackRealignment(const MachineFunction &MF) const override
unsigned getReg() const
getReg - Returns the register number.
const ARM::ArchExtKind Kind
void lowerCRBitSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
static cl::opt< bool > EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(true), cl::desc("Enable use of a base pointer for complex stack frames"))
int getCRSpillFrameIndex() const
bool usesTOCBasePtr() const
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
bool hasBasePointer(const MachineFunction &MF) const
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
getLargestLegalSuperClass - Returns the largest super class of RC that is legal to use in the current...
bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, int &FrameIdx) const override