24 iterator_range<MCInst::const_iterator>
49 exOp.
setImm((Bits & 0x3f) << Shift);
56 assert((iClass <= 0xf) &&
"iClass must have range of 0 to 0xf");
58 duplexInst->
setOpcode(Hexagon::DuplexIClass0 + iClass);
145 return ~(-1U << (bits - 1));
147 return ~(-1U << bits);
160 return -1U << (bits - 1);
198 return Hexagon::ArchV4;
200 return Hexagon::ArchV5;
226 auto MI =
I.getInst();
265 return ((Reg >= Hexagon::D0 && Reg <= Hexagon::D3) ||
266 (Reg >= Hexagon::D8 && Reg <= Hexagon::D11));
305 assert(MO.
isImm() &&
"Extendable operand must be Immediate type");
307 int ImmValue = MO.
getImm();
308 return (ImmValue < MinValue || ImmValue > MaxValue);
330 return (Op == Hexagon::A4_ext_b || Op == Hexagon::A4_ext_c ||
331 Op == Hexagon::A4_ext_g || Op == Hexagon::A4_ext);
341 return (Reg >= Hexagon::R0 && Reg <= Hexagon::R31);
345 return ((Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
346 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23));
359 unsigned short OperandNum) {
385 return (Reg >= Hexagon::P0 && Reg <= Hexagon::P3_0);
425 switch (SchedClass) {
426 case Hexagon::Sched::ALU32_3op_tc_2_SLOT0123:
427 case Hexagon::Sched::ALU64_tc_2_SLOT23:
428 case Hexagon::Sched::ALU64_tc_3x_SLOT23:
429 case Hexagon::Sched::M_tc_2_SLOT23:
430 case Hexagon::Sched::M_tc_3x_SLOT23:
431 case Hexagon::Sched::S_2op_tc_2_SLOT23:
432 case Hexagon::Sched::S_3op_tc_2_SLOT23:
433 case Hexagon::Sched::S_3op_tc_3x_SLOT23:
448 assert(Duplex !=
nullptr);
bool isSoloAin1(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn can be packaged only with an A-type insn in slot #1.
#define HEXAGON_PACKET_INNER_SIZE
bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned short getNewValueOp(MCInstrInfo const &MCII, MCInst const &MCI)
MCInst const * extenderForIndex(MCInst const &MCB, size_t Index)
unsigned getBitCount(MCInstrInfo const &MCII, MCInst const &MCI)
void padEndloop(MCInst &MCI)
void clampExtended(MCInstrInfo const &MCII, MCInst &MCI)
void setInst(const MCInst *Val)
Describe properties that are true of each instruction in the target description file.
bool isIntRegForSubInst(unsigned Reg)
bool isBundle(MCInst const &MCI)
bool isSolo(MCInstrInfo const &MCII, MCInst const &MCI)
bool isDblRegForSubInst(unsigned Reg)
bool isOuterLoop(MCInst const &MCI)
bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
void setInnerLoop(MCInst &MCI)
bool isImmext(MCInst const &MCI)
MCInst const & instruction(MCInst const &MCB, size_t Index)
#define HEXAGON_PACKET_SIZE
Reg
All possible values of the reg field in the ModR/M byte.
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget's CPU.
void replaceDuplex(MCContext &Context, MCInst &MCB, DuplexCandidate Candidate)
Context object for machine code objects.
bool isOperandExtended(MCInstrInfo const &MCII, MCInst const &MCI, unsigned short OperandNum)
int getMaxValue(MCInstrInfo const &MCII, MCInst const &MCI)
const InstrItinerary * InstrItineraries
Instances of this class represent a single low-level machine instruction.
bool isPrefix(MCInstrInfo const &MCII, MCInst const &MCI)
int getMinValue(MCInstrInfo const &MCII, MCInst const &MCI)
char const * getName(MCInstrInfo const &MCII, MCInst const &MCI)
const char * getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
Interface to description of machine instruction set.
int64_t const outerLoopMask
void setOuterLoop(MCInst &MCI)
iterator_range< MCInst::const_iterator > bundleInstructions(MCInst const &MCI)
bool prefersSlot3(MCInstrInfo const &MCII, MCInst const &MCI)
bool isCanon(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI)
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
void setOpcode(unsigned Op)
size_t const bundleInstructionsOffset
bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)
HexagonII::MemAccessSize getAccessSize(MCInstrInfo const &MCII, MCInst const &MCI)
BUNDLE - This instruction represents an instruction bundle.
A range adaptor for a pair of iterators.
unsigned getOpcode() const
Target - Wrapper for Target specific information.
bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI)
bool isExtended(MCInstrInfo const &MCII, MCInst const &MCI)
#define HEXAGON_PACKET_OUTER_SIZE
static MCOperand createInst(const MCInst *Val)
MCInst deriveSubInst(MCInst const &Inst)
bool isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn can be packaged only with A and X-type insns.
unsigned getSchedClass() const
Return the scheduling class for this instruction.
bool hasExtenderForIndex(MCInst const &MCB, size_t Index)
MCSubtargetInfo - Generic base class for all target subtargets.
const InstrStage HexagonStages[]
const MCInst * getInst() const
MCInstrDesc const & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
size_t bundleSize(MCInst const &MCI)
int getSubTarget(MCInstrInfo const &MCII, MCInst const &MCI)
bool hasImmExt(MCInst const &MCI)
bool isInnerLoop(MCInst const &MCI)
bool isFloat(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether it is a floating-point insn.
An itinerary represents the scheduling information for an instruction.
bool isPredReg(unsigned Reg)
unsigned getUnits(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Return the slots used by the insn.
bool isConstExtended(MCInstrInfo const &MCII, MCInst const &MCI)
bool isIntReg(unsigned Reg)
void addOperand(const MCOperand &Op)
MCInst * deriveDuplex(MCContext &Context, unsigned iClass, MCInst const &inst0, MCInst const &inst1)
bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI)
int64_t const innerLoopMask
unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned short getCExtOpNum(MCInstrInfo const &MCII, MCInst const &MCI)
Instances of this class represent operands of the MCInst class.
bool isPredicatedTrue(MCInstrInfo const &MCII, MCInst const &MCI)
MCOperand const & getExtendableOperand(MCInstrInfo const &MCII, MCInst const &MCI)
const MCOperand & getOperand(unsigned i) const
MCOperand const & getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI)