LLVM  3.7.0
MachineVerifier.cpp
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1 //===-- MachineVerifier.cpp - Machine Code Verifier -----------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Pass to verify generated machine code. The following is checked:
11 //
12 // Operand counts: All explicit operands must be present.
13 //
14 // Register classes: All physical and virtual register operands must be
15 // compatible with the register class required by the instruction descriptor.
16 //
17 // Register live intervals: Registers must be defined only once, and must be
18 // defined before use.
19 //
20 // The machine code verifier is enabled from LLVMTargetMachine.cpp with the
21 // command-line option -verify-machineinstrs, or by defining the environment
22 // variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
23 // the verifier errors.
24 //===----------------------------------------------------------------------===//
25 
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/ADT/DenseSet.h"
29 #include "llvm/ADT/SetOperations.h"
30 #include "llvm/ADT/SmallVector.h"
38 #include "llvm/IR/BasicBlock.h"
39 #include "llvm/IR/InlineAsm.h"
40 #include "llvm/IR/Instructions.h"
41 #include "llvm/MC/MCAsmInfo.h"
42 #include "llvm/Support/Debug.h"
45 #include "llvm/Support/Format.h"
51 using namespace llvm;
52 
53 namespace {
54  struct MachineVerifier {
55 
56  MachineVerifier(Pass *pass, const char *b) :
57  PASS(pass),
58  Banner(b)
59  {}
60 
61  bool runOnMachineFunction(MachineFunction &MF);
62 
63  Pass *const PASS;
64  const char *Banner;
65  const MachineFunction *MF;
66  const TargetMachine *TM;
67  const TargetInstrInfo *TII;
68  const TargetRegisterInfo *TRI;
69  const MachineRegisterInfo *MRI;
70 
71  unsigned foundErrors;
72 
73  typedef SmallVector<unsigned, 16> RegVector;
74  typedef SmallVector<const uint32_t*, 4> RegMaskVector;
75  typedef DenseSet<unsigned> RegSet;
78 
79  const MachineInstr *FirstTerminator;
80  BlockSet FunctionBlocks;
81 
82  BitVector regsReserved;
83  RegSet regsLive;
84  RegVector regsDefined, regsDead, regsKilled;
85  RegMaskVector regMasks;
86  RegSet regsLiveInButUnused;
87 
88  SlotIndex lastIndex;
89 
90  // Add Reg and any sub-registers to RV
91  void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
92  RV.push_back(Reg);
94  for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
95  RV.push_back(*SubRegs);
96  }
97 
98  struct BBInfo {
99  // Is this MBB reachable from the MF entry point?
100  bool reachable;
101 
102  // Vregs that must be live in because they are used without being
103  // defined. Map value is the user.
104  RegMap vregsLiveIn;
105 
106  // Regs killed in MBB. They may be defined again, and will then be in both
107  // regsKilled and regsLiveOut.
108  RegSet regsKilled;
109 
110  // Regs defined in MBB and live out. Note that vregs passing through may
111  // be live out without being mentioned here.
112  RegSet regsLiveOut;
113 
114  // Vregs that pass through MBB untouched. This set is disjoint from
115  // regsKilled and regsLiveOut.
116  RegSet vregsPassed;
117 
118  // Vregs that must pass through MBB because they are needed by a successor
119  // block. This set is disjoint from regsLiveOut.
120  RegSet vregsRequired;
121 
122  // Set versions of block's predecessor and successor lists.
123  BlockSet Preds, Succs;
124 
125  BBInfo() : reachable(false) {}
126 
127  // Add register to vregsPassed if it belongs there. Return true if
128  // anything changed.
129  bool addPassed(unsigned Reg) {
131  return false;
132  if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
133  return false;
134  return vregsPassed.insert(Reg).second;
135  }
136 
137  // Same for a full set.
138  bool addPassed(const RegSet &RS) {
139  bool changed = false;
140  for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
141  if (addPassed(*I))
142  changed = true;
143  return changed;
144  }
145 
146  // Add register to vregsRequired if it belongs there. Return true if
147  // anything changed.
148  bool addRequired(unsigned Reg) {
150  return false;
151  if (regsLiveOut.count(Reg))
152  return false;
153  return vregsRequired.insert(Reg).second;
154  }
155 
156  // Same for a full set.
157  bool addRequired(const RegSet &RS) {
158  bool changed = false;
159  for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
160  if (addRequired(*I))
161  changed = true;
162  return changed;
163  }
164 
165  // Same for a full map.
166  bool addRequired(const RegMap &RM) {
167  bool changed = false;
168  for (RegMap::const_iterator I = RM.begin(), E = RM.end(); I != E; ++I)
169  if (addRequired(I->first))
170  changed = true;
171  return changed;
172  }
173 
174  // Live-out registers are either in regsLiveOut or vregsPassed.
175  bool isLiveOut(unsigned Reg) const {
176  return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
177  }
178  };
179 
180  // Extra register info per MBB.
182 
183  bool isReserved(unsigned Reg) {
184  return Reg < regsReserved.size() && regsReserved.test(Reg);
185  }
186 
187  bool isAllocatable(unsigned Reg) {
188  return Reg < TRI->getNumRegs() && MRI->isAllocatable(Reg);
189  }
190 
191  // Analysis information if available
192  LiveVariables *LiveVars;
193  LiveIntervals *LiveInts;
194  LiveStacks *LiveStks;
195  SlotIndexes *Indexes;
196 
197  void visitMachineFunctionBefore();
198  void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
199  void visitMachineBundleBefore(const MachineInstr *MI);
200  void visitMachineInstrBefore(const MachineInstr *MI);
201  void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
202  void visitMachineInstrAfter(const MachineInstr *MI);
203  void visitMachineBundleAfter(const MachineInstr *MI);
204  void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
205  void visitMachineFunctionAfter();
206 
207  void report(const char *msg, const MachineFunction *MF);
208  void report(const char *msg, const MachineBasicBlock *MBB);
209  void report(const char *msg, const MachineInstr *MI);
210  void report(const char *msg, const MachineOperand *MO, unsigned MONum);
211  void report(const char *msg, const MachineFunction *MF,
212  const LiveInterval &LI);
213  void report(const char *msg, const MachineBasicBlock *MBB,
214  const LiveInterval &LI);
215  void report(const char *msg, const MachineFunction *MF,
216  const LiveRange &LR, unsigned Reg, unsigned LaneMask);
217  void report(const char *msg, const MachineBasicBlock *MBB,
218  const LiveRange &LR, unsigned Reg, unsigned LaneMask);
219 
220  void verifyInlineAsm(const MachineInstr *MI);
221 
222  void checkLiveness(const MachineOperand *MO, unsigned MONum);
223  void markReachable(const MachineBasicBlock *MBB);
224  void calcRegsPassed();
225  void checkPHIOps(const MachineBasicBlock *MBB);
226 
227  void calcRegsRequired();
228  void verifyLiveVariables();
229  void verifyLiveIntervals();
230  void verifyLiveInterval(const LiveInterval&);
231  void verifyLiveRangeValue(const LiveRange&, const VNInfo*, unsigned,
232  unsigned);
233  void verifyLiveRangeSegment(const LiveRange&,
234  const LiveRange::const_iterator I, unsigned,
235  unsigned);
236  void verifyLiveRange(const LiveRange&, unsigned, unsigned LaneMask = 0);
237 
238  void verifyStackFrame();
239  };
240 
241  struct MachineVerifierPass : public MachineFunctionPass {
242  static char ID; // Pass ID, replacement for typeid
243  const std::string Banner;
244 
245  MachineVerifierPass(const std::string &banner = nullptr)
246  : MachineFunctionPass(ID), Banner(banner) {
248  }
249 
250  void getAnalysisUsage(AnalysisUsage &AU) const override {
251  AU.setPreservesAll();
253  }
254 
255  bool runOnMachineFunction(MachineFunction &MF) override {
256  MF.verify(this, Banner.c_str());
257  return false;
258  }
259  };
260 
261 }
262 
263 char MachineVerifierPass::ID = 0;
264 INITIALIZE_PASS(MachineVerifierPass, "machineverifier",
265  "Verify generated machine code", false, false)
266 
267 FunctionPass *llvm::createMachineVerifierPass(const std::string &Banner) {
268  return new MachineVerifierPass(Banner);
269 }
270 
271 void MachineFunction::verify(Pass *p, const char *Banner) const {
272  MachineVerifier(p, Banner)
273  .runOnMachineFunction(const_cast<MachineFunction&>(*this));
274 }
275 
276 bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) {
277  foundErrors = 0;
278 
279  this->MF = &MF;
280  TM = &MF.getTarget();
281  TII = MF.getSubtarget().getInstrInfo();
282  TRI = MF.getSubtarget().getRegisterInfo();
283  MRI = &MF.getRegInfo();
284 
285  LiveVars = nullptr;
286  LiveInts = nullptr;
287  LiveStks = nullptr;
288  Indexes = nullptr;
289  if (PASS) {
290  LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>();
291  // We don't want to verify LiveVariables if LiveIntervals is available.
292  if (!LiveInts)
293  LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
294  LiveStks = PASS->getAnalysisIfAvailable<LiveStacks>();
295  Indexes = PASS->getAnalysisIfAvailable<SlotIndexes>();
296  }
297 
298  visitMachineFunctionBefore();
299  for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
300  MFI!=MFE; ++MFI) {
301  visitMachineBasicBlockBefore(MFI);
302  // Keep track of the current bundle header.
303  const MachineInstr *CurBundle = nullptr;
304  // Do we expect the next instruction to be part of the same bundle?
305  bool InBundle = false;
306 
307  for (MachineBasicBlock::const_instr_iterator MBBI = MFI->instr_begin(),
308  MBBE = MFI->instr_end(); MBBI != MBBE; ++MBBI) {
309  if (MBBI->getParent() != MFI) {
310  report("Bad instruction parent pointer", MFI);
311  errs() << "Instruction: " << *MBBI;
312  continue;
313  }
314 
315  // Check for consistent bundle flags.
316  if (InBundle && !MBBI->isBundledWithPred())
317  report("Missing BundledPred flag, "
318  "BundledSucc was set on predecessor", MBBI);
319  if (!InBundle && MBBI->isBundledWithPred())
320  report("BundledPred flag is set, "
321  "but BundledSucc not set on predecessor", MBBI);
322 
323  // Is this a bundle header?
324  if (!MBBI->isInsideBundle()) {
325  if (CurBundle)
326  visitMachineBundleAfter(CurBundle);
327  CurBundle = MBBI;
328  visitMachineBundleBefore(CurBundle);
329  } else if (!CurBundle)
330  report("No bundle header", MBBI);
331  visitMachineInstrBefore(MBBI);
332  for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
333  const MachineInstr &MI = *MBBI;
334  const MachineOperand &Op = MI.getOperand(I);
335  if (Op.getParent() != &MI) {
336  // Make sure to use correct addOperand / RemoveOperand / ChangeTo
337  // functions when replacing operands of a MachineInstr.
338  report("Instruction has operand with wrong parent set", &MI);
339  }
340 
341  visitMachineOperand(&Op, I);
342  }
343 
344  visitMachineInstrAfter(MBBI);
345 
346  // Was this the last bundled instruction?
347  InBundle = MBBI->isBundledWithSucc();
348  }
349  if (CurBundle)
350  visitMachineBundleAfter(CurBundle);
351  if (InBundle)
352  report("BundledSucc flag set on last instruction in block", &MFI->back());
353  visitMachineBasicBlockAfter(MFI);
354  }
355  visitMachineFunctionAfter();
356 
357  if (foundErrors)
358  report_fatal_error("Found "+Twine(foundErrors)+" machine code errors.");
359 
360  // Clean up.
361  regsLive.clear();
362  regsDefined.clear();
363  regsDead.clear();
364  regsKilled.clear();
365  regMasks.clear();
366  regsLiveInButUnused.clear();
367  MBBInfoMap.clear();
368 
369  return false; // no changes
370 }
371 
372 void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
373  assert(MF);
374  errs() << '\n';
375  if (!foundErrors++) {
376  if (Banner)
377  errs() << "# " << Banner << '\n';
378  MF->print(errs(), Indexes);
379  }
380  errs() << "*** Bad machine code: " << msg << " ***\n"
381  << "- function: " << MF->getName() << "\n";
382 }
383 
384 void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
385  assert(MBB);
386  report(msg, MBB->getParent());
387  errs() << "- basic block: BB#" << MBB->getNumber()
388  << ' ' << MBB->getName()
389  << " (" << (const void*)MBB << ')';
390  if (Indexes)
391  errs() << " [" << Indexes->getMBBStartIdx(MBB)
392  << ';' << Indexes->getMBBEndIdx(MBB) << ')';
393  errs() << '\n';
394 }
395 
396 void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
397  assert(MI);
398  report(msg, MI->getParent());
399  errs() << "- instruction: ";
400  if (Indexes && Indexes->hasIndex(MI))
401  errs() << Indexes->getInstructionIndex(MI) << '\t';
402  MI->print(errs(), TM);
403 }
404 
405 void MachineVerifier::report(const char *msg,
406  const MachineOperand *MO, unsigned MONum) {
407  assert(MO);
408  report(msg, MO->getParent());
409  errs() << "- operand " << MONum << ": ";
410  MO->print(errs(), TRI);
411  errs() << "\n";
412 }
413 
414 void MachineVerifier::report(const char *msg, const MachineFunction *MF,
415  const LiveInterval &LI) {
416  report(msg, MF);
417  errs() << "- interval: " << LI << '\n';
418 }
419 
420 void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB,
421  const LiveInterval &LI) {
422  report(msg, MBB);
423  errs() << "- interval: " << LI << '\n';
424 }
425 
426 void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB,
427  const LiveRange &LR, unsigned Reg,
428  unsigned LaneMask) {
429  report(msg, MBB);
430  errs() << "- liverange: " << LR << '\n';
431  errs() << "- register: " << PrintReg(Reg, TRI) << '\n';
432  if (LaneMask != 0)
433  errs() << "- lanemask: " << format("%04X\n", LaneMask);
434 }
435 
436 void MachineVerifier::report(const char *msg, const MachineFunction *MF,
437  const LiveRange &LR, unsigned Reg,
438  unsigned LaneMask) {
439  report(msg, MF);
440  errs() << "- liverange: " << LR << '\n';
441  errs() << "- register: " << PrintReg(Reg, TRI) << '\n';
442  if (LaneMask != 0)
443  errs() << "- lanemask: " << format("%04X\n", LaneMask);
444 }
445 
446 void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
447  BBInfo &MInfo = MBBInfoMap[MBB];
448  if (!MInfo.reachable) {
449  MInfo.reachable = true;
451  SuE = MBB->succ_end(); SuI != SuE; ++SuI)
452  markReachable(*SuI);
453  }
454 }
455 
456 void MachineVerifier::visitMachineFunctionBefore() {
457  lastIndex = SlotIndex();
458  regsReserved = MRI->getReservedRegs();
459 
460  // A sub-register of a reserved register is also reserved
461  for (int Reg = regsReserved.find_first(); Reg>=0;
462  Reg = regsReserved.find_next(Reg)) {
463  for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
464  // FIXME: This should probably be:
465  // assert(regsReserved.test(*SubRegs) && "Non-reserved sub-register");
466  regsReserved.set(*SubRegs);
467  }
468  }
469 
470  markReachable(&MF->front());
471 
472  // Build a set of the basic blocks in the function.
473  FunctionBlocks.clear();
474  for (const auto &MBB : *MF) {
475  FunctionBlocks.insert(&MBB);
476  BBInfo &MInfo = MBBInfoMap[&MBB];
477 
478  MInfo.Preds.insert(MBB.pred_begin(), MBB.pred_end());
479  if (MInfo.Preds.size() != MBB.pred_size())
480  report("MBB has duplicate entries in its predecessor list.", &MBB);
481 
482  MInfo.Succs.insert(MBB.succ_begin(), MBB.succ_end());
483  if (MInfo.Succs.size() != MBB.succ_size())
484  report("MBB has duplicate entries in its successor list.", &MBB);
485  }
486 
487  // Check that the register use lists are sane.
488  MRI->verifyUseLists();
489 
490  verifyStackFrame();
491 }
492 
493 // Does iterator point to a and b as the first two elements?
495  const MachineBasicBlock *a, const MachineBasicBlock *b) {
496  if (*i == a)
497  return *++i == b;
498  if (*i == b)
499  return *++i == a;
500  return false;
501 }
502 
503 void
504 MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
505  FirstTerminator = nullptr;
506 
507  if (MRI->isSSA()) {
508  // If this block has allocatable physical registers live-in, check that
509  // it is an entry block or landing pad.
511  LE = MBB->livein_end();
512  LI != LE; ++LI) {
513  unsigned reg = *LI;
514  if (isAllocatable(reg) && !MBB->isLandingPad() &&
515  MBB != MBB->getParent()->begin()) {
516  report("MBB has allocable live-in, but isn't entry or landing-pad.", MBB);
517  }
518  }
519  }
520 
521  // Count the number of landing pad successors.
522  SmallPtrSet<MachineBasicBlock*, 4> LandingPadSuccs;
524  E = MBB->succ_end(); I != E; ++I) {
525  if ((*I)->isLandingPad())
526  LandingPadSuccs.insert(*I);
527  if (!FunctionBlocks.count(*I))
528  report("MBB has successor that isn't part of the function.", MBB);
529  if (!MBBInfoMap[*I].Preds.count(MBB)) {
530  report("Inconsistent CFG", MBB);
531  errs() << "MBB is not in the predecessor list of the successor BB#"
532  << (*I)->getNumber() << ".\n";
533  }
534  }
535 
536  // Check the predecessor list.
538  E = MBB->pred_end(); I != E; ++I) {
539  if (!FunctionBlocks.count(*I))
540  report("MBB has predecessor that isn't part of the function.", MBB);
541  if (!MBBInfoMap[*I].Succs.count(MBB)) {
542  report("Inconsistent CFG", MBB);
543  errs() << "MBB is not in the successor list of the predecessor BB#"
544  << (*I)->getNumber() << ".\n";
545  }
546  }
547 
548  const MCAsmInfo *AsmInfo = TM->getMCAsmInfo();
549  const BasicBlock *BB = MBB->getBasicBlock();
550  if (LandingPadSuccs.size() > 1 &&
551  !(AsmInfo &&
553  BB && isa<SwitchInst>(BB->getTerminator())))
554  report("MBB has more than one landing pad successor", MBB);
555 
556  // Call AnalyzeBranch. If it succeeds, there several more conditions to check.
557  MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
559  if (!TII->AnalyzeBranch(*const_cast<MachineBasicBlock *>(MBB),
560  TBB, FBB, Cond)) {
561  // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's
562  // check whether its answers match up with reality.
563  if (!TBB && !FBB) {
564  // Block falls through to its successor.
566  ++MBBI;
567  if (MBBI == MF->end()) {
568  // It's possible that the block legitimately ends with a noreturn
569  // call or an unreachable, in which case it won't actually fall
570  // out the bottom of the function.
571  } else if (MBB->succ_size() == LandingPadSuccs.size()) {
572  // It's possible that the block legitimately ends with a noreturn
573  // call or an unreachable, in which case it won't actuall fall
574  // out of the block.
575  } else if (MBB->succ_size() != 1+LandingPadSuccs.size()) {
576  report("MBB exits via unconditional fall-through but doesn't have "
577  "exactly one CFG successor!", MBB);
578  } else if (!MBB->isSuccessor(MBBI)) {
579  report("MBB exits via unconditional fall-through but its successor "
580  "differs from its CFG successor!", MBB);
581  }
582  if (!MBB->empty() && MBB->back().isBarrier() &&
583  !TII->isPredicated(&MBB->back())) {
584  report("MBB exits via unconditional fall-through but ends with a "
585  "barrier instruction!", MBB);
586  }
587  if (!Cond.empty()) {
588  report("MBB exits via unconditional fall-through but has a condition!",
589  MBB);
590  }
591  } else if (TBB && !FBB && Cond.empty()) {
592  // Block unconditionally branches somewhere.
593  // If the block has exactly one successor, that happens to be a
594  // landingpad, accept it as valid control flow.
595  if (MBB->succ_size() != 1+LandingPadSuccs.size() &&
596  (MBB->succ_size() != 1 || LandingPadSuccs.size() != 1 ||
597  *MBB->succ_begin() != *LandingPadSuccs.begin())) {
598  report("MBB exits via unconditional branch but doesn't have "
599  "exactly one CFG successor!", MBB);
600  } else if (!MBB->isSuccessor(TBB)) {
601  report("MBB exits via unconditional branch but the CFG "
602  "successor doesn't match the actual successor!", MBB);
603  }
604  if (MBB->empty()) {
605  report("MBB exits via unconditional branch but doesn't contain "
606  "any instructions!", MBB);
607  } else if (!MBB->back().isBarrier()) {
608  report("MBB exits via unconditional branch but doesn't end with a "
609  "barrier instruction!", MBB);
610  } else if (!MBB->back().isTerminator()) {
611  report("MBB exits via unconditional branch but the branch isn't a "
612  "terminator instruction!", MBB);
613  }
614  } else if (TBB && !FBB && !Cond.empty()) {
615  // Block conditionally branches somewhere, otherwise falls through.
617  ++MBBI;
618  if (MBBI == MF->end()) {
619  report("MBB conditionally falls through out of function!", MBB);
620  } else if (MBB->succ_size() == 1) {
621  // A conditional branch with only one successor is weird, but allowed.
622  if (&*MBBI != TBB)
623  report("MBB exits via conditional branch/fall-through but only has "
624  "one CFG successor!", MBB);
625  else if (TBB != *MBB->succ_begin())
626  report("MBB exits via conditional branch/fall-through but the CFG "
627  "successor don't match the actual successor!", MBB);
628  } else if (MBB->succ_size() != 2) {
629  report("MBB exits via conditional branch/fall-through but doesn't have "
630  "exactly two CFG successors!", MBB);
631  } else if (!matchPair(MBB->succ_begin(), TBB, MBBI)) {
632  report("MBB exits via conditional branch/fall-through but the CFG "
633  "successors don't match the actual successors!", MBB);
634  }
635  if (MBB->empty()) {
636  report("MBB exits via conditional branch/fall-through but doesn't "
637  "contain any instructions!", MBB);
638  } else if (MBB->back().isBarrier()) {
639  report("MBB exits via conditional branch/fall-through but ends with a "
640  "barrier instruction!", MBB);
641  } else if (!MBB->back().isTerminator()) {
642  report("MBB exits via conditional branch/fall-through but the branch "
643  "isn't a terminator instruction!", MBB);
644  }
645  } else if (TBB && FBB) {
646  // Block conditionally branches somewhere, otherwise branches
647  // somewhere else.
648  if (MBB->succ_size() == 1) {
649  // A conditional branch with only one successor is weird, but allowed.
650  if (FBB != TBB)
651  report("MBB exits via conditional branch/branch through but only has "
652  "one CFG successor!", MBB);
653  else if (TBB != *MBB->succ_begin())
654  report("MBB exits via conditional branch/branch through but the CFG "
655  "successor don't match the actual successor!", MBB);
656  } else if (MBB->succ_size() != 2) {
657  report("MBB exits via conditional branch/branch but doesn't have "
658  "exactly two CFG successors!", MBB);
659  } else if (!matchPair(MBB->succ_begin(), TBB, FBB)) {
660  report("MBB exits via conditional branch/branch but the CFG "
661  "successors don't match the actual successors!", MBB);
662  }
663  if (MBB->empty()) {
664  report("MBB exits via conditional branch/branch but doesn't "
665  "contain any instructions!", MBB);
666  } else if (!MBB->back().isBarrier()) {
667  report("MBB exits via conditional branch/branch but doesn't end with a "
668  "barrier instruction!", MBB);
669  } else if (!MBB->back().isTerminator()) {
670  report("MBB exits via conditional branch/branch but the branch "
671  "isn't a terminator instruction!", MBB);
672  }
673  if (Cond.empty()) {
674  report("MBB exits via conditinal branch/branch but there's no "
675  "condition!", MBB);
676  }
677  } else {
678  report("AnalyzeBranch returned invalid data!", MBB);
679  }
680  }
681 
682  regsLive.clear();
684  E = MBB->livein_end(); I != E; ++I) {
686  report("MBB live-in list contains non-physical register", MBB);
687  continue;
688  }
689  for (MCSubRegIterator SubRegs(*I, TRI, /*IncludeSelf=*/true);
690  SubRegs.isValid(); ++SubRegs)
691  regsLive.insert(*SubRegs);
692  }
693  regsLiveInButUnused = regsLive;
694 
695  const MachineFrameInfo *MFI = MF->getFrameInfo();
696  assert(MFI && "Function has no frame info");
697  BitVector PR = MFI->getPristineRegs(*MF);
698  for (int I = PR.find_first(); I>0; I = PR.find_next(I)) {
699  for (MCSubRegIterator SubRegs(I, TRI, /*IncludeSelf=*/true);
700  SubRegs.isValid(); ++SubRegs)
701  regsLive.insert(*SubRegs);
702  }
703 
704  regsKilled.clear();
705  regsDefined.clear();
706 
707  if (Indexes)
708  lastIndex = Indexes->getMBBStartIdx(MBB);
709 }
710 
711 // This function gets called for all bundle headers, including normal
712 // stand-alone unbundled instructions.
713 void MachineVerifier::visitMachineBundleBefore(const MachineInstr *MI) {
714  if (Indexes && Indexes->hasIndex(MI)) {
715  SlotIndex idx = Indexes->getInstructionIndex(MI);
716  if (!(idx > lastIndex)) {
717  report("Instruction index out of order", MI);
718  errs() << "Last instruction was at " << lastIndex << '\n';
719  }
720  lastIndex = idx;
721  }
722 
723  // Ensure non-terminators don't follow terminators.
724  // Ignore predicated terminators formed by if conversion.
725  // FIXME: If conversion shouldn't need to violate this rule.
726  if (MI->isTerminator() && !TII->isPredicated(MI)) {
727  if (!FirstTerminator)
728  FirstTerminator = MI;
729  } else if (FirstTerminator) {
730  report("Non-terminator instruction after the first terminator", MI);
731  errs() << "First terminator was:\t" << *FirstTerminator;
732  }
733 }
734 
735 // The operands on an INLINEASM instruction must follow a template.
736 // Verify that the flag operands make sense.
737 void MachineVerifier::verifyInlineAsm(const MachineInstr *MI) {
738  // The first two operands on INLINEASM are the asm string and global flags.
739  if (MI->getNumOperands() < 2) {
740  report("Too few operands on inline asm", MI);
741  return;
742  }
743  if (!MI->getOperand(0).isSymbol())
744  report("Asm string must be an external symbol", MI);
745  if (!MI->getOperand(1).isImm())
746  report("Asm flags must be an immediate", MI);
747  // Allowed flags are Extra_HasSideEffects = 1, Extra_IsAlignStack = 2,
748  // Extra_AsmDialect = 4, Extra_MayLoad = 8, and Extra_MayStore = 16.
749  if (!isUInt<5>(MI->getOperand(1).getImm()))
750  report("Unknown asm flags", &MI->getOperand(1), 1);
751 
752  static_assert(InlineAsm::MIOp_FirstOperand == 2, "Asm format changed");
753 
754  unsigned OpNo = InlineAsm::MIOp_FirstOperand;
755  unsigned NumOps;
756  for (unsigned e = MI->getNumOperands(); OpNo < e; OpNo += NumOps) {
757  const MachineOperand &MO = MI->getOperand(OpNo);
758  // There may be implicit ops after the fixed operands.
759  if (!MO.isImm())
760  break;
761  NumOps = 1 + InlineAsm::getNumOperandRegisters(MO.getImm());
762  }
763 
764  if (OpNo > MI->getNumOperands())
765  report("Missing operands in last group", MI);
766 
767  // An optional MDNode follows the groups.
768  if (OpNo < MI->getNumOperands() && MI->getOperand(OpNo).isMetadata())
769  ++OpNo;
770 
771  // All trailing operands must be implicit registers.
772  for (unsigned e = MI->getNumOperands(); OpNo < e; ++OpNo) {
773  const MachineOperand &MO = MI->getOperand(OpNo);
774  if (!MO.isReg() || !MO.isImplicit())
775  report("Expected implicit register after groups", &MO, OpNo);
776  }
777 }
778 
779 void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
780  const MCInstrDesc &MCID = MI->getDesc();
781  if (MI->getNumOperands() < MCID.getNumOperands()) {
782  report("Too few operands", MI);
783  errs() << MCID.getNumOperands() << " operands expected, but "
784  << MI->getNumOperands() << " given.\n";
785  }
786 
787  // Check the tied operands.
788  if (MI->isInlineAsm())
789  verifyInlineAsm(MI);
790 
791  // Check the MachineMemOperands for basic consistency.
793  E = MI->memoperands_end(); I != E; ++I) {
794  if ((*I)->isLoad() && !MI->mayLoad())
795  report("Missing mayLoad flag", MI);
796  if ((*I)->isStore() && !MI->mayStore())
797  report("Missing mayStore flag", MI);
798  }
799 
800  // Debug values must not have a slot index.
801  // Other instructions must have one, unless they are inside a bundle.
802  if (LiveInts) {
803  bool mapped = !LiveInts->isNotInMIMap(MI);
804  if (MI->isDebugValue()) {
805  if (mapped)
806  report("Debug instruction has a slot index", MI);
807  } else if (MI->isInsideBundle()) {
808  if (mapped)
809  report("Instruction inside bundle has a slot index", MI);
810  } else {
811  if (!mapped)
812  report("Missing slot index", MI);
813  }
814  }
815 
816  StringRef ErrorInfo;
817  if (!TII->verifyInstruction(MI, ErrorInfo))
818  report(ErrorInfo.data(), MI);
819 }
820 
821 void
822 MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
823  const MachineInstr *MI = MO->getParent();
824  const MCInstrDesc &MCID = MI->getDesc();
825 
826  // The first MCID.NumDefs operands must be explicit register defines
827  if (MONum < MCID.getNumDefs()) {
828  const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
829  if (!MO->isReg())
830  report("Explicit definition must be a register", MO, MONum);
831  else if (!MO->isDef() && !MCOI.isOptionalDef())
832  report("Explicit definition marked as use", MO, MONum);
833  else if (MO->isImplicit())
834  report("Explicit definition marked as implicit", MO, MONum);
835  } else if (MONum < MCID.getNumOperands()) {
836  const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
837  // Don't check if it's the last operand in a variadic instruction. See,
838  // e.g., LDM_RET in the arm back end.
839  if (MO->isReg() &&
840  !(MI->isVariadic() && MONum == MCID.getNumOperands()-1)) {
841  if (MO->isDef() && !MCOI.isOptionalDef())
842  report("Explicit operand marked as def", MO, MONum);
843  if (MO->isImplicit())
844  report("Explicit operand marked as implicit", MO, MONum);
845  }
846 
847  int TiedTo = MCID.getOperandConstraint(MONum, MCOI::TIED_TO);
848  if (TiedTo != -1) {
849  if (!MO->isReg())
850  report("Tied use must be a register", MO, MONum);
851  else if (!MO->isTied())
852  report("Operand should be tied", MO, MONum);
853  else if (unsigned(TiedTo) != MI->findTiedOperandIdx(MONum))
854  report("Tied def doesn't match MCInstrDesc", MO, MONum);
855  } else if (MO->isReg() && MO->isTied())
856  report("Explicit operand should not be tied", MO, MONum);
857  } else {
858  // ARM adds %reg0 operands to indicate predicates. We'll allow that.
859  if (MO->isReg() && !MO->isImplicit() && !MI->isVariadic() && MO->getReg())
860  report("Extra explicit operand on non-variadic instruction", MO, MONum);
861  }
862 
863  switch (MO->getType()) {
865  const unsigned Reg = MO->getReg();
866  if (!Reg)
867  return;
868  if (MRI->tracksLiveness() && !MI->isDebugValue())
869  checkLiveness(MO, MONum);
870 
871  // Verify the consistency of tied operands.
872  if (MO->isTied()) {
873  unsigned OtherIdx = MI->findTiedOperandIdx(MONum);
874  const MachineOperand &OtherMO = MI->getOperand(OtherIdx);
875  if (!OtherMO.isReg())
876  report("Must be tied to a register", MO, MONum);
877  if (!OtherMO.isTied())
878  report("Missing tie flags on tied operand", MO, MONum);
879  if (MI->findTiedOperandIdx(OtherIdx) != MONum)
880  report("Inconsistent tie links", MO, MONum);
881  if (MONum < MCID.getNumDefs()) {
882  if (OtherIdx < MCID.getNumOperands()) {
883  if (-1 == MCID.getOperandConstraint(OtherIdx, MCOI::TIED_TO))
884  report("Explicit def tied to explicit use without tie constraint",
885  MO, MONum);
886  } else {
887  if (!OtherMO.isImplicit())
888  report("Explicit def should be tied to implicit use", MO, MONum);
889  }
890  }
891  }
892 
893  // Verify two-address constraints after leaving SSA form.
894  unsigned DefIdx;
895  if (!MRI->isSSA() && MO->isUse() &&
896  MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
897  Reg != MI->getOperand(DefIdx).getReg())
898  report("Two-address instruction operands must be identical", MO, MONum);
899 
900  // Check register classes.
901  if (MONum < MCID.getNumOperands() && !MO->isImplicit()) {
902  unsigned SubIdx = MO->getSubReg();
903 
905  if (SubIdx) {
906  report("Illegal subregister index for physical register", MO, MONum);
907  return;
908  }
909  if (const TargetRegisterClass *DRC =
910  TII->getRegClass(MCID, MONum, TRI, *MF)) {
911  if (!DRC->contains(Reg)) {
912  report("Illegal physical register for instruction", MO, MONum);
913  errs() << TRI->getName(Reg) << " is not a "
914  << TRI->getRegClassName(DRC) << " register.\n";
915  }
916  }
917  } else {
918  // Virtual register.
919  const TargetRegisterClass *RC = MRI->getRegClass(Reg);
920  if (SubIdx) {
921  const TargetRegisterClass *SRC =
922  TRI->getSubClassWithSubReg(RC, SubIdx);
923  if (!SRC) {
924  report("Invalid subregister index for virtual register", MO, MONum);
925  errs() << "Register class " << TRI->getRegClassName(RC)
926  << " does not support subreg index " << SubIdx << "\n";
927  return;
928  }
929  if (RC != SRC) {
930  report("Invalid register class for subregister index", MO, MONum);
931  errs() << "Register class " << TRI->getRegClassName(RC)
932  << " does not fully support subreg index " << SubIdx << "\n";
933  return;
934  }
935  }
936  if (const TargetRegisterClass *DRC =
937  TII->getRegClass(MCID, MONum, TRI, *MF)) {
938  if (SubIdx) {
939  const TargetRegisterClass *SuperRC =
940  TRI->getLargestLegalSuperClass(RC, *MF);
941  if (!SuperRC) {
942  report("No largest legal super class exists.", MO, MONum);
943  return;
944  }
945  DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
946  if (!DRC) {
947  report("No matching super-reg register class.", MO, MONum);
948  return;
949  }
950  }
951  if (!RC->hasSuperClassEq(DRC)) {
952  report("Illegal virtual register for instruction", MO, MONum);
953  errs() << "Expected a " << TRI->getRegClassName(DRC)
954  << " register, but got a " << TRI->getRegClassName(RC)
955  << " register\n";
956  }
957  }
958  }
959  }
960  break;
961  }
962 
964  regMasks.push_back(MO->getRegMask());
965  break;
966 
968  if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent()))
969  report("PHI operand is not in the CFG", MO, MONum);
970  break;
971 
973  if (LiveStks && LiveStks->hasInterval(MO->getIndex()) &&
974  LiveInts && !LiveInts->isNotInMIMap(MI)) {
975  LiveInterval &LI = LiveStks->getInterval(MO->getIndex());
976  SlotIndex Idx = LiveInts->getInstructionIndex(MI);
977  if (MI->mayLoad() && !LI.liveAt(Idx.getRegSlot(true))) {
978  report("Instruction loads from dead spill slot", MO, MONum);
979  errs() << "Live stack: " << LI << '\n';
980  }
981  if (MI->mayStore() && !LI.liveAt(Idx.getRegSlot())) {
982  report("Instruction stores to dead spill slot", MO, MONum);
983  errs() << "Live stack: " << LI << '\n';
984  }
985  }
986  break;
987 
988  default:
989  break;
990  }
991 }
992 
993 void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
994  const MachineInstr *MI = MO->getParent();
995  const unsigned Reg = MO->getReg();
996 
997  // Both use and def operands can read a register.
998  if (MO->readsReg()) {
999  regsLiveInButUnused.erase(Reg);
1000 
1001  if (MO->isKill())
1002  addRegWithSubRegs(regsKilled, Reg);
1003 
1004  // Check that LiveVars knows this kill.
1005  if (LiveVars && TargetRegisterInfo::isVirtualRegister(Reg) &&
1006  MO->isKill()) {
1007  LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
1008  if (std::find(VI.Kills.begin(), VI.Kills.end(), MI) == VI.Kills.end())
1009  report("Kill missing from LiveVariables", MO, MONum);
1010  }
1011 
1012  // Check LiveInts liveness and kill.
1013  if (LiveInts && !LiveInts->isNotInMIMap(MI)) {
1014  SlotIndex UseIdx = LiveInts->getInstructionIndex(MI);
1015  // Check the cached regunit intervals.
1016  if (TargetRegisterInfo::isPhysicalRegister(Reg) && !isReserved(Reg)) {
1017  for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) {
1018  if (const LiveRange *LR = LiveInts->getCachedRegUnit(*Units)) {
1019  LiveQueryResult LRQ = LR->Query(UseIdx);
1020  if (!LRQ.valueIn()) {
1021  report("No live segment at use", MO, MONum);
1022  errs() << UseIdx << " is not live in " << PrintRegUnit(*Units, TRI)
1023  << ' ' << *LR << '\n';
1024  }
1025  if (MO->isKill() && !LRQ.isKill()) {
1026  report("Live range continues after kill flag", MO, MONum);
1027  errs() << PrintRegUnit(*Units, TRI) << ' ' << *LR << '\n';
1028  }
1029  }
1030  }
1031  }
1032 
1034  if (LiveInts->hasInterval(Reg)) {
1035  // This is a virtual register interval.
1036  const LiveInterval &LI = LiveInts->getInterval(Reg);
1037  LiveQueryResult LRQ = LI.Query(UseIdx);
1038  if (!LRQ.valueIn()) {
1039  report("No live segment at use", MO, MONum);
1040  errs() << UseIdx << " is not live in " << LI << '\n';
1041  }
1042  // Check for extra kill flags.
1043  // Note that we allow missing kill flags for now.
1044  if (MO->isKill() && !LRQ.isKill()) {
1045  report("Live range continues after kill flag", MO, MONum);
1046  errs() << "Live range: " << LI << '\n';
1047  }
1048  } else {
1049  report("Virtual register has no live interval", MO, MONum);
1050  }
1051  }
1052  }
1053 
1054  // Use of a dead register.
1055  if (!regsLive.count(Reg)) {
1057  // Reserved registers may be used even when 'dead'.
1058  bool Bad = !isReserved(Reg);
1059  // We are fine if just any subregister has a defined value.
1060  if (Bad) {
1061  for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid();
1062  ++SubRegs) {
1063  if (regsLive.count(*SubRegs)) {
1064  Bad = false;
1065  break;
1066  }
1067  }
1068  }
1069  // If there is an additional implicit-use of a super register we stop
1070  // here. By definition we are fine if the super register is not
1071  // (completely) dead, if the complete super register is dead we will
1072  // get a report for its operand.
1073  if (Bad) {
1074  for (const MachineOperand &MOP : MI->uses()) {
1075  if (!MOP.isReg())
1076  continue;
1077  if (!MOP.isImplicit())
1078  continue;
1079  for (MCSubRegIterator SubRegs(MOP.getReg(), TRI); SubRegs.isValid();
1080  ++SubRegs) {
1081  if (*SubRegs == Reg) {
1082  Bad = false;
1083  break;
1084  }
1085  }
1086  }
1087  }
1088  if (Bad)
1089  report("Using an undefined physical register", MO, MONum);
1090  } else if (MRI->def_empty(Reg)) {
1091  report("Reading virtual register without a def", MO, MONum);
1092  } else {
1093  BBInfo &MInfo = MBBInfoMap[MI->getParent()];
1094  // We don't know which virtual registers are live in, so only complain
1095  // if vreg was killed in this MBB. Otherwise keep track of vregs that
1096  // must be live in. PHI instructions are handled separately.
1097  if (MInfo.regsKilled.count(Reg))
1098  report("Using a killed virtual register", MO, MONum);
1099  else if (!MI->isPHI())
1100  MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
1101  }
1102  }
1103  }
1104 
1105  if (MO->isDef()) {
1106  // Register defined.
1107  // TODO: verify that earlyclobber ops are not used.
1108  if (MO->isDead())
1109  addRegWithSubRegs(regsDead, Reg);
1110  else
1111  addRegWithSubRegs(regsDefined, Reg);
1112 
1113  // Verify SSA form.
1114  if (MRI->isSSA() && TargetRegisterInfo::isVirtualRegister(Reg) &&
1115  std::next(MRI->def_begin(Reg)) != MRI->def_end())
1116  report("Multiple virtual register defs in SSA form", MO, MONum);
1117 
1118  // Check LiveInts for a live segment, but only for virtual registers.
1119  if (LiveInts && TargetRegisterInfo::isVirtualRegister(Reg) &&
1120  !LiveInts->isNotInMIMap(MI)) {
1121  SlotIndex DefIdx = LiveInts->getInstructionIndex(MI);
1122  DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber());
1123  if (LiveInts->hasInterval(Reg)) {
1124  const LiveInterval &LI = LiveInts->getInterval(Reg);
1125  if (const VNInfo *VNI = LI.getVNInfoAt(DefIdx)) {
1126  assert(VNI && "NULL valno is not allowed");
1127  if (VNI->def != DefIdx) {
1128  report("Inconsistent valno->def", MO, MONum);
1129  errs() << "Valno " << VNI->id << " is not defined at "
1130  << DefIdx << " in " << LI << '\n';
1131  }
1132  } else {
1133  report("No live segment at def", MO, MONum);
1134  errs() << DefIdx << " is not live in " << LI << '\n';
1135  }
1136  // Check that, if the dead def flag is present, LiveInts agree.
1137  if (MO->isDead()) {
1138  LiveQueryResult LRQ = LI.Query(DefIdx);
1139  if (!LRQ.isDeadDef()) {
1140  report("Live range continues after dead def flag", MO, MONum);
1141  errs() << "Live range: " << LI << '\n';
1142  }
1143  }
1144  } else {
1145  report("Virtual register has no Live interval", MO, MONum);
1146  }
1147  }
1148  }
1149 }
1150 
1151 void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) {
1152 }
1153 
1154 // This function gets called after visiting all instructions in a bundle. The
1155 // argument points to the bundle header.
1156 // Normal stand-alone instructions are also considered 'bundles', and this
1157 // function is called for all of them.
1158 void MachineVerifier::visitMachineBundleAfter(const MachineInstr *MI) {
1159  BBInfo &MInfo = MBBInfoMap[MI->getParent()];
1160  set_union(MInfo.regsKilled, regsKilled);
1161  set_subtract(regsLive, regsKilled); regsKilled.clear();
1162  // Kill any masked registers.
1163  while (!regMasks.empty()) {
1164  const uint32_t *Mask = regMasks.pop_back_val();
1165  for (RegSet::iterator I = regsLive.begin(), E = regsLive.end(); I != E; ++I)
1168  regsDead.push_back(*I);
1169  }
1170  set_subtract(regsLive, regsDead); regsDead.clear();
1171  set_union(regsLive, regsDefined); regsDefined.clear();
1172 }
1173 
1174 void
1175 MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
1176  MBBInfoMap[MBB].regsLiveOut = regsLive;
1177  regsLive.clear();
1178 
1179  if (Indexes) {
1180  SlotIndex stop = Indexes->getMBBEndIdx(MBB);
1181  if (!(stop > lastIndex)) {
1182  report("Block ends before last instruction index", MBB);
1183  errs() << "Block ends at " << stop
1184  << " last instruction was at " << lastIndex << '\n';
1185  }
1186  lastIndex = stop;
1187  }
1188 }
1189 
1190 // Calculate the largest possible vregsPassed sets. These are the registers that
1191 // can pass through an MBB live, but may not be live every time. It is assumed
1192 // that all vregsPassed sets are empty before the call.
1193 void MachineVerifier::calcRegsPassed() {
1194  // First push live-out regs to successors' vregsPassed. Remember the MBBs that
1195  // have any vregsPassed.
1197  for (const auto &MBB : *MF) {
1198  BBInfo &MInfo = MBBInfoMap[&MBB];
1199  if (!MInfo.reachable)
1200  continue;
1202  SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
1203  BBInfo &SInfo = MBBInfoMap[*SuI];
1204  if (SInfo.addPassed(MInfo.regsLiveOut))
1205  todo.insert(*SuI);
1206  }
1207  }
1208 
1209  // Iteratively push vregsPassed to successors. This will converge to the same
1210  // final state regardless of DenseSet iteration order.
1211  while (!todo.empty()) {
1212  const MachineBasicBlock *MBB = *todo.begin();
1213  todo.erase(MBB);
1214  BBInfo &MInfo = MBBInfoMap[MBB];
1216  SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
1217  if (*SuI == MBB)
1218  continue;
1219  BBInfo &SInfo = MBBInfoMap[*SuI];
1220  if (SInfo.addPassed(MInfo.vregsPassed))
1221  todo.insert(*SuI);
1222  }
1223  }
1224 }
1225 
1226 // Calculate the set of virtual registers that must be passed through each basic
1227 // block in order to satisfy the requirements of successor blocks. This is very
1228 // similar to calcRegsPassed, only backwards.
1229 void MachineVerifier::calcRegsRequired() {
1230  // First push live-in regs to predecessors' vregsRequired.
1232  for (const auto &MBB : *MF) {
1233  BBInfo &MInfo = MBBInfoMap[&MBB];
1235  PrE = MBB.pred_end(); PrI != PrE; ++PrI) {
1236  BBInfo &PInfo = MBBInfoMap[*PrI];
1237  if (PInfo.addRequired(MInfo.vregsLiveIn))
1238  todo.insert(*PrI);
1239  }
1240  }
1241 
1242  // Iteratively push vregsRequired to predecessors. This will converge to the
1243  // same final state regardless of DenseSet iteration order.
1244  while (!todo.empty()) {
1245  const MachineBasicBlock *MBB = *todo.begin();
1246  todo.erase(MBB);
1247  BBInfo &MInfo = MBBInfoMap[MBB];
1249  PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
1250  if (*PrI == MBB)
1251  continue;
1252  BBInfo &SInfo = MBBInfoMap[*PrI];
1253  if (SInfo.addRequired(MInfo.vregsRequired))
1254  todo.insert(*PrI);
1255  }
1256  }
1257 }
1258 
1259 // Check PHI instructions at the beginning of MBB. It is assumed that
1260 // calcRegsPassed has been run so BBInfo::isLiveOut is valid.
1261 void MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB) {
1263  for (const auto &BBI : *MBB) {
1264  if (!BBI.isPHI())
1265  break;
1266  seen.clear();
1267 
1268  for (unsigned i = 1, e = BBI.getNumOperands(); i != e; i += 2) {
1269  unsigned Reg = BBI.getOperand(i).getReg();
1270  const MachineBasicBlock *Pre = BBI.getOperand(i + 1).getMBB();
1271  if (!Pre->isSuccessor(MBB))
1272  continue;
1273  seen.insert(Pre);
1274  BBInfo &PrInfo = MBBInfoMap[Pre];
1275  if (PrInfo.reachable && !PrInfo.isLiveOut(Reg))
1276  report("PHI operand is not live-out from predecessor",
1277  &BBI.getOperand(i), i);
1278  }
1279 
1280  // Did we see all predecessors?
1281  for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
1282  PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
1283  if (!seen.count(*PrI)) {
1284  report("Missing PHI operand", &BBI);
1285  errs() << "BB#" << (*PrI)->getNumber()
1286  << " is a predecessor according to the CFG.\n";
1287  }
1288  }
1289  }
1290 }
1291 
1292 void MachineVerifier::visitMachineFunctionAfter() {
1293  calcRegsPassed();
1294 
1295  for (const auto &MBB : *MF) {
1296  BBInfo &MInfo = MBBInfoMap[&MBB];
1297 
1298  // Skip unreachable MBBs.
1299  if (!MInfo.reachable)
1300  continue;
1301 
1302  checkPHIOps(&MBB);
1303  }
1304 
1305  // Now check liveness info if available
1306  calcRegsRequired();
1307 
1308  // Check for killed virtual registers that should be live out.
1309  for (const auto &MBB : *MF) {
1310  BBInfo &MInfo = MBBInfoMap[&MBB];
1311  for (RegSet::iterator
1312  I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
1313  ++I)
1314  if (MInfo.regsKilled.count(*I)) {
1315  report("Virtual register killed in block, but needed live out.", &MBB);
1316  errs() << "Virtual register " << PrintReg(*I)
1317  << " is used after the block.\n";
1318  }
1319  }
1320 
1321  if (!MF->empty()) {
1322  BBInfo &MInfo = MBBInfoMap[&MF->front()];
1323  for (RegSet::iterator
1324  I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
1325  ++I)
1326  report("Virtual register def doesn't dominate all uses.",
1327  MRI->getVRegDef(*I));
1328  }
1329 
1330  if (LiveVars)
1331  verifyLiveVariables();
1332  if (LiveInts)
1333  verifyLiveIntervals();
1334 }
1335 
1336 void MachineVerifier::verifyLiveVariables() {
1337  assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
1338  for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
1339  unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
1340  LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
1341  for (const auto &MBB : *MF) {
1342  BBInfo &MInfo = MBBInfoMap[&MBB];
1343 
1344  // Our vregsRequired should be identical to LiveVariables' AliveBlocks
1345  if (MInfo.vregsRequired.count(Reg)) {
1346  if (!VI.AliveBlocks.test(MBB.getNumber())) {
1347  report("LiveVariables: Block missing from AliveBlocks", &MBB);
1348  errs() << "Virtual register " << PrintReg(Reg)
1349  << " must be live through the block.\n";
1350  }
1351  } else {
1352  if (VI.AliveBlocks.test(MBB.getNumber())) {
1353  report("LiveVariables: Block should not be in AliveBlocks", &MBB);
1354  errs() << "Virtual register " << PrintReg(Reg)
1355  << " is not needed live through the block.\n";
1356  }
1357  }
1358  }
1359  }
1360 }
1361 
1362 void MachineVerifier::verifyLiveIntervals() {
1363  assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts");
1364  for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
1365  unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
1366 
1367  // Spilling and splitting may leave unused registers around. Skip them.
1368  if (MRI->reg_nodbg_empty(Reg))
1369  continue;
1370 
1371  if (!LiveInts->hasInterval(Reg)) {
1372  report("Missing live interval for virtual register", MF);
1373  errs() << PrintReg(Reg, TRI) << " still has defs or uses\n";
1374  continue;
1375  }
1376 
1377  const LiveInterval &LI = LiveInts->getInterval(Reg);
1378  assert(Reg == LI.reg && "Invalid reg to interval mapping");
1379  verifyLiveInterval(LI);
1380  }
1381 
1382  // Verify all the cached regunit intervals.
1383  for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
1384  if (const LiveRange *LR = LiveInts->getCachedRegUnit(i))
1385  verifyLiveRange(*LR, i);
1386 }
1387 
1388 void MachineVerifier::verifyLiveRangeValue(const LiveRange &LR,
1389  const VNInfo *VNI, unsigned Reg,
1390  unsigned LaneMask) {
1391  if (VNI->isUnused())
1392  return;
1393 
1394  const VNInfo *DefVNI = LR.getVNInfoAt(VNI->def);
1395 
1396  if (!DefVNI) {
1397  report("Valno not live at def and not marked unused", MF, LR, Reg,
1398  LaneMask);
1399  errs() << "Valno #" << VNI->id << '\n';
1400  return;
1401  }
1402 
1403  if (DefVNI != VNI) {
1404  report("Live segment at def has different valno", MF, LR, Reg, LaneMask);
1405  errs() << "Valno #" << VNI->id << " is defined at " << VNI->def
1406  << " where valno #" << DefVNI->id << " is live\n";
1407  return;
1408  }
1409 
1410  const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def);
1411  if (!MBB) {
1412  report("Invalid definition index", MF, LR, Reg, LaneMask);
1413  errs() << "Valno #" << VNI->id << " is defined at " << VNI->def
1414  << " in " << LR << '\n';
1415  return;
1416  }
1417 
1418  if (VNI->isPHIDef()) {
1419  if (VNI->def != LiveInts->getMBBStartIdx(MBB)) {
1420  report("PHIDef value is not defined at MBB start", MBB, LR, Reg,
1421  LaneMask);
1422  errs() << "Valno #" << VNI->id << " is defined at " << VNI->def
1423  << ", not at the beginning of BB#" << MBB->getNumber() << '\n';
1424  }
1425  return;
1426  }
1427 
1428  // Non-PHI def.
1429  const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def);
1430  if (!MI) {
1431  report("No instruction at def index", MBB, LR, Reg, LaneMask);
1432  errs() << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
1433  return;
1434  }
1435 
1436  if (Reg != 0) {
1437  bool hasDef = false;
1438  bool isEarlyClobber = false;
1439  for (ConstMIBundleOperands MOI(MI); MOI.isValid(); ++MOI) {
1440  if (!MOI->isReg() || !MOI->isDef())
1441  continue;
1443  if (MOI->getReg() != Reg)
1444  continue;
1445  } else {
1446  if (!TargetRegisterInfo::isPhysicalRegister(MOI->getReg()) ||
1447  !TRI->hasRegUnit(MOI->getReg(), Reg))
1448  continue;
1449  }
1450  if (LaneMask != 0 &&
1451  (TRI->getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask) == 0)
1452  continue;
1453  hasDef = true;
1454  if (MOI->isEarlyClobber())
1455  isEarlyClobber = true;
1456  }
1457 
1458  if (!hasDef) {
1459  report("Defining instruction does not modify register", MI);
1460  errs() << "Valno #" << VNI->id << " in " << LR << '\n';
1461  }
1462 
1463  // Early clobber defs begin at USE slots, but other defs must begin at
1464  // DEF slots.
1465  if (isEarlyClobber) {
1466  if (!VNI->def.isEarlyClobber()) {
1467  report("Early clobber def must be at an early-clobber slot", MBB, LR,
1468  Reg, LaneMask);
1469  errs() << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
1470  }
1471  } else if (!VNI->def.isRegister()) {
1472  report("Non-PHI, non-early clobber def must be at a register slot",
1473  MBB, LR, Reg, LaneMask);
1474  errs() << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
1475  }
1476  }
1477 }
1478 
1479 void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
1481  unsigned Reg, unsigned LaneMask) {
1482  const LiveRange::Segment &S = *I;
1483  const VNInfo *VNI = S.valno;
1484  assert(VNI && "Live segment has no valno");
1485 
1486  if (VNI->id >= LR.getNumValNums() || VNI != LR.getValNumInfo(VNI->id)) {
1487  report("Foreign valno in live segment", MF, LR, Reg, LaneMask);
1488  errs() << S << " has a bad valno\n";
1489  }
1490 
1491  if (VNI->isUnused()) {
1492  report("Live segment valno is marked unused", MF, LR, Reg, LaneMask);
1493  errs() << S << '\n';
1494  }
1495 
1496  const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(S.start);
1497  if (!MBB) {
1498  report("Bad start of live segment, no basic block", MF, LR, Reg, LaneMask);
1499  errs() << S << '\n';
1500  return;
1501  }
1502  SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB);
1503  if (S.start != MBBStartIdx && S.start != VNI->def) {
1504  report("Live segment must begin at MBB entry or valno def", MBB, LR, Reg,
1505  LaneMask);
1506  errs() << S << '\n';
1507  }
1508 
1509  const MachineBasicBlock *EndMBB =
1510  LiveInts->getMBBFromIndex(S.end.getPrevSlot());
1511  if (!EndMBB) {
1512  report("Bad end of live segment, no basic block", MF, LR, Reg, LaneMask);
1513  errs() << S << '\n';
1514  return;
1515  }
1516 
1517  // No more checks for live-out segments.
1518  if (S.end == LiveInts->getMBBEndIdx(EndMBB))
1519  return;
1520 
1521  // RegUnit intervals are allowed dead phis.
1522  if (!TargetRegisterInfo::isVirtualRegister(Reg) && VNI->isPHIDef() &&
1523  S.start == VNI->def && S.end == VNI->def.getDeadSlot())
1524  return;
1525 
1526  // The live segment is ending inside EndMBB
1527  const MachineInstr *MI =
1528  LiveInts->getInstructionFromIndex(S.end.getPrevSlot());
1529  if (!MI) {
1530  report("Live segment doesn't end at a valid instruction", EndMBB, LR, Reg,
1531  LaneMask);
1532  errs() << S << '\n';
1533  return;
1534  }
1535 
1536  // The block slot must refer to a basic block boundary.
1537  if (S.end.isBlock()) {
1538  report("Live segment ends at B slot of an instruction", EndMBB, LR, Reg,
1539  LaneMask);
1540  errs() << S << '\n';
1541  }
1542 
1543  if (S.end.isDead()) {
1544  // Segment ends on the dead slot.
1545  // That means there must be a dead def.
1546  if (!SlotIndex::isSameInstr(S.start, S.end)) {
1547  report("Live segment ending at dead slot spans instructions", EndMBB, LR,
1548  Reg, LaneMask);
1549  errs() << S << '\n';
1550  }
1551  }
1552 
1553  // A live segment can only end at an early-clobber slot if it is being
1554  // redefined by an early-clobber def.
1555  if (S.end.isEarlyClobber()) {
1556  if (I+1 == LR.end() || (I+1)->start != S.end) {
1557  report("Live segment ending at early clobber slot must be "
1558  "redefined by an EC def in the same instruction", EndMBB, LR, Reg,
1559  LaneMask);
1560  errs() << S << '\n';
1561  }
1562  }
1563 
1564  // The following checks only apply to virtual registers. Physreg liveness
1565  // is too weird to check.
1567  // A live segment can end with either a redefinition, a kill flag on a
1568  // use, or a dead flag on a def.
1569  bool hasRead = false;
1570  bool hasSubRegDef = false;
1571  for (ConstMIBundleOperands MOI(MI); MOI.isValid(); ++MOI) {
1572  if (!MOI->isReg() || MOI->getReg() != Reg)
1573  continue;
1574  if (LaneMask != 0 &&
1575  (LaneMask & TRI->getSubRegIndexLaneMask(MOI->getSubReg())) == 0)
1576  continue;
1577  if (MOI->isDef() && MOI->getSubReg() != 0)
1578  hasSubRegDef = true;
1579  if (MOI->readsReg())
1580  hasRead = true;
1581  }
1582  if (!S.end.isDead()) {
1583  if (!hasRead) {
1584  // When tracking subregister liveness, the main range must start new
1585  // values on partial register writes, even if there is no read.
1586  if (!MRI->shouldTrackSubRegLiveness(Reg) || LaneMask != 0 ||
1587  !hasSubRegDef) {
1588  report("Instruction ending live segment doesn't read the register",
1589  MI);
1590  errs() << S << " in " << LR << '\n';
1591  }
1592  }
1593  }
1594  }
1595 
1596  // Now check all the basic blocks in this live segment.
1598  // Is this live segment the beginning of a non-PHIDef VN?
1599  if (S.start == VNI->def && !VNI->isPHIDef()) {
1600  // Not live-in to any blocks.
1601  if (MBB == EndMBB)
1602  return;
1603  // Skip this block.
1604  ++MFI;
1605  }
1606  for (;;) {
1607  assert(LiveInts->isLiveInToMBB(LR, MFI));
1608  // We don't know how to track physregs into a landing pad.
1610  MFI->isLandingPad()) {
1611  if (&*MFI == EndMBB)
1612  break;
1613  ++MFI;
1614  continue;
1615  }
1616 
1617  // Is VNI a PHI-def in the current block?
1618  bool IsPHI = VNI->isPHIDef() &&
1619  VNI->def == LiveInts->getMBBStartIdx(MFI);
1620 
1621  // Check that VNI is live-out of all predecessors.
1622  for (MachineBasicBlock::const_pred_iterator PI = MFI->pred_begin(),
1623  PE = MFI->pred_end(); PI != PE; ++PI) {
1624  SlotIndex PEnd = LiveInts->getMBBEndIdx(*PI);
1625  const VNInfo *PVNI = LR.getVNInfoBefore(PEnd);
1626 
1627  // All predecessors must have a live-out value.
1628  if (!PVNI) {
1629  report("Register not marked live out of predecessor", *PI, LR, Reg,
1630  LaneMask);
1631  errs() << "Valno #" << VNI->id << " live into BB#" << MFI->getNumber()
1632  << '@' << LiveInts->getMBBStartIdx(MFI) << ", not live before "
1633  << PEnd << '\n';
1634  continue;
1635  }
1636 
1637  // Only PHI-defs can take different predecessor values.
1638  if (!IsPHI && PVNI != VNI) {
1639  report("Different value live out of predecessor", *PI, LR, Reg,
1640  LaneMask);
1641  errs() << "Valno #" << PVNI->id << " live out of BB#"
1642  << (*PI)->getNumber() << '@' << PEnd
1643  << "\nValno #" << VNI->id << " live into BB#" << MFI->getNumber()
1644  << '@' << LiveInts->getMBBStartIdx(MFI) << '\n';
1645  }
1646  }
1647  if (&*MFI == EndMBB)
1648  break;
1649  ++MFI;
1650  }
1651 }
1652 
1653 void MachineVerifier::verifyLiveRange(const LiveRange &LR, unsigned Reg,
1654  unsigned LaneMask) {
1655  for (const VNInfo *VNI : LR.valnos)
1656  verifyLiveRangeValue(LR, VNI, Reg, LaneMask);
1657 
1658  for (LiveRange::const_iterator I = LR.begin(), E = LR.end(); I != E; ++I)
1659  verifyLiveRangeSegment(LR, I, Reg, LaneMask);
1660 }
1661 
1662 void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) {
1663  unsigned Reg = LI.reg;
1665  verifyLiveRange(LI, Reg);
1666 
1667  unsigned Mask = 0;
1668  unsigned MaxMask = MRI->getMaxLaneMaskForVReg(Reg);
1669  for (const LiveInterval::SubRange &SR : LI.subranges()) {
1670  if ((Mask & SR.LaneMask) != 0)
1671  report("Lane masks of sub ranges overlap in live interval", MF, LI);
1672  if ((SR.LaneMask & ~MaxMask) != 0)
1673  report("Subrange lanemask is invalid", MF, LI);
1674  Mask |= SR.LaneMask;
1675  verifyLiveRange(SR, LI.reg, SR.LaneMask);
1676  if (!LI.covers(SR))
1677  report("A Subrange is not covered by the main range", MF, LI);
1678  }
1679 
1680  // Check the LI only has one connected component.
1681  ConnectedVNInfoEqClasses ConEQ(*LiveInts);
1682  unsigned NumComp = ConEQ.Classify(&LI);
1683  if (NumComp > 1) {
1684  report("Multiple connected components in live interval", MF, LI);
1685  for (unsigned comp = 0; comp != NumComp; ++comp) {
1686  errs() << comp << ": valnos";
1688  E = LI.vni_end(); I!=E; ++I)
1689  if (comp == ConEQ.getEqClass(*I))
1690  errs() << ' ' << (*I)->id;
1691  errs() << '\n';
1692  }
1693  }
1694 }
1695 
1696 namespace {
1697  // FrameSetup and FrameDestroy can have zero adjustment, so using a single
1698  // integer, we can't tell whether it is a FrameSetup or FrameDestroy if the
1699  // value is zero.
1700  // We use a bool plus an integer to capture the stack state.
1701  struct StackStateOfBB {
1702  StackStateOfBB() : EntryValue(0), ExitValue(0), EntryIsSetup(false),
1703  ExitIsSetup(false) { }
1704  StackStateOfBB(int EntryVal, int ExitVal, bool EntrySetup, bool ExitSetup) :
1705  EntryValue(EntryVal), ExitValue(ExitVal), EntryIsSetup(EntrySetup),
1706  ExitIsSetup(ExitSetup) { }
1707  // Can be negative, which means we are setting up a frame.
1708  int EntryValue;
1709  int ExitValue;
1710  bool EntryIsSetup;
1711  bool ExitIsSetup;
1712  };
1713 }
1714 
1715 /// Make sure on every path through the CFG, a FrameSetup <n> is always followed
1716 /// by a FrameDestroy <n>, stack adjustments are identical on all
1717 /// CFG edges to a merge point, and frame is destroyed at end of a return block.
1718 void MachineVerifier::verifyStackFrame() {
1719  unsigned FrameSetupOpcode = TII->getCallFrameSetupOpcode();
1720  unsigned FrameDestroyOpcode = TII->getCallFrameDestroyOpcode();
1721 
1723  SPState.resize(MF->getNumBlockIDs());
1725 
1726  // Visit the MBBs in DFS order.
1727  for (df_ext_iterator<const MachineFunction*,
1729  DFI = df_ext_begin(MF, Reachable), DFE = df_ext_end(MF, Reachable);
1730  DFI != DFE; ++DFI) {
1731  const MachineBasicBlock *MBB = *DFI;
1732 
1733  StackStateOfBB BBState;
1734  // Check the exit state of the DFS stack predecessor.
1735  if (DFI.getPathLength() >= 2) {
1736  const MachineBasicBlock *StackPred = DFI.getPath(DFI.getPathLength() - 2);
1737  assert(Reachable.count(StackPred) &&
1738  "DFS stack predecessor is already visited.\n");
1739  BBState.EntryValue = SPState[StackPred->getNumber()].ExitValue;
1740  BBState.EntryIsSetup = SPState[StackPred->getNumber()].ExitIsSetup;
1741  BBState.ExitValue = BBState.EntryValue;
1742  BBState.ExitIsSetup = BBState.EntryIsSetup;
1743  }
1744 
1745  // Update stack state by checking contents of MBB.
1746  for (const auto &I : *MBB) {
1747  if (I.getOpcode() == FrameSetupOpcode) {
1748  // The first operand of a FrameOpcode should be i32.
1749  int Size = I.getOperand(0).getImm();
1750  assert(Size >= 0 &&
1751  "Value should be non-negative in FrameSetup and FrameDestroy.\n");
1752 
1753  if (BBState.ExitIsSetup)
1754  report("FrameSetup is after another FrameSetup", &I);
1755  BBState.ExitValue -= Size;
1756  BBState.ExitIsSetup = true;
1757  }
1758 
1759  if (I.getOpcode() == FrameDestroyOpcode) {
1760  // The first operand of a FrameOpcode should be i32.
1761  int Size = I.getOperand(0).getImm();
1762  assert(Size >= 0 &&
1763  "Value should be non-negative in FrameSetup and FrameDestroy.\n");
1764 
1765  if (!BBState.ExitIsSetup)
1766  report("FrameDestroy is not after a FrameSetup", &I);
1767  int AbsSPAdj = BBState.ExitValue < 0 ? -BBState.ExitValue :
1768  BBState.ExitValue;
1769  if (BBState.ExitIsSetup && AbsSPAdj != Size) {
1770  report("FrameDestroy <n> is after FrameSetup <m>", &I);
1771  errs() << "FrameDestroy <" << Size << "> is after FrameSetup <"
1772  << AbsSPAdj << ">.\n";
1773  }
1774  BBState.ExitValue += Size;
1775  BBState.ExitIsSetup = false;
1776  }
1777  }
1778  SPState[MBB->getNumber()] = BBState;
1779 
1780  // Make sure the exit state of any predecessor is consistent with the entry
1781  // state.
1782  for (MachineBasicBlock::const_pred_iterator I = MBB->pred_begin(),
1783  E = MBB->pred_end(); I != E; ++I) {
1784  if (Reachable.count(*I) &&
1785  (SPState[(*I)->getNumber()].ExitValue != BBState.EntryValue ||
1786  SPState[(*I)->getNumber()].ExitIsSetup != BBState.EntryIsSetup)) {
1787  report("The exit stack state of a predecessor is inconsistent.", MBB);
1788  errs() << "Predecessor BB#" << (*I)->getNumber() << " has exit state ("
1789  << SPState[(*I)->getNumber()].ExitValue << ", "
1790  << SPState[(*I)->getNumber()].ExitIsSetup
1791  << "), while BB#" << MBB->getNumber() << " has entry state ("
1792  << BBState.EntryValue << ", " << BBState.EntryIsSetup << ").\n";
1793  }
1794  }
1795 
1796  // Make sure the entry state of any successor is consistent with the exit
1797  // state.
1798  for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
1799  E = MBB->succ_end(); I != E; ++I) {
1800  if (Reachable.count(*I) &&
1801  (SPState[(*I)->getNumber()].EntryValue != BBState.ExitValue ||
1802  SPState[(*I)->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) {
1803  report("The entry stack state of a successor is inconsistent.", MBB);
1804  errs() << "Successor BB#" << (*I)->getNumber() << " has entry state ("
1805  << SPState[(*I)->getNumber()].EntryValue << ", "
1806  << SPState[(*I)->getNumber()].EntryIsSetup
1807  << "), while BB#" << MBB->getNumber() << " has exit state ("
1808  << BBState.ExitValue << ", " << BBState.ExitIsSetup << ").\n";
1809  }
1810  }
1811 
1812  // Make sure a basic block with return ends with zero stack adjustment.
1813  if (!MBB->empty() && MBB->back().isReturn()) {
1814  if (BBState.ExitIsSetup)
1815  report("A return block ends with a FrameSetup.", MBB);
1816  if (BBState.ExitValue)
1817  report("A return block ends with a nonzero stack adjustment.", MBB);
1818  }
1819  }
1820 }
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:82
bool isInsideBundle() const
Return true if MI is in a bundle (but not the first MI in a bundle).
Definition: MachineInstr.h:205
bool isImplicit() const
unsigned succ_size() const
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
Definition: BitVector.h:156
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
const unsigned reg
Definition: LiveInterval.h:616
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Definition: SmallPtrSet.h:78
SlotIndex def
The index of the defining instruction.
Definition: LiveInterval.h:53
BitVector getPristineRegs(const MachineFunction &MF) const
Return a set of physical registers that are pristine.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
iterator_range< mop_iterator > uses()
Definition: MachineInstr.h:325
MachineBasicBlock * getMBB() const
static unsigned index2VirtReg(unsigned Index)
index2VirtReg - Convert a 0-based index to a virtual register number.
int getNumber() const
getNumber - MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a M...
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:191
DenseSet - This implements a dense probed hash-table based set.
Definition: DenseSet.h:39
int find_next(unsigned Prev) const
find_next - Returns the index of the next set bit following the "Prev" bit.
Definition: BitVector.h:165
DWARF-like instruction based exceptions.
vni_iterator vni_begin()
Definition: LiveInterval.h:213
std::vector< unsigned >::const_iterator livein_iterator
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:588
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:138
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:579
bool isDead() const
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
static bool matchPair(MachineBasicBlock::const_succ_iterator i, const MachineBasicBlock *a, const MachineBasicBlock *b)
size_type count(PtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
Definition: SmallPtrSet.h:276
void verify(Pass *p=nullptr, const char *Banner=nullptr) const
verify - Run the current MachineFunction through the machine code verifier, useful for debugger use...
bool isTied() const
PrintRegUnit - Helper class for printing register units on a raw_ostream.
bool isKill() const
Return true if the live-in value is killed by this instruction.
Definition: LiveInterval.h:108
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:264
A live range for subregisters.
Definition: LiveInterval.h:595
MachineBasicBlock reference.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
hasSuperClassEq - Returns true if RC is a super-class of or equal to this class.
This represents a simple continuous liveness interval for a value.
Definition: LiveInterval.h:159
VarInfo - This represents the regions where a virtual register is live in the program.
Definition: LiveVariables.h:79
bool isRegister() const
isRegister - Returns true if this is a normal register use/def slot.
Definition: SlotIndexes.h:236
VNInfo - Value Number Information.
Definition: LiveInterval.h:45
bool isMetadata() const
isMetadata - Tests if this is a MO_Metadata operand.
unsigned getNumValNums() const
Definition: LiveInterval.h:288
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
Definition: LiveInterval.h:392
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:419
bool isEarlyClobber() const
isEarlyClobber - Returns true if this is an early-clobber slot.
Definition: SlotIndexes.h:232
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag=true)
Reports a serious error, calling any installed error handler.
This class represents the liveness of a register, stack slot, etc.
Definition: LiveInterval.h:153
void initializeMachineVerifierPassPass(PassRegistry &)
Mask of preserved registers.
FunctionPass * createMachineVerifierPass(const std::string &Banner)
createMachineVerifierPass - This pass verifies cenerated machine code instructions for correctness...
livein_iterator livein_begin() const
bool test(unsigned Idx)
MachineMemOperand - A description of a memory reference used in the backend.
void clear()
clear - Clear all bits.
Definition: BitVector.h:187
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:79
const HexagonInstrInfo * TII
bool isPredicated(const MachineInstr *MI) const override
AnalysisType * getAnalysisIfAvailable() const
getAnalysisIfAvailable<AnalysisType>() - Subclasses use this function to get analysis information tha...
bool isPHI() const
Definition: MachineInstr.h:757
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
iterator end()
Definition: LiveInterval.h:206
bool isReg() const
isReg - Tests if this is a MO_Register operand.
iterator_range< subrange_iterator > subranges()
Definition: LiveInterval.h:670
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:566
Result of a LiveRange query.
Definition: LiveInterval.h:86
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool isBlock() const
isBlock - Returns true if this is a block boundary slot.
Definition: SlotIndexes.h:229
#define false
Definition: ConvertUTF.c:65
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
Definition: SlotIndexes.h:262
SparseBitVector AliveBlocks
AliveBlocks - Set of blocks in which this value is alive completely through.
Definition: LiveVariables.h:84
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:271
bool isUnused() const
Returns true if this value is unused.
Definition: LiveInterval.h:77
PrintReg - Helper class for printing registers on a raw_ostream.
const MachineBasicBlock & front() const
bool isDead() const
isDead - Returns true if this is a dead def kill slot.
Definition: SlotIndexes.h:239
bool isKill() const
SlotIndexes pass.
Definition: SlotIndexes.h:334
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Definition: SmallVector.h:57
const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
Definition: StringRef.h:107
void print(raw_ostream &OS, SlotIndexes *=nullptr) const
print - Print out the MachineFunction in a format suitable for debugging to the specified stream...
int64_t getImm() const
VNInfoList::const_iterator const_vni_iterator
Definition: LiveInterval.h:216
INITIALIZE_PASS(MachineVerifierPass,"machineverifier","Verify generated machine code", false, false) FunctionPass *llvm
const BasicBlock * getBasicBlock() const
getBasicBlock - Return the LLVM basic block that this instance corresponded to originally.
SlotIndex getPrevSlot() const
Returns the previous slot in the index list.
Definition: SlotIndexes.h:292
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:120
format_object< Ts...> format(const char *Fmt, const Ts &...Vals)
These are helper functions used to produce formatted output.
Definition: Format.h:111
TargetInstrInfo - Interface to description of machine instruction set.
bool isDebugValue() const
Definition: MachineInstr.h:748
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:58
mmo_iterator memoperands_end() const
Definition: MachineInstr.h:341
bool isDeadDef() const
Return true if this instruction has a dead def.
Definition: LiveInterval.h:113
bool isEarlyClobber() const
unsigned findTiedOperandIdx(unsigned OpIdx) const
Given the index of a tied register operand, find the operand it is tied to.
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr) const
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
Definition: LiveInterval.h:493
LLVM Basic Block Representation.
Definition: BasicBlock.h:65
size_type size() const
Definition: SmallPtrSet.h:79
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
void print(raw_ostream &OS, bool SkipOpers=false) const
df_ext_iterator< T, SetTy > df_ext_end(const T &G, SetTy &S)
bool isOptionalDef() const
Set if this operand is a optional def.
Definition: MCInstrDesc.h:85
livein_iterator livein_end() const
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:264
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag...
Definition: InlineAsm.h:332
Two Address instruction pass
Represent the analysis usage information of a pass.
df_ext_iterator< T, SetTy > df_ext_begin(const T &G, SetTy &S)
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
bool isVariadic(QueryType Type=IgnoreBundle) const
Return true if this instruction can have a variable number of operands.
Definition: MachineInstr.h:383
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:294
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:511
iterator begin() const
Definition: SmallPtrSet.h:286
unsigned getSubReg() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
MCSubRegIterator enumerates all sub-registers of Reg.
bool liveAt(SlotIndex index) const
Definition: LiveInterval.h:372
bool isPHIDef() const
Returns true if this value is defined by a PHI instruction (or was, PHI instructions may have been el...
Definition: LiveInterval.h:74
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:162
std::vector< MachineBasicBlock * >::const_iterator const_pred_iterator
std::vector< MachineInstr * > Kills
Kills - List of MachineInstruction's which are the last use of this virtual register (kill it) in the...
Definition: LiveVariables.h:89
unsigned id
The ID number of this value.
Definition: LiveInterval.h:50
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
Definition: SmallPtrSet.h:299
bool erase(PtrType Ptr)
erase - If the set contains the specified pointer, remove it and return true, otherwise return false...
Definition: SmallPtrSet.h:271
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
Definition: SlotIndexes.h:206
ConnectedVNInfoEqClasses - Helper class that can divide VNInfos in a LiveInterval into equivalence cl...
Definition: LiveInterval.h:841
MachineOperand class - Representation of each machine instruction operand.
bool isInlineAsm() const
Definition: MachineInstr.h:760
bool isSuccessor(const MachineBasicBlock *MBB) const
isSuccessor - Return true if the specified MBB is a successor of this block.
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
StringRef getName() const
getName - Return the name of the corresponding LLVM basic block, or "(null)".
void setPreservesAll()
Set by analyses that do not transform their input at all.
VNInfoList valnos
Definition: LiveInterval.h:196
VNInfo * getValNumInfo(unsigned ValNo)
getValNumInfo - Returns pointer to the specified val#.
Definition: LiveInterval.h:292
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
void set_subtract(S1Ty &S1, const S2Ty &S2)
set_subtract(A, B) - Compute A := A - B
Definition: SetOperations.h:63
Representation of each machine instruction.
Definition: MachineInstr.h:51
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
static bool isPhysicalRegister(unsigned Reg)
isPhysicalRegister - Return true if the specified register number is in the physical register namespa...
bool isLandingPad() const
isLandingPad - Returns true if the block is a landing pad.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
#define I(x, y, z)
Definition: MD5.cpp:54
TerminatorInst * getTerminator()
Returns the terminator instruction if the block is well formed or null if the block is not well forme...
Definition: BasicBlock.cpp:124
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Abstract Stack Frame Index.
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def...
Definition: SlotIndexes.h:257
iterator begin()
Definition: LiveInterval.h:205
unsigned getReg() const
getReg - Returns the register number.
bool isValid() const
isValid - Returns true until all the operands have been visited.
std::vector< MachineBasicBlock * >::const_iterator const_succ_iterator
aarch64 promote const
virtual const TargetInstrInfo * getInstrInfo() const
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:185
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:149
Primary interface to the complete machine description for the target machine.
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:40
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register. ...
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
VNInfo * valueIn() const
Return the value that is live-in to the instruction.
Definition: LiveInterval.h:101
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:56
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:92
bool covers(const LiveRange &Other) const
Returns true if all segments of the Other live range are completely covered by this live range...
vni_iterator vni_end()
Definition: LiveInterval.h:214
bool set_union(S1Ty &S1, const S2Ty &S2)
set_union(A, B) - Compute A := A u B, return whether A changed.
Definition: SetOperations.h:23
unsigned pred_size() const
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:410
VNInfo * getVNInfoBefore(SlotIndex Idx) const
getVNInfoBefore - Return the VNInfo that is live up to but not necessarilly including Idx...
Definition: LiveInterval.h:400
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:340
void resize(size_type N)
Definition: SmallVector.h:376