LLVM  3.7.0
SIInstrInfo.h
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1 //===-- SIInstrInfo.h - SI Instruction Info Interface -----------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief Interface definition for SIInstrInfo.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 
16 #ifndef LLVM_LIB_TARGET_R600_SIINSTRINFO_H
17 #define LLVM_LIB_TARGET_R600_SIINSTRINFO_H
18 
19 #include "AMDGPUInstrInfo.h"
20 #include "SIDefines.h"
21 #include "SIRegisterInfo.h"
22 
23 namespace llvm {
24 
25 class SIInstrInfo : public AMDGPUInstrInfo {
26 private:
27  const SIRegisterInfo RI;
28 
29  unsigned buildExtractSubReg(MachineBasicBlock::iterator MI,
31  MachineOperand &SuperReg,
32  const TargetRegisterClass *SuperRC,
33  unsigned SubIdx,
34  const TargetRegisterClass *SubRC) const;
35  MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI,
37  MachineOperand &SuperReg,
38  const TargetRegisterClass *SuperRC,
39  unsigned SubIdx,
40  const TargetRegisterClass *SubRC) const;
41 
42  unsigned split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist,
45  const TargetRegisterClass *RC,
46  const MachineOperand &Op) const;
47 
48  void swapOperands(MachineBasicBlock::iterator Inst) const;
49 
50  void splitScalar64BitUnaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
51  MachineInstr *Inst, unsigned Opcode) const;
52 
53  void splitScalar64BitBinaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
54  MachineInstr *Inst, unsigned Opcode) const;
55 
56  void splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
57  MachineInstr *Inst) const;
58  void splitScalar64BitBFE(SmallVectorImpl<MachineInstr *> &Worklist,
59  MachineInstr *Inst) const;
60 
61  void addDescImplicitUseDef(const MCInstrDesc &Desc, MachineInstr *MI) const;
62 
63  bool checkInstOffsetsDoNotOverlap(MachineInstr *MIa,
64  MachineInstr *MIb) const;
65 
66  unsigned findUsedSGPR(const MachineInstr *MI, int OpIndices[3]) const;
67 
68 public:
69  explicit SIInstrInfo(const AMDGPUSubtarget &st);
70 
71  const SIRegisterInfo &getRegisterInfo() const override {
72  return RI;
73  }
74 
76  AliasAnalysis *AA) const override;
77 
78  bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
79  int64_t &Offset1,
80  int64_t &Offset2) const override;
81 
82  bool getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
83  unsigned &Offset,
84  const TargetRegisterInfo *TRI) const final;
85 
86  bool shouldClusterLoads(MachineInstr *FirstLdSt,
87  MachineInstr *SecondLdSt,
88  unsigned NumLoads) const final;
89 
92  unsigned DestReg, unsigned SrcReg,
93  bool KillSrc) const override;
94 
97  RegScavenger *RS,
98  unsigned TmpReg,
99  unsigned Offset,
100  unsigned Size) const;
101 
104  unsigned SrcReg, bool isKill, int FrameIndex,
105  const TargetRegisterClass *RC,
106  const TargetRegisterInfo *TRI) const override;
107 
110  unsigned DestReg, int FrameIndex,
111  const TargetRegisterClass *RC,
112  const TargetRegisterInfo *TRI) const override;
113 
114  bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
115 
116  // \brief Returns an opcode that can be used to move a value to a \p DstRC
117  // register. If there is no hardware instruction that can store to \p
118  // DstRC, then AMDGPU::COPY is returned.
119  unsigned getMovOpcode(const TargetRegisterClass *DstRC) const;
120  int commuteOpcode(const MachineInstr &MI) const;
121 
123  bool NewMI = false) const override;
125  unsigned &SrcOpIdx1,
126  unsigned &SrcOpIdx2) const override;
127 
129  AliasAnalysis *AA = nullptr) const;
130 
132  MachineInstr *MIa, MachineInstr *MIb,
133  AliasAnalysis *AA = nullptr) const override;
134 
137  unsigned DstReg, unsigned SrcReg) const override;
138  bool isMov(unsigned Opcode) const override;
139 
140  bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
141 
142  bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
143  unsigned Reg, MachineRegisterInfo *MRI) const final;
144 
145  unsigned getMachineCSELookAheadLimit() const override { return 500; }
146 
149  LiveVariables *LV) const override;
150 
151  bool isSALU(uint16_t Opcode) const {
152  return get(Opcode).TSFlags & SIInstrFlags::SALU;
153  }
154 
155  bool isVALU(uint16_t Opcode) const {
156  return get(Opcode).TSFlags & SIInstrFlags::VALU;
157  }
158 
159  bool isSOP1(uint16_t Opcode) const {
160  return get(Opcode).TSFlags & SIInstrFlags::SOP1;
161  }
162 
163  bool isSOP2(uint16_t Opcode) const {
164  return get(Opcode).TSFlags & SIInstrFlags::SOP2;
165  }
166 
167  bool isSOPC(uint16_t Opcode) const {
168  return get(Opcode).TSFlags & SIInstrFlags::SOPC;
169  }
170 
171  bool isSOPK(uint16_t Opcode) const {
172  return get(Opcode).TSFlags & SIInstrFlags::SOPK;
173  }
174 
175  bool isSOPP(uint16_t Opcode) const {
176  return get(Opcode).TSFlags & SIInstrFlags::SOPP;
177  }
178 
179  bool isVOP1(uint16_t Opcode) const {
180  return get(Opcode).TSFlags & SIInstrFlags::VOP1;
181  }
182 
183  bool isVOP2(uint16_t Opcode) const {
184  return get(Opcode).TSFlags & SIInstrFlags::VOP2;
185  }
186 
187  bool isVOP3(uint16_t Opcode) const {
188  return get(Opcode).TSFlags & SIInstrFlags::VOP3;
189  }
190 
191  bool isVOPC(uint16_t Opcode) const {
192  return get(Opcode).TSFlags & SIInstrFlags::VOPC;
193  }
194 
195  bool isMUBUF(uint16_t Opcode) const {
196  return get(Opcode).TSFlags & SIInstrFlags::MUBUF;
197  }
198 
199  bool isMTBUF(uint16_t Opcode) const {
200  return get(Opcode).TSFlags & SIInstrFlags::MTBUF;
201  }
202 
203  bool isSMRD(uint16_t Opcode) const {
204  return get(Opcode).TSFlags & SIInstrFlags::SMRD;
205  }
206 
207  bool isDS(uint16_t Opcode) const {
208  return get(Opcode).TSFlags & SIInstrFlags::DS;
209  }
210 
211  bool isMIMG(uint16_t Opcode) const {
212  return get(Opcode).TSFlags & SIInstrFlags::MIMG;
213  }
214 
215  bool isFLAT(uint16_t Opcode) const {
216  return get(Opcode).TSFlags & SIInstrFlags::FLAT;
217  }
218 
219  bool isWQM(uint16_t Opcode) const {
220  return get(Opcode).TSFlags & SIInstrFlags::WQM;
221  }
222 
223  bool isVGPRSpill(uint16_t Opcode) const {
224  return get(Opcode).TSFlags & SIInstrFlags::VGPRSpill;
225  }
226 
227  bool isInlineConstant(const APInt &Imm) const;
228  bool isInlineConstant(const MachineOperand &MO, unsigned OpSize) const;
229  bool isLiteralConstant(const MachineOperand &MO, unsigned OpSize) const;
230 
231  bool isImmOperandLegal(const MachineInstr *MI, unsigned OpNo,
232  const MachineOperand &MO) const;
233 
234  /// \brief Return true if this 64-bit VALU instruction has a 32-bit encoding.
235  /// This function will return false if you pass it a 32-bit instruction.
236  bool hasVALU32BitEncoding(unsigned Opcode) const;
237 
238  /// \brief Returns true if this operand uses the constant bus.
239  bool usesConstantBus(const MachineRegisterInfo &MRI,
240  const MachineOperand &MO,
241  unsigned OpSize) const;
242 
243  /// \brief Return true if this instruction has any modifiers.
244  /// e.g. src[012]_mod, omod, clamp.
245  bool hasModifiers(unsigned Opcode) const;
246 
247  bool hasModifiersSet(const MachineInstr &MI,
248  unsigned OpName) const;
249 
250  bool verifyInstruction(const MachineInstr *MI,
251  StringRef &ErrInfo) const override;
252 
253  static unsigned getVALUOp(const MachineInstr &MI);
254 
255  bool isSALUOpSupportedOnVALU(const MachineInstr &MI) const;
256 
257  /// \brief Return the correct register class for \p OpNo. For target-specific
258  /// instructions, this will return the register class that has been defined
259  /// in tablegen. For generic instructions, like REG_SEQUENCE it will return
260  /// the register class of its machine operand.
261  /// to infer the correct register class base on the other operands.
263  unsigned OpNo) const;
264 
265  /// \brief Return the size in bytes of the operand OpNo on the given
266  // instruction opcode.
267  unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const {
268  const MCOperandInfo &OpInfo = get(Opcode).OpInfo[OpNo];
269 
270  if (OpInfo.RegClass == -1) {
271  // If this is an immediate operand, this must be a 32-bit literal.
272  assert(OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE);
273  return 4;
274  }
275 
276  return RI.getRegClass(OpInfo.RegClass)->getSize();
277  }
278 
279  /// \brief This form should usually be preferred since it handles operands
280  /// with unknown register classes.
281  unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const {
282  return getOpRegClass(MI, OpNo)->getSize();
283  }
284 
285  /// \returns true if it is legal for the operand at index \p OpNo
286  /// to read a VGPR.
287  bool canReadVGPR(const MachineInstr &MI, unsigned OpNo) const;
288 
289  /// \brief Legalize the \p OpIndex operand of this instruction by inserting
290  /// a MOV. For example:
291  /// ADD_I32_e32 VGPR0, 15
292  /// to
293  /// MOV VGPR1, 15
294  /// ADD_I32_e32 VGPR0, VGPR1
295  ///
296  /// If the operand being legalized is a register, then a COPY will be used
297  /// instead of MOV.
298  void legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const;
299 
300  /// \brief Check if \p MO is a legal operand if it was the \p OpIdx Operand
301  /// for \p MI.
302  bool isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
303  const MachineOperand *MO = nullptr) const;
304 
305  /// \brief Legalize all operands in this instruction. This function may
306  /// create new instruction and insert them before \p MI.
307  void legalizeOperands(MachineInstr *MI) const;
308 
309  /// \brief Split an SMRD instruction into two smaller loads of half the
310  // size storing the results in \p Lo and \p Hi.
311  void splitSMRD(MachineInstr *MI, const TargetRegisterClass *HalfRC,
312  unsigned HalfImmOp, unsigned HalfSGPROp,
313  MachineInstr *&Lo, MachineInstr *&Hi) const;
314 
315  void moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const;
316 
317  /// \brief Replace this instruction's opcode with the equivalent VALU
318  /// opcode. This function will also move the users of \p MI to the
319  /// VALU if necessary.
320  void moveToVALU(MachineInstr &MI) const;
321 
322  unsigned calculateIndirectAddress(unsigned RegIndex,
323  unsigned Channel) const override;
324 
325  const TargetRegisterClass *getIndirectAddrRegClass() const override;
326 
329  unsigned ValueReg,
330  unsigned Address,
331  unsigned OffsetReg) const override;
332 
335  unsigned ValueReg,
336  unsigned Address,
337  unsigned OffsetReg) const override;
339  const MachineFunction &MF) const;
340 
342  unsigned SavReg, unsigned IndexReg) const;
343 
344  void insertNOPs(MachineBasicBlock::iterator MI, int Count) const;
345 
346  /// \brief Returns the operand named \p Op. If \p MI does not have an
347  /// operand named \c Op, this function returns nullptr.
348  MachineOperand *getNamedOperand(MachineInstr &MI, unsigned OperandName) const;
349 
351  unsigned OpName) const {
352  return getNamedOperand(const_cast<MachineInstr &>(MI), OpName);
353  }
354 
355  uint64_t getDefaultRsrcDataFormat() const;
356 
357 };
358 
359 namespace AMDGPU {
360 
361  int getVOPe64(uint16_t Opcode);
362  int getVOPe32(uint16_t Opcode);
363  int getCommuteRev(uint16_t Opcode);
364  int getCommuteOrig(uint16_t Opcode);
365  int getAddr64Inst(uint16_t Opcode);
366  int getAtomicRetOp(uint16_t Opcode);
367  int getAtomicNoRetOp(uint16_t Opcode);
368 
369  const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
370  const uint64_t RSRC_TID_ENABLE = 1LL << 55;
371 
372 } // End namespace AMDGPU
373 
374 namespace SI {
375 namespace KernelInputOffsets {
376 
377 /// Offsets in bytes from the start of the input buffer
378 enum Offsets {
388 };
389 
390 } // End namespace KernelInputOffsets
391 } // End namespace SI
392 
393 } // End namespace llvm
394 
395 #endif
Interface definition for SIRegisterInfo.
bool shouldClusterLoads(MachineInstr *FirstLdSt, MachineInstr *SecondLdSt, unsigned NumLoads) const final
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned ValueReg, unsigned Address, unsigned OffsetReg) const override
Build instruction(s) for an indirect register write.
int getVOPe64(uint16_t Opcode)
const SIRegisterInfo & getRegisterInfo() const override
Definition: SIInstrInfo.h:71
void splitSMRD(MachineInstr *MI, const TargetRegisterClass *HalfRC, unsigned HalfImmOp, unsigned HalfSGPROp, MachineInstr *&Lo, MachineInstr *&Hi) const
Split an SMRD instruction into two smaller loads of half the.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:138
bool isSOPP(uint16_t Opcode) const
Definition: SIInstrInfo.h:175
void moveToVALU(MachineInstr &MI) const
Replace this instruction's opcode with the equivalent VALU opcode.
bool isSALU(uint16_t Opcode) const
Definition: SIInstrInfo.h:151
bool isSOP2(uint16_t Opcode) const
Definition: SIInstrInfo.h:163
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:378
A debug info location.
Definition: DebugLoc.h:34
unsigned getMovOpcode(const TargetRegisterClass *DstRC) const
MachineInstr * commuteInstruction(MachineInstr *MI, bool NewMI=false) const override
bool hasModifiers(unsigned Opcode) const
Return true if this instruction has any modifiers.
bool isFLAT(uint16_t Opcode) const
Definition: SIInstrInfo.h:215
unsigned getSize() const
getSize - Return the size of the register in bytes, which is also the size of a stack slot allocated ...
bool verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const override
bool isVALU(uint16_t Opcode) const
Definition: SIInstrInfo.h:155
int getAtomicNoRetOp(uint16_t Opcode)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APInt.h:33
unsigned calculateLDSSpillAddress(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, RegScavenger *RS, unsigned TmpReg, unsigned Offset, unsigned Size) const
bool getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg, unsigned &Offset, const TargetRegisterInfo *TRI) const final
MachineOperand * getNamedOperand(MachineInstr &MI, unsigned OperandName) const
Returns the operand named Op.
Reg
All possible values of the reg field in the ModR/M byte.
int getCommuteOrig(uint16_t Opcode)
bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override
int getAtomicRetOp(uint16_t Opcode)
unsigned calculateIndirectAddress(unsigned RegIndex, unsigned Channel) const override
Calculate the "Indirect Address" for the given RegIndex and Channel.
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:68
int commuteOpcode(const MachineInstr &MI) const
unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const
This form should usually be preferred since it handles operands with unknown register classes...
Definition: SIInstrInfo.h:281
bool canReadVGPR(const MachineInstr &MI, unsigned OpNo) const
bool isImmOperandLegal(const MachineInstr *MI, unsigned OpNo, const MachineOperand &MO) const
SIInstrInfo(const AMDGPUSubtarget &st)
Definition: SIInstrInfo.cpp:30
const uint64_t RSRC_DATA_FORMAT
Definition: SIInstrInfo.h:369
bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override
const MachineOperand * getNamedOperand(const MachineInstr &MI, unsigned OpName) const
Definition: SIInstrInfo.h:350
bool isVOP3(uint16_t Opcode) const
Definition: SIInstrInfo.h:187
bool isSMRD(uint16_t Opcode) const
Definition: SIInstrInfo.h:203
bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
bundle_iterator< MachineInstr, instr_iterator > iterator
unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const
Return the size in bytes of the operand OpNo on the given.
Definition: SIInstrInfo.h:267
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool usesConstantBus(const MachineRegisterInfo &MRI, const MachineOperand &MO, unsigned OpSize) const
Returns true if this operand uses the constant bus.
bundle_iterator - MachineBasicBlock iterator that automatically skips over MIs that are inside bundle...
bool isMov(unsigned Opcode) const override
bool isSOPK(uint16_t Opcode) const
Definition: SIInstrInfo.h:171
uint64_t getDefaultRsrcDataFormat() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isLiteralConstant(const MachineOperand &MO, unsigned OpSize) const
int getVOPe32(uint16_t Opcode)
const uint64_t RSRC_TID_ENABLE
Definition: SIInstrInfo.h:370
bool isVOP1(uint16_t Opcode) const
Definition: SIInstrInfo.h:179
bool isInlineConstant(const APInt &Imm) const
void legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const
Legalize the OpIndex operand of this instruction by inserting a MOV.
bool isOperandLegal(const MachineInstr *MI, unsigned OpIdx, const MachineOperand *MO=nullptr) const
Check if MO is a legal operand if it was the OpIdx Operand for MI.
bool isWQM(uint16_t Opcode) const
Definition: SIInstrInfo.h:219
bool hasVALU32BitEncoding(unsigned Opcode) const
Return true if this 64-bit VALU instruction has a 32-bit encoding.
MachineOperand class - Representation of each machine instruction operand.
const TargetRegisterClass * getIndirectAddrRegClass() const override
bool isMIMG(uint16_t Opcode) const
Definition: SIInstrInfo.h:211
MachineInstr * convertToThreeAddress(MachineFunction::iterator &MBB, MachineBasicBlock::iterator &MI, LiveVariables *LV) const override
Represents one node in the SelectionDAG.
bool isDS(uint16_t Opcode) const
Definition: SIInstrInfo.h:207
bool isVOP2(uint16_t Opcode) const
Definition: SIInstrInfo.h:183
bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
Definition: SIInstrInfo.cpp:91
bool isSOP1(uint16_t Opcode) const
Definition: SIInstrInfo.h:159
Class for arbitrary precision integers.
Definition: APInt.h:73
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, unsigned Reg, MachineRegisterInfo *MRI) const final
void reserveIndirectRegisters(BitVector &Reserved, const MachineFunction &MF) const
Contains the definition of a TargetInstrInfo class that is common to all AMD GPUs.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
void moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const
Representation of each machine instruction.
Definition: MachineInstr.h:51
bool isVGPRSpill(uint16_t Opcode) const
Definition: SIInstrInfo.h:223
bool isMTBUF(uint16_t Opcode) const
Definition: SIInstrInfo.h:199
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:62
void legalizeOperands(MachineInstr *MI) const
Legalize all operands in this instruction.
#define I(x, y, z)
Definition: MD5.cpp:54
int getCommuteRev(uint16_t Opcode)
void LoadM0(MachineInstr *MoveRel, MachineBasicBlock::iterator I, unsigned SavReg, unsigned IndexReg) const
int getAddr64Inst(uint16_t Opcode)
static unsigned getVALUOp(const MachineInstr &MI)
bool isSALUOpSupportedOnVALU(const MachineInstr &MI) const
MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned ValueReg, unsigned Address, unsigned OffsetReg) const override
Build instruction(s) for an indirect register read.
bool isSOPC(uint16_t Opcode) const
Definition: SIInstrInfo.h:167
bool isTriviallyReMaterializable(const MachineInstr *MI, AliasAnalysis *AA=nullptr) const
bool hasModifiersSet(const MachineInstr &MI, unsigned OpName) const
bool areMemAccessesTriviallyDisjoint(MachineInstr *MIa, MachineInstr *MIb, AliasAnalysis *AA=nullptr) const override
unsigned getMachineCSELookAheadLimit() const override
Definition: SIInstrInfo.h:145
bool isVOPC(uint16_t Opcode) const
Definition: SIInstrInfo.h:191
BasicBlockListType::iterator iterator
const TargetRegisterClass * getOpRegClass(const MachineInstr &MI, unsigned OpNo) const
Return the correct register class for OpNo.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:40
MachineInstr * buildMovInstr(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned DstReg, unsigned SrcReg) const override
Build a MOV instruction.
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:56
void insertNOPs(MachineBasicBlock::iterator MI, int Count) const
bool isMUBUF(uint16_t Opcode) const
Definition: SIInstrInfo.h:195
bool isReallyTriviallyReMaterializable(const MachineInstr *MI, AliasAnalysis *AA) const override
Definition: SIInstrInfo.cpp:77