183 for (
MVT VT : ScalarIntVTs) {
207 assert(DstIdx != -1);
212 MI->
getOpcode() == AMDGPU::LDS_CMPST_RET)
224 case AMDGPU::CLAMP_R600: {
233 case AMDGPU::FABS_R600: {
242 case AMDGPU::FNEG_R600: {
251 case AMDGPU::MASK_WRITE: {
259 case AMDGPU::MOV_IMM_F32:
264 case AMDGPU::MOV_IMM_I32:
268 case AMDGPU::CONST_COPY: {
276 case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
277 case AMDGPU::RAT_WRITE_CACHELESS_64_eg:
278 case AMDGPU::RAT_WRITE_CACHELESS_128_eg: {
279 unsigned EOP = (std::next(I)->getOpcode() ==
AMDGPU::RETURN) ? 1 : 0;
294 unsigned SrcX = 0, SrcY = 1, SrcZ = 2, SrcW = 3;
295 unsigned CTX = 1, CTY = 1, CTZ = 1, CTW = 1;
389 case AMDGPU::TXD_SHADOW: {
395 unsigned SrcX = 0, SrcY = 1, SrcZ = 2, SrcW = 3;
396 unsigned CTX = 1, CTY = 1, CTZ = 1, CTW = 1;
496 case AMDGPU::BRANCH_COND_f32: {
499 AMDGPU::PREDICATE_BIT)
510 case AMDGPU::BRANCH_COND_i32: {
513 AMDGPU::PREDICATE_BIT)
524 case AMDGPU::EG_ExportSwz:
525 case AMDGPU::R600_ExportSwz: {
527 bool isLastInstructionOfItsType =
true;
530 EndBlock = BB->
end(); NextExportInst != EndBlock;
531 NextExportInst = std::next(NextExportInst)) {
532 if (NextExportInst->getOpcode() == AMDGPU::EG_ExportSwz ||
533 NextExportInst->getOpcode() == AMDGPU::R600_ExportSwz) {
534 unsigned CurrentInstExportType = NextExportInst->getOperand(1)
536 if (CurrentInstExportType == InstExportType) {
537 isLastInstructionOfItsType =
false;
543 if (!EOP && !isLastInstructionOfItsType)
545 unsigned CfInst = (MI->
getOpcode() == AMDGPU::EG_ExportSwz)? 84 : 40;
563 for (
unsigned i = 0, e = MFI->
LiveOuts.
size(); i != e; ++i)
590 case ISD::FSIN:
return LowerTrig(Op, DAG);
594 SDValue Result = LowerLOAD(Op, DAG);
597 "Load should return a value and a chain");
605 unsigned IntrinsicID =
606 cast<ConstantSDNode>(Op.
getOperand(1))->getZExtValue();
607 switch (IntrinsicID) {
608 case AMDGPUIntrinsic::AMDGPU_store_output: {
609 int64_t RegIndex = cast<ConstantSDNode>(Op.
getOperand(3))->getZExtValue();
610 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
614 case AMDGPUIntrinsic::R600_store_swizzle: {
636 unsigned IntrinsicID =
637 cast<ConstantSDNode>(Op.
getOperand(0))->getZExtValue();
640 switch(IntrinsicID) {
642 case AMDGPUIntrinsic::R600_load_input: {
643 int64_t RegIndex = cast<ConstantSDNode>(Op.
getOperand(1))->getZExtValue();
644 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
652 case AMDGPUIntrinsic::R600_interp_input: {
653 int slot = cast<ConstantSDNode>(Op.
getOperand(1))->getZExtValue();
654 int ijb = cast<ConstantSDNode>(Op.
getOperand(2))->getSExtValue();
667 unsigned RegisterI = AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb);
668 unsigned RegisterJ = AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb + 1);
679 RegisterJNode, RegisterINode);
683 RegisterJNode, RegisterINode);
684 return SDValue(interp, slot % 2);
686 case AMDGPUIntrinsic::R600_interp_xy:
687 case AMDGPUIntrinsic::R600_interp_zw: {
688 int slot = cast<ConstantSDNode>(Op.
getOperand(1))->getZExtValue();
693 if (IntrinsicID == AMDGPUIntrinsic::R600_interp_xy)
696 RegisterJNode, RegisterINode);
700 RegisterJNode, RegisterINode);
704 case AMDGPUIntrinsic::R600_tex:
705 case AMDGPUIntrinsic::R600_texc:
706 case AMDGPUIntrinsic::R600_txl:
707 case AMDGPUIntrinsic::R600_txlc:
708 case AMDGPUIntrinsic::R600_txb:
709 case AMDGPUIntrinsic::R600_txbc:
710 case AMDGPUIntrinsic::R600_txf:
711 case AMDGPUIntrinsic::R600_txq:
712 case AMDGPUIntrinsic::R600_ddx:
713 case AMDGPUIntrinsic::R600_ddy:
714 case AMDGPUIntrinsic::R600_ldptr: {
716 switch (IntrinsicID) {
717 case AMDGPUIntrinsic::R600_tex:
720 case AMDGPUIntrinsic::R600_texc:
723 case AMDGPUIntrinsic::R600_txl:
726 case AMDGPUIntrinsic::R600_txlc:
729 case AMDGPUIntrinsic::R600_txb:
732 case AMDGPUIntrinsic::R600_txbc:
735 case AMDGPUIntrinsic::R600_txf:
738 case AMDGPUIntrinsic::R600_txq:
741 case AMDGPUIntrinsic::R600_ddx:
744 case AMDGPUIntrinsic::R600_ddy:
747 case AMDGPUIntrinsic::R600_ldptr:
777 case AMDGPUIntrinsic::AMDGPU_dp4: {
799 case Intrinsic::r600_read_ngroups_x:
800 return LowerImplicitParameter(DAG, VT, DL, 0);
801 case Intrinsic::r600_read_ngroups_y:
802 return LowerImplicitParameter(DAG, VT, DL, 1);
803 case Intrinsic::r600_read_ngroups_z:
804 return LowerImplicitParameter(DAG, VT, DL, 2);
805 case Intrinsic::r600_read_global_size_x:
806 return LowerImplicitParameter(DAG, VT, DL, 3);
807 case Intrinsic::r600_read_global_size_y:
808 return LowerImplicitParameter(DAG, VT, DL, 4);
809 case Intrinsic::r600_read_global_size_z:
810 return LowerImplicitParameter(DAG, VT, DL, 5);
811 case Intrinsic::r600_read_local_size_x:
812 return LowerImplicitParameter(DAG, VT, DL, 6);
813 case Intrinsic::r600_read_local_size_y:
814 return LowerImplicitParameter(DAG, VT, DL, 7);
815 case Intrinsic::r600_read_local_size_z:
816 return LowerImplicitParameter(DAG, VT, DL, 8);
818 case Intrinsic::AMDGPU_read_workdim: {
820 return LowerImplicitParameter(DAG, VT, DL, ByteOffset / 4);
823 case Intrinsic::r600_read_tgid_x:
826 case Intrinsic::r600_read_tgid_y:
829 case Intrinsic::r600_read_tgid_z:
832 case Intrinsic::r600_read_tidig_x:
835 case Intrinsic::r600_read_tidig_y:
838 case Intrinsic::r600_read_tidig_z:
841 case Intrinsic::AMDGPU_rsq:
845 case AMDGPUIntrinsic::AMDGPU_fract:
846 case AMDGPUIntrinsic::AMDIL_fraction:
917 if (isa<ConstantSDNode>(Index) ||
921 Vector = vectorToVerticalVector(DAG, Vector);
933 if (isa<ConstantSDNode>(Index) ||
937 Vector = vectorToVerticalVector(DAG, Vector);
939 Vector, Value, Index);
940 return vectorToVerticalVector(DAG, Insert);
1050 unsigned mainop,
unsigned ovf)
const {
1080 unsigned DwordOffset)
const {
1081 unsigned ByteOffset = DwordOffset * 4;
1091 false,
false,
false, 0);
1094 bool R600TargetLowering::isZero(
SDValue Op)
const {
1096 return Cst->isNullValue();
1098 return CstFP->isZero();
1155 (CompareVT == VT || VT ==
MVT::i32)) {
1193 if (CompareVT != VT) {
1228 }
else if (CompareVT ==
MVT::i32) {
1252 unsigned StackWidth,
1255 switch(StackWidth) {
1273 void R600TargetLowering::getStackAddress(
unsigned StackWidth,
1276 unsigned &PtrIncr)
const {
1277 switch (StackWidth) {
1288 Channel = ElemIdx % 2;
1344 SDValue Args[3] = { Chain, Input, DWordAddr };
1381 Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG);
1388 assert(NumElemVT >= StackWidth &&
"Stack width cannot be greater than "
1389 "vector width in load");
1391 for (
unsigned i = 0; i < NumElemVT; ++i) {
1392 unsigned Channel, PtrIncr;
1393 getStackAddress(StackWidth, i, Channel, PtrIncr);
1418 switch (AddressSpace) {
1424 return 512 + 4096 * 2;
1426 return 512 + 4096 * 3;
1428 return 512 + 4096 * 4;
1430 return 512 + 4096 * 5;
1432 return 512 + 4096 * 6;
1434 return 512 + 4096 * 7;
1436 return 512 + 4096 * 8;
1438 return 512 + 4096 * 9;
1440 return 512 + 4096 * 10;
1442 return 512 + 4096 * 11;
1444 return 512 + 4096 * 12;
1446 return 512 + 4096 * 13;
1448 return 512 + 4096 * 14;
1450 return 512 + 4096 * 15;
1493 if (ConstantBlock > -1 &&
1499 isa<ConstantSDNode>(Ptr)) {
1501 for (
unsigned i = 0; i < 4; i++) {
1512 unsigned NumElements = 4;
1560 SDValue MergedValues[2] = { Res, Chain };
1574 Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG);
1581 assert(NumElemVT >= StackWidth &&
"Stack width cannot be greater than "
1582 "vector width in load");
1584 for (
unsigned i = 0; i < NumElemVT; ++i) {
1585 unsigned Channel, PtrIncr;
1586 getStackAddress(StackWidth, i, Channel, PtrIncr);
1594 for (
unsigned i = NumElemVT; i < 4; ++i) {
1645 for (
unsigned i = 0, e = Ins.
size(); i < e; ++i) {
1656 unsigned Reg = MF.addLiveIn(VA.
getLocReg(), &AMDGPU::R600_Reg128RegClass);
1694 MemVT,
false,
true,
true, 4);
1714 assert(RemapSwizzle.
empty());
1722 for (
unsigned i = 0; i < 4; i++) {
1727 RemapSwizzle[i] = 7;
1730 RemapSwizzle[i] = 4;
1732 }
else if (
C->isExactlyValue(1.0)) {
1733 RemapSwizzle[i] = 5;
1740 for (
unsigned j = 0; j < i; j++) {
1741 if (NewBldVec[i] == NewBldVec[j]) {
1743 RemapSwizzle[i] = j;
1756 assert(RemapSwizzle.
empty());
1763 bool isUnmovable[4] = {
false,
false,
false,
false };
1764 for (
unsigned i = 0; i < 4; i++) {
1765 RemapSwizzle[i] = i;
1770 isUnmovable[Idx] =
true;
1774 for (
unsigned i = 0; i < 4; i++) {
1778 if (isUnmovable[Idx])
1781 std::swap(NewBldVec[Idx], NewBldVec[i]);
1782 std::swap(RemapSwizzle[i], RemapSwizzle[Idx]);
1800 for (
unsigned i = 0; i < 4; i++) {
1801 unsigned Idx = cast<ConstantSDNode>(Swz[i])->getZExtValue();
1802 if (SwizzleRemap.find(Idx) != SwizzleRemap.end())
1806 SwizzleRemap.clear();
1808 for (
unsigned i = 0; i < 4; i++) {
1809 unsigned Idx = cast<ConstantSDNode>(Swz[i])->getZExtValue();
1810 if (SwizzleRemap.find(Idx) != SwizzleRemap.end())
1887 if (!isa<ConstantSDNode>(EltNo))
1889 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
1906 if (Elt < Ops.
size()) {
1909 EVT OpVT = Ops[0].getValueType();
1927 unsigned Element = Const->getZExtValue();
1934 unsigned Element = Const->getZExtValue();
2005 NewArgs[1] = OptimizeSwizzle(N->
getOperand(1), &NewArgs[4], DAG,
DL);
2035 NewArgs[1] = OptimizeSwizzle(N->
getOperand(1), &NewArgs[2], DAG,
DL);
2051 case AMDGPU::FNEG_R600:
2057 case AMDGPU::FABS_R600:
2063 case AMDGPU::CONST_COPY: {
2065 bool HasDst = TII->
getOperandIdx(Opcode, AMDGPU::OpName::dst) > -1;
2075 int SrcIndices[] = {
2088 std::vector<unsigned> Consts;
2089 for (
int OtherSrcIdx : SrcIndices) {
2090 int OtherSelIdx = TII->
getSelIdx(Opcode, OtherSrcIdx);
2091 if (OtherSrcIdx < 0 || OtherSelIdx < 0)
2098 dyn_cast<RegisterSDNode>(ParentNode->
getOperand(OtherSrcIdx))) {
2099 if (
Reg->getReg() == AMDGPU::ALU_CONST) {
2101 = cast<ConstantSDNode>(ParentNode->
getOperand(OtherSelIdx));
2117 case AMDGPU::MOV_IMM_I32:
2118 case AMDGPU::MOV_IMM_F32: {
2119 unsigned ImmReg = AMDGPU::ALU_LITERAL_X;
2120 uint64_t ImmValue = 0;
2126 if (FloatValue == 0.0) {
2127 ImmReg = AMDGPU::ZERO;
2128 }
else if (FloatValue == 0.5) {
2129 ImmReg = AMDGPU::HALF;
2130 }
else if (FloatValue == 1.0) {
2131 ImmReg = AMDGPU::ONE;
2139 ImmReg = AMDGPU::ZERO;
2140 }
else if (Value == 1) {
2141 ImmReg = AMDGPU::ONE_INT;
2150 if (ImmReg == AMDGPU::ALU_LITERAL_X) {
2180 if (Opcode == AMDGPU::DOT_4) {
2181 int OperandIdx[] = {
2211 for (
unsigned i = 0; i < 8; i++) {
2212 if (OperandIdx[i] < 0)
2214 SDValue &Src = Ops[OperandIdx[i] - 1];
2215 SDValue &Neg = Ops[NegIdx[i] - 1];
2216 SDValue &Abs = Ops[AbsIdx[i] - 1];
2217 bool HasDst = TII->
getOperandIdx(Opcode, AMDGPU::OpName::dst) > -1;
2218 int SelIdx = TII->
getSelIdx(Opcode, OperandIdx[i]);
2221 SDValue &Sel = (SelIdx > -1) ? Ops[SelIdx] : FakeOp;
2222 if (
FoldOperand(Node, i, Src, Neg, Abs, Sel, FakeOp, DAG))
2226 for (
unsigned i = 1, e = Node->
getNumOperands(); i < e; i += 2) {
2228 if (
FoldOperand(Node, i, Src, FakeOp, FakeOp, FakeOp, FakeOp, DAG))
2231 }
else if (Opcode == AMDGPU::CLAMP_R600) {
2237 AMDGPU::OpName::clamp);
2248 int OperandIdx[] = {
2263 for (
unsigned i = 0; i < 3; i++) {
2264 if (OperandIdx[i] < 0)
2266 SDValue &Src = Ops[OperandIdx[i] - 1];
2267 SDValue &Neg = Ops[NegIdx[i] - 1];
2269 SDValue &Abs = (AbsIdx[i] > -1) ? Ops[AbsIdx[i] - 1] : FakeAbs;
2270 bool HasDst = TII->
getOperandIdx(Opcode, AMDGPU::OpName::dst) > -1;
2271 int SelIdx = TII->
getSelIdx(Opcode, OperandIdx[i]);
2272 int ImmIdx = TII->
getOperandIdx(Opcode, AMDGPU::OpName::literal);
2277 SDValue &Sel = (SelIdx > -1) ? Ops[SelIdx] : FakeOp;
2279 if (
FoldOperand(Node, i, Src, Neg, Abs, Sel, Imm, DAG))
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
static SDValue CompactSwizzlableVector(SelectionDAG &DAG, SDValue VectorEntry, DenseMap< unsigned, unsigned > &RemapSwizzle)
void push_back(const T &Elt)
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
A parsed version of the target data layout string in and methods for querying it. ...
SDValue getValue(unsigned R) const
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
void setImmOperand(MachineInstr *MI, unsigned Op, int64_t Imm) const
Helper function for setting instruction flag values.
LLVMContext * getContext() const
SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N)
AMDGPU specific subclass of TargetSubtarget.
uint64_t getZExtValue() const
Get zero extended value.
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG, SmallVectorImpl< SDValue > &Results) const
BR_CC - Conditional branch.
Interface definition for R600InstrInfo.
const ConstantFP * getFPImm() const
SmallVector< unsigned, 4 > LiveOuts
void AnalyzeFormalArguments(CCState &State, const SmallVectorImpl< ISD::InputArg > &Ins) const
SDVTList getVTList() const
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, SelectionDAG &DAG) const
SDValue getMergeValues(ArrayRef< SDValue > Ops, SDLoc dl)
Create a MERGE_VALUES node from the given operands.
Carry-setting nodes for multiple precision addition and subtraction.
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
const TargetSubtargetInfo & getSubtarget() const
static PointerType * get(Type *ElementType, unsigned AddressSpace)
PointerType::get - This constructs a pointer to an object of the specified type in a numbered address...
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
SDValue getSelectCC(SDLoc DL, SDValue LHS, SDValue RHS, SDValue True, SDValue False, ISD::CondCode Cond)
Helper function to make it easier to build SelectCC's if you just have an ISD::CondCode instead of an...
Type * getTypeForEVT(LLVMContext &Context) const
getTypeForEVT - This method returns an LLVM type corresponding to the specified EVT.
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
unsigned getNumOperands() const
Return the number of values used by this operation.
#define OPCODE_IS_NOT_ZERO_INT
const SDValue & getOperand(unsigned Num) const
Address space for local memory.
bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const
Expand float(f32) to SINT(i64) conversion.
const SDValue & getBasePtr() const
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
const R600RegisterInfo & getRegisterInfo() const override
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
bool isVector() const
isVector - Return true if this is a vector value type.
SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
const HexagonInstrInfo * TII
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Shift and rotation operations.
unsigned getShaderType() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
MachineFunction & getMachineFunction() const
int getLDSNoRetOp(uint16_t Opcode)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
virtual SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const
Helper function that adds Reg to the LiveIn list of the DAG's MachineFunction.
const AMDGPUInstrInfo * getInstrInfo() const override
Reg
All possible values of the reg field in the ModR/M byte.
void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn't supported on the target and indicate what to d...
MachineInstr * buildMovImm(MachineBasicBlock &BB, MachineBasicBlock::iterator I, unsigned DstReg, uint64_t Imm) const
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
unsigned getMachineOpcode() const
bool bitsGE(EVT VT) const
bitsGE - Return true if this has no less bits than VT.
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
Interface to describe a layout of a stack frame on a AMDIL target machine.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
bool hasInstrModifiers(unsigned Opcode) const
EVT getVectorElementType() const
getVectorElementType - Given a vector type, return the type of each element.
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
load Combine Adjacent Loads
unsigned getLocReg() const
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
const AMDGPUSubtarget * Subtarget
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
#define OPCODE_IS_NOT_ZERO
Simple integer binary arithmetic operators.
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
EVT getMemoryVT() const
Return the type of the in-memory value.
R600TargetLowering(TargetMachine &TM, const AMDGPUSubtarget &STI)
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
const DataLayout & getDataLayout() const
bool bitsLE(EVT VT) const
bitsLE - Return true if this has no more bits than VT.
PointerType - Class to represent pointers.
bool isHWTrueValue(SDValue Op) const
UNDEF - An undefined node.
This class is used to represent ISD::STORE nodes.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
This node is for VLIW targets and it is used to represent a vector that is stored in consecutive regi...
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable...
SDNode * getNode() const
get the SDNode which holds the desired result
bundle_iterator< MachineInstr, instr_iterator > iterator
unsigned getScalarSizeInBits() const
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
static ConstantPointerNull * get(PointerType *T)
get() - Static factory methods - Return objects of the specified value
MVT - Machine Value Type.
const SDValue & getOperand(unsigned i) const
This is an important class for using LLVM in a threaded context.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
Address space for constant memory.
Simple binary floating point operators.
void setTargetDAGCombine(ISD::NodeType NT)
Targets should invoke this method for each target independent node that they want to provide a custom...
bool isNonTemporal() const
static int ConstantAddressBlock(unsigned AddressSpace)
Address space for private memory.
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
DebugLoc findDebugLoc(instr_iterator MBBI)
findDebugLoc - find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE instructions...
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL...
const MachineOperand & getOperand(unsigned i) const
unsigned getSubRegFromChannel(unsigned Channel) const
bool isBeforeLegalizeOps() const
Carry-using nodes for multiple precision addition and subtraction.
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT)
SDValue getTargetConstant(uint64_t Val, SDLoc DL, EVT VT, bool isOpaque=false)
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
unsigned getOpcode() const
int getOperandIdx(const MachineInstr &MI, unsigned Op) const
Get the index of Op in the MachineInstr.
CondCode getSetCCSwappedOperands(CondCode Operation)
getSetCCSwappedOperands - Return the operation corresponding to (Y op X) when given the operation for...
SDValue ScalarizeVectorLoad(SDValue Op, SelectionDAG &DAG) const
Split a vector load into a scalar load of each component.
SDValue getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes())
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
void append(in_iter in_start, in_iter in_end)
Add the specified range to the end of the SmallVector.
EVT - Extended Value Type.
static UndefValue * get(Type *T)
get() - Static factory methods - Return an 'undef' object of the specified type.
const APFloat & getValueAPF() const
bool isHWFalseValue(SDValue Op) const
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements)
getVectorVT - Returns the EVT that represents a vector NumElements in length, where each element is o...
MachinePointerInfo - This class contains a discriminated union of information about pointers in memor...
Value * GetUnderlyingObject(Value *V, const DataLayout &DL, unsigned MaxLookup=6)
GetUnderlyingObject - This method strips off any GEP address adjustments and pointer casts from the s...
static SDValue ReorganizeVector(SelectionDAG &DAG, SDValue VectorEntry, DenseMap< unsigned, unsigned > &RemapSwizzle)
const MachinePointerInfo & getPointerInfo() const
static bool FoldOperand(SDNode *ParentNode, unsigned SrcIdx, SDValue &Src, SDValue &Neg, SDValue &Abs, SDValue &Sel, SDValue &Imm, SelectionDAG &DAG)
REG_SEQUENCE - This variadic instruction is used to form a register that represents a consecutive seq...
bool bitsGT(EVT VT) const
bitsGT - Return true if this has more bits than VT.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
TokenFactor - This node takes multiple tokens as input and produces a single token result...
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
virtual MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
CCState - This class holds information needed while lowering arguments and return values...
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
CCValAssign - Represent assignment of one arg/retval to a location.
BRCOND - Conditional branch.
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
An SDNode that represents everything that will be needed to construct a MachineInstr.
const SDValue & getChain() const
Promote Memory to Register
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
bool isMachineOpcode() const
unsigned getStackWidth(const MachineFunction &MF) const
Represents one node in the SelectionDAG.
CondCode getSetCCInverse(CondCode Operation, bool isInteger)
getSetCCInverse - Return the operation corresponding to !(X op Y), where 'op' is a valid SetCC operat...
static mvt_range integer_valuetypes()
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
const Value * getValue() const
getValue - Return the base address of the memory access.
Select(COND, TRUEVAL, FALSEVAL).
Interface for the AMDGPU Implementation of the Intrinsic Info class.
op_iterator op_begin() const
ZERO_EXTEND - Used for integer types, zeroing the new bits.
APInt bitcastToAPInt() const
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
ANY_EXTEND - Used for integer types. The high bits are undefined.
const AMDGPUFrameLowering * getFrameLowering() const override
int getSelIdx(unsigned Opcode, unsigned SrcIdx) const
unsigned getAddressSpace() const
Return the address space for the associated pointer.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
void addFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const
Add one of the MO_FLAG* flags to the specified Operand.
MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned Opcode, unsigned DstReg, unsigned Src0Reg, unsigned Src1Reg=0) const
buildDefaultInstruction - This function returns a MachineInstr with all the instruction modifiers ini...
Bitwise operators - logical and, logical or, logical xor.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
R600 DAG Lowering interface definition.
unsigned ABIArgOffset
Start of implicit kernel args.
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Information about the stack frame layout on the AMDGPU targets.
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
bool isIndexed() const
Return true if this is a pre/post inc/dec load/store.
float convertToFloat() const
op_iterator op_end() const
MachineSDNode * getMachineNode(unsigned Opcode, SDLoc dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s), MachineInstr opcode, and operands.
SDValue CombineFMinMaxLegacy(SDLoc DL, EVT VT, SDValue LHS, SDValue RHS, SDValue True, SDValue False, SDValue CC, DAGCombinerInfo &DCI) const
Generate Min/Max node.
bool isInt< 16 >(int64_t x)
EVT getValueType() const
Return the ValueType of the referenced return value.
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
SDValue getCondCode(ISD::CondCode Cond)
SDValue getConstant(uint64_t Val, SDLoc DL, EVT VT, bool isTarget=false, bool isOpaque=false)
const APFloat & getValueAPF() const
void getOriginalFunctionArgs(SelectionDAG &DAG, const Function *F, const SmallVectorImpl< ISD::InputArg > &Ins, SmallVectorImpl< ISD::InputArg > &OrigIns) const
The SelectionDAGBuilder will automatically promote function arguments with illegal types...
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
unsigned getReg() const
getReg - Returns the register number.
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
SDValue getTargetExtractSubreg(int SRIdx, SDLoc DL, EVT VT, SDValue Operand)
A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG nodes.
SDValue getZExtOrTrunc(SDValue Op, SDLoc DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either zero-extending or trunca...
virtual const TargetInstrInfo * getInstrInfo() const
LLVM Value Representation.
SDValue getRegister(unsigned Reg, EVT VT)
bool isTruncatingStore() const
Return true if the op does a truncation before store.
SDValue getValueType(EVT)
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
Primary interface to the complete machine description for the target machine.
SetCC operator - This evaluates to a true value iff the condition is true.
unsigned getImplicitParameterOffset(const AMDGPUMachineFunction *MFI, const ImplicitParameter Param) const
Helper function that returns the byte offset of the given type of implicit parameter.
SDValue getConstantFP(double Val, SDLoc DL, EVT VT, bool isTarget=false)
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
unsigned getLocMemOffset() const
bool fitsConstReadLimitations(const std::vector< MachineInstr * > &) const
An instruction group can only access 2 channel pair (either [XY] or [ZW]) from KCache bank on R700+...
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
bool isLDSRetInstr(unsigned Opcode) const
SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const
TRUNCATE - Completely drop the high bits.
unsigned getAlignment() const
bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const
Return true if the specified condition code is legal on this target.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &, EVT VT) const override
Return the ValueType of the result of SETCC operations.
FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2, FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR - Perform various unary floating point operations.
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, SDLoc DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
XXX Only kernel functions are supported, so we can assume for now that every function is a kernel fun...
MVT getVectorIdxTy(const DataLayout &) const override
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
EVT changeVectorElementTypeToInteger() const
changeVectorElementTypeToInteger - Return a vector with the same number of elements as this vector...
MVT getSimpleVT() const
getSimpleVT - Return the SimpleValueType held in the specified simple EVT.
SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const
SDValue getMemIntrinsicNode(unsigned Opcode, SDLoc dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, unsigned Align=0, bool Vol=false, bool ReadMem=true, bool WriteMem=true, unsigned Size=0)
Creates a MemIntrinsicNode that may produce a result and takes a list of operands.
bool isMachineOpcode() const
Test if this node has a post-isel opcode, directly corresponding to a MachineInstr opcode...
unsigned getMachineOpcode() const
This may only be called if isMachineOpcode returns true.
bool use_empty(unsigned RegNo) const
use_empty - Return true if there are no instructions using the specified register.
const AMDGPURegisterInfo * getRegisterInfo() const override
Address space for global memory (RAT0, VTX0).
uint64_t getZExtValue() const
unsigned getVectorNumElements() const
getVectorNumElements - Given a vector type, return the number of elements it contains.
This class is used to represent ISD::LOAD nodes.