LLVM  3.7.0
PPCRegisterInfo.cpp
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1 //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the PowerPC implementation of the TargetRegisterInfo
11 // class.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "PPCRegisterInfo.h"
16 #include "PPC.h"
17 #include "PPCFrameLowering.h"
18 #include "PPCInstrBuilder.h"
19 #include "PPCMachineFunctionInfo.h"
20 #include "PPCSubtarget.h"
21 #include "PPCTargetMachine.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/STLExtras.h"
30 #include "llvm/IR/CallingConv.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/Type.h"
35 #include "llvm/Support/Debug.h"
43 #include <cstdlib>
44 
45 using namespace llvm;
46 
47 #define DEBUG_TYPE "reginfo"
48 
49 #define GET_REGINFO_TARGET_DESC
50 #include "PPCGenRegisterInfo.inc"
51 
52 static cl::opt<bool>
53 EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(true),
54  cl::desc("Enable use of a base pointer for complex stack frames"));
55 
56 static cl::opt<bool>
57 AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(false),
58  cl::desc("Force the use of a base pointer in every function"));
59 
61  : PPCGenRegisterInfo(TM.isPPC64() ? PPC::LR8 : PPC::LR,
62  TM.isPPC64() ? 0 : 1,
63  TM.isPPC64() ? 0 : 1),
64  TM(TM) {
65  ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
66  ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
67  ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
68  ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
69  ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
70  ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
71  ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
72  ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
73  ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32;
74 
75  // 64-bit
76  ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
77  ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
78  ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
79  ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
80  ImmToIdxMap[PPC::ADDI8] = PPC::ADD8;
81 }
82 
83 /// getPointerRegClass - Return the register class to use to hold pointers.
84 /// This is used for addressing modes.
85 const TargetRegisterClass *
87  const {
88  // Note that PPCInstrInfo::FoldImmediate also directly uses this Kind value
89  // when it checks for ZERO folding.
90  if (Kind == 1) {
91  if (TM.isPPC64())
92  return &PPC::G8RC_NOX0RegClass;
93  return &PPC::GPRC_NOR0RegClass;
94  }
95 
96  if (TM.isPPC64())
97  return &PPC::G8RCRegClass;
98  return &PPC::GPRCRegClass;
99 }
100 
101 const MCPhysReg*
103  const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>();
105  if (Subtarget.hasVSX())
106  return CSR_64_AllRegs_VSX_SaveList;
107  if (Subtarget.hasAltivec())
108  return CSR_64_AllRegs_Altivec_SaveList;
109  return CSR_64_AllRegs_SaveList;
110  }
111 
112  if (Subtarget.isDarwinABI())
113  return TM.isPPC64()
114  ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_SaveList
115  : CSR_Darwin64_SaveList)
116  : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_SaveList
117  : CSR_Darwin32_SaveList);
118 
119  // On PPC64, we might need to save r2 (but only if it is not reserved).
120  bool SaveR2 = MF->getRegInfo().isAllocatable(PPC::X2);
121 
122  return TM.isPPC64()
123  ? (Subtarget.hasAltivec()
124  ? (SaveR2 ? CSR_SVR464_R2_Altivec_SaveList
125  : CSR_SVR464_Altivec_SaveList)
126  : (SaveR2 ? CSR_SVR464_R2_SaveList : CSR_SVR464_SaveList))
127  : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_SaveList
128  : CSR_SVR432_SaveList);
129 }
130 
131 const uint32_t *
133  CallingConv::ID CC) const {
134  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
135  if (CC == CallingConv::AnyReg) {
136  if (Subtarget.hasVSX())
137  return CSR_64_AllRegs_VSX_RegMask;
138  if (Subtarget.hasAltivec())
139  return CSR_64_AllRegs_Altivec_RegMask;
140  return CSR_64_AllRegs_RegMask;
141  }
142 
143  if (Subtarget.isDarwinABI())
144  return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_RegMask
145  : CSR_Darwin64_RegMask)
146  : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_RegMask
147  : CSR_Darwin32_RegMask);
148 
149  return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR464_Altivec_RegMask
150  : CSR_SVR464_RegMask)
151  : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_RegMask
152  : CSR_SVR432_RegMask);
153 }
154 
155 const uint32_t*
157  return CSR_NoRegs_RegMask;
158 }
159 
160 void PPCRegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const {
161  for (unsigned PseudoReg : {PPC::ZERO, PPC::ZERO8, PPC::RM})
162  Mask[PseudoReg / 32] &= ~(1u << (PseudoReg % 32));
163 }
164 
166  BitVector Reserved(getNumRegs());
167  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
168  const PPCFrameLowering *TFI = getFrameLowering(MF);
169 
170  // The ZERO register is not really a register, but the representation of r0
171  // when used in instructions that treat r0 as the constant 0.
172  Reserved.set(PPC::ZERO);
173  Reserved.set(PPC::ZERO8);
174 
175  // The FP register is also not really a register, but is the representation
176  // of the frame pointer register used by ISD::FRAMEADDR.
177  Reserved.set(PPC::FP);
178  Reserved.set(PPC::FP8);
179 
180  // The BP register is also not really a register, but is the representation
181  // of the base pointer register used by setjmp.
182  Reserved.set(PPC::BP);
183  Reserved.set(PPC::BP8);
184 
185  // The counter registers must be reserved so that counter-based loops can
186  // be correctly formed (and the mtctr instructions are not DCE'd).
187  Reserved.set(PPC::CTR);
188  Reserved.set(PPC::CTR8);
189 
190  Reserved.set(PPC::R1);
191  Reserved.set(PPC::LR);
192  Reserved.set(PPC::LR8);
193  Reserved.set(PPC::RM);
194 
195  if (!Subtarget.isDarwinABI() || !Subtarget.hasAltivec())
196  Reserved.set(PPC::VRSAVE);
197 
198  // The SVR4 ABI reserves r2 and r13
199  if (Subtarget.isSVR4ABI()) {
200  Reserved.set(PPC::R2); // System-reserved register
201  Reserved.set(PPC::R13); // Small Data Area pointer register
202  }
203 
204  // On PPC64, r13 is the thread pointer. Never allocate this register.
205  if (TM.isPPC64()) {
206  Reserved.set(PPC::R13);
207 
208  Reserved.set(PPC::X1);
209  Reserved.set(PPC::X13);
210 
211  if (TFI->needsFP(MF))
212  Reserved.set(PPC::X31);
213 
214  if (hasBasePointer(MF))
215  Reserved.set(PPC::X30);
216 
217  // The 64-bit SVR4 ABI reserves r2 for the TOC pointer.
218  if (Subtarget.isSVR4ABI()) {
219  // We only reserve r2 if we need to use the TOC pointer. If we have no
220  // explicit uses of the TOC pointer (meaning we're a leaf function with
221  // no constant-pool loads, etc.) and we have no potential uses inside an
222  // inline asm block, then we can treat r2 has an ordinary callee-saved
223  // register.
224  const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
225  if (FuncInfo->usesTOCBasePtr() || MF.hasInlineAsm())
226  Reserved.set(PPC::X2);
227  else
228  Reserved.reset(PPC::R2);
229  }
230  }
231 
232  if (TFI->needsFP(MF))
233  Reserved.set(PPC::R31);
234 
235  if (hasBasePointer(MF)) {
236  if (Subtarget.isSVR4ABI() && !TM.isPPC64() &&
238  Reserved.set(PPC::R29);
239  else
240  Reserved.set(PPC::R30);
241  }
242 
243  if (Subtarget.isSVR4ABI() && !TM.isPPC64() &&
245  Reserved.set(PPC::R30);
246 
247  // Reserve Altivec registers when Altivec is unavailable.
248  if (!Subtarget.hasAltivec())
249  for (TargetRegisterClass::iterator I = PPC::VRRCRegClass.begin(),
250  IE = PPC::VRRCRegClass.end(); I != IE; ++I)
251  Reserved.set(*I);
252 
253  return Reserved;
254 }
255 
257  MachineFunction &MF) const {
258  const PPCFrameLowering *TFI = getFrameLowering(MF);
259  const unsigned DefaultSafety = 1;
260 
261  switch (RC->getID()) {
262  default:
263  return 0;
264  case PPC::G8RC_NOX0RegClassID:
265  case PPC::GPRC_NOR0RegClassID:
266  case PPC::G8RCRegClassID:
267  case PPC::GPRCRegClassID: {
268  unsigned FP = TFI->hasFP(MF) ? 1 : 0;
269  return 32 - FP - DefaultSafety;
270  }
271  case PPC::F8RCRegClassID:
272  case PPC::F4RCRegClassID:
273  case PPC::QFRCRegClassID:
274  case PPC::QSRCRegClassID:
275  case PPC::QBRCRegClassID:
276  case PPC::VRRCRegClassID:
277  case PPC::VFRCRegClassID:
278  case PPC::VSLRCRegClassID:
279  case PPC::VSHRCRegClassID:
280  return 32 - DefaultSafety;
281  case PPC::VSRCRegClassID:
282  case PPC::VSFRCRegClassID:
283  case PPC::VSSRCRegClassID:
284  return 64 - DefaultSafety;
285  case PPC::CRRCRegClassID:
286  return 8 - DefaultSafety;
287  }
288 }
289 
290 const TargetRegisterClass *
292  const MachineFunction &MF) const {
293  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
294  if (Subtarget.hasVSX()) {
295  // With VSX, we can inflate various sub-register classes to the full VSX
296  // register set.
297 
298  if (RC == &PPC::F8RCRegClass)
299  return &PPC::VSFRCRegClass;
300  else if (RC == &PPC::VRRCRegClass)
301  return &PPC::VSRCRegClass;
302  else if (RC == &PPC::F4RCRegClass && Subtarget.hasP8Vector())
303  return &PPC::VSSRCRegClass;
304  }
305 
307 }
308 
309 //===----------------------------------------------------------------------===//
310 // Stack Frame Processing methods
311 //===----------------------------------------------------------------------===//
312 
313 /// lowerDynamicAlloc - Generate the code for allocating an object in the
314 /// current frame. The sequence of code with be in the general form
315 ///
316 /// addi R0, SP, \#frameSize ; get the address of the previous frame
317 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
318 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation
319 ///
321  // Get the instruction.
322  MachineInstr &MI = *II;
323  // Get the instruction's basic block.
324  MachineBasicBlock &MBB = *MI.getParent();
325  // Get the basic block's function.
326  MachineFunction &MF = *MBB.getParent();
327  // Get the frame info.
328  MachineFrameInfo *MFI = MF.getFrameInfo();
329  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
330  // Get the instruction info.
331  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
332  // Determine whether 64-bit pointers are used.
333  bool LP64 = TM.isPPC64();
334  DebugLoc dl = MI.getDebugLoc();
335 
336  // Get the maximum call stack size.
337  unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
338  // Get the total frame size.
339  unsigned FrameSize = MFI->getStackSize();
340 
341  // Get stack alignments.
342  const PPCFrameLowering *TFI = getFrameLowering(MF);
343  unsigned TargetAlign = TFI->getStackAlignment();
344  unsigned MaxAlign = MFI->getMaxAlignment();
345  assert((maxCallFrameSize & (MaxAlign-1)) == 0 &&
346  "Maximum call-frame size not sufficiently aligned");
347 
348  // Determine the previous frame's address. If FrameSize can't be
349  // represented as 16 bits or we need special alignment, then we load the
350  // previous frame's address from 0(SP). Why not do an addis of the hi?
351  // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
352  // Constructing the constant and adding would take 3 instructions.
353  // Fortunately, a frame greater than 32K is rare.
354  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
355  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
356  unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
357 
358  if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) {
359  BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
360  .addReg(PPC::R31)
361  .addImm(FrameSize);
362  } else if (LP64) {
363  BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
364  .addImm(0)
365  .addReg(PPC::X1);
366  } else {
367  BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
368  .addImm(0)
369  .addReg(PPC::R1);
370  }
371 
372  bool KillNegSizeReg = MI.getOperand(1).isKill();
373  unsigned NegSizeReg = MI.getOperand(1).getReg();
374 
375  // Grow the stack and update the stack pointer link, then determine the
376  // address of new allocated space.
377  if (LP64) {
378  if (MaxAlign > TargetAlign) {
379  unsigned UnalNegSizeReg = NegSizeReg;
380  NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
381 
382  // Unfortunately, there is no andi, only andi., and we can't insert that
383  // here because we might clobber cr0 while it is live.
384  BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg)
385  .addImm(~(MaxAlign-1));
386 
387  unsigned NegSizeReg1 = NegSizeReg;
388  NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
389  BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg)
390  .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
391  .addReg(NegSizeReg1, RegState::Kill);
392  KillNegSizeReg = true;
393  }
394 
395  BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1)
396  .addReg(Reg, RegState::Kill)
397  .addReg(PPC::X1)
398  .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
399  BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
400  .addReg(PPC::X1)
401  .addImm(maxCallFrameSize);
402  } else {
403  if (MaxAlign > TargetAlign) {
404  unsigned UnalNegSizeReg = NegSizeReg;
405  NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
406 
407  // Unfortunately, there is no andi, only andi., and we can't insert that
408  // here because we might clobber cr0 while it is live.
409  BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg)
410  .addImm(~(MaxAlign-1));
411 
412  unsigned NegSizeReg1 = NegSizeReg;
413  NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
414  BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg)
415  .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
416  .addReg(NegSizeReg1, RegState::Kill);
417  KillNegSizeReg = true;
418  }
419 
420  BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1)
421  .addReg(Reg, RegState::Kill)
422  .addReg(PPC::R1)
423  .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
424  BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
425  .addReg(PPC::R1)
426  .addImm(maxCallFrameSize);
427  }
428 
429  // Discard the DYNALLOC instruction.
430  MBB.erase(II);
431 }
432 
433 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
434 /// reserving a whole register (R0), we scrounge for one here. This generates
435 /// code like this:
436 ///
437 /// mfcr rA ; Move the conditional register into GPR rA.
438 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
439 /// stw rA, FI ; Store rA to the frame.
440 ///
442  unsigned FrameIndex) const {
443  // Get the instruction.
444  MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>
445  // Get the instruction's basic block.
446  MachineBasicBlock &MBB = *MI.getParent();
447  MachineFunction &MF = *MBB.getParent();
448  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
449  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
450  DebugLoc dl = MI.getDebugLoc();
451 
452  bool LP64 = TM.isPPC64();
453  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
454  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
455 
456  unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
457  unsigned SrcReg = MI.getOperand(0).getReg();
458 
459  // We need to store the CR in the low 4-bits of the saved value. First, issue
460  // an MFOCRF to save all of the CRBits and, if needed, kill the SrcReg.
461  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg)
462  .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
463 
464  // If the saved register wasn't CR0, shift the bits left so that they are in
465  // CR0's slot.
466  if (SrcReg != PPC::CR0) {
467  unsigned Reg1 = Reg;
468  Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
469 
470  // rlwinm rA, rA, ShiftBits, 0, 31.
471  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
472  .addReg(Reg1, RegState::Kill)
473  .addImm(getEncodingValue(SrcReg) * 4)
474  .addImm(0)
475  .addImm(31);
476  }
477 
478  addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
479  .addReg(Reg, RegState::Kill),
480  FrameIndex);
481 
482  // Discard the pseudo instruction.
483  MBB.erase(II);
484 }
485 
487  unsigned FrameIndex) const {
488  // Get the instruction.
489  MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset>
490  // Get the instruction's basic block.
491  MachineBasicBlock &MBB = *MI.getParent();
492  MachineFunction &MF = *MBB.getParent();
493  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
494  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
495  DebugLoc dl = MI.getDebugLoc();
496 
497  bool LP64 = TM.isPPC64();
498  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
499  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
500 
501  unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
502  unsigned DestReg = MI.getOperand(0).getReg();
503  assert(MI.definesRegister(DestReg) &&
504  "RESTORE_CR does not define its destination");
505 
506  addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
507  Reg), FrameIndex);
508 
509  // If the reloaded register isn't CR0, shift the bits right so that they are
510  // in the right CR's slot.
511  if (DestReg != PPC::CR0) {
512  unsigned Reg1 = Reg;
513  Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
514 
515  unsigned ShiftBits = getEncodingValue(DestReg)*4;
516  // rlwinm r11, r11, 32-ShiftBits, 0, 31.
517  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
518  .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0)
519  .addImm(31);
520  }
521 
522  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg)
523  .addReg(Reg, RegState::Kill);
524 
525  // Discard the pseudo instruction.
526  MBB.erase(II);
527 }
528 
530  unsigned FrameIndex) const {
531  // Get the instruction.
532  MachineInstr &MI = *II; // ; SPILL_CRBIT <SrcReg>, <offset>
533  // Get the instruction's basic block.
534  MachineBasicBlock &MBB = *MI.getParent();
535  MachineFunction &MF = *MBB.getParent();
536  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
537  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
538  DebugLoc dl = MI.getDebugLoc();
539 
540  bool LP64 = TM.isPPC64();
541  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
542  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
543 
544  unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
545  unsigned SrcReg = MI.getOperand(0).getReg();
546 
547  BuildMI(MBB, II, dl, TII.get(TargetOpcode::KILL),
548  getCRFromCRBit(SrcReg))
549  .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
550 
551  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg)
552  .addReg(getCRFromCRBit(SrcReg));
553 
554  // If the saved register wasn't CR0LT, shift the bits left so that the bit to
555  // store is the first one. Mask all but that bit.
556  unsigned Reg1 = Reg;
557  Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
558 
559  // rlwinm rA, rA, ShiftBits, 0, 0.
560  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
561  .addReg(Reg1, RegState::Kill)
562  .addImm(getEncodingValue(SrcReg))
563  .addImm(0).addImm(0);
564 
565  addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
566  .addReg(Reg, RegState::Kill),
567  FrameIndex);
568 
569  // Discard the pseudo instruction.
570  MBB.erase(II);
571 }
572 
574  unsigned FrameIndex) const {
575  // Get the instruction.
576  MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CRBIT <offset>
577  // Get the instruction's basic block.
578  MachineBasicBlock &MBB = *MI.getParent();
579  MachineFunction &MF = *MBB.getParent();
580  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
581  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
582  DebugLoc dl = MI.getDebugLoc();
583 
584  bool LP64 = TM.isPPC64();
585  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
586  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
587 
588  unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
589  unsigned DestReg = MI.getOperand(0).getReg();
590  assert(MI.definesRegister(DestReg) &&
591  "RESTORE_CRBIT does not define its destination");
592 
593  addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
594  Reg), FrameIndex);
595 
596  BuildMI(MBB, II, dl, TII.get(TargetOpcode::IMPLICIT_DEF), DestReg);
597 
598  unsigned RegO = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
599  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), RegO)
600  .addReg(getCRFromCRBit(DestReg));
601 
602  unsigned ShiftBits = getEncodingValue(DestReg);
603  // rlwimi r11, r10, 32-ShiftBits, ..., ...
604  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWIMI8 : PPC::RLWIMI), RegO)
605  .addReg(RegO, RegState::Kill).addReg(Reg, RegState::Kill)
606  .addImm(ShiftBits ? 32-ShiftBits : 0)
607  .addImm(ShiftBits).addImm(ShiftBits);
608 
609  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF),
610  getCRFromCRBit(DestReg))
611  .addReg(RegO, RegState::Kill)
612  // Make sure we have a use dependency all the way through this
613  // sequence of instructions. We can't have the other bits in the CR
614  // modified in between the mfocrf and the mtocrf.
616 
617  // Discard the pseudo instruction.
618  MBB.erase(II);
619 }
620 
622  unsigned FrameIndex) const {
623  // Get the instruction.
624  MachineInstr &MI = *II; // ; SPILL_VRSAVE <SrcReg>, <offset>
625  // Get the instruction's basic block.
626  MachineBasicBlock &MBB = *MI.getParent();
627  MachineFunction &MF = *MBB.getParent();
628  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
629  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
630  DebugLoc dl = MI.getDebugLoc();
631 
632  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
633  unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC);
634  unsigned SrcReg = MI.getOperand(0).getReg();
635 
636  BuildMI(MBB, II, dl, TII.get(PPC::MFVRSAVEv), Reg)
637  .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
638 
639  addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::STW))
640  .addReg(Reg, RegState::Kill),
641  FrameIndex);
642 
643  // Discard the pseudo instruction.
644  MBB.erase(II);
645 }
646 
648  unsigned FrameIndex) const {
649  // Get the instruction.
650  MachineInstr &MI = *II; // ; <DestReg> = RESTORE_VRSAVE <offset>
651  // Get the instruction's basic block.
652  MachineBasicBlock &MBB = *MI.getParent();
653  MachineFunction &MF = *MBB.getParent();
654  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
655  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
656  DebugLoc dl = MI.getDebugLoc();
657 
658  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
659  unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC);
660  unsigned DestReg = MI.getOperand(0).getReg();
661  assert(MI.definesRegister(DestReg) &&
662  "RESTORE_VRSAVE does not define its destination");
663 
664  addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::LWZ),
665  Reg), FrameIndex);
666 
667  BuildMI(MBB, II, dl, TII.get(PPC::MTVRSAVEv), DestReg)
668  .addReg(Reg, RegState::Kill);
669 
670  // Discard the pseudo instruction.
671  MBB.erase(II);
672 }
673 
674 bool
676  unsigned Reg, int &FrameIdx) const {
677  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
678  // For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4
679  // ABI, return true to prevent allocating an additional frame slot.
680  // For 64-bit, the CR save area is at SP+8; the value of FrameIdx = 0
681  // is arbitrary and will be subsequently ignored. For 32-bit, we have
682  // previously created the stack slot if needed, so return its FrameIdx.
683  if (Subtarget.isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) {
684  if (TM.isPPC64())
685  FrameIdx = 0;
686  else {
687  const PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
688  FrameIdx = FI->getCRSpillFrameIndex();
689  }
690  return true;
691  }
692  return false;
693 }
694 
695 // Figure out if the offset in the instruction must be a multiple of 4.
696 // This is true for instructions like "STD".
697 static bool usesIXAddr(const MachineInstr &MI) {
698  unsigned OpC = MI.getOpcode();
699 
700  switch (OpC) {
701  default:
702  return false;
703  case PPC::LWA:
704  case PPC::LWA_32:
705  case PPC::LD:
706  case PPC::STD:
707  return true;
708  }
709 }
710 
711 // Return the OffsetOperandNo given the FIOperandNum (and the instruction).
712 static unsigned getOffsetONFromFION(const MachineInstr &MI,
713  unsigned FIOperandNum) {
714  // Take into account whether it's an add or mem instruction
715  unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2;
716  if (MI.isInlineAsm())
717  OffsetOperandNo = FIOperandNum - 1;
718  else if (MI.getOpcode() == TargetOpcode::STACKMAP ||
720  OffsetOperandNo = FIOperandNum + 1;
721 
722  return OffsetOperandNo;
723 }
724 
725 void
727  int SPAdj, unsigned FIOperandNum,
728  RegScavenger *RS) const {
729  assert(SPAdj == 0 && "Unexpected");
730 
731  // Get the instruction.
732  MachineInstr &MI = *II;
733  // Get the instruction's basic block.
734  MachineBasicBlock &MBB = *MI.getParent();
735  // Get the basic block's function.
736  MachineFunction &MF = *MBB.getParent();
737  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
738  // Get the instruction info.
739  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
740  // Get the frame info.
741  MachineFrameInfo *MFI = MF.getFrameInfo();
742  DebugLoc dl = MI.getDebugLoc();
743 
744  unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
745 
746  // Get the frame index.
747  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
748 
749  // Get the frame pointer save index. Users of this index are primarily
750  // DYNALLOC instructions.
752  int FPSI = FI->getFramePointerSaveIndex();
753  // Get the instruction opcode.
754  unsigned OpC = MI.getOpcode();
755 
756  // Special case for dynamic alloca.
757  if (FPSI && FrameIndex == FPSI &&
758  (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
759  lowerDynamicAlloc(II);
760  return;
761  }
762 
763  // Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc.
764  if (OpC == PPC::SPILL_CR) {
765  lowerCRSpilling(II, FrameIndex);
766  return;
767  } else if (OpC == PPC::RESTORE_CR) {
768  lowerCRRestore(II, FrameIndex);
769  return;
770  } else if (OpC == PPC::SPILL_CRBIT) {
771  lowerCRBitSpilling(II, FrameIndex);
772  return;
773  } else if (OpC == PPC::RESTORE_CRBIT) {
774  lowerCRBitRestore(II, FrameIndex);
775  return;
776  } else if (OpC == PPC::SPILL_VRSAVE) {
777  lowerVRSAVESpilling(II, FrameIndex);
778  return;
779  } else if (OpC == PPC::RESTORE_VRSAVE) {
780  lowerVRSAVERestore(II, FrameIndex);
781  return;
782  }
783 
784  // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
785  MI.getOperand(FIOperandNum).ChangeToRegister(
786  FrameIndex < 0 ? getBaseRegister(MF) : getFrameRegister(MF), false);
787 
788  // Figure out if the offset in the instruction is shifted right two bits.
789  bool isIXAddr = usesIXAddr(MI);
790 
791  // If the instruction is not present in ImmToIdxMap, then it has no immediate
792  // form (and must be r+r).
793  bool noImmForm = !MI.isInlineAsm() && OpC != TargetOpcode::STACKMAP &&
794  OpC != TargetOpcode::PATCHPOINT && !ImmToIdxMap.count(OpC);
795 
796  // Now add the frame object offset to the offset from r1.
797  int Offset = MFI->getObjectOffset(FrameIndex);
798  Offset += MI.getOperand(OffsetOperandNo).getImm();
799 
800  // If we're not using a Frame Pointer that has been set to the value of the
801  // SP before having the stack size subtracted from it, then add the stack size
802  // to Offset to get the correct offset.
803  // Naked functions have stack size 0, although getStackSize may not reflect that
804  // because we didn't call all the pieces that compute it for naked functions.
806  if (!(hasBasePointer(MF) && FrameIndex < 0))
807  Offset += MFI->getStackSize();
808  }
809 
810  // If we can, encode the offset directly into the instruction. If this is a
811  // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If
812  // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
813  // clear can be encoded. This is extremely uncommon, because normally you
814  // only "std" to a stack slot that is at least 4-byte aligned, but it can
815  // happen in invalid code.
816  assert(OpC != PPC::DBG_VALUE &&
817  "This should be handled in a target-independent way");
818  if (!noImmForm && ((isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0)) ||
819  OpC == TargetOpcode::STACKMAP ||
820  OpC == TargetOpcode::PATCHPOINT)) {
821  MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
822  return;
823  }
824 
825  // The offset doesn't fit into a single register, scavenge one to build the
826  // offset in.
827 
828  bool is64Bit = TM.isPPC64();
829  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
830  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
831  const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC;
832  unsigned SRegHi = MF.getRegInfo().createVirtualRegister(RC),
833  SReg = MF.getRegInfo().createVirtualRegister(RC);
834 
835  // Insert a set of rA with the full offset value before the ld, st, or add
836  BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi)
837  .addImm(Offset >> 16);
838  BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
839  .addReg(SRegHi, RegState::Kill)
840  .addImm(Offset);
841 
842  // Convert into indexed form of the instruction:
843  //
844  // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
845  // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
846  unsigned OperandBase;
847 
848  if (noImmForm)
849  OperandBase = 1;
850  else if (OpC != TargetOpcode::INLINEASM) {
851  assert(ImmToIdxMap.count(OpC) &&
852  "No indexed form of load or store available!");
853  unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
854  MI.setDesc(TII.get(NewOpcode));
855  OperandBase = 1;
856  } else {
857  OperandBase = OffsetOperandNo;
858  }
859 
860  unsigned StackReg = MI.getOperand(FIOperandNum).getReg();
861  MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
862  MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true);
863 }
864 
866  const PPCFrameLowering *TFI = getFrameLowering(MF);
867 
868  if (!TM.isPPC64())
869  return TFI->hasFP(MF) ? PPC::R31 : PPC::R1;
870  else
871  return TFI->hasFP(MF) ? PPC::X31 : PPC::X1;
872 }
873 
875  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
876  if (!hasBasePointer(MF))
877  return getFrameRegister(MF);
878 
879  if (TM.isPPC64())
880  return PPC::X30;
881 
882  if (Subtarget.isSVR4ABI() &&
884  return PPC::R29;
885 
886  return PPC::R30;
887 }
888 
890  if (!EnableBasePointer)
891  return false;
892  if (AlwaysBasePointer)
893  return true;
894 
895  // If we need to realign the stack, then the stack pointer can no longer
896  // serve as an offset into the caller's stack space. As a result, we need a
897  // base pointer.
898  return needsStackRealignment(MF);
899 }
900 
902  if (MF.getFunction()->hasFnAttribute("no-realign-stack"))
903  return false;
904 
905  return true;
906 }
907 
909  const PPCFrameLowering *TFI = getFrameLowering(MF);
910  const MachineFrameInfo *MFI = MF.getFrameInfo();
911  const Function *F = MF.getFunction();
912  unsigned StackAlign = TFI->getStackAlignment();
913  bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
915 
916  return requiresRealignment && canRealignStack(MF);
917 }
918 
919 /// Returns true if the instruction's frame index
920 /// reference would be better served by a base register other than FP
921 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
922 /// references it should create new base registers for.
924 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
925  assert(Offset < 0 && "Local offset must be negative");
926 
927  // It's the load/store FI references that cause issues, as it can be difficult
928  // to materialize the offset if it won't fit in the literal field. Estimate
929  // based on the size of the local frame and some conservative assumptions
930  // about the rest of the stack frame (note, this is pre-regalloc, so
931  // we don't know everything for certain yet) whether this offset is likely
932  // to be out of range of the immediate. Return true if so.
933 
934  // We only generate virtual base registers for loads and stores that have
935  // an r+i form. Return false for everything else.
936  unsigned OpC = MI->getOpcode();
937  if (!ImmToIdxMap.count(OpC))
938  return false;
939 
940  // Don't generate a new virtual base register just to add zero to it.
941  if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) &&
942  MI->getOperand(2).getImm() == 0)
943  return false;
944 
945  MachineBasicBlock &MBB = *MI->getParent();
946  MachineFunction &MF = *MBB.getParent();
947  const PPCFrameLowering *TFI = getFrameLowering(MF);
948  unsigned StackEst = TFI->determineFrameLayout(MF, false, true);
949 
950  // If we likely don't need a stack frame, then we probably don't need a
951  // virtual base register either.
952  if (!StackEst)
953  return false;
954 
955  // Estimate an offset from the stack pointer.
956  // The incoming offset is relating to the SP at the start of the function,
957  // but when we access the local it'll be relative to the SP after local
958  // allocation, so adjust our SP-relative offset by that allocation size.
959  Offset += StackEst;
960 
961  // The frame pointer will point to the end of the stack, so estimate the
962  // offset as the difference between the object offset and the FP location.
963  return !isFrameOffsetLegal(MI, getBaseRegister(MF), Offset);
964 }
965 
966 /// Insert defining instruction(s) for BaseReg to
967 /// be a pointer to FrameIdx at the beginning of the basic block.
970  unsigned BaseReg, int FrameIdx,
971  int64_t Offset) const {
972  unsigned ADDriOpc = TM.isPPC64() ? PPC::ADDI8 : PPC::ADDI;
973 
975  DebugLoc DL; // Defaults to "unknown"
976  if (Ins != MBB->end())
977  DL = Ins->getDebugLoc();
978 
979  const MachineFunction &MF = *MBB->getParent();
980  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
981  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
982  const MCInstrDesc &MCID = TII.get(ADDriOpc);
983  MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
984  MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
985 
986  BuildMI(*MBB, Ins, DL, MCID, BaseReg)
987  .addFrameIndex(FrameIdx).addImm(Offset);
988 }
989 
991  int64_t Offset) const {
992  unsigned FIOperandNum = 0;
993  while (!MI.getOperand(FIOperandNum).isFI()) {
994  ++FIOperandNum;
995  assert(FIOperandNum < MI.getNumOperands() &&
996  "Instr doesn't have FrameIndex operand!");
997  }
998 
999  MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg, false);
1000  unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
1001  Offset += MI.getOperand(OffsetOperandNo).getImm();
1002  MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
1003 
1004  MachineBasicBlock &MBB = *MI.getParent();
1005  MachineFunction &MF = *MBB.getParent();
1006  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1007  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1008  const MCInstrDesc &MCID = MI.getDesc();
1009  MachineRegisterInfo &MRI = MF.getRegInfo();
1010  MRI.constrainRegClass(BaseReg,
1011  TII.getRegClass(MCID, FIOperandNum, this, MF));
1012 }
1013 
1015  unsigned BaseReg,
1016  int64_t Offset) const {
1017  unsigned FIOperandNum = 0;
1018  while (!MI->getOperand(FIOperandNum).isFI()) {
1019  ++FIOperandNum;
1020  assert(FIOperandNum < MI->getNumOperands() &&
1021  "Instr doesn't have FrameIndex operand!");
1022  }
1023 
1024  unsigned OffsetOperandNo = getOffsetONFromFION(*MI, FIOperandNum);
1025  Offset += MI->getOperand(OffsetOperandNo).getImm();
1026 
1027  return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm
1028  MI->getOpcode() == TargetOpcode::STACKMAP ||
1030  (isInt<16>(Offset) && (!usesIXAddr(*MI) || (Offset & 3) == 0));
1031 }
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
BitVector getReservedRegs(const MachineFunction &MF) const override
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
BitVector & set()
Definition: BitVector.h:218
bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const override
Alignment of stack for function (3 bits) stored as log2 of alignment with +1 bias 0 means unaligned (...
Definition: Attributes.h:106
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
bool isDarwinABI() const
Definition: PPCSubtarget.h:268
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
Returns true if the instruction's frame index reference would be better served by a base register oth...
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:138
The following two target-specific nodes are used for calls through function pointers in the 64-bit SV...
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
bool hasInlineAsm() const
Returns true if the function contains any inline assembly.
A Stackmap instruction captures the location of live variables at its position in the instruction str...
unsigned getID() const
getID() - Return the register class ID number.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:264
const_iterator begin(StringRef path)
Get begin iterator over path.
Definition: Path.cpp:232
A debug info location.
Definition: DebugLoc.h:34
F(f)
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
void lowerVRSAVERestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
#define R2(n)
bool hasAltivec() const
Definition: PPCSubtarget.h:221
Naked function.
Definition: Attributes.h:81
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:172
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
DILocation * get() const
Get the underlying DILocation.
Definition: DebugLoc.cpp:22
const HexagonInstrInfo * TII
static unsigned getOffsetONFromFION(const MachineInstr &MI, unsigned FIOperandNum)
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:271
bool isKill() const
unsigned getFrameRegister(const MachineFunction &MF) const override
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
void lowerVRSAVESpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
void lowerCRRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
int64_t getImm() const
void adjustStackMapLiveOutMask(uint32_t *Mask) const override
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
unsigned getKillRegState(bool B)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:267
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:120
TargetInstrInfo - Interface to description of machine instruction set.
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
DBG_VALUE - a mapping of the llvm.dbg.value intrinsic.
Definition: TargetOpcodes.h:69
IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
Definition: TargetOpcodes.h:52
void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const override
Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx at the beginning of the basic ...
bundle_iterator< MachineInstr, instr_iterator > iterator
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:325
Patchable call instruction - this instruction represents a call to a constant address, followed by a series of NOPs.
unsigned getBaseRegister(const MachineFunction &MF) const
static bool is64Bit(const char *name)
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
BitVector & reset()
Definition: BitVector.h:259
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
PPCTargetMachine - Common code between 32-bit and 64-bit PowerPC targets.
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
bool isSVR4ABI() const
Definition: PPCSubtarget.h:269
void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override
PPCRegisterInfo(const PPCTargetMachine &TM)
static unsigned getCRFromCRBit(unsigned SrcReg)
bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
Definition: MachineInstr.h:866
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
void lowerDynamicAlloc(MachineBasicBlock::iterator II) const
lowerDynamicAlloc - Generate the code for allocating an object in the current frame.
const uint32_t * getNoPreservedMask() const
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
static cl::opt< bool > AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(false), cl::desc("Force the use of a base pointer in every function"))
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
static bool usesIXAddr(const MachineInstr &MI)
const PPCInstrInfo * getInstrInfo() const override
Definition: PPCSubtarget.h:163
bool isInlineAsm() const
Definition: MachineInstr.h:760
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call...
bool isAllocatable(unsigned PhysReg) const
isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn't been...
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
unsigned determineFrameLayout(MachineFunction &MF, bool UpdateMF=true, bool UseEstimate=false) const
determineFrameLayout - Determine the size of the frame and maximum call frame size.
const MachineInstrBuilder & addFrameIndex(int Idx) const
size_type count(const KeyT &Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Definition: DenseMap.h:119
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:238
void lowerCRBitRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
KILL - This instruction is a noop that is used only to adjust the liveness of registers.
Definition: TargetOpcodes.h:35
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:51
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:217
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
getPointerRegClass - Return the register class to use to hold pointers.
#define I(x, y, z)
Definition: MD5.cpp:54
bool hasVSX() const
Definition: PPCSubtarget.h:224
iterator find(const KeyT &Val)
Definition: DenseMap.h:124
bool canRealignStack(const MachineFunction &MF) const
bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:272
bool hasP8Vector() const
Definition: PPCSubtarget.h:225
void lowerCRSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
lowerCRSpilling - Generate the code for spilling a CR register.
bool needsStackRealignment(const MachineFunction &MF) const override
unsigned getReg() const
getReg - Returns the register number.
const ARM::ArchExtKind Kind
void lowerCRBitSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
static cl::opt< bool > EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(true), cl::desc("Enable use of a base pointer for complex stack frames"))
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
bool hasBasePointer(const MachineFunction &MF) const
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
getLargestLegalSuperClass - Returns the largest super class of RC that is legal to use in the current...
bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, int &FrameIdx) const override