LLVM  3.7.0
ARMBaseInstrInfo.cpp
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1 //===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARM.h"
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMBaseRegisterInfo.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMFeatures.h"
19 #include "ARMHazardRecognizer.h"
20 #include "ARMMachineFunctionInfo.h"
22 #include "llvm/ADT/STLExtras.h"
32 #include "llvm/IR/Constants.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/IR/GlobalValue.h"
35 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/MC/MCExpr.h"
39 #include "llvm/Support/Debug.h"
42 
43 using namespace llvm;
44 
45 #define DEBUG_TYPE "arm-instrinfo"
46 
47 #define GET_INSTRINFO_CTOR_DTOR
48 #include "ARMGenInstrInfo.inc"
49 
50 static cl::opt<bool>
51 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
52  cl::desc("Enable ARM 2-addr to 3-addr conv"));
53 
54 static cl::opt<bool>
55 WidenVMOVS("widen-vmovs", cl::Hidden, cl::init(true),
56  cl::desc("Widen ARM vmovs to vmovd when possible"));
57 
58 static cl::opt<unsigned>
59 SwiftPartialUpdateClearance("swift-partial-update-clearance",
60  cl::Hidden, cl::init(12),
61  cl::desc("Clearance before partial register updates"));
62 
63 /// ARM_MLxEntry - Record information about MLA / MLS instructions.
64 struct ARM_MLxEntry {
65  uint16_t MLxOpc; // MLA / MLS opcode
66  uint16_t MulOpc; // Expanded multiplication opcode
67  uint16_t AddSubOpc; // Expanded add / sub opcode
68  bool NegAcc; // True if the acc is negated before the add / sub.
69  bool HasLane; // True if instruction has an extra "lane" operand.
70 };
71 
72 static const ARM_MLxEntry ARM_MLxTable[] = {
73  // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane
74  // fp scalar ops
75  { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
76  { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
77  { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
78  { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
79  { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
80  { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
81  { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
82  { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
83 
84  // fp SIMD ops
85  { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
86  { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
87  { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false },
88  { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false },
89  { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true },
90  { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true },
91  { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true },
92  { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
93 };
94 
96  : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
97  Subtarget(STI) {
98  for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) {
99  if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
100  assert(false && "Duplicated entries?");
101  MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc);
102  MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc);
103  }
104 }
105 
106 // Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl
107 // currently defaults to no prepass hazard recognizer.
110  const ScheduleDAG *DAG) const {
111  if (usePreRAHazardRecognizer()) {
112  const InstrItineraryData *II =
113  static_cast<const ARMSubtarget *>(STI)->getInstrItineraryData();
114  return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched");
115  }
117 }
118 
121  const ScheduleDAG *DAG) const {
122  if (Subtarget.isThumb2() || Subtarget.hasVFP2())
123  return (ScheduleHazardRecognizer *)new ARMHazardRecognizer(II, DAG);
125 }
126 
127 MachineInstr *
130  LiveVariables *LV) const {
131  // FIXME: Thumb2 support.
132 
133  if (!EnableARM3Addr)
134  return nullptr;
135 
136  MachineInstr *MI = MBBI;
137  MachineFunction &MF = *MI->getParent()->getParent();
138  uint64_t TSFlags = MI->getDesc().TSFlags;
139  bool isPre = false;
140  switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
141  default: return nullptr;
142  case ARMII::IndexModePre:
143  isPre = true;
144  break;
146  break;
147  }
148 
149  // Try splitting an indexed load/store to an un-indexed one plus an add/sub
150  // operation.
151  unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
152  if (MemOpc == 0)
153  return nullptr;
154 
155  MachineInstr *UpdateMI = nullptr;
156  MachineInstr *MemMI = nullptr;
157  unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
158  const MCInstrDesc &MCID = MI->getDesc();
159  unsigned NumOps = MCID.getNumOperands();
160  bool isLoad = !MI->mayStore();
161  const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
162  const MachineOperand &Base = MI->getOperand(2);
163  const MachineOperand &Offset = MI->getOperand(NumOps-3);
164  unsigned WBReg = WB.getReg();
165  unsigned BaseReg = Base.getReg();
166  unsigned OffReg = Offset.getReg();
167  unsigned OffImm = MI->getOperand(NumOps-2).getImm();
168  ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
169  switch (AddrMode) {
170  default: llvm_unreachable("Unknown indexed op!");
171  case ARMII::AddrMode2: {
172  bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
173  unsigned Amt = ARM_AM::getAM2Offset(OffImm);
174  if (OffReg == 0) {
175  if (ARM_AM::getSOImmVal(Amt) == -1)
176  // Can't encode it in a so_imm operand. This transformation will
177  // add more than 1 instruction. Abandon!
178  return nullptr;
179  UpdateMI = BuildMI(MF, MI->getDebugLoc(),
180  get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
181  .addReg(BaseReg).addImm(Amt)
182  .addImm(Pred).addReg(0).addReg(0);
183  } else if (Amt != 0) {
185  unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
186  UpdateMI = BuildMI(MF, MI->getDebugLoc(),
187  get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg)
188  .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
189  .addImm(Pred).addReg(0).addReg(0);
190  } else
191  UpdateMI = BuildMI(MF, MI->getDebugLoc(),
192  get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
193  .addReg(BaseReg).addReg(OffReg)
194  .addImm(Pred).addReg(0).addReg(0);
195  break;
196  }
197  case ARMII::AddrMode3 : {
198  bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
199  unsigned Amt = ARM_AM::getAM3Offset(OffImm);
200  if (OffReg == 0)
201  // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
202  UpdateMI = BuildMI(MF, MI->getDebugLoc(),
203  get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
204  .addReg(BaseReg).addImm(Amt)
205  .addImm(Pred).addReg(0).addReg(0);
206  else
207  UpdateMI = BuildMI(MF, MI->getDebugLoc(),
208  get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
209  .addReg(BaseReg).addReg(OffReg)
210  .addImm(Pred).addReg(0).addReg(0);
211  break;
212  }
213  }
214 
215  std::vector<MachineInstr*> NewMIs;
216  if (isPre) {
217  if (isLoad)
218  MemMI = BuildMI(MF, MI->getDebugLoc(),
219  get(MemOpc), MI->getOperand(0).getReg())
220  .addReg(WBReg).addImm(0).addImm(Pred);
221  else
222  MemMI = BuildMI(MF, MI->getDebugLoc(),
223  get(MemOpc)).addReg(MI->getOperand(1).getReg())
224  .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
225  NewMIs.push_back(MemMI);
226  NewMIs.push_back(UpdateMI);
227  } else {
228  if (isLoad)
229  MemMI = BuildMI(MF, MI->getDebugLoc(),
230  get(MemOpc), MI->getOperand(0).getReg())
231  .addReg(BaseReg).addImm(0).addImm(Pred);
232  else
233  MemMI = BuildMI(MF, MI->getDebugLoc(),
234  get(MemOpc)).addReg(MI->getOperand(1).getReg())
235  .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
236  if (WB.isDead())
237  UpdateMI->getOperand(0).setIsDead();
238  NewMIs.push_back(UpdateMI);
239  NewMIs.push_back(MemMI);
240  }
241 
242  // Transfer LiveVariables states, kill / dead info.
243  if (LV) {
244  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
245  MachineOperand &MO = MI->getOperand(i);
247  unsigned Reg = MO.getReg();
248 
250  if (MO.isDef()) {
251  MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
252  if (MO.isDead())
253  LV->addVirtualRegisterDead(Reg, NewMI);
254  }
255  if (MO.isUse() && MO.isKill()) {
256  for (unsigned j = 0; j < 2; ++j) {
257  // Look at the two new MI's in reverse order.
258  MachineInstr *NewMI = NewMIs[j];
259  if (!NewMI->readsRegister(Reg))
260  continue;
261  LV->addVirtualRegisterKilled(Reg, NewMI);
262  if (VI.removeKill(MI))
263  VI.Kills.push_back(NewMI);
264  break;
265  }
266  }
267  }
268  }
269  }
270 
271  MFI->insert(MBBI, NewMIs[1]);
272  MFI->insert(MBBI, NewMIs[0]);
273  return NewMIs[0];
274 }
275 
276 // Branch analysis.
277 bool
279  MachineBasicBlock *&FBB,
281  bool AllowModify) const {
282  TBB = nullptr;
283  FBB = nullptr;
284 
286  if (I == MBB.begin())
287  return false; // Empty blocks are easy.
288  --I;
289 
290  // Walk backwards from the end of the basic block until the branch is
291  // analyzed or we give up.
292  while (isPredicated(I) || I->isTerminator() || I->isDebugValue()) {
293 
294  // Flag to be raised on unanalyzeable instructions. This is useful in cases
295  // where we want to clean up on the end of the basic block before we bail
296  // out.
297  bool CantAnalyze = false;
298 
299  // Skip over DEBUG values and predicated nonterminators.
300  while (I->isDebugValue() || !I->isTerminator()) {
301  if (I == MBB.begin())
302  return false;
303  --I;
304  }
305 
306  if (isIndirectBranchOpcode(I->getOpcode()) ||
307  isJumpTableBranchOpcode(I->getOpcode())) {
308  // Indirect branches and jump tables can't be analyzed, but we still want
309  // to clean up any instructions at the tail of the basic block.
310  CantAnalyze = true;
311  } else if (isUncondBranchOpcode(I->getOpcode())) {
312  TBB = I->getOperand(0).getMBB();
313  } else if (isCondBranchOpcode(I->getOpcode())) {
314  // Bail out if we encounter multiple conditional branches.
315  if (!Cond.empty())
316  return true;
317 
318  assert(!FBB && "FBB should have been null.");
319  FBB = TBB;
320  TBB = I->getOperand(0).getMBB();
321  Cond.push_back(I->getOperand(1));
322  Cond.push_back(I->getOperand(2));
323  } else if (I->isReturn()) {
324  // Returns can't be analyzed, but we should run cleanup.
325  CantAnalyze = !isPredicated(I);
326  } else {
327  // We encountered other unrecognized terminator. Bail out immediately.
328  return true;
329  }
330 
331  // Cleanup code - to be run for unpredicated unconditional branches and
332  // returns.
333  if (!isPredicated(I) &&
334  (isUncondBranchOpcode(I->getOpcode()) ||
335  isIndirectBranchOpcode(I->getOpcode()) ||
336  isJumpTableBranchOpcode(I->getOpcode()) ||
337  I->isReturn())) {
338  // Forget any previous condition branch information - it no longer applies.
339  Cond.clear();
340  FBB = nullptr;
341 
342  // If we can modify the function, delete everything below this
343  // unconditional branch.
344  if (AllowModify) {
345  MachineBasicBlock::iterator DI = std::next(I);
346  while (DI != MBB.end()) {
347  MachineInstr *InstToDelete = DI;
348  ++DI;
349  InstToDelete->eraseFromParent();
350  }
351  }
352  }
353 
354  if (CantAnalyze)
355  return true;
356 
357  if (I == MBB.begin())
358  return false;
359 
360  --I;
361  }
362 
363  // We made it past the terminators without bailing out - we must have
364  // analyzed this branch successfully.
365  return false;
366 }
367 
368 
371  if (I == MBB.end())
372  return 0;
373 
374  if (!isUncondBranchOpcode(I->getOpcode()) &&
375  !isCondBranchOpcode(I->getOpcode()))
376  return 0;
377 
378  // Remove the branch.
379  I->eraseFromParent();
380 
381  I = MBB.end();
382 
383  if (I == MBB.begin()) return 1;
384  --I;
385  if (!isCondBranchOpcode(I->getOpcode()))
386  return 1;
387 
388  // Remove the branch.
389  I->eraseFromParent();
390  return 2;
391 }
392 
393 unsigned
395  MachineBasicBlock *FBB,
397  DebugLoc DL) const {
399  int BOpc = !AFI->isThumbFunction()
400  ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
401  int BccOpc = !AFI->isThumbFunction()
402  ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
403  bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function();
404 
405  // Shouldn't be a fall through.
406  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
407  assert((Cond.size() == 2 || Cond.size() == 0) &&
408  "ARM branch conditions have two components!");
409 
410  // For conditional branches, we use addOperand to preserve CPSR flags.
411 
412  if (!FBB) {
413  if (Cond.empty()) { // Unconditional branch?
414  if (isThumb)
415  BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0);
416  else
417  BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
418  } else
419  BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
420  .addImm(Cond[0].getImm()).addOperand(Cond[1]);
421  return 1;
422  }
423 
424  // Two-way conditional branch.
425  BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
426  .addImm(Cond[0].getImm()).addOperand(Cond[1]);
427  if (isThumb)
428  BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0);
429  else
430  BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
431  return 2;
432 }
433 
436  ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
437  Cond[0].setImm(ARMCC::getOppositeCondition(CC));
438  return false;
439 }
440 
442  if (MI->isBundle()) {
445  while (++I != E && I->isInsideBundle()) {
446  int PIdx = I->findFirstPredOperandIdx();
447  if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL)
448  return true;
449  }
450  return false;
451  }
452 
453  int PIdx = MI->findFirstPredOperandIdx();
454  return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
455 }
456 
459  unsigned Opc = MI->getOpcode();
460  if (isUncondBranchOpcode(Opc)) {
461  MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
463  .addImm(Pred[0].getImm())
464  .addReg(Pred[1].getReg());
465  return true;
466  }
467 
468  int PIdx = MI->findFirstPredOperandIdx();
469  if (PIdx != -1) {
470  MachineOperand &PMO = MI->getOperand(PIdx);
471  PMO.setImm(Pred[0].getImm());
472  MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
473  return true;
474  }
475  return false;
476 }
477 
479  ArrayRef<MachineOperand> Pred2) const {
480  if (Pred1.size() > 2 || Pred2.size() > 2)
481  return false;
482 
483  ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
484  ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
485  if (CC1 == CC2)
486  return true;
487 
488  switch (CC1) {
489  default:
490  return false;
491  case ARMCC::AL:
492  return true;
493  case ARMCC::HS:
494  return CC2 == ARMCC::HI;
495  case ARMCC::LS:
496  return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
497  case ARMCC::GE:
498  return CC2 == ARMCC::GT;
499  case ARMCC::LE:
500  return CC2 == ARMCC::LT;
501  }
502 }
503 
505  std::vector<MachineOperand> &Pred) const {
506  bool Found = false;
507  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
508  const MachineOperand &MO = MI->getOperand(i);
509  if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) ||
510  (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
511  Pred.push_back(MO);
512  Found = true;
513  }
514  }
515 
516  return Found;
517 }
518 
519 static bool isCPSRDefined(const MachineInstr *MI) {
520  for (const auto &MO : MI->operands())
521  if (MO.isReg() && MO.getReg() == ARM::CPSR && MO.isDef())
522  return true;
523  return false;
524 }
525 
526 static bool isEligibleForITBlock(const MachineInstr *MI) {
527  switch (MI->getOpcode()) {
528  default: return true;
529  case ARM::tADC: // ADC (register) T1
530  case ARM::tADDi3: // ADD (immediate) T1
531  case ARM::tADDi8: // ADD (immediate) T2
532  case ARM::tADDrr: // ADD (register) T1
533  case ARM::tAND: // AND (register) T1
534  case ARM::tASRri: // ASR (immediate) T1
535  case ARM::tASRrr: // ASR (register) T1
536  case ARM::tBIC: // BIC (register) T1
537  case ARM::tEOR: // EOR (register) T1
538  case ARM::tLSLri: // LSL (immediate) T1
539  case ARM::tLSLrr: // LSL (register) T1
540  case ARM::tLSRri: // LSR (immediate) T1
541  case ARM::tLSRrr: // LSR (register) T1
542  case ARM::tMUL: // MUL T1
543  case ARM::tMVN: // MVN (register) T1
544  case ARM::tORR: // ORR (register) T1
545  case ARM::tROR: // ROR (register) T1
546  case ARM::tRSB: // RSB (immediate) T1
547  case ARM::tSBC: // SBC (register) T1
548  case ARM::tSUBi3: // SUB (immediate) T1
549  case ARM::tSUBi8: // SUB (immediate) T2
550  case ARM::tSUBrr: // SUB (register) T1
551  return !isCPSRDefined(MI);
552  }
553 }
554 
555 /// isPredicable - Return true if the specified instruction can be predicated.
556 /// By default, this returns true for every instruction with a
557 /// PredicateOperand.
559  if (!MI->isPredicable())
560  return false;
561 
562  if (!isEligibleForITBlock(MI))
563  return false;
564 
565  ARMFunctionInfo *AFI =
567 
568  if (AFI->isThumb2Function()) {
569  if (getSubtarget().restrictIT())
570  return isV8EligibleForIT(MI);
571  } else { // non-Thumb
573  return false;
574  }
575 
576  return true;
577 }
578 
579 namespace llvm {
581  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
582  const MachineOperand &MO = MI->getOperand(i);
583  if (!MO.isReg() || MO.isUndef() || MO.isUse())
584  continue;
585  if (MO.getReg() != ARM::CPSR)
586  continue;
587  if (!MO.isDead())
588  return false;
589  }
590  // all definitions of CPSR are dead
591  return true;
592 }
593 }
594 
595 /// GetInstSize - Return the size of the specified MachineInstr.
596 ///
598  const MachineBasicBlock &MBB = *MI->getParent();
599  const MachineFunction *MF = MBB.getParent();
600  const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
601 
602  const MCInstrDesc &MCID = MI->getDesc();
603  if (MCID.getSize())
604  return MCID.getSize();
605 
606  // If this machine instr is an inline asm, measure it.
607  if (MI->getOpcode() == ARM::INLINEASM)
608  return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
609  unsigned Opc = MI->getOpcode();
610  switch (Opc) {
611  default:
612  // pseudo-instruction sizes are zero.
613  return 0;
615  return getInstBundleLength(MI);
616  case ARM::MOVi16_ga_pcrel:
617  case ARM::MOVTi16_ga_pcrel:
618  case ARM::t2MOVi16_ga_pcrel:
619  case ARM::t2MOVTi16_ga_pcrel:
620  return 4;
621  case ARM::MOVi32imm:
622  case ARM::t2MOVi32imm:
623  return 8;
624  case ARM::CONSTPOOL_ENTRY:
625  case ARM::JUMPTABLE_INSTS:
626  case ARM::JUMPTABLE_ADDRS:
627  case ARM::JUMPTABLE_TBB:
628  case ARM::JUMPTABLE_TBH:
629  // If this machine instr is a constant pool entry, its size is recorded as
630  // operand #2.
631  return MI->getOperand(2).getImm();
632  case ARM::Int_eh_sjlj_longjmp:
633  return 16;
634  case ARM::tInt_eh_sjlj_longjmp:
635  return 10;
636  case ARM::Int_eh_sjlj_setjmp:
637  case ARM::Int_eh_sjlj_setjmp_nofp:
638  return 20;
639  case ARM::tInt_eh_sjlj_setjmp:
640  case ARM::t2Int_eh_sjlj_setjmp:
641  case ARM::t2Int_eh_sjlj_setjmp_nofp:
642  return 12;
643  case ARM::SPACE:
644  return MI->getOperand(1).getImm();
645  }
646 }
647 
648 unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr *MI) const {
649  unsigned Size = 0;
652  while (++I != E && I->isInsideBundle()) {
653  assert(!I->isBundle() && "No nested bundle!");
654  Size += GetInstSizeInBytes(&*I);
655  }
656  return Size;
657 }
658 
661  unsigned DestReg, bool KillSrc,
662  const ARMSubtarget &Subtarget) const {
663  unsigned Opc = Subtarget.isThumb()
664  ? (Subtarget.isMClass() ? ARM::t2MRS_M : ARM::t2MRS_AR)
665  : ARM::MRS;
666 
667  MachineInstrBuilder MIB =
668  BuildMI(MBB, I, I->getDebugLoc(), get(Opc), DestReg);
669 
670  // There is only 1 A/R class MRS instruction, and it always refers to
671  // APSR. However, there are lots of other possibilities on M-class cores.
672  if (Subtarget.isMClass())
673  MIB.addImm(0x800);
674 
675  AddDefaultPred(MIB);
676 
677  MIB.addReg(ARM::CPSR, RegState::Implicit | getKillRegState(KillSrc));
678 }
679 
682  unsigned SrcReg, bool KillSrc,
683  const ARMSubtarget &Subtarget) const {
684  unsigned Opc = Subtarget.isThumb()
685  ? (Subtarget.isMClass() ? ARM::t2MSR_M : ARM::t2MSR_AR)
686  : ARM::MSR;
687 
688  MachineInstrBuilder MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
689 
690  if (Subtarget.isMClass())
691  MIB.addImm(0x800);
692  else
693  MIB.addImm(8);
694 
695  MIB.addReg(SrcReg, getKillRegState(KillSrc));
696 
697  AddDefaultPred(MIB);
698 
699  MIB.addReg(ARM::CPSR, RegState::Implicit | RegState::Define);
700 }
701 
704  unsigned DestReg, unsigned SrcReg,
705  bool KillSrc) const {
706  bool GPRDest = ARM::GPRRegClass.contains(DestReg);
707  bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
708 
709  if (GPRDest && GPRSrc) {
710  AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
711  .addReg(SrcReg, getKillRegState(KillSrc))));
712  return;
713  }
714 
715  bool SPRDest = ARM::SPRRegClass.contains(DestReg);
716  bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
717 
718  unsigned Opc = 0;
719  if (SPRDest && SPRSrc)
720  Opc = ARM::VMOVS;
721  else if (GPRDest && SPRSrc)
722  Opc = ARM::VMOVRS;
723  else if (SPRDest && GPRSrc)
724  Opc = ARM::VMOVSR;
725  else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && !Subtarget.isFPOnlySP())
726  Opc = ARM::VMOVD;
727  else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
728  Opc = ARM::VORRq;
729 
730  if (Opc) {
731  MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
732  MIB.addReg(SrcReg, getKillRegState(KillSrc));
733  if (Opc == ARM::VORRq)
734  MIB.addReg(SrcReg, getKillRegState(KillSrc));
735  AddDefaultPred(MIB);
736  return;
737  }
738 
739  // Handle register classes that require multiple instructions.
740  unsigned BeginIdx = 0;
741  unsigned SubRegs = 0;
742  int Spacing = 1;
743 
744  // Use VORRq when possible.
745  if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) {
746  Opc = ARM::VORRq;
747  BeginIdx = ARM::qsub_0;
748  SubRegs = 2;
749  } else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) {
750  Opc = ARM::VORRq;
751  BeginIdx = ARM::qsub_0;
752  SubRegs = 4;
753  // Fall back to VMOVD.
754  } else if (ARM::DPairRegClass.contains(DestReg, SrcReg)) {
755  Opc = ARM::VMOVD;
756  BeginIdx = ARM::dsub_0;
757  SubRegs = 2;
758  } else if (ARM::DTripleRegClass.contains(DestReg, SrcReg)) {
759  Opc = ARM::VMOVD;
760  BeginIdx = ARM::dsub_0;
761  SubRegs = 3;
762  } else if (ARM::DQuadRegClass.contains(DestReg, SrcReg)) {
763  Opc = ARM::VMOVD;
764  BeginIdx = ARM::dsub_0;
765  SubRegs = 4;
766  } else if (ARM::GPRPairRegClass.contains(DestReg, SrcReg)) {
767  Opc = Subtarget.isThumb2() ? ARM::tMOVr : ARM::MOVr;
768  BeginIdx = ARM::gsub_0;
769  SubRegs = 2;
770  } else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg)) {
771  Opc = ARM::VMOVD;
772  BeginIdx = ARM::dsub_0;
773  SubRegs = 2;
774  Spacing = 2;
775  } else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg)) {
776  Opc = ARM::VMOVD;
777  BeginIdx = ARM::dsub_0;
778  SubRegs = 3;
779  Spacing = 2;
780  } else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg)) {
781  Opc = ARM::VMOVD;
782  BeginIdx = ARM::dsub_0;
783  SubRegs = 4;
784  Spacing = 2;
785  } else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && Subtarget.isFPOnlySP()) {
786  Opc = ARM::VMOVS;
787  BeginIdx = ARM::ssub_0;
788  SubRegs = 2;
789  } else if (SrcReg == ARM::CPSR) {
790  copyFromCPSR(MBB, I, DestReg, KillSrc, Subtarget);
791  return;
792  } else if (DestReg == ARM::CPSR) {
793  copyToCPSR(MBB, I, SrcReg, KillSrc, Subtarget);
794  return;
795  }
796 
797  assert(Opc && "Impossible reg-to-reg copy");
798 
799  const TargetRegisterInfo *TRI = &getRegisterInfo();
801 
802  // Copy register tuples backward when the first Dest reg overlaps with SrcReg.
803  if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) {
804  BeginIdx = BeginIdx + ((SubRegs - 1) * Spacing);
805  Spacing = -Spacing;
806  }
807 #ifndef NDEBUG
808  SmallSet<unsigned, 4> DstRegs;
809 #endif
810  for (unsigned i = 0; i != SubRegs; ++i) {
811  unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i * Spacing);
812  unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i * Spacing);
813  assert(Dst && Src && "Bad sub-register");
814 #ifndef NDEBUG
815  assert(!DstRegs.count(Src) && "destructive vector copy");
816  DstRegs.insert(Dst);
817 #endif
818  Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst).addReg(Src);
819  // VORR takes two source operands.
820  if (Opc == ARM::VORRq)
821  Mov.addReg(Src);
822  Mov = AddDefaultPred(Mov);
823  // MOVr can set CC.
824  if (Opc == ARM::MOVr)
825  Mov = AddDefaultCC(Mov);
826  }
827  // Add implicit super-register defs and kills to the last instruction.
828  Mov->addRegisterDefined(DestReg, TRI);
829  if (KillSrc)
830  Mov->addRegisterKilled(SrcReg, TRI);
831 }
832 
833 const MachineInstrBuilder &
835  unsigned SubIdx, unsigned State,
836  const TargetRegisterInfo *TRI) const {
837  if (!SubIdx)
838  return MIB.addReg(Reg, State);
839 
841  return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
842  return MIB.addReg(Reg, State, SubIdx);
843 }
844 
847  unsigned SrcReg, bool isKill, int FI,
848  const TargetRegisterClass *RC,
849  const TargetRegisterInfo *TRI) const {
850  DebugLoc DL;
851  if (I != MBB.end()) DL = I->getDebugLoc();
852  MachineFunction &MF = *MBB.getParent();
853  MachineFrameInfo &MFI = *MF.getFrameInfo();
854  unsigned Align = MFI.getObjectAlignment(FI);
855 
856  MachineMemOperand *MMO =
859  MFI.getObjectSize(FI),
860  Align);
861 
862  switch (RC->getSize()) {
863  case 4:
864  if (ARM::GPRRegClass.hasSubClassEq(RC)) {
865  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12))
866  .addReg(SrcReg, getKillRegState(isKill))
867  .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
868  } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
869  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
870  .addReg(SrcReg, getKillRegState(isKill))
871  .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
872  } else
873  llvm_unreachable("Unknown reg class!");
874  break;
875  case 8:
876  if (ARM::DPRRegClass.hasSubClassEq(RC)) {
877  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
878  .addReg(SrcReg, getKillRegState(isKill))
879  .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
880  } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
881  if (Subtarget.hasV5TEOps()) {
882  MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STRD));
883  AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
884  AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
885  MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO);
886 
887  AddDefaultPred(MIB);
888  } else {
889  // Fallback to STM instruction, which has existed since the dawn of
890  // time.
891  MachineInstrBuilder MIB =
892  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STMIA))
893  .addFrameIndex(FI).addMemOperand(MMO));
894  AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
895  AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
896  }
897  } else
898  llvm_unreachable("Unknown reg class!");
899  break;
900  case 16:
901  if (ARM::DPairRegClass.hasSubClassEq(RC)) {
902  // Use aligned spills if the stack can be realigned.
903  if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
904  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64))
905  .addFrameIndex(FI).addImm(16)
906  .addReg(SrcReg, getKillRegState(isKill))
907  .addMemOperand(MMO));
908  } else {
909  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA))
910  .addReg(SrcReg, getKillRegState(isKill))
911  .addFrameIndex(FI)
912  .addMemOperand(MMO));
913  }
914  } else
915  llvm_unreachable("Unknown reg class!");
916  break;
917  case 24:
918  if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
919  // Use aligned spills if the stack can be realigned.
920  if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
921  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64TPseudo))
922  .addFrameIndex(FI).addImm(16)
923  .addReg(SrcReg, getKillRegState(isKill))
924  .addMemOperand(MMO));
925  } else {
926  MachineInstrBuilder MIB =
927  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
928  .addFrameIndex(FI))
929  .addMemOperand(MMO);
930  MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
931  MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
932  AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
933  }
934  } else
935  llvm_unreachable("Unknown reg class!");
936  break;
937  case 32:
938  if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
939  if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
940  // FIXME: It's possible to only store part of the QQ register if the
941  // spilled def has a sub-register index.
942  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
943  .addFrameIndex(FI).addImm(16)
944  .addReg(SrcReg, getKillRegState(isKill))
945  .addMemOperand(MMO));
946  } else {
947  MachineInstrBuilder MIB =
948  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
949  .addFrameIndex(FI))
950  .addMemOperand(MMO);
951  MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
952  MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
953  MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
954  AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
955  }
956  } else
957  llvm_unreachable("Unknown reg class!");
958  break;
959  case 64:
960  if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
961  MachineInstrBuilder MIB =
962  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
963  .addFrameIndex(FI))
964  .addMemOperand(MMO);
965  MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
966  MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
967  MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
968  MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
969  MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
970  MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
971  MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
972  AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
973  } else
974  llvm_unreachable("Unknown reg class!");
975  break;
976  default:
977  llvm_unreachable("Unknown reg class!");
978  }
979 }
980 
981 unsigned
983  int &FrameIndex) const {
984  switch (MI->getOpcode()) {
985  default: break;
986  case ARM::STRrs:
987  case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
988  if (MI->getOperand(1).isFI() &&
989  MI->getOperand(2).isReg() &&
990  MI->getOperand(3).isImm() &&
991  MI->getOperand(2).getReg() == 0 &&
992  MI->getOperand(3).getImm() == 0) {
993  FrameIndex = MI->getOperand(1).getIndex();
994  return MI->getOperand(0).getReg();
995  }
996  break;
997  case ARM::STRi12:
998  case ARM::t2STRi12:
999  case ARM::tSTRspi:
1000  case ARM::VSTRD:
1001  case ARM::VSTRS:
1002  if (MI->getOperand(1).isFI() &&
1003  MI->getOperand(2).isImm() &&
1004  MI->getOperand(2).getImm() == 0) {
1005  FrameIndex = MI->getOperand(1).getIndex();
1006  return MI->getOperand(0).getReg();
1007  }
1008  break;
1009  case ARM::VST1q64:
1010  case ARM::VST1d64TPseudo:
1011  case ARM::VST1d64QPseudo:
1012  if (MI->getOperand(0).isFI() &&
1013  MI->getOperand(2).getSubReg() == 0) {
1014  FrameIndex = MI->getOperand(0).getIndex();
1015  return MI->getOperand(2).getReg();
1016  }
1017  break;
1018  case ARM::VSTMQIA:
1019  if (MI->getOperand(1).isFI() &&
1020  MI->getOperand(0).getSubReg() == 0) {
1021  FrameIndex = MI->getOperand(1).getIndex();
1022  return MI->getOperand(0).getReg();
1023  }
1024  break;
1025  }
1026 
1027  return 0;
1028 }
1029 
1031  int &FrameIndex) const {
1032  const MachineMemOperand *Dummy;
1033  return MI->mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex);
1034 }
1035 
1036 void ARMBaseInstrInfo::
1038  unsigned DestReg, int FI,
1039  const TargetRegisterClass *RC,
1040  const TargetRegisterInfo *TRI) const {
1041  DebugLoc DL;
1042  if (I != MBB.end()) DL = I->getDebugLoc();
1043  MachineFunction &MF = *MBB.getParent();
1044  MachineFrameInfo &MFI = *MF.getFrameInfo();
1045  unsigned Align = MFI.getObjectAlignment(FI);
1046  MachineMemOperand *MMO =
1050  MFI.getObjectSize(FI),
1051  Align);
1052 
1053  switch (RC->getSize()) {
1054  case 4:
1055  if (ARM::GPRRegClass.hasSubClassEq(RC)) {
1056  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
1057  .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
1058 
1059  } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
1060  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
1061  .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
1062  } else
1063  llvm_unreachable("Unknown reg class!");
1064  break;
1065  case 8:
1066  if (ARM::DPRRegClass.hasSubClassEq(RC)) {
1067  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
1068  .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
1069  } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
1070  MachineInstrBuilder MIB;
1071 
1072  if (Subtarget.hasV5TEOps()) {
1073  MIB = BuildMI(MBB, I, DL, get(ARM::LDRD));
1074  AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1075  AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1076  MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO);
1077 
1078  AddDefaultPred(MIB);
1079  } else {
1080  // Fallback to LDM instruction, which has existed since the dawn of
1081  // time.
1082  MIB = AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDMIA))
1083  .addFrameIndex(FI).addMemOperand(MMO));
1084  MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1085  MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1086  }
1087 
1089  MIB.addReg(DestReg, RegState::ImplicitDefine);
1090  } else
1091  llvm_unreachable("Unknown reg class!");
1092  break;
1093  case 16:
1094  if (ARM::DPairRegClass.hasSubClassEq(RC)) {
1095  if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1096  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg)
1097  .addFrameIndex(FI).addImm(16)
1098  .addMemOperand(MMO));
1099  } else {
1100  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
1101  .addFrameIndex(FI)
1102  .addMemOperand(MMO));
1103  }
1104  } else
1105  llvm_unreachable("Unknown reg class!");
1106  break;
1107  case 24:
1108  if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
1109  if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1110  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg)
1111  .addFrameIndex(FI).addImm(16)
1112  .addMemOperand(MMO));
1113  } else {
1114  MachineInstrBuilder MIB =
1115  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1116  .addFrameIndex(FI)
1117  .addMemOperand(MMO));
1118  MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1119  MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1120  MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1122  MIB.addReg(DestReg, RegState::ImplicitDefine);
1123  }
1124  } else
1125  llvm_unreachable("Unknown reg class!");
1126  break;
1127  case 32:
1128  if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
1129  if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1130  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
1131  .addFrameIndex(FI).addImm(16)
1132  .addMemOperand(MMO));
1133  } else {
1134  MachineInstrBuilder MIB =
1135  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1136  .addFrameIndex(FI))
1137  .addMemOperand(MMO);
1138  MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1139  MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1140  MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1141  MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1143  MIB.addReg(DestReg, RegState::ImplicitDefine);
1144  }
1145  } else
1146  llvm_unreachable("Unknown reg class!");
1147  break;
1148  case 64:
1149  if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
1150  MachineInstrBuilder MIB =
1151  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1152  .addFrameIndex(FI))
1153  .addMemOperand(MMO);
1154  MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1155  MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1156  MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1157  MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1158  MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI);
1159  MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI);
1160  MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI);
1161  MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI);
1163  MIB.addReg(DestReg, RegState::ImplicitDefine);
1164  } else
1165  llvm_unreachable("Unknown reg class!");
1166  break;
1167  default:
1168  llvm_unreachable("Unknown regclass!");
1169  }
1170 }
1171 
1172 unsigned
1174  int &FrameIndex) const {
1175  switch (MI->getOpcode()) {
1176  default: break;
1177  case ARM::LDRrs:
1178  case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
1179  if (MI->getOperand(1).isFI() &&
1180  MI->getOperand(2).isReg() &&
1181  MI->getOperand(3).isImm() &&
1182  MI->getOperand(2).getReg() == 0 &&
1183  MI->getOperand(3).getImm() == 0) {
1184  FrameIndex = MI->getOperand(1).getIndex();
1185  return MI->getOperand(0).getReg();
1186  }
1187  break;
1188  case ARM::LDRi12:
1189  case ARM::t2LDRi12:
1190  case ARM::tLDRspi:
1191  case ARM::VLDRD:
1192  case ARM::VLDRS:
1193  if (MI->getOperand(1).isFI() &&
1194  MI->getOperand(2).isImm() &&
1195  MI->getOperand(2).getImm() == 0) {
1196  FrameIndex = MI->getOperand(1).getIndex();
1197  return MI->getOperand(0).getReg();
1198  }
1199  break;
1200  case ARM::VLD1q64:
1201  case ARM::VLD1d64TPseudo:
1202  case ARM::VLD1d64QPseudo:
1203  if (MI->getOperand(1).isFI() &&
1204  MI->getOperand(0).getSubReg() == 0) {
1205  FrameIndex = MI->getOperand(1).getIndex();
1206  return MI->getOperand(0).getReg();
1207  }
1208  break;
1209  case ARM::VLDMQIA:
1210  if (MI->getOperand(1).isFI() &&
1211  MI->getOperand(0).getSubReg() == 0) {
1212  FrameIndex = MI->getOperand(1).getIndex();
1213  return MI->getOperand(0).getReg();
1214  }
1215  break;
1216  }
1217 
1218  return 0;
1219 }
1220 
1222  int &FrameIndex) const {
1223  const MachineMemOperand *Dummy;
1224  return MI->mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1225 }
1226 
1227 bool
1229  MachineFunction &MF = *MI->getParent()->getParent();
1231 
1232  if (MI->getOpcode() == TargetOpcode::LOAD_STACK_GUARD) {
1233  assert(getSubtarget().getTargetTriple().isOSBinFormatMachO() &&
1234  "LOAD_STACK_GUARD currently supported only for MachO.");
1235  expandLoadStackGuard(MI, RM);
1236  MI->getParent()->erase(MI);
1237  return true;
1238  }
1239 
1240  // This hook gets to expand COPY instructions before they become
1241  // copyPhysReg() calls. Look for VMOVS instructions that can legally be
1242  // widened to VMOVD. We prefer the VMOVD when possible because it may be
1243  // changed into a VORR that can go down the NEON pipeline.
1244  if (!WidenVMOVS || !MI->isCopy() || Subtarget.isCortexA15() ||
1245  Subtarget.isFPOnlySP())
1246  return false;
1247 
1248  // Look for a copy between even S-registers. That is where we keep floats
1249  // when using NEON v2f32 instructions for f32 arithmetic.
1250  unsigned DstRegS = MI->getOperand(0).getReg();
1251  unsigned SrcRegS = MI->getOperand(1).getReg();
1252  if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS))
1253  return false;
1254 
1255  const TargetRegisterInfo *TRI = &getRegisterInfo();
1256  unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0,
1257  &ARM::DPRRegClass);
1258  unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0,
1259  &ARM::DPRRegClass);
1260  if (!DstRegD || !SrcRegD)
1261  return false;
1262 
1263  // We want to widen this into a DstRegD = VMOVD SrcRegD copy. This is only
1264  // legal if the COPY already defines the full DstRegD, and it isn't a
1265  // sub-register insertion.
1266  if (!MI->definesRegister(DstRegD, TRI) || MI->readsRegister(DstRegD, TRI))
1267  return false;
1268 
1269  // A dead copy shouldn't show up here, but reject it just in case.
1270  if (MI->getOperand(0).isDead())
1271  return false;
1272 
1273  // All clear, widen the COPY.
1274  DEBUG(dbgs() << "widening: " << *MI);
1275  MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
1276 
1277  // Get rid of the old <imp-def> of DstRegD. Leave it if it defines a Q-reg
1278  // or some other super-register.
1279  int ImpDefIdx = MI->findRegisterDefOperandIdx(DstRegD);
1280  if (ImpDefIdx != -1)
1281  MI->RemoveOperand(ImpDefIdx);
1282 
1283  // Change the opcode and operands.
1284  MI->setDesc(get(ARM::VMOVD));
1285  MI->getOperand(0).setReg(DstRegD);
1286  MI->getOperand(1).setReg(SrcRegD);
1287  AddDefaultPred(MIB);
1288 
1289  // We are now reading SrcRegD instead of SrcRegS. This may upset the
1290  // register scavenger and machine verifier, so we need to indicate that we
1291  // are reading an undefined value from SrcRegD, but a proper value from
1292  // SrcRegS.
1293  MI->getOperand(1).setIsUndef();
1294  MIB.addReg(SrcRegS, RegState::Implicit);
1295 
1296  // SrcRegD may actually contain an unrelated value in the ssub_1
1297  // sub-register. Don't kill it. Only kill the ssub_0 sub-register.
1298  if (MI->getOperand(1).isKill()) {
1299  MI->getOperand(1).setIsKill(false);
1300  MI->addRegisterKilled(SrcRegS, TRI, true);
1301  }
1302 
1303  DEBUG(dbgs() << "replaced by: " << *MI);
1304  return true;
1305 }
1306 
1307 /// Create a copy of a const pool value. Update CPI to the new index and return
1308 /// the label UID.
1309 static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
1312 
1313  const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
1314  assert(MCPE.isMachineConstantPoolEntry() &&
1315  "Expecting a machine constantpool entry!");
1316  ARMConstantPoolValue *ACPV =
1317  static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
1318 
1319  unsigned PCLabelId = AFI->createPICLabelUId();
1320  ARMConstantPoolValue *NewCPV = nullptr;
1321 
1322  // FIXME: The below assumes PIC relocation model and that the function
1323  // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and
1324  // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR
1325  // instructions, so that's probably OK, but is PIC always correct when
1326  // we get here?
1327  if (ACPV->isGlobalValue())
1328  NewCPV = ARMConstantPoolConstant::
1329  Create(cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId,
1330  ARMCP::CPValue, 4);
1331  else if (ACPV->isExtSymbol())
1332  NewCPV = ARMConstantPoolSymbol::
1333  Create(MF.getFunction()->getContext(),
1334  cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(), PCLabelId, 4);
1335  else if (ACPV->isBlockAddress())
1336  NewCPV = ARMConstantPoolConstant::
1337  Create(cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(), PCLabelId,
1339  else if (ACPV->isLSDA())
1340  NewCPV = ARMConstantPoolConstant::Create(MF.getFunction(), PCLabelId,
1341  ARMCP::CPLSDA, 4);
1342  else if (ACPV->isMachineBasicBlock())
1343  NewCPV = ARMConstantPoolMBB::
1344  Create(MF.getFunction()->getContext(),
1345  cast<ARMConstantPoolMBB>(ACPV)->getMBB(), PCLabelId, 4);
1346  else
1347  llvm_unreachable("Unexpected ARM constantpool value type!!");
1348  CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
1349  return PCLabelId;
1350 }
1351 
1352 void ARMBaseInstrInfo::
1355  unsigned DestReg, unsigned SubIdx,
1356  const MachineInstr *Orig,
1357  const TargetRegisterInfo &TRI) const {
1358  unsigned Opcode = Orig->getOpcode();
1359  switch (Opcode) {
1360  default: {
1361  MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1362  MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1363  MBB.insert(I, MI);
1364  break;
1365  }
1366  case ARM::tLDRpci_pic:
1367  case ARM::t2LDRpci_pic: {
1368  MachineFunction &MF = *MBB.getParent();
1369  unsigned CPI = Orig->getOperand(1).getIndex();
1370  unsigned PCLabelId = duplicateCPV(MF, CPI);
1371  MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1372  DestReg)
1373  .addConstantPoolIndex(CPI).addImm(PCLabelId);
1374  MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
1375  break;
1376  }
1377  }
1378 }
1379 
1380 MachineInstr *
1382  MachineInstr *MI = TargetInstrInfo::duplicate(Orig, MF);
1383  switch(Orig->getOpcode()) {
1384  case ARM::tLDRpci_pic:
1385  case ARM::t2LDRpci_pic: {
1386  unsigned CPI = Orig->getOperand(1).getIndex();
1387  unsigned PCLabelId = duplicateCPV(MF, CPI);
1388  Orig->getOperand(1).setIndex(CPI);
1389  Orig->getOperand(2).setImm(PCLabelId);
1390  break;
1391  }
1392  }
1393  return MI;
1394 }
1395 
1397  const MachineInstr *MI1,
1398  const MachineRegisterInfo *MRI) const {
1399  unsigned Opcode = MI0->getOpcode();
1400  if (Opcode == ARM::t2LDRpci ||
1401  Opcode == ARM::t2LDRpci_pic ||
1402  Opcode == ARM::tLDRpci ||
1403  Opcode == ARM::tLDRpci_pic ||
1404  Opcode == ARM::LDRLIT_ga_pcrel ||
1405  Opcode == ARM::LDRLIT_ga_pcrel_ldr ||
1406  Opcode == ARM::tLDRLIT_ga_pcrel ||
1407  Opcode == ARM::MOV_ga_pcrel ||
1408  Opcode == ARM::MOV_ga_pcrel_ldr ||
1409  Opcode == ARM::t2MOV_ga_pcrel) {
1410  if (MI1->getOpcode() != Opcode)
1411  return false;
1412  if (MI0->getNumOperands() != MI1->getNumOperands())
1413  return false;
1414 
1415  const MachineOperand &MO0 = MI0->getOperand(1);
1416  const MachineOperand &MO1 = MI1->getOperand(1);
1417  if (MO0.getOffset() != MO1.getOffset())
1418  return false;
1419 
1420  if (Opcode == ARM::LDRLIT_ga_pcrel ||
1421  Opcode == ARM::LDRLIT_ga_pcrel_ldr ||
1422  Opcode == ARM::tLDRLIT_ga_pcrel ||
1423  Opcode == ARM::MOV_ga_pcrel ||
1424  Opcode == ARM::MOV_ga_pcrel_ldr ||
1425  Opcode == ARM::t2MOV_ga_pcrel)
1426  // Ignore the PC labels.
1427  return MO0.getGlobal() == MO1.getGlobal();
1428 
1429  const MachineFunction *MF = MI0->getParent()->getParent();
1430  const MachineConstantPool *MCP = MF->getConstantPool();
1431  int CPI0 = MO0.getIndex();
1432  int CPI1 = MO1.getIndex();
1433  const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1434  const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1435  bool isARMCP0 = MCPE0.isMachineConstantPoolEntry();
1436  bool isARMCP1 = MCPE1.isMachineConstantPoolEntry();
1437  if (isARMCP0 && isARMCP1) {
1438  ARMConstantPoolValue *ACPV0 =
1439  static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1440  ARMConstantPoolValue *ACPV1 =
1441  static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1442  return ACPV0->hasSameValue(ACPV1);
1443  } else if (!isARMCP0 && !isARMCP1) {
1444  return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal;
1445  }
1446  return false;
1447  } else if (Opcode == ARM::PICLDR) {
1448  if (MI1->getOpcode() != Opcode)
1449  return false;
1450  if (MI0->getNumOperands() != MI1->getNumOperands())
1451  return false;
1452 
1453  unsigned Addr0 = MI0->getOperand(1).getReg();
1454  unsigned Addr1 = MI1->getOperand(1).getReg();
1455  if (Addr0 != Addr1) {
1456  if (!MRI ||
1459  return false;
1460 
1461  // This assumes SSA form.
1462  MachineInstr *Def0 = MRI->getVRegDef(Addr0);
1463  MachineInstr *Def1 = MRI->getVRegDef(Addr1);
1464  // Check if the loaded value, e.g. a constantpool of a global address, are
1465  // the same.
1466  if (!produceSameValue(Def0, Def1, MRI))
1467  return false;
1468  }
1469 
1470  for (unsigned i = 3, e = MI0->getNumOperands(); i != e; ++i) {
1471  // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg
1472  const MachineOperand &MO0 = MI0->getOperand(i);
1473  const MachineOperand &MO1 = MI1->getOperand(i);
1474  if (!MO0.isIdenticalTo(MO1))
1475  return false;
1476  }
1477  return true;
1478  }
1479 
1480  return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1481 }
1482 
1483 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1484 /// determine if two loads are loading from the same base address. It should
1485 /// only return true if the base pointers are the same and the only differences
1486 /// between the two addresses is the offset. It also returns the offsets by
1487 /// reference.
1488 ///
1489 /// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched
1490 /// is permanently disabled.
1492  int64_t &Offset1,
1493  int64_t &Offset2) const {
1494  // Don't worry about Thumb: just ARM and Thumb2.
1495  if (Subtarget.isThumb1Only()) return false;
1496 
1497  if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1498  return false;
1499 
1500  switch (Load1->getMachineOpcode()) {
1501  default:
1502  return false;
1503  case ARM::LDRi12:
1504  case ARM::LDRBi12:
1505  case ARM::LDRD:
1506  case ARM::LDRH:
1507  case ARM::LDRSB:
1508  case ARM::LDRSH:
1509  case ARM::VLDRD:
1510  case ARM::VLDRS:
1511  case ARM::t2LDRi8:
1512  case ARM::t2LDRBi8:
1513  case ARM::t2LDRDi8:
1514  case ARM::t2LDRSHi8:
1515  case ARM::t2LDRi12:
1516  case ARM::t2LDRBi12:
1517  case ARM::t2LDRSHi12:
1518  break;
1519  }
1520 
1521  switch (Load2->getMachineOpcode()) {
1522  default:
1523  return false;
1524  case ARM::LDRi12:
1525  case ARM::LDRBi12:
1526  case ARM::LDRD:
1527  case ARM::LDRH:
1528  case ARM::LDRSB:
1529  case ARM::LDRSH:
1530  case ARM::VLDRD:
1531  case ARM::VLDRS:
1532  case ARM::t2LDRi8:
1533  case ARM::t2LDRBi8:
1534  case ARM::t2LDRSHi8:
1535  case ARM::t2LDRi12:
1536  case ARM::t2LDRBi12:
1537  case ARM::t2LDRSHi12:
1538  break;
1539  }
1540 
1541  // Check if base addresses and chain operands match.
1542  if (Load1->getOperand(0) != Load2->getOperand(0) ||
1543  Load1->getOperand(4) != Load2->getOperand(4))
1544  return false;
1545 
1546  // Index should be Reg0.
1547  if (Load1->getOperand(3) != Load2->getOperand(3))
1548  return false;
1549 
1550  // Determine the offsets.
1551  if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
1552  isa<ConstantSDNode>(Load2->getOperand(1))) {
1553  Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
1554  Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
1555  return true;
1556  }
1557 
1558  return false;
1559 }
1560 
1561 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
1562 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
1563 /// be scheduled togther. On some targets if two loads are loading from
1564 /// addresses in the same cache line, it's better if they are scheduled
1565 /// together. This function takes two integers that represent the load offsets
1566 /// from the common base address. It returns true if it decides it's desirable
1567 /// to schedule the two loads together. "NumLoads" is the number of loads that
1568 /// have already been scheduled after Load1.
1569 ///
1570 /// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched
1571 /// is permanently disabled.
1573  int64_t Offset1, int64_t Offset2,
1574  unsigned NumLoads) const {
1575  // Don't worry about Thumb: just ARM and Thumb2.
1576  if (Subtarget.isThumb1Only()) return false;
1577 
1578  assert(Offset2 > Offset1);
1579 
1580  if ((Offset2 - Offset1) / 8 > 64)
1581  return false;
1582 
1583  // Check if the machine opcodes are different. If they are different
1584  // then we consider them to not be of the same base address,
1585  // EXCEPT in the case of Thumb2 byte loads where one is LDRBi8 and the other LDRBi12.
1586  // In this case, they are considered to be the same because they are different
1587  // encoding forms of the same basic instruction.
1588  if ((Load1->getMachineOpcode() != Load2->getMachineOpcode()) &&
1589  !((Load1->getMachineOpcode() == ARM::t2LDRBi8 &&
1590  Load2->getMachineOpcode() == ARM::t2LDRBi12) ||
1591  (Load1->getMachineOpcode() == ARM::t2LDRBi12 &&
1592  Load2->getMachineOpcode() == ARM::t2LDRBi8)))
1593  return false; // FIXME: overly conservative?
1594 
1595  // Four loads in a row should be sufficient.
1596  if (NumLoads >= 3)
1597  return false;
1598 
1599  return true;
1600 }
1601 
1603  const MachineBasicBlock *MBB,
1604  const MachineFunction &MF) const {
1605  // Debug info is never a scheduling boundary. It's necessary to be explicit
1606  // due to the special treatment of IT instructions below, otherwise a
1607  // dbg_value followed by an IT will result in the IT instruction being
1608  // considered a scheduling hazard, which is wrong. It should be the actual
1609  // instruction preceding the dbg_value instruction(s), just like it is
1610  // when debug info is not present.
1611  if (MI->isDebugValue())
1612  return false;
1613 
1614  // Terminators and labels can't be scheduled around.
1615  if (MI->isTerminator() || MI->isPosition())
1616  return true;
1617 
1618  // Treat the start of the IT block as a scheduling boundary, but schedule
1619  // t2IT along with all instructions following it.
1620  // FIXME: This is a big hammer. But the alternative is to add all potential
1621  // true and anti dependencies to IT block instructions as implicit operands
1622  // to the t2IT instruction. The added compile time and complexity does not
1623  // seem worth it.
1625  // Make sure to skip any dbg_value instructions
1626  while (++I != MBB->end() && I->isDebugValue())
1627  ;
1628  if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
1629  return true;
1630 
1631  // Don't attempt to schedule around any instruction that defines
1632  // a stack-oriented pointer, as it's unlikely to be profitable. This
1633  // saves compile time, because it doesn't require every single
1634  // stack slot reference to depend on the instruction that does the
1635  // modification.
1636  // Calls don't actually change the stack pointer, even if they have imp-defs.
1637  // No ARM calling conventions change the stack pointer. (X86 calling
1638  // conventions sometimes do).
1639  if (!MI->isCall() && MI->definesRegister(ARM::SP))
1640  return true;
1641 
1642  return false;
1643 }
1644 
1645 bool ARMBaseInstrInfo::
1647  unsigned NumCycles, unsigned ExtraPredCycles,
1648  const BranchProbability &Probability) const {
1649  if (!NumCycles)
1650  return false;
1651 
1652  // If we are optimizing for size, see if the branch in the predecessor can be
1653  // lowered to cbn?z by the constant island lowering pass, and return false if
1654  // so. This results in a shorter instruction sequence.
1655  const Function *F = MBB.getParent()->getFunction();
1658  MachineBasicBlock *Pred = *MBB.pred_begin();
1659  if (!Pred->empty()) {
1660  MachineInstr *LastMI = &*Pred->rbegin();
1661  if (LastMI->getOpcode() == ARM::t2Bcc) {
1662  MachineBasicBlock::iterator CmpMI = LastMI;
1663  if (CmpMI != Pred->begin()) {
1664  --CmpMI;
1665  if (CmpMI->getOpcode() == ARM::tCMPi8 ||
1666  CmpMI->getOpcode() == ARM::t2CMPri) {
1667  unsigned Reg = CmpMI->getOperand(0).getReg();
1668  unsigned PredReg = 0;
1669  ARMCC::CondCodes P = getInstrPredicate(CmpMI, PredReg);
1670  if (P == ARMCC::AL && CmpMI->getOperand(1).getImm() == 0 &&
1671  isARMLowRegister(Reg))
1672  return false;
1673  }
1674  }
1675  }
1676  }
1677  }
1678 
1679  // Attempt to estimate the relative costs of predication versus branching.
1680  unsigned UnpredCost = Probability.getNumerator() * NumCycles;
1681  UnpredCost /= Probability.getDenominator();
1682  UnpredCost += 1; // The branch itself
1683  UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1684 
1685  return (NumCycles + ExtraPredCycles) <= UnpredCost;
1686 }
1687 
1688 bool ARMBaseInstrInfo::
1690  unsigned TCycles, unsigned TExtra,
1691  MachineBasicBlock &FMBB,
1692  unsigned FCycles, unsigned FExtra,
1693  const BranchProbability &Probability) const {
1694  if (!TCycles || !FCycles)
1695  return false;
1696 
1697  // Attempt to estimate the relative costs of predication versus branching.
1698  unsigned TUnpredCost = Probability.getNumerator() * TCycles;
1699  TUnpredCost /= Probability.getDenominator();
1700 
1701  uint32_t Comp = Probability.getDenominator() - Probability.getNumerator();
1702  unsigned FUnpredCost = Comp * FCycles;
1703  FUnpredCost /= Probability.getDenominator();
1704 
1705  unsigned UnpredCost = TUnpredCost + FUnpredCost;
1706  UnpredCost += 1; // The branch itself
1707  UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1708 
1709  return (TCycles + FCycles + TExtra + FExtra) <= UnpredCost;
1710 }
1711 
1712 bool
1714  MachineBasicBlock &FMBB) const {
1715  // Reduce false anti-dependencies to let Swift's out-of-order execution
1716  // engine do its thing.
1717  return Subtarget.isSwift();
1718 }
1719 
1720 /// getInstrPredicate - If instruction is predicated, returns its predicate
1721 /// condition, otherwise returns AL. It also returns the condition code
1722 /// register by reference.
1724 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1725  int PIdx = MI->findFirstPredOperandIdx();
1726  if (PIdx == -1) {
1727  PredReg = 0;
1728  return ARMCC::AL;
1729  }
1730 
1731  PredReg = MI->getOperand(PIdx+1).getReg();
1732  return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1733 }
1734 
1735 
1736 unsigned llvm::getMatchingCondBranchOpcode(unsigned Opc) {
1737  if (Opc == ARM::B)
1738  return ARM::Bcc;
1739  if (Opc == ARM::tB)
1740  return ARM::tBcc;
1741  if (Opc == ARM::t2B)
1742  return ARM::t2Bcc;
1743 
1744  llvm_unreachable("Unknown unconditional branch opcode!");
1745 }
1746 
1747 /// commuteInstruction - Handle commutable instructions.
1748 MachineInstr *
1750  switch (MI->getOpcode()) {
1751  case ARM::MOVCCr:
1752  case ARM::t2MOVCCr: {
1753  // MOVCC can be commuted by inverting the condition.
1754  unsigned PredReg = 0;
1755  ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg);
1756  // MOVCC AL can't be inverted. Shouldn't happen.
1757  if (CC == ARMCC::AL || PredReg != ARM::CPSR)
1758  return nullptr;
1759  MI = TargetInstrInfo::commuteInstruction(MI, NewMI);
1760  if (!MI)
1761  return nullptr;
1762  // After swapping the MOVCC operands, also invert the condition.
1764  .setImm(ARMCC::getOppositeCondition(CC));
1765  return MI;
1766  }
1767  }
1768  return TargetInstrInfo::commuteInstruction(MI, NewMI);
1769 }
1770 
1771 /// Identify instructions that can be folded into a MOVCC instruction, and
1772 /// return the defining instruction.
1774  const MachineRegisterInfo &MRI,
1775  const TargetInstrInfo *TII) {
1777  return nullptr;
1778  if (!MRI.hasOneNonDBGUse(Reg))
1779  return nullptr;
1780  MachineInstr *MI = MRI.getVRegDef(Reg);
1781  if (!MI)
1782  return nullptr;
1783  // MI is folded into the MOVCC by predicating it.
1784  if (!MI->isPredicable())
1785  return nullptr;
1786  // Check if MI has any non-dead defs or physreg uses. This also detects
1787  // predicated instructions which will be reading CPSR.
1788  for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
1789  const MachineOperand &MO = MI->getOperand(i);
1790  // Reject frame index operands, PEI can't handle the predicated pseudos.
1791  if (MO.isFI() || MO.isCPI() || MO.isJTI())
1792  return nullptr;
1793  if (!MO.isReg())
1794  continue;
1795  // MI can't have any tied operands, that would conflict with predication.
1796  if (MO.isTied())
1797  return nullptr;
1799  return nullptr;
1800  if (MO.isDef() && !MO.isDead())
1801  return nullptr;
1802  }
1803  bool DontMoveAcrossStores = true;
1804  if (!MI->isSafeToMove(/* AliasAnalysis = */ nullptr, DontMoveAcrossStores))
1805  return nullptr;
1806  return MI;
1807 }
1808 
1811  unsigned &TrueOp, unsigned &FalseOp,
1812  bool &Optimizable) const {
1813  assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) &&
1814  "Unknown select instruction");
1815  // MOVCC operands:
1816  // 0: Def.
1817  // 1: True use.
1818  // 2: False use.
1819  // 3: Condition code.
1820  // 4: CPSR use.
1821  TrueOp = 1;
1822  FalseOp = 2;
1823  Cond.push_back(MI->getOperand(3));
1824  Cond.push_back(MI->getOperand(4));
1825  // We can always fold a def.
1826  Optimizable = true;
1827  return false;
1828 }
1829 
1830 MachineInstr *
1833  bool PreferFalse) const {
1834  assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) &&
1835  "Unknown select instruction");
1837  MachineInstr *DefMI = canFoldIntoMOVCC(MI->getOperand(2).getReg(), MRI, this);
1838  bool Invert = !DefMI;
1839  if (!DefMI)
1840  DefMI = canFoldIntoMOVCC(MI->getOperand(1).getReg(), MRI, this);
1841  if (!DefMI)
1842  return nullptr;
1843 
1844  // Find new register class to use.
1845  MachineOperand FalseReg = MI->getOperand(Invert ? 2 : 1);
1846  unsigned DestReg = MI->getOperand(0).getReg();
1847  const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg());
1848  if (!MRI.constrainRegClass(DestReg, PreviousClass))
1849  return nullptr;
1850 
1851  // Create a new predicated version of DefMI.
1852  // Rfalse is the first use.
1853  MachineInstrBuilder NewMI = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1854  DefMI->getDesc(), DestReg);
1855 
1856  // Copy all the DefMI operands, excluding its (null) predicate.
1857  const MCInstrDesc &DefDesc = DefMI->getDesc();
1858  for (unsigned i = 1, e = DefDesc.getNumOperands();
1859  i != e && !DefDesc.OpInfo[i].isPredicate(); ++i)
1860  NewMI.addOperand(DefMI->getOperand(i));
1861 
1862  unsigned CondCode = MI->getOperand(3).getImm();
1863  if (Invert)
1865  else
1866  NewMI.addImm(CondCode);
1867  NewMI.addOperand(MI->getOperand(4));
1868 
1869  // DefMI is not the -S version that sets CPSR, so add an optional %noreg.
1870  if (NewMI->hasOptionalDef())
1871  AddDefaultCC(NewMI);
1872 
1873  // The output register value when the predicate is false is an implicit
1874  // register operand tied to the first def.
1875  // The tie makes the register allocator ensure the FalseReg is allocated the
1876  // same register as operand 0.
1877  FalseReg.setImplicit();
1878  NewMI.addOperand(FalseReg);
1879  NewMI->tieOperands(0, NewMI->getNumOperands() - 1);
1880 
1881  // Update SeenMIs set: register newly created MI and erase removed DefMI.
1882  SeenMIs.insert(NewMI);
1883  SeenMIs.erase(DefMI);
1884 
1885  // If MI is inside a loop, and DefMI is outside the loop, then kill flags on
1886  // DefMI would be invalid when tranferred inside the loop. Checking for a
1887  // loop is expensive, but at least remove kill flags if they are in different
1888  // BBs.
1889  if (DefMI->getParent() != MI->getParent())
1890  NewMI->clearKillInfo();
1891 
1892  // The caller will erase MI, but not DefMI.
1893  DefMI->eraseFromParent();
1894  return NewMI;
1895 }
1896 
1897 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether the
1898 /// instruction is encoded with an 'S' bit is determined by the optional CPSR
1899 /// def operand.
1900 ///
1901 /// This will go away once we can teach tblgen how to set the optional CPSR def
1902 /// operand itself.
1904  uint16_t PseudoOpc;
1905  uint16_t MachineOpc;
1906 };
1907 
1909  {ARM::ADDSri, ARM::ADDri},
1910  {ARM::ADDSrr, ARM::ADDrr},
1911  {ARM::ADDSrsi, ARM::ADDrsi},
1912  {ARM::ADDSrsr, ARM::ADDrsr},
1913 
1914  {ARM::SUBSri, ARM::SUBri},
1915  {ARM::SUBSrr, ARM::SUBrr},
1916  {ARM::SUBSrsi, ARM::SUBrsi},
1917  {ARM::SUBSrsr, ARM::SUBrsr},
1918 
1919  {ARM::RSBSri, ARM::RSBri},
1920  {ARM::RSBSrsi, ARM::RSBrsi},
1921  {ARM::RSBSrsr, ARM::RSBrsr},
1922 
1923  {ARM::t2ADDSri, ARM::t2ADDri},
1924  {ARM::t2ADDSrr, ARM::t2ADDrr},
1925  {ARM::t2ADDSrs, ARM::t2ADDrs},
1926 
1927  {ARM::t2SUBSri, ARM::t2SUBri},
1928  {ARM::t2SUBSrr, ARM::t2SUBrr},
1929  {ARM::t2SUBSrs, ARM::t2SUBrs},
1930 
1931  {ARM::t2RSBSri, ARM::t2RSBri},
1932  {ARM::t2RSBSrs, ARM::t2RSBrs},
1933 };
1934 
1935 unsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) {
1936  for (unsigned i = 0, e = array_lengthof(AddSubFlagsOpcodeMap); i != e; ++i)
1937  if (OldOpc == AddSubFlagsOpcodeMap[i].PseudoOpc)
1938  return AddSubFlagsOpcodeMap[i].MachineOpc;
1939  return 0;
1940 }
1941 
1944  unsigned DestReg, unsigned BaseReg, int NumBytes,
1945  ARMCC::CondCodes Pred, unsigned PredReg,
1946  const ARMBaseInstrInfo &TII, unsigned MIFlags) {
1947  if (NumBytes == 0 && DestReg != BaseReg) {
1948  BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), DestReg)
1949  .addReg(BaseReg, RegState::Kill)
1950  .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
1951  .setMIFlags(MIFlags);
1952  return;
1953  }
1954 
1955  bool isSub = NumBytes < 0;
1956  if (isSub) NumBytes = -NumBytes;
1957 
1958  while (NumBytes) {
1959  unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1960  unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1961  assert(ThisVal && "Didn't extract field correctly");
1962 
1963  // We will handle these bits from offset, clear them.
1964  NumBytes &= ~ThisVal;
1965 
1966  assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1967 
1968  // Build the new ADD / SUB.
1969  unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1970  BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1971  .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1972  .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
1973  .setMIFlags(MIFlags);
1974  BaseReg = DestReg;
1975  }
1976 }
1977 
1978 static bool isAnySubRegLive(unsigned Reg, const TargetRegisterInfo *TRI,
1979  MachineInstr *MI) {
1980  for (MCSubRegIterator Subreg(Reg, TRI, /* IncludeSelf */ true);
1981  Subreg.isValid(); ++Subreg)
1982  if (MI->getParent()->computeRegisterLiveness(TRI, *Subreg, MI) !=
1984  return true;
1985  return false;
1986 }
1988  MachineFunction &MF, MachineInstr *MI,
1989  unsigned NumBytes) {
1990  // This optimisation potentially adds lots of load and store
1991  // micro-operations, it's only really a great benefit to code-size.
1993  return false;
1994 
1995  // If only one register is pushed/popped, LLVM can use an LDR/STR
1996  // instead. We can't modify those so make sure we're dealing with an
1997  // instruction we understand.
1998  bool IsPop = isPopOpcode(MI->getOpcode());
1999  bool IsPush = isPushOpcode(MI->getOpcode());
2000  if (!IsPush && !IsPop)
2001  return false;
2002 
2003  bool IsVFPPushPop = MI->getOpcode() == ARM::VSTMDDB_UPD ||
2004  MI->getOpcode() == ARM::VLDMDIA_UPD;
2005  bool IsT1PushPop = MI->getOpcode() == ARM::tPUSH ||
2006  MI->getOpcode() == ARM::tPOP ||
2007  MI->getOpcode() == ARM::tPOP_RET;
2008 
2009  assert((IsT1PushPop || (MI->getOperand(0).getReg() == ARM::SP &&
2010  MI->getOperand(1).getReg() == ARM::SP)) &&
2011  "trying to fold sp update into non-sp-updating push/pop");
2012 
2013  // The VFP push & pop act on D-registers, so we can only fold an adjustment
2014  // by a multiple of 8 bytes in correctly. Similarly rN is 4-bytes. Don't try
2015  // if this is violated.
2016  if (NumBytes % (IsVFPPushPop ? 8 : 4) != 0)
2017  return false;
2018 
2019  // ARM and Thumb2 push/pop insts have explicit "sp, sp" operands (+
2020  // pred) so the list starts at 4. Thumb1 starts after the predicate.
2021  int RegListIdx = IsT1PushPop ? 2 : 4;
2022 
2023  // Calculate the space we'll need in terms of registers.
2024  unsigned FirstReg = MI->getOperand(RegListIdx).getReg();
2025  unsigned RD0Reg, RegsNeeded;
2026  if (IsVFPPushPop) {
2027  RD0Reg = ARM::D0;
2028  RegsNeeded = NumBytes / 8;
2029  } else {
2030  RD0Reg = ARM::R0;
2031  RegsNeeded = NumBytes / 4;
2032  }
2033 
2034  // We're going to have to strip all list operands off before
2035  // re-adding them since the order matters, so save the existing ones
2036  // for later.
2038  for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i)
2039  RegList.push_back(MI->getOperand(i));
2040 
2042  const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
2043 
2044  // Now try to find enough space in the reglist to allocate NumBytes.
2045  for (unsigned CurReg = FirstReg - 1; CurReg >= RD0Reg && RegsNeeded;
2046  --CurReg) {
2047  if (!IsPop) {
2048  // Pushing any register is completely harmless, mark the
2049  // register involved as undef since we don't care about it in
2050  // the slightest.
2051  RegList.push_back(MachineOperand::CreateReg(CurReg, false, false,
2052  false, false, true));
2053  --RegsNeeded;
2054  continue;
2055  }
2056 
2057  // However, we can only pop an extra register if it's not live. For
2058  // registers live within the function we might clobber a return value
2059  // register; the other way a register can be live here is if it's
2060  // callee-saved.
2061  // TODO: Currently, computeRegisterLiveness() does not report "live" if a
2062  // sub reg is live. When computeRegisterLiveness() works for sub reg, it
2063  // can replace isAnySubRegLive().
2064  if (isCalleeSavedRegister(CurReg, CSRegs) ||
2065  isAnySubRegLive(CurReg, TRI, MI)) {
2066  // VFP pops don't allow holes in the register list, so any skip is fatal
2067  // for our transformation. GPR pops do, so we should just keep looking.
2068  if (IsVFPPushPop)
2069  return false;
2070  else
2071  continue;
2072  }
2073 
2074  // Mark the unimportant registers as <def,dead> in the POP.
2075  RegList.push_back(MachineOperand::CreateReg(CurReg, true, false, false,
2076  true));
2077  --RegsNeeded;
2078  }
2079 
2080  if (RegsNeeded > 0)
2081  return false;
2082 
2083  // Finally we know we can profitably perform the optimisation so go
2084  // ahead: strip all existing registers off and add them back again
2085  // in the right order.
2086  for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i)
2087  MI->RemoveOperand(i);
2088 
2089  // Add the complete list back in.
2090  MachineInstrBuilder MIB(MF, &*MI);
2091  for (int i = RegList.size() - 1; i >= 0; --i)
2092  MIB.addOperand(RegList[i]);
2093 
2094  return true;
2095 }
2096 
2097 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
2098  unsigned FrameReg, int &Offset,
2099  const ARMBaseInstrInfo &TII) {
2100  unsigned Opcode = MI.getOpcode();
2101  const MCInstrDesc &Desc = MI.getDesc();
2102  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
2103  bool isSub = false;
2104 
2105  // Memory operands in inline assembly always use AddrMode2.
2106  if (Opcode == ARM::INLINEASM)
2107  AddrMode = ARMII::AddrMode2;
2108 
2109  if (Opcode == ARM::ADDri) {
2110  Offset += MI.getOperand(FrameRegIdx+1).getImm();
2111  if (Offset == 0) {
2112  // Turn it into a move.
2113  MI.setDesc(TII.get(ARM::MOVr));
2114  MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2115  MI.RemoveOperand(FrameRegIdx+1);
2116  Offset = 0;
2117  return true;
2118  } else if (Offset < 0) {
2119  Offset = -Offset;
2120  isSub = true;
2121  MI.setDesc(TII.get(ARM::SUBri));
2122  }
2123 
2124  // Common case: small offset, fits into instruction.
2125  if (ARM_AM::getSOImmVal(Offset) != -1) {
2126  // Replace the FrameIndex with sp / fp
2127  MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2128  MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
2129  Offset = 0;
2130  return true;
2131  }
2132 
2133  // Otherwise, pull as much of the immedidate into this ADDri/SUBri
2134  // as possible.
2135  unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
2136  unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
2137 
2138  // We will handle these bits from offset, clear them.
2139  Offset &= ~ThisImmVal;
2140 
2141  // Get the properly encoded SOImmVal field.
2142  assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
2143  "Bit extraction didn't work?");
2144  MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
2145  } else {
2146  unsigned ImmIdx = 0;
2147  int InstrOffs = 0;
2148  unsigned NumBits = 0;
2149  unsigned Scale = 1;
2150  switch (AddrMode) {
2151  case ARMII::AddrMode_i12: {
2152  ImmIdx = FrameRegIdx + 1;
2153  InstrOffs = MI.getOperand(ImmIdx).getImm();
2154  NumBits = 12;
2155  break;
2156  }
2157  case ARMII::AddrMode2: {
2158  ImmIdx = FrameRegIdx+2;
2159  InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
2160  if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2161  InstrOffs *= -1;
2162  NumBits = 12;
2163  break;
2164  }
2165  case ARMII::AddrMode3: {
2166  ImmIdx = FrameRegIdx+2;
2167  InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
2168  if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2169  InstrOffs *= -1;
2170  NumBits = 8;
2171  break;
2172  }
2173  case ARMII::AddrMode4:
2174  case ARMII::AddrMode6:
2175  // Can't fold any offset even if it's zero.
2176  return false;
2177  case ARMII::AddrMode5: {
2178  ImmIdx = FrameRegIdx+1;
2179  InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
2180  if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2181  InstrOffs *= -1;
2182  NumBits = 8;
2183  Scale = 4;
2184  break;
2185  }
2186  default:
2187  llvm_unreachable("Unsupported addressing mode!");
2188  }
2189 
2190  Offset += InstrOffs * Scale;
2191  assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
2192  if (Offset < 0) {
2193  Offset = -Offset;
2194  isSub = true;
2195  }
2196 
2197  // Attempt to fold address comp. if opcode has offset bits
2198  if (NumBits > 0) {
2199  // Common case: small offset, fits into instruction.
2200  MachineOperand &ImmOp = MI.getOperand(ImmIdx);
2201  int ImmedOffset = Offset / Scale;
2202  unsigned Mask = (1 << NumBits) - 1;
2203  if ((unsigned)Offset <= Mask * Scale) {
2204  // Replace the FrameIndex with sp
2205  MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2206  // FIXME: When addrmode2 goes away, this will simplify (like the
2207  // T2 version), as the LDR.i12 versions don't need the encoding
2208  // tricks for the offset value.
2209  if (isSub) {
2210  if (AddrMode == ARMII::AddrMode_i12)
2211  ImmedOffset = -ImmedOffset;
2212  else
2213  ImmedOffset |= 1 << NumBits;
2214  }
2215  ImmOp.ChangeToImmediate(ImmedOffset);
2216  Offset = 0;
2217  return true;
2218  }
2219 
2220  // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
2221  ImmedOffset = ImmedOffset & Mask;
2222  if (isSub) {
2223  if (AddrMode == ARMII::AddrMode_i12)
2224  ImmedOffset = -ImmedOffset;
2225  else
2226  ImmedOffset |= 1 << NumBits;
2227  }
2228  ImmOp.ChangeToImmediate(ImmedOffset);
2229  Offset &= ~(Mask*Scale);
2230  }
2231  }
2232 
2233  Offset = (isSub) ? -Offset : Offset;
2234  return Offset == 0;
2235 }
2236 
2237 /// analyzeCompare - For a comparison instruction, return the source registers
2238 /// in SrcReg and SrcReg2 if having two register operands, and the value it
2239 /// compares against in CmpValue. Return true if the comparison instruction
2240 /// can be analyzed.
2241 bool ARMBaseInstrInfo::
2242 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
2243  int &CmpMask, int &CmpValue) const {
2244  switch (MI->getOpcode()) {
2245  default: break;
2246  case ARM::CMPri:
2247  case ARM::t2CMPri:
2248  SrcReg = MI->getOperand(0).getReg();
2249  SrcReg2 = 0;
2250  CmpMask = ~0;
2251  CmpValue = MI->getOperand(1).getImm();
2252  return true;
2253  case ARM::CMPrr:
2254  case ARM::t2CMPrr:
2255  SrcReg = MI->getOperand(0).getReg();
2256  SrcReg2 = MI->getOperand(1).getReg();
2257  CmpMask = ~0;
2258  CmpValue = 0;
2259  return true;
2260  case ARM::TSTri:
2261  case ARM::t2TSTri:
2262  SrcReg = MI->getOperand(0).getReg();
2263  SrcReg2 = 0;
2264  CmpMask = MI->getOperand(1).getImm();
2265  CmpValue = 0;
2266  return true;
2267  }
2268 
2269  return false;
2270 }
2271 
2272 /// isSuitableForMask - Identify a suitable 'and' instruction that
2273 /// operates on the given source register and applies the same mask
2274 /// as a 'tst' instruction. Provide a limited look-through for copies.
2275 /// When successful, MI will hold the found instruction.
2276 static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg,
2277  int CmpMask, bool CommonUse) {
2278  switch (MI->getOpcode()) {
2279  case ARM::ANDri:
2280  case ARM::t2ANDri:
2281  if (CmpMask != MI->getOperand(2).getImm())
2282  return false;
2283  if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg())
2284  return true;
2285  break;
2286  }
2287 
2288  return false;
2289 }
2290 
2291 /// getSwappedCondition - assume the flags are set by MI(a,b), return
2292 /// the condition code if we modify the instructions such that flags are
2293 /// set by MI(b,a).
2295  switch (CC) {
2296  default: return ARMCC::AL;
2297  case ARMCC::EQ: return ARMCC::EQ;
2298  case ARMCC::NE: return ARMCC::NE;
2299  case ARMCC::HS: return ARMCC::LS;
2300  case ARMCC::LO: return ARMCC::HI;
2301  case ARMCC::HI: return ARMCC::LO;
2302  case ARMCC::LS: return ARMCC::HS;
2303  case ARMCC::GE: return ARMCC::LE;
2304  case ARMCC::LT: return ARMCC::GT;
2305  case ARMCC::GT: return ARMCC::LT;
2306  case ARMCC::LE: return ARMCC::GE;
2307  }
2308 }
2309 
2310 /// isRedundantFlagInstr - check whether the first instruction, whose only
2311 /// purpose is to update flags, can be made redundant.
2312 /// CMPrr can be made redundant by SUBrr if the operands are the same.
2313 /// CMPri can be made redundant by SUBri if the operands are the same.
2314 /// This function can be extended later on.
2315 inline static bool isRedundantFlagInstr(MachineInstr *CmpI, unsigned SrcReg,
2316  unsigned SrcReg2, int ImmValue,
2317  MachineInstr *OI) {
2318  if ((CmpI->getOpcode() == ARM::CMPrr ||
2319  CmpI->getOpcode() == ARM::t2CMPrr) &&
2320  (OI->getOpcode() == ARM::SUBrr ||
2321  OI->getOpcode() == ARM::t2SUBrr) &&
2322  ((OI->getOperand(1).getReg() == SrcReg &&
2323  OI->getOperand(2).getReg() == SrcReg2) ||
2324  (OI->getOperand(1).getReg() == SrcReg2 &&
2325  OI->getOperand(2).getReg() == SrcReg)))
2326  return true;
2327 
2328  if ((CmpI->getOpcode() == ARM::CMPri ||
2329  CmpI->getOpcode() == ARM::t2CMPri) &&
2330  (OI->getOpcode() == ARM::SUBri ||
2331  OI->getOpcode() == ARM::t2SUBri) &&
2332  OI->getOperand(1).getReg() == SrcReg &&
2333  OI->getOperand(2).getImm() == ImmValue)
2334  return true;
2335  return false;
2336 }
2337 
2338 /// optimizeCompareInstr - Convert the instruction supplying the argument to the
2339 /// comparison into one that sets the zero bit in the flags register;
2340 /// Remove a redundant Compare instruction if an earlier instruction can set the
2341 /// flags in the same way as Compare.
2342 /// E.g. SUBrr(r1,r2) and CMPrr(r1,r2). We also handle the case where two
2343 /// operands are swapped: SUBrr(r1,r2) and CMPrr(r2,r1), by updating the
2344 /// condition code of instructions which use the flags.
2345 bool ARMBaseInstrInfo::
2346 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
2347  int CmpMask, int CmpValue,
2348  const MachineRegisterInfo *MRI) const {
2349  // Get the unique definition of SrcReg.
2350  MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
2351  if (!MI) return false;
2352 
2353  // Masked compares sometimes use the same register as the corresponding 'and'.
2354  if (CmpMask != ~0) {
2355  if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(MI)) {
2356  MI = nullptr;
2358  UI = MRI->use_instr_begin(SrcReg), UE = MRI->use_instr_end();
2359  UI != UE; ++UI) {
2360  if (UI->getParent() != CmpInstr->getParent()) continue;
2361  MachineInstr *PotentialAND = &*UI;
2362  if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true) ||
2363  isPredicated(PotentialAND))
2364  continue;
2365  MI = PotentialAND;
2366  break;
2367  }
2368  if (!MI) return false;
2369  }
2370  }
2371 
2372  // Get ready to iterate backward from CmpInstr.
2373  MachineBasicBlock::iterator I = CmpInstr, E = MI,
2374  B = CmpInstr->getParent()->begin();
2375 
2376  // Early exit if CmpInstr is at the beginning of the BB.
2377  if (I == B) return false;
2378 
2379  // There are two possible candidates which can be changed to set CPSR:
2380  // One is MI, the other is a SUB instruction.
2381  // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
2382  // For CMPri(r1, CmpValue), we are looking for SUBri(r1, CmpValue).
2383  MachineInstr *Sub = nullptr;
2384  if (SrcReg2 != 0)
2385  // MI is not a candidate for CMPrr.
2386  MI = nullptr;
2387  else if (MI->getParent() != CmpInstr->getParent() || CmpValue != 0) {
2388  // Conservatively refuse to convert an instruction which isn't in the same
2389  // BB as the comparison.
2390  // For CMPri w/ CmpValue != 0, a Sub may still be a candidate.
2391  // Thus we cannot return here.
2392  if (CmpInstr->getOpcode() == ARM::CMPri ||
2393  CmpInstr->getOpcode() == ARM::t2CMPri)
2394  MI = nullptr;
2395  else
2396  return false;
2397  }
2398 
2399  // Check that CPSR isn't set between the comparison instruction and the one we
2400  // want to change. At the same time, search for Sub.
2401  const TargetRegisterInfo *TRI = &getRegisterInfo();
2402  --I;
2403  for (; I != E; --I) {
2404  const MachineInstr &Instr = *I;
2405 
2406  if (Instr.modifiesRegister(ARM::CPSR, TRI) ||
2407  Instr.readsRegister(ARM::CPSR, TRI))
2408  // This instruction modifies or uses CPSR after the one we want to
2409  // change. We can't do this transformation.
2410  return false;
2411 
2412  // Check whether CmpInstr can be made redundant by the current instruction.
2413  if (isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) {
2414  Sub = &*I;
2415  break;
2416  }
2417 
2418  if (I == B)
2419  // The 'and' is below the comparison instruction.
2420  return false;
2421  }
2422 
2423  // Return false if no candidates exist.
2424  if (!MI && !Sub)
2425  return false;
2426 
2427  // The single candidate is called MI.
2428  if (!MI) MI = Sub;
2429 
2430  // We can't use a predicated instruction - it doesn't always write the flags.
2431  if (isPredicated(MI))
2432  return false;
2433 
2434  switch (MI->getOpcode()) {
2435  default: break;
2436  case ARM::RSBrr:
2437  case ARM::RSBri:
2438  case ARM::RSCrr:
2439  case ARM::RSCri:
2440  case ARM::ADDrr:
2441  case ARM::ADDri:
2442  case ARM::ADCrr:
2443  case ARM::ADCri:
2444  case ARM::SUBrr:
2445  case ARM::SUBri:
2446  case ARM::SBCrr:
2447  case ARM::SBCri:
2448  case ARM::t2RSBri:
2449  case ARM::t2ADDrr:
2450  case ARM::t2ADDri:
2451  case ARM::t2ADCrr:
2452  case ARM::t2ADCri:
2453  case ARM::t2SUBrr:
2454  case ARM::t2SUBri:
2455  case ARM::t2SBCrr:
2456  case ARM::t2SBCri:
2457  case ARM::ANDrr:
2458  case ARM::ANDri:
2459  case ARM::t2ANDrr:
2460  case ARM::t2ANDri:
2461  case ARM::ORRrr:
2462  case ARM::ORRri:
2463  case ARM::t2ORRrr:
2464  case ARM::t2ORRri:
2465  case ARM::EORrr:
2466  case ARM::EORri:
2467  case ARM::t2EORrr:
2468  case ARM::t2EORri: {
2469  // Scan forward for the use of CPSR
2470  // When checking against MI: if it's a conditional code that requires
2471  // checking of the V bit or C bit, then this is not safe to do.
2472  // It is safe to remove CmpInstr if CPSR is redefined or killed.
2473  // If we are done with the basic block, we need to check whether CPSR is
2474  // live-out.
2476  OperandsToUpdate;
2477  bool isSafe = false;
2478  I = CmpInstr;
2479  E = CmpInstr->getParent()->end();
2480  while (!isSafe && ++I != E) {
2481  const MachineInstr &Instr = *I;
2482  for (unsigned IO = 0, EO = Instr.getNumOperands();
2483  !isSafe && IO != EO; ++IO) {
2484  const MachineOperand &MO = Instr.getOperand(IO);
2485  if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) {
2486  isSafe = true;
2487  break;
2488  }
2489  if (!MO.isReg() || MO.getReg() != ARM::CPSR)
2490  continue;
2491  if (MO.isDef()) {
2492  isSafe = true;
2493  break;
2494  }
2495  // Condition code is after the operand before CPSR except for VSELs.
2496  ARMCC::CondCodes CC;
2497  bool IsInstrVSel = true;
2498  switch (Instr.getOpcode()) {
2499  default:
2500  IsInstrVSel = false;
2501  CC = (ARMCC::CondCodes)Instr.getOperand(IO - 1).getImm();
2502  break;
2503  case ARM::VSELEQD:
2504  case ARM::VSELEQS:
2505  CC = ARMCC::EQ;
2506  break;
2507  case ARM::VSELGTD:
2508  case ARM::VSELGTS:
2509  CC = ARMCC::GT;
2510  break;
2511  case ARM::VSELGED:
2512  case ARM::VSELGES:
2513  CC = ARMCC::GE;
2514  break;
2515  case ARM::VSELVSS:
2516  case ARM::VSELVSD:
2517  CC = ARMCC::VS;
2518  break;
2519  }
2520 
2521  if (Sub) {
2523  if (NewCC == ARMCC::AL)
2524  return false;
2525  // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based
2526  // on CMP needs to be updated to be based on SUB.
2527  // Push the condition code operands to OperandsToUpdate.
2528  // If it is safe to remove CmpInstr, the condition code of these
2529  // operands will be modified.
2530  if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
2531  Sub->getOperand(2).getReg() == SrcReg) {
2532  // VSel doesn't support condition code update.
2533  if (IsInstrVSel)
2534  return false;
2535  OperandsToUpdate.push_back(
2536  std::make_pair(&((*I).getOperand(IO - 1)), NewCC));
2537  }
2538  } else {
2539  // No Sub, so this is x = <op> y, z; cmp x, 0.
2540  switch (CC) {
2541  case ARMCC::EQ: // Z
2542  case ARMCC::NE: // Z
2543  case ARMCC::MI: // N
2544  case ARMCC::PL: // N
2545  case ARMCC::AL: // none
2546  // CPSR can be used multiple times, we should continue.
2547  break;
2548  case ARMCC::HS: // C
2549  case ARMCC::LO: // C
2550  case ARMCC::VS: // V
2551  case ARMCC::VC: // V
2552  case ARMCC::HI: // C Z
2553  case ARMCC::LS: // C Z
2554  case ARMCC::GE: // N V
2555  case ARMCC::LT: // N V
2556  case ARMCC::GT: // Z N V
2557  case ARMCC::LE: // Z N V
2558  // The instruction uses the V bit or C bit which is not safe.
2559  return false;
2560  }
2561  }
2562  }
2563  }
2564 
2565  // If CPSR is not killed nor re-defined, we should check whether it is
2566  // live-out. If it is live-out, do not optimize.
2567  if (!isSafe) {
2568  MachineBasicBlock *MBB = CmpInstr->getParent();
2570  SE = MBB->succ_end(); SI != SE; ++SI)
2571  if ((*SI)->isLiveIn(ARM::CPSR))
2572  return false;
2573  }
2574 
2575  // Toggle the optional operand to CPSR.
2576  MI->getOperand(5).setReg(ARM::CPSR);
2577  MI->getOperand(5).setIsDef(true);
2578  assert(!isPredicated(MI) && "Can't use flags from predicated instruction");
2579  CmpInstr->eraseFromParent();
2580 
2581  // Modify the condition code of operands in OperandsToUpdate.
2582  // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
2583  // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
2584  for (unsigned i = 0, e = OperandsToUpdate.size(); i < e; i++)
2585  OperandsToUpdate[i].first->setImm(OperandsToUpdate[i].second);
2586  return true;
2587  }
2588  }
2589 
2590  return false;
2591 }
2592 
2594  MachineInstr *DefMI, unsigned Reg,
2595  MachineRegisterInfo *MRI) const {
2596  // Fold large immediates into add, sub, or, xor.
2597  unsigned DefOpc = DefMI->getOpcode();
2598  if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm)
2599  return false;
2600  if (!DefMI->getOperand(1).isImm())
2601  // Could be t2MOVi32imm <ga:xx>
2602  return false;
2603 
2604  if (!MRI->hasOneNonDBGUse(Reg))
2605  return false;
2606 
2607  const MCInstrDesc &DefMCID = DefMI->getDesc();
2608  if (DefMCID.hasOptionalDef()) {
2609  unsigned NumOps = DefMCID.getNumOperands();
2610  const MachineOperand &MO = DefMI->getOperand(NumOps-1);
2611  if (MO.getReg() == ARM::CPSR && !MO.isDead())
2612  // If DefMI defines CPSR and it is not dead, it's obviously not safe
2613  // to delete DefMI.
2614  return false;
2615  }
2616 
2617  const MCInstrDesc &UseMCID = UseMI->getDesc();
2618  if (UseMCID.hasOptionalDef()) {
2619  unsigned NumOps = UseMCID.getNumOperands();
2620  if (UseMI->getOperand(NumOps-1).getReg() == ARM::CPSR)
2621  // If the instruction sets the flag, do not attempt this optimization
2622  // since it may change the semantics of the code.
2623  return false;
2624  }
2625 
2626  unsigned UseOpc = UseMI->getOpcode();
2627  unsigned NewUseOpc = 0;
2628  uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm();
2629  uint32_t SOImmValV1 = 0, SOImmValV2 = 0;
2630  bool Commute = false;
2631  switch (UseOpc) {
2632  default: return false;
2633  case ARM::SUBrr:
2634  case ARM::ADDrr:
2635  case ARM::ORRrr:
2636  case ARM::EORrr:
2637  case ARM::t2SUBrr:
2638  case ARM::t2ADDrr:
2639  case ARM::t2ORRrr:
2640  case ARM::t2EORrr: {
2641  Commute = UseMI->getOperand(2).getReg() != Reg;
2642  switch (UseOpc) {
2643  default: break;
2644  case ARM::SUBrr: {
2645  if (Commute)
2646  return false;
2647  ImmVal = -ImmVal;
2648  NewUseOpc = ARM::SUBri;
2649  // Fallthrough
2650  }
2651  case ARM::ADDrr:
2652  case ARM::ORRrr:
2653  case ARM::EORrr: {
2654  if (!ARM_AM::isSOImmTwoPartVal(ImmVal))
2655  return false;
2656  SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
2657  SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
2658  switch (UseOpc) {
2659  default: break;
2660  case ARM::ADDrr: NewUseOpc = ARM::ADDri; break;
2661  case ARM::ORRrr: NewUseOpc = ARM::ORRri; break;
2662  case ARM::EORrr: NewUseOpc = ARM::EORri; break;
2663  }
2664  break;
2665  }
2666  case ARM::t2SUBrr: {
2667  if (Commute)
2668  return false;
2669  ImmVal = -ImmVal;
2670  NewUseOpc = ARM::t2SUBri;
2671  // Fallthrough
2672  }
2673  case ARM::t2ADDrr:
2674  case ARM::t2ORRrr:
2675  case ARM::t2EORrr: {
2676  if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal))
2677  return false;
2678  SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
2679  SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
2680  switch (UseOpc) {
2681  default: break;
2682  case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break;
2683  case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break;
2684  case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break;
2685  }
2686  break;
2687  }
2688  }
2689  }
2690  }
2691 
2692  unsigned OpIdx = Commute ? 2 : 1;
2693  unsigned Reg1 = UseMI->getOperand(OpIdx).getReg();
2694  bool isKill = UseMI->getOperand(OpIdx).isKill();
2695  unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg));
2697  UseMI, UseMI->getDebugLoc(),
2698  get(NewUseOpc), NewReg)
2699  .addReg(Reg1, getKillRegState(isKill))
2700  .addImm(SOImmValV1)));
2701  UseMI->setDesc(get(NewUseOpc));
2702  UseMI->getOperand(1).setReg(NewReg);
2703  UseMI->getOperand(1).setIsKill();
2704  UseMI->getOperand(2).ChangeToImmediate(SOImmValV2);
2705  DefMI->eraseFromParent();
2706  return true;
2707 }
2708 
2709 static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData,
2710  const MachineInstr *MI) {
2711  switch (MI->getOpcode()) {
2712  default: {
2713  const MCInstrDesc &Desc = MI->getDesc();
2714  int UOps = ItinData->getNumMicroOps(Desc.getSchedClass());
2715  assert(UOps >= 0 && "bad # UOps");
2716  return UOps;
2717  }
2718 
2719  case ARM::LDRrs:
2720  case ARM::LDRBrs:
2721  case ARM::STRrs:
2722  case ARM::STRBrs: {
2723  unsigned ShOpVal = MI->getOperand(3).getImm();
2724  bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2725  unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2726  if (!isSub &&
2727  (ShImm == 0 ||
2728  ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2729  ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2730  return 1;
2731  return 2;
2732  }
2733 
2734  case ARM::LDRH:
2735  case ARM::STRH: {
2736  if (!MI->getOperand(2).getReg())
2737  return 1;
2738 
2739  unsigned ShOpVal = MI->getOperand(3).getImm();
2740  bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2741  unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2742  if (!isSub &&
2743  (ShImm == 0 ||
2744  ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2745  ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2746  return 1;
2747  return 2;
2748  }
2749 
2750  case ARM::LDRSB:
2751  case ARM::LDRSH:
2752  return (ARM_AM::getAM3Op(MI->getOperand(3).getImm()) == ARM_AM::sub) ? 3:2;
2753 
2754  case ARM::LDRSB_POST:
2755  case ARM::LDRSH_POST: {
2756  unsigned Rt = MI->getOperand(0).getReg();
2757  unsigned Rm = MI->getOperand(3).getReg();
2758  return (Rt == Rm) ? 4 : 3;
2759  }
2760 
2761  case ARM::LDR_PRE_REG:
2762  case ARM::LDRB_PRE_REG: {
2763  unsigned Rt = MI->getOperand(0).getReg();
2764  unsigned Rm = MI->getOperand(3).getReg();
2765  if (Rt == Rm)
2766  return 3;
2767  unsigned ShOpVal = MI->getOperand(4).getImm();
2768  bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2769  unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2770  if (!isSub &&
2771  (ShImm == 0 ||
2772  ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2773  ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2774  return 2;
2775  return 3;
2776  }
2777 
2778  case ARM::STR_PRE_REG:
2779  case ARM::STRB_PRE_REG: {
2780  unsigned ShOpVal = MI->getOperand(4).getImm();
2781  bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2782  unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2783  if (!isSub &&
2784  (ShImm == 0 ||
2785  ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2786  ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2787  return 2;
2788  return 3;
2789  }
2790 
2791  case ARM::LDRH_PRE:
2792  case ARM::STRH_PRE: {
2793  unsigned Rt = MI->getOperand(0).getReg();
2794  unsigned Rm = MI->getOperand(3).getReg();
2795  if (!Rm)
2796  return 2;
2797  if (Rt == Rm)
2798  return 3;
2799  return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub)
2800  ? 3 : 2;
2801  }
2802 
2803  case ARM::LDR_POST_REG:
2804  case ARM::LDRB_POST_REG:
2805  case ARM::LDRH_POST: {
2806  unsigned Rt = MI->getOperand(0).getReg();
2807  unsigned Rm = MI->getOperand(3).getReg();
2808  return (Rt == Rm) ? 3 : 2;
2809  }
2810 
2811  case ARM::LDR_PRE_IMM:
2812  case ARM::LDRB_PRE_IMM:
2813  case ARM::LDR_POST_IMM:
2814  case ARM::LDRB_POST_IMM:
2815  case ARM::STRB_POST_IMM:
2816  case ARM::STRB_POST_REG:
2817  case ARM::STRB_PRE_IMM:
2818  case ARM::STRH_POST:
2819  case ARM::STR_POST_IMM:
2820  case ARM::STR_POST_REG:
2821  case ARM::STR_PRE_IMM:
2822  return 2;
2823 
2824  case ARM::LDRSB_PRE:
2825  case ARM::LDRSH_PRE: {
2826  unsigned Rm = MI->getOperand(3).getReg();
2827  if (Rm == 0)
2828  return 3;
2829  unsigned Rt = MI->getOperand(0).getReg();
2830  if (Rt == Rm)
2831  return 4;
2832  unsigned ShOpVal = MI->getOperand(4).getImm();
2833  bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2834  unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2835  if (!isSub &&
2836  (ShImm == 0 ||
2837  ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2838  ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2839  return 3;
2840  return 4;
2841  }
2842 
2843  case ARM::LDRD: {
2844  unsigned Rt = MI->getOperand(0).getReg();
2845  unsigned Rn = MI->getOperand(2).getReg();
2846  unsigned Rm = MI->getOperand(3).getReg();
2847  if (Rm)
2848  return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) ?4:3;
2849  return (Rt == Rn) ? 3 : 2;
2850  }
2851 
2852  case ARM::STRD: {
2853  unsigned Rm = MI->getOperand(3).getReg();
2854  if (Rm)
2855  return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) ?4:3;
2856  return 2;
2857  }
2858 
2859  case ARM::LDRD_POST:
2860  case ARM::t2LDRD_POST:
2861  return 3;
2862 
2863  case ARM::STRD_POST:
2864  case ARM::t2STRD_POST:
2865  return 4;
2866 
2867  case ARM::LDRD_PRE: {
2868  unsigned Rt = MI->getOperand(0).getReg();
2869  unsigned Rn = MI->getOperand(3).getReg();
2870  unsigned Rm = MI->getOperand(4).getReg();
2871  if (Rm)
2872  return (ARM_AM::getAM3Op(MI->getOperand(5).getImm()) == ARM_AM::sub) ?5:4;
2873  return (Rt == Rn) ? 4 : 3;
2874  }
2875 
2876  case ARM::t2LDRD_PRE: {
2877  unsigned Rt = MI->getOperand(0).getReg();
2878  unsigned Rn = MI->getOperand(3).getReg();
2879  return (Rt == Rn) ? 4 : 3;
2880  }
2881 
2882  case ARM::STRD_PRE: {
2883  unsigned Rm = MI->getOperand(4).getReg();
2884  if (Rm)
2885  return (ARM_AM::getAM3Op(MI->getOperand(5).getImm()) == ARM_AM::sub) ?5:4;
2886  return 3;
2887  }
2888 
2889  case ARM::t2STRD_PRE:
2890  return 3;
2891 
2892  case ARM::t2LDR_POST:
2893  case ARM::t2LDRB_POST:
2894  case ARM::t2LDRB_PRE:
2895  case ARM::t2LDRSBi12:
2896  case ARM::t2LDRSBi8:
2897  case ARM::t2LDRSBpci:
2898  case ARM::t2LDRSBs:
2899  case ARM::t2LDRH_POST:
2900  case ARM::t2LDRH_PRE:
2901  case ARM::t2LDRSBT:
2902  case ARM::t2LDRSB_POST:
2903  case ARM::t2LDRSB_PRE:
2904  case ARM::t2LDRSH_POST:
2905  case ARM::t2LDRSH_PRE:
2906  case ARM::t2LDRSHi12:
2907  case ARM::t2LDRSHi8:
2908  case ARM::t2LDRSHpci:
2909  case ARM::t2LDRSHs:
2910  return 2;
2911 
2912  case ARM::t2LDRDi8: {
2913  unsigned Rt = MI->getOperand(0).getReg();
2914  unsigned Rn = MI->getOperand(2).getReg();
2915  return (Rt == Rn) ? 3 : 2;
2916  }
2917 
2918  case ARM::t2STRB_POST:
2919  case ARM::t2STRB_PRE:
2920  case ARM::t2STRBs:
2921  case ARM::t2STRDi8:
2922  case ARM::t2STRH_POST:
2923  case ARM::t2STRH_PRE:
2924  case ARM::t2STRHs:
2925  case ARM::t2STR_POST:
2926  case ARM::t2STR_PRE:
2927  case ARM::t2STRs:
2928  return 2;
2929  }
2930 }
2931 
2932 // Return the number of 32-bit words loaded by LDM or stored by STM. If this
2933 // can't be easily determined return 0 (missing MachineMemOperand).
2934 //
2935 // FIXME: The current MachineInstr design does not support relying on machine
2936 // mem operands to determine the width of a memory access. Instead, we expect
2937 // the target to provide this information based on the instruction opcode and
2938 // operands. However, using MachineMemOperand is the best solution now for
2939 // two reasons:
2940 //
2941 // 1) getNumMicroOps tries to infer LDM memory width from the total number of MI
2942 // operands. This is much more dangerous than using the MachineMemOperand
2943 // sizes because CodeGen passes can insert/remove optional machine operands. In
2944 // fact, it's totally incorrect for preRA passes and appears to be wrong for
2945 // postRA passes as well.
2946 //
2947 // 2) getNumLDMAddresses is only used by the scheduling machine model and any
2948 // machine model that calls this should handle the unknown (zero size) case.
2949 //
2950 // Long term, we should require a target hook that verifies MachineMemOperand
2951 // sizes during MC lowering. That target hook should be local to MC lowering
2952 // because we can't ensure that it is aware of other MI forms. Doing this will
2953 // ensure that MachineMemOperands are correctly propagated through all passes.
2955  unsigned Size = 0;
2957  E = MI->memoperands_end(); I != E; ++I) {
2958  Size += (*I)->getSize();
2959  }
2960  return Size / 4;
2961 }
2962 
2963 unsigned
2965  const MachineInstr *MI) const {
2966  if (!ItinData || ItinData->isEmpty())
2967  return 1;
2968 
2969  const MCInstrDesc &Desc = MI->getDesc();
2970  unsigned Class = Desc.getSchedClass();
2971  int ItinUOps = ItinData->getNumMicroOps(Class);
2972  if (ItinUOps >= 0) {
2973  if (Subtarget.isSwift() && (Desc.mayLoad() || Desc.mayStore()))
2974  return getNumMicroOpsSwiftLdSt(ItinData, MI);
2975 
2976  return ItinUOps;
2977  }
2978 
2979  unsigned Opc = MI->getOpcode();
2980  switch (Opc) {
2981  default:
2982  llvm_unreachable("Unexpected multi-uops instruction!");
2983  case ARM::VLDMQIA:
2984  case ARM::VSTMQIA:
2985  return 2;
2986 
2987  // The number of uOps for load / store multiple are determined by the number
2988  // registers.
2989  //
2990  // On Cortex-A8, each pair of register loads / stores can be scheduled on the
2991  // same cycle. The scheduling for the first load / store must be done
2992  // separately by assuming the address is not 64-bit aligned.
2993  //
2994  // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address
2995  // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON
2996  // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1.
2997  case ARM::VLDMDIA:
2998  case ARM::VLDMDIA_UPD:
2999  case ARM::VLDMDDB_UPD:
3000  case ARM::VLDMSIA:
3001  case ARM::VLDMSIA_UPD:
3002  case ARM::VLDMSDB_UPD:
3003  case ARM::VSTMDIA:
3004  case ARM::VSTMDIA_UPD:
3005  case ARM::VSTMDDB_UPD:
3006  case ARM::VSTMSIA:
3007  case ARM::VSTMSIA_UPD:
3008  case ARM::VSTMSDB_UPD: {
3009  unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands();
3010  return (NumRegs / 2) + (NumRegs % 2) + 1;
3011  }
3012 
3013  case ARM::LDMIA_RET:
3014  case ARM::LDMIA:
3015  case ARM::LDMDA:
3016  case ARM::LDMDB:
3017  case ARM::LDMIB:
3018  case ARM::LDMIA_UPD:
3019  case ARM::LDMDA_UPD:
3020  case ARM::LDMDB_UPD:
3021  case ARM::LDMIB_UPD:
3022  case ARM::STMIA:
3023  case ARM::STMDA:
3024  case ARM::STMDB:
3025  case ARM::STMIB:
3026  case ARM::STMIA_UPD:
3027  case ARM::STMDA_UPD:
3028  case ARM::STMDB_UPD:
3029  case ARM::STMIB_UPD:
3030  case ARM::tLDMIA:
3031  case ARM::tLDMIA_UPD:
3032  case ARM::tSTMIA_UPD:
3033  case ARM::tPOP_RET:
3034  case ARM::tPOP:
3035  case ARM::tPUSH:
3036  case ARM::t2LDMIA_RET:
3037  case ARM::t2LDMIA:
3038  case ARM::t2LDMDB:
3039  case ARM::t2LDMIA_UPD:
3040  case ARM::t2LDMDB_UPD:
3041  case ARM::t2STMIA:
3042  case ARM::t2STMDB:
3043  case ARM::t2STMIA_UPD:
3044  case ARM::t2STMDB_UPD: {
3045  unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1;
3046  if (Subtarget.isSwift()) {
3047  int UOps = 1 + NumRegs; // One for address computation, one for each ld / st.
3048  switch (Opc) {
3049  default: break;
3050  case ARM::VLDMDIA_UPD:
3051  case ARM::VLDMDDB_UPD:
3052  case ARM::VLDMSIA_UPD:
3053  case ARM::VLDMSDB_UPD:
3054  case ARM::VSTMDIA_UPD:
3055  case ARM::VSTMDDB_UPD:
3056  case ARM::VSTMSIA_UPD:
3057  case ARM::VSTMSDB_UPD:
3058  case ARM::LDMIA_UPD:
3059  case ARM::LDMDA_UPD:
3060  case ARM::LDMDB_UPD:
3061  case ARM::LDMIB_UPD:
3062  case ARM::STMIA_UPD:
3063  case ARM::STMDA_UPD:
3064  case ARM::STMDB_UPD:
3065  case ARM::STMIB_UPD:
3066  case ARM::tLDMIA_UPD:
3067  case ARM::tSTMIA_UPD:
3068  case ARM::t2LDMIA_UPD:
3069  case ARM::t2LDMDB_UPD:
3070  case ARM::t2STMIA_UPD:
3071  case ARM::t2STMDB_UPD:
3072  ++UOps; // One for base register writeback.
3073  break;
3074  case ARM::LDMIA_RET:
3075  case ARM::tPOP_RET:
3076  case ARM::t2LDMIA_RET:
3077  UOps += 2; // One for base reg wb, one for write to pc.
3078  break;
3079  }
3080  return UOps;
3081  } else if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3082  if (NumRegs < 4)
3083  return 2;
3084  // 4 registers would be issued: 2, 2.
3085  // 5 registers would be issued: 2, 2, 1.
3086  int A8UOps = (NumRegs / 2);
3087  if (NumRegs % 2)
3088  ++A8UOps;
3089  return A8UOps;
3090  } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3091  int A9UOps = (NumRegs / 2);
3092  // If there are odd number of registers or if it's not 64-bit aligned,
3093  // then it takes an extra AGU (Address Generation Unit) cycle.
3094  if ((NumRegs % 2) ||
3095  !MI->hasOneMemOperand() ||
3096  (*MI->memoperands_begin())->getAlignment() < 8)
3097  ++A9UOps;
3098  return A9UOps;
3099  } else {
3100  // Assume the worst.
3101  return NumRegs;
3102  }
3103  }
3104  }
3105 }
3106 
3107 int
3108 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
3109  const MCInstrDesc &DefMCID,
3110  unsigned DefClass,
3111  unsigned DefIdx, unsigned DefAlign) const {
3112  int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3113  if (RegNo <= 0)
3114  // Def is the address writeback.
3115  return ItinData->getOperandCycle(DefClass, DefIdx);
3116 
3117  int DefCycle;
3118  if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3119  // (regno / 2) + (regno % 2) + 1
3120  DefCycle = RegNo / 2 + 1;
3121  if (RegNo % 2)
3122  ++DefCycle;
3123  } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3124  DefCycle = RegNo;
3125  bool isSLoad = false;
3126 
3127  switch (DefMCID.getOpcode()) {
3128  default: break;
3129  case ARM::VLDMSIA:
3130  case ARM::VLDMSIA_UPD:
3131  case ARM::VLDMSDB_UPD:
3132  isSLoad = true;
3133  break;
3134  }
3135 
3136  // If there are odd number of 'S' registers or if it's not 64-bit aligned,
3137  // then it takes an extra cycle.
3138  if ((isSLoad && (RegNo % 2)) || DefAlign < 8)
3139  ++DefCycle;
3140  } else {
3141  // Assume the worst.
3142  DefCycle = RegNo + 2;
3143  }
3144 
3145  return DefCycle;
3146 }
3147 
3148 int
3149 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
3150  const MCInstrDesc &DefMCID,
3151  unsigned DefClass,
3152  unsigned DefIdx, unsigned DefAlign) const {
3153  int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3154  if (RegNo <= 0)
3155  // Def is the address writeback.
3156  return ItinData->getOperandCycle(DefClass, DefIdx);
3157 
3158  int DefCycle;
3159  if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3160  // 4 registers would be issued: 1, 2, 1.
3161  // 5 registers would be issued: 1, 2, 2.
3162  DefCycle = RegNo / 2;
3163  if (DefCycle < 1)
3164  DefCycle = 1;
3165  // Result latency is issue cycle + 2: E2.
3166  DefCycle += 2;
3167  } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3168  DefCycle = (RegNo / 2);
3169  // If there are odd number of registers or if it's not 64-bit aligned,
3170  // then it takes an extra AGU (Address Generation Unit) cycle.
3171  if ((RegNo % 2) || DefAlign < 8)
3172  ++DefCycle;
3173  // Result latency is AGU cycles + 2.
3174  DefCycle += 2;
3175  } else {
3176  // Assume the worst.
3177  DefCycle = RegNo + 2;
3178  }
3179 
3180  return DefCycle;
3181 }
3182 
3183 int
3184 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
3185  const MCInstrDesc &UseMCID,
3186  unsigned UseClass,
3187  unsigned UseIdx, unsigned UseAlign) const {
3188  int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
3189  if (RegNo <= 0)
3190  return ItinData->getOperandCycle(UseClass, UseIdx);
3191 
3192  int UseCycle;
3193  if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3194  // (regno / 2) + (regno % 2) + 1
3195  UseCycle = RegNo / 2 + 1;
3196  if (RegNo % 2)
3197  ++UseCycle;
3198  } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3199  UseCycle = RegNo;
3200  bool isSStore = false;
3201 
3202  switch (UseMCID.getOpcode()) {
3203  default: break;
3204  case ARM::VSTMSIA:
3205  case ARM::VSTMSIA_UPD:
3206  case ARM::VSTMSDB_UPD:
3207  isSStore = true;
3208  break;
3209  }
3210 
3211  // If there are odd number of 'S' registers or if it's not 64-bit aligned,
3212  // then it takes an extra cycle.
3213  if ((isSStore && (RegNo % 2)) || UseAlign < 8)
3214  ++UseCycle;
3215  } else {
3216  // Assume the worst.
3217  UseCycle = RegNo + 2;
3218  }
3219 
3220  return UseCycle;
3221 }
3222 
3223 int
3224 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
3225  const MCInstrDesc &UseMCID,
3226  unsigned UseClass,
3227  unsigned UseIdx, unsigned UseAlign) const {
3228  int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
3229  if (RegNo <= 0)
3230  return ItinData->getOperandCycle(UseClass, UseIdx);
3231 
3232  int UseCycle;
3233  if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3234  UseCycle = RegNo / 2;
3235  if (UseCycle < 2)
3236  UseCycle = 2;
3237  // Read in E3.
3238  UseCycle += 2;
3239  } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3240  UseCycle = (RegNo / 2);
3241  // If there are odd number of registers or if it's not 64-bit aligned,
3242  // then it takes an extra AGU (Address Generation Unit) cycle.
3243  if ((RegNo % 2) || UseAlign < 8)
3244  ++UseCycle;
3245  } else {
3246  // Assume the worst.
3247  UseCycle = 1;
3248  }
3249  return UseCycle;
3250 }
3251 
3252 int
3254  const MCInstrDesc &DefMCID,
3255  unsigned DefIdx, unsigned DefAlign,
3256  const MCInstrDesc &UseMCID,
3257  unsigned UseIdx, unsigned UseAlign) const {
3258  unsigned DefClass = DefMCID.getSchedClass();
3259  unsigned UseClass = UseMCID.getSchedClass();
3260 
3261  if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
3262  return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
3263 
3264  // This may be a def / use of a variable_ops instruction, the operand
3265  // latency might be determinable dynamically. Let the target try to
3266  // figure it out.
3267  int DefCycle = -1;
3268  bool LdmBypass = false;
3269  switch (DefMCID.getOpcode()) {
3270  default:
3271  DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
3272  break;
3273 
3274  case ARM::VLDMDIA:
3275  case ARM::VLDMDIA_UPD:
3276  case ARM::VLDMDDB_UPD:
3277  case ARM::VLDMSIA:
3278  case ARM::VLDMSIA_UPD:
3279  case ARM::VLDMSDB_UPD:
3280  DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
3281  break;
3282 
3283  case ARM::LDMIA_RET:
3284  case ARM::LDMIA:
3285  case ARM::LDMDA:
3286  case ARM::LDMDB:
3287  case ARM::LDMIB:
3288  case ARM::LDMIA_UPD:
3289  case ARM::LDMDA_UPD:
3290  case ARM::LDMDB_UPD:
3291  case ARM::LDMIB_UPD:
3292  case ARM::tLDMIA:
3293  case ARM::tLDMIA_UPD:
3294  case ARM::tPUSH:
3295  case ARM::t2LDMIA_RET:
3296  case ARM::t2LDMIA:
3297  case ARM::t2LDMDB:
3298  case ARM::t2LDMIA_UPD:
3299  case ARM::t2LDMDB_UPD:
3300  LdmBypass = 1;
3301  DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
3302  break;
3303  }
3304 
3305  if (DefCycle == -1)
3306  // We can't seem to determine the result latency of the def, assume it's 2.
3307  DefCycle = 2;
3308 
3309  int UseCycle = -1;
3310  switch (UseMCID.getOpcode()) {
3311  default:
3312  UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
3313  break;
3314 
3315  case ARM::VSTMDIA:
3316  case ARM::VSTMDIA_UPD:
3317  case ARM::VSTMDDB_UPD:
3318  case ARM::VSTMSIA:
3319  case ARM::VSTMSIA_UPD:
3320  case ARM::VSTMSDB_UPD:
3321  UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
3322  break;
3323 
3324  case ARM::STMIA:
3325  case ARM::STMDA:
3326  case ARM::STMDB:
3327  case ARM::STMIB:
3328  case ARM::STMIA_UPD:
3329  case ARM::STMDA_UPD:
3330  case ARM::STMDB_UPD:
3331  case ARM::STMIB_UPD:
3332  case ARM::tSTMIA_UPD:
3333  case ARM::tPOP_RET:
3334  case ARM::tPOP:
3335  case ARM::t2STMIA:
3336  case ARM::t2STMDB:
3337  case ARM::t2STMIA_UPD:
3338  case ARM::t2STMDB_UPD:
3339  UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
3340  break;
3341  }
3342 
3343  if (UseCycle == -1)
3344  // Assume it's read in the first stage.
3345  UseCycle = 1;
3346 
3347  UseCycle = DefCycle - UseCycle + 1;
3348  if (UseCycle > 0) {
3349  if (LdmBypass) {
3350  // It's a variable_ops instruction so we can't use DefIdx here. Just use
3351  // first def operand.
3352  if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1,
3353  UseClass, UseIdx))
3354  --UseCycle;
3355  } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
3356  UseClass, UseIdx)) {
3357  --UseCycle;
3358  }
3359  }
3360 
3361  return UseCycle;
3362 }
3363 
3365  const MachineInstr *MI, unsigned Reg,
3366  unsigned &DefIdx, unsigned &Dist) {
3367  Dist = 0;
3368 
3370  MachineBasicBlock::const_instr_iterator II = std::prev(I.getInstrIterator());
3371  assert(II->isInsideBundle() && "Empty bundle?");
3372 
3373  int Idx = -1;
3374  while (II->isInsideBundle()) {
3375  Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI);
3376  if (Idx != -1)
3377  break;
3378  --II;
3379  ++Dist;
3380  }
3381 
3382  assert(Idx != -1 && "Cannot find bundled definition!");
3383  DefIdx = Idx;
3384  return II;
3385 }
3386 
3388  const MachineInstr *MI, unsigned Reg,
3389  unsigned &UseIdx, unsigned &Dist) {
3390  Dist = 0;
3391 
3393  assert(II->isInsideBundle() && "Empty bundle?");
3395 
3396  // FIXME: This doesn't properly handle multiple uses.
3397  int Idx = -1;
3398  while (II != E && II->isInsideBundle()) {
3399  Idx = II->findRegisterUseOperandIdx(Reg, false, TRI);
3400  if (Idx != -1)
3401  break;
3402  if (II->getOpcode() != ARM::t2IT)
3403  ++Dist;
3404  ++II;
3405  }
3406 
3407  if (Idx == -1) {
3408  Dist = 0;
3409  return nullptr;
3410  }
3411 
3412  UseIdx = Idx;
3413  return II;
3414 }
3415 
3416 /// Return the number of cycles to add to (or subtract from) the static
3417 /// itinerary based on the def opcode and alignment. The caller will ensure that
3418 /// adjusted latency is at least one cycle.
3419 static int adjustDefLatency(const ARMSubtarget &Subtarget,
3420  const MachineInstr *DefMI,
3421  const MCInstrDesc *DefMCID, unsigned DefAlign) {
3422  int Adjust = 0;
3423  if (Subtarget.isCortexA8() || Subtarget.isLikeA9() || Subtarget.isCortexA7()) {
3424  // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
3425  // variants are one cycle cheaper.
3426  switch (DefMCID->getOpcode()) {
3427  default: break;
3428  case ARM::LDRrs:
3429  case ARM::LDRBrs: {
3430  unsigned ShOpVal = DefMI->getOperand(3).getImm();
3431  unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3432  if (ShImm == 0 ||
3433  (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3434  --Adjust;
3435  break;
3436  }
3437  case ARM::t2LDRs:
3438  case ARM::t2LDRBs:
3439  case ARM::t2LDRHs:
3440  case ARM::t2LDRSHs: {
3441  // Thumb2 mode: lsl only.
3442  unsigned ShAmt = DefMI->getOperand(3).getImm();
3443  if (ShAmt == 0 || ShAmt == 2)
3444  --Adjust;
3445  break;
3446  }
3447  }
3448  } else if (Subtarget.isSwift()) {
3449  // FIXME: Properly handle all of the latency adjustments for address
3450  // writeback.
3451  switch (DefMCID->getOpcode()) {
3452  default: break;
3453  case ARM::LDRrs:
3454  case ARM::LDRBrs: {
3455  unsigned ShOpVal = DefMI->getOperand(3).getImm();
3456  bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
3457  unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3458  if (!isSub &&
3459  (ShImm == 0 ||
3460  ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3461  ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
3462  Adjust -= 2;
3463  else if (!isSub &&
3464  ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr)
3465  --Adjust;
3466  break;
3467  }
3468  case ARM::t2LDRs:
3469  case ARM::t2LDRBs:
3470  case ARM::t2LDRHs:
3471  case ARM::t2LDRSHs: {
3472  // Thumb2 mode: lsl only.
3473  unsigned ShAmt = DefMI->getOperand(3).getImm();
3474  if (ShAmt == 0 || ShAmt == 1 || ShAmt == 2 || ShAmt == 3)
3475  Adjust -= 2;
3476  break;
3477  }
3478  }
3479  }
3480 
3481  if (DefAlign < 8 && Subtarget.isLikeA9()) {
3482  switch (DefMCID->getOpcode()) {
3483  default: break;
3484  case ARM::VLD1q8:
3485  case ARM::VLD1q16:
3486  case ARM::VLD1q32:
3487  case ARM::VLD1q64:
3488  case ARM::VLD1q8wb_fixed:
3489  case ARM::VLD1q16wb_fixed:
3490  case ARM::VLD1q32wb_fixed:
3491  case ARM::VLD1q64wb_fixed:
3492  case ARM::VLD1q8wb_register:
3493  case ARM::VLD1q16wb_register:
3494  case ARM::VLD1q32wb_register:
3495  case ARM::VLD1q64wb_register:
3496  case ARM::VLD2d8:
3497  case ARM::VLD2d16:
3498  case ARM::VLD2d32:
3499  case ARM::VLD2q8:
3500  case ARM::VLD2q16:
3501  case ARM::VLD2q32:
3502  case ARM::VLD2d8wb_fixed:
3503  case ARM::VLD2d16wb_fixed:
3504  case ARM::VLD2d32wb_fixed:
3505  case ARM::VLD2q8wb_fixed:
3506  case ARM::VLD2q16wb_fixed:
3507  case ARM::VLD2q32wb_fixed:
3508  case ARM::VLD2d8wb_register:
3509  case ARM::VLD2d16wb_register:
3510  case ARM::VLD2d32wb_register:
3511  case ARM::VLD2q8wb_register:
3512  case ARM::VLD2q16wb_register:
3513  case ARM::VLD2q32wb_register:
3514  case ARM::VLD3d8:
3515  case ARM::VLD3d16:
3516  case ARM::VLD3d32:
3517  case ARM::VLD1d64T:
3518  case ARM::VLD3d8_UPD:
3519  case ARM::VLD3d16_UPD:
3520  case ARM::VLD3d32_UPD:
3521  case ARM::VLD1d64Twb_fixed:
3522  case ARM::VLD1d64Twb_register:
3523  case ARM::VLD3q8_UPD:
3524  case ARM::VLD3q16_UPD:
3525  case ARM::VLD3q32_UPD:
3526  case ARM::VLD4d8:
3527  case ARM::VLD4d16:
3528  case ARM::VLD4d32:
3529  case ARM::VLD1d64Q:
3530  case ARM::VLD4d8_UPD:
3531  case ARM::VLD4d16_UPD:
3532  case ARM::VLD4d32_UPD:
3533  case ARM::VLD1d64Qwb_fixed:
3534  case ARM::VLD1d64Qwb_register:
3535  case ARM::VLD4q8_UPD:
3536  case ARM::VLD4q16_UPD:
3537  case ARM::VLD4q32_UPD:
3538  case ARM::VLD1DUPq8:
3539  case ARM::VLD1DUPq16:
3540  case ARM::VLD1DUPq32:
3541  case ARM::VLD1DUPq8wb_fixed:
3542  case ARM::VLD1DUPq16wb_fixed:
3543  case ARM::VLD1DUPq32wb_fixed:
3544  case ARM::VLD1DUPq8wb_register:
3545  case ARM::VLD1DUPq16wb_register:
3546  case ARM::VLD1DUPq32wb_register:
3547  case ARM::VLD2DUPd8:
3548  case ARM::VLD2DUPd16:
3549  case ARM::VLD2DUPd32:
3550  case ARM::VLD2DUPd8wb_fixed:
3551  case ARM::VLD2DUPd16wb_fixed:
3552  case ARM::VLD2DUPd32wb_fixed:
3553  case ARM::VLD2DUPd8wb_register:
3554  case ARM::VLD2DUPd16wb_register:
3555  case ARM::VLD2DUPd32wb_register:
3556  case ARM::VLD4DUPd8:
3557  case ARM::VLD4DUPd16:
3558  case ARM::VLD4DUPd32:
3559  case ARM::VLD4DUPd8_UPD:
3560  case ARM::VLD4DUPd16_UPD:
3561  case ARM::VLD4DUPd32_UPD:
3562  case ARM::VLD1LNd8:
3563  case ARM::VLD1LNd16:
3564  case ARM::VLD1LNd32:
3565  case ARM::VLD1LNd8_UPD:
3566  case ARM::VLD1LNd16_UPD:
3567  case ARM::VLD1LNd32_UPD:
3568  case ARM::VLD2LNd8:
3569  case ARM::VLD2LNd16:
3570  case ARM::VLD2LNd32:
3571  case ARM::VLD2LNq16:
3572  case ARM::VLD2LNq32:
3573  case ARM::VLD2LNd8_UPD:
3574  case ARM::VLD2LNd16_UPD:
3575  case ARM::VLD2LNd32_UPD:
3576  case ARM::VLD2LNq16_UPD:
3577  case ARM::VLD2LNq32_UPD:
3578  case ARM::VLD4LNd8:
3579  case ARM::VLD4LNd16:
3580  case ARM::VLD4LNd32:
3581  case ARM::VLD4LNq16:
3582  case ARM::VLD4LNq32:
3583  case ARM::VLD4LNd8_UPD:
3584  case ARM::VLD4LNd16_UPD:
3585  case ARM::VLD4LNd32_UPD:
3586  case ARM::VLD4LNq16_UPD:
3587  case ARM::VLD4LNq32_UPD:
3588  // If the address is not 64-bit aligned, the latencies of these
3589  // instructions increases by one.
3590  ++Adjust;
3591  break;
3592  }
3593  }
3594  return Adjust;
3595 }
3596 
3597 
3598 
3599 int
3601  const MachineInstr *DefMI, unsigned DefIdx,
3602  const MachineInstr *UseMI,
3603  unsigned UseIdx) const {
3604  // No operand latency. The caller may fall back to getInstrLatency.
3605  if (!ItinData || ItinData->isEmpty())
3606  return -1;
3607 
3608  const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
3609  unsigned Reg = DefMO.getReg();
3610  const MCInstrDesc *DefMCID = &DefMI->getDesc();
3611  const MCInstrDesc *UseMCID = &UseMI->getDesc();
3612 
3613  unsigned DefAdj = 0;
3614  if (DefMI->isBundle()) {
3615  DefMI = getBundledDefMI(&getRegisterInfo(), DefMI, Reg, DefIdx, DefAdj);
3616  DefMCID = &DefMI->getDesc();
3617  }
3618  if (DefMI->isCopyLike() || DefMI->isInsertSubreg() ||
3619  DefMI->isRegSequence() || DefMI->isImplicitDef()) {
3620  return 1;
3621  }
3622 
3623  unsigned UseAdj = 0;
3624  if (UseMI->isBundle()) {
3625  unsigned NewUseIdx;
3626  const MachineInstr *NewUseMI = getBundledUseMI(&getRegisterInfo(), UseMI,
3627  Reg, NewUseIdx, UseAdj);
3628  if (!NewUseMI)
3629  return -1;
3630 
3631  UseMI = NewUseMI;
3632  UseIdx = NewUseIdx;
3633  UseMCID = &UseMI->getDesc();
3634  }
3635 
3636  if (Reg == ARM::CPSR) {
3637  if (DefMI->getOpcode() == ARM::FMSTAT) {
3638  // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?)
3639  return Subtarget.isLikeA9() ? 1 : 20;
3640  }
3641 
3642  // CPSR set and branch can be paired in the same cycle.
3643  if (UseMI->isBranch())
3644  return 0;
3645 
3646  // Otherwise it takes the instruction latency (generally one).
3647  unsigned Latency = getInstrLatency(ItinData, DefMI);
3648 
3649  // For Thumb2 and -Os, prefer scheduling CPSR setting instruction close to
3650  // its uses. Instructions which are otherwise scheduled between them may
3651  // incur a code size penalty (not able to use the CPSR setting 16-bit
3652  // instructions).
3653  if (Latency > 0 && Subtarget.isThumb2()) {
3654  const MachineFunction *MF = DefMI->getParent()->getParent();
3656  --Latency;
3657  }
3658  return Latency;
3659  }
3660 
3661  if (DefMO.isImplicit() || UseMI->getOperand(UseIdx).isImplicit())
3662  return -1;
3663 
3664  unsigned DefAlign = DefMI->hasOneMemOperand()
3665  ? (*DefMI->memoperands_begin())->getAlignment() : 0;
3666  unsigned UseAlign = UseMI->hasOneMemOperand()
3667  ? (*UseMI->memoperands_begin())->getAlignment() : 0;
3668 
3669  // Get the itinerary's latency if possible, and handle variable_ops.
3670  int Latency = getOperandLatency(ItinData, *DefMCID, DefIdx, DefAlign,
3671  *UseMCID, UseIdx, UseAlign);
3672  // Unable to find operand latency. The caller may resort to getInstrLatency.
3673  if (Latency < 0)
3674  return Latency;
3675 
3676  // Adjust for IT block position.
3677  int Adj = DefAdj + UseAdj;
3678 
3679  // Adjust for dynamic def-side opcode variants not captured by the itinerary.
3680  Adj += adjustDefLatency(Subtarget, DefMI, DefMCID, DefAlign);
3681  if (Adj >= 0 || (int)Latency > -Adj) {
3682  return Latency + Adj;
3683  }
3684  // Return the itinerary latency, which may be zero but not less than zero.
3685  return Latency;
3686 }
3687 
3688 int
3690  SDNode *DefNode, unsigned DefIdx,
3691  SDNode *UseNode, unsigned UseIdx) const {
3692  if (!DefNode->isMachineOpcode())
3693  return 1;
3694 
3695  const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode());
3696 
3697  if (isZeroCost(DefMCID.Opcode))
3698  return 0;
3699 
3700  if (!ItinData || ItinData->isEmpty())
3701  return DefMCID.mayLoad() ? 3 : 1;
3702 
3703  if (!UseNode->isMachineOpcode()) {
3704  int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
3705  if (Subtarget.isLikeA9() || Subtarget.isSwift())
3706  return Latency <= 2 ? 1 : Latency - 1;
3707  else
3708  return Latency <= 3 ? 1 : Latency - 2;
3709  }
3710 
3711  const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode());
3712  const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode);
3713  unsigned DefAlign = !DefMN->memoperands_empty()
3714  ? (*DefMN->memoperands_begin())->getAlignment() : 0;
3715  const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode);
3716  unsigned UseAlign = !UseMN->memoperands_empty()
3717  ? (*UseMN->memoperands_begin())->getAlignment() : 0;
3718  int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
3719  UseMCID, UseIdx, UseAlign);
3720 
3721  if (Latency > 1 &&
3722  (Subtarget.isCortexA8() || Subtarget.isLikeA9() ||
3723  Subtarget.isCortexA7())) {
3724  // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
3725  // variants are one cycle cheaper.
3726  switch (DefMCID.getOpcode()) {
3727  default: break;
3728  case ARM::LDRrs:
3729  case ARM::LDRBrs: {
3730  unsigned ShOpVal =
3731  cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3732  unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3733  if (ShImm == 0 ||
3734  (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3735  --Latency;
3736  break;
3737  }
3738  case ARM::t2LDRs:
3739  case ARM::t2LDRBs:
3740  case ARM::t2LDRHs:
3741  case ARM::t2LDRSHs: {
3742  // Thumb2 mode: lsl only.
3743  unsigned ShAmt =
3744  cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3745  if (ShAmt == 0 || ShAmt == 2)
3746  --Latency;
3747  break;
3748  }
3749  }
3750  } else if (DefIdx == 0 && Latency > 2 && Subtarget.isSwift()) {
3751  // FIXME: Properly handle all of the latency adjustments for address
3752  // writeback.
3753  switch (DefMCID.getOpcode()) {
3754  default: break;
3755  case ARM::LDRrs:
3756  case ARM::LDRBrs: {
3757  unsigned ShOpVal =
3758  cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3759  unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3760  if (ShImm == 0 ||
3761  ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3762  ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3763  Latency -= 2;
3764  else if (ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr)
3765  --Latency;
3766  break;
3767  }
3768  case ARM::t2LDRs:
3769  case ARM::t2LDRBs:
3770  case ARM::t2LDRHs:
3771  case ARM::t2LDRSHs: {
3772  // Thumb2 mode: lsl 0-3 only.
3773  Latency -= 2;
3774  break;
3775  }
3776  }
3777  }
3778 
3779  if (DefAlign < 8 && Subtarget.isLikeA9())
3780  switch (DefMCID.getOpcode()) {
3781  default: break;
3782  case ARM::VLD1q8:
3783  case ARM::VLD1q16:
3784  case ARM::VLD1q32:
3785  case ARM::VLD1q64:
3786  case ARM::VLD1q8wb_register:
3787  case ARM::VLD1q16wb_register:
3788  case ARM::VLD1q32wb_register:
3789  case ARM::VLD1q64wb_register:
3790  case ARM::VLD1q8wb_fixed:
3791  case ARM::VLD1q16wb_fixed:
3792  case ARM::VLD1q32wb_fixed:
3793  case ARM::VLD1q64wb_fixed:
3794  case ARM::VLD2d8:
3795  case ARM::VLD2d16:
3796  case ARM::VLD2d32:
3797  case ARM::VLD2q8Pseudo:
3798  case ARM::VLD2q16Pseudo:
3799  case ARM::VLD2q32Pseudo:
3800  case ARM::VLD2d8wb_fixed:
3801  case ARM::VLD2d16wb_fixed:
3802  case ARM::VLD2d32wb_fixed:
3803  case ARM::VLD2q8PseudoWB_fixed:
3804  case ARM::VLD2q16PseudoWB_fixed:
3805  case ARM::VLD2q32PseudoWB_fixed:
3806  case ARM::VLD2d8wb_register:
3807  case ARM::VLD2d16wb_register:
3808  case ARM::VLD2d32wb_register:
3809  case ARM::VLD2q8PseudoWB_register:
3810  case ARM::VLD2q16PseudoWB_register:
3811  case ARM::VLD2q32PseudoWB_register:
3812  case ARM::VLD3d8Pseudo:
3813  case ARM::VLD3d16Pseudo:
3814  case ARM::VLD3d32Pseudo:
3815  case ARM::VLD1d64TPseudo:
3816  case ARM::VLD1d64TPseudoWB_fixed:
3817  case ARM::VLD3d8Pseudo_UPD:
3818  case ARM::VLD3d16Pseudo_UPD:
3819  case ARM::VLD3d32Pseudo_UPD:
3820  case ARM::VLD3q8Pseudo_UPD:
3821  case ARM::VLD3q16Pseudo_UPD:
3822  case ARM::VLD3q32Pseudo_UPD:
3823  case ARM::VLD3q8oddPseudo:
3824  case ARM::VLD3q16oddPseudo:
3825  case ARM::VLD3q32oddPseudo:
3826  case ARM::VLD3q8oddPseudo_UPD:
3827  case ARM::VLD3q16oddPseudo_UPD:
3828  case ARM::VLD3q32oddPseudo_UPD:
3829  case ARM::VLD4d8Pseudo:
3830  case ARM::VLD4d16Pseudo:
3831  case ARM::VLD4d32Pseudo:
3832  case ARM::VLD1d64QPseudo:
3833  case ARM::VLD1d64QPseudoWB_fixed:
3834  case ARM::VLD4d8Pseudo_UPD:
3835  case ARM::VLD4d16Pseudo_UPD:
3836  case ARM::VLD4d32Pseudo_UPD:
3837  case ARM::VLD4q8Pseudo_UPD:
3838  case ARM::VLD4q16Pseudo_UPD:
3839  case ARM::VLD4q32Pseudo_UPD:
3840  case ARM::VLD4q8oddPseudo:
3841  case ARM::VLD4q16oddPseudo:
3842  case ARM::VLD4q32oddPseudo:
3843  case ARM::VLD4q8oddPseudo_UPD:
3844  case ARM::VLD4q16oddPseudo_UPD:
3845  case ARM::VLD4q32oddPseudo_UPD:
3846  case ARM::VLD1DUPq8:
3847  case ARM::VLD1DUPq16:
3848  case ARM::VLD1DUPq32:
3849  case ARM::VLD1DUPq8wb_fixed:
3850  case ARM::VLD1DUPq16wb_fixed:
3851  case ARM::VLD1DUPq32wb_fixed:
3852  case ARM::VLD1DUPq8wb_register:
3853  case ARM::VLD1DUPq16wb_register:
3854  case ARM::VLD1DUPq32wb_register:
3855  case ARM::VLD2DUPd8:
3856  case ARM::VLD2DUPd16:
3857  case ARM::VLD2DUPd32:
3858  case ARM::VLD2DUPd8wb_fixed:
3859  case ARM::VLD2DUPd16wb_fixed:
3860  case ARM::VLD2DUPd32wb_fixed:
3861  case ARM::VLD2DUPd8wb_register:
3862  case ARM::VLD2DUPd16wb_register:
3863  case ARM::VLD2DUPd32wb_register:
3864  case ARM::VLD4DUPd8Pseudo:
3865  case ARM::VLD4DUPd16Pseudo:
3866  case ARM::VLD4DUPd32Pseudo:
3867  case ARM::VLD4DUPd8Pseudo_UPD:
3868  case ARM::VLD4DUPd16Pseudo_UPD:
3869  case ARM::VLD4DUPd32Pseudo_UPD:
3870  case ARM::VLD1LNq8Pseudo:
3871  case ARM::VLD1LNq16Pseudo:
3872  case ARM::VLD1LNq32Pseudo:
3873  case ARM::VLD1LNq8Pseudo_UPD:
3874  case ARM::VLD1LNq16Pseudo_UPD:
3875  case ARM::VLD1LNq32Pseudo_UPD:
3876  case ARM::VLD2LNd8Pseudo:
3877  case ARM::VLD2LNd16Pseudo:
3878  case ARM::VLD2LNd32Pseudo:
3879  case ARM::VLD2LNq16Pseudo:
3880  case ARM::VLD2LNq32Pseudo:
3881  case ARM::VLD2LNd8Pseudo_UPD:
3882  case ARM::VLD2LNd16Pseudo_UPD:
3883  case ARM::VLD2LNd32Pseudo_UPD:
3884  case ARM::VLD2LNq16Pseudo_UPD:
3885  case ARM::VLD2LNq32Pseudo_UPD:
3886  case ARM::VLD4LNd8Pseudo:
3887  case ARM::VLD4LNd16Pseudo:
3888  case ARM::VLD4LNd32Pseudo:
3889  case ARM::VLD4LNq16Pseudo:
3890  case ARM::VLD4LNq32Pseudo:
3891  case ARM::VLD4LNd8Pseudo_UPD:
3892  case ARM::VLD4LNd16Pseudo_UPD:
3893  case ARM::VLD4LNd32Pseudo_UPD:
3894  case ARM::VLD4LNq16Pseudo_UPD:
3895  case ARM::VLD4LNq32Pseudo_UPD:
3896  // If the address is not 64-bit aligned, the latencies of these
3897  // instructions increases by one.
3898  ++Latency;
3899  break;
3900  }
3901 
3902  return Latency;
3903 }
3904 
3905 unsigned ARMBaseInstrInfo::getPredicationCost(const MachineInstr *MI) const {
3906  if (MI->isCopyLike() || MI->isInsertSubreg() ||
3907  MI->isRegSequence() || MI->isImplicitDef())
3908  return 0;
3909 
3910  if (MI->isBundle())
3911  return 0;
3912 
3913  const MCInstrDesc &MCID = MI->getDesc();
3914 
3915  if (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR)) {
3916  // When predicated, CPSR is an additional source operand for CPSR updating
3917  // instructions, this apparently increases their latencies.
3918  return 1;
3919  }
3920  return 0;
3921 }
3922 
3923 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
3924  const MachineInstr *MI,
3925  unsigned *PredCost) const {
3926  if (MI->isCopyLike() || MI->isInsertSubreg() ||
3927  MI->isRegSequence() || MI->isImplicitDef())
3928  return 1;
3929 
3930  // An instruction scheduler typically runs on unbundled instructions, however
3931  // other passes may query the latency of a bundled instruction.
3932  if (MI->isBundle()) {
3933  unsigned Latency = 0;
3936  while (++I != E && I->isInsideBundle()) {
3937  if (I->getOpcode() != ARM::t2IT)
3938  Latency += getInstrLatency(ItinData, I, PredCost);
3939  }
3940  return Latency;
3941  }
3942 
3943  const MCInstrDesc &MCID = MI->getDesc();
3944  if (PredCost && (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR))) {
3945  // When predicated, CPSR is an additional source operand for CPSR updating
3946  // instructions, this apparently increases their latencies.
3947  *PredCost = 1;
3948  }
3949  // Be sure to call getStageLatency for an empty itinerary in case it has a
3950  // valid MinLatency property.
3951  if (!ItinData)
3952  return MI->mayLoad() ? 3 : 1;
3953 
3954  unsigned Class = MCID.getSchedClass();
3955 
3956  // For instructions with variable uops, use uops as latency.
3957  if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0)
3958  return getNumMicroOps(ItinData, MI);
3959 
3960  // For the common case, fall back on the itinerary's latency.
3961  unsigned Latency = ItinData->getStageLatency(Class);
3962 
3963  // Adjust for dynamic def-side opcode variants not captured by the itinerary.
3964  unsigned DefAlign = MI->hasOneMemOperand()
3965  ? (*MI->memoperands_begin())->getAlignment() : 0;
3966  int Adj = adjustDefLatency(Subtarget, MI, &MCID, DefAlign);
3967  if (Adj >= 0 || (int)Latency > -Adj) {
3968  return Latency + Adj;
3969  }
3970  return Latency;
3971 }
3972 
3973 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
3974  SDNode *Node) const {
3975  if (!Node->isMachineOpcode())
3976  return 1;
3977 
3978  if (!ItinData || ItinData->isEmpty())
3979  return 1;
3980 
3981  unsigned Opcode = Node->getMachineOpcode();
3982  switch (Opcode) {
3983  default:
3984  return ItinData->getStageLatency(get(Opcode).getSchedClass());
3985  case ARM::VLDMQIA:
3986  case ARM::VSTMQIA:
3987  return 2;
3988  }
3989 }
3990 
3991 bool ARMBaseInstrInfo::
3992 hasHighOperandLatency(const TargetSchedModel &SchedModel,
3993  const MachineRegisterInfo *MRI,
3994  const MachineInstr *DefMI, unsigned DefIdx,
3995  const MachineInstr *UseMI, unsigned UseIdx) const {
3996  unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
3997  unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask;
3998  if (Subtarget.isCortexA8() &&
3999  (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP))
4000  // CortexA8 VFP instructions are not pipelined.
4001  return true;
4002 
4003  // Hoist VFP / NEON instructions with 4 or higher latency.
4004  unsigned Latency
4005  = SchedModel.computeOperandLatency(DefMI, DefIdx, UseMI, UseIdx);
4006  if (Latency <= 3)
4007  return false;
4008  return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON ||
4009  UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON;
4010 }
4011 
4012 bool ARMBaseInstrInfo::
4013 hasLowDefLatency(const TargetSchedModel &SchedModel,
4014  const MachineInstr *DefMI, unsigned DefIdx) const {
4015  const InstrItineraryData *ItinData = SchedModel.getInstrItineraries();
4016  if (!ItinData || ItinData->isEmpty())
4017  return false;
4018 
4019  unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
4020  if (DDomain == ARMII::DomainGeneral) {
4021  unsigned DefClass = DefMI->getDesc().getSchedClass();
4022  int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
4023  return (DefCycle != -1 && DefCycle <= 2);
4024  }
4025  return false;
4026 }
4027 
4028 bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr *MI,
4029  StringRef &ErrInfo) const {
4030  if (convertAddSubFlagsOpcode(MI->getOpcode())) {
4031  ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG";
4032  return false;
4033  }
4034  return true;
4035 }
4036 
4037 // LoadStackGuard has so far only been implemented for MachO. Different code
4038 // sequence is needed for other targets.
4040  unsigned LoadImmOpc,
4041  unsigned LoadOpc,
4042  Reloc::Model RM) const {
4043  MachineBasicBlock &MBB = *MI->getParent();
4044  DebugLoc DL = MI->getDebugLoc();
4045  unsigned Reg = MI->getOperand(0).getReg();
4046  const GlobalValue *GV =
4047  cast<GlobalValue>((*MI->memoperands_begin())->getValue());
4048  MachineInstrBuilder MIB;
4049 
4050  BuildMI(MBB, MI, DL, get(LoadImmOpc), Reg)
4052 
4053  if (Subtarget.GVIsIndirectSymbol(GV, RM)) {
4054  MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg);
4055  MIB.addReg(Reg, RegState::Kill).addImm(0);
4057  MachineMemOperand *MMO = MBB.getParent()->
4058  getMachineMemOperand(MachinePointerInfo::getGOT(), Flag, 4, 4);
4059  MIB.addMemOperand(MMO);
4060  AddDefaultPred(MIB);
4061  }
4062 
4063  MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg);
4064  MIB.addReg(Reg, RegState::Kill).addImm(0);
4065  MIB.setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
4066  AddDefaultPred(MIB);
4067 }
4068 
4069 bool
4070 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
4071  unsigned &AddSubOpc,
4072  bool &NegAcc, bool &HasLane) const {
4073  DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode);
4074  if (I == MLxEntryMap.end())
4075  return false;
4076 
4077  const ARM_MLxEntry &Entry = ARM_MLxTable[I->second];
4078  MulOpc = Entry.MulOpc;
4079  AddSubOpc = Entry.AddSubOpc;
4080  NegAcc = Entry.NegAcc;
4081  HasLane = Entry.HasLane;
4082  return true;
4083 }
4084 
4085 //===----------------------------------------------------------------------===//
4086 // Execution domains.
4087 //===----------------------------------------------------------------------===//
4088 //
4089 // Some instructions go down the NEON pipeline, some go down the VFP pipeline,
4090 // and some can go down both. The vmov instructions go down the VFP pipeline,
4091 // but they can be changed to vorr equivalents that are executed by the NEON
4092 // pipeline.
4093 //
4094 // We use the following execution domain numbering:
4095 //
4098  ExeVFP = 1,
4100 };
4101 //
4102 // Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h
4103 //
4104 std::pair<uint16_t, uint16_t>
4106  // If we don't have access to NEON instructions then we won't be able
4107  // to swizzle anything to the NEON domain. Check to make sure.
4108  if (Subtarget.hasNEON()) {
4109  // VMOVD, VMOVRS and VMOVSR are VFP instructions, but can be changed to NEON
4110  // if they are not predicated.
4111  if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI))
4112  return std::make_pair(ExeVFP, (1 << ExeVFP) | (1 << ExeNEON));
4113 
4114  // CortexA9 is particularly picky about mixing the two and wants these
4115  // converted.
4116  if (Subtarget.isCortexA9() && !isPredicated(MI) &&
4117  (MI->getOpcode() == ARM::VMOVRS || MI->getOpcode() == ARM::VMOVSR ||
4118  MI->getOpcode() == ARM::VMOVS))
4119  return std::make_pair(ExeVFP, (1 << ExeVFP) | (1 << ExeNEON));
4120  }
4121  // No other instructions can be swizzled, so just determine their domain.
4122  unsigned Domain = MI->getDesc().TSFlags & ARMII::DomainMask;
4123 
4124  if (Domain & ARMII::DomainNEON)
4125  return std::make_pair(ExeNEON, 0);
4126 
4127  // Certain instructions can go either way on Cortex-A8.
4128  // Treat them as NEON instructions.
4129  if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8())
4130  return std::make_pair(ExeNEON, 0);
4131 
4132  if (Domain & ARMII::DomainVFP)
4133  return std::make_pair(ExeVFP, 0);
4134 
4135  return std::make_pair(ExeGeneric, 0);
4136 }
4137 
4139  unsigned SReg, unsigned &Lane) {
4140  unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass);
4141  Lane = 0;
4142 
4143  if (DReg != ARM::NoRegister)
4144  return DReg;
4145 
4146  Lane = 1;
4147  DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass);
4148 
4149  assert(DReg && "S-register with no D super-register?");
4150  return DReg;
4151 }
4152 
4153 /// getImplicitSPRUseForDPRUse - Given a use of a DPR register and lane,
4154 /// set ImplicitSReg to a register number that must be marked as implicit-use or
4155 /// zero if no register needs to be defined as implicit-use.
4156 ///
4157 /// If the function cannot determine if an SPR should be marked implicit use or
4158 /// not, it returns false.
4159 ///
4160 /// This function handles cases where an instruction is being modified from taking
4161 /// an SPR to a DPR[Lane]. A use of the DPR is being added, which may conflict
4162 /// with an earlier def of an SPR corresponding to DPR[Lane^1] (i.e. the other
4163 /// lane of the DPR).
4164 ///
4165 /// If the other SPR is defined, an implicit-use of it should be added. Else,
4166 /// (including the case where the DPR itself is defined), it should not.
4167 ///
4169  MachineInstr *MI,
4170  unsigned DReg, unsigned Lane,
4171  unsigned &ImplicitSReg) {
4172  // If the DPR is defined or used already, the other SPR lane will be chained
4173  // correctly, so there is nothing to be done.
4174  if (MI->definesRegister(DReg, TRI) || MI->readsRegister(DReg, TRI)) {
4175  ImplicitSReg = 0;
4176  return true;
4177  }
4178 
4179  // Otherwise we need to go searching to see if the SPR is set explicitly.
4180  ImplicitSReg = TRI->getSubReg(DReg,
4181  (Lane & 1) ? ARM::ssub_0 : ARM::ssub_1);
4183  MI->getParent()->computeRegisterLiveness(TRI, ImplicitSReg, MI);
4184 
4185  if (LQR == MachineBasicBlock::LQR_Live)
4186  return true;
4187  else if (LQR == MachineBasicBlock::LQR_Unknown)
4188  return false;
4189 
4190  // If the register is known not to be live, there is no need to add an
4191  // implicit-use.
4192  ImplicitSReg = 0;
4193  return true;
4194 }
4195 
4196 void
4198  unsigned DstReg, SrcReg, DReg;
4199  unsigned Lane;
4200  MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
4201  const TargetRegisterInfo *TRI = &getRegisterInfo();
4202  switch (MI->getOpcode()) {
4203  default:
4204  llvm_unreachable("cannot handle opcode!");
4205  break;
4206  case ARM::VMOVD:
4207  if (Domain != ExeNEON)
4208  break;
4209 
4210  // Zap the predicate operands.
4211  assert(!isPredicated(MI) && "Cannot predicate a VORRd");
4212 
4213  // Make sure we've got NEON instructions.
4214  assert(Subtarget.hasNEON() && "VORRd requires NEON");
4215 
4216  // Source instruction is %DDst = VMOVD %DSrc, 14, %noreg (; implicits)
4217  DstReg = MI->getOperand(0).getReg();
4218  SrcReg = MI->getOperand(1).getReg();
4219 
4220  for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4221  MI->RemoveOperand(i-1);
4222 
4223  // Change to a %DDst = VORRd %DSrc, %DSrc, 14, %noreg (; implicits)
4224  MI->setDesc(get(ARM::VORRd));
4225  AddDefaultPred(MIB.addReg(DstReg, RegState::Define)
4226  .addReg(SrcReg)
4227  .addReg(SrcReg));
4228  break;
4229  case ARM::VMOVRS:
4230  if (Domain != ExeNEON)
4231  break;
4232  assert(!isPredicated(MI) && "Cannot predicate a VGETLN");
4233 
4234  // Source instruction is %RDst = VMOVRS %SSrc, 14, %noreg (; implicits)
4235  DstReg = MI->getOperand(0).getReg();
4236  SrcReg = MI->getOperand(1).getReg();
4237 
4238  for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4239  MI->RemoveOperand(i-1);
4240 
4241  DReg = getCorrespondingDRegAndLane(TRI, SrcReg, Lane);
4242 
4243  // Convert to %RDst = VGETLNi32 %DSrc, Lane, 14, %noreg (; imps)
4244  // Note that DSrc has been widened and the other lane may be undef, which
4245  // contaminates the entire register.
4246  MI->setDesc(get(ARM::VGETLNi32));
4247  AddDefaultPred(MIB.addReg(DstReg, RegState::Define)
4248  .addReg(DReg, RegState::Undef)
4249  .addImm(Lane));
4250 
4251  // The old source should be an implicit use, otherwise we might think it
4252  // was dead before here.
4253  MIB.addReg(SrcReg, RegState::Implicit);
4254  break;
4255  case ARM::VMOVSR: {
4256  if (Domain != ExeNEON)
4257  break;
4258  assert(!isPredicated(MI) && "Cannot predicate a VSETLN");
4259 
4260  // Source instruction is %SDst = VMOVSR %RSrc, 14, %noreg (; implicits)
4261  DstReg = MI->getOperand(0).getReg();
4262  SrcReg = MI->getOperand(1).getReg();
4263 
4264  DReg = getCorrespondingDRegAndLane(TRI, DstReg, Lane);
4265 
4266  unsigned ImplicitSReg;
4267  if (!getImplicitSPRUseForDPRUse(TRI, MI, DReg, Lane, ImplicitSReg))
4268  break;
4269 
4270  for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4271  MI->RemoveOperand(i-1);
4272 
4273  // Convert to %DDst = VSETLNi32 %DDst, %RSrc, Lane, 14, %noreg (; imps)
4274  // Again DDst may be undefined at the beginning of this instruction.
4275  MI->setDesc(get(ARM::VSETLNi32));
4276  MIB.addReg(DReg, RegState::Define)
4277  .addReg(DReg, getUndefRegState(!MI->readsRegister(DReg, TRI)))
4278  .addReg(SrcReg)
4279  .addImm(Lane);
4280  AddDefaultPred(MIB);
4281 
4282  // The narrower destination must be marked as set to keep previous chains
4283  // in place.
4284  MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
4285  if (ImplicitSReg != 0)
4286  MIB.addReg(ImplicitSReg, RegState::Implicit);
4287  break;
4288  }
4289  case ARM::VMOVS: {
4290  if (Domain != ExeNEON)
4291  break;
4292 
4293  // Source instruction is %SDst = VMOVS %SSrc, 14, %noreg (; implicits)
4294  DstReg = MI->getOperand(0).getReg();
4295  SrcReg = MI->getOperand(1).getReg();
4296 
4297  unsigned DstLane = 0, SrcLane = 0, DDst, DSrc;
4298  DDst = getCorrespondingDRegAndLane(TRI, DstReg, DstLane);
4299  DSrc = getCorrespondingDRegAndLane(TRI, SrcReg, SrcLane);
4300 
4301  unsigned ImplicitSReg;
4302  if (!getImplicitSPRUseForDPRUse(TRI, MI, DSrc, SrcLane, ImplicitSReg))
4303  break;
4304 
4305  for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4306  MI->RemoveOperand(i-1);
4307 
4308  if (DSrc == DDst) {
4309  // Destination can be:
4310  // %DDst = VDUPLN32d %DDst, Lane, 14, %noreg (; implicits)
4311  MI->setDesc(get(ARM::VDUPLN32d));
4312  MIB.addReg(DDst, RegState::Define)
4313  .addReg(DDst, getUndefRegState(!MI->readsRegister(DDst, TRI)))
4314  .addImm(SrcLane);
4315  AddDefaultPred(MIB);
4316 
4317  // Neither the source or the destination are naturally represented any
4318  // more, so add them in manually.
4319  MIB.addReg(DstReg, RegState::Implicit | RegState::Define);
4320  MIB.addReg(SrcReg, RegState::Implicit);
4321  if (ImplicitSReg != 0)
4322  MIB.addReg(ImplicitSReg, RegState::Implicit);
4323  break;
4324  }
4325 
4326  // In general there's no single instruction that can perform an S <-> S
4327  // move in NEON space, but a pair of VEXT instructions *can* do the
4328  // job. It turns out that the VEXTs needed will only use DSrc once, with
4329  // the position based purely on the combination of lane-0 and lane-1
4330  // involved. For example
4331  // vmov s0, s2 -> vext.32 d0, d0, d1, #1 vext.32 d0, d0, d0, #1
4332  // vmov s1, s3 -> vext.32 d0, d1, d0, #1 vext.32 d0, d0, d0, #1
4333  // vmov s0, s3 -> vext.32 d0, d0, d0, #1 vext.32 d0, d1, d0, #1
4334  // vmov s1, s2 -> vext.32 d0, d0, d0, #1 vext.32 d0, d0, d1, #1
4335  //
4336  // Pattern of the MachineInstrs is:
4337  // %DDst = VEXTd32 %DSrc1, %DSrc2, Lane, 14, %noreg (;implicits)
4338  MachineInstrBuilder NewMIB;
4339  NewMIB = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
4340  get(ARM::VEXTd32), DDst);
4341 
4342  // On the first instruction, both DSrc and DDst may be <undef> if present.
4343  // Specifically when the original instruction didn't have them as an
4344  // <imp-use>.
4345  unsigned CurReg = SrcLane == 1 && DstLane == 1 ? DSrc : DDst;
4346  bool CurUndef = !MI->readsRegister(CurReg, TRI);
4347  NewMIB.addReg(CurReg, getUndefRegState(CurUndef));
4348 
4349  CurReg = SrcLane == 0 && DstLane == 0 ? DSrc : DDst;
4350  CurUndef = !MI->readsRegister(CurReg, TRI);
4351  NewMIB.addReg(CurReg, getUndefRegState(CurUndef));
4352 
4353  NewMIB.addImm(1);
4354  AddDefaultPred(NewMIB);
4355 
4356  if (SrcLane == DstLane)
4357  NewMIB.addReg(SrcReg, RegState::Implicit);
4358 
4359  MI->setDesc(get(ARM::VEXTd32));
4360  MIB.addReg(DDst, RegState::Define);
4361 
4362  // On the second instruction, DDst has definitely been defined above, so
4363  // it is not <undef>. DSrc, if present, can be <undef> as above.
4364  CurReg = SrcLane == 1 && DstLane == 0 ? DSrc : DDst;
4365  CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI);
4366  MIB.addReg(CurReg, getUndefRegState(CurUndef));
4367 
4368  CurReg = SrcLane == 0 && DstLane == 1 ? DSrc : DDst;
4369  CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI);
4370  MIB.addReg(CurReg, getUndefRegState(CurUndef));
4371 
4372  MIB.addImm(1);
4373  AddDefaultPred(MIB);
4374 
4375  if (SrcLane != DstLane)
4376  MIB.addReg(SrcReg, RegState::Implicit);
4377 
4378  // As before, the original destination is no longer represented, add it
4379  // implicitly.
4380  MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
4381  if (ImplicitSReg != 0)
4382  MIB.addReg(ImplicitSReg, RegState::Implicit);
4383  break;
4384  }
4385  }
4386 
4387 }
4388 
4389 //===----------------------------------------------------------------------===//
4390 // Partial register updates
4391 //===----------------------------------------------------------------------===//
4392 //
4393 // Swift renames NEON registers with 64-bit granularity. That means any
4394 // instruction writing an S-reg implicitly reads the containing D-reg. The
4395 // problem is mostly avoided by translating f32 operations to v2f32 operations
4396 // on D-registers, but f32 loads are still a problem.
4397 //
4398 // These instructions can load an f32 into a NEON register:
4399 //
4400 // VLDRS - Only writes S, partial D update.
4401 // VLD1LNd32 - Writes all D-regs, explicit partial D update, 2 uops.
4402 // VLD1DUPd32 - Writes all D-regs, no partial reg update, 2 uops.
4403 //
4404 // FCONSTD can be used as a dependency-breaking instruction.
4405 unsigned ARMBaseInstrInfo::
4407  unsigned OpNum,
4408  const TargetRegisterInfo *TRI) const {
4410  !(Subtarget.isSwift() || Subtarget.isCortexA15()))
4411  return 0;
4412 
4413  assert(TRI && "Need TRI instance");
4414 
4415  const MachineOperand &MO = MI->getOperand(OpNum);
4416  if (MO.readsReg())
4417  return 0;
4418  unsigned Reg = MO.getReg();
4419  int UseOp = -1;
4420 
4421  switch(MI->getOpcode()) {
4422  // Normal instructions writing only an S-register.
4423  case ARM::VLDRS:
4424  case ARM::FCONSTS:
4425  case ARM::VMOVSR:
4426  case ARM::VMOVv8i8:
4427  case ARM::VMOVv4i16:
4428  case ARM::VMOVv2i32:
4429  case ARM::VMOVv2f32:
4430  case ARM::VMOVv1i64:
4431  UseOp = MI->findRegisterUseOperandIdx(Reg, false, TRI);
4432  break;
4433 
4434  // Explicitly reads the dependency.
4435  case ARM::VLD1LNd32:
4436  UseOp = 3;
4437  break;
4438  default:
4439  return 0;
4440  }
4441 
4442  // If this instruction actually reads a value from Reg, there is no unwanted
4443  // dependency.
4444  if (UseOp != -1 && MI->getOperand(UseOp).readsReg())
4445  return 0;
4446 
4447  // We must be able to clobber the whole D-reg.
4449  // Virtual register must be a foo:ssub_0<def,undef> operand.
4450  if (!MO.getSubReg() || MI->readsVirtualRegister(Reg))
4451  return 0;
4452  } else if (ARM::SPRRegClass.contains(Reg)) {
4453  // Physical register: MI must define the full D-reg.
4454  unsigned DReg = TRI->getMatchingSuperReg(Reg, ARM::ssub_0,
4455  &ARM::DPRRegClass);
4456  if (!DReg || !MI->definesRegister(DReg, TRI))
4457  return 0;
4458  }
4459 
4460  // MI has an unwanted D-register dependency.
4461  // Avoid defs in the previous N instructrions.
4463 }
4464 
4465 // Break a partial register dependency after getPartialRegUpdateClearance
4466 // returned non-zero.
4467 void ARMBaseInstrInfo::
4469  unsigned OpNum,
4470  const TargetRegisterInfo *TRI) const {
4471  assert(MI && OpNum < MI->getDesc().getNumDefs() && "OpNum is not a def");
4472  assert(TRI && "Need TRI instance");
4473 
4474  const MachineOperand &MO = MI->getOperand(OpNum);
4475  unsigned Reg = MO.getReg();
4477  "Can't break virtual register dependencies.");
4478  unsigned DReg = Reg;
4479 
4480  // If MI defines an S-reg, find the corresponding D super-register.
4481  if (ARM::SPRRegClass.contains(Reg)) {
4482  DReg = ARM::D0 + (Reg - ARM::S0) / 2;
4483  assert(TRI->isSuperRegister(Reg, DReg) && "Register enums broken");
4484  }
4485 
4486  assert(ARM::DPRRegClass.contains(DReg) && "Can only break D-reg deps");
4487  assert(MI->definesRegister(DReg, TRI) && "MI doesn't clobber full D-reg");
4488 
4489  // FIXME: In some cases, VLDRS can be changed to a VLD1DUPd32 which defines
4490  // the full D-register by loading the same value to both lanes. The
4491  // instruction is micro-coded with 2 uops, so don't do this until we can
4492  // properly schedule micro-coded instructions. The dispatcher stalls cause
4493  // too big regressions.
4494 
4495  // Insert the dependency-breaking FCONSTD before MI.
4496  // 96 is the encoding of 0.5, but the actual value doesn't matter here.
4497  AddDefaultPred(BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
4498  get(ARM::FCONSTD), DReg).addImm(96));
4499  MI->addRegisterKilled(DReg, TRI, true);
4500 }
4501 
4503  return Subtarget.getFeatureBits()[ARM::HasV6KOps];
4504 }
4505 
4507  if (MI->getNumOperands() < 4)
4508  return true;
4509  unsigned ShOpVal = MI->getOperand(3).getImm();
4510  unsigned ShImm = ARM_AM::getSORegOffset(ShOpVal);
4511  // Swift supports faster shifts for: lsl 2, lsl 1, and lsr 1.
4512  if ((ShImm == 1 && ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsr) ||
4513  ((ShImm == 1 || ShImm == 2) &&
4514  ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsl))
4515  return true;
4516 
4517  return false;
4518 }
4519 
4521  const MachineInstr &MI, unsigned DefIdx,
4522  SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
4523  assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
4524  assert(MI.isRegSequenceLike() && "Invalid kind of instruction");
4525 
4526  switch (MI.getOpcode()) {
4527  case ARM::VMOVDRR:
4528  // dX = VMOVDRR rY, rZ
4529  // is the same as:
4530  // dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1
4531  // Populate the InputRegs accordingly.
4532  // rY
4533  const MachineOperand *MOReg = &MI.getOperand(1);
4534  InputRegs.push_back(
4535  RegSubRegPairAndIdx(MOReg->getReg(), MOReg->getSubReg(), ARM::ssub_0));
4536  // rZ
4537  MOReg = &MI.getOperand(2);
4538  InputRegs.push_back(
4539  RegSubRegPairAndIdx(MOReg->getReg(), MOReg->getSubReg(), ARM::ssub_1));
4540  return true;
4541  }
4542  llvm_unreachable("Target dependent opcode missing");
4543 }
4544 
4546  const MachineInstr &MI, unsigned DefIdx,
4547  RegSubRegPairAndIdx &InputReg) const {
4548  assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
4549  assert(MI.isExtractSubregLike() && "Invalid kind of instruction");
4550 
4551  switch (MI.getOpcode()) {
4552  case ARM::VMOVRRD:
4553  // rX, rY = VMOVRRD dZ
4554  // is the same as:
4555  // rX = EXTRACT_SUBREG dZ, ssub_0
4556  // rY = EXTRACT_SUBREG dZ, ssub_1
4557  const MachineOperand &MOReg = MI.getOperand(2);
4558  InputReg.Reg = MOReg.getReg();
4559  InputReg.SubReg = MOReg.getSubReg();
4560  InputReg.SubIdx = DefIdx == 0 ? ARM::ssub_0 : ARM::ssub_1;
4561  return true;
4562  }
4563  llvm_unreachable("Target dependent opcode missing");
4564 }
4565 
4567  const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg,
4568  RegSubRegPairAndIdx &InsertedReg) const {
4569  assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
4570  assert(MI.isInsertSubregLike() && "Invalid kind of instruction");
4571 
4572  switch (MI.getOpcode()) {
4573  case ARM::VSETLNi32:
4574  // dX = VSETLNi32 dY, rZ, imm
4575  const MachineOperand &MOBaseReg = MI.getOperand(1);
4576  const MachineOperand &MOInsertedReg = MI.getOperand(2);
4577  const MachineOperand &MOIndex = MI.getOperand(3);
4578  BaseReg.Reg = MOBaseReg.getReg();
4579  BaseReg.SubReg = MOBaseReg.getSubReg();
4580 
4581  InsertedReg.Reg = MOInsertedReg.getReg();
4582  InsertedReg.SubReg = MOInsertedReg.getSubReg();
4583  InsertedReg.SubIdx = MOIndex.getImm() == 0 ? ARM::ssub_0 : ARM::ssub_1;
4584  return true;
4585  }
4586  llvm_unreachable("Target dependent opcode missing");
4587 }
virtual MachineInstr * duplicate(MachineInstr *Orig, MachineFunction &MF) const
Create a duplicate of the Orig instruction in MF.
MachineConstantPoolValue * MachineCPVal
bool isImplicit() const
The memory access reads data.
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
bool getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const override
Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx.
The memory access writes data.
const GlobalValue * getGlobal() const
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
static cl::opt< unsigned > SwiftPartialUpdateClearance("swift-partial-update-clearance", cl::Hidden, cl::init(12), cl::desc("Clearance before partial register updates"))
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:223
bool isFPOnlySP() const
Definition: ARMSubtarget.h:337
instr_iterator instr_end()
static unsigned char getAM3Offset(unsigned AM3Opc)
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:427
unsigned getMispredictionPenalty() const
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
bool removeKill(MachineInstr *MI)
removeKill - Delete a kill corresponding to the specified machine instruction.
Definition: LiveVariables.h:94
static void Found()
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
static const MachineInstr * getBundledUseMI(const TargetRegisterInfo *TRI, const MachineInstr *MI, unsigned Reg, unsigned &UseIdx, unsigned &Dist)
int getNumMicroOps(unsigned ItinClassIndx) const
Return the number of micro-ops that the given class decodes to.
bool ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
MachineInstr * duplicate(MachineInstr *Orig, MachineFunction &MF) const override
bool isCortexA8() const
Definition: ARMSubtarget.h:303
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:191
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
static unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm)
bool hasOptionalDef() const
Set if this instruction has an optional definition, e.g.
Definition: MCInstrDesc.h:204
bool mayStore() const
Return true if this instruction could possibly modify memory.
Definition: MCInstrDesc.h:356
ARMConstantPoolValue - ARM specific constantpool value.
void setIsDef(bool Val=true)
Change a def to a use, or a use to a def.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:138
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:579
bool isDead() const
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
unsigned getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr *MI) const override
static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg, int CmpMask, bool CommonUse)
isSuitableForMask - Identify a suitable 'and' instruction that operates on the given source register ...
std::pair< uint16_t, uint16_t > getExecutionDomain(const MachineInstr *MI) const override
VFP/NEON execution domains.
bool isTied() const
bool isPredicable(QueryType Type=AllInBundle) const
Return true if this instruction has a predicate operand that controls execution.
Definition: MachineInstr.h:457
bool readsVirtualRegister(unsigned Reg) const
Return true if the MachineInstr reads the specified virtual register.
Definition: MachineInstr.h:844
virtual ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
uint32_t getNumerator() const
static unsigned getCorrespondingDRegAndLane(const TargetRegisterInfo *TRI, unsigned SReg, unsigned &Lane)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const override
optimizeCompareInstr - Convert the instruction to set the zero flag so that we can remove a "comparis...
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:264
virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const
GetInstSize - Returns the size of the specified MachineInstr.
bool hasV5TEOps() const
Definition: ARMSubtarget.h:292
const char * getSymbolName() const
VarInfo - This represents the regions where a virtual register is live in the program.
Definition: LiveVariables.h:79
A debug info location.
Definition: DebugLoc.h:34
const SDValue & getOperand(unsigned Num) const
void setIsDead(bool Val=true)
F(f)
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
bool produceSameValue(const MachineInstr *MI0, const MachineInstr *MI1, const MachineRegisterInfo *MRI) const override
bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget, MachineFunction &MF, MachineInstr *MI, unsigned NumBytes)
Tries to add registers to the reglist of a given base-updating push/pop instruction to adjust the sta...
unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const override
bool isThumb1Only() const
Definition: ARMSubtarget.h:405
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:295
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, unsigned f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
getMachineMemOperand - Allocate a new MachineMemOperand.
static bool isThumb(const MCSubtargetInfo &STI)
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:419
static bool getImplicitSPRUseForDPRUse(const TargetRegisterInfo *TRI, MachineInstr *MI, unsigned DReg, unsigned Lane, unsigned &ImplicitSReg)
getImplicitSPRUseForDPRUse - Given a use of a DPR register and lane, set ImplicitSReg to a register n...
static unsigned getSOImmValRotate(unsigned Imm)
getSOImmValRotate - Try to handle Imm with an immediate shifter operand, computing the rotate amount ...
bool restrictIT() const
Definition: ARMSubtarget.h:424
static MachinePointerInfo getFixedStack(int FI, int64_t offset=0)
getFixedStack - Return a MachinePointerInfo record that refers to the the specified FrameIndex...
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:242
static unsigned rotr32(unsigned Val, unsigned Amt)
rotr32 - Rotate a 32-bit unsigned value right by a specified # bits.
bool isCortexA9() const
Definition: ARMSubtarget.h:304
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Definition: DenseMap.h:169
void clearKillInfo()
Clears kill flags on all operands.
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
unsigned getSize() const
getSize - Return the size of the register in bytes, which is also the size of a stack slot allocated ...
int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const
Return the cycle for the given class and operand.
MachineMemOperand - A description of a memory reference used in the backend.
static const MachineInstrBuilder & AddDefaultPred(const MachineInstrBuilder &MIB)
mmo_iterator memoperands_begin() const
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
Provide an instruction scheduling machine model to CodeGen passes.
const HexagonInstrInfo * TII
const TargetRegisterInfo * getTargetRegisterInfo() const
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false)
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, DebugLoc DL) const override
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
use_instr_iterator use_instr_begin(unsigned RegNo) const
bool isCall() const
Return true if the instruction is a call.
Definition: MCInstrDesc.h:214
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APInt.h:33
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void setImplicit(bool Val=true)
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:566
bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const ARMBaseInstrInfo &TII)
rewriteARMFrameIndex / rewriteT2FrameIndex - Rewrite MI to access 'Offset' bytes from the FP...
const TargetRegisterClass * getRegClass(unsigned Reg) const
getRegClass - Return the register class of the specified virtual register.
std::vector< MachineBasicBlock * >::iterator succ_iterator
Reg
All possible values of the reg field in the ModR/M byte.
bool memoperands_empty() const
void setIndex(int Idx)
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool isUndef() const
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override
shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction w...
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Definition: Value.cpp:317
bool isThumb() const
Definition: ARMSubtarget.h:404
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:571
static unsigned getT2SOImmTwoPartFirst(unsigned Imm)
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:271
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
defusechain_iterator - This class provides iterator support for machine operands in the function that...
bool isFpMLxInstruction(unsigned Opcode) const
isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS instruction.
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, const BranchProbability &Probability) const override
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
bool isKill() const
static ARMCC::CondCodes getSwappedCondition(ARMCC::CondCodes CC)
getSwappedCondition - assume the flags are set by MI(a,b), return the condition code if we modify the...
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Definition: SmallVector.h:57
virtual MachineInstr * commuteInstruction(MachineInstr *MI, bool NewMI=false) const
If a target has any instructions that are commutable but require converting to different instructions...
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
getMatchingSuperReg - Return a super-register of the specified register Reg so its sub-register of in...
bool isV8EligibleForIT(InstrType *Instr)
Definition: ARMFeatures.h:25
bool isCopyLike() const
Return true if the instruction behaves like a copy.
Definition: MachineInstr.h:790
static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData, const MachineInstr *MI)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: ArrayRef.h:31
bool PredicateInstruction(MachineInstr *MI, ArrayRef< MachineOperand > Pred) const override
bool hasNEON() const
Definition: ARMSubtarget.h:318
Itinerary data supplied by a subtarget to be used by a target.
iterator getLastNonDebugInstr()
getLastNonDebugInstr - returns an iterator to the last non-debug instruction in the basic block...
This class is a data container for one entry in a MachineConstantPool.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:804
static const ARM_MLxEntry ARM_MLxTable[]
unsigned getMatchingCondBranchOpcode(unsigned Opc)
ARM_MLxEntry - Record information about MLA / MLS instructions.
int64_t getImm() const
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
unsigned getUndefRegState(bool B)
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
getCalleeSavedRegs - Return a null-terminated list of all of the callee saved registers on this targe...
LivenessQueryResult computeRegisterLiveness(const TargetRegisterInfo *TRI, unsigned Reg, const_iterator Before, unsigned Neighborhood=10) const
Return whether (physical) register Reg has been <def>ined and not <kill>ed as of just before Before...
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:134
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
reverse_iterator rbegin()
unsigned getKillRegState(bool B)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:267
bool isMachineConstantPoolEntry() const
isMachineConstantPoolEntry - Return true if the MachineConstantPoolEntry is indeed a target specific ...
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:97
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:120
TargetInstrInfo - Interface to description of machine instruction set.
static bool isCondBranchOpcode(int Opc)
bool IsCPSRDead< MachineInstr >(MachineInstr *MI)
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:247
bool isDebugValue() const
Definition: MachineInstr.h:748
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:58
bool isImplicitDef() const
Definition: MachineInstr.h:759
mmo_iterator memoperands_end() const
Definition: MachineInstr.h:341
bool isInsertSubreg() const
Definition: MachineInstr.h:766
bool isBundle() const
Definition: MachineInstr.h:775
bundle_iterator< MachineInstr, instr_iterator > iterator
#define P(N)
static bool isCalleeSavedRegister(unsigned Reg, const MCPhysReg *CSRegs)
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:325
bool regsOverlap(unsigned regA, unsigned regB) const
regsOverlap - Returns true if the two registers are equal or alias each other.
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
const InstrItineraryData * getInstrItineraries() const
static bool isAnySubRegLive(unsigned Reg, const TargetRegisterInfo *TRI, MachineInstr *MI)
bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are lo...
ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg)
getInstrPredicate - If instruction is predicated, returns its predicate condition, otherwise returns AL.
static unsigned char getAM5Offset(unsigned AM5Opc)
bool isMClass() const
Definition: ARMSubtarget.h:408
static unsigned getSOImmTwoPartSecond(unsigned V)
getSOImmTwoPartSecond - If V is a value that satisfies isSOImmTwoPartVal, return the second chunk of ...
int findRegisterDefOperandIdx(unsigned Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a def of the specified register or -1 if it is not found...
bool isSchedulingBoundary(const MachineInstr *MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:32
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
static cl::opt< bool > WidenVMOVS("widen-vmovs", cl::Hidden, cl::init(true), cl::desc("Widen ARM vmovs to vmovd when possible"))
bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Definition: MCInstrDesc.h:532
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:264
static bool isJumpTableBranchOpcode(int Opc)
unsigned getStageLatency(unsigned ItinClassIndx) const
Return the total stage latency of the given class.
virtual bool hasSameValue(ARMConstantPoolValue *ACPV)
hasSameValue - Return true if this ARM constpool value can share the same constantpool entry as anoth...
static bool isEligibleForITBlock(const MachineInstr *MI)
static unsigned getT2SOImmTwoPartSecond(unsigned Imm)
Register is known to be dead.
This pseudo-instruction loads the stack guard value.
bool isPosition() const
Definition: MachineInstr.h:746
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
void copyFromCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, bool KillSrc, const ARMSubtarget &Subtarget) const
void setImm(int64_t immVal)
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
Definition: MachineInstr.h:352
bool isCortexA15() const
Definition: ARMSubtarget.h:305
unsigned convertAddSubFlagsOpcode(unsigned OldOpc)
Map pseudo instructions that imply an 'S' bit onto real opcodes.
int64_t getOffset() const
Return the offset from the symbol in this operand.
MachineInstr * commuteInstruction(MachineInstr *, bool=false) const override
commuteInstruction - Handle commutable instructions.
static bool isRedundantFlagInstr(MachineInstr *CmpI, unsigned SrcReg, unsigned SrcReg2, int ImmValue, MachineInstr *OI)
isRedundantFlagInstr - check whether the first instruction, whose only purpose is to update flags...
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:69
MachineInstr * optimizeSelect(MachineInstr *MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool) const override
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:129
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
LivenessQueryResult
Possible outcome of a register liveness query to computeRegisterLiveness()
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
Register is known to be live.
unsigned getSubReg() const
void breakPartialRegDependency(MachineBasicBlock::iterator, unsigned, const TargetRegisterInfo *TRI) const override
VarInfo & getVarInfo(unsigned RegIdx)
getVarInfo - Return the VarInfo structure for the specified VIRTUAL register.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
MCSubRegIterator enumerates all sub-registers of Reg.
static const MachineInstr * getBundledDefMI(const TargetRegisterInfo *TRI, const MachineInstr *MI, unsigned Reg, unsigned &DefIdx, unsigned &Dist)
struct llvm::MachineOperand::@33::@34 Reg
void emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of instructions to materializea des...
unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const override
bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const override
analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if h...
bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
Definition: MachineInstr.h:866
The memory access is invariant.
void setIsKill(bool Val=true)
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:178
bool isInsertSubregLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions...
Definition: MachineInstr.h:555
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:53
bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
std::vector< MachineInstr * > Kills
Kills - List of MachineInstruction's which are the last use of this virtual register (kill it) in the...
Definition: LiveVariables.h:89
static AddrOpc getAM2Op(unsigned AM2Opc)
bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
Definition: MachineInstr.h:836
ARMConstantPoolConstant - ARM-specific constant pool values for Constants, Functions, and BlockAddresses.
int findRegisterUseOperandIdx(unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a use of the specific register or -1 if it is not found...
static const MachineInstrBuilder & AddDefaultCC(const MachineInstrBuilder &MIB)
static bool isIndirectBranchOpcode(int Opc)
bool isSwift() const
Definition: ARMSubtarget.h:306
static bool isUncondBranchOpcode(int Opc)
virtual unsigned getUnindexedOpcode(unsigned Opc) const =0
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
unsigned RemoveBranch(MachineBasicBlock &MBB) const override
bool erase(PtrType Ptr)
erase - If the set contains the specified pointer, remove it and return true, otherwise return false...
Definition: SmallPtrSet.h:271
bool isIdenticalTo(const MachineInstr *Other, MICheckType Check=CheckDefs) const
Return true if this instruction is identical to (same opcode and same operands as) the specified inst...
bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const
GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
static unsigned getAM2Offset(unsigned AM2Opc)
ARMConstantPoolSymbol - ARM-specific constantpool values for external symbols.
MachineInstr * CloneMachineInstr(const MachineInstr *Orig)
CloneMachineInstr - Create a new MachineInstr which is a copy of the 'Orig' instruction, identical in all ways except the instruction has no parent, prev, or next.
static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI)
Create a copy of a const pool value.
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:861
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
Map pseudo instructions that imply an 'S' bit onto real opcodes.
An SDNode that represents everything that will be needed to construct a MachineInstr.
bool isSwiftFastImmShift(const MachineInstr *MI) const
Returns true if the instruction has a shift by immediate that can be executed in one cycle less...
bool hasVFP2() const
Definition: ARMSubtarget.h:314
bool mayLoad() const
Return true if this instruction could possibly read memory.
Definition: MCInstrDesc.h:350
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Represents one node in the SelectionDAG.
static bool isPushOpcode(int Opc)
static bool isSOImmTwoPartVal(unsigned V)
isSOImmTwoPartVal - Return true if the specified value can be obtained by or'ing together two SOImmVa...
ARMConstantPoolMBB - ARM-specific constantpool value of a machine basic block.
const MachineInstrBuilder & addFrameIndex(int Idx) const
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
unsigned short Opcode
Definition: MCInstrDesc.h:140
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:123
BUNDLE - This instruction represents an instruction bundle.
Definition: TargetOpcodes.h:91
void addRegisterDefined(unsigned Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
void copyToCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool KillSrc, const ARMSubtarget &Subtarget) const
static int adjustDefLatency(const ARMSubtarget &Subtarget, const MachineInstr *DefMI, const MCInstrDesc *DefMCID, unsigned DefAlign)
Return the number of cycles to add to (or subtract from) the static itinerary based on the def opcode...
bool isPredicable(MachineInstr *MI) const override
isPredicable - Return true if the specified instruction can be predicated.
bool isCortexA7() const
Definition: ARMSubtarget.h:302
AddrMode
ARM Addressing Modes.
Definition: ARMBaseInfo.h:235
static AddrOpc getAM3Op(unsigned AM3Opc)
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:285
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
bool isExtractSubregLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions...
Definition: MachineInstr.h:541
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:238
bool DefinesPredicate(MachineInstr *MI, std::vector< MachineOperand > &Pred) const override
int getOperandLatency(unsigned DefClass, unsigned DefIdx, unsigned UseClass, unsigned UseIdx) const
Compute and return the use operand latency of a given itinerary class and operand index if the value ...
static int getSOImmVal(unsigned Arg)
getSOImmVal - Given a 32-bit immediate, if it is something that can fit into an shifter_operand immed...
ARMBaseInstrInfo(const ARMSubtarget &STI)
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned char TargetFlags=0) const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
TargetSubtargetInfo - Generic base class for all target subtargets.
bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, unsigned Reg, MachineRegisterInfo *MRI) const override
FoldImmediate - 'Reg' is known to be defined by a move immediate instruction, try to fold the immedia...
static bool isPopOpcode(int Opc)
bool isSuperRegister(unsigned RegA, unsigned RegB) const
Returns true if RegB is a super-register of RegA.
static bool isARMLowRegister(unsigned Reg)
isARMLowRegister - Returns true if the register is a low register (r0-r7).
Definition: ARMBaseInfo.h:210
static MachinePointerInfo getGOT()
getGOT - Return a MachinePointerInfo record that refers to a GOT entry.
Representation of each machine instruction.
Definition: MachineInstr.h:51
static MachineInstr * canFoldIntoMOVCC(unsigned Reg, const MachineRegisterInfo &MRI, const TargetInstrInfo *TII)
Identify instructions that can be folded into a MOVCC instruction, and return the defining instructio...
bundle_iterator< const MachineInstr, const_instr_iterator > const_iterator
static bool isPhysicalRegister(unsigned Reg)
isPhysicalRegister - Return true if the specified register number is in the physical register namespa...
static CondCodes getOppositeCondition(CondCodes CC)
Definition: ARMBaseInfo.h:47
static const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[]
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:528
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:217
uint32_t getDenominator() const
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool isThumb2() const
Definition: ARMSubtarget.h:406
bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const override
Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx.
Register liveness not decidable from local neighborhood.
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
unsigned getNumLDMAddresses(const MachineInstr *MI) const
Get the number of addresses by LDM or VLDM or zero for unknown.
void addVirtualRegisterDead(unsigned IncomingReg, MachineInstr *MI, bool AddIfNotFound=false)
addVirtualRegisterDead - Add information about the fact that the specified register is dead after bei...
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx, unsigned UseClass, unsigned UseIdx) const
Return true if there is a pipeline forwarding between instructions of itinerary classes DefClass and ...
void setReg(unsigned Reg)
Change the register this operand corresponds to.
const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned char TargetFlags=0) const
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
#define I(x, y, z)
Definition: MD5.cpp:54
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:403
bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override
bool isPredicated(const MachineInstr *MI) const override
bool getRegSequenceLikeInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const override
Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx.
iterator end()
Definition: DenseMap.h:68
iterator find(const KeyT &Val)
Definition: DenseMap.h:124
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
union llvm::MachineConstantPoolEntry::@30 Val
The constant itself.
MCInstrDesc const & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
int getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const override
bool analyzeSelect(const MachineInstr *MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const override
static AddrOpc getAM5Op(unsigned AM5Opc)
unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx, const MachineInstr *UseMI, unsigned UseOperIdx) const
Compute operand latency based on the available machine model.
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const override
virtual ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
unsigned getReg() const
getReg - Returns the register number.
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
ARMHazardRecognizer handles special constraints that are not expressed in the scheduling itinerary...
bool isLikeA9() const
Definition: ARMSubtarget.h:308
static ShiftOpc getAM2ShiftOpc(unsigned AM2Opc)
virtual const ARMBaseRegisterInfo & getRegisterInfo() const =0
static unsigned getSORegOffset(unsigned Op)
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
static use_instr_iterator use_instr_end()
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:185
MO_NONLAZY - This is an independent flag, on a symbol operand "FOO" it represents a symbol which...
Definition: ARMBaseInfo.h:310
unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const override
bool hasImplicitDefOfPhysReg(unsigned Reg, const MCRegisterInfo *MRI=nullptr) const
Return true if this instruction implicitly defines the specified physical register.
Definition: MCInstrDesc.cpp:54
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
BasicBlockListType::iterator iterator
#define DEBUG(X)
Definition: Debug.h:92
const ARMSubtarget & getSubtarget() const
bool addRegisterKilled(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
const std::vector< MachineConstantPoolEntry > & getConstants() const
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:40
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register. ...
bool hasOptionalDef(QueryType Type=IgnoreBundle) const
Set if this instruction has an optional definition, e.g.
Definition: MachineInstr.h:389
unsigned getPartialRegUpdateClearance(const MachineInstr *, unsigned, const TargetRegisterInfo *) const override
bool isIdenticalTo(const MachineOperand &Other) const
isIdenticalTo - Return true if this operand is identical to the specified operand.
bool isRegSequence() const
Definition: MachineInstr.h:772
void expandLoadStackGuardBase(MachineBasicBlock::iterator MI, unsigned LoadImmOpc, unsigned LoadOpc, Reloc::Model RM) const
static bool isT2SOImmTwoPartVal(unsigned Imm)
static unsigned getSOImmTwoPartFirst(unsigned V)
getSOImmTwoPartFirst - If V is a value that satisfies isSOImmTwoPartVal, return the first chunk of it...
void setExecutionDomain(MachineInstr *MI, unsigned Domain) const override
bool isRegSequenceLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions.
Definition: MachineInstr.h:526
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
bool isEmpty() const
Returns true if there are no itineraries.
void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd)
Assign this MachineInstr's memory reference descriptor list.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
static ARMConstantPoolConstant * Create(const Constant *C, unsigned ID)
unsigned getConstantPoolIndex(const Constant *C, unsigned Alignment)
getConstantPoolIndex - Create a new entry in the constant pool or return an existing one...
bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
Definition: MachineInstr.h:874
const MachineInstrBuilder & AddDReg(MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI) const
MachineInstr * convertToThreeAddress(MachineFunction::iterator &MFI, MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const override
void addVirtualRegisterKilled(unsigned IncomingReg, MachineInstr *MI, bool AddIfNotFound=false)
addVirtualRegisterKilled - Add information about the fact that the specified register is killed after...
static cl::opt< bool > EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden, cl::desc("Enable ARM 2-addr to 3-addr conv"))
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SubIdx, const MachineInstr *Orig, const TargetRegisterInfo &TRI) const override
bool isMachineOpcode() const
Test if this node has a post-isel opcode, directly corresponding to a MachineInstr opcode...
static ShiftOpc getSORegShOp(unsigned Op)
unsigned getMachineOpcode() const
This may only be called if isMachineOpcode returns true.
static bool isCPSRDefined(const MachineInstr *MI)
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:340
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
Function must be optimized for size first.
Definition: Attributes.h:80