LLVM  3.7.0
Macros | Typedefs | Enumerations | Functions | Variables
HexagonDisassembler.cpp File Reference
#include "Hexagon.h"
#include "MCTargetDesc/HexagonBaseInfo.h"
#include "MCTargetDesc/HexagonMCInstrInfo.h"
#include "MCTargetDesc/HexagonMCTargetDesc.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCDisassembler.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCFixedLenDisassembler.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/Endian.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/LEB128.h"
#include "llvm/Support/TargetRegistry.h"
#include "llvm/Support/raw_ostream.h"
#include <array>
#include <vector>
#include "HexagonGenDisassemblerTables.inc"
Include dependency graph for HexagonDisassembler.cpp:

Go to the source code of this file.

Macros

#define DEBUG_TYPE   "hexagon-disassembler"
 

Typedefs

typedef
llvm::MCDisassembler::DecodeStatus 
DecodeStatus
 

Enumerations

enum  subInstBinaryValues {
  V4_SA1_addi_BITS = 0x0000, V4_SA1_addi_MASK = 0x1800, V4_SA1_addrx_BITS = 0x1800, V4_SA1_addrx_MASK = 0x1f00,
  V4_SA1_addsp_BITS = 0x0c00, V4_SA1_addsp_MASK = 0x1c00, V4_SA1_and1_BITS = 0x1200, V4_SA1_and1_MASK = 0x1f00,
  V4_SA1_clrf_BITS = 0x1a70, V4_SA1_clrf_MASK = 0x1e70, V4_SA1_clrfnew_BITS = 0x1a50, V4_SA1_clrfnew_MASK = 0x1e70,
  V4_SA1_clrt_BITS = 0x1a60, V4_SA1_clrt_MASK = 0x1e70, V4_SA1_clrtnew_BITS = 0x1a40, V4_SA1_clrtnew_MASK = 0x1e70,
  V4_SA1_cmpeqi_BITS = 0x1900, V4_SA1_cmpeqi_MASK = 0x1f00, V4_SA1_combine0i_BITS = 0x1c00, V4_SA1_combine0i_MASK = 0x1d18,
  V4_SA1_combine1i_BITS = 0x1c08, V4_SA1_combine1i_MASK = 0x1d18, V4_SA1_combine2i_BITS = 0x1c10, V4_SA1_combine2i_MASK = 0x1d18,
  V4_SA1_combine3i_BITS = 0x1c18, V4_SA1_combine3i_MASK = 0x1d18, V4_SA1_combinerz_BITS = 0x1d08, V4_SA1_combinerz_MASK = 0x1d08,
  V4_SA1_combinezr_BITS = 0x1d00, V4_SA1_combinezr_MASK = 0x1d08, V4_SA1_dec_BITS = 0x1300, V4_SA1_dec_MASK = 0x1f00,
  V4_SA1_inc_BITS = 0x1100, V4_SA1_inc_MASK = 0x1f00, V4_SA1_seti_BITS = 0x0800, V4_SA1_seti_MASK = 0x1c00,
  V4_SA1_setin1_BITS = 0x1a00, V4_SA1_setin1_MASK = 0x1e40, V4_SA1_sxtb_BITS = 0x1500, V4_SA1_sxtb_MASK = 0x1f00,
  V4_SA1_sxth_BITS = 0x1400, V4_SA1_sxth_MASK = 0x1f00, V4_SA1_tfr_BITS = 0x1000, V4_SA1_tfr_MASK = 0x1f00,
  V4_SA1_zxtb_BITS = 0x1700, V4_SA1_zxtb_MASK = 0x1f00, V4_SA1_zxth_BITS = 0x1600, V4_SA1_zxth_MASK = 0x1f00,
  V4_SL1_loadri_io_BITS = 0x0000, V4_SL1_loadri_io_MASK = 0x1000, V4_SL1_loadrub_io_BITS = 0x1000, V4_SL1_loadrub_io_MASK = 0x1000,
  V4_SL2_deallocframe_BITS = 0x1f00, V4_SL2_deallocframe_MASK = 0x1fc0, V4_SL2_jumpr31_BITS = 0x1fc0, V4_SL2_jumpr31_MASK = 0x1fc4,
  V4_SL2_jumpr31_f_BITS = 0x1fc5, V4_SL2_jumpr31_f_MASK = 0x1fc7, V4_SL2_jumpr31_fnew_BITS = 0x1fc7, V4_SL2_jumpr31_fnew_MASK = 0x1fc7,
  V4_SL2_jumpr31_t_BITS = 0x1fc4, V4_SL2_jumpr31_t_MASK = 0x1fc7, V4_SL2_jumpr31_tnew_BITS = 0x1fc6, V4_SL2_jumpr31_tnew_MASK = 0x1fc7,
  V4_SL2_loadrb_io_BITS = 0x1000, V4_SL2_loadrb_io_MASK = 0x1800, V4_SL2_loadrd_sp_BITS = 0x1e00, V4_SL2_loadrd_sp_MASK = 0x1f00,
  V4_SL2_loadrh_io_BITS = 0x0000, V4_SL2_loadrh_io_MASK = 0x1800, V4_SL2_loadri_sp_BITS = 0x1c00, V4_SL2_loadri_sp_MASK = 0x1e00,
  V4_SL2_loadruh_io_BITS = 0x0800, V4_SL2_loadruh_io_MASK = 0x1800, V4_SL2_return_BITS = 0x1f40, V4_SL2_return_MASK = 0x1fc4,
  V4_SL2_return_f_BITS = 0x1f45, V4_SL2_return_f_MASK = 0x1fc7, V4_SL2_return_fnew_BITS = 0x1f47, V4_SL2_return_fnew_MASK = 0x1fc7,
  V4_SL2_return_t_BITS = 0x1f44, V4_SL2_return_t_MASK = 0x1fc7, V4_SL2_return_tnew_BITS = 0x1f46, V4_SL2_return_tnew_MASK = 0x1fc7,
  V4_SS1_storeb_io_BITS = 0x1000, V4_SS1_storeb_io_MASK = 0x1000, V4_SS1_storew_io_BITS = 0x0000, V4_SS1_storew_io_MASK = 0x1000,
  V4_SS2_allocframe_BITS = 0x1c00, V4_SS2_allocframe_MASK = 0x1e00, V4_SS2_storebi0_BITS = 0x1200, V4_SS2_storebi0_MASK = 0x1f00,
  V4_SS2_storebi1_BITS = 0x1300, V4_SS2_storebi1_MASK = 0x1f00, V4_SS2_stored_sp_BITS = 0x0a00, V4_SS2_stored_sp_MASK = 0x1e00,
  V4_SS2_storeh_io_BITS = 0x0000, V4_SS2_storeh_io_MASK = 0x1800, V4_SS2_storew_sp_BITS = 0x0800, V4_SS2_storew_sp_MASK = 0x1e00,
  V4_SS2_storewi0_BITS = 0x1000, V4_SS2_storewi0_MASK = 0x1f00, V4_SS2_storewi1_BITS = 0x1100, V4_SS2_storewi1_MASK = 0x1f00
}
 

Functions

static DecodeStatus DecodeModRegsRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
 
static DecodeStatus DecodeCtrRegsRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
 
static DecodeStatus DecodeCtrRegs64RegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, void const *Decoder)
 
static unsigned GetSubinstOpcode (unsigned IClass, unsigned inst, unsigned &op, raw_ostream &os)
 
static void AddSubinstOperands (MCInst *MI, unsigned opcode, unsigned inst)
 
static DecodeStatus s16ImmDecoder (MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
 
static DecodeStatus s12ImmDecoder (MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
 
static DecodeStatus s11_0ImmDecoder (MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
 
static DecodeStatus s11_1ImmDecoder (MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
 
static DecodeStatus s11_2ImmDecoder (MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
 
static DecodeStatus s11_3ImmDecoder (MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
 
static DecodeStatus s10ImmDecoder (MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
 
static DecodeStatus s8ImmDecoder (MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
 
static DecodeStatus s6_0ImmDecoder (MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
 
static DecodeStatus s4_0ImmDecoder (MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
 
static DecodeStatus s4_1ImmDecoder (MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
 
static DecodeStatus s4_2ImmDecoder (MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
 
static DecodeStatus s4_3ImmDecoder (MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
 
static DecodeStatus DecodeRegisterClass (MCInst &Inst, unsigned RegNo, const uint16_t Table[], size_t Size)
 
static DecodeStatus DecodeIntRegsRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t, void const *Decoder)
 
static DecodeStatus DecodeDoubleRegsRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t, const void *Decoder)
 
static DecodeStatus DecodePredRegsRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t, void const *Decoder)
 
static MCDisassemblercreateHexagonDisassembler (Target const &T, MCSubtargetInfo const &STI, MCContext &Ctx)
 
void LLVMInitializeHexagonDisassembler ()
 
static unsigned getRegFromSubinstEncoding (unsigned encoded_reg)
 
static unsigned getDRegFromSubinstEncoding (unsigned encoded_dreg)
 

Variables

static const uint16_t IntRegDecoderTable []
 
static const uint16_t PredRegDecoderTable []
 

Macro Definition Documentation

#define DEBUG_TYPE   "hexagon-disassembler"

Definition at line 34 of file HexagonDisassembler.cpp.

Typedef Documentation

Definition at line 37 of file HexagonDisassembler.cpp.

Enumeration Type Documentation

Enumerator
V4_SA1_addi_BITS 
V4_SA1_addi_MASK 
V4_SA1_addrx_BITS 
V4_SA1_addrx_MASK 
V4_SA1_addsp_BITS 
V4_SA1_addsp_MASK 
V4_SA1_and1_BITS 
V4_SA1_and1_MASK 
V4_SA1_clrf_BITS 
V4_SA1_clrf_MASK 
V4_SA1_clrfnew_BITS 
V4_SA1_clrfnew_MASK 
V4_SA1_clrt_BITS 
V4_SA1_clrt_MASK 
V4_SA1_clrtnew_BITS 
V4_SA1_clrtnew_MASK 
V4_SA1_cmpeqi_BITS 
V4_SA1_cmpeqi_MASK 
V4_SA1_combine0i_BITS 
V4_SA1_combine0i_MASK 
V4_SA1_combine1i_BITS 
V4_SA1_combine1i_MASK 
V4_SA1_combine2i_BITS 
V4_SA1_combine2i_MASK 
V4_SA1_combine3i_BITS 
V4_SA1_combine3i_MASK 
V4_SA1_combinerz_BITS 
V4_SA1_combinerz_MASK 
V4_SA1_combinezr_BITS 
V4_SA1_combinezr_MASK 
V4_SA1_dec_BITS 
V4_SA1_dec_MASK 
V4_SA1_inc_BITS 
V4_SA1_inc_MASK 
V4_SA1_seti_BITS 
V4_SA1_seti_MASK 
V4_SA1_setin1_BITS 
V4_SA1_setin1_MASK 
V4_SA1_sxtb_BITS 
V4_SA1_sxtb_MASK 
V4_SA1_sxth_BITS 
V4_SA1_sxth_MASK 
V4_SA1_tfr_BITS 
V4_SA1_tfr_MASK 
V4_SA1_zxtb_BITS 
V4_SA1_zxtb_MASK 
V4_SA1_zxth_BITS 
V4_SA1_zxth_MASK 
V4_SL1_loadri_io_BITS 
V4_SL1_loadri_io_MASK 
V4_SL1_loadrub_io_BITS 
V4_SL1_loadrub_io_MASK 
V4_SL2_deallocframe_BITS 
V4_SL2_deallocframe_MASK 
V4_SL2_jumpr31_BITS 
V4_SL2_jumpr31_MASK 
V4_SL2_jumpr31_f_BITS 
V4_SL2_jumpr31_f_MASK 
V4_SL2_jumpr31_fnew_BITS 
V4_SL2_jumpr31_fnew_MASK 
V4_SL2_jumpr31_t_BITS 
V4_SL2_jumpr31_t_MASK 
V4_SL2_jumpr31_tnew_BITS 
V4_SL2_jumpr31_tnew_MASK 
V4_SL2_loadrb_io_BITS 
V4_SL2_loadrb_io_MASK 
V4_SL2_loadrd_sp_BITS 
V4_SL2_loadrd_sp_MASK 
V4_SL2_loadrh_io_BITS 
V4_SL2_loadrh_io_MASK 
V4_SL2_loadri_sp_BITS 
V4_SL2_loadri_sp_MASK 
V4_SL2_loadruh_io_BITS 
V4_SL2_loadruh_io_MASK 
V4_SL2_return_BITS 
V4_SL2_return_MASK 
V4_SL2_return_f_BITS 
V4_SL2_return_f_MASK 
V4_SL2_return_fnew_BITS 
V4_SL2_return_fnew_MASK 
V4_SL2_return_t_BITS 
V4_SL2_return_t_MASK 
V4_SL2_return_tnew_BITS 
V4_SL2_return_tnew_MASK 
V4_SS1_storeb_io_BITS 
V4_SS1_storeb_io_MASK 
V4_SS1_storew_io_BITS 
V4_SS1_storew_io_MASK 
V4_SS2_allocframe_BITS 
V4_SS2_allocframe_MASK 
V4_SS2_storebi0_BITS 
V4_SS2_storebi0_MASK 
V4_SS2_storebi1_BITS 
V4_SS2_storebi1_MASK 
V4_SS2_stored_sp_BITS 
V4_SS2_stored_sp_MASK 
V4_SS2_storeh_io_BITS 
V4_SS2_storeh_io_MASK 
V4_SS2_storew_sp_BITS 
V4_SS2_storew_sp_MASK 
V4_SS2_storewi0_BITS 
V4_SS2_storewi0_MASK 
V4_SS2_storewi1_BITS 
V4_SS2_storewi1_MASK 

Definition at line 478 of file HexagonDisassembler.cpp.

Function Documentation

static void AddSubinstOperands ( MCInst MI,
unsigned  opcode,
unsigned  inst 
)
static
static MCDisassembler* createHexagonDisassembler ( Target const T,
MCSubtargetInfo const STI,
MCContext Ctx 
)
static

Definition at line 217 of file HexagonDisassembler.cpp.

Referenced by LLVMInitializeHexagonDisassembler().

static DecodeStatus DecodeCtrRegs64RegisterClass ( MCInst Inst,
unsigned  RegNo,
uint64_t  Address,
void const Decoder 
)
static
static DecodeStatus DecodeCtrRegsRegisterClass ( MCInst Inst,
unsigned  RegNo,
uint64_t  Address,
const void *  Decoder 
)
static
static DecodeStatus DecodeDoubleRegsRegisterClass ( MCInst Inst,
unsigned  RegNo,
uint64_t  ,
const void *  Decoder 
)
static

Definition at line 191 of file HexagonDisassembler.cpp.

References DecodeRegisterClass().

static DecodeStatus DecodeIntRegsRegisterClass ( MCInst Inst,
unsigned  RegNo,
uint64_t  ,
void const Decoder 
)
static
static DecodeStatus DecodeModRegsRegisterClass ( MCInst Inst,
unsigned  RegNo,
uint64_t  Address,
const void *  Decoder 
)
static
static DecodeStatus DecodePredRegsRegisterClass ( MCInst Inst,
unsigned  RegNo,
uint64_t  ,
void const Decoder 
)
static
static DecodeStatus DecodeRegisterClass ( MCInst Inst,
unsigned  RegNo,
const uint16_t  Table[],
size_t  Size 
)
static
static unsigned getDRegFromSubinstEncoding ( unsigned  encoded_dreg)
static

Definition at line 737 of file HexagonDisassembler.cpp.

Referenced by AddSubinstOperands().

static unsigned getRegFromSubinstEncoding ( unsigned  encoded_reg)
static

Definition at line 729 of file HexagonDisassembler.cpp.

Referenced by AddSubinstOperands().

static unsigned GetSubinstOpcode ( unsigned  IClass,
unsigned  inst,
unsigned op,
raw_ostream os 
)
static

Definition at line 585 of file HexagonDisassembler.cpp.

References llvm::MCDisassembler::Fail, llvm::HexagonII::HSIG_A, llvm::HexagonII::HSIG_L1, llvm::HexagonII::HSIG_L2, llvm::HexagonII::HSIG_S1, llvm::HexagonII::HSIG_S2, llvm::MCDisassembler::Success, V4_SA1_addi_BITS, V4_SA1_addi_MASK, V4_SA1_addrx_BITS, V4_SA1_addrx_MASK, V4_SA1_addsp_BITS, V4_SA1_addsp_MASK, V4_SA1_and1_BITS, V4_SA1_and1_MASK, V4_SA1_clrf_BITS, V4_SA1_clrf_MASK, V4_SA1_clrfnew_BITS, V4_SA1_clrfnew_MASK, V4_SA1_clrt_BITS, V4_SA1_clrt_MASK, V4_SA1_clrtnew_BITS, V4_SA1_clrtnew_MASK, V4_SA1_cmpeqi_BITS, V4_SA1_cmpeqi_MASK, V4_SA1_combine0i_BITS, V4_SA1_combine0i_MASK, V4_SA1_combine1i_BITS, V4_SA1_combine1i_MASK, V4_SA1_combine2i_BITS, V4_SA1_combine2i_MASK, V4_SA1_combine3i_BITS, V4_SA1_combine3i_MASK, V4_SA1_combinerz_BITS, V4_SA1_combinerz_MASK, V4_SA1_combinezr_BITS, V4_SA1_combinezr_MASK, V4_SA1_dec_BITS, V4_SA1_dec_MASK, V4_SA1_inc_BITS, V4_SA1_inc_MASK, V4_SA1_seti_BITS, V4_SA1_seti_MASK, V4_SA1_setin1_BITS, V4_SA1_setin1_MASK, V4_SA1_sxtb_BITS, V4_SA1_sxtb_MASK, V4_SA1_sxth_BITS, V4_SA1_sxth_MASK, V4_SA1_tfr_BITS, V4_SA1_tfr_MASK, V4_SA1_zxtb_BITS, V4_SA1_zxtb_MASK, V4_SA1_zxth_BITS, V4_SA1_zxth_MASK, V4_SL1_loadri_io_BITS, V4_SL1_loadri_io_MASK, V4_SL1_loadrub_io_BITS, V4_SL1_loadrub_io_MASK, V4_SL2_deallocframe_BITS, V4_SL2_deallocframe_MASK, V4_SL2_jumpr31_BITS, V4_SL2_jumpr31_f_BITS, V4_SL2_jumpr31_f_MASK, V4_SL2_jumpr31_fnew_BITS, V4_SL2_jumpr31_fnew_MASK, V4_SL2_jumpr31_MASK, V4_SL2_jumpr31_t_BITS, V4_SL2_jumpr31_t_MASK, V4_SL2_jumpr31_tnew_BITS, V4_SL2_jumpr31_tnew_MASK, V4_SL2_loadrb_io_BITS, V4_SL2_loadrb_io_MASK, V4_SL2_loadrd_sp_BITS, V4_SL2_loadrd_sp_MASK, V4_SL2_loadrh_io_BITS, V4_SL2_loadrh_io_MASK, V4_SL2_loadri_sp_BITS, V4_SL2_loadri_sp_MASK, V4_SL2_loadruh_io_BITS, V4_SL2_loadruh_io_MASK, V4_SL2_return_BITS, V4_SL2_return_f_BITS, V4_SL2_return_f_MASK, V4_SL2_return_fnew_BITS, V4_SL2_return_fnew_MASK, V4_SL2_return_MASK, V4_SL2_return_t_BITS, V4_SL2_return_t_MASK, V4_SL2_return_tnew_BITS, V4_SL2_return_tnew_MASK, V4_SS1_storeb_io_BITS, V4_SS1_storeb_io_MASK, V4_SS1_storew_io_BITS, V4_SS1_storew_io_MASK, V4_SS2_allocframe_BITS, V4_SS2_allocframe_MASK, V4_SS2_storebi0_BITS, V4_SS2_storebi0_MASK, V4_SS2_storebi1_BITS, V4_SS2_storebi1_MASK, V4_SS2_stored_sp_BITS, V4_SS2_stored_sp_MASK, V4_SS2_storeh_io_BITS, V4_SS2_storeh_io_MASK, V4_SS2_storew_sp_BITS, V4_SS2_storew_sp_MASK, V4_SS2_storewi0_BITS, V4_SS2_storewi0_MASK, V4_SS2_storewi1_BITS, and V4_SS2_storewi1_MASK.

void LLVMInitializeHexagonDisassembler ( )
static DecodeStatus s10ImmDecoder ( MCInst MI,
unsigned  tmp,
uint64_t  Address,
const void *  Decoder 
)
static
static DecodeStatus s11_0ImmDecoder ( MCInst MI,
unsigned  tmp,
uint64_t  Address,
const void *  Decoder 
)
static
static DecodeStatus s11_1ImmDecoder ( MCInst MI,
unsigned  tmp,
uint64_t  Address,
const void *  Decoder 
)
static
static DecodeStatus s11_2ImmDecoder ( MCInst MI,
unsigned  tmp,
uint64_t  Address,
const void *  Decoder 
)
static
static DecodeStatus s11_3ImmDecoder ( MCInst MI,
unsigned  tmp,
uint64_t  Address,
const void *  Decoder 
)
static
static DecodeStatus s12ImmDecoder ( MCInst MI,
unsigned  tmp,
uint64_t  Address,
const void *  Decoder 
)
static
static DecodeStatus s16ImmDecoder ( MCInst MI,
unsigned  tmp,
uint64_t  Address,
const void *  Decoder 
)
static
static DecodeStatus s4_0ImmDecoder ( MCInst MI,
unsigned  tmp,
uint64_t  Address,
const void *  Decoder 
)
static
static DecodeStatus s4_1ImmDecoder ( MCInst MI,
unsigned  tmp,
uint64_t  Address,
const void *  Decoder 
)
static
static DecodeStatus s4_2ImmDecoder ( MCInst MI,
unsigned  tmp,
uint64_t  Address,
const void *  Decoder 
)
static
static DecodeStatus s4_3ImmDecoder ( MCInst MI,
unsigned  tmp,
uint64_t  Address,
const void *  Decoder 
)
static
static DecodeStatus s6_0ImmDecoder ( MCInst MI,
unsigned  tmp,
uint64_t  Address,
const void *  Decoder 
)
static
static DecodeStatus s8ImmDecoder ( MCInst MI,
unsigned  tmp,
uint64_t  Address,
const void *  Decoder 
)
static

Variable Documentation

const uint16_t IntRegDecoderTable[]
static
Initial value:
= {
Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9,
Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,
Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24,
Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29,
Hexagon::R30, Hexagon::R31}
#define R4(n)
#define R2(n)
#define R6(n)

Definition at line 99 of file HexagonDisassembler.cpp.

Referenced by DecodeIntRegsRegisterClass().

const uint16_t PredRegDecoderTable[]
static
Initial value:
= {Hexagon::P0, Hexagon::P1,
Hexagon::P2, Hexagon::P3}

Definition at line 108 of file HexagonDisassembler.cpp.

Referenced by DecodePredRegsRegisterClass().