27 #define DEBUG_TYPE "legalize-types"
37 void DAGTypeLegalizer::PromoteIntegerResult(
SDNode *
N,
unsigned ResNo) {
48 dbgs() <<
"PromoteIntegerResult #" << ResNo <<
": ";
55 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N);
break;
56 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N);
break;
60 Res = PromoteIntRes_CONVERT_RNDSAT(N);
break;
62 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N);
break;
63 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N);
break;
65 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N);
break;
67 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N);
break;
68 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));
break;
69 case ISD::MLOAD: Res = PromoteIntRes_MLOAD(cast<MaskedLoadSDNode>(N));
break;
70 case ISD::SELECT: Res = PromoteIntRes_SELECT(N);
break;
71 case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N);
break;
73 case ISD::SETCC: Res = PromoteIntRes_SETCC(N);
break;
77 case ISD::UMAX: Res = PromoteIntRes_SimpleIntBinOp(N);
break;
78 case ISD::SHL: Res = PromoteIntRes_SHL(N);
break;
80 Res = PromoteIntRes_SIGN_EXTEND_INREG(N);
break;
81 case ISD::SRA: Res = PromoteIntRes_SRA(N);
break;
82 case ISD::SRL: Res = PromoteIntRes_SRL(N);
break;
84 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N);
break;
85 case ISD::VAARG: Res = PromoteIntRes_VAARG(N);
break;
88 Res = PromoteIntRes_EXTRACT_SUBVECTOR(N);
break;
90 Res = PromoteIntRes_VECTOR_SHUFFLE(N);
break;
92 Res = PromoteIntRes_INSERT_VECTOR_ELT(N);
break;
94 Res = PromoteIntRes_BUILD_VECTOR(N);
break;
96 Res = PromoteIntRes_SCALAR_TO_VECTOR(N);
break;
98 Res = PromoteIntRes_CONCAT_VECTORS(N);
break;
114 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N);
break;
117 case ISD::SREM: Res = PromoteIntRes_SDIV(N);
break;
120 case ISD::UREM: Res = PromoteIntRes_UDIV(N);
break;
123 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo);
break;
125 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo);
break;
127 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo);
break;
130 Res = PromoteIntRes_Atomic0(cast<AtomicSDNode>(N));
break;
143 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N));
break;
147 Res = PromoteIntRes_AtomicCmpSwap(cast<AtomicSDNode>(N), ResNo);
153 SetPromotedInteger(
SDValue(N, ResNo), Res);
158 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
159 return GetPromotedInteger(Op);
169 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(
SDNode *N) {
234 for (
unsigned i = 1, NumResults = N->
getNumValues(); i < NumResults; ++i)
247 switch (getTypeAction(InVT)) {
260 if (NOutVT.
bitsEq(NInVT)) {
261 SDValue PromotedOp = GetPromotedFloat(InOp);
275 BitConvertToInteger(GetScalarizedVector(InOp)));
282 Lo = BitConvertToInteger(Lo);
283 Hi = BitConvertToInteger(Hi);
291 JoinIntegers(Lo, Hi));
303 CreateStackStoreLoad(InOp, OutVT));
319 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(
SDNode *N) {
328 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(
SDNode *N) {
338 assert(isa<ConstantSDNode>(Result) &&
"Didn't constant fold ext?");
342 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(
SDNode *N) {
347 "can only promote integers");
384 OVT.getScalarSizeInBits());
390 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(
SDNode *N) {
397 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(
SDNode *N) {
421 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_FP16(
SDNode *N) {
431 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(
SDNode *N) {
479 EVT NewMaskVT = getSetCCResultType(NVT);
481 Mask = PromoteTargetBoolean(Mask, NewMaskVT);
493 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(
SDNode *N) {
503 ReplaceValueWith(
SDValue(N, 0), Res);
508 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(
SDNode *N,
unsigned ResNo) {
510 return PromoteIntRes_Overflow(N);
532 ReplaceValueWith(
SDValue(N, 1), Ofl);
557 Mask = PromoteTargetBoolean(Mask, OpTy);
564 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(
SDNode *N) {
584 "Vector compare must return a vector result!");
590 !LHS.getValueType().isVector())
591 LHS = GetPromotedInteger(LHS);
594 RHS = GetPromotedInteger(RHS);
601 assert(NVT.bitsLE(SVT) &&
"Integer type overpromoted?");
610 LHS = GetPromotedInteger(LHS);
612 RHS = ZExtPromotedInteger(RHS);
616 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(
SDNode *N) {
622 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(
SDNode *N) {
637 LHS = SExtPromotedInteger(LHS);
639 RHS = ZExtPromotedInteger(RHS);
648 LHS = ZExtPromotedInteger(LHS);
650 RHS = ZExtPromotedInteger(RHS);
654 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(
SDNode *N) {
667 Res = GetPromotedInteger(InOp);
671 assert(InVT.
isVector() &&
"Cannot split scalar types");
674 "Dst and Src must have the same number of elements");
676 "Promoted vector type must be a power of two");
679 GetSplitVector(InOp, EOp1, EOp2);
693 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(
SDNode *N,
unsigned ResNo) {
695 return PromoteIntRes_Overflow(N);
716 ReplaceValueWith(
SDValue(N, 1), Ofl);
721 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(
SDNode *N,
unsigned ResNo) {
724 return PromoteIntRes_Overflow(N);
735 LHS = SExtPromotedInteger(LHS);
736 RHS = SExtPromotedInteger(RHS);
738 LHS = ZExtPromotedInteger(LHS);
739 RHS = ZExtPromotedInteger(RHS);
769 ReplaceValueWith(
SDValue(N, 1), Overflow);
797 for (
unsigned i = 0; i < NumRegs; ++i) {
805 std::reverse(Parts.begin(), Parts.end());
810 for (
unsigned i = 1; i < NumRegs; ++i) {
821 ReplaceValueWith(
SDValue(N, 1), Chain);
834 bool DAGTypeLegalizer::PromoteIntegerOperand(
SDNode *N,
unsigned OpNo) {
844 dbgs() <<
"PromoteIntegerOperand Op #" << OpNo <<
": ";
851 Res = PromoteIntOp_ATOMIC_STORE(cast<AtomicSDNode>(N));
853 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N);
break;
854 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo);
break;
855 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo);
break;
861 Res = PromoteIntOp_CONVERT_RNDSAT(N);
break;
863 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);
break;
865 Res = PromoteIntOp_SCALAR_TO_VECTOR(N);
break;
867 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo);
break;
868 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo);
break;
869 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo);
break;
872 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
874 case ISD::MSTORE: Res = PromoteIntOp_MSTORE(cast<MaskedStoreSDNode>(N),
876 case ISD::MLOAD: Res = PromoteIntOp_MLOAD(cast<MaskedLoadSDNode>(N),
888 case ISD::ROTR: Res = PromoteIntOp_Shift(N);
break;
892 if (!Res.getNode())
return false;
896 if (Res.getNode() ==
N)
900 "Invalid operand expansion");
902 ReplaceValueWith(
SDValue(N, 0), Res);
908 void DAGTypeLegalizer::PromoteSetCCOperands(
SDValue &NewLHS,
SDValue &NewRHS,
917 SDValue OpL = GetPromotedInteger(NewLHS);
918 SDValue OpR = GetPromotedInteger(NewRHS);
931 NewLHS = ZExtPromotedInteger(NewLHS);
932 NewRHS = ZExtPromotedInteger(NewRHS);
943 NewLHS = ZExtPromotedInteger(NewLHS);
944 NewRHS = ZExtPromotedInteger(NewRHS);
950 NewLHS = SExtPromotedInteger(NewLHS);
951 NewRHS = SExtPromotedInteger(NewRHS);
956 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(
SDNode *N) {
974 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(
SDNode *N,
unsigned OpNo) {
975 assert(OpNo == 2 &&
"Don't know how to promote this operand!");
979 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->
getOperand(1))->
get());
988 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(
SDNode *N,
unsigned OpNo) {
989 assert(OpNo == 1 &&
"only know how to promote condition");
999 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(
SDNode *N) {
1013 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(
SDNode *N) {
1019 assert(!((NumElts & 1) && (!TLI.
isTypeLegal(VecVT))) &&
1020 "Legal vector of one illegal element?");
1027 "Type of inserted value narrower than vector element type!");
1030 for (
unsigned i = 0; i < NumElts; ++i)
1036 SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(
SDNode *N) {
1037 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(
N)->getCvtCode();
1041 "can only promote integer arguments");
1048 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(
SDNode *N,
1057 "Type of inserted value narrower than vector element type!");
1064 assert(OpNo == 2 &&
"Different operand and result vector types?");
1073 SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(
SDNode *N) {
1080 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(
SDNode *N,
unsigned OpNo) {
1081 assert(OpNo == 0 &&
"Only know how to promote the condition!");
1087 Cond = PromoteTargetBoolean(Cond, OpVT);
1093 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(
SDNode *N,
unsigned OpNo) {
1094 assert(OpNo == 0 &&
"Don't know how to promote this operand!");
1098 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->
getOperand(4))->
get());
1105 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(
SDNode *N,
unsigned OpNo) {
1106 assert(OpNo == 0 &&
"Don't know how to promote this operand!");
1110 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->
getOperand(2))->
get());
1121 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(
SDNode *N) {
1129 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(
SDNode *N) {
1154 bool TruncateStore =
false;
1157 DataOp = GetPromotedInteger(DataOp);
1159 Mask = PromoteTargetBoolean(Mask, DataOp.
getValueType());
1160 TruncateStore =
true;
1164 "Unexpected data legalization in MSTORE");
1165 DataOp = GetWidenedVector(DataOp);
1168 Mask = GetWidenedVector(Mask);
1177 unsigned NumConcat = WidenNumElts / MaskNumElts;
1181 for (
unsigned i = 1; i != NumConcat; ++i)
1196 assert(OpNo == 2 &&
"Only know how to promote the mask!");
1200 NewOps[OpNo] = Mask;
1204 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(
SDNode *N) {
1209 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(
SDNode *N) {
1214 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(
SDNode *N) {
1231 void DAGTypeLegalizer::ExpandIntegerResult(
SDNode *N,
unsigned ResNo) {
1243 dbgs() <<
"ExpandIntegerResult #" << ResNo <<
": ";
1246 llvm_unreachable(
"Do not know how to expand the result of this operator!");
1249 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi);
break;
1251 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi);
break;
1253 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi);
break;
1257 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi);
break;
1262 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi);
break;
1263 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi);
break;
1265 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi);
break;
1266 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi);
break;
1268 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi);
break;
1271 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
break;
1272 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi);
break;
1273 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi);
break;
1276 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi);
break;
1277 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi);
break;
1278 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi);
break;
1279 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi);
break;
1295 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(N);
1296 SplitInteger(Tmp.first, Lo, Hi);
1297 ReplaceValueWith(
SDValue(N, 1), Tmp.second);
1315 SplitInteger(Tmp, Lo, Hi);
1316 ReplaceValueWith(
SDValue(N, 1), Success);
1323 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi);
break;
1326 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi);
break;
1329 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi);
break;
1332 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi);
break;
1336 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi);
break;
1339 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi);
break;
1341 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi);
break;
1343 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi);
break;
1352 std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(
SDNode *Node) {
1358 return ExpandChainLibCall(LC, Node,
false);
1363 void DAGTypeLegalizer::ExpandShiftByConstant(
SDNode *N,
const APInt &Amt,
1368 GetExpandedInteger(N->
getOperand(0), InL, InH);
1384 if (Amt.
ugt(VTBits)) {
1386 }
else if (Amt.
ugt(NVTBits)) {
1390 }
else if (Amt == NVTBits) {
1393 }
else if (Amt == 1 &&
1398 SDValue LoOps[2] = { InL, InL };
1414 if (Amt.
ugt(VTBits)) {
1416 }
else if (Amt.
ugt(NVTBits)) {
1420 }
else if (Amt == NVTBits) {
1435 if (Amt.
ugt(VTBits)) {
1438 }
else if (Amt.
ugt(NVTBits)) {
1443 }
else if (Amt == NVTBits) {
1461 bool DAGTypeLegalizer::
1469 "Expanded integer type size not a power of two!");
1473 APInt KnownZero, KnownOne;
1477 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1482 GetExpandedInteger(N->
getOperand(0), InL, InH);
1511 if ((KnownZero & HighBitMask) == HighBitMask) {
1549 bool DAGTypeLegalizer::
1556 "Expanded integer type size not a power of two!");
1561 GetExpandedInteger(N->
getOperand(0), InL, InH);
1586 Lo = DAG.
getSelect(dl, NVT, isShort, LoS, LoL);
1587 Hi = DAG.
getSelect(dl, NVT, isZero, InH,
1588 DAG.
getSelect(dl, NVT, isShort, HiS, HiL));
1603 Lo = DAG.
getSelect(dl, NVT, isZero, InL,
1604 DAG.
getSelect(dl, NVT, isShort, LoS, LoL));
1605 Hi = DAG.
getSelect(dl, NVT, isShort, HiS, HiL);
1619 Lo = DAG.
getSelect(dl, NVT, isZero, InL,
1620 DAG.
getSelect(dl, NVT, isShort, LoS, LoL));
1621 Hi = DAG.
getSelect(dl, NVT, isShort, HiS, HiL);
1626 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(
SDNode *N,
1630 SDValue LHSL, LHSH, RHSL, RHSH;
1631 GetExpandedInteger(N->
getOperand(0), LHSL, LHSH);
1632 GetExpandedInteger(N->
getOperand(1), RHSL, RHSH);
1635 SDValue LoOps[2] = { LHSL, RHSL };
1636 SDValue HiOps[3] = { LHSH, RHSH };
1689 Hi = DAG.
getNode(RevOpc, dl, NVT, Hi, OVF);
1697 SDValue Cmp1 = DAG.
getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[0],
1702 SDValue Cmp2 = DAG.
getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[1],
1711 DAG.
getSetCC(dl, getSetCCResultType(LoOps[0].getValueType()),
1720 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(
SDNode *N,
1723 SDValue LHSL, LHSH, RHSL, RHSH;
1725 GetExpandedInteger(N->
getOperand(0), LHSL, LHSH);
1726 GetExpandedInteger(N->
getOperand(1), RHSL, RHSH);
1728 SDValue LoOps[2] = { LHSL, RHSL };
1729 SDValue HiOps[3] = { LHSH, RHSH };
1746 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(
SDNode *N,
1749 SDValue LHSL, LHSH, RHSL, RHSH;
1751 GetExpandedInteger(N->
getOperand(0), LHSL, LHSH);
1752 GetExpandedInteger(N->
getOperand(1), RHSL, RHSH);
1755 SDValue HiOps[3] = { LHSH, RHSH };
1766 void DAGTypeLegalizer::ExpandIntRes_MERGE_VALUES(
SDNode *N,
unsigned ResNo,
1768 SDValue Res = DisintegrateMERGE_VALUES(N, ResNo);
1769 SplitInteger(Res, Lo, Hi);
1772 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(
SDNode *N,
1786 "Only know how to promote this result!");
1787 SDValue Res = GetPromotedInteger(Op);
1789 "Operand over promoted?");
1791 SplitInteger(Res, Lo, Hi);
1795 void DAGTypeLegalizer::ExpandIntRes_AssertSext(
SDNode *N,
1801 unsigned NVTBits = NVT.getSizeInBits();
1804 if (NVTBits < EVTBits) {
1807 EVTBits - NVTBits)));
1817 void DAGTypeLegalizer::ExpandIntRes_AssertZext(
SDNode *N,
1822 EVT EVT = cast<VTSDNode>(N->
getOperand(1))->getVT();
1823 unsigned NVTBits = NVT.getSizeInBits();
1826 if (NVTBits < EVTBits) {
1829 EVTBits - NVTBits)));
1837 void DAGTypeLegalizer::ExpandIntRes_BSWAP(
SDNode *N,
1845 void DAGTypeLegalizer::ExpandIntRes_Constant(
SDNode *N,
1849 auto Constant = cast<ConstantSDNode>(
N);
1851 bool IsTarget =
Constant->isTargetOpcode();
1852 bool IsOpaque =
Constant->isOpaque();
1854 Lo = DAG.
getConstant(Cst.trunc(NBitWidth), dl, NVT, IsTarget, IsOpaque);
1855 Hi = DAG.
getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), dl, NVT, IsTarget,
1859 void DAGTypeLegalizer::ExpandIntRes_CTLZ(
SDNode *N,
1872 Lo = DAG.
getSelect(dl, NVT, HiNotZero, HiLZ,
1879 void DAGTypeLegalizer::ExpandIntRes_CTPOP(
SDNode *N,
1890 void DAGTypeLegalizer::ExpandIntRes_CTTZ(
SDNode *N,
1903 Lo = DAG.
getSelect(dl, NVT, LoNotZero, LoLZ,
1910 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(
SDNode *N,
SDValue &Lo,
1917 Op = GetPromotedFloat(Op);
1921 SplitInteger(TLI.
makeLibCall(DAG, LC, VT, &Op, 1,
true,
1926 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(
SDNode *N,
SDValue &Lo,
1933 Op = GetPromotedFloat(Op);
1937 SplitInteger(TLI.
makeLibCall(DAG, LC, VT, &Op, 1,
false,
1942 void DAGTypeLegalizer::ExpandIntRes_LOAD(
LoadSDNode *N,
1945 ExpandRes_NormalLoad(N, Lo, Hi);
1963 assert(NVT.
isByteSized() &&
"Expanded type not byte sized!");
1969 MemVT,
isVolatile, isNonTemporal, isInvariant,
1993 isVolatile, isNonTemporal, isInvariant, Alignment,
1996 unsigned ExcessBits =
2004 Hi = DAG.
getExtLoad(ExtType, dl, NVT, Ch, Ptr,
2007 MinAlign(Alignment, IncrementSize), AAInfo);
2019 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2025 isVolatile, isNonTemporal, isInvariant, Alignment,
2035 isVolatile, isNonTemporal, isInvariant,
2036 MinAlign(Alignment, IncrementSize), AAInfo);
2060 ReplaceValueWith(
SDValue(N, 1), Ch);
2063 void DAGTypeLegalizer::ExpandIntRes_Logical(
SDNode *N,
2067 GetExpandedInteger(N->
getOperand(0), LL, LH);
2068 GetExpandedInteger(N->
getOperand(1), RL, RH);
2073 void DAGTypeLegalizer::ExpandIntRes_MUL(
SDNode *N,
2080 GetExpandedInteger(N->
getOperand(0), LL, LH);
2081 GetExpandedInteger(N->
getOperand(1), RL, RH);
2083 if (TLI.
expandMUL(N, Lo, Hi, NVT, DAG, LL, LH, RL, RH))
2099 SplitInteger(TLI.
makeLibCall(DAG, LC, VT, Ops, 2,
true,
2104 void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(
SDNode *Node,
2115 SplitInteger(Sum, Lo, Hi);
2143 ReplaceValueWith(
SDValue(Node, 1), Cmp);
2146 void DAGTypeLegalizer::ExpandIntRes_SDIV(
SDNode *N,
2169 SplitInteger(TLI.
makeLibCall(DAG, LC, VT, Ops, 2,
true, dl).first,
Lo,
Hi);
2172 void DAGTypeLegalizer::ExpandIntRes_Shift(
SDNode *N,
2180 return ExpandShiftByConstant(N, CN->getAPIntValue(),
Lo,
Hi);
2184 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
2206 GetExpandedInteger(N->
getOperand(0), LHSL, LHSH);
2216 "ShiftAmountTy is too small to cover the range of this type!");
2220 SDValue Ops[] = { LHSL, LHSH, ShiftOp };
2264 SplitInteger(TLI.
makeLibCall(DAG, LC, VT, Ops, 2, isSigned, dl).first,
Lo,
2269 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
2273 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(
SDNode *N,
2291 "Only know how to promote this result!");
2292 SDValue Res = GetPromotedInteger(Op);
2294 "Operand over promoted?");
2296 SplitInteger(Res, Lo, Hi);
2297 unsigned ExcessBits =
2305 void DAGTypeLegalizer::
2309 EVT EVT = cast<VTSDNode>(N->
getOperand(1))->getVT();
2324 unsigned ExcessBits =
2332 void DAGTypeLegalizer::ExpandIntRes_SREM(
SDNode *N,
2355 SplitInteger(TLI.
makeLibCall(DAG, LC, VT, Ops, 2,
true, dl).first,
Lo,
Hi);
2358 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(
SDNode *N,
2370 void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(
SDNode *N,
2381 SplitInteger(Sum, Lo, Hi);
2390 ReplaceValueWith(
SDValue(N, 1), Ofl);
2393 void DAGTypeLegalizer::ExpandIntRes_XMULO(
SDNode *N,
2403 SplitInteger(MUL, Lo, Hi);
2417 ReplaceValueWith(
SDValue(N, 1), Overflow);
2450 Args.push_back(Entry);
2458 Args.push_back(Entry);
2463 CLI.setDebugLoc(dl).setChain(Chain)
2467 std::pair<SDValue, SDValue> CallInfo = TLI.
LowerCallTo(CLI);
2469 SplitInteger(CallInfo.first, Lo, Hi);
2476 ReplaceValueWith(
SDValue(N, 1), Ofl);
2479 void DAGTypeLegalizer::ExpandIntRes_UDIV(
SDNode *N,
2502 SplitInteger(TLI.
makeLibCall(DAG, LC, VT, Ops, 2,
false, dl).first,
Lo,
Hi);
2505 void DAGTypeLegalizer::ExpandIntRes_UREM(
SDNode *N,
2528 SplitInteger(TLI.
makeLibCall(DAG, LC, VT, Ops, 2,
false, dl).first,
Lo,
Hi);
2531 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(
SDNode *N,
2545 "Only know how to promote this result!");
2546 SDValue Res = GetPromotedInteger(Op);
2548 "Operand over promoted?");
2550 SplitInteger(Res, Lo, Hi);
2551 unsigned ExcessBits =
2559 void DAGTypeLegalizer::ExpandIntRes_ATOMIC_LOAD(
SDNode *N,
2562 EVT VT = cast<AtomicSDNode>(
N)->getMemoryVT();
2567 cast<AtomicSDNode>(N)->getMemoryVT(), VTs, N->
getOperand(0),
2568 N->
getOperand(1), Zero, Zero, cast<AtomicSDNode>(
N)->getMemOperand(),
2569 cast<AtomicSDNode>(
N)->getOrdering(),
2570 cast<AtomicSDNode>(
N)->getOrdering(),
2571 cast<AtomicSDNode>(
N)->getSynchScope());
2585 bool DAGTypeLegalizer::ExpandIntegerOperand(
SDNode *N,
unsigned OpNo) {
2595 dbgs() <<
"ExpandIntegerOperand Op #" << OpNo <<
": ";
2601 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N);
break;
2607 case ISD::SETCC: Res = ExpandIntOp_SETCC(N);
break;
2609 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo);
break;
2617 case ISD::ROTR: Res = ExpandIntOp_Shift(N);
break;
2625 if (!Res.getNode())
return false;
2629 if (Res.getNode() ==
N)
2633 "Invalid operand expansion");
2635 ReplaceValueWith(
SDValue(N, 0), Res);
2641 void DAGTypeLegalizer::IntegerExpandSetCCOperands(
SDValue &NewLHS,
2645 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
2646 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
2647 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
2650 if (RHSLo == RHSHi) {
2652 if (RHSCST->isAllOnesValue()) {
2672 if ((CCCode ==
ISD::SETLT && CST->isNullValue()) ||
2673 (CCCode ==
ISD::SETGT && CST->isAllOnesValue())) {
2705 LHSLo, RHSLo, LowCC,
false, DagCombineInfo, dl);
2708 LHSLo, RHSLo, LowCC);
2712 LHSHi, RHSHi, CCCode,
false, DagCombineInfo, dl);
2721 (Tmp2C && Tmp2C->isNullValue() &&
2724 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
2737 DagCombineInfo, dl);
2742 NewLHS, Tmp1, Tmp2);
2749 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode,
SDLoc(N));
2764 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(
SDNode *N) {
2767 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode,
SDLoc(N));
2785 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode,
SDLoc(N));
2790 "Unexpected setcc expansion!");
2808 SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(
SDNode *N) {
2817 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(
SDNode *N) {
2822 "Don't know how to expand this SINT_TO_FP!");
2828 return ExpandOp_NormalStore(N, OpNo);
2831 assert(OpNo == 1 &&
"Can only expand the stored value so far");
2844 assert(NVT.
isByteSized() &&
"Expanded type not byte sized!");
2858 isVolatile, isNonTemporal, Alignment, AAInfo);
2860 unsigned ExcessBits =
2871 MinAlign(Alignment, IncrementSize), AAInfo);
2880 unsigned EBytes = ExtVT.getStoreSize();
2882 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2884 ExtVT.getSizeInBits() - ExcessBits);
2900 HiVT,
isVolatile, isNonTemporal, Alignment, AAInfo);
2909 isVolatile, isNonTemporal,
2910 MinAlign(Alignment, IncrementSize), AAInfo);
2916 GetExpandedInteger(N->
getOperand(0), InL, InH);
2921 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(
SDNode *N) {
2941 const uint64_t F32TwoE32 = 0x4F800000ULL;
2942 const uint64_t F32TwoE64 = 0x5F800000ULL;
2943 const uint64_t F32TwoE128 = 0x7F800000ULL;
2947 FF =
APInt(32, F32TwoE32);
2949 FF =
APInt(32, F32TwoE64);
2951 FF =
APInt(32, F32TwoE128);
2957 GetExpandedInteger(Op, Lo, Hi);
2976 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
2979 Alignment =
std::min(Alignment, 4u);
2987 false,
false,
false, Alignment);
2994 "Don't know how to expand this UINT_TO_FP!");
2995 return TLI.
makeLibCall(DAG, LC, DstVT, &Op, 1,
true, dl).first;
2998 SDValue DAGTypeLegalizer::ExpandIntOp_ATOMIC_STORE(
SDNode *N) {
3001 cast<AtomicSDNode>(N)->getMemoryVT(),
3004 cast<AtomicSDNode>(
N)->getMemOperand(),
3005 cast<AtomicSDNode>(
N)->getOrdering(),
3006 cast<AtomicSDNode>(
N)->getSynchScope());
3011 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(
SDNode *N) {
3017 assert(NOutVT.
isVector() &&
"This type must be promoted to a vector type");
3026 for (
unsigned i = 0; i != OutNumElems; ++i) {
3043 SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(
SDNode *N) {
3058 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(
SDNode *N) {
3061 assert(NOutVT.
isVector() &&
"This type must be promoted to a vector type");
3069 for (
unsigned i = 0; i != NumElems; ++i) {
3085 SDValue DAGTypeLegalizer::PromoteIntRes_SCALAR_TO_VECTOR(
SDNode *N) {
3090 "Input must be a scalar");
3094 assert(NOutVT.
isVector() &&
"This type must be promoted to a vector type");
3102 SDValue DAGTypeLegalizer::PromoteIntRes_CONCAT_VECTORS(
SDNode *N) {
3107 assert(NOutVT.
isVector() &&
"This type must be promoted to a vector type");
3115 assert(NumElem * NumOperands == NumOutElem &&
3116 "Unexpected number of elements");
3120 for (
unsigned i = 0; i < NumOperands; ++i) {
3122 for (
unsigned j = 0; j < NumElem; ++j) {
3133 SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(
SDNode *N) {
3136 assert(NOutVT.
isVector() &&
"This type must be promoted to a vector type");
3149 SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_VECTOR_ELT(
SDNode *N) {
3163 SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_SUBVECTOR(
SDNode *N) {
3173 SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(
SDNode *N) {
3183 for (
unsigned VecIdx = 0; VecIdx != NumElems; ++VecIdx) {
3188 for (
unsigned i=0; i<NumElem; ++i) {
SDValue getTruncStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT TVT, bool isNonTemporal, bool isVolatile, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes())
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
void push_back(const T &Elt)
unsigned Log2_32_Ceil(uint32_t Value)
Log2_32_Ceil - This function returns the ceil log base 2 of the specified value, 32 if the value is z...
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
SDValue getValue(unsigned R) const
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant, which is required to be operand #1) half of the integer or float value specified as operand #0.
bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT, SelectionDAG &DAG, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) const
Expand a MUL into two nodes.
LLVMContext * getContext() const
void dump() const
Dump this node, for debugging.
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an vector value) starting with the ...
BR_CC - Conditional branch.
unsigned getNumRegisters(LLVMContext &Context, EVT VT) const
Return the number of registers that this ValueType will eventually require.
static MVT getVectorVT(MVT VT, unsigned NumElements)
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
SDValue getVAArg(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, SDValue SV, unsigned Align)
VAArg produces a result and token chain, and takes a pointer and a source value as input...
AtomicOrdering getSuccessOrdering() const
Carry-setting nodes for multiple precision addition and subtraction.
void computeKnownBits(SDValue Op, APInt &KnownZero, APInt &KnownOne, unsigned Depth=0) const
Determine which bits of Op are known to be either zero or one and return them in the KnownZero/KnownO...
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
const SDValue & getSrc0() const
Type * getTypeForEVT(LLVMContext &Context) const
getTypeForEVT - This method returns an LLVM type corresponding to the specified EVT.
unsigned getSizeInBits() const
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
SDValue getZeroExtendInReg(SDValue Op, SDLoc DL, EVT SrcTy)
Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value...
static const fltSemantics & EVTToAPFloatSemantics(EVT VT)
Returns an APFloat semantics tag appropriate for the given type.
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
unsigned getNumOperands() const
Return the number of values used by this operation.
EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
const SDValue & getOperand(unsigned Num) const
static MachinePointerInfo getConstantPool()
getConstantPool - Return a MachinePointerInfo record that refers to the constant pool.
[US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned integers.
CvtCode
CvtCode enum - This enum defines the various converts CONVERT_RNDSAT supports.
void reserve(size_type N)
LegalizeAction getOperationAction(unsigned Op, EVT VT) const
Return how this operation should be treated: either it is legal, needs to be promoted to a larger siz...
const SDValue & getBasePtr() const
SDValue getConstantPool(const Constant *C, EVT VT, unsigned Align=0, int Offs=0, bool isT=false, unsigned char TargetFlags=0)
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
bool bitsLT(EVT VT) const
bitsLT - Return true if this has less bits than VT.
This SDNode is used to implement the code generator support for the llvm IR shufflevector instruction...
SDValue getExternalSymbol(const char *Sym, EVT VT)
Libcall getUINTTOFP(EVT OpVT, EVT RetVT)
getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
bool isVector() const
isVector - Return true if this is a vector value type.
SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Shift and rotation operations.
bool isNormalStore(const SDNode *N)
Returns true if the specified node is a non-truncating and unindexed store.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
std::pair< SDValue, SDValue > makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops, unsigned NumOps, bool isSigned, SDLoc dl, bool doesNotReturn=false, bool isReturnValueUsed=true) const
Returns a pair of (return value, chain).
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
MachinePointerInfo getWithOffset(int64_t O) const
EVT getScalarType() const
getScalarType - If this is a vector type, return the element type, otherwise return this...
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) For double-word atomic operations: ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi) ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi) These correspond to the atomicrmw instruction.
Number of individual test Apply this number of consecutive mutations to each input exit after the first new interesting input is found the minimized corpus is saved into the first input directory Number of jobs to run If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG...
This is an SDNode representing atomic operations.
SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, SDLoc dl) const
Try to simplify a setcc built with the specified operands and cc.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
This class is used to represent an MSTORE node.
virtual MVT getVectorIdxTy(const DataLayout &DL) const
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
EVT getVectorElementType() const
getVectorElementType - Given a vector type, return the type of each element.
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
bool isUNINDEXEDStore(const SDNode *N)
Returns true if the specified node is an unindexed store.
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
Simple integer binary arithmetic operators.
SDValue getVectorShuffle(EVT VT, SDLoc dl, SDValue N1, SDValue N2, const int *MaskElts)
Return an ISD::VECTOR_SHUFFLE node.
AtomicOrdering getOrdering() const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
static unsigned int semanticsPrecision(const fltSemantics &)
bool isLittleEndian() const
Layout endianness...
const SDValue & getBasePtr() const
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
EVT getMemoryVT() const
Return the type of the in-memory value.
SDValue getAnyExtOrTrunc(SDValue Op, SDLoc DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either any-extending or truncat...
const DataLayout & getDataLayout() const
bool bitsLE(EVT VT) const
bitsLE - Return true if this has no more bits than VT.
UNDEF - An undefined node.
This class is used to represent ISD::STORE nodes.
const SDValue & getBasePtr() const
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable...
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Get a value with high bits set.
SDNode * getNode() const
get the SDNode which holds the desired result
unsigned getScalarSizeInBits() const
unsigned getStoreSize() const
getStoreSize - Return the number of bytes overwritten by a store of the specified value type...
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
bool isNormalLoad(const SDNode *N)
Returns true if the specified node is a non-extending and unindexed load.
SynchronizationScope getSynchScope() const
bool intersects(const APInt &RHS) const
This operation tests if there are any pairs of corresponding bits between this APInt and RHS that are...
MVT - Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Simple binary floating point operators.
bool isNonTemporal() const
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
This is an important base class in LLVM.
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
LegalizeAction
This enum indicates whether operations are valid for a target, and if not, what action should be used...
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL...
Carry-using nodes for multiple precision addition and subtraction.
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
AtomicOrdering getFailureOrdering() const
Libcall getFPTOSINT(EVT OpVT, EVT RetVT)
getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
static APInt getOneBitSet(unsigned numBits, unsigned BitNo)
Return an APInt with exactly one bit set in the result.
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
const SDValue & getValue() const
SDValue getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes())
Bit counting operators with an undefined result for zero inputs.
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo...
EVT - Extended Value Type.
std::vector< ArgListEntry > ArgListTy
const SDValue & getMask() const
bool bitsEq(EVT VT) const
bitsEq - Return true if this has the same number of bits as VT.
SDValue getMaskedLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, SDValue Mask, SDValue Src0, EVT MemVT, MachineMemOperand *MMO, ISD::LoadExtType)
This structure contains all information that is necessary for lowering calls.
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
For targets without i1 registers, this gives the nature of the high-bits of boolean values held in ty...
PointerType * getPointerTo(unsigned AddrSpace=0)
getPointerTo - Return a pointer to the current type.
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements)
getVectorVT - Returns the EVT that represents a vector NumElements in length, where each element is o...
MachinePointerInfo - This class contains a discriminated union of information about pointers in memor...
uint64_t getConstantOperandVal(unsigned Num) const
Helper method returns the integer value of a ConstantSDNode operand.
SDValue getMaskedStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, SDValue Mask, EVT MemVT, MachineMemOperand *MMO, bool IsTrunc)
SDValue CreateStackTemporary(EVT VT, unsigned minAlign=1)
Create a stack temporary, suitable for holding the specified value type.
const MachinePointerInfo & getPointerInfo() const
bool isUNINDEXEDLoad(const SDNode *N)
Returns true if the specified node is an unindexed load.
ArrayRef< int > getMask() const
bool ugt(const APInt &RHS) const
Unsigned greather than comparison.
TokenFactor - This node takes multiple tokens as input and produces a single token result...
SDValue getConvertRndSat(EVT VT, SDLoc dl, SDValue Val, SDValue DTy, SDValue STy, SDValue Rnd, SDValue Sat, ISD::CvtCode Code)
Returns the ConvertRndSat Note: Avoid using this node because it may disappear in the future and most...
const char * getLibcallName(RTLIB::Libcall Call) const
Get the libcall routine name for the specified libcall.
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
SDNode * UpdateNodeOperands(SDNode *N, SDValue Op)
Mutate the specified node in-place to have the specified operands.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
BRCOND - Conditional branch.
const SDValue & getChain() const
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Byte Swap and Counting operators.
FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions and truncation for half-preci...
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
SDValue getAtomic(unsigned Opcode, SDLoc dl, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Val, const Value *PtrVal, unsigned Alignment, AtomicOrdering Ordering, SynchronizationScope SynchScope)
Gets a node for an atomic op, produces result (if relevant) and chain and takes 2 operands...
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Represents one node in the SelectionDAG.
AAMDNodes getAAInfo() const
Returns the AA info that describes the dereference.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
unsigned Log2_32(uint32_t Value)
Log2_32 - This function returns the floor log base 2 of the specified value, -1 if the value is zero...
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
const SDValue & getValue() const
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
Class for arbitrary precision integers.
Select(COND, TRUEVAL, FALSEVAL).
op_iterator op_begin() const
ZERO_EXTEND - Used for integer types, zeroing the new bits.
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
ANY_EXTEND - Used for integer types. The high bits are undefined.
iterator_range< value_op_iterator > op_values() const
uint64_t MinAlign(uint64_t A, uint64_t B)
MinAlign - A and B are either alignments or offsets.
static bool isZero(Value *V, const DataLayout &DL, DominatorTree *DT, AssumptionCache *AC)
Libcall getFPTOUINT(EVT OpVT, EVT RetVT)
getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
Bitwise operators - logical and, logical or, logical xor.
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
op_iterator op_end() const
bool isNON_EXTLoad(const SDNode *N)
Returns true if the specified node is a non-extending load.
EVT getValueType() const
Return the ValueType of the referenced return value.
SDValue getCondCode(ISD::CondCode Cond)
Libcall getSINTTOFP(EVT OpVT, EVT RetVT)
getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
SDValue getConstant(uint64_t Val, SDLoc DL, EVT VT, bool isTarget=false, bool isOpaque=false)
CONVERT_RNDSAT - This operator is used to support various conversions between various types (float...
Libcall getATOMIC(unsigned Opc, MVT VT)
Return the SYNC_FETCH_AND_* value for the given opcode and type, or UNKNOWN_LIBCALL if there is none...
bool isByteSized() const
isByteSized - Return true if the bit size is a multiple of 8.
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
SDValue getSelect(SDLoc DL, EVT VT, SDValue Cond, SDValue LHS, SDValue RHS)
Helper function to make it easier to build Select's if you just have operands and don't want to check...
This class is used to represent an MLOAD node.
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
SDValue getZExtOrTrunc(SDValue Op, SDLoc DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either zero-extending or trunca...
EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
const SDValue & getBasePtr() const
SDValue getValueType(EVT)
bool isPowerOf2_32(uint32_t Value)
isPowerOf2_32 - This function returns true if the argument is a power of two > 0. ...
SetCC operator - This evaluates to a true value iff the condition is true.
SDValue getSetCC(SDLoc DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
static bool isVolatile(Instruction *Inst)
BooleanContent
Enum that describes how the target represents true/false values.
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val) This corresponds to "store atomic" instruction.
TRUNCATE - Completely drop the high bits.
EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL) const
unsigned getAlignment() const
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
getIntegerVT - Returns the EVT that represents an integer with the given number of bits...
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const
This callback is invoked for operations that are unsupported by the target, which are registered to u...
SDValue getAtomicCmpSwap(unsigned Opcode, SDLoc dl, EVT MemVT, SDVTList VTs, SDValue Chain, SDValue Ptr, SDValue Cmp, SDValue Swp, MachinePointerInfo PtrInfo, unsigned Alignment, AtomicOrdering SuccessOrdering, AtomicOrdering FailureOrdering, SynchronizationScope SynchScope)
Gets a node for an atomic cmpxchg op.
Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) This corresponds to "load atomic" instruction.
SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a scalar value into element 0 of the...
MVT getSimpleVT() const
getSimpleVT - Return the SimpleValueType held in the specified simple EVT.
SDValue getIntPtrConstant(uint64_t Val, SDLoc DL, bool isTarget=false)
unsigned getVectorNumElements() const
getVectorNumElements - Given a vector type, return the number of elements it contains.
This class is used to represent ISD::LOAD nodes.