LLVM  3.7.0
SIRegisterInfo.cpp
Go to the documentation of this file.
1 //===-- SIRegisterInfo.cpp - SI Register Information ---------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief SI implementation of the TargetRegisterInfo class.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 
16 #include "SIRegisterInfo.h"
17 #include "SIInstrInfo.h"
18 #include "SIMachineFunctionInfo.h"
22 #include "llvm/IR/Function.h"
23 #include "llvm/IR/LLVMContext.h"
24 
25 using namespace llvm;
26 
28 
30  BitVector Reserved(getNumRegs());
31  Reserved.set(AMDGPU::EXEC);
32 
33  // EXEC_LO and EXEC_HI could be allocated and used as regular register,
34  // but this seems likely to result in bugs, so I'm marking them as reserved.
35  Reserved.set(AMDGPU::EXEC_LO);
36  Reserved.set(AMDGPU::EXEC_HI);
37 
38  Reserved.set(AMDGPU::INDIRECT_BASE_ADDR);
39  Reserved.set(AMDGPU::FLAT_SCR);
40  Reserved.set(AMDGPU::FLAT_SCR_LO);
41  Reserved.set(AMDGPU::FLAT_SCR_HI);
42 
43  // Reserve some VGPRs to use as temp registers in case we have to spill VGPRs
44  Reserved.set(AMDGPU::VGPR255);
45  Reserved.set(AMDGPU::VGPR254);
46 
47  // Tonga and Iceland can only allocate a fixed number of SGPRs due
48  // to a hw bug.
50  unsigned NumSGPRs = AMDGPU::SGPR_32RegClass.getNumRegs();
51  // Reserve some SGPRs for FLAT_SCRATCH and VCC (4 SGPRs).
52  // Assume XNACK_MASK is unused.
54 
55  for (unsigned i = Limit; i < NumSGPRs; ++i) {
56  unsigned Reg = AMDGPU::SGPR_32RegClass.getRegister(i);
57  MCRegAliasIterator R = MCRegAliasIterator(Reg, this, true);
58 
59  for (; R.isValid(); ++R)
60  Reserved.set(*R);
61  }
62  }
63 
64  return Reserved;
65 }
66 
68  unsigned Idx) const {
69 
70  const AMDGPUSubtarget &STI = MF.getSubtarget<AMDGPUSubtarget>();
71  // FIXME: We should adjust the max number of waves based on LDS size.
72  unsigned SGPRLimit = getNumSGPRsAllowed(STI.getGeneration(),
73  STI.getMaxWavesPerCU());
74  unsigned VGPRLimit = getNumVGPRsAllowed(STI.getMaxWavesPerCU());
75 
76  for (regclass_iterator I = regclass_begin(), E = regclass_end();
77  I != E; ++I) {
78 
79  unsigned NumSubRegs = std::max((int)(*I)->getSize() / 4, 1);
80  unsigned Limit;
81 
82  if (isSGPRClass(*I)) {
83  Limit = SGPRLimit / NumSubRegs;
84  } else {
85  Limit = VGPRLimit / NumSubRegs;
86  }
87 
88  const int *Sets = getRegClassPressureSets(*I);
89  assert(Sets);
90  for (unsigned i = 0; Sets[i] != -1; ++i) {
91  if (Sets[i] == (int)Idx)
92  return Limit;
93  }
94  }
95  return 256;
96 }
97 
99  return Fn.getFrameInfo()->hasStackObjects();
100 }
101 
102 static unsigned getNumSubRegsForSpillOp(unsigned Op) {
103 
104  switch (Op) {
105  case AMDGPU::SI_SPILL_S512_SAVE:
106  case AMDGPU::SI_SPILL_S512_RESTORE:
107  case AMDGPU::SI_SPILL_V512_SAVE:
108  case AMDGPU::SI_SPILL_V512_RESTORE:
109  return 16;
110  case AMDGPU::SI_SPILL_S256_SAVE:
111  case AMDGPU::SI_SPILL_S256_RESTORE:
112  case AMDGPU::SI_SPILL_V256_SAVE:
113  case AMDGPU::SI_SPILL_V256_RESTORE:
114  return 8;
115  case AMDGPU::SI_SPILL_S128_SAVE:
116  case AMDGPU::SI_SPILL_S128_RESTORE:
117  case AMDGPU::SI_SPILL_V128_SAVE:
118  case AMDGPU::SI_SPILL_V128_RESTORE:
119  return 4;
120  case AMDGPU::SI_SPILL_V96_SAVE:
121  case AMDGPU::SI_SPILL_V96_RESTORE:
122  return 3;
123  case AMDGPU::SI_SPILL_S64_SAVE:
124  case AMDGPU::SI_SPILL_S64_RESTORE:
125  case AMDGPU::SI_SPILL_V64_SAVE:
126  case AMDGPU::SI_SPILL_V64_RESTORE:
127  return 2;
128  case AMDGPU::SI_SPILL_S32_SAVE:
129  case AMDGPU::SI_SPILL_S32_RESTORE:
130  case AMDGPU::SI_SPILL_V32_SAVE:
131  case AMDGPU::SI_SPILL_V32_RESTORE:
132  return 1;
133  default: llvm_unreachable("Invalid spill opcode");
134  }
135 }
136 
137 void SIRegisterInfo::buildScratchLoadStore(MachineBasicBlock::iterator MI,
138  unsigned LoadStoreOp,
139  unsigned Value,
140  unsigned ScratchRsrcReg,
141  unsigned ScratchOffset,
142  int64_t Offset,
143  RegScavenger *RS) const {
144 
145  MachineBasicBlock *MBB = MI->getParent();
146  const MachineFunction *MF = MI->getParent()->getParent();
147  const SIInstrInfo *TII =
148  static_cast<const SIInstrInfo *>(MF->getSubtarget().getInstrInfo());
149  LLVMContext &Ctx = MF->getFunction()->getContext();
150  DebugLoc DL = MI->getDebugLoc();
151  bool IsLoad = TII->get(LoadStoreOp).mayLoad();
152 
153  bool RanOutOfSGPRs = false;
154  unsigned SOffset = ScratchOffset;
155 
156  unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
157  unsigned Size = NumSubRegs * 4;
158 
159  if (!isUInt<12>(Offset + Size)) {
160  SOffset = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, MI, 0);
161  if (SOffset == AMDGPU::NoRegister) {
162  RanOutOfSGPRs = true;
163  SOffset = AMDGPU::SGPR0;
164  }
165  BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_U32), SOffset)
166  .addReg(ScratchOffset)
167  .addImm(Offset);
168  Offset = 0;
169  }
170 
171  if (RanOutOfSGPRs)
172  Ctx.emitError("Ran out of SGPRs for spilling VGPRS");
173 
174  for (unsigned i = 0, e = NumSubRegs; i != e; ++i, Offset += 4) {
175  unsigned SubReg = NumSubRegs > 1 ?
176  getPhysRegSubReg(Value, &AMDGPU::VGPR_32RegClass, i) :
177  Value;
178  bool IsKill = (i == e - 1);
179 
180  BuildMI(*MBB, MI, DL, TII->get(LoadStoreOp))
181  .addReg(SubReg, getDefRegState(IsLoad))
182  .addReg(ScratchRsrcReg, getKillRegState(IsKill))
183  .addReg(SOffset)
184  .addImm(Offset)
185  .addImm(0) // glc
186  .addImm(0) // slc
187  .addImm(0) // tfe
188  .addReg(Value, RegState::Implicit | getDefRegState(IsLoad));
189  }
190 }
191 
193  int SPAdj, unsigned FIOperandNum,
194  RegScavenger *RS) const {
195  MachineFunction *MF = MI->getParent()->getParent();
196  MachineBasicBlock *MBB = MI->getParent();
198  MachineFrameInfo *FrameInfo = MF->getFrameInfo();
199  const SIInstrInfo *TII =
200  static_cast<const SIInstrInfo *>(MF->getSubtarget().getInstrInfo());
201  DebugLoc DL = MI->getDebugLoc();
202 
203  MachineOperand &FIOp = MI->getOperand(FIOperandNum);
204  int Index = MI->getOperand(FIOperandNum).getIndex();
205 
206  switch (MI->getOpcode()) {
207  // SGPR register spill
208  case AMDGPU::SI_SPILL_S512_SAVE:
209  case AMDGPU::SI_SPILL_S256_SAVE:
210  case AMDGPU::SI_SPILL_S128_SAVE:
211  case AMDGPU::SI_SPILL_S64_SAVE:
212  case AMDGPU::SI_SPILL_S32_SAVE: {
213  unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
214 
215  for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
216  unsigned SubReg = getPhysRegSubReg(MI->getOperand(0).getReg(),
217  &AMDGPU::SGPR_32RegClass, i);
218  struct SIMachineFunctionInfo::SpilledReg Spill =
219  MFI->getSpilledReg(MF, Index, i);
220 
221  if (Spill.VGPR == AMDGPU::NoRegister) {
222  LLVMContext &Ctx = MF->getFunction()->getContext();
223  Ctx.emitError("Ran out of VGPRs for spilling SGPR");
224  }
225 
226  BuildMI(*MBB, MI, DL,
227  TII->getMCOpcodeFromPseudo(AMDGPU::V_WRITELANE_B32),
228  Spill.VGPR)
229  .addReg(SubReg)
230  .addImm(Spill.Lane);
231 
232  }
233  MI->eraseFromParent();
234  break;
235  }
236 
237  // SGPR register restore
238  case AMDGPU::SI_SPILL_S512_RESTORE:
239  case AMDGPU::SI_SPILL_S256_RESTORE:
240  case AMDGPU::SI_SPILL_S128_RESTORE:
241  case AMDGPU::SI_SPILL_S64_RESTORE:
242  case AMDGPU::SI_SPILL_S32_RESTORE: {
243  unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
244 
245  for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
246  unsigned SubReg = getPhysRegSubReg(MI->getOperand(0).getReg(),
247  &AMDGPU::SGPR_32RegClass, i);
248  struct SIMachineFunctionInfo::SpilledReg Spill =
249  MFI->getSpilledReg(MF, Index, i);
250 
251  if (Spill.VGPR == AMDGPU::NoRegister) {
252  LLVMContext &Ctx = MF->getFunction()->getContext();
253  Ctx.emitError("Ran out of VGPRs for spilling SGPR");
254  }
255 
256  BuildMI(*MBB, MI, DL,
257  TII->getMCOpcodeFromPseudo(AMDGPU::V_READLANE_B32),
258  SubReg)
259  .addReg(Spill.VGPR)
260  .addImm(Spill.Lane)
261  .addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine);
262  }
263 
264  // TODO: only do this when it is needed
265  switch (MF->getSubtarget<AMDGPUSubtarget>().getGeneration()) {
267  // "VALU writes SGPR" -> "SMRD reads that SGPR" needs "S_NOP 3" on SI
268  TII->insertNOPs(MI, 3);
269  break;
271  break;
272  default: // VOLCANIC_ISLANDS and later
273  // "VALU writes SGPR -> VMEM reads that SGPR" needs "S_NOP 4" on VI
274  // and later. This also applies to VALUs which write VCC, but we're
275  // unlikely to see VMEM use VCC.
276  TII->insertNOPs(MI, 4);
277  }
278 
279  MI->eraseFromParent();
280  break;
281  }
282 
283  // VGPR register spill
284  case AMDGPU::SI_SPILL_V512_SAVE:
285  case AMDGPU::SI_SPILL_V256_SAVE:
286  case AMDGPU::SI_SPILL_V128_SAVE:
287  case AMDGPU::SI_SPILL_V96_SAVE:
288  case AMDGPU::SI_SPILL_V64_SAVE:
289  case AMDGPU::SI_SPILL_V32_SAVE:
290  buildScratchLoadStore(MI, AMDGPU::BUFFER_STORE_DWORD_OFFSET,
291  TII->getNamedOperand(*MI, AMDGPU::OpName::src)->getReg(),
292  TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_rsrc)->getReg(),
293  TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_offset)->getReg(),
294  FrameInfo->getObjectOffset(Index), RS);
295  MI->eraseFromParent();
296  break;
297  case AMDGPU::SI_SPILL_V32_RESTORE:
298  case AMDGPU::SI_SPILL_V64_RESTORE:
299  case AMDGPU::SI_SPILL_V96_RESTORE:
300  case AMDGPU::SI_SPILL_V128_RESTORE:
301  case AMDGPU::SI_SPILL_V256_RESTORE:
302  case AMDGPU::SI_SPILL_V512_RESTORE: {
303  buildScratchLoadStore(MI, AMDGPU::BUFFER_LOAD_DWORD_OFFSET,
304  TII->getNamedOperand(*MI, AMDGPU::OpName::dst)->getReg(),
305  TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_rsrc)->getReg(),
306  TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_offset)->getReg(),
307  FrameInfo->getObjectOffset(Index), RS);
308  MI->eraseFromParent();
309  break;
310  }
311 
312  default: {
313  int64_t Offset = FrameInfo->getObjectOffset(Index);
314  FIOp.ChangeToImmediate(Offset);
315  if (!TII->isImmOperandLegal(MI, FIOperandNum, FIOp)) {
316  unsigned TmpReg = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, SPAdj);
317  BuildMI(*MBB, MI, MI->getDebugLoc(),
318  TII->get(AMDGPU::V_MOV_B32_e32), TmpReg)
319  .addImm(Offset);
320  FIOp.ChangeToRegister(TmpReg, false, false, true);
321  }
322  }
323  }
324 }
325 
327  MVT VT) const {
328  switch(VT.SimpleTy) {
329  default:
330  case MVT::i32: return &AMDGPU::VGPR_32RegClass;
331  }
332 }
333 
334 unsigned SIRegisterInfo::getHWRegIndex(unsigned Reg) const {
335  return getEncodingValue(Reg) & 0xff;
336 }
337 
340 
341  static const TargetRegisterClass *BaseClasses[] = {
342  &AMDGPU::VGPR_32RegClass,
343  &AMDGPU::SReg_32RegClass,
344  &AMDGPU::VReg_64RegClass,
345  &AMDGPU::SReg_64RegClass,
346  &AMDGPU::VReg_96RegClass,
347  &AMDGPU::VReg_128RegClass,
348  &AMDGPU::SReg_128RegClass,
349  &AMDGPU::VReg_256RegClass,
350  &AMDGPU::SReg_256RegClass,
351  &AMDGPU::VReg_512RegClass,
352  &AMDGPU::SReg_512RegClass
353  };
354 
355  for (const TargetRegisterClass *BaseClass : BaseClasses) {
356  if (BaseClass->contains(Reg)) {
357  return BaseClass;
358  }
359  }
360  return nullptr;
361 }
362 
364  return getCommonSubClass(&AMDGPU::VGPR_32RegClass, RC) ||
365  getCommonSubClass(&AMDGPU::VReg_64RegClass, RC) ||
366  getCommonSubClass(&AMDGPU::VReg_96RegClass, RC) ||
367  getCommonSubClass(&AMDGPU::VReg_128RegClass, RC) ||
368  getCommonSubClass(&AMDGPU::VReg_256RegClass, RC) ||
369  getCommonSubClass(&AMDGPU::VReg_512RegClass, RC);
370 }
371 
373  const TargetRegisterClass *SRC) const {
374  if (hasVGPRs(SRC)) {
375  return SRC;
376  } else if (SRC == &AMDGPU::SCCRegRegClass) {
377  return &AMDGPU::VCCRegRegClass;
378  } else if (getCommonSubClass(SRC, &AMDGPU::SGPR_32RegClass)) {
379  return &AMDGPU::VGPR_32RegClass;
380  } else if (getCommonSubClass(SRC, &AMDGPU::SGPR_64RegClass)) {
381  return &AMDGPU::VReg_64RegClass;
382  } else if (getCommonSubClass(SRC, &AMDGPU::SReg_128RegClass)) {
383  return &AMDGPU::VReg_128RegClass;
384  } else if (getCommonSubClass(SRC, &AMDGPU::SReg_256RegClass)) {
385  return &AMDGPU::VReg_256RegClass;
386  } else if (getCommonSubClass(SRC, &AMDGPU::SReg_512RegClass)) {
387  return &AMDGPU::VReg_512RegClass;
388  }
389  return nullptr;
390 }
391 
393  const TargetRegisterClass *RC, unsigned SubIdx) const {
394  if (SubIdx == AMDGPU::NoSubRegister)
395  return RC;
396 
397  // If this register has a sub-register, we can safely assume it is a 32-bit
398  // register, because all of SI's sub-registers are 32-bit.
399  if (isSGPRClass(RC)) {
400  return &AMDGPU::SGPR_32RegClass;
401  } else {
402  return &AMDGPU::VGPR_32RegClass;
403  }
404 }
405 
407  const TargetRegisterClass *SubRC,
408  unsigned Channel) const {
409 
410  switch (Reg) {
411  case AMDGPU::VCC:
412  switch(Channel) {
413  case 0: return AMDGPU::VCC_LO;
414  case 1: return AMDGPU::VCC_HI;
415  default: llvm_unreachable("Invalid SubIdx for VCC");
416  }
417 
418  case AMDGPU::FLAT_SCR:
419  switch (Channel) {
420  case 0:
421  return AMDGPU::FLAT_SCR_LO;
422  case 1:
423  return AMDGPU::FLAT_SCR_HI;
424  default:
425  llvm_unreachable("Invalid SubIdx for FLAT_SCR");
426  }
427  break;
428 
429  case AMDGPU::EXEC:
430  switch (Channel) {
431  case 0:
432  return AMDGPU::EXEC_LO;
433  case 1:
434  return AMDGPU::EXEC_HI;
435  default:
436  llvm_unreachable("Invalid SubIdx for EXEC");
437  }
438  break;
439  }
440 
441  const TargetRegisterClass *RC = getPhysRegClass(Reg);
442  // 32-bit registers don't have sub-registers, so we can just return the
443  // Reg. We need to have this check here, because the calculation below
444  // using getHWRegIndex() will fail with special 32-bit registers like
445  // VCC_LO, VCC_HI, EXEC_LO, EXEC_HI and M0.
446  if (RC->getSize() == 4) {
447  assert(Channel == 0);
448  return Reg;
449  }
450 
451  unsigned Index = getHWRegIndex(Reg);
452  return SubRC->getRegister(Index + Channel);
453 }
454 
455 bool SIRegisterInfo::opCanUseLiteralConstant(unsigned OpType) const {
456  return OpType == AMDGPU::OPERAND_REG_IMM32;
457 }
458 
459 bool SIRegisterInfo::opCanUseInlineConstant(unsigned OpType) const {
460  if (opCanUseLiteralConstant(OpType))
461  return true;
462 
463  return OpType == AMDGPU::OPERAND_REG_INLINE_C;
464 }
465 
467  enum PreloadedValue Value) const {
468 
470  switch (Value) {
472  return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 0);
474  return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 1);
476  return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 2);
478  if (MFI->getShaderType() != ShaderType::COMPUTE)
479  return MFI->ScratchOffsetReg;
480  return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 4);
482  return AMDGPU::SGPR2_SGPR3;
484  return AMDGPU::SGPR0_SGPR1;
486  return AMDGPU::VGPR0;
488  return AMDGPU::VGPR1;
490  return AMDGPU::VGPR2;
491  }
492  llvm_unreachable("unexpected preloaded value type");
493 }
494 
495 /// \brief Returns a register that is not used at any point in the function.
496 /// If all registers are used, then this function will return
497 // AMDGPU::NoRegister.
499  const TargetRegisterClass *RC) const {
500 
501  for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
502  I != E; ++I) {
503  if (!MRI.isPhysRegUsed(*I))
504  return *I;
505  }
506  return AMDGPU::NoRegister;
507 }
508 
509 unsigned SIRegisterInfo::getNumVGPRsAllowed(unsigned WaveCount) const {
510  switch(WaveCount) {
511  case 10: return 24;
512  case 9: return 28;
513  case 8: return 32;
514  case 7: return 36;
515  case 6: return 40;
516  case 5: return 48;
517  case 4: return 64;
518  case 3: return 84;
519  case 2: return 128;
520  default: return 256;
521  }
522 }
523 
525  unsigned WaveCount) const {
527  switch (WaveCount) {
528  case 10: return 80;
529  case 9: return 80;
530  case 8: return 96;
531  default: return 102;
532  }
533  } else {
534  switch(WaveCount) {
535  case 10: return 48;
536  case 9: return 56;
537  case 8: return 64;
538  case 7: return 72;
539  case 6: return 80;
540  case 5: return 96;
541  default: return 103;
542  }
543  }
544 }
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
bool opCanUseInlineConstant(unsigned OpType) const
BitVector & set()
Definition: BitVector.h:218
Interface definition for SIRegisterInfo.
unsigned getPhysRegSubReg(unsigned Reg, const TargetRegisterClass *SubRC, unsigned Channel) const
Channel This is the register channel (e.g.
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:223
unsigned getRegister(unsigned i) const
getRegister - Return the specified register in the class.
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
bool hasVGPRs(const TargetRegisterClass *RC) const
A debug info location.
Definition: DebugLoc.h:34
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
static unsigned getNumSubRegsForSpillOp(unsigned Op)
BitVector getReservedRegs(const MachineFunction &MF) const override
unsigned getSize() const
getSize - Return the size of the register in bytes, which is also the size of a stack slot allocated ...
bool hasSGPRInitBug() const
const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const override
get the register class of the specified type to use in the CFGStructurizer
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const HexagonInstrInfo * TII
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
MachineOperand * getNamedOperand(MachineInstr &MI, unsigned OperandName) const
Returns the operand named Op.
bool isSGPRClass(const TargetRegisterClass *RC) const
iterator begin() const
begin/end - Return all of the registers in this class.
Reg
All possible values of the reg field in the ModR/M byte.
bool requiresRegisterScavenging(const MachineFunction &Fn) const override
SimpleValueType SimpleTy
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
const MCInstrDesc & getMCOpcodeFromPseudo(unsigned Opcode) const
Return the descriptor of the target-specific machine instruction that corresponds to the specified ps...
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
void emitError(unsigned LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
unsigned getHWRegIndex(unsigned Reg) const override
bool hasStackObjects() const
Return true if there are any stack objects in this function.
bool isImmOperandLegal(const MachineInstr *MI, unsigned OpNo, const MachineOperand &MO) const
Operand with register or inline constant.
Definition: SIDefines.h:50
Generation getGeneration() const
unsigned getKillRegState(bool B)
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
unsigned getDefRegState(bool B)
bundle_iterator< MachineInstr, instr_iterator > iterator
MVT - Machine Value Type.
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:41
unsigned getNumVGPRsAllowed(unsigned WaveCount) const
Give the maximum number of VGPRs that can be used by WaveCount concurrent waves.
unsigned getMaxWavesPerCU() const
unsigned getPreloadedValue(const MachineFunction &MF, enum PreloadedValue Value) const
Returns the physical register that Value is stored in.
MCRegAliasIterator enumerates all registers aliasing Reg.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
unsigned findUnusedRegister(const MachineRegisterInfo &MRI, const TargetRegisterClass *RC) const
Returns a register that is not used at any point in the function.
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
const TargetRegisterClass * getEquivalentVGPRClass(const TargetRegisterClass *SRC) const
bool opCanUseLiteralConstant(unsigned OpType) const
MachineOperand class - Representation of each machine instruction operand.
SpilledReg getSpilledReg(MachineFunction *MF, unsigned FrameIndex, unsigned SubIdx)
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
unsigned getNumSGPRsAllowed(AMDGPUSubtarget::Generation gen, unsigned WaveCount) const
Give the maximum number of SGPRs that can be used by WaveCount concurrent waves.
const TargetRegisterClass * getSubRegClass(const TargetRegisterClass *RC, unsigned SubIdx) const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
const TargetRegisterClass * getPhysRegClass(unsigned Reg) const
Return the 'base' register class for this register.
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
Interface definition for SIInstrInfo.
#define I(x, y, z)
Definition: MD5.cpp:54
Operand with register or 32-bit immediate.
Definition: SIDefines.h:48
unsigned getReg() const
getReg - Returns the register number.
virtual const TargetInstrInfo * getInstrInfo() const
LLVM Value Representation.
Definition: Value.h:69
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const override
bool isPhysRegUsed(unsigned Reg) const
isPhysRegUsed - Return true if the specified register is used in this function.
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
void insertNOPs(MachineBasicBlock::iterator MI, int Count) const
unsigned scavengeRegister(const TargetRegisterClass *RegClass, MachineBasicBlock::iterator I, int SPAdj)
Make a register of the specific register class available and do the appropriate bookkeeping.