LLVM  3.7.0
MachineInstr.cpp
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1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Methods common to all machine instructions.
11 //
12 //===----------------------------------------------------------------------===//
13 
15 #include "llvm/ADT/FoldingSet.h"
16 #include "llvm/ADT/Hashing.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/IR/DebugInfo.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/IR/InlineAsm.h"
28 #include "llvm/IR/LLVMContext.h"
29 #include "llvm/IR/Metadata.h"
30 #include "llvm/IR/Module.h"
32 #include "llvm/IR/Type.h"
33 #include "llvm/IR/Value.h"
34 #include "llvm/MC/MCInstrDesc.h"
35 #include "llvm/MC/MCSymbol.h"
36 #include "llvm/Support/Debug.h"
44 using namespace llvm;
45 
46 //===----------------------------------------------------------------------===//
47 // MachineOperand Implementation
48 //===----------------------------------------------------------------------===//
49 
50 void MachineOperand::setReg(unsigned Reg) {
51  if (getReg() == Reg) return; // No change.
52 
53  // Otherwise, we have to change the register. If this operand is embedded
54  // into a machine function, we need to update the old and new register's
55  // use/def lists.
56  if (MachineInstr *MI = getParent())
57  if (MachineBasicBlock *MBB = MI->getParent())
58  if (MachineFunction *MF = MBB->getParent()) {
59  MachineRegisterInfo &MRI = MF->getRegInfo();
61  SmallContents.RegNo = Reg;
62  MRI.addRegOperandToUseList(this);
63  return;
64  }
65 
66  // Otherwise, just change the register, no problem. :)
67  SmallContents.RegNo = Reg;
68 }
69 
70 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
71  const TargetRegisterInfo &TRI) {
73  if (SubIdx && getSubReg())
74  SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
75  setReg(Reg);
76  if (SubIdx)
77  setSubReg(SubIdx);
78 }
79 
82  if (getSubReg()) {
83  Reg = TRI.getSubReg(Reg, getSubReg());
84  // Note that getSubReg() may return 0 if the sub-register doesn't exist.
85  // That won't happen in legal code.
86  setSubReg(0);
87  }
88  setReg(Reg);
89 }
90 
91 /// Change a def to a use, or a use to a def.
92 void MachineOperand::setIsDef(bool Val) {
93  assert(isReg() && "Wrong MachineOperand accessor");
94  assert((!Val || !isDebug()) && "Marking a debug operation as def");
95  if (IsDef == Val)
96  return;
97  // MRI may keep uses and defs in different list positions.
98  if (MachineInstr *MI = getParent())
99  if (MachineBasicBlock *MBB = MI->getParent())
100  if (MachineFunction *MF = MBB->getParent()) {
101  MachineRegisterInfo &MRI = MF->getRegInfo();
102  MRI.removeRegOperandFromUseList(this);
103  IsDef = Val;
104  MRI.addRegOperandToUseList(this);
105  return;
106  }
107  IsDef = Val;
108 }
109 
110 // If this operand is currently a register operand, and if this is in a
111 // function, deregister the operand from the register's use/def list.
112 void MachineOperand::removeRegFromUses() {
113  if (!isReg() || !isOnRegUseList())
114  return;
115 
116  if (MachineInstr *MI = getParent()) {
117  if (MachineBasicBlock *MBB = MI->getParent()) {
118  if (MachineFunction *MF = MBB->getParent())
119  MF->getRegInfo().removeRegOperandFromUseList(this);
120  }
121  }
122 }
123 
124 /// ChangeToImmediate - Replace this operand with a new immediate operand of
125 /// the specified value. If an operand is known to be an immediate already,
126 /// the setImm method should be used.
127 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
128  assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
129 
130  removeRegFromUses();
131 
132  OpKind = MO_Immediate;
133  Contents.ImmVal = ImmVal;
134 }
135 
137  assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
138 
139  removeRegFromUses();
140 
141  OpKind = MO_FPImmediate;
142  Contents.CFP = FPImm;
143 }
144 
145 void MachineOperand::ChangeToES(const char *SymName, unsigned char TargetFlags) {
146  assert((!isReg() || !isTied()) &&
147  "Cannot change a tied operand into an external symbol");
148 
149  removeRegFromUses();
150 
151  OpKind = MO_ExternalSymbol;
152  Contents.OffsetedInfo.Val.SymbolName = SymName;
153  setOffset(0); // Offset is always 0.
154  setTargetFlags(TargetFlags);
155 }
156 
158  assert((!isReg() || !isTied()) &&
159  "Cannot change a tied operand into an MCSymbol");
160 
161  removeRegFromUses();
162 
163  OpKind = MO_MCSymbol;
164  Contents.Sym = Sym;
165 }
166 
167 /// ChangeToRegister - Replace this operand with a new register operand of
168 /// the specified value. If an operand is known to be an register already,
169 /// the setReg method should be used.
170 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
171  bool isKill, bool isDead, bool isUndef,
172  bool isDebug) {
173  MachineRegisterInfo *RegInfo = nullptr;
174  if (MachineInstr *MI = getParent())
175  if (MachineBasicBlock *MBB = MI->getParent())
176  if (MachineFunction *MF = MBB->getParent())
177  RegInfo = &MF->getRegInfo();
178  // If this operand is already a register operand, remove it from the
179  // register's use/def lists.
180  bool WasReg = isReg();
181  if (RegInfo && WasReg)
182  RegInfo->removeRegOperandFromUseList(this);
183 
184  // Change this to a register and set the reg#.
185  OpKind = MO_Register;
186  SmallContents.RegNo = Reg;
187  SubReg_TargetFlags = 0;
188  IsDef = isDef;
189  IsImp = isImp;
190  IsKill = isKill;
191  IsDead = isDead;
192  IsUndef = isUndef;
193  IsInternalRead = false;
194  IsEarlyClobber = false;
195  IsDebug = isDebug;
196  // Ensure isOnRegUseList() returns false.
197  Contents.Reg.Prev = nullptr;
198  // Preserve the tie when the operand was already a register.
199  if (!WasReg)
200  TiedTo = 0;
201 
202  // If this operand is embedded in a function, add the operand to the
203  // register's use/def list.
204  if (RegInfo)
205  RegInfo->addRegOperandToUseList(this);
206 }
207 
208 /// isIdenticalTo - Return true if this operand is identical to the specified
209 /// operand. Note that this should stay in sync with the hash_value overload
210 /// below.
212  if (getType() != Other.getType() ||
213  getTargetFlags() != Other.getTargetFlags())
214  return false;
215 
216  switch (getType()) {
218  return getReg() == Other.getReg() && isDef() == Other.isDef() &&
219  getSubReg() == Other.getSubReg();
221  return getImm() == Other.getImm();
223  return getCImm() == Other.getCImm();
225  return getFPImm() == Other.getFPImm();
227  return getMBB() == Other.getMBB();
229  return getIndex() == Other.getIndex();
232  return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
234  return getIndex() == Other.getIndex();
236  return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
238  return !strcmp(getSymbolName(), Other.getSymbolName()) &&
239  getOffset() == Other.getOffset();
241  return getBlockAddress() == Other.getBlockAddress() &&
242  getOffset() == Other.getOffset();
245  return getRegMask() == Other.getRegMask();
247  return getMCSymbol() == Other.getMCSymbol();
249  return getCFIIndex() == Other.getCFIIndex();
251  return getMetadata() == Other.getMetadata();
252  }
253  llvm_unreachable("Invalid machine operand type");
254 }
255 
256 // Note: this must stay exactly in sync with isIdenticalTo above.
258  switch (MO.getType()) {
260  // Register operands don't have target flags.
261  return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef());
263  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
265  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
267  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
269  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
271  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
274  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
275  MO.getOffset());
277  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
279  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
280  MO.getSymbolName());
282  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
283  MO.getOffset());
285  return hash_combine(MO.getType(), MO.getTargetFlags(),
286  MO.getBlockAddress(), MO.getOffset());
289  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
291  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
293  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
295  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
296  }
297  llvm_unreachable("Invalid machine operand type");
298 }
299 
301  const TargetRegisterInfo *TRI) const {
302  ModuleSlotTracker DummyMST(nullptr);
303  print(OS, DummyMST, TRI);
304 }
305 
307  const TargetRegisterInfo *TRI) const {
308  switch (getType()) {
310  OS << PrintReg(getReg(), TRI, getSubReg());
311 
312  if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
313  isInternalRead() || isEarlyClobber() || isTied()) {
314  OS << '<';
315  bool NeedComma = false;
316  if (isDef()) {
317  if (NeedComma) OS << ',';
318  if (isEarlyClobber())
319  OS << "earlyclobber,";
320  if (isImplicit())
321  OS << "imp-";
322  OS << "def";
323  NeedComma = true;
324  // <def,read-undef> only makes sense when getSubReg() is set.
325  // Don't clutter the output otherwise.
326  if (isUndef() && getSubReg())
327  OS << ",read-undef";
328  } else if (isImplicit()) {
329  OS << "imp-use";
330  NeedComma = true;
331  }
332 
333  if (isKill()) {
334  if (NeedComma) OS << ',';
335  OS << "kill";
336  NeedComma = true;
337  }
338  if (isDead()) {
339  if (NeedComma) OS << ',';
340  OS << "dead";
341  NeedComma = true;
342  }
343  if (isUndef() && isUse()) {
344  if (NeedComma) OS << ',';
345  OS << "undef";
346  NeedComma = true;
347  }
348  if (isInternalRead()) {
349  if (NeedComma) OS << ',';
350  OS << "internal";
351  NeedComma = true;
352  }
353  if (isTied()) {
354  if (NeedComma) OS << ',';
355  OS << "tied";
356  if (TiedTo != 15)
357  OS << unsigned(TiedTo - 1);
358  }
359  OS << '>';
360  }
361  break;
362  case MachineOperand::MO_Immediate:
363  OS << getImm();
364  break;
365  case MachineOperand::MO_CImmediate:
366  getCImm()->getValue().print(OS, false);
367  break;
368  case MachineOperand::MO_FPImmediate:
369  if (getFPImm()->getType()->isFloatTy())
370  OS << getFPImm()->getValueAPF().convertToFloat();
371  else
372  OS << getFPImm()->getValueAPF().convertToDouble();
373  break;
374  case MachineOperand::MO_MachineBasicBlock:
375  OS << "<BB#" << getMBB()->getNumber() << ">";
376  break;
377  case MachineOperand::MO_FrameIndex:
378  OS << "<fi#" << getIndex() << '>';
379  break;
380  case MachineOperand::MO_ConstantPoolIndex:
381  OS << "<cp#" << getIndex();
382  if (getOffset()) OS << "+" << getOffset();
383  OS << '>';
384  break;
385  case MachineOperand::MO_TargetIndex:
386  OS << "<ti#" << getIndex();
387  if (getOffset()) OS << "+" << getOffset();
388  OS << '>';
389  break;
390  case MachineOperand::MO_JumpTableIndex:
391  OS << "<jt#" << getIndex() << '>';
392  break;
393  case MachineOperand::MO_GlobalAddress:
394  OS << "<ga:";
395  getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
396  if (getOffset()) OS << "+" << getOffset();
397  OS << '>';
398  break;
399  case MachineOperand::MO_ExternalSymbol:
400  OS << "<es:" << getSymbolName();
401  if (getOffset()) OS << "+" << getOffset();
402  OS << '>';
403  break;
404  case MachineOperand::MO_BlockAddress:
405  OS << '<';
406  getBlockAddress()->printAsOperand(OS, /*PrintType=*/false, MST);
407  if (getOffset()) OS << "+" << getOffset();
408  OS << '>';
409  break;
410  case MachineOperand::MO_RegisterMask:
411  OS << "<regmask>";
412  break;
413  case MachineOperand::MO_RegisterLiveOut:
414  OS << "<regliveout>";
415  break;
416  case MachineOperand::MO_Metadata:
417  OS << '<';
418  getMetadata()->printAsOperand(OS, MST);
419  OS << '>';
420  break;
421  case MachineOperand::MO_MCSymbol:
422  OS << "<MCSym=" << *getMCSymbol() << '>';
423  break;
424  case MachineOperand::MO_CFIIndex:
425  OS << "<call frame instruction>";
426  break;
427  }
428 
429  if (unsigned TF = getTargetFlags())
430  OS << "[TF=" << TF << ']';
431 }
432 
433 //===----------------------------------------------------------------------===//
434 // MachineMemOperand Implementation
435 //===----------------------------------------------------------------------===//
436 
437 /// getAddrSpace - Return the LLVM IR address space number that this pointer
438 /// points into.
439 unsigned MachinePointerInfo::getAddrSpace() const {
440  if (V.isNull() || V.is<const PseudoSourceValue*>()) return 0;
441  return cast<PointerType>(V.get<const Value*>()->getType())->getAddressSpace();
442 }
443 
444 /// getConstantPool - Return a MachinePointerInfo record that refers to the
445 /// constant pool.
446 MachinePointerInfo MachinePointerInfo::getConstantPool() {
447  return MachinePointerInfo(PseudoSourceValue::getConstantPool());
448 }
449 
450 /// getFixedStack - Return a MachinePointerInfo record that refers to the
451 /// the specified FrameIndex.
452 MachinePointerInfo MachinePointerInfo::getFixedStack(int FI, int64_t offset) {
453  return MachinePointerInfo(PseudoSourceValue::getFixedStack(FI), offset);
454 }
455 
456 MachinePointerInfo MachinePointerInfo::getJumpTable() {
457  return MachinePointerInfo(PseudoSourceValue::getJumpTable());
458 }
459 
460 MachinePointerInfo MachinePointerInfo::getGOT() {
461  return MachinePointerInfo(PseudoSourceValue::getGOT());
462 }
463 
464 MachinePointerInfo MachinePointerInfo::getStack(int64_t Offset) {
465  return MachinePointerInfo(PseudoSourceValue::getStack(), Offset);
466 }
467 
468 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f,
469  uint64_t s, unsigned int a,
470  const AAMDNodes &AAInfo,
471  const MDNode *Ranges)
472  : PtrInfo(ptrinfo), Size(s),
473  Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)),
474  AAInfo(AAInfo), Ranges(Ranges) {
475  assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue*>() ||
476  isa<PointerType>(PtrInfo.V.get<const Value*>()->getType())) &&
477  "invalid pointer value");
478  assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
479  assert((isLoad() || isStore()) && "Not a load/store!");
480 }
481 
482 /// Profile - Gather unique data for the object.
483 ///
484 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
485  ID.AddInteger(getOffset());
486  ID.AddInteger(Size);
487  ID.AddPointer(getOpaqueValue());
488  ID.AddInteger(Flags);
489 }
490 
491 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
492  // The Value and Offset may differ due to CSE. But the flags and size
493  // should be the same.
494  assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
495  assert(MMO->getSize() == getSize() && "Size mismatch!");
496 
497  if (MMO->getBaseAlignment() >= getBaseAlignment()) {
498  // Update the alignment value.
499  Flags = (Flags & ((1 << MOMaxBits) - 1)) |
500  ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits);
501  // Also update the base and offset, because the new alignment may
502  // not be applicable with the old ones.
503  PtrInfo = MMO->PtrInfo;
504  }
505 }
506 
507 /// getAlignment - Return the minimum known alignment in bytes of the
508 /// actual memory reference.
509 uint64_t MachineMemOperand::getAlignment() const {
510  return MinAlign(getBaseAlignment(), getOffset());
511 }
512 
513 void MachineMemOperand::print(raw_ostream &OS) const {
514  ModuleSlotTracker DummyMST(nullptr);
515  print(OS, DummyMST);
516 }
517 void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST) const {
518  assert((isLoad() || isStore()) &&
519  "SV has to be a load, store or both.");
520 
521  if (isVolatile())
522  OS << "Volatile ";
523 
524  if (isLoad())
525  OS << "LD";
526  if (isStore())
527  OS << "ST";
528  OS << getSize();
529 
530  // Print the address information.
531  OS << "[";
532  if (const Value *V = getValue())
533  V->printAsOperand(OS, /*PrintType=*/false, MST);
534  else if (const PseudoSourceValue *PSV = getPseudoValue())
535  PSV->printCustom(OS);
536  else
537  OS << "<unknown>";
538 
539  unsigned AS = getAddrSpace();
540  if (AS != 0)
541  OS << "(addrspace=" << AS << ')';
542 
543  // If the alignment of the memory reference itself differs from the alignment
544  // of the base pointer, print the base alignment explicitly, next to the base
545  // pointer.
546  if (getBaseAlignment() != getAlignment())
547  OS << "(align=" << getBaseAlignment() << ")";
548 
549  if (getOffset() != 0)
550  OS << "+" << getOffset();
551  OS << "]";
552 
553  // Print the alignment of the reference.
554  if (getBaseAlignment() != getAlignment() || getBaseAlignment() != getSize())
555  OS << "(align=" << getAlignment() << ")";
556 
557  // Print TBAA info.
558  if (const MDNode *TBAAInfo = getAAInfo().TBAA) {
559  OS << "(tbaa=";
560  if (TBAAInfo->getNumOperands() > 0)
561  TBAAInfo->getOperand(0)->printAsOperand(OS, MST);
562  else
563  OS << "<unknown>";
564  OS << ")";
565  }
566 
567  // Print AA scope info.
568  if (const MDNode *ScopeInfo = getAAInfo().Scope) {
569  OS << "(alias.scope=";
570  if (ScopeInfo->getNumOperands() > 0)
571  for (unsigned i = 0, ie = ScopeInfo->getNumOperands(); i != ie; ++i) {
572  ScopeInfo->getOperand(i)->printAsOperand(OS, MST);
573  if (i != ie-1)
574  OS << ",";
575  }
576  else
577  OS << "<unknown>";
578  OS << ")";
579  }
580 
581  // Print AA noalias scope info.
582  if (const MDNode *NoAliasInfo = getAAInfo().NoAlias) {
583  OS << "(noalias=";
584  if (NoAliasInfo->getNumOperands() > 0)
585  for (unsigned i = 0, ie = NoAliasInfo->getNumOperands(); i != ie; ++i) {
586  NoAliasInfo->getOperand(i)->printAsOperand(OS, MST);
587  if (i != ie-1)
588  OS << ",";
589  }
590  else
591  OS << "<unknown>";
592  OS << ")";
593  }
594 
595  // Print nontemporal info.
596  if (isNonTemporal())
597  OS << "(nontemporal)";
598 
599  if (isInvariant())
600  OS << "(invariant)";
601 }
602 
603 //===----------------------------------------------------------------------===//
604 // MachineInstr Implementation
605 //===----------------------------------------------------------------------===//
606 
607 void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) {
608  if (MCID->ImplicitDefs)
609  for (const uint16_t *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
610  addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
611  if (MCID->ImplicitUses)
612  for (const uint16_t *ImpUses = MCID->getImplicitUses(); *ImpUses; ++ImpUses)
613  addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
614 }
615 
616 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
617 /// implicit operands. It reserves space for the number of operands specified by
618 /// the MCInstrDesc.
619 MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid,
620  DebugLoc dl, bool NoImp)
621  : MCID(&tid), Parent(nullptr), Operands(nullptr), NumOperands(0), Flags(0),
622  AsmPrinterFlags(0), NumMemRefs(0), MemRefs(nullptr),
623  debugLoc(std::move(dl)) {
624  assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
625 
626  // Reserve space for the expected number of operands.
627  if (unsigned NumOps = MCID->getNumOperands() +
628  MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
629  CapOperands = OperandCapacity::get(NumOps);
630  Operands = MF.allocateOperandArray(CapOperands);
631  }
632 
633  if (!NoImp)
634  addImplicitDefUseOperands(MF);
635 }
636 
637 /// MachineInstr ctor - Copies MachineInstr arg exactly
638 ///
639 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
640  : MCID(&MI.getDesc()), Parent(nullptr), Operands(nullptr), NumOperands(0),
641  Flags(0), AsmPrinterFlags(0),
642  NumMemRefs(MI.NumMemRefs), MemRefs(MI.MemRefs),
643  debugLoc(MI.getDebugLoc()) {
644  assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
645 
646  CapOperands = OperandCapacity::get(MI.getNumOperands());
647  Operands = MF.allocateOperandArray(CapOperands);
648 
649  // Copy operands.
650  for (const MachineOperand &MO : MI.operands())
651  addOperand(MF, MO);
652 
653  // Copy all the sensible flags.
654  setFlags(MI.Flags);
655 }
656 
657 /// getRegInfo - If this instruction is embedded into a MachineFunction,
658 /// return the MachineRegisterInfo object for the current function, otherwise
659 /// return null.
660 MachineRegisterInfo *MachineInstr::getRegInfo() {
661  if (MachineBasicBlock *MBB = getParent())
662  return &MBB->getParent()->getRegInfo();
663  return nullptr;
664 }
665 
666 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
667 /// this instruction from their respective use lists. This requires that the
668 /// operands already be on their use lists.
669 void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
670  for (MachineOperand &MO : operands())
671  if (MO.isReg())
672  MRI.removeRegOperandFromUseList(&MO);
673 }
674 
675 /// AddRegOperandsToUseLists - Add all of the register operands in
676 /// this instruction from their respective use lists. This requires that the
677 /// operands not be on their use lists yet.
678 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
679  for (MachineOperand &MO : operands())
680  if (MO.isReg())
681  MRI.addRegOperandToUseList(&MO);
682 }
683 
684 void MachineInstr::addOperand(const MachineOperand &Op) {
685  MachineBasicBlock *MBB = getParent();
686  assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs");
687  MachineFunction *MF = MBB->getParent();
688  assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs");
689  addOperand(*MF, Op);
690 }
691 
692 /// Move NumOps MachineOperands from Src to Dst, with support for overlapping
693 /// ranges. If MRI is non-null also update use-def chains.
694 static void moveOperands(MachineOperand *Dst, MachineOperand *Src,
695  unsigned NumOps, MachineRegisterInfo *MRI) {
696  if (MRI)
697  return MRI->moveOperands(Dst, Src, NumOps);
698 
699  // MachineOperand is a trivially copyable type so we can just use memmove.
700  std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));
701 }
702 
703 /// addOperand - Add the specified operand to the instruction. If it is an
704 /// implicit operand, it is added to the end of the operand list. If it is
705 /// an explicit operand it is added at the end of the explicit operand list
706 /// (before the first implicit operand).
707 void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) {
708  assert(MCID && "Cannot add operands before providing an instr descriptor");
709 
710  // Check if we're adding one of our existing operands.
711  if (&Op >= Operands && &Op < Operands + NumOperands) {
712  // This is unusual: MI->addOperand(MI->getOperand(i)).
713  // If adding Op requires reallocating or moving existing operands around,
714  // the Op reference could go stale. Support it by copying Op.
715  MachineOperand CopyOp(Op);
716  return addOperand(MF, CopyOp);
717  }
718 
719  // Find the insert location for the new operand. Implicit registers go at
720  // the end, everything else goes before the implicit regs.
721  //
722  // FIXME: Allow mixed explicit and implicit operands on inline asm.
723  // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
724  // implicit-defs, but they must not be moved around. See the FIXME in
725  // InstrEmitter.cpp.
726  unsigned OpNo = getNumOperands();
727  bool isImpReg = Op.isReg() && Op.isImplicit();
728  if (!isImpReg && !isInlineAsm()) {
729  while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
730  --OpNo;
731  assert(!Operands[OpNo].isTied() && "Cannot move tied operands");
732  }
733  }
734 
735 #ifndef NDEBUG
736  bool isMetaDataOp = Op.getType() == MachineOperand::MO_Metadata;
737  // OpNo now points as the desired insertion point. Unless this is a variadic
738  // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
739  // RegMask operands go between the explicit and implicit operands.
740  assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||
741  OpNo < MCID->getNumOperands() || isMetaDataOp) &&
742  "Trying to add an operand to a machine instr that is already done!");
743 #endif
744 
745  MachineRegisterInfo *MRI = getRegInfo();
746 
747  // Determine if the Operands array needs to be reallocated.
748  // Save the old capacity and operand array.
749  OperandCapacity OldCap = CapOperands;
750  MachineOperand *OldOperands = Operands;
751  if (!OldOperands || OldCap.getSize() == getNumOperands()) {
752  CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
753  Operands = MF.allocateOperandArray(CapOperands);
754  // Move the operands before the insertion point.
755  if (OpNo)
756  moveOperands(Operands, OldOperands, OpNo, MRI);
757  }
758 
759  // Move the operands following the insertion point.
760  if (OpNo != NumOperands)
761  moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
762  MRI);
763  ++NumOperands;
764 
765  // Deallocate the old operand array.
766  if (OldOperands != Operands && OldOperands)
767  MF.deallocateOperandArray(OldCap, OldOperands);
768 
769  // Copy Op into place. It still needs to be inserted into the MRI use lists.
770  MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
771  NewMO->ParentMI = this;
772 
773  // When adding a register operand, tell MRI about it.
774  if (NewMO->isReg()) {
775  // Ensure isOnRegUseList() returns false, regardless of Op's status.
776  NewMO->Contents.Reg.Prev = nullptr;
777  // Ignore existing ties. This is not a property that can be copied.
778  NewMO->TiedTo = 0;
779  // Add the new operand to MRI, but only for instructions in an MBB.
780  if (MRI)
781  MRI->addRegOperandToUseList(NewMO);
782  // The MCID operand information isn't accurate until we start adding
783  // explicit operands. The implicit operands are added first, then the
784  // explicits are inserted before them.
785  if (!isImpReg) {
786  // Tie uses to defs as indicated in MCInstrDesc.
787  if (NewMO->isUse()) {
788  int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
789  if (DefIdx != -1)
790  tieOperands(DefIdx, OpNo);
791  }
792  // If the register operand is flagged as early, mark the operand as such.
793  if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
794  NewMO->setIsEarlyClobber(true);
795  }
796  }
797 }
798 
799 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
800 /// fewer operand than it started with.
801 ///
802 void MachineInstr::RemoveOperand(unsigned OpNo) {
803  assert(OpNo < getNumOperands() && "Invalid operand number");
804  untieRegOperand(OpNo);
805 
806 #ifndef NDEBUG
807  // Moving tied operands would break the ties.
808  for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
809  if (Operands[i].isReg())
810  assert(!Operands[i].isTied() && "Cannot move tied operands");
811 #endif
812 
813  MachineRegisterInfo *MRI = getRegInfo();
814  if (MRI && Operands[OpNo].isReg())
816 
817  // Don't call the MachineOperand destructor. A lot of this code depends on
818  // MachineOperand having a trivial destructor anyway, and adding a call here
819  // wouldn't make it 'destructor-correct'.
820 
821  if (unsigned N = NumOperands - 1 - OpNo)
822  moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI);
823  --NumOperands;
824 }
825 
826 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
827 /// This function should be used only occasionally. The setMemRefs function
828 /// is the primary method for setting up a MachineInstr's MemRefs list.
830  MachineMemOperand *MO) {
831  mmo_iterator OldMemRefs = MemRefs;
832  unsigned OldNumMemRefs = NumMemRefs;
833 
834  unsigned NewNum = NumMemRefs + 1;
835  mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
836 
837  std::copy(OldMemRefs, OldMemRefs + OldNumMemRefs, NewMemRefs);
838  NewMemRefs[NewNum - 1] = MO;
839  setMemRefs(NewMemRefs, NewMemRefs + NewNum);
840 }
841 
842 bool MachineInstr::hasPropertyInBundle(unsigned Mask, QueryType Type) const {
843  assert(!isBundledWithPred() && "Must be called on bundle header");
844  for (MachineBasicBlock::const_instr_iterator MII = this;; ++MII) {
845  if (MII->getDesc().getFlags() & Mask) {
846  if (Type == AnyInBundle)
847  return true;
848  } else {
849  if (Type == AllInBundle && !MII->isBundle())
850  return false;
851  }
852  // This was the last instruction in the bundle.
853  if (!MII->isBundledWithSucc())
854  return Type == AllInBundle;
855  }
856 }
857 
859  MICheckType Check) const {
860  // If opcodes or number of operands are not the same then the two
861  // instructions are obviously not identical.
862  if (Other->getOpcode() != getOpcode() ||
863  Other->getNumOperands() != getNumOperands())
864  return false;
865 
866  if (isBundle()) {
867  // Both instructions are bundles, compare MIs inside the bundle.
872  while (++I1 != E1 && I1->isInsideBundle()) {
873  ++I2;
874  if (I2 == E2 || !I2->isInsideBundle() || !I1->isIdenticalTo(I2, Check))
875  return false;
876  }
877  }
878 
879  // Check operands to make sure they match.
880  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
881  const MachineOperand &MO = getOperand(i);
882  const MachineOperand &OMO = Other->getOperand(i);
883  if (!MO.isReg()) {
884  if (!MO.isIdenticalTo(OMO))
885  return false;
886  continue;
887  }
888 
889  // Clients may or may not want to ignore defs when testing for equality.
890  // For example, machine CSE pass only cares about finding common
891  // subexpressions, so it's safe to ignore virtual register defs.
892  if (MO.isDef()) {
893  if (Check == IgnoreDefs)
894  continue;
895  else if (Check == IgnoreVRegDefs) {
898  if (MO.getReg() != OMO.getReg())
899  return false;
900  } else {
901  if (!MO.isIdenticalTo(OMO))
902  return false;
903  if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
904  return false;
905  }
906  } else {
907  if (!MO.isIdenticalTo(OMO))
908  return false;
909  if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
910  return false;
911  }
912  }
913  // If DebugLoc does not match then two dbg.values are not identical.
914  if (isDebugValue())
915  if (getDebugLoc() && Other->getDebugLoc() &&
916  getDebugLoc() != Other->getDebugLoc())
917  return false;
918  return true;
919 }
920 
922  assert(getParent() && "Not embedded in a basic block!");
923  return getParent()->remove(this);
924 }
925 
927  assert(getParent() && "Not embedded in a basic block!");
928  return getParent()->remove_instr(this);
929 }
930 
932  assert(getParent() && "Not embedded in a basic block!");
933  getParent()->erase(this);
934 }
935 
937  assert(getParent() && "Not embedded in a basic block!");
939  MachineFunction *MF = MBB->getParent();
940  assert(MF && "Not embedded in a function!");
941 
942  MachineInstr *MI = (MachineInstr *)this;
943  MachineRegisterInfo &MRI = MF->getRegInfo();
944 
945  for (const MachineOperand &MO : MI->operands()) {
946  if (!MO.isReg() || !MO.isDef())
947  continue;
948  unsigned Reg = MO.getReg();
950  continue;
952  }
953  MI->eraseFromParent();
954 }
955 
957  assert(getParent() && "Not embedded in a basic block!");
958  getParent()->erase_instr(this);
959 }
960 
961 /// getNumExplicitOperands - Returns the number of non-implicit operands.
962 ///
964  unsigned NumOperands = MCID->getNumOperands();
965  if (!MCID->isVariadic())
966  return NumOperands;
967 
968  for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
969  const MachineOperand &MO = getOperand(i);
970  if (!MO.isReg() || !MO.isImplicit())
971  NumOperands++;
972  }
973  return NumOperands;
974 }
975 
977  assert(!isBundledWithPred() && "MI is already bundled with its predecessor");
978  setFlag(BundledPred);
980  --Pred;
981  assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags");
982  Pred->setFlag(BundledSucc);
983 }
984 
986  assert(!isBundledWithSucc() && "MI is already bundled with its successor");
987  setFlag(BundledSucc);
989  ++Succ;
990  assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags");
991  Succ->setFlag(BundledPred);
992 }
993 
995  assert(isBundledWithPred() && "MI isn't bundled with its predecessor");
996  clearFlag(BundledPred);
998  --Pred;
999  assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags");
1000  Pred->clearFlag(BundledSucc);
1001 }
1002 
1004  assert(isBundledWithSucc() && "MI isn't bundled with its successor");
1005  clearFlag(BundledSucc);
1007  ++Succ;
1008  assert(Succ->isBundledWithPred() && "Inconsistent bundle flags");
1009  Succ->clearFlag(BundledPred);
1010 }
1011 
1013  if (isInlineAsm()) {
1014  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1015  if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1016  return true;
1017  }
1018  return false;
1019 }
1020 
1022  assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!");
1023  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1024  return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
1025 }
1026 
1028  unsigned *GroupNo) const {
1029  assert(isInlineAsm() && "Expected an inline asm instruction");
1030  assert(OpIdx < getNumOperands() && "OpIdx out of range");
1031 
1032  // Ignore queries about the initial operands.
1033  if (OpIdx < InlineAsm::MIOp_FirstOperand)
1034  return -1;
1035 
1036  unsigned Group = 0;
1037  unsigned NumOps;
1038  for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1039  i += NumOps) {
1040  const MachineOperand &FlagMO = getOperand(i);
1041  // If we reach the implicit register operands, stop looking.
1042  if (!FlagMO.isImm())
1043  return -1;
1044  NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
1045  if (i + NumOps > OpIdx) {
1046  if (GroupNo)
1047  *GroupNo = Group;
1048  return i;
1049  }
1050  ++Group;
1051  }
1052  return -1;
1053 }
1054 
1055 const TargetRegisterClass*
1057  const TargetInstrInfo *TII,
1058  const TargetRegisterInfo *TRI) const {
1059  assert(getParent() && "Can't have an MBB reference here!");
1060  assert(getParent()->getParent() && "Can't have an MF reference here!");
1061  const MachineFunction &MF = *getParent()->getParent();
1062 
1063  // Most opcodes have fixed constraints in their MCInstrDesc.
1064  if (!isInlineAsm())
1065  return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
1066 
1067  if (!getOperand(OpIdx).isReg())
1068  return nullptr;
1069 
1070  // For tied uses on inline asm, get the constraint from the def.
1071  unsigned DefIdx;
1072  if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
1073  OpIdx = DefIdx;
1074 
1075  // Inline asm stores register class constraints in the flag word.
1076  int FlagIdx = findInlineAsmFlagIdx(OpIdx);
1077  if (FlagIdx < 0)
1078  return nullptr;
1079 
1080  unsigned Flag = getOperand(FlagIdx).getImm();
1081  unsigned RCID;
1082  if (InlineAsm::hasRegClassConstraint(Flag, RCID))
1083  return TRI->getRegClass(RCID);
1084 
1085  // Assume that all registers in a memory operand are pointers.
1087  return TRI->getPointerRegClass(MF);
1088 
1089  return nullptr;
1090 }
1091 
1093  unsigned Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
1094  const TargetRegisterInfo *TRI, bool ExploreBundle) const {
1095  // Check every operands inside the bundle if we have
1096  // been asked to.
1097  if (ExploreBundle)
1098  for (ConstMIBundleOperands OpndIt(this); OpndIt.isValid() && CurRC;
1099  ++OpndIt)
1100  CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
1101  OpndIt.getOperandNo(), Reg, CurRC, TII, TRI);
1102  else
1103  // Otherwise, just check the current operands.
1104  for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)
1105  CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI);
1106  return CurRC;
1107 }
1108 
1109 const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl(
1110  unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC,
1111  const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
1112  assert(CurRC && "Invalid initial register class");
1113  // Check if Reg is constrained by some of its use/def from MI.
1114  const MachineOperand &MO = getOperand(OpIdx);
1115  if (!MO.isReg() || MO.getReg() != Reg)
1116  return CurRC;
1117  // If yes, accumulate the constraints through the operand.
1118  return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);
1119 }
1120 
1122  unsigned OpIdx, const TargetRegisterClass *CurRC,
1123  const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
1124  const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);
1125  const MachineOperand &MO = getOperand(OpIdx);
1126  assert(MO.isReg() &&
1127  "Cannot get register constraints for non-register operand");
1128  assert(CurRC && "Invalid initial register class");
1129  if (unsigned SubIdx = MO.getSubReg()) {
1130  if (OpRC)
1131  CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);
1132  else
1133  CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx);
1134  } else if (OpRC)
1135  CurRC = TRI->getCommonSubClass(CurRC, OpRC);
1136  return CurRC;
1137 }
1138 
1139 /// Return the number of instructions inside the MI bundle, not counting the
1140 /// header instruction.
1143  unsigned Size = 0;
1144  while (I->isBundledWithSucc())
1145  ++Size, ++I;
1146  return Size;
1147 }
1148 
1149 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
1150 /// the specific register or -1 if it is not found. It further tightens
1151 /// the search criteria to a use that kills the register if isKill is true.
1153  const TargetRegisterInfo *TRI) const {
1154  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1155  const MachineOperand &MO = getOperand(i);
1156  if (!MO.isReg() || !MO.isUse())
1157  continue;
1158  unsigned MOReg = MO.getReg();
1159  if (!MOReg)
1160  continue;
1161  if (MOReg == Reg ||
1162  (TRI &&
1165  TRI->isSubRegister(MOReg, Reg)))
1166  if (!isKill || MO.isKill())
1167  return i;
1168  }
1169  return -1;
1170 }
1171 
1172 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
1173 /// indicating if this instruction reads or writes Reg. This also considers
1174 /// partial defines.
1175 std::pair<bool,bool>
1177  SmallVectorImpl<unsigned> *Ops) const {
1178  bool PartDef = false; // Partial redefine.
1179  bool FullDef = false; // Full define.
1180  bool Use = false;
1181 
1182  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1183  const MachineOperand &MO = getOperand(i);
1184  if (!MO.isReg() || MO.getReg() != Reg)
1185  continue;
1186  if (Ops)
1187  Ops->push_back(i);
1188  if (MO.isUse())
1189  Use |= !MO.isUndef();
1190  else if (MO.getSubReg() && !MO.isUndef())
1191  // A partial <def,undef> doesn't count as reading the register.
1192  PartDef = true;
1193  else
1194  FullDef = true;
1195  }
1196  // A partial redefine uses Reg unless there is also a full define.
1197  return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
1198 }
1199 
1200 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
1201 /// the specified register or -1 if it is not found. If isDead is true, defs
1202 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
1203 /// also checks if there is a def of a super-register.
1204 int
1205 MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
1206  const TargetRegisterInfo *TRI) const {
1207  bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
1208  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1209  const MachineOperand &MO = getOperand(i);
1210  // Accept regmask operands when Overlap is set.
1211  // Ignore them when looking for a specific def operand (Overlap == false).
1212  if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
1213  return i;
1214  if (!MO.isReg() || !MO.isDef())
1215  continue;
1216  unsigned MOReg = MO.getReg();
1217  bool Found = (MOReg == Reg);
1218  if (!Found && TRI && isPhys &&
1220  if (Overlap)
1221  Found = TRI->regsOverlap(MOReg, Reg);
1222  else
1223  Found = TRI->isSubRegister(MOReg, Reg);
1224  }
1225  if (Found && (!isDead || MO.isDead()))
1226  return i;
1227  }
1228  return -1;
1229 }
1230 
1231 /// findFirstPredOperandIdx() - Find the index of the first operand in the
1232 /// operand list that is used to represent the predicate. It returns -1 if
1233 /// none is found.
1235  // Don't call MCID.findFirstPredOperandIdx() because this variant
1236  // is sometimes called on an instruction that's not yet complete, and
1237  // so the number of operands is less than the MCID indicates. In
1238  // particular, the PTX target does this.
1239  const MCInstrDesc &MCID = getDesc();
1240  if (MCID.isPredicable()) {
1241  for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1242  if (MCID.OpInfo[i].isPredicate())
1243  return i;
1244  }
1245 
1246  return -1;
1247 }
1248 
1249 // MachineOperand::TiedTo is 4 bits wide.
1250 const unsigned TiedMax = 15;
1251 
1252 /// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1253 ///
1254 /// Use and def operands can be tied together, indicated by a non-zero TiedTo
1255 /// field. TiedTo can have these values:
1256 ///
1257 /// 0: Operand is not tied to anything.
1258 /// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
1259 /// TiedMax: Tied to an operand >= TiedMax-1.
1260 ///
1261 /// The tied def must be one of the first TiedMax operands on a normal
1262 /// instruction. INLINEASM instructions allow more tied defs.
1263 ///
1264 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1265  MachineOperand &DefMO = getOperand(DefIdx);
1266  MachineOperand &UseMO = getOperand(UseIdx);
1267  assert(DefMO.isDef() && "DefIdx must be a def operand");
1268  assert(UseMO.isUse() && "UseIdx must be a use operand");
1269  assert(!DefMO.isTied() && "Def is already tied to another use");
1270  assert(!UseMO.isTied() && "Use is already tied to another def");
1271 
1272  if (DefIdx < TiedMax)
1273  UseMO.TiedTo = DefIdx + 1;
1274  else {
1275  // Inline asm can use the group descriptors to find tied operands, but on
1276  // normal instruction, the tied def must be within the first TiedMax
1277  // operands.
1278  assert(isInlineAsm() && "DefIdx out of range");
1279  UseMO.TiedTo = TiedMax;
1280  }
1281 
1282  // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1283  DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
1284 }
1285 
1286 /// Given the index of a tied register operand, find the operand it is tied to.
1287 /// Defs are tied to uses and vice versa. Returns the index of the tied operand
1288 /// which must exist.
1289 unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
1290  const MachineOperand &MO = getOperand(OpIdx);
1291  assert(MO.isTied() && "Operand isn't tied");
1292 
1293  // Normally TiedTo is in range.
1294  if (MO.TiedTo < TiedMax)
1295  return MO.TiedTo - 1;
1296 
1297  // Uses on normal instructions can be out of range.
1298  if (!isInlineAsm()) {
1299  // Normal tied defs must be in the 0..TiedMax-1 range.
1300  if (MO.isUse())
1301  return TiedMax - 1;
1302  // MO is a def. Search for the tied use.
1303  for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
1304  const MachineOperand &UseMO = getOperand(i);
1305  if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1306  return i;
1307  }
1308  llvm_unreachable("Can't find tied use");
1309  }
1310 
1311  // Now deal with inline asm by parsing the operand group descriptor flags.
1312  // Find the beginning of each operand group.
1313  SmallVector<unsigned, 8> GroupIdx;
1314  unsigned OpIdxGroup = ~0u;
1315  unsigned NumOps;
1316  for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1317  i += NumOps) {
1318  const MachineOperand &FlagMO = getOperand(i);
1319  assert(FlagMO.isImm() && "Invalid tied operand on inline asm");
1320  unsigned CurGroup = GroupIdx.size();
1321  GroupIdx.push_back(i);
1322  NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
1323  // OpIdx belongs to this operand group.
1324  if (OpIdx > i && OpIdx < i + NumOps)
1325  OpIdxGroup = CurGroup;
1326  unsigned TiedGroup;
1327  if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup))
1328  continue;
1329  // Operands in this group are tied to operands in TiedGroup which must be
1330  // earlier. Find the number of operands between the two groups.
1331  unsigned Delta = i - GroupIdx[TiedGroup];
1332 
1333  // OpIdx is a use tied to TiedGroup.
1334  if (OpIdxGroup == CurGroup)
1335  return OpIdx - Delta;
1336 
1337  // OpIdx is a def tied to this use group.
1338  if (OpIdxGroup == TiedGroup)
1339  return OpIdx + Delta;
1340  }
1341  llvm_unreachable("Invalid tied operand on inline asm");
1342 }
1343 
1344 /// clearKillInfo - Clears kill flags on all operands.
1345 ///
1347  for (MachineOperand &MO : operands()) {
1348  if (MO.isReg() && MO.isUse())
1349  MO.setIsKill(false);
1350  }
1351 }
1352 
1353 void MachineInstr::substituteRegister(unsigned FromReg,
1354  unsigned ToReg,
1355  unsigned SubIdx,
1356  const TargetRegisterInfo &RegInfo) {
1358  if (SubIdx)
1359  ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1360  for (MachineOperand &MO : operands()) {
1361  if (!MO.isReg() || MO.getReg() != FromReg)
1362  continue;
1363  MO.substPhysReg(ToReg, RegInfo);
1364  }
1365  } else {
1366  for (MachineOperand &MO : operands()) {
1367  if (!MO.isReg() || MO.getReg() != FromReg)
1368  continue;
1369  MO.substVirtReg(ToReg, SubIdx, RegInfo);
1370  }
1371  }
1372 }
1373 
1374 /// isSafeToMove - Return true if it is safe to move this instruction. If
1375 /// SawStore is set to true, it means that there is a store (or call) between
1376 /// the instruction's location and its intended destination.
1378  // Ignore stuff that we obviously can't move.
1379  //
1380  // Treat volatile loads as stores. This is not strictly necessary for
1381  // volatiles, but it is required for atomic loads. It is not allowed to move
1382  // a load across an atomic load with Ordering > Monotonic.
1383  if (mayStore() || isCall() ||
1384  (mayLoad() && hasOrderedMemoryRef())) {
1385  SawStore = true;
1386  return false;
1387  }
1388 
1389  if (isPosition() || isDebugValue() || isTerminator() ||
1390  hasUnmodeledSideEffects())
1391  return false;
1392 
1393  // See if this instruction does a load. If so, we have to guarantee that the
1394  // loaded value doesn't change between the load and the its intended
1395  // destination. The check for isInvariantLoad gives the targe the chance to
1396  // classify the load as always returning a constant, e.g. a constant pool
1397  // load.
1398  if (mayLoad() && !isInvariantLoad(AA))
1399  // Otherwise, this is a real load. If there is a store between the load and
1400  // end of block, we can't move it.
1401  return !SawStore;
1402 
1403  return true;
1404 }
1405 
1406 /// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1407 /// or volatile memory reference, or if the information describing the memory
1408 /// reference is not available. Return false if it is known to have no ordered
1409 /// memory references.
1411  // An instruction known never to access memory won't have a volatile access.
1412  if (!mayStore() &&
1413  !mayLoad() &&
1414  !isCall() &&
1415  !hasUnmodeledSideEffects())
1416  return false;
1417 
1418  // Otherwise, if the instruction has no memory reference information,
1419  // conservatively assume it wasn't preserved.
1420  if (memoperands_empty())
1421  return true;
1422 
1423  // Check the memory reference information for ordered references.
1424  for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
1425  if (!(*I)->isUnordered())
1426  return true;
1427 
1428  return false;
1429 }
1430 
1431 /// isInvariantLoad - Return true if this instruction is loading from a
1432 /// location whose value is invariant across the function. For example,
1433 /// loading a value from the constant pool or from the argument area
1434 /// of a function if it does not change. This should only return true of
1435 /// *all* loads the instruction does are invariant (if it does multiple loads).
1437  // If the instruction doesn't load at all, it isn't an invariant load.
1438  if (!mayLoad())
1439  return false;
1440 
1441  // If the instruction has lost its memoperands, conservatively assume that
1442  // it may not be an invariant load.
1443  if (memoperands_empty())
1444  return false;
1445 
1446  const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo();
1447 
1448  for (mmo_iterator I = memoperands_begin(),
1449  E = memoperands_end(); I != E; ++I) {
1450  if ((*I)->isVolatile()) return false;
1451  if ((*I)->isStore()) return false;
1452  if ((*I)->isInvariant()) return true;
1453 
1454 
1455  // A load from a constant PseudoSourceValue is invariant.
1456  if (const PseudoSourceValue *PSV = (*I)->getPseudoValue())
1457  if (PSV->isConstant(MFI))
1458  continue;
1459 
1460  if (const Value *V = (*I)->getValue()) {
1461  // If we have an AliasAnalysis, ask it whether the memory is constant.
1462  if (AA &&
1464  MemoryLocation(V, (*I)->getSize(), (*I)->getAAInfo())))
1465  continue;
1466  }
1467 
1468  // Otherwise assume conservatively.
1469  return false;
1470  }
1471 
1472  // Everything checks out.
1473  return true;
1474 }
1475 
1476 /// isConstantValuePHI - If the specified instruction is a PHI that always
1477 /// merges together the same virtual register, return the register, otherwise
1478 /// return 0.
1480  if (!isPHI())
1481  return 0;
1482  assert(getNumOperands() >= 3 &&
1483  "It's illegal to have a PHI without source operands");
1484 
1485  unsigned Reg = getOperand(1).getReg();
1486  for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1487  if (getOperand(i).getReg() != Reg)
1488  return 0;
1489  return Reg;
1490 }
1491 
1493  if (hasProperty(MCID::UnmodeledSideEffects))
1494  return true;
1495  if (isInlineAsm()) {
1496  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1497  if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1498  return true;
1499  }
1500 
1501  return false;
1502 }
1503 
1504 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
1505 ///
1507  for (const MachineOperand &MO : operands()) {
1508  if (!MO.isReg() || MO.isUse())
1509  continue;
1510  if (!MO.isDead())
1511  return false;
1512  }
1513  return true;
1514 }
1515 
1516 /// copyImplicitOps - Copy implicit register operands from specified
1517 /// instruction to this instruction.
1519  const MachineInstr *MI) {
1520  for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
1521  i != e; ++i) {
1522  const MachineOperand &MO = MI->getOperand(i);
1523  if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
1524  addOperand(MF, MO);
1525  }
1526 }
1527 
1528 void MachineInstr::dump() const {
1529 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1530  dbgs() << " " << *this;
1531 #endif
1532 }
1533 
1534 void MachineInstr::print(raw_ostream &OS, bool SkipOpers) const {
1535  const Module *M = nullptr;
1536  if (const MachineBasicBlock *MBB = getParent())
1537  if (const MachineFunction *MF = MBB->getParent())
1538  M = MF->getFunction()->getParent();
1539 
1540  ModuleSlotTracker MST(M);
1541  print(OS, MST, SkipOpers);
1542 }
1543 
1545  bool SkipOpers) const {
1546  // We can be a bit tidier if we know the MachineFunction.
1547  const MachineFunction *MF = nullptr;
1548  const TargetRegisterInfo *TRI = nullptr;
1549  const MachineRegisterInfo *MRI = nullptr;
1550  const TargetInstrInfo *TII = nullptr;
1551  if (const MachineBasicBlock *MBB = getParent()) {
1552  MF = MBB->getParent();
1553  if (MF) {
1554  MRI = &MF->getRegInfo();
1555  TRI = MF->getSubtarget().getRegisterInfo();
1556  TII = MF->getSubtarget().getInstrInfo();
1557  }
1558  }
1559 
1560  // Save a list of virtual registers.
1561  SmallVector<unsigned, 8> VirtRegs;
1562 
1563  // Print explicitly defined operands on the left of an assignment syntax.
1564  unsigned StartOp = 0, e = getNumOperands();
1565  for (; StartOp < e && getOperand(StartOp).isReg() &&
1566  getOperand(StartOp).isDef() &&
1567  !getOperand(StartOp).isImplicit();
1568  ++StartOp) {
1569  if (StartOp != 0) OS << ", ";
1570  getOperand(StartOp).print(OS, MST, TRI);
1571  unsigned Reg = getOperand(StartOp).getReg();
1573  VirtRegs.push_back(Reg);
1574  }
1575 
1576  if (StartOp != 0)
1577  OS << " = ";
1578 
1579  // Print the opcode name.
1580  if (TII)
1581  OS << TII->getName(getOpcode());
1582  else
1583  OS << "UNKNOWN";
1584 
1585  if (SkipOpers)
1586  return;
1587 
1588  // Print the rest of the operands.
1589  bool OmittedAnyCallClobbers = false;
1590  bool FirstOp = true;
1591  unsigned AsmDescOp = ~0u;
1592  unsigned AsmOpCount = 0;
1593 
1594  if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1595  // Print asm string.
1596  OS << " ";
1597  getOperand(InlineAsm::MIOp_AsmString).print(OS, MST, TRI);
1598 
1599  // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
1600  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1601  if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1602  OS << " [sideeffect]";
1603  if (ExtraInfo & InlineAsm::Extra_MayLoad)
1604  OS << " [mayload]";
1605  if (ExtraInfo & InlineAsm::Extra_MayStore)
1606  OS << " [maystore]";
1607  if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1608  OS << " [alignstack]";
1609  if (getInlineAsmDialect() == InlineAsm::AD_ATT)
1610  OS << " [attdialect]";
1611  if (getInlineAsmDialect() == InlineAsm::AD_Intel)
1612  OS << " [inteldialect]";
1613 
1614  StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1615  FirstOp = false;
1616  }
1617 
1618 
1619  for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1620  const MachineOperand &MO = getOperand(i);
1621 
1623  VirtRegs.push_back(MO.getReg());
1624 
1625  // Omit call-clobbered registers which aren't used anywhere. This makes
1626  // call instructions much less noisy on targets where calls clobber lots
1627  // of registers. Don't rely on MO.isDead() because we may be called before
1628  // LiveVariables is run, or we may be looking at a non-allocatable reg.
1629  if (MRI && isCall() &&
1630  MO.isReg() && MO.isImplicit() && MO.isDef()) {
1631  unsigned Reg = MO.getReg();
1633  if (MRI->use_empty(Reg)) {
1634  bool HasAliasLive = false;
1635  for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
1636  unsigned AliasReg = *AI;
1637  if (!MRI->use_empty(AliasReg)) {
1638  HasAliasLive = true;
1639  break;
1640  }
1641  }
1642  if (!HasAliasLive) {
1643  OmittedAnyCallClobbers = true;
1644  continue;
1645  }
1646  }
1647  }
1648  }
1649 
1650  if (FirstOp) FirstOp = false; else OS << ",";
1651  OS << " ";
1652  if (i < getDesc().NumOperands) {
1653  const MCOperandInfo &MCOI = getDesc().OpInfo[i];
1654  if (MCOI.isPredicate())
1655  OS << "pred:";
1656  if (MCOI.isOptionalDef())
1657  OS << "opt:";
1658  }
1659  if (isDebugValue() && MO.isMetadata()) {
1660  // Pretty print DBG_VALUE instructions.
1661  auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata());
1662  if (DIV && !DIV->getName().empty())
1663  OS << "!\"" << DIV->getName() << '\"';
1664  else
1665  MO.print(OS, MST, TRI);
1666  } else if (TRI && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
1667  OS << TRI->getSubRegIndexName(MO.getImm());
1668  } else if (i == AsmDescOp && MO.isImm()) {
1669  // Pretty print the inline asm operand descriptor.
1670  OS << '$' << AsmOpCount++;
1671  unsigned Flag = MO.getImm();
1672  switch (InlineAsm::getKind(Flag)) {
1673  case InlineAsm::Kind_RegUse: OS << ":[reguse"; break;
1674  case InlineAsm::Kind_RegDef: OS << ":[regdef"; break;
1675  case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;
1676  case InlineAsm::Kind_Clobber: OS << ":[clobber"; break;
1677  case InlineAsm::Kind_Imm: OS << ":[imm"; break;
1678  case InlineAsm::Kind_Mem: OS << ":[mem"; break;
1679  default: OS << ":[??" << InlineAsm::getKind(Flag); break;
1680  }
1681 
1682  unsigned RCID = 0;
1683  if (InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1684  if (TRI) {
1685  OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
1686  } else
1687  OS << ":RC" << RCID;
1688  }
1689 
1690  unsigned TiedTo = 0;
1691  if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1692  OS << " tiedto:$" << TiedTo;
1693 
1694  OS << ']';
1695 
1696  // Compute the index of the next operand descriptor.
1697  AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1698  } else
1699  MO.print(OS, MST, TRI);
1700  }
1701 
1702  // Briefly indicate whether any call clobbers were omitted.
1703  if (OmittedAnyCallClobbers) {
1704  if (!FirstOp) OS << ",";
1705  OS << " ...";
1706  }
1707 
1708  bool HaveSemi = false;
1709  const unsigned PrintableFlags = FrameSetup;
1710  if (Flags & PrintableFlags) {
1711  if (!HaveSemi) OS << ";"; HaveSemi = true;
1712  OS << " flags: ";
1713 
1714  if (Flags & FrameSetup)
1715  OS << "FrameSetup";
1716  }
1717 
1718  if (!memoperands_empty()) {
1719  if (!HaveSemi) OS << ";"; HaveSemi = true;
1720 
1721  OS << " mem:";
1722  for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1723  i != e; ++i) {
1724  (*i)->print(OS, MST);
1725  if (std::next(i) != e)
1726  OS << " ";
1727  }
1728  }
1729 
1730  // Print the regclass of any virtual registers encountered.
1731  if (MRI && !VirtRegs.empty()) {
1732  if (!HaveSemi) OS << ";"; HaveSemi = true;
1733  for (unsigned i = 0; i != VirtRegs.size(); ++i) {
1734  const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]);
1735  OS << " " << TRI->getRegClassName(RC)
1736  << ':' << PrintReg(VirtRegs[i]);
1737  for (unsigned j = i+1; j != VirtRegs.size();) {
1738  if (MRI->getRegClass(VirtRegs[j]) != RC) {
1739  ++j;
1740  continue;
1741  }
1742  if (VirtRegs[i] != VirtRegs[j])
1743  OS << "," << PrintReg(VirtRegs[j]);
1744  VirtRegs.erase(VirtRegs.begin()+j);
1745  }
1746  }
1747  }
1748 
1749  // Print debug location information.
1750  if (isDebugValue() && getOperand(e - 2).isMetadata()) {
1751  if (!HaveSemi) OS << ";";
1752  auto *DV = cast<DILocalVariable>(getOperand(e - 2).getMetadata());
1753  OS << " line no:" << DV->getLine();
1754  if (auto *InlinedAt = debugLoc->getInlinedAt()) {
1755  DebugLoc InlinedAtDL(InlinedAt);
1756  if (InlinedAtDL && MF) {
1757  OS << " inlined @[ ";
1758  InlinedAtDL.print(OS);
1759  OS << " ]";
1760  }
1761  }
1762  if (isIndirectDebugValue())
1763  OS << " indirect";
1764  } else if (debugLoc && MF) {
1765  if (!HaveSemi) OS << ";";
1766  OS << " dbg:";
1767  debugLoc.print(OS);
1768  }
1769 
1770  OS << '\n';
1771 }
1772 
1773 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1774  const TargetRegisterInfo *RegInfo,
1775  bool AddIfNotFound) {
1776  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1777  bool hasAliases = isPhysReg &&
1778  MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1779  bool Found = false;
1780  SmallVector<unsigned,4> DeadOps;
1781  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1782  MachineOperand &MO = getOperand(i);
1783  if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1784  continue;
1785  unsigned Reg = MO.getReg();
1786  if (!Reg)
1787  continue;
1788 
1789  if (Reg == IncomingReg) {
1790  if (!Found) {
1791  if (MO.isKill())
1792  // The register is already marked kill.
1793  return true;
1794  if (isPhysReg && isRegTiedToDefOperand(i))
1795  // Two-address uses of physregs must not be marked kill.
1796  return true;
1797  MO.setIsKill();
1798  Found = true;
1799  }
1800  } else if (hasAliases && MO.isKill() &&
1802  // A super-register kill already exists.
1803  if (RegInfo->isSuperRegister(IncomingReg, Reg))
1804  return true;
1805  if (RegInfo->isSubRegister(IncomingReg, Reg))
1806  DeadOps.push_back(i);
1807  }
1808  }
1809 
1810  // Trim unneeded kill operands.
1811  while (!DeadOps.empty()) {
1812  unsigned OpIdx = DeadOps.back();
1813  if (getOperand(OpIdx).isImplicit())
1814  RemoveOperand(OpIdx);
1815  else
1816  getOperand(OpIdx).setIsKill(false);
1817  DeadOps.pop_back();
1818  }
1819 
1820  // If not found, this means an alias of one of the operands is killed. Add a
1821  // new implicit operand if required.
1822  if (!Found && AddIfNotFound) {
1823  addOperand(MachineOperand::CreateReg(IncomingReg,
1824  false /*IsDef*/,
1825  true /*IsImp*/,
1826  true /*IsKill*/));
1827  return true;
1828  }
1829  return Found;
1830 }
1831 
1833  const TargetRegisterInfo *RegInfo) {
1835  RegInfo = nullptr;
1836  for (MachineOperand &MO : operands()) {
1837  if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1838  continue;
1839  unsigned OpReg = MO.getReg();
1840  if (OpReg == Reg || (RegInfo && RegInfo->isSuperRegister(Reg, OpReg)))
1841  MO.setIsKill(false);
1842  }
1843 }
1844 
1846  const TargetRegisterInfo *RegInfo,
1847  bool AddIfNotFound) {
1848  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(Reg);
1849  bool hasAliases = isPhysReg &&
1850  MCRegAliasIterator(Reg, RegInfo, false).isValid();
1851  bool Found = false;
1852  SmallVector<unsigned,4> DeadOps;
1853  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1854  MachineOperand &MO = getOperand(i);
1855  if (!MO.isReg() || !MO.isDef())
1856  continue;
1857  unsigned MOReg = MO.getReg();
1858  if (!MOReg)
1859  continue;
1860 
1861  if (MOReg == Reg) {
1862  MO.setIsDead();
1863  Found = true;
1864  } else if (hasAliases && MO.isDead() &&
1866  // There exists a super-register that's marked dead.
1867  if (RegInfo->isSuperRegister(Reg, MOReg))
1868  return true;
1869  if (RegInfo->isSubRegister(Reg, MOReg))
1870  DeadOps.push_back(i);
1871  }
1872  }
1873 
1874  // Trim unneeded dead operands.
1875  while (!DeadOps.empty()) {
1876  unsigned OpIdx = DeadOps.back();
1877  if (getOperand(OpIdx).isImplicit())
1878  RemoveOperand(OpIdx);
1879  else
1880  getOperand(OpIdx).setIsDead(false);
1881  DeadOps.pop_back();
1882  }
1883 
1884  // If not found, this means an alias of one of the operands is dead. Add a
1885  // new implicit operand if required.
1886  if (Found || !AddIfNotFound)
1887  return Found;
1888 
1889  addOperand(MachineOperand::CreateReg(Reg,
1890  true /*IsDef*/,
1891  true /*IsImp*/,
1892  false /*IsKill*/,
1893  true /*IsDead*/));
1894  return true;
1895 }
1896 
1898  for (MachineOperand &MO : operands()) {
1899  if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
1900  continue;
1901  MO.setIsDead(false);
1902  }
1903 }
1904 
1906  for (MachineOperand &MO : operands()) {
1907  if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
1908  continue;
1909  MO.setIsUndef();
1910  }
1911 }
1912 
1914  const TargetRegisterInfo *RegInfo) {
1916  MachineOperand *MO = findRegisterDefOperand(Reg, false, RegInfo);
1917  if (MO)
1918  return;
1919  } else {
1920  for (const MachineOperand &MO : operands()) {
1921  if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
1922  MO.getSubReg() == 0)
1923  return;
1924  }
1925  }
1926  addOperand(MachineOperand::CreateReg(Reg,
1927  true /*IsDef*/,
1928  true /*IsImp*/));
1929 }
1930 
1932  const TargetRegisterInfo &TRI) {
1933  bool HasRegMask = false;
1934  for (MachineOperand &MO : operands()) {
1935  if (MO.isRegMask()) {
1936  HasRegMask = true;
1937  continue;
1938  }
1939  if (!MO.isReg() || !MO.isDef()) continue;
1940  unsigned Reg = MO.getReg();
1941  if (!TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
1942  // If there are no uses, including partial uses, the def is dead.
1943  if (std::none_of(UsedRegs.begin(), UsedRegs.end(),
1944  [&](unsigned Use) { return TRI.regsOverlap(Use, Reg); }))
1945  MO.setIsDead();
1946  }
1947 
1948  // This is a call with a register mask operand.
1949  // Mask clobbers are always dead, so add defs for the non-dead defines.
1950  if (HasRegMask)
1951  for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1952  I != E; ++I)
1953  addRegisterDefined(*I, &TRI);
1954 }
1955 
1956 unsigned
1958  // Build up a buffer of hash code components.
1959  SmallVector<size_t, 8> HashComponents;
1960  HashComponents.reserve(MI->getNumOperands() + 1);
1961  HashComponents.push_back(MI->getOpcode());
1962  for (const MachineOperand &MO : MI->operands()) {
1963  if (MO.isReg() && MO.isDef() &&
1965  continue; // Skip virtual register defs.
1966 
1967  HashComponents.push_back(hash_value(MO));
1968  }
1969  return hash_combine_range(HashComponents.begin(), HashComponents.end());
1970 }
1971 
1973  // Find the source location cookie.
1974  unsigned LocCookie = 0;
1975  const MDNode *LocMD = nullptr;
1976  for (unsigned i = getNumOperands(); i != 0; --i) {
1977  if (getOperand(i-1).isMetadata() &&
1978  (LocMD = getOperand(i-1).getMetadata()) &&
1979  LocMD->getNumOperands() != 0) {
1980  if (const ConstantInt *CI =
1981  mdconst::dyn_extract<ConstantInt>(LocMD->getOperand(0))) {
1982  LocCookie = CI->getZExtValue();
1983  break;
1984  }
1985  }
1986  }
1987 
1988  if (const MachineBasicBlock *MBB = getParent())
1989  if (const MachineFunction *MF = MBB->getParent())
1990  return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
1991  report_fatal_error(Msg);
1992 }
bool isImplicit() const
void bundleWithPred()
Bundle this instruction with its predecessor.
void push_back(const T &Elt)
Definition: SmallVector.h:222
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
const GlobalValue * getGlobal() const
bool isPredicate() const
Set if this is one of the operands that made up of the predicate operand that controls an isPredicabl...
Definition: MCInstrDesc.h:82
instr_iterator instr_end()
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
static void Found()
void setTargetFlags(unsigned F)
const ConstantFP * getFPImm() const
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
MachineBasicBlock * getMBB() const
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:39
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:114
bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
unsigned getNumOperands() const
Return number of MDNode operands.
Definition: Metadata.h:942
void setIsDef(bool Val=true)
Change a def to a use, or a use to a def.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:138
void setIsUndef(bool Val=true)
iterator end() const
Definition: ArrayRef.h:123
bool isDead() const
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
Address of indexed Jump Table for switch.
This file contains the declarations for metadata subclasses.
bool isTied() const
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
bool isBundle(MCInst const &MCI)
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:264
MachineBasicBlock reference.
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const
getCommonSubClass - find the largest common subclass of A and B.
const char * getSymbolName() const
A debug info location.
Definition: DebugLoc.h:34
Metadata node.
Definition: Metadata.h:740
void setIsDead(bool Val=true)
bool isSubRegister(unsigned RegA, unsigned RegB) const
Returns true if RegB is a sub-register of RegA.
union llvm::MachineOperand::@33::@35::@36 Val
Manage lifetime of a slot tracker for printing IR.
const MDNode * getMetadata() const
void reserve(size_type N)
Definition: SmallVector.h:401
Instructions::iterator instr_iterator
Mask of live-out registers.
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:295
void substVirtReg(unsigned Reg, unsigned SubIdx, const TargetRegisterInfo &)
substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.
bool isMetadata() const
isMetadata - Tests if this is a MO_Metadata operand.
void markUsesInDebugValueAsUndef(unsigned Reg) const
markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the specified register as undefined wh...
void setPhysRegsDeadExcept(ArrayRef< unsigned > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx)
isUseOperandTiedToDef - Return true if the flag of the inline asm operand indicates it is an use oper...
Definition: InlineAsm.h:338
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag=true)
Reports a serious error, calling any installed error handler.
virtual bool pointsToConstantMemory(const MemoryLocation &Loc, bool OrLocal=false)
pointsToConstantMemory - If the specified memory location is known to be constant, return true.
Mask of preserved registers.
const TargetRegisterClass * getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.
void ChangeToMCSymbol(MCSymbol *Sym)
ChangeToMCSymbol - Replace this operand with a new MC symbol operand.
void clearKillInfo()
Clears kill flags on all operands.
unsigned getBundleSize() const
Return the number of instructions inside the MI bundle, excluding the bundle header.
MachineMemOperand - A description of a memory reference used in the backend.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
const HexagonInstrInfo * TII
unsigned getCFIIndex() const
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false)
MCCFIInstruction index.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
const TargetRegisterClass * getRegClass(unsigned i) const
getRegClass - Returns the register class associated with the enumeration value.
A Use represents the edge between a Value definition and its users.
Definition: Use.h:69
void ChangeToES(const char *SymName, unsigned char TargetFlags=0)
ChangeToES - Replace this operand with a new external symbol operand.
Target-dependent index+offset operand.
std::pair< bool, bool > readsWritesVirtualRegister(unsigned Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
const TargetRegisterClass * getRegClass(unsigned Reg) const
getRegClass - Return the register class of the specified virtual register.
Name of external global symbol.
void addRegisterDefReadUndef(unsigned Reg)
Mark all subregister defs of register Reg with the undef flag.
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
Number of individual test Apply this number of consecutive mutations to each input exit after the first new interesting input is found the minimized corpus is saved into the first input directory Number of jobs to run If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
bool isUndef() const
void bundleWithSucc()
Bundle this instruction with its successor.
ELFYAML::ELF_STO Other
Definition: ELFYAML.cpp:591
void print(raw_ostream &OS) const
prints source location /path/to/file.exe:line:col @[inlined at]
Definition: DebugLoc.cpp:86
void eraseFromParentAndMarkDBGValuesForRemoval()
Unlink 'this' from the containing basic block and delete it.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:271
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
Definition: MCInstrDesc.h:264
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
Definition: Constants.h:117
void setIsEarlyClobber(bool Val=true)
void unbundleFromPred()
Break bundle above this instruction.
PrintReg - Helper class for printing registers on a raw_ostream.
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
bool isKill() const
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Definition: SmallVector.h:57
Immediate >64bit operand.
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
getMatchingSuperRegClass - Return a subclass of the specified register class A so that each register ...
hash_code hash_value(const APFloat &Arg)
See friend declarations above.
Definition: APFloat.cpp:2848
const char * getRegClassName(const TargetRegisterClass *Class) const
getRegClassName - Returns the name of the register class.
int64_t getImm() const
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo)
Clear all kill flags affecting Reg.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:267
unsigned short NumOperands
Definition: MCInstrDesc.h:141
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:97
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:120
Function * getFunction(StringRef Name) const
Look up the specified function in the module symbol table.
Definition: Module.cpp:188
TargetInstrInfo - Interface to description of machine instruction set.
bool isEarlyClobber() const
unsigned findTiedOperandIdx(unsigned OpIdx) const
Given the index of a tied register operand, find the operand it is tied to.
Address of a global value.
unsigned getTargetFlags() const
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr) const
bool regsOverlap(unsigned regA, unsigned regB) const
regsOverlap - Returns true if the two registers are equal or alias each other.
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
void print(raw_ostream &OS, bool SkipOpers=false) const
bool isOptionalDef() const
Set if this operand is a optional def.
Definition: MCInstrDesc.h:85
void clearRegisterDeads(unsigned Reg)
Clear all dead flags on operands defining register Reg.
const char * getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
Definition: MCInstrInfo.h:51
int findRegisterDefOperandIdx(unsigned Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a def of the specified register or -1 if it is not found...
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:233
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag...
Definition: InlineAsm.h:332
MCRegAliasIterator enumerates all registers aliasing Reg.
int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo=nullptr) const
Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instructio...
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
Address of a basic block.
iterator begin() const
Definition: ArrayRef.h:122
void substPhysReg(unsigned Reg, const TargetRegisterInfo &)
substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore...
static unsigned getKind(unsigned Flags)
Definition: InlineAsm.h:311
int64_t getOffset() const
Return the offset from the symbol in this operand.
SI Fold Operands
bool isInvariantLoad(AliasAnalysis *AA) const
Return true if this instruction is loading from a location whose value is invariant across the functi...
void setOffset(int64_t Offset)
unsigned getSubReg() const
static unsigned getHashValue(const MachineInstr *const &MI)
iterator erase(iterator I)
Definition: SmallVector.h:455
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
struct llvm::MachineOperand::@33::@34 Reg
void emitError(StringRef Msg) const
Emit an error referring to the source location of this instruction.
void eraseFromBundle()
Unlink 'this' form its basic block and delete it.
void setIsKill(bool Val=true)
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
Representation for a specific memory location.
int findRegisterUseOperandIdx(unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a use of the specific register or -1 if it is not found...
const ConstantInt * CI
const MDOperand & getOperand(unsigned I) const
Definition: Metadata.h:936
MachineInstr * removeFromBundle()
Unlink this instruction from its basic block and return it without deleting it.
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
This is the shared class of boolean and integer constants.
Definition: Constants.h:47
void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
bool isIdenticalTo(const MachineInstr *Other, MICheckType Check=CheckDefs) const
Return true if this instruction is identical to (same opcode and same operands as) the specified inst...
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
MachineBasicBlock * MBB
MachineOperand class - Representation of each machine instruction operand.
Module.h This file contains the declarations for the Module class.
void ChangeToFPImmediate(const ConstantFP *FPImm)
ChangeToFPImmediate - Replace this operand with a new FP immediate operand of the specified value...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:123
friend hash_code hash_value(const MachineOperand &MO)
MachineOperand hash_value overload.
MCSymbol reference (for debug/eh info)
void dump() const
void addRegisterDefined(unsigned Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
const ConstantInt * getCImm() const
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
hash_code hash_combine(const Ts &...args)
Combine values into a single hash_code.
Definition: Hashing.h:603
PseudoSourceValue - Special value supplied for machine level alias analysis.
const char * getSubRegIndexName(unsigned SubIdx) const
getSubRegIndexName - Return the human-readable symbolic target-specific name for the specified SubReg...
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:285
hash_code hash_combine_range(InputIteratorT first, InputIteratorT last)
Compute a hash_code for a sequence of values.
Definition: Hashing.h:481
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
An opaque object representing a hash code.
Definition: Hashing.h:73
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:238
const unsigned TiedMax
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
static bool hasRegClassConstraint(unsigned Flag, unsigned &RC)
hasRegClassConstraint - Returns true if the flag contains a register class constraint.
Definition: InlineAsm.h:347
bool isSuperRegister(unsigned RegA, unsigned RegB) const
Returns true if RegB is a super-register of RegA.
Representation of each machine instruction.
Definition: MachineInstr.h:51
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
static bool isPhysicalRegister(unsigned Reg)
isPhysicalRegister - Return true if the specified register number is in the physical register namespa...
void copyImplicitOps(MachineFunction &MF, const MachineInstr *MI)
Copy implicit register operands from specified instruction to this instruction.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps, MachineRegisterInfo *MRI)
Move NumOps MachineOperands from Src to Dst, with support for overlapping ranges. ...
std::error_code Check(std::error_code Err)
void setReg(unsigned Reg)
Change the register this operand corresponds to.
#define I(x, y, z)
Definition: MD5.cpp:54
#define N
void setSubReg(unsigned subReg)
MCSymbol * getMCSymbol() const
MCInstrDesc const & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
Abstract Stack Frame Index.
const TargetRegisterClass * getRegClassConstraintEffectForVReg(unsigned Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ExploreBundle=false) const
Applies the constraints (def/use) implied by this MI on Reg to the given CurRC.
MachineInstr * removeFromParent()
Unlink 'this' from the containing basic block, and return it without deleting it. ...
unsigned getReg() const
getReg - Returns the register number.
bool isValid() const
isValid - Returns true until all the operands have been visited.
void unbundleFromSucc()
Break bundle below this instruction.
unsigned isConstantValuePHI() const
If the specified instruction is a PHI that always merges together the same virtual register...
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
getSubClassWithSubReg - Returns the largest legal sub-class of RC that supports the sub-register inde...
virtual const TargetInstrInfo * getInstrInfo() const
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:365
LLVM Value Representation.
Definition: Value.h:69
Floating-point immediate operand.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:185
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:149
bool isDebug() const
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:38
bool addRegisterKilled(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:40
const BlockAddress * getBlockAddress() const
unsigned composeSubRegIndices(unsigned a, unsigned b) const
composeSubRegIndices - Return the subregister index you get from composing two subregister indices...
const TargetRegisterClass * getRegClass(const MCInstrDesc &TID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum...
Address of indexed Constant in Constant Pool.
bool isStackAligningInlineAsm() const
bool isIdenticalTo(const MachineOperand &Other) const
isIdenticalTo - Return true if this operand is identical to the specified operand.
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:56
MachineInstr::mmo_iterator allocateMemRefsArray(unsigned long Num)
allocateMemRefsArray - Allocate an array to hold MachineMemOperand pointers.
virtual const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const
getPointerRegClass - Returns a TargetRegisterClass used for pointer values.
InlineAsm::AsmDialect getInlineAsmDialect() const
bool isInternalRead() const
bool use_empty(unsigned RegNo) const
use_empty - Return true if there are no instructions using the specified register.
Metadata reference (for debug info)
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.