LLVM  3.7.0
SelectionDAGISel.h
Go to the documentation of this file.
1 //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the SelectionDAGISel class, which is used as the common
11 // base class for SelectionDAG-based instruction selectors.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_CODEGEN_SELECTIONDAGISEL_H
16 #define LLVM_CODEGEN_SELECTIONDAGISEL_H
17 
20 #include "llvm/IR/BasicBlock.h"
21 #include "llvm/Pass.h"
23 
24 namespace llvm {
25  class FastISel;
26  class SelectionDAGBuilder;
27  class SDValue;
28  class MachineRegisterInfo;
29  class MachineBasicBlock;
30  class MachineFunction;
31  class MachineInstr;
32  class TargetLowering;
33  class TargetLibraryInfo;
34  class FunctionLoweringInfo;
35  class ScheduleHazardRecognizer;
36  class GCFunctionInfo;
37  class ScheduleDAGSDNodes;
38  class LoadInst;
39 
40 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based
41 /// pattern-matching instruction selectors.
43 public:
56 
57  static char ID;
58 
59  explicit SelectionDAGISel(TargetMachine &tm,
61  ~SelectionDAGISel() override;
62 
63  const TargetLowering *getTargetLowering() const { return TLI; }
64 
65  void getAnalysisUsage(AnalysisUsage &AU) const override;
66 
67  bool runOnMachineFunction(MachineFunction &MF) override;
68 
69  virtual void EmitFunctionEntryCode() {}
70 
71  /// PreprocessISelDAG - This hook allows targets to hack on the graph before
72  /// instruction selection starts.
73  virtual void PreprocessISelDAG() {}
74 
75  /// PostprocessISelDAG() - This hook allows the target to hack on the graph
76  /// right after selection.
77  virtual void PostprocessISelDAG() {}
78 
79  /// Select - Main hook targets implement to select a node.
80  virtual SDNode *Select(SDNode *N) = 0;
81 
82  /// SelectInlineAsmMemoryOperand - Select the specified address as a target
83  /// addressing mode, according to the specified constraint. If this does
84  /// not match or is not implemented, return true. The resultant operands
85  /// (which will appear in the machine instruction) should be added to the
86  /// OutOps vector.
87  virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
88  unsigned ConstraintID,
89  std::vector<SDValue> &OutOps) {
90  return true;
91  }
92 
93  /// IsProfitableToFold - Returns true if it's profitable to fold the specific
94  /// operand node N of U during instruction selection that starts at Root.
95  virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
96 
97  /// IsLegalToFold - Returns true if the specific operand node N of
98  /// U can be folded during instruction selection that starts at Root.
99  /// FIXME: This is a static member function because the MSP430/X86
100  /// targets, which uses it during isel. This could become a proper member.
101  static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
103  bool IgnoreChains = false);
104 
105  // Opcodes used by the DAG state machine:
135 
149  };
150 
151  enum {
152  OPFL_None = 0, // Node has no chain or glue input and isn't variadic.
153  OPFL_Chain = 1, // Node has a chain input.
154  OPFL_GlueInput = 2, // Node has a glue input.
155  OPFL_GlueOutput = 4, // Node has a glue output.
156  OPFL_MemRefs = 8, // Node gets accumulated MemRefs.
157  OPFL_Variadic0 = 1<<4, // Node is variadic, root has 0 fixed inputs.
158  OPFL_Variadic1 = 2<<4, // Node is variadic, root has 1 fixed inputs.
159  OPFL_Variadic2 = 3<<4, // Node is variadic, root has 2 fixed inputs.
160  OPFL_Variadic3 = 4<<4, // Node is variadic, root has 3 fixed inputs.
161  OPFL_Variadic4 = 5<<4, // Node is variadic, root has 4 fixed inputs.
162  OPFL_Variadic5 = 6<<4, // Node is variadic, root has 5 fixed inputs.
163  OPFL_Variadic6 = 7<<4, // Node is variadic, root has 6 fixed inputs.
164 
166  };
167 
168  /// getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the
169  /// number of fixed arity values that should be skipped when copying from the
170  /// root.
171  static inline int getNumFixedFromVariadicInfo(unsigned Flags) {
172  return ((Flags&OPFL_VariadicInfo) >> 4)-1;
173  }
174 
175 
176 protected:
177  /// DAGSize - Size of DAG being instruction selected.
178  ///
179  unsigned DAGSize;
180 
181  /// ReplaceUses - replace all uses of the old node F with the use
182  /// of the new node T.
185  }
186 
187  /// ReplaceUses - replace all uses of the old nodes F with the use
188  /// of the new nodes T.
189  void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num) {
191  }
192 
193  /// ReplaceUses - replace all uses of the old node F with the use
194  /// of the new node T.
196  CurDAG->ReplaceAllUsesWith(F, T);
197  }
198 
199 
200  /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
201  /// by tblgen. Others should not call it.
202  void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops, SDLoc DL);
203 
204 
205 public:
206  // Calls to these predicates are generated by tblgen.
207  bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
208  int64_t DesiredMaskS) const;
209  bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
210  int64_t DesiredMaskS) const;
211 
212 
213  /// CheckPatternPredicate - This function is generated by tblgen in the
214  /// target. It runs the specified pattern predicate and returns true if it
215  /// succeeds or false if it fails. The number is a private implementation
216  /// detail to the code tblgen produces.
217  virtual bool CheckPatternPredicate(unsigned PredNo) const {
218  llvm_unreachable("Tblgen should generate the implementation of this!");
219  }
220 
221  /// CheckNodePredicate - This function is generated by tblgen in the target.
222  /// It runs node predicate number PredNo and returns true if it succeeds or
223  /// false if it fails. The number is a private implementation
224  /// detail to the code tblgen produces.
225  virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const {
226  llvm_unreachable("Tblgen should generate the implementation of this!");
227  }
228 
229  virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N,
230  unsigned PatternNo,
231  SmallVectorImpl<std::pair<SDValue, SDNode*> > &Result) {
232  llvm_unreachable("Tblgen should generate the implementation of this!");
233  }
234 
235  virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) {
236  llvm_unreachable("Tblgen should generate this!");
237  }
238 
239  SDNode *SelectCodeCommon(SDNode *NodeToMatch,
240  const unsigned char *MatcherTable,
241  unsigned TableSize);
242 
243  /// \brief Return true if complex patterns for this target can mutate the
244  /// DAG.
245  virtual bool ComplexPatternFuncMutatesDAG() const {
246  return false;
247  }
248 
249 private:
250 
251  // Calls to these functions are generated by tblgen.
252  SDNode *Select_INLINEASM(SDNode *N);
253  SDNode *Select_READ_REGISTER(SDNode *N);
254  SDNode *Select_WRITE_REGISTER(SDNode *N);
255  SDNode *Select_UNDEF(SDNode *N);
256  void CannotYetSelect(SDNode *N);
257 
258 private:
259  void DoInstructionSelection();
260  SDNode *MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTs,
261  ArrayRef<SDValue> Ops, unsigned EmitNodeInfo);
262 
263  /// Prepares the landing pad to take incoming values or do other EH
264  /// personality specific tasks. Returns true if the block should be
265  /// instruction selected, false if no code should be emitted for it.
266  bool PrepareEHLandingPad();
267 
268  /// \brief Perform instruction selection on all basic blocks in the function.
269  void SelectAllBasicBlocks(const Function &Fn);
270 
271  /// \brief Perform instruction selection on a single basic block, for
272  /// instructions between \p Begin and \p End. \p HadTailCall will be set
273  /// to true if a call in the block was translated as a tail call.
274  void SelectBasicBlock(BasicBlock::const_iterator Begin,
276  bool &HadTailCall);
277  void FinishBasicBlock();
278 
279  void CodeGenAndEmitDAG();
280 
281  /// \brief Generate instructions for lowering the incoming arguments of the
282  /// given function.
283  void LowerArguments(const Function &F);
284 
285  void ComputeLiveOutVRegInfo();
286 
287  /// Create the scheduler. If a specific scheduler was specified
288  /// via the SchedulerRegistry, use it, otherwise select the
289  /// one preferred by the target.
290  ///
291  ScheduleDAGSDNodes *CreateScheduler();
292 
293  /// OpcodeOffset - This is a cache used to dispatch efficiently into isel
294  /// state machines that start with a OPC_SwitchOpcode node.
295  std::vector<unsigned> OpcodeOffset;
296 
297  void UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
298  const SmallVectorImpl<SDNode*> &ChainNodesMatched,
299  SDValue InputGlue, const SmallVectorImpl<SDNode*> &F,
300  bool isMorphNodeTo);
301 
302 };
303 
304 }
305 
306 #endif /* LLVM_CODEGEN_SELECTIONDAGISEL_H */
void ReplaceUses(SDNode *F, SDNode *T)
ReplaceUses - replace all uses of the old node F with the use of the new node T.
SelectionDAGBuilder * SDB
static int getNumFixedFromVariadicInfo(unsigned Flags)
getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the number of fixed arity values ...
GCFunctionInfo * GFI
void ReplaceUses(SDValue F, SDValue T)
ReplaceUses - replace all uses of the old node F with the use of the new node T.
SelectionDAGBuilder - This is the common target-independent lowering implementation that is parameter...
F(f)
MachineFunction * MF
void ReplaceAllUsesOfValuesWith(const SDValue *From, const SDValue *To, unsigned Num)
Like ReplaceAllUsesOfValueWith, but for multiple values at once.
const TargetLibraryInfo * LibInfo
bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS, int64_t DesiredMaskS) const
CheckAndMask - The isel is trying to match something like (and X, 255).
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, CodeGenOpt::Level OptLevel, bool IgnoreChains=false)
IsLegalToFold - Returns true if the specific operand node N of U can be folded during instruction sel...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
const TargetLowering * TLI
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APInt.h:33
const TargetLowering * getTargetLowering() const
SDNode * SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, unsigned TableSize)
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
unsigned DAGSize
DAGSize - Size of DAG being instruction selected.
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: ArrayRef.h:31
TargetInstrInfo - Interface to description of machine instruction set.
MachineRegisterInfo * RegInfo
virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const
IsProfitableToFold - Returns true if it's profitable to fold the specific operand node N of U during ...
CodeGenOpt::Level OptLevel
ScheduleDAGSDNodes - A ScheduleDAG for scheduling SDNode-based DAGs.
virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const
CheckNodePredicate - This function is generated by tblgen in the target.
Represent the analysis usage information of a pass.
virtual void EmitFunctionEntryCode()
virtual void PostprocessISelDAG()
PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection...
virtual SDNode * Select(SDNode *N)=0
Select - Main hook targets implement to select a node.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:179
Provides information about what library functions are available for the current target.
SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL=CodeGenOpt::Default)
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N, unsigned PatternNo, SmallVectorImpl< std::pair< SDValue, SDNode * > > &Result)
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
void SelectInlineAsmMemoryOperands(std::vector< SDValue > &Ops, SDLoc DL)
SelectInlineAsmMemoryOperands - Calls to this are automatically generated by tblgen.
void ReplaceAllUsesWith(SDValue From, SDValue Op)
Modify anything using 'From' to use 'To' instead.
#define N
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS, int64_t DesiredMaskS) const
CheckOrMask - The isel is trying to match something like (or X, 255).
virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, std::vector< SDValue > &OutOps)
SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode...
virtual bool CheckPatternPredicate(unsigned PredNo) const
CheckPatternPredicate - This function is generated by tblgen in the target.
void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num)
ReplaceUses - replace all uses of the old nodes F with the use of the new nodes T.
void ReplaceAllUsesOfValueWith(SDValue From, SDValue To)
Replace any uses of From with To, leaving uses of other values produced by From.Val alone...
Primary interface to the complete machine description for the target machine.
Garbage collection metadata for a single function.
Definition: GCMetadata.h:73
virtual void PreprocessISelDAG()
PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts...
virtual bool ComplexPatternFuncMutatesDAG() const
Return true if complex patterns for this target can mutate the DAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
const TargetInstrInfo * TII
FunctionLoweringInfo * FuncInfo
virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo)