15 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64CALLINGCONVENTION_H
16 #define LLVM_LIB_TARGET_AARCH64_AARCH64CALLINGCONVENTION_H
28 static const uint16_t XRegList[] = {AArch64::X0, AArch64::X1, AArch64::X2,
29 AArch64::X3, AArch64::X4, AArch64::X5,
30 AArch64::X6, AArch64::X7};
31 static const uint16_t HRegList[] = {AArch64::H0, AArch64::H1, AArch64::H2,
32 AArch64::H3, AArch64::H4, AArch64::H5,
33 AArch64::H6, AArch64::H7};
34 static const uint16_t
SRegList[] = {AArch64::S0, AArch64::S1, AArch64::S2,
35 AArch64::S3, AArch64::S4, AArch64::S5,
36 AArch64::S6, AArch64::S7};
37 static const uint16_t
DRegList[] = {AArch64::D0, AArch64::D1, AArch64::D2,
38 AArch64::D3, AArch64::D4, AArch64::D5,
39 AArch64::D6, AArch64::D7};
40 static const uint16_t
QRegList[] = {AArch64::Q0, AArch64::Q1, AArch64::Q2,
41 AArch64::Q3, AArch64::Q4, AArch64::Q5,
42 AArch64::Q6, AArch64::Q7};
46 CCState &State,
unsigned SlotAlign) {
54 for (
auto &It : PendingMembers) {
55 It.convertToMem(State.
AllocateStack(Size, std::max(Align, SlotAlign)));
61 PendingMembers.clear();
67 static bool CC_AArch64_Custom_Stack_Block(
80 return finishStackBlock(PendingMembers, LocVT, ArgFlags, State, 8);
86 static bool CC_AArch64_Custom_Block(
unsigned &ValNo,
MVT &ValVT,
MVT &LocVT,
119 for (
auto &It : PendingMembers) {
120 It.convertToReg(RegResult);
124 PendingMembers.clear();
129 for (
auto Reg : RegList)
136 return finishStackBlock(PendingMembers, LocVT, ArgFlags, State, SlotAlign);
void push_back(const T &Elt)
static CCValAssign getPending(unsigned ValNo, MVT ValVT, MVT LocVT, LocInfo HTP, unsigned ExtraInfo=0)
unsigned getStackAlignment() const
unsigned getSizeInBits() const
bool is32BitVector() const
is32BitVector - Return true if this is a 32-bit vector type.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void addLoc(const CCValAssign &V)
Reg
All possible values of the reg field in the ModR/M byte.
Number of individual test Apply this number of consecutive mutations to each input exit after the first new interesting input is found the minimized corpus is saved into the first input directory Number of jobs to run If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
SmallVectorImpl< llvm::CCValAssign > & getPendingLocs()
MachineFunction & getMachineFunction() const
static const uint16_t QRegList[]
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
bool isInConsecutiveRegsLast() const
unsigned AllocateRegBlock(ArrayRef< uint16_t > Regs, unsigned RegsRequired)
AllocateRegBlock - Attempt to allocate a block of RegsRequired consecutive registers.
MVT - Machine Value Type.
CCState - This class holds information needed while lowering arguments and return values...
const DataLayout * getDataLayout() const
Deprecated in 3.7, will be removed in 3.8.
static const uint16_t SRegList[]
bool is64BitVector() const
is64BitVector - Return true if this is a 64-bit vector type.
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
bool is128BitVector() const
is128BitVector - Return true if this is a 128-bit vector type.
bool isTargetDarwin() const
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
static const uint16_t DRegList[]
unsigned getOrigAlign() const
unsigned AllocateReg(unsigned Reg)
AllocateReg - Attempt to allocate one register.
unsigned AllocateStack(unsigned Size, unsigned Align)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.