31 #define GET_INSTRINFO_CTOR_DTOR
32 #include "XCoreGenInstrInfo.inc"
47 void XCoreInstrInfo::anchor() {}
66 if (Opcode == XCore::LDWFI)
88 if (Opcode == XCore::STWFI)
105 static inline bool IsBRU(
unsigned BrOpc) {
106 return BrOpc == XCore::BRFU_u6
107 || BrOpc == XCore::BRFU_lu6
108 || BrOpc == XCore::BRBU_u6
109 || BrOpc == XCore::BRBU_lu6;
112 static inline bool IsBRT(
unsigned BrOpc) {
113 return BrOpc == XCore::BRFT_ru6
114 || BrOpc == XCore::BRFT_lru6
115 || BrOpc == XCore::BRBT_ru6
116 || BrOpc == XCore::BRBT_lru6;
119 static inline bool IsBRF(
unsigned BrOpc) {
120 return BrOpc == XCore::BRFF_ru6
121 || BrOpc == XCore::BRFF_lru6
122 || BrOpc == XCore::BRBF_ru6
123 || BrOpc == XCore::BRBF_lru6;
141 }
else if (
IsBRF(BrOpc)) {
197 bool AllowModify)
const {
203 if (!isUnpredicatedTerminator(I))
210 if (I == MBB.
begin() || !isUnpredicatedTerminator(--I)) {
233 if (SecondLastInst && I != MBB.
begin() &&
234 isUnpredicatedTerminator(--I))
237 unsigned SecondLastOpc = SecondLastInst->
getOpcode();
282 assert(TBB &&
"InsertBranch must not be told to insert a fallthrough");
283 assert((Cond.
size() == 2 || Cond.
size() == 0) &&
284 "Unexpected number of components!");
300 assert(Cond.
size() == 2 &&
"Unexpected number of components!");
318 I->eraseFromParent();
322 if (I == MBB.
begin())
return 1;
328 I->eraseFromParent();
334 unsigned DestReg,
unsigned SrcReg,
335 bool KillSrc)
const {
336 bool GRDest = XCore::GRRegsRegClass.contains(DestReg);
337 bool GRSrc = XCore::GRRegsRegClass.contains(SrcReg);
339 if (GRDest && GRSrc) {
340 BuildMI(MBB, I, DL,
get(XCore::ADD_2rus), DestReg)
346 if (GRDest && SrcReg == XCore::SP) {
347 BuildMI(MBB, I, DL,
get(XCore::LDAWSP_ru6), DestReg).
addImm(0);
351 if (DestReg == XCore::SP && GRSrc) {
352 BuildMI(MBB, I, DL,
get(XCore::SETSP_1r))
361 unsigned SrcReg,
bool isKill,
367 if (I != MBB.
end() && !I->isDebugValue())
368 DL = I->getDebugLoc();
376 BuildMI(MBB, I, DL,
get(XCore::STWFI))
390 if (I != MBB.
end() && !I->isDebugValue())
391 DL = I->getDebugLoc();
399 BuildMI(MBB, I, DL,
get(XCore::LDWFI), DestReg)
409 assert((Cond.
size() == 2) &&
410 "Invalid XCore branch condition!");
416 return val < (1 << 6);
420 return val < (1 << 16);
428 return (N >= 1 && N <= 8) || N == 16 || N == 24 || N == 32;
434 unsigned Reg, uint64_t
Value)
const {
436 if (MI != MBB.
end() && !MI->isDebugValue())
437 dl = MI->getDebugLoc();
440 return BuildMI(MBB, MI, dl,
get(XCore::MKMSK_rus), Reg)
445 int Opcode =
isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
452 return BuildMI(MBB, MI, dl,
get(XCore::LDWCP_lru6), Reg)
void push_back(const T &Elt)
The memory access reads data.
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
unsigned RemoveBranch(MachineBasicBlock &MBB) const override
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
The memory access writes data.
static bool IsBRT(unsigned BrOpc)
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
bool ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
ReverseBranchCondition - Return the inverse opcode of the specified Branch instruction.
MachineBasicBlock * getMBB() const
static bool isImmMskBitp(unsigned val)
unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const override
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot...
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
static XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC)
GetOppositeBranchCondition - Return the inverse of the specified condition, e.g.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, unsigned f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
getMachineMemOperand - Allocate a new MachineMemOperand.
static MachinePointerInfo getFixedStack(int FI, int64_t offset=0)
getFixedStack - Return a MachinePointerInfo record that refers to the the specified FrameIndex...
MachineMemOperand - A description of a memory reference used in the backend.
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static bool IsBRF(unsigned BrOpc)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, DebugLoc DL) const override
bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
AnalyzeBranch - Analyze the branching code at the end of MBB, returning true if it cannot be understo...
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
iterator getLastNonDebugInstr()
getLastNonDebugInstr - returns an iterator to the last non-debug instruction in the basic block...
static bool IsBRU(unsigned BrOpc)
static bool isImmU16(unsigned val)
size_t size() const
size - Get the array size.
unsigned getKillRegState(bool B)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
bundle_iterator< MachineInstr, instr_iterator > iterator
static bool isImmU6(unsigned val)
This is an important base class in LLVM.
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const MachineOperand & getOperand(unsigned i) const
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
MachineBasicBlock::iterator loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Reg, uint64_t Value) const
bool empty() const
empty - Check if the array is empty.
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
static unsigned GetCondBranchFromCond(XCore::CondCode CC)
GetCondBranchFromCond - Return the Branch instruction opcode that matches the cc. ...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
MachineOperand class - Representation of each machine instruction operand.
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const MachineInstrBuilder & addFrameIndex(int Idx) const
unsigned Log2_32(uint32_t Value)
Log2_32 - This function returns the floor log base 2 of the specified value, -1 if the value is zero...
static bool IsCondBranch(unsigned BrOpc)
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
bool isMask_32(uint32_t Value)
isMask_32 - This function returns true if the argument is a non-empty sequence of ones starting at th...
unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot...
BR_JT - Jumptable branch.
Representation of each machine instruction.
static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc)
GetCondFromBranchOpc - Return the XCore CC that matches the correspondent Branch instruction opcode...
static IntegerType * getInt32Ty(LLVMContext &C)
const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned char TargetFlags=0) const
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
static MachineOperand CreateImm(int64_t Val)
unsigned getReg() const
getReg - Returns the register number.
LLVM Value Representation.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
static bool IsBR_JT(unsigned BrOpc)
static bool isZeroImm(const MachineOperand &op)
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
unsigned getConstantPoolIndex(const Constant *C, unsigned Alignment)
getConstantPoolIndex - Create a new entry in the constant pool or return an existing one...
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly. ...