31 #define DEBUG_TYPE "regalloc"
33 STATISTIC(NumFinished,
"Number of splits finished");
34 STATISTIC(NumSimple,
"Number of splits that were simple");
35 STATISTIC(NumCopies,
"Number of copies inserted for splitting");
36 STATISTIC(NumRemats,
"Number of rematerialized defs for splitting");
37 STATISTIC(NumRepairs,
"Number of invalid live ranges repaired");
45 : MF(vrm.getMachineFunction()), VRM(vrm), LIS(lis),
Loops(mli),
46 TII(*MF.getSubtarget().getInstrInfo()), CurLI(nullptr),
47 LastSplitPoint(MF.getNumBlockIDs()) {}
52 ThroughBlocks.
clear();
54 DidRepairRange =
false;
57 SlotIndex SplitAnalysis::computeLastSplitPoint(
unsigned Num) {
60 std::pair<SlotIndex, SlotIndex> &LSP = LastSplitPoint[Num];
65 if (!LSP.first.isValid()) {
67 if (FirstTerm == MBB->
end())
76 LSP.second = LSP.first;
118 void SplitAnalysis::analyzeUses() {
119 assert(UseSlots.empty() &&
"Call clear first");
125 UseSlots.push_back(VNI->
def);
137 UseSlots.erase(std::unique(UseSlots.begin(), UseSlots.end(),
142 if (!calcLiveBlockInfo()) {
145 DidRepairRange =
true;
147 DEBUG(
dbgs() <<
"*** Fixing inconsistent live interval! ***\n");
149 .shrinkToUses(const_cast<LiveInterval*>(CurLI));
151 ThroughBlocks.
clear();
152 bool fixed = calcLiveBlockInfo();
154 assert(fixed &&
"Couldn't fix broken live interval");
158 << UseSlots.size() <<
" instrs in "
159 << UseBlocks.size() <<
" blocks, through "
160 << NumThroughBlocks <<
" blocks.\n");
165 bool SplitAnalysis::calcLiveBlockInfo() {
167 NumThroughBlocks = NumGapBlocks = 0;
175 UseI = UseSlots.begin();
176 UseE = UseSlots.end();
189 if (UseI == UseE || *UseI >= Stop) {
191 ThroughBlocks.
set(BI.MBB->getNumber());
198 BI.FirstInstr = *UseI;
199 assert(BI.FirstInstr >= Start);
201 while (UseI != UseE && *UseI < Stop);
202 BI.LastInstr = UseI[-1];
203 assert(BI.LastInstr < Stop);
206 BI.LiveIn = LVI->start <= Start;
210 assert(LVI->start == LVI->valno->def &&
"Dangling Segment start");
211 assert(LVI->start == BI.FirstInstr &&
"First instr should be a def");
212 BI.FirstDef = BI.FirstInstr;
217 while (LVI->end < Stop) {
219 if (++LVI == LVE || LVI->start >= Stop) {
221 BI.LastInstr = LastStop;
225 if (LastStop < LVI->start) {
232 UseBlocks.push_back(BI);
233 UseBlocks.back().LastInstr = LastStop;
238 BI.FirstInstr = BI.FirstDef = LVI->start;
242 assert(LVI->start == LVI->valno->def &&
"Dangling Segment start");
244 BI.FirstDef = LVI->start;
247 UseBlocks.push_back(BI);
255 if (LVI->end == Stop && ++LVI == LVE)
259 if (LVI->start < Stop)
288 }
while (Stop <= LVI->start);
295 assert(!Orig.
empty() &&
"Splitting empty interval?");
299 if (I != Orig.
end() && I->start <= Idx)
300 return I->start == Idx;
303 return I != Orig.
begin() && (--
I)->
end == Idx;
321 : SA(sa), LIS(lis), VRM(vrm), MRI(vrm.getMachineFunction().getRegInfo()),
322 MDT(mdt),
TII(*vrm.getMachineFunction().getSubtarget().getInstrInfo()),
323 TRI(*vrm.getMachineFunction().getSubtarget().getRegisterInfo()),
324 MBFI(mbfi), Edit(nullptr), OpenIdx(0), SpillMode(SM_Partition),
325 RegAssign(Allocator) {}
346 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
348 if (RegAssign.
empty()) {
349 dbgs() <<
" empty\n";
354 dbgs() <<
" [" <<
I.start() <<
';' <<
I.stop() <<
"):" <<
I.value();
359 VNInfo *SplitEditor::defValue(
unsigned RegIdx,
362 assert(ParentVNI &&
"Mapping NULL value");
363 assert(Idx.
isValid() &&
"Invalid SlotIndex");
371 std::pair<ValueMap::iterator, bool> InsP =
372 Values.
insert(std::make_pair(std::make_pair(RegIdx, ParentVNI->
id),
373 ValueForcePair(VNI,
false)));
381 if (
VNInfo *OldVNI = InsP.first->second.getPointer()) {
385 InsP.first->second = ValueForcePair();
390 LI->addSegment(LiveInterval::Segment(Def, Def.
getDeadSlot(), VNI));
395 void SplitEditor::forceRecompute(
unsigned RegIdx,
const VNInfo *ParentVNI) {
396 assert(ParentVNI &&
"Mapping NULL value");
397 ValueForcePair &VFP = Values[std::make_pair(RegIdx, ParentVNI->
id)];
398 VNInfo *VNI = VFP.getPointer();
413 VFP = ValueForcePair(
nullptr,
true);
416 VNInfo *SplitEditor::defFromParent(
unsigned RegIdx,
427 bool Late = RegIdx != 0;
444 return defValue(RegIdx, ParentVNI, Def);
454 OpenIdx = Edit->
size();
460 assert(Idx != 0 &&
"Cannot select the complement interval");
461 assert(Idx < Edit->
size() &&
"Can only select previously opened interval");
462 DEBUG(
dbgs() <<
" selectIntv " << OpenIdx <<
" -> " << Idx <<
'\n');
467 assert(OpenIdx &&
"openIntv not called before enterIntvBefore");
468 DEBUG(
dbgs() <<
" enterIntvBefore " << Idx);
475 DEBUG(
dbgs() <<
": valno " << ParentVNI->
id <<
'\n');
477 assert(MI &&
"enterIntvBefore called with invalid index");
484 assert(OpenIdx &&
"openIntv not called before enterIntvAfter");
485 DEBUG(
dbgs() <<
" enterIntvAfter " << Idx);
492 DEBUG(
dbgs() <<
": valno " << ParentVNI->
id <<
'\n');
494 assert(MI &&
"enterIntvAfter called with invalid index");
502 assert(OpenIdx &&
"openIntv not called before enterIntvAtEnd");
511 DEBUG(
dbgs() <<
": valno " << ParentVNI->id);
512 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Last, MBB,
514 RegAssign.
insert(VNI->
def, End, OpenIdx);
525 assert(OpenIdx &&
"openIntv not called before useIntv");
526 DEBUG(
dbgs() <<
" useIntv [" << Start <<
';' << End <<
"):");
527 RegAssign.
insert(Start, End, OpenIdx);
532 assert(OpenIdx &&
"openIntv not called before leaveIntvAfter");
533 DEBUG(
dbgs() <<
" leaveIntvAfter " << Idx);
542 DEBUG(
dbgs() <<
": valno " << ParentVNI->
id <<
'\n');
544 assert(MI &&
"No instruction at index");
552 forceRecompute(0, ParentVNI);
553 defFromParent(0, ParentVNI, Idx, *MI->
getParent(),
MI);
563 assert(OpenIdx &&
"openIntv not called before leaveIntvBefore");
564 DEBUG(
dbgs() <<
" leaveIntvBefore " << Idx);
573 DEBUG(
dbgs() <<
": valno " << ParentVNI->
id <<
'\n');
576 assert(MI &&
"No instruction at index");
582 assert(OpenIdx &&
"openIntv not called before leaveIntvAtTop");
592 VNInfo *VNI = defFromParent(0, ParentVNI, Start, MBB,
594 RegAssign.
insert(Start, VNI->
def, OpenIdx);
600 assert(OpenIdx &&
"openIntv not called before overlapIntv");
603 "Parent changes value in extended range");
605 "Range cannot span basic blocks");
609 forceRecompute(0, ParentVNI);
610 DEBUG(
dbgs() <<
" overlapIntv [" << Start <<
';' << End <<
"):");
611 RegAssign.
insert(Start, End, OpenIdx);
621 DEBUG(
dbgs() <<
"Removing " << Copies.
size() <<
" back-copies.\n");
623 AssignI.setMap(RegAssign);
625 for (
unsigned i = 0, e = Copies.
size(); i != e; ++i) {
628 assert(MI &&
"No instruction for back-copy");
633 do AtBegin = MBBI == MBB->
begin();
634 while (!AtBegin && (--MBBI)->isDebugValue());
636 DEBUG(
dbgs() <<
"Removing " << Def <<
'\t' << *MI);
644 if (!AssignI.valid() || AssignI.start() >=
Def)
647 if (AssignI.stop() !=
Def)
649 unsigned RegIdx = AssignI.value();
650 if (AtBegin || !MBBI->readsVirtualRegister(Edit->
getReg())) {
651 DEBUG(
dbgs() <<
" cannot find simple kill of RegIdx " << RegIdx <<
'\n');
655 DEBUG(
dbgs() <<
" move kill to " << Kill <<
'\t' << *MBBI);
656 AssignI.setStop(Kill);
666 assert(MDT.
dominates(DefMBB, MBB) &&
"MBB must be dominated by the def.");
669 const MachineLoop *DefLoop = Loops.getLoopFor(DefMBB);
674 unsigned BestDepth = UINT_MAX;
688 if (Loop == DefLoop) {
690 << MBB->
getNumber() <<
" in the same loop\n");
696 if (Depth < BestDepth) {
700 << MBB->
getNumber() <<
" at depth " << Depth <<
'\n');
708 if (!IDom || !MDT.
dominates(DefDomNode, IDom))
715 void SplitEditor::hoistCopiesForSize() {
722 typedef std::pair<MachineBasicBlock*, SlotIndex> DomPair;
731 assert(ParentVNI &&
"Parent not live at complement def");
739 DomPair &Dom = NearestDom[ParentVNI->
id];
744 if (VNI->
def == ParentVNI->
def) {
745 DEBUG(
dbgs() <<
"Direct complement def at " << VNI->
def <<
'\n');
746 Dom = DomPair(ValMBB, VNI->
def);
752 DEBUG(
dbgs() <<
"Single complement def at " << VNI->
def <<
'\n');
758 Dom = DomPair(ValMBB, VNI->
def);
759 }
else if (Dom.first == ValMBB) {
761 if (!Dom.second.isValid() || VNI->
def < Dom.second)
762 Dom.second = VNI->
def;
769 Dom = DomPair(ValMBB, VNI->
def);
770 else if (Near != Dom.first)
775 DEBUG(
dbgs() <<
"Multi-mapped complement " << VNI->
id <<
'@' << VNI->
def
776 <<
" for parent " << ParentVNI->
id <<
'@' << ParentVNI->
def
777 <<
" hoist to BB#" << Dom.first->getNumber() <<
' '
778 << Dom.second <<
'\n');
782 for (
unsigned i = 0, e = Parent->
getNumValNums(); i != e; ++i) {
783 DomPair &Dom = NearestDom[i];
784 if (!Dom.first || Dom.second.isValid())
790 Dom.first = findShallowDominator(Dom.first, DefMBB);
793 defFromParent(0, ParentVNI, Last, *Dom.first,
804 const DomPair &Dom = NearestDom[ParentVNI->
id];
805 if (!Dom.first || Dom.second == VNI->
def)
808 forceRecompute(0, ParentVNI);
810 removeBackCopies(BackCopies);
816 bool SplitEditor::transferValues() {
821 VNInfo *ParentVNI = S.valno;
824 AssignI.advanceTo(Start);
828 if (!AssignI.valid()) {
830 }
else if (AssignI.start() <= Start) {
831 RegIdx = AssignI.value();
832 if (AssignI.stop() < End) {
833 End = AssignI.stop();
838 End =
std::min(End, AssignI.start());
842 DEBUG(
dbgs() <<
" [" << Start <<
';' << End <<
")=" << RegIdx);
846 ValueForcePair VFP = Values.
lookup(std::make_pair(RegIdx, ParentVNI->
id));
847 if (
VNInfo *VNI = VFP.getPointer()) {
849 LR.
addSegment(LiveInterval::Segment(Start, End, VNI));
872 if (Start != BlockStart) {
874 assert(VNI &&
"Missing def for complex mapped value");
875 DEBUG(
dbgs() <<
':' << VNI->
id <<
"*BB#" << MBB->getNumber());
882 BlockStart = BlockEnd;
886 assert(Start <= BlockStart &&
"Expected live-in block");
887 while (BlockStart < End) {
888 DEBUG(
dbgs() <<
">BB#" << MBB->getNumber());
890 if (BlockStart == ParentVNI->
def) {
892 assert(ParentVNI->
isPHIDef() &&
"Non-phi defined at block start?");
894 assert(VNI &&
"Missing def for complex mapped parent PHI");
908 BlockStart = BlockEnd;
912 }
while (Start != S.end);
923 void SplitEditor::extendPHIKillRanges() {
926 if (PHIVNI->isUnused() || !PHIVNI->isPHIDef())
928 unsigned RegIdx = RegAssign.
lookup(PHIVNI->def);
933 PE = MBB->
pred_end(); PI != PE; ++PI) {
939 assert(RegAssign.
lookup(LastUse) == RegIdx &&
940 "Different register assignment in phi predecessor");
948 void SplitEditor::rewriteAssigned(
bool ExtendRanges) {
950 RE = MRI.
reg_end(); RI != RE;) {
969 unsigned RegIdx = RegAssign.
lookup(Idx);
973 << Idx <<
':' << RegIdx <<
'\t' << *
MI);
976 if (!ExtendRanges || MO.
isUndef())
995 void SplitEditor::deleteRematVictims() {
1004 assert(MI &&
"Missing instruction for dead def");
1010 DEBUG(
dbgs() <<
"All defs dead: " << *MI);
1031 unsigned RegIdx = RegAssign.
lookup(ParentVNI->
def);
1032 defValue(RegIdx, ParentVNI, ParentVNI->
def);
1037 for (
unsigned i = 0, e = Edit->
size(); i != e; ++i)
1038 forceRecompute(i, ParentVNI);
1042 switch (SpillMode) {
1047 hoistCopiesForSize();
1054 bool Skipped = transferValues();
1056 extendPHIKillRanges();
1061 rewriteAssigned(Skipped);
1065 deleteRematVictims();
1076 for (
unsigned i = 0, e = Edit->
size(); i != e; ++i)
1082 for (
unsigned i = 0, e = Edit->
size(); i != e; ++i) {
1085 unsigned NumComp = ConEQ.
Classify(li);
1088 DEBUG(
dbgs() <<
" " << NumComp <<
" components: " << *li <<
'\n');
1091 for (
unsigned j = 1; j != NumComp; ++j)
1102 assert(!LRMap || LRMap->
size() == Edit->
size());
1111 bool SingleInstrs)
const {
1157 unsigned IntvOut,
SlotIndex EnterAfter){
1161 DEBUG(
dbgs() <<
"BB#" << MBBNum <<
" [" << Start <<
';' << Stop
1162 <<
") intf " << LeaveBefore <<
'-' << EnterAfter
1163 <<
", live-through " << IntvIn <<
" -> " << IntvOut);
1165 assert((IntvIn || IntvOut) &&
"Use splitSingleBlock for isolated blocks");
1167 assert((!LeaveBefore || LeaveBefore < Stop) &&
"Interference after block");
1168 assert((!IntvIn || !LeaveBefore || LeaveBefore > Start) &&
"Impossible intf");
1169 assert((!EnterAfter || EnterAfter >= Start) &&
"Interference before block");
1182 assert((!LeaveBefore || Idx <= LeaveBefore) &&
"Interference");
1196 assert((!EnterAfter || Idx >= EnterAfter) &&
"Interference");
1201 if (IntvIn == IntvOut && !LeaveBefore && !EnterAfter) {
1202 DEBUG(
dbgs() <<
", straight through.\n");
1214 assert((!IntvOut || !EnterAfter || EnterAfter < LSP) &&
"Impossible intf");
1216 if (IntvIn != IntvOut && (!LeaveBefore || !EnterAfter ||
1218 DEBUG(
dbgs() <<
", switch avoiding interference.\n");
1226 if (LeaveBefore && LeaveBefore < LSP) {
1234 assert((!LeaveBefore || Idx <= LeaveBefore) &&
"Interference");
1235 assert((!EnterAfter || Idx >= EnterAfter) &&
"Interference");
1239 DEBUG(
dbgs() <<
", create local intv for interference.\n");
1245 assert(LeaveBefore <= EnterAfter &&
"Missed case");
1250 assert((!EnterAfter || Idx >= EnterAfter) &&
"Interference");
1255 assert((!LeaveBefore || Idx <= LeaveBefore) &&
"Interference");
1260 unsigned IntvIn,
SlotIndex LeaveBefore) {
1266 <<
", reg-in " << IntvIn <<
", leave before " << LeaveBefore
1267 << (BI.
LiveOut ?
", stack-out" :
", killed in block"));
1269 assert(IntvIn &&
"Must have register in");
1270 assert(BI.
LiveIn &&
"Must be live-in");
1271 assert((!LeaveBefore || LeaveBefore > Start) &&
"Bad interference");
1274 DEBUG(
dbgs() <<
" before interference.\n");
1299 DEBUG(
dbgs() <<
", spill after last use before interference.\n");
1303 assert((!LeaveBefore || Idx <= LeaveBefore) &&
"Interference");
1305 DEBUG(
dbgs() <<
", spill before last split point.\n");
1310 assert((!LeaveBefore || Idx <= LeaveBefore) &&
"Interference");
1320 DEBUG(
dbgs() <<
", creating local interval " << LocalIntv <<
".\n");
1333 assert((!LeaveBefore || From <= LeaveBefore) &&
"Interference");
1348 assert((!LeaveBefore || From <= LeaveBefore) &&
"Interference");
1352 unsigned IntvOut,
SlotIndex EnterAfter) {
1358 <<
", reg-out " << IntvOut <<
", enter after " << EnterAfter
1359 << (BI.
LiveIn ?
", stack-in" :
", defined in block"));
1363 assert(IntvOut &&
"Must have register out");
1364 assert(BI.
LiveOut &&
"Must be live-out");
1365 assert((!EnterAfter || EnterAfter < LSP) &&
"Bad interference");
1368 DEBUG(
dbgs() <<
" after interference.\n");
1380 DEBUG(
dbgs() <<
", reload after interference.\n");
1389 assert((!EnterAfter || Idx >= EnterAfter) &&
"Interference");
1396 DEBUG(
dbgs() <<
", interference overlaps uses.\n");
1405 assert((!EnterAfter || Idx >= EnterAfter) &&
"Interference");
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
void RenumberValues()
RenumberValues - Renumber all values in order of appearance and remove unused values.
ValT lookup(KeyT x, ValT NotFound=ValT()) const
lookup - Return the mapped value at x or NotFound.
void push_back(const T &Elt)
void extend(LiveRange &LR, SlotIndex Use, unsigned PhysReg=0)
Extend the live range of LR to reach Use.
const_iterator end(StringRef path)
Get end iterator over path.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
const_iterator begin() const
SlotIndex def
The index of the defining instruction.
STATISTIC(NumFunctions,"Total number of functions")
bool anyRematerializable(AliasAnalysis *)
anyRematerializable - Return true if any parent values may be rematerializable.
ValueT lookup(const KeyT &Val) const
lookup - Return the entry for the specified key, or a default constructed value if no such entry exis...
SlotIndex getBoundaryIndex() const
Returns the boundary index for associated with this index.
MachineFunction & getMachineFunction() const
void reset(LiveRangeEdit &, ComplementSpillMode=SM_Partition)
reset - Prepare for a new split.
int getNumber() const
getNumber - MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a M...
SlotIndex getBaseIndex() const
Returns the base index for associated with this index.
bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
SlotIndex getLastSplitPoint(unsigned Num)
getLastSplitPoint - Return the base index of the last valid split point in the basic block numbered N...
void setLiveOutValue(MachineBasicBlock *MBB, VNInfo *VNI)
setLiveOutValue - Indicate that VNI is live out from MBB.
LiveInterval - This class represents the liveness of a register, or stack slot.
iterator getFirstTerminator()
getFirstTerminator - returns an iterator to the first terminator instruction of this basic block...
SlotIndex getInstructionIndex(const MachineInstr *instr) const
Returns the base index of the given instruction.
SM_Speed - Overlap intervals to minimize the expected execution frequency of the inserted copies...
iterator advanceTo(iterator I, SlotIndex Pos)
advanceTo - Advance the specified iterator to point to the Segment containing the specified position...
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
SplitEditor(SplitAnalysis &SA, LiveIntervals &, VirtRegMap &, MachineDominatorTree &, MachineBlockFrequencyInfo &)
Create a new SplitEditor for editing the LiveInterval analyzed by SA.
SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const
Return the last index in the given basic block.
bool isLiveInToMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const
bool readsVirtualRegister(unsigned Reg) const
Return true if the MachineInstr reads the specified virtual register.
MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...
const MachineLoopInfo & Loops
ComplementSpillMode
ComplementSpillMode - Select how the complement live range should be created.
This represents a simple continuous liveness interval for a value.
SplitAnalysis(const VirtRegMap &vrm, const LiveIntervals &lis, const MachineLoopInfo &mli)
friend class const_iterator
SlotIndex enterIntvAtEnd(MachineBasicBlock &MBB)
enterIntvAtEnd - Enter the open interval at the end of MBB.
VNInfo - Value Number Information.
bool didRematerialize(const VNInfo *ParentVNI) const
didRematerialize - Return true if ParentVNI was rematerialized anywhere.
unsigned getNumValNums() const
void splitRegInBlock(const SplitAnalysis::BlockInfo &BI, unsigned IntvIn, SlotIndex LeaveBefore)
splitRegInBlock - Split CurLI in the given block such that it enters the block in IntvIn and leaves i...
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
BlockT * getHeader() const
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
This class represents the liveness of a register, stack slot, etc.
static bool isEarlierInstr(SlotIndex A, SlotIndex B)
isEarlierInstr - Return true if A refers to an instruction earlier than B.
COPY - Target-independent register copy.
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
void analyze(const LiveInterval *li)
analyze - set CurLI to the specified interval, and analyze how it may be split.
void clear()
clear - Clear all bits.
unsigned getNumBlockIDs() const
getNumBlockIDs - Return the number of MBB ID's allocated.
void splitSingleBlock(const SplitAnalysis::BlockInfo &BI)
splitSingleBlock - Split CurLI into a separate live interval around the uses in a single block...
const HexagonInstrInfo * TII
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
VNInfo::Allocator & getVNInfoAllocator()
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
SmallVectorImpl< unsigned >::const_iterator iterator
Iterator for accessing the new registers added by this edit.
Number of individual test Apply this number of consecutive mutations to each input exit after the first new interesting input is found the minimized corpus is saved into the first input directory Number of jobs to run If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
unsigned Classify(const LiveInterval *LI)
Classify - Classify the values in LI into connected components.
void overlapIntv(SlotIndex Start, SlotIndex End)
overlapIntv - Indicate that all instructions in range should use the open interval, but also let the complement interval be live.
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
unsigned openIntv()
Create a new virtual register and live interval.
bool isUnused() const
Returns true if this value is unused.
bool shouldSplitSingleBlock(const BlockInfo &BI, bool SingleInstrs) const
shouldSplitSingleBlock - Returns true if it would help to create a local live range for the instructi...
void Distribute(LiveInterval *LIV[], MachineRegisterInfo &MRI)
Distribute - Distribute values in LIV[0] into a separate LiveInterval for each connected component...
bool empty() const
empty - Return true when no intervals are mapped.
SlotIndex leaveIntvAfter(SlotIndex Idx)
leaveIntvAfter - Leave the open interval after the instruction at Idx.
void addLiveInBlock(LiveRange &LR, MachineDomTreeNode *DomNode, SlotIndex Kill=SlotIndex())
addLiveInBlock - Add a block with an unknown live-in value.
MachineBasicBlock::iterator getLastSplitPointIter(MachineBasicBlock *)
getLastSplitPointIter - Returns the last split point as an iterator.
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
iterator addSegment(Segment S)
Add the specified Segment to this range, merging segments as appropriate.
Base class for the actual dominator tree node.
bool isCopyLike() const
Return true if the instruction behaves like a copy.
void clear()
clear - Remove all entries.
const LiveIntervals & LIS
std::vector< MachineBasicBlock * >::iterator pred_iterator
void finish(SmallVectorImpl< unsigned > *LRMap=nullptr)
finish - after all the new live ranges have been created, compute the remaining live range...
MachineBasicBlock * findNearestCommonDominator(MachineBasicBlock *A, MachineBasicBlock *B)
findNearestCommonDominator - Find nearest common dominator basic block for basic block A and B...
VNInfo * extendInBlock(SlotIndex StartIdx, SlotIndex Use)
If this range is live before Use in the basic block that starts at StartIdx, extend it to be live up ...
SlotIndex LastInstr
Last instr accessing current reg.
unsigned get(unsigned idx) const
SlotIndex getPrevSlot() const
Returns the previous slot in the index list.
const MachineBasicBlock * getParent() const
bool isDebugValue() const
bool isEarlyClobber() const
void reset(const MachineFunction *MF, SlotIndexes *, MachineDominatorTree *, VNInfo::Allocator *)
reset - Prepare caches for a new set of non-overlapping live ranges.
bundle_iterator< MachineInstr, instr_iterator > iterator
void RemoveMachineInstrFromMaps(MachineInstr *MI)
void array_pod_sort(IteratorTy Start, IteratorTy End)
array_pod_sort - This sorts an array with the specified start and end extent.
SlotIndexes * getSlotIndexes() const
iterator SkipPHIsAndLabels(iterator I)
SkipPHIsAndLabels - Return the first instruction in MBB after I that is not a PHI or a label...
bool isValid() const
Returns true if this is a valid index.
void useIntv(const MachineBasicBlock &MBB)
useIntv - indicate that all instructions in MBB should use OpenLI.
bool isOneInstr() const
isOneInstr - Returns true when this BlockInfo describes a single instruction.
iterator_range< use_nodbg_iterator > use_nodbg_operands(unsigned Reg) const
unsigned getOriginal(unsigned VirtReg) const
getOriginal - Return the original virtual register that VirtReg descends from through splitting...
SM_Partition(Default) - Try to create the complement interval so it doesn't overlap any other interva...
SM_Size - Overlap intervals to minimize the number of inserted COPY instructions. ...
const MachineBasicBlock * getLandingPadSuccessor() const
getLandingPadSuccessor - If this block has a successor that is a landing pad, return it...
bool canRematerializeAt(Remat &RM, SlotIndex UseIdx, bool cheapAsAMove)
canRematerializeAt - Determine if ParentVNI can be rematerialized at UseIdx.
LiveInterval & getParent() const
SlotIndex leaveIntvAtTop(MachineBasicBlock &MBB)
leaveIntvAtTop - Leave the interval at the top of MBB.
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
unsigned getSubReg() const
void selectIntv(unsigned Idx)
selectIntv - Select a previously opened interval index.
pred_iterator pred_begin()
bool liveAt(SlotIndex index) const
bool isPHIDef() const
Returns true if this value is defined by a PHI instruction (or was, PHI instructions may have been el...
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
void insert(KeyT a, KeyT b, ValT y)
insert - Add a mapping of [a;b] to y, coalesce with adjacent intervals.
void splitRegOutBlock(const SplitAnalysis::BlockInfo &BI, unsigned IntvOut, SlotIndex EnterAfter)
splitRegOutBlock - Split CurLI in the given block such that it enters the block on the stack (or isn'...
iterator find(SlotIndex Pos)
find - Return an iterator pointing to the first segment that ends after Pos, or end().
unsigned id
The ID number of this value.
PointerTy getPointer() const
Segments::const_iterator const_iterator
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
const MachineFunction & MF
unsigned getNumLiveBlocks() const
getNumLiveBlocks - Return the number of blocks where CurLI is live.
SlotIndex FirstInstr
First instr accessing current reg.
SlotIndex leaveIntvBefore(SlotIndex Idx)
leaveIntvBefore - Leave the open interval before the instruction at Idx.
ConnectedVNInfoEqClasses - Helper class that can divide VNInfos in a LiveInterval into equivalence cl...
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Additional information about basic blocks where the current variable is live.
MachineBasicBlock * getBlockNumbered(unsigned N) const
getBlockNumbered - MachineBasicBlocks are automatically numbered when they are inserted into the mach...
SplitAnalysis - Analyze a LiveInterval, looking for live range splitting opportunities.
LiveInterval & getInterval(unsigned Reg)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
bool LiveOut
Current reg is live out.
VNInfo * getValNumInfo(unsigned ValNo)
getValNumInfo - Returns pointer to the specified val#.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
void clear()
clear - clear all data structures so SplitAnalysis is ready to analyze a new interval.
Representation of each machine instruction.
void splitLiveThroughBlock(unsigned MBBNum, unsigned IntvIn, SlotIndex LeaveBefore, unsigned IntvOut, SlotIndex EnterAfter)
splitLiveThroughBlock - Split CurLI in the given block such that it enters the block in IntvIn and le...
bundle_iterator< const MachineInstr, const_instr_iterator > const_iterator
SlotIndex rematerializeAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, const Remat &RM, const TargetRegisterInfo &, bool Late=false)
rematerializeAt - Rematerialize RM.ParentVNI into DestReg by inserting an instruction into MBB before...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
void setReg(unsigned Reg)
Change the register this operand corresponds to.
SlotIndex enterIntvBefore(SlotIndex Idx)
enterIntvBefore - Enter the open interval before the instruction at Idx.
Remat - Information needed to rematerialize at a specific location.
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def...
void eliminateDeadDefs(SmallVectorImpl< MachineInstr * > &Dead, ArrayRef< unsigned > RegsBeingSpilled=None)
eliminateDeadDefs - Try to delete machine instructions that are now dead (allDefsAreDead returns true...
unsigned countLiveBlocks(const LiveInterval *li) const
countLiveBlocks - Return the number of blocks where li is live.
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
LiveInterval & createEmptyInterval()
create - Create a new register with the same class and original slot as parent.
BasicBlockListType::iterator iterator
SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const
Return the first index in the given basic block.
void calculateRegClassAndHint(MachineFunction &, const MachineLoopInfo &, const MachineBlockFrequencyInfo &)
calculateRegClassAndHint - Recompute register class and hint for each new register.
reg_iterator reg_begin(unsigned RegNo) const
SlotIndex enterIntvAfter(SlotIndex Idx)
enterIntvAfter - Enter the open interval after the instruction at Idx.
SlotIndex getNextSlot() const
Returns the next slot in the index list.
static reg_iterator reg_end()
bool LiveIn
Current reg is live in.
bool dominates(const MachineDomTreeNode *A, const MachineDomTreeNode *B) const
SlotIndex - An opaque wrapper around machine indexes.
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
void dump() const
dump - print the current interval mapping to dbgs().
SlotIndex insertMachineInstrInMaps(MachineInstr *mi, bool Late=false)
Insert the given machine instruction into the mapping.
unsigned getLoopDepth() const
getLoopDepth - Return the nesting level of this loop.
void calculateValues()
calculateValues - Calculate the value that will be live-in to each block added with addLiveInBlock...
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
bool isOriginalEndpoint(SlotIndex Idx) const
isOriginalEndpoint - Return true if the original live range was killed or (re-)defined at Idx...
VNInfo * getVNInfoBefore(SlotIndex Idx) const
getVNInfoBefore - Return the VNInfo that is live up to but not necessarilly including Idx...
void removeVRegDefAt(LiveInterval &LI, SlotIndex Pos)
Remove value number and related live segments of LI and its subranges that start at position Pos...
const std::pair< SlotIndex, SlotIndex > & getMBBRange(unsigned Num) const
Return the (start,end) range of the given basic block number.