33 #define DEBUG_TYPE "mccodeemitter"
35 STATISTIC(MCNumEmitted,
"Number of MC instructions emitted.");
36 STATISTIC(MCNumCPRelocations,
"Number of constant pool relocations created.");
40 ARMMCCodeEmitter(
const ARMMCCodeEmitter &) =
delete;
41 void operator=(
const ARMMCCodeEmitter &) =
delete;
48 : MCII(mcii), CTX(ctx), IsLittleEndian(IsLittle) {
51 ~ARMMCCodeEmitter()
override {}
64 unsigned getMachineSoImmOpValue(
unsigned SoImm)
const;
68 uint64_t getBinaryCodeForInstr(
const MCInst &
MI,
81 uint32_t getHiLo16ImmOpValue(
const MCInst &
MI,
unsigned OpIdx,
85 bool EncodeAddrModeOpValues(
const MCInst &
MI,
unsigned OpIdx,
86 unsigned &
Reg,
unsigned &Imm,
92 uint32_t getThumbBLTargetOpValue(
const MCInst &
MI,
unsigned OpIdx,
98 uint32_t getThumbBLXTargetOpValue(
const MCInst &
MI,
unsigned OpIdx,
103 uint32_t getThumbBRTargetOpValue(
const MCInst &
MI,
unsigned OpIdx,
108 uint32_t getThumbBCCTargetOpValue(
const MCInst &
MI,
unsigned OpIdx,
113 uint32_t getThumbCBTargetOpValue(
const MCInst &
MI,
unsigned OpIdx,
125 uint32_t getUnconditionalBranchTargetOpValue(
const MCInst &
MI,
unsigned OpIdx,
131 uint32_t getARMBranchTargetOpValue(
const MCInst &
MI,
unsigned OpIdx,
134 uint32_t getARMBLTargetOpValue(
const MCInst &
MI,
unsigned OpIdx,
137 uint32_t getARMBLXTargetOpValue(
const MCInst &
MI,
unsigned OpIdx,
143 uint32_t getAdrLabelOpValue(
const MCInst &
MI,
unsigned OpIdx,
146 uint32_t getThumbAdrLabelOpValue(
const MCInst &
MI,
unsigned OpIdx,
149 uint32_t getT2AdrLabelOpValue(
const MCInst &
MI,
unsigned OpIdx,
156 uint32_t getAddrModeImm12OpValue(
const MCInst &
MI,
unsigned OpIdx,
161 uint32_t getThumbAddrModeRegRegOpValue(
const MCInst &
MI,
unsigned OpIdx,
167 uint32_t getT2AddrModeImm8s4OpValue(
const MCInst &
MI,
unsigned OpIdx,
173 uint32_t getT2AddrModeImm0_1020s4OpValue(
const MCInst &
MI,
unsigned OpIdx,
179 uint32_t getT2Imm8s4OpValue(
const MCInst &
MI,
unsigned OpIdx,
186 uint32_t getLdStSORegOpValue(
const MCInst &
MI,
unsigned OpIdx,
191 uint32_t getLdStmModeOpValue(
const MCInst &
MI,
unsigned OpIdx,
218 uint32_t getAddrMode2OpValue(
const MCInst &MI,
unsigned OpIdx,
223 uint32_t getAddrMode2OffsetOpValue(
const MCInst &MI,
unsigned OpIdx,
228 uint32_t getPostIdxRegOpValue(
const MCInst &MI,
unsigned OpIdx,
233 uint32_t getAddrMode3OffsetOpValue(
const MCInst &MI,
unsigned OpIdx,
238 uint32_t getAddrMode3OpValue(
const MCInst &MI,
unsigned OpIdx,
244 uint32_t getAddrModeThumbSPOpValue(
const MCInst &MI,
unsigned OpIdx,
249 uint32_t getAddrModeISOpValue(
const MCInst &MI,
unsigned OpIdx,
254 uint32_t getAddrModePCOpValue(
const MCInst &MI,
unsigned OpIdx,
259 uint32_t getAddrMode5OpValue(
const MCInst &MI,
unsigned OpIdx,
264 unsigned getCCOutOpValue(
const MCInst &MI,
unsigned Op,
273 unsigned getSOImmOpValue(
const MCInst &MI,
unsigned Op,
294 unsigned SoImm = MO.
getImm();
296 assert(SoImmVal != -1 &&
"Not a valid so_imm value!");
307 unsigned getModImmOpValue(
const MCInst &MI,
unsigned Op,
330 unsigned getT2SOImmOpValue(
const MCInst &MI,
unsigned Op,
335 assert(Encoded != ~0U &&
"Not a Thumb2 so_imm value?");
339 unsigned getT2AddrModeSORegOpValue(
const MCInst &MI,
unsigned OpNum,
342 unsigned getT2AddrModeImm8OpValue(
const MCInst &MI,
unsigned OpNum,
345 unsigned getT2AddrModeImm8OffsetOpValue(
const MCInst &MI,
unsigned OpNum,
348 unsigned getT2AddrModeImm12OffsetOpValue(
const MCInst &MI,
unsigned OpNum,
353 unsigned getSORegRegOpValue(
const MCInst &MI,
unsigned Op,
356 unsigned getSORegImmOpValue(
const MCInst &MI,
unsigned Op,
359 unsigned getT2SORegOpValue(
const MCInst &MI,
unsigned Op,
363 unsigned getNEONVcvtImm32OpValue(
const MCInst &MI,
unsigned Op,
369 unsigned getBitfieldInvertedMaskOpValue(
const MCInst &MI,
unsigned Op,
373 unsigned getRegisterListOpValue(
const MCInst &MI,
unsigned Op,
376 unsigned getAddrMode6AddressOpValue(
const MCInst &MI,
unsigned Op,
379 unsigned getAddrMode6OneLane32AddressOpValue(
const MCInst &MI,
unsigned Op,
382 unsigned getAddrMode6DupAddressOpValue(
const MCInst &MI,
unsigned Op,
385 unsigned getAddrMode6OffsetOpValue(
const MCInst &MI,
unsigned Op,
389 unsigned getShiftRight8Imm(
const MCInst &MI,
unsigned Op,
392 unsigned getShiftRight16Imm(
const MCInst &MI,
unsigned Op,
395 unsigned getShiftRight32Imm(
const MCInst &MI,
unsigned Op,
398 unsigned getShiftRight64Imm(
const MCInst &MI,
unsigned Op,
402 unsigned getThumbSRImmOpValue(
const MCInst &MI,
unsigned Op,
406 unsigned NEONThumb2DataIPostEncoder(
const MCInst &MI,
407 unsigned EncodedValue,
409 unsigned NEONThumb2LoadStorePostEncoder(
const MCInst &MI,
410 unsigned EncodedValue,
412 unsigned NEONThumb2DupPostEncoder(
const MCInst &MI,
413 unsigned EncodedValue,
415 unsigned NEONThumb2V8PostEncoder(
const MCInst &MI,
416 unsigned EncodedValue,
419 unsigned VFPThumb2PostEncoder(
const MCInst &MI,
420 unsigned EncodedValue,
427 void EmitConstant(uint64_t Val,
unsigned Size,
raw_ostream &OS)
const {
429 for (
unsigned i = 0; i != Size; ++i) {
430 unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
431 EmitByte((Val >> Shift) & 0xff, OS);
445 return new ARMMCCodeEmitter(MCII, Ctx,
true);
451 return new ARMMCCodeEmitter(MCII, Ctx,
false);
457 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(
const MCInst &MI,
458 unsigned EncodedValue,
464 unsigned Bit24 = EncodedValue & 0x01000000;
465 unsigned Bit28 = Bit24 << 4;
466 EncodedValue &= 0xEFFFFFFF;
467 EncodedValue |= Bit28;
468 EncodedValue |= 0x0F000000;
477 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(
const MCInst &MI,
478 unsigned EncodedValue,
481 EncodedValue &= 0xF0FFFFFF;
482 EncodedValue |= 0x09000000;
491 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(
const MCInst &MI,
492 unsigned EncodedValue,
495 EncodedValue &= 0x00FFFFFF;
496 EncodedValue |= 0xEE000000;
504 unsigned ARMMCCodeEmitter::NEONThumb2V8PostEncoder(
const MCInst &MI,
505 unsigned EncodedValue,
508 EncodedValue |= 0xC000000;
516 unsigned ARMMCCodeEmitter::
517 VFPThumb2PostEncoder(
const MCInst &MI,
unsigned EncodedValue,
520 EncodedValue &= 0x0FFFFFFF;
521 EncodedValue |= 0xE0000000;
528 unsigned ARMMCCodeEmitter::
534 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
540 case ARM::Q0:
case ARM::Q1:
case ARM::Q2:
case ARM::Q3:
541 case ARM::Q4:
case ARM::Q5:
case ARM::Q6:
case ARM::Q7:
542 case ARM::Q8:
case ARM::Q9:
case ARM::Q10:
case ARM::Q11:
543 case ARM::Q12:
case ARM::Q13:
case ARM::Q14:
case ARM::Q15:
546 }
else if (MO.
isImm()) {
547 return static_cast<unsigned>(MO.
getImm());
550 .bitcastToAPInt().getHiBits(32).getLimitedValue());
557 bool ARMMCCodeEmitter::
558 EncodeAddrModeOpValues(
const MCInst &MI,
unsigned OpIdx,
unsigned &Reg,
564 Reg = CTX.getRegisterInfo()->getEncodingValue(MO.
getReg());
566 int32_t SImm = MO1.
getImm();
570 if (SImm == INT32_MIN) {
595 assert(MO.
isExpr() &&
"Unexpected branch target type!");
608 uint32_t S = (offset & 0x800000) >> 23;
609 uint32_t J1 = (offset & 0x400000) >> 22;
610 uint32_t J2 = (offset & 0x200000) >> 21;
624 uint32_t ARMMCCodeEmitter::
625 getThumbBLTargetOpValue(
const MCInst &MI,
unsigned OpIdx,
637 uint32_t ARMMCCodeEmitter::
638 getThumbBLXTargetOpValue(
const MCInst &MI,
unsigned OpIdx,
649 uint32_t ARMMCCodeEmitter::
650 getThumbBRTargetOpValue(
const MCInst &MI,
unsigned OpIdx,
657 return (MO.
getImm() >> 1);
661 uint32_t ARMMCCodeEmitter::
662 getThumbBCCTargetOpValue(
const MCInst &MI,
unsigned OpIdx,
669 return (MO.
getImm() >> 1);
673 uint32_t ARMMCCodeEmitter::
674 getThumbCBTargetOpValue(
const MCInst &MI,
unsigned OpIdx,
680 return (MO.
getImm() >> 1);
687 for (
int i = 0; i < NumOp-1; ++i) {
711 return getARMBranchTargetOpValue(MI, OpIdx, Fixups, STI);
716 uint32_t ARMMCCodeEmitter::
717 getARMBranchTargetOpValue(
const MCInst &MI,
unsigned OpIdx,
732 uint32_t ARMMCCodeEmitter::
733 getARMBLTargetOpValue(
const MCInst &MI,
unsigned OpIdx,
747 uint32_t ARMMCCodeEmitter::
748 getARMBLXTargetOpValue(
const MCInst &MI,
unsigned OpIdx,
760 uint32_t ARMMCCodeEmitter::
761 getUnconditionalBranchTargetOpValue(
const MCInst &MI,
unsigned OpIdx,
772 bool I = (Val & 0x800000);
773 bool J1 = (Val & 0x400000);
774 bool J2 = (Val & 0x200000);
790 uint32_t ARMMCCodeEmitter::
791 getAdrLabelOpValue(
const MCInst &MI,
unsigned OpIdx,
798 int64_t offset = MO.
getImm();
799 uint32_t Val = 0x2000;
802 if (offset == INT32_MIN) {
805 }
else if (offset < 0) {
823 assert(SoImmVal != -1 &&
"Not a valid so_imm value!");
831 uint32_t ARMMCCodeEmitter::
832 getT2AdrLabelOpValue(
const MCInst &MI,
unsigned OpIdx,
839 int32_t Val = MO.
getImm();
840 if (Val == INT32_MIN)
851 uint32_t ARMMCCodeEmitter::
852 getThumbAdrLabelOpValue(
const MCInst &MI,
unsigned OpIdx,
864 uint32_t ARMMCCodeEmitter::
865 getThumbAddrModeRegRegOpValue(
const MCInst &MI,
unsigned OpIdx,
873 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.
getReg());
874 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.
getReg());
875 return (Rm << 3) | Rn;
879 uint32_t ARMMCCodeEmitter::
880 getAddrModeImm12OpValue(
const MCInst &MI,
unsigned OpIdx,
891 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);
905 ++MCNumCPRelocations;
908 int32_t Offset = MO.
getImm();
909 if (Offset == INT32_MIN) {
912 }
else if (Offset < 0) {
919 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI);
921 uint32_t Binary = Imm12 & 0xfff;
925 Binary |= (Reg << 13);
931 uint32_t ARMMCCodeEmitter::
932 getT2Imm8s4OpValue(
const MCInst &MI,
unsigned OpIdx,
945 bool isAdd = Imm8 >= 0;
949 Imm8 = -(uint32_t)Imm8;
954 uint32_t Binary = Imm8 & 0xff;
963 uint32_t ARMMCCodeEmitter::
964 getT2AddrModeImm8s4OpValue(
const MCInst &MI,
unsigned OpIdx,
975 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);
979 assert(MO.
isExpr() &&
"Unexpected machine operand type!");
984 ++MCNumCPRelocations;
986 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
994 uint32_t Binary = (Imm8 >> 2) & 0xff;
998 Binary |= (Reg << 9);
1004 uint32_t ARMMCCodeEmitter::
1005 getT2AddrModeImm0_1020s4OpValue(
const MCInst &MI,
unsigned OpIdx,
1012 unsigned Reg = CTX.getRegisterInfo()->getEncodingValue(MO.
getReg());
1013 unsigned Imm8 = MO1.
getImm();
1014 return (Reg << 8) |
Imm8;
1018 ARMMCCodeEmitter::getHiLo16ImmOpValue(
const MCInst &MI,
unsigned OpIdx,
1026 return static_cast<unsigned>(MO.
getImm());
1032 const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E);
1036 const int64_t
Value = MCE->getValue();
1037 if (Value > UINT32_MAX)
1040 switch (ARM16Expr->
getKind()) {
1042 return (int32_t(Value) & 0xffff0000) >> 16;
1044 return (int32_t(Value) & 0x0000ffff);
1049 switch (ARM16Expr->
getKind()) {
1073 uint32_t ARMMCCodeEmitter::
1074 getLdStSORegOpValue(
const MCInst &MI,
unsigned OpIdx,
1080 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.
getReg());
1081 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.
getReg());
1085 unsigned SBits = getShiftOp(ShOp);
1089 assert((ShImm & ~0x1f) == 0 &&
"Out of range shift amount");
1098 uint32_t Binary = Rm;
1100 Binary |= SBits << 5;
1101 Binary |= ShImm << 7;
1107 uint32_t ARMMCCodeEmitter::
1108 getAddrMode2OpValue(
const MCInst &MI,
unsigned OpIdx,
1116 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.
getReg());
1117 uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups, STI);
1122 uint32_t ARMMCCodeEmitter::
1123 getAddrMode2OffsetOpValue(
const MCInst &MI,
unsigned OpIdx,
1131 unsigned Imm = MO1.
getImm();
1139 Binary |= getShiftOp(ShOp) << 5;
1140 Binary |= CTX.getRegisterInfo()->getEncodingValue(MO.
getReg());
1142 return Binary | (isAdd << 12) | (isReg << 13);
1145 uint32_t ARMMCCodeEmitter::
1146 getPostIdxRegOpValue(
const MCInst &MI,
unsigned OpIdx,
1153 bool isAdd = MO1.
getImm() != 0;
1154 return CTX.getRegisterInfo()->getEncodingValue(MO.
getReg()) | (isAdd << 4);
1157 uint32_t ARMMCCodeEmitter::
1158 getAddrMode3OffsetOpValue(
const MCInst &MI,
unsigned OpIdx,
1167 unsigned Imm = MO1.
getImm();
1169 bool isImm = MO.
getReg() == 0;
1173 Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO.
getReg());
1174 return Imm8 | (isAdd << 8) | (isImm << 9);
1177 uint32_t ARMMCCodeEmitter::
1178 getAddrMode3OpValue(
const MCInst &MI,
unsigned OpIdx,
1192 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);
1194 assert(MO.
isExpr() &&
"Unexpected machine operand type!");
1199 ++MCNumCPRelocations;
1200 return (Rn << 9) | (1 << 13);
1202 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.
getReg());
1203 unsigned Imm = MO2.
getImm();
1205 bool isImm = MO1.
getReg() == 0;
1209 Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO1.
getReg());
1210 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
1214 uint32_t ARMMCCodeEmitter::
1215 getAddrModeThumbSPOpValue(
const MCInst &MI,
unsigned OpIdx,
1222 "Unexpected base register!");
1226 return MO1.
getImm() & 0xff;
1230 uint32_t ARMMCCodeEmitter::
1231 getAddrModeISOpValue(
const MCInst &MI,
unsigned OpIdx,
1239 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.
getReg());
1240 unsigned Imm5 = MO1.
getImm();
1241 return ((Imm5 & 0x1f) << 3) | Rn;
1245 uint32_t ARMMCCodeEmitter::
1246 getAddrModePCOpValue(
const MCInst &MI,
unsigned OpIdx,
1252 return (MO.
getImm() >> 2);
1256 uint32_t ARMMCCodeEmitter::
1257 getAddrMode5OpValue(
const MCInst &MI,
unsigned OpIdx,
1268 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);
1272 assert(MO.
isExpr() &&
"Unexpected machine operand type!");
1281 ++MCNumCPRelocations;
1283 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1291 Binary |= (Reg << 9);
1295 unsigned ARMMCCodeEmitter::
1296 getSORegRegOpValue(
const MCInst &MI,
unsigned OpIdx,
1315 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.
getReg());
1319 unsigned Rs = MO1.
getReg();
1335 Binary |= SBits << 4;
1340 return Binary | (CTX.getRegisterInfo()->getEncodingValue(Rs) <<
ARMII::RegRsShift);
1343 unsigned ARMMCCodeEmitter::
1344 getSORegImmOpValue(
const MCInst &MI,
unsigned OpIdx,
1360 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.
getReg());
1383 Binary |= SBits << 4;
1385 assert(Offset < 32 &&
"Offset must be in range 0-31!");
1386 return Binary | (Offset << 7);
1390 unsigned ARMMCCodeEmitter::
1391 getT2AddrModeSORegOpValue(
const MCInst &MI,
unsigned OpNum,
1400 unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.
getReg());
1402 Value |= CTX.getRegisterInfo()->getEncodingValue(MO2.
getReg());
1409 unsigned ARMMCCodeEmitter::
1410 getT2AddrModeImm8OpValue(
const MCInst &MI,
unsigned OpNum,
1417 unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.
getReg());
1422 int32_t tmp = (int32_t)MO2.
getImm();
1431 unsigned ARMMCCodeEmitter::
1432 getT2AddrModeImm8OffsetOpValue(
const MCInst &MI,
unsigned OpNum,
1439 int32_t tmp = (int32_t)MO1.
getImm();
1448 unsigned ARMMCCodeEmitter::
1449 getT2AddrModeImm12OffsetOpValue(
const MCInst &MI,
unsigned OpNum,
1456 int32_t tmp = (int32_t)MO1.
getImm();
1461 Value |= tmp & 4095;
1465 unsigned ARMMCCodeEmitter::
1466 getT2SORegOpValue(
const MCInst &MI,
unsigned OpIdx,
1482 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.
getReg());
1500 Binary |= SBits << 4;
1508 unsigned ARMMCCodeEmitter::
1509 getBitfieldInvertedMaskOpValue(
const MCInst &MI,
unsigned Op,
1515 uint32_t v = ~MO.
getImm();
1518 assert (v != 0 && lsb < 32 && msb < 32 &&
"Illegal bitfield mask!");
1519 return lsb | (msb << 5);
1522 unsigned ARMMCCodeEmitter::
1523 getRegisterListOpValue(
const MCInst &MI,
unsigned Op,
1533 bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg);
1534 bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg);
1536 unsigned Binary = 0;
1538 if (SPRRegs || DPRRegs) {
1540 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
1542 Binary |= (RegNo & 0x1f) << 8;
1546 Binary |= NumRegs * 2;
1549 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(MI.
getOperand(I).
getReg());
1550 Binary |= 1 << RegNo;
1559 unsigned ARMMCCodeEmitter::
1560 getAddrMode6AddressOpValue(
const MCInst &MI,
unsigned Op,
1566 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.
getReg());
1573 case 8: Align = 0x01;
break;
1574 case 16: Align = 0x02;
break;
1575 case 32: Align = 0x03;
break;
1578 return RegNo | (Align << 4);
1583 unsigned ARMMCCodeEmitter::
1584 getAddrMode6OneLane32AddressOpValue(
const MCInst &MI,
unsigned Op,
1590 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.
getReg());
1598 case 2: Align = 0x00;
break;
1599 case 4: Align = 0x03;
break;
1602 return RegNo | (Align << 4);
1610 unsigned ARMMCCodeEmitter::
1611 getAddrMode6DupAddressOpValue(
const MCInst &MI,
unsigned Op,
1617 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.
getReg());
1624 case 8: Align = 0x01;
break;
1625 case 16: Align = 0x03;
break;
1628 return RegNo | (Align << 4);
1631 unsigned ARMMCCodeEmitter::
1632 getAddrMode6OffsetOpValue(
const MCInst &MI,
unsigned Op,
1636 if (MO.
getReg() == 0)
return 0x0D;
1637 return CTX.getRegisterInfo()->getEncodingValue(MO.
getReg());
1640 unsigned ARMMCCodeEmitter::
1641 getShiftRight8Imm(
const MCInst &MI,
unsigned Op,
1647 unsigned ARMMCCodeEmitter::
1648 getShiftRight16Imm(
const MCInst &MI,
unsigned Op,
1654 unsigned ARMMCCodeEmitter::
1655 getShiftRight32Imm(
const MCInst &MI,
unsigned Op,
1661 unsigned ARMMCCodeEmitter::
1662 getShiftRight64Imm(
const MCInst &MI,
unsigned Op,
1668 void ARMMCCodeEmitter::
1674 uint64_t TSFlags = Desc.
TSFlags;
1684 uint32_t Binary = getBinaryCodeForInstr(MI, Fixups, STI);
1687 if (
isThumb(STI) && Size == 4) {
1688 EmitConstant(Binary >> 16, 2, OS);
1689 EmitConstant(Binary & 0xffff, 2, OS);
1691 EmitConstant(Binary, Size, OS);
1695 #include "ARMGenMCCodeEmitter.inc"
static bool isReg(const MCInst &MI, unsigned OpNo)
void push_back(const T &Elt)
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
static unsigned char getAM3Offset(unsigned AM3Opc)
STATISTIC(NumFunctions,"Total number of functions")
Describe properties that are true of each instruction in the target description file.
VariantKind getKind() const
getOpcode - Get the kind of this expression.
std::size_t countLeadingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the most significant bit to the least stopping at the first 1...
static bool isThumb(const MCSubtargetInfo &STI)
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag=true)
Reports a serious error, calling any installed error handler.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Base class for the full range of assembler expressions which are needed for parsing.
Reg
All possible values of the reg field in the ModR/M byte.
const MCExpr * getSubExpr() const
getSubExpr - Get the child of this expression.
Context object for machine code objects.
unsigned getReg() const
Returns the register number.
static int getT2SOImmVal(unsigned Arg)
getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit into a Thumb-2 shifter_oper...
Instances of this class represent a single low-level machine instruction.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
static unsigned getSOImmValRot(unsigned Imm)
getSOImmValRot - Given an encoded imm field for the reg/imm form, return the rotate amount...
const MCExpr * getExpr() const
std::size_t countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the least significant bit to the most stopping at the first 1...
static unsigned char getAM5Offset(unsigned AM5Opc)
MCCodeEmitter - Generic instruction encoding interface.
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Interface to description of machine instruction set.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
static unsigned getSOImmValImm(unsigned Imm)
getSOImmValImm - Given an encoded imm field for the reg/imm form, return the 8-bit imm value...
This file declares a class to represent arbitrary precision floating point values and provide a varie...
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
static int32_t encodeThumbBLOffset(int32_t offset)
Triple - Helper class for working with autoconf configuration names.
static bool HasConditionalBranch(const MCInst &MI)
Return true if this branch has a non-always predication.
static AddrOpc getAM2Op(unsigned AM2Opc)
static unsigned getAM2Offset(unsigned AM2Opc)
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
unsigned getOpcode() const
static AddrOpc getAM3Op(unsigned AM3Opc)
static int getSOImmVal(unsigned Arg)
getSOImmVal - Given a 32-bit immediate, if it is something that can fit into an shifter_operand immed...
MCCodeEmitter * createARMLEMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
unsigned getNumOperands() const
APFloat abs(APFloat X)
Returns the absolute value of the argument.
MCSubtargetInfo - Generic base class for all target subtargets.
const Triple & getTargetTriple() const
getTargetTriple - Return the target triple string.
static AddrOpc getAM5Op(unsigned AM5Opc)
static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI)
getBranchTargetOpValue - Helper function to get the branch target operand, which is either an immedia...
const ARM::ArchExtKind Kind
static ShiftOpc getAM2ShiftOpc(unsigned AM2Opc)
LLVM Value Representation.
static unsigned getSORegOffset(unsigned Op)
This class implements an extremely fast bulk output stream that can only output to a stream...
Target specific expression.
Instances of this class represent operands of the MCInst class.
MCCodeEmitter * createARMBEMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
const MCOperand & getOperand(unsigned i) const
static ShiftOpc getSORegShOp(unsigned Op)