30 #define DEBUG_TYPE "mccodeemitter"
32 #define GET_INSTRMAP_INFO
33 #include "MipsGenInstrInfo.inc"
34 #undef GET_INSTRMAP_INFO
54 assert(Inst.
getNumOperands() == 3 &&
"Invalid no. of operands for shift!");
88 if (Opcode == Mips::DEXT)
90 "Invalid no. of machine operands for DEXT!");
93 "Invalid no. of machine operands for DINS!");
105 InstIn.
setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTU : Mips::DINSU);
109 assert(pos < 32 && "DEXT/DINS cannot have both size and pos > 32
");
110 InstIn.getOperand(3).setImm(size - 32);
111 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTM : Mips::DINSM);
115 bool MipsMCCodeEmitter::isMicroMips(const MCSubtargetInfo &STI) const {
116 return STI.getFeatureBits()[Mips::FeatureMicroMips];
119 bool MipsMCCodeEmitter::isMips32r6(const MCSubtargetInfo &STI) const {
120 return STI.getFeatureBits()[Mips::FeatureMips32r6];
123 void MipsMCCodeEmitter::EmitByte(unsigned char C, raw_ostream &OS) const {
127 void MipsMCCodeEmitter::EmitInstruction(uint64_t Val, unsigned Size,
128 const MCSubtargetInfo &STI,
129 raw_ostream &OS) const {
130 // Output the instruction encoding in little endian byte order.
131 // Little-endian byte ordering:
132 // mips32r2: 4 | 3 | 2 | 1
133 // microMIPS: 2 | 1 | 4 | 3
134 if (IsLittleEndian && Size == 4 && isMicroMips(STI)) {
135 EmitInstruction(Val >> 16, 2, STI, OS);
136 EmitInstruction(Val, 2, STI, OS);
138 for (unsigned i = 0; i < Size; ++i) {
139 unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
140 EmitByte((Val >> Shift) & 0xff, OS);
147 void MipsMCCodeEmitter::
148 encodeInstruction(const MCInst &MI, raw_ostream &OS,
149 SmallVectorImpl<MCFixup> &Fixups,
150 const MCSubtargetInfo &STI) const
153 // Non-pseudo instructions that get changed for direct object
154 // only based on operand values.
155 // If this list of instructions get much longer we will move
156 // the check to a function call. Until then, this is more efficient.
158 switch (MI.getOpcode()) {
159 // If shift amount is >= 32 it the inst needs to be lowered further
164 LowerLargeShift(TmpInst);
166 // Double extract instruction is chosen by pos and size operands
169 LowerDextDins(TmpInst);
172 unsigned long N = Fixups.size();
173 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
175 // Check for unimplemented opcodes.
176 // Unfortunately in MIPS both NOP and SLL will come in with Binary == 0
177 // so we have to special check for them.
178 unsigned Opcode = TmpInst.getOpcode();
179 if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) &&
180 (Opcode != Mips::SLL_MM) && !Binary)
181 llvm_unreachable("unimplemented opcode in encodeInstruction()
");
184 if (isMicroMips(STI)) {
185 if (isMips32r6(STI)) {
186 NewOpcode = Mips::MipsR62MicroMipsR6(Opcode, Mips::Arch_micromipsr6);
188 NewOpcode = Mips::Std2MicroMipsR6(Opcode, Mips::Arch_micromipsr6);
191 NewOpcode = Mips::Std2MicroMips(Opcode, Mips::Arch_micromips);
193 if (NewOpcode != -1) {
194 if (Fixups.size() > N)
198 TmpInst.setOpcode (NewOpcode);
199 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
203 const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
205 // Get byte count of instruction
206 unsigned Size = Desc.getSize();
208 llvm_unreachable("Desc.getSize() returns 0
");
210 EmitInstruction(Binary, Size, STI, OS);
216 unsigned MipsMCCodeEmitter::
217 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
218 SmallVectorImpl<MCFixup> &Fixups,
219 const MCSubtargetInfo &STI) const {
221 const MCOperand &MO = MI.getOperand(OpNo);
223 // If the destination is an immediate, divide by 4.
224 if (MO.isImm()) return MO.getImm() >> 2;
226 assert(MO.isExpr() &&
229 const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
230 MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
231 Fixups.push_back(MCFixup::create(0, FixupExpression,
232 MCFixupKind(Mips::fixup_Mips_PC16)));
239 unsigned MipsMCCodeEmitter::
240 getBranchTarget7OpValueMM(const MCInst &MI, unsigned OpNo,
241 SmallVectorImpl<MCFixup> &Fixups,
242 const MCSubtargetInfo &STI) const {
244 const MCOperand &MO = MI.getOperand(OpNo);
246 // If the destination is an immediate, divide by 2.
247 if (MO.isImm()) return MO.getImm() >> 1;
249 assert(MO.isExpr() &&
250 "getBranchTargetOpValueMM expects only expressions or immediates
");
252 const MCExpr *Expr = MO.getExpr();
253 Fixups.push_back(MCFixup::create(0, Expr,
254 MCFixupKind(Mips::fixup_MICROMIPS_PC7_S1)));
261 unsigned MipsMCCodeEmitter::
262 getBranchTargetOpValueMMPC10(const MCInst &MI, unsigned OpNo,
263 SmallVectorImpl<MCFixup> &Fixups,
264 const MCSubtargetInfo &STI) const {
266 const MCOperand &MO = MI.getOperand(OpNo);
268 // If the destination is an immediate, divide by 2.
269 if (MO.isImm()) return MO.getImm() >> 1;
271 assert(MO.isExpr() &&
272 "getBranchTargetOpValuePC10 expects only expressions or immediates
");
274 const MCExpr *Expr = MO.getExpr();
275 Fixups.push_back(MCFixup::create(0, Expr,
276 MCFixupKind(Mips::fixup_MICROMIPS_PC10_S1)));
283 unsigned MipsMCCodeEmitter::
284 getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
285 SmallVectorImpl<MCFixup> &Fixups,
286 const MCSubtargetInfo &STI) const {
288 const MCOperand &MO = MI.getOperand(OpNo);
290 // If the destination is an immediate, divide by 2.
291 if (MO.isImm()) return MO.getImm() >> 1;
293 assert(MO.isExpr() &&
294 "getBranchTargetOpValueMM expects only expressions or immediates
");
296 const MCExpr *Expr = MO.getExpr();
297 Fixups.push_back(MCFixup::create(0, Expr,
299 fixup_MICROMIPS_PC16_S1)));
306 unsigned MipsMCCodeEmitter::
307 getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo,
308 SmallVectorImpl<MCFixup> &Fixups,
309 const MCSubtargetInfo &STI) const {
311 const MCOperand &MO = MI.getOperand(OpNo);
313 // If the destination is an immediate, divide by 4.
314 if (MO.isImm()) return MO.getImm() >> 2;
316 assert(MO.isExpr() &&
317 "getBranchTarget21OpValue expects only expressions or immediates
");
319 const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
320 MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
321 Fixups.push_back(MCFixup::create(0, FixupExpression,
322 MCFixupKind(Mips::fixup_MIPS_PC21_S2)));
329 unsigned MipsMCCodeEmitter::
330 getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo,
331 SmallVectorImpl<MCFixup> &Fixups,
332 const MCSubtargetInfo &STI) const {
334 const MCOperand &MO = MI.getOperand(OpNo);
336 // If the destination is an immediate, divide by 4.
337 if (MO.isImm()) return MO.getImm() >> 2;
339 assert(MO.isExpr() &&
340 "getBranchTarget26OpValue expects only expressions or immediates
");
342 const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
343 MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
344 Fixups.push_back(MCFixup::create(0, FixupExpression,
345 MCFixupKind(Mips::fixup_MIPS_PC26_S2)));
352 unsigned MipsMCCodeEmitter::
353 getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo,
354 SmallVectorImpl<MCFixup> &Fixups,
355 const MCSubtargetInfo &STI) const {
357 const MCOperand &MO = MI.getOperand(OpNo);
359 if (MO.isImm()) return MO.getImm();
361 assert(MO.isExpr() &&
362 "getJumpOffset16OpValue expects only expressions or an immediate
");
371 unsigned MipsMCCodeEmitter::
372 getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
373 SmallVectorImpl<MCFixup> &Fixups,
374 const MCSubtargetInfo &STI) const {
376 const MCOperand &MO = MI.getOperand(OpNo);
377 // If the destination is an immediate, divide by 4.
378 if (MO.isImm()) return MO.getImm()>>2;
380 assert(MO.isExpr() &&
381 "getJumpTargetOpValue expects only expressions or an immediate
");
383 const MCExpr *Expr = MO.getExpr();
384 Fixups.push_back(MCFixup::create(0, Expr,
385 MCFixupKind(Mips::fixup_Mips_26)));
389 unsigned MipsMCCodeEmitter::
390 getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo,
391 SmallVectorImpl<MCFixup> &Fixups,
392 const MCSubtargetInfo &STI) const {
394 const MCOperand &MO = MI.getOperand(OpNo);
395 // If the destination is an immediate, divide by 2.
396 if (MO.isImm()) return MO.getImm() >> 1;
398 assert(MO.isExpr() &&
399 "getJumpTargetOpValueMM expects only expressions or an immediate
");
401 const MCExpr *Expr = MO.getExpr();
402 Fixups.push_back(MCFixup::create(0, Expr,
403 MCFixupKind(Mips::fixup_MICROMIPS_26_S1)));
407 unsigned MipsMCCodeEmitter::
408 getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo,
409 SmallVectorImpl<MCFixup> &Fixups,
410 const MCSubtargetInfo &STI) const {
412 const MCOperand &MO = MI.getOperand(OpNo);
414 // The immediate is encoded as 'immediate << 2'.
415 unsigned Res = getMachineOpValue(MI, MO, Fixups, STI);
416 assert((Res & 3) == 0);
420 assert(MO.isExpr() &&
421 "getUImm5Lsl2Encoding expects only expressions or an immediate
");
426 unsigned MipsMCCodeEmitter::
427 getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo,
428 SmallVectorImpl<MCFixup> &Fixups,
429 const MCSubtargetInfo &STI) const {
431 const MCOperand &MO = MI.getOperand(OpNo);
433 int Value = MO.getImm();
440 unsigned MipsMCCodeEmitter::
441 getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo,
442 SmallVectorImpl<MCFixup> &Fixups,
443 const MCSubtargetInfo &STI) const {
445 const MCOperand &MO = MI.getOperand(OpNo);
447 unsigned Value = MO.getImm();
454 unsigned MipsMCCodeEmitter::
455 getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo,
456 SmallVectorImpl<MCFixup> &Fixups,
457 const MCSubtargetInfo &STI) const {
459 const MCOperand &MO = MI.getOperand(OpNo);
461 unsigned Binary = (MO.getImm() >> 2) & 0x0000ffff;
462 return (((Binary & 0x8000) >> 7) | (Binary & 0x00ff));
468 unsigned MipsMCCodeEmitter::
469 getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups,
470 const MCSubtargetInfo &STI) const {
473 if (Expr->evaluateAsAbsolute(Res))
476 MCExpr::ExprKind Kind = Expr->getKind();
477 if (Kind == MCExpr::Constant) {
478 return cast<MCConstantExpr>(Expr)->getValue();
481 if (Kind == MCExpr::Binary) {
482 unsigned Res = getExprOpValue(cast<MCBinaryExpr>(Expr)->getLHS(), Fixups, STI);
483 Res += getExprOpValue(cast<MCBinaryExpr>(Expr)->getRHS(), Fixups, STI);
487 if (Kind == MCExpr::Target) {
488 const MipsMCExpr *MipsExpr = cast<MipsMCExpr>(Expr);
490 Mips::Fixups FixupKind = Mips::Fixups(0);
491 switch (MipsExpr->getKind()) {
492 default: llvm_unreachable("Unsupported fixup kind
for target expression!
");
493 case MipsMCExpr::VK_Mips_HIGHEST:
494 FixupKind = Mips::fixup_Mips_HIGHEST;
496 case MipsMCExpr::VK_Mips_HIGHER:
497 FixupKind = Mips::fixup_Mips_HIGHER;
499 case MipsMCExpr::VK_Mips_HI:
500 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HI16
501 : Mips::fixup_Mips_HI16;
503 case MipsMCExpr::VK_Mips_LO:
504 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16
505 : Mips::fixup_Mips_LO16;
508 Fixups.push_back(MCFixup::create(0, MipsExpr, MCFixupKind(FixupKind)));
512 if (Kind == MCExpr::SymbolRef) {
513 Mips::Fixups FixupKind = Mips::Fixups(0);
515 switch(cast<MCSymbolRefExpr>(Expr)->getKind()) {
516 default: llvm_unreachable("Unknown fixup kind!
");
518 case MCSymbolRefExpr::VK_None:
519 FixupKind = Mips::fixup_Mips_32; // FIXME: This is ok for O32/N32 but not N64.
521 case MCSymbolRefExpr::VK_Mips_GPOFF_HI :
522 FixupKind = Mips::fixup_Mips_GPOFF_HI;
524 case MCSymbolRefExpr::VK_Mips_GPOFF_LO :
525 FixupKind = Mips::fixup_Mips_GPOFF_LO;
527 case MCSymbolRefExpr::VK_Mips_GOT_PAGE :
528 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_PAGE
529 : Mips::fixup_Mips_GOT_PAGE;
531 case MCSymbolRefExpr::VK_Mips_GOT_OFST :
532 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_OFST
533 : Mips::fixup_Mips_GOT_OFST;
535 case MCSymbolRefExpr::VK_Mips_GOT_DISP :
536 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_DISP
537 : Mips::fixup_Mips_GOT_DISP;
539 case MCSymbolRefExpr::VK_Mips_GPREL:
540 FixupKind = Mips::fixup_Mips_GPREL16;
542 case MCSymbolRefExpr::VK_Mips_GOT_CALL:
543 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_CALL16
544 : Mips::fixup_Mips_CALL16;
546 case MCSymbolRefExpr::VK_Mips_GOT16:
547 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT16
548 : Mips::fixup_Mips_GOT_Global;
550 case MCSymbolRefExpr::VK_Mips_GOT:
551 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT16
552 : Mips::fixup_Mips_GOT_Local;
554 case MCSymbolRefExpr::VK_Mips_ABS_HI:
555 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HI16
556 : Mips::fixup_Mips_HI16;
558 case MCSymbolRefExpr::VK_Mips_ABS_LO:
559 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16
560 : Mips::fixup_Mips_LO16;
562 case MCSymbolRefExpr::VK_Mips_TLSGD:
563 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_GD
564 : Mips::fixup_Mips_TLSGD;
566 case MCSymbolRefExpr::VK_Mips_TLSLDM:
567 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_LDM
568 : Mips::fixup_Mips_TLSLDM;
570 case MCSymbolRefExpr::VK_Mips_DTPREL_HI:
571 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_HI16
572 : Mips::fixup_Mips_DTPREL_HI;
574 case MCSymbolRefExpr::VK_Mips_DTPREL_LO:
575 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_LO16
576 : Mips::fixup_Mips_DTPREL_LO;
578 case MCSymbolRefExpr::VK_Mips_GOTTPREL:
579 FixupKind = Mips::fixup_Mips_GOTTPREL;
581 case MCSymbolRefExpr::VK_Mips_TPREL_HI:
582 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_HI16
583 : Mips::fixup_Mips_TPREL_HI;
585 case MCSymbolRefExpr::VK_Mips_TPREL_LO:
586 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_LO16
587 : Mips::fixup_Mips_TPREL_LO;
589 case MCSymbolRefExpr::VK_Mips_HIGHER:
590 FixupKind = Mips::fixup_Mips_HIGHER;
592 case MCSymbolRefExpr::VK_Mips_HIGHEST:
593 FixupKind = Mips::fixup_Mips_HIGHEST;
595 case MCSymbolRefExpr::VK_Mips_GOT_HI16:
596 FixupKind = Mips::fixup_Mips_GOT_HI16;
598 case MCSymbolRefExpr::VK_Mips_GOT_LO16:
599 FixupKind = Mips::fixup_Mips_GOT_LO16;
601 case MCSymbolRefExpr::VK_Mips_CALL_HI16:
602 FixupKind = Mips::fixup_Mips_CALL_HI16;
604 case MCSymbolRefExpr::VK_Mips_CALL_LO16:
605 FixupKind = Mips::fixup_Mips_CALL_LO16;
607 case MCSymbolRefExpr::VK_Mips_PCREL_HI16:
608 FixupKind = Mips::fixup_MIPS_PCHI16;
610 case MCSymbolRefExpr::VK_Mips_PCREL_LO16:
611 FixupKind = Mips::fixup_MIPS_PCLO16;
615 Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind)));
623 unsigned MipsMCCodeEmitter::
624 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
625 SmallVectorImpl<MCFixup> &Fixups,
626 const MCSubtargetInfo &STI) const {
628 unsigned Reg = MO.getReg();
629 unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
631 } else if (MO.isImm()) {
632 return static_cast<unsigned>(MO.getImm());
633 } else if (MO.isFPImm()) {
634 return static_cast<unsigned>(APFloat(MO.getFPImm())
635 .bitcastToAPInt().getHiBits(32).getLimitedValue());
637 // MO must be an Expr.
639 return getExprOpValue(MO.getExpr(),Fixups, STI);
645 MipsMCCodeEmitter::getMSAMemEncoding(const MCInst &MI, unsigned OpNo,
646 SmallVectorImpl<MCFixup> &Fixups,
647 const MCSubtargetInfo &STI) const {
648 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
649 assert(MI.getOperand(OpNo).isReg());
650 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16;
651 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
653 // The immediate field of an LD/ST instruction is scaled which means it must
654 // be divided (when encoding) by the size (in bytes) of the instructions'
660 switch(MI.getOpcode())
667 // We don't need to scale the offset in this case
683 return (OffBits & 0xFFFF) | RegBits;
689 MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo,
690 SmallVectorImpl<MCFixup> &Fixups,
691 const MCSubtargetInfo &STI) const {
692 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
693 assert(MI.getOperand(OpNo).isReg());
694 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16;
695 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
697 return (OffBits & 0xFFFF) | RegBits;
700 unsigned MipsMCCodeEmitter::
701 getMemEncodingMMImm4(const MCInst &MI, unsigned OpNo,
702 SmallVectorImpl<MCFixup> &Fixups,
703 const MCSubtargetInfo &STI) const {
704 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
705 assert(MI.getOperand(OpNo).isReg());
706 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
708 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
711 return (OffBits & 0xF) | RegBits;
714 unsigned MipsMCCodeEmitter::
715 getMemEncodingMMImm4Lsl1(const MCInst &MI, unsigned OpNo,
716 SmallVectorImpl<MCFixup> &Fixups,
717 const MCSubtargetInfo &STI) const {
718 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
719 assert(MI.getOperand(OpNo).isReg());
720 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
722 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
725 return (OffBits & 0xF) | RegBits;
728 unsigned MipsMCCodeEmitter::
729 getMemEncodingMMImm4Lsl2(const MCInst &MI, unsigned OpNo,
730 SmallVectorImpl<MCFixup> &Fixups,
731 const MCSubtargetInfo &STI) const {
732 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
733 assert(MI.getOperand(OpNo).isReg());
734 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
736 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
739 return (OffBits & 0xF) | RegBits;
742 unsigned MipsMCCodeEmitter::
743 getMemEncodingMMSPImm5Lsl2(const MCInst &MI, unsigned OpNo,
744 SmallVectorImpl<MCFixup> &Fixups,
745 const MCSubtargetInfo &STI) const {
746 // Register is encoded in bits 9-5, offset is encoded in bits 4-0.
747 assert(MI.getOperand(OpNo).isReg() &&
748 MI.getOperand(OpNo).getReg() == Mips::SP &&
749 "Unexpected base
register!
");
750 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
753 return OffBits & 0x1F;
756 unsigned MipsMCCodeEmitter::
757 getMemEncodingMMGPImm7Lsl2(const MCInst &MI, unsigned OpNo,
758 SmallVectorImpl<MCFixup> &Fixups,
759 const MCSubtargetInfo &STI) const {
760 // Register is encoded in bits 9-7, offset is encoded in bits 6-0.
761 assert(MI.getOperand(OpNo).isReg() &&
762 MI.getOperand(OpNo).getReg() == Mips::GP &&
763 "Unexpected base
register!
");
765 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
768 return OffBits & 0x7F;
771 unsigned MipsMCCodeEmitter::
772 getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
773 SmallVectorImpl<MCFixup> &Fixups,
774 const MCSubtargetInfo &STI) const {
775 // opNum can be invalid if instruction had reglist as operand.
776 // MemOperand is always last operand of instruction (base + offset).
777 switch (MI.getOpcode()) {
782 OpNo = MI.getNumOperands() - 2;
786 // Base register is encoded in bits 20-16, offset is encoded in bits 11-0.
787 assert(MI.getOperand(OpNo).isReg());
788 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) << 16;
789 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
791 return (OffBits & 0x0FFF) | RegBits;
794 unsigned MipsMCCodeEmitter::
795 getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo,
796 SmallVectorImpl<MCFixup> &Fixups,
797 const MCSubtargetInfo &STI) const {
798 // opNum can be invalid if instruction had reglist as operand
799 // MemOperand is always last operand of instruction (base + offset)
800 switch (MI.getOpcode()) {
805 OpNo = MI.getNumOperands() - 2;
809 // Offset is encoded in bits 4-0.
810 assert(MI.getOperand(OpNo).isReg());
811 // Base register is always SP - thus it is not encoded.
812 assert(MI.getOperand(OpNo+1).isImm());
813 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
815 return ((OffBits >> 2) & 0x0F);
819 MipsMCCodeEmitter::getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
820 SmallVectorImpl<MCFixup> &Fixups,
821 const MCSubtargetInfo &STI) const {
822 assert(MI.getOperand(OpNo).isImm());
823 unsigned SizeEncoding = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
824 return SizeEncoding - 1;
827 // FIXME: should be called getMSBEncoding
830 MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
831 SmallVectorImpl<MCFixup> &Fixups,
832 const MCSubtargetInfo &STI) const {
833 assert(MI.getOperand(OpNo-1).isImm());
834 assert(MI.getOperand(OpNo).isImm());
835 unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups, STI);
836 unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
838 return Position + Size - 1;
842 MipsMCCodeEmitter::getLSAImmEncoding(const MCInst &MI, unsigned OpNo,
843 SmallVectorImpl<MCFixup> &Fixups,
844 const MCSubtargetInfo &STI) const {
845 assert(MI.getOperand(OpNo).isImm());
846 // The immediate is encoded as 'immediate - 1'.
847 return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) - 1;
851 MipsMCCodeEmitter::getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo,
852 SmallVectorImpl<MCFixup> &Fixups,
853 const MCSubtargetInfo &STI) const {
854 const MCOperand &MO = MI.getOperand(OpNo);
856 // The immediate is encoded as 'immediate << 2'.
857 unsigned Res = getMachineOpValue(MI, MO, Fixups, STI);
858 assert((Res & 3) == 0);
862 assert(MO.isExpr() &&
863 "getSimm19Lsl2Encoding expects only expressions or an immediate
");
865 const MCExpr *Expr = MO.getExpr();
866 Fixups.push_back(MCFixup::create(0, Expr,
867 MCFixupKind(Mips::fixup_MIPS_PC19_S2)));
872 MipsMCCodeEmitter::getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo,
873 SmallVectorImpl<MCFixup> &Fixups,
874 const MCSubtargetInfo &STI) const {
875 const MCOperand &MO = MI.getOperand(OpNo);
877 // The immediate is encoded as 'immediate << 3'.
878 unsigned Res = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
879 assert((Res & 7) == 0);
883 assert(MO.isExpr() &&
884 "getSimm18Lsl2Encoding expects only expressions or an immediate
");
886 const MCExpr *Expr = MO.getExpr();
887 Fixups.push_back(MCFixup::create(0, Expr,
888 MCFixupKind(Mips::fixup_MIPS_PC18_S3)));
893 MipsMCCodeEmitter::getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo,
894 SmallVectorImpl<MCFixup> &Fixups,
895 const MCSubtargetInfo &STI) const {
896 assert(MI.getOperand(OpNo).isImm());
897 const MCOperand &MO = MI.getOperand(OpNo);
898 return MO.getImm() % 8;
902 MipsMCCodeEmitter::getUImm4AndValue(const MCInst &MI, unsigned OpNo,
903 SmallVectorImpl<MCFixup> &Fixups,
904 const MCSubtargetInfo &STI) const {
905 assert(MI.getOperand(OpNo).isImm());
906 const MCOperand &MO = MI.getOperand(OpNo);
907 unsigned Value = MO.getImm();
909 case 128: return 0x0;
922 case 255: return 0xd;
923 case 32768: return 0xe;
924 case 65535: return 0xf;
926 llvm_unreachable("Unexpected value
");
930 MipsMCCodeEmitter::getRegisterListOpValue(const MCInst &MI, unsigned OpNo,
931 SmallVectorImpl<MCFixup> &Fixups,
932 const MCSubtargetInfo &STI) const {
935 // Register list operand is always first operand of instruction and it is
936 // placed before memory operand (register + imm).
938 for (unsigned I = OpNo, E = MI.getNumOperands() - 2; I < E; ++I) {
939 unsigned Reg = MI.getOperand(I).getReg();
940 unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
950 MipsMCCodeEmitter::getRegisterListOpValue16(const MCInst &MI, unsigned OpNo,
951 SmallVectorImpl<MCFixup> &Fixups,
952 const MCSubtargetInfo &STI) const {
953 return (MI.getNumOperands() - 4);
957 MipsMCCodeEmitter::getRegisterPairOpValue(const MCInst &MI, unsigned OpNo,
958 SmallVectorImpl<MCFixup> &Fixups,
959 const MCSubtargetInfo &STI) const {
960 return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
964 MipsMCCodeEmitter::getMovePRegPairOpValue(const MCInst &MI, unsigned OpNo,
965 SmallVectorImpl<MCFixup> &Fixups,
966 const MCSubtargetInfo &STI) const {
969 if (MI.getOperand(0).getReg() == Mips::A1 &&
970 MI.getOperand(1).getReg() == Mips::A2)
972 else if (MI.getOperand(0).getReg() == Mips::A1 &&
973 MI.getOperand(1).getReg() == Mips::A3)
975 else if (MI.getOperand(0).getReg() == Mips::A2 &&
976 MI.getOperand(1).getReg() == Mips::A3)
978 else if (MI.getOperand(0).getReg() == Mips::A0 &&
979 MI.getOperand(1).getReg() == Mips::S5)
981 else if (MI.getOperand(0).getReg() == Mips::A0 &&
982 MI.getOperand(1).getReg() == Mips::S6)
984 else if (MI.getOperand(0).getReg() == Mips::A0 &&
985 MI.getOperand(1).getReg() == Mips::A1)
987 else if (MI.getOperand(0).getReg() == Mips::A0 &&
988 MI.getOperand(1).getReg() == Mips::A2)
990 else if (MI.getOperand(0).getReg() == Mips::A0 &&
991 MI.getOperand(1).getReg() == Mips::A3)
998 MipsMCCodeEmitter::getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo,
999 SmallVectorImpl<MCFixup> &Fixups,
1000 const MCSubtargetInfo &STI) const {
1001 const MCOperand &MO = MI.getOperand(OpNo);
1002 assert(MO.isImm() && "getSimm23Lsl2Encoding expects only an immediate
");
1003 // The immediate is encoded as 'immediate >> 2'.
1004 unsigned Res = static_cast<unsigned>(MO.getImm());
1005 assert((Res & 3) == 0);
1009 #include "MipsGenMCCodeEmitter.inc
"
static void LowerDextDins(MCInst &InstIn)
MCInst const & instruction(MCInst const &MCB, size_t Index)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Context object for machine code objects.
Instances of this class represent a single low-level machine instruction.
MCCodeEmitter * createMipsMCCodeEmitterEL(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
MCCodeEmitter - Generic instruction encoding interface.
Interface to description of machine instruction set.
This file declares a class to represent arbitrary precision floating point values and provide a varie...
void setOpcode(unsigned Op)
static void LowerLargeShift(MCInst &Inst)
unsigned getOpcode() const
MCCodeEmitter * createMipsMCCodeEmitterEB(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
unsigned getNumOperands() const
static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI)
getBranchTargetOpValue - Helper function to get the branch target operand, which is either an immedia...
const MCOperand & getOperand(unsigned i) const