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LLVM
3.7.0
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#include "llvm/CodeGen/DFAPacketizer.h"#include "Hexagon.h"#include "HexagonMachineFunctionInfo.h"#include "HexagonRegisterInfo.h"#include "HexagonSubtarget.h"#include "HexagonTargetMachine.h"#include "llvm/ADT/DenseMap.h"#include "llvm/ADT/Statistic.h"#include "llvm/CodeGen/LatencyPriorityQueue.h"#include "llvm/CodeGen/MachineDominators.h"#include "llvm/CodeGen/MachineFrameInfo.h"#include "llvm/CodeGen/MachineFunctionAnalysis.h"#include "llvm/CodeGen/MachineFunctionPass.h"#include "llvm/CodeGen/MachineInstrBuilder.h"#include "llvm/CodeGen/MachineLoopInfo.h"#include "llvm/CodeGen/MachineRegisterInfo.h"#include "llvm/CodeGen/Passes.h"#include "llvm/CodeGen/ScheduleDAG.h"#include "llvm/CodeGen/ScheduleDAGInstrs.h"#include "llvm/CodeGen/ScheduleHazardRecognizer.h"#include "llvm/CodeGen/SchedulerRegistry.h"#include "llvm/MC/MCInstrItineraries.h"#include "llvm/Support/CommandLine.h"#include "llvm/Support/Compiler.h"#include "llvm/Support/Debug.h"#include "llvm/Support/MathExtras.h"#include "llvm/Target/TargetInstrInfo.h"#include "llvm/Target/TargetMachine.h"#include "llvm/Target/TargetRegisterInfo.h"#include <map>#include <vector>Go to the source code of this file.
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| llvm | |
| Compute iterated dominance frontiers using a linear time algorithm. | |
Macros | |
| #define | DEBUG_TYPE "packets" |
Enumerations | |
| enum | PredicateKind { PK_False, PK_True, PK_Unknown } |
Variables | |
| static cl::opt< bool > | PacketizeVolatiles ("hexagon-packetize-volatiles", cl::ZeroOrMore, cl::Hidden, cl::init(true), cl::desc("Allow non-solo packetization of volatile memory references")) |
| packets | |
| Hexagon | Packetizer |
| Hexagon | false |
| #define DEBUG_TYPE "packets" |
Definition at line 53 of file HexagonVLIWPacketizer.cpp.
| enum PredicateKind |
| Enumerator | |
|---|---|
| PK_False | |
| PK_True | |
| PK_Unknown | |
Definition at line 450 of file HexagonVLIWPacketizer.cpp.
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DoesModifyCalleeSavedReg - Returns true if the instruction modifies a callee-saved register.
Definition at line 388 of file HexagonVLIWPacketizer.cpp.
References llvm::TargetRegisterInfo::getCalleeSavedRegs(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), and llvm::MachineInstr::modifiesRegister().
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Definition at line 469 of file HexagonVLIWPacketizer.cpp.
References llvm::MachineInstr::getDesc(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isDef(), llvm::HexagonInstrInfo::isPostIncrement(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isUse(), llvm_unreachable, llvm::MCInstrDesc::mayLoad(), and llvm::MCInstrDesc::mayStore().
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Gets the predicate register of a predicated instruction.
We use the following rule: The first predicate register that is a use is the predicate register of a predicated instruction.
Definition at line 830 of file HexagonVLIWPacketizer.cpp.
References llvm::MachineOperand::getReg(), llvm::HexagonInstrInfo::isPredicated(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isUse(), llvm_unreachable, llvm::MachineInstr::operands_begin(), and llvm::MachineInstr::operands_end().
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Returns true if an instruction is predicated on p0 and false if it's predicated on !p0.
Definition at line 458 of file HexagonVLIWPacketizer.cpp.
References llvm::HexagonInstrInfo::isPredicated(), llvm::HexagonInstrInfo::isPredicatedTrue(), PK_False, PK_True, and PK_Unknown.
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Definition at line 509 of file HexagonVLIWPacketizer.cpp.
References llvm::MachineInstr::getNumOperands(), and llvm::MachineInstr::getOperand().
| INITIALIZE_PASS_BEGIN | ( | HexagonPacketizer | , |
| "packets" | , | ||
| "Hexagon Packetizer" | , | ||
| false | , | ||
| false | |||
| ) |
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Definition at line 377 of file HexagonVLIWPacketizer.cpp.
References llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::isCall(), and llvm::MCInstrDesc::isTerminator().
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Definition at line 365 of file HexagonVLIWPacketizer.cpp.
References llvm::MachineInstr::getOpcode().
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Definition at line 267 of file HexagonVLIWPacketizer.cpp.
References llvm::MachineInstr::getOpcode().
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Definition at line 381 of file HexagonVLIWPacketizer.cpp.
References llvm::MachineInstr::getOpcode().
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Definition at line 360 of file HexagonVLIWPacketizer.cpp.
References llvm::SDep::Anti, llvm::SDep::Data, and llvm::SDep::Output.
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Definition at line 369 of file HexagonVLIWPacketizer.cpp.
References llvm::MachineInstr::getOpcode().
| Hexagon false |
Definition at line 181 of file HexagonVLIWPacketizer.cpp.
| Hexagon Packetizer |
Definition at line 181 of file HexagonVLIWPacketizer.cpp.
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| packets |
Definition at line 181 of file HexagonVLIWPacketizer.cpp.
1.8.6