LLVM  3.7.0
SIMachineFunctionInfo.h
Go to the documentation of this file.
1 //===- SIMachineFunctionInfo.h - SIMachineFunctionInfo interface -*- C++ -*-==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 //
12 //===----------------------------------------------------------------------===//
13 
14 
15 #ifndef LLVM_LIB_TARGET_R600_SIMACHINEFUNCTIONINFO_H
16 #define LLVM_LIB_TARGET_R600_SIMACHINEFUNCTIONINFO_H
17 
18 #include "AMDGPUMachineFunction.h"
19 #include "SIRegisterInfo.h"
20 #include <map>
21 
22 namespace llvm {
23 
24 class MachineRegisterInfo;
25 
26 /// This class keeps track of the SPI_SP_INPUT_ADDR config register, which
27 /// tells the hardware which interpolation parameters to load.
29  void anchor() override;
30 
31  unsigned TIDReg;
32  bool HasSpilledVGPRs;
33 
34 public:
35 
36  struct SpilledReg {
37  unsigned VGPR;
38  int Lane;
39  SpilledReg(unsigned R, int L) : VGPR (R), Lane (L) { }
40  SpilledReg() : VGPR(0), Lane(-1) { }
41  bool hasLane() { return Lane != -1;}
42  };
43 
44  // SIMachineFunctionInfo definition
45 
47  SpilledReg getSpilledReg(MachineFunction *MF, unsigned FrameIndex,
48  unsigned SubIdx);
49  unsigned PSInputAddr;
50  unsigned NumUserSGPRs;
51  std::map<unsigned, unsigned> LaneVGPRs;
52  unsigned LDSWaveSpillSize;
53  unsigned ScratchOffsetReg;
54  bool hasCalculatedTID() const { return TIDReg != AMDGPU::NoRegister; };
55  unsigned getTIDReg() const { return TIDReg; };
56  void setTIDReg(unsigned Reg) { TIDReg = Reg; }
57  bool hasSpilledVGPRs() const { return HasSpilledVGPRs; }
58  void setHasSpilledVGPRs(bool Spill = true) { HasSpilledVGPRs = Spill; }
59 
60  unsigned getMaximumWorkGroupSize(const MachineFunction &MF) const;
61 };
62 
63 } // End namespace llvm
64 
65 
66 #endif
Interface definition for SIRegisterInfo.
SIMachineFunctionInfo(const MachineFunction &MF)
void setHasSpilledVGPRs(bool Spill=true)
Reg
All possible values of the reg field in the ModR/M byte.
unsigned getMaximumWorkGroupSize(const MachineFunction &MF) const
SpilledReg getSpilledReg(MachineFunction *MF, unsigned FrameIndex, unsigned SubIdx)
std::map< unsigned, unsigned > LaneVGPRs
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...