36 unsigned FIOperandNum,
42 return AMDGPU::NoRegister;
46 static const unsigned SubRegs[] = {
47 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, AMDGPU::sub4,
48 AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, AMDGPU::sub8, AMDGPU::sub9,
49 AMDGPU::sub10, AMDGPU::sub11, AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14,
54 return SubRegs[Channel];
62 #define GET_REGINFO_TARGET_DESC
63 #include "AMDGPUGenRegisterInfo.inc"
unsigned getIndirectSubReg(unsigned IndirectIndex) const
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
TargetRegisterInfo interface that is implemented by all hw codegen targets.
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
bundle_iterator< MachineInstr, instr_iterator > iterator
unsigned getSubRegFromChannel(unsigned Channel) const
The AMDGPU TargetMachine interface definition for hw codgen targets.
static const MCPhysReg CalleeSavedReg
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const override
unsigned getFrameRegister(const MachineFunction &MF) const override