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LLVM
3.7.0
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#include "llvm/PassSupport.h"#include "Hexagon.h"#include "HexagonInstrInfo.h"#include "HexagonMachineFunctionInfo.h"#include "HexagonRegisterInfo.h"#include "HexagonSubtarget.h"#include "HexagonTargetMachine.h"#include "llvm/ADT/DenseMap.h"#include "llvm/ADT/DenseSet.h"#include "llvm/CodeGen/MachineBasicBlock.h"#include "llvm/CodeGen/MachineFunction.h"#include "llvm/CodeGen/MachineFunctionPass.h"#include "llvm/CodeGen/MachineInstr.h"#include "llvm/CodeGen/MachineInstrBuilder.h"#include "llvm/CodeGen/Passes.h"#include "llvm/Support/CodeGen.h"#include "llvm/Support/CommandLine.h"#include "llvm/Support/Debug.h"#include "llvm/Support/raw_ostream.h"#include "llvm/Target/TargetRegisterInfo.h"Go to the source code of this file.
Namespaces | |
| llvm | |
| Compute iterated dominance frontiers using a linear time algorithm. | |
Macros | |
| #define | DEBUG_TYPE "hexagon-copy-combine" |
Functions | |
| FunctionPass * | llvm::createHexagonCopyToCombine () |
| void | llvm::initializeHexagonCopyToCombinePass (PassRegistry &) |
| INITIALIZE_PASS (HexagonCopyToCombine,"hexagon-copy-combine","Hexagon Copy-To-Combine Pass", false, false) static bool isCombinableInstType(MachineInstr *MI | |
| const HexagonInstrInfo bool ShouldCombineAggressively | switch (MI->getOpcode()) |
| template<unsigned N> | |
| static bool | isGreaterThanNBitTFRI (const MachineInstr *I) |
| static bool | areCombinableOperations (const TargetRegisterInfo *TRI, MachineInstr *HighRegInst, MachineInstr *LowRegInst) |
| areCombinableOperations - Returns true if the two instruction can be merge into a combine (ignoring register constraints). More... | |
| static bool | isEvenReg (unsigned Reg) |
| static void | removeKillInfo (MachineInstr *MI, unsigned RegNotKilled) |
| static bool | isUnsafeToMoveAcross (MachineInstr *I, unsigned UseReg, unsigned DestReg, const TargetRegisterInfo *TRI) |
isUnsafeToMoveAcross - Returns true if it is unsafe to move a copy instruction from UseReg to DestReg over the instruction I. More... | |
| static unsigned | UseReg (const MachineOperand &MO) |
Variables | |
| static cl::opt< bool > | IsCombinesDisabled ("disable-merge-into-combines", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable merging into combines")) |
| static cl::opt< unsigned > | MaxNumOfInstsBetweenNewValueStoreAndTFR ("max-num-inst-between-tfr-and-nv-store", cl::Hidden, cl::init(4), cl::desc("Maximum distance between a tfr feeding a store we ""consider the store still to be newifiable")) |
| const HexagonInstrInfo * | TII |
| return | false |
| #define DEBUG_TYPE "hexagon-copy-combine" |
Definition at line 37 of file HexagonCopyToCombine.cpp.
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areCombinableOperations - Returns true if the two instruction can be merge into a combine (ignoring register constraints).
Definition at line 169 of file HexagonCopyToCombine.cpp.
References llvm::MachineInstr::getOpcode().
| INITIALIZE_PASS | ( | HexagonCopyToCombine | , |
| "hexagon-copy-combine" | , | ||
| "Hexagon Copy-To-Combine Pass" | , | ||
| false | , | ||
| false | |||
| ) |
Definition at line 188 of file HexagonCopyToCombine.cpp.
References contains(), and llvm::TargetRegisterInfo::isPhysicalRegister().
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Definition at line 158 of file HexagonCopyToCombine.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::isImm().
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isUnsafeToMoveAcross - Returns true if it is unsafe to move a copy instruction from UseReg to DestReg over the instruction I.
Definition at line 205 of file HexagonCopyToCombine.cpp.
References llvm::MachineInstr::hasUnmodeledSideEffects(), llvm::MachineInstr::isDebugValue(), llvm::MachineInstr::isInlineAsm(), llvm::MachineInstr::modifiesRegister(), and llvm::MachineInstr::readsRegister().
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Definition at line 194 of file HexagonCopyToCombine.cpp.
References llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), I, llvm::MachineOperand::isKill(), llvm::MachineOperand::isReg(), and llvm::MachineOperand::setIsKill().
| const HexagonInstrInfo bool ShouldCombineAggressively switch | ( | MI-> | getOpcode() | ) |
Definition at line 117 of file HexagonCopyToCombine.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getTargetFlags(), llvm::MachineOperand::isImm(), llvm::isInt< 8 >(), llvm::MachineOperand::isReg(), and llvm::HexagonII::MO_NO_FLAG.
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Definition at line 215 of file HexagonCopyToCombine.cpp.
References llvm::MachineOperand::getReg(), and llvm::MachineOperand::isReg().
| return false |
Definition at line 154 of file HexagonCopyToCombine.cpp.
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| const HexagonInstrInfo* TII |
Definition at line 115 of file HexagonCopyToCombine.cpp.
Referenced by llvm::MachineBasicBlock::addLiveIn(), llvm::SITargetLowering::AdjustInstrPostInstrSelection(), llvm::SITargetLowering::analyzeImmediate(), llvm::SITargetLowering::buildScratchRSRC(), llvm::MachineBasicBlock::canFallThrough(), CombineCVTAToLocal(), llvm::createBURRListDAGScheduler(), llvm::createHybridListDAGScheduler(), llvm::createILPListDAGScheduler(), llvm::createSourceListDAGScheduler(), llvm::Mips16FrameLowering::determineCalleeSaves(), llvm::AArch64FrameLowering::eliminateCallFramePseudoInstr(), llvm::MSP430FrameLowering::eliminateCallFramePseudoInstr(), llvm::XCoreFrameLowering::eliminateCallFramePseudoInstr(), llvm::Thumb1FrameLowering::eliminateCallFramePseudoInstr(), llvm::PPCFrameLowering::eliminateCallFramePseudoInstr(), llvm::BPFRegisterInfo::eliminateFrameIndex(), llvm::MSP430RegisterInfo::eliminateFrameIndex(), llvm::SparcRegisterInfo::eliminateFrameIndex(), llvm::XCoreRegisterInfo::eliminateFrameIndex(), llvm::SystemZRegisterInfo::eliminateFrameIndex(), llvm::AArch64RegisterInfo::eliminateFrameIndex(), llvm::PPCRegisterInfo::eliminateFrameIndex(), llvm::ARMBaseRegisterInfo::eliminateFrameIndex(), llvm::PPCTargetLowering::EmitAtomicBinary(), llvm::AArch64FrameLowering::emitCalleeSavedFrameMoves(), emitComments(), llvm::PPCTargetLowering::emitEHSjLjLongJmp(), llvm::PPCTargetLowering::emitEHSjLjSetJmp(), llvm::Mips16FrameLowering::emitEpilogue(), llvm::MipsSEFrameLowering::emitEpilogue(), llvm::MSP430FrameLowering::emitEpilogue(), llvm::Thumb1FrameLowering::emitEpilogue(), llvm::XCoreFrameLowering::emitEpilogue(), llvm::AArch64FrameLowering::emitEpilogue(), llvm::PPCFrameLowering::emitEpilogue(), llvm::AArch64TargetLowering::EmitF128CSEL(), llvm::R600TargetLowering::EmitInstrWithCustomInserter(), llvm::BPFTargetLowering::EmitInstrWithCustomInserter(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), llvm::MSP430TargetLowering::EmitInstrWithCustomInserter(), llvm::PPCTargetLowering::EmitInstrWithCustomInserter(), llvm::ARMBaseRegisterInfo::emitLoadConstPool(), llvm::PPCTargetLowering::EmitPartwordAtomicBinary(), llvm::Mips16FrameLowering::emitPrologue(), llvm::MipsSEFrameLowering::emitPrologue(), llvm::MSP430FrameLowering::emitPrologue(), llvm::Thumb1FrameLowering::emitPrologue(), llvm::XCoreFrameLowering::emitPrologue(), llvm::ARMFrameLowering::emitPrologue(), llvm::AArch64FrameLowering::emitPrologue(), llvm::PPCFrameLowering::emitPrologue(), llvm::MSP430TargetLowering::EmitShiftInstr(), emitThumb1LoadConstPool(), emitThumb2LoadConstPool(), llvm::SparcTargetLowering::expandAtomicRMW(), llvm::SparcTargetLowering::expandSelectCC(), llvm::finalizeBundle(), FindCallSeqStart(), FoldOperand(), llvm::ARMHazardRecognizer::getHazardType(), llvm::MSP430InstrInfo::GetInstSizeInBytes(), llvm::SystemZTTIImpl::getIntImmCost(), llvm::SDNode::getOperationName(), llvm::PPCTargetLowering::getPrefLoopAlignment(), llvm::MachineInstr::getRegClassConstraintEffectForVReg(), llvm::R600RegisterInfo::getReservedRegs(), llvm::ARMTargetLowering::getSchedulingPreference(), llvm::ConvergingVLIWScheduler::initialize(), INITIALIZE_PASS(), IsChainDependent(), llvm::PPCRegisterInfo::lowerCRBitRestore(), llvm::PPCRegisterInfo::lowerCRBitSpilling(), llvm::PPCRegisterInfo::lowerCRRestore(), llvm::PPCRegisterInfo::lowerCRSpilling(), llvm::PPCRegisterInfo::lowerDynamicAlloc(), llvm::R600TargetLowering::LowerOperation(), llvm::PPCRegisterInfo::lowerVRSAVERestore(), llvm::PPCRegisterInfo::lowerVRSAVESpilling(), llvm::AArch64RegisterInfo::materializeFrameBaseRegister(), llvm::PPCRegisterInfo::materializeFrameBaseRegister(), llvm::ARMBaseRegisterInfo::materializeFrameBaseRegister(), MIsNeedChainEdge(), llvm::SITargetLowering::PostISelFolding(), reassociateOps(), llvm::MachineRegisterInfo::recomputeRegClass(), replaceFI(), llvm::AArch64RegisterInfo::resolveFrameIndex(), llvm::PPCRegisterInfo::resolveFrameIndex(), llvm::ARMBaseRegisterInfo::resolveFrameIndex(), llvm::SystemZFrameLowering::restoreCalleeSavedRegisters(), llvm::Thumb1FrameLowering::restoreCalleeSavedRegisters(), llvm::XCoreFrameLowering::restoreCalleeSavedRegisters(), llvm::MSP430FrameLowering::restoreCalleeSavedRegisters(), llvm::AArch64FrameLowering::restoreCalleeSavedRegisters(), llvm::PPCFrameLowering::restoreCalleeSavedRegisters(), restoreCRs(), llvm::rewriteAArch64FrameIndex(), llvm::VirtRegMap::runOnMachineFunction(), llvm::MachineTraceMetrics::runOnMachineFunction(), llvm::Mips16RegisterInfo::saveScavengerRegister(), llvm::FunctionLoweringInfo::set(), setCallTargetReg(), llvm::SITargetLowering::shouldConvertConstantLoadToIntImm(), llvm::MipsSEFrameLowering::spillCalleeSavedRegisters(), llvm::SystemZFrameLowering::spillCalleeSavedRegisters(), llvm::Thumb1FrameLowering::spillCalleeSavedRegisters(), llvm::XCoreFrameLowering::spillCalleeSavedRegisters(), llvm::MSP430FrameLowering::spillCalleeSavedRegisters(), llvm::AArch64FrameLowering::spillCalleeSavedRegisters(), llvm::PPCFrameLowering::spillCalleeSavedRegisters(), llvm::MachineBasicBlock::SplitCriticalEdge(), UpdateOperandRegClass(), llvm::MachineBasicBlock::updateTerminator(), and llvm::SITargetLowering::wrapAddr64Rsrc().
1.8.6