35 uint64_t &FixedValue)
override {
36 assert(!
"Not implemented");
45 AMDGPUAsmBackend(
const Target &
T)
50 uint64_t
Value,
bool IsPCRel)
const override;
56 void relaxInstruction(
const MCInst &Inst,
MCInst &Res)
const override {
57 assert(!
"Not implemented");
59 bool mayNeedRelaxation(
const MCInst &Inst)
const override {
return false; }
60 bool writeNopData(uint64_t Count,
MCObjectWriter *OW)
const override;
74 void AMDGPUAsmBackend::applyFixup(
const MCFixup &
Fixup,
char *Data,
75 unsigned DataSize, uint64_t
Value,
78 switch ((
unsigned)Fixup.
getKind()) {
81 uint16_t *Dst = (uint16_t*)(Data + Fixup.
getOffset());
82 *Dst = (Value - 4) / 4;
87 uint32_t *Dst = (uint32_t*)(Data + Fixup.
getOffset());
93 uint32_t *Dst = (uint32_t*)(Data + Fixup.
getOffset());
107 {
"fixup_si_rodata", 0, 32, 0 },
117 bool AMDGPUAsmBackend::writeNopData(uint64_t Count,
MCObjectWriter *OW)
const {
129 class ELFAMDGPUAsmBackend :
public AMDGPUAsmBackend {
133 ELFAMDGPUAsmBackend(
const Target &
T,
bool Is64Bit) :
134 AMDGPUAsmBackend(T), Is64Bit(Is64Bit) { }
fixup for offset from instruction to end of text section
void WriteZeros(unsigned N)
This represents an "assembler immediate".
fixup for global addresses with constant initializers
Defines the object file and target independent interfaces used by the assembler backend to write nati...
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...
Encapsulates the layout of an assembly file at a particular point in time.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
uint32_t getOffset() const
Instances of this class represent a single low-level machine instruction.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
MCAsmBackend * createAMDGPUAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU)
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
void writeSectionData(const MCSection *Section, const MCAsmLayout &Layout) const
Emit the section contents using the given object writer.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
MCFixupKind getKind() const
Triple - Helper class for working with autoconf configuration names.
PowerPC TLS Dynamic Call Fixup
An iterator type that allows iterating over the pointees via some other iterator. ...
Target - Wrapper for Target specific information.
Provides AMDGPU specific target descriptions.
16-bit PC relative fixup for SOPP branch instructions.
Target independent information on a fixup kind.
An abstract base class for streams implementations that also support a pwrite operation.
MCObjectWriter * createAMDGPUELFObjectWriter(bool Is64Bit, raw_pwrite_stream &OS)
const ARM::ArchExtKind Kind
LLVM Value Representation.
Generic interface to target specific assembler backends.
StringRef - Represent a constant reference to a string, i.e.
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.