45 if ((Opc == Mips::LW) || (Opc ==
Mips::LD) ||
46 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) {
67 if ((Opc == Mips::SW) || (Opc == Mips::SD) ||
68 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) {
81 unsigned DestReg,
unsigned SrcReg,
83 unsigned Opc = 0, ZeroReg = 0;
86 if (Mips::GPR32RegClass.
contains(DestReg)) {
87 if (Mips::GPR32RegClass.
contains(SrcReg)) {
89 Opc = Mips::MOVE16_MM;
91 Opc = Mips::ADDu, ZeroReg = Mips::ZERO;
92 }
else if (Mips::CCRRegClass.
contains(SrcReg))
94 else if (Mips::FGR32RegClass.
contains(SrcReg))
96 else if (Mips::HI32RegClass.
contains(SrcReg)) {
97 Opc = isMicroMips ? Mips::MFHI16_MM :
Mips::MFHI;
99 }
else if (Mips::LO32RegClass.
contains(SrcReg)) {
100 Opc = isMicroMips ? Mips::MFLO16_MM :
Mips::MFLO;
102 }
else if (Mips::HI32DSPRegClass.
contains(SrcReg))
103 Opc = Mips::MFHI_DSP;
104 else if (Mips::LO32DSPRegClass.
contains(SrcReg))
105 Opc = Mips::MFLO_DSP;
106 else if (Mips::DSPCCRegClass.
contains(SrcReg)) {
107 BuildMI(MBB, I, DL,
get(Mips::RDDSP), DestReg).
addImm(1 << 4)
111 else if (Mips::MSACtrlRegClass.
contains(SrcReg))
114 else if (Mips::GPR32RegClass.
contains(SrcReg)) {
115 if (Mips::CCRRegClass.
contains(DestReg))
117 else if (Mips::FGR32RegClass.
contains(DestReg))
119 else if (Mips::HI32RegClass.
contains(DestReg))
120 Opc = Mips::MTHI, DestReg = 0;
121 else if (Mips::LO32RegClass.
contains(DestReg))
122 Opc = Mips::MTLO, DestReg = 0;
123 else if (Mips::HI32DSPRegClass.
contains(DestReg))
124 Opc = Mips::MTHI_DSP;
125 else if (Mips::LO32DSPRegClass.
contains(DestReg))
126 Opc = Mips::MTLO_DSP;
127 else if (Mips::DSPCCRegClass.
contains(DestReg)) {
128 BuildMI(MBB, I, DL,
get(Mips::WRDSP))
133 else if (Mips::MSACtrlRegClass.
contains(DestReg))
136 else if (Mips::FGR32RegClass.
contains(DestReg, SrcReg))
138 else if (Mips::AFGR64RegClass.
contains(DestReg, SrcReg))
139 Opc = Mips::FMOV_D32;
140 else if (Mips::FGR64RegClass.
contains(DestReg, SrcReg))
141 Opc = Mips::FMOV_D64;
142 else if (Mips::GPR64RegClass.
contains(DestReg)) {
143 if (Mips::GPR64RegClass.
contains(SrcReg))
144 Opc = Mips::DADDu, ZeroReg = Mips::ZERO_64;
145 else if (Mips::HI64RegClass.
contains(SrcReg))
146 Opc = Mips::MFHI64, SrcReg = 0;
147 else if (Mips::LO64RegClass.
contains(SrcReg))
148 Opc = Mips::MFLO64, SrcReg = 0;
149 else if (Mips::FGR64RegClass.
contains(SrcReg))
152 else if (Mips::GPR64RegClass.
contains(SrcReg)) {
153 if (Mips::HI64RegClass.
contains(DestReg))
154 Opc = Mips::MTHI64, DestReg = 0;
155 else if (Mips::LO64RegClass.
contains(DestReg))
156 Opc = Mips::MTLO64, DestReg = 0;
157 else if (Mips::FGR64RegClass.
contains(DestReg))
160 else if (Mips::MSA128BRegClass.
contains(DestReg)) {
161 if (Mips::MSA128BRegClass.
contains(SrcReg))
165 assert(Opc &&
"Cannot copy registers");
181 unsigned SrcReg,
bool isKill,
int FI,
183 int64_t Offset)
const {
185 if (I != MBB.
end()) DL = I->getDebugLoc();
190 if (Mips::GPR32RegClass.hasSubClassEq(RC))
192 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
194 else if (Mips::ACC64RegClass.hasSubClassEq(RC))
195 Opc = Mips::STORE_ACC64;
196 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
197 Opc = Mips::STORE_ACC64DSP;
198 else if (Mips::ACC128RegClass.hasSubClassEq(RC))
199 Opc = Mips::STORE_ACC128;
200 else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
201 Opc = Mips::STORE_CCOND_DSP;
202 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
204 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
206 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
217 assert(Opc &&
"Register class not handled!");
227 if (I != MBB.
end()) DL = I->getDebugLoc();
231 if (Mips::GPR32RegClass.hasSubClassEq(RC))
233 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
235 else if (Mips::ACC64RegClass.hasSubClassEq(RC))
236 Opc = Mips::LOAD_ACC64;
237 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
238 Opc = Mips::LOAD_ACC64DSP;
239 else if (Mips::ACC128RegClass.hasSubClassEq(RC))
240 Opc = Mips::LOAD_ACC128;
241 else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
242 Opc = Mips::LOAD_CCOND_DSP;
243 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
245 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
247 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
258 assert(Opc &&
"Register class not handled!");
268 switch(MI->getDesc().getOpcode()) {
272 expandRetRA(MBB, MI);
274 case Mips::PseudoMFHI:
275 Opc = isMicroMips ? Mips::MFHI16_MM :
Mips::MFHI;
276 expandPseudoMFHiLo(MBB, MI, Opc);
278 case Mips::PseudoMFLO:
279 Opc = isMicroMips ? Mips::MFLO16_MM :
Mips::MFLO;
280 expandPseudoMFHiLo(MBB, MI, Opc);
282 case Mips::PseudoMFHI64:
283 expandPseudoMFHiLo(MBB, MI, Mips::MFHI64);
285 case Mips::PseudoMFLO64:
286 expandPseudoMFHiLo(MBB, MI, Mips::MFLO64);
288 case Mips::PseudoMTLOHI:
289 expandPseudoMTLoHi(MBB, MI, Mips::MTLO, Mips::MTHI,
false);
291 case Mips::PseudoMTLOHI64:
292 expandPseudoMTLoHi(MBB, MI, Mips::MTLO64, Mips::MTHI64,
false);
294 case Mips::PseudoMTLOHI_DSP:
295 expandPseudoMTLoHi(MBB, MI, Mips::MTLO_DSP, Mips::MTHI_DSP,
true);
297 case Mips::PseudoCVT_S_W:
298 expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1,
false);
300 case Mips::PseudoCVT_D32_W:
301 expandCvtFPInt(MBB, MI, Mips::CVT_D32_W, Mips::MTC1,
false);
303 case Mips::PseudoCVT_S_L:
304 expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1,
true);
306 case Mips::PseudoCVT_D64_W:
307 expandCvtFPInt(MBB, MI, Mips::CVT_D64_W, Mips::MTC1,
true);
309 case Mips::PseudoCVT_D64_L:
310 expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1,
true);
313 expandBuildPairF64(MBB, MI,
false);
315 case Mips::BuildPairF64_64:
316 expandBuildPairF64(MBB, MI,
true);
319 expandExtractElementF64(MBB, MI,
false);
321 case Mips::ExtractElementF64_64:
322 expandExtractElementF64(MBB, MI,
true);
324 case Mips::MIPSeh_return32:
325 case Mips::MIPSeh_return64:
326 expandEhReturn(MBB, MI);
339 case Mips::BEQ:
return Mips::BNE;
340 case Mips::BNE:
return Mips::BEQ;
341 case Mips::BGTZ:
return Mips::BLEZ;
342 case Mips::BGEZ:
return Mips::BLTZ;
343 case Mips::BLTZ:
return Mips::BGEZ;
344 case Mips::BLEZ:
return Mips::BGTZ;
345 case Mips::BEQ64:
return Mips::BNE64;
346 case Mips::BNE64:
return Mips::BEQ64;
347 case Mips::BGTZ64:
return Mips::BLEZ64;
348 case Mips::BGEZ64:
return Mips::BLTZ64;
349 case Mips::BLTZ64:
return Mips::BGEZ64;
350 case Mips::BLEZ64:
return Mips::BGTZ64;
351 case Mips::BC1T:
return Mips::BC1F;
352 case Mips::BC1F:
return Mips::BC1T;
353 case Mips::BEQZC_MM:
return Mips::BNEZC_MM;
354 case Mips::BNEZC_MM:
return Mips::BEQZC_MM;
383 unsigned *NewImm)
const {
387 unsigned Size = STI.
isABI_N64() ? 64 : 32;
388 unsigned LUi = STI.
isABI_N64() ? Mips::LUi64 : Mips::LUi;
389 unsigned ZEROReg = STI.
isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
391 &Mips::GPR64RegClass : &Mips::GPR32RegClass;
392 bool LastInstrIsADDiu = NewImm;
395 AnalyzeImm.
Analyze(Imm, Size, LastInstrIsADDiu);
398 assert(Seq.
size() && (!LastInstrIsADDiu || (Seq.
size() > 1)));
405 if (Inst->Opc == LUi)
406 BuildMI(MBB, II, DL,
get(LUi), Reg).
addImm(SignExtend64<16>(Inst->ImmOpnd));
409 .
addImm(SignExtend64<16>(Inst->ImmOpnd));
412 for (++Inst; Inst != Seq.
end() - LastInstrIsADDiu; ++Inst)
414 .
addImm(SignExtend64<16>(Inst->ImmOpnd));
416 if (LastInstrIsADDiu)
417 *NewImm = Inst->ImmOpnd;
422 unsigned MipsSEInstrInfo::getAnalyzableBrOpc(
unsigned Opc)
const {
423 return (Opc == Mips::BEQ || Opc == Mips::BNE || Opc == Mips::BGTZ ||
424 Opc == Mips::BGEZ || Opc == Mips::BLTZ || Opc == Mips::BLEZ ||
425 Opc == Mips::BEQ64 || Opc == Mips::BNE64 || Opc == Mips::BGTZ64 ||
426 Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 ||
427 Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::B ||
428 Opc == Mips::J || Opc == Mips::BEQZC_MM || Opc == Mips::BNEZC_MM) ?
435 BuildMI(MBB, I, I->getDebugLoc(),
get(Mips::PseudoReturn64))
438 BuildMI(MBB, I, I->getDebugLoc(),
get(Mips::PseudoReturn)).
addReg(Mips::RA);
441 std::pair<bool, bool>
442 MipsSEInstrInfo::compareOpndSize(
unsigned Opc,
445 assert(Desc.
NumOperands == 2 &&
"Unary instruction expected.");
447 unsigned DstRegSize =
getRegClass(Desc, 0, RI, MF)->getSize();
448 unsigned SrcRegSize =
getRegClass(Desc, 1, RI, MF)->getSize();
450 return std::make_pair(DstRegSize > SrcRegSize, DstRegSize < SrcRegSize);
455 unsigned NewOpc)
const {
456 BuildMI(MBB, I, I->getDebugLoc(),
get(NewOpc), I->getOperand(0).getReg());
463 bool HasExplicitDef)
const {
471 const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2);
479 if (HasExplicitDef) {
490 unsigned CvtOpc,
unsigned MovOpc,
492 const MCInstrDesc &CvtDesc =
get(CvtOpc), &MovDesc =
get(MovOpc);
493 const MachineOperand &Dst = I->getOperand(0), &Src = I->getOperand(1);
494 unsigned DstReg = Dst.
getReg(), SrcReg = Src.getReg(), TmpReg = DstReg;
497 bool DstIsLarger, SrcIsLarger;
499 std::tie(DstIsLarger, SrcIsLarger) =
500 compareOpndSize(CvtOpc, *MBB.
getParent());
508 BuildMI(MBB, I, DL, MovDesc, TmpReg).
addReg(SrcReg, KillSrc);
515 unsigned DstReg = I->getOperand(0).getReg();
516 unsigned SrcReg = I->getOperand(1).getReg();
517 unsigned N = I->getOperand(2).getImm();
520 assert(N < 2 &&
"Invalid immediate");
521 unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo;
545 BuildMI(MBB, I, dl,
get(FP64 ? Mips::MFHC1_D64 : Mips::MFHC1_D32), DstReg)
554 unsigned DstReg = I->getOperand(0).getReg();
555 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
598 BuildMI(MBB, I, dl,
get(FP64 ? Mips::MTHC1_D64 : Mips::MTHC1_D32), DstReg)
619 unsigned OffsetReg = I->getOperand(0).getReg();
620 unsigned TargetReg = I->getOperand(1).getReg();
627 BuildMI(MBB, I, I->getDebugLoc(),
get(ADDU), T9)
630 BuildMI(MBB, I, I->getDebugLoc(),
get(ADDU), RA)
bool hasType(MVT vt) const
hasType - return true if this TargetRegisterClass has the ValueType vt.
bool isZeroImm(const MachineOperand &op) const
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
The memory access reads data.
The memory access writes data.
const MipsABIInfo & getABI() const
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
unsigned getOppositeBranchOpc(unsigned Opc) const override
getOppositeBranchOpc - Return the inverse of the specified opcode, e.g.
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Describe properties that are true of each instruction in the target description file.
void loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const override
MipsSEInstrInfo(const MipsSubtarget &STI)
MachineMemOperand - A description of a memory reference used in the backend.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Reg
All possible values of the reg field in the ModR/M byte.
const MipsSubtarget & Subtarget
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
Adjust SP by Amount bytes.
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
unsigned getKillRegState(bool B)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
unsigned short NumOperands
void storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const override
bundle_iterator< MachineInstr, instr_iterator > iterator
const MachineOperand & getOperand(unsigned i) const
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override
unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const override
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot...
bool inMicroMipsMode() const
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static unsigned getRegClass(bool IsVgpr, unsigned RegWidth)
MachineOperand class - Representation of each machine instruction operand.
const MachineInstrBuilder & addFrameIndex(int Idx) const
unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot...
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
const MipsInstrInfo * createMipsSEInstrInfo(const MipsSubtarget &STI)
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
unsigned loadImmediate(int64_t Imm, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, DebugLoc DL, unsigned *NewImm) const
Emit a series of instructions to load an immediate.
bool isInt< 16 >(int64_t x)
unsigned getReg() const
getReg - Returns the register number.
unsigned GetPtrAdduOp() const
Primary interface to the complete machine description for the target machine.
MachineMemOperand * GetMemOperand(MachineBasicBlock &MBB, int FI, unsigned Flag) const
unsigned GetPtrAddiuOp() const
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
const MipsRegisterInfo & getRegisterInfo() const override
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.