LLVM  3.7.0
ARMAsmPrinter.cpp
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1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "ARMAsmPrinter.h"
16 #include "ARM.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMTargetMachine.h"
20 #include "ARMTargetObjectFile.h"
23 #include "MCTargetDesc/ARMMCExpr.h"
24 #include "llvm/ADT/SetVector.h"
25 #include "llvm/ADT/SmallString.h"
29 #include "llvm/IR/Constants.h"
30 #include "llvm/IR/DataLayout.h"
31 #include "llvm/IR/DebugInfo.h"
32 #include "llvm/IR/Mangler.h"
33 #include "llvm/IR/Module.h"
34 #include "llvm/IR/Type.h"
35 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/MC/MCAssembler.h"
37 #include "llvm/MC/MCContext.h"
38 #include "llvm/MC/MCELFStreamer.h"
39 #include "llvm/MC/MCInst.h"
40 #include "llvm/MC/MCInstBuilder.h"
42 #include "llvm/MC/MCSectionMachO.h"
43 #include "llvm/MC/MCStreamer.h"
44 #include "llvm/MC/MCSymbol.h"
47 #include "llvm/Support/COFF.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ELF.h"
55 #include <cctype>
56 using namespace llvm;
57 
58 #define DEBUG_TYPE "asm-printer"
59 
61  std::unique_ptr<MCStreamer> Streamer)
62  : AsmPrinter(TM, std::move(Streamer)), AFI(nullptr), MCP(nullptr),
63  InConstantPool(false) {}
64 
66  // Make sure to terminate any constant pools that were at the end
67  // of the function.
68  if (!InConstantPool)
69  return;
70  InConstantPool = false;
71  OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
72 }
73 
75  if (AFI->isThumbFunction()) {
76  OutStreamer->EmitAssemblerFlag(MCAF_Code16);
77  OutStreamer->EmitThumbFunc(CurrentFnSym);
78  }
79 
80  OutStreamer->EmitLabel(CurrentFnSym);
81 }
82 
84  uint64_t Size = TM.getDataLayout()->getTypeAllocSize(CV->getType());
85  assert(Size && "C++ constructor pointer had zero size!");
86 
88  assert(GV && "C++ constructor pointer was not a GlobalValue!");
89 
90  const MCExpr *E = MCSymbolRefExpr::create(GetARMGVSymbol(GV,
92  (Subtarget->isTargetELF()
95  OutContext);
96 
97  OutStreamer->EmitValue(E, Size);
98 }
99 
100 /// runOnMachineFunction - This uses the EmitInstruction()
101 /// method to print assembly for each instruction.
102 ///
104  AFI = MF.getInfo<ARMFunctionInfo>();
105  MCP = MF.getConstantPool();
106  Subtarget = &MF.getSubtarget<ARMSubtarget>();
107 
109 
110  if (Subtarget->isTargetCOFF()) {
111  bool Internal = MF.getFunction()->hasInternalLinkage();
115 
116  OutStreamer->BeginCOFFSymbolDef(CurrentFnSym);
117  OutStreamer->EmitCOFFSymbolStorageClass(Scl);
118  OutStreamer->EmitCOFFSymbolType(Type);
119  OutStreamer->EndCOFFSymbolDef();
120  }
121 
122  // Emit the rest of the function body.
124 
125  // If we need V4T thumb mode Register Indirect Jump pads, emit them.
126  // These are created per function, rather than per TU, since it's
127  // relatively easy to exceed the thumb branch range within a TU.
128  if (! ThumbIndirectPads.empty()) {
129  OutStreamer->EmitAssemblerFlag(MCAF_Code16);
130  EmitAlignment(1);
131  for (unsigned i = 0, e = ThumbIndirectPads.size(); i < e; i++) {
132  OutStreamer->EmitLabel(ThumbIndirectPads[i].second);
134  .addReg(ThumbIndirectPads[i].first)
135  // Add predicate operands.
136  .addImm(ARMCC::AL)
137  .addReg(0));
138  }
139  ThumbIndirectPads.clear();
140  }
141 
142  // We didn't modify anything.
143  return false;
144 }
145 
147  raw_ostream &O) {
148  const MachineOperand &MO = MI->getOperand(OpNum);
149  unsigned TF = MO.getTargetFlags();
150 
151  switch (MO.getType()) {
152  default: llvm_unreachable("<unknown operand type>");
154  unsigned Reg = MO.getReg();
156  assert(!MO.getSubReg() && "Subregs should be eliminated!");
157  if(ARM::GPRPairRegClass.contains(Reg)) {
158  const MachineFunction &MF = *MI->getParent()->getParent();
159  const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
160  Reg = TRI->getSubReg(Reg, ARM::gsub_0);
161  }
163  break;
164  }
166  int64_t Imm = MO.getImm();
167  O << '#';
168  if (TF == ARMII::MO_LO16)
169  O << ":lower16:";
170  else if (TF == ARMII::MO_HI16)
171  O << ":upper16:";
172  O << Imm;
173  break;
174  }
176  MO.getMBB()->getSymbol()->print(O, MAI);
177  return;
179  const GlobalValue *GV = MO.getGlobal();
180  if (TF & ARMII::MO_LO16)
181  O << ":lower16:";
182  else if (TF & ARMII::MO_HI16)
183  O << ":upper16:";
184  GetARMGVSymbol(GV, TF)->print(O, MAI);
185 
186  printOffset(MO.getOffset(), O);
187  if (TF == ARMII::MO_PLT)
188  O << "(PLT)";
189  break;
190  }
192  GetCPISymbol(MO.getIndex())->print(O, MAI);
193  break;
194  }
195 }
196 
197 //===--------------------------------------------------------------------===//
198 
199 MCSymbol *ARMAsmPrinter::
200 GetARMJTIPICJumpTableLabel(unsigned uid) const {
201  const DataLayout *DL = TM.getDataLayout();
203  raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "JTI"
204  << getFunctionNumber() << '_' << uid;
205  return OutContext.getOrCreateSymbol(Name);
206 }
207 
208 
209 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel() const {
210  const DataLayout *DL = TM.getDataLayout();
212  raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "SJLJEH"
213  << getFunctionNumber();
214  return OutContext.getOrCreateSymbol(Name);
215 }
216 
217 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
218  unsigned AsmVariant, const char *ExtraCode,
219  raw_ostream &O) {
220  // Does this asm operand have a single letter operand modifier?
221  if (ExtraCode && ExtraCode[0]) {
222  if (ExtraCode[1] != 0) return true; // Unknown modifier.
223 
224  switch (ExtraCode[0]) {
225  default:
226  // See if this is a generic print operand
227  return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
228  case 'a': // Print as a memory address.
229  if (MI->getOperand(OpNum).isReg()) {
230  O << "["
232  << "]";
233  return false;
234  }
235  // Fallthrough
236  case 'c': // Don't print "#" before an immediate operand.
237  if (!MI->getOperand(OpNum).isImm())
238  return true;
239  O << MI->getOperand(OpNum).getImm();
240  return false;
241  case 'P': // Print a VFP double precision register.
242  case 'q': // Print a NEON quad precision register.
243  printOperand(MI, OpNum, O);
244  return false;
245  case 'y': // Print a VFP single precision register as indexed double.
246  if (MI->getOperand(OpNum).isReg()) {
247  unsigned Reg = MI->getOperand(OpNum).getReg();
249  // Find the 'd' register that has this 's' register as a sub-register,
250  // and determine the lane number.
251  for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
252  if (!ARM::DPRRegClass.contains(*SR))
253  continue;
254  bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
255  O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
256  return false;
257  }
258  }
259  return true;
260  case 'B': // Bitwise inverse of integer or symbol without a preceding #.
261  if (!MI->getOperand(OpNum).isImm())
262  return true;
263  O << ~(MI->getOperand(OpNum).getImm());
264  return false;
265  case 'L': // The low 16 bits of an immediate constant.
266  if (!MI->getOperand(OpNum).isImm())
267  return true;
268  O << (MI->getOperand(OpNum).getImm() & 0xffff);
269  return false;
270  case 'M': { // A register range suitable for LDM/STM.
271  if (!MI->getOperand(OpNum).isReg())
272  return true;
273  const MachineOperand &MO = MI->getOperand(OpNum);
274  unsigned RegBegin = MO.getReg();
275  // This takes advantage of the 2 operand-ness of ldm/stm and that we've
276  // already got the operands in registers that are operands to the
277  // inline asm statement.
278  O << "{";
279  if (ARM::GPRPairRegClass.contains(RegBegin)) {
281  unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
282  O << ARMInstPrinter::getRegisterName(Reg0) << ", ";
283  RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
284  }
285  O << ARMInstPrinter::getRegisterName(RegBegin);
286 
287  // FIXME: The register allocator not only may not have given us the
288  // registers in sequence, but may not be in ascending registers. This
289  // will require changes in the register allocator that'll need to be
290  // propagated down here if the operands change.
291  unsigned RegOps = OpNum + 1;
292  while (MI->getOperand(RegOps).isReg()) {
293  O << ", "
295  RegOps++;
296  }
297 
298  O << "}";
299 
300  return false;
301  }
302  case 'R': // The most significant register of a pair.
303  case 'Q': { // The least significant register of a pair.
304  if (OpNum == 0)
305  return true;
306  const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
307  if (!FlagsOP.isImm())
308  return true;
309  unsigned Flags = FlagsOP.getImm();
310 
311  // This operand may not be the one that actually provides the register. If
312  // it's tied to a previous one then we should refer instead to that one
313  // for registers and their classes.
314  unsigned TiedIdx;
315  if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
316  for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
317  unsigned OpFlags = MI->getOperand(OpNum).getImm();
318  OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
319  }
320  Flags = MI->getOperand(OpNum).getImm();
321 
322  // Later code expects OpNum to be pointing at the register rather than
323  // the flags.
324  OpNum += 1;
325  }
326 
327  unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
328  unsigned RC;
330  if (RC == ARM::GPRPairRegClassID) {
331  if (NumVals != 1)
332  return true;
333  const MachineOperand &MO = MI->getOperand(OpNum);
334  if (!MO.isReg())
335  return true;
337  unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
338  ARM::gsub_0 : ARM::gsub_1);
340  return false;
341  }
342  if (NumVals != 2)
343  return true;
344  unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
345  if (RegOp >= MI->getNumOperands())
346  return true;
347  const MachineOperand &MO = MI->getOperand(RegOp);
348  if (!MO.isReg())
349  return true;
350  unsigned Reg = MO.getReg();
352  return false;
353  }
354 
355  case 'e': // The low doubleword register of a NEON quad register.
356  case 'f': { // The high doubleword register of a NEON quad register.
357  if (!MI->getOperand(OpNum).isReg())
358  return true;
359  unsigned Reg = MI->getOperand(OpNum).getReg();
360  if (!ARM::QPRRegClass.contains(Reg))
361  return true;
363  unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
364  ARM::dsub_0 : ARM::dsub_1);
365  O << ARMInstPrinter::getRegisterName(SubReg);
366  return false;
367  }
368 
369  // This modifier is not yet supported.
370  case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
371  return true;
372  case 'H': { // The highest-numbered register of a pair.
373  const MachineOperand &MO = MI->getOperand(OpNum);
374  if (!MO.isReg())
375  return true;
376  const MachineFunction &MF = *MI->getParent()->getParent();
377  const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
378  unsigned Reg = MO.getReg();
379  if(!ARM::GPRPairRegClass.contains(Reg))
380  return false;
381  Reg = TRI->getSubReg(Reg, ARM::gsub_1);
383  return false;
384  }
385  }
386  }
387 
388  printOperand(MI, OpNum, O);
389  return false;
390 }
391 
393  unsigned OpNum, unsigned AsmVariant,
394  const char *ExtraCode,
395  raw_ostream &O) {
396  // Does this asm operand have a single letter operand modifier?
397  if (ExtraCode && ExtraCode[0]) {
398  if (ExtraCode[1] != 0) return true; // Unknown modifier.
399 
400  switch (ExtraCode[0]) {
401  case 'A': // A memory operand for a VLD1/VST1 instruction.
402  default: return true; // Unknown modifier.
403  case 'm': // The base register of a memory operand.
404  if (!MI->getOperand(OpNum).isReg())
405  return true;
407  return false;
408  }
409  }
410 
411  const MachineOperand &MO = MI->getOperand(OpNum);
412  assert(MO.isReg() && "unexpected inline asm memory operand");
413  O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
414  return false;
415 }
416 
417 static bool isThumb(const MCSubtargetInfo& STI) {
418  return STI.getFeatureBits()[ARM::ModeThumb];
419 }
420 
422  const MCSubtargetInfo *EndInfo) const {
423  // If either end mode is unknown (EndInfo == NULL) or different than
424  // the start mode, then restore the start mode.
425  const bool WasThumb = isThumb(StartInfo);
426  if (!EndInfo || WasThumb != isThumb(*EndInfo)) {
427  OutStreamer->EmitAssemblerFlag(WasThumb ? MCAF_Code16 : MCAF_Code32);
428  }
429 }
430 
432  const Triple &TT = TM.getTargetTriple();
433  // Use unified assembler syntax.
434  OutStreamer->EmitAssemblerFlag(MCAF_SyntaxUnified);
435 
436  // Emit ARM Build Attributes
437  if (TT.isOSBinFormatELF())
438  emitAttributes();
439 
440  // Use the triple's architecture and subarchitecture to determine
441  // if we're thumb for the purposes of the top level code16 assembler
442  // flag.
443  bool isThumb = TT.getArch() == Triple::thumb ||
444  TT.getArch() == Triple::thumbeb ||
447  if (!M.getModuleInlineAsm().empty() && isThumb)
448  OutStreamer->EmitAssemblerFlag(MCAF_Code16);
449 }
450 
451 static void
454  // L_foo$stub:
455  OutStreamer.EmitLabel(StubLabel);
456  // .indirect_symbol _foo
457  OutStreamer.EmitSymbolAttribute(MCSym.getPointer(), MCSA_IndirectSymbol);
458 
459  if (MCSym.getInt())
460  // External to current translation unit.
461  OutStreamer.EmitIntValue(0, 4/*size*/);
462  else
463  // Internal to current translation unit.
464  //
465  // When we place the LSDA into the TEXT section, the type info
466  // pointers need to be indirect and pc-rel. We accomplish this by
467  // using NLPs; however, sometimes the types are local to the file.
468  // We need to fill in the value for the NLP in those cases.
469  OutStreamer.EmitValue(
470  MCSymbolRefExpr::create(MCSym.getPointer(), OutStreamer.getContext()),
471  4 /*size*/);
472 }
473 
474 
476  const Triple &TT = TM.getTargetTriple();
477  if (TT.isOSBinFormatMachO()) {
478  // All darwin targets use mach-o.
479  const TargetLoweringObjectFileMachO &TLOFMacho =
480  static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
481  MachineModuleInfoMachO &MMIMacho =
483 
484  // Output non-lazy-pointers for external and common global variables.
486 
487  if (!Stubs.empty()) {
488  // Switch with ".non_lazy_symbol_pointer" directive.
489  OutStreamer->SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
490  EmitAlignment(2);
491 
492  for (auto &Stub : Stubs)
493  emitNonLazySymbolPointer(*OutStreamer, Stub.first, Stub.second);
494 
495  Stubs.clear();
496  OutStreamer->AddBlankLine();
497  }
498 
499  Stubs = MMIMacho.GetHiddenGVStubList();
500  if (!Stubs.empty()) {
501  OutStreamer->SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
502  EmitAlignment(2);
503 
504  for (auto &Stub : Stubs)
505  emitNonLazySymbolPointer(*OutStreamer, Stub.first, Stub.second);
506 
507  Stubs.clear();
508  OutStreamer->AddBlankLine();
509  }
510 
511  // Funny Darwin hack: This flag tells the linker that no global symbols
512  // contain code that falls through to other global symbols (e.g. the obvious
513  // implementation of multiple entry points). If this doesn't occur, the
514  // linker can safely perform dead code stripping. Since LLVM never
515  // generates code that does this, it is always safe to set.
516  OutStreamer->EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
517  }
518 }
519 
520 //===----------------------------------------------------------------------===//
521 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
522 // FIXME:
523 // The following seem like one-off assembler flags, but they actually need
524 // to appear in the .ARM.attributes section in ELF.
525 // Instead of subclassing the MCELFStreamer, we do the work here.
526 
528  const ARMSubtarget *Subtarget) {
529  if (CPU == "xscale")
530  return ARMBuildAttrs::v5TEJ;
531 
532  if (Subtarget->hasV8Ops())
533  return ARMBuildAttrs::v8;
534  else if (Subtarget->hasV7Ops()) {
535  if (Subtarget->isMClass() && Subtarget->hasThumb2DSP())
536  return ARMBuildAttrs::v7E_M;
537  return ARMBuildAttrs::v7;
538  } else if (Subtarget->hasV6T2Ops())
539  return ARMBuildAttrs::v6T2;
540  else if (Subtarget->hasV6MOps())
541  return ARMBuildAttrs::v6S_M;
542  else if (Subtarget->hasV6Ops())
543  return ARMBuildAttrs::v6;
544  else if (Subtarget->hasV5TEOps())
545  return ARMBuildAttrs::v5TE;
546  else if (Subtarget->hasV5TOps())
547  return ARMBuildAttrs::v5T;
548  else if (Subtarget->hasV4TOps())
549  return ARMBuildAttrs::v4T;
550  else
551  return ARMBuildAttrs::v4;
552 }
553 
554 void ARMAsmPrinter::emitAttributes() {
555  MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
556  ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
557 
559 
560  ATS.switchVendor("aeabi");
561 
562  // Compute ARM ELF Attributes based on the default subtarget that
563  // we'd have constructed. The existing ARM behavior isn't LTO clean
564  // anyhow.
565  // FIXME: For ifunc related functions we could iterate over and look
566  // for a feature string that doesn't match the default one.
567  const Triple &TT = TM.getTargetTriple();
568  StringRef CPU = TM.getTargetCPU();
570  std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
571  if (!FS.empty()) {
572  if (!ArchFS.empty())
573  ArchFS = (Twine(ArchFS) + "," + FS).str();
574  else
575  ArchFS = FS;
576  }
577  const ARMBaseTargetMachine &ATM =
578  static_cast<const ARMBaseTargetMachine &>(TM);
579  const ARMSubtarget STI(TT, CPU, ArchFS, ATM, ATM.isLittleEndian());
580 
581  std::string CPUString = STI.getCPUString();
582 
583  if (CPUString.find("generic") != 0) { //CPUString doesn't start with "generic"
584  // FIXME: remove krait check when GNU tools support krait cpu
585  if (STI.isKrait()) {
586  ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a9");
587  // We consider krait as a "cortex-a9" + hwdiv CPU
588  // Enable hwdiv through ".arch_extension idiv"
589  if (STI.hasDivide() || STI.hasDivideInARMMode())
591  } else
593  }
594 
595  ATS.emitAttribute(ARMBuildAttrs::CPU_arch, getArchForCPU(CPUString, &STI));
596 
597  // Tag_CPU_arch_profile must have the default value of 0 when "Architecture
598  // profile is not applicable (e.g. pre v7, or cross-profile code)".
599  if (STI.hasV7Ops()) {
600  if (STI.isAClass()) {
603  } else if (STI.isRClass()) {
606  } else if (STI.isMClass()) {
609  }
610  }
611 
613  STI.hasARMOps() ? ARMBuildAttrs::Allowed
615  if (STI.isThumb1Only()) {
617  } else if (STI.hasThumb2()) {
620  }
621 
622  if (STI.hasNEON()) {
623  /* NEON is not exactly a VFP architecture, but GAS emit one of
624  * neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
625  if (STI.hasFPARMv8()) {
626  if (STI.hasCrypto())
628  else
630  } else if (STI.hasVFP4())
632  else
633  ATS.emitFPU(STI.hasFP16() ? ARM::FK_NEON_FP16 : ARM::FK_NEON);
634  // Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
635  if (STI.hasV8Ops())
637  STI.hasV8_1aOps() ? ARMBuildAttrs::AllowNeonARMv8_1a:
639  } else {
640  if (STI.hasFPARMv8())
641  // FPv5 and FP-ARMv8 have the same instructions, so are modeled as one
642  // FPU, but there are two different names for it depending on the CPU.
643  ATS.emitFPU(STI.hasD16()
644  ? (STI.isFPOnlySP() ? ARM::FK_FPV5_SP_D16 : ARM::FK_FPV5_D16)
645  : ARM::FK_FP_ARMV8);
646  else if (STI.hasVFP4())
647  ATS.emitFPU(STI.hasD16()
648  ? (STI.isFPOnlySP() ? ARM::FK_FPV4_SP_D16 : ARM::FK_VFPV4_D16)
649  : ARM::FK_VFPV4);
650  else if (STI.hasVFP3())
651  ATS.emitFPU(STI.hasD16()
652  // +d16
653  ? (STI.isFPOnlySP()
654  ? (STI.hasFP16() ? ARM::FK_VFPV3XD_FP16 : ARM::FK_VFPV3XD)
655  : (STI.hasFP16() ? ARM::FK_VFPV3_D16_FP16 : ARM::FK_VFPV3_D16))
656  // -d16
657  : (STI.hasFP16() ? ARM::FK_VFPV3_FP16 : ARM::FK_VFPV3));
658  else if (STI.hasVFP2())
659  ATS.emitFPU(ARM::FK_VFPV2);
660  }
661 
662  if (TM.getRelocationModel() == Reloc::PIC_) {
663  // PIC specific attributes.
670  } else {
671  // Allow direct addressing of imported data for all other relocation models.
674  }
675 
676  // Signal various FP modes.
677  if (!TM.Options.UnsafeFPMath) {
681 
682  // If the user has permitted this code to choose the IEEE 754
683  // rounding at run-time, emit the rounding attribute.
686  } else {
687  if (!STI.hasVFP2()) {
688  // When the target doesn't have an FPU (by design or
689  // intention), the assumptions made on the software support
690  // mirror that of the equivalent hardware support *if it
691  // existed*. For v7 and better we indicate that denormals are
692  // flushed preserving sign, and for V6 we indicate that
693  // denormals are flushed to positive zero.
694  if (STI.hasV7Ops())
697  } else if (STI.hasVFP3()) {
698  // In VFPv4, VFPv4U, VFPv3, or VFPv3U, it is preserved. That is,
699  // the sign bit of the zero matches the sign bit of the input or
700  // result that is being flushed to zero.
703  }
704  // For VFPv2 implementations it is implementation defined as
705  // to whether denormals are flushed to positive zero or to
706  // whatever the sign of zero is (ARM v7AR ARM 2.7.5). Historically
707  // LLVM has chosen to flush this to positive zero (most likely for
708  // GCC compatibility), so that's the chosen value here (the
709  // absence of its emission implies zero).
710  }
711 
712  // TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath is the
713  // equivalent of GCC's -ffinite-math-only flag.
717  else
720 
721  if (STI.allowsUnalignedMem())
724  else
727 
728  // FIXME: add more flags to ARMBuildAttributes.h
729  // 8-bytes alignment stuff.
732 
733  // ABI_HardFP_use attribute to indicate single precision FP.
734  if (STI.isFPOnlySP())
737 
738  // Hard float. Use both S and D registers and conform to AAPCS-VFP.
739  if (STI.isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
741 
742  // FIXME: Should we signal R9 usage?
743 
744  if (STI.hasFP16())
746 
747  // FIXME: To support emitting this build attribute as GCC does, the
748  // -mfp16-format option and associated plumbing must be
749  // supported. For now the __fp16 type is exposed by default, so this
750  // attribute should be emitted with value 1.
753 
754  if (STI.hasMPExtension())
756 
757  // Hardware divide in ARM mode is part of base arch, starting from ARMv8.
758  // If only Thumb hwdiv is present, it must also be in base arch (ARMv7-R/M).
759  // It is not possible to produce DisallowDIV: if hwdiv is present in the base
760  // arch, supplying -hwdiv downgrades the effective arch, via ClearImpliedBits.
761  // AllowDIVExt is only emitted if hwdiv isn't available in the base arch;
762  // otherwise, the default value (AllowDIVIfExists) applies.
763  if (STI.hasDivideInARMMode() && !STI.hasV8Ops())
765 
766  if (MMI) {
767  if (const Module *SourceModule = MMI->getModule()) {
768  // ABI_PCS_wchar_t to indicate wchar_t width
769  // FIXME: There is no way to emit value 0 (wchar_t prohibited).
770  if (auto WCharWidthValue = mdconst::extract_or_null<ConstantInt>(
771  SourceModule->getModuleFlag("wchar_size"))) {
772  int WCharWidth = WCharWidthValue->getZExtValue();
773  assert((WCharWidth == 2 || WCharWidth == 4) &&
774  "wchar_t width must be 2 or 4 bytes");
776  }
777 
778  // ABI_enum_size to indicate enum width
779  // FIXME: There is no way to emit value 0 (enums prohibited) or value 3
780  // (all enums contain a value needing 32 bits to encode).
781  if (auto EnumWidthValue = mdconst::extract_or_null<ConstantInt>(
782  SourceModule->getModuleFlag("min_enum_size"))) {
783  int EnumWidth = EnumWidthValue->getZExtValue();
784  assert((EnumWidth == 1 || EnumWidth == 4) &&
785  "Minimum enum width must be 1 or 4 bytes");
786  int EnumBuildAttr = EnumWidth == 1 ? 1 : 2;
787  ATS.emitAttribute(ARMBuildAttrs::ABI_enum_size, EnumBuildAttr);
788  }
789  }
790  }
791 
792  // TODO: We currently only support either reserving the register, or treating
793  // it as another callee-saved register, but not as SB or a TLS pointer; It
794  // would instead be nicer to push this from the frontend as metadata, as we do
795  // for the wchar and enum size tags
796  if (STI.isR9Reserved())
798  else
800 
801  if (STI.hasTrustZone() && STI.hasVirtualization())
804  else if (STI.hasTrustZone())
807  else if (STI.hasVirtualization())
810 
812 }
813 
814 //===----------------------------------------------------------------------===//
815 
816 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
817  unsigned LabelId, MCContext &Ctx) {
818 
819  MCSymbol *Label = Ctx.getOrCreateSymbol(Twine(Prefix)
820  + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
821  return Label;
822 }
823 
826  switch (Modifier) {
831  case ARMCP::GOT: return MCSymbolRefExpr::VK_GOT;
833  }
834  llvm_unreachable("Invalid ARMCPModifier!");
835 }
836 
837 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
838  unsigned char TargetFlags) {
839  if (Subtarget->isTargetMachO()) {
840  bool IsIndirect = (TargetFlags & ARMII::MO_NONLAZY) &&
841  Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
842 
843  if (!IsIndirect)
844  return getSymbol(GV);
845 
846  // FIXME: Remove this when Darwin transition to @GOT like syntax.
847  MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
848  MachineModuleInfoMachO &MMIMachO =
851  GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym)
852  : MMIMachO.getGVStubEntry(MCSym);
853  if (!StubSym.getPointer())
855  !GV->hasInternalLinkage());
856  return MCSym;
857  } else if (Subtarget->isTargetCOFF()) {
858  assert(Subtarget->isTargetWindows() &&
859  "Windows is the only supported COFF target");
860 
861  bool IsIndirect = (TargetFlags & ARMII::MO_DLLIMPORT);
862  if (!IsIndirect)
863  return getSymbol(GV);
864 
866  Name = "__imp_";
867  getNameWithPrefix(Name, GV);
868 
869  return OutContext.getOrCreateSymbol(Name);
870  } else if (Subtarget->isTargetELF()) {
871  return getSymbol(GV);
872  }
873  llvm_unreachable("unexpected target");
874 }
875 
876 void ARMAsmPrinter::
878  const DataLayout *DL = TM.getDataLayout();
879  int Size = TM.getDataLayout()->getTypeAllocSize(MCPV->getType());
880 
881  ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
882 
883  MCSymbol *MCSym;
884  if (ACPV->isLSDA()) {
885  MCSym = getCurExceptionSym();
886  } else if (ACPV->isBlockAddress()) {
887  const BlockAddress *BA =
888  cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
889  MCSym = GetBlockAddressSymbol(BA);
890  } else if (ACPV->isGlobalValue()) {
891  const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
892 
893  // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
894  // flag the global as MO_NONLAZY.
895  unsigned char TF = Subtarget->isTargetMachO() ? ARMII::MO_NONLAZY : 0;
896  MCSym = GetARMGVSymbol(GV, TF);
897  } else if (ACPV->isMachineBasicBlock()) {
898  const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
899  MCSym = MBB->getSymbol();
900  } else {
901  assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
902  const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
903  MCSym = GetExternalSymbolSymbol(Sym);
904  }
905 
906  // Create an MCSymbol for the reference.
907  const MCExpr *Expr =
909  OutContext);
910 
911  if (ACPV->getPCAdjustment()) {
914  ACPV->getLabelId(),
915  OutContext);
916  const MCExpr *PCRelExpr = MCSymbolRefExpr::create(PCLabel, OutContext);
917  PCRelExpr =
918  MCBinaryExpr::createAdd(PCRelExpr,
920  OutContext),
921  OutContext);
922  if (ACPV->mustAddCurrentAddress()) {
923  // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
924  // label, so just emit a local label end reference that instead.
926  OutStreamer->EmitLabel(DotSym);
927  const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext);
928  PCRelExpr = MCBinaryExpr::createSub(PCRelExpr, DotExpr, OutContext);
929  }
930  Expr = MCBinaryExpr::createSub(Expr, PCRelExpr, OutContext);
931  }
932  OutStreamer->EmitValue(Expr, Size);
933 }
934 
936  const MachineOperand &MO1 = MI->getOperand(1);
937  unsigned JTI = MO1.getIndex();
938 
939  // Make sure the Thumb jump table is 4-byte aligned. This will be a nop for
940  // ARM mode tables.
941  EmitAlignment(2);
942 
943  // Emit a label for the jump table.
944  MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
945  OutStreamer->EmitLabel(JTISymbol);
946 
947  // Mark the jump table as data-in-code.
948  OutStreamer->EmitDataRegion(MCDR_DataRegionJT32);
949 
950  // Emit each entry of the table.
951  const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
952  const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
953  const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
954 
955  for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
956  MachineBasicBlock *MBB = JTBBs[i];
957  // Construct an MCExpr for the entry. We want a value of the form:
958  // (BasicBlockAddr - TableBeginAddr)
959  //
960  // For example, a table with entries jumping to basic blocks BB0 and BB1
961  // would look like:
962  // LJTI_0_0:
963  // .word (LBB0 - LJTI_0_0)
964  // .word (LBB1 - LJTI_0_0)
965  const MCExpr *Expr = MCSymbolRefExpr::create(MBB->getSymbol(), OutContext);
966 
968  Expr = MCBinaryExpr::createSub(Expr, MCSymbolRefExpr::create(JTISymbol,
969  OutContext),
970  OutContext);
971  // If we're generating a table of Thumb addresses in static relocation
972  // model, we need to add one to keep interworking correctly.
973  else if (AFI->isThumbFunction())
975  OutContext);
976  OutStreamer->EmitValue(Expr, 4);
977  }
978  // Mark the end of jump table data-in-code region.
979  OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
980 }
981 
983  const MachineOperand &MO1 = MI->getOperand(1);
984  unsigned JTI = MO1.getIndex();
985 
986  MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
987  OutStreamer->EmitLabel(JTISymbol);
988 
989  // Emit each entry of the table.
990  const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
991  const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
992  const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
993 
994  for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
995  MachineBasicBlock *MBB = JTBBs[i];
996  const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(MBB->getSymbol(),
997  OutContext);
998  // If this isn't a TBB or TBH, the entries are direct branch instructions.
1000  .addExpr(MBBSymbolExpr)
1001  .addImm(ARMCC::AL)
1002  .addReg(0));
1003  }
1004 }
1005 
1007  unsigned OffsetWidth) {
1008  assert((OffsetWidth == 1 || OffsetWidth == 2) && "invalid tbb/tbh width");
1009  const MachineOperand &MO1 = MI->getOperand(1);
1010  unsigned JTI = MO1.getIndex();
1011 
1012  MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
1013  OutStreamer->EmitLabel(JTISymbol);
1014 
1015  // Emit each entry of the table.
1016  const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1017  const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1018  const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1019 
1020  // Mark the jump table as data-in-code.
1021  OutStreamer->EmitDataRegion(OffsetWidth == 1 ? MCDR_DataRegionJT8
1023 
1024  for (auto MBB : JTBBs) {
1025  const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(MBB->getSymbol(),
1026  OutContext);
1027  // Otherwise it's an offset from the dispatch instruction. Construct an
1028  // MCExpr for the entry. We want a value of the form:
1029  // (BasicBlockAddr - TBBInstAddr + 4) / 2
1030  //
1031  // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1032  // would look like:
1033  // LJTI_0_0:
1034  // .byte (LBB0 - (LCPI0_0 + 4)) / 2
1035  // .byte (LBB1 - (LCPI0_0 + 4)) / 2
1036  // where LCPI0_0 is a label defined just before the TBB instruction using
1037  // this table.
1038  MCSymbol *TBInstPC = GetCPISymbol(MI->getOperand(0).getImm());
1039  const MCExpr *Expr = MCBinaryExpr::createAdd(
1042  Expr = MCBinaryExpr::createSub(MBBSymbolExpr, Expr, OutContext);
1044  OutContext);
1045  OutStreamer->EmitValue(Expr, OffsetWidth);
1046  }
1047  // Mark the end of jump table data-in-code region. 32-bit offsets use
1048  // actual branch instructions here, so we don't mark those as a data-region
1049  // at all.
1050  OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
1051 
1052  // Make sure the next instruction is 2-byte aligned.
1053  EmitAlignment(1);
1054 }
1055 
1056 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1057  assert(MI->getFlag(MachineInstr::FrameSetup) &&
1058  "Only instruction which are involved into frame setup code are allowed");
1059 
1060  MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
1061  ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
1062  const MachineFunction &MF = *MI->getParent()->getParent();
1063  const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
1064  const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
1065 
1066  unsigned FramePtr = RegInfo->getFrameRegister(MF);
1067  unsigned Opc = MI->getOpcode();
1068  unsigned SrcReg, DstReg;
1069 
1070  if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
1071  // Two special cases:
1072  // 1) tPUSH does not have src/dst regs.
1073  // 2) for Thumb1 code we sometimes materialize the constant via constpool
1074  // load. Yes, this is pretty fragile, but for now I don't see better
1075  // way... :(
1076  SrcReg = DstReg = ARM::SP;
1077  } else {
1078  SrcReg = MI->getOperand(1).getReg();
1079  DstReg = MI->getOperand(0).getReg();
1080  }
1081 
1082  // Try to figure out the unwinding opcode out of src / dst regs.
1083  if (MI->mayStore()) {
1084  // Register saves.
1085  assert(DstReg == ARM::SP &&
1086  "Only stack pointer as a destination reg is supported");
1087 
1088  SmallVector<unsigned, 4> RegList;
1089  // Skip src & dst reg, and pred ops.
1090  unsigned StartOp = 2 + 2;
1091  // Use all the operands.
1092  unsigned NumOffset = 0;
1093 
1094  switch (Opc) {
1095  default:
1096  MI->dump();
1097  llvm_unreachable("Unsupported opcode for unwinding information");
1098  case ARM::tPUSH:
1099  // Special case here: no src & dst reg, but two extra imp ops.
1100  StartOp = 2; NumOffset = 2;
1101  case ARM::STMDB_UPD:
1102  case ARM::t2STMDB_UPD:
1103  case ARM::VSTMDDB_UPD:
1104  assert(SrcReg == ARM::SP &&
1105  "Only stack pointer as a source reg is supported");
1106  for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1107  i != NumOps; ++i) {
1108  const MachineOperand &MO = MI->getOperand(i);
1109  // Actually, there should never be any impdef stuff here. Skip it
1110  // temporary to workaround PR11902.
1111  if (MO.isImplicit())
1112  continue;
1113  RegList.push_back(MO.getReg());
1114  }
1115  break;
1116  case ARM::STR_PRE_IMM:
1117  case ARM::STR_PRE_REG:
1118  case ARM::t2STR_PRE:
1119  assert(MI->getOperand(2).getReg() == ARM::SP &&
1120  "Only stack pointer as a source reg is supported");
1121  RegList.push_back(SrcReg);
1122  break;
1123  }
1125  ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1126  } else {
1127  // Changes of stack / frame pointer.
1128  if (SrcReg == ARM::SP) {
1129  int64_t Offset = 0;
1130  switch (Opc) {
1131  default:
1132  MI->dump();
1133  llvm_unreachable("Unsupported opcode for unwinding information");
1134  case ARM::MOVr:
1135  case ARM::tMOVr:
1136  Offset = 0;
1137  break;
1138  case ARM::ADDri:
1139  Offset = -MI->getOperand(2).getImm();
1140  break;
1141  case ARM::SUBri:
1142  case ARM::t2SUBri:
1143  Offset = MI->getOperand(2).getImm();
1144  break;
1145  case ARM::tSUBspi:
1146  Offset = MI->getOperand(2).getImm()*4;
1147  break;
1148  case ARM::tADDspi:
1149  case ARM::tADDrSPi:
1150  Offset = -MI->getOperand(2).getImm()*4;
1151  break;
1152  case ARM::tLDRpci: {
1153  // Grab the constpool index and check, whether it corresponds to
1154  // original or cloned constpool entry.
1155  unsigned CPI = MI->getOperand(1).getIndex();
1156  const MachineConstantPool *MCP = MF.getConstantPool();
1157  if (CPI >= MCP->getConstants().size())
1158  CPI = AFI.getOriginalCPIdx(CPI);
1159  assert(CPI != -1U && "Invalid constpool index");
1160 
1161  // Derive the actual offset.
1162  const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1163  assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1164  // FIXME: Check for user, it should be "add" instruction!
1165  Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1166  break;
1167  }
1168  }
1169 
1171  if (DstReg == FramePtr && FramePtr != ARM::SP)
1172  // Set-up of the frame pointer. Positive values correspond to "add"
1173  // instruction.
1174  ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
1175  else if (DstReg == ARM::SP) {
1176  // Change of SP by an offset. Positive values correspond to "sub"
1177  // instruction.
1178  ATS.emitPad(Offset);
1179  } else {
1180  // Move of SP to a register. Positive values correspond to an "add"
1181  // instruction.
1182  ATS.emitMovSP(DstReg, -Offset);
1183  }
1184  }
1185  } else if (DstReg == ARM::SP) {
1186  MI->dump();
1187  llvm_unreachable("Unsupported opcode for unwinding information");
1188  }
1189  else {
1190  MI->dump();
1191  llvm_unreachable("Unsupported opcode for unwinding information");
1192  }
1193  }
1194 }
1195 
1196 // Simple pseudo-instructions have their lowering (with expansion to real
1197 // instructions) auto-generated.
1198 #include "ARMGenMCPseudoLowering.inc"
1199 
1201  const DataLayout *DL = TM.getDataLayout();
1202 
1203  // If we just ended a constant pool, mark it as such.
1204  if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1205  OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
1206  InConstantPool = false;
1207  }
1208 
1209  // Emit unwinding stuff for frame-related instructions
1210  if (Subtarget->isTargetEHABICompatible() &&
1212  EmitUnwindingInstruction(MI);
1213 
1214  // Do any auto-generated pseudo lowerings.
1215  if (emitPseudoExpansionLowering(*OutStreamer, MI))
1216  return;
1217 
1218  assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1219  "Pseudo flag setting opcode should be expanded early");
1220 
1221  // Check for manual lowerings.
1222  unsigned Opc = MI->getOpcode();
1223  switch (Opc) {
1224  case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1225  case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
1226  case ARM::LEApcrel:
1227  case ARM::tLEApcrel:
1228  case ARM::t2LEApcrel: {
1229  // FIXME: Need to also handle globals and externals
1230  MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
1232  ARM::t2LEApcrel ? ARM::t2ADR
1233  : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1234  : ARM::ADR))
1235  .addReg(MI->getOperand(0).getReg())
1236  .addExpr(MCSymbolRefExpr::create(CPISymbol, OutContext))
1237  // Add predicate operands.
1238  .addImm(MI->getOperand(2).getImm())
1239  .addReg(MI->getOperand(3).getReg()));
1240  return;
1241  }
1242  case ARM::LEApcrelJT:
1243  case ARM::tLEApcrelJT:
1244  case ARM::t2LEApcrelJT: {
1245  MCSymbol *JTIPICSymbol =
1246  GetARMJTIPICJumpTableLabel(MI->getOperand(1).getIndex());
1248  ARM::t2LEApcrelJT ? ARM::t2ADR
1249  : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1250  : ARM::ADR))
1251  .addReg(MI->getOperand(0).getReg())
1252  .addExpr(MCSymbolRefExpr::create(JTIPICSymbol, OutContext))
1253  // Add predicate operands.
1254  .addImm(MI->getOperand(2).getImm())
1255  .addReg(MI->getOperand(3).getReg()));
1256  return;
1257  }
1258  // Darwin call instructions are just normal call instructions with different
1259  // clobber semantics (they clobber R9).
1260  case ARM::BX_CALL: {
1262  .addReg(ARM::LR)
1263  .addReg(ARM::PC)
1264  // Add predicate operands.
1265  .addImm(ARMCC::AL)
1266  .addReg(0)
1267  // Add 's' bit operand (always reg0 for this)
1268  .addReg(0));
1269 
1271  .addReg(MI->getOperand(0).getReg()));
1272  return;
1273  }
1274  case ARM::tBX_CALL: {
1275  if (Subtarget->hasV5TOps())
1276  llvm_unreachable("Expected BLX to be selected for v5t+");
1277 
1278  // On ARM v4t, when doing a call from thumb mode, we need to ensure
1279  // that the saved lr has its LSB set correctly (the arch doesn't
1280  // have blx).
1281  // So here we generate a bl to a small jump pad that does bx rN.
1282  // The jump pads are emitted after the function body.
1283 
1284  unsigned TReg = MI->getOperand(0).getReg();
1285  MCSymbol *TRegSym = nullptr;
1286  for (unsigned i = 0, e = ThumbIndirectPads.size(); i < e; i++) {
1287  if (ThumbIndirectPads[i].first == TReg) {
1288  TRegSym = ThumbIndirectPads[i].second;
1289  break;
1290  }
1291  }
1292 
1293  if (!TRegSym) {
1294  TRegSym = OutContext.createTempSymbol();
1295  ThumbIndirectPads.push_back(std::make_pair(TReg, TRegSym));
1296  }
1297 
1298  // Create a link-saving branch to the Reg Indirect Jump Pad.
1300  // Predicate comes first here.
1301  .addImm(ARMCC::AL).addReg(0)
1302  .addExpr(MCSymbolRefExpr::create(TRegSym, OutContext)));
1303  return;
1304  }
1305  case ARM::BMOVPCRX_CALL: {
1307  .addReg(ARM::LR)
1308  .addReg(ARM::PC)
1309  // Add predicate operands.
1310  .addImm(ARMCC::AL)
1311  .addReg(0)
1312  // Add 's' bit operand (always reg0 for this)
1313  .addReg(0));
1314 
1316  .addReg(ARM::PC)
1317  .addReg(MI->getOperand(0).getReg())
1318  // Add predicate operands.
1319  .addImm(ARMCC::AL)
1320  .addReg(0)
1321  // Add 's' bit operand (always reg0 for this)
1322  .addReg(0));
1323  return;
1324  }
1325  case ARM::BMOVPCB_CALL: {
1327  .addReg(ARM::LR)
1328  .addReg(ARM::PC)
1329  // Add predicate operands.
1330  .addImm(ARMCC::AL)
1331  .addReg(0)
1332  // Add 's' bit operand (always reg0 for this)
1333  .addReg(0));
1334 
1335  const MachineOperand &Op = MI->getOperand(0);
1336  const GlobalValue *GV = Op.getGlobal();
1337  const unsigned TF = Op.getTargetFlags();
1338  MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1339  const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1341  .addExpr(GVSymExpr)
1342  // Add predicate operands.
1343  .addImm(ARMCC::AL)
1344  .addReg(0));
1345  return;
1346  }
1347  case ARM::MOVi16_ga_pcrel:
1348  case ARM::t2MOVi16_ga_pcrel: {
1349  MCInst TmpInst;
1350  TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1351  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1352 
1353  unsigned TF = MI->getOperand(1).getTargetFlags();
1354  const GlobalValue *GV = MI->getOperand(1).getGlobal();
1355  MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1356  const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1357 
1358  MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
1360  MI->getOperand(2).getImm(), OutContext);
1361  const MCExpr *LabelSymExpr= MCSymbolRefExpr::create(LabelSym, OutContext);
1362  unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1363  const MCExpr *PCRelExpr =
1365  MCBinaryExpr::createAdd(LabelSymExpr,
1368  TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
1369 
1370  // Add predicate operands.
1372  TmpInst.addOperand(MCOperand::createReg(0));
1373  // Add 's' bit operand (always reg0 for this)
1374  TmpInst.addOperand(MCOperand::createReg(0));
1375  EmitToStreamer(*OutStreamer, TmpInst);
1376  return;
1377  }
1378  case ARM::MOVTi16_ga_pcrel:
1379  case ARM::t2MOVTi16_ga_pcrel: {
1380  MCInst TmpInst;
1381  TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1382  ? ARM::MOVTi16 : ARM::t2MOVTi16);
1383  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1384  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
1385 
1386  unsigned TF = MI->getOperand(2).getTargetFlags();
1387  const GlobalValue *GV = MI->getOperand(2).getGlobal();
1388  MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1389  const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1390 
1391  MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
1393  MI->getOperand(3).getImm(), OutContext);
1394  const MCExpr *LabelSymExpr= MCSymbolRefExpr::create(LabelSym, OutContext);
1395  unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1396  const MCExpr *PCRelExpr =
1398  MCBinaryExpr::createAdd(LabelSymExpr,
1401  TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
1402  // Add predicate operands.
1404  TmpInst.addOperand(MCOperand::createReg(0));
1405  // Add 's' bit operand (always reg0 for this)
1406  TmpInst.addOperand(MCOperand::createReg(0));
1407  EmitToStreamer(*OutStreamer, TmpInst);
1408  return;
1409  }
1410  case ARM::tPICADD: {
1411  // This is a pseudo op for a label + instruction sequence, which looks like:
1412  // LPC0:
1413  // add r0, pc
1414  // This adds the address of LPC0 to r0.
1415 
1416  // Emit the label.
1419  MI->getOperand(2).getImm(),
1420  OutContext));
1421 
1422  // Form and emit the add.
1423  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
1424  .addReg(MI->getOperand(0).getReg())
1425  .addReg(MI->getOperand(0).getReg())
1426  .addReg(ARM::PC)
1427  // Add predicate operands.
1428  .addImm(ARMCC::AL)
1429  .addReg(0));
1430  return;
1431  }
1432  case ARM::PICADD: {
1433  // This is a pseudo op for a label + instruction sequence, which looks like:
1434  // LPC0:
1435  // add r0, pc, r0
1436  // This adds the address of LPC0 to r0.
1437 
1438  // Emit the label.
1441  MI->getOperand(2).getImm(),
1442  OutContext));
1443 
1444  // Form and emit the add.
1446  .addReg(MI->getOperand(0).getReg())
1447  .addReg(ARM::PC)
1448  .addReg(MI->getOperand(1).getReg())
1449  // Add predicate operands.
1450  .addImm(MI->getOperand(3).getImm())
1451  .addReg(MI->getOperand(4).getReg())
1452  // Add 's' bit operand (always reg0 for this)
1453  .addReg(0));
1454  return;
1455  }
1456  case ARM::PICSTR:
1457  case ARM::PICSTRB:
1458  case ARM::PICSTRH:
1459  case ARM::PICLDR:
1460  case ARM::PICLDRB:
1461  case ARM::PICLDRH:
1462  case ARM::PICLDRSB:
1463  case ARM::PICLDRSH: {
1464  // This is a pseudo op for a label + instruction sequence, which looks like:
1465  // LPC0:
1466  // OP r0, [pc, r0]
1467  // The LCP0 label is referenced by a constant pool entry in order to get
1468  // a PC-relative address at the ldr instruction.
1469 
1470  // Emit the label.
1473  MI->getOperand(2).getImm(),
1474  OutContext));
1475 
1476  // Form and emit the load
1477  unsigned Opcode;
1478  switch (MI->getOpcode()) {
1479  default:
1480  llvm_unreachable("Unexpected opcode!");
1481  case ARM::PICSTR: Opcode = ARM::STRrs; break;
1482  case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1483  case ARM::PICSTRH: Opcode = ARM::STRH; break;
1484  case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1485  case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1486  case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1487  case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1488  case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1489  }
1491  .addReg(MI->getOperand(0).getReg())
1492  .addReg(ARM::PC)
1493  .addReg(MI->getOperand(1).getReg())
1494  .addImm(0)
1495  // Add predicate operands.
1496  .addImm(MI->getOperand(3).getImm())
1497  .addReg(MI->getOperand(4).getReg()));
1498 
1499  return;
1500  }
1501  case ARM::CONSTPOOL_ENTRY: {
1502  /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1503  /// in the function. The first operand is the ID# for this instruction, the
1504  /// second is the index into the MachineConstantPool that this is, the third
1505  /// is the size in bytes of this constant pool entry.
1506  /// The required alignment is specified on the basic block holding this MI.
1507  unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1508  unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1509 
1510  // If this is the first entry of the pool, mark it.
1511  if (!InConstantPool) {
1512  OutStreamer->EmitDataRegion(MCDR_DataRegion);
1513  InConstantPool = true;
1514  }
1515 
1516  OutStreamer->EmitLabel(GetCPISymbol(LabelId));
1517 
1518  const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1519  if (MCPE.isMachineConstantPoolEntry())
1521  else
1523  return;
1524  }
1525  case ARM::JUMPTABLE_ADDRS:
1526  EmitJumpTableAddrs(MI);
1527  return;
1528  case ARM::JUMPTABLE_INSTS:
1529  EmitJumpTableInsts(MI);
1530  return;
1531  case ARM::JUMPTABLE_TBB:
1532  case ARM::JUMPTABLE_TBH:
1533  EmitJumpTableTBInst(MI, MI->getOpcode() == ARM::JUMPTABLE_TBB ? 1 : 2);
1534  return;
1535  case ARM::t2BR_JT: {
1536  // Lower and emit the instruction itself, then the jump table following it.
1538  .addReg(ARM::PC)
1539  .addReg(MI->getOperand(0).getReg())
1540  // Add predicate operands.
1541  .addImm(ARMCC::AL)
1542  .addReg(0));
1543  return;
1544  }
1545  case ARM::t2TBB_JT:
1546  case ARM::t2TBH_JT: {
1547  unsigned Opc = MI->getOpcode() == ARM::t2TBB_JT ? ARM::t2TBB : ARM::t2TBH;
1548  // Lower and emit the PC label, then the instruction itself.
1549  OutStreamer->EmitLabel(GetCPISymbol(MI->getOperand(3).getImm()));
1551  .addReg(MI->getOperand(0).getReg())
1552  .addReg(MI->getOperand(1).getReg())
1553  // Add predicate operands.
1554  .addImm(ARMCC::AL)
1555  .addReg(0));
1556  return;
1557  }
1558  case ARM::tBR_JTr:
1559  case ARM::BR_JTr: {
1560  // Lower and emit the instruction itself, then the jump table following it.
1561  // mov pc, target
1562  MCInst TmpInst;
1563  unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1564  ARM::MOVr : ARM::tMOVr;
1565  TmpInst.setOpcode(Opc);
1566  TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1567  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1568  // Add predicate operands.
1570  TmpInst.addOperand(MCOperand::createReg(0));
1571  // Add 's' bit operand (always reg0 for this)
1572  if (Opc == ARM::MOVr)
1573  TmpInst.addOperand(MCOperand::createReg(0));
1574  EmitToStreamer(*OutStreamer, TmpInst);
1575  return;
1576  }
1577  case ARM::BR_JTm: {
1578  // Lower and emit the instruction itself, then the jump table following it.
1579  // ldr pc, target
1580  MCInst TmpInst;
1581  if (MI->getOperand(1).getReg() == 0) {
1582  // literal offset
1583  TmpInst.setOpcode(ARM::LDRi12);
1584  TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1585  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1586  TmpInst.addOperand(MCOperand::createImm(MI->getOperand(2).getImm()));
1587  } else {
1588  TmpInst.setOpcode(ARM::LDRrs);
1589  TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1590  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1591  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
1592  TmpInst.addOperand(MCOperand::createImm(0));
1593  }
1594  // Add predicate operands.
1596  TmpInst.addOperand(MCOperand::createReg(0));
1597  EmitToStreamer(*OutStreamer, TmpInst);
1598  return;
1599  }
1600  case ARM::BR_JTadd: {
1601  // Lower and emit the instruction itself, then the jump table following it.
1602  // add pc, target, idx
1604  .addReg(ARM::PC)
1605  .addReg(MI->getOperand(0).getReg())
1606  .addReg(MI->getOperand(1).getReg())
1607  // Add predicate operands.
1608  .addImm(ARMCC::AL)
1609  .addReg(0)
1610  // Add 's' bit operand (always reg0 for this)
1611  .addReg(0));
1612  return;
1613  }
1614  case ARM::SPACE:
1615  OutStreamer->EmitZeros(MI->getOperand(1).getImm());
1616  return;
1617  case ARM::TRAP: {
1618  // Non-Darwin binutils don't yet support the "trap" mnemonic.
1619  // FIXME: Remove this special case when they do.
1620  if (!Subtarget->isTargetMachO()) {
1621  //.long 0xe7ffdefe @ trap
1622  uint32_t Val = 0xe7ffdefeUL;
1623  OutStreamer->AddComment("trap");
1624  OutStreamer->EmitIntValue(Val, 4);
1625  return;
1626  }
1627  break;
1628  }
1629  case ARM::TRAPNaCl: {
1630  //.long 0xe7fedef0 @ trap
1631  uint32_t Val = 0xe7fedef0UL;
1632  OutStreamer->AddComment("trap");
1633  OutStreamer->EmitIntValue(Val, 4);
1634  return;
1635  }
1636  case ARM::tTRAP: {
1637  // Non-Darwin binutils don't yet support the "trap" mnemonic.
1638  // FIXME: Remove this special case when they do.
1639  if (!Subtarget->isTargetMachO()) {
1640  //.short 57086 @ trap
1641  uint16_t Val = 0xdefe;
1642  OutStreamer->AddComment("trap");
1643  OutStreamer->EmitIntValue(Val, 2);
1644  return;
1645  }
1646  break;
1647  }
1648  case ARM::t2Int_eh_sjlj_setjmp:
1649  case ARM::t2Int_eh_sjlj_setjmp_nofp:
1650  case ARM::tInt_eh_sjlj_setjmp: {
1651  // Two incoming args: GPR:$src, GPR:$val
1652  // mov $val, pc
1653  // adds $val, #7
1654  // str $val, [$src, #4]
1655  // movs r0, #0
1656  // b 1f
1657  // movs r0, #1
1658  // 1:
1659  unsigned SrcReg = MI->getOperand(0).getReg();
1660  unsigned ValReg = MI->getOperand(1).getReg();
1661  MCSymbol *Label = GetARMSJLJEHLabel();
1662  OutStreamer->AddComment("eh_setjmp begin");
1664  .addReg(ValReg)
1665  .addReg(ARM::PC)
1666  // Predicate.
1667  .addImm(ARMCC::AL)
1668  .addReg(0));
1669 
1671  .addReg(ValReg)
1672  // 's' bit operand
1673  .addReg(ARM::CPSR)
1674  .addReg(ValReg)
1675  .addImm(7)
1676  // Predicate.
1677  .addImm(ARMCC::AL)
1678  .addReg(0));
1679 
1681  .addReg(ValReg)
1682  .addReg(SrcReg)
1683  // The offset immediate is #4. The operand value is scaled by 4 for the
1684  // tSTR instruction.
1685  .addImm(1)
1686  // Predicate.
1687  .addImm(ARMCC::AL)
1688  .addReg(0));
1689 
1691  .addReg(ARM::R0)
1692  .addReg(ARM::CPSR)
1693  .addImm(0)
1694  // Predicate.
1695  .addImm(ARMCC::AL)
1696  .addReg(0));
1697 
1698  const MCExpr *SymbolExpr = MCSymbolRefExpr::create(Label, OutContext);
1700  .addExpr(SymbolExpr)
1701  .addImm(ARMCC::AL)
1702  .addReg(0));
1703 
1704  OutStreamer->AddComment("eh_setjmp end");
1706  .addReg(ARM::R0)
1707  .addReg(ARM::CPSR)
1708  .addImm(1)
1709  // Predicate.
1710  .addImm(ARMCC::AL)
1711  .addReg(0));
1712 
1713  OutStreamer->EmitLabel(Label);
1714  return;
1715  }
1716 
1717  case ARM::Int_eh_sjlj_setjmp_nofp:
1718  case ARM::Int_eh_sjlj_setjmp: {
1719  // Two incoming args: GPR:$src, GPR:$val
1720  // add $val, pc, #8
1721  // str $val, [$src, #+4]
1722  // mov r0, #0
1723  // add pc, pc, #0
1724  // mov r0, #1
1725  unsigned SrcReg = MI->getOperand(0).getReg();
1726  unsigned ValReg = MI->getOperand(1).getReg();
1727 
1728  OutStreamer->AddComment("eh_setjmp begin");
1730  .addReg(ValReg)
1731  .addReg(ARM::PC)
1732  .addImm(8)
1733  // Predicate.
1734  .addImm(ARMCC::AL)
1735  .addReg(0)
1736  // 's' bit operand (always reg0 for this).
1737  .addReg(0));
1738 
1740  .addReg(ValReg)
1741  .addReg(SrcReg)
1742  .addImm(4)
1743  // Predicate.
1744  .addImm(ARMCC::AL)
1745  .addReg(0));
1746 
1748  .addReg(ARM::R0)
1749  .addImm(0)
1750  // Predicate.
1751  .addImm(ARMCC::AL)
1752  .addReg(0)
1753  // 's' bit operand (always reg0 for this).
1754  .addReg(0));
1755 
1757  .addReg(ARM::PC)
1758  .addReg(ARM::PC)
1759  .addImm(0)
1760  // Predicate.
1761  .addImm(ARMCC::AL)
1762  .addReg(0)
1763  // 's' bit operand (always reg0 for this).
1764  .addReg(0));
1765 
1766  OutStreamer->AddComment("eh_setjmp end");
1768  .addReg(ARM::R0)
1769  .addImm(1)
1770  // Predicate.
1771  .addImm(ARMCC::AL)
1772  .addReg(0)
1773  // 's' bit operand (always reg0 for this).
1774  .addReg(0));
1775  return;
1776  }
1777  case ARM::Int_eh_sjlj_longjmp: {
1778  // ldr sp, [$src, #8]
1779  // ldr $scratch, [$src, #4]
1780  // ldr r7, [$src]
1781  // bx $scratch
1782  unsigned SrcReg = MI->getOperand(0).getReg();
1783  unsigned ScratchReg = MI->getOperand(1).getReg();
1785  .addReg(ARM::SP)
1786  .addReg(SrcReg)
1787  .addImm(8)
1788  // Predicate.
1789  .addImm(ARMCC::AL)
1790  .addReg(0));
1791 
1793  .addReg(ScratchReg)
1794  .addReg(SrcReg)
1795  .addImm(4)
1796  // Predicate.
1797  .addImm(ARMCC::AL)
1798  .addReg(0));
1799 
1801  .addReg(ARM::R7)
1802  .addReg(SrcReg)
1803  .addImm(0)
1804  // Predicate.
1805  .addImm(ARMCC::AL)
1806  .addReg(0));
1807 
1809  .addReg(ScratchReg)
1810  // Predicate.
1811  .addImm(ARMCC::AL)
1812  .addReg(0));
1813  return;
1814  }
1815  case ARM::tInt_eh_sjlj_longjmp: {
1816  // ldr $scratch, [$src, #8]
1817  // mov sp, $scratch
1818  // ldr $scratch, [$src, #4]
1819  // ldr r7, [$src]
1820  // bx $scratch
1821  unsigned SrcReg = MI->getOperand(0).getReg();
1822  unsigned ScratchReg = MI->getOperand(1).getReg();
1824  .addReg(ScratchReg)
1825  .addReg(SrcReg)
1826  // The offset immediate is #8. The operand value is scaled by 4 for the
1827  // tLDR instruction.
1828  .addImm(2)
1829  // Predicate.
1830  .addImm(ARMCC::AL)
1831  .addReg(0));
1832 
1834  .addReg(ARM::SP)
1835  .addReg(ScratchReg)
1836  // Predicate.
1837  .addImm(ARMCC::AL)
1838  .addReg(0));
1839 
1841  .addReg(ScratchReg)
1842  .addReg(SrcReg)
1843  .addImm(1)
1844  // Predicate.
1845  .addImm(ARMCC::AL)
1846  .addReg(0));
1847 
1849  .addReg(ARM::R7)
1850  .addReg(SrcReg)
1851  .addImm(0)
1852  // Predicate.
1853  .addImm(ARMCC::AL)
1854  .addReg(0));
1855 
1857  .addReg(ScratchReg)
1858  // Predicate.
1859  .addImm(ARMCC::AL)
1860  .addReg(0));
1861  return;
1862  }
1863  }
1864 
1865  MCInst TmpInst;
1866  LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1867 
1868  EmitToStreamer(*OutStreamer, TmpInst);
1869 }
1870 
1871 //===----------------------------------------------------------------------===//
1872 // Target Registry Stuff
1873 //===----------------------------------------------------------------------===//
1874 
1875 // Force static initialization.
1876 extern "C" void LLVMInitializeARMAsmPrinter() {
1881 }
bool hasV4TOps() const
Definition: ARMSubtarget.h:290
MCSection * getNonLazySymbolPointerSection() const
MachineConstantPoolValue * MachineCPVal
bool isImplicit() const
MO_DLLIMPORT - On a symbol operand, this represents that the reference to the symbol is for an import...
Definition: ARMBaseInfo.h:303
StubValueTy & getHiddenGVStubEntry(MCSymbol *Sym)
void push_back(const T &Elt)
Definition: SmallVector.h:222
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:104
Target TheThumbLETarget
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
virtual void emitFPU(unsigned FPU)
StringRef getTargetCPU() const
void EmitStartOfAsmFile(Module &M) override
This virtual method can be overridden by targets that want to emit something at the start of their fi...
const GlobalValue * getGlobal() const
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:489
static ARMBuildAttrs::CPUArch getArchForCPU(StringRef CPU, const ARMSubtarget *Subtarget)
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
Definition: AsmPrinter.h:83
MCSymbol * getSymbol(const GlobalValue *GV) const
Definition: AsmPrinter.cpp:339
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:315
void print(raw_ostream &OS, const MCAsmInfo *MAI) const
print - Print the value to the stream OS.
Definition: MCSymbol.cpp:51
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
const std::string & getCPUString() const
Definition: ARMSubtarget.h:426
MachineBasicBlock * getMBB() const
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:39
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:114
void EmitJumpTableTBInst(const MachineInstr *MI, unsigned OffsetWidth)
MCContext & OutContext
This is the context for the output file that we are streaming.
Definition: AsmPrinter.h:78
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:129
virtual void emitArchExtension(unsigned ArchExt)
bool isTargetEHABICompatible() const
Definition: ARMSubtarget.h:381
ARMConstantPoolValue - ARM specific constantpool value.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:579
Target specific streamer interface.
Definition: MCStreamer.h:73
virtual void emitPad(int64_t Offset)
const MachineFunction * MF
The current machine function.
Definition: AsmPrinter.h:86
static GlobalValue * getGV(DataRefImpl &Symb)
const char * getPrivateGlobalPrefix() const
Definition: DataLayout.h:281
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:488
MCSymbol * getSymbolWithGlobalValueBase(const GlobalValue *GV, StringRef Suffix) const
Return the MCSymbol for a private symbol with global value name as its base, with the specified suffi...
bool hasV5TEOps() const
Definition: ARMSubtarget.h:292
MachineBasicBlock reference.
unsigned getFunctionNumber() const
Return a unique ID for the current function.
Definition: AsmPrinter.cpp:130
bool hasV6Ops() const
Definition: ARMSubtarget.h:293
bool runOnMachineFunction(MachineFunction &F) override
runOnMachineFunction - This uses the EmitInstruction() method to print assembly for each instruction...
virtual void finishAttributeSection()
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
setjmp/longjmp based exceptions
bool hasV6T2Ops() const
Definition: ARMSubtarget.h:296
MO_PLT - On a symbol operand, this represents an ELF PLT reference on a call operand.
Definition: ARMBaseInfo.h:294
std::vector< std::pair< MCSymbol *, StubValueTy > > SymbolListTy
static bool isThumb(const MCSubtargetInfo &STI)
static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx)
isUseOperandTiedToDef - Return true if the flag of the inline asm operand indicates it is an use oper...
Definition: InlineAsm.h:338
void LLVMInitializeARMAsmPrinter()
void emitInlineAsmEnd(const MCSubtargetInfo &StartInfo, const MCSubtargetInfo *EndInfo) const override
Let the target do anything it needs to do after emitting inlineasm.
void getNameWithPrefix(SmallVectorImpl< char > &Name, const GlobalValue *GV) const
Definition: AsmPrinter.cpp:334
bool hasV6MOps() const
Definition: ARMSubtarget.h:294
void EmitFunctionBodyEnd() override
Targets can override this to emit stuff after the last basic block in the function.
const Triple & getTargetTriple() const
const std::vector< MachineJumpTableEntry > & getJumpTables() const
BlockAddress - The address of a basic block.
Definition: Constants.h:802
bool hasV8Ops() const
Definition: ARMSubtarget.h:298
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:111
MCSuperRegIterator enumerates all super-registers of Reg.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:79
bool isTargetELF() const
Definition: ARMSubtarget.h:363
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
bool hasInternalLinkage() const
Definition: GlobalValue.h:278
void EmitInstruction(const MachineInstr *MI) override
Targets should implement this to emit instructions.
static const MCBinaryExpr * createDiv(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:454
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:33
const Module * getModule() const
Reg
All possible values of the reg field in the ModR/M byte.
.data_region jt16
Definition: MCDirectives.h:58
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Definition: Value.cpp:317
virtual unsigned getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
#define false
Definition: ConvertUTF.c:65
MCContext & getContext() const
Definition: MCStreamer.h:210
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:271
Context object for machine code objects.
Definition: MCContext.h:48
bool hasV7Ops() const
Definition: ARMSubtarget.h:297
static const ARMMCExpr * createLower16(const MCExpr *Expr, MCContext &Ctx)
Definition: ARMMCExpr.h:43
void EmitFunctionBody()
This method emits the body and trailer for a function.
Definition: AsmPrinter.cpp:784
unsigned NoNaNsFPMath
NoNaNsFPMath - This flag is enabled when the -enable-no-nans-fp-math flag is specified on the command...
void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) override
EmitMachineConstantPoolValue - Print a machine constantpool value to the .s file. ...
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:514
.code16 (X86) / .code 16 (ARM)
Definition: MCDirectives.h:50
static MCSymbol * getPICLabel(const char *Prefix, unsigned FunctionNumber, unsigned LabelId, MCContext &Ctx)
bool isTargetCOFF() const
Definition: ARMSubtarget.h:362
bool isTargetMachO() const
Definition: ARMSubtarget.h:364
const MachineJumpTableInfo * getJumpTableInfo() const
getJumpTableInfo - Return the jump table info object for the current function.
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:25
virtual void emitMovSP(unsigned Reg, int64_t Offset=0)
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Definition: Triple.h:242
This class is a data container for one entry in a MachineConstantPool.
static MCSymbolRefExpr::VariantKind getModifierVariantKind(ARMCP::ARMCPModifier Modifier)
int64_t getImm() const
static const char * getRegisterName(unsigned RegNo)
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:446
virtual void EmitIntValue(uint64_t Value, unsigned Size)
Special case of EmitValue that avoids the client having to pass in a MCExpr for constant integers...
Definition: MCStreamer.cpp:79
MachineModuleInfo * MMI
This is a pointer to the current MachineModuleInfo.
Definition: AsmPrinter.h:89
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:150
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:267
bool isMachineConstantPoolEntry() const
isMachineConstantPoolEntry - Return true if the MachineConstantPoolEntry is indeed a target specific ...
SubArchType getSubArch() const
getSubArch - get the parsed subarchitecture type for this triple.
Definition: Triple.h:245
virtual void emitAttribute(unsigned Attribute, unsigned Value)
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:120
DBG_VALUE - a mapping of the llvm.dbg.value intrinsic.
Definition: TargetOpcodes.h:69
.data_region jt32
Definition: MCDirectives.h:59
Address of a global value.
void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O)
unsigned getTargetFlags() const
Streaming machine code generation interface.
Definition: MCStreamer.h:157
MCInstBuilder & addReg(unsigned Reg)
Add a new register operand.
Definition: MCInstBuilder.h:32
unsigned UnsafeFPMath
UnsafeFPMath - This flag is enabled when the -enable-unsafe-fp-math flag is specified on the command ...
virtual void emitRegSave(const SmallVectorImpl< unsigned > &RegList, bool isVector)
MCSymbol * createTempSymbol(bool CanBeUnnamed=true)
Create and return a new assembler temporary symbol with a unique but unspecified name.
Definition: MCContext.cpp:222
Constant * stripPointerCasts()
Definition: Constant.h:170
MCSymbol * CurrentFnSym
The symbol for the current function.
Definition: AsmPrinter.h:98
const MCAsmInfo * MAI
Target Asm Printer information.
Definition: AsmPrinter.h:74
PointerIntPair - This class implements a pair of a pointer and small integer.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important base class in LLVM.
Definition: Constant.h:41
bool isMClass() const
Definition: ARMSubtarget.h:408
bool hasHiddenVisibility() const
Definition: GlobalValue.h:141
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &OS)
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant...
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
Type is formed as (base + (derived << SCT_COMPLEX_TYPE_SHIFT))
Definition: Support/COFF.h:227
virtual void emitSetFP(unsigned FpReg, unsigned SpReg, int64_t Offset=0)
TargetMachine & TM
Target machine description.
Definition: AsmPrinter.h:70
This class is intended to be used as a driving class for all asm writers.
Definition: AsmPrinter.h:66
bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant as...
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag...
Definition: InlineAsm.h:332
virtual bool EmitSymbolAttribute(MCSymbol *Symbol, MCSymbolAttr Attribute)=0
Add the given Attribute to Symbol.
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang","erlang-compatible garbage collector")
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:150
void printOffset(int64_t Offset, raw_ostream &OS) const
This is just convenient handler for printing offsets.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
.subsections_via_symbols (MachO)
Definition: MCDirectives.h:49
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:644
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:511
A function that returns a base type.
Definition: Support/COFF.h:223
unsigned convertAddSubFlagsOpcode(unsigned OldOpc)
Map pseudo instructions that imply an 'S' bit onto real opcodes.
int64_t getOffset() const
Return the offset from the symbol in this operand.
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
Definition: MCInstBuilder.h:38
Ty & getObjFileInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
ARMAsmPrinter(TargetMachine &TM, std::unique_ptr< MCStreamer > Streamer)
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
unsigned NoInfsFPMath
NoInfsFPMath - This flag is enabled when the -enable-no-infs-fp-math flag is specified on the command...
void EmitXXStructor(const Constant *CV) override
Targets can override this to change how global constants that are part of a C++ static/global constru...
unsigned getSubReg() const
IntType getInt() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void EmitFunctionEntryLabel() override
EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function.
Abstract base class for all machine specific constantpool value subclasses.
MCSymbol * getSymbol() const
getSymbol - Return the MCSymbol for this basic block.
StubValueTy & getGVStubEntry(MCSymbol *Sym)
MO_LO16 - On a symbol operand, this represents a relocation containing lower 16 bit of the address...
Definition: ARMBaseInfo.h:286
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
void EmitAlignment(unsigned NumBits, const GlobalObject *GO=nullptr) const
Emit an alignment directive to the specified power of two boundary.
const std::string & getModuleInlineAsm() const
Get any module-scope inline assembly blocks.
Definition: Module.h:269
void EmitJumpTableInsts(const MachineInstr *MI)
PointerTy getPointer() const
void setOpcode(unsigned Op)
Definition: MCInst.h:158
StringRef getTargetFeatureString() const
virtual void EmitLabel(MCSymbol *Symbol)
Emit a label for Symbol into the current section.
Definition: MCStreamer.cpp:203
bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const
GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
uint64_t getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:388
static void emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel, MachineModuleInfoImpl::StubValueTy &MCSym)
void EmitGlobalConstant(const Constant *CV)
Print a general LLVM constant to the .s file.
const DataLayout * getDataLayout() const
Deprecated in 3.7, will be removed in 3.8.
MachineOperand class - Representation of each machine instruction operand.
Module.h This file contains the declarations for the Module class.
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:222
.indirect_symbol (MachO)
Definition: MCDirectives.h:32
void EmitToStreamer(MCStreamer &S, const MCInst &Inst)
Definition: AsmPrinter.cpp:148
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
Type * getType() const
getType - get type of this MachineConstantPoolValue.
void dump() const
SymbolStorageClass
Storage class tells where and what the symbol represents.
Definition: Support/COFF.h:165
.syntax (ARM/ELF)
Definition: MCDirectives.h:48
MCSymbol * getCurExceptionSym()
void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, ARMAsmPrinter &AP)
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:285
.code32 (X86) / .code 32 (ARM)
Definition: MCDirectives.h:51
FunctionNumber(functionNumber)
Definition: LLParser.cpp:2146
static bool hasRegClassConstraint(unsigned Flag, unsigned &RC)
hasRegClassConstraint - Returns true if the flag contains a register class constraint.
Definition: InlineAsm.h:347
Representation of each machine instruction.
Definition: MachineInstr.h:51
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
static bool isPhysicalRegister(unsigned Reg)
isPhysicalRegister - Return true if the specified register number is in the physical register namespa...
void SetupMachineFunction(MachineFunction &MF)
This should be called when a new MachineFunction is being processed from runOnMachineFunction.
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:479
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:111
bool hasV5TOps() const
Definition: ARMSubtarget.h:291
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
MCSymbol * GetBlockAddressSymbol(const BlockAddress *BA) const
Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block.
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant...
Target TheThumbBETarget
void EmitJumpTableAddrs(const MachineInstr *MI)
static const ARMMCExpr * createUpper16(const MCExpr *Expr, MCContext &Ctx)
Definition: ARMMCExpr.h:39
Target TheARMLETarget
MCSubtargetInfo - Generic base class for all target subtargets.
union llvm::MachineConstantPoolEntry::@30 Val
The constant itself.
Target TheARMBETarget
MachineModuleInfoMachO - This is a MachineModuleInfoImpl implementation for MachO targets...
void EmitValue(const MCExpr *Value, unsigned Size, const SMLoc &Loc=SMLoc())
Definition: MCStreamer.cpp:110
virtual MCSymbol * GetCPISymbol(unsigned CPID) const
Return the symbol for the specified constant pool entry.
unsigned getReg() const
getReg - Returns the register number.
const TargetLoweringObjectFile & getObjFileLowering() const
Return information about object file lowering.
Definition: AsmPrinter.cpp:134
unsigned char getPCAdjustment() const
.data_region jt8
Definition: MCDirectives.h:57
unsigned HonorSignDependentRoundingFPMathOption
HonorSignDependentRoundingFPMath - This returns true when the -enable-sign-dependent-rounding-fp-math...
RegisterAsmPrinter - Helper template for registering a target specific assembly printer, for use in the target machine initialization function.
MO_NONLAZY - This is an independent flag, on a symbol operand "FOO" it represents a symbol which...
Definition: ARMBaseInfo.h:310
std::string ParseARMTriple(const Triple &TT, StringRef CPU)
static const unsigned FramePtr
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:38
static TraceState * TS
Primary interface to the complete machine description for the target machine.
const std::vector< MachineConstantPoolEntry > & getConstants() const
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
void addOperand(const MCOperand &Op)
Definition: MCInst.h:168
virtual void print(raw_ostream &O, const Module *M) const
print - Print out the internal state of the pass.
Definition: Pass.cpp:111
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:40
Address of indexed Constant in Constant Pool.
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml","ocaml 3.10-compatible collector")
unsigned getOriginalCPIdx(unsigned CloneIdx) const
ARMCP::ARMCPModifier getModifier() const
MCSymbol * GetExternalSymbolSymbol(StringRef Sym) const
Return the MCSymbol for the specified ExternalSymbol.
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:117
bool hasThumb2DSP() const
Definition: ARMSubtarget.h:346
bool isTargetWindows() const
Definition: ARMSubtarget.h:360
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx)
Definition: MCExpr.cpp:150
.end_data_region
Definition: MCDirectives.h:60
MO_HI16 - On a symbol operand, this represents a relocation containing higher 16 bit of the address...
Definition: ARMBaseInfo.h:290
virtual void switchVendor(StringRef Vendor)
bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:110
FloatABI::ABIType FloatABIType
FloatABIType - This setting is set by -float-abi=xxx option is specfied on the command line...
virtual void emitTextAttribute(unsigned Attribute, StringRef String)
void EmitEndOfAsmFile(Module &M) override
This virtual method can be overridden by targets that want to emit something at the end of their file...