42 #define DEBUG_TYPE "hexagon-lowering"
46 cl::desc(
"Control jump table emission on Hexagon target"));
50 cl::desc(
"Enable Hexagon SDNode scheduling"));
54 cl::desc(
"Enable Fast Math processing"));
58 cl::desc(
"Set minimum jump tables"));
62 cl::desc(
"Max #stores to inline memcpy"));
66 cl::desc(
"Max #stores to inline memcpy"));
70 cl::desc(
"Max #stores to inline memmove"));
74 cl::desc(
"Max #stores to inline memmove"));
78 cl::desc(
"Max #stores to inline memset"));
82 cl::desc(
"Max #stores to inline memset"));
86 class HexagonCCState :
public CCState {
87 unsigned NumNamedVarArgParams;
92 int NumNamedVarArgParams)
93 :
CCState(CC, isVarArg, MF, locs, C),
94 NumNamedVarArgParams(NumNamedVarArgParams) {}
96 unsigned getNumNamedVarArgParams()
const {
return NumNamedVarArgParams; }
135 HexagonCCState &HState =
static_cast<HexagonCCState &
>(State);
137 if (ValNo < HState.getNumNamedVarArgParams()) {
139 return CC_Hexagon(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State);
157 else if (ArgFlags.
isZExt())
194 else if (ArgFlags.
isZExt())
207 if (!
CC_Hexagon32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
212 if (!
CC_Hexagon64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
248 Hexagon::D1, Hexagon::D2
251 Hexagon::R1, Hexagon::R3
275 else if (ArgFlags.
isZExt())
379 for (
unsigned i = 0; i != RVLocs.
size(); ++i) {
402 if (!CI->
isTailCall() || Attr.getValueAsString() ==
"true")
432 for (
unsigned i = 0; i != RVLocs.
size(); ++i) {
434 RVLocs[i].getLocReg(),
435 RVLocs[i].getValVT(), InFlag).
getValue(1);
460 bool IsStructRet = (Outs.
empty()) ?
false : Outs[0].
Flags.isSRet();
465 int NumNamedVarArgParams = -1;
470 if ((CalleeFn = dyn_cast<Function>(GA->getGlobal())))
493 if (Attr.getValueAsString() ==
"true")
499 isVarArg, IsStructRet,
501 Outs, OutVals, Ins, DAG);
502 for (
unsigned i = 0, e = ArgLocs.
size(); i != e; ++i) {
509 DEBUG(
dbgs() << (isTailCall ?
"Eligible for Tail Call\n"
510 :
"Argument must be passed on stack. "
511 "Not eligible for Tail Call\n"));
514 unsigned NumBytes = CCInfo.getNextStackOffset();
523 for (
unsigned i = 0, e = ArgLocs.
size(); i != e; ++i) {
574 if (!MemOpChains.
empty())
588 for (
unsigned i = 0, e = RegsToPass.
size(); i != e; ++i) {
589 Chain = DAG.
getCopyToReg(Chain, dl, RegsToPass[i].first,
590 RegsToPass[i].second, InFlag);
605 for (
unsigned i = 0, e = RegsToPass.
size(); i != e; ++i) {
606 Chain = DAG.
getCopyToReg(Chain, dl, RegsToPass[i].first,
607 RegsToPass[i].second, InFlag);
617 const char *MemcpyName =
618 "__hexagon_memcpy_likely_aligned_min32bytes_mult8bytes";
624 dyn_cast<ExternalSymbolSDNode>(Callee)) {
636 for (
unsigned i = 0, e = RegsToPass.
size(); i != e; ++i) {
638 RegsToPass[i].second.getValueType()));
650 Chain = DAG.
getNode(OpCode, dl, NodeTys, Ops);
660 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
661 InVals, OutVals, Callee);
676 return (isa<ConstantSDNode>(Offset));
692 if (ShiftAmount > 0) {
694 v = v >> ShiftAmount;
696 return (v <= 7) && (v >= -8) && (m == 0);
713 VT =
LD->getMemoryVT();
716 VT =
ST->getMemoryVT();
717 if (
ST->getValue().getValueType() ==
MVT::i64 &&
ST->isTruncatingStore()) {
749 if (FuncInfo.hasClobberLR())
752 cast<ConstantSDNode>(Node->
getOperand(i))->getZExtValue();
763 for (; NumVals; --NumVals, ++i) {}
767 for (; NumVals; --NumVals, ++i) {
774 FuncInfo.setHasClobberLR(
true);
805 const std::vector<MachineJumpTableEntry> &JTE = MJTI->
getJumpTables();
806 const std::vector<MachineBasicBlock*> &JTBBs = JTE[JTI].MBBs;
807 for (
unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
837 assert(AlignConst &&
"Non-constant Align in LowerDYNAMIC_STACKALLOC");
843 A = HFI.getStackAlignment();
887 for (
unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
891 unsigned StackLocation;
915 assert (0 &&
"ByValSize must be bigger than 8 bytes");
956 CCInfo.getNextStackOffset(),
958 FuncInfo.setVarArgsFrameIndex(FrameIndex);
1002 if (isa<ConstantSDNode>(InpVal)) {
1003 uint64_t V = cast<ConstantSDNode>(InpVal)->getZExtValue();
1095 if (Alignment == 2) {
1142 Loads[0].getValue(1), Loads[1].getValue(1),
1143 Loads[2].getValue(1), Loads[3].getValue(1));
1157 SDValue Ops[] = { Result, LoadChain };
1190 unsigned Depth = cast<ConstantSDNode>(Op.
getOperand(0))->getZExtValue();
1212 unsigned Depth = cast<ConstantSDNode>(Op.
getOperand(0))->getZExtValue();
1218 false,
false,
false, 0);
1232 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1233 int64_t Offset = cast<GlobalAddressSDNode>(Op)->
getOffset();
1249 void HexagonTargetLowering::promoteLdStType(
EVT VT,
EVT PromotedLdStVT) {
1250 if (VT != PromotedLdStVT) {
1263 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1422 for (
unsigned IntExpOp :
1430 for (
unsigned FPExpOp :
1478 static unsigned VectExpOps[] = {
1505 for (
unsigned VectExpOp : VectExpOps)
1581 for (
unsigned FPExpOpV4 :
1790 unsigned DefinedValues)
const {
1795 if ((EltBits != 8) && (EltBits != 16))
1815 if (Lane == -1) Lane = 0;
1819 return createSplat(DAG, dl, VT, V1.getOperand(0));
1825 !isa<ConstantSDNode>(V1.getOperand(0))) {
1826 bool IsScalarToVector =
true;
1827 for (
unsigned i = 1, e = V1.getNumOperands(); i != e; ++i)
1828 if (V1.getOperand(i).getOpcode() !=
ISD::UNDEF) {
1829 IsScalarToVector =
false;
1832 if (IsScalarToVector)
1833 return createSplat(DAG, dl, VT, V1.getOperand(0));
1853 for (
unsigned i = 1, e = NElts; i != e; ++i) {
1871 if ((BVN = dyn_cast<BuildVectorSDNode>(V1.
getNode())) &&
1874 else if ((BVN = dyn_cast<BuildVectorSDNode>(V2.
getNode())) &&
1931 APInt APSplatBits, APSplatUndef;
1932 unsigned SplatBitSize;
1939 HasAnyUndefs, 0,
true) && SplatBitSize <= 16)) {
1941 int32_t SextVal = ((int32_t) (SplatBits << (32 - SplatBitSize)) >>
1942 (32 - SplatBitSize));
1972 for (
unsigned i = 0, e = NElts; i != e; ++i) {
1991 unsigned EltSize = Size / NElts;
1993 uint64_t Mask = ~uint64_t(0ULL) >> (64 - EltSize);
1994 bool HasNonConstantElements =
false;
1996 for (
unsigned i = 0, e = NElts; i != e; ++i) {
1999 unsigned OpIdx = NElts - i - 1;
2006 Val = Cst->getSExtValue();
2008 HasNonConstantElements =
true;
2011 Res = (Res << EltSize) | Val;
2021 if (HasNonConstantElements) {
2027 for (
unsigned i = 0, e = NElts; i != e; ++i) {
2030 unsigned OpIdx = NElts - i - 1;
2032 if (isa<ConstantSDNode>(Operand))
2045 const SDValue Ops[] = {ConstVal, Operand, Combined};
2074 if ((W->
getZExtValue() == 32) && ((S->getZExtValue() >> 32) == 32)) {
2083 if ((W->
getZExtValue() == 32) && ((S->getZExtValue() >> 32) == 32)) {
2091 for (
unsigned i = 0, e = NElts; i != e; ++i) {
2092 unsigned OpIdx = NElts - i - 1;
2104 const SDValue Ops[] = {ConstVal, Operand, Combined};
2127 EltSize : VTN * EltSize, dl,
MVT::i64);
2131 uint64_t
X = CI->getZExtValue();
2133 const SDValue Ops[] = {Vec, Width, Offset};
2136 assert(CW &&
"Non constant width in LowerEXTRACT_VECTOR");
2144 unsigned Subreg = (X == 0) ? Hexagon::subreg_loreg : 0;
2147 Subreg = Hexagon::subreg_loreg;
2149 Subreg = Hexagon::subreg_hireg;
2151 Subreg = Hexagon::subreg_hireg;
2153 Subreg = Hexagon::subreg_hireg;
2176 const SDValue Ops[] = {Vec, Combined};
2202 EltSize : VTN * EltSize, dl,
MVT::i64);
2206 const SDValue Ops[] = {Vec, Val, Width, Offset};
2230 const SDValue Ops[] = {Vec, Val, Combined};
2267 unsigned OffsetReg = Hexagon::R28;
2274 Chain = DAG.
getCopyToReg(Chain, dl, OffsetReg, Offset);
2290 errs() <<
"Check for a non-legal type in this operation\n";
2343 std::pair<unsigned, const TargetRegisterClass *>
2346 if (Constraint.
size() == 1) {
2347 switch (Constraint[0]) {
2356 return std::make_pair(0U, &Hexagon::IntRegsRegClass);
2359 return std::make_pair(0U, &Hexagon::DoubleRegsRegClass);
2380 unsigned AS)
const {
2389 int Scale = AM.
Scale;
2390 if (Scale < 0) Scale = -Scale;
2405 return Imm >= -512 && Imm <= 511;
2415 bool isCalleeStructRet,
2416 bool isCallerStructRet,
2423 bool CCMatch = CallerCC == CalleeCC;
2431 if (!(dyn_cast<GlobalAddressSDNode>(Callee))
2432 && !(dyn_cast<ExternalSymbolSDNode>(Callee))) {
2446 if (isCalleeStructRet || isCallerStructRet)
2474 Type *Ty = cast<PointerType>(Addr->
getType())->getElementType();
2476 assert((SZ == 32 || SZ == 64) &&
"Only 32/64-bit atomic loads supported");
2477 Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_L2_loadw_locked
2478 : Intrinsic::hexagon_L4_loadd_locked;
2491 assert((SZ == 32 || SZ == 64) &&
"Only 32/64-bit atomic stores supported");
2492 Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_S2_storew_locked
2493 : Intrinsic::hexagon_S4_stored_locked;
static bool Is_PostInc_S4_Offset(SDNode *S, int ShiftAmount)
void setFrameAddressIsTaken(bool T)
bool IsGlobalInSmallSection(const GlobalValue *GV, const TargetMachine &TM, SectionKind Kind) const
IsGlobalInSmallSection - Return true if this global address should be placed into small data/bss sect...
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
bool isFPImmLegal(const APFloat &Imm, EVT VT) const override
isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively...
Value * getValueOperand()
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...
void push_back(const T &Elt)
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
A parsed version of the target data layout string in and methods for querying it. ...
SDValue getValue(unsigned R) const
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
bool shouldExpandAtomicLoadInIR(LoadInst *LI) const override
Returns true if the given (atomic) load should be expanded by the IR-level AtomicExpand pass into a l...
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
LLVMContext * getContext() const
SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N)
uint64_t getZExtValue() const
Get zero extended value.
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, SDLoc DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd)...
unsigned getFrameRegister(const MachineFunction &MF) const override
bool isLegalICmpImmediate(int64_t Imm) const override
isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register.
void dump() const
Dump this node, for debugging.
size_t size() const
size - Get the string size.
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an vector value) starting with the ...
BR_CC - Conditional branch.
LocInfo getLocInfo() const
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
void setHasEHReturn(bool H=true)
A Module instance is used to store all the information related to an LLVM module. ...
unsigned getNumParams() const
getNumParams - Return the number of fixed parameters this function type requires. ...
const TargetMachine & getTargetMachine() const
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
getPostIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mo...
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
SDValue getMergeValues(ArrayRef< SDValue > Ops, SDLoc dl)
Create a MERGE_VALUES node from the given operands.
SDValue LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals, const SmallVectorImpl< SDValue > &OutVals, SDValue Callee) const
LowerCallResult - Lower the result values of an ISD::CALL into the appropriate copies out of appropri...
int getSplatIndex() const
Carry-setting nodes for multiple precision addition and subtraction.
static cl::opt< bool > EmitJumpTables("hexagon-emit-jump-tables", cl::init(true), cl::Hidden, cl::desc("Control jump table emission on Hexagon target"))
unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain...
CallInst - This class represents a function call, abstracting a target machine's calling convention...
unsigned getRARegister() const
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
unsigned getByValSize() const
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array...
static bool RetCC_Hexagon64(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
Hexagon target-specific information for each MachineFunction.
unsigned getNumOperands() const
Return the number of values used by this operation.
bool isPositiveHalfWord(SDNode *N)
const Function * getParent() const
Return the enclosing method, or null if none.
unsigned getNumOperands() const
const SDValue & getOperand(unsigned Num) const
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
LoadInst - an instruction for reading from memory.
const HexagonFrameLowering * getFrameLowering() const override
virtual bool shouldExpandBuildVectorWithShuffles(EVT, unsigned DefinedValues) const
Value * CreateICmpEQ(Value *LHS, Value *RHS, const Twine &Name="")
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags=0)
SDValue LowerEXTRACT_VECTOR(SDValue Op, SelectionDAG &DAG) const
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
static std::error_code getOffset(const SymbolRef &Sym, SectionRef Sec, uint64_t &Result)
const SDValue & getBasePtr() const
INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector with VECTOR2 inserted into VECTOR1 at the ...
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
bool isUnsignedIntSetCC(CondCode Code)
isUnsignedIntSetCC - Return true if this is a setcc instruction that performs an unsigned comparison ...
This SDNode is used to implement the code generator support for the llvm IR shufflevector instruction...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
SDValue getMemcpy(SDValue Chain, SDLoc dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
void dumpr() const
Dump (recursively) this node and its use-def subgraph.
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
bool isNegative() const
Determine sign of this APInt.
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
bool isVector() const
isVector - Return true if this is a vector value type.
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...
const std::vector< MachineJumpTableEntry > & getJumpTables() const
BlockAddress - The address of a basic block.
SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
bool isSEXTLoad(const SDNode *N)
Returns true if the specified node is a SEXTLOAD.
Value * emitStoreConditional(IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const override
Perform a store-conditional operation to Addr.
Shift and rotation operations.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool shouldExpandBuildVectorWithShuffles(EVT VT, unsigned DefinedValues) const override
MachineFunction & getMachineFunction() const
const HexagonRegisterInfo * getRegisterInfo() const override
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
bool isInt< 8 >(int64_t x)
SDValue getTargetGlobalAddress(const GlobalValue *GV, SDLoc DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
virtual TargetLoweringObjectFile * getObjFileLowering() const
void addLoc(const CCValAssign &V)
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Reg
All possible values of the reg field in the ModR/M byte.
void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn't supported on the target and indicate what to d...
#define Hexagon_PointerSize
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
INLINEASM - Represents an inline asm block.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
SmallVector< ISD::InputArg, 32 > Ins
STACKSAVE - STACKSAVE has one operand, an input chain.
EVT getVectorElementType() const
getVectorElementType - Given a vector type, return the type of each element.
bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef, unsigned &SplatBitSize, bool &HasAnyUndefs, unsigned MinSplatBits=0, bool isBigEndian=false) const
Check if this is a constant splat, and if so, find the smallest element size that splats the vector...
load Combine Adjacent Loads
SDValue getCALLSEQ_START(SDValue Chain, SDValue Op, SDLoc DL)
Return a new CALLSEQ_START node, which always must have a glue result (to ensure it's not CSE'd)...
unsigned getLocReg() const
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
bool hasStructRetAttr() const
Determine if the function returns a structure through first pointer argument.
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
Simple integer binary arithmetic operators.
static bool CC_Hexagon32(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
SmallVector< ISD::OutputArg, 32 > Outs
const MachineJumpTableInfo * getJumpTableInfo() const
getJumpTableInfo - Return the jump table info object for the current function.
Function * getDeclaration(Module *M, ID id, ArrayRef< Type * > Tys=None)
Create or insert an LLVM Function declaration for an intrinsic, and return it.
MachineConstantPoolValue * getMachineCPVal() const
StoreInst - an instruction for storing to memory.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
const APInt & getAPIntValue() const
SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override
Return true if a truncation from Ty1 to Ty2 is permitted when deciding whether a call is in tail posi...
bool isSignedIntSetCC(CondCode Code)
isSignedIntSetCC - Return true if this is a setcc instruction that performs a signed comparison when ...
static cl::opt< int > MinimumJumpTables("minimum-jump-tables", cl::Hidden, cl::ZeroOrMore, cl::init(5), cl::desc("Set minimum jump tables"))
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
const DataLayout & getDataLayout() const
SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const
const BasicBlock * getBasicBlock() const
getBasicBlock - Return the LLVM basic block that this instance corresponded to originally.
UNDEF - An undefined node.
This class is used to represent ISD::STORE nodes.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
Flag
These should be considered private to the implementation of the MCInstrDesc class.
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable...
SDNode * getNode() const
get the SDNode which holds the desired result
A self-contained host- and target-independent arbitrary-precision floating-point software implementat...
initializer< Ty > init(const Ty &Val)
bool isMachineConstantPoolEntry() const
MVT - Machine Value Type.
LLVM Basic Block Representation.
const SDValue & getOperand(unsigned i) const
The instances of the Type class are immutable: once they are created, they are never changed...
This is an important class for using LLVM in a threaded context.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const
Simple binary floating point operators.
bool isNonTemporal() const
static BlockAddress * get(Function *F, BasicBlock *BB)
get - Return a BlockAddress for the specified function and basic block.
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE...
static bool getIndexedAddressParts(SDNode *Ptr, EVT VT, bool isSEXTLoad, SDValue &Base, SDValue &Offset, bool &isInc, SelectionDAG &DAG)
static bool CC_Hexagon(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
static cl::opt< int > MaxStoresPerMemmoveOptSizeCL("max-store-memmove-Os", cl::Hidden, cl::ZeroOrMore, cl::init(4), cl::desc("Max #stores to inline memmove"))
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL...
const Constant * getConstVal() const
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Carry-using nodes for multiple precision addition and subtraction.
bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override
Returns true if the given (atomic) store should be expanded by the IR-level AtomicExpand pass into an...
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
Return true if it's free to truncate a value of type Ty1 to type Ty2.
bool mayBeEmittedAsTailCall(CallInst *CI) const override
Return true if the target may be able emit the call instruction as a tail call.
SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const
static mvt_range fp_valuetypes()
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag...
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT)
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang","erlang-compatible garbage collector")
SDValue getTargetConstant(uint64_t Val, SDLoc DL, EVT VT, bool isOpaque=false)
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
unsigned getOpcode() const
static unsigned getKind(unsigned Flags)
void setPrefFunctionAlignment(unsigned Align)
Set the target's preferred function alignment.
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
static mvt_range vector_valuetypes()
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool Immutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
unsigned MaxStoresPerMemmove
Specify maximum bytes of store instructions per memmove call.
SDValue getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes())
Bit counting operators with an undefined result for zero inputs.
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const
EVT - Extended Value Type.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
CallInst * CreateCall(Value *Callee, ArrayRef< Value * > Args=None, const Twine &Name="")
This structure contains all information that is necessary for lowering calls.
static bool isSExtFree(SDValue N)
MachinePointerInfo - This class contains a discriminated union of information about pointers in memor...
const MachinePointerInfo & getPointerInfo() const
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
unsigned getByValAlign() const
SDValue getTargetConstantPool(const Constant *C, EVT VT, unsigned Align=0, int Offset=0, unsigned char TargetFlags=0)
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned char TargetFlags=0)
TokenFactor - This node takes multiple tokens as input and produces a single token result...
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
#define HEXAGON_LRFP_SIZE
CCState - This class holds information needed while lowering arguments and return values...
unsigned countPopulation(T Value)
Count the number of set bits in a value.
Value * CreateZExt(Value *V, Type *DestTy, const Twine &Name="")
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
void setExceptionPointerRegister(unsigned R)
If set to a physical register, this sets the register that receives the exception address on entry to...
static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, SDLoc dl)
CreateCopyOfByValArgument - Make a copy of an aggregate at address specified by "Src" to address "Dst...
SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
void addAllocaAdjustInst(MachineInstr *MI)
SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const
Type * getType() const
All values are typed, get the type of this value.
CCValAssign - Represent assignment of one arg/retval to a location.
const SDValue & getChain() const
Byte Swap and Counting operators.
CHAIN = SC CHAIN, Imm128 - System call.
ConstantInt * getInt32(uint32_t C)
Get a constant 32-bit value.
BasicBlock * GetInsertBlock() const
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Represents one node in the SelectionDAG.
static MachinePointerInfo getStack(int64_t Offset)
getStack - stack pointer relative access.
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
static mvt_range integer_valuetypes()
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
void setMinimumJumpTableEntries(int Val)
Indicate the number of blocks to generate jump tables rather than if sequence.
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
Class for arbitrary precision integers.
void setExceptionSelectorRegister(unsigned R)
If set to a physical register, this sets the register that receives the exception typeid on entry to ...
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
A "pseudo-class" with methods for operating on BUILD_VECTORs.
Select(COND, TRUEVAL, FALSEVAL).
void setMinFunctionAlignment(unsigned Align)
Set the target's minimum function alignment (in log2(bytes))
int64_t getSExtValue() const
bool isIntegerTy() const
isIntegerTy - True if this is an instance of IntegerType.
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
Return the register class that should be used for the specified value type.
void setPrefLoopAlignment(unsigned Align)
Set the target's preferred loop alignment.
ZERO_EXTEND - Used for integer types, zeroing the new bits.
void setHasAddressTaken()
setHasAddressTaken - Set this block to reflect that it potentially is the target of an indirect branc...
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
ANY_EXTEND - Used for integer types. The high bits are undefined.
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
static cl::opt< int > MaxStoresPerMemsetCL("max-store-memset", cl::Hidden, cl::ZeroOrMore, cl::init(8), cl::desc("Max #stores to inline memset"))
static SDValue LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG)
static SDValue createSplat(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue Val)
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
BR_JT - Jumptable branch.
Representation of each machine instruction.
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned char TargetFlags=0)
SmallVector< SDValue, 32 > OutVals
static cl::opt< bool > EnableHexSDNodeSched("enable-hexagon-sdnode-sched", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Enable Hexagon SDNode scheduling"))
Bitwise operators - logical and, logical or, logical xor.
bool IsEligibleForTailCallOptimization(SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet, bool isCallerStructRet, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SmallVectorImpl< ISD::InputArg > &Ins, SelectionDAG &DAG) const
IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization...
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) const
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static IntegerType * getInt32Ty(LLVMContext &C)
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
int getVarArgsFrameIndex()
unsigned getStoreSizeInBits() const
getStoreSizeInBits - Return the number of bits overwritten by a store of the specified value type...
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
static bool RetCC_Hexagon(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
FunctionType * getFunctionType() const
static cl::opt< int > MaxStoresPerMemcpyOptSizeCL("max-store-memcpy-Os", cl::Hidden, cl::ZeroOrMore, cl::init(4), cl::desc("Max #stores to inline memcpy"))
unsigned MaxStoresPerMemmoveOptSize
Maximum number of store instructions that may be substituted for a call to memmove, used for functions with OpSize attribute.
Value * emitLoadLinked(IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const override
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type...
unsigned MaxStoresPerMemcpyOptSize
Maximum number of store operations that may be substituted for a call to memcpy, used for functions w...
void setStackPointerRegisterToSaveRestore(unsigned R)
If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
static bool CC_Hexagon_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
static bool CC_Hexagon64(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
static CCValAssign getMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG)
FSINCOS - Compute both fsin and fcos as a single operation.
bool isInt< 16 >(int64_t x)
unsigned MaxStoresPerMemcpy
Specify maximum bytes of store instructions per memcpy call.
static EVT getEVT(Type *Ty, bool HandleUnknown=false)
getEVT - Return the value type corresponding to the specified type.
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const
EVT getValueType() const
Return the ValueType of the referenced return value.
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 'eh_return' gcc dwarf builtin...
SDValue getConstant(uint64_t Val, SDLoc DL, EVT VT, bool isTarget=false, bool isOpaque=false)
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
void setReturnAddressIsTaken(bool s)
bool isSimple() const
isSimple - Test if the given EVT is simple (as opposed to being extended).
unsigned getAlignment() const
static cl::opt< int > MaxStoresPerMemcpyCL("max-store-memcpy", cl::Hidden, cl::ZeroOrMore, cl::init(6), cl::desc("Max #stores to inline memcpy"))
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
SDValue getTargetExtractSubreg(int SRIdx, SDLoc DL, EVT VT, SDValue Operand)
A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG nodes.
unsigned getPrimitiveSizeInBits() const LLVM_READONLY
getPrimitiveSizeInBits - Return the basic size of this type if it is a primitive type.
Module * getParent()
Get the module that this global value is contained inside of...
LLVM Value Representation.
FMA - Perform a * b + c with no intermediate rounding step.
SDValue getRegister(unsigned Reg, EVT VT)
void setInsertFencesForAtomic(bool fence)
Set if the DAG builder should automatically insert fences and reduce the order of atomic memory opera...
static bool RetCC_Hexagon32(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
Primary interface to the complete machine description for the target machine.
static bool isCommonSplatElement(BuildVectorSDNode *BVN)
StringRef - Represent a constant reference to a string, i.e.
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
LowerCall - Functions arguments are copied from virtual regs to (physical regs)/(stack frame)...
SetCC operator - This evaluates to a true value iff the condition is true.
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
unsigned MaxStoresPerMemsetOptSize
Maximum number of stores operations that may be substituted for the call to memset, used for functions with OptSize attribute.
unsigned getLocMemOffset() const
SDValue LowerINSERT_VECTOR(SDValue Op, SelectionDAG &DAG) const
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
TRUNCATE - Completely drop the high bits.
unsigned getAlignment() const
static cl::opt< int > MaxStoresPerMemmoveCL("max-store-memmove", cl::Hidden, cl::ZeroOrMore, cl::init(6), cl::desc("Max #stores to inline memmove"))
#define LLVM_FUNCTION_NAME
LLVM_FUNCTION_NAME
SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const
static cl::opt< int > MaxStoresPerMemsetOptSizeCL("max-store-memset-Os", cl::Hidden, cl::ZeroOrMore, cl::init(4), cl::desc("Max #stores to inline memset"))
unsigned AllocateReg(unsigned Reg)
AllocateReg - Attempt to allocate one register.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2, FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR - Perform various unary floating point operations.
static cl::opt< bool > EnableFastMath("ffast-math", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Enable Fast Math processing"))
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
unsigned AllocateStack(unsigned Size, unsigned Align)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
const BasicBlock * getParent() const
SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a scalar value into element 0 of the...
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, SDLoc dl, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array...
MVT getSimpleVT() const
getSimpleVT - Return the SimpleValueType held in the specified simple EVT.
SDValue getIntPtrConstant(uint64_t Val, SDLoc DL, bool isTarget=false)
LLVMContext & getContext() const
Get the global data context.
HexagonTargetLowering(const TargetMachine &TM, const HexagonSubtarget &ST)
void setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed store does or does not work with the specified type and indicate ...
uint64_t getZExtValue() const
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
unsigned getVectorNumElements() const
getVectorNumElements - Given a vector type, return the number of elements it contains.
This class is used to represent ISD::LOAD nodes.
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary...