LLVM  3.7.0
MipsRegisterInfo.cpp
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1 //===-- MipsRegisterInfo.cpp - MIPS Register Information -== --------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the MIPS implementation of the TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsRegisterInfo.h"
15 #include "Mips.h"
16 #include "MipsAnalyzeImmediate.h"
17 #include "MipsInstrInfo.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsSubtarget.h"
20 #include "MipsTargetMachine.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/STLExtras.h"
27 #include "llvm/IR/Constants.h"
28 #include "llvm/IR/DebugInfo.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/Type.h"
32 #include "llvm/Support/Debug.h"
39 
40 using namespace llvm;
41 
42 #define DEBUG_TYPE "mips-reg-info"
43 
44 #define GET_REGINFO_TARGET_DESC
45 #include "MipsGenRegisterInfo.inc"
46 
48 
49 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
50 
51 const TargetRegisterClass *
53  unsigned Kind) const {
54  MipsABIInfo ABI = MF.getSubtarget<MipsSubtarget>().getABI();
55  return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
56 }
57 
58 unsigned
60  MachineFunction &MF) const {
61  switch (RC->getID()) {
62  default:
63  return 0;
64  case Mips::GPR32RegClassID:
65  case Mips::GPR64RegClassID:
66  case Mips::DSPRRegClassID: {
68  return 28 - TFI->hasFP(MF);
69  }
70  case Mips::FGR32RegClassID:
71  return 32;
72  case Mips::AFGR64RegClassID:
73  return 16;
74  case Mips::FGR64RegClassID:
75  return 32;
76  }
77 }
78 
79 //===----------------------------------------------------------------------===//
80 // Callee Saved Registers methods
81 //===----------------------------------------------------------------------===//
82 
83 /// Mips Callee Saved Registers
84 const MCPhysReg *
86  const MipsSubtarget &Subtarget = MF->getSubtarget<MipsSubtarget>();
87  if (Subtarget.isSingleFloat())
88  return CSR_SingleFloatOnly_SaveList;
89 
90  if (Subtarget.isABI_N64())
91  return CSR_N64_SaveList;
92 
93  if (Subtarget.isABI_N32())
94  return CSR_N32_SaveList;
95 
96  if (Subtarget.isFP64bit())
97  return CSR_O32_FP64_SaveList;
98 
99  if (Subtarget.isFPXX())
100  return CSR_O32_FPXX_SaveList;
101 
102  return CSR_O32_SaveList;
103 }
104 
105 const uint32_t *
107  CallingConv::ID) const {
108  const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
109  if (Subtarget.isSingleFloat())
110  return CSR_SingleFloatOnly_RegMask;
111 
112  if (Subtarget.isABI_N64())
113  return CSR_N64_RegMask;
114 
115  if (Subtarget.isABI_N32())
116  return CSR_N32_RegMask;
117 
118  if (Subtarget.isFP64bit())
119  return CSR_O32_FP64_RegMask;
120 
121  if (Subtarget.isFPXX())
122  return CSR_O32_FPXX_RegMask;
123 
124  return CSR_O32_RegMask;
125 }
126 
128  return CSR_Mips16RetHelper_RegMask;
129 }
130 
133  static const MCPhysReg ReservedGPR32[] = {
134  Mips::ZERO, Mips::K0, Mips::K1, Mips::SP
135  };
136 
137  static const MCPhysReg ReservedGPR64[] = {
138  Mips::ZERO_64, Mips::K0_64, Mips::K1_64, Mips::SP_64
139  };
140 
141  BitVector Reserved(getNumRegs());
142  const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
143  typedef TargetRegisterClass::const_iterator RegIter;
144 
145  for (unsigned I = 0; I < array_lengthof(ReservedGPR32); ++I)
146  Reserved.set(ReservedGPR32[I]);
147 
148  // Reserve registers for the NaCl sandbox.
149  if (Subtarget.isTargetNaCl()) {
150  Reserved.set(Mips::T6); // Reserved for control flow mask.
151  Reserved.set(Mips::T7); // Reserved for memory access mask.
152  Reserved.set(Mips::T8); // Reserved for thread pointer.
153  }
154 
155  for (unsigned I = 0; I < array_lengthof(ReservedGPR64); ++I)
156  Reserved.set(ReservedGPR64[I]);
157 
158  // For mno-abicalls, GP is a program invariant!
159  if (!Subtarget.isABICalls()) {
160  Reserved.set(Mips::GP);
161  Reserved.set(Mips::GP_64);
162  }
163 
164  if (Subtarget.isFP64bit()) {
165  // Reserve all registers in AFGR64.
166  for (RegIter Reg = Mips::AFGR64RegClass.begin(),
167  EReg = Mips::AFGR64RegClass.end(); Reg != EReg; ++Reg)
168  Reserved.set(*Reg);
169  } else {
170  // Reserve all registers in FGR64.
171  for (RegIter Reg = Mips::FGR64RegClass.begin(),
172  EReg = Mips::FGR64RegClass.end(); Reg != EReg; ++Reg)
173  Reserved.set(*Reg);
174  }
175  // Reserve FP if this function should have a dedicated frame pointer register.
176  if (Subtarget.getFrameLowering()->hasFP(MF)) {
177  if (Subtarget.inMips16Mode())
178  Reserved.set(Mips::S0);
179  else {
180  Reserved.set(Mips::FP);
181  Reserved.set(Mips::FP_64);
182 
183  // Reserve the base register if we need to both realign the stack and
184  // allocate variable-sized objects at runtime. This should test the
185  // same conditions as MipsFrameLowering::hasBP().
186  if (needsStackRealignment(MF) &&
188  Reserved.set(Mips::S7);
189  Reserved.set(Mips::S7_64);
190  }
191  }
192  }
193 
194  // Reserve hardware registers.
195  Reserved.set(Mips::HWR29);
196 
197  // Reserve DSP control register.
198  Reserved.set(Mips::DSPPos);
199  Reserved.set(Mips::DSPSCount);
200  Reserved.set(Mips::DSPCarry);
201  Reserved.set(Mips::DSPEFI);
202  Reserved.set(Mips::DSPOutFlag);
203 
204  // Reserve MSA control registers.
205  Reserved.set(Mips::MSAIR);
206  Reserved.set(Mips::MSACSR);
207  Reserved.set(Mips::MSAAccess);
208  Reserved.set(Mips::MSASave);
209  Reserved.set(Mips::MSAModify);
210  Reserved.set(Mips::MSARequest);
211  Reserved.set(Mips::MSAMap);
212  Reserved.set(Mips::MSAUnmap);
213 
214  // Reserve RA if in mips16 mode.
215  if (Subtarget.inMips16Mode()) {
216  const MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
217  Reserved.set(Mips::RA);
218  Reserved.set(Mips::RA_64);
219  Reserved.set(Mips::T0);
220  Reserved.set(Mips::T1);
221  if (MF.getFunction()->hasFnAttribute("saveS2") || MipsFI->hasSaveS2())
222  Reserved.set(Mips::S2);
223  }
224 
225  // Reserve GP if small section is used.
226  if (Subtarget.useSmallSection()) {
227  Reserved.set(Mips::GP);
228  Reserved.set(Mips::GP_64);
229  }
230 
231  if (Subtarget.isABI_O32() && !Subtarget.useOddSPReg()) {
232  for (const auto &Reg : Mips::OddSPRegClass)
233  Reserved.set(Reg);
234  }
235 
236  return Reserved;
237 }
238 
239 bool
241  return true;
242 }
243 
244 bool
246  return true;
247 }
248 
249 // FrameIndex represent objects inside a abstract stack.
250 // We must replace FrameIndex with an stack/frame pointer
251 // direct reference.
254  unsigned FIOperandNum, RegScavenger *RS) const {
255  MachineInstr &MI = *II;
256  MachineFunction &MF = *MI.getParent()->getParent();
257 
258  DEBUG(errs() << "\nFunction : " << MF.getName() << "\n";
259  errs() << "<--------->\n" << MI);
260 
261  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
262  uint64_t stackSize = MF.getFrameInfo()->getStackSize();
263  int64_t spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
264 
265  DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
266  << "spOffset : " << spOffset << "\n"
267  << "stackSize : " << stackSize << "\n");
268 
269  eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset);
270 }
271 
272 unsigned MipsRegisterInfo::
274  const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
275  const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
276  bool IsN64 =
277  static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI().IsN64();
278 
279  if (Subtarget.inMips16Mode())
280  return TFI->hasFP(MF) ? Mips::S0 : Mips::SP;
281  else
282  return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) :
283  (IsN64 ? Mips::SP_64 : Mips::SP);
284 }
285 
287  const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
288  unsigned FP = Subtarget.isGP32bit() ? Mips::FP : Mips::FP_64;
289  unsigned BP = Subtarget.isGP32bit() ? Mips::S7 : Mips::S7_64;
290 
291  // Support dynamic stack realignment only for targets with standard encoding.
292  if (!Subtarget.hasStandardEncoding())
293  return false;
294 
295  // We can't perform dynamic stack realignment if we can't reserve the
296  // frame pointer register.
297  if (!MF.getRegInfo().canReserveReg(FP))
298  return false;
299 
300  // We can realign the stack if we know the maximum call frame size and we
301  // don't have variable sized objects.
302  if (Subtarget.getFrameLowering()->hasReservedCallFrame(MF))
303  return true;
304 
305  // We have to reserve the base pointer register in the presence of variable
306  // sized objects.
307  return MF.getRegInfo().canReserveReg(BP);
308 }
309 
311  const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
312  const MachineFrameInfo *MFI = MF.getFrameInfo();
313 
314  bool CanRealign = canRealignStack(MF);
315 
316  // Avoid realigning functions that explicitly do not want to be realigned.
317  // Normally, we should report an error when a function should be dynamically
318  // realigned but also has the attribute no-realign-stack. Unfortunately,
319  // with this attribute, MachineFrameInfo clamps each new object's alignment
320  // to that of the stack's alignment as specified by the ABI. As a result,
321  // the information of whether we have objects with larger alignment
322  // requirement than the stack's alignment is already lost at this point.
323  if (MF.getFunction()->hasFnAttribute("no-realign-stack"))
324  return false;
325 
326  const Function *F = MF.getFunction();
328 #ifdef DEBUG
329  if (!CanRealign)
330  DEBUG(dbgs() << "It's not possible to realign the stack of the function: "
331  << F->getName() << "\n");
332 #endif
333  return CanRealign;
334  }
335 
336  unsigned StackAlignment = Subtarget.getFrameLowering()->getStackAlignment();
337  if (MFI->getMaxAlignment() > StackAlignment) {
338 #ifdef DEBUG
339  if (!CanRealign)
340  DEBUG(dbgs() << "It's not possible to realign the stack of the function: "
341  << F->getName() << "\n");
342 #endif
343  return CanRealign;
344  }
345 
346  return false;
347 }
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
const MCPhysReg * const_iterator
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:240
BitVector & set()
Definition: BitVector.h:218
bool ArePtrs64bit() const
Definition: MipsABIInfo.h:72
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Alignment of stack for function (3 bits) stored as log2 of alignment with +1 bias 0 means unaligned (...
Definition: Attributes.h:106
unsigned getID() const
getID() - Return the register class ID number.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
unsigned getFrameRegister(const MachineFunction &MF) const override
Debug information queries.
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
const_iterator begin(StringRef path)
Get begin iterator over path.
Definition: Path.cpp:232
F(f)
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
bool isFPXX() const
bool isGP32bit() const
bool canReserveReg(unsigned PhysReg) const
canReserveReg - Returns true if PhysReg can be used as a reserved register.
StringRef getName() const
Return a constant reference to the value's name.
Definition: Value.cpp:188
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
virtual bool hasFP(const MachineFunction &MF) const =0
hasFP - Return true if the specified function should have a dedicated frame pointer register...
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
BitVector getReservedRegs(const MachineFunction &MF) const override
const TargetFrameLowering * getFrameLowering() const override
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:120
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:247
bundle_iterator< MachineInstr, instr_iterator > iterator
friend const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:240
bool useOddSPReg() const
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
bool isFP64bit() const
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind) const override
Code Generation virtual methods...
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
bool inMips16Mode() const
virtual bool hasReservedCallFrame(const MachineFunction &MF) const
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required, we reserve argument space for call sites in the function immediately on entry to the current function.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
virtual const TargetFrameLowering * getFrameLowering() const
bool isTargetNaCl() const
bool isABICalls() const
static unsigned getPICCallReg()
Get PIC indirect call register.
bool isABI_N64() const
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Mips Callee Saved Registers.
Information about stack frame layout on the target.
bool hasStandardEncoding() const
bool canRealignStack(const MachineFunction &MF) const
bool isABI_N32() const
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:123
Representation of each machine instruction.
Definition: MachineInstr.h:51
static const uint32_t * getMips16RetHelperMask()
bool needsStackRealignment(const MachineFunction &MF) const override
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:217
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool isSingleFloat() const
#define I(x, y, z)
Definition: MD5.cpp:54
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
bool isABI_O32() const
const ARM::ArchExtKind Kind
bool useSmallSection() const
bool requiresRegisterScavenging(const MachineFunction &MF) const override
#define DEBUG(X)
Definition: Debug.h:92
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
Stack Frame Processing Methods.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
#define T1