36 #define DEBUG_TYPE "arm-subtarget"
38 #define GET_SUBTARGETINFO_TARGET_DESC
39 #define GET_SUBTARGETINFO_CTOR
40 #include "ARMGenSubtargetInfo.inc"
44 cl::desc(
"Reserve R9, making it unavailable as GPR"));
66 "Generate unaligned accesses only on hardware/OS "
67 "combinations that are known to support them"),
69 "Disallow all unaligned memory accesses"),
70 clEnumValN(NoStrictAlign,
"arm-no-strict-align",
71 "Allow unaligned memory accesses"),
84 "Generate IT block based on arch"),
86 "Disallow deprecated IT based on ARMv8"),
88 "Allow IT blocks based on ARMv7"),
95 initializeEnvironment();
96 initSubtargetFeatures(CPU, FS);
110 const std::string &FS,
113 ARMProcClass(
None), stackAlignment(4), CPUString(CPU), IsLittle(IsLittle),
114 TargetTriple(TT), Options(TM.Options), TM(TM),
115 FrameLowering(initializeFrameLowering(CPU, FS)),
118 InstrInfo(isThumb1Only()
125 void ARMSubtarget::initializeEnvironment() {
193 ArchFS = (
Twine(ArchFS) +
"," +
FS).str();
228 if (
Align == DefaultAlign) {
268 if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) &&
unsigned MispredictPenalty
ValuesClass< DataType > LLVM_END_WITH_NULL values(const char *Arg, DataType Val, const char *Desc,...)
unsigned stackAlignment
stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and ...
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
static cl::opt< bool > ArmUseMOVT("arm-use-movt", cl::init(true), cl::Hidden)
unsigned getMispredictionPenalty() const
unsigned EnableFastISel
EnableFastISel - This flag enables fast-path instruction selection which trades away generated code q...
bool SlowFPVMLx
SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates whether the FP VML[AS] instruct...
bool AllowsUnalignedMem
AllowsUnalignedMem - If true, the subtarget allows unaligned memory accesses for some types...
bool endswith(StringRef Suffix) const
Check if this string ends with the given Suffix.
bool useFastISel() const
True if fast-isel is used.
bool HasVFPv2
HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what floating point ISAs are supported...
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
bool HasHardwareDivideInARM
HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode.
enum llvm::ARMBaseTargetMachine::ARMABI TargetABI
bool isThumb1Only() const
const ARMBaseTargetMachine & TM
bool GenLongCalls
Generate calls via indirect call instructions.
bool SupportsTailCall
SupportsTailCall - True if the OS supports tail call.
static bool isThumb(const MCSubtargetInfo &STI)
bool UseMulOps
UseMulOps - True if non-microcoded fused integer multiply-add and multiply-subtract instructions shou...
bool hasCommonLinkage() const
bool HasRAS
HasRAS - Some processors perform return stack prediction.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
static cl::opt< ITMode > IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT), cl::ZeroOrMore, cl::values(clEnumValN(DefaultIT,"arm-default-it","Generate IT block based on arch"), clEnumValN(RestrictedIT,"arm-restrict-it","Disallow deprecated IT based on ARMv8"), clEnumValN(NoRestrictedIT,"arm-no-restrict-it","Allow IT blocks based on ARMv7"), clEnumValEnd))
bool isTargetDarwin() const
bool HasZeroCycleZeroing
If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are particularly effective at zeroi...
This file contains the simple types necessary to represent the attributes associated with functions a...
bool HasThumb2
HasThumb2 - True if Thumb2 instructions are supported.
bool UnsafeFPMath
Target machine allowed unsafe FP math (such as use of NEON fp)
bool isStrongDefinitionForLinker() const
Returns true if this global's definition will be the one chosen by the linker.
bool Pref32BitThumb
Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions over 16-bit ones...
const Triple & getTargetTriple() const
bool enableAtomicExpand() const override
bool isTargetMachO() const
bool NoARM
NoARM - True if subtarget does not support ARM mode execution.
bool hasAnyDataBarrier() const
bool HasT2ExtractPack
HasT2ExtractPack - True if subtarget supports thumb2 extract/pack instructions.
bool HasPerfMon
If true, the processor supports the Performance Monitor Extensions.
bool isTargetNetBSD() const
bool isiOS() const
Is this an iOS triple.
bool AvoidMOVsShifterOperand
AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting movs with shifter operand ...
bool HasCRC
HasCRC - if true, processor supports CRC instructions.
initializer< Ty > init(const Ty &Val)
unsigned UnsafeFPMath
UnsafeFPMath - This flag is enabled when the -enable-unsafe-fp-math flag is specified on the command ...
bool HasVirtualization
HasVirtualization - True if the subtarget supports the Virtualization extension.
bool RestrictIT
RestrictIT - If true, the subtarget disallows generation of deprecated IT blocks to conform to ARMv8 ...
static cl::opt< bool > UseFusedMulOps("arm-use-mulops", cl::init(true), cl::Hidden)
bool hasHiddenVisibility() const
bool UseMovt
UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit imms (including global add...
bool HasV4TOps
HasV4TOps, HasV5TOps, HasV5TEOps, HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops - Specify whether target support specific ARM ISA variants.
bool HasVMLxForwarding
HasVMLxForwarding - If true, NEON has special multiplier accumulator forwarding to allow mul + mla be...
bool HasCrypto
HasCrypto - if true, processor supports Cryptography extensions.
bool Thumb2DSP
Thumb2DSP - If true, the subtarget supports the v7 DSP (saturating arith and such) instructions in Th...
bool HasMPExtension
HasMPExtension - True if the subtarget supports Multiprocessing extension (ARMv7 only).
bool hasSinCos() const
This function returns true if the target has sincos() routine in its compiler runtime or math librari...
Triple - Helper class for working with autoconf configuration names.
bool HasFP16
HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF only so far) ...
bool HasTrustZone
HasTrustZone - if true, processor supports TrustZone security extensions.
bool InThumbMode
InThumbMode - True if compiling for Thumb, false for ARM.
ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const ARMBaseTargetMachine &TM, bool IsLittle)
This constructor initializes the data members to match that of the specified triple.
bool isTargetNaCl() const
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const
GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
bool FPOnlySP
FPOnlySP - If true, the floating point unit only supports single precision.
bool UseNaClTrap
NaCl TRAP instruction is generated instead of the regular TRAP.
MCSchedModel SchedModel
SchedModel - Processor specific instruction costs.
const TargetOptions & Options
Options passed via command line that could influence the target.
static cl::opt< bool > ReserveR9("arm-reserve-r9", cl::Hidden, cl::desc("Reserve R9, making it unavailable as GPR"))
ARMSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
initializeSubtargetDependencies - Initializes using a CPU and feature string so that we can use initi...
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(DefaultAlign), cl::values(clEnumValN(DefaultAlign,"arm-default-align","Generate unaligned accesses only on hardware/OS ""combinations that are known to support them"), clEnumValN(StrictAlign,"arm-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"arm-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
bool UseSoftFloat
UseSoftFloat - True if we're using software floating point features.
bool isOSVersionLT(unsigned Major, unsigned Minor=0, unsigned Micro=0) const
isOSVersionLT - Helper function for doing comparisons against version numbers included in the target ...
bool IsR9Reserved
IsR9Reserved - True if R9 is a not available as general purpose register.
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
bool isTargetLinux() const
StringRef getArchName() const
getArchName - Get the architecture (first) component of the triple.
InstrItineraryData InstrItins
Selected instruction itineraries (one entry per itinerary class.)
bool UseNEONForSinglePrecisionFP
UseNEONForSinglePrecisionFP - if the NEONFP attribute has been specified.
bool useMovt(const MachineFunction &MF) const
bool hasLocalLinkage() const
bool SlowFPBrcc
SlowFPBrcc - True if floating point compare + branch is slow.
bool HasD16
HasD16 - True if subtarget is limited to 16 double precision FP registers for VFPv3.
bool enablePostRAScheduler() const override
True for some subtargets at > -O0.
bool AvoidCPSRPartialUpdate
AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions that partially update CPSR a...
std::string ParseARMTriple(const Triple &TT, StringRef CPU)
std::string CPUString
CPUString - String name of used CPU.
StringRef - Represent a constant reference to a string, i.e.
bool HasDataBarrier
HasDataBarrier - True if the subtarget supports DMB / DSB data barrier instructions.
bool isDeclarationForLinker() const
bool isTargetWindows() const
bool HasHardwareDivide
HasHardwareDivide - True if subtarget supports [su]div.
bool empty() const
empty - Check if the string is empty.
Function must be optimized for size first.