16 #ifndef LLVM_LIB_TARGET_ARM_THUMB1REGISTERINFO_H
17 #define LLVM_LIB_TARGET_ARM_THUMB1REGISTERINFO_H
24 class ARMBaseInstrInfo;
36 unsigned Kind = 0)
const override;
42 DebugLoc dl,
unsigned DestReg,
unsigned SubIdx,
int Val,
50 unsigned FrameReg,
int &Offset,
53 int64_t Offset)
const override;
58 unsigned Reg)
const override;
60 int SPAdj,
unsigned FIOperandNum,
void emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred=ARMCC::AL, unsigned PredReg=0, unsigned MIFlags=MachineInstr::NoFlags) const override
emitLoadConstPool - Emits a load from constpool to materialize the specified immediate.
bool saveScavengerRegister(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, unsigned Reg) const override
saveScavengerRegister - Spill the register so it can be used by the register scavenger.
const HexagonInstrInfo * TII
Reg
All possible values of the reg field in the ModR/M byte.
void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override
bundle_iterator< MachineInstr, instr_iterator > iterator
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
Representation of each machine instruction.
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
bool rewriteFrameIndex(MachineBasicBlock::iterator II, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const ARMBaseInstrInfo &TII) const
const ARM::ArchExtKind Kind