31 #define DEBUG_TYPE "mccodeemitter"
33 STATISTIC(MCNumEmitted,
"Number of MC instructions emitted");
37 PPCMCCodeEmitter(
const PPCMCCodeEmitter &) =
delete;
38 void operator=(
const PPCMCCodeEmitter &) =
delete;
46 : MCII(mcii), CTX(ctx),
47 IsLittleEndian(ctx.getAsmInfo()->isLittleEndian()) {}
49 ~PPCMCCodeEmitter()
override {}
51 unsigned getDirectBrEncoding(
const MCInst &
MI,
unsigned OpNo,
54 unsigned getCondBrEncoding(
const MCInst &
MI,
unsigned OpNo,
57 unsigned getAbsDirectBrEncoding(
const MCInst &
MI,
unsigned OpNo,
60 unsigned getAbsCondBrEncoding(
const MCInst &
MI,
unsigned OpNo,
63 unsigned getImm16Encoding(
const MCInst &
MI,
unsigned OpNo,
66 unsigned getMemRIEncoding(
const MCInst &
MI,
unsigned OpNo,
69 unsigned getMemRIXEncoding(
const MCInst &
MI,
unsigned OpNo,
72 unsigned getSPE8DisEncoding(
const MCInst &
MI,
unsigned OpNo,
75 unsigned getSPE4DisEncoding(
const MCInst &
MI,
unsigned OpNo,
78 unsigned getSPE2DisEncoding(
const MCInst &
MI,
unsigned OpNo,
81 unsigned getTLSRegEncoding(
const MCInst &
MI,
unsigned OpNo,
84 unsigned getTLSCallEncoding(
const MCInst &
MI,
unsigned OpNo,
87 unsigned get_crbitm_encoding(
const MCInst &
MI,
unsigned OpNo,
99 uint64_t getBinaryCodeForInstr(
const MCInst &
MI,
113 uint64_t
Bits = getBinaryCodeForInstr(MI, Fixups, STI);
116 unsigned Size = Desc.
getSize();
119 if (IsLittleEndian) {
128 if (IsLittleEndian) {
129 uint64_t Swapped = (Bits << 32) | (Bits >> 32);
149 return new PPCMCCodeEmitter(MCII, Ctx);
152 unsigned PPCMCCodeEmitter::
153 getDirectBrEncoding(
const MCInst &MI,
unsigned OpNo,
157 if (MO.
isReg() || MO.
isImm())
return getMachineOpValue(MI, MO, Fixups, STI);
165 unsigned PPCMCCodeEmitter::getCondBrEncoding(
const MCInst &MI,
unsigned OpNo,
169 if (MO.
isReg() || MO.
isImm())
return getMachineOpValue(MI, MO, Fixups, STI);
177 unsigned PPCMCCodeEmitter::
178 getAbsDirectBrEncoding(
const MCInst &MI,
unsigned OpNo,
182 if (MO.
isReg() || MO.
isImm())
return getMachineOpValue(MI, MO, Fixups, STI);
190 unsigned PPCMCCodeEmitter::
191 getAbsCondBrEncoding(
const MCInst &MI,
unsigned OpNo,
195 if (MO.
isReg() || MO.
isImm())
return getMachineOpValue(MI, MO, Fixups, STI);
203 unsigned PPCMCCodeEmitter::getImm16Encoding(
const MCInst &MI,
unsigned OpNo,
207 if (MO.
isReg() || MO.
isImm())
return getMachineOpValue(MI, MO, Fixups, STI);
215 unsigned PPCMCCodeEmitter::getMemRIEncoding(
const MCInst &MI,
unsigned OpNo,
221 unsigned RegBits = getMachineOpValue(MI, MI.
getOperand(OpNo+1),
Fixups, STI) << 16;
225 return (getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF) | RegBits;
234 unsigned PPCMCCodeEmitter::getMemRIXEncoding(
const MCInst &MI,
unsigned OpNo,
240 unsigned RegBits = getMachineOpValue(MI, MI.
getOperand(OpNo+1),
Fixups, STI) << 14;
244 return ((getMachineOpValue(MI, MO, Fixups, STI) >> 2) & 0x3FFF) | RegBits;
253 unsigned PPCMCCodeEmitter::getSPE8DisEncoding(
const MCInst &MI,
unsigned OpNo,
260 uint32_t RegBits = getMachineOpValue(MI, MI.
getOperand(OpNo+1),
Fixups, STI) << 5;
264 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 3;
269 unsigned PPCMCCodeEmitter::getSPE4DisEncoding(
const MCInst &MI,
unsigned OpNo,
276 uint32_t RegBits = getMachineOpValue(MI, MI.
getOperand(OpNo+1),
Fixups, STI) << 5;
280 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 2;
285 unsigned PPCMCCodeEmitter::getSPE2DisEncoding(
const MCInst &MI,
unsigned OpNo,
292 uint32_t RegBits = getMachineOpValue(MI, MI.
getOperand(OpNo+1),
Fixups, STI) << 5;
296 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 1;
301 unsigned PPCMCCodeEmitter::getTLSRegEncoding(
const MCInst &MI,
unsigned OpNo,
305 if (MO.
isReg())
return getMachineOpValue(MI, MO, Fixups, STI);
314 return CTX.getRegisterInfo()->getEncodingValue(isPPC64 ? PPC::X13 :
PPC::R2);
317 unsigned PPCMCCodeEmitter::getTLSCallEncoding(
const MCInst &MI,
unsigned OpNo,
326 return getDirectBrEncoding(MI, OpNo, Fixups, STI);
329 unsigned PPCMCCodeEmitter::
330 get_crbitm_encoding(
const MCInst &MI,
unsigned OpNo,
337 return 0x80 >> CTX.getRegisterInfo()->getEncodingValue(MO.
getReg());
341 unsigned PPCMCCodeEmitter::
351 return CTX.getRegisterInfo()->getEncodingValue(MO.
getReg());
355 "Relocation required in an instruction that we cannot encode!");
360 #include "PPCGenMCCodeEmitter.inc"
void push_back(const T &Elt)
STATISTIC(NumFunctions,"Total number of functions")
Describe properties that are true of each instruction in the target description file.
fixup_ppc_brcond14abs - 14-bit absolute relocation for conditional branches.
fixup_ppc_half16 - A 16-bit fixup corresponding to lo16(_foo) or ha16(_foo) for instrs like 'li' or '...
fixup_ppc_br24abs - 24-bit absolute relocation for direct branches like 'ba' and 'bla'.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
fixup_ppc_nofixup - Not a true fixup, but ties a symbol to a call to __tls_get_addr for the TLS gener...
Context object for machine code objects.
unsigned getReg() const
Returns the register number.
R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Instances of this class represent a single low-level machine instruction.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
const MCExpr * getExpr() const
MCCodeEmitter - Generic instruction encoding interface.
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Interface to description of machine instruction set.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Triple - Helper class for working with autoconf configuration names.
unsigned getOpcode() const
fixup_ppc_half16ds - A 14-bit fixup corresponding to lo16(_foo) with implied 2 zero bits for instrs l...
Adapter to write values to a stream in a particular byte order.
COPY_TO_REGCLASS - This instruction is a placeholder for a plain register-to-register copy into a spe...
MCSubtargetInfo - Generic base class for all target subtargets.
const Triple & getTargetTriple() const
getTargetTriple - Return the target triple string.
This class implements an extremely fast bulk output stream that can only output to a stream...
fixup_ppc_brcond14 - 14-bit PC relative relocation for conditional branches.
T reverseBits(T Val)
Reverse the bits in Val.
Instances of this class represent operands of the MCInst class.
MCCodeEmitter * createPPCMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
const MCOperand & getOperand(unsigned i) const