14 #ifndef LLVM_LIB_TARGET_ARM_ARMBASEREGISTERINFO_H
15 #define LLVM_LIB_TARGET_ARM_ARMBASEREGISTERINFO_H
20 #define GET_REGINFO_HEADER
21 #include "ARMGenRegisterInfo.inc"
37 case R0:
case R1:
case R2:
case R3:
38 case R4:
case R5:
case R6:
case R7:
39 case LR:
case SP:
case PC:
63 case D15:
case D14:
case D13:
case D12:
64 case D11:
case D10:
case D9:
case D8:
73 for (
unsigned i = 0; CSRegs[i]; ++i)
114 unsigned Kind = 0)
const override;
139 int Idx)
const override;
142 unsigned BaseReg,
int FrameIdx,
143 int64_t Offset)
const override;
145 int64_t Offset)
const override;
147 int64_t Offset)
const override;
162 DebugLoc dl,
unsigned DestReg,
unsigned SubIdx,
164 unsigned PredReg = 0,
177 int SPAdj,
unsigned FIOperandNum,
void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const override
materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx...
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
unsigned getBaseRegister() const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
void updateRegAllocHint(unsigned Reg, unsigned NewReg, MachineFunction &MF) const override
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
needsFrameBaseReg - Returns true if the instruction's frame index reference would be better served by...
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
void getRegAllocationHints(unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM) const override
unsigned getFrameRegister(const MachineFunction &MF) const override
Reg
All possible values of the reg field in the ModR/M byte.
bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
const uint32_t * getThisReturnPreservedMask(const MachineFunction &MF, CallingConv::ID) const
getThisReturnPreservedMask - Returns a call preserved mask specific to the case that 'returned' is on...
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
static bool isARMArea1Register(unsigned Reg, bool isIOS)
isARMArea1Register - Returns true if the register is a low register (r0-r7) or a stack/pc register th...
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
static bool isCalleeSavedRegister(unsigned Reg, const MCPhysReg *CSRegs)
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override
bool requiresRegisterScavenging(const MachineFunction &MF) const override
Code Generation virtual methods...
int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const override
bool isLowRegister(unsigned Reg) const
bundle_iterator - MachineBasicBlock iterator that automatically skips over MIs that are inside bundle...
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override
bool canRealignStack(const MachineFunction &MF) const
static bool isARMArea2Register(unsigned Reg, bool isIOS)
const uint32_t * getNoPreservedMask() const
bool hasBasePointer(const MachineFunction &MF) const
void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override
Representation of each machine instruction.
unsigned getOpcode(int Op) const
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC) const override
SrcRC and DstRC will be morphed into NewRC if this returns true.
unsigned BasePtr
BasePtr - ARM physical register used as a base ptr in complex stack frames.
virtual void emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred=ARMCC::AL, unsigned PredReg=0, unsigned MIFlags=MachineInstr::NoFlags) const
emitLoadConstPool - Emits a load from constpool to materialize the specified immediate.
static bool isARMArea3Register(unsigned Reg, bool isIOS)
const ARM::ArchExtKind Kind
bool cannotEliminateFrame(const MachineFunction &MF) const
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
bool needsStackRealignment(const MachineFunction &MF) const override