LLVM  3.7.0
llvm::GenericScheduler Member List

This is the complete list of members for llvm::GenericScheduler, including all inherited members.

BotHeightReduce enum valuellvm::GenericSchedulerBase
BotPathReduce enum valuellvm::GenericSchedulerBase
CandReason enum namellvm::GenericSchedulerBase
checkAcyclicLatency()llvm::GenericSchedulerprotected
Cluster enum valuellvm::GenericSchedulerBase
Contextllvm::GenericSchedulerBaseprotected
GenericScheduler(const MachineSchedContext *C)llvm::GenericSchedulerinline
GenericSchedulerBase(const MachineSchedContext *C)llvm::GenericSchedulerBaseinlineprotected
getReasonStr(GenericSchedulerBase::CandReason Reason)llvm::GenericSchedulerBasestatic
initialize(ScheduleDAGMI *dag) overridellvm::GenericSchedulervirtual
initPolicy(MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, unsigned NumRegionInstrs) overridellvm::GenericSchedulervirtual
NextDefUse enum valuellvm::GenericSchedulerBase
NoCand enum valuellvm::GenericSchedulerBase
NodeOrder enum valuellvm::GenericSchedulerBase
PhysRegCopy enum valuellvm::GenericSchedulerBase
pickNode(bool &IsTopNode) overridellvm::GenericSchedulervirtual
pickNodeBidirectional(bool &IsTopNode)llvm::GenericSchedulerprotected
pickNodeFromQueue(SchedBoundary &Zone, const RegPressureTracker &RPTracker, SchedCandidate &Candidate)llvm::GenericSchedulerprotected
RegCritical enum valuellvm::GenericSchedulerBase
RegExcess enum valuellvm::GenericSchedulerBase
registerRoots() overridellvm::GenericSchedulervirtual
RegMax enum valuellvm::GenericSchedulerBase
releaseBottomNode(SUnit *SU) overridellvm::GenericSchedulerinlinevirtual
releaseTopNode(SUnit *SU) overridellvm::GenericSchedulerinlinevirtual
Remllvm::GenericSchedulerBaseprotected
reschedulePhysRegCopies(SUnit *SU, bool isTop)llvm::GenericSchedulerprotected
ResourceDemand enum valuellvm::GenericSchedulerBase
ResourceReduce enum valuellvm::GenericSchedulerBase
SchedModelllvm::GenericSchedulerBaseprotected
schedNode(SUnit *SU, bool IsTopNode) overridellvm::GenericSchedulervirtual
scheduleTree(unsigned SubtreeID)llvm::MachineSchedStrategyinlinevirtual
setPolicy(CandPolicy &Policy, bool IsPostRA, SchedBoundary &CurrZone, SchedBoundary *OtherZone)llvm::GenericSchedulerBaseprotected
shouldTrackPressure() const overridellvm::GenericSchedulerinlinevirtual
Stall enum valuellvm::GenericSchedulerBase
TopDepthReduce enum valuellvm::GenericSchedulerBase
TopPathReduce enum valuellvm::GenericSchedulerBase
traceCandidate(const SchedCandidate &Cand)llvm::GenericSchedulerBaseprotected
TRIllvm::GenericSchedulerBaseprotected
tryCandidate(SchedCandidate &Cand, SchedCandidate &TryCand, SchedBoundary &Zone, const RegPressureTracker &RPTracker, RegPressureTracker &TempTracker)llvm::GenericSchedulerprotected
Weak enum valuellvm::GenericSchedulerBase
~MachineSchedStrategy()llvm::MachineSchedStrategyinlinevirtual