14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
26 class InstrItineraryData;
29 class MachineMemOperand;
30 class MachineRegisterInfo;
34 class MCSymbolRefExpr;
36 class ScheduleHazardRecognizer;
39 class TargetRegisterClass;
40 class TargetRegisterInfo;
41 class BranchProbability;
42 class TargetSubtargetInfo;
43 class TargetSchedModel;
46 template<
class T>
class SmallVectorImpl;
58 : CallFrameSetupOpcode(CFSetupOpcode),
59 CallFrameDestroyOpcode(CFDestroyOpcode) {
81 isReallyTriviallyReMaterializableGeneric(MI, AA)));
102 bool isReallyTriviallyReMaterializableGeneric(
const MachineInstr *
MI,
126 unsigned &SrcReg,
unsigned &DstReg,
127 unsigned &SubIdx)
const {
189 int &SrcFrameIndex)
const {
207 unsigned &Size,
unsigned &Offset,
225 unsigned DestReg,
unsigned SubIdx,
262 bool NewMI =
false)
const;
268 unsigned &SrcOpIdx2)
const;
325 RegSubRegPairAndIdx &InputReg)
const;
345 RegSubRegPair &BaseReg,
346 RegSubRegPairAndIdx &InsertedReg)
const;
386 bool AllowModify =
false)
const {
431 bool AllowModify =
false)
const {
470 "TargetInstrInfo::getUnconditionalBranch!");
513 unsigned ExtraPredCycles,
526 unsigned NumTCycles,
unsigned ExtraTCycles,
528 unsigned NumFCycles,
unsigned ExtraFCycles,
580 unsigned TrueReg,
unsigned FalseReg,
582 int &TrueCycles,
int &FalseCycles)
const {
604 unsigned TrueReg,
unsigned FalseReg)
const {
628 unsigned &TrueOp,
unsigned &FalseOp,
629 bool &Optimizable)
const {
630 assert(MI && MI->
getDesc().
isSelect() &&
"MI must be a select instruction");
651 bool PreferFalse =
false)
const {
666 unsigned DestReg,
unsigned SrcReg,
667 bool KillSrc)
const {
681 "TargetInstrInfo::storeRegToStackSlot!");
693 "TargetInstrInfo::loadRegFromStackSlot!");
830 unsigned Reg,
bool UnfoldLoad,
bool UnfoldStore,
847 bool UnfoldLoad,
bool UnfoldStore,
848 unsigned *LoadRegIndex =
nullptr)
const {
857 int64_t &Offset1, int64_t &Offset2)
const {
870 int64_t Offset1, int64_t Offset2,
871 unsigned NumLoads)
const {
887 unsigned NumLoads)
const {
941 std::vector<MachineOperand> &Pred)
const {
996 unsigned &SrcReg,
unsigned &SrcReg2,
997 int &Mask,
int &
Value)
const {
1005 unsigned SrcReg,
unsigned SrcReg2,
1006 int Mask,
int Value,
1021 unsigned &FoldAsLoadDefReg,
1053 SDNode *DefNode,
unsigned DefIdx,
1054 SDNode *UseNode,
unsigned UseIdx)
const;
1067 unsigned UseIdx)
const;
1081 unsigned *PredCost =
nullptr)
const;
1142 virtual std::pair<uint16_t, uint16_t>
1144 return std::make_pair(0, 0);
1255 "MIa must load from or modify a memory location");
1257 "MIb must load from or modify a memory location");
1270 unsigned CallFrameSetupOpcode, CallFrameDestroyOpcode;
virtual MachineInstr * duplicate(MachineInstr *Orig, MachineFunction &MF) const
Create a duplicate of the Orig instruction in MF.
virtual ScheduleHazardRecognizer * CreateTargetMIHazardRecognizer(const InstrItineraryData *, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
virtual bool canInsertSelect(const MachineBasicBlock &MBB, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const
Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseRe...
virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, const BranchProbability &Probability) const
Return true if it's profitable for if-converter to duplicate instructions of specified accumulated in...
virtual bool hasStoreToStackSlot(const MachineInstr *MI, const MachineMemOperand *&MMO, int &FrameIndex) const
If the specified machine instruction has a store to a stack slot, return true along with the FrameInd...
virtual bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const
For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two registe...
unsigned computeOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const
Compute and return the latency of the given data dependent def and use when the operand indices are a...
RegSubRegPair(unsigned Reg=0, unsigned SubReg=0)
virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx, unsigned &Size, unsigned &Offset, const MachineFunction &MF) const
Compute the size in bytes and offset within a stack slot of a spilled register or subregister...
virtual void breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum, const TargetRegisterInfo *TRI) const
Insert a dependency-breaking instruction before MI to eliminate an unwanted dependency on OpNum...
virtual bool hasLoadFromStackSlot(const MachineInstr *MI, const MachineMemOperand *&MMO, int &FrameIndex) const
If the specified machine instruction has a load from a stack slot, return true along with the FrameIn...
bool usePreRAHazardRecognizer() const
Provide a global flag for disabling the PreRA hazard recognizer that targets may choose to honor...
Describe properties that are true of each instruction in the target description file.
TargetInstrInfo(unsigned CFSetupOpcode=~0u, unsigned CFDestroyOpcode=~0u)
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
bool getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const
Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx.
bool SingleUseCondition
SingleUseCondition is true if ConditionDef is dead except for the branch(es) at the end of the basic ...
virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e...
virtual void genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern::MC_PATTERN Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could...
virtual ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
virtual bool isSchedulingBoundary(const MachineInstr *MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const
Test if the given instruction should be considered a scheduling boundary.
virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const
This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePt...
virtual void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SubIdx, const MachineInstr *Orig, const TargetRegisterInfo &TRI) const
Re-issue the specified 'original' instruction at the specific location targeting a new destination re...
bool isRematerializable() const
Returns true if this instruction is a candidate for remat.
virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const
Remove the branching code at the end of the specific MBB.
virtual bool DefinesPredicate(MachineInstr *MI, std::vector< MachineOperand > &Pred) const
If the specified instruction defines any predicate or condition code register(s) used for predication...
virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const
Check for post-frame ptr elimination stack locations as well.
Represents a predicate at the MachineFunction level.
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
COPY - Target-independent register copy.
virtual unsigned getPredicationCost(const MachineInstr *MI) const
virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel, const MachineInstr *DefMI, unsigned DefIdx) const
Compute operand latency of a def of 'Reg'.
MachineBasicBlock * TrueDest
MachineMemOperand - A description of a memory reference used in the backend.
unsigned getCallFrameDestroyOpcode() const
Provide an instruction scheduling machine model to CodeGen passes.
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr *LoadMI) const
Target-dependent implementation for foldMemoryOperand.
virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const
Check for post-frame ptr elimination stack locations as well.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
virtual bool areMemAccessesTriviallyDisjoint(MachineInstr *MIa, MachineInstr *MIb, AliasAnalysis *AA=nullptr) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Reg
All possible values of the reg field in the ModR/M byte.
Represent a reference to a symbol from inside an expression.
virtual bool getMemOpBaseRegImmOfs(MachineInstr *MemOp, unsigned &BaseReg, unsigned &Offset, const TargetRegisterInfo *TRI) const
Get the base register and byte offset of an instruction that reads/writes memory. ...
virtual unsigned getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum, const TargetRegisterInfo *TRI) const
Returns the preferred minimum clearance before an instruction with an unwanted partial register updat...
virtual bool AnalyzeBranchPredicate(MachineBasicBlock &MBB, MachineBranchPredicate &MBP, bool AllowModify=false) const
Analyze the branching code at the end of MBB and parse it into the MachineBranchPredicate structure i...
virtual bool produceSameValue(const MachineInstr *MI0, const MachineInstr *MI1, const MachineRegisterInfo *MRI=nullptr) const
Return true if two machine instructions would produce identical values.
virtual bool useMachineCombiner() const
Return true when a target supports MachineCombiner.
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
virtual bool analyzeSelect(const MachineInstr *MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const
Analyze the given select instruction, returning true if it cannot be understood.
unsigned getCallFrameSetupOpcode() const
These methods return the opcode of the frame setup/destroy instructions if they exist (-1 otherwise)...
virtual MachineInstr * commuteInstruction(MachineInstr *MI, bool NewMI=false) const
If a target has any instructions that are commutable but require converting to different instructions...
virtual bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const
Returns true if the first specified predicate subsumes the second, e.g.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Itinerary data supplied by a subtarget to be used by a target.
virtual bool ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const
Reverses the branch condition of the specified condition list, returning false on success and true if...
RegSubRegPairAndIdx(unsigned Reg=0, unsigned SubReg=0, unsigned SubIdx=0)
virtual unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr *MI, unsigned *PredCost=nullptr) const
Compute the instruction latency of a given instruction.
Instances of this class represent a single low-level machine instruction.
virtual unsigned getJumpInstrTableEntryBound() const
Get a number of bytes that suffices to hold either the instruction returned by getUnconditionalBranch...
bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const
Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
virtual bool enableClusterLoads() const
MachineBasicBlock * FalseDest
TargetInstrInfo - Interface to description of machine instruction set.
MachineInstr * ConditionDef
This class is intended to be used as a base class for asm properties and features specific to the tar...
virtual DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &) const
Create machine specific model for scheduling.
IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
bundle_iterator< MachineInstr, instr_iterator > iterator
virtual bool isStackSlotCopy(const MachineInstr *MI, int &DestFrameIndex, int &SrcFrameIndex) const
Return true if the specified machine instruction is a copy of one stack slot to another and has no ot...
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
virtual void getTrap(MCInst &MI) const
Get a machine trap instruction.
virtual bool isAsCheapAsAMove(const MachineInstr *MI) const
Return true if the instruction is as cheap as a move instruction.
unsigned defaultDefLatency(const MCSchedModel &SchedModel, const MachineInstr *DefMI) const
Return the default expected latency for a def based on it's opcode.
virtual MachineInstr * optimizeLoadInstr(MachineInstr *MI, const MachineRegisterInfo *MRI, unsigned &FoldAsLoadDefReg, MachineInstr *&DefMI) const
Try to remove the load by folding it to a register operand at the use.
virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const
This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base a...
virtual void getUnconditionalBranch(MCInst &MI, const MCSymbolRefExpr *BranchTarget) const
Get an instruction that performs an unconditional branch to the given symbol.
bool isAsCheapAsAMove(QueryType Type=AllInBundle) const
Returns true if this instruction has the same cost (or less) than a move instruction.
bundle_iterator - MachineBasicBlock iterator that automatically skips over MIs that are inside bundle...
virtual int getSPAdjust(const MachineInstr *MI) const
Returns the actual stack pointer adjustment made by an instruction as part of a call sequence...
Interface to description of machine instruction set.
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Load the specified register of the given register class from the specified stack frame index...
virtual unsigned getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum, const TargetRegisterInfo *TRI) const
Return the minimum clearance before an instruction that reads an unused register. ...
virtual unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
If the specified machine instruction is a direct store to a stack slot, return the virtual or physica...
virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const
unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a st...
virtual bool getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const
Target-dependent implementation of getInsertSubregInputs.
virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB, unsigned NumFCycles, unsigned ExtraFCycles, const BranchProbability &Probability) const
Second variant of isProfitableToIfCvt.
virtual bool shouldClusterLoads(MachineInstr *FirstLdSt, MachineInstr *SecondLdSt, unsigned NumLoads) const
virtual bool optimizeCondBranch(MachineInstr *MI) const
virtual void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Store the specified register of the given register class to the specified stack frame index...
virtual void setExecutionDomain(MachineInstr *MI, unsigned Domain) const
Change the opcode of MI to execute in Domain.
bool isZeroCost(unsigned Opcode) const
Return true for pseudo instructions that don't consume any machine resources in their current form...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI, AliasAnalysis *AA) const
For instructions with opcodes for which the M_REMATERIALIZABLE flag is set, this hook lets the target...
virtual void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
Insert a noop into the instruction stream at the specified point.
virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const
If specified MI is commutable, return the two operand indices that would swap value.
bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const
Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
virtual MachineInstr * optimizeSelect(MachineInstr *MI, SmallPtrSetImpl< MachineInstr * > &NewMIs, bool PreferFalse=false) const
Given a select instruction that was understood by analyzeSelect and returned Optimizable = true...
virtual ~TargetInstrInfo()
MachineOperand class - Representation of each machine instruction operand.
A pair composed of a register and a sub-register index.
virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr *MI) const
Return the number of u-operations the given machine instruction will be decoded to on the target cpu...
virtual MachineInstr * convertToThreeAddress(MachineFunction::iterator &MFI, MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const
This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag.
virtual bool verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const
Perform target-specific instruction verification.
bool isTriviallyReMaterializable(const MachineInstr *MI, AliasAnalysis *AA=nullptr) const
Return true if the instruction is trivially rematerializable, meaning it has no side effects and requ...
virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const
Returns true if the instruction is a terminator instruction that has not been predicated.
virtual bool isPredicable(MachineInstr *MI) const
Return true if the specified instruction can be predicated.
Represents one node in the SelectionDAG.
virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const
Compute operand latency between a def of 'Reg' and a use in the current loop.
virtual void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const
Emit instructions to copy a pair of physical registers.
MachineInstr * foldMemoryOperand(MachineBasicBlock::iterator MI, ArrayRef< unsigned > Ops, int FrameIndex) const
Attempt to fold a load or store of the specified stack slot into the specified machine instruction fo...
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const
Target-dependent implementation of getExtractSubregInputs.
virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const
Return true if it's legal to split the given basic block at the specified instruction (i...
Representation of each machine instruction.
virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, SmallVectorImpl< SDNode * > &NewNodes) const
virtual unsigned getInlineAsmLength(const char *Str, const MCAsmInfo &MAI) const
Measure the specified inline asm to determine an approximation of its length.
virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, unsigned Reg, MachineRegisterInfo *MRI) const
'Reg' is known to be defined by a move immediate instruction, try to fold the immediate into the use ...
virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, const BranchProbability &Probability) const
Return true if it's profitable to predicate instructions with accumulated instruction latency of "Num...
virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
If the specified machine instruction is a direct load from a stack slot, return the virtual or physic...
virtual bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const
See if the comparison instruction can be converted into something more efficient. ...
virtual bool getRegSequenceLikeInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const
Target-dependent implementation of getRegSequenceInputs.
virtual void getNoopForMachoTarget(MCInst &NopInst) const
Return the noop instruction to use for a noop.
virtual int getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, DebugLoc DL) const
Insert branch code into the end of the specified MachineBasicBlock.
virtual bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern::MC_PATTERN > &Pattern) const
Return true when there is potentially a faster code sequence for an instruction chain ending in Root...
virtual bool canFoldMemoryOperand(const MachineInstr *MI, ArrayRef< unsigned > Ops) const
Returns true for the specified load / store if folding is possible.
bool isSelect() const
Return true if this is a select instruction.
virtual ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
ComparePredicate Predicate
virtual bool PredicateInstruction(MachineInstr *MI, ArrayRef< MachineOperand > Pred) const
Convert the instruction into a predicated instruction.
LLVM Value Representation.
int computeDefOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI) const
If we can determine the operand latency from the def only, without itinerary lookup, do so.
virtual std::pair< uint16_t, uint16_t > getExecutionDomain(const MachineInstr *MI) const
Return the current execution domain and bit mask of possible domains for instruction.
virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const
This function is called for all pseudo instructions that remain after register allocation.
virtual void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const
Insert a select instruction into MBB before I that will copy TrueReg to DstReg when Cond is true...
BasicBlockListType::iterator iterator
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex) const
Target-dependent implementation for foldMemoryOperand.
virtual bool isPredicated(const MachineInstr *MI) const
Returns true if the instruction is already predicated.
virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const
Return true if it's safe to move a machine instruction that defines the specified register class...
StringRef - Represent a constant reference to a string, i.e.
const TargetRegisterClass * getRegClass(const MCInstrDesc &TID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum...
virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const
Delete the instruction OldInst and everything after it, replacing it with an unconditional branch to ...
virtual bool shouldScheduleAdjacent(MachineInstr *First, MachineInstr *Second) const
Can this target fuse the given instructions if they are scheduled adjacent.
virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const
Return true if it's profitable to unpredicate one side of a 'diamond', i.e.
virtual unsigned getMachineCSELookAheadLimit() const
Return the value to use for the MachineCSE's LookAheadLimit, which is a heuristic used for CSE'ing ph...
Machine model for scheduling, bundling, and heuristics.
virtual bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const
Return true if the instruction is a "coalescable" extension instruction.
virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const
Returns the opcode of the would be new instruction after load / store are unfolded from an instructio...
virtual bool isHighLatencyDef(int opc) const
Return true if this opcode has high latency to its result.
A pair composed of a pair of a register and a sub-register index, and another sub-register index...