29 #define GET_INSTRINFO_CTOR_DTOR
30 #include "SparcGenInstrInfo.inc"
33 void SparcInstrInfo::anchor() {}
131 bool AllowModify)
const
136 while (I != MBB.
begin()) {
139 if (I->isDebugValue())
143 if (!isUnpredicatedTerminator(I))
151 if (I->getOpcode() == SP::BA) {
155 TBB = I->getOperand(0).getMBB();
159 while (std::next(I) != MBB.
end())
169 UnCondBrIter = MBB.
end();
173 TBB = I->getOperand(0).getMBB();
177 unsigned Opcode = I->getOpcode();
178 if (Opcode != SP::BCOND && Opcode != SP::FBCOND)
185 if (AllowModify && UnCondBrIter != MBB.
end() &&
206 .
addMBB(UnCondBrIter->getOperand(0).getMBB()).addImm(BranchCode);
211 UnCondBrIter->eraseFromParent();
213 UnCondBrIter = MBB.
end();
218 TBB = I->getOperand(0).getMBB();
234 assert(TBB &&
"InsertBranch must not be told to insert a fallthrough");
235 assert((Cond.
size() == 1 || Cond.
size() == 0) &&
236 "Sparc branch conditions should have one component!");
239 assert(!FBB &&
"Unconditional branch with multiple successors!");
245 unsigned CC = Cond[0].getImm();
262 while (I != MBB.
begin()) {
265 if (I->isDebugValue())
268 if (I->getOpcode() != SP::BA
269 && I->getOpcode() != SP::BCOND
270 && I->getOpcode() != SP::FBCOND)
273 I->eraseFromParent();
282 unsigned DestReg,
unsigned SrcReg,
283 bool KillSrc)
const {
284 unsigned numSubRegs = 0;
286 const unsigned *subRegIdx =
nullptr;
288 const unsigned DFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd };
289 const unsigned QFP_DFP_SubRegsIdx[] = { SP::sub_even64, SP::sub_odd64 };
290 const unsigned QFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd,
291 SP::sub_odd64_then_sub_even,
292 SP::sub_odd64_then_sub_odd };
294 if (SP::IntRegsRegClass.
contains(DestReg, SrcReg))
297 else if (SP::FPRegsRegClass.
contains(DestReg, SrcReg))
298 BuildMI(MBB, I, DL,
get(SP::FMOVS), DestReg)
300 else if (SP::DFPRegsRegClass.
contains(DestReg, SrcReg)) {
301 if (Subtarget.
isV9()) {
302 BuildMI(MBB, I, DL,
get(SP::FMOVD), DestReg)
306 subRegIdx = DFP_FP_SubRegsIdx;
310 }
else if (SP::QFPRegsRegClass.
contains(DestReg, SrcReg)) {
311 if (Subtarget.
isV9()) {
313 BuildMI(MBB, I, DL,
get(SP::FMOVQ), DestReg)
317 subRegIdx = QFP_DFP_SubRegsIdx;
323 subRegIdx = QFP_FP_SubRegsIdx;
327 }
else if (SP::ASRRegsRegClass.
contains(DestReg) &&
328 SP::IntRegsRegClass.
contains(SrcReg)) {
329 BuildMI(MBB, I, DL,
get(SP::WRASRrr), DestReg)
332 }
else if (SP::IntRegsRegClass.
contains(DestReg) &&
333 SP::ASRRegsRegClass.
contains(SrcReg)) {
334 BuildMI(MBB, I, DL,
get(SP::RDASR), DestReg)
339 if (numSubRegs == 0 || subRegIdx ==
nullptr || movOpc == 0)
345 for (
unsigned i = 0; i != numSubRegs; ++i) {
346 unsigned Dst = TRI->
getSubReg(DestReg, subRegIdx[i]);
347 unsigned Src = TRI->
getSubReg(SrcReg, subRegIdx[i]);
348 assert(Dst && Src &&
"Bad sub-register");
360 unsigned SrcReg,
bool isKill,
int FI,
364 if (I != MBB.
end()) DL = I->getDebugLoc();
375 if (RC == &SP::I64RegsRegClass)
378 else if (RC == &SP::IntRegsRegClass)
381 else if (RC == &SP::FPRegsRegClass)
384 else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
387 else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
398 unsigned DestReg,
int FI,
402 if (I != MBB.
end()) DL = I->getDebugLoc();
412 if (RC == &SP::I64RegsRegClass)
415 else if (RC == &SP::IntRegsRegClass)
418 else if (RC == &SP::FPRegsRegClass)
421 else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
424 else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
437 if (GlobalBaseReg != 0)
446 Subtarget.
is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
451 BuildMI(FirstMBB, MBBI, dl,
get(SP::GETPCX), GlobalBaseReg);
void push_back(const T &Elt)
The memory access reads data.
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
The memory access writes data.
unsigned RemoveBranch(MachineBasicBlock &MBB) const override
unsigned getGlobalBaseReg(MachineFunction *MF) const
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, unsigned f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
getMachineMemOperand - Allocate a new MachineMemOperand.
static MachinePointerInfo getFixedStack(int FI, int64_t offset=0)
getFixedStack - Return a MachinePointerInfo record that refers to the the specified FrameIndex...
GlobalBaseReg - On Darwin, this node represents the result of the mflr at function entry...
void eraseFromParent()
eraseFromParent - This method unlinks 'this' from the containing function and deletes it...
MachineMemOperand - A description of a memory reference used in the backend.
unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const override
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot...
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
static bool IsIntegerCC(unsigned CC)
const MachineBasicBlock & front() const
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
size_t size() const
size - Get the array size.
const SparcRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
unsigned getKillRegState(bool B)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
bundle_iterator< MachineInstr, instr_iterator > iterator
DebugLoc findDebugLoc(instr_iterator MBBI)
findDebugLoc - find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE instructions...
const MachineOperand & getOperand(unsigned i) const
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot...
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
bool empty() const
empty - Check if the array is empty.
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
void setGlobalBaseReg(unsigned Reg)
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const MachineInstrBuilder & addFrameIndex(int Idx) const
void addRegisterDefined(unsigned Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
unsigned getGlobalBaseReg() const
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, DebugLoc DL) const override
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC)
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
SparcInstrInfo(SparcSubtarget &ST)
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
static MachineOperand CreateImm(int64_t Val)
bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
unsigned getReg() const
getReg - Returns the register number.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
bool addRegisterKilled(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
isLayoutSuccessor - Return true if the specified MBB will be emitted immediately after this block...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.