| adjustSchedDependency(SUnit *def, SUnit *use, SDep &dep) const | llvm::TargetSubtargetInfo | inlinevirtual |
| ANTIDEP_ALL enum value | llvm::TargetSubtargetInfo | |
| ANTIDEP_CRITICAL enum value | llvm::TargetSubtargetInfo | |
| ANTIDEP_NONE enum value | llvm::TargetSubtargetInfo | |
| AntiDepBreakMode enum name | llvm::TargetSubtargetInfo | |
| ApplyFeatureFlag(StringRef FS) | llvm::MCSubtargetInfo | |
| enableAtomicExpand() const | llvm::TargetSubtargetInfo | virtual |
| enableEarlyIfConversion() const | llvm::TargetSubtargetInfo | inlinevirtual |
| enableJoinGlobalCopies() const | llvm::TargetSubtargetInfo | virtual |
| enableMachineSchedDefaultSched() const | llvm::TargetSubtargetInfo | inlinevirtual |
| enableMachineScheduler() const | llvm::TargetSubtargetInfo | virtual |
| enablePostRAScheduler() const | llvm::TargetSubtargetInfo | virtual |
| enableRALocalReassignment(CodeGenOpt::Level OptLevel) const | llvm::TargetSubtargetInfo | virtual |
| enableSubRegLiveness() const | llvm::TargetSubtargetInfo | inlinevirtual |
| getAntiDepBreakMode() const | llvm::TargetSubtargetInfo | inlinevirtual |
| getCPU() const | llvm::MCSubtargetInfo | inline |
| getCriticalPathRCs(RegClassVector &CriticalPathRCs) const | llvm::TargetSubtargetInfo | inlinevirtual |
| getCustomPBQPConstraints() const | llvm::TargetSubtargetInfo | inlinevirtual |
| getFeatureBits() const | llvm::MCSubtargetInfo | inline |
| getFrameLowering() const | llvm::TargetSubtargetInfo | inlinevirtual |
| getInstrInfo() const | llvm::TargetSubtargetInfo | inlinevirtual |
| getInstrItineraryData() const | llvm::TargetSubtargetInfo | inlinevirtual |
| getInstrItineraryForCPU(StringRef CPU) const | llvm::MCSubtargetInfo | |
| getOptLevelToEnablePostRAScheduler() const | llvm::TargetSubtargetInfo | inlinevirtual |
| getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx, unsigned WriteResID) const | llvm::MCSubtargetInfo | inline |
| getRegisterInfo() const | llvm::TargetSubtargetInfo | inlinevirtual |
| getSchedModel() const | llvm::MCSubtargetInfo | inline |
| getSchedModelForCPU(StringRef CPU) const | llvm::MCSubtargetInfo | |
| getSelectionDAGInfo() const | llvm::TargetSubtargetInfo | inlinevirtual |
| getTargetLowering() const | llvm::TargetSubtargetInfo | inlinevirtual |
| getTargetTriple() const | llvm::MCSubtargetInfo | inline |
| getWriteLatencyEntry(const MCSchedClassDesc *SC, unsigned DefIdx) const | llvm::MCSubtargetInfo | inline |
| getWriteProcResBegin(const MCSchedClassDesc *SC) const | llvm::MCSubtargetInfo | inline |
| getWriteProcResEnd(const MCSchedClassDesc *SC) const | llvm::MCSubtargetInfo | inline |
| initInstrItins(InstrItineraryData &InstrItins) const | llvm::MCSubtargetInfo | |
| InitMCProcessorInfo(StringRef CPU, StringRef FS) | llvm::MCSubtargetInfo | protected |
| isCPUStringValid(StringRef CPU) const | llvm::MCSubtargetInfo | inline |
| MCSubtargetInfo(const MCSubtargetInfo &)=default | llvm::MCSubtargetInfo | |
| MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS, ArrayRef< SubtargetFeatureKV > PF, ArrayRef< SubtargetFeatureKV > PD, const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP) | llvm::MCSubtargetInfo | |
| overrideSchedPolicy(MachineSchedPolicy &Policy, MachineInstr *begin, MachineInstr *end, unsigned NumRegionInstrs) const | llvm::TargetSubtargetInfo | inlinevirtual |
| RegClassVector typedef | llvm::TargetSubtargetInfo | |
| resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const | llvm::TargetSubtargetInfo | inlinevirtual |
| setDefaultFeatures(StringRef CPU) | llvm::MCSubtargetInfo | |
| setFeatureBits(const FeatureBitset &FeatureBits_) | llvm::MCSubtargetInfo | inline |
| TargetSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS, ArrayRef< SubtargetFeatureKV > PF, ArrayRef< SubtargetFeatureKV > PD, const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP) | llvm::TargetSubtargetInfo | protected |
| ToggleFeature(uint64_t FB) | llvm::MCSubtargetInfo | |
| ToggleFeature(const FeatureBitset &FB) | llvm::MCSubtargetInfo | |
| ToggleFeature(StringRef FS) | llvm::MCSubtargetInfo | |
| useAA() const | llvm::TargetSubtargetInfo | virtual |
| ~TargetSubtargetInfo() | llvm::TargetSubtargetInfo | virtual |