LLVM  3.7.0
PPCSubtarget.cpp
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1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the PPC specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCSubtarget.h"
15 #include "PPC.h"
16 #include "PPCRegisterInfo.h"
17 #include "PPCTargetMachine.h"
20 #include "llvm/IR/Attributes.h"
21 #include "llvm/IR/Function.h"
22 #include "llvm/IR/GlobalValue.h"
26 #include <cstdlib>
27 
28 using namespace llvm;
29 
30 #define DEBUG_TYPE "ppc-subtarget"
31 
32 #define GET_SUBTARGETINFO_TARGET_DESC
33 #define GET_SUBTARGETINFO_CTOR
34 #include "PPCGenSubtargetInfo.inc"
35 
36 static cl::opt<bool> UseSubRegLiveness("ppc-track-subreg-liveness",
37 cl::desc("Enable subregister liveness tracking for PPC"), cl::Hidden);
38 
39 static cl::opt<bool> QPXStackUnaligned("qpx-stack-unaligned",
40  cl::desc("Even when QPX is enabled the stack is not 32-byte aligned"),
41  cl::Hidden);
42 
44  StringRef FS) {
45  initializeEnvironment();
46  initSubtargetFeatures(CPU, FS);
47  return *this;
48 }
49 
50 PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU,
51  const std::string &FS, const PPCTargetMachine &TM)
52  : PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT),
53  IsPPC64(TargetTriple.getArch() == Triple::ppc64 ||
54  TargetTriple.getArch() == Triple::ppc64le),
55  TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, FS)),
56  InstrInfo(*this), TLInfo(TM, *this) {}
57 
58 void PPCSubtarget::initializeEnvironment() {
59  StackAlignment = 16;
61  HasMFOCRF = false;
62  Has64BitSupport = false;
63  Use64BitRegs = false;
64  UseCRBits = false;
65  HasAltivec = false;
66  HasSPE = false;
67  HasQPX = false;
68  HasVSX = false;
69  HasP8Vector = false;
70  HasP8Altivec = false;
71  HasP8Crypto = false;
72  HasFCPSGN = false;
73  HasFSQRT = false;
74  HasFRE = false;
75  HasFRES = false;
76  HasFRSQRTE = false;
77  HasFRSQRTES = false;
78  HasRecipPrec = false;
79  HasSTFIWX = false;
80  HasLFIWAX = false;
81  HasFPRND = false;
82  HasFPCVT = false;
83  HasISEL = false;
84  HasPOPCNTD = false;
85  HasBPERMD = false;
86  HasExtDiv = false;
87  HasCMPB = false;
88  HasLDBRX = false;
89  IsBookE = false;
90  HasOnlyMSYNC = false;
91  IsPPC4xx = false;
92  IsPPC6xx = false;
93  IsE500 = false;
94  FeatureMFTB = false;
95  DeprecatedDST = false;
96  HasLazyResolverStubs = false;
97  HasICBT = false;
99  HasPartwordAtomics = false;
100  HasDirectMove = false;
101  IsQPXStackUnaligned = false;
102  HasHTM = false;
103 }
104 
105 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
106  // Determine default and user specified characteristics
107  std::string CPUName = CPU;
108  if (CPUName.empty()) {
109  // If cross-compiling with -march=ppc64le without -mcpu
111  CPUName = "ppc64le";
112  else
113  CPUName = "generic";
114  }
115 
116  // Initialize scheduling itinerary for the specified CPU.
117  InstrItins = getInstrItineraryForCPU(CPUName);
118 
119  // Parse features string.
120  ParseSubtargetFeatures(CPUName, FS);
121 
122  // If the user requested use of 64-bit regs, but the cpu selected doesn't
123  // support it, ignore.
124  if (IsPPC64 && has64BitSupport())
125  Use64BitRegs = true;
126 
127  // Set up darwin-specific properties.
128  if (isDarwin())
129  HasLazyResolverStubs = true;
130 
131  // QPX requires a 32-byte aligned stack. Note that we need to do this if
132  // we're compiling for a BG/Q system regardless of whether or not QPX
133  // is enabled because external functions will assume this alignment.
136 
137  // Determine endianness.
138  // FIXME: Part of the TargetMachine.
140 }
141 
142 /// hasLazyResolverStub - Return true if accesses to the specified global have
143 /// to go through a dyld lazy resolution stub. This means that an extra load
144 /// is required to get the address of the global.
146  // We never have stubs if HasLazyResolverStubs=false or if in static mode.
148  return false;
149  bool isDecl = GV->isDeclaration();
150  if (GV->hasHiddenVisibility() && !isDecl && !GV->hasCommonLinkage())
151  return false;
152  return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
153  GV->hasCommonLinkage() || isDecl;
154 }
155 
156 // Embedded cores need aggressive scheduling (and some others also benefit).
157 static bool needsAggressiveScheduling(unsigned Directive) {
158  switch (Directive) {
159  default: return false;
160  case PPC::DIR_440:
161  case PPC::DIR_A2:
162  case PPC::DIR_E500mc:
163  case PPC::DIR_E5500:
164  case PPC::DIR_PWR7:
165  case PPC::DIR_PWR8:
166  return true;
167  }
168 }
169 
171  // Enable MI scheduling for the embedded cores.
172  // FIXME: Enable this for all cores (some additional modeling
173  // may be necessary).
175 }
176 
177 // This overrides the PostRAScheduler bit in the SchedModel for each CPU.
178 bool PPCSubtarget::enablePostRAScheduler() const { return true; }
179 
180 PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const {
182 }
183 
184 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
185  CriticalPathRCs.clear();
186  CriticalPathRCs.push_back(isPPC64() ?
187  &PPC::G8RCRegClass : &PPC::GPRCRegClass);
188 }
189 
192  MachineInstr *end,
193  unsigned NumRegionInstrs) const {
195  Policy.OnlyTopDown = false;
196  Policy.OnlyBottomUp = false;
197  }
198 
199  // Spilling is generally expensive on all PPC cores, so always enable
200  // register-pressure tracking.
201  Policy.ShouldTrackPressure = true;
202 }
203 
204 bool PPCSubtarget::useAA() const {
205  // Use AA during code generation for the embedded cores.
207 }
208 
210  return UseSubRegLiveness;
211 }
212 
213 bool PPCSubtarget::isELFv2ABI() const { return TM.isELFv2ABI(); }
214 bool PPCSubtarget::isPPC64() const { return TM.isPPC64(); }
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:240
PPCSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const PPCTargetMachine &TM)
This constructor initializes the data members to match that of the specified triple.
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
bool IsQPXStackUnaligned
When targeting QPX running a stock PPC64 Linux kernel where the stack alignment has not been changed...
Definition: PPCSubtarget.h:126
bool useAA() const override
bool hasLazyResolverStub(const GlobalValue *GV) const
hasLazyResolverStub - Return true if accesses to the specified global have to go through a dyld lazy ...
unsigned StackAlignment
stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and ...
Definition: PPCSubtarget.h:73
const_iterator begin(StringRef path)
Get begin iterator over path.
Definition: Path.cpp:232
bool isDarwin() const
isDarwin - True if this is any darwin platform.
Definition: PPCSubtarget.h:261
bool hasCommonLinkage() const
Definition: GlobalValue.h:282
unsigned getPlatformStackAlignment() const
Definition: PPCSubtarget.h:250
This file contains the simple types necessary to represent the attributes associated with functions a...
unsigned DarwinDirective
Which cpu directive was used.
Definition: PPCSubtarget.h:79
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Definition: Triple.h:242
InstrItineraryData InstrItins
Selected instruction itineraries (one entry per itinerary class.)
Definition: PPCSubtarget.h:76
bool isELFv2ABI() const
void overrideSchedPolicy(MachineSchedPolicy &Policy, MachineInstr *begin, MachineInstr *end, unsigned NumRegionInstrs) const override
bool enableSubRegLiveness() const override
AntiDepBreakMode getAntiDepBreakMode() const override
PPCSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
initializeSubtargetDependencies - Initializes using a CPU and feature string so that we can use initi...
static bool needsAggressiveScheduling(unsigned Directive)
bool hasHiddenVisibility() const
Definition: GlobalValue.h:141
bool HasInvariantFunctionDescriptors
Definition: PPCSubtarget.h:118
static cl::opt< bool > QPXStackUnaligned("qpx-stack-unaligned", cl::desc("Even when QPX is enabled the stack is not 32-byte aligned"), cl::Hidden)
bool has64BitSupport() const
has64BitSupport - Return true if the selected CPU supports 64-bit instructions, regardless of whether...
Definition: PPCSubtarget.h:190
PPCTargetMachine - Common code between 32-bit and 64-bit PowerPC targets.
bool hasWeakLinkage() const
Definition: GlobalValue.h:268
const PPCTargetMachine & TM
Definition: PPCSubtarget.h:128
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
Definition: PPCSubtarget.h:69
bool enableMachineScheduler() const override
bool hasLinkOnceLinkage() const
Definition: GlobalValue.h:264
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.
Representation of each machine instruction.
Definition: MachineInstr.h:51
static cl::opt< bool > UseSubRegLiveness("ppc-track-subreg-liveness", cl::desc("Enable subregister liveness tracking for PPC"), cl::Hidden)
bool isDeclaration() const
Return true if the primary definition of this global value is outside of the current translation unit...
Definition: Globals.cpp:128
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:40
bool HasMFOCRF
Used by the ISel to turn in optimizations for POWER4-derived architectures.
Definition: PPCSubtarget.h:82
bool enablePostRAScheduler() const override