21 using namespace llvm::PatternMatch;
23 #define DEBUG_TYPE "instcombine"
31 assert(I &&
"No instruction?");
32 assert(OpNo < I->getNumOperands() &&
"Operand index too large");
36 if (!OpC)
return false;
40 if ((~Demanded & OpC->
getValue()) == 0)
55 bool InstCombiner::SimplifyDemandedInstructionBits(
Instruction &Inst) {
57 APInt KnownZero(BitWidth, 0), KnownOne(BitWidth, 0);
60 Value *V = SimplifyDemandedUseBits(&Inst, DemandedMask, KnownZero, KnownOne,
63 if (V == &Inst)
return true;
64 ReplaceInstUsesWith(Inst, V);
71 bool InstCombiner::SimplifyDemandedBits(
Use &U,
APInt DemandedMask,
75 Value *NewVal = SimplifyDemandedUseBits(U.
get(), DemandedMask, KnownZero,
76 KnownOne, Depth, UserI);
77 if (!NewVal)
return false;
104 Value *InstCombiner::SimplifyDemandedUseBits(
Value *V,
APInt DemandedMask,
108 assert(V !=
nullptr &&
"Null pointer of Value???");
109 assert(Depth <= 6 &&
"Limit Search Depth");
116 "Value *V, DemandedMask, KnownZero and KnownOne "
117 "must have same BitWidth");
120 KnownOne = CI->getValue() & DemandedMask;
121 KnownZero = ~KnownOne & DemandedMask;
124 if (isa<ConstantPointerNull>(V)) {
127 KnownZero = DemandedMask;
133 if (DemandedMask == 0) {
134 if (isa<UndefValue>(V))
142 APInt LHSKnownZero(BitWidth, 0), LHSKnownOne(BitWidth, 0);
143 APInt RHSKnownZero(BitWidth, 0), RHSKnownOne(BitWidth, 0);
169 if ((DemandedMask & ~LHSKnownZero & RHSKnownOne) ==
170 (DemandedMask & ~LHSKnownZero))
172 if ((DemandedMask & ~RHSKnownZero & LHSKnownOne) ==
173 (DemandedMask & ~RHSKnownZero))
177 if ((DemandedMask & (RHSKnownZero|LHSKnownZero)) == DemandedMask)
193 if ((DemandedMask & ~LHSKnownOne & RHSKnownZero) ==
194 (DemandedMask & ~LHSKnownOne))
196 if ((DemandedMask & ~RHSKnownOne & LHSKnownZero) ==
197 (DemandedMask & ~RHSKnownOne))
202 if ((DemandedMask & (~RHSKnownZero) & LHSKnownOne) ==
203 (DemandedMask & (~RHSKnownZero)))
205 if ((DemandedMask & (~LHSKnownZero) & RHSKnownOne) ==
206 (DemandedMask & (~LHSKnownZero)))
219 if ((DemandedMask & RHSKnownZero) == DemandedMask)
221 if ((DemandedMask & LHSKnownZero) == DemandedMask)
243 if (SimplifyDemandedBits(I->
getOperandUse(1), DemandedMask, RHSKnownZero,
244 RHSKnownOne, Depth + 1) ||
245 SimplifyDemandedBits(I->
getOperandUse(0), DemandedMask & ~RHSKnownZero,
246 LHSKnownZero, LHSKnownOne, Depth + 1))
248 assert(!(RHSKnownZero & RHSKnownOne) &&
"Bits known to be one AND zero?");
249 assert(!(LHSKnownZero & LHSKnownOne) &&
"Bits known to be one AND zero?");
253 if ((DemandedMask & ((RHSKnownZero | LHSKnownZero)|
254 (RHSKnownOne & LHSKnownOne))) == DemandedMask)
259 if ((DemandedMask & ~LHSKnownZero & RHSKnownOne) ==
260 (DemandedMask & ~LHSKnownZero))
262 if ((DemandedMask & ~RHSKnownZero & LHSKnownOne) ==
263 (DemandedMask & ~RHSKnownZero))
267 if ((DemandedMask & (RHSKnownZero|LHSKnownZero)) == DemandedMask)
275 KnownOne = RHSKnownOne & LHSKnownOne;
277 KnownZero = RHSKnownZero | LHSKnownZero;
281 if (SimplifyDemandedBits(I->
getOperandUse(1), DemandedMask, RHSKnownZero,
282 RHSKnownOne, Depth + 1) ||
283 SimplifyDemandedBits(I->
getOperandUse(0), DemandedMask & ~RHSKnownOne,
284 LHSKnownZero, LHSKnownOne, Depth + 1))
286 assert(!(RHSKnownZero & RHSKnownOne) &&
"Bits known to be one AND zero?");
287 assert(!(LHSKnownZero & LHSKnownOne) &&
"Bits known to be one AND zero?");
291 if ((DemandedMask & ((RHSKnownZero & LHSKnownZero)|
292 (RHSKnownOne | LHSKnownOne))) == DemandedMask)
297 if ((DemandedMask & ~LHSKnownOne & RHSKnownZero) ==
298 (DemandedMask & ~LHSKnownOne))
300 if ((DemandedMask & ~RHSKnownOne & LHSKnownZero) ==
301 (DemandedMask & ~RHSKnownOne))
306 if ((DemandedMask & (~RHSKnownZero) & LHSKnownOne) ==
307 (DemandedMask & (~RHSKnownZero)))
309 if ((DemandedMask & (~LHSKnownZero) & RHSKnownOne) ==
310 (DemandedMask & (~LHSKnownZero)))
318 KnownZero = RHSKnownZero & LHSKnownZero;
320 KnownOne = RHSKnownOne | LHSKnownOne;
323 if (SimplifyDemandedBits(I->
getOperandUse(1), DemandedMask, RHSKnownZero,
324 RHSKnownOne, Depth + 1) ||
325 SimplifyDemandedBits(I->
getOperandUse(0), DemandedMask, LHSKnownZero,
326 LHSKnownOne, Depth + 1))
328 assert(!(RHSKnownZero & RHSKnownOne) &&
"Bits known to be one AND zero?");
329 assert(!(LHSKnownZero & LHSKnownOne) &&
"Bits known to be one AND zero?");
332 APInt IKnownZero = (RHSKnownZero & LHSKnownZero) |
333 (RHSKnownOne & LHSKnownOne);
335 APInt IKnownOne = (RHSKnownZero & LHSKnownOne) |
336 (RHSKnownOne & LHSKnownZero);
340 if ((DemandedMask & (IKnownZero|IKnownOne)) == DemandedMask)
345 if ((DemandedMask & RHSKnownZero) == DemandedMask)
347 if ((DemandedMask & LHSKnownZero) == DemandedMask)
353 if ((DemandedMask & ~RHSKnownZero & ~LHSKnownZero) == 0) {
357 return InsertNewInstWith(Or, *I);
364 if ((DemandedMask & (RHSKnownZero|RHSKnownOne)) == DemandedMask) {
366 if ((RHSKnownOne & LHSKnownOne) == RHSKnownOne) {
368 ~RHSKnownOne & DemandedMask);
370 return InsertNewInstWith(And, *I);
386 isa<ConstantInt>(LHSInst->getOperand(1)) &&
387 (LHSKnownOne & RHSKnownOne & DemandedMask) != 0) {
388 ConstantInt *AndRHS = cast<ConstantInt>(LHSInst->getOperand(1));
390 APInt NewMask = ~(LHSKnownOne & RHSKnownOne & DemandedMask);
395 InsertNewInstWith(NewAnd, *I);
399 Instruction *NewXor = BinaryOperator::CreateXor(NewAnd, XorC);
400 return InsertNewInstWith(NewXor, *I);
404 KnownZero= (RHSKnownZero & LHSKnownZero) | (RHSKnownOne & LHSKnownOne);
406 KnownOne = (RHSKnownZero & LHSKnownOne) | (RHSKnownOne & LHSKnownZero);
416 if (SimplifyDemandedBits(I->
getOperandUse(2), DemandedMask, RHSKnownZero,
417 RHSKnownOne, Depth + 1) ||
418 SimplifyDemandedBits(I->
getOperandUse(1), DemandedMask, LHSKnownZero,
419 LHSKnownOne, Depth + 1))
421 assert(!(RHSKnownZero & RHSKnownOne) &&
"Bits known to be one AND zero?");
422 assert(!(LHSKnownZero & LHSKnownOne) &&
"Bits known to be one AND zero?");
430 KnownOne = RHSKnownOne & LHSKnownOne;
431 KnownZero = RHSKnownZero & LHSKnownZero;
433 case Instruction::Trunc: {
435 DemandedMask = DemandedMask.
zext(truncBf);
436 KnownZero = KnownZero.
zext(truncBf);
437 KnownOne = KnownOne.
zext(truncBf);
438 if (SimplifyDemandedBits(I->
getOperandUse(0), DemandedMask, KnownZero,
439 KnownOne, Depth + 1))
441 DemandedMask = DemandedMask.
trunc(BitWidth);
442 KnownZero = KnownZero.
trunc(BitWidth);
443 KnownOne = KnownOne.
trunc(BitWidth);
444 assert(!(KnownZero & KnownOne) &&
"Bits known to be one AND zero?");
447 case Instruction::BitCast:
454 if (DstVTy->getNumElements() != SrcVTy->getNumElements())
464 if (SimplifyDemandedBits(I->
getOperandUse(0), DemandedMask, KnownZero,
465 KnownOne, Depth + 1))
467 assert(!(KnownZero & KnownOne) &&
"Bits known to be one AND zero?");
469 case Instruction::ZExt: {
473 DemandedMask = DemandedMask.
trunc(SrcBitWidth);
474 KnownZero = KnownZero.
trunc(SrcBitWidth);
475 KnownOne = KnownOne.
trunc(SrcBitWidth);
476 if (SimplifyDemandedBits(I->
getOperandUse(0), DemandedMask, KnownZero,
477 KnownOne, Depth + 1))
479 DemandedMask = DemandedMask.
zext(BitWidth);
480 KnownZero = KnownZero.
zext(BitWidth);
481 KnownOne = KnownOne.
zext(BitWidth);
482 assert(!(KnownZero & KnownOne) &&
"Bits known to be one AND zero?");
487 case Instruction::SExt: {
491 APInt InputDemandedBits = DemandedMask &
497 if ((NewBits & DemandedMask) != 0)
498 InputDemandedBits.
setBit(SrcBitWidth-1);
500 InputDemandedBits = InputDemandedBits.
trunc(SrcBitWidth);
501 KnownZero = KnownZero.
trunc(SrcBitWidth);
502 KnownOne = KnownOne.
trunc(SrcBitWidth);
503 if (SimplifyDemandedBits(I->
getOperandUse(0), InputDemandedBits, KnownZero,
504 KnownOne, Depth + 1))
506 InputDemandedBits = InputDemandedBits.
zext(BitWidth);
507 KnownZero = KnownZero.
zext(BitWidth);
508 KnownOne = KnownOne.
zext(BitWidth);
509 assert(!(KnownZero & KnownOne) &&
"Bits known to be one AND zero?");
516 if (KnownZero[SrcBitWidth-1] || (NewBits & ~DemandedMask) == NewBits) {
519 return InsertNewInstWith(NewCast, *I);
520 }
else if (KnownOne[SrcBitWidth-1]) {
525 case Instruction::Add:
526 case Instruction::Sub: {
529 unsigned NLZ = DemandedMask.countLeadingZeros();
534 if (SimplifyDemandedBits(I->
getOperandUse(0), DemandedFromOps,
535 LHSKnownZero, LHSKnownOne, Depth + 1) ||
538 LHSKnownZero, LHSKnownOne, Depth + 1)) {
554 case Instruction::Shl:
560 Value *R = SimplifyShrShlDemandedBits(Shr, I, DemandedMask,
561 KnownZero, KnownOne);
567 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1);
568 APInt DemandedMaskIn(DemandedMask.lshr(ShiftAmt));
572 if (IOp->hasNoSignedWrap())
574 else if (IOp->hasNoUnsignedWrap())
577 if (SimplifyDemandedBits(I->
getOperandUse(0), DemandedMaskIn, KnownZero,
578 KnownOne, Depth + 1))
580 assert(!(KnownZero & KnownOne) &&
"Bits known to be one AND zero?");
581 KnownZero <<= ShiftAmt;
582 KnownOne <<= ShiftAmt;
588 case Instruction::LShr:
591 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1);
594 APInt DemandedMaskIn(DemandedMask.shl(ShiftAmt));
598 if (cast<LShrOperator>(I)->isExact())
601 if (SimplifyDemandedBits(I->
getOperandUse(0), DemandedMaskIn, KnownZero,
602 KnownOne, Depth + 1))
604 assert(!(KnownZero & KnownOne) &&
"Bits known to be one AND zero?");
610 KnownZero |= HighBits;
614 case Instruction::AShr:
619 if (DemandedMask == 1) {
623 return InsertNewInstWith(NewVal, *I);
628 if (DemandedMask.isSignBit())
632 uint32_t ShiftAmt = SA->getLimitedValue(BitWidth-1);
635 APInt DemandedMaskIn(DemandedMask.shl(ShiftAmt));
638 if (DemandedMask.countLeadingZeros() <= ShiftAmt)
639 DemandedMaskIn.
setBit(BitWidth-1);
643 if (cast<AShrOperator>(I)->isExact())
646 if (SimplifyDemandedBits(I->
getOperandUse(0), DemandedMaskIn, KnownZero,
647 KnownOne, Depth + 1))
649 assert(!(KnownZero & KnownOne) &&
"Bits known to be one AND zero?");
662 if (BitWidth <= ShiftAmt || KnownZero[BitWidth-ShiftAmt-1] ||
663 (HighBits & ~DemandedMask) == HighBits) {
667 NewVal->
setIsExact(cast<BinaryOperator>(I)->isExact());
668 return InsertNewInstWith(NewVal, *I);
669 }
else if ((KnownOne & SignBit) != 0) {
670 KnownOne |= HighBits;
674 case Instruction::SRem:
678 if (Rem->isAllOnesValue())
682 if (DemandedMask.ult(RA))
685 APInt LowBits = RA - 1;
687 if (SimplifyDemandedBits(I->
getOperandUse(0), Mask2, LHSKnownZero,
688 LHSKnownOne, Depth + 1))
692 KnownZero = LHSKnownZero & LowBits;
693 KnownOne = LHSKnownOne & LowBits;
697 if (LHSKnownZero[BitWidth-1] || ((LHSKnownZero & LowBits) == LowBits))
698 KnownZero |= ~LowBits;
702 if (LHSKnownOne[BitWidth-1] && ((LHSKnownOne & LowBits) != 0))
703 KnownOne |= ~LowBits;
705 assert(!(KnownZero & KnownOne) &&
"Bits known to be one AND zero?");
711 if (DemandedMask.isNegative() && KnownZero.isNonNegative()) {
712 APInt LHSKnownZero(BitWidth, 0), LHSKnownOne(BitWidth, 0);
716 if (LHSKnownZero.isNegative())
717 KnownZero.setBit(KnownZero.getBitWidth() - 1);
720 case Instruction::URem: {
721 APInt KnownZero2(BitWidth, 0), KnownOne2(BitWidth, 0);
723 if (SimplifyDemandedBits(I->
getOperandUse(0), AllOnes, KnownZero2,
724 KnownOne2, Depth + 1) ||
725 SimplifyDemandedBits(I->
getOperandUse(1), AllOnes, KnownZero2,
726 KnownOne2, Depth + 1))
729 unsigned Leaders = KnownZero2.countLeadingOnes();
730 Leaders = std::max(Leaders,
731 KnownZero2.countLeadingOnes());
737 switch (II->getIntrinsicID()) {
739 case Intrinsic::bswap: {
742 unsigned NLZ = DemandedMask.countLeadingZeros();
743 unsigned NTZ = DemandedMask.countTrailingZeros();
751 if (BitWidth-NLZ-NTZ == 8) {
752 unsigned ResultBit = NTZ;
753 unsigned InputBit = BitWidth-NTZ-8;
758 if (InputBit > ResultBit)
759 NewVal = BinaryOperator::CreateLShr(II->getArgOperand(0),
762 NewVal = BinaryOperator::CreateShl(II->getArgOperand(0),
765 return InsertNewInstWith(NewVal, *I);
771 case Intrinsic::x86_sse42_crc32_64_64:
782 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask)
807 const APInt &ShlOp1 = cast<ConstantInt>(Shl->
getOperand(1))->getValue();
808 const APInt &ShrOp1 = cast<ConstantInt>(Shr->
getOperand(1))->getValue();
809 if (!ShlOp1 || !ShrOp1)
815 if (ShlOp1.
uge(BitWidth) || ShrOp1.
uge(BitWidth))
823 KnownZero &= DemandedMask;
828 bool isLshr = (Shr->
getOpcode() == Instruction::LShr);
829 BitMask1 = isLshr ? (BitMask1.lshr(ShrAmt) << ShlAmt) :
830 (BitMask1.ashr(ShrAmt) << ShlAmt);
832 if (ShrAmt <= ShlAmt) {
833 BitMask2 <<= (ShlAmt - ShrAmt);
835 BitMask2 = isLshr ? BitMask2.lshr(ShrAmt - ShlAmt):
836 BitMask2.ashr(ShrAmt - ShlAmt);
840 if ((BitMask1 & DemandedMask) == (BitMask2 & DemandedMask)) {
841 if (ShrAmt == ShlAmt)
848 if (ShrAmt < ShlAmt) {
850 New = BinaryOperator::CreateShl(VarX, Amt);
856 New = isLshr ? BinaryOperator::CreateLShr(VarX, Amt) :
858 if (cast<BinaryOperator>(Shr)->isExact())
862 return InsertNewInstWith(New, *Shl);
876 Value *InstCombiner::SimplifyDemandedVectorElts(
Value *V,
APInt DemandedElts,
879 unsigned VWidth = cast<VectorType>(V->
getType())->getNumElements();
881 assert((DemandedElts & ~EltMask) == 0 &&
"Invalid DemandedElts!");
883 if (isa<UndefValue>(V)) {
889 if (DemandedElts == 0) {
897 if (
Constant *C = dyn_cast<Constant>(V)) {
903 Type *EltTy = cast<VectorType>(V->
getType())->getElementType();
907 for (
unsigned i = 0; i != VWidth; ++i) {
908 if (!DemandedElts[i]) {
914 Constant *Elt =
C->getAggregateElement(i);
915 if (!Elt)
return nullptr;
917 if (isa<UndefValue>(Elt)) {
927 return NewCV !=
C ? NewCV :
nullptr;
946 DemandedElts = EltMask;
950 if (!I)
return nullptr;
952 bool MadeChange =
false;
953 APInt UndefElts2(VWidth, 0);
958 case Instruction::InsertElement: {
965 TmpV = SimplifyDemandedVectorElts(I->
getOperand(0), DemandedElts,
966 UndefElts2, Depth + 1);
967 if (TmpV) { I->
setOperand(0, TmpV); MadeChange =
true; }
974 if (IdxNo >= VWidth || !DemandedElts[IdxNo]) {
981 APInt DemandedElts2 = DemandedElts;
983 TmpV = SimplifyDemandedVectorElts(I->
getOperand(0), DemandedElts2,
984 UndefElts, Depth + 1);
985 if (TmpV) { I->
setOperand(0, TmpV); MadeChange =
true; }
988 UndefElts.clearBit(IdxNo);
991 case Instruction::ShuffleVector: {
995 APInt LeftDemanded(LHSVWidth, 0), RightDemanded(LHSVWidth, 0);
996 for (
unsigned i = 0; i < VWidth; i++) {
997 if (DemandedElts[i]) {
999 if (MaskVal != -1u) {
1000 assert(MaskVal < LHSVWidth * 2 &&
1001 "shufflevector mask index out of range!");
1002 if (MaskVal < LHSVWidth)
1003 LeftDemanded.setBit(MaskVal);
1005 RightDemanded.setBit(MaskVal - LHSVWidth);
1010 APInt UndefElts4(LHSVWidth, 0);
1011 TmpV = SimplifyDemandedVectorElts(I->
getOperand(0), LeftDemanded,
1012 UndefElts4, Depth + 1);
1013 if (TmpV) { I->
setOperand(0, TmpV); MadeChange =
true; }
1015 APInt UndefElts3(LHSVWidth, 0);
1016 TmpV = SimplifyDemandedVectorElts(I->
getOperand(1), RightDemanded,
1017 UndefElts3, Depth + 1);
1018 if (TmpV) { I->
setOperand(1, TmpV); MadeChange =
true; }
1020 bool NewUndefElts =
false;
1021 for (
unsigned i = 0; i < VWidth; i++) {
1023 if (MaskVal == -1u) {
1024 UndefElts.setBit(i);
1025 }
else if (!DemandedElts[i]) {
1026 NewUndefElts =
true;
1027 UndefElts.setBit(i);
1028 }
else if (MaskVal < LHSVWidth) {
1029 if (UndefElts4[MaskVal]) {
1030 NewUndefElts =
true;
1031 UndefElts.setBit(i);
1034 if (UndefElts3[MaskVal - LHSVWidth]) {
1035 NewUndefElts =
true;
1036 UndefElts.setBit(i);
1044 for (
unsigned i = 0; i < VWidth; ++i) {
1057 APInt LeftDemanded(DemandedElts), RightDemanded(DemandedElts);
1059 for (
unsigned i = 0; i < VWidth; i++) {
1060 if (CV->getAggregateElement(i)->isNullValue())
1061 LeftDemanded.clearBit(i);
1063 RightDemanded.clearBit(i);
1067 TmpV = SimplifyDemandedVectorElts(I->
getOperand(1), LeftDemanded, UndefElts,
1069 if (TmpV) { I->
setOperand(1, TmpV); MadeChange =
true; }
1071 TmpV = SimplifyDemandedVectorElts(I->
getOperand(2), RightDemanded,
1072 UndefElts2, Depth + 1);
1073 if (TmpV) { I->
setOperand(2, TmpV); MadeChange =
true; }
1076 UndefElts &= UndefElts2;
1079 case Instruction::BitCast: {
1084 APInt InputDemandedElts(InVWidth, 0);
1087 if (VWidth == InVWidth) {
1091 InputDemandedElts = DemandedElts;
1092 }
else if (VWidth > InVWidth) {
1099 Ratio = VWidth/InVWidth;
1100 for (
unsigned OutIdx = 0; OutIdx != VWidth; ++OutIdx) {
1101 if (DemandedElts[OutIdx])
1102 InputDemandedElts.setBit(OutIdx/Ratio);
1111 Ratio = InVWidth/VWidth;
1112 for (
unsigned InIdx = 0; InIdx != InVWidth; ++InIdx)
1113 if (DemandedElts[InIdx/Ratio])
1114 InputDemandedElts.setBit(InIdx);
1118 TmpV = SimplifyDemandedVectorElts(I->
getOperand(0), InputDemandedElts,
1119 UndefElts2, Depth + 1);
1125 UndefElts = UndefElts2;
1126 if (VWidth > InVWidth) {
1131 for (
unsigned OutIdx = 0; OutIdx != VWidth; ++OutIdx)
1132 if (UndefElts2[OutIdx/Ratio])
1133 UndefElts.setBit(OutIdx);
1134 }
else if (VWidth < InVWidth) {
1139 UndefElts = ~0ULL >> (64-VWidth);
1140 for (
unsigned InIdx = 0; InIdx != InVWidth; ++InIdx)
1141 if (!UndefElts2[InIdx])
1142 UndefElts.clearBit(InIdx/Ratio);
1149 case Instruction::Add:
1150 case Instruction::Sub:
1151 case Instruction::Mul:
1153 TmpV = SimplifyDemandedVectorElts(I->
getOperand(0), DemandedElts, UndefElts,
1155 if (TmpV) { I->
setOperand(0, TmpV); MadeChange =
true; }
1156 TmpV = SimplifyDemandedVectorElts(I->
getOperand(1), DemandedElts,
1157 UndefElts2, Depth + 1);
1158 if (TmpV) { I->
setOperand(1, TmpV); MadeChange =
true; }
1162 UndefElts &= UndefElts2;
1164 case Instruction::FPTrunc:
1165 case Instruction::FPExt:
1166 TmpV = SimplifyDemandedVectorElts(I->
getOperand(0), DemandedElts, UndefElts,
1168 if (TmpV) { I->
setOperand(0, TmpV); MadeChange =
true; }
1179 case Intrinsic::x86_sse_sub_ss:
1180 case Intrinsic::x86_sse_mul_ss:
1181 case Intrinsic::x86_sse_min_ss:
1182 case Intrinsic::x86_sse_max_ss:
1183 case Intrinsic::x86_sse2_sub_sd:
1184 case Intrinsic::x86_sse2_mul_sd:
1185 case Intrinsic::x86_sse2_min_sd:
1186 case Intrinsic::x86_sse2_max_sd:
1187 TmpV = SimplifyDemandedVectorElts(II->
getArgOperand(0), DemandedElts,
1188 UndefElts, Depth + 1);
1189 if (TmpV) { II->
setArgOperand(0, TmpV); MadeChange =
true; }
1190 TmpV = SimplifyDemandedVectorElts(II->
getArgOperand(1), DemandedElts,
1191 UndefElts2, Depth + 1);
1192 if (TmpV) { II->
setArgOperand(1, TmpV); MadeChange =
true; }
1196 if (DemandedElts == 1) {
1199 case Intrinsic::x86_sse_sub_ss:
1200 case Intrinsic::x86_sse_mul_ss:
1201 case Intrinsic::x86_sse2_sub_sd:
1202 case Intrinsic::x86_sse2_mul_sd:
1214 case Intrinsic::x86_sse_sub_ss:
1215 case Intrinsic::x86_sse2_sub_sd:
1216 TmpV = InsertNewInstWith(BinaryOperator::CreateFSub(LHS, RHS,
1219 case Intrinsic::x86_sse_mul_ss:
1220 case Intrinsic::x86_sse2_mul_sd:
1221 TmpV = InsertNewInstWith(BinaryOperator::CreateFMul(LHS, RHS,
1231 InsertNewInstWith(New, *II);
1238 UndefElts &= UndefElts2;
1244 return MadeChange ? I :
nullptr;
void clearAllBits()
Set every bit to 0.
static int getMaskValue(Constant *Mask, unsigned i)
getMaskValue - Return the index from the shuffle mask for the specified output result.
const Use & getOperandUse(unsigned i) const
void push_back(const T &Elt)
IntegerType * getType() const
getType - Specialize the getType() method to always return an IntegerType, which reduces the amount o...
class_match< Value > m_Value()
Match an arbitrary value and ignore it.
void setHasNoSignedWrap(bool b=true)
Set or clear the nsw flag on this instruction, which must be an operator which supports this flag...
static APInt getSignBit(unsigned BitWidth)
Get the SignBit for a specific bit width.
APInt LLVM_ATTRIBUTE_UNUSED_RESULT abs() const
Get the absolute value;.
static APInt getAllOnesValue(unsigned numBits)
Get the all-ones value.
uint64_t getZExtValue() const
Get zero extended value.
Intrinsic::ID getIntrinsicID() const
getIntrinsicID - Return the intrinsic ID of this intrinsic.
void setBit(unsigned bitPosition)
Set a given bit to 1.
This class represents zero extension of integer types.
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Get a value with low bits set.
void computeKnownBits(Value *V, APInt &KnownZero, APInt &KnownOne, const DataLayout &DL, unsigned Depth=0, AssumptionCache *AC=nullptr, const Instruction *CxtI=nullptr, const DominatorTree *DT=nullptr)
Determine which bits of V are known to be either zero or one and return them in the KnownZero/KnownOn...
ShuffleVectorInst - This instruction constructs a fixed permutation of two input vectors.
static bool ShrinkDemandedConstant(Instruction *I, unsigned OpNo, APInt Demanded)
ShrinkDemandedConstant - Check to see if the specified operand of the specified instruction is a cons...
APInt LLVM_ATTRIBUTE_UNUSED_RESULT zextOrTrunc(unsigned width) const
Zero extend or truncate to width.
static Constant * getNullValue(Type *Ty)
StringRef getName() const
Return a constant reference to the value's name.
SelectPatternFlavor matchSelectPattern(Value *V, Value *&LHS, Value *&RHS, Instruction::CastOps *CastOp=nullptr)
Pattern match integer [SU]MIN, [SU]MAX and ABS idioms, returning the kind and providing the out param...
bool match(Val *V, const Pattern &P)
static InsertElementInst * Create(Value *Vec, Value *NewElt, Value *Idx, const Twine &NameStr="", Instruction *InsertBefore=nullptr)
This is the base class for all instructions that perform data casts.
const APInt & getValue() const
Return the constant as an APInt value reference.
BinOp2_match< LHS, RHS, Instruction::LShr, Instruction::AShr > m_Shr(const LHS &L, const RHS &R)
Matches LShr or AShr.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
A Use represents the edge between a Value definition and its users.
void setHasNoUnsignedWrap(bool b=true)
Set or clear the nsw flag on this instruction, which must be an operator which supports this flag...
static Constant * get(ArrayRef< Constant * > V)
APInt lshr(const APInt &LHS, unsigned shiftAmt)
Logical right-shift function.
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
class_match< ConstantInt > m_ConstantInt()
Match an arbitrary ConstantInt and ignore it.
unsigned getNumElements() const
Return the number of elements in the Vector type.
void takeName(Value *V)
Transfer the name from V to this value.
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Get a value with high bits set.
bool isIntOrIntVectorTy() const
isIntOrIntVectorTy - Return true if this is an integer type or a vector of integer types...
APInt LLVM_ATTRIBUTE_UNUSED_RESULT trunc(unsigned width) const
Truncate to new width.
The instances of the Type class are immutable: once they are created, they are never changed...
bool isVectorTy() const
isVectorTy - True if this is an instance of VectorType.
This is an important base class in LLVM.
APInt Or(const APInt &LHS, const APInt &RHS)
Bitwise OR function for APInt.
APInt Xor(const APInt &LHS, const APInt &RHS)
Bitwise XOR function for APInt.
unsigned getBitWidth() const
Return the number of bits in the APInt.
bool uge(const APInt &RHS) const
Unsigned greater or equal comparison.
User * getUser() const
Returns the User that contains this Use.
Value * getOperand(unsigned i) const
ConstantVector - Constant Vector Declarations.
static UndefValue * get(Type *T)
get() - Static factory methods - Return an 'undef' object of the specified type.
LLVMContext & getContext() const
All values hold a context through their type.
bool hasNoSignedWrap() const
Determine whether the no signed wrap flag is set.
bool isPowerOf2() const
Check if this APInt's value is a power of two greater than zero.
static Constant * getIntegerValue(Type *Ty, const APInt &V)
getIntegerValue - Return the value for an integer or pointer constant, or a vector thereof...
void setIsExact(bool b=true)
Set or clear the exact flag on this instruction, which must be an operator which supports this flag...
unsigned getIntegerBitWidth() const
This is the shared class of boolean and integer constants.
unsigned getScalarSizeInBits() const LLVM_READONLY
getScalarSizeInBits - If this is a vector type, return the getPrimitiveSizeInBits value for the eleme...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Type * getType() const
All values are typed, get the type of this value.
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
void setOperand(unsigned i, Value *Val)
Value * getArgOperand(unsigned i) const
getArgOperand/setArgOperand - Return/set the i-th call argument.
VectorType - Class to represent vector types.
Class for arbitrary precision integers.
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
APInt And(const APInt &LHS, const APInt &RHS)
Bitwise AND function for APInt.
static APInt getBitsSet(unsigned numBits, unsigned loBit, unsigned hiBit)
Get a value with a block of bits set.
bool isAllOnesValue() const
Determine if all bits are set.
static IntegerType * getInt32Ty(LLVMContext &C)
void clearBit(unsigned bitPosition)
Set a given bit to 0.
bool hasOneUse() const
Return true if there is exactly one user of this value.
void setArgOperand(unsigned i, Value *v)
LLVM Value Representation.
bool hasNoUnsignedWrap() const
Determine whether the no unsigned wrap flag is set.
This file provides internal interfaces used to implement the InstCombine.
unsigned getOpcode() const
getOpcode() returns a member of one of the enums like Instruction::Add.
C - The default llvm calling convention, compatible with C.
APInt LLVM_ATTRIBUTE_UNUSED_RESULT zext(unsigned width) const
Zero extend to a new width.
IntrinsicInst - A useful wrapper class for inspecting calls to intrinsic functions.