28 #define GET_INSTRINFO_CTOR_DTOR
29 #include "AMDGPUGenDFAPacketizer.inc"
49 unsigned DestReg,
unsigned SrcReg,
51 unsigned VectorComponents = 0;
52 if ((AMDGPU::R600_Reg128RegClass.
contains(DestReg) ||
53 AMDGPU::R600_Reg128VerticalRegClass.
contains(DestReg)) &&
54 (AMDGPU::R600_Reg128RegClass.
contains(SrcReg) ||
55 AMDGPU::R600_Reg128VerticalRegClass.
contains(SrcReg))) {
57 }
else if((AMDGPU::R600_Reg64RegClass.
contains(DestReg) ||
58 AMDGPU::R600_Reg64VerticalRegClass.
contains(DestReg)) &&
59 (AMDGPU::R600_Reg64RegClass.
contains(SrcReg) ||
60 AMDGPU::R600_Reg64VerticalRegClass.
contains(SrcReg))) {
64 if (VectorComponents > 0) {
65 for (
unsigned I = 0;
I < VectorComponents;
I++) {
68 RI.getSubReg(DestReg, SubRegIndex),
69 RI.getSubReg(SrcReg, SubRegIndex))
85 E = MBBI->operands_end();
I != E; ++
I) {
97 default:
return false;
99 case AMDGPU::MOV_IMM_F32:
100 case AMDGPU::MOV_IMM_I32:
110 default:
return false;
122 default:
return false;
123 case AMDGPU::CUBE_r600_pseudo:
124 case AMDGPU::CUBE_r600_real:
125 case AMDGPU::CUBE_eg_pseudo:
126 case AMDGPU::CUBE_eg_real:
132 unsigned TargetFlags =
get(Opcode).TSFlags;
138 unsigned TargetFlags =
get(Opcode).TSFlags;
146 unsigned TargetFlags =
get(Opcode).TSFlags;
168 case AMDGPU::INTERP_PAIR_XY:
169 case AMDGPU::INTERP_PAIR_ZW:
170 case AMDGPU::INTERP_VEC_LOAD:
182 return (
get(Opcode).getSchedClass() == AMDGPU::Sched::TransALU);
190 return (
get(Opcode).getSchedClass() == AMDGPU::Sched::VecALU);
227 case AMDGPU::GROUP_BARRIER:
248 if (!
I->isReg() || !
I->isUse() ||
252 if (AMDGPU::R600_LDS_SRC_REGRegClass.
contains(
I->getReg()))
259 static const unsigned OpTable[] = {
260 AMDGPU::OpName::src0,
261 AMDGPU::OpName::src1,
270 static const unsigned SrcSelTable[][2] = {
271 {AMDGPU::OpName::src0, AMDGPU::OpName::src0_sel},
272 {AMDGPU::OpName::src1, AMDGPU::OpName::src1_sel},
273 {AMDGPU::OpName::src2, AMDGPU::OpName::src2_sel},
274 {AMDGPU::OpName::src0_X, AMDGPU::OpName::src0_sel_X},
275 {AMDGPU::OpName::src0_Y, AMDGPU::OpName::src0_sel_Y},
276 {AMDGPU::OpName::src0_Z, AMDGPU::OpName::src0_sel_Z},
277 {AMDGPU::OpName::src0_W, AMDGPU::OpName::src0_sel_W},
278 {AMDGPU::OpName::src1_X, AMDGPU::OpName::src1_sel_X},
279 {AMDGPU::OpName::src1_Y, AMDGPU::OpName::src1_sel_Y},
280 {AMDGPU::OpName::src1_Z, AMDGPU::OpName::src1_sel_Z},
281 {AMDGPU::OpName::src1_W, AMDGPU::OpName::src1_sel_W}
284 for (
const auto &Row : SrcSelTable) {
297 static const unsigned OpTable[8][2] = {
298 {AMDGPU::OpName::src0_X, AMDGPU::OpName::src0_sel_X},
299 {AMDGPU::OpName::src0_Y, AMDGPU::OpName::src0_sel_Y},
300 {AMDGPU::OpName::src0_Z, AMDGPU::OpName::src0_sel_Z},
301 {AMDGPU::OpName::src0_W, AMDGPU::OpName::src0_sel_W},
302 {AMDGPU::OpName::src1_X, AMDGPU::OpName::src1_sel_X},
303 {AMDGPU::OpName::src1_Y, AMDGPU::OpName::src1_sel_Y},
304 {AMDGPU::OpName::src1_Z, AMDGPU::OpName::src1_sel_Z},
305 {AMDGPU::OpName::src1_W, AMDGPU::OpName::src1_sel_W},
308 for (
unsigned j = 0; j < 8; j++) {
312 if (Reg == AMDGPU::ALU_CONST) {
315 Result.
push_back(std::pair<MachineOperand *, int64_t>(&MO, Sel));
323 static const unsigned OpTable[3][2] = {
324 {AMDGPU::OpName::src0, AMDGPU::OpName::src0_sel},
325 {AMDGPU::OpName::src1, AMDGPU::OpName::src1_sel},
326 {AMDGPU::OpName::src2, AMDGPU::OpName::src2_sel},
329 for (
unsigned j = 0; j < 3; j++) {
335 if (Reg == AMDGPU::ALU_CONST) {
338 Result.
push_back(std::pair<MachineOperand *, int64_t>(&MO, Sel));
341 if (Reg == AMDGPU::ALU_LITERAL_X) {
344 Result.
push_back(std::pair<MachineOperand *, int64_t>(&MO, Imm));
347 Result.
push_back(std::pair<MachineOperand *, int64_t>(&MO, 0));
352 std::vector<std::pair<int, unsigned> >
355 unsigned &ConstCount)
const {
358 const std::pair<int, unsigned> DummyPair(-1, 0);
359 std::vector<std::pair<int, unsigned> > Result;
361 for (
unsigned n = Srcs.
size(); i < n; ++i) {
362 unsigned Reg = Srcs[i].first->getReg();
363 unsigned Index = RI.getEncodingValue(Reg) & 0xff;
364 if (Reg == AMDGPU::OQAP) {
365 Result.push_back(std::pair<int, unsigned>(Index, 0));
367 if (PV.
find(Reg) != PV.
end()) {
369 Result.push_back(std::pair<int, unsigned>(255, 0));
374 Result.push_back(DummyPair);
378 Result.push_back(std::pair<int, unsigned>(Index, Chan));
381 Result.push_back(DummyPair);
385 static std::vector<std::pair<int, unsigned> >
386 Swizzle(std::vector<std::pair<int, unsigned> > Src,
388 if (Src[0] == Src[1])
418 unsigned Cycles[3] = { 2, 1, 0};
422 unsigned Cycles[3] = { 1, 2, 2};
426 unsigned Cycles[3] = { 2, 1, 2};
430 unsigned Cycles[3] = { 2, 2, 1};
443 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
444 const std::vector<R600InstrInfo::BankSwizzle> &Swz,
445 const std::vector<std::pair<int, unsigned> > &TransSrcs,
448 memset(Vector, -1,
sizeof(Vector));
449 for (
unsigned i = 0, e = IGSrcs.size(); i < e; i++) {
450 const std::vector<std::pair<int, unsigned> > &Srcs =
452 for (
unsigned j = 0; j < 3; j++) {
453 const std::pair<int, unsigned> &Src = Srcs[j];
454 if (Src.first < 0 || Src.first == 255)
456 if (Src.first ==
GET_REG_INDEX(RI.getEncodingValue(AMDGPU::OQAP))) {
466 if (Vector[Src.second][j] < 0)
467 Vector[Src.second][j] = Src.first;
468 if (Vector[Src.second][j] != Src.first)
473 for (
unsigned i = 0, e = TransSrcs.size(); i < e; ++i) {
474 const std::pair<int, unsigned> &Src = TransSrcs[i];
478 if (Src.first == 255)
480 if (Vector[Src.second][Cycle] < 0)
481 Vector[Src.second][Cycle] = Src.first;
482 if (Vector[Src.second][Cycle] != Src.first)
483 return IGSrcs.size() - 1;
485 return IGSrcs.size();
493 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
495 assert(Idx < SwzCandidate.size());
499 for (
unsigned i = ResetIdx + 1, e = SwzCandidate.size(); i < e; i++) {
504 int NextSwizzle = SwzCandidate[ResetIdx] + 1;
512 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
513 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
514 const std::vector<std::pair<int, unsigned> > &TransSrcs,
516 unsigned ValidUpTo = 0;
518 ValidUpTo =
isLegalUpTo(IGSrcs, SwzCandidate, TransSrcs, TransSwz);
519 if (ValidUpTo == IGSrcs.size())
529 const std::vector<std::pair<int, unsigned> > &TransOps,
530 unsigned ConstCount) {
534 for (
unsigned i = 0, e = TransOps.size(); i < e; ++i) {
535 const std::pair<int, unsigned> &Src = TransOps[i];
539 if (ConstCount > 0 && Cycle == 0)
541 if (ConstCount > 1 && Cycle == 1)
550 std::vector<BankSwizzle> &ValidSwizzle,
555 std::vector<std::vector<std::pair<int, unsigned> > > IGSrcs;
556 ValidSwizzle.clear();
559 for (
unsigned i = 0, e = IG.size(); i < e; ++i) {
560 IGSrcs.push_back(ExtractSrcs(IG[i], PV, ConstCount));
562 AMDGPU::OpName::bank_swizzle);
564 IG[i]->getOperand(Op).getImm());
566 std::vector<std::pair<int, unsigned> > TransOps;
570 TransOps = std::move(IGSrcs.back());
572 ValidSwizzle.pop_back();
580 for (
unsigned i = 0; i < 4; i++) {
581 TransBS = TransSwz[i];
587 ValidSwizzle.push_back(TransBS);
599 assert (Consts.size() <= 12 &&
"Too many operands in instructions group");
600 unsigned Pair1 = 0, Pair2 = 0;
601 for (
unsigned i = 0, n = Consts.size(); i < n; ++i) {
602 unsigned ReadConstHalf = Consts[i] & 2;
603 unsigned ReadConstIndex = Consts[i] & (~3);
604 unsigned ReadHalfConst = ReadConstIndex | ReadConstHalf;
606 Pair1 = ReadHalfConst;
609 if (Pair1 == ReadHalfConst)
612 Pair2 = ReadHalfConst;
615 if (Pair2 != ReadHalfConst)
624 std::vector<unsigned> Consts;
626 for (
unsigned i = 0, n = MIs.size(); i < n; i++) {
633 for (
unsigned j = 0, e = Srcs.
size(); j < e; j++) {
634 std::pair<MachineOperand *, unsigned> Src = Srcs[j];
635 if (Src.first->getReg() == AMDGPU::ALU_LITERAL_X)
636 Literals.
insert(Src.second);
637 if (Literals.
size() > 4)
639 if (Src.first->getReg() == AMDGPU::ALU_CONST)
640 Consts.push_back(Src.second);
641 if (AMDGPU::R600_KC0RegClass.
contains(Src.first->getReg()) ||
642 AMDGPU::R600_KC1RegClass.
contains(Src.first->getReg())) {
643 unsigned Index = RI.getEncodingValue(Src.first->getReg()) & 0xff;
645 Consts.push_back((Index << 2) | Chan);
655 return static_cast<const AMDGPUSubtarget &
>(STI).createDFAPacketizer(II);
671 while (I != MBB.
begin()) {
683 return Opcode == AMDGPU::JUMP || Opcode == AMDGPU::JUMP_COND;
687 return Opcode == AMDGPU::BRANCH || Opcode == AMDGPU::BRANCH_COND_i32 ||
688 Opcode == AMDGPU::BRANCH_COND_f32;
696 bool AllowModify)
const {
708 if (!
isJump(static_cast<MachineInstr *>(I)->getOpcode())) {
713 while (I != MBB.
begin() && std::prev(I)->getOpcode() == AMDGPU::JUMP) {
716 I->removeFromParent();
722 unsigned LastOpc = LastInst->
getOpcode();
723 if (I == MBB.
begin() ||
724 !
isJump(static_cast<MachineInstr *>(--I)->getOpcode())) {
725 if (LastOpc == AMDGPU::JUMP) {
728 }
else if (LastOpc == AMDGPU::JUMP_COND) {
744 unsigned SecondLastOpc = SecondLastInst->
getOpcode();
747 if (SecondLastOpc == AMDGPU::JUMP_COND && LastOpc == AMDGPU::JUMP) {
768 if (It->getOpcode() == AMDGPU::CF_ALU ||
769 It->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE)
770 return std::prev(It.base());
781 assert(TBB &&
"InsertBranch must not be told to insert a fallthrough");
789 assert(PredSet &&
"No previous predicate !");
793 BuildMI(&MBB, DL,
get(AMDGPU::JUMP_COND))
797 if (CfAlu == MBB.
end())
799 assert (CfAlu->getOpcode() == AMDGPU::CF_ALU);
800 CfAlu->setDesc(
get(AMDGPU::CF_ALU_PUSH_BEFORE));
805 assert(PredSet &&
"No previous predicate !");
808 BuildMI(&MBB, DL,
get(AMDGPU::JUMP_COND))
813 if (CfAlu == MBB.
end())
815 assert (CfAlu->getOpcode() == AMDGPU::CF_ALU);
816 CfAlu->setDesc(
get(AMDGPU::CF_ALU_PUSH_BEFORE));
829 if (I == MBB.
begin()) {
833 switch (I->getOpcode()) {
836 case AMDGPU::JUMP_COND: {
839 I->eraseFromParent();
841 if (CfAlu == MBB.
end())
843 assert (CfAlu->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE);
844 CfAlu->setDesc(
get(AMDGPU::CF_ALU));
848 I->eraseFromParent();
853 if (I == MBB.
begin()) {
857 switch (I->getOpcode()) {
861 case AMDGPU::JUMP_COND: {
864 I->eraseFromParent();
866 if (CfAlu == MBB.
end())
868 assert (CfAlu->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE);
869 CfAlu->setDesc(
get(AMDGPU::CF_ALU));
873 I->eraseFromParent();
887 default:
return false;
888 case AMDGPU::PRED_SEL_ONE:
889 case AMDGPU::PRED_SEL_ZERO:
890 case AMDGPU::PREDICATE_BIT:
904 }
else if (MI->
getOpcode() == AMDGPU::CF_ALU) {
924 unsigned ExtraPredCycles,
932 unsigned ExtraTCycles,
935 unsigned ExtraFCycles,
977 case AMDGPU::PRED_SEL_ZERO:
978 MO2.
setReg(AMDGPU::PRED_SEL_ONE);
980 case AMDGPU::PRED_SEL_ONE:
981 MO2.
setReg(AMDGPU::PRED_SEL_ZERO);
991 std::vector<MachineOperand> &Pred)
const {
1008 if (MI->
getOpcode() == AMDGPU::CF_ALU) {
1044 unsigned *PredCost)
const {
1052 switch(MI->getOpcode()) {
1054 case AMDGPU::R600_EXTRACT_ELT_V2:
1055 case AMDGPU::R600_EXTRACT_ELT_V4:
1056 buildIndirectRead(MI->getParent(),
MI, MI->getOperand(0).getReg(),
1058 MI->getOperand(2).getReg(),
1061 case AMDGPU::R600_INSERT_ELT_V2:
1062 case AMDGPU::R600_INSERT_ELT_V4:
1063 buildIndirectWrite(MI->getParent(),
MI, MI->getOperand(2).getReg(),
1065 MI->getOperand(3).getReg(),
1069 MI->eraseFromParent();
1085 unsigned SuperReg = AMDGPU::R600_Reg128RegClass.getRegister(Index);
1086 Reserved.
set(SuperReg);
1087 for (
unsigned Chan = 0; Chan < StackWidth; ++Chan) {
1088 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister((4 * Index) + Chan);
1095 unsigned Channel)
const {
1097 assert(Channel == 0);
1102 return &AMDGPU::R600_TReg32_XRegClass;
1107 unsigned ValueReg,
unsigned Address,
1108 unsigned OffsetReg)
const {
1109 return buildIndirectWrite(MBB, I, ValueReg, Address, OffsetReg, 0);
1114 unsigned ValueReg,
unsigned Address,
1116 unsigned AddrChan)
const {
1120 case 0: AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address);
break;
1121 case 1: AddrReg = AMDGPU::R600_Addr_YRegClass.getRegister(Address);
break;
1122 case 2: AddrReg = AMDGPU::R600_Addr_ZRegClass.getRegister(Address);
break;
1123 case 3: AddrReg = AMDGPU::R600_Addr_WRegClass.getRegister(Address);
break;
1126 AMDGPU::AR_X, OffsetReg);
1139 unsigned ValueReg,
unsigned Address,
1140 unsigned OffsetReg)
const {
1141 return buildIndirectRead(MBB, I, ValueReg, Address, OffsetReg, 0);
1146 unsigned ValueReg,
unsigned Address,
1148 unsigned AddrChan)
const {
1152 case 0: AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address);
break;
1153 case 1: AddrReg = AMDGPU::R600_Addr_YRegClass.getRegister(Address);
break;
1154 case 2: AddrReg = AMDGPU::R600_Addr_ZRegClass.getRegister(Address);
break;
1155 case 3: AddrReg = AMDGPU::R600_Addr_WRegClass.getRegister(Address);
break;
1180 unsigned Src1Reg)
const {
1209 .
addReg(AMDGPU::PRED_SEL_OFF)
1216 #define OPERAND_CASE(Label) \
1218 static const unsigned Ops[] = \
1257 assert (MI->
getOpcode() == AMDGPU::DOT_4 &&
"Not Implemented");
1260 Opcode = AMDGPU::DOT4_r600;
1262 Opcode = AMDGPU::DOT4_eg;
1270 static const unsigned Operands[14] = {
1271 AMDGPU::OpName::update_exec_mask,
1272 AMDGPU::OpName::update_pred,
1274 AMDGPU::OpName::omod,
1275 AMDGPU::OpName::dst_rel,
1276 AMDGPU::OpName::clamp,
1277 AMDGPU::OpName::src0_neg,
1278 AMDGPU::OpName::src0_rel,
1279 AMDGPU::OpName::src0_abs,
1280 AMDGPU::OpName::src0_sel,
1281 AMDGPU::OpName::src1_neg,
1282 AMDGPU::OpName::src1_rel,
1283 AMDGPU::OpName::src1_abs,
1284 AMDGPU::OpName::src1_sel,
1292 for (
unsigned i = 0; i < 14; i++) {
1295 assert (MO.
isImm());
1305 uint64_t Imm)
const {
1307 AMDGPU::ALU_LITERAL_X);
1314 unsigned DstReg,
unsigned SrcReg)
const {
1327 int64_t Imm)
const {
1329 assert(Idx != -1 &&
"Operand not supported for this instruction.");
1343 unsigned Flag)
const {
1344 unsigned TargetFlags =
get(MI->
getOpcode()).TSFlags;
1365 case 0: FlagIndex =
getOperandIdx(*MI, AMDGPU::OpName::src0_neg);
break;
1366 case 1: FlagIndex =
getOperandIdx(*MI, AMDGPU::OpName::src1_neg);
break;
1367 case 2: FlagIndex =
getOperandIdx(*MI, AMDGPU::OpName::src2_neg);
break;
1372 assert(!IsOP3 &&
"Cannot set absolute value modifier for OP3 "
1376 case 0: FlagIndex =
getOperandIdx(*MI, AMDGPU::OpName::src0_abs);
break;
1377 case 1: FlagIndex =
getOperandIdx(*MI, AMDGPU::OpName::src1_abs);
break;
1385 assert(FlagIndex != -1 &&
"Flag not supported for this instruction");
1388 assert(FlagIndex != 0 &&
1389 "Instruction flags not supported for this instruction");
1393 assert(FlagOp.
isImm());
1398 unsigned Flag)
const {
1399 unsigned TargetFlags =
get(MI->
getOpcode()).TSFlags;
1419 unsigned Flag)
const {
1420 unsigned TargetFlags =
get(MI->
getOpcode()).TSFlags;
1426 unsigned InstFlags = FlagOp.
getImm();
1428 FlagOp.
setImm(InstFlags);
MachineInstr * buildSlotOfVectorInstruction(MachineBasicBlock &MBB, MachineInstr *MI, unsigned Slot, unsigned DstReg) const
bool readsLDSSrcReg(const MachineInstr *MI) const
bool hasCaymanISA() const
void push_back(const T &Elt)
void clearFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const
Clear the specified flag on the instruction.
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
mop_iterator operands_end()
void setImmOperand(MachineInstr *MI, unsigned Op, int64_t Imm) const
Helper function for setting instruction flag values.
bool isLDSInstr(unsigned Opcode) const
AMDGPU specific subclass of TargetSubtarget.
unsigned calculateIndirectAddress(unsigned RegIndex, unsigned Channel) const override
Calculate the "Indirect Address" for the given RegIndex and Channel.
int getSrcIdx(unsigned Opcode, unsigned SrcNum) const
Interface definition for R600InstrInfo.
MachineBasicBlock * getMBB() const
unsigned getHWRegChan(unsigned reg) const
get the HW encoding for a register's channel.
bool canBeConsideredALU(const MachineInstr *MI) const
bool isVector(const MachineInstr &MI) const
Vector instructions are instructions that must fill all instruction slots within an instruction group...
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, DebugLoc DL) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
bool fitsReadPortLimitations(const std::vector< MachineInstr * > &MIs, const DenseMap< unsigned, unsigned > &PV, std::vector< BankSwizzle > &BS, bool isLastAluTrans) const
Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210 returns true and the first ...
static unsigned getSlotedOps(unsigned Op, unsigned Slot)
static bool isConstCompatible(R600InstrInfo::BankSwizzle TransSwz, const std::vector< std::pair< int, unsigned > > &TransOps, unsigned ConstCount)
Instructions in Trans slot can't read gpr at cycle 0 if they also read a const, and can't read a gpr ...
#define OPCODE_IS_NOT_ZERO_INT
bool hasVertexCache() const
bool isPlaceHolderOpcode(unsigned opcode) const
Interface definition for R600RegisterInfo.
bool isVectorOnly(unsigned Opcode) const
bool hasFlagOperand(const MachineInstr &MI) const
bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
const R600RegisterInfo & getRegisterInfo() const override
COPY - Target-independent register copy.
bool isCubeOp(unsigned opcode) const
static MachineBasicBlock::iterator FindLastAluClause(MachineBasicBlock &MBB)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const AMDGPUSubtarget & ST
static unsigned getTransSwizzle(R600InstrInfo::BankSwizzle Swz, unsigned Op)
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false)
unsigned getShaderType() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Reg
All possible values of the reg field in the ModR/M byte.
MachineInstr * buildMovImm(MachineBasicBlock &BB, MachineBasicBlock::iterator I, unsigned DstReg, uint64_t Imm) const
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
MachineInstr * buildMovInstr(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned DstReg, unsigned SrcReg) const override
Build a MOV instruction.
virtual const InstrItineraryData * getInstrItineraryData() const
getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget...
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
#define HAS_NATIVE_OPERANDS(Flags)
bool DefinesPredicate(MachineInstr *MI, std::vector< MachineOperand > &Pred) const override
bool hasInstrModifiers(unsigned Opcode) const
static bool isJump(unsigned Opcode)
bool isPredicable(MachineInstr *MI) const override
bool usesVertexCache(unsigned Opcode) const
#define OPCODE_IS_NOT_ZERO
R600InstrInfo(const AMDGPUSubtarget &st)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Itinerary data supplied by a subtarget to be used by a target.
iterator getLastNonDebugInstr()
getLastNonDebugInstr - returns an iterator to the last non-debug instruction in the basic block...
MachineOperand & getFlagOp(MachineInstr *MI, unsigned SrcIdx=0, unsigned Flag=0) const
bool usesTextureCache(unsigned Opcode) const
Generation getGeneration() const
size_t size() const
size - Get the array size.
reverse_iterator rbegin()
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Flag
These should be considered private to the implementation of the MCInstrDesc class.
const MachineBasicBlock * getParent() const
bool isExport(unsigned Opcode) const
bundle_iterator< MachineInstr, instr_iterator > iterator
SmallVector< std::pair< MachineOperand *, int64_t >, 3 > getSrcs(MachineInstr *MI) const
unsigned getHWRegIndex(unsigned Reg) const override
bool isPredicated(const MachineInstr *MI) const override
bool FindSwizzleForVectorSlot(const std::vector< std::vector< std::pair< int, unsigned > > > &IGSrcs, std::vector< R600InstrInfo::BankSwizzle > &SwzCandidate, const std::vector< std::pair< int, unsigned > > &TransSrcs, R600InstrInfo::BankSwizzle TransSwz) const
Enumerate all possible Swizzle sequence to find one that can meet all read port requirements.
int findRegisterDefOperandIdx(unsigned Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a def of the specified register or -1 if it is not found...
DebugLoc findDebugLoc(instr_iterator MBBI)
findDebugLoc - find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE instructions...
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
bundle_iterator - MachineBasicBlock iterator that automatically skips over MIs that are inside bundle...
const MachineOperand & getOperand(unsigned i) const
unsigned getSubRegFromChannel(unsigned Channel) const
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, const BranchProbability &Probability) const override
bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override
bool isPredicable(MachineInstr *MI) const override
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
void setImm(int64_t immVal)
int getOperandIdx(const MachineInstr &MI, unsigned Op) const
Get the index of Op in the MachineInstr.
static MachineInstr * findFirstPredicateSetterFrom(MachineBasicBlock &MBB, MachineBasicBlock::iterator I)
unsigned RemoveBranch(MachineBasicBlock &MBB) const override
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
bool empty() const
empty - Check if the array is empty.
The AMDGPU TargetMachine interface definition for hw codgen targets.
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override
void setIsKill(bool Val=true)
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, unsigned ExtraPredCycles, const BranchProbability &Probability) const override
static bool NextPossibleSolution(std::vector< R600InstrInfo::BankSwizzle > &SwzCandidate, unsigned Idx)
Given a swizzle sequence SwzCandidate and an index Idx, returns the next (in lexicographic term) swiz...
virtual const TargetFrameLowering * getFrameLowering() const
unsigned int getPredicationCost(const MachineInstr *) const override
int findRegisterUseOperandIdx(unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a use of the specific register or -1 if it is not found...
bool usesAddressRegister(MachineInstr *MI) const
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
bool isPhysRegLiveAcrossClauses(unsigned Reg) const
#define OPERAND_CASE(Label)
unsigned getStackWidth(const MachineFunction &MF) const
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
bool isTrig(const MachineInstr &MI) const
bool mustBeLastInClause(unsigned Opcode) const
static bool isPredicateSetter(unsigned Opcode)
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
void write(void *memory, value_type value)
Write a value to memory with a particular endianness.
int getSelIdx(unsigned Opcode, unsigned SrcIdx) const
bool ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
int getIndirectIndexEnd(const MachineFunction &MF) const
unsigned int getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr *MI, unsigned *PredCost=nullptr) const override
TargetSubtargetInfo - Generic base class for all target subtargets.
Representation of each machine instruction.
void addFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const
Add one of the MO_FLAG* flags to the specified Operand.
void reserveIndirectRegisters(BitVector &Reserved, const MachineFunction &MF) const
Reserve the registers that may be accesed using indirect addressing.
MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned Opcode, unsigned DstReg, unsigned Src0Reg, unsigned Src1Reg=0) const
buildDefaultInstruction - This function returns a MachineInstr with all the instruction modifiers ini...
#define GET_FLAG_OPERAND_IDX(Flags)
Helper for getting the operand index for the instruction flags operand.
Information about the stack frame layout on the AMDGPU targets.
void setReg(unsigned Reg)
Change the register this operand corresponds to.
unsigned isLegalUpTo(const std::vector< std::vector< std::pair< int, unsigned > > > &IGSrcs, const std::vector< R600InstrInfo::BankSwizzle > &Swz, const std::vector< std::pair< int, unsigned > > &TransSrcs, R600InstrInfo::BankSwizzle TransSwz) const
returns how many MIs (whose inputs are represented by IGSrcs) can be packed in the same Instruction G...
iterator find(const KeyT &Val)
static std::vector< std::pair< int, unsigned > > Swizzle(std::vector< std::pair< int, unsigned > > Src, R600InstrInfo::BankSwizzle Swz)
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
unsigned getMaxAlusPerClause() const
bool isReductionOp(unsigned opcode) const
const TargetRegisterClass * getIndirectAddrRegClass() const override
unsigned getReg() const
getReg - Returns the register number.
DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &) const override
bool isMov(unsigned Opcode) const override
static bool isBranch(unsigned Opcode)
std::reverse_iterator< iterator > reverse_iterator
mop_iterator operands_begin()
bool definesAddressRegister(MachineInstr *MI) const
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
int getIndirectIndexBegin(const MachineFunction &MF) const
#define GET_REG_INDEX(reg)
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex)
bool isLDSNoRetInstr(unsigned Opcode) const
bool fitsConstReadLimitations(const std::vector< MachineInstr * > &) const
An instruction group can only access 2 channel pair (either [XY] or [ZW]) from KCache bank on R700+...
bool isLDSRetInstr(unsigned Opcode) const
bool PredicateInstruction(MachineInstr *MI, ArrayRef< MachineOperand > Pred) const override
bool isALUInstr(unsigned Opcode) const
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
bool isTransOnly(unsigned Opcode) const
#define OPCODE_IS_ZERO_INT
bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const override