37 PPC::R0, PPC::R1,
PPC::R2, PPC::R3,
39 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
40 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
41 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
42 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
43 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
44 PPC::R28, PPC::R29, PPC::R30, PPC::R31
50 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
51 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
52 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
53 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
54 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
55 PPC::R28, PPC::R29, PPC::R30, PPC::R31
58 PPC::X0, PPC::X1, PPC::X2, PPC::X3,
59 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
60 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
61 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
62 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
63 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
64 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
65 PPC::X28, PPC::X29, PPC::X30, PPC::X31
69 PPC::X1, PPC::X2, PPC::X3,
70 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
71 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
72 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
73 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
74 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
75 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
76 PPC::X28, PPC::X29, PPC::X30, PPC::X31
79 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
80 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
81 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
82 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
83 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
84 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
85 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
86 PPC::F28, PPC::F29, PPC::F30, PPC::F31
89 PPC::V0, PPC::V1,
PPC::V2, PPC::V3,
90 PPC::V4, PPC::V5, PPC::V6, PPC::V7,
91 PPC::V8, PPC::V9, PPC::V10, PPC::V11,
92 PPC::V12, PPC::V13, PPC::V14, PPC::V15,
93 PPC::V16, PPC::V17, PPC::V18, PPC::V19,
94 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
95 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
96 PPC::V28, PPC::V29, PPC::V30, PPC::V31
99 PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3,
100 PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7,
101 PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11,
102 PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15,
103 PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19,
104 PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23,
105 PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27,
106 PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31,
108 PPC::VSH0, PPC::VSH1, PPC::VSH2, PPC::VSH3,
109 PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7,
110 PPC::VSH8, PPC::VSH9, PPC::VSH10, PPC::VSH11,
111 PPC::VSH12, PPC::VSH13, PPC::VSH14, PPC::VSH15,
112 PPC::VSH16, PPC::VSH17, PPC::VSH18, PPC::VSH19,
113 PPC::VSH20, PPC::VSH21, PPC::VSH22, PPC::VSH23,
114 PPC::VSH24, PPC::VSH25, PPC::VSH26, PPC::VSH27,
115 PPC::VSH28, PPC::VSH29, PPC::VSH30, PPC::VSH31
118 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
119 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
120 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
121 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
122 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
123 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
124 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
125 PPC::F28, PPC::F29, PPC::F30, PPC::F31,
127 PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3,
128 PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
129 PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11,
130 PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
131 PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
132 PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
133 PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
134 PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
137 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
138 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
139 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
140 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
141 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
142 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
143 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
144 PPC::F28, PPC::F29, PPC::F30, PPC::F31,
146 PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3,
147 PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
148 PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11,
149 PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
150 PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
151 PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
152 PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
153 PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
156 PPC::QF0, PPC::QF1, PPC::QF2, PPC::QF3,
157 PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7,
158 PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11,
159 PPC::QF12, PPC::QF13, PPC::QF14, PPC::QF15,
160 PPC::QF16, PPC::QF17, PPC::QF18, PPC::QF19,
161 PPC::QF20, PPC::QF21, PPC::QF22, PPC::QF23,
162 PPC::QF24, PPC::QF25, PPC::QF26, PPC::QF27,
163 PPC::QF28, PPC::QF29, PPC::QF30, PPC::QF31
166 PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
167 PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
168 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
169 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
170 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
171 PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
172 PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
173 PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
176 PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
177 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
190 int64_t Res = cast<MCConstantExpr>(E)->getValue();
191 return Res < 0 ? -1 : Res;
198 if (Name ==
"lt")
return 0;
199 if (Name ==
"gt")
return 1;
200 if (Name ==
"eq")
return 2;
201 if (Name ==
"so")
return 3;
202 if (Name ==
"un")
return 3;
204 if (Name ==
"cr0")
return 0;
205 if (Name ==
"cr1")
return 1;
206 if (Name ==
"cr2")
return 2;
207 if (Name ==
"cr3")
return 3;
208 if (Name ==
"cr4")
return 4;
209 if (Name ==
"cr5")
return 5;
210 if (Name ==
"cr6")
return 6;
211 if (Name ==
"cr7")
return 7;
225 if (LHSVal < 0 || RHSVal < 0)
234 return Res < 0 ? -1 : Res;
251 void Warning(
SMLoc L,
const Twine &Msg) { getParser().Warning(L, Msg); }
252 bool Error(
SMLoc L,
const Twine &Msg) {
return getParser().Error(L, Msg); }
254 bool isPPC64()
const {
return IsPPC64; }
255 bool isDarwin()
const {
return IsDarwin; }
258 unsigned &RegNo, int64_t &
IntVal);
260 bool ParseRegister(
unsigned &RegNo,
SMLoc &StartLoc,
SMLoc &EndLoc)
override;
265 bool ParseExpression(
const MCExpr *&EVal);
266 bool ParseDarwinExpression(
const MCExpr *&EVal);
270 bool ParseDirectiveWord(
unsigned Size,
SMLoc L);
271 bool ParseDirectiveTC(
unsigned Size,
SMLoc L);
272 bool ParseDirectiveMachine(
SMLoc L);
273 bool ParseDarwinDirectiveMachine(
SMLoc L);
274 bool ParseDirectiveAbiVersion(
SMLoc L);
275 bool ParseDirectiveLocalEntry(
SMLoc L);
277 bool MatchAndEmitInstruction(
SMLoc IDLoc,
unsigned &Opcode,
280 bool MatchingInlineAsm)
override;
287 #define GET_ASSEMBLER_HEADER
288 #include "PPCGenAsmMatcher.inc"
303 setAvailableFeatures(ComputeAvailableFeatures(STI.
getFeatureBits()));
309 bool ParseDirective(
AsmToken DirectiveID)
override;
312 unsigned Kind)
override;
330 SMLoc StartLoc, EndLoc;
355 struct TLSRegOp TLSReg;
362 StartLoc = o.StartLoc;
370 case ContextImmediate:
383 SMLoc getStartLoc()
const override {
return StartLoc; }
386 SMLoc getEndLoc()
const override {
return EndLoc; }
389 bool isPPC64()
const {
return IsPPC64; }
391 int64_t getImm()
const {
392 assert(
Kind == Immediate &&
"Invalid access!");
395 int64_t getImmS16Context()
const {
396 assert((
Kind == Immediate ||
Kind == ContextImmediate) &&
"Invalid access!");
397 if (
Kind == Immediate)
399 return static_cast<int16_t
>(Imm.Val);
401 int64_t getImmU16Context()
const {
402 assert((
Kind == Immediate ||
Kind == ContextImmediate) &&
"Invalid access!");
406 const MCExpr *getExpr()
const {
407 assert(
Kind == Expression &&
"Invalid access!");
411 int64_t getExprCRVal()
const {
412 assert(
Kind == Expression &&
"Invalid access!");
416 const MCExpr *getTLSReg()
const {
417 assert(
Kind == TLSRegister &&
"Invalid access!");
421 unsigned getReg()
const override {
422 assert(isRegNumber() &&
"Invalid access!");
423 return (
unsigned) Imm.Val;
426 unsigned getVSReg()
const {
427 assert(isVSRegNumber() &&
"Invalid access!");
428 return (
unsigned) Imm.Val;
431 unsigned getCCReg()
const {
432 assert(isCCRegNumber() &&
"Invalid access!");
433 return (
unsigned) (
Kind == Immediate ? Imm.Val : Expr.CRVal);
436 unsigned getCRBit()
const {
437 assert(isCRBitNumber() &&
"Invalid access!");
438 return (
unsigned) (
Kind == Immediate ? Imm.Val : Expr.CRVal);
441 unsigned getCRBitMask()
const {
442 assert(isCRBitMask() &&
"Invalid access!");
443 return 7 - countTrailingZeros<uint64_t>(Imm.Val);
446 bool isToken()
const override {
return Kind == Token; }
447 bool isImm()
const override {
return Kind == Immediate ||
Kind == Expression; }
448 bool isU1Imm()
const {
return Kind == Immediate && isUInt<1>(getImm()); }
449 bool isU2Imm()
const {
return Kind == Immediate && isUInt<2>(getImm()); }
450 bool isU3Imm()
const {
return Kind == Immediate && isUInt<3>(getImm()); }
451 bool isU4Imm()
const {
return Kind == Immediate && isUInt<4>(getImm()); }
452 bool isU5Imm()
const {
return Kind == Immediate && isUInt<5>(getImm()); }
453 bool isS5Imm()
const {
return Kind == Immediate && isInt<5>(getImm()); }
454 bool isU6Imm()
const {
return Kind == Immediate && isUInt<6>(getImm()); }
455 bool isU6ImmX2()
const {
return Kind == Immediate &&
456 isUInt<6>(getImm()) &&
457 (getImm() & 1) == 0; }
458 bool isU7ImmX4()
const {
return Kind == Immediate &&
459 isUInt<7>(getImm()) &&
460 (getImm() & 3) == 0; }
461 bool isU8ImmX8()
const {
return Kind == Immediate &&
463 (getImm() & 7) == 0; }
465 bool isU10Imm()
const {
return Kind == Immediate && isUInt<10>(getImm()); }
466 bool isU12Imm()
const {
return Kind == Immediate && isUInt<12>(getImm()); }
467 bool isU16Imm()
const {
472 case ContextImmediate:
478 bool isS16Imm()
const {
483 case ContextImmediate:
489 bool isS16ImmX4()
const {
return Kind == Expression ||
491 (getImm() & 3) == 0); }
492 bool isS17Imm()
const {
497 case ContextImmediate:
498 return isInt<17>(getImmS16Context());
503 bool isTLSReg()
const {
return Kind == TLSRegister; }
504 bool isDirectBr()
const {
505 if (
Kind == Expression)
507 if (
Kind != Immediate)
510 if ((getImm() & 3) != 0)
512 if (isInt<26>(getImm()))
516 if (
isUInt<32>(getImm()) && isInt<26>(static_cast<int32_t>(getImm())))
521 bool isCondBr()
const {
return Kind == Expression ||
523 (getImm() & 3) == 0); }
524 bool isRegNumber()
const {
return Kind == Immediate && isUInt<5>(getImm()); }
525 bool isVSRegNumber()
const {
return Kind == Immediate && isUInt<6>(getImm()); }
526 bool isCCRegNumber()
const {
return (
Kind == Expression
527 && isUInt<3>(getExprCRVal())) ||
529 && isUInt<3>(getImm())); }
530 bool isCRBitNumber()
const {
return (
Kind == Expression
531 && isUInt<5>(getExprCRVal())) ||
533 && isUInt<5>(getImm())); }
534 bool isCRBitMask()
const {
return Kind == Immediate &&
isUInt<8>(getImm()) &&
536 bool isMem()
const override {
return false; }
537 bool isReg()
const override {
return false; }
539 void addRegOperands(
MCInst &Inst,
unsigned N)
const {
543 void addRegGPRCOperands(
MCInst &Inst,
unsigned N)
const {
544 assert(N == 1 &&
"Invalid number of operands!");
548 void addRegGPRCNoR0Operands(
MCInst &Inst,
unsigned N)
const {
549 assert(N == 1 &&
"Invalid number of operands!");
553 void addRegG8RCOperands(
MCInst &Inst,
unsigned N)
const {
554 assert(N == 1 &&
"Invalid number of operands!");
558 void addRegG8RCNoX0Operands(
MCInst &Inst,
unsigned N)
const {
559 assert(N == 1 &&
"Invalid number of operands!");
563 void addRegGxRCOperands(
MCInst &Inst,
unsigned N)
const {
565 addRegG8RCOperands(Inst, N);
567 addRegGPRCOperands(Inst, N);
570 void addRegGxRCNoR0Operands(
MCInst &Inst,
unsigned N)
const {
572 addRegG8RCNoX0Operands(Inst, N);
574 addRegGPRCNoR0Operands(Inst, N);
577 void addRegF4RCOperands(
MCInst &Inst,
unsigned N)
const {
578 assert(N == 1 &&
"Invalid number of operands!");
582 void addRegF8RCOperands(
MCInst &Inst,
unsigned N)
const {
583 assert(N == 1 &&
"Invalid number of operands!");
587 void addRegVRRCOperands(
MCInst &Inst,
unsigned N)
const {
588 assert(N == 1 &&
"Invalid number of operands!");
592 void addRegVSRCOperands(
MCInst &Inst,
unsigned N)
const {
593 assert(N == 1 &&
"Invalid number of operands!");
597 void addRegVSFRCOperands(
MCInst &Inst,
unsigned N)
const {
598 assert(N == 1 &&
"Invalid number of operands!");
602 void addRegVSSRCOperands(
MCInst &Inst,
unsigned N)
const {
603 assert(N == 1 &&
"Invalid number of operands!");
607 void addRegQFRCOperands(
MCInst &Inst,
unsigned N)
const {
608 assert(N == 1 &&
"Invalid number of operands!");
612 void addRegQSRCOperands(
MCInst &Inst,
unsigned N)
const {
613 assert(N == 1 &&
"Invalid number of operands!");
617 void addRegQBRCOperands(
MCInst &Inst,
unsigned N)
const {
618 assert(N == 1 &&
"Invalid number of operands!");
622 void addRegCRBITRCOperands(
MCInst &Inst,
unsigned N)
const {
623 assert(N == 1 &&
"Invalid number of operands!");
627 void addRegCRRCOperands(
MCInst &Inst,
unsigned N)
const {
628 assert(N == 1 &&
"Invalid number of operands!");
632 void addCRBitMaskOperands(
MCInst &Inst,
unsigned N)
const {
633 assert(N == 1 &&
"Invalid number of operands!");
637 void addImmOperands(
MCInst &Inst,
unsigned N)
const {
638 assert(N == 1 &&
"Invalid number of operands!");
639 if (
Kind == Immediate)
645 void addS16ImmOperands(
MCInst &Inst,
unsigned N)
const {
646 assert(N == 1 &&
"Invalid number of operands!");
651 case ContextImmediate:
660 void addU16ImmOperands(
MCInst &Inst,
unsigned N)
const {
661 assert(N == 1 &&
"Invalid number of operands!");
666 case ContextImmediate:
675 void addBranchTargetOperands(
MCInst &Inst,
unsigned N)
const {
676 assert(N == 1 &&
"Invalid number of operands!");
677 if (
Kind == Immediate)
683 void addTLSRegOperands(
MCInst &Inst,
unsigned N)
const {
684 assert(N == 1 &&
"Invalid number of operands!");
689 assert(
Kind == Token &&
"Invalid access!");
695 static std::unique_ptr<PPCOperand> CreateToken(
StringRef Str,
SMLoc S,
697 auto Op = make_unique<PPCOperand>(Token);
698 Op->Tok.Data = Str.
data();
699 Op->Tok.Length = Str.
size();
702 Op->IsPPC64 = IsPPC64;
706 static std::unique_ptr<PPCOperand>
713 void *Mem = ::operator
new(
sizeof(PPCOperand) + Str.
size());
714 std::unique_ptr<PPCOperand> Op(
new (Mem) PPCOperand(Token));
715 Op->Tok.Data =
reinterpret_cast<const char *
>(Op.get() + 1);
716 Op->Tok.Length = Str.
size();
717 std::memcpy(const_cast<char *>(Op->Tok.Data), Str.
data(), Str.
size());
720 Op->IsPPC64 = IsPPC64;
724 static std::unique_ptr<PPCOperand> CreateImm(int64_t Val,
SMLoc S,
SMLoc E,
726 auto Op = make_unique<PPCOperand>(Immediate);
730 Op->IsPPC64 = IsPPC64;
734 static std::unique_ptr<PPCOperand> CreateExpr(
const MCExpr *Val,
SMLoc S,
735 SMLoc E,
bool IsPPC64) {
736 auto Op = make_unique<PPCOperand>(Expression);
741 Op->IsPPC64 = IsPPC64;
745 static std::unique_ptr<PPCOperand>
747 auto Op = make_unique<PPCOperand>(TLSRegister);
748 Op->TLSReg.Sym = Sym;
751 Op->IsPPC64 = IsPPC64;
755 static std::unique_ptr<PPCOperand>
756 CreateContextImm(int64_t Val,
SMLoc S,
SMLoc E,
bool IsPPC64) {
757 auto Op = make_unique<PPCOperand>(ContextImmediate);
761 Op->IsPPC64 = IsPPC64;
765 static std::unique_ptr<PPCOperand>
768 return CreateImm(
CE->getValue(), S, E, IsPPC64);
772 return CreateTLSReg(SRE, S, E, IsPPC64);
774 if (
const PPCMCExpr *TE = dyn_cast<PPCMCExpr>(Val)) {
776 if (TE->evaluateAsConstant(Res))
777 return CreateContextImm(Res, S, E, IsPPC64);
780 return CreateExpr(Val, S, E, IsPPC64);
792 case ContextImmediate:
811 if (
const MCUnaryExpr *UnExpr = dyn_cast<MCUnaryExpr>(Expr)) {
816 }
else if (
const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Expr)) {
819 BinExpr->getLHS(), Ctx);
827 void PPCAsmParser::ProcessInstruction(
MCInst &Inst,
836 TmpInst.
setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ?
837 PPC::DCBT : PPC::DCBTST);
839 (Opcode == PPC::DCBTx || Opcode == PPC::DCBTSTx) ? 0 : 16));
856 case PPC::DCBTSTDS: {
915 TmpInst.
setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
929 TmpInst.
setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
943 TmpInst.
setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
958 TmpInst.
setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
972 TmpInst.
setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
985 TmpInst.
setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
998 TmpInst.
setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
1008 case PPC::CLRRWIo: {
1011 TmpInst.
setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
1021 case PPC::CLRLSLWIo: {
1025 TmpInst.
setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
1035 case PPC::EXTLDIo: {
1039 TmpInst.
setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
1048 case PPC::EXTRDIo: {
1052 TmpInst.
setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
1061 case PPC::INSRDIo: {
1065 TmpInst.
setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
1075 case PPC::ROTRDIo: {
1078 TmpInst.
setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
1090 TmpInst.
setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
1102 TmpInst.
setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
1111 case PPC::CLRRDIo: {
1114 TmpInst.
setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
1123 case PPC::CLRLSLDIo: {
1127 TmpInst.
setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
1136 case PPC::RLWINMobm: {
1143 TmpInst.
setOpcode(Opcode == PPC::RLWINMbm ? PPC::RLWINM : PPC::RLWINMo);
1153 case PPC::RLWIMIobm: {
1160 TmpInst.
setOpcode(Opcode == PPC::RLWIMIbm ? PPC::RLWIMI : PPC::RLWIMIo);
1171 case PPC::RLWNMobm: {
1178 TmpInst.
setOpcode(Opcode == PPC::RLWNMbm ? PPC::RLWNM : PPC::RLWNMo);
1188 if (STI.getFeatureBits()[PPC::FeatureMFTB]) {
1197 bool PPCAsmParser::MatchAndEmitInstruction(
SMLoc IDLoc,
unsigned &Opcode,
1200 bool MatchingInlineAsm) {
1203 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
1206 ProcessInstruction(Inst, Operands);
1210 case Match_MissingFeature:
1211 return Error(IDLoc,
"instruction use requires an option to be enabled");
1212 case Match_MnemonicFail:
1213 return Error(IDLoc,
"unrecognized instruction mnemonic");
1214 case Match_InvalidOperand: {
1215 SMLoc ErrorLoc = IDLoc;
1216 if (ErrorInfo != ~0ULL) {
1217 if (ErrorInfo >= Operands.
size())
1218 return Error(IDLoc,
"too few operands for instruction");
1220 ErrorLoc = ((PPCOperand &)*Operands[ErrorInfo]).getStartLoc();
1221 if (ErrorLoc ==
SMLoc()) ErrorLoc = IDLoc;
1224 return Error(ErrorLoc,
"invalid operand for instruction");
1237 RegNo = isPPC64()? PPC::LR8 : PPC::LR;
1241 RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
1245 RegNo = PPC::VRSAVE;
1279 ParseRegister(
unsigned &RegNo,
SMLoc &StartLoc,
SMLoc &EndLoc) {
1292 return Error(StartLoc,
"invalid register name");
1301 const MCExpr *PPCAsmParser::
1302 ExtractModifierFromExpr(
const MCExpr *E,
1304 MCContext &Context = getParser().getContext();
1355 const MCExpr *LHS = ExtractModifierFromExpr(BE->
getLHS(), LHSVariant);
1356 const MCExpr *RHS = ExtractModifierFromExpr(BE->
getRHS(), RHSVariant);
1361 if (!LHS) LHS = BE->
getLHS();
1362 if (!RHS) RHS = BE->
getRHS();
1365 Variant = RHSVariant;
1367 Variant = LHSVariant;
1368 else if (LHSVariant == RHSVariant)
1369 Variant = LHSVariant;
1384 const MCExpr *PPCAsmParser::
1385 FixupVariantKind(
const MCExpr *E) {
1386 MCContext &Context = getParser().getContext();
1434 ParseExpression(
const MCExpr *&EVal) {
1437 return ParseDarwinExpression(EVal);
1441 if (getParser().parseExpression(EVal))
1444 EVal = FixupVariantKind(EVal);
1447 const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1461 ParseDarwinExpression(
const MCExpr *&EVal) {
1464 switch (getLexer().getKind()) {
1489 if (getParser().parseExpression(EVal))
1511 switch (getLexer().getKind()) {
1520 Operands.
push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1523 return Error(S,
"invalid register name");
1535 Operands.
push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1549 if (!ParseExpression(EVal))
1553 return Error(S,
"unknown operand");
1557 Operands.
push_back(PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64()));
1560 bool TLSCall =
false;
1562 TLSCall = Ref->getSymbol().getName() ==
"__tls_get_addr";
1569 if (ParseExpression(TLSSym))
1570 return Error(S,
"invalid TLS call expression");
1576 Operands.
push_back(PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64()));
1585 switch (getLexer().getKind()) {
1590 return Error(S,
"invalid register name");
1596 if (getParser().parseAbsoluteExpression(IntVal) ||
1597 IntVal < 0 || IntVal > 31)
1598 return Error(S,
"invalid register number");
1600 return Error(S,
"unexpected integer value");
1615 return Error(S,
"invalid memory operand");
1623 Operands.
push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1635 std::string NewOpcode;
1650 size_t Dot = Name.
find(
'.');
1652 if (!NewOpcode.empty())
1654 PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64()));
1656 Operands.
push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1660 if (!NewOpcode.empty())
1662 PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64()));
1664 Operands.
push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1672 if (ParseOperand(Operands))
1681 if (ParseOperand(Operands))
1693 if (STI.getFeatureBits()[PPC::FeatureBookE] &&
1694 Operands.
size() == 4 &&
1695 (Name ==
"dcbt" || Name ==
"dcbtst")) {
1704 bool PPCAsmParser::ParseDirective(
AsmToken DirectiveID) {
1707 if (IDVal ==
".word")
1708 return ParseDirectiveWord(2, DirectiveID.
getLoc());
1709 if (IDVal ==
".llong")
1710 return ParseDirectiveWord(8, DirectiveID.
getLoc());
1712 return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.
getLoc());
1713 if (IDVal ==
".machine")
1714 return ParseDirectiveMachine(DirectiveID.
getLoc());
1715 if (IDVal ==
".abiversion")
1716 return ParseDirectiveAbiVersion(DirectiveID.
getLoc());
1717 if (IDVal ==
".localentry")
1718 return ParseDirectiveLocalEntry(DirectiveID.
getLoc());
1720 if (IDVal ==
".machine")
1721 return ParseDarwinDirectiveMachine(DirectiveID.
getLoc());
1728 bool PPCAsmParser::ParseDirectiveWord(
unsigned Size,
SMLoc L) {
1733 if (getParser().parseExpression(Value))
1736 getParser().getStreamer().EmitValue(Value, Size);
1742 return Error(L,
"unexpected token in directive");
1753 bool PPCAsmParser::ParseDirectiveTC(
unsigned Size,
SMLoc L) {
1760 Error(L,
"unexpected token in directive");
1766 getParser().getStreamer().EmitValueToAlignment(Size);
1769 return ParseDirectiveWord(Size, L);
1774 bool PPCAsmParser::ParseDirectiveMachine(
SMLoc L) {
1778 Error(L,
"unexpected token in directive");
1790 if (CPU !=
"any" && CPU !=
"push" && CPU !=
"pop") {
1791 Error(L,
"unrecognized machine type");
1796 Error(L,
"unexpected token in directive");
1801 getParser().getStreamer().getTargetStreamer());
1809 bool PPCAsmParser::ParseDarwinDirectiveMachine(
SMLoc L) {
1813 Error(L,
"unexpected token in directive");
1823 if (CPU !=
"ppc7400" && CPU !=
"ppc" && CPU !=
"ppc64") {
1824 Error(L,
"unrecognized cpu type");
1828 if (isPPC64() && (CPU ==
"ppc7400" || CPU ==
"ppc")) {
1829 Error(L,
"wrong cpu type specified for 64bit");
1832 if (!isPPC64() && CPU ==
"ppc64") {
1833 Error(L,
"wrong cpu type specified for 32bit");
1838 Error(L,
"unexpected token in directive");
1847 bool PPCAsmParser::ParseDirectiveAbiVersion(
SMLoc L) {
1849 if (getParser().parseAbsoluteExpression(AbiVersion)){
1850 Error(L,
"expected constant expression");
1854 Error(L,
"unexpected token in directive");
1860 getParser().getStreamer().getTargetStreamer());
1868 bool PPCAsmParser::ParseDirectiveLocalEntry(
SMLoc L) {
1870 if (getParser().parseIdentifier(Name)) {
1871 Error(L,
"expected identifier in directive");
1874 MCSymbolELF *Sym = cast<MCSymbolELF>(getContext().getOrCreateSymbol(Name));
1877 Error(L,
"unexpected token in directive");
1883 if (getParser().parseExpression(Expr)) {
1884 Error(L,
"expected expression");
1889 Error(L,
"unexpected token in directive");
1895 getParser().getStreamer().getTargetStreamer());
1910 #define GET_REGISTER_MATCHER
1911 #define GET_MATCHER_IMPLEMENTATION
1912 #include "PPCGenAsmMatcher.inc"
1923 case MCK_0: ImmVal = 0;
break;
1924 case MCK_1: ImmVal = 1;
break;
1925 case MCK_2: ImmVal = 2;
break;
1926 case MCK_3: ImmVal = 3;
break;
1927 case MCK_4: ImmVal = 4;
break;
1928 case MCK_5: ImmVal = 5;
break;
1929 case MCK_6: ImmVal = 6;
break;
1930 case MCK_7: ImmVal = 7;
break;
1931 default:
return Match_InvalidOperand;
1934 PPCOperand &Op =
static_cast<PPCOperand &
>(AsmOp);
1935 if (Op.isImm() && Op.getImm() == ImmVal)
1936 return Match_Success;
1938 return Match_InvalidOperand;
1942 PPCAsmParser::applyModifierToExpr(
const MCExpr *E,
static bool isReg(const MCInst &MI, unsigned OpNo)
bool isUInt< 8 >(uint64_t x)
std::enable_if< std::numeric_limits< T >::is_signed, bool >::type getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
static const MCPhysReg XRegsNoX0[32]
void push_back(const T &Elt)
static int64_t EvaluateCRExpr(const MCExpr *E)
static const MCUnaryExpr * create(Opcode Op, const MCExpr *Expr, MCContext &Ctx)
static const MCUnaryExpr * createMinus(const MCExpr *Expr, MCContext &Ctx)
const MCSymbol & getSymbol() const
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
const char * getPointer() const
size_t size() const
size - Get the string size.
static unsigned MatchRegisterName(StringRef Name)
Generic assembler parser interface, for use by target specific assembly parsers.
static const PPCMCExpr * create(VariantKind Kind, const MCExpr *Expr, bool isDarwin, MCContext &Ctx)
static MCOperand createExpr(const MCExpr *Val)
MCTargetAsmParser - Generic interface to target specific assembly parsers.
size_t find(char C, size_t From=0) const
Search for the first character C in the string.
StringRef getString() const
Get the string for the current token, this includes all characters (for example, the quotes on string...
StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
static const MCPhysReg VRegs[32]
static const MCPhysReg CRBITRegs[32]
virtual const AsmToken & Lex()=0
Get the next AsmToken in the stream, possibly handling file inclusion first.
static const MCPhysReg FRegs[32]
virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
bool isMacOSX() const
isMacOSX - Is this a Mac OS X triple.
static const MCBinaryExpr * create(Opcode Op, const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
static MCOperand createReg(unsigned Reg)
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
std::pair< StringRef, StringRef > getToken(StringRef Source, StringRef Delimiters=" \t\n\v\f\r")
getToken - This function extracts one token from source, ignoring any leading characters that appear ...
static const MCPhysReg VSSRegs[64]
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Base class for the full range of assembler expressions which are needed for parsing.
Target independent representation for an assembler token.
Represent a reference to a symbol from inside an expression.
Windows NT (Windows on ARM)
static const MCPhysReg CRRegs[8]
MCParsedAsmOperand - This abstract class represents a source-level assembly instruction operand...
static const MCPhysReg XRegs[32]
Context object for machine code objects.
static unsigned QFRegs[32]
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
Unary assembler expressions.
virtual void emitLocalEntry(MCSymbolELF *S, const MCExpr *LocalOffset)=0
const AsmToken & getTok() const
Get the current AsmToken from the stream.
Instances of this class represent a single low-level machine instruction.
const MCExpr * getExpr() const
const MCExpr * getLHS() const
Get the left-hand side expression of the binary operator.
Streaming machine code generation interface.
virtual void emitAbiVersion(int AbiVersion)=0
Interface to description of machine instruction set.
void LLVMInitializePowerPCAsmParser()
Force static initialization.
Binary assembler expressions.
static void addNegOperand(MCInst &Inst, MCOperand &Op, MCContext &Ctx)
Triple - Helper class for working with autoconf configuration names.
void setOpcode(unsigned Op)
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
bool is(TokenKind K) const
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
unsigned getOpcode() const
bool isUInt< 32 >(uint64_t x)
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
static SMLoc getFromPointer(const char *Ptr)
const MCExpr * getRHS() const
Get the right-hand side expression of the binary operator.
StringRef getIdentifier() const
Get the identifier string for the current token, which should be an identifier or a string...
static const MCPhysReg VSRegs[64]
const MCExpr * getSubExpr() const
Get the child of this unary expression.
RegisterMCAsmParser - Helper template for registering a target specific assembly parser, for use in the target machine initialization function.
StringRef getName() const
getName - Get the symbol name.
bool equals_lower(StringRef RHS) const
equals_lower - Check for string equality, ignoring case.
unsigned getNumOperands() const
Opcode getOpcode() const
Get the kind of this binary expression.
MCSubtargetInfo - Generic base class for all target subtargets.
References to labels and assigned expressions.
static bool isMem(const MachineInstr *MI, unsigned Op)
bool isInt< 16 >(int64_t x)
const Triple & getTargetTriple() const
getTargetTriple - Return the target triple string.
static const MCPhysReg RRegs[32]
VariantKind getKind() const
const ARM::ArchExtKind Kind
static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME)
Returns true iff Val consists of one contiguous run of 1s with any number of 0s on either side...
LLVM Value Representation.
static const MCPhysReg VSFRegs[64]
bool isUInt< 16 >(uint64_t x)
This class implements an extremely fast bulk output stream that can only output to a stream...
C - The default llvm calling convention, compatible with C.
bool isPowerOf2_32(uint32_t Value)
isPowerOf2_32 - This function returns true if the argument is a power of two > 0. ...
void addOperand(const MCOperand &Op)
StringRef - Represent a constant reference to a string, i.e.
Target specific expression.
StringRef slice(size_t Start, size_t End) const
Return a reference to the substring from [Start, End).
virtual void emitMachine(StringRef CPU)=0
Represents a location in source code.
bool startswith_lower(StringRef Prefix) const
Check if this string starts with the given Prefix, ignoring case.
Instances of this class represent operands of the MCInst class.
static MCOperand createImm(int64_t Val)
const MCOperand & getOperand(unsigned i) const
static const MCPhysReg RRegsNoR0[32]
Opcode getOpcode() const
Get the kind of this unary expression.