16 #ifndef LLVM_LIB_TARGET_R600_SIINSTRINFO_H
17 #define LLVM_LIB_TARGET_R600_SIINSTRINFO_H
66 unsigned findUsedSGPR(
const MachineInstr *MI,
int OpIndices[3])
const;
80 int64_t &Offset2)
const override;
88 unsigned NumLoads)
const final;
92 unsigned DestReg,
unsigned SrcReg,
93 bool KillSrc)
const override;
100 unsigned Size)
const;
123 bool NewMI =
false)
const override;
126 unsigned &SrcOpIdx2)
const override;
137 unsigned DstReg,
unsigned SrcReg)
const override;
138 bool isMov(
unsigned Opcode)
const override;
207 bool isDS(uint16_t Opcode)
const {
241 unsigned OpSize)
const;
248 unsigned OpName)
const;
263 unsigned OpNo)
const;
267 unsigned getOpSize(uint16_t Opcode,
unsigned OpNo)
const {
276 return RI.getRegClass(OpInfo.
RegClass)->getSize();
312 unsigned HalfImmOp,
unsigned HalfSGPROp,
323 unsigned Channel)
const override;
331 unsigned OffsetReg)
const override;
337 unsigned OffsetReg)
const override;
342 unsigned SavReg,
unsigned IndexReg)
const;
351 unsigned OpName)
const {
375 namespace KernelInputOffsets {
Interface definition for SIRegisterInfo.
bool shouldClusterLoads(MachineInstr *FirstLdSt, MachineInstr *SecondLdSt, unsigned NumLoads) const final
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned ValueReg, unsigned Address, unsigned OffsetReg) const override
Build instruction(s) for an indirect register write.
int getVOPe64(uint16_t Opcode)
const SIRegisterInfo & getRegisterInfo() const override
void splitSMRD(MachineInstr *MI, const TargetRegisterClass *HalfRC, unsigned HalfImmOp, unsigned HalfSGPROp, MachineInstr *&Lo, MachineInstr *&Hi) const
Split an SMRD instruction into two smaller loads of half the.
Describe properties that are true of each instruction in the target description file.
bool isSOPP(uint16_t Opcode) const
void moveToVALU(MachineInstr &MI) const
Replace this instruction's opcode with the equivalent VALU opcode.
bool isSALU(uint16_t Opcode) const
bool isSOP2(uint16_t Opcode) const
unsigned getMovOpcode(const TargetRegisterClass *DstRC) const
MachineInstr * commuteInstruction(MachineInstr *MI, bool NewMI=false) const override
bool hasModifiers(unsigned Opcode) const
Return true if this instruction has any modifiers.
bool isFLAT(uint16_t Opcode) const
unsigned getSize() const
getSize - Return the size of the register in bytes, which is also the size of a stack slot allocated ...
bool verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const override
bool isVALU(uint16_t Opcode) const
int getAtomicNoRetOp(uint16_t Opcode)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
unsigned calculateLDSSpillAddress(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, RegScavenger *RS, unsigned TmpReg, unsigned Offset, unsigned Size) const
bool getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg, unsigned &Offset, const TargetRegisterInfo *TRI) const final
MachineOperand * getNamedOperand(MachineInstr &MI, unsigned OperandName) const
Returns the operand named Op.
Reg
All possible values of the reg field in the ModR/M byte.
int getCommuteOrig(uint16_t Opcode)
bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override
int getAtomicRetOp(uint16_t Opcode)
unsigned calculateIndirectAddress(unsigned RegIndex, unsigned Channel) const override
Calculate the "Indirect Address" for the given RegIndex and Channel.
uint8_t OperandType
Information about the type of the operand.
int commuteOpcode(const MachineInstr &MI) const
unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const
This form should usually be preferred since it handles operands with unknown register classes...
bool canReadVGPR(const MachineInstr &MI, unsigned OpNo) const
bool isImmOperandLegal(const MachineInstr *MI, unsigned OpNo, const MachineOperand &MO) const
SIInstrInfo(const AMDGPUSubtarget &st)
const uint64_t RSRC_DATA_FORMAT
bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override
const MachineOperand * getNamedOperand(const MachineInstr &MI, unsigned OpName) const
bool isVOP3(uint16_t Opcode) const
bool isSMRD(uint16_t Opcode) const
bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
bundle_iterator< MachineInstr, instr_iterator > iterator
unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const
Return the size in bytes of the operand OpNo on the given.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool usesConstantBus(const MachineRegisterInfo &MRI, const MachineOperand &MO, unsigned OpSize) const
Returns true if this operand uses the constant bus.
bundle_iterator - MachineBasicBlock iterator that automatically skips over MIs that are inside bundle...
bool isMov(unsigned Opcode) const override
bool isSOPK(uint16_t Opcode) const
uint64_t getDefaultRsrcDataFormat() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isLiteralConstant(const MachineOperand &MO, unsigned OpSize) const
int getVOPe32(uint16_t Opcode)
const uint64_t RSRC_TID_ENABLE
bool isVOP1(uint16_t Opcode) const
bool isInlineConstant(const APInt &Imm) const
void legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const
Legalize the OpIndex operand of this instruction by inserting a MOV.
bool isOperandLegal(const MachineInstr *MI, unsigned OpIdx, const MachineOperand *MO=nullptr) const
Check if MO is a legal operand if it was the OpIdx Operand for MI.
bool isWQM(uint16_t Opcode) const
bool hasVALU32BitEncoding(unsigned Opcode) const
Return true if this 64-bit VALU instruction has a 32-bit encoding.
MachineOperand class - Representation of each machine instruction operand.
const TargetRegisterClass * getIndirectAddrRegClass() const override
bool isMIMG(uint16_t Opcode) const
MachineInstr * convertToThreeAddress(MachineFunction::iterator &MBB, MachineBasicBlock::iterator &MI, LiveVariables *LV) const override
Represents one node in the SelectionDAG.
bool isDS(uint16_t Opcode) const
bool isVOP2(uint16_t Opcode) const
bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
bool isSOP1(uint16_t Opcode) const
Class for arbitrary precision integers.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, unsigned Reg, MachineRegisterInfo *MRI) const final
void reserveIndirectRegisters(BitVector &Reserved, const MachineFunction &MF) const
Contains the definition of a TargetInstrInfo class that is common to all AMD GPUs.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
void moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const
Representation of each machine instruction.
bool isVGPRSpill(uint16_t Opcode) const
bool isMTBUF(uint16_t Opcode) const
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
void legalizeOperands(MachineInstr *MI) const
Legalize all operands in this instruction.
int getCommuteRev(uint16_t Opcode)
void LoadM0(MachineInstr *MoveRel, MachineBasicBlock::iterator I, unsigned SavReg, unsigned IndexReg) const
int getAddr64Inst(uint16_t Opcode)
static unsigned getVALUOp(const MachineInstr &MI)
bool isSALUOpSupportedOnVALU(const MachineInstr &MI) const
MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned ValueReg, unsigned Address, unsigned OffsetReg) const override
Build instruction(s) for an indirect register read.
bool isSOPC(uint16_t Opcode) const
bool isTriviallyReMaterializable(const MachineInstr *MI, AliasAnalysis *AA=nullptr) const
bool hasModifiersSet(const MachineInstr &MI, unsigned OpName) const
bool areMemAccessesTriviallyDisjoint(MachineInstr *MIa, MachineInstr *MIb, AliasAnalysis *AA=nullptr) const override
unsigned getMachineCSELookAheadLimit() const override
bool isVOPC(uint16_t Opcode) const
BasicBlockListType::iterator iterator
const TargetRegisterClass * getOpRegClass(const MachineInstr &MI, unsigned OpNo) const
Return the correct register class for OpNo.
StringRef - Represent a constant reference to a string, i.e.
MachineInstr * buildMovInstr(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned DstReg, unsigned SrcReg) const override
Build a MOV instruction.
This holds information about one operand of a machine instruction, indicating the register class for ...
void insertNOPs(MachineBasicBlock::iterator MI, int Count) const
bool isMUBUF(uint16_t Opcode) const
bool isReallyTriviallyReMaterializable(const MachineInstr *MI, AliasAnalysis *AA) const override