25 #define DEBUG_TYPE "nvptx-isel"
29 cl::desc(
"NVPTX Specifies: 0 use div.approx, 1 use div.full, 2 use"
30 " IEEE Compliant F32 div.rnd if available."),
35 cl::desc(
"NVPTX Specific: 0 use sqrt.approx, 1 use sqrt.rn."),
40 cl::desc(
"NVPTX Specific: Flush f32 subnormals to sign-preserving zero."),
48 return new NVPTXDAGToDAGISel(TM, OptLevel);
54 doMulWide = (OptLevel > 0);
59 return SelectionDAGISel::runOnMachineFunction(MF);
62 int NVPTXDAGToDAGISel::getDivF32Level()
const {
68 if (
TM.Options.UnsafeFPMath)
75 bool NVPTXDAGToDAGISel::usePrecSqrtF32()
const {
81 return !
TM.Options.UnsafeFPMath;
85 bool NVPTXDAGToDAGISel::useF32FTZ()
const {
99 bool NVPTXDAGToDAGISel::allowFMA()
const {
113 SDNode *ResNode =
nullptr;
116 ResNode = SelectLoad(N);
119 ResNode = SelectStore(N);
123 ResNode = SelectLoadVector(N);
129 ResNode = SelectLDGLDU(N);
133 ResNode = SelectStoreVector(N);
138 ResNode = SelectLoadParam(N);
143 ResNode = SelectStoreRetval(N);
150 ResNode = SelectStoreParam(N);
153 ResNode = SelectIntrinsicNoChain(N);
156 ResNode = SelectIntrinsicChain(N);
326 ResNode = SelectTextureIntrinsic(N);
493 ResNode = SelectSurfaceIntrinsic(N);
499 ResNode = SelectBFE(N);
502 ResNode = SelectAddrSpaceCast(N);
509 return SelectCode(N);
512 SDNode *NVPTXDAGToDAGISel::SelectIntrinsicChain(
SDNode *N) {
513 unsigned IID = cast<ConstantSDNode>(N->
getOperand(1))->getZExtValue();
517 case Intrinsic::nvvm_ldg_global_f:
518 case Intrinsic::nvvm_ldg_global_i:
519 case Intrinsic::nvvm_ldg_global_p:
520 case Intrinsic::nvvm_ldu_global_f:
521 case Intrinsic::nvvm_ldu_global_i:
522 case Intrinsic::nvvm_ldu_global_p:
523 return SelectLDGLDU(N);
534 switch (PT->getAddressSpace()) {
547 SDNode *NVPTXDAGToDAGISel::SelectIntrinsicNoChain(
SDNode *N) {
548 unsigned IID = cast<ConstantSDNode>(N->
getOperand(0))->getZExtValue();
552 case Intrinsic::nvvm_texsurf_handle_internal:
553 return SelectTexSurfHandle(N);
557 SDNode *NVPTXDAGToDAGISel::SelectTexSurfHandle(
SDNode *N) {
561 return CurDAG->getMachineNode(NVPTX::texsurf_handles,
SDLoc(N), MVT::i64,
565 SDNode *NVPTXDAGToDAGISel::SelectAddrSpaceCast(
SDNode *N) {
571 assert(SrcAddrSpace != DstAddrSpace &&
572 "addrspacecast must be between different address spaces");
577 switch (SrcAddrSpace) {
580 Opc =
TM.is64Bit() ? NVPTX::cvta_global_yes_64 : NVPTX::cvta_global_yes;
583 Opc =
TM.is64Bit() ? NVPTX::cvta_shared_yes_64 : NVPTX::cvta_shared_yes;
586 Opc =
TM.is64Bit() ? NVPTX::cvta_const_yes_64 : NVPTX::cvta_const_yes;
589 Opc =
TM.is64Bit() ? NVPTX::cvta_local_yes_64 : NVPTX::cvta_local_yes;
595 if (SrcAddrSpace != 0)
598 switch (DstAddrSpace) {
601 Opc =
TM.is64Bit() ? NVPTX::cvta_to_global_yes_64
602 : NVPTX::cvta_to_global_yes;
605 Opc =
TM.is64Bit() ? NVPTX::cvta_to_shared_yes_64
606 : NVPTX::cvta_to_shared_yes;
610 TM.is64Bit() ? NVPTX::cvta_to_const_yes_64 : NVPTX::cvta_to_const_yes;
614 TM.is64Bit() ? NVPTX::cvta_to_local_yes_64 : NVPTX::cvta_to_local_yes;
617 Opc =
TM.is64Bit() ? NVPTX::nvvm_ptr_gen_to_param_64
618 : NVPTX::nvvm_ptr_gen_to_param;
629 SDNode *NVPTXLD =
nullptr;
635 if (!LoadedVT.isSimple())
650 MVT SimpleVT = LoadedVT.getSimpleVT();
670 unsigned fromTypeWidth = std::max(8U, ScalarVT.
getSizeInBits());
671 unsigned int fromType;
687 if (SelectDirectAddr(N1, Addr)) {
690 Opcode = NVPTX::LD_i8_avar;
693 Opcode = NVPTX::LD_i16_avar;
696 Opcode = NVPTX::LD_i32_avar;
699 Opcode = NVPTX::LD_i64_avar;
702 Opcode = NVPTX::LD_f32_avar;
705 Opcode = NVPTX::LD_f64_avar;
710 SDValue Ops[] = { getI32Imm(isVolatile, dl), getI32Imm(codeAddrSpace, dl),
711 getI32Imm(vecType, dl), getI32Imm(fromType, dl),
712 getI32Imm(fromTypeWidth, dl), Addr, Chain };
713 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT,
MVT::Other, Ops);
714 }
else if (
TM.is64Bit() ? SelectADDRsi64(N1.
getNode(), N1, Base, Offset)
715 : SelectADDRsi(N1.
getNode(), N1, Base, Offset)) {
718 Opcode = NVPTX::LD_i8_asi;
721 Opcode = NVPTX::LD_i16_asi;
724 Opcode = NVPTX::LD_i32_asi;
727 Opcode = NVPTX::LD_i64_asi;
730 Opcode = NVPTX::LD_f32_asi;
733 Opcode = NVPTX::LD_f64_asi;
738 SDValue Ops[] = { getI32Imm(isVolatile, dl), getI32Imm(codeAddrSpace, dl),
739 getI32Imm(vecType, dl), getI32Imm(fromType, dl),
740 getI32Imm(fromTypeWidth, dl), Base, Offset, Chain };
741 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT,
MVT::Other, Ops);
742 }
else if (
TM.is64Bit() ? SelectADDRri64(N1.
getNode(), N1, Base, Offset)
743 : SelectADDRri(N1.
getNode(), N1, Base, Offset)) {
747 Opcode = NVPTX::LD_i8_ari_64;
750 Opcode = NVPTX::LD_i16_ari_64;
753 Opcode = NVPTX::LD_i32_ari_64;
756 Opcode = NVPTX::LD_i64_ari_64;
759 Opcode = NVPTX::LD_f32_ari_64;
762 Opcode = NVPTX::LD_f64_ari_64;
770 Opcode = NVPTX::LD_i8_ari;
773 Opcode = NVPTX::LD_i16_ari;
776 Opcode = NVPTX::LD_i32_ari;
779 Opcode = NVPTX::LD_i64_ari;
782 Opcode = NVPTX::LD_f32_ari;
785 Opcode = NVPTX::LD_f64_ari;
791 SDValue Ops[] = { getI32Imm(isVolatile, dl), getI32Imm(codeAddrSpace, dl),
792 getI32Imm(vecType, dl), getI32Imm(fromType, dl),
793 getI32Imm(fromTypeWidth, dl), Base, Offset, Chain };
794 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT,
MVT::Other, Ops);
799 Opcode = NVPTX::LD_i8_areg_64;
802 Opcode = NVPTX::LD_i16_areg_64;
805 Opcode = NVPTX::LD_i32_areg_64;
808 Opcode = NVPTX::LD_i64_areg_64;
811 Opcode = NVPTX::LD_f32_areg_64;
814 Opcode = NVPTX::LD_f64_areg_64;
822 Opcode = NVPTX::LD_i8_areg;
825 Opcode = NVPTX::LD_i16_areg;
828 Opcode = NVPTX::LD_i32_areg;
831 Opcode = NVPTX::LD_i64_areg;
834 Opcode = NVPTX::LD_f32_areg;
837 Opcode = NVPTX::LD_f64_areg;
843 SDValue Ops[] = { getI32Imm(isVolatile, dl), getI32Imm(codeAddrSpace, dl),
844 getI32Imm(vecType, dl), getI32Imm(fromType, dl),
845 getI32Imm(fromTypeWidth, dl), N1, Chain };
846 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT,
MVT::Other, Ops);
851 MemRefs0[0] = cast<MemSDNode>(
N)->getMemOperand();
852 cast<MachineSDNode>(NVPTXLD)->setMemRefs(MemRefs0, MemRefs0 + 1);
858 SDNode *NVPTXDAGToDAGISel::SelectLoadVector(
SDNode *N) {
869 if (!LoadedVT.isSimple())
884 MVT SimpleVT = LoadedVT.getSimpleVT();
894 unsigned FromTypeWidth = std::max(8U, ScalarVT.
getSizeInBits());
897 unsigned ExtensionType = cast<ConstantSDNode>(
921 if (SelectDirectAddr(Op1, Addr)) {
930 Opcode = NVPTX::LDV_i8_v2_avar;
933 Opcode = NVPTX::LDV_i16_v2_avar;
936 Opcode = NVPTX::LDV_i32_v2_avar;
939 Opcode = NVPTX::LDV_i64_v2_avar;
942 Opcode = NVPTX::LDV_f32_v2_avar;
945 Opcode = NVPTX::LDV_f64_v2_avar;
954 Opcode = NVPTX::LDV_i8_v4_avar;
957 Opcode = NVPTX::LDV_i16_v4_avar;
960 Opcode = NVPTX::LDV_i32_v4_avar;
963 Opcode = NVPTX::LDV_f32_v4_avar;
969 SDValue Ops[] = { getI32Imm(IsVolatile, DL), getI32Imm(CodeAddrSpace, DL),
970 getI32Imm(VecType, DL), getI32Imm(FromType, DL),
971 getI32Imm(FromTypeWidth, DL), Addr, Chain };
972 LD = CurDAG->getMachineNode(Opcode, DL, N->
getVTList(), Ops);
973 }
else if (
TM.is64Bit() ? SelectADDRsi64(Op1.
getNode(), Op1, Base, Offset)
974 : SelectADDRsi(Op1.
getNode(), Op1, Base, Offset)) {
983 Opcode = NVPTX::LDV_i8_v2_asi;
986 Opcode = NVPTX::LDV_i16_v2_asi;
989 Opcode = NVPTX::LDV_i32_v2_asi;
992 Opcode = NVPTX::LDV_i64_v2_asi;
995 Opcode = NVPTX::LDV_f32_v2_asi;
998 Opcode = NVPTX::LDV_f64_v2_asi;
1007 Opcode = NVPTX::LDV_i8_v4_asi;
1010 Opcode = NVPTX::LDV_i16_v4_asi;
1013 Opcode = NVPTX::LDV_i32_v4_asi;
1016 Opcode = NVPTX::LDV_f32_v4_asi;
1022 SDValue Ops[] = { getI32Imm(IsVolatile, DL), getI32Imm(CodeAddrSpace, DL),
1023 getI32Imm(VecType, DL), getI32Imm(FromType, DL),
1024 getI32Imm(FromTypeWidth, DL), Base, Offset, Chain };
1025 LD = CurDAG->getMachineNode(Opcode, DL, N->
getVTList(), Ops);
1026 }
else if (
TM.is64Bit() ? SelectADDRri64(Op1.
getNode(), Op1, Base, Offset)
1027 : SelectADDRri(Op1.
getNode(), Op1, Base, Offset)) {
1037 Opcode = NVPTX::LDV_i8_v2_ari_64;
1040 Opcode = NVPTX::LDV_i16_v2_ari_64;
1043 Opcode = NVPTX::LDV_i32_v2_ari_64;
1046 Opcode = NVPTX::LDV_i64_v2_ari_64;
1049 Opcode = NVPTX::LDV_f32_v2_ari_64;
1052 Opcode = NVPTX::LDV_f64_v2_ari_64;
1061 Opcode = NVPTX::LDV_i8_v4_ari_64;
1064 Opcode = NVPTX::LDV_i16_v4_ari_64;
1067 Opcode = NVPTX::LDV_i32_v4_ari_64;
1070 Opcode = NVPTX::LDV_f32_v4_ari_64;
1084 Opcode = NVPTX::LDV_i8_v2_ari;
1087 Opcode = NVPTX::LDV_i16_v2_ari;
1090 Opcode = NVPTX::LDV_i32_v2_ari;
1093 Opcode = NVPTX::LDV_i64_v2_ari;
1096 Opcode = NVPTX::LDV_f32_v2_ari;
1099 Opcode = NVPTX::LDV_f64_v2_ari;
1108 Opcode = NVPTX::LDV_i8_v4_ari;
1111 Opcode = NVPTX::LDV_i16_v4_ari;
1114 Opcode = NVPTX::LDV_i32_v4_ari;
1117 Opcode = NVPTX::LDV_f32_v4_ari;
1124 SDValue Ops[] = { getI32Imm(IsVolatile, DL), getI32Imm(CodeAddrSpace, DL),
1125 getI32Imm(VecType, DL), getI32Imm(FromType, DL),
1126 getI32Imm(FromTypeWidth, DL), Base, Offset, Chain };
1128 LD = CurDAG->getMachineNode(Opcode, DL, N->
getVTList(), Ops);
1139 Opcode = NVPTX::LDV_i8_v2_areg_64;
1142 Opcode = NVPTX::LDV_i16_v2_areg_64;
1145 Opcode = NVPTX::LDV_i32_v2_areg_64;
1148 Opcode = NVPTX::LDV_i64_v2_areg_64;
1151 Opcode = NVPTX::LDV_f32_v2_areg_64;
1154 Opcode = NVPTX::LDV_f64_v2_areg_64;
1163 Opcode = NVPTX::LDV_i8_v4_areg_64;
1166 Opcode = NVPTX::LDV_i16_v4_areg_64;
1169 Opcode = NVPTX::LDV_i32_v4_areg_64;
1172 Opcode = NVPTX::LDV_f32_v4_areg_64;
1186 Opcode = NVPTX::LDV_i8_v2_areg;
1189 Opcode = NVPTX::LDV_i16_v2_areg;
1192 Opcode = NVPTX::LDV_i32_v2_areg;
1195 Opcode = NVPTX::LDV_i64_v2_areg;
1198 Opcode = NVPTX::LDV_f32_v2_areg;
1201 Opcode = NVPTX::LDV_f64_v2_areg;
1210 Opcode = NVPTX::LDV_i8_v4_areg;
1213 Opcode = NVPTX::LDV_i16_v4_areg;
1216 Opcode = NVPTX::LDV_i32_v4_areg;
1219 Opcode = NVPTX::LDV_f32_v4_areg;
1226 SDValue Ops[] = { getI32Imm(IsVolatile, DL), getI32Imm(CodeAddrSpace, DL),
1227 getI32Imm(VecType, DL), getI32Imm(FromType, DL),
1228 getI32Imm(FromTypeWidth, DL), Op1, Chain };
1229 LD = CurDAG->getMachineNode(Opcode, DL, N->
getVTList(), Ops);
1233 MemRefs0[0] = cast<MemSDNode>(
N)->getMemOperand();
1234 cast<MachineSDNode>(
LD)->setMemRefs(MemRefs0, MemRefs0 + 1);
1250 Mem = cast<MemIntrinsicSDNode>(
N);
1251 unsigned IID = cast<ConstantSDNode>(N->
getOperand(1))->getZExtValue();
1255 case Intrinsic::nvvm_ldg_global_f:
1256 case Intrinsic::nvvm_ldg_global_i:
1257 case Intrinsic::nvvm_ldg_global_p:
1260 case Intrinsic::nvvm_ldu_global_f:
1261 case Intrinsic::nvvm_ldu_global_i:
1262 case Intrinsic::nvvm_ldu_global_p:
1268 Mem = cast<MemSDNode>(
N);
1281 if (SelectDirectAddr(Op1, Addr)) {
1291 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i8avar;
1294 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i16avar;
1297 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i32avar;
1300 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i64avar;
1303 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f32avar;
1306 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f64avar;
1314 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i8avar;
1317 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i16avar;
1320 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i32avar;
1323 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i64avar;
1326 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f32avar;
1329 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f64avar;
1339 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_avar;
1342 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_avar;
1345 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_avar;
1348 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_avar;
1351 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_avar;
1354 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_avar;
1363 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_avar;
1366 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_avar;
1369 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_avar;
1372 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_avar;
1375 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_avar;
1378 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_avar;
1387 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_avar;
1390 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_avar;
1393 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_avar;
1396 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_avar;
1405 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_avar;
1408 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_avar;
1411 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_avar;
1414 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_avar;
1420 SDValue Ops[] = { Addr, Chain };
1421 LD = CurDAG->getMachineNode(Opcode, DL, N->
getVTList(), Ops);
1422 }
else if (
TM.is64Bit() ? SelectADDRri64(Op1.
getNode(), Op1, Base, Offset)
1423 : SelectADDRri(Op1.
getNode(), Op1, Base, Offset)) {
1434 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i8ari64;
1437 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i16ari64;
1440 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i32ari64;
1443 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i64ari64;
1446 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f32ari64;
1449 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f64ari64;
1457 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i8ari64;
1460 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i16ari64;
1463 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i32ari64;
1466 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i64ari64;
1469 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f32ari64;
1472 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f64ari64;
1482 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_ari64;
1485 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_ari64;
1488 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_ari64;
1491 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_ari64;
1494 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_ari64;
1497 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_ari64;
1506 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_ari64;
1509 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_ari64;
1512 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_ari64;
1515 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_ari64;
1518 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_ari64;
1521 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_ari64;
1530 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_ari64;
1533 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_ari64;
1536 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_ari64;
1539 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_ari64;
1548 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_ari64;
1551 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_ari64;
1554 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_ari64;
1557 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_ari64;
1572 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i8ari;
1575 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i16ari;
1578 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i32ari;
1581 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i64ari;
1584 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f32ari;
1587 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f64ari;
1595 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i8ari;
1598 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i16ari;
1601 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i32ari;
1604 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i64ari;
1607 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f32ari;
1610 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f64ari;
1620 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_ari32;
1623 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_ari32;
1626 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_ari32;
1629 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_ari32;
1632 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_ari32;
1635 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_ari32;
1644 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_ari32;
1647 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_ari32;
1650 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_ari32;
1653 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_ari32;
1656 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_ari32;
1659 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_ari32;
1668 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_ari32;
1671 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_ari32;
1674 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_ari32;
1677 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_ari32;
1686 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_ari32;
1689 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_ari32;
1692 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_ari32;
1695 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_ari32;
1702 SDValue Ops[] = { Base, Offset, Chain };
1704 LD = CurDAG->getMachineNode(Opcode, DL, N->
getVTList(), Ops);
1716 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i8areg64;
1719 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i16areg64;
1722 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i32areg64;
1725 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i64areg64;
1728 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f32areg64;
1731 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f64areg64;
1739 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i8areg64;
1742 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i16areg64;
1745 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i32areg64;
1748 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i64areg64;
1751 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f32areg64;
1754 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f64areg64;
1764 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_areg64;
1767 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_areg64;
1770 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_areg64;
1773 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_areg64;
1776 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_areg64;
1779 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_areg64;
1788 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_areg64;
1791 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_areg64;
1794 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_areg64;
1797 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_areg64;
1800 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_areg64;
1803 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_areg64;
1812 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_areg64;
1815 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_areg64;
1818 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_areg64;
1821 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_areg64;
1830 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_areg64;
1833 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_areg64;
1836 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_areg64;
1839 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_areg64;
1854 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i8areg;
1857 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i16areg;
1860 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i32areg;
1863 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i64areg;
1866 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f32areg;
1869 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f64areg;
1877 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i8areg;
1880 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i16areg;
1883 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i32areg;
1886 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i64areg;
1889 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f32areg;
1892 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f64areg;
1902 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_areg32;
1905 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_areg32;
1908 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_areg32;
1911 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_areg32;
1914 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_areg32;
1917 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_areg32;
1926 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_areg32;
1929 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_areg32;
1932 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_areg32;
1935 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_areg32;
1938 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_areg32;
1941 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_areg32;
1950 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_areg32;
1953 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_areg32;
1956 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_areg32;
1959 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_areg32;
1968 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_areg32;
1971 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_areg32;
1974 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_areg32;
1977 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_areg32;
1984 SDValue Ops[] = { Op1, Chain };
1985 LD = CurDAG->getMachineNode(Opcode, DL, N->
getVTList(), Ops);
1990 cast<MachineSDNode>(
LD)->setMemRefs(MemRefs0, MemRefs0 + 1);
1999 SDNode *NVPTXST =
nullptr;
2005 if (!StoreVT.isSimple())
2020 MVT SimpleVT = StoreVT.getSimpleVT();
2037 unsigned int toType;
2052 if (SelectDirectAddr(N2, Addr)) {
2055 Opcode = NVPTX::ST_i8_avar;
2058 Opcode = NVPTX::ST_i16_avar;
2061 Opcode = NVPTX::ST_i32_avar;
2064 Opcode = NVPTX::ST_i64_avar;
2067 Opcode = NVPTX::ST_f32_avar;
2070 Opcode = NVPTX::ST_f64_avar;
2075 SDValue Ops[] = { N1, getI32Imm(isVolatile, dl),
2076 getI32Imm(codeAddrSpace, dl), getI32Imm(vecType, dl),
2077 getI32Imm(toType, dl), getI32Imm(toTypeWidth, dl), Addr,
2079 NVPTXST = CurDAG->getMachineNode(Opcode, dl,
MVT::Other, Ops);
2080 }
else if (
TM.is64Bit() ? SelectADDRsi64(N2.
getNode(), N2, Base, Offset)
2081 : SelectADDRsi(N2.
getNode(), N2, Base, Offset)) {
2084 Opcode = NVPTX::ST_i8_asi;
2087 Opcode = NVPTX::ST_i16_asi;
2090 Opcode = NVPTX::ST_i32_asi;
2093 Opcode = NVPTX::ST_i64_asi;
2096 Opcode = NVPTX::ST_f32_asi;
2099 Opcode = NVPTX::ST_f64_asi;
2104 SDValue Ops[] = { N1, getI32Imm(isVolatile, dl),
2105 getI32Imm(codeAddrSpace, dl), getI32Imm(vecType, dl),
2106 getI32Imm(toType, dl), getI32Imm(toTypeWidth, dl), Base,
2108 NVPTXST = CurDAG->getMachineNode(Opcode, dl,
MVT::Other, Ops);
2109 }
else if (
TM.is64Bit() ? SelectADDRri64(N2.
getNode(), N2, Base, Offset)
2110 : SelectADDRri(N2.
getNode(), N2, Base, Offset)) {
2114 Opcode = NVPTX::ST_i8_ari_64;
2117 Opcode = NVPTX::ST_i16_ari_64;
2120 Opcode = NVPTX::ST_i32_ari_64;
2123 Opcode = NVPTX::ST_i64_ari_64;
2126 Opcode = NVPTX::ST_f32_ari_64;
2129 Opcode = NVPTX::ST_f64_ari_64;
2137 Opcode = NVPTX::ST_i8_ari;
2140 Opcode = NVPTX::ST_i16_ari;
2143 Opcode = NVPTX::ST_i32_ari;
2146 Opcode = NVPTX::ST_i64_ari;
2149 Opcode = NVPTX::ST_f32_ari;
2152 Opcode = NVPTX::ST_f64_ari;
2158 SDValue Ops[] = { N1, getI32Imm(isVolatile, dl),
2159 getI32Imm(codeAddrSpace, dl), getI32Imm(vecType, dl),
2160 getI32Imm(toType, dl), getI32Imm(toTypeWidth, dl), Base,
2162 NVPTXST = CurDAG->getMachineNode(Opcode, dl,
MVT::Other, Ops);
2167 Opcode = NVPTX::ST_i8_areg_64;
2170 Opcode = NVPTX::ST_i16_areg_64;
2173 Opcode = NVPTX::ST_i32_areg_64;
2176 Opcode = NVPTX::ST_i64_areg_64;
2179 Opcode = NVPTX::ST_f32_areg_64;
2182 Opcode = NVPTX::ST_f64_areg_64;
2190 Opcode = NVPTX::ST_i8_areg;
2193 Opcode = NVPTX::ST_i16_areg;
2196 Opcode = NVPTX::ST_i32_areg;
2199 Opcode = NVPTX::ST_i64_areg;
2202 Opcode = NVPTX::ST_f32_areg;
2205 Opcode = NVPTX::ST_f64_areg;
2211 SDValue Ops[] = { N1, getI32Imm(isVolatile, dl),
2212 getI32Imm(codeAddrSpace, dl), getI32Imm(vecType, dl),
2213 getI32Imm(toType, dl), getI32Imm(toTypeWidth, dl), N2,
2215 NVPTXST = CurDAG->getMachineNode(Opcode, dl,
MVT::Other, Ops);
2220 MemRefs0[0] = cast<MemSDNode>(
N)->getMemOperand();
2221 cast<MachineSDNode>(NVPTXST)->setMemRefs(MemRefs0, MemRefs0 + 1);
2227 SDNode *NVPTXDAGToDAGISel::SelectStoreVector(
SDNode *N) {
2256 assert(StoreVT.isSimple() &&
"Store value is not simple");
2260 if (ScalarVT.isFloatingPoint())
2288 StOps.
push_back(getI32Imm(IsVolatile, DL));
2289 StOps.
push_back(getI32Imm(CodeAddrSpace, DL));
2290 StOps.
push_back(getI32Imm(VecType, DL));
2292 StOps.
push_back(getI32Imm(ToTypeWidth, DL));
2294 if (SelectDirectAddr(N2, Addr)) {
2303 Opcode = NVPTX::STV_i8_v2_avar;
2306 Opcode = NVPTX::STV_i16_v2_avar;
2309 Opcode = NVPTX::STV_i32_v2_avar;
2312 Opcode = NVPTX::STV_i64_v2_avar;
2315 Opcode = NVPTX::STV_f32_v2_avar;
2318 Opcode = NVPTX::STV_f64_v2_avar;
2327 Opcode = NVPTX::STV_i8_v4_avar;
2330 Opcode = NVPTX::STV_i16_v4_avar;
2333 Opcode = NVPTX::STV_i32_v4_avar;
2336 Opcode = NVPTX::STV_f32_v4_avar;
2342 }
else if (
TM.is64Bit() ? SelectADDRsi64(N2.
getNode(), N2, Base, Offset)
2343 : SelectADDRsi(N2.
getNode(), N2, Base, Offset)) {
2352 Opcode = NVPTX::STV_i8_v2_asi;
2355 Opcode = NVPTX::STV_i16_v2_asi;
2358 Opcode = NVPTX::STV_i32_v2_asi;
2361 Opcode = NVPTX::STV_i64_v2_asi;
2364 Opcode = NVPTX::STV_f32_v2_asi;
2367 Opcode = NVPTX::STV_f64_v2_asi;
2376 Opcode = NVPTX::STV_i8_v4_asi;
2379 Opcode = NVPTX::STV_i16_v4_asi;
2382 Opcode = NVPTX::STV_i32_v4_asi;
2385 Opcode = NVPTX::STV_f32_v4_asi;
2392 }
else if (
TM.is64Bit() ? SelectADDRri64(N2.
getNode(), N2, Base, Offset)
2393 : SelectADDRri(N2.
getNode(), N2, Base, Offset)) {
2403 Opcode = NVPTX::STV_i8_v2_ari_64;
2406 Opcode = NVPTX::STV_i16_v2_ari_64;
2409 Opcode = NVPTX::STV_i32_v2_ari_64;
2412 Opcode = NVPTX::STV_i64_v2_ari_64;
2415 Opcode = NVPTX::STV_f32_v2_ari_64;
2418 Opcode = NVPTX::STV_f64_v2_ari_64;
2427 Opcode = NVPTX::STV_i8_v4_ari_64;
2430 Opcode = NVPTX::STV_i16_v4_ari_64;
2433 Opcode = NVPTX::STV_i32_v4_ari_64;
2436 Opcode = NVPTX::STV_f32_v4_ari_64;
2450 Opcode = NVPTX::STV_i8_v2_ari;
2453 Opcode = NVPTX::STV_i16_v2_ari;
2456 Opcode = NVPTX::STV_i32_v2_ari;
2459 Opcode = NVPTX::STV_i64_v2_ari;
2462 Opcode = NVPTX::STV_f32_v2_ari;
2465 Opcode = NVPTX::STV_f64_v2_ari;
2474 Opcode = NVPTX::STV_i8_v4_ari;
2477 Opcode = NVPTX::STV_i16_v4_ari;
2480 Opcode = NVPTX::STV_i32_v4_ari;
2483 Opcode = NVPTX::STV_f32_v4_ari;
2501 Opcode = NVPTX::STV_i8_v2_areg_64;
2504 Opcode = NVPTX::STV_i16_v2_areg_64;
2507 Opcode = NVPTX::STV_i32_v2_areg_64;
2510 Opcode = NVPTX::STV_i64_v2_areg_64;
2513 Opcode = NVPTX::STV_f32_v2_areg_64;
2516 Opcode = NVPTX::STV_f64_v2_areg_64;
2525 Opcode = NVPTX::STV_i8_v4_areg_64;
2528 Opcode = NVPTX::STV_i16_v4_areg_64;
2531 Opcode = NVPTX::STV_i32_v4_areg_64;
2534 Opcode = NVPTX::STV_f32_v4_areg_64;
2548 Opcode = NVPTX::STV_i8_v2_areg;
2551 Opcode = NVPTX::STV_i16_v2_areg;
2554 Opcode = NVPTX::STV_i32_v2_areg;
2557 Opcode = NVPTX::STV_i64_v2_areg;
2560 Opcode = NVPTX::STV_f32_v2_areg;
2563 Opcode = NVPTX::STV_f64_v2_areg;
2572 Opcode = NVPTX::STV_i8_v4_areg;
2575 Opcode = NVPTX::STV_i16_v4_areg;
2578 Opcode = NVPTX::STV_i32_v4_areg;
2581 Opcode = NVPTX::STV_f32_v4_areg;
2592 ST = CurDAG->getMachineNode(Opcode, DL,
MVT::Other, StOps);
2595 MemRefs0[0] = cast<MemSDNode>(
N)->getMemOperand();
2596 cast<MachineSDNode>(
ST)->setMemRefs(MemRefs0, MemRefs0 + 1);
2601 SDNode *NVPTXDAGToDAGISel::SelectLoadParam(
SDNode *Node) {
2636 Opc = NVPTX::LoadParamMemI8;
2639 Opc = NVPTX::LoadParamMemI8;
2642 Opc = NVPTX::LoadParamMemI16;
2645 Opc = NVPTX::LoadParamMemI32;
2648 Opc = NVPTX::LoadParamMemI64;
2651 Opc = NVPTX::LoadParamMemF32;
2654 Opc = NVPTX::LoadParamMemF64;
2663 Opc = NVPTX::LoadParamMemV2I8;
2666 Opc = NVPTX::LoadParamMemV2I8;
2669 Opc = NVPTX::LoadParamMemV2I16;
2672 Opc = NVPTX::LoadParamMemV2I32;
2675 Opc = NVPTX::LoadParamMemV2I64;
2678 Opc = NVPTX::LoadParamMemV2F32;
2681 Opc = NVPTX::LoadParamMemV2F64;
2690 Opc = NVPTX::LoadParamMemV4I8;
2693 Opc = NVPTX::LoadParamMemV4I8;
2696 Opc = NVPTX::LoadParamMemV4I16;
2699 Opc = NVPTX::LoadParamMemV4I32;
2702 Opc = NVPTX::LoadParamMemV4F32;
2710 VTs = CurDAG->getVTList(EltVT,
MVT::Other, MVT::Glue);
2711 }
else if (VecSize == 2) {
2712 VTs = CurDAG->getVTList(EltVT, EltVT,
MVT::Other, MVT::Glue);
2715 VTs = CurDAG->getVTList(EVTs);
2718 unsigned OffsetVal = cast<ConstantSDNode>(Offset)->getZExtValue();
2721 Ops.
push_back(CurDAG->getTargetConstant(OffsetVal, DL, MVT::i32));
2725 return CurDAG->getMachineNode(Opc, DL, VTs, Ops);
2728 SDNode *NVPTXDAGToDAGISel::SelectStoreRetval(
SDNode *N) {
2732 unsigned OffsetVal = cast<ConstantSDNode>(Offset)->getZExtValue();
2736 unsigned NumElts = 1;
2753 for (
unsigned i = 0; i < NumElts; ++i)
2755 Ops.
push_back(CurDAG->getTargetConstant(OffsetVal, DL, MVT::i32));
2761 unsigned Opcode = 0;
2770 Opcode = NVPTX::StoreRetvalI8;
2773 Opcode = NVPTX::StoreRetvalI8;
2776 Opcode = NVPTX::StoreRetvalI16;
2779 Opcode = NVPTX::StoreRetvalI32;
2782 Opcode = NVPTX::StoreRetvalI64;
2785 Opcode = NVPTX::StoreRetvalF32;
2788 Opcode = NVPTX::StoreRetvalF64;
2797 Opcode = NVPTX::StoreRetvalV2I8;
2800 Opcode = NVPTX::StoreRetvalV2I8;
2803 Opcode = NVPTX::StoreRetvalV2I16;
2806 Opcode = NVPTX::StoreRetvalV2I32;
2809 Opcode = NVPTX::StoreRetvalV2I64;
2812 Opcode = NVPTX::StoreRetvalV2F32;
2815 Opcode = NVPTX::StoreRetvalV2F64;
2824 Opcode = NVPTX::StoreRetvalV4I8;
2827 Opcode = NVPTX::StoreRetvalV4I8;
2830 Opcode = NVPTX::StoreRetvalV4I16;
2833 Opcode = NVPTX::StoreRetvalV4I32;
2836 Opcode = NVPTX::StoreRetvalV4F32;
2843 CurDAG->getMachineNode(Opcode, DL,
MVT::Other, Ops);
2845 MemRefs0[0] = cast<MemSDNode>(
N)->getMemOperand();
2846 cast<MachineSDNode>(
Ret)->setMemRefs(MemRefs0, MemRefs0 + 1);
2851 SDNode *NVPTXDAGToDAGISel::SelectStoreParam(
SDNode *N) {
2855 unsigned ParamVal = cast<ConstantSDNode>(Param)->getZExtValue();
2857 unsigned OffsetVal = cast<ConstantSDNode>(Offset)->getZExtValue();
2862 unsigned NumElts = 1;
2881 for (
unsigned i = 0; i < NumElts; ++i)
2883 Ops.
push_back(CurDAG->getTargetConstant(ParamVal, DL, MVT::i32));
2884 Ops.
push_back(CurDAG->getTargetConstant(OffsetVal, DL, MVT::i32));
2891 unsigned Opcode = 0;
2902 Opcode = NVPTX::StoreParamI8;
2905 Opcode = NVPTX::StoreParamI8;
2908 Opcode = NVPTX::StoreParamI16;
2911 Opcode = NVPTX::StoreParamI32;
2914 Opcode = NVPTX::StoreParamI64;
2917 Opcode = NVPTX::StoreParamF32;
2920 Opcode = NVPTX::StoreParamF64;
2929 Opcode = NVPTX::StoreParamV2I8;
2932 Opcode = NVPTX::StoreParamV2I8;
2935 Opcode = NVPTX::StoreParamV2I16;
2938 Opcode = NVPTX::StoreParamV2I32;
2941 Opcode = NVPTX::StoreParamV2I64;
2944 Opcode = NVPTX::StoreParamV2F32;
2947 Opcode = NVPTX::StoreParamV2F64;
2956 Opcode = NVPTX::StoreParamV4I8;
2959 Opcode = NVPTX::StoreParamV4I8;
2962 Opcode = NVPTX::StoreParamV4I16;
2965 Opcode = NVPTX::StoreParamV4I32;
2968 Opcode = NVPTX::StoreParamV4F32;
2978 Opcode = NVPTX::StoreParamI32;
2981 SDNode *Cvt = CurDAG->getMachineNode(NVPTX::CVT_u32_u16, DL,
2982 MVT::i32, Ops[0], CvtNone);
2987 Opcode = NVPTX::StoreParamI32;
2990 SDNode *Cvt = CurDAG->getMachineNode(NVPTX::CVT_s32_s16, DL,
2991 MVT::i32, Ops[0], CvtNone);
2999 CurDAG->getMachineNode(Opcode, DL, RetVTs, Ops);
3001 MemRefs0[0] = cast<MemSDNode>(
N)->getMemOperand();
3002 cast<MachineSDNode>(
Ret)->setMemRefs(MemRefs0, MemRefs0 + 1);
3007 SDNode *NVPTXDAGToDAGISel::SelectTextureIntrinsic(
SDNode *N) {
3014 default:
return nullptr;
3016 Opc = NVPTX::TEX_1D_F32_S32;
3019 Opc = NVPTX::TEX_1D_F32_F32;
3022 Opc = NVPTX::TEX_1D_F32_F32_LEVEL;
3025 Opc = NVPTX::TEX_1D_F32_F32_GRAD;
3028 Opc = NVPTX::TEX_1D_S32_S32;
3031 Opc = NVPTX::TEX_1D_S32_F32;
3034 Opc = NVPTX::TEX_1D_S32_F32_LEVEL;
3037 Opc = NVPTX::TEX_1D_S32_F32_GRAD;
3040 Opc = NVPTX::TEX_1D_U32_S32;
3043 Opc = NVPTX::TEX_1D_U32_F32;
3046 Opc = NVPTX::TEX_1D_U32_F32_LEVEL;
3049 Opc = NVPTX::TEX_1D_U32_F32_GRAD;
3052 Opc = NVPTX::TEX_1D_ARRAY_F32_S32;
3055 Opc = NVPTX::TEX_1D_ARRAY_F32_F32;
3058 Opc = NVPTX::TEX_1D_ARRAY_F32_F32_LEVEL;
3061 Opc = NVPTX::TEX_1D_ARRAY_F32_F32_GRAD;
3064 Opc = NVPTX::TEX_1D_ARRAY_S32_S32;
3067 Opc = NVPTX::TEX_1D_ARRAY_S32_F32;
3070 Opc = NVPTX::TEX_1D_ARRAY_S32_F32_LEVEL;
3073 Opc = NVPTX::TEX_1D_ARRAY_S32_F32_GRAD;
3076 Opc = NVPTX::TEX_1D_ARRAY_U32_S32;
3079 Opc = NVPTX::TEX_1D_ARRAY_U32_F32;
3082 Opc = NVPTX::TEX_1D_ARRAY_U32_F32_LEVEL;
3085 Opc = NVPTX::TEX_1D_ARRAY_U32_F32_GRAD;
3088 Opc = NVPTX::TEX_2D_F32_S32;
3091 Opc = NVPTX::TEX_2D_F32_F32;
3094 Opc = NVPTX::TEX_2D_F32_F32_LEVEL;
3097 Opc = NVPTX::TEX_2D_F32_F32_GRAD;
3100 Opc = NVPTX::TEX_2D_S32_S32;
3103 Opc = NVPTX::TEX_2D_S32_F32;
3106 Opc = NVPTX::TEX_2D_S32_F32_LEVEL;
3109 Opc = NVPTX::TEX_2D_S32_F32_GRAD;
3112 Opc = NVPTX::TEX_2D_U32_S32;
3115 Opc = NVPTX::TEX_2D_U32_F32;
3118 Opc = NVPTX::TEX_2D_U32_F32_LEVEL;
3121 Opc = NVPTX::TEX_2D_U32_F32_GRAD;
3124 Opc = NVPTX::TEX_2D_ARRAY_F32_S32;
3127 Opc = NVPTX::TEX_2D_ARRAY_F32_F32;
3130 Opc = NVPTX::TEX_2D_ARRAY_F32_F32_LEVEL;
3133 Opc = NVPTX::TEX_2D_ARRAY_F32_F32_GRAD;
3136 Opc = NVPTX::TEX_2D_ARRAY_S32_S32;
3139 Opc = NVPTX::TEX_2D_ARRAY_S32_F32;
3142 Opc = NVPTX::TEX_2D_ARRAY_S32_F32_LEVEL;
3145 Opc = NVPTX::TEX_2D_ARRAY_S32_F32_GRAD;
3148 Opc = NVPTX::TEX_2D_ARRAY_U32_S32;
3151 Opc = NVPTX::TEX_2D_ARRAY_U32_F32;
3154 Opc = NVPTX::TEX_2D_ARRAY_U32_F32_LEVEL;
3157 Opc = NVPTX::TEX_2D_ARRAY_U32_F32_GRAD;
3160 Opc = NVPTX::TEX_3D_F32_S32;
3163 Opc = NVPTX::TEX_3D_F32_F32;
3166 Opc = NVPTX::TEX_3D_F32_F32_LEVEL;
3169 Opc = NVPTX::TEX_3D_F32_F32_GRAD;
3172 Opc = NVPTX::TEX_3D_S32_S32;
3175 Opc = NVPTX::TEX_3D_S32_F32;
3178 Opc = NVPTX::TEX_3D_S32_F32_LEVEL;
3181 Opc = NVPTX::TEX_3D_S32_F32_GRAD;
3184 Opc = NVPTX::TEX_3D_U32_S32;
3187 Opc = NVPTX::TEX_3D_U32_F32;
3190 Opc = NVPTX::TEX_3D_U32_F32_LEVEL;
3193 Opc = NVPTX::TEX_3D_U32_F32_GRAD;
3196 Opc = NVPTX::TEX_CUBE_F32_F32;
3199 Opc = NVPTX::TEX_CUBE_F32_F32_LEVEL;
3202 Opc = NVPTX::TEX_CUBE_S32_F32;
3205 Opc = NVPTX::TEX_CUBE_S32_F32_LEVEL;
3208 Opc = NVPTX::TEX_CUBE_U32_F32;
3211 Opc = NVPTX::TEX_CUBE_U32_F32_LEVEL;
3214 Opc = NVPTX::TEX_CUBE_ARRAY_F32_F32;
3217 Opc = NVPTX::TEX_CUBE_ARRAY_F32_F32_LEVEL;
3220 Opc = NVPTX::TEX_CUBE_ARRAY_S32_F32;
3223 Opc = NVPTX::TEX_CUBE_ARRAY_S32_F32_LEVEL;
3226 Opc = NVPTX::TEX_CUBE_ARRAY_U32_F32;
3229 Opc = NVPTX::TEX_CUBE_ARRAY_U32_F32_LEVEL;
3232 Opc = NVPTX::TLD4_R_2D_F32_F32;
3235 Opc = NVPTX::TLD4_G_2D_F32_F32;
3238 Opc = NVPTX::TLD4_B_2D_F32_F32;
3241 Opc = NVPTX::TLD4_A_2D_F32_F32;
3244 Opc = NVPTX::TLD4_R_2D_S32_F32;
3247 Opc = NVPTX::TLD4_G_2D_S32_F32;
3250 Opc = NVPTX::TLD4_B_2D_S32_F32;
3253 Opc = NVPTX::TLD4_A_2D_S32_F32;
3256 Opc = NVPTX::TLD4_R_2D_U32_F32;
3259 Opc = NVPTX::TLD4_G_2D_U32_F32;
3262 Opc = NVPTX::TLD4_B_2D_U32_F32;
3265 Opc = NVPTX::TLD4_A_2D_U32_F32;
3268 Opc = NVPTX::TEX_UNIFIED_1D_F32_S32;
3271 Opc = NVPTX::TEX_UNIFIED_1D_F32_F32;
3274 Opc = NVPTX::TEX_UNIFIED_1D_F32_F32_LEVEL;
3277 Opc = NVPTX::TEX_UNIFIED_1D_F32_F32_GRAD;
3280 Opc = NVPTX::TEX_UNIFIED_1D_S32_S32;
3283 Opc = NVPTX::TEX_UNIFIED_1D_S32_F32;
3286 Opc = NVPTX::TEX_UNIFIED_1D_S32_F32_LEVEL;
3289 Opc = NVPTX::TEX_UNIFIED_1D_S32_F32_GRAD;
3292 Opc = NVPTX::TEX_UNIFIED_1D_U32_S32;
3295 Opc = NVPTX::TEX_UNIFIED_1D_U32_F32;
3298 Opc = NVPTX::TEX_UNIFIED_1D_U32_F32_LEVEL;
3301 Opc = NVPTX::TEX_UNIFIED_1D_U32_F32_GRAD;
3304 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_F32_S32;
3307 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_F32_F32;
3310 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_F32_F32_LEVEL;
3313 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_F32_F32_GRAD;
3316 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_S32_S32;
3319 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_S32_F32;
3322 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_S32_F32_LEVEL;
3325 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_S32_F32_GRAD;
3328 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_U32_S32;
3331 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_U32_F32;
3334 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_U32_F32_LEVEL;
3337 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_U32_F32_GRAD;
3340 Opc = NVPTX::TEX_UNIFIED_2D_F32_S32;
3343 Opc = NVPTX::TEX_UNIFIED_2D_F32_F32;
3346 Opc = NVPTX::TEX_UNIFIED_2D_F32_F32_LEVEL;
3349 Opc = NVPTX::TEX_UNIFIED_2D_F32_F32_GRAD;
3352 Opc = NVPTX::TEX_UNIFIED_2D_S32_S32;
3355 Opc = NVPTX::TEX_UNIFIED_2D_S32_F32;
3358 Opc = NVPTX::TEX_UNIFIED_2D_S32_F32_LEVEL;
3361 Opc = NVPTX::TEX_UNIFIED_2D_S32_F32_GRAD;
3364 Opc = NVPTX::TEX_UNIFIED_2D_U32_S32;
3367 Opc = NVPTX::TEX_UNIFIED_2D_U32_F32;
3370 Opc = NVPTX::TEX_UNIFIED_2D_U32_F32_LEVEL;
3373 Opc = NVPTX::TEX_UNIFIED_2D_U32_F32_GRAD;
3376 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_F32_S32;
3379 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_F32_F32;
3382 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_F32_F32_LEVEL;
3385 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_F32_F32_GRAD;
3388 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_S32_S32;
3391 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_S32_F32;
3394 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_S32_F32_LEVEL;
3397 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_S32_F32_GRAD;
3400 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_U32_S32;
3403 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_U32_F32;
3406 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_U32_F32_LEVEL;
3409 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_U32_F32_GRAD;
3412 Opc = NVPTX::TEX_UNIFIED_3D_F32_S32;
3415 Opc = NVPTX::TEX_UNIFIED_3D_F32_F32;
3418 Opc = NVPTX::TEX_UNIFIED_3D_F32_F32_LEVEL;
3421 Opc = NVPTX::TEX_UNIFIED_3D_F32_F32_GRAD;
3424 Opc = NVPTX::TEX_UNIFIED_3D_S32_S32;
3427 Opc = NVPTX::TEX_UNIFIED_3D_S32_F32;
3430 Opc = NVPTX::TEX_UNIFIED_3D_S32_F32_LEVEL;
3433 Opc = NVPTX::TEX_UNIFIED_3D_S32_F32_GRAD;
3436 Opc = NVPTX::TEX_UNIFIED_3D_U32_S32;
3439 Opc = NVPTX::TEX_UNIFIED_3D_U32_F32;
3442 Opc = NVPTX::TEX_UNIFIED_3D_U32_F32_LEVEL;
3445 Opc = NVPTX::TEX_UNIFIED_3D_U32_F32_GRAD;
3448 Opc = NVPTX::TEX_UNIFIED_CUBE_F32_F32;
3451 Opc = NVPTX::TEX_UNIFIED_CUBE_F32_F32_LEVEL;
3454 Opc = NVPTX::TEX_UNIFIED_CUBE_S32_F32;
3457 Opc = NVPTX::TEX_UNIFIED_CUBE_S32_F32_LEVEL;
3460 Opc = NVPTX::TEX_UNIFIED_CUBE_U32_F32;
3463 Opc = NVPTX::TEX_UNIFIED_CUBE_U32_F32_LEVEL;
3466 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_F32_F32;
3469 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_F32_F32_LEVEL;
3472 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_S32_F32;
3475 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_S32_F32_LEVEL;
3478 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_U32_F32;
3481 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_U32_F32_LEVEL;
3484 Opc = NVPTX::TLD4_UNIFIED_R_2D_F32_F32;
3487 Opc = NVPTX::TLD4_UNIFIED_G_2D_F32_F32;
3490 Opc = NVPTX::TLD4_UNIFIED_B_2D_F32_F32;
3493 Opc = NVPTX::TLD4_UNIFIED_A_2D_F32_F32;
3496 Opc = NVPTX::TLD4_UNIFIED_R_2D_S32_F32;
3499 Opc = NVPTX::TLD4_UNIFIED_G_2D_S32_F32;
3502 Opc = NVPTX::TLD4_UNIFIED_B_2D_S32_F32;
3505 Opc = NVPTX::TLD4_UNIFIED_A_2D_S32_F32;
3508 Opc = NVPTX::TLD4_UNIFIED_R_2D_U32_F32;
3511 Opc = NVPTX::TLD4_UNIFIED_G_2D_U32_F32;
3514 Opc = NVPTX::TLD4_UNIFIED_B_2D_U32_F32;
3517 Opc = NVPTX::TLD4_UNIFIED_A_2D_U32_F32;
3527 Ret = CurDAG->getMachineNode(Opc,
SDLoc(N), N->
getVTList(), Ops);
3531 SDNode *NVPTXDAGToDAGISel::SelectSurfaceIntrinsic(
SDNode *N) {
3538 default:
return nullptr;
3540 Opc = NVPTX::SULD_1D_I8_CLAMP;
3546 Opc = NVPTX::SULD_1D_I16_CLAMP;
3552 Opc = NVPTX::SULD_1D_I32_CLAMP;
3558 Opc = NVPTX::SULD_1D_I64_CLAMP;
3564 Opc = NVPTX::SULD_1D_V2I8_CLAMP;
3570 Opc = NVPTX::SULD_1D_V2I16_CLAMP;
3576 Opc = NVPTX::SULD_1D_V2I32_CLAMP;
3582 Opc = NVPTX::SULD_1D_V2I64_CLAMP;
3588 Opc = NVPTX::SULD_1D_V4I8_CLAMP;
3594 Opc = NVPTX::SULD_1D_V4I16_CLAMP;
3600 Opc = NVPTX::SULD_1D_V4I32_CLAMP;
3606 Opc = NVPTX::SULD_1D_ARRAY_I8_CLAMP;
3613 Opc = NVPTX::SULD_1D_ARRAY_I16_CLAMP;
3620 Opc = NVPTX::SULD_1D_ARRAY_I32_CLAMP;
3627 Opc = NVPTX::SULD_1D_ARRAY_I64_CLAMP;
3634 Opc = NVPTX::SULD_1D_ARRAY_V2I8_CLAMP;
3641 Opc = NVPTX::SULD_1D_ARRAY_V2I16_CLAMP;
3648 Opc = NVPTX::SULD_1D_ARRAY_V2I32_CLAMP;
3655 Opc = NVPTX::SULD_1D_ARRAY_V2I64_CLAMP;
3662 Opc = NVPTX::SULD_1D_ARRAY_V4I8_CLAMP;
3669 Opc = NVPTX::SULD_1D_ARRAY_V4I16_CLAMP;
3676 Opc = NVPTX::SULD_1D_ARRAY_V4I32_CLAMP;
3683 Opc = NVPTX::SULD_2D_I8_CLAMP;
3690 Opc = NVPTX::SULD_2D_I16_CLAMP;
3697 Opc = NVPTX::SULD_2D_I32_CLAMP;
3704 Opc = NVPTX::SULD_2D_I64_CLAMP;
3711 Opc = NVPTX::SULD_2D_V2I8_CLAMP;
3718 Opc = NVPTX::SULD_2D_V2I16_CLAMP;
3725 Opc = NVPTX::SULD_2D_V2I32_CLAMP;
3732 Opc = NVPTX::SULD_2D_V2I64_CLAMP;
3739 Opc = NVPTX::SULD_2D_V4I8_CLAMP;
3746 Opc = NVPTX::SULD_2D_V4I16_CLAMP;
3753 Opc = NVPTX::SULD_2D_V4I32_CLAMP;
3760 Opc = NVPTX::SULD_2D_ARRAY_I8_CLAMP;
3768 Opc = NVPTX::SULD_2D_ARRAY_I16_CLAMP;
3776 Opc = NVPTX::SULD_2D_ARRAY_I32_CLAMP;
3784 Opc = NVPTX::SULD_2D_ARRAY_I64_CLAMP;
3792 Opc = NVPTX::SULD_2D_ARRAY_V2I8_CLAMP;
3800 Opc = NVPTX::SULD_2D_ARRAY_V2I16_CLAMP;
3808 Opc = NVPTX::SULD_2D_ARRAY_V2I32_CLAMP;
3816 Opc = NVPTX::SULD_2D_ARRAY_V2I64_CLAMP;
3824 Opc = NVPTX::SULD_2D_ARRAY_V4I8_CLAMP;
3832 Opc = NVPTX::SULD_2D_ARRAY_V4I16_CLAMP;
3840 Opc = NVPTX::SULD_2D_ARRAY_V4I32_CLAMP;
3848 Opc = NVPTX::SULD_3D_I8_CLAMP;
3856 Opc = NVPTX::SULD_3D_I16_CLAMP;
3864 Opc = NVPTX::SULD_3D_I32_CLAMP;
3872 Opc = NVPTX::SULD_3D_I64_CLAMP;
3880 Opc = NVPTX::SULD_3D_V2I8_CLAMP;
3888 Opc = NVPTX::SULD_3D_V2I16_CLAMP;
3896 Opc = NVPTX::SULD_3D_V2I32_CLAMP;
3904 Opc = NVPTX::SULD_3D_V2I64_CLAMP;
3912 Opc = NVPTX::SULD_3D_V4I8_CLAMP;
3920 Opc = NVPTX::SULD_3D_V4I16_CLAMP;
3928 Opc = NVPTX::SULD_3D_V4I32_CLAMP;
3936 Opc = NVPTX::SULD_1D_I8_TRAP;
3942 Opc = NVPTX::SULD_1D_I16_TRAP;
3948 Opc = NVPTX::SULD_1D_I32_TRAP;
3954 Opc = NVPTX::SULD_1D_I64_TRAP;
3960 Opc = NVPTX::SULD_1D_V2I8_TRAP;
3966 Opc = NVPTX::SULD_1D_V2I16_TRAP;
3972 Opc = NVPTX::SULD_1D_V2I32_TRAP;
3978 Opc = NVPTX::SULD_1D_V2I64_TRAP;
3984 Opc = NVPTX::SULD_1D_V4I8_TRAP;
3990 Opc = NVPTX::SULD_1D_V4I16_TRAP;
3996 Opc = NVPTX::SULD_1D_V4I32_TRAP;
4002 Opc = NVPTX::SULD_1D_ARRAY_I8_TRAP;
4009 Opc = NVPTX::SULD_1D_ARRAY_I16_TRAP;
4016 Opc = NVPTX::SULD_1D_ARRAY_I32_TRAP;
4023 Opc = NVPTX::SULD_1D_ARRAY_I64_TRAP;
4030 Opc = NVPTX::SULD_1D_ARRAY_V2I8_TRAP;
4037 Opc = NVPTX::SULD_1D_ARRAY_V2I16_TRAP;
4044 Opc = NVPTX::SULD_1D_ARRAY_V2I32_TRAP;
4051 Opc = NVPTX::SULD_1D_ARRAY_V2I64_TRAP;
4058 Opc = NVPTX::SULD_1D_ARRAY_V4I8_TRAP;
4065 Opc = NVPTX::SULD_1D_ARRAY_V4I16_TRAP;
4072 Opc = NVPTX::SULD_1D_ARRAY_V4I32_TRAP;
4079 Opc = NVPTX::SULD_2D_I8_TRAP;
4086 Opc = NVPTX::SULD_2D_I16_TRAP;
4093 Opc = NVPTX::SULD_2D_I32_TRAP;
4100 Opc = NVPTX::SULD_2D_I64_TRAP;
4107 Opc = NVPTX::SULD_2D_V2I8_TRAP;
4114 Opc = NVPTX::SULD_2D_V2I16_TRAP;
4121 Opc = NVPTX::SULD_2D_V2I32_TRAP;
4128 Opc = NVPTX::SULD_2D_V2I64_TRAP;
4135 Opc = NVPTX::SULD_2D_V4I8_TRAP;
4142 Opc = NVPTX::SULD_2D_V4I16_TRAP;
4149 Opc = NVPTX::SULD_2D_V4I32_TRAP;
4156 Opc = NVPTX::SULD_2D_ARRAY_I8_TRAP;
4164 Opc = NVPTX::SULD_2D_ARRAY_I16_TRAP;
4172 Opc = NVPTX::SULD_2D_ARRAY_I32_TRAP;
4180 Opc = NVPTX::SULD_2D_ARRAY_I64_TRAP;
4188 Opc = NVPTX::SULD_2D_ARRAY_V2I8_TRAP;
4196 Opc = NVPTX::SULD_2D_ARRAY_V2I16_TRAP;
4204 Opc = NVPTX::SULD_2D_ARRAY_V2I32_TRAP;
4212 Opc = NVPTX::SULD_2D_ARRAY_V2I64_TRAP;
4220 Opc = NVPTX::SULD_2D_ARRAY_V4I8_TRAP;
4228 Opc = NVPTX::SULD_2D_ARRAY_V4I16_TRAP;
4236 Opc = NVPTX::SULD_2D_ARRAY_V4I32_TRAP;
4244 Opc = NVPTX::SULD_3D_I8_TRAP;
4252 Opc = NVPTX::SULD_3D_I16_TRAP;
4260 Opc = NVPTX::SULD_3D_I32_TRAP;
4268 Opc = NVPTX::SULD_3D_I64_TRAP;
4276 Opc = NVPTX::SULD_3D_V2I8_TRAP;
4284 Opc = NVPTX::SULD_3D_V2I16_TRAP;
4292 Opc = NVPTX::SULD_3D_V2I32_TRAP;
4300 Opc = NVPTX::SULD_3D_V2I64_TRAP;
4308 Opc = NVPTX::SULD_3D_V4I8_TRAP;
4316 Opc = NVPTX::SULD_3D_V4I16_TRAP;
4324 Opc = NVPTX::SULD_3D_V4I32_TRAP;
4332 Opc = NVPTX::SULD_1D_I8_ZERO;
4338 Opc = NVPTX::SULD_1D_I16_ZERO;
4344 Opc = NVPTX::SULD_1D_I32_ZERO;
4350 Opc = NVPTX::SULD_1D_I64_ZERO;
4356 Opc = NVPTX::SULD_1D_V2I8_ZERO;
4362 Opc = NVPTX::SULD_1D_V2I16_ZERO;
4368 Opc = NVPTX::SULD_1D_V2I32_ZERO;
4374 Opc = NVPTX::SULD_1D_V2I64_ZERO;
4380 Opc = NVPTX::SULD_1D_V4I8_ZERO;
4386 Opc = NVPTX::SULD_1D_V4I16_ZERO;
4392 Opc = NVPTX::SULD_1D_V4I32_ZERO;
4398 Opc = NVPTX::SULD_1D_ARRAY_I8_ZERO;
4405 Opc = NVPTX::SULD_1D_ARRAY_I16_ZERO;
4412 Opc = NVPTX::SULD_1D_ARRAY_I32_ZERO;
4419 Opc = NVPTX::SULD_1D_ARRAY_I64_ZERO;
4426 Opc = NVPTX::SULD_1D_ARRAY_V2I8_ZERO;
4433 Opc = NVPTX::SULD_1D_ARRAY_V2I16_ZERO;
4440 Opc = NVPTX::SULD_1D_ARRAY_V2I32_ZERO;
4447 Opc = NVPTX::SULD_1D_ARRAY_V2I64_ZERO;
4454 Opc = NVPTX::SULD_1D_ARRAY_V4I8_ZERO;
4461 Opc = NVPTX::SULD_1D_ARRAY_V4I16_ZERO;
4468 Opc = NVPTX::SULD_1D_ARRAY_V4I32_ZERO;
4475 Opc = NVPTX::SULD_2D_I8_ZERO;
4482 Opc = NVPTX::SULD_2D_I16_ZERO;
4489 Opc = NVPTX::SULD_2D_I32_ZERO;
4496 Opc = NVPTX::SULD_2D_I64_ZERO;
4503 Opc = NVPTX::SULD_2D_V2I8_ZERO;
4510 Opc = NVPTX::SULD_2D_V2I16_ZERO;
4517 Opc = NVPTX::SULD_2D_V2I32_ZERO;
4524 Opc = NVPTX::SULD_2D_V2I64_ZERO;
4531 Opc = NVPTX::SULD_2D_V4I8_ZERO;
4538 Opc = NVPTX::SULD_2D_V4I16_ZERO;
4545 Opc = NVPTX::SULD_2D_V4I32_ZERO;
4552 Opc = NVPTX::SULD_2D_ARRAY_I8_ZERO;
4560 Opc = NVPTX::SULD_2D_ARRAY_I16_ZERO;
4568 Opc = NVPTX::SULD_2D_ARRAY_I32_ZERO;
4576 Opc = NVPTX::SULD_2D_ARRAY_I64_ZERO;
4584 Opc = NVPTX::SULD_2D_ARRAY_V2I8_ZERO;
4592 Opc = NVPTX::SULD_2D_ARRAY_V2I16_ZERO;
4600 Opc = NVPTX::SULD_2D_ARRAY_V2I32_ZERO;
4608 Opc = NVPTX::SULD_2D_ARRAY_V2I64_ZERO;
4616 Opc = NVPTX::SULD_2D_ARRAY_V4I8_ZERO;
4624 Opc = NVPTX::SULD_2D_ARRAY_V4I16_ZERO;
4632 Opc = NVPTX::SULD_2D_ARRAY_V4I32_ZERO;
4640 Opc = NVPTX::SULD_3D_I8_ZERO;
4648 Opc = NVPTX::SULD_3D_I16_ZERO;
4656 Opc = NVPTX::SULD_3D_I32_ZERO;
4664 Opc = NVPTX::SULD_3D_I64_ZERO;
4672 Opc = NVPTX::SULD_3D_V2I8_ZERO;
4680 Opc = NVPTX::SULD_3D_V2I16_ZERO;
4688 Opc = NVPTX::SULD_3D_V2I32_ZERO;
4696 Opc = NVPTX::SULD_3D_V2I64_ZERO;
4704 Opc = NVPTX::SULD_3D_V4I8_ZERO;
4712 Opc = NVPTX::SULD_3D_V4I16_ZERO;
4720 Opc = NVPTX::SULD_3D_V4I32_ZERO;
4728 Ret = CurDAG->getMachineNode(Opc,
SDLoc(N), N->
getVTList(), Ops);
4742 bool IsSigned =
false;
4747 if (isa<ConstantSDNode>(LHS) && !isa<ConstantSDNode>(RHS)) {
4768 Len = CurDAG->getTargetConstant(NumBits, DL, MVT::i32);
4780 if (NumBits > GoodBits) {
4786 Start = CurDAG->getTargetConstant(StartVal, DL, MVT::i32);
4814 if (isa<ConstantSDNode>(AndLHS)) {
4838 NumBits = NumZeros + NumOnes - ShiftAmt;
4844 if (ShiftAmt < NumZeros) {
4851 Start = CurDAG->getTargetConstant(ShiftAmt, DL, MVT::i32);
4852 Len = CurDAG->getTargetConstant(NumBits, DL, MVT::i32);
4880 if (OuterShiftAmt < InnerShiftAmt) {
4892 CurDAG->getTargetConstant(OuterShiftAmt - InnerShiftAmt, DL, MVT::i32);
4895 OuterShiftAmt,
DL, MVT::i32);
4917 Opc = NVPTX::BFE_S32rii;
4919 Opc = NVPTX::BFE_U32rii;
4923 Opc = NVPTX::BFE_S64rii;
4925 Opc = NVPTX::BFE_U64rii;
4936 return CurDAG->getMachineNode(Opc, DL, N->
getVTList(), Ops);
4953 unsigned IID = cast<ConstantSDNode>(N.
getOperand(0))->getZExtValue();
4954 if (IID == Intrinsic::nvvm_ptr_gen_to_param)
4962 bool NVPTXDAGToDAGISel::SelectADDRsi_imp(
4967 if (SelectDirectAddr(base, Base)) {
4968 Offset = CurDAG->getTargetConstant(CN->getZExtValue(),
SDLoc(OpNode),
4978 bool NVPTXDAGToDAGISel::SelectADDRsi(
SDNode *OpNode,
SDValue Addr,
4980 return SelectADDRsi_imp(OpNode, Addr, Base, Offset, MVT::i32);
4984 bool NVPTXDAGToDAGISel::SelectADDRsi64(
SDNode *OpNode,
SDValue Addr,
4986 return SelectADDRsi_imp(OpNode, Addr, Base, Offset, MVT::i64);
4990 bool NVPTXDAGToDAGISel::SelectADDRri_imp(
4993 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), mvt);
4994 Offset = CurDAG->getTargetConstant(0,
SDLoc(OpNode), mvt);
5002 if (SelectDirectAddr(Addr.
getOperand(0), Addr)) {
5007 dyn_cast<FrameIndexSDNode>(Addr.
getOperand(0)))
5009 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), mvt);
5012 Offset = CurDAG->getTargetConstant(CN->getZExtValue(),
SDLoc(OpNode),
5021 bool NVPTXDAGToDAGISel::SelectADDRri(
SDNode *OpNode,
SDValue Addr,
5023 return SelectADDRri_imp(OpNode, Addr, Base, Offset, MVT::i32);
5027 bool NVPTXDAGToDAGISel::SelectADDRri64(
SDNode *OpNode,
SDValue Addr,
5029 return SelectADDRri_imp(OpNode, Addr, Base, Offset, MVT::i64);
5032 bool NVPTXDAGToDAGISel::ChkMemSDNodeAddressSpace(
SDNode *N,
5033 unsigned int spN)
const {
5034 const Value *Src =
nullptr;
5035 if (
MemSDNode *mN = dyn_cast<MemSDNode>(N)) {
5036 if (spN == 0 && mN->getMemOperand()->getPseudoValue())
5038 Src = mN->getMemOperand()->getValue();
5043 return (PT->getAddressSpace() == spN);
5049 bool NVPTXDAGToDAGISel::SelectInlineAsmMemoryOperand(
5050 const SDValue &Op,
unsigned ConstraintID, std::vector<SDValue> &OutOps) {
5052 switch (ConstraintID) {
5055 case InlineAsm::Constraint_m:
5056 if (SelectDirectAddr(Op, Op0)) {
5057 OutOps.push_back(Op0);
5058 OutOps.push_back(CurDAG->getTargetConstant(0,
SDLoc(Op), MVT::i32));
5061 if (SelectADDRri(Op.
getNode(), Op, Op0, Op1)) {
5062 OutOps.push_back(Op0);
5063 OutOps.push_back(Op1);
void push_back(const T &Elt)
unsigned getDestAddressSpace() const
SDVTList getVTList() const
unsigned getSrcAddressSpace() const
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
unsigned getSizeInBits() const
static unsigned int getCodeAddrSpace(MemSDNode *N)
TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or anything else with this node...
unsigned getNumOperands() const
Return the number of values used by this operation.
const SDValue & getOperand(unsigned Num) const
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
void setNodeId(int Id)
Set unique node id.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag=true)
Reports a serious error, calling any installed error handler.
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
bool isVector() const
isVector - Return true if this is a vector value type.
MachineMemOperand - A description of a memory reference used in the backend.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Shift and rotation operations.
std::size_t countTrailingOnes(T Value, ZeroBehavior ZB=ZB_Width)
Count the number of ones from the least significant bit to the first zero bit.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
MVT getScalarType() const
getScalarType - If this is a vector type, return the element type, otherwise return this...
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
EVT getVectorElementType() const
getVectorElementType - Given a vector type, return the type of each element.
bool isMask_64(uint64_t Value)
isMask_64 - This function returns true if the argument is a non-empty sequence of ones starting at th...
EVT getMemoryVT() const
Return the type of the in-memory value.
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
PointerType - Class to represent pointers.
This class is used to represent ISD::STORE nodes.
Flag
These should be considered private to the implementation of the MCInstrDesc class.
SDNode * getNode() const
get the SDNode which holds the desired result
initializer< Ty > init(const Ty &Val)
bool allowFMA(MachineFunction &MF, CodeGenOpt::Level OptLevel) const
std::size_t countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the least significant bit to the most stopping at the first 1...
unsigned getVectorNumElements() const
MVT - Machine Value Type.
const SDValue & getOperand(unsigned i) const
bool isVector() const
isVector - Return true if this is a vector value type.
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
static cl::opt< bool > UsePrecSqrtF32("nvptx-prec-sqrtf32", cl::Hidden, cl::desc("NVPTX Specific: 0 use sqrt.approx, 1 use sqrt.rn."), cl::init(true))
static ManagedStatic< std::set< EVT, EVT::compareRawBits > > EVTs
unsigned getOpcode() const
FunctionPass class - This class is used to implement most global optimizations.
EVT - Extended Value Type.
bool isShiftedMask_64(uint64_t Value)
isShiftedMask_64 - This function returns true if the argument contains a non-empty sequence of ones w...
ADDRSPACECAST - This operator converts between pointers of different address spaces.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Type * getType() const
All values are typed, get the type of this value.
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
This is an abstract virtual class for memory operations.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
const Value * getValue() const
getValue - Return the base address of the memory access.
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
static cl::opt< bool > FtzEnabled("nvptx-f32ftz", cl::ZeroOrMore, cl::Hidden, cl::desc("NVPTX Specific: Flush f32 subnormals to sign-preserving zero."), cl::init(false))
static cl::opt< int > UsePrecDivF32("nvptx-prec-divf32", cl::ZeroOrMore, cl::Hidden, cl::desc("NVPTX Specifies: 0 use div.approx, 1 use div.full, 2 use"" IEEE Compliant F32 div.rnd if available."), cl::init(2))
FunctionPass * createNVPTXISelDag(NVPTXTargetMachine &TM, llvm::CodeGenOpt::Level OptLevel)
createNVPTXISelDag - This pass converts a legalized DAG into a NVPTX-specific DAG, ready for instruction scheduling.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
bool isIndexed() const
Return true if this is a pre/post inc/dec load/store.
EVT getValueType() const
Return the ValueType of the referenced return value.
StringRef getValueAsString() const
Return the attribute's value as a string.
LLVM Value Representation.
static bool isVolatile(Instruction *Inst)
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
MVT getSimpleValueType(unsigned ResNo) const
Return the type of a specified result as a simple type.
MachineInstr::mmo_iterator allocateMemRefsArray(unsigned long Num)
allocateMemRefsArray - Allocate an array to hold MachineMemOperand pointers.
MVT getSimpleVT() const
getSimpleVT - Return the SimpleValueType held in the specified simple EVT.
bool isMachineOpcode() const
Test if this node has a post-isel opcode, directly corresponding to a MachineInstr opcode...
uint64_t getZExtValue() const
This class is used to represent ISD::LOAD nodes.