55 std::string
Ret =
"e-p:32:32";
59 Ret +=
"-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64";
62 Ret +=
"-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256"
63 "-v512:512-v1024:1024-v2048:2048-n32:64";
116 return getTM<AMDGPUTargetMachine>();
127 void addIRPasses()
override;
128 void addCodeGenPrepare()
override;
129 virtual bool addPreISel()
override;
130 virtual bool addInstSelector()
override;
133 class R600PassConfig :
public AMDGPUPassConfig {
136 : AMDGPUPassConfig(TM, PM) { }
138 bool addPreISel()
override;
139 void addPreRegAlloc()
override;
140 void addPreSched2()
override;
141 void addPreEmitPass()
override;
144 class GCNPassConfig :
public AMDGPUPassConfig {
147 : AMDGPUPassConfig(TM, PM) { }
148 bool addPreISel()
override;
149 bool addInstSelector()
override;
150 void addPreRegAlloc()
override;
151 void addPostRegAlloc()
override;
152 void addPreSched2()
override;
153 void addPreEmitPass()
override;
165 void AMDGPUPassConfig::addIRPasses() {
178 void AMDGPUPassConfig::addCodeGenPrepare() {
179 const AMDGPUSubtarget &ST = *getAMDGPUTargetMachine().getSubtargetImpl();
188 AMDGPUPassConfig::addPreISel() {
189 const AMDGPUSubtarget &ST = *getAMDGPUTargetMachine().getSubtargetImpl();
196 bool AMDGPUPassConfig::addInstSelector() {
205 bool R600PassConfig::addPreISel() {
206 AMDGPUPassConfig::addPreISel();
211 void R600PassConfig::addPreRegAlloc() {
215 void R600PassConfig::addPreSched2() {
216 const AMDGPUSubtarget &ST = *getAMDGPUTargetMachine().getSubtargetImpl();
223 void R600PassConfig::addPreEmitPass() {
232 return new R600PassConfig(
this, PM);
239 bool GCNPassConfig::addPreISel() {
240 AMDGPUPassConfig::addPreISel();
247 bool GCNPassConfig::addInstSelector() {
248 AMDGPUPassConfig::addInstSelector();
255 void GCNPassConfig::addPreRegAlloc() {
256 const AMDGPUSubtarget &ST = *getAMDGPUTargetMachine().getSubtargetImpl();
280 void GCNPassConfig::addPostRegAlloc() {
285 void GCNPassConfig::addPreSched2() {
288 void GCNPassConfig::addPreEmitPass() {
294 return new GCNPassConfig(
this, PM);
FunctionPass * createSIAnnotateControlFlowPass()
Create the annotation pass.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
TargetLoweringObjectFile * TLOF
static std::string computeDataLayout(const Triple &TT)
Interface definition for R600InstrInfo.
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Target TheGCNTarget
The target for GCN GPUs.
FunctionPass * createSIShrinkInstructionsPass()
char & SILoadStoreOptimizerID
char & RegisterCoalescerID
RegisterCoalescer - This pass merges live ranges to eliminate copies.
Analysis pass providing the TargetTransformInfo.
R600 Machine Scheduler interface.
char & MachineSchedulerID
MachineScheduler - This pass schedules machine instructions.
FunctionPass * createAMDGPUCFGStructurizerPass()
MachineSchedRegistry provides a selection of available machine instruction schedulers.
Pass * createAlwaysInlinerPass()
createAlwaysInlinerPass - Return a new pass object that inlines only functions that are marked as "al...
FunctionPass * createSIInsertWaits(TargetMachine &tm)
bool loadStoreOptEnabled() const
Target TheAMDGPUTarget
The target which suports all AMD GPUs.
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
FunctionPass * createR600TextureIntrinsicsReplacer()
FunctionPass * createR600ExpandSpecialInstrsPass(TargetMachine &tm)
FunctionPass * createSROAPass(bool RequiresDomTree=true)
FunctionPass * createSinkingPass()
char & SIFixControlFlowLiveIntervalsID
char & FinalizeMachineBundlesID
FinalizeMachineBundles - This pass finalize machine instruction bundles (created earlier, e.g.
FunctionPass * createR600VectorRegMerger(TargetMachine &tm)
Target-Independent Code Generator Pass Configuration Options.
FunctionPass * createSITypeRewriter()
FunctionPass * createR600ClauseMergePass(TargetMachine &tm)
FunctionPass * createSILowerControlFlowPass(TargetMachine &tm)
FunctionPass * createSILowerI1CopiesPass()
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
bool isIfCvtEnabled() const
Generation getGeneration() const
FunctionPass * createR600ControlFlowFinalizer(TargetMachine &tm)
FunctionPass * createSIFixSGPRCopiesPass(TargetMachine &tm)
bool IsIRStructurizerEnabled() const
AMDGPUTargetMachine(const Target &T, const Triple &TT, StringRef FS, StringRef CPU, TargetOptions Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL)
FunctionPass * createFlattenCFGPass()
FunctionPass * createAMDGPUISelDag(TargetMachine &tm)
This pass converts a legalized DAG into a AMDGPU-specific.
void LLVMInitializeAMDGPUTarget()
SI DAG Lowering interface definition.
R600TargetMachine(const Target &T, const Triple &TT, StringRef FS, StringRef CPU, TargetOptions Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL)
FunctionPass * createR600Packetizer(TargetMachine &tm)
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang","erlang-compatible garbage collector")
This class describes a target machine that is implemented with the LLVM target-independent code gener...
ModulePass * createBarrierNoopPass()
createBarrierNoopPass - This pass is purely a module pass barrier in a pass manager.
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
FunctionPass * createSIPrepareScratchRegs()
The AMDGPU TargetMachine interface definition for hw codgen targets.
static ScheduleDAGInstrs * createR600MachineScheduler(MachineSchedContext *C)
bool isPromoteAllocaEnabled() const
Triple - Helper class for working with autoconf configuration names.
ModulePass * createAMDGPUAlwaysInlinePass()
GCNTargetMachine(const Target &T, const Triple &TT, StringRef FS, StringRef CPU, TargetOptions Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL)
void setRequiresStructuredCFG(bool Value)
Target - Wrapper for Target specific information.
void initializeSILoadStoreOptimizerPass(PassRegistry &)
ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of MachineInstrs. ...
const DataLayout & getDataLayout() const
Get the data layout for the module's target platform.
Interface definition for SIInstrInfo.
R600 DAG Lowering interface definition.
FunctionPass * createSIFoldOperandsPass()
char & IfConverterID
IfConverter - This pass performs machine code if conversion.
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
TargetIRAnalysis getTargetIRAnalysis() override
Get a TargetIRAnalysis implementation for the target.
FunctionPass * createR600EmitClauseMarkers()
static MachineSchedRegistry SchedCustomRegistry("r600","Run R600's custom scheduler", createR600MachineScheduler)
RegisterTargetMachine - Helper template for registering a target machine implementation, for use in the target machine initialization function.
Module * getParent()
Get the module that this global value is contained inside of...
void initializeSIFixControlFlowLiveIntervalsPass(PassRegistry &)
Pass * createStructurizeCFGPass()
Create the pass.
Primary interface to the complete machine description for the target machine.
FunctionPass * createSIFixSGPRLiveRangesPass()
StringRef - Represent a constant reference to a string, i.e.
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml","ocaml 3.10-compatible collector")
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
FunctionPass * createAMDGPUPromoteAlloca(const AMDGPUSubtarget &ST)