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LLVM
3.7.0
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#include "llvm/CodeGen/SelectionDAG.h"#include "llvm/ADT/SetVector.h"#include "llvm/ADT/SmallBitVector.h"#include "llvm/ADT/SmallPtrSet.h"#include "llvm/ADT/Statistic.h"#include "llvm/Analysis/AliasAnalysis.h"#include "llvm/CodeGen/MachineFrameInfo.h"#include "llvm/CodeGen/MachineFunction.h"#include "llvm/IR/DataLayout.h"#include "llvm/IR/DerivedTypes.h"#include "llvm/IR/Function.h"#include "llvm/IR/LLVMContext.h"#include "llvm/Support/CommandLine.h"#include "llvm/Support/Debug.h"#include "llvm/Support/ErrorHandling.h"#include "llvm/Support/MathExtras.h"#include "llvm/Support/raw_ostream.h"#include "llvm/Target/TargetLowering.h"#include "llvm/Target/TargetOptions.h"#include "llvm/Target/TargetRegisterInfo.h"#include "llvm/Target/TargetSubtargetInfo.h"#include <algorithm>Go to the source code of this file.
Macros | |
| #define | DEBUG_TYPE "dagcombine" |
Functions | |
| STATISTIC (NodesCombined,"Number of dag nodes combined") | |
| STATISTIC (PreIndexedNodes,"Number of pre-indexed nodes created") | |
| STATISTIC (PostIndexedNodes,"Number of post-indexed nodes created") | |
| STATISTIC (OpsNarrowed,"Number of load/op/store narrowed") | |
| STATISTIC (LdStFP2Int,"Number of fp load/store pairs transformed to int") | |
| STATISTIC (SlicedLoads,"Number of load sliced") | |
| static char | isNegatibleForFree (SDValue Op, bool LegalOperations, const TargetLowering &TLI, const TargetOptions *Options, unsigned Depth=0) |
| Return 1 if we can compute the negated form of the specified expression for the same cost as the expression itself, or 2 if we can compute the negated form more cheaply than the expression itself. More... | |
| static SDValue | GetNegatedExpression (SDValue Op, SelectionDAG &DAG, bool LegalOperations, unsigned Depth=0) |
| If isNegatibleForFree returns true, return the newly negated expression. More... | |
| static bool | isConstantSplatVector (SDNode *N, APInt &SplatValue) |
| Returns true if N is a BUILD_VECTOR node whose elements are all the same constant or undefined. More... | |
| static SDNode * | isConstantIntBuildVectorOrConstantInt (SDValue N) |
| static SDNode * | isConstantFPBuildVectorOrConstantFP (SDValue N) |
| static ConstantSDNode * | isConstOrConstSplat (SDValue N) |
| static ConstantFPSDNode * | isConstOrConstSplatFP (SDValue N) |
| static SDValue | getInputChainForNode (SDNode *N) |
| Given a node, return its input chain if it has one, otherwise return a null sd operand. More... | |
| static bool | isNullConstant (SDValue V) |
| static bool | isNullFPConstant (SDValue V) |
| static bool | isAllOnesConstant (SDValue V) |
| static bool | isOneConstant (SDValue V) |
| static ConstantSDNode * | getAsNonOpaqueConstant (SDValue N) |
If N is a ContantSDNode with isOpaque() == false return it casted to a ContantSDNode pointer else nullptr. More... | |
| static SDValue | tryFoldToZero (SDLoc DL, const TargetLowering &TLI, EVT VT, SelectionDAG &DAG, bool LegalOperations, bool LegalTypes) |
| static bool | isBSwapHWordElement (SDValue N, MutableArrayRef< SDNode * > Parts) |
| Return true if the specified node is an element that makes up a 32-bit packed halfword byteswap. More... | |
| static bool | MatchRotateHalf (SDValue Op, SDValue &Shift, SDValue &Mask) |
| Match "(X shl/srl V1) & V2" where V2 may not be present. More... | |
| static bool | matchRotateSub (SDValue Pos, SDValue Neg, unsigned OpSize) |
| static SDValue | combineMinNumMaxNum (SDLoc DL, EVT VT, SDValue LHS, SDValue RHS, SDValue True, SDValue False, ISD::CondCode CC, const TargetLowering &TLI, SelectionDAG &DAG) |
| Generate Min/Max node. More... | |
| static std::pair< SDValue, SDValue > | SplitVSETCC (const SDNode *N, SelectionDAG &DAG) |
| static SDValue | ConvertSelectToConcatVector (SDNode *N, SelectionDAG &DAG) |
| static SDNode * | tryToFoldExtendOfConstant (SDNode *N, const TargetLowering &TLI, SelectionDAG &DAG, bool LegalTypes, bool LegalOperations) |
| Try to fold a sext/zext/aext dag node into a ConstantSDNode or a build_vector of constants. More... | |
| static bool | ExtendUsesToFormExtLoad (SDNode *N, SDValue N0, unsigned ExtOpc, SmallVectorImpl< SDNode * > &ExtendNodes, const TargetLowering &TLI) |
| static bool | isTruncateOf (SelectionDAG &DAG, SDValue N, SDValue &Op, APInt &KnownZero) |
| static SDNode * | getBuildPairElt (SDNode *N, unsigned i) |
| static SDValue | FoldIntToFPToInt (SDNode *N, SelectionDAG &DAG) |
| static bool | canFoldInAddressingMode (SDNode *N, SDNode *Use, SelectionDAG &DAG, const TargetLowering &TLI) |
| Return true if 'Use' is a load or a store that uses N as its base pointer and that N may be folded in the load / store addressing mode. More... | |
| static bool | areUsedBitsDense (const APInt &UsedBits) |
Check that all bits set in UsedBits form a dense region, i.e., UsedBits looks like 0..0 1..1 0..0. More... | |
| static bool | areSlicesNextToEachOther (const LoadedSlice &First, const LoadedSlice &Second) |
Check whether or not First and Second are next to each other in memory. More... | |
| static void | adjustCostForPairing (SmallVectorImpl< LoadedSlice > &LoadedSlices, LoadedSlice::Cost &GlobalLSCost) |
Adjust the GlobalLSCost according to the target paring capabilities and the layout of the slices. More... | |
| static bool | isSlicingProfitable (SmallVectorImpl< LoadedSlice > &LoadedSlices, const APInt &UsedBits, bool ForCodeSize) |
| Check the profitability of all involved LoadedSlice. More... | |
| static std::pair< unsigned, unsigned > | CheckForMaskedLoad (SDValue V, SDValue Ptr, SDValue Chain) |
| Check to see if V is (and load (ptr), imm), where the load is having specific bytes cleared out. More... | |
| static SDNode * | ShrinkLoadReplaceStoreWithStore (const std::pair< unsigned, unsigned > &MaskInfo, SDValue IVal, StoreSDNode *St, DAGCombiner *DC) |
| Check to see if IVal is something that provides a value as specified by MaskInfo. More... | |
| static bool | allowableAlignment (const SelectionDAG &DAG, const TargetLowering &TLI, EVT EVTTy, unsigned AS, unsigned Align) |
| static SDValue | combineConcatVectorOfScalars (SDNode *N, SelectionDAG &DAG) |
| static SDValue | simplifyShuffleOperandRecursively (SmallBitVector &UsedElements, SDValue V, SelectionDAG &DAG) |
| static SDValue | simplifyShuffleOperands (ShuffleVectorSDNode *SVN, SDValue N0, SDValue N1, SelectionDAG &DAG) |
| static SDValue | partitionShuffleOfConcats (SDNode *N, SelectionDAG &DAG) |
| static bool | FindBaseOffset (SDValue Ptr, SDValue &Base, int64_t &Offset, const GlobalValue *&GV, const void *&CV) |
| Return true if base is a frame index, which is known not to alias with anything but itself. More... | |
| #define DEBUG_TYPE "dagcombine" |
Definition at line 43 of file DAGCombiner.cpp.
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Adjust the GlobalLSCost according to the target paring capabilities and the layout of the slices.
GlobalLSCost should account for at least as many loads as there is in the slices in LoadedSlices. Definition at line 10016 of file DAGCombiner.cpp.
References areSlicesNextToEachOther(), llvm::SmallVectorTemplateCommon< T >::begin(), llvm::SmallVectorTemplateCommon< T >::end(), and llvm::SmallVectorTemplateCommon< T >::size().
Referenced by isSlicingProfitable().
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Definition at line 10746 of file DAGCombiner.cpp.
References llvm::TargetLoweringBase::allowsMisalignedMemoryAccesses(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::DataLayout::getPrefTypeAlignment(), and llvm::EVT::getTypeForEVT().
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Check whether or not First and Second are next to each other in memory.
This means that there is no hole between the bits loaded by First and the bits loaded by Second.
Definition at line 10001 of file DAGCombiner.cpp.
References areUsedBitsDense().
Referenced by adjustCostForPairing().
Check that all bits set in UsedBits form a dense region, i.e., UsedBits looks like 0..0 1..1 0..0.
Definition at line 9984 of file DAGCombiner.cpp.
References llvm::APInt::countLeadingZeros(), llvm::APInt::countTrailingZeros(), llvm::APInt::getActiveBits(), llvm::APInt::isAllOnesValue(), llvm::APInt::lshr(), and llvm::APInt::trunc().
Referenced by areSlicesNextToEachOther(), and isSlicingProfitable().
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Return true if 'Use' is a load or a store that uses N as its base pointer and that N may be folded in the load / store addressing mode.
Definition at line 9115 of file DAGCombiner.cpp.
References llvm::ISD::ADD, llvm::dyn_cast(), llvm::MemSDNode::getAddressSpace(), llvm::LoadSDNode::getBasePtr(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::ConstantSDNode::getSExtValue(), llvm::EVT::getTypeForEVT(), llvm::LSBaseSDNode::isIndexed(), llvm::TargetLoweringBase::isLegalAddressingMode(), N, llvm::AArch64DB::ST, and llvm::ISD::SUB.
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Check to see if V is (and load (ptr), imm), where the load is having specific bytes cleared out.
If so, return the byte size being masked out and the shift amount.
Definition at line 10223 of file DAGCombiner.cpp.
References llvm::ISD::AND, llvm::countLeadingZeros(), llvm::countTrailingOnes(), llvm::countTrailingZeros(), llvm::LoadSDNode::getBasePtr(), llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::ISD::isNormalLoad(), llvm::AArch64DB::LD, llvm::SDNode::op_values(), and llvm::ISD::TokenFactor.
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Definition at line 12124 of file DAGCombiner.cpp.
References llvm::SmallVectorTemplateCommon< T >::back(), llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::DL, llvm::SelectionDAG::getContext(), llvm::EVT::getFloatingPointVT(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorVT(), llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), llvm::SDNode::ops(), llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), and llvm::ISD::UNDEF.
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Generate Min/Max node.
Definition at line 4865 of file DAGCombiner.cpp.
References llvm::ISD::FMAXNUM, llvm::ISD::FMINNUM, llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::isOperationLegal(), llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, and llvm::ISD::SETULT.
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Definition at line 5094 of file DAGCombiner.cpp.
References llvm::ISD::BUILD_VECTOR, llvm::ISD::CONCAT_VECTORS, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::ConstantSDNode::isNullValue(), and llvm::ISD::UNDEF.
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Definition at line 5646 of file DAGCombiner.cpp.
References llvm::ISD::ANY_EXTEND, llvm::ISD::CopyToReg, llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getResNo(), llvm::SDUse::getResNo(), llvm::SDUse::getUser(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::ISD::isSignedIntSetCC(), llvm::TargetLoweringBase::isTruncateFree(), llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::ISD::SETCC, llvm::SmallVectorTemplateCommon< T >::size(), llvm::SDNode::use_begin(), llvm::SDNode::use_end(), and llvm::ISD::ZERO_EXTEND.
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Return true if base is a frame index, which is known not to alias with anything but itself.
Provides base object and offset as results.
Definition at line 13804 of file DAGCombiner.cpp.
References llvm::ISD::ADD, G, llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), and llvm::ConstantSDNode::getZExtValue().
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Definition at line 8587 of file DAGCombiner.cpp.
References llvm::ISD::BITCAST, llvm::SelectionDAG::EVTToAPFloatSemantics(), llvm::ISD::FP_TO_SINT, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), fuzzer::min(), llvm::APFloat::semanticsPrecision(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::TRUNCATE, llvm::ISD::UINT_TO_FP, and llvm::ISD::ZERO_EXTEND.
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If N is a ContantSDNode with isOpaque() == false return it casted to a ContantSDNode pointer else nullptr.
Definition at line 1620 of file DAGCombiner.cpp.
References llvm::dyn_cast(), llvm::ConstantSDNode::isOpaque(), and N.
Definition at line 7070 of file DAGCombiner.cpp.
References llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getResNo(), and llvm::ISD::MERGE_VALUES.
Given a node, return its input chain if it has one, otherwise return a null sd operand.
Definition at line 1490 of file DAGCombiner.cpp.
References llvm::SDNode::getNumOperands(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), and llvm::MVT::Other.
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If isNegatibleForFree returns true, return the newly negated expression.
Definition at line 599 of file DAGCombiner.cpp.
References llvm::APFloat::changeSign(), llvm::ISD::ConstantFP, llvm::ISD::FADD, llvm::ISD::FDIV, llvm::ISD::FMUL, llvm::ISD::FNEG, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::ISD::FSIN, llvm::ISD::FSUB, llvm::SelectionDAG::getConstantFP(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getTarget(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::TargetOptions::HonorSignDependentRoundingFPMath(), isNegatibleForFree(), llvm_unreachable, llvm::TargetMachine::Options, and llvm::TargetOptions::UnsafeFPMath.
Definition at line 1608 of file DAGCombiner.cpp.
References llvm::dyn_cast(), and llvm::ConstantSDNode::isAllOnesValue().
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Return true if the specified node is an element that makes up a 32-bit packed halfword byteswap.
((x & 0x000000ff) << 8) | ((x & 0x0000ff00) >> 8) | ((x & 0x00ff0000) << 8) | ((x & 0xff000000) >> 8)
Definition at line 3320 of file DAGCombiner.cpp.
References llvm::ISD::AND, llvm::C, llvm::dyn_cast(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ConstantSDNode::getZExtValue(), llvm::SDNode::hasOneUse(), llvm::ISD::SHL, and llvm::ISD::SRL.
Definition at line 743 of file DAGCombiner.cpp.
References llvm::SDValue::getNode(), and llvm::ISD::isBuildVectorOfConstantFPSDNodes().
Definition at line 733 of file DAGCombiner.cpp.
References llvm::SDValue::getNode(), and llvm::ISD::isBuildVectorOfConstantSDNodes().
Returns true if N is a BUILD_VECTOR node whose elements are all the same constant or undefined.
Definition at line 717 of file DAGCombiner.cpp.
References llvm::C, llvm::dyn_cast(), llvm::EVT::getSizeInBits(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::BuildVectorSDNode::isConstantSplat(), and N.
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Definition at line 753 of file DAGCombiner.cpp.
References llvm::EVT::getScalarType(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), and llvm::BitVector::none().
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Definition at line 774 of file DAGCombiner.cpp.
References llvm::BitVector::none().
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Return 1 if we can compute the negated form of the specified expression for the same cost as the expression itself, or 2 if we can compute the negated form more cheaply than the expression itself.
Definition at line 536 of file DAGCombiner.cpp.
References llvm::ISD::ConstantFP, llvm::ISD::FADD, llvm::ISD::FDIV, llvm::ISD::FMUL, llvm::ISD::FNEG, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::ISD::FSIN, llvm::ISD::FSUB, llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), and llvm::TargetOptions::UnsafeFPMath.
Referenced by GetNegatedExpression().
Definition at line 1598 of file DAGCombiner.cpp.
References llvm::dyn_cast(), and llvm::ConstantSDNode::isNullValue().
Referenced by isTruncateOf().
Definition at line 1603 of file DAGCombiner.cpp.
References llvm::dyn_cast(), llvm::ConstantFPSDNode::isNegative(), and llvm::ConstantFPSDNode::isZero().
Definition at line 1613 of file DAGCombiner.cpp.
References llvm::dyn_cast(), and llvm::ConstantSDNode::isOne().
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Check the profitability of all involved LoadedSlice.
Currently, it is considered profitable if there is exactly two involved slices (1) which are (2) next to each other in memory, and whose cost (
Note: The order of the elements in LoadedSlices may be modified, but not the elements themselves.
FIXME: When the cost model will be mature enough, we can relax constraints (1) and (2).
Definition at line 10084 of file DAGCombiner.cpp.
References adjustCostForPairing(), areUsedBitsDense(), and llvm::SmallVectorTemplateCommon< T >::size().
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Definition at line 6050 of file DAGCombiner.cpp.
References llvm::SelectionDAG::computeKnownBits(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::MVT::i1, isNullConstant(), llvm::ISD::SETCC, llvm::ISD::SETNE, and llvm::ISD::TRUNCATE.
Match "(X shl/srl V1) & V2" where V2 may not be present.
Definition at line 3711 of file DAGCombiner.cpp.
References llvm::ISD::AND, llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ISD::SHL, and llvm::ISD::SRL.
Definition at line 3738 of file DAGCombiner.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, llvm::ISD::Constant, llvm::dyn_cast(), llvm::ConstantSDNode::getAPIntValue(), llvm::APInt::getLoBits(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::isPowerOf2_64(), llvm::Log2_64(), and llvm::ISD::SUB.
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Definition at line 12486 of file DAGCombiner.cpp.
References llvm::all_of(), llvm::ISD::CONCAT_VECTORS, llvm::ShuffleVectorSDNode::getMask(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), I, N, and llvm::ISD::UNDEF.
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Check to see if IVal is something that provides a value as specified by MaskInfo.
If so, replace the specified store with a narrower store of truncated IVal.
Definition at line 10298 of file DAGCombiner.cpp.
References llvm::ISD::ADD, llvm::DL, llvm::MemSDNode::getAlignment(), llvm::StoreSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::MemSDNode::getPointerInfo(), llvm::SelectionDAG::getStore(), llvm::EVT::getStoreSize(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::MachinePointerInfo::getWithOffset(), llvm::DataLayout::isLittleEndian(), llvm::SelectionDAG::MaskedValueIsZero(), llvm::MinAlign(), llvm::ISD::SRL, and llvm::ISD::TRUNCATE.
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Definition at line 12398 of file DAGCombiner.cpp.
References llvm::SmallVectorTemplateCommon< T >::back(), llvm::ISD::CONCAT_VECTORS, llvm::DL, llvm::dyn_cast(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::ISD::INSERT_SUBVECTOR, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::SmallVectorImpl< T >::reserve(), and llvm::SmallBitVector::reset().
Referenced by simplifyShuffleOperands().
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Definition at line 12465 of file DAGCombiner.cpp.
References llvm::ShuffleVectorSDNode::getMask(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), and simplifyShuffleOperandRecursively().
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Definition at line 5076 of file DAGCombiner.cpp.
References llvm::DL, llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::GetSplitDestVTs(), llvm::SDNode::getValueType(), llvm::MipsISD::Hi, llvm::MipsISD::Lo, and llvm::SelectionDAG::SplitVectorOperand().
| STATISTIC | ( | NodesCombined | , |
| "Number of dag nodes combined" | |||
| ) |
| STATISTIC | ( | PreIndexedNodes | , |
| "Number of pre-indexed nodes created" | |||
| ) |
| STATISTIC | ( | PostIndexedNodes | , |
| "Number of post-indexed nodes created" | |||
| ) |
| STATISTIC | ( | OpsNarrowed | , |
| "Number of load/op/store narrowed" | |||
| ) |
| STATISTIC | ( | SlicedLoads | , |
| "Number of load sliced" | |||
| ) |
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Definition at line 1853 of file DAGCombiner.cpp.
References llvm::ISD::BUILD_VECTOR, llvm::SelectionDAG::getConstant(), llvm::TargetLoweringBase::isOperationLegal(), and llvm::EVT::isVector().
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Try to fold a sext/zext/aext dag node into a ConstantSDNode or a build_vector of constants.
This function is called by the DAGCombiner when visiting sext/zext/aext dag nodes (see for example method DAGCombiner::visitSIGN_EXTEND). Vector extends are not folded if operations are legal; this is to avoid introducing illegal build_vector dag nodes.
Definition at line 5589 of file DAGCombiner.cpp.
References llvm::ISD::ANY_EXTEND, llvm::ISD::BUILD_VECTOR, llvm::C, llvm::DL, llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getScalarType(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::APInt::sext(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_VECTOR_INREG, llvm::ISD::UNDEF, llvm::ISD::ZERO_EXTEND, and llvm::APInt::zext().
1.8.6