22 #define DEBUG_TYPE "systemz-isel"
26 struct SystemZAddressingMode {
61 bool IncludesDynAlloc;
63 SystemZAddressingMode(AddrForm form, DispRange dr)
64 :
Form(form), DR(dr), Base(), Disp(0), Index(),
65 IncludesDynAlloc(
false) {}
68 bool hasIndexField() {
return Form != FormBD; }
71 bool isDynAlloc() {
return Form == FormBDXDynAlloc; }
74 errs() <<
"SystemZAddressingMode " <<
this <<
'\n';
78 Base.getNode()->dump();
82 if (hasIndexField()) {
85 Index.getNode()->dump();
90 errs() <<
" Disp " << Disp;
92 errs() <<
" + ADJDYNALLOC";
98 static uint64_t
allOnes(
unsigned int Count) {
102 return (uint64_t(1) << Count) - 1;
117 struct RxSBGOperands {
118 RxSBGOperands(
unsigned Op,
SDValue N)
120 Mask(
allOnes(BitSize)), Input(N), Start(64 - BitSize), End(63),
136 inline SDValue getImm(
const SDNode *Node, uint64_t Imm)
const {
145 return Subtarget->getInstrInfo();
150 bool expandAddress(SystemZAddressingMode &AM,
bool IsBase)
const;
153 bool selectAddress(
SDValue N, SystemZAddressingMode &AM)
const;
156 void getAddressOperands(
const SystemZAddressingMode &AM,
EVT VT,
158 void getAddressOperands(
const SystemZAddressingMode &AM,
EVT VT,
164 bool selectBDAddr(SystemZAddressingMode::DispRange DR,
SDValue Addr,
170 bool selectMVIAddr(SystemZAddressingMode::DispRange DR,
SDValue Addr,
176 bool selectBDXAddr(SystemZAddressingMode::AddrForm
Form,
177 SystemZAddressingMode::DispRange DR,
SDValue Addr,
191 return selectBDAddr(SystemZAddressingMode::Disp12Only, Addr, Base, Disp);
194 return selectBDAddr(SystemZAddressingMode::Disp12Pair, Addr, Base, Disp);
197 return selectBDAddr(SystemZAddressingMode::Disp20Only, Addr, Base, Disp);
200 return selectBDAddr(SystemZAddressingMode::Disp20Pair, Addr, Base, Disp);
205 return selectMVIAddr(SystemZAddressingMode::Disp12Pair, Addr, Base, Disp);
208 return selectMVIAddr(SystemZAddressingMode::Disp20Pair, Addr, Base, Disp);
214 return selectBDXAddr(SystemZAddressingMode::FormBDXNormal,
215 SystemZAddressingMode::Disp12Only,
216 Addr, Base, Disp, Index);
220 return selectBDXAddr(SystemZAddressingMode::FormBDXNormal,
221 SystemZAddressingMode::Disp12Pair,
222 Addr, Base, Disp, Index);
226 return selectBDXAddr(SystemZAddressingMode::FormBDXDynAlloc,
227 SystemZAddressingMode::Disp12Only,
228 Addr, Base, Disp, Index);
232 return selectBDXAddr(SystemZAddressingMode::FormBDXNormal,
233 SystemZAddressingMode::Disp20Only,
234 Addr, Base, Disp, Index);
238 return selectBDXAddr(SystemZAddressingMode::FormBDXNormal,
239 SystemZAddressingMode::Disp20Only128,
240 Addr, Base, Disp, Index);
244 return selectBDXAddr(SystemZAddressingMode::FormBDXNormal,
245 SystemZAddressingMode::Disp20Pair,
246 Addr, Base, Disp, Index);
250 return selectBDXAddr(SystemZAddressingMode::FormBDXLA,
251 SystemZAddressingMode::Disp12Pair,
252 Addr, Base, Disp, Index);
256 return selectBDXAddr(SystemZAddressingMode::FormBDXLA,
257 SystemZAddressingMode::Disp20Pair,
258 Addr, Base, Disp, Index);
271 bool detectOrAndInsertion(
SDValue &Op, uint64_t InsertMask)
const;
275 bool refineRxSBGMask(RxSBGOperands &RxSBG, uint64_t Mask)
const;
279 bool expandRxSBG(RxSBGOperands &RxSBG)
const;
303 uint64_t UpperVal, uint64_t LowerVal);
324 bool storeLoadCanUseMVC(
SDNode *N)
const;
329 bool storeLoadCanUseBlockBinary(
SDNode *N,
unsigned I)
const;
341 const char *getPassName()
const override {
342 return "SystemZ DAG->DAG Pattern Instruction Selection";
347 bool SelectInlineAsmMemoryOperand(
const SDValue &Op,
unsigned ConstraintID,
348 std::vector<SDValue> &OutOps)
override;
351 #include "SystemZGenDAGISel.inc"
357 return new SystemZDAGToDAGISel(TM, OptLevel);
363 static bool selectDisp(SystemZAddressingMode::DispRange DR, int64_t Val) {
365 case SystemZAddressingMode::Disp12Only:
366 return isUInt<12>(Val);
368 case SystemZAddressingMode::Disp12Pair:
369 case SystemZAddressingMode::Disp20Only:
370 case SystemZAddressingMode::Disp20Pair:
371 return isInt<20>(Val);
373 case SystemZAddressingMode::Disp20Only128:
374 return isInt<20>(Val) && isInt<20>(Val + 8);
394 if (AM.isDynAlloc() && !AM.IncludesDynAlloc) {
396 AM.IncludesDynAlloc =
true;
406 if (AM.hasIndexField() && !AM.Index.getNode()) {
416 static bool expandDisp(SystemZAddressingMode &AM,
bool IsBase,
419 int64_t TestDisp = AM.Disp + Op1;
431 bool SystemZDAGToDAGISel::expandAddress(SystemZAddressingMode &AM,
433 SDValue N = IsBase ? AM.Base : AM.Index;
439 if (Opcode ==
ISD::ADD || CurDAG->isBaseWithConstantOffset(N)) {
453 cast<ConstantSDNode>(Op0)->getSExtValue());
456 cast<ConstantSDNode>(Op1)->getSExtValue());
465 uint64_t Offset = (cast<GlobalAddressSDNode>(
Full)->
getOffset() -
466 cast<GlobalAddressSDNode>(Anchor)->
getOffset());
474 static bool isValidDisp(SystemZAddressingMode::DispRange DR, int64_t Val) {
475 assert(
selectDisp(DR, Val) &&
"Invalid displacement");
477 case SystemZAddressingMode::Disp12Only:
478 case SystemZAddressingMode::Disp20Only:
479 case SystemZAddressingMode::Disp20Only128:
482 case SystemZAddressingMode::Disp12Pair:
484 return isUInt<12>(Val);
486 case SystemZAddressingMode::Disp20Pair:
488 return !isUInt<12>(Val);
512 if (isUInt<12>(Disp))
531 unsigned IndexOpcode = Index->
getOpcode();
546 bool SystemZDAGToDAGISel::selectAddress(
SDValue Addr,
547 SystemZAddressingMode &AM)
const {
555 cast<ConstantSDNode>(Addr)->getSExtValue()))
559 while (expandAddress(AM,
true) ||
560 (AM.Index.getNode() && expandAddress(AM,
false)))
564 if (AM.Form == SystemZAddressingMode::FormBDXLA &&
565 !
shouldUseLA(AM.Base.getNode(), AM.Disp, AM.Index.getNode()))
573 if (AM.isDynAlloc() && !AM.IncludesDynAlloc)
593 void SystemZDAGToDAGISel::getAddressOperands(
const SystemZAddressingMode &AM,
599 Base = CurDAG->getRegister(0, VT);
602 int64_t
FrameIndex = cast<FrameIndexSDNode>(Base)->getIndex();
603 Base = CurDAG->getTargetFrameIndex(FrameIndex, VT);
607 "Unexpected truncation");
615 Disp = CurDAG->getTargetConstant(AM.Disp,
SDLoc(Base), VT);
618 void SystemZDAGToDAGISel::getAddressOperands(
const SystemZAddressingMode &AM,
622 getAddressOperands(AM, VT, Base, Disp);
627 Index = CurDAG->getRegister(0, VT);
630 bool SystemZDAGToDAGISel::selectBDAddr(SystemZAddressingMode::DispRange DR,
633 SystemZAddressingMode AM(SystemZAddressingMode::FormBD, DR);
634 if (!selectAddress(Addr, AM))
637 getAddressOperands(AM, Addr.
getValueType(), Base, Disp);
641 bool SystemZDAGToDAGISel::selectMVIAddr(SystemZAddressingMode::DispRange DR,
644 SystemZAddressingMode AM(SystemZAddressingMode::FormBDXNormal, DR);
645 if (!selectAddress(Addr, AM) || AM.Index.getNode())
648 getAddressOperands(AM, Addr.
getValueType(), Base, Disp);
652 bool SystemZDAGToDAGISel::selectBDXAddr(SystemZAddressingMode::AddrForm
Form,
653 SystemZAddressingMode::DispRange DR,
656 SystemZAddressingMode AM(Form, DR);
657 if (!selectAddress(Addr, AM))
660 getAddressOperands(AM, Addr.
getValueType(), Base, Disp, Index);
664 bool SystemZDAGToDAGISel::selectBDVAddr12Only(
SDValue Addr,
SDValue Elem,
669 if (selectBDXAddr12Only(Addr, Regs[0], Disp, Regs[1]) &&
670 Regs[0].getNode() && Regs[1].getNode()) {
671 for (
unsigned int I = 0;
I < 2; ++
I) {
688 bool SystemZDAGToDAGISel::detectOrAndInsertion(
SDValue &Op,
689 uint64_t InsertMask)
const {
702 if (InsertMask & AndMask)
708 if (Used != (AndMask | InsertMask)) {
709 APInt KnownZero, KnownOne;
710 CurDAG->computeKnownBits(Op.
getOperand(0), KnownZero, KnownOne);
711 if (Used != (AndMask | InsertMask | KnownZero.
getZExtValue()))
719 bool SystemZDAGToDAGISel::refineRxSBGMask(RxSBGOperands &RxSBG,
720 uint64_t Mask)
const {
722 if (RxSBG.Rotate != 0)
723 Mask = (Mask << RxSBG.Rotate) | (Mask >> (64 - RxSBG.Rotate));
725 if (TII->
isRxSBGMask(Mask, RxSBG.BitSize, RxSBG.Start, RxSBG.End)) {
735 if (RxSBG.Rotate != 0)
736 Mask = ((Mask << RxSBG.Rotate) | (Mask >> (64 - RxSBG.Rotate)));
737 return (Mask & RxSBG.Mask) != 0;
740 bool SystemZDAGToDAGISel::expandRxSBG(RxSBGOperands &RxSBG)
const {
745 if (RxSBG.Opcode == SystemZ::RNSBG)
753 uint64_t Mask = MaskNode->getZExtValue();
754 if (!refineRxSBGMask(RxSBG, Mask)) {
758 APInt KnownZero, KnownOne;
759 CurDAG->computeKnownBits(Input, KnownZero, KnownOne);
761 if (!refineRxSBGMask(RxSBG, Mask))
769 if (RxSBG.Opcode != SystemZ::RNSBG)
777 uint64_t Mask = ~MaskNode->getZExtValue();
778 if (!refineRxSBGMask(RxSBG, Mask)) {
782 APInt KnownZero, KnownOne;
783 CurDAG->computeKnownBits(Input, KnownZero, KnownOne);
785 if (!refineRxSBGMask(RxSBG, Mask))
800 RxSBG.Rotate = (RxSBG.Rotate + CountNode->getZExtValue()) & 63;
811 if (RxSBG.Opcode != SystemZ::RNSBG) {
814 if (!refineRxSBGMask(RxSBG,
allOnes(InnerBitSize)))
840 if (Count < 1 || Count >= BitSize)
843 if (RxSBG.Opcode == SystemZ::RNSBG) {
850 if (!refineRxSBGMask(RxSBG,
allOnes(BitSize - Count) << Count))
854 RxSBG.Rotate = (RxSBG.Rotate + Count) & 63;
867 if (Count < 1 || Count >= BitSize)
870 if (RxSBG.Opcode == SystemZ::RNSBG || Opcode ==
ISD::SRA) {
878 if (!refineRxSBGMask(RxSBG,
allOnes(BitSize - Count)))
882 RxSBG.Rotate = (RxSBG.Rotate - Count) & 63;
898 return CurDAG->getTargetInsertSubreg(SystemZ::subreg_l32,
901 return CurDAG->getTargetExtractSubreg(SystemZ::subreg_l32, DL, VT, N);
902 assert(N.
getValueType() == VT &&
"Unexpected value types");
911 RxSBGOperands RISBG(SystemZ::RISBG,
SDValue(N, 0));
913 while (expandRxSBG(RISBG))
928 RISBG.Mask == 0xff ||
929 RISBG.Mask == 0xffff ||
934 if (MaskN->getZExtValue() != RISBG.Mask) {
935 SDValue NewMask = CurDAG->getConstant(RISBG.Mask, DL, VT);
936 N = CurDAG->UpdateNodeOperands(N, N->
getOperand(0), NewMask);
937 return SelectCode(N);
943 unsigned Opcode = SystemZ::RISBG;
945 if (Subtarget->hasMiscellaneousExtensions())
946 Opcode = SystemZ::RISBGN;
948 if (VT ==
MVT::i32 && Subtarget->hasHighWord()) {
949 Opcode = SystemZ::RISBMux;
955 getUNDEF(DL, OpcodeVT),
956 convertTo(DL, OpcodeVT, RISBG.Input),
957 CurDAG->getTargetConstant(RISBG.Start, DL,
MVT::i32),
958 CurDAG->getTargetConstant(RISBG.End | 128, DL,
MVT::i32),
959 CurDAG->getTargetConstant(RISBG.Rotate, DL,
MVT::i32)
961 N = CurDAG->getMachineNode(Opcode, DL, OpcodeVT, Ops);
962 return convertTo(DL, VT,
SDValue(N, 0)).getNode();
965 SDNode *SystemZDAGToDAGISel::tryRxSBG(
SDNode *N,
unsigned Opcode) {
972 RxSBGOperands RxSBG[] = {
976 unsigned Count[] = { 0, 0 };
977 for (
unsigned I = 0;
I < 2; ++
I)
978 while (expandRxSBG(RxSBG[
I]))
983 if (Count[0] == 0 && Count[1] == 0)
987 unsigned I = Count[0] > Count[1] ? 0 : 1;
991 if (Opcode == SystemZ::ROSBG && (RxSBG[I].Mask & 0xff) == 0)
992 if (
auto *
Load = dyn_cast<LoadSDNode>(Op0.
getNode()))
998 if (Opcode == SystemZ::ROSBG && detectOrAndInsertion(Op0, RxSBG[I].Mask)) {
999 Opcode = SystemZ::RISBG;
1001 if (Subtarget->hasMiscellaneousExtensions())
1002 Opcode = SystemZ::RISBGN;
1007 convertTo(DL,
MVT::i64, RxSBG[I].Input),
1008 CurDAG->getTargetConstant(RxSBG[I].Start, DL,
MVT::i32),
1009 CurDAG->getTargetConstant(RxSBG[I].End, DL,
MVT::i32),
1010 CurDAG->getTargetConstant(RxSBG[I].Rotate, DL,
MVT::i32)
1012 N = CurDAG->getMachineNode(Opcode, DL,
MVT::i64, Ops);
1013 return convertTo(DL, VT,
SDValue(N, 0)).getNode();
1016 SDNode *SystemZDAGToDAGISel::splitLargeImmediate(
unsigned Opcode,
SDNode *Node,
1017 SDValue Op0, uint64_t UpperVal,
1018 uint64_t LowerVal) {
1021 SDValue Upper = CurDAG->getConstant(UpperVal, DL, VT);
1023 Upper = CurDAG->getNode(Opcode, DL, VT, Op0, Upper);
1026 SDValue Lower = CurDAG->getConstant(LowerVal, DL, VT);
1027 SDValue Or = CurDAG->getNode(Opcode, DL, VT, Upper, Lower);
1031 SDNode *SystemZDAGToDAGISel::tryGather(
SDNode *N,
unsigned Opcode) {
1037 unsigned Elem = ElemN->getZExtValue();
1045 if (
Load->getMemoryVT().getSizeInBits() !=
1046 Load->getValueType(0).getSizeInBits())
1050 if (!selectBDVAddr12Only(
Load->getBasePtr(), ElemV, Base, Disp, Index) ||
1057 CurDAG->getTargetConstant(Elem, DL,
MVT::i32),
Load->getChain()
1079 unsigned Elem = ElemN->getZExtValue();
1084 if (!selectBDVAddr12Only(Store->
getBasePtr(), ElemV, Base, Disp, Index) ||
1090 Vec, Base, Disp, Index, CurDAG->getTargetConstant(Elem, DL,
MVT::i32),
1093 return CurDAG->getMachineNode(Opcode, DL,
MVT::Other, Ops);
1096 bool SystemZDAGToDAGISel::canUseBlockOperation(
StoreSDNode *Store,
1120 if (V1 == V2 && End1 == End2)
1127 bool SystemZDAGToDAGISel::storeLoadCanUseMVC(
SDNode *N)
const {
1128 auto *Store = cast<StoreSDNode>(
N);
1129 auto *Load = cast<LoadSDNode>(Store->
getValue());
1134 if (Size > 1 && Size <= 8) {
1143 return canUseBlockOperation(Store, Load);
1146 bool SystemZDAGToDAGISel::storeLoadCanUseBlockBinary(
SDNode *N,
1148 auto *StoreA = cast<StoreSDNode>(
N);
1149 auto *LoadA = cast<LoadSDNode>(StoreA->getValue().getOperand(1 - I));
1150 auto *LoadB = cast<LoadSDNode>(StoreA->getValue().getOperand(I));
1151 return !LoadA->isVolatile() && canUseBlockOperation(StoreA, LoadB);
1166 SDNode *ResNode =
nullptr;
1170 ResNode = tryRxSBG(Node, SystemZ::ROSBG);
1175 ResNode = tryRxSBG(Node, SystemZ::RXSBG);
1181 if (
auto *Op1 = dyn_cast<ConstantSDNode>(Node->
getOperand(1))) {
1182 uint64_t Val = Op1->getZExtValue();
1184 Node = splitLargeImmediate(Opcode, Node, Node->
getOperand(0),
1185 Val - uint32_t(Val), uint32_t(Val));
1191 ResNode = tryRxSBG(Node, SystemZ::RNSBG);
1198 ResNode = tryRISBGZero(Node);
1205 uint64_t Val = cast<ConstantSDNode>(Node)->getZExtValue();
1208 Val - uint32_t(Val), uint32_t(Val));
1220 uint64_t ConstCCValid =
1221 cast<ConstantSDNode>(CCValid.
getNode())->getZExtValue();
1222 uint64_t ConstCCMask =
1223 cast<ConstantSDNode>(CCMask.
getNode())->getZExtValue();
1225 CCMask = CurDAG->getConstant(ConstCCValid ^ ConstCCMask,
SDLoc(Node),
1228 Node = CurDAG->UpdateNodeOperands(Node, Op1, Op0, CCValid, CCMask, Op4);
1236 if (ElemBitSize == 32)
1237 ResNode = tryGather(Node, SystemZ::VGEF);
1238 else if (ElemBitSize == 64)
1239 ResNode = tryGather(Node, SystemZ::VGEG);
1244 auto *Store = cast<StoreSDNode>(Node);
1246 if (ElemBitSize == 32)
1247 ResNode = tryScatter(Store, SystemZ::VSCEF);
1248 else if (ElemBitSize == 64)
1249 ResNode = tryScatter(Store, SystemZ::VSCEG);
1256 ResNode = SelectCode(Node);
1259 if (ResNode ==
nullptr || ResNode == Node)
1262 ResNode->
dump(CurDAG);
1268 bool SystemZDAGToDAGISel::
1269 SelectInlineAsmMemoryOperand(
const SDValue &Op,
1270 unsigned ConstraintID,
1271 std::vector<SDValue> &OutOps) {
1272 switch(ConstraintID) {
1284 if (selectBDXAddr(SystemZAddressingMode::FormBD,
1285 SystemZAddressingMode::Disp12Only,
1286 Op, Base, Disp, Index)) {
1287 OutOps.push_back(Base);
1288 OutOps.push_back(Disp);
1289 OutOps.push_back(Index);
bool isInt< 32 >(int64_t x)
static bool isImmHF(uint64_t Val)
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
static void insertDAGNode(SelectionDAG *DAG, SDNode *Pos, SDValue N)
uint64_t getZExtValue() const
Get zero extended value.
void dump() const
Dump this node, for debugging.
bool hasOneUse() const
Return true if there is exactly one use of this node.
static bool isImmLF(uint64_t Val)
static bool maskMatters(RxSBGOperands &RxSBG, uint64_t Mask)
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
const SDValue & getOperand(unsigned Num) const
void setNodeId(int Id)
Set unique node id.
static std::error_code getOffset(const SymbolRef &Sym, SectionRef Sec, uint64_t &Result)
int64_t getSrcValueOffset() const
static uint64_t allOnes(unsigned int Count)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const HexagonInstrInfo * TII
Shift and rotation operations.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
FunctionPass * createSystemZISelDag(SystemZTargetMachine &TM, CodeGenOpt::Level OptLevel)
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
EVT getVectorElementType() const
getVectorElementType - Given a vector type, return the type of each element.
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Simple integer binary arithmetic operators.
static bool expandAdjDynAlloc(SystemZAddressingMode &AM, bool IsBase, SDValue Value)
const SDValue & getBasePtr() const
EVT getMemoryVT() const
Return the type of the in-memory value.
static bool shouldUseLA(SDNode *Base, int64_t Disp, SDNode *Index)
This class is used to represent ISD::STORE nodes.
SDNode * getNode() const
get the SDNode which holds the desired result
IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
unsigned getStoreSize() const
getStoreSize - Return the number of bytes overwritten by a store of the specified value type...
void dump(const SparseBitVector< ElementSize > &LHS, raw_ostream &out)
const SDValue & getOperand(unsigned i) const
static bool expandDisp(SystemZAddressingMode &AM, bool IsBase, SDValue Op0, uint64_t Op1)
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL...
APInt Or(const APInt &LHS, const APInt &RHS)
Bitwise OR function for APInt.
void RepositionNode(allnodes_iterator Position, SDNode *N)
Move node N in the AllNodes list to be immediately before the given iterator Position.
static void changeComponent(SystemZAddressingMode &AM, bool IsBase, SDValue Value)
unsigned getOpcode() const
FunctionPass class - This class is used to implement most global optimizations.
bool isPCREL(unsigned Opcode)
const SDValue & getValue() const
bool isRxSBGMask(uint64_t Mask, unsigned BitSize, unsigned &Start, unsigned &End) const
EVT - Extended Value Type.
Representation for a specific memory location.
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
const SDValue & getChain() const
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
AAMDNodes getAAInfo() const
Returns the AA info that describes the dereference.
Target - Wrapper for Target specific information.
Class for arbitrary precision integers.
const Value * getValue() const
getValue - Return the base address of the memory access.
ZERO_EXTEND - Used for integer types, zeroing the new bits.
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
ANY_EXTEND - Used for integer types. The high bits are undefined.
Bitwise operators - logical and, logical or, logical xor.
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
bool isInt< 16 >(int64_t x)
int getNodeId() const
Return the unique node id.
EVT getValueType() const
Return the ValueType of the referenced return value.
static bool selectDisp(SystemZAddressingMode::DispRange DR, int64_t Val)
static bool expandIndex(SystemZAddressingMode &AM, SDValue Base, SDValue Index)
LLVM Value Representation.
static bool isValidDisp(SystemZAddressingMode::DispRange DR, int64_t Val)
TRUNCATE - Completely drop the high bits.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
EVT changeVectorElementTypeToInteger() const
changeVectorElementTypeToInteger - Return a vector with the same number of elements as this vector...
bool isMachineOpcode() const
Test if this node has a post-isel opcode, directly corresponding to a MachineInstr opcode...
uint64_t getZExtValue() const
unsigned getVectorNumElements() const
getVectorNumElements - Given a vector type, return the number of elements it contains.
This class is used to represent ISD::LOAD nodes.