LLVM  3.7.0
HexagonInstrInfo.cpp
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1 //===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Hexagon implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "HexagonInstrInfo.h"
15 #include "Hexagon.h"
16 #include "HexagonRegisterInfo.h"
17 #include "HexagonSubtarget.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallVector.h"
26 #include "llvm/Support/Debug.h"
29 
30 using namespace llvm;
31 
32 #define DEBUG_TYPE "hexagon-instrinfo"
33 
34 #define GET_INSTRINFO_CTOR_DTOR
35 #define GET_INSTRMAP_INFO
36 #include "HexagonGenInstrInfo.inc"
37 #include "HexagonGenDFAPacketizer.inc"
38 
39 ///
40 /// Constants for Hexagon instructions.
41 ///
42 const int Hexagon_MEMW_OFFSET_MAX = 4095;
43 const int Hexagon_MEMW_OFFSET_MIN = -4096;
44 const int Hexagon_MEMD_OFFSET_MAX = 8191;
45 const int Hexagon_MEMD_OFFSET_MIN = -8192;
46 const int Hexagon_MEMH_OFFSET_MAX = 2047;
47 const int Hexagon_MEMH_OFFSET_MIN = -2048;
48 const int Hexagon_MEMB_OFFSET_MAX = 1023;
49 const int Hexagon_MEMB_OFFSET_MIN = -1024;
50 const int Hexagon_ADDI_OFFSET_MAX = 32767;
51 const int Hexagon_ADDI_OFFSET_MIN = -32768;
52 const int Hexagon_MEMD_AUTOINC_MAX = 56;
53 const int Hexagon_MEMD_AUTOINC_MIN = -64;
54 const int Hexagon_MEMW_AUTOINC_MAX = 28;
55 const int Hexagon_MEMW_AUTOINC_MIN = -32;
56 const int Hexagon_MEMH_AUTOINC_MAX = 14;
57 const int Hexagon_MEMH_AUTOINC_MIN = -16;
59 const int Hexagon_MEMB_AUTOINC_MIN = -8;
60 
61 // Pin the vtable to this file.
62 void HexagonInstrInfo::anchor() {}
63 
65  : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
66  RI(), Subtarget(ST) {}
67 
68 /// isLoadFromStackSlot - If the specified machine instruction is a direct
69 /// load from a stack slot, return the virtual or physical register number of
70 /// the destination along with the FrameIndex of the loaded stack slot. If
71 /// not, return 0. This predicate must return 0 if the instruction has
72 /// any side effects other than loading from the stack slot.
74  int &FrameIndex) const {
75 
76 
77  switch (MI->getOpcode()) {
78  default: break;
79  case Hexagon::L2_loadri_io:
80  case Hexagon::L2_loadrd_io:
81  case Hexagon::L2_loadrh_io:
82  case Hexagon::L2_loadrb_io:
83  case Hexagon::L2_loadrub_io:
84  if (MI->getOperand(2).isFI() &&
85  MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
86  FrameIndex = MI->getOperand(2).getIndex();
87  return MI->getOperand(0).getReg();
88  }
89  break;
90  }
91  return 0;
92 }
93 
94 
95 /// isStoreToStackSlot - If the specified machine instruction is a direct
96 /// store to a stack slot, return the virtual or physical register number of
97 /// the source reg along with the FrameIndex of the loaded stack slot. If
98 /// not, return 0. This predicate must return 0 if the instruction has
99 /// any side effects other than storing to the stack slot.
101  int &FrameIndex) const {
102  switch (MI->getOpcode()) {
103  default: break;
104  case Hexagon::S2_storeri_io:
105  case Hexagon::S2_storerd_io:
106  case Hexagon::S2_storerh_io:
107  case Hexagon::S2_storerb_io:
108  if (MI->getOperand(2).isFI() &&
109  MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
110  FrameIndex = MI->getOperand(0).getIndex();
111  return MI->getOperand(2).getReg();
112  }
113  break;
114  }
115  return 0;
116 }
117 
118 // Find the hardware loop instruction used to set-up the specified loop.
119 // On Hexagon, we have two instructions used to set-up the hardware loop
120 // (LOOP0, LOOP1) with corresponding endloop (ENDLOOP0, ENDLOOP1) instructions
121 // to indicate the end of a loop.
122 static MachineInstr *
123 findLoopInstr(MachineBasicBlock *BB, int EndLoopOp,
125  int LOOPi;
126  int LOOPr;
127  if (EndLoopOp == Hexagon::ENDLOOP0) {
128  LOOPi = Hexagon::J2_loop0i;
129  LOOPr = Hexagon::J2_loop0r;
130  } else { // EndLoopOp == Hexagon::EndLOOP1
131  LOOPi = Hexagon::J2_loop1i;
132  LOOPr = Hexagon::J2_loop1r;
133  }
134 
135  // The loop set-up instruction will be in a predecessor block
137  PE = BB->pred_end(); PB != PE; ++PB) {
138  // If this has been visited, already skip it.
139  if (!Visited.insert(*PB).second)
140  continue;
141  if (*PB == BB)
142  continue;
143  for (MachineBasicBlock::reverse_instr_iterator I = (*PB)->instr_rbegin(),
144  E = (*PB)->instr_rend(); I != E; ++I) {
145  int Opc = I->getOpcode();
146  if (Opc == LOOPi || Opc == LOOPr)
147  return &*I;
148  // We've reached a different loop, which means the loop0 has been removed.
149  if (Opc == EndLoopOp)
150  return 0;
151  }
152  // Check the predecessors for the LOOP instruction.
153  MachineInstr *loop = findLoopInstr(*PB, EndLoopOp, Visited);
154  if (loop)
155  return loop;
156  }
157  return 0;
158 }
159 
162  ArrayRef<MachineOperand> Cond, DebugLoc DL) const {
163 
164  Opcode_t BOpc = Hexagon::J2_jump;
165  Opcode_t BccOpc = Hexagon::J2_jumpt;
166 
167  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
168 
169  // Check if ReverseBranchCondition has asked to reverse this branch
170  // If we want to reverse the branch an odd number of times, we want
171  // J2_jumpf.
172  if (!Cond.empty() && Cond[0].isImm())
173  BccOpc = Cond[0].getImm();
174 
175  if (!FBB) {
176  if (Cond.empty()) {
177  // Due to a bug in TailMerging/CFG Optimization, we need to add a
178  // special case handling of a predicated jump followed by an
179  // unconditional jump. If not, Tail Merging and CFG Optimization go
180  // into an infinite loop.
181  MachineBasicBlock *NewTBB, *NewFBB;
183  MachineInstr *Term = MBB.getFirstTerminator();
184  if (Term != MBB.end() && isPredicated(Term) &&
185  !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond, false)) {
186  MachineBasicBlock *NextBB =
187  std::next(MachineFunction::iterator(&MBB));
188  if (NewTBB == NextBB) {
190  RemoveBranch(MBB);
191  return InsertBranch(MBB, TBB, nullptr, Cond, DL);
192  }
193  }
194  BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
195  } else if (isEndLoopN(Cond[0].getImm())) {
196  int EndLoopOp = Cond[0].getImm();
197  assert(Cond[1].isMBB());
198  // Since we're adding an ENDLOOP, there better be a LOOP instruction.
199  // Check for it, and change the BB target if needed.
201  MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, VisitedBBs);
202  assert(Loop != 0 && "Inserting an ENDLOOP without a LOOP");
203  Loop->getOperand(0).setMBB(TBB);
204  // Add the ENDLOOP after the finding the LOOP0.
205  BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
206  } else if (isNewValueJump(Cond[0].getImm())) {
207  assert((Cond.size() == 3) && "Only supporting rr/ri version of nvjump");
208  // New value jump
209  // (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset)
210  // (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset)
211  unsigned Flags1 = getUndefRegState(Cond[1].isUndef());
212  DEBUG(dbgs() << "\nInserting NVJump for BB#" << MBB.getNumber(););
213  if (Cond[2].isReg()) {
214  unsigned Flags2 = getUndefRegState(Cond[2].isUndef());
215  BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
216  addReg(Cond[2].getReg(), Flags2).addMBB(TBB);
217  } else if(Cond[2].isImm()) {
218  BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
219  addImm(Cond[2].getImm()).addMBB(TBB);
220  } else
221  llvm_unreachable("Invalid condition for branching");
222  } else {
223  assert((Cond.size() == 2) && "Malformed cond vector");
224  const MachineOperand &RO = Cond[1];
225  unsigned Flags = getUndefRegState(RO.isUndef());
226  BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
227  }
228  return 1;
229  }
230  assert((!Cond.empty()) &&
231  "Cond. cannot be empty when multiple branchings are required");
232  assert((!isNewValueJump(Cond[0].getImm())) &&
233  "NV-jump cannot be inserted with another branch");
234  // Special case for hardware loops. The condition is a basic block.
235  if (isEndLoopN(Cond[0].getImm())) {
236  int EndLoopOp = Cond[0].getImm();
237  assert(Cond[1].isMBB());
238  // Since we're adding an ENDLOOP, there better be a LOOP instruction.
239  // Check for it, and change the BB target if needed.
241  MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, VisitedBBs);
242  assert(Loop != 0 && "Inserting an ENDLOOP without a LOOP");
243  Loop->getOperand(0).setMBB(TBB);
244  // Add the ENDLOOP after the finding the LOOP0.
245  BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
246  } else {
247  const MachineOperand &RO = Cond[1];
248  unsigned Flags = getUndefRegState(RO.isUndef());
249  BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
250  }
251  BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
252 
253  return 2;
254 }
255 
256 
257 /// This function can analyze one/two way branching only and should (mostly) be
258 /// called by target independent side.
259 /// First entry is always the opcode of the branching instruction, except when
260 /// the Cond vector is supposed to be empty, e.g., when AnalyzeBranch fails, a
261 /// BB with only unconditional jump. Subsequent entries depend upon the opcode,
262 /// e.g. Jump_c p will have
263 /// Cond[0] = Jump_c
264 /// Cond[1] = p
265 /// HW-loop ENDLOOP:
266 /// Cond[0] = ENDLOOP
267 /// Cond[1] = MBB
268 /// New value jump:
269 /// Cond[0] = Hexagon::CMPEQri_f_Jumpnv_t_V4 -- specific opcode
270 /// Cond[1] = R
271 /// Cond[2] = Imm
272 /// @note Related function is \fn findInstrPredicate which fills in
273 /// Cond. vector when a predicated instruction is passed to it.
274 /// We follow same protocol in that case too.
275 ///
277  MachineBasicBlock *&TBB,
278  MachineBasicBlock *&FBB,
280  bool AllowModify) const {
281  TBB = nullptr;
282  FBB = nullptr;
283  Cond.clear();
284 
285  // If the block has no terminators, it just falls into the block after it.
287  if (I == MBB.instr_begin())
288  return false;
289 
290  // A basic block may looks like this:
291  //
292  // [ insn
293  // EH_LABEL
294  // insn
295  // insn
296  // insn
297  // EH_LABEL
298  // insn ]
299  //
300  // It has two succs but does not have a terminator
301  // Don't know how to handle it.
302  do {
303  --I;
304  if (I->isEHLabel())
305  // Don't analyze EH branches.
306  return true;
307  } while (I != MBB.instr_begin());
308 
309  I = MBB.instr_end();
310  --I;
311 
312  while (I->isDebugValue()) {
313  if (I == MBB.instr_begin())
314  return false;
315  --I;
316  }
317 
318  bool JumpToBlock = I->getOpcode() == Hexagon::J2_jump &&
319  I->getOperand(0).isMBB();
320  // Delete the J2_jump if it's equivalent to a fall-through.
321  if (AllowModify && JumpToBlock &&
322  MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
323  DEBUG(dbgs()<< "\nErasing the jump to successor block\n";);
324  I->eraseFromParent();
325  I = MBB.instr_end();
326  if (I == MBB.instr_begin())
327  return false;
328  --I;
329  }
330  if (!isUnpredicatedTerminator(I))
331  return false;
332 
333  // Get the last instruction in the block.
334  MachineInstr *LastInst = I;
335  MachineInstr *SecondLastInst = nullptr;
336  // Find one more terminator if present.
337  do {
338  if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(I)) {
339  if (!SecondLastInst)
340  SecondLastInst = I;
341  else
342  // This is a third branch.
343  return true;
344  }
345  if (I == MBB.instr_begin())
346  break;
347  --I;
348  } while(I);
349 
350  int LastOpcode = LastInst->getOpcode();
351  int SecLastOpcode = SecondLastInst ? SecondLastInst->getOpcode() : 0;
352  // If the branch target is not a basic block, it could be a tail call.
353  // (It is, if the target is a function.)
354  if (LastOpcode == Hexagon::J2_jump && !LastInst->getOperand(0).isMBB())
355  return true;
356  if (SecLastOpcode == Hexagon::J2_jump &&
357  !SecondLastInst->getOperand(0).isMBB())
358  return true;
359 
360  bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c(LastOpcode);
361  bool LastOpcodeHasNVJump = isNewValueJump(LastInst);
362 
363  // If there is only one terminator instruction, process it.
364  if (LastInst && !SecondLastInst) {
365  if (LastOpcode == Hexagon::J2_jump) {
366  TBB = LastInst->getOperand(0).getMBB();
367  return false;
368  }
369  if (isEndLoopN(LastOpcode)) {
370  TBB = LastInst->getOperand(0).getMBB();
371  Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
372  Cond.push_back(LastInst->getOperand(0));
373  return false;
374  }
375  if (LastOpcodeHasJMP_c) {
376  TBB = LastInst->getOperand(1).getMBB();
377  Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
378  Cond.push_back(LastInst->getOperand(0));
379  return false;
380  }
381  // Only supporting rr/ri versions of new-value jumps.
382  if (LastOpcodeHasNVJump && (LastInst->getNumExplicitOperands() == 3)) {
383  TBB = LastInst->getOperand(2).getMBB();
384  Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
385  Cond.push_back(LastInst->getOperand(0));
386  Cond.push_back(LastInst->getOperand(1));
387  return false;
388  }
389  DEBUG(dbgs() << "\nCant analyze BB#" << MBB.getNumber()
390  << " with one jump\n";);
391  // Otherwise, don't know what this is.
392  return true;
393  }
394 
395  bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c(SecLastOpcode);
396  bool SecLastOpcodeHasNVJump = isNewValueJump(SecondLastInst);
397  if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) {
398  TBB = SecondLastInst->getOperand(1).getMBB();
399  Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
400  Cond.push_back(SecondLastInst->getOperand(0));
401  FBB = LastInst->getOperand(0).getMBB();
402  return false;
403  }
404 
405  // Only supporting rr/ri versions of new-value jumps.
406  if (SecLastOpcodeHasNVJump &&
407  (SecondLastInst->getNumExplicitOperands() == 3) &&
408  (LastOpcode == Hexagon::J2_jump)) {
409  TBB = SecondLastInst->getOperand(2).getMBB();
410  Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
411  Cond.push_back(SecondLastInst->getOperand(0));
412  Cond.push_back(SecondLastInst->getOperand(1));
413  FBB = LastInst->getOperand(0).getMBB();
414  return false;
415  }
416 
417  // If the block ends with two Hexagon:JMPs, handle it. The second one is not
418  // executed, so remove it.
419  if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) {
420  TBB = SecondLastInst->getOperand(0).getMBB();
421  I = LastInst;
422  if (AllowModify)
423  I->eraseFromParent();
424  return false;
425  }
426 
427  // If the block ends with an ENDLOOP, and J2_jump, handle it.
428  if (isEndLoopN(SecLastOpcode) && LastOpcode == Hexagon::J2_jump) {
429  TBB = SecondLastInst->getOperand(0).getMBB();
430  Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
431  Cond.push_back(SecondLastInst->getOperand(0));
432  FBB = LastInst->getOperand(0).getMBB();
433  return false;
434  }
435  DEBUG(dbgs() << "\nCant analyze BB#" << MBB.getNumber()
436  << " with two jumps";);
437  // Otherwise, can't handle this.
438  return true;
439 }
440 
442  DEBUG(dbgs() << "\nRemoving branches out of BB#" << MBB.getNumber());
444  unsigned Count = 0;
445  while (I != MBB.begin()) {
446  --I;
447  if (I->isDebugValue())
448  continue;
449  // Only removing branches from end of MBB.
450  if (!I->isBranch())
451  return Count;
452  if (Count && (I->getOpcode() == Hexagon::J2_jump))
453  llvm_unreachable("Malformed basic block: unconditional branch not last");
454  MBB.erase(&MBB.back());
455  I = MBB.end();
456  ++Count;
457  }
458  return Count;
459 }
460 
461 /// \brief For a comparison instruction, return the source registers in
462 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
463 /// compares against in CmpValue. Return true if the comparison instruction
464 /// can be analyzed.
466  unsigned &SrcReg, unsigned &SrcReg2,
467  int &Mask, int &Value) const {
468  unsigned Opc = MI->getOpcode();
469 
470  // Set mask and the first source register.
471  switch (Opc) {
472  case Hexagon::C2_cmpeq:
473  case Hexagon::C2_cmpeqp:
474  case Hexagon::C2_cmpgt:
475  case Hexagon::C2_cmpgtp:
476  case Hexagon::C2_cmpgtu:
477  case Hexagon::C2_cmpgtup:
478  case Hexagon::C4_cmpneq:
479  case Hexagon::C4_cmplte:
480  case Hexagon::C4_cmplteu:
481  case Hexagon::C2_cmpeqi:
482  case Hexagon::C2_cmpgti:
483  case Hexagon::C2_cmpgtui:
484  case Hexagon::C4_cmpneqi:
485  case Hexagon::C4_cmplteui:
486  case Hexagon::C4_cmpltei:
487  SrcReg = MI->getOperand(1).getReg();
488  Mask = ~0;
489  break;
490  case Hexagon::A4_cmpbeq:
491  case Hexagon::A4_cmpbgt:
492  case Hexagon::A4_cmpbgtu:
493  case Hexagon::A4_cmpbeqi:
494  case Hexagon::A4_cmpbgti:
495  case Hexagon::A4_cmpbgtui:
496  SrcReg = MI->getOperand(1).getReg();
497  Mask = 0xFF;
498  break;
499  case Hexagon::A4_cmpheq:
500  case Hexagon::A4_cmphgt:
501  case Hexagon::A4_cmphgtu:
502  case Hexagon::A4_cmpheqi:
503  case Hexagon::A4_cmphgti:
504  case Hexagon::A4_cmphgtui:
505  SrcReg = MI->getOperand(1).getReg();
506  Mask = 0xFFFF;
507  break;
508  }
509 
510  // Set the value/second source register.
511  switch (Opc) {
512  case Hexagon::C2_cmpeq:
513  case Hexagon::C2_cmpeqp:
514  case Hexagon::C2_cmpgt:
515  case Hexagon::C2_cmpgtp:
516  case Hexagon::C2_cmpgtu:
517  case Hexagon::C2_cmpgtup:
518  case Hexagon::A4_cmpbeq:
519  case Hexagon::A4_cmpbgt:
520  case Hexagon::A4_cmpbgtu:
521  case Hexagon::A4_cmpheq:
522  case Hexagon::A4_cmphgt:
523  case Hexagon::A4_cmphgtu:
524  case Hexagon::C4_cmpneq:
525  case Hexagon::C4_cmplte:
526  case Hexagon::C4_cmplteu:
527  SrcReg2 = MI->getOperand(2).getReg();
528  return true;
529 
530  case Hexagon::C2_cmpeqi:
531  case Hexagon::C2_cmpgtui:
532  case Hexagon::C2_cmpgti:
533  case Hexagon::C4_cmpneqi:
534  case Hexagon::C4_cmplteui:
535  case Hexagon::C4_cmpltei:
536  case Hexagon::A4_cmpbeqi:
537  case Hexagon::A4_cmpbgti:
538  case Hexagon::A4_cmpbgtui:
539  case Hexagon::A4_cmpheqi:
540  case Hexagon::A4_cmphgti:
541  case Hexagon::A4_cmphgtui:
542  SrcReg2 = 0;
543  Value = MI->getOperand(2).getImm();
544  return true;
545  }
546 
547  return false;
548 }
549 
550 
553  unsigned DestReg, unsigned SrcReg,
554  bool KillSrc) const {
555  if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
556  BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), DestReg).addReg(SrcReg);
557  return;
558  }
559  if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
560  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrp), DestReg).addReg(SrcReg);
561  return;
562  }
563  if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
564  // Map Pd = Ps to Pd = or(Ps, Ps).
565  BuildMI(MBB, I, DL, get(Hexagon::C2_or),
566  DestReg).addReg(SrcReg).addReg(SrcReg);
567  return;
568  }
569  if (Hexagon::DoubleRegsRegClass.contains(DestReg) &&
570  Hexagon::IntRegsRegClass.contains(SrcReg)) {
571  // We can have an overlap between single and double reg: r1:0 = r0.
572  if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) {
573  // r1:0 = r0
574  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrsi), (RI.getSubReg(DestReg,
575  Hexagon::subreg_hireg))).addImm(0);
576  } else {
577  // r1:0 = r1 or no overlap.
578  BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), (RI.getSubReg(DestReg,
579  Hexagon::subreg_loreg))).addReg(SrcReg);
580  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrsi), (RI.getSubReg(DestReg,
581  Hexagon::subreg_hireg))).addImm(0);
582  }
583  return;
584  }
585  if (Hexagon::CtrRegsRegClass.contains(DestReg) &&
586  Hexagon::IntRegsRegClass.contains(SrcReg)) {
587  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg).addReg(SrcReg);
588  return;
589  }
590  if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
591  Hexagon::IntRegsRegClass.contains(DestReg)) {
592  BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg).
593  addReg(SrcReg, getKillRegState(KillSrc));
594  return;
595  }
596  if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
597  Hexagon::PredRegsRegClass.contains(DestReg)) {
598  BuildMI(MBB, I, DL, get(Hexagon::C2_tfrrp), DestReg).
599  addReg(SrcReg, getKillRegState(KillSrc));
600  return;
601  }
602 
603  llvm_unreachable("Unimplemented");
604 }
605 
606 
609  unsigned SrcReg, bool isKill, int FI,
610  const TargetRegisterClass *RC,
611  const TargetRegisterInfo *TRI) const {
612 
613  DebugLoc DL = MBB.findDebugLoc(I);
614  MachineFunction &MF = *MBB.getParent();
615  MachineFrameInfo &MFI = *MF.getFrameInfo();
616  unsigned Align = MFI.getObjectAlignment(FI);
617 
618  MachineMemOperand *MMO =
622  MFI.getObjectSize(FI),
623  Align);
624 
625  if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
626  BuildMI(MBB, I, DL, get(Hexagon::S2_storeri_io))
627  .addFrameIndex(FI).addImm(0)
628  .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
629  } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
630  BuildMI(MBB, I, DL, get(Hexagon::S2_storerd_io))
631  .addFrameIndex(FI).addImm(0)
632  .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
633  } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
634  BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
635  .addFrameIndex(FI).addImm(0)
636  .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
637  } else {
638  llvm_unreachable("Unimplemented");
639  }
640 }
641 
642 
644  MachineFunction &MF, unsigned SrcReg,
645  bool isKill,
647  const TargetRegisterClass *RC,
648  SmallVectorImpl<MachineInstr*> &NewMIs) const
649 {
650  llvm_unreachable("Unimplemented");
651 }
652 
653 
656  unsigned DestReg, int FI,
657  const TargetRegisterClass *RC,
658  const TargetRegisterInfo *TRI) const {
659  DebugLoc DL = MBB.findDebugLoc(I);
660  MachineFunction &MF = *MBB.getParent();
661  MachineFrameInfo &MFI = *MF.getFrameInfo();
662  unsigned Align = MFI.getObjectAlignment(FI);
663 
664  MachineMemOperand *MMO =
668  MFI.getObjectSize(FI),
669  Align);
670  if (RC == &Hexagon::IntRegsRegClass) {
671  BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg)
672  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
673  } else if (RC == &Hexagon::DoubleRegsRegClass) {
674  BuildMI(MBB, I, DL, get(Hexagon::L2_loadrd_io), DestReg)
675  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
676  } else if (RC == &Hexagon::PredRegsRegClass) {
677  BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
678  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
679  } else {
680  llvm_unreachable("Can't store this register to stack slot");
681  }
682 }
683 
684 
687  const TargetRegisterClass *RC,
688  SmallVectorImpl<MachineInstr*> &NewMIs) const {
689  llvm_unreachable("Unimplemented");
690 }
691 bool
693  const HexagonRegisterInfo &TRI = getRegisterInfo();
694  MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
695  MachineBasicBlock &MBB = *MI->getParent();
696  DebugLoc DL = MI->getDebugLoc();
697  unsigned Opc = MI->getOpcode();
698 
699  switch (Opc) {
700  case Hexagon::ALIGNA:
701  BuildMI(MBB, MI, DL, get(Hexagon::A2_andir), MI->getOperand(0).getReg())
702  .addReg(TRI.getFrameRegister())
703  .addImm(-MI->getOperand(1).getImm());
704  MBB.erase(MI);
705  return true;
706  case Hexagon::TFR_PdTrue: {
707  unsigned Reg = MI->getOperand(0).getReg();
708  BuildMI(MBB, MI, DL, get(Hexagon::C2_orn), Reg)
709  .addReg(Reg, RegState::Undef)
710  .addReg(Reg, RegState::Undef);
711  MBB.erase(MI);
712  return true;
713  }
714  case Hexagon::TFR_PdFalse: {
715  unsigned Reg = MI->getOperand(0).getReg();
716  BuildMI(MBB, MI, DL, get(Hexagon::C2_andn), Reg)
717  .addReg(Reg, RegState::Undef)
718  .addReg(Reg, RegState::Undef);
719  MBB.erase(MI);
720  return true;
721  }
722  case Hexagon::VMULW: {
723  // Expand a 64-bit vector multiply into 2 32-bit scalar multiplies.
724  unsigned DstReg = MI->getOperand(0).getReg();
725  unsigned Src1Reg = MI->getOperand(1).getReg();
726  unsigned Src2Reg = MI->getOperand(2).getReg();
727  unsigned Src1SubHi = TRI.getSubReg(Src1Reg, Hexagon::subreg_hireg);
728  unsigned Src1SubLo = TRI.getSubReg(Src1Reg, Hexagon::subreg_loreg);
729  unsigned Src2SubHi = TRI.getSubReg(Src2Reg, Hexagon::subreg_hireg);
730  unsigned Src2SubLo = TRI.getSubReg(Src2Reg, Hexagon::subreg_loreg);
731  BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_mpyi),
732  TRI.getSubReg(DstReg, Hexagon::subreg_hireg)).addReg(Src1SubHi)
733  .addReg(Src2SubHi);
734  BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_mpyi),
735  TRI.getSubReg(DstReg, Hexagon::subreg_loreg)).addReg(Src1SubLo)
736  .addReg(Src2SubLo);
737  MBB.erase(MI);
738  MRI.clearKillFlags(Src1SubHi);
739  MRI.clearKillFlags(Src1SubLo);
740  MRI.clearKillFlags(Src2SubHi);
741  MRI.clearKillFlags(Src2SubLo);
742  return true;
743  }
744  case Hexagon::VMULW_ACC: {
745  // Expand 64-bit vector multiply with addition into 2 scalar multiplies.
746  unsigned DstReg = MI->getOperand(0).getReg();
747  unsigned Src1Reg = MI->getOperand(1).getReg();
748  unsigned Src2Reg = MI->getOperand(2).getReg();
749  unsigned Src3Reg = MI->getOperand(3).getReg();
750  unsigned Src1SubHi = TRI.getSubReg(Src1Reg, Hexagon::subreg_hireg);
751  unsigned Src1SubLo = TRI.getSubReg(Src1Reg, Hexagon::subreg_loreg);
752  unsigned Src2SubHi = TRI.getSubReg(Src2Reg, Hexagon::subreg_hireg);
753  unsigned Src2SubLo = TRI.getSubReg(Src2Reg, Hexagon::subreg_loreg);
754  unsigned Src3SubHi = TRI.getSubReg(Src3Reg, Hexagon::subreg_hireg);
755  unsigned Src3SubLo = TRI.getSubReg(Src3Reg, Hexagon::subreg_loreg);
756  BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_maci),
757  TRI.getSubReg(DstReg, Hexagon::subreg_hireg)).addReg(Src1SubHi)
758  .addReg(Src2SubHi).addReg(Src3SubHi);
759  BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_maci),
760  TRI.getSubReg(DstReg, Hexagon::subreg_loreg)).addReg(Src1SubLo)
761  .addReg(Src2SubLo).addReg(Src3SubLo);
762  MBB.erase(MI);
763  MRI.clearKillFlags(Src1SubHi);
764  MRI.clearKillFlags(Src1SubLo);
765  MRI.clearKillFlags(Src2SubHi);
766  MRI.clearKillFlags(Src2SubLo);
767  MRI.clearKillFlags(Src3SubHi);
768  MRI.clearKillFlags(Src3SubLo);
769  return true;
770  }
771  case Hexagon::TCRETURNi:
772  MI->setDesc(get(Hexagon::J2_jump));
773  return true;
774  case Hexagon::TCRETURNr:
775  MI->setDesc(get(Hexagon::J2_jumpr));
776  return true;
777  }
778 
779  return false;
780 }
781 
784  MachineBasicBlock::iterator InsertPt, int FI) const {
785  // Hexagon_TODO: Implement.
786  return nullptr;
787 }
788 
790 
791  MachineRegisterInfo &RegInfo = MF->getRegInfo();
792  const TargetRegisterClass *TRC;
793  if (VT == MVT::i1) {
794  TRC = &Hexagon::PredRegsRegClass;
795  } else if (VT == MVT::i32 || VT == MVT::f32) {
796  TRC = &Hexagon::IntRegsRegClass;
797  } else if (VT == MVT::i64 || VT == MVT::f64) {
798  TRC = &Hexagon::DoubleRegsRegClass;
799  } else {
800  llvm_unreachable("Cannot handle this register class");
801  }
802 
803  unsigned NewReg = RegInfo.createVirtualRegister(TRC);
804  return NewReg;
805 }
806 
808  const MCInstrDesc &MID = MI->getDesc();
809  const uint64_t F = MID.TSFlags;
811  return true;
812 
813  // TODO: This is largely obsolete now. Will need to be removed
814  // in consecutive patches.
815  switch(MI->getOpcode()) {
816  // TFR_FI Remains a special case.
817  case Hexagon::TFR_FI:
818  return true;
819  default:
820  return false;
821  }
822  return false;
823 }
824 
825 // This returns true in two cases:
826 // - The OP code itself indicates that this is an extended instruction.
827 // - One of MOs has been marked with HMOTF_ConstExtended flag.
829  // First check if this is permanently extended op code.
830  const uint64_t F = MI->getDesc().TSFlags;
832  return true;
833  // Use MO operand flags to determine if one of MI's operands
834  // has HMOTF_ConstExtended flag set.
836  E = MI->operands_end(); I != E; ++I) {
837  if (I->getTargetFlags() && HexagonII::HMOTF_ConstExtended)
838  return true;
839  }
840  return false;
841 }
842 
844  return MI->getDesc().isBranch();
845 }
846 
848  if (isNewValueJump(MI))
849  return true;
850 
851  if (isNewValueStore(MI))
852  return true;
853 
854  return false;
855 }
856 
858  const uint64_t F = MI->getDesc().TSFlags;
860 }
861 
863  const uint64_t F = get(Opcode).TSFlags;
865 }
866 
868  return MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4;
869 }
870 
872  bool isPred = MI->getDesc().isPredicable();
873 
874  if (!isPred)
875  return false;
876 
877  const int Opc = MI->getOpcode();
878 
879  switch(Opc) {
880  case Hexagon::A2_tfrsi:
881  return (isOperandExtended(MI, 1) && isConstExtended(MI)) || isInt<12>(MI->getOperand(1).getImm());
882 
883  case Hexagon::S2_storerd_io:
884  return isShiftedUInt<6,3>(MI->getOperand(1).getImm());
885 
886  case Hexagon::S2_storeri_io:
887  case Hexagon::S2_storerinew_io:
888  return isShiftedUInt<6,2>(MI->getOperand(1).getImm());
889 
890  case Hexagon::S2_storerh_io:
891  case Hexagon::S2_storerhnew_io:
892  return isShiftedUInt<6,1>(MI->getOperand(1).getImm());
893 
894  case Hexagon::S2_storerb_io:
895  case Hexagon::S2_storerbnew_io:
896  return isUInt<6>(MI->getOperand(1).getImm());
897 
898  case Hexagon::L2_loadrd_io:
899  return isShiftedUInt<6,3>(MI->getOperand(2).getImm());
900 
901  case Hexagon::L2_loadri_io:
902  return isShiftedUInt<6,2>(MI->getOperand(2).getImm());
903 
904  case Hexagon::L2_loadrh_io:
905  case Hexagon::L2_loadruh_io:
906  return isShiftedUInt<6,1>(MI->getOperand(2).getImm());
907 
908  case Hexagon::L2_loadrb_io:
909  case Hexagon::L2_loadrub_io:
910  return isUInt<6>(MI->getOperand(2).getImm());
911 
912  case Hexagon::L2_loadrd_pi:
913  return isShiftedInt<4,3>(MI->getOperand(3).getImm());
914 
915  case Hexagon::L2_loadri_pi:
916  return isShiftedInt<4,2>(MI->getOperand(3).getImm());
917 
918  case Hexagon::L2_loadrh_pi:
919  case Hexagon::L2_loadruh_pi:
920  return isShiftedInt<4,1>(MI->getOperand(3).getImm());
921 
922  case Hexagon::L2_loadrb_pi:
923  case Hexagon::L2_loadrub_pi:
924  return isInt<4>(MI->getOperand(3).getImm());
925 
926  case Hexagon::S4_storeirb_io:
927  case Hexagon::S4_storeirh_io:
928  case Hexagon::S4_storeiri_io:
929  return (isUInt<6>(MI->getOperand(1).getImm()) &&
930  isInt<6>(MI->getOperand(2).getImm()));
931 
932  case Hexagon::A2_addi:
933  return isInt<8>(MI->getOperand(2).getImm());
934 
935  case Hexagon::A2_aslh:
936  case Hexagon::A2_asrh:
937  case Hexagon::A2_sxtb:
938  case Hexagon::A2_sxth:
939  case Hexagon::A2_zxtb:
940  case Hexagon::A2_zxth:
941  return true;
942  }
943 
944  return true;
945 }
946 
947 // This function performs the following inversiones:
948 //
949 // cPt ---> cNotPt
950 // cNotPt ---> cPt
951 //
952 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
953  int InvPredOpcode;
954  InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc)
955  : Hexagon::getTruePredOpcode(Opc);
956  if (InvPredOpcode >= 0) // Valid instruction with the inverted predicate.
957  return InvPredOpcode;
958 
959  switch(Opc) {
960  default: llvm_unreachable("Unexpected predicated instruction");
961  case Hexagon::C2_ccombinewt:
962  return Hexagon::C2_ccombinewf;
963  case Hexagon::C2_ccombinewf:
964  return Hexagon::C2_ccombinewt;
965 
966  // Dealloc_return.
967  case Hexagon::L4_return_t:
968  return Hexagon::L4_return_f;
969  case Hexagon::L4_return_f:
970  return Hexagon::L4_return_t;
971  }
972 }
973 
974 // New Value Store instructions.
976  const uint64_t F = MI->getDesc().TSFlags;
977 
979 }
980 
981 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
982  const uint64_t F = get(Opcode).TSFlags;
983 
985 }
986 
987 int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const {
988  enum Hexagon::PredSense inPredSense;
989  inPredSense = invertPredicate ? Hexagon::PredSense_false :
990  Hexagon::PredSense_true;
991  int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
992  if (CondOpcode >= 0) // Valid Conditional opcode/instruction
993  return CondOpcode;
994 
995  // This switch case will be removed once all the instructions have been
996  // modified to use relation maps.
997  switch(Opc) {
998  case Hexagon::TFRI_f:
999  return !invertPredicate ? Hexagon::TFRI_cPt_f :
1000  Hexagon::TFRI_cNotPt_f;
1001  case Hexagon::A2_combinew:
1002  return !invertPredicate ? Hexagon::C2_ccombinewt :
1003  Hexagon::C2_ccombinewf;
1004 
1005  // DEALLOC_RETURN.
1006  case Hexagon::L4_return:
1007  return !invertPredicate ? Hexagon::L4_return_t:
1008  Hexagon::L4_return_f;
1009  }
1010  llvm_unreachable("Unexpected predicable instruction");
1011 }
1012 
1013 
1014 bool HexagonInstrInfo::
1016  ArrayRef<MachineOperand> Cond) const {
1017  if (Cond.empty() || isEndLoopN(Cond[0].getImm())) {
1018  DEBUG(dbgs() << "\nCannot predicate:"; MI->dump(););
1019  return false;
1020  }
1021  int Opc = MI->getOpcode();
1022  assert (isPredicable(MI) && "Expected predicable instruction");
1023  bool invertJump = predOpcodeHasNot(Cond);
1024 
1025  // We have to predicate MI "in place", i.e. after this function returns,
1026  // MI will need to be transformed into a predicated form. To avoid com-
1027  // plicated manipulations with the operands (handling tied operands,
1028  // etc.), build a new temporary instruction, then overwrite MI with it.
1029 
1030  MachineBasicBlock &B = *MI->getParent();
1031  DebugLoc DL = MI->getDebugLoc();
1032  unsigned PredOpc = getCondOpcode(Opc, invertJump);
1033  MachineInstrBuilder T = BuildMI(B, MI, DL, get(PredOpc));
1034  unsigned NOp = 0, NumOps = MI->getNumOperands();
1035  while (NOp < NumOps) {
1036  MachineOperand &Op = MI->getOperand(NOp);
1037  if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
1038  break;
1039  T.addOperand(Op);
1040  NOp++;
1041  }
1042 
1043  unsigned PredReg, PredRegPos, PredRegFlags;
1044  bool GotPredReg = getPredReg(Cond, PredReg, PredRegPos, PredRegFlags);
1045  (void)GotPredReg;
1046  assert(GotPredReg);
1047  T.addReg(PredReg, PredRegFlags);
1048  while (NOp < NumOps)
1049  T.addOperand(MI->getOperand(NOp++));
1050 
1051  MI->setDesc(get(PredOpc));
1052  while (unsigned n = MI->getNumOperands())
1053  MI->RemoveOperand(n-1);
1054  for (unsigned i = 0, n = T->getNumOperands(); i < n; ++i)
1055  MI->addOperand(T->getOperand(i));
1056 
1058  B.erase(TI);
1059 
1061  MRI.clearKillFlags(PredReg);
1062 
1063  return true;
1064 }
1065 
1066 
1067 bool
1070  unsigned NumCycles,
1071  unsigned ExtraPredCycles,
1072  const BranchProbability &Probability) const {
1073  return true;
1074 }
1075 
1076 
1077 bool
1080  unsigned NumTCycles,
1081  unsigned ExtraTCycles,
1082  MachineBasicBlock &FMBB,
1083  unsigned NumFCycles,
1084  unsigned ExtraFCycles,
1085  const BranchProbability &Probability) const {
1086  return true;
1087 }
1088 
1089 // Returns true if an instruction is predicated irrespective of the predicate
1090 // sense. For example, all of the following will return true.
1091 // if (p0) R1 = add(R2, R3)
1092 // if (!p0) R1 = add(R2, R3)
1093 // if (p0.new) R1 = add(R2, R3)
1094 // if (!p0.new) R1 = add(R2, R3)
1096  const uint64_t F = MI->getDesc().TSFlags;
1097 
1099 }
1100 
1101 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
1102  const uint64_t F = get(Opcode).TSFlags;
1103 
1105 }
1106 
1108  const uint64_t F = MI->getDesc().TSFlags;
1109 
1110  assert(isPredicated(MI));
1111  return (!((F >> HexagonII::PredicatedFalsePos) &
1113 }
1114 
1115 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
1116  const uint64_t F = get(Opcode).TSFlags;
1117 
1118  // Make sure that the instruction is predicated.
1120  return (!((F >> HexagonII::PredicatedFalsePos) &
1122 }
1123 
1125  const uint64_t F = MI->getDesc().TSFlags;
1126 
1127  assert(isPredicated(MI));
1129 }
1130 
1131 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
1132  const uint64_t F = get(Opcode).TSFlags;
1133 
1134  assert(isPredicated(Opcode));
1136 }
1137 
1138 // Returns true, if a ST insn can be promoted to a new-value store.
1140  const uint64_t F = MI->getDesc().TSFlags;
1141 
1142  return ((F >> HexagonII::mayNVStorePos) &
1144 }
1145 
1146 bool
1148  std::vector<MachineOperand> &Pred) const {
1149  for (unsigned oper = 0; oper < MI->getNumOperands(); ++oper) {
1150  MachineOperand MO = MI->getOperand(oper);
1151  if (MO.isReg() && MO.isDef()) {
1152  const TargetRegisterClass* RC = RI.getMinimalPhysRegClass(MO.getReg());
1153  if (RC == &Hexagon::PredRegsRegClass) {
1154  Pred.push_back(MO);
1155  return true;
1156  }
1157  }
1158  }
1159  return false;
1160 }
1161 
1162 
1163 bool
1166  ArrayRef<MachineOperand> Pred2) const {
1167  // TODO: Fix this
1168  return false;
1169 }
1170 
1171 
1172 //
1173 // We indicate that we want to reverse the branch by
1174 // inserting the reversed branching opcode.
1175 //
1177  SmallVectorImpl<MachineOperand> &Cond) const {
1178  if (Cond.empty())
1179  return true;
1180  assert(Cond[0].isImm() && "First entry in the cond vector not imm-val");
1181  Opcode_t opcode = Cond[0].getImm();
1182  //unsigned temp;
1183  assert(get(opcode).isBranch() && "Should be a branching condition.");
1184  if (isEndLoopN(opcode))
1185  return true;
1186  Opcode_t NewOpcode = getInvertedPredicatedOpcode(opcode);
1187  Cond[0].setImm(NewOpcode);
1188  return false;
1189 }
1190 
1191 
1192 bool HexagonInstrInfo::
1194  const BranchProbability &Probability) const {
1195  return (NumInstrs <= 4);
1196 }
1197 
1199  switch (MI->getOpcode()) {
1200  default: return false;
1201  case Hexagon::L4_return:
1202  case Hexagon::L4_return_t:
1203  case Hexagon::L4_return_f:
1204  case Hexagon::L4_return_tnew_pnt:
1205  case Hexagon::L4_return_fnew_pnt:
1206  case Hexagon::L4_return_tnew_pt:
1207  case Hexagon::L4_return_fnew_pt:
1208  return true;
1209  }
1210 }
1211 
1212 
1213 bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset,
1214  bool Extend) const {
1215  // This function is to check whether the "Offset" is in the correct range of
1216  // the given "Opcode". If "Offset" is not in the correct range, "A2_addi" is
1217  // inserted to calculate the final address. Due to this reason, the function
1218  // assumes that the "Offset" has correct alignment.
1219  // We used to assert if the offset was not properly aligned, however,
1220  // there are cases where a misaligned pointer recast can cause this
1221  // problem, and we need to allow for it. The front end warns of such
1222  // misaligns with respect to load size.
1223 
1224  switch (Opcode) {
1225  case Hexagon::J2_loop0i:
1226  case Hexagon::J2_loop1i:
1227  return isUInt<10>(Offset);
1228  }
1229 
1230  if (Extend)
1231  return true;
1232 
1233  switch (Opcode) {
1234  case Hexagon::L2_loadri_io:
1235  case Hexagon::S2_storeri_io:
1236  return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
1237  (Offset <= Hexagon_MEMW_OFFSET_MAX);
1238 
1239  case Hexagon::L2_loadrd_io:
1240  case Hexagon::S2_storerd_io:
1241  return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
1242  (Offset <= Hexagon_MEMD_OFFSET_MAX);
1243 
1244  case Hexagon::L2_loadrh_io:
1245  case Hexagon::L2_loadruh_io:
1246  case Hexagon::S2_storerh_io:
1247  return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
1248  (Offset <= Hexagon_MEMH_OFFSET_MAX);
1249 
1250  case Hexagon::L2_loadrb_io:
1251  case Hexagon::S2_storerb_io:
1252  case Hexagon::L2_loadrub_io:
1253  return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
1254  (Offset <= Hexagon_MEMB_OFFSET_MAX);
1255 
1256  case Hexagon::A2_addi:
1257  return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
1258  (Offset <= Hexagon_ADDI_OFFSET_MAX);
1259 
1260  case Hexagon::L4_iadd_memopw_io:
1261  case Hexagon::L4_isub_memopw_io:
1262  case Hexagon::L4_add_memopw_io:
1263  case Hexagon::L4_sub_memopw_io:
1264  case Hexagon::L4_and_memopw_io:
1265  case Hexagon::L4_or_memopw_io:
1266  return (0 <= Offset && Offset <= 255);
1267 
1268  case Hexagon::L4_iadd_memoph_io:
1269  case Hexagon::L4_isub_memoph_io:
1270  case Hexagon::L4_add_memoph_io:
1271  case Hexagon::L4_sub_memoph_io:
1272  case Hexagon::L4_and_memoph_io:
1273  case Hexagon::L4_or_memoph_io:
1274  return (0 <= Offset && Offset <= 127);
1275 
1276  case Hexagon::L4_iadd_memopb_io:
1277  case Hexagon::L4_isub_memopb_io:
1278  case Hexagon::L4_add_memopb_io:
1279  case Hexagon::L4_sub_memopb_io:
1280  case Hexagon::L4_and_memopb_io:
1281  case Hexagon::L4_or_memopb_io:
1282  return (0 <= Offset && Offset <= 63);
1283 
1284  // LDri_pred and STriw_pred are pseudo operations, so it has to take offset of
1285  // any size. Later pass knows how to handle it.
1286  case Hexagon::STriw_pred:
1287  case Hexagon::LDriw_pred:
1288  return true;
1289 
1290  case Hexagon::TFR_FI:
1291  case Hexagon::TFR_FIA:
1292  case Hexagon::INLINEASM:
1293  return true;
1294  }
1295 
1296  llvm_unreachable("No offset range is defined for this opcode. "
1297  "Please define it in the above switch statement!");
1298 }
1299 
1300 
1301 //
1302 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
1303 //
1304 bool HexagonInstrInfo::
1305 isValidAutoIncImm(const EVT VT, const int Offset) const {
1306 
1307  if (VT == MVT::i64) {
1308  return (Offset >= Hexagon_MEMD_AUTOINC_MIN &&
1309  Offset <= Hexagon_MEMD_AUTOINC_MAX &&
1310  (Offset & 0x7) == 0);
1311  }
1312  if (VT == MVT::i32) {
1313  return (Offset >= Hexagon_MEMW_AUTOINC_MIN &&
1314  Offset <= Hexagon_MEMW_AUTOINC_MAX &&
1315  (Offset & 0x3) == 0);
1316  }
1317  if (VT == MVT::i16) {
1318  return (Offset >= Hexagon_MEMH_AUTOINC_MIN &&
1319  Offset <= Hexagon_MEMH_AUTOINC_MAX &&
1320  (Offset & 0x1) == 0);
1321  }
1322  if (VT == MVT::i8) {
1323  return (Offset >= Hexagon_MEMB_AUTOINC_MIN &&
1324  Offset <= Hexagon_MEMB_AUTOINC_MAX);
1325  }
1326  llvm_unreachable("Not an auto-inc opc!");
1327 }
1328 
1329 
1330 bool HexagonInstrInfo::
1331 isMemOp(const MachineInstr *MI) const {
1332 // return MI->getDesc().mayLoad() && MI->getDesc().mayStore();
1333 
1334  switch (MI->getOpcode())
1335  {
1336  default: return false;
1337  case Hexagon::L4_iadd_memopw_io:
1338  case Hexagon::L4_isub_memopw_io:
1339  case Hexagon::L4_add_memopw_io:
1340  case Hexagon::L4_sub_memopw_io:
1341  case Hexagon::L4_and_memopw_io:
1342  case Hexagon::L4_or_memopw_io:
1343  case Hexagon::L4_iadd_memoph_io:
1344  case Hexagon::L4_isub_memoph_io:
1345  case Hexagon::L4_add_memoph_io:
1346  case Hexagon::L4_sub_memoph_io:
1347  case Hexagon::L4_and_memoph_io:
1348  case Hexagon::L4_or_memoph_io:
1349  case Hexagon::L4_iadd_memopb_io:
1350  case Hexagon::L4_isub_memopb_io:
1351  case Hexagon::L4_add_memopb_io:
1352  case Hexagon::L4_sub_memopb_io:
1353  case Hexagon::L4_and_memopb_io:
1354  case Hexagon::L4_or_memopb_io:
1355  case Hexagon::L4_ior_memopb_io:
1356  case Hexagon::L4_ior_memoph_io:
1357  case Hexagon::L4_ior_memopw_io:
1358  case Hexagon::L4_iand_memopb_io:
1359  case Hexagon::L4_iand_memoph_io:
1360  case Hexagon::L4_iand_memopw_io:
1361  return true;
1362  }
1363  return false;
1364 }
1365 
1366 
1367 bool HexagonInstrInfo::
1369  switch (MI->getOpcode()) {
1370  default: return false;
1371  case Hexagon::STriw_pred :
1372  case Hexagon::LDriw_pred :
1373  return true;
1374  }
1375 }
1376 
1378  switch (MI->getOpcode()) {
1379  default: return false;
1380  case Hexagon::C2_cmpeq:
1381  case Hexagon::C2_cmpeqi:
1382  case Hexagon::C2_cmpgt:
1383  case Hexagon::C2_cmpgti:
1384  case Hexagon::C2_cmpgtu:
1385  case Hexagon::C2_cmpgtui:
1386  return true;
1387  }
1388 }
1389 
1390 bool HexagonInstrInfo::
1392  switch (MI->getOpcode()) {
1393  default: return false;
1394  case Hexagon::A2_tfrt:
1395  case Hexagon::A2_tfrf:
1396  case Hexagon::C2_cmoveit:
1397  case Hexagon::C2_cmoveif:
1398  case Hexagon::A2_tfrtnew:
1399  case Hexagon::A2_tfrfnew:
1400  case Hexagon::C2_cmovenewit:
1401  case Hexagon::C2_cmovenewif:
1402  return true;
1403  }
1404 }
1405 
1407  switch (MI->getOpcode())
1408  {
1409  default: return false;
1410  case Hexagon::A2_paddf:
1411  case Hexagon::A2_paddfnew:
1412  case Hexagon::A2_paddt:
1413  case Hexagon::A2_paddtnew:
1414  case Hexagon::A2_pandf:
1415  case Hexagon::A2_pandfnew:
1416  case Hexagon::A2_pandt:
1417  case Hexagon::A2_pandtnew:
1418  case Hexagon::A4_paslhf:
1419  case Hexagon::A4_paslhfnew:
1420  case Hexagon::A4_paslht:
1421  case Hexagon::A4_paslhtnew:
1422  case Hexagon::A4_pasrhf:
1423  case Hexagon::A4_pasrhfnew:
1424  case Hexagon::A4_pasrht:
1425  case Hexagon::A4_pasrhtnew:
1426  case Hexagon::A2_porf:
1427  case Hexagon::A2_porfnew:
1428  case Hexagon::A2_port:
1429  case Hexagon::A2_portnew:
1430  case Hexagon::A2_psubf:
1431  case Hexagon::A2_psubfnew:
1432  case Hexagon::A2_psubt:
1433  case Hexagon::A2_psubtnew:
1434  case Hexagon::A2_pxorf:
1435  case Hexagon::A2_pxorfnew:
1436  case Hexagon::A2_pxort:
1437  case Hexagon::A2_pxortnew:
1438  case Hexagon::A4_psxthf:
1439  case Hexagon::A4_psxthfnew:
1440  case Hexagon::A4_psxtht:
1441  case Hexagon::A4_psxthtnew:
1442  case Hexagon::A4_psxtbf:
1443  case Hexagon::A4_psxtbfnew:
1444  case Hexagon::A4_psxtbt:
1445  case Hexagon::A4_psxtbtnew:
1446  case Hexagon::A4_pzxtbf:
1447  case Hexagon::A4_pzxtbfnew:
1448  case Hexagon::A4_pzxtbt:
1449  case Hexagon::A4_pzxtbtnew:
1450  case Hexagon::A4_pzxthf:
1451  case Hexagon::A4_pzxthfnew:
1452  case Hexagon::A4_pzxtht:
1453  case Hexagon::A4_pzxthtnew:
1454  case Hexagon::A2_paddit:
1455  case Hexagon::A2_paddif:
1456  case Hexagon::C2_ccombinewt:
1457  case Hexagon::C2_ccombinewf:
1458  return true;
1459  }
1460 }
1461 
1462 bool HexagonInstrInfo::
1464  switch (MI->getOpcode())
1465  {
1466  default: return false;
1467  case Hexagon::L2_ploadrdt_io :
1468  case Hexagon::L2_ploadrdf_io:
1469  case Hexagon::L2_ploadrit_io:
1470  case Hexagon::L2_ploadrif_io:
1471  case Hexagon::L2_ploadrht_io:
1472  case Hexagon::L2_ploadrhf_io:
1473  case Hexagon::L2_ploadrbt_io:
1474  case Hexagon::L2_ploadrbf_io:
1475  case Hexagon::L2_ploadruht_io:
1476  case Hexagon::L2_ploadruhf_io:
1477  case Hexagon::L2_ploadrubt_io:
1478  case Hexagon::L2_ploadrubf_io:
1479  case Hexagon::L2_ploadrdt_pi:
1480  case Hexagon::L2_ploadrdf_pi:
1481  case Hexagon::L2_ploadrit_pi:
1482  case Hexagon::L2_ploadrif_pi:
1483  case Hexagon::L2_ploadrht_pi:
1484  case Hexagon::L2_ploadrhf_pi:
1485  case Hexagon::L2_ploadrbt_pi:
1486  case Hexagon::L2_ploadrbf_pi:
1487  case Hexagon::L2_ploadruht_pi:
1488  case Hexagon::L2_ploadruhf_pi:
1489  case Hexagon::L2_ploadrubt_pi:
1490  case Hexagon::L2_ploadrubf_pi:
1491  case Hexagon::L4_ploadrdt_rr:
1492  case Hexagon::L4_ploadrdf_rr:
1493  case Hexagon::L4_ploadrbt_rr:
1494  case Hexagon::L4_ploadrbf_rr:
1495  case Hexagon::L4_ploadrubt_rr:
1496  case Hexagon::L4_ploadrubf_rr:
1497  case Hexagon::L4_ploadrht_rr:
1498  case Hexagon::L4_ploadrhf_rr:
1499  case Hexagon::L4_ploadruht_rr:
1500  case Hexagon::L4_ploadruhf_rr:
1501  case Hexagon::L4_ploadrit_rr:
1502  case Hexagon::L4_ploadrif_rr:
1503  return true;
1504  }
1505 }
1506 
1507 // Returns true if an instruction is a conditional store.
1508 //
1509 // Note: It doesn't include conditional new-value stores as they can't be
1510 // converted to .new predicate.
1511 //
1512 // p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
1513 // ^ ^
1514 // / \ (not OK. it will cause new-value store to be
1515 // / X conditional on p0.new while R2 producer is
1516 // / \ on p0)
1517 // / \.
1518 // p.new store p.old NV store
1519 // [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new]
1520 // ^ ^
1521 // \ /
1522 // \ /
1523 // \ /
1524 // p.old store
1525 // [if (p0)memw(R0+#0)=R2]
1526 //
1527 // The above diagram shows the steps involoved in the conversion of a predicated
1528 // store instruction to its .new predicated new-value form.
1529 //
1530 // The following set of instructions further explains the scenario where
1531 // conditional new-value store becomes invalid when promoted to .new predicate
1532 // form.
1533 //
1534 // { 1) if (p0) r0 = add(r1, r2)
1535 // 2) p0 = cmp.eq(r3, #0) }
1536 //
1537 // 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with
1538 // the first two instructions because in instr 1, r0 is conditional on old value
1539 // of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
1540 // is not valid for new-value stores.
1541 bool HexagonInstrInfo::
1543  switch (MI->getOpcode())
1544  {
1545  default: return false;
1546  case Hexagon::S4_storeirbt_io:
1547  case Hexagon::S4_storeirbf_io:
1548  case Hexagon::S4_pstorerbt_rr:
1549  case Hexagon::S4_pstorerbf_rr:
1550  case Hexagon::S2_pstorerbt_io:
1551  case Hexagon::S2_pstorerbf_io:
1552  case Hexagon::S2_pstorerbt_pi:
1553  case Hexagon::S2_pstorerbf_pi:
1554  case Hexagon::S2_pstorerdt_io:
1555  case Hexagon::S2_pstorerdf_io:
1556  case Hexagon::S4_pstorerdt_rr:
1557  case Hexagon::S4_pstorerdf_rr:
1558  case Hexagon::S2_pstorerdt_pi:
1559  case Hexagon::S2_pstorerdf_pi:
1560  case Hexagon::S2_pstorerht_io:
1561  case Hexagon::S2_pstorerhf_io:
1562  case Hexagon::S4_storeirht_io:
1563  case Hexagon::S4_storeirhf_io:
1564  case Hexagon::S4_pstorerht_rr:
1565  case Hexagon::S4_pstorerhf_rr:
1566  case Hexagon::S2_pstorerht_pi:
1567  case Hexagon::S2_pstorerhf_pi:
1568  case Hexagon::S2_pstorerit_io:
1569  case Hexagon::S2_pstorerif_io:
1570  case Hexagon::S4_storeirit_io:
1571  case Hexagon::S4_storeirif_io:
1572  case Hexagon::S4_pstorerit_rr:
1573  case Hexagon::S4_pstorerif_rr:
1574  case Hexagon::S2_pstorerit_pi:
1575  case Hexagon::S2_pstorerif_pi:
1576 
1577  // V4 global address store before promoting to dot new.
1578  case Hexagon::S4_pstorerdt_abs:
1579  case Hexagon::S4_pstorerdf_abs:
1580  case Hexagon::S4_pstorerbt_abs:
1581  case Hexagon::S4_pstorerbf_abs:
1582  case Hexagon::S4_pstorerht_abs:
1583  case Hexagon::S4_pstorerhf_abs:
1584  case Hexagon::S4_pstorerit_abs:
1585  case Hexagon::S4_pstorerif_abs:
1586  return true;
1587 
1588  // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
1589  // from the "Conditional Store" list. Because a predicated new value store
1590  // would NOT be promoted to a double dot new store. See diagram below:
1591  // This function returns yes for those stores that are predicated but not
1592  // yet promoted to predicate dot new instructions.
1593  //
1594  // +---------------------+
1595  // /-----| if (p0) memw(..)=r0 |---------\~
1596  // || +---------------------+ ||
1597  // promote || /\ /\ || promote
1598  // || /||\ /||\ ||
1599  // \||/ demote || \||/
1600  // \/ || || \/
1601  // +-------------------------+ || +-------------------------+
1602  // | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new |
1603  // +-------------------------+ || +-------------------------+
1604  // || || ||
1605  // || demote \||/
1606  // promote || \/ NOT possible
1607  // || || /\~
1608  // \||/ || /||\~
1609  // \/ || ||
1610  // +-----------------------------+
1611  // | if (p0.new) memw(..)=r0.new |
1612  // +-----------------------------+
1613  // Double Dot New Store
1614  //
1615  }
1616 }
1617 
1618 
1620  if (isNewValue(MI) && isBranch(MI))
1621  return true;
1622  return false;
1623 }
1624 
1626  return isNewValue(Opcode) && get(Opcode).isBranch() && isPredicated(Opcode);
1627 }
1628 
1630  return (getAddrMode(MI) == HexagonII::PostInc);
1631 }
1632 
1633 // Returns true, if any one of the operands is a dot new
1634 // insn, whether it is predicated dot new or register dot new.
1636  return (isNewValueInst(MI) ||
1637  (isPredicated(MI) && isPredicatedNew(MI)));
1638 }
1639 
1640 // Returns the most basic instruction for the .new predicated instructions and
1641 // new-value stores.
1642 // For example, all of the following instructions will be converted back to the
1643 // same instruction:
1644 // 1) if (p0.new) memw(R0+#0) = R1.new --->
1645 // 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1
1646 // 3) if (p0.new) memw(R0+#0) = R1 --->
1647 //
1648 
1649 int HexagonInstrInfo::GetDotOldOp(const int opc) const {
1650  int NewOp = opc;
1651  if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
1652  NewOp = Hexagon::getPredOldOpcode(NewOp);
1653  assert(NewOp >= 0 &&
1654  "Couldn't change predicate new instruction to its old form.");
1655  }
1656 
1657  if (isNewValueStore(NewOp)) { // Convert into non-new-value format
1658  NewOp = Hexagon::getNonNVStore(NewOp);
1659  assert(NewOp >= 0 && "Couldn't change new-value store to its old form.");
1660  }
1661  return NewOp;
1662 }
1663 
1664 // Return the new value instruction for a given store.
1666  int NVOpcode = Hexagon::getNewValueOpcode(MI->getOpcode());
1667  if (NVOpcode >= 0) // Valid new-value store instruction.
1668  return NVOpcode;
1669 
1670  switch (MI->getOpcode()) {
1671  default: llvm_unreachable("Unknown .new type");
1672  case Hexagon::S4_storerb_ur:
1673  return Hexagon::S4_storerbnew_ur;
1674 
1675  case Hexagon::S4_storerh_ur:
1676  return Hexagon::S4_storerhnew_ur;
1677 
1678  case Hexagon::S4_storeri_ur:
1679  return Hexagon::S4_storerinew_ur;
1680 
1681  case Hexagon::S2_storerb_pci:
1682  return Hexagon::S2_storerb_pci;
1683 
1684  case Hexagon::S2_storeri_pci:
1685  return Hexagon::S2_storeri_pci;
1686 
1687  case Hexagon::S2_storerh_pci:
1688  return Hexagon::S2_storerh_pci;
1689 
1690  case Hexagon::S2_storerd_pci:
1691  return Hexagon::S2_storerd_pci;
1692 
1693  case Hexagon::S2_storerf_pci:
1694  return Hexagon::S2_storerf_pci;
1695  }
1696  return 0;
1697 }
1698 
1699 // Return .new predicate version for an instruction.
1702  *MBPI) const {
1703 
1704  int NewOpcode = Hexagon::getPredNewOpcode(MI->getOpcode());
1705  if (NewOpcode >= 0) // Valid predicate new instruction
1706  return NewOpcode;
1707 
1708  switch (MI->getOpcode()) {
1709  default: llvm_unreachable("Unknown .new type");
1710  // Condtional Jumps
1711  case Hexagon::J2_jumpt:
1712  case Hexagon::J2_jumpf:
1713  return getDotNewPredJumpOp(MI, MBPI);
1714 
1715  case Hexagon::J2_jumprt:
1716  return Hexagon::J2_jumptnewpt;
1717 
1718  case Hexagon::J2_jumprf:
1719  return Hexagon::J2_jumprfnewpt;
1720 
1721  case Hexagon::JMPrett:
1722  return Hexagon::J2_jumprtnewpt;
1723 
1724  case Hexagon::JMPretf:
1725  return Hexagon::J2_jumprfnewpt;
1726 
1727 
1728  // Conditional combine
1729  case Hexagon::C2_ccombinewt:
1730  return Hexagon::C2_ccombinewnewt;
1731  case Hexagon::C2_ccombinewf:
1732  return Hexagon::C2_ccombinewnewf;
1733  }
1734 }
1735 
1736 
1738  const uint64_t F = MI->getDesc().TSFlags;
1739 
1741 }
1742 
1743 /// immediateExtend - Changes the instruction in place to one using an immediate
1744 /// extender.
1746  assert((isExtendable(MI)||isConstExtended(MI)) &&
1747  "Instruction must be extendable");
1748  // Find which operand is extendable.
1749  short ExtOpNum = getCExtOpNum(MI);
1750  MachineOperand &MO = MI->getOperand(ExtOpNum);
1751  // This needs to be something we understand.
1752  assert((MO.isMBB() || MO.isImm()) &&
1753  "Branch with unknown extendable field type");
1754  // Mark given operand as extended.
1756 }
1757 
1759  const TargetSubtargetInfo &STI) const {
1760  const InstrItineraryData *II = STI.getInstrItineraryData();
1761  return static_cast<const HexagonSubtarget &>(STI).createDFAPacketizer(II);
1762 }
1763 
1765  const MachineBasicBlock *MBB,
1766  const MachineFunction &MF) const {
1767  // Debug info is never a scheduling boundary. It's necessary to be explicit
1768  // due to the special treatment of IT instructions below, otherwise a
1769  // dbg_value followed by an IT will result in the IT instruction being
1770  // considered a scheduling hazard, which is wrong. It should be the actual
1771  // instruction preceding the dbg_value instruction(s), just like it is
1772  // when debug info is not present.
1773  if (MI->isDebugValue())
1774  return false;
1775 
1776  // Terminators and labels can't be scheduled around.
1777  if (MI->getDesc().isTerminator() || MI->isPosition() || MI->isInlineAsm())
1778  return true;
1779 
1780  return false;
1781 }
1782 
1784  const uint64_t F = MI->getDesc().TSFlags;
1786  if (isExtended) // Instruction must be extended.
1787  return true;
1788 
1789  unsigned isExtendable =
1791  if (!isExtendable)
1792  return false;
1793 
1794  short ExtOpNum = getCExtOpNum(MI);
1795  const MachineOperand &MO = MI->getOperand(ExtOpNum);
1796  // Use MO operand flags to determine if MO
1797  // has the HMOTF_ConstExtended flag set.
1799  return true;
1800  // If this is a Machine BB address we are talking about, and it is
1801  // not marked as extended, say so.
1802  if (MO.isMBB())
1803  return false;
1804 
1805  // We could be using an instruction with an extendable immediate and shoehorn
1806  // a global address into it. If it is a global address it will be constant
1807  // extended. We do this for COMBINE.
1808  // We currently only handle isGlobal() because it is the only kind of
1809  // object we are going to end up with here for now.
1810  // In the future we probably should add isSymbol(), etc.
1811  if (MO.isGlobal() || MO.isSymbol() || MO.isBlockAddress() ||
1812  MO.isJTI() || MO.isCPI())
1813  return true;
1814 
1815  // If the extendable operand is not 'Immediate' type, the instruction should
1816  // have 'isExtended' flag set.
1817  assert(MO.isImm() && "Extendable operand must be Immediate type");
1818 
1819  int MinValue = getMinValue(MI);
1820  int MaxValue = getMaxValue(MI);
1821  int ImmValue = MO.getImm();
1822 
1823  return (ImmValue < MinValue || ImmValue > MaxValue);
1824 }
1825 
1826 // Return the number of bytes required to encode the instruction.
1827 // Hexagon instructions are fixed length, 4 bytes, unless they
1828 // use a constant extender, which requires another 4 bytes.
1829 // For debug instructions and prolog labels, return 0.
1831 
1832  if (MI->isDebugValue() || MI->isPosition())
1833  return 0;
1834 
1835  unsigned Size = MI->getDesc().getSize();
1836  if (!Size)
1837  // Assume the default insn size in case it cannot be determined
1838  // for whatever reason.
1839  Size = HEXAGON_INSTR_SIZE;
1840 
1841  if (isConstExtended(MI) || isExtended(MI))
1842  Size += HEXAGON_INSTR_SIZE;
1843 
1844  return Size;
1845 }
1846 
1847 // Returns the opcode to use when converting MI, which is a conditional jump,
1848 // into a conditional instruction which uses the .new value of the predicate.
1849 // We also use branch probabilities to add a hint to the jump.
1850 int
1852  const
1853  MachineBranchProbabilityInfo *MBPI) const {
1854 
1855  // We assume that block can have at most two successors.
1856  bool taken = false;
1857  MachineBasicBlock *Src = MI->getParent();
1858  MachineOperand *BrTarget = &MI->getOperand(1);
1859  MachineBasicBlock *Dst = BrTarget->getMBB();
1860 
1861  const BranchProbability Prediction = MBPI->getEdgeProbability(Src, Dst);
1862  if (Prediction >= BranchProbability(1,2))
1863  taken = true;
1864 
1865  switch (MI->getOpcode()) {
1866  case Hexagon::J2_jumpt:
1867  return taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
1868  case Hexagon::J2_jumpf:
1869  return taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
1870 
1871  default:
1872  llvm_unreachable("Unexpected jump instruction.");
1873  }
1874 }
1875 // Returns true if a particular operand is extendable for an instruction.
1877  unsigned short OperandNum) const {
1878  const uint64_t F = MI->getDesc().TSFlags;
1879 
1881  == OperandNum;
1882 }
1883 
1884 // Returns Operand Index for the constant extended instruction.
1885 unsigned short HexagonInstrInfo::getCExtOpNum(const MachineInstr *MI) const {
1886  const uint64_t F = MI->getDesc().TSFlags;
1888 }
1889 
1890 // Returns the min value that doesn't need to be extended.
1892  const uint64_t F = MI->getDesc().TSFlags;
1893  unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
1895  unsigned bits = (F >> HexagonII::ExtentBitsPos)
1897 
1898  if (isSigned) // if value is signed
1899  return -1U << (bits - 1);
1900  else
1901  return 0;
1902 }
1903 
1904 // Returns the max value that doesn't need to be extended.
1906  const uint64_t F = MI->getDesc().TSFlags;
1907  unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
1909  unsigned bits = (F >> HexagonII::ExtentBitsPos)
1911 
1912  if (isSigned) // if value is signed
1913  return ~(-1U << (bits - 1));
1914  else
1915  return ~(-1U << bits);
1916 }
1917 
1918 // Returns true if an instruction can be converted into a non-extended
1919 // equivalent instruction.
1921 
1922  short NonExtOpcode;
1923  // Check if the instruction has a register form that uses register in place
1924  // of the extended operand, if so return that as the non-extended form.
1925  if (Hexagon::getRegForm(MI->getOpcode()) >= 0)
1926  return true;
1927 
1928  if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
1929  // Check addressing mode and retrieve non-ext equivalent instruction.
1930 
1931  switch (getAddrMode(MI)) {
1932  case HexagonII::Absolute :
1933  // Load/store with absolute addressing mode can be converted into
1934  // base+offset mode.
1935  NonExtOpcode = Hexagon::getBasedWithImmOffset(MI->getOpcode());
1936  break;
1938  // Load/store with base+offset addressing mode can be converted into
1939  // base+register offset addressing mode. However left shift operand should
1940  // be set to 0.
1941  NonExtOpcode = Hexagon::getBaseWithRegOffset(MI->getOpcode());
1942  break;
1943  default:
1944  return false;
1945  }
1946  if (NonExtOpcode < 0)
1947  return false;
1948  return true;
1949  }
1950  return false;
1951 }
1952 
1953 // Returns opcode of the non-extended equivalent instruction.
1955 
1956  // Check if the instruction has a register form that uses register in place
1957  // of the extended operand, if so return that as the non-extended form.
1958  short NonExtOpcode = Hexagon::getRegForm(MI->getOpcode());
1959  if (NonExtOpcode >= 0)
1960  return NonExtOpcode;
1961 
1962  if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
1963  // Check addressing mode and retrieve non-ext equivalent instruction.
1964  switch (getAddrMode(MI)) {
1965  case HexagonII::Absolute :
1966  return Hexagon::getBasedWithImmOffset(MI->getOpcode());
1968  return Hexagon::getBaseWithRegOffset(MI->getOpcode());
1969  default:
1970  return -1;
1971  }
1972  }
1973  return -1;
1974 }
1975 
1977  return (Opcode == Hexagon::J2_jumpt) ||
1978  (Opcode == Hexagon::J2_jumpf) ||
1979  (Opcode == Hexagon::J2_jumptnewpt) ||
1980  (Opcode == Hexagon::J2_jumpfnewpt) ||
1981  (Opcode == Hexagon::J2_jumpt) ||
1982  (Opcode == Hexagon::J2_jumpf);
1983 }
1984 
1986  if (Cond.empty() || !isPredicated(Cond[0].getImm()))
1987  return false;
1988  return !isPredicatedTrue(Cond[0].getImm());
1989 }
1990 
1992  return (Opcode == Hexagon::ENDLOOP0 ||
1993  Opcode == Hexagon::ENDLOOP1);
1994 }
1995 
1997  unsigned &PredReg, unsigned &PredRegPos,
1998  unsigned &PredRegFlags) const {
1999  if (Cond.empty())
2000  return false;
2001  assert(Cond.size() == 2);
2002  if (isNewValueJump(Cond[0].getImm()) || Cond[1].isMBB()) {
2003  DEBUG(dbgs() << "No predregs for new-value jumps/endloop");
2004  return false;
2005  }
2006  PredReg = Cond[1].getReg();
2007  PredRegPos = 1;
2008  // See IfConversion.cpp why we add RegState::Implicit | RegState::Undef
2009  PredRegFlags = 0;
2010  if (Cond[1].isImplicit())
2011  PredRegFlags = RegState::Implicit;
2012  if (Cond[1].isUndef())
2013  PredRegFlags |= RegState::Undef;
2014  return true;
2015 }
2016 
static bool isReg(const MCInst &MI, unsigned OpNo)
bool isImplicit() const
bool isSpillPredRegOp(const MachineInstr *MI) const
bool isConditionalLoad(const MachineInstr *MI) const
The memory access reads data.
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
mop_iterator operands_end()
Definition: MachineInstr.h:290
bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
The memory access writes data.
instr_iterator instr_begin()
const int Hexagon_MEMH_OFFSET_MAX
instr_iterator instr_end()
const int Hexagon_ADDI_OFFSET_MAX
unsigned getFrameRegister(const MachineFunction &MF) const override
const int Hexagon_MEMH_OFFSET_MIN
bool isBranch(const MachineInstr *MI) const
bool isExtendable(const MachineInstr *MI) const
MachineBasicBlock * getMBB() const
int getNumber() const
getNumber - MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a M...
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override
bool mayStore() const
Return true if this instruction could possibly modify memory.
Definition: MCInstrDesc.h:356
iterator getFirstTerminator()
getFirstTerminator - returns an iterator to the first terminator instruction of this basic block...
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:138
int getMaxValue(const MachineInstr *MI) const
int getDotNewPredJumpOp(MachineInstr *MI, const MachineBranchProbabilityInfo *MBPI) const
const int Hexagon_ADDI_OFFSET_MIN
bool isBlockAddress() const
isBlockAddress - Tests if this is a MO_BlockAddress operand.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:264
A debug info location.
Definition: DebugLoc.h:34
F(f)
int getMinValue(const MachineInstr *MI) const
bool isEndLoopN(Opcode_t Opcode) const
const int Hexagon_MEMD_OFFSET_MAX
Instructions::iterator instr_iterator
unsigned short getCExtOpNum(const MachineInstr *MI) const
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, unsigned f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
getMachineMemOperand - Allocate a new MachineMemOperand.
bool PredicateInstruction(MachineInstr *MI, ArrayRef< MachineOperand > Cond) const override
bool isPostIncrement(const MachineInstr *MI) const
bool isConditionalTransfer(const MachineInstr *MI) const
bool isPredicatedNew(const MachineInstr *MI) const
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
bool isSchedulingBoundary(const MachineInstr *MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
MachineMemOperand - A description of a memory reference used in the backend.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const override
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot...
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
bool isMemOp(const MachineInstr *MI) const
bool isPredicated(const MachineInstr *MI) const override
unsigned getSize(const MachineInstr *MI) const
int GetDotOldOp(const int opc) const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MCInstrDesc.h:233
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APInt.h:33
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isInt< 8 >(int64_t x)
Definition: MathExtras.h:268
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
bool isNewValueJumpCandidate(const MachineInstr *MI) const
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool isTerminator() const
Returns true if this instruction part of the terminator for a basic block.
Definition: MCInstrDesc.h:227
bool isUndef() const
bool predOpcodeHasNot(ArrayRef< MachineOperand > Cond) const
const int Hexagon_MEMH_AUTOINC_MIN
static const PseudoSourceValue * getFixedStack(int FI)
A pseudo source value referencing a fixed stack frame entry, e.g., a spill slot.
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Definition: Value.cpp:317
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
const int Hexagon_MEMB_AUTOINC_MAX
virtual const InstrItineraryData * getInstrItineraryData() const
getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget...
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:571
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:271
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
Definition: MCInstrDesc.h:264
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
const HexagonRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
std::reverse_iterator< instr_iterator > reverse_instr_iterator
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Definition: SmallVector.h:57
#define T
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: ArrayRef.h:31
const int Hexagon_MEMD_AUTOINC_MIN
Itinerary data supplied by a subtarget to be used by a target.
std::vector< MachineBasicBlock * >::iterator pred_iterator
int64_t getImm() const
unsigned getInvertedPredicatedOpcode(const int Opc) const
unsigned getUndefRegState(bool B)
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:134
const int Hexagon_MEMW_AUTOINC_MAX
unsigned getAddrMode(const MachineInstr *MI) const
unsigned getKillRegState(bool B)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:267
const int Hexagon_MEMD_OFFSET_MIN
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:120
bool isDebugValue() const
Definition: MachineInstr.h:748
bool isBundle() const
Definition: MachineInstr.h:775
bundle_iterator< MachineInstr, instr_iterator > iterator
unsigned getTargetFlags() const
const int Hexagon_MEMW_OFFSET_MAX
Constants for Hexagon instructions.
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, const BranchProbability &Probability) const override
const int Hexagon_MEMH_AUTOINC_MAX
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, const BranchProbability &Probability) const override
MVT - Machine Value Type.
unsigned RemoveBranch(MachineBasicBlock &MBB) const override
bool isNewValueStore(const MachineInstr *MI) const
DebugLoc findDebugLoc(instr_iterator MBBI)
findDebugLoc - find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE instructions...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
bool ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Definition: MCInstrDesc.h:532
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:264
void setMBB(MachineBasicBlock *MBB)
bool isSaveCalleeSavedRegsCall(const MachineInstr *MI) const
bool isDeallocRet(const MachineInstr *MI) const
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex) const override
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
bool isPosition() const
Definition: MachineInstr.h:746
bool isNewValueInst(const MachineInstr *MI) const
unsigned createVR(MachineFunction *MF, MVT VT) const
bool isPredicatedTrue(const MachineInstr *MI) const
bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override
expandPostRAPseudo - This function is called for all pseudo instructions that remain after register a...
bool isConstExtended(const MachineInstr *MI) const
void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, SmallVectorImpl< MachineInstr * > &NewMIs) const
bool isConditionalStore(const MachineInstr *MI) const
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:129
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
int GetDotNewOp(const MachineInstr *MI) const
EVT - Extended Value Type.
Definition: ValueTypes.h:31
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool getPredReg(ArrayRef< MachineOperand > Cond, unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const
MachinePointerInfo - This class contains a discriminated union of information about pointers in memor...
const MDOperand & getOperand(unsigned I) const
Definition: Metadata.h:936
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
Definition: SmallPtrSet.h:299
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
const int Hexagon_MEMW_AUTOINC_MIN
HexagonInstrInfo(HexagonSubtarget &ST)
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
static MachineInstr * findLoopInstr(MachineBasicBlock *BB, int EndLoopOp, SmallPtrSet< MachineBasicBlock *, 8 > &Visited)
bool DefinesPredicate(MachineInstr *MI, std::vector< MachineOperand > &Pred) const override
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:861
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
int getCondOpcode(int Opc, bool sense) const
bool isInlineAsm() const
Definition: MachineInstr.h:760
bool mayLoad() const
Return true if this instruction could possibly read memory.
Definition: MCInstrDesc.h:350
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const MachineInstrBuilder & addFrameIndex(int Idx) const
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
bool isPredicable(MachineInstr *MI) const override
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:123
void dump() const
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:238
int GetDotNewPredOp(MachineInstr *MI, const MachineBranchProbabilityInfo *MBPI) const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
TargetSubtargetInfo - Generic base class for all target subtargets.
bool isExtended(const MachineInstr *MI) const
bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override
For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two registe...
Representation of each machine instruction.
Definition: MachineInstr.h:51
void addTargetFlag(unsigned F)
const int Hexagon_MEMB_OFFSET_MAX
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool isValidAutoIncImm(const EVT VT, const int Offset) const
unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot...
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
static MachineOperand CreateImm(int64_t Val)
#define I(x, y, z)
Definition: MD5.cpp:54
void clearKillFlags(unsigned Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
bool isConditionalALU32(const MachineInstr *MI) const
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, DebugLoc DL) const override
const int Hexagon_MEMW_OFFSET_MIN
bool isOperandExtended(const MachineInstr *MI, unsigned short OperandNum) const
short getNonExtOpcode(const MachineInstr *MI) const
unsigned getReg() const
getReg - Returns the register number.
#define HEXAGON_INSTR_SIZE
Definition: Hexagon.h:30
LLVM Value Representation.
Definition: Value.h:69
mop_iterator operands_begin()
Definition: MachineInstr.h:289
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
void immediateExtend(MachineInstr *MI) const
immediateExtend - Changes the instruction in place to one using an immediate extender.
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
bool isNewValueJump(const MachineInstr *MI) const
BasicBlockListType::iterator iterator
#define DEBUG(X)
Definition: Debug.h:92
void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, SmallVectorImpl< MachineInstr * > &NewMIs) const
bool isNewValue(const MachineInstr *MI) const
bool PredOpcodeHasJMP_c(Opcode_t Opcode) const
const int Hexagon_MEMD_AUTOINC_MAX
BranchProbability getEdgeProbability(const MachineBasicBlock *Src, const MachineBasicBlock *Dst) const
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
isLayoutSuccessor - Return true if the specified MBB will be emitted immediately after this block...
bool isValidOffset(unsigned Opcode, int Offset, bool Extend=true) const
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
const int Hexagon_MEMB_AUTOINC_MIN
bool NonExtEquivalentExists(const MachineInstr *MI) const
bool isDotNewInst(const MachineInstr *MI) const
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
const int Hexagon_MEMB_OFFSET_MIN
bool mayBeNewStore(const MachineInstr *MI) const