42 #define DEBUG_TYPE "regalloc"
48 struct CompSpillWeight {
67 std::unique_ptr<Spiller> SpillerInstance;
68 std::priority_queue<LiveInterval*, std::vector<LiveInterval*>,
69 CompSpillWeight> Queue;
79 const char* getPassName()
const override {
80 return "Basic Register Allocator";
86 void releaseMemory()
override;
88 Spiller &spiller()
override {
return *SpillerInstance; }
111 bool spillInterferences(
LiveInterval &VirtReg,
unsigned PhysReg,
155 MachineFunctionPass::getAnalysisUsage(AU);
158 void RABasic::releaseMemory() {
159 SpillerInstance.reset();
166 bool RABasic::spillInterferences(
LiveInterval &VirtReg,
unsigned PhysReg,
185 DEBUG(
dbgs() <<
"spilling " << TRI->getName(PhysReg) <<
186 " interferences with " << VirtReg <<
"\n");
187 assert(!Intfs.
empty() &&
"expected interference");
190 for (
unsigned i = 0, e = Intfs.
size(); i != e; ++i) {
194 if (!VRM->hasPhys(Spill.
reg))
203 spiller().spill(LRE);
227 while (
unsigned PhysReg = Order.next()) {
229 switch (
Matrix->checkInterference(VirtReg, PhysReg)) {
230 case LiveRegMatrix::IK_Free:
234 case LiveRegMatrix::IK_VirtReg:
247 PhysRegE = PhysRegSpillCands.
end(); PhysRegI != PhysRegE; ++PhysRegI) {
248 if (!spillInterferences(VirtReg, *PhysRegI, SplitVRegs))
251 assert(!
Matrix->checkInterference(VirtReg, *PhysRegI) &&
252 "Interference after spill.");
258 DEBUG(
dbgs() <<
"spilling: " << VirtReg <<
'\n');
262 spiller().spill(LRE);
270 DEBUG(
dbgs() <<
"********** BASIC REGISTER ALLOCATION **********\n"
271 <<
"********** Function: "
276 getAnalysis<LiveIntervals>(),
277 getAnalysis<LiveRegMatrix>());
280 getAnalysis<MachineLoopInfo>(),
281 getAnalysis<MachineBlockFrequencyInfo>());
288 DEBUG(
dbgs() <<
"Post alloc VirtRegMap:\n" << *VRM <<
"\n");
296 return new RABasic();
void push_back(const T &Elt)
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
char & MachineDominatorsID
MachineDominators - This pass is a machine dominators analysis pass.
LiveInterval - This class represents the liveness of a register, or stack slot.
void initializeLiveDebugVariablesPass(PassRegistry &)
bool isSpillable() const
isSpillable - Can this interval be spilled?
MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...
void initializeMachineLoopInfoPass(PassRegistry &)
void calculateSpillWeightsAndHints(LiveIntervals &LIS, MachineFunction &MF, const MachineLoopInfo &MLI, const MachineBlockFrequencyInfo &MBFI, VirtRegAuxInfo::NormalizingFn norm=normalizeSpillWeight)
Compute spill weights and allocation hints for all virtual register live intervals.
void initializeRegisterCoalescerPass(PassRegistry &)
AnalysisUsage & addRequired()
Query interferences between a single live virtual register and a live interval union.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
static RegisterRegAlloc basicRegAlloc("basic","basic register allocator", createBasicRegisterAllocator)
RegAllocBase provides the register allocation driver and interface that can be extended to add intere...
const SmallVectorImpl< LiveInterval * > & interferingVRegs() const
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
AnalysisUsage & addPreservedID(const void *ID)
RegisterRegAlloc class - Track the registration of register allocators.
void initializeMachineDominatorTreePass(PassRegistry &)
initializer< Ty > init(const Ty &Val)
void initializeSlotIndexesPass(PassRegistry &)
void initializeLiveStacksPass(PassRegistry &)
Represent the analysis usage information of a pass.
void initializeLiveIntervalsPass(PassRegistry &)
FunctionPass class - This class is used to implement most global optimizations.
AnalysisUsage & addRequiredID(const void *ID)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
FunctionPass * createBasicRegisterAllocator()
BasicRegisterAllocation Pass - This pass implements a degenerate global register allocator using the ...
void setPreservesCFG()
This function should be called by the pass, iff they do not:
bool seenUnspillableVReg() const
void initializeMachineSchedulerPass(PassRegistry &)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void initializeVirtRegMapPass(PassRegistry &)
Spiller * createInlineSpiller(MachineFunctionPass &pass, MachineFunction &mf, VirtRegMap &vrm)
Create and return a spiller that will insert spill code directly instead of deferring though VirtRegM...
void initializeLiveRegMatrixPass(PassRegistry &)
unsigned collectInterferingVRegs(unsigned MaxInterferingRegs=UINT_MAX)
StringRef getName() const
getName - Return the name of the corresponding LLVM function.