39 #define DEBUG_TYPE "ppc-codegen"
47 cl::desc(
"use aggressive ppc isel for bit permutations"),
50 "ppc-bit-perm-rewriter-stress-rotates",
51 cl::desc(
"stress rotate selection in aggressive ppc isel for "
82 if (!PPCSubTarget->isSVR4ABI())
88 void PreprocessISelDAG()
override;
89 void PostprocessISelDAG()
override;
94 return CurDAG->getTargetConstant(Imm, dl,
MVT::i32);
100 return CurDAG->getTargetConstant(Imm, dl,
MVT::i64);
104 inline SDValue getSmallIPtrImm(
unsigned Imm,
SDLoc dl) {
105 return CurDAG->getTargetConstant(
106 Imm, dl, PPCLowering->getPointerTy(CurDAG->getDataLayout()));
111 static bool isRotateAndMask(
SDNode *
N,
unsigned Mask,
bool isShiftMask,
112 unsigned &SH,
unsigned &MB,
unsigned &ME);
116 SDNode *getGlobalBaseReg();
135 return PPCLowering->SelectAddressRegImm(N, Disp, Base, *CurDAG,
false);
155 return PPCLowering->SelectAddressRegReg(N, Base, Index, *CurDAG);
161 return PPCLowering->SelectAddressRegRegOnly(N, Base, Index, *CurDAG);
168 return PPCLowering->SelectAddressRegImm(N, Disp, Base, *CurDAG,
true);
182 bool SelectInlineAsmMemoryOperand(
const SDValue &Op,
183 unsigned ConstraintID,
184 std::vector<SDValue> &OutOps)
override {
186 switch(ConstraintID) {
188 errs() <<
"ConstraintID: " << ConstraintID <<
"\n";
208 OutOps.push_back(NewOp);
216 const char *getPassName()
const override {
217 return "PowerPC DAG->DAG Pattern Instruction Selection";
221 #include "PPCGenDAGISel.inc"
226 void PeepholePPC64();
227 void PeepholePPC64ZExt();
228 void PeepholeCROps();
233 bool AllUsersSelectZero(
SDNode *N);
234 void SwapAllSelectUsers(
SDNode *N);
249 bool HasVectorVReg =
false;
250 for (
unsigned i = 0, e = RegInfo->getNumVirtRegs(); i != e; ++i) {
252 if (RegInfo->getRegClass(Reg) == &PPC::VRRCRegClass) {
253 HasVectorVReg =
true;
257 if (!HasVectorVReg)
return;
271 unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
272 unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
282 BuildMI(EntryBB, IP, dl, TII.
get(PPC::MFVRSAVE), InVRSAVE);
283 BuildMI(EntryBB, IP, dl, TII.
get(PPC::UPDATE_VRSAVE),
284 UpdatedVRSAVE).addReg(InVRSAVE);
285 BuildMI(EntryBB, IP, dl, TII.
get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
289 if (!BB->empty() && BB->back().isReturn()) {
290 IP = BB->end(); --IP;
295 while (I2 != BB->begin() && (--I2)->isTerminator())
299 BuildMI(*BB, IP, dl, TII.
get(PPC::MTVRSAVE)).addReg(InVRSAVE);
308 SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
317 if (PPCLowering->getPointerTy(CurDAG->getDataLayout()) ==
MVT::i32) {
318 if (PPCSubTarget->isTargetELF()) {
321 BuildMI(FirstMBB, MBBI, dl, TII.
get(PPC::MoveGOTtoLR));
325 BuildMI(FirstMBB, MBBI, dl, TII.
get(PPC::MovePCtoLR));
327 unsigned TempReg = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
335 RegInfo->createVirtualRegister(&PPC::GPRC_NOR0RegClass);
336 BuildMI(FirstMBB, MBBI, dl, TII.
get(PPC::MovePCtoLR));
340 GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::G8RC_NOX0RegClass);
341 BuildMI(FirstMBB, MBBI, dl, TII.
get(PPC::MovePCtoLR8));
346 PPCLowering->getPointerTy(CurDAG->getDataLayout()))
358 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
360 return Imm == (int32_t)cast<ConstantSDNode>(
N)->getZExtValue();
362 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
374 Imm = cast<ConstantSDNode>(
N)->getZExtValue();
384 Imm = cast<ConstantSDNode>(
N)->getZExtValue();
407 int FI = cast<FrameIndexSDNode>(
N)->getIndex();
411 return CurDAG->SelectNodeTo(SN, Opc, N->
getValueType(0), TFI,
412 getSmallIPtrImm(Offset, dl));
413 return CurDAG->getMachineNode(Opc, dl, N->
getValueType(0), TFI,
414 getSmallIPtrImm(Offset, dl));
417 bool PPCDAGToDAGISel::isRotateAndMask(
SDNode *N,
unsigned Mask,
418 bool isShiftMask,
unsigned &SH,
419 unsigned &MB,
unsigned &ME) {
426 unsigned Indeterminant = ~0;
434 if (isShiftMask) Mask = Mask << Shift;
436 Indeterminant = ~(0xFFFFFFFFu << Shift);
439 if (isShiftMask) Mask = Mask >> Shift;
441 Indeterminant = ~(0xFFFFFFFFu >> Shift);
451 if (Mask && !(Mask & Indeterminant)) {
461 SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(
SDNode *N) {
466 APInt LKZ, LKO, RKZ, RKO;
467 CurDAG->computeKnownBits(Op0, LKZ, LKO);
468 CurDAG->computeKnownBits(Op1, RKZ, RKO);
473 if ((TargetMask | InsertMask) == 0xFFFFFFFF) {
476 unsigned Value, SH = 0;
477 TargetMask = ~TargetMask;
478 InsertMask = ~InsertMask;
508 SH = (Op1Opc ==
ISD::SHL) ? Value : 32 - Value;
515 CurDAG->computeKnownBits(Op1.
getOperand(1), MKZ, MKO);
524 SH = (SHOpc ==
ISD::SHL) ? Value : 32 - Value;
529 SDValue Ops[] = { Op0, Op1, getI32Imm(SH, dl), getI32Imm(MB, dl),
531 return CurDAG->getMachineNode(PPC::RLWIMI, dl,
MVT::i32, Ops);
541 unsigned Remainder = 0;
547 Shift = countTrailingZeros<uint64_t>(Imm);
548 int64_t ImmSh =
static_cast<uint64_t
>(Imm) >> Shift;
566 unsigned Lo = Imm & 0xFFFF;
567 unsigned Hi = (Imm >> 16) & 0xFFFF;
582 if (!Shift)
return Result;
589 if ((Hi = (Remainder >> 16) & 0xFFFF))
591 if ((Lo = Remainder & 0xFFFF))
597 static uint64_t
Rot64(uint64_t Imm,
unsigned R) {
598 return (Imm << R) | (Imm >> (64 - R));
606 for (
unsigned r = 1; r < 63; ++r) {
607 uint64_t RImm =
Rot64(Imm, r);
616 uint64_t OnesMask = -(int64_t) (UINT64_C(1) << (LS+1));
617 uint64_t RImmWithOnes = RImm | OnesMask;
630 unsigned Remainder = 0;
636 Shift = countTrailingZeros<uint64_t>(Imm);
637 int64_t ImmSh =
static_cast<uint64_t
>(Imm) >> Shift;
655 unsigned Lo = Imm & 0xFFFF;
656 unsigned Hi = (Imm >> 16) & 0xFFFF;
658 auto getI32Imm = [CurDAG, dl](
unsigned Imm) {
668 unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8;
672 SDValue(Result, 0), getI32Imm(Lo));
679 if (!Shift)
return Result;
686 getI32Imm(63 - Shift));
690 if ((Hi = (Remainder >> 16) & 0xFFFF)) {
692 SDValue(Result, 0), getI32Imm(Hi));
694 if ((Lo = Remainder & 0xFFFF)) {
696 SDValue(Result, 0), getI32Imm(Lo));
712 for (
unsigned r = 1; r < 63; ++r) {
713 uint64_t RImm =
Rot64(Imm, r);
715 if (RCount < Count) {
734 uint64_t OnesMask = -(int64_t) (UINT64_C(1) << (LS+1));
735 uint64_t RImmWithOnes = RImm | OnesMask;
738 if (RCount < Count) {
741 MatImm = RImmWithOnes;
749 auto getI32Imm = [CurDAG, dl](
unsigned Imm) {
755 getI32Imm(64 - RMin), getI32Imm(MaskEnd));
763 int64_t Imm = cast<ConstantSDNode>(
N)->getZExtValue();
768 class BitPermutationSelector {
782 : V(V), Idx(I), K(K) {}
783 ValueBit(
Kind K = Variable)
784 : V(
SDValue(nullptr, 0)), Idx(UINT32_MAX), K(K) {}
787 return K == ConstZero;
790 bool hasValue()
const {
791 return K == Variable;
795 assert(hasValue() &&
"Cannot get the value of a constant bit");
799 unsigned getValueBitIndex()
const {
800 assert(hasValue() &&
"Cannot get the value bit index of a constant bit");
809 unsigned StartIdx, EndIdx;
819 bool Repl32Coalesced;
821 BitGroup(
SDValue V,
unsigned R,
unsigned S,
unsigned E)
822 : V(V), RLAmt(R), StartIdx(S), EndIdx(E), Repl32(
false), Repl32CR(
false),
823 Repl32Coalesced(
false) {
825 " [" << S <<
", " << E <<
"]\n");
831 struct ValueRotInfo {
835 unsigned FirstGroupStartIdx;
839 : RLAmt(UINT32_MAX), NumGroups(0), FirstGroupStartIdx(UINT32_MAX),
848 if (Repl32 < Other.Repl32)
850 else if (Repl32 > Other.Repl32)
852 else if (NumGroups > Other.NumGroups)
854 else if (NumGroups < Other.NumGroups)
856 else if (FirstGroupStartIdx < Other.FirstGroupStartIdx)
875 for (
unsigned i = 0; i < Bits.
size(); ++i)
876 Bits[i] = LHSBits[i < RotAmt ? i + (Bits.
size() - RotAmt) : i - RotAmt];
888 for (
unsigned i = ShiftAmt; i < Bits.
size(); ++i)
889 Bits[i] = LHSBits[i - ShiftAmt];
891 for (
unsigned i = 0; i < ShiftAmt; ++i)
892 Bits[i] = ValueBit(ValueBit::ConstZero);
904 for (
unsigned i = 0; i < Bits.
size() - ShiftAmt; ++i)
905 Bits[i] = LHSBits[i + ShiftAmt];
907 for (
unsigned i = Bits.
size() - ShiftAmt; i < Bits.
size(); ++i)
908 Bits[i] = ValueBit(ValueBit::ConstZero);
918 bool LHSTrivial = getValueBits(V.
getOperand(0), LHSBits);
920 for (
unsigned i = 0; i < Bits.
size(); ++i)
921 if (((Mask >> i) & 1) == 1)
922 Bits[i] = LHSBits[i];
924 Bits[i] = ValueBit(ValueBit::ConstZero);
938 bool AllDisjoint =
true;
939 for (
unsigned i = 0; i < Bits.
size(); ++i)
941 Bits[i] = RHSBits[i];
942 else if (RHSBits[i].
isZero())
943 Bits[i] = LHSBits[i];
956 for (
unsigned i = 0; i < Bits.
size(); ++i)
957 Bits[i] = ValueBit(V, i);
964 void computeRotationAmounts() {
967 for (
unsigned i = 0; i < Bits.
size(); ++i)
968 if (Bits[i].hasValue()) {
969 unsigned VBI = Bits[i].getValueBitIndex();
973 RLAmt[i] = Bits.
size() - (VBI - i);
974 }
else if (Bits[i].
isZero()) {
976 RLAmt[i] = UINT32_MAX;
985 void collectBitGroups(
bool LateMask) {
988 unsigned LastRLAmt = RLAmt[0];
989 SDValue LastValue = Bits[0].hasValue() ? Bits[0].getValue() :
SDValue();
990 unsigned LastGroupStartIdx = 0;
991 for (
unsigned i = 1; i < Bits.
size(); ++i) {
992 unsigned ThisRLAmt = RLAmt[i];
993 SDValue ThisValue = Bits[i].hasValue() ? Bits[i].getValue() :
SDValue();
994 if (LateMask && !ThisValue) {
995 ThisValue = LastValue;
996 ThisRLAmt = LastRLAmt;
999 if (BitGroups.empty())
1000 LastGroupStartIdx = 0;
1005 if (ThisRLAmt == LastRLAmt && ThisValue == LastValue)
1009 BitGroups.push_back(BitGroup(LastValue, LastRLAmt, LastGroupStartIdx,
1011 LastRLAmt = ThisRLAmt;
1012 LastValue = ThisValue;
1013 LastGroupStartIdx = i;
1016 BitGroups.push_back(BitGroup(LastValue, LastRLAmt, LastGroupStartIdx,
1019 if (BitGroups.empty())
1023 if (BitGroups.size() > 1) {
1027 if (BitGroups[0].StartIdx == 0 &&
1028 BitGroups[BitGroups.size()-1].EndIdx == Bits.
size()-1 &&
1029 BitGroups[0].V == BitGroups[BitGroups.size()-1].V &&
1030 BitGroups[0].RLAmt == BitGroups[BitGroups.size()-1].RLAmt) {
1031 DEBUG(
dbgs() <<
"\tcombining final bit group with inital one\n");
1032 BitGroups[BitGroups.size()-1].EndIdx = BitGroups[0].EndIdx;
1033 BitGroups.erase(BitGroups.begin());
1041 void collectValueRotInfo() {
1044 for (
auto &BG : BitGroups) {
1045 unsigned RLAmtKey = BG.RLAmt + (BG.Repl32 ? 64 : 0);
1046 ValueRotInfo &VRI = ValueRots[std::make_pair(BG.V, RLAmtKey)];
1048 VRI.RLAmt = BG.RLAmt;
1049 VRI.Repl32 = BG.Repl32;
1051 VRI.FirstGroupStartIdx =
std::min(VRI.FirstGroupStartIdx, BG.StartIdx);
1056 ValueRotsVec.clear();
1057 for (
auto &
I : ValueRots) {
1058 ValueRotsVec.push_back(
I.second);
1060 std::sort(ValueRotsVec.begin(), ValueRotsVec.end());
1071 void assignRepl32BitGroups() {
1082 auto IsAllLow32 = [
this](BitGroup & BG) {
1083 if (BG.StartIdx <= BG.EndIdx) {
1084 for (
unsigned i = BG.StartIdx; i <= BG.EndIdx; ++i) {
1085 if (!Bits[i].hasValue())
1087 if (Bits[i].getValueBitIndex() >= 32)
1091 for (
unsigned i = BG.StartIdx; i < Bits.
size(); ++i) {
1092 if (!Bits[i].hasValue())
1094 if (Bits[i].getValueBitIndex() >= 32)
1097 for (
unsigned i = 0; i <= BG.EndIdx; ++i) {
1098 if (!Bits[i].hasValue())
1100 if (Bits[i].getValueBitIndex() >= 32)
1108 for (
auto &BG : BitGroups) {
1109 if (BG.StartIdx < 32 && BG.EndIdx < 32) {
1110 if (IsAllLow32(BG)) {
1111 if (BG.RLAmt >= 32) {
1118 DEBUG(
dbgs() <<
"\t32-bit replicated bit group for " <<
1119 BG.V.getNode() <<
" RLAmt = " << BG.RLAmt <<
1120 " [" << BG.StartIdx <<
", " << BG.EndIdx <<
"]\n");
1126 for (
auto I = BitGroups.begin();
I != BitGroups.end();) {
1129 auto IP = (
I == BitGroups.begin()) ?
1130 std::prev(BitGroups.end()) : std::prev(
I);
1131 if (
I->Repl32 && IP->Repl32 &&
I->V == IP->V &&
I->RLAmt == IP->RLAmt &&
1132 I->StartIdx == (IP->EndIdx + 1) % 64 &&
I !=
IP) {
1134 DEBUG(
dbgs() <<
"\tcombining 32-bit replicated bit group for " <<
1135 I->V.getNode() <<
" RLAmt = " <<
I->RLAmt <<
1136 " [" <<
I->StartIdx <<
", " <<
I->EndIdx <<
1137 "] with group with range [" <<
1138 IP->StartIdx <<
", " << IP->EndIdx <<
"]\n");
1140 IP->EndIdx =
I->EndIdx;
1141 IP->Repl32CR = IP->Repl32CR ||
I->Repl32CR;
1142 IP->Repl32Coalesced =
true;
1143 I = BitGroups.erase(
I);
1152 if (
I->StartIdx == 32 &&
I->EndIdx == 63) {
1153 assert(std::next(
I) == BitGroups.end() &&
1154 "bit group ends at index 63 but there is another?");
1155 auto IN = BitGroups.begin();
1157 if (IP->Repl32 && IN->Repl32 &&
I->V == IP->V &&
I->V == IN->V &&
1158 (
I->RLAmt % 32) == IP->RLAmt && (
I->RLAmt % 32) == IN->RLAmt &&
1159 IP->EndIdx == 31 && IN->StartIdx == 0 &&
I != IP &&
1162 DEBUG(
dbgs() <<
"\tcombining bit group for " <<
1163 I->V.getNode() <<
" RLAmt = " <<
I->RLAmt <<
1164 " [" <<
I->StartIdx <<
", " <<
I->EndIdx <<
1165 "] with 32-bit replicated groups with ranges [" <<
1166 IP->StartIdx <<
", " << IP->EndIdx <<
"] and [" <<
1167 IN->StartIdx <<
", " << IN->EndIdx <<
"]\n");
1175 IP->Repl32CR = IP->Repl32CR ||
I->RLAmt >= 32;
1176 IP->Repl32Coalesced =
true;
1177 I = BitGroups.erase(
I);
1182 IP->EndIdx = IN->EndIdx;
1183 IP->Repl32CR = IP->Repl32CR || IN->Repl32CR ||
I->RLAmt >= 32;
1184 IP->Repl32Coalesced =
true;
1185 I = BitGroups.erase(
I);
1186 BitGroups.erase(BitGroups.begin());
1201 return CurDAG->getTargetConstant(Imm, dl,
MVT::i32);
1204 uint64_t getZerosMask() {
1206 for (
unsigned i = 0; i < Bits.
size(); ++i) {
1207 if (Bits[i].hasValue())
1209 Mask |= (UINT64_C(1) << i);
1218 void SelectAndParts32(
SDLoc dl,
SDValue &Res,
unsigned *InstCnt) {
1222 for (ValueRotInfo &VRI : ValueRotsVec) {
1224 for (
unsigned i = 0; i < Bits.
size(); ++i) {
1225 if (!Bits[i].hasValue() || Bits[i].getValue() != VRI.V)
1227 if (RLAmt[i] != VRI.RLAmt)
1233 unsigned ANDIMask = (Mask & UINT16_MAX), ANDISMask = Mask >> 16;
1234 assert((ANDIMask != 0 || ANDISMask != 0) &&
1235 "No set bits in mask for value bit groups");
1236 bool NeedsRotate = VRI.RLAmt != 0;
1252 unsigned NumAndInsts = (
unsigned) NeedsRotate +
1253 (
unsigned) (ANDIMask != 0) +
1254 (
unsigned) (ANDISMask != 0) +
1255 (
unsigned) (ANDIMask != 0 && ANDISMask != 0) +
1256 (
unsigned) (
bool) Res;
1258 DEBUG(
dbgs() <<
"\t\trotation groups for " << VRI.V.getNode() <<
1259 " RL: " << VRI.RLAmt <<
":" <<
1260 "\n\t\t\tisel using masking: " << NumAndInsts <<
1261 " using rotates: " << VRI.NumGroups <<
"\n");
1263 if (NumAndInsts >= VRI.NumGroups)
1266 DEBUG(
dbgs() <<
"\t\t\t\tusing masking\n");
1268 if (InstCnt) *InstCnt += NumAndInsts;
1273 { VRI.V, getI32Imm(VRI.RLAmt, dl), getI32Imm(0, dl),
1274 getI32Imm(31, dl) };
1284 VRot, getI32Imm(ANDIMask, dl)), 0);
1287 VRot, getI32Imm(ANDISMask, dl)), 0);
1291 TotalVal = ANDISVal;
1296 ANDIVal, ANDISVal), 0);
1306 eraseMatchingBitGroups([VRI](
const BitGroup &BG) {
1307 return BG.V == VRI.V && BG.RLAmt == VRI.RLAmt;
1313 SDNode *Select32(
SDNode *N,
bool LateMask,
unsigned *InstCnt) {
1317 if (InstCnt) *InstCnt = 0;
1320 SelectAndParts32(dl, Res, InstCnt);
1325 if ((!HasZeros || LateMask) && !Res) {
1326 ValueRotInfo &VRI = ValueRotsVec[0];
1328 if (InstCnt) *InstCnt += 1;
1330 { VRI.V, getI32Imm(VRI.RLAmt, dl), getI32Imm(0, dl),
1331 getI32Imm(31, dl) };
1339 eraseMatchingBitGroups([VRI](
const BitGroup &BG) {
1340 return BG.V == VRI.V && BG.RLAmt == VRI.RLAmt;
1344 if (InstCnt) *InstCnt += BitGroups.size();
1347 for (
auto &BG : BitGroups) {
1350 { BG.V, getI32Imm(BG.RLAmt, dl),
1351 getI32Imm(Bits.
size() - BG.EndIdx - 1, dl),
1352 getI32Imm(Bits.
size() - BG.StartIdx - 1, dl) };
1353 Res =
SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl,
MVT::i32, Ops), 0);
1356 { Res, BG.V, getI32Imm(BG.RLAmt, dl),
1357 getI32Imm(Bits.
size() - BG.EndIdx - 1, dl),
1358 getI32Imm(Bits.
size() - BG.StartIdx - 1, dl) };
1359 Res =
SDValue(CurDAG->getMachineNode(PPC::RLWIMI, dl,
MVT::i32, Ops), 0);
1364 unsigned Mask = (
unsigned) getZerosMask();
1366 unsigned ANDIMask = (Mask & UINT16_MAX), ANDISMask = Mask >> 16;
1367 assert((ANDIMask != 0 || ANDISMask != 0) &&
1368 "No set bits in zeros mask?");
1370 if (InstCnt) *InstCnt += (
unsigned) (ANDIMask != 0) +
1372 (
unsigned) (ANDIMask != 0 && ANDISMask != 0);
1377 Res, getI32Imm(ANDIMask, dl)), 0);
1380 Res, getI32Imm(ANDISMask, dl)), 0);
1388 ANDIVal, ANDISVal), 0);
1394 unsigned SelectRotMask64Count(
unsigned RLAmt,
bool Repl32,
1395 unsigned MaskStart,
unsigned MaskEnd,
1399 unsigned InstMaskStart = 64 - MaskEnd - 1,
1400 InstMaskEnd = 64 - MaskStart - 1;
1405 if ((!IsIns && (InstMaskEnd == 63 || InstMaskStart == 0)) ||
1406 InstMaskEnd == 63 - RLAmt)
1415 unsigned MaskStart,
unsigned MaskEnd,
1416 unsigned *InstCnt =
nullptr) {
1419 unsigned InstMaskStart = 64 - MaskEnd - 1,
1420 InstMaskEnd = 64 - MaskStart - 1;
1422 if (InstCnt) *InstCnt += 1;
1428 assert(InstMaskStart >= 32 &&
"Mask cannot start out of range");
1429 assert(InstMaskEnd >= 32 &&
"Mask cannot end out of range");
1431 { V, getI32Imm(RLAmt, dl), getI32Imm(InstMaskStart - 32, dl),
1432 getI32Imm(InstMaskEnd - 32, dl) };
1437 if (InstMaskEnd == 63) {
1439 { V, getI32Imm(RLAmt, dl), getI32Imm(InstMaskStart, dl) };
1440 return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl,
MVT::i64, Ops), 0);
1443 if (InstMaskStart == 0) {
1445 { V, getI32Imm(RLAmt, dl), getI32Imm(InstMaskEnd, dl) };
1446 return SDValue(CurDAG->getMachineNode(PPC::RLDICR, dl,
MVT::i64, Ops), 0);
1449 if (InstMaskEnd == 63 - RLAmt) {
1451 { V, getI32Imm(RLAmt, dl), getI32Imm(InstMaskStart, dl) };
1452 return SDValue(CurDAG->getMachineNode(PPC::RLDIC, dl,
MVT::i64, Ops), 0);
1461 if (InstCnt) *InstCnt += 1;
1464 unsigned RLAmt2 = MaskStart;
1467 unsigned RLAmt1 = (64 + RLAmt - RLAmt2) % 64;
1469 V = SelectRotMask64(V, dl, RLAmt1,
false, 0, 63);
1470 return SelectRotMask64(V, dl, RLAmt2,
false, MaskStart, MaskEnd);
1476 bool Repl32,
unsigned MaskStart,
1477 unsigned MaskEnd,
unsigned *InstCnt =
nullptr) {
1480 unsigned InstMaskStart = 64 - MaskEnd - 1,
1481 InstMaskEnd = 64 - MaskStart - 1;
1483 if (InstCnt) *InstCnt += 1;
1489 assert(InstMaskStart >= 32 &&
"Mask cannot start out of range");
1490 assert(InstMaskEnd >= 32 &&
"Mask cannot end out of range");
1492 { Base, V, getI32Imm(RLAmt, dl), getI32Imm(InstMaskStart - 32, dl),
1493 getI32Imm(InstMaskEnd - 32, dl) };
1498 if (InstMaskEnd == 63 - RLAmt) {
1500 { Base, V, getI32Imm(RLAmt, dl), getI32Imm(InstMaskStart, dl) };
1501 return SDValue(CurDAG->getMachineNode(PPC::RLDIMI, dl,
MVT::i64, Ops), 0);
1510 if (InstCnt) *InstCnt += 1;
1513 unsigned RLAmt2 = MaskStart;
1516 unsigned RLAmt1 = (64 + RLAmt - RLAmt2) % 64;
1518 V = SelectRotMask64(V, dl, RLAmt1,
false, 0, 63);
1519 return SelectRotMaskIns64(Base, V, dl, RLAmt2,
false, MaskStart, MaskEnd);
1522 void SelectAndParts64(
SDLoc dl,
SDValue &Res,
unsigned *InstCnt) {
1535 for (ValueRotInfo &VRI : ValueRotsVec) {
1543 auto MatchingBG = [VRI](
const BitGroup &BG) {
1547 unsigned EffRLAmt = BG.RLAmt;
1548 if (!VRI.Repl32 && BG.Repl32) {
1549 if (BG.StartIdx < 32 && BG.EndIdx < 32 && BG.StartIdx <= BG.EndIdx &&
1550 !BG.Repl32Coalesced) {
1556 }
else if (VRI.Repl32 != BG.Repl32) {
1560 if (VRI.RLAmt != EffRLAmt)
1566 for (
auto &BG : BitGroups) {
1567 if (!MatchingBG(BG))
1570 if (BG.StartIdx <= BG.EndIdx) {
1571 for (
unsigned i = BG.StartIdx; i <= BG.EndIdx; ++i)
1572 Mask |= (UINT64_C(1) << i);
1574 for (
unsigned i = BG.StartIdx; i < Bits.
size(); ++i)
1575 Mask |= (UINT64_C(1) << i);
1576 for (
unsigned i = 0; i <= BG.EndIdx; ++i)
1577 Mask |= (UINT64_C(1) << i);
1586 unsigned ANDIMask = (Mask & UINT16_MAX),
1587 ANDISMask = (Mask >> 16) & UINT16_MAX;
1589 bool NeedsRotate = VRI.RLAmt || (VRI.Repl32 && !
isUInt<32>(Mask));
1591 unsigned NumAndInsts = (
unsigned) NeedsRotate +
1592 (
unsigned) (
bool) Res;
1595 (
unsigned) (ANDIMask != 0 && ANDISMask != 0);
1599 unsigned NumRLInsts = 0;
1600 bool FirstBG =
true;
1601 for (
auto &BG : BitGroups) {
1602 if (!MatchingBG(BG))
1605 SelectRotMask64Count(BG.RLAmt, BG.Repl32, BG.StartIdx, BG.EndIdx,
1610 DEBUG(
dbgs() <<
"\t\trotation groups for " << VRI.V.getNode() <<
1611 " RL: " << VRI.RLAmt << (VRI.Repl32 ?
" (32):" :
":") <<
1612 "\n\t\t\tisel using masking: " << NumAndInsts <<
1613 " using rotates: " << NumRLInsts <<
"\n");
1619 if (NumAndInsts > NumRLInsts)
1621 if (Use32BitInsts && NumAndInsts == NumRLInsts)
1624 DEBUG(
dbgs() <<
"\t\t\t\tusing masking\n");
1626 if (InstCnt) *InstCnt += NumAndInsts;
1633 if (VRI.RLAmt || (VRI.Repl32 && !
isUInt<32>(Mask)))
1634 VRot = SelectRotMask64(VRI.V, dl, VRI.RLAmt, VRI.Repl32,
1635 VRI.Repl32 ? 31 : 0, VRI.Repl32 ? 30 : 63);
1640 if (Use32BitInsts) {
1641 assert((ANDIMask != 0 || ANDISMask != 0) &&
1642 "No set bits in mask when using 32-bit ands for 64-bit value");
1647 VRot, getI32Imm(ANDIMask, dl)), 0);
1650 VRot, getI32Imm(ANDISMask, dl)), 0);
1653 TotalVal = ANDISVal;
1658 ANDIVal, ANDISVal), 0);
1663 VRot, TotalVal), 0);
1674 eraseMatchingBitGroups(MatchingBG);
1679 SDNode *Select64(
SDNode *N,
bool LateMask,
unsigned *InstCnt) {
1683 if (InstCnt) *InstCnt = 0;
1686 SelectAndParts64(dl, Res, InstCnt);
1691 if ((!HasZeros || LateMask) && !Res) {
1695 unsigned MaxGroupsIdx = 0;
1696 if (!ValueRotsVec[0].Repl32) {
1697 for (
unsigned i = 0, ie = ValueRotsVec.size(); i < ie; ++i)
1698 if (ValueRotsVec[i].Repl32) {
1699 if (ValueRotsVec[i].NumGroups > ValueRotsVec[0].NumGroups)
1705 ValueRotInfo &VRI = ValueRotsVec[MaxGroupsIdx];
1706 bool NeedsRotate =
false;
1709 }
else if (VRI.Repl32) {
1710 for (
auto &BG : BitGroups) {
1711 if (BG.V != VRI.V || BG.RLAmt != VRI.RLAmt ||
1712 BG.Repl32 != VRI.Repl32)
1717 if (BG.StartIdx < 32 && BG.EndIdx < 32 && BG.StartIdx < BG.EndIdx)
1726 Res = SelectRotMask64(VRI.V, dl, VRI.RLAmt, VRI.Repl32,
1727 VRI.Repl32 ? 31 : 0, VRI.Repl32 ? 30 : 63,
1734 eraseMatchingBitGroups([VRI](
const BitGroup &BG) {
1735 return BG.V == VRI.V && BG.RLAmt == VRI.RLAmt &&
1736 BG.Repl32 == VRI.Repl32;
1743 for (
auto I = BitGroups.begin(),
IE = BitGroups.end();
I !=
IE; ++
I) {
1744 if (SelectRotMask64Count(
I->RLAmt,
I->Repl32,
I->StartIdx,
I->EndIdx,
1746 SelectRotMask64Count(
I->RLAmt,
I->Repl32,
I->StartIdx,
I->EndIdx,
1748 if (
I != BitGroups.begin()) {
1751 BitGroups.insert(BitGroups.begin(), BG);
1759 for (
auto &BG : BitGroups) {
1761 Res = SelectRotMask64(BG.V, dl, BG.RLAmt, BG.Repl32, BG.StartIdx,
1762 BG.EndIdx, InstCnt);
1764 Res = SelectRotMaskIns64(Res, BG.V, dl, BG.RLAmt, BG.Repl32,
1765 BG.StartIdx, BG.EndIdx, InstCnt);
1769 uint64_t Mask = getZerosMask();
1776 unsigned ANDIMask = (Mask & UINT16_MAX),
1777 ANDISMask = (Mask >> 16) & UINT16_MAX;
1779 if (Use32BitInsts) {
1780 assert((ANDIMask != 0 || ANDISMask != 0) &&
1781 "No set bits in mask when using 32-bit ands for 64-bit value");
1783 if (InstCnt) *InstCnt += (
unsigned) (ANDIMask != 0) +
1785 (
unsigned) (ANDIMask != 0 && ANDISMask != 0);
1790 Res, getI32Imm(ANDIMask, dl)), 0);
1793 Res, getI32Imm(ANDISMask, dl)), 0);
1801 ANDIVal, ANDISVal), 0);
1817 collectBitGroups(LateMask);
1818 if (BitGroups.empty())
1822 if (Bits.
size() == 64)
1823 assignRepl32BitGroups();
1826 collectValueRotInfo();
1828 if (Bits.
size() == 32) {
1829 return Select32(N, LateMask, InstCnt);
1831 assert(Bits.
size() == 64 &&
"Not 64 bits here?");
1832 return Select64(N, LateMask, InstCnt);
1838 void eraseMatchingBitGroups(
function_ref<
bool(
const BitGroup &)>
F) {
1839 BitGroups.erase(std::remove_if(BitGroups.begin(), BitGroups.end(),
F),
1864 if (!getValueBits(
SDValue(N, 0), Bits))
1867 DEBUG(
dbgs() <<
"Considering bit-permutation-based instruction"
1868 " selection for: ");
1872 computeRotationAmounts();
1885 unsigned InstCnt, InstCntLateMask;
1888 DEBUG(
dbgs() <<
"\t\tisel would use " << InstCnt <<
" instructions\n");
1892 DEBUG(
dbgs() <<
"\t\tisel would use " << InstCntLateMask <<
1895 if (InstCnt <= InstCntLateMask) {
1896 DEBUG(
dbgs() <<
"\tUsing early-masking for isel\n");
1900 DEBUG(
dbgs() <<
"\tUsing late-masking for isel\n");
1906 SDNode *PPCDAGToDAGISel::SelectBitPermutation(
SDNode *N) {
1921 BitPermutationSelector BPS(CurDAG);
1922 return BPS.Select(N);
1943 getI32Imm(Imm & 0xFFFF, dl)),
1948 getI32Imm(Imm & 0xFFFF, dl)),
1961 getI32Imm(Imm >> 16, dl)), 0);
1963 getI32Imm(Imm & 0xFFFF, dl)), 0);
1969 getI32Imm(Imm & 0xFFFF, dl)), 0);
1975 getI32Imm((
int)SImm & 0xFFFF,
1987 getI32Imm(Imm & 0xFFFF, dl)),
1992 getI32Imm(Imm & 0xFFFF, dl)),
2006 getI64Imm(Imm >> 16, dl)), 0);
2008 getI64Imm(Imm & 0xFFFF, dl)),
2016 getI64Imm(Imm & 0xFFFF, dl)), 0);
2022 getI64Imm(SImm & 0xFFFF, dl)),
2030 Opc = PPCSubTarget->hasVSX() ? PPC::XSCMPUDP : PPC::FCMPUD;
2083 case ISD::SETO: Invert =
true;
return 3;
2099 bool HasVSX,
bool &Swap,
bool &Negate) {
2127 return HasVSX ? PPC::XVCMPEQSP : PPC::VCMPEQFP;
2129 return PPC::XVCMPEQDP;
2134 return HasVSX ? PPC::XVCMPGTSP : PPC::VCMPGTFP;
2136 return PPC::XVCMPGTDP;
2141 return HasVSX ? PPC::XVCMPGESP : PPC::VCMPGEFP;
2143 return PPC::XVCMPGEDP;
2171 return PPC::VCMPEQUB;
2173 return PPC::VCMPEQUH;
2175 return PPC::VCMPEQUW;
2177 return PPC::VCMPEQUD;
2181 return PPC::VCMPGTSB;
2183 return PPC::VCMPGTSH;
2185 return PPC::VCMPGTSW;
2187 return PPC::VCMPGTSD;
2191 return PPC::VCMPGTUB;
2193 return PPC::VCMPGTUH;
2195 return PPC::VCMPGTUW;
2197 return PPC::VCMPGTUD;
2212 bool isPPC64 = (PtrVT ==
MVT::i64);
2214 if (!PPCSubTarget->useCRBits() &&
2225 SDValue Ops[] = { Op, getI32Imm(27, dl), getI32Imm(5, dl),
2226 getI32Imm(31, dl) };
2233 Op, getI32Imm(~0U, dl)), 0);
2238 SDValue Ops[] = { Op, getI32Imm(1, dl), getI32Imm(31, dl),
2239 getI32Imm(31, dl) };
2246 SDValue Ops[] = {
T, getI32Imm(1, dl), getI32Imm(31, dl),
2247 getI32Imm(31, dl) };
2251 }
else if (Imm == ~0U) {
2258 Op, getI32Imm(1, dl)), 0);
2268 Op, getI32Imm(~0U, dl));
2274 getI32Imm(1, dl)), 0);
2277 SDValue Ops[] = { AN, getI32Imm(1, dl), getI32Imm(31, dl),
2278 getI32Imm(31, dl) };
2282 SDValue Ops[] = { Op, getI32Imm(1, dl), getI32Imm(31, dl),
2283 getI32Imm(31, dl) };
2298 if (PPCSubTarget->hasQPX())
2304 PPCSubTarget->hasVSX(), Swap, Negate);
2311 return CurDAG->
SelectNodeTo(N, PPCSubTarget->hasVSX() ? PPC::XXLNOR :
2316 return CurDAG->
SelectNodeTo(N, VCmpInst, ResVT, LHS, RHS);
2319 if (PPCSubTarget->useCRBits())
2324 SDValue CCReg = SelectCC(LHS, RHS, CC, dl);
2332 InFlag).getValue(1);
2337 SDValue Ops[] = { IntCR, getI32Imm((32 - (3 - Idx)) & 31, dl),
2338 getI32Imm(31, dl), getI32Imm(31, dl) };
2351 MemOp[0] = cast<MemSDNode>(
N)->getMemOperand();
2352 cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
2374 if (
SDNode *NN = SelectBitPermutation(N))
2387 SDNode *SN = SelectSETCC(N);
2393 return getGlobalBaseReg();
2396 return getFrameIndex(N, N);
2413 getConstantIntValue(), dl,
2423 "Expecting i64 or i32 in PPCISD::SRA_ADDZE");
2449 assert((!isSExt || LoadedVT ==
MVT::i16) &&
"Invalid sext update load");
2450 switch (LoadedVT.getSimpleVT().SimpleTy) {
2452 case MVT::f64: Opcode = PPC::LFDU;
break;
2453 case MVT::f32: Opcode = PPC::LFSU;
break;
2454 case MVT::i32: Opcode = PPC::LWZU;
break;
2455 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU;
break;
2457 case MVT::i8: Opcode = PPC::LBZU;
break;
2461 assert((!isSExt || LoadedVT ==
MVT::i16) &&
"Invalid sext update load");
2462 switch (LoadedVT.getSimpleVT().SimpleTy) {
2464 case MVT::i64: Opcode = PPC::LDU;
break;
2465 case MVT::i32: Opcode = PPC::LWZU8;
break;
2466 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8;
break;
2468 case MVT::i8: Opcode = PPC::LBZU8;
break;
2474 SDValue Ops[] = { Offset, Base, Chain };
2475 return transferMemOperands(
2485 assert((!isSExt || LoadedVT ==
MVT::i16) &&
"Invalid sext update load");
2486 switch (LoadedVT.getSimpleVT().SimpleTy) {
2488 case MVT::v4f64: Opcode = PPC::QVLFDUX;
break;
2489 case MVT::v4f32: Opcode = PPC::QVLFSUX;
break;
2490 case MVT::f64: Opcode = PPC::LFDUX;
break;
2491 case MVT::f32: Opcode = PPC::LFSUX;
break;
2492 case MVT::i32: Opcode = PPC::LWZUX;
break;
2493 case MVT::i16: Opcode = isSExt ? PPC::LHAUX : PPC::LHZUX;
break;
2495 case MVT::i8: Opcode = PPC::LBZUX;
break;
2500 "Invalid sext update load");
2501 switch (LoadedVT.getSimpleVT().SimpleTy) {
2503 case MVT::i64: Opcode = PPC::LDUX;
break;
2504 case MVT::i32: Opcode = isSExt ? PPC::LWAUX : PPC::LWZUX8;
break;
2505 case MVT::i16: Opcode = isSExt ? PPC::LHAUX8 : PPC::LHZUX8;
break;
2507 case MVT::i8: Opcode = PPC::LBZUX8;
break;
2513 SDValue Ops[] = { Base, Offset, Chain };
2514 return transferMemOperands(
2523 unsigned Imm, Imm2, SH, MB, ME;
2531 SDValue Ops[] = { Val, getI32Imm(SH, dl), getI32Imm(MB, dl),
2532 getI32Imm(ME, dl) };
2541 SDValue Ops[] = { Val, getI32Imm(0, dl), getI32Imm(MB, dl),
2542 getI32Imm(ME, dl) };
2559 assert(Imm < 64 &&
"Illegal shift amount");
2564 SDValue Ops[] = { Val, getI32Imm(SH, dl), getI32Imm(MB, dl) };
2582 getI32Imm(0, dl), getI32Imm(MB, dl),
2583 getI32Imm(ME, dl) };
2593 if (
SDNode *
I = SelectBitfieldInsert(N))
2599 APInt LHSKnownZero, LHSKnownOne;
2604 if ((LHSKnownZero.
getZExtValue()|~(uint64_t)Imm) == ~0ULL)
2620 unsigned Imm, SH, MB, ME;
2622 isRotateAndMask(N, Imm,
true, SH, MB, ME)) {
2624 getI32Imm(SH, dl), getI32Imm(MB, dl),
2625 getI32Imm(ME, dl) };
2633 unsigned Imm, SH, MB, ME;
2635 isRotateAndMask(N, Imm,
true, SH, MB, ME)) {
2637 getI32Imm(SH, dl), getI32Imm(MB, dl),
2638 getI32Imm(ME, dl) };
2653 "Invalid input type for ANDIo_1_EQ_BIT");
2655 unsigned Opcode = (InVT ==
MVT::i64) ? PPC::ANDIo8 : PPC::ANDIo;
2663 PPC::sub_eq : PPC::sub_gt, dl,
MVT::i32);
2673 bool isPPC64 = (PtrVT ==
MVT::i64);
2676 if (PPCSubTarget->useCRBits() &&
2685 if (N1C->isNullValue() && N3C->isNullValue() &&
2686 N2C->getZExtValue() == 1ULL && CC ==
ISD::SETNE &&
2707 case 0: SRI = PPC::sub_lt;
break;
2708 case 1: SRI = PPC::sub_gt;
break;
2709 case 2: SRI = PPC::sub_eq;
break;
2710 case 3: SRI = PPC::sub_un;
break;
2717 SDValue C = Inv ? NotCCBit : CCBit,
2718 NotC = Inv ? CCBit : NotCCBit;
2730 unsigned SelectCCOp;
2732 SelectCCOp = PPC::SELECT_CC_I4;
2734 SelectCCOp = PPC::SELECT_CC_I8;
2736 if (PPCSubTarget->hasP8Vector())
2737 SelectCCOp = PPC::SELECT_CC_VSSRC;
2739 SelectCCOp = PPC::SELECT_CC_F4;
2741 if (PPCSubTarget->hasVSX())
2742 SelectCCOp = PPC::SELECT_CC_VSFRC;
2744 SelectCCOp = PPC::SELECT_CC_F8;
2746 SelectCCOp = PPC::SELECT_CC_QFRC;
2748 SelectCCOp = PPC::SELECT_CC_QSRC;
2750 SelectCCOp = PPC::SELECT_CC_QBRC;
2753 SelectCCOp = PPC::SELECT_CC_VSRC;
2755 SelectCCOp = PPC::SELECT_CC_VRRC;
2758 getI32Imm(BROpc, dl) };
2762 if (PPCSubTarget->hasVSX()) {
2777 for (
int i = 0; i < 2; ++i)
2783 if (Op1 == Op2 && DM[0] == 0 && DM[1] == 0 &&
2785 isa<LoadSDNode>(Op1.getOperand(0))) {
2786 LoadSDNode *LD = cast<LoadSDNode>(Op1.getOperand(0));
2790 SelectAddrIdxOnly(LD->
getBasePtr(), Base, Offset)) {
2792 SDValue Ops[] = { Base, Offset, Chain };
2800 if (PPCSubTarget->isLittleEndian()) {
2802 unsigned tmp = DM[0];
2809 SDValue Ops[] = { Op1, Op2, DMV };
2816 bool IsPPC64 = PPCSubTarget->isPPC64();
2831 getI32Imm(cast<ConstantSDNode>(N->
getOperand(1))->getZExtValue(), dl);
2845 case PPC::PRED_LT: Opc = PPC::CRANDC; Swap =
true;
break;
2846 case PPC::PRED_LE: Opc = PPC::CRORC; Swap =
true;
break;
2847 case PPC::PRED_EQ: Opc = PPC::CREQV; Swap =
false;
break;
2848 case PPC::PRED_GE: Opc = PPC::CRORC; Swap =
false;
break;
2849 case PPC::PRED_GT: Opc = PPC::CRANDC; Swap =
false;
break;
2850 case PPC::PRED_NE: Opc = PPC::CRXOR; Swap =
false;
break;
2876 assert ((PPCSubTarget->isPPC64() || PPCSubTarget->isSVR4ABI()) &&
2877 "Only supported for 64-bit ABI and 32-bit SVR4");
2878 if (PPCSubTarget->isSVR4ABI() && !PPCSubTarget->isPPC64()) {
2880 return transferMemOperands(N, CurDAG->
getMachineNode(PPC::LWZtoc, dl,
2903 if (isa<JumpTableSDNode>(GA) || isa<BlockAddressSDNode>(GA) ||
2905 return transferMemOperands(N, CurDAG->
getMachineNode(PPC::LDtocL, dl,
2914 return transferMemOperands(N, CurDAG->
getMachineNode(PPC::LDtocL, dl,
2923 assert(!PPCSubTarget->isPPC64() && PPCSubTarget->isSVR4ABI() &&
2924 "PPCISD::PPC32_PICGOT is only supported for 32-bit SVR4");
2926 N, PPC::PPC32PICGOT, PPCLowering->getPointerTy(CurDAG->
getDataLayout()),
2932 assert(isa<ConstantSDNode>(N->
getOperand(0)) &&
2934 "Invalid operand on VADD_SPLAT!");
2938 unsigned Opc1, Opc2, Opc3;
2942 Opc1 = PPC::VSPLTISB;
2943 Opc2 = PPC::VADDUBM;
2944 Opc3 = PPC::VSUBUBM;
2946 }
else if (EltSize == 2) {
2947 Opc1 = PPC::VSPLTISH;
2948 Opc2 = PPC::VADDUHM;
2949 Opc3 = PPC::VSUBUHM;
2952 assert(EltSize == 4 &&
"Invalid element size on VADD_SPLAT!");
2953 Opc1 = PPC::VSPLTISW;
2954 Opc2 = PPC::VADDUWM;
2955 Opc3 = PPC::VSUBUWM;
2959 if ((Elt & 1) == 0) {
2966 SDValue EltVal = getI32Imm(Elt >> 1, dl);
2971 }
else if (Elt > 0) {
2978 SDValue EltVal = getI32Imm(Elt - 16, dl);
2980 EltVal = getI32Imm(-16, dl);
2992 SDValue EltVal = getI32Imm(Elt + 16, dl);
2994 EltVal = getI32Imm(-16, dl);
3002 return SelectCode(N);
3015 "Only OR nodes are supported for CMPB");
3018 if (!PPCSubTarget->hasCMPB())
3028 bool BytesFound[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
3029 uint64_t Mask = 0, Alt = 0;
3031 auto IsByteSelectCC = [
this](
SDValue O,
unsigned &b,
3032 uint64_t &Mask, uint64_t &Alt,
3044 for (b = 0; b < 8; ++b) {
3045 uint64_t Mask = UINT64_C(0xFF) << (8*b);
3046 if (PM && (PM & Mask) == PM && (PAlt & Mask) == PAlt)
3090 if (ULim != (UINT64_C(1) << b*8))
3151 while (!Queue.empty()) {
3152 SDValue V = Queue.pop_back_val();
3156 uint64_t M = 0,
A = 0;
3160 }
else if (IsByteSelectCC(O, b, M,
A, OLHS, ORHS)) {
3164 BytesFound[b] =
true;
3167 }
else if ((LHS == ORHS && RHS == OLHS) ||
3168 (RHS == ORHS && LHS == OLHS)) {
3169 BytesFound[b] =
true;
3181 unsigned LastB = 0, BCnt = 0;
3182 for (
unsigned i = 0; i < 8; ++i)
3183 if (BytesFound[LastB]) {
3188 if (!LastB || BCnt < 2)
3193 if (LHS.getValueType() != VT) {
3200 bool NonTrivialMask = ((int64_t) Mask) != INT64_C(-1);
3201 if (NonTrivialMask && !Alt) {
3228 void PPCDAGToDAGISel::foldBoolExts(
SDValue &Res,
SDNode *&N) {
3229 if (!PPCSubTarget->useCRBits())
3255 auto TryFold = [
this,
N, User, dl](
SDValue Val) {
3261 User->getValueType(0),
3265 SDValue TrueRes = TryFold(ConstTrue);
3268 SDValue FalseRes = TryFold(ConstFalse);
3274 uint64_t True = cast<ConstantSDNode>(TrueRes)->getZExtValue(),
3275 False = cast<ConstantSDNode>(FalseRes)->getZExtValue();
3281 Res = CurDAG->
getSelect(dl, User->getValueType(0), Cond, TrueRes, FalseRes);
3283 ConstTrue = TrueRes;
3284 ConstFalse = FalseRes;
3288 void PPCDAGToDAGISel::PreprocessISelDAG() {
3292 bool MadeChange =
false;
3302 Res = combineToCMPB(N);
3307 foldBoolExts(Res, N);
3310 DEBUG(
dbgs() <<
"PPC DAG preprocessing replacing:\nOld: ");
3327 void PPCDAGToDAGISel::PostprocessISelDAG() {
3335 PeepholePPC64ZExt();
3343 bool PPCDAGToDAGISel::AllUsersSelectZero(
SDNode *N) {
3345 if (!PPCSubTarget->hasISEL())
3376 void PPCDAGToDAGISel::SwapAllSelectUsers(
SDNode *N) {
3383 "Must have all select users");
3388 UE = ToReplace.
end(); UI != UE; ++UI) {
3396 DEBUG(
dbgs() <<
"CR Peephole replacing:\nOld: ");
3402 ReplaceUses(User, ResNode);
3406 void PPCDAGToDAGISel::PeepholeCROps() {
3412 if (!MachineNode || MachineNode->
use_empty())
3414 SDNode *ResNode = MachineNode;
3416 bool Op1Set =
false, Op1Unset =
false,
3418 Op2Set =
false, Op2Unset =
false,
3445 case PPC::SELECT_I4:
3446 case PPC::SELECT_I8:
3447 case PPC::SELECT_F4:
3448 case PPC::SELECT_F8:
3449 case PPC::SELECT_QFRC:
3450 case PPC::SELECT_QSRC:
3451 case PPC::SELECT_QBRC:
3452 case PPC::SELECT_VRRC:
3453 case PPC::SELECT_VSFRC:
3454 case PPC::SELECT_VSSRC:
3455 case PPC::SELECT_VSRC: {
3470 bool SelectSwap =
false;
3483 else if (Op1Unset || Op2Unset)
3499 else if (AllUsersSelectZero(MachineNode))
3521 else if (Op1Unset || Op2Unset)
3537 else if (AllUsersSelectZero(MachineNode))
3547 else if (Op1Set || Op2Set)
3569 else if (AllUsersSelectZero(MachineNode))
3608 else if (AllUsersSelectZero(MachineNode))
3615 if (Op1Set || Op2Set)
3641 else if (AllUsersSelectZero(MachineNode))
3680 else if (AllUsersSelectZero(MachineNode))
3696 else if (Op1Unset || Op2Set)
3715 else if (AllUsersSelectZero(MachineNode))
3726 else if (Op1Set || Op2Unset)
3750 else if (AllUsersSelectZero(MachineNode))
3756 case PPC::SELECT_I4:
3757 case PPC::SELECT_I8:
3758 case PPC::SELECT_F4:
3759 case PPC::SELECT_F8:
3760 case PPC::SELECT_QFRC:
3761 case PPC::SELECT_QSRC:
3762 case PPC::SELECT_QBRC:
3763 case PPC::SELECT_VRRC:
3764 case PPC::SELECT_VSFRC:
3765 case PPC::SELECT_VSSRC:
3766 case PPC::SELECT_VSRC:
3798 SwapAllSelectUsers(MachineNode);
3800 if (ResNode != MachineNode) {
3801 DEBUG(
dbgs() <<
"CR Peephole replacing:\nOld: ");
3807 ReplaceUses(MachineNode, ResNode);
3813 }
while (IsModified);
3923 if (!Op0OK && !Op1OK)
3946 if (!Op0OK && !Op1OK)
3960 void PPCDAGToDAGISel::PeepholePPC64ZExt() {
3961 if (!PPCSubTarget->isPPC64())
3976 bool MadeChange =
false;
4022 bool OutsideUse =
false;
4023 for (
SDNode *PN : ToPromote) {
4025 if (!ToPromote.count(UN) && UN != ISR.
getNode()) {
4043 for (
SDNode *PN : ToPromote) {
4045 switch (PN->getMachineOpcode()) {
4048 case PPC::RLWINM: NewOpcode = PPC::RLWINM8;
break;
4049 case PPC::RLWNM: NewOpcode = PPC::RLWNM8;
break;
4050 case PPC::SLW: NewOpcode = PPC::SLW8;
break;
4051 case PPC::SRW: NewOpcode = PPC::SRW8;
break;
4052 case PPC::LI: NewOpcode = PPC::LI8;
break;
4053 case PPC::LIS: NewOpcode = PPC::LIS8;
break;
4054 case PPC::LHBRX: NewOpcode = PPC::LHBRX8;
break;
4055 case PPC::LWBRX: NewOpcode = PPC::LWBRX8;
break;
4056 case PPC::CNTLZW: NewOpcode = PPC::CNTLZW8;
break;
4057 case PPC::RLWIMI: NewOpcode = PPC::RLWIMI8;
break;
4058 case PPC::OR: NewOpcode = PPC::OR8;
break;
4059 case PPC::SELECT_I4: NewOpcode = PPC::SELECT_I8;
break;
4060 case PPC::ORI: NewOpcode = PPC::ORI8;
break;
4061 case PPC::ORIS: NewOpcode = PPC::ORIS8;
break;
4062 case PPC::AND: NewOpcode = PPC::AND8;
break;
4063 case PPC::ANDIo: NewOpcode = PPC::ANDIo8;
break;
4064 case PPC::ANDISo: NewOpcode = PPC::ANDISo8;
break;
4075 !isa<ConstantSDNode>(V)) {
4092 for (
unsigned i = 0, ie = VTs.
NumVTs; i != ie; ++i)
4098 DEBUG(
dbgs() <<
"PPC64 ZExt Peephole morphing:\nOld: ");
4099 DEBUG(PN->dump(CurDAG));
4104 DEBUG(PN->dump(CurDAG));
4112 DEBUG(
dbgs() <<
"PPC64 ZExt Peephole replacing:\nOld: ");
4118 ReplaceUses(N, Op32.
getNode());
4125 void PPCDAGToDAGISel::PeepholePPC64() {
4127 if (PPCSubTarget->isDarwin() || !PPCSubTarget->isPPC64())
4142 switch (StorageOpcode) {
4175 if (!isa<ConstantSDNode>(N->
getOperand(FirstOp)) ||
4184 bool ReplaceFlags =
true;
4204 ReplaceFlags =
false;
4208 if ((StorageOpcode == PPC::LWA ||
4210 StorageOpcode == PPC::STD) &&
4215 case PPC::ADDIdtprelL:
4218 case PPC::ADDItlsldL:
4230 DEBUG(
dbgs() <<
"Folding add-immediate into mem-op:\nBase: ");
4247 (StorageOpcode ==
PPC::LD || StorageOpcode == PPC::STD ||
4248 StorageOpcode == PPC::LWA)) {
4249 DEBUG(
dbgs() <<
"Rejected this candidate for alignment.\n\n");
4254 dyn_cast<ConstantPoolSDNode>(ImmOpnd)) {
4280 return new PPCDAGToDAGISel(TM);
4284 const char *
Name =
"PowerPC DAG->DAG Pattern Instruction Selection";
4286 nullptr,
false,
false);
bool isInt< 32 >(int64_t x)
bool use_empty() const
Return true if there are no uses of this node.
void push_back(const T &Elt)
SDValue getValue(unsigned R) const
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
T findLastSet(T Val, ZeroBehavior ZB=ZB_Max)
Get the index of the last set bit starting from the least significant bit.
static unsigned SelectInt64CountDirect(int64_t Imm)
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N)
uint64_t getZExtValue() const
Get zero extended value.
void dump() const
Dump this node, for debugging.
static cl::opt< bool > UseBitPermRewriter("ppc-use-bit-perm-rewriter", cl::init(true), cl::desc("use aggressive ppc isel for bit permutations"), cl::Hidden)
BR_CC - Conditional branch.
GPRC = address of GLOBAL_OFFSET_TABLE.
bool hasOneUse() const
Return true if there is exactly one use of this node.
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
static unsigned index2VirtReg(unsigned Index)
index2VirtReg - Convert a 0-based index to a virtual register number.
A Module instance is used to store all the information related to an LLVM module. ...
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
SDVTList getVTList() const
VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded during instruction selection to optimi...
A global registry used in conjunction with static constructors to make pluggable components (like tar...
void computeKnownBits(SDValue Op, APInt &KnownZero, APInt &KnownOne, unsigned Depth=0) const
Determine which bits of Op are known to be either zero or one and return them in the KnownZero/KnownO...
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
An efficient, type-erasing, non-owning reference to a callable.
unsigned getID() const
getID() - Return the register class ID number.
TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or anything else with this node...
bool hasAvailableExternallyLinkage() const
bool isUnindexed() const
Return true if this is NOT a pre/post inc/dec load/store.
unsigned getNumOperands() const
Return the number of values used by this operation.
static bool isInt32Immediate(SDNode *N, unsigned &Imm)
isInt32Immediate - This method tests to see if the node is a 32-bit constant operand.
const SDValue & getOperand(unsigned Num) const
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
void setNodeId(int Id)
Set unique node id.
static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned &Imm)
const SDValue & getBasePtr() const
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
bool isUnsignedIntSetCC(CondCode Code)
isUnsignedIntSetCC - Return true if this is a setcc instruction that performs an unsigned comparison ...
This SDNode is used to implement the code generator support for the llvm IR shufflevector instruction...
GlobalBaseReg - On Darwin, this node represents the result of the mflr at function entry...
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
bool isVector() const
isVector - Return true if this is a vector value type.
static bool PeepholePPC64ZExtGather(SDValue Op32, SmallPtrSetImpl< SDNode * > &ToPromote)
MachineMemOperand - A description of a memory reference used in the backend.
bool hasCommonLinkage() const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
const HexagonInstrInfo * TII
Shift and rotation operations.
std::size_t countTrailingOnes(T Value, ZeroBehavior ZB=ZB_Width)
Count the number of ones from the least significant bit to the first zero bit.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
SDValue getTargetGlobalAddress(const GlobalValue *GV, SDLoc DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
Reg
All possible values of the reg field in the ModR/M byte.
Number of individual test Apply this number of consecutive mutations to each input exit after the first new interesting input is found the minimized corpus is saved into the first input directory Number of jobs to run If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
unsigned getMachineOpcode() const
bool isStrongDefinitionForLinker() const
Returns true if this global's definition will be the one chosen by the linker.
int getMaskElt(unsigned Idx) const
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
iterator_range< allnodes_iterator > allnodes()
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const MachineBasicBlock & front() const
static unsigned SelectInt64Count(int64_t Imm)
CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based loops.
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
Simple integer binary arithmetic operators.
bool isMask_64(uint64_t Value)
isMask_64 - This function returns true if the argument is a non-empty sequence of ones starting at th...
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
TargetConstant* - Like Constant*, but the DAG does not do any folding, simplification, or lowering of the constant.
EVT getMemoryVT() const
Return the type of the in-memory value.
SDValue getAnyExtOrTrunc(SDValue Op, SDLoc DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either any-extending or truncat...
Type * getElementType() const
const DataLayout & getDataLayout() const
TargetInstrInfo - Interface to description of machine instruction set.
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Get a value with high bits set.
SDNode * getNode() const
get the SDNode which holds the desired result
IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
bundle_iterator< MachineInstr, instr_iterator > iterator
static bool isIntS16Immediate(SDNode *N, short &Imm)
isIntS16Immediate - This method tests to see if the node is either a 32-bit or 64-bit immediate...
initializer< Ty > init(const Ty &Val)
cl::opt< bool > ANDIGlueBug("expose-ppc-andi-glue-bug", cl::desc("expose the ANDI glue bug on PPC"), cl::Hidden)
MVT - Machine Value Type.
const SDValue & getOperand(unsigned i) const
This is an important base class in LLVM.
static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC)
CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a MTCTR instruction.
This file contains the declarations for the subclasses of Constant, which represent the different fla...
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
APInt Xor(const APInt &LHS, const APInt &RHS)
Bitwise XOR function for APInt.
INSERT_SUBREG - This instruction takes three operands: a register that has subregisters, a register providing an insert value, and a subregister index.
void RemoveDeadNodes()
This method deletes all unreachable nodes in the SelectionDAG.
This class provides iterator support for SDUse operands that use a specific SDNode.
const PPCTargetLowering * getTargetLowering() const override
SDValue getTargetConstant(uint64_t Val, SDLoc DL, EVT VT, bool isOpaque=false)
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
static bool isInt64Immediate(SDNode *N, uint64_t &Imm)
isInt64Immediate - This method tests to see if the node is a 64-bit constant operand.
unsigned getOpcode() const
void initializePPCDAGToDAGISelPass(PassRegistry &)
FunctionPass class - This class is used to implement most global optimizations.
void RemoveDeadNode(SDNode *N)
Remove the specified node from the system.
use_iterator use_begin() const
Provide iteration support to walk over all uses of an SDNode.
PPCTargetMachine - Common code between 32-bit and 64-bit PowerPC targets.
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth=0) const
Return true if 'Op & Mask' is known to be zero.
PassInfo class - An instance of this class exists for every pass known by the system, and can be obtained from a live Pass by calling its getPassInfo() method.
EVT - Extended Value Type.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
ISD::MemIndexedMode getAddressingMode() const
Return the addressing mode for this load or store: unindexed, pre-inc, pre-dec, post-inc, or post-dec.
uint64_t getConstantOperandVal(unsigned Num) const
Helper method returns the integer value of a ConstantSDNode operand.
const SDValue & getRoot() const
Return the root tag of the SelectionDAG.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
const SDValue & getOffset() const
static cl::opt< bool > BPermRewriterNoMasking("ppc-bit-perm-rewriter-stress-rotates", cl::desc("stress rotate selection in aggressive ppc isel for ""bit permutations"), cl::Hidden)
SDValue getTargetConstantPool(const Constant *C, EVT VT, unsigned Align=0, int Offset=0, unsigned char TargetFlags=0)
SDValue FoldConstantArithmetic(unsigned Opcode, SDLoc DL, EVT VT, SDNode *Cst1, SDNode *Cst2)
EXTRACT_SUBREG - This instruction takes two operands: a register that has subregisters, and a subregister index.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
GPRC = TOC_ENTRY GA, TOC Loads the entry for GA from the TOC, where the TOC base is given by the last...
PICLevel::Level getPICLevel() const
Returns the PIC level (small or large model)
allnodes_const_iterator allnodes_begin() const
bool isFunctionTy() const
isFunctionTy - True if this is an instance of FunctionType.
SDNode * UpdateNodeOperands(SDNode *N, SDValue Op)
Mutate the specified node in-place to have the specified operands.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
SDNode * SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT)
These are used for target selectors to mutate the specified node to have the specified return type...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Module.h This file contains the declarations for the Module class.
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
An SDNode that represents everything that will be needed to construct a MachineInstr.
const SDValue & getChain() const
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
bool isMachineOpcode() const
Represents one node in the SelectionDAG.
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
These values identify relocations on immediates folded into memory operations.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
i1 = ANDIo_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the eq or gt bit of CR0 after execu...
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
Target - Wrapper for Target specific information.
Class for arbitrary precision integers.
bool isUInt< 32 >(uint64_t x)
iterator_range< use_iterator > uses()
static use_iterator use_end()
ZERO_EXTEND - Used for integer types, zeroing the new bits.
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
ANY_EXTEND - Used for integer types. The high bits are undefined.
The combination of sra[wd]i and addze used to implemented signed integer division by a power of 2...
static bool isZero(Value *V, const DataLayout &DL, DominatorTree *DT, AssumptionCache *AC)
PointerType * getType() const
Global values are always pointers.
uint64_t getConstantOperandVal(unsigned i) const
Bitwise operators - logical and, logical or, logical xor.
bool isDeclaration() const
Return true if the primary definition of this global value is outside of the current translation unit...
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
COPY_TO_REGCLASS - This instruction is a placeholder for a plain register-to-register copy into a spe...
static SDNode * SelectInt64Direct(SelectionDAG *CurDAG, SDLoc dl, int64_t Imm)
ArrayRef< SDUse > ops() const
The CMPB instruction (takes two operands of i32 or i64).
MachineSDNode * getMachineNode(unsigned Opcode, SDLoc dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s), MachineInstr opcode, and operands.
bool isInt< 16 >(int64_t x)
static SDNode * SelectInt64(SelectionDAG *CurDAG, SDLoc dl, int64_t Imm)
EVT getValueType() const
Return the ValueType of the referenced return value.
SDValue getConstant(uint64_t Val, SDLoc DL, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue getSelect(SDLoc DL, EVT VT, SDValue Cond, SDValue LHS, SDValue RHS)
Helper function to make it easier to build Select's if you just have operands and don't want to check...
unsigned getAlignment() const
const ARM::ArchExtKind Kind
static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME)
Returns true iff Val consists of one contiguous run of 1s with any number of 0s on either side...
bool operator<(int64_t V1, const APSInt &V2)
static uint64_t Rot64(uint64_t Imm, unsigned R)
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
SDValue getTargetExtractSubreg(int SRIdx, SDLoc DL, EVT VT, SDValue Operand)
A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG nodes.
Module * getParent()
Get the module that this global value is contained inside of...
LLVM Value Representation.
SDValue getRegister(unsigned Reg, EVT VT)
#define CALL_ONCE_INITIALIZATION(function)
CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This corresponds to the COND_BRANCH pseudo ...
bool isUInt< 16 >(uint64_t x)
static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert)
getCRIdxForSetCC - Return the index of the condition register field associated with the SetCC conditi...
BasicBlockListType::iterator iterator
const TargetLowering & getTargetLoweringInfo() const
void ReplaceAllUsesOfValueWith(SDValue From, SDValue To)
Replace any uses of From with To, leaving uses of other values produced by From.Val alone...
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
SetCC operator - This evaluates to a true value iff the condition is true.
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
TRUNCATE - Completely drop the high bits.
FunctionPass * createPPCISelDag(PPCTargetMachine &TM)
createPPCISelDag - This pass converts a legalized DAG into a PowerPC-specific DAG, ready for instruction scheduling.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
static void initializePassOnce(PassRegistry &Registry)
void registerPass(const PassInfo &PI, bool ShouldFree=false)
registerPass - Register a pass (by means of its PassInfo) with the registry.
MachineInstr::mmo_iterator allocateMemRefsArray(unsigned long Num)
allocateMemRefsArray - Allocate an array to hold MachineMemOperand pointers.
virtual const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const
getPointerRegClass - Returns a TargetRegisterClass used for pointer values.
SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a scalar value into element 0 of the...
EVT changeVectorElementTypeToInteger() const
changeVectorElementTypeToInteger - Return a vector with the same number of elements as this vector...
MVT getSimpleVT() const
getSimpleVT - Return the SimpleValueType held in the specified simple EVT.
bool isMachineOpcode() const
Test if this node has a post-isel opcode, directly corresponding to a MachineInstr opcode...
unsigned getMachineOpcode() const
This may only be called if isMachineOpcode returns true.
static unsigned int getVCmpInst(MVT VecVT, ISD::CondCode CC, bool HasVSX, bool &Swap, bool &Negate)
This class is used to represent ISD::LOAD nodes.