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LLVM
3.7.0
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#include <ARMBaseInstrInfo.h>
Protected Member Functions | |
| ARMBaseInstrInfo (const ARMSubtarget &STI) | |
| void | expandLoadStackGuardBase (MachineBasicBlock::iterator MI, unsigned LoadImmOpc, unsigned LoadOpc, Reloc::Model RM) const |
| bool | getRegSequenceLikeInputs (const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const override |
Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx. More... | |
| bool | getExtractSubregLikeInputs (const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const override |
Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx. More... | |
| bool | getInsertSubregLikeInputs (const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const override |
Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx. More... | |
Definition at line 31 of file ARMBaseInstrInfo.h.
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Definition at line 95 of file ARMBaseInstrInfo.cpp.
References ARM_MLxTable, llvm::array_lengthof(), llvm::SmallSet< T, N, C >::insert(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::insert(), and ARM_MLxEntry::MLxOpc.
| const MachineInstrBuilder & ARMBaseInstrInfo::AddDReg | ( | MachineInstrBuilder & | MIB, |
| unsigned | Reg, | ||
| unsigned | SubIdx, | ||
| unsigned | State, | ||
| const TargetRegisterInfo * | TRI | ||
| ) | const |
Definition at line 834 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::MCRegisterInfo::getSubReg(), and llvm::TargetRegisterInfo::isPhysicalRegister().
Referenced by llvm::Thumb2InstrInfo::loadRegFromStackSlot(), loadRegFromStackSlot(), llvm::Thumb2InstrInfo::storeRegToStackSlot(), and storeRegToStackSlot().
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Definition at line 278 of file ARMBaseInstrInfo.cpp.
References llvm::MachineBasicBlock::begin(), llvm::SmallVectorImpl< T >::clear(), llvm::DI, llvm::SmallVectorBase::empty(), llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), I, llvm::isCondBranchOpcode(), llvm::isIndirectBranchOpcode(), llvm::isJumpTableBranchOpcode(), isPredicated(), llvm::isUncondBranchOpcode(), and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().
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analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue.
Return true if the comparison instruction can be analyzed.
Definition at line 2242 of file ARMBaseInstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::getReg().
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Definition at line 1809 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().
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areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address.
It should only return true if the base pointers are the same and the only differences between the two addresses is the offset. It also returns the offsets by reference.
It should only return true if the base pointers are the same and the only differences between the two addresses is the offset. It also returns the offsets by reference.
FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched is permanently disabled.
Definition at line 1491 of file ARMBaseInstrInfo.cpp.
References llvm::SDNode::getMachineOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::isMachineOpcode(), and llvm::ARMSubtarget::isThumb1Only().
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Definition at line 4468 of file ARMBaseInstrInfo.cpp.
References llvm::AddDefaultPred(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstr::addRegisterKilled(), llvm::BuildMI(), contains(), llvm::HexagonMCInstrInfo::getDesc(), llvm::MachineOperand::getReg(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MCRegisterInfo::isSuperRegister(), and llvm::AArch64CC::MI.
canCauseFpMLxStall - Return true if an instruction of the specified opcode will cause stalls when scheduled after (within 4-cycle window) a fp MLA / MLS instruction.
Definition at line 374 of file ARMBaseInstrInfo.h.
References llvm::SmallSet< T, N, C >::count().
Referenced by llvm::ARMHazardRecognizer::getHazardType().
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commuteInstruction - Handle commutable instructions.
Definition at line 1749 of file ARMBaseInstrInfo.cpp.
References llvm::ARMCC::AL, llvm::TargetInstrInfo::commuteInstruction(), llvm::MachineInstr::findFirstPredOperandIdx(), llvm::getInstrPredicate(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::ARMCC::getOppositeCondition(), and llvm::AArch64CC::MI.
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Definition at line 128 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::ARMII::AddrMode2, llvm::ARMII::AddrMode3, llvm::ARMII::AddrModeMask, llvm::LiveVariables::addVirtualRegisterDead(), llvm::LiveVariables::addVirtualRegisterKilled(), llvm::BuildMI(), EnableARM3Addr, llvm::ARM_AM::getAM2Offset(), llvm::ARM_AM::getAM2Op(), llvm::ARM_AM::getAM2ShiftOpc(), llvm::ARM_AM::getAM3Offset(), llvm::ARM_AM::getAM3Op(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::ARM_AM::getSOImmVal(), llvm::ARM_AM::getSORegOpc(), getUnindexedOpcode(), llvm::LiveVariables::getVarInfo(), llvm::ARMII::IndexModeMask, llvm::ARMII::IndexModePost, llvm::ARMII::IndexModePre, llvm::ARMII::IndexModeShift, llvm::MachineOperand::isDead(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isKill(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isUse(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::LiveVariables::VarInfo::Kills, llvm_unreachable, llvm::MachineInstr::mayStore(), llvm::AArch64CC::MI, llvm::MachineInstr::readsRegister(), llvm::LiveVariables::VarInfo::removeKill(), llvm::MachineOperand::setIsDead(), llvm::ARM_AM::sub, llvm::MCInstrDesc::TSFlags, and VI.
| void ARMBaseInstrInfo::copyFromCPSR | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | I, | ||
| unsigned | DestReg, | ||
| bool | KillSrc, | ||
| const ARMSubtarget & | Subtarget | ||
| ) | const |
Definition at line 659 of file ARMBaseInstrInfo.cpp.
References llvm::AddDefaultPred(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::getKillRegState(), llvm::RegState::Implicit, llvm::ARMSubtarget::isMClass(), and llvm::ARMSubtarget::isThumb().
Referenced by copyPhysReg().
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Definition at line 702 of file ARMBaseInstrInfo.cpp.
References llvm::AddDefaultCC(), llvm::AddDefaultPred(), llvm::MachineInstrBuilder::addReg(), llvm::MachineInstr::addRegisterDefined(), llvm::MachineInstr::addRegisterKilled(), llvm::BuildMI(), contains(), copyFromCPSR(), copyToCPSR(), llvm::SmallSet< T, N, C >::count(), llvm::getKillRegState(), getRegisterInfo(), llvm::MCRegisterInfo::getSubReg(), llvm::SmallSet< T, N, C >::insert(), llvm::ARMSubtarget::isFPOnlySP(), llvm::ARMSubtarget::isThumb2(), and llvm::TargetRegisterInfo::regsOverlap().
Referenced by llvm::Thumb2InstrInfo::copyPhysReg().
| void ARMBaseInstrInfo::copyToCPSR | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | I, | ||
| unsigned | SrcReg, | ||
| bool | KillSrc, | ||
| const ARMSubtarget & | Subtarget | ||
| ) | const |
Definition at line 680 of file ARMBaseInstrInfo.cpp.
References llvm::AddDefaultPred(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::RegState::Define, llvm::getKillRegState(), llvm::RegState::Implicit, llvm::ARMSubtarget::isMClass(), and llvm::ARMSubtarget::isThumb().
Referenced by copyPhysReg().
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Definition at line 109 of file ARMBaseInstrInfo.cpp.
References llvm::TargetInstrInfo::CreateTargetHazardRecognizer().
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Definition at line 120 of file ARMBaseInstrInfo.cpp.
References llvm::TargetInstrInfo::CreateTargetPostRAHazardRecognizer(), llvm::ARMSubtarget::hasVFP2(), and llvm::ARMSubtarget::isThumb2().
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Definition at line 504 of file ARMBaseInstrInfo.cpp.
References llvm::MachineOperand::clobbersPhysReg(), Found(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isReg(), and llvm::MachineOperand::isRegMask().
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Definition at line 1381 of file ARMBaseInstrInfo.cpp.
References llvm::TargetInstrInfo::duplicate(), duplicateCPV(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::AArch64CC::MI, llvm::MachineOperand::setImm(), and llvm::MachineOperand::setIndex().
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Definition at line 4039 of file ARMBaseInstrInfo.cpp.
References llvm::AddDefaultPred(), llvm::MachineInstrBuilder::addGlobalAddress(), llvm::BuildMI(), llvm::DL, llvm::MachinePointerInfo::getGOT(), llvm::MachineBasicBlock::getParent(), llvm::ARMSubtarget::GVIsIndirectSymbol(), llvm::RegState::Kill, llvm::ARMII::MO_NONLAZY, llvm::MachineMemOperand::MOInvariant, and llvm::MachineMemOperand::MOLoad.
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Definition at line 1228 of file ARMBaseInstrInfo.cpp.
References llvm::AddDefaultPred(), contains(), llvm::dbgs(), DEBUG, llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::TargetRegisterInfo::getMatchingSuperReg(), getRegisterInfo(), llvm::TargetMachine::getRelocationModel(), getSubtarget(), llvm::MachineFunction::getTarget(), llvm::RegState::Implicit, llvm::ARMSubtarget::isCortexA15(), llvm::ARMSubtarget::isFPOnlySP(), llvm::TargetOpcode::LOAD_STACK_GUARD, llvm::AArch64CC::MI, llvm::NVPTX::PTXCvtMode::RM, and WidenVMOVS.
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FoldImmediate - 'Reg' is known to be defined by a move immediate instruction, try to fold the immediate into the use instruction.
Definition at line 2593 of file ARMBaseInstrInfo.cpp.
References llvm::AddDefaultCC(), llvm::AddDefaultPred(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineOperand::ChangeToImmediate(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MachineInstr::eraseFromParent(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::getKillRegState(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::ARM_AM::getSOImmTwoPartFirst(), llvm::ARM_AM::getSOImmTwoPartSecond(), llvm::ARM_AM::getT2SOImmTwoPartFirst(), llvm::ARM_AM::getT2SOImmTwoPartSecond(), llvm::MachineRegisterInfo::hasOneNonDBGUse(), llvm::MCInstrDesc::hasOptionalDef(), llvm::MachineOperand::isDead(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isKill(), llvm::ARM_AM::isSOImmTwoPartVal(), llvm::ARM_AM::isT2SOImmTwoPartVal(), llvm::MachineInstr::setDesc(), llvm::MachineOperand::setIsKill(), and llvm::MachineOperand::setReg().
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VFP/NEON execution domains.
Definition at line 4105 of file ARMBaseInstrInfo.cpp.
References llvm::ARMII::DomainMask, llvm::ARMII::DomainNEON, llvm::ARMII::DomainNEONA8, llvm::ARMII::DomainVFP, ExeGeneric, ExeNEON, ExeVFP, llvm::MachineInstr::getDesc(), llvm::MachineInstr::getOpcode(), llvm::ARMSubtarget::hasNEON(), llvm::ARMSubtarget::isCortexA8(), llvm::ARMSubtarget::isCortexA9(), isPredicated(), and llvm::MCInstrDesc::TSFlags.
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Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx.
[out] InputReg of the equivalent EXTRACT_SUBREG. E.g., EXTRACT_SUBREG vreg1:sub1, sub0, sub1 would produce:
MI, DefIdx. False otherwise.Definition at line 4545 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getNumDefs(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineInstr::isExtractSubregLike(), llvm_unreachable, llvm::MachineOperand::Reg, and llvm::ARMISD::VMOVRRD.
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Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx.
[out] BaseReg and [out] InsertedReg contain the equivalent inputs of INSERT_SUBREG. E.g., INSERT_SUBREG vreg0:sub0, vreg1:sub1, sub3 would produce:
MI, DefIdx. False otherwise.Definition at line 4566 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::MCInstrDesc::getNumDefs(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineInstr::isInsertSubregLike(), llvm_unreachable, and llvm::MachineOperand::Reg.
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GetInstSize - Returns the size of the specified MachineInstr.
GetInstSize - Return the size of the specified MachineInstr.
Definition at line 597 of file ARMBaseInstrInfo.cpp.
References llvm::TargetOpcode::BUNDLE, llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::TargetMachine::getMCAsmInfo(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MCInstrDesc::getSize(), llvm::MachineOperand::getSymbolName(), llvm::MachineFunction::getTarget(), and llvm::ISD::INLINEASM.
Referenced by GetFunctionSizeInBytes().
| unsigned ARMBaseInstrInfo::getNumLDMAddresses | ( | const MachineInstr * | MI | ) | const |
Get the number of addresses by LDM or VLDM or zero for unknown.
Definition at line 2954 of file ARMBaseInstrInfo.cpp.
References I, llvm::MachineInstr::memoperands_begin(), and llvm::MachineInstr::memoperands_end().
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Definition at line 2964 of file ARMBaseInstrInfo.cpp.
References llvm::Class, llvm::MachineInstr::getDesc(), llvm::InstrItineraryData::getNumMicroOps(), getNumMicroOpsSwiftLdSt(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MCInstrDesc::getSchedClass(), llvm::MachineInstr::hasOneMemOperand(), llvm::ARMSubtarget::isCortexA7(), llvm::ARMSubtarget::isCortexA8(), llvm::InstrItineraryData::isEmpty(), llvm::ARMSubtarget::isLikeA9(), llvm::ARMSubtarget::isSwift(), llvm_unreachable, llvm::MCInstrDesc::mayLoad(), llvm::MCInstrDesc::mayStore(), and llvm::MachineInstr::memoperands_begin().
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Definition at line 3600 of file ARMBaseInstrInfo.cpp.
References adjustDefLatency(), llvm::ARMISD::FMSTAT, getBundledDefMI(), getBundledUseMI(), llvm::MachineInstr::getDesc(), llvm::MachineFunction::getFunction(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), getRegisterInfo(), llvm::Function::hasFnAttribute(), llvm::MachineInstr::hasOneMemOperand(), llvm::MachineInstr::isBranch(), llvm::MachineInstr::isBundle(), llvm::MachineInstr::isCopyLike(), llvm::InstrItineraryData::isEmpty(), llvm::MachineOperand::isImplicit(), llvm::MachineInstr::isImplicitDef(), llvm::MachineInstr::isInsertSubreg(), llvm::ARMSubtarget::isLikeA9(), llvm::MachineInstr::isRegSequence(), llvm::ARMSubtarget::isThumb2(), llvm::MachineInstr::memoperands_begin(), and llvm::Attribute::OptimizeForSize.
Referenced by getOperandLatency().
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Definition at line 3689 of file ARMBaseInstrInfo.cpp.
References llvm::dyn_cast(), llvm::ARM_AM::getAM2Offset(), llvm::ARM_AM::getAM2ShiftOpc(), llvm::SDNode::getMachineOpcode(), llvm::MCInstrDesc::getOpcode(), llvm::SDNode::getOperand(), llvm::InstrItineraryData::getOperandCycle(), getOperandLatency(), llvm::MCInstrDesc::getSchedClass(), llvm::ARMSubtarget::isCortexA7(), llvm::ARMSubtarget::isCortexA8(), llvm::InstrItineraryData::isEmpty(), llvm::ARMSubtarget::isLikeA9(), llvm::SDNode::isMachineOpcode(), llvm::ARMSubtarget::isSwift(), llvm::ARM_AM::lsl, llvm::ARM_AM::lsr, llvm::MCInstrDesc::mayLoad(), llvm::MachineSDNode::memoperands_begin(), llvm::MachineSDNode::memoperands_empty(), and llvm::MCInstrDesc::Opcode.
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Definition at line 4406 of file ARMBaseInstrInfo.cpp.
References contains(), llvm::MachineInstr::definesRegister(), llvm::MachineInstr::findRegisterUseOperandIdx(), llvm::TargetRegisterInfo::getMatchingSuperReg(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::ARMSubtarget::isCortexA15(), llvm::ARMSubtarget::isSwift(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::MachineOperand::readsReg(), llvm::MachineInstr::readsVirtualRegister(), and SwiftPartialUpdateClearance.
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Definition at line 128 of file ARMBaseInstrInfo.h.
References llvm::ARMCC::AL, llvm::MachineInstr::findFirstPredOperandIdx(), llvm::MachineOperand::getImm(), and llvm::MachineInstr::getOperand().
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Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx.
[out] InputRegs of the equivalent REG_SEQUENCE. Each element of the list is modeled as <Reg:SubReg, SubIdx>. E.g., REG_SEQUENCE vreg1:sub1, sub0, vreg2, sub1 would produce two elements:
MI, DefIdx. False otherwise.Definition at line 4520 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getNumDefs(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineInstr::isRegSequenceLike(), llvm_unreachable, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), and llvm::ARMISD::VMOVDRR.
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Definition at line 102 of file ARMBaseInstrInfo.h.
Referenced by expandPostRAPseudo(), llvm::ARMHazardRecognizer::getHazardType(), and isPredicable().
Implemented in llvm::Thumb2InstrInfo, llvm::ARMInstrInfo, and llvm::Thumb1InstrInfo.
Referenced by convertToThreeAddress().
| bool ARMBaseInstrInfo::hasNOP | ( | ) | const |
Definition at line 4502 of file ARMBaseInstrInfo.cpp.
Referenced by llvm::ARMInstrInfo::getNoopForMachoTarget().
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Definition at line 394 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addOperand(), llvm::MachineInstrBuilder::addReg(), llvm::ARMCC::AL, llvm::BuildMI(), llvm::ArrayRef< T >::empty(), llvm::MachineFunction::getInfo(), llvm::MachineBasicBlock::getParent(), isThumb(), llvm::ARMFunctionInfo::isThumb2Function(), llvm::ARMFunctionInfo::isThumbFunction(), and llvm::ArrayRef< T >::size().
isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS instruction.
Definition at line 360 of file ARMBaseInstrInfo.h.
References llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::count().
Referenced by llvm::ARMHazardRecognizer::getHazardType().
| bool ARMBaseInstrInfo::isFpMLxInstruction | ( | unsigned | Opcode, |
| unsigned & | MulOpc, | ||
| unsigned & | AddSubOpc, | ||
| bool & | NegAcc, | ||
| bool & | HasLane | ||
| ) | const |
isFpMLxInstruction - This version also returns the multiply opcode and the addition / subtraction opcode to expand to.
Return true for 'HasLane' for the MLX instructions with an extra lane operand.
Definition at line 4070 of file ARMBaseInstrInfo.cpp.
References ARM_MLxEntry::AddSubOpc, ARM_MLxTable, llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::end(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::find(), ARM_MLxEntry::HasLane, ARM_MLxEntry::MulOpc, and ARM_MLxEntry::NegAcc.
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Definition at line 1173 of file ARMBaseInstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), and llvm::MachineOperand::isReg().
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Definition at line 1221 of file ARMBaseInstrInfo.cpp.
References llvm::NVPTXISD::Dummy, and llvm::MachineInstr::mayLoad().
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isPredicable - Return true if the specified instruction can be predicated.
By default, this returns true for every instruction with a PredicateOperand.
Definition at line 558 of file ARMBaseInstrInfo.cpp.
References llvm::ARMII::DomainMask, llvm::ARMII::DomainNEON, llvm::MachineInstr::getDesc(), llvm::MachineFunction::getInfo(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), getSubtarget(), isEligibleForITBlock(), llvm::MachineInstr::isPredicable(), llvm::ARMFunctionInfo::isThumb2Function(), llvm::isV8EligibleForIT(), llvm::ARMSubtarget::restrictIT(), and llvm::MCInstrDesc::TSFlags.
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Definition at line 441 of file ARMBaseInstrInfo.cpp.
References llvm::ARMCC::AL, llvm::MachineInstr::findFirstPredOperandIdx(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), I, llvm::MachineBasicBlock::instr_end(), llvm::MachineInstr::isBundle(), and llvm::AArch64CC::MI.
Referenced by AnalyzeBranch(), getExecutionDomain(), optimizeCompareInstr(), and setExecutionDomain().
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Definition at line 234 of file ARMBaseInstrInfo.h.
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Definition at line 1646 of file ARMBaseInstrInfo.cpp.
References llvm::ARMCC::AL, llvm::MachineBasicBlock::begin(), llvm::MachineBasicBlock::empty(), F(), llvm::BranchProbability::getDenominator(), llvm::MachineFunction::getFunction(), llvm::getInstrPredicate(), llvm::ARMSubtarget::getMispredictionPenalty(), llvm::BranchProbability::getNumerator(), llvm::MachineInstr::getOpcode(), llvm::MachineBasicBlock::getParent(), llvm::Function::hasFnAttribute(), llvm::isARMLowRegister(), llvm::Attribute::MinSize, llvm::Attribute::OptimizeForSize, P, llvm::MachineBasicBlock::pred_begin(), and llvm::MachineBasicBlock::rbegin().
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Definition at line 1689 of file ARMBaseInstrInfo.cpp.
References llvm::BranchProbability::getDenominator(), llvm::ARMSubtarget::getMispredictionPenalty(), and llvm::BranchProbability::getNumerator().
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Definition at line 1713 of file ARMBaseInstrInfo.cpp.
References llvm::ARMSubtarget::isSwift().
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Definition at line 982 of file ARMBaseInstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), and llvm::MachineOperand::isReg().
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Definition at line 1030 of file ARMBaseInstrInfo.cpp.
References llvm::NVPTXISD::Dummy, and llvm::MachineInstr::mayStore().
| bool ARMBaseInstrInfo::isSwiftFastImmShift | ( | const MachineInstr * | MI | ) | const |
Returns true if the instruction has a shift by immediate that can be executed in one cycle less.
Definition at line 4506 of file ARMBaseInstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::ARM_AM::getSORegOffset(), llvm::ARM_AM::getSORegShOp(), llvm::ARM_AM::lsl, and llvm::ARM_AM::lsr.
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Definition at line 1037 of file ARMBaseInstrInfo.cpp.
References llvm::AddDefaultPred(), AddDReg(), llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), Align(), llvm::BuildMI(), llvm::RegState::DefineNoRead, llvm::DL, llvm::MachineBasicBlock::end(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), getRegisterInfo(), llvm::TargetRegisterClass::getSize(), llvm::ARMSubtarget::hasV5TEOps(), llvm::RegState::ImplicitDefine, llvm::TargetRegisterInfo::isPhysicalRegister(), llvm_unreachable, and llvm::MachineMemOperand::MOLoad.
Referenced by llvm::Thumb2InstrInfo::loadRegFromStackSlot().
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optimizeCompareInstr - Convert the instruction to set the zero flag so that we can remove a "comparison with zero"; Remove a redundant CMP instruction if the flags can be updated in the same way by an earlier instruction such as SUB.
optimizeCompareInstr - Convert the instruction supplying the argument to the comparison into one that sets the zero bit in the flags register; Remove a redundant Compare instruction if an earlier instruction can set the flags in the same way as Compare.
E.g. SUBrr(r1,r2) and CMPrr(r1,r2). We also handle the case where two operands are swapped: SUBrr(r1,r2) and CMPrr(r2,r1), by updating the condition code of instructions which use the flags.
Definition at line 2346 of file ARMBaseInstrInfo.cpp.
References llvm::ARMCC::AL, llvm::MachineBasicBlock::begin(), llvm::MachineOperand::clobbersPhysReg(), llvm::MachineBasicBlock::end(), llvm::ARMCC::EQ, llvm::MachineInstr::eraseFromParent(), llvm::ARMCC::GE, llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), getRegisterInfo(), getSwappedCondition(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::ARMCC::GT, llvm::ARMCC::HI, llvm::ARMCC::HS, I, llvm::MachineOperand::isDef(), isPredicated(), isRedundantFlagInstr(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isRegMask(), isSuitableForMask(), llvm::ARMCC::LE, llvm::ARMCC::LO, llvm::ARMCC::LS, llvm::ARMCC::LT, llvm::ARMCC::MI, llvm::AArch64CC::MI, llvm::MachineInstr::modifiesRegister(), llvm::ARMCC::NE, llvm::ARMCC::PL, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::MachineInstr::readsRegister(), llvm::MachineOperand::setIsDef(), llvm::MachineOperand::setReg(), llvm::SI, llvm::SmallVectorTemplateCommon< T >::size(), llvm::MachineBasicBlock::succ_begin(), llvm::MachineBasicBlock::succ_end(), llvm::MachineRegisterInfo::use_instr_begin(), llvm::MachineRegisterInfo::use_instr_end(), llvm::ARMCC::VC, and llvm::ARMCC::VS.
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Definition at line 1831 of file ARMBaseInstrInfo.cpp.
References llvm::AddDefaultCC(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addOperand(), llvm::BuildMI(), canFoldIntoMOVCC(), llvm::MachineInstr::clearKillInfo(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::SmallPtrSetImpl< PtrType >::erase(), llvm::MachineInstr::eraseFromParent(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::ARMCC::getOppositeCondition(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::MachineInstr::hasOptionalDef(), llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::AArch64CC::MI, llvm::MachineOperand::setImplicit(), and llvm::MachineInstr::tieOperands().
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Definition at line 458 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstr::findFirstPredOperandIdx(), llvm::getMatchingCondBranchOpcode(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), getReg(), llvm::isUncondBranchOpcode(), llvm::AArch64CC::MI, llvm::MachineInstr::setDesc(), llvm::MachineOperand::setImm(), and llvm::MachineOperand::setReg().
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Definition at line 1396 of file ARMBaseInstrInfo.cpp.
References llvm::MachineConstantPoolEntry::ConstVal, llvm::MachineFunction::getConstantPool(), llvm::MachineConstantPool::getConstants(), llvm::MachineOperand::getGlobal(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getNumOperands(), llvm::MachineOperand::getOffset(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getVRegDef(), llvm::ARMConstantPoolValue::hasSameValue(), llvm::MachineInstr::IgnoreVRegDefs, llvm::MachineOperand::isIdenticalTo(), llvm::MachineInstr::isIdenticalTo(), llvm::MachineConstantPoolEntry::isMachineConstantPoolEntry(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::MachineConstantPoolEntry::MachineCPVal, and llvm::MachineConstantPoolEntry::Val.
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Definition at line 1353 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstrBuilder::addConstantPoolIndex(), llvm::MachineInstrBuilder::addImm(), llvm::BuildMI(), llvm::MachineFunction::CloneMachineInstr(), duplicateCPV(), llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineBasicBlock::insert(), llvm::MachineInstr::memoperands_begin(), llvm::MachineInstr::memoperands_end(), llvm::MachineInstr::setMemRefs(), and llvm::MachineInstr::substituteRegister().
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Definition at line 369 of file ARMBaseInstrInfo.cpp.
References llvm::MachineBasicBlock::begin(), llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getLastNonDebugInstr(), I, llvm::isCondBranchOpcode(), and llvm::isUncondBranchOpcode().
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Definition at line 435 of file ARMBaseInstrInfo.cpp.
References llvm::ARMCC::getOppositeCondition().
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Definition at line 4197 of file ARMBaseInstrInfo.cpp.
References llvm::AddDefaultPred(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::RegState::Define, ExeNEON, getCorrespondingDRegAndLane(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getDesc(), getImplicitSPRUseForDPRUse(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), getRegisterInfo(), llvm::getUndefRegState(), llvm::ARMSubtarget::hasNEON(), llvm::RegState::Implicit, isPredicated(), llvm_unreachable, llvm::AArch64CC::MI, llvm::MachineInstr::readsRegister(), llvm::MachineInstr::RemoveOperand(), llvm::MachineInstr::setDesc(), and llvm::RegState::Undef.
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shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePtr) if two loads should be scheduled togther.
On some targets if two loads are loading from addresses in the same cache line, it's better if they are scheduled together. This function takes two integers that represent the load offsets from the common base address. It returns true if it decides it's desirable to schedule the two loads together. "NumLoads" is the number of loads that have already been scheduled after Load1.
On some targets if two loads are loading from addresses in the same cache line, it's better if they are scheduled together. This function takes two integers that represent the load offsets from the common base address. It returns true if it decides it's desirable to schedule the two loads together. "NumLoads" is the number of loads that have already been scheduled after Load1.
FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched is permanently disabled.
Definition at line 1572 of file ARMBaseInstrInfo.cpp.
References llvm::SDNode::getMachineOpcode(), and llvm::ARMSubtarget::isThumb1Only().
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Definition at line 846 of file ARMBaseInstrInfo.cpp.
References llvm::AddDefaultPred(), AddDReg(), llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), Align(), llvm::BuildMI(), llvm::DL, llvm::MachineBasicBlock::end(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), getRegisterInfo(), llvm::TargetRegisterClass::getSize(), llvm::ARMSubtarget::hasV5TEOps(), llvm_unreachable, and llvm::MachineMemOperand::MOStore.
Referenced by llvm::Thumb2InstrInfo::storeRegToStackSlot().
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Definition at line 478 of file ARMBaseInstrInfo.cpp.
References llvm::ARMCC::AL, llvm::ARMCC::EQ, llvm::ARMCC::GE, llvm::ARMCC::GT, llvm::ARMCC::HI, llvm::ARMCC::HS, llvm::ARMCC::LE, llvm::ARMCC::LO, llvm::ARMCC::LS, llvm::ARMCC::LT, and llvm::ArrayRef< T >::size().
1.8.6