22 #define GET_INSTRINFO_CTOR_DTOR
23 #define GET_INSTRMAP_INFO
24 #include "SystemZGenInstrInfo.inc"
27 static uint64_t
allOnes(
unsigned int Count) {
28 return Count == 0 ? 0 : (uint64_t(1) << (Count - 1) << 1) - 1;
34 if (SystemZ::GRH32BitRegClass.
contains(Reg))
36 assert(SystemZ::GR32BitRegClass.
contains(Reg) &&
"Invalid GRX32");
41 void SystemZInstrInfo::anchor() {}
51 unsigned NewOpcode)
const {
58 MBB->
insert(MI, EarlierMI);
63 HighRegOp.
setReg(RI.getSubReg(HighRegOp.
getReg(), SystemZ::subreg_h64));
64 LowRegOp.
setReg(RI.getSubReg(LowRegOp.
getReg(), SystemZ::subreg_l64));
75 assert(HighOpcode && LowOpcode &&
"Both offsets should be in range");
77 EarlierMI->
setDesc(
get(HighOpcode));
78 MI->setDesc(
get(LowOpcode));
92 assert(NewOpcode &&
"No support for huge argument lists yet");
93 MI->setDesc(
get(NewOpcode));
103 void SystemZInstrInfo::expandRIPseudo(
MachineInstr *MI,
unsigned LowOpcode,
105 bool ConvertHigh)
const {
108 MI->
setDesc(
get(IsHigh ? HighOpcode : LowOpcode));
109 if (IsHigh && ConvertHigh)
117 void SystemZInstrInfo::expandRIEPseudo(
MachineInstr *MI,
unsigned LowOpcode,
119 unsigned HighOpcode)
const {
124 if (!DestIsHigh && !SrcIsHigh)
128 DestReg, SrcReg, SystemZ::LR, 32,
130 MI->
setDesc(
get(DestIsHigh ? HighOpcode : LowOpcode));
138 void SystemZInstrInfo::expandRXYPseudo(
MachineInstr *MI,
unsigned LowOpcode,
139 unsigned HighOpcode)
const {
149 void SystemZInstrInfo::expandZExtPseudo(
MachineInstr *MI,
unsigned LowOpcode,
150 unsigned Size)
const {
165 unsigned SrcReg,
unsigned LowLowOpcode,
166 unsigned Size,
bool KillSrc)
const {
170 if (DestIsHigh && SrcIsHigh)
171 Opcode = SystemZ::RISBHH;
172 else if (DestIsHigh && !SrcIsHigh)
173 Opcode = SystemZ::RISBHL;
174 else if (!DestIsHigh && SrcIsHigh)
175 Opcode = SystemZ::RISBLH;
177 BuildMI(MBB, MBBI, DL,
get(LowLowOpcode), DestReg)
181 unsigned Rotate = (DestIsHigh != SrcIsHigh ? 32 : 0);
182 BuildMI(MBB, MBBI, DL,
get(Opcode), DestReg)
218 int &SrcFrameIndex)
const {
236 DestFrameIndex = FI1;
245 bool AllowModify)
const {
251 while (I != MBB.
begin()) {
253 if (I->isDebugValue())
258 if (!isUnpredicatedTerminator(I))
283 while (std::next(I) != MBB.
end())
313 assert(Cond.
size() == 2 && TBB &&
"Should have seen a conditional branch");
321 unsigned OldCCValid = Cond[0].getImm();
322 unsigned OldCCMask = Cond[1].getImm();
323 if (OldCCValid == Branch.
CCValid && OldCCMask == Branch.
CCMask)
338 while (I != MBB.
begin()) {
340 if (I->isDebugValue())
347 I->eraseFromParent();
357 assert(Cond.
size() == 2 &&
"Invalid condition");
358 Cond[1].setImm(Cond[1].getImm() ^ Cond[0].getImm());
372 assert(TBB &&
"InsertBranch must not be told to insert a fallthrough");
373 assert((Cond.
size() == 2 || Cond.
size() == 0) &&
374 "SystemZ branch conditions have one component!");
378 assert(!FBB &&
"Unconditional branch with multiple successors!");
385 unsigned CCValid = Cond[0].getImm();
386 unsigned CCMask = Cond[1].getImm();
387 BuildMI(&MBB, DL,
get(SystemZ::BRC))
400 unsigned &SrcReg,
unsigned &SrcReg2,
401 int &Mask,
int &
Value)
const {
402 assert(MI->
isCompare() &&
"Caller should have checked for a comparison");
447 if (RLL && RLL->
getOpcode() == SystemZ::LGFR) {
451 if (!RLL || !
isShift(RLL, SystemZ::RLL, 31))
466 for (++MBBI; MBBI != MBBE; ++MBBI) {
484 unsigned SrcReg,
unsigned SrcReg2,
487 assert(!SrcReg2 &&
"Only optimizing constant comparisons so far");
500 case SystemZ::LR:
return SystemZ::LOCR;
501 case SystemZ::LGR:
return SystemZ::LOCGR;
516 unsigned NumCycles,
unsigned ExtraPredCycles,
519 return NumCycles == 1;
524 unsigned NumCyclesT,
unsigned ExtraPredCyclesT,
526 unsigned NumCyclesF,
unsigned ExtraPredCyclesF,
534 assert(Pred.
size() == 2 &&
"Invalid condition");
535 unsigned CCValid = Pred[0].getImm();
536 unsigned CCMask = Pred[1].getImm();
537 assert(CCMask > 0 && CCMask < 15 &&
"Invalid predicate");
543 .addImm(CCValid).
addImm(CCMask)
554 unsigned DestReg,
unsigned SrcReg,
555 bool KillSrc)
const {
557 if (SystemZ::GR128BitRegClass.
contains(DestReg, SrcReg)) {
558 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_h64),
559 RI.getSubReg(SrcReg, SystemZ::subreg_h64), KillSrc);
560 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_l64),
561 RI.getSubReg(SrcReg, SystemZ::subreg_l64), KillSrc);
565 if (SystemZ::GRX32BitRegClass.
contains(DestReg, SrcReg)) {
566 emitGRX32Move(MBB, MBBI, DL, DestReg, SrcReg, SystemZ::LR, 32, KillSrc);
572 if (SystemZ::GR64BitRegClass.
contains(DestReg, SrcReg))
573 Opcode = SystemZ::LGR;
574 else if (SystemZ::FP32BitRegClass.
contains(DestReg, SrcReg))
575 Opcode = SystemZ::LER;
576 else if (SystemZ::FP64BitRegClass.
contains(DestReg, SrcReg))
578 else if (SystemZ::FP128BitRegClass.
contains(DestReg, SrcReg))
579 Opcode = SystemZ::LXR;
580 else if (SystemZ::VR32BitRegClass.
contains(DestReg, SrcReg))
581 Opcode = SystemZ::VLR32;
582 else if (SystemZ::VR64BitRegClass.
contains(DestReg, SrcReg))
583 Opcode = SystemZ::VLR64;
584 else if (SystemZ::VR128BitRegClass.
contains(DestReg, SrcReg))
585 Opcode = SystemZ::VLR;
589 BuildMI(MBB, MBBI, DL,
get(Opcode), DestReg)
596 unsigned SrcReg,
bool isKill,
604 unsigned LoadOpcode, StoreOpcode;
613 unsigned DestReg,
int FrameIdx,
620 unsigned LoadOpcode, StoreOpcode;
630 return ((MCID.
TSFlags & Flag) &&
637 LogicOp() : RegSize(0), ImmLSB(0), ImmSize(0) {}
638 LogicOp(
unsigned regSize,
unsigned immLSB,
unsigned immSize)
639 : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {}
641 explicit operator bool()
const {
return RegSize; }
643 unsigned RegSize, ImmLSB, ImmSize;
649 case SystemZ::NILMux:
return LogicOp(32, 0, 16);
650 case SystemZ::NIHMux:
return LogicOp(32, 16, 16);
651 case SystemZ::NILL64:
return LogicOp(64, 0, 16);
652 case SystemZ::NILH64:
return LogicOp(64, 16, 16);
653 case SystemZ::NIHL64:
return LogicOp(64, 32, 16);
654 case SystemZ::NIHH64:
return LogicOp(64, 48, 16);
655 case SystemZ::NIFMux:
return LogicOp(32, 0, 32);
656 case SystemZ::NILF64:
return LogicOp(64, 0, 32);
657 case SystemZ::NIHF64:
return LogicOp(64, 32, 32);
658 default:
return LogicOp();
669 for (
unsigned I = 1;
I < NumOps; ++
I) {
696 unsigned DestReg = Dest.
getReg();
697 unsigned SrcReg = Src.
getReg();
701 if (Opcode == SystemZ::AHIMux &&
709 int ThreeOperandOpcode = SystemZ::getThreeOperandOpcode(Opcode);
710 if (ThreeOperandOpcode >= 0) {
717 for (
unsigned I = 2;
I < NumOps; ++
I)
731 if (
And.RegSize == 64) {
732 NewOpcode = SystemZ::RISBG;
735 NewOpcode = SystemZ::RISBGN;
737 NewOpcode = SystemZ::RISBMux;
761 if (Ops.
size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
762 if ((Opcode == SystemZ::LA || Opcode == SystemZ::LAY) &&
779 unsigned OpNum = Ops[0];
782 "Invalid size combination");
784 if ((Opcode == SystemZ::AHI || Opcode == SystemZ::AGHI) &&
788 Opcode = (Opcode == SystemZ::AHI ? SystemZ::ASI : SystemZ::AGSI);
796 if (Opcode == SystemZ::LGDR || Opcode == SystemZ::LDGR) {
797 bool Op0IsGPR = (Opcode == SystemZ::LGDR);
798 bool Op1IsGPR = (Opcode == SystemZ::LDGR);
802 unsigned StoreOpcode = Op1IsGPR ? SystemZ::STG : SystemZ::STD;
806 .addFrameIndex(FrameIndex)
813 unsigned LoadOpcode = Op0IsGPR ? SystemZ::LG :
SystemZ::LD;
816 get(LoadOpcode), Dest)
866 int MemOpcode = SystemZ::getMemOpcode(Opcode);
867 if (MemOpcode >= 0) {
869 if (OpNum == NumOps - 1) {
872 assert(AccessBytes != 0 &&
"Size of access should be known");
873 assert(AccessBytes <= Size &&
"Access outside the frame index");
874 uint64_t Offset = Size - AccessBytes;
877 for (
unsigned I = 0;
I < OpNum; ++
I)
897 switch (MI->getOpcode()) {
899 splitMove(MI, SystemZ::LG);
903 splitMove(MI, SystemZ::STG);
911 splitMove(MI, SystemZ::STD);
915 expandRXYPseudo(MI, SystemZ::LB, SystemZ::LBH);
919 expandRXYPseudo(MI, SystemZ::LH, SystemZ::LHH);
922 case SystemZ::LLCRMux:
923 expandZExtPseudo(MI, SystemZ::LLCR, 8);
926 case SystemZ::LLHRMux:
927 expandZExtPseudo(MI, SystemZ::LLHR, 16);
930 case SystemZ::LLCMux:
931 expandRXYPseudo(MI, SystemZ::LLC, SystemZ::LLCH);
934 case SystemZ::LLHMux:
935 expandRXYPseudo(MI, SystemZ::LLH, SystemZ::LLHH);
939 expandRXYPseudo(MI, SystemZ::L, SystemZ::LFH);
942 case SystemZ::STCMux:
943 expandRXYPseudo(MI, SystemZ::STC, SystemZ::STCH);
946 case SystemZ::STHMux:
947 expandRXYPseudo(MI, SystemZ::STH, SystemZ::STHH);
954 case SystemZ::LHIMux:
955 expandRIPseudo(MI, SystemZ::LHI, SystemZ::IIHF,
true);
958 case SystemZ::IIFMux:
959 expandRIPseudo(MI, SystemZ::IILF, SystemZ::IIHF,
false);
962 case SystemZ::IILMux:
963 expandRIPseudo(MI, SystemZ::IILL, SystemZ::IIHL,
false);
966 case SystemZ::IIHMux:
967 expandRIPseudo(MI, SystemZ::IILH, SystemZ::IIHH,
false);
970 case SystemZ::NIFMux:
971 expandRIPseudo(MI, SystemZ::NILF, SystemZ::NIHF,
false);
974 case SystemZ::NILMux:
975 expandRIPseudo(MI, SystemZ::NILL, SystemZ::NIHL,
false);
978 case SystemZ::NIHMux:
979 expandRIPseudo(MI, SystemZ::NILH, SystemZ::NIHH,
false);
982 case SystemZ::OIFMux:
983 expandRIPseudo(MI, SystemZ::OILF, SystemZ::OIHF,
false);
986 case SystemZ::OILMux:
987 expandRIPseudo(MI, SystemZ::OILL, SystemZ::OIHL,
false);
990 case SystemZ::OIHMux:
991 expandRIPseudo(MI, SystemZ::OILH, SystemZ::OIHH,
false);
994 case SystemZ::XIFMux:
995 expandRIPseudo(MI, SystemZ::XILF, SystemZ::XIHF,
false);
998 case SystemZ::TMLMux:
999 expandRIPseudo(MI, SystemZ::TMLL, SystemZ::TMHL,
false);
1002 case SystemZ::TMHMux:
1003 expandRIPseudo(MI, SystemZ::TMLH, SystemZ::TMHH,
false);
1006 case SystemZ::AHIMux:
1007 expandRIPseudo(MI, SystemZ::AHI, SystemZ::AIH,
false);
1010 case SystemZ::AHIMuxK:
1011 expandRIEPseudo(MI, SystemZ::AHI, SystemZ::AHIK, SystemZ::AIH);
1014 case SystemZ::AFIMux:
1015 expandRIPseudo(MI, SystemZ::AFI, SystemZ::AIH,
false);
1018 case SystemZ::CFIMux:
1019 expandRIPseudo(MI, SystemZ::CFI, SystemZ::CIH,
false);
1022 case SystemZ::CLFIMux:
1023 expandRIPseudo(MI, SystemZ::CLFI, SystemZ::CLIH,
false);
1027 expandRXYPseudo(MI, SystemZ::C, SystemZ::CHF);
1030 case SystemZ::CLMux:
1031 expandRXYPseudo(MI, SystemZ::CL, SystemZ::CLHF);
1034 case SystemZ::RISBMux: {
1035 bool DestIsHigh =
isHighReg(MI->getOperand(0).getReg());
1036 bool SrcIsHigh =
isHighReg(MI->getOperand(2).getReg());
1037 if (SrcIsHigh == DestIsHigh)
1038 MI->setDesc(
get(DestIsHigh ? SystemZ::RISBHH : SystemZ::RISBLL));
1040 MI->setDesc(
get(DestIsHigh ? SystemZ::RISBHL : SystemZ::RISBLH));
1041 MI->getOperand(5).setImm(MI->getOperand(5).getImm() ^ 32);
1047 splitAdjDynAlloc(MI);
1083 case SystemZ::BRCTG:
1102 case SystemZ::CLGIJ:
1103 case SystemZ::CLGRJ:
1113 unsigned &LoadOpcode,
1114 unsigned &StoreOpcode)
const {
1115 if (RC == &SystemZ::GR32BitRegClass || RC == &SystemZ::ADDR32BitRegClass) {
1116 LoadOpcode = SystemZ::L;
1118 }
else if (RC == &SystemZ::GRH32BitRegClass) {
1119 LoadOpcode = SystemZ::LFH;
1120 StoreOpcode = SystemZ::STFH;
1121 }
else if (RC == &SystemZ::GRX32BitRegClass) {
1122 LoadOpcode = SystemZ::LMux;
1123 StoreOpcode = SystemZ::STMux;
1124 }
else if (RC == &SystemZ::GR64BitRegClass ||
1125 RC == &SystemZ::ADDR64BitRegClass) {
1126 LoadOpcode = SystemZ::LG;
1127 StoreOpcode = SystemZ::STG;
1128 }
else if (RC == &SystemZ::GR128BitRegClass ||
1129 RC == &SystemZ::ADDR128BitRegClass) {
1130 LoadOpcode = SystemZ::L128;
1131 StoreOpcode = SystemZ::ST128;
1132 }
else if (RC == &SystemZ::FP32BitRegClass) {
1134 StoreOpcode = SystemZ::STE;
1135 }
else if (RC == &SystemZ::FP64BitRegClass) {
1137 StoreOpcode = SystemZ::STD;
1138 }
else if (RC == &SystemZ::FP128BitRegClass) {
1139 LoadOpcode = SystemZ::LX;
1140 StoreOpcode = SystemZ::STX;
1141 }
else if (RC == &SystemZ::VR32BitRegClass) {
1142 LoadOpcode = SystemZ::VL32;
1143 StoreOpcode = SystemZ::VST32;
1144 }
else if (RC == &SystemZ::VR64BitRegClass) {
1145 LoadOpcode = SystemZ::VL64;
1146 StoreOpcode = SystemZ::VST64;
1147 }
else if (RC == &SystemZ::VF128BitRegClass ||
1148 RC == &SystemZ::VR128BitRegClass) {
1149 LoadOpcode = SystemZ::VL;
1150 StoreOpcode = SystemZ::VST;
1156 int64_t Offset)
const {
1159 if (isUInt<12>(Offset) && isUInt<12>(Offset2)) {
1161 int Disp12Opcode = SystemZ::getDisp12Opcode(Opcode);
1162 if (Disp12Opcode >= 0)
1163 return Disp12Opcode;
1169 if (isInt<20>(Offset) && isInt<20>(Offset2)) {
1171 int Disp20Opcode = SystemZ::getDisp20Opcode(Opcode);
1172 if (Disp20Opcode >= 0)
1173 return Disp20Opcode;
1186 case SystemZ::LG:
return SystemZ::LTG;
1187 case SystemZ::LGF:
return SystemZ::LTGF;
1188 case SystemZ::LR:
return SystemZ::LTR;
1189 case SystemZ::LGFR:
return SystemZ::LTGFR;
1190 case SystemZ::LGR:
return SystemZ::LTGR;
1191 case SystemZ::LER:
return SystemZ::LTEBR;
1193 case SystemZ::LXR:
return SystemZ::LTXBR;
1198 case SystemZ::RISBGN:
return SystemZ::RISBG;
1208 uint64_t Top = (Mask >> First) + 1;
1209 if ((Top & -Top) == Top) {
1218 unsigned &Start,
unsigned &End)
const {
1226 unsigned LSB, Length;
1228 Start = 63 - (LSB + Length - 1);
1236 assert(LSB > 0 &&
"Bottom bit must be set");
1237 assert(LSB + Length < BitSize &&
"Top bit must be set");
1238 Start = 63 - (LSB - 1);
1239 End = 63 - (LSB + Length);
1250 return SystemZ::CRJ;
1252 return SystemZ::CGRJ;
1258 return SystemZ::CLRJ;
1260 return SystemZ::CLGRJ;
1263 case SystemZ::CLGFI:
1272 unsigned Reg, uint64_t
Value)
const {
1276 Opcode = SystemZ::LGHI;
1278 Opcode = SystemZ::LLILL;
1280 Opcode = SystemZ::LLILH;
1283 assert(
isInt<32>(Value) &&
"Huge values not handled yet");
1284 Opcode = SystemZ::LGFI;
bool isInt< 32 >(int64_t x)
bool isUInt< 8 >(uint64_t x)
void push_back(const T &Elt)
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
bool isPredicable(MachineInstr *MI) const override
const int64_t CallFrameSize
SystemZInstrInfo(SystemZSubtarget &STI)
unsigned getCompareAndBranch(unsigned Opcode, const MachineInstr *MI=nullptr) const
MachineBasicBlock * getMBB() const
unsigned RemoveBranch(MachineBasicBlock &MBB) const override
Describe properties that are true of each instruction in the target description file.
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
static bool removeIPMBasedCompare(MachineInstr *Compare, unsigned SrcReg, const MachineRegisterInfo *MRI, const TargetRegisterInfo *TRI)
static int isSimpleMove(const MachineInstr *MI, int &FrameIndex, unsigned Flag)
bool use_nodbg_empty(unsigned RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register...
static void eraseIfDead(MachineInstr *MI, const MachineRegisterInfo *MRI)
bool expandPostRAPseudo(MachineBasicBlock::iterator MBBI) const override
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
const char * getSymbolName() const
const unsigned CCMASK_ICMP
unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const override
static uint64_t allOnes(unsigned int Count)
unsigned getLoadAndTest(unsigned Opcode) const
bool hasLoadStoreOnCond() const
void eraseFromParent()
eraseFromParent - This method unlinks 'this' from the containing function and deletes it...
MachineMemOperand - A description of a memory reference used in the backend.
bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const override
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned Reg, uint64_t Value) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isInt< 8 >(int64_t x)
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
const TargetRegisterClass * getRegClass(unsigned Reg) const
getRegClass - Return the register class of the specified virtual register.
Reg
All possible values of the reg field in the ModR/M byte.
void replaceKillInstruction(unsigned Reg, MachineInstr *OldMI, MachineInstr *NewMI)
replaceKillInstruction - Update register kill info by replacing a kill instruction with a new one...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
uint64_t getInstSizeInBytes(const MachineInstr *MI) const
void getLoadStoreOpcodes(const TargetRegisterClass *RC, unsigned &LoadOpcode, unsigned &StoreOpcode) const
static LogicOp interpretAndImmediate(unsigned Opcode)
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
const MachineOperand * Target
const unsigned CCMASK_ANY
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
SystemZII::Branch getBranchInfo(const MachineInstr *MI) const
size_t size() const
size - Get the array size.
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
unsigned getKillRegState(bool B)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Flag
These should be considered private to the implementation of the MCInstrDesc class.
const MachineBasicBlock * getParent() const
bundle_iterator< MachineInstr, instr_iterator > iterator
Control flow instructions. These all have token chains.
unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset) const
static unsigned getAccessSize(unsigned int Flags)
const MachineOperand & getOperand(unsigned i) const
MachineInstr * convertToThreeAddress(MachineFunction::iterator &MFI, MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const override
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, const BranchProbability &Probability) const override
void setImm(int64_t immVal)
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
bool empty() const
empty - Check if the array is empty.
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
bool isRxSBGMask(uint64_t Mask, unsigned BitSize, unsigned &Start, unsigned &End) const
unsigned getSubReg() const
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static bool isImmLH(uint64_t Val)
T findFirstSet(T Val, ZeroBehavior ZB=ZB_Max)
Get the index of the first set bit starting from the least significant bit.
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
static bool isHighReg(unsigned int Reg)
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
MachineInstr * CloneMachineInstr(const MachineInstr *Orig)
CloneMachineInstr - Create a new MachineInstr which is a copy of the 'Orig' instruction, identical in all ways except the instruction has no parent, prev, or next.
MachineOperand class - Representation of each machine instruction operand.
static bool isStringOfOnes(uint64_t Mask, unsigned &LSB, unsigned &Length)
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call...
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
const unsigned CCMASK_CMP_NE
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
bool ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
const MachineInstrBuilder & addFrameIndex(int Idx) const
bool isCompare(QueryType Type=IgnoreBundle) const
Return true if this instruction is a comparison.
static MachineInstr * finishConvertToThreeAddress(MachineInstr *OldMI, MachineInstr *NewMI, LiveVariables *LV)
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
APInt And(const APInt &LHS, const APInt &RHS)
Bitwise AND function for APInt.
bool hasMiscellaneousExtensions() const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Representation of each machine instruction.
static bool isPhysicalRegister(unsigned Reg)
isPhysicalRegister - Return true if the specified register number is in the physical register namespa...
static MachineInstr * getDef(unsigned Reg, const MachineRegisterInfo *MRI)
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
void setReg(unsigned Reg)
Change the register this operand corresponds to.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
static MachineOperand CreateImm(int64_t Val)
static bool isSimpleBD12Move(const MachineInstr *MI, unsigned Flag)
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool PredicateInstruction(MachineInstr *MI, ArrayRef< MachineOperand > Pred) const override
static unsigned getConditionalMove(unsigned Opcode)
bool isInt< 16 >(int64_t x)
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, DebugLoc DL) const override
unsigned getReg() const
getReg - Returns the register number.
bool hasDistinctOps() const
LLVM Value Representation.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex) const override
static bool isShift(MachineInstr *MI, unsigned Opcode, int64_t Imm)
unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const override
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
BasicBlockListType::iterator iterator
uint64_t getSize() const
getSize - Return the size in bytes of the memory reference.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
static bool isImmLL(uint64_t Val)
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
isLayoutSuccessor - Return true if the specified MBB will be emitted immediately after this block...
bool isStackSlotCopy(const MachineInstr *MI, int &DestFrameIndex, int &SrcFrameIndex) const override
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
bool contains(unsigned Reg) const
contains - Return true if the specified register is included in this register class.