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LLVM
3.7.0
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TargetSubtargetInfo - Generic base class for all target subtargets. More...
#include <TargetSubtargetInfo.h>
Public Types | |
| enum | AntiDepBreakMode { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL } |
| typedef SmallVectorImpl< const TargetRegisterClass * > | RegClassVector |
Public Member Functions | |
| virtual | ~TargetSubtargetInfo () |
| virtual const TargetInstrInfo * | getInstrInfo () const |
| virtual const TargetFrameLowering * | getFrameLowering () const |
| virtual const TargetLowering * | getTargetLowering () const |
| virtual const TargetSelectionDAGInfo * | getSelectionDAGInfo () const |
| virtual const TargetRegisterInfo * | getRegisterInfo () const |
| getRegisterInfo - If register information is available, return it. More... | |
| virtual const InstrItineraryData * | getInstrItineraryData () const |
| getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget. More... | |
| virtual unsigned | resolveSchedClass (unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const |
| Resolve a SchedClass at runtime, where SchedClass identifies an MCSchedClassDesc with the isVariant property. More... | |
| virtual bool | enableMachineScheduler () const |
| True if the subtarget should run MachineScheduler after aggressive coalescing. More... | |
| virtual bool | enableMachineSchedDefaultSched () const |
| True if the machine scheduler should disable the TLI preference for preRA scheduling with the source level scheduler. More... | |
| virtual bool | enableJoinGlobalCopies () const |
| True if the subtarget should enable joining global copies. More... | |
| virtual bool | enablePostRAScheduler () const |
| True if the subtarget should run a scheduler after register allocation. More... | |
| virtual bool | enableAtomicExpand () const |
| True if the subtarget should run the atomic expansion pass. More... | |
| virtual void | overrideSchedPolicy (MachineSchedPolicy &Policy, MachineInstr *begin, MachineInstr *end, unsigned NumRegionInstrs) const |
| Override generic scheduling policy within a region. More... | |
| virtual void | adjustSchedDependency (SUnit *def, SUnit *use, SDep &dep) const |
| virtual AntiDepBreakMode | getAntiDepBreakMode () const |
| virtual void | getCriticalPathRCs (RegClassVector &CriticalPathRCs) const |
| virtual CodeGenOpt::Level | getOptLevelToEnablePostRAScheduler () const |
| virtual bool | enableRALocalReassignment (CodeGenOpt::Level OptLevel) const |
| True if the subtarget should run the local reassignment heuristic of the register allocator. More... | |
| virtual bool | useAA () const |
| Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.). More... | |
| virtual bool | enableEarlyIfConversion () const |
| Enable the use of the early if conversion pass. More... | |
| virtual std::unique_ptr < PBQPRAConstraint > | getCustomPBQPConstraints () const |
| Return PBQPConstraint(s) for the target. More... | |
| virtual bool | enableSubRegLiveness () const |
| Enable tracking of subregister liveness in register allocator. More... | |
Public Member Functions inherited from llvm::MCSubtargetInfo | |
| MCSubtargetInfo (const MCSubtargetInfo &)=default | |
| MCSubtargetInfo (const Triple &TT, StringRef CPU, StringRef FS, ArrayRef< SubtargetFeatureKV > PF, ArrayRef< SubtargetFeatureKV > PD, const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP) | |
| const Triple & | getTargetTriple () const |
| getTargetTriple - Return the target triple string. More... | |
| StringRef | getCPU () const |
| getCPU - Return the CPU string. More... | |
| const FeatureBitset & | getFeatureBits () const |
| getFeatureBits - Return the feature bits. More... | |
| void | setFeatureBits (const FeatureBitset &FeatureBits_) |
| setFeatureBits - Set the feature bits. More... | |
| void | setDefaultFeatures (StringRef CPU) |
| Set the features to the default for the given CPU. More... | |
| FeatureBitset | ToggleFeature (uint64_t FB) |
| ToggleFeature - Toggle a feature and returns the re-computed feature bits. More... | |
| FeatureBitset | ToggleFeature (const FeatureBitset &FB) |
| ToggleFeature - Toggle a feature and returns the re-computed feature bits. More... | |
| FeatureBitset | ToggleFeature (StringRef FS) |
| ToggleFeature - Toggle a set of features and returns the re-computed feature bits. More... | |
| FeatureBitset | ApplyFeatureFlag (StringRef FS) |
| Apply a feature flag and return the re-computed feature bits, including all feature bits implied by the flag. More... | |
| const MCSchedModel & | getSchedModelForCPU (StringRef CPU) const |
| getSchedModelForCPU - Get the machine model of a CPU. More... | |
| const MCSchedModel & | getSchedModel () const |
| Get the machine model for this subtarget's CPU. More... | |
| const MCWriteProcResEntry * | getWriteProcResBegin (const MCSchedClassDesc *SC) const |
| Return an iterator at the first process resource consumed by the given scheduling class. More... | |
| const MCWriteProcResEntry * | getWriteProcResEnd (const MCSchedClassDesc *SC) const |
| const MCWriteLatencyEntry * | getWriteLatencyEntry (const MCSchedClassDesc *SC, unsigned DefIdx) const |
| int | getReadAdvanceCycles (const MCSchedClassDesc *SC, unsigned UseIdx, unsigned WriteResID) const |
| InstrItineraryData | getInstrItineraryForCPU (StringRef CPU) const |
| getInstrItineraryForCPU - Get scheduling itinerary of a CPU. More... | |
| void | initInstrItins (InstrItineraryData &InstrItins) const |
| Initialize an InstrItineraryData instance. More... | |
| bool | isCPUStringValid (StringRef CPU) const |
| Check whether the CPU string is valid. More... | |
Protected Member Functions | |
| TargetSubtargetInfo (const Triple &TT, StringRef CPU, StringRef FS, ArrayRef< SubtargetFeatureKV > PF, ArrayRef< SubtargetFeatureKV > PD, const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP) | |
Protected Member Functions inherited from llvm::MCSubtargetInfo | |
| void | InitMCProcessorInfo (StringRef CPU, StringRef FS) |
| Initialize the scheduling model and feature bits. More... | |
TargetSubtargetInfo - Generic base class for all target subtargets.
All Target-specific options that control code generation and printing should be exposed through a TargetSubtargetInfo-derived class.
Definition at line 44 of file TargetSubtargetInfo.h.
Definition at line 63 of file TargetSubtargetInfo.h.
| Enumerator | |
|---|---|
| ANTIDEP_NONE | |
| ANTIDEP_CRITICAL | |
| ANTIDEP_ALL | |
Definition at line 62 of file TargetSubtargetInfo.h.
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protected |
Definition at line 22 of file TargetSubtargetInfo.cpp.
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Definition at line 31 of file TargetSubtargetInfo.cpp.
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Definition at line 146 of file TargetSubtargetInfo.h.
Referenced by llvm::ScheduleDAGInstrs::addVRegUseDeps().
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True if the subtarget should run the atomic expansion pass.
Definition at line 33 of file TargetSubtargetInfo.cpp.
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Enable the use of the early if conversion pass.
Definition at line 176 of file TargetSubtargetInfo.h.
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True if the subtarget should enable joining global copies.
By default this is enabled if the machine scheduler is enabled, but can be overridden.
Definition at line 41 of file TargetSubtargetInfo.cpp.
References enableMachineScheduler().
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True if the machine scheduler should disable the TLI preference for preRA scheduling with the source level scheduler.
Definition at line 118 of file TargetSubtargetInfo.h.
Referenced by llvm::createDefaultScheduler().
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True if the subtarget should run MachineScheduler after aggressive coalescing.
This currently replaces the SelectionDAG scheduler with the "source" order scheduler (though see below for an option to turn this off and use the TargetLowering preference). It does not yet disable the postRA scheduler.
Definition at line 37 of file TargetSubtargetInfo.cpp.
Referenced by llvm::createDefaultScheduler(), and enableJoinGlobalCopies().
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True if the subtarget should run a scheduler after register allocation.
By default this queries the PostRAScheduling bit in the scheduling model which is the preferred way to influence this.
Definition at line 50 of file TargetSubtargetInfo.cpp.
References llvm::MCSubtargetInfo::getSchedModel(), and llvm::MCSchedModel::PostRAScheduler.
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True if the subtarget should run the local reassignment heuristic of the register allocator.
This heuristic may be compile time intensive, OptLevel provides a finer grain to tune the register allocator.
Definition at line 45 of file TargetSubtargetInfo.cpp.
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Enable tracking of subregister liveness in register allocator.
Definition at line 186 of file TargetSubtargetInfo.h.
Referenced by llvm::LiveIntervals::runOnMachineFunction().
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Definition at line 150 of file TargetSubtargetInfo.h.
References ANTIDEP_NONE.
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Definition at line 155 of file TargetSubtargetInfo.h.
References llvm::SmallVectorImpl< T >::clear().
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Return PBQPConstraint(s) for the target.
Override to provide custom PBQP constraints.
Definition at line 181 of file TargetSubtargetInfo.h.
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Definition at line 77 of file TargetSubtargetInfo.h.
Referenced by checkNumAlignedDPRCS2Regs(), llvm::TargetOptions::DisableFramePointerElim(), llvm::AArch64FrameLowering::eliminateCallFramePseudoInstr(), emitDebugValueComment(), llvm::MachineFrameInfo::estimateStackSize(), llvm::AMDGPUInstrInfo::getIndirectIndexEnd(), llvm::MipsRegisterInfo::getRegPressureLimit(), llvm::TargetInstrInfo::getSPAdjust(), llvm::X86InstrInfo::getSPAdjust(), llvm::MachineFunction::MachineFunction(), llvm::MachineFrameInfo::print(), llvm::R600InstrInfo::reserveIndirectRegisters(), and llvm::FunctionLoweringInfo::set().
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Definition at line 76 of file TargetSubtargetInfo.h.
Referenced by llvm::MachineBasicBlock::addLiveIn(), llvm::ARMFrameLowering::adjustForSegmentedStacks(), llvm::VirtRegAuxInfo::calculateSpillWeightAndHint(), llvm::MachineBasicBlock::canFallThrough(), llvm::createBURRListDAGScheduler(), llvm::createHybridListDAGScheduler(), llvm::createILPListDAGScheduler(), llvm::createSourceListDAGScheduler(), llvm::ARMFrameLowering::determineCalleeSaves(), llvm::AArch64FrameLowering::eliminateCallFramePseudoInstr(), llvm::MSP430FrameLowering::eliminateCallFramePseudoInstr(), llvm::BPFRegisterInfo::eliminateFrameIndex(), llvm::MSP430RegisterInfo::eliminateFrameIndex(), llvm::SIRegisterInfo::eliminateFrameIndex(), llvm::XCoreRegisterInfo::eliminateFrameIndex(), llvm::SystemZRegisterInfo::eliminateFrameIndex(), llvm::ARMBaseRegisterInfo::eliminateFrameIndex(), emitAlignedDPRCS2Restores(), emitAlignedDPRCS2Spills(), llvm::AArch64FrameLowering::emitCalleeSavedFrameMoves(), emitComments(), llvm::SparcFrameLowering::emitEpilogue(), llvm::MSP430FrameLowering::emitEpilogue(), llvm::ARMFrameLowering::emitEpilogue(), llvm::AArch64FrameLowering::emitEpilogue(), llvm::SystemZFrameLowering::emitEpilogue(), llvm::AMDGPUAsmPrinter::EmitInstruction(), llvm::BPFTargetLowering::EmitInstrWithCustomInserter(), llvm::MSP430TargetLowering::EmitInstrWithCustomInserter(), llvm::ARMBaseRegisterInfo::emitLoadConstPool(), llvm::NVPTXFrameLowering::emitPrologue(), llvm::SparcFrameLowering::emitPrologue(), llvm::MSP430FrameLowering::emitPrologue(), llvm::AArch64FrameLowering::emitPrologue(), llvm::SystemZFrameLowering::emitPrologue(), llvm::MSP430TargetLowering::EmitShiftInstr(), emitThumb2LoadConstPool(), llvm::RegScavenger::enterBasicBlock(), llvm::finalizeBundle(), llvm::ARMFrameLowering::fixTCReturn(), FoldOperand(), llvm::AArch64InstrInfo::genAlternativeCodeSequence(), llvm::ARMHazardRecognizer::getHazardType(), llvm::MSP430InstrInfo::GetInstSizeInBytes(), llvm::SDNode::getOperationName(), llvm::R600RegisterInfo::getReservedRegs(), llvm::ConvergingVLIWScheduler::initialize(), llvm::PostGenericScheduler::initialize(), llvm::MachineSSAUpdater::MachineSSAUpdater(), llvm::ARMBaseRegisterInfo::materializeFrameBaseRegister(), MIsNeedChainEdge(), llvm::MachineInstr::print(), reassociateOps(), llvm::MachineRegisterInfo::recomputeRegClass(), replaceFI(), llvm::ARMBaseRegisterInfo::resolveFrameIndex(), llvm::ResourcePriorityQueue::ResourcePriorityQueue(), llvm::SystemZFrameLowering::restoreCalleeSavedRegisters(), llvm::XCoreFrameLowering::restoreCalleeSavedRegisters(), llvm::MSP430FrameLowering::restoreCalleeSavedRegisters(), llvm::AArch64FrameLowering::restoreCalleeSavedRegisters(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::MachineTraceMetrics::runOnMachineFunction(), llvm::LiveIntervals::runOnMachineFunction(), llvm::Mips16RegisterInfo::saveScavengerRegister(), llvm::FunctionLoweringInfo::set(), setCallTargetReg(), llvm::SystemZFrameLowering::spillCalleeSavedRegisters(), llvm::XCoreFrameLowering::spillCalleeSavedRegisters(), llvm::MSP430FrameLowering::spillCalleeSavedRegisters(), llvm::AArch64FrameLowering::spillCalleeSavedRegisters(), llvm::MachineBasicBlock::SplitCriticalEdge(), UpdateOperandRegClass(), llvm::MachineBasicBlock::updateTerminator(), llvm::VLIWPacketizerList::VLIWPacketizerList(), and llvm::VLIWResourceModel::VLIWResourceModel().
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getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget.
Definition at line 94 of file TargetSubtargetInfo.h.
Referenced by llvm::R600InstrInfo::CreateTargetScheduleState(), and llvm::HexagonInstrInfo::CreateTargetScheduleState().
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Definition at line 161 of file TargetSubtargetInfo.h.
References llvm::CodeGenOpt::Default.
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getRegisterInfo - If register information is available, return it.
If not, return null. This is kept separate from RegInfo until RegInfo has details of graph coloring register allocation removed from it.
Definition at line 89 of file TargetSubtargetInfo.h.
Referenced by addLiveInRegs(), addSavedGPR(), llvm::A57ChainingConstraint::apply(), llvm::DwarfDebug::beginFunction(), llvm::LiveRangeEdit::calculateRegClassAndHint(), llvm::VirtRegAuxInfo::calculateSpillWeightAndHint(), checkNumAlignedDPRCS2Regs(), llvm::TargetSchedModel::computeOutputLatency(), llvm::createBURRListDAGScheduler(), llvm::createHybridListDAGScheduler(), llvm::createILPListDAGScheduler(), llvm::createSourceListDAGScheduler(), llvm::SystemZFrameLowering::determineCalleeSaves(), llvm::ARMFrameLowering::determineCalleeSaves(), llvm::AArch64FrameLowering::determineCalleeSaves(), llvm::TargetFrameLowering::determineCalleeSaves(), emitDebugLocValue(), llvm::AsmPrinter::EmitDwarfRegOp(), llvm::ARMFrameLowering::emitEpilogue(), llvm::AArch64FrameLowering::emitEpilogue(), llvm::MipsAsmPrinter::emitFrameDirective(), llvm::AMDGPUAsmPrinter::EmitInstruction(), llvm::XCoreFrameLowering::emitPrologue(), llvm::AArch64FrameLowering::emitPrologue(), llvm::RegScavenger::enterBasicBlock(), llvm::MachineFrameInfo::estimateStackSize(), llvm::DebugLocEntry::finalize(), llvm::finalizeBundle(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::TargetFrameLowering::getFrameIndexReference(), getMemcpyLoadsAndStores(), llvm::MachineFrameInfo::getPristineRegs(), GetRegistersForValue(), llvm::TargetInstrInfo::getStackSlotRange(), llvm::MachineRegisterInfo::getTargetRegisterInfo(), HandleVRSaveUpdate(), llvm::ARMFrameLowering::hasFP(), llvm::AArch64FrameLowering::hasFP(), llvm::RegPressureTracker::init(), initReachingDef(), llvm::TargetInstrInfo::isSchedulingBoundary(), llvm::MachineFunction::MachineFunction(), llvm::MachineFunction::print(), llvm::MachineBasicBlock::print(), llvm::MachineInstr::print(), llvm::ARMAsmPrinter::PrintAsmOperand(), llvm::ARMAsmPrinter::printOperand(), llvm::MipsAsmPrinter::printSavedRegsBitmask(), reassociateOps(), llvm::AArch64FrameLowering::resolveFrameIndexReference(), llvm::ARMFrameLowering::ResolveFrameIndexReference(), llvm::ResourcePriorityQueue::ResourcePriorityQueue(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::MachineTraceMetrics::runOnMachineFunction(), llvm::RegisterClassInfo::runOnMachineFunction(), llvm::LiveStacks::runOnMachineFunction(), llvm::LiveVariables::runOnMachineFunction(), llvm::LiveIntervals::runOnMachineFunction(), llvm::FunctionLoweringInfo::set(), setAliasRegs(), llvm::X86MachineFunctionInfo::setRestoreBasePointer(), llvm::MachineBasicBlock::SplitCriticalEdge(), UpdateOperandRegClass(), and llvm::DwarfCompileUnit::updateSubprogramScopeDIE().
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Definition at line 81 of file TargetSubtargetInfo.h.
Referenced by llvm::SelectionDAG::init().
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Definition at line 80 of file TargetSubtargetInfo.h.
Referenced by accumulateAndSortLibcalls(), llvm::CCState::analyzeMustTailForwardedRegisters(), llvm::FunctionLoweringInfo::CreateReg(), llvm::FunctionLoweringInfo::CreateRegs(), llvm::XCoreFrameLowering::emitEpilogue(), llvm::AsmPrinter::EmitJumpTableInfo(), llvm::XCoreFrameLowering::emitPrologue(), llvm::XCoreSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::CCState::HandleByVal(), llvm::SelectionDAG::init(), llvm::GenericScheduler::initPolicy(), llvm::isInTailCallPosition(), llvm::TargetInstrInfo::isSchedulingBoundary(), llvm::MachineFunction::MachineFunction(), llvm::StackProtector::runOnFunction(), llvm::SelectionDAGISel::runOnMachineFunction(), and llvm::FunctionLoweringInfo::set().
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Override generic scheduling policy within a region.
This is a convenient way for targets that don't provide any custom scheduling heuristics (no custom MachineSchedStrategy) to make changes to the generic scheduling policy.
Definition at line 140 of file TargetSubtargetInfo.h.
Referenced by llvm::GenericScheduler::initPolicy().
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Resolve a SchedClass at runtime, where SchedClass identifies an MCSchedClassDesc with the isVariant property.
This may return the ID of another variant SchedClass, but repeated invocation must quickly terminate in a nonvariant SchedClass.
Definition at line 102 of file TargetSubtargetInfo.h.
Referenced by llvm::TargetSchedModel::resolveSchedClass().
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Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.).
Definition at line 54 of file TargetSubtargetInfo.cpp.
Referenced by llvm::ScheduleDAGInstrs::buildSchedGraph().
1.8.6