29 #define DEBUG_TYPE "mccodeemitter"
31 STATISTIC(MCNumEmitted,
"Number of MC instructions emitted.");
32 STATISTIC(MCNumFixups,
"Number of MC fixups created.");
39 AArch64MCCodeEmitter(
const AArch64MCCodeEmitter &);
40 void operator=(
const AArch64MCCodeEmitter &);
44 ~AArch64MCCodeEmitter()
override {}
48 uint64_t getBinaryCodeForInstr(
const MCInst &
MI,
61 template <u
int32_t FixupKind>
62 uint32_t getLdStUImm12OpValue(
const MCInst &
MI,
unsigned OpIdx,
68 uint32_t getAdrLabelOpValue(
const MCInst &
MI,
unsigned OpIdx,
74 uint32_t getAddSubImmOpValue(
const MCInst &
MI,
unsigned OpIdx,
80 uint32_t getCondBranchTargetOpValue(
const MCInst &
MI,
unsigned OpIdx,
86 uint32_t getLoadLiteralOpValue(
const MCInst &
MI,
unsigned OpIdx,
93 uint32_t getMemExtendOpValue(
const MCInst &
MI,
unsigned OpIdx,
99 uint32_t getTestBranchTargetOpValue(
const MCInst &
MI,
unsigned OpIdx,
111 uint32_t getMoveWideImmOpValue(
const MCInst &
MI,
unsigned OpIdx,
116 uint32_t getVecShifterOpValue(
const MCInst &
MI,
unsigned OpIdx,
122 uint32_t getMoveVecShifterOpValue(
const MCInst &
MI,
unsigned OpIdx,
128 uint32_t getFixedPointScaleOpValue(
const MCInst &
MI,
unsigned OpIdx,
132 uint32_t getVecShiftR64OpValue(
const MCInst &
MI,
unsigned OpIdx,
135 uint32_t getVecShiftR32OpValue(
const MCInst &
MI,
unsigned OpIdx,
138 uint32_t getVecShiftR16OpValue(
const MCInst &
MI,
unsigned OpIdx,
141 uint32_t getVecShiftR8OpValue(
const MCInst &
MI,
unsigned OpIdx,
144 uint32_t getVecShiftL64OpValue(
const MCInst &
MI,
unsigned OpIdx,
147 uint32_t getVecShiftL32OpValue(
const MCInst &
MI,
unsigned OpIdx,
150 uint32_t getVecShiftL16OpValue(
const MCInst &
MI,
unsigned OpIdx,
153 uint32_t getVecShiftL8OpValue(
const MCInst &
MI,
unsigned OpIdx,
159 uint32_t getSIMDShift64OpValue(
const MCInst &
MI,
unsigned OpIdx,
163 uint32_t getSIMDShift64_32OpValue(
const MCInst &
MI,
unsigned OpIdx,
167 uint32_t getSIMDShift32OpValue(
const MCInst &
MI,
unsigned OpIdx,
171 uint32_t getSIMDShift16OpValue(
const MCInst &
MI,
unsigned OpIdx,
175 unsigned fixMOVZ(
const MCInst &
MI,
unsigned EncodedValue,
182 unsigned fixMulHigh(
const MCInst &
MI,
unsigned EncodedValue,
185 template<
int hasRs,
int hasRt2>
unsigned
186 fixLoadStoreExclusive(
const MCInst &
MI,
unsigned EncodedValue,
189 unsigned fixOneOperandFPComparison(
const MCInst &
MI,
unsigned EncodedValue,
198 return new AArch64MCCodeEmitter(MCII, Ctx);
208 return Ctx.getRegisterInfo()->getEncodingValue(MO.
getReg());
210 assert(MO.
isImm() &&
"did not expect relocated expression");
211 return static_cast<unsigned>(MO.
getImm());
214 template<
unsigned FixupKind> uint32_t
215 AArch64MCCodeEmitter::getLdStUImm12OpValue(
const MCInst &MI,
unsigned OpIdx,
222 ImmVal = static_cast<uint32_t>(MO.
getImm());
224 assert(MO.
isExpr() &&
"unable to encode load/store imm operand");
236 AArch64MCCodeEmitter::getAdrLabelOpValue(
const MCInst &MI,
unsigned OpIdx,
244 assert(MO.
isExpr() &&
"Unexpected target type!");
262 AArch64MCCodeEmitter::getAddSubImmOpValue(
const MCInst &MI,
unsigned OpIdx,
269 "unexpected shift type for add/sub immediate");
271 assert((ShiftVal == 0 || ShiftVal == 12) &&
272 "unexpected shift value for add/sub immediate");
274 return MO.
getImm() | (ShiftVal == 0 ? 0 : (1 << 12));
275 assert(MO.
isExpr() &&
"Unable to encode MCOperand!");
289 uint32_t AArch64MCCodeEmitter::getCondBranchTargetOpValue(
297 assert(MO.
isExpr() &&
"Unexpected target type!");
311 AArch64MCCodeEmitter::getLoadLiteralOpValue(
const MCInst &MI,
unsigned OpIdx,
319 assert(MO.
isExpr() &&
"Unexpected target type!");
331 AArch64MCCodeEmitter::getMemExtendOpValue(
const MCInst &MI,
unsigned OpIdx,
336 return (SignExtend << 1) | DoShift;
340 AArch64MCCodeEmitter::getMoveWideImmOpValue(
const MCInst &MI,
unsigned OpIdx,
347 assert(MO.
isExpr() &&
"Unexpected movz/movk immediate");
359 uint32_t AArch64MCCodeEmitter::getTestBranchTargetOpValue(
367 assert(MO.
isExpr() &&
"Unexpected ADR target type!");
389 assert(MO.
isExpr() &&
"Unexpected ADR target type!");
391 MCFixupKind Kind = MI.
getOpcode() == AArch64::BL
409 AArch64MCCodeEmitter::getVecShifterOpValue(
const MCInst &MI,
unsigned OpIdx,
413 assert(MO.
isImm() &&
"Expected an immediate value for the shift amount!");
432 AArch64MCCodeEmitter::getSIMDShift64OpValue(
const MCInst &MI,
unsigned OpIdx,
436 assert(MO.
isImm() &&
"Expected an immediate value for the shift amount!");
437 return 64 - (MO.
getImm());
440 uint32_t AArch64MCCodeEmitter::getSIMDShift64_32OpValue(
444 assert(MO.
isImm() &&
"Expected an immediate value for the shift amount!");
445 return 64 - (MO.
getImm() | 32);
449 AArch64MCCodeEmitter::getSIMDShift32OpValue(
const MCInst &MI,
unsigned OpIdx,
453 assert(MO.
isImm() &&
"Expected an immediate value for the shift amount!");
454 return 32 - (MO.
getImm() | 16);
458 AArch64MCCodeEmitter::getSIMDShift16OpValue(
const MCInst &MI,
unsigned OpIdx,
462 assert(MO.
isImm() &&
"Expected an immediate value for the shift amount!");
463 return 16 - (MO.
getImm() | 8);
468 uint32_t AArch64MCCodeEmitter::getFixedPointScaleOpValue(
472 assert(MO.
isImm() &&
"Expected an immediate value for the scale amount!");
477 AArch64MCCodeEmitter::getVecShiftR64OpValue(
const MCInst &MI,
unsigned OpIdx,
481 assert(MO.
isImm() &&
"Expected an immediate value for the scale amount!");
486 AArch64MCCodeEmitter::getVecShiftR32OpValue(
const MCInst &MI,
unsigned OpIdx,
490 assert(MO.
isImm() &&
"Expected an immediate value for the scale amount!");
495 AArch64MCCodeEmitter::getVecShiftR16OpValue(
const MCInst &MI,
unsigned OpIdx,
499 assert(MO.
isImm() &&
"Expected an immediate value for the scale amount!");
504 AArch64MCCodeEmitter::getVecShiftR8OpValue(
const MCInst &MI,
unsigned OpIdx,
508 assert(MO.
isImm() &&
"Expected an immediate value for the scale amount!");
513 AArch64MCCodeEmitter::getVecShiftL64OpValue(
const MCInst &MI,
unsigned OpIdx,
517 assert(MO.
isImm() &&
"Expected an immediate value for the scale amount!");
522 AArch64MCCodeEmitter::getVecShiftL32OpValue(
const MCInst &MI,
unsigned OpIdx,
526 assert(MO.
isImm() &&
"Expected an immediate value for the scale amount!");
531 AArch64MCCodeEmitter::getVecShiftL16OpValue(
const MCInst &MI,
unsigned OpIdx,
535 assert(MO.
isImm() &&
"Expected an immediate value for the scale amount!");
540 AArch64MCCodeEmitter::getVecShiftL8OpValue(
const MCInst &MI,
unsigned OpIdx,
544 assert(MO.
isImm() &&
"Expected an immediate value for the scale amount!");
550 uint32_t AArch64MCCodeEmitter::getMoveVecShifterOpValue(
555 "Expected an immediate value for the move shift amount!");
557 assert((ShiftVal == 8 || ShiftVal == 16) &&
"Invalid shift amount!");
558 return ShiftVal == 8 ? 0 : 1;
561 unsigned AArch64MCCodeEmitter::fixMOVZ(
const MCInst &MI,
unsigned EncodedValue,
570 if (UImm16MO.
isImm())
582 return EncodedValue & ~(1u << 30);
589 return EncodedValue & ~(1u << 30);
595 if (MI.
getOpcode() == AArch64::TLSDESCCALL) {
604 uint64_t
Binary = getBinaryCodeForInstr(MI, Fixups, STI);
610 AArch64MCCodeEmitter::fixMulHigh(
const MCInst &MI,
611 unsigned EncodedValue,
615 EncodedValue |= 0x1f << 10;
619 template<
int hasRs,
int hasRt2>
unsigned
620 AArch64MCCodeEmitter::fixLoadStoreExclusive(
const MCInst &MI,
621 unsigned EncodedValue,
623 if (!hasRs) EncodedValue |= 0x001F0000;
624 if (!hasRt2) EncodedValue |= 0x00007C00;
629 unsigned AArch64MCCodeEmitter::fixOneOperandFPComparison(
633 EncodedValue &= ~(0x1f << 16);
637 #include "AArch64GenMCCodeEmitter.inc"
void push_back(const T &Elt)
STATISTIC(NumFunctions,"Total number of functions")
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Base class for the full range of assembler expressions which are needed for parsing.
VariantKind getKind() const
Get the kind of this expression.
Context object for machine code objects.
unsigned getReg() const
Returns the register number.
Instances of this class represent a single low-level machine instruction.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
static unsigned getShiftValue(unsigned Imm)
getShiftValue - Extract the shift value.
const MCExpr * getExpr() const
MCCodeEmitter - Generic instruction encoding interface.
Interface to description of machine instruction set.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
PowerPC TLS Dynamic Call Fixup
MCCodeEmitter * createAArch64MCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
unsigned getOpcode() const
Adapter to write values to a stream in a particular byte order.
static AArch64_AM::ShiftExtendType getShiftType(unsigned Imm)
getShiftType - Extract the shift type.
MCSubtargetInfo - Generic base class for all target subtargets.
static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI)
getBranchTargetOpValue - Helper function to get the branch target operand, which is either an immedia...
const ARM::ArchExtKind Kind
This class implements an extremely fast bulk output stream that can only output to a stream...
Instances of this class represent operands of the MCInst class.
const MCOperand & getOperand(unsigned i) const