LLVM  3.7.0
XCoreInstrInfo.h
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1 //===-- XCoreInstrInfo.h - XCore Instruction Information --------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the XCore implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_XCORE_XCOREINSTRINFO_H
15 #define LLVM_LIB_TARGET_XCORE_XCOREINSTRINFO_H
16 
17 #include "XCoreRegisterInfo.h"
19 
20 #define GET_INSTRINFO_HEADER
21 #include "XCoreGenInstrInfo.inc"
22 
23 namespace llvm {
24 
26  const XCoreRegisterInfo RI;
27  virtual void anchor();
28 public:
30 
31  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
32  /// such, whenever a client has an instance of instruction info, it should
33  /// always be able to get register info as well (through this method).
34  ///
35  const TargetRegisterInfo &getRegisterInfo() const { return RI; }
36 
37  /// isLoadFromStackSlot - If the specified machine instruction is a direct
38  /// load from a stack slot, return the virtual or physical register number of
39  /// the destination along with the FrameIndex of the loaded stack slot. If
40  /// not, return 0. This predicate must return 0 if the instruction has
41  /// any side effects other than loading from the stack slot.
42  unsigned isLoadFromStackSlot(const MachineInstr *MI,
43  int &FrameIndex) const override;
44 
45  /// isStoreToStackSlot - If the specified machine instruction is a direct
46  /// store to a stack slot, return the virtual or physical register number of
47  /// the source reg along with the FrameIndex of the loaded stack slot. If
48  /// not, return 0. This predicate must return 0 if the instruction has
49  /// any side effects other than storing to the stack slot.
50  unsigned isStoreToStackSlot(const MachineInstr *MI,
51  int &FrameIndex) const override;
52 
54  MachineBasicBlock *&FBB,
56  bool AllowModify) const override;
57 
60  DebugLoc DL) const override;
61 
62  unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
63 
66  unsigned DestReg, unsigned SrcReg,
67  bool KillSrc) const override;
68 
71  unsigned SrcReg, bool isKill, int FrameIndex,
72  const TargetRegisterClass *RC,
73  const TargetRegisterInfo *TRI) const override;
74 
77  unsigned DestReg, int FrameIndex,
78  const TargetRegisterClass *RC,
79  const TargetRegisterInfo *TRI) const override;
80 
82  SmallVectorImpl<MachineOperand> &Cond) const override;
83 
84  // Emit code before MBBI to load immediate value into physical register Reg.
85  // Returns an iterator to the new instruction.
88  unsigned Reg, uint64_t Value) const;
89 };
90 
91 }
92 
93 #endif
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
unsigned RemoveBranch(MachineBasicBlock &MBB) const override
bool ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
ReverseBranchCondition - Return the inverse opcode of the specified Branch instruction.
unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const override
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot...
A debug info location.
Definition: DebugLoc.h:34
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APInt.h:33
Reg
All possible values of the reg field in the ModR/M byte.
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, DebugLoc DL) const override
bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
AnalyzeBranch - Analyze the branching code at the end of MBB, returning true if it cannot be understo...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: ArrayRef.h:31
bundle_iterator - MachineBasicBlock iterator that automatically skips over MIs that are inside bundle...
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
MachineBasicBlock::iterator loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Reg, uint64_t Value) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
const TargetRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot...
Representation of each machine instruction.
Definition: MachineInstr.h:51
#define I(x, y, z)
Definition: MD5.cpp:54
LLVM Value Representation.
Definition: Value.h:69