29 #define DEBUG_TYPE "mccodeemitter"
31 STATISTIC(MCNumEmitted,
"Number of MC instructions emitted");
35 SparcMCCodeEmitter(
const SparcMCCodeEmitter &) =
delete;
36 void operator=(
const SparcMCCodeEmitter &) =
delete;
40 SparcMCCodeEmitter(
MCContext &ctx): Ctx(ctx) {}
42 ~SparcMCCodeEmitter()
override {}
50 uint64_t getBinaryCodeForInstr(
const MCInst &
MI,
60 unsigned getCallTargetOpValue(
const MCInst &
MI,
unsigned OpNo,
66 unsigned getBranchPredTargetOpValue(
const MCInst &
MI,
unsigned OpNo,
69 unsigned getBranchOnRegTargetOpValue(
const MCInst &
MI,
unsigned OpNo,
79 return new SparcMCCodeEmitter(Ctx);
85 unsigned Bits = getBinaryCodeForInstr(MI, Fixups, STI);
87 if (Ctx.getAsmInfo()->isLittleEndian()) {
101 case SP::TLS_LDXrr: tlsOpNo = 3;
break;
105 uint64_t
op = getMachineOpValue(MI, MO, Fixups, STI);
106 assert(op == 0 &&
"Unexpected operand value!");
114 unsigned SparcMCCodeEmitter::
120 return Ctx.getRegisterInfo()->getEncodingValue(MO.
getReg());
127 if (
const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(Expr)) {
134 if (Expr->evaluateAsAbsolute(Res))
141 unsigned SparcMCCodeEmitter::
142 getCallTargetOpValue(
const MCInst &MI,
unsigned OpNo,
147 return getMachineOpValue(MI, MO, Fixups, STI);
156 "Unexpected expression in TLS_CALL");
158 assert(SymExpr->getSymbol().getName() ==
"__tls_get_addr" &&
159 "Unexpected function for TLS_CALL");
182 return getMachineOpValue(MI, MO, Fixups, STI);
189 unsigned SparcMCCodeEmitter::
190 getBranchPredTargetOpValue(
const MCInst &MI,
unsigned OpNo,
195 return getMachineOpValue(MI, MO, Fixups, STI);
201 unsigned SparcMCCodeEmitter::
202 getBranchOnRegTargetOpValue(
const MCInst &MI,
unsigned OpNo,
207 return getMachineOpValue(MI, MO, Fixups, STI);
219 #include "SparcGenMCCodeEmitter.inc"
void push_back(const T &Elt)
MCCodeEmitter * createSparcMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
STATISTIC(NumFunctions,"Total number of functions")
const MCExpr * getSubExpr() const
getSubExpr - Get the child of this expression.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Base class for the full range of assembler expressions which are needed for parsing.
Represent a reference to a symbol from inside an expression.
Context object for machine code objects.
unsigned getReg() const
Returns the register number.
Instances of this class represent a single low-level machine instruction.
fixup_sparc_br19 - 19-bit PC relative relocation for branches on icc/xcc
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
const MCExpr * getExpr() const
MCCodeEmitter - Generic instruction encoding interface.
Interface to description of machine instruction set.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
VariantKind getKind() const
getOpcode - Get the kind of this expression.
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
fixup_sparc_bpr - 16-bit fixup for bpr
unsigned getOpcode() const
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Adapter to write values to a stream in a particular byte order.
MCSubtargetInfo - Generic base class for all target subtargets.
References to labels and assigned expressions.
static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI)
getBranchTargetOpValue - Helper function to get the branch target operand, which is either an immedia...
fixup_sparc_br22 - 22-bit PC relative relocation for branches
const ARM::ArchExtKind Kind
This class implements an extremely fast bulk output stream that can only output to a stream...
Instances of this class represent operands of the MCInst class.
const MCOperand & getOperand(unsigned i) const