44 #define GET_REGINFO_TARGET_DESC
45 #include "X86GenRegisterInfo.inc"
49 cl::desc(
"Force align the stack to the minimum alignment"
50 " needed for the function."),
55 cl::desc(
"Enable use of a base pointer for complex stack frames"));
61 (TT.isArch64Bit() ? X86::RIP : X86::EIP)) {
77 StackPtr = Use64BitReg ? X86::RSP : X86::ESP;
78 FramePtr = Use64BitReg ? X86::RBP : X86::EBP;
79 BasePtr = Use64BitReg ? X86::RBX : X86::EBX;
96 return getEncodingValue(i);
101 unsigned Idx)
const {
104 if (!Is64Bit && Idx == X86::sub_8bit)
105 Idx = X86::sub_8bit_hi;
108 return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
114 unsigned SubIdx)
const {
116 if (!Is64Bit && SubIdx == X86::sub_8bit) {
117 A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
121 return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
135 if (RC == &X86::GR8_NOREXRegClass)
141 switch (Super->
getID()) {
142 case X86::GR8RegClassID:
143 case X86::GR16RegClassID:
144 case X86::GR32RegClassID:
145 case X86::GR64RegClassID:
146 case X86::FR32RegClassID:
147 case X86::FR64RegClassID:
148 case X86::RFP32RegClassID:
149 case X86::RFP64RegClassID:
150 case X86::RFP80RegClassID:
151 case X86::VR128RegClassID:
152 case X86::VR256RegClassID:
165 unsigned Kind)
const {
171 return &X86::GR64RegClass;
172 return &X86::GR32RegClass;
175 return &X86::GR64_NOSPRegClass;
176 return &X86::GR32_NOSPRegClass;
180 return &X86::GR64_TCW64RegClass;
182 return &X86::GR64_TCRegClass;
186 return &X86::GR32RegClass;
187 return &X86::GR32_TCRegClass;
193 if (RC == &X86::CCRRegClass) {
195 return &X86::GR64RegClass;
197 return &X86::GR32RegClass;
207 unsigned FPDiff = TFI->
hasFP(MF) ? 1 : 0;
208 switch (RC->
getID()) {
211 case X86::GR32RegClassID:
213 case X86::GR64RegClassID:
215 case X86::VR128RegClassID:
216 return Is64Bit ? 10 : 4;
217 case X86::VR64RegClassID:
225 bool HasAVX = Subtarget.
hasAVX();
229 assert(MF &&
"MachineFunction required");
233 return CSR_NoRegs_SaveList;
236 return CSR_64_AllRegs_AVX_SaveList;
237 return CSR_64_AllRegs_SaveList;
239 return CSR_64_RT_MostRegs_SaveList;
242 return CSR_64_RT_AllRegs_AVX_SaveList;
243 return CSR_64_RT_AllRegs_SaveList;
245 if (HasAVX512 && IsWin64)
246 return CSR_Win64_Intel_OCL_BI_AVX512_SaveList;
247 if (HasAVX512 && Is64Bit)
248 return CSR_64_Intel_OCL_BI_AVX512_SaveList;
249 if (HasAVX && IsWin64)
250 return CSR_Win64_Intel_OCL_BI_AVX_SaveList;
251 if (HasAVX && Is64Bit)
252 return CSR_64_Intel_OCL_BI_AVX_SaveList;
253 if (!HasAVX && !IsWin64 && Is64Bit)
254 return CSR_64_Intel_OCL_BI_SaveList;
259 return CSR_64_MostRegs_SaveList;
262 return CSR_Win64_SaveList;
265 return CSR_64EHRet_SaveList;
266 return CSR_64_SaveList;
273 return CSR_Win64_SaveList;
275 return CSR_64EHRet_SaveList;
276 return CSR_64_SaveList;
279 return CSR_32EHRet_SaveList;
280 return CSR_32_SaveList;
287 bool HasAVX = Subtarget.
hasAVX();
293 return CSR_NoRegs_RegMask;
296 return CSR_64_AllRegs_AVX_RegMask;
297 return CSR_64_AllRegs_RegMask;
299 return CSR_64_RT_MostRegs_RegMask;
302 return CSR_64_RT_AllRegs_AVX_RegMask;
303 return CSR_64_RT_AllRegs_RegMask;
305 if (HasAVX512 && IsWin64)
306 return CSR_Win64_Intel_OCL_BI_AVX512_RegMask;
307 if (HasAVX512 && Is64Bit)
308 return CSR_64_Intel_OCL_BI_AVX512_RegMask;
309 if (HasAVX && IsWin64)
310 return CSR_Win64_Intel_OCL_BI_AVX_RegMask;
311 if (HasAVX && Is64Bit)
312 return CSR_64_Intel_OCL_BI_AVX_RegMask;
313 if (!HasAVX && !IsWin64 && Is64Bit)
314 return CSR_64_Intel_OCL_BI_RegMask;
319 return CSR_64_MostRegs_RegMask;
324 return CSR_Win64_RegMask;
326 return CSR_64_RegMask;
333 return CSR_Win64_RegMask;
334 return CSR_64_RegMask;
336 return CSR_32_RegMask;
341 return CSR_NoRegs_RegMask;
359 if (TFI->
hasFP(MF)) {
371 "Stack realignment in presence of dynamic allocas is not supported with"
372 "this calling convention.");
382 Reserved.
set(X86::CS);
383 Reserved.
set(X86::SS);
384 Reserved.
set(X86::DS);
385 Reserved.
set(X86::ES);
386 Reserved.
set(X86::FS);
387 Reserved.
set(X86::GS);
390 for (
unsigned n = 0; n != 8; ++n)
391 Reserved.
set(X86::ST0 + n);
397 Reserved.
set(X86::SIL);
398 Reserved.
set(X86::DIL);
399 Reserved.
set(X86::BPL);
400 Reserved.
set(X86::SPL);
402 for (
unsigned n = 0; n != 8; ++n) {
413 for (
unsigned n = 16; n != 32; ++n) {
430 assert(!(Mask[X86::EFLAGS / 32] & (1U << (X86::EFLAGS % 32))) &&
431 "EFLAGS are not live-out from a patchpoint.");
434 for (
auto Reg : {X86::EFLAGS, X86::RIP, X86::EIP, X86::IP})
435 Mask[
Reg / 32] &= ~(1U << (
Reg % 32));
456 return CantUseFP && CantUseSP;
494 unsigned Reg,
int &FrameIdx)
const {
502 int SPAdj,
unsigned FIOperandNum,
511 bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm ||
512 Opc == X86::TCRETURNmi || Opc == X86::TCRETURNmi64;
516 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
520 BasePtr = (TFI->
hasFP(MF) ? FramePtr : StackPtr);
542 if (Opc == X86::LEA64_32r && X86::GR32RegClass.
contains(BasePtr))
558 if (BasePtr == StackPtr)
564 assert(BasePtr == FramePtr &&
"Expected the FP as base register");
573 int Offset = FIOffset + Imm;
574 assert((!Is64Bit ||
isInt<32>((
long long)FIOffset + Imm)) &&
575 "Requesting 64-bit offset in 32-bit immediate!");
579 uint64_t Offset = FIOffset +
587 return TFI->
hasFP(MF) ? FramePtr : StackPtr;
608 case X86::SIL:
case X86::SI:
case X86::ESI:
case X86::RSI:
610 case X86::DIL:
case X86::DI:
case X86::EDI:
case X86::RDI:
612 case X86::BPL:
case X86::BP:
case X86::EBP:
case X86::RBP:
614 case X86::SPL:
case X86::SP:
case X86::ESP:
case X86::RSP:
616 case X86::AH:
case X86::AL:
case X86::AX:
case X86::EAX:
case X86::RAX:
618 case X86::DH:
case X86::DL:
case X86::DX:
case X86::EDX:
case X86::RDX:
620 case X86::CH:
case X86::CL:
case X86::CX:
case X86::ECX:
case X86::RCX:
622 case X86::BH:
case X86::BL:
case X86::BX:
case X86::EBX:
case X86::RBX:
628 case X86::AH:
case X86::AL:
case X86::AX:
case X86::EAX:
case X86::RAX:
630 case X86::DH:
case X86::DL:
case X86::DX:
case X86::EDX:
case X86::RDX:
632 case X86::CH:
case X86::CL:
case X86::CX:
case X86::ECX:
case X86::RCX:
634 case X86::BH:
case X86::BL:
case X86::BX:
case X86::EBX:
case X86::RBX:
636 case X86::SIL:
case X86::SI:
case X86::ESI:
case X86::RSI:
638 case X86::DIL:
case X86::DI:
case X86::EDI:
case X86::RDI:
640 case X86::BPL:
case X86::BP:
case X86::EBP:
case X86::RBP:
642 case X86::SPL:
case X86::SP:
case X86::ESP:
case X86::RSP:
644 case X86::R8B:
case X86::R8W:
case X86::R8D:
case X86::R8:
646 case X86::R9B:
case X86::R9W:
case X86::R9D:
case X86::R9:
648 case X86::R10B:
case X86::R10W:
case X86::R10D:
case X86::R10:
650 case X86::R11B:
case X86::R11W:
case X86::R11D:
case X86::R11:
652 case X86::R12B:
case X86::R12W:
case X86::R12D:
case X86::R12:
654 case X86::R13B:
case X86::R13W:
case X86::R13D:
case X86::R13:
656 case X86::R14B:
case X86::R14W:
case X86::R14D:
case X86::R14:
658 case X86::R15B:
case X86::R15W:
case X86::R15D:
case X86::R15:
665 case X86::AH:
case X86::AL:
case X86::AX:
case X86::EAX:
case X86::RAX:
667 case X86::DH:
case X86::DL:
case X86::DX:
case X86::EDX:
case X86::RDX:
669 case X86::CH:
case X86::CL:
case X86::CX:
case X86::ECX:
case X86::RCX:
671 case X86::BH:
case X86::BL:
case X86::BX:
case X86::EBX:
case X86::RBX:
673 case X86::SIL:
case X86::SI:
case X86::ESI:
case X86::RSI:
675 case X86::DIL:
case X86::DI:
case X86::EDI:
case X86::RDI:
677 case X86::BPL:
case X86::BP:
case X86::EBP:
case X86::RBP:
679 case X86::SPL:
case X86::SP:
case X86::ESP:
case X86::RSP:
681 case X86::R8B:
case X86::R8W:
case X86::R8D:
case X86::R8:
683 case X86::R9B:
case X86::R9W:
case X86::R9D:
case X86::R9:
685 case X86::R10B:
case X86::R10W:
case X86::R10D:
case X86::R10:
687 case X86::R11B:
case X86::R11W:
case X86::R11D:
case X86::R11:
689 case X86::R12B:
case X86::R12W:
case X86::R12D:
case X86::R12:
691 case X86::R13B:
case X86::R13W:
case X86::R13D:
case X86::R13:
693 case X86::R14B:
case X86::R14W:
case X86::R14D:
case X86::R14:
695 case X86::R15B:
case X86::R15W:
case X86::R15D:
case X86::R15:
701 case X86::AH:
case X86::AL:
case X86::AX:
case X86::EAX:
case X86::RAX:
703 case X86::DH:
case X86::DL:
case X86::DX:
case X86::EDX:
case X86::RDX:
705 case X86::CH:
case X86::CL:
case X86::CX:
case X86::ECX:
case X86::RCX:
707 case X86::BH:
case X86::BL:
case X86::BX:
case X86::EBX:
case X86::RBX:
709 case X86::SIL:
case X86::SI:
case X86::ESI:
case X86::RSI:
711 case X86::DIL:
case X86::DI:
case X86::EDI:
case X86::RDI:
713 case X86::BPL:
case X86::BP:
case X86::EBP:
case X86::RBP:
715 case X86::SPL:
case X86::SP:
case X86::ESP:
case X86::RSP:
717 case X86::R8B:
case X86::R8W:
case X86::R8D:
case X86::R8:
719 case X86::R9B:
case X86::R9W:
case X86::R9D:
case X86::R9:
721 case X86::R10B:
case X86::R10W:
case X86::R10D:
case X86::R10:
723 case X86::R11B:
case X86::R11W:
case X86::R11D:
case X86::R11:
725 case X86::R12B:
case X86::R12W:
case X86::R12D:
case X86::R12:
727 case X86::R13B:
case X86::R13W:
case X86::R13D:
case X86::R13:
729 case X86::R14B:
case X86::R14W:
case X86::R14D:
case X86::R14:
731 case X86::R15B:
case X86::R15W:
case X86::R15D:
case X86::R15:
737 case X86::AH:
case X86::AL:
case X86::AX:
case X86::EAX:
case X86::RAX:
739 case X86::DH:
case X86::DL:
case X86::DX:
case X86::EDX:
case X86::RDX:
741 case X86::CH:
case X86::CL:
case X86::CX:
case X86::ECX:
case X86::RCX:
743 case X86::BH:
case X86::BL:
case X86::BX:
case X86::EBX:
case X86::RBX:
745 case X86::SIL:
case X86::SI:
case X86::ESI:
case X86::RSI:
747 case X86::DIL:
case X86::DI:
case X86::EDI:
case X86::RDI:
749 case X86::BPL:
case X86::BP:
case X86::EBP:
case X86::RBP:
751 case X86::SPL:
case X86::SP:
case X86::ESP:
case X86::RSP:
753 case X86::R8B:
case X86::R8W:
case X86::R8D:
case X86::R8:
755 case X86::R9B:
case X86::R9W:
case X86::R9D:
case X86::R9:
757 case X86::R10B:
case X86::R10W:
case X86::R10D:
case X86::R10:
759 case X86::R11B:
case X86::R11W:
case X86::R11D:
case X86::R11:
761 case X86::R12B:
case X86::R12W:
case X86::R12D:
case X86::R12:
763 case X86::R13B:
case X86::R13W:
case X86::R13D:
case X86::R13:
765 case X86::R14B:
case X86::R14W:
case X86::R14D:
case X86::R14:
767 case X86::R15B:
case X86::R15W:
case X86::R15D:
case X86::R15:
782 if (Reg >= X86::XMM0 && Reg <= X86::XMM31)
783 return X86::ZMM0 + (Reg - X86::XMM0);
784 if (Reg >= X86::YMM0 && Reg <= X86::YMM31)
785 return X86::ZMM0 + (Reg - X86::YMM0);
786 if (Reg >= X86::ZMM0 && Reg <= X86::ZMM31)
bool isInt< 32 >(int64_t x)
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const override
getMatchingSuperRegClass - Return a subclass of the specified register class A so that each register ...
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
Intel_OCL_BI - Calling conventions for Intel OpenCL built-ins.
The C convention as specified in the x86-64 supplement to the System V ABI, used on most non-Windows ...
Alignment of stack for function (3 bits) stored as log2 of alignment with +1 bias 0 means unaligned (...
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
bool hasBasePointer(const MachineFunction &MF) const
A Stackmap instruction captures the location of live variables at its position in the instruction str...
unsigned getID() const
getID() - Return the register class ID number.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
unsigned getDwarfRegFlavour(const Triple &TT, bool isEH)
bool canReserveReg(unsigned PhysReg) const
canReserveReg - Returns true if PhysReg can be used as a reserved register.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag=true)
Reports a serious error, calling any installed error handler.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
bool isOSWindows() const
Tests whether the OS is Windows.
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
unsigned getSize() const
getSize - Return the size of the register in bytes, which is also the size of a stack slot allocated ...
X86RegisterInfo(const Triple &TT)
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
getPointerRegClass - Returns a TargetRegisterClass used for pointer values.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
bool isArch64Bit() const
Test whether the architecture is 64-bit.
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
bool canRealignStack(const MachineFunction &MF) const
static cl::opt< bool > EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true), cl::desc("Enable use of a base pointer for complex stack frames"))
BitVector getReservedRegs(const MachineFunction &MF) const override
getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a ...
unsigned getX86SubSuperRegister(unsigned Reg, MVT::SimpleValueType VT, bool High)
Returns the sub or super register of a specific X86 register.
void adjustStackMapLiveOutMask(uint32_t *Mask) const override
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
const MachineBasicBlock * getParent() const
bundle_iterator< MachineInstr, instr_iterator > iterator
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, int &FrameIdx) const override
Instruction that records the offset of a local stack allocation passed to llvm.localescape.
initializer< Ty > init(const Ty &Val)
Patchable call instruction - this instruction represents a call to a constant address, followed by a series of NOPs.
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override
Code Generation virtual methods...
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const MachineOperand & getOperand(unsigned i) const
unsigned get512BitSuperRegister(unsigned Reg)
MCRegAliasIterator enumerates all registers aliasing Reg.
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
unsigned getX86SubSuperRegisterOrZero(unsigned Reg, MVT::SimpleValueType VT, bool High)
Returns the sub or super register of a specific X86 register.
int64_t getOffset() const
Return the offset from the symbol in this operand.
void setOffset(int64_t Offset)
const TargetRegisterClass *const * sc_iterator
MCSubRegIterator enumerates all sub-registers of Reg.
unsigned getBaseRegister() const
Triple - Helper class for working with autoconf configuration names.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
bool callsEHReturn() const
void InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI)
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
bool isTarget64BitILP32() const
Is this x86_64 with the ILP32 programming model (x32 ABI)?
MachineOperand class - Representation of each machine instruction operand.
int getOffsetOfLocalArea() const
getOffsetOfLocalArea - This method returns the offset of the local area from the stack pointer on ent...
int getSEHRegNum(unsigned i) const
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
getCalleeSavedRegs - Return a null-terminated list of all of the callee-save registers on this target...
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
getCrossCopyRegClass - Returns a legal register class to copy a register in the specified class to or...
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
const uint32_t * getNoPreservedMask() const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool isTarget64BitLP64() const
Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
bool needsStackRealignment(const MachineFunction &MF) const override
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const override
int getFrameIndexOffsetFromSP(const MachineFunction &MF, int FI) const
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
cl::opt< bool > ForceStackAlign("force-align-stack", cl::desc("Force align the stack to the minimum alignment"" needed for the function."), cl::init(false), cl::Hidden)
EnvironmentType getEnvironment() const
getEnvironment - Get the parsed environment type of this triple.
const ARM::ArchExtKind Kind
The C convention as implemented on Windows/x86-64.
bool hasOpaqueSPAdjustment() const
Returns true if the function contains opaque dynamic stack adjustments.
MachineModuleInfo & getMMI() const
unsigned getFrameRegister(const MachineFunction &MF) const override
int getFrameIndexOffset(const MachineFunction &MF, int FI) const override
getFrameIndexOffset - Returns the displacement from the frame register to the stack frame of the spec...
sc_iterator getSuperClasses() const
getSuperClasses - Returns a NULL terminated list of super-classes.
unsigned getPtrSizedFrameRegister(const MachineFunction &MF) const
bool usesWindowsCFI() const