LLVM  3.7.0
llvm::MCInstrDesc Member List

This is the complete list of members for llvm::MCInstrDesc, including all inherited members.

canFoldAsLoad() const llvm::MCInstrDescinline
ComplexDeprecationInfollvm::MCInstrDesc
DeprecatedFeaturellvm::MCInstrDesc
findFirstPredOperandIdx() const llvm::MCInstrDescinline
Flagsllvm::MCInstrDesc
getDeprecatedInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info) const llvm::MCInstrDesc
getFlags() const llvm::MCInstrDescinline
getImplicitDefs() const llvm::MCInstrDescinline
getImplicitUses() const llvm::MCInstrDescinline
getNumDefs() const llvm::MCInstrDescinline
getNumImplicitDefs() const llvm::MCInstrDescinline
getNumImplicitUses() const llvm::MCInstrDescinline
getNumOperands() const llvm::MCInstrDescinline
getOpcode() const llvm::MCInstrDescinline
getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const llvm::MCInstrDescinline
getSchedClass() const llvm::MCInstrDescinline
getSize() const llvm::MCInstrDescinline
hasDelaySlot() const llvm::MCInstrDescinline
hasExtraDefRegAllocReq() const llvm::MCInstrDescinline
hasExtraSrcRegAllocReq() const llvm::MCInstrDescinline
hasImplicitDefOfPhysReg(unsigned Reg, const MCRegisterInfo *MRI=nullptr) const llvm::MCInstrDesc
hasImplicitUseOfPhysReg(unsigned Reg) const llvm::MCInstrDescinline
hasOptionalDef() const llvm::MCInstrDescinline
hasPostISelHook() const llvm::MCInstrDescinline
hasUnmodeledSideEffects() const llvm::MCInstrDescinline
ImplicitDefsllvm::MCInstrDesc
ImplicitUsesllvm::MCInstrDesc
isAsCheapAsAMove() const llvm::MCInstrDescinline
isBarrier() const llvm::MCInstrDescinline
isBitcast() const llvm::MCInstrDescinline
isBranch() const llvm::MCInstrDescinline
isCall() const llvm::MCInstrDescinline
isCommutable() const llvm::MCInstrDescinline
isCompare() const llvm::MCInstrDescinline
isConditionalBranch() const llvm::MCInstrDescinline
isConvergent() const llvm::MCInstrDescinline
isConvertibleTo3Addr() const llvm::MCInstrDescinline
isExtractSubregLike() const llvm::MCInstrDescinline
isIndirectBranch() const llvm::MCInstrDescinline
isInsertSubregLike() const llvm::MCInstrDescinline
isMoveImmediate() const llvm::MCInstrDescinline
isNotDuplicable() const llvm::MCInstrDescinline
isPredicable() const llvm::MCInstrDescinline
isPseudo() const llvm::MCInstrDescinline
isRegSequenceLike() const llvm::MCInstrDescinline
isRematerializable() const llvm::MCInstrDescinline
isReturn() const llvm::MCInstrDescinline
isSelect() const llvm::MCInstrDescinline
isTerminator() const llvm::MCInstrDescinline
isUnconditionalBranch() const llvm::MCInstrDescinline
isVariadic() const llvm::MCInstrDescinline
mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const llvm::MCInstrDesc
mayLoad() const llvm::MCInstrDescinline
mayStore() const llvm::MCInstrDescinline
NumDefsllvm::MCInstrDesc
NumOperandsllvm::MCInstrDesc
Opcodellvm::MCInstrDesc
OpInfollvm::MCInstrDesc
SchedClassllvm::MCInstrDesc
Sizellvm::MCInstrDesc
TSFlagsllvm::MCInstrDesc
usesCustomInsertionHook() const llvm::MCInstrDescinline