LLVM  3.7.0
HexagonExpandCondsets.cpp
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1 //===--- HexagonExpandCondsets.cpp ----------------------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 // Replace mux instructions with the corresponding legal instructions.
11 // It is meant to work post-SSA, but still on virtual registers. It was
12 // originally placed between register coalescing and machine instruction
13 // scheduler.
14 // In this place in the optimization sequence, live interval analysis had
15 // been performed, and the live intervals should be preserved. A large part
16 // of the code deals with preserving the liveness information.
17 //
18 // Liveness tracking aside, the main functionality of this pass is divided
19 // into two steps. The first step is to replace an instruction
20 // vreg0 = C2_mux vreg0, vreg1, vreg2
21 // with a pair of conditional transfers
22 // vreg0 = A2_tfrt vreg0, vreg1
23 // vreg0 = A2_tfrf vreg0, vreg2
24 // It is the intention that the execution of this pass could be terminated
25 // after this step, and the code generated would be functionally correct.
26 //
27 // If the uses of the source values vreg1 and vreg2 are kills, and their
28 // definitions are predicable, then in the second step, the conditional
29 // transfers will then be rewritten as predicated instructions. E.g.
30 // vreg0 = A2_or vreg1, vreg2
31 // vreg3 = A2_tfrt vreg99, vreg0<kill>
32 // will be rewritten as
33 // vreg3 = A2_port vreg99, vreg1, vreg2
34 //
35 // This replacement has two variants: "up" and "down". Consider this case:
36 // vreg0 = A2_or vreg1, vreg2
37 // ... [intervening instructions] ...
38 // vreg3 = A2_tfrt vreg99, vreg0<kill>
39 // variant "up":
40 // vreg3 = A2_port vreg99, vreg1, vreg2
41 // ... [intervening instructions, vreg0->vreg3] ...
42 // [deleted]
43 // variant "down":
44 // [deleted]
45 // ... [intervening instructions] ...
46 // vreg3 = A2_port vreg99, vreg1, vreg2
47 //
48 // Both, one or none of these variants may be valid, and checks are made
49 // to rule out inapplicable variants.
50 //
51 // As an additional optimization, before either of the two steps above is
52 // executed, the pass attempts to coalesce the target register with one of
53 // the source registers, e.g. given an instruction
54 // vreg3 = C2_mux vreg0, vreg1, vreg2
55 // vreg3 will be coalesced with either vreg1 or vreg2. If this succeeds,
56 // the instruction would then be (for example)
57 // vreg3 = C2_mux vreg0, vreg3, vreg2
58 // and, under certain circumstances, this could result in only one predicated
59 // instruction:
60 // vreg3 = A2_tfrf vreg0, vreg2
61 //
62 
63 #define DEBUG_TYPE "expand-condsets"
64 #include "HexagonTargetMachine.h"
65 
66 #include "llvm/CodeGen/Passes.h"
76 #include "llvm/Support/Debug.h"
78 
79 using namespace llvm;
80 
81 static cl::opt<unsigned> OptTfrLimit("expand-condsets-tfr-limit",
82  cl::init(~0U), cl::Hidden, cl::desc("Max number of mux expansions"));
83 static cl::opt<unsigned> OptCoaLimit("expand-condsets-coa-limit",
84  cl::init(~0U), cl::Hidden, cl::desc("Max number of segment coalescings"));
85 
86 namespace llvm {
89 }
90 
91 namespace {
92  class HexagonExpandCondsets : public MachineFunctionPass {
93  public:
94  static char ID;
95  HexagonExpandCondsets() :
96  MachineFunctionPass(ID), HII(0), TRI(0), MRI(0),
97  LIS(0), CoaLimitActive(false),
98  TfrLimitActive(false), CoaCounter(0), TfrCounter(0) {
99  if (OptCoaLimit.getPosition())
100  CoaLimitActive = true, CoaLimit = OptCoaLimit;
101  if (OptTfrLimit.getPosition())
102  TfrLimitActive = true, TfrLimit = OptTfrLimit;
104  }
105 
106  virtual const char *getPassName() const {
107  return "Hexagon Expand Condsets";
108  }
109  virtual void getAnalysisUsage(AnalysisUsage &AU) const {
114  }
115  virtual bool runOnMachineFunction(MachineFunction &MF);
116 
117  private:
118  const HexagonInstrInfo *HII;
119  const TargetRegisterInfo *TRI;
120  MachineRegisterInfo *MRI;
121  LiveIntervals *LIS;
122 
123  bool CoaLimitActive, TfrLimitActive;
124  unsigned CoaLimit, TfrLimit, CoaCounter, TfrCounter;
125 
126  struct RegisterRef {
127  RegisterRef(const MachineOperand &Op) : Reg(Op.getReg()),
128  Sub(Op.getSubReg()) {}
129  RegisterRef(unsigned R = 0, unsigned S = 0) : Reg(R), Sub(S) {}
130  bool operator== (RegisterRef RR) const {
131  return Reg == RR.Reg && Sub == RR.Sub;
132  }
133  bool operator!= (RegisterRef RR) const { return !operator==(RR); }
134  unsigned Reg, Sub;
135  };
136 
137  typedef DenseMap<unsigned,unsigned> ReferenceMap;
138  enum { Sub_Low = 0x1, Sub_High = 0x2, Sub_None = (Sub_Low | Sub_High) };
139  enum { Exec_Then = 0x10, Exec_Else = 0x20 };
140  unsigned getMaskForSub(unsigned Sub);
141  bool isCondset(const MachineInstr *MI);
142 
143  void addRefToMap(RegisterRef RR, ReferenceMap &Map, unsigned Exec);
144  bool isRefInMap(RegisterRef, ReferenceMap &Map, unsigned Exec);
145 
146  LiveInterval::iterator nextSegment(LiveInterval &LI, SlotIndex S);
147  LiveInterval::iterator prevSegment(LiveInterval &LI, SlotIndex S);
148  void makeDefined(unsigned Reg, SlotIndex S, bool SetDef);
149  void makeUndead(unsigned Reg, SlotIndex S);
150  void shrinkToUses(unsigned Reg, LiveInterval &LI);
151  void updateKillFlags(unsigned Reg, LiveInterval &LI);
152  void terminateSegment(LiveInterval::iterator LT, SlotIndex S,
153  LiveInterval &LI);
154  void addInstrToLiveness(MachineInstr *MI);
155  void removeInstrFromLiveness(MachineInstr *MI);
156 
157  unsigned getCondTfrOpcode(const MachineOperand &SO, bool Cond);
158  MachineInstr *genTfrFor(MachineOperand &SrcOp, unsigned DstR,
159  unsigned DstSR, const MachineOperand &PredOp, bool Cond);
160  bool split(MachineInstr *MI);
161  bool splitInBlock(MachineBasicBlock &B);
162 
163  bool isPredicable(MachineInstr *MI);
164  MachineInstr *getReachingDefForPred(RegisterRef RD,
165  MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond);
166  bool canMoveOver(MachineInstr *MI, ReferenceMap &Defs, ReferenceMap &Uses);
167  bool canMoveMemTo(MachineInstr *MI, MachineInstr *ToI, bool IsDown);
168  void predicateAt(RegisterRef RD, MachineInstr *MI,
169  MachineBasicBlock::iterator Where, unsigned PredR, bool Cond);
170  void renameInRange(RegisterRef RO, RegisterRef RN, unsigned PredR,
171  bool Cond, MachineBasicBlock::iterator First,
173  bool predicate(MachineInstr *TfrI, bool Cond);
174  bool predicateInBlock(MachineBasicBlock &B);
175 
176  void postprocessUndefImplicitUses(MachineBasicBlock &B);
177  void removeImplicitUses(MachineInstr *MI);
178  void removeImplicitUses(MachineBasicBlock &B);
179 
180  bool isIntReg(RegisterRef RR, unsigned &BW);
181  bool isIntraBlocks(LiveInterval &LI);
182  bool coalesceRegisters(RegisterRef R1, RegisterRef R2);
183  bool coalesceSegments(MachineFunction &MF);
184  };
185 }
186 
188 
189 
190 unsigned HexagonExpandCondsets::getMaskForSub(unsigned Sub) {
191  switch (Sub) {
192  case Hexagon::subreg_loreg:
193  return Sub_Low;
194  case Hexagon::subreg_hireg:
195  return Sub_High;
196  case Hexagon::NoSubRegister:
197  return Sub_None;
198  }
199  llvm_unreachable("Invalid subregister");
200 }
201 
202 
203 bool HexagonExpandCondsets::isCondset(const MachineInstr *MI) {
204  unsigned Opc = MI->getOpcode();
205  switch (Opc) {
206  case Hexagon::C2_mux:
207  case Hexagon::C2_muxii:
208  case Hexagon::C2_muxir:
209  case Hexagon::C2_muxri:
210  case Hexagon::MUX64_rr:
211  return true;
212  break;
213  }
214  return false;
215 }
216 
217 
218 void HexagonExpandCondsets::addRefToMap(RegisterRef RR, ReferenceMap &Map,
219  unsigned Exec) {
220  unsigned Mask = getMaskForSub(RR.Sub) | Exec;
221  ReferenceMap::iterator F = Map.find(RR.Reg);
222  if (F == Map.end())
223  Map.insert(std::make_pair(RR.Reg, Mask));
224  else
225  F->second |= Mask;
226 }
227 
228 
229 bool HexagonExpandCondsets::isRefInMap(RegisterRef RR, ReferenceMap &Map,
230  unsigned Exec) {
231  ReferenceMap::iterator F = Map.find(RR.Reg);
232  if (F == Map.end())
233  return false;
234  unsigned Mask = getMaskForSub(RR.Sub) | Exec;
235  if (Mask & F->second)
236  return true;
237  return false;
238 }
239 
240 
241 LiveInterval::iterator HexagonExpandCondsets::nextSegment(LiveInterval &LI,
242  SlotIndex S) {
243  for (LiveInterval::iterator I = LI.begin(), E = LI.end(); I != E; ++I) {
244  if (I->start >= S)
245  return I;
246  }
247  return LI.end();
248 }
249 
250 
251 LiveInterval::iterator HexagonExpandCondsets::prevSegment(LiveInterval &LI,
252  SlotIndex S) {
254  for (LiveInterval::iterator I = LI.begin(), E = LI.end(); I != E; ++I) {
255  if (I->end > S)
256  return P;
257  P = I;
258  }
259  return P;
260 }
261 
262 
263 /// Find the implicit use of register Reg in slot index S, and make sure
264 /// that the "defined" flag is set to SetDef. While the mux expansion is
265 /// going on, predicated instructions will have implicit uses of the
266 /// registers that are being defined. This is to keep any preceding
267 /// definitions live. If there is no preceding definition, the implicit
268 /// use will be marked as "undef", otherwise it will be "defined". This
269 /// function is used to update the flag.
270 void HexagonExpandCondsets::makeDefined(unsigned Reg, SlotIndex S,
271  bool SetDef) {
272  if (!S.isRegister())
273  return;
274  MachineInstr *MI = LIS->getInstructionFromIndex(S);
275  assert(MI && "Expecting instruction");
276  for (auto &Op : MI->operands()) {
277  if (!Op.isReg() || !Op.isUse() || Op.getReg() != Reg)
278  continue;
279  bool IsDef = !Op.isUndef();
280  if (Op.isImplicit() && IsDef != SetDef)
281  Op.setIsUndef(!SetDef);
282  }
283 }
284 
285 
286 void HexagonExpandCondsets::makeUndead(unsigned Reg, SlotIndex S) {
287  // If S is a block boundary, then there can still be a dead def reaching
288  // this point. Instead of traversing the CFG, queue start points of all
289  // live segments that begin with a register, and end at a block boundary.
290  // This may "resurrect" some truly dead definitions, but doing so is
291  // harmless.
293  if (S.isBlock()) {
294  LiveInterval &LI = LIS->getInterval(Reg);
295  for (LiveInterval::iterator I = LI.begin(), E = LI.end(); I != E; ++I) {
296  if (!I->start.isRegister() || !I->end.isBlock())
297  continue;
298  MachineInstr *MI = LIS->getInstructionFromIndex(I->start);
299  Defs.push_back(MI);
300  }
301  } else if (S.isRegister()) {
302  MachineInstr *MI = LIS->getInstructionFromIndex(S);
303  Defs.push_back(MI);
304  }
305 
306  for (unsigned i = 0, n = Defs.size(); i < n; ++i) {
307  MachineInstr *MI = Defs[i];
308  for (auto &Op : MI->operands()) {
309  if (!Op.isReg() || !Op.isDef() || Op.getReg() != Reg)
310  continue;
311  Op.setIsDead(false);
312  }
313  }
314 }
315 
316 
317 /// Shrink the segments in the live interval for a given register to the last
318 /// use before each subsequent def. Unlike LiveIntervals::shrinkToUses, this
319 /// function will not mark any definitions of Reg as dead. The reason for this
320 /// is that this function is used while a MUX instruction is being expanded,
321 /// or while a conditional copy is undergoing predication. During these
322 /// processes, there may be defs present in the instruction sequence that have
323 /// not yet been removed, or there may be missing uses that have not yet been
324 /// added. We want to utilize LiveIntervals::shrinkToUses as much as possible,
325 /// but since it does not extend any intervals that are too short, we need to
326 /// pre-emptively extend them here in anticipation of further changes.
327 void HexagonExpandCondsets::shrinkToUses(unsigned Reg, LiveInterval &LI) {
329  LIS->shrinkToUses(&LI, &Deads);
330  // Need to undo the deadification made by "shrinkToUses". It's easier to
331  // do it here, since we have a list of all instructions that were just
332  // marked as dead.
333  for (unsigned i = 0, n = Deads.size(); i < n; ++i) {
334  MachineInstr *MI = Deads[i];
335  // Clear the "dead" flag.
336  for (auto &Op : MI->operands()) {
337  if (!Op.isReg() || !Op.isDef() || Op.getReg() != Reg)
338  continue;
339  Op.setIsDead(false);
340  }
341  // Extend the live segment to the beginning of the next one.
342  LiveInterval::iterator End = LI.end();
343  SlotIndex S = LIS->getInstructionIndex(MI).getRegSlot();
345  assert(T != End);
346  LiveInterval::iterator N = std::next(T);
347  if (N != End)
348  T->end = N->start;
349  else
350  T->end = LIS->getMBBEndIdx(MI->getParent());
351  }
352  updateKillFlags(Reg, LI);
353 }
354 
355 
356 /// Given an updated live interval LI for register Reg, update the kill flags
357 /// in instructions using Reg to reflect the liveness changes.
358 void HexagonExpandCondsets::updateKillFlags(unsigned Reg, LiveInterval &LI) {
359  MRI->clearKillFlags(Reg);
360  for (LiveInterval::iterator I = LI.begin(), E = LI.end(); I != E; ++I) {
361  SlotIndex EX = I->end;
362  if (!EX.isRegister())
363  continue;
364  MachineInstr *MI = LIS->getInstructionFromIndex(EX);
365  for (auto &Op : MI->operands()) {
366  if (!Op.isReg() || !Op.isUse() || Op.getReg() != Reg)
367  continue;
368  // Only set the kill flag on the first encountered use of Reg in this
369  // instruction.
370  Op.setIsKill(true);
371  break;
372  }
373  }
374 }
375 
376 
377 /// When adding a new instruction to liveness, the newly added definition
378 /// will start a new live segment. This may happen at a position that falls
379 /// within an existing live segment. In such case that live segment needs to
380 /// be truncated to make room for the new segment. Ultimately, the truncation
381 /// will occur at the last use, but for now the segment can be terminated
382 /// right at the place where the new segment will start. The segments will be
383 /// shrunk-to-uses later.
384 void HexagonExpandCondsets::terminateSegment(LiveInterval::iterator LT,
385  SlotIndex S, LiveInterval &LI) {
386  // Terminate the live segment pointed to by LT within a live interval LI.
387  if (LT == LI.end())
388  return;
389 
390  VNInfo *OldVN = LT->valno;
391  SlotIndex EX = LT->end;
392  LT->end = S;
393  // If LT does not end at a block boundary, the termination is done.
394  if (!EX.isBlock())
395  return;
396 
397  // If LT ended at a block boundary, it's possible that its value number
398  // is picked up at the beginning other blocks. Create a new value number
399  // and change such blocks to use it instead.
400  VNInfo *NewVN = 0;
401  for (LiveInterval::iterator I = LI.begin(), E = LI.end(); I != E; ++I) {
402  if (!I->start.isBlock() || I->valno != OldVN)
403  continue;
404  // Generate on-demand a new value number that is defined by the
405  // block beginning (i.e. -phi).
406  if (!NewVN)
407  NewVN = LI.getNextValue(I->start, LIS->getVNInfoAllocator());
408  I->valno = NewVN;
409  }
410 }
411 
412 
413 /// Add the specified instruction to live intervals. This function is used
414 /// to update the live intervals while the program code is being changed.
415 /// Neither the expansion of a MUX, nor the predication are atomic, and this
416 /// function is used to update the live intervals while these transformations
417 /// are being done.
418 void HexagonExpandCondsets::addInstrToLiveness(MachineInstr *MI) {
419  SlotIndex MX = LIS->isNotInMIMap(MI) ? LIS->InsertMachineInstrInMaps(MI)
420  : LIS->getInstructionIndex(MI);
421  DEBUG(dbgs() << "adding liveness info for instr\n " << MX << " " << *MI);
422 
423  MX = MX.getRegSlot();
424  bool Predicated = HII->isPredicated(MI);
425  MachineBasicBlock *MB = MI->getParent();
426 
427  // Strip all implicit uses from predicated instructions. They will be
428  // added again, according to the updated information.
429  if (Predicated)
430  removeImplicitUses(MI);
431 
432  // For each def in MI we need to insert a new live segment starting at MX
433  // into the interval. If there already exists a live segment in the interval
434  // that contains MX, we need to terminate it at MX.
436  for (auto &Op : MI->operands())
437  if (Op.isReg() && Op.isDef())
438  Defs.push_back(RegisterRef(Op));
439 
440  for (unsigned i = 0, n = Defs.size(); i < n; ++i) {
441  unsigned DefR = Defs[i].Reg;
442  LiveInterval &LID = LIS->getInterval(DefR);
443  DEBUG(dbgs() << "adding def " << PrintReg(DefR, TRI)
444  << " with interval\n " << LID << "\n");
445  // If MX falls inside of an existing live segment, terminate it.
447  if (LT != LID.end())
448  terminateSegment(LT, MX, LID);
449  DEBUG(dbgs() << "after terminating segment\n " << LID << "\n");
450 
451  // Create a new segment starting from MX.
452  LiveInterval::iterator P = prevSegment(LID, MX), N = nextSegment(LID, MX);
453  SlotIndex EX;
454  VNInfo *VN = LID.getNextValue(MX, LIS->getVNInfoAllocator());
455  if (N == LID.end()) {
456  // There is no live segment after MX. End this segment at the end of
457  // the block.
458  EX = LIS->getMBBEndIdx(MB);
459  } else {
460  // If the next segment starts at the block boundary, end the new segment
461  // at the boundary of the preceding block (i.e. the previous index).
462  // Otherwise, end the segment at the beginning of the next segment. In
463  // either case it will be "shrunk-to-uses" later.
464  EX = N->start.isBlock() ? N->start.getPrevIndex() : N->start;
465  }
466  if (Predicated) {
467  // Predicated instruction will have an implicit use of the defined
468  // register. This is necessary so that this definition will not make
469  // any previous definitions dead. If there are no previous live
470  // segments, still add the implicit use, but make it "undef".
471  // Because of the implicit use, the preceding definition is not
472  // dead. Mark is as such (if necessary).
473  MachineOperand ImpUse = MachineOperand::CreateReg(DefR, false, true);
474  ImpUse.setSubReg(Defs[i].Sub);
475  bool Undef = false;
476  if (P == LID.end())
477  Undef = true;
478  else {
479  // If the previous segment extends to the end of the previous block,
480  // the end index may actually be the beginning of this block. If
481  // the previous segment ends at a block boundary, move it back by one,
482  // to get the proper block for it.
483  SlotIndex PE = P->end.isBlock() ? P->end.getPrevIndex() : P->end;
484  MachineBasicBlock *PB = LIS->getMBBFromIndex(PE);
485  if (PB != MB && !LIS->isLiveInToMBB(LID, MB))
486  Undef = true;
487  }
488  if (!Undef) {
489  makeUndead(DefR, P->valno->def);
490  // We are adding a live use, so extend the previous segment to
491  // include it.
492  P->end = MX;
493  } else {
494  ImpUse.setIsUndef(true);
495  }
496 
497  if (!MI->readsRegister(DefR))
498  MI->addOperand(ImpUse);
499  if (N != LID.end())
500  makeDefined(DefR, N->start, true);
501  }
502  LiveRange::Segment NR = LiveRange::Segment(MX, EX, VN);
503  LID.addSegment(NR);
504  DEBUG(dbgs() << "added a new segment " << NR << "\n " << LID << "\n");
505  shrinkToUses(DefR, LID);
506  DEBUG(dbgs() << "updated imp-uses: " << *MI);
507  LID.verify();
508  }
509 
510  // For each use in MI:
511  // - If there is no live segment that contains MX for the used register,
512  // extend the previous one. Ignore implicit uses.
513  for (auto &Op : MI->operands()) {
514  if (!Op.isReg() || !Op.isUse() || Op.isImplicit() || Op.isUndef())
515  continue;
516  unsigned UseR = Op.getReg();
517  LiveInterval &LIU = LIS->getInterval(UseR);
518  // Find the last segment P that starts before MX.
520  if (P == LIU.end())
521  P = prevSegment(LIU, MX);
522 
523  assert(P != LIU.end() && "MI uses undefined register?");
524  SlotIndex EX = P->end;
525  // If P contains MX, there is not much to do.
526  if (EX > MX) {
527  Op.setIsKill(false);
528  continue;
529  }
530  // Otherwise, extend P to "next(MX)".
531  P->end = MX.getNextIndex();
532  Op.setIsKill(true);
533  // Get the old "kill" instruction, and remove the kill flag.
534  if (MachineInstr *KI = LIS->getInstructionFromIndex(MX))
535  KI->clearRegisterKills(UseR, nullptr);
536  shrinkToUses(UseR, LIU);
537  LIU.verify();
538  }
539 }
540 
541 
542 /// Update the live interval information to reflect the removal of the given
543 /// instruction from the program. As with "addInstrToLiveness", this function
544 /// is called while the program code is being changed.
545 void HexagonExpandCondsets::removeInstrFromLiveness(MachineInstr *MI) {
546  SlotIndex MX = LIS->getInstructionIndex(MI).getRegSlot();
547  DEBUG(dbgs() << "removing instr\n " << MX << " " << *MI);
548 
549  // For each def in MI:
550  // If MI starts a live segment, merge this segment with the previous segment.
551  //
552  for (auto &Op : MI->operands()) {
553  if (!Op.isReg() || !Op.isDef())
554  continue;
555  unsigned DefR = Op.getReg();
556  LiveInterval &LID = LIS->getInterval(DefR);
558  assert(LT != LID.end() && "Expecting live segments");
559  DEBUG(dbgs() << "removing def at " << MX << " of " << PrintReg(DefR, TRI)
560  << " with interval\n " << LID << "\n");
561  if (LT->start != MX)
562  continue;
563 
564  VNInfo *MVN = LT->valno;
565  if (LT != LID.begin()) {
566  // If the current live segment is not the first, the task is easy. If
567  // the previous segment continues into the current block, extend it to
568  // the end of the current one, and merge the value numbers.
569  // Otherwise, remove the current segment, and make the end of it "undef".
570  LiveInterval::iterator P = std::prev(LT);
571  SlotIndex PE = P->end.isBlock() ? P->end.getPrevIndex() : P->end;
572  MachineBasicBlock *MB = MI->getParent();
573  MachineBasicBlock *PB = LIS->getMBBFromIndex(PE);
574  if (PB != MB && !LIS->isLiveInToMBB(LID, MB)) {
575  makeDefined(DefR, LT->end, false);
576  LID.removeSegment(*LT);
577  } else {
578  // Make the segments adjacent, so that merge-vn can also merge the
579  // segments.
580  P->end = LT->start;
581  makeUndead(DefR, P->valno->def);
582  LID.MergeValueNumberInto(MVN, P->valno);
583  }
584  } else {
585  LiveInterval::iterator N = std::next(LT);
586  LiveInterval::iterator RmB = LT, RmE = N;
587  while (N != LID.end()) {
588  // Iterate until the first register-based definition is found
589  // (i.e. skip all block-boundary entries).
590  LiveInterval::iterator Next = std::next(N);
591  if (N->start.isRegister()) {
592  makeDefined(DefR, N->start, false);
593  break;
594  }
595  if (N->end.isRegister()) {
596  makeDefined(DefR, N->end, false);
597  RmE = Next;
598  break;
599  }
600  RmE = Next;
601  N = Next;
602  }
603  // Erase the segments in one shot to avoid invalidating iterators.
604  LID.segments.erase(RmB, RmE);
605  }
606 
607  bool VNUsed = false;
608  for (LiveInterval::iterator I = LID.begin(), E = LID.end(); I != E; ++I) {
609  if (I->valno != MVN)
610  continue;
611  VNUsed = true;
612  break;
613  }
614  if (!VNUsed)
615  MVN->markUnused();
616 
617  DEBUG(dbgs() << "new interval: ");
618  if (!LID.empty()) {
619  DEBUG(dbgs() << LID << "\n");
620  LID.verify();
621  } else {
622  DEBUG(dbgs() << "<empty>\n");
623  LIS->removeInterval(DefR);
624  }
625  }
626 
627  // For uses there is nothing to do. The intervals will be updated via
628  // shrinkToUses.
630  for (auto &Op : MI->operands()) {
631  if (!Op.isReg() || !Op.isUse())
632  continue;
633  unsigned R = Op.getReg();
635  continue;
636  Uses.push_back(R);
637  }
638  LIS->RemoveMachineInstrFromMaps(MI);
639  MI->eraseFromParent();
640  for (unsigned i = 0, n = Uses.size(); i < n; ++i) {
641  LiveInterval &LI = LIS->getInterval(Uses[i]);
642  shrinkToUses(Uses[i], LI);
643  }
644 }
645 
646 
647 /// Get the opcode for a conditional transfer of the value in SO (source
648 /// operand). The condition (true/false) is given in Cond.
649 unsigned HexagonExpandCondsets::getCondTfrOpcode(const MachineOperand &SO,
650  bool Cond) {
651  using namespace Hexagon;
652  if (SO.isReg()) {
653  unsigned PhysR;
654  RegisterRef RS = SO;
656  const TargetRegisterClass *VC = MRI->getRegClass(RS.Reg);
657  assert(VC->begin() != VC->end() && "Empty register class");
658  PhysR = *VC->begin();
659  } else {
661  PhysR = RS.Reg;
662  }
663  unsigned PhysS = (RS.Sub == 0) ? PhysR : TRI->getSubReg(PhysR, RS.Sub);
664  const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(PhysS);
665  switch (RC->getSize()) {
666  case 4:
667  return Cond ? A2_tfrt : A2_tfrf;
668  case 8:
669  return Cond ? A2_tfrpt : A2_tfrpf;
670  }
671  llvm_unreachable("Invalid register operand");
672  }
673  if (SO.isImm() || SO.isFPImm())
674  return Cond ? C2_cmoveit : C2_cmoveif;
675  llvm_unreachable("Unexpected source operand");
676 }
677 
678 
679 /// Generate a conditional transfer, copying the value SrcOp to the
680 /// destination register DstR:DstSR, and using the predicate register from
681 /// PredOp. The Cond argument specifies whether the predicate is to be
682 /// if(PredOp), or if(!PredOp).
683 MachineInstr *HexagonExpandCondsets::genTfrFor(MachineOperand &SrcOp,
684  unsigned DstR, unsigned DstSR, const MachineOperand &PredOp, bool Cond) {
685  MachineInstr *MI = SrcOp.getParent();
686  MachineBasicBlock &B = *MI->getParent();
688  DebugLoc DL = MI->getDebugLoc();
689 
690  // Don't avoid identity copies here (i.e. if the source and the destination
691  // are the same registers). It is actually better to generate them here,
692  // since this would cause the copy to potentially be predicated in the next
693  // step. The predication will remove such a copy if it is unable to
694  /// predicate.
695 
696  unsigned Opc = getCondTfrOpcode(SrcOp, Cond);
697  MachineInstr *TfrI = BuildMI(B, At, DL, HII->get(Opc))
698  .addReg(DstR, RegState::Define, DstSR)
699  .addOperand(PredOp)
700  .addOperand(SrcOp);
701  // We don't want any kills yet.
702  TfrI->clearKillInfo();
703  DEBUG(dbgs() << "created an initial copy: " << *TfrI);
704  return TfrI;
705 }
706 
707 
708 /// Replace a MUX instruction MI with a pair A2_tfrt/A2_tfrf. This function
709 /// performs all necessary changes to complete the replacement.
711  if (TfrLimitActive) {
712  if (TfrCounter >= TfrLimit)
713  return false;
714  TfrCounter++;
715  }
716  DEBUG(dbgs() << "\nsplitting BB#" << MI->getParent()->getNumber()
717  << ": " << *MI);
718  MachineOperand &MD = MI->getOperand(0); // Definition
719  MachineOperand &MP = MI->getOperand(1); // Predicate register
720  assert(MD.isDef());
721  unsigned DR = MD.getReg(), DSR = MD.getSubReg();
722 
723  // First, create the two invididual conditional transfers, and add each
724  // of them to the live intervals information. Do that first and then remove
725  // the old instruction from live intervals.
726  if (MachineInstr *TfrT = genTfrFor(MI->getOperand(2), DR, DSR, MP, true))
727  addInstrToLiveness(TfrT);
728  if (MachineInstr *TfrF = genTfrFor(MI->getOperand(3), DR, DSR, MP, false))
729  addInstrToLiveness(TfrF);
730  removeInstrFromLiveness(MI);
731 
732  return true;
733 }
734 
735 
736 /// Split all MUX instructions in the given block into pairs of contitional
737 /// transfers.
738 bool HexagonExpandCondsets::splitInBlock(MachineBasicBlock &B) {
739  bool Changed = false;
740  MachineBasicBlock::iterator I, E, NextI;
741  for (I = B.begin(), E = B.end(); I != E; I = NextI) {
742  NextI = std::next(I);
743  if (isCondset(I))
744  Changed |= split(I);
745  }
746  return Changed;
747 }
748 
749 
750 bool HexagonExpandCondsets::isPredicable(MachineInstr *MI) {
751  if (HII->isPredicated(MI) || !HII->isPredicable(MI))
752  return false;
753  if (MI->hasUnmodeledSideEffects() || MI->mayStore())
754  return false;
755  // Reject instructions with multiple defs (e.g. post-increment loads).
756  bool HasDef = false;
757  for (auto &Op : MI->operands()) {
758  if (!Op.isReg() || !Op.isDef())
759  continue;
760  if (HasDef)
761  return false;
762  HasDef = true;
763  }
764  for (auto &Mo : MI->memoperands())
765  if (Mo->isVolatile())
766  return false;
767  return true;
768 }
769 
770 
771 /// Find the reaching definition for a predicated use of RD. The RD is used
772 /// under the conditions given by PredR and Cond, and this function will ignore
773 /// definitions that set RD under the opposite conditions.
774 MachineInstr *HexagonExpandCondsets::getReachingDefForPred(RegisterRef RD,
775  MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond) {
776  MachineBasicBlock &B = *UseIt->getParent();
777  MachineBasicBlock::iterator I = UseIt, S = B.begin();
778  if (I == S)
779  return 0;
780 
781  bool PredValid = true;
782  do {
783  --I;
784  MachineInstr *MI = &*I;
785  // Check if this instruction can be ignored, i.e. if it is predicated
786  // on the complementary condition.
787  if (PredValid && HII->isPredicated(MI)) {
788  if (MI->readsRegister(PredR) && (Cond != HII->isPredicatedTrue(MI)))
789  continue;
790  }
791 
792  // Check the defs. If the PredR is defined, invalidate it. If RD is
793  // defined, return the instruction or 0, depending on the circumstances.
794  for (auto &Op : MI->operands()) {
795  if (!Op.isReg() || !Op.isDef())
796  continue;
797  RegisterRef RR = Op;
798  if (RR.Reg == PredR) {
799  PredValid = false;
800  continue;
801  }
802  if (RR.Reg != RD.Reg)
803  continue;
804  // If the "Reg" part agrees, there is still the subregister to check.
805  // If we are looking for vreg1:loreg, we can skip vreg1:hireg, but
806  // not vreg1 (w/o subregisters).
807  if (RR.Sub == RD.Sub)
808  return MI;
809  if (RR.Sub == 0 || RD.Sub == 0)
810  return 0;
811  // We have different subregisters, so we can continue looking.
812  }
813  } while (I != S);
814 
815  return 0;
816 }
817 
818 
819 /// Check if the instruction MI can be safely moved over a set of instructions
820 /// whose side-effects (in terms of register defs and uses) are expressed in
821 /// the maps Defs and Uses. These maps reflect the conditional defs and uses
822 /// that depend on the same predicate register to allow moving instructions
823 /// over instructions predicated on the opposite condition.
824 bool HexagonExpandCondsets::canMoveOver(MachineInstr *MI, ReferenceMap &Defs,
825  ReferenceMap &Uses) {
826  // In order to be able to safely move MI over instructions that define
827  // "Defs" and use "Uses", no def operand from MI can be defined or used
828  // and no use operand can be defined.
829  for (auto &Op : MI->operands()) {
830  if (!Op.isReg())
831  continue;
832  RegisterRef RR = Op;
833  // For physical register we would need to check register aliases, etc.
834  // and we don't want to bother with that. It would be of little value
835  // before the actual register rewriting (from virtual to physical).
837  return false;
838  // No redefs for any operand.
839  if (isRefInMap(RR, Defs, Exec_Then))
840  return false;
841  // For defs, there cannot be uses.
842  if (Op.isDef() && isRefInMap(RR, Uses, Exec_Then))
843  return false;
844  }
845  return true;
846 }
847 
848 
849 /// Check if the instruction accessing memory (TheI) can be moved to the
850 /// location ToI.
851 bool HexagonExpandCondsets::canMoveMemTo(MachineInstr *TheI, MachineInstr *ToI,
852  bool IsDown) {
853  bool IsLoad = TheI->mayLoad(), IsStore = TheI->mayStore();
854  if (!IsLoad && !IsStore)
855  return true;
856  if (HII->areMemAccessesTriviallyDisjoint(TheI, ToI))
857  return true;
858  if (TheI->hasUnmodeledSideEffects())
859  return false;
860 
861  MachineBasicBlock::iterator StartI = IsDown ? TheI : ToI;
862  MachineBasicBlock::iterator EndI = IsDown ? ToI : TheI;
863  bool Ordered = TheI->hasOrderedMemoryRef();
864 
865  // Search for aliased memory reference in (StartI, EndI).
866  for (MachineBasicBlock::iterator I = std::next(StartI); I != EndI; ++I) {
867  MachineInstr *MI = &*I;
868  if (MI->hasUnmodeledSideEffects())
869  return false;
870  bool L = MI->mayLoad(), S = MI->mayStore();
871  if (!L && !S)
872  continue;
873  if (Ordered && MI->hasOrderedMemoryRef())
874  return false;
875 
876  bool Conflict = (L && IsStore) || S;
877  if (Conflict)
878  return false;
879  }
880  return true;
881 }
882 
883 
884 /// Generate a predicated version of MI (where the condition is given via
885 /// PredR and Cond) at the point indicated by Where.
886 void HexagonExpandCondsets::predicateAt(RegisterRef RD, MachineInstr *MI,
887  MachineBasicBlock::iterator Where, unsigned PredR, bool Cond) {
888  // The problem with updating live intervals is that we can move one def
889  // past another def. In particular, this can happen when moving an A2_tfrt
890  // over an A2_tfrf defining the same register. From the point of view of
891  // live intervals, these two instructions are two separate definitions,
892  // and each one starts another live segment. LiveIntervals's "handleMove"
893  // does not allow such moves, so we need to handle it ourselves. To avoid
894  // invalidating liveness data while we are using it, the move will be
895  // implemented in 4 steps: (1) add a clone of the instruction MI at the
896  // target location, (2) update liveness, (3) delete the old instruction,
897  // and (4) update liveness again.
898 
899  MachineBasicBlock &B = *MI->getParent();
900  DebugLoc DL = Where->getDebugLoc(); // "Where" points to an instruction.
901  unsigned Opc = MI->getOpcode();
902  unsigned PredOpc = HII->getCondOpcode(Opc, !Cond);
903  MachineInstrBuilder MB = BuildMI(B, Where, DL, HII->get(PredOpc));
904  unsigned Ox = 0, NP = MI->getNumOperands();
905  // Skip all defs from MI first.
906  while (Ox < NP) {
907  MachineOperand &MO = MI->getOperand(Ox);
908  if (!MO.isReg() || !MO.isDef())
909  break;
910  Ox++;
911  }
912  // Add the new def, then the predicate register, then the rest of the
913  // operands.
914  MB.addReg(RD.Reg, RegState::Define, RD.Sub);
915  MB.addReg(PredR);
916  while (Ox < NP) {
917  MachineOperand &MO = MI->getOperand(Ox);
918  if (!MO.isReg() || !MO.isImplicit())
919  MB.addOperand(MO);
920  Ox++;
921  }
922 
923  MachineFunction &MF = *B.getParent();
925  unsigned NR = std::distance(I, MI->memoperands_end());
927  for (unsigned i = 0; i < NR; ++i)
928  MemRefs[i] = *I++;
929  MB.setMemRefs(MemRefs, MemRefs+NR);
930 
931  MachineInstr *NewI = MB;
932  NewI->clearKillInfo();
933  addInstrToLiveness(NewI);
934 }
935 
936 
937 /// In the range [First, Last], rename all references to the "old" register RO
938 /// to the "new" register RN, but only in instructions predicated on the given
939 /// condition.
940 void HexagonExpandCondsets::renameInRange(RegisterRef RO, RegisterRef RN,
941  unsigned PredR, bool Cond, MachineBasicBlock::iterator First,
943  MachineBasicBlock::iterator End = std::next(Last);
944  for (MachineBasicBlock::iterator I = First; I != End; ++I) {
945  MachineInstr *MI = &*I;
946  // Do not touch instructions that are not predicated, or are predicated
947  // on the opposite condition.
948  if (!HII->isPredicated(MI))
949  continue;
950  if (!MI->readsRegister(PredR) || (Cond != HII->isPredicatedTrue(MI)))
951  continue;
952 
953  for (auto &Op : MI->operands()) {
954  if (!Op.isReg() || RO != RegisterRef(Op))
955  continue;
956  Op.setReg(RN.Reg);
957  Op.setSubReg(RN.Sub);
958  // In practice, this isn't supposed to see any defs.
959  assert(!Op.isDef() && "Not expecting a def");
960  }
961  }
962 }
963 
964 
965 /// For a given conditional copy, predicate the definition of the source of
966 /// the copy under the given condition (using the same predicate register as
967 /// the copy).
968 bool HexagonExpandCondsets::predicate(MachineInstr *TfrI, bool Cond) {
969  // TfrI - A2_tfr[tf] Instruction (not A2_tfrsi).
970  unsigned Opc = TfrI->getOpcode();
971  (void)Opc;
972  assert(Opc == Hexagon::A2_tfrt || Opc == Hexagon::A2_tfrf);
973  DEBUG(dbgs() << "\nattempt to predicate if-" << (Cond ? "true" : "false")
974  << ": " << *TfrI);
975 
976  MachineOperand &MD = TfrI->getOperand(0);
977  MachineOperand &MP = TfrI->getOperand(1);
978  MachineOperand &MS = TfrI->getOperand(2);
979  // The source operand should be a <kill>. This is not strictly necessary,
980  // but it makes things a lot simpler. Otherwise, we would need to rename
981  // some registers, which would complicate the transformation considerably.
982  if (!MS.isKill())
983  return false;
984 
985  RegisterRef RT(MS);
986  unsigned PredR = MP.getReg();
987  MachineInstr *DefI = getReachingDefForPred(RT, TfrI, PredR, Cond);
988  if (!DefI || !isPredicable(DefI))
989  return false;
990 
991  DEBUG(dbgs() << "Source def: " << *DefI);
992 
993  // Collect the information about registers defined and used between the
994  // DefI and the TfrI.
995  // Map: reg -> bitmask of subregs
996  ReferenceMap Uses, Defs;
997  MachineBasicBlock::iterator DefIt = DefI, TfrIt = TfrI;
998 
999  // Check if the predicate register is valid between DefI and TfrI.
1000  // If it is, we can then ignore instructions predicated on the negated
1001  // conditions when collecting def and use information.
1002  bool PredValid = true;
1003  for (MachineBasicBlock::iterator I = std::next(DefIt); I != TfrIt; ++I) {
1004  if (!I->modifiesRegister(PredR, 0))
1005  continue;
1006  PredValid = false;
1007  break;
1008  }
1009 
1010  for (MachineBasicBlock::iterator I = std::next(DefIt); I != TfrIt; ++I) {
1011  MachineInstr *MI = &*I;
1012  // If this instruction is predicated on the same register, it could
1013  // potentially be ignored.
1014  // By default assume that the instruction executes on the same condition
1015  // as TfrI (Exec_Then), and also on the opposite one (Exec_Else).
1016  unsigned Exec = Exec_Then | Exec_Else;
1017  if (PredValid && HII->isPredicated(MI) && MI->readsRegister(PredR))
1018  Exec = (Cond == HII->isPredicatedTrue(MI)) ? Exec_Then : Exec_Else;
1019 
1020  for (auto &Op : MI->operands()) {
1021  if (!Op.isReg())
1022  continue;
1023  // We don't want to deal with physical registers. The reason is that
1024  // they can be aliased with other physical registers. Aliased virtual
1025  // registers must share the same register number, and can only differ
1026  // in the subregisters, which we are keeping track of. Physical
1027  // registers ters no longer have subregisters---their super- and
1028  // subregisters are other physical registers, and we are not checking
1029  // that.
1030  RegisterRef RR = Op;
1032  return false;
1033 
1034  ReferenceMap &Map = Op.isDef() ? Defs : Uses;
1035  addRefToMap(RR, Map, Exec);
1036  }
1037  }
1038 
1039  // The situation:
1040  // RT = DefI
1041  // ...
1042  // RD = TfrI ..., RT
1043 
1044  // If the register-in-the-middle (RT) is used or redefined between
1045  // DefI and TfrI, we may not be able proceed with this transformation.
1046  // We can ignore a def that will not execute together with TfrI, and a
1047  // use that will. If there is such a use (that does execute together with
1048  // TfrI), we will not be able to move DefI down. If there is a use that
1049  // executed if TfrI's condition is false, then RT must be available
1050  // unconditionally (cannot be predicated).
1051  // Essentially, we need to be able to rename RT to RD in this segment.
1052  if (isRefInMap(RT, Defs, Exec_Then) || isRefInMap(RT, Uses, Exec_Else))
1053  return false;
1054  RegisterRef RD = MD;
1055  // If the predicate register is defined between DefI and TfrI, the only
1056  // potential thing to do would be to move the DefI down to TfrI, and then
1057  // predicate. The reaching def (DefI) must be movable down to the location
1058  // of the TfrI.
1059  // If the target register of the TfrI (RD) is not used or defined between
1060  // DefI and TfrI, consider moving TfrI up to DefI.
1061  bool CanUp = canMoveOver(TfrI, Defs, Uses);
1062  bool CanDown = canMoveOver(DefI, Defs, Uses);
1063  // The TfrI does not access memory, but DefI could. Check if it's safe
1064  // to move DefI down to TfrI.
1065  if (DefI->mayLoad() || DefI->mayStore())
1066  if (!canMoveMemTo(DefI, TfrI, true))
1067  CanDown = false;
1068 
1069  DEBUG(dbgs() << "Can move up: " << (CanUp ? "yes" : "no")
1070  << ", can move down: " << (CanDown ? "yes\n" : "no\n"));
1071  MachineBasicBlock::iterator PastDefIt = std::next(DefIt);
1072  if (CanUp)
1073  predicateAt(RD, DefI, PastDefIt, PredR, Cond);
1074  else if (CanDown)
1075  predicateAt(RD, DefI, TfrIt, PredR, Cond);
1076  else
1077  return false;
1078 
1079  if (RT != RD)
1080  renameInRange(RT, RD, PredR, Cond, PastDefIt, TfrIt);
1081 
1082  // Delete the user of RT first (it should work either way, but this order
1083  // of deleting is more natural).
1084  removeInstrFromLiveness(TfrI);
1085  removeInstrFromLiveness(DefI);
1086  return true;
1087 }
1088 
1089 
1090 /// Predicate all cases of conditional copies in the specified block.
1091 bool HexagonExpandCondsets::predicateInBlock(MachineBasicBlock &B) {
1092  bool Changed = false;
1093  MachineBasicBlock::iterator I, E, NextI;
1094  for (I = B.begin(), E = B.end(); I != E; I = NextI) {
1095  NextI = std::next(I);
1096  unsigned Opc = I->getOpcode();
1097  if (Opc == Hexagon::A2_tfrt || Opc == Hexagon::A2_tfrf) {
1098  bool Done = predicate(I, (Opc == Hexagon::A2_tfrt));
1099  if (!Done) {
1100  // If we didn't predicate I, we may need to remove it in case it is
1101  // an "identity" copy, e.g. vreg1 = A2_tfrt vreg2, vreg1.
1102  if (RegisterRef(I->getOperand(0)) == RegisterRef(I->getOperand(2)))
1103  removeInstrFromLiveness(I);
1104  }
1105  Changed |= Done;
1106  }
1107  }
1108  return Changed;
1109 }
1110 
1111 
1112 void HexagonExpandCondsets::removeImplicitUses(MachineInstr *MI) {
1113  for (unsigned i = MI->getNumOperands(); i > 0; --i) {
1114  MachineOperand &MO = MI->getOperand(i-1);
1115  if (MO.isReg() && MO.isUse() && MO.isImplicit())
1116  MI->RemoveOperand(i-1);
1117  }
1118 }
1119 
1120 
1121 void HexagonExpandCondsets::removeImplicitUses(MachineBasicBlock &B) {
1122  for (MachineBasicBlock::iterator I = B.begin(), E = B.end(); I != E; ++I) {
1123  MachineInstr *MI = &*I;
1124  if (HII->isPredicated(MI))
1125  removeImplicitUses(MI);
1126  }
1127 }
1128 
1129 
1130 void HexagonExpandCondsets::postprocessUndefImplicitUses(MachineBasicBlock &B) {
1131  // Implicit uses that are "undef" are only meaningful (outside of the
1132  // internals of this pass) when the instruction defines a subregister,
1133  // and the implicit-undef use applies to the defined register. In such
1134  // cases, the proper way to record the information in the IR is to mark
1135  // the definition as "undef", which will be interpreted as "read-undef".
1136  typedef SmallSet<unsigned,2> RegisterSet;
1137  for (MachineBasicBlock::iterator I = B.begin(), E = B.end(); I != E; ++I) {
1138  MachineInstr *MI = &*I;
1139  RegisterSet Undefs;
1140  for (unsigned i = MI->getNumOperands(); i > 0; --i) {
1141  MachineOperand &MO = MI->getOperand(i-1);
1142  if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.isUndef()) {
1143  MI->RemoveOperand(i-1);
1144  Undefs.insert(MO.getReg());
1145  }
1146  }
1147  for (auto &Op : MI->operands()) {
1148  if (!Op.isReg() || !Op.isDef() || !Op.getSubReg())
1149  continue;
1150  if (Undefs.count(Op.getReg()))
1151  Op.setIsUndef(true);
1152  }
1153  }
1154 }
1155 
1156 
1157 bool HexagonExpandCondsets::isIntReg(RegisterRef RR, unsigned &BW) {
1159  return false;
1160  const TargetRegisterClass *RC = MRI->getRegClass(RR.Reg);
1161  if (RC == &Hexagon::IntRegsRegClass) {
1162  BW = 32;
1163  return true;
1164  }
1165  if (RC == &Hexagon::DoubleRegsRegClass) {
1166  BW = (RR.Sub != 0) ? 32 : 64;
1167  return true;
1168  }
1169  return false;
1170 }
1171 
1172 
1173 bool HexagonExpandCondsets::isIntraBlocks(LiveInterval &LI) {
1174  for (LiveInterval::iterator I = LI.begin(), E = LI.end(); I != E; ++I) {
1175  LiveRange::Segment &LR = *I;
1176  // Range must start at a register...
1177  if (!LR.start.isRegister())
1178  return false;
1179  // ...and end in a register or in a dead slot.
1180  if (!LR.end.isRegister() && !LR.end.isDead())
1181  return false;
1182  }
1183  return true;
1184 }
1185 
1186 
1187 bool HexagonExpandCondsets::coalesceRegisters(RegisterRef R1, RegisterRef R2) {
1188  if (CoaLimitActive) {
1189  if (CoaCounter >= CoaLimit)
1190  return false;
1191  CoaCounter++;
1192  }
1193  unsigned BW1, BW2;
1194  if (!isIntReg(R1, BW1) || !isIntReg(R2, BW2) || BW1 != BW2)
1195  return false;
1196  if (MRI->isLiveIn(R1.Reg))
1197  return false;
1198  if (MRI->isLiveIn(R2.Reg))
1199  return false;
1200 
1201  LiveInterval &L1 = LIS->getInterval(R1.Reg);
1202  LiveInterval &L2 = LIS->getInterval(R2.Reg);
1203  bool Overlap = L1.overlaps(L2);
1204 
1205  DEBUG(dbgs() << "compatible registers: ("
1206  << (Overlap ? "overlap" : "disjoint") << ")\n "
1207  << PrintReg(R1.Reg, TRI, R1.Sub) << " " << L1 << "\n "
1208  << PrintReg(R2.Reg, TRI, R2.Sub) << " " << L2 << "\n");
1209  if (R1.Sub || R2.Sub)
1210  return false;
1211  if (Overlap)
1212  return false;
1213 
1214  // Coalescing could have a negative impact on scheduling, so try to limit
1215  // to some reasonable extent. Only consider coalescing segments, when one
1216  // of them does not cross basic block boundaries.
1217  if (!isIntraBlocks(L1) && !isIntraBlocks(L2))
1218  return false;
1219 
1220  MRI->replaceRegWith(R2.Reg, R1.Reg);
1221 
1222  // Move all live segments from L2 to L1.
1223  typedef DenseMap<VNInfo*,VNInfo*> ValueInfoMap;
1224  ValueInfoMap VM;
1225  for (LiveInterval::iterator I = L2.begin(), E = L2.end(); I != E; ++I) {
1226  VNInfo *NewVN, *OldVN = I->valno;
1227  ValueInfoMap::iterator F = VM.find(OldVN);
1228  if (F == VM.end()) {
1229  NewVN = L1.getNextValue(I->valno->def, LIS->getVNInfoAllocator());
1230  VM.insert(std::make_pair(OldVN, NewVN));
1231  } else {
1232  NewVN = F->second;
1233  }
1234  L1.addSegment(LiveRange::Segment(I->start, I->end, NewVN));
1235  }
1236  while (L2.begin() != L2.end())
1237  L2.removeSegment(*L2.begin());
1238 
1239  updateKillFlags(R1.Reg, L1);
1240  DEBUG(dbgs() << "coalesced: " << L1 << "\n");
1241  L1.verify();
1242 
1243  return true;
1244 }
1245 
1246 
1247 /// Attempt to coalesce one of the source registers to a MUX intruction with
1248 /// the destination register. This could lead to having only one predicated
1249 /// instruction in the end instead of two.
1250 bool HexagonExpandCondsets::coalesceSegments(MachineFunction &MF) {
1252  for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
1253  MachineBasicBlock &B = *I;
1254  for (MachineBasicBlock::iterator J = B.begin(), F = B.end(); J != F; ++J) {
1255  MachineInstr *MI = &*J;
1256  if (!isCondset(MI))
1257  continue;
1258  MachineOperand &S1 = MI->getOperand(2), &S2 = MI->getOperand(3);
1259  if (!S1.isReg() && !S2.isReg())
1260  continue;
1261  Condsets.push_back(MI);
1262  }
1263  }
1264 
1265  bool Changed = false;
1266  for (unsigned i = 0, n = Condsets.size(); i < n; ++i) {
1267  MachineInstr *CI = Condsets[i];
1268  RegisterRef RD = CI->getOperand(0);
1269  RegisterRef RP = CI->getOperand(1);
1270  MachineOperand &S1 = CI->getOperand(2), &S2 = CI->getOperand(3);
1271  bool Done = false;
1272  // Consider this case:
1273  // vreg1 = instr1 ...
1274  // vreg2 = instr2 ...
1275  // vreg0 = C2_mux ..., vreg1, vreg2
1276  // If vreg0 was coalesced with vreg1, we could end up with the following
1277  // code:
1278  // vreg0 = instr1 ...
1279  // vreg2 = instr2 ...
1280  // vreg0 = A2_tfrf ..., vreg2
1281  // which will later become:
1282  // vreg0 = instr1 ...
1283  // vreg0 = instr2_cNotPt ...
1284  // i.e. there will be an unconditional definition (instr1) of vreg0
1285  // followed by a conditional one. The output dependency was there before
1286  // and it unavoidable, but if instr1 is predicable, we will no longer be
1287  // able to predicate it here.
1288  // To avoid this scenario, don't coalesce the destination register with
1289  // a source register that is defined by a predicable instruction.
1290  if (S1.isReg()) {
1291  RegisterRef RS = S1;
1292  MachineInstr *RDef = getReachingDefForPred(RS, CI, RP.Reg, true);
1293  if (!RDef || !HII->isPredicable(RDef))
1294  Done = coalesceRegisters(RD, RegisterRef(S1));
1295  }
1296  if (!Done && S2.isReg()) {
1297  RegisterRef RS = S2;
1298  MachineInstr *RDef = getReachingDefForPred(RS, CI, RP.Reg, false);
1299  if (!RDef || !HII->isPredicable(RDef))
1300  Done = coalesceRegisters(RD, RegisterRef(S2));
1301  }
1302  Changed |= Done;
1303  }
1304  return Changed;
1305 }
1306 
1307 
1308 bool HexagonExpandCondsets::runOnMachineFunction(MachineFunction &MF) {
1309  HII = static_cast<const HexagonInstrInfo*>(MF.getSubtarget().getInstrInfo());
1310  TRI = MF.getSubtarget().getRegisterInfo();
1311  LIS = &getAnalysis<LiveIntervals>();
1312  MRI = &MF.getRegInfo();
1313 
1314  bool Changed = false;
1315 
1316  // Try to coalesce the target of a mux with one of its sources.
1317  // This could eliminate a register copy in some circumstances.
1318  Changed |= coalesceSegments(MF);
1319 
1320  for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
1321  // First, simply split all muxes into a pair of conditional transfers
1322  // and update the live intervals to reflect the new arrangement.
1323  // This is done mainly to make the live interval update simpler, than it
1324  // would be while trying to predicate instructions at the same time.
1325  Changed |= splitInBlock(*I);
1326  // Traverse all blocks and collapse predicable instructions feeding
1327  // conditional transfers into predicated instructions.
1328  // Walk over all the instructions again, so we may catch pre-existing
1329  // cases that were not created in the previous step.
1330  Changed |= predicateInBlock(*I);
1331  }
1332 
1333  for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
1334  postprocessUndefImplicitUses(*I);
1335  return Changed;
1336 }
1337 
1338 
1339 //===----------------------------------------------------------------------===//
1340 // Public Constructor Functions
1341 //===----------------------------------------------------------------------===//
1342 
1344  const char *Name = "Hexagon Expand Condsets";
1345  PassInfo *PI = new PassInfo(Name, "expand-condsets",
1346  &HexagonExpandCondsets::ID, 0, false, false);
1347  Registry.registerPass(*PI, true);
1348 }
1349 
1352 }
1353 
1354 
1356  return new HexagonExpandCondsets();
1357 }
bool isImplicit() const
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Segments::iterator iterator
Definition: LiveInterval.h:204
int getNumber() const
getNumber - MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a M...
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:588
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:579
void setIsUndef(bool Val=true)
FunctionPass * createHexagonExpandCondsets()
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
A global registry used in conjunction with static constructors to make pluggable components (like tar...
Definition: Registry.h:61
bool isPredicable(QueryType Type=AllInBundle) const
Return true if this instruction has a predicate operand that controls execution.
Definition: MachineInstr.h:457
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
This represents a simple continuous liveness interval for a value.
Definition: LiveInterval.h:159
A debug info location.
Definition: DebugLoc.h:34
static std::pair< StringRef, StringRef > split(StringRef Str, char Separator)
Checked version of split, to ensure mandatory subparts.
Definition: DataLayout.cpp:192
F(f)
bool isRegister() const
isRegister - Returns true if this is a normal register use/def slot.
Definition: SlotIndexes.h:236
void markUnused()
Mark this value as unused.
Definition: LiveInterval.h:80
#define R2(n)
iterator_range< mmo_iterator > memoperands()
Definition: MachineInstr.h:344
VNInfo - Value Number Information.
Definition: LiveInterval.h:45
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:295
bool empty() const
Definition: LiveInterval.h:353
static void initializePassOnce(PassRegistry &Registry)
void clearKillInfo()
Clears kill flags on all operands.
unsigned getSize() const
getSize - Return the size of the register in bytes, which is also the size of a stack slot allocated ...
AnalysisUsage & addRequired()
MachineMemOperand - A description of a memory reference used in the backend.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false)
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
iterator end()
Definition: LiveInterval.h:206
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:566
iterator begin() const
begin/end - Return all of the registers in this class.
Reg
All possible values of the reg field in the ModR/M byte.
bool isUndef() const
bool isBlock() const
isBlock - Returns true if this is a block boundary slot.
Definition: SlotIndexes.h:229
#define false
Definition: ConvertUTF.c:65
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:271
PrintReg - Helper class for printing registers on a raw_ostream.
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
bool isDead() const
isDead - Returns true if this is a dead def kill slot.
Definition: SlotIndexes.h:239
bool isKill() const
SlotIndexes pass.
Definition: SlotIndexes.h:334
iterator addSegment(Segment S)
Add the specified Segment to this range, merging segments as appropriate.
Segments segments
Definition: LiveInterval.h:195
VNInfo * MergeValueNumberInto(VNInfo *V1, VNInfo *V2)
MergeValueNumberInto - This method is called when two value numbers are found to be equivalent...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:267
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:120
mmo_iterator memoperands_end() const
Definition: MachineInstr.h:341
bundle_iterator< MachineInstr, instr_iterator > iterator
#define P(N)
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:325
const MachineInstrBuilder & setMemRefs(MachineInstr::mmo_iterator b, MachineInstr::mmo_iterator e) const
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:32
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
bool overlaps(const LiveRange &other) const
overlaps - Return true if the intersection of the two live ranges is not empty.
Definition: LiveInterval.h:419
Represent the analysis usage information of a pass.
static cl::opt< unsigned > OptCoaLimit("expand-condsets-coa-limit", cl::init(~0U), cl::Hidden, cl::desc("Max number of segment coalescings"))
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore...
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:294
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
PassInfo class - An instance of this class exists for every pass known by the system, and can be obtained from a live Pass by calling its getPassInfo() method.
Definition: PassInfo.h:30
iterator erase(iterator I)
Definition: SmallVector.h:455
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void removeSegment(SlotIndex Start, SlotIndex End, bool RemoveDeadValNo=false)
Remove the specified segment from this range.
bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
Definition: MachineInstr.h:836
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:861
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:123
bool isFPImm() const
isFPImm - Tests if this is a MO_FPImmediate operand.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:238
static cl::opt< unsigned > OptTfrLimit("expand-condsets-tfr-limit", cl::init(~0U), cl::Hidden, cl::desc("Max number of mux expansions"))
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
SlotIndex getNextIndex() const
Returns the next index.
Definition: SlotIndexes.h:282
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)
Definition: Metadata.h:1030
bool operator!=(uint64_t V1, const APInt &V2)
Definition: APInt.h:1736
Representation of each machine instruction.
Definition: MachineInstr.h:51
static bool isPhysicalRegister(unsigned Reg)
isPhysicalRegister - Return true if the specified register number is in the physical register namespa...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
#define I(x, y, z)
Definition: MD5.cpp:54
#define N
void setSubReg(unsigned subReg)
void verify(const MachineRegisterInfo *MRI=nullptr) const
Walks the interval and assert if any invariants fail to hold.
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def...
Definition: SlotIndexes.h:257
iterator begin()
Definition: LiveInterval.h:205
unsigned getReg() const
getReg - Returns the register number.
VNInfo * getNextValue(SlotIndex def, VNInfo::Allocator &VNInfoAllocator)
getNextValue - Create a new value number and return it.
Definition: LiveInterval.h:306
virtual const TargetInstrInfo * getInstrInfo() const
#define CALL_ONCE_INITIALIZATION(function)
Definition: PassSupport.h:36
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
BasicBlockListType::iterator iterator
#define DEBUG(X)
Definition: Debug.h:92
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:41
iterator FindSegmentContaining(SlotIndex Idx)
Return an iterator to the segment that contains the specified index, or end() if there is none...
Definition: LiveInterval.h:407
bool operator==(uint64_t V1, const APInt &V2)
Definition: APInt.h:1734
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:92
void initializeHexagonExpandCondsetsPass(PassRegistry &)
void registerPass(const PassInfo &PI, bool ShouldFree=false)
registerPass - Register a pass (by means of its PassInfo) with the registry.
MachineInstr::mmo_iterator allocateMemRefsArray(unsigned long Num)
allocateMemRefsArray - Allocate an array to hold MachineMemOperand pointers.
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:340