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Here is a list of all file members with links to the files they belong to:
- v -
v2FromEVEX4of4 :
X86DisassemblerDecoder.h
V4_SA1_addi_BITS :
HexagonDisassembler.cpp
V4_SA1_addi_MASK :
HexagonDisassembler.cpp
V4_SA1_addrx_BITS :
HexagonDisassembler.cpp
V4_SA1_addrx_MASK :
HexagonDisassembler.cpp
V4_SA1_addsp_BITS :
HexagonDisassembler.cpp
V4_SA1_addsp_MASK :
HexagonDisassembler.cpp
V4_SA1_and1_BITS :
HexagonDisassembler.cpp
V4_SA1_and1_MASK :
HexagonDisassembler.cpp
V4_SA1_clrf_BITS :
HexagonDisassembler.cpp
V4_SA1_clrf_MASK :
HexagonDisassembler.cpp
V4_SA1_clrfnew_BITS :
HexagonDisassembler.cpp
V4_SA1_clrfnew_MASK :
HexagonDisassembler.cpp
V4_SA1_clrt_BITS :
HexagonDisassembler.cpp
V4_SA1_clrt_MASK :
HexagonDisassembler.cpp
V4_SA1_clrtnew_BITS :
HexagonDisassembler.cpp
V4_SA1_clrtnew_MASK :
HexagonDisassembler.cpp
V4_SA1_cmpeqi_BITS :
HexagonDisassembler.cpp
V4_SA1_cmpeqi_MASK :
HexagonDisassembler.cpp
V4_SA1_combine0i_BITS :
HexagonDisassembler.cpp
V4_SA1_combine0i_MASK :
HexagonDisassembler.cpp
V4_SA1_combine1i_BITS :
HexagonDisassembler.cpp
V4_SA1_combine1i_MASK :
HexagonDisassembler.cpp
V4_SA1_combine2i_BITS :
HexagonDisassembler.cpp
V4_SA1_combine2i_MASK :
HexagonDisassembler.cpp
V4_SA1_combine3i_BITS :
HexagonDisassembler.cpp
V4_SA1_combine3i_MASK :
HexagonDisassembler.cpp
V4_SA1_combinerz_BITS :
HexagonDisassembler.cpp
V4_SA1_combinerz_MASK :
HexagonDisassembler.cpp
V4_SA1_combinezr_BITS :
HexagonDisassembler.cpp
V4_SA1_combinezr_MASK :
HexagonDisassembler.cpp
V4_SA1_dec_BITS :
HexagonDisassembler.cpp
V4_SA1_dec_MASK :
HexagonDisassembler.cpp
V4_SA1_inc_BITS :
HexagonDisassembler.cpp
V4_SA1_inc_MASK :
HexagonDisassembler.cpp
V4_SA1_seti_BITS :
HexagonDisassembler.cpp
V4_SA1_seti_MASK :
HexagonDisassembler.cpp
V4_SA1_setin1_BITS :
HexagonDisassembler.cpp
V4_SA1_setin1_MASK :
HexagonDisassembler.cpp
V4_SA1_sxtb_BITS :
HexagonDisassembler.cpp
V4_SA1_sxtb_MASK :
HexagonDisassembler.cpp
V4_SA1_sxth_BITS :
HexagonDisassembler.cpp
V4_SA1_sxth_MASK :
HexagonDisassembler.cpp
V4_SA1_tfr_BITS :
HexagonDisassembler.cpp
V4_SA1_tfr_MASK :
HexagonDisassembler.cpp
V4_SA1_zxtb_BITS :
HexagonDisassembler.cpp
V4_SA1_zxtb_MASK :
HexagonDisassembler.cpp
V4_SA1_zxth_BITS :
HexagonDisassembler.cpp
V4_SA1_zxth_MASK :
HexagonDisassembler.cpp
V4_SL1_loadri_io_BITS :
HexagonDisassembler.cpp
V4_SL1_loadri_io_MASK :
HexagonDisassembler.cpp
V4_SL1_loadrub_io_BITS :
HexagonDisassembler.cpp
V4_SL1_loadrub_io_MASK :
HexagonDisassembler.cpp
V4_SL2_deallocframe_BITS :
HexagonDisassembler.cpp
V4_SL2_deallocframe_MASK :
HexagonDisassembler.cpp
V4_SL2_jumpr31_BITS :
HexagonDisassembler.cpp
V4_SL2_jumpr31_f_BITS :
HexagonDisassembler.cpp
V4_SL2_jumpr31_f_MASK :
HexagonDisassembler.cpp
V4_SL2_jumpr31_fnew_BITS :
HexagonDisassembler.cpp
V4_SL2_jumpr31_fnew_MASK :
HexagonDisassembler.cpp
V4_SL2_jumpr31_MASK :
HexagonDisassembler.cpp
V4_SL2_jumpr31_t_BITS :
HexagonDisassembler.cpp
V4_SL2_jumpr31_t_MASK :
HexagonDisassembler.cpp
V4_SL2_jumpr31_tnew_BITS :
HexagonDisassembler.cpp
V4_SL2_jumpr31_tnew_MASK :
HexagonDisassembler.cpp
V4_SL2_loadrb_io_BITS :
HexagonDisassembler.cpp
V4_SL2_loadrb_io_MASK :
HexagonDisassembler.cpp
V4_SL2_loadrd_sp_BITS :
HexagonDisassembler.cpp
V4_SL2_loadrd_sp_MASK :
HexagonDisassembler.cpp
V4_SL2_loadrh_io_BITS :
HexagonDisassembler.cpp
V4_SL2_loadrh_io_MASK :
HexagonDisassembler.cpp
V4_SL2_loadri_sp_BITS :
HexagonDisassembler.cpp
V4_SL2_loadri_sp_MASK :
HexagonDisassembler.cpp
V4_SL2_loadruh_io_BITS :
HexagonDisassembler.cpp
V4_SL2_loadruh_io_MASK :
HexagonDisassembler.cpp
V4_SL2_return_BITS :
HexagonDisassembler.cpp
V4_SL2_return_f_BITS :
HexagonDisassembler.cpp
V4_SL2_return_f_MASK :
HexagonDisassembler.cpp
V4_SL2_return_fnew_BITS :
HexagonDisassembler.cpp
V4_SL2_return_fnew_MASK :
HexagonDisassembler.cpp
V4_SL2_return_MASK :
HexagonDisassembler.cpp
V4_SL2_return_t_BITS :
HexagonDisassembler.cpp
V4_SL2_return_t_MASK :
HexagonDisassembler.cpp
V4_SL2_return_tnew_BITS :
HexagonDisassembler.cpp
V4_SL2_return_tnew_MASK :
HexagonDisassembler.cpp
V4_SS1_storeb_io_BITS :
HexagonDisassembler.cpp
V4_SS1_storeb_io_MASK :
HexagonDisassembler.cpp
V4_SS1_storew_io_BITS :
HexagonDisassembler.cpp
V4_SS1_storew_io_MASK :
HexagonDisassembler.cpp
V4_SS2_allocframe_BITS :
HexagonDisassembler.cpp
V4_SS2_allocframe_MASK :
HexagonDisassembler.cpp
V4_SS2_storebi0_BITS :
HexagonDisassembler.cpp
V4_SS2_storebi0_MASK :
HexagonDisassembler.cpp
V4_SS2_storebi1_BITS :
HexagonDisassembler.cpp
V4_SS2_storebi1_MASK :
HexagonDisassembler.cpp
V4_SS2_stored_sp_BITS :
HexagonDisassembler.cpp
V4_SS2_stored_sp_MASK :
HexagonDisassembler.cpp
V4_SS2_storeh_io_BITS :
HexagonDisassembler.cpp
V4_SS2_storeh_io_MASK :
HexagonDisassembler.cpp
V4_SS2_storew_sp_BITS :
HexagonDisassembler.cpp
V4_SS2_storew_sp_MASK :
HexagonDisassembler.cpp
V4_SS2_storewi0_BITS :
HexagonDisassembler.cpp
V4_SS2_storewi0_MASK :
HexagonDisassembler.cpp
V4_SS2_storewi1_BITS :
HexagonDisassembler.cpp
V4_SS2_storewi1_MASK :
HexagonDisassembler.cpp
ValidLookupTableConstant() :
SimplifyCFG.cpp
ValueDominatesPHI() :
InstructionSimplify.cpp
ValueHasExactlyOneBitSet() :
TargetLowering.cpp
valueHasFloatPrecision() :
SimplifyLibCalls.cpp
ValueIsOnlyUsedLocallyOrStoredToOneGlobal() :
GlobalOpt.cpp
ValuesOverlap() :
SimplifyCFG.cpp
valueToAttrIndex() :
CFLAliasAnalysis.cpp
ValueType :
ScheduleDAGInstrs.cpp
variables :
GlobalMerge.cpp
VARIANT_EQUAL_CASE :
PDBTypes.h
VectorBits :
BBVectorize.cpp
VectorDecoderTable :
AArch64Disassembler.cpp
VectorizationFactor :
LoopAccessAnalysis.cpp
VectorizationInterleave :
LoopAccessAnalysis.cpp
VectorLaneTy :
ARMAsmParser.cpp
VectorZextCombine() :
X86ISelLowering.cpp
verify :
PPCCTRLoops.cpp
Verify :
PPCCTRLoops.cpp
VerifyARMPseudo :
ARMExpandPseudoInsts.cpp
VerifyCoalescing :
RegisterCoalescer.cpp
verifyCTRBranch() :
PPCCTRLoops.cpp
VerifyDebugInfo :
Verifier.cpp
VerifyDomInfo :
Dominators.cpp
VerifyDomInfoX :
Dominators.cpp
VerifyIndvars :
IndVarSimplify.cpp
verifyLeafProcRegUse() :
SparcFrameLowering.cpp
VerifyLoopInfo :
LoopInfo.cpp
VerifyLoopInfoX :
LoopInfo.cpp
VerifyLowRegs() :
Thumb2SizeReduction.cpp
VerifyMachineCode :
Passes.cpp
VerifyMap :
ScalarEvolution.cpp
VerifyNoDeadCode :
SeparateConstOffsetFromGEP.cpp
VerifyPHIs() :
TailDuplication.cpp
VerifyRegAlloc :
RegAllocBase.cpp
VerifyRegionInfoX :
RegionInfo.cpp
VerifySCEV :
ScalarEvolution.cpp
VerifyScheduling :
MachineScheduler.cpp
VerifySDNode() :
SelectionDAG.cpp
VerifySubExpr() :
PHITransAddr.cpp
VerifyVectorType() :
SystemZISelLowering.cpp
VerifyVectorTypes() :
SystemZISelLowering.cpp
VersionPrinterInstance :
CommandLine.cpp
VersOp :
CommandLine.cpp
VI :
AMDGPUInstrInfo.cpp
ViewBackground :
GraphWriter.cpp
ViewBlockFreqPropagationDAG :
BlockFrequencyInfo.cpp
ViewDAGCombine1 :
SelectionDAGISel.cpp
ViewDAGCombine2 :
SelectionDAGISel.cpp
ViewDAGCombineLT :
SelectionDAGISel.cpp
ViewEdgeBundles :
EdgeBundles.cpp
ViewISelDAGs :
SelectionDAGISel.cpp
ViewLegalizeDAGs :
SelectionDAGISel.cpp
ViewLegalizeTypesDAGs :
SelectionDAGISel.cpp
ViewMachineBlockFreqPropagationDAG :
MachineBlockFrequencyInfo.cpp
ViewMISchedDAGs :
MachineScheduler.cpp
ViewSchedDAGs :
SelectionDAGISel.cpp
ViewSUnitDAGs :
SelectionDAGISel.cpp
virtregrewriter :
VirtRegMap.cpp
Visibility :
ELFYAML.cpp
VISIT_MD_FIELDS :
LLParser.cpp
VisitedSDNodeSet :
SelectionDAGDumper.cpp
visitIVCast() :
IndVarSimplify.cpp
visitUDivOperand() :
InstCombineMulDivRem.cpp
VLIWScheduler :
ScheduleDAGVLIW.cpp
vMips16Helper :
Mips16ISelLowering.cpp
VOP3OptionalOps :
AMDGPUAsmParser.cpp
VRegDistCutoff :
HexagonGenInsert.cpp
VRegIndexCutoff :
HexagonGenInsert.cpp
VRegs :
PPCDisassembler.cpp
,
PPCAsmParser.cpp
VRRegNo :
PPCFrameLowering.cpp
VSFRegs :
PPCDisassembler.cpp
,
PPCAsmParser.cpp
VSRegs :
PPCDisassembler.cpp
,
PPCAsmParser.cpp
VSSRegs :
PPCAsmParser.cpp
,
PPCDisassembler.cpp
VST_BBENTRY_6_ABBREV :
BitcodeWriter.cpp
VST_ENTRY_6_ABBREV :
BitcodeWriter.cpp
VST_ENTRY_7_ABBREV :
BitcodeWriter.cpp
VST_ENTRY_8_ABBREV :
BitcodeWriter.cpp
VSXFMAMutateEarly :
PPCTargetMachine.cpp
VSXSelfCopyCrash :
PPCInstrInfo.cpp
VTMutex :
SelectionDAG.cpp
vvvvFromEVEX3of4 :
X86DisassemblerDecoder.h
vvvvFromVEX2of2 :
X86DisassemblerDecoder.h
vvvvFromVEX3of3 :
X86DisassemblerDecoder.h
vvvvFromXOP3of3 :
X86DisassemblerDecoder.h
Generated on Mon Aug 31 2015 11:19:46 for LLVM by
1.8.6