36 InstrItins(I), CurrentState(0), DFAStateInputTable(SIT),
37 DFAStateEntryTable(SET) {}
49 void DFAPacketizer::ReadTable(
unsigned int state) {
50 unsigned ThisState = DFAStateEntryTable[state];
51 unsigned NextStateInTable = DFAStateEntryTable[state+1];
54 if (CachedTable.
count(UnsignPair(state,
55 DFAStateInputTable[ThisState][0])))
58 for (
unsigned i = ThisState; i < NextStateInTable; i++)
59 CachedTable[UnsignPair(state, DFAStateInputTable[i][0])] =
60 DFAStateInputTable[i][1];
70 UnsignPair StateTrans = UnsignPair(CurrentState, FuncUnits);
71 ReadTable(CurrentState);
72 return (CachedTable.
count(StateTrans) != 0);
82 UnsignPair StateTrans = UnsignPair(CurrentState, FuncUnits);
83 ReadTable(CurrentState);
84 assert(CachedTable.
count(StateTrans) != 0);
85 CurrentState = CachedTable[StateTrans];
160 assert(
VLIWScheduler &&
"VLIW Scheduler is not initialized!");
163 std::distance(BeginItr, EndItr));
174 for (; BeginItr != EndItr; ++BeginItr) {
190 assert(SUI &&
"Missing SUnit Info!");
200 assert(SUJ &&
"Missing SUnit Info!");
bool canReserveResources(const llvm::MCInstrDesc *MID)
std::vector< MachineInstr * > CurrentPacketMIs
virtual void finishBlock()
finishBlock - Clean up after scheduling in the given block.
virtual void initPacketizerState()
void buildSchedGraph(AliasAnalysis *AA, RegPressureTracker *RPTracker=nullptr, PressureDiffs *PDiffs=nullptr)
buildSchedGraph - Build SUnits from the MachineBasicBlock that we are input.
Describe properties that are true of each instruction in the target description file.
MachineInstr * getInstr() const
getInstr - Return the representative MachineInstr for this SUnit.
bool CanHandleTerminators
The standard DAG builder does not normally include terminators as DAG nodes because it does not creat...
virtual bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ)
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
virtual void startBlock(MachineBasicBlock *BB)
startBlock - Prepare to perform scheduling in the given block.
void schedule() override
schedule - Order nodes according to selected style, filling in the Sequence member.
virtual bool ignorePseudoInstruction(MachineInstr *I, MachineBasicBlock *MBB)
std::map< MachineInstr *, SUnit * > MIToSUnit
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const InstrStage * beginStage(unsigned ItinClassIndx) const
Return the first stage of the itinerary.
unsigned getUnits() const
Returns the choice of FUs.
DFAPacketizer * ResourceTracker
Itinerary data supplied by a subtarget to be used by a target.
bool IsPostRA
isPostRA flag indicates vregs cannot be present.
void reserveResources(const llvm::MCInstrDesc *MID)
virtual void enterRegion(MachineBasicBlock *bb, MachineBasicBlock::iterator begin, MachineBasicBlock::iterator end, unsigned regioninstrs)
Initialize the scheduler state for the next scheduling region.
virtual DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &) const
Create machine specific model for scheduling.
bundle_iterator< MachineInstr, instr_iterator > iterator
virtual void exitRegion()
Notify that the scheduler has finished scheduling the current region.
const TargetInstrInfo * TII
const MachineLoopInfo * MLI
size_type count(const KeyT &Val) const
Return 1 if the specified key is in the map, 0 otherwise.
virtual bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ)
VLIWPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI, bool IsPostRA)
DFAPacketizer(const InstrItineraryData *I, const int(*SIT)[2], const unsigned *SET)
ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of MachineInstrs. ...
Representation of each machine instruction.
unsigned getSchedClass() const
Return the scheduling class for this instruction.
These values represent a non-pipelined step in the execution of an instruction.
void endPacket(MachineBasicBlock *MBB, MachineInstr *MI)
virtual bool isSoloInstruction(MachineInstr *MI)
virtual ~VLIWPacketizerList()
DefaultVLIWScheduler(MachineFunction &MF, MachineLoopInfo &MLI, bool IsPostRA)
virtual const TargetInstrInfo * getInstrInfo() const
std::vector< SUnit > SUnits
void finalizeBundle(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
finalizeBundle - Finalize a machine instruction bundle which includes a sequence of instructions star...
void PacketizeMIs(MachineBasicBlock *MBB, MachineBasicBlock::iterator BeginItr, MachineBasicBlock::iterator EndItr)
DefaultVLIWScheduler * VLIWScheduler
SUnit - Scheduling unit. This is a node in the scheduling DAG.
virtual MachineBasicBlock::iterator addToPacket(MachineInstr *MI)