14 #ifndef LLVM_LIB_TARGET_XCORE_XCOREINSTRINFO_H
15 #define LLVM_LIB_TARGET_XCORE_XCOREINSTRINFO_H
20 #define GET_INSTRINFO_HEADER
21 #include "XCoreGenInstrInfo.inc"
27 virtual void anchor();
56 bool AllowModify)
const override;
66 unsigned DestReg,
unsigned SrcReg,
67 bool KillSrc)
const override;
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
unsigned RemoveBranch(MachineBasicBlock &MBB) const override
bool ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
ReverseBranchCondition - Return the inverse opcode of the specified Branch instruction.
unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const override
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Reg
All possible values of the reg field in the ModR/M byte.
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, DebugLoc DL) const override
bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
AnalyzeBranch - Analyze the branching code at the end of MBB, returning true if it cannot be understo...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
bundle_iterator - MachineBasicBlock iterator that automatically skips over MIs that are inside bundle...
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
MachineBasicBlock::iterator loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Reg, uint64_t Value) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
const TargetRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot...
Representation of each machine instruction.
LLVM Value Representation.