LLVM  3.7.0
ARMMCTargetDesc.cpp
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1 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides ARM specific target descriptions.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMBaseInfo.h"
15 #include "ARMMCAsmInfo.h"
16 #include "ARMMCTargetDesc.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/MC/MCCodeGenInfo.h"
20 #include "llvm/MC/MCELFStreamer.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/MC/MCStreamer.h"
28 
29 using namespace llvm;
30 
31 #define GET_REGINFO_MC_DESC
32 #include "ARMGenRegisterInfo.inc"
33 
35  std::string &Info) {
36  if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] &&
37  (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) &&
38  (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) &&
39  // Checks for the deprecated CP15ISB encoding:
40  // mcr p15, #0, rX, c7, c5, #4
41  (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) {
42  if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) {
43  if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) {
44  Info = "deprecated since v7, use 'isb'";
45  return true;
46  }
47 
48  // Checks for the deprecated CP15DSB encoding:
49  // mcr p15, #0, rX, c7, c10, #4
50  if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) {
51  Info = "deprecated since v7, use 'dsb'";
52  return true;
53  }
54  }
55  // Checks for the deprecated CP15DMB encoding:
56  // mcr p15, #0, rX, c7, c10, #5
57  if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 &&
58  (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) {
59  Info = "deprecated since v7, use 'dmb'";
60  return true;
61  }
62  }
63  return false;
64 }
65 
66 static bool getITDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
67  std::string &Info) {
68  if (STI.getFeatureBits()[llvm::ARM::HasV8Ops] && MI.getOperand(1).isImm() &&
69  MI.getOperand(1).getImm() != 8) {
70  Info = "applying IT instruction to more than one subsequent instruction is "
71  "deprecated";
72  return true;
73  }
74 
75  return false;
76 }
77 
79  std::string &Info) {
80  assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
81  "cannot predicate thumb instructions");
82 
83  assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
84  for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) {
85  assert(MI.getOperand(OI).isReg() && "expected register");
86  if (MI.getOperand(OI).getReg() == ARM::SP ||
87  MI.getOperand(OI).getReg() == ARM::PC) {
88  Info = "use of SP or PC in the list is deprecated";
89  return true;
90  }
91  }
92  return false;
93 }
94 
96  std::string &Info) {
97  assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
98  "cannot predicate thumb instructions");
99 
100  assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
101  bool ListContainsPC = false, ListContainsLR = false;
102  for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) {
103  assert(MI.getOperand(OI).isReg() && "expected register");
104  switch (MI.getOperand(OI).getReg()) {
105  default:
106  break;
107  case ARM::LR:
108  ListContainsLR = true;
109  break;
110  case ARM::PC:
111  ListContainsPC = true;
112  break;
113  case ARM::SP:
114  Info = "use of SP in the list is deprecated";
115  return true;
116  }
117  }
118 
119  if (ListContainsPC && ListContainsLR) {
120  Info = "use of LR and PC simultaneously in the list is deprecated";
121  return true;
122  }
123 
124  return false;
125 }
126 
127 #define GET_INSTRINFO_MC_DESC
128 #include "ARMGenInstrInfo.inc"
129 
130 #define GET_SUBTARGETINFO_MC_DESC
131 #include "ARMGenSubtargetInfo.inc"
132 
133 std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) {
134  bool isThumb =
135  TT.getArch() == Triple::thumb || TT.getArch() == Triple::thumbeb;
136 
137  bool NoCPU = CPU == "generic" || CPU.empty();
138  std::string ARMArchFeature;
139  switch (TT.getSubArch()) {
140  default:
141  llvm_unreachable("invalid sub-architecture for ARM");
143  if (NoCPU)
144  // v8a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2,
145  // FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone,
146  // FeatureT2XtPk, FeatureCrypto, FeatureCRC
147  ARMArchFeature = "+v8,+db,+fp-armv8,+neon,+t2dsp,+mp,+hwdiv,+hwdiv-arm,"
148  "+trustzone,+t2xtpk,+crypto,+crc";
149  else
150  // Use CPU to figure out the exact features
151  ARMArchFeature = "+v8";
152  break;
154  if (NoCPU)
155  // v8.1a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2,
156  // FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone,
157  // FeatureT2XtPk, FeatureCrypto, FeatureCRC, FeatureV8_1a
158  ARMArchFeature = "+v8.1a,+db,+fp-armv8,+neon,+t2dsp,+mp,+hwdiv,+hwdiv-arm,"
159  "+trustzone,+t2xtpk,+crypto,+crc";
160  else
161  // Use CPU to figure out the exact features
162  ARMArchFeature = "+v8.1a";
163  break;
165  isThumb = true;
166  if (NoCPU)
167  // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
168  ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass";
169  else
170  // Use CPU to figure out the exact features.
171  ARMArchFeature = "+v7";
172  break;
174  if (NoCPU)
175  // v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
176  // FeatureT2XtPk, FeatureMClass
177  ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,+t2xtpk,+mclass";
178  else
179  // Use CPU to figure out the exact features.
180  ARMArchFeature = "+v7";
181  break;
183  if (NoCPU)
184  // v7s: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureHasRAS
185  // Swift
186  ARMArchFeature = "+v7,+swift,+neon,+db,+t2dsp,+ras";
187  else
188  // Use CPU to figure out the exact features.
189  ARMArchFeature = "+v7";
190  break;
192  // v7 CPUs have lots of different feature sets. If no CPU is specified,
193  // then assume v7a (e.g. cortex-a8) feature set. Otherwise, return
194  // the "minimum" feature set and use CPU string to figure out the exact
195  // features.
196  if (NoCPU)
197  // v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
198  ARMArchFeature = "+v7,+neon,+db,+t2dsp,+t2xtpk";
199  else
200  // Use CPU to figure out the exact features.
201  ARMArchFeature = "+v7";
202  break;
204  ARMArchFeature = "+v6t2";
205  break;
207  ARMArchFeature = "+v6k";
208  break;
210  isThumb = true;
211  if (NoCPU)
212  // v6m: FeatureNoARM, FeatureMClass
213  ARMArchFeature = "+v6m,+noarm,+mclass";
214  else
215  ARMArchFeature = "+v6";
216  break;
218  ARMArchFeature = "+v6";
219  break;
221  ARMArchFeature = "+v5te";
222  break;
224  ARMArchFeature = "+v5t";
225  break;
227  ARMArchFeature = "+v4t";
228  break;
229  case Triple::NoSubArch:
230  break;
231  }
232 
233  if (isThumb) {
234  if (ARMArchFeature.empty())
235  ARMArchFeature = "+thumb-mode";
236  else
237  ARMArchFeature += ",+thumb-mode";
238  }
239 
240  if (TT.isOSNaCl()) {
241  if (ARMArchFeature.empty())
242  ARMArchFeature = "+nacl-trap";
243  else
244  ARMArchFeature += ",+nacl-trap";
245  }
246 
247  return ARMArchFeature;
248 }
249 
251  StringRef CPU, StringRef FS) {
252  std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
253  if (!FS.empty()) {
254  if (!ArchFS.empty())
255  ArchFS = (Twine(ArchFS) + "," + FS).str();
256  else
257  ArchFS = FS;
258  }
259 
260  return createARMMCSubtargetInfoImpl(TT, CPU, ArchFS);
261 }
262 
264  MCInstrInfo *X = new MCInstrInfo();
265  InitARMMCInstrInfo(X);
266  return X;
267 }
268 
271  InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
272  return X;
273 }
274 
276  const Triple &TheTriple) {
277  MCAsmInfo *MAI;
278  if (TheTriple.isOSDarwin() || TheTriple.isOSBinFormatMachO())
279  MAI = new ARMMCAsmInfoDarwin(TheTriple);
280  else if (TheTriple.isWindowsMSVCEnvironment())
281  MAI = new ARMCOFFMCAsmInfoMicrosoft();
282  else if (TheTriple.isOSWindows())
283  MAI = new ARMCOFFMCAsmInfoGNU();
284  else
285  MAI = new ARMELFMCAsmInfo(TheTriple);
286 
287  unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true);
289 
290  return MAI;
291 }
292 
294  CodeModel::Model CM,
295  CodeGenOpt::Level OL) {
296  MCCodeGenInfo *X = new MCCodeGenInfo();
297  if (RM == Reloc::Default) {
298  // Default relocation model on Darwin is PIC, not DynamicNoPIC.
300  }
301  X->initMCCodeGenInfo(RM, CM, OL);
302  return X;
303 }
304 
307  MCCodeEmitter *Emitter, bool RelaxAll) {
308  return createARMELFStreamer(Ctx, MAB, OS, Emitter, false,
309  T.getArch() == Triple::thumb);
310 }
311 
313  raw_pwrite_stream &OS,
314  MCCodeEmitter *Emitter, bool RelaxAll,
315  bool DWARFMustBeAtTheEnd) {
316  return createMachOStreamer(Ctx, MAB, OS, Emitter, false, DWARFMustBeAtTheEnd);
317 }
318 
320  unsigned SyntaxVariant,
321  const MCAsmInfo &MAI,
322  const MCInstrInfo &MII,
323  const MCRegisterInfo &MRI) {
324  if (SyntaxVariant == 0)
325  return new ARMInstPrinter(MAI, MII, MRI);
326  return nullptr;
327 }
328 
330  MCContext &Ctx) {
331  if (TT.isOSBinFormatMachO())
332  return createARMMachORelocationInfo(Ctx);
333  // Default to the stock relocation info.
334  return llvm::createMCRelocationInfo(TT, Ctx);
335 }
336 
337 namespace {
338 
339 class ARMMCInstrAnalysis : public MCInstrAnalysis {
340 public:
341  ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
342 
343  bool isUnconditionalBranch(const MCInst &Inst) const override {
344  // BCCs with the "always" predicate are unconditional branches.
345  if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
346  return true;
348  }
349 
350  bool isConditionalBranch(const MCInst &Inst) const override {
351  // BCCs with the "always" predicate are unconditional branches.
352  if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
353  return false;
355  }
356 
357  bool evaluateBranch(const MCInst &Inst, uint64_t Addr,
358  uint64_t Size, uint64_t &Target) const override {
359  // We only handle PCRel branches for now.
360  if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
361  return false;
362 
363  int64_t Imm = Inst.getOperand(0).getImm();
364  // FIXME: This is not right for thumb.
365  Target = Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.
366  return true;
367  }
368 };
369 
370 }
371 
373  return new ARMMCInstrAnalysis(Info);
374 }
375 
376 // Force static initialization.
377 extern "C" void LLVMInitializeARMTargetMC() {
378  for (Target *T : {&TheARMLETarget, &TheARMBETarget, &TheThumbLETarget,
379  &TheThumbBETarget}) {
380  // Register the MC asm info.
382 
383  // Register the MC codegen info.
385 
386  // Register the MC instruction info.
388 
389  // Register the MC register info.
391 
392  // Register the MC subtarget info.
395 
396  // Register the MC instruction analyzer.
398 
402 
403  // Register the obj target streamer.
406 
407  // Register the asm streamer.
409 
410  // Register the null TargetStreamer.
412 
413  // Register the MCInstPrinter.
415 
416  // Register the MC relocation info.
418  }
419 
420  // Register the MC Code Emitter
421  for (Target *T : {&TheARMLETarget, &TheThumbLETarget})
423  for (Target *T : {&TheARMBETarget, &TheThumbBETarget})
425 
426  // Register the asm backend.
433 }
Target TheThumbLETarget
MCELFStreamer * createARMELFStreamer(MCContext &Context, MCAsmBackend &TAB, raw_pwrite_stream &OS, MCCodeEmitter *Emitter, bool RelaxAll, bool IsThumb)
static bool isUnconditionalBranch(unsigned int Opcode)
static MCStreamer * createARMMachOStreamer(MCContext &Ctx, MCAsmBackend &MAB, raw_pwrite_stream &OS, MCCodeEmitter *Emitter, bool RelaxAll, bool DWARFMustBeAtTheEnd)
int getDwarfRegNum(unsigned RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:489
bool isReg() const
Definition: MCInst.h:56
static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)
RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target...
static MCInstrInfo * createARMMCInstrInfo()
static bool getITDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info)
MCRelocationInfo * createARMMachORelocationInfo(MCContext &Ctx)
Construct ARM Mach-O relocation info.
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.
void LLVMInitializeARMTargetMC()
static bool isThumb(const MCSubtargetInfo &STI)
static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:464
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:79
MCStreamer * createARMWinCOFFStreamer(MCContext &Context, MCAsmBackend &MAB, raw_pwrite_stream &OS, MCCodeEmitter *Emitter, bool RelaxAll)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
Reg
All possible values of the reg field in the ModR/M byte.
static void RegisterCOFFStreamer(Target &T, Target::COFFStreamerCtorTy Fn)
static MCInstPrinter * createARMMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
bool isWindowsMSVCEnvironment() const
Definition: Triple.h:430
Context object for machine code objects.
Definition: MCContext.h:48
MCAsmBackend * createARMLEAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU)
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:63
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
Definition: Triple.h:469
MCAsmBackend * createThumbBEAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU)
void addInitialFrameState(const MCCFIInstruction &Inst)
Definition: MCAsmInfo.h:534
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Definition: Triple.h:242
MCTargetStreamer * createARMTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, bool isVerboseAsm)
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:150
MCRelocationInfo * createMCRelocationInfo(const Triple &TT, MCContext &Ctx)
SubArchType getSubArch() const
getSubArch - get the parsed subarchitecture type for this triple.
Definition: Triple.h:245
virtual bool isUnconditionalBranch(const MCInst &Inst) const
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
bool isImm() const
Definition: MCInst.h:57
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:58
static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.
MCTargetStreamer * createARMObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
static MCRegisterInfo * createARMMCRegisterInfo(const Triple &Triple)
Streaming machine code generation interface.
Definition: MCStreamer.h:157
static MCCFIInstruction createDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it...
Definition: MCDwarf.h:354
static void RegisterMachOStreamer(Target &T, Target::MachOStreamerCtorTy Fn)
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:23
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang","erlang-compatible garbage collector")
Create MCExprs from relocations found in an object file.
static void RegisterMCCodeGenInfo(Target &T, Target::MCCodeGenInfoCtorFnTy Fn)
RegisterMCCodeGenInfo - Register a MCCodeGenInfo implementation for the given target.
MCSubtargetInfo * createARMMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Create a ARM MCSubtargetInfo instance.
static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target...
static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)
static bool getARMLoadDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info)
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X or iOS).
Definition: Triple.h:404
virtual bool isConditionalBranch(const MCInst &Inst) const
static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.
MCStreamer * createELFStreamer(MCContext &Ctx, MCAsmBackend &TAB, raw_pwrite_stream &OS, MCCodeEmitter *CE, bool RelaxAll)
Takes ownership of TAB and CE.
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.
unsigned getOpcode() const
Definition: MCInst.h:159
Target - Wrapper for Target specific information.
static bool getMCRDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info)
static MCCodeGenInfo * createARMMCCodeGenInfo(const Triple &TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL)
int64_t getImm() const
Definition: MCInst.h:74
MCCodeEmitter * createARMLEMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
RegisterMCAsmInfoFn - Helper template for registering a target assembly info implementation.
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:38
OperandType
Types of operands to CF instructions.
void initMCCodeGenInfo(Reloc::Model RM=Reloc::Default, CodeModel::Model CM=CodeModel::Default, CodeGenOpt::Level OL=CodeGenOpt::Default)
unsigned getNumOperands() const
Definition: MCInst.h:166
static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)
RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target. ...
Target TheThumbBETarget
Target TheARMLETarget
MCSubtargetInfo - Generic base class for all target subtargets.
static MCAsmInfo * createARMMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TheTriple)
static void RegisterELFStreamer(Target &T, Target::ELFStreamerCtorTy Fn)
Target TheARMBETarget
static MCInstrAnalysis * createARMMCInstrAnalysis(const MCInstrInfo *Info)
An abstract base class for streams implementations that also support a pwrite operation.
Definition: raw_ostream.h:321
MCTargetStreamer * createARMNullTargetStreamer(MCStreamer &S)
cl::opt< bool > RelaxAll("mc-relax-all", cl::desc("When used with filetype=obj, ""relax all fixups in the emitted object file"))
static bool isConditionalBranch(unsigned Opc)
MCStreamer * createMachOStreamer(MCContext &Ctx, MCAsmBackend &TAB, raw_pwrite_stream &OS, MCCodeEmitter *CE, bool RelaxAll, bool DWARFMustBeAtTheEnd, bool LabelSections=false)
MCAsmBackend * createThumbLEAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU)
static void RegisterNullTargetStreamer(Target &T, Target::NullTargetStreamerCtorTy Fn)
MCAsmBackend * createARMBEAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU)
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:34
std::string ParseARMTriple(const Triple &TT, StringRef CPU)
static void RegisterMCRelocationInfo(Target &T, Target::MCRelocationInfoCtorTy Fn)
RegisterMCRelocationInfo - Register an MCRelocationInfo implementation for the given target...
static MCRelocationInfo * createARMMCRelocationInfo(const Triple &TT, MCContext &Ctx)
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:40
static bool getARMStoreDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info)
MCCodeEmitter * createARMBEMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:164
bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:110