51 #define DEBUG_TYPE "aarch64-simd-scalar"
57 cl::desc(
"Force use of AdvSIMD scalar instructions everywhere"),
60 STATISTIC(NumScalarInsnsUsed,
"Number of scalar instructions used");
61 STATISTIC(NumCopiesDeleted,
"Number of cross-class copies deleted");
62 STATISTIC(NumCopiesInserted,
"Number of cross-class copies inserted");
89 const char *getPassName()
const override {
90 return "AdvSIMD Scalar Operation Optimization";
107 return AArch64::GPR64RegClass.contains(Reg);
116 SubReg == AArch64::dsub);
118 return (AArch64::FPR64RegClass.
contains(Reg) && SubReg == 0) ||
119 (AArch64::FPR128RegClass.
contains(Reg) && SubReg == AArch64::dsub);
129 if (MI->
getOpcode() == AArch64::FMOVDXr ||
135 SubReg = AArch64::dsub;
166 case AArch64::ADDXrr:
167 return AArch64::ADDv1i64;
168 case AArch64::SUBXrr:
169 return AArch64::SUBv1i64;
170 case AArch64::ANDXrr:
171 return AArch64::ANDv8i8;
172 case AArch64::EORXrr:
173 return AArch64::EORv8i8;
174 case AArch64::ORRXrr:
175 return AArch64::ORRv8i8;
190 AArch64AdvSIMDScalar::isProfitableToTransform(
const MachineInstr *
MI)
const {
198 unsigned NumNewCopies = 3;
199 unsigned NumRemovableCopies = 0;
203 unsigned Src0 = 0, SubReg0;
204 unsigned Src1 = 0, SubReg1;
205 if (!MRI->def_empty(OrigSrc0)) {
207 MRI->def_instr_begin(OrigSrc0);
208 assert(std::next(Def) == MRI->def_instr_end() &&
"Multiple def in SSA!");
215 if (Src0 && MRI->hasOneNonDBGUse(OrigSrc0))
216 ++NumRemovableCopies;
218 if (!MRI->def_empty(OrigSrc1)) {
220 MRI->def_instr_begin(OrigSrc1);
221 assert(std::next(Def) == MRI->def_instr_end() &&
"Multiple def in SSA!");
227 if (Src1 && MRI->hasOneNonDBGUse(OrigSrc1))
228 ++NumRemovableCopies;
237 bool AllUsesAreCopies =
true;
239 Use = MRI->use_instr_nodbg_begin(Dst),
240 E = MRI->use_instr_nodbg_end();
244 ++NumRemovableCopies;
251 Use->getOpcode() == AArch64::INSvi64gpr)
254 AllUsesAreCopies =
false;
258 if (AllUsesAreCopies)
263 if (NumNewCopies <= NumRemovableCopies)
272 unsigned Dst,
unsigned Src,
bool IsKill) {
277 DEBUG(
dbgs() <<
" adding copy: " << *MIB);
285 void AArch64AdvSIMDScalar::transformInstruction(
MachineInstr *MI) {
286 DEBUG(
dbgs() <<
"Scalar transform: " << *MI);
291 assert(OldOpc != NewOpc &&
"transform an instruction to itself?!");
296 unsigned Src0 = 0, SubReg0;
297 unsigned Src1 = 0, SubReg1;
298 if (!MRI->def_empty(OrigSrc0)) {
300 MRI->def_instr_begin(OrigSrc0);
301 assert(std::next(Def) == MRI->def_instr_end() &&
"Multiple def in SSA!");
305 if (Src0 && MRI->hasOneNonDBGUse(OrigSrc0)) {
306 assert(Src0 &&
"Can't delete copy w/o a valid original source!");
311 if (!MRI->def_empty(OrigSrc1)) {
313 MRI->def_instr_begin(OrigSrc1);
314 assert(std::next(Def) == MRI->def_instr_end() &&
"Multiple def in SSA!");
318 if (Src1 && MRI->hasOneNonDBGUse(OrigSrc1)) {
319 assert(Src1 &&
"Can't delete copy w/o a valid original source!");
328 Src0 = MRI->createVirtualRegister(&AArch64::FPR64RegClass);
333 Src1 = MRI->createVirtualRegister(&AArch64::FPR64RegClass);
340 unsigned Dst = MRI->createVirtualRegister(&AArch64::FPR64RegClass);
357 ++NumScalarInsnsUsed;
362 bool Changed =
false;
366 if (isProfitableToTransform(MI)) {
367 transformInstruction(MI);
376 bool Changed =
false;
377 DEBUG(
dbgs() <<
"***** AArch64AdvSIMDScalar *****\n");
384 if (processMachineBasicBlock(
I))
392 return new AArch64AdvSIMDScalar();
STATISTIC(NumFunctions,"Total number of functions")
static unsigned getSrcFromCopy(const MachineInstr *MI, const MachineRegisterInfo *MRI, unsigned &SubReg)
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
bool hasSuperClassEq(const TargetRegisterClass *RC) const
hasSuperClassEq - Returns true if RC is a super-class of or equal to this class.
static bool isTransformable(const MachineInstr *MI)
COPY - Target-independent register copy.
static bool isFPR64(unsigned Reg, unsigned SubReg, const MachineRegisterInfo *MRI)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
A Use represents the edge between a Value definition and its users.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
const TargetRegisterClass * getRegClass(unsigned Reg) const
getRegClass - Return the register class of the specified virtual register.
Reg
All possible values of the reg field in the ModR/M byte.
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
defusechain_iterator - This class provides iterator support for machine operands in the function that...
unsigned getKillRegState(bool B)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineBasicBlock * getParent() const
TargetInstrInfo - Interface to description of machine instruction set.
bundle_iterator< MachineInstr, instr_iterator > iterator
initializer< Ty > init(const Ty &Val)
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
static cl::opt< bool > TransformAll("aarch64-simd-scalar-force-all", cl::desc("Force use of AdvSIMD scalar instructions everywhere"), cl::init(false), cl::Hidden)
const MachineOperand & getOperand(unsigned i) const
INSERT_SUBREG - This instruction takes three operands: a register that has subregisters, a register providing an insert value, and a subregister index.
Represent the analysis usage information of a pass.
FunctionPass * createAArch64AdvSIMDScalar()
static unsigned getTransformOpcode(unsigned Opc)
FunctionPass class - This class is used to implement most global optimizations.
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
unsigned getSubReg() const
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
void setPreservesCFG()
This function should be called by the pass, iff they do not:
static MachineInstr * insertCopy(const TargetInstrInfo *TII, MachineInstr *MI, unsigned Dst, unsigned Src, bool IsKill)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
unsigned getReg() const
getReg - Returns the register number.
virtual const TargetInstrInfo * getInstrInfo() const
BasicBlockListType::iterator iterator
static bool isGPR64(unsigned Reg, unsigned SubReg, const MachineRegisterInfo *MRI)