LLVM  3.7.0
TargetParser.h
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1 //===-- TargetParser - Parser for target features ---------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements a target parser to recognise hardware features such as
11 // FPU/CPU/ARCH names as well as specific support such as HDIV, etc.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_SUPPORT_TARGETPARSER_H
16 #define LLVM_SUPPORT_TARGETPARSER_H
17 
18 // FIXME: vector is used because that's what clang uses for subtarget feature
19 // lists, but SmallVector would probably be better
20 #include <vector>
21 
22 namespace llvm {
23  class StringRef;
24 
25 // Target specific information into their own namespaces. These should be
26 // generated from TableGen because the information is already there, and there
27 // is where new information about targets will be added.
28 // FIXME: To TableGen this we need to make some table generated files available
29 // even if the back-end is not compiled with LLVM, plus we need to create a new
30 // back-end to TableGen to create these clean tables.
31 namespace ARM {
32  // FPU names.
33  enum FPUKind {
57  };
58 
59  // FPU Version
60  enum FPUVersion {
61  FV_NONE = 0,
67  };
68 
69  // An FPU name implies one of three levels of Neon support:
71  NS_None = 0, ///< No Neon
72  NS_Neon, ///< Neon
73  NS_Crypto ///< Neon with Crypto
74  };
75 
76  // An FPU name restricts the FPU in one of three ways:
78  FR_None = 0, ///< No restriction
79  FR_D16, ///< Only 16 D registers
80  FR_SP_D16 ///< Only single-precision instructions, with 16 D registers
81  };
82 
83  // Arch names.
84  enum ArchKind {
108  // Non-standard Arch names.
121  };
122 
123  // Arch extension modifiers for CPUs.
124  enum ArchExtKind {
134  // Unsupported extensions.
141  };
142 
143  // ISA kinds.
144  enum ISAKind {
149  };
150 
151  // Endianness
152  // FIXME: BE8 vs. BE32?
153  enum EndianKind {
157  };
158 
159  // v6/v7/v8 Profile
160  enum ProfileKind {
165  };
166 } // namespace ARM
167 
168 // Target Parsers, one per architecture.
170  static StringRef getFPUSynonym(StringRef FPU);
171  static StringRef getArchSynonym(StringRef Arch);
172 
173 public:
175 
176  // Information by ID
177  static const char * getFPUName(unsigned FPUKind);
178  static unsigned getFPUVersion(unsigned FPUKind);
179  static unsigned getFPUNeonSupportLevel(unsigned FPUKind);
180  static unsigned getFPURestriction(unsigned FPUKind);
181  // FIXME: This should be moved to TargetTuple once it exists
182  static bool getFPUFeatures(unsigned FPUKind,
183  std::vector<const char*> &Features);
184  static const char * getArchName(unsigned ArchKind);
185  static unsigned getArchAttr(unsigned ArchKind);
186  static const char * getCPUAttr(unsigned ArchKind);
187  static const char * getSubArch(unsigned ArchKind);
188  static const char * getArchExtName(unsigned ArchExtKind);
189  static const char * getDefaultCPU(StringRef Arch);
190 
191  // Parser
192  static unsigned parseFPU(StringRef FPU);
193  static unsigned parseArch(StringRef Arch);
194  static unsigned parseArchExt(StringRef ArchExt);
195  static unsigned parseCPUArch(StringRef CPU);
196  static unsigned parseArchISA(StringRef Arch);
197  static unsigned parseArchEndian(StringRef Arch);
198  static unsigned parseArchProfile(StringRef Arch);
199  static unsigned parseArchVersion(StringRef Arch);
200 
201 };
202 
203 } // namespace llvm
204 
205 #endif
static unsigned getFPUVersion(unsigned FPUKind)
static unsigned parseCPUArch(StringRef CPU)
static unsigned parseArch(StringRef Arch)
static unsigned parseArchExt(StringRef ArchExt)
static const char * getSubArch(unsigned ArchKind)
const FeatureBitset Features
static unsigned parseFPU(StringRef FPU)
static bool getFPUFeatures(unsigned FPUKind, std::vector< const char * > &Features)
Only single-precision instructions, with 16 D registers.
Definition: TargetParser.h:80
Only 16 D registers.
Definition: TargetParser.h:79
static const char * getDefaultCPU(StringRef Arch)
static unsigned getArchAttr(unsigned ArchKind)
static unsigned parseArchVersion(StringRef Arch)
static const char * getCPUAttr(unsigned ArchKind)
static unsigned getFPUNeonSupportLevel(unsigned FPUKind)
static unsigned parseArchEndian(StringRef Arch)
static const char * getFPUName(unsigned FPUKind)
Neon with Crypto.
Definition: TargetParser.h:73
static const char * getArchExtName(unsigned ArchExtKind)
No restriction.
Definition: TargetParser.h:78
static unsigned parseArchProfile(StringRef Arch)
static unsigned parseArchISA(StringRef Arch)
static const char * getArchName(unsigned ArchKind)
static unsigned getFPURestriction(unsigned FPUKind)
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:40
static StringRef getCanonicalArchName(StringRef Arch)