LLVM  3.7.0
R600InstrInfo.h
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1 //===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief Interface definition for R600InstrInfo
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_R600_R600INSTRINFO_H
16 #define LLVM_LIB_TARGET_R600_R600INSTRINFO_H
17 
18 #include "AMDGPUInstrInfo.h"
19 #include "R600Defines.h"
20 #include "R600RegisterInfo.h"
21 #include <map>
22 
23 namespace llvm {
24 
25  class AMDGPUTargetMachine;
26  class DFAPacketizer;
27  class ScheduleDAG;
28  class MachineFunction;
29  class MachineInstr;
30  class MachineInstrBuilder;
31 
32  class R600InstrInfo : public AMDGPUInstrInfo {
33  private:
34  const R600RegisterInfo RI;
35 
36  std::vector<std::pair<int, unsigned> >
37  ExtractSrcs(MachineInstr *MI, const DenseMap<unsigned, unsigned> &PV, unsigned &ConstCount) const;
38 
39 
40  MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
42  unsigned ValueReg, unsigned Address,
43  unsigned OffsetReg,
44  unsigned AddrChan) const;
45 
46  MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
48  unsigned ValueReg, unsigned Address,
49  unsigned OffsetReg,
50  unsigned AddrChan) const;
51  public:
52  enum BankSwizzle {
59  };
60 
61  explicit R600InstrInfo(const AMDGPUSubtarget &st);
62 
63  const R600RegisterInfo &getRegisterInfo() const override;
66  unsigned DestReg, unsigned SrcReg,
67  bool KillSrc) const override;
69  MachineBasicBlock::iterator MBBI) const override;
70 
71  bool isTrig(const MachineInstr &MI) const;
72  bool isPlaceHolderOpcode(unsigned opcode) const;
73  bool isReductionOp(unsigned opcode) const;
74  bool isCubeOp(unsigned opcode) const;
75 
76  /// \returns true if this \p Opcode represents an ALU instruction.
77  bool isALUInstr(unsigned Opcode) const;
78  bool hasInstrModifiers(unsigned Opcode) const;
79  bool isLDSInstr(unsigned Opcode) const;
80  bool isLDSNoRetInstr(unsigned Opcode) const;
81  bool isLDSRetInstr(unsigned Opcode) const;
82 
83  /// \returns true if this \p Opcode represents an ALU instruction or an
84  /// instruction that will be lowered in ExpandSpecialInstrs Pass.
85  bool canBeConsideredALU(const MachineInstr *MI) const;
86 
87  bool isTransOnly(unsigned Opcode) const;
88  bool isTransOnly(const MachineInstr *MI) const;
89  bool isVectorOnly(unsigned Opcode) const;
90  bool isVectorOnly(const MachineInstr *MI) const;
91  bool isExport(unsigned Opcode) const;
92 
93  bool usesVertexCache(unsigned Opcode) const;
94  bool usesVertexCache(const MachineInstr *MI) const;
95  bool usesTextureCache(unsigned Opcode) const;
96  bool usesTextureCache(const MachineInstr *MI) const;
97 
98  bool mustBeLastInClause(unsigned Opcode) const;
99  bool usesAddressRegister(MachineInstr *MI) const;
100  bool definesAddressRegister(MachineInstr *MI) const;
101  bool readsLDSSrcReg(const MachineInstr *MI) const;
102 
103  /// \returns The operand index for the given source number. Legal values
104  /// for SrcNum are 0, 1, and 2.
105  int getSrcIdx(unsigned Opcode, unsigned SrcNum) const;
106  /// \returns The operand Index for the Sel operand given an index to one
107  /// of the instruction's src operands.
108  int getSelIdx(unsigned Opcode, unsigned SrcIdx) const;
109 
110  /// \returns a pair for each src of an ALU instructions.
111  /// The first member of a pair is the register id.
112  /// If register is ALU_CONST, second member is SEL.
113  /// If register is ALU_LITERAL, second member is IMM.
114  /// Otherwise, second member value is undefined.
116  getSrcs(MachineInstr *MI) const;
117 
118  unsigned isLegalUpTo(
119  const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
120  const std::vector<R600InstrInfo::BankSwizzle> &Swz,
121  const std::vector<std::pair<int, unsigned> > &TransSrcs,
122  R600InstrInfo::BankSwizzle TransSwz) const;
123 
125  const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
126  std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
127  const std::vector<std::pair<int, unsigned> > &TransSrcs,
128  R600InstrInfo::BankSwizzle TransSwz) const;
129 
130  /// Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210
131  /// returns true and the first (in lexical order) BankSwizzle affectation
132  /// starting from the one already provided in the Instruction Group MIs that
133  /// fits Read Port limitations in BS if available. Otherwise returns false
134  /// and undefined content in BS.
135  /// isLastAluTrans should be set if the last Alu of MIs will be executed on
136  /// Trans ALU. In this case, ValidTSwizzle returns the BankSwizzle value to
137  /// apply to the last instruction.
138  /// PV holds GPR to PV registers in the Instruction Group MIs.
139  bool fitsReadPortLimitations(const std::vector<MachineInstr *> &MIs,
141  std::vector<BankSwizzle> &BS,
142  bool isLastAluTrans) const;
143 
144  /// An instruction group can only access 2 channel pair (either [XY] or [ZW])
145  /// from KCache bank on R700+. This function check if MI set in input meet
146  /// this limitations
147  bool fitsConstReadLimitations(const std::vector<MachineInstr *> &) const;
148  /// Same but using const index set instead of MI set.
149  bool fitsConstReadLimitations(const std::vector<unsigned>&) const;
150 
151  /// \brief Vector instructions are instructions that must fill all
152  /// instruction slots within an instruction group.
153  bool isVector(const MachineInstr &MI) const;
154 
155  bool isMov(unsigned Opcode) const override;
156 
157  DFAPacketizer *
158  CreateTargetScheduleState(const TargetSubtargetInfo &) const override;
159 
160  bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
161 
163  SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const override;
164 
167  DebugLoc DL) const override;
168 
169  unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
170 
171  bool isPredicated(const MachineInstr *MI) const override;
172 
173  bool isPredicable(MachineInstr *MI) const override;
174 
175  bool
176  isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
177  const BranchProbability &Probability) const override;
178 
179  bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
180  unsigned ExtraPredCycles,
181  const BranchProbability &Probability) const override ;
182 
183  bool
185  unsigned NumTCycles, unsigned ExtraTCycles,
186  MachineBasicBlock &FMBB,
187  unsigned NumFCycles, unsigned ExtraFCycles,
188  const BranchProbability &Probability) const override;
189 
191  std::vector<MachineOperand> &Pred) const override;
192 
194  ArrayRef<MachineOperand> Pred2) const override;
195 
197  MachineBasicBlock &FMBB) const override;
198 
200  ArrayRef<MachineOperand> Pred) const override;
201 
202  unsigned int getPredicationCost(const MachineInstr *) const override;
203 
204  unsigned int getInstrLatency(const InstrItineraryData *ItinData,
205  const MachineInstr *MI,
206  unsigned *PredCost = nullptr) const override;
207 
208  int getInstrLatency(const InstrItineraryData *ItinData,
209  SDNode *Node) const override { return 1;}
210 
211  bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
212 
213  /// \brief Reserve the registers that may be accesed using indirect addressing.
215  const MachineFunction &MF) const;
216 
217  unsigned calculateIndirectAddress(unsigned RegIndex,
218  unsigned Channel) const override;
219 
220  const TargetRegisterClass *getIndirectAddrRegClass() const override;
221 
222  MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
224  unsigned ValueReg, unsigned Address,
225  unsigned OffsetReg) const override;
226 
227  MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
229  unsigned ValueReg, unsigned Address,
230  unsigned OffsetReg) const override;
231 
232  unsigned getMaxAlusPerClause() const;
233 
234  ///buildDefaultInstruction - This function returns a MachineInstr with
235  /// all the instruction modifiers initialized to their default values.
236  /// You can use this function to avoid manually specifying each instruction
237  /// modifier operand when building a new instruction.
238  ///
239  /// \returns a MachineInstr with all the instruction modifiers initialized
240  /// to their default values.
243  unsigned Opcode,
244  unsigned DstReg,
245  unsigned Src0Reg,
246  unsigned Src1Reg = 0) const;
247 
249  MachineInstr *MI,
250  unsigned Slot,
251  unsigned DstReg) const;
252 
255  unsigned DstReg,
256  uint64_t Imm) const;
257 
260  unsigned DstReg, unsigned SrcReg) const override;
261 
262  /// \brief Get the index of Op in the MachineInstr.
263  ///
264  /// \returns -1 if the Instruction does not contain the specified \p Op.
265  int getOperandIdx(const MachineInstr &MI, unsigned Op) const;
266 
267  /// \brief Get the index of \p Op for the given Opcode.
268  ///
269  /// \returns -1 if the Instruction does not contain the specified \p Op.
270  int getOperandIdx(unsigned Opcode, unsigned Op) const;
271 
272  /// \brief Helper function for setting instruction flag values.
273  void setImmOperand(MachineInstr *MI, unsigned Op, int64_t Imm) const;
274 
275  /// \returns true if this instruction has an operand for storing target flags.
276  bool hasFlagOperand(const MachineInstr &MI) const;
277 
278  ///\brief Add one of the MO_FLAG* flags to the specified \p Operand.
279  void addFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
280 
281  ///\brief Determine if the specified \p Flag is set on this \p Operand.
282  bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const;
283 
284  /// \param SrcIdx The register source to set the flag on (e.g src0, src1, src2)
285  /// \param Flag The flag being set.
286  ///
287  /// \returns the operand containing the flags for this instruction.
288  MachineOperand &getFlagOp(MachineInstr *MI, unsigned SrcIdx = 0,
289  unsigned Flag = 0) const;
290 
291  /// \brief Clear the specified flag on the instruction.
292  void clearFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
293 };
294 
295 namespace AMDGPU {
296 
297 int getLDSNoRetOp(uint16_t Opcode);
298 
299 } //End namespace AMDGPU
300 
301 } // End llvm namespace
302 
303 #endif
MachineInstr * buildSlotOfVectorInstruction(MachineBasicBlock &MBB, MachineInstr *MI, unsigned Slot, unsigned DstReg) const
bool readsLDSSrcReg(const MachineInstr *MI) const
void clearFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const
Clear the specified flag on the instruction.
void setImmOperand(MachineInstr *MI, unsigned Op, int64_t Imm) const
Helper function for setting instruction flag values.
bool isLDSInstr(unsigned Opcode) const
bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const
Determine if the specified Flag is set on this Operand.
unsigned calculateIndirectAddress(unsigned RegIndex, unsigned Channel) const override
Calculate the "Indirect Address" for the given RegIndex and Channel.
int getSrcIdx(unsigned Opcode, unsigned SrcNum) const
bool canBeConsideredALU(const MachineInstr *MI) const
bool isVector(const MachineInstr &MI) const
Vector instructions are instructions that must fill all instruction slots within an instruction group...
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, DebugLoc DL) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
bool fitsReadPortLimitations(const std::vector< MachineInstr * > &MIs, const DenseMap< unsigned, unsigned > &PV, std::vector< BankSwizzle > &BS, bool isLastAluTrans) const
Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210 returns true and the first ...
A debug info location.
Definition: DebugLoc.h:34
bool isPlaceHolderOpcode(unsigned opcode) const
Interface definition for R600RegisterInfo.
bool isVectorOnly(unsigned Opcode) const
bool hasFlagOperand(const MachineInstr &MI) const
bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
const R600RegisterInfo & getRegisterInfo() const override
bool isCubeOp(unsigned opcode) const
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
int getLDSNoRetOp(uint16_t Opcode)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APInt.h:33
MachineInstr * buildMovImm(MachineBasicBlock &BB, MachineBasicBlock::iterator I, unsigned DstReg, uint64_t Imm) const
MachineInstr * buildMovInstr(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned DstReg, unsigned SrcReg) const override
Build a MOV instruction.
bool DefinesPredicate(MachineInstr *MI, std::vector< MachineOperand > &Pred) const override
bool hasInstrModifiers(unsigned Opcode) const
bool isPredicable(MachineInstr *MI) const override
bool usesVertexCache(unsigned Opcode) const
R600InstrInfo(const AMDGPUSubtarget &st)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: ArrayRef.h:31
Itinerary data supplied by a subtarget to be used by a target.
MachineOperand & getFlagOp(MachineInstr *MI, unsigned SrcIdx=0, unsigned Flag=0) const
bool usesTextureCache(unsigned Opcode) const
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:97
bool isExport(unsigned Opcode) const
bundle_iterator< MachineInstr, instr_iterator > iterator
SmallVector< std::pair< MachineOperand *, int64_t >, 3 > getSrcs(MachineInstr *MI) const
bool isPredicated(const MachineInstr *MI) const override
bool FindSwizzleForVectorSlot(const std::vector< std::vector< std::pair< int, unsigned > > > &IGSrcs, std::vector< R600InstrInfo::BankSwizzle > &SwzCandidate, const std::vector< std::pair< int, unsigned > > &TransSrcs, R600InstrInfo::BankSwizzle TransSwz) const
Enumerate all possible Swizzle sequence to find one that can meet all read port requirements.
bundle_iterator - MachineBasicBlock iterator that automatically skips over MIs that are inside bundle...
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, const BranchProbability &Probability) const override
int getOperandIdx(const MachineInstr &MI, unsigned Op) const
Get the index of Op in the MachineInstr.
unsigned RemoveBranch(MachineBasicBlock &MBB) const override
bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, unsigned ExtraPredCycles, const BranchProbability &Probability) const override
unsigned int getPredicationCost(const MachineInstr *) const override
bool usesAddressRegister(MachineInstr *MI) const
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:861
Represents one node in the SelectionDAG.
bool isTrig(const MachineInstr &MI) const
bool mustBeLastInClause(unsigned Opcode) const
int getSelIdx(unsigned Opcode, unsigned SrcIdx) const
bool ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
unsigned int getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr *MI, unsigned *PredCost=nullptr) const override
Contains the definition of a TargetInstrInfo class that is common to all AMD GPUs.
TargetSubtargetInfo - Generic base class for all target subtargets.
Representation of each machine instruction.
Definition: MachineInstr.h:51
void addFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const
Add one of the MO_FLAG* flags to the specified Operand.
void reserveIndirectRegisters(BitVector &Reserved, const MachineFunction &MF) const
Reserve the registers that may be accesed using indirect addressing.
MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned Opcode, unsigned DstReg, unsigned Src0Reg, unsigned Src1Reg=0) const
buildDefaultInstruction - This function returns a MachineInstr with all the instruction modifiers ini...
unsigned isLegalUpTo(const std::vector< std::vector< std::pair< int, unsigned > > > &IGSrcs, const std::vector< R600InstrInfo::BankSwizzle > &Swz, const std::vector< std::pair< int, unsigned > > &TransSrcs, R600InstrInfo::BankSwizzle TransSwz) const
returns how many MIs (whose inputs are represented by IGSrcs) can be packed in the same Instruction G...
#define I(x, y, z)
Definition: MD5.cpp:54
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
unsigned getMaxAlusPerClause() const
bool isReductionOp(unsigned opcode) const
const TargetRegisterClass * getIndirectAddrRegClass() const override
DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &) const override
bool isMov(unsigned Opcode) const override
bool definesAddressRegister(MachineInstr *MI) const
int getInstrLatency(const InstrItineraryData *ItinData, SDNode *Node) const override
bool isLDSNoRetInstr(unsigned Opcode) const
bool fitsConstReadLimitations(const std::vector< MachineInstr * > &) const
An instruction group can only access 2 channel pair (either [XY] or [ZW]) from KCache bank on R700+...
bool isLDSRetInstr(unsigned Opcode) const
bool PredicateInstruction(MachineInstr *MI, ArrayRef< MachineOperand > Pred) const override
bool isALUInstr(unsigned Opcode) const
bool isTransOnly(unsigned Opcode) const
bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const override