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LLVM
3.7.0
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#include "X86InstrInfo.h"#include "X86.h"#include "X86InstrBuilder.h"#include "X86MachineFunctionInfo.h"#include "X86Subtarget.h"#include "X86TargetMachine.h"#include "llvm/ADT/STLExtras.h"#include "llvm/CodeGen/LiveVariables.h"#include "llvm/CodeGen/MachineConstantPool.h"#include "llvm/CodeGen/MachineDominators.h"#include "llvm/CodeGen/MachineFrameInfo.h"#include "llvm/CodeGen/MachineInstrBuilder.h"#include "llvm/CodeGen/MachineRegisterInfo.h"#include "llvm/CodeGen/StackMaps.h"#include "llvm/IR/DerivedTypes.h"#include "llvm/IR/Function.h"#include "llvm/IR/LLVMContext.h"#include "llvm/MC/MCAsmInfo.h"#include "llvm/MC/MCExpr.h"#include "llvm/MC/MCInst.h"#include "llvm/Support/CommandLine.h"#include "llvm/Support/Debug.h"#include "llvm/Support/ErrorHandling.h"#include "llvm/Support/raw_ostream.h"#include "llvm/Target/TargetOptions.h"#include <limits>#include "X86GenInstrInfo.inc"Go to the source code of this file.
Classes | |
| struct | X86MemoryFoldTableEntry |
Macros | |
| #define | DEBUG_TYPE "x86-instr-info" |
| #define | GET_INSTRINFO_CTOR_DTOR |
Enumerations | |
| enum | { TB_INDEX_0 = 0, TB_INDEX_1 = 1, TB_INDEX_2 = 2, TB_INDEX_3 = 3, TB_INDEX_4 = 4, TB_INDEX_MASK = 0xf, TB_NO_REVERSE = 1 << 4, TB_NO_FORWARD = 1 << 5, TB_FOLDED_LOAD = 1 << 6, TB_FOLDED_STORE = 1 << 7, TB_ALIGN_SHIFT = 8, TB_ALIGN_NONE = 0 << TB_ALIGN_SHIFT, TB_ALIGN_16 = 16 << TB_ALIGN_SHIFT, TB_ALIGN_32 = 32 << TB_ALIGN_SHIFT, TB_ALIGN_64 = 64 << TB_ALIGN_SHIFT, TB_ALIGN_MASK = 0xff << TB_ALIGN_SHIFT } |
Functions | |
| static bool | isFrameLoadOpcode (int Opcode) |
| static bool | isFrameStoreOpcode (int Opcode) |
| static bool | regIsPICBase (unsigned BaseReg, const MachineRegisterInfo &MRI) |
| Return true if register is PIC base; i.e.g defined by X86::MOVPC32r. More... | |
| static bool | hasLiveCondCodeDef (MachineInstr *MI) |
| True if MI has a condition code def, e.g. EFLAGS, that is not marked dead. More... | |
| static unsigned | getTruncatedShiftCount (MachineInstr *MI, unsigned ShiftAmtOperandIdx) |
| Check whether the shift count for a machine operand is non-zero. More... | |
| static bool | isTruncatedShiftCountForLEA (unsigned ShAmt) |
| Check whether the given shift count is appropriate can be represented by a LEA instruction. More... | |
| static X86::CondCode | getCondFromBranchOpc (unsigned BrOpc) |
| static X86::CondCode | getCondFromSETOpc (unsigned Opc) |
| Return condition code of a SET opcode. More... | |
| static X86::CondCode | getSwappedCondition (X86::CondCode CC) |
| Assuming the flags are set by MI(a,b), return the condition code if we modify the instructions such that flags are set by MI(b,a). More... | |
| static bool | isHReg (unsigned Reg) |
| Test if the given register is a physical h register. More... | |
| static unsigned | CopyToFromAsymmetricReg (unsigned DestReg, unsigned SrcReg, const X86Subtarget &Subtarget) |
| static bool | MaskRegClassContains (unsigned Reg) |
| static unsigned | copyPhysRegOpcode_AVX512 (unsigned &DestReg, unsigned &SrcReg) |
| static unsigned | getLoadStoreRegOpcode (unsigned Reg, const TargetRegisterClass *RC, bool isStackAligned, const X86Subtarget &STI, bool load) |
| static unsigned | getStoreRegOpcode (unsigned SrcReg, const TargetRegisterClass *RC, bool isStackAligned, const X86Subtarget &STI) |
| static unsigned | getLoadRegOpcode (unsigned DestReg, const TargetRegisterClass *RC, bool isStackAligned, const X86Subtarget &STI) |
| static bool | isRedundantFlagInstr (MachineInstr *FlagI, unsigned SrcReg, unsigned SrcReg2, int ImmValue, MachineInstr *OI) |
| Check whether the first instruction, whose only purpose is to update flags, can be made redundant. More... | |
| static bool | isDefConvertible (MachineInstr *MI) |
| Check whether the definition can be converted to remove a comparison against zero. More... | |
| static X86::CondCode | isUseDefConvertible (MachineInstr *MI) |
| Check whether the use can be converted to remove a comparison against zero. More... | |
| static bool | Expand2AddrUndef (MachineInstrBuilder &MIB, const MCInstrDesc &Desc) |
| Expand a single-def pseudo instruction to a two-addr instruction with two undef reads of the register being defined. More... | |
| static void | expandLoadStackGuard (MachineInstrBuilder &MIB, const TargetInstrInfo &TII) |
| static void | addOperands (MachineInstrBuilder &MIB, ArrayRef< MachineOperand > MOs) |
| static MachineInstr * | FuseTwoAddrInst (MachineFunction &MF, unsigned Opcode, ArrayRef< MachineOperand > MOs, MachineBasicBlock::iterator InsertPt, MachineInstr *MI, const TargetInstrInfo &TII) |
| static MachineInstr * | FuseInst (MachineFunction &MF, unsigned Opcode, unsigned OpNo, ArrayRef< MachineOperand > MOs, MachineBasicBlock::iterator InsertPt, MachineInstr *MI, const TargetInstrInfo &TII) |
| static MachineInstr * | MakeM0Inst (const TargetInstrInfo &TII, unsigned Opcode, ArrayRef< MachineOperand > MOs, MachineBasicBlock::iterator InsertPt, MachineInstr *MI) |
| static bool | hasPartialRegUpdate (unsigned Opcode) |
| Return true for all instructions that only update the first 32 or 64-bits of the destination register and leave the rest unmodified. More... | |
| static bool | hasUndefRegUpdate (unsigned Opcode) |
| static bool | isNonFoldablePartialRegisterLoad (const MachineInstr &LoadMI, const MachineInstr &UserMI, const MachineFunction &MF) |
Check if LoadMI is a partial register load that we can't fold into MI because the latter uses contents that wouldn't be defined in the folded version. More... | |
| static const uint16_t * | lookup (unsigned opcode, unsigned domain) |
| static const uint16_t * | lookupAVX2 (unsigned opcode, unsigned domain) |
| static bool | hasVirtualRegDefsInBasicBlock (const MachineInstr &Inst, const MachineBasicBlock *MBB) |
| static bool | hasReassocSibling (const MachineInstr &Inst, bool &Commuted) |
| static bool | isAssociativeAndCommutative (unsigned Opcode) |
| static bool | isReassocCandidate (const MachineInstr &Inst, bool &Commuted) |
| Return true if the input instruction is part of a chain of dependent ops that are suitable for reassociation, otherwise return false. More... | |
| static void | reassociateOps (MachineInstr &Root, MachineInstr &Prev, MachineCombinerPattern::MC_PATTERN Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) |
| Attempt the following reassociation to reduce critical path length: B = A op X (Prev) C = B op Y (Root) ===> B = X op Y C = A op B. More... | |
Variables | |
| static cl::opt< bool > | NoFusing ("disable-spill-fusing", cl::desc("Disable fusing of spill code into instructions")) |
| static cl::opt< bool > | PrintFailedFusing ("print-failed-fuse-candidates", cl::desc("Print instructions that the allocator wants to"" fuse, but the X86 backend currently can't"), cl::Hidden) |
| static cl::opt< bool > | ReMatPICStubLoad ("remat-pic-stub-load", cl::desc("Re-materialize load from stub in PIC mode"), cl::init(false), cl::Hidden) |
| static const uint16_t | ReplaceableInstrs [][3] |
| static const uint16_t | ReplaceableInstrsAVX2 [][3] |
| #define DEBUG_TYPE "x86-instr-info" |
Definition at line 43 of file X86InstrInfo.cpp.
| #define GET_INSTRINFO_CTOR_DTOR |
Definition at line 45 of file X86InstrInfo.cpp.
| anonymous enum |
Definition at line 61 of file X86InstrInfo.cpp.
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Definition at line 4791 of file X86InstrInfo.cpp.
References llvm::addOffset(), llvm::MachineInstrBuilder::addOperand(), and llvm::ArrayRef< T >::size().
Referenced by FuseInst(), FuseTwoAddrInst(), and MakeM0Inst().
Definition at line 3832 of file X86InstrInfo.cpp.
References contains(), llvm::get512BitSuperRegister(), llvm::getX86SubSuperRegister(), llvm::MVT::i32, and MaskRegClassContains().
Referenced by llvm::X86InstrInfo::copyPhysReg().
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Definition at line 3783 of file X86InstrInfo.cpp.
References contains(), llvm::X86Subtarget::hasAVX(), and llvm::X86Subtarget::hasAVX512().
Referenced by llvm::X86InstrInfo::copyPhysReg().
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Expand a single-def pseudo instruction to a two-addr instruction with two undef reads of the register being defined.
This is used for mapping: xmm4 = V_SET0 to: xmm4 = PXORrr xmm4<undef>, xmm4<undef>
Definition at line 4713 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineInstr::setDesc(), and llvm::RegState::Undef.
Referenced by llvm::X86InstrInfo::expandPostRAPseudo().
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Definition at line 4730 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addGlobalAddress(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::DL, llvm::MCInstrInfo::get(), llvm::MachineInstr::getDebugLoc(), llvm::MachinePointerInfo::getGOT(), llvm::MachineInstrBuilder::getInstr(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::RegState::Kill, llvm::MachineInstr::memoperands_begin(), llvm::X86II::MO_GOTPCREL, llvm::MachineMemOperand::MOInvariant, llvm::MachineMemOperand::MOLoad, llvm::MachineInstr::setDebugLoc(), and llvm::MachineInstr::setDesc().
Referenced by llvm::X86InstrInfo::expandPostRAPseudo().
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Definition at line 4828 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addOperand(), addOperands(), llvm::MachineFunction::CreateMachineInstr(), llvm::MCInstrInfo::get(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineBasicBlock::insert(), and llvm::MachineOperand::isReg().
Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl().
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Definition at line 4799 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addOperand(), addOperands(), llvm::MachineFunction::CreateMachineInstr(), llvm::MCInstrInfo::get(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), and llvm::MachineBasicBlock::insert().
Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl().
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Definition at line 3186 of file X86InstrInfo.cpp.
References llvm::X86::COND_A, llvm::X86::COND_AE, llvm::X86::COND_B, llvm::X86::COND_BE, llvm::X86::COND_E, llvm::X86::COND_G, llvm::X86::COND_GE, llvm::X86::COND_INVALID, llvm::X86::COND_L, llvm::X86::COND_LE, llvm::X86::COND_NE, llvm::X86::COND_NO, llvm::X86::COND_NP, llvm::X86::COND_NS, llvm::X86::COND_O, llvm::X86::COND_P, and llvm::X86::COND_S.
Referenced by llvm::X86InstrInfo::optimizeCompareInstr(), and llvm::X86InstrInfo::RemoveBranch().
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Return condition code of a SET opcode.
Definition at line 3209 of file X86InstrInfo.cpp.
References llvm::X86::COND_A, llvm::X86::COND_AE, llvm::X86::COND_B, llvm::X86::COND_BE, llvm::X86::COND_E, llvm::X86::COND_G, llvm::X86::COND_GE, llvm::X86::COND_INVALID, llvm::X86::COND_L, llvm::X86::COND_LE, llvm::X86::COND_NE, llvm::X86::COND_NO, llvm::X86::COND_NP, llvm::X86::COND_NS, llvm::X86::COND_O, llvm::X86::COND_P, and llvm::X86::COND_S.
Referenced by llvm::X86InstrInfo::optimizeCompareInstr().
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Definition at line 4063 of file X86InstrInfo.cpp.
References getLoadStoreRegOpcode().
Referenced by llvm::X86InstrInfo::loadRegFromAddr(), llvm::X86InstrInfo::loadRegFromStackSlot(), and llvm::X86InstrInfo::unfoldMemoryOperand().
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Definition at line 3938 of file X86InstrInfo.cpp.
References llvm::TargetRegisterClass::getSize(), llvm::X86Subtarget::hasAVX(), llvm::X86Subtarget::hasAVX512(), llvm::X86Subtarget::is64Bit(), isHReg(), and llvm_unreachable.
Referenced by getLoadRegOpcode(), and getStoreRegOpcode().
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Definition at line 4055 of file X86InstrInfo.cpp.
References getLoadStoreRegOpcode().
Referenced by llvm::X86InstrInfo::storeRegToAddr(), llvm::X86InstrInfo::storeRegToStackSlot(), and llvm::X86InstrInfo::unfoldMemoryOperand().
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Assuming the flags are set by MI(a,b), return the condition code if we modify the instructions such that flags are set by MI(b,a).
Definition at line 3334 of file X86InstrInfo.cpp.
References llvm::X86::COND_A, llvm::X86::COND_AE, llvm::X86::COND_B, llvm::X86::COND_BE, llvm::X86::COND_E, llvm::X86::COND_G, llvm::X86::COND_GE, llvm::X86::COND_INVALID, llvm::X86::COND_L, llvm::X86::COND_LE, and llvm::X86::COND_NE.
Referenced by llvm::X86InstrInfo::optimizeCompareInstr().
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Check whether the shift count for a machine operand is non-zero.
Definition at line 2443 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOperand(), llvm::X86II::REX_W, and llvm::MCInstrDesc::TSFlags.
Referenced by llvm::X86InstrInfo::convertToThreeAddress(), and isDefConvertible().
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True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
Definition at line 2431 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isDead(), llvm::MachineOperand::isDef(), and llvm::MachineOperand::isReg().
Referenced by llvm::X86InstrInfo::convertToThreeAddress().
Return true for all instructions that only update the first 32 or 64-bits of the destination register and leave the rest unmodified.
This can be used to avoid folding loads if the instructions only update part of the destination register, and the non-updated part is not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks the partial register dependency and it can improve performance. e.g.:
movss (rdi), xmm0 cvtss2sd xmm0, xmm0
Instead of cvtss2sd (rdi), xmm0
FIXME: This should be turned into a TSFlags.
Definition at line 5045 of file X86InstrInfo.cpp.
Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl(), and llvm::X86InstrInfo::getPartialRegUpdateClearance().
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Definition at line 6372 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::MachineRegisterInfo::hasOneNonDBGUse(), hasVirtualRegDefsInBasicBlock(), and std::swap().
Referenced by isReassocCandidate().
Definition at line 5118 of file X86InstrInfo.cpp.
Referenced by llvm::X86InstrInfo::getUndefRegClearance().
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Definition at line 6350 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::MachineOperand::isReg(), and llvm::TargetRegisterInfo::isVirtualRegister().
Referenced by hasReassocSibling(), and isReassocCandidate().
Definition at line 6400 of file X86InstrInfo.cpp.
Referenced by isReassocCandidate().
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Check whether the definition can be converted to remove a comparison against zero.
Definition at line 4259 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), getTruncatedShiftCount(), and isTruncatedShiftCountForLEA().
Referenced by llvm::X86InstrInfo::optimizeCompareInstr().
Definition at line 2124 of file X86InstrInfo.cpp.
Referenced by llvm::X86InstrInfo::isLoadFromStackSlot(), and llvm::X86InstrInfo::isLoadFromStackSlotPostFE().
Definition at line 2157 of file X86InstrInfo.cpp.
Referenced by llvm::X86InstrInfo::isStoreToStackSlot(), and llvm::X86InstrInfo::isStoreToStackSlotPostFE().
Test if the given register is a physical h register.
Definition at line 3778 of file X86InstrInfo.cpp.
Referenced by llvm::X86InstrInfo::copyPhysReg(), and getLoadStoreRegOpcode().
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Check if LoadMI is a partial register load that we can't fold into MI because the latter uses contents that wouldn't be defined in the folded version.
For instance, this transformation isn't legal: movss (rdi), xmm0 addps xmm0, xmm0 -> addps (rdi), xmm0
But this one is: movss (rdi), xmm0 addss xmm0, xmm0 -> addss (rdi), xmm0
Definition at line 5289 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), and llvm::MachineFunction::getRegInfo().
Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl().
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Return true if the input instruction is part of a chain of dependent ops that are suitable for reassociation, otherwise return false.
If the instruction's operands must be commuted to have a previous instruction of the same type define the first source operand, Commuted will be set to true.
Definition at line 6421 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getParent(), hasReassocSibling(), hasVirtualRegDefsInBasicBlock(), and isAssociativeAndCommutative().
Referenced by llvm::X86InstrInfo::getMachineCombinerPatterns().
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Check whether the first instruction, whose only purpose is to update flags, can be made redundant.
CMPrr can be made redundant by SUBrr if the operands are the same. This function can be extended later on. SrcReg, SrcRegs: register operands for FlagI. ImmValue: immediate for FlagI if it takes an immediate.
Definition at line 4220 of file X86InstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::getReg().
Referenced by llvm::X86InstrInfo::optimizeCompareInstr().
Check whether the given shift count is appropriate can be represented by a LEA instruction.
Definition at line 2453 of file X86InstrInfo.cpp.
Referenced by llvm::X86InstrInfo::convertToThreeAddress(), and isDefConvertible().
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Check whether the use can be converted to remove a comparison against zero.
Definition at line 4344 of file X86InstrInfo.cpp.
References llvm::X86::COND_B, llvm::X86::COND_E, llvm::X86::COND_INVALID, and llvm::MachineInstr::getOpcode().
Referenced by llvm::X86InstrInfo::optimizeCompareInstr().
Definition at line 6194 of file X86InstrInfo.cpp.
References llvm::array_lengthof().
Referenced by llvm::X86InstrInfo::getExecutionDomain(), llvm::Module::getNamedMetadata(), and llvm::X86InstrInfo::setExecutionDomain().
Definition at line 6201 of file X86InstrInfo.cpp.
References llvm::array_lengthof().
Referenced by llvm::X86InstrInfo::getExecutionDomain(), and llvm::X86InstrInfo::setExecutionDomain().
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Definition at line 4853 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), addOperands(), llvm::BuildMI(), llvm::MCInstrInfo::get(), and llvm::MachineInstr::getDebugLoc().
Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl().
Definition at line 3824 of file X86InstrInfo.cpp.
Referenced by copyPhysRegOpcode_AVX512().
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Attempt the following reassociation to reduce critical path length: B = A op X (Prev) C = B op Y (Root) ===> B = X op Y C = A op B.
Definition at line 6478 of file X86InstrInfo.cpp.
References llvm::BuildMI(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MCInstrInfo::get(), llvm::MachineInstr::getDebugLoc(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::getKillRegState(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineInstr::getRegClassConstraint(), llvm::MachineFunction::getRegInfo(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::insert(), llvm::MachineOperand::isKill(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), and TII.
Referenced by llvm::X86InstrInfo::genAlternativeCodeSequence().
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Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
Definition at line 2235 of file X86InstrInfo.cpp.
References llvm::MachineRegisterInfo::def_instr_begin(), llvm::MachineRegisterInfo::def_instr_end(), llvm::MachineInstr::getOpcode(), I, and llvm::TargetRegisterInfo::isVirtualRegister().
Referenced by llvm::X86InstrInfo::isReallyTriviallyReMaterializable().
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Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl().
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Referenced by llvm::X86InstrInfo::isReallyTriviallyReMaterializable().
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Definition at line 6125 of file X86InstrInfo.cpp.
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Definition at line 6167 of file X86InstrInfo.cpp.
1.8.6