LLVM  3.7.0
Public Member Functions | Protected Member Functions | Protected Attributes | List of all members
llvm::AMDGPUInstrInfo Class Referenceabstract

#include <AMDGPUInstrInfo.h>

Inheritance diagram for llvm::AMDGPUInstrInfo:
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Collaboration diagram for llvm::AMDGPUInstrInfo:
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Public Member Functions

 AMDGPUInstrInfo (const AMDGPUSubtarget &st)
 
virtual const AMDGPURegisterInfogetRegisterInfo () const =0
 
bool isCoalescableExtInstr (const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override
 
unsigned isLoadFromStackSlot (const MachineInstr *MI, int &FrameIndex) const override
 
unsigned isLoadFromStackSlotPostFE (const MachineInstr *MI, int &FrameIndex) const override
 
bool hasLoadFromStackSlot (const MachineInstr *MI, const MachineMemOperand *&MMO, int &FrameIndex) const override
 
unsigned isStoreFromStackSlot (const MachineInstr *MI, int &FrameIndex) const
 
unsigned isStoreFromStackSlotPostFE (const MachineInstr *MI, int &FrameIndex) const
 
bool hasStoreFromStackSlot (const MachineInstr *MI, const MachineMemOperand *&MMO, int &FrameIndex) const
 
MachineInstrconvertToThreeAddress (MachineFunction::iterator &MFI, MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const override
 
bool expandPostRAPseudo (MachineBasicBlock::iterator MI) const override
 
void storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
 
void loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
 
int getIndirectIndexBegin (const MachineFunction &MF) const
 
int getIndirectIndexEnd (const MachineFunction &MF) const
 
bool canFoldMemoryOperand (const MachineInstr *MI, ArrayRef< unsigned > Ops) const override
 
bool unfoldMemoryOperand (MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const override
 
bool unfoldMemoryOperand (SelectionDAG &DAG, SDNode *N, SmallVectorImpl< SDNode * > &NewNodes) const override
 
unsigned getOpcodeAfterMemoryUnfold (unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const override
 
bool enableClusterLoads () const override
 
bool shouldScheduleLoadsNear (SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override
 
bool ReverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
 
void insertNoop (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
 
bool isPredicated (const MachineInstr *MI) const override
 
bool SubsumesPredicate (ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
 
bool DefinesPredicate (MachineInstr *MI, std::vector< MachineOperand > &Pred) const override
 
bool isPredicable (MachineInstr *MI) const override
 
bool isSafeToMoveRegClassDefs (const TargetRegisterClass *RC) const override
 
bool isRegisterStore (const MachineInstr &MI) const
 
bool isRegisterLoad (const MachineInstr &MI) const
 
int pseudoToMCOpcode (int Opcode) const
 Return a target-specific opcode if Opcode is a pseudo instruction. More...
 
const MCInstrDescgetMCOpcodeFromPseudo (unsigned Opcode) const
 Return the descriptor of the target-specific machine instruction that corresponds to the specified pseudo or native opcode. More...
 
virtual bool isMov (unsigned opcode) const =0
 
virtual unsigned calculateIndirectAddress (unsigned RegIndex, unsigned Channel) const =0
 Calculate the "Indirect Address" for the given RegIndex and Channel. More...
 
virtual const TargetRegisterClassgetIndirectAddrRegClass () const =0
 
virtual MachineInstrBuilder buildIndirectWrite (MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned ValueReg, unsigned Address, unsigned OffsetReg) const =0
 Build instruction(s) for an indirect register write. More...
 
virtual MachineInstrBuilder buildIndirectRead (MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned ValueReg, unsigned Address, unsigned OffsetReg) const =0
 Build instruction(s) for an indirect register read. More...
 
virtual MachineInstrbuildMovInstr (MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned DstReg, unsigned SrcReg) const =0
 Build a MOV instruction. More...
 
int getMaskedMIMGOp (uint16_t Opcode, unsigned Channels) const
 Given a MIMG Opcode that writes all 4 channels, return the equivalent opcode that writes Channels Channels. More...
 

Protected Member Functions

MachineInstrfoldMemoryOperandImpl (MachineFunction &MF, MachineInstr *MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex) const override
 
MachineInstrfoldMemoryOperandImpl (MachineFunction &MF, MachineInstr *MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr *LoadMI) const override
 

Protected Attributes

const AMDGPUSubtargetST
 

Detailed Description

Definition at line 40 of file AMDGPUInstrInfo.h.

Constructor & Destructor Documentation

AMDGPUInstrInfo::AMDGPUInstrInfo ( const AMDGPUSubtarget st)
explicit

Definition at line 33 of file AMDGPUInstrInfo.cpp.

Member Function Documentation

virtual MachineInstrBuilder llvm::AMDGPUInstrInfo::buildIndirectRead ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
unsigned  ValueReg,
unsigned  Address,
unsigned  OffsetReg 
) const
pure virtual

Build instruction(s) for an indirect register read.

Returns
The instruction that performs the indirect register read

Implemented in llvm::SIInstrInfo, and llvm::R600InstrInfo.

Referenced by expandPostRAPseudo().

virtual MachineInstrBuilder llvm::AMDGPUInstrInfo::buildIndirectWrite ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
unsigned  ValueReg,
unsigned  Address,
unsigned  OffsetReg 
) const
pure virtual

Build instruction(s) for an indirect register write.

Returns
The instruction that performs the indirect register write

Implemented in llvm::SIInstrInfo, and llvm::R600InstrInfo.

Referenced by expandPostRAPseudo().

virtual MachineInstr* llvm::AMDGPUInstrInfo::buildMovInstr ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
unsigned  DstReg,
unsigned  SrcReg 
) const
pure virtual

Build a MOV instruction.

Implemented in llvm::R600InstrInfo, and llvm::SIInstrInfo.

Referenced by expandPostRAPseudo().

virtual unsigned llvm::AMDGPUInstrInfo::calculateIndirectAddress ( unsigned  RegIndex,
unsigned  Channel 
) const
pure virtual

Calculate the "Indirect Address" for the given RegIndex and Channel.

We model indirect addressing using a virtual address space that can be accesed with loads and stores. The "Indirect Address" is the memory address in this virtual address space that maps to the given RegIndex and Channel.

Implemented in llvm::SIInstrInfo, and llvm::R600InstrInfo.

Referenced by expandPostRAPseudo().

bool AMDGPUInstrInfo::canFoldMemoryOperand ( const MachineInstr MI,
ArrayRef< unsigned Ops 
) const
override

Definition at line 167 of file AMDGPUInstrInfo.cpp.

MachineInstr * AMDGPUInstrInfo::convertToThreeAddress ( MachineFunction::iterator MFI,
MachineBasicBlock::iterator MBBI,
LiveVariables LV 
) const
override

Definition at line 83 of file AMDGPUInstrInfo.cpp.

bool AMDGPUInstrInfo::DefinesPredicate ( MachineInstr MI,
std::vector< MachineOperand > &  Pred 
) const
override

Definition at line 244 of file AMDGPUInstrInfo.cpp.

bool AMDGPUInstrInfo::enableClusterLoads ( ) const
override

Definition at line 196 of file AMDGPUInstrInfo.cpp.

bool AMDGPUInstrInfo::expandPostRAPseudo ( MachineBasicBlock::iterator  MI) const
override
MachineInstr * AMDGPUInstrInfo::foldMemoryOperandImpl ( MachineFunction MF,
MachineInstr MI,
ArrayRef< unsigned Ops,
MachineBasicBlock::iterator  InsertPt,
int  FrameIndex 
) const
overrideprotected

Definition at line 155 of file AMDGPUInstrInfo.cpp.

MachineInstr * AMDGPUInstrInfo::foldMemoryOperandImpl ( MachineFunction MF,
MachineInstr MI,
ArrayRef< unsigned Ops,
MachineBasicBlock::iterator  InsertPt,
MachineInstr LoadMI 
) const
overrideprotected

Definition at line 161 of file AMDGPUInstrInfo.cpp.

virtual const TargetRegisterClass* llvm::AMDGPUInstrInfo::getIndirectAddrRegClass ( ) const
pure virtual
Returns
The register class to be used for loading and storing values from an "Indirect Address" .

Implemented in llvm::SIInstrInfo, and llvm::R600InstrInfo.

Referenced by expandPostRAPseudo(), and getIndirectIndexBegin().

int AMDGPUInstrInfo::getIndirectIndexBegin ( const MachineFunction MF) const
int AMDGPUInstrInfo::getIndirectIndexEnd ( const MachineFunction MF) const
int AMDGPUInstrInfo::getMaskedMIMGOp ( uint16_t  Opcode,
unsigned  Channels 
) const

Given a MIMG Opcode that writes all 4 channels, return the equivalent opcode that writes Channels Channels.

Definition at line 320 of file AMDGPUInstrInfo.cpp.

Referenced by llvm::SITargetLowering::AdjustInstrPostInstrSelection().

const MCInstrDesc& llvm::AMDGPUInstrInfo::getMCOpcodeFromPseudo ( unsigned  Opcode) const
inline

Return the descriptor of the target-specific machine instruction that corresponds to the specified pseudo or native opcode.

Definition at line 146 of file AMDGPUInstrInfo.h.

References pseudoToMCOpcode().

Referenced by llvm::SIRegisterInfo::eliminateFrameIndex().

unsigned AMDGPUInstrInfo::getOpcodeAfterMemoryUnfold ( unsigned  Opc,
bool  UnfoldLoad,
bool  UnfoldStore,
unsigned LoadRegIndex = nullptr 
) const
override

Definition at line 189 of file AMDGPUInstrInfo.cpp.

const AMDGPURegisterInfo & AMDGPUInstrInfo::getRegisterInfo ( ) const
pure virtual

Implemented in llvm::SIInstrInfo, and llvm::R600InstrInfo.

Definition at line 36 of file AMDGPUInstrInfo.cpp.

bool AMDGPUInstrInfo::hasLoadFromStackSlot ( const MachineInstr MI,
const MachineMemOperand *&  MMO,
int FrameIndex 
) const
override

Definition at line 59 of file AMDGPUInstrInfo.cpp.

bool AMDGPUInstrInfo::hasStoreFromStackSlot ( const MachineInstr MI,
const MachineMemOperand *&  MMO,
int FrameIndex 
) const

Definition at line 75 of file AMDGPUInstrInfo.cpp.

void AMDGPUInstrInfo::insertNoop ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI 
) const
override

Definition at line 228 of file AMDGPUInstrInfo.cpp.

bool AMDGPUInstrInfo::isCoalescableExtInstr ( const MachineInstr MI,
unsigned SrcReg,
unsigned DstReg,
unsigned SubIdx 
) const
override

Definition at line 40 of file AMDGPUInstrInfo.cpp.

unsigned AMDGPUInstrInfo::isLoadFromStackSlot ( const MachineInstr MI,
int FrameIndex 
) const
override

Definition at line 47 of file AMDGPUInstrInfo.cpp.

unsigned AMDGPUInstrInfo::isLoadFromStackSlotPostFE ( const MachineInstr MI,
int FrameIndex 
) const
override

Definition at line 53 of file AMDGPUInstrInfo.cpp.

virtual bool llvm::AMDGPUInstrInfo::isMov ( unsigned  opcode) const
pure virtual

Implemented in llvm::R600InstrInfo, and llvm::SIInstrInfo.

bool AMDGPUInstrInfo::isPredicable ( MachineInstr MI) const
override
bool AMDGPUInstrInfo::isPredicated ( const MachineInstr MI) const
override

Definition at line 233 of file AMDGPUInstrInfo.cpp.

bool AMDGPUInstrInfo::isRegisterLoad ( const MachineInstr MI) const

Definition at line 265 of file AMDGPUInstrInfo.cpp.

References AMDGPU_FLAG_REGISTER_LOAD, and llvm::MachineInstr::getOpcode().

Referenced by expandPostRAPseudo().

bool AMDGPUInstrInfo::isRegisterStore ( const MachineInstr MI) const

Definition at line 261 of file AMDGPUInstrInfo.cpp.

References AMDGPU_FLAG_REGISTER_STORE, and llvm::MachineInstr::getOpcode().

Referenced by expandPostRAPseudo().

bool AMDGPUInstrInfo::isSafeToMoveRegClassDefs ( const TargetRegisterClass RC) const
override

Definition at line 256 of file AMDGPUInstrInfo.cpp.

unsigned AMDGPUInstrInfo::isStoreFromStackSlot ( const MachineInstr MI,
int FrameIndex 
) const

Definition at line 65 of file AMDGPUInstrInfo.cpp.

unsigned AMDGPUInstrInfo::isStoreFromStackSlotPostFE ( const MachineInstr MI,
int FrameIndex 
) const

Definition at line 70 of file AMDGPUInstrInfo.cpp.

void AMDGPUInstrInfo::loadRegFromStackSlot ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
unsigned  DestReg,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI 
) const
override

Definition at line 101 of file AMDGPUInstrInfo.cpp.

References llvm_unreachable.

int AMDGPUInstrInfo::pseudoToMCOpcode ( int  Opcode) const

Return a target-specific opcode if Opcode is a pseudo instruction.

Return -1 if the target-specific opcode for the pseudo instruction does not exist. If Opcode is not a pseudo instruction, this is identity.

Definition at line 355 of file AMDGPUInstrInfo.cpp.

References AMDGPUSubtargetToSISubtarget(), llvm::AMDGPUSubtarget::getGeneration(), llvm::AMDGPU::getMCOpcode(), and ST.

Referenced by llvm::SIInstrInfo::commuteOpcode(), getMCOpcodeFromPseudo(), llvm::SIInstrInfo::hasVALU32BitEncoding(), and llvm::AMDGPUMCInstLower::lower().

bool AMDGPUInstrInfo::ReverseBranchCondition ( SmallVectorImpl< MachineOperand > &  Cond) const
override

Definition at line 223 of file AMDGPUInstrInfo.cpp.

bool AMDGPUInstrInfo::shouldScheduleLoadsNear ( SDNode Load1,
SDNode Load2,
int64_t  Offset1,
int64_t  Offset2,
unsigned  NumLoads 
) const
override

Definition at line 210 of file AMDGPUInstrInfo.cpp.

void AMDGPUInstrInfo::storeRegToStackSlot ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
unsigned  SrcReg,
bool  isKill,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI 
) const
override

Definition at line 91 of file AMDGPUInstrInfo.cpp.

References llvm_unreachable.

bool AMDGPUInstrInfo::SubsumesPredicate ( ArrayRef< MachineOperand Pred1,
ArrayRef< MachineOperand Pred2 
) const
override

Definition at line 238 of file AMDGPUInstrInfo.cpp.

bool AMDGPUInstrInfo::unfoldMemoryOperand ( MachineFunction MF,
MachineInstr MI,
unsigned  Reg,
bool  UnfoldLoad,
bool  UnfoldStore,
SmallVectorImpl< MachineInstr * > &  NewMIs 
) const
override

Definition at line 173 of file AMDGPUInstrInfo.cpp.

bool AMDGPUInstrInfo::unfoldMemoryOperand ( SelectionDAG DAG,
SDNode N,
SmallVectorImpl< SDNode * > &  NewNodes 
) const
override

Definition at line 182 of file AMDGPUInstrInfo.cpp.

Member Data Documentation

const AMDGPUSubtarget& llvm::AMDGPUInstrInfo::ST
protected

The documentation for this class was generated from the following files: