LLVM  3.7.0
llvm::AMDGPUSubtarget Member List

This is the complete list of members for llvm::AMDGPUSubtarget, including all inherited members.

AMDGPUSubtarget(const Triple &TT, StringRef CPU, StringRef FS, TargetMachine &TM)llvm::AMDGPUSubtarget
dumpCode() const llvm::AMDGPUSubtargetinline
enableHugeScratchBuffer() const llvm::AMDGPUSubtargetinline
enableMachineScheduler() const overridellvm::AMDGPUSubtargetinline
enableSubRegLiveness() const overridellvm::AMDGPUSubtargetinline
EVERGREEN enum valuellvm::AMDGPUSubtarget
FIXED_SGPR_COUNT_FOR_INIT_BUG enum valuellvm::AMDGPUSubtarget
Generation enum namellvm::AMDGPUSubtarget
getAmdKernelCodeChipID() const llvm::AMDGPUSubtarget
getDeviceName() const llvm::AMDGPUSubtargetinline
getExplicitKernelArgOffset() const llvm::AMDGPUSubtargetinline
getFrameLowering() const overridellvm::AMDGPUSubtargetinline
getGeneration() const llvm::AMDGPUSubtargetinline
getInstrInfo() const overridellvm::AMDGPUSubtargetinline
getInstrItineraryData() const overridellvm::AMDGPUSubtargetinline
getIsaVersion() const llvm::AMDGPUSubtarget
getLDSBankCount() const llvm::AMDGPUSubtargetinline
getLocalMemorySize() const llvm::AMDGPUSubtargetinline
getMaxWavesPerCU() const llvm::AMDGPUSubtargetinline
getRegisterInfo() const overridellvm::AMDGPUSubtargetinline
getStackEntrySize() const llvm::AMDGPUSubtarget
getTargetLowering() const overridellvm::AMDGPUSubtargetinline
getTexVTXClauseSize() const llvm::AMDGPUSubtargetinline
getWavefrontSize() const llvm::AMDGPUSubtargetinline
hasBCNT(unsigned Size) const llvm::AMDGPUSubtargetinline
hasBFE() const llvm::AMDGPUSubtargetinline
hasBFI() const llvm::AMDGPUSubtargetinline
hasBFM() const llvm::AMDGPUSubtargetinline
hasBORROW() const llvm::AMDGPUSubtargetinline
hasCARRY() const llvm::AMDGPUSubtargetinline
hasCaymanISA() const llvm::AMDGPUSubtargetinline
hasCFAluBug() const llvm::AMDGPUSubtargetinline
hasFastFMAF32() const llvm::AMDGPUSubtargetinline
hasFFBH() const llvm::AMDGPUSubtargetinline
hasFFBL() const llvm::AMDGPUSubtargetinline
hasFlatAddressSpace() const llvm::AMDGPUSubtargetinline
hasFP32Denormals() const llvm::AMDGPUSubtargetinline
hasFP64Denormals() const llvm::AMDGPUSubtargetinline
hasHWFP64() const llvm::AMDGPUSubtargetinline
hasMulI24() const llvm::AMDGPUSubtargetinline
hasMulU24() const llvm::AMDGPUSubtargetinline
hasSGPRInitBug() const llvm::AMDGPUSubtargetinline
hasVertexCache() const llvm::AMDGPUSubtargetinline
initializeSubtargetDependencies(const Triple &TT, StringRef GPU, StringRef FS)llvm::AMDGPUSubtarget
is64bit() const llvm::AMDGPUSubtargetinline
isAmdHsaOS() const llvm::AMDGPUSubtargetinline
ISAVersion0_0_0 enum valuellvm::AMDGPUSubtarget
ISAVersion7_0_0 enum valuellvm::AMDGPUSubtarget
ISAVersion7_0_1 enum valuellvm::AMDGPUSubtarget
ISAVersion8_0_0 enum valuellvm::AMDGPUSubtarget
ISAVersion8_0_1 enum valuellvm::AMDGPUSubtarget
isIfCvtEnabled() const llvm::AMDGPUSubtargetinline
IsIRStructurizerEnabled() const llvm::AMDGPUSubtargetinline
isPromoteAllocaEnabled() const llvm::AMDGPUSubtargetinline
isTargetELF() const llvm::AMDGPUSubtargetinline
isVGPRSpillingEnabled(const SIMachineFunctionInfo *MFI) const llvm::AMDGPUSubtarget
loadStoreOptEnabled() const llvm::AMDGPUSubtargetinline
NORTHERN_ISLANDS enum valuellvm::AMDGPUSubtarget
overrideSchedPolicy(MachineSchedPolicy &Policy, MachineInstr *begin, MachineInstr *end, unsigned NumRegionInstrs) const overridellvm::AMDGPUSubtarget
ParseSubtargetFeatures(StringRef CPU, StringRef FS)llvm::AMDGPUSubtarget
R600 enum valuellvm::AMDGPUSubtarget
r600ALUEncoding() const llvm::AMDGPUSubtargetinline
R700 enum valuellvm::AMDGPUSubtarget
SEA_ISLANDS enum valuellvm::AMDGPUSubtarget
SOUTHERN_ISLANDS enum valuellvm::AMDGPUSubtarget
unsafeDSOffsetFoldingEnabled() const llvm::AMDGPUSubtargetinline
VOLCANIC_ISLANDS enum valuellvm::AMDGPUSubtarget