LLVM  3.7.0
Functions | Variables
ARMFrameLowering.cpp File Reference
#include "ARMFrameLowering.h"
#include "ARMBaseInstrInfo.h"
#include "ARMBaseRegisterInfo.h"
#include "ARMConstantPoolValue.h"
#include "ARMMachineFunctionInfo.h"
#include "MCTargetDesc/ARMAddressingModes.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/Function.h"
#include "llvm/MC/MCContext.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Target/TargetOptions.h"
Include dependency graph for ARMFrameLowering.cpp:

Go to the source code of this file.

Functions

static MachineBasicBlock::iterator skipAlignedDPRCS2Spills (MachineBasicBlock::iterator MI, unsigned NumAlignedDPRCS2Regs)
 Skip past the code inserted by emitAlignedDPRCS2Spills, and return an iterator to the following instruction. More...
 
static bool isCSRestore (MachineInstr *MI, const ARMBaseInstrInfo &TII, const MCPhysReg *CSRegs)
 
static void emitRegPlusImmediate (bool isARM, MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, const ARMBaseInstrInfo &TII, unsigned DestReg, unsigned SrcReg, int NumBytes, unsigned MIFlags=MachineInstr::NoFlags, ARMCC::CondCodes Pred=ARMCC::AL, unsigned PredReg=0)
 
static void emitSPUpdate (bool isARM, MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, const ARMBaseInstrInfo &TII, int NumBytes, unsigned MIFlags=MachineInstr::NoFlags, ARMCC::CondCodes Pred=ARMCC::AL, unsigned PredReg=0)
 
static int sizeOfSPAdjustment (const MachineInstr *MI)
 
static bool WindowsRequiresStackProbe (const MachineFunction &MF, size_t StackSizeInBytes)
 
static void emitAligningInstructions (MachineFunction &MF, ARMFunctionInfo *AFI, const TargetInstrInfo &TII, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc DL, const unsigned Reg, const unsigned Alignment, const bool MustBeSingleInstruction)
 Emit an instruction sequence that will align the address in register Reg by zero-ing out the lower bits. More...
 
static void emitAlignedDPRCS2Spills (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned NumAlignedDPRCS2Regs, const std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI)
 Emit aligned spill instructions for NumAlignedDPRCS2Regs D-registers starting from d8. More...
 
static void emitAlignedDPRCS2Restores (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned NumAlignedDPRCS2Regs, const std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI)
 Emit aligned reload instructions for NumAlignedDPRCS2Regs D-registers starting from d8. More...
 
static unsigned GetFunctionSizeInBytes (const MachineFunction &MF, const ARMBaseInstrInfo &TII)
 
static unsigned estimateRSStackSizeLimit (MachineFunction &MF, const TargetFrameLowering *TFI)
 estimateRSStackSizeLimit - Look at each instruction that references stack frames and return the stack size limit beyond which some of these instructions will require a scratch register during their expansion later. More...
 
static void checkNumAlignedDPRCS2Regs (MachineFunction &MF, BitVector &SavedRegs)
 
static uint32_t alignToARMConstant (uint32_t Value)
 Get the minimum constant for ARM that is greater than or equal to the argument. More...
 

Variables

static cl::opt< boolSpillAlignedNEONRegs ("align-neon-spills", cl::Hidden, cl::init(true), cl::desc("Align ARM NEON spills in prolog and epilog"))
 
static const uint64_t kSplitStackAvailable = 256
 

Function Documentation

static uint32_t alignToARMConstant ( uint32_t  Value)
static

Get the minimum constant for ARM that is greater than or equal to the argument.

In ARM, constants can have any value that can be produced by rotating an 8-bit value to the right by an even number of bits within a 32-bit word.

Definition at line 1821 of file ARMFrameLowering.cpp.

Referenced by llvm::ARMFrameLowering::adjustForSegmentedStacks().

static void checkNumAlignedDPRCS2Regs ( MachineFunction MF,
BitVector SavedRegs 
)
static
static void emitAlignedDPRCS2Restores ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
unsigned  NumAlignedDPRCS2Regs,
const std::vector< CalleeSavedInfo > &  CSI,
const TargetRegisterInfo TRI 
)
static
static void emitAlignedDPRCS2Spills ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
unsigned  NumAlignedDPRCS2Regs,
const std::vector< CalleeSavedInfo > &  CSI,
const TargetRegisterInfo TRI 
)
static
static void emitAligningInstructions ( MachineFunction MF,
ARMFunctionInfo AFI,
const TargetInstrInfo TII,
MachineBasicBlock MBB,
MachineBasicBlock::iterator  MBBI,
DebugLoc  DL,
const unsigned  Reg,
const unsigned  Alignment,
const bool  MustBeSingleInstruction 
)
static

Emit an instruction sequence that will align the address in register Reg by zero-ing out the lower bits.

For versions of the architecture that support Neon, this must be done in a single instruction, since skipAlignedDPRCS2Spills assumes it is done in a single instruction. That function only gets called when optimizing spilling of D registers on a core with the Neon instruction set present.

Definition at line 233 of file ARMFrameLowering.cpp.

References llvm::AddDefaultCC(), llvm::AddDefaultPred(), llvm::MachineInstrBuilder::addImm(), llvm::BuildMI(), llvm::countTrailingZeros(), llvm::MCInstrInfo::get(), llvm::ARM_AM::getSORegOpc(), llvm::MachineFunction::getSubtarget(), llvm::ARMSubtarget::hasV6T2Ops(), llvm::ARMSubtarget::hasV7Ops(), llvm::ARMFunctionInfo::isThumb1OnlyFunction(), llvm::ARMFunctionInfo::isThumbFunction(), llvm::RegState::Kill, llvm::ARM_AM::lsl, and llvm::ARM_AM::lsr.

Referenced by emitAlignedDPRCS2Spills(), and llvm::ARMFrameLowering::emitPrologue().

static void emitRegPlusImmediate ( bool  isARM,
MachineBasicBlock MBB,
MachineBasicBlock::iterator MBBI,
DebugLoc  dl,
const ARMBaseInstrInfo TII,
unsigned  DestReg,
unsigned  SrcReg,
int  NumBytes,
unsigned  MIFlags = MachineInstr::NoFlags,
ARMCC::CondCodes  Pred = ARMCC::AL,
unsigned  PredReg = 0 
)
static
static void emitSPUpdate ( bool  isARM,
MachineBasicBlock MBB,
MachineBasicBlock::iterator MBBI,
DebugLoc  dl,
const ARMBaseInstrInfo TII,
int  NumBytes,
unsigned  MIFlags = MachineInstr::NoFlags,
ARMCC::CondCodes  Pred = ARMCC::AL,
unsigned  PredReg = 0 
)
static
static unsigned estimateRSStackSizeLimit ( MachineFunction MF,
const TargetFrameLowering TFI 
)
static

estimateRSStackSizeLimit - Look at each instruction that references stack frames and return the stack size limit beyond which some of these instructions will require a scratch register during their expansion later.

Definition at line 1420 of file ARMFrameLowering.cpp.

References llvm::ARMII::AddrMode3, llvm::ARMII::AddrMode4, llvm::ARMII::AddrMode5, llvm::ARMII::AddrMode6, llvm::ARMII::AddrModeMask, llvm::ARMII::AddrModeT2_i12, llvm::ARMII::AddrModeT2_i8, llvm::ARMII::AddrModeT2_i8s4, llvm::MachineFunction::getInfo(), llvm::TargetFrameLowering::hasFP(), llvm::ARMFunctionInfo::hasStackFrame(), and fuzzer::min().

Referenced by llvm::ARMFrameLowering::determineCalleeSaves().

static unsigned GetFunctionSizeInBytes ( const MachineFunction MF,
const ARMBaseInstrInfo TII 
)
static
static bool isCSRestore ( MachineInstr MI,
const ARMBaseInstrInfo TII,
const MCPhysReg CSRegs 
)
static
static int sizeOfSPAdjustment ( const MachineInstr MI)
static
static MachineBasicBlock::iterator skipAlignedDPRCS2Spills ( MachineBasicBlock::iterator  MI,
unsigned  NumAlignedDPRCS2Regs 
)
static

Skip past the code inserted by emitAlignedDPRCS2Spills, and return an iterator to the following instruction.

Definition at line 1237 of file ARMFrameLowering.cpp.

References llvm::AArch64CC::MI, and R4.

Referenced by llvm::ARMFrameLowering::emitPrologue().

static bool WindowsRequiresStackProbe ( const MachineFunction MF,
size_t  StackSizeInBytes 
)
static

Variable Documentation

const uint64_t kSplitStackAvailable = 256
static
cl::opt<bool> SpillAlignedNEONRegs("align-neon-spills", cl::Hidden, cl::init(true), cl::desc("Align ARM NEON spills in prolog and epilog"))
static