24 using namespace Hexagon;
26 #define DEBUG_TYPE "hexagon-asm-backend"
33 mutable uint64_t relaxedCnt;
34 std::unique_ptr <MCInstrInfo> MCII;
35 std::unique_ptr <MCInst *> RelaxTarget;
44 unsigned getNumFixupKinds()
const override {
57 {
"fixup_Hexagon_LO16", 0, 32, 0},
58 {
"fixup_Hexagon_HI16", 0, 32, 0},
59 {
"fixup_Hexagon_32", 0, 32, 0},
60 {
"fixup_Hexagon_16", 0, 32, 0},
61 {
"fixup_Hexagon_8", 0, 32, 0},
62 {
"fixup_Hexagon_GPREL16_0", 0, 32, 0},
63 {
"fixup_Hexagon_GPREL16_1", 0, 32, 0},
64 {
"fixup_Hexagon_GPREL16_2", 0, 32, 0},
65 {
"fixup_Hexagon_GPREL16_3", 0, 32, 0},
66 {
"fixup_Hexagon_HL16", 0, 32, 0},
70 {
"fixup_Hexagon_32_6_X", 0, 32, 0},
76 {
"fixup_Hexagon_16_X", 0, 32, 0},
77 {
"fixup_Hexagon_12_X", 0, 32, 0},
78 {
"fixup_Hexagon_11_X", 0, 32, 0},
79 {
"fixup_Hexagon_10_X", 0, 32, 0},
80 {
"fixup_Hexagon_9_X", 0, 32, 0},
81 {
"fixup_Hexagon_8_X", 0, 32, 0},
82 {
"fixup_Hexagon_7_X", 0, 32, 0},
83 {
"fixup_Hexagon_6_X", 0, 32, 0},
85 {
"fixup_Hexagon_COPY", 0, 32, 0},
86 {
"fixup_Hexagon_GLOB_DAT", 0, 32, 0},
87 {
"fixup_Hexagon_JMP_SLOT", 0, 32, 0},
88 {
"fixup_Hexagon_RELATIVE", 0, 32, 0},
90 {
"fixup_Hexagon_GOTREL_LO16", 0, 32, 0},
91 {
"fixup_Hexagon_GOTREL_HI16", 0, 32, 0},
92 {
"fixup_Hexagon_GOTREL_32", 0, 32, 0},
93 {
"fixup_Hexagon_GOT_LO16", 0, 32, 0},
94 {
"fixup_Hexagon_GOT_HI16", 0, 32, 0},
95 {
"fixup_Hexagon_GOT_32", 0, 32, 0},
96 {
"fixup_Hexagon_GOT_16", 0, 32, 0},
97 {
"fixup_Hexagon_DTPMOD_32", 0, 32, 0},
98 {
"fixup_Hexagon_DTPREL_LO16", 0, 32, 0},
99 {
"fixup_Hexagon_DTPREL_HI16", 0, 32, 0},
100 {
"fixup_Hexagon_DTPREL_32", 0, 32, 0},
101 {
"fixup_Hexagon_DTPREL_16", 0, 32, 0},
104 {
"fixup_Hexagon_GD_GOT_LO16", 0, 32, 0},
105 {
"fixup_Hexagon_GD_GOT_HI16", 0, 32, 0},
106 {
"fixup_Hexagon_GD_GOT_32", 0, 32, 0},
107 {
"fixup_Hexagon_GD_GOT_16", 0, 32, 0},
108 {
"fixup_Hexagon_LD_GOT_LO16", 0, 32, 0},
109 {
"fixup_Hexagon_LD_GOT_HI16", 0, 32, 0},
110 {
"fixup_Hexagon_LD_GOT_32", 0, 32, 0},
111 {
"fixup_Hexagon_LD_GOT_16", 0, 32, 0},
112 {
"fixup_Hexagon_IE_LO16", 0, 32, 0},
113 {
"fixup_Hexagon_IE_HI16", 0, 32, 0},
114 {
"fixup_Hexagon_IE_32", 0, 32, 0},
115 {
"fixup_Hexagon_IE_16", 0, 32, 0},
116 {
"fixup_Hexagon_IE_GOT_LO16", 0, 32, 0},
117 {
"fixup_Hexagon_IE_GOT_HI16", 0, 32, 0},
118 {
"fixup_Hexagon_IE_GOT_32", 0, 32, 0},
119 {
"fixup_Hexagon_IE_GOT_16", 0, 32, 0},
120 {
"fixup_Hexagon_TPREL_LO16", 0, 32, 0},
121 {
"fixup_Hexagon_TPREL_HI16", 0, 32, 0},
122 {
"fixup_Hexagon_TPREL_32", 0, 32, 0},
123 {
"fixup_Hexagon_TPREL_16", 0, 32, 0},
125 {
"fixup_Hexagon_GOTREL_32_6_X", 0, 32, 0},
126 {
"fixup_Hexagon_GOTREL_16_X", 0, 32, 0},
127 {
"fixup_Hexagon_GOTREL_11_X", 0, 32, 0},
128 {
"fixup_Hexagon_GOT_32_6_X", 0, 32, 0},
129 {
"fixup_Hexagon_GOT_16_X", 0, 32, 0},
130 {
"fixup_Hexagon_GOT_11_X", 0, 32, 0},
131 {
"fixup_Hexagon_DTPREL_32_6_X", 0, 32, 0},
132 {
"fixup_Hexagon_DTPREL_16_X", 0, 32, 0},
133 {
"fixup_Hexagon_DTPREL_11_X", 0, 32, 0},
134 {
"fixup_Hexagon_GD_GOT_32_6_X", 0, 32, 0},
135 {
"fixup_Hexagon_GD_GOT_16_X", 0, 32, 0},
136 {
"fixup_Hexagon_GD_GOT_11_X", 0, 32, 0},
137 {
"fixup_Hexagon_LD_GOT_32_6_X", 0, 32, 0},
138 {
"fixup_Hexagon_LD_GOT_16_X", 0, 32, 0},
139 {
"fixup_Hexagon_LD_GOT_11_X", 0, 32, 0},
140 {
"fixup_Hexagon_IE_32_6_X", 0, 32, 0},
141 {
"fixup_Hexagon_IE_16_X", 0, 32, 0},
142 {
"fixup_Hexagon_IE_GOT_32_6_X", 0, 32, 0},
143 {
"fixup_Hexagon_IE_GOT_16_X", 0, 32, 0},
144 {
"fixup_Hexagon_IE_GOT_11_X", 0, 32, 0},
145 {
"fixup_Hexagon_TPREL_32_6_X", 0, 32, 0},
146 {
"fixup_Hexagon_TPREL_16_X", 0, 32, 0},
147 {
"fixup_Hexagon_TPREL_11_X", 0, 32, 0}};
158 void applyFixup(
MCFixup const & ,
char * ,
159 unsigned , uint64_t ,
160 bool )
const override {
164 bool isInstRelaxable(
MCInst const &HMI)
const {
166 bool Relaxable =
false;
183 bool mayNeedRelaxation(
MCInst const &Inst)
const override {
185 bool PreviousIsExtender =
false;
187 auto const &Inst = *
I.getInst();
188 if (!PreviousIsExtender) {
189 if (isInstRelaxable(Inst))
199 bool fixupNeedsRelaxationAdvanced(
const MCFixup &
Fixup,
bool Resolved,
206 *RelaxTarget =
nullptr;
211 switch ((
unsigned)Fixup.
getKind()) {
233 bool Relaxable = isInstRelaxable(MCI);
234 if (Relaxable ==
false)
238 int64_t sValue = Value;
241 switch ((
unsigned)Kind) {
255 maxValue = INT64_MAX;
259 bool isFarAway = -maxValue > sValue || sValue > maxValue - 1;
273 bool fixupNeedsRelaxation(
const MCFixup &Fixup, uint64_t Value,
279 void relaxInstruction(
MCInst const & ,
280 MCInst & )
const override {
284 bool writeNopData(uint64_t Count,
286 static const uint32_t Nopcode = 0x7f000000,
287 ParseIn = 0x00004000,
288 ParseEnd = 0x0000c000;
291 DEBUG(
dbgs() <<
"Alignment not a multiple of the instruction size:" <<
292 Count % HEXAGON_INSTR_SIZE <<
"/" << HEXAGON_INSTR_SIZE <<
"\n");
302 OW->
write32(Nopcode | ParseBits);
314 return new HexagonAsmBackend(T, OSABI, CPU);
OSType getOS() const
getOS - Get the parsed operating system type of this triple.
Describe properties that are true of each instruction in the target description file.
bool isBundle(MCInst const &MCI)
Defines the object file and target independent interfaces used by the assembler backend to write nati...
void write8(uint8_t Value)
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
const MCInst & getInst() const
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...
MCInstrInfo * createMCInstrInfo() const
createMCInstrInfo - Create a MCInstrInfo implementation.
bool isImmext(MCInst const &MCI)
MCInst const & instruction(MCInst const &MCB, size_t Index)
Encapsulates the layout of an assembly file at a particular point in time.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
#define HEXAGON_PACKET_SIZE
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
MCAsmBackend * createHexagonAsmBackend(Target const &T, MCRegisterInfo const &, const Triple &TT, StringRef CPU)
uint32_t getOffset() const
MCObjectWriter * createHexagonELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI, StringRef CPU)
Instances of this class represent a single low-level machine instruction.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
void write32(uint32_t Value)
MCFixupKind
Extensible enumeration to represent the type of a fixup.
iterator_range< MCInst::const_iterator > bundleInstructions(MCInst const &MCI)
MCFixupKind getKind() const
Triple - Helper class for working with autoconf configuration names.
PowerPC TLS Dynamic Call Fixup
bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
unsigned getOpcode() const
Target - Wrapper for Target specific information.
MCInstrDesc const & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
size_t bundleSize(MCInst const &MCI)
Target independent information on a fixup kind.
An abstract base class for streams implementations that also support a pwrite operation.
const ARM::ArchExtKind Kind
#define HEXAGON_INSTR_SIZE
LLVM Value Representation.
Generic interface to target specific assembler backends.
StringRef - Represent a constant reference to a string, i.e.
unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI)
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.