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LLVM
3.7.0
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#include "llvm/CodeGen/SchedulerRegistry.h"#include "ScheduleDAGSDNodes.h"#include "llvm/ADT/STLExtras.h"#include "llvm/ADT/SmallSet.h"#include "llvm/ADT/Statistic.h"#include "llvm/CodeGen/MachineRegisterInfo.h"#include "llvm/CodeGen/ScheduleHazardRecognizer.h"#include "llvm/CodeGen/SelectionDAGISel.h"#include "llvm/IR/DataLayout.h"#include "llvm/IR/InlineAsm.h"#include "llvm/Support/Debug.h"#include "llvm/Support/ErrorHandling.h"#include "llvm/Support/raw_ostream.h"#include "llvm/Target/TargetInstrInfo.h"#include "llvm/Target/TargetLowering.h"#include "llvm/Target/TargetRegisterInfo.h"#include "llvm/Target/TargetSubtargetInfo.h"#include <climits>Go to the source code of this file.
Macros | |
| #define | DEBUG_TYPE "pre-RA-sched" |
Functions | |
| STATISTIC (NumBacktracks,"Number of times scheduler backtracked") | |
| STATISTIC (NumUnfolds,"Number of nodes unfolded") | |
| STATISTIC (NumDups,"Number of duplicated nodes") | |
| STATISTIC (NumPRCopies,"Number of physical register copies") | |
| static void | GetCostForDef (const ScheduleDAGSDNodes::RegDefIter &RegDefPos, const TargetLowering *TLI, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, unsigned &RegClass, unsigned &Cost, const MachineFunction &MF) |
| GetCostForDef - Looks up the register class and cost for a given definition. More... | |
| static bool | IsChainDependent (SDNode *Outer, SDNode *Inner, unsigned NestLevel, const TargetInstrInfo *TII) |
| IsChainDependent - Test if Outer is reachable from Inner through chain dependencies. More... | |
| static SDNode * | FindCallSeqStart (SDNode *N, unsigned &NestLevel, unsigned &MaxNest, const TargetInstrInfo *TII) |
| FindCallSeqStart - Starting from the (lowered) CALLSEQ_END node, locate the corresponding (lowered) CALLSEQ_BEGIN node. More... | |
| static void | resetVRegCycle (SUnit *SU) |
| static bool | isOperandOf (const SUnit *SU, SDNode *N) |
| static MVT | getPhysicalRegisterVT (SDNode *N, unsigned Reg, const TargetInstrInfo *TII) |
| getPhysicalRegisterVT - Returns the ValueType of the physical register definition of the specified node. More... | |
| static void | CheckForLiveRegDef (SUnit *SU, unsigned Reg, std::vector< SUnit * > &LiveRegDefs, SmallSet< unsigned, 4 > &RegAdded, SmallVectorImpl< unsigned > &LRegs, const TargetRegisterInfo *TRI) |
| CheckForLiveRegDef - Return true and update live register vector if the specified register def of the specified SUnit clobbers any "live" registers. More... | |
| static void | CheckForLiveRegDefMasked (SUnit *SU, const uint32_t *RegMask, std::vector< SUnit * > &LiveRegDefs, SmallSet< unsigned, 4 > &RegAdded, SmallVectorImpl< unsigned > &LRegs) |
| CheckForLiveRegDefMasked - Check for any live physregs that are clobbered by RegMask, and add them to LRegs. More... | |
| static const uint32_t * | getNodeRegMask (const SDNode *N) |
| getNodeRegMask - Returns the register mask attached to an SDNode, if any. More... | |
| static int | checkSpecialNodes (const SUnit *left, const SUnit *right) |
| static unsigned | CalcNodeSethiUllmanNumber (const SUnit *SU, std::vector< unsigned > &SUNumbers) |
| CalcNodeSethiUllmanNumber - Compute Sethi Ullman number. More... | |
| static unsigned | closestSucc (const SUnit *SU) |
| closestSucc - Returns the scheduled cycle of the successor which is closest to the current cycle. More... | |
| static unsigned | calcMaxScratches (const SUnit *SU) |
| calcMaxScratches - Returns an cost estimate of the worse case requirement for scratch registers, i.e. More... | |
| static bool | hasOnlyLiveInOpers (const SUnit *SU) |
| hasOnlyLiveInOpers - Return true if SU has only value predecessors that are CopyFromReg from a virtual register. More... | |
| static bool | hasOnlyLiveOutUses (const SUnit *SU) |
| hasOnlyLiveOutUses - Return true if SU has only value successors that are CopyToReg to a virtual register. More... | |
| static void | initVRegCycle (SUnit *SU) |
| static bool | hasVRegCycleUse (const SUnit *SU) |
| static bool | BUHasStall (SUnit *SU, int Height, RegReductionPQBase *SPQ) |
| static int | BUCompareLatency (SUnit *left, SUnit *right, bool checkPref, RegReductionPQBase *SPQ) |
| static bool | BURRSort (SUnit *left, SUnit *right, RegReductionPQBase *SPQ) |
| static bool | canEnableCoalescing (SUnit *SU) |
| static bool | canClobberReachingPhysRegUse (const SUnit *DepSU, const SUnit *SU, ScheduleDAGRRList *scheduleDAG, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) |
| canClobberReachingPhysRegUse - True if SU would clobber one of it's successor's explicit physregs whose definition can reach DepSU. More... | |
| static bool | canClobberPhysRegDefs (const SUnit *SuccSU, const SUnit *SU, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) |
| canClobberPhysRegDefs - True if SU would clobber one of SuccSU's physical register defs. More... | |
Variables | |
| static RegisterScheduler | burrListDAGScheduler ("list-burr","Bottom-up register reduction list scheduling", createBURRListDAGScheduler) |
| static RegisterScheduler | sourceListDAGScheduler ("source","Similar to list-burr but schedules in source ""order when possible", createSourceListDAGScheduler) |
| static RegisterScheduler | hybridListDAGScheduler ("list-hybrid","Bottom-up register pressure aware list scheduling ""which tries to balance latency and register pressure", createHybridListDAGScheduler) |
| static RegisterScheduler | ILPListDAGScheduler ("list-ilp","Bottom-up register pressure aware list scheduling ""which tries to balance ILP and register pressure", createILPListDAGScheduler) |
| static cl::opt< bool > | DisableSchedCycles ("disable-sched-cycles", cl::Hidden, cl::init(false), cl::desc("Disable cycle-level precision during preRA scheduling")) |
| static cl::opt< bool > | DisableSchedRegPressure ("disable-sched-reg-pressure", cl::Hidden, cl::init(false), cl::desc("Disable regpressure priority in sched=list-ilp")) |
| static cl::opt< bool > | DisableSchedLiveUses ("disable-sched-live-uses", cl::Hidden, cl::init(true), cl::desc("Disable live use priority in sched=list-ilp")) |
| static cl::opt< bool > | DisableSchedVRegCycle ("disable-sched-vrcycle", cl::Hidden, cl::init(false), cl::desc("Disable virtual register cycle interference checks")) |
| static cl::opt< bool > | DisableSchedPhysRegJoin ("disable-sched-physreg-join", cl::Hidden, cl::init(false), cl::desc("Disable physreg def-use affinity")) |
| static cl::opt< bool > | DisableSchedStalls ("disable-sched-stalls", cl::Hidden, cl::init(true), cl::desc("Disable no-stall priority in sched=list-ilp")) |
| static cl::opt< bool > | DisableSchedCriticalPath ("disable-sched-critical-path", cl::Hidden, cl::init(false), cl::desc("Disable critical path priority in sched=list-ilp")) |
| static cl::opt< bool > | DisableSchedHeight ("disable-sched-height", cl::Hidden, cl::init(false), cl::desc("Disable scheduled-height priority in sched=list-ilp")) |
| static cl::opt< bool > | Disable2AddrHack ("disable-2addr-hack", cl::Hidden, cl::init(true), cl::desc("Disable scheduler's two-address hack")) |
| static cl::opt< int > | MaxReorderWindow ("max-sched-reorder", cl::Hidden, cl::init(6), cl::desc("Number of instructions to allow ahead of the critical path ""in sched=list-ilp")) |
| static cl::opt< unsigned > | AvgIPC ("sched-avg-ipc", cl::Hidden, cl::init(1), cl::desc("Average inst/cycle whan no target itinerary exists.")) |
| #define DEBUG_TYPE "pre-RA-sched" |
Definition at line 38 of file ScheduleDAGRRList.cpp.
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Definition at line 2351 of file ScheduleDAGRRList.cpp.
References BUHasStall(), llvm::dbgs(), DEBUG, llvm::SUnit::getDepth(), llvm::SUnit::getHeight(), hasVRegCycleUse(), llvm::Sched::ILP, llvm::SUnit::Latency, llvm::SUnit::NodeNum, and llvm::SUnit::SchedulingPref.
Referenced by BURRSort().
Definition at line 2341 of file ScheduleDAGRRList.cpp.
References llvm::ScheduleHazardRecognizer::NoHazard.
Referenced by BUCompareLatency().
Definition at line 2402 of file ScheduleDAGRRList.cpp.
References BUCompareLatency(), calcMaxScratches(), closestSucc(), llvm::dbgs(), DEBUG, DisableSchedCycles, DisableSchedPhysRegJoin, llvm::SUnit::getDepth(), llvm::SUnit::getHeight(), llvm::SUnit::getNode(), llvm::SDNode::getNumValues(), llvm::SUnit::hasPhysRegDefs, llvm::SUnit::isCall, llvm::SUnit::isCallOp, llvm::SUnit::NodeNum, and llvm::SUnit::NodeQueueId.
calcMaxScratches - Returns an cost estimate of the worse case requirement for scratch registers, i.e.
number of data dependencies.
Definition at line 2219 of file ScheduleDAGRRList.cpp.
References I, and llvm::SUnit::Preds.
Referenced by BURRSort().
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CalcNodeSethiUllmanNumber - Compute Sethi Ullman number.
Smaller number is the higher priority.
Definition at line 1849 of file ScheduleDAGRRList.cpp.
References I, llvm::SUnit::NodeNum, and llvm::SUnit::Preds.
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canClobberPhysRegDefs - True if SU would clobber one of SuccSU's physical register defs.
Definition at line 2754 of file ScheduleDAGRRList.cpp.
References llvm::MachineOperand::clobbersPhysReg(), llvm::MCInstrInfo::get(), llvm::SDNode::getGluedNode(), llvm::SDNode::getMachineOpcode(), llvm::SUnit::getNode(), getNodeRegMask(), llvm::SDNode::getNumValues(), llvm::SDNode::getSimpleValueType(), llvm::MVT::Glue, llvm::SDNode::hasAnyUseOfValue(), llvm::MVT::Other, and llvm::TargetRegisterInfo::regsOverlap().
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canClobberReachingPhysRegUse - True if SU would clobber one of it's successor's explicit physregs whose definition can reach DepSU.
i.e. DepSU should not be scheduled above SU.
Definition at line 2717 of file ScheduleDAGRRList.cpp.
References llvm::MachineOperand::clobbersPhysReg(), llvm::MCInstrInfo::get(), llvm::SDNode::getMachineOpcode(), llvm::SUnit::getNode(), getNodeRegMask(), llvm::SUnit::Preds, llvm::TargetRegisterInfo::regsOverlap(), SI, and llvm::SUnit::Succs.
Definition at line 2590 of file ScheduleDAGRRList.cpp.
References llvm::ISD::CopyToReg, llvm::TargetOpcode::EXTRACT_SUBREG, llvm::SUnit::getNode(), llvm::SDNode::getOpcode(), llvm::TargetOpcode::INSERT_SUBREG, llvm::SUnit::NumPreds, llvm::SUnit::NumSuccs, llvm::TargetOpcode::SUBREG_TO_REG, and llvm::ISD::TokenFactor.
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CheckForLiveRegDef - Return true and update live register vector if the specified register def of the specified SUnit clobbers any "live" registers.
Definition at line 1220 of file ScheduleDAGRRList.cpp.
References llvm::SmallSet< T, N, C >::insert(), llvm::MCRegAliasIterator::isValid(), and llvm::SmallVectorTemplateBase< T, isPodLike >::push_back().
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CheckForLiveRegDefMasked - Check for any live physregs that are clobbered by RegMask, and add them to LRegs.
Definition at line 1242 of file ScheduleDAGRRList.cpp.
References llvm::MachineOperand::clobbersPhysReg(), llvm::SmallSet< T, N, C >::insert(), and llvm::SmallVectorTemplateBase< T, isPodLike >::push_back().
Definition at line 1838 of file ScheduleDAGRRList.cpp.
References llvm::SUnit::isScheduleLow.
closestSucc - Returns the scheduled cycle of the successor which is closest to the current cycle.
Definition at line 2200 of file ScheduleDAGRRList.cpp.
References llvm::ISD::CopyToReg, I, and llvm::SUnit::Succs.
Referenced by BURRSort().
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FindCallSeqStart - Starting from the (lowered) CALLSEQ_END node, locate the corresponding (lowered) CALLSEQ_BEGIN node.
NestLevel and MaxNested are used in recursion to indcate the current level of nesting of CALLSEQ_BEGIN and CALLSEQ_END pairs, as well as the maximum level seen so far.
TODO: It would be better to give CALLSEQ_END an explicit operand to point to the corresponding CALLSEQ_BEGIN to avoid needing to search for it.
Definition at line 458 of file ScheduleDAGRRList.cpp.
References llvm::ISD::EntryToken, llvm::TargetInstrInfo::getCallFrameDestroyOpcode(), llvm::TargetInstrInfo::getCallFrameSetupOpcode(), llvm::SDNode::getMachineOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::isMachineOpcode(), N, llvm::SDNode::op_values(), llvm::MVT::Other, TII, and llvm::ISD::TokenFactor.
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GetCostForDef - Looks up the register class and cost for a given definition.
Typically this just means looking up the representative register class, but for untyped values (MVT::Untyped) it means inspecting the node's opcode to determine what register class is being generated.
Definition at line 275 of file ScheduleDAGRRList.cpp.
References llvm::ISD::CopyFromReg, llvm::MCInstrInfo::get(), llvm::TargetRegisterClass::getID(), llvm::ScheduleDAGSDNodes::RegDefIter::GetIdx(), llvm::SDNode::getMachineOpcode(), llvm::ScheduleDAGSDNodes::RegDefIter::GetNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), getReg(), llvm::TargetInstrInfo::getRegClass(), llvm::MachineRegisterInfo::getRegClass(), llvm::TargetRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::TargetLoweringBase::getRepRegClassCostFor(), llvm::TargetLoweringBase::getRepRegClassFor(), llvm::ScheduleDAGSDNodes::RegDefIter::GetValue(), llvm::SDNode::isMachineOpcode(), llvm::TargetOpcode::REG_SEQUENCE, and llvm::MVT::Untyped.
getNodeRegMask - Returns the register mask attached to an SDNode, if any.
Definition at line 1257 of file ScheduleDAGRRList.cpp.
References llvm::SDNode::op_values().
Referenced by canClobberPhysRegDefs(), and canClobberReachingPhysRegUse().
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getPhysicalRegisterVT - Returns the ValueType of the physical register definition of the specified node.
FIXME: Move to SelectionDAG?
Definition at line 1199 of file ScheduleDAGRRList.cpp.
References llvm::ISD::CopyFromReg, llvm::MCInstrInfo::get(), llvm::MCInstrDesc::getImplicitDefs(), llvm::SDNode::getMachineOpcode(), llvm::MCInstrDesc::getNumDefs(), llvm::SDNode::getOpcode(), llvm::SDNode::getSimpleValueType(), and llvm::MCInstrDesc::ImplicitDefs.
hasOnlyLiveInOpers - Return true if SU has only value predecessors that are CopyFromReg from a virtual register.
Definition at line 2231 of file ScheduleDAGRRList.cpp.
References llvm::ISD::CopyFromReg, llvm::SUnit::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), getReg(), I, llvm::TargetRegisterInfo::isVirtualRegister(), and llvm::SUnit::Preds.
Referenced by initVRegCycle().
hasOnlyLiveOutUses - Return true if SU has only value successors that are CopyToReg to a virtual register.
This SU def is probably a liveout and it has no other use. It should be scheduled closer to the terminator.
Definition at line 2254 of file ScheduleDAGRRList.cpp.
References llvm::ISD::CopyToReg, llvm::SUnit::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), getReg(), I, llvm::TargetRegisterInfo::isVirtualRegister(), and llvm::SUnit::Succs.
Referenced by initVRegCycle().
Definition at line 2321 of file ScheduleDAGRRList.cpp.
References llvm::ISD::CopyFromReg, llvm::dbgs(), DEBUG, I, llvm::SUnit::isVRegCycle, llvm::SUnit::NodeNum, and llvm::SUnit::Preds.
Referenced by BUCompareLatency().
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Definition at line 2283 of file ScheduleDAGRRList.cpp.
References llvm::dbgs(), DEBUG, DisableSchedVRegCycle, hasOnlyLiveInOpers(), hasOnlyLiveOutUses(), I, llvm::SUnit::isVRegCycle, llvm::SUnit::NodeNum, and llvm::SUnit::Preds.
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IsChainDependent - Test if Outer is reachable from Inner through chain dependencies.
Definition at line 407 of file ScheduleDAGRRList.cpp.
References llvm::ISD::EntryToken, llvm::TargetInstrInfo::getCallFrameDestroyOpcode(), llvm::TargetInstrInfo::getCallFrameSetupOpcode(), llvm::SDNode::getMachineOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::isMachineOpcode(), llvm::SDNode::op_values(), llvm::MVT::Other, TII, and llvm::ISD::TokenFactor.
Definition at line 935 of file ScheduleDAGRRList.cpp.
References llvm::SDNode::getGluedNode(), and llvm::SUnit::getNode().
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Definition at line 2303 of file ScheduleDAGRRList.cpp.
References llvm::ISD::CopyFromReg, llvm::SUnit::getNode(), llvm::SDNode::getOpcode(), I, llvm::SUnit::isVRegCycle, and llvm::SUnit::Preds.
| STATISTIC | ( | NumBacktracks | , |
| "Number of times scheduler backtracked" | |||
| ) |
| STATISTIC | ( | NumUnfolds | , |
| "Number of nodes unfolded" | |||
| ) |
| STATISTIC | ( | NumDups | , |
| "Number of duplicated nodes" | |||
| ) |
| STATISTIC | ( | NumPRCopies | , |
| "Number of physical register copies" | |||
| ) |
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Referenced by BURRSort().
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Referenced by BURRSort().
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Referenced by initVRegCycle().
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1.8.6