45 #define DEBUG_TYPE "regalloc"
50 "Live Interval Analysis",
false,
false)
61 cl::desc(
"Eagerly compute live intervals for all physreg units."));
68 cl::desc(
"Enable subregister liveness tracking."));
74 "Use segment set for the computation of the live ranges of physregs."));
95 DomTree(nullptr), LRCalc(nullptr) {
105 for (
unsigned i = 0, e = VirtRegIntervals.size(); i != e; ++i)
107 VirtRegIntervals.clear();
108 RegMaskSlots.clear();
110 RegMaskBlocks.
clear();
112 for (
unsigned i = 0, e = RegUnitRanges.size(); i != e; ++i)
113 delete RegUnitRanges[i];
114 RegUnitRanges.clear();
117 VNInfoAllocator.
Reset();
127 AA = &getAnalysis<AliasAnalysis>();
128 Indexes = &getAnalysis<SlotIndexes>();
129 DomTree = &getAnalysis<MachineDominatorTree>();
142 computeLiveInRegUnits();
156 OS <<
"********** INTERVALS **********\n";
159 for (
unsigned i = 0, e = RegUnitRanges.size(); i != e; ++i)
171 for (
unsigned i = 0, e = RegMaskSlots.size(); i != e; ++i)
172 OS <<
' ' << RegMaskSlots[i];
178 void LiveIntervals::printInstrs(
raw_ostream &OS)
const {
179 OS <<
"********** MACHINEINSTRS **********\n";
180 MF->
print(OS, Indexes);
183 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
184 void LiveIntervals::dumpInstrs()
const {
189 LiveInterval* LiveIntervals::createInterval(
unsigned reg) {
198 void LiveIntervals::computeVirtRegInterval(
LiveInterval &LI) {
199 assert(LRCalc &&
"LRCalc not initialized.");
200 assert(LI.
empty() &&
"Should only compute empty intervals.");
203 computeDeadValues(LI,
nullptr);
206 void LiveIntervals::computeVirtRegs() {
215 void LiveIntervals::computeRegMasks() {
222 std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[MBB->
getNumber()];
223 RMB.first = RegMaskSlots.size();
233 RMB.second = RegMaskSlots.size() - RMB.first;
251 void LiveIntervals::computeRegUnitRange(
LiveRange &LR,
unsigned Unit) {
252 assert(LRCalc &&
"LRCalc not initialized.");
273 unsigned Reg = *Supers;
275 LRCalc->extendToUses(LR, Reg);
289 void LiveIntervals::computeLiveInRegUnits() {
291 DEBUG(
dbgs() <<
"Computing live-in reg-units in ABI blocks.\n");
311 unsigned Unit = *Units;
325 DEBUG(
dbgs() <<
"Created " << NewRanges.
size() <<
" new intervals.\n");
328 for (
unsigned i = 0, e = NewRanges.
size(); i != e; ++i) {
329 unsigned Unit = NewRanges[i];
330 computeRegUnitRange(*RegUnitRanges[Unit], Unit);
337 for (
auto VNI : VNIs) {
356 while (!WorkList.
empty()) {
365 assert(ExtVNI == VNI &&
"Unexpected existing value number");
369 !UsedPHIs.
insert(VNI).second)
373 if (!LiveOut.
insert(Pred).second)
378 WorkList.
push_back(std::make_pair(Stop, PVNI));
384 DEBUG(
dbgs() <<
" live-in at " << BlockStart <<
'\n');
389 if (!LiveOut.
insert(Pred).second)
393 "Wrong value out of predecessor");
394 WorkList.
push_back(std::make_pair(Stop, VNI));
404 DEBUG(
dbgs() <<
"Shrink: " << *li <<
'\n');
406 &&
"Can only shrink virtual registers");
431 <<
"Warning: Instr claims to read non-existent value in "
440 WorkList.
push_back(std::make_pair(Idx, VNI));
452 bool CanSeparate = computeDeadValues(*li, dead);
453 DEBUG(
dbgs() <<
"Shrunk: " << *li <<
'\n');
459 bool PHIRemoved =
false;
460 for (
auto VNI : LI.
valnos) {
465 assert(I != LI.
end() &&
"Missing segment for VNI");
482 DEBUG(
dbgs() <<
"Dead PHI at " << Def <<
" may separate interval\n");
487 assert(MI &&
"No instruction defining live value");
490 DEBUG(
dbgs() <<
"All defs dead: " << Def <<
'\t' << *MI);
500 DEBUG(
dbgs() <<
"Shrink: " << SR <<
'\n');
502 &&
"Can only shrink virtual registers");
513 unsigned SubReg = MO.getSubReg();
516 if ((SubRegMask & SR.
LaneMask) == 0)
537 WorkList.
push_back(std::make_pair(Idx, VNI));
549 for (
auto VNI : SR.
valnos) {
553 assert(Segment !=
nullptr &&
"Missing segment for VNI");
560 DEBUG(
dbgs() <<
"Dead PHI at " << VNI->
def <<
" may separate interval\n");
564 DEBUG(
dbgs() <<
"Shrunk: " << SR <<
'\n');
569 assert(LRCalc &&
"LRCalc not initialized.");
571 for (
unsigned i = 0, e = Indices.
size(); i != e; ++i)
572 LRCalc->
extend(LR, Indices[i]);
594 if (EndPoints) EndPoints->
push_back(MBBEnd);
603 SuccI != SuccE; ++SuccI) {
611 std::tie(MBBStart, MBBEnd) = Indexes->
getMBBRange(MBB);
629 if (EndPoints) EndPoints->
push_back(MBBEnd);
667 for (
const LiveInterval::SubRange &SR : LI.
subranges()) {
668 SRs.push_back(std::make_pair(&SR, SR.find(LI.
begin()->end)));
677 if (RI->end.isBlock())
691 for (
auto &RUP : RU) {
693 LiveRange::const_iterator &I = RUP.second;
694 if (I == RURange.
end())
697 if (I == RURange.
end() || I->start >= RI->end)
715 unsigned DefinedLanesMask;
718 DefinedLanesMask = 0;
719 for (
auto &SRP : SRs) {
720 const LiveInterval::SubRange &SR = *SRP.first;
721 LiveRange::const_iterator &I = SRP.second;
725 if (I == SR.
end() || I->start >= RI->end)
731 DefinedLanesMask = ~0u;
733 bool IsFullWrite =
false;
735 if (!MO.isReg() || MO.getReg() !=
Reg)
740 if ((UseMask & ~DefinedLanesMask) != 0)
742 }
else if (MO.getSubReg() == 0) {
755 LiveRange::const_iterator
N = std::next(RI);
756 if (N != LI.
end() && N->start == RI->end)
790 return MBB1 == MBB2 ? MBB1 :
nullptr;
858 std::lower_bound(Slots.
begin(), Slots.
end(), LiveI->start);
867 assert(*SlotI >= LiveI->start);
869 while (*SlotI < LiveI->
end) {
879 if (++SlotI == SlotE)
887 while (*SlotI < LiveI->start)
888 if (++SlotI == SlotE)
912 : LIS(LIS), MRI(MRI), TRI(TRI), OldIdx(OldIdx), NewIdx(NewIdx),
913 UpdateFlags(UpdateFlags) {}
921 return &LIS.getRegUnit(Unit);
922 return LIS.getCachedRegUnit(Unit);
928 DEBUG(
dbgs() <<
"handleMove " << OldIdx <<
" -> " << NewIdx <<
": " << *MI);
929 bool hasRegMask =
false;
940 unsigned Reg = MO.getReg();
946 unsigned SubReg = MO.getSubReg();
947 unsigned LaneMask = TRI.getSubRegIndexLaneMask(SubReg);
949 if ((S.LaneMask & LaneMask) == 0)
951 updateRange(S, Reg, S.LaneMask);
954 updateRange(LI, Reg, 0);
962 updateRange(*LR, *Units, 0);
965 updateRegMaskSlots();
971 void updateRange(
LiveRange &LR,
unsigned Reg,
unsigned LaneMask) {
972 if (!Updated.insert(&LR).second)
983 dbgs() <<
":\t" << LR <<
'\n';
988 handleMoveUp(LR, Reg, LaneMask);
1030 if (
MachineInstr *KillMI = LIS.getInstructionFromIndex(I->end))
1032 if (MO->isReg() && MO->isUse())
1033 MO->setIsKill(
false);
1036 I->end = NewIdx.getRegSlot(I->end.isEarlyClobber());
1047 VNInfo *DefVNI = I->valno;
1048 assert(DefVNI->
def == I->start &&
"Inconsistent def");
1053 I->start = DefVNI->
def;
1060 assert((I->end == OldIdx.getDeadSlot() ||
1062 "Cannot move def below kill");
1067 assert(NewI->valno != DefVNI &&
"Multiple defs of value?");
1075 assert(NewI != I &&
"Inconsistent iterators");
1076 std::copy(std::next(I), NewI, I);
1101 void handleMoveUp(
LiveRange &LR,
unsigned Reg,
unsigned LaneMask) {
1116 I->end = NewIdx.getRegSlot(I->end.isEarlyClobber());
1122 std::prev(I)->end = findLastUseBefore(Reg, LaneMask).getRegSlot();
1129 VNInfo *DefVNI = I->valno;
1130 assert(DefVNI->
def == I->start &&
"Inconsistent def");
1136 assert(NewI->valno != DefVNI &&
"Same value defined more than once?");
1138 if (I->end.isDead()) {
1144 I->start = DefVNI->
def;
1150 if (!I->end.isDead()) {
1152 I->start = DefVNI->
def;
1158 std::copy_backward(NewI, I, std::next(I));
1162 void updateRegMaskSlots() {
1164 std::lower_bound(LIS.RegMaskSlots.begin(), LIS.RegMaskSlots.end(),
1166 assert(RI != LIS.RegMaskSlots.end() && *RI == OldIdx.getRegSlot() &&
1167 "No RegMask at OldIdx.");
1168 *RI = NewIdx.getRegSlot();
1169 assert((RI == LIS.RegMaskSlots.begin() ||
1171 "Cannot move regmask instruction above another call");
1172 assert((std::next(RI) == LIS.RegMaskSlots.end() ||
1174 "Cannot move regmask instruction below another call");
1178 SlotIndex findLastUseBefore(
unsigned Reg,
unsigned LaneMask) {
1183 unsigned SubReg = MO.getSubReg();
1184 if (SubReg != 0 && LaneMask != 0
1185 && (TRI.getSubRegIndexLaneMask(SubReg) & LaneMask) == 0)
1189 SlotIndex InstSlot = LIS.getSlotIndexes()->getInstructionIndex(MI);
1190 if (InstSlot > LastUse && InstSlot < OldIdx)
1198 assert(NewIdx < OldIdx &&
"Expected upwards move");
1211 while (MII != Begin) {
1212 if ((--MII)->isDebugValue())
1224 TRI.hasRegUnit(MO->getReg(),
Reg))
1233 assert(!MI->
isBundled() &&
"Can't handle bundled instructions yet.");
1239 "Cannot handle moves across basic block boundaries.");
1241 HMEditor HME(*
this, *MRI, *TRI, OldIndex, NewIndex, UpdateFlags);
1250 HMEditor HME(*
this, *MRI, *TRI, OldIndex, NewIndex, UpdateFlags);
1258 const unsigned LaneMask) {
1261 if (LII != LR.
end() && LII->start < endIdx)
1262 lastUseIdx = LII->end;
1286 if ((Mask & LaneMask) == 0)
1290 if (!isStartValid) {
1291 if (LII->end.isDead()) {
1293 if (LII != LR.
begin())
1294 prevStart = std::prev(LII)->start;
1300 LII = LR.
find(prevStart);
1319 }
else if (LII->start != instrIdx.
getRegSlot()) {
1329 }
else if (MO.
isUse()) {
1333 if (!isEndValid && !LII->end.isBlock())
1351 while (End != MBB->
end() && !Indexes->
hasIndex(End))
1355 if (End == MBB->
end())
1377 for (
unsigned i = 0, e = OrigRegs.
size(); i != e; ++i) {
1378 unsigned Reg = OrigRegs[i];
1388 repairOldRegInRange(Begin, End, endIdx, S, Reg, S.LaneMask);
1390 repairOldRegInRange(Begin, End, endIdx, LI, Reg);
1410 if (
VNInfo *SVNI = S.getVNInfoAt(Pos))
1411 S.removeValNo(SVNI);
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
void push_back(const T &Elt)
void extend(LiveRange &LR, SlotIndex Use, unsigned PhysReg=0)
Extend the live range of LR to reach Use.
const_iterator end(StringRef path)
Get end iterator over path.
mop_iterator operands_end()
bool isValid() const
Check if the iterator is at the end of the list.
const Segment * getSegmentContaining(SlotIndex Idx) const
Return the segment that contains the specified index, or null if there is none.
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
ArrayRef< SlotIndex > getRegMaskSlots() const
getRegMaskSlots - Returns a sorted array of slot indices of all instructions with register mask opera...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
cl::opt< bool > UseSegmentSetForPhysRegs
SlotIndex def
The index of the defining instruction.
void createDeadDefs(LiveRange &LR, unsigned Reg)
createDeadDefs - Create a dead def in LI for every def operand of Reg.
void updateAllRanges(MachineInstr *MI)
Update all live ranges touched by MI, assuming a move from OldIdx to NewIdx.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
void removePhysRegDefAt(unsigned Reg, SlotIndex Pos)
Remove value numbers and related live segments starting at position Pos that are part of any liverang...
static unsigned index2VirtReg(unsigned Index)
index2VirtReg - Convert a 0-based index to a virtual register number.
int getNumber() const
getNumber - MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a M...
A Module instance is used to store all the information related to an LLVM module. ...
bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
bool runOnMachineFunction(MachineFunction &) override
runOnMachineFunction - pass entry point
Interval Class - An Interval is a set of nodes defined such that every node in the interval has all o...
virtual bool enableSubRegLiveness() const
Enable tracking of subregister liveness in register allocator.
char & MachineDominatorsID
MachineDominators - This pass is a machine dominators analysis pass.
std::vector< unsigned >::const_iterator livein_iterator
LiveInterval - This class represents the liveness of a register, or stack slot.
MIBundleOperands - Iterate over all operands in a bundle of machine instructions. ...
SlotIndex getInstructionIndex(const MachineInstr *instr) const
Returns the base index of the given instruction.
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
iterator advanceTo(iterator I, SlotIndex Pos)
advanceTo - Advance the specified iterator to point to the Segment containing the specified position...
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const
Return the last index in the given basic block.
iterator_range< reg_iterator > reg_operands(unsigned Reg) const
bool readsVirtualRegister(unsigned Reg) const
Return true if the MachineInstr reads the specified virtual register.
INITIALIZE_PASS_BEGIN(LiveIntervals,"liveintervals","Live Interval Analysis", false, false) INITIALIZE_PASS_END(LiveIntervals
PrintRegUnit - Helper class for printing register units on a raw_ostream.
MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...
A live range for subregisters.
This represents a simple continuous liveness interval for a value.
SlotIndex endPoint() const
Return the end point of the last live range segment to interact with the instruction, if any.
uint64_t getFrequency() const
Returns the frequency as a fixpoint number scaled by the entry frequency.
void markUnused()
Mark this value as unused.
VNInfo - Value Number Information.
void print(raw_ostream &O, const Module *=nullptr) const override
print - Implement the dump method.
iterator_range< mop_iterator > operands()
bool checkRegMaskInterference(LiveInterval &LI, BitVector &UsableRegs)
checkRegMaskInterference - Test if LI is live across any register mask instructions, and compute a bit mask of physical registers that are not clobbered by any of them.
void flushSegmentSet()
Flush segment set into the regular segment vector.
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
BlockFrequency getBlockFreq(const MachineBasicBlock *MBB) const
getblockFreq - Return block frequency.
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
This class represents the liveness of a register, stack slot, etc.
static bool isEarlierInstr(SlotIndex A, SlotIndex B)
isEarlierInstr - Return true if A refers to an instruction earlier than B.
livein_iterator livein_begin() const
void removeEmptySubRanges()
Removes all subranges without any segments (subranges without segments are not considered valid and s...
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
AnalysisUsage & addRequired()
#define INITIALIZE_PASS_DEPENDENCY(depName)
void pruneValue(LiveRange &LR, SlotIndex Kill, SmallVectorImpl< SlotIndex > *EndPoints)
If LR has a live value at Kill, prune its live range by removing any liveness reachable from Kill...
uint64_t getEntryFreq() const
void clear()
clear - Clear all bits.
MachineBasicBlock * intervalIsInOneMBB(const LiveInterval &LI) const
intervalIsInOneMBB - If LI is confined to a single basic block, return a pointer to that block...
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
unsigned getNumBlockIDs() const
getNumBlockIDs - Return the number of MBB ID's allocated.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MCSuperRegIterator enumerates all super-registers of Reg.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
ArrayRef< SlotIndex > getRegMaskSlotsInBlock(unsigned MBBNum) const
getRegMaskSlotsInBlock - Returns a sorted array of slot indices of all instructions with register mas...
void Reset()
Deallocate all but the current slab and reset the current pointer to the beginning of it...
ArrayRef< const uint32_t * > getRegMaskBits() const
getRegMaskBits() - Returns an array of register mask pointers corresponding to getRegMaskSlots().
VNInfo::Allocator & getVNInfoAllocator()
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
iterator_range< subrange_iterator > subranges()
Result of a LiveRange query.
SmallVector< std::pair< SlotIndex, VNInfo * >, 16 > ShrinkToUsesWorkList
void addRegisterDefReadUndef(unsigned Reg)
Mark all subregister defs of register Reg with the undef flag.
std::vector< MachineBasicBlock * >::iterator succ_iterator
Reg
All possible values of the reg field in the ModR/M byte.
bool isBlock() const
isBlock - Returns true if this is a block boundary slot.
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
bool isUnused() const
Returns true if this value is unused.
static reg_instr_iterator reg_instr_end()
SlotIndex getNextNonNullIndex(SlotIndex Index)
Returns the next non-null index, if one exists.
defusechain_iterator - This class provides iterator support for machine operands in the function that...
PrintReg - Helper class for printing registers on a raw_ostream.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
iterator addSegment(Segment S)
Add the specified Segment to this range, merging segments as appropriate.
MCRegUnitRootIterator enumerates the root registers of a register unit.
bool isBundled() const
Return true if this instruction part of a bundle.
VNInfo * valueOutOrDead() const
Returns the value alive at the end of the instruction, if any.
bool shrinkToUses(LiveInterval *li, SmallVectorImpl< MachineInstr * > *dead=nullptr)
shrinkToUses - After removing some uses of a register, shrink its live range to just the remaining us...
static void extendSegmentsToUses(LiveRange &LR, const SlotIndexes &Indexes, ShrinkToUsesWorkList &WorkList, const LiveRange &OldRange)
bool livein_empty() const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
AnalysisUsage & addPreservedID(const void *ID)
void print(raw_ostream &OS, SlotIndexes *=nullptr) const
print - Print out the MachineFunction in a format suitable for debugging to the specified stream...
char & LiveIntervalsID
LiveIntervals - This analysis keeps track of the live ranges of virtual and physical registers...
VNInfo * extendInBlock(SlotIndex StartIdx, SlotIndex Use)
If this range is live before Use in the basic block that starts at StartIdx, extend it to be live up ...
size_t size() const
size - Get the array size.
LiveRange * getCachedRegUnit(unsigned Unit)
getCachedRegUnit - Return the live range for Unit if it has already been computed, or NULL if it hasn't been computed yet.
void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo)
Clear all kill flags affecting Reg.
SlotIndex getPrevSlot() const
Returns the previous slot in the index list.
const MachineBasicBlock * getParent() const
format_object< Ts...> format(const char *Fmt, const Ts &...Vals)
These are helper functions used to produce formatted output.
bool hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const
Returns true if VNI is killed by any PHI-def values in LI.
bool isDebugValue() const
void reset(const MachineFunction *MF, SlotIndexes *, MachineDominatorTree *, VNInfo::Allocator *)
reset - Prepare caches for a new set of non-overlapping live ranges.
bundle_iterator< MachineInstr, instr_iterator > iterator
void removeValNo(VNInfo *ValNo)
removeValNo - Remove all the segments defined by the specified value#.
initializer< Ty > init(const Ty &Val)
bool hasAtLeastOneValue() const
void clearBitsNotInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
clearBitsNotInMask - Clear a bit in this vector for every '0' bit in Mask.
SlotIndexes * getSlotIndexes() const
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
bool isValid() const
Returns true if this is a valid index.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
void swap(SmallVectorImpl &RHS)
df_ext_iterator< T, SetTy > df_ext_end(const T &G, SetTy &S)
unsigned getSubRegIndexLaneMask(unsigned SubIdx) const
getSubRegIndexLaneMask - Return a bitmask representing the parts of a register that are covered by Su...
bool isReserved(unsigned PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
livein_iterator livein_end() const
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Live Interval static false cl::opt< bool > EnablePrecomputePhysRegs("precompute-phys-liveness", cl::Hidden, cl::desc("Eagerly compute live intervals for all physreg units."))
Represent the analysis usage information of a pass.
df_ext_iterator< T, SetTy > df_ext_begin(const T &G, SetTy &S)
void initializeLiveIntervalsPass(PassRegistry &)
LiveInterval::Segment addSegmentToEndOfBlock(unsigned reg, MachineInstr *startInst)
Given a register and an instruction, adds a live segment from that instruction to the end of its MBB...
reg_instr_iterator reg_instr_begin(unsigned RegNo) const
static float getSpillWeight(bool isDef, bool isUse, const MachineBlockFrequencyInfo *MBFI, const MachineInstr *Instr)
VNInfo * valueDefined() const
Return the value defined by this instruction, if any.
for(unsigned i=0, e=MI->getNumOperands();i!=e;++i)
HMEditor(LiveIntervals &LIS, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, SlotIndex OldIdx, SlotIndex NewIdx, bool UpdateFlags)
iterator_range< pred_iterator > predecessors()
void verify() const
Walk the range and assert if any invariants fail to hold.
bool subRegLivenessEnabled() const
#define INITIALIZE_AG_DEPENDENCY(depName)
succ_iterator succ_begin()
void repairIntervalsInRange(MachineBasicBlock *MBB, MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, ArrayRef< unsigned > OrigRegs)
repairIntervalsInRange - Update live intervals for instructions in a range of iterators.
unsigned getSubReg() const
void handleMove(MachineInstr *MI, bool UpdateFlags=false)
handleMove - call this method to notify LiveIntervals that instruction 'mi' has been moved within a b...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
pred_iterator pred_begin()
bool isPHIDef() const
Returns true if this value is defined by a PHI instruction (or was, PHI instructions may have been el...
SlotIndex getInstructionIndex(const MachineInstr *MI) const
Returns the base index for the given instruction.
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction for the given index, or null if the given index has no instruction associated...
std::vector< MachineBasicBlock * >::const_iterator const_pred_iterator
iterator find(SlotIndex Pos)
find - Return an iterator pointing to the first segment that ends after Pos, or end().
unsigned id
The ID number of this value.
void removeSegment(SlotIndex Start, SlotIndex End, bool RemoveDeadValNo=false)
Remove the specified segment from this range.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
ArrayRef< const uint32_t * > getRegMaskBitsInBlock(unsigned MBBNum) const
getRegMaskBitsInBlock - Returns an array of mask pointers corresponding to getRegMaskSlotsInBlock(MBB...
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
MachineOperand class - Representation of each machine instruction operand.
bool hasIndex(const MachineInstr *instr) const
Returns true if the given machine instr is mapped to an index, otherwise returns false.
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
Returns the basic block which the given index falls in.
LiveRange * getRegUnitLI(unsigned Unit)
void setPreservesCFG()
This function should be called by the pass, iff they do not:
LiveInterval & getInterval(unsigned Reg)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
SlotIndex getMBBEndIdx(unsigned Num) const
Returns the last index in the given basic block number.
static cl::opt< bool > EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden, cl::init(true), cl::desc("Enable subregister liveness tracking."))
A range adaptor for a pair of iterators.
void repairIndexesInRange(MachineBasicBlock *MBB, MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End)
Repair indexes after adding and removing instructions.
LiveInterval & createEmptyInterval(unsigned Reg)
unsigned getNumRegUnits() const
Return the number of (native) register units in the target.
void calculate(LiveInterval &LI, bool TrackSubRegs)
Calculates liveness for the register specified in live interval LI.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
SlotIndex beginIndex() const
beginIndex - Return the lowest numbered slot covered.
Representation of each machine instruction.
static bool isPhysicalRegister(unsigned Reg)
isPhysicalRegister - Return true if the specified register number is in the physical register namespa...
bool isLandingPad() const
isLandingPad - Returns true if the block is a landing pad.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
void addKillFlags(const VirtRegMap *)
addKillFlags - Add kill flags to any instruction that kills a virtual register.
VNInfo * createDeadDef(SlotIndex Def, VNInfo::Allocator &VNInfoAllocator)
createDeadDef - Make sure the range has a value defined at Def.
void handleMoveIntoBundle(MachineInstr *MI, MachineInstr *BundleStart, bool UpdateFlags=false)
moveIntoBundle - Update intervals for operands of MI so that they begin/end on the SlotIndex for Bund...
SlotIndex endIndex() const
endNumber - return the maximum point of the range of the whole, exclusive.
void enableSubRegLiveness(bool Enable=true)
AnalysisUsage & addRequiredTransitiveID(char &ID)
AnalysisUsage & addRequiredTransitive()
void removeMachineInstrFromMaps(MachineInstr *mi)
Remove the given machine instruction from the mapping.
SlotIndex getMBBStartIdx(unsigned Num) const
Returns the first index in the given basic block number.
bool hasInterval(unsigned Reg) const
bool reg_empty(unsigned RegNo) const
reg_empty - Return true if there are no instructions using or defining the specified register (it may...
~LiveIntervals() override
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def...
std::vector< uint8_t > Unit
unsigned getReg() const
getReg - Returns the register number.
bool isValid() const
isValid - Returns true until all the operands have been visited.
void releaseMemory() override
releaseMemory() - This member can be implemented by a pass if it wants to be able to release its memo...
VNInfo * getNextValue(SlotIndex def, VNInfo::Allocator &VNInfoAllocator)
getNextValue - Create a new value number and return it.
virtual const TargetInstrInfo * getInstrInfo() const
mop_iterator operands_begin()
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
BasicBlockListType::iterator iterator
This class implements an extremely fast bulk output stream that can only output to a stream...
SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const
Return the first index in the given basic block.
bool addRegisterKilled(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
unsigned getPhys(unsigned virtReg) const
returns the physical register mapped to the specified virtual register
iterator FindSegmentContaining(SlotIndex Idx)
Return an iterator to the segment that contains the specified index, or end() if there is none...
VNInfo * valueIn() const
Return the value that is live-in to the instruction.
bool hasSubRanges() const
Returns true if subregister liveness information is available.
SlotIndex - An opaque wrapper around machine indexes.
SlotIndex insertMachineInstrInMaps(MachineInstr *mi, bool Late=false)
Insert the given machine instruction into the mapping.
void extendToIndices(LiveRange &LR, ArrayRef< SlotIndex > Indices)
extendToIndices - Extend the live range of LI to reach all points in Indices.
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
unsigned pred_size() const
bool reg_nodbg_empty(unsigned RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions...
LiveRange & getRegUnit(unsigned Unit)
getRegUnit - Return the live range for Unit.
VNInfo * getVNInfoBefore(SlotIndex Idx) const
getVNInfoBefore - Return the VNInfo that is live up to but not necessarilly including Idx...
bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const
Returns true if liveness for register class RC should be tracked at the subregister level...
LiveInterval & createAndComputeVirtRegInterval(unsigned Reg)
static void createSegmentsForValues(LiveRange &LR, iterator_range< LiveInterval::vni_iterator > VNIs)
void removeVRegDefAt(LiveInterval &LI, SlotIndex Pos)
Remove value number and related live segments of LI and its subranges that start at position Pos...
const std::pair< SlotIndex, SlotIndex > & getMBBRange(unsigned Num) const
Return the (start,end) range of the given basic block number.