LLVM  3.7.0
CriticalAntiDepBreaker.h
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1 //=- llvm/CodeGen/CriticalAntiDepBreaker.h - Anti-Dep Support -*- C++ -*-=//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the CriticalAntiDepBreaker class, which
11 // implements register anti-dependence breaking along a blocks
12 // critical path during post-RA scheduler.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_CODEGEN_CRITICALANTIDEPBREAKER_H
17 #define LLVM_LIB_CODEGEN_CRITICALANTIDEPBREAKER_H
18 
19 #include "AntiDepBreaker.h"
20 #include "llvm/ADT/BitVector.h"
27 #include <map>
28 
29 namespace llvm {
30 class RegisterClassInfo;
31 class TargetInstrInfo;
32 class TargetRegisterInfo;
33 
35  MachineFunction& MF;
37  const TargetInstrInfo *TII;
38  const TargetRegisterInfo *TRI;
39  const RegisterClassInfo &RegClassInfo;
40 
41  /// The set of allocatable registers.
42  /// We'll be ignoring anti-dependencies on non-allocatable registers,
43  /// because they may not be safe to break.
44  const BitVector AllocatableSet;
45 
46  /// For live regs that are only used in one register class in a
47  /// live range, the register class. If the register is not live, the
48  /// corresponding value is null. If the register is live but used in
49  /// multiple register classes, the corresponding value is -1 casted to a
50  /// pointer.
51  std::vector<const TargetRegisterClass*> Classes;
52 
53  /// Map registers to all their references within a live range.
54  std::multimap<unsigned, MachineOperand *> RegRefs;
55  typedef std::multimap<unsigned, MachineOperand *>::const_iterator
56  RegRefIter;
57 
58  /// The index of the most recent kill (proceeding bottom-up),
59  /// or ~0u if the register is not live.
60  std::vector<unsigned> KillIndices;
61 
62  /// The index of the most recent complete def (proceeding
63  /// bottom up), or ~0u if the register is live.
64  std::vector<unsigned> DefIndices;
65 
66  /// A set of registers which are live and cannot be changed to
67  /// break anti-dependencies.
68  BitVector KeepRegs;
69 
70  public:
72  ~CriticalAntiDepBreaker() override;
73 
74  /// Initialize anti-dep breaking for a new basic block.
75  void StartBlock(MachineBasicBlock *BB) override;
76 
77  /// Identifiy anti-dependencies along the critical path
78  /// of the ScheduleDAG and break them by renaming registers.
79  unsigned BreakAntiDependencies(const std::vector<SUnit>& SUnits,
82  unsigned InsertPosIndex,
83  DbgValueVector &DbgValues) override;
84 
85  /// Update liveness information to account for the current
86  /// instruction, which will not be scheduled.
87  void Observe(MachineInstr *MI, unsigned Count,
88  unsigned InsertPosIndex) override;
89 
90  /// Finish anti-dep breaking for a basic block.
91  void FinishBlock() override;
92 
93  private:
94  void PrescanInstruction(MachineInstr *MI);
95  void ScanInstruction(MachineInstr *MI, unsigned Count);
96  bool isNewRegClobberedByRefs(RegRefIter RegRefBegin,
97  RegRefIter RegRefEnd,
98  unsigned NewReg);
99  unsigned findSuitableFreeRegister(RegRefIter RegRefBegin,
100  RegRefIter RegRefEnd,
101  unsigned AntiDepReg,
102  unsigned LastNewReg,
103  const TargetRegisterClass *RC,
104  SmallVectorImpl<unsigned> &Forbid);
105  };
106 }
107 
108 #endif
const HexagonInstrInfo * TII
This class works in conjunction with the post-RA scheduler to rename registers to break register anti...
TargetInstrInfo - Interface to description of machine instruction set.
bundle_iterator< MachineInstr, instr_iterator > iterator
#define LLVM_LIBRARY_VISIBILITY
LLVM_LIBRARY_VISIBILITY - If a class marked with this attribute is linked into a shared library...
Definition: Compiler.h:110
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:51
std::vector< std::pair< MachineInstr *, MachineInstr * > > DbgValueVector