LLVM  3.7.0
PPCInstrInfo.h
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1 //===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
15 #define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
16 
17 #include "PPC.h"
18 #include "PPCRegisterInfo.h"
20 
21 #define GET_INSTRINFO_HEADER
22 #include "PPCGenInstrInfo.inc"
23 
24 namespace llvm {
25 
26 /// PPCII - This namespace holds all of the PowerPC target-specific
27 /// per-instruction flags. These must match the corresponding definitions in
28 /// PPC.td and PPCInstrFormats.td.
29 namespace PPCII {
30 enum {
31  // PPC970 Instruction Flags. These flags describe the characteristics of the
32  // PowerPC 970 (aka G5) dispatch groups and how they are formed out of
33  // raw machine instructions.
34 
35  /// PPC970_First - This instruction starts a new dispatch group, so it will
36  /// always be the first one in the group.
37  PPC970_First = 0x1,
38 
39  /// PPC970_Single - This instruction starts a new dispatch group and
40  /// terminates it, so it will be the sole instruction in the group.
42 
43  /// PPC970_Cracked - This instruction is cracked into two pieces, requiring
44  /// two dispatch pipes to be available to issue.
46 
47  /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that
48  /// an instruction is issued to.
51 };
53  /// These are the various PPC970 execution unit pipelines. Each instruction
54  /// is one of these.
55  PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction
56  PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit
57  PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit
58  PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit
59  PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit
60  PPC970_VALU = 5 << PPC970_Shift, // Vector ALU
61  PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit
62  PPC970_BRU = 7 << PPC970_Shift // Branch Unit
63 };
64 } // end namespace PPCII
65 
66 class PPCSubtarget;
67 class PPCInstrInfo : public PPCGenInstrInfo {
68  PPCSubtarget &Subtarget;
69  const PPCRegisterInfo RI;
70 
71  bool StoreRegToStackSlot(MachineFunction &MF,
72  unsigned SrcReg, bool isKill, int FrameIdx,
73  const TargetRegisterClass *RC,
75  bool &NonRI, bool &SpillsVRS) const;
76  bool LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
77  unsigned DestReg, int FrameIdx,
78  const TargetRegisterClass *RC,
80  bool &NonRI, bool &SpillsVRS) const;
81  virtual void anchor();
82 public:
83  explicit PPCInstrInfo(PPCSubtarget &STI);
84 
85  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
86  /// such, whenever a client has an instance of instruction info, it should
87  /// always be able to get register info as well (through this method).
88  ///
89  const PPCRegisterInfo &getRegisterInfo() const { return RI; }
90 
93  const ScheduleDAG *DAG) const override;
96  const ScheduleDAG *DAG) const override;
97 
98  unsigned getInstrLatency(const InstrItineraryData *ItinData,
99  const MachineInstr *MI,
100  unsigned *PredCost = nullptr) const override;
101 
102  int getOperandLatency(const InstrItineraryData *ItinData,
103  const MachineInstr *DefMI, unsigned DefIdx,
104  const MachineInstr *UseMI,
105  unsigned UseIdx) const override;
107  SDNode *DefNode, unsigned DefIdx,
108  SDNode *UseNode, unsigned UseIdx) const override {
109  return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx,
110  UseNode, UseIdx);
111  }
112 
113  bool hasLowDefLatency(const TargetSchedModel &SchedModel,
114  const MachineInstr *DefMI,
115  unsigned DefIdx) const override {
116  // Machine LICM should hoist all instructions in low-register-pressure
117  // situations; none are sufficiently free to justify leaving in a loop
118  // body.
119  return false;
120  }
121 
123  unsigned &SrcReg, unsigned &DstReg,
124  unsigned &SubIdx) const override;
125  unsigned isLoadFromStackSlot(const MachineInstr *MI,
126  int &FrameIndex) const override;
127  unsigned isStoreToStackSlot(const MachineInstr *MI,
128  int &FrameIndex) const override;
129 
130  // commuteInstruction - We can commute rlwimi instructions, but only if the
131  // rotate amt is zero. We also have to munge the immediates a bit.
132  MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const override;
133 
134  bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
135  unsigned &SrcOpIdx2) const override;
136 
137  void insertNoop(MachineBasicBlock &MBB,
138  MachineBasicBlock::iterator MI) const override;
139 
140 
141  // Branch analysis.
143  MachineBasicBlock *&FBB,
145  bool AllowModify) const override;
146  unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
149  DebugLoc DL) const override;
150 
151  // Select analysis.
153  unsigned, unsigned, int &, int &, int &) const override;
155  DebugLoc DL, unsigned DstReg, ArrayRef<MachineOperand> Cond,
156  unsigned TrueReg, unsigned FalseReg) const override;
157 
158  void copyPhysReg(MachineBasicBlock &MBB,
160  unsigned DestReg, unsigned SrcReg,
161  bool KillSrc) const override;
162 
165  unsigned SrcReg, bool isKill, int FrameIndex,
166  const TargetRegisterClass *RC,
167  const TargetRegisterInfo *TRI) const override;
168 
171  unsigned DestReg, int FrameIndex,
172  const TargetRegisterClass *RC,
173  const TargetRegisterInfo *TRI) const override;
174 
175  bool
177 
178  bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
179  unsigned Reg, MachineRegisterInfo *MRI) const override;
180 
181  // If conversion by predication (only supported by some branch instructions).
182  // All of the profitability checks always return true; it is always
183  // profitable to use the predicated branches.
185  unsigned NumCycles, unsigned ExtraPredCycles,
186  const BranchProbability &Probability) const override {
187  return true;
188  }
189 
191  unsigned NumT, unsigned ExtraT,
192  MachineBasicBlock &FMBB,
193  unsigned NumF, unsigned ExtraF,
194  const BranchProbability &Probability) const override;
195 
197  unsigned NumCycles,
198  const BranchProbability
199  &Probability) const override {
200  return true;
201  }
202 
204  MachineBasicBlock &FMBB) const override {
205  return false;
206  }
207 
208  // Predication support.
209  bool isPredicated(const MachineInstr *MI) const override;
210 
211  bool isUnpredicatedTerminator(const MachineInstr *MI) const override;
212 
214  ArrayRef<MachineOperand> Pred) const override;
215 
217  ArrayRef<MachineOperand> Pred2) const override;
218 
220  std::vector<MachineOperand> &Pred) const override;
221 
222  bool isPredicable(MachineInstr *MI) const override;
223 
224  // Comparison optimization.
225 
226 
227  bool analyzeCompare(const MachineInstr *MI,
228  unsigned &SrcReg, unsigned &SrcReg2,
229  int &Mask, int &Value) const override;
230 
231  bool optimizeCompareInstr(MachineInstr *CmpInstr,
232  unsigned SrcReg, unsigned SrcReg2,
233  int Mask, int Value,
234  const MachineRegisterInfo *MRI) const override;
235 
236  /// GetInstSize - Return the number of bytes of code the specified
237  /// instruction may be. This returns the maximum number of bytes.
238  ///
239  unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
240 
241  void getNoopForMachoTarget(MCInst &NopInst) const override;
242 };
243 
244 }
245 
246 #endif
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override
bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
PPC970_Cracked - This instruction is cracked into two pieces, requiring two dispatch pipes to be avai...
Definition: PPCInstrInfo.h:45
bool ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, unsigned Reg, MachineRegisterInfo *MRI) const override
These are the various PPC970 execution unit pipelines.
Definition: PPCInstrInfo.h:55
A debug info location.
Definition: DebugLoc.h:34
ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
CreateTargetHazardRecognizer - Return the hazard recognizer to use for this target when scheduling th...
MachineInstr * commuteInstruction(MachineInstr *MI, bool NewMI) const override
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, const BranchProbability &Probability) const override
Definition: PPCInstrInfo.h:184
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
Definition: PPCInstrInfo.h:203
Provide an instruction scheduling machine model to CodeGen passes.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APInt.h:33
Reg
All possible values of the reg field in the ModR/M byte.
bool hasLowDefLatency(const TargetSchedModel &SchedModel, const MachineInstr *DefMI, unsigned DefIdx) const override
Definition: PPCInstrInfo.h:113
bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
bool PredicateInstruction(MachineInstr *MI, ArrayRef< MachineOperand > Pred) const override
PPCInstrInfo(PPCSubtarget &STI)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: ArrayRef.h:31
unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const override
Itinerary data supplied by a subtarget to be used by a target.
bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:150
PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that an instruction is issued to...
Definition: PPCInstrInfo.h:49
PPC970_First - This instruction starts a new dispatch group, so it will always be the first one in th...
Definition: PPCInstrInfo.h:37
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
bool isUnpredicatedTerminator(const MachineInstr *MI) const override
bundle_iterator - MachineBasicBlock iterator that automatically skips over MIs that are inside bundle...
PPC970_Single - This instruction starts a new dispatch group and terminates it, so it will be the sol...
Definition: PPCInstrInfo.h:41
bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const override
unsigned RemoveBranch(MachineBasicBlock &MBB) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const override
bool isPredicable(MachineInstr *MI) const override
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr *MI, unsigned *PredCost=nullptr) const override
int getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const override
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override
bool isPredicated(const MachineInstr *MI) const override
Represents one node in the SelectionDAG.
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
void getNoopForMachoTarget(MCInst &NopInst) const override
getNoopForMachoTarget - Return the noop instruction to use for a noop.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
TargetSubtargetInfo - Generic base class for all target subtargets.
const PPCRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: PPCInstrInfo.h:89
Representation of each machine instruction.
Definition: MachineInstr.h:51
int getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const override
Definition: PPCInstrInfo.h:106
#define I(x, y, z)
Definition: MD5.cpp:54
unsigned GetInstSizeInBytes(const MachineInstr *MI) const
GetInstSize - Return the number of bytes of code the specified instruction may be.
LLVM Value Representation.
Definition: Value.h:69
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, DebugLoc DL) const override
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer to use for this target when ...
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool DefinesPredicate(MachineInstr *MI, std::vector< MachineOperand > &Pred) const override
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, const BranchProbability &Probability) const override
Definition: PPCInstrInfo.h:196