15 #ifndef LLVM_LIB_TARGET_R600_R600INSTRINFO_H
16 #define LLVM_LIB_TARGET_R600_R600INSTRINFO_H
25 class AMDGPUTargetMachine;
28 class MachineFunction;
30 class MachineInstrBuilder;
36 std::vector<std::pair<int, unsigned> >
42 unsigned ValueReg,
unsigned Address,
44 unsigned AddrChan)
const;
48 unsigned ValueReg,
unsigned Address,
50 unsigned AddrChan)
const;
66 unsigned DestReg,
unsigned SrcReg,
67 bool KillSrc)
const override;
74 bool isCubeOp(
unsigned opcode)
const;
91 bool isExport(
unsigned Opcode)
const;
105 int getSrcIdx(
unsigned Opcode,
unsigned SrcNum)
const;
108 int getSelIdx(
unsigned Opcode,
unsigned SrcIdx)
const;
119 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
120 const std::vector<R600InstrInfo::BankSwizzle> &Swz,
121 const std::vector<std::pair<int, unsigned> > &TransSrcs,
125 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
126 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
127 const std::vector<std::pair<int, unsigned> > &TransSrcs,
141 std::vector<BankSwizzle> &BS,
142 bool isLastAluTrans)
const;
155 bool isMov(
unsigned Opcode)
const override;
180 unsigned ExtraPredCycles,
185 unsigned NumTCycles,
unsigned ExtraTCycles,
187 unsigned NumFCycles,
unsigned ExtraFCycles,
191 std::vector<MachineOperand> &Pred)
const override;
206 unsigned *PredCost =
nullptr)
const override;
209 SDNode *Node)
const override {
return 1;}
218 unsigned Channel)
const override;
224 unsigned ValueReg,
unsigned Address,
225 unsigned OffsetReg)
const override;
229 unsigned ValueReg,
unsigned Address,
230 unsigned OffsetReg)
const override;
246 unsigned Src1Reg = 0)
const;
251 unsigned DstReg)
const;
260 unsigned DstReg,
unsigned SrcReg)
const override;
289 unsigned Flag = 0)
const;
MachineInstr * buildSlotOfVectorInstruction(MachineBasicBlock &MBB, MachineInstr *MI, unsigned Slot, unsigned DstReg) const
bool readsLDSSrcReg(const MachineInstr *MI) const
void clearFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const
Clear the specified flag on the instruction.
void setImmOperand(MachineInstr *MI, unsigned Op, int64_t Imm) const
Helper function for setting instruction flag values.
bool isLDSInstr(unsigned Opcode) const
bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const
Determine if the specified Flag is set on this Operand.
unsigned calculateIndirectAddress(unsigned RegIndex, unsigned Channel) const override
Calculate the "Indirect Address" for the given RegIndex and Channel.
int getSrcIdx(unsigned Opcode, unsigned SrcNum) const
bool canBeConsideredALU(const MachineInstr *MI) const
bool isVector(const MachineInstr &MI) const
Vector instructions are instructions that must fill all instruction slots within an instruction group...
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, DebugLoc DL) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
bool fitsReadPortLimitations(const std::vector< MachineInstr * > &MIs, const DenseMap< unsigned, unsigned > &PV, std::vector< BankSwizzle > &BS, bool isLastAluTrans) const
Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210 returns true and the first ...
bool isPlaceHolderOpcode(unsigned opcode) const
Interface definition for R600RegisterInfo.
bool isVectorOnly(unsigned Opcode) const
bool hasFlagOperand(const MachineInstr &MI) const
bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
const R600RegisterInfo & getRegisterInfo() const override
bool isCubeOp(unsigned opcode) const
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
int getLDSNoRetOp(uint16_t Opcode)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
MachineInstr * buildMovImm(MachineBasicBlock &BB, MachineBasicBlock::iterator I, unsigned DstReg, uint64_t Imm) const
MachineInstr * buildMovInstr(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned DstReg, unsigned SrcReg) const override
Build a MOV instruction.
bool DefinesPredicate(MachineInstr *MI, std::vector< MachineOperand > &Pred) const override
bool hasInstrModifiers(unsigned Opcode) const
bool isPredicable(MachineInstr *MI) const override
bool usesVertexCache(unsigned Opcode) const
R600InstrInfo(const AMDGPUSubtarget &st)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Itinerary data supplied by a subtarget to be used by a target.
MachineOperand & getFlagOp(MachineInstr *MI, unsigned SrcIdx=0, unsigned Flag=0) const
bool usesTextureCache(unsigned Opcode) const
Flag
These should be considered private to the implementation of the MCInstrDesc class.
bool isExport(unsigned Opcode) const
bundle_iterator< MachineInstr, instr_iterator > iterator
SmallVector< std::pair< MachineOperand *, int64_t >, 3 > getSrcs(MachineInstr *MI) const
bool isPredicated(const MachineInstr *MI) const override
bool FindSwizzleForVectorSlot(const std::vector< std::vector< std::pair< int, unsigned > > > &IGSrcs, std::vector< R600InstrInfo::BankSwizzle > &SwzCandidate, const std::vector< std::pair< int, unsigned > > &TransSrcs, R600InstrInfo::BankSwizzle TransSwz) const
Enumerate all possible Swizzle sequence to find one that can meet all read port requirements.
bundle_iterator - MachineBasicBlock iterator that automatically skips over MIs that are inside bundle...
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, const BranchProbability &Probability) const override
int getOperandIdx(const MachineInstr &MI, unsigned Op) const
Get the index of Op in the MachineInstr.
unsigned RemoveBranch(MachineBasicBlock &MBB) const override
bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, unsigned ExtraPredCycles, const BranchProbability &Probability) const override
unsigned int getPredicationCost(const MachineInstr *) const override
bool usesAddressRegister(MachineInstr *MI) const
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Represents one node in the SelectionDAG.
bool isTrig(const MachineInstr &MI) const
bool mustBeLastInClause(unsigned Opcode) const
int getSelIdx(unsigned Opcode, unsigned SrcIdx) const
bool ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
unsigned int getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr *MI, unsigned *PredCost=nullptr) const override
Contains the definition of a TargetInstrInfo class that is common to all AMD GPUs.
TargetSubtargetInfo - Generic base class for all target subtargets.
Representation of each machine instruction.
void addFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const
Add one of the MO_FLAG* flags to the specified Operand.
void reserveIndirectRegisters(BitVector &Reserved, const MachineFunction &MF) const
Reserve the registers that may be accesed using indirect addressing.
MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned Opcode, unsigned DstReg, unsigned Src0Reg, unsigned Src1Reg=0) const
buildDefaultInstruction - This function returns a MachineInstr with all the instruction modifiers ini...
unsigned isLegalUpTo(const std::vector< std::vector< std::pair< int, unsigned > > > &IGSrcs, const std::vector< R600InstrInfo::BankSwizzle > &Swz, const std::vector< std::pair< int, unsigned > > &TransSrcs, R600InstrInfo::BankSwizzle TransSwz) const
returns how many MIs (whose inputs are represented by IGSrcs) can be packed in the same Instruction G...
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
unsigned getMaxAlusPerClause() const
bool isReductionOp(unsigned opcode) const
const TargetRegisterClass * getIndirectAddrRegClass() const override
DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &) const override
bool isMov(unsigned Opcode) const override
bool definesAddressRegister(MachineInstr *MI) const
int getInstrLatency(const InstrItineraryData *ItinData, SDNode *Node) const override
bool isLDSNoRetInstr(unsigned Opcode) const
bool fitsConstReadLimitations(const std::vector< MachineInstr * > &) const
An instruction group can only access 2 channel pair (either [XY] or [ZW]) from KCache bank on R700+...
bool isLDSRetInstr(unsigned Opcode) const
bool PredicateInstruction(MachineInstr *MI, ArrayRef< MachineOperand > Pred) const override
bool isALUInstr(unsigned Opcode) const
bool isTransOnly(unsigned Opcode) const
bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const override