LLVM  3.7.0
HexagonMCCodeEmitter.cpp
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1 //===-- HexagonMCCodeEmitter.cpp - Hexagon Target Descriptions ------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "Hexagon.h"
16 #include "llvm/ADT/Statistic.h"
17 #include "llvm/MC/MCCodeEmitter.h"
18 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/Support/Debug.h"
27 
28 #define DEBUG_TYPE "mccodeemitter"
29 
30 using namespace llvm;
31 using namespace Hexagon;
32 
33 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
34 
36  MCContext &aMCT)
37  : MCT(aMCT), MCII(aMII), Addend(new unsigned(0)),
38  Extended(new bool(false)), CurrentBundle(new MCInst const *) {}
39 
40 uint32_t HexagonMCCodeEmitter::parseBits(size_t Instruction, size_t Last,
41  MCInst const &MCB,
42  MCInst const &MCI) const {
43  bool Duplex = HexagonMCInstrInfo::isDuplex(MCII, MCI);
44  if (Instruction == 0) {
46  assert(!Duplex);
47  assert(Instruction != Last);
49  }
50  }
51  if (Instruction == 1) {
53  assert(!Duplex);
54  assert(Instruction != Last);
56  }
57  }
58  if (Duplex) {
59  assert(Instruction == Last);
61  }
62  if(Instruction == Last)
65 }
66 
69  MCSubtargetInfo const &STI) const {
70  MCInst &HMB = const_cast<MCInst &>(MI);
71 
72  assert(HexagonMCInstrInfo::isBundle(HMB));
73  DEBUG(dbgs() << "Encoding bundle\n";);
74  *Addend = 0;
75  *Extended = false;
76  *CurrentBundle = &MI;
77  size_t Instruction = 0;
78  size_t Last = HexagonMCInstrInfo::bundleSize(HMB) - 1;
79  for (auto &I : HexagonMCInstrInfo::bundleInstructions(HMB)) {
80  MCInst &HMI = const_cast<MCInst &>(*I.getInst());
81  EncodeSingleInstruction(HMI, OS, Fixups, STI,
82  parseBits(Instruction, Last, HMB, HMI),
83  Instruction);
84  *Extended = HexagonMCInstrInfo::isImmext(HMI);
85  *Addend += HEXAGON_INSTR_SIZE;
86  ++Instruction;
87  }
88  return;
89 }
90 
91 /// EncodeSingleInstruction - Emit a single
94  const MCSubtargetInfo &STI, uint32_t Parse, size_t Index) const {
95  MCInst HMB = MI;
96  assert(!HexagonMCInstrInfo::isBundle(HMB));
97  uint64_t Binary;
98 
99  // Pseudo instructions don't get encoded and shouldn't be here
100  // in the first place!
101  assert(!HexagonMCInstrInfo::getDesc(MCII, HMB).isPseudo() &&
102  "pseudo-instruction found");
103  DEBUG(dbgs() << "Encoding insn"
104  " `" << HexagonMCInstrInfo::getName(MCII, HMB) << "'"
105  "\n");
106 
107  if (HexagonMCInstrInfo::isNewValue(MCII, HMB)) {
108  // Calculate the new value distance to the associated producer
109  MCOperand &MCO =
111  unsigned SOffset = 0;
112  unsigned Register = MCO.getReg();
113  unsigned Register1;
114  auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle);
115  auto i = Instructions.begin() + Index - 1;
116  for (;; --i) {
117  assert(i != Instructions.begin() - 1 && "Couldn't find producer");
118  MCInst const &Inst = *i->getInst();
120  continue;
121  ++SOffset;
122  Register1 =
125  : static_cast<unsigned>(Hexagon::NoRegister);
126  if (Register != Register1)
127  // This isn't the register we're looking for
128  continue;
129  if (!HexagonMCInstrInfo::isPredicated(MCII, Inst))
130  // Producer is unpredicated
131  break;
132  assert(HexagonMCInstrInfo::isPredicated(MCII, HMB) &&
133  "Unpredicated consumer depending on predicated producer");
134  if (HexagonMCInstrInfo::isPredicatedTrue(MCII, Inst) ==
136  // Producer predicate sense matched ours
137  break;
138  }
139  // Hexagon PRM 10.11 Construct Nt from distance
140  unsigned Offset = SOffset;
141  Offset <<= 1;
142  MCO.setReg(Offset + Hexagon::R0);
143  }
144 
145  Binary = getBinaryCodeForInstr(HMB, Fixups, STI);
146  // Check for unimplemented instructions. Immediate extenders
147  // are encoded as zero, so they need to be accounted for.
148  if ((!Binary) &&
149  ((HMB.getOpcode() != DuplexIClass0) && (HMB.getOpcode() != A4_ext) &&
150  (HMB.getOpcode() != A4_ext_b) && (HMB.getOpcode() != A4_ext_c) &&
151  (HMB.getOpcode() != A4_ext_g))) {
152  // Use a A2_nop for unimplemented instructions.
153  DEBUG(dbgs() << "Unimplemented inst: "
154  " `" << HexagonMCInstrInfo::getName(MCII, HMB) << "'"
155  "\n");
156  llvm_unreachable("Unimplemented Instruction");
157  }
158  Binary |= Parse;
159 
160  // if we need to emit a duplexed instruction
161  if (HMB.getOpcode() >= Hexagon::DuplexIClass0 &&
162  HMB.getOpcode() <= Hexagon::DuplexIClassF) {
163  assert(Parse == HexagonII::INST_PARSE_DUPLEX &&
164  "Emitting duplex without duplex parse bits");
165  unsigned dupIClass;
166  switch (HMB.getOpcode()) {
167  case Hexagon::DuplexIClass0:
168  dupIClass = 0;
169  break;
170  case Hexagon::DuplexIClass1:
171  dupIClass = 1;
172  break;
173  case Hexagon::DuplexIClass2:
174  dupIClass = 2;
175  break;
176  case Hexagon::DuplexIClass3:
177  dupIClass = 3;
178  break;
179  case Hexagon::DuplexIClass4:
180  dupIClass = 4;
181  break;
182  case Hexagon::DuplexIClass5:
183  dupIClass = 5;
184  break;
185  case Hexagon::DuplexIClass6:
186  dupIClass = 6;
187  break;
188  case Hexagon::DuplexIClass7:
189  dupIClass = 7;
190  break;
191  case Hexagon::DuplexIClass8:
192  dupIClass = 8;
193  break;
194  case Hexagon::DuplexIClass9:
195  dupIClass = 9;
196  break;
197  case Hexagon::DuplexIClassA:
198  dupIClass = 10;
199  break;
200  case Hexagon::DuplexIClassB:
201  dupIClass = 11;
202  break;
203  case Hexagon::DuplexIClassC:
204  dupIClass = 12;
205  break;
206  case Hexagon::DuplexIClassD:
207  dupIClass = 13;
208  break;
209  case Hexagon::DuplexIClassE:
210  dupIClass = 14;
211  break;
212  case Hexagon::DuplexIClassF:
213  dupIClass = 15;
214  break;
215  default:
216  llvm_unreachable("Unimplemented DuplexIClass");
217  break;
218  }
219  // 29 is the bit position.
220  // 0b1110 =0xE bits are masked off and down shifted by 1 bit.
221  // Last bit is moved to bit position 13
222  Binary = ((dupIClass & 0xE) << (29 - 1)) | ((dupIClass & 0x1) << 13);
223 
224  const MCInst *subInst0 = HMB.getOperand(0).getInst();
225  const MCInst *subInst1 = HMB.getOperand(1).getInst();
226 
227  // get subinstruction slot 0
228  unsigned subInstSlot0Bits = getBinaryCodeForInstr(*subInst0, Fixups, STI);
229  // get subinstruction slot 1
230  unsigned subInstSlot1Bits = getBinaryCodeForInstr(*subInst1, Fixups, STI);
231 
232  Binary |= subInstSlot0Bits | (subInstSlot1Bits << 16);
233  }
234  support::endian::Writer<support::little>(OS).write<uint32_t>(Binary);
235  ++MCNumEmitted;
236 }
237 
239  const MCOperand &MO,
240  const MCSymbolRefExpr::VariantKind kind) {
241  const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI);
242  unsigned insnType = llvm::HexagonMCInstrInfo::getType(MCII, MI);
243 
244  if (insnType == HexagonII::TypePREFIX) {
245  switch (kind) {
262  default:
263  if (MCID.isBranch())
265  else
267  }
268  } else if (MCID.isBranch())
270 
271  switch (MCID.getOpcode()) {
272  case Hexagon::HI:
273  case Hexagon::A2_tfrih:
274  switch (kind) {
291  default:
293  }
294 
295  case Hexagon::LO:
296  case Hexagon::A2_tfril:
297  switch (kind) {
314  default:
316  }
317 
318  // The only relocs left should be GP relative:
319  default:
320  if (MCID.mayStore() || MCID.mayLoad()) {
321  for (const uint16_t *ImpUses = MCID.getImplicitUses(); *ImpUses;
322  ++ImpUses) {
323  if (*ImpUses == Hexagon::GP) {
324  switch (HexagonMCInstrInfo::getAccessSize(MCII, MI)) {
333  default:
334  llvm_unreachable("unhandled fixup");
335  }
336  }
337  }
338  } else
339  llvm_unreachable("unhandled fixup");
340  }
341 
342  return LastTargetFixupKind;
343 }
344 
345 namespace llvm {
346 extern const MCInstrDesc HexagonInsts[];
347 }
348 
349 namespace {
350  bool isPCRel (unsigned Kind) {
351  switch(Kind){
368  return true;
369  default:
370  return false;
371  }
372  }
373 }
374 
375 unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI,
376  const MCOperand &MO,
377  const MCExpr *ME,
379  const MCSubtargetInfo &STI) const
380 
381 {
382  int64_t Res;
383 
384  if (ME->evaluateAsAbsolute(Res))
385  return Res;
386 
387  MCExpr::ExprKind MK = ME->getKind();
388  if (MK == MCExpr::Constant) {
389  return cast<MCConstantExpr>(ME)->getValue();
390  }
391  if (MK == MCExpr::Binary) {
392  unsigned Res;
393  Res = getExprOpValue(MI, MO, cast<MCBinaryExpr>(ME)->getLHS(), Fixups, STI);
394  Res +=
395  getExprOpValue(MI, MO, cast<MCBinaryExpr>(ME)->getRHS(), Fixups, STI);
396  return 0;
397  }
398 
399  assert(MK == MCExpr::SymbolRef);
400 
403  const MCSymbolRefExpr *MCSRE = static_cast<const MCSymbolRefExpr *>(ME);
404  const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI);
405  unsigned bits = HexagonMCInstrInfo::getExtentBits(MCII, MI) -
407  const MCSymbolRefExpr::VariantKind kind = MCSRE->getKind();
408 
409  DEBUG(dbgs() << "----------------------------------------\n");
410  DEBUG(dbgs() << "Opcode Name: " << HexagonMCInstrInfo::getName(MCII, MI)
411  << "\n");
412  DEBUG(dbgs() << "Opcode: " << MCID.getOpcode() << "\n");
413  DEBUG(dbgs() << "Relocation bits: " << bits << "\n");
414  DEBUG(dbgs() << "Addend: " << *Addend << "\n");
415  DEBUG(dbgs() << "----------------------------------------\n");
416 
417  switch (bits) {
418  default:
419  DEBUG(dbgs() << "unrecognized bit count of " << bits << '\n');
420  break;
421 
422  case 32:
423  switch (kind) {
426  break;
428  FixupKind = *Extended ? Hexagon::fixup_Hexagon_GOT_32_6_X
430  break;
432  FixupKind = *Extended ? Hexagon::fixup_Hexagon_GOTREL_32_6_X
434  break;
436  FixupKind = *Extended ? Hexagon::fixup_Hexagon_GD_GOT_32_6_X
438  break;
440  FixupKind = *Extended ? Hexagon::fixup_Hexagon_LD_GOT_32_6_X
442  break;
444  FixupKind = *Extended ? Hexagon::fixup_Hexagon_IE_32_6_X
446  break;
448  FixupKind = *Extended ? Hexagon::fixup_Hexagon_IE_GOT_32_6_X
450  break;
452  FixupKind = *Extended ? Hexagon::fixup_Hexagon_TPREL_32_6_X
454  break;
456  FixupKind = *Extended ? Hexagon::fixup_Hexagon_DTPREL_32_6_X
458  break;
459  default:
460  FixupKind =
462  break;
463  }
464  break;
465 
466  case 22:
467  switch (kind) {
470  break;
473  break;
474  default:
475  if (MCID.isBranch() || MCID.isCall()) {
476  FixupKind = *Extended ? Hexagon::fixup_Hexagon_B22_PCREL_X
478  } else {
479  errs() << "unrecognized relocation, bits: " << bits << "\n";
480  errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
481  }
482  break;
483  }
484  break;
485 
486  case 16:
487  if (*Extended) {
488  switch (kind) {
489  default:
490  FixupKind = Hexagon::fixup_Hexagon_16_X;
491  break;
494  break;
497  break;
500  break;
503  break;
505  FixupKind = Hexagon::fixup_Hexagon_IE_16_X;
506  break;
509  break;
512  break;
515  break;
516  }
517  } else
518  switch (kind) {
519  default:
520  errs() << "unrecognized relocation, bits " << bits << "\n";
521  errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
522  break;
524  if ((MCID.getOpcode() == Hexagon::HI) ||
525  (MCID.getOpcode() == Hexagon::LO_H))
527  else
529  break;
532  break;
534  FixupKind = Hexagon::fixup_Hexagon_LO16;
535  break;
537  FixupKind = Hexagon::fixup_Hexagon_HI16;
538  break;
541  break;
544  break;
547  break;
550  break;
553  break;
554  }
555  break;
556 
557  case 15:
558  if (MCID.isBranch() || MCID.isCall())
559  FixupKind = *Extended ? Hexagon::fixup_Hexagon_B15_PCREL_X
561  break;
562 
563  case 13:
564  if (MCID.isBranch())
566  else {
567  errs() << "unrecognized relocation, bits " << bits << "\n";
568  errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
569  }
570  break;
571 
572  case 12:
573  if (*Extended)
574  switch (kind) {
575  default:
576  FixupKind = Hexagon::fixup_Hexagon_12_X;
577  break;
578  // There isn't a GOT_12_X, both 11_X and 16_X resolve to 6/26
581  break;
584  break;
585  }
586  else {
587  errs() << "unrecognized relocation, bits " << bits << "\n";
588  errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
589  }
590  break;
591 
592  case 11:
593  if (*Extended)
594  switch (kind) {
595  default:
596  FixupKind = Hexagon::fixup_Hexagon_11_X;
597  break;
600  break;
603  break;
606  break;
609  break;
612  break;
615  break;
618  break;
619  }
620  else {
621  errs() << "unrecognized relocation, bits " << bits << "\n";
622  errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
623  }
624  break;
625 
626  case 10:
627  if (*Extended)
628  FixupKind = Hexagon::fixup_Hexagon_10_X;
629  break;
630 
631  case 9:
632  if (MCID.isBranch() ||
634  FixupKind = *Extended ? Hexagon::fixup_Hexagon_B9_PCREL_X
636  else if (*Extended)
637  FixupKind = Hexagon::fixup_Hexagon_9_X;
638  else {
639  errs() << "unrecognized relocation, bits " << bits << "\n";
640  errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
641  }
642  break;
643 
644  case 8:
645  if (*Extended)
646  FixupKind = Hexagon::fixup_Hexagon_8_X;
647  else {
648  errs() << "unrecognized relocation, bits " << bits << "\n";
649  errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
650  }
651  break;
652 
653  case 7:
654  if (MCID.isBranch() ||
656  FixupKind = *Extended ? Hexagon::fixup_Hexagon_B7_PCREL_X
658  else if (*Extended)
659  FixupKind = Hexagon::fixup_Hexagon_7_X;
660  else {
661  errs() << "unrecognized relocation, bits " << bits << "\n";
662  errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
663  }
664  break;
665 
666  case 6:
667  if (*Extended) {
668  switch (kind) {
669  default:
670  FixupKind = Hexagon::fixup_Hexagon_6_X;
671  break;
674  break;
675  // This is part of an extender, GOT_11 is a
676  // Word32_U6 unsigned/truncated reloc.
679  break;
682  break;
683  }
684  } else {
685  errs() << "unrecognized relocation, bits " << bits << "\n";
686  errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
687  }
688  break;
689 
690  case 0:
691  FixupKind = getFixupNoBits(MCII, MI, MO, kind);
692  break;
693  }
694 
695  MCExpr const *FixupExpression = (*Addend > 0 && isPCRel(FixupKind)) ?
697  MCConstantExpr::create(*Addend, MCT), MCT) :
698  MO.getExpr();
699 
700  MCFixup fixup = MCFixup::create(*Addend, FixupExpression,
701  MCFixupKind(FixupKind), MI.getLoc());
702  Fixups.push_back(fixup);
703  // All of the information is in the fixup.
704  return (0);
705 }
706 
707 unsigned
709  SmallVectorImpl<MCFixup> &Fixups,
710  MCSubtargetInfo const &STI) const {
711  if (MO.isReg())
712  return MCT.getRegisterInfo()->getEncodingValue(MO.getReg());
713  if (MO.isImm())
714  return static_cast<unsigned>(MO.getImm());
715 
716  // MO must be an ME.
717  assert(MO.isExpr());
718  return getExprOpValue(MI, MO, MO.getExpr(), Fixups, STI);
719 }
720 
722  MCRegisterInfo const &MRI,
723  MCContext &MCT) {
724  return new HexagonMCCodeEmitter(MII, MCT);
725 }
726 
727 #include "HexagonGenMCCodeEmitter.inc"
bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned short getNewValueOp(MCInstrInfo const &MCII, MCInst const &MCI)
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
STATISTIC(NumFunctions,"Total number of functions")
bool isReg() const
Definition: MCInst.h:56
bool mayStore() const
Return true if this instruction could possibly modify memory.
Definition: MCInstrDesc.h:356
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:138
const uint16_t * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction...
Definition: MCInstrDesc.h:475
ExprKind getKind() const
Definition: MCExpr.h:69
bool isBundle(MCInst const &MCI)
uint64_t getBinaryCodeForInstr(MCInst const &MI, SmallVectorImpl< MCFixup > &Fixups, MCSubtargetInfo const &STI) const
bool isOuterLoop(MCInst const &MCI)
bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:62
uint32_t parseBits(size_t Instruction, size_t Last, MCInst const &MCB, MCInst const &MCI) const
static Hexagon::Fixups getFixupNoBits(MCInstrInfo const &MCII, const MCInst &MI, const MCOperand &MO, const MCSymbolRefExpr::VariantKind kind)
bool isImmext(MCInst const &MCI)
void EncodeSingleInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI, uint32_t Parse, size_t Index) const
EncodeSingleInstruction - Emit a single.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MCInstrDesc.h:233
bool isCall() const
Return true if the instruction is a call.
Definition: MCInstrDesc.h:214
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APInt.h:33
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:33
const MCInstrDesc HexagonInsts[]
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:159
#define false
Definition: ConvertUTF.c:65
Context object for machine code objects.
Definition: MCContext.h:48
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:63
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:446
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:150
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
bool isImm() const
Definition: MCInst.h:57
void encodeInstruction(MCInst const &MI, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, MCSubtargetInfo const &STI) const override
EncodeInstruction - Encode the given Inst to bytes on the output stream OS.
const MCExpr * getExpr() const
Definition: MCInst.h:93
char const * getName(MCInstrInfo const &MCII, MCInst const &MCI)
MCCodeEmitter * createHexagonMCCodeEmitter(MCInstrInfo const &MCII, MCRegisterInfo const &MRI, MCContext &MCT)
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:23
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:23
bool isExpr() const
Definition: MCInst.h:59
iterator_range< MCInst::const_iterator > bundleInstructions(MCInst const &MCI)
SMLoc getLoc() const
Definition: MCInst.h:162
Definition for classes that emit Hexagon machine code from MCInsts.
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:78
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:178
Promote Memory to Register
Definition: Mem2Reg.cpp:58
bool mayLoad() const
Return true if this instruction could possibly read memory.
Definition: MCInstrDesc.h:350
HexagonII::MemAccessSize getAccessSize(MCInstrInfo const &MCII, MCInst const &MCI)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:123
unsigned getOpcode() const
Definition: MCInst.h:159
bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI)
int64_t getImm() const
Definition: MCInst.h:74
HexagonMCCodeEmitter(MCInstrInfo const &aMII, MCContext &aMCT)
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:227
Adapter to write values to a stream in a particular byte order.
Definition: EndianStream.h:26
#define I(x, y, z)
Definition: MD5.cpp:54
MCSubtargetInfo - Generic base class for all target subtargets.
const MCInst * getInst() const
Definition: MCInst.h:102
References to labels and assigned expressions.
Definition: MCExpr.h:38
MCInstrDesc const & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
size_t bundleSize(MCInst const &MCI)
void setReg(unsigned Reg)
Set the register number.
Definition: MCInst.h:69
VariantKind getKind() const
Definition: MCExpr.h:330
bool isInnerLoop(MCInst const &MCI)
const ARM::ArchExtKind Kind
#define HEXAGON_INSTR_SIZE
Definition: Hexagon.h:30
aarch64 promote const
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
Constant expressions.
Definition: MCExpr.h:37
Binary expressions.
Definition: MCExpr.h:36
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:38
#define DEBUG(X)
Definition: Debug.h:92
bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI)
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:33
bool isPredicatedTrue(MCInstrInfo const &MCII, MCInst const &MCI)
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx)
Definition: MCExpr.cpp:150
unsigned getMachineOpValue(MCInst const &MI, MCOperand const &MO, SmallVectorImpl< MCFixup > &Fixups, MCSubtargetInfo const &STI) const
Return binary encoding of operand.
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:164
MCOperand const & getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI)