29 cl::desc(
"Use old-style Thumb2 if-conversion heuristics"),
74 while (Count && MBBI != E) {
75 if (MBBI->isDebugValue()) {
79 if (MBBI->getOpcode() == ARM::t2IT) {
80 unsigned Mask = MBBI->getOperand(1).getImm();
82 MBBI->eraseFromParent();
84 unsigned MaskOn = 1 << Count;
85 unsigned MaskOff = ~(MaskOn - 1);
86 MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn);
102 while (MBBI->isDebugValue()) {
104 if (MBBI == MBB.
end())
108 unsigned PredReg = 0;
114 unsigned DestReg,
unsigned SrcReg,
115 bool KillSrc)
const {
117 if (!ARM::GPRRegClass.
contains(DestReg, SrcReg))
126 unsigned SrcReg,
bool isKill,
int FI,
130 if (I != MBB.
end()) DL = I->getDebugLoc();
140 if (RC == &ARM::GPRRegClass || RC == &ARM::tGPRRegClass ||
141 RC == &ARM::tcGPRRegClass || RC == &ARM::rGPRRegClass ||
142 RC == &ARM::GPRnopcRegClass) {
145 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
149 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
158 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
169 unsigned DestReg,
int FI,
180 if (I != MBB.
end()) DL = I->getDebugLoc();
182 if (RC == &ARM::GPRRegClass || RC == &ARM::tGPRRegClass ||
183 RC == &ARM::tcGPRRegClass || RC == &ARM::rGPRRegClass ||
184 RC == &ARM::GPRnopcRegClass) {
186 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
190 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
222 unsigned DestReg,
unsigned BaseReg,
int NumBytes,
225 if (NumBytes == 0 && DestReg != BaseReg) {
226 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
232 bool isSub = NumBytes < 0;
233 if (isSub) NumBytes = -NumBytes;
237 if (DestReg != ARM::SP && DestReg != BaseReg &&
241 if (NumBytes < 65536) {
243 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
247 }
else if ((NumBytes & 0xffff) == 0) {
249 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
258 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
269 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)
280 unsigned ThisVal = NumBytes;
282 if (DestReg == ARM::SP && BaseReg != ARM::SP) {
290 bool HasCCOut =
true;
291 if (BaseReg == ARM::SP) {
293 if (DestReg == ARM::SP && (ThisVal < ((1 << 7)-1) * 4)) {
294 assert((ThisVal & 3) == 0 &&
"Stack update is not multiple of 4?");
295 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
303 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
310 NumBytes &= ~ThisVal;
312 "Bit extraction didn't work?");
315 assert(DestReg != ARM::SP && BaseReg != ARM::SP);
316 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
319 }
else if (ThisVal < 4096) {
320 Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
327 NumBytes &= ~ThisVal;
329 "Bit extraction didn't work?");
337 .
addImm(ThisVal)).setMIFlags(MIFlags);
349 case ARM::t2LDRi12:
return ARM::t2LDRi8;
350 case ARM::t2LDRHi12:
return ARM::t2LDRHi8;
351 case ARM::t2LDRBi12:
return ARM::t2LDRBi8;
352 case ARM::t2LDRSHi12:
return ARM::t2LDRSHi8;
353 case ARM::t2LDRSBi12:
return ARM::t2LDRSBi8;
354 case ARM::t2STRi12:
return ARM::t2STRi8;
355 case ARM::t2STRBi12:
return ARM::t2STRBi8;
356 case ARM::t2STRHi12:
return ARM::t2STRHi8;
357 case ARM::t2PLDi12:
return ARM::t2PLDi8;
381 case ARM::t2LDRi8:
return ARM::t2LDRi12;
382 case ARM::t2LDRHi8:
return ARM::t2LDRHi12;
383 case ARM::t2LDRBi8:
return ARM::t2LDRBi12;
384 case ARM::t2LDRSHi8:
return ARM::t2LDRSHi12;
385 case ARM::t2LDRSBi8:
return ARM::t2LDRSBi12;
386 case ARM::t2STRi8:
return ARM::t2STRi12;
387 case ARM::t2STRBi8:
return ARM::t2STRBi12;
388 case ARM::t2STRHi8:
return ARM::t2STRHi12;
389 case ARM::t2PLDi8:
return ARM::t2PLDi12;
394 case ARM::t2LDRSHi12:
395 case ARM::t2LDRSBi12:
413 case ARM::t2LDRs:
return ARM::t2LDRi12;
414 case ARM::t2LDRHs:
return ARM::t2LDRHi12;
415 case ARM::t2LDRBs:
return ARM::t2LDRBi12;
416 case ARM::t2LDRSHs:
return ARM::t2LDRSHi12;
417 case ARM::t2LDRSBs:
return ARM::t2LDRSBi12;
418 case ARM::t2STRs:
return ARM::t2STRi12;
419 case ARM::t2STRBs:
return ARM::t2STRBi12;
420 case ARM::t2STRHs:
return ARM::t2STRHi12;
421 case ARM::t2PLDs:
return ARM::t2PLDi12;
426 case ARM::t2LDRSHi12:
427 case ARM::t2LDRSBi12:
451 unsigned FrameReg,
int &Offset,
462 if (Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) {
468 MI.
setDesc(TII.get(ARM::tMOVr));
478 bool HasCCOut = Opcode != ARM::t2ADDri12;
483 MI.
setDesc(TII.get(ARM::t2SUBri));
485 MI.
setDesc(TII.get(ARM::t2ADDri));
501 unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
514 unsigned RotAmt = countLeadingZeros<unsigned>(Offset);
515 unsigned ThisImmVal = Offset &
ARM_AM::rotr32(0xff000000U, RotAmt);
518 Offset &= ~ThisImmVal;
521 "Bit extraction didn't work?");
535 unsigned NewOpc = Opcode;
538 if (OffsetReg != 0) {
549 unsigned NumBits = 0;
573 Offset += InstrOffs * 4;
574 assert((Offset & (Scale-1)) == 0 &&
"Can't encode this offset!");
584 assert((Offset & 3) == 0 &&
"Can't encode this offset!");
589 if (NewOpc != Opcode)
596 int ImmedOffset = Offset / Scale;
597 unsigned Mask = (1 << NumBits) - 1;
598 if ((
unsigned)Offset <= Mask * Scale) {
604 ImmedOffset |= 1 << NumBits;
606 ImmedOffset = -ImmedOffset;
614 ImmedOffset = ImmedOffset & Mask;
618 ImmedOffset |= 1 << NumBits;
620 ImmedOffset = -ImmedOffset;
621 if (ImmedOffset == 0)
627 Offset &= ~(Mask*Scale);
630 Offset = (isSub) ? -Offset : Offset;
637 if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
The memory access reads data.
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
The memory access writes data.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
Describe properties that are true of each instruction in the target description file.
void emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
static unsigned negativeOffsetOpcode(unsigned opcode)
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
std::size_t countLeadingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the most significant bit to the least stopping at the first 1...
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, unsigned f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
getMachineMemOperand - Allocate a new MachineMemOperand.
ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg)
getITInstrPredicate - Valid only in Thumb2 mode.
void getNoopForMachoTarget(MCInst &NopInst) const override
getNoopForMachoTarget - Return the noop instruction to use for a noop.
static MachinePointerInfo getFixedStack(int FI, int64_t offset=0)
getFixedStack - Return a MachinePointerInfo record that refers to the the specified FrameIndex...
static unsigned rotr32(unsigned Val, unsigned Amt)
rotr32 - Rotate a 32-bit unsigned value right by a specified # bits.
static cl::opt< bool > OldT2IfCvt("old-thumb2-ifcvt", cl::Hidden, cl::desc("Use old-style Thumb2 if-conversion heuristics"), cl::init(false))
bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const override
MachineMemOperand - A description of a memory reference used in the backend.
static const MachineInstrBuilder & AddDefaultPred(const MachineInstrBuilder &MIB)
static MCOperand createReg(unsigned Reg)
const HexagonInstrInfo * TII
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const ARMBaseInstrInfo &TII)
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
INLINEASM - Represents an inline asm block.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
static int getT2SOImmVal(unsigned Arg)
getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit into a Thumb-2 shifter_oper...
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
Instances of this class represent a single low-level machine instruction.
unsigned getKillRegState(bool B)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
const MachineBasicBlock * getParent() const
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bundle_iterator< MachineInstr, instr_iterator > iterator
unsigned getUnindexedOpcode(unsigned Opc) const override
initializer< Ty > init(const Ty &Val)
ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg)
getInstrPredicate - If instruction is predicated, returns its predicate condition, otherwise returns AL.
static unsigned char getAM5Offset(unsigned AM5Opc)
const MachineOperand & getOperand(unsigned i) const
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Thumb2InstrInfo(const ARMSubtarget &STI)
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
static unsigned immediateOffsetOpcode(unsigned opcode)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static const MachineInstrBuilder & AddDefaultCC(const MachineInstrBuilder &MIB)
void setOpcode(unsigned Op)
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
MachineOperand class - Representation of each machine instruction operand.
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const override
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const MachineInstrBuilder & addFrameIndex(int Idx) const
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
AddrMode
ARM Addressing Modes.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
static bool isPhysicalRegister(unsigned Reg)
isPhysicalRegister - Return true if the specified register number is in the physical register namespa...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static unsigned positiveOffsetOpcode(unsigned opcode)
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
static AddrOpc getAM5Op(unsigned AM5Opc)
unsigned getReg() const
getReg - Returns the register number.
void addOperand(const MCOperand &Op)
virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const
Delete the instruction OldInst and everything after it, replacing it with an unconditional branch to ...
void expandLoadStackGuardBase(MachineBasicBlock::iterator MI, unsigned LoadImmOpc, unsigned LoadOpc, Reloc::Model RM) const
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
static MCOperand createImm(int64_t Val)
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
const MachineInstrBuilder & AddDReg(MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI) const