LLVM  3.7.0
AMDGPUAsmBackend.cpp
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1 //===-- AMDGPUAsmBackend.cpp - AMDGPU Assembler Backend -------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 /// \file
9 //===----------------------------------------------------------------------===//
10 
13 #include "llvm/ADT/StringRef.h"
14 #include "llvm/MC/MCAsmBackend.h"
15 #include "llvm/MC/MCAssembler.h"
17 #include "llvm/MC/MCObjectWriter.h"
18 #include "llvm/MC/MCValue.h"
20 
21 using namespace llvm;
22 
23 namespace {
24 
25 class AMDGPUMCObjectWriter : public MCObjectWriter {
26 public:
27  AMDGPUMCObjectWriter(raw_pwrite_stream &OS) : MCObjectWriter(OS, true) {}
28  void executePostLayoutBinding(MCAssembler &Asm,
29  const MCAsmLayout &Layout) override {
30  //XXX: Implement if necessary.
31  }
32  void recordRelocation(MCAssembler &Asm, const MCAsmLayout &Layout,
33  const MCFragment *Fragment, const MCFixup &Fixup,
34  MCValue Target, bool &IsPCRel,
35  uint64_t &FixedValue) override {
36  assert(!"Not implemented");
37  }
38 
39  void writeObject(MCAssembler &Asm, const MCAsmLayout &Layout) override;
40 
41 };
42 
43 class AMDGPUAsmBackend : public MCAsmBackend {
44 public:
45  AMDGPUAsmBackend(const Target &T)
46  : MCAsmBackend() {}
47 
48  unsigned getNumFixupKinds() const override { return AMDGPU::NumTargetFixupKinds; };
49  void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
50  uint64_t Value, bool IsPCRel) const override;
51  bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
52  const MCRelaxableFragment *DF,
53  const MCAsmLayout &Layout) const override {
54  return false;
55  }
56  void relaxInstruction(const MCInst &Inst, MCInst &Res) const override {
57  assert(!"Not implemented");
58  }
59  bool mayNeedRelaxation(const MCInst &Inst) const override { return false; }
60  bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
61 
62  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
63 };
64 
65 } //End anonymous namespace
66 
67 void AMDGPUMCObjectWriter::writeObject(MCAssembler &Asm,
68  const MCAsmLayout &Layout) {
69  for (MCAssembler::iterator I = Asm.begin(), E = Asm.end(); I != E; ++I) {
70  Asm.writeSectionData(&*I, Layout);
71  }
72 }
73 
74 void AMDGPUAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
75  unsigned DataSize, uint64_t Value,
76  bool IsPCRel) const {
77 
78  switch ((unsigned)Fixup.getKind()) {
79  default: llvm_unreachable("Unknown fixup kind");
81  uint16_t *Dst = (uint16_t*)(Data + Fixup.getOffset());
82  *Dst = (Value - 4) / 4;
83  break;
84  }
85 
87  uint32_t *Dst = (uint32_t*)(Data + Fixup.getOffset());
88  *Dst = Value;
89  break;
90  }
91 
93  uint32_t *Dst = (uint32_t*)(Data + Fixup.getOffset());
94  // The value points to the last instruction in the text section, so we
95  // need to add 4 bytes to get to the start of the constants.
96  *Dst = Value + 4;
97  break;
98  }
99  }
100 }
101 
102 const MCFixupKindInfo &AMDGPUAsmBackend::getFixupKindInfo(
103  MCFixupKind Kind) const {
104  const static MCFixupKindInfo Infos[AMDGPU::NumTargetFixupKinds] = {
105  // name offset bits flags
106  { "fixup_si_sopp_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
107  { "fixup_si_rodata", 0, 32, 0 },
108  { "fixup_si_end_of_text", 0, 32, MCFixupKindInfo::FKF_IsPCRel }
109  };
110 
111  if (Kind < FirstTargetFixupKind)
112  return MCAsmBackend::getFixupKindInfo(Kind);
113 
114  return Infos[Kind - FirstTargetFixupKind];
115 }
116 
117 bool AMDGPUAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
118  OW->WriteZeros(Count);
119 
120  return true;
121 }
122 
123 //===----------------------------------------------------------------------===//
124 // ELFAMDGPUAsmBackend class
125 //===----------------------------------------------------------------------===//
126 
127 namespace {
128 
129 class ELFAMDGPUAsmBackend : public AMDGPUAsmBackend {
130  bool Is64Bit;
131 
132 public:
133  ELFAMDGPUAsmBackend(const Target &T, bool Is64Bit) :
134  AMDGPUAsmBackend(T), Is64Bit(Is64Bit) { }
135 
136  MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
137  return createAMDGPUELFObjectWriter(Is64Bit, OS);
138  }
139 };
140 
141 } // end anonymous namespace
142 
144  const MCRegisterInfo &MRI,
145  const Triple &TT, StringRef CPU) {
146  Triple TargetTriple(TT);
147 
148  // Use 64-bit ELF for amdgcn
149  return new ELFAMDGPUAsmBackend(T, TargetTriple.getArch() == Triple::amdgcn);
150 }
fixup for offset from instruction to end of text section
void WriteZeros(unsigned N)
This represents an "assembler immediate".
Definition: MCValue.h:44
iterator begin()
Definition: MCAssembler.h:764
fixup for global addresses with constant initializers
Defines the object file and target independent interfaces used by the assembler backend to write nati...
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:62
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...
Encapsulates the layout of an assembly file at a particular point in time.
Definition: MCAsmLayout.h:29
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Definition: Triple.h:242
iterator end()
Definition: MCAssembler.h:767
uint32_t getOffset() const
Definition: MCFixup.h:91
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:150
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
MCAsmBackend * createAMDGPUAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU)
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
Definition: MCAssembler.h:259
#define true
Definition: ConvertUTF.c:66
void writeSectionData(const MCSection *Section, const MCAsmLayout &Layout) const
Emit the section contents using the given object writer.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:23
MCFixupKind getKind() const
Definition: MCFixup.h:89
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
PowerPC TLS Dynamic Call Fixup
An iterator type that allows iterating over the pointees via some other iterator. ...
Definition: iterator.h:231
Target - Wrapper for Target specific information.
Provides AMDGPU specific target descriptions.
#define I(x, y, z)
Definition: MD5.cpp:54
16-bit PC relative fixup for SOPP branch instructions.
Target independent information on a fixup kind.
An abstract base class for streams implementations that also support a pwrite operation.
Definition: raw_ostream.h:321
MCObjectWriter * createAMDGPUELFObjectWriter(bool Is64Bit, raw_pwrite_stream &OS)
const ARM::ArchExtKind Kind
LLVM Value Representation.
Definition: Value.h:69
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:34
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:40
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.