LLVM  3.7.0
ARMBaseRegisterInfo.cpp
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1 //===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMBaseRegisterInfo.h"
15 #include "ARM.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMFrameLowering.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMSubtarget.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/SmallVector.h"
30 #include "llvm/IR/Constants.h"
31 #include "llvm/IR/DerivedTypes.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/LLVMContext.h"
34 #include "llvm/Support/Debug.h"
40 
41 #define DEBUG_TYPE "arm-register-info"
42 
43 #define GET_REGINFO_TARGET_DESC
44 #include "ARMGenRegisterInfo.inc"
45 
46 using namespace llvm;
47 
49  : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC), BasePtr(ARM::R6) {}
50 
51 static unsigned getFramePointerReg(const ARMSubtarget &STI) {
52  if (STI.isTargetMachO()) {
53  if (STI.isTargetDarwin() || STI.isThumb1Only())
54  return ARM::R7;
55  else
56  return ARM::R11;
57  } else if (STI.isTargetWindows())
58  return ARM::R11;
59  else // ARM EABI
60  return STI.isThumb() ? ARM::R7 : ARM::R11;
61 }
62 
63 const MCPhysReg*
65  const ARMSubtarget &STI = MF->getSubtarget<ARMSubtarget>();
66  const MCPhysReg *RegList =
67  STI.isTargetDarwin() ? CSR_iOS_SaveList : CSR_AAPCS_SaveList;
68 
69  const Function *F = MF->getFunction();
70  if (F->getCallingConv() == CallingConv::GHC) {
71  // GHC set of callee saved regs is empty as all those regs are
72  // used for passing STG regs around
73  return CSR_NoRegs_SaveList;
74  } else if (F->hasFnAttribute("interrupt")) {
75  if (STI.isMClass()) {
76  // M-class CPUs have hardware which saves the registers needed to allow a
77  // function conforming to the AAPCS to function as a handler.
78  return CSR_AAPCS_SaveList;
79  } else if (F->getFnAttribute("interrupt").getValueAsString() == "FIQ") {
80  // Fast interrupt mode gives the handler a private copy of R8-R14, so less
81  // need to be saved to restore user-mode state.
82  return CSR_FIQ_SaveList;
83  } else {
84  // Generally only R13-R14 (i.e. SP, LR) are automatically preserved by
85  // exception handling.
86  return CSR_GenericInt_SaveList;
87  }
88  }
89 
90  return RegList;
91 }
92 
93 const uint32_t *
95  CallingConv::ID CC) const {
96  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
97  if (CC == CallingConv::GHC)
98  // This is academic becase all GHC calls are (supposed to be) tail calls
99  return CSR_NoRegs_RegMask;
100  return STI.isTargetDarwin() ? CSR_iOS_RegMask : CSR_AAPCS_RegMask;
101 }
102 
103 const uint32_t*
105  return CSR_NoRegs_RegMask;
106 }
107 
108 const uint32_t *
110  CallingConv::ID CC) const {
111  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
112  // This should return a register mask that is the same as that returned by
113  // getCallPreservedMask but that additionally preserves the register used for
114  // the first i32 argument (which must also be the register used to return a
115  // single i32 return value)
116  //
117  // In case that the calling convention does not use the same register for
118  // both or otherwise does not want to enable this optimization, the function
119  // should return NULL
120  if (CC == CallingConv::GHC)
121  // This is academic becase all GHC calls are (supposed to be) tail calls
122  return nullptr;
123  return STI.isTargetDarwin() ? CSR_iOS_ThisReturn_RegMask
124  : CSR_AAPCS_ThisReturn_RegMask;
125 }
126 
129  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
130  const ARMFrameLowering *TFI = getFrameLowering(MF);
131 
132  // FIXME: avoid re-calculating this every time.
133  BitVector Reserved(getNumRegs());
134  Reserved.set(ARM::SP);
135  Reserved.set(ARM::PC);
136  Reserved.set(ARM::FPSCR);
137  Reserved.set(ARM::APSR_NZCV);
138  if (TFI->hasFP(MF))
139  Reserved.set(getFramePointerReg(STI));
140  if (hasBasePointer(MF))
141  Reserved.set(BasePtr);
142  // Some targets reserve R9.
143  if (STI.isR9Reserved())
144  Reserved.set(ARM::R9);
145  // Reserve D16-D31 if the subtarget doesn't support them.
146  if (!STI.hasVFP3() || STI.hasD16()) {
147  assert(ARM::D31 == ARM::D16 + 15);
148  for (unsigned i = 0; i != 16; ++i)
149  Reserved.set(ARM::D16 + i);
150  }
151  const TargetRegisterClass *RC = &ARM::GPRPairRegClass;
152  for(TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I!=E; ++I)
153  for (MCSubRegIterator SI(*I, this); SI.isValid(); ++SI)
154  if (Reserved.test(*SI)) Reserved.set(*I);
155 
156  return Reserved;
157 }
158 
159 const TargetRegisterClass *
161  const MachineFunction &) const {
162  const TargetRegisterClass *Super = RC;
164  do {
165  switch (Super->getID()) {
166  case ARM::GPRRegClassID:
167  case ARM::SPRRegClassID:
168  case ARM::DPRRegClassID:
169  case ARM::QPRRegClassID:
170  case ARM::QQPRRegClassID:
171  case ARM::QQQQPRRegClassID:
172  case ARM::GPRPairRegClassID:
173  return Super;
174  }
175  Super = *I++;
176  } while (Super);
177  return RC;
178 }
179 
180 const TargetRegisterClass *
182  const {
183  return &ARM::GPRRegClass;
184 }
185 
186 const TargetRegisterClass *
188  if (RC == &ARM::CCRRegClass)
189  return &ARM::rGPRRegClass; // Can't copy CCR registers.
190  return RC;
191 }
192 
193 unsigned
195  MachineFunction &MF) const {
196  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
197  const ARMFrameLowering *TFI = getFrameLowering(MF);
198 
199  switch (RC->getID()) {
200  default:
201  return 0;
202  case ARM::tGPRRegClassID:
203  return TFI->hasFP(MF) ? 4 : 5;
204  case ARM::GPRRegClassID: {
205  unsigned FP = TFI->hasFP(MF) ? 1 : 0;
206  return 10 - FP - (STI.isR9Reserved() ? 1 : 0);
207  }
208  case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
209  case ARM::DPRRegClassID:
210  return 32 - 10;
211  }
212 }
213 
214 // Get the other register in a GPRPair.
215 static unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI) {
216  for (MCSuperRegIterator Supers(Reg, RI); Supers.isValid(); ++Supers)
217  if (ARM::GPRPairRegClass.contains(*Supers))
218  return RI->getSubReg(*Supers, Odd ? ARM::gsub_1 : ARM::gsub_0);
219  return 0;
220 }
221 
222 // Resolve the RegPairEven / RegPairOdd register allocator hints.
223 void
225  ArrayRef<MCPhysReg> Order,
227  const MachineFunction &MF,
228  const VirtRegMap *VRM) const {
229  const MachineRegisterInfo &MRI = MF.getRegInfo();
230  std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg);
231 
232  unsigned Odd;
233  switch (Hint.first) {
234  case ARMRI::RegPairEven:
235  Odd = 0;
236  break;
237  case ARMRI::RegPairOdd:
238  Odd = 1;
239  break;
240  default:
241  TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM);
242  return;
243  }
244 
245  // This register should preferably be even (Odd == 0) or odd (Odd == 1).
246  // Check if the other part of the pair has already been assigned, and provide
247  // the paired register as the first hint.
248  unsigned Paired = Hint.second;
249  if (Paired == 0)
250  return;
251 
252  unsigned PairedPhys = 0;
254  PairedPhys = Paired;
255  } else if (VRM && VRM->hasPhys(Paired)) {
256  PairedPhys = getPairedGPR(VRM->getPhys(Paired), Odd, this);
257  }
258 
259  // First prefer the paired physreg.
260  if (PairedPhys &&
261  std::find(Order.begin(), Order.end(), PairedPhys) != Order.end())
262  Hints.push_back(PairedPhys);
263 
264  // Then prefer even or odd registers.
265  for (unsigned I = 0, E = Order.size(); I != E; ++I) {
266  unsigned Reg = Order[I];
267  if (Reg == PairedPhys || (getEncodingValue(Reg) & 1) != Odd)
268  continue;
269  // Don't provide hints that are paired to a reserved register.
270  unsigned Paired = getPairedGPR(Reg, !Odd, this);
271  if (!Paired || MRI.isReserved(Paired))
272  continue;
273  Hints.push_back(Reg);
274  }
275 }
276 
277 void
279  MachineFunction &MF) const {
280  MachineRegisterInfo *MRI = &MF.getRegInfo();
281  std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
282  if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
283  Hint.first == (unsigned)ARMRI::RegPairEven) &&
285  // If 'Reg' is one of the even / odd register pair and it's now changed
286  // (e.g. coalesced) into a different register. The other register of the
287  // pair allocation hint must be updated to reflect the relationship
288  // change.
289  unsigned OtherReg = Hint.second;
290  Hint = MRI->getRegAllocationHint(OtherReg);
291  // Make sure the pair has not already divorced.
292  if (Hint.second == Reg) {
293  MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
295  MRI->setRegAllocationHint(NewReg,
296  Hint.first == (unsigned)ARMRI::RegPairOdd ? ARMRI::RegPairEven
297  : ARMRI::RegPairOdd, OtherReg);
298  }
299  }
300 }
301 
303  const MachineFrameInfo *MFI = MF.getFrameInfo();
304  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
305  const ARMFrameLowering *TFI = getFrameLowering(MF);
306 
307  // When outgoing call frames are so large that we adjust the stack pointer
308  // around the call, we can no longer use the stack pointer to reach the
309  // emergency spill slot.
310  if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF))
311  return true;
312 
313  // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
314  // negative range for ldr/str (255), and thumb1 is positive offsets only.
315  // It's going to be better to use the SP or Base Pointer instead. When there
316  // are variable sized objects, we can't reference off of the SP, so we
317  // reserve a Base Pointer.
318  if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) {
319  // Conservatively estimate whether the negative offset from the frame
320  // pointer will be sufficient to reach. If a function has a smallish
321  // frame, it's less likely to have lots of spills and callee saved
322  // space, so it's all more likely to be within range of the frame pointer.
323  // If it's wrong, the scavenger will still enable access to work, it just
324  // won't be optimal.
325  if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128)
326  return false;
327  return true;
328  }
329 
330  return false;
331 }
332 
334  const MachineRegisterInfo *MRI = &MF.getRegInfo();
335  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
336  const ARMFrameLowering *TFI = getFrameLowering(MF);
337  // We can't realign the stack if:
338  // 1. Dynamic stack realignment is explicitly disabled,
339  // 2. This is a Thumb1 function (it's not useful, so we don't bother), or
340  // 3. There are VLAs in the function and the base pointer is disabled.
341  if (MF.getFunction()->hasFnAttribute("no-realign-stack"))
342  return false;
343  if (AFI->isThumb1OnlyFunction())
344  return false;
345  // Stack realignment requires a frame pointer. If we already started
346  // register allocation with frame pointer elimination, it is too late now.
348  return false;
349  // We may also need a base pointer if there are dynamic allocas or stack
350  // pointer adjustments around calls.
351  if (TFI->hasReservedCallFrame(MF))
352  return true;
353  // A base pointer is required and allowed. Check that it isn't too late to
354  // reserve it.
355  return MRI->canReserveReg(BasePtr);
356 }
357 
360  const MachineFrameInfo *MFI = MF.getFrameInfo();
361  const ARMFrameLowering *TFI = getFrameLowering(MF);
362  const Function *F = MF.getFunction();
363  unsigned StackAlign = TFI->getStackAlignment();
364  bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
366 
367  return requiresRealignment && canRealignStack(MF);
368 }
369 
372  const MachineFrameInfo *MFI = MF.getFrameInfo();
373  if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI->adjustsStack())
374  return true;
375  return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
376  || needsStackRealignment(MF);
377 }
378 
379 unsigned
381  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
382  const ARMFrameLowering *TFI = getFrameLowering(MF);
383 
384  if (TFI->hasFP(MF))
385  return getFramePointerReg(STI);
386  return ARM::SP;
387 }
388 
389 /// emitLoadConstPool - Emits a load from constpool to materialize the
390 /// specified immediate.
394  DebugLoc dl,
395  unsigned DestReg, unsigned SubIdx, int Val,
396  ARMCC::CondCodes Pred,
397  unsigned PredReg, unsigned MIFlags) const {
398  MachineFunction &MF = *MBB.getParent();
399  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
401  const Constant *C =
403  unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
404 
405  BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
406  .addReg(DestReg, getDefRegState(true), SubIdx)
407  .addConstantPoolIndex(Idx)
408  .addImm(0).addImm(Pred).addReg(PredReg)
409  .setMIFlags(MIFlags);
410 }
411 
414  return true;
415 }
416 
419  return true;
420 }
421 
424  return true;
425 }
426 
429  return true;
430 }
431 
432 int64_t ARMBaseRegisterInfo::
433 getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
434  const MCInstrDesc &Desc = MI->getDesc();
435  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
436  int64_t InstrOffs = 0;
437  int Scale = 1;
438  unsigned ImmIdx = 0;
439  switch (AddrMode) {
442  case ARMII::AddrMode_i12:
443  InstrOffs = MI->getOperand(Idx+1).getImm();
444  Scale = 1;
445  break;
446  case ARMII::AddrMode5: {
447  // VFP address mode.
448  const MachineOperand &OffOp = MI->getOperand(Idx+1);
449  InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
450  if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
451  InstrOffs = -InstrOffs;
452  Scale = 4;
453  break;
454  }
455  case ARMII::AddrMode2: {
456  ImmIdx = Idx+2;
457  InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
458  if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
459  InstrOffs = -InstrOffs;
460  break;
461  }
462  case ARMII::AddrMode3: {
463  ImmIdx = Idx+2;
464  InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
465  if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
466  InstrOffs = -InstrOffs;
467  break;
468  }
469  case ARMII::AddrModeT1_s: {
470  ImmIdx = Idx+1;
471  InstrOffs = MI->getOperand(ImmIdx).getImm();
472  Scale = 4;
473  break;
474  }
475  default:
476  llvm_unreachable("Unsupported addressing mode!");
477  }
478 
479  return InstrOffs * Scale;
480 }
481 
482 /// needsFrameBaseReg - Returns true if the instruction's frame index
483 /// reference would be better served by a base register other than FP
484 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
485 /// references it should create new base registers for.
487 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
488  for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
489  assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
490  }
491 
492  // It's the load/store FI references that cause issues, as it can be difficult
493  // to materialize the offset if it won't fit in the literal field. Estimate
494  // based on the size of the local frame and some conservative assumptions
495  // about the rest of the stack frame (note, this is pre-regalloc, so
496  // we don't know everything for certain yet) whether this offset is likely
497  // to be out of range of the immediate. Return true if so.
498 
499  // We only generate virtual base registers for loads and stores, so
500  // return false for everything else.
501  unsigned Opc = MI->getOpcode();
502  switch (Opc) {
503  case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
504  case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
505  case ARM::t2LDRi12: case ARM::t2LDRi8:
506  case ARM::t2STRi12: case ARM::t2STRi8:
507  case ARM::VLDRS: case ARM::VLDRD:
508  case ARM::VSTRS: case ARM::VSTRD:
509  case ARM::tSTRspi: case ARM::tLDRspi:
510  break;
511  default:
512  return false;
513  }
514 
515  // Without a virtual base register, if the function has variable sized
516  // objects, all fixed-size local references will be via the frame pointer,
517  // Approximate the offset and see if it's legal for the instruction.
518  // Note that the incoming offset is based on the SP value at function entry,
519  // so it'll be negative.
520  MachineFunction &MF = *MI->getParent()->getParent();
521  const ARMFrameLowering *TFI = getFrameLowering(MF);
522  MachineFrameInfo *MFI = MF.getFrameInfo();
524 
525  // Estimate an offset from the frame pointer.
526  // Conservatively assume all callee-saved registers get pushed. R4-R6
527  // will be earlier than the FP, so we ignore those.
528  // R7, LR
529  int64_t FPOffset = Offset - 8;
530  // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
531  if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
532  FPOffset -= 80;
533  // Estimate an offset from the stack pointer.
534  // The incoming offset is relating to the SP at the start of the function,
535  // but when we access the local it'll be relative to the SP after local
536  // allocation, so adjust our SP-relative offset by that allocation size.
537  Offset += MFI->getLocalFrameSize();
538  // Assume that we'll have at least some spill slots allocated.
539  // FIXME: This is a total SWAG number. We should run some statistics
540  // and pick a real one.
541  Offset += 128; // 128 bytes of spill slots
542 
543  // If there's a frame pointer and the addressing mode allows it, try using it.
544  // The FP is only available if there is no dynamic realignment. We
545  // don't know for sure yet whether we'll need that, so we guess based
546  // on whether there are any local variables that would trigger it.
547  unsigned StackAlign = TFI->getStackAlignment();
548  if (TFI->hasFP(MF) &&
549  !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
550  if (isFrameOffsetLegal(MI, getFrameRegister(MF), FPOffset))
551  return false;
552  }
553  // If we can reference via the stack pointer, try that.
554  // FIXME: This (and the code that resolves the references) can be improved
555  // to only disallow SP relative references in the live range of
556  // the VLA(s). In practice, it's unclear how much difference that
557  // would make, but it may be worth doing.
558  if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, ARM::SP, Offset))
559  return false;
560 
561  // The offset likely isn't legal, we want to allocate a virtual base register.
562  return true;
563 }
564 
565 /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
566 /// be a pointer to FrameIdx at the beginning of the basic block.
569  unsigned BaseReg, int FrameIdx,
570  int64_t Offset) const {
572  unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
573  (AFI->isThumb1OnlyFunction() ? ARM::tADDframe : ARM::t2ADDri);
574 
576  DebugLoc DL; // Defaults to "unknown"
577  if (Ins != MBB->end())
578  DL = Ins->getDebugLoc();
579 
580  const MachineFunction &MF = *MBB->getParent();
581  MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
582  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
583  const MCInstrDesc &MCID = TII.get(ADDriOpc);
584  MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
585 
586  MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg)
587  .addFrameIndex(FrameIdx).addImm(Offset);
588 
589  if (!AFI->isThumb1OnlyFunction())
591 }
592 
594  int64_t Offset) const {
595  MachineBasicBlock &MBB = *MI.getParent();
596  MachineFunction &MF = *MBB.getParent();
597  const ARMBaseInstrInfo &TII =
598  *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
600  int Off = Offset; // ARM doesn't need the general 64-bit offsets
601  unsigned i = 0;
602 
603  assert(!AFI->isThumb1OnlyFunction() &&
604  "This resolveFrameIndex does not support Thumb1!");
605 
606  while (!MI.getOperand(i).isFI()) {
607  ++i;
608  assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
609  }
610  bool Done = false;
611  if (!AFI->isThumbFunction())
612  Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
613  else {
614  assert(AFI->isThumb2Function());
615  Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
616  }
617  assert (Done && "Unable to resolve frame index!");
618  (void)Done;
619 }
620 
622  int64_t Offset) const {
623  const MCInstrDesc &Desc = MI->getDesc();
624  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
625  unsigned i = 0;
626 
627  while (!MI->getOperand(i).isFI()) {
628  ++i;
629  assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
630  }
631 
632  // AddrMode4 and AddrMode6 cannot handle any offset.
633  if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
634  return Offset == 0;
635 
636  unsigned NumBits = 0;
637  unsigned Scale = 1;
638  bool isSigned = true;
639  switch (AddrMode) {
642  // i8 supports only negative, and i12 supports only positive, so
643  // based on Offset sign, consider the appropriate instruction
644  Scale = 1;
645  if (Offset < 0) {
646  NumBits = 8;
647  Offset = -Offset;
648  } else {
649  NumBits = 12;
650  }
651  break;
652  case ARMII::AddrMode5:
653  // VFP address mode.
654  NumBits = 8;
655  Scale = 4;
656  break;
657  case ARMII::AddrMode_i12:
658  case ARMII::AddrMode2:
659  NumBits = 12;
660  break;
661  case ARMII::AddrMode3:
662  NumBits = 8;
663  break;
664  case ARMII::AddrModeT1_s:
665  NumBits = (BaseReg == ARM::SP ? 8 : 5);
666  Scale = 4;
667  isSigned = false;
668  break;
669  default:
670  llvm_unreachable("Unsupported addressing mode!");
671  }
672 
673  Offset += getFrameIndexInstrOffset(MI, i);
674  // Make sure the offset is encodable for instructions that scale the
675  // immediate.
676  if ((Offset & (Scale-1)) != 0)
677  return false;
678 
679  if (isSigned && Offset < 0)
680  Offset = -Offset;
681 
682  unsigned Mask = (1 << NumBits) - 1;
683  if ((unsigned)Offset <= Mask * Scale)
684  return true;
685 
686  return false;
687 }
688 
689 void
691  int SPAdj, unsigned FIOperandNum,
692  RegScavenger *RS) const {
693  MachineInstr &MI = *II;
694  MachineBasicBlock &MBB = *MI.getParent();
695  MachineFunction &MF = *MBB.getParent();
696  const ARMBaseInstrInfo &TII =
697  *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
698  const ARMFrameLowering *TFI = getFrameLowering(MF);
700  assert(!AFI->isThumb1OnlyFunction() &&
701  "This eliminateFrameIndex does not support Thumb1!");
702  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
703  unsigned FrameReg;
704 
705  int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
706 
707  // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the
708  // call frame setup/destroy instructions have already been eliminated. That
709  // means the stack pointer cannot be used to access the emergency spill slot
710  // when !hasReservedCallFrame().
711 #ifndef NDEBUG
712  if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){
713  assert(TFI->hasReservedCallFrame(MF) &&
714  "Cannot use SP to access the emergency spill slot in "
715  "functions without a reserved call frame");
716  assert(!MF.getFrameInfo()->hasVarSizedObjects() &&
717  "Cannot use SP to access the emergency spill slot in "
718  "functions with variable sized frame objects");
719  }
720 #endif // NDEBUG
721 
722  assert(!MI.isDebugValue() && "DBG_VALUEs should be handled in target-independent code");
723 
724  // Modify MI as necessary to handle as much of 'Offset' as possible
725  bool Done = false;
726  if (!AFI->isThumbFunction())
727  Done = rewriteARMFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);
728  else {
729  assert(AFI->isThumb2Function());
730  Done = rewriteT2FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);
731  }
732  if (Done)
733  return;
734 
735  // If we get here, the immediate doesn't fit into the instruction. We folded
736  // as much as possible above, handle the rest, providing a register that is
737  // SP+LargeImm.
738  assert((Offset ||
741  "This code isn't needed if offset already handled!");
742 
743  unsigned ScratchReg = 0;
744  int PIdx = MI.findFirstPredOperandIdx();
745  ARMCC::CondCodes Pred = (PIdx == -1)
747  unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
748  if (Offset == 0)
749  // Must be addrmode4/6.
750  MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, false);
751  else {
752  ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass);
753  if (!AFI->isThumbFunction())
754  emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
755  Offset, Pred, PredReg, TII);
756  else {
757  assert(AFI->isThumb2Function());
758  emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
759  Offset, Pred, PredReg, TII);
760  }
761  // Update the original instruction to use the scratch register.
762  MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false,true);
763  }
764 }
765 
767  const TargetRegisterClass *SrcRC,
768  unsigned SubReg,
769  const TargetRegisterClass *DstRC,
770  unsigned DstSubReg,
771  const TargetRegisterClass *NewRC) const {
772  auto MBB = MI->getParent();
773  auto MF = MBB->getParent();
774  const MachineRegisterInfo &MRI = MF->getRegInfo();
775  // If not copying into a sub-register this should be ok because we shouldn't
776  // need to split the reg.
777  if (!DstSubReg)
778  return true;
779  // Small registers don't frequently cause a problem, so we can coalesce them.
780  if (NewRC->getSize() < 32 && DstRC->getSize() < 32 && SrcRC->getSize() < 32)
781  return true;
782 
783  auto NewRCWeight =
785  auto SrcRCWeight =
787  auto DstRCWeight =
789  // If the source register class is more expensive than the destination, the
790  // coalescing is probably profitable.
791  if (SrcRCWeight.RegWeight > NewRCWeight.RegWeight)
792  return true;
793  if (DstRCWeight.RegWeight > NewRCWeight.RegWeight)
794  return true;
795 
796  // If the register allocator isn't constrained, we can always allow coalescing
797  // unfortunately we don't know yet if we will be constrained.
798  // The goal of this heuristic is to restrict how many expensive registers
799  // we allow to coalesce in a given basic block.
800  auto AFI = MF->getInfo<ARMFunctionInfo>();
801  auto It = AFI->getCoalescedWeight(MBB);
802 
803  DEBUG(dbgs() << "\tARM::shouldCoalesce - Coalesced Weight: "
804  << It->second << "\n");
805  DEBUG(dbgs() << "\tARM::shouldCoalesce - Reg Weight: "
806  << NewRCWeight.RegWeight << "\n");
807 
808  // This number is the largest round number that which meets the criteria:
809  // (1) addresses PR18825
810  // (2) generates better code in some test cases (like vldm-shed-a9.ll)
811  // (3) Doesn't regress any test cases (in-tree, test-suite, and SPEC)
812  // In practice the SizeMultiplier will only factor in for straight line code
813  // that uses a lot of NEON vectors, which isn't terribly common.
814  unsigned SizeMultiplier = MBB->size()/100;
815  SizeMultiplier = SizeMultiplier ? SizeMultiplier : 1;
816  if (It->second < NewRCWeight.WeightLimit * SizeMultiplier) {
817  It->second += NewRCWeight.RegWeight;
818  return true;
819  }
820  return false;
821 }
bool hasPhys(unsigned virtReg) const
returns true if the specified virtual register is mapped to a physical register
Definition: VirtRegMap.h:92
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
void push_back(const T &Elt)
Definition: SmallVector.h:222
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
BitVector & set()
Definition: BitVector.h:218
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const override
materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx...
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:223
static unsigned char getAM3Offset(unsigned AM3Opc)
Alignment of stack for function (3 bits) stored as log2 of alignment with +1 bias 0 means unaligned (...
Definition: Attributes.h:106
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:138
iterator end() const
Definition: ArrayRef.h:123
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
void emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
int ResolveFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg, int SPAdj) const
unsigned getID() const
getID() - Return the register class ID number.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:264
A debug info location.
Definition: DebugLoc.h:34
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:225
F(f)
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
bool isThumb1Only() const
Definition: ARMSubtarget.h:405
aarch64 collect AArch64 Collect Linker Optimization Hint(LOH)"
bool canReserveReg(unsigned PhysReg) const
canReserveReg - Returns true if PhysReg can be used as a reserved register.
void updateRegAllocHint(unsigned Reg, unsigned NewReg, MachineFunction &MF) const override
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
needsFrameBaseReg - Returns true if the instruction's frame index reference would be better served by...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:172
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
bool isR9Reserved() const
Definition: ARMSubtarget.h:416
int64_t getLocalFrameSize() const
Get the size of the local object blob.
unsigned getSize() const
getSize - Return the size of the register in bytes, which is also the size of a stack slot allocated ...
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
void getRegAllocationHints(unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM) const override
static const MachineInstrBuilder & AddDefaultPred(const MachineInstrBuilder &MIB)
static unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
bool hasVFP3() const
Definition: ARMSubtarget.h:315
MCSuperRegIterator enumerates all super-registers of Reg.
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
const HexagonInstrInfo * TII
const TargetRegisterInfo * getTargetRegisterInfo() const
bool isTargetDarwin() const
Definition: ARMSubtarget.h:355
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
unsigned getFrameRegister(const MachineFunction &MF) const override
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required, we reserve argument space for call sites in the function immediately on entry to the current function.
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const ARMBaseInstrInfo &TII)
rewriteARMFrameIndex / rewriteT2FrameIndex - Rewrite MI to access 'Offset' bytes from the FP...
iterator begin() const
begin/end - Return all of the registers in this class.
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Definition: Value.cpp:317
bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const ARMBaseInstrInfo &TII)
bool isThumb() const
Definition: ARMSubtarget.h:404
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:271
bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
const uint32_t * getThisReturnPreservedMask(const MachineFunction &MF, CallingConv::ID) const
getThisReturnPreservedMask - Returns a call preserved mask specific to the case that 'returned' is on...
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
bool isTargetMachO() const
Definition: ARMSubtarget.h:364
unsigned getLocalFrameMaxAlign() const
Return the required alignment of the local object blob.
int64_t getImm() const
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:134
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:267
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:120
TargetInstrInfo - Interface to description of machine instruction set.
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
bool isDebugValue() const
Definition: MachineInstr.h:748
unsigned getDefRegState(bool B)
bundle_iterator< MachineInstr, instr_iterator > iterator
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override
bool requiresRegisterScavenging(const MachineFunction &MF) const override
Code Generation virtual methods...
int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const override
This is an important base class in LLVM.
Definition: Constant.h:41
bool isReserved(unsigned PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
static unsigned char getAM5Offset(unsigned AM5Opc)
bool isMClass() const
Definition: ARMSubtarget.h:408
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
iterator begin() const
Definition: ArrayRef.h:122
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
const TargetRegisterClass *const * sc_iterator
static unsigned getFramePointerReg(const ARMSubtarget &STI)
virtual void getRegAllocationHints(unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr) const
Get a list of 'hint' registers that the register allocator should try first when allocating a physica...
MCSubRegIterator enumerates all sub-registers of Reg.
void emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of instructions to materializea des...
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
bool canRealignStack(const MachineFunction &MF) const
bool isScavengingFrameIndex(int FI) const
Query whether a frame index is a scavenging frame index.
static AddrOpc getAM2Op(unsigned AM2Opc)
static const MachineInstrBuilder & AddDefaultCC(const MachineInstrBuilder &MIB)
#define R6(n)
static unsigned getAM2Offset(unsigned AM2Opc)
MachineOperand class - Representation of each machine instruction operand.
virtual const RegClassWeight & getRegClassWeight(const TargetRegisterClass *RC) const =0
Get the weight in units of pressure for this register class.
void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg)
setRegAllocationHint - Specify a register allocation hint for the specified virtual register...
bool test(unsigned Idx) const
Definition: BitVector.h:322
const uint32_t * getNoPreservedMask() const
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:582
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const MachineInstrBuilder & addFrameIndex(int Idx) const
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:123
bool hasBasePointer(const MachineFunction &MF) const
AddrMode
ARM Addressing Modes.
Definition: ARMBaseInfo.h:235
static AddrOpc getAM3Op(unsigned AM3Opc)
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:238
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override
Representation of each machine instruction.
Definition: MachineInstr.h:51
static bool isPhysicalRegister(unsigned Reg)
isPhysicalRegister - Return true if the specified register number is in the physical register namespa...
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:217
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static IntegerType * getInt32Ty(LLVMContext &C)
Definition: Type.cpp:239
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC) const override
SrcRC and DstRC will be morphed into NewRC if this returns true.
#define I(x, y, z)
Definition: MD5.cpp:54
unsigned BasePtr
BasePtr - ARM physical register used as a base ptr in complex stack frames.
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
static AddrOpc getAM5Op(unsigned AM5Opc)
virtual void emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred=ARMCC::AL, unsigned PredReg=0, unsigned MIFlags=MachineInstr::NoFlags) const
emitLoadConstPool - Emits a load from constpool to materialize the specified immediate.
unsigned getReg() const
getReg - Returns the register number.
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:140
const ARM::ArchExtKind Kind
bool cannotEliminateFrame(const MachineFunction &MF) const
virtual const TargetInstrInfo * getInstrInfo() const
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
#define DEBUG(X)
Definition: Debug.h:92
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
unsigned getPhys(unsigned virtReg) const
returns the physical register mapped to the specified virtual register
Definition: VirtRegMap.h:98
const TargetRegisterClass * getRegClass(const MCInstrDesc &TID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum...
bool hasD16() const
Definition: ARMSubtarget.h:351
std::pair< unsigned, unsigned > getRegAllocationHint(unsigned VReg) const
getRegAllocationHint - Return the register allocation hint for the specified virtual register...
DenseMap< const MachineBasicBlock *, unsigned >::iterator getCoalescedWeight(MachineBasicBlock *MBB)
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
bool needsStackRealignment(const MachineFunction &MF) const override
bool isTargetWindows() const
Definition: ARMSubtarget.h:360
sc_iterator getSuperClasses() const
getSuperClasses - Returns a NULL terminated list of super-classes.
unsigned getConstantPoolIndex(const Constant *C, unsigned Alignment)
getConstantPoolIndex - Create a new entry in the constant pool or return an existing one...