15 #ifndef LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
16 #define LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
378 unsigned ShuffleKind, SelectionDAG &DAG);
383 unsigned ShuffleKind, SelectionDAG &DAG);
388 unsigned ShuffleKind, SelectionDAG &DAG);
408 SDValue
get_VSPLTI_elt(SDNode *N,
unsigned ByteSize, SelectionDAG &DAG);
440 EVT VT)
const override;
491 std::vector<SDNode *> *Created)
const override;
500 unsigned Depth = 0)
const override;
505 bool IsStore,
bool IsLoad)
const override;
507 bool IsStore,
bool IsLoad)
const override;
515 unsigned BinOpcode)
const;
518 bool is8bit,
unsigned Opcode)
const;
531 AsmOperandInfo &
info,
const char *constraint)
const override;
533 std::pair<unsigned, const TargetRegisterClass *>
546 std::string &Constraint,
547 std::vector<SDValue> &Ops,
552 if (ConstraintCode ==
"es")
554 else if (ConstraintCode ==
"o")
556 else if (ConstraintCode ==
"Q")
558 else if (ConstraintCode ==
"Z")
560 else if (ConstraintCode ==
"Zy")
568 Type *Ty,
unsigned AS)
const override;
595 Type *Ty)
const override;
601 unsigned Intrinsic)
const override;
616 bool IsMemset,
bool ZeroMemset,
bool MemcpyStrSrc,
624 bool *
Fast =
nullptr)
const override;
637 unsigned DefinedValues)
const override;
660 struct ReuseLoadInfo {
670 ReuseLoadInfo() : IsInvariant(
false), Alignment(0),
Ranges(nullptr) {}
673 bool canReuseLoadAddress(SDValue Op, EVT MemVT, ReuseLoadInfo &RLI,
676 void spliceIntoChain(SDValue ResChain, SDValue NewResChain,
677 SelectionDAG &DAG)
const;
679 void LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
680 SelectionDAG &DAG, SDLoc dl)
const;
681 SDValue LowerFP_TO_INTDirectMove(SDValue Op, SelectionDAG &DAG,
683 SDValue LowerINT_TO_FPDirectMove(SDValue Op, SelectionDAG &DAG,
686 SDValue getFramePointerFrameIndex(SelectionDAG & DAG)
const;
687 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG)
const;
690 IsEligibleForTailCallOptimization(SDValue Callee,
693 const SmallVectorImpl<ISD::InputArg> &
Ins,
694 SelectionDAG& DAG)
const;
696 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
704 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG)
const;
705 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG)
const;
706 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG)
const;
707 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG)
const;
708 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG)
const;
709 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG)
const;
710 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG)
const;
711 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG)
const;
712 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG)
const;
713 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG)
const;
714 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
715 const PPCSubtarget &Subtarget)
const;
716 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG,
717 const PPCSubtarget &Subtarget)
const;
718 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG,
719 const PPCSubtarget &Subtarget)
const;
720 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
721 const PPCSubtarget &Subtarget)
const;
722 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
723 const PPCSubtarget &Subtarget)
const;
724 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG)
const;
725 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG)
const;
726 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG)
const;
727 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG)
const;
728 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, SDLoc dl)
const;
729 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG)
const;
730 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG)
const;
731 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG)
const;
732 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG)
const;
733 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG)
const;
734 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG)
const;
735 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG)
const;
736 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG)
const;
737 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG)
const;
738 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG)
const;
739 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG)
const;
740 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG)
const;
742 SDValue LowerVectorLoad(SDValue Op, SelectionDAG &DAG)
const;
743 SDValue LowerVectorStore(SDValue Op, SelectionDAG &DAG)
const;
745 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
747 const SmallVectorImpl<ISD::InputArg> &
Ins,
748 SDLoc dl, SelectionDAG &DAG,
749 SmallVectorImpl<SDValue> &InVals)
const;
750 SDValue FinishCall(
CallingConv::ID CallConv, SDLoc dl,
bool isTailCall,
751 bool isVarArg,
bool IsPatchPoint,
bool hasNest,
753 SmallVector<std::pair<unsigned, SDValue>, 8>
755 SDValue InFlag, SDValue Chain, SDValue CallSeqStart,
757 int SPDiff,
unsigned NumBytes,
758 const SmallVectorImpl<ISD::InputArg> &
Ins,
759 SmallVectorImpl<SDValue> &InVals,
760 ImmutableCallSite *
CS)
const;
763 LowerFormalArguments(SDValue Chain,
765 const SmallVectorImpl<ISD::InputArg> &
Ins,
766 SDLoc dl, SelectionDAG &DAG,
767 SmallVectorImpl<SDValue> &InVals)
const override;
770 LowerCall(TargetLowering::CallLoweringInfo &CLI,
771 SmallVectorImpl<SDValue> &InVals)
const override;
776 const SmallVectorImpl<ISD::OutputArg> &Outs,
777 LLVMContext &Context)
const override;
780 LowerReturn(SDValue Chain,
782 const SmallVectorImpl<ISD::OutputArg> &Outs,
783 const SmallVectorImpl<SDValue> &OutVals,
784 SDLoc dl, SelectionDAG &DAG)
const override;
787 extendArgForPPC64(ISD::ArgFlagsTy
Flags, EVT ObjectVT, SelectionDAG &DAG,
788 SDValue ArgVal, SDLoc dl)
const;
791 LowerFormalArguments_Darwin(SDValue Chain,
793 const SmallVectorImpl<ISD::InputArg> &
Ins,
794 SDLoc dl, SelectionDAG &DAG,
795 SmallVectorImpl<SDValue> &InVals)
const;
797 LowerFormalArguments_64SVR4(SDValue Chain,
799 const SmallVectorImpl<ISD::InputArg> &
Ins,
800 SDLoc dl, SelectionDAG &DAG,
801 SmallVectorImpl<SDValue> &InVals)
const;
803 LowerFormalArguments_32SVR4(SDValue Chain,
805 const SmallVectorImpl<ISD::InputArg> &
Ins,
806 SDLoc dl, SelectionDAG &DAG,
807 SmallVectorImpl<SDValue> &InVals)
const;
810 createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
811 SDValue CallSeqStart, ISD::ArgFlagsTy
Flags,
812 SelectionDAG &DAG, SDLoc dl)
const;
815 LowerCall_Darwin(SDValue Chain, SDValue Callee,
817 bool isVarArg,
bool isTailCall,
bool IsPatchPoint,
818 const SmallVectorImpl<ISD::OutputArg> &Outs,
819 const SmallVectorImpl<SDValue> &OutVals,
820 const SmallVectorImpl<ISD::InputArg> &
Ins,
821 SDLoc dl, SelectionDAG &DAG,
822 SmallVectorImpl<SDValue> &InVals,
823 ImmutableCallSite *
CS)
const;
825 LowerCall_64SVR4(SDValue Chain, SDValue Callee,
827 bool isVarArg,
bool isTailCall,
bool IsPatchPoint,
828 const SmallVectorImpl<ISD::OutputArg> &Outs,
829 const SmallVectorImpl<SDValue> &OutVals,
830 const SmallVectorImpl<ISD::InputArg> &
Ins,
831 SDLoc dl, SelectionDAG &DAG,
832 SmallVectorImpl<SDValue> &InVals,
833 ImmutableCallSite *
CS)
const;
835 LowerCall_32SVR4(SDValue Chain, SDValue Callee,
CallingConv::ID CallConv,
836 bool isVarArg,
bool isTailCall,
bool IsPatchPoint,
837 const SmallVectorImpl<ISD::OutputArg> &Outs,
838 const SmallVectorImpl<SDValue> &OutVals,
839 const SmallVectorImpl<ISD::InputArg> &
Ins,
840 SDLoc dl, SelectionDAG &DAG,
841 SmallVectorImpl<SDValue> &InVals,
842 ImmutableCallSite *
CS)
const;
844 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG)
const;
845 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG)
const;
847 SDValue DAGCombineExtBoolTrunc(SDNode *
N, DAGCombinerInfo &DCI)
const;
848 SDValue DAGCombineTruncBoolExt(SDNode *
N, DAGCombinerInfo &DCI)
const;
849 SDValue combineFPToIntToFP(SDNode *
N, DAGCombinerInfo &DCI)
const;
851 SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI,
852 unsigned &RefinementSteps,
853 bool &UseOneConstNR)
const override;
854 SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI,
855 unsigned &RefinementSteps)
const override;
856 bool combineRepeatedFPDivisors(
unsigned NumUsers)
const override;
863 const TargetLibraryInfo *LibInfo);
868 ISD::ArgFlagsTy &ArgFlags,
874 ISD::ArgFlagsTy &ArgFlags,
880 ISD::ArgFlagsTy &ArgFlags,
884 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
PPCTargetLowering(const PPCTargetMachine &TM, const PPCSubtarget &STI)
G8RC = ADDI_TLSLD_L_ADDR G8RReg, Symbol, Symbol - Op that combines ADDI_TLSLD_L and GET_TLSLD_ADDR un...
X3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS model, produces an ADDI8 instruction tha...
BUILTIN_OP_END - This must be the last enum value in this list.
A parsed version of the target data layout string in and methods for querying it. ...
SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const
MachineBasicBlock * EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *MBB, unsigned AtomicSize, unsigned BinOpcode) const
FastISel * createFastISel(FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo)
Return with a flag operand, matched by 'blr'.
Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for unsigned integers.
SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG)
get_VSPLTI_elt - If this is a build_vector of constants which can be formed by using a vspltis[bhw] i...
GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a byte-swapping load instruction.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
unsigned getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const override
Return the register ID of the name passed in.
unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const override
getByValTypeAlignment - Return the desired alignment for ByVal aggregate function arguments in the ca...
QVFPERM = This corresponds to the QPX qvfperm instruction.
GPRC = address of GLOBAL_OFFSET_TABLE.
G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS model, produces an ADDI8 instruction ...
bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
MachineBasicBlock * EmitPartwordAtomicBinary(MachineInstr *MI, MachineBasicBlock *MBB, bool is8bit, unsigned Opcode) const
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
The following two target-specific nodes are used for calls through function pointers in the 64-bit SV...
VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded during instruction selection to optimi...
CallInst - This class represents a function call, abstracting a target machine's calling convention...
QBRC, CHAIN = QVLFSb CHAIN, Ptr The 4xf32 load used for v4i1 constants.
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
CHAIN = RFEBB CHAIN, State - Return from event-based branch.
bool shouldExpandBuildVectorWithShuffles(EVT VT, unsigned DefinedValues) const override
CALL - A direct function call.
CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a BCTRL instruction.
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...
bool isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a VPKUDUM instruction.
bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
getPreIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mod...
Newer FCFID[US] integer-to-floating-point conversion instructions for unsigned integers and single-pr...
bool isLegalICmpImmediate(int64_t Imm) const override
isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a VPKUHUM instruction.
GlobalBaseReg - On Darwin, this node represents the result of the mflr at function entry...
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, unsigned Align=1, bool *Fast=nullptr) const override
Is unaligned memory access allowed for the given type, and is it fast relative to software emulation...
bool isFPExtFree(EVT VT) const override
Return true if an fpext operation is free (for instance, because single-precision floating-point numb...
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
MachineBasicBlock * emitEHSjLjLongJmp(MachineInstr *MI, MachineBasicBlock *MBB) const
G8RC = ADDI_TLSGD_L_ADDR G8RReg, Symbol, Symbol - Op that combines ADDI_TLSGD_L and GET_TLS_ADDR unti...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
Direct move from a GPR to a VSX register (algebraic)
X3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS model, produces an ADDI8 instruction t...
QVALIGNI = This corresponds to the QPX qvaligni instruction.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Sched::Preference getSchedulingPreference() const
Return target scheduling preference.
unsigned getPrefLoopAlignment(MachineLoop *ML) const override
Return the preferred loop alignment.
bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override
Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calli...
bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize)
isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand specifies a splat of a singl...
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - Return the ISD::SETCC ValueType
CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based loops.
R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
G8RC = ADDIS_TLSGD_HA X2, Symbol - For the general-dynamic TLS model, produces an ADDIS8 instruction ...
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Returns true if it is beneficial to convert a load of a constant to just the constant itself...
CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, MachineFunction &MF) const override
getOptimalMemOpType - Returns the target specific optimal type for load and store operations as a res...
bool isArrayTy() const
isArrayTy - True if this is an instance of ArrayType.
bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG)
isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for a VRGL* instruction with the ...
bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
bool isFMAFasterThanFMulAndFAdd(EVT VT) const override
isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster than a pair of fmul and fadd i...
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
ReplaceNodeResults - Replace the results of node with an illegal result type with new values built ou...
Flag
These should be considered private to the implementation of the MCInstrDesc class.
VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
Instruction * emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord, bool IsStore, bool IsLoad) const override
FSEL - Traditional three-operand fsel node.
MVT - Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
This is an important class for using LLVM in a threaded context.
ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
G8RC = ADDIS_DTPREL_HA X3, Symbol - For the local-dynamic TLS model, produces an ADDIS8 instruction t...
Direct move from a VSX register to a GPR.
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a MTCTR instruction.
unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize, SelectionDAG &DAG)
getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the specified isSplatShuffleMask...
STFIWX - The STFIWX instruction.
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint, return the type of constraint it is for this target...
FCFID - The FCFID instruction, taking an f64 operand and producing and f64 value containing the FP re...
bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a VPKUWUM instruction.
CHAIN = CLRBHRB CHAIN - Clear branch history rolling buffer.
GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point load which sign-extends from a 32-bit inte...
G8RC = ADDIS_TLSLD_HA X2, Symbol - For the local-dynamic TLS model, produces an ADDIS8 instruction th...
G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec TLS model, produces a LD instruction ...
QVESPLATI = This corresponds to the QPX qvesplati instruction.
void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
PPCTargetMachine - Common code between 32-bit and 64-bit PowerPC targets.
int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift amount, otherwise return -1...
EVT - Extended Value Type.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
MachinePointerInfo - This class contains a discriminated union of information about pointers in memor...
Instruction * emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord, bool IsStore, bool IsLoad) const override
Inserts in the IR a target-specific intrinsic specifying a fence.
CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl instruction and the TOC reload r...
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector.
QBFLT = Access the underlying QPX floating-point boolean representation.
X3 = GET_TLSLD_ADDR X3, Symbol - For the local-dynamic TLS model, produces a call to __tls_get_addr(s...
GPRC = TOC_ENTRY GA, TOC Loads the entry for GA from the TOC, where the TOC base is given by the last...
SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, std::vector< SDNode * > *Created) const override
bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS model, produces an ADD instruction that ...
bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG) const
SelectAddressRegRegOnly - Given the specified addressed, force it to be represented as an indexed [r+...
Provides information about what library functions are available for the current target.
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
CHAIN = SC CHAIN, Imm128 - System call.
const char * getTargetNodeName(unsigned Opcode) const override
getTargetNodeName() - This method returns the name of a target specific DAG node. ...
bool enableAggressiveFMAFusion(EVT VT) const override
Return true if target always beneficiates from combining into FMA for a given value type...
X3 = GET_TLS_ADDR X3, Symbol - For the general-dynamic TLS model, produces a call to __tls_get_addr(s...
bool isCheapToSpeculateCttz() const override
Return true if it is cheap to speculate a call to intrinsic cttz.
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Represents one node in the SelectionDAG.
MachineBasicBlock * emitEHSjLjSetJmp(MachineInstr *MI, MachineBasicBlock *MBB) const
VPERM - The PPC VPERM Instruction.
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
i1 = ANDIo_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the eq or gt bit of CR0 after execu...
SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const
G8RC = ADDIS_GOT_TPREL_HA X2, Symbol - Used by the initial-exec TLS model, produces an ADDIS8 instruc...
Class for arbitrary precision integers.
QVGPCI = This corresponds to the QPX qvgpci instruction.
bool isLegalAddImmediate(int64_t Imm) const override
isLegalAddImmediate - Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register and the immediate without having to materialize the immediate into a register.
AddrMode
ARM Addressing Modes.
bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG) const
SelectAddressRegReg - Given the specified addressed, check to see if it can be represented as an inde...
The combination of sra[wd]i and addze used to implemented signed integer division by a power of 2...
GPRC = address of GLOBAL_OFFSET_TABLE.
Representation of each machine instruction.
GPRC, CHAIN = MFBHRBE CHAIN, Entry, Dummy - Move from branch history rolling buffer entry...
const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const override
Returns a 0 terminated array of registers that can be safely used as scratch registers.
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
Reciprocal estimate instructions (unary FP ops).
bool isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven, unsigned ShuffleKind, SelectionDAG &DAG)
isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for a VMRGEW or VMRGOW instructi...
F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
Direct move from a GPR to a VSX register (zero)
Fast - This calling convention attempts to make calls as fast as possible (e.g.
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
The CMPB instruction (takes two operands of i32 or i64).
CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a byte-swapping store instruction. ...
TC_RETURN - A tail call return.
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little endian.
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG, bool Aligned) const
SelectAddressRegImm - Returns true if the address N can be represented by a base register plus a sign...
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
isTruncateFree - Return true if it's free to truncate a value of type Ty1 to type Ty2...
CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This corresponds to the COND_BRANCH pseudo ...
These nodes represent the 32-bit PPC shifts that operate on 6-bit shift amounts.
StringRef - Represent a constant reference to a string, i.e.
RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP* instructions.
FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 operand, producing an f64 value...
Hi/Lo - These represent the high and low 16-bit parts of a global address respectively.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
FastISel * createFastISel(FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo) const override
createFastISel - This method returns a target-specific FastISel object, or null if the target does no...
F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding towards zero.
RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the altivec VCMP*o instructions.
GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point load which zero-extends from a 32-bit inte...
bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG)
isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for a VRGH* instruction with the ...
This file describes how to lower LLVM code to machine code.
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
bool isZExtFree(SDValue Val, EVT VT2) const override
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicit...
int isQVALIGNIShuffleMask(SDNode *N)
If this is a qvaligni shuffle mask, return the shift amount, otherwise return -1. ...