68 #define DEBUG_TYPE "isel"
76 cl::desc(
"Generate low-precision inline sequences "
77 "for some float libcalls"),
83 cl::desc(
"Enable fast-math-flags for DAG nodes"));
102 const SDValue *Parts,
unsigned NumParts,
112 unsigned NumParts,
MVT PartVT,
EVT ValueVT,
119 assert(NumParts > 0 &&
"No parts to assemble!");
130 unsigned RoundParts = NumParts & (NumParts - 1) ?
131 1 <<
Log2_32(NumParts) : NumParts;
132 unsigned RoundBits = PartBits * RoundParts;
133 EVT RoundVT = RoundBits == ValueBits ?
139 if (RoundParts > 2) {
143 RoundParts / 2, PartVT, HalfVT, V);
154 if (RoundParts < NumParts) {
156 unsigned OddParts = NumParts - RoundParts;
159 Parts + RoundParts, OddParts, PartVT, OddVT, V);
169 DAG.
getConstant(Lo.getValueType().getSizeInBits(), DL,
187 !PartVT.
isVector() &&
"Unexpected split");
196 if (PartEVT == ValueVT)
200 if (ValueVT.
bitsLT(PartEVT)) {
205 Val = DAG.
getNode(AssertOp, DL, PartEVT, Val,
229 const Twine &ErrMsg) {
230 const Instruction *
I = dyn_cast_or_null<Instruction>(V);
234 const char *AsmError =
", possible invalid constraint for vector type";
235 if (
const CallInst *CI = dyn_cast<CallInst>(I))
236 if (isa<InlineAsm>(CI->getCalledValue()))
237 return Ctx.
emitError(I, ErrMsg + AsmError);
248 const SDValue *Parts,
unsigned NumParts,
250 assert(ValueVT.
isVector() &&
"Not a vector value");
251 assert(NumParts > 0 &&
"No parts to assemble!");
259 unsigned NumIntermediates;
262 NumIntermediates, RegisterVT);
263 assert(NumRegs == NumParts &&
"Part count doesn't match vector breakdown!");
265 assert(RegisterVT == PartVT &&
"Part type doesn't match vector breakdown!");
268 "Part type sizes don't match!");
272 if (NumIntermediates == NumParts) {
275 for (
unsigned i = 0; i != NumParts; ++i)
277 PartVT, IntermediateVT, V);
278 }
else if (NumParts > 0) {
281 assert(NumParts % NumIntermediates == 0 &&
282 "Must expand into a divisible number of parts!");
283 unsigned Factor = NumParts / NumIntermediates;
284 for (
unsigned i = 0; i != NumIntermediates; ++i)
286 PartVT, IntermediateVT, V);
299 if (PartEVT == ValueVT)
309 "Cannot narrow, it would be a lossy transformation");
320 "Cannot handle this kind of promotion");
322 bool Smaller = ValueVT.
bitsLE(PartEVT);
337 "non-trivial scalar-to-vector conversion");
343 bool Smaller = ValueVT.
bitsLE(PartEVT);
369 unsigned OrigNumParts = NumParts;
371 "Copying to an illegal type!");
376 assert(!ValueVT.
isVector() &&
"Vector case handled elsewhere");
377 EVT PartEVT = PartVT;
378 if (PartEVT == ValueVT) {
379 assert(NumParts == 1 &&
"No-op copy with multiple parts!");
387 assert(NumParts == 1 &&
"Do not know what to promote to!");
392 "Unknown mismatch!");
394 Val = DAG.
getNode(ExtendKind, DL, ValueVT, Val);
400 assert(NumParts == 1 && PartEVT != ValueVT);
406 "Unknown mismatch!");
416 "Failed to tile the value with PartVT!");
419 if (PartEVT != ValueVT)
421 "scalar-to-vector conversion failed");
428 if (NumParts & (NumParts - 1)) {
431 "Do not know what to expand to!");
432 unsigned RoundParts = 1 <<
Log2_32(NumParts);
433 unsigned RoundBits = RoundParts * PartBits;
434 unsigned OddParts = NumParts - RoundParts;
437 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
441 std::reverse(Parts + RoundParts, Parts + NumParts);
443 NumParts = RoundParts;
455 for (
unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
456 for (
unsigned i = 0; i < NumParts; i += StepSize) {
457 unsigned ThisBits = StepSize * PartBits / 2;
460 SDValue &Part1 = Parts[i+StepSize/2];
467 if (ThisBits == PartBits && ThisVT != PartVT) {
475 std::reverse(Parts, Parts + OrigNumParts);
485 assert(ValueVT.
isVector() &&
"Not a vector");
489 EVT PartEVT = PartVT;
490 if (PartEVT == ValueVT) {
523 bool Smaller = PartEVT.
bitsLE(ValueVT);
529 "Only trivial vector-to-scalar conversions should get here!");
534 bool Smaller = ValueVT.
bitsLE(PartVT);
546 unsigned NumIntermediates;
547 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.
getContext(), ValueVT,
549 NumIntermediates, RegisterVT);
552 assert(NumRegs == NumParts &&
"Part count doesn't match vector breakdown!");
554 assert(RegisterVT == PartVT &&
"Part type doesn't match vector breakdown!");
558 for (
unsigned i = 0; i != NumIntermediates; ++i) {
559 if (IntermediateVT.isVector())
562 DAG.
getConstant(i * (NumElements / NumIntermediates), DL,
571 if (NumParts == NumIntermediates) {
574 for (
unsigned i = 0; i != NumParts; ++i)
576 }
else if (NumParts > 0) {
579 assert(NumIntermediates != 0 &&
"division by zero");
580 assert(NumParts % NumIntermediates == 0 &&
581 "Must expand into a divisible number of parts!");
582 unsigned Factor = NumParts / NumIntermediates;
583 for (
unsigned i = 0; i != NumIntermediates; ++i)
584 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
592 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
602 for (
unsigned i = 0; i != NumRegs; ++i)
604 RegVTs.push_back(RegisterVT);
617 const Value *V)
const {
634 for (
unsigned i = 0; i != NumRegs; ++i) {
661 if (NumZeroBits == RegSize) {
673 if (NumSignBits == RegSize)
674 isSExt =
true, FromVT =
MVT::i1;
675 else if (NumZeroBits >= RegSize-1)
676 isSExt =
false, FromVT =
MVT::i1;
677 else if (NumSignBits > RegSize-8)
678 isSExt =
true, FromVT =
MVT::i8;
679 else if (NumZeroBits >= RegSize-8)
680 isSExt =
false, FromVT =
MVT::i8;
681 else if (NumSignBits > RegSize-16)
683 else if (NumZeroBits >= RegSize-16)
685 else if (NumSignBits > RegSize-32)
687 else if (NumZeroBits >= RegSize-32)
699 NumRegs, RegisterVT, ValueVT, V);
729 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
735 for (
unsigned i = 0; i != NumRegs; ++i) {
747 if (NumRegs == 1 || Flag)
758 Chain = Chains[NumRegs-1];
767 unsigned MatchingIdx,
SDLoc dl,
769 std::vector<SDValue> &Ops)
const {
794 for (
unsigned i = 0; i != NumRegs; ++i) {
795 assert(
Reg <
Regs.
size() &&
"Mismatch in # registers expected");
802 hasOpaqueSPAdjustment());
826 UnusedArgNodeMap.clear();
828 PendingExports.clear();
842 DanglingDebugInfoMap.clear();
876 if (PendingExports.empty())
881 unsigned i = 0, e = PendingExports.size();
882 for (; i != e; ++i) {
883 assert(PendingExports[i].getNode()->getNumOperands() > 1);
884 if (PendingExports[i].getNode()->getOperand(0) == Root)
889 PendingExports.push_back(Root);
894 PendingExports.clear();
901 if (isa<TerminatorInst>(&I))
902 HandlePHINodesInSuccessorBlocks(I.
getParent());
916 void SelectionDAGBuilder::visitPHI(
const PHINode &) {
926 #define HANDLE_INST(NUM, OPCODE, CLASS) \
927 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
928 #include "llvm/IR/Instruction.def"
936 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
940 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
944 "Expected inlined-at fields to agree");
947 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
950 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, dl, Offset, IsIndirect,
953 IsIndirect, Offset, dl, DbgSDNodeOrder);
957 DEBUG(
dbgs() <<
"Dropping debug info for " << *DI <<
"\n");
958 DanglingDebugInfoMap[V] = DanglingDebugInfo();
969 unsigned InReg = It->second;
1004 return (NodeMap.find(V) != NodeMap.end()) ||
1014 if (isa<ConstantSDNode>(N) || isa<ConstantFPSDNode>(
N)) {
1036 if (
const Constant *
C = dyn_cast<Constant>(V)) {
1045 if (isa<ConstantPointerNull>(
C)) {
1051 if (
const ConstantFP *CFP = dyn_cast<ConstantFP>(
C))
1058 visit(CE->getOpcode(), *CE);
1060 assert(N1.getNode() &&
"visit didn't populate the NodeMap!");
1064 if (isa<ConstantStruct>(
C) || isa<ConstantArray>(
C)) {
1073 for (
unsigned i = 0, e = Val->
getNumValues(); i != e; ++i)
1081 dyn_cast<ConstantDataSequential>(
C)) {
1083 for (
unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1087 for (
unsigned i = 0, e = Val->
getNumValues(); i != e; ++i)
1091 if (isa<ArrayType>(CDS->getType()))
1097 if (
C->getType()->isStructTy() ||
C->getType()->isArrayTy()) {
1098 assert((isa<ConstantAggregateZero>(
C) || isa<UndefValue>(
C)) &&
1099 "Unknown struct or array constant!");
1103 unsigned NumElts = ValueVTs.
size();
1107 for (
unsigned i = 0; i != NumElts; ++i) {
1108 EVT EltVT = ValueVTs[i];
1109 if (isa<UndefValue>(
C))
1130 for (
unsigned i = 0; i != NumElements; ++i)
1133 assert(isa<ConstantAggregateZero>(
C) &&
"Unknown vector constant!");
1142 Ops.
assign(NumElements, Op);
1151 if (
const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1160 if (
const Instruction *Inst = dyn_cast<Instruction>(V)) {
1171 void SelectionDAGBuilder::visitRet(
const ReturnInst &
I) {
1195 unsigned NumValues = ValueVTs.size();
1198 for (
unsigned i = 0; i != NumValues; ++i) {
1215 unsigned NumValues = ValueVTs.
size();
1233 for (
unsigned j = 0; j != NumValues; ++j) {
1234 EVT VT = ValueVTs[j];
1244 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1257 for (
unsigned i = 0; i < NumParts; ++i) {
1274 "LowerReturn didn't return a valid chain!");
1290 assert(!V->
use_empty() &&
"Unused value assigned virtual registers!");
1300 if (!isa<Instruction>(V) && !isa<Argument>(V))
return;
1315 if (
VI->getParent() == FromBB)
1324 if (isa<Argument>(V)) {
1347 void SelectionDAGBuilder::
1351 Weight = getEdgeWeight(Src, Dst);
1357 if (
const Instruction *I = dyn_cast<Instruction>(V))
1378 if (
const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1382 if (CurBB == SwitchBB ||
1386 if (
const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1388 }
else if (
const FCmpInst *
FC = dyn_cast<FCmpInst>(Cond)) {
1390 if (
TM.Options.NoNaNsFPMath)
1397 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1),
nullptr,
1398 TBB, FBB, CurBB, TWeight, FWeight);
1406 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1412 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1413 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1414 NewTrue = NewTrue / Scale;
1415 NewFalse = NewFalse / Scale;
1424 unsigned Opc, uint32_t TWeight,
1428 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1465 uint64_t NewTrueWeight = TWeight;
1466 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1470 NewTrueWeight, NewFalseWeight);
1472 NewTrueWeight = TWeight;
1473 NewFalseWeight = 2 * (uint64_t)FWeight;
1477 NewTrueWeight, NewFalseWeight);
1499 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1500 uint64_t NewFalseWeight = FWeight;
1504 NewTrueWeight, NewFalseWeight);
1506 NewTrueWeight = 2 * (uint64_t)TWeight;
1507 NewFalseWeight = FWeight;
1511 NewTrueWeight, NewFalseWeight);
1520 if (Cases.size() != 2)
return true;
1524 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1525 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1526 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1527 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1533 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1534 Cases[0].CC == Cases[1].CC &&
1535 isa<Constant>(Cases[0].CmpRHS) &&
1536 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1537 if (Cases[0].CC ==
ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1539 if (Cases[0].CC ==
ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1546 void SelectionDAGBuilder::visitBr(
const BranchInst &I) {
1587 if (
const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1592 BOp->getOpcode(), getEdgeWeight(BrMBB, Succ0MBB),
1593 getEdgeWeight(BrMBB, Succ1MBB));
1597 assert(
SwitchCases[0].ThisBB == BrMBB &&
"Unexpected lowering!");
1601 for (
unsigned i = 1, e =
SwitchCases.size(); i != e; ++i) {
1614 for (
unsigned i = 1, e =
SwitchCases.size(); i != e; ++i)
1623 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1652 assert(CB.CC ==
ISD::SETLE &&
"Can handle only LE ranges now");
1654 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->
getValue();
1655 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->
getValue();
1660 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(
true)) {
1672 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1675 if (CB.TrueBB != CB.FalseBB)
1676 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1680 if (CB.TrueBB == NextBlock(SwitchBB)) {
1702 assert(JT.Reg != -1U &&
"Should lower JT Header first!");
1716 JumpTableHeader &JTH,
1736 unsigned JumpTableReg =
1739 JumpTableReg, SwitchOp);
1740 JT.Reg = JumpTableReg;
1755 if (JT.MBB != NextBlock(SwitchBB))
1778 const Value *IRGuard = SPD.getGuard();
1790 unsigned GuardReg = SPD.getGuardReg();
1798 true,
false,
false,
Align);
1803 true,
false,
false,
Align);
1840 nullptr, 0,
false,
getCurSDLoc(),
false,
false).second;
1864 bool UsePtrType =
false;
1868 for (
unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1887 addSuccessorWithWeight(SwitchBB, B.Default);
1888 addSuccessorWithWeight(SwitchBB, MBB);
1895 if (MBB != NextBlock(SwitchBB))
1905 uint32_t BranchWeightToNext,
1915 if (PopCount == 1) {
1922 }
else if (PopCount == BB.Range) {
1942 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1944 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
1951 if (NextMBB != NextBlock(SwitchBB))
1958 void SelectionDAGBuilder::visitInvoke(
const InvokeInst &I) {
1967 if (isa<InlineAsm>(Callee))
1969 else if (Fn && Fn->isIntrinsic()) {
1970 switch (Fn->getIntrinsicID()) {
1973 case Intrinsic::donothing:
1976 case Intrinsic::experimental_patchpoint_void:
1977 case Intrinsic::experimental_patchpoint_i64:
1978 visitPatchpoint(&I, LandingPad);
1980 case Intrinsic::experimental_gc_statepoint:
1996 addSuccessorWithWeight(InvokeMBB, Return);
1997 addSuccessorWithWeight(InvokeMBB, LandingPad);
2005 void SelectionDAGBuilder::visitResume(
const ResumeInst &RI) {
2006 llvm_unreachable(
"SelectionDAGBuilder shouldn't visit resume instructions!");
2009 void SelectionDAGBuilder::visitLandingPad(
const LandingPadInst &LP) {
2011 "Call to landingpad not in landing pad!");
2027 assert(ValueVTs.
size() == 2 &&
"Only two-valued landingpads are supported");
2053 void SelectionDAGBuilder::sortAndRangeify(CaseClusterVector &Clusters) {
2055 for (
const CaseCluster &CC : Clusters)
2056 assert(CC.Low == CC.High &&
"Input clusters must be single-case");
2059 std::sort(Clusters.begin(), Clusters.end(),
2060 [](
const CaseCluster &a,
const CaseCluster &b) {
2061 return a.Low->getValue().slt(b.Low->getValue());
2065 const unsigned N = Clusters.size();
2066 unsigned DstIndex = 0;
2067 for (
unsigned SrcIndex = 0; SrcIndex <
N; ++SrcIndex) {
2068 CaseCluster &CC = Clusters[SrcIndex];
2072 if (DstIndex != 0 && Clusters[DstIndex - 1].MBB == Succ &&
2073 (CaseVal->
getValue() - Clusters[DstIndex - 1].High->getValue()) == 1) {
2076 Clusters[DstIndex - 1].High = CaseVal;
2077 Clusters[DstIndex - 1].Weight += CC.Weight;
2078 assert(Clusters[DstIndex - 1].Weight >= CC.Weight &&
"Weight overflow!");
2080 std::memmove(&Clusters[DstIndex++], &Clusters[SrcIndex],
2081 sizeof(Clusters[SrcIndex]));
2084 Clusters.resize(DstIndex);
2090 for (
unsigned i = 0, e =
JTCases.size(); i != e; ++i)
2091 if (
JTCases[i].first.HeaderBB == First)
2092 JTCases[i].first.HeaderBB = Last;
2095 for (
unsigned i = 0, e =
BitTestCases.size(); i != e; ++i)
2100 void SelectionDAGBuilder::visitIndirectBr(
const IndirectBrInst &I) {
2107 bool Inserted = Done.
insert(BB).second;
2112 addSuccessorWithWeight(IndirectBrMBB, Succ);
2120 void SelectionDAGBuilder::visitUnreachable(
const UnreachableInst &I) {
2125 void SelectionDAGBuilder::visitFSub(
const User &I) {
2139 void SelectionDAGBuilder::visitBinary(
const User &I,
unsigned OpCode) {
2149 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2150 nuw = OFBinOp->hasNoUnsignedWrap();
2151 nsw = OFBinOp->hasNoSignedWrap();
2154 dyn_cast<const PossiblyExactOperator>(&I))
2155 exact = ExactOp->isExact();
2156 if (
const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(&I))
2157 FMF = FPOp->getFastMathFlags();
2175 void SelectionDAGBuilder::visitShift(
const User &I,
unsigned Opcode) {
2185 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2189 if (ShiftSize > Op2Size)
2196 else if (ShiftSize >=
Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2211 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2212 nuw = OFBinOp->hasNoUnsignedWrap();
2213 nsw = OFBinOp->hasNoSignedWrap();
2216 dyn_cast<const PossiblyExactOperator>(&I))
2217 exact = ExactOp->isExact();
2228 void SelectionDAGBuilder::visitSDiv(
const User &I) {
2233 Flags.setExact(isa<PossiblyExactOperator>(&I) &&
2234 cast<PossiblyExactOperator>(&I)->isExact());
2239 void SelectionDAGBuilder::visitICmp(
const User &I) {
2241 if (
const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2242 predicate = IC->getPredicate();
2243 else if (
const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2254 void SelectionDAGBuilder::visitFCmp(
const User &I) {
2256 if (
const FCmpInst *
FC = dyn_cast<FCmpInst>(&I))
2257 predicate =
FC->getPredicate();
2263 if (
TM.Options.NoNaNsFPMath)
2270 void SelectionDAGBuilder::visitSelect(
const User &I) {
2274 unsigned NumValues = ValueVTs.
size();
2275 if (NumValues == 0)
return;
2281 auto BaseOps = {Cond};
2298 EVT VT = ValueVTs[0];
2308 cast<SelectInst>(&
I)->getCondition()->hasOneUse()) {
2316 for (
unsigned i = 0; i != NumValues; ++i) {
2319 Ops.push_back(
SDValue(RHSVal.getNode(), RHSVal.getResNo() + i));
2321 LHSVal.getNode()->getValueType(LHSVal.getResNo()+i),
2329 void SelectionDAGBuilder::visitTrunc(
const User &I) {
2337 void SelectionDAGBuilder::visitZExt(
const User &I) {
2346 void SelectionDAGBuilder::visitSExt(
const User &I) {
2355 void SelectionDAGBuilder::visitFPTrunc(
const User &I) {
2366 void SelectionDAGBuilder::visitFPExt(
const User &I) {
2374 void SelectionDAGBuilder::visitFPToUI(
const User &I) {
2382 void SelectionDAGBuilder::visitFPToSI(
const User &I) {
2390 void SelectionDAGBuilder::visitUIToFP(
const User &I) {
2398 void SelectionDAGBuilder::visitSIToFP(
const User &I) {
2406 void SelectionDAGBuilder::visitPtrToInt(
const User &I) {
2415 void SelectionDAGBuilder::visitIntToPtr(
const User &I) {
2424 void SelectionDAGBuilder::visitBitCast(
const User &I) {
2446 void SelectionDAGBuilder::visitAddrSpaceCast(
const User &I) {
2461 void SelectionDAGBuilder::visitInsertElement(
const User &I) {
2469 InVec, InVal, InIdx));
2472 void SelectionDAGBuilder::visitExtractElement(
const User &I) {
2486 unsigned Pos,
unsigned Size,
int Low) {
2487 for (
unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2488 if (Mask[i] >= 0 && Mask[i] != Low)
2493 void SelectionDAGBuilder::visitShuffleVector(
const User &I) {
2499 unsigned MaskNumElts = Mask.size();
2506 if (SrcNumElts == MaskNumElts) {
2513 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2517 if (SrcNumElts*2 == MaskNumElts) {
2537 unsigned NumConcat = MaskNumElts / SrcNumElts;
2554 for (
unsigned i = 0; i != MaskNumElts; ++i) {
2556 if (Idx >= (
int)SrcNumElts)
2557 Idx -= SrcNumElts - MaskNumElts;
2566 if (SrcNumElts > MaskNumElts) {
2570 int MinRange[2] = {
static_cast<int>(SrcNumElts),
2571 static_cast<int>(SrcNumElts)};
2572 int MaxRange[2] = {-1, -1};
2574 for (
unsigned i = 0; i != MaskNumElts; ++i) {
2580 if (Idx >= (
int)SrcNumElts) {
2584 if (Idx > MaxRange[Input])
2585 MaxRange[Input] = Idx;
2586 if (Idx < MinRange[Input])
2587 MinRange[Input] = Idx;
2592 int RangeUse[2] = { -1, -1 };
2595 for (
unsigned Input = 0; Input < 2; ++Input) {
2596 if (MinRange[Input] >= (
int)SrcNumElts && MaxRange[Input] < 0) {
2597 RangeUse[Input] = 0;
2598 StartIdx[Input] = 0;
2604 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2605 if (MaxRange[Input] - StartIdx[Input] < (
int)MaskNumElts &&
2606 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2607 RangeUse[Input] = 1;
2610 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2614 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
2616 for (
unsigned Input = 0; Input < 2; ++Input) {
2617 SDValue &Src = Input == 0 ? Src1 : Src2;
2618 if (RangeUse[Input] == 0)
2631 for (
unsigned i = 0; i != MaskNumElts; ++i) {
2634 if (Idx < (
int)SrcNumElts)
2637 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
2655 for (
unsigned i = 0; i != MaskNumElts; ++i) {
2662 SDValue &Src = Idx < (
int)SrcNumElts ? Src1 : Src2;
2663 if (Idx >= (
int)SrcNumElts) Idx -= SrcNumElts;
2675 void SelectionDAGBuilder::visitInsertValue(
const InsertValueInst &I) {
2680 bool IntoUndef = isa<UndefValue>(Op0);
2681 bool FromUndef = isa<UndefValue>(Op1);
2691 unsigned NumAggValues = AggValueVTs.
size();
2692 unsigned NumValValues = ValValueVTs.size();
2696 if (!NumAggValues) {
2704 for (; i != LinearIndex; ++i)
2705 Values[i] = IntoUndef ?
DAG.
getUNDEF(AggValueVTs[i]) :
2710 for (; i != LinearIndex + NumValValues; ++i)
2711 Values[i] = FromUndef ?
DAG.
getUNDEF(AggValueVTs[i]) :
2715 for (; i != NumAggValues; ++i)
2716 Values[i] = IntoUndef ?
DAG.
getUNDEF(AggValueVTs[i]) :
2727 bool OutOfUndef = isa<UndefValue>(Op0);
2735 unsigned NumValValues = ValValueVTs.
size();
2738 if (!NumValValues) {
2747 for (
unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2748 Values[i - LinearIndex] =
2757 void SelectionDAGBuilder::visitGetElementPtr(
const User &I) {
2769 cast<VectorType>(I.
getType())->getVectorNumElements() : 0;
2778 const Value *Idx = *OI;
2779 if (
StructType *StTy = dyn_cast<StructType>(Ty)) {
2780 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
2783 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
2788 Ty = StTy->getElementType(Field);
2790 Ty = cast<SequentialType>(Ty)->getElementType();
2794 APInt ElementSize(PtrSize, DL->getTypeAllocSize(Ty));
2799 if (!CI && isa<ConstantDataVector>(Idx) &&
2800 cast<ConstantDataVector>(Idx)->getSplatValue())
2801 CI = cast<ConstantInt>(cast<ConstantDataVector>(Idx)->getSplatValue());
2807 SDValue OffsVal = VectorWidth ?
2828 if (ElementSize != 1) {
2829 if (ElementSize.isPowerOf2()) {
2830 unsigned Amt = ElementSize.logBase2();
2849 void SelectionDAGBuilder::visitAlloca(
const AllocaInst &I) {
2859 uint64_t TySize = DL.getTypeAllocSize(Ty);
2861 std::max((
unsigned)DL.getPrefTypeAlignment(Ty), I.
getAlignment());
2866 if (AllocSize.getValueType() != IntPtr)
2876 unsigned StackAlign =
2878 if (Align <= StackAlign)
2884 AllocSize.getValueType(), AllocSize,
2889 AllocSize.getValueType(), AllocSize,
2902 void SelectionDAGBuilder::visitLoad(
const LoadInst &I) {
2904 return visitAtomicLoad(I);
2934 unsigned NumValues = ValueVTs.size();
2939 bool ConstantMemory =
false;
2947 ConstantMemory =
true;
2961 unsigned ChainI = 0;
2962 for (
unsigned i = 0; i != NumValues; ++i, ++ChainI) {
2970 assert(
PendingLoads.empty() &&
"PendingLoads must be serialized first");
2981 isNonTemporal, isInvariant, Alignment, AAInfo,
2988 if (!ConstantMemory) {
3001 void SelectionDAGBuilder::visitStore(
const StoreInst &I) {
3003 return visitAtomicStore(I);
3012 unsigned NumValues = ValueVTs.
size();
3033 unsigned ChainI = 0;
3034 for (
unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3047 isVolatile, isNonTemporal, Alignment, AAInfo);
3048 Chains[ChainI] = St;
3056 void SelectionDAGBuilder::visitMaskedStore(
const CallInst &I) {
3065 unsigned Alignment = (cast<ConstantInt>(I.
getArgOperand(2)))->getZExtValue();
3092 if (!Gep || Gep->getNumOperands() > 2)
3097 cast<Instruction>(ShuffleInst->
getOperand(0))->getOpcode() !=
3098 Instruction::InsertElement)
3101 Ptr = cast<InsertElementInst>(ShuffleInst->
getOperand(0))->getOperand(1);
3111 SDLoc sdl = ShuffleNode;
3121 Value *IndexVal = Gep->getOperand(1);
3125 if (
SExtInst* Sext = dyn_cast<SExtInst>(IndexVal)) {
3126 IndexVal = Sext->getOperand(0);
3135 void SelectionDAGBuilder::visitMaskedScatter(
const CallInst &I) {
3143 unsigned Alignment = (cast<ConstantInt>(I.
getArgOperand(2)))->getZExtValue();
3153 Value *BasePtr = Ptr;
3156 Value *MemOpBasePtr = UniformBase ? BasePtr :
nullptr;
3172 void SelectionDAGBuilder::visitMaskedLoad(
const CallInst &I) {
3183 unsigned Alignment = (cast<ConstantInt>(I.
getArgOperand(1)))->getZExtValue();
3202 Alignment, AAInfo,
Ranges);
3211 void SelectionDAGBuilder::visitMaskedGather(
const CallInst &I) {
3221 unsigned Alignment = (cast<ConstantInt>(I.
getArgOperand(1)))->getZExtValue();
3232 Value *BasePtr = Ptr;
3234 bool ConstantMemory =
false;
3240 ConstantMemory =
true;
3247 Alignment, AAInfo,
Ranges);
3253 SDValue Ops[] = { Root, Src0, Mask, Base, Index };
3258 if (!ConstantMemory)
3277 0, SuccessOrder, FailureOrder, Scope);
3285 void SelectionDAGBuilder::visitAtomicRMW(
const AtomicRMWInst &I) {
3322 void SelectionDAGBuilder::visitFence(
const FenceInst &I) {
3334 void SelectionDAGBuilder::visitAtomicLoad(
const LoadInst &I) {
3368 void SelectionDAGBuilder::visitAtomicStore(
const StoreInst &I) {
3396 void SelectionDAGBuilder::visitTargetIntrinsic(
const CallInst &I,
3397 unsigned Intrinsic) {
3413 TargetLowering::IntrinsicInfo Info;
3439 if (IsTgtIntrinsic) {
3442 VTs, Ops, Info.memVT,
3444 Info.align, Info.vol,
3445 Info.readMem, Info.writeMem, Info.size);
3446 }
else if (!HasChain) {
3527 SDValue TwoToFractionalPartOfX;
3639 if (LimitFloatPrecision <= 6) {
3654 }
else if (LimitFloatPrecision <= 12) {
3735 if (LimitFloatPrecision <= 6) {
3748 }
else if (LimitFloatPrecision <= 12) {
3830 if (LimitFloatPrecision <= 6) {
3845 }
else if (LimitFloatPrecision <= 12) {
3916 bool IsExp10 =
false;
3921 IsExp10 = LHSC->isExactlyValue(Ten);
3950 unsigned Val = RHSC->getSExtValue();
3951 if ((
int)Val < 0) Val = -Val;
3977 CurSquare, CurSquare);
3982 if (RHSC->getSExtValue() < 0)
4014 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
4062 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4069 "Expected inlined-at fields to agree");
4073 Op->
getReg(), Offset, Variable, Expr));
4086 #if defined(_MSC_VER) && defined(setjmp) && \
4087 !defined(setjmp_undefined_for_msvc)
4088 # pragma push_macro("setjmp")
4090 # define setjmp_undefined_for_msvc
4097 SelectionDAGBuilder::visitIntrinsicCall(
const CallInst &I,
unsigned Intrinsic) {
4103 switch (Intrinsic) {
4106 visitTargetIntrinsic(I, Intrinsic);
4108 case Intrinsic::vastart: visitVAStart(I);
return nullptr;
4109 case Intrinsic::vaend: visitVAEnd(I);
return nullptr;
4110 case Intrinsic::vacopy: visitVACopy(I);
return nullptr;
4111 case Intrinsic::returnaddress:
4116 case Intrinsic::frameaddress:
4121 case Intrinsic::read_register: {
4125 DAG.
getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4133 case Intrinsic::write_register: {
4138 DAG.
getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4143 case Intrinsic::setjmp:
4145 case Intrinsic::longjmp:
4147 case Intrinsic::memcpy: {
4155 "Unknown address space");
4159 unsigned Align = cast<ConstantInt>(I.
getArgOperand(3))->getZExtValue();
4162 bool isVol = cast<ConstantInt>(I.
getArgOperand(4))->getZExtValue();
4168 updateDAGForMaybeTailCall(MC);
4171 case Intrinsic::memset: {
4177 "Unknown address space");
4181 unsigned Align = cast<ConstantInt>(I.
getArgOperand(3))->getZExtValue();
4184 bool isVol = cast<ConstantInt>(I.
getArgOperand(4))->getZExtValue();
4188 updateDAGForMaybeTailCall(MS);
4191 case Intrinsic::memmove: {
4199 "Unknown address space");
4203 unsigned Align = cast<ConstantInt>(I.
getArgOperand(3))->getZExtValue();
4206 bool isVol = cast<ConstantInt>(I.
getArgOperand(4))->getZExtValue();
4211 updateDAGForMaybeTailCall(MM);
4214 case Intrinsic::dbg_declare: {
4219 assert(Variable &&
"Missing variable");
4221 DEBUG(
dbgs() <<
"Dropping debug info for " << DI <<
"\n");
4226 if (isa<UndefValue>(Address) ||
4228 DEBUG(
dbgs() <<
"Dropping debug info for " << DI <<
"\n");
4235 N = UnusedArgNodeMap[
Address];
4238 if (
const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4239 Address = BCI->getOperand(0);
4241 bool isParameter = Variable->getTag() == dwarf::DW_TAG_arg_variable ||
4246 if (isParameter && !AI) {
4251 Variable, Expression, FINode->
getIndex(), 0, dl, SDNodeOrder);
4255 EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0,
false,
4261 true, 0, dl, SDNodeOrder);
4264 DEBUG(
dbgs() <<
"Dropping debug info for " << DI <<
"\n");
4265 DEBUG(
dbgs() <<
"non-AllocaInst issue for Address: \n\t");
4273 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0,
false,
4277 if (
const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4278 if (AI->getParent() != DI.
getParent()) {
4283 0, dl, SDNodeOrder);
4289 DEBUG(
dbgs() <<
"Dropping debug info for " << DI <<
"\n");
4294 case Intrinsic::dbg_value: {
4306 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4314 if (!N.
getNode() && isa<Argument>(V))
4316 N = UnusedArgNodeMap[V];
4319 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4320 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, dl, Offset,
4323 IsIndirect, Offset, dl, SDNodeOrder);
4329 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4330 DanglingDebugInfoMap[V] = DDI;
4334 DEBUG(
dbgs() <<
"Dropping debug info for " << DI <<
"\n");
4339 if (
const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4340 V = BCI->getOperand(0);
4344 DEBUG(
dbgs() <<
"Dropping debug location info for:\n " << DI <<
"\n");
4345 DEBUG(
dbgs() <<
" Last seen at:\n " << *V <<
"\n");
4355 case Intrinsic::eh_typeid_for: {
4364 case Intrinsic::eh_return_i32:
4365 case Intrinsic::eh_return_i64:
4373 case Intrinsic::eh_unwind_init:
4376 case Intrinsic::eh_dwarf_cfa: {
4391 case Intrinsic::eh_sjlj_callsite: {
4394 assert(CI &&
"Non-constant call site value in eh.sjlj.callsite!");
4400 case Intrinsic::eh_sjlj_functioncontext: {
4409 case Intrinsic::eh_sjlj_setjmp: {
4419 case Intrinsic::eh_sjlj_longjmp: {
4425 case Intrinsic::masked_gather:
4426 visitMaskedGather(I);
4428 case Intrinsic::masked_load:
4431 case Intrinsic::masked_scatter:
4432 visitMaskedScatter(I);
4434 case Intrinsic::masked_store:
4435 visitMaskedStore(I);
4437 case Intrinsic::x86_mmx_pslli_w:
4438 case Intrinsic::x86_mmx_pslli_d:
4439 case Intrinsic::x86_mmx_pslli_q:
4440 case Intrinsic::x86_mmx_psrli_w:
4441 case Intrinsic::x86_mmx_psrli_d:
4442 case Intrinsic::x86_mmx_psrli_q:
4443 case Intrinsic::x86_mmx_psrai_w:
4444 case Intrinsic::x86_mmx_psrai_d: {
4446 if (isa<ConstantSDNode>(ShAmt)) {
4447 visitTargetIntrinsic(I, Intrinsic);
4450 unsigned NewIntrinsic = 0;
4452 switch (Intrinsic) {
4453 case Intrinsic::x86_mmx_pslli_w:
4454 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4456 case Intrinsic::x86_mmx_pslli_d:
4457 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4459 case Intrinsic::x86_mmx_pslli_q:
4460 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4462 case Intrinsic::x86_mmx_psrli_w:
4463 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4465 case Intrinsic::x86_mmx_psrli_d:
4466 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4468 case Intrinsic::x86_mmx_psrli_q:
4469 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4471 case Intrinsic::x86_mmx_psrai_w:
4472 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4474 case Intrinsic::x86_mmx_psrai_d:
4475 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4496 case Intrinsic::convertff:
4497 case Intrinsic::convertfsi:
4498 case Intrinsic::convertfui:
4499 case Intrinsic::convertsif:
4500 case Intrinsic::convertuif:
4501 case Intrinsic::convertss:
4502 case Intrinsic::convertsu:
4503 case Intrinsic::convertus:
4504 case Intrinsic::convertuu: {
4506 switch (Intrinsic) {
4508 case Intrinsic::convertff: Code =
ISD::CVT_FF;
break;
4509 case Intrinsic::convertfsi: Code =
ISD::CVT_FS;
break;
4510 case Intrinsic::convertfui: Code =
ISD::CVT_FU;
break;
4511 case Intrinsic::convertsif: Code =
ISD::CVT_SF;
break;
4512 case Intrinsic::convertuif: Code =
ISD::CVT_UF;
break;
4513 case Intrinsic::convertss: Code =
ISD::CVT_SS;
break;
4514 case Intrinsic::convertsu: Code =
ISD::CVT_SU;
break;
4515 case Intrinsic::convertus: Code =
ISD::CVT_US;
break;
4516 case Intrinsic::convertuu: Code =
ISD::CVT_UU;
break;
4529 case Intrinsic::powi:
4533 case Intrinsic::log:
4536 case Intrinsic::log2:
4539 case Intrinsic::log10:
4542 case Intrinsic::exp:
4545 case Intrinsic::exp2:
4548 case Intrinsic::pow:
4552 case Intrinsic::sqrt:
4553 case Intrinsic::fabs:
4554 case Intrinsic::sin:
4555 case Intrinsic::cos:
4556 case Intrinsic::floor:
4557 case Intrinsic::ceil:
4558 case Intrinsic::trunc:
4559 case Intrinsic::rint:
4560 case Intrinsic::nearbyint:
4561 case Intrinsic::round: {
4563 switch (Intrinsic) {
4565 case Intrinsic::sqrt: Opcode =
ISD::FSQRT;
break;
4566 case Intrinsic::fabs: Opcode =
ISD::FABS;
break;
4567 case Intrinsic::sin: Opcode =
ISD::FSIN;
break;
4568 case Intrinsic::cos: Opcode =
ISD::FCOS;
break;
4569 case Intrinsic::floor: Opcode =
ISD::FFLOOR;
break;
4570 case Intrinsic::ceil: Opcode =
ISD::FCEIL;
break;
4571 case Intrinsic::trunc: Opcode =
ISD::FTRUNC;
break;
4572 case Intrinsic::rint: Opcode =
ISD::FRINT;
break;
4574 case Intrinsic::round: Opcode =
ISD::FROUND;
break;
4594 case Intrinsic::copysign:
4600 case Intrinsic::fma:
4607 case Intrinsic::fmuladd: {
4629 case Intrinsic::convert_to_fp16:
4636 case Intrinsic::convert_from_fp16:
4642 case Intrinsic::pcmarker: {
4647 case Intrinsic::readcyclecounter: {
4655 case Intrinsic::bswap:
4660 case Intrinsic::cttz: {
4668 case Intrinsic::ctlz: {
4676 case Intrinsic::ctpop: {
4682 case Intrinsic::stacksave: {
4691 case Intrinsic::stackrestore: {
4696 case Intrinsic::stackprotector: {
4708 if (
const Operator *BC = dyn_cast<Operator>(Ptr))
4709 if (BC->getOpcode() == Instruction::BitCast)
4710 GV = dyn_cast<GlobalVariable>(BC->getOperand(0));
4753 case Intrinsic::objectsize: {
4757 assert(CI &&
"Non-constant type in __builtin_object_size?");
4770 case Intrinsic::annotation:
4771 case Intrinsic::ptr_annotation:
4775 case Intrinsic::assume:
4776 case Intrinsic::var_annotation:
4780 case Intrinsic::init_trampoline: {
4796 case Intrinsic::adjust_trampoline: {
4802 case Intrinsic::gcroot:
4811 case Intrinsic::gcread:
4812 case Intrinsic::gcwrite:
4814 case Intrinsic::flt_rounds:
4818 case Intrinsic::expect: {
4824 case Intrinsic::debugtrap:
4825 case Intrinsic::trap: {
4830 if (TrapFuncName.
empty()) {
4839 CLI.setDebugLoc(sdl).setChain(
getRoot()).setCallee(
4843 std::move(Args), 0);
4845 std::pair<SDValue, SDValue> Result = TLI.
LowerCallTo(CLI);
4850 case Intrinsic::uadd_with_overflow:
4851 case Intrinsic::sadd_with_overflow:
4852 case Intrinsic::usub_with_overflow:
4853 case Intrinsic::ssub_with_overflow:
4854 case Intrinsic::umul_with_overflow:
4855 case Intrinsic::smul_with_overflow: {
4857 switch (Intrinsic) {
4859 case Intrinsic::uadd_with_overflow: Op =
ISD::UADDO;
break;
4860 case Intrinsic::sadd_with_overflow: Op =
ISD::SADDO;
break;
4861 case Intrinsic::usub_with_overflow: Op =
ISD::USUBO;
break;
4862 case Intrinsic::ssub_with_overflow: Op =
ISD::SSUBO;
break;
4863 case Intrinsic::umul_with_overflow: Op =
ISD::UMULO;
break;
4864 case Intrinsic::smul_with_overflow: Op =
ISD::SMULO;
break;
4875 unsigned rw = cast<ConstantInt>(I.
getArgOperand(1))->getZExtValue();
4891 case Intrinsic::lifetime_start:
4892 case Intrinsic::lifetime_end: {
4893 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
4902 E = Allocas.
end(); Object != E; ++Object) {
4903 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
4906 if (!LifetimeObject)
4915 int FI = SI->second;
4928 case Intrinsic::invariant_start:
4932 case Intrinsic::invariant_end:
4935 case Intrinsic::stackprotectorcheck: {
4947 case Intrinsic::clear_cache:
4949 case Intrinsic::eh_actions:
4952 case Intrinsic::donothing:
4955 case Intrinsic::experimental_stackmap: {
4959 case Intrinsic::experimental_patchpoint_void:
4960 case Intrinsic::experimental_patchpoint_i64: {
4961 visitPatchpoint(&I);
4964 case Intrinsic::experimental_gc_statepoint: {
4968 case Intrinsic::experimental_gc_result_int:
4969 case Intrinsic::experimental_gc_result_float:
4970 case Intrinsic::experimental_gc_result_ptr:
4971 case Intrinsic::experimental_gc_result: {
4975 case Intrinsic::experimental_gc_relocate: {
4979 case Intrinsic::instrprof_increment:
4982 case Intrinsic::localescape: {
4990 if (isa<ConstantPointerNull>(Arg))
4994 "can only escape static allocas");
5001 .addSym(FrameAllocSym)
5008 case Intrinsic::localrecover: {
5016 unsigned IdxVal =
unsigned(Idx->getLimitedValue(INT_MAX));
5035 case Intrinsic::eh_begincatch:
5036 case Intrinsic::eh_endcatch:
5038 case Intrinsic::eh_exceptioncode: {
5040 assert(Reg &&
"cannot get exception code on this platform");
5054 std::pair<SDValue, SDValue>
5068 if (CallSiteIndex) {
5084 std::pair<SDValue, SDValue> Result = TLI.
LowerCallTo(CLI);
5086 assert((CLI.
IsTailCall || Result.second.getNode()) &&
5087 "Non-null chain expected with non-tail call!");
5088 assert((Result.second.getNode() || !Result.first.getNode()) &&
5089 "Null value expected with tail call!");
5091 if (!Result.second.getNode()) {
5098 PendingExports.clear();
5110 MMI.
addInvoke(LandingPad, BeginLabel, EndLabel);
5121 Type *RetTy = FTy->getReturnType();
5129 const Value *V = *i;
5140 Args.push_back(Entry);
5144 if (Entry.
isSRet && isa<Instruction>(V))
5155 .
setCallee(RetTy, FTy, Callee, std::move(Args), CS)
5157 std::pair<SDValue,SDValue> Result = lowerInvokable(CLI, LandingPad);
5159 if (Result.first.getNode())
5167 if (
const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5168 if (IC->isEquality())
5169 if (
const Constant *
C = dyn_cast<Constant>(IC->getOperand(1)))
5170 if (
C->isNullValue())
5184 if (
const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5190 const_cast<Constant *>(LoadInput), *Builder.
DL))
5197 bool ConstantMemory =
false;
5202 ConstantMemory =
true;
5215 if (!ConstantMemory)
5222 void SelectionDAGBuilder::processIntegerCallValue(
const Instruction &I,
5237 bool SelectionDAGBuilder::visitMemCmpCall(
const CallInst &I) {
5258 std::pair<SDValue, SDValue> Res =
5263 if (Res.first.getNode()) {
5264 processIntegerCallValue(I, Res.first,
true);
5272 bool ActuallyDoIt =
true;
5279 ActuallyDoIt =
false;
5319 ActuallyDoIt =
false;
5328 processIntegerCallValue(I, Res,
false);
5340 bool SelectionDAGBuilder::visitMemChrCall(
const CallInst &I) {
5355 std::pair<SDValue, SDValue> Res =
5359 if (Res.first.getNode()) {
5371 bool SelectionDAGBuilder::visitStrCpyCall(
const CallInst &I,
bool isStpcpy) {
5378 !Arg1->getType()->isPointerTy() ||
5383 std::pair<SDValue, SDValue> Res =
5388 if (Res.first.getNode()) {
5400 bool SelectionDAGBuilder::visitStrCmpCall(
const CallInst &I) {
5407 !Arg1->getType()->isPointerTy() ||
5412 std::pair<SDValue, SDValue> Res =
5417 if (Res.first.getNode()) {
5418 processIntegerCallValue(I, Res.first,
true);
5429 bool SelectionDAGBuilder::visitStrLenCall(
const CallInst &I) {
5439 std::pair<SDValue, SDValue> Res =
5442 if (Res.first.getNode()) {
5443 processIntegerCallValue(I, Res.first,
false);
5454 bool SelectionDAGBuilder::visitStrNLenCall(
const CallInst &I) {
5461 !Arg1->getType()->isIntegerTy() ||
5466 std::pair<SDValue, SDValue> Res =
5470 if (Res.first.getNode()) {
5471 processIntegerCallValue(I, Res.first,
false);
5482 bool SelectionDAGBuilder::visitUnaryFloatCall(
const CallInst &I,
5499 bool SelectionDAGBuilder::visitBinaryFloatCall(
const CallInst &I,
5516 void SelectionDAGBuilder::visitCall(
const CallInst &I) {
5526 const char *RenameFn =
nullptr;
5530 if (
unsigned IID = II->getIntrinsicID(F)) {
5531 RenameFn = visitIntrinsicCall(I, IID);
5537 RenameFn = visitIntrinsicCall(I, IID);
5551 case LibFunc::copysign:
5552 case LibFunc::copysignf:
5553 case LibFunc::copysignl:
5567 case LibFunc::fabsf:
5568 case LibFunc::fabsl:
5573 case LibFunc::fminf:
5574 case LibFunc::fminl:
5579 case LibFunc::fmaxf:
5580 case LibFunc::fmaxl:
5597 case LibFunc::sqrtf:
5598 case LibFunc::sqrtl:
5599 case LibFunc::sqrt_finite:
5600 case LibFunc::sqrtf_finite:
5601 case LibFunc::sqrtl_finite:
5605 case LibFunc::floor:
5606 case LibFunc::floorf:
5607 case LibFunc::floorl:
5611 case LibFunc::nearbyint:
5612 case LibFunc::nearbyintf:
5613 case LibFunc::nearbyintl:
5618 case LibFunc::ceilf:
5619 case LibFunc::ceill:
5624 case LibFunc::rintf:
5625 case LibFunc::rintl:
5629 case LibFunc::round:
5630 case LibFunc::roundf:
5631 case LibFunc::roundl:
5635 case LibFunc::trunc:
5636 case LibFunc::truncf:
5637 case LibFunc::truncl:
5642 case LibFunc::log2f:
5643 case LibFunc::log2l:
5648 case LibFunc::exp2f:
5649 case LibFunc::exp2l:
5653 case LibFunc::memcmp:
5654 if (visitMemCmpCall(I))
5657 case LibFunc::memchr:
5658 if (visitMemChrCall(I))
5661 case LibFunc::strcpy:
5662 if (visitStrCpyCall(I,
false))
5665 case LibFunc::stpcpy:
5666 if (visitStrCpyCall(I,
true))
5669 case LibFunc::strcmp:
5670 if (visitStrCmpCall(I))
5673 case LibFunc::strlen:
5674 if (visitStrLenCall(I))
5677 case LibFunc::strnlen:
5678 if (visitStrNLenCall(I))
5724 if (isa<BasicBlock>(CallOperandVal))
5727 llvm::Type *OpTy = CallOperandVal->getType();
5740 if (
StructType *STy = dyn_cast<StructType>(OpTy))
5741 if (STy->getNumElements() == 1)
5742 OpTy = STy->getElementType(0);
5780 SDISelAsmOperandInfo &OpInfo) {
5788 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
5790 OpInfo.ConstraintCode,
5791 OpInfo.ConstraintVT);
5793 unsigned NumRegs = 1;
5799 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5803 MVT RegVT = *PhysReg.second->vt_begin();
5804 if (RegVT.
getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
5806 RegVT, OpInfo.CallOperand);
5807 OpInfo.ConstraintVT = RegVT;
5808 }
else if (RegVT.
isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5815 RegVT, OpInfo.CallOperand);
5816 OpInfo.ConstraintVT = RegVT;
5824 EVT ValueVT = OpInfo.ConstraintVT;
5828 if (
unsigned AssignedReg = PhysReg.first) {
5844 for (; *I != AssignedReg; ++
I)
5845 assert(I != RC->
end() &&
"Didn't find reg!");
5849 for (; NumRegs; --NumRegs, ++
I) {
5850 assert(I != RC->
end() &&
"Ran out of registers to allocate!");
5855 OpInfo.AssignedRegs =
RegsForValue(Regs, RegVT, ValueVT);
5868 for (; NumRegs; --NumRegs)
5871 OpInfo.AssignedRegs =
RegsForValue(Regs, RegVT, ValueVT);
5884 SDISelAsmOperandInfoVector ConstraintOperands;
5890 bool hasMemory =
false;
5894 for (
unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5895 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
5896 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5901 switch (OpInfo.Type) {
5904 if (OpInfo.isIndirect) {
5905 OpInfo.CallOperandVal =
const_cast<Value *
>(CS.
getArgument(ArgNo++));
5914 STy->getElementType(ResNo));
5916 assert(ResNo == 0 &&
"Asm only has one result!");
5922 OpInfo.CallOperandVal =
const_cast<Value *
>(CS.
getArgument(ArgNo++));
5931 if (OpInfo.CallOperandVal) {
5932 if (
const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5935 OpInfo.CallOperand =
getValue(OpInfo.CallOperandVal);
5942 OpInfo.ConstraintVT = OpVT;
5945 if (OpInfo.isIndirect)
5948 for (
unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
5970 for (
unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5971 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5977 if (OpInfo.hasMatchingInput()) {
5978 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5980 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5982 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
5984 OpInfo.ConstraintVT);
5985 std::pair<unsigned, const TargetRegisterClass *> InputRC =
5987 Input.ConstraintVT);
5988 if ((OpInfo.ConstraintVT.isInteger() !=
5989 Input.ConstraintVT.isInteger()) ||
5990 (MatchRC.second != InputRC.second)) {
5992 " with a matching output constraint of"
5993 " incompatible type!");
5995 Input.ConstraintVT = OpInfo.ConstraintVT;
6009 !OpInfo.isIndirect) {
6010 assert((OpInfo.isMultipleAlternative ||
6012 "Can only indirectify direct input operands!");
6024 const Value *OpVal = OpInfo.CallOperandVal;
6025 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6026 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6041 OpInfo.CallOperand, StackSlot,
6044 OpInfo.CallOperand = StackSlot;
6048 OpInfo.CallOperandVal =
nullptr;
6051 OpInfo.isIndirect =
true;
6062 for (
unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6063 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6072 std::vector<SDValue> AsmNodeOperands;
6073 AsmNodeOperands.push_back(
SDValue());
6085 unsigned ExtraInfo = 0;
6094 for (
unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6123 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6125 for (
unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6126 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6128 switch (OpInfo.Type) {
6133 assert(OpInfo.isIndirect &&
"Memory output must be indirect operand");
6135 unsigned ConstraintID =
6138 "Failed to convert memory constraint code to constraint id.");
6145 AsmNodeOperands.push_back(OpInfo.CallOperand);
6153 if (OpInfo.AssignedRegs.Regs.empty()) {
6156 "couldn't allocate output register for constraint '" +
6157 Twine(OpInfo.ConstraintCode) +
"'");
6163 if (OpInfo.isIndirect) {
6164 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6165 OpInfo.CallOperandVal));
6170 RetValRegs.
append(OpInfo.AssignedRegs);
6176 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6183 SDValue InOperandVal = OpInfo.CallOperand;
6185 if (OpInfo.isMatchingInputConstraint()) {
6188 unsigned OperandNo = OpInfo.getMatchedOperand();
6193 for (; OperandNo; --OperandNo) {
6196 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6204 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6208 if (OpInfo.isIndirect) {
6212 " don't know how to handle tied "
6213 "indirect register inputs");
6219 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6220 MatchedRegs.
RegVTs.push_back(RegVT);
6229 "inline asm error: This value"
6230 " type register class is not natively supported!");
6239 true, OpInfo.getMatchedOperand(), dl,
6240 DAG, AsmNodeOperands);
6246 "Unexpected number of operands");
6251 OpInfo.getMatchedOperand());
6254 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6264 std::vector<SDValue> Ops;
6270 "invalid operand for inline asm constraint '" +
6271 Twine(OpInfo.ConstraintCode) +
"'");
6276 unsigned ResOpType =
6280 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6285 assert(OpInfo.isIndirect &&
"Operand must be indirect to be a mem!");
6288 "Memory operands expect pointer values");
6290 unsigned ConstraintID =
6293 "Failed to convert memory constraint code to constraint id.");
6301 AsmNodeOperands.push_back(InOperandVal);
6307 "Unknown constraint type!");
6310 if (OpInfo.isIndirect) {
6313 "Don't know how to handle indirect register inputs yet "
6314 "for constraint '" +
6315 Twine(OpInfo.ConstraintCode) +
"'");
6320 if (OpInfo.AssignedRegs.Regs.empty()) {
6323 "couldn't allocate input reg for constraint '" +
6324 Twine(OpInfo.ConstraintCode) +
"'");
6330 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal,
DAG, dl,
6334 dl,
DAG, AsmNodeOperands);
6340 if (!OpInfo.AssignedRegs.Regs.empty())
6351 if (Flag.
getNode()) AsmNodeOperands.push_back(Flag);
6384 assert(ResultType == Val.
getValueType() &&
"Asm result value mismatch!");
6389 if (!IA->
hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6393 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6397 for (
unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6399 const Value *Ptr = IndirectStoresToEmit[i].second;
6402 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6407 for (
unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6409 StoresToEmit[i].first,
6416 if (!OutChains.
empty())
6422 void SelectionDAGBuilder::visitVAStart(
const CallInst &I) {
6429 void SelectionDAGBuilder::visitVAArg(
const VAArgInst &I) {
6440 void SelectionDAGBuilder::visitVAEnd(
const CallInst &I) {
6447 void SelectionDAGBuilder::visitVACopy(
const CallInst &I) {
6463 std::pair<SDValue, SDValue>
6465 unsigned NumArgs,
SDValue Callee,
6468 bool IsPatchPoint) {
6470 Args.reserve(NumArgs);
6474 for (
unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6475 ArgI != ArgE; ++ArgI) {
6476 const Value *V = CS->getOperand(ArgI);
6483 Entry.setAttributes(&CS, AttrI);
6484 Args.push_back(Entry);
6490 .setDiscardResult(CS->use_empty()).setIsPatchPoint(IsPatchPoint);
6492 return lowerInvokable(CLI, LandingPad);
6515 for (
unsigned i = StartIdx, e = CS.
arg_size(); i != e; ++i) {
6532 void SelectionDAGBuilder::visitStackmap(
const CallInst &CI) {
6536 assert(CI.
getType()->
isVoidTy() &&
"Stackmap cannot return a value.");
6538 SDValue Chain, InFlag, Callee, NullPtr;
6561 cast<ConstantSDNode>(IDVal)->getZExtValue(),
DL,
MVT::i64));
6564 cast<ConstantSDNode>(NBytesVal)->getZExtValue(),
DL,
6581 InFlag = Chain.getValue(1);
6611 if (
auto* ConstCallee = dyn_cast<ConstantSDNode>(Callee))
6614 else if (
auto* SymbolicCallee = dyn_cast<GlobalAddressSDNode>(Callee))
6616 SDLoc(SymbolicCallee),
6617 SymbolicCallee->getValueType(0));
6621 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
6626 assert(CS.
arg_size() >= NumMetaOpers + NumArgs &&
6627 "Not enough arguments provided to the patchpoint intrinsic");
6630 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
6633 std::pair<SDValue, SDValue> Result =
6637 SDNode *CallEnd = Result.second.getNode();
6644 "Expected a callseq node.");
6654 cast<ConstantSDNode>(IDVal)->getZExtValue(), dl,
MVT::i64));
6657 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), dl,
6666 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
6667 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
6676 for (
unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
6681 Ops.
append(Call->op_begin() + 2, e);
6701 if (IsAnyRegCC && HasDef) {
6706 assert(ValueVTs.
size() == 1 &&
"Expected only one return value type.");
6731 if (IsAnyRegCC && HasDef) {
6762 std::pair<SDValue, SDValue>
6780 int DemoteStackIdx = -100;
6781 if (!CanLowerReturn) {
6785 uint64_t TySize = DL.getTypeAllocSize(CLI.
RetTy);
6786 unsigned Align = DL.getPrefTypeAlignment(CLI.
RetTy);
6793 Entry.
Node = DemoteStackSlot;
6794 Entry.
Ty = StackSlotPtrType;
6810 for (
unsigned I = 0, E = RetTys.
size(); I != E; ++
I) {
6814 for (
unsigned i = 0; i != NumRegs; ++i) {
6816 MyFlags.
VT = RegisterVT;
6834 for (
unsigned i = 0, e = Args.size(); i != e; ++i) {
6837 Type *FinalType = Args[i].Ty;
6838 if (Args[i].isByVal)
6839 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
6842 for (
unsigned Value = 0, NumValues = ValueVTs.
size(); Value != NumValues;
6844 EVT VT = ValueVTs[Value];
6847 Args[i].
Node.getResNo() + Value);
6849 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
6855 if (Args[i].isInReg)
6859 if (Args[i].isByVal)
6861 if (Args[i].isInAlloca) {
6862 Flags.setInAlloca();
6870 if (Args[i].isByVal || Args[i].isInAlloca) {
6873 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
6876 unsigned FrameAlign;
6877 if (Args[i].Alignment)
6878 FrameAlign = Args[i].Alignment;
6881 Flags.setByValAlign(FrameAlign);
6886 Flags.setInConsecutiveRegs();
6887 Flags.setOrigAlign(OriginalAlignment);
6896 else if (Args[i].isZExt)
6901 assert(CLI.
RetTy == Args[i].Ty && RetTys.
size() == NumValues &&
6902 "unexpected use of 'returned'");
6916 Flags.setReturned();
6922 for (
unsigned j = 0; j != NumParts; ++j) {
6926 i, j*Parts[j].getValueType().getStoreSize());
6927 if (NumParts > 1 && j == 0)
6930 MyFlags.Flags.setOrigAlign(1);
6933 CLI.
OutVals.push_back(Parts[j]);
6936 if (NeedsRegBlock && Value == NumValues - 1)
6937 CLI.
Outs[CLI.
Outs.
size() - 1].Flags.setInConsecutiveRegsLast();
6946 "LowerCall didn't return a valid chain!");
6948 "LowerCall emitted a return value for a tail call!");
6950 "LowerCall didn't emit the correct number of values!");
6961 DEBUG(
for (
unsigned i = 0, e = CLI.
Ins.
size(); i != e; ++i) {
6962 assert(InVals[i].getNode() &&
6963 "LowerCall emitted a null value!");
6964 assert(
EVT(CLI.
Ins[i].VT) == InVals[i].getValueType() &&
6965 "LowerCall emitted a value with the wrong type!");
6969 if (!CanLowerReturn) {
6976 assert(PVTs.
size() == 1 &&
"Pointers should fit in one register");
6977 EVT PtrVT = PVTs[0];
6979 unsigned NumValues = RetTys.
size();
6980 ReturnValues.resize(NumValues);
6983 for (
unsigned i = 0; i < NumValues; ++i) {
6988 RetTys[i], CLI.
DL, CLI.
Chain, Add,
6991 ReturnValues[i] = L;
7004 unsigned CurReg = 0;
7005 for (
unsigned I = 0, E = RetTys.
size(); I != E; ++
I) {
7011 NumRegs, RegisterVT, VT,
nullptr,
7019 if (ReturnValues.empty())
7025 return std::make_pair(Res, CLI.
Chain);
7045 "Copy from a reg to the same reg!");
7057 RFV.getCopyToRegs(Op,
DAG,
getCurSDLoc(), Chain,
nullptr, V, ExtendType);
7058 PendingExports.push_back(Chain);
7074 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
7080 void SelectionDAGISel::LowerArguments(
const Function &F) {
7105 I != E; ++
I, ++Idx) {
7109 unsigned PartBase = 0;
7112 FinalType = cast<PointerType>(FinalType)->getElementType();
7115 for (
unsigned Value = 0, NumValues = ValueVTs.
size();
7116 Value != NumValues; ++Value) {
7117 EVT VT = ValueVTs[Value];
7147 unsigned FrameAlign;
7162 for (
unsigned i = 0; i != NumRegs; ++i) {
7163 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7165 if (NumRegs > 1 && i == 0)
7169 MyFlags.Flags.setOrigAlign(1);
7172 if (NeedsRegBlock && Value == NumValues - 1)
7173 Ins[Ins.
size() - 1].Flags.setInConsecutiveRegsLast();
7185 "LowerFormalArguments didn't return a valid chain!");
7186 assert(InVals.
size() == Ins.
size() &&
7187 "LowerFormalArguments didn't emit the correct number of values!");
7189 for (
unsigned i = 0, e = Ins.
size(); i != e; ++i) {
7190 assert(InVals[i].getNode() &&
7191 "LowerFormalArguments emitted a null value!");
7192 assert(
EVT(Ins[i].VT) == InVals[i].getValueType() &&
7193 "LowerFormalArguments emitted a value with the wrong type!");
7198 DAG.setRoot(NewRoot);
7209 MVT VT = ValueVTs[0].getSimpleVT();
7213 RegVT, VT,
nullptr, AssertOp);
7221 DAG.setRoot(NewRoot);
7233 unsigned NumValues = ValueVTs.
size();
7242 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7246 for (
unsigned Val = 0; Val != NumValues; ++Val) {
7247 EVT VT = ValueVTs[Val];
7259 NumParts, PartVT, VT,
7260 nullptr, AssertOp));
7267 if (ArgValues.
empty())
7272 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7283 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7306 assert(i == InVals.
size() &&
"Argument register count mismatch!");
7320 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(
const BasicBlock *LLVMBB) {
7329 if (!isa<PHINode>(SuccBB->
begin()))
continue;
7334 if (!SuccsHandled.
insert(SuccMBB).second)
7354 if (
const Constant *
C = dyn_cast<Constant>(PHIOp)) {
7367 assert(isa<AllocaInst>(PHIOp) &&
7369 "Didn't codegen value into a register!??");
7380 for (
unsigned vti = 0, vte = ValueVTs.
size(); vti != vte; ++vti) {
7381 EVT VT = ValueVTs[vti];
7383 for (
unsigned i = 0, e = NumRegisters; i != e; ++i)
7385 Reg += NumRegisters;
7390 ConstantsOut.clear();
7396 SelectionDAGBuilder::StackProtectorDescriptor::
7406 MF->
insert(++BBI, SuccMBB);
7410 SuccMBB, BranchProbabilityInfo::getBranchWeightStackProtector(IsLikely));
7426 void SelectionDAGBuilder::updateDAGForMaybeTailCall(
SDValue MaybeTC) {
7428 if (MaybeTC.
getNode() !=
nullptr)
7429 DAG.setRoot(MaybeTC);
7434 bool SelectionDAGBuilder::isDense(
const CaseClusterVector &Clusters,
7435 unsigned *TotalCases,
unsigned First,
7437 assert(Last >= First);
7438 assert(TotalCases[Last] >= TotalCases[First]);
7440 APInt LowCase = Clusters[First].Low->getValue();
7441 APInt HighCase = Clusters[Last].High->getValue();
7448 uint64_t Diff = (HighCase - LowCase).getLimitedValue((UINT64_MAX - 1) / 100);
7449 uint64_t Range = Diff + 1;
7452 TotalCases[Last] - (First == 0 ? 0 : TotalCases[First - 1]);
7454 assert(NumCases < UINT64_MAX / 100);
7455 assert(Range >= NumCases);
7457 return NumCases * 100 >= Range * MinJumpTableDensity;
7465 bool SelectionDAGBuilder::buildJumpTable(CaseClusterVector &Clusters,
7466 unsigned First,
unsigned Last,
7469 CaseCluster &JTCluster) {
7470 assert(First <= Last);
7472 uint32_t Weight = 0;
7473 unsigned NumCmps = 0;
7474 std::vector<MachineBasicBlock*> Table;
7476 for (
unsigned I = First; I <= Last; ++
I) {
7477 assert(Clusters[I].
Kind == CC_Range);
7478 Weight += Clusters[
I].Weight;
7479 assert(Weight >= Clusters[I].Weight &&
"Weight overflow!");
7480 APInt Low = Clusters[
I].Low->getValue();
7481 APInt High = Clusters[
I].High->getValue();
7482 NumCmps += (Low == High) ? 1 : 2;
7485 APInt PreviousHigh = Clusters[I - 1].High->getValue();
7486 assert(PreviousHigh.
slt(Low));
7487 uint64_t Gap = (Low - PreviousHigh).getLimitedValue() - 1;
7488 for (uint64_t J = 0; J < Gap; J++)
7489 Table.push_back(DefaultMBB);
7491 uint64_t ClusterSize = (High - Low).getLimitedValue() + 1;
7492 for (uint64_t J = 0; J < ClusterSize; ++J)
7493 Table.push_back(Clusters[I].MBB);
7494 JTWeights[Clusters[
I].MBB] += Clusters[
I].Weight;
7497 unsigned NumDests = JTWeights.
size();
7498 if (isSuitableForBitTests(NumDests, NumCmps,
7499 Clusters[First].Low->getValue(),
7500 Clusters[Last].High->getValue())) {
7514 if (Done.
count(Succ))
7516 addSuccessorWithWeight(JumpTableMBB, Succ, JTWeights[Succ]);
7522 ->createJumpTableIndex(Table);
7526 JumpTableHeader JTH(Clusters[First].Low->getValue(),
7529 JTCases.emplace_back(std::move(JTH), std::move(
JT));
7531 JTCluster = CaseCluster::jumpTable(Clusters[First].Low, Clusters[Last].High,
7536 void SelectionDAGBuilder::findJumpTables(CaseClusterVector &Clusters,
7541 assert(!Clusters.empty());
7542 for (CaseCluster &
C : Clusters)
7543 assert(
C.Kind == CC_Range);
7544 for (
unsigned i = 1, e = Clusters.size(); i < e; ++i)
7545 assert(Clusters[i - 1].High->getValue().
slt(Clusters[i].Low->getValue()));
7552 const int64_t N = Clusters.size();
7558 for (
unsigned i = 0; i <
N; ++i) {
7559 APInt Hi = Clusters[i].High->getValue();
7560 APInt Lo = Clusters[i].Low->getValue();
7561 TotalCases[i] = (Hi -
Lo).getLimitedValue() + 1;
7563 TotalCases[i] += TotalCases[i - 1];
7566 if (N >= MinJumpTableSize && isDense(Clusters, &TotalCases[0], 0, N - 1)) {
7568 CaseCluster JTCluster;
7569 if (buildJumpTable(Clusters, 0, N - 1, SI, DefaultMBB, JTCluster)) {
7570 Clusters[0] = JTCluster;
7595 MinPartitions[N - 1] = 1;
7596 LastElement[N - 1] = N - 1;
7597 assert(MinJumpTableSize > 1);
7598 NumTables[N - 1] = 0;
7601 for (int64_t i = N - 2; i >= 0; i--) {
7604 MinPartitions[i] = MinPartitions[i + 1] + 1;
7606 NumTables[i] = NumTables[i + 1];
7609 for (int64_t j = N - 1; j > i; j--) {
7611 if (isDense(Clusters, &TotalCases[0], i, j)) {
7612 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7613 bool IsTable = j - i + 1 >= MinJumpTableSize;
7614 unsigned Tables = IsTable + (j == N - 1 ? 0 : NumTables[j + 1]);
7618 if (NumPartitions < MinPartitions[i] ||
7619 (NumPartitions == MinPartitions[i] && Tables > NumTables[i])) {
7620 MinPartitions[i] = NumPartitions;
7622 NumTables[i] = Tables;
7629 unsigned DstIndex = 0;
7630 for (
unsigned First = 0, Last; First <
N; First = Last + 1) {
7631 Last = LastElement[First];
7632 assert(Last >= First);
7633 assert(DstIndex <= First);
7634 unsigned NumClusters = Last - First + 1;
7636 CaseCluster JTCluster;
7637 if (NumClusters >= MinJumpTableSize &&
7638 buildJumpTable(Clusters, First, Last, SI, DefaultMBB, JTCluster)) {
7639 Clusters[DstIndex++] = JTCluster;
7641 for (
unsigned I = First; I <= Last; ++
I)
7642 std::memmove(&Clusters[DstIndex++], &Clusters[I],
sizeof(Clusters[I]));
7645 Clusters.resize(DstIndex);
7648 bool SelectionDAGBuilder::rangeFitsInWord(
const APInt &Low,
const APInt &High) {
7650 uint64_t BW = DAG.getDataLayout().getPointerSizeInBits();
7651 uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
7655 bool SelectionDAGBuilder::isSuitableForBitTests(
unsigned NumDests,
7658 const APInt &High) {
7666 if (!rangeFitsInWord(Low, High))
7673 return (NumDests == 1 && NumCmps >= 3) ||
7674 (NumDests == 2 && NumCmps >= 5) ||
7675 (NumDests == 3 && NumCmps >= 6);
7678 bool SelectionDAGBuilder::buildBitTests(CaseClusterVector &Clusters,
7679 unsigned First,
unsigned Last,
7681 CaseCluster &BTCluster) {
7682 assert(First <= Last);
7687 unsigned NumCmps = 0;
7688 for (int64_t I = First; I <= Last; ++
I) {
7689 assert(Clusters[I].
Kind == CC_Range);
7690 Dests.set(Clusters[I].MBB->
getNumber());
7691 NumCmps += (Clusters[
I].Low == Clusters[
I].High) ? 1 : 2;
7693 unsigned NumDests = Dests.count();
7695 APInt Low = Clusters[First].Low->getValue();
7696 APInt High = Clusters[Last].High->getValue();
7697 assert(Low.
slt(High));
7699 if (!isSuitableForBitTests(NumDests, NumCmps, Low, High))
7705 const int BitWidth = DAG.getTargetLoweringInfo()
7706 .getPointerTy(DAG.getDataLayout())
7708 assert(rangeFitsInWord(Low, High) &&
"Case range must fit in bit mask!");
7718 CmpRange = High - Low;
7722 uint32_t TotalWeight = 0;
7723 for (
unsigned i = First; i <= Last; ++i) {
7726 for (j = 0; j < CBV.size(); ++j)
7727 if (CBV[j].BB == Clusters[i].MBB)
7729 if (j == CBV.size())
7730 CBV.push_back(CaseBits(0, Clusters[i].MBB, 0, 0));
7731 CaseBits *CB = &CBV[j];
7734 uint64_t Lo = (Clusters[i].Low->getValue() - LowBound).getZExtValue();
7735 uint64_t Hi = (Clusters[i].High->getValue() - LowBound).getZExtValue();
7736 assert(Hi >= Lo && Hi < 64 &&
"Invalid bit case!");
7737 CB->Mask |= (-1ULL >> (63 - (Hi -
Lo))) << Lo;
7738 CB->Bits += Hi - Lo + 1;
7739 CB->ExtraWeight += Clusters[i].Weight;
7740 TotalWeight += Clusters[i].Weight;
7741 assert(TotalWeight >= Clusters[i].Weight &&
"Weight overflow!");
7745 std::sort(CBV.begin(), CBV.end(), [](
const CaseBits &a,
const CaseBits &b) {
7747 if (a.ExtraWeight != b.ExtraWeight)
7748 return a.ExtraWeight > b.ExtraWeight;
7749 return a.Bits > b.Bits;
7752 for (
auto &CB : CBV) {
7755 BTI.
push_back(BitTestCase(CB.Mask, BitTestBB, CB.BB, CB.ExtraWeight));
7757 BitTestCases.emplace_back(std::move(LowBound), std::move(CmpRange),
7759 nullptr, std::move(BTI));
7761 BTCluster = CaseCluster::bitTests(Clusters[First].Low, Clusters[Last].High,
7766 void SelectionDAGBuilder::findBitTestClusters(CaseClusterVector &Clusters,
7773 assert(!Clusters.empty());
7774 assert(Clusters[0].
Kind == CC_Range || Clusters[0].
Kind == CC_JumpTable);
7775 for (
const CaseCluster &
C : Clusters)
7776 assert(
C.Kind == CC_Range ||
C.Kind == CC_JumpTable);
7777 for (
unsigned i = 1; i < Clusters.size(); ++i)
7778 assert(Clusters[i-1].High->getValue().
slt(Clusters[i].Low->getValue()));
7792 const int64_t N = Clusters.size();
7802 MinPartitions[N - 1] = 1;
7803 LastElement[N - 1] = N - 1;
7806 for (int64_t i = N - 2; i >= 0; --i) {
7809 MinPartitions[i] = MinPartitions[i + 1] + 1;
7814 for (int64_t j =
std::min(N - 1, i + BitWidth - 1); j > i; --j) {
7818 if (!rangeFitsInWord(Clusters[i].Low->getValue(),
7819 Clusters[j].High->getValue()))
7824 bool RangesOnly =
true;
7826 for (int64_t k = i; k <= j; k++) {
7827 if (Clusters[k].
Kind != CC_Range) {
7831 Dests.set(Clusters[k].MBB->getNumber());
7833 if (!RangesOnly || Dests.count() > 3)
7837 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7838 if (NumPartitions < MinPartitions[i]) {
7840 MinPartitions[i] = NumPartitions;
7847 unsigned DstIndex = 0;
7848 for (
unsigned First = 0, Last; First <
N; First = Last + 1) {
7849 Last = LastElement[First];
7850 assert(First <= Last);
7851 assert(DstIndex <= First);
7853 CaseCluster BitTestCluster;
7854 if (buildBitTests(Clusters, First, Last, SI, BitTestCluster)) {
7855 Clusters[DstIndex++] = BitTestCluster;
7857 size_t NumClusters = Last - First + 1;
7858 std::memmove(&Clusters[DstIndex], &Clusters[First],
7859 sizeof(Clusters[0]) * NumClusters);
7860 DstIndex += NumClusters;
7863 Clusters.resize(DstIndex);
7866 void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
7875 unsigned Size = W.LastCluster - W.FirstCluster + 1;
7879 if (Size == 2 && W.MBB == SwitchMBB) {
7887 CaseCluster &
Small = *W.FirstCluster;
7888 CaseCluster &Big = *W.LastCluster;
7890 if (Small.Low == Small.High && Big.Low == Big.High &&
7891 Small.MBB == Big.MBB) {
7892 const APInt &SmallValue = Small.Low->getValue();
7893 const APInt &BigValue = Big.Low->getValue();
7896 APInt CommonBit = BigValue ^ SmallValue;
7903 DAG.getConstant(CommonBit, DL, VT));
7905 DL,
MVT::i1, Or, DAG.getConstant(BigValue | SmallValue, DL, VT),
7910 addSuccessorWithWeight(SwitchMBB, Small.MBB, Small.Weight + Big.Weight);
7911 addSuccessorWithWeight(
7912 SwitchMBB, DefaultMBB,
7920 DAG.getBasicBlock(Small.MBB));
7922 BrCond = DAG.getNode(
ISD::BR, DL, MVT::Other, BrCond,
7923 DAG.getBasicBlock(DefaultMBB));
7925 DAG.setRoot(BrCond);
7933 std::sort(W.FirstCluster, W.LastCluster + 1,
7934 [](
const CaseCluster &a,
const CaseCluster &b) {
7935 return a.Weight > b.Weight;
7940 for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster; ) {
7942 if (I->Weight > W.LastCluster->Weight)
7944 if (I->Kind == CC_Range && I->MBB == NextMBB) {
7952 uint32_t UnhandledWeights = 0;
7953 for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I) {
7954 UnhandledWeights += I->Weight;
7955 assert(UnhandledWeights >= I->Weight &&
"Weight overflow!");
7959 for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) {
7961 if (I == W.LastCluster) {
7963 Fallthrough = DefaultMBB;
7966 CurMF->
insert(BBI, Fallthrough);
7968 ExportFromCurrentBlock(Cond);
7972 case CC_JumpTable: {
7974 JumpTableHeader *JTH = &JTCases[I->JTCasesIndex].first;
7979 CurMF->
insert(BBI, JumpMBB);
7980 addSuccessorWithWeight(CurMBB, Fallthrough);
7981 addSuccessorWithWeight(CurMBB, JumpMBB);
7985 JTH->HeaderBB = CurMBB;
7986 JT->Default = Fallthrough;
7989 if (CurMBB == SwitchMBB) {
7990 visitJumpTableHeader(*JT, *JTH, SwitchMBB);
7991 JTH->Emitted =
true;
7997 BitTestBlock *BTB = &BitTestCases[I->BTCasesIndex];
8000 for (BitTestCase &BTC : BTB->Cases)
8001 CurMF->
insert(BBI, BTC.ThisBB);
8004 BTB->Parent = CurMBB;
8005 BTB->Default = Fallthrough;
8008 if (CurMBB ==SwitchMBB) {
8009 visitBitTestHeader(*BTB, SwitchMBB);
8010 BTB->Emitted =
true;
8015 const Value *RHS, *LHS, *MHS;
8017 if (I->Low == I->High) {
8032 UnhandledWeights -= I->Weight;
8033 CaseBlock CB(CC, LHS, RHS, MHS, I->MBB, Fallthrough, CurMBB, I->Weight,
8036 if (CurMBB == SwitchMBB)
8037 visitSwitchCase(CB, SwitchMBB);
8039 SwitchCases.push_back(CB);
8044 CurMBB = Fallthrough;
8048 unsigned SelectionDAGBuilder::caseClusterRank(
const CaseCluster &CC,
8049 CaseClusterIt First,
8050 CaseClusterIt Last) {
8051 return std::count_if(First, Last + 1, [&](
const CaseCluster &
X) {
8052 if (X.Weight != CC.Weight)
8053 return X.Weight > CC.Weight;
8056 return X.Low->getValue().slt(CC.Low->getValue());
8060 void SelectionDAGBuilder::splitWorkItem(SwitchWorkList &WorkList,
8061 const SwitchWorkListItem &W,
8064 assert(W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) &&
8065 "Clusters not sorted?");
8067 assert(W.LastCluster - W.FirstCluster + 1 >= 2 &&
"Too small to split!");
8072 CaseClusterIt LastLeft = W.FirstCluster;
8073 CaseClusterIt FirstRight = W.LastCluster;
8074 uint32_t LeftWeight = LastLeft->Weight;
8075 uint32_t RightWeight = FirstRight->Weight;
8082 while (LastLeft + 1 < FirstRight) {
8083 if (LeftWeight < RightWeight || (LeftWeight == RightWeight && (I & 1)))
8084 LeftWeight += (++LastLeft)->Weight;
8086 RightWeight += (--FirstRight)->Weight;
8096 unsigned NumLeft = LastLeft - W.FirstCluster + 1;
8097 unsigned NumRight = W.LastCluster - FirstRight + 1;
8099 if (
std::min(NumLeft, NumRight) < 3 && std::max(NumLeft, NumRight) > 3) {
8103 if (NumLeft < NumRight) {
8105 CaseCluster &CC = *FirstRight;
8106 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8107 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8108 if (LeftSideRank <= RightSideRank) {
8115 assert(NumRight < NumLeft);
8117 CaseCluster &CC = *LastLeft;
8118 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8119 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8120 if (RightSideRank <= LeftSideRank) {
8131 assert(LastLeft + 1 == FirstRight);
8132 assert(LastLeft >= W.FirstCluster);
8133 assert(FirstRight <= W.LastCluster);
8137 CaseClusterIt PivotCluster = FirstRight;
8138 assert(PivotCluster > W.FirstCluster);
8139 assert(PivotCluster <= W.LastCluster);
8141 CaseClusterIt FirstLeft = W.FirstCluster;
8142 CaseClusterIt LastRight = W.LastCluster;
8154 if (FirstLeft == LastLeft && FirstLeft->Kind == CC_Range &&
8155 FirstLeft->Low == W.GE &&
8156 (FirstLeft->High->getValue() + 1LL) == Pivot->
getValue()) {
8157 LeftMBB = FirstLeft->MBB;
8161 WorkList.push_back({LeftMBB, FirstLeft, LastLeft, W.GE, Pivot});
8170 if (FirstRight == LastRight && FirstRight->Kind == CC_Range &&
8171 W.LT && (FirstRight->High->getValue() + 1ULL) == W.LT->getValue()) {
8172 RightMBB = FirstRight->MBB;
8176 WorkList.push_back({RightMBB, FirstRight, LastRight, Pivot, W.LT});
8182 CaseBlock CB(
ISD::SETLT, Cond, Pivot,
nullptr, LeftMBB, RightMBB, W.MBB,
8183 LeftWeight, RightWeight);
8185 if (W.MBB == SwitchMBB)
8191 void SelectionDAGBuilder::visitSwitch(
const SwitchInst &SI) {
8194 CaseClusterVector Clusters;
8196 for (
auto I : SI.
cases()) {
8201 Clusters.push_back(CaseCluster::range(CaseVal, CaseVal, Succ, Weight));
8209 sortAndRangeify(Clusters);
8214 bool UnreachableDefault =
8216 if (UnreachableDefault && !Clusters.empty()) {
8218 unsigned MaxPop = 0;
8220 for (
auto I : SI.
cases()) {
8222 if (++Popularity[BB] > MaxPop) {
8223 MaxPop = Popularity[BB];
8228 assert(MaxPop > 0 && MaxBB);
8233 CaseClusterVector New;
8234 New.reserve(Clusters.size());
8235 for (CaseCluster &CC : Clusters) {
8236 if (CC.MBB != DefaultMBB)
8239 Clusters = std::move(New);
8245 if (Clusters.empty()) {
8247 if (DefaultMBB != NextBlock(SwitchMBB)) {
8254 findJumpTables(Clusters, &SI, DefaultMBB);
8255 findBitTestClusters(Clusters, &SI);
8258 dbgs() <<
"Case clusters: ";
8259 for (
const CaseCluster &
C : Clusters) {
8260 if (
C.Kind == CC_JumpTable)
dbgs() <<
"JT:";
8261 if (
C.Kind == CC_BitTests)
dbgs() <<
"BT:";
8263 C.Low->getValue().print(
dbgs(),
true);
8264 if (
C.Low !=
C.High) {
8266 C.High->getValue().print(
dbgs(),
true);
8273 assert(!Clusters.empty());
8274 SwitchWorkList WorkList;
8275 CaseClusterIt First = Clusters.begin();
8276 CaseClusterIt Last = Clusters.end() - 1;
8277 WorkList.push_back({SwitchMBB, First, Last,
nullptr,
nullptr});
8279 while (!WorkList.empty()) {
8280 SwitchWorkListItem W = WorkList.back();
8281 WorkList.pop_back();
8282 unsigned NumClusters = W.LastCluster - W.FirstCluster + 1;
8286 splitWorkItem(WorkList, W, SI.
getCondition(), SwitchMBB);
8290 lowerWorkItem(W, SI.
getCondition(), SwitchMBB, DefaultMBB);
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
void setHasStackMap(bool s=true)
ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic.
virtual SDValue LowerReturn(SDValue, CallingConv::ID, bool, const SmallVectorImpl< ISD::OutputArg > &, const SmallVectorImpl< SDValue > &, SDLoc, SelectionDAG &) const
This hook must be implemented to lower outgoing return values, described by the Outs array...
static unsigned getTruncatedArgReg(const SDValue &N)
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
void setAllowReciprocal(bool b)
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
BasicBlock * getSuccessor(unsigned i) const
ReturnInst - Return a value (possibly void), from a function.
Value * getValueOperand()
const Value * getCalledValue() const
getCalledValue - Get a pointer to the function that is invoked by this instruction.
std::vector< BitTestBlock > BitTestCases
BitTestCases - Vector of BitTestBlock structures used to communicate SwitchInst code generation infor...
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
bool describes(const Function *F) const
Check if this subprogram decribes the given function.
static MVT getIntegerVT(unsigned BitWidth)
void setByValAlign(unsigned A)
void push_back(const T &Elt)
unsigned Log2_32_Ceil(uint32_t Value)
Log2_32_Ceil - This function returns the ceil log base 2 of the specified value, 32 if the value is z...
The memory access reads data.
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
SelectionDAGBuilder * SDB
A parsed version of the target data layout string in and methods for querying it. ...
AtomicOrdering getFailureOrdering() const
Returns the ordering constraint on this cmpxchg.
AsmDialect getDialect() const
static ConstantInt * getFalse(LLVMContext &Context)
virtual std::pair< SDValue, SDValue > EmitTargetCodeForStrcpy(SelectionDAG &DAG, SDLoc DL, SDValue Chain, SDValue Dest, SDValue Src, MachinePointerInfo DestPtrInfo, MachinePointerInfo SrcPtrInfo, bool isStpcpy) const
EmitTargetCodeForStrcpy - Emit target-specific code that performs a strcpy or stpcpy, in cases where that is faster than a libcall.
ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred)
getICmpCondCode - Return the ISD condition code corresponding to the given LLVM IR integer condition ...
CallLoweringInfo & setCallee(CallingConv::ID CC, Type *ResultType, SDValue Target, ArgListTy &&ArgsList, unsigned FixedArgs=-1)
SDValue getValue(unsigned R) const
This class is the base class for the comparison instructions.
The memory access writes data.
bool findValue(const Value *V) const
unsigned getTypeIDFor(const GlobalValue *TI)
getTypeIDFor - Return the type id for the specified typeinfo.
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant, which is required to be operand #1) half of the integer or float value specified as operand #0.
*p = old <signed v ? old : v
iterator_range< CaseIt > cases()
cases - iteration adapter for range-for loops.
LLVMContext * getContext() const
LLVM Argument representation.
SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N)
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, SDLoc DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd)...
static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse)
Scale down both weights to fit into uint32_t.
void addStackRoot(int Num, const Constant *Metadata)
addStackRoot - Registers a root that lives on the stack.
DELETED_NODE - This is an illegal value that is used to catch errors.
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an vector value) starting with the ...
LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const
Return how we should legalize values of this type, either it is already legal (return 'Legal') or we ...
bool isVolatile() const
isVolatile - Return true if this is a store to a volatile memory location.
void ExportFromCurrentBlock(const Value *V)
ExportFromCurrentBlock - If this condition isn't known to be exported from the current basic block...
SynchronizationScope getSynchScope() const
const TargetLibraryInfo * LibInfo
ArrayRef< unsigned > getIndices() const
Sign extended before/after call.
unsigned getNumRegisters(LLVMContext &Context, EVT VT) const
Return the number of registers that this ValueType will eventually require.
static MVT getVectorVT(MVT VT, unsigned NumElements)
ValTy * getArgument(unsigned ArgNo) const
void LowerStatepoint(ImmutableStatepoint Statepoint, MachineBasicBlock *LandingPad=nullptr)
void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd)
Assign this MachineSDNodes's memory reference descriptor list.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
unsigned EnableFastISel
EnableFastISel - This flag enables fast-path instruction selection which trades away generated code q...
Force argument to be passed in register.
int getNumber() const
getNumber - MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a M...
AtomicOrdering getSuccessOrdering() const
Returns the ordering constraint on this cmpxchg.
FenceInst - an instruction for ordering other memory operations.
InstrTy * getInstruction() const
SDValue getVAArg(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, SDValue SV, unsigned Align)
VAArg produces a result and token chain, and takes a pointer and a source value as input...
void CopyValueToVirtualRegister(const Value *V, unsigned Reg)
AtomicCmpXchgInst - an instruction that atomically checks whether a specified value is in a memory lo...
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
static bool getUniformBase(Value *&Ptr, SDValue &Base, SDValue &Index, SelectionDAGBuilder *SDB)
CallLoweringInfo & setDebugLoc(SDLoc dl)
static unsigned LimitFloatPrecision
LimitFloatPrecision - Generate low-precision inline sequences for some float libcalls (6...
DILocalScope * getScope() const
Get the local scope for this variable.
SDValue getMergeValues(ArrayRef< SDValue > Ops, SDLoc dl)
Create a MERGE_VALUES node from the given operands.
unsigned getNumOperands() const
Nested function static chain.
SelectionDAGBuilder - This is the common target-independent lowering implementation that is parameter...
A specialization of it's base class for read only access to a gc.statepoint.
const TargetMachine & getTarget() const
virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL, SelectionDAG &DAG) const
This callback is used to prepare for a volatile or atomic load.
unsigned getPrefTypeAlignment(Type *Ty) const
Returns the preferred stack/global alignment for the specified type.
MCSymbol * getOrCreateFrameAllocSymbol(StringRef FuncName, unsigned Idx)
Gets a symbol that will be defined to the final stack offset of a local variable after codegen...
static unsigned getFlagWord(unsigned Kind, unsigned NumOps)
SDNode * getGluedNode() const
If this node has a glue operand, return the node to which the glue operand points.
bool isNonNegative() const
Determine if this APInt Value is non-negative (>= 0)
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
A Stackmap instruction captures the location of live variables at its position in the instruction str...
const TargetSubtargetInfo & getSubtarget() const
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain...
CallInst - This class represents a function call, abstracting a target machine's calling convention...
MVT getSimpleValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the MVT corresponding to this LLVM type. See getValueType.
bool usesUnderscoreSetJmp() const
Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
size_type count(PtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
const std::string & getAsmString() const
SDValue getBasicBlock(MachineBasicBlock *MBB)
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
*p = old <unsigned v ? old : v
const TargetSelectionDAGInfo & getSelectionDAGInfo() const
void addLiveIn(unsigned Reg)
Adds the specified register as a live in.
void setValue(const Value *V, SDValue NewN)
unsigned getID() const
getID() - Return the register class ID number.
void visitJumpTableHeader(JumpTable &JT, JumpTableHeader &JTH, MachineBasicBlock *SwitchBB)
visitJumpTableHeader - This function emits necessary code to produce index in the JumpTable from swit...
*p = old >unsigned v ? old : v
Type * getTypeForEVT(LLVMContext &Context) const
getTypeForEVT - This method returns an LLVM type corresponding to the specified EVT.
unsigned getSizeInBits() const
ShuffleVectorInst - This instruction constructs a fixed permutation of two input vectors.
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
virtual bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg) const
For some targets, an LLVM struct type must be broken down into multiple simple types, but the calling convention specifies that the entire struct must be passed in a block of consecutive registers.
static cl::opt< bool > EnableFMFInDAG("enable-fmf-dag", cl::init(false), cl::Hidden, cl::desc("Enable fast-math-flags for DAG nodes"))
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
Type * getReturnType() const
void setInConsecutiveRegs()
const Function * getParent() const
Return the enclosing method, or null if none.
Value * getNewValOperand()
virtual bool isZExtFree(Type *, Type *) const
Return true if any actual instruction that defines a value of type Ty1 implicitly zero-extends the va...
const SDValue & getOperand(unsigned Num) const
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
SDValue getMaskedGather(SDVTList VTs, EVT VT, SDLoc dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO)
This class represents a sign extension of integer types.
virtual bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace=0, unsigned Align=1, bool *=nullptr) const
Determine if the target supports unaligned memory accesses.
LoadInst - an instruction for reading from memory.
static IntegerType * getInt64Ty(LLVMContext &C)
[US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned integers.
AtomicRMWInst - an instruction that atomically reads a memory location, combines it with another valu...
void GetUnderlyingObjects(Value *V, SmallVectorImpl< Value * > &Objects, const DataLayout &DL, LoopInfo *LI=nullptr, unsigned MaxLookup=6)
This method is similar to GetUnderlyingObject except that it can look through phi and select instruct...
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags=0)
CvtCode
CvtCode enum - This enum defines the various converts CONVERT_RNDSAT supports.
bool CanLowerReturn
CanLowerReturn - true iff the function's return value can be lowered to registers.
unsigned getPointerAddressSpace() const
Get the address space of this pointer or pointer vector type.
const SDValue & setRoot(SDValue N)
Set the current root tag of the SelectionDAG.
static IntegerType * getInt16Ty(LLVMContext &C)
bool hasAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return true if the attribute exists at the given index.
const MCPhysReg * iterator
GlobalValue * ExtractTypeInfo(Value *V)
ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V, const Twine &ErrMsg)
void setNoSignedZeros(bool b)
void DeleteNode(SDNode *N)
Remove the specified node from the system.
SDValue getValueImpl(const Value *V)
getValueImpl - Helper function for getValue and getNonRegisterValue.
SDValue getConstantPool(const Constant *C, EVT VT, unsigned Align=0, int Offs=0, bool isT=false, unsigned char TargetFlags=0)
*p = old >signed v ? old : v
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, unsigned f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
getMachineMemOperand - Allocate a new MachineMemOperand.
DebugLoc getCurDebugLoc() const
uint64_t getOffset() const
EntryToken - This is the marker used to indicate the start of a region.
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
void AddDbgValue(SDDbgValue *DB, SDNode *SD, bool isParameter)
Add a dbg_value SDNode.
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
unsigned getResNo() const
get the index which selects a specific result in the SDNode
SDValue getMCSymbol(MCSymbol *Sym, EVT VT)
void ReplaceAllUsesOfValuesWith(const SDValue *From, const SDValue *To, unsigned Num)
Like ReplaceAllUsesOfValueWith, but for multiple values at once.
bool bitsLT(EVT VT) const
bitsLT - Return true if this has less bits than VT.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag=true)
Reports a serious error, calling any installed error handler.
void FindMergedConditions(const Value *Cond, MachineBasicBlock *TBB, MachineBasicBlock *FBB, MachineBasicBlock *CurBB, MachineBasicBlock *SwitchBB, unsigned Opc, uint32_t TW, uint32_t FW)
FindMergedConditions - If Cond is an expression like.
SDValue getExternalSymbol(const char *Sym, EVT VT)
Constant * getMask() const
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
SDValue getMemcpy(SDValue Chain, SDLoc dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
static MachinePointerInfo getFixedStack(int FI, int64_t offset=0)
getFixedStack - Return a MachinePointerInfo record that refers to the the specified FrameIndex...
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
virtual bool pointsToConstantMemory(const MemoryLocation &Loc, bool OrLocal=false)
pointsToConstantMemory - If the specified memory location is known to be constant, return true.
void setCurrentCallSite(unsigned Site)
setCurrentCallSite - Set the call site currently being processed.
StringRef getName() const
Return a constant reference to the value's name.
MachineJumpTableInfo * getOrCreateJumpTableInfo(unsigned JTEntryKind)
getOrCreateJumpTableInfo - Get the JumpTableInfo for this function, if it does already exist...
SDValue getValue(const Value *V)
getValue - Return an SDValue for the given Value.
iterator begin()
Instruction iterator methods.
bool isSingleValueType() const
isSingleValueType - Return true if the type is a valid type for a register in codegen.
OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer) This corresponds to the eh.sjlj.longjmp intrinsic...
SelectPatternFlavor matchSelectPattern(Value *V, Value *&LHS, Value *&RHS, Instruction::CastOps *CastOp=nullptr)
Pattern match integer [SU]MIN, [SU]MAX and ABS idioms, returning the kind and providing the out param...
StackProtectorDescriptor SPDescriptor
A StackProtectorDescriptor structure used to communicate stack protector information in between Selec...
Instruction * getFirstNonPHIOrDbg()
Returns a pointer to the first instruction in this block that is not a PHINode or a debug intrinsic...
bool isVector() const
isVector - Return true if this is a vector value type.
void setNoSignedWrap(bool b)
void visitSPDescriptorParent(StackProtectorDescriptor &SPD, MachineBasicBlock *ParentBB)
Codegen a new tail for a stack protector check ParentMBB which has had its tail spliced into a stack ...
SDValue getRoot()
getRoot - Return the current virtual root of the Selection DAG, flushing any PendingLoad items...
BlockAddress - The address of a basic block.
bool onlyReadsMemory() const
Determine if the call does not access or only reads memory.
SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
void setAttributes(ImmutableCallSite *CS, unsigned AttrIdx)
Set CallLoweringInfo attribute flags based on a call instruction and called function attributes...
bool isUnconditional() const
MachineMemOperand - A description of a memory reference used in the backend.
unsigned DemoteRegister
DemoteRegister - if CanLowerReturn is false, DemoteRegister is a vreg allocated to hold a pointer to ...
void setHasPatchPoint(bool s=true)
static Value * getPointerOperand(Instruction &Inst)
static unsigned getFlagWordForRegClass(unsigned InputFlag, unsigned RC)
getFlagWordForRegClass - Augment an existing flag word returned by getFlagWord with the required regi...
SDValue getMemset(SDValue Chain, SDLoc dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool isTailCall, MachinePointerInfo DstPtrInfo)
unsigned getNumBlockIDs() const
getNumBlockIDs - Return the number of MBB ID's allocated.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
PCMARKER - This corresponds to the pcmarker intrinsic.
bool noSignedZeros() const
void visitSwitchCase(CaseBlock &CB, MachineBasicBlock *SwitchBB)
visitSwitchCase - Emits the necessary code to represent a single node in the binary search tree resul...
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
const HexagonInstrInfo * TII
static SDValue GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, SDLoc dl)
GetExponent - Get the exponent:
const APInt & getValue() const
Return the constant as an APInt value reference.
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false)
Shift and rotation operations.
std::size_t countTrailingOnes(T Value, ZeroBehavior ZB=ZB_Width)
Count the number of ones from the least significant bit to the first zero bit.
StructType - Class to represent struct types.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
A Use represents the edge between a Value definition and its users.
bool hasOptimizedCodeGen(LibFunc::Func F) const
Tests if the function is both available and a candidate for optimized code generation.
bool isDereferenceablePointer(const Value *V, const DataLayout &DL, const Instruction *CtxI=nullptr, const DominatorTree *DT=nullptr, const TargetLibraryInfo *TLI=nullptr)
isDereferenceablePointer - Return true if this is always a dereferenceable pointer.
MachineFunction & getMachineFunction() const
void visitJumpTable(JumpTable &JT)
visitJumpTable - Emit JumpTable node in the current MBB
std::pair< SDValue, SDValue > makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops, unsigned NumOps, bool isSigned, SDLoc dl, bool doesNotReturn=false, bool isReturnValueUsed=true) const
Returns a pair of (return value, chain).
TargetLowering::ConstraintType ConstraintType
Information about the constraint code, e.g.
CallLoweringInfo & setChain(SDValue InChain)
Constant * ConstantFoldLoadFromConstPtr(Constant *C, const DataLayout &DL)
ConstantFoldLoadFromConstPtr - Return the value that a load from C would produce if it is constant an...
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
unsigned getNumArgOperands() const
getNumArgOperands - Return the number of call arguments.
SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, SDLoc dl, SDValue &Chain, SDValue *Flag, const Value *V=nullptr) const
getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from this value and returns the resu...
SDValue getTargetGlobalAddress(const GlobalValue *GV, SDLoc DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast between SrcAS and DestAS is a noop.
const TargetRegisterClass * getRegClass(unsigned Reg) const
getRegClass - Return the register class of the specified virtual register.
FLT_ROUNDS_ - Returns current rounding mode: -1 Undefined 0 Round to 0 1 Round to nearest 2 Round to ...
const Value * getCalledValue() const
getCalledValue - Get a pointer to the function that is invoked by this instruction ...
SmallVector< EVT, 4 > ValueVTs
ValueVTs - The value types of the values, which may not be legal, and may need be promoted or synthes...
iterator begin() const
begin/end - Return all of the registers in this class.
Reg
All possible values of the reg field in the ModR/M byte.
SDDbgValue * getDbgValue(MDNode *Var, MDNode *Expr, SDNode *N, unsigned R, bool IsIndirect, uint64_t Off, DebugLoc DL, unsigned O)
Creates a SDDbgValue node.
TypeID
Definitions of all of the base types for the Type system.
bool isSized(SmallPtrSetImpl< const Type * > *Visited=nullptr) const
isSized - Return true if it makes sense to take the size of this type.
EVT getScalarType() const
getScalarType - If this is a vector type, return the element type, otherwise return this...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) For double-word atomic operations: ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi) ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi) These correspond to the atomicrmw instruction.
Number of individual test Apply this number of consecutive mutations to each input exit after the first new interesting input is found the minimized corpus is saved into the first input directory Number of jobs to run If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
static bool isRegDefEarlyClobberKind(unsigned Flag)
static unsigned convertMemFlagWordToMatchingFlagWord(unsigned InputFlag)
bool bitsGE(EVT VT) const
bitsGE - Return true if this has no less bits than VT.
static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI)
expandExp - Lower an exp intrinsic.
static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx, SDLoc DL, SmallVectorImpl< SDValue > &Ops, SelectionDAGBuilder &Builder)
Add a stack map intrinsic call's live variable operands to a stackmap or patchpoint target node's ope...
void setByValSize(unsigned S)
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
unsigned getStoreSize() const
getStoreSize - Return the number of bytes overwritten by a store of the specified value type...
The memory access is volatile.
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG...
void setFunctionContextIndex(int I)
static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI)
expandLog10 - Lower a log10 intrinsic.
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Hidden pointer to structure to return.
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
INLINEASM - Represents an inline asm block.
OutputArg - This struct carries flags and a value for a single outgoing (actual) argument or outgoing...
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
unsigned getEVTAlignment(EVT MemoryVT) const
getEVTAlignment - Compute the default alignment value for the given type.
SynchronizationScope getSynchScope() const
SmallVector< ISD::InputArg, 32 > Ins
STACKSAVE - STACKSAVE has one operand, an input chain.
FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to first (possible) on-stack ar...
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
virtual MVT getVectorIdxTy(const DataLayout &DL) const
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
bool isStatepoint(const ImmutableCallSite &CS)
EVT getVectorElementType() const
getVectorElementType - Given a vector type, return the type of each element.
void assign(size_type NumElts, const T &Elt)
bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const
When splitting a value of the specified type into parts, does the Lo or Hi part come first...
int getArgumentFrameIndex(const Argument *A)
getArgumentFrameIndex - Get frame index for the byval argument.
void emitError(unsigned LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
Value * getPointerOperand()
SDValue getCALLSEQ_START(SDValue Chain, SDValue Op, SDLoc DL)
Return a new CALLSEQ_START node, which always must have a glue result (to ensure it's not CSE'd)...
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
FunctionType - Class to represent function types.
ConstantExpr - a constant value that is initialized with an expression using other constant values...
AtomicOrdering getOrdering() const
Returns the ordering constraint on this RMW.
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
bool usesUnderscoreLongJmp() const
Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
LLVMContext & getContext() const
getContext - Return the LLVMContext in which this type was uniqued.
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
const LiveOutInfo * GetLiveOutRegInfo(unsigned Reg)
GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the register is a PHI destinat...
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
ValTy * getCalledValue() const
getCalledValue - Return the pointer to function that is being called.
void setCallSiteBeginLabel(MCSymbol *BeginLabel, unsigned Site)
setCallSiteBeginLabel - Map the begin label for a call site.
ConstantDataSequential - A vector or array constant whose element type is a simple 1/2/4/8-byte integ...
void GetReturnInfo(Type *ReturnType, AttributeSet attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags...
const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
SDValue getTargetFrameIndex(int FI, EVT VT)
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
virtual EVT getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT, ISD::NodeType) const
Return the type that should be used to zero or sign extend a zeroext/signext integer argument or retu...
This contains information for each constraint that we are lowering.
Simple integer binary arithmetic operators.
SDValue getVectorShuffle(EVT VT, SDLoc dl, SDValue N1, SDValue N2, const int *MaskElts)
Return an ISD::VECTOR_SHUFFLE node.
static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS, SelectionDAG &DAG)
ExpandPowI - Expand a llvm.powi intrinsic.
SDValue getNonRegisterValue(const Value *V)
getNonRegisterValue - Return an SDValue for the given Value, but don't look in FuncInfo.ValueMap for a virtual register.
This instruction compares its operands according to the predicate given to the constructor.
BasicBlock * getSuccessor(unsigned i) const
SmallVector< ISD::OutputArg, 32 > Outs
This class represents a no-op cast from one type to another.
unsigned getCurrentCallSite()
getCurrentCallSite - Get the call site currently being processed, if any.
uint64_t getTypeStoreSize(Type *Ty)
getTypeStoreSize - Return the DataLayout store size for the given type, if known, or a conservative v...
bool isFloatingPointTy() const
isFloatingPointTy - Return true if this is one of the six floating point types
bool ShouldEmitAsBranches(const std::vector< CaseBlock > &Cases)
If the set of cases should be emitted as a series of branches, return true.
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
StoreInst - an instruction for storing to memory.
static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI)
expandLog2 - Lower a log2 intrinsic.
int getMinimumJumpTableEntries() const
Return integer threshold on number of blocks to use jump tables rather than if sequence.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
virtual SDValue LowerCall(CallLoweringInfo &, SmallVectorImpl< SDValue > &) const
This hook must be implemented to lower calls into the specified DAG.
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
bool allowReciprocal() const
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred)
getFCmpCondCode - Return the ISD condition code corresponding to the given LLVM IR floating-point con...
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
ConstraintPrefix Type
Type - The basic type of the constraint: input/output/clobber.
unsigned getNumElements() const
Return the number of elements in the Vector type.
static bool isRegDefKind(unsigned Flag)
void setStackProtectorIndex(int I)
void setOrigAlign(unsigned A)
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
Type * getElementType() const
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
const DataLayout & getDataLayout() const
bool bitsLE(EVT VT) const
bitsLE - Return true if this has no more bits than VT.
bool isAtomic() const
isAtomic - Return true if this instruction has an AtomicOrdering of unordered or higher.
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
void AddLandingPadInfo(const LandingPadInst &I, MachineModuleInfo &MMI, MachineBasicBlock *MBB)
AddLandingPadInfo - Extract the exception handling information from the landingpad instruction and ad...
PointerType - Class to represent pointers.
const BasicBlock * getBasicBlock() const
getBasicBlock - Return the LLVM basic block that this instance corresponded to originally.
void append(const RegsForValue &RHS)
append - Add the specified values to this one.
UNDEF - An undefined node.
SDValue getAddrSpaceCast(SDLoc dl, EVT VT, SDValue Ptr, unsigned SrcAS, unsigned DestAS)
Return an AddrSpaceCastSDNode.
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
TargetSelectionDAGInfo - Targets can subclass this to parameterize the SelectionDAG lowering and inst...
Flag
These should be considered private to the implementation of the MCInstrDesc class.
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable...
TargetInstrInfo - Interface to description of machine instruction set.
This corresponds to the llvm.lifetime.
bool unsafeAlgebra() const
static Constant * getBitCast(Constant *C, Type *Ty, bool OnlyIfReduced=false)
DBG_VALUE - a mapping of the llvm.dbg.value intrinsic.
unsigned getNumSuccessors() const
Return the number of successors that this terminator has.
SDNode * getNode() const
get the SDNode which holds the desired result
GetElementPtrInst - an instruction for type-safe pointer arithmetic to access elements of arrays and ...
bundle_iterator< MachineInstr, instr_iterator > iterator
A self-contained host- and target-independent arbitrary-precision floating-point software implementat...
bool getLibFunc(StringRef funcName, LibFunc::Func &F) const
Searches for a particular function name.
unsigned getStoreSize() const
getStoreSize - Return the number of bytes overwritten by a store of the specified value type...
SDValue getMDNode(const MDNode *MD)
Return an MDNodeSDNode which holds an MDNode.
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
virtual std::pair< SDValue, SDValue > EmitTargetCodeForStrlen(SelectionDAG &DAG, SDLoc DL, SDValue Chain, SDValue Src, MachinePointerInfo SrcPtrInfo) const
Instruction that records the offset of a local stack allocation passed to llvm.localescape.
initializer< Ty > init(const Ty &Val)
SDValue getMaskedScatter(SDVTList VTs, EVT VT, SDLoc dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO)
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
Patchable call instruction - this instruction represents a call to a constant address, followed by a series of NOPs.
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
LandingPadInst - The landingpad instruction holds all of the information necessary to generate correc...
Control flow instructions. These all have token chains.
MCSymbol * createTempSymbol(bool CanBeUnnamed=true)
Create and return a new assembler temporary symbol with a unique but unspecified name.
READ_REGISTER, WRITE_REGISTER - This node represents llvm.register on the DAG, which implements the n...
unsigned getAlignment() const
getAlignment - Return the alignment of the access that is being performed
Subclasses of this class are all able to terminate a basic block.
std::vector< std::pair< MachineInstr *, unsigned > > PHINodesToUpdate
PHINodesToUpdate - A list of phi instructions whose operand list will be updated after processing the...
std::size_t countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the least significant bit to the most stopping at the first 1...
bool HasTailCall
HasTailCall - This is set to true if a call in the current block has been translated as a tail call...
void setCallsEHReturn(bool b)
unsigned getVectorNumElements() const
LOCAL_RECOVER - Represents the llvm.localrecover intrinsic.
bool hasSideEffects() const
MVT - Machine Value Type.
SynchronizationScope getSynchScope() const
Returns whether this RMW is atomic between threads or only within a single thread.
LLVM Basic Block Representation.
const SDValue & getOperand(unsigned i) const
The instances of the Type class are immutable: once they are created, they are never changed...
BasicBlock * getSuccessor(unsigned idx) const
Return the specified successor.
This is an important class for using LLVM in a threaded context.
DIExpression * getExpression() const
void AddInlineAsmOperands(unsigned Kind, bool HasMatching, unsigned MatchingIdx, SDLoc dl, SelectionDAG &DAG, std::vector< SDValue > &Ops) const
AddInlineAsmOperands - Add this value to the specified inlineasm node operand list.
const Function * getParent() const
Simple binary floating point operators.
BranchInst - Conditional or Unconditional Branch instruction.
bool isVectorTy() const
isVectorTy - True if this is an instance of VectorType.
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
UnreachableInst - This function has undefined behavior.
This is an important base class in LLVM.
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE...
bool isVector() const
isVector - Return true if this is a vector value type.
ResumeInst - Resume the propagation of an exception.
Value * getCompareOperand()
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL...
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
This file contains the declarations for the subclasses of Constant, which represent the different fla...
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
IndirectBrInst - Indirect Branch Instruction.
static SDValue getLimitedPrecisionExp2(SDValue t0, SDLoc dl, SelectionDAG &DAG)
void LowerCallTo(ImmutableCallSite CS, SDValue Callee, bool IsTailCall, MachineBasicBlock *LandingPad=nullptr)
APInt Or(const APInt &LHS, const APInt &RHS)
Bitwise OR function for APInt.
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
unsigned getAlignment() const
getAlignment - Return the alignment of the memory that is being allocated by the instruction.
ConstantFP - Floating Point Values [float, double].
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
virtual std::pair< SDValue, SDValue > EmitTargetCodeForMemchr(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Src, SDValue Char, SDValue Length, MachinePointerInfo SrcPtrInfo) const
EmitTargetCodeForMemchr - Emit target-specific code that performs a memchr, in cases where that is fa...
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag...
A udiv or sdiv instruction, which can be marked as "exact", indicating that no bits are destroyed...
This pseudo-instruction loads the stack guard value.
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
Pass structure in an alloca.
static Type * getVoidTy(LLVMContext &C)
static cl::opt< unsigned, true > LimitFPPrecision("limit-float-precision", cl::desc("Generate low-precision inline sequences ""for some float libcalls"), cl::location(LimitFloatPrecision), cl::init(0))
static SDValue getF32Constant(SelectionDAG &DAG, unsigned Flt, SDLoc dl)
getF32Constant - Get 32-bit floating point constant.
SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT)
void visitBitTestCase(BitTestBlock &BB, MachineBasicBlock *NextMBB, uint32_t BranchWeightToNext, unsigned Reg, BitTestCase &B, MachineBasicBlock *SwitchBB)
visitBitTestCase - this function produces one "bit test"
SDValue getSExtOrTrunc(SDValue Op, SDLoc DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either sign-extending or trunca...
INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic.
void getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl, SDValue &Chain, SDValue *Flag, const Value *V=nullptr, ISD::NodeType PreferredExtendType=ISD::ANY_EXTEND) const
getCopyToRegs - Emit a series of CopyToReg nodes that copies the specified value into the registers s...
void clear()
Clear the memory usage of this object.
virtual bool isFMAFasterThanFMulAndFAdd(EVT) const
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
virtual void EmitFunctionEntryCode()
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang","erlang-compatible garbage collector")
This instruction compares its operands according to the predicate given to the constructor.
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
SDValue getTargetConstant(uint64_t Val, SDLoc DL, EVT VT, bool isOpaque=false)
Utility class for integer arithmetic operators which may exhibit overflow - Add, Sub, and Mul.
unsigned getBitWidth() const
Return the number of bits in the APInt.
static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, Type *LoadTy, SelectionDAGBuilder &Builder)
unsigned getOpcode() const
TRAP - Trapping instruction.
bool doesNotAccessMemory() const
Determine if the call does not access memory.
Value * getOperand(unsigned i) const
Zero extended before/after call.
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI)
expandExp2 - Lower an exp2 intrinsic.
Value * getPointerOperand()
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
DEBUGTRAP - Trap intended to get the attention of a debugger.
virtual bool useLoadStackGuardNode() const
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
void addInvoke(MachineBasicBlock *LandingPad, MCSymbol *BeginLabel, MCSymbol *EndLabel)
addInvoke - Provide the begin and end labels of an invoke style call and associate it with a try land...
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
ConstantVector - Constant Vector Declarations.
SDLoc getCurSDLoc() const
static unsigned getFlagWordForMem(unsigned InputFlag, unsigned Constraint)
Augment an existing flag word returned by getFlagWord with the constraint code for a memory constrain...
unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Vector types are broken down into some number of legal first class types.
virtual std::pair< SDValue, SDValue > EmitTargetCodeForStrnlen(SelectionDAG &DAG, SDLoc DL, SDValue Chain, SDValue Src, SDValue MaxLength, MachinePointerInfo SrcPtrInfo) const
Bit counting operators with an undefined result for zero inputs.
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
unsigned ExceptionPointerVirtReg
If the current MBB is a landing pad, the exception pointer and exception selector registers are copie...
unsigned getStackPointerRegisterToSaveRestore() const
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save...
void append(in_iter in_start, in_iter in_end)
Add the specified range to the end of the SmallVector.
static bool isMemKind(unsigned Flag)
EVT - Extended Value Type.
bool isPointerTy() const
isPointerTy - True if this is an instance of PointerType.
std::vector< ArgListEntry > ArgListTy
unsigned getExceptionPointerRegister() const
If a physical register, this returns the register that receives the exception address on entry to a l...
VAArgInst - This class represents the va_arg llvm instruction, which returns an argument of the speci...
SDValue getGlobalAddress(const GlobalValue *GV, SDLoc DL, EVT VT, int64_t offset=0, bool isTargetGA=false, unsigned char TargetFlags=0)
SDValue getMaskedLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, SDValue Mask, SDValue Src0, EVT MemVT, MachineMemOperand *MMO, ISD::LoadExtType)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void EmitBranchForMergedCondition(const Value *Cond, MachineBasicBlock *TBB, MachineBasicBlock *FBB, MachineBasicBlock *CurBB, MachineBasicBlock *SwitchBB, uint32_t TW, uint32_t FW)
EmitBranchForMergedCondition - Helper method for FindMergedConditions.
virtual unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const
Return the desired alignment for ByVal or InAlloca aggregate function arguments in the caller paramet...
LLVMContext & getContext() const
All values hold a context through their type.
This structure contains all information that is necessary for lowering calls.
virtual SDValue LowerFormalArguments(SDValue, CallingConv::ID, bool, const SmallVectorImpl< ISD::InputArg > &, SDLoc, SelectionDAG &, SmallVectorImpl< SDValue > &) const
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array...
MachinePointerInfo - This class contains a discriminated union of information about pointers in memor...
bool isPowerOf2() const
Check if this APInt's value is a power of two greater than zero.
LLVM_READONLY APFloat maxnum(const APFloat &A, const APFloat &B)
Implements IEEE maxNum semantics.
const SDValue & getRoot() const
Return the root tag of the SelectionDAG.
SDValue getMaskedStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, SDValue Mask, EVT MemVT, MachineMemOperand *MMO, bool IsTrunc)
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
MachineBasicBlock * MBB
MBB - The current block.
bool isInTailCallPosition(ImmutableCallSite CS, const TargetMachine &TM)
Test if the given instruction is in a position to be optimized with a tail-call.
unsigned getNumSuccessors() const
The memory access is invariant.
virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=nullptr) const
Determines the constraint code and constraint type to use for the specific AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
void dump() const
Support for debugging, callable in GDB: V->dump()
BasicBlock * getSuccessor(unsigned i) const
TargetIntrinsicInfo - Interface to description of machine instruction set.
void CopyToExportRegsIfNeeded(const Value *V)
CopyToExportRegsIfNeeded - If the given value has virtual registers created for it, emit nodes to copy the value into the virtual registers.
Representation for a specific memory location.
virtual const TargetFrameLowering * getFrameLowering() const
std::vector< AsmOperandInfo > AsmOperandInfoVector
TokenFactor - This node takes multiple tokens as input and produces a single token result...
unsigned getABITypeAlignment(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
void visitSPDescriptorFailure(StackProtectorDescriptor &SPD)
Codegen the failure basic block for a stack protector check.
static IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
DIExpression * getExpression() const
SDValue getConvertRndSat(EVT VT, SDLoc dl, SDValue Val, SDValue DTy, SDValue STy, SDValue Rnd, SDValue Sat, ISD::CvtCode Code)
Returns the ConvertRndSat Note: Avoid using this node because it may disappear in the future and most...
SDDbgValue * getConstantDbgValue(MDNode *Var, MDNode *Expr, const Value *C, uint64_t Off, DebugLoc DL, unsigned O)
Constant.
void setNoUnsignedWrap(bool b)
AtomicOrdering getOrdering() const
Returns the ordering effect of this store.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
unsigned countPopulation(T Value)
Count the number of set bits in a value.
virtual unsigned getJumpTableEncoding() const
Return the entry encoding for a jump table in the current function.
static PointerType * getUnqual(Type *ElementType)
PointerType::getUnqual - This constructs a pointer to an object of the specified type in the generic ...
This is the shared class of boolean and integer constants.
bool slt(const APInt &RHS) const
Signed less than comparison.
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
uint64_t getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
const MCContext & getContext() const
const DataLayout * getDataLayout() const
Deprecated in 3.7, will be removed in 3.8.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
RegsForValue - This struct represents the registers (physical or virtual) that a particular set of va...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
SmallVector< MachineInstr *, 8 > ArgDbgValues
ArgDbgValues - A list of DBG_VALUE instructions created during isel for function arguments that are i...
Utility class for floating point operations which can have information about relaxed accuracy require...
This is a utility class that provides an abstraction for the common functionality between Instruction...
Module.h This file contains the declarations for the Module class.
Type * getType() const
All values are typed, get the type of this value.
SelectPatternFlavor
Specific patterns of select instructions we can match.
void setCallsUnwindInit(bool b)
Provides information about what library functions are available for the current target.
virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const
Return the ValueType of the result of SETCC operations.
MDNode * getMetadata(unsigned KindID) const
getMetadata - Get the metadata of given kind attached to this Instruction.
void clear()
clear - Clear out the current SelectionDAG and the associated state and prepare this SelectionDAGBuil...
bool isVolatile() const
isVolatile - Return true if this is a load from a volatile memory location.
BRCOND - Conditional branch.
An SDNode that represents everything that will be needed to construct a MachineInstr.
virtual std::pair< SDValue, SDValue > EmitTargetCodeForMemcmp(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const
EmitTargetCodeForMemcmp - Emit target-specific code that performs a memcmp, in cases where that is fa...
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Byte Swap and Counting operators.
void visit(const Instruction &I)
unsigned arg_size() const
static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel)
isOnlyUsedInEntryBlock - If the specified argument is only used in the entry block, return true.
Value * stripPointerCasts()
Strip off pointer casts, all-zero GEPs, and aliases.
SDValue getAtomic(unsigned Opcode, SDLoc dl, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Val, const Value *PtrVal, unsigned Alignment, AtomicOrdering Ordering, SynchronizationScope SynchScope)
Gets a node for an atomic op, produces result (if relevant) and chain and takes 2 operands...
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static bool isSequentialInRange(const SmallVectorImpl< int > &Mask, unsigned Pos, unsigned Size, int Low)
Function * getCalledFunction() const
getCalledFunction - Return the function called, or null if this is an indirect function invocation...
AtomicOrdering getOrdering() const
Returns the ordering effect of this fence.
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
bool isZero() const
This is just a convenience method to make client code smaller for a common code.
Represents one node in the SelectionDAG.
const BasicBlock & getEntryBlock() const
const MachineInstrBuilder & addFrameIndex(int Idx) const
void UpdateSplitBlock(MachineBasicBlock *First, MachineBasicBlock *Last)
UpdateSplitBlock - When an MBB was split during scheduling, update the references that need to refer ...
bool isNullValue() const
isNullValue - Return true if this is the value that would be returned by getNullValue.
static void getCopyToParts(SelectionDAG &DAG, SDLoc DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, const Value *V, ISD::NodeType ExtendKind=ISD::ANY_EXTEND)
getCopyToParts - Create a series of nodes that contain the specified value split into legal parts...
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
static ConstantInt * getTrue(LLVMContext &Context)
BinOp getOperation() const
ISD::CondCode getFCmpCodeWithoutNaN(ISD::CondCode CC)
getFCmpCodeWithoutNaN - Given an ISD condition code comparing floats, return the equivalent code if w...
Intrinsic::ID getIntrinsicID() const LLVM_READONLY
getIntrinsicID - This method returns the ID number of the specified function, or Intrinsic::not_intri...
unsigned CreateRegs(Type *Ty)
CreateRegs - Allocate the appropriate number of virtual registers of the correctly promoted or expand...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
static SDValue GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl)
GetSignificand - Get the significand and build it into a floating-point number with exponent of 1: ...
static bool areJTsAllowed(const TargetLowering &TLI)
unsigned Log2_32(uint32_t Value)
Log2_32 - This function returns the floor log base 2 of the specified value, -1 if the value is zero...
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
AttributeSet getAttributes() const
Return the attribute list for this Function.
GCFunctionInfo * GFI
GFI - Garbage collection metadata for the function.
SynchronizationScope getSynchScope() const
Value * getArgOperand(unsigned i) const
getArgOperand/setArgOperand - Return/set the i-th call argument.
VectorType - Class to represent vector types.
virtual const char * getClearCacheBuiltinName() const
Return the builtin name for the __builtin___clear_cache intrinsic Default is to invoke the clear cach...
static const unsigned MaxParallelChains
Class for arbitrary precision integers.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
BranchProbabilityInfo * BPI
Select(COND, TRUEVAL, FALSEVAL).
Value * getIncomingValueForBlock(const BasicBlock *BB) const
bool isIntegerTy() const
isIntegerTy - True if this is an instance of IntegerType.
This file defines the FastISel class.
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
Return the register class that should be used for the specified value type.
iterator_range< user_iterator > users()
ZERO_EXTEND - Used for integer types, zeroing the new bits.
static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, const Value *V, ISD::NodeType AssertOp=ISD::DELETED_NODE)
getCopyFromParts - Create a value that contains the specified legal parts combined into the value the...
std::vector< JumpTableBlock > JTCases
JTCases - Vector of JumpTable structures used to communicate SwitchInst code generation information...
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
ANY_EXTEND - Used for integer types. The high bits are undefined.
static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI)
Returns an AttributeSet representing the attributes applied to the return value of the given call...
static bool IsOnlyUsedInZeroEqualityComparison(const Value *V)
IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the value is equal or not-eq...
static void GetRegistersForValue(SelectionDAG &DAG, const TargetLowering &TLI, SDLoc DL, SDISelAsmOperandInfo &OpInfo)
GetRegistersForValue - Assign registers (virtual or physical) for the specified operand.
Value * getCondition() const
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
const AttributeSet & getAttributes() const
getAttributes - Return the parameter attributes for this call.
int getStackProtectorIndex() const
Return the index for the stack protector object.
SDValue getBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, bool isTarget=false, unsigned char TargetFlags=0)
virtual bool CanLowerReturn(CallingConv::ID, MachineFunction &, bool, const SmallVectorImpl< ISD::OutputArg > &, LLVMContext &) const
This hook should be implemented to check whether the return values described by the Outs array can fi...
SDDbgValue * getFrameIndexDbgValue(MDNode *Var, MDNode *Expr, unsigned FI, uint64_t Off, DebugLoc DL, unsigned O)
FrameIndex.
const Type * getScalarType() const LLVM_READONLY
getScalarType - If this is a vector type, return the element type, otherwise return 'this'...
APInt And(const APInt &LHS, const APInt &RHS)
Bitwise AND function for APInt.
SmallVector< SDValue, 8 > PendingLoads
PendingLoads - Loads are not emitted to the program immediately.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
CallLoweringInfo & setTailCall(bool Value=true)
DenseMap< const Value *, ISD::NodeType > PreferredExtendType
Record the preferred extend type (ISD::SIGN_EXTEND or ISD::ZERO_EXTEND) for a value.
BR_JT - Jumptable branch.
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the source.
static StringRef getRealLinkageName(StringRef Name)
If special LLVM prefix that is used to inform the asm printer to not emit usual symbol prefix before ...
unsigned countLeadingOnes() const
Count the number of leading one bits.
static bool isPhysicalRegister(unsigned Reg)
isPhysicalRegister - Return true if the specified register number is in the physical register namespa...
cl::opt< std::string > TrapFuncName("trap-func", cl::Hidden, cl::desc("Emit a call to trap function rather than a trap instruction"), cl::init(""))
These are IR-level optimization flags that may be propagated to SDNodes.
Represents a use of a SDNode.
unsigned ExceptionSelectorVirtReg
SmallVector< SDValue, 32 > OutVals
bool isLandingPad() const
isLandingPad - Returns true if the block is a landing pad.
static const fltSemantics IEEEsingle
Value * getCondition() const
Analysis pass providing branch probability information.
BasicBlock * getDefaultDest() const
Bitwise operators - logical and, logical or, logical xor.
pointer data()
Return a pointer to the vector's buffer, even if empty().
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
bool isAggregateType() const
isAggregateType - Return true if the type is an aggregate type.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static IntegerType * getInt32Ty(LLVMContext &C)
AtomicOrdering getOrdering() const
Returns the ordering effect of this fence.
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
bool isDeclaration() const
Return true if the primary definition of this global value is outside of the current translation unit...
DbgValueInst - This represents the llvm.dbg.value instruction.
unsigned getAlignment() const
getAlignment - Return the alignment of the access that is being performed
Value * getPointerOperand()
void getAAMetadata(AAMDNodes &N, bool Merge=false) const
getAAMetadata - Fills the AAMDNodes structure with AA metadata from this instruction.
ImmutableCallSite - establish a view to a call site for examination.
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
void ReplaceAllUsesWith(SDValue From, SDValue Op)
Modify anything using 'From' to use 'To' instead.
CallingConv::ID getCallingConv() const
getCallingConv/setCallingConv - get or set the calling convention of the call.
void push_back(MachineInstr *MI)
TerminatorInst * getTerminator()
Returns the terminator instruction if the block is well formed or null if the block is not well forme...
bool hasOneUse() const
Return true if there is exactly one user of this value.
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
static Constant * getZeroValueForNegation(Type *Ty)
Floating point negation must be implemented with f(x) = -0.0 - x.
std::pair< SDValue, SDValue > lowerCallOperands(ImmutableCallSite CS, unsigned ArgIdx, unsigned NumArgs, SDValue Callee, Type *ReturnTy, MachineBasicBlock *LandingPad=nullptr, bool IsPatchPoint=false)
Lower an argument list according to the target calling convention.
iterator find(const KeyT &Val)
MachineBasicBlock::iterator InsertPt
MBB - The current insert position inside the current block.
MachineSDNode * getMachineNode(unsigned Opcode, SDLoc dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s), MachineInstr opcode, and operands.
unsigned CreateReg(MVT VT)
CreateReg - Allocate a single virtual register for the given type.
StatepointLoweringState StatepointLowering
State used while lowering a statepoint sequence (gc_statepoint, gc_relocate, and gc_result).
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
DenseMap< const AllocaInst *, int > StaticAllocaMap
StaticAllocaMap - Keep track of frame indices for fixed sized allocas in the entry block...
RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer) This corresponds to the eh.sjlj.setjmp intrinsic.
unsigned getNumCases() const
getNumCases - return the number of 'cases' in this switch instruction, except the default case ...
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
SDValue getMemmove(SDValue Chain, SDLoc dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSS, const AllocaInst *Alloca=nullptr)
Create a new statically sized stack object, returning a nonnegative identifier to represent it...
SDValue getCopyFromRegs(const Value *V, Type *Ty)
getCopyFromRegs - If there was virtual register allocated for the value V emit CopyFromReg of the spe...
EVT getValueType() const
Return the ValueType of the referenced return value.
bool hasLocalLinkage() const
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 'eh_return' gcc dwarf builtin...
virtual std::pair< SDValue, SDValue > EmitTargetCodeForStrcmp(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const
EmitTargetCodeForStrcmp - Emit target-specific code that performs a strcmp, in cases where that is fa...
Attribute getAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return the attribute object that exists at the given index.
SDValue getConstant(uint64_t Val, SDLoc DL, EVT VT, bool isTarget=false, bool isOpaque=false)
void setUnsafeAlgebra(bool b)
Type * getType() const
getType - Return the type of the instruction that generated this call site
SwitchInst - Multiway switch.
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
unsigned getReg() const
getReg - Returns the register number.
StringRef getValueAsString() const
Return the attribute's value as a string.
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
void erase(iterator MBBI)
FunctionLoweringInfo & FuncInfo
FuncInfo - Information about the function as a whole.
SmallVector< MVT, 4 > RegVTs
RegVTs - The value types of the registers.
DILocalVariable * getVariable() const
virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, unsigned) const
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
SDValue getJumpTable(int JTI, EVT VT, bool isTarget=false, unsigned char TargetFlags=0)
void insert(iterator MBBI, MachineBasicBlock *MBB)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
const ARM::ArchExtKind Kind
void setUnusedArgValue(const Value *V, SDValue NewN)
unsigned getParamAlignment(unsigned i) const
Extract the alignment for a call or parameter (0=unknown).
bool isEmptyTy() const
isEmptyTy - Return true if this type is empty, that is, it has no elements or all its elements are em...
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
SDValue getZExtOrTrunc(SDValue Op, SDLoc DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either zero-extending or trunca...
virtual const TargetInstrInfo * getInstrInfo() const
EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
LLVM Value Representation.
FMA - Perform a * b + c with no intermediate rounding step.
SDValue getRegister(unsigned Reg, EVT VT)
static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, const Value *V)
getCopyToPartsVector - Create a series of nodes that contain the specified value split into legal par...
APInt LLVM_ATTRIBUTE_UNUSED_RESULT sextOrTrunc(unsigned width) const
Sign extend or truncate to width.
void init(GCFunctionInfo *gfi, AliasAnalysis &aa, const TargetLibraryInfo *li)
SDValue getEHLabel(SDLoc dl, SDValue Root, MCSymbol *Label)
unsigned getOpcode() const
getOpcode() returns a member of one of the enums like Instruction::Add.
Value * getAddress() const
DbgDeclareInst - This represents the llvm.dbg.declare instruction.
DILocalVariable * getVariable() const
void setDebugLoc(DebugLoc dl)
Set source location info.
SDValue getValueType(EVT)
const Value * getArraySize() const
getArraySize - Get the number of elements allocated.
PREFETCH - This corresponds to a prefetch intrinsic.
uint64_t getTypeSizeInBits(Type *Ty) const
Size examples:
BasicBlockListType::iterator iterator
const TargetLowering & getTargetLoweringInfo() const
const Value * getValue() const
DbgValueInst - This represents the llvm.dbg.value instruction.
InvokeInst - Invoke instruction.
std::vector< CaseBlock > SwitchCases
SwitchCases - Vector of CaseBlock structures used to communicate SwitchInst code generation informati...
uint32_t getEdgeWeight(const BasicBlock *Src, unsigned IndexInSuccessors) const
Get the raw edge weight calculated for the edge.
IterTy arg_begin() const
arg_begin/arg_end - Return iterators corresponding to the actual argument list for a call site...
bool isValidLocationForIntrinsic(const DILocation *DL) const
Check that a location is valid for this variable.
SDValue getSrcValue(const Value *v)
Construct a node to track a Value* through the backend.
DenseMap< const BasicBlock *, MachineBasicBlock * > MBBMap
MBBMap - A mapping from LLVM basic blocks to their machine code entry.
SDValue getControlRoot()
getControlRoot - Similar to getRoot, but instead of flushing all the PendingLoad items, flush all the PendingExports items.
C - The default llvm calling convention, compatible with C.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Convenience struct for specifying and reasoning about fast-math flags.
vt_iterator vt_begin() const
vt_begin / vt_end - Loop over all of the value types that can be represented by values in this regist...
StringRef - Represent a constant reference to a string, i.e.
Garbage collection metadata for a single function.
MachineModuleInfo & getMMI() const
void clearDanglingDebugInfo()
clearDanglingDebugInfo - Clear the dangling debug information map.
unsigned TrapUnreachable
Emit target-specific trap instruction for 'unreachable' IR instructions.
static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, const Value *V)
getCopyFromPartsVector - Create a value that contains the specified legal parts combined into the val...
SDValue getConstantFP(double Val, SDLoc DL, EVT VT, bool isTarget=false)
static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const TargetLowering &TLI)
visitPow - Lower a pow intrinsic.
DenseMap< MachineBasicBlock *, SmallVector< unsigned, 4 > > LPadToCallSiteMap
LPadToCallSiteMap - Map a landing pad to the call site indexes.
unsigned getExceptionSelectorRegister() const
If a physical register, this returns the register that receives the exception typeid on entry to a la...
SDValue getSetCC(SDLoc DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
MVT getVectorElementType() const
static bool isVolatile(Instruction *Inst)
static APInt getNullValue(unsigned numBits)
Get the '0' value.
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val) This corresponds to "store atomic" instruction.
TRUNCATE - Completely drop the high bits.
EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL) const
bool isUIntN(unsigned N, uint64_t x)
isUIntN - Checks if an unsigned integer fits into the given (dynamic) bit width.
Type * getAllocatedType() const
getAllocatedType - Return the type that is being allocated by the instruction.
void setArgumentFrameIndex(const Argument *A, int FI)
setArgumentFrameIndex - Record frame index for the byval argument.
DenseMap< const Constant *, unsigned > ConstantsOut
bool isAlignStack() const
DISubprogram * getSubprogram() const
Get the subprogram for this scope.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
void ComputeUsesVAFloatArgument(const CallInst &I, MachineModuleInfo *MMI)
ComputeUsesVAFloatArgument - Determine if any floating-point values are being passed to this variadic...
unsigned ComputeLinearIndex(Type *Ty, const unsigned *Indices, const unsigned *IndicesEnd, unsigned CurIndex=0)
Compute the linearized index of a member in a nested aggregate/struct/array.
bool isExportableFromCurrentBlock(const Value *V, const BasicBlock *FromBB)
SynchronizationScope getSynchScope() const
Returns whether this cmpxchg is atomic between threads or only within a single thread.
SDDbgValue - Holds the information from a dbg_value node through SDISel.
DbgDeclareInst - This represents the llvm.dbg.declare instruction.
FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2, FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR - Perform various unary floating point operations.
DenseMap< const Value *, unsigned > ValueMap
ValueMap - Since we emit code for the function a basic block at a time, we must remember which virtua...
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
getIntegerVT - Returns the EVT that represents an integer with the given number of bits...
bool isJumpExpensive() const
Return true if Flow Control is an expensive operation that should be avoided.
SmallVector< unsigned, 4 > Regs
Regs - This list holds the registers assigned to the values.
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Value * getPointerOperand()
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const
This callback is invoked for operations that are unsupported by the target, which are registered to u...
MachineInstr::mmo_iterator allocateMemRefsArray(unsigned long Num)
allocateMemRefsArray - Allocate an array to hold MachineMemOperand pointers.
void addSuccessor(MachineBasicBlock *succ, uint32_t weight=0)
addSuccessor - Add succ as a successor of this MachineBasicBlock.
SDValue getAtomicCmpSwap(unsigned Opcode, SDLoc dl, EVT MemVT, SDVTList VTs, SDValue Chain, SDValue Ptr, SDValue Cmp, SDValue Swp, MachinePointerInfo PtrInfo, unsigned Alignment, AtomicOrdering SuccessOrdering, AtomicOrdering FailureOrdering, SynchronizationScope SynchScope)
Gets a node for an atomic cmpxchg op.
Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) This corresponds to "load atomic" instruction.
static MachineOperand CreateFI(int Idx)
void visitBitTestHeader(BitTestBlock &B, MachineBasicBlock *SwitchBB)
visitBitTestHeader - This function emits necessary code to produce value suitable for "bit tests" ...
LocationClass< Ty > location(Ty &L)
const BasicBlock * getParent() const
bool isExportedInst(const Value *V)
isExportedInst - Return true if the specified value is an instruction exported from its block...
virtual AsmOperandInfoVector ParseConstraints(const DataLayout &DL, const TargetRegisterInfo *TRI, ImmutableCallSite CS) const
Split up the constraint string from the inline assembly value into the specific constraints and their...
LLVM_READONLY APFloat minnum(const APFloat &A, const APFloat &B)
Implements IEEE minNum semantics.
static const unsigned LowestSDNodeOrder
Lowest valid SDNodeOrder.
FunctionLoweringInfo * FuncInfo
virtual void LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const
This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but leg...
MVT getSimpleVT() const
getSimpleVT - Return the SimpleValueType held in the specified simple EVT.
SmallVector< int, 16 > getShuffleMask() const
void resolveDanglingDebugInfo(const Value *V, SDValue Val)
static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI)
expandLog - Lower a log intrinsic.
static unsigned getFlagWordForMatchingOp(unsigned InputFlag, unsigned MatchedOperandNo)
getFlagWordForMatchingOp - Augment an existing flag word returned by getFlagWord with information ind...
SDValue getIntPtrConstant(uint64_t Val, SDLoc DL, bool isTarget=false)
bool noNaNs() const
Flag queries.
SDValue getMemIntrinsicNode(unsigned Opcode, SDLoc dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, unsigned Align=0, bool Vol=false, bool ReadMem=true, bool WriteMem=true, unsigned Size=0)
Creates a MemIntrinsicNode that may produce a result and takes a list of operands.
MachineModuleInfo - This class contains meta information specific to a module.
This file describes how to lower LLVM code to machine code.
bool isVoidTy() const
isVoidTy - Return true if this is 'void'.
AllocaInst - an instruction to allocate memory on the stack.
unsigned getLiveInPhysReg(unsigned VReg) const
getLiveInPhysReg - If VReg is a live-in virtual register, return the corresponding live-in physical r...
InsertValueInst - This instruction inserts a struct field of array element value into an aggregate va...
unsigned InitializeRegForValue(const Value *V)
bool empty() const
empty - Check if the string is empty.
unsigned getVectorNumElements() const
getVectorNumElements - Given a vector type, return the number of elements it contains.
static bool InBlock(const Value *V, const BasicBlock *BB)
const Use * const_op_iterator
This class is used to represent ISD::LOAD nodes.
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary...