29 #define DEBUG_TYPE "arm-disassembler"
47 void advanceITState() {
52 bool instrInITBlock() {
53 return !ITStates.empty();
57 bool instrLastInITBlock() {
58 return ITStates.size() == 1;
64 void setITState(
char Firstcond,
char Mask) {
66 unsigned CondBit0 = Firstcond & 1;
67 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
68 unsigned char CCBits =
static_cast<unsigned char>(Firstcond & 0xf);
69 assert(NumTZ <= 3 &&
"Invalid IT mask!");
71 for (
unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
72 bool T = ((Mask >> Pos) & 1) == CondBit0;
74 ITStates.push_back(CCBits);
76 ITStates.push_back(CCBits ^ 1);
78 ITStates.push_back(CCBits);
82 std::vector<unsigned char> ITStates;
94 ~ARMDisassembler()
override {}
109 ~ThumbDisassembler()
override {}
117 mutable ITStatus ITBlock;
119 void UpdateThumbVFPPredicate(
MCInst&)
const;
142 uint64_t
Address,
const void *Decoder);
144 unsigned RegNo, uint64_t
Address,
145 const void *Decoder);
147 unsigned RegNo, uint64_t
Address,
148 const void *Decoder);
150 uint64_t
Address,
const void *Decoder);
152 uint64_t
Address,
const void *Decoder);
154 uint64_t
Address,
const void *Decoder);
156 uint64_t
Address,
const void *Decoder);
158 uint64_t
Address,
const void *Decoder);
160 uint64_t
Address,
const void *Decoder);
162 uint64_t
Address,
const void *Decoder);
166 const void *Decoder);
168 uint64_t
Address,
const void *Decoder);
170 uint64_t
Address,
const void *Decoder);
172 unsigned RegNo, uint64_t
Address,
173 const void *Decoder);
176 uint64_t
Address,
const void *Decoder);
178 uint64_t
Address,
const void *Decoder);
180 uint64_t
Address,
const void *Decoder);
182 uint64_t
Address,
const void *Decoder);
184 uint64_t
Address,
const void *Decoder);
187 uint64_t
Address,
const void *Decoder);
189 uint64_t
Address,
const void *Decoder);
193 const void *Decoder);
195 uint64_t
Address,
const void *Decoder);
197 uint64_t
Address,
const void *Decoder);
199 uint64_t
Address,
const void *Decoder);
201 uint64_t
Address,
const void *Decoder);
206 const void *Decoder);
208 uint64_t
Address,
const void *Decoder);
210 uint64_t
Address,
const void *Decoder);
212 uint64_t
Address,
const void *Decoder);
214 uint64_t
Address,
const void *Decoder);
216 uint64_t
Address,
const void *Decoder);
218 uint64_t
Address,
const void *Decoder);
220 uint64_t
Address,
const void *Decoder);
222 uint64_t
Address,
const void *Decoder);
224 uint64_t
Address,
const void *Decoder);
226 uint64_t
Address,
const void *Decoder);
228 uint64_t
Address,
const void *Decoder);
230 uint64_t
Address,
const void *Decoder);
232 uint64_t
Address,
const void *Decoder);
234 uint64_t
Address,
const void *Decoder);
236 uint64_t
Address,
const void *Decoder);
238 uint64_t
Address,
const void *Decoder);
240 uint64_t
Address,
const void *Decoder);
242 uint64_t
Address,
const void *Decoder);
244 uint64_t
Address,
const void *Decoder);
246 uint64_t
Address,
const void *Decoder);
248 uint64_t
Address,
const void *Decoder);
250 uint64_t
Address,
const void *Decoder);
252 uint64_t
Address,
const void *Decoder);
254 uint64_t
Address,
const void *Decoder);
256 uint64_t
Address,
const void *Decoder);
258 uint64_t
Address,
const void *Decoder);
260 uint64_t
Address,
const void *Decoder);
262 uint64_t
Address,
const void *Decoder);
264 uint64_t
Address,
const void *Decoder);
266 uint64_t
Address,
const void *Decoder);
268 uint64_t
Address,
const void *Decoder);
270 uint64_t
Address,
const void *Decoder);
272 uint64_t
Address,
const void *Decoder);
274 uint64_t
Address,
const void *Decoder);
276 uint64_t
Address,
const void *Decoder);
278 uint64_t
Address,
const void *Decoder);
280 uint64_t
Address,
const void *Decoder);
282 uint64_t
Address,
const void *Decoder);
284 uint64_t
Address,
const void *Decoder);
286 uint64_t
Address,
const void *Decoder);
288 uint64_t
Address,
const void *Decoder);
290 uint64_t
Address,
const void *Decoder);
292 uint64_t
Address,
const void *Decoder);
294 uint64_t
Address,
const void *Decoder);
296 uint64_t
Address,
const void *Decoder);
298 uint64_t
Address,
const void *Decoder);
300 uint64_t
Address,
const void *Decoder);
302 uint64_t
Address,
const void *Decoder);
304 uint64_t
Address,
const void *Decoder);
306 uint64_t
Address,
const void *Decoder);
308 uint64_t
Address,
const void *Decoder);
310 uint64_t
Address,
const void *Decoder);
312 uint64_t
Address,
const void *Decoder);
314 uint64_t
Address,
const void *Decoder);
316 uint64_t
Address,
const void *Decoder);
320 uint64_t
Address,
const void *Decoder);
322 uint64_t
Address,
const void *Decoder);
324 uint64_t
Address,
const void *Decoder);
326 uint64_t
Address,
const void *Decoder);
328 uint64_t
Address,
const void *Decoder);
330 uint64_t
Address,
const void *Decoder);
332 uint64_t
Address,
const void *Decoder);
334 uint64_t
Address,
const void *Decoder);
336 uint64_t
Address,
const void *Decoder);
338 uint64_t
Address,
const void *Decoder);
340 uint64_t
Address,
const void* Decoder);
342 uint64_t
Address,
const void* Decoder);
344 uint64_t
Address,
const void* Decoder);
346 uint64_t
Address,
const void* Decoder);
348 uint64_t
Address,
const void *Decoder);
350 uint64_t
Address,
const void *Decoder);
352 uint64_t
Address,
const void *Decoder);
354 uint64_t
Address,
const void *Decoder);
356 uint64_t
Address,
const void *Decoder);
358 uint64_t
Address,
const void *Decoder);
360 uint64_t
Address,
const void *Decoder);
362 uint64_t
Address,
const void *Decoder);
364 uint64_t
Address,
const void *Decoder);
366 uint64_t
Address,
const void *Decoder);
368 uint64_t
Address,
const void *Decoder);
370 uint64_t
Address,
const void *Decoder);
372 uint64_t
Address,
const void *Decoder);
374 uint64_t
Address,
const void *Decoder);
376 uint64_t
Address,
const void *Decoder);
378 uint64_t
Address,
const void *Decoder);
380 uint64_t
Address,
const void *Decoder);
382 uint64_t
Address,
const void *Decoder);
384 uint64_t
Address,
const void *Decoder);
386 uint64_t
Address,
const void *Decoder);
388 uint64_t
Address,
const void *Decoder);
390 uint64_t
Address,
const void *Decoder);
393 uint64_t
Address,
const void *Decoder);
395 uint64_t
Address,
const void *Decoder);
396 #include "ARMGenDisassemblerTables.inc"
401 return new ARMDisassembler(STI, Ctx);
407 return new ThumbDisassembler(STI, Ctx);
421 uint32_t Cond = (Insn >> 28) & 0xF;
428 default:
return Result;
438 assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
439 "Asked to disassemble an ARM instruction but Subtarget is in Thumb "
443 if (Bytes.
size() < 4) {
450 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
551 MCInst &MI,
const void *Decoder) {
568 const void *Decoder) {
581 for (
unsigned i = 0; i < NumOps; ++i, ++
I) {
582 if (I == MI.
end())
break;
583 if (OpInfo[i].isOptionalDef() && OpInfo[i].
RegClass == ARM::CCRRegClassID) {
584 if (i > 0 && OpInfo[i-1].isPredicate())
continue;
598 ThumbDisassembler::AddThumbPredicate(
MCInst &MI)
const {
616 if (ITBlock.instrInITBlock())
627 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
637 CC = ITBlock.getITCC();
640 if (ITBlock.instrInITBlock())
641 ITBlock.advanceITState();
646 for (
unsigned i = 0; i < NumOps; ++i, ++
I) {
647 if (I == MI.
end())
break;
648 if (OpInfo[i].isPredicate()) {
674 void ThumbDisassembler::UpdateThumbVFPPredicate(
MCInst &MI)
const {
676 CC = ITBlock.getITCC();
677 if (ITBlock.instrInITBlock())
678 ITBlock.advanceITState();
683 for (
unsigned i = 0; i < NumOps; ++i, ++
I) {
684 if (OpInfo[i].isPredicate() ) {
690 I->setReg(ARM::CPSR);
703 assert(STI.getFeatureBits()[ARM::ModeThumb] &&
704 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
707 if (Bytes.
size() < 2) {
712 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0];
717 Check(Result, AddThumbPredicate(MI));
726 bool InITBlock = ITBlock.instrInITBlock();
727 Check(Result, AddThumbPredicate(MI));
740 if (MI.
getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
743 Check(Result, AddThumbPredicate(MI));
752 ITBlock.setITState(Firstcond, Mask);
759 if (Bytes.
size() < 4) {
765 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16);
771 bool InITBlock = ITBlock.instrInITBlock();
772 Check(Result, AddThumbPredicate(MI));
782 Check(Result, AddThumbPredicate(MI));
786 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
792 UpdateThumbVFPPredicate(MI);
805 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
811 Check(Result, AddThumbPredicate(MI));
816 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) {
818 uint32_t NEONLdStInsn = Insn32;
819 NEONLdStInsn &= 0xF0FFFFFF;
820 NEONLdStInsn |= 0x04000000;
825 Check(Result, AddThumbPredicate(MI));
830 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {
832 uint32_t NEONDataInsn = Insn32;
833 NEONDataInsn &= 0xF0FFFFFF;
834 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4;
835 NEONDataInsn |= 0x12000000;
840 Check(Result, AddThumbPredicate(MI));
845 uint32_t NEONCryptoInsn = Insn32;
846 NEONCryptoInsn &= 0xF0FFFFFF;
847 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4;
848 NEONCryptoInsn |= 0x12000000;
857 uint32_t NEONv8Insn = Insn32;
858 NEONv8Insn &= 0xF3FFFFFF;
885 ARM::R0, ARM::R1,
ARM::R2, ARM::R3,
887 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
888 ARM::R12, ARM::SP, ARM::LR, ARM::PC
892 uint64_t Address,
const void *Decoder) {
903 uint64_t Address,
const void *Decoder) {
916 uint64_t Address,
const void *Decoder) {
930 uint64_t Address,
const void *Decoder) {
937 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
938 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
942 uint64_t Address,
const void *Decoder) {
948 if ((RegNo & 1) || RegNo == 0xe)
957 uint64_t Address,
const void *Decoder) {
987 uint64_t Address,
const void *Decoder) {
989 if (RegNo == 13 || RegNo == 15)
996 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
997 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
998 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
999 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
1000 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
1001 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
1002 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
1003 ARM::S28, ARM::S29, ARM::S30, ARM::S31
1007 uint64_t Address,
const void *Decoder) {
1017 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1018 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1019 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
1020 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1021 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1022 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1023 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1024 ARM::D28, ARM::D29, ARM::D30, ARM::D31
1028 uint64_t Address,
const void *Decoder) {
1030 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1032 bool hasD16 = featureBits[ARM::FeatureD16];
1034 if (RegNo > 31 || (hasD16 && RegNo > 15))
1043 uint64_t Address,
const void *Decoder) {
1051 uint64_t Address,
const void *Decoder) {
1058 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1059 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1060 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1061 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1066 uint64_t Address,
const void *Decoder) {
1067 if (RegNo > 31 || (RegNo & 1) != 0)
1077 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1078 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1079 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1080 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1081 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1086 uint64_t Address,
const void *Decoder) {
1096 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1097 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1098 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1099 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1100 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1101 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1102 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1103 ARM::D28_D30, ARM::D29_D31
1109 const void *Decoder) {
1119 uint64_t Address,
const void *Decoder) {
1122 if (Inst.
getOpcode() == ARM::tBcc && Val == 0xE)
1133 uint64_t Address,
const void *Decoder) {
1142 uint64_t Address,
const void *Decoder) {
1145 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1146 unsigned type = fieldFromInstruction(Val, 5, 2);
1147 unsigned imm = fieldFromInstruction(Val, 7, 5);
1172 unsigned Op = Shift | (imm << 3);
1179 uint64_t Address,
const void *Decoder) {
1182 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1183 unsigned type = fieldFromInstruction(Val, 5, 2);
1184 unsigned Rs = fieldFromInstruction(Val, 8, 4);
1214 uint64_t Address,
const void *Decoder) {
1217 bool NeedDisjointWriteback =
false;
1218 unsigned WritebackReg = 0;
1222 case ARM::LDMIA_UPD:
1223 case ARM::LDMDB_UPD:
1224 case ARM::LDMIB_UPD:
1225 case ARM::LDMDA_UPD:
1226 case ARM::t2LDMIA_UPD:
1227 case ARM::t2LDMDB_UPD:
1228 case ARM::t2STMIA_UPD:
1229 case ARM::t2STMDB_UPD:
1230 NeedDisjointWriteback =
true;
1237 for (
unsigned i = 0; i < 16; ++i) {
1238 if (Val & (1 << i)) {
1242 if (NeedDisjointWriteback && WritebackReg == Inst.
end()[-1].getReg())
1251 uint64_t Address,
const void *Decoder) {
1254 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1255 unsigned regs = fieldFromInstruction(Val, 0, 8);
1258 if (regs == 0 || (Vd + regs) > 32) {
1259 regs = Vd + regs > 32 ? 32 - Vd : regs;
1260 regs = std::max( 1u, regs);
1266 for (
unsigned i = 0; i < (regs - 1); ++i) {
1275 uint64_t Address,
const void *Decoder) {
1278 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1279 unsigned regs = fieldFromInstruction(Val, 1, 7);
1282 if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
1283 regs = Vd + regs > 32 ? 32 - Vd : regs;
1284 regs = std::max( 1u, regs);
1291 for (
unsigned i = 0; i < (regs - 1); ++i) {
1300 uint64_t Address,
const void *Decoder) {
1306 unsigned msb = fieldFromInstruction(Val, 5, 5);
1307 unsigned lsb = fieldFromInstruction(Val, 0, 5);
1318 uint32_t msb_mask = 0xFFFFFFFF;
1319 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1320 uint32_t lsb_mask = (1U << lsb) - 1;
1327 uint64_t Address,
const void *Decoder) {
1330 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1331 unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1332 unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1333 unsigned imm = fieldFromInstruction(Insn, 0, 8);
1334 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1335 unsigned U = fieldFromInstruction(Insn, 23, 1);
1338 case ARM::LDC_OFFSET:
1341 case ARM::LDC_OPTION:
1342 case ARM::LDCL_OFFSET:
1344 case ARM::LDCL_POST:
1345 case ARM::LDCL_OPTION:
1346 case ARM::STC_OFFSET:
1349 case ARM::STC_OPTION:
1350 case ARM::STCL_OFFSET:
1352 case ARM::STCL_POST:
1353 case ARM::STCL_OPTION:
1354 case ARM::t2LDC_OFFSET:
1355 case ARM::t2LDC_PRE:
1356 case ARM::t2LDC_POST:
1357 case ARM::t2LDC_OPTION:
1358 case ARM::t2LDCL_OFFSET:
1359 case ARM::t2LDCL_PRE:
1360 case ARM::t2LDCL_POST:
1361 case ARM::t2LDCL_OPTION:
1362 case ARM::t2STC_OFFSET:
1363 case ARM::t2STC_PRE:
1364 case ARM::t2STC_POST:
1365 case ARM::t2STC_OPTION:
1366 case ARM::t2STCL_OFFSET:
1367 case ARM::t2STCL_PRE:
1368 case ARM::t2STCL_POST:
1369 case ARM::t2STCL_OPTION:
1370 if (coproc == 0xA || coproc == 0xB)
1378 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1379 if (featureBits[ARM::HasV8Ops] && (coproc != 14))
1388 case ARM::t2LDC2_OFFSET:
1389 case ARM::t2LDC2L_OFFSET:
1390 case ARM::t2LDC2_PRE:
1391 case ARM::t2LDC2L_PRE:
1392 case ARM::t2STC2_OFFSET:
1393 case ARM::t2STC2L_OFFSET:
1394 case ARM::t2STC2_PRE:
1395 case ARM::t2STC2L_PRE:
1396 case ARM::LDC2_OFFSET:
1397 case ARM::LDC2L_OFFSET:
1399 case ARM::LDC2L_PRE:
1400 case ARM::STC2_OFFSET:
1401 case ARM::STC2L_OFFSET:
1403 case ARM::STC2L_PRE:
1404 case ARM::t2LDC_OFFSET:
1405 case ARM::t2LDCL_OFFSET:
1406 case ARM::t2LDC_PRE:
1407 case ARM::t2LDCL_PRE:
1408 case ARM::t2STC_OFFSET:
1409 case ARM::t2STCL_OFFSET:
1410 case ARM::t2STC_PRE:
1411 case ARM::t2STCL_PRE:
1412 case ARM::LDC_OFFSET:
1413 case ARM::LDCL_OFFSET:
1416 case ARM::STC_OFFSET:
1417 case ARM::STCL_OFFSET:
1423 case ARM::t2LDC2_POST:
1424 case ARM::t2LDC2L_POST:
1425 case ARM::t2STC2_POST:
1426 case ARM::t2STC2L_POST:
1427 case ARM::LDC2_POST:
1428 case ARM::LDC2L_POST:
1429 case ARM::STC2_POST:
1430 case ARM::STC2L_POST:
1431 case ARM::t2LDC_POST:
1432 case ARM::t2LDCL_POST:
1433 case ARM::t2STC_POST:
1434 case ARM::t2STCL_POST:
1436 case ARM::LDCL_POST:
1438 case ARM::STCL_POST:
1449 case ARM::LDC_OFFSET:
1452 case ARM::LDC_OPTION:
1453 case ARM::LDCL_OFFSET:
1455 case ARM::LDCL_POST:
1456 case ARM::LDCL_OPTION:
1457 case ARM::STC_OFFSET:
1460 case ARM::STC_OPTION:
1461 case ARM::STCL_OFFSET:
1463 case ARM::STCL_POST:
1464 case ARM::STCL_OPTION:
1477 uint64_t Address,
const void *Decoder) {
1480 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1481 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1482 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1483 unsigned imm = fieldFromInstruction(Insn, 0, 12);
1484 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1485 unsigned reg = fieldFromInstruction(Insn, 25, 1);
1486 unsigned P = fieldFromInstruction(Insn, 24, 1);
1487 unsigned W = fieldFromInstruction(Insn, 21, 1);
1491 case ARM::STR_POST_IMM:
1492 case ARM::STR_POST_REG:
1493 case ARM::STRB_POST_IMM:
1494 case ARM::STRB_POST_REG:
1495 case ARM::STRT_POST_REG:
1496 case ARM::STRT_POST_IMM:
1497 case ARM::STRBT_POST_REG:
1498 case ARM::STRBT_POST_IMM:
1511 case ARM::LDR_POST_IMM:
1512 case ARM::LDR_POST_REG:
1513 case ARM::LDRB_POST_IMM:
1514 case ARM::LDRB_POST_REG:
1515 case ARM::LDRBT_POST_REG:
1516 case ARM::LDRBT_POST_IMM:
1517 case ARM::LDRT_POST_REG:
1518 case ARM::LDRT_POST_IMM:
1530 if (!fieldFromInstruction(Insn, 23, 1))
1533 bool writeback = (P == 0) || (W == 1);
1534 unsigned idx_mode = 0;
1537 else if (!P && writeback)
1540 if (writeback && (Rn == 15 || Rn == Rt))
1547 switch( fieldFromInstruction(Insn, 5, 2)) {
1563 unsigned amt = fieldFromInstruction(Insn, 7, 5);
1582 uint64_t Address,
const void *Decoder) {
1585 unsigned Rn = fieldFromInstruction(Val, 13, 4);
1586 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1587 unsigned type = fieldFromInstruction(Val, 5, 2);
1588 unsigned imm = fieldFromInstruction(Val, 7, 5);
1589 unsigned U = fieldFromInstruction(Val, 12, 1);
1626 uint64_t Address,
const void *Decoder) {
1629 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1630 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1631 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1632 unsigned type = fieldFromInstruction(Insn, 22, 1);
1633 unsigned imm = fieldFromInstruction(Insn, 8, 4);
1634 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
1635 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1636 unsigned W = fieldFromInstruction(Insn, 21, 1);
1637 unsigned P = fieldFromInstruction(Insn, 24, 1);
1638 unsigned Rt2 = Rt + 1;
1640 bool writeback = (W == 1) | (P == 0);
1646 case ARM::STRD_POST:
1649 case ARM::LDRD_POST:
1658 case ARM::STRD_POST:
1659 if (P == 0 && W == 1)
1662 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1664 if (type && Rm == 15)
1668 if (!type && fieldFromInstruction(Insn, 8, 4))
1673 case ARM::STRH_POST:
1676 if (writeback && (Rn == 15 || Rn == Rt))
1678 if (!type && Rm == 15)
1683 case ARM::LDRD_POST:
1684 if (type && Rn == 15){
1689 if (P == 0 && W == 1)
1691 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1693 if (!type && writeback && Rn == 15)
1695 if (writeback && (Rn == Rt || Rn == Rt2))
1700 case ARM::LDRH_POST:
1701 if (type && Rn == 15){
1708 if (!type && Rm == 15)
1710 if (!type && writeback && (Rn == 15 || Rn == Rt))
1714 case ARM::LDRSH_PRE:
1715 case ARM::LDRSH_POST:
1717 case ARM::LDRSB_PRE:
1718 case ARM::LDRSB_POST:
1719 if (type && Rn == 15){
1724 if (type && (Rt == 15 || (writeback && Rn == Rt)))
1726 if (!type && (Rt == 15 || Rm == 15))
1728 if (!type && writeback && (Rn == 15 || Rn == Rt))
1745 case ARM::STRD_POST:
1748 case ARM::STRH_POST:
1762 case ARM::STRD_POST:
1765 case ARM::LDRD_POST:
1778 case ARM::LDRD_POST:
1781 case ARM::LDRH_POST:
1783 case ARM::LDRSH_PRE:
1784 case ARM::LDRSH_POST:
1786 case ARM::LDRSB_PRE:
1787 case ARM::LDRSB_POST:
1817 uint64_t Address,
const void *Decoder) {
1820 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1821 unsigned mode = fieldFromInstruction(Insn, 23, 2);
1846 uint64_t Address,
const void *Decoder) {
1849 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
1850 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1851 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1852 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1870 uint64_t Address,
const void *Decoder) {
1873 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1874 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1875 unsigned reglist = fieldFromInstruction(Insn, 0, 16);
1883 case ARM::LDMDA_UPD:
1889 case ARM::LDMDB_UPD:
1895 case ARM::LDMIA_UPD:
1901 case ARM::LDMIB_UPD:
1907 case ARM::STMDA_UPD:
1913 case ARM::STMDB_UPD:
1919 case ARM::STMIA_UPD:
1925 case ARM::STMIB_UPD:
1933 if (fieldFromInstruction(Insn, 20, 1) == 0) {
1935 if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
1936 fieldFromInstruction(Insn, 20, 1) == 0))
1960 uint64_t Address,
const void *Decoder) {
1961 unsigned imod = fieldFromInstruction(Insn, 18, 2);
1962 unsigned M = fieldFromInstruction(Insn, 17, 1);
1963 unsigned iflags = fieldFromInstruction(Insn, 6, 3);
1964 unsigned mode = fieldFromInstruction(Insn, 0, 5);
1970 if (fieldFromInstruction(Insn, 5, 1) != 0 ||
1971 fieldFromInstruction(Insn, 16, 1) != 0 ||
1972 fieldFromInstruction(Insn, 20, 8) != 0x10)
1987 }
else if (imod && !M) {
1992 }
else if (!imod && M) {
2007 uint64_t Address,
const void *Decoder) {
2008 unsigned imod = fieldFromInstruction(Insn, 9, 2);
2009 unsigned M = fieldFromInstruction(Insn, 8, 1);
2010 unsigned iflags = fieldFromInstruction(Insn, 5, 3);
2011 unsigned mode = fieldFromInstruction(Insn, 0, 5);
2027 }
else if (imod && !M) {
2032 }
else if (!imod && M) {
2038 int imm = fieldFromInstruction(Insn, 0, 8);
2049 uint64_t Address,
const void *Decoder) {
2052 unsigned Rd = fieldFromInstruction(Insn, 8, 4);
2055 imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
2056 imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
2057 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2058 imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
2073 uint64_t Address,
const void *Decoder) {
2076 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2077 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2080 imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2081 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2100 uint64_t Address,
const void *Decoder) {
2103 unsigned Rd = fieldFromInstruction(Insn, 16, 4);
2104 unsigned Rn = fieldFromInstruction(Insn, 0, 4);
2105 unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2106 unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2107 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2128 uint64_t Address,
const void *Decoder) {
2131 unsigned Pred = fieldFromInstruction(Insn, 28, 4);
2132 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2133 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2149 uint64_t Address,
const void *Decoder) {
2152 unsigned Imm = fieldFromInstruction(Insn, 9, 1);
2157 if (!FeatureBits[ARM::HasV8_1aOps] ||
2158 !FeatureBits[ARM::HasV8Ops])
2163 if (fieldFromInstruction(Insn, 20,12) != 0xf11 ||
2164 fieldFromInstruction(Insn, 4,4) != 0)
2166 if (fieldFromInstruction(Insn, 10,10) != 0 ||
2167 fieldFromInstruction(Insn, 0,4) != 0)
2177 uint64_t Address,
const void *Decoder) {
2180 unsigned add = fieldFromInstruction(Val, 12, 1);
2181 unsigned imm = fieldFromInstruction(Val, 0, 12);
2182 unsigned Rn = fieldFromInstruction(Val, 13, 4);
2187 if (!add) imm *= -1;
2188 if (imm == 0 && !add) imm = INT32_MIN;
2197 uint64_t Address,
const void *Decoder) {
2200 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2201 unsigned U = fieldFromInstruction(Val, 8, 1);
2202 unsigned imm = fieldFromInstruction(Val, 0, 8);
2216 uint64_t Address,
const void *Decoder) {
2222 uint64_t Address,
const void *Decoder) {
2231 unsigned S = fieldFromInstruction(Insn, 26, 1);
2232 unsigned J1 = fieldFromInstruction(Insn, 13, 1);
2233 unsigned J2 = fieldFromInstruction(Insn, 11, 1);
2234 unsigned I1 = !(J1 ^ S);
2235 unsigned I2 = !(J2 ^ S);
2236 unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
2237 unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
2238 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2239 int imm32 = SignExtend32<25>(tmp << 1);
2241 true, 4, Inst, Decoder))
2249 uint64_t Address,
const void *Decoder) {
2252 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2253 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
2257 imm |= fieldFromInstruction(Insn, 24, 1) << 1;
2259 true, 4, Inst, Decoder))
2265 true, 4, Inst, Decoder))
2275 uint64_t Address,
const void *Decoder) {
2278 unsigned Rm = fieldFromInstruction(Val, 0, 4);
2279 unsigned align = fieldFromInstruction(Val, 4, 2);
2292 uint64_t Address,
const void *Decoder) {
2295 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2296 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2297 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2298 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2299 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2300 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2304 case ARM::VLD1q16:
case ARM::VLD1q32:
case ARM::VLD1q64:
case ARM::VLD1q8:
2305 case ARM::VLD1q16wb_fixed:
case ARM::VLD1q16wb_register:
2306 case ARM::VLD1q32wb_fixed:
case ARM::VLD1q32wb_register:
2307 case ARM::VLD1q64wb_fixed:
case ARM::VLD1q64wb_register:
2308 case ARM::VLD1q8wb_fixed:
case ARM::VLD1q8wb_register:
2309 case ARM::VLD2d16:
case ARM::VLD2d32:
case ARM::VLD2d8:
2310 case ARM::VLD2d16wb_fixed:
case ARM::VLD2d16wb_register:
2311 case ARM::VLD2d32wb_fixed:
case ARM::VLD2d32wb_register:
2312 case ARM::VLD2d8wb_fixed:
case ARM::VLD2d8wb_register:
2319 case ARM::VLD2b16wb_fixed:
2320 case ARM::VLD2b16wb_register:
2321 case ARM::VLD2b32wb_fixed:
2322 case ARM::VLD2b32wb_register:
2323 case ARM::VLD2b8wb_fixed:
2324 case ARM::VLD2b8wb_register:
2338 case ARM::VLD3d8_UPD:
2339 case ARM::VLD3d16_UPD:
2340 case ARM::VLD3d32_UPD:
2344 case ARM::VLD4d8_UPD:
2345 case ARM::VLD4d16_UPD:
2346 case ARM::VLD4d32_UPD:
2353 case ARM::VLD3q8_UPD:
2354 case ARM::VLD3q16_UPD:
2355 case ARM::VLD3q32_UPD:
2359 case ARM::VLD4q8_UPD:
2360 case ARM::VLD4q16_UPD:
2361 case ARM::VLD4q32_UPD:
2373 case ARM::VLD3d8_UPD:
2374 case ARM::VLD3d16_UPD:
2375 case ARM::VLD3d32_UPD:
2379 case ARM::VLD4d8_UPD:
2380 case ARM::VLD4d16_UPD:
2381 case ARM::VLD4d32_UPD:
2388 case ARM::VLD3q8_UPD:
2389 case ARM::VLD3q16_UPD:
2390 case ARM::VLD3q32_UPD:
2394 case ARM::VLD4q8_UPD:
2395 case ARM::VLD4q16_UPD:
2396 case ARM::VLD4q32_UPD:
2409 case ARM::VLD4d8_UPD:
2410 case ARM::VLD4d16_UPD:
2411 case ARM::VLD4d32_UPD:
2418 case ARM::VLD4q8_UPD:
2419 case ARM::VLD4q16_UPD:
2420 case ARM::VLD4q32_UPD:
2430 case ARM::VLD1d8wb_fixed:
2431 case ARM::VLD1d16wb_fixed:
2432 case ARM::VLD1d32wb_fixed:
2433 case ARM::VLD1d64wb_fixed:
2434 case ARM::VLD1d8wb_register:
2435 case ARM::VLD1d16wb_register:
2436 case ARM::VLD1d32wb_register:
2437 case ARM::VLD1d64wb_register:
2438 case ARM::VLD1q8wb_fixed:
2439 case ARM::VLD1q16wb_fixed:
2440 case ARM::VLD1q32wb_fixed:
2441 case ARM::VLD1q64wb_fixed:
2442 case ARM::VLD1q8wb_register:
2443 case ARM::VLD1q16wb_register:
2444 case ARM::VLD1q32wb_register:
2445 case ARM::VLD1q64wb_register:
2446 case ARM::VLD1d8Twb_fixed:
2447 case ARM::VLD1d8Twb_register:
2448 case ARM::VLD1d16Twb_fixed:
2449 case ARM::VLD1d16Twb_register:
2450 case ARM::VLD1d32Twb_fixed:
2451 case ARM::VLD1d32Twb_register:
2452 case ARM::VLD1d64Twb_fixed:
2453 case ARM::VLD1d64Twb_register:
2454 case ARM::VLD1d8Qwb_fixed:
2455 case ARM::VLD1d8Qwb_register:
2456 case ARM::VLD1d16Qwb_fixed:
2457 case ARM::VLD1d16Qwb_register:
2458 case ARM::VLD1d32Qwb_fixed:
2459 case ARM::VLD1d32Qwb_register:
2460 case ARM::VLD1d64Qwb_fixed:
2461 case ARM::VLD1d64Qwb_register:
2462 case ARM::VLD2d8wb_fixed:
2463 case ARM::VLD2d16wb_fixed:
2464 case ARM::VLD2d32wb_fixed:
2465 case ARM::VLD2q8wb_fixed:
2466 case ARM::VLD2q16wb_fixed:
2467 case ARM::VLD2q32wb_fixed:
2468 case ARM::VLD2d8wb_register:
2469 case ARM::VLD2d16wb_register:
2470 case ARM::VLD2d32wb_register:
2471 case ARM::VLD2q8wb_register:
2472 case ARM::VLD2q16wb_register:
2473 case ARM::VLD2q32wb_register:
2474 case ARM::VLD2b8wb_fixed:
2475 case ARM::VLD2b16wb_fixed:
2476 case ARM::VLD2b32wb_fixed:
2477 case ARM::VLD2b8wb_register:
2478 case ARM::VLD2b16wb_register:
2479 case ARM::VLD2b32wb_register:
2482 case ARM::VLD3d8_UPD:
2483 case ARM::VLD3d16_UPD:
2484 case ARM::VLD3d32_UPD:
2485 case ARM::VLD3q8_UPD:
2486 case ARM::VLD3q16_UPD:
2487 case ARM::VLD3q32_UPD:
2488 case ARM::VLD4d8_UPD:
2489 case ARM::VLD4d16_UPD:
2490 case ARM::VLD4d32_UPD:
2491 case ARM::VLD4q8_UPD:
2492 case ARM::VLD4q16_UPD:
2493 case ARM::VLD4q32_UPD:
2519 case ARM::VLD1d8wb_fixed:
2520 case ARM::VLD1d16wb_fixed:
2521 case ARM::VLD1d32wb_fixed:
2522 case ARM::VLD1d64wb_fixed:
2523 case ARM::VLD1d8Twb_fixed:
2524 case ARM::VLD1d16Twb_fixed:
2525 case ARM::VLD1d32Twb_fixed:
2526 case ARM::VLD1d64Twb_fixed:
2527 case ARM::VLD1d8Qwb_fixed:
2528 case ARM::VLD1d16Qwb_fixed:
2529 case ARM::VLD1d32Qwb_fixed:
2530 case ARM::VLD1d64Qwb_fixed:
2531 case ARM::VLD1d8wb_register:
2532 case ARM::VLD1d16wb_register:
2533 case ARM::VLD1d32wb_register:
2534 case ARM::VLD1d64wb_register:
2535 case ARM::VLD1q8wb_fixed:
2536 case ARM::VLD1q16wb_fixed:
2537 case ARM::VLD1q32wb_fixed:
2538 case ARM::VLD1q64wb_fixed:
2539 case ARM::VLD1q8wb_register:
2540 case ARM::VLD1q16wb_register:
2541 case ARM::VLD1q32wb_register:
2542 case ARM::VLD1q64wb_register:
2546 if (Rm != 0xD && Rm != 0xF &&
2550 case ARM::VLD2d8wb_fixed:
2551 case ARM::VLD2d16wb_fixed:
2552 case ARM::VLD2d32wb_fixed:
2553 case ARM::VLD2b8wb_fixed:
2554 case ARM::VLD2b16wb_fixed:
2555 case ARM::VLD2b32wb_fixed:
2556 case ARM::VLD2q8wb_fixed:
2557 case ARM::VLD2q16wb_fixed:
2558 case ARM::VLD2q32wb_fixed:
2566 uint64_t Address,
const void *Decoder) {
2567 unsigned type = fieldFromInstruction(Insn, 8, 4);
2568 unsigned align = fieldFromInstruction(Insn, 4, 2);
2573 unsigned load = fieldFromInstruction(Insn, 21, 1);
2579 uint64_t Address,
const void *Decoder) {
2580 unsigned size = fieldFromInstruction(Insn, 6, 2);
2583 unsigned type = fieldFromInstruction(Insn, 8, 4);
2584 unsigned align = fieldFromInstruction(Insn, 4, 2);
2588 unsigned load = fieldFromInstruction(Insn, 21, 1);
2594 uint64_t Address,
const void *Decoder) {
2595 unsigned size = fieldFromInstruction(Insn, 6, 2);
2598 unsigned align = fieldFromInstruction(Insn, 4, 2);
2601 unsigned load = fieldFromInstruction(Insn, 21, 1);
2607 uint64_t Address,
const void *Decoder) {
2608 unsigned size = fieldFromInstruction(Insn, 6, 2);
2611 unsigned load = fieldFromInstruction(Insn, 21, 1);
2617 uint64_t Address,
const void *Decoder) {
2620 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2621 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2622 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2623 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2624 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2625 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2629 case ARM::VST1d8wb_fixed:
2630 case ARM::VST1d16wb_fixed:
2631 case ARM::VST1d32wb_fixed:
2632 case ARM::VST1d64wb_fixed:
2633 case ARM::VST1d8wb_register:
2634 case ARM::VST1d16wb_register:
2635 case ARM::VST1d32wb_register:
2636 case ARM::VST1d64wb_register:
2637 case ARM::VST1q8wb_fixed:
2638 case ARM::VST1q16wb_fixed:
2639 case ARM::VST1q32wb_fixed:
2640 case ARM::VST1q64wb_fixed:
2641 case ARM::VST1q8wb_register:
2642 case ARM::VST1q16wb_register:
2643 case ARM::VST1q32wb_register:
2644 case ARM::VST1q64wb_register:
2645 case ARM::VST1d8Twb_fixed:
2646 case ARM::VST1d16Twb_fixed:
2647 case ARM::VST1d32Twb_fixed:
2648 case ARM::VST1d64Twb_fixed:
2649 case ARM::VST1d8Twb_register:
2650 case ARM::VST1d16Twb_register:
2651 case ARM::VST1d32Twb_register:
2652 case ARM::VST1d64Twb_register:
2653 case ARM::VST1d8Qwb_fixed:
2654 case ARM::VST1d16Qwb_fixed:
2655 case ARM::VST1d32Qwb_fixed:
2656 case ARM::VST1d64Qwb_fixed:
2657 case ARM::VST1d8Qwb_register:
2658 case ARM::VST1d16Qwb_register:
2659 case ARM::VST1d32Qwb_register:
2660 case ARM::VST1d64Qwb_register:
2661 case ARM::VST2d8wb_fixed:
2662 case ARM::VST2d16wb_fixed:
2663 case ARM::VST2d32wb_fixed:
2664 case ARM::VST2d8wb_register:
2665 case ARM::VST2d16wb_register:
2666 case ARM::VST2d32wb_register:
2667 case ARM::VST2q8wb_fixed:
2668 case ARM::VST2q16wb_fixed:
2669 case ARM::VST2q32wb_fixed:
2670 case ARM::VST2q8wb_register:
2671 case ARM::VST2q16wb_register:
2672 case ARM::VST2q32wb_register:
2673 case ARM::VST2b8wb_fixed:
2674 case ARM::VST2b16wb_fixed:
2675 case ARM::VST2b32wb_fixed:
2676 case ARM::VST2b8wb_register:
2677 case ARM::VST2b16wb_register:
2678 case ARM::VST2b32wb_register:
2683 case ARM::VST3d8_UPD:
2684 case ARM::VST3d16_UPD:
2685 case ARM::VST3d32_UPD:
2686 case ARM::VST3q8_UPD:
2687 case ARM::VST3q16_UPD:
2688 case ARM::VST3q32_UPD:
2689 case ARM::VST4d8_UPD:
2690 case ARM::VST4d16_UPD:
2691 case ARM::VST4d32_UPD:
2692 case ARM::VST4q8_UPD:
2693 case ARM::VST4q16_UPD:
2694 case ARM::VST4q32_UPD:
2711 else if (Rm != 0xF) {
2716 case ARM::VST1d8wb_fixed:
2717 case ARM::VST1d16wb_fixed:
2718 case ARM::VST1d32wb_fixed:
2719 case ARM::VST1d64wb_fixed:
2720 case ARM::VST1q8wb_fixed:
2721 case ARM::VST1q16wb_fixed:
2722 case ARM::VST1q32wb_fixed:
2723 case ARM::VST1q64wb_fixed:
2724 case ARM::VST1d8Twb_fixed:
2725 case ARM::VST1d16Twb_fixed:
2726 case ARM::VST1d32Twb_fixed:
2727 case ARM::VST1d64Twb_fixed:
2728 case ARM::VST1d8Qwb_fixed:
2729 case ARM::VST1d16Qwb_fixed:
2730 case ARM::VST1d32Qwb_fixed:
2731 case ARM::VST1d64Qwb_fixed:
2732 case ARM::VST2d8wb_fixed:
2733 case ARM::VST2d16wb_fixed:
2734 case ARM::VST2d32wb_fixed:
2735 case ARM::VST2q8wb_fixed:
2736 case ARM::VST2q16wb_fixed:
2737 case ARM::VST2q32wb_fixed:
2738 case ARM::VST2b8wb_fixed:
2739 case ARM::VST2b16wb_fixed:
2740 case ARM::VST2b32wb_fixed:
2751 case ARM::VST1q16wb_fixed:
2752 case ARM::VST1q16wb_register:
2753 case ARM::VST1q32wb_fixed:
2754 case ARM::VST1q32wb_register:
2755 case ARM::VST1q64wb_fixed:
2756 case ARM::VST1q64wb_register:
2757 case ARM::VST1q8wb_fixed:
2758 case ARM::VST1q8wb_register:
2762 case ARM::VST2d16wb_fixed:
2763 case ARM::VST2d16wb_register:
2764 case ARM::VST2d32wb_fixed:
2765 case ARM::VST2d32wb_register:
2766 case ARM::VST2d8wb_fixed:
2767 case ARM::VST2d8wb_register:
2774 case ARM::VST2b16wb_fixed:
2775 case ARM::VST2b16wb_register:
2776 case ARM::VST2b32wb_fixed:
2777 case ARM::VST2b32wb_register:
2778 case ARM::VST2b8wb_fixed:
2779 case ARM::VST2b8wb_register:
2793 case ARM::VST3d8_UPD:
2794 case ARM::VST3d16_UPD:
2795 case ARM::VST3d32_UPD:
2799 case ARM::VST4d8_UPD:
2800 case ARM::VST4d16_UPD:
2801 case ARM::VST4d32_UPD:
2808 case ARM::VST3q8_UPD:
2809 case ARM::VST3q16_UPD:
2810 case ARM::VST3q32_UPD:
2814 case ARM::VST4q8_UPD:
2815 case ARM::VST4q16_UPD:
2816 case ARM::VST4q32_UPD:
2829 case ARM::VST3d8_UPD:
2830 case ARM::VST3d16_UPD:
2831 case ARM::VST3d32_UPD:
2835 case ARM::VST4d8_UPD:
2836 case ARM::VST4d16_UPD:
2837 case ARM::VST4d32_UPD:
2844 case ARM::VST3q8_UPD:
2845 case ARM::VST3q16_UPD:
2846 case ARM::VST3q32_UPD:
2850 case ARM::VST4q8_UPD:
2851 case ARM::VST4q16_UPD:
2852 case ARM::VST4q32_UPD:
2865 case ARM::VST4d8_UPD:
2866 case ARM::VST4d16_UPD:
2867 case ARM::VST4d32_UPD:
2874 case ARM::VST4q8_UPD:
2875 case ARM::VST4q16_UPD:
2876 case ARM::VST4q32_UPD:
2888 uint64_t Address,
const void *Decoder) {
2891 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2892 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2893 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2894 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2895 unsigned align = fieldFromInstruction(Insn, 4, 1);
2896 unsigned size = fieldFromInstruction(Insn, 6, 2);
2898 if (size == 0 && align == 1)
2900 align *= (1 <<
size);
2903 case ARM::VLD1DUPq16:
case ARM::VLD1DUPq32:
case ARM::VLD1DUPq8:
2904 case ARM::VLD1DUPq16wb_fixed:
case ARM::VLD1DUPq16wb_register:
2905 case ARM::VLD1DUPq32wb_fixed:
case ARM::VLD1DUPq32wb_register:
2906 case ARM::VLD1DUPq8wb_fixed:
case ARM::VLD1DUPq8wb_register:
2927 if (Rm != 0xD && Rm != 0xF &&
2935 uint64_t Address,
const void *Decoder) {
2938 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2939 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2940 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2941 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2942 unsigned align = fieldFromInstruction(Insn, 4, 1);
2943 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
2947 case ARM::VLD2DUPd16:
case ARM::VLD2DUPd32:
case ARM::VLD2DUPd8:
2948 case ARM::VLD2DUPd16wb_fixed:
case ARM::VLD2DUPd16wb_register:
2949 case ARM::VLD2DUPd32wb_fixed:
case ARM::VLD2DUPd32wb_register:
2950 case ARM::VLD2DUPd8wb_fixed:
case ARM::VLD2DUPd8wb_register:
2954 case ARM::VLD2DUPd16x2:
case ARM::VLD2DUPd32x2:
case ARM::VLD2DUPd8x2:
2955 case ARM::VLD2DUPd16x2wb_fixed:
case ARM::VLD2DUPd16x2wb_register:
2956 case ARM::VLD2DUPd32x2wb_fixed:
case ARM::VLD2DUPd32x2wb_register:
2957 case ARM::VLD2DUPd8x2wb_fixed:
case ARM::VLD2DUPd8x2wb_register:
2974 if (Rm != 0xD && Rm != 0xF) {
2983 uint64_t Address,
const void *Decoder) {
2986 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2987 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2988 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2989 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2990 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3009 else if (Rm != 0xF) {
3018 uint64_t Address,
const void *Decoder) {
3021 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3022 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3023 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3024 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3025 unsigned size = fieldFromInstruction(Insn, 6, 2);
3026 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3027 unsigned align = fieldFromInstruction(Insn, 4, 1);
3061 else if (Rm != 0xF) {
3071 uint64_t Address,
const void *Decoder) {
3074 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3075 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3076 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3077 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3078 imm |= fieldFromInstruction(Insn, 24, 1) << 7;
3079 imm |= fieldFromInstruction(Insn, 8, 4) << 8;
3080 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3081 unsigned Q = fieldFromInstruction(Insn, 6, 1);
3094 case ARM::VORRiv4i16:
3095 case ARM::VORRiv2i32:
3096 case ARM::VBICiv4i16:
3097 case ARM::VBICiv2i32:
3101 case ARM::VORRiv8i16:
3102 case ARM::VORRiv4i32:
3103 case ARM::VBICiv8i16:
3104 case ARM::VBICiv4i32:
3116 uint64_t Address,
const void *Decoder) {
3119 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3120 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3121 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3122 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3123 unsigned size = fieldFromInstruction(Insn, 18, 2);
3135 uint64_t Address,
const void *Decoder) {
3141 uint64_t Address,
const void *Decoder) {
3147 uint64_t Address,
const void *Decoder) {
3153 uint64_t Address,
const void *Decoder) {
3159 uint64_t Address,
const void *Decoder) {
3162 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3163 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3164 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3165 Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
3166 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3167 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3168 unsigned op = fieldFromInstruction(Insn, 6, 1);
3195 uint64_t Address,
const void *Decoder) {
3198 unsigned dst = fieldFromInstruction(Insn, 8, 3);
3199 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3219 uint64_t Address,
const void *Decoder) {
3221 true, 2, Inst, Decoder))
3227 uint64_t Address,
const void *Decoder) {
3229 true, 4, Inst, Decoder))
3235 uint64_t Address,
const void *Decoder) {
3237 true, 2, Inst, Decoder))
3243 uint64_t Address,
const void *Decoder) {
3246 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3247 unsigned Rm = fieldFromInstruction(Val, 3, 3);
3258 uint64_t Address,
const void *Decoder) {
3261 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3262 unsigned imm = fieldFromInstruction(Val, 3, 5);
3272 uint64_t Address,
const void *Decoder) {
3273 unsigned imm = Val << 2;
3282 uint64_t Address,
const void *Decoder) {
3290 uint64_t Address,
const void *Decoder) {
3293 unsigned Rn = fieldFromInstruction(Val, 6, 4);
3294 unsigned Rm = fieldFromInstruction(Val, 2, 4);
3295 unsigned imm = fieldFromInstruction(Val, 0, 2);
3318 uint64_t Address,
const void *Decoder) {
3321 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3322 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3325 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3327 bool hasMP = featureBits[ARM::FeatureMP];
3328 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3382 if (!hasV7Ops || !hasMP)
3390 unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
3391 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
3392 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
3400 uint64_t Address,
const void* Decoder) {
3403 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3404 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3405 unsigned U = fieldFromInstruction(Insn, 9, 1);
3406 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3409 unsigned add = fieldFromInstruction(Insn, 9, 1);
3412 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3414 bool hasMP = featureBits[ARM::FeatureMP];
3415 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3425 case ARM::t2LDRSBi8:
3431 case ARM::t2LDRSHi8:
3448 case ARM::t2LDRSHi8:
3454 case ARM::t2LDRSBi8:
3470 if (!hasV7Ops || !hasMP)
3484 uint64_t Address,
const void* Decoder) {
3487 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3488 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3489 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3493 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3495 bool hasMP = featureBits[ARM::FeatureMP];
3496 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3503 case ARM::t2LDRHi12:
3506 case ARM::t2LDRSHi12:
3509 case ARM::t2LDRBi12:
3512 case ARM::t2LDRSBi12:
3529 case ARM::t2LDRSHi12:
3531 case ARM::t2LDRHi12:
3534 case ARM::t2LDRSBi12:
3549 case ARM::t2PLDWi12:
3550 if (!hasV7Ops || !hasMP)
3564 uint64_t Address,
const void* Decoder) {
3567 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3568 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3569 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3603 uint64_t Address,
const void* Decoder) {
3606 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3607 unsigned U = fieldFromInstruction(Insn, 23, 1);
3608 int imm = fieldFromInstruction(Insn, 0, 12);
3611 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3613 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3617 case ARM::t2LDRBpci:
3618 case ARM::t2LDRHpci:
3621 case ARM::t2LDRSBpci:
3624 case ARM::t2LDRSHpci:
3656 uint64_t Address,
const void *Decoder) {
3660 int imm = Val & 0xFF;
3662 if (!(Val & 0x100)) imm *= -1;
3670 uint64_t Address,
const void *Decoder) {
3673 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3674 unsigned imm = fieldFromInstruction(Val, 0, 9);
3685 uint64_t Address,
const void *Decoder) {
3688 unsigned Rn = fieldFromInstruction(Val, 8, 4);
3689 unsigned imm = fieldFromInstruction(Val, 0, 8);
3700 uint64_t Address,
const void *Decoder) {
3701 int imm = Val & 0xFF;
3704 else if (!(Val & 0x100))
3713 uint64_t Address,
const void *Decoder) {
3716 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3717 unsigned imm = fieldFromInstruction(Val, 0, 9);
3759 uint64_t Address,
const void *Decoder) {
3762 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3763 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3764 unsigned addr = fieldFromInstruction(Insn, 0, 8);
3765 addr |= fieldFromInstruction(Insn, 9, 1) << 8;
3767 unsigned load = fieldFromInstruction(Insn, 20, 1);
3771 case ARM::t2LDR_PRE:
3772 case ARM::t2LDR_POST:
3775 case ARM::t2LDRB_PRE:
3776 case ARM::t2LDRB_POST:
3779 case ARM::t2LDRH_PRE:
3780 case ARM::t2LDRH_POST:
3783 case ARM::t2LDRSB_PRE:
3784 case ARM::t2LDRSB_POST:
3790 case ARM::t2LDRSH_PRE:
3791 case ARM::t2LDRSH_POST:
3820 uint64_t Address,
const void *Decoder) {
3823 unsigned Rn = fieldFromInstruction(Val, 13, 4);
3824 unsigned imm = fieldFromInstruction(Val, 0, 12);
3829 case ARM::t2STRBi12:
3830 case ARM::t2STRHi12:
3846 uint64_t Address,
const void *Decoder) {
3847 unsigned imm = fieldFromInstruction(Insn, 0, 7);
3857 uint64_t Address,
const void *Decoder) {
3861 unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
3862 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
3869 }
else if (Inst.
getOpcode() == ARM::tADDspr) {
3870 unsigned Rm = fieldFromInstruction(Insn, 3, 4);
3882 uint64_t Address,
const void *Decoder) {
3883 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
3884 unsigned flags = fieldFromInstruction(Insn, 0, 3);
3893 uint64_t Address,
const void *Decoder) {
3895 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3896 unsigned add = fieldFromInstruction(Insn, 4, 1);
3906 uint64_t Address,
const void *Decoder) {
3914 unsigned S = (Val >> 23) & 1;
3915 unsigned J1 = (Val >> 22) & 1;
3916 unsigned J2 = (Val >> 21) & 1;
3917 unsigned I1 = !(J1 ^ S);
3918 unsigned I2 = !(J2 ^ S);
3919 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3920 int imm32 = SignExtend32<25>(tmp << 1);
3923 (Address & ~2u) + imm32 + 4,
3924 true, 4, Inst, Decoder))
3930 uint64_t Address,
const void *Decoder) {
3931 if (Val == 0xA || Val == 0xB)
3935 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3937 if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15))
3946 uint64_t Address,
const void *Decoder) {
3949 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3950 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3962 uint64_t Address,
const void *Decoder) {
3965 unsigned pred = fieldFromInstruction(Insn, 22, 4);
3966 if (pred == 0xE || pred == 0xF) {
3967 unsigned opc = fieldFromInstruction(Insn, 4, 28);
3982 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3986 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
3987 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
3988 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
3989 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
3990 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
4004 uint64_t Address,
const void *Decoder) {
4005 unsigned ctrl = fieldFromInstruction(Val, 10, 2);
4007 unsigned byte = fieldFromInstruction(Val, 8, 2);
4008 unsigned imm = fieldFromInstruction(Val, 0, 8);
4025 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
4026 unsigned rot = fieldFromInstruction(Val, 7, 5);
4027 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
4036 uint64_t Address,
const void *Decoder){
4038 true, 2, Inst, Decoder))
4044 uint64_t Address,
const void *Decoder){
4052 unsigned S = (Val >> 23) & 1;
4053 unsigned J1 = (Val >> 22) & 1;
4054 unsigned J2 = (Val >> 21) & 1;
4055 unsigned I1 = !(J1 ^ S);
4056 unsigned I2 = !(J2 ^ S);
4057 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
4058 int imm32 = SignExtend32<25>(tmp << 1);
4061 true, 4, Inst, Decoder))
4067 uint64_t Address,
const void *Decoder) {
4076 uint64_t Address,
const void *Decoder) {
4085 uint64_t Address,
const void *Decoder) {
4088 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4090 if (FeatureBits[ARM::FeatureMClass]) {
4091 unsigned ValLow = Val & 0xff;
4110 if (!(FeatureBits[ARM::HasV7Ops]))
4119 unsigned Mask = fieldFromInstruction(Val, 10, 2);
4120 if (!(FeatureBits[ARM::HasV7Ops])) {
4133 if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
4134 (!(FeatureBits[ARM::FeatureDSPThumb2]) && (Mask & 1)))
4148 uint64_t Address,
const void *Decoder) {
4150 unsigned R = fieldFromInstruction(Val, 5, 1);
4151 unsigned SysM = fieldFromInstruction(Val, 0, 5);
4157 if (SysM == 0x7 || SysM == 0xf || SysM == 0x18 || SysM == 0x19 ||
4158 SysM == 0x1a || SysM == 0x1b)
4161 if (SysM != 0xe && SysM != 0x10 && SysM != 0x12 && SysM != 0x14 &&
4162 SysM != 0x16 && SysM != 0x1c && SysM != 0x1e)
4171 uint64_t Address,
const void *Decoder) {
4174 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4175 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4176 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4192 uint64_t Address,
const void *Decoder){
4195 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4196 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
4197 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4198 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4203 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
4217 uint64_t Address,
const void *Decoder) {
4220 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4221 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4222 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4223 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4224 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4225 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4242 uint64_t Address,
const void *Decoder) {
4245 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4246 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4247 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4248 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4249 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4250 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4251 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4270 uint64_t Address,
const void *Decoder) {
4273 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4274 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4275 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4276 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4277 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4278 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4295 uint64_t Address,
const void *Decoder) {
4298 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4299 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4300 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4301 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4302 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4303 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4320 uint64_t Address,
const void *Decoder) {
4323 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4324 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4325 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4326 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4327 unsigned size = fieldFromInstruction(Insn, 10, 2);
4335 if (fieldFromInstruction(Insn, 4, 1))
4337 index = fieldFromInstruction(Insn, 5, 3);
4340 if (fieldFromInstruction(Insn, 5, 1))
4342 index = fieldFromInstruction(Insn, 6, 2);
4343 if (fieldFromInstruction(Insn, 4, 1))
4347 if (fieldFromInstruction(Insn, 6, 1))
4349 index = fieldFromInstruction(Insn, 7, 1);
4351 switch (fieldFromInstruction(Insn, 4, 2)) {
4387 uint64_t Address,
const void *Decoder) {
4390 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4391 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4392 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4393 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4394 unsigned size = fieldFromInstruction(Insn, 10, 2);
4402 if (fieldFromInstruction(Insn, 4, 1))
4404 index = fieldFromInstruction(Insn, 5, 3);
4407 if (fieldFromInstruction(Insn, 5, 1))
4409 index = fieldFromInstruction(Insn, 6, 2);
4410 if (fieldFromInstruction(Insn, 4, 1))
4414 if (fieldFromInstruction(Insn, 6, 1))
4416 index = fieldFromInstruction(Insn, 7, 1);
4418 switch (fieldFromInstruction(Insn, 4, 2)) {
4453 uint64_t Address,
const void *Decoder) {
4456 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4457 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4458 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4459 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4460 unsigned size = fieldFromInstruction(Insn, 10, 2);
4469 index = fieldFromInstruction(Insn, 5, 3);
4470 if (fieldFromInstruction(Insn, 4, 1))
4474 index = fieldFromInstruction(Insn, 6, 2);
4475 if (fieldFromInstruction(Insn, 4, 1))
4477 if (fieldFromInstruction(Insn, 5, 1))
4481 if (fieldFromInstruction(Insn, 5, 1))
4483 index = fieldFromInstruction(Insn, 7, 1);
4484 if (fieldFromInstruction(Insn, 4, 1) != 0)
4486 if (fieldFromInstruction(Insn, 6, 1))
4520 uint64_t Address,
const void *Decoder) {
4523 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4524 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4525 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4526 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4527 unsigned size = fieldFromInstruction(Insn, 10, 2);
4536 index = fieldFromInstruction(Insn, 5, 3);
4537 if (fieldFromInstruction(Insn, 4, 1))
4541 index = fieldFromInstruction(Insn, 6, 2);
4542 if (fieldFromInstruction(Insn, 4, 1))
4544 if (fieldFromInstruction(Insn, 5, 1))
4548 if (fieldFromInstruction(Insn, 5, 1))
4550 index = fieldFromInstruction(Insn, 7, 1);
4551 if (fieldFromInstruction(Insn, 4, 1) != 0)
4553 if (fieldFromInstruction(Insn, 6, 1))
4584 uint64_t Address,
const void *Decoder) {
4587 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4588 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4589 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4590 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4591 unsigned size = fieldFromInstruction(Insn, 10, 2);
4600 if (fieldFromInstruction(Insn, 4, 1))
4602 index = fieldFromInstruction(Insn, 5, 3);
4605 if (fieldFromInstruction(Insn, 4, 1))
4607 index = fieldFromInstruction(Insn, 6, 2);
4608 if (fieldFromInstruction(Insn, 5, 1))
4612 if (fieldFromInstruction(Insn, 4, 2))
4614 index = fieldFromInstruction(Insn, 7, 1);
4615 if (fieldFromInstruction(Insn, 6, 1))
4654 uint64_t Address,
const void *Decoder) {
4657 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4658 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4659 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4660 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4661 unsigned size = fieldFromInstruction(Insn, 10, 2);
4670 if (fieldFromInstruction(Insn, 4, 1))
4672 index = fieldFromInstruction(Insn, 5, 3);
4675 if (fieldFromInstruction(Insn, 4, 1))
4677 index = fieldFromInstruction(Insn, 6, 2);
4678 if (fieldFromInstruction(Insn, 5, 1))
4682 if (fieldFromInstruction(Insn, 4, 2))
4684 index = fieldFromInstruction(Insn, 7, 1);
4685 if (fieldFromInstruction(Insn, 6, 1))
4718 uint64_t Address,
const void *Decoder) {
4721 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4722 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4723 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4724 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4725 unsigned size = fieldFromInstruction(Insn, 10, 2);
4734 if (fieldFromInstruction(Insn, 4, 1))
4736 index = fieldFromInstruction(Insn, 5, 3);
4739 if (fieldFromInstruction(Insn, 4, 1))
4741 index = fieldFromInstruction(Insn, 6, 2);
4742 if (fieldFromInstruction(Insn, 5, 1))
4746 switch (fieldFromInstruction(Insn, 4, 2)) {
4752 align = 4 << fieldFromInstruction(Insn, 4, 2);
break;
4755 index = fieldFromInstruction(Insn, 7, 1);
4756 if (fieldFromInstruction(Insn, 6, 1))
4799 uint64_t Address,
const void *Decoder) {
4802 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4803 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4804 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4805 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4806 unsigned size = fieldFromInstruction(Insn, 10, 2);
4815 if (fieldFromInstruction(Insn, 4, 1))
4817 index = fieldFromInstruction(Insn, 5, 3);
4820 if (fieldFromInstruction(Insn, 4, 1))
4822 index = fieldFromInstruction(Insn, 6, 2);
4823 if (fieldFromInstruction(Insn, 5, 1))
4827 switch (fieldFromInstruction(Insn, 4, 2)) {
4833 align = 4 << fieldFromInstruction(Insn, 4, 2);
break;
4836 index = fieldFromInstruction(Insn, 7, 1);
4837 if (fieldFromInstruction(Insn, 6, 1))
4871 uint64_t Address,
const void *Decoder) {
4873 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4874 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4875 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4876 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4877 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4879 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4897 uint64_t Address,
const void *Decoder) {
4899 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4900 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4901 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4902 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4903 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4905 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4923 uint64_t Address,
const void *Decoder) {
4925 unsigned pred = fieldFromInstruction(Insn, 4, 4);
4926 unsigned mask = fieldFromInstruction(Insn, 0, 4);
4943 uint64_t Address,
const void *Decoder) {
4946 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4947 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4948 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4949 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4950 unsigned W = fieldFromInstruction(Insn, 21, 1);
4951 unsigned U = fieldFromInstruction(Insn, 23, 1);
4952 unsigned P = fieldFromInstruction(Insn, 24, 1);
4953 bool writeback = (W == 1) | (P == 0);
4955 addr |= (U << 8) | (Rn << 9);
4957 if (writeback && (Rn == Rt || Rn == Rt2))
4980 uint64_t Address,
const void *Decoder) {
4983 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4984 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4985 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4986 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4987 unsigned W = fieldFromInstruction(Insn, 21, 1);
4988 unsigned U = fieldFromInstruction(Insn, 23, 1);
4989 unsigned P = fieldFromInstruction(Insn, 24, 1);
4990 bool writeback = (W == 1) | (P == 0);
4992 addr |= (U << 8) | (Rn << 9);
4994 if (writeback && (Rn == Rt || Rn == Rt2))
5014 uint64_t Address,
const void *Decoder) {
5015 unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
5016 unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
5019 unsigned Val = fieldFromInstruction(Insn, 0, 8);
5020 Val |= fieldFromInstruction(Insn, 12, 3) << 8;
5021 Val |= fieldFromInstruction(Insn, 26, 1) << 11;
5030 const void *Decoder) {
5040 uint64_t Address,
const void *Decoder) {
5041 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5042 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
5043 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5044 unsigned pred = fieldFromInstruction(Insn, 28, 4);
5051 if (Rt == Rn || Rn == Rt2)
5067 uint64_t Address,
const void *Decoder) {
5068 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5069 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5070 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5071 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5072 unsigned imm = fieldFromInstruction(Insn, 16, 6);
5073 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5074 unsigned op = fieldFromInstruction(Insn, 5, 1);
5079 if (!(imm & 0x38) && cmode == 0xF) {
5097 uint64_t Address,
const void *Decoder) {
5098 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5099 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5100 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5101 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5102 unsigned imm = fieldFromInstruction(Insn, 16, 6);
5103 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5104 unsigned op = fieldFromInstruction(Insn, 5, 1);
5109 if (!(imm & 0x38) && cmode == 0xF) {
5127 uint64_t Address,
const void *Decoder) {
5130 unsigned Rn = fieldFromInstruction(Val, 16, 4);
5131 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5132 unsigned Rm = fieldFromInstruction(Val, 0, 4);
5133 Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
5134 unsigned Cond = fieldFromInstruction(Val, 28, 4);
5136 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)
5154 uint64_t Address,
const void *Decoder) {
5158 unsigned CRm = fieldFromInstruction(Val, 0, 4);
5159 unsigned opc1 = fieldFromInstruction(Val, 4, 4);
5160 unsigned cop = fieldFromInstruction(Val, 8, 4);
5161 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5162 unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
5164 if ((cop & ~0x1) == 0xa)
static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static MCDisassembler * createARMDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static const uint16_t GPRPairDecoderTable[]
static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static MCDisassembler * createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
DecodeStatus
Ternary decode status.
static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
Superclass for all disassemblers.
static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Describe properties that are true of each instruction in the target description file.
static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static unsigned getAM5Opc(AddrOpc Opc, unsigned char Offset)
getAM5Opc - This function encodes the addrmode5 opc field.
static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static const uint16_t GPRDecoderTable[]
static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
MCDisassembler::DecodeStatus DecodeStatus
static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static MCOperand createReg(unsigned Reg)
static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static const uint16_t DPairSpacedDecoderTable[]
const MCInstrDesc ARMInsts[]
static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Number of individual test Apply this number of consecutive mutations to each input exit after the first new interesting input is found the minimized corpus is saved into the first input directory Number of jobs to run If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Context object for machine code objects.
static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
unsigned getReg() const
Returns the register number.
int decodeInstruction(InternalInstruction *insn, byteReader_t reader, const void *readerArg, dlog_t logger, void *loggerArg, const void *miiArg, uint64_t startLoc, DisassemblerMode mode)
Decode one instruction and store the decoding results in a buffer provided by the consumer...
static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static bool add(uint64_t *dest, const uint64_t *x, const uint64_t *y, unsigned len)
This function adds the integer array x to the integer array Y and places the result in dest...
static const uint16_t SPRDecoderTable[]
static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
size_t size() const
size - Get the array size.
iterator insert(iterator I, const MCOperand &Op)
static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Instances of this class represent a single low-level machine instruction.
static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
unsigned short NumOperands
static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
const MCSubtargetInfo & getSubtargetInfo() const
static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static const uint16_t DPRDecoderTable[]
static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO, unsigned IdxMode=0)
static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static const uint16_t DPairDecoderTable[]
static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static const uint16_t QPRDecoderTable[]
static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, uint64_t Address, raw_ostream &OS, raw_ostream &CS, uint32_t Insn, DecodeStatus Result)
static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t InstSize) const
void setOpcode(unsigned Op)
static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
Promote Memory to Register
static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn, uint64_t Adddress, const void *Decoder)
static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static void AddThumb1SBit(MCInst &MI, bool InITBlock)
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
void LLVMInitializeARMDisassembler()
static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
unsigned getOpcode() const
Target - Wrapper for Target specific information.
static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
std::error_code Check(std::error_code Err)
static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
MCSubtargetInfo - Generic base class for all target subtargets.
static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static bool isBranch(unsigned Opcode)
static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, uint64_t Address, const void *Decoder)
LLVM Value Representation.
static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
const MCOperandInfo * OpInfo
static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
This class implements an extremely fast bulk output stream that can only output to a stream...
static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
void addOperand(const MCOperand &Op)
static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, const void *Decoder)
tryAddingPcLoadReferenceComment - trys to add a comment as to what is being referenced by a load inst...
static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
This holds information about one operand of a machine instruction, indicating the register class for ...
static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder)
void tryAddingPcLoadReferenceComment(int64_t Value, uint64_t Address) const
static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static MCOperand createImm(int64_t Val)
static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
const MCOperand & getOperand(unsigned i) const
static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, bool isBranch, uint64_t InstSize, MCInst &MI, const void *Decoder)
tryAddingSymbolicOperand - trys to add a symbolic operand in place of the immediate Value in the MCIn...
static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)