14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
15 #define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
21 #define GET_INSTRINFO_HEADER
22 #include "PPCGenInstrInfo.inc"
72 unsigned SrcReg,
bool isKill,
int FrameIdx,
75 bool &NonRI,
bool &SpillsVRS)
const;
77 unsigned DestReg,
int FrameIdx,
80 bool &NonRI,
bool &SpillsVRS)
const;
81 virtual void anchor();
100 unsigned *PredCost =
nullptr)
const override;
105 unsigned UseIdx)
const override;
107 SDNode *DefNode,
unsigned DefIdx,
108 SDNode *UseNode,
unsigned UseIdx)
const override {
109 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx,
115 unsigned DefIdx)
const override {
123 unsigned &SrcReg,
unsigned &DstReg,
124 unsigned &SubIdx)
const override;
135 unsigned &SrcOpIdx2)
const override;
145 bool AllowModify)
const override;
153 unsigned,
unsigned,
int &,
int &,
int &)
const override;
156 unsigned TrueReg,
unsigned FalseReg)
const override;
160 unsigned DestReg,
unsigned SrcReg,
161 bool KillSrc)
const override;
185 unsigned NumCycles,
unsigned ExtraPredCycles,
191 unsigned NumT,
unsigned ExtraT,
193 unsigned NumF,
unsigned ExtraF,
199 &Probability)
const override {
220 std::vector<MachineOperand> &Pred)
const override;
228 unsigned &SrcReg,
unsigned &SrcReg2,
229 int &Mask,
int &
Value)
const override;
232 unsigned SrcReg,
unsigned SrcReg2,
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override
bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
PPC970_Cracked - This instruction is cracked into two pieces, requiring two dispatch pipes to be avai...
bool ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, unsigned Reg, MachineRegisterInfo *MRI) const override
These are the various PPC970 execution unit pipelines.
ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
CreateTargetHazardRecognizer - Return the hazard recognizer to use for this target when scheduling th...
MachineInstr * commuteInstruction(MachineInstr *MI, bool NewMI) const override
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, const BranchProbability &Probability) const override
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
Provide an instruction scheduling machine model to CodeGen passes.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Reg
All possible values of the reg field in the ModR/M byte.
bool hasLowDefLatency(const TargetSchedModel &SchedModel, const MachineInstr *DefMI, unsigned DefIdx) const override
bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
bool PredicateInstruction(MachineInstr *MI, ArrayRef< MachineOperand > Pred) const override
PPCInstrInfo(PPCSubtarget &STI)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const override
Itinerary data supplied by a subtarget to be used by a target.
bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override
Instances of this class represent a single low-level machine instruction.
PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that an instruction is issued to...
PPC970_First - This instruction starts a new dispatch group, so it will always be the first one in th...
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
bool isUnpredicatedTerminator(const MachineInstr *MI) const override
bundle_iterator - MachineBasicBlock iterator that automatically skips over MIs that are inside bundle...
PPC970_Single - This instruction starts a new dispatch group and terminates it, so it will be the sol...
bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const override
unsigned RemoveBranch(MachineBasicBlock &MBB) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const override
bool isPredicable(MachineInstr *MI) const override
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr *MI, unsigned *PredCost=nullptr) const override
int getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const override
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override
bool isPredicated(const MachineInstr *MI) const override
Represents one node in the SelectionDAG.
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
void getNoopForMachoTarget(MCInst &NopInst) const override
getNoopForMachoTarget - Return the noop instruction to use for a noop.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
TargetSubtargetInfo - Generic base class for all target subtargets.
const PPCRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Representation of each machine instruction.
int getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const override
unsigned GetInstSizeInBytes(const MachineInstr *MI) const
GetInstSize - Return the number of bytes of code the specified instruction may be.
LLVM Value Representation.
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, DebugLoc DL) const override
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer to use for this target when ...
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool DefinesPredicate(MachineInstr *MI, std::vector< MachineOperand > &Pred) const override
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, const BranchProbability &Probability) const override