LLVM  3.7.0
PHIElimination.cpp
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1 //===-- PhiElimination.cpp - Eliminate PHI nodes by inserting copies ------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This pass eliminates machine instruction PHI nodes by inserting copy
11 // instructions. This destroys SSA information, but is the desired input for
12 // some register allocators.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "llvm/CodeGen/Passes.h"
17 #include "PHIEliminationUtils.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallPtrSet.h"
20 #include "llvm/ADT/Statistic.h"
28 #include "llvm/IR/Function.h"
30 #include "llvm/Support/Compiler.h"
31 #include "llvm/Support/Debug.h"
35 #include <algorithm>
36 using namespace llvm;
37 
38 #define DEBUG_TYPE "phielim"
39 
40 static cl::opt<bool>
41 DisableEdgeSplitting("disable-phi-elim-edge-splitting", cl::init(false),
42  cl::Hidden, cl::desc("Disable critical edge splitting "
43  "during PHI elimination"));
44 
45 static cl::opt<bool>
46 SplitAllCriticalEdges("phi-elim-split-all-critical-edges", cl::init(false),
47  cl::Hidden, cl::desc("Split all critical edges during "
48  "PHI elimination"));
49 
51  "no-phi-elim-live-out-early-exit", cl::init(false), cl::Hidden,
52  cl::desc("Do not use an early exit if isLiveOutPastPHIs returns true."));
53 
54 namespace {
55  class PHIElimination : public MachineFunctionPass {
56  MachineRegisterInfo *MRI; // Machine register information
57  LiveVariables *LV;
58  LiveIntervals *LIS;
59 
60  public:
61  static char ID; // Pass identification, replacement for typeid
62  PHIElimination() : MachineFunctionPass(ID) {
64  }
65 
66  bool runOnMachineFunction(MachineFunction &Fn) override;
67  void getAnalysisUsage(AnalysisUsage &AU) const override;
68 
69  private:
70  /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions
71  /// in predecessor basic blocks.
72  ///
73  bool EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB);
74  void LowerPHINode(MachineBasicBlock &MBB,
75  MachineBasicBlock::iterator LastPHIIt);
76 
77  /// analyzePHINodes - Gather information about the PHI nodes in
78  /// here. In particular, we want to map the number of uses of a virtual
79  /// register which is used in a PHI node. We map that to the BB the
80  /// vreg is coming from. This is used later to determine when the vreg
81  /// is killed in the BB.
82  ///
83  void analyzePHINodes(const MachineFunction& Fn);
84 
85  /// Split critical edges where necessary for good coalescer performance.
86  bool SplitPHIEdges(MachineFunction &MF, MachineBasicBlock &MBB,
87  MachineLoopInfo *MLI);
88 
89  // These functions are temporary abstractions around LiveVariables and
90  // LiveIntervals, so they can go away when LiveVariables does.
91  bool isLiveIn(unsigned Reg, const MachineBasicBlock *MBB);
92  bool isLiveOutPastPHIs(unsigned Reg, const MachineBasicBlock *MBB);
93 
94  typedef std::pair<unsigned, unsigned> BBVRegPair;
95  typedef DenseMap<BBVRegPair, unsigned> VRegPHIUse;
96 
97  VRegPHIUse VRegPHIUseCount;
98 
99  // Defs of PHI sources which are implicit_def.
101 
102  // Map reusable lowered PHI node -> incoming join register.
103  typedef DenseMap<MachineInstr*, unsigned,
104  MachineInstrExpressionTrait> LoweredPHIMap;
105  LoweredPHIMap LoweredPHIs;
106  };
107 }
108 
109 STATISTIC(NumLowered, "Number of phis lowered");
110 STATISTIC(NumCriticalEdgesSplit, "Number of critical edges split");
111 STATISTIC(NumReused, "Number of reused lowered phis");
112 
113 char PHIElimination::ID = 0;
115 
116 INITIALIZE_PASS_BEGIN(PHIElimination, "phi-node-elimination",
117  "Eliminate PHI nodes for register allocation",
118  false, false)
120 INITIALIZE_PASS_END(PHIElimination, "phi-node-elimination",
121  "Eliminate PHI nodes for register allocation", false, false)
122 
123 void PHIElimination::getAnalysisUsage(AnalysisUsage &AU) const {
124  AU.addPreserved<LiveVariables>();
125  AU.addPreserved<SlotIndexes>();
126  AU.addPreserved<LiveIntervals>();
127  AU.addPreserved<MachineDominatorTree>();
128  AU.addPreserved<MachineLoopInfo>();
130 }
131 
132 bool PHIElimination::runOnMachineFunction(MachineFunction &MF) {
133  MRI = &MF.getRegInfo();
134  LV = getAnalysisIfAvailable<LiveVariables>();
135  LIS = getAnalysisIfAvailable<LiveIntervals>();
136 
137  bool Changed = false;
138 
139  // This pass takes the function out of SSA form.
140  MRI->leaveSSA();
141 
142  // Split critical edges to help the coalescer. This does not yet support
143  // updating LiveIntervals, so we disable it.
144  if (!DisableEdgeSplitting && (LV || LIS)) {
145  MachineLoopInfo *MLI = getAnalysisIfAvailable<MachineLoopInfo>();
146  for (auto &MBB : MF)
147  Changed |= SplitPHIEdges(MF, MBB, MLI);
148  }
149 
150  // Populate VRegPHIUseCount
151  analyzePHINodes(MF);
152 
153  // Eliminate PHI instructions by inserting copies into predecessor blocks.
154  for (auto &MBB : MF)
155  Changed |= EliminatePHINodes(MF, MBB);
156 
157  // Remove dead IMPLICIT_DEF instructions.
158  for (MachineInstr *DefMI : ImpDefs) {
159  unsigned DefReg = DefMI->getOperand(0).getReg();
160  if (MRI->use_nodbg_empty(DefReg)) {
161  if (LIS)
162  LIS->RemoveMachineInstrFromMaps(DefMI);
163  DefMI->eraseFromParent();
164  }
165  }
166 
167  // Clean up the lowered PHI instructions.
168  for (LoweredPHIMap::iterator I = LoweredPHIs.begin(), E = LoweredPHIs.end();
169  I != E; ++I) {
170  if (LIS)
171  LIS->RemoveMachineInstrFromMaps(I->first);
172  MF.DeleteMachineInstr(I->first);
173  }
174 
175  LoweredPHIs.clear();
176  ImpDefs.clear();
177  VRegPHIUseCount.clear();
178 
179  return Changed;
180 }
181 
182 /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in
183 /// predecessor basic blocks.
184 ///
185 bool PHIElimination::EliminatePHINodes(MachineFunction &MF,
186  MachineBasicBlock &MBB) {
187  if (MBB.empty() || !MBB.front().isPHI())
188  return false; // Quick exit for basic blocks without PHIs.
189 
190  // Get an iterator to the first instruction after the last PHI node (this may
191  // also be the end of the basic block).
192  MachineBasicBlock::iterator LastPHIIt =
193  std::prev(MBB.SkipPHIsAndLabels(MBB.begin()));
194 
195  while (MBB.front().isPHI())
196  LowerPHINode(MBB, LastPHIIt);
197 
198  return true;
199 }
200 
201 /// isImplicitlyDefined - Return true if all defs of VirtReg are implicit-defs.
202 /// This includes registers with no defs.
203 static bool isImplicitlyDefined(unsigned VirtReg,
204  const MachineRegisterInfo *MRI) {
205  for (MachineInstr &DI : MRI->def_instructions(VirtReg))
206  if (!DI.isImplicitDef())
207  return false;
208  return true;
209 }
210 
211 /// isSourceDefinedByImplicitDef - Return true if all sources of the phi node
212 /// are implicit_def's.
214  const MachineRegisterInfo *MRI) {
215  for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2)
216  if (!isImplicitlyDefined(MPhi->getOperand(i).getReg(), MRI))
217  return false;
218  return true;
219 }
220 
221 
222 /// LowerPHINode - Lower the PHI node at the top of the specified block,
223 ///
224 void PHIElimination::LowerPHINode(MachineBasicBlock &MBB,
225  MachineBasicBlock::iterator LastPHIIt) {
226  ++NumLowered;
227 
228  MachineBasicBlock::iterator AfterPHIsIt = std::next(LastPHIIt);
229 
230  // Unlink the PHI node from the basic block, but don't delete the PHI yet.
231  MachineInstr *MPhi = MBB.remove(MBB.begin());
232 
233  unsigned NumSrcs = (MPhi->getNumOperands() - 1) / 2;
234  unsigned DestReg = MPhi->getOperand(0).getReg();
235  assert(MPhi->getOperand(0).getSubReg() == 0 && "Can't handle sub-reg PHIs");
236  bool isDead = MPhi->getOperand(0).isDead();
237 
238  // Create a new register for the incoming PHI arguments.
239  MachineFunction &MF = *MBB.getParent();
240  unsigned IncomingReg = 0;
241  bool reusedIncoming = false; // Is IncomingReg reused from an earlier PHI?
242 
243  // Insert a register to register copy at the top of the current block (but
244  // after any remaining phi nodes) which copies the new incoming register
245  // into the phi node destination.
247  if (isSourceDefinedByImplicitDef(MPhi, MRI))
248  // If all sources of a PHI node are implicit_def, just emit an
249  // implicit_def instead of a copy.
250  BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
251  TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
252  else {
253  // Can we reuse an earlier PHI node? This only happens for critical edges,
254  // typically those created by tail duplication.
255  unsigned &entry = LoweredPHIs[MPhi];
256  if (entry) {
257  // An identical PHI node was already lowered. Reuse the incoming register.
258  IncomingReg = entry;
259  reusedIncoming = true;
260  ++NumReused;
261  DEBUG(dbgs() << "Reusing " << PrintReg(IncomingReg) << " for " << *MPhi);
262  } else {
263  const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
264  entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
265  }
266  BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
267  TII->get(TargetOpcode::COPY), DestReg)
268  .addReg(IncomingReg);
269  }
270 
271  // Update live variable information if there is any.
272  if (LV) {
273  MachineInstr *PHICopy = std::prev(AfterPHIsIt);
274 
275  if (IncomingReg) {
276  LiveVariables::VarInfo &VI = LV->getVarInfo(IncomingReg);
277 
278  // Increment use count of the newly created virtual register.
279  LV->setPHIJoin(IncomingReg);
280 
281  // When we are reusing the incoming register, it may already have been
282  // killed in this block. The old kill will also have been inserted at
283  // AfterPHIsIt, so it appears before the current PHICopy.
284  if (reusedIncoming)
285  if (MachineInstr *OldKill = VI.findKill(&MBB)) {
286  DEBUG(dbgs() << "Remove old kill from " << *OldKill);
287  LV->removeVirtualRegisterKilled(IncomingReg, OldKill);
288  DEBUG(MBB.dump());
289  }
290 
291  // Add information to LiveVariables to know that the incoming value is
292  // killed. Note that because the value is defined in several places (once
293  // each for each incoming block), the "def" block and instruction fields
294  // for the VarInfo is not filled in.
295  LV->addVirtualRegisterKilled(IncomingReg, PHICopy);
296  }
297 
298  // Since we are going to be deleting the PHI node, if it is the last use of
299  // any registers, or if the value itself is dead, we need to move this
300  // information over to the new copy we just inserted.
301  LV->removeVirtualRegistersKilled(MPhi);
302 
303  // If the result is dead, update LV.
304  if (isDead) {
305  LV->addVirtualRegisterDead(DestReg, PHICopy);
306  LV->removeVirtualRegisterDead(DestReg, MPhi);
307  }
308  }
309 
310  // Update LiveIntervals for the new copy or implicit def.
311  if (LIS) {
312  MachineInstr *NewInstr = std::prev(AfterPHIsIt);
313  SlotIndex DestCopyIndex = LIS->InsertMachineInstrInMaps(NewInstr);
314 
315  SlotIndex MBBStartIndex = LIS->getMBBStartIdx(&MBB);
316  if (IncomingReg) {
317  // Add the region from the beginning of MBB to the copy instruction to
318  // IncomingReg's live interval.
319  LiveInterval &IncomingLI = LIS->createEmptyInterval(IncomingReg);
320  VNInfo *IncomingVNI = IncomingLI.getVNInfoAt(MBBStartIndex);
321  if (!IncomingVNI)
322  IncomingVNI = IncomingLI.getNextValue(MBBStartIndex,
323  LIS->getVNInfoAllocator());
324  IncomingLI.addSegment(LiveInterval::Segment(MBBStartIndex,
325  DestCopyIndex.getRegSlot(),
326  IncomingVNI));
327  }
328 
329  LiveInterval &DestLI = LIS->getInterval(DestReg);
330  assert(DestLI.begin() != DestLI.end() &&
331  "PHIs should have nonempty LiveIntervals.");
332  if (DestLI.endIndex().isDead()) {
333  // A dead PHI's live range begins and ends at the start of the MBB, but
334  // the lowered copy, which will still be dead, needs to begin and end at
335  // the copy instruction.
336  VNInfo *OrigDestVNI = DestLI.getVNInfoAt(MBBStartIndex);
337  assert(OrigDestVNI && "PHI destination should be live at block entry.");
338  DestLI.removeSegment(MBBStartIndex, MBBStartIndex.getDeadSlot());
339  DestLI.createDeadDef(DestCopyIndex.getRegSlot(),
340  LIS->getVNInfoAllocator());
341  DestLI.removeValNo(OrigDestVNI);
342  } else {
343  // Otherwise, remove the region from the beginning of MBB to the copy
344  // instruction from DestReg's live interval.
345  DestLI.removeSegment(MBBStartIndex, DestCopyIndex.getRegSlot());
346  VNInfo *DestVNI = DestLI.getVNInfoAt(DestCopyIndex.getRegSlot());
347  assert(DestVNI && "PHI destination should be live at its definition.");
348  DestVNI->def = DestCopyIndex.getRegSlot();
349  }
350  }
351 
352  // Adjust the VRegPHIUseCount map to account for the removal of this PHI node.
353  for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2)
354  --VRegPHIUseCount[BBVRegPair(MPhi->getOperand(i+1).getMBB()->getNumber(),
355  MPhi->getOperand(i).getReg())];
356 
357  // Now loop over all of the incoming arguments, changing them to copy into the
358  // IncomingReg register in the corresponding predecessor basic block.
359  SmallPtrSet<MachineBasicBlock*, 8> MBBsInsertedInto;
360  for (int i = NumSrcs - 1; i >= 0; --i) {
361  unsigned SrcReg = MPhi->getOperand(i*2+1).getReg();
362  unsigned SrcSubReg = MPhi->getOperand(i*2+1).getSubReg();
363  bool SrcUndef = MPhi->getOperand(i*2+1).isUndef() ||
364  isImplicitlyDefined(SrcReg, MRI);
365  assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
366  "Machine PHI Operands must all be virtual registers!");
367 
368  // Get the MachineBasicBlock equivalent of the BasicBlock that is the source
369  // path the PHI.
370  MachineBasicBlock &opBlock = *MPhi->getOperand(i*2+2).getMBB();
371 
372  // Check to make sure we haven't already emitted the copy for this block.
373  // This can happen because PHI nodes may have multiple entries for the same
374  // basic block.
375  if (!MBBsInsertedInto.insert(&opBlock).second)
376  continue; // If the copy has already been emitted, we're done.
377 
378  // Find a safe location to insert the copy, this may be the first terminator
379  // in the block (or end()).
380  MachineBasicBlock::iterator InsertPos =
381  findPHICopyInsertPoint(&opBlock, &MBB, SrcReg);
382 
383  // Insert the copy.
384  MachineInstr *NewSrcInstr = nullptr;
385  if (!reusedIncoming && IncomingReg) {
386  if (SrcUndef) {
387  // The source register is undefined, so there is no need for a real
388  // COPY, but we still need to ensure joint dominance by defs.
389  // Insert an IMPLICIT_DEF instruction.
390  NewSrcInstr = BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(),
392  IncomingReg);
393 
394  // Clean up the old implicit-def, if there even was one.
395  if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg))
396  if (DefMI->isImplicitDef())
397  ImpDefs.insert(DefMI);
398  } else {
399  NewSrcInstr = BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(),
400  TII->get(TargetOpcode::COPY), IncomingReg)
401  .addReg(SrcReg, 0, SrcSubReg);
402  }
403  }
404 
405  // We only need to update the LiveVariables kill of SrcReg if this was the
406  // last PHI use of SrcReg to be lowered on this CFG edge and it is not live
407  // out of the predecessor. We can also ignore undef sources.
408  if (LV && !SrcUndef &&
409  !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)] &&
410  !LV->isLiveOut(SrcReg, opBlock)) {
411  // We want to be able to insert a kill of the register if this PHI (aka,
412  // the copy we just inserted) is the last use of the source value. Live
413  // variable analysis conservatively handles this by saying that the value
414  // is live until the end of the block the PHI entry lives in. If the value
415  // really is dead at the PHI copy, there will be no successor blocks which
416  // have the value live-in.
417 
418  // Okay, if we now know that the value is not live out of the block, we
419  // can add a kill marker in this block saying that it kills the incoming
420  // value!
421 
422  // In our final twist, we have to decide which instruction kills the
423  // register. In most cases this is the copy, however, terminator
424  // instructions at the end of the block may also use the value. In this
425  // case, we should mark the last such terminator as being the killing
426  // block, not the copy.
427  MachineBasicBlock::iterator KillInst = opBlock.end();
428  MachineBasicBlock::iterator FirstTerm = opBlock.getFirstTerminator();
429  for (MachineBasicBlock::iterator Term = FirstTerm;
430  Term != opBlock.end(); ++Term) {
431  if (Term->readsRegister(SrcReg))
432  KillInst = Term;
433  }
434 
435  if (KillInst == opBlock.end()) {
436  // No terminator uses the register.
437 
438  if (reusedIncoming || !IncomingReg) {
439  // We may have to rewind a bit if we didn't insert a copy this time.
440  KillInst = FirstTerm;
441  while (KillInst != opBlock.begin()) {
442  --KillInst;
443  if (KillInst->isDebugValue())
444  continue;
445  if (KillInst->readsRegister(SrcReg))
446  break;
447  }
448  } else {
449  // We just inserted this copy.
450  KillInst = std::prev(InsertPos);
451  }
452  }
453  assert(KillInst->readsRegister(SrcReg) && "Cannot find kill instruction");
454 
455  // Finally, mark it killed.
456  LV->addVirtualRegisterKilled(SrcReg, KillInst);
457 
458  // This vreg no longer lives all of the way through opBlock.
459  unsigned opBlockNum = opBlock.getNumber();
460  LV->getVarInfo(SrcReg).AliveBlocks.reset(opBlockNum);
461  }
462 
463  if (LIS) {
464  if (NewSrcInstr) {
465  LIS->InsertMachineInstrInMaps(NewSrcInstr);
466  LIS->addSegmentToEndOfBlock(IncomingReg, NewSrcInstr);
467  }
468 
469  if (!SrcUndef &&
470  !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)]) {
471  LiveInterval &SrcLI = LIS->getInterval(SrcReg);
472 
473  bool isLiveOut = false;
474  for (MachineBasicBlock::succ_iterator SI = opBlock.succ_begin(),
475  SE = opBlock.succ_end(); SI != SE; ++SI) {
476  SlotIndex startIdx = LIS->getMBBStartIdx(*SI);
477  VNInfo *VNI = SrcLI.getVNInfoAt(startIdx);
478 
479  // Definitions by other PHIs are not truly live-in for our purposes.
480  if (VNI && VNI->def != startIdx) {
481  isLiveOut = true;
482  break;
483  }
484  }
485 
486  if (!isLiveOut) {
487  MachineBasicBlock::iterator KillInst = opBlock.end();
488  MachineBasicBlock::iterator FirstTerm = opBlock.getFirstTerminator();
489  for (MachineBasicBlock::iterator Term = FirstTerm;
490  Term != opBlock.end(); ++Term) {
491  if (Term->readsRegister(SrcReg))
492  KillInst = Term;
493  }
494 
495  if (KillInst == opBlock.end()) {
496  // No terminator uses the register.
497 
498  if (reusedIncoming || !IncomingReg) {
499  // We may have to rewind a bit if we didn't just insert a copy.
500  KillInst = FirstTerm;
501  while (KillInst != opBlock.begin()) {
502  --KillInst;
503  if (KillInst->isDebugValue())
504  continue;
505  if (KillInst->readsRegister(SrcReg))
506  break;
507  }
508  } else {
509  // We just inserted this copy.
510  KillInst = std::prev(InsertPos);
511  }
512  }
513  assert(KillInst->readsRegister(SrcReg) &&
514  "Cannot find kill instruction");
515 
516  SlotIndex LastUseIndex = LIS->getInstructionIndex(KillInst);
517  SrcLI.removeSegment(LastUseIndex.getRegSlot(),
518  LIS->getMBBEndIdx(&opBlock));
519  }
520  }
521  }
522  }
523 
524  // Really delete the PHI instruction now, if it is not in the LoweredPHIs map.
525  if (reusedIncoming || !IncomingReg) {
526  if (LIS)
527  LIS->RemoveMachineInstrFromMaps(MPhi);
528  MF.DeleteMachineInstr(MPhi);
529  }
530 }
531 
532 /// analyzePHINodes - Gather information about the PHI nodes in here. In
533 /// particular, we want to map the number of uses of a virtual register which is
534 /// used in a PHI node. We map that to the BB the vreg is coming from. This is
535 /// used later to determine when the vreg is killed in the BB.
536 ///
537 void PHIElimination::analyzePHINodes(const MachineFunction& MF) {
538  for (const auto &MBB : MF)
539  for (const auto &BBI : MBB) {
540  if (!BBI.isPHI())
541  break;
542  for (unsigned i = 1, e = BBI.getNumOperands(); i != e; i += 2)
543  ++VRegPHIUseCount[BBVRegPair(BBI.getOperand(i+1).getMBB()->getNumber(),
544  BBI.getOperand(i).getReg())];
545  }
546 }
547 
548 bool PHIElimination::SplitPHIEdges(MachineFunction &MF,
549  MachineBasicBlock &MBB,
550  MachineLoopInfo *MLI) {
551  if (MBB.empty() || !MBB.front().isPHI() || MBB.isLandingPad())
552  return false; // Quick exit for basic blocks without PHIs.
553 
554  const MachineLoop *CurLoop = MLI ? MLI->getLoopFor(&MBB) : nullptr;
555  bool IsLoopHeader = CurLoop && &MBB == CurLoop->getHeader();
556 
557  bool Changed = false;
558  for (MachineBasicBlock::iterator BBI = MBB.begin(), BBE = MBB.end();
559  BBI != BBE && BBI->isPHI(); ++BBI) {
560  for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
561  unsigned Reg = BBI->getOperand(i).getReg();
562  MachineBasicBlock *PreMBB = BBI->getOperand(i+1).getMBB();
563  // Is there a critical edge from PreMBB to MBB?
564  if (PreMBB->succ_size() == 1)
565  continue;
566 
567  // Avoid splitting backedges of loops. It would introduce small
568  // out-of-line blocks into the loop which is very bad for code placement.
569  if (PreMBB == &MBB && !SplitAllCriticalEdges)
570  continue;
571  const MachineLoop *PreLoop = MLI ? MLI->getLoopFor(PreMBB) : nullptr;
572  if (IsLoopHeader && PreLoop == CurLoop && !SplitAllCriticalEdges)
573  continue;
574 
575  // LV doesn't consider a phi use live-out, so isLiveOut only returns true
576  // when the source register is live-out for some other reason than a phi
577  // use. That means the copy we will insert in PreMBB won't be a kill, and
578  // there is a risk it may not be coalesced away.
579  //
580  // If the copy would be a kill, there is no need to split the edge.
581  bool ShouldSplit = isLiveOutPastPHIs(Reg, PreMBB);
582  if (!ShouldSplit && !NoPhiElimLiveOutEarlyExit)
583  continue;
584  if (ShouldSplit) {
585  DEBUG(dbgs() << PrintReg(Reg) << " live-out before critical edge BB#"
586  << PreMBB->getNumber() << " -> BB#" << MBB.getNumber()
587  << ": " << *BBI);
588  }
589 
590  // If Reg is not live-in to MBB, it means it must be live-in to some
591  // other PreMBB successor, and we can avoid the interference by splitting
592  // the edge.
593  //
594  // If Reg *is* live-in to MBB, the interference is inevitable and a copy
595  // is likely to be left after coalescing. If we are looking at a loop
596  // exiting edge, split it so we won't insert code in the loop, otherwise
597  // don't bother.
598  ShouldSplit = ShouldSplit && !isLiveIn(Reg, &MBB);
599 
600  // Check for a loop exiting edge.
601  if (!ShouldSplit && CurLoop != PreLoop) {
602  DEBUG({
603  dbgs() << "Split wouldn't help, maybe avoid loop copies?\n";
604  if (PreLoop) dbgs() << "PreLoop: " << *PreLoop;
605  if (CurLoop) dbgs() << "CurLoop: " << *CurLoop;
606  });
607  // This edge could be entering a loop, exiting a loop, or it could be
608  // both: Jumping directly form one loop to the header of a sibling
609  // loop.
610  // Split unless this edge is entering CurLoop from an outer loop.
611  ShouldSplit = PreLoop && !PreLoop->contains(CurLoop);
612  }
613  if (!ShouldSplit && !SplitAllCriticalEdges)
614  continue;
615  if (!PreMBB->SplitCriticalEdge(&MBB, this)) {
616  DEBUG(dbgs() << "Failed to split critical edge.\n");
617  continue;
618  }
619  Changed = true;
620  ++NumCriticalEdgesSplit;
621  }
622  }
623  return Changed;
624 }
625 
626 bool PHIElimination::isLiveIn(unsigned Reg, const MachineBasicBlock *MBB) {
627  assert((LV || LIS) &&
628  "isLiveIn() requires either LiveVariables or LiveIntervals");
629  if (LIS)
630  return LIS->isLiveInToMBB(LIS->getInterval(Reg), MBB);
631  else
632  return LV->isLiveIn(Reg, *MBB);
633 }
634 
635 bool PHIElimination::isLiveOutPastPHIs(unsigned Reg,
636  const MachineBasicBlock *MBB) {
637  assert((LV || LIS) &&
638  "isLiveOutPastPHIs() requires either LiveVariables or LiveIntervals");
639  // LiveVariables considers uses in PHIs to be in the predecessor basic block,
640  // so that a register used only in a PHI is not live out of the block. In
641  // contrast, LiveIntervals considers uses in PHIs to be on the edge rather than
642  // in the predecessor basic block, so that a register used only in a PHI is live
643  // out of the block.
644  if (LIS) {
645  const LiveInterval &LI = LIS->getInterval(Reg);
646  for (const MachineBasicBlock *SI : MBB->successors())
647  if (LI.liveAt(LIS->getMBBStartIdx(SI)))
648  return true;
649  return false;
650  } else {
651  return LV->isLiveOut(Reg, *MBB);
652  }
653 }
unsigned succ_size() const
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
SlotIndex def
The index of the defining instruction.
Definition: LiveInterval.h:53
STATISTIC(NumFunctions,"Total number of functions")
MachineBasicBlock * getMBB() const
int getNumber() const
getNumber - MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a M...
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:588
iterator getFirstTerminator()
getFirstTerminator - returns an iterator to the first terminator instruction of this basic block...
bool isDead() const
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
MachineBasicBlock::iterator findPHICopyInsertPoint(MachineBasicBlock *MBB, MachineBasicBlock *SuccMBB, unsigned SrcReg)
findPHICopyInsertPoint - Find a safe place in MBB to insert a copy from SrcReg when following the CFG...
phi node Eliminate PHI nodes for register false
static cl::opt< bool > DisableEdgeSplitting("disable-phi-elim-edge-splitting", cl::init(false), cl::Hidden, cl::desc("Disable critical edge splitting ""during PHI elimination"))
VarInfo - This represents the regions where a virtual register is live in the program.
Definition: LiveVariables.h:79
unsigned SplitAllCriticalEdges(Function &F, const CriticalEdgeSplittingOptions &Options=CriticalEdgeSplittingOptions())
VNInfo - Value Number Information.
Definition: LiveInterval.h:45
static bool isImplicitlyDefined(unsigned VirtReg, const MachineRegisterInfo *MRI)
isImplicitlyDefined - Return true if all defs of VirtReg are implicit-defs.
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
Definition: LiveInterval.h:392
BlockT * getHeader() const
Definition: LoopInfo.h:96
Special DenseMapInfo traits to compare MachineInstr* by value of the instruction rather than by point...
iterator_range< succ_iterator > successors()
COPY - Target-independent register copy.
Definition: TargetOpcodes.h:86
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:70
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
bool isPHI() const
Definition: MachineInstr.h:757
iterator end()
Definition: LiveInterval.h:206
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:75
const TargetRegisterClass * getRegClass(unsigned Reg) const
getRegClass - Return the register class of the specified virtual register.
std::vector< MachineBasicBlock * >::iterator succ_iterator
Reg
All possible values of the reg field in the ModR/M byte.
MachineBasicBlock * SplitCriticalEdge(MachineBasicBlock *Succ, Pass *P)
SplitCriticalEdge - Split the critical edge from this block to the given successor block...
bool isUndef() const
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
Definition: SlotIndexes.h:262
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:271
PrintReg - Helper class for printing registers on a raw_ostream.
bool isDead() const
isDead - Returns true if this is a dead def kill slot.
Definition: SlotIndexes.h:239
SlotIndexes pass.
Definition: SlotIndexes.h:334
iterator addSegment(Segment S)
Add the specified Segment to this range, merging segments as appropriate.
static cl::opt< bool > NoPhiElimLiveOutEarlyExit("no-phi-elim-live-out-early-exit", cl::init(false), cl::Hidden, cl::desc("Do not use an early exit if isLiveOutPastPHIs returns true."))
TargetInstrInfo - Interface to description of machine instruction set.
char & PHIEliminationID
PHIElimination - This pass eliminates machine instruction PHI nodes by inserting copy instructions...
IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
Definition: TargetOpcodes.h:52
MachineLoop * getLoopFor(const MachineBasicBlock *BB) const
getLoopFor - Return the inner most loop that BB lives in.
bundle_iterator< MachineInstr, instr_iterator > iterator
void removeValNo(VNInfo *ValNo)
removeValNo - Remove all the segments defined by the specified value#.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:325
iterator SkipPHIsAndLabels(iterator I)
SkipPHIsAndLabels - Return the first instruction in MBB after I that is not a PHI or a label...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:264
Represent the analysis usage information of a pass.
bool contains(const LoopT *L) const
contains - Return true if the specified loop is contained within in this loop.
Definition: LoopInfo.h:105
for(unsigned i=0, e=MI->getNumOperands();i!=e;++i)
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
unsigned getSubReg() const
void DeleteMachineInstr(MachineInstr *MI)
DeleteMachineInstr - Delete the given MachineInstr.
bool liveAt(SlotIndex index) const
Definition: LiveInterval.h:372
void initializePHIEliminationPass(PassRegistry &)
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
phi node elimination
void removeSegment(SlotIndex Start, SlotIndex End, bool RemoveDeadValNo=false)
Remove the specified segment from this range.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
Definition: SmallPtrSet.h:299
MachineInstr * remove(MachineInstr *I)
Remove the unbundled instruction from the instruction list without deleting it.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:123
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:238
INITIALIZE_PASS_BEGIN(PHIElimination,"phi-node-elimination","Eliminate PHI nodes for register allocation", false, false) INITIALIZE_PASS_END(PHIElimination
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
phi node Eliminate PHI nodes for register allocation
MachineInstr * findKill(const MachineBasicBlock *MBB) const
findKill - Find a kill instruction in MBB. Return NULL if none is found.
Representation of each machine instruction.
Definition: MachineInstr.h:51
bool isLandingPad() const
isLandingPad - Returns true if the block is a landing pad.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
VNInfo * createDeadDef(SlotIndex Def, VNInfo::Allocator &VNInfoAllocator)
createDeadDef - Make sure the range has a value defined at Def.
SlotIndex endIndex() const
endNumber - return the maximum point of the range of the whole, exclusive.
Definition: LiveInterval.h:363
#define I(x, y, z)
Definition: MD5.cpp:54
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def...
Definition: SlotIndexes.h:257
iterator begin()
Definition: LiveInterval.h:205
unsigned getReg() const
getReg - Returns the register number.
VNInfo * getNextValue(SlotIndex def, VNInfo::Allocator &VNInfoAllocator)
getNextValue - Create a new value number and return it.
Definition: LiveInterval.h:306
static bool isSourceDefinedByImplicitDef(const MachineInstr *MPhi, const MachineRegisterInfo *MRI)
isSourceDefinedByImplicitDef - Return true if all sources of the phi node are implicit_def's.
virtual const TargetInstrInfo * getInstrInfo() const
iterator_range< def_instr_iterator > def_instructions(unsigned Reg) const
#define DEBUG(X)
Definition: Debug.h:92
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:92
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...