25 #define DEBUG_TYPE "mccodeemitter"
34 : MCII(mcii), Ctx(ctx) {
37 ~SystemZMCCodeEmitter()
override {}
46 uint64_t getBinaryCodeForInstr(
const MCInst &MI,
60 uint64_t getBDAddr12Encoding(
const MCInst &MI,
unsigned OpNum,
63 uint64_t getBDAddr20Encoding(
const MCInst &MI,
unsigned OpNum,
66 uint64_t getBDXAddr12Encoding(
const MCInst &MI,
unsigned OpNum,
69 uint64_t getBDXAddr20Encoding(
const MCInst &MI,
unsigned OpNum,
72 uint64_t getBDLAddr12Len8Encoding(
const MCInst &MI,
unsigned OpNum,
75 uint64_t getBDVAddr12Encoding(
const MCInst &MI,
unsigned OpNum,
84 uint64_t getPCRelEncoding(
const MCInst &MI,
unsigned OpNum,
86 unsigned Kind, int64_t Offset,
89 uint64_t getPC16DBLEncoding(
const MCInst &MI,
unsigned OpNum,
92 return getPCRelEncoding(MI, OpNum, Fixups,
95 uint64_t getPC32DBLEncoding(
const MCInst &MI,
unsigned OpNum,
98 return getPCRelEncoding(MI, OpNum, Fixups,
101 uint64_t getPC16DBLTLSEncoding(
const MCInst &MI,
unsigned OpNum,
104 return getPCRelEncoding(MI, OpNum, Fixups,
107 uint64_t getPC32DBLTLSEncoding(
const MCInst &MI,
unsigned OpNum,
110 return getPCRelEncoding(MI, OpNum, Fixups,
119 return new SystemZMCCodeEmitter(MCII, Ctx);
122 void SystemZMCCodeEmitter::
126 uint64_t
Bits = getBinaryCodeForInstr(MI, Fixups, STI);
127 unsigned Size = MCII.get(MI.
getOpcode()).getSize();
129 unsigned ShiftValue = (Size * 8) - 8;
130 for (
unsigned I = 0;
I != Size; ++
I) {
131 OS << uint8_t(Bits >> ShiftValue);
136 uint64_t SystemZMCCodeEmitter::
141 return Ctx.getRegisterInfo()->getEncodingValue(MO.
getReg());
143 return static_cast<uint64_t>(MO.
getImm());
147 uint64_t SystemZMCCodeEmitter::
148 getBDAddr12Encoding(
const MCInst &MI,
unsigned OpNum,
152 uint64_t Disp = getMachineOpValue(MI, MI.
getOperand(OpNum + 1),
Fixups, STI);
153 assert(isUInt<4>(Base) && isUInt<12>(Disp));
154 return (Base << 12) | Disp;
157 uint64_t SystemZMCCodeEmitter::
158 getBDAddr20Encoding(
const MCInst &MI,
unsigned OpNum,
162 uint64_t Disp = getMachineOpValue(MI, MI.
getOperand(OpNum + 1),
Fixups, STI);
163 assert(isUInt<4>(Base) && isInt<20>(Disp));
164 return (Base << 20) | ((Disp & 0xfff) << 8) | ((Disp & 0xff000) >> 12);
167 uint64_t SystemZMCCodeEmitter::
168 getBDXAddr12Encoding(
const MCInst &MI,
unsigned OpNum,
172 uint64_t Disp = getMachineOpValue(MI, MI.
getOperand(OpNum + 1),
Fixups, STI);
173 uint64_t Index = getMachineOpValue(MI, MI.
getOperand(OpNum + 2),
Fixups, STI);
174 assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Index));
175 return (Index << 16) | (Base << 12) | Disp;
178 uint64_t SystemZMCCodeEmitter::
179 getBDXAddr20Encoding(
const MCInst &MI,
unsigned OpNum,
183 uint64_t Disp = getMachineOpValue(MI, MI.
getOperand(OpNum + 1),
Fixups, STI);
184 uint64_t Index = getMachineOpValue(MI, MI.
getOperand(OpNum + 2),
Fixups, STI);
185 assert(isUInt<4>(Base) && isInt<20>(Disp) && isUInt<4>(Index));
186 return (Index << 24) | (Base << 20) | ((Disp & 0xfff) << 8)
187 | ((Disp & 0xff000) >> 12);
190 uint64_t SystemZMCCodeEmitter::
191 getBDLAddr12Len8Encoding(
const MCInst &MI,
unsigned OpNum,
195 uint64_t Disp = getMachineOpValue(MI, MI.
getOperand(OpNum + 1),
Fixups, STI);
196 uint64_t Len = getMachineOpValue(MI, MI.
getOperand(OpNum + 2),
Fixups, STI) - 1;
197 assert(isUInt<4>(Base) && isUInt<12>(Disp) &&
isUInt<8>(Len));
198 return (Len << 16) | (Base << 12) | Disp;
201 uint64_t SystemZMCCodeEmitter::
202 getBDVAddr12Encoding(
const MCInst &MI,
unsigned OpNum,
206 uint64_t Disp = getMachineOpValue(MI, MI.
getOperand(OpNum + 1),
Fixups, STI);
207 uint64_t Index = getMachineOpValue(MI, MI.
getOperand(OpNum + 2),
Fixups, STI);
208 assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<5>(Index));
209 return (Index << 16) | (Base << 12) | Disp;
213 SystemZMCCodeEmitter::getPCRelEncoding(
const MCInst &MI,
unsigned OpNum,
215 unsigned Kind, int64_t Offset,
216 bool AllowTLS)
const {
243 #include "SystemZGenMCCodeEmitter.inc"
bool isUInt< 8 >(uint64_t x)
void push_back(const T &Elt)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Base class for the full range of assembler expressions which are needed for parsing.
Context object for machine code objects.
unsigned getReg() const
Returns the register number.
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Instances of this class represent a single low-level machine instruction.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
const MCExpr * getExpr() const
MCCodeEmitter - Generic instruction encoding interface.
Interface to description of machine instruction set.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
unsigned getOpcode() const
MCCodeEmitter * createSystemZMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
unsigned getNumOperands() const
MCSubtargetInfo - Generic base class for all target subtargets.
const ARM::ArchExtKind Kind
This class implements an extremely fast bulk output stream that can only output to a stream...
Instances of this class represent operands of the MCInst class.
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx)
const MCOperand & getOperand(unsigned i) const