LLVM  3.7.0
HexagonInstrInfo.h
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1 
2 //===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===//
3 //
4 // The LLVM Compiler Infrastructure
5 //
6 // This file is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
8 //
9 //===----------------------------------------------------------------------===//
10 //
11 // This file contains the Hexagon implementation of the TargetInstrInfo class.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
16 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
17 
18 #include "HexagonRegisterInfo.h"
23 
24 #define GET_INSTRINFO_HEADER
25 #include "HexagonGenInstrInfo.inc"
26 
27 namespace llvm {
28 
29 struct EVT;
30 class HexagonSubtarget;
32  virtual void anchor();
33  const HexagonRegisterInfo RI;
34  const HexagonSubtarget &Subtarget;
35 
36 public:
37  typedef unsigned Opcode_t;
38 
40 
41  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
42  /// such, whenever a client has an instance of instruction info, it should
43  /// always be able to get register info as well (through this method).
44  ///
45  const HexagonRegisterInfo &getRegisterInfo() const { return RI; }
46 
47  /// isLoadFromStackSlot - If the specified machine instruction is a direct
48  /// load from a stack slot, return the virtual or physical register number of
49  /// the destination along with the FrameIndex of the loaded stack slot. If
50  /// not, return 0. This predicate must return 0 if the instruction has
51  /// any side effects other than loading from the stack slot.
52  unsigned isLoadFromStackSlot(const MachineInstr *MI,
53  int &FrameIndex) const override;
54 
55  /// isStoreToStackSlot - If the specified machine instruction is a direct
56  /// store to a stack slot, return the virtual or physical register number of
57  /// the source reg along with the FrameIndex of the loaded stack slot. If
58  /// not, return 0. This predicate must return 0 if the instruction has
59  /// any side effects other than storing to the stack slot.
60  unsigned isStoreToStackSlot(const MachineInstr *MI,
61  int &FrameIndex) const override;
62 
63 
65  MachineBasicBlock *&FBB,
67  bool AllowModify) const override;
68 
69  unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
70 
73  DebugLoc DL) const override;
74 
75  bool analyzeCompare(const MachineInstr *MI,
76  unsigned &SrcReg, unsigned &SrcReg2,
77  int &Mask, int &Value) const override;
78 
81  unsigned DestReg, unsigned SrcReg,
82  bool KillSrc) const override;
83 
86  unsigned SrcReg, bool isKill, int FrameIndex,
87  const TargetRegisterClass *RC,
88  const TargetRegisterInfo *TRI) const override;
89 
90  void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
92  const TargetRegisterClass *RC,
93  SmallVectorImpl<MachineInstr*> &NewMIs) const;
94 
97  unsigned DestReg, int FrameIndex,
98  const TargetRegisterClass *RC,
99  const TargetRegisterInfo *TRI) const override;
100 
101  void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
103  const TargetRegisterClass *RC,
104  SmallVectorImpl<MachineInstr*> &NewMIs) const;
105 
106  /// expandPostRAPseudo - This function is called for all pseudo instructions
107  /// that remain after register allocation. Many pseudo instructions are
108  /// created to help register allocation. This is the place to convert them
109  /// into real instructions. The target can edit MI in place, or it can insert
110  /// new instructions and erase MI. The function should return true if
111  /// anything was changed.
113 
115  ArrayRef<unsigned> Ops,
117  int FrameIndex) const override;
118 
120  ArrayRef<unsigned> Ops,
122  MachineInstr *LoadMI) const override {
123  return nullptr;
124  }
125 
126  unsigned createVR(MachineFunction* MF, MVT VT) const;
127 
128  bool isBranch(const MachineInstr *MI) const;
129  bool isPredicable(MachineInstr *MI) const override;
131  ArrayRef<MachineOperand> Cond) const override;
132 
133  bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
134  unsigned ExtraPredCycles,
135  const BranchProbability &Probability) const override;
136 
138  unsigned NumTCycles, unsigned ExtraTCycles,
139  MachineBasicBlock &FMBB,
140  unsigned NumFCycles, unsigned ExtraFCycles,
141  const BranchProbability &Probability) const override;
142 
143  bool isPredicated(const MachineInstr *MI) const override;
144  bool isPredicated(unsigned Opcode) const;
145  bool isPredicatedTrue(const MachineInstr *MI) const;
146  bool isPredicatedTrue(unsigned Opcode) const;
147  bool isPredicatedNew(const MachineInstr *MI) const;
148  bool isPredicatedNew(unsigned Opcode) const;
150  std::vector<MachineOperand> &Pred) const override;
152  ArrayRef<MachineOperand> Pred2) const override;
153 
154  bool
156 
157  bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
158  const BranchProbability &Probability) const override;
159 
160  DFAPacketizer *
161  CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override;
162 
164  const MachineBasicBlock *MBB,
165  const MachineFunction &MF) const override;
166  bool isValidOffset(unsigned Opcode, int Offset, bool Extend = true) const;
167  bool isValidAutoIncImm(const EVT VT, const int Offset) const;
168  bool isMemOp(const MachineInstr *MI) const;
169  bool isSpillPredRegOp(const MachineInstr *MI) const;
170  bool isU6_3Immediate(const int value) const;
171  bool isU6_2Immediate(const int value) const;
172  bool isU6_1Immediate(const int value) const;
173  bool isU6_0Immediate(const int value) const;
174  bool isS4_3Immediate(const int value) const;
175  bool isS4_2Immediate(const int value) const;
176  bool isS4_1Immediate(const int value) const;
177  bool isS4_0Immediate(const int value) const;
178  bool isS12_Immediate(const int value) const;
179  bool isU6_Immediate(const int value) const;
180  bool isS8_Immediate(const int value) const;
181  bool isS6_Immediate(const int value) const;
182 
183  bool isSaveCalleeSavedRegsCall(const MachineInstr* MI) const;
184  bool isConditionalTransfer(const MachineInstr* MI) const;
185  bool isConditionalALU32 (const MachineInstr* MI) const;
186  bool isConditionalLoad (const MachineInstr* MI) const;
187  bool isConditionalStore(const MachineInstr* MI) const;
188  bool isNewValueInst(const MachineInstr* MI) const;
189  bool isNewValue(const MachineInstr* MI) const;
190  bool isNewValue(Opcode_t Opcode) const;
191  bool isDotNewInst(const MachineInstr* MI) const;
192  int GetDotOldOp(const int opc) const;
193  int GetDotNewOp(const MachineInstr* MI) const;
196  *MBPI) const;
197  bool mayBeNewStore(const MachineInstr* MI) const;
198  bool isDeallocRet(const MachineInstr *MI) const;
199  unsigned getInvertedPredicatedOpcode(const int Opc) const;
200  bool isExtendable(const MachineInstr* MI) const;
201  bool isExtended(const MachineInstr* MI) const;
202  bool isPostIncrement(const MachineInstr* MI) const;
203  bool isNewValueStore(const MachineInstr* MI) const;
204  bool isNewValueStore(unsigned Opcode) const;
205  bool isNewValueJump(const MachineInstr* MI) const;
206  bool isNewValueJump(Opcode_t Opcode) const;
207  bool isNewValueJumpCandidate(const MachineInstr *MI) const;
208 
209 
210  void immediateExtend(MachineInstr *MI) const;
211  bool isConstExtended(const MachineInstr *MI) const;
212  unsigned getSize(const MachineInstr *MI) const;
214  const MachineBranchProbabilityInfo *MBPI) const;
215  unsigned getAddrMode(const MachineInstr* MI) const;
216  bool isOperandExtended(const MachineInstr *MI,
217  unsigned short OperandNum) const;
218  unsigned short getCExtOpNum(const MachineInstr *MI) const;
219  int getMinValue(const MachineInstr *MI) const;
220  int getMaxValue(const MachineInstr *MI) const;
221  bool NonExtEquivalentExists (const MachineInstr *MI) const;
222  short getNonExtOpcode(const MachineInstr *MI) const;
223  bool PredOpcodeHasJMP_c(Opcode_t Opcode) const;
225  bool isEndLoopN(Opcode_t Opcode) const;
226  bool getPredReg(ArrayRef<MachineOperand> Cond, unsigned &PredReg,
227  unsigned &PredRegPos, unsigned &PredRegFlags) const;
228  int getCondOpcode(int Opc, bool sense) const;
229 
230 };
231 
232 }
233 
234 #endif
bool isSpillPredRegOp(const MachineInstr *MI) const
bool isConditionalLoad(const MachineInstr *MI) const
bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
bool isBranch(const MachineInstr *MI) const
bool isExtendable(const MachineInstr *MI) const
bool isU6_3Immediate(const int value) const
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
int getMaxValue(const MachineInstr *MI) const
int getDotNewPredJumpOp(MachineInstr *MI, const MachineBranchProbabilityInfo *MBPI) const
bool isU6_2Immediate(const int value) const
A debug info location.
Definition: DebugLoc.h:34
int getMinValue(const MachineInstr *MI) const
bool isEndLoopN(Opcode_t Opcode) const
bool isU6_1Immediate(const int value) const
unsigned short getCExtOpNum(const MachineInstr *MI) const
bool PredicateInstruction(MachineInstr *MI, ArrayRef< MachineOperand > Cond) const override
bool isPostIncrement(const MachineInstr *MI) const
bool isConditionalTransfer(const MachineInstr *MI) const
bool isPredicatedNew(const MachineInstr *MI) const
bool isSchedulingBoundary(const MachineInstr *MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const override
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot...
bool isMemOp(const MachineInstr *MI) const
bool isPredicated(const MachineInstr *MI) const override
unsigned getSize(const MachineInstr *MI) const
int GetDotOldOp(const int opc) const
bool isS4_1Immediate(const int value) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APInt.h:33
bool isNewValueJumpCandidate(const MachineInstr *MI) const
bool predOpcodeHasNot(ArrayRef< MachineOperand > Cond) const
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
const HexagonRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: ArrayRef.h:31
unsigned getInvertedPredicatedOpcode(const int Opc) const
unsigned getAddrMode(const MachineInstr *MI) const
bundle_iterator< MachineInstr, instr_iterator > iterator
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, const BranchProbability &Probability) const override
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, const BranchProbability &Probability) const override
MVT - Machine Value Type.
unsigned RemoveBranch(MachineBasicBlock &MBB) const override
bool isNewValueStore(const MachineInstr *MI) const
bundle_iterator - MachineBasicBlock iterator that automatically skips over MIs that are inside bundle...
bool ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr *LoadMI) const override
bool isSaveCalleeSavedRegsCall(const MachineInstr *MI) const
bool isDeallocRet(const MachineInstr *MI) const
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex) const override
bool isNewValueInst(const MachineInstr *MI) const
unsigned createVR(MachineFunction *MF, MVT VT) const
bool isPredicatedTrue(const MachineInstr *MI) const
bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override
expandPostRAPseudo - This function is called for all pseudo instructions that remain after register a...
bool isConstExtended(const MachineInstr *MI) const
void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, SmallVectorImpl< MachineInstr * > &NewMIs) const
bool isConditionalStore(const MachineInstr *MI) const
int GetDotNewOp(const MachineInstr *MI) const
EVT - Extended Value Type.
Definition: ValueTypes.h:31
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool getPredReg(ArrayRef< MachineOperand > Cond, unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const
bool isU6_0Immediate(const int value) const
HexagonInstrInfo(HexagonSubtarget &ST)
bool DefinesPredicate(MachineInstr *MI, std::vector< MachineOperand > &Pred) const override
int getCondOpcode(int Opc, bool sense) const
bool isS6_Immediate(const int value) const
bool isPredicable(MachineInstr *MI) const override
int GetDotNewPredOp(MachineInstr *MI, const MachineBranchProbabilityInfo *MBPI) const
bool isExtended(const MachineInstr *MI) const
TargetSubtargetInfo - Generic base class for all target subtargets.
bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override
For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two registe...
Representation of each machine instruction.
Definition: MachineInstr.h:51
bool isS4_3Immediate(const int value) const
bool isValidAutoIncImm(const EVT VT, const int Offset) const
unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot...
#define I(x, y, z)
Definition: MD5.cpp:54
bool isConditionalALU32(const MachineInstr *MI) const
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, DebugLoc DL) const override
bool isOperandExtended(const MachineInstr *MI, unsigned short OperandNum) const
short getNonExtOpcode(const MachineInstr *MI) const
bool isS4_0Immediate(const int value) const
bool isU6_Immediate(const int value) const
bool isS8_Immediate(const int value) const
LLVM Value Representation.
Definition: Value.h:69
void immediateExtend(MachineInstr *MI) const
immediateExtend - Changes the instruction in place to one using an immediate extender.
bool isNewValueJump(const MachineInstr *MI) const
void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, SmallVectorImpl< MachineInstr * > &NewMIs) const
bool isNewValue(const MachineInstr *MI) const
bool PredOpcodeHasJMP_c(Opcode_t Opcode) const
bool isValidOffset(unsigned Opcode, int Offset, bool Extend=true) const
bool NonExtEquivalentExists(const MachineInstr *MI) const
bool isDotNewInst(const MachineInstr *MI) const
bool isS12_Immediate(const int value) const
bool isS4_2Immediate(const int value) const
bool mayBeNewStore(const MachineInstr *MI) const