LLVM  3.7.0
HexagonMCTargetDesc.h
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1 //===-- HexagonMCTargetDesc.h - Hexagon Target Descriptions -----*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides Hexagon specific target descriptions.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H
15 #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H
16 
17 #include <cstdint>
18 
19 namespace llvm {
20 struct InstrItinerary;
21 struct InstrStage;
22 class MCAsmBackend;
23 class MCCodeEmitter;
24 class MCContext;
25 class MCInstrInfo;
26 class MCObjectWriter;
27 class MCRegisterInfo;
28 class MCSubtargetInfo;
29 class Target;
30 class Triple;
31 class StringRef;
32 class raw_ostream;
33 class raw_pwrite_stream;
34 
35 extern Target TheHexagonTarget;
36 
37 extern const InstrStage HexagonStages[];
38 
39 MCInstrInfo *createHexagonMCInstrInfo();
40 
41 MCCodeEmitter *createHexagonMCCodeEmitter(MCInstrInfo const &MCII,
42  MCRegisterInfo const &MRI,
43  MCContext &MCT);
44 
45 MCAsmBackend *createHexagonAsmBackend(Target const &T,
46  MCRegisterInfo const &MRI,
47  const Triple &TT, StringRef CPU);
48 
49 MCObjectWriter *createHexagonELFObjectWriter(raw_pwrite_stream &OS,
50  uint8_t OSABI, StringRef CPU);
51 
52 } // End llvm namespace
53 
54 // Define symbolic names for Hexagon registers. This defines a mapping from
55 // register name to register number.
56 //
57 #define GET_REGINFO_ENUM
58 #include "HexagonGenRegisterInfo.inc"
59 
60 // Defines symbolic names for the Hexagon instructions.
61 //
62 #define GET_INSTRINFO_ENUM
63 #include "HexagonGenInstrInfo.inc"
64 
65 #define GET_SUBTARGETINFO_ENUM
66 #include "HexagonGenSubtargetInfo.inc"
67 
68 #endif
MCAsmBackend * createHexagonAsmBackend(Target const &T, MCRegisterInfo const &, const Triple &TT, StringRef CPU)
MCInstrInfo * createHexagonMCInstrInfo()
MCObjectWriter * createHexagonELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI, StringRef CPU)
MCCodeEmitter * createHexagonMCCodeEmitter(MCInstrInfo const &MCII, MCRegisterInfo const &MRI, MCContext &MCT)
const InstrStage HexagonStages[]
Target TheHexagonTarget