41 #define DEBUG_TYPE "arm-register-info"
43 #define GET_REGINFO_TARGET_DESC
44 #include "ARMGenRegisterInfo.inc"
60 return STI.
isThumb() ? ARM::R7 : ARM::R11;
73 return CSR_NoRegs_SaveList;
78 return CSR_AAPCS_SaveList;
82 return CSR_FIQ_SaveList;
86 return CSR_GenericInt_SaveList;
99 return CSR_NoRegs_RegMask;
100 return STI.
isTargetDarwin() ? CSR_iOS_RegMask : CSR_AAPCS_RegMask;
105 return CSR_NoRegs_RegMask;
124 : CSR_AAPCS_ThisReturn_RegMask;
134 Reserved.
set(ARM::SP);
135 Reserved.
set(ARM::PC);
136 Reserved.
set(ARM::FPSCR);
137 Reserved.
set(ARM::APSR_NZCV);
144 Reserved.
set(ARM::R9);
147 assert(ARM::D31 == ARM::D16 + 15);
148 for (
unsigned i = 0; i != 16; ++i)
149 Reserved.
set(ARM::D16 + i);
165 switch (Super->
getID()) {
166 case ARM::GPRRegClassID:
167 case ARM::SPRRegClassID:
168 case ARM::DPRRegClassID:
169 case ARM::QPRRegClassID:
170 case ARM::QQPRRegClassID:
171 case ARM::QQQQPRRegClassID:
172 case ARM::GPRPairRegClassID:
183 return &ARM::GPRRegClass;
188 if (RC == &ARM::CCRRegClass)
189 return &ARM::rGPRRegClass;
199 switch (RC->
getID()) {
202 case ARM::tGPRRegClassID:
203 return TFI->hasFP(MF) ? 4 : 5;
204 case ARM::GPRRegClassID: {
205 unsigned FP = TFI->hasFP(MF) ? 1 : 0;
208 case ARM::SPRRegClassID:
209 case ARM::DPRRegClassID:
217 if (ARM::GPRPairRegClass.
contains(*Supers))
218 return RI->
getSubReg(*Supers, Odd ? ARM::gsub_1 : ARM::gsub_0);
233 switch (Hint.first) {
248 unsigned Paired = Hint.second;
252 unsigned PairedPhys = 0;
255 }
else if (VRM && VRM->
hasPhys(Paired)) {
261 std::find(Order.
begin(), Order.
end(), PairedPhys) != Order.
end())
265 for (
unsigned I = 0, E = Order.
size();
I != E; ++
I) {
266 unsigned Reg = Order[
I];
267 if (Reg == PairedPhys || (getEncodingValue(Reg) & 1) != Odd)
289 unsigned OtherReg = Hint.second;
292 if (Hint.second == Reg) {
351 if (TFI->hasReservedCallFrame(MF))
395 unsigned DestReg,
unsigned SubIdx,
int Val,
397 unsigned PredReg,
unsigned MIFlags)
const {
407 .addConstantPoolIndex(Idx)
436 int64_t InstrOffs = 0;
451 InstrOffs = -InstrOffs;
459 InstrOffs = -InstrOffs;
466 InstrOffs = -InstrOffs;
479 return InstrOffs * Scale;
489 assert(i < MI->getNumOperands() &&
"Instr doesn't have FrameIndex operand!");
503 case ARM::LDRi12:
case ARM::LDRH:
case ARM::LDRBi12:
504 case ARM::STRi12:
case ARM::STRH:
case ARM::STRBi12:
505 case ARM::t2LDRi12:
case ARM::t2LDRi8:
506 case ARM::t2STRi12:
case ARM::t2STRi8:
507 case ARM::VLDRS:
case ARM::VLDRD:
508 case ARM::VSTRS:
case ARM::VSTRD:
509 case ARM::tSTRspi:
case ARM::tLDRspi:
529 int64_t FPOffset = Offset - 8;
548 if (TFI->
hasFP(MF) &&
569 unsigned BaseReg,
int FrameIdx,
570 int64_t Offset)
const {
577 if (Ins != MBB->
end())
578 DL = Ins->getDebugLoc();
594 int64_t Offset)
const {
604 "This resolveFrameIndex does not support Thumb1!");
608 assert(i < MI.
getNumOperands() &&
"Instr doesn't have FrameIndex operand!");
617 assert (Done &&
"Unable to resolve frame index!");
622 int64_t Offset)
const {
629 assert(i < MI->getNumOperands() &&
"Instr doesn't have FrameIndex operand!");
636 unsigned NumBits = 0;
638 bool isSigned =
true;
665 NumBits = (BaseReg == ARM::SP ? 8 : 5);
676 if ((Offset & (Scale-1)) != 0)
679 if (isSigned && Offset < 0)
682 unsigned Mask = (1 << NumBits) - 1;
683 if ((
unsigned)Offset <= Mask * Scale)
691 int SPAdj,
unsigned FIOperandNum,
701 "This eliminateFrameIndex does not support Thumb1!");
714 "Cannot use SP to access the emergency spill slot in "
715 "functions without a reserved call frame");
717 "Cannot use SP to access the emergency spill slot in "
718 "functions with variable sized frame objects");
722 assert(!MI.
isDebugValue() &&
"DBG_VALUEs should be handled in target-independent code");
741 "This code isn't needed if offset already handled!");
743 unsigned ScratchReg = 0;
755 Offset, Pred, PredReg,
TII);
759 Offset, Pred, PredReg,
TII);
791 if (SrcRCWeight.RegWeight > NewRCWeight.RegWeight)
793 if (DstRCWeight.RegWeight > NewRCWeight.RegWeight)
803 DEBUG(
dbgs() <<
"\tARM::shouldCoalesce - Coalesced Weight: "
804 << It->second <<
"\n");
805 DEBUG(
dbgs() <<
"\tARM::shouldCoalesce - Reg Weight: "
806 << NewRCWeight.RegWeight <<
"\n");
814 unsigned SizeMultiplier = MBB->size()/100;
815 SizeMultiplier = SizeMultiplier ? SizeMultiplier : 1;
816 if (It->second < NewRCWeight.WeightLimit * SizeMultiplier) {
817 It->second += NewRCWeight.RegWeight;
bool hasPhys(unsigned virtReg) const
returns true if the specified virtual register is mapped to a physical register
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
void push_back(const T &Elt)
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const override
materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx...
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
static unsigned char getAM3Offset(unsigned AM3Opc)
Alignment of stack for function (3 bits) stored as log2 of alignment with +1 bias 0 means unaligned (...
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
Describe properties that are true of each instruction in the target description file.
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
void emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
int ResolveFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg, int SPAdj) const
unsigned getID() const
getID() - Return the register class ID number.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
bool isThumbFunction() const
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
bool isThumb1Only() const
const MCPhysReg * iterator
aarch64 collect AArch64 Collect Linker Optimization Hint(LOH)"
bool canReserveReg(unsigned PhysReg) const
canReserveReg - Returns true if PhysReg can be used as a reserved register.
void updateRegAllocHint(unsigned Reg, unsigned NewReg, MachineFunction &MF) const override
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
needsFrameBaseReg - Returns true if the instruction's frame index reference would be better served by...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
bool isR9Reserved() const
int64_t getLocalFrameSize() const
Get the size of the local object blob.
unsigned getSize() const
getSize - Return the size of the register in bytes, which is also the size of a stack slot allocated ...
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
void getRegAllocationHints(unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM) const override
static const MachineInstrBuilder & AddDefaultPred(const MachineInstrBuilder &MIB)
static unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MCSuperRegIterator enumerates all super-registers of Reg.
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
const HexagonInstrInfo * TII
const TargetRegisterInfo * getTargetRegisterInfo() const
bool isTargetDarwin() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getFrameRegister(const MachineFunction &MF) const override
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required, we reserve argument space for call sites in the function immediately on entry to the current function.
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const ARMBaseInstrInfo &TII)
rewriteARMFrameIndex / rewriteT2FrameIndex - Rewrite MI to access 'Offset' bytes from the FP...
iterator begin() const
begin/end - Return all of the registers in this class.
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const ARMBaseInstrInfo &TII)
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
const uint32_t * getThisReturnPreservedMask(const MachineFunction &MF, CallingConv::ID) const
getThisReturnPreservedMask - Returns a call preserved mask specific to the case that 'returned' is on...
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
bool isTargetMachO() const
unsigned getLocalFrameMaxAlign() const
Return the required alignment of the local object blob.
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
bool isThumb1OnlyFunction() const
size_t size() const
size - Get the array size.
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
const MachineBasicBlock * getParent() const
TargetInstrInfo - Interface to description of machine instruction set.
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
bool isDebugValue() const
unsigned getDefRegState(bool B)
bundle_iterator< MachineInstr, instr_iterator > iterator
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override
bool requiresRegisterScavenging(const MachineFunction &MF) const override
Code Generation virtual methods...
int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const override
This is an important base class in LLVM.
bool isReserved(unsigned PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
static unsigned char getAM5Offset(unsigned AM5Opc)
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const MachineOperand & getOperand(unsigned i) const
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
const TargetRegisterClass *const * sc_iterator
static unsigned getFramePointerReg(const ARMSubtarget &STI)
virtual void getRegAllocationHints(unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr) const
Get a list of 'hint' registers that the register allocator should try first when allocating a physica...
MCSubRegIterator enumerates all sub-registers of Reg.
void emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of instructions to materializea des...
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
bool canRealignStack(const MachineFunction &MF) const
bool isScavengingFrameIndex(int FI) const
Query whether a frame index is a scavenging frame index.
static AddrOpc getAM2Op(unsigned AM2Opc)
static const MachineInstrBuilder & AddDefaultCC(const MachineInstrBuilder &MIB)
static unsigned getAM2Offset(unsigned AM2Opc)
MachineOperand class - Representation of each machine instruction operand.
virtual const RegClassWeight & getRegClassWeight(const TargetRegisterClass *RC) const =0
Get the weight in units of pressure for this register class.
void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg)
setRegAllocationHint - Specify a register allocation hint for the specified virtual register...
bool test(unsigned Idx) const
const uint32_t * getNoPreservedMask() const
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const MachineInstrBuilder & addFrameIndex(int Idx) const
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
bool hasBasePointer(const MachineFunction &MF) const
AddrMode
ARM Addressing Modes.
static AddrOpc getAM3Op(unsigned AM3Opc)
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override
Representation of each machine instruction.
static bool isPhysicalRegister(unsigned Reg)
isPhysicalRegister - Return true if the specified register number is in the physical register namespa...
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static IntegerType * getInt32Ty(LLVMContext &C)
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC) const override
SrcRC and DstRC will be morphed into NewRC if this returns true.
unsigned BasePtr
BasePtr - ARM physical register used as a base ptr in complex stack frames.
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
static AddrOpc getAM5Op(unsigned AM5Opc)
virtual void emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred=ARMCC::AL, unsigned PredReg=0, unsigned MIFlags=MachineInstr::NoFlags) const
emitLoadConstPool - Emits a load from constpool to materialize the specified immediate.
unsigned getReg() const
getReg - Returns the register number.
StringRef getValueAsString() const
Return the attribute's value as a string.
const ARM::ArchExtKind Kind
bool cannotEliminateFrame(const MachineFunction &MF) const
virtual const TargetInstrInfo * getInstrInfo() const
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
unsigned getPhys(unsigned virtReg) const
returns the physical register mapped to the specified virtual register
const TargetRegisterClass * getRegClass(const MCInstrDesc &TID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum...
std::pair< unsigned, unsigned > getRegAllocationHint(unsigned VReg) const
getRegAllocationHint - Return the register allocation hint for the specified virtual register...
bool isThumb2Function() const
DenseMap< const MachineBasicBlock *, unsigned >::iterator getCoalescedWeight(MachineBasicBlock *MBB)
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
bool needsStackRealignment(const MachineFunction &MF) const override
bool isTargetWindows() const
sc_iterator getSuperClasses() const
getSuperClasses - Returns a NULL terminated list of super-classes.
unsigned getConstantPoolIndex(const Constant *C, unsigned Alignment)
getConstantPoolIndex - Create a new entry in the constant pool or return an existing one...