37 #define DEBUG_TYPE "regalloc"
39 STATISTIC(NumNewQueued ,
"Number of new live ranges queued");
45 cl::desc(
"Verify during register allocation"));
55 void RegAllocBase::anchor() {}
72 void RegAllocBase::seedLiveRegs() {
89 assert(!
VRM->
hasPhys(VirtReg->reg) &&
"Register already assigned");
93 DEBUG(
dbgs() <<
"Dropping unused " << *VirtReg <<
'\n');
107 <<
':' << *VirtReg <<
" w=" << VirtReg->weight <<
'\n');
109 VirtRegVec SplitVRegs;
110 unsigned AvailablePhysReg =
selectOrSplit(*VirtReg, SplitVRegs);
112 if (AvailablePhysReg == ~0u) {
126 MI->
emitError(
"inline assembly requires more registers than available");
135 if (AvailablePhysReg)
138 for (VirtRegVec::iterator
I = SplitVRegs.begin(), E = SplitVRegs.end();
141 assert(!
VRM->
hasPhys(SplitVirtReg->
reg) &&
"Register already assigned");
143 DEBUG(
dbgs() <<
"not queueing unused " << *SplitVirtReg <<
'\n');
148 DEBUG(
dbgs() <<
"queuing new interval: " << *SplitVirtReg <<
"\n");
150 "expect split value in virtual register");
bool hasPhys(unsigned virtReg) const
returns true if the specified virtual register is mapped to a physical register
STATISTIC(NumFunctions,"Total number of functions")
MachineFunction & getMachineFunction() const
static unsigned index2VirtReg(unsigned Index)
index2VirtReg - Convert a 0-based index to a virtual register number.
LiveInterval - This class represents the liveness of a register, or stack slot.
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
virtual unsigned selectOrSplit(LiveInterval &VirtReg, SmallVectorImpl< unsigned > &splitLVRs)=0
void assignVirt2Phys(unsigned virtReg, unsigned physReg)
creates a mapping for the specified virtual register to the specified physical register ...
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag=true)
Reports a serious error, calling any installed error handler.
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
NamedRegionTimer - This class is basically a combination of TimeRegion and Timer. ...
const TargetRegisterClass * getRegClass(unsigned Reg) const
getRegClass - Return the register class of the specified virtual register.
void freezeReservedRegs(const MachineFunction &)
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
Reg
All possible values of the reg field in the ModR/M byte.
ArrayRef< MCPhysReg > getOrder(const TargetRegisterClass *RC) const
getOrder - Returns the preferred allocation order for RC.
static reg_instr_iterator reg_instr_end()
defusechain_iterator - This class provides iterator support for machine operands in the function that...
void assign(LiveInterval &VirtReg, unsigned PhysReg)
Assign VirtReg to PhysReg.
const char * getRegClassName(const TargetRegisterClass *Class) const
getRegClassName - Returns the name of the register class.
void invalidateVirtRegs()
Invalidate cached interference queries after modifying virtual register live ranges.
void removeInterval(unsigned Reg)
const TargetRegisterInfo & getTargetRegInfo() const
reg_instr_iterator reg_instr_begin(unsigned RegNo) const
void runOnMachineFunction(const MachineFunction &MF)
runOnFunction - Prepare to answer questions about MF.
void init(VirtRegMap &vrm, LiveIntervals &lis, LiveRegMatrix &mat)
static const char TimerGroupName[]
void emitError(StringRef Msg) const
Emit an error referring to the source location of this instruction.
virtual void enqueue(LiveInterval *LI)=0
enqueue - Add VirtReg to the priority queue of unassigned registers.
LiveInterval & getInterval(unsigned Reg)
static cl::opt< bool, true > VerifyRegAlloc("verify-regalloc", cl::location(RegAllocBase::VerifyEnabled), cl::desc("Verify during register allocation"))
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
virtual void aboutToRemoveInterval(LiveInterval &LI)
Method called when the allocator is about to remove a LiveInterval.
Representation of each machine instruction.
static bool VerifyEnabled
VerifyEnabled - True when -verify-regalloc is given.
const TargetRegisterInfo * TRI
MachineRegisterInfo & getRegInfo() const
RegisterClassInfo RegClassInfo
bool TimePassesIsEnabled
If the user specifies the -time-passes argument on an LLVM tool command line then the value of this b...
MachineRegisterInfo * MRI
LocationClass< Ty > location(Ty &L)
bool reg_nodbg_empty(unsigned RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions...
virtual LiveInterval * dequeue()=0
dequeue - Return the next unassigned register, or NULL.