30 void AMDGPUInstPrinter::printU8ImmOperand(
const MCInst *
MI,
unsigned OpNo,
35 void AMDGPUInstPrinter::printU16ImmOperand(
const MCInst *MI,
unsigned OpNo,
40 void AMDGPUInstPrinter::printU32ImmOperand(
const MCInst *MI,
unsigned OpNo,
45 void AMDGPUInstPrinter::printU8ImmDecOperand(
const MCInst *MI,
unsigned OpNo,
50 void AMDGPUInstPrinter::printU16ImmDecOperand(
const MCInst *MI,
unsigned OpNo,
55 void AMDGPUInstPrinter::printOffen(
const MCInst *MI,
unsigned OpNo,
61 void AMDGPUInstPrinter::printIdxen(
const MCInst *MI,
unsigned OpNo,
67 void AMDGPUInstPrinter::printAddr64(
const MCInst *MI,
unsigned OpNo,
73 void AMDGPUInstPrinter::printMBUFOffset(
const MCInst *MI,
unsigned OpNo,
77 printU16ImmDecOperand(MI, OpNo, O);
81 void AMDGPUInstPrinter::printDSOffset(
const MCInst *MI,
unsigned OpNo,
86 printU16ImmDecOperand(MI, OpNo, O);
90 void AMDGPUInstPrinter::printDSOffset0(
const MCInst *MI,
unsigned OpNo,
94 printU8ImmDecOperand(MI, OpNo, O);
98 void AMDGPUInstPrinter::printDSOffset1(
const MCInst *MI,
unsigned OpNo,
102 printU8ImmDecOperand(MI, OpNo, O);
106 void AMDGPUInstPrinter::printGDS(
const MCInst *MI,
unsigned OpNo,
112 void AMDGPUInstPrinter::printGLC(
const MCInst *MI,
unsigned OpNo,
118 void AMDGPUInstPrinter::printSLC(
const MCInst *MI,
unsigned OpNo,
124 void AMDGPUInstPrinter::printTFE(
const MCInst *MI,
unsigned OpNo,
145 case AMDGPU::FLAT_SCR:
154 case AMDGPU::EXEC_LO:
157 case AMDGPU::EXEC_HI:
160 case AMDGPU::FLAT_SCR_LO:
161 O <<
"flat_scratch_lo";
163 case AMDGPU::FLAT_SCR_HI:
164 O <<
"flat_scratch_hi";
219 O << Type <<
'[' << RegIdx <<
':' << (RegIdx + NumRegs - 1) <<
']';
222 void AMDGPUInstPrinter::printVOPDst(
const MCInst *MI,
unsigned OpNo,
229 printOperand(MI, OpNo, O);
232 void AMDGPUInstPrinter::printImmediate32(uint32_t Imm,
raw_ostream &O) {
233 int32_t SImm =
static_cast<int32_t
>(Imm);
234 if (SImm >= -16 && SImm <= 64) {
258 O << formatHex(static_cast<uint64_t>(Imm));
261 void AMDGPUInstPrinter::printImmediate64(uint64_t Imm,
raw_ostream &O) {
262 int64_t SImm =
static_cast<int64_t
>(Imm);
263 if (SImm >= -16 && SImm <= 64) {
290 void AMDGPUInstPrinter::printOperand(
const MCInst *MI,
unsigned OpNo,
297 case AMDGPU::PRED_SEL_OFF:
304 }
else if (Op.
isImm()) {
310 printImmediate32(Op.
getImm(), O);
312 printImmediate64(Op.
getImm(), O);
316 printImmediate32(Op.
getImm(), O);
346 void AMDGPUInstPrinter::printOperandAndMods(
const MCInst *MI,
unsigned OpNo,
353 printOperand(MI, OpNo + 1, O);
354 if (InputModifiers & SISrcMods::ABS)
358 void AMDGPUInstPrinter::printInterpSlot(
const MCInst *MI,
unsigned OpNum,
364 }
else if (Imm == 1) {
366 }
else if (Imm == 0) {
373 void AMDGPUInstPrinter::printMemOperand(
const MCInst *MI,
unsigned OpNo,
375 printOperand(MI, OpNo, O);
377 printOperand(MI, OpNo + 1, O);
380 void AMDGPUInstPrinter::printIfSet(
const MCInst *MI,
unsigned OpNo,
392 void AMDGPUInstPrinter::printAbs(
const MCInst *MI,
unsigned OpNo,
394 printIfSet(MI, OpNo, O,
"|");
397 void AMDGPUInstPrinter::printClamp(
const MCInst *MI,
unsigned OpNo,
399 printIfSet(MI, OpNo, O,
"_SAT");
402 void AMDGPUInstPrinter::printClampSI(
const MCInst *MI,
unsigned OpNo,
408 void AMDGPUInstPrinter::printOModSI(
const MCInst *MI,
unsigned OpNo,
419 void AMDGPUInstPrinter::printLiteral(
const MCInst *MI,
unsigned OpNo,
425 void AMDGPUInstPrinter::printLast(
const MCInst *MI,
unsigned OpNo,
427 printIfSet(MI, OpNo, O,
"*",
" ");
430 void AMDGPUInstPrinter::printNeg(
const MCInst *MI,
unsigned OpNo,
432 printIfSet(MI, OpNo, O,
"-");
435 void AMDGPUInstPrinter::printOMOD(
const MCInst *MI,
unsigned OpNo,
451 void AMDGPUInstPrinter::printRel(
const MCInst *MI,
unsigned OpNo,
453 printIfSet(MI, OpNo, O,
"+");
456 void AMDGPUInstPrinter::printUpdateExecMask(
const MCInst *MI,
unsigned OpNo,
458 printIfSet(MI, OpNo, O,
"ExecMask,");
461 void AMDGPUInstPrinter::printUpdatePred(
const MCInst *MI,
unsigned OpNo,
463 printIfSet(MI, OpNo, O,
"Pred,");
466 void AMDGPUInstPrinter::printWrite(
const MCInst *MI,
unsigned OpNo,
474 void AMDGPUInstPrinter::printSel(
const MCInst *MI,
unsigned OpNo,
476 const char * chans =
"XYZW";
486 O << cb <<
'[' << sel <<
']';
487 }
else if (sel >= 448) {
490 }
else if (sel >= 0){
495 O <<
'.' << chans[chan];
498 void AMDGPUInstPrinter::printBankSwizzle(
const MCInst *MI,
unsigned OpNo,
501 switch (BankSwizzle) {
503 O <<
"BS:VEC_021/SCL_122";
506 O <<
"BS:VEC_120/SCL_212";
509 O <<
"BS:VEC_102/SCL_221";
523 void AMDGPUInstPrinter::printRSel(
const MCInst *MI,
unsigned OpNo,
553 void AMDGPUInstPrinter::printCT(
const MCInst *MI,
unsigned OpNo,
568 void AMDGPUInstPrinter::printKCache(
const MCInst *MI,
unsigned OpNo,
571 if (KCacheMode > 0) {
573 O <<
"CB" << KCacheBank <<
':';
575 int LineSize = (KCacheMode == 1) ? 16 : 32;
576 O << KCacheAddr * 16 <<
'-' << KCacheAddr * 16 + LineSize;
580 void AMDGPUInstPrinter::printSendMsg(
const MCInst *MI,
unsigned OpNo,
583 unsigned Msg = SImm16 & 0xF;
584 if (Msg == 2 || Msg == 3) {
585 unsigned Op = (SImm16 >> 4) & 0xF;
593 unsigned Stream = (SImm16 >> 8) & 0x3;
600 O <<
" stream " << Stream;
608 O <<
"unknown(" << Msg <<
") ";
611 void AMDGPUInstPrinter::printWaitFlag(
const MCInst *MI,
unsigned OpNo,
617 unsigned Vmcnt = SImm16 & 0xF;
618 unsigned Expcnt = (SImm16 >> 4) & 0xF;
619 unsigned Lgkmcnt = (SImm16 >> 8) & 0xF;
621 bool NeedSpace =
false;
624 O <<
"vmcnt(" << Vmcnt <<
')';
631 O <<
"expcnt(" << Expcnt <<
')';
635 if (Lgkmcnt != 0x7) {
638 O <<
"lgkmcnt(" << Lgkmcnt <<
')';
642 #include "AMDGPUGenAsmWriter.inc"
format_object< int64_t > formatHex(int64_t Value) const
Describe properties that are true of each instruction in the target description file.
float BitsToFloat(uint32_t Bits)
BitsToFloat - This function takes a 32-bit integer and returns the bit equivalent float...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static void printRegOperand(unsigned RegNo, raw_ostream &O, const MCRegisterInfo &MRI)
Base class for the full range of assembler expressions which are needed for parsing.
uint8_t OperandType
Information about the type of the operand.
void printInstruction(const MCInst *MI, raw_ostream &O)
unsigned getReg() const
Returns the register number.
static const char * getRegisterName(unsigned RegNo)
format_object< int64_t > formatDec(int64_t Value) const
Utility functions to print decimal/hexadecimal values.
MCRegisterClass - Base class of TargetRegisterClass.
Instances of this class represent a single low-level machine instruction.
uint32_t FloatToBits(float Float)
FloatToBits - This function takes a float and returns the bit equivalent 32-bit integer.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
const MCExpr * getExpr() const
void print(raw_ostream &OS, const MCAsmInfo *MAI) const
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
unsigned getSize() const
getSize - Return the size of the register in bytes, which is also the size of a stack slot allocated ...
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
bool contains(unsigned Reg) const
contains - Return true if the specified register is included in this register class.
uint64_t DoubleToBits(double Double)
DoubleToBits - This function takes a double and returns the bit equivalent 64-bit integer...
unsigned getOpcode() const
Provides AMDGPU specific target descriptions.
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, const MCSubtargetInfo &STI) override
Print the specified MCInst to the specified raw_ostream.
MCSubtargetInfo - Generic base class for all target subtargets.
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
const MCOperandInfo * OpInfo
This class implements an extremely fast bulk output stream that can only output to a stream...
StringRef - Represent a constant reference to a string, i.e.
Instances of this class represent operands of the MCInst class.
const MCOperand & getOperand(unsigned i) const
const MCRegisterInfo & MRI