LLVM  3.7.0
AArch64DeadRegisterDefinitionsPass.cpp
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1 //==-- AArch64DeadRegisterDefinitions.cpp - Replace dead defs w/ zero reg --==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 // When allowed by the instruction, replace a dead definition of a GPR with
10 // the zero register. This makes the code a bit friendlier towards the
11 // hardware's register renamer.
12 //===----------------------------------------------------------------------===//
13 
14 #include "AArch64.h"
15 #include "AArch64RegisterInfo.h"
16 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Support/Debug.h"
23 using namespace llvm;
24 
25 #define DEBUG_TYPE "aarch64-dead-defs"
26 
27 STATISTIC(NumDeadDefsReplaced, "Number of dead definitions replaced");
28 
29 namespace {
30 class AArch64DeadRegisterDefinitions : public MachineFunctionPass {
31 private:
32  const TargetRegisterInfo *TRI;
33  bool implicitlyDefinesOverlappingReg(unsigned Reg, const MachineInstr &MI);
34  bool processMachineBasicBlock(MachineBasicBlock &MBB);
35  bool usesFrameIndex(const MachineInstr &MI);
36 public:
37  static char ID; // Pass identification, replacement for typeid.
38  explicit AArch64DeadRegisterDefinitions() : MachineFunctionPass(ID) {}
39 
40  bool runOnMachineFunction(MachineFunction &F) override;
41 
42  const char *getPassName() const override { return "Dead register definitions"; }
43 
44  void getAnalysisUsage(AnalysisUsage &AU) const override {
45  AU.setPreservesCFG();
47  }
48 };
50 } // end anonymous namespace
51 
52 bool AArch64DeadRegisterDefinitions::implicitlyDefinesOverlappingReg(
53  unsigned Reg, const MachineInstr &MI) {
54  for (const MachineOperand &MO : MI.implicit_operands())
55  if (MO.isReg() && MO.isDef())
56  if (TRI->regsOverlap(Reg, MO.getReg()))
57  return true;
58  return false;
59 }
60 
61 bool AArch64DeadRegisterDefinitions::usesFrameIndex(const MachineInstr &MI) {
62  for (const MachineOperand &Op : MI.uses())
63  if (Op.isFI())
64  return true;
65  return false;
66 }
67 
68 bool AArch64DeadRegisterDefinitions::processMachineBasicBlock(
69  MachineBasicBlock &MBB) {
70  bool Changed = false;
71  for (MachineInstr &MI : MBB) {
72  if (usesFrameIndex(MI)) {
73  // We need to skip this instruction because while it appears to have a
74  // dead def it uses a frame index which might expand into a multi
75  // instruction sequence during EPI.
76  DEBUG(dbgs() << " Ignoring, operand is frame index\n");
77  continue;
78  }
79  for (int i = 0, e = MI.getDesc().getNumDefs(); i != e; ++i) {
80  MachineOperand &MO = MI.getOperand(i);
81  if (MO.isReg() && MO.isDead() && MO.isDef()) {
82  assert(!MO.isImplicit() && "Unexpected implicit def!");
83  DEBUG(dbgs() << " Dead def operand #" << i << " in:\n ";
84  MI.print(dbgs()));
85  // Be careful not to change the register if it's a tied operand.
86  if (MI.isRegTiedToUseOperand(i)) {
87  DEBUG(dbgs() << " Ignoring, def is tied operand.\n");
88  continue;
89  }
90  // Don't change the register if there's an implicit def of a subreg or
91  // supperreg.
92  if (implicitlyDefinesOverlappingReg(MO.getReg(), MI)) {
93  DEBUG(dbgs() << " Ignoring, implicitly defines overlap reg.\n");
94  continue;
95  }
96  // Make sure the instruction take a register class that contains
97  // the zero register and replace it if so.
98  unsigned NewReg;
99  switch (MI.getDesc().OpInfo[i].RegClass) {
100  default:
101  DEBUG(dbgs() << " Ignoring, register is not a GPR.\n");
102  continue;
103  case AArch64::GPR32RegClassID:
104  NewReg = AArch64::WZR;
105  break;
106  case AArch64::GPR64RegClassID:
107  NewReg = AArch64::XZR;
108  break;
109  }
110  DEBUG(dbgs() << " Replacing with zero register. New:\n ");
111  MO.setReg(NewReg);
112  DEBUG(MI.print(dbgs()));
113  ++NumDeadDefsReplaced;
114  }
115  }
116  }
117  return Changed;
118 }
119 
120 // Scan the function for instructions that have a dead definition of a
121 // register. Replace that register with the zero register when possible.
122 bool AArch64DeadRegisterDefinitions::runOnMachineFunction(MachineFunction &MF) {
123  TRI = MF.getSubtarget().getRegisterInfo();
124  bool Changed = false;
125  DEBUG(dbgs() << "***** AArch64DeadRegisterDefinitions *****\n");
126 
127  for (auto &MBB : MF)
128  if (processMachineBasicBlock(MBB))
129  Changed = true;
130  return Changed;
131 }
132 
134  return new AArch64DeadRegisterDefinitions();
135 }
bool isImplicit() const
STATISTIC(NumFunctions,"Total number of functions")
iterator_range< mop_iterator > uses()
Definition: MachineInstr.h:325
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:191
bool isDead() const
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:264
F(f)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Reg
All possible values of the reg field in the ModR/M byte.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
void print(raw_ostream &OS, bool SkipOpers=false) const
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx=nullptr) const
Given the index of a register def operand, check if the register def is tied to a source operand...
Definition: MachineInstr.h:995
Represent the analysis usage information of a pass.
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:294
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
MachineOperand class - Representation of each machine instruction operand.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:263
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:123
iterator_range< mop_iterator > implicit_operands()
Definition: MachineInstr.h:309
Representation of each machine instruction.
Definition: MachineInstr.h:51
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:62
void setReg(unsigned Reg)
Change the register this operand corresponds to.
unsigned getReg() const
getReg - Returns the register number.
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:149
#define DEBUG(X)
Definition: Debug.h:92
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
FunctionPass * createAArch64DeadRegisterDefinitions()