27 #define DEBUG_TYPE "mips-disassembler"
40 IsBigEndian(IsBigEndian) {}
42 bool hasMips3()
const {
return STI.
getFeatureBits()[Mips::FeatureMips3]; }
43 bool hasMips32()
const {
return STI.
getFeatureBits()[Mips::FeatureMips32]; }
44 bool hasMips32r6()
const {
48 bool isGP64()
const {
return STI.
getFeatureBits()[Mips::FeatureGP64Bit]; }
50 bool hasCnMips()
const {
return STI.
getFeatureBits()[Mips::FeatureCnMips]; }
52 bool hasCOP3()
const {
54 return !hasMips32() && !hasMips3();
100 const void *Decoder);
105 const void *Decoder);
110 const void *Decoder);
115 const void *Decoder);
120 const void *Decoder);
125 const void *Decoder);
129 const void *Decoder);
134 const void *Decoder);
139 const void *Decoder);
144 const void *Decoder);
149 const void *Decoder);
154 const void *Decoder);
159 const void *Decoder);
164 const void *Decoder);
169 const void *Decoder);
174 const void *Decoder);
179 const void *Decoder);
184 const void *Decoder);
189 const void *Decoder);
194 const void *Decoder);
199 const void *Decoder);
204 const void *Decoder);
209 const void *Decoder);
216 const void *Decoder);
223 const void *Decoder);
230 const void *Decoder);
237 const void *Decoder);
242 const void *Decoder);
247 const void *Decoder);
252 const void *Decoder);
257 const void *Decoder);
262 const void *Decoder);
265 uint64_t
Address,
const void *Decoder);
270 const void *Decoder);
275 const void *Decoder);
280 const void *Decoder);
285 const void *Decoder);
290 const void *Decoder);
295 const void *Decoder);
299 const void *Decoder);
303 const void *Decoder);
307 const void *Decoder);
311 const void *Decoder);
316 const void *Decoder);
321 const void *Decoder);
326 const void *Decoder);
331 const void *Decoder);
336 const void *Decoder);
341 const void *Decoder);
348 const void *Decoder);
353 const void *Decoder);
358 const void *Decoder);
361 uint64_t
Address,
const void *Decoder);
364 uint64_t
Address,
const void *Decoder);
367 uint64_t
Address,
const void *Decoder);
370 uint64_t
Address,
const void *Decoder);
373 uint64_t
Address,
const void *Decoder);
376 uint64_t
Address,
const void *Decoder);
380 template <
typename InsnType>
382 const void *Decoder);
384 template <
typename InsnType>
387 const void *Decoder);
389 template <
typename InsnType>
392 const void *Decoder);
394 template <
typename InsnType>
397 const void *Decoder);
399 template <
typename InsnType>
402 const void *Decoder);
404 template <
typename InsnType>
407 const void *Decoder);
409 template <
typename InsnType>
412 const void *Decoder);
416 const void *Decoder);
420 const void *Decoder);
424 const void *Decoder);
435 return new MipsDisassembler(STI, Ctx,
true);
442 return new MipsDisassembler(STI, Ctx,
false);
457 #include "MipsGenDisassemblerTables.inc"
459 static unsigned getReg(
const void *D,
unsigned RC,
unsigned RegNo) {
460 const MipsDisassembler *Dis =
static_cast<const MipsDisassembler*
>(D);
461 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
465 template <
typename InsnType>
467 const void *Decoder) {
471 InsnType tmp = fieldFromInstruction(insn, 17, 5);
473 DecodeFN RegDecoder =
nullptr;
474 if ((tmp & 0x18) == 0x00) {
477 }
else if ((tmp & 0x1c) == 0x10) {
480 }
else if ((tmp & 0x1e) == 0x18) {
483 }
else if ((tmp & 0x1f) == 0x1c) {
489 assert(NSize != 0 && RegDecoder !=
nullptr);
492 tmp = fieldFromInstruction(insn, 6, 5);
499 tmp = fieldFromInstruction(insn, 16, NSize);
502 tmp = fieldFromInstruction(insn, 11, 5);
511 template <
typename InsnType>
514 const void *Decoder) {
525 InsnType Rs = fieldFromInstruction(insn, 21, 5);
526 InsnType Rt = fieldFromInstruction(insn, 16, 5);
527 InsnType Imm =
SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
533 }
else if (Rs != 0 && Rs < Rt) {
550 template <
typename InsnType>
553 const void *Decoder) {
564 InsnType Rs = fieldFromInstruction(insn, 21, 5);
565 InsnType Rt = fieldFromInstruction(insn, 16, 5);
566 InsnType Imm =
SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
572 }
else if (Rs != 0 && Rs < Rt) {
589 template <
typename InsnType>
592 const void *Decoder) {
604 InsnType Rs = fieldFromInstruction(insn, 21, 5);
605 InsnType Rt = fieldFromInstruction(insn, 16, 5);
606 InsnType Imm =
SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
632 template <
typename InsnType>
635 const void *Decoder) {
649 InsnType Rs = fieldFromInstruction(insn, 21, 5);
650 InsnType Rt = fieldFromInstruction(insn, 16, 5);
651 InsnType Imm =
SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
676 template <
typename InsnType>
679 const void *Decoder) {
691 InsnType Rs = fieldFromInstruction(insn, 21, 5);
692 InsnType Rt = fieldFromInstruction(insn, 16, 5);
693 InsnType Imm =
SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
700 }
else if (Rs == 0) {
703 }
else if (Rs == Rt) {
725 template <
typename InsnType>
728 const void *Decoder) {
740 InsnType Rs = fieldFromInstruction(insn, 21, 5);
741 InsnType Rt = fieldFromInstruction(insn, 16, 5);
742 InsnType Imm =
SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
770 uint64_t &Size, uint32_t &Insn,
773 if (Bytes.
size() < 2) {
779 Insn = (Bytes[0] << 8) | Bytes[1];
781 Insn = (Bytes[1] << 8) | Bytes[0];
790 uint64_t &Size, uint32_t &Insn,
791 bool IsBigEndian,
bool IsMicroMips) {
793 if (Bytes.
size() < 4) {
809 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
812 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
815 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
834 DEBUG(
dbgs() <<
"Trying MicroMips16 table (16-bit instructions):\n");
848 DEBUG(
dbgs() <<
"Trying MicroMips32r632 table (32-bit instructions):\n");
853 DEBUG(
dbgs() <<
"Trying MicroMips32 table (32-bit instructions):\n");
870 DEBUG(
dbgs() <<
"Trying COP3_ table (32-bit opcodes):\n");
879 if (hasMips32r6() && isGP64()) {
880 DEBUG(
dbgs() <<
"Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
890 DEBUG(
dbgs() <<
"Trying Mips32r6_64r6 table (32-bit opcodes):\n");
900 DEBUG(
dbgs() <<
"Trying CnMips table (32-bit opcodes):\n");
910 DEBUG(
dbgs() <<
"Trying Mips64 (GPR64) table (32-bit opcodes):\n");
919 DEBUG(
dbgs() <<
"Trying Mips table (32-bit opcodes):\n");
934 const void *Decoder) {
943 const void *Decoder) {
948 unsigned Reg =
getReg(Decoder, Mips::GPR64RegClassID, RegNo);
956 const void *Decoder) {
959 unsigned Reg =
getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
967 const void *Decoder) {
970 unsigned Reg =
getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);
978 const void *Decoder) {
981 unsigned Reg =
getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo);
989 const void *Decoder) {
992 unsigned Reg =
getReg(Decoder, Mips::GPR32RegClassID, RegNo);
1000 const void *Decoder) {
1001 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64())
1010 const void *Decoder) {
1017 const void *Decoder) {
1021 unsigned Reg =
getReg(Decoder, Mips::FGR64RegClassID, RegNo);
1029 const void *Decoder) {
1033 unsigned Reg =
getReg(Decoder, Mips::FGR32RegClassID, RegNo);
1041 const void *Decoder) {
1044 unsigned Reg =
getReg(Decoder, Mips::CCRRegClassID, RegNo);
1052 const void *Decoder) {
1055 unsigned Reg =
getReg(Decoder, Mips::FCCRegClassID, RegNo);
1062 const void *Decoder) {
1066 unsigned Reg =
getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
1074 const void *Decoder) {
1075 int Offset = SignExtend32<16>(Insn & 0xffff);
1076 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1077 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1079 Reg =
getReg(Decoder, Mips::GPR32RegClassID, Reg);
1080 Base =
getReg(Decoder, Mips::GPR32RegClassID, Base);
1097 const void *Decoder) {
1098 int Offset = SignExtend32<16>(Insn & 0xffff);
1099 unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1100 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1102 Base =
getReg(Decoder, Mips::GPR32RegClassID, Base);
1114 const void *Decoder) {
1115 int Offset = SignExtend32<12>(Insn & 0xfff);
1116 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1117 unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1119 Base =
getReg(Decoder, Mips::GPR32RegClassID, Base);
1131 const void *Decoder) {
1132 int Offset = fieldFromInstruction(Insn, 7, 9);
1133 unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1134 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1136 Base =
getReg(Decoder, Mips::GPR32RegClassID, Base);
1148 const void *Decoder) {
1149 int Offset = SignExtend32<16>(Insn & 0xffff);
1150 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1152 Base =
getReg(Decoder, Mips::GPR32RegClassID, Base);
1161 uint64_t Address,
const void *Decoder) {
1162 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
1163 unsigned Reg = fieldFromInstruction(Insn, 6, 5);
1164 unsigned Base = fieldFromInstruction(Insn, 11, 5);
1166 Reg =
getReg(Decoder, Mips::MSA128BRegClassID, Reg);
1167 Base =
getReg(Decoder, Mips::GPR32RegClassID, Base);
1182 assert (0 &&
"Unexpected instruction");
1209 const void *Decoder) {
1210 unsigned Offset = Insn & 0xf;
1211 unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1212 unsigned Base = fieldFromInstruction(Insn, 4, 3);
1215 case Mips::LBU16_MM:
1216 case Mips::LHU16_MM:
1236 case Mips::LBU16_MM:
1245 case Mips::LHU16_MM:
1261 const void *Decoder) {
1262 unsigned Offset = Insn & 0x1F;
1263 unsigned Reg = fieldFromInstruction(Insn, 5, 5);
1265 Reg =
getReg(Decoder, Mips::GPR32RegClassID, Reg);
1277 const void *Decoder) {
1278 unsigned Offset = Insn & 0x7F;
1279 unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1281 Reg =
getReg(Decoder, Mips::GPR32RegClassID, Reg);
1293 const void *Decoder) {
1294 int Offset = SignExtend32<4>(Insn & 0xf);
1309 const void *Decoder) {
1310 int Offset = SignExtend32<12>(Insn & 0x0fff);
1311 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1312 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1314 Reg =
getReg(Decoder, Mips::GPR32RegClassID, Reg);
1315 Base =
getReg(Decoder, Mips::GPR32RegClassID, Base);
1318 case Mips::SWM32_MM:
1319 case Mips::LWM32_MM:
1344 const void *Decoder) {
1345 int Offset = SignExtend32<16>(Insn & 0xffff);
1346 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1347 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1349 Reg =
getReg(Decoder, Mips::GPR32RegClassID, Reg);
1350 Base =
getReg(Decoder, Mips::GPR32RegClassID, Base);
1362 const void *Decoder) {
1363 int Offset = SignExtend32<16>(Insn & 0xffff);
1364 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1365 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1367 Reg =
getReg(Decoder, Mips::FGR64RegClassID, Reg);
1368 Base =
getReg(Decoder, Mips::GPR32RegClassID, Base);
1380 const void *Decoder) {
1381 int Offset = SignExtend32<16>(Insn & 0xffff);
1382 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1383 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1385 Reg =
getReg(Decoder, Mips::COP2RegClassID, Reg);
1386 Base =
getReg(Decoder, Mips::GPR32RegClassID, Base);
1398 const void *Decoder) {
1399 int Offset = SignExtend32<16>(Insn & 0xffff);
1400 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1401 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1403 Reg =
getReg(Decoder, Mips::COP3RegClassID, Reg);
1404 Base =
getReg(Decoder, Mips::GPR32RegClassID, Base);
1416 const void *Decoder) {
1417 int Offset = SignExtend32<11>(Insn & 0x07ff);
1418 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1419 unsigned Base = fieldFromInstruction(Insn, 11, 5);
1421 Reg =
getReg(Decoder, Mips::COP2RegClassID, Reg);
1422 Base =
getReg(Decoder, Mips::GPR32RegClassID, Base);
1433 const void *Decoder) {
1434 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
1435 unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1436 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1438 Rt =
getReg(Decoder, Mips::GPR32RegClassID, Rt);
1439 Base =
getReg(Decoder, Mips::GPR32RegClassID, Base);
1455 const void *Decoder) {
1466 const void *Decoder) {
1467 if (RegNo > 30 || RegNo %2)
1471 unsigned Reg =
getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
1479 const void *Decoder) {
1483 unsigned Reg =
getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
1491 const void *Decoder) {
1495 unsigned Reg =
getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
1503 const void *Decoder) {
1507 unsigned Reg =
getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
1515 const void *Decoder) {
1519 unsigned Reg =
getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
1527 const void *Decoder) {
1531 unsigned Reg =
getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
1539 const void *Decoder) {
1543 unsigned Reg =
getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
1551 const void *Decoder) {
1555 unsigned Reg =
getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
1563 const void *Decoder) {
1567 unsigned Reg =
getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
1575 const void *Decoder) {
1579 unsigned Reg =
getReg(Decoder, Mips::COP0RegClassID, RegNo);
1587 const void *Decoder) {
1591 unsigned Reg =
getReg(Decoder, Mips::COP2RegClassID, RegNo);
1599 const void *Decoder) {
1600 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
1608 const void *Decoder) {
1610 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1618 const void *Decoder) {
1619 int32_t BranchOffset = SignExtend32<21>(Offset) * 4;
1628 const void *Decoder) {
1629 int32_t BranchOffset = SignExtend32<26>(Offset) * 4;
1638 const void *Decoder) {
1639 int32_t BranchOffset = SignExtend32<7>(Offset) << 1;
1647 const void *Decoder) {
1648 int32_t BranchOffset = SignExtend32<10>(Offset) << 1;
1656 const void *Decoder) {
1657 int32_t BranchOffset = SignExtend32<16>(Offset) * 2;
1665 const void *Decoder) {
1666 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1674 const void *Decoder) {
1677 else if (Value == 0x7)
1687 const void *Decoder) {
1695 const void *Decoder) {
1706 const void *Decoder) {
1714 const void *Decoder) {
1722 const void *Decoder) {
1731 const void *Decoder) {
1734 int Size = (
int) Insn - Pos + 1;
1742 const void *Decoder) {
1743 int Size = (
int) Insn + 1;
1749 uint64_t Address,
const void *Decoder) {
1755 uint64_t Address,
const void *Decoder) {
1761 uint64_t Address,
const void *Decoder) {
1762 int32_t DecodedValue;
1764 case 0: DecodedValue = 256;
break;
1765 case 1: DecodedValue = 257;
break;
1766 case 510: DecodedValue = -258;
break;
1767 case 511: DecodedValue = -257;
break;
1768 default: DecodedValue = SignExtend32<9>(Insn);
break;
1775 uint64_t Address,
const void *Decoder) {
1778 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
1785 uint64_t Address,
const void *Decoder) {
1793 const void *Decoder) {
1794 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
1795 Mips::S6, Mips::FP};
1798 unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
1803 RegNum = RegLst & 0xf;
1804 for (
unsigned i = 0; i < RegNum; i++)
1815 const void *Decoder) {
1816 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
1817 unsigned RegLst = fieldFromInstruction(Insn, 4, 2);
1818 unsigned RegNum = RegLst & 0x3;
1820 for (
unsigned i = 0; i <= RegNum; i++)
1829 uint64_t Address,
const void *Decoder) {
1831 unsigned RegPair = fieldFromInstruction(Insn, 7, 3);
1874 uint64_t Address,
const void *Decoder) {
static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSimm16(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBranchTarget21(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
INSVE_[BHWD] have an implicit operand that the generated decoder doesn't handle.
static DecodeStatus DecodeCacheOpR6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
DecodeStatus
Ternary decode status.
static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Superclass for all disassemblers.
static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBranchTarget(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSyncI(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static MCDisassembler * createMipsDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
aarch64 collect AArch64 Collect Linker Optimization Hint(LOH)"
static DecodeStatus DecodeMemMMImm4(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static MCOperand createReg(unsigned Reg)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Reg
All possible values of the reg field in the ModR/M byte.
static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Context object for machine code objects.
static DecodeStatus DecodeMemMMImm12(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
int decodeInstruction(InternalInstruction *insn, byteReader_t reader, const void *readerArg, dlog_t logger, void *loggerArg, const void *miiArg, uint64_t startLoc, DisassemblerMode mode)
Decode one instruction and store the decoding results in a buffer provided by the consumer...
static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
size_t size() const
size - Get the array size.
static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Instances of this class represent a single low-level machine instruction.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
static DecodeStatus DecodeExtSize(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static MCDisassembler * createMipselDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
void LLVMInitializeMipsDisassembler()
static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeCacheOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
void setOpcode(unsigned Op)
int64_t SignExtend64(uint64_t x)
SignExtend64 - Sign extend B-bit number x to 64-bit int.
static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus readInstruction16(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsBigEndian)
Read two bytes from the ArrayRef and return 16 bit halfword sorted according to the given endianess...
static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
CHAIN = SC CHAIN, Imm128 - System call.
static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
unsigned getOpcode() const
Target - Wrapper for Target specific information.
static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
static DecodeStatus DecodeSimm4(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
MCDisassembler::DecodeStatus DecodeStatus
static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeLSAImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
MCSubtargetInfo - Generic base class for all target subtargets.
static DecodeStatus DecodeBranchTarget26(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
iterator begin() const
begin/end - Return all of the registers in this class.
static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
LLVM Value Representation.
static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeJumpTarget(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
This class implements an extremely fast bulk output stream that can only output to a stream...
static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
void addOperand(const MCOperand &Op)
static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus readInstruction32(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsBigEndian, bool IsMicroMips)
Read four bytes from the ArrayRef and return 32 bit word sorted according to the given endianess...
static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static MCOperand createImm(int64_t Val)
static DecodeStatus DecodeLiSimm7(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
const MCOperand & getOperand(unsigned i) const
static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMemMMImm16(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder)