26 const char *
const *SRINames,
27 const unsigned *SRILaneMasks,
28 unsigned SRICoveringLanes)
29 : InfoDesc(ID), SubRegIndexNames(SRINames),
30 SubRegIndexLaneMasks(SRILaneMasks),
31 RegClassBegin(RCB), RegClassEnd(RCE),
32 CoveringLanes(SRICoveringLanes) {
44 else if (TRI && Reg < TRI->getNumRegs())
47 OS <<
"%physreg" << Reg;
52 OS <<
":sub(" << SubIdx <<
')';
59 OS <<
"Unit~" <<
Unit;
65 OS <<
"BadUnit~" <<
Unit;
71 assert(Roots.
isValid() &&
"Unit has no roots.");
73 for (++Roots; Roots.
isValid(); ++Roots)
94 Base < BaseE; Base += 32) {
96 for (
unsigned Mask = *SubClass++; Mask; Mask >>= 1) {
125 assert(BestRC &&
"Couldn't find the register class");
133 assert(RC->
isAllocatable() &&
"invalid for nonallocatable sets");
135 for (
unsigned i = 0; i != Order.size(); ++i)
150 if ((*I)->isAllocatable())
156 Allocatable &= Reserved.
flip();
166 if (
unsigned Common = *A++ & *B++)
188 unsigned Idx)
const {
189 assert(A && B &&
"Missing register class");
190 assert(Idx &&
"Bad sub-register index");
194 if (RCI.getSubReg() == Idx)
204 unsigned &PreA,
unsigned &PreB)
const {
205 assert(RCA && SubA && RCB && SubB &&
"Invalid arguments");
220 unsigned *BestPreA = &PreA;
221 unsigned *BestPreB = &PreB;
230 unsigned MinSize = RCA->
getSize();
238 if (!RC || RC->
getSize() < MinSize)
243 if (FinalA != FinalB)
252 *BestPreA = IA.getSubReg();
253 *BestPreB = IB.getSubReg();
256 if (BestRC->
getSize() == MinSize)
276 assert(Hint.first == 0 &&
"Target must implement TRI::getRegAllocationHints");
279 unsigned Phys = Hint.second;
291 if (std::find(Order.
begin(), Order.
end(), Phys) == Order.
end())
298 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
bool hasType(MVT vt) const
hasType - return true if this TargetRegisterClass has the ValueType vt.
void push_back(const T &Elt)
bool isValid() const
Check if the iterator is at the end of the list.
TargetRegisterInfo(const TargetRegisterInfoDesc *ID, regclass_iterator RegClassBegin, regclass_iterator RegClassEnd, const char *const *SRINames, const unsigned *SRILaneMasks, unsigned CoveringLanes)
void print(raw_ostream &) const
static unsigned virtReg2Index(unsigned Reg)
virtReg2Index - Convert a virtual register number to a 0-based index.
virtual ~TargetRegisterInfo()
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
static void dumpReg(unsigned Reg, unsigned SubRegIndex=0, const TargetRegisterInfo *TRI=nullptr)
Debugging helper: dump register in human readable form to dbgs() stream.
void print(raw_ostream &) const
regclass_iterator regclass_end() const
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const
getCommonSubClass - find the largest common subclass of A and B.
aarch64 collect AArch64 Collect Linker Optimization Hint(LOH)"
static int stackSlot2Index(unsigned Reg)
stackSlot2Index - Compute the frame index from a register value representing a stack slot...
unsigned getSize() const
getSize - Return the size of the register in bytes, which is also the size of a stack slot allocated ...
unsigned getNumRegClasses() const
const TargetRegisterClass * getRegClass(unsigned i) const
getRegClass - Returns the register class associated with the enumeration value.
ArrayRef< MCPhysReg > getRawAllocationOrder(const MachineFunction &MF) const
getRawAllocationOrder - Returns the preferred order for allocating registers from this register class...
Reg
All possible values of the reg field in the ModR/M byte.
PrintReg - Helper class for printing registers on a raw_ostream.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
MCRegUnitRootIterator enumerates the root registers of a register unit.
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
getMatchingSuperRegClass - Return a subclass of the specified register class A so that each register ...
BitVector getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const
getAllocatableSet - Returns a bitset indexed by register number indicating if a register is allocatab...
MCRegisterClass - Base class of TargetRegisterClass.
const TargetRegisterClass * getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA, const TargetRegisterClass *RCB, unsigned SubB, unsigned &PreA, unsigned &PreB) const
getCommonSuperRegClass - Find a common super-register class if it exists.
std::size_t countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the least significant bit to the most stopping at the first 1...
regclass_iterator regclass_begin() const
Register class iterators.
MVT - Machine Value Type.
bool isReserved(unsigned PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
TargetRegisterInfoDesc - Extra information, not in MCRegisterDesc, about registers.
virtual void getRegAllocationHints(unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr) const
Get a list of 'hint' registers that the register allocator should try first when allocating a physica...
const TargetRegisterClass * getAllocatableClass(const TargetRegisterClass *RC) const
getAllocatableClass - Return the maximal subclass of the given register class that is alloctable...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool hasSubClass(const TargetRegisterClass *RC) const
hasSubClass - return true if the specified TargetRegisterClass is a proper sub-class of this TargetRe...
void print(raw_ostream &) const
static bool isStackSlot(unsigned Reg)
isStackSlot - Sometimes it is useful the be able to store a non-negative frame index in a variable th...
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
static void getAllocatableSetForRC(const MachineFunction &MF, const TargetRegisterClass *RC, BitVector &R)
getAllocatableSetForRC - Toggle the bits that represent allocatable registers for the specific regist...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a ...
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
getMinimalPhysRegClass - Returns the Register Class of a physical register of the given type...
const char * getSubRegIndexName(unsigned SubIdx) const
getSubRegIndexName - Return the human-readable symbolic target-specific name for the specified SubReg...
unsigned getNumRegUnits() const
Return the number of (native) register units in the target.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
static bool isPhysicalRegister(unsigned Reg)
isPhysicalRegister - Return true if the specified register number is in the physical register namespa...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool isAllocatable() const
isAllocatable - Return true if this register class may be used to create virtual registers.
This class implements an extremely fast bulk output stream that can only output to a stream...
const char * getName(unsigned RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register...
static const TargetRegisterClass * firstCommonClass(const uint32_t *A, const uint32_t *B, const TargetRegisterInfo *TRI)
unsigned getPhys(unsigned virtReg) const
returns the physical register mapped to the specified virtual register
unsigned composeSubRegIndices(unsigned a, unsigned b) const
composeSubRegIndices - Return the subregister index you get from composing two subregister indices...
std::pair< unsigned, unsigned > getRegAllocationHint(unsigned VReg) const
getRegAllocationHint - Return the register allocation hint for the specified virtual register...
const TargetRegisterInfo * TRI
const uint32_t * getSubClassMask() const
getSubClassMask - Returns a bit vector of subclasses, including this one.
const TargetRegisterClass *const * regclass_iterator
bool contains(unsigned Reg) const
contains - Return true if the specified register is included in this register class.