LLVM  3.7.0
Public Member Functions | Static Public Member Functions | List of all members
llvm::X86InstrInfo Class Referencefinal

#include <X86InstrInfo.h>

Inheritance diagram for llvm::X86InstrInfo:
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Collaboration diagram for llvm::X86InstrInfo:
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Public Member Functions

 X86InstrInfo (X86Subtarget &STI)
 
const X86RegisterInfogetRegisterInfo () const
 getRegisterInfo - TargetInstrInfo is a superset of MRegister info. More...
 
int getSPAdjust (const MachineInstr *MI) const override
 getSPAdjust - This returns the stack pointer adjustment made by this instruction. More...
 
bool isCoalescableExtInstr (const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override
 isCoalescableExtInstr - Return true if the instruction is a "coalescable" extension instruction. More...
 
unsigned isLoadFromStackSlot (const MachineInstr *MI, int &FrameIndex) const override
 
unsigned isLoadFromStackSlotPostFE (const MachineInstr *MI, int &FrameIndex) const override
 isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well. More...
 
unsigned isStoreToStackSlot (const MachineInstr *MI, int &FrameIndex) const override
 
unsigned isStoreToStackSlotPostFE (const MachineInstr *MI, int &FrameIndex) const override
 isStoreToStackSlotPostFE - Check for post-frame ptr elimination stack locations as well. More...
 
bool isReallyTriviallyReMaterializable (const MachineInstr *MI, AliasAnalysis *AA) const override
 
void reMaterialize (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SubIdx, const MachineInstr *Orig, const TargetRegisterInfo &TRI) const override
 
bool classifyLEAReg (MachineInstr *MI, const MachineOperand &Src, unsigned LEAOpcode, bool AllowSP, unsigned &NewSrc, bool &isKill, bool &isUndef, MachineOperand &ImplicitOp) const
 Given an operand within a MachineInstr, insert preceding code to put it into the right format for a particular kind of LEA instruction. More...
 
MachineInstrconvertToThreeAddress (MachineFunction::iterator &MFI, MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const override
 convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag. More...
 
MachineInstrcommuteInstruction (MachineInstr *MI, bool NewMI) const override
 commuteInstruction - We have a few instructions that must be hacked on to commute them. More...
 
bool findCommutedOpIndices (MachineInstr *MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
 
bool isUnpredicatedTerminator (const MachineInstr *MI) const override
 
bool AnalyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
 
bool getMemOpBaseRegImmOfs (MachineInstr *LdSt, unsigned &BaseReg, unsigned &Offset, const TargetRegisterInfo *TRI) const override
 
bool AnalyzeBranchPredicate (MachineBasicBlock &MBB, TargetInstrInfo::MachineBranchPredicate &MBP, bool AllowModify=false) const override
 
unsigned RemoveBranch (MachineBasicBlock &MBB) const override
 
unsigned InsertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, DebugLoc DL) const override
 
bool canInsertSelect (const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override
 
void insertSelect (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
 
void copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
 
void storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
 
void storeRegToAddr (MachineFunction &MF, unsigned SrcReg, bool isKill, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, MachineInstr::mmo_iterator MMOBegin, MachineInstr::mmo_iterator MMOEnd, SmallVectorImpl< MachineInstr * > &NewMIs) const
 
void loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
 
void loadRegFromAddr (MachineFunction &MF, unsigned DestReg, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, MachineInstr::mmo_iterator MMOBegin, MachineInstr::mmo_iterator MMOEnd, SmallVectorImpl< MachineInstr * > &NewMIs) const
 
bool expandPostRAPseudo (MachineBasicBlock::iterator MI) const override
 
MachineInstrfoldMemoryOperandImpl (MachineFunction &MF, MachineInstr *MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex) const override
 foldMemoryOperand - If this target supports it, fold a load or store of the specified stack slot into the specified machine instruction for the specified operand(s). More...
 
MachineInstrfoldMemoryOperandImpl (MachineFunction &MF, MachineInstr *MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr *LoadMI) const override
 foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address, not just from a specific stack slot. More...
 
bool canFoldMemoryOperand (const MachineInstr *, ArrayRef< unsigned >) const override
 canFoldMemoryOperand - Returns true if the specified load / store is folding is possible. More...
 
bool unfoldMemoryOperand (MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const override
 unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a store into two or more instruction. More...
 
bool unfoldMemoryOperand (SelectionDAG &DAG, SDNode *N, SmallVectorImpl< SDNode * > &NewNodes) const override
 
unsigned getOpcodeAfterMemoryUnfold (unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const override
 getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new instruction after load / store are unfolded from an instruction of the specified opcode. More...
 
bool areLoadsFromSameBasePtr (SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
 areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address. More...
 
bool shouldScheduleLoadsNear (SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override
 shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePtr) if two loads should be scheduled togther. More...
 
bool shouldScheduleAdjacent (MachineInstr *First, MachineInstr *Second) const override
 
void getNoopForMachoTarget (MCInst &NopInst) const override
 Return the noop instruction to use for a noop. More...
 
bool ReverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
 
bool isSafeToMoveRegClassDefs (const TargetRegisterClass *RC) const override
 isSafeToMoveRegClassDefs - Return true if it's safe to move a machine instruction that defines the specified register class. More...
 
bool isSafeToClobberEFLAGS (MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const
 isSafeToClobberEFLAGS - Return true if it's safe insert an instruction tha would clobber the EFLAGS condition register. More...
 
unsigned getGlobalBaseReg (MachineFunction *MF) const
 getGlobalBaseReg - Return a virtual register initialized with the the global base register value. More...
 
std::pair< uint16_t, uint16_t > getExecutionDomain (const MachineInstr *MI) const override
 
void setExecutionDomain (MachineInstr *MI, unsigned Domain) const override
 
unsigned getPartialRegUpdateClearance (const MachineInstr *MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override
 Inform the ExeDepsFix pass how many idle instructions we would like before a partial register update. More...
 
unsigned getUndefRegClearance (const MachineInstr *MI, unsigned &OpNum, const TargetRegisterInfo *TRI) const override
 Inform the ExeDepsFix pass how many idle instructions we would like before certain undef register reads. More...
 
void breakPartialRegDependency (MachineBasicBlock::iterator MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override
 
MachineInstrfoldMemoryOperandImpl (MachineFunction &MF, MachineInstr *MI, unsigned OpNum, ArrayRef< MachineOperand > MOs, MachineBasicBlock::iterator InsertPt, unsigned Size, unsigned Alignment, bool AllowCommute) const
 
void getUnconditionalBranch (MCInst &Branch, const MCSymbolRefExpr *BranchTarget) const override
 
void getTrap (MCInst &MI) const override
 
unsigned getJumpInstrTableEntryBound () const override
 
bool isHighLatencyDef (int opc) const override
 
bool hasHighOperandLatency (const TargetSchedModel &SchedModel, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const override
 
bool useMachineCombiner () const override
 
bool getMachineCombinerPatterns (MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern::MC_PATTERN > &P) const override
 Return true when there is potentially a faster code sequence for an instruction chain ending in <Root>. More...
 
void genAlternativeCodeSequence (MachineInstr &Root, MachineCombinerPattern::MC_PATTERN P, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
 When getMachineCombinerPatterns() finds a pattern, this function generates the instructions that could replace the original code sequence. More...
 
bool analyzeCompare (const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const override
 analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue. More...
 
bool optimizeCompareInstr (MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const override
 optimizeCompareInstr - Check if there exists an earlier instruction that operates on the same source operands and sets flags in the same way as Compare; remove Compare if possible. More...
 
MachineInstroptimizeLoadInstr (MachineInstr *MI, const MachineRegisterInfo *MRI, unsigned &FoldAsLoadDefReg, MachineInstr *&DefMI) const override
 optimizeLoadInstr - Try to remove the load by folding it to a register operand at the use. More...
 

Static Public Member Functions

static bool isX86_64ExtendedReg (const MachineOperand &MO)
 

Detailed Description

Definition at line 154 of file X86InstrInfo.h.

Constructor & Destructor Documentation

X86InstrInfo::X86InstrInfo ( X86Subtarget STI)
explicit

Member Function Documentation

bool X86InstrInfo::AnalyzeBranch ( MachineBasicBlock MBB,
MachineBasicBlock *&  TBB,
MachineBasicBlock *&  FBB,
SmallVectorImpl< MachineOperand > &  Cond,
bool  AllowModify 
) const
override

Definition at line 3582 of file X86InstrInfo.cpp.

bool X86InstrInfo::AnalyzeBranchPredicate ( MachineBasicBlock MBB,
TargetInstrInfo::MachineBranchPredicate MBP,
bool  AllowModify = false 
) const
override
bool X86InstrInfo::analyzeCompare ( const MachineInstr MI,
unsigned SrcReg,
unsigned SrcReg2,
int CmpMask,
int CmpValue 
) const
override

analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue.

Return true if the comparison instruction can be analyzed.

Definition at line 4143 of file X86InstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::getReg().

bool X86InstrInfo::areLoadsFromSameBasePtr ( SDNode Load1,
SDNode Load2,
int64_t &  Offset1,
int64_t &  Offset2 
) const
override

areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address.

It should only return true if the base pointers are the same and the only differences between the two addresses are the offset. It also returns the offsets by reference.

Definition at line 5769 of file X86InstrInfo.cpp.

References llvm::SDNode::getMachineOpcode(), llvm::SDNode::getOperand(), and llvm::SDNode::isMachineOpcode().

void X86InstrInfo::breakPartialRegDependency ( MachineBasicBlock::iterator  MI,
unsigned  OpNum,
const TargetRegisterInfo TRI 
) const
override
bool X86InstrInfo::canFoldMemoryOperand ( const MachineInstr MI,
ArrayRef< unsigned Ops 
) const
override
bool X86InstrInfo::canInsertSelect ( const MachineBasicBlock MBB,
ArrayRef< MachineOperand Cond,
unsigned  TrueReg,
unsigned  FalseReg,
int CondCycles,
int TrueCycles,
int FalseCycles 
) const
override
bool X86InstrInfo::classifyLEAReg ( MachineInstr MI,
const MachineOperand Src,
unsigned  LEAOpcode,
bool  AllowSP,
unsigned NewSrc,
bool isKill,
bool isUndef,
MachineOperand ImplicitOp 
) const
MachineInstr * X86InstrInfo::commuteInstruction ( MachineInstr MI,
bool  NewMI 
) const
override
MachineInstr * X86InstrInfo::convertToThreeAddress ( MachineFunction::iterator MFI,
MachineBasicBlock::iterator MBBI,
LiveVariables LV 
) const
override

convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag.

This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag.

When this flag is set, the target may be able to convert a two-address instruction into a true three-address instruction on demand. This allows the X86 target (for example) to convert ADD and SHL instructions into LEA instructions if they would require register copies due to two-addressness.

This method returns a null pointer if the transformation cannot be performed, otherwise it returns the new instruction.

Definition at line 2653 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::addOffset(), llvm::MachineInstrBuilder::addOperand(), llvm::MachineInstrBuilder::addReg(), llvm::addRegReg(), llvm::BuildMI(), classifyLEAReg(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::MachineOperand::CreateReg(), llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getImm(), llvm::getKillRegState(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), getTruncatedShiftCount(), llvm::getUndefRegState(), hasLiveCondCodeDef(), llvm::X86Subtarget::is64Bit(), is64Bit(), llvm::MachineOperand::isDead(), llvm::MachineOperand::isKill(), isTruncatedShiftCountForLEA(), llvm::MachineOperand::isUndef(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::AArch64CC::MI, and llvm::LiveVariables::replaceKillInstruction().

void X86InstrInfo::copyPhysReg ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
DebugLoc  DL,
unsigned  DestReg,
unsigned  SrcReg,
bool  KillSrc 
) const
override
bool X86InstrInfo::expandPostRAPseudo ( MachineBasicBlock::iterator  MI) const
override
bool X86InstrInfo::findCommutedOpIndices ( MachineInstr MI,
unsigned SrcOpIdx1,
unsigned SrcOpIdx2 
) const
override
MachineInstr * X86InstrInfo::foldMemoryOperandImpl ( MachineFunction MF,
MachineInstr MI,
ArrayRef< unsigned Ops,
MachineBasicBlock::iterator  InsertPt,
int  FrameIndex 
) const
override

foldMemoryOperand - If this target supports it, fold a load or store of the specified stack slot into the specified machine instruction for the specified operand(s).

If this is possible, the target should perform the folding and return true, otherwise it should return false. If it folds the instruction, it is likely that the MachineInstruction the iterator references has been changed.

Definition at line 5230 of file X86InstrInfo.cpp.

References llvm::MachineOperand::ChangeToImmediate(), llvm::MachineOperand::CreateFI(), llvm::MachineFunction::getFrameInfo(), llvm::X86Subtarget::getFrameLowering(), llvm::MachineFunction::getFunction(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::TargetFrameLowering::getStackAlignment(), llvm::Function::hasFnAttribute(), hasPartialRegUpdate(), fuzzer::min(), llvm::X86RegisterInfo::needsStackRealignment(), NoFusing, llvm::Attribute::OptimizeForSize, llvm::MachineInstr::setDesc(), and llvm::ArrayRef< T >::size().

Referenced by foldMemoryOperandImpl().

MachineInstr * X86InstrInfo::foldMemoryOperandImpl ( MachineFunction MF,
MachineInstr MI,
ArrayRef< unsigned Ops,
MachineBasicBlock::iterator  InsertPt,
MachineInstr LoadMI 
) const
override

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address, not just from a specific stack slot.

Definition at line 5330 of file X86InstrInfo.cpp.

References llvm::X86::AddrNumOperands, llvm::SmallVectorImpl< T >::append(), llvm::C, llvm::MachineOperand::ChangeToImmediate(), llvm::MachineOperand::CreateCPI(), llvm::MachineOperand::CreateImm(), llvm::MachineOperand::CreateReg(), foldMemoryOperandImpl(), llvm::ISD::FrameIndex, llvm::VectorType::get(), llvm::Constant::getAllOnesValue(), llvm::TargetMachine::getCodeModel(), llvm::MachineFunction::getConstantPool(), llvm::MachineConstantPool::getConstantPoolIndex(), llvm::Function::getContext(), llvm::MachineInstr::getDesc(), llvm::Type::getDoubleTy(), llvm::Type::getFloatTy(), llvm::MachineFunction::getFunction(), llvm::Type::getInt32Ty(), llvm::Constant::getNullValue(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::TargetMachine::getRelocationModel(), llvm::MachineOperand::getSubReg(), llvm::MachineFunction::getTarget(), llvm::Function::hasFnAttribute(), llvm::MachineInstr::hasOneMemOperand(), hasPartialRegUpdate(), llvm::X86Subtarget::is64Bit(), isLoadFromStackSlot(), isNonFoldablePartialRegisterLoad(), llvm::CodeModel::Kernel, llvm::MachineInstr::memoperands_begin(), NoFusing, llvm::MachineInstr::operands_begin(), llvm::Attribute::OptimizeForSize, llvm::Reloc::PIC_, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::MachineInstr::setDesc(), llvm::ArrayRef< T >::size(), and llvm::CodeModel::Small.

MachineInstr * X86InstrInfo::foldMemoryOperandImpl ( MachineFunction MF,
MachineInstr MI,
unsigned  OpNum,
ArrayRef< MachineOperand MOs,
MachineBasicBlock::iterator  InsertPt,
unsigned  Size,
unsigned  Alignment,
bool  AllowCommute 
) const
void X86InstrInfo::genAlternativeCodeSequence ( MachineInstr Root,
MachineCombinerPattern::MC_PATTERN  P,
SmallVectorImpl< MachineInstr * > &  InsInstrs,
SmallVectorImpl< MachineInstr * > &  DelInstrs,
DenseMap< unsigned, unsigned > &  InstrIdxForVirtReg 
) const
override
std::pair< uint16_t, uint16_t > X86InstrInfo::getExecutionDomain ( const MachineInstr MI) const
override
unsigned X86InstrInfo::getGlobalBaseReg ( MachineFunction MF) const

getGlobalBaseReg - Return a virtual register initialized with the the global base register value.

Return a virtual register initialized with the the global base register value.

Output instructions required to initialize the register in the function entry block, if necessary.

Output instructions required to initialize the register in the function entry block, if necessary.

TODO: Eliminate this and move the code to X86MachineFunctionInfo.

Definition at line 6105 of file X86InstrInfo.cpp.

References llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MachineFunction::getInfo(), llvm::MachineFunction::getRegInfo(), llvm::PPCISD::GlobalBaseReg, and llvm::X86Subtarget::is64Bit().

unsigned X86InstrInfo::getJumpInstrTableEntryBound ( ) const
override

Definition at line 6259 of file X86InstrInfo.cpp.

bool X86InstrInfo::getMachineCombinerPatterns ( MachineInstr Root,
SmallVectorImpl< MachineCombinerPattern::MC_PATTERN > &  P 
) const
override
bool X86InstrInfo::getMemOpBaseRegImmOfs ( MachineInstr LdSt,
unsigned BaseReg,
unsigned Offset,
const TargetRegisterInfo TRI 
) const
override
void X86InstrInfo::getNoopForMachoTarget ( MCInst NopInst) const
override

Return the noop instruction to use for a noop.

Definition at line 6235 of file X86InstrInfo.cpp.

References llvm::MCInst::setOpcode().

unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold ( unsigned  Opc,
bool  UnfoldLoad,
bool  UnfoldStore,
unsigned LoadRegIndex = nullptr 
) const
override

getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new instruction after load / store are unfolded from an instruction of the specified opcode.

It returns zero if the specified unfolding is not possible. If LoadRegIndex is non-null, it is filled in with the operand index of the operand which will hold the register holding the loaded value.

Definition at line 5750 of file X86InstrInfo.cpp.

References llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::end(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::find(), TB_FOLDED_LOAD, TB_FOLDED_STORE, and TB_INDEX_MASK.

unsigned X86InstrInfo::getPartialRegUpdateClearance ( const MachineInstr MI,
unsigned  OpNum,
const TargetRegisterInfo TRI 
) const
override
const X86RegisterInfo& llvm::X86InstrInfo::getRegisterInfo ( ) const
inline

getRegisterInfo - TargetInstrInfo is a superset of MRegister info.

As such, whenever a client has an instance of instruction info, it should always be able to get register info as well (through this method).

Definition at line 195 of file X86InstrInfo.h.

Referenced by AnalyzeBranchPredicate(), classifyLEAReg(), llvm::X86Subtarget::getRegisterInfo(), and optimizeCompareInstr().

int X86InstrInfo::getSPAdjust ( const MachineInstr MI) const
override
void X86InstrInfo::getTrap ( MCInst MI) const
override

Definition at line 6253 of file X86InstrInfo.cpp.

References llvm::MCInst::setOpcode(), and llvm::ISD::TRAP.

void X86InstrInfo::getUnconditionalBranch ( MCInst Branch,
const MCSymbolRefExpr BranchTarget 
) const
override
unsigned X86InstrInfo::getUndefRegClearance ( const MachineInstr MI,
unsigned OpNum,
const TargetRegisterInfo TRI 
) const
override

Inform the ExeDepsFix pass how many idle instructions we would like before certain undef register reads.

This catches the VCVTSI2SD family of instructions:

vcvtsi2sdq rax, xmm0<undef>, xmm14

We should to be careful not to catch VXOR idioms which are presumably handled specially in the pipeline:

vxorps xmm1<undef>, xmm1<undef>, xmm1

Like getPartialRegUpdateClearance, this makes a strong assumption that the high bits that are passed-through are not live.

Definition at line 5188 of file X86InstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), hasUndefRegUpdate(), llvm::TargetRegisterInfo::isPhysicalRegister(), and llvm::MachineOperand::isUndef().

bool X86InstrInfo::hasHighOperandLatency ( const TargetSchedModel SchedModel,
const MachineRegisterInfo MRI,
const MachineInstr DefMI,
unsigned  DefIdx,
const MachineInstr UseMI,
unsigned  UseIdx 
) const
override

Definition at line 6343 of file X86InstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), and isHighLatencyDef().

unsigned X86InstrInfo::InsertBranch ( MachineBasicBlock MBB,
MachineBasicBlock TBB,
MachineBasicBlock FBB,
ArrayRef< MachineOperand Cond,
DebugLoc  DL 
) const
override
void X86InstrInfo::insertSelect ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
DebugLoc  DL,
unsigned  DstReg,
ArrayRef< MachineOperand Cond,
unsigned  TrueReg,
unsigned  FalseReg 
) const
override
bool X86InstrInfo::isCoalescableExtInstr ( const MachineInstr MI,
unsigned SrcReg,
unsigned DstReg,
unsigned SubIdx 
) const
override

isCoalescableExtInstr - Return true if the instruction is a "coalescable" extension instruction.

That is, it's like a copy where it's legal for the source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns true, then it's expected the pre-extension value is available as a subreg of the result register. This also returns the sub-register index in SubIdx.

Definition at line 2008 of file X86InstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::X86Subtarget::is64Bit(), and llvm_unreachable.

bool X86InstrInfo::isHighLatencyDef ( int  opc) const
override

Definition at line 6265 of file X86InstrInfo.cpp.

Referenced by hasHighOperandLatency().

unsigned X86InstrInfo::isLoadFromStackSlot ( const MachineInstr MI,
int FrameIndex 
) const
override
unsigned X86InstrInfo::isLoadFromStackSlotPostFE ( const MachineInstr MI,
int FrameIndex 
) const
override

isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well.

This uses a heuristic so it isn't reliable for correctness.

Definition at line 2199 of file X86InstrInfo.cpp.

References llvm::NVPTXISD::Dummy, llvm::MachineInstr::getOpcode(), isFrameLoadOpcode(), and isLoadFromStackSlot().

bool X86InstrInfo::isReallyTriviallyReMaterializable ( const MachineInstr MI,
AliasAnalysis AA 
) const
override
bool X86InstrInfo::isSafeToClobberEFLAGS ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I 
) const

isSafeToClobberEFLAGS - Return true if it's safe insert an instruction tha would clobber the EFLAGS condition register.

Note the result may be conservative. If it cannot definitely determine the safety after visiting a few instructions in each direction it assumes it's not safe.

Definition at line 2331 of file X86InstrInfo.cpp.

References llvm::MachineBasicBlock::begin(), llvm::MachineOperand::clobbersPhysReg(), llvm::MachineBasicBlock::end(), llvm::MachineOperand::getReg(), I, llvm::MachineOperand::isDead(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isKill(), llvm::MachineBasicBlock::isLiveIn(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isRegMask(), llvm::MachineOperand::isUse(), llvm::SI, llvm::MachineBasicBlock::succ_begin(), and llvm::MachineBasicBlock::succ_end().

Referenced by reMaterialize().

bool X86InstrInfo::isSafeToMoveRegClassDefs ( const TargetRegisterClass RC) const
override

isSafeToMoveRegClassDefs - Return true if it's safe to move a machine instruction that defines the specified register class.

Definition at line 6092 of file X86InstrInfo.cpp.

unsigned X86InstrInfo::isStoreToStackSlot ( const MachineInstr MI,
int FrameIndex 
) const
override
unsigned X86InstrInfo::isStoreToStackSlotPostFE ( const MachineInstr MI,
int FrameIndex 
) const
override

isStoreToStackSlotPostFE - Check for post-frame ptr elimination stack locations as well.

This uses a heuristic so it isn't reliable for correctness.

Definition at line 2221 of file X86InstrInfo.cpp.

References llvm::NVPTXISD::Dummy, llvm::MachineInstr::getOpcode(), isFrameStoreOpcode(), and isStoreToStackSlot().

bool X86InstrInfo::isUnpredicatedTerminator ( const MachineInstr MI) const
override
static bool llvm::X86InstrInfo::isX86_64ExtendedReg ( const MachineOperand MO)
inlinestatic
void X86InstrInfo::loadRegFromAddr ( MachineFunction MF,
unsigned  DestReg,
SmallVectorImpl< MachineOperand > &  Addr,
const TargetRegisterClass RC,
MachineInstr::mmo_iterator  MMOBegin,
MachineInstr::mmo_iterator  MMOEnd,
SmallVectorImpl< MachineInstr * > &  NewMIs 
) const
void X86InstrInfo::loadRegFromStackSlot ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
unsigned  DestReg,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI 
) const
override
bool X86InstrInfo::optimizeCompareInstr ( MachineInstr CmpInstr,
unsigned  SrcReg,
unsigned  SrcReg2,
int  CmpMask,
int  CmpValue,
const MachineRegisterInfo MRI 
) const
override

optimizeCompareInstr - Check if there exists an earlier instruction that operates on the same source operands and sets flags in the same way as Compare; remove Compare if possible.

Check if there exists an earlier instruction that operates on the same source operands and sets flags in the same way as Compare; remove Compare if possible.

Definition at line 4366 of file X86InstrInfo.cpp.

References llvm::X86::COND_A, llvm::X86::COND_AE, llvm::X86::COND_B, llvm::X86::COND_BE, llvm::X86::COND_E, llvm::X86::COND_G, llvm::X86::COND_GE, llvm::X86::COND_INVALID, llvm::X86::COND_L, llvm::X86::COND_LE, llvm::X86::COND_NE, llvm::X86::COND_NO, llvm::X86::COND_O, llvm::tgtok::Def, llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), llvm::X86::getCMovFromCond(), GetCondBranchFromCond(), getCondFromBranchOpc(), llvm::X86::getCondFromCMovOpc(), getCondFromSETOpc(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), GetOppositeBranchCondition(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), getRegisterInfo(), llvm::X86::getSETFromCond(), llvm::TargetRegisterClass::getSize(), getSwappedCondition(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::MachineInstr::hasOneMemOperand(), I, llvm::MachineBasicBlock::insert(), llvm::MachineInstr::isBranch(), llvm::MachineOperand::isDef(), isDefConvertible(), isRedundantFlagInstr(), llvm::MachineOperand::isReg(), isUseDefConvertible(), llvm::MachineInstr::killsRegister(), llvm_unreachable, llvm::AArch64CC::MI, llvm::MachineInstr::modifiesRegister(), llvm::MachineInstr::readsRegister(), llvm::MachineInstr::registerDefIsDead(), llvm::MachineBasicBlock::remove(), llvm::MachineInstr::RemoveOperand(), llvm::MachineBasicBlock::rend(), llvm::MachineInstr::setDesc(), llvm::MachineOperand::setIsDead(), llvm::SI, llvm::MachineBasicBlock::succ_begin(), llvm::MachineBasicBlock::succ_end(), and llvm::MachineRegisterInfo::use_nodbg_empty().

MachineInstr * X86InstrInfo::optimizeLoadInstr ( MachineInstr MI,
const MachineRegisterInfo MRI,
unsigned FoldAsLoadDefReg,
MachineInstr *&  DefMI 
) const
override

optimizeLoadInstr - Try to remove the load by folding it to a register operand at the use.

Try to remove the load by folding it to a register operand at the use.

We fold the load instructions if and only if the def and use are in the same BB. We only look at one load and see whether it can be folded into MI. FoldAsLoadDefReg is the virtual register defined by the load we are trying to fold. DefMI returns the machine instruction that defines FoldAsLoadDefReg, and the function returns the machine instruction generated due to folding.

We fold the load instructions if load defines a virtual register, the virtual register is used once in the same BB, and the instructions in-between do not load or store, and have no side effects.

Definition at line 4657 of file X86InstrInfo.cpp.

References llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineRegisterInfo::getVRegDef(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isReg(), llvm::MachineInstr::isSafeToMove(), llvm::MachineInstr::mayLoad(), and SawStore.

void X86InstrInfo::reMaterialize ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
unsigned  DestReg,
unsigned  SubIdx,
const MachineInstr Orig,
const TargetRegisterInfo TRI 
) const
override
unsigned X86InstrInfo::RemoveBranch ( MachineBasicBlock MBB) const
override
bool X86InstrInfo::ReverseBranchCondition ( SmallVectorImpl< MachineOperand > &  Cond) const
override
void X86InstrInfo::setExecutionDomain ( MachineInstr MI,
unsigned  Domain 
) const
override
bool X86InstrInfo::shouldScheduleAdjacent ( MachineInstr First,
MachineInstr Second 
) const
override
bool X86InstrInfo::shouldScheduleLoadsNear ( SDNode Load1,
SDNode Load2,
int64_t  Offset1,
int64_t  Offset2,
unsigned  NumLoads 
) const
override

shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePtr) if two loads should be scheduled togther.

On some targets if two loads are loading from addresses in the same cache line, it's better if they are scheduled together. This function takes two integers that represent the load offsets from the common base address. It returns true if it decides it's desirable to schedule the two loads together. "NumLoads" is the number of loads that have already been scheduled after Load1.

Definition at line 5874 of file X86InstrInfo.cpp.

References llvm::MVT::f32, llvm::MVT::f64, llvm::SDNode::getMachineOpcode(), llvm::EVT::getSimpleVT(), llvm::SDNode::getValueType(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::X86Subtarget::is64Bit(), and llvm::MVT::SimpleTy.

void X86InstrInfo::storeRegToAddr ( MachineFunction MF,
unsigned  SrcReg,
bool  isKill,
SmallVectorImpl< MachineOperand > &  Addr,
const TargetRegisterClass RC,
MachineInstr::mmo_iterator  MMOBegin,
MachineInstr::mmo_iterator  MMOEnd,
SmallVectorImpl< MachineInstr * > &  NewMIs 
) const
void X86InstrInfo::storeRegToStackSlot ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
unsigned  SrcReg,
bool  isKill,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI 
) const
override
bool X86InstrInfo::unfoldMemoryOperand ( MachineFunction MF,
MachineInstr MI,
unsigned  Reg,
bool  UnfoldLoad,
bool  UnfoldStore,
SmallVectorImpl< MachineInstr * > &  NewMIs 
) const
override

unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a store into two or more instruction.

If this is possible, returns true as well as the new instructions by reference.

Definition at line 5519 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::addOperand(), llvm::MachineInstrBuilder::addReg(), llvm::X86::AddrNumOperands, llvm::MachineOperand::ChangeToRegister(), llvm::MachineFunction::CreateMachineInstr(), llvm::RegState::Define, llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::end(), llvm::MachineFunction::extractLoadMemRefs(), llvm::MachineFunction::extractStoreMemRefs(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::find(), llvm::getDeadRegState(), llvm::MachineInstr::getDebugLoc(), llvm::getDefRegState(), llvm::MachineOperand::getImm(), llvm::getKillRegState(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), getRegClass(), llvm::getUndefRegState(), llvm::MachineInstr::hasOneMemOperand(), llvm::RegState::Implicit, llvm::MachineOperand::isDead(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isImplicit(), llvm::MachineOperand::isKill(), llvm::MachineOperand::isReg(), llvm::X86Subtarget::isUnalignedMemAccessFast(), llvm::MachineOperand::isUndef(), llvm_unreachable, loadRegFromAddr(), llvm::MachineInstr::memoperands_begin(), llvm::MachineInstr::memoperands_end(), llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::MachineInstr::setDesc(), llvm::MachineOperand::setIsKill(), llvm::SmallVectorTemplateCommon< T >::size(), storeRegToAddr(), TB_FOLDED_LOAD, TB_FOLDED_STORE, and TB_INDEX_MASK.

bool X86InstrInfo::unfoldMemoryOperand ( SelectionDAG DAG,
SDNode N,
SmallVectorImpl< SDNode * > &  NewNodes 
) const
override
bool llvm::X86InstrInfo::useMachineCombiner ( ) const
inlineoverride

Definition at line 457 of file X86InstrInfo.h.


The documentation for this class was generated from the following files: