34 #define DEBUG_TYPE "arm-pseudo"
38 cl::desc(
"Verify machine code after expanding ARM pseudos"));
53 const char *getPassName()
const override {
54 return "ARM pseudo instruction expansion pass";
67 unsigned Opc,
bool IsExt);
76 void ARMExpandPseudo::TransferImpOps(
MachineInstr &OldMI,
104 struct NEONLdStTableEntry {
109 bool hasWritebackOperand;
118 bool copyAllListRegs;
121 bool operator<(
const NEONLdStTableEntry &TE)
const {
122 return PseudoOpc < TE.PseudoOpc;
124 friend bool operator<(
const NEONLdStTableEntry &TE,
unsigned PseudoOpc) {
125 return TE.PseudoOpc < PseudoOpc;
128 const NEONLdStTableEntry &TE) {
129 return PseudoOpc < TE.PseudoOpc;
135 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16,
true,
false,
false, EvenDblSpc, 1, 4 ,
true},
136 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD,
true,
true,
true, EvenDblSpc, 1, 4 ,
true},
137 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32,
true,
false,
false, EvenDblSpc, 1, 2 ,
true},
138 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD,
true,
true,
true, EvenDblSpc, 1, 2 ,
true},
139 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8,
true,
false,
false, EvenDblSpc, 1, 8 ,
true},
140 { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD,
true,
true,
true, EvenDblSpc, 1, 8 ,
true},
142 { ARM::VLD1d64QPseudo, ARM::VLD1d64Q,
true,
false,
false, SingleSpc, 4, 1 ,
false},
143 { ARM::VLD1d64QPseudoWB_fixed, ARM::VLD1d64Qwb_fixed,
true,
true,
false, SingleSpc, 4, 1 ,
false},
144 { ARM::VLD1d64TPseudo, ARM::VLD1d64T,
true,
false,
false, SingleSpc, 3, 1 ,
false},
145 { ARM::VLD1d64TPseudoWB_fixed, ARM::VLD1d64Twb_fixed,
true,
true,
false, SingleSpc, 3, 1 ,
false},
147 { ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16,
true,
false,
false, SingleSpc, 2, 4 ,
true},
148 { ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD,
true,
true,
true, SingleSpc, 2, 4 ,
true},
149 { ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32,
true,
false,
false, SingleSpc, 2, 2 ,
true},
150 { ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD,
true,
true,
true, SingleSpc, 2, 2 ,
true},
151 { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8,
true,
false,
false, SingleSpc, 2, 8 ,
true},
152 { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD,
true,
true,
true, SingleSpc, 2, 8 ,
true},
153 { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16,
true,
false,
false, EvenDblSpc, 2, 4 ,
true},
154 { ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD,
true,
true,
true, EvenDblSpc, 2, 4 ,
true},
155 { ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32,
true,
false,
false, EvenDblSpc, 2, 2 ,
true},
156 { ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD,
true,
true,
true, EvenDblSpc, 2, 2 ,
true},
158 { ARM::VLD2q16Pseudo, ARM::VLD2q16,
true,
false,
false, SingleSpc, 4, 4 ,
false},
159 { ARM::VLD2q16PseudoWB_fixed, ARM::VLD2q16wb_fixed,
true,
true,
false, SingleSpc, 4, 4 ,
false},
160 { ARM::VLD2q16PseudoWB_register, ARM::VLD2q16wb_register,
true,
true,
true, SingleSpc, 4, 4 ,
false},
161 { ARM::VLD2q32Pseudo, ARM::VLD2q32,
true,
false,
false, SingleSpc, 4, 2 ,
false},
162 { ARM::VLD2q32PseudoWB_fixed, ARM::VLD2q32wb_fixed,
true,
true,
false, SingleSpc, 4, 2 ,
false},
163 { ARM::VLD2q32PseudoWB_register, ARM::VLD2q32wb_register,
true,
true,
true, SingleSpc, 4, 2 ,
false},
164 { ARM::VLD2q8Pseudo, ARM::VLD2q8,
true,
false,
false, SingleSpc, 4, 8 ,
false},
165 { ARM::VLD2q8PseudoWB_fixed, ARM::VLD2q8wb_fixed,
true,
true,
false, SingleSpc, 4, 8 ,
false},
166 { ARM::VLD2q8PseudoWB_register, ARM::VLD2q8wb_register,
true,
true,
true, SingleSpc, 4, 8 ,
false},
168 { ARM::VLD3DUPd16Pseudo, ARM::VLD3DUPd16,
true,
false,
false, SingleSpc, 3, 4,
true},
169 { ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD,
true,
true,
true, SingleSpc, 3, 4,
true},
170 { ARM::VLD3DUPd32Pseudo, ARM::VLD3DUPd32,
true,
false,
false, SingleSpc, 3, 2,
true},
171 { ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD,
true,
true,
true, SingleSpc, 3, 2,
true},
172 { ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd8,
true,
false,
false, SingleSpc, 3, 8,
true},
173 { ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd8_UPD,
true,
true,
true, SingleSpc, 3, 8,
true},
175 { ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16,
true,
false,
false, SingleSpc, 3, 4 ,
true},
176 { ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD,
true,
true,
true, SingleSpc, 3, 4 ,
true},
177 { ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32,
true,
false,
false, SingleSpc, 3, 2 ,
true},
178 { ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD,
true,
true,
true, SingleSpc, 3, 2 ,
true},
179 { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8,
true,
false,
false, SingleSpc, 3, 8 ,
true},
180 { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD,
true,
true,
true, SingleSpc, 3, 8 ,
true},
181 { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16,
true,
false,
false, EvenDblSpc, 3, 4 ,
true},
182 { ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD,
true,
true,
true, EvenDblSpc, 3, 4 ,
true},
183 { ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32,
true,
false,
false, EvenDblSpc, 3, 2 ,
true},
184 { ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD,
true,
true,
true, EvenDblSpc, 3, 2 ,
true},
186 { ARM::VLD3d16Pseudo, ARM::VLD3d16,
true,
false,
false, SingleSpc, 3, 4 ,
true},
187 { ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD,
true,
true,
true, SingleSpc, 3, 4 ,
true},
188 { ARM::VLD3d32Pseudo, ARM::VLD3d32,
true,
false,
false, SingleSpc, 3, 2 ,
true},
189 { ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD,
true,
true,
true, SingleSpc, 3, 2 ,
true},
190 { ARM::VLD3d8Pseudo, ARM::VLD3d8,
true,
false,
false, SingleSpc, 3, 8 ,
true},
191 { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD,
true,
true,
true, SingleSpc, 3, 8 ,
true},
193 { ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD,
true,
true,
true, EvenDblSpc, 3, 4 ,
true},
194 { ARM::VLD3q16oddPseudo, ARM::VLD3q16,
true,
false,
false, OddDblSpc, 3, 4 ,
true},
195 { ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD,
true,
true,
true, OddDblSpc, 3, 4 ,
true},
196 { ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD,
true,
true,
true, EvenDblSpc, 3, 2 ,
true},
197 { ARM::VLD3q32oddPseudo, ARM::VLD3q32,
true,
false,
false, OddDblSpc, 3, 2 ,
true},
198 { ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD,
true,
true,
true, OddDblSpc, 3, 2 ,
true},
199 { ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD,
true,
true,
true, EvenDblSpc, 3, 8 ,
true},
200 { ARM::VLD3q8oddPseudo, ARM::VLD3q8,
true,
false,
false, OddDblSpc, 3, 8 ,
true},
201 { ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD,
true,
true,
true, OddDblSpc, 3, 8 ,
true},
203 { ARM::VLD4DUPd16Pseudo, ARM::VLD4DUPd16,
true,
false,
false, SingleSpc, 4, 4,
true},
204 { ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD,
true,
true,
true, SingleSpc, 4, 4,
true},
205 { ARM::VLD4DUPd32Pseudo, ARM::VLD4DUPd32,
true,
false,
false, SingleSpc, 4, 2,
true},
206 { ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD,
true,
true,
true, SingleSpc, 4, 2,
true},
207 { ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd8,
true,
false,
false, SingleSpc, 4, 8,
true},
208 { ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd8_UPD,
true,
true,
true, SingleSpc, 4, 8,
true},
210 { ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16,
true,
false,
false, SingleSpc, 4, 4 ,
true},
211 { ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD,
true,
true,
true, SingleSpc, 4, 4 ,
true},
212 { ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32,
true,
false,
false, SingleSpc, 4, 2 ,
true},
213 { ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD,
true,
true,
true, SingleSpc, 4, 2 ,
true},
214 { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8,
true,
false,
false, SingleSpc, 4, 8 ,
true},
215 { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD,
true,
true,
true, SingleSpc, 4, 8 ,
true},
216 { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16,
true,
false,
false, EvenDblSpc, 4, 4 ,
true},
217 { ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD,
true,
true,
true, EvenDblSpc, 4, 4 ,
true},
218 { ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32,
true,
false,
false, EvenDblSpc, 4, 2 ,
true},
219 { ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD,
true,
true,
true, EvenDblSpc, 4, 2 ,
true},
221 { ARM::VLD4d16Pseudo, ARM::VLD4d16,
true,
false,
false, SingleSpc, 4, 4 ,
true},
222 { ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD,
true,
true,
true, SingleSpc, 4, 4 ,
true},
223 { ARM::VLD4d32Pseudo, ARM::VLD4d32,
true,
false,
false, SingleSpc, 4, 2 ,
true},
224 { ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD,
true,
true,
true, SingleSpc, 4, 2 ,
true},
225 { ARM::VLD4d8Pseudo, ARM::VLD4d8,
true,
false,
false, SingleSpc, 4, 8 ,
true},
226 { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD,
true,
true,
true, SingleSpc, 4, 8 ,
true},
228 { ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD,
true,
true,
true, EvenDblSpc, 4, 4 ,
true},
229 { ARM::VLD4q16oddPseudo, ARM::VLD4q16,
true,
false,
false, OddDblSpc, 4, 4 ,
true},
230 { ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD,
true,
true,
true, OddDblSpc, 4, 4 ,
true},
231 { ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD,
true,
true,
true, EvenDblSpc, 4, 2 ,
true},
232 { ARM::VLD4q32oddPseudo, ARM::VLD4q32,
true,
false,
false, OddDblSpc, 4, 2 ,
true},
233 { ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD,
true,
true,
true, OddDblSpc, 4, 2 ,
true},
234 { ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD,
true,
true,
true, EvenDblSpc, 4, 8 ,
true},
235 { ARM::VLD4q8oddPseudo, ARM::VLD4q8,
true,
false,
false, OddDblSpc, 4, 8 ,
true},
236 { ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD,
true,
true,
true, OddDblSpc, 4, 8 ,
true},
238 { ARM::VST1LNq16Pseudo, ARM::VST1LNd16,
false,
false,
false, EvenDblSpc, 1, 4 ,
true},
239 { ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD,
false,
true,
true, EvenDblSpc, 1, 4 ,
true},
240 { ARM::VST1LNq32Pseudo, ARM::VST1LNd32,
false,
false,
false, EvenDblSpc, 1, 2 ,
true},
241 { ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD,
false,
true,
true, EvenDblSpc, 1, 2 ,
true},
242 { ARM::VST1LNq8Pseudo, ARM::VST1LNd8,
false,
false,
false, EvenDblSpc, 1, 8 ,
true},
243 { ARM::VST1LNq8Pseudo_UPD, ARM::VST1LNd8_UPD,
false,
true,
true, EvenDblSpc, 1, 8 ,
true},
245 { ARM::VST1d64QPseudo, ARM::VST1d64Q,
false,
false,
false, SingleSpc, 4, 1 ,
false},
246 { ARM::VST1d64QPseudoWB_fixed, ARM::VST1d64Qwb_fixed,
false,
true,
false, SingleSpc, 4, 1 ,
false},
247 { ARM::VST1d64QPseudoWB_register, ARM::VST1d64Qwb_register,
false,
true,
true, SingleSpc, 4, 1 ,
false},
248 { ARM::VST1d64TPseudo, ARM::VST1d64T,
false,
false,
false, SingleSpc, 3, 1 ,
false},
249 { ARM::VST1d64TPseudoWB_fixed, ARM::VST1d64Twb_fixed,
false,
true,
false, SingleSpc, 3, 1 ,
false},
250 { ARM::VST1d64TPseudoWB_register, ARM::VST1d64Twb_register,
false,
true,
true, SingleSpc, 3, 1 ,
false},
252 { ARM::VST2LNd16Pseudo, ARM::VST2LNd16,
false,
false,
false, SingleSpc, 2, 4 ,
true},
253 { ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD,
false,
true,
true, SingleSpc, 2, 4 ,
true},
254 { ARM::VST2LNd32Pseudo, ARM::VST2LNd32,
false,
false,
false, SingleSpc, 2, 2 ,
true},
255 { ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD,
false,
true,
true, SingleSpc, 2, 2 ,
true},
256 { ARM::VST2LNd8Pseudo, ARM::VST2LNd8,
false,
false,
false, SingleSpc, 2, 8 ,
true},
257 { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD,
false,
true,
true, SingleSpc, 2, 8 ,
true},
258 { ARM::VST2LNq16Pseudo, ARM::VST2LNq16,
false,
false,
false, EvenDblSpc, 2, 4,
true},
259 { ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD,
false,
true,
true, EvenDblSpc, 2, 4,
true},
260 { ARM::VST2LNq32Pseudo, ARM::VST2LNq32,
false,
false,
false, EvenDblSpc, 2, 2,
true},
261 { ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD,
false,
true,
true, EvenDblSpc, 2, 2,
true},
263 { ARM::VST2q16Pseudo, ARM::VST2q16,
false,
false,
false, SingleSpc, 4, 4 ,
false},
264 { ARM::VST2q16PseudoWB_fixed, ARM::VST2q16wb_fixed,
false,
true,
false, SingleSpc, 4, 4 ,
false},
265 { ARM::VST2q16PseudoWB_register, ARM::VST2q16wb_register,
false,
true,
true, SingleSpc, 4, 4 ,
false},
266 { ARM::VST2q32Pseudo, ARM::VST2q32,
false,
false,
false, SingleSpc, 4, 2 ,
false},
267 { ARM::VST2q32PseudoWB_fixed, ARM::VST2q32wb_fixed,
false,
true,
false, SingleSpc, 4, 2 ,
false},
268 { ARM::VST2q32PseudoWB_register, ARM::VST2q32wb_register,
false,
true,
true, SingleSpc, 4, 2 ,
false},
269 { ARM::VST2q8Pseudo, ARM::VST2q8,
false,
false,
false, SingleSpc, 4, 8 ,
false},
270 { ARM::VST2q8PseudoWB_fixed, ARM::VST2q8wb_fixed,
false,
true,
false, SingleSpc, 4, 8 ,
false},
271 { ARM::VST2q8PseudoWB_register, ARM::VST2q8wb_register,
false,
true,
true, SingleSpc, 4, 8 ,
false},
273 { ARM::VST3LNd16Pseudo, ARM::VST3LNd16,
false,
false,
false, SingleSpc, 3, 4 ,
true},
274 { ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD,
false,
true,
true, SingleSpc, 3, 4 ,
true},
275 { ARM::VST3LNd32Pseudo, ARM::VST3LNd32,
false,
false,
false, SingleSpc, 3, 2 ,
true},
276 { ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD,
false,
true,
true, SingleSpc, 3, 2 ,
true},
277 { ARM::VST3LNd8Pseudo, ARM::VST3LNd8,
false,
false,
false, SingleSpc, 3, 8 ,
true},
278 { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD,
false,
true,
true, SingleSpc, 3, 8 ,
true},
279 { ARM::VST3LNq16Pseudo, ARM::VST3LNq16,
false,
false,
false, EvenDblSpc, 3, 4,
true},
280 { ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD,
false,
true,
true, EvenDblSpc, 3, 4,
true},
281 { ARM::VST3LNq32Pseudo, ARM::VST3LNq32,
false,
false,
false, EvenDblSpc, 3, 2,
true},
282 { ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD,
false,
true,
true, EvenDblSpc, 3, 2,
true},
284 { ARM::VST3d16Pseudo, ARM::VST3d16,
false,
false,
false, SingleSpc, 3, 4 ,
true},
285 { ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD,
false,
true,
true, SingleSpc, 3, 4 ,
true},
286 { ARM::VST3d32Pseudo, ARM::VST3d32,
false,
false,
false, SingleSpc, 3, 2 ,
true},
287 { ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD,
false,
true,
true, SingleSpc, 3, 2 ,
true},
288 { ARM::VST3d8Pseudo, ARM::VST3d8,
false,
false,
false, SingleSpc, 3, 8 ,
true},
289 { ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD,
false,
true,
true, SingleSpc, 3, 8 ,
true},
291 { ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD,
false,
true,
true, EvenDblSpc, 3, 4 ,
true},
292 { ARM::VST3q16oddPseudo, ARM::VST3q16,
false,
false,
false, OddDblSpc, 3, 4 ,
true},
293 { ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD,
false,
true,
true, OddDblSpc, 3, 4 ,
true},
294 { ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD,
false,
true,
true, EvenDblSpc, 3, 2 ,
true},
295 { ARM::VST3q32oddPseudo, ARM::VST3q32,
false,
false,
false, OddDblSpc, 3, 2 ,
true},
296 { ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD,
false,
true,
true, OddDblSpc, 3, 2 ,
true},
297 { ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD,
false,
true,
true, EvenDblSpc, 3, 8 ,
true},
298 { ARM::VST3q8oddPseudo, ARM::VST3q8,
false,
false,
false, OddDblSpc, 3, 8 ,
true},
299 { ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD,
false,
true,
true, OddDblSpc, 3, 8 ,
true},
301 { ARM::VST4LNd16Pseudo, ARM::VST4LNd16,
false,
false,
false, SingleSpc, 4, 4 ,
true},
302 { ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD,
false,
true,
true, SingleSpc, 4, 4 ,
true},
303 { ARM::VST4LNd32Pseudo, ARM::VST4LNd32,
false,
false,
false, SingleSpc, 4, 2 ,
true},
304 { ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD,
false,
true,
true, SingleSpc, 4, 2 ,
true},
305 { ARM::VST4LNd8Pseudo, ARM::VST4LNd8,
false,
false,
false, SingleSpc, 4, 8 ,
true},
306 { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD,
false,
true,
true, SingleSpc, 4, 8 ,
true},
307 { ARM::VST4LNq16Pseudo, ARM::VST4LNq16,
false,
false,
false, EvenDblSpc, 4, 4,
true},
308 { ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD,
false,
true,
true, EvenDblSpc, 4, 4,
true},
309 { ARM::VST4LNq32Pseudo, ARM::VST4LNq32,
false,
false,
false, EvenDblSpc, 4, 2,
true},
310 { ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD,
false,
true,
true, EvenDblSpc, 4, 2,
true},
312 { ARM::VST4d16Pseudo, ARM::VST4d16,
false,
false,
false, SingleSpc, 4, 4 ,
true},
313 { ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD,
false,
true,
true, SingleSpc, 4, 4 ,
true},
314 { ARM::VST4d32Pseudo, ARM::VST4d32,
false,
false,
false, SingleSpc, 4, 2 ,
true},
315 { ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD,
false,
true,
true, SingleSpc, 4, 2 ,
true},
316 { ARM::VST4d8Pseudo, ARM::VST4d8,
false,
false,
false, SingleSpc, 4, 8 ,
true},
317 { ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD,
false,
true,
true, SingleSpc, 4, 8 ,
true},
319 { ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD,
false,
true,
true, EvenDblSpc, 4, 4 ,
true},
320 { ARM::VST4q16oddPseudo, ARM::VST4q16,
false,
false,
false, OddDblSpc, 4, 4 ,
true},
321 { ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD,
false,
true,
true, OddDblSpc, 4, 4 ,
true},
322 { ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD,
false,
true,
true, EvenDblSpc, 4, 2 ,
true},
323 { ARM::VST4q32oddPseudo, ARM::VST4q32,
false,
false,
false, OddDblSpc, 4, 2 ,
true},
324 { ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD,
false,
true,
true, OddDblSpc, 4, 2 ,
true},
325 { ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD,
false,
true,
true, EvenDblSpc, 4, 8 ,
true},
326 { ARM::VST4q8oddPseudo, ARM::VST4q8,
false,
false,
false, OddDblSpc, 4, 8 ,
true},
327 { ARM::VST4q8oddPseudo_UPD, ARM::VST4q8_UPD,
false,
true,
true, OddDblSpc, 4, 8 ,
true}
337 static bool TableChecked =
false;
339 for (
unsigned i = 0; i != NumEntries-1; ++i)
341 "NEONLdStTable is not sorted!");
346 const NEONLdStTableEntry *
I =
348 if (I !=
NEONLdStTable + NumEntries && I->PseudoOpc == Opcode)
358 unsigned &D1,
unsigned &D2,
unsigned &D3) {
359 if (RegSpc == SingleSpc) {
364 }
else if (RegSpc == EvenDblSpc) {
370 assert(RegSpc == OddDblSpc &&
"unknown register spacing");
385 assert(TableEntry && TableEntry->IsLoad &&
"NEONLdStTable lookup failed");
387 unsigned NumRegs = TableEntry->NumRegs;
390 TII->get(TableEntry->RealOpc));
395 unsigned D0, D1, D2, D3;
398 if (NumRegs > 1 && TableEntry->copyAllListRegs)
400 if (NumRegs > 2 && TableEntry->copyAllListRegs)
402 if (NumRegs > 3 && TableEntry->copyAllListRegs)
405 if (TableEntry->isUpdating)
412 if (TableEntry->hasWritebackOperand)
418 unsigned SrcOpIdx = 0;
419 if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc)
435 TransferImpOps(MI, MIB, MIB);
450 assert(TableEntry && !TableEntry->IsLoad &&
"NEONLdStTable lookup failed");
452 unsigned NumRegs = TableEntry->NumRegs;
455 TII->get(TableEntry->RealOpc));
457 if (TableEntry->isUpdating)
464 if (TableEntry->hasWritebackOperand)
470 unsigned D0, D1, D2, D3;
473 if (NumRegs > 1 && TableEntry->copyAllListRegs)
475 if (NumRegs > 2 && TableEntry->copyAllListRegs)
477 if (NumRegs > 3 && TableEntry->copyAllListRegs)
484 if (SrcIsKill && !SrcIsUndef)
485 MIB->addRegisterKilled(SrcReg, TRI,
true);
486 else if (!SrcIsUndef)
488 TransferImpOps(MI, MIB, MIB);
503 assert(TableEntry &&
"NEONLdStTable lookup failed");
505 unsigned NumRegs = TableEntry->NumRegs;
506 unsigned RegElts = TableEntry->RegElts;
509 TII->get(TableEntry->RealOpc));
516 assert(RegSpc != OddDblSpc &&
"unexpected register spacing for VLD/VST-lane");
517 if (RegSpc == EvenDblSpc && Lane >= RegElts) {
521 assert(Lane < RegElts &&
"out of range lane for VLD/VST-lane");
523 unsigned D0 = 0, D1 = 0, D2 = 0, D3 = 0;
525 bool DstIsDead =
false;
526 if (TableEntry->IsLoad) {
539 if (TableEntry->isUpdating)
546 if (TableEntry->hasWritebackOperand)
551 if (!TableEntry->IsLoad)
557 MIB.addReg(D0, SrcFlags);
559 MIB.addReg(D1, SrcFlags);
561 MIB.addReg(D2, SrcFlags);
563 MIB.addReg(D3, SrcFlags);
576 if (TableEntry->IsLoad)
579 TransferImpOps(MI, MIB, MIB);
588 unsigned Opc,
bool IsExt) {
602 unsigned D0, D1, D2, D3;
603 GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3);
615 TransferImpOps(MI, MIB, MIB);
656 unsigned PredReg = 0;
660 bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm;
665 if (!STI->hasV6T2Ops() &&
666 (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) {
668 assert(!STI->isTargetWindows() &&
"Windows on ARM requires ARMv7+");
676 assert (MO.
isImm() &&
"MOVi32imm w/ non-immediate source operand!");
680 LO16 = LO16.addImm(SOImmValV1);
681 HI16 = HI16.addImm(SOImmValV2);
684 LO16.addImm(Pred).addReg(PredReg).addReg(0);
685 HI16.addImm(Pred).addReg(PredReg).addReg(0);
686 TransferImpOps(MI, LO16, HI16);
691 unsigned LO16Opc = 0;
692 unsigned HI16Opc = 0;
693 if (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm) {
694 LO16Opc = ARM::t2MOVi16;
695 HI16Opc = ARM::t2MOVTi16;
697 LO16Opc = ARM::MOVi16;
698 HI16Opc = ARM::MOVTi16;
708 unsigned Imm = MO.
getImm();
709 unsigned Lo16 = Imm & 0xffff;
710 unsigned Hi16 = (Imm >> 16) & 0xffff;
711 LO16 = LO16.addImm(Lo16);
712 HI16 = HI16.addImm(Hi16);
733 LO16.addImm(Pred).addReg(PredReg);
734 HI16.addImm(Pred).addReg(PredReg);
736 if (RequiresBundling)
739 TransferImpOps(MI, LO16, HI16);
752 unsigned newOpc = Opcode == ARM::VMOVScc ? ARM::VMOVS : ARM::VMOVD;
764 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr;
800 case ARM::t2MOVCCi16:
801 case ARM::MOVCCi16: {
802 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16;
813 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi;
826 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MVNi : ARM::MVNi;
837 case ARM::t2MOVCClsl:
838 case ARM::t2MOVCClsr:
839 case ARM::t2MOVCCasr:
840 case ARM::t2MOVCCror: {
843 case ARM::t2MOVCClsl: NewOpc = ARM::t2LSLri;
break;
844 case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri;
break;
845 case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri;
break;
846 case ARM::t2MOVCCror: NewOpc = ARM::t2RORri;
break;
859 case ARM::Int_eh_sjlj_dispatchsetup: {
868 int32_t NumBytes = AFI->getFramePtrSpillOffset();
871 "base pointer without frame pointer?");
873 if (AFI->isThumb2Function()) {
876 }
else if (AFI->isThumbFunction()) {
888 assert (!AFI->isThumb1OnlyFunction());
890 assert(MaxAlign <= 256 &&
"The BIC instruction cannot encode "
891 "immediates larger than 256 with all lower "
893 unsigned bicOpc = AFI->isThumbFunction() ?
894 ARM::t2BICri : ARM::BICri;
906 case ARM::MOVsrl_flag:
907 case ARM::MOVsra_flag: {
927 TransferImpOps(MI, MIB, MIB);
934 if (Opcode == ARM::tTPsoft)
937 .addImm((
unsigned)ARMCC::AL).addReg(0)
938 .addExternalSymbol("__aeabi_read_tp", 0);
940 MIB =
BuildMI(MBB, MBBI, MI.getDebugLoc(),
942 .addExternalSymbol("__aeabi_read_tp", 0);
944 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
945 TransferImpOps(MI, MIB, MIB);
946 MI.eraseFromParent();
949 case ARM::tLDRpci_pic:
950 case ARM::t2LDRpci_pic: {
951 unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic)
952 ? ARM::tLDRpci : ARM::t2LDRpci;
953 unsigned DstReg = MI.getOperand(0).getReg();
954 bool DstIsDead = MI.getOperand(0).isDead();
957 TII->get(NewLdOpc), DstReg)
958 .addOperand(MI.getOperand(1)));
959 MIB1->
setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
961 TII->get(ARM::tPICADD))
965 TransferImpOps(MI, MIB1, MIB2);
966 MI.eraseFromParent();
970 case ARM::LDRLIT_ga_abs:
971 case ARM::LDRLIT_ga_pcrel:
972 case ARM::LDRLIT_ga_pcrel_ldr:
973 case ARM::tLDRLIT_ga_abs:
974 case ARM::tLDRLIT_ga_pcrel: {
975 unsigned DstReg = MI.getOperand(0).getReg();
976 bool DstIsDead = MI.getOperand(0).isDead();
980 Opcode != ARM::tLDRLIT_ga_pcrel && Opcode != ARM::tLDRLIT_ga_abs;
982 Opcode != ARM::LDRLIT_ga_abs && Opcode != ARM::tLDRLIT_ga_abs;
983 unsigned LDRLITOpc = IsARM ? ARM::LDRi12 : ARM::tLDRpci;
986 ? (Opcode == ARM::LDRLIT_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
991 unsigned ARMPCLabelIndex = 0;
995 unsigned PCAdj = IsARM ? 8 : 4;
996 ARMPCLabelIndex = AFI->createPICLabelUId();
1003 BuildMI(MBB, MBBI, MI.getDebugLoc(),
TII->get(LDRLITOpc), DstReg)
1004 .addConstantPoolIndex(MCP->getConstantPoolIndex(CPV, 4));
1011 BuildMI(MBB, MBBI, MI.getDebugLoc(),
TII->get(PICAddOpc))
1014 .
addImm(ARMPCLabelIndex);
1020 MI.eraseFromParent();
1023 case ARM::MOV_ga_pcrel:
1024 case ARM::MOV_ga_pcrel_ldr:
1025 case ARM::t2MOV_ga_pcrel: {
1027 unsigned LabelId = AFI->createPICLabelUId();
1028 unsigned DstReg = MI.getOperand(0).getReg();
1029 bool DstIsDead = MI.getOperand(0).isDead();
1033 bool isARM = Opcode != ARM::t2MOV_ga_pcrel;
1034 unsigned LO16Opc = isARM ? ARM::MOVi16_ga_pcrel : ARM::t2MOVi16_ga_pcrel;
1035 unsigned HI16Opc = isARM ? ARM::MOVTi16_ga_pcrel :ARM::t2MOVTi16_ga_pcrel;
1038 unsigned PICAddOpc = isARM
1039 ? (Opcode == ARM::MOV_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
1042 TII->get(LO16Opc), DstReg)
1043 .addGlobalAddress(GV, MO1.
getOffset(), TF | LO16TF)
1046 BuildMI(MBB, MBBI, MI.getDebugLoc(),
TII->get(HI16Opc), DstReg)
1052 TII->get(PICAddOpc))
1054 .addReg(DstReg).
addImm(LabelId);
1057 if (Opcode == ARM::MOV_ga_pcrel_ldr)
1058 MIB3->
setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1060 TransferImpOps(MI, MIB1, MIB3);
1061 MI.eraseFromParent();
1065 case ARM::MOVi32imm:
1066 case ARM::MOVCCi32imm:
1067 case ARM::t2MOVi32imm:
1068 case ARM::t2MOVCCi32imm:
1069 ExpandMOV32BitImm(MBB, MBBI);
1072 case ARM::SUBS_PC_LR: {
1074 BuildMI(MBB, MBBI, MI.getDebugLoc(),
TII->get(ARM::SUBri), ARM::PC)
1077 .addOperand(MI.getOperand(1))
1078 .addOperand(MI.getOperand(2))
1080 TransferImpOps(MI, MIB, MIB);
1081 MI.eraseFromParent();
1084 case ARM::VLDMQIA: {
1085 unsigned NewOpc = ARM::VLDMDIA;
1087 BuildMI(MBB, MBBI, MI.getDebugLoc(),
TII->get(NewOpc));
1091 bool DstIsDead = MI.getOperand(OpIdx).isDead();
1092 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
1102 unsigned D0 = TRI->getSubReg(DstReg, ARM::dsub_0);
1103 unsigned D1 = TRI->getSubReg(DstReg, ARM::dsub_1);
1109 TransferImpOps(MI, MIB, MIB);
1110 MIB.
setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1111 MI.eraseFromParent();
1115 case ARM::VSTMQIA: {
1116 unsigned NewOpc = ARM::VSTMDIA;
1118 BuildMI(MBB, MBBI, MI.getDebugLoc(),
TII->get(NewOpc));
1122 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
1123 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
1133 unsigned D0 = TRI->getSubReg(SrcReg, ARM::dsub_0);
1134 unsigned D1 = TRI->getSubReg(SrcReg, ARM::dsub_1);
1136 .
addReg(D1, SrcIsKill ? RegState::Kill : 0);
1141 TransferImpOps(MI, MIB, MIB);
1142 MIB.
setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1143 MI.eraseFromParent();
1147 case ARM::VLD2q8Pseudo:
1148 case ARM::VLD2q16Pseudo:
1149 case ARM::VLD2q32Pseudo:
1150 case ARM::VLD2q8PseudoWB_fixed:
1151 case ARM::VLD2q16PseudoWB_fixed:
1152 case ARM::VLD2q32PseudoWB_fixed:
1153 case ARM::VLD2q8PseudoWB_register:
1154 case ARM::VLD2q16PseudoWB_register:
1155 case ARM::VLD2q32PseudoWB_register:
1156 case ARM::VLD3d8Pseudo:
1157 case ARM::VLD3d16Pseudo:
1158 case ARM::VLD3d32Pseudo:
1159 case ARM::VLD1d64TPseudo:
1160 case ARM::VLD1d64TPseudoWB_fixed:
1161 case ARM::VLD3d8Pseudo_UPD:
1162 case ARM::VLD3d16Pseudo_UPD:
1163 case ARM::VLD3d32Pseudo_UPD:
1164 case ARM::VLD3q8Pseudo_UPD:
1165 case ARM::VLD3q16Pseudo_UPD:
1166 case ARM::VLD3q32Pseudo_UPD:
1167 case ARM::VLD3q8oddPseudo:
1168 case ARM::VLD3q16oddPseudo:
1169 case ARM::VLD3q32oddPseudo:
1170 case ARM::VLD3q8oddPseudo_UPD:
1171 case ARM::VLD3q16oddPseudo_UPD:
1172 case ARM::VLD3q32oddPseudo_UPD:
1173 case ARM::VLD4d8Pseudo:
1174 case ARM::VLD4d16Pseudo:
1175 case ARM::VLD4d32Pseudo:
1176 case ARM::VLD1d64QPseudo:
1177 case ARM::VLD1d64QPseudoWB_fixed:
1178 case ARM::VLD4d8Pseudo_UPD:
1179 case ARM::VLD4d16Pseudo_UPD:
1180 case ARM::VLD4d32Pseudo_UPD:
1181 case ARM::VLD4q8Pseudo_UPD:
1182 case ARM::VLD4q16Pseudo_UPD:
1183 case ARM::VLD4q32Pseudo_UPD:
1184 case ARM::VLD4q8oddPseudo:
1185 case ARM::VLD4q16oddPseudo:
1186 case ARM::VLD4q32oddPseudo:
1187 case ARM::VLD4q8oddPseudo_UPD:
1188 case ARM::VLD4q16oddPseudo_UPD:
1189 case ARM::VLD4q32oddPseudo_UPD:
1190 case ARM::VLD3DUPd8Pseudo:
1191 case ARM::VLD3DUPd16Pseudo:
1192 case ARM::VLD3DUPd32Pseudo:
1193 case ARM::VLD3DUPd8Pseudo_UPD:
1194 case ARM::VLD3DUPd16Pseudo_UPD:
1195 case ARM::VLD3DUPd32Pseudo_UPD:
1196 case ARM::VLD4DUPd8Pseudo:
1197 case ARM::VLD4DUPd16Pseudo:
1198 case ARM::VLD4DUPd32Pseudo:
1199 case ARM::VLD4DUPd8Pseudo_UPD:
1200 case ARM::VLD4DUPd16Pseudo_UPD:
1201 case ARM::VLD4DUPd32Pseudo_UPD:
1205 case ARM::VST2q8Pseudo:
1206 case ARM::VST2q16Pseudo:
1207 case ARM::VST2q32Pseudo:
1208 case ARM::VST2q8PseudoWB_fixed:
1209 case ARM::VST2q16PseudoWB_fixed:
1210 case ARM::VST2q32PseudoWB_fixed:
1211 case ARM::VST2q8PseudoWB_register:
1212 case ARM::VST2q16PseudoWB_register:
1213 case ARM::VST2q32PseudoWB_register:
1214 case ARM::VST3d8Pseudo:
1215 case ARM::VST3d16Pseudo:
1216 case ARM::VST3d32Pseudo:
1217 case ARM::VST1d64TPseudo:
1218 case ARM::VST3d8Pseudo_UPD:
1219 case ARM::VST3d16Pseudo_UPD:
1220 case ARM::VST3d32Pseudo_UPD:
1221 case ARM::VST1d64TPseudoWB_fixed:
1222 case ARM::VST1d64TPseudoWB_register:
1223 case ARM::VST3q8Pseudo_UPD:
1224 case ARM::VST3q16Pseudo_UPD:
1225 case ARM::VST3q32Pseudo_UPD:
1226 case ARM::VST3q8oddPseudo:
1227 case ARM::VST3q16oddPseudo:
1228 case ARM::VST3q32oddPseudo:
1229 case ARM::VST3q8oddPseudo_UPD:
1230 case ARM::VST3q16oddPseudo_UPD:
1231 case ARM::VST3q32oddPseudo_UPD:
1232 case ARM::VST4d8Pseudo:
1233 case ARM::VST4d16Pseudo:
1234 case ARM::VST4d32Pseudo:
1235 case ARM::VST1d64QPseudo:
1236 case ARM::VST4d8Pseudo_UPD:
1237 case ARM::VST4d16Pseudo_UPD:
1238 case ARM::VST4d32Pseudo_UPD:
1239 case ARM::VST1d64QPseudoWB_fixed:
1240 case ARM::VST1d64QPseudoWB_register:
1241 case ARM::VST4q8Pseudo_UPD:
1242 case ARM::VST4q16Pseudo_UPD:
1243 case ARM::VST4q32Pseudo_UPD:
1244 case ARM::VST4q8oddPseudo:
1245 case ARM::VST4q16oddPseudo:
1246 case ARM::VST4q32oddPseudo:
1247 case ARM::VST4q8oddPseudo_UPD:
1248 case ARM::VST4q16oddPseudo_UPD:
1249 case ARM::VST4q32oddPseudo_UPD:
1253 case ARM::VLD1LNq8Pseudo:
1254 case ARM::VLD1LNq16Pseudo:
1255 case ARM::VLD1LNq32Pseudo:
1256 case ARM::VLD1LNq8Pseudo_UPD:
1257 case ARM::VLD1LNq16Pseudo_UPD:
1258 case ARM::VLD1LNq32Pseudo_UPD:
1259 case ARM::VLD2LNd8Pseudo:
1260 case ARM::VLD2LNd16Pseudo:
1261 case ARM::VLD2LNd32Pseudo:
1262 case ARM::VLD2LNq16Pseudo:
1263 case ARM::VLD2LNq32Pseudo:
1264 case ARM::VLD2LNd8Pseudo_UPD:
1265 case ARM::VLD2LNd16Pseudo_UPD:
1266 case ARM::VLD2LNd32Pseudo_UPD:
1267 case ARM::VLD2LNq16Pseudo_UPD:
1268 case ARM::VLD2LNq32Pseudo_UPD:
1269 case ARM::VLD3LNd8Pseudo:
1270 case ARM::VLD3LNd16Pseudo:
1271 case ARM::VLD3LNd32Pseudo:
1272 case ARM::VLD3LNq16Pseudo:
1273 case ARM::VLD3LNq32Pseudo:
1274 case ARM::VLD3LNd8Pseudo_UPD:
1275 case ARM::VLD3LNd16Pseudo_UPD:
1276 case ARM::VLD3LNd32Pseudo_UPD:
1277 case ARM::VLD3LNq16Pseudo_UPD:
1278 case ARM::VLD3LNq32Pseudo_UPD:
1279 case ARM::VLD4LNd8Pseudo:
1280 case ARM::VLD4LNd16Pseudo:
1281 case ARM::VLD4LNd32Pseudo:
1282 case ARM::VLD4LNq16Pseudo:
1283 case ARM::VLD4LNq32Pseudo:
1284 case ARM::VLD4LNd8Pseudo_UPD:
1285 case ARM::VLD4LNd16Pseudo_UPD:
1286 case ARM::VLD4LNd32Pseudo_UPD:
1287 case ARM::VLD4LNq16Pseudo_UPD:
1288 case ARM::VLD4LNq32Pseudo_UPD:
1289 case ARM::VST1LNq8Pseudo:
1290 case ARM::VST1LNq16Pseudo:
1291 case ARM::VST1LNq32Pseudo:
1292 case ARM::VST1LNq8Pseudo_UPD:
1293 case ARM::VST1LNq16Pseudo_UPD:
1294 case ARM::VST1LNq32Pseudo_UPD:
1295 case ARM::VST2LNd8Pseudo:
1296 case ARM::VST2LNd16Pseudo:
1297 case ARM::VST2LNd32Pseudo:
1298 case ARM::VST2LNq16Pseudo:
1299 case ARM::VST2LNq32Pseudo:
1300 case ARM::VST2LNd8Pseudo_UPD:
1301 case ARM::VST2LNd16Pseudo_UPD:
1302 case ARM::VST2LNd32Pseudo_UPD:
1303 case ARM::VST2LNq16Pseudo_UPD:
1304 case ARM::VST2LNq32Pseudo_UPD:
1305 case ARM::VST3LNd8Pseudo:
1306 case ARM::VST3LNd16Pseudo:
1307 case ARM::VST3LNd32Pseudo:
1308 case ARM::VST3LNq16Pseudo:
1309 case ARM::VST3LNq32Pseudo:
1310 case ARM::VST3LNd8Pseudo_UPD:
1311 case ARM::VST3LNd16Pseudo_UPD:
1312 case ARM::VST3LNd32Pseudo_UPD:
1313 case ARM::VST3LNq16Pseudo_UPD:
1314 case ARM::VST3LNq32Pseudo_UPD:
1315 case ARM::VST4LNd8Pseudo:
1316 case ARM::VST4LNd16Pseudo:
1317 case ARM::VST4LNd32Pseudo:
1318 case ARM::VST4LNq16Pseudo:
1319 case ARM::VST4LNq32Pseudo:
1320 case ARM::VST4LNd8Pseudo_UPD:
1321 case ARM::VST4LNd16Pseudo_UPD:
1322 case ARM::VST4LNd32Pseudo_UPD:
1323 case ARM::VST4LNq16Pseudo_UPD:
1324 case ARM::VST4LNq32Pseudo_UPD:
1328 case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3,
false);
return true;
1329 case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4,
false);
return true;
1330 case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3,
true);
return true;
1331 case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4,
true);
return true;
1336 bool Modified =
false;
1341 Modified |= ExpandMI(MBB, MBBI);
1350 TII = STI->getInstrInfo();
1354 bool Modified =
false;
1357 Modified |= ExpandMBB(*MFI);
1359 MF.
verify(
this,
"After expanding ARM pseudo instructions.");
1366 return new ARMExpandPseudo();
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
const GlobalValue * getGlobal() const
static cl::opt< bool > VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden, cl::desc("Verify machine code after expanding ARM pseudos"))
static unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm)
static const NEONLdStTableEntry * LookupNEONLdSt(unsigned Opcode)
LookupNEONLdSt - Search the NEONLdStTable for information about a NEON load or store pseudo instructi...
Describe properties that are true of each instruction in the target description file.
void emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
Address of indexed Jump Table for switch.
FunctionPass * createARMExpandPseudoPass()
createARMExpandPseudoPass - returns an instance of the pseudo instruction expansion pass...
void verify(Pass *p=nullptr, const char *Banner=nullptr) const
verify - Run the current MachineFunction through the machine code verifier, useful for debugger use...
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
MachineBasicBlock reference.
const char * getSymbolName() const
Mask of live-out registers.
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
Mask of preserved registers.
static const MachineInstrBuilder & AddDefaultPred(const MachineInstrBuilder &MIB)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static const NEONLdStTableEntry NEONLdStTable[]
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
virtual bool hasFP(const MachineFunction &MF) const =0
hasFP - Return true if the specified function should have a dedicated frame pointer register...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Target-dependent index+offset operand.
unsigned getFrameRegister(const MachineFunction &MF) const override
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void setImplicit(bool Val=true)
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
Name of external global symbol.
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
const HexagonRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Immediate >64bit operand.
unsigned getUndefRegState(bool B)
unsigned getKillRegState(bool B)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineBasicBlock * getParent() const
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
unsigned getDeadRegState(bool B)
mmo_iterator memoperands_end() const
bundle_iterator< MachineInstr, instr_iterator > iterator
Address of a global value.
unsigned getTargetFlags() const
const MachineInstrBuilder & setMemRefs(MachineInstr::mmo_iterator b, MachineInstr::mmo_iterator e) const
ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg)
getInstrPredicate - If instruction is predicated, returns its predicate condition, otherwise returns AL.
static unsigned getSOImmTwoPartSecond(unsigned V)
getSOImmTwoPartSecond - If V is a value that satisfies isSOImmTwoPartVal, return the second chunk of ...
const MachineOperand & getOperand(unsigned i) const
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags=0)
Address of a basic block.
#define LLVM_ATTRIBUTE_UNUSED
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
FunctionPass class - This class is used to implement most global optimizations.
int64_t getOffset() const
Return the offset from the symbol in this operand.
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Abstract base class for all machine specific constantpool value subclasses.
void emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of instructions to materializea des...
MO_LO16 - On a symbol operand, this represents a relocation containing lower 16 bit of the address...
virtual const TargetFrameLowering * getFrameLowering() const
static const MachineInstrBuilder & AddDefaultCC(const MachineInstrBuilder &MIB)
MachineOperand class - Representation of each machine instruction operand.
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MCSymbol reference (for debug/eh info)
bool hasBasePointer(const MachineFunction &MF) const
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned char TargetFlags=0) const
Representation of each machine instruction.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc, const TargetRegisterInfo *TRI, unsigned &D0, unsigned &D1, unsigned &D2, unsigned &D3)
GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register, corresponding to the specified regis...
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
Abstract Stack Frame Index.
unsigned getReg() const
getReg - Returns the register number.
bool operator<(int64_t V1, const APSInt &V2)
virtual const ARMBaseRegisterInfo & getRegisterInfo() const =0
Floating-point immediate operand.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
static bool IsAnAddressOperand(const MachineOperand &MO)
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
static const unsigned FramePtr
BasicBlockListType::iterator iterator
bool addRegisterKilled(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
Address of indexed Constant in Constant Pool.
static unsigned getSOImmTwoPartFirst(unsigned V)
getSOImmTwoPartFirst - If V is a value that satisfies isSOImmTwoPartVal, return the first chunk of it...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
void finalizeBundle(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
finalizeBundle - Finalize a machine instruction bundle which includes a sequence of instructions star...
bool needsStackRealignment(const MachineFunction &MF) const override
void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd)
Assign this MachineInstr's memory reference descriptor list.
static ARMConstantPoolConstant * Create(const Constant *C, unsigned ID)
MO_HI16 - On a symbol operand, this represents a relocation containing higher 16 bit of the address...
Metadata reference (for debug info)
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.