LLVM  3.7.0
HexagonPeephole.cpp
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1 //===-- HexagonPeephole.cpp - Hexagon Peephole Optimiztions ---------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 // This peephole pass optimizes in the following cases.
9 // 1. Optimizes redundant sign extends for the following case
10 // Transform the following pattern
11 // %vreg170<def> = SXTW %vreg166
12 // ...
13 // %vreg176<def> = COPY %vreg170:subreg_loreg
14 //
15 // Into
16 // %vreg176<def> = COPY vreg166
17 //
18 // 2. Optimizes redundant negation of predicates.
19 // %vreg15<def> = CMPGTrr %vreg6, %vreg2
20 // ...
21 // %vreg16<def> = NOT_p %vreg15<kill>
22 // ...
23 // JMP_c %vreg16<kill>, <BB#1>, %PC<imp-def,dead>
24 //
25 // Into
26 // %vreg15<def> = CMPGTrr %vreg6, %vreg2;
27 // ...
28 // JMP_cNot %vreg15<kill>, <BB#1>, %PC<imp-def,dead>;
29 //
30 // Note: The peephole pass makes the instrucstions like
31 // %vreg170<def> = SXTW %vreg166 or %vreg16<def> = NOT_p %vreg15<kill>
32 // redundant and relies on some form of dead removal instructions, like
33 // DCE or DIE to actually eliminate them.
34 
35 
36 //===----------------------------------------------------------------------===//
37 
38 #include "Hexagon.h"
39 #include "HexagonTargetMachine.h"
40 #include "llvm/ADT/DenseMap.h"
41 #include "llvm/ADT/Statistic.h"
46 #include "llvm/CodeGen/Passes.h"
47 #include "llvm/IR/Constants.h"
48 #include "llvm/PassSupport.h"
50 #include "llvm/Support/Debug.h"
55 #include <algorithm>
56 
57 using namespace llvm;
58 
59 #define DEBUG_TYPE "hexagon-peephole"
60 
61 static cl::opt<bool> DisableHexagonPeephole("disable-hexagon-peephole",
63  cl::desc("Disable Peephole Optimization"));
64 
65 static cl::opt<bool> DisablePNotP("disable-hexagon-pnotp",
67  cl::desc("Disable Optimization of PNotP"));
68 
69 static cl::opt<bool> DisableOptSZExt("disable-hexagon-optszext",
71  cl::desc("Disable Optimization of Sign/Zero Extends"));
72 
73 static cl::opt<bool> DisableOptExtTo64("disable-hexagon-opt-ext-to-64",
75  cl::desc("Disable Optimization of extensions to i64."));
76 
77 namespace llvm {
80 }
81 
82 namespace {
83  struct HexagonPeephole : public MachineFunctionPass {
84  const HexagonInstrInfo *QII;
85  const HexagonRegisterInfo *QRI;
86  const MachineRegisterInfo *MRI;
87 
88  public:
89  static char ID;
90  HexagonPeephole() : MachineFunctionPass(ID) {
92  }
93 
94  bool runOnMachineFunction(MachineFunction &MF) override;
95 
96  const char *getPassName() const override {
97  return "Hexagon optimize redundant zero and size extends";
98  }
99 
100  void getAnalysisUsage(AnalysisUsage &AU) const override {
102  }
103 
104  private:
105  void ChangeOpInto(MachineOperand &Dst, MachineOperand &Src);
106  };
107 }
108 
109 char HexagonPeephole::ID = 0;
110 
111 INITIALIZE_PASS(HexagonPeephole, "hexagon-peephole", "Hexagon Peephole",
112  false, false)
113 
114 bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
115  QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo());
116  QRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
117  MRI = &MF.getRegInfo();
118 
119  DenseMap<unsigned, unsigned> PeepholeMap;
120  DenseMap<unsigned, std::pair<unsigned, unsigned> > PeepholeDoubleRegsMap;
121 
122  if (DisableHexagonPeephole) return false;
123 
124  // Loop over all of the basic blocks.
125  for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end();
126  MBBb != MBBe; ++MBBb) {
127  MachineBasicBlock* MBB = MBBb;
128  PeepholeMap.clear();
129  PeepholeDoubleRegsMap.clear();
130 
131  // Traverse the basic block.
132  for (MachineBasicBlock::iterator MII = MBB->begin(); MII != MBB->end();
133  ++MII) {
134  MachineInstr *MI = MII;
135  // Look for sign extends:
136  // %vreg170<def> = SXTW %vreg166
137  if (!DisableOptSZExt && MI->getOpcode() == Hexagon::A2_sxtw) {
138  assert (MI->getNumOperands() == 2);
139  MachineOperand &Dst = MI->getOperand(0);
140  MachineOperand &Src = MI->getOperand(1);
141  unsigned DstReg = Dst.getReg();
142  unsigned SrcReg = Src.getReg();
143  // Just handle virtual registers.
146  // Map the following:
147  // %vreg170<def> = SXTW %vreg166
148  // PeepholeMap[170] = vreg166
149  PeepholeMap[DstReg] = SrcReg;
150  }
151  }
152 
153  // Look for %vreg170<def> = COMBINE_ir_V4 (0, %vreg169)
154  // %vreg170:DoublRegs, %vreg169:IntRegs
155  if (!DisableOptExtTo64 &&
156  MI->getOpcode () == Hexagon::A4_combineir) {
157  assert (MI->getNumOperands() == 3);
158  MachineOperand &Dst = MI->getOperand(0);
159  MachineOperand &Src1 = MI->getOperand(1);
160  MachineOperand &Src2 = MI->getOperand(2);
161  if (Src1.getImm() != 0)
162  continue;
163  unsigned DstReg = Dst.getReg();
164  unsigned SrcReg = Src2.getReg();
165  PeepholeMap[DstReg] = SrcReg;
166  }
167 
168  // Look for this sequence below
169  // %vregDoubleReg1 = LSRd_ri %vregDoubleReg0, 32
170  // %vregIntReg = COPY %vregDoubleReg1:subreg_loreg.
171  // and convert into
172  // %vregIntReg = COPY %vregDoubleReg0:subreg_hireg.
173  if (MI->getOpcode() == Hexagon::S2_lsr_i_p) {
174  assert(MI->getNumOperands() == 3);
175  MachineOperand &Dst = MI->getOperand(0);
176  MachineOperand &Src1 = MI->getOperand(1);
177  MachineOperand &Src2 = MI->getOperand(2);
178  if (Src2.getImm() != 32)
179  continue;
180  unsigned DstReg = Dst.getReg();
181  unsigned SrcReg = Src1.getReg();
182  PeepholeDoubleRegsMap[DstReg] =
183  std::make_pair(*&SrcReg, 1/*Hexagon::subreg_hireg*/);
184  }
185 
186  // Look for P=NOT(P).
187  if (!DisablePNotP &&
188  (MI->getOpcode() == Hexagon::C2_not)) {
189  assert (MI->getNumOperands() == 2);
190  MachineOperand &Dst = MI->getOperand(0);
191  MachineOperand &Src = MI->getOperand(1);
192  unsigned DstReg = Dst.getReg();
193  unsigned SrcReg = Src.getReg();
194  // Just handle virtual registers.
197  // Map the following:
198  // %vreg170<def> = NOT_xx %vreg166
199  // PeepholeMap[170] = vreg166
200  PeepholeMap[DstReg] = SrcReg;
201  }
202  }
203 
204  // Look for copy:
205  // %vreg176<def> = COPY %vreg170:subreg_loreg
206  if (!DisableOptSZExt && MI->isCopy()) {
207  assert (MI->getNumOperands() == 2);
208  MachineOperand &Dst = MI->getOperand(0);
209  MachineOperand &Src = MI->getOperand(1);
210 
211  // Make sure we are copying the lower 32 bits.
212  if (Src.getSubReg() != Hexagon::subreg_loreg)
213  continue;
214 
215  unsigned DstReg = Dst.getReg();
216  unsigned SrcReg = Src.getReg();
219  // Try to find in the map.
220  if (unsigned PeepholeSrc = PeepholeMap.lookup(SrcReg)) {
221  // Change the 1st operand.
222  MI->RemoveOperand(1);
223  MI->addOperand(MachineOperand::CreateReg(PeepholeSrc, false));
224  } else {
226  PeepholeDoubleRegsMap.find(SrcReg);
227  if (DI != PeepholeDoubleRegsMap.end()) {
228  std::pair<unsigned,unsigned> PeepholeSrc = DI->second;
229  MI->RemoveOperand(1);
230  MI->addOperand(MachineOperand::CreateReg(PeepholeSrc.first,
231  false /*isDef*/,
232  false /*isImp*/,
233  false /*isKill*/,
234  false /*isDead*/,
235  false /*isUndef*/,
236  false /*isEarlyClobber*/,
237  PeepholeSrc.second));
238  }
239  }
240  }
241  }
242 
243  // Look for Predicated instructions.
244  if (!DisablePNotP) {
245  bool Done = false;
246  if (QII->isPredicated(MI)) {
247  MachineOperand &Op0 = MI->getOperand(0);
248  unsigned Reg0 = Op0.getReg();
249  const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0);
250  if (RC0->getID() == Hexagon::PredRegsRegClassID) {
251  // Handle instructions that have a prediate register in op0
252  // (most cases of predicable instructions).
254  // Try to find in the map.
255  if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) {
256  // Change the 1st operand and, flip the opcode.
257  MI->getOperand(0).setReg(PeepholeSrc);
258  int NewOp = QII->getInvertedPredicatedOpcode(MI->getOpcode());
259  MI->setDesc(QII->get(NewOp));
260  Done = true;
261  }
262  }
263  }
264  }
265 
266  if (!Done) {
267  // Handle special instructions.
268  unsigned Op = MI->getOpcode();
269  unsigned NewOp = 0;
270  unsigned PR = 1, S1 = 2, S2 = 3; // Operand indices.
271 
272  switch (Op) {
273  case Hexagon::C2_mux:
274  case Hexagon::C2_muxii:
275  NewOp = Op;
276  break;
277  case Hexagon::C2_muxri:
278  NewOp = Hexagon::C2_muxir;
279  break;
280  case Hexagon::C2_muxir:
281  NewOp = Hexagon::C2_muxri;
282  break;
283  }
284  if (NewOp) {
285  unsigned PSrc = MI->getOperand(PR).getReg();
286  if (unsigned POrig = PeepholeMap.lookup(PSrc)) {
287  MI->getOperand(PR).setReg(POrig);
288  MI->setDesc(QII->get(NewOp));
289  // Swap operands S1 and S2.
290  MachineOperand Op1 = MI->getOperand(S1);
291  MachineOperand Op2 = MI->getOperand(S2);
292  ChangeOpInto(MI->getOperand(S1), Op2);
293  ChangeOpInto(MI->getOperand(S2), Op1);
294  }
295  } // if (NewOp)
296  } // if (!Done)
297 
298  } // if (!DisablePNotP)
299 
300  } // Instruction
301  } // Basic Block
302  return true;
303 }
304 
305 void HexagonPeephole::ChangeOpInto(MachineOperand &Dst, MachineOperand &Src) {
306  assert (&Dst != &Src && "Cannot duplicate into itself");
307  switch (Dst.getType()) {
309  if (Src.isReg()) {
310  Dst.setReg(Src.getReg());
311  } else if (Src.isImm()) {
312  Dst.ChangeToImmediate(Src.getImm());
313  } else {
314  llvm_unreachable("Unexpected src operand type");
315  }
316  break;
317 
319  if (Src.isImm()) {
320  Dst.setImm(Src.getImm());
321  } else if (Src.isReg()) {
322  Dst.ChangeToRegister(Src.getReg(), Src.isDef(), Src.isImplicit(),
323  Src.isKill(), Src.isDead(), Src.isUndef(),
324  Src.isDebug());
325  } else {
326  llvm_unreachable("Unexpected src operand type");
327  }
328  break;
329 
330  default:
331  llvm_unreachable("Unexpected dst operand type");
332  break;
333  }
334 }
335 
337  return new HexagonPeephole();
338 }
bool isImplicit() const
INITIALIZE_PASS(HexagonPeephole,"hexagon-peephole","Hexagon Peephole", false, false) bool HexagonPeephole
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
ValueT lookup(const KeyT &Val) const
lookup - Return the entry for the specified key, or a default constructed value if no such entry exis...
Definition: DenseMap.h:159
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
bool isDead() const
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
unsigned getID() const
getID() - Return the register class ID number.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false)
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
static cl::opt< bool > DisableOptExtTo64("disable-hexagon-opt-ext-to-64", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable Optimization of extensions to i64."))
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isUndef() const
static cl::opt< bool > DisablePNotP("disable-hexagon-pnotp", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable Optimization of PNotP"))
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:271
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
bool isKill() const
int64_t getImm() const
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:267
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
bundle_iterator< MachineInstr, instr_iterator > iterator
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:325
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
bool isCopy() const
Definition: MachineInstr.h:778
Represent the analysis usage information of a pass.
void setImm(int64_t immVal)
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:294
unsigned getSubReg() const
void initializeHexagonPeepholePass(PassRegistry &)
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
MachineOperand class - Representation of each machine instruction operand.
static cl::opt< bool > DisableOptSZExt("disable-hexagon-optszext", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable Optimization of Sign/Zero Extends"))
FunctionPass * createHexagonPeephole()
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:51
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
static cl::opt< bool > DisableHexagonPeephole("disable-hexagon-peephole", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable Peephole Optimization"))
void setReg(unsigned Reg)
Change the register this operand corresponds to.
unsigned getReg() const
getReg - Returns the register number.
bool isDebug() const
BasicBlockListType::iterator iterator
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:41