15 #ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
16 #define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
25 class ARMConstantPoolValue;
253 EVT VT)
const override;
260 SDNode *Node)
const override;
272 bool *
Fast)
const override;
275 unsigned DstAlign,
unsigned SrcAlign,
276 bool IsMemset,
bool ZeroMemset,
291 Type *Ty,
unsigned AS)
const override;
323 unsigned Depth)
const override;
333 AsmOperandInfo &
info,
const char *constraint)
const override;
335 std::pair<unsigned, const TargetRegisterClass *>
344 std::vector<SDValue> &Ops,
349 if (ConstraintCode ==
"Q")
351 else if (ConstraintCode.
size() == 2) {
352 if (ConstraintCode[0] ==
'U') {
353 switch(ConstraintCode[1]) {
391 unsigned &PrefAlign)
const override;
411 unsigned Intrinsic)
const override;
416 Type *Ty)
const override;
431 bool IsStore,
bool IsLoad)
const override;
433 bool IsStore,
bool IsLoad)
const override;
440 unsigned Factor)
const override;
442 unsigned Factor)
const override;
452 unsigned &Cost)
const override;
455 std::pair<const TargetRegisterClass *, uint8_t>
457 MVT VT)
const override;
470 unsigned ARMPCLabelIndex;
472 void addTypeForNEON(
MVT VT,
MVT PromotedLdStVT,
MVT PromotedBitwiseVT);
473 void addDRTypeForNEON(
MVT VT);
474 void addQRTypeForNEON(
MVT VT);
480 RegsToPassVector &RegsToPass,
490 bool isVarArg)
const;
492 bool isVarArg)
const;
535 unsigned getRegisterByName(
const char* RegName,
EVT VT,
547 bool isFMAFasterThanFMulAndFAdd(
EVT VT)
const override {
return false; }
549 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG)
const;
551 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
553 const SmallVectorImpl<ISD::InputArg> &
Ins,
554 SDLoc dl, SelectionDAG &DAG,
555 SmallVectorImpl<SDValue> &InVals,
556 bool isThisReturn, SDValue ThisVal)
const;
559 LowerFormalArguments(SDValue Chain,
561 const SmallVectorImpl<ISD::InputArg> &
Ins,
562 SDLoc dl, SelectionDAG &DAG,
563 SmallVectorImpl<SDValue> &InVals)
const override;
565 int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
566 SDLoc dl, SDValue &Chain,
567 const Value *OrigArg,
568 unsigned InRegsParamRecordIdx,
570 unsigned ArgSize)
const;
572 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
573 SDLoc dl, SDValue &Chain,
575 unsigned TotalArgRegsSaveSize,
576 bool ForceMutable =
false)
const;
579 LowerCall(TargetLowering::CallLoweringInfo &CLI,
580 SmallVectorImpl<SDValue> &InVals)
const override;
583 void HandleByVal(CCState *,
unsigned &,
unsigned)
const override;
588 bool IsEligibleForTailCallOptimization(SDValue Callee,
591 bool isCalleeStructRet,
592 bool isCallerStructRet,
593 const SmallVectorImpl<ISD::OutputArg> &Outs,
594 const SmallVectorImpl<SDValue> &OutVals,
595 const SmallVectorImpl<ISD::InputArg> &
Ins,
596 SelectionDAG& DAG)
const;
599 MachineFunction &MF,
bool isVarArg,
600 const SmallVectorImpl<ISD::OutputArg> &Outs,
601 LLVMContext &Context)
const override;
604 LowerReturn(SDValue Chain,
606 const SmallVectorImpl<ISD::OutputArg> &Outs,
607 const SmallVectorImpl<SDValue> &OutVals,
608 SDLoc dl, SelectionDAG &DAG)
const override;
610 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain)
const override;
612 bool mayBeEmittedAsTailCall(CallInst *CI)
const override;
614 SDValue getCMOV(SDLoc dl, EVT VT, SDValue FalseVal, SDValue TrueVal,
615 SDValue ARMcc, SDValue CCR, SDValue Cmp,
616 SelectionDAG &DAG)
const;
617 SDValue getARMCmp(SDValue LHS, SDValue RHS,
ISD::CondCode CC,
618 SDValue &ARMcc, SelectionDAG &DAG, SDLoc dl)
const;
619 SDValue getVFPCmp(SDValue LHS, SDValue RHS,
620 SelectionDAG &DAG, SDLoc dl)
const;
621 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG)
const;
623 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG)
const;
625 void SetupEntryBlockForSjLj(MachineInstr *
MI,
626 MachineBasicBlock *MBB,
627 MachineBasicBlock *DispatchBB,
int FI)
const;
629 void EmitSjLjDispatchBlock(MachineInstr *
MI, MachineBasicBlock *MBB)
const;
631 bool RemapAddSubWithFlags(MachineInstr *
MI, MachineBasicBlock *BB)
const;
633 MachineBasicBlock *EmitStructByval(MachineInstr *
MI,
634 MachineBasicBlock *MBB)
const;
636 MachineBasicBlock *EmitLowered__chkstk(MachineInstr *
MI,
637 MachineBasicBlock *MBB)
const;
648 const TargetLibraryInfo *libInfo);
652 #endif // ARMISELLOWERING_H
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
BUILTIN_OP_END - This must be the last enum value in this list.
A parsed version of the target data layout string in and methods for querying it. ...
TargetLoweringBase::AtomicRMWExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all...
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - Return the value type to use for ISD::SETCC.
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...
size_t size() const
size - Get the string size.
bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
getPreIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mod...
CallInst - This class represents a function call, abstracting a target machine's calling convention...
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
ShuffleVectorInst - This instruction constructs a fixed permutation of two input vectors.
virtual bool isZExtFree(Type *, Type *) const
Return true if any actual instruction that defines a value of type Ty1 implicitly zero-extends the va...
LoadInst - an instruction for reading from memory.
AtomicRMWInst - an instruction that atomically reads a memory location, combines it with another valu...
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
createFastISel - This method returns a target specific FastISel object, or null if the target does no...
bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override
Return true if it is profitable for dag combiner to transform a floating point op of specified opcode...
bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override
Return true if a truncation from Ty1 to Ty2 is permitted when deciding whether a call is in tail posi...
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const override
Lower an interleaved store into a vstN intrinsic.
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
AtomicRMWExpansionKind
Enum that specifies what a AtomicRMWInst is expanded to, if at all.
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector.
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Value * emitStoreConditional(IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const override
Perform a store-conditional operation to Addr.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, MachineFunction &MF) const override
Returns the target specific optimal type for load and store operations as a result of memset...
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
ReplaceNodeResults - Replace the results of node with an illegal result type with new values built ou...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Sched::Preference getSchedulingPreference() const
Return target scheduling preference.
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
getPostIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mo...
bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx, unsigned &Cost) const override
Return true if the target can combine store(extractelement VectorTy, Idx).
bool shouldExpandAtomicLoadInIR(LoadInst *LI) const override
Returns true if the given (atomic) load should be expanded by the IR-level AtomicExpand pass into a l...
bool lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const override
Lower an interleaved load into a vldN intrinsic.
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Value * emitLoadLinked(IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const override
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type...
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Returns true if it is beneficial to convert a load of a constant to just the constant itself...
void AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const override
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Itinerary data supplied by a subtarget to be used by a target.
StoreInst - an instruction for storing to memory.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
A self-contained host- and target-independent arbitrary-precision floating-point software implementat...
bool useSoftFloat() const override
MVT - Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize, unsigned &PrefAlign) const override
Return true if the pointer arguments to CI should be aligned by aligning the object whose address is ...
This is an important class for using LLVM in a threaded context.
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
unsigned getJumpTableEncoding() const override
Return the entry encoding for a jump table in the current function.
std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const override
Return the largest legal super-reg register class of the register class for the specified type and it...
SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const
PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV.
EVT - Extended Value Type.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const ARMSubtarget * getSubtarget() const
unsigned getMaxSupportedInterleaveFactor() const override
Get the maximum supported factor for interleaved memory accesses.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Provides information about what library functions are available for the current target.
CCValAssign - Represent assignment of one arg/retval to a location.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
bool isFPImmLegal(const APFloat &Imm, EVT VT) const override
isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively...
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Represents one node in the SelectionDAG.
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
bool ExpandInlineAsm(CallInst *CI) const override
This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to...
Class for arbitrary precision integers.
Instruction * emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord, bool IsStore, bool IsLoad) const override
Inserts in the IR a target-specific intrinsic specifying a fence.
AddrMode
ARM Addressing Modes.
const TargetRegisterClass * getRegClassFor(MVT VT) const override
getRegClassFor - Return the register class that should be used for the specified value type...
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, unsigned Intrinsic) const override
getTgtMemIntrinsic - Represent NEON load and store intrinsics as MemIntrinsicNodes.
Representation of each machine instruction.
SelectSupportKind
Enum that describes what type of support for selects the target has.
bool isVectorLoadExtDesirable(SDValue ExtVal) const override
Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable...
Fast - This calling convention attempts to make calls as fast as possible (e.g.
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
bool isLegalAddImmediate(int64_t Imm) const override
isLegalAddImmediate - Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register and the immediate without having to materialize the immediate into a register.
bool isLegalICmpImmediate(int64_t Imm) const override
isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register.
bool hasLoadLinkedStoreConditional() const override
True if AtomicExpandPass should use emitLoadLinked/emitStoreConditional and expand AtomicCmpXchgInst...
const ARM::ArchExtKind Kind
bool isSelectSupported(SelectSupportKind Kind) const override
bool isShuffleMaskLegal(const SmallVectorImpl< int > &M, EVT VT) const override
isShuffleMaskLegal - Targets can use this to indicate that they only support some VECTOR_SHUFFLE oper...
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
LLVM Value Representation.
bool useLoadStackGuardNode() const override
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
Instruction * makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) const
ARMTargetLowering(const TargetMachine &TM, const ARMSubtarget &STI)
bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override
Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calli...
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target...
Primary interface to the complete machine description for the target machine.
StringRef - Represent a constant reference to a string, i.e.
bool isZExtFree(SDValue Val, EVT VT2) const override
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicit...
bool isBitFieldInvertedMask(unsigned v)
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override
Returns true if the given (atomic) store should be expanded by the IR-level AtomicExpand pass into an...
bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const
Instruction * emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord, bool IsStore, bool IsLoad) const override
This file describes how to lower LLVM code to machine code.
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, unsigned Align, bool *Fast) const override
allowsMisalignedMemoryAccesses - Returns true if the target allows unaligned memory accesses of the s...
void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.