14 #ifndef LLVM_LIB_TARGET_ARM_THUMB2INSTRINFO_H
15 #define LLVM_LIB_TARGET_ARM_THUMB2INSTRINFO_H
22 class ScheduleHazardRecognizer;
44 unsigned DestReg,
unsigned SrcReg,
45 bool KillSrc)
const override;
55 unsigned DestReg,
int FrameIndex,
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg)
getITInstrPredicate - Valid only in Thumb2 mode.
void getNoopForMachoTarget(MCInst &NopInst) const override
getNoopForMachoTarget - Return the noop instruction to use for a noop.
bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const override
Instances of this class represent a single low-level machine instruction.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bundle_iterator< MachineInstr, instr_iterator > iterator
unsigned getUnindexedOpcode(unsigned Opc) const override
bundle_iterator - MachineBasicBlock iterator that automatically skips over MIs that are inside bundle...
Thumb2InstrInfo(const ARMSubtarget &STI)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const override
const ThumbRegisterInfo & getRegisterInfo() const override
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.