LLVM  3.7.0
ExpandPostRAPseudos.cpp
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1 //===-- ExpandPostRAPseudos.cpp - Pseudo instruction expansion pass -------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines a pass that expands COPY and SUBREG_TO_REG pseudo
11 // instructions after register allocation.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "llvm/CodeGen/Passes.h"
20 #include "llvm/Support/Debug.h"
25 
26 using namespace llvm;
27 
28 #define DEBUG_TYPE "postrapseudos"
29 
30 namespace {
31 struct ExpandPostRA : public MachineFunctionPass {
32 private:
33  const TargetRegisterInfo *TRI;
34  const TargetInstrInfo *TII;
35 
36 public:
37  static char ID; // Pass identification, replacement for typeid
38  ExpandPostRA() : MachineFunctionPass(ID) {}
39 
40  void getAnalysisUsage(AnalysisUsage &AU) const override {
41  AU.setPreservesCFG();
45  }
46 
47  /// runOnMachineFunction - pass entry point
48  bool runOnMachineFunction(MachineFunction&) override;
49 
50 private:
51  bool LowerSubregToReg(MachineInstr *MI);
52  bool LowerCopy(MachineInstr *MI);
53 
54  void TransferImplicitDefs(MachineInstr *MI);
55 };
56 } // end anonymous namespace
57 
58 char ExpandPostRA::ID = 0;
60 
61 INITIALIZE_PASS(ExpandPostRA, "postrapseudos",
62  "Post-RA pseudo instruction expansion pass", false, false)
63 
64 /// TransferImplicitDefs - MI is a pseudo-instruction, and the lowered
65 /// replacement instructions immediately precede it. Copy any implicit-def
66 /// operands from MI to the replacement instruction.
67 void
68 ExpandPostRA::TransferImplicitDefs(MachineInstr *MI) {
70  --CopyMI;
71 
72  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
73  MachineOperand &MO = MI->getOperand(i);
74  if (!MO.isReg() || !MO.isImplicit() || MO.isUse())
75  continue;
76  CopyMI->addOperand(MachineOperand::CreateReg(MO.getReg(), true, true));
77  }
78 }
79 
80 bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) {
81  MachineBasicBlock *MBB = MI->getParent();
82  assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
83  MI->getOperand(1).isImm() &&
84  (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
85  MI->getOperand(3).isImm() && "Invalid subreg_to_reg");
86 
87  unsigned DstReg = MI->getOperand(0).getReg();
88  unsigned InsReg = MI->getOperand(2).getReg();
89  assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?");
90  unsigned SubIdx = MI->getOperand(3).getImm();
91 
92  assert(SubIdx != 0 && "Invalid index for insert_subreg");
93  unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
94 
96  "Insert destination must be in a physical register");
98  "Inserted value must be in a physical register");
99 
100  DEBUG(dbgs() << "subreg: CONVERTING: " << *MI);
101 
102  if (MI->allDefsAreDead()) {
103  MI->setDesc(TII->get(TargetOpcode::KILL));
104  DEBUG(dbgs() << "subreg: replaced by: " << *MI);
105  return true;
106  }
107 
108  if (DstSubReg == InsReg) {
109  // No need to insert an identity copy instruction.
110  // Watch out for case like this:
111  // %RAX<def> = SUBREG_TO_REG 0, %EAX<kill>, 3
112  // We must leave %RAX live.
113  if (DstReg != InsReg) {
114  MI->setDesc(TII->get(TargetOpcode::KILL));
115  MI->RemoveOperand(3); // SubIdx
116  MI->RemoveOperand(1); // Imm
117  DEBUG(dbgs() << "subreg: replace by: " << *MI);
118  return true;
119  }
120  DEBUG(dbgs() << "subreg: eliminated!");
121  } else {
122  TII->copyPhysReg(*MBB, MI, MI->getDebugLoc(), DstSubReg, InsReg,
123  MI->getOperand(2).isKill());
124 
125  // Implicitly define DstReg for subsequent uses.
127  --CopyMI;
128  CopyMI->addRegisterDefined(DstReg);
129  DEBUG(dbgs() << "subreg: " << *CopyMI);
130  }
131 
132  DEBUG(dbgs() << '\n');
133  MBB->erase(MI);
134  return true;
135 }
136 
137 bool ExpandPostRA::LowerCopy(MachineInstr *MI) {
138 
139  if (MI->allDefsAreDead()) {
140  DEBUG(dbgs() << "dead copy: " << *MI);
141  MI->setDesc(TII->get(TargetOpcode::KILL));
142  DEBUG(dbgs() << "replaced by: " << *MI);
143  return true;
144  }
145 
146  MachineOperand &DstMO = MI->getOperand(0);
147  MachineOperand &SrcMO = MI->getOperand(1);
148 
149  if (SrcMO.getReg() == DstMO.getReg()) {
150  DEBUG(dbgs() << "identity copy: " << *MI);
151  // No need to insert an identity copy instruction, but replace with a KILL
152  // if liveness is changed.
153  if (SrcMO.isUndef() || MI->getNumOperands() > 2) {
154  // We must make sure the super-register gets killed. Replace the
155  // instruction with KILL.
156  MI->setDesc(TII->get(TargetOpcode::KILL));
157  DEBUG(dbgs() << "replaced by: " << *MI);
158  return true;
159  }
160  // Vanilla identity copy.
161  MI->eraseFromParent();
162  return true;
163  }
164 
165  DEBUG(dbgs() << "real copy: " << *MI);
166  TII->copyPhysReg(*MI->getParent(), MI, MI->getDebugLoc(),
167  DstMO.getReg(), SrcMO.getReg(), SrcMO.isKill());
168 
169  if (MI->getNumOperands() > 2)
170  TransferImplicitDefs(MI);
171  DEBUG({
173  dbgs() << "replaced by: " << *(--dMI);
174  });
175  MI->eraseFromParent();
176  return true;
177 }
178 
179 /// runOnMachineFunction - Reduce subregister inserts and extracts to register
180 /// copies.
181 ///
182 bool ExpandPostRA::runOnMachineFunction(MachineFunction &MF) {
183  DEBUG(dbgs() << "Machine Function\n"
184  << "********** EXPANDING POST-RA PSEUDO INSTRS **********\n"
185  << "********** Function: " << MF.getName() << '\n');
186  TRI = MF.getSubtarget().getRegisterInfo();
187  TII = MF.getSubtarget().getInstrInfo();
188 
189  bool MadeChange = false;
190 
191  for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
192  mbbi != mbbe; ++mbbi) {
193  for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
194  mi != me;) {
195  MachineInstr *MI = mi;
196  // Advance iterator here because MI may be erased.
197  ++mi;
198 
199  // Only expand pseudos.
200  if (!MI->isPseudo())
201  continue;
202 
203  // Give targets a chance to expand even standard pseudos.
204  if (TII->expandPostRAPseudo(MI)) {
205  MadeChange = true;
206  continue;
207  }
208 
209  // Expand standard pseudos.
210  switch (MI->getOpcode()) {
212  MadeChange |= LowerSubregToReg(MI);
213  break;
214  case TargetOpcode::COPY:
215  MadeChange |= LowerCopy(MI);
216  break;
218  continue;
221  llvm_unreachable("Sub-register pseudos should have been eliminated.");
222  }
223  }
224  }
225 
226  return MadeChange;
227 }
bool isImplicit() const
char & MachineDominatorsID
MachineDominators - This pass is a machine dominators analysis pass.
bool isPseudo(QueryType Type=IgnoreBundle) const
Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction...
Definition: MachineInstr.h:395
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
COPY - Target-independent register copy.
Definition: TargetOpcodes.h:86
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false)
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
bool isUndef() const
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:271
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
bool isKill() const
char & ExpandPostRAPseudosID
ExpandPostRAPseudos - This pass expands pseudo instructions after register allocation.
AnalysisUsage & addPreservedID(const void *ID)
int64_t getImm() const
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:267
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:120
TargetInstrInfo - Interface to description of machine instruction set.
DBG_VALUE - a mapping of the llvm.dbg.value intrinsic.
Definition: TargetOpcodes.h:69
bundle_iterator< MachineInstr, instr_iterator > iterator
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
INSERT_SUBREG - This instruction takes three operands: a register that has subregisters, a register providing an insert value, and a subregister index.
Definition: TargetOpcodes.h:49
Represent the analysis usage information of a pass.
bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override
expandPostRAPseudo - This function is called for all pseudo instructions that remain after register a...
unsigned getSubReg() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
EXTRACT_SUBREG - This instruction takes two operands: a register that has subregisters, and a subregister index.
Definition: TargetOpcodes.h:41
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
MachineOperand class - Representation of each machine instruction operand.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:263
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:123
INITIALIZE_PASS(ExpandPostRA,"postrapseudos","Post-RA pseudo instruction expansion pass", false, false) void ExpandPostRA
TransferImplicitDefs - MI is a pseudo-instruction, and the lowered replacement instructions immediate...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:238
KILL - This instruction is a noop that is used only to adjust the liveness of registers.
Definition: TargetOpcodes.h:35
Representation of each machine instruction.
Definition: MachineInstr.h:51
static bool isPhysicalRegister(unsigned Reg)
isPhysicalRegister - Return true if the specified register number is in the physical register namespa...
unsigned getReg() const
getReg - Returns the register number.
virtual const TargetInstrInfo * getInstrInfo() const
BasicBlockListType::iterator iterator
#define DEBUG(X)
Definition: Debug.h:92
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except that the first operand is an imme...
Definition: TargetOpcodes.h:58