38 #define DEBUG_TYPE "phielim"
43 "during PHI elimination"));
52 cl::desc(
"Do not use an early exit if isLiveOutPastPHIs returns true."));
94 typedef std::pair<unsigned, unsigned> BBVRegPair;
97 VRegPHIUse VRegPHIUseCount;
105 LoweredPHIMap LoweredPHIs;
109 STATISTIC(NumLowered,
"Number of phis lowered");
110 STATISTIC(NumCriticalEdgesSplit,
"Number of critical edges split");
111 STATISTIC(NumReused,
"Number of reused lowered phis");
117 "Eliminate PHI nodes for register allocation",
123 void PHIElimination::getAnalysisUsage(
AnalysisUsage &AU)
const {
134 LV = getAnalysisIfAvailable<LiveVariables>();
135 LIS = getAnalysisIfAvailable<LiveIntervals>();
137 bool Changed =
false;
147 Changed |= SplitPHIEdges(MF, MBB, MLI);
155 Changed |= EliminatePHINodes(MF, MBB);
159 unsigned DefReg = DefMI->getOperand(0).getReg();
160 if (MRI->use_nodbg_empty(DefReg)) {
162 LIS->RemoveMachineInstrFromMaps(DefMI);
163 DefMI->eraseFromParent();
168 for (LoweredPHIMap::iterator
I = LoweredPHIs.begin(), E = LoweredPHIs.end();
171 LIS->RemoveMachineInstrFromMaps(
I->first);
172 MF.DeleteMachineInstr(
I->first);
177 VRegPHIUseCount.clear();
196 LowerPHINode(MBB, LastPHIIt);
206 if (!
DI.isImplicitDef())
240 unsigned IncomingReg = 0;
241 bool reusedIncoming =
false;
255 unsigned &entry = LoweredPHIs[MPhi];
259 reusedIncoming =
true;
268 .addReg(IncomingReg);
279 LV->setPHIJoin(IncomingReg);
286 DEBUG(
dbgs() <<
"Remove old kill from " << *OldKill);
287 LV->removeVirtualRegisterKilled(IncomingReg, OldKill);
295 LV->addVirtualRegisterKilled(IncomingReg, PHICopy);
301 LV->removeVirtualRegistersKilled(MPhi);
305 LV->addVirtualRegisterDead(DestReg, PHICopy);
306 LV->removeVirtualRegisterDead(DestReg, MPhi);
313 SlotIndex DestCopyIndex = LIS->InsertMachineInstrInMaps(NewInstr);
315 SlotIndex MBBStartIndex = LIS->getMBBStartIdx(&MBB);
319 LiveInterval &IncomingLI = LIS->createEmptyInterval(IncomingReg);
323 LIS->getVNInfoAllocator());
324 IncomingLI.
addSegment(LiveInterval::Segment(MBBStartIndex,
330 assert(DestLI.
begin() != DestLI.
end() &&
331 "PHIs should have nonempty LiveIntervals.");
337 assert(OrigDestVNI &&
"PHI destination should be live at block entry.");
340 LIS->getVNInfoAllocator());
347 assert(DestVNI &&
"PHI destination should be live at its definition.");
360 for (
int i = NumSrcs - 1; i >= 0; --i) {
366 "Machine PHI Operands must all be virtual registers!");
375 if (!MBBsInsertedInto.
insert(&opBlock).second)
385 if (!reusedIncoming && IncomingReg) {
396 if (DefMI->isImplicitDef())
397 ImpDefs.insert(DefMI);
401 .addReg(SrcReg, 0, SrcSubReg);
408 if (LV && !SrcUndef &&
409 !VRegPHIUseCount[BBVRegPair(opBlock.
getNumber(), SrcReg)] &&
410 !LV->isLiveOut(SrcReg, opBlock)) {
430 Term != opBlock.
end(); ++Term) {
431 if (Term->readsRegister(SrcReg))
435 if (KillInst == opBlock.
end()) {
438 if (reusedIncoming || !IncomingReg) {
440 KillInst = FirstTerm;
441 while (KillInst != opBlock.
begin()) {
443 if (KillInst->isDebugValue())
445 if (KillInst->readsRegister(SrcReg))
450 KillInst = std::prev(InsertPos);
453 assert(KillInst->readsRegister(SrcReg) &&
"Cannot find kill instruction");
456 LV->addVirtualRegisterKilled(SrcReg, KillInst);
459 unsigned opBlockNum = opBlock.
getNumber();
460 LV->getVarInfo(SrcReg).AliveBlocks.reset(opBlockNum);
465 LIS->InsertMachineInstrInMaps(NewSrcInstr);
466 LIS->addSegmentToEndOfBlock(IncomingReg, NewSrcInstr);
470 !VRegPHIUseCount[BBVRegPair(opBlock.
getNumber(), SrcReg)]) {
473 bool isLiveOut =
false;
476 SlotIndex startIdx = LIS->getMBBStartIdx(*SI);
480 if (VNI && VNI->
def != startIdx) {
490 Term != opBlock.
end(); ++Term) {
491 if (Term->readsRegister(SrcReg))
495 if (KillInst == opBlock.
end()) {
498 if (reusedIncoming || !IncomingReg) {
500 KillInst = FirstTerm;
501 while (KillInst != opBlock.
begin()) {
503 if (KillInst->isDebugValue())
505 if (KillInst->readsRegister(SrcReg))
510 KillInst = std::prev(InsertPos);
513 assert(KillInst->readsRegister(SrcReg) &&
514 "Cannot find kill instruction");
516 SlotIndex LastUseIndex = LIS->getInstructionIndex(KillInst);
518 LIS->getMBBEndIdx(&opBlock));
525 if (reusedIncoming || !IncomingReg) {
527 LIS->RemoveMachineInstrFromMaps(MPhi);
538 for (
const auto &MBB : MF)
539 for (
const auto &BBI : MBB) {
542 for (
unsigned i = 1, e = BBI.getNumOperands(); i != e; i += 2)
543 ++VRegPHIUseCount[BBVRegPair(BBI.getOperand(i+1).getMBB()->getNumber(),
544 BBI.getOperand(i).getReg())];
555 bool IsLoopHeader = CurLoop && &MBB == CurLoop->
getHeader();
557 bool Changed =
false;
559 BBI != BBE && BBI->isPHI(); ++BBI) {
560 for (
unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
561 unsigned Reg = BBI->getOperand(i).getReg();
581 bool ShouldSplit = isLiveOutPastPHIs(Reg, PreMBB);
586 << PreMBB->
getNumber() <<
" -> BB#" << MBB.getNumber()
598 ShouldSplit = ShouldSplit && !isLiveIn(Reg, &MBB);
601 if (!ShouldSplit && CurLoop != PreLoop) {
603 dbgs() <<
"Split wouldn't help, maybe avoid loop copies?\n";
604 if (PreLoop)
dbgs() <<
"PreLoop: " << *PreLoop;
605 if (CurLoop)
dbgs() <<
"CurLoop: " << *CurLoop;
611 ShouldSplit = PreLoop && !PreLoop->
contains(CurLoop);
616 DEBUG(
dbgs() <<
"Failed to split critical edge.\n");
620 ++NumCriticalEdgesSplit;
627 assert((LV || LIS) &&
628 "isLiveIn() requires either LiveVariables or LiveIntervals");
630 return LIS->isLiveInToMBB(LIS->getInterval(Reg), MBB);
632 return LV->isLiveIn(Reg, *MBB);
635 bool PHIElimination::isLiveOutPastPHIs(
unsigned Reg,
637 assert((LV || LIS) &&
638 "isLiveOutPastPHIs() requires either LiveVariables or LiveIntervals");
647 if (LI.
liveAt(LIS->getMBBStartIdx(SI)))
651 return LV->isLiveOut(Reg, *MBB);
unsigned succ_size() const
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
SlotIndex def
The index of the defining instruction.
STATISTIC(NumFunctions,"Total number of functions")
MachineBasicBlock * getMBB() const
int getNumber() const
getNumber - MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a M...
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
LiveInterval - This class represents the liveness of a register, or stack slot.
iterator getFirstTerminator()
getFirstTerminator - returns an iterator to the first terminator instruction of this basic block...
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
MachineBasicBlock::iterator findPHICopyInsertPoint(MachineBasicBlock *MBB, MachineBasicBlock *SuccMBB, unsigned SrcReg)
findPHICopyInsertPoint - Find a safe place in MBB to insert a copy from SrcReg when following the CFG...
phi node Eliminate PHI nodes for register false
static cl::opt< bool > DisableEdgeSplitting("disable-phi-elim-edge-splitting", cl::init(false), cl::Hidden, cl::desc("Disable critical edge splitting ""during PHI elimination"))
VarInfo - This represents the regions where a virtual register is live in the program.
unsigned SplitAllCriticalEdges(Function &F, const CriticalEdgeSplittingOptions &Options=CriticalEdgeSplittingOptions())
VNInfo - Value Number Information.
static bool isImplicitlyDefined(unsigned VirtReg, const MachineRegisterInfo *MRI)
isImplicitlyDefined - Return true if all defs of VirtReg are implicit-defs.
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
BlockT * getHeader() const
Special DenseMapInfo traits to compare MachineInstr* by value of the instruction rather than by point...
iterator_range< succ_iterator > successors()
COPY - Target-independent register copy.
#define INITIALIZE_PASS_DEPENDENCY(depName)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
const TargetRegisterClass * getRegClass(unsigned Reg) const
getRegClass - Return the register class of the specified virtual register.
std::vector< MachineBasicBlock * >::iterator succ_iterator
Reg
All possible values of the reg field in the ModR/M byte.
MachineBasicBlock * SplitCriticalEdge(MachineBasicBlock *Succ, Pass *P)
SplitCriticalEdge - Split the critical edge from this block to the given successor block...
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
PrintReg - Helper class for printing registers on a raw_ostream.
bool isDead() const
isDead - Returns true if this is a dead def kill slot.
iterator addSegment(Segment S)
Add the specified Segment to this range, merging segments as appropriate.
static cl::opt< bool > NoPhiElimLiveOutEarlyExit("no-phi-elim-live-out-early-exit", cl::init(false), cl::Hidden, cl::desc("Do not use an early exit if isLiveOutPastPHIs returns true."))
TargetInstrInfo - Interface to description of machine instruction set.
char & PHIEliminationID
PHIElimination - This pass eliminates machine instruction PHI nodes by inserting copy instructions...
IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
MachineLoop * getLoopFor(const MachineBasicBlock *BB) const
getLoopFor - Return the inner most loop that BB lives in.
bundle_iterator< MachineInstr, instr_iterator > iterator
void removeValNo(VNInfo *ValNo)
removeValNo - Remove all the segments defined by the specified value#.
initializer< Ty > init(const Ty &Val)
iterator SkipPHIsAndLabels(iterator I)
SkipPHIsAndLabels - Return the first instruction in MBB after I that is not a PHI or a label...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
const MachineOperand & getOperand(unsigned i) const
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Represent the analysis usage information of a pass.
bool contains(const LoopT *L) const
contains - Return true if the specified loop is contained within in this loop.
for(unsigned i=0, e=MI->getNumOperands();i!=e;++i)
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
succ_iterator succ_begin()
unsigned getSubReg() const
void DeleteMachineInstr(MachineInstr *MI)
DeleteMachineInstr - Delete the given MachineInstr.
bool liveAt(SlotIndex index) const
void initializePHIEliminationPass(PassRegistry &)
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
void removeSegment(SlotIndex Start, SlotIndex End, bool RemoveDeadValNo=false)
Remove the specified segment from this range.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
MachineInstr * remove(MachineInstr *I)
Remove the unbundled instruction from the instruction list without deleting it.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
INITIALIZE_PASS_BEGIN(PHIElimination,"phi-node-elimination","Eliminate PHI nodes for register allocation", false, false) INITIALIZE_PASS_END(PHIElimination
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
phi node Eliminate PHI nodes for register allocation
MachineInstr * findKill(const MachineBasicBlock *MBB) const
findKill - Find a kill instruction in MBB. Return NULL if none is found.
Representation of each machine instruction.
bool isLandingPad() const
isLandingPad - Returns true if the block is a landing pad.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
VNInfo * createDeadDef(SlotIndex Def, VNInfo::Allocator &VNInfoAllocator)
createDeadDef - Make sure the range has a value defined at Def.
SlotIndex endIndex() const
endNumber - return the maximum point of the range of the whole, exclusive.
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def...
unsigned getReg() const
getReg - Returns the register number.
VNInfo * getNextValue(SlotIndex def, VNInfo::Allocator &VNInfoAllocator)
getNextValue - Create a new value number and return it.
static bool isSourceDefinedByImplicitDef(const MachineInstr *MPhi, const MachineRegisterInfo *MRI)
isSourceDefinedByImplicitDef - Return true if all sources of the phi node are implicit_def's.
virtual const TargetInstrInfo * getInstrInfo() const
iterator_range< def_instr_iterator > def_instructions(unsigned Reg) const
SlotIndex - An opaque wrapper around machine indexes.
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...