25 #define GET_INSTRINFO_CTOR_DTOR
26 #include "NVPTXGenInstrInfo.inc"
29 void NVPTXInstrInfo::anchor() {}
35 unsigned DestReg,
unsigned SrcReg,
bool KillSrc)
const {
43 if (DestRC == &NVPTX::Int32RegsRegClass)
44 BuildMI(MBB, I, DL,
get(NVPTX::IMOV32rr), DestReg)
46 else if (DestRC == &NVPTX::Int1RegsRegClass)
47 BuildMI(MBB, I, DL,
get(NVPTX::IMOV1rr), DestReg)
49 else if (DestRC == &NVPTX::Float32RegsRegClass)
50 BuildMI(MBB, I, DL,
get(NVPTX::FMOV32rr), DestReg)
52 else if (DestRC == &NVPTX::Int16RegsRegClass)
53 BuildMI(MBB, I, DL,
get(NVPTX::IMOV16rr), DestReg)
55 else if (DestRC == &NVPTX::Int64RegsRegClass)
56 BuildMI(MBB, I, DL,
get(NVPTX::IMOV64rr), DestReg)
58 else if (DestRC == &NVPTX::Float64RegsRegClass)
59 BuildMI(MBB, I, DL,
get(NVPTX::FMOV64rr), DestReg)
67 unsigned &DestReg)
const {
73 isMove = (TSFlags == 1);
78 assert(dest.
isReg() &&
"dest of a movrr is not a reg");
79 assert(src.
isReg() &&
"src of a movrr is not a reg");
93 case NVPTX::INT_PTX_SREG_NTID_X:
94 case NVPTX::INT_PTX_SREG_NTID_Y:
95 case NVPTX::INT_PTX_SREG_NTID_Z:
96 case NVPTX::INT_PTX_SREG_TID_X:
97 case NVPTX::INT_PTX_SREG_TID_Y:
98 case NVPTX::INT_PTX_SREG_TID_Z:
99 case NVPTX::INT_PTX_SREG_CTAID_X:
100 case NVPTX::INT_PTX_SREG_CTAID_Y:
101 case NVPTX::INT_PTX_SREG_CTAID_Z:
102 case NVPTX::INT_PTX_SREG_NCTAID_X:
103 case NVPTX::INT_PTX_SREG_NCTAID_Y:
104 case NVPTX::INT_PTX_SREG_NCTAID_Z:
105 case NVPTX::INT_PTX_SREG_WARPSIZE:
111 unsigned &AddrSpace)
const {
115 isLoad = (TSFlags == 1);
122 unsigned &AddrSpace)
const {
123 bool isStore =
false;
126 isStore = (TSFlags == 1);
133 unsigned addrspace = 0;
134 if (MI->
getOpcode() == NVPTX::INT_CUDA_SYNCTHREADS)
173 if (I == MBB.
begin() || !isUnpredicatedTerminator(--I))
180 if (I == MBB.
begin() || !isUnpredicatedTerminator(--I)) {
181 if (LastInst->
getOpcode() == NVPTX::GOTO) {
184 }
else if (LastInst->
getOpcode() == NVPTX::CBranch) {
198 if (SecondLastInst && I != MBB.
begin() && isUnpredicatedTerminator(--I))
202 if (SecondLastInst->
getOpcode() == NVPTX::CBranch &&
212 if (SecondLastInst->
getOpcode() == NVPTX::GOTO &&
227 if (I == MBB.
begin())
230 if (I->getOpcode() != NVPTX::GOTO && I->getOpcode() != NVPTX::CBranch)
234 I->eraseFromParent();
238 if (I == MBB.
begin())
241 if (I->getOpcode() != NVPTX::CBranch)
245 I->eraseFromParent();
253 assert(TBB &&
"InsertBranch must not be told to insert a fallthrough");
254 assert((Cond.
size() == 1 || Cond.
size() == 0) &&
255 "NVPTX branch conditions have two components!");
260 BuildMI(&MBB, DL,
get(NVPTX::GOTO)).addMBB(TBB);
void push_back(const T &Elt)
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
bool isStoreInstr(const MachineInstr &MI, unsigned &AddrSpace) const
MachineBasicBlock * getMBB() const
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag=true)
Reports a serious error, calling any installed error handler.
unsigned getLdStCodeAddrSpace(const MachineInstr &MI) const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
const TargetRegisterClass * getRegClass(unsigned Reg) const
getRegClass - Return the register class of the specified virtual register.
bool isReadSpecialReg(MachineInstr &MI) const
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, DebugLoc DL) const override
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
size_t size() const
size - Get the array size.
unsigned getKillRegState(bool B)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
bundle_iterator< MachineInstr, instr_iterator > iterator
virtual bool CanTailMerge(const MachineInstr *MI) const
unsigned RemoveBranch(MachineBasicBlock &MBB) const override
const MachineOperand & getOperand(unsigned i) const
bool empty() const
empty - Check if the array is empty.
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
AnalyzeBranch - Analyze the branching code at the end of MBB, returning true if it cannot be understo...
MachineOperand class - Representation of each machine instruction operand.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
unsigned getReg() const
getReg - Returns the register number.
virtual bool isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DestReg) const
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
bool isLoadInstr(const MachineInstr &MI, unsigned &AddrSpace) const