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LLVM
3.7.0
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#include <R600InstrInfo.h>
Public Types | |
| enum | BankSwizzle { ALU_VEC_012_SCL_210 = 0, ALU_VEC_021_SCL_122, ALU_VEC_120_SCL_212, ALU_VEC_102_SCL_221, ALU_VEC_201, ALU_VEC_210 } |
Additional Inherited Members | |
Protected Member Functions inherited from llvm::AMDGPUInstrInfo | |
| MachineInstr * | foldMemoryOperandImpl (MachineFunction &MF, MachineInstr *MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex) const override |
| MachineInstr * | foldMemoryOperandImpl (MachineFunction &MF, MachineInstr *MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr *LoadMI) const override |
Protected Attributes inherited from llvm::AMDGPUInstrInfo | |
| const AMDGPUSubtarget & | ST |
Definition at line 32 of file R600InstrInfo.h.
| Enumerator | |
|---|---|
| ALU_VEC_012_SCL_210 | |
| ALU_VEC_021_SCL_122 | |
| ALU_VEC_120_SCL_212 | |
| ALU_VEC_102_SCL_221 | |
| ALU_VEC_201 | |
| ALU_VEC_210 | |
Definition at line 52 of file R600InstrInfo.h.
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explicit |
Definition at line 31 of file R600InstrInfo.cpp.
| void R600InstrInfo::addFlag | ( | MachineInstr * | MI, |
| unsigned | Operand, | ||
| unsigned | Flag | ||
| ) | const |
Add one of the MO_FLAG* flags to the specified Operand.
Definition at line 1397 of file R600InstrInfo.cpp.
References clearFlag(), getFlagOp(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), HAS_NATIVE_OPERANDS, MO_FLAG_LAST, MO_FLAG_MASK, MO_FLAG_NOT_LAST, NUM_MO_FLAGS, and llvm::MachineOperand::setImm().
Referenced by llvm::R600TargetLowering::EmitInstrWithCustomInserter(), and InsertBranch().
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Definition at line 692 of file R600InstrInfo.cpp.
References llvm::MachineBasicBlock::begin(), llvm::MachineOperand::CreateReg(), llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getLastNonDebugInstr(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), I, isBranch(), isJump(), isPredicateSetter(), and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().
| MachineInstrBuilder R600InstrInfo::buildDefaultInstruction | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | I, | ||
| unsigned | Opcode, | ||
| unsigned | DstReg, | ||
| unsigned | Src0Reg, | ||
| unsigned | Src1Reg = 0 |
||
| ) | const |
buildDefaultInstruction - This function returns a MachineInstr with all the instruction modifiers initialized to their default values.
You can use this function to avoid manually specifying each instruction modifier operand when building a new instruction.
Definition at line 1175 of file R600InstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), and llvm::MachineBasicBlock::findDebugLoc().
Referenced by buildMovImm(), buildMovInstr(), buildSlotOfVectorInstruction(), copyPhysReg(), and llvm::R600TargetLowering::EmitInstrWithCustomInserter().
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Build instruction(s) for an indirect register read.
Implements llvm::AMDGPUInstrInfo.
Definition at line 1137 of file R600InstrInfo.cpp.
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Build instruction(s) for an indirect register write.
Implements llvm::AMDGPUInstrInfo.
Definition at line 1105 of file R600InstrInfo.cpp.
| MachineInstr * R600InstrInfo::buildMovImm | ( | MachineBasicBlock & | BB, |
| MachineBasicBlock::iterator | I, | ||
| unsigned | DstReg, | ||
| uint64_t | Imm | ||
| ) | const |
Definition at line 1302 of file R600InstrInfo.cpp.
References buildDefaultInstruction(), and setImmOperand().
Referenced by llvm::R600TargetLowering::EmitInstrWithCustomInserter().
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Build a MOV instruction.
Implements llvm::AMDGPUInstrInfo.
Definition at line 1312 of file R600InstrInfo.cpp.
References buildDefaultInstruction().
| MachineInstr * R600InstrInfo::buildSlotOfVectorInstruction | ( | MachineBasicBlock & | MBB, |
| MachineInstr * | MI, | ||
| unsigned | Slot, | ||
| unsigned | DstReg | ||
| ) | const |
Definition at line 1254 of file R600InstrInfo.cpp.
References buildDefaultInstruction(), llvm::AMDGPUSubtarget::getGeneration(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getOperandIdx(), llvm::MachineOperand::getReg(), getSlotedOps(), llvm::MachineOperand::isImm(), llvm::AArch64CC::MI, Operands, llvm::AMDGPUSubtarget::R700, llvm::MachineOperand::setImm(), setImmOperand(), llvm::MachineOperand::setReg(), llvm::AMDGPUInstrInfo::ST, and llvm::support::endian::write().
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Calculate the "Indirect Address" for the given RegIndex and Channel.
We model indirect addressing using a virtual address space that can be accesed with loads and stores. The "Indirect Address" is the memory address in this virtual address space that maps to the given RegIndex and Channel.
Implements llvm::AMDGPUInstrInfo.
Definition at line 1094 of file R600InstrInfo.cpp.
| bool R600InstrInfo::canBeConsideredALU | ( | const MachineInstr * | MI | ) | const |
Opcode represents an ALU instruction or an instruction that will be lowered in ExpandSpecialInstrs Pass. Definition at line 161 of file R600InstrInfo.cpp.
References llvm::TargetOpcode::COPY, llvm::MachineInstr::getOpcode(), isALUInstr(), isCubeOp(), and isVector().
| void R600InstrInfo::clearFlag | ( | MachineInstr * | MI, |
| unsigned | Operand, | ||
| unsigned | Flag | ||
| ) | const |
Clear the specified flag on the instruction.
Definition at line 1418 of file R600InstrInfo.cpp.
References getFlagOp(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), HAS_NATIVE_OPERANDS, NUM_MO_FLAGS, and llvm::MachineOperand::setImm().
Referenced by addFlag(), and RemoveBranch().
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Definition at line 47 of file R600InstrInfo.cpp.
References buildDefaultInstruction(), contains(), llvm::RegState::Define, llvm::MachineInstr::getOperand(), getOperandIdx(), llvm::AMDGPURegisterInfo::getSubRegFromChannel(), I, llvm::RegState::Implicit, and llvm::MachineOperand::setIsKill().
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Definition at line 653 of file R600InstrInfo.cpp.
References llvm::TargetSubtargetInfo::getInstrItineraryData().
| bool R600InstrInfo::definesAddressRegister | ( | MachineInstr * | MI | ) | const |
Definition at line 238 of file R600InstrInfo.cpp.
References llvm::MachineInstr::findRegisterDefOperandIdx().
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Definition at line 990 of file R600InstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), and isPredicateSetter().
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Definition at line 1050 of file R600InstrInfo.cpp.
References llvm::AMDGPUInstrInfo::expandPostRAPseudo(), llvm::R600RegisterInfo::getHWRegChan(), llvm::R600RegisterInfo::getHWRegIndex(), and llvm::AArch64CC::MI.
| bool R600InstrInfo::FindSwizzleForVectorSlot | ( | const std::vector< std::vector< std::pair< int, unsigned > > > & | IGSrcs, |
| std::vector< R600InstrInfo::BankSwizzle > & | SwzCandidate, | ||
| const std::vector< std::pair< int, unsigned > > & | TransSrcs, | ||
| R600InstrInfo::BankSwizzle | TransSwz | ||
| ) | const |
Enumerate all possible Swizzle sequence to find one that can meet all read port requirements.
Definition at line 511 of file R600InstrInfo.cpp.
References isLegalUpTo(), and NextPossibleSolution().
Referenced by fitsReadPortLimitations().
| bool R600InstrInfo::fitsConstReadLimitations | ( | const std::vector< MachineInstr * > & | MIs | ) | const |
An instruction group can only access 2 channel pair (either [XY] or [ZW]) from KCache bank on R700+.
This function check if MI set in input meet this limitations
Definition at line 622 of file R600InstrInfo.cpp.
References contains(), llvm::R600RegisterInfo::getHWRegChan(), llvm::MachineInstr::getOpcode(), getSrcs(), llvm::SmallSet< T, N, C >::insert(), isALUInstr(), llvm::SmallSet< T, N, C >::size(), and llvm::ArrayRef< T >::size().
Referenced by FoldOperand().
Same but using const index set instead of MI set.
Definition at line 597 of file R600InstrInfo.cpp.
| bool R600InstrInfo::fitsReadPortLimitations | ( | const std::vector< MachineInstr * > & | MIs, |
| const DenseMap< unsigned, unsigned > & | PV, | ||
| std::vector< BankSwizzle > & | BS, | ||
| bool | isLastAluTrans | ||
| ) | const |
Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210 returns true and the first (in lexical order) BankSwizzle affectation starting from the one already provided in the Instruction Group MIs that fits Read Port limitations in BS if available.
Otherwise returns false and undefined content in BS. isLastAluTrans should be set if the last Alu of MIs will be executed on Trans ALU. In this case, ValidTSwizzle returns the BankSwizzle value to apply to the last instruction. PV holds GPR to PV registers in the Instruction Group MIs.
Definition at line 548 of file R600InstrInfo.cpp.
References ALU_VEC_012_SCL_210, ALU_VEC_021_SCL_122, ALU_VEC_102_SCL_221, ALU_VEC_120_SCL_212, FindSwizzleForVectorSlot(), getOperandIdx(), and isConstCompatible().
| MachineOperand & R600InstrInfo::getFlagOp | ( | MachineInstr * | MI, |
| unsigned | SrcIdx = 0, |
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| unsigned | Flag = 0 |
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| ) | const |
| SrcIdx | The register source to set the flag on (e.g src0, src1, src2) |
| Flag | The flag being set. |
Definition at line 1342 of file R600InstrInfo.cpp.
References GET_FLAG_OPERAND_IDX, llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getOperandIdx(), HAS_NATIVE_OPERANDS, llvm::MachineOperand::isImm(), MO_FLAG_ABS, MO_FLAG_CLAMP, MO_FLAG_LAST, MO_FLAG_MASK, MO_FLAG_NEG, MO_FLAG_NOT_LAST, R600_InstFlag::OP3, and llvm::support::endian::write().
Referenced by addFlag(), and clearFlag().
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Implements llvm::AMDGPUInstrInfo.
Definition at line 1101 of file R600InstrInfo.cpp.
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Definition at line 1042 of file R600InstrInfo.cpp.
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Definition at line 208 of file R600InstrInfo.h.
| unsigned R600InstrInfo::getMaxAlusPerClause | ( | ) | const |
Definition at line 1171 of file R600InstrInfo.cpp.
| int R600InstrInfo::getOperandIdx | ( | const MachineInstr & | MI, |
| unsigned | Op | ||
| ) | const |
Get the index of Op in the MachineInstr.
Op. Definition at line 1318 of file R600InstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
Referenced by buildSlotOfVectorInstruction(), copyPhysReg(), llvm::R600TargetLowering::EmitInstrWithCustomInserter(), fitsReadPortLimitations(), FoldOperand(), getFlagOp(), getSelIdx(), getSrcIdx(), getSrcs(), isLDSNoRetInstr(), isLDSRetInstr(), PredicateInstruction(), and setImmOperand().
Get the index of Op for the given Opcode.
Op. Definition at line 1322 of file R600InstrInfo.cpp.
References llvm::AMDGPU::getNamedOperandIdx().
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Definition at line 1038 of file R600InstrInfo.cpp.
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Implements llvm::AMDGPUInstrInfo.
Definition at line 34 of file R600InstrInfo.cpp.
Referenced by llvm::R600TargetLowering::LowerOperation().
Definition at line 269 of file R600InstrInfo.cpp.
References getOperandIdx().
Referenced by FoldOperand().
Definition at line 258 of file R600InstrInfo.cpp.
References getOperandIdx().
| SmallVector< std::pair< MachineOperand *, int64_t >, 3 > R600InstrInfo::getSrcs | ( | MachineInstr * | MI | ) | const |
Definition at line 293 of file R600InstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getOperandIdx(), llvm::MachineOperand::getReg(), and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().
Referenced by fitsConstReadLimitations().
| bool R600InstrInfo::hasFlagOperand | ( | const MachineInstr & | MI | ) | const |
Definition at line 1338 of file R600InstrInfo.cpp.
References GET_FLAG_OPERAND_IDX, and llvm::MachineInstr::getOpcode().
Definition at line 137 of file R600InstrInfo.cpp.
References R600_InstFlag::OP1, R600_InstFlag::OP2, and R600_InstFlag::OP3.
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Definition at line 776 of file R600InstrInfo.cpp.
References addFlag(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::ArrayRef< T >::empty(), llvm::MachineBasicBlock::end(), findFirstPredicateSetterFrom(), FindLastAluClause(), llvm::MachineInstr::getOperand(), llvm::RegState::Kill, MO_FLAG_PUSH, and llvm::MachineOperand::setImm().
Opcode represents an ALU instruction. Definition at line 131 of file R600InstrInfo.cpp.
References R600_InstFlag::ALU_INST.
Referenced by canBeConsideredALU(), fitsConstReadLimitations(), and readsLDSSrcReg().
Definition at line 120 of file R600InstrInfo.cpp.
Referenced by canBeConsideredALU().
Definition at line 197 of file R600InstrInfo.cpp.
References R600_InstFlag::IS_EXPORT.
| bool llvm::R600InstrInfo::isFlagSet | ( | const MachineInstr & | MI, |
| unsigned | Operand, | ||
| unsigned | Flag | ||
| ) | const |
Determine if the specified Flag is set on this Operand.
Definition at line 145 of file R600InstrInfo.cpp.
References R600_InstFlag::LDS_1A, R600_InstFlag::LDS_1A1D, and R600_InstFlag::LDS_1A2D.
Referenced by isLDSNoRetInstr(), and isLDSRetInstr().
Definition at line 153 of file R600InstrInfo.cpp.
References getOperandIdx(), and isLDSInstr().
Definition at line 157 of file R600InstrInfo.cpp.
References getOperandIdx(), and isLDSInstr().
Referenced by llvm::R600TargetLowering::EmitInstrWithCustomInserter().
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MBBI can be moved into a new basic. Definition at line 82 of file R600InstrInfo.cpp.
References I, llvm::R600RegisterInfo::isPhysRegLiveAcrossClauses(), and llvm::TargetRegisterInfo::isVirtualRegister().
| unsigned R600InstrInfo::isLegalUpTo | ( | const std::vector< std::vector< std::pair< int, unsigned > > > & | IGSrcs, |
| const std::vector< R600InstrInfo::BankSwizzle > & | Swz, | ||
| const std::vector< std::pair< int, unsigned > > & | TransSrcs, | ||
| R600InstrInfo::BankSwizzle | TransSwz | ||
| ) | const |
returns how many MIs (whose inputs are represented by IGSrcs) can be packed in the same Instruction Group while meeting read port limitations given a Swz swizzle sequence.
Definition at line 442 of file R600InstrInfo.cpp.
References ALU_VEC_012_SCL_210, ALU_VEC_021_SCL_122, GET_REG_INDEX, getTransSwizzle(), and Swizzle().
Referenced by FindSwizzleForVectorSlot().
Implements llvm::AMDGPUInstrInfo.
Definition at line 93 of file R600InstrInfo.cpp.
Definition at line 108 of file R600InstrInfo.cpp.
References llvm::NVPTXISD::RETURN.
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Definition at line 896 of file R600InstrInfo.cpp.
References llvm::MachineBasicBlock::begin(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::AMDGPUInstrInfo::isPredicable(), and isVector().
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Definition at line 880 of file R600InstrInfo.cpp.
References llvm::MachineInstr::findFirstPredOperandIdx(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::getReg().
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Definition at line 941 of file R600InstrInfo.cpp.
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Definition at line 922 of file R600InstrInfo.cpp.
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Definition at line 930 of file R600InstrInfo.cpp.
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Definition at line 949 of file R600InstrInfo.cpp.
Definition at line 116 of file R600InstrInfo.cpp.
Definition at line 179 of file R600InstrInfo.cpp.
References llvm::AMDGPUSubtarget::hasCaymanISA(), and llvm::AMDGPUInstrInfo::ST.
Referenced by isTransOnly().
| bool R600InstrInfo::isTransOnly | ( | const MachineInstr * | MI | ) | const |
Definition at line 185 of file R600InstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), and isTransOnly().
| bool R600InstrInfo::isTrig | ( | const MachineInstr & | MI | ) | const |
Definition at line 38 of file R600InstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), and R600_InstFlag::TRIG.
| bool R600InstrInfo::isVector | ( | const MachineInstr & | MI | ) | const |
Vector instructions are instructions that must fill all instruction slots within an instruction group.
Definition at line 42 of file R600InstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), and R600_InstFlag::VECTOR.
Referenced by canBeConsideredALU(), and isPredicable().
Definition at line 189 of file R600InstrInfo.cpp.
Referenced by isVectorOnly().
| bool R600InstrInfo::isVectorOnly | ( | const MachineInstr * | MI | ) | const |
Definition at line 193 of file R600InstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), and isVectorOnly().
Definition at line 224 of file R600InstrInfo.cpp.
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Definition at line 1004 of file R600InstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::MachineInstr::findFirstPredOperandIdx(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getOperandIdx(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), getReg(), llvm::RegState::Implicit, llvm::AArch64CC::MI, llvm::MachineOperand::setImm(), and llvm::MachineOperand::setReg().
| bool R600InstrInfo::readsLDSSrcReg | ( | const MachineInstr * | MI | ) | const |
Definition at line 242 of file R600InstrInfo.cpp.
References contains(), llvm::MachineInstr::getOpcode(), I, isALUInstr(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::MachineInstr::operands_begin(), and llvm::MachineInstr::operands_end().
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Definition at line 822 of file R600InstrInfo.cpp.
References llvm::MachineBasicBlock::begin(), clearFlag(), llvm::MachineBasicBlock::end(), findFirstPredicateSetterFrom(), FindLastAluClause(), I, and MO_FLAG_PUSH.
| void R600InstrInfo::reserveIndirectRegisters | ( | BitVector & | Reserved, |
| const MachineFunction & | MF | ||
| ) | const |
Reserve the registers that may be accesed using indirect addressing.
Definition at line 1073 of file R600InstrInfo.cpp.
References llvm::TargetSubtargetInfo::getFrameLowering(), llvm::AMDGPUInstrInfo::getIndirectIndexBegin(), llvm::AMDGPUInstrInfo::getIndirectIndexEnd(), llvm::AMDGPUFrameLowering::getStackWidth(), llvm::MachineFunction::getSubtarget(), and llvm::BitVector::set().
Referenced by llvm::R600RegisterInfo::getReservedRegs().
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Definition at line 956 of file R600InstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineOperand::getReg(), OPCODE_IS_NOT_ZERO, OPCODE_IS_NOT_ZERO_INT, OPCODE_IS_ZERO, OPCODE_IS_ZERO_INT, llvm::MachineOperand::setImm(), and llvm::MachineOperand::setReg().
| void R600InstrInfo::setImmOperand | ( | MachineInstr * | MI, |
| unsigned | Op, | ||
| int64_t | Imm | ||
| ) | const |
Helper function for setting instruction flag values.
Definition at line 1326 of file R600InstrInfo.cpp.
References llvm::MachineInstr::getOperand(), getOperandIdx(), llvm::MachineOperand::isImm(), and llvm::MachineOperand::setImm().
Referenced by buildMovImm(), buildSlotOfVectorInstruction(), and llvm::R600TargetLowering::EmitInstrWithCustomInserter().
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Definition at line 997 of file R600InstrInfo.cpp.
| bool R600InstrInfo::usesAddressRegister | ( | MachineInstr * | MI | ) | const |
Definition at line 234 of file R600InstrInfo.cpp.
References llvm::MachineInstr::findRegisterUseOperandIdx().
Definition at line 212 of file R600InstrInfo.cpp.
References llvm::AMDGPUSubtarget::hasVertexCache(), IS_TEX, IS_VTX, and llvm::AMDGPUInstrInfo::ST.
Referenced by usesTextureCache().
| bool R600InstrInfo::usesTextureCache | ( | const MachineInstr * | MI | ) | const |
Definition at line 216 of file R600InstrInfo.cpp.
References ShaderType::COMPUTE, llvm::MachineFunction::getInfo(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::AMDGPUMachineFunction::getShaderType(), usesTextureCache(), and usesVertexCache().
Definition at line 201 of file R600InstrInfo.cpp.
References llvm::AMDGPUSubtarget::hasVertexCache(), IS_VTX, and llvm::AMDGPUInstrInfo::ST.
Referenced by usesTextureCache(), and usesVertexCache().
| bool R600InstrInfo::usesVertexCache | ( | const MachineInstr * | MI | ) | const |
Definition at line 205 of file R600InstrInfo.cpp.
References ShaderType::COMPUTE, llvm::MachineFunction::getInfo(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::AMDGPUMachineFunction::getShaderType(), and usesVertexCache().
1.8.6