54 struct MachineVerifier {
56 MachineVerifier(
Pass *
pass,
const char *b) :
80 BlockSet FunctionBlocks;
84 RegVector regsDefined, regsDead, regsKilled;
85 RegMaskVector regMasks;
86 RegSet regsLiveInButUnused;
91 void addRegWithSubRegs(RegVector &RV,
unsigned Reg) {
95 RV.push_back(*SubRegs);
120 RegSet vregsRequired;
123 BlockSet Preds, Succs;
125 BBInfo() : reachable(
false) {}
129 bool addPassed(
unsigned Reg) {
132 if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
134 return vregsPassed.insert(Reg).second;
138 bool addPassed(
const RegSet &RS) {
139 bool changed =
false;
140 for (RegSet::const_iterator
I = RS.begin(), E = RS.end();
I != E; ++
I)
148 bool addRequired(
unsigned Reg) {
151 if (regsLiveOut.count(Reg))
153 return vregsRequired.insert(Reg).second;
157 bool addRequired(
const RegSet &RS) {
158 bool changed =
false;
159 for (RegSet::const_iterator
I = RS.begin(), E = RS.end();
I != E; ++
I)
166 bool addRequired(
const RegMap &
RM) {
167 bool changed =
false;
168 for (RegMap::const_iterator
I = RM.begin(), E = RM.end();
I != E; ++
I)
169 if (addRequired(
I->first))
175 bool isLiveOut(
unsigned Reg)
const {
176 return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
183 bool isReserved(
unsigned Reg) {
184 return Reg < regsReserved.size() && regsReserved.test(Reg);
187 bool isAllocatable(
unsigned Reg) {
188 return Reg < TRI->getNumRegs() && MRI->isAllocatable(Reg);
197 void visitMachineFunctionBefore();
201 void visitMachineOperand(
const MachineOperand *MO,
unsigned MONum);
205 void visitMachineFunctionAfter();
210 void report(
const char *msg,
const MachineOperand *MO,
unsigned MONum);
216 const LiveRange &LR,
unsigned Reg,
unsigned LaneMask);
218 const LiveRange &LR,
unsigned Reg,
unsigned LaneMask);
224 void calcRegsPassed();
227 void calcRegsRequired();
228 void verifyLiveVariables();
229 void verifyLiveIntervals();
233 void verifyLiveRangeSegment(
const LiveRange&,
236 void verifyLiveRange(
const LiveRange&,
unsigned,
unsigned LaneMask = 0);
238 void verifyStackFrame();
243 const std::string Banner;
245 MachineVerifierPass(
const std::string &banner =
nullptr)
256 MF.
verify(
this, Banner.c_str());
265 "Verify generated machine code",
false,
false)
268 return new MachineVerifierPass(Banner);
272 MachineVerifier(p, Banner)
273 .runOnMachineFunction(const_cast<MachineFunction&>(*
this));
298 visitMachineFunctionBefore();
301 visitMachineBasicBlockBefore(MFI);
305 bool InBundle =
false;
308 MBBE = MFI->instr_end(); MBBI != MBBE; ++MBBI) {
309 if (MBBI->getParent() != MFI) {
310 report(
"Bad instruction parent pointer", MFI);
311 errs() <<
"Instruction: " << *MBBI;
316 if (InBundle && !MBBI->isBundledWithPred())
317 report(
"Missing BundledPred flag, "
318 "BundledSucc was set on predecessor", MBBI);
319 if (!InBundle && MBBI->isBundledWithPred())
320 report(
"BundledPred flag is set, "
321 "but BundledSucc not set on predecessor", MBBI);
324 if (!MBBI->isInsideBundle()) {
326 visitMachineBundleAfter(CurBundle);
328 visitMachineBundleBefore(CurBundle);
329 }
else if (!CurBundle)
330 report(
"No bundle header", MBBI);
331 visitMachineInstrBefore(MBBI);
332 for (
unsigned I = 0, E = MBBI->getNumOperands();
I != E; ++
I) {
338 report(
"Instruction has operand with wrong parent set", &MI);
341 visitMachineOperand(&Op,
I);
344 visitMachineInstrAfter(MBBI);
347 InBundle = MBBI->isBundledWithSucc();
350 visitMachineBundleAfter(CurBundle);
352 report(
"BundledSucc flag set on last instruction in block", &MFI->back());
353 visitMachineBasicBlockAfter(MFI);
355 visitMachineFunctionAfter();
366 regsLiveInButUnused.clear();
372 void MachineVerifier::report(
const char *msg,
const MachineFunction *MF) {
375 if (!foundErrors++) {
377 errs() <<
"# " << Banner <<
'\n';
380 errs() <<
"*** Bad machine code: " << msg <<
" ***\n"
381 <<
"- function: " << MF->
getName() <<
"\n";
389 <<
" (" << (
const void*)MBB <<
')';
391 errs() <<
" [" << Indexes->getMBBStartIdx(MBB)
392 <<
';' << Indexes->getMBBEndIdx(MBB) <<
')';
396 void MachineVerifier::report(
const char *msg,
const MachineInstr *MI) {
399 errs() <<
"- instruction: ";
400 if (Indexes && Indexes->hasIndex(MI))
401 errs() << Indexes->getInstructionIndex(MI) <<
'\t';
405 void MachineVerifier::report(
const char *msg,
409 errs() <<
"- operand " << MONum <<
": ";
414 void MachineVerifier::report(
const char *msg,
const MachineFunction *MF,
417 errs() <<
"- interval: " << LI <<
'\n';
423 errs() <<
"- interval: " << LI <<
'\n';
430 errs() <<
"- liverange: " << LR <<
'\n';
433 errs() <<
"- lanemask: " <<
format(
"%04X\n", LaneMask);
436 void MachineVerifier::report(
const char *msg,
const MachineFunction *MF,
440 errs() <<
"- liverange: " << LR <<
'\n';
443 errs() <<
"- lanemask: " <<
format(
"%04X\n", LaneMask);
447 BBInfo &MInfo = MBBInfoMap[MBB];
448 if (!MInfo.reachable) {
449 MInfo.reachable =
true;
451 SuE = MBB->
succ_end(); SuI != SuE; ++SuI)
456 void MachineVerifier::visitMachineFunctionBefore() {
458 regsReserved = MRI->getReservedRegs();
461 for (
int Reg = regsReserved.find_first(); Reg>=0;
462 Reg = regsReserved.find_next(Reg)) {
466 regsReserved.set(*SubRegs);
470 markReachable(&MF->
front());
473 FunctionBlocks.clear();
474 for (
const auto &MBB : *MF) {
475 FunctionBlocks.insert(&MBB);
476 BBInfo &MInfo = MBBInfoMap[&MBB];
479 if (MInfo.Preds.size() != MBB.
pred_size())
480 report(
"MBB has duplicate entries in its predecessor list.", &MBB);
483 if (MInfo.Succs.size() != MBB.
succ_size())
484 report(
"MBB has duplicate entries in its successor list.", &MBB);
488 MRI->verifyUseLists();
505 FirstTerminator =
nullptr;
516 report(
"MBB has allocable live-in, but isn't entry or landing-pad.", MBB);
525 if ((*I)->isLandingPad())
527 if (!FunctionBlocks.count(*
I))
528 report(
"MBB has successor that isn't part of the function.", MBB);
529 if (!MBBInfoMap[*
I].Preds.count(MBB)) {
530 report(
"Inconsistent CFG", MBB);
531 errs() <<
"MBB is not in the predecessor list of the successor BB#"
532 << (*I)->getNumber() <<
".\n";
539 if (!FunctionBlocks.count(*
I))
540 report(
"MBB has predecessor that isn't part of the function.", MBB);
541 if (!MBBInfoMap[*
I].Succs.count(MBB)) {
542 report(
"Inconsistent CFG", MBB);
543 errs() <<
"MBB is not in the successor list of the predecessor BB#"
544 << (*I)->getNumber() <<
".\n";
550 if (LandingPadSuccs.
size() > 1 &&
554 report(
"MBB has more than one landing pad successor", MBB);
567 if (MBBI == MF->end()) {
576 report(
"MBB exits via unconditional fall-through but doesn't have "
577 "exactly one CFG successor!", MBB);
579 report(
"MBB exits via unconditional fall-through but its successor "
580 "differs from its CFG successor!", MBB);
584 report(
"MBB exits via unconditional fall-through but ends with a "
585 "barrier instruction!", MBB);
588 report(
"MBB exits via unconditional fall-through but has a condition!",
591 }
else if (TBB && !FBB && Cond.
empty()) {
598 report(
"MBB exits via unconditional branch but doesn't have "
599 "exactly one CFG successor!", MBB);
601 report(
"MBB exits via unconditional branch but the CFG "
602 "successor doesn't match the actual successor!", MBB);
605 report(
"MBB exits via unconditional branch but doesn't contain "
606 "any instructions!", MBB);
608 report(
"MBB exits via unconditional branch but doesn't end with a "
609 "barrier instruction!", MBB);
611 report(
"MBB exits via unconditional branch but the branch isn't a "
612 "terminator instruction!", MBB);
614 }
else if (TBB && !FBB && !Cond.
empty()) {
618 if (MBBI == MF->end()) {
619 report(
"MBB conditionally falls through out of function!", MBB);
623 report(
"MBB exits via conditional branch/fall-through but only has "
624 "one CFG successor!", MBB);
626 report(
"MBB exits via conditional branch/fall-through but the CFG "
627 "successor don't match the actual successor!", MBB);
629 report(
"MBB exits via conditional branch/fall-through but doesn't have "
630 "exactly two CFG successors!", MBB);
632 report(
"MBB exits via conditional branch/fall-through but the CFG "
633 "successors don't match the actual successors!", MBB);
636 report(
"MBB exits via conditional branch/fall-through but doesn't "
637 "contain any instructions!", MBB);
639 report(
"MBB exits via conditional branch/fall-through but ends with a "
640 "barrier instruction!", MBB);
642 report(
"MBB exits via conditional branch/fall-through but the branch "
643 "isn't a terminator instruction!", MBB);
645 }
else if (TBB && FBB) {
651 report(
"MBB exits via conditional branch/branch through but only has "
652 "one CFG successor!", MBB);
654 report(
"MBB exits via conditional branch/branch through but the CFG "
655 "successor don't match the actual successor!", MBB);
657 report(
"MBB exits via conditional branch/branch but doesn't have "
658 "exactly two CFG successors!", MBB);
660 report(
"MBB exits via conditional branch/branch but the CFG "
661 "successors don't match the actual successors!", MBB);
664 report(
"MBB exits via conditional branch/branch but doesn't "
665 "contain any instructions!", MBB);
667 report(
"MBB exits via conditional branch/branch but doesn't end with a "
668 "barrier instruction!", MBB);
670 report(
"MBB exits via conditional branch/branch but the branch "
671 "isn't a terminator instruction!", MBB);
674 report(
"MBB exits via conditinal branch/branch but there's no "
678 report(
"AnalyzeBranch returned invalid data!", MBB);
686 report(
"MBB live-in list contains non-physical register", MBB);
691 regsLive.insert(*SubRegs);
693 regsLiveInButUnused = regsLive;
696 assert(MFI &&
"Function has no frame info");
701 regsLive.insert(*SubRegs);
708 lastIndex = Indexes->getMBBStartIdx(MBB);
713 void MachineVerifier::visitMachineBundleBefore(
const MachineInstr *MI) {
714 if (Indexes && Indexes->hasIndex(MI)) {
715 SlotIndex idx = Indexes->getInstructionIndex(MI);
716 if (!(idx > lastIndex)) {
717 report(
"Instruction index out of order", MI);
718 errs() <<
"Last instruction was at " << lastIndex <<
'\n';
727 if (!FirstTerminator)
728 FirstTerminator =
MI;
729 }
else if (FirstTerminator) {
730 report(
"Non-terminator instruction after the first terminator", MI);
731 errs() <<
"First terminator was:\t" << *FirstTerminator;
737 void MachineVerifier::verifyInlineAsm(
const MachineInstr *MI) {
740 report(
"Too few operands on inline asm", MI);
744 report(
"Asm string must be an external symbol", MI);
746 report(
"Asm flags must be an immediate", MI);
750 report(
"Unknown asm flags", &MI->
getOperand(1), 1);
756 for (
unsigned e = MI->
getNumOperands(); OpNo < e; OpNo += NumOps) {
765 report(
"Missing operands in last group", MI);
775 report(
"Expected implicit register after groups", &MO, OpNo);
779 void MachineVerifier::visitMachineInstrBefore(
const MachineInstr *MI) {
782 report(
"Too few operands", MI);
794 if ((*I)->isLoad() && !MI->
mayLoad())
795 report(
"Missing mayLoad flag", MI);
796 if ((*I)->isStore() && !MI->
mayStore())
797 report(
"Missing mayStore flag", MI);
803 bool mapped = !LiveInts->isNotInMIMap(MI);
806 report(
"Debug instruction has a slot index", MI);
809 report(
"Instruction inside bundle has a slot index", MI);
812 report(
"Missing slot index", MI);
817 if (!
TII->verifyInstruction(MI, ErrorInfo))
818 report(ErrorInfo.
data(),
MI);
822 MachineVerifier::visitMachineOperand(
const MachineOperand *MO,
unsigned MONum) {
830 report(
"Explicit definition must be a register", MO, MONum);
832 report(
"Explicit definition marked as use", MO, MONum);
834 report(
"Explicit definition marked as implicit", MO, MONum);
842 report(
"Explicit operand marked as def", MO, MONum);
844 report(
"Explicit operand marked as implicit", MO, MONum);
850 report(
"Tied use must be a register", MO, MONum);
852 report(
"Operand should be tied", MO, MONum);
854 report(
"Tied def doesn't match MCInstrDesc", MO, MONum);
856 report(
"Explicit operand should not be tied", MO, MONum);
860 report(
"Extra explicit operand on non-variadic instruction", MO, MONum);
865 const unsigned Reg = MO->
getReg();
869 checkLiveness(MO, MONum);
875 if (!OtherMO.
isReg())
876 report(
"Must be tied to a register", MO, MONum);
878 report(
"Missing tie flags on tied operand", MO, MONum);
880 report(
"Inconsistent tie links", MO, MONum);
884 report(
"Explicit def tied to explicit use without tie constraint",
888 report(
"Explicit def should be tied to implicit use", MO, MONum);
895 if (!MRI->isSSA() && MO->
isUse() &&
898 report(
"Two-address instruction operands must be identical", MO, MONum);
906 report(
"Illegal subregister index for physical register", MO, MONum);
910 TII->getRegClass(MCID, MONum, TRI, *MF)) {
911 if (!DRC->contains(Reg)) {
912 report(
"Illegal physical register for instruction", MO, MONum);
913 errs() << TRI->getName(Reg) <<
" is not a "
914 << TRI->getRegClassName(DRC) <<
" register.\n";
922 TRI->getSubClassWithSubReg(RC, SubIdx);
924 report(
"Invalid subregister index for virtual register", MO, MONum);
925 errs() <<
"Register class " << TRI->getRegClassName(RC)
926 <<
" does not support subreg index " << SubIdx <<
"\n";
930 report(
"Invalid register class for subregister index", MO, MONum);
931 errs() <<
"Register class " << TRI->getRegClassName(RC)
932 <<
" does not fully support subreg index " << SubIdx <<
"\n";
937 TII->getRegClass(MCID, MONum, TRI, *MF)) {
940 TRI->getLargestLegalSuperClass(RC, *MF);
942 report(
"No largest legal super class exists.", MO, MONum);
945 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
947 report(
"No matching super-reg register class.", MO, MONum);
952 report(
"Illegal virtual register for instruction", MO, MONum);
953 errs() <<
"Expected a " << TRI->getRegClassName(DRC)
954 <<
" register, but got a " << TRI->getRegClassName(RC)
969 report(
"PHI operand is not in the CFG", MO, MONum);
973 if (LiveStks && LiveStks->hasInterval(MO->
getIndex()) &&
974 LiveInts && !LiveInts->isNotInMIMap(MI)) {
976 SlotIndex Idx = LiveInts->getInstructionIndex(MI);
978 report(
"Instruction loads from dead spill slot", MO, MONum);
979 errs() <<
"Live stack: " << LI <<
'\n';
982 report(
"Instruction stores to dead spill slot", MO, MONum);
983 errs() <<
"Live stack: " << LI <<
'\n';
993 void MachineVerifier::checkLiveness(
const MachineOperand *MO,
unsigned MONum) {
995 const unsigned Reg = MO->
getReg();
999 regsLiveInButUnused.erase(Reg);
1002 addRegWithSubRegs(regsKilled, Reg);
1009 report(
"Kill missing from LiveVariables", MO, MONum);
1013 if (LiveInts && !LiveInts->isNotInMIMap(MI)) {
1014 SlotIndex UseIdx = LiveInts->getInstructionIndex(MI);
1018 if (
const LiveRange *LR = LiveInts->getCachedRegUnit(*Units)) {
1021 report(
"No live segment at use", MO, MONum);
1023 <<
' ' << *LR <<
'\n';
1026 report(
"Live range continues after kill flag", MO, MONum);
1034 if (LiveInts->hasInterval(Reg)) {
1039 report(
"No live segment at use", MO, MONum);
1040 errs() << UseIdx <<
" is not live in " << LI <<
'\n';
1045 report(
"Live range continues after kill flag", MO, MONum);
1046 errs() <<
"Live range: " << LI <<
'\n';
1049 report(
"Virtual register has no live interval", MO, MONum);
1055 if (!regsLive.count(Reg)) {
1058 bool Bad = !isReserved(Reg);
1063 if (regsLive.count(*SubRegs)) {
1077 if (!MOP.isImplicit())
1081 if (*SubRegs == Reg) {
1089 report(
"Using an undefined physical register", MO, MONum);
1090 }
else if (MRI->def_empty(Reg)) {
1091 report(
"Reading virtual register without a def", MO, MONum);
1093 BBInfo &MInfo = MBBInfoMap[MI->
getParent()];
1097 if (MInfo.regsKilled.count(Reg))
1098 report(
"Using a killed virtual register", MO, MONum);
1099 else if (!MI->
isPHI())
1100 MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
1109 addRegWithSubRegs(regsDead, Reg);
1111 addRegWithSubRegs(regsDefined, Reg);
1115 std::next(MRI->def_begin(Reg)) != MRI->def_end())
1116 report(
"Multiple virtual register defs in SSA form", MO, MONum);
1120 !LiveInts->isNotInMIMap(MI)) {
1121 SlotIndex DefIdx = LiveInts->getInstructionIndex(MI);
1123 if (LiveInts->hasInterval(Reg)) {
1126 assert(VNI &&
"NULL valno is not allowed");
1127 if (VNI->def != DefIdx) {
1128 report(
"Inconsistent valno->def", MO, MONum);
1129 errs() <<
"Valno " << VNI->id <<
" is not defined at "
1130 << DefIdx <<
" in " << LI <<
'\n';
1133 report(
"No live segment at def", MO, MONum);
1134 errs() << DefIdx <<
" is not live in " << LI <<
'\n';
1140 report(
"Live range continues after dead def flag", MO, MONum);
1141 errs() <<
"Live range: " << LI <<
'\n';
1145 report(
"Virtual register has no Live interval", MO, MONum);
1151 void MachineVerifier::visitMachineInstrAfter(
const MachineInstr *MI) {
1158 void MachineVerifier::visitMachineBundleAfter(
const MachineInstr *MI) {
1159 BBInfo &MInfo = MBBInfoMap[MI->
getParent()];
1160 set_union(MInfo.regsKilled, regsKilled);
1161 set_subtract(regsLive, regsKilled); regsKilled.clear();
1163 while (!regMasks.empty()) {
1164 const uint32_t *Mask = regMasks.pop_back_val();
1165 for (RegSet::iterator
I = regsLive.begin(), E = regsLive.end();
I != E; ++
I)
1168 regsDead.push_back(*
I);
1171 set_union(regsLive, regsDefined); regsDefined.clear();
1176 MBBInfoMap[MBB].regsLiveOut = regsLive;
1180 SlotIndex stop = Indexes->getMBBEndIdx(MBB);
1181 if (!(stop > lastIndex)) {
1182 report(
"Block ends before last instruction index", MBB);
1183 errs() <<
"Block ends at " << stop
1184 <<
" last instruction was at " << lastIndex <<
'\n';
1193 void MachineVerifier::calcRegsPassed() {
1197 for (
const auto &MBB : *MF) {
1198 BBInfo &MInfo = MBBInfoMap[&MBB];
1199 if (!MInfo.reachable)
1202 SuE = MBB.
succ_end(); SuI != SuE; ++SuI) {
1203 BBInfo &SInfo = MBBInfoMap[*SuI];
1204 if (SInfo.addPassed(MInfo.regsLiveOut))
1211 while (!todo.
empty()) {
1214 BBInfo &MInfo = MBBInfoMap[MBB];
1216 SuE = MBB->
succ_end(); SuI != SuE; ++SuI) {
1219 BBInfo &SInfo = MBBInfoMap[*SuI];
1220 if (SInfo.addPassed(MInfo.vregsPassed))
1229 void MachineVerifier::calcRegsRequired() {
1232 for (
const auto &MBB : *MF) {
1233 BBInfo &MInfo = MBBInfoMap[&MBB];
1235 PrE = MBB.
pred_end(); PrI != PrE; ++PrI) {
1236 BBInfo &PInfo = MBBInfoMap[*PrI];
1237 if (PInfo.addRequired(MInfo.vregsLiveIn))
1244 while (!todo.
empty()) {
1247 BBInfo &MInfo = MBBInfoMap[MBB];
1249 PrE = MBB->
pred_end(); PrI != PrE; ++PrI) {
1252 BBInfo &SInfo = MBBInfoMap[*PrI];
1253 if (SInfo.addRequired(MInfo.vregsRequired))
1263 for (
const auto &BBI : *MBB) {
1268 for (
unsigned i = 1, e = BBI.getNumOperands(); i != e; i += 2) {
1269 unsigned Reg = BBI.getOperand(i).getReg();
1274 BBInfo &PrInfo = MBBInfoMap[Pre];
1275 if (PrInfo.reachable && !PrInfo.isLiveOut(Reg))
1276 report(
"PHI operand is not live-out from predecessor",
1277 &BBI.getOperand(i), i);
1282 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
1283 if (!seen.
count(*PrI)) {
1284 report(
"Missing PHI operand", &BBI);
1285 errs() <<
"BB#" << (*PrI)->getNumber()
1286 <<
" is a predecessor according to the CFG.\n";
1292 void MachineVerifier::visitMachineFunctionAfter() {
1295 for (
const auto &MBB : *MF) {
1296 BBInfo &MInfo = MBBInfoMap[&MBB];
1299 if (!MInfo.reachable)
1309 for (
const auto &MBB : *MF) {
1310 BBInfo &MInfo = MBBInfoMap[&MBB];
1311 for (RegSet::iterator
1312 I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end();
I != E;
1314 if (MInfo.regsKilled.count(*
I)) {
1315 report(
"Virtual register killed in block, but needed live out.", &MBB);
1317 <<
" is used after the block.\n";
1322 BBInfo &MInfo = MBBInfoMap[&MF->front()];
1323 for (RegSet::iterator
1324 I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end();
I != E;
1326 report(
"Virtual register def doesn't dominate all uses.",
1327 MRI->getVRegDef(*
I));
1331 verifyLiveVariables();
1333 verifyLiveIntervals();
1336 void MachineVerifier::verifyLiveVariables() {
1337 assert(LiveVars &&
"Don't call verifyLiveVariables without LiveVars");
1338 for (
unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
1341 for (
const auto &MBB : *MF) {
1342 BBInfo &MInfo = MBBInfoMap[&MBB];
1345 if (MInfo.vregsRequired.count(Reg)) {
1347 report(
"LiveVariables: Block missing from AliveBlocks", &MBB);
1349 <<
" must be live through the block.\n";
1353 report(
"LiveVariables: Block should not be in AliveBlocks", &MBB);
1355 <<
" is not needed live through the block.\n";
1362 void MachineVerifier::verifyLiveIntervals() {
1363 assert(LiveInts &&
"Don't call verifyLiveIntervals without LiveInts");
1364 for (
unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
1368 if (MRI->reg_nodbg_empty(Reg))
1371 if (!LiveInts->hasInterval(Reg)) {
1372 report(
"Missing live interval for virtual register", MF);
1373 errs() <<
PrintReg(Reg, TRI) <<
" still has defs or uses\n";
1378 assert(Reg == LI.
reg &&
"Invalid reg to interval mapping");
1379 verifyLiveInterval(LI);
1383 for (
unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
1384 if (
const LiveRange *LR = LiveInts->getCachedRegUnit(i))
1385 verifyLiveRange(*LR, i);
1388 void MachineVerifier::verifyLiveRangeValue(
const LiveRange &LR,
1389 const VNInfo *VNI,
unsigned Reg,
1390 unsigned LaneMask) {
1397 report(
"Valno not live at def and not marked unused", MF, LR, Reg,
1399 errs() <<
"Valno #" << VNI->
id <<
'\n';
1403 if (DefVNI != VNI) {
1404 report(
"Live segment at def has different valno", MF, LR, Reg, LaneMask);
1405 errs() <<
"Valno #" << VNI->
id <<
" is defined at " << VNI->
def
1406 <<
" where valno #" << DefVNI->
id <<
" is live\n";
1412 report(
"Invalid definition index", MF, LR, Reg, LaneMask);
1413 errs() <<
"Valno #" << VNI->
id <<
" is defined at " << VNI->
def
1414 <<
" in " << LR <<
'\n';
1419 if (VNI->
def != LiveInts->getMBBStartIdx(MBB)) {
1420 report(
"PHIDef value is not defined at MBB start", MBB, LR, Reg,
1422 errs() <<
"Valno #" << VNI->
id <<
" is defined at " << VNI->
def
1423 <<
", not at the beginning of BB#" << MBB->
getNumber() <<
'\n';
1431 report(
"No instruction at def index", MBB, LR, Reg, LaneMask);
1432 errs() <<
"Valno #" << VNI->
id <<
" is defined at " << VNI->
def <<
'\n';
1437 bool hasDef =
false;
1438 bool isEarlyClobber =
false;
1440 if (!MOI->isReg() || !MOI->isDef())
1443 if (MOI->getReg() !=
Reg)
1447 !TRI->hasRegUnit(MOI->getReg(),
Reg))
1450 if (LaneMask != 0 &&
1451 (TRI->getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask) == 0)
1454 if (MOI->isEarlyClobber())
1455 isEarlyClobber =
true;
1459 report(
"Defining instruction does not modify register", MI);
1460 errs() <<
"Valno #" << VNI->
id <<
" in " << LR <<
'\n';
1465 if (isEarlyClobber) {
1467 report(
"Early clobber def must be at an early-clobber slot", MBB, LR,
1469 errs() <<
"Valno #" << VNI->
id <<
" is defined at " << VNI->
def <<
'\n';
1472 report(
"Non-PHI, non-early clobber def must be at a register slot",
1473 MBB, LR, Reg, LaneMask);
1474 errs() <<
"Valno #" << VNI->
id <<
" is defined at " << VNI->
def <<
'\n';
1479 void MachineVerifier::verifyLiveRangeSegment(
const LiveRange &LR,
1481 unsigned Reg,
unsigned LaneMask) {
1484 assert(VNI &&
"Live segment has no valno");
1487 report(
"Foreign valno in live segment", MF, LR, Reg, LaneMask);
1488 errs() << S <<
" has a bad valno\n";
1492 report(
"Live segment valno is marked unused", MF, LR, Reg, LaneMask);
1493 errs() << S <<
'\n';
1498 report(
"Bad start of live segment, no basic block", MF, LR, Reg, LaneMask);
1499 errs() << S <<
'\n';
1502 SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB);
1504 report(
"Live segment must begin at MBB entry or valno def", MBB, LR, Reg,
1506 errs() << S <<
'\n';
1512 report(
"Bad end of live segment, no basic block", MF, LR, Reg, LaneMask);
1513 errs() << S <<
'\n';
1518 if (S.
end == LiveInts->getMBBEndIdx(EndMBB))
1530 report(
"Live segment doesn't end at a valid instruction", EndMBB, LR, Reg,
1532 errs() << S <<
'\n';
1538 report(
"Live segment ends at B slot of an instruction", EndMBB, LR, Reg,
1540 errs() << S <<
'\n';
1547 report(
"Live segment ending at dead slot spans instructions", EndMBB, LR,
1549 errs() << S <<
'\n';
1556 if (I+1 == LR.
end() || (I+1)->start != S.
end) {
1557 report(
"Live segment ending at early clobber slot must be "
1558 "redefined by an EC def in the same instruction", EndMBB, LR, Reg,
1560 errs() << S <<
'\n';
1569 bool hasRead =
false;
1570 bool hasSubRegDef =
false;
1572 if (!MOI->isReg() || MOI->getReg() !=
Reg)
1574 if (LaneMask != 0 &&
1575 (LaneMask & TRI->getSubRegIndexLaneMask(MOI->getSubReg())) == 0)
1577 if (MOI->isDef() && MOI->getSubReg() != 0)
1578 hasSubRegDef =
true;
1579 if (MOI->readsReg())
1586 if (!MRI->shouldTrackSubRegLiveness(Reg) || LaneMask != 0 ||
1588 report(
"Instruction ending live segment doesn't read the register",
1590 errs() << S <<
" in " << LR <<
'\n';
1607 assert(LiveInts->isLiveInToMBB(LR, MFI));
1610 MFI->isLandingPad()) {
1611 if (&*MFI == EndMBB)
1619 VNI->
def == LiveInts->getMBBStartIdx(MFI);
1623 PE = MFI->pred_end(); PI != PE; ++PI) {
1624 SlotIndex PEnd = LiveInts->getMBBEndIdx(*PI);
1629 report(
"Register not marked live out of predecessor", *PI, LR, Reg,
1631 errs() <<
"Valno #" << VNI->
id <<
" live into BB#" << MFI->getNumber()
1632 <<
'@' << LiveInts->getMBBStartIdx(MFI) <<
", not live before "
1638 if (!IsPHI && PVNI != VNI) {
1639 report(
"Different value live out of predecessor", *PI, LR, Reg,
1641 errs() <<
"Valno #" << PVNI->
id <<
" live out of BB#"
1642 << (*PI)->getNumber() <<
'@' << PEnd
1643 <<
"\nValno #" << VNI->
id <<
" live into BB#" << MFI->getNumber()
1644 <<
'@' << LiveInts->getMBBStartIdx(MFI) <<
'\n';
1647 if (&*MFI == EndMBB)
1653 void MachineVerifier::verifyLiveRange(
const LiveRange &LR,
unsigned Reg,
1654 unsigned LaneMask) {
1656 verifyLiveRangeValue(LR, VNI, Reg, LaneMask);
1659 verifyLiveRangeSegment(LR, I, Reg, LaneMask);
1662 void MachineVerifier::verifyLiveInterval(
const LiveInterval &LI) {
1663 unsigned Reg = LI.
reg;
1665 verifyLiveRange(LI, Reg);
1668 unsigned MaxMask = MRI->getMaxLaneMaskForVReg(Reg);
1670 if ((Mask & SR.LaneMask) != 0)
1671 report(
"Lane masks of sub ranges overlap in live interval", MF, LI);
1672 if ((SR.LaneMask & ~MaxMask) != 0)
1673 report(
"Subrange lanemask is invalid", MF, LI);
1674 Mask |= SR.LaneMask;
1675 verifyLiveRange(SR, LI.
reg, SR.LaneMask);
1677 report(
"A Subrange is not covered by the main range", MF, LI);
1682 unsigned NumComp = ConEQ.Classify(&LI);
1684 report(
"Multiple connected components in live interval", MF, LI);
1685 for (
unsigned comp = 0; comp != NumComp; ++comp) {
1686 errs() << comp <<
": valnos";
1689 if (comp == ConEQ.getEqClass(*I))
1690 errs() <<
' ' << (*I)->id;
1701 struct StackStateOfBB {
1702 StackStateOfBB() : EntryValue(0), ExitValue(0), EntryIsSetup(
false),
1703 ExitIsSetup(
false) { }
1704 StackStateOfBB(
int EntryVal,
int ExitVal,
bool EntrySetup,
bool ExitSetup) :
1705 EntryValue(EntryVal), ExitValue(ExitVal), EntryIsSetup(EntrySetup),
1706 ExitIsSetup(ExitSetup) { }
1718 void MachineVerifier::verifyStackFrame() {
1719 unsigned FrameSetupOpcode =
TII->getCallFrameSetupOpcode();
1720 unsigned FrameDestroyOpcode =
TII->getCallFrameDestroyOpcode();
1723 SPState.
resize(MF->getNumBlockIDs());
1730 DFI != DFE; ++DFI) {
1733 StackStateOfBB BBState;
1735 if (DFI.getPathLength() >= 2) {
1737 assert(Reachable.
count(StackPred) &&
1738 "DFS stack predecessor is already visited.\n");
1739 BBState.EntryValue = SPState[StackPred->
getNumber()].ExitValue;
1740 BBState.EntryIsSetup = SPState[StackPred->
getNumber()].ExitIsSetup;
1741 BBState.ExitValue = BBState.EntryValue;
1742 BBState.ExitIsSetup = BBState.EntryIsSetup;
1746 for (
const auto &I : *MBB) {
1747 if (I.getOpcode() == FrameSetupOpcode) {
1749 int Size = I.getOperand(0).getImm();
1751 "Value should be non-negative in FrameSetup and FrameDestroy.\n");
1753 if (BBState.ExitIsSetup)
1754 report(
"FrameSetup is after another FrameSetup", &I);
1755 BBState.ExitValue -= Size;
1756 BBState.ExitIsSetup =
true;
1759 if (I.getOpcode() == FrameDestroyOpcode) {
1761 int Size = I.getOperand(0).getImm();
1763 "Value should be non-negative in FrameSetup and FrameDestroy.\n");
1765 if (!BBState.ExitIsSetup)
1766 report(
"FrameDestroy is not after a FrameSetup", &I);
1767 int AbsSPAdj = BBState.ExitValue < 0 ? -BBState.ExitValue :
1769 if (BBState.ExitIsSetup && AbsSPAdj != Size) {
1770 report(
"FrameDestroy <n> is after FrameSetup <m>", &I);
1771 errs() <<
"FrameDestroy <" << Size <<
"> is after FrameSetup <"
1772 << AbsSPAdj <<
">.\n";
1774 BBState.ExitValue += Size;
1775 BBState.ExitIsSetup =
false;
1778 SPState[MBB->getNumber()] = BBState;
1783 E = MBB->pred_end(); I != E; ++
I) {
1784 if (Reachable.
count(*I) &&
1785 (SPState[(*I)->getNumber()].ExitValue != BBState.EntryValue ||
1786 SPState[(*I)->getNumber()].ExitIsSetup != BBState.EntryIsSetup)) {
1787 report(
"The exit stack state of a predecessor is inconsistent.", MBB);
1788 errs() <<
"Predecessor BB#" << (*I)->getNumber() <<
" has exit state ("
1789 << SPState[(*I)->getNumber()].ExitValue <<
", "
1790 << SPState[(*I)->getNumber()].ExitIsSetup
1791 <<
"), while BB#" << MBB->getNumber() <<
" has entry state ("
1792 << BBState.EntryValue <<
", " << BBState.EntryIsSetup <<
").\n";
1799 E = MBB->succ_end(); I != E; ++
I) {
1800 if (Reachable.
count(*I) &&
1801 (SPState[(*I)->getNumber()].EntryValue != BBState.ExitValue ||
1802 SPState[(*I)->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) {
1803 report(
"The entry stack state of a successor is inconsistent.", MBB);
1804 errs() <<
"Successor BB#" << (*I)->getNumber() <<
" has entry state ("
1805 << SPState[(*I)->getNumber()].EntryValue <<
", "
1806 << SPState[(*I)->getNumber()].EntryIsSetup
1807 <<
"), while BB#" << MBB->getNumber() <<
" has exit state ("
1808 << BBState.ExitValue <<
", " << BBState.ExitIsSetup <<
").\n";
1813 if (!MBB->empty() && MBB->back().isReturn()) {
1814 if (BBState.ExitIsSetup)
1815 report(
"A return block ends with a FrameSetup.", MBB);
1816 if (BBState.ExitValue)
1817 report(
"A return block ends with a nonzero stack adjustment.", MBB);
Pass interface - Implemented by all 'passes'.
bool isInsideBundle() const
Return true if MI is in a bundle (but not the first MI in a bundle).
unsigned succ_size() const
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
SlotIndex def
The index of the defining instruction.
BitVector getPristineRegs(const MachineFunction &MF) const
Return a set of physical registers that are pristine.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
iterator_range< mop_iterator > uses()
MachineBasicBlock * getMBB() const
static unsigned index2VirtReg(unsigned Index)
index2VirtReg - Convert a 0-based index to a virtual register number.
int getNumber() const
getNumber - MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a M...
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
DenseSet - This implements a dense probed hash-table based set.
int find_next(unsigned Prev) const
find_next - Returns the index of the next set bit following the "Prev" bit.
DWARF-like instruction based exceptions.
std::vector< unsigned >::const_iterator livein_iterator
LiveInterval - This class represents the liveness of a register, or stack slot.
Describe properties that are true of each instruction in the target description file.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
static bool matchPair(MachineBasicBlock::const_succ_iterator i, const MachineBasicBlock *a, const MachineBasicBlock *b)
size_type count(PtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
void verify(Pass *p=nullptr, const char *Banner=nullptr) const
verify - Run the current MachineFunction through the machine code verifier, useful for debugger use...
PrintRegUnit - Helper class for printing register units on a raw_ostream.
bool isKill() const
Return true if the live-in value is killed by this instruction.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
A live range for subregisters.
MachineBasicBlock reference.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
hasSuperClassEq - Returns true if RC is a super-class of or equal to this class.
This represents a simple continuous liveness interval for a value.
VarInfo - This represents the regions where a virtual register is live in the program.
bool isRegister() const
isRegister - Returns true if this is a normal register use/def slot.
VNInfo - Value Number Information.
bool isMetadata() const
isMetadata - Tests if this is a MO_Metadata operand.
unsigned getNumValNums() const
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
bool isEarlyClobber() const
isEarlyClobber - Returns true if this is an early-clobber slot.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag=true)
Reports a serious error, calling any installed error handler.
This class represents the liveness of a register, stack slot, etc.
void initializeMachineVerifierPassPass(PassRegistry &)
Mask of preserved registers.
FunctionPass * createMachineVerifierPass(const std::string &Banner)
createMachineVerifierPass - This pass verifies cenerated machine code instructions for correctness...
livein_iterator livein_begin() const
MachineMemOperand - A description of a memory reference used in the backend.
void clear()
clear - Clear all bits.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
const HexagonInstrInfo * TII
bool isPredicated(const MachineInstr *MI) const override
AnalysisType * getAnalysisIfAvailable() const
getAnalysisIfAvailable<AnalysisType>() - Subclasses use this function to get analysis information tha...
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
iterator_range< subrange_iterator > subranges()
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Result of a LiveRange query.
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool isBlock() const
isBlock - Returns true if this is a block boundary slot.
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
SparseBitVector AliveBlocks
AliveBlocks - Set of blocks in which this value is alive completely through.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
bool isUnused() const
Returns true if this value is unused.
PrintReg - Helper class for printing registers on a raw_ostream.
const MachineBasicBlock & front() const
bool isDead() const
isDead - Returns true if this is a dead def kill slot.
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
void print(raw_ostream &OS, SlotIndexes *=nullptr) const
print - Print out the MachineFunction in a format suitable for debugging to the specified stream...
VNInfoList::const_iterator const_vni_iterator
INITIALIZE_PASS(MachineVerifierPass,"machineverifier","Verify generated machine code", false, false) FunctionPass *llvm
const BasicBlock * getBasicBlock() const
getBasicBlock - Return the LLVM basic block that this instance corresponded to originally.
SlotIndex getPrevSlot() const
Returns the previous slot in the index list.
const MachineBasicBlock * getParent() const
format_object< Ts...> format(const char *Fmt, const Ts &...Vals)
These are helper functions used to produce formatted output.
TargetInstrInfo - Interface to description of machine instruction set.
bool isDebugValue() const
This class is intended to be used as a base class for asm properties and features specific to the tar...
mmo_iterator memoperands_end() const
bool isDeadDef() const
Return true if this instruction has a dead def.
bool isEarlyClobber() const
unsigned findTiedOperandIdx(unsigned OpIdx) const
Given the index of a tied register operand, find the operand it is tied to.
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr) const
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
LLVM Basic Block Representation.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
void print(raw_ostream &OS, bool SkipOpers=false) const
df_ext_iterator< T, SetTy > df_ext_end(const T &G, SetTy &S)
bool isOptionalDef() const
Set if this operand is a optional def.
livein_iterator livein_end() const
const MachineOperand & getOperand(unsigned i) const
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag...
Two Address instruction pass
Represent the analysis usage information of a pass.
df_ext_iterator< T, SetTy > df_ext_begin(const T &G, SetTy &S)
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
bool isVariadic(QueryType Type=IgnoreBundle) const
Return true if this instruction can have a variable number of operands.
FunctionPass class - This class is used to implement most global optimizations.
ExceptionHandling getExceptionHandlingType() const
succ_iterator succ_begin()
unsigned getSubReg() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
pred_iterator pred_begin()
MCSubRegIterator enumerates all sub-registers of Reg.
bool liveAt(SlotIndex index) const
bool isPHIDef() const
Returns true if this value is defined by a PHI instruction (or was, PHI instructions may have been el...
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
std::vector< MachineBasicBlock * >::const_iterator const_pred_iterator
std::vector< MachineInstr * > Kills
Kills - List of MachineInstruction's which are the last use of this virtual register (kill it) in the...
unsigned id
The ID number of this value.
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
bool erase(PtrType Ptr)
erase - If the set contains the specified pointer, remove it and return true, otherwise return false...
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
ConnectedVNInfoEqClasses - Helper class that can divide VNInfos in a LiveInterval into equivalence cl...
MachineOperand class - Representation of each machine instruction operand.
bool isSuccessor(const MachineBasicBlock *MBB) const
isSuccessor - Return true if the specified MBB is a successor of this block.
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
StringRef getName() const
getName - Return the name of the corresponding LLVM basic block, or "(null)".
void setPreservesAll()
Set by analyses that do not transform their input at all.
VNInfo * getValNumInfo(unsigned ValNo)
getValNumInfo - Returns pointer to the specified val#.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
void set_subtract(S1Ty &S1, const S2Ty &S2)
set_subtract(A, B) - Compute A := A - B
Representation of each machine instruction.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
static bool isPhysicalRegister(unsigned Reg)
isPhysicalRegister - Return true if the specified register number is in the physical register namespa...
bool isLandingPad() const
isLandingPad - Returns true if the block is a landing pad.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
TerminatorInst * getTerminator()
Returns the terminator instruction if the block is well formed or null if the block is not well forme...
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Abstract Stack Frame Index.
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def...
unsigned getReg() const
getReg - Returns the register number.
bool isValid() const
isValid - Returns true until all the operands have been visited.
std::vector< MachineBasicBlock * >::const_iterator const_succ_iterator
virtual const TargetInstrInfo * getInstrInfo() const
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
const MCOperandInfo * OpInfo
Primary interface to the complete machine description for the target machine.
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
StringRef - Represent a constant reference to a string, i.e.
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register. ...
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
VNInfo * valueIn() const
Return the value that is live-in to the instruction.
This holds information about one operand of a machine instruction, indicating the register class for ...
SlotIndex - An opaque wrapper around machine indexes.
bool covers(const LiveRange &Other) const
Returns true if all segments of the Other live range are completely covered by this live range...
bool set_union(S1Ty &S1, const S2Ty &S2)
set_union(A, B) - Compute A := A u B, return whether A changed.
unsigned pred_size() const
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
VNInfo * getVNInfoBefore(SlotIndex Idx) const
getVNInfoBefore - Return the VNInfo that is live up to but not necessarilly including Idx...
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.