15 #ifndef LLVM_LIB_TARGET_ARM_ARMCALLINGCONV_H
16 #define LLVM_LIB_TARGET_ARM_ARMCALLINGCONV_H
62 if (!
f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State,
true))
75 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 };
76 static const MCPhysReg ShadowRegList[] = { ARM::R0, ARM::R1 };
84 assert((!Reg || Reg == ARM::R3) &&
"Wrong GPRs usage for f64");
98 for (i = 0; i < 2; ++i)
99 if (HiRegList[i] == Reg)
104 assert(T == LoRegList[i] &&
"Could not allocate register");
127 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 };
134 for (i = 0; i < 2; ++i)
135 if (HiRegList[i] == Reg)
165 static const uint16_t
SRegList[] = { ARM::S0, ARM::S1, ARM::S2, ARM::S3,
166 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
167 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
168 ARM::S12, ARM::S13, ARM::S14, ARM::S15 };
169 static const uint16_t
DRegList[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3,
170 ARM::D4, ARM::D5, ARM::D6, ARM::D7 };
171 static const uint16_t
QRegList[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3 };
187 if (PendingMembers.
size() > 0)
188 assert(PendingMembers[0].getLocVT() == LocVT);
202 unsigned Align =
std::min(PendingMembers[0].getExtraInfo(), 8U);
213 while (RegIdx % RegAlign != 0 && RegIdx < RegList.
size())
235 It != PendingMembers.
end(); ++It) {
236 It->convertToReg(RegResult);
240 PendingMembers.
clear();
250 for (
auto &It : PendingMembers) {
251 if (RegIdx >= RegList.
size())
254 It.convertToReg(State.
AllocateReg(RegList[RegIdx++]));
258 PendingMembers.clear();
264 for (
auto Reg : RegList)
267 for (
auto &It : PendingMembers) {
278 PendingMembers.clear();
void push_back(const T &Elt)
static CCValAssign getPending(unsigned ValNo, MVT ValVT, MVT LocVT, LocInfo HTP, unsigned ExtraInfo=0)
static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
unsigned getSizeInBits() const
static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
static bool f64AssignAAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, CCState &State, bool CanFail)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void addLoc(const CCValAssign &V)
Reg
All possible values of the reg field in the ModR/M byte.
Number of individual test Apply this number of consecutive mutations to each input exit after the first new interesting input is found the minimized corpus is saved into the first input directory Number of jobs to run If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
static bool f64AssignAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, CCState &State, bool CanFail)
SmallVectorImpl< llvm::CCValAssign > & getPendingLocs()
static const uint16_t QRegList[]
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
bool isInConsecutiveRegsLast() const
static const uint16_t RRegList[]
static const MCPhysReg GPRArgRegs[]
size_t size() const
size - Get the array size.
unsigned AllocateRegBlock(ArrayRef< uint16_t > Regs, unsigned RegsRequired)
AllocateRegBlock - Attempt to allocate a block of RegsRequired consecutive registers.
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set, or Regs.size() if they are all allocated.
MVT - Machine Value Type.
static bool f64RetAssign(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, CCState &State)
static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
unsigned getNextStackOffset() const
static bool CC_ARM_AAPCS_Custom_Aggregate(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
CCState - This class holds information needed while lowering arguments and return values...
static const uint16_t SRegList[]
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
uint64_t RoundUpToAlignment(uint64_t Value, uint64_t Align)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
static CCValAssign getCustomMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
static const uint16_t DRegList[]
unsigned getOrigAlign() const
unsigned AllocateReg(unsigned Reg)
AllocateReg - Attempt to allocate one register.
unsigned AllocateStack(unsigned Size, unsigned Align)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.