16 #ifndef LLVM_LIB_TARGET_R600_AMDGPUINSTRINFO_H
17 #define LLVM_LIB_TARGET_R600_AMDGPUINSTRINFO_H
23 #define GET_INSTRINFO_HEADER
24 #define GET_INSTRINFO_ENUM
25 #define GET_INSTRINFO_OPERAND_ENUM
26 #include "AMDGPUGenInstrInfo.inc"
28 #define OPCODE_IS_ZERO_INT AMDGPU::PRED_SETE_INT
29 #define OPCODE_IS_NOT_ZERO_INT AMDGPU::PRED_SETNE_INT
30 #define OPCODE_IS_ZERO AMDGPU::PRED_SETE
31 #define OPCODE_IS_NOT_ZERO AMDGPU::PRED_SETNE
35 class AMDGPUSubtarget;
36 class MachineFunction;
38 class MachineInstrBuilder;
43 virtual void anchor();
52 unsigned &DstReg,
unsigned &SubIdx)
const override;
109 unsigned Reg,
bool UnfoldLoad,
bool UnfoldStore,
114 bool UnfoldLoad,
bool UnfoldStore,
115 unsigned *LoadRegIndex =
nullptr)
const override;
120 int64_t Offset1, int64_t Offset2,
121 unsigned NumLoads)
const override;
131 std::vector<MachineOperand> &Pred)
const override;
154 virtual bool isMov(
unsigned opcode)
const = 0;
164 unsigned Channel)
const = 0;
175 unsigned ValueReg,
unsigned Address,
176 unsigned OffsetReg)
const = 0;
183 unsigned ValueReg,
unsigned Address,
184 unsigned OffsetReg)
const = 0;
189 unsigned DstReg,
unsigned SrcReg)
const = 0;
203 #define AMDGPU_FLAG_REGISTER_LOAD (UINT64_C(1) << 63)
204 #define AMDGPU_FLAG_REGISTER_STORE (UINT64_C(1) << 62)
int getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const
Given a MIMG Opcode that writes all 4 channels, return the equivalent opcode that writes Channels Cha...
bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override
Describe properties that are true of each instruction in the target description file.
unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const override
bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override
AMDGPUInstrInfo(const AMDGPUSubtarget &st)
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool DefinesPredicate(MachineInstr *MI, std::vector< MachineOperand > &Pred) const override
bool hasStoreFromStackSlot(const MachineInstr *MI, const MachineMemOperand *&MMO, int &FrameIndex) const
bool ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
int pseudoToMCOpcode(int Opcode) const
Return a target-specific opcode if Opcode is a pseudo instruction.
MachineMemOperand - A description of a memory reference used in the backend.
const AMDGPUSubtarget & ST
bool isPredicated(const MachineInstr *MI) const override
virtual const AMDGPURegisterInfo & getRegisterInfo() const =0
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Reg
All possible values of the reg field in the ModR/M byte.
unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const override
unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const override
const MCInstrDesc & getMCOpcodeFromPseudo(unsigned Opcode) const
Return the descriptor of the target-specific machine instruction that corresponds to the specified ps...
TargetRegisterInfo interface that is implemented by all hw codegen targets.
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
bool canFoldMemoryOperand(const MachineInstr *MI, ArrayRef< unsigned > Ops) const override
MachineInstr * convertToThreeAddress(MachineFunction::iterator &MFI, MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const override
virtual unsigned calculateIndirectAddress(unsigned RegIndex, unsigned Channel) const =0
Calculate the "Indirect Address" for the given RegIndex and Channel.
bundle_iterator< MachineInstr, instr_iterator > iterator
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex) const override
bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override
virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned ValueReg, unsigned Address, unsigned OffsetReg) const =0
Build instruction(s) for an indirect register write.
bundle_iterator - MachineBasicBlock iterator that automatically skips over MIs that are inside bundle...
bool hasLoadFromStackSlot(const MachineInstr *MI, const MachineMemOperand *&MMO, int &FrameIndex) const override
bool isRegisterLoad(const MachineInstr &MI) const
bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override
bool isPredicable(MachineInstr *MI) const override
bool enableClusterLoads() const override
virtual const TargetRegisterClass * getIndirectAddrRegClass() const =0
virtual MachineInstr * buildMovInstr(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned DstReg, unsigned SrcReg) const =0
Build a MOV instruction.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
unsigned isStoreFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
Represents one node in the SelectionDAG.
unsigned isStoreFromStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const
int getIndirectIndexEnd(const MachineFunction &MF) const
Representation of each machine instruction.
bool isRegisterStore(const MachineInstr &MI) const
int getIndirectIndexBegin(const MachineFunction &MF) const
BasicBlockListType::iterator iterator
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex)
virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned ValueReg, unsigned Address, unsigned OffsetReg) const =0
Build instruction(s) for an indirect register read.
virtual bool isMov(unsigned opcode) const =0