49 if (ARM::tGPRRegClass.hasSubClassEq(RC))
50 return &ARM::tGPRRegClass;
56 unsigned Kind)
const {
59 return &ARM::tGPRRegClass;
65 unsigned SubIdx,
int Val,
85 unsigned SubIdx,
int Val,
106 unsigned PredReg,
unsigned MIFlags)
const {
111 "Thumb1 does not have ldr to high register");
127 unsigned DestReg,
unsigned BaseReg,
128 int NumBytes,
bool CanChangeCC,
140 if (NumBytes < 0 && !isHigh && CanChangeCC) {
142 NumBytes = -NumBytes;
144 unsigned LdReg = DestReg;
145 if (DestReg == ARM::SP)
146 assert(BaseReg == ARM::SP &&
"Unexpected!");
150 if (NumBytes <= 255 && NumBytes >= 0 && CanChangeCC) {
153 }
else if (NumBytes < 0 && NumBytes >= -255 && CanChangeCC) {
163 int Opc = (isSub) ? ARM::tSUBrr : ((isHigh || !CanChangeCC) ? ARM::tADDhirr
166 BuildMI(MBB, MBBI, dl, TII.
get(Opc), DestReg);
167 if (Opc != ARM::tADDhirr)
169 if (DestReg == ARM::SP || isSub)
183 unsigned DestReg,
unsigned BaseReg,
187 bool isSub = NumBytes < 0;
188 unsigned Bytes = (
unsigned)NumBytes;
189 if (isSub) Bytes = -NumBytes;
192 unsigned CopyBits = 0;
193 unsigned CopyScale = 1;
194 bool CopyNeedsCC =
false;
196 unsigned ExtraBits = 0;
197 unsigned ExtraScale = 1;
198 bool ExtraNeedsCC =
false;
213 if (DestReg == ARM::SP) {
214 if (BaseReg == ARM::SP) {
219 CopyOpc = ARM::tMOVr;
222 ExtraOpc = isSub ? ARM::tSUBspi : ARM::tADDspi;
226 if (BaseReg == ARM::SP) {
228 assert(!isSub &&
"Thumb1 does not have tSUBrSPi");
229 CopyOpc = ARM::tADDrSPi;
232 }
else if (DestReg == BaseReg) {
237 CopyOpc = isSub ? ARM::tSUBi3 : ARM::tADDi3;
242 CopyOpc = ARM::tMOVr;
245 ExtraOpc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
249 if (DestReg == BaseReg) {
254 CopyOpc = ARM::tMOVr;
262 assert(((Bytes & 3) == 0 || ExtraScale == 1) &&
263 "Unaligned offset, but all instructions require alignment");
265 unsigned CopyRange = ((1 << CopyBits) - 1) * CopyScale;
267 if (CopyOpc && Bytes < CopyScale) {
268 CopyOpc = ARM::tMOVr;
273 unsigned ExtraRange = ((1 << ExtraBits) - 1) * ExtraScale;
274 unsigned RequiredCopyInstrs = CopyOpc ? 1 : 0;
275 unsigned RangeAfterCopy = (CopyRange > Bytes) ? 0 : (Bytes - CopyRange);
279 assert(RangeAfterCopy % ExtraScale == 0 &&
280 "Extra instruction requires immediate to be aligned");
282 unsigned RequiredExtraInstrs;
285 else if (RangeAfterCopy > 0)
287 RequiredExtraInstrs = 1000000;
289 RequiredExtraInstrs = 0;
290 unsigned RequiredInstrs = RequiredCopyInstrs + RequiredExtraInstrs;
291 unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;
294 if (RequiredInstrs > Threshold) {
296 DestReg, BaseReg, NumBytes,
true,
303 unsigned CopyImm =
std::min(Bytes, CopyRange) / CopyScale;
304 Bytes -= CopyImm * CopyScale;
310 if (CopyOpc != ARM::tMOVr) {
320 unsigned ExtraImm =
std::min(Bytes, ExtraRange) / ExtraScale;
321 Bytes -= ExtraImm * ExtraScale;
353 unsigned FrameRegIdx,
354 unsigned FrameReg,
int &Offset,
359 "This isn't needed for thumb2!");
366 if (Opcode == ARM::tADDframe) {
378 unsigned ImmIdx = FrameRegIdx + 1;
380 unsigned NumBits = (FrameReg == ARM::SP) ? 8 : 5;
383 Offset += InstrOffs * Scale;
384 assert((Offset & (Scale - 1)) == 0 &&
"Can't encode this offset!");
388 int ImmedOffset = Offset / Scale;
389 unsigned Mask = (1 << NumBits) - 1;
391 if ((
unsigned)Offset <= Mask * Scale) {
399 if (NewOpc != Opcode && FrameReg != ARM::SP)
406 Mask = (1 << NumBits) - 1;
410 if (Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi) {
414 ImmedOffset = ImmedOffset & Mask;
416 Offset &= ~(Mask * Scale);
424 int64_t Offset)
const {
436 assert(i < MI.
getNumOperands() &&
"Instr doesn't have FrameIndex operand!");
439 assert (Done &&
"Unable to resolve frame index!");
448 unsigned Reg)
const {
452 return ARMBaseRegisterInfo::saveScavengerRegister(MBB, I, UseMI, RC, Reg);
470 if (II->isDebugValue())
473 for (
unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
483 if (MO.
getReg() == ARM::R12) {
498 int SPAdj,
unsigned FIOperandNum,
514 unsigned FrameReg = ARM::SP;
537 "Cannot use SP to access the emergency spill slot in "
538 "functions without a reserved call frame");
540 "Cannot use SP to access the emergency spill slot in "
541 "functions with variable sized frame objects");
547 MI.
getOperand(FIOperandNum). ChangeToRegister(FrameReg,
false );
554 "This eliminateFrameIndex only supports Thumb1!");
561 assert(Offset &&
"This code isn't needed if offset already handled!");
574 if (Opcode == ARM::tLDRspi) {
575 if (FrameReg == ARM::SP)
577 Offset,
false, TII, *
this);
587 MI.
setDesc(TII.get(UseRR ? ARM::tLDRr : ARM::tLDRi));
598 if (Opcode == ARM::tSTRspi) {
599 if (FrameReg == ARM::SP)
601 Offset,
false, TII, *
this);
609 MI.
setDesc(TII.get(UseRR ? ARM::tSTRr : ARM::tSTRi));
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
static void removeOperands(MachineInstr &MI, unsigned i)
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
Describe properties that are true of each instruction in the target description file.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
void emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred=ARMCC::AL, unsigned PredReg=0, unsigned MIFlags=MachineInstr::NoFlags) const override
emitLoadConstPool - Emits a load from constpool to materialize the specified immediate.
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
bool isPredicable(QueryType Type=AllInBundle) const
Return true if this instruction has a predicate operand that controls execution.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
bool isThumbFunction() const
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
bool isThumb1Only() const
static unsigned convertToNonSPOpcode(unsigned Opcode)
convertToNonSPOpcode - Change the opcode to the non-SP version, because we're replacing the frame ind...
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
const ARMBaseInstrInfo * getInstrInfo() const override
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
bool saveScavengerRegister(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, unsigned Reg) const override
saveScavengerRegister - Spill the register so it can be used by the register scavenger.
static const MachineInstrBuilder & AddDefaultPred(const MachineInstrBuilder &MIB)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
DILocation * get() const
Get the underlying DILocation.
const HexagonInstrInfo * TII
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getFrameRegister(const MachineFunction &MF) const override
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required, we reserve argument space for call sites in the function immediately on entry to the current function.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Reg
All possible values of the reg field in the ModR/M byte.
Number of individual test Apply this number of consecutive mutations to each input exit after the first new interesting input is found the minimized corpus is saved into the first input directory Number of jobs to run If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
const MachineBasicBlock * getParent() const
TargetInstrInfo - Interface to description of machine instruction set.
bool isDebugValue() const
unsigned getDefRegState(bool B)
bundle_iterator< MachineInstr, instr_iterator > iterator
This is an important base class in LLVM.
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const MachineOperand & getOperand(unsigned i) const
unsigned getFramePtrSpillOffset() const
void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags=0)
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const ARMFrameLowering * getFrameLowering() const override
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
bool isScavengingFrameIndex(int FI) const
Query whether a frame index is a scavenging frame index.
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
MachineOperand class - Representation of each machine instruction operand.
static void emitThumb2LoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags)
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
bool hasBasePointer(const MachineFunction &MF) const
AddrMode
ARM Addressing Modes.
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
uint64_t RoundUpToAlignment(uint64_t Value, uint64_t Align)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
cl::opt< bool > ReuseFrameIndexVals
void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override
static bool isARMLowRegister(unsigned Reg)
isARMLowRegister - Returns true if the register is a low register (r0-r7).
Representation of each machine instruction.
static void emitThumb1LoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags)
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static IntegerType * getInt32Ty(LLVMContext &C)
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
static void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, bool CanChangeCC, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags=MachineInstr::NoFlags)
emitThumbRegPlusImmInReg - Emits a series of instructions to materialize a destreg = basereg + immedi...
unsigned BasePtr
BasePtr - ARM physical register used as a base ptr in complex stack frames.
bool rewriteFrameIndex(MachineBasicBlock::iterator II, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const ARMBaseInstrInfo &TII) const
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
virtual void emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred=ARMCC::AL, unsigned PredReg=0, unsigned MIFlags=MachineInstr::NoFlags) const
emitLoadConstPool - Emits a load from constpool to materialize the specified immediate.
static int const Threshold
TODO: Write a new FunctionPass AliasAnalysis so that it can keep a cache.
unsigned getReg() const
getReg - Returns the register number.
const ARM::ArchExtKind Kind
virtual const TargetInstrInfo * getInstrInfo() const
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
unsigned getConstantPoolIndex(const Constant *C, unsigned Alignment)
getConstantPoolIndex - Create a new entry in the constant pool or return an existing one...
static const MachineInstrBuilder & AddDefaultT1CC(const MachineInstrBuilder &MIB, bool isDead=false)