LLVM  3.7.0
R600MCCodeEmitter.cpp
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1 //===- R600MCCodeEmitter.cpp - Code Emitter for R600->Cayman GPU families -===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 ///
12 /// \brief The R600 code emitter produces machine code that can be executed
13 /// directly on the GPU device.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #include "R600Defines.h"
20 #include "llvm/MC/MCCodeEmitter.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/MC/MCInstrInfo.h"
24 #include "llvm/MC/MCRegisterInfo.h"
28 
29 using namespace llvm;
30 
31 namespace {
32 
33 class R600MCCodeEmitter : public AMDGPUMCCodeEmitter {
34  R600MCCodeEmitter(const R600MCCodeEmitter &) = delete;
35  void operator=(const R600MCCodeEmitter &) = delete;
36  const MCInstrInfo &MCII;
37  const MCRegisterInfo &MRI;
38 
39 public:
40 
41  R600MCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri)
42  : MCII(mcii), MRI(mri) { }
43 
44  /// \brief Encode the instruction and write it to the OS.
45  void encodeInstruction(const MCInst &MI, raw_ostream &OS,
47  const MCSubtargetInfo &STI) const override;
48 
49  /// \returns the encoding for an MCOperand.
50  uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
52  const MCSubtargetInfo &STI) const override;
53 private:
54 
55  void EmitByte(unsigned int byte, raw_ostream &OS) const;
56 
57  void Emit(uint32_t value, raw_ostream &OS) const;
58  void Emit(uint64_t value, raw_ostream &OS) const;
59 
60  unsigned getHWRegChan(unsigned reg) const;
61  unsigned getHWReg(unsigned regNo) const;
62 
63 };
64 
65 } // End anonymous namespace
66 
67 enum RegElement {
68  ELEMENT_X = 0,
72 };
73 
74 enum FCInstr {
82 };
83 
85  const MCRegisterInfo &MRI,
86  MCContext &Ctx) {
87  return new R600MCCodeEmitter(MCII, MRI);
88 }
89 
90 void R600MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
92  const MCSubtargetInfo &STI) const {
93  const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
94  if (MI.getOpcode() == AMDGPU::RETURN ||
95  MI.getOpcode() == AMDGPU::FETCH_CLAUSE ||
96  MI.getOpcode() == AMDGPU::ALU_CLAUSE ||
97  MI.getOpcode() == AMDGPU::BUNDLE ||
98  MI.getOpcode() == AMDGPU::KILL) {
99  return;
100  } else if (IS_VTX(Desc)) {
101  uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups, STI);
102  uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset
103  if (!(STI.getFeatureBits()[AMDGPU::FeatureCaymanISA])) {
104  InstWord2 |= 1 << 19; // Mega-Fetch bit
105  }
106 
107  Emit(InstWord01, OS);
108  Emit(InstWord2, OS);
109  Emit((uint32_t) 0, OS);
110  } else if (IS_TEX(Desc)) {
111  int64_t Sampler = MI.getOperand(14).getImm();
112 
113  int64_t SrcSelect[4] = {
114  MI.getOperand(2).getImm(),
115  MI.getOperand(3).getImm(),
116  MI.getOperand(4).getImm(),
117  MI.getOperand(5).getImm()
118  };
119  int64_t Offsets[3] = {
120  MI.getOperand(6).getImm() & 0x1F,
121  MI.getOperand(7).getImm() & 0x1F,
122  MI.getOperand(8).getImm() & 0x1F
123  };
124 
125  uint64_t Word01 = getBinaryCodeForInstr(MI, Fixups, STI);
126  uint32_t Word2 = Sampler << 15 | SrcSelect[ELEMENT_X] << 20 |
127  SrcSelect[ELEMENT_Y] << 23 | SrcSelect[ELEMENT_Z] << 26 |
128  SrcSelect[ELEMENT_W] << 29 | Offsets[0] << 0 | Offsets[1] << 5 |
129  Offsets[2] << 10;
130 
131  Emit(Word01, OS);
132  Emit(Word2, OS);
133  Emit((uint32_t) 0, OS);
134  } else {
135  uint64_t Inst = getBinaryCodeForInstr(MI, Fixups, STI);
136  if ((STI.getFeatureBits()[AMDGPU::FeatureR600ALUInst]) &&
137  ((Desc.TSFlags & R600_InstFlag::OP1) ||
138  Desc.TSFlags & R600_InstFlag::OP2)) {
139  uint64_t ISAOpCode = Inst & (0x3FFULL << 39);
140  Inst &= ~(0x3FFULL << 39);
141  Inst |= ISAOpCode << 1;
142  }
143  Emit(Inst, OS);
144  }
145 }
146 
147 void R600MCCodeEmitter::EmitByte(unsigned int Byte, raw_ostream &OS) const {
148  OS.write((uint8_t) Byte & 0xff);
149 }
150 
151 void R600MCCodeEmitter::Emit(uint32_t Value, raw_ostream &OS) const {
153 }
154 
155 void R600MCCodeEmitter::Emit(uint64_t Value, raw_ostream &OS) const {
157 }
158 
159 unsigned R600MCCodeEmitter::getHWRegChan(unsigned reg) const {
160  return MRI.getEncodingValue(reg) >> HW_CHAN_SHIFT;
161 }
162 
163 unsigned R600MCCodeEmitter::getHWReg(unsigned RegNo) const {
164  return MRI.getEncodingValue(RegNo) & HW_REG_MASK;
165 }
166 
167 uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI,
168  const MCOperand &MO,
170  const MCSubtargetInfo &STI) const {
171  if (MO.isReg()) {
172  if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags))
173  return MRI.getEncodingValue(MO.getReg());
174  return getHWReg(MO.getReg());
175  }
176 
177  assert(MO.isImm());
178  return MO.getImm();
179 }
180 
181 #include "AMDGPUGenMCCodeEmitter.inc"
bool isReg() const
Definition: MCInst.h:56
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:138
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:378
MCCodeEmitter * createR600MCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APInt.h:33
#define HW_CHAN_SHIFT
Definition: R600Defines.h:57
#define HAS_NATIVE_OPERANDS(Flags)
Definition: R600Defines.h:53
Context object for machine code objects.
Definition: MCContext.h:48
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:63
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:150
#define HW_REG_MASK
Defines for extracting register information from register encoding.
Definition: R600Defines.h:56
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
bool isImm() const
Definition: MCInst.h:57
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:23
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
raw_ostream & write(unsigned char C)
PowerPC TLS Dynamic Call Fixup
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
#define IS_TEX(desc)
Definition: R600Defines.h:63
BUNDLE - This instruction represents an instruction bundle.
Definition: TargetOpcodes.h:91
unsigned getOpcode() const
Definition: MCInst.h:159
int64_t getImm() const
Definition: MCInst.h:74
KILL - This instruction is a noop that is used only to adjust the liveness of registers.
Definition: TargetOpcodes.h:35
void write(void *memory, value_type value)
Write a value to memory with a particular endianness.
Definition: Endian.h:73
Provides AMDGPU specific target descriptions.
Adapter to write values to a stream in a particular byte order.
Definition: EndianStream.h:26
MCSubtargetInfo - Generic base class for all target subtargets.
CodeEmitter interface for R600 and SI codegen.
LLVM Value Representation.
Definition: Value.h:69
#define IS_VTX(desc)
Definition: R600Defines.h:62
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:38
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:33
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:164