28 #define DEBUG_TYPE "mccodeemitter"
31 using namespace Hexagon;
33 STATISTIC(MCNumEmitted,
"Number of MC instructions emitted");
37 : MCT(aMCT), MCII(aMII), Addend(new
unsigned(0)),
44 if (Instruction == 0) {
47 assert(Instruction != Last);
51 if (Instruction == 1) {
54 assert(Instruction != Last);
59 assert(Instruction == Last);
62 if(Instruction == Last)
102 "pseudo-instruction found");
111 unsigned SOffset = 0;
115 auto i = Instructions.begin() + Index - 1;
117 assert(i != Instructions.begin() - 1 &&
"Couldn't find producer");
118 MCInst const &Inst = *i->getInst();
125 :
static_cast<unsigned>(Hexagon::NoRegister);
126 if (Register != Register1)
133 "Unpredicated consumer depending on predicated producer");
140 unsigned Offset = SOffset;
142 MCO.
setReg(Offset + Hexagon::R0);
161 if (HMB.
getOpcode() >= Hexagon::DuplexIClass0 &&
162 HMB.
getOpcode() <= Hexagon::DuplexIClassF) {
164 "Emitting duplex without duplex parse bits");
167 case Hexagon::DuplexIClass0:
170 case Hexagon::DuplexIClass1:
173 case Hexagon::DuplexIClass2:
176 case Hexagon::DuplexIClass3:
179 case Hexagon::DuplexIClass4:
182 case Hexagon::DuplexIClass5:
185 case Hexagon::DuplexIClass6:
188 case Hexagon::DuplexIClass7:
191 case Hexagon::DuplexIClass8:
194 case Hexagon::DuplexIClass9:
197 case Hexagon::DuplexIClassA:
200 case Hexagon::DuplexIClassB:
203 case Hexagon::DuplexIClassC:
206 case Hexagon::DuplexIClassD:
209 case Hexagon::DuplexIClassE:
212 case Hexagon::DuplexIClassF:
222 Binary = ((dupIClass & 0xE) << (29 - 1)) | ((dupIClass & 0x1) << 13);
232 Binary |= subInstSlot0Bits | (subInstSlot1Bits << 16);
273 case Hexagon::A2_tfrih:
296 case Hexagon::A2_tfril:
323 if (*ImpUses == Hexagon::GP) {
350 bool isPCRel (
unsigned Kind) {
375 unsigned HexagonMCCodeEmitter::getExprOpValue(
const MCInst &
MI,
384 if (ME->evaluateAsAbsolute(Res))
389 return cast<MCConstantExpr>(ME)->getValue();
393 Res = getExprOpValue(MI, MO, cast<MCBinaryExpr>(ME)->getLHS(), Fixups, STI);
395 getExprOpValue(MI, MO, cast<MCBinaryExpr>(ME)->getRHS(), Fixups, STI);
409 DEBUG(
dbgs() <<
"----------------------------------------\n");
413 DEBUG(
dbgs() <<
"Relocation bits: " << bits <<
"\n");
414 DEBUG(
dbgs() <<
"Addend: " << *Addend <<
"\n");
415 DEBUG(
dbgs() <<
"----------------------------------------\n");
419 DEBUG(
dbgs() <<
"unrecognized bit count of " << bits <<
'\n');
479 errs() <<
"unrecognized relocation, bits: " << bits <<
"\n";
520 errs() <<
"unrecognized relocation, bits " << bits <<
"\n";
567 errs() <<
"unrecognized relocation, bits " << bits <<
"\n";
587 errs() <<
"unrecognized relocation, bits " << bits <<
"\n";
621 errs() <<
"unrecognized relocation, bits " << bits <<
"\n";
639 errs() <<
"unrecognized relocation, bits " << bits <<
"\n";
648 errs() <<
"unrecognized relocation, bits " << bits <<
"\n";
661 errs() <<
"unrecognized relocation, bits " << bits <<
"\n";
685 errs() <<
"unrecognized relocation, bits " << bits <<
"\n";
695 MCExpr const *FixupExpression = (*Addend > 0 && isPCRel(FixupKind)) ?
714 return static_cast<unsigned>(MO.
getImm());
727 #include "HexagonGenMCCodeEmitter.inc"
bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
void push_back(const T &Elt)
unsigned short getNewValueOp(MCInstrInfo const &MCII, MCInst const &MCI)
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
STATISTIC(NumFunctions,"Total number of functions")
bool mayStore() const
Return true if this instruction could possibly modify memory.
Describe properties that are true of each instruction in the target description file.
const uint16_t * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction...
bool isBundle(MCInst const &MCI)
uint64_t getBinaryCodeForInstr(MCInst const &MI, SmallVectorImpl< MCFixup > &Fixups, MCSubtargetInfo const &STI) const
bool isOuterLoop(MCInst const &MCI)
bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
uint32_t parseBits(size_t Instruction, size_t Last, MCInst const &MCB, MCInst const &MCI) const
static Hexagon::Fixups getFixupNoBits(MCInstrInfo const &MCII, const MCInst &MI, const MCOperand &MO, const MCSymbolRefExpr::VariantKind kind)
bool isImmext(MCInst const &MCI)
void EncodeSingleInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI, uint32_t Parse, size_t Index) const
EncodeSingleInstruction - Emit a single.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
bool isCall() const
Return true if the instruction is a call.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Base class for the full range of assembler expressions which are needed for parsing.
const MCInstrDesc HexagonInsts[]
Represent a reference to a symbol from inside an expression.
Context object for machine code objects.
unsigned getReg() const
Returns the register number.
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Instances of this class represent a single low-level machine instruction.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
void encodeInstruction(MCInst const &MI, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, MCSubtargetInfo const &STI) const override
EncodeInstruction - Encode the given Inst to bytes on the output stream OS.
const MCExpr * getExpr() const
char const * getName(MCInstrInfo const &MCII, MCInst const &MCI)
MCCodeEmitter * createHexagonMCCodeEmitter(MCInstrInfo const &MCII, MCRegisterInfo const &MRI, MCContext &MCT)
MCCodeEmitter - Generic instruction encoding interface.
Interface to description of machine instruction set.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
iterator_range< MCInst::const_iterator > bundleInstructions(MCInst const &MCI)
Definition for classes that emit Hexagon machine code from MCInsts.
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
unsigned getOpcode() const
Return the opcode number for this descriptor.
Promote Memory to Register
bool mayLoad() const
Return true if this instruction could possibly read memory.
HexagonII::MemAccessSize getAccessSize(MCInstrInfo const &MCII, MCInst const &MCI)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
unsigned getOpcode() const
bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI)
HexagonMCCodeEmitter(MCInstrInfo const &aMII, MCContext &aMCT)
const MCRegisterInfo * getRegisterInfo() const
Adapter to write values to a stream in a particular byte order.
MCSubtargetInfo - Generic base class for all target subtargets.
const MCInst * getInst() const
References to labels and assigned expressions.
MCInstrDesc const & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
size_t bundleSize(MCInst const &MCI)
void setReg(unsigned Reg)
Set the register number.
VariantKind getKind() const
bool isInnerLoop(MCInst const &MCI)
const ARM::ArchExtKind Kind
#define HEXAGON_INSTR_SIZE
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
This class implements an extremely fast bulk output stream that can only output to a stream...
bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI)
Instances of this class represent operands of the MCInst class.
bool isPredicatedTrue(MCInstrInfo const &MCII, MCInst const &MCI)
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx)
unsigned getMachineOpValue(MCInst const &MI, MCOperand const &MO, SmallVectorImpl< MCFixup > &Fixups, MCSubtargetInfo const &STI) const
Return binary encoding of operand.
const MCOperand & getOperand(unsigned i) const
MCOperand const & getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI)