39 #define DEBUG_TYPE "xcore-reg-info"
41 #define GET_REGINFO_TARGET_DESC
42 #include "XCoreGenRegisterInfo.inc"
49 static inline bool isImmUs(
unsigned val) {
53 static inline bool isImmU6(
unsigned val) {
54 return val < (1 << 6);
58 return val < (1 << 16);
64 unsigned Reg,
unsigned FrameReg,
int Offset ) {
71 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus),
Reg)
77 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
84 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus),
Reg)
95 unsigned Reg,
unsigned FrameReg,
97 assert(RS &&
"requiresRegisterScavenging failed");
101 unsigned ScratchOffset = RS->
scavengeRegister(&XCore::GRRegsRegClass, II, 0);
107 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r),
Reg)
113 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r))
120 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r),
Reg)
131 unsigned Reg,
int Offset) {
140 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
146 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
147 BuildMI(MBB, II, dl, TII.get(NewOpcode))
153 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
165 assert(RS &&
"requiresRegisterScavenging failed");
171 unsigned ScratchBase;
172 if (OpCode==XCore::STWFI) {
177 BuildMI(MBB, II, dl, TII.get(XCore::LDAWSP_ru6), ScratchBase).addImm(0);
178 unsigned ScratchOffset = RS->
scavengeRegister(&XCore::GRRegsRegClass, II, 0);
184 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r),
Reg)
190 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r))
197 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r),
Reg)
215 static const MCPhysReg CalleeSavedRegs[] = {
217 XCore::R8, XCore::R9, XCore::R10,
220 static const MCPhysReg CalleeSavedRegsFP[] = {
222 XCore::R8, XCore::R9,
227 return CalleeSavedRegsFP;
228 return CalleeSavedRegs;
236 Reserved.
set(XCore::DP);
237 Reserved.
set(XCore::SP);
238 Reserved.
set(XCore::LR);
239 if (TFI->
hasFP(MF)) {
240 Reserved.
set(XCore::R10);
262 int SPAdj,
unsigned FIOperandNum,
264 assert(SPAdj == 0 &&
"Unexpected");
282 DEBUG(
errs() <<
"FrameIndex : " << FrameIndex <<
"\n");
283 DEBUG(
errs() <<
"FrameOffset : " << Offset <<
"\n");
284 DEBUG(
errs() <<
"StackSize : " << StackSize <<
"\n");
302 assert(Offset%4 == 0 &&
"Misaligned stack offset");
303 DEBUG(
errs() <<
"Offset : " << Offset <<
"\n" <<
"<--------->\n");
307 assert(XCore::GRRegsRegClass.
contains(Reg) &&
"Unexpected register operand");
309 if (TFI->
hasFP(MF)) {
329 return TFI->
hasFP(MF) ? XCore::R10 : XCore::SP;
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
const HexagonInstrInfo * TII
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Reg
All possible values of the reg field in the ModR/M byte.
bool hasDebugInfo() const
hasDebugInfo - Returns true if valid debug info is present.
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
static bool needsFrameMoves(const MachineFunction &MF)
Return whether to emit frame moves.
unsigned getKillRegState(bool B)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
const MachineBasicBlock * getParent() const
bool isDebugValue() const
bundle_iterator< MachineInstr, instr_iterator > iterator
bool useFPForScavengingIndex(const MachineFunction &MF) const override
void print(raw_ostream &OS, bool SkipOpers=false) const
const MachineOperand & getOperand(unsigned i) const
static void InsertSPImmInst(MachineBasicBlock::iterator II, const XCoreInstrInfo &TII, unsigned Reg, int Offset)
unsigned getFrameRegister(const MachineFunction &MF) const override
static void InsertFPConstInst(MachineBasicBlock::iterator II, const XCoreInstrInfo &TII, unsigned Reg, unsigned FrameReg, int Offset, RegScavenger *RS)
MachineBasicBlock::iterator loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Reg, uint64_t Value) const
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
bool requiresRegisterScavenging(const MachineFunction &MF) const override
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
static bool isImmUs(unsigned val)
MachineOperand class - Representation of each machine instruction operand.
BitVector getReservedRegs(const MachineFunction &MF) const override
bool needsUnwindTableEntry() const
True if this function needs an unwind table.
void setRegUsed(unsigned Reg)
Tell the scavenger a register is used.
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static bool isImmU6(unsigned val)
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Representation of each machine instruction.
static bool isImmU16(unsigned val)
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
static void InsertSPConstInst(MachineBasicBlock::iterator II, const XCoreInstrInfo &TII, unsigned Reg, int Offset, RegScavenger *RS)
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
static void InsertFPImmInst(MachineBasicBlock::iterator II, const XCoreInstrInfo &TII, unsigned Reg, unsigned FrameReg, int Offset)
unsigned getReg() const
getReg - Returns the register number.
virtual const TargetInstrInfo * getInstrInfo() const
MachineModuleInfo & getMMI() const
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
unsigned scavengeRegister(const TargetRegisterClass *RegClass, MachineBasicBlock::iterator I, int SPAdj)
Make a register of the specific register class available and do the appropriate bookkeeping.
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...