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LLVM
3.7.0
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#include <X86InstrInfo.h>
Public Member Functions | |
| X86InstrInfo (X86Subtarget &STI) | |
| const X86RegisterInfo & | getRegisterInfo () const |
| getRegisterInfo - TargetInstrInfo is a superset of MRegister info. More... | |
| int | getSPAdjust (const MachineInstr *MI) const override |
| getSPAdjust - This returns the stack pointer adjustment made by this instruction. More... | |
| bool | isCoalescableExtInstr (const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override |
| isCoalescableExtInstr - Return true if the instruction is a "coalescable" extension instruction. More... | |
| unsigned | isLoadFromStackSlot (const MachineInstr *MI, int &FrameIndex) const override |
| unsigned | isLoadFromStackSlotPostFE (const MachineInstr *MI, int &FrameIndex) const override |
| isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well. More... | |
| unsigned | isStoreToStackSlot (const MachineInstr *MI, int &FrameIndex) const override |
| unsigned | isStoreToStackSlotPostFE (const MachineInstr *MI, int &FrameIndex) const override |
| isStoreToStackSlotPostFE - Check for post-frame ptr elimination stack locations as well. More... | |
| bool | isReallyTriviallyReMaterializable (const MachineInstr *MI, AliasAnalysis *AA) const override |
| void | reMaterialize (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SubIdx, const MachineInstr *Orig, const TargetRegisterInfo &TRI) const override |
| bool | classifyLEAReg (MachineInstr *MI, const MachineOperand &Src, unsigned LEAOpcode, bool AllowSP, unsigned &NewSrc, bool &isKill, bool &isUndef, MachineOperand &ImplicitOp) const |
| Given an operand within a MachineInstr, insert preceding code to put it into the right format for a particular kind of LEA instruction. More... | |
| MachineInstr * | convertToThreeAddress (MachineFunction::iterator &MFI, MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const override |
| convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag. More... | |
| MachineInstr * | commuteInstruction (MachineInstr *MI, bool NewMI) const override |
| commuteInstruction - We have a few instructions that must be hacked on to commute them. More... | |
| bool | findCommutedOpIndices (MachineInstr *MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override |
| bool | isUnpredicatedTerminator (const MachineInstr *MI) const override |
| bool | AnalyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override |
| bool | getMemOpBaseRegImmOfs (MachineInstr *LdSt, unsigned &BaseReg, unsigned &Offset, const TargetRegisterInfo *TRI) const override |
| bool | AnalyzeBranchPredicate (MachineBasicBlock &MBB, TargetInstrInfo::MachineBranchPredicate &MBP, bool AllowModify=false) const override |
| unsigned | RemoveBranch (MachineBasicBlock &MBB) const override |
| unsigned | InsertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, DebugLoc DL) const override |
| bool | canInsertSelect (const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override |
| void | insertSelect (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override |
| void | copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override |
| void | storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override |
| void | storeRegToAddr (MachineFunction &MF, unsigned SrcReg, bool isKill, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, MachineInstr::mmo_iterator MMOBegin, MachineInstr::mmo_iterator MMOEnd, SmallVectorImpl< MachineInstr * > &NewMIs) const |
| void | loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override |
| void | loadRegFromAddr (MachineFunction &MF, unsigned DestReg, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, MachineInstr::mmo_iterator MMOBegin, MachineInstr::mmo_iterator MMOEnd, SmallVectorImpl< MachineInstr * > &NewMIs) const |
| bool | expandPostRAPseudo (MachineBasicBlock::iterator MI) const override |
| MachineInstr * | foldMemoryOperandImpl (MachineFunction &MF, MachineInstr *MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex) const override |
| foldMemoryOperand - If this target supports it, fold a load or store of the specified stack slot into the specified machine instruction for the specified operand(s). More... | |
| MachineInstr * | foldMemoryOperandImpl (MachineFunction &MF, MachineInstr *MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr *LoadMI) const override |
| foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address, not just from a specific stack slot. More... | |
| bool | canFoldMemoryOperand (const MachineInstr *, ArrayRef< unsigned >) const override |
| canFoldMemoryOperand - Returns true if the specified load / store is folding is possible. More... | |
| bool | unfoldMemoryOperand (MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const override |
| unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a store into two or more instruction. More... | |
| bool | unfoldMemoryOperand (SelectionDAG &DAG, SDNode *N, SmallVectorImpl< SDNode * > &NewNodes) const override |
| unsigned | getOpcodeAfterMemoryUnfold (unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const override |
| getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new instruction after load / store are unfolded from an instruction of the specified opcode. More... | |
| bool | areLoadsFromSameBasePtr (SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override |
| areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address. More... | |
| bool | shouldScheduleLoadsNear (SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override |
| shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePtr) if two loads should be scheduled togther. More... | |
| bool | shouldScheduleAdjacent (MachineInstr *First, MachineInstr *Second) const override |
| void | getNoopForMachoTarget (MCInst &NopInst) const override |
| Return the noop instruction to use for a noop. More... | |
| bool | ReverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override |
| bool | isSafeToMoveRegClassDefs (const TargetRegisterClass *RC) const override |
| isSafeToMoveRegClassDefs - Return true if it's safe to move a machine instruction that defines the specified register class. More... | |
| bool | isSafeToClobberEFLAGS (MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const |
| isSafeToClobberEFLAGS - Return true if it's safe insert an instruction tha would clobber the EFLAGS condition register. More... | |
| unsigned | getGlobalBaseReg (MachineFunction *MF) const |
| getGlobalBaseReg - Return a virtual register initialized with the the global base register value. More... | |
| std::pair< uint16_t, uint16_t > | getExecutionDomain (const MachineInstr *MI) const override |
| void | setExecutionDomain (MachineInstr *MI, unsigned Domain) const override |
| unsigned | getPartialRegUpdateClearance (const MachineInstr *MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override |
| Inform the ExeDepsFix pass how many idle instructions we would like before a partial register update. More... | |
| unsigned | getUndefRegClearance (const MachineInstr *MI, unsigned &OpNum, const TargetRegisterInfo *TRI) const override |
| Inform the ExeDepsFix pass how many idle instructions we would like before certain undef register reads. More... | |
| void | breakPartialRegDependency (MachineBasicBlock::iterator MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override |
| MachineInstr * | foldMemoryOperandImpl (MachineFunction &MF, MachineInstr *MI, unsigned OpNum, ArrayRef< MachineOperand > MOs, MachineBasicBlock::iterator InsertPt, unsigned Size, unsigned Alignment, bool AllowCommute) const |
| void | getUnconditionalBranch (MCInst &Branch, const MCSymbolRefExpr *BranchTarget) const override |
| void | getTrap (MCInst &MI) const override |
| unsigned | getJumpInstrTableEntryBound () const override |
| bool | isHighLatencyDef (int opc) const override |
| bool | hasHighOperandLatency (const TargetSchedModel &SchedModel, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const override |
| bool | useMachineCombiner () const override |
| bool | getMachineCombinerPatterns (MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern::MC_PATTERN > &P) const override |
| Return true when there is potentially a faster code sequence for an instruction chain ending in <Root>. More... | |
| void | genAlternativeCodeSequence (MachineInstr &Root, MachineCombinerPattern::MC_PATTERN P, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override |
| When getMachineCombinerPatterns() finds a pattern, this function generates the instructions that could replace the original code sequence. More... | |
| bool | analyzeCompare (const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const override |
| analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue. More... | |
| bool | optimizeCompareInstr (MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const override |
| optimizeCompareInstr - Check if there exists an earlier instruction that operates on the same source operands and sets flags in the same way as Compare; remove Compare if possible. More... | |
| MachineInstr * | optimizeLoadInstr (MachineInstr *MI, const MachineRegisterInfo *MRI, unsigned &FoldAsLoadDefReg, MachineInstr *&DefMI) const override |
| optimizeLoadInstr - Try to remove the load by folding it to a register operand at the use. More... | |
Static Public Member Functions | |
| static bool | isX86_64ExtendedReg (const MachineOperand &MO) |
Definition at line 154 of file X86InstrInfo.h.
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Definition at line 103 of file X86InstrInfo.cpp.
References TB_ALIGN_16, TB_ALIGN_32, TB_ALIGN_64, TB_ALIGN_NONE, TB_FOLDED_LOAD, TB_FOLDED_STORE, TB_INDEX_0, TB_INDEX_1, TB_INDEX_2, TB_INDEX_3, TB_INDEX_4, and TB_NO_REVERSE.
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Definition at line 3582 of file X86InstrInfo.cpp.
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Definition at line 3591 of file X86InstrInfo.cpp.
References llvm::X86::COND_E, llvm::X86::COND_NE, llvm::MachineOperand::CreateImm(), llvm::ilist_node< NodeTy >::getNextNode(), getRegisterInfo(), I, llvm::PPC::PRED_EQ, llvm::PPC::PRED_NE, llvm::MachineBasicBlock::rbegin(), llvm::MachineBasicBlock::rend(), llvm::SmallVectorTemplateCommon< T >::size(), and llvm::MachineBasicBlock::successors().
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analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue.
Return true if the comparison instruction can be analyzed.
Definition at line 4143 of file X86InstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::getReg().
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areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address.
It should only return true if the base pointers are the same and the only differences between the two addresses are the offset. It also returns the offsets by reference.
Definition at line 5769 of file X86InstrInfo.cpp.
References llvm::SDNode::getMachineOpcode(), llvm::SDNode::getOperand(), and llvm::SDNode::isMachineOpcode().
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Definition at line 5205 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::MachineInstr::addRegisterKilled(), llvm::BuildMI(), contains(), llvm::MCRegisterInfo::getSubReg(), llvm::X86Subtarget::hasAVX(), llvm::RegState::ImplicitDefine, llvm::AArch64CC::MI, and llvm::RegState::Undef.
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canFoldMemoryOperand - Returns true if the specified load / store is folding is possible.
Definition at line 5463 of file X86InstrInfo.cpp.
References llvm::TargetInstrInfo::canFoldMemoryOperand(), llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MCInstrDesc::getOperandConstraint(), llvm::MachineOperand::getTargetFlags(), llvm::X86II::MO_GOT_ABSOLUTE_ADDRESS, NoFusing, llvm::ArrayRef< T >::size(), and llvm::MCOI::TIED_TO.
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Definition at line 3729 of file X86InstrInfo.cpp.
References llvm::X86::COND_S, llvm::MachineBasicBlock::getParent(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::X86Subtarget::hasCMov(), and llvm::ArrayRef< T >::size().
| bool X86InstrInfo::classifyLEAReg | ( | MachineInstr * | MI, |
| const MachineOperand & | Src, | ||
| unsigned | LEAOpcode, | ||
| bool | AllowSP, | ||
| unsigned & | NewSrc, | ||
| bool & | isKill, | ||
| bool & | isUndef, | ||
| MachineOperand & | ImplicitOp | ||
| ) | const |
Given an operand within a MachineInstr, insert preceding code to put it into the right format for a particular kind of LEA instruction.
This may involve using an appropriate super-register instead (with an implicit use of the original) or creating a new virtual register and inserting COPY instructions to get the data into the right class.
Reference parameters are set to indicate how caller should add this operand to the LEA instruction.
Definition at line 2462 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addOperand(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineBasicBlock::computeRegisterLiveness(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::TargetOpcode::COPY, llvm::MachineRegisterInfo::createVirtualRegister(), llvm::RegState::Define, llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), getRegisterInfo(), llvm::getX86SubSuperRegister(), llvm::MVT::i64, llvm::MachineOperand::isKill(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineOperand::isUndef(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::MachineInstr::killsRegister(), llvm::MachineBasicBlock::LQR_Live, llvm::MachineBasicBlock::LQR_Unknown, llvm::AArch64CC::MI, llvm::MachineOperand::setImplicit(), and llvm::RegState::Undef.
Referenced by convertToThreeAddress().
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commuteInstruction - We have a few instructions that must be hacked on to commute them.
We have a few instructions that must be hacked on to commute them.
Definition at line 2920 of file X86InstrInfo.cpp.
References llvm::MachineFunction::CloneMachineInstr(), llvm::TargetInstrInfo::commuteInstruction(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm_unreachable, llvm::MachineInstr::setDesc(), and llvm::MachineOperand::setImm().
Referenced by foldMemoryOperandImpl().
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convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag.
This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag.
When this flag is set, the target may be able to convert a two-address instruction into a true three-address instruction on demand. This allows the X86 target (for example) to convert ADD and SHL instructions into LEA instructions if they would require register copies due to two-addressness.
This method returns a null pointer if the transformation cannot be performed, otherwise it returns the new instruction.
Definition at line 2653 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::addOffset(), llvm::MachineInstrBuilder::addOperand(), llvm::MachineInstrBuilder::addReg(), llvm::addRegReg(), llvm::BuildMI(), classifyLEAReg(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::MachineOperand::CreateReg(), llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getImm(), llvm::getKillRegState(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), getTruncatedShiftCount(), llvm::getUndefRegState(), hasLiveCondCodeDef(), llvm::X86Subtarget::is64Bit(), is64Bit(), llvm::MachineOperand::isDead(), llvm::MachineOperand::isKill(), isTruncatedShiftCountForLEA(), llvm::MachineOperand::isUndef(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::AArch64CC::MI, and llvm::LiveVariables::replaceKillInstruction().
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Definition at line 3860 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), contains(), copyPhysRegOpcode_AVX512(), CopyToFromAsymmetricReg(), llvm::dbgs(), DEBUG, llvm::getKillRegState(), llvm::X86Subtarget::hasAVX(), llvm::X86Subtarget::hasAVX512(), llvm::X86Subtarget::is64Bit(), isHReg(), and llvm_unreachable.
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Definition at line 4750 of file X86InstrInfo.cpp.
References Expand2AddrUndef(), expandLoadStackGuard(), llvm::X86Subtarget::hasAVX(), llvm::TargetOpcode::LOAD_STACK_GUARD, and llvm::AArch64CC::MI.
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Definition at line 3131 of file X86InstrInfo.cpp.
References llvm::TargetInstrInfo::findCommutedOpIndices(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), and llvm::MachineInstr::getOperand().
Referenced by foldMemoryOperandImpl().
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foldMemoryOperand - If this target supports it, fold a load or store of the specified stack slot into the specified machine instruction for the specified operand(s).
If this is possible, the target should perform the folding and return true, otherwise it should return false. If it folds the instruction, it is likely that the MachineInstruction the iterator references has been changed.
Definition at line 5230 of file X86InstrInfo.cpp.
References llvm::MachineOperand::ChangeToImmediate(), llvm::MachineOperand::CreateFI(), llvm::MachineFunction::getFrameInfo(), llvm::X86Subtarget::getFrameLowering(), llvm::MachineFunction::getFunction(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::TargetFrameLowering::getStackAlignment(), llvm::Function::hasFnAttribute(), hasPartialRegUpdate(), fuzzer::min(), llvm::X86RegisterInfo::needsStackRealignment(), NoFusing, llvm::Attribute::OptimizeForSize, llvm::MachineInstr::setDesc(), and llvm::ArrayRef< T >::size().
Referenced by foldMemoryOperandImpl().
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foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address, not just from a specific stack slot.
Definition at line 5330 of file X86InstrInfo.cpp.
References llvm::X86::AddrNumOperands, llvm::SmallVectorImpl< T >::append(), llvm::C, llvm::MachineOperand::ChangeToImmediate(), llvm::MachineOperand::CreateCPI(), llvm::MachineOperand::CreateImm(), llvm::MachineOperand::CreateReg(), foldMemoryOperandImpl(), llvm::ISD::FrameIndex, llvm::VectorType::get(), llvm::Constant::getAllOnesValue(), llvm::TargetMachine::getCodeModel(), llvm::MachineFunction::getConstantPool(), llvm::MachineConstantPool::getConstantPoolIndex(), llvm::Function::getContext(), llvm::MachineInstr::getDesc(), llvm::Type::getDoubleTy(), llvm::Type::getFloatTy(), llvm::MachineFunction::getFunction(), llvm::Type::getInt32Ty(), llvm::Constant::getNullValue(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::TargetMachine::getRelocationModel(), llvm::MachineOperand::getSubReg(), llvm::MachineFunction::getTarget(), llvm::Function::hasFnAttribute(), llvm::MachineInstr::hasOneMemOperand(), hasPartialRegUpdate(), llvm::X86Subtarget::is64Bit(), isLoadFromStackSlot(), isNonFoldablePartialRegisterLoad(), llvm::CodeModel::Kernel, llvm::MachineInstr::memoperands_begin(), NoFusing, llvm::MachineInstr::operands_begin(), llvm::Attribute::OptimizeForSize, llvm::Reloc::PIC_, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::MachineInstr::setDesc(), llvm::ArrayRef< T >::size(), and llvm::CodeModel::Small.
| MachineInstr * X86InstrInfo::foldMemoryOperandImpl | ( | MachineFunction & | MF, |
| MachineInstr * | MI, | ||
| unsigned | OpNum, | ||
| ArrayRef< MachineOperand > | MOs, | ||
| MachineBasicBlock::iterator | InsertPt, | ||
| unsigned | Size, | ||
| unsigned | Alignment, | ||
| bool | AllowCommute | ||
| ) | const |
Definition at line 4863 of file X86InstrInfo.cpp.
References llvm::X86Subtarget::callRegIndirect(), commuteInstruction(), llvm::dbgs(), llvm::DenseMapBase< DenseMap< KeyT, ValueT, KeyInfoT, BucketT >, KeyT, ValueT, KeyInfoT, BucketT >::end(), llvm::MachineInstr::eraseFromParent(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::find(), findCommutedOpIndices(), foldMemoryOperandImpl(), FuseInst(), FuseTwoAddrInst(), llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getNumDefs(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MCInstrDesc::getOperandConstraint(), llvm::MachineOperand::getReg(), getRegClass(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::getTargetFlags(), llvm::MachineInstr::isCopy(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineOperand::isReg(), MakeM0Inst(), llvm::AArch64CC::MI, llvm::MinAlign(), llvm::X86II::MO_GOT_ABSOLUTE_ADDRESS, PrintFailedFusing, llvm::MachineOperand::setReg(), llvm::MachineOperand::setSubReg(), TB_ALIGN_MASK, TB_ALIGN_SHIFT, and llvm::MCOI::TIED_TO.
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When getMachineCombinerPatterns() finds a pattern, this function generates the instructions that could replace the original code sequence.
Definition at line 6551 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::MachineCombinerPattern::MC_REASSOC_AX_BY, llvm::MachineCombinerPattern::MC_REASSOC_AX_YB, llvm::MachineCombinerPattern::MC_REASSOC_XA_BY, llvm::MachineCombinerPattern::MC_REASSOC_XA_YB, and reassociateOps().
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Definition at line 6209 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getDesc(), llvm::MachineInstr::getOpcode(), llvm::X86Subtarget::hasAVX2(), lookup(), lookupAVX2(), llvm::X86II::SSEDomainShift, and llvm::MCInstrDesc::TSFlags.
| unsigned X86InstrInfo::getGlobalBaseReg | ( | MachineFunction * | MF | ) | const |
getGlobalBaseReg - Return a virtual register initialized with the the global base register value.
Return a virtual register initialized with the the global base register value.
Output instructions required to initialize the register in the function entry block, if necessary.
Output instructions required to initialize the register in the function entry block, if necessary.
TODO: Eliminate this and move the code to X86MachineFunctionInfo.
Definition at line 6105 of file X86InstrInfo.cpp.
References llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MachineFunction::getInfo(), llvm::MachineFunction::getRegInfo(), llvm::PPCISD::GlobalBaseReg, and llvm::X86Subtarget::is64Bit().
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Definition at line 6259 of file X86InstrInfo.cpp.
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Return true when there is potentially a faster code sequence for an instruction chain ending in <Root>.
All potential patterns are output in the <Pattern> array.
Definition at line 6441 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getTarget(), isReassocCandidate(), llvm::MachineCombinerPattern::MC_REASSOC_AX_BY, llvm::MachineCombinerPattern::MC_REASSOC_AX_YB, llvm::MachineCombinerPattern::MC_REASSOC_XA_BY, llvm::MachineCombinerPattern::MC_REASSOC_XA_YB, llvm::TargetMachine::Options, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), and llvm::TargetOptions::UnsafeFPMath.
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Definition at line 4025 of file X86InstrInfo.cpp.
References llvm::X86::AddrBaseReg, llvm::X86::AddrDisp, llvm::X86::AddrIndexReg, llvm::X86::AddrScaleAmt, llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::X86II::getMemoryOperandNo(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::X86II::getOperandBias(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isImm(), and llvm::MCInstrDesc::TSFlags.
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Return the noop instruction to use for a noop.
Definition at line 6235 of file X86InstrInfo.cpp.
References llvm::MCInst::setOpcode().
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getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new instruction after load / store are unfolded from an instruction of the specified opcode.
It returns zero if the specified unfolding is not possible. If LoadRegIndex is non-null, it is filled in with the operand index of the operand which will hold the register holding the loaded value.
Definition at line 5750 of file X86InstrInfo.cpp.
References llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::end(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::find(), TB_FOLDED_LOAD, TB_FOLDED_STORE, and TB_INDEX_MASK.
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Inform the ExeDepsFix pass how many idle instructions we would like before a partial register update.
Definition at line 5094 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), hasPartialRegUpdate(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::MachineOperand::readsReg(), llvm::MachineInstr::readsRegister(), and llvm::MachineInstr::readsVirtualRegister().
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getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
As such, whenever a client has an instance of instruction info, it should always be able to get register info as well (through this method).
Definition at line 195 of file X86InstrInfo.h.
Referenced by AnalyzeBranchPredicate(), classifyLEAReg(), llvm::X86Subtarget::getRegisterInfo(), and optimizeCompareInstr().
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getSPAdjust - This returns the stack pointer adjustment made by this instruction.
For x86, we need to handle more complex call sequences involving PUSHes.
Definition at line 2055 of file X86InstrInfo.cpp.
References llvm::MachineBasicBlock::end(), llvm::TargetSubtargetInfo::getFrameLowering(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::TargetFrameLowering::getStackAlignment(), llvm::MachineFunction::getSubtarget(), I, and llvm::MachineInstr::isCall().
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Definition at line 6253 of file X86InstrInfo.cpp.
References llvm::MCInst::setOpcode(), and llvm::ISD::TRAP.
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Definition at line 6243 of file X86InstrInfo.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createExpr(), and llvm::MCInst::setOpcode().
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Inform the ExeDepsFix pass how many idle instructions we would like before certain undef register reads.
This catches the VCVTSI2SD family of instructions:
vcvtsi2sdq rax, xmm0<undef>, xmm14
We should to be careful not to catch VXOR idioms which are presumably handled specially in the pipeline:
vxorps xmm1<undef>, xmm1<undef>, xmm1
Like getPartialRegUpdateClearance, this makes a strong assumption that the high bits that are passed-through are not live.
Definition at line 5188 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), hasUndefRegUpdate(), llvm::TargetRegisterInfo::isPhysicalRegister(), and llvm::MachineOperand::isUndef().
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Definition at line 6343 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), and isHighLatencyDef().
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Definition at line 3681 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addMBB(), llvm::BuildMI(), llvm::X86::COND_NE_OR_P, llvm::X86::COND_NP_OR_E, llvm::ArrayRef< T >::empty(), GetCondBranchFromCond(), and llvm::ArrayRef< T >::size().
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Definition at line 3765 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::X86::getCMovFromCond(), llvm::MachineBasicBlock::getParent(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::TargetRegisterClass::getSize(), and llvm::ArrayRef< T >::size().
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isCoalescableExtInstr - Return true if the instruction is a "coalescable" extension instruction.
That is, it's like a copy where it's legal for the source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns true, then it's expected the pre-extension value is available as a subreg of the result register. This also returns the sub-register index in SubIdx.
Definition at line 2008 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::X86Subtarget::is64Bit(), and llvm_unreachable.
Definition at line 6265 of file X86InstrInfo.cpp.
Referenced by hasHighOperandLatency().
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Definition at line 2191 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), and isFrameLoadOpcode().
Referenced by foldMemoryOperandImpl(), isLoadFromStackSlotPostFE(), and MatchingStackOffset().
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isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well.
This uses a heuristic so it isn't reliable for correctness.
Definition at line 2199 of file X86InstrInfo.cpp.
References llvm::NVPTXISD::Dummy, llvm::MachineInstr::getOpcode(), isFrameLoadOpcode(), and isLoadFromStackSlot().
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Definition at line 2252 of file X86InstrInfo.cpp.
References llvm::X86::AddrBaseReg, llvm::X86::AddrDisp, llvm::X86::AddrIndexReg, llvm::X86::AddrScaleAmt, llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineOperand::isGlobal(), llvm::MachineOperand::isImm(), llvm::MachineInstr::isInvariantLoad(), llvm::MachineOperand::isReg(), regIsPICBase(), and ReMatPICStubLoad.
| bool X86InstrInfo::isSafeToClobberEFLAGS | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | I | ||
| ) | const |
isSafeToClobberEFLAGS - Return true if it's safe insert an instruction tha would clobber the EFLAGS condition register.
Note the result may be conservative. If it cannot definitely determine the safety after visiting a few instructions in each direction it assumes it's not safe.
Definition at line 2331 of file X86InstrInfo.cpp.
References llvm::MachineBasicBlock::begin(), llvm::MachineOperand::clobbersPhysReg(), llvm::MachineBasicBlock::end(), llvm::MachineOperand::getReg(), I, llvm::MachineOperand::isDead(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isKill(), llvm::MachineBasicBlock::isLiveIn(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isRegMask(), llvm::MachineOperand::isUse(), llvm::SI, llvm::MachineBasicBlock::succ_begin(), and llvm::MachineBasicBlock::succ_end().
Referenced by reMaterialize().
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isSafeToMoveRegClassDefs - Return true if it's safe to move a machine instruction that defines the specified register class.
Definition at line 6092 of file X86InstrInfo.cpp.
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Definition at line 2212 of file X86InstrInfo.cpp.
References llvm::X86::AddrNumOperands, llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), and isFrameStoreOpcode().
Referenced by isStoreToStackSlotPostFE().
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isStoreToStackSlotPostFE - Check for post-frame ptr elimination stack locations as well.
This uses a heuristic so it isn't reliable for correctness.
Definition at line 2221 of file X86InstrInfo.cpp.
References llvm::NVPTXISD::Dummy, llvm::MachineInstr::getOpcode(), isFrameStoreOpcode(), and isStoreToStackSlot().
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Definition at line 3425 of file X86InstrInfo.cpp.
References llvm::MachineInstr::isBarrier(), llvm::MachineInstr::isBranch(), llvm::MachineInstr::isPredicable(), llvm::HexagonMCInstrInfo::isPredicated(), and llvm::MachineInstr::isTerminator().
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Definition at line 409 of file X86InstrInfo.h.
References llvm::MachineOperand::getReg(), llvm::MachineOperand::isReg(), and llvm::X86II::isX86_64ExtendedReg().
| void X86InstrInfo::loadRegFromAddr | ( | MachineFunction & | MF, |
| unsigned | DestReg, | ||
| SmallVectorImpl< MachineOperand > & | Addr, | ||
| const TargetRegisterClass * | RC, | ||
| MachineInstr::mmo_iterator | MMOBegin, | ||
| MachineInstr::mmo_iterator | MMOEnd, | ||
| SmallVectorImpl< MachineInstr * > & | NewMIs | ||
| ) | const |
Definition at line 4124 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addOperand(), llvm::BuildMI(), llvm::DL, llvm::MachineMemOperand::getAlignment(), getLoadRegOpcode(), llvm::TargetRegisterClass::getSize(), llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::MachineInstrBuilder::setMemRefs(), and llvm::SmallVectorTemplateCommon< T >::size().
Referenced by unfoldMemoryOperand().
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Definition at line 4109 of file X86InstrInfo.cpp.
References llvm::addFrameReference(), llvm::BuildMI(), llvm::X86RegisterInfo::canRealignStack(), llvm::DL, llvm::MachineBasicBlock::findDebugLoc(), llvm::X86Subtarget::getFrameLowering(), getLoadRegOpcode(), llvm::MachineBasicBlock::getParent(), llvm::TargetRegisterClass::getSize(), and llvm::TargetFrameLowering::getStackAlignment().
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optimizeCompareInstr - Check if there exists an earlier instruction that operates on the same source operands and sets flags in the same way as Compare; remove Compare if possible.
Check if there exists an earlier instruction that operates on the same source operands and sets flags in the same way as Compare; remove Compare if possible.
Definition at line 4366 of file X86InstrInfo.cpp.
References llvm::X86::COND_A, llvm::X86::COND_AE, llvm::X86::COND_B, llvm::X86::COND_BE, llvm::X86::COND_E, llvm::X86::COND_G, llvm::X86::COND_GE, llvm::X86::COND_INVALID, llvm::X86::COND_L, llvm::X86::COND_LE, llvm::X86::COND_NE, llvm::X86::COND_NO, llvm::X86::COND_O, llvm::tgtok::Def, llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), llvm::X86::getCMovFromCond(), GetCondBranchFromCond(), getCondFromBranchOpc(), llvm::X86::getCondFromCMovOpc(), getCondFromSETOpc(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), GetOppositeBranchCondition(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), getRegisterInfo(), llvm::X86::getSETFromCond(), llvm::TargetRegisterClass::getSize(), getSwappedCondition(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::MachineInstr::hasOneMemOperand(), I, llvm::MachineBasicBlock::insert(), llvm::MachineInstr::isBranch(), llvm::MachineOperand::isDef(), isDefConvertible(), isRedundantFlagInstr(), llvm::MachineOperand::isReg(), isUseDefConvertible(), llvm::MachineInstr::killsRegister(), llvm_unreachable, llvm::AArch64CC::MI, llvm::MachineInstr::modifiesRegister(), llvm::MachineInstr::readsRegister(), llvm::MachineInstr::registerDefIsDead(), llvm::MachineBasicBlock::remove(), llvm::MachineInstr::RemoveOperand(), llvm::MachineBasicBlock::rend(), llvm::MachineInstr::setDesc(), llvm::MachineOperand::setIsDead(), llvm::SI, llvm::MachineBasicBlock::succ_begin(), llvm::MachineBasicBlock::succ_end(), and llvm::MachineRegisterInfo::use_nodbg_empty().
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optimizeLoadInstr - Try to remove the load by folding it to a register operand at the use.
Try to remove the load by folding it to a register operand at the use.
We fold the load instructions if and only if the def and use are in the same BB. We only look at one load and see whether it can be folded into MI. FoldAsLoadDefReg is the virtual register defined by the load we are trying to fold. DefMI returns the machine instruction that defines FoldAsLoadDefReg, and the function returns the machine instruction generated due to folding.
We fold the load instructions if load defines a virtual register, the virtual register is used once in the same BB, and the instructions in-between do not load or store, and have no side effects.
Definition at line 4657 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineRegisterInfo::getVRegDef(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isReg(), llvm::MachineInstr::isSafeToMove(), llvm::MachineInstr::mayLoad(), and SawStore.
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Definition at line 2409 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addOperand(), llvm::BuildMI(), llvm::MachineFunction::CloneMachineInstr(), llvm::DL, llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineBasicBlock::insert(), isSafeToClobberEFLAGS(), and llvm::MachineInstr::substituteRegister().
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Definition at line 3660 of file X86InstrInfo.cpp.
References llvm::MachineBasicBlock::begin(), llvm::X86::COND_INVALID, llvm::MachineBasicBlock::end(), getCondFromBranchOpc(), and I.
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Definition at line 6082 of file X86InstrInfo.cpp.
References llvm::X86::COND_NE_OR_P, llvm::X86::COND_NP_OR_E, GetOppositeBranchCondition(), and llvm::SmallVectorTemplateCommon< T >::size().
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Definition at line 6220 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getDesc(), llvm::MachineInstr::getOpcode(), llvm::X86Subtarget::hasAVX2(), lookup(), lookupAVX2(), llvm::MachineInstr::setDesc(), llvm::X86II::SSEDomainShift, and llvm::MCInstrDesc::TSFlags.
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Definition at line 5922 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), and llvm::X86Subtarget::hasAVX().
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shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePtr) if two loads should be scheduled togther.
On some targets if two loads are loading from addresses in the same cache line, it's better if they are scheduled together. This function takes two integers that represent the load offsets from the common base address. It returns true if it decides it's desirable to schedule the two loads together. "NumLoads" is the number of loads that have already been scheduled after Load1.
Definition at line 5874 of file X86InstrInfo.cpp.
References llvm::MVT::f32, llvm::MVT::f64, llvm::SDNode::getMachineOpcode(), llvm::EVT::getSimpleVT(), llvm::SDNode::getValueType(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::X86Subtarget::is64Bit(), and llvm::MVT::SimpleTy.
| void X86InstrInfo::storeRegToAddr | ( | MachineFunction & | MF, |
| unsigned | SrcReg, | ||
| bool | isKill, | ||
| SmallVectorImpl< MachineOperand > & | Addr, | ||
| const TargetRegisterClass * | RC, | ||
| MachineInstr::mmo_iterator | MMOBegin, | ||
| MachineInstr::mmo_iterator | MMOEnd, | ||
| SmallVectorImpl< MachineInstr * > & | NewMIs | ||
| ) | const |
Definition at line 4088 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addOperand(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::DL, llvm::MachineMemOperand::getAlignment(), llvm::getKillRegState(), llvm::TargetRegisterClass::getSize(), getStoreRegOpcode(), llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::MachineInstrBuilder::setMemRefs(), and llvm::SmallVectorTemplateCommon< T >::size().
Referenced by unfoldMemoryOperand().
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Definition at line 4070 of file X86InstrInfo.cpp.
References llvm::addFrameReference(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::X86RegisterInfo::canRealignStack(), llvm::DL, llvm::MachineBasicBlock::findDebugLoc(), llvm::MachineFunction::getFrameInfo(), llvm::X86Subtarget::getFrameLowering(), llvm::getKillRegState(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), llvm::TargetRegisterClass::getSize(), llvm::TargetFrameLowering::getStackAlignment(), and getStoreRegOpcode().
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unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a store into two or more instruction.
If this is possible, returns true as well as the new instructions by reference.
Definition at line 5519 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addOperand(), llvm::MachineInstrBuilder::addReg(), llvm::X86::AddrNumOperands, llvm::MachineOperand::ChangeToRegister(), llvm::MachineFunction::CreateMachineInstr(), llvm::RegState::Define, llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::end(), llvm::MachineFunction::extractLoadMemRefs(), llvm::MachineFunction::extractStoreMemRefs(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::find(), llvm::getDeadRegState(), llvm::MachineInstr::getDebugLoc(), llvm::getDefRegState(), llvm::MachineOperand::getImm(), llvm::getKillRegState(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), getRegClass(), llvm::getUndefRegState(), llvm::MachineInstr::hasOneMemOperand(), llvm::RegState::Implicit, llvm::MachineOperand::isDead(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isImplicit(), llvm::MachineOperand::isKill(), llvm::MachineOperand::isReg(), llvm::X86Subtarget::isUnalignedMemAccessFast(), llvm::MachineOperand::isUndef(), llvm_unreachable, loadRegFromAddr(), llvm::MachineInstr::memoperands_begin(), llvm::MachineInstr::memoperands_end(), llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::MachineInstr::setDesc(), llvm::MachineOperand::setIsKill(), llvm::SmallVectorTemplateCommon< T >::size(), storeRegToAddr(), TB_FOLDED_LOAD, TB_FOLDED_STORE, and TB_INDEX_MASK.
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Definition at line 5645 of file X86InstrInfo.cpp.
References llvm::X86::AddrNumOperands, llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::end(), llvm::MachineFunction::extractLoadMemRefs(), llvm::MachineFunction::extractStoreMemRefs(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::find(), getLoadRegOpcode(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getMachineNode(), llvm::SDNode::getMachineOpcode(), llvm::MCInstrDesc::getNumDefs(), llvm::SDNode::getNumOperands(), llvm::SDNode::getNumValues(), llvm::SDNode::getOperand(), getRegClass(), llvm::TargetRegisterClass::getSize(), getStoreRegOpcode(), llvm::SDNode::getValueType(), llvm::SDNode::isMachineOpcode(), llvm::X86Subtarget::isUnalignedMemAccessFast(), llvm::SPII::Load, llvm::MCInstrDesc::NumDefs, llvm::MVT::Other, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::SPII::Store, TB_FOLDED_LOAD, TB_FOLDED_STORE, TB_INDEX_MASK, and llvm::TargetRegisterClass::vt_begin().
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Definition at line 457 of file X86InstrInfo.h.
1.8.6