LLVM  3.7.0
X86AsmBackend.cpp
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1 //===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
12 #include "llvm/ADT/StringSwitch.h"
13 #include "llvm/MC/MCAsmBackend.h"
15 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCObjectWriter.h"
20 #include "llvm/MC/MCRegisterInfo.h"
21 #include "llvm/MC/MCSectionCOFF.h"
22 #include "llvm/MC/MCSectionELF.h"
23 #include "llvm/MC/MCSectionMachO.h"
25 #include "llvm/Support/ELF.h"
27 #include "llvm/Support/MachO.h"
30 using namespace llvm;
31 
32 static unsigned getFixupKindLog2Size(unsigned Kind) {
33  switch (Kind) {
34  default:
35  llvm_unreachable("invalid fixup kind!");
36  case FK_PCRel_1:
37  case FK_SecRel_1:
38  case FK_Data_1:
39  return 0;
40  case FK_PCRel_2:
41  case FK_SecRel_2:
42  case FK_Data_2:
43  return 1;
44  case FK_PCRel_4:
49  case FK_SecRel_4:
50  case FK_Data_4:
51  return 2;
52  case FK_PCRel_8:
53  case FK_SecRel_8:
54  case FK_Data_8:
56  return 3;
57  }
58 }
59 
60 namespace {
61 
62 class X86ELFObjectWriter : public MCELFObjectTargetWriter {
63 public:
64  X86ELFObjectWriter(bool is64Bit, uint8_t OSABI, uint16_t EMachine,
65  bool HasRelocationAddend, bool foobar)
66  : MCELFObjectTargetWriter(is64Bit, OSABI, EMachine, HasRelocationAddend) {}
67 };
68 
69 class X86AsmBackend : public MCAsmBackend {
70  const StringRef CPU;
71  bool HasNopl;
72  const uint64_t MaxNopLength;
73 public:
74  X86AsmBackend(const Target &T, StringRef CPU)
75  : MCAsmBackend(), CPU(CPU), MaxNopLength(CPU == "slm" ? 7 : 15) {
76  HasNopl = CPU != "generic" && CPU != "i386" && CPU != "i486" &&
77  CPU != "i586" && CPU != "pentium" && CPU != "pentium-mmx" &&
78  CPU != "i686" && CPU != "k6" && CPU != "k6-2" && CPU != "k6-3" &&
79  CPU != "geode" && CPU != "winchip-c6" && CPU != "winchip2" &&
80  CPU != "c3" && CPU != "c3-2";
81  }
82 
83  unsigned getNumFixupKinds() const override {
85  }
86 
87  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
88  const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = {
89  { "reloc_riprel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
90  { "reloc_riprel_4byte_movq_load", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel},
91  { "reloc_signed_4byte", 0, 4 * 8, 0},
92  { "reloc_global_offset_table", 0, 4 * 8, 0}
93  };
94 
95  if (Kind < FirstTargetFixupKind)
96  return MCAsmBackend::getFixupKindInfo(Kind);
97 
98  assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
99  "Invalid kind!");
100  return Infos[Kind - FirstTargetFixupKind];
101  }
102 
103  void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
104  uint64_t Value, bool IsPCRel) const override {
105  unsigned Size = 1 << getFixupKindLog2Size(Fixup.getKind());
106 
107  assert(Fixup.getOffset() + Size <= DataSize &&
108  "Invalid fixup offset!");
109 
110  // Check that uppper bits are either all zeros or all ones.
111  // Specifically ignore overflow/underflow as long as the leakage is
112  // limited to the lower bits. This is to remain compatible with
113  // other assemblers.
114  assert(isIntN(Size * 8 + 1, Value) &&
115  "Value does not fit in the Fixup field");
116 
117  for (unsigned i = 0; i != Size; ++i)
118  Data[Fixup.getOffset() + i] = uint8_t(Value >> (i * 8));
119  }
120 
121  bool mayNeedRelaxation(const MCInst &Inst) const override;
122 
123  bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
124  const MCRelaxableFragment *DF,
125  const MCAsmLayout &Layout) const override;
126 
127  void relaxInstruction(const MCInst &Inst, MCInst &Res) const override;
128 
129  bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
130 };
131 } // end anonymous namespace
132 
133 static unsigned getRelaxedOpcodeBranch(unsigned Op) {
134  switch (Op) {
135  default:
136  return Op;
137 
138  case X86::JAE_1: return X86::JAE_4;
139  case X86::JA_1: return X86::JA_4;
140  case X86::JBE_1: return X86::JBE_4;
141  case X86::JB_1: return X86::JB_4;
142  case X86::JE_1: return X86::JE_4;
143  case X86::JGE_1: return X86::JGE_4;
144  case X86::JG_1: return X86::JG_4;
145  case X86::JLE_1: return X86::JLE_4;
146  case X86::JL_1: return X86::JL_4;
147  case X86::JMP_1: return X86::JMP_4;
148  case X86::JNE_1: return X86::JNE_4;
149  case X86::JNO_1: return X86::JNO_4;
150  case X86::JNP_1: return X86::JNP_4;
151  case X86::JNS_1: return X86::JNS_4;
152  case X86::JO_1: return X86::JO_4;
153  case X86::JP_1: return X86::JP_4;
154  case X86::JS_1: return X86::JS_4;
155  }
156 }
157 
158 static unsigned getRelaxedOpcodeArith(unsigned Op) {
159  switch (Op) {
160  default:
161  return Op;
162 
163  // IMUL
164  case X86::IMUL16rri8: return X86::IMUL16rri;
165  case X86::IMUL16rmi8: return X86::IMUL16rmi;
166  case X86::IMUL32rri8: return X86::IMUL32rri;
167  case X86::IMUL32rmi8: return X86::IMUL32rmi;
168  case X86::IMUL64rri8: return X86::IMUL64rri32;
169  case X86::IMUL64rmi8: return X86::IMUL64rmi32;
170 
171  // AND
172  case X86::AND16ri8: return X86::AND16ri;
173  case X86::AND16mi8: return X86::AND16mi;
174  case X86::AND32ri8: return X86::AND32ri;
175  case X86::AND32mi8: return X86::AND32mi;
176  case X86::AND64ri8: return X86::AND64ri32;
177  case X86::AND64mi8: return X86::AND64mi32;
178 
179  // OR
180  case X86::OR16ri8: return X86::OR16ri;
181  case X86::OR16mi8: return X86::OR16mi;
182  case X86::OR32ri8: return X86::OR32ri;
183  case X86::OR32mi8: return X86::OR32mi;
184  case X86::OR64ri8: return X86::OR64ri32;
185  case X86::OR64mi8: return X86::OR64mi32;
186 
187  // XOR
188  case X86::XOR16ri8: return X86::XOR16ri;
189  case X86::XOR16mi8: return X86::XOR16mi;
190  case X86::XOR32ri8: return X86::XOR32ri;
191  case X86::XOR32mi8: return X86::XOR32mi;
192  case X86::XOR64ri8: return X86::XOR64ri32;
193  case X86::XOR64mi8: return X86::XOR64mi32;
194 
195  // ADD
196  case X86::ADD16ri8: return X86::ADD16ri;
197  case X86::ADD16mi8: return X86::ADD16mi;
198  case X86::ADD32ri8: return X86::ADD32ri;
199  case X86::ADD32mi8: return X86::ADD32mi;
200  case X86::ADD64ri8: return X86::ADD64ri32;
201  case X86::ADD64mi8: return X86::ADD64mi32;
202 
203  // SUB
204  case X86::SUB16ri8: return X86::SUB16ri;
205  case X86::SUB16mi8: return X86::SUB16mi;
206  case X86::SUB32ri8: return X86::SUB32ri;
207  case X86::SUB32mi8: return X86::SUB32mi;
208  case X86::SUB64ri8: return X86::SUB64ri32;
209  case X86::SUB64mi8: return X86::SUB64mi32;
210 
211  // CMP
212  case X86::CMP16ri8: return X86::CMP16ri;
213  case X86::CMP16mi8: return X86::CMP16mi;
214  case X86::CMP32ri8: return X86::CMP32ri;
215  case X86::CMP32mi8: return X86::CMP32mi;
216  case X86::CMP64ri8: return X86::CMP64ri32;
217  case X86::CMP64mi8: return X86::CMP64mi32;
218 
219  // PUSH
220  case X86::PUSH32i8: return X86::PUSHi32;
221  case X86::PUSH16i8: return X86::PUSHi16;
222  case X86::PUSH64i8: return X86::PUSH64i32;
223  }
224 }
225 
226 static unsigned getRelaxedOpcode(unsigned Op) {
227  unsigned R = getRelaxedOpcodeArith(Op);
228  if (R != Op)
229  return R;
230  return getRelaxedOpcodeBranch(Op);
231 }
232 
233 bool X86AsmBackend::mayNeedRelaxation(const MCInst &Inst) const {
234  // Branches can always be relaxed.
235  if (getRelaxedOpcodeBranch(Inst.getOpcode()) != Inst.getOpcode())
236  return true;
237 
238  // Check if this instruction is ever relaxable.
239  if (getRelaxedOpcodeArith(Inst.getOpcode()) == Inst.getOpcode())
240  return false;
241 
242 
243  // Check if the relaxable operand has an expression. For the current set of
244  // relaxable instructions, the relaxable operand is always the last operand.
245  unsigned RelaxableOp = Inst.getNumOperands() - 1;
246  if (Inst.getOperand(RelaxableOp).isExpr())
247  return true;
248 
249  return false;
250 }
251 
252 bool X86AsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
253  uint64_t Value,
254  const MCRelaxableFragment *DF,
255  const MCAsmLayout &Layout) const {
256  // Relax if the value is too big for a (signed) i8.
257  return int64_t(Value) != int64_t(int8_t(Value));
258 }
259 
260 // FIXME: Can tblgen help at all here to verify there aren't other instructions
261 // we can relax?
262 void X86AsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const {
263  // The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel.
264  unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
265 
266  if (RelaxedOp == Inst.getOpcode()) {
267  SmallString<256> Tmp;
268  raw_svector_ostream OS(Tmp);
269  Inst.dump_pretty(OS);
270  OS << "\n";
271  report_fatal_error("unexpected instruction to relax: " + OS.str());
272  }
273 
274  Res = Inst;
275  Res.setOpcode(RelaxedOp);
276 }
277 
278 /// \brief Write a sequence of optimal nops to the output, covering \p Count
279 /// bytes.
280 /// \return - true on success, false on failure
281 bool X86AsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
282  static const uint8_t Nops[10][10] = {
283  // nop
284  {0x90},
285  // xchg %ax,%ax
286  {0x66, 0x90},
287  // nopl (%[re]ax)
288  {0x0f, 0x1f, 0x00},
289  // nopl 0(%[re]ax)
290  {0x0f, 0x1f, 0x40, 0x00},
291  // nopl 0(%[re]ax,%[re]ax,1)
292  {0x0f, 0x1f, 0x44, 0x00, 0x00},
293  // nopw 0(%[re]ax,%[re]ax,1)
294  {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
295  // nopl 0L(%[re]ax)
296  {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
297  // nopl 0L(%[re]ax,%[re]ax,1)
298  {0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
299  // nopw 0L(%[re]ax,%[re]ax,1)
300  {0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
301  // nopw %cs:0L(%[re]ax,%[re]ax,1)
302  {0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
303  };
304 
305  // This CPU doesn't support long nops. If needed add more.
306  // FIXME: Can we get this from the subtarget somehow?
307  // FIXME: We could generated something better than plain 0x90.
308  if (!HasNopl) {
309  for (uint64_t i = 0; i < Count; ++i)
310  OW->write8(0x90);
311  return true;
312  }
313 
314  // 15 is the longest single nop instruction. Emit as many 15-byte nops as
315  // needed, then emit a nop of the remaining length.
316  do {
317  const uint8_t ThisNopLength = (uint8_t) std::min(Count, MaxNopLength);
318  const uint8_t Prefixes = ThisNopLength <= 10 ? 0 : ThisNopLength - 10;
319  for (uint8_t i = 0; i < Prefixes; i++)
320  OW->write8(0x66);
321  const uint8_t Rest = ThisNopLength - Prefixes;
322  for (uint8_t i = 0; i < Rest; i++)
323  OW->write8(Nops[Rest - 1][i]);
324  Count -= ThisNopLength;
325  } while (Count != 0);
326 
327  return true;
328 }
329 
330 /* *** */
331 
332 namespace {
333 
334 class ELFX86AsmBackend : public X86AsmBackend {
335 public:
336  uint8_t OSABI;
337  ELFX86AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
338  : X86AsmBackend(T, CPU), OSABI(OSABI) {}
339 };
340 
341 class ELFX86_32AsmBackend : public ELFX86AsmBackend {
342 public:
343  ELFX86_32AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
344  : ELFX86AsmBackend(T, OSABI, CPU) {}
345 
346  MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
347  return createX86ELFObjectWriter(OS, /*IsELF64*/ false, OSABI, ELF::EM_386);
348  }
349 };
350 
351 class ELFX86_X32AsmBackend : public ELFX86AsmBackend {
352 public:
353  ELFX86_X32AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
354  : ELFX86AsmBackend(T, OSABI, CPU) {}
355 
356  MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
357  return createX86ELFObjectWriter(OS, /*IsELF64*/ false, OSABI,
359  }
360 };
361 
362 class ELFX86_64AsmBackend : public ELFX86AsmBackend {
363 public:
364  ELFX86_64AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
365  : ELFX86AsmBackend(T, OSABI, CPU) {}
366 
367  MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
368  return createX86ELFObjectWriter(OS, /*IsELF64*/ true, OSABI, ELF::EM_X86_64);
369  }
370 };
371 
372 class WindowsX86AsmBackend : public X86AsmBackend {
373  bool Is64Bit;
374 
375 public:
376  WindowsX86AsmBackend(const Target &T, bool is64Bit, StringRef CPU)
377  : X86AsmBackend(T, CPU)
378  , Is64Bit(is64Bit) {
379  }
380 
381  MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
382  return createX86WinCOFFObjectWriter(OS, Is64Bit);
383  }
384 };
385 
386 namespace CU {
387 
388  /// Compact unwind encoding values.
390  /// [RE]BP based frame where [RE]BP is pused on the stack immediately after
391  /// the return address, then [RE]SP is moved to [RE]BP.
392  UNWIND_MODE_BP_FRAME = 0x01000000,
393 
394  /// A frameless function with a small constant stack size.
395  UNWIND_MODE_STACK_IMMD = 0x02000000,
396 
397  /// A frameless function with a large constant stack size.
398  UNWIND_MODE_STACK_IND = 0x03000000,
399 
400  /// No compact unwind encoding is available.
401  UNWIND_MODE_DWARF = 0x04000000,
402 
403  /// Mask for encoding the frame registers.
404  UNWIND_BP_FRAME_REGISTERS = 0x00007FFF,
405 
406  /// Mask for encoding the frameless registers.
407  UNWIND_FRAMELESS_STACK_REG_PERMUTATION = 0x000003FF
408  };
409 
410 } // end CU namespace
411 
412 class DarwinX86AsmBackend : public X86AsmBackend {
413  const MCRegisterInfo &MRI;
414 
415  /// \brief Number of registers that can be saved in a compact unwind encoding.
416  enum { CU_NUM_SAVED_REGS = 6 };
417 
418  mutable unsigned SavedRegs[CU_NUM_SAVED_REGS];
419  bool Is64Bit;
420 
421  unsigned OffsetSize; ///< Offset of a "push" instruction.
422  unsigned MoveInstrSize; ///< Size of a "move" instruction.
423  unsigned StackDivide; ///< Amount to adjust stack size by.
424 protected:
425  /// \brief Size of a "push" instruction for the given register.
426  unsigned PushInstrSize(unsigned Reg) const {
427  switch (Reg) {
428  case X86::EBX:
429  case X86::ECX:
430  case X86::EDX:
431  case X86::EDI:
432  case X86::ESI:
433  case X86::EBP:
434  case X86::RBX:
435  case X86::RBP:
436  return 1;
437  case X86::R12:
438  case X86::R13:
439  case X86::R14:
440  case X86::R15:
441  return 2;
442  }
443  return 1;
444  }
445 
446  /// \brief Implementation of algorithm to generate the compact unwind encoding
447  /// for the CFI instructions.
448  uint32_t
449  generateCompactUnwindEncodingImpl(ArrayRef<MCCFIInstruction> Instrs) const {
450  if (Instrs.empty()) return 0;
451 
452  // Reset the saved registers.
453  unsigned SavedRegIdx = 0;
454  memset(SavedRegs, 0, sizeof(SavedRegs));
455 
456  bool HasFP = false;
457 
458  // Encode that we are using EBP/RBP as the frame pointer.
459  uint32_t CompactUnwindEncoding = 0;
460 
461  unsigned SubtractInstrIdx = Is64Bit ? 3 : 2;
462  unsigned InstrOffset = 0;
463  unsigned StackAdjust = 0;
464  unsigned StackSize = 0;
465  unsigned PrevStackSize = 0;
466  unsigned NumDefCFAOffsets = 0;
467 
468  for (unsigned i = 0, e = Instrs.size(); i != e; ++i) {
469  const MCCFIInstruction &Inst = Instrs[i];
470 
471  switch (Inst.getOperation()) {
472  default:
473  // Any other CFI directives indicate a frame that we aren't prepared
474  // to represent via compact unwind, so just bail out.
475  return 0;
477  // Defines a frame pointer. E.g.
478  //
479  // movq %rsp, %rbp
480  // L0:
481  // .cfi_def_cfa_register %rbp
482  //
483  HasFP = true;
484  assert(MRI.getLLVMRegNum(Inst.getRegister(), true) ==
485  (Is64Bit ? X86::RBP : X86::EBP) && "Invalid frame pointer!");
486 
487  // Reset the counts.
488  memset(SavedRegs, 0, sizeof(SavedRegs));
489  StackAdjust = 0;
490  SavedRegIdx = 0;
491  InstrOffset += MoveInstrSize;
492  break;
493  }
495  // Defines a new offset for the CFA. E.g.
496  //
497  // With frame:
498  //
499  // pushq %rbp
500  // L0:
501  // .cfi_def_cfa_offset 16
502  //
503  // Without frame:
504  //
505  // subq $72, %rsp
506  // L0:
507  // .cfi_def_cfa_offset 80
508  //
509  PrevStackSize = StackSize;
510  StackSize = std::abs(Inst.getOffset()) / StackDivide;
511  ++NumDefCFAOffsets;
512  break;
513  }
515  // Defines a "push" of a callee-saved register. E.g.
516  //
517  // pushq %r15
518  // pushq %r14
519  // pushq %rbx
520  // L0:
521  // subq $120, %rsp
522  // L1:
523  // .cfi_offset %rbx, -40
524  // .cfi_offset %r14, -32
525  // .cfi_offset %r15, -24
526  //
527  if (SavedRegIdx == CU_NUM_SAVED_REGS)
528  // If there are too many saved registers, we cannot use a compact
529  // unwind encoding.
530  return CU::UNWIND_MODE_DWARF;
531 
532  unsigned Reg = MRI.getLLVMRegNum(Inst.getRegister(), true);
533  SavedRegs[SavedRegIdx++] = Reg;
534  StackAdjust += OffsetSize;
535  InstrOffset += PushInstrSize(Reg);
536  break;
537  }
538  }
539  }
540 
541  StackAdjust /= StackDivide;
542 
543  if (HasFP) {
544  if ((StackAdjust & 0xFF) != StackAdjust)
545  // Offset was too big for a compact unwind encoding.
546  return CU::UNWIND_MODE_DWARF;
547 
548  // Get the encoding of the saved registers when we have a frame pointer.
549  uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame();
550  if (RegEnc == ~0U) return CU::UNWIND_MODE_DWARF;
551 
552  CompactUnwindEncoding |= CU::UNWIND_MODE_BP_FRAME;
553  CompactUnwindEncoding |= (StackAdjust & 0xFF) << 16;
554  CompactUnwindEncoding |= RegEnc & CU::UNWIND_BP_FRAME_REGISTERS;
555  } else {
556  // If the amount of the stack allocation is the size of a register, then
557  // we "push" the RAX/EAX register onto the stack instead of adjusting the
558  // stack pointer with a SUB instruction. We don't support the push of the
559  // RAX/EAX register with compact unwind. So we check for that situation
560  // here.
561  if ((NumDefCFAOffsets == SavedRegIdx + 1 &&
562  StackSize - PrevStackSize == 1) ||
563  (Instrs.size() == 1 && NumDefCFAOffsets == 1 && StackSize == 2))
564  return CU::UNWIND_MODE_DWARF;
565 
566  SubtractInstrIdx += InstrOffset;
567  ++StackAdjust;
568 
569  if ((StackSize & 0xFF) == StackSize) {
570  // Frameless stack with a small stack size.
571  CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IMMD;
572 
573  // Encode the stack size.
574  CompactUnwindEncoding |= (StackSize & 0xFF) << 16;
575  } else {
576  if ((StackAdjust & 0x7) != StackAdjust)
577  // The extra stack adjustments are too big for us to handle.
578  return CU::UNWIND_MODE_DWARF;
579 
580  // Frameless stack with an offset too large for us to encode compactly.
581  CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IND;
582 
583  // Encode the offset to the nnnnnn value in the 'subl $nnnnnn, ESP'
584  // instruction.
585  CompactUnwindEncoding |= (SubtractInstrIdx & 0xFF) << 16;
586 
587  // Encode any extra stack stack adjustments (done via push
588  // instructions).
589  CompactUnwindEncoding |= (StackAdjust & 0x7) << 13;
590  }
591 
592  // Encode the number of registers saved. (Reverse the list first.)
593  std::reverse(&SavedRegs[0], &SavedRegs[SavedRegIdx]);
594  CompactUnwindEncoding |= (SavedRegIdx & 0x7) << 10;
595 
596  // Get the encoding of the saved registers when we don't have a frame
597  // pointer.
598  uint32_t RegEnc = encodeCompactUnwindRegistersWithoutFrame(SavedRegIdx);
599  if (RegEnc == ~0U) return CU::UNWIND_MODE_DWARF;
600 
601  // Encode the register encoding.
602  CompactUnwindEncoding |=
603  RegEnc & CU::UNWIND_FRAMELESS_STACK_REG_PERMUTATION;
604  }
605 
606  return CompactUnwindEncoding;
607  }
608 
609 private:
610  /// \brief Get the compact unwind number for a given register. The number
611  /// corresponds to the enum lists in compact_unwind_encoding.h.
612  int getCompactUnwindRegNum(unsigned Reg) const {
613  static const uint16_t CU32BitRegs[7] = {
614  X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0
615  };
616  static const uint16_t CU64BitRegs[] = {
617  X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
618  };
619  const uint16_t *CURegs = Is64Bit ? CU64BitRegs : CU32BitRegs;
620  for (int Idx = 1; *CURegs; ++CURegs, ++Idx)
621  if (*CURegs == Reg)
622  return Idx;
623 
624  return -1;
625  }
626 
627  /// \brief Return the registers encoded for a compact encoding with a frame
628  /// pointer.
629  uint32_t encodeCompactUnwindRegistersWithFrame() const {
630  // Encode the registers in the order they were saved --- 3-bits per
631  // register. The list of saved registers is assumed to be in reverse
632  // order. The registers are numbered from 1 to CU_NUM_SAVED_REGS.
633  uint32_t RegEnc = 0;
634  for (int i = 0, Idx = 0; i != CU_NUM_SAVED_REGS; ++i) {
635  unsigned Reg = SavedRegs[i];
636  if (Reg == 0) break;
637 
638  int CURegNum = getCompactUnwindRegNum(Reg);
639  if (CURegNum == -1) return ~0U;
640 
641  // Encode the 3-bit register number in order, skipping over 3-bits for
642  // each register.
643  RegEnc |= (CURegNum & 0x7) << (Idx++ * 3);
644  }
645 
646  assert((RegEnc & 0x3FFFF) == RegEnc &&
647  "Invalid compact register encoding!");
648  return RegEnc;
649  }
650 
651  /// \brief Create the permutation encoding used with frameless stacks. It is
652  /// passed the number of registers to be saved and an array of the registers
653  /// saved.
654  uint32_t encodeCompactUnwindRegistersWithoutFrame(unsigned RegCount) const {
655  // The saved registers are numbered from 1 to 6. In order to encode the
656  // order in which they were saved, we re-number them according to their
657  // place in the register order. The re-numbering is relative to the last
658  // re-numbered register. E.g., if we have registers {6, 2, 4, 5} saved in
659  // that order:
660  //
661  // Orig Re-Num
662  // ---- ------
663  // 6 6
664  // 2 2
665  // 4 3
666  // 5 3
667  //
668  for (unsigned i = 0; i < RegCount; ++i) {
669  int CUReg = getCompactUnwindRegNum(SavedRegs[i]);
670  if (CUReg == -1) return ~0U;
671  SavedRegs[i] = CUReg;
672  }
673 
674  // Reverse the list.
675  std::reverse(&SavedRegs[0], &SavedRegs[CU_NUM_SAVED_REGS]);
676 
677  uint32_t RenumRegs[CU_NUM_SAVED_REGS];
678  for (unsigned i = CU_NUM_SAVED_REGS - RegCount; i < CU_NUM_SAVED_REGS; ++i){
679  unsigned Countless = 0;
680  for (unsigned j = CU_NUM_SAVED_REGS - RegCount; j < i; ++j)
681  if (SavedRegs[j] < SavedRegs[i])
682  ++Countless;
683 
684  RenumRegs[i] = SavedRegs[i] - Countless - 1;
685  }
686 
687  // Take the renumbered values and encode them into a 10-bit number.
688  uint32_t permutationEncoding = 0;
689  switch (RegCount) {
690  case 6:
691  permutationEncoding |= 120 * RenumRegs[0] + 24 * RenumRegs[1]
692  + 6 * RenumRegs[2] + 2 * RenumRegs[3]
693  + RenumRegs[4];
694  break;
695  case 5:
696  permutationEncoding |= 120 * RenumRegs[1] + 24 * RenumRegs[2]
697  + 6 * RenumRegs[3] + 2 * RenumRegs[4]
698  + RenumRegs[5];
699  break;
700  case 4:
701  permutationEncoding |= 60 * RenumRegs[2] + 12 * RenumRegs[3]
702  + 3 * RenumRegs[4] + RenumRegs[5];
703  break;
704  case 3:
705  permutationEncoding |= 20 * RenumRegs[3] + 4 * RenumRegs[4]
706  + RenumRegs[5];
707  break;
708  case 2:
709  permutationEncoding |= 5 * RenumRegs[4] + RenumRegs[5];
710  break;
711  case 1:
712  permutationEncoding |= RenumRegs[5];
713  break;
714  }
715 
716  assert((permutationEncoding & 0x3FF) == permutationEncoding &&
717  "Invalid compact register encoding!");
718  return permutationEncoding;
719  }
720 
721 public:
722  DarwinX86AsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef CPU,
723  bool Is64Bit)
724  : X86AsmBackend(T, CPU), MRI(MRI), Is64Bit(Is64Bit) {
725  memset(SavedRegs, 0, sizeof(SavedRegs));
726  OffsetSize = Is64Bit ? 8 : 4;
727  MoveInstrSize = Is64Bit ? 3 : 2;
728  StackDivide = Is64Bit ? 8 : 4;
729  }
730 };
731 
732 class DarwinX86_32AsmBackend : public DarwinX86AsmBackend {
733 public:
734  DarwinX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI,
735  StringRef CPU)
736  : DarwinX86AsmBackend(T, MRI, CPU, false) {}
737 
738  MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
739  return createX86MachObjectWriter(OS, /*Is64Bit=*/false,
742  }
743 
744  /// \brief Generate the compact unwind encoding for the CFI instructions.
745  uint32_t generateCompactUnwindEncoding(
746  ArrayRef<MCCFIInstruction> Instrs) const override {
747  return generateCompactUnwindEncodingImpl(Instrs);
748  }
749 };
750 
751 class DarwinX86_64AsmBackend : public DarwinX86AsmBackend {
752  const MachO::CPUSubTypeX86 Subtype;
753 public:
754  DarwinX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI,
756  : DarwinX86AsmBackend(T, MRI, CPU, true), Subtype(st) {}
757 
758  MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
759  return createX86MachObjectWriter(OS, /*Is64Bit=*/true,
760  MachO::CPU_TYPE_X86_64, Subtype);
761  }
762 
763  /// \brief Generate the compact unwind encoding for the CFI instructions.
764  uint32_t generateCompactUnwindEncoding(
765  ArrayRef<MCCFIInstruction> Instrs) const override {
766  return generateCompactUnwindEncodingImpl(Instrs);
767  }
768 };
769 
770 } // end anonymous namespace
771 
773  const MCRegisterInfo &MRI,
774  const Triple &TheTriple,
775  StringRef CPU) {
776  if (TheTriple.isOSBinFormatMachO())
777  return new DarwinX86_32AsmBackend(T, MRI, CPU);
778 
779  if (TheTriple.isOSWindows() && !TheTriple.isOSBinFormatELF())
780  return new WindowsX86AsmBackend(T, false, CPU);
781 
782  uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
783  return new ELFX86_32AsmBackend(T, OSABI, CPU);
784 }
785 
787  const MCRegisterInfo &MRI,
788  const Triple &TheTriple,
789  StringRef CPU) {
790  if (TheTriple.isOSBinFormatMachO()) {
793  .Case("x86_64h", MachO::CPU_SUBTYPE_X86_64_H)
795  return new DarwinX86_64AsmBackend(T, MRI, CPU, CS);
796  }
797 
798  if (TheTriple.isOSWindows() && !TheTriple.isOSBinFormatELF())
799  return new WindowsX86AsmBackend(T, true, CPU);
800 
801  uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
802 
803  if (TheTriple.getEnvironment() == Triple::GNUX32)
804  return new ELFX86_X32AsmBackend(T, OSABI, CPU);
805  return new ELFX86_64AsmBackend(T, OSABI, CPU);
806 }
OSType getOS() const
getOS - Get the parsed operating system type of this triple.
Definition: Triple.h:251
A eight-byte pc relative fixup.
Definition: MCFixup.h:31
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:489
MCAsmBackend * createX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU)
MCAsmBackend * createX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU)
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:488
Defines the object file and target independent interfaces used by the assembler backend to write nati...
void write8(uint8_t Value)
unsigned getRegister() const
Definition: MCDwarf.h:444
void dump_pretty(raw_ostream &OS, const MCInstPrinter *Printer=nullptr, StringRef Separator=" ") const
Dump the MCInst as prettily as possible using the additional MC structures, if given.
Definition: MCInst.cpp:51
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag=true)
Reports a serious error, calling any installed error handler.
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:464
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:62
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...
A one-byte pc relative fixup.
Definition: MCFixup.h:28
int getOffset() const
Definition: MCDwarf.h:457
MCObjectWriter * createX86WinCOFFObjectWriter(raw_pwrite_stream &OS, bool Is64Bit)
Construct an X86 Win COFF object writer.
Encapsulates the layout of an assembly file at a particular point in time.
Definition: MCAsmLayout.h:29
static unsigned getRelaxedOpcode(unsigned Op)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
Reg
All possible values of the reg field in the ModR/M byte.
Number of individual test Apply this number of consecutive mutations to each input exit after the first new interesting input is found the minimized corpus is saved into the first input directory Number of jobs to run If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
A four-byte section relative fixup.
Definition: MCFixup.h:38
#define false
Definition: ConvertUTF.c:65
A four-byte fixup.
Definition: MCFixup.h:26
A two-byte section relative fixup.
Definition: MCFixup.h:37
CompactUnwindEncodings
Compact unwind encoding values.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: ArrayRef.h:31
uint32_t getOffset() const
Definition: MCFixup.h:91
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:134
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:150
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
Definition: MCAssembler.h:259
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:42
#define true
Definition: ConvertUTF.c:66
MCObjectWriter * createX86MachObjectWriter(raw_pwrite_stream &OS, bool Is64Bit, uint32_t CPUType, uint32_t CPUSubtype)
Construct an X86 Mach-O object writer.
static bool is64Bit(const char *name)
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:23
bool isExpr() const
Definition: MCInst.h:59
static unsigned getRelaxedOpcodeArith(unsigned Op)
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:129
static unsigned getFixupKindLog2Size(unsigned Kind)
bool isIntN(unsigned N, int64_t x)
isIntN - Checks if an signed integer fits into the given (dynamic) bit width.
Definition: MathExtras.h:321
MCFixupKind getKind() const
Definition: MCFixup.h:89
A one-byte fixup.
Definition: MCFixup.h:24
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
PowerPC TLS Dynamic Call Fixup
OpType getOperation() const
Definition: MCDwarf.h:441
void setOpcode(unsigned Op)
Definition: MCInst.h:158
A two-byte pc relative fixup.
Definition: MCFixup.h:29
A four-byte pc relative fixup.
Definition: MCFixup.h:30
static unsigned getRelaxedOpcodeBranch(unsigned Op)
R Default(const T &Value) const
Definition: StringSwitch.h:111
MCObjectWriter * createX86ELFObjectWriter(raw_pwrite_stream &OS, bool IsELF64, uint8_t OSABI, uint16_t EMachine)
Construct an X86 ELF object writer.
unsigned getOpcode() const
Definition: MCInst.h:159
Target - Wrapper for Target specific information.
A one-byte section relative fixup.
Definition: MCFixup.h:36
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:479
A eight-byte section relative fixup.
Definition: MCFixup.h:39
unsigned getNumOperands() const
Definition: MCInst.h:166
StringRef getArchName() const
getArchName - Get the architecture (first) component of the triple.
Definition: Triple.cpp:783
APFloat abs(APFloat X)
Returns the absolute value of the argument.
Definition: APFloat.h:651
A eight-byte fixup.
Definition: MCFixup.h:27
Target independent information on a fixup kind.
EnvironmentType getEnvironment() const
getEnvironment - Get the parsed environment type of this triple.
Definition: Triple.h:260
An abstract base class for streams implementations that also support a pwrite operation.
Definition: raw_ostream.h:321
const ARM::ArchExtKind Kind
LLVM Value Representation.
Definition: Value.h:69
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:34
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:40
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
A two-byte fixup.
Definition: MCFixup.h:25
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:164