86 #define DEBUG_TYPE "peephole-opt"
91 cl::desc(
"Aggressive extension optimization"));
95 cl::desc(
"Disable the peephole optimizer"));
99 cl::desc(
"Disable advanced copy optimization"));
101 STATISTIC(NumReuse,
"Number of extension results reused");
102 STATISTIC(NumCmps,
"Number of compares eliminated");
103 STATISTIC(NumImmFold,
"Number of move immediate folded");
104 STATISTIC(NumLoadFold,
"Number of loads folded");
105 STATISTIC(NumSelects,
"Number of selects optimized");
106 STATISTIC(NumUncoalescableCopies,
"Number of uncoalescable copies optimized");
107 STATISTIC(NumRewrittenCopies,
"Number of copies rewritten");
144 bool findNextSource(
unsigned &
Reg,
unsigned &SubReg);
207 bool UseAdvancedTracking;
216 bool getNextSourceImpl(
unsigned &SrcReg,
unsigned &SrcSubReg);
218 bool getNextSourceFromCopy(
unsigned &SrcReg,
unsigned &SrcSubReg);
220 bool getNextSourceFromBitcast(
unsigned &SrcReg,
unsigned &SrcSubReg);
223 bool getNextSourceFromRegSequence(
unsigned &SrcReg,
unsigned &SrcSubReg);
226 bool getNextSourceFromInsertSubreg(
unsigned &SrcReg,
unsigned &SrcSubReg);
229 bool getNextSourceFromExtractSubreg(
unsigned &SrcReg,
unsigned &SrcSubReg);
232 bool getNextSourceFromSubregToReg(
unsigned &SrcReg,
unsigned &SrcSubReg);
247 ValueTracker(
unsigned Reg,
unsigned DefSubReg,
249 bool UseAdvancedTracking =
false,
251 :
Def(nullptr), DefIdx(0), DefSubReg(DefSubReg), Reg(Reg),
252 UseAdvancedTracking(UseAdvancedTracking), MRI(MRI),
TII(
TII) {
266 ValueTracker(
const MachineInstr &MI,
unsigned DefIdx,
unsigned DefSubReg,
268 bool UseAdvancedTracking =
false,
270 :
Def(&MI), DefIdx(DefIdx), DefSubReg(DefSubReg),
271 UseAdvancedTracking(UseAdvancedTracking), MRI(MRI),
TII(
TII) {
272 assert(DefIdx < Def->
getDesc().getNumDefs() &&
273 Def->getOperand(DefIdx).isReg() &&
"Invalid definition");
274 Reg =
Def->getOperand(DefIdx).getReg();
288 const MachineInstr *getNextSource(
unsigned &SrcReg,
unsigned &SrcSubReg);
301 "Peephole Optimizations",
false,
false)
315 bool PeepholeOptimizer::
318 unsigned SrcReg, DstReg, SubIdx;
319 if (!
TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx))
333 DstRC = TRI->getSubClassWithSubReg(DstRC, SubIdx);
343 TRI->getSubClassWithSubReg(MRI->
getRegClass(SrcReg), SubIdx) !=
nullptr;
349 ReachedBBs.
insert(UI.getParent());
357 bool ExtendLife =
true;
363 if (UseMI->
isPHI()) {
369 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx)
395 if (!LocalMIs.count(UseMI))
397 }
else if (ReachedBBs.
count(UseMBB)) {
401 }
else if (
Aggressive && DT->dominates(MBB, UseMBB)) {
413 if (ExtendLife && !ExtendedUses.
empty())
418 bool Changed =
false;
427 PHIBBs.
insert(UI.getParent());
430 for (
unsigned i = 0, e = Uses.
size(); i != e; ++i) {
434 if (PHIBBs.
count(UseMBB))
446 .addReg(DstReg, 0, SubIdx);
465 bool PeepholeOptimizer::optimizeCmpInstr(
MachineInstr *MI,
469 unsigned SrcReg, SrcReg2;
470 int CmpMask, CmpValue;
477 if (
TII->optimizeCompareInstr(MI, SrcReg, SrcReg2, CmpMask, CmpValue, MRI)) {
486 bool PeepholeOptimizer::optimizeSelect(
MachineInstr *MI,
489 unsigned FalseOp = 0;
490 bool Optimizable =
false;
492 if (
TII->analyzeSelect(MI, Cond, TrueOp, FalseOp, Optimizable))
496 if (!
TII->optimizeSelect(MI, LocalMIs))
505 bool PeepholeOptimizer::optimizeCondBranch(
MachineInstr *MI) {
506 return TII->optimizeCondBranch(MI);
515 unsigned SrcSubReg) {
521 unsigned SrcIdx, DefIdx;
522 if (SrcSubReg && DefSubReg)
524 SrcIdx, DefIdx) !=
nullptr;
544 bool PeepholeOptimizer::findNextSource(
unsigned &Reg,
unsigned &SubReg) {
553 unsigned DefSubReg = SubReg;
557 bool ShouldRewrite =
false;
563 unsigned CopySrcReg, CopySrcSubReg;
564 if (!ValTracker.getNextSource(CopySrcReg, CopySrcSubReg))
567 SrcSubReg = CopySrcSubReg;
582 }
while (!ShouldRewrite);
585 if (!ShouldRewrite || Src == Reg)
600 unsigned CurrentSrcIdx;
603 CopyRewriter(
MachineInstr &MI) : CopyLike(MI), CurrentSrcIdx(0) {}
605 virtual ~CopyRewriter() {}
632 virtual bool getNextRewritableSource(
unsigned &SrcReg,
unsigned &SrcSubReg,
634 unsigned &TrackSubReg) {
638 if (!CopyLike.isCopy() || CurrentSrcIdx == 1)
649 TrackReg = MODef.
getReg();
657 virtual bool RewriteCurrentSource(
unsigned NewReg,
unsigned NewSubReg) {
658 if (!CopyLike.isCopy() || CurrentSrcIdx != 1)
668 class InsertSubregRewriter :
public CopyRewriter {
670 InsertSubregRewriter(
MachineInstr &MI) : CopyRewriter(MI) {
685 bool getNextRewritableSource(
unsigned &SrcReg,
unsigned &SrcSubReg,
687 unsigned &TrackSubReg)
override {
689 if (CurrentSrcIdx == 2)
694 SrcReg = MOInsertedReg.
getReg();
700 TrackReg = MODef.
getReg();
704 TrackSubReg = (
unsigned)CopyLike.getOperand(3).getImm();
707 bool RewriteCurrentSource(
unsigned NewReg,
unsigned NewSubReg)
override {
708 if (CurrentSrcIdx != 2)
719 class ExtractSubregRewriter :
public CopyRewriter {
724 : CopyRewriter(MI), TII(TII) {
733 bool getNextRewritableSource(
unsigned &SrcReg,
unsigned &SrcSubReg,
735 unsigned &TrackSubReg)
override {
737 if (CurrentSrcIdx == 1)
742 SrcReg = MOExtractedReg.
getReg();
747 SrcSubReg = CopyLike.getOperand(2).getImm();
751 TrackReg = MODef.
getReg();
756 bool RewriteCurrentSource(
unsigned NewReg,
unsigned NewSubReg)
override {
758 if (CurrentSrcIdx != 1)
761 CopyLike.getOperand(CurrentSrcIdx).setReg(NewReg);
772 CopyLike.RemoveOperand(2);
777 CopyLike.getOperand(CurrentSrcIdx + 1).setImm(NewSubReg);
783 class RegSequenceRewriter :
public CopyRewriter {
785 RegSequenceRewriter(
MachineInstr &MI) : CopyRewriter(MI) {
805 bool getNextRewritableSource(
unsigned &SrcReg,
unsigned &SrcSubReg,
807 unsigned &TrackSubReg)
override {
811 if (CurrentSrcIdx == 0) {
816 if (CurrentSrcIdx >= CopyLike.getNumOperands())
819 const MachineOperand &MOInsertedReg = CopyLike.getOperand(CurrentSrcIdx);
820 SrcReg = MOInsertedReg.
getReg();
822 if ((SrcSubReg = MOInsertedReg.
getSubReg()))
827 TrackSubReg = CopyLike.getOperand(CurrentSrcIdx + 1).getImm();
830 TrackReg = MODef.
getReg();
835 bool RewriteCurrentSource(
unsigned NewReg,
unsigned NewSubReg)
override {
838 if ((CurrentSrcIdx & 1) != 1 || CurrentSrcIdx > CopyLike.getNumOperands())
858 return new CopyRewriter(MI);
860 return new InsertSubregRewriter(MI);
862 return new ExtractSubregRewriter(MI, TII);
864 return new RegSequenceRewriter(MI);
881 bool PeepholeOptimizer::optimizeCoalescableCopy(
MachineInstr *MI) {
882 assert(MI && isCoalescableCopy(*MI) &&
"Invalid argument");
884 "Coalescer can understand multiple defs?!");
890 bool Changed =
false;
897 unsigned SrcReg, SrcSubReg, TrackReg, TrackSubReg;
898 while (CpyRewriter->getNextRewritableSource(SrcReg, SrcSubReg, TrackReg,
900 unsigned NewSrc = TrackReg;
901 unsigned NewSubReg = TrackSubReg;
905 if (!findNextSource(NewSrc, NewSubReg) || SrcReg == NewSrc)
908 if (CpyRewriter->RewriteCurrentSource(NewSrc, NewSubReg)) {
919 NumRewrittenCopies += Changed;
934 bool PeepholeOptimizer::optimizeUncoalescableCopy(
936 assert(MI && isUncoalescableCopy(*MI) &&
"Invalid argument");
940 std::pair<TargetInstrInfo::RegSubRegPair, TargetInstrInfo::RegSubRegPair>,
956 if (!findNextSource(Src.Reg, Src.SubReg))
961 for (
const auto &PairDefSrc : RewritePairs) {
962 const auto &
Def = PairDefSrc.first;
963 const auto &Src = PairDefSrc.second;
966 "We do not rewrite physical registers");
971 NewVR).addReg(Src.Reg, 0, Src.SubReg);
984 ++NumUncoalescableCopies;
991 bool PeepholeOptimizer::isLoadFoldable(
1007 FoldAsLoadDefCandidates.
insert(Reg);
1013 bool PeepholeOptimizer::isMoveImmediate(
MachineInstr *MI,
1023 ImmDefMIs.
insert(std::make_pair(Reg, MI));
1041 unsigned Reg = MO.
getReg();
1044 if (ImmDefRegs.
count(Reg) == 0)
1047 assert(II != ImmDefMIs.
end());
1060 DEBUG(
dbgs() <<
"********** PEEPHOLE OPTIMIZER **********\n");
1069 DT =
Aggressive ? &getAnalysis<MachineDominatorTree>() :
nullptr;
1071 bool Changed =
false;
1076 bool SeenMoveImm =
false;
1090 MII =
I->begin(), MIE =
I->end(); MII != MIE; ) {
1105 FoldAsLoadDefCandidates.
clear();
1109 FoldAsLoadDefCandidates.
clear();
1111 if ((isUncoalescableCopy(*MI) &&
1112 optimizeUncoalescableCopy(MI, LocalMIs)) ||
1113 (MI->
isCompare() && optimizeCmpInstr(MI, MBB)) ||
1114 (MI->
isSelect() && optimizeSelect(MI, LocalMIs))) {
1126 if (isCoalescableCopy(*MI) && optimizeCoalescableCopy(MI)) {
1132 if (isMoveImmediate(MI, ImmDefRegs, ImmDefMIs)) {
1135 Changed |= optimizeExtInstr(MI, MBB, LocalMIs);
1142 Changed |= foldImmediate(MI, MBB, ImmDefRegs, ImmDefMIs);
1148 if (!isLoadFoldable(MI, FoldAsLoadDefCandidates) &&
1149 !FoldAsLoadDefCandidates.
empty()) {
1156 unsigned FoldAsLoadDefReg = MOp.
getReg();
1157 if (FoldAsLoadDefCandidates.
count(FoldAsLoadDefReg)) {
1162 unsigned FoldedReg = FoldAsLoadDefReg;
1173 LocalMIs.
erase(DefMI);
1178 FoldAsLoadDefCandidates.
erase(FoldedReg);
1193 bool ValueTracker::getNextSourceFromCopy(
unsigned &SrcReg,
1194 unsigned &SrcSubReg) {
1195 assert(
Def->isCopy() &&
"Invalid definition");
1198 assert(
Def->getNumOperands() == 2 &&
"Invalid number of operands");
1200 if (
Def->getOperand(DefIdx).getSubReg() != DefSubReg)
1211 bool ValueTracker::getNextSourceFromBitcast(
unsigned &SrcReg,
1212 unsigned &SrcSubReg) {
1213 assert(
Def->isBitcast() &&
"Invalid definition");
1216 if (
Def->hasUnmodeledSideEffects())
1220 if (
Def->getDesc().getNumDefs() != 1)
1222 if (
Def->getOperand(DefIdx).getSubReg() != DefSubReg)
1227 unsigned SrcIdx =
Def->getNumOperands();
1228 for (
unsigned OpIdx = DefIdx + 1, EndOpIdx = SrcIdx; OpIdx != EndOpIdx;
1233 assert(!MO.
isDef() &&
"We should have skipped all the definitions by now");
1234 if (SrcIdx != EndOpIdx)
1245 bool ValueTracker::getNextSourceFromRegSequence(
unsigned &SrcReg,
1246 unsigned &SrcSubReg) {
1247 assert((
Def->isRegSequence() ||
Def->isRegSequenceLike()) &&
1248 "Invalid definition");
1250 if (
Def->getOperand(DefIdx).getSubReg())
1279 for (
auto &RegSeqInput : RegSeqInputRegs) {
1280 if (RegSeqInput.SubIdx == DefSubReg) {
1281 if (RegSeqInput.SubReg)
1285 SrcReg = RegSeqInput.Reg;
1286 SrcSubReg = RegSeqInput.SubReg;
1297 bool ValueTracker::getNextSourceFromInsertSubreg(
unsigned &SrcReg,
1298 unsigned &SrcSubReg) {
1299 assert((
Def->isInsertSubreg() ||
Def->isInsertSubregLike()) &&
1300 "Invalid definition");
1302 if (
Def->getOperand(DefIdx).getSubReg())
1325 if (InsertedReg.
SubIdx == DefSubReg) {
1326 SrcReg = InsertedReg.
Reg;
1327 SrcSubReg = InsertedReg.
SubReg;
1350 SrcReg = BaseReg.
Reg;
1351 SrcSubReg = DefSubReg;
1355 bool ValueTracker::getNextSourceFromExtractSubreg(
unsigned &SrcReg,
1356 unsigned &SrcSubReg) {
1357 assert((
Def->isExtractSubreg() ||
1358 Def->isExtractSubregLike()) &&
"Invalid definition");
1378 if (ExtractSubregInputReg.
SubReg)
1381 SrcReg = ExtractSubregInputReg.
Reg;
1382 SrcSubReg = ExtractSubregInputReg.
SubIdx;
1386 bool ValueTracker::getNextSourceFromSubregToReg(
unsigned &SrcReg,
1387 unsigned &SrcSubReg) {
1388 assert(
Def->isSubregToReg() &&
"Invalid definition");
1396 if (DefSubReg !=
Def->getOperand(3).getImm())
1400 if (
Def->getOperand(2).getSubReg())
1403 SrcReg =
Def->getOperand(2).getReg();
1404 SrcSubReg =
Def->getOperand(3).getImm();
1408 bool ValueTracker::getNextSourceImpl(
unsigned &SrcReg,
unsigned &SrcSubReg) {
1409 assert(
Def &&
"This method needs a valid definition");
1412 (DefIdx < Def->
getDesc().getNumDefs() ||
Def->getDesc().isVariadic()) &&
1413 Def->getOperand(DefIdx).isDef() &&
"Invalid DefIdx");
1415 return getNextSourceFromCopy(SrcReg, SrcSubReg);
1416 if (
Def->isBitcast())
1417 return getNextSourceFromBitcast(SrcReg, SrcSubReg);
1420 if (!UseAdvancedTracking)
1422 if (
Def->isRegSequence() ||
Def->isRegSequenceLike())
1423 return getNextSourceFromRegSequence(SrcReg, SrcSubReg);
1424 if (
Def->isInsertSubreg() ||
Def->isInsertSubregLike())
1425 return getNextSourceFromInsertSubreg(SrcReg, SrcSubReg);
1426 if (
Def->isExtractSubreg() ||
Def->isExtractSubregLike())
1427 return getNextSourceFromExtractSubreg(SrcReg, SrcSubReg);
1428 if (
Def->isSubregToReg())
1429 return getNextSourceFromSubregToReg(SrcReg, SrcSubReg);
1433 const MachineInstr *ValueTracker::getNextSource(
unsigned &SrcReg,
1434 unsigned &SrcSubReg) {
1442 if (getNextSourceImpl(SrcReg, SrcSubReg)) {
1454 DefSubReg = SrcSubReg;
void push_back(const T &Elt)
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
STATISTIC(NumFunctions,"Total number of functions")
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Describe properties that are true of each instruction in the target description file.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
void setIsUndef(bool Val=true)
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
bool getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const
Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx.
size_type count(PtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const
getCommonSubClass - find the largest common subclass of A and B.
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
bool canFoldAsLoad(QueryType Type=IgnoreBundle) const
Return true for instructions that can be folded as memory operands in other instructions.
bool isConditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
bool isExtractSubreg() const
void markUsesInDebugValueAsUndef(unsigned Reg) const
markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the specified register as undefined wh...
bool isSelect(QueryType Type=IgnoreBundle) const
Return true if this instruction is a select instruction.
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
COPY - Target-independent register copy.
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
AnalysisUsage & addRequired()
#define INITIALIZE_PASS_DEPENDENCY(depName)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
const TargetRegisterInfo * getTargetRegisterInfo() const
static cl::opt< bool > Aggressive("aggressive-ext-opt", cl::Hidden, cl::desc("Aggressive extension optimization"))
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
const TargetRegisterClass * getRegClass(unsigned Reg) const
getRegClass - Return the register class of the specified virtual register.
Reg
All possible values of the reg field in the ModR/M byte.
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
void initializePeepholeOptimizerPass(PassRegistry &)
bool isBitcast(QueryType Type=IgnoreBundle) const
Return true if this instruction is a bitcast instruction.
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
getMatchingSuperRegClass - Return a subclass of the specified register class A so that each register ...
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const
Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineBasicBlock * getParent() const
TargetInstrInfo - Interface to description of machine instruction set.
bool isDebugValue() const
bool isImplicitDef() const
const TargetRegisterClass * getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA, const TargetRegisterClass *RCB, unsigned SubB, unsigned &PreA, unsigned &PreB) const
getCommonSuperRegClass - Find a common super-register class if it exists.
bool isInsertSubreg() const
bundle_iterator< MachineInstr, instr_iterator > iterator
initializer< Ty > init(const Ty &Val)
iterator_range< use_nodbg_iterator > use_nodbg_operands(unsigned Reg) const
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
unsigned getSubRegIndexLaneMask(unsigned SubIdx) const
getSubRegIndexLaneMask - Return a bitmask representing the parts of a register that are covered by Su...
virtual MachineInstr * optimizeLoadInstr(MachineInstr *MI, const MachineRegisterInfo *MRI, unsigned &FoldAsLoadDefReg, MachineInstr *&DefMI) const
Try to remove the load by folding it to a register operand at the use.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
const MachineOperand & getOperand(unsigned i) const
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
INSERT_SUBREG - This instruction takes three operands: a register that has subregisters, a register providing an insert value, and a subregister index.
unsigned getOperandNo() const
getOperandNo - Return the operand # of this MachineOperand in its MachineInstr.
Represent the analysis usage information of a pass.
static CopyRewriter * getCopyRewriter(MachineInstr &MI, const TargetInstrInfo &TII)
Get the appropriated CopyRewriter for MI.
iterator_range< mop_iterator > defs()
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore...
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
void append(in_iter in_start, in_iter in_end)
Add the specified range to the end of the SmallVector.
unsigned getSubReg() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
REG_SEQUENCE - This variadic instruction is used to form a register that represents a consecutive seq...
bool isInsertSubregLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions...
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
EXTRACT_SUBREG - This instruction takes two operands: a register that has subregisters, and a subregister index.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const
Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx.
bool erase(PtrType Ptr)
erase - If the set contains the specified pointer, remove it and return true, otherwise return false...
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
A pair composed of a register and a sub-register index.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
bool isCompare(QueryType Type=IgnoreBundle) const
Return true if this instruction is a comparison.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
char & PeepholeOptimizerID
PeepholeOptimizer - This pass performs peephole optimizations - like extension and comparison elimina...
bool isExtractSubregLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
void replaceRegWith(unsigned FromReg, unsigned ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
def_iterator def_begin(unsigned RegNo) const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override
For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two registe...
Representation of each machine instruction.
static bool isPhysicalRegister(unsigned Reg)
isPhysicalRegister - Return true if the specified register number is in the physical register namespa...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, unsigned Reg, MachineRegisterInfo *MRI) const
'Reg' is known to be defined by a move immediate instruction, try to fold the immediate into the use ...
iterator_range< use_instr_nodbg_iterator > use_nodbg_instructions(unsigned Reg) const
static cl::opt< bool > DisablePeephole("disable-peephole", cl::Hidden, cl::init(false), cl::desc("Disable the peephole optimizer"))
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
void setReg(unsigned Reg)
Change the register this operand corresponds to.
bool isCall(QueryType Type=AnyInBundle) const
void setSubReg(unsigned subReg)
void clearKillFlags(unsigned Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
iterator find(const KeyT &Val)
peephole Peephole Optimizations
MCInstrDesc const & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
INITIALIZE_PASS_BEGIN(PeepholeOptimizer,"peephole-opts","Peephole Optimizations", false, false) INITIALIZE_PASS_END(PeepholeOptimizer
unsigned getReg() const
getReg - Returns the register number.
static bool shareSameRegisterFile(const TargetRegisterInfo &TRI, const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg)
Check if the registers defined by the pair (RegisterClass, SubReg) share the same register file...
virtual const TargetInstrInfo * getInstrInfo() const
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
BasicBlockListType::iterator iterator
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except that the first operand is an imme...
bool isRegSequence() const
bool isMoveImmediate(QueryType Type=IgnoreBundle) const
Return true if this instruction is a move immediate (including conditional moves) instruction...
bool isRegSequenceLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions.
static cl::opt< bool > DisableAdvCopyOpt("disable-adv-copy-opt", cl::Hidden, cl::init(false), cl::desc("Disable advanced copy optimization"))
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
A pair composed of a pair of a register and a sub-register index, and another sub-register index...