16 #ifndef LLVM_LIB_TARGET_R600_SIREGISTERINFO_H
17 #define LLVM_LIB_TARGET_R600_SIREGISTERINFO_H
32 unsigned Idx)
const override;
37 unsigned FIOperandNum,
60 if (static_cast<int>(RCID) == -1)
77 unsigned SubIdx)
const;
83 unsigned Channel)
const;
117 unsigned WaveCount)
const;
124 unsigned LoadStoreOp,
unsigned Value,
125 unsigned ScratchRsrcReg,
unsigned ScratchOffset,
bool opCanUseInlineConstant(unsigned OpType) const
unsigned getPhysRegSubReg(unsigned Reg, const TargetRegisterClass *SubRC, unsigned Channel) const
Channel This is the register channel (e.g.
AMDGPU specific subclass of TargetSubtarget.
unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override
bool hasVGPRs(const TargetRegisterClass *RC) const
BitVector getReservedRegs(const MachineFunction &MF) const override
const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const override
get the register class of the specified type to use in the CFGStructurizer
bool isSGPRClass(const TargetRegisterClass *RC) const
Reg
All possible values of the reg field in the ModR/M byte.
bool requiresRegisterScavenging(const MachineFunction &Fn) const override
TargetRegisterInfo interface that is implemented by all hw codegen targets.
unsigned getHWRegIndex(unsigned Reg) const override
bundle_iterator< MachineInstr, instr_iterator > iterator
MVT - Machine Value Type.
unsigned getNumVGPRsAllowed(unsigned WaveCount) const
Give the maximum number of VGPRs that can be used by WaveCount concurrent waves.
bundle_iterator - MachineBasicBlock iterator that automatically skips over MIs that are inside bundle...
unsigned getPreloadedValue(const MachineFunction &MF, enum PreloadedValue Value) const
Returns the physical register that Value is stored in.
unsigned findUnusedRegister(const MachineRegisterInfo &MRI, const TargetRegisterClass *RC) const
Returns a register that is not used at any point in the function.
const TargetRegisterClass * getEquivalentVGPRClass(const TargetRegisterClass *SRC) const
static unsigned getRegClass(bool IsVgpr, unsigned RegWidth)
bool opCanUseLiteralConstant(unsigned OpType) const
unsigned getNumSGPRsAllowed(AMDGPUSubtarget::Generation gen, unsigned WaveCount) const
Give the maximum number of SGPRs that can be used by WaveCount concurrent waves.
bool isSGPRClassID(unsigned RCID) const
const TargetRegisterClass * getSubRegClass(const TargetRegisterClass *RC, unsigned SubIdx) const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
const TargetRegisterClass * getPhysRegClass(unsigned Reg) const
Return the 'base' register class for this register.
LLVM Value Representation.
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const override