40 #define DEBUG_TYPE "regalloc"
42 STATISTIC(NumStores,
"Number of stores added");
43 STATISTIC(NumLoads ,
"Number of loads added");
44 STATISTIC(NumCopies,
"Number of copies coalesced");
54 isBulkSpilling(
false) {}
74 unsigned short LastOpNum;
77 explicit LiveReg(
unsigned v)
78 : LastUse(nullptr), VirtReg(v), PhysReg(0), LastOpNum(0), Dirty(
false){}
80 unsigned getSparseSetIndex()
const {
89 LiveRegMap LiveVirtRegs;
114 std::vector<unsigned> PhysRegState;
121 UsedInInstrSet UsedInInstr;
124 void markRegUsedInInstr(
unsigned PhysReg) {
126 UsedInInstr.
insert(*Units);
130 bool isRegUsedInInstr(
unsigned PhysReg)
const {
132 if (UsedInInstr.count(*Units))
150 spillImpossible = ~0u
153 const char *getPassName()
const override {
154 return "Fast Register Allocator";
164 void AllocateBasicBlock();
170 void addKillFlag(
const LiveReg&);
171 void killVirtReg(LiveRegMap::iterator);
172 void killVirtReg(
unsigned VirtReg);
177 void definePhysReg(
MachineInstr *
MI,
unsigned PhysReg, RegState NewState);
178 unsigned calcSpillCost(
unsigned PhysReg)
const;
179 void assignVirtToPhysReg(LiveReg&,
unsigned PhysReg);
180 LiveRegMap::iterator findLiveVirtReg(
unsigned VirtReg) {
183 LiveRegMap::const_iterator findLiveVirtReg(
unsigned VirtReg)
const {
186 LiveRegMap::iterator assignVirtToPhysReg(
unsigned VReg,
unsigned PhysReg);
187 LiveRegMap::iterator allocVirtReg(
MachineInstr *
MI, LiveRegMap::iterator,
189 LiveRegMap::iterator defineVirtReg(
MachineInstr *
MI,
unsigned OpNum,
190 unsigned VirtReg,
unsigned Hint);
191 LiveRegMap::iterator reloadVirtReg(
MachineInstr *
MI,
unsigned OpNum,
192 unsigned VirtReg,
unsigned Hint);
194 bool setPhysReg(
MachineInstr *
MI,
unsigned OpNum,
unsigned PhysReg);
203 int SS = StackSlotForVirtReg[VirtReg];
208 int FrameIdx = MF->getFrameInfo()->CreateSpillStackObject(RC->
getSize(),
212 StackSlotForVirtReg[VirtReg] = FrameIdx;
222 if (StackSlotForVirtReg[MO.
getReg()] != -1)
229 return ++I == MRI->reg_nodbg_end();
233 void RAFast::addKillFlag(
const LiveReg &LR) {
234 if (!LR.LastUse)
return;
236 if (MO.
isUse() && !LR.LastUse->isRegTiedToDefOperand(LR.LastOpNum)) {
237 if (MO.
getReg() == LR.PhysReg)
240 LR.LastUse->addRegisterKilled(LR.PhysReg, TRI,
true);
245 void RAFast::killVirtReg(LiveRegMap::iterator LRI) {
247 assert(PhysRegState[LRI->PhysReg] == LRI->VirtReg &&
248 "Broken RegState mapping");
249 PhysRegState[LRI->PhysReg] = regFree;
252 LiveVirtRegs.erase(LRI);
256 void RAFast::killVirtReg(
unsigned VirtReg) {
258 "killVirtReg needs a virtual register");
259 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
260 if (LRI != LiveVirtRegs.end())
268 "Spilling a physical register is illegal!");
269 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
270 assert(LRI != LiveVirtRegs.end() &&
"Spilling unmapped virtual register");
271 spillVirtReg(MI, LRI);
276 LiveRegMap::iterator LRI) {
278 assert(PhysRegState[LR.PhysReg] == LRI->VirtReg &&
"Broken RegState mapping");
283 bool SpillKill = LR.LastUse !=
MI;
286 <<
" in " <<
PrintReg(LR.PhysReg, TRI));
288 int FI = getStackSpaceFor(LRI->VirtReg, RC);
289 DEBUG(
dbgs() <<
" to stack slot #" << FI <<
"\n");
297 LiveDbgValueMap[LRI->VirtReg];
298 for (
unsigned li = 0, le = LRIDbgValues.
size(); li != le; ++li) {
305 assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(DL) &&
306 "Expected inlined-at fields to agree");
313 assert(NewDV->
getParent() == MBB &&
"dangling parent pointer");
315 DEBUG(
dbgs() <<
"Inserting debug info due to spill:" <<
"\n" << *NewDV);
320 LRIDbgValues.
clear();
322 LR.LastUse =
nullptr;
329 if (LiveVirtRegs.empty())
return;
330 isBulkSpilling =
true;
333 for (LiveRegMap::iterator i = LiveVirtRegs.begin(), e = LiveVirtRegs.end();
336 LiveVirtRegs.clear();
337 isBulkSpilling =
false;
345 unsigned PhysReg = MO.
getReg();
347 "Bad usePhysReg operand");
348 markRegUsedInInstr(PhysReg);
349 switch (PhysRegState[PhysReg]) {
353 PhysRegState[PhysReg] = regFree;
366 unsigned Alias = *AI;
367 switch (PhysRegState[Alias]) {
380 assert((TRI->isSuperRegister(PhysReg, Alias) ||
381 TRI->isSuperRegister(Alias, PhysReg)) &&
382 "Instruction is not using a subregister of a reserved register");
385 if (TRI->isSuperRegister(PhysReg, Alias)) {
387 PhysRegState[Alias] = regFree;
392 PhysRegState[Alias] = regDisabled;
400 PhysRegState[PhysReg] = regFree;
407 void RAFast::definePhysReg(
MachineInstr *MI,
unsigned PhysReg,
409 markRegUsedInInstr(PhysReg);
410 switch (
unsigned VirtReg = PhysRegState[PhysReg]) {
414 spillVirtReg(MI, VirtReg);
418 PhysRegState[PhysReg] = NewState;
423 PhysRegState[PhysReg] = NewState;
425 unsigned Alias = *AI;
426 switch (
unsigned VirtReg = PhysRegState[Alias]) {
430 spillVirtReg(MI, VirtReg);
434 PhysRegState[Alias] = regDisabled;
435 if (TRI->isSuperRegister(PhysReg, Alias))
448 unsigned RAFast::calcSpillCost(
unsigned PhysReg)
const {
449 if (isRegUsedInInstr(PhysReg)) {
451 return spillImpossible;
453 switch (
unsigned VirtReg = PhysRegState[PhysReg]) {
460 <<
PrintReg(PhysReg, TRI) <<
" is reserved already.\n");
461 return spillImpossible;
463 LiveRegMap::const_iterator I = findLiveVirtReg(VirtReg);
464 assert(I != LiveVirtRegs.end() &&
"Missing VirtReg entry");
465 return I->Dirty ? spillDirty : spillClean;
473 unsigned Alias = *AI;
474 switch (
unsigned VirtReg = PhysRegState[Alias]) {
481 return spillImpossible;
483 LiveRegMap::const_iterator I = findLiveVirtReg(VirtReg);
484 assert(I != LiveVirtRegs.end() &&
"Missing VirtReg entry");
485 Cost += I->Dirty ? spillDirty : spillClean;
498 void RAFast::assignVirtToPhysReg(LiveReg &LR,
unsigned PhysReg) {
501 PhysRegState[PhysReg] = LR.VirtReg;
502 assert(!LR.PhysReg &&
"Already assigned a physreg");
503 LR.PhysReg = PhysReg;
507 RAFast::assignVirtToPhysReg(
unsigned VirtReg,
unsigned PhysReg) {
508 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
509 assert(LRI != LiveVirtRegs.end() &&
"VirtReg disappeared");
510 assignVirtToPhysReg(*LRI, PhysReg);
516 LiveRegMap::iterator LRI,
518 const unsigned VirtReg = LRI->VirtReg;
521 "Can only allocate virtual registers");
527 !RC->
contains(Hint) || !MRI->isAllocatable(Hint)))
533 unsigned Cost = calcSpillCost(Hint);
534 if (Cost < spillDirty) {
536 definePhysReg(MI, Hint, regFree);
539 return assignVirtToPhysReg(VirtReg, Hint);
547 unsigned PhysReg = *
I;
548 if (PhysRegState[PhysReg] == regFree && !isRegUsedInInstr(PhysReg)) {
549 assignVirtToPhysReg(*LRI, PhysReg);
555 << TRI->getRegClassName(RC) <<
"\n");
557 unsigned BestReg = 0, BestCost = spillImpossible;
559 unsigned Cost = calcSpillCost(*I);
561 DEBUG(
dbgs() <<
"\tCost: " << Cost <<
"\n");
562 DEBUG(
dbgs() <<
"\tBestCost: " << BestCost <<
"\n");
565 assignVirtToPhysReg(*LRI, *I);
569 BestReg = *
I, BestCost = Cost;
573 definePhysReg(MI, BestReg, regFree);
576 return assignVirtToPhysReg(VirtReg, BestReg);
581 MI->
emitError(
"inline assembly requires more registers than available");
583 MI->
emitError(
"ran out of registers during register allocation");
584 definePhysReg(MI, *AO.
begin(), regFree);
585 return assignVirtToPhysReg(VirtReg, *AO.
begin());
591 unsigned VirtReg,
unsigned Hint) {
593 "Not a virtual register");
594 LiveRegMap::iterator LRI;
596 std::tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));
600 MRI->hasOneNonDBGUse(VirtReg)) {
601 const MachineInstr &UseMI = *MRI->use_instr_nodbg_begin(VirtReg);
606 LRI = allocVirtReg(MI, LRI, Hint);
607 }
else if (LRI->LastUse) {
610 if (LRI->LastUse != MI || LRI->LastUse->
getOperand(LRI->LastOpNum).
isUse())
613 assert(LRI->PhysReg &&
"Register not assigned");
615 LRI->LastOpNum = OpNum;
617 markRegUsedInInstr(LRI->PhysReg);
624 unsigned VirtReg,
unsigned Hint) {
626 "Not a virtual register");
627 LiveRegMap::iterator LRI;
629 std::tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));
632 LRI = allocVirtReg(MI, LRI, Hint);
634 int FrameIndex = getStackSpaceFor(VirtReg, RC);
636 <<
PrintReg(LRI->PhysReg, TRI) <<
"\n");
639 }
else if (LRI->Dirty) {
640 if (isLastUseOfLocalReg(MO)) {
641 DEBUG(
dbgs() <<
"Killing last use: " << MO <<
"\n");
647 DEBUG(
dbgs() <<
"Clearing dubious kill: " << MO <<
"\n");
650 DEBUG(
dbgs() <<
"Clearing dubious dead: " << MO <<
"\n");
658 DEBUG(
dbgs() <<
"Clearing clean kill: " << MO <<
"\n");
661 DEBUG(
dbgs() <<
"Clearing clean dead: " << MO <<
"\n");
664 assert(LRI->PhysReg &&
"Register not assigned");
666 LRI->LastOpNum = OpNum;
667 markRegUsedInInstr(LRI->PhysReg);
674 bool RAFast::setPhysReg(
MachineInstr *MI,
unsigned OpNum,
unsigned PhysReg) {
705 DEBUG(
dbgs() <<
"Scanning for through registers:");
709 if (!MO.
isReg())
continue;
715 if (ThroughRegs.
insert(Reg).second)
722 DEBUG(
dbgs() <<
"\nChecking for physdef collisions.\n");
726 unsigned Reg = MO.
getReg();
728 markRegUsedInInstr(Reg);
730 if (ThroughRegs.
count(PhysRegState[*AI]))
731 definePhysReg(MI, *AI, regFree);
736 DEBUG(
dbgs() <<
"Allocating tied uses.\n");
739 if (!MO.
isReg())
continue;
740 unsigned Reg = MO.
getReg();
745 DEBUG(
dbgs() <<
"Operand " << i <<
"("<< MO <<
") is tied to operand "
747 LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, 0);
748 unsigned PhysReg = LRI->PhysReg;
749 setPhysReg(MI, i, PhysReg);
753 DEBUG(
dbgs() <<
"Partial redefine: " << MO <<
"\n");
756 LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, 0);
761 DEBUG(
dbgs() <<
"Allocating early clobbers.\n");
764 if (!MO.
isReg())
continue;
765 unsigned Reg = MO.
getReg();
770 LiveRegMap::iterator LRI = defineVirtReg(MI, i, Reg, 0);
771 unsigned PhysReg = LRI->PhysReg;
772 if (setPhysReg(MI, i, PhysReg))
781 unsigned Reg = MO.
getReg();
784 <<
" as used in instr\n");
785 markRegUsedInInstr(Reg);
789 for (
unsigned i = 0, e = PartialDefs.
size(); i != e; ++i)
790 markRegUsedInInstr(PartialDefs[i]);
793 void RAFast::AllocateBasicBlock() {
794 DEBUG(
dbgs() <<
"\nAllocating " << *MBB);
796 PhysRegState.assign(TRI->getNumRegs(), regDisabled);
797 assert(LiveVirtRegs.empty() &&
"Mapping not cleared from last block?");
803 E = MBB->livein_end(); I != E; ++
I)
804 if (MRI->isAllocatable(*I))
805 definePhysReg(MII, *I, regReserved);
811 while (MII != MBB->end()) {
815 dbgs() <<
"\n>> " << *MI <<
"Regs:";
816 for (
unsigned Reg = 1, E = TRI->getNumRegs(); Reg != E; ++
Reg) {
817 if (PhysRegState[Reg] == regDisabled)
continue;
818 dbgs() <<
" " << TRI->getName(Reg);
819 switch(PhysRegState[Reg]) {
827 LiveRegMap::iterator I = findLiveVirtReg(PhysRegState[Reg]);
828 assert(I != LiveVirtRegs.end() &&
"Missing VirtReg entry");
831 assert(I->PhysReg == Reg &&
"Bad inverse map");
838 for (LiveRegMap::iterator i = LiveVirtRegs.begin(),
839 e = LiveVirtRegs.end(); i != e; ++i) {
844 assert(PhysRegState[i->PhysReg] == i->VirtReg &&
"Bad inverse map");
850 bool ScanDbgValue =
true;
851 while (ScanDbgValue) {
852 ScanDbgValue =
false;
855 if (!MO.
isReg())
continue;
856 unsigned Reg = MO.
getReg();
858 LiveRegMap::iterator LRI = findLiveVirtReg(Reg);
859 if (LRI != LiveVirtRegs.end())
860 setPhysReg(MI, i, LRI->PhysReg);
862 int SS = StackSlotForVirtReg[
Reg];
865 DEBUG(
dbgs() <<
"Unable to allocate vreg used by DBG_VALUE");
877 cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(DL) &&
878 "Expected inlined-at fields to agree");
885 DEBUG(
dbgs() <<
"Modifying debug info due to spill:"
893 LiveDbgValueMap[
Reg].push_back(MI);
901 unsigned CopySrc = 0, CopyDst = 0, CopySrcSub = 0, CopyDstSub = 0;
915 unsigned VirtOpEnd = 0;
916 bool hasTiedOps =
false;
917 bool hasEarlyClobbers =
false;
918 bool hasPartialRedefs =
false;
919 bool hasPhysDefs =
false;
924 MRI->addPhysRegsUsedFromRegMask(MO.
getRegMask());
927 if (!MO.
isReg())
continue;
928 unsigned Reg = MO.
getReg();
933 hasTiedOps = hasTiedOps ||
937 hasEarlyClobbers =
true;
939 hasPartialRedefs =
true;
943 if (!MRI->isAllocatable(Reg))
continue;
948 regFree : regReserved);
949 hasEarlyClobbers =
true;
963 if (MI->
isInlineAsm() || hasEarlyClobbers || hasPartialRedefs ||
964 (hasTiedOps && (hasPhysDefs || MCID.
getNumDefs() > 1))) {
965 handleThroughOperands(MI, VirtDead);
970 hasEarlyClobbers =
true;
975 for (
unsigned i = 0; i != VirtOpEnd; ++i) {
977 if (!MO.
isReg())
continue;
978 unsigned Reg = MO.
getReg();
981 LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, CopyDst);
982 unsigned PhysReg = LRI->PhysReg;
983 CopySrc = (CopySrc == Reg || CopySrc == PhysReg) ? PhysReg : 0;
984 if (setPhysReg(MI, i, PhysReg))
989 for (UsedInInstrSet::iterator
990 I = UsedInInstr.begin(), E = UsedInInstr.end(); I != E; ++
I)
991 MRI->setRegUnitUsed(*I);
996 if (hasEarlyClobbers) {
999 if (!MO.
isReg())
continue;
1000 unsigned Reg = MO.
getReg();
1004 markRegUsedInInstr(Reg);
1014 DefOpEnd = VirtOpEnd;
1015 DEBUG(
dbgs() <<
" Spilling remaining registers before call.\n");
1020 SkippedInstrs.insert(&MCID);
1025 for (
unsigned i = 0; i != DefOpEnd; ++i) {
1029 unsigned Reg = MO.
getReg();
1032 if (!MRI->isAllocatable(Reg))
continue;
1033 definePhysReg(MI, Reg, MO.
isDead() ? regFree : regReserved);
1036 LiveRegMap::iterator LRI = defineVirtReg(MI, i, Reg, CopySrc);
1037 unsigned PhysReg = LRI->PhysReg;
1038 if (setPhysReg(MI, i, PhysReg)) {
1042 CopyDst = (CopyDst == Reg || CopyDst == PhysReg) ? PhysReg : 0;
1049 for (
unsigned i = 0, e = VirtDead.
size(); i != e; ++i)
1050 killVirtReg(VirtDead[i]);
1053 for (UsedInInstrSet::iterator
1054 I = UsedInInstr.begin(), E = UsedInInstr.end(); I != E; ++
I)
1055 MRI->setRegUnitUsed(*I);
1057 if (CopyDst && CopyDst == CopySrc && CopyDstSub == CopySrcSub) {
1058 DEBUG(
dbgs() <<
"-- coalescing: " << *MI);
1066 DEBUG(
dbgs() <<
"Spilling live registers at end of block.\n");
1071 for (
unsigned i = 0, e = Coalesced.
size(); i != e; ++i)
1072 MBB->
erase(Coalesced[i]);
1073 NumCopies += Coalesced.
size();
1081 DEBUG(
dbgs() <<
"********** FAST REGISTER ALLOCATION **********\n"
1082 <<
"********** Function: " << Fn.
getName() <<
'\n');
1085 TRI = MF->getSubtarget().getRegisterInfo();
1086 TII = MF->getSubtarget().getInstrInfo();
1087 MRI->freezeReservedRegs(Fn);
1088 RegClassInfo.runOnMachineFunction(Fn);
1089 UsedInInstr.clear();
1090 UsedInInstr.setUniverse(TRI->getNumRegUnits());
1092 assert(!MRI->isSSA() &&
"regalloc requires leaving SSA");
1096 StackSlotForVirtReg.resize(MRI->getNumVirtRegs());
1097 LiveVirtRegs.setUniverse(MRI->getNumVirtRegs());
1101 MBBi != MBBe; ++MBBi) {
1103 AllocateBasicBlock();
1108 if (
const uint16_t *Defs = Desc->getImplicitDefs())
1110 MRI->setPhysRegUsed(*Defs++);
1114 MRI->clearVirtRegs();
1116 SkippedInstrs.clear();
1117 StackSlotForVirtReg.clear();
1118 LiveDbgValueMap.clear();
1123 return new RAFast();
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
void push_back(const T &Elt)
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
STATISTIC(NumFunctions,"Total number of functions")
static unsigned virtReg2Index(unsigned Reg)
virtReg2Index - Convert a virtual register number to a 0-based index.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
std::pair< iterator, bool > insert(const ValueT &Val)
insert - Attempts to insert a new element.
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
const DIExpression * getDebugExpression() const
Return the complex address expression referenced by this DBG_VALUE instruction.
std::vector< unsigned >::const_iterator livein_iterator
iterator getFirstTerminator()
getFirstTerminator - returns an iterator to the first terminator instruction of this basic block...
Describe properties that are true of each instruction in the target description file.
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
bool readsVirtualRegister(unsigned Reg) const
Return true if the MachineInstr reads the specified virtual register.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
void setIsDead(bool Val=true)
aarch64 collect AArch64 Collect Linker Optimization Hint(LOH)"
unsigned getSize() const
getSize - Return the size of the register in bytes, which is also the size of a stack slot allocated ...
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Reg
All possible values of the reg field in the ModR/M byte.
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
PrintReg - Helper class for printing registers on a raw_ostream.
bool isCopyLike() const
Return true if the instruction behaves like a copy.
DenseT::iterator iterator
RegisterRegAlloc class - Track the registration of register allocators.
const MachineBasicBlock * getParent() const
TargetInstrInfo - Interface to description of machine instruction set.
bool isDebugValue() const
DBG_VALUE - a mapping of the llvm.dbg.value intrinsic.
bool isEarlyClobber() const
bundle_iterator< MachineInstr, instr_iterator > iterator
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
unsigned getAlignment() const
getAlignment - Return the minimum required alignment for a register of this class.
bool isIndirectDebugValue() const
A DBG_VALUE is indirect iff the first operand is a register and the second operand is an immediate...
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
const MachineOperand & getOperand(unsigned i) const
MCRegAliasIterator enumerates all registers aliasing Reg.
Represent the analysis usage information of a pass.
FunctionPass class - This class is used to implement most global optimizations.
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
unsigned getSubReg() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void emitError(StringRef Msg) const
Emit an error referring to the source location of this instruction.
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
void setIsKill(bool Val=true)
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
const DILocalVariable * getDebugVariable() const
Return the debug variable referenced by this DBG_VALUE instruction.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
MachineOperand class - Representation of each machine instruction operand.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void addRegisterDefined(unsigned Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
static bool isPhysicalRegister(unsigned Reg)
isPhysicalRegister - Return true if the specified register number is in the physical register namespa...
SparseSet - Fast set implmentation for objects that can be identified by small unsigned keys...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static RegisterRegAlloc fastRegAlloc("fast","fast register allocator", createFastRegisterAllocator)
void setReg(unsigned Reg)
Change the register this operand corresponds to.
bool isCall(QueryType Type=AnyInBundle) const
void setSubReg(unsigned subReg)
unsigned getReg() const
getReg - Returns the register number.
FunctionPass * createFastRegisterAllocator()
FastRegisterAllocation Pass - This pass register allocates as fast as possible.
BasicBlockListType::iterator iterator
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
bool addRegisterKilled(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
bool contains(unsigned Reg) const
contains - Return true if the specified register is included in this register class.