LLVM  3.7.0
MachineRegisterInfo.cpp
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1 //===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Implementation of the MachineRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
16 #include "llvm/IR/Function.h"
21 
22 using namespace llvm;
23 
24 // Pin the vtable to this file.
25 void MachineRegisterInfo::Delegate::anchor() {}
26 
27 MachineRegisterInfo::MachineRegisterInfo(const MachineFunction *MF)
28  : MF(MF), TheDelegate(nullptr), IsSSA(true), TracksLiveness(true),
29  TracksSubRegLiveness(false) {
30  VRegInfo.reserve(256);
31  RegAllocHints.reserve(256);
32  UsedRegUnits.resize(getTargetRegisterInfo()->getNumRegUnits());
33  UsedPhysRegMask.resize(getTargetRegisterInfo()->getNumRegs());
34 
35  // Create the physreg use/def lists.
36  PhysRegUseDefLists.resize(getTargetRegisterInfo()->getNumRegs(), nullptr);
37 }
38 
39 /// setRegClass - Set the register class of the specified virtual register.
40 ///
41 void
43  assert(RC && RC->isAllocatable() && "Invalid RC for virtual register");
44  VRegInfo[Reg].first = RC;
45 }
46 
47 const TargetRegisterClass *
49  const TargetRegisterClass *RC,
50  unsigned MinNumRegs) {
51  const TargetRegisterClass *OldRC = getRegClass(Reg);
52  if (OldRC == RC)
53  return RC;
54  const TargetRegisterClass *NewRC =
56  if (!NewRC || NewRC == OldRC)
57  return NewRC;
58  if (NewRC->getNumRegs() < MinNumRegs)
59  return nullptr;
60  setRegClass(Reg, NewRC);
61  return NewRC;
62 }
63 
64 bool
67  const TargetRegisterClass *OldRC = getRegClass(Reg);
68  const TargetRegisterClass *NewRC =
70 
71  // Stop early if there is no room to grow.
72  if (NewRC == OldRC)
73  return false;
74 
75  // Accumulate constraints from all uses.
76  for (MachineOperand &MO : reg_nodbg_operands(Reg)) {
77  // Apply the effect of the given operand to NewRC.
78  MachineInstr *MI = MO.getParent();
79  unsigned OpNo = &MO - &MI->getOperand(0);
80  NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII,
82  if (!NewRC || NewRC == OldRC)
83  return false;
84  }
85  setRegClass(Reg, NewRC);
86  return true;
87 }
88 
89 /// createVirtualRegister - Create and return a new virtual register in the
90 /// function with the specified register class.
91 ///
92 unsigned
94  assert(RegClass && "Cannot create register without RegClass!");
95  assert(RegClass->isAllocatable() &&
96  "Virtual register RegClass must be allocatable.");
97 
98  // New virtual register number.
100  VRegInfo.grow(Reg);
101  VRegInfo[Reg].first = RegClass;
102  RegAllocHints.grow(Reg);
103  if (TheDelegate)
104  TheDelegate->MRI_NoteNewVirtualRegister(Reg);
105  return Reg;
106 }
107 
108 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
110 #ifndef NDEBUG
111  for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) {
113  if (!VRegInfo[Reg].second)
114  continue;
115  verifyUseList(Reg);
116  llvm_unreachable("Remaining virtual register operands");
117  }
118 #endif
119  VRegInfo.clear();
120 }
121 
123 #ifndef NDEBUG
124  bool Valid = true;
125  for (MachineOperand &M : reg_operands(Reg)) {
126  MachineOperand *MO = &M;
127  MachineInstr *MI = MO->getParent();
128  if (!MI) {
129  errs() << PrintReg(Reg, getTargetRegisterInfo())
130  << " use list MachineOperand " << MO
131  << " has no parent instruction.\n";
132  Valid = false;
133  continue;
134  }
135  MachineOperand *MO0 = &MI->getOperand(0);
136  unsigned NumOps = MI->getNumOperands();
137  if (!(MO >= MO0 && MO < MO0+NumOps)) {
138  errs() << PrintReg(Reg, getTargetRegisterInfo())
139  << " use list MachineOperand " << MO
140  << " doesn't belong to parent MI: " << *MI;
141  Valid = false;
142  }
143  if (!MO->isReg()) {
144  errs() << PrintReg(Reg, getTargetRegisterInfo())
145  << " MachineOperand " << MO << ": " << *MO
146  << " is not a register\n";
147  Valid = false;
148  }
149  if (MO->getReg() != Reg) {
150  errs() << PrintReg(Reg, getTargetRegisterInfo())
151  << " use-list MachineOperand " << MO << ": "
152  << *MO << " is the wrong register\n";
153  Valid = false;
154  }
155  }
156  assert(Valid && "Invalid use list");
157 #endif
158 }
159 
161 #ifndef NDEBUG
162  for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i)
164  for (unsigned i = 1, e = getTargetRegisterInfo()->getNumRegs(); i != e; ++i)
165  verifyUseList(i);
166 #endif
167 }
168 
169 /// Add MO to the linked list of operands for its register.
171  assert(!MO->isOnRegUseList() && "Already on list");
172  MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
173  MachineOperand *const Head = HeadRef;
174 
175  // Head points to the first list element.
176  // Next is NULL on the last list element.
177  // Prev pointers are circular, so Head->Prev == Last.
178 
179  // Head is NULL for an empty list.
180  if (!Head) {
181  MO->Contents.Reg.Prev = MO;
182  MO->Contents.Reg.Next = nullptr;
183  HeadRef = MO;
184  return;
185  }
186  assert(MO->getReg() == Head->getReg() && "Different regs on the same list!");
187 
188  // Insert MO between Last and Head in the circular Prev chain.
189  MachineOperand *Last = Head->Contents.Reg.Prev;
190  assert(Last && "Inconsistent use list");
191  assert(MO->getReg() == Last->getReg() && "Different regs on the same list!");
192  Head->Contents.Reg.Prev = MO;
193  MO->Contents.Reg.Prev = Last;
194 
195  // Def operands always precede uses. This allows def_iterator to stop early.
196  // Insert def operands at the front, and use operands at the back.
197  if (MO->isDef()) {
198  // Insert def at the front.
199  MO->Contents.Reg.Next = Head;
200  HeadRef = MO;
201  } else {
202  // Insert use at the end.
203  MO->Contents.Reg.Next = nullptr;
204  Last->Contents.Reg.Next = MO;
205  }
206 }
207 
208 /// Remove MO from its use-def list.
210  assert(MO->isOnRegUseList() && "Operand not on use list");
211  MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
212  MachineOperand *const Head = HeadRef;
213  assert(Head && "List already empty");
214 
215  // Unlink this from the doubly linked list of operands.
216  MachineOperand *Next = MO->Contents.Reg.Next;
217  MachineOperand *Prev = MO->Contents.Reg.Prev;
218 
219  // Prev links are circular, next link is NULL instead of looping back to Head.
220  if (MO == Head)
221  HeadRef = Next;
222  else
223  Prev->Contents.Reg.Next = Next;
224 
225  (Next ? Next : Head)->Contents.Reg.Prev = Prev;
226 
227  MO->Contents.Reg.Prev = nullptr;
228  MO->Contents.Reg.Next = nullptr;
229 }
230 
231 /// Move NumOps operands from Src to Dst, updating use-def lists as needed.
232 ///
233 /// The Dst range is assumed to be uninitialized memory. (Or it may contain
234 /// operands that won't be destroyed, which is OK because the MO destructor is
235 /// trivial anyway).
236 ///
237 /// The Src and Dst ranges may overlap.
239  MachineOperand *Src,
240  unsigned NumOps) {
241  assert(Src != Dst && NumOps && "Noop moveOperands");
242 
243  // Copy backwards if Dst is within the Src range.
244  int Stride = 1;
245  if (Dst >= Src && Dst < Src + NumOps) {
246  Stride = -1;
247  Dst += NumOps - 1;
248  Src += NumOps - 1;
249  }
250 
251  // Copy one operand at a time.
252  do {
253  new (Dst) MachineOperand(*Src);
254 
255  // Dst takes Src's place in the use-def chain.
256  if (Src->isReg()) {
257  MachineOperand *&Head = getRegUseDefListHead(Src->getReg());
258  MachineOperand *Prev = Src->Contents.Reg.Prev;
259  MachineOperand *Next = Src->Contents.Reg.Next;
260  assert(Head && "List empty, but operand is chained");
261  assert(Prev && "Operand was not on use-def list");
262 
263  // Prev links are circular, next link is NULL instead of looping back to
264  // Head.
265  if (Src == Head)
266  Head = Dst;
267  else
268  Prev->Contents.Reg.Next = Dst;
269 
270  // Update Prev pointer. This also works when Src was pointing to itself
271  // in a 1-element list. In that case Head == Dst.
272  (Next ? Next : Head)->Contents.Reg.Prev = Dst;
273  }
274 
275  Dst += Stride;
276  Src += Stride;
277  } while (--NumOps);
278 }
279 
280 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
281 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
282 /// except that it also changes any definitions of the register as well.
283 /// If ToReg is a physical register we apply the sub register to obtain the
284 /// final/proper physical register.
285 void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
286  assert(FromReg != ToReg && "Cannot replace a reg with itself");
287 
289 
290  // TODO: This could be more efficient by bulk changing the operands.
291  for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) {
292  MachineOperand &O = *I;
293  ++I;
295  O.substPhysReg(ToReg, *TRI);
296  } else {
297  O.setReg(ToReg);
298  }
299  }
300 }
301 
302 /// getVRegDef - Return the machine instr that defines the specified virtual
303 /// register or null if none is found. This assumes that the code is in SSA
304 /// form, so there should only be one definition.
306  // Since we are in SSA form, we can use the first definition.
308  assert((I.atEnd() || std::next(I) == def_instr_end()) &&
309  "getVRegDef assumes a single definition or no definition");
310  return !I.atEnd() ? &*I : nullptr;
311 }
312 
313 /// getUniqueVRegDef - Return the unique machine instr that defines the
314 /// specified virtual register or null if none is found. If there are
315 /// multiple definitions or no definition, return null.
317  if (def_empty(Reg)) return nullptr;
319  if (std::next(I) != def_instr_end())
320  return nullptr;
321  return &*I;
322 }
323 
324 bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const {
326  if (UI == use_nodbg_end())
327  return false;
328  return ++UI == use_nodbg_end();
329 }
330 
331 /// clearKillFlags - Iterate over all the uses of the given register and
332 /// clear the kill flag from the MachineOperand. This function is used by
333 /// optimization passes which extend register lifetimes and need only
334 /// preserve conservative kill flag information.
336  for (MachineOperand &MO : use_operands(Reg))
337  MO.setIsKill(false);
338 }
339 
340 bool MachineRegisterInfo::isLiveIn(unsigned Reg) const {
341  for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
342  if (I->first == Reg || I->second == Reg)
343  return true;
344  return false;
345 }
346 
347 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
348 /// corresponding live-in physical register.
349 unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const {
350  for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
351  if (I->second == VReg)
352  return I->first;
353  return 0;
354 }
355 
356 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
357 /// corresponding live-in physical register.
358 unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const {
359  for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
360  if (I->first == PReg)
361  return I->second;
362  return 0;
363 }
364 
365 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
366 /// into the given entry block.
367 void
369  const TargetRegisterInfo &TRI,
370  const TargetInstrInfo &TII) {
371  // Emit the copies into the top of the block.
372  for (unsigned i = 0, e = LiveIns.size(); i != e; ++i)
373  if (LiveIns[i].second) {
374  if (use_empty(LiveIns[i].second)) {
375  // The livein has no uses. Drop it.
376  //
377  // It would be preferable to have isel avoid creating live-in
378  // records for unused arguments in the first place, but it's
379  // complicated by the debug info code for arguments.
380  LiveIns.erase(LiveIns.begin() + i);
381  --i; --e;
382  } else {
383  // Emit a copy.
384  BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(),
385  TII.get(TargetOpcode::COPY), LiveIns[i].second)
386  .addReg(LiveIns[i].first);
387 
388  // Add the register to the entry block live-in set.
389  EntryMBB->addLiveIn(LiveIns[i].first);
390  }
391  } else {
392  // Add the register to the entry block live-in set.
393  EntryMBB->addLiveIn(LiveIns[i].first);
394  }
395 }
396 
398 {
399  // Lane masks are only defined for vregs.
401  const TargetRegisterClass &TRC = *getRegClass(Reg);
402  return TRC.getLaneMask();
403 }
404 
405 #ifndef NDEBUG
406 void MachineRegisterInfo::dumpUses(unsigned Reg) const {
407  for (MachineInstr &I : use_instructions(Reg))
408  I.dump();
409 }
410 #endif
411 
413  ReservedRegs = getTargetRegisterInfo()->getReservedRegs(MF);
414  assert(ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs() &&
415  "Invalid ReservedRegs vector from target");
416 }
417 
419  const MachineFunction &MF) const {
421 
422  // Check if any overlapping register is modified, or allocatable so it may be
423  // used later.
424  for (MCRegAliasIterator AI(PhysReg, getTargetRegisterInfo(), true);
425  AI.isValid(); ++AI)
426  if (!def_empty(*AI) || isAllocatable(*AI))
427  return false;
428  return true;
429 }
430 
431 /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
432 /// specified register as undefined which causes the DBG_VALUE to be
433 /// deleted during LiveDebugVariables analysis.
435  // Mark any DBG_VALUE that uses Reg as undef (but don't delete it.)
438  I != E; I = nextI) {
439  nextI = std::next(I); // I is invalidated by the setReg
440  MachineInstr *UseMI = &*I;
441  if (UseMI->isDebugValue())
442  UseMI->getOperand(0).setReg(0U);
443  }
444 }
445 
446 static const Function *getCalledFunction(const MachineInstr &MI) {
447  for (const MachineOperand &MO : MI.operands()) {
448  if (!MO.isGlobal())
449  continue;
450  const Function *Func = dyn_cast<Function>(MO.getGlobal());
451  if (Func != nullptr)
452  return Func;
453  }
454  return nullptr;
455 }
456 
457 static bool isNoReturnDef(const MachineOperand &MO) {
458  // Anything which is not a noreturn function is a real def.
459  const MachineInstr &MI = *MO.getParent();
460  if (!MI.isCall())
461  return false;
462  const MachineBasicBlock &MBB = *MI.getParent();
463  if (!MBB.succ_empty())
464  return false;
465  const MachineFunction &MF = *MBB.getParent();
466  // We need to keep correct unwind information even if the function will
467  // not return, since the runtime may need it.
469  return false;
470  const Function *Called = getCalledFunction(MI);
471  if (Called == nullptr || !Called->hasFnAttribute(Attribute::NoReturn)
472  || !Called->hasFnAttribute(Attribute::NoUnwind))
473  return false;
474 
475  return true;
476 }
477 
478 bool MachineRegisterInfo::isPhysRegModified(unsigned PhysReg) const {
479  if (UsedPhysRegMask.test(PhysReg))
480  return true;
482  for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI) {
483  for (const MachineOperand &MO : make_range(def_begin(*AI), def_end())) {
484  if (isNoReturnDef(MO))
485  continue;
486  return true;
487  }
488  }
489  return false;
490 }
bool isConstantPhysReg(unsigned PhysReg, const MachineFunction &MF) const
isConstantPhysReg - Returns true if PhysReg is unallocatable and constant throughout the function...
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Definition: BitVector.h:192
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
void EmitLiveInCopies(MachineBasicBlock *EntryMBB, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII)
EmitLiveInCopies - Emit copies to initialize livein virtual registers into the given entry block...
size_type size() const
size - Returns the number of bits in this bitvector.
Definition: BitVector.h:118
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
livein_iterator livein_end() const
static unsigned index2VirtReg(unsigned Index)
index2VirtReg - Convert a 0-based index to a virtual register number.
bool isPhysRegModified(unsigned PhysReg) const
Return true if the specified register is modified in this function.
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
iterator_range< use_iterator > use_operands(unsigned Reg) const
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
iterator_range< reg_iterator > reg_operands(unsigned Reg) const
void addLiveIn(unsigned Reg)
Adds the specified register as a live in.
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const
getCommonSubClass - find the largest common subclass of A and B.
A debug info location.
Definition: DebugLoc.h:34
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:295
void markUsesInDebugValueAsUndef(unsigned Reg) const
markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the specified register as undefined wh...
static use_nodbg_iterator use_nodbg_end()
void clearVirtRegs()
clearVirtRegs - Remove all virtual registers (after physreg assignment).
const TargetRegisterClass * getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.
unsigned getMaxLaneMaskForVReg(unsigned Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
COPY - Target-independent register copy.
Definition: TargetOpcodes.h:86
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const HexagonInstrInfo * TII
const TargetRegisterInfo * getTargetRegisterInfo() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
use_instr_iterator use_instr_begin(unsigned RegNo) const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
const TargetRegisterClass * getRegClass(unsigned Reg) const
getRegClass - Return the register class of the specified virtual register.
void freezeReservedRegs(const MachineFunction &)
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
Reg
All possible values of the reg field in the ModR/M byte.
Function must be in a unwind table.
Definition: Attributes.h:118
#define false
Definition: ConvertUTF.c:65
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:271
defusechain_iterator - This class provides iterator support for machine operands in the function that...
PrintReg - Helper class for printing registers on a raw_ostream.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
bool isLiveIn(unsigned Reg) const
static def_instr_iterator def_instr_end()
bool atEnd() const
atEnd - return true if this iterator is equal to reg_end() on the value.
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:120
TargetInstrInfo - Interface to description of machine instruction set.
bool isDebugValue() const
Definition: MachineInstr.h:748
#define true
Definition: ConvertUTF.c:66
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
unsigned getLiveInVirtReg(unsigned PReg) const
getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in physical ...
MCRegAliasIterator enumerates all registers aliasing Reg.
void substPhysReg(unsigned Reg, const TargetRegisterInfo &)
substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...
Function doesn't unwind stack.
Definition: Attributes.h:96
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
Mark the function as not returning.
Definition: Attributes.h:95
iterator_range< use_instr_iterator > use_instructions(unsigned Reg) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
struct llvm::MachineOperand::@33::@34 Reg
static const Function * getCalledFunction(const MachineInstr &MI)
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
unsigned getLaneMask() const
Returns the combination of all lane masks of register in this class.
MachineOperand class - Representation of each machine instruction operand.
bool test(unsigned Idx) const
Definition: BitVector.h:322
bool isAllocatable(unsigned PhysReg) const
isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn't been...
livein_iterator livein_begin() const
bool recomputeRegClass(unsigned Reg)
recomputeRegClass - Try to find a legal super-class of Reg's register class that still satisfies the ...
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a ...
unsigned getNumRegs() const
getNumRegs - Return the number of registers in this class.
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:285
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
void replaceRegWith(unsigned FromReg, unsigned ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
def_iterator def_begin(unsigned RegNo) const
void verifyUseList(unsigned Reg) const
Verify the sanity of the use list for Reg.
Representation of each machine instruction.
Definition: MachineInstr.h:51
static bool isPhysicalRegister(unsigned Reg)
isPhysicalRegister - Return true if the specified register number is in the physical register namespa...
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:217
def_instr_iterator def_instr_begin(unsigned RegNo) const
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
void setReg(unsigned Reg)
Change the register this operand corresponds to.
#define I(x, y, z)
Definition: MD5.cpp:54
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:403
bool isAllocatable() const
isAllocatable - Return true if this register class may be used to create virtual registers.
void clearKillFlags(unsigned Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
std::vector< std::pair< unsigned, unsigned > >::const_iterator livein_iterator
unsigned getReg() const
getReg - Returns the register number.
iterator_range< reg_nodbg_iterator > reg_nodbg_operands(unsigned Reg) const
void dumpUses(unsigned RegNo) const
static def_iterator def_end()
virtual const TargetInstrInfo * getInstrInfo() const
static bool isNoReturnDef(const MachineOperand &MO)
void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps)
Move NumOps operands from Src to Dst, updating use-def lists as needed.
static use_instr_iterator use_instr_end()
bool def_empty(unsigned RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
void setRegClass(unsigned Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
reg_iterator reg_begin(unsigned RegNo) const
virtual void MRI_NoteNewVirtualRegister(unsigned Reg)=0
void verifyUseLists() const
Verify the use list of all registers.
static reg_iterator reg_end()
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
getLargestLegalSuperClass - Returns the largest super class of RC that is legal to use in the current...
unsigned getLiveInPhysReg(unsigned VReg) const
getLiveInPhysReg - If VReg is a live-in virtual register, return the corresponding live-in physical r...
bool use_empty(unsigned RegNo) const
use_empty - Return true if there are no instructions using the specified register.
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.