LLVM  3.7.0
Public Member Functions | List of all members
llvm::DefaultVLIWScheduler Class Reference
Inheritance diagram for llvm::DefaultVLIWScheduler:
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Collaboration diagram for llvm::DefaultVLIWScheduler:
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Public Member Functions

 DefaultVLIWScheduler (MachineFunction &MF, MachineLoopInfo &MLI, bool IsPostRA)
 
void schedule () override
 schedule - Order nodes according to selected style, filling in the Sequence member. More...
 
- Public Member Functions inherited from llvm::ScheduleDAGInstrs
 ScheduleDAGInstrs (MachineFunction &mf, const MachineLoopInfo *mli, bool IsPostRAFlag, bool RemoveKillFlags=false, LiveIntervals *LIS=nullptr)
 
 ~ScheduleDAGInstrs () override
 
bool isPostRA () const
 
LiveIntervalsgetLIS () const
 Expose LiveIntervals for use in DAG mutators and such. More...
 
const TargetSchedModelgetSchedModel () const
 Get the machine model for instruction scheduling. More...
 
const MCSchedClassDescgetSchedClass (SUnit *SU) const
 Resolve and cache a resolved scheduling class for an SUnit. More...
 
MachineBasicBlock::iterator begin () const
 begin - Return an iterator to the top of the current scheduling region. More...
 
MachineBasicBlock::iterator end () const
 end - Return an iterator to the bottom of the current scheduling region. More...
 
SUnitnewSUnit (MachineInstr *MI)
 newSUnit - Creates a new SUnit and return a ptr to it. More...
 
SUnitgetSUnit (MachineInstr *MI) const
 getSUnit - Return an existing SUnit for this MI, or NULL. More...
 
virtual void startBlock (MachineBasicBlock *BB)
 startBlock - Prepare to perform scheduling in the given block. More...
 
virtual void finishBlock ()
 finishBlock - Clean up after scheduling in the given block. More...
 
virtual void enterRegion (MachineBasicBlock *bb, MachineBasicBlock::iterator begin, MachineBasicBlock::iterator end, unsigned regioninstrs)
 Initialize the scheduler state for the next scheduling region. More...
 
virtual void exitRegion ()
 Notify that the scheduler has finished scheduling the current region. More...
 
void buildSchedGraph (AliasAnalysis *AA, RegPressureTracker *RPTracker=nullptr, PressureDiffs *PDiffs=nullptr)
 buildSchedGraph - Build SUnits from the MachineBasicBlock that we are input. More...
 
void addSchedBarrierDeps ()
 addSchedBarrierDeps - Add dependencies from instructions in the current list of instructions being scheduled to scheduling barrier. More...
 
virtual void finalizeSchedule ()
 finalizeSchedule - Allow targets to perform final scheduling actions at the level of the whole MachineFunction. More...
 
void dumpNode (const SUnit *SU) const override
 
std::string getGraphNodeLabel (const SUnit *SU) const override
 Return a label for a DAG node that points to an instruction. More...
 
std::string getDAGName () const override
 Return a label for the region of code covered by the DAG. More...
 
void fixupKills (MachineBasicBlock *MBB)
 Fix register kill flags that scheduling has made invalid. More...
 
- Public Member Functions inherited from llvm::ScheduleDAG
 ScheduleDAG (MachineFunction &mf)
 
virtual ~ScheduleDAG ()
 
void clearDAG ()
 clearDAG - clear the DAG state (between regions). More...
 
const MCInstrDescgetInstrDesc (const SUnit *SU) const
 getInstrDesc - Return the MCInstrDesc of this SUnit. More...
 
virtual void viewGraph (const Twine &Name, const Twine &Title)
 viewGraph - Pop up a GraphViz/gv window with the ScheduleDAG rendered using 'dot'. More...
 
virtual void viewGraph ()
 Out-of-line implementation with no arguments is handy for gdb. More...
 
virtual void addCustomGraphFeatures (GraphWriter< ScheduleDAG * > &) const
 addCustomGraphFeatures - Add custom features for a visualization of the ScheduleDAG. More...
 
unsigned VerifyScheduledDAG (bool isBottomUp)
 VerifyScheduledDAG - Verify that all SUnits were scheduled and that their state is consistent. More...
 

Additional Inherited Members

- Public Attributes inherited from llvm::ScheduleDAG
const TargetMachineTM
 
const TargetInstrInfoTII
 
const TargetRegisterInfoTRI
 
MachineFunctionMF
 
MachineRegisterInfoMRI
 
std::vector< SUnitSUnits
 
SUnit EntrySU
 
SUnit ExitSU
 
bool StressSched
 
- Protected Types inherited from llvm::ScheduleDAGInstrs
typedef std::vector< std::pair
< MachineInstr *, MachineInstr * > > 
DbgValueVector
 DbgValues - Remember instruction that precedes DBG_VALUE. More...
 
- Protected Member Functions inherited from llvm::ScheduleDAGInstrs
void initSUnits ()
 Create an SUnit for each real instruction, numbered in top-down toplological order. More...
 
void addPhysRegDataDeps (SUnit *SU, unsigned OperIdx)
 MO is an operand of SU's instruction that defines a physical register. More...
 
void addPhysRegDeps (SUnit *SU, unsigned OperIdx)
 addPhysRegDeps - Add register dependencies (data, anti, and output) from this SUnit to following instructions in the same scheduling region that depend the physical register referenced at OperIdx. More...
 
void addVRegDefDeps (SUnit *SU, unsigned OperIdx)
 addVRegDefDeps - Add register output and data dependencies from this SUnit to instructions that occur later in the same scheduling region if they read from or write to the virtual register defined at OperIdx. More...
 
void addVRegUseDeps (SUnit *SU, unsigned OperIdx)
 addVRegUseDeps - Add a register data dependency if the instruction that defines the virtual register used at OperIdx is mapped to an SUnit. More...
 
void startBlockForKills (MachineBasicBlock *BB)
 PostRA helper for rewriting kill flags. More...
 
bool toggleKillFlag (MachineInstr *MI, MachineOperand &MO)
 Toggle a register operand kill flag. More...
 
- Protected Attributes inherited from llvm::ScheduleDAGInstrs
const MachineLoopInfoMLI
 
const MachineFrameInfoMFI
 
LiveIntervalsLIS
 Live Intervals provides reaching defs in preRA scheduling. More...
 
TargetSchedModel SchedModel
 TargetSchedModel provides an interface to the machine model. More...
 
bool IsPostRA
 isPostRA flag indicates vregs cannot be present. More...
 
bool RemoveKillFlags
 True if the DAG builder should remove kill flags (in preparation for rescheduling). More...
 
bool CanHandleTerminators
 The standard DAG builder does not normally include terminators as DAG nodes because it does not create the necessary dependencies to prevent reordering. More...
 
MachineBasicBlockBB
 State specific to the current scheduling region. More...
 
MachineBasicBlock::iterator RegionBegin
 The beginning of the range to be scheduled. More...
 
MachineBasicBlock::iterator RegionEnd
 The end of the range to be scheduled. More...
 
unsigned NumRegionInstrs
 Instructions in this region (distance(RegionBegin, RegionEnd)). More...
 
DenseMap< MachineInstr *, SUnit * > MISUnitMap
 After calling BuildSchedGraph, each machine instruction in the current scheduling region is mapped to an SUnit. More...
 
VReg2UseMap VRegUses
 After calling BuildSchedGraph, each vreg used in the scheduling region is mapped to a set of SUnits. More...
 
Reg2SUnitsMap Defs
 State internal to DAG building. More...
 
Reg2SUnitsMap Uses
 
VReg2SUnitMap VRegDefs
 Track the last instruction in this region defining each virtual register. More...
 
std::vector< SUnit * > PendingLoads
 PendingLoads - Remember where unknown loads are after the most recent unknown store, as we iterate. More...
 
DbgValueVector DbgValues
 
MachineInstrFirstDbgValue
 
BitVector LiveRegs
 Set of live physical registers for updating kill flags. More...
 

Detailed Description

Definition at line 106 of file DFAPacketizer.cpp.

Constructor & Destructor Documentation

DefaultVLIWScheduler::DefaultVLIWScheduler ( MachineFunction MF,
MachineLoopInfo MLI,
bool  IsPostRA 
)

Definition at line 115 of file DFAPacketizer.cpp.

References llvm::ScheduleDAGInstrs::CanHandleTerminators.

Member Function Documentation

void DefaultVLIWScheduler::schedule ( )
overridevirtual

schedule - Order nodes according to selected style, filling in the Sequence member.

Typically, a scheduling algorithm will implement schedule() without overriding enterRegion() or exitRegion().

Implements llvm::ScheduleDAGInstrs.

Definition at line 121 of file DFAPacketizer.cpp.

References llvm::ScheduleDAGInstrs::buildSchedGraph().

Referenced by llvm::VLIWPacketizerList::PacketizeMIs().


The documentation for this class was generated from the following file: