LLVM  3.7.0
MipsFastISel.cpp
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1 //===-- MipsastISel.cpp - Mips FastISel implementation
2 //---------------------===//
3 
4 #include "MipsCCState.h"
5 #include "MipsInstrInfo.h"
6 #include "MipsISelLowering.h"
7 #include "MipsMachineFunction.h"
8 #include "MipsRegisterInfo.h"
9 #include "MipsSubtarget.h"
10 #include "MipsTargetMachine.h"
12 #include "llvm/CodeGen/FastISel.h"
17 #include "llvm/IR/GlobalAlias.h"
18 #include "llvm/IR/GlobalVariable.h"
19 #include "llvm/MC/MCSymbol.h"
21 
22 using namespace llvm;
23 
24 namespace {
25 
26 class MipsFastISel final : public FastISel {
27 
28  // All possible address modes.
29  class Address {
30  public:
31  typedef enum { RegBase, FrameIndexBase } BaseKind;
32 
33  private:
34  BaseKind Kind;
35  union {
36  unsigned Reg;
37  int FI;
38  } Base;
39 
40  int64_t Offset;
41 
42  const GlobalValue *GV;
43 
44  public:
45  // Innocuous defaults for our address.
46  Address() : Kind(RegBase), Offset(0), GV(0) { Base.Reg = 0; }
47  void setKind(BaseKind K) { Kind = K; }
48  BaseKind getKind() const { return Kind; }
49  bool isRegBase() const { return Kind == RegBase; }
50  bool isFIBase() const { return Kind == FrameIndexBase; }
51  void setReg(unsigned Reg) {
52  assert(isRegBase() && "Invalid base register access!");
53  Base.Reg = Reg;
54  }
55  unsigned getReg() const {
56  assert(isRegBase() && "Invalid base register access!");
57  return Base.Reg;
58  }
59  void setFI(unsigned FI) {
60  assert(isFIBase() && "Invalid base frame index access!");
61  Base.FI = FI;
62  }
63  unsigned getFI() const {
64  assert(isFIBase() && "Invalid base frame index access!");
65  return Base.FI;
66  }
67 
68  void setOffset(int64_t Offset_) { Offset = Offset_; }
69  int64_t getOffset() const { return Offset; }
70  void setGlobalValue(const GlobalValue *G) { GV = G; }
71  const GlobalValue *getGlobalValue() { return GV; }
72  };
73 
74  /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
75  /// make the right decision when generating code for different targets.
76  const TargetMachine &TM;
77  const MipsSubtarget *Subtarget;
78  const TargetInstrInfo &TII;
79  const TargetLowering &TLI;
80  MipsFunctionInfo *MFI;
81 
82  // Convenience variables to avoid some queries.
83  LLVMContext *Context;
84 
85  bool fastLowerCall(CallLoweringInfo &CLI) override;
86  bool fastLowerIntrinsicCall(const IntrinsicInst *II) override;
87 
88  bool TargetSupported;
89  bool UnsupportedFPMode; // To allow fast-isel to proceed and just not handle
90  // floating point but not reject doing fast-isel in other
91  // situations
92 
93 private:
94  // Selection routines.
95  bool selectLogicalOp(const Instruction *I);
96  bool selectLoad(const Instruction *I);
97  bool selectStore(const Instruction *I);
98  bool selectBranch(const Instruction *I);
99  bool selectSelect(const Instruction *I);
100  bool selectCmp(const Instruction *I);
101  bool selectFPExt(const Instruction *I);
102  bool selectFPTrunc(const Instruction *I);
103  bool selectFPToInt(const Instruction *I, bool IsSigned);
104  bool selectRet(const Instruction *I);
105  bool selectTrunc(const Instruction *I);
106  bool selectIntExt(const Instruction *I);
107  bool selectShift(const Instruction *I);
108  bool selectDivRem(const Instruction *I, unsigned ISDOpcode);
109 
110  // Utility helper routines.
111  bool isTypeLegal(Type *Ty, MVT &VT);
112  bool isTypeSupported(Type *Ty, MVT &VT);
113  bool isLoadTypeLegal(Type *Ty, MVT &VT);
114  bool computeAddress(const Value *Obj, Address &Addr);
115  bool computeCallAddress(const Value *V, Address &Addr);
116  void simplifyAddress(Address &Addr);
117 
118  // Emit helper routines.
119  bool emitCmp(unsigned DestReg, const CmpInst *CI);
120  bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
121  unsigned Alignment = 0);
122  bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
123  MachineMemOperand *MMO = nullptr);
124  bool emitStore(MVT VT, unsigned SrcReg, Address &Addr,
125  unsigned Alignment = 0);
126  unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
127  bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
128 
129  bool IsZExt);
130  bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
131 
132  bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
133  bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
134  unsigned DestReg);
135  bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
136  unsigned DestReg);
137 
138  unsigned getRegEnsuringSimpleIntegerWidening(const Value *, bool IsUnsigned);
139 
140  unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
141  const Value *RHS);
142 
143  unsigned materializeFP(const ConstantFP *CFP, MVT VT);
144  unsigned materializeGV(const GlobalValue *GV, MVT VT);
145  unsigned materializeInt(const Constant *C, MVT VT);
146  unsigned materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
147  unsigned materializeExternalCallSym(MCSymbol *Syn);
148 
149  MachineInstrBuilder emitInst(unsigned Opc) {
150  return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
151  }
152  MachineInstrBuilder emitInst(unsigned Opc, unsigned DstReg) {
153  return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
154  DstReg);
155  }
156  MachineInstrBuilder emitInstStore(unsigned Opc, unsigned SrcReg,
157  unsigned MemReg, int64_t MemOffset) {
158  return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
159  }
160  MachineInstrBuilder emitInstLoad(unsigned Opc, unsigned DstReg,
161  unsigned MemReg, int64_t MemOffset) {
162  return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset);
163  }
164 
165  unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
166  const TargetRegisterClass *RC,
167  unsigned Op0, bool Op0IsKill,
168  unsigned Op1, bool Op1IsKill);
169 
170  // for some reason, this default is not generated by tablegen
171  // so we explicitly generate it here.
172  //
173  unsigned fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC,
174  unsigned Op0, bool Op0IsKill, uint64_t imm1,
175  uint64_t imm2, unsigned Op3, bool Op3IsKill) {
176  return 0;
177  }
178 
179  // Call handling routines.
180 private:
181  CCAssignFn *CCAssignFnForCall(CallingConv::ID CC) const;
182  bool processCallArgs(CallLoweringInfo &CLI, SmallVectorImpl<MVT> &ArgVTs,
183  unsigned &NumBytes);
184  bool finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);
185 
186 public:
187  // Backend specific FastISel code.
188  explicit MipsFastISel(FunctionLoweringInfo &funcInfo,
189  const TargetLibraryInfo *libInfo)
190  : FastISel(funcInfo, libInfo), TM(funcInfo.MF->getTarget()),
191  Subtarget(&funcInfo.MF->getSubtarget<MipsSubtarget>()),
192  TII(*Subtarget->getInstrInfo()), TLI(*Subtarget->getTargetLowering()) {
193  MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
194  Context = &funcInfo.Fn->getContext();
195  TargetSupported =
196  ((TM.getRelocationModel() == Reloc::PIC_) &&
197  ((Subtarget->hasMips32r2() || Subtarget->hasMips32()) &&
198  (static_cast<const MipsTargetMachine &>(TM).getABI().IsO32())));
199  UnsupportedFPMode = Subtarget->isFP64bit();
200  }
201 
202  unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
203  unsigned fastMaterializeConstant(const Constant *C) override;
204  bool fastSelectInstruction(const Instruction *I) override;
205 
206 #include "MipsGenFastISel.inc"
207 };
208 } // end anonymous namespace.
209 
210 static bool CC_Mips(unsigned ValNo, MVT ValVT, MVT LocVT,
211  CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
213 
214 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, MVT LocVT,
215  CCValAssign::LocInfo LocInfo,
216  ISD::ArgFlagsTy ArgFlags, CCState &State) {
217  llvm_unreachable("should not be called");
218 }
219 
220 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT,
221  CCValAssign::LocInfo LocInfo,
222  ISD::ArgFlagsTy ArgFlags, CCState &State) {
223  llvm_unreachable("should not be called");
224 }
225 
226 #include "MipsGenCallingConv.inc"
227 
228 CCAssignFn *MipsFastISel::CCAssignFnForCall(CallingConv::ID CC) const {
229  return CC_MipsO32;
230 }
231 
232 unsigned MipsFastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,
233  const Value *LHS, const Value *RHS) {
234  // Canonicalize immediates to the RHS first.
235  if (isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS))
236  std::swap(LHS, RHS);
237 
238  unsigned Opc;
239  if (ISDOpc == ISD::AND) {
240  Opc = Mips::AND;
241  } else if (ISDOpc == ISD::OR) {
242  Opc = Mips::OR;
243  } else if (ISDOpc == ISD::XOR) {
244  Opc = Mips::XOR;
245  } else
246  llvm_unreachable("unexpected opcode");
247 
248  unsigned LHSReg = getRegForValue(LHS);
249  unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
250  if (!ResultReg)
251  return 0;
252 
253  unsigned RHSReg;
254  if (!LHSReg)
255  return 0;
256 
257  if (const auto *C = dyn_cast<ConstantInt>(RHS))
258  RHSReg = materializeInt(C, MVT::i32);
259  else
260  RHSReg = getRegForValue(RHS);
261 
262  if (!RHSReg)
263  return 0;
264 
265  emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg);
266  return ResultReg;
267 }
268 
269 unsigned MipsFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
270  if (!TargetSupported)
271  return 0;
272 
273  assert(TLI.getValueType(DL, AI->getType(), true) == MVT::i32 &&
274  "Alloca should always return a pointer.");
275 
277  FuncInfo.StaticAllocaMap.find(AI);
278 
279  if (SI != FuncInfo.StaticAllocaMap.end()) {
280  unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
281  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::LEA_ADDiu),
282  ResultReg)
283  .addFrameIndex(SI->second)
284  .addImm(0);
285  return ResultReg;
286  }
287 
288  return 0;
289 }
290 
291 unsigned MipsFastISel::materializeInt(const Constant *C, MVT VT) {
292  if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
293  return 0;
294  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
295  const ConstantInt *CI = cast<ConstantInt>(C);
296  return materialize32BitInt(CI->getZExtValue(), RC);
297 }
298 
299 unsigned MipsFastISel::materialize32BitInt(int64_t Imm,
300  const TargetRegisterClass *RC) {
301  unsigned ResultReg = createResultReg(RC);
302 
303  if (isInt<16>(Imm)) {
304  unsigned Opc = Mips::ADDiu;
305  emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
306  return ResultReg;
307  } else if (isUInt<16>(Imm)) {
308  emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
309  return ResultReg;
310  }
311  unsigned Lo = Imm & 0xFFFF;
312  unsigned Hi = (Imm >> 16) & 0xFFFF;
313  if (Lo) {
314  // Both Lo and Hi have nonzero bits.
315  unsigned TmpReg = createResultReg(RC);
316  emitInst(Mips::LUi, TmpReg).addImm(Hi);
317  emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
318  } else {
319  emitInst(Mips::LUi, ResultReg).addImm(Hi);
320  }
321  return ResultReg;
322 }
323 
324 unsigned MipsFastISel::materializeFP(const ConstantFP *CFP, MVT VT) {
325  if (UnsupportedFPMode)
326  return 0;
327  int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
328  if (VT == MVT::f32) {
329  const TargetRegisterClass *RC = &Mips::FGR32RegClass;
330  unsigned DestReg = createResultReg(RC);
331  unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass);
332  emitInst(Mips::MTC1, DestReg).addReg(TempReg);
333  return DestReg;
334  } else if (VT == MVT::f64) {
335  const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
336  unsigned DestReg = createResultReg(RC);
337  unsigned TempReg1 = materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
338  unsigned TempReg2 =
339  materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
340  emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
341  return DestReg;
342  }
343  return 0;
344 }
345 
346 unsigned MipsFastISel::materializeGV(const GlobalValue *GV, MVT VT) {
347  // For now 32-bit only.
348  if (VT != MVT::i32)
349  return 0;
350  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
351  unsigned DestReg = createResultReg(RC);
352  const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
353  bool IsThreadLocal = GVar && GVar->isThreadLocal();
354  // TLS not supported at this time.
355  if (IsThreadLocal)
356  return 0;
357  emitInst(Mips::LW, DestReg)
358  .addReg(MFI->getGlobalBaseReg())
359  .addGlobalAddress(GV, 0, MipsII::MO_GOT);
360  if ((GV->hasInternalLinkage() ||
361  (GV->hasLocalLinkage() && !isa<Function>(GV)))) {
362  unsigned TempReg = createResultReg(RC);
363  emitInst(Mips::ADDiu, TempReg)
364  .addReg(DestReg)
365  .addGlobalAddress(GV, 0, MipsII::MO_ABS_LO);
366  DestReg = TempReg;
367  }
368  return DestReg;
369 }
370 
371 unsigned MipsFastISel::materializeExternalCallSym(MCSymbol *Sym) {
372  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
373  unsigned DestReg = createResultReg(RC);
374  emitInst(Mips::LW, DestReg)
375  .addReg(MFI->getGlobalBaseReg())
376  .addSym(Sym, MipsII::MO_GOT);
377  return DestReg;
378 }
379 
380 // Materialize a constant into a register, and return the register
381 // number (or zero if we failed to handle it).
382 unsigned MipsFastISel::fastMaterializeConstant(const Constant *C) {
383  if (!TargetSupported)
384  return 0;
385 
386  EVT CEVT = TLI.getValueType(DL, C->getType(), true);
387 
388  // Only handle simple types.
389  if (!CEVT.isSimple())
390  return 0;
391  MVT VT = CEVT.getSimpleVT();
392 
393  if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
394  return (UnsupportedFPMode) ? 0 : materializeFP(CFP, VT);
395  else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
396  return materializeGV(GV, VT);
397  else if (isa<ConstantInt>(C))
398  return materializeInt(C, VT);
399 
400  return 0;
401 }
402 
403 bool MipsFastISel::computeAddress(const Value *Obj, Address &Addr) {
404 
405  const User *U = nullptr;
406  unsigned Opcode = Instruction::UserOp1;
407  if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
408  // Don't walk into other basic blocks unless the object is an alloca from
409  // another block, otherwise it may not have a virtual register assigned.
410  if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
411  FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
412  Opcode = I->getOpcode();
413  U = I;
414  }
415  } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
416  Opcode = C->getOpcode();
417  U = C;
418  }
419  switch (Opcode) {
420  default:
421  break;
422  case Instruction::BitCast: {
423  // Look through bitcasts.
424  return computeAddress(U->getOperand(0), Addr);
425  }
426  case Instruction::GetElementPtr: {
427  Address SavedAddr = Addr;
428  uint64_t TmpOffset = Addr.getOffset();
429  // Iterate through the GEP folding the constants into offsets where
430  // we can.
432  for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end(); i != e;
433  ++i, ++GTI) {
434  const Value *Op = *i;
435  if (StructType *STy = dyn_cast<StructType>(*GTI)) {
436  const StructLayout *SL = DL.getStructLayout(STy);
437  unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
438  TmpOffset += SL->getElementOffset(Idx);
439  } else {
440  uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
441  for (;;) {
442  if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
443  // Constant-offset addressing.
444  TmpOffset += CI->getSExtValue() * S;
445  break;
446  }
447  if (canFoldAddIntoGEP(U, Op)) {
448  // A compatible add with a constant operand. Fold the constant.
449  ConstantInt *CI =
450  cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
451  TmpOffset += CI->getSExtValue() * S;
452  // Iterate on the other operand.
453  Op = cast<AddOperator>(Op)->getOperand(0);
454  continue;
455  }
456  // Unsupported
457  goto unsupported_gep;
458  }
459  }
460  }
461  // Try to grab the base operand now.
462  Addr.setOffset(TmpOffset);
463  if (computeAddress(U->getOperand(0), Addr))
464  return true;
465  // We failed, restore everything and try the other options.
466  Addr = SavedAddr;
467  unsupported_gep:
468  break;
469  }
470  case Instruction::Alloca: {
471  const AllocaInst *AI = cast<AllocaInst>(Obj);
473  FuncInfo.StaticAllocaMap.find(AI);
474  if (SI != FuncInfo.StaticAllocaMap.end()) {
475  Addr.setKind(Address::FrameIndexBase);
476  Addr.setFI(SI->second);
477  return true;
478  }
479  break;
480  }
481  }
482  Addr.setReg(getRegForValue(Obj));
483  return Addr.getReg() != 0;
484 }
485 
486 bool MipsFastISel::computeCallAddress(const Value *V, Address &Addr) {
487  const User *U = nullptr;
488  unsigned Opcode = Instruction::UserOp1;
489 
490  if (const auto *I = dyn_cast<Instruction>(V)) {
491  // Check if the value is defined in the same basic block. This information
492  // is crucial to know whether or not folding an operand is valid.
493  if (I->getParent() == FuncInfo.MBB->getBasicBlock()) {
494  Opcode = I->getOpcode();
495  U = I;
496  }
497  } else if (const auto *C = dyn_cast<ConstantExpr>(V)) {
498  Opcode = C->getOpcode();
499  U = C;
500  }
501 
502  switch (Opcode) {
503  default:
504  break;
505  case Instruction::BitCast:
506  // Look past bitcasts if its operand is in the same BB.
507  return computeCallAddress(U->getOperand(0), Addr);
508  break;
509  case Instruction::IntToPtr:
510  // Look past no-op inttoptrs if its operand is in the same BB.
511  if (TLI.getValueType(DL, U->getOperand(0)->getType()) ==
512  TLI.getPointerTy(DL))
513  return computeCallAddress(U->getOperand(0), Addr);
514  break;
515  case Instruction::PtrToInt:
516  // Look past no-op ptrtoints if its operand is in the same BB.
517  if (TLI.getValueType(DL, U->getType()) == TLI.getPointerTy(DL))
518  return computeCallAddress(U->getOperand(0), Addr);
519  break;
520  }
521 
522  if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
523  Addr.setGlobalValue(GV);
524  return true;
525  }
526 
527  // If all else fails, try to materialize the value in a register.
528  if (!Addr.getGlobalValue()) {
529  Addr.setReg(getRegForValue(V));
530  return Addr.getReg() != 0;
531  }
532 
533  return false;
534 }
535 
536 bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) {
537  EVT evt = TLI.getValueType(DL, Ty, true);
538  // Only handle simple types.
539  if (evt == MVT::Other || !evt.isSimple())
540  return false;
541  VT = evt.getSimpleVT();
542 
543  // Handle all legal types, i.e. a register that will directly hold this
544  // value.
545  return TLI.isTypeLegal(VT);
546 }
547 
548 bool MipsFastISel::isTypeSupported(Type *Ty, MVT &VT) {
549  if (Ty->isVectorTy())
550  return false;
551 
552  if (isTypeLegal(Ty, VT))
553  return true;
554 
555  // If this is a type than can be sign or zero-extended to a basic operation
556  // go ahead and accept it now.
557  if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
558  return true;
559 
560  return false;
561 }
562 
563 bool MipsFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
564  if (isTypeLegal(Ty, VT))
565  return true;
566  // We will extend this in a later patch:
567  // If this is a type than can be sign or zero-extended to a basic operation
568  // go ahead and accept it now.
569  if (VT == MVT::i8 || VT == MVT::i16)
570  return true;
571  return false;
572 }
573 // Because of how EmitCmp is called with fast-isel, you can
574 // end up with redundant "andi" instructions after the sequences emitted below.
575 // We should try and solve this issue in the future.
576 //
577 bool MipsFastISel::emitCmp(unsigned ResultReg, const CmpInst *CI) {
578  const Value *Left = CI->getOperand(0), *Right = CI->getOperand(1);
579  bool IsUnsigned = CI->isUnsigned();
580  unsigned LeftReg = getRegEnsuringSimpleIntegerWidening(Left, IsUnsigned);
581  if (LeftReg == 0)
582  return false;
583  unsigned RightReg = getRegEnsuringSimpleIntegerWidening(Right, IsUnsigned);
584  if (RightReg == 0)
585  return false;
587 
588  switch (P) {
589  default:
590  return false;
591  case CmpInst::ICMP_EQ: {
592  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
593  emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
594  emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);
595  break;
596  }
597  case CmpInst::ICMP_NE: {
598  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
599  emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
600  emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg);
601  break;
602  }
603  case CmpInst::ICMP_UGT: {
604  emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg);
605  break;
606  }
607  case CmpInst::ICMP_ULT: {
608  emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg);
609  break;
610  }
611  case CmpInst::ICMP_UGE: {
612  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
613  emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg);
614  emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
615  break;
616  }
617  case CmpInst::ICMP_ULE: {
618  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
619  emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg);
620  emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
621  break;
622  }
623  case CmpInst::ICMP_SGT: {
624  emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg);
625  break;
626  }
627  case CmpInst::ICMP_SLT: {
628  emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg);
629  break;
630  }
631  case CmpInst::ICMP_SGE: {
632  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
633  emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg);
634  emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
635  break;
636  }
637  case CmpInst::ICMP_SLE: {
638  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
639  emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg);
640  emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
641  break;
642  }
643  case CmpInst::FCMP_OEQ:
644  case CmpInst::FCMP_UNE:
645  case CmpInst::FCMP_OLT:
646  case CmpInst::FCMP_OLE:
647  case CmpInst::FCMP_OGT:
648  case CmpInst::FCMP_OGE: {
649  if (UnsupportedFPMode)
650  return false;
651  bool IsFloat = Left->getType()->isFloatTy();
652  bool IsDouble = Left->getType()->isDoubleTy();
653  if (!IsFloat && !IsDouble)
654  return false;
655  unsigned Opc, CondMovOpc;
656  switch (P) {
657  case CmpInst::FCMP_OEQ:
658  Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
659  CondMovOpc = Mips::MOVT_I;
660  break;
661  case CmpInst::FCMP_UNE:
662  Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
663  CondMovOpc = Mips::MOVF_I;
664  break;
665  case CmpInst::FCMP_OLT:
666  Opc = IsFloat ? Mips::C_OLT_S : Mips::C_OLT_D32;
667  CondMovOpc = Mips::MOVT_I;
668  break;
669  case CmpInst::FCMP_OLE:
670  Opc = IsFloat ? Mips::C_OLE_S : Mips::C_OLE_D32;
671  CondMovOpc = Mips::MOVT_I;
672  break;
673  case CmpInst::FCMP_OGT:
674  Opc = IsFloat ? Mips::C_ULE_S : Mips::C_ULE_D32;
675  CondMovOpc = Mips::MOVF_I;
676  break;
677  case CmpInst::FCMP_OGE:
678  Opc = IsFloat ? Mips::C_ULT_S : Mips::C_ULT_D32;
679  CondMovOpc = Mips::MOVF_I;
680  break;
681  default:
682  llvm_unreachable("Only switching of a subset of CCs.");
683  }
684  unsigned RegWithZero = createResultReg(&Mips::GPR32RegClass);
685  unsigned RegWithOne = createResultReg(&Mips::GPR32RegClass);
686  emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0);
687  emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1);
688  emitInst(Opc).addReg(LeftReg).addReg(RightReg).addReg(
689  Mips::FCC0, RegState::ImplicitDefine);
690  MachineInstrBuilder MI = emitInst(CondMovOpc, ResultReg)
691  .addReg(RegWithOne)
692  .addReg(Mips::FCC0)
693  .addReg(RegWithZero, RegState::Implicit);
694  MI->tieOperands(0, 3);
695  break;
696  }
697  }
698  return true;
699 }
700 bool MipsFastISel::emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
701  unsigned Alignment) {
702  //
703  // more cases will be handled here in following patches.
704  //
705  unsigned Opc;
706  switch (VT.SimpleTy) {
707  case MVT::i32: {
708  ResultReg = createResultReg(&Mips::GPR32RegClass);
709  Opc = Mips::LW;
710  break;
711  }
712  case MVT::i16: {
713  ResultReg = createResultReg(&Mips::GPR32RegClass);
714  Opc = Mips::LHu;
715  break;
716  }
717  case MVT::i8: {
718  ResultReg = createResultReg(&Mips::GPR32RegClass);
719  Opc = Mips::LBu;
720  break;
721  }
722  case MVT::f32: {
723  if (UnsupportedFPMode)
724  return false;
725  ResultReg = createResultReg(&Mips::FGR32RegClass);
726  Opc = Mips::LWC1;
727  break;
728  }
729  case MVT::f64: {
730  if (UnsupportedFPMode)
731  return false;
732  ResultReg = createResultReg(&Mips::AFGR64RegClass);
733  Opc = Mips::LDC1;
734  break;
735  }
736  default:
737  return false;
738  }
739  if (Addr.isRegBase()) {
740  simplifyAddress(Addr);
741  emitInstLoad(Opc, ResultReg, Addr.getReg(), Addr.getOffset());
742  return true;
743  }
744  if (Addr.isFIBase()) {
745  unsigned FI = Addr.getFI();
746  unsigned Align = 4;
747  unsigned Offset = Addr.getOffset();
748  MachineFrameInfo &MFI = *MF->getFrameInfo();
749  MachineMemOperand *MMO = MF->getMachineMemOperand(
751  MFI.getObjectSize(FI), Align);
752  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
753  .addFrameIndex(FI)
754  .addImm(Offset)
755  .addMemOperand(MMO);
756  return true;
757  }
758  return false;
759 }
760 
761 bool MipsFastISel::emitStore(MVT VT, unsigned SrcReg, Address &Addr,
762  unsigned Alignment) {
763  //
764  // more cases will be handled here in following patches.
765  //
766  unsigned Opc;
767  switch (VT.SimpleTy) {
768  case MVT::i8:
769  Opc = Mips::SB;
770  break;
771  case MVT::i16:
772  Opc = Mips::SH;
773  break;
774  case MVT::i32:
775  Opc = Mips::SW;
776  break;
777  case MVT::f32:
778  if (UnsupportedFPMode)
779  return false;
780  Opc = Mips::SWC1;
781  break;
782  case MVT::f64:
783  if (UnsupportedFPMode)
784  return false;
785  Opc = Mips::SDC1;
786  break;
787  default:
788  return false;
789  }
790  if (Addr.isRegBase()) {
791  simplifyAddress(Addr);
792  emitInstStore(Opc, SrcReg, Addr.getReg(), Addr.getOffset());
793  return true;
794  }
795  if (Addr.isFIBase()) {
796  unsigned FI = Addr.getFI();
797  unsigned Align = 4;
798  unsigned Offset = Addr.getOffset();
799  MachineFrameInfo &MFI = *MF->getFrameInfo();
800  MachineMemOperand *MMO = MF->getMachineMemOperand(
802  MFI.getObjectSize(FI), Align);
803  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
804  .addReg(SrcReg)
805  .addFrameIndex(FI)
806  .addImm(Offset)
807  .addMemOperand(MMO);
808  return true;
809  }
810  return false;
811 }
812 
813 bool MipsFastISel::selectLogicalOp(const Instruction *I) {
814  MVT VT;
815  if (!isTypeSupported(I->getType(), VT))
816  return false;
817 
818  unsigned ResultReg;
819  switch (I->getOpcode()) {
820  default:
821  llvm_unreachable("Unexpected instruction.");
822  case Instruction::And:
823  ResultReg = emitLogicalOp(ISD::AND, VT, I->getOperand(0), I->getOperand(1));
824  break;
825  case Instruction::Or:
826  ResultReg = emitLogicalOp(ISD::OR, VT, I->getOperand(0), I->getOperand(1));
827  break;
828  case Instruction::Xor:
829  ResultReg = emitLogicalOp(ISD::XOR, VT, I->getOperand(0), I->getOperand(1));
830  break;
831  }
832 
833  if (!ResultReg)
834  return false;
835 
836  updateValueMap(I, ResultReg);
837  return true;
838 }
839 
840 bool MipsFastISel::selectLoad(const Instruction *I) {
841  // Atomic loads need special handling.
842  if (cast<LoadInst>(I)->isAtomic())
843  return false;
844 
845  // Verify we have a legal type before going any further.
846  MVT VT;
847  if (!isLoadTypeLegal(I->getType(), VT))
848  return false;
849 
850  // See if we can handle this address.
851  Address Addr;
852  if (!computeAddress(I->getOperand(0), Addr))
853  return false;
854 
855  unsigned ResultReg;
856  if (!emitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
857  return false;
858  updateValueMap(I, ResultReg);
859  return true;
860 }
861 
862 bool MipsFastISel::selectStore(const Instruction *I) {
863  Value *Op0 = I->getOperand(0);
864  unsigned SrcReg = 0;
865 
866  // Atomic stores need special handling.
867  if (cast<StoreInst>(I)->isAtomic())
868  return false;
869 
870  // Verify we have a legal type before going any further.
871  MVT VT;
872  if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
873  return false;
874 
875  // Get the value to be stored into a register.
876  SrcReg = getRegForValue(Op0);
877  if (SrcReg == 0)
878  return false;
879 
880  // See if we can handle this address.
881  Address Addr;
882  if (!computeAddress(I->getOperand(1), Addr))
883  return false;
884 
885  if (!emitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
886  return false;
887  return true;
888 }
889 
890 //
891 // This can cause a redundant sltiu to be generated.
892 // FIXME: try and eliminate this in a future patch.
893 //
894 bool MipsFastISel::selectBranch(const Instruction *I) {
895  const BranchInst *BI = cast<BranchInst>(I);
896  MachineBasicBlock *BrBB = FuncInfo.MBB;
897  //
898  // TBB is the basic block for the case where the comparison is true.
899  // FBB is the basic block for the case where the comparison is false.
900  // if (cond) goto TBB
901  // goto FBB
902  // TBB:
903  //
904  MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
905  MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
906  BI->getCondition();
907  // For now, just try the simplest case where it's fed by a compare.
908  if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
909  unsigned CondReg = createResultReg(&Mips::GPR32RegClass);
910  if (!emitCmp(CondReg, CI))
911  return false;
912  BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::BGTZ))
913  .addReg(CondReg)
914  .addMBB(TBB);
915  fastEmitBranch(FBB, DbgLoc);
916  FuncInfo.MBB->addSuccessor(TBB);
917  return true;
918  }
919  return false;
920 }
921 
922 bool MipsFastISel::selectCmp(const Instruction *I) {
923  const CmpInst *CI = cast<CmpInst>(I);
924  unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
925  if (!emitCmp(ResultReg, CI))
926  return false;
927  updateValueMap(I, ResultReg);
928  return true;
929 }
930 
931 // Attempt to fast-select a floating-point extend instruction.
932 bool MipsFastISel::selectFPExt(const Instruction *I) {
933  if (UnsupportedFPMode)
934  return false;
935  Value *Src = I->getOperand(0);
936  EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
937  EVT DestVT = TLI.getValueType(DL, I->getType(), true);
938 
939  if (SrcVT != MVT::f32 || DestVT != MVT::f64)
940  return false;
941 
942  unsigned SrcReg =
943  getRegForValue(Src); // his must be a 32 bit floating point register class
944  // maybe we should handle this differently
945  if (!SrcReg)
946  return false;
947 
948  unsigned DestReg = createResultReg(&Mips::AFGR64RegClass);
949  emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg);
950  updateValueMap(I, DestReg);
951  return true;
952 }
953 
954 bool MipsFastISel::selectSelect(const Instruction *I) {
955  assert(isa<SelectInst>(I) && "Expected a select instruction.");
956 
957  MVT VT;
958  if (!isTypeSupported(I->getType(), VT))
959  return false;
960 
961  unsigned CondMovOpc;
962  const TargetRegisterClass *RC;
963 
964  if (VT.isInteger() && !VT.isVector() && VT.getSizeInBits() <= 32) {
965  CondMovOpc = Mips::MOVN_I_I;
966  RC = &Mips::GPR32RegClass;
967  } else if (VT == MVT::f32) {
968  CondMovOpc = Mips::MOVN_I_S;
969  RC = &Mips::FGR32RegClass;
970  } else if (VT == MVT::f64) {
971  CondMovOpc = Mips::MOVN_I_D32;
972  RC = &Mips::AFGR64RegClass;
973  } else
974  return false;
975 
976  const SelectInst *SI = cast<SelectInst>(I);
977  const Value *Cond = SI->getCondition();
978  unsigned Src1Reg = getRegForValue(SI->getTrueValue());
979  unsigned Src2Reg = getRegForValue(SI->getFalseValue());
980  unsigned CondReg = getRegForValue(Cond);
981 
982  if (!Src1Reg || !Src2Reg || !CondReg)
983  return false;
984 
985  unsigned ZExtCondReg = createResultReg(&Mips::GPR32RegClass);
986  if (!ZExtCondReg)
987  return false;
988 
989  if (!emitIntExt(MVT::i1, CondReg, MVT::i32, ZExtCondReg, true))
990  return false;
991 
992  unsigned ResultReg = createResultReg(RC);
993  unsigned TempReg = createResultReg(RC);
994 
995  if (!ResultReg || !TempReg)
996  return false;
997 
998  emitInst(TargetOpcode::COPY, TempReg).addReg(Src2Reg);
999  emitInst(CondMovOpc, ResultReg)
1000  .addReg(Src1Reg).addReg(ZExtCondReg).addReg(TempReg);
1001  updateValueMap(I, ResultReg);
1002  return true;
1003 }
1004 
1005 // Attempt to fast-select a floating-point truncate instruction.
1006 bool MipsFastISel::selectFPTrunc(const Instruction *I) {
1007  if (UnsupportedFPMode)
1008  return false;
1009  Value *Src = I->getOperand(0);
1010  EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
1011  EVT DestVT = TLI.getValueType(DL, I->getType(), true);
1012 
1013  if (SrcVT != MVT::f64 || DestVT != MVT::f32)
1014  return false;
1015 
1016  unsigned SrcReg = getRegForValue(Src);
1017  if (!SrcReg)
1018  return false;
1019 
1020  unsigned DestReg = createResultReg(&Mips::FGR32RegClass);
1021  if (!DestReg)
1022  return false;
1023 
1024  emitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg);
1025  updateValueMap(I, DestReg);
1026  return true;
1027 }
1028 
1029 // Attempt to fast-select a floating-point-to-integer conversion.
1030 bool MipsFastISel::selectFPToInt(const Instruction *I, bool IsSigned) {
1031  if (UnsupportedFPMode)
1032  return false;
1033  MVT DstVT, SrcVT;
1034  if (!IsSigned)
1035  return false; // We don't handle this case yet. There is no native
1036  // instruction for this but it can be synthesized.
1037  Type *DstTy = I->getType();
1038  if (!isTypeLegal(DstTy, DstVT))
1039  return false;
1040 
1041  if (DstVT != MVT::i32)
1042  return false;
1043 
1044  Value *Src = I->getOperand(0);
1045  Type *SrcTy = Src->getType();
1046  if (!isTypeLegal(SrcTy, SrcVT))
1047  return false;
1048 
1049  if (SrcVT != MVT::f32 && SrcVT != MVT::f64)
1050  return false;
1051 
1052  unsigned SrcReg = getRegForValue(Src);
1053  if (SrcReg == 0)
1054  return false;
1055 
1056  // Determine the opcode for the conversion, which takes place
1057  // entirely within FPRs.
1058  unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1059  unsigned TempReg = createResultReg(&Mips::FGR32RegClass);
1060  unsigned Opc;
1061 
1062  if (SrcVT == MVT::f32)
1063  Opc = Mips::TRUNC_W_S;
1064  else
1065  Opc = Mips::TRUNC_W_D32;
1066 
1067  // Generate the convert.
1068  emitInst(Opc, TempReg).addReg(SrcReg);
1069 
1070  emitInst(Mips::MFC1, DestReg).addReg(TempReg);
1071 
1072  updateValueMap(I, DestReg);
1073  return true;
1074 }
1075 //
1076 bool MipsFastISel::processCallArgs(CallLoweringInfo &CLI,
1077  SmallVectorImpl<MVT> &OutVTs,
1078  unsigned &NumBytes) {
1079  CallingConv::ID CC = CLI.CallConv;
1081  CCState CCInfo(CC, false, *FuncInfo.MF, ArgLocs, *Context);
1082  CCInfo.AnalyzeCallOperands(OutVTs, CLI.OutFlags, CCAssignFnForCall(CC));
1083  // Get a count of how many bytes are to be pushed on the stack.
1084  NumBytes = CCInfo.getNextStackOffset();
1085  // This is the minimum argument area used for A0-A3.
1086  if (NumBytes < 16)
1087  NumBytes = 16;
1088 
1089  emitInst(Mips::ADJCALLSTACKDOWN).addImm(16);
1090  // Process the args.
1091  MVT firstMVT;
1092  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1093  CCValAssign &VA = ArgLocs[i];
1094  const Value *ArgVal = CLI.OutVals[VA.getValNo()];
1095  MVT ArgVT = OutVTs[VA.getValNo()];
1096 
1097  if (i == 0) {
1098  firstMVT = ArgVT;
1099  if (ArgVT == MVT::f32) {
1100  VA.convertToReg(Mips::F12);
1101  } else if (ArgVT == MVT::f64) {
1102  VA.convertToReg(Mips::D6);
1103  }
1104  } else if (i == 1) {
1105  if ((firstMVT == MVT::f32) || (firstMVT == MVT::f64)) {
1106  if (ArgVT == MVT::f32) {
1107  VA.convertToReg(Mips::F14);
1108  } else if (ArgVT == MVT::f64) {
1109  VA.convertToReg(Mips::D7);
1110  }
1111  }
1112  }
1113  if (((ArgVT == MVT::i32) || (ArgVT == MVT::f32) || (ArgVT == MVT::i16) ||
1114  (ArgVT == MVT::i8)) &&
1115  VA.isMemLoc()) {
1116  switch (VA.getLocMemOffset()) {
1117  case 0:
1118  VA.convertToReg(Mips::A0);
1119  break;
1120  case 4:
1121  VA.convertToReg(Mips::A1);
1122  break;
1123  case 8:
1124  VA.convertToReg(Mips::A2);
1125  break;
1126  case 12:
1127  VA.convertToReg(Mips::A3);
1128  break;
1129  default:
1130  break;
1131  }
1132  }
1133  unsigned ArgReg = getRegForValue(ArgVal);
1134  if (!ArgReg)
1135  return false;
1136 
1137  // Handle arg promotion: SExt, ZExt, AExt.
1138  switch (VA.getLocInfo()) {
1139  case CCValAssign::Full:
1140  break;
1141  case CCValAssign::AExt:
1142  case CCValAssign::SExt: {
1143  MVT DestVT = VA.getLocVT();
1144  MVT SrcVT = ArgVT;
1145  ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);
1146  if (!ArgReg)
1147  return false;
1148  break;
1149  }
1150  case CCValAssign::ZExt: {
1151  MVT DestVT = VA.getLocVT();
1152  MVT SrcVT = ArgVT;
1153  ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);
1154  if (!ArgReg)
1155  return false;
1156  break;
1157  }
1158  default:
1159  llvm_unreachable("Unknown arg promotion!");
1160  }
1161 
1162  // Now copy/store arg to correct locations.
1163  if (VA.isRegLoc() && !VA.needsCustom()) {
1164  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1165  TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);
1166  CLI.OutRegs.push_back(VA.getLocReg());
1167  } else if (VA.needsCustom()) {
1168  llvm_unreachable("Mips does not use custom args.");
1169  return false;
1170  } else {
1171  //
1172  // FIXME: This path will currently return false. It was copied
1173  // from the AArch64 port and should be essentially fine for Mips too.
1174  // The work to finish up this path will be done in a follow-on patch.
1175  //
1176  assert(VA.isMemLoc() && "Assuming store on stack.");
1177  // Don't emit stores for undef values.
1178  if (isa<UndefValue>(ArgVal))
1179  continue;
1180 
1181  // Need to store on the stack.
1182  // FIXME: This alignment is incorrect but this path is disabled
1183  // for now (will return false). We need to determine the right alignment
1184  // based on the normal alignment for the underlying machine type.
1185  //
1186  unsigned ArgSize = RoundUpToAlignment(ArgVT.getSizeInBits(), 4);
1187 
1188  unsigned BEAlign = 0;
1189  if (ArgSize < 8 && !Subtarget->isLittle())
1190  BEAlign = 8 - ArgSize;
1191 
1192  Address Addr;
1193  Addr.setKind(Address::RegBase);
1194  Addr.setReg(Mips::SP);
1195  Addr.setOffset(VA.getLocMemOffset() + BEAlign);
1196 
1197  unsigned Alignment = DL.getABITypeAlignment(ArgVal->getType());
1198  MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
1199  MachinePointerInfo::getStack(Addr.getOffset()),
1200  MachineMemOperand::MOStore, ArgVT.getStoreSize(), Alignment);
1201  (void)(MMO);
1202  // if (!emitStore(ArgVT, ArgReg, Addr, MMO))
1203  return false; // can't store on the stack yet.
1204  }
1205  }
1206 
1207  return true;
1208 }
1209 
1210 bool MipsFastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT,
1211  unsigned NumBytes) {
1212  CallingConv::ID CC = CLI.CallConv;
1213  emitInst(Mips::ADJCALLSTACKUP).addImm(16);
1214  if (RetVT != MVT::isVoid) {
1216  CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
1217  CCInfo.AnalyzeCallResult(RetVT, RetCC_Mips);
1218 
1219  // Only handle a single return value.
1220  if (RVLocs.size() != 1)
1221  return false;
1222  // Copy all of the result registers out of their specified physreg.
1223  MVT CopyVT = RVLocs[0].getValVT();
1224  // Special handling for extended integers.
1225  if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
1226  CopyVT = MVT::i32;
1227 
1228  unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
1229  if (!ResultReg)
1230  return false;
1231  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1232  TII.get(TargetOpcode::COPY),
1233  ResultReg).addReg(RVLocs[0].getLocReg());
1234  CLI.InRegs.push_back(RVLocs[0].getLocReg());
1235 
1236  CLI.ResultReg = ResultReg;
1237  CLI.NumResultRegs = 1;
1238  }
1239  return true;
1240 }
1241 
1242 bool MipsFastISel::fastLowerCall(CallLoweringInfo &CLI) {
1243  if (!TargetSupported)
1244  return false;
1245 
1246  CallingConv::ID CC = CLI.CallConv;
1247  bool IsTailCall = CLI.IsTailCall;
1248  bool IsVarArg = CLI.IsVarArg;
1249  const Value *Callee = CLI.Callee;
1250  MCSymbol *Symbol = CLI.Symbol;
1251 
1252  // Do not handle FastCC.
1253  if (CC == CallingConv::Fast)
1254  return false;
1255 
1256  // Allow SelectionDAG isel to handle tail calls.
1257  if (IsTailCall)
1258  return false;
1259 
1260  // Let SDISel handle vararg functions.
1261  if (IsVarArg)
1262  return false;
1263 
1264  // FIXME: Only handle *simple* calls for now.
1265  MVT RetVT;
1266  if (CLI.RetTy->isVoidTy())
1267  RetVT = MVT::isVoid;
1268  else if (!isTypeSupported(CLI.RetTy, RetVT))
1269  return false;
1270 
1271  for (auto Flag : CLI.OutFlags)
1272  if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal())
1273  return false;
1274 
1275  // Set up the argument vectors.
1276  SmallVector<MVT, 16> OutVTs;
1277  OutVTs.reserve(CLI.OutVals.size());
1278 
1279  for (auto *Val : CLI.OutVals) {
1280  MVT VT;
1281  if (!isTypeLegal(Val->getType(), VT) &&
1282  !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16))
1283  return false;
1284 
1285  // We don't handle vector parameters yet.
1286  if (VT.isVector() || VT.getSizeInBits() > 64)
1287  return false;
1288 
1289  OutVTs.push_back(VT);
1290  }
1291 
1292  Address Addr;
1293  if (!computeCallAddress(Callee, Addr))
1294  return false;
1295 
1296  // Handle the arguments now that we've gotten them.
1297  unsigned NumBytes;
1298  if (!processCallArgs(CLI, OutVTs, NumBytes))
1299  return false;
1300 
1301  if (!Addr.getGlobalValue())
1302  return false;
1303 
1304  // Issue the call.
1305  unsigned DestAddress;
1306  if (Symbol)
1307  DestAddress = materializeExternalCallSym(Symbol);
1308  else
1309  DestAddress = materializeGV(Addr.getGlobalValue(), MVT::i32);
1310  emitInst(TargetOpcode::COPY, Mips::T9).addReg(DestAddress);
1311  MachineInstrBuilder MIB =
1312  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::JALR),
1313  Mips::RA).addReg(Mips::T9);
1314 
1315  // Add implicit physical register uses to the call.
1316  for (auto Reg : CLI.OutRegs)
1317  MIB.addReg(Reg, RegState::Implicit);
1318 
1319  // Add a register mask with the call-preserved registers.
1320  // Proper defs for return values will be added by setPhysRegsDeadExcept().
1321  MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
1322 
1323  CLI.Call = MIB;
1324 
1325  // Finish off the call including any return values.
1326  return finishCall(CLI, RetVT, NumBytes);
1327 }
1328 
1329 bool MipsFastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
1330  if (!TargetSupported)
1331  return false;
1332 
1333  switch (II->getIntrinsicID()) {
1334  default:
1335  return false;
1336  case Intrinsic::bswap: {
1337  Type *RetTy = II->getCalledFunction()->getReturnType();
1338 
1339  MVT VT;
1340  if (!isTypeSupported(RetTy, VT))
1341  return false;
1342 
1343  unsigned SrcReg = getRegForValue(II->getOperand(0));
1344  if (SrcReg == 0)
1345  return false;
1346  unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1347  if (DestReg == 0)
1348  return false;
1349  if (VT == MVT::i16) {
1350  if (Subtarget->hasMips32r2()) {
1351  emitInst(Mips::WSBH, DestReg).addReg(SrcReg);
1352  updateValueMap(II, DestReg);
1353  return true;
1354  } else {
1355  unsigned TempReg[3];
1356  for (int i = 0; i < 3; i++) {
1357  TempReg[i] = createResultReg(&Mips::GPR32RegClass);
1358  if (TempReg[i] == 0)
1359  return false;
1360  }
1361  emitInst(Mips::SLL, TempReg[0]).addReg(SrcReg).addImm(8);
1362  emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(8);
1363  emitInst(Mips::OR, TempReg[2]).addReg(TempReg[0]).addReg(TempReg[1]);
1364  emitInst(Mips::ANDi, DestReg).addReg(TempReg[2]).addImm(0xFFFF);
1365  updateValueMap(II, DestReg);
1366  return true;
1367  }
1368  } else if (VT == MVT::i32) {
1369  if (Subtarget->hasMips32r2()) {
1370  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1371  emitInst(Mips::WSBH, TempReg).addReg(SrcReg);
1372  emitInst(Mips::ROTR, DestReg).addReg(TempReg).addImm(16);
1373  updateValueMap(II, DestReg);
1374  return true;
1375  } else {
1376  unsigned TempReg[8];
1377  for (int i = 0; i < 8; i++) {
1378  TempReg[i] = createResultReg(&Mips::GPR32RegClass);
1379  if (TempReg[i] == 0)
1380  return false;
1381  }
1382 
1383  emitInst(Mips::SRL, TempReg[0]).addReg(SrcReg).addImm(8);
1384  emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(24);
1385  emitInst(Mips::ANDi, TempReg[2]).addReg(TempReg[0]).addImm(0xFF00);
1386  emitInst(Mips::OR, TempReg[3]).addReg(TempReg[1]).addReg(TempReg[2]);
1387 
1388  emitInst(Mips::ANDi, TempReg[4]).addReg(SrcReg).addImm(0xFF00);
1389  emitInst(Mips::SLL, TempReg[5]).addReg(TempReg[4]).addImm(8);
1390 
1391  emitInst(Mips::SLL, TempReg[6]).addReg(SrcReg).addImm(24);
1392  emitInst(Mips::OR, TempReg[7]).addReg(TempReg[3]).addReg(TempReg[5]);
1393  emitInst(Mips::OR, DestReg).addReg(TempReg[6]).addReg(TempReg[7]);
1394  updateValueMap(II, DestReg);
1395  return true;
1396  }
1397  }
1398  return false;
1399  }
1400  case Intrinsic::memcpy:
1401  case Intrinsic::memmove: {
1402  const auto *MTI = cast<MemTransferInst>(II);
1403  // Don't handle volatile.
1404  if (MTI->isVolatile())
1405  return false;
1406  if (!MTI->getLength()->getType()->isIntegerTy(32))
1407  return false;
1408  const char *IntrMemName = isa<MemCpyInst>(II) ? "memcpy" : "memmove";
1409  return lowerCallTo(II, IntrMemName, II->getNumArgOperands() - 2);
1410  }
1411  case Intrinsic::memset: {
1412  const MemSetInst *MSI = cast<MemSetInst>(II);
1413  // Don't handle volatile.
1414  if (MSI->isVolatile())
1415  return false;
1416  if (!MSI->getLength()->getType()->isIntegerTy(32))
1417  return false;
1418  return lowerCallTo(II, "memset", II->getNumArgOperands() - 2);
1419  }
1420  }
1421  return false;
1422 }
1423 
1424 bool MipsFastISel::selectRet(const Instruction *I) {
1425  const Function &F = *I->getParent()->getParent();
1426  const ReturnInst *Ret = cast<ReturnInst>(I);
1427 
1428  if (!FuncInfo.CanLowerReturn)
1429  return false;
1430 
1431  // Build a list of return value registers.
1432  SmallVector<unsigned, 4> RetRegs;
1433 
1434  if (Ret->getNumOperands() > 0) {
1436 
1437  // Do not handle FastCC.
1438  if (CC == CallingConv::Fast)
1439  return false;
1440 
1442  GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI, DL);
1443 
1444  // Analyze operands of the call, assigning locations to each operand.
1446  MipsCCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs,
1447  I->getContext());
1448  CCAssignFn *RetCC = RetCC_Mips;
1449  CCInfo.AnalyzeReturn(Outs, RetCC);
1450 
1451  // Only handle a single return value for now.
1452  if (ValLocs.size() != 1)
1453  return false;
1454 
1455  CCValAssign &VA = ValLocs[0];
1456  const Value *RV = Ret->getOperand(0);
1457 
1458  // Don't bother handling odd stuff for now.
1459  if ((VA.getLocInfo() != CCValAssign::Full) &&
1460  (VA.getLocInfo() != CCValAssign::BCvt))
1461  return false;
1462 
1463  // Only handle register returns for now.
1464  if (!VA.isRegLoc())
1465  return false;
1466 
1467  unsigned Reg = getRegForValue(RV);
1468  if (Reg == 0)
1469  return false;
1470 
1471  unsigned SrcReg = Reg + VA.getValNo();
1472  unsigned DestReg = VA.getLocReg();
1473  // Avoid a cross-class copy. This is very unlikely.
1474  if (!MRI.getRegClass(SrcReg)->contains(DestReg))
1475  return false;
1476 
1477  EVT RVEVT = TLI.getValueType(DL, RV->getType());
1478  if (!RVEVT.isSimple())
1479  return false;
1480 
1481  if (RVEVT.isVector())
1482  return false;
1483 
1484  MVT RVVT = RVEVT.getSimpleVT();
1485  if (RVVT == MVT::f128)
1486  return false;
1487 
1488  MVT DestVT = VA.getValVT();
1489  // Special handling for extended integers.
1490  if (RVVT != DestVT) {
1491  if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
1492  return false;
1493 
1494  if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
1495  bool IsZExt = Outs[0].Flags.isZExt();
1496  SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt);
1497  if (SrcReg == 0)
1498  return false;
1499  }
1500  }
1501 
1502  // Make the copy.
1503  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1504  TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);
1505 
1506  // Add register to return instruction.
1507  RetRegs.push_back(VA.getLocReg());
1508  }
1509  MachineInstrBuilder MIB = emitInst(Mips::RetRA);
1510  for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
1511  MIB.addReg(RetRegs[i], RegState::Implicit);
1512  return true;
1513 }
1514 
1515 bool MipsFastISel::selectTrunc(const Instruction *I) {
1516  // The high bits for a type smaller than the register size are assumed to be
1517  // undefined.
1518  Value *Op = I->getOperand(0);
1519 
1520  EVT SrcVT, DestVT;
1521  SrcVT = TLI.getValueType(DL, Op->getType(), true);
1522  DestVT = TLI.getValueType(DL, I->getType(), true);
1523 
1524  if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1525  return false;
1526  if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1527  return false;
1528 
1529  unsigned SrcReg = getRegForValue(Op);
1530  if (!SrcReg)
1531  return false;
1532 
1533  // Because the high bits are undefined, a truncate doesn't generate
1534  // any code.
1535  updateValueMap(I, SrcReg);
1536  return true;
1537 }
1538 bool MipsFastISel::selectIntExt(const Instruction *I) {
1539  Type *DestTy = I->getType();
1540  Value *Src = I->getOperand(0);
1541  Type *SrcTy = Src->getType();
1542 
1543  bool isZExt = isa<ZExtInst>(I);
1544  unsigned SrcReg = getRegForValue(Src);
1545  if (!SrcReg)
1546  return false;
1547 
1548  EVT SrcEVT, DestEVT;
1549  SrcEVT = TLI.getValueType(DL, SrcTy, true);
1550  DestEVT = TLI.getValueType(DL, DestTy, true);
1551  if (!SrcEVT.isSimple())
1552  return false;
1553  if (!DestEVT.isSimple())
1554  return false;
1555 
1556  MVT SrcVT = SrcEVT.getSimpleVT();
1557  MVT DestVT = DestEVT.getSimpleVT();
1558  unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1559 
1560  if (!emitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt))
1561  return false;
1562  updateValueMap(I, ResultReg);
1563  return true;
1564 }
1565 bool MipsFastISel::emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1566  unsigned DestReg) {
1567  unsigned ShiftAmt;
1568  switch (SrcVT.SimpleTy) {
1569  default:
1570  return false;
1571  case MVT::i8:
1572  ShiftAmt = 24;
1573  break;
1574  case MVT::i16:
1575  ShiftAmt = 16;
1576  break;
1577  }
1578  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1579  emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);
1580  emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);
1581  return true;
1582 }
1583 
1584 bool MipsFastISel::emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1585  unsigned DestReg) {
1586  switch (SrcVT.SimpleTy) {
1587  default:
1588  return false;
1589  case MVT::i8:
1590  emitInst(Mips::SEB, DestReg).addReg(SrcReg);
1591  break;
1592  case MVT::i16:
1593  emitInst(Mips::SEH, DestReg).addReg(SrcReg);
1594  break;
1595  }
1596  return true;
1597 }
1598 
1599 bool MipsFastISel::emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1600  unsigned DestReg) {
1601  if ((DestVT != MVT::i32) && (DestVT != MVT::i16))
1602  return false;
1603  if (Subtarget->hasMips32r2())
1604  return emitIntSExt32r2(SrcVT, SrcReg, DestVT, DestReg);
1605  return emitIntSExt32r1(SrcVT, SrcReg, DestVT, DestReg);
1606 }
1607 
1608 bool MipsFastISel::emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1609  unsigned DestReg) {
1610  switch (SrcVT.SimpleTy) {
1611  default:
1612  return false;
1613  case MVT::i1:
1614  emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(1);
1615  break;
1616  case MVT::i8:
1617  emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(0xff);
1618  break;
1619  case MVT::i16:
1620  emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(0xffff);
1621  break;
1622  }
1623  return true;
1624 }
1625 
1626 bool MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1627  unsigned DestReg, bool IsZExt) {
1628  // FastISel does not have plumbing to deal with extensions where the SrcVT or
1629  // DestVT are odd things, so test to make sure that they are both types we can
1630  // handle (i1/i8/i16/i32 for SrcVT and i8/i16/i32/i64 for DestVT), otherwise
1631  // bail out to SelectionDAG.
1632  if (((DestVT != MVT::i8) && (DestVT != MVT::i16) && (DestVT != MVT::i32)) ||
1633  ((SrcVT != MVT::i1) && (SrcVT != MVT::i8) && (SrcVT != MVT::i16)))
1634  return false;
1635  if (IsZExt)
1636  return emitIntZExt(SrcVT, SrcReg, DestVT, DestReg);
1637  return emitIntSExt(SrcVT, SrcReg, DestVT, DestReg);
1638 }
1639 
1640 unsigned MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1641  bool isZExt) {
1642  unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1643  bool Success = emitIntExt(SrcVT, SrcReg, DestVT, DestReg, isZExt);
1644  return Success ? DestReg : 0;
1645 }
1646 
1647 bool MipsFastISel::selectDivRem(const Instruction *I, unsigned ISDOpcode) {
1648  EVT DestEVT = TLI.getValueType(DL, I->getType(), true);
1649  if (!DestEVT.isSimple())
1650  return false;
1651 
1652  MVT DestVT = DestEVT.getSimpleVT();
1653  if (DestVT != MVT::i32)
1654  return false;
1655 
1656  unsigned DivOpc;
1657  switch (ISDOpcode) {
1658  default:
1659  return false;
1660  case ISD::SDIV:
1661  case ISD::SREM:
1662  DivOpc = Mips::SDIV;
1663  break;
1664  case ISD::UDIV:
1665  case ISD::UREM:
1666  DivOpc = Mips::UDIV;
1667  break;
1668  }
1669 
1670  unsigned Src0Reg = getRegForValue(I->getOperand(0));
1671  unsigned Src1Reg = getRegForValue(I->getOperand(1));
1672  if (!Src0Reg || !Src1Reg)
1673  return false;
1674 
1675  emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg);
1676  emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7);
1677 
1678  unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1679  if (!ResultReg)
1680  return false;
1681 
1682  unsigned MFOpc = (ISDOpcode == ISD::SREM || ISDOpcode == ISD::UREM)
1683  ? Mips::MFHI
1684  : Mips::MFLO;
1685  emitInst(MFOpc, ResultReg);
1686 
1687  updateValueMap(I, ResultReg);
1688  return true;
1689 }
1690 
1691 bool MipsFastISel::selectShift(const Instruction *I) {
1692  MVT RetVT;
1693 
1694  if (!isTypeSupported(I->getType(), RetVT))
1695  return false;
1696 
1697  unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1698  if (!ResultReg)
1699  return false;
1700 
1701  unsigned Opcode = I->getOpcode();
1702  const Value *Op0 = I->getOperand(0);
1703  unsigned Op0Reg = getRegForValue(Op0);
1704  if (!Op0Reg)
1705  return false;
1706 
1707  // If AShr or LShr, then we need to make sure the operand0 is sign extended.
1708  if (Opcode == Instruction::AShr || Opcode == Instruction::LShr) {
1709  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1710  if (!TempReg)
1711  return false;
1712 
1713  MVT Op0MVT = TLI.getValueType(DL, Op0->getType(), true).getSimpleVT();
1714  bool IsZExt = Opcode == Instruction::LShr;
1715  if (!emitIntExt(Op0MVT, Op0Reg, MVT::i32, TempReg, IsZExt))
1716  return false;
1717 
1718  Op0Reg = TempReg;
1719  }
1720 
1721  if (const auto *C = dyn_cast<ConstantInt>(I->getOperand(1))) {
1722  uint64_t ShiftVal = C->getZExtValue();
1723 
1724  switch (Opcode) {
1725  default:
1726  llvm_unreachable("Unexpected instruction.");
1727  case Instruction::Shl:
1728  Opcode = Mips::SLL;
1729  break;
1730  case Instruction::AShr:
1731  Opcode = Mips::SRA;
1732  break;
1733  case Instruction::LShr:
1734  Opcode = Mips::SRL;
1735  break;
1736  }
1737 
1738  emitInst(Opcode, ResultReg).addReg(Op0Reg).addImm(ShiftVal);
1739  updateValueMap(I, ResultReg);
1740  return true;
1741  }
1742 
1743  unsigned Op1Reg = getRegForValue(I->getOperand(1));
1744  if (!Op1Reg)
1745  return false;
1746 
1747  switch (Opcode) {
1748  default:
1749  llvm_unreachable("Unexpected instruction.");
1750  case Instruction::Shl:
1751  Opcode = Mips::SLLV;
1752  break;
1753  case Instruction::AShr:
1754  Opcode = Mips::SRAV;
1755  break;
1756  case Instruction::LShr:
1757  Opcode = Mips::SRLV;
1758  break;
1759  }
1760 
1761  emitInst(Opcode, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
1762  updateValueMap(I, ResultReg);
1763  return true;
1764 }
1765 
1766 bool MipsFastISel::fastSelectInstruction(const Instruction *I) {
1767  if (!TargetSupported)
1768  return false;
1769  switch (I->getOpcode()) {
1770  default:
1771  break;
1772  case Instruction::Load:
1773  return selectLoad(I);
1774  case Instruction::Store:
1775  return selectStore(I);
1776  case Instruction::SDiv:
1777  if (!selectBinaryOp(I, ISD::SDIV))
1778  return selectDivRem(I, ISD::SDIV);
1779  return true;
1780  case Instruction::UDiv:
1781  if (!selectBinaryOp(I, ISD::UDIV))
1782  return selectDivRem(I, ISD::UDIV);
1783  return true;
1784  case Instruction::SRem:
1785  if (!selectBinaryOp(I, ISD::SREM))
1786  return selectDivRem(I, ISD::SREM);
1787  return true;
1788  case Instruction::URem:
1789  if (!selectBinaryOp(I, ISD::UREM))
1790  return selectDivRem(I, ISD::UREM);
1791  return true;
1792  case Instruction::Shl:
1793  case Instruction::LShr:
1794  case Instruction::AShr:
1795  return selectShift(I);
1796  case Instruction::And:
1797  case Instruction::Or:
1798  case Instruction::Xor:
1799  return selectLogicalOp(I);
1800  case Instruction::Br:
1801  return selectBranch(I);
1802  case Instruction::Ret:
1803  return selectRet(I);
1804  case Instruction::Trunc:
1805  return selectTrunc(I);
1806  case Instruction::ZExt:
1807  case Instruction::SExt:
1808  return selectIntExt(I);
1809  case Instruction::FPTrunc:
1810  return selectFPTrunc(I);
1811  case Instruction::FPExt:
1812  return selectFPExt(I);
1813  case Instruction::FPToSI:
1814  return selectFPToInt(I, /*isSigned*/ true);
1815  case Instruction::FPToUI:
1816  return selectFPToInt(I, /*isSigned*/ false);
1817  case Instruction::ICmp:
1818  case Instruction::FCmp:
1819  return selectCmp(I);
1820  case Instruction::Select:
1821  return selectSelect(I);
1822  }
1823  return false;
1824 }
1825 
1826 unsigned MipsFastISel::getRegEnsuringSimpleIntegerWidening(const Value *V,
1827  bool IsUnsigned) {
1828  unsigned VReg = getRegForValue(V);
1829  if (VReg == 0)
1830  return 0;
1831  MVT VMVT = TLI.getValueType(DL, V->getType(), true).getSimpleVT();
1832  if ((VMVT == MVT::i8) || (VMVT == MVT::i16)) {
1833  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1834  if (!emitIntExt(VMVT, VReg, MVT::i32, TempReg, IsUnsigned))
1835  return 0;
1836  VReg = TempReg;
1837  }
1838  return VReg;
1839 }
1840 
1841 void MipsFastISel::simplifyAddress(Address &Addr) {
1842  if (!isInt<16>(Addr.getOffset())) {
1843  unsigned TempReg =
1844  materialize32BitInt(Addr.getOffset(), &Mips::GPR32RegClass);
1845  unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1846  emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg());
1847  Addr.setReg(DestReg);
1848  Addr.setOffset(0);
1849  }
1850 }
1851 
1852 unsigned MipsFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
1853  const TargetRegisterClass *RC,
1854  unsigned Op0, bool Op0IsKill,
1855  unsigned Op1, bool Op1IsKill) {
1856  // We treat the MUL instruction in a special way because it clobbers
1857  // the HI0 & LO0 registers. The TableGen definition of this instruction can
1858  // mark these registers only as implicitly defined. As a result, the
1859  // register allocator runs out of registers when this instruction is
1860  // followed by another instruction that defines the same registers too.
1861  // We can fix this by explicitly marking those registers as dead.
1862  if (MachineInstOpcode == Mips::MUL) {
1863  unsigned ResultReg = createResultReg(RC);
1864  const MCInstrDesc &II = TII.get(MachineInstOpcode);
1865  Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1866  Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
1867  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1868  .addReg(Op0, getKillRegState(Op0IsKill))
1869  .addReg(Op1, getKillRegState(Op1IsKill))
1872  return ResultReg;
1873  }
1874 
1875  return FastISel::fastEmitInst_rr(MachineInstOpcode, RC, Op0, Op0IsKill, Op1,
1876  Op1IsKill);
1877 }
1878 
1879 namespace llvm {
1881  const TargetLibraryInfo *libInfo) {
1882  return new MipsFastISel(funcInfo, libInfo);
1883 }
1884 }
ReturnInst - Return a value (possibly void), from a function.
The memory access reads data.
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
This class is the base class for the comparison instructions.
Definition: InstrTypes.h:679
The memory access writes data.
MVT getValVT() const
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:223
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1327
LocInfo getLocInfo() const
bool isVolatile() const
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:39
Intrinsic::ID getIntrinsicID() const
getIntrinsicID - Return the intrinsic ID of this intrinsic.
Definition: IntrinsicInst.h:44
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:191
unsigned getNumOperands() const
Definition: User.h:138
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:138
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
unsigned less or equal
Definition: InstrTypes.h:723
unsigned less than
Definition: InstrTypes.h:722
0 1 0 0 True if ordered and less than
Definition: InstrTypes.h:703
unsigned getSizeInBits() const
bool isDoubleTy() const
isDoubleTy - Return true if this is 'double', a 64-bit IEEE fp type.
Definition: Type.h:146
1 1 1 0 True if unordered or not equal
Definition: InstrTypes.h:713
MemSetInst - This class wraps the llvm.memset intrinsic.
Type * getReturnType() const
Definition: Function.cpp:233
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:111
F(f)
void reserve(size_type N)
Definition: SmallVector.h:401
static std::error_code getOffset(const SymbolRef &Sym, SectionRef Sec, uint64_t &Result)
unsigned getValNo() const
op_iterator op_begin()
Definition: User.h:183
bool isRegLoc() const
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:172
static MachinePointerInfo getFixedStack(int FI, int64_t offset=0)
getFixedStack - Return a MachinePointerInfo record that refers to the the specified FrameIndex...
COPY - Target-independent register copy.
Definition: TargetOpcodes.h:86
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:115
Used to lazily calculate structure layout information for a target machine, based on the DataLayout s...
Definition: DataLayout.h:475
MachineMemOperand - A description of a memory reference used in the backend.
SelectInst - This class represents the LLVM 'select' instruction.
const HexagonInstrInfo * TII
StructType - Class to represent struct types.
Definition: DerivedTypes.h:191
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
A Use represents the edge between a Value definition and its users.
Definition: Use.h:69
bool hasInternalLinkage() const
Definition: GlobalValue.h:278
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APInt.h:33
unsigned getNumArgOperands() const
getNumArgOperands - Return the number of call arguments.
static SDValue emitCmp(SelectionDAG &DAG, SDLoc DL, Comparison &C)
Reg
All possible values of the reg field in the ModR/M byte.
0 1 0 1 True if ordered and less than or equal
Definition: InstrTypes.h:704
SimpleValueType SimpleTy
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
unsigned getStoreSize() const
getStoreSize - Return the number of bytes overwritten by a store of the specified value type...
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
#define G(x, y, z)
Definition: MD5.cpp:52
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
Definition: Constants.h:117
unsigned getLocReg() const
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:30
ConstantExpr - a constant value that is initialized with an expression using other constant values...
Definition: Constants.h:852
void GetReturnInfo(Type *ReturnType, AttributeSet attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags...
BasicBlock * getSuccessor(unsigned i) const
unsigned getKillRegState(bool B)
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:97
TargetInstrInfo - Interface to description of machine instruction set.
uint64_t getElementOffset(unsigned Idx) const
Definition: DataLayout.h:491
#define P(N)
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
MVT - Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:41
BranchInst - Conditional or Unconditional Branch instruction.
bool isVectorTy() const
isVectorTy - True if this is an instance of VectorType.
Definition: Type.h:226
MVT getLocVT() const
This is an important base class in LLVM.
Definition: Constant.h:41
PointerType * getType() const
getType - Overload to return most specific pointer type
Definition: Instructions.h:115
bool isVector() const
isVector - Return true if this is a vector value type.
const Value * getCondition() const
bool isFloatTy() const
isFloatTy - Return true if this is 'float', a 32-bit IEEE fp type.
Definition: Type.h:143
APInt Or(const APInt &LHS, const APInt &RHS)
Bitwise OR function for APInt.
Definition: APInt.h:1895
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:233
APInt Xor(const APInt &LHS, const APInt &RHS)
Bitwise XOR function for APInt.
Definition: APInt.h:1900
op_iterator op_end()
Definition: User.h:185
#define LLVM_ATTRIBUTE_UNUSED
Definition: Compiler.h:142
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:697
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Value * getOperand(unsigned i) const
Definition: User.h:118
Predicate getPredicate() const
Return the predicate for this instruction.
Definition: InstrTypes.h:760
bool isThreadLocal() const
If the value is "Thread Local", its value isn't shared by the threads.
Definition: GlobalValue.h:152
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
EVT - Extended Value Type.
Definition: ValueTypes.h:31
LLVMContext & getContext() const
All values hold a context through their type.
Definition: Value.cpp:519
static bool isAtomic(Instruction *I)
const Value * getTrueValue() const
signed greater than
Definition: InstrTypes.h:724
bool needsCustom() const
0 0 1 0 True if ordered and greater than
Definition: InstrTypes.h:701
CCState - This class holds information needed while lowering arguments and return values...
This is the shared class of boolean and integer constants.
Definition: Constants.h:47
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:861
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:222
Provides information about what library functions are available for the current target.
static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, ArrayRef< MCPhysReg > F64Regs)
CCValAssign - Represent assignment of one arg/retval to a location.
signed less than
Definition: InstrTypes.h:726
Value * getLength() const
unsigned fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill)
Emit a MachineInstr with two register operands and a result register in the given register class...
Definition: FastISel.cpp:1768
Function * getCalledFunction() const
getCalledFunction - Return the function called, or null if this is an indirect function invocation...
const MachineInstrBuilder & addFrameIndex(int Idx) const
static MachinePointerInfo getStack(int64_t Offset)
getStack - stack pointer relative access.
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
static bool CC_Mips(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State) LLVM_ATTRIBUTE_UNUSED
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:576
AttributeSet getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:181
signed less or equal
Definition: InstrTypes.h:727
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
bool isIntegerTy() const
isIntegerTy - True if this is an instance of IntegerType.
Definition: Type.h:193
This file defines the FastISel class.
bool isMemLoc() const
APInt bitcastToAPInt() const
Definition: APFloat.cpp:3084
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:285
uint64_t RoundUpToAlignment(uint64_t Value, uint64_t Align)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
Definition: MathExtras.h:609
APInt And(const APInt &LHS, const APInt &RHS)
Bitwise AND function for APInt.
Definition: APInt.h:1890
#define Success
Value * getCondition() const
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:321
unsigned greater or equal
Definition: InstrTypes.h:721
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
#define I(x, y, z)
Definition: MD5.cpp:54
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:272
bool hasLocalLinkage() const
Definition: GlobalValue.h:280
const APFloat & getValueAPF() const
Definition: Constants.h:270
bool isUnsigned() const
Determine if this instruction is using an unsigned comparison.
Definition: InstrTypes.h:832
const ARM::ArchExtKind Kind
bool isSimple() const
isSimple - Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:94
0 0 0 1 True if ordered and equal
Definition: InstrTypes.h:700
LLVM Value Representation.
Definition: Value.h:69
unsigned getOpcode() const
getOpcode() returns a member of one of the enums like Instruction::Add.
Definition: Instruction.h:112
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:298
Primary interface to the complete machine description for the target machine.
const Value * getFalseValue() const
unsigned greater than
Definition: InstrTypes.h:720
unsigned getLocMemOffset() const
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
int64_t getSExtValue() const
Return the constant as a 64-bit integer value after it has been sign extended as appropriate for the ...
Definition: Constants.h:125
0 0 1 1 True if ordered and greater than or equal
Definition: InstrTypes.h:702
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Definition: Function.cpp:229
static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
const BasicBlock * getParent() const
Definition: Instruction.h:72
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
void convertToReg(unsigned RegNo)
MVT getSimpleVT() const
getSimpleVT - Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:203
signed greater or equal
Definition: InstrTypes.h:725
IntrinsicInst - A useful wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:37
AllocaInst - an instruction to allocate memory on the stack.
Definition: Instructions.h:76
gep_type_iterator gep_type_begin(const User *GEP)
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.