LLVM  3.7.0
SystemZLongBranch.cpp
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1 //===-- SystemZLongBranch.cpp - Branch lengthening for SystemZ ------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This pass makes sure that all branches are in range. There are several ways
11 // in which this could be done. One aggressive approach is to assume that all
12 // branches are in range and successively replace those that turn out not
13 // to be in range with a longer form (branch relaxation). A simple
14 // implementation is to continually walk through the function relaxing
15 // branches until no more changes are needed and a fixed point is reached.
16 // However, in the pathological worst case, this implementation is
17 // quadratic in the number of blocks; relaxing branch N can make branch N-1
18 // go out of range, which in turn can make branch N-2 go out of range,
19 // and so on.
20 //
21 // An alternative approach is to assume that all branches must be
22 // converted to their long forms, then reinstate the short forms of
23 // branches that, even under this pessimistic assumption, turn out to be
24 // in range (branch shortening). This too can be implemented as a function
25 // walk that is repeated until a fixed point is reached. In general,
26 // the result of shortening is not as good as that of relaxation, and
27 // shortening is also quadratic in the worst case; shortening branch N
28 // can bring branch N-1 in range of the short form, which in turn can do
29 // the same for branch N-2, and so on. The main advantage of shortening
30 // is that each walk through the function produces valid code, so it is
31 // possible to stop at any point after the first walk. The quadraticness
32 // could therefore be handled with a maximum pass count, although the
33 // question then becomes: what maximum count should be used?
34 //
35 // On SystemZ, long branches are only needed for functions bigger than 64k,
36 // which are relatively rare to begin with, and the long branch sequences
37 // are actually relatively cheap. It therefore doesn't seem worth spending
38 // much compilation time on the problem. Instead, the approach we take is:
39 //
40 // (1) Work out the address that each block would have if no branches
41 // need relaxing. Exit the pass early if all branches are in range
42 // according to this assumption.
43 //
44 // (2) Work out the address that each block would have if all branches
45 // need relaxing.
46 //
47 // (3) Walk through the block calculating the final address of each instruction
48 // and relaxing those that need to be relaxed. For backward branches,
49 // this check uses the final address of the target block, as calculated
50 // earlier in the walk. For forward branches, this check uses the
51 // address of the target block that was calculated in (2). Both checks
52 // give a conservatively-correct range.
53 //
54 //===----------------------------------------------------------------------===//
55 
56 #include "SystemZTargetMachine.h"
57 #include "llvm/ADT/Statistic.h"
60 #include "llvm/IR/Function.h"
66 
67 using namespace llvm;
68 
69 #define DEBUG_TYPE "systemz-long-branch"
70 
71 STATISTIC(LongBranches, "Number of long branches.");
72 
73 namespace {
74 // Represents positional information about a basic block.
75 struct MBBInfo {
76  // The address that we currently assume the block has.
77  uint64_t Address;
78 
79  // The size of the block in bytes, excluding terminators.
80  // This value never changes.
81  uint64_t Size;
82 
83  // The minimum alignment of the block, as a log2 value.
84  // This value never changes.
85  unsigned Alignment;
86 
87  // The number of terminators in this block. This value never changes.
88  unsigned NumTerminators;
89 
90  MBBInfo()
91  : Address(0), Size(0), Alignment(0), NumTerminators(0) {}
92 };
93 
94 // Represents the state of a block terminator.
95 struct TerminatorInfo {
96  // If this terminator is a relaxable branch, this points to the branch
97  // instruction, otherwise it is null.
99 
100  // The address that we currently assume the terminator has.
101  uint64_t Address;
102 
103  // The current size of the terminator in bytes.
104  uint64_t Size;
105 
106  // If Branch is nonnull, this is the number of the target block,
107  // otherwise it is unused.
108  unsigned TargetBlock;
109 
110  // If Branch is nonnull, this is the length of the longest relaxed form,
111  // otherwise it is zero.
112  unsigned ExtraRelaxSize;
113 
114  TerminatorInfo() : Branch(nullptr), Size(0), TargetBlock(0),
115  ExtraRelaxSize(0) {}
116 };
117 
118 // Used to keep track of the current position while iterating over the blocks.
119 struct BlockPosition {
120  // The address that we assume this position has.
121  uint64_t Address;
122 
123  // The number of low bits in Address that are known to be the same
124  // as the runtime address.
125  unsigned KnownBits;
126 
127  BlockPosition(unsigned InitialAlignment)
128  : Address(0), KnownBits(InitialAlignment) {}
129 };
130 
131 class SystemZLongBranch : public MachineFunctionPass {
132 public:
133  static char ID;
134  SystemZLongBranch(const SystemZTargetMachine &tm)
135  : MachineFunctionPass(ID), TII(nullptr) {}
136 
137  const char *getPassName() const override {
138  return "SystemZ Long Branch";
139  }
140 
141  bool runOnMachineFunction(MachineFunction &F) override;
142 
143 private:
144  void skipNonTerminators(BlockPosition &Position, MBBInfo &Block);
145  void skipTerminator(BlockPosition &Position, TerminatorInfo &Terminator,
146  bool AssumeRelaxed);
147  TerminatorInfo describeTerminator(MachineInstr *MI);
148  uint64_t initMBBInfo();
149  bool mustRelaxBranch(const TerminatorInfo &Terminator, uint64_t Address);
150  bool mustRelaxABranch();
151  void setWorstCaseAddresses();
152  void splitBranchOnCount(MachineInstr *MI, unsigned AddOpcode);
153  void splitCompareBranch(MachineInstr *MI, unsigned CompareOpcode);
154  void relaxBranch(TerminatorInfo &Terminator);
155  void relaxBranches();
156 
157  const SystemZInstrInfo *TII;
158  MachineFunction *MF;
161 };
162 
163 char SystemZLongBranch::ID = 0;
164 
165 const uint64_t MaxBackwardRange = 0x10000;
166 const uint64_t MaxForwardRange = 0xfffe;
167 } // end anonymous namespace
168 
170  return new SystemZLongBranch(TM);
171 }
172 
173 // Position describes the state immediately before Block. Update Block
174 // accordingly and move Position to the end of the block's non-terminator
175 // instructions.
176 void SystemZLongBranch::skipNonTerminators(BlockPosition &Position,
177  MBBInfo &Block) {
178  if (Block.Alignment > Position.KnownBits) {
179  // When calculating the address of Block, we need to conservatively
180  // assume that Block had the worst possible misalignment.
181  Position.Address += ((uint64_t(1) << Block.Alignment) -
182  (uint64_t(1) << Position.KnownBits));
183  Position.KnownBits = Block.Alignment;
184  }
185 
186  // Align the addresses.
187  uint64_t AlignMask = (uint64_t(1) << Block.Alignment) - 1;
188  Position.Address = (Position.Address + AlignMask) & ~AlignMask;
189 
190  // Record the block's position.
191  Block.Address = Position.Address;
192 
193  // Move past the non-terminators in the block.
194  Position.Address += Block.Size;
195 }
196 
197 // Position describes the state immediately before Terminator.
198 // Update Terminator accordingly and move Position past it.
199 // Assume that Terminator will be relaxed if AssumeRelaxed.
200 void SystemZLongBranch::skipTerminator(BlockPosition &Position,
201  TerminatorInfo &Terminator,
202  bool AssumeRelaxed) {
203  Terminator.Address = Position.Address;
204  Position.Address += Terminator.Size;
205  if (AssumeRelaxed)
206  Position.Address += Terminator.ExtraRelaxSize;
207 }
208 
209 // Return a description of terminator instruction MI.
210 TerminatorInfo SystemZLongBranch::describeTerminator(MachineInstr *MI) {
211  TerminatorInfo Terminator;
212  Terminator.Size = TII->getInstSizeInBytes(MI);
213  if (MI->isConditionalBranch() || MI->isUnconditionalBranch()) {
214  switch (MI->getOpcode()) {
215  case SystemZ::J:
216  // Relaxes to JG, which is 2 bytes longer.
217  Terminator.ExtraRelaxSize = 2;
218  break;
219  case SystemZ::BRC:
220  // Relaxes to BRCL, which is 2 bytes longer.
221  Terminator.ExtraRelaxSize = 2;
222  break;
223  case SystemZ::BRCT:
224  case SystemZ::BRCTG:
225  // Relaxes to A(G)HI and BRCL, which is 6 bytes longer.
226  Terminator.ExtraRelaxSize = 6;
227  break;
228  case SystemZ::CRJ:
229  case SystemZ::CLRJ:
230  // Relaxes to a C(L)R/BRCL sequence, which is 2 bytes longer.
231  Terminator.ExtraRelaxSize = 2;
232  break;
233  case SystemZ::CGRJ:
234  case SystemZ::CLGRJ:
235  // Relaxes to a C(L)GR/BRCL sequence, which is 4 bytes longer.
236  Terminator.ExtraRelaxSize = 4;
237  break;
238  case SystemZ::CIJ:
239  case SystemZ::CGIJ:
240  // Relaxes to a C(G)HI/BRCL sequence, which is 4 bytes longer.
241  Terminator.ExtraRelaxSize = 4;
242  break;
243  case SystemZ::CLIJ:
244  case SystemZ::CLGIJ:
245  // Relaxes to a CL(G)FI/BRCL sequence, which is 6 bytes longer.
246  Terminator.ExtraRelaxSize = 6;
247  break;
248  default:
249  llvm_unreachable("Unrecognized branch instruction");
250  }
251  Terminator.Branch = MI;
252  Terminator.TargetBlock =
253  TII->getBranchInfo(MI).Target->getMBB()->getNumber();
254  }
255  return Terminator;
256 }
257 
258 // Fill MBBs and Terminators, setting the addresses on the assumption
259 // that no branches need relaxation. Return the size of the function under
260 // this assumption.
261 uint64_t SystemZLongBranch::initMBBInfo() {
262  MF->RenumberBlocks();
263  unsigned NumBlocks = MF->size();
264 
265  MBBs.clear();
266  MBBs.resize(NumBlocks);
267 
268  Terminators.clear();
269  Terminators.reserve(NumBlocks);
270 
271  BlockPosition Position(MF->getAlignment());
272  for (unsigned I = 0; I < NumBlocks; ++I) {
273  MachineBasicBlock *MBB = MF->getBlockNumbered(I);
274  MBBInfo &Block = MBBs[I];
275 
276  // Record the alignment, for quick access.
277  Block.Alignment = MBB->getAlignment();
278 
279  // Calculate the size of the fixed part of the block.
281  MachineBasicBlock::iterator End = MBB->end();
282  while (MI != End && !MI->isTerminator()) {
283  Block.Size += TII->getInstSizeInBytes(MI);
284  ++MI;
285  }
286  skipNonTerminators(Position, Block);
287 
288  // Add the terminators.
289  while (MI != End) {
290  if (!MI->isDebugValue()) {
291  assert(MI->isTerminator() && "Terminator followed by non-terminator");
292  Terminators.push_back(describeTerminator(MI));
293  skipTerminator(Position, Terminators.back(), false);
294  ++Block.NumTerminators;
295  }
296  ++MI;
297  }
298  }
299 
300  return Position.Address;
301 }
302 
303 // Return true if, under current assumptions, Terminator would need to be
304 // relaxed if it were placed at address Address.
305 bool SystemZLongBranch::mustRelaxBranch(const TerminatorInfo &Terminator,
306  uint64_t Address) {
307  if (!Terminator.Branch)
308  return false;
309 
310  const MBBInfo &Target = MBBs[Terminator.TargetBlock];
311  if (Address >= Target.Address) {
312  if (Address - Target.Address <= MaxBackwardRange)
313  return false;
314  } else {
315  if (Target.Address - Address <= MaxForwardRange)
316  return false;
317  }
318 
319  return true;
320 }
321 
322 // Return true if, under current assumptions, any terminator needs
323 // to be relaxed.
324 bool SystemZLongBranch::mustRelaxABranch() {
325  for (auto &Terminator : Terminators)
326  if (mustRelaxBranch(Terminator, Terminator.Address))
327  return true;
328  return false;
329 }
330 
331 // Set the address of each block on the assumption that all branches
332 // must be long.
333 void SystemZLongBranch::setWorstCaseAddresses() {
335  BlockPosition Position(MF->getAlignment());
336  for (auto &Block : MBBs) {
337  skipNonTerminators(Position, Block);
338  for (unsigned BTI = 0, BTE = Block.NumTerminators; BTI != BTE; ++BTI) {
339  skipTerminator(Position, *TI, true);
340  ++TI;
341  }
342  }
343 }
344 
345 // Split BRANCH ON COUNT MI into the addition given by AddOpcode followed
346 // by a BRCL on the result.
347 void SystemZLongBranch::splitBranchOnCount(MachineInstr *MI,
348  unsigned AddOpcode) {
349  MachineBasicBlock *MBB = MI->getParent();
350  DebugLoc DL = MI->getDebugLoc();
351  BuildMI(*MBB, MI, DL, TII->get(AddOpcode))
352  .addOperand(MI->getOperand(0))
353  .addOperand(MI->getOperand(1))
354  .addImm(-1);
355  MachineInstr *BRCL = BuildMI(*MBB, MI, DL, TII->get(SystemZ::BRCL))
356  .addImm(SystemZ::CCMASK_ICMP)
358  .addOperand(MI->getOperand(2));
359  // The implicit use of CC is a killing use.
360  BRCL->addRegisterKilled(SystemZ::CC, &TII->getRegisterInfo());
361  MI->eraseFromParent();
362 }
363 
364 // Split MI into the comparison given by CompareOpcode followed
365 // a BRCL on the result.
366 void SystemZLongBranch::splitCompareBranch(MachineInstr *MI,
367  unsigned CompareOpcode) {
368  MachineBasicBlock *MBB = MI->getParent();
369  DebugLoc DL = MI->getDebugLoc();
370  BuildMI(*MBB, MI, DL, TII->get(CompareOpcode))
371  .addOperand(MI->getOperand(0))
372  .addOperand(MI->getOperand(1));
373  MachineInstr *BRCL = BuildMI(*MBB, MI, DL, TII->get(SystemZ::BRCL))
374  .addImm(SystemZ::CCMASK_ICMP)
375  .addOperand(MI->getOperand(2))
376  .addOperand(MI->getOperand(3));
377  // The implicit use of CC is a killing use.
378  BRCL->addRegisterKilled(SystemZ::CC, &TII->getRegisterInfo());
379  MI->eraseFromParent();
380 }
381 
382 // Relax the branch described by Terminator.
383 void SystemZLongBranch::relaxBranch(TerminatorInfo &Terminator) {
384  MachineInstr *Branch = Terminator.Branch;
385  switch (Branch->getOpcode()) {
386  case SystemZ::J:
387  Branch->setDesc(TII->get(SystemZ::JG));
388  break;
389  case SystemZ::BRC:
390  Branch->setDesc(TII->get(SystemZ::BRCL));
391  break;
392  case SystemZ::BRCT:
393  splitBranchOnCount(Branch, SystemZ::AHI);
394  break;
395  case SystemZ::BRCTG:
396  splitBranchOnCount(Branch, SystemZ::AGHI);
397  break;
398  case SystemZ::CRJ:
399  splitCompareBranch(Branch, SystemZ::CR);
400  break;
401  case SystemZ::CGRJ:
402  splitCompareBranch(Branch, SystemZ::CGR);
403  break;
404  case SystemZ::CIJ:
405  splitCompareBranch(Branch, SystemZ::CHI);
406  break;
407  case SystemZ::CGIJ:
408  splitCompareBranch(Branch, SystemZ::CGHI);
409  break;
410  case SystemZ::CLRJ:
411  splitCompareBranch(Branch, SystemZ::CLR);
412  break;
413  case SystemZ::CLGRJ:
414  splitCompareBranch(Branch, SystemZ::CLGR);
415  break;
416  case SystemZ::CLIJ:
417  splitCompareBranch(Branch, SystemZ::CLFI);
418  break;
419  case SystemZ::CLGIJ:
420  splitCompareBranch(Branch, SystemZ::CLGFI);
421  break;
422  default:
423  llvm_unreachable("Unrecognized branch");
424  }
425 
426  Terminator.Size += Terminator.ExtraRelaxSize;
427  Terminator.ExtraRelaxSize = 0;
428  Terminator.Branch = nullptr;
429 
430  ++LongBranches;
431 }
432 
433 // Run a shortening pass and relax any branches that need to be relaxed.
434 void SystemZLongBranch::relaxBranches() {
436  BlockPosition Position(MF->getAlignment());
437  for (auto &Block : MBBs) {
438  skipNonTerminators(Position, Block);
439  for (unsigned BTI = 0, BTE = Block.NumTerminators; BTI != BTE; ++BTI) {
440  assert(Position.Address <= TI->Address &&
441  "Addresses shouldn't go forwards");
442  if (mustRelaxBranch(*TI, Position.Address))
443  relaxBranch(*TI);
444  skipTerminator(Position, *TI, false);
445  ++TI;
446  }
447  }
448 }
449 
450 bool SystemZLongBranch::runOnMachineFunction(MachineFunction &F) {
451  TII = static_cast<const SystemZInstrInfo *>(F.getSubtarget().getInstrInfo());
452  MF = &F;
453  uint64_t Size = initMBBInfo();
454  if (Size <= MaxForwardRange || !mustRelaxABranch())
455  return false;
456 
457  setWorstCaseAddresses();
458  relaxBranches();
459  return true;
460 }
STATISTIC(NumFunctions,"Total number of functions")
A debug info location.
Definition: DebugLoc.h:34
F(f)
bool isConditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
Definition: MachineInstr.h:441
const unsigned CCMASK_ICMP
Definition: SystemZ.h:47
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
const HexagonRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:267
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:120
bundle_iterator< MachineInstr, instr_iterator > iterator
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:294
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:861
const unsigned CCMASK_CMP_NE
Definition: SystemZ.h:38
FunctionPass * createSystemZLongBranchPass(SystemZTargetMachine &TM)
Target - Wrapper for Target specific information.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:238
Representation of each machine instruction.
Definition: MachineInstr.h:51
#define I(x, y, z)
Definition: MD5.cpp:54
virtual const TargetInstrInfo * getInstrInfo() const
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
bool addRegisterKilled(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
bool isUnconditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which always transfers control flow to some other block...
Definition: MachineInstr.h:449
unsigned getAlignment() const
getAlignment - Return alignment of the basic block.