LLVM  3.7.0
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llvm::TargetLoweringBase Class Reference

This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from the rest of CodeGen. More...

#include <TargetLowering.h>

Inheritance diagram for llvm::TargetLoweringBase:
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Collaboration diagram for llvm::TargetLoweringBase:
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Classes

struct  AddrMode
 This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null, there is no BaseGV. More...
 
struct  IntrinsicInfo
 
class  ValueTypeActionImpl
 

Public Types

enum  LegalizeAction { Legal, Promote, Expand, Custom }
 This enum indicates whether operations are valid for a target, and if not, what action should be used to make them valid. More...
 
enum  LegalizeTypeAction {
  TypeLegal, TypePromoteInteger, TypeExpandInteger, TypeSoftenFloat,
  TypeExpandFloat, TypeScalarizeVector, TypeSplitVector, TypeWidenVector,
  TypePromoteFloat
}
 This enum indicates whether a types are legal for a target, and if not, what action should be used to make them valid. More...
 
enum  BooleanContent { UndefinedBooleanContent, ZeroOrOneBooleanContent, ZeroOrNegativeOneBooleanContent }
 Enum that describes how the target represents true/false values. More...
 
enum  SelectSupportKind { ScalarValSelect, ScalarCondVectorVal, VectorMaskSelect }
 Enum that describes what type of support for selects the target has. More...
 
enum  AtomicRMWExpansionKind { AtomicRMWExpansionKind::None, AtomicRMWExpansionKind::LLSC, AtomicRMWExpansionKind::CmpXChg }
 Enum that specifies what a AtomicRMWInst is expanded to, if at all. More...
 
typedef std::pair
< LegalizeTypeAction, EVT
LegalizeKind
 LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it. More...
 

Public Member Functions

 TargetLoweringBase (const TargetMachine &TM)
 NOTE: The TargetMachine owns TLOF. More...
 
virtual ~TargetLoweringBase ()
 
const TargetMachinegetTargetMachine () const
 
virtual bool useSoftFloat () const
 
MVT getPointerTy (const DataLayout &DL, uint32_t AS=0) const
 Return the pointer type for the given address space, defaults to the pointer type from the data layout. More...
 
virtual MVT getScalarShiftAmountTy (const DataLayout &, EVT) const
 EVT is not used in-tree, but is used by out-of-tree target. More...
 
EVT getShiftAmountTy (EVT LHSTy, const DataLayout &DL) const
 
virtual MVT getVectorIdxTy (const DataLayout &DL) const
 Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR. More...
 
bool isSelectExpensive () const
 Return true if the select operation is expensive for this target. More...
 
virtual bool isSelectSupported (SelectSupportKind) const
 
bool hasMultipleConditionRegisters () const
 Return true if multiple condition registers are available. More...
 
bool hasExtractBitsInsn () const
 Return true if the target has BitExtract instructions. More...
 
virtual
TargetLoweringBase::LegalizeTypeAction 
getPreferredVectorAction (EVT VT) const
 Return the preferred vector type legalization action. More...
 
virtual bool shouldExpandBuildVectorWithShuffles (EVT, unsigned DefinedValues) const
 
bool isIntDivCheap () const
 Return true if integer divide is usually cheaper than a sequence of several shifts, adds, and multiplies for this target. More...
 
bool isFsqrtCheap () const
 Return true if sqrt(x) is as cheap or cheaper than 1 / rsqrt(x) More...
 
bool isSlowDivBypassed () const
 Returns true if target has indicated at least one type should be bypassed. More...
 
const DenseMap< unsigned int,
unsigned int > & 
getBypassSlowDivWidths () const
 Returns map of slow types for division or remainder with corresponding fast types. More...
 
bool isPow2SDivCheap () const
 Return true if pow2 sdiv is cheaper than a chain of sra/srl/add/sra. More...
 
bool isJumpExpensive () const
 Return true if Flow Control is an expensive operation that should be avoided. More...
 
bool isPredictableSelectExpensive () const
 Return true if selects are only cheaper than branches if the branch is unlikely to be predicted right. More...
 
virtual bool isLoadBitCastBeneficial (EVT, EVT) const
 isLoadBitCastBeneficial() - Return true if the following transform is beneficial. More...
 
virtual bool storeOfVectorConstantIsCheap (EVT MemVT, unsigned NumElem, unsigned AddrSpace) const
 Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the given size and type for the address space than to store the individual scalar element constants. More...
 
virtual bool isCheapToSpeculateCttz () const
 Return true if it is cheap to speculate a call to intrinsic cttz. More...
 
virtual bool isCheapToSpeculateCtlz () const
 Return true if it is cheap to speculate a call to intrinsic ctlz. More...
 
bool isMaskAndBranchFoldingLegal () const
 Return if the target supports combining a chain like: More...
 
bool enableExtLdPromotion () const
 Return true if the target wants to use the optimization that turns ext(promotableInst1(...(promotableInstN(load)))) into promotedInst1(...(promotedInstN(ext(load)))). More...
 
virtual bool canCombineStoreAndExtract (Type *VectorTy, Value *Idx, unsigned &Cost) const
 Return true if the target can combine store(extractelement VectorTy, Idx). More...
 
bool hasFloatingPointExceptions () const
 Return true if target supports floating point exceptions. More...
 
virtual bool enableAggressiveFMAFusion (EVT VT) const
 Return true if target always beneficiates from combining into FMA for a given value type. More...
 
virtual EVT getSetCCResultType (const DataLayout &DL, LLVMContext &Context, EVT VT) const
 Return the ValueType of the result of SETCC operations. More...
 
virtual MVT::SimpleValueType getCmpLibcallReturnType () const
 Return the ValueType for comparison libcalls. More...
 
BooleanContent getBooleanContents (bool isVec, bool isFloat) const
 For targets without i1 registers, this gives the nature of the high-bits of boolean values held in types wider than i1. More...
 
BooleanContent getBooleanContents (EVT Type) const
 
Sched::Preference getSchedulingPreference () const
 Return target scheduling preference. More...
 
virtual Sched::Preference getSchedulingPreference (SDNode *) const
 Some scheduler, e.g. More...
 
virtual const TargetRegisterClassgetRegClassFor (MVT VT) const
 Return the register class that should be used for the specified value type. More...
 
virtual const TargetRegisterClassgetRepRegClassFor (MVT VT) const
 Return the 'representative' register class for the specified value type. More...
 
virtual uint8_t getRepRegClassCostFor (MVT VT) const
 Return the cost of the 'representative' register class for the specified value type. More...
 
bool isTypeLegal (EVT VT) const
 Return true if the target has native support for the specified value type. More...
 
const ValueTypeActionImplgetValueTypeActions () const
 
LegalizeTypeAction getTypeAction (LLVMContext &Context, EVT VT) const
 Return how we should legalize values of this type, either it is already legal (return 'Legal') or we need to promote it to a larger type (return 'Promote'), or we need to expand it into multiple registers of smaller integer type (return 'Expand'). More...
 
LegalizeTypeAction getTypeAction (MVT VT) const
 
EVT getTypeToTransformTo (LLVMContext &Context, EVT VT) const
 For types supported by the target, this is an identity function. More...
 
EVT getTypeToExpandTo (LLVMContext &Context, EVT VT) const
 For types supported by the target, this is an identity function. More...
 
unsigned getVectorTypeBreakdown (LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
 Vector types are broken down into some number of legal first class types. More...
 
virtual bool getTgtMemIntrinsic (IntrinsicInfo &, const CallInst &, unsigned) const
 Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (touches memory). More...
 
virtual bool isFPImmLegal (const APFloat &, EVT) const
 Returns true if the target can instruction select the specified FP immediate natively. More...
 
virtual bool isShuffleMaskLegal (const SmallVectorImpl< int > &, EVT) const
 Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks. More...
 
virtual bool canOpTrap (unsigned Op, EVT VT) const
 Returns true if the operation can trap for the value type. More...
 
virtual bool isVectorClearMaskLegal (const SmallVectorImpl< int > &, EVT) const
 Similar to isShuffleMaskLegal. More...
 
LegalizeAction getOperationAction (unsigned Op, EVT VT) const
 Return how this operation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More...
 
bool isOperationLegalOrCustom (unsigned Op, EVT VT) const
 Return true if the specified operation is legal on this target or can be made legal with custom lowering. More...
 
bool isOperationLegalOrPromote (unsigned Op, EVT VT) const
 Return true if the specified operation is legal on this target or can be made legal using promotion. More...
 
bool isOperationExpand (unsigned Op, EVT VT) const
 Return true if the specified operation is illegal on this target or unlikely to be made legal with custom lowering. More...
 
bool isOperationLegal (unsigned Op, EVT VT) const
 Return true if the specified operation is legal on this target. More...
 
LegalizeAction getLoadExtAction (unsigned ExtType, EVT ValVT, EVT MemVT) const
 Return how this load with extension should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More...
 
bool isLoadExtLegal (unsigned ExtType, EVT ValVT, EVT MemVT) const
 Return true if the specified load with extension is legal on this target. More...
 
bool isLoadExtLegalOrCustom (unsigned ExtType, EVT ValVT, EVT MemVT) const
 Return true if the specified load with extension is legal or custom on this target. More...
 
LegalizeAction getTruncStoreAction (EVT ValVT, EVT MemVT) const
 Return how this store with truncation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More...
 
bool isTruncStoreLegal (EVT ValVT, EVT MemVT) const
 Return true if the specified store with truncation is legal on this target. More...
 
LegalizeAction getIndexedLoadAction (unsigned IdxMode, MVT VT) const
 Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More...
 
bool isIndexedLoadLegal (unsigned IdxMode, EVT VT) const
 Return true if the specified indexed load is legal on this target. More...
 
LegalizeAction getIndexedStoreAction (unsigned IdxMode, MVT VT) const
 Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More...
 
bool isIndexedStoreLegal (unsigned IdxMode, EVT VT) const
 Return true if the specified indexed load is legal on this target. More...
 
LegalizeAction getCondCodeAction (ISD::CondCode CC, MVT VT) const
 Return how the condition code should be treated: either it is legal, needs to be expanded to some other code sequence, or the target has a custom expander for it. More...
 
bool isCondCodeLegal (ISD::CondCode CC, MVT VT) const
 Return true if the specified condition code is legal on this target. More...
 
MVT getTypeToPromoteTo (unsigned Op, MVT VT) const
 If the action for this operation is to promote, this method returns the ValueType to promote to. More...
 
EVT getValueType (const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
 Return the EVT corresponding to this LLVM type. More...
 
MVT getSimpleValueType (const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
 Return the MVT corresponding to this LLVM type. See getValueType. More...
 
virtual unsigned getByValTypeAlignment (Type *Ty, const DataLayout &DL) const
 Return the desired alignment for ByVal or InAlloca aggregate function arguments in the caller parameter area. More...
 
MVT getRegisterType (MVT VT) const
 Return the type of registers that this ValueType will eventually require. More...
 
MVT getRegisterType (LLVMContext &Context, EVT VT) const
 Return the type of registers that this ValueType will eventually require. More...
 
unsigned getNumRegisters (LLVMContext &Context, EVT VT) const
 Return the number of registers that this ValueType will eventually require. More...
 
virtual bool ShouldShrinkFPConstant (EVT) const
 If true, then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime. More...
 
virtual bool shouldReduceLoadWidth (SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const
 
bool hasBigEndianPartOrdering (EVT VT, const DataLayout &DL) const
 When splitting a value of the specified type into parts, does the Lo or Hi part come first? This usually follows the endianness, except for ppcf128, where the Hi part always comes first. More...
 
bool hasTargetDAGCombine (ISD::NodeType NT) const
 If true, the target has custom DAG combine transformations that it can perform for the specified node. More...
 
unsigned getMaxStoresPerMemset (bool OptSize) const
 Get maximum # of store operations permitted for llvm.memset. More...
 
unsigned getMaxStoresPerMemcpy (bool OptSize) const
 Get maximum # of store operations permitted for llvm.memcpy. More...
 
unsigned getMaxStoresPerMemmove (bool OptSize) const
 Get maximum # of store operations permitted for llvm.memmove. More...
 
virtual bool allowsMisalignedMemoryAccesses (EVT, unsigned AddrSpace=0, unsigned Align=1, bool *=nullptr) const
 Determine if the target supports unaligned memory accesses. More...
 
virtual EVT getOptimalMemOpType (uint64_t, unsigned, unsigned, bool, bool, bool, MachineFunction &) const
 Returns the target specific optimal type for load and store operations as a result of memset, memcpy, and memmove lowering. More...
 
virtual bool isSafeMemOpType (MVT) const
 Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline. More...
 
bool usesUnderscoreSetJmp () const
 Determine if we should use _setjmp or setjmp to implement llvm.setjmp. More...
 
bool usesUnderscoreLongJmp () const
 Determine if we should use _longjmp or longjmp to implement llvm.longjmp. More...
 
int getMinimumJumpTableEntries () const
 Return integer threshold on number of blocks to use jump tables rather than if sequence. More...
 
unsigned getStackPointerRegisterToSaveRestore () const
 If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore. More...
 
unsigned getExceptionPointerRegister () const
 If a physical register, this returns the register that receives the exception address on entry to a landing pad. More...
 
unsigned getExceptionSelectorRegister () const
 If a physical register, this returns the register that receives the exception typeid on entry to a landing pad. More...
 
unsigned getJumpBufSize () const
 Returns the target's jmp_buf size in bytes (if never set, the default is 200) More...
 
unsigned getJumpBufAlignment () const
 Returns the target's jmp_buf alignment in bytes (if never set, the default is 0) More...
 
unsigned getMinStackArgumentAlignment () const
 Return the minimum stack alignment of an argument. More...
 
unsigned getMinFunctionAlignment () const
 Return the minimum function alignment. More...
 
unsigned getPrefFunctionAlignment () const
 Return the preferred function alignment. More...
 
virtual unsigned getPrefLoopAlignment (MachineLoop *ML=nullptr) const
 Return the preferred loop alignment. More...
 
bool getInsertFencesForAtomic () const
 Return whether the DAG builder should automatically insert fences and reduce ordering for atomics. More...
 
virtual bool getStackCookieLocation (unsigned &, unsigned &) const
 Return true if the target stores stack protector cookies at a fixed offset in some non-standard address space, and populates the address space and offset as appropriate. More...
 
virtual bool isNoopAddrSpaceCast (unsigned SrcAS, unsigned DestAS) const
 Returns true if a cast between SrcAS and DestAS is a noop. More...
 
virtual bool shouldAlignPointerArgs (CallInst *, unsigned &, unsigned &) const
 Return true if the pointer arguments to CI should be aligned by aligning the object whose address is being passed. More...
 
virtual bool shouldExpandAtomicStoreInIR (StoreInst *SI) const
 Returns true if the given (atomic) store should be expanded by the IR-level AtomicExpand pass into an "atomic xchg" which ignores its input. More...
 
virtual bool shouldSignExtendTypeInLibCall (EVT Type, bool IsSigned) const
 Returns true if arguments should be sign-extended in lib calls. More...
 
virtual bool shouldExpandAtomicLoadInIR (LoadInst *LI) const
 Returns true if the given (atomic) load should be expanded by the IR-level AtomicExpand pass into a load-linked instruction (through emitLoadLinked()). More...
 
virtual AtomicRMWExpansionKind shouldExpandAtomicRMWInIR (AtomicRMWInst *) const
 Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all. More...
 
virtual LoadInstlowerIdempotentRMWIntoFencedLoad (AtomicRMWInst *RMWI) const
 On some platforms, an AtomicRMW that never actually modifies the value (such as fetch_add of 0) can be turned into a fence followed by an atomic load. More...
 
virtual bool shouldNormalizeToSelectSequence (LLVMContext &Context, EVT VT) const
 Returns true if we should normalize select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely that it saves us from materializing N0 and N1 in an integer register. More...
 
virtual bool GetAddrModeArguments (IntrinsicInst *, SmallVectorImpl< Value * > &, Type *&, unsigned AddrSpace=0) const
 CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the address. More...
 
virtual bool isLegalAddressingMode (const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AddrSpace) const
 Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type. More...
 
virtual int getScalingFactorCost (const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS=0) const
 Return the cost of the scaling factor used in the addressing mode represented by AM for this target, for a load/store of the specified type. More...
 
virtual bool isLegalICmpImmediate (int64_t) const
 Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register. More...
 
virtual bool isLegalAddImmediate (int64_t) const
 Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register with the immediate without having to materialize the immediate into a register. More...
 
virtual bool isVectorShiftByScalarCheap (Type *Ty) const
 Return true if it's significantly cheaper to shift a vector by a uniform scalar than by an amount which will vary across each lane. More...
 
virtual bool isTruncateFree (Type *, Type *) const
 Return true if it's free to truncate a value of type Ty1 to type Ty2. More...
 
virtual bool allowTruncateForTailCall (Type *, Type *) const
 Return true if a truncation from Ty1 to Ty2 is permitted when deciding whether a call is in tail position. More...
 
virtual bool isTruncateFree (EVT, EVT) const
 
virtual bool isProfitableToHoist (Instruction *I) const
 
bool isExtFree (const Instruction *I) const
 Return true if the extension represented by I is free. More...
 
virtual bool isZExtFree (Type *, Type *) const
 Return true if any actual instruction that defines a value of type Ty1 implicitly zero-extends the value to Ty2 in the result register. More...
 
virtual bool isZExtFree (EVT, EVT) const
 
virtual bool hasPairedLoad (Type *, unsigned &) const
 Return true if the target supplies and combines to a paired load two loaded values of type LoadedType next to each other in memory. More...
 
virtual bool hasPairedLoad (EVT, unsigned &) const
 
virtual unsigned getMaxSupportedInterleaveFactor () const
 Get the maximum supported factor for interleaved memory accesses. More...
 
virtual bool lowerInterleavedLoad (LoadInst *LI, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const
 Lower an interleaved load to target specific intrinsics. More...
 
virtual bool lowerInterleavedStore (StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const
 Lower an interleaved store to target specific intrinsics. More...
 
virtual bool isZExtFree (SDValue Val, EVT VT2) const
 Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicitly zero-extended such as ARM ldrb / ldrh or because it's folded such as X86 zero-extending loads). More...
 
virtual bool isFPExtFree (EVT VT) const
 Return true if an fpext operation is free (for instance, because single-precision floating-point numbers are implicitly extended to double-precision). More...
 
virtual bool isVectorLoadExtDesirable (SDValue ExtVal) const
 Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable. More...
 
virtual bool isFNegFree (EVT VT) const
 Return true if an fneg operation is free to the point where it is never worthwhile to replace it with a bitwise operation. More...
 
virtual bool isFAbsFree (EVT VT) const
 Return true if an fabs operation is free to the point where it is never worthwhile to replace it with a bitwise operation. More...
 
virtual bool isFMAFasterThanFMulAndFAdd (EVT) const
 Return true if an FMA operation is faster than a pair of fmul and fadd instructions. More...
 
virtual bool isNarrowingProfitable (EVT, EVT) const
 Return true if it's profitable to narrow operations of type VT1 to VT2. More...
 
virtual bool shouldConvertConstantLoadToIntImm (const APInt &Imm, Type *Ty) const
 Return true if it is beneficial to convert a load of a constant to just the constant itself. More...
 
virtual bool isExtractSubvectorCheap (EVT ResVT, unsigned Index) const
 Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index. More...
 
void setLibcallName (RTLIB::Libcall Call, const char *Name)
 Rename the default libcall routine name for the specified libcall. More...
 
const char * getLibcallName (RTLIB::Libcall Call) const
 Get the libcall routine name for the specified libcall. More...
 
void setCmpLibcallCC (RTLIB::Libcall Call, ISD::CondCode CC)
 Override the default CondCode to be used to test the result of the comparison libcall against zero. More...
 
ISD::CondCode getCmpLibcallCC (RTLIB::Libcall Call) const
 Get the CondCode that's to be used to test the result of the comparison libcall against zero. More...
 
void setLibcallCallingConv (RTLIB::Libcall Call, CallingConv::ID CC)
 Set the CallingConv that should be used for the specified libcall. More...
 
CallingConv::ID getLibcallCallingConv (RTLIB::Libcall Call) const
 Get the CallingConv that should be used for the specified libcall. More...
 
Helpers for TargetTransformInfo implementations
int InstructionOpcodeToISD (unsigned Opcode) const
 Get the ISD node that corresponds to the Instruction class opcode. More...
 
std::pair< unsigned, MVTgetTypeLegalizationCost (const DataLayout &DL, Type *Ty) const
 Estimate the cost of type-legalization and the legalized type. More...
 
Helpers for atomic expansion.
virtual bool hasLoadLinkedStoreConditional () const
 True if AtomicExpandPass should use emitLoadLinked/emitStoreConditional and expand AtomicCmpXchgInst. More...
 
virtual ValueemitLoadLinked (IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const
 Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type. More...
 
virtual ValueemitStoreConditional (IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const
 Perform a store-conditional operation to Addr. More...
 
virtual InstructionemitLeadingFence (IRBuilder<> &Builder, AtomicOrdering Ord, bool IsStore, bool IsLoad) const
 Inserts in the IR a target-specific intrinsic specifying a fence. More...
 
virtual InstructionemitTrailingFence (IRBuilder<> &Builder, AtomicOrdering Ord, bool IsStore, bool IsLoad) const
 

Static Public Member Functions

static ISD::NodeType getExtendForContent (BooleanContent Content)
 

Protected Member Functions

void initActions ()
 Initialize all of the actions to default values. More...
 
void setBooleanContents (BooleanContent Ty)
 Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type. More...
 
void setBooleanContents (BooleanContent IntTy, BooleanContent FloatTy)
 Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type. More...
 
void setBooleanVectorContents (BooleanContent Ty)
 Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider type. More...
 
void setSchedulingPreference (Sched::Preference Pref)
 Specify the target scheduling preference. More...
 
void setUseUnderscoreSetJmp (bool Val)
 Indicate whether this target prefers to use _setjmp to implement llvm.setjmp or the version without _. More...
 
void setUseUnderscoreLongJmp (bool Val)
 Indicate whether this target prefers to use _longjmp to implement llvm.longjmp or the version without _. More...
 
void setMinimumJumpTableEntries (int Val)
 Indicate the number of blocks to generate jump tables rather than if sequence. More...
 
void setStackPointerRegisterToSaveRestore (unsigned R)
 If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore. More...
 
void setExceptionPointerRegister (unsigned R)
 If set to a physical register, this sets the register that receives the exception address on entry to a landing pad. More...
 
void setExceptionSelectorRegister (unsigned R)
 If set to a physical register, this sets the register that receives the exception typeid on entry to a landing pad. More...
 
void setSelectIsExpensive (bool isExpensive=true)
 Tells the code generator not to expand operations into sequences that use the select operations if possible. More...
 
void setHasMultipleConditionRegisters (bool hasManyRegs=true)
 Tells the code generator that the target has multiple (allocatable) condition registers that can be used to store the results of comparisons for use by selects and conditional branches. More...
 
void setHasExtractBitsInsn (bool hasExtractInsn=true)
 Tells the code generator that the target has BitExtract instructions. More...
 
void setJumpIsExpensive (bool isExpensive=true)
 Tells the code generator not to expand logic operations on comparison predicates into separate sequences that increase the amount of flow control. More...
 
void setIntDivIsCheap (bool isCheap=true)
 Tells the code generator that integer divide is expensive, and if possible, should be replaced by an alternate sequence of instructions not containing an integer divide. More...
 
void setFsqrtIsCheap (bool isCheap=true)
 Tells the code generator that fsqrt is cheap, and should not be replaced with an alternative sequence of instructions. More...
 
void setHasFloatingPointExceptions (bool FPExceptions=true)
 Tells the code generator that this target supports floating point exceptions and cares about preserving floating point exception behavior. More...
 
void addBypassSlowDiv (unsigned int SlowBitWidth, unsigned int FastBitWidth)
 Tells the code generator which bitwidths to bypass. More...
 
void setPow2SDivIsCheap (bool isCheap=true)
 Tells the code generator that it shouldn't generate sra/srl/add/sra for a signed divide by power of two; let the target handle it. More...
 
void addRegisterClass (MVT VT, const TargetRegisterClass *RC)
 Add the specified register class as an available regclass for the specified value type. More...
 
void clearRegisterClasses ()
 Remove all register classes. More...
 
void clearOperationActions ()
 Remove all operation actions. More...
 
virtual std::pair< const
TargetRegisterClass *, uint8_t > 
findRepresentativeClass (const TargetRegisterInfo *TRI, MVT VT) const
 Return the largest legal super-reg register class of the register class for the specified type and its associated "cost". More...
 
void computeRegisterProperties (const TargetRegisterInfo *TRI)
 Once all of the register classes are added, this allows us to compute derived properties we expose. More...
 
void setOperationAction (unsigned Op, MVT VT, LegalizeAction Action)
 Indicate that the specified operation does not work with the specified type and indicate what to do about it. More...
 
void setLoadExtAction (unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
 Indicate that the specified load with extension does not work with the specified type and indicate what to do about it. More...
 
void setTruncStoreAction (MVT ValVT, MVT MemVT, LegalizeAction Action)
 Indicate that the specified truncating store does not work with the specified type and indicate what to do about it. More...
 
void setIndexedLoadAction (unsigned IdxMode, MVT VT, LegalizeAction Action)
 Indicate that the specified indexed load does or does not work with the specified type and indicate what to do abort it. More...
 
void setIndexedStoreAction (unsigned IdxMode, MVT VT, LegalizeAction Action)
 Indicate that the specified indexed store does or does not work with the specified type and indicate what to do about it. More...
 
void setCondCodeAction (ISD::CondCode CC, MVT VT, LegalizeAction Action)
 Indicate that the specified condition code is or isn't supported on the target and indicate what to do about it. More...
 
void AddPromotedToType (unsigned Opc, MVT OrigVT, MVT DestVT)
 If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/fp until it can find one that works. More...
 
void setTargetDAGCombine (ISD::NodeType NT)
 Targets should invoke this method for each target independent node that they want to provide a custom DAG combiner for by implementing the PerformDAGCombine virtual method. More...
 
void setJumpBufSize (unsigned Size)
 Set the target's required jmp_buf buffer size (in bytes); default is 200. More...
 
void setJumpBufAlignment (unsigned Align)
 Set the target's required jmp_buf buffer alignment (in bytes); default is 0. More...
 
void setMinFunctionAlignment (unsigned Align)
 Set the target's minimum function alignment (in log2(bytes)) More...
 
void setPrefFunctionAlignment (unsigned Align)
 Set the target's preferred function alignment. More...
 
void setPrefLoopAlignment (unsigned Align)
 Set the target's preferred loop alignment. More...
 
void setMinStackArgumentAlignment (unsigned Align)
 Set the minimum stack alignment of an argument (in log2(bytes)). More...
 
void setInsertFencesForAtomic (bool fence)
 Set if the DAG builder should automatically insert fences and reduce the order of atomic memory operations to Monotonic. More...
 
virtual bool isExtFreeImpl (const Instruction *I) const
 Return true if the extension represented by I is free. More...
 
bool isLegalRC (const TargetRegisterClass *RC) const
 Return true if the value types that can be represented by the specified register class are all legal. More...
 
MachineBasicBlockemitPatchPoint (MachineInstr *MI, MachineBasicBlock *MBB) const
 Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that is recognized by PrologEpilogInserter. More...
 

Protected Attributes

unsigned MaxStoresPerMemset
 Specify maximum number of store instructions per memset call. More...
 
unsigned MaxStoresPerMemsetOptSize
 Maximum number of stores operations that may be substituted for the call to memset, used for functions with OptSize attribute. More...
 
unsigned MaxStoresPerMemcpy
 Specify maximum bytes of store instructions per memcpy call. More...
 
unsigned MaxStoresPerMemcpyOptSize
 Maximum number of store operations that may be substituted for a call to memcpy, used for functions with OptSize attribute. More...
 
unsigned MaxStoresPerMemmove
 Specify maximum bytes of store instructions per memmove call. More...
 
unsigned MaxStoresPerMemmoveOptSize
 Maximum number of store instructions that may be substituted for a call to memmove, used for functions with OpSize attribute. More...
 
bool PredictableSelectIsExpensive
 Tells the code generator that select is more expensive than a branch if the branch is usually predicted right. More...
 
bool MaskAndBranchFoldingIsLegal
 MaskAndBranchFoldingIsLegal - Indicates if the target supports folding a mask of a single bit, a compare, and a branch into a single instruction. More...
 
bool EnableExtLdPromotion
 

Detailed Description

This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from the rest of CodeGen.

Definition at line 79 of file TargetLowering.h.

Member Typedef Documentation

LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it.

Definition at line 109 of file TargetLowering.h.

Member Enumeration Documentation

Enum that specifies what a AtomicRMWInst is expanded to, if at all.

Exists because different targets have different levels of support for these atomic RMW instructions, and also have different options w.r.t. what they should expand to.

Enumerator
None 
LLSC 
CmpXChg 

Definition at line 131 of file TargetLowering.h.

Enum that describes how the target represents true/false values.

Enumerator
UndefinedBooleanContent 
ZeroOrOneBooleanContent 
ZeroOrNegativeOneBooleanContent 

Definition at line 112 of file TargetLowering.h.

This enum indicates whether operations are valid for a target, and if not, what action should be used to make them valid.

Enumerator
Legal 
Promote 
Expand 
Custom 

Definition at line 86 of file TargetLowering.h.

This enum indicates whether a types are legal for a target, and if not, what action should be used to make them valid.

Enumerator
TypeLegal 
TypePromoteInteger 
TypeExpandInteger 
TypeSoftenFloat 
TypeExpandFloat 
TypeScalarizeVector 
TypeSplitVector 
TypeWidenVector 
TypePromoteFloat 

Definition at line 95 of file TargetLowering.h.

Enum that describes what type of support for selects the target has.

Enumerator
ScalarValSelect 
ScalarCondVectorVal 
VectorMaskSelect 

Definition at line 119 of file TargetLowering.h.

Constructor & Destructor Documentation

TargetLoweringBase::TargetLoweringBase ( const TargetMachine TM)
explicit
virtual llvm::TargetLoweringBase::~TargetLoweringBase ( )
inlinevirtual

Definition at line 156 of file TargetLowering.h.

Member Function Documentation

void llvm::TargetLoweringBase::addBypassSlowDiv ( unsigned int  SlowBitWidth,
unsigned int  FastBitWidth 
)
inlineprotected

Tells the code generator which bitwidths to bypass.

Definition at line 1263 of file TargetLowering.h.

Referenced by llvm::X86TargetLowering::X86TargetLowering().

void llvm::TargetLoweringBase::AddPromotedToType ( unsigned  Opc,
MVT  OrigVT,
MVT  DestVT 
)
inlineprotected

If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/fp until it can find one that works.

If that default is insufficient, this method can be used by the target to override the default.

Definition at line 1371 of file TargetLowering.h.

References llvm::MVT::SimpleTy.

Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::MipsTargetLowering::MipsTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::SITargetLowering::SITargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().

void llvm::TargetLoweringBase::addRegisterClass ( MVT  VT,
const TargetRegisterClass RC 
)
inlineprotected
virtual bool llvm::TargetLoweringBase::allowsMisalignedMemoryAccesses ( EVT  ,
unsigned  AddrSpace = 0,
unsigned  Align = 1,
bool = nullptr 
) const
inlinevirtual

Determine if the target supports unaligned memory accesses.

This function returns true if the target allows unaligned memory accesses of the specified type in the given address space. If true, it also returns whether the unaligned memory access is "fast" in the last argument by reference. This is used, for example, in situations where an array copy/move/set is converted to a sequence of store operations. Its use helps to ensure that such replacements don't generate code that causes an alignment error (trap) on the target machine.

Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::SystemZTargetLowering, llvm::ARMTargetLowering, llvm::AArch64TargetLowering, llvm::SITargetLowering, llvm::MipsSETargetLowering, and llvm::Mips16TargetLowering.

Definition at line 874 of file TargetLowering.h.

Referenced by allowableAlignment(), and FindOptimalMemOpLowering().

virtual bool llvm::TargetLoweringBase::allowTruncateForTailCall ( Type ,
Type  
) const
inlinevirtual

Return true if a truncation from Ty1 to Ty2 is permitted when deciding whether a call is in tail position.

Typically this means that both results would be assigned to the same register or stack slot, but it could mean the target performs adequate checks of its own before proceeding with the tail call.

Reimplemented in llvm::X86TargetLowering, llvm::SystemZTargetLowering, llvm::ARMTargetLowering, and llvm::HexagonTargetLowering.

Definition at line 1519 of file TargetLowering.h.

Referenced by getNoopInput().

virtual bool llvm::TargetLoweringBase::canCombineStoreAndExtract ( Type VectorTy,
Value Idx,
unsigned Cost 
) const
inlinevirtual

Return true if the target can combine store(extractelement VectorTy, Idx).

Cost[out] gives the cost of that transformation when this is true.

Reimplemented in llvm::ARMTargetLowering.

Definition at line 312 of file TargetLowering.h.

bool TargetLoweringBase::canOpTrap ( unsigned  Op,
EVT  VT 
) const
virtual

Returns true if the operation can trap for the value type.

canOpTrap - Returns true if the operation can trap for the value type.

VT must be a legal type. By default, we optimistically assume most operations don't trap except for divide and remainder.

VT must be a legal type.

Definition at line 896 of file TargetLoweringBase.cpp.

References llvm::ISD::FDIV, llvm::ISD::FREM, isTypeLegal(), llvm::ISD::SDIV, llvm::ISD::SREM, llvm::ISD::UDIV, and llvm::ISD::UREM.

void llvm::TargetLoweringBase::clearOperationActions ( )
inlineprotected

Remove all operation actions.

Definition at line 1288 of file TargetLowering.h.

void llvm::TargetLoweringBase::clearRegisterClasses ( )
inlineprotected

Remove all register classes.

Definition at line 1281 of file TargetLowering.h.

References llvm::MVT::LAST_VALUETYPE.

void TargetLoweringBase::computeRegisterProperties ( const TargetRegisterInfo TRI)
protected

Once all of the register classes are added, this allows us to compute derived properties we expose.

computeRegisterProperties - Once all of the register classes are added, this allows us to compute derived properties we expose.

Definition at line 1198 of file TargetLoweringBase.cpp.

References llvm::MVT::f128, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, findRepresentativeClass(), llvm::MVT::FIRST_VECTOR_VALUETYPE, llvm::MVT::getPow2VectorType(), getPreferredVectorAction(), llvm::MVT::getScalarType(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), getVectorTypeBreakdownMVT(), llvm::MVT::i1, llvm::MVT::i128, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::isInteger(), isTypeLegal(), llvm::MVT::isVoid, llvm::MVT::LAST_INTEGER_VALUETYPE, llvm::MVT::LAST_VALUETYPE, llvm::MVT::LAST_VECTOR_VALUETYPE, llvm_unreachable, llvm::MVT::MAX_ALLOWED_VALUETYPE, llvm::MVT::Other, llvm::MVT::ppcf128, llvm::MSP430ISD::RRC, llvm::TargetLoweringBase::ValueTypeActionImpl::setTypeAction(), TypeExpandFloat, TypeExpandInteger, TypePromoteFloat, TypePromoteInteger, TypeScalarizeVector, TypeSoftenFloat, TypeSplitVector, and TypeWidenVector.

Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::BPFTargetLowering::BPFTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::Mips16TargetLowering::Mips16TargetLowering(), llvm::MipsSETargetLowering::MipsSETargetLowering(), llvm::MSP430TargetLowering::MSP430TargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::R600TargetLowering::R600TargetLowering(), llvm::SITargetLowering::SITargetLowering(), llvm::SparcTargetLowering::SparcTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), llvm::X86TargetLowering::X86TargetLowering(), and llvm::XCoreTargetLowering::XCoreTargetLowering().

virtual Instruction* llvm::TargetLoweringBase::emitLeadingFence ( IRBuilder<> &  Builder,
AtomicOrdering  Ord,
bool  IsStore,
bool  IsLoad 
) const
inlinevirtual

Inserts in the IR a target-specific intrinsic specifying a fence.

It is called by AtomicExpandPass before expanding an AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad. RMW and CmpXchg set both IsStore and IsLoad to true. This function should either return a nullptr, or a pointer to an IR-level Instruction*. Even complex fence sequences can be represented by a single Instruction* through an intrinsic to be lowered later. Backends with !getInsertFencesForAtomic() should keep a no-op here. Backends should override this method to produce target-specific intrinsic for their fences. FIXME: Please note that the default implementation here in terms of IR-level fences exists for historical/compatibility reasons and is unsound ! Fences cannot, in general, be used to restore sequential consistency. For example, consider the following example: atomic<int> x = y = 0; int r1, r2, r3, r4; Thread 0: x.store(1); Thread 1: y.store(1); Thread 2: r1 = x.load(); r2 = y.load(); Thread 3: r3 = y.load(); r4 = x.load(); r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all seq_cst. But if they are lowered to monotonic accesses, no amount of IR-level fences can prevent it.

Reimplemented in llvm::PPCTargetLowering, and llvm::ARMTargetLowering.

Definition at line 1071 of file TargetLowering.h.

References llvm::IRBuilder< preserveNames, T, Inserter >::CreateFence(), getInsertFencesForAtomic(), and llvm::isAtLeastRelease().

virtual Value* llvm::TargetLoweringBase::emitLoadLinked ( IRBuilder<> &  Builder,
Value Addr,
AtomicOrdering  Ord 
) const
inlinevirtual

Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type.

This may entail some non-trivial operations to truncate or reconstruct types that will be illegal in the backend. See ARMISelLowering for an example implementation.

Reimplemented in llvm::ARMTargetLowering, llvm::AArch64TargetLowering, and llvm::HexagonTargetLowering.

Definition at line 1029 of file TargetLowering.h.

References llvm_unreachable.

MachineBasicBlock * TargetLoweringBase::emitPatchPoint ( MachineInstr MI,
MachineBasicBlock MBB 
) const
protected
virtual Value* llvm::TargetLoweringBase::emitStoreConditional ( IRBuilder<> &  Builder,
Value Val,
Value Addr,
AtomicOrdering  Ord 
) const
inlinevirtual

Perform a store-conditional operation to Addr.

Return the status of the store. This should be 0 if the store succeeded, non-zero otherwise.

Reimplemented in llvm::ARMTargetLowering, llvm::AArch64TargetLowering, and llvm::HexagonTargetLowering.

Definition at line 1036 of file TargetLowering.h.

References llvm_unreachable.

virtual Instruction* llvm::TargetLoweringBase::emitTrailingFence ( IRBuilder<> &  Builder,
AtomicOrdering  Ord,
bool  IsStore,
bool  IsLoad 
) const
inlinevirtual
virtual bool llvm::TargetLoweringBase::enableAggressiveFMAFusion ( EVT  VT) const
inlinevirtual

Return true if target always beneficiates from combining into FMA for a given value type.

This must typically return false on targets where FMA takes more cycles to execute than FADD.

Reimplemented in llvm::NVPTXTargetLowering, llvm::PPCTargetLowering, and llvm::SITargetLowering.

Definition at line 325 of file TargetLowering.h.

bool llvm::TargetLoweringBase::enableExtLdPromotion ( ) const
inline

Return true if the target wants to use the optimization that turns ext(promotableInst1(...(promotableInstN(load)))) into promotedInst1(...(promotedInstN(ext(load)))).

Definition at line 307 of file TargetLowering.h.

References EnableExtLdPromotion.

std::pair< const TargetRegisterClass *, uint8_t > TargetLoweringBase::findRepresentativeClass ( const TargetRegisterInfo TRI,
MVT  VT 
) const
protectedvirtual

Return the largest legal super-reg register class of the register class for the specified type and its associated "cost".

findRepresentativeClass - Return the largest legal super-reg register class of the register class for the specified type and its associated "cost".

Reimplemented in llvm::X86TargetLowering, and llvm::ARMTargetLowering.

Definition at line 1171 of file TargetLoweringBase.cpp.

References llvm::TargetRegisterInfo::getNumRegClasses(), llvm::TargetRegisterInfo::getRegClass(), llvm::TargetRegisterClass::getSize(), isLegalRC(), llvm::SuperRegClassIterator::isValid(), llvm::BitVector::setBitsInMask(), and llvm::MVT::SimpleTy.

Referenced by computeRegisterProperties(), llvm::ARMTargetLowering::findRepresentativeClass(), and llvm::X86TargetLowering::findRepresentativeClass().

virtual bool llvm::TargetLoweringBase::GetAddrModeArguments ( IntrinsicInst ,
SmallVectorImpl< Value * > &  ,
Type *&  ,
unsigned  AddrSpace = 0 
) const
inlinevirtual

CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the address.

This allows as much computation as possible to be done in the address mode for that operand. This hook lets targets also pass back when this should be done on intrinsics which load/store.

Definition at line 1435 of file TargetLowering.h.

BooleanContent llvm::TargetLoweringBase::getBooleanContents ( bool  isVec,
bool  isFloat 
) const
inline

For targets without i1 registers, this gives the nature of the high-bits of boolean values held in types wider than i1.

"Boolean values" are special true/false values produced by nodes like SETCC and consumed (as the condition) by nodes like SELECT and BRCOND. Not to be confused with general values promoted from i1. Some cpus distinguish between vectors of boolean and scalars; the isVec parameter selects between the two kinds. For example on X86 a scalar boolean should be zero extended from i1, while the elements of a vector of booleans should be sign extended from i1.

Some cpus also treat floating point types the same way as they treat vectors instead of the way they treat scalars.

Definition at line 352 of file TargetLowering.h.

Referenced by llvm::SelectionDAG::computeKnownBits(), llvm::SelectionDAG::ComputeNumSignBits(), llvm::SelectionDAG::FoldSetCC(), getBooleanContents(), llvm::SelectionDAG::getBoolExtOrTrunc(), llvm::SelectionDAG::getLogicalNOT(), llvm::TargetLowering::isConstFalseVal(), llvm::TargetLowering::isConstTrueVal(), and llvm::TargetLowering::SimplifySetCC().

BooleanContent llvm::TargetLoweringBase::getBooleanContents ( EVT  Type) const
inline
const DenseMap<unsigned int, unsigned int>& llvm::TargetLoweringBase::getBypassSlowDivWidths ( ) const
inline

Returns map of slow types for division or remainder with corresponding fast types.

Definition at line 241 of file TargetLowering.h.

unsigned TargetLoweringBase::getByValTypeAlignment ( Type Ty,
const DataLayout DL 
) const
virtual

Return the desired alignment for ByVal or InAlloca aggregate function arguments in the caller parameter area.

getByValTypeAlignment - Return the desired alignment for ByVal aggregate function arguments in the caller parameter area.

This is the actual alignment, not its logarithm.

Reimplemented in llvm::X86TargetLowering, and llvm::PPCTargetLowering.

Definition at line 1526 of file TargetLoweringBase.cpp.

References llvm::DataLayout::getABITypeAlignment().

Referenced by llvm::FastISel::lowerCallTo(), and llvm::TargetLowering::LowerCallTo().

ISD::CondCode llvm::TargetLoweringBase::getCmpLibcallCC ( RTLIB::Libcall  Call) const
inline

Get the CondCode that's to be used to test the result of the comparison libcall against zero.

Definition at line 1724 of file TargetLowering.h.

References llvm::Call.

Referenced by llvm::TargetLowering::softenSetCCOperands().

MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType ( ) const
virtual

Return the ValueType for comparison libcalls.

Comparions libcalls include floating point comparion calls, and Ordered/Unordered check calls on floating point numbers.

Definition at line 1395 of file TargetLoweringBase.cpp.

References llvm::MVT::i32.

Referenced by llvm::TargetLowering::softenSetCCOperands().

LegalizeAction llvm::TargetLoweringBase::getCondCodeAction ( ISD::CondCode  CC,
MVT  VT 
) const
inline

Return how the condition code should be treated: either it is legal, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 670 of file TargetLowering.h.

References llvm::array_lengthof(), Promote, and llvm::MVT::SimpleTy.

Referenced by isCondCodeLegal(), and llvm::TargetLowering::SimplifySetCC().

unsigned llvm::TargetLoweringBase::getExceptionPointerRegister ( ) const
inline

If a physical register, this returns the register that receives the exception address on entry to a landing pad.

Definition at line 934 of file TargetLowering.h.

Referenced by GetEHSpillList().

unsigned llvm::TargetLoweringBase::getExceptionSelectorRegister ( ) const
inline

If a physical register, this returns the register that receives the exception typeid on entry to a landing pad.

Definition at line 940 of file TargetLowering.h.

Referenced by GetEHSpillList().

static ISD::NodeType llvm::TargetLoweringBase::getExtendForContent ( BooleanContent  Content)
inlinestatic
LegalizeAction llvm::TargetLoweringBase::getIndexedLoadAction ( unsigned  IdxMode,
MVT  VT 
) const
inline

Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 634 of file TargetLowering.h.

References llvm::MVT::isValid(), llvm::ISD::LAST_INDEXED_MODE, and llvm::MVT::SimpleTy.

Referenced by isIndexedLoadLegal().

LegalizeAction llvm::TargetLoweringBase::getIndexedStoreAction ( unsigned  IdxMode,
MVT  VT 
) const
inline

Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 652 of file TargetLowering.h.

References llvm::MVT::isValid(), llvm::ISD::LAST_INDEXED_MODE, and llvm::MVT::SimpleTy.

Referenced by isIndexedStoreLegal().

bool llvm::TargetLoweringBase::getInsertFencesForAtomic ( ) const
inline

Return whether the DAG builder should automatically insert fences and reduce ordering for atomics.

Definition at line 978 of file TargetLowering.h.

Referenced by llvm::ARMTargetLowering::emitLeadingFence(), emitLeadingFence(), llvm::ARMTargetLowering::emitTrailingFence(), and emitTrailingFence().

unsigned llvm::TargetLoweringBase::getJumpBufAlignment ( ) const
inline

Returns the target's jmp_buf alignment in bytes (if never set, the default is 0)

Definition at line 952 of file TargetLowering.h.

Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getJumpBufAlignment().

unsigned llvm::TargetLoweringBase::getJumpBufSize ( ) const
inline

Returns the target's jmp_buf size in bytes (if never set, the default is 200)

Definition at line 946 of file TargetLowering.h.

Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getJumpBufSize().

CallingConv::ID llvm::TargetLoweringBase::getLibcallCallingConv ( RTLIB::Libcall  Call) const
inline
const char* llvm::TargetLoweringBase::getLibcallName ( RTLIB::Libcall  Call) const
inline
LegalizeAction llvm::TargetLoweringBase::getLoadExtAction ( unsigned  ExtType,
EVT  ValVT,
EVT  MemVT 
) const
inline

Return how this load with extension should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 587 of file TargetLowering.h.

References Expand, llvm::EVT::getSimpleVT(), llvm::EVT::isExtended(), llvm::ISD::LAST_LOADEXT_TYPE, llvm::MVT::LAST_VALUETYPE, and llvm::MVT::SimpleTy.

Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getMemoryOpCost(), isLoadExtLegal(), and isLoadExtLegalOrCustom().

unsigned llvm::TargetLoweringBase::getMaxStoresPerMemcpy ( bool  OptSize) const
inline

Get maximum # of store operations permitted for llvm.memcpy.

This function returns the maximum number of store operations permitted to replace a call to llvm.memcpy. The value is set by the target at the performance threshold for such a replacement. If OptSize is true, return the limit for functions that have OptSize attribute.

Definition at line 851 of file TargetLowering.h.

References MaxStoresPerMemcpy, and MaxStoresPerMemcpyOptSize.

Referenced by getMemcpyLoadsAndStores().

unsigned llvm::TargetLoweringBase::getMaxStoresPerMemmove ( bool  OptSize) const
inline

Get maximum # of store operations permitted for llvm.memmove.

This function returns the maximum number of store operations permitted to replace a call to llvm.memmove. The value is set by the target at the performance threshold for such a replacement. If OptSize is true, return the limit for functions that have OptSize attribute.

Definition at line 861 of file TargetLowering.h.

References MaxStoresPerMemmove, and MaxStoresPerMemmoveOptSize.

Referenced by getMemmoveLoadsAndStores().

unsigned llvm::TargetLoweringBase::getMaxStoresPerMemset ( bool  OptSize) const
inline

Get maximum # of store operations permitted for llvm.memset.

This function returns the maximum number of store operations permitted to replace a call to llvm.memset. The value is set by the target at the performance threshold for such a replacement. If OptSize is true, return the limit for functions that have OptSize attribute.

Definition at line 841 of file TargetLowering.h.

References MaxStoresPerMemset, and MaxStoresPerMemsetOptSize.

Referenced by getMemsetStores().

virtual unsigned llvm::TargetLoweringBase::getMaxSupportedInterleaveFactor ( ) const
inlinevirtual

Get the maximum supported factor for interleaved memory accesses.

Default to be the minimum interleave factor: 2.

Reimplemented in llvm::ARMTargetLowering, and llvm::AArch64TargetLowering.

Definition at line 1605 of file TargetLowering.h.

unsigned llvm::TargetLoweringBase::getMinFunctionAlignment ( ) const
inline

Return the minimum function alignment.

Definition at line 962 of file TargetLowering.h.

Referenced by llvm::MachineFunction::MachineFunction().

int llvm::TargetLoweringBase::getMinimumJumpTableEntries ( ) const
inline

Return integer threshold on number of blocks to use jump tables rather than if sequence.

Definition at line 922 of file TargetLowering.h.

unsigned llvm::TargetLoweringBase::getMinStackArgumentAlignment ( ) const
inline

Return the minimum stack alignment of an argument.

Definition at line 957 of file TargetLowering.h.

unsigned llvm::TargetLoweringBase::getNumRegisters ( LLVMContext Context,
EVT  VT 
) const
inline

Return the number of registers that this ValueType will eventually require.

This is one for any types promoted to live in larger registers, but may be more than one for types (like i64) that are split into pieces. For types like i140, which are first promoted then expanded, it is the number of registers needed to hold all the bits of the original type. For an i140 on a 32 bit machine this means 5 registers.

Definition at line 786 of file TargetLowering.h.

References llvm::array_lengthof(), getRegisterType(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), getVectorTypeBreakdown(), llvm::EVT::isInteger(), llvm::EVT::isSimple(), llvm::EVT::isVector(), llvm_unreachable, and llvm::MVT::SimpleTy.

Referenced by llvm::RegsForValue::AddInlineAsmOperands(), llvm::FunctionLoweringInfo::ComputePHILiveOutRegInfo(), llvm::FunctionLoweringInfo::CreateRegs(), llvm::RegsForValue::getCopyFromRegs(), llvm::RegsForValue::getCopyToRegs(), GetRegistersForValue(), llvm::GetReturnInfo(), llvm::NVPTXTargetLowering::LowerCall(), llvm::FastISel::lowerCallTo(), llvm::TargetLowering::LowerCallTo(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::RegsForValue::RegsForValue(), and llvm::FastISel::selectExtractValue().

LegalizeAction llvm::TargetLoweringBase::getOperationAction ( unsigned  Op,
EVT  VT 
) const
inline

Return how this operation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 544 of file TargetLowering.h.

References llvm::array_lengthof(), Custom, Expand, llvm::EVT::getSimpleVT(), I, llvm::EVT::isExtended(), and llvm::MVT::SimpleTy.

Referenced by getTypeToPromoteTo(), isOperationExpand(), isOperationLegal(), isOperationLegalOrCustom(), isOperationLegalOrPromote(), and llvm::SystemZTargetLowering::SystemZTargetLowering().

virtual EVT llvm::TargetLoweringBase::getOptimalMemOpType ( uint64_t  ,
unsigned  ,
unsigned  ,
bool  ,
bool  ,
bool  ,
MachineFunction  
) const
inlinevirtual

Returns the target specific optimal type for load and store operations as a result of memset, memcpy, and memmove lowering.

If DstAlign is zero that means it's safe to destination alignment can satisfy any constraint. Similarly if SrcAlign is zero it means there isn't a need to check it against alignment requirement, probably because the source does not need to be loaded. If 'IsMemset' is true, that means it's expanding a memset. If 'ZeroMemset' is true, that means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it does not need to be loaded. It returns EVT::Other if the type should be determined using generic target-independent logic.

Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::AArch64TargetLowering, llvm::ARMTargetLowering, and llvm::SITargetLowering.

Definition at line 892 of file TargetLowering.h.

References llvm::MVT::Other.

Referenced by FindOptimalMemOpLowering().

MVT llvm::TargetLoweringBase::getPointerTy ( const DataLayout DL,
uint32_t  AS = 0 
) const
inline

Return the pointer type for the given address space, defaults to the pointer type from the data layout.

FIXME: The default needs to be removed once all the code is updated.

Definition at line 170 of file TargetLowering.h.

References llvm::MVT::getIntegerVT(), and llvm::DataLayout::getPointerSizeInBits().

Referenced by AddCombineToVPADDL(), addStackMapLiveVars(), llvm::X86TargetLowering::BuildFILD(), CheckType(), CheckValueType(), llvm::SelectionDAG::CreateStackTemporary(), llvm::PPCTargetLowering::emitEHSjLjLongJmp(), llvm::PPCTargetLowering::emitEHSjLjSetJmp(), llvm::XCoreSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::AArch64SelectionDAGInfo::EmitTargetCodeForMemset(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(), ExpandUnalignedLoad(), ExpandUnalignedStore(), FindOptimalMemOpLowering(), getCopyFromParts(), GetExponent(), llvm::SelectionDAG::getIntPtrConstant(), getLimitedPrecisionExp2(), llvm::SelectionDAG::getMemcpy(), llvm::SelectionDAG::getMemmove(), llvm::SelectionDAG::getMemset(), llvm::X86TargetLowering::getPICJumpTableRelocBase(), llvm::TargetLowering::getPICJumpTableRelocBase(), llvm::NVPTXTargetLowering::getPrototype(), llvm::FastISel::getRegForGEPIndex(), llvm::MSP430TargetLowering::getReturnAddressFrameIndex(), llvm::X86TargetLowering::getReturnAddressFrameIndex(), llvm::ARMTargetLowering::getSetCCResultType(), getSetCCResultType(), llvm::NVPTXTargetLowering::getTgtMemIntrinsic(), llvm::SelectionDAGBuilder::getValueImpl(), getValueType(), getVectorIdxTy(), isBLACompatibleAddress(), llvm::MSP430TargetLowering::LowerBlockAddress(), llvm::HexagonTargetLowering::LowerBlockAddress(), llvm::HexagonTargetLowering::LowerBR_JT(), llvm::HexagonTargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), llvm::TargetLowering::LowerCallTo(), llvm::HexagonTargetLowering::LowerEH_RETURN(), LowerExtendedLoad(), llvm::MSP430TargetLowering::LowerExternalSymbol(), llvm::SparcTargetLowering::LowerF128_LibCallArg(), llvm::SparcTargetLowering::LowerF128Compare(), llvm::SparcTargetLowering::LowerF128Op(), LowerFABSorFNEG(), LowerFCOPYSIGN(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerFormalArguments_64(), LowerFSINCOS(), llvm::AMDGPUTargetLowering::LowerGlobalAddress(), llvm::MSP430TargetLowering::LowerGlobalAddress(), llvm::HexagonTargetLowering::LowerGLOBALADDRESS(), llvm::NVPTXTargetLowering::LowerGlobalAddress(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), LowerINTRINSIC_W_CHAIN(), llvm::MSP430TargetLowering::LowerJumpTable(), LowerMemOpCallTo(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::MSP430TargetLowering::LowerRETURNADDR(), LowerRETURNADDR(), llvm::MSP430TargetLowering::LowerVASTART(), LowerVASTART(), LowerVectorBroadcast(), llvm::SparcTargetLowering::makeAddress(), llvm::TargetLowering::makeLibCall(), llvm::PPCTargetLowering::PerformDAGCombine(), PerformEXTRACT_VECTOR_ELTCombine(), PerformLOADCombine(), PerformSTORECombine(), PrepareCall(), recoverFramePointer(), llvm::PPCTargetLowering::SelectAddressRegImm(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::FastISel::selectGetElementPtr(), llvm::TargetLowering::SimplifySetCC(), llvm::SparcTargetLowering::SparcTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), llvm::SelectionDAGBuilder::visitBitTestHeader(), llvm::SelectionDAGBuilder::visitJumpTable(), llvm::SelectionDAGBuilder::visitJumpTableHeader(), llvm::SelectionDAGBuilder::visitSPDescriptorParent(), and llvm::X86TargetLowering::X86TargetLowering().

virtual TargetLoweringBase::LegalizeTypeAction llvm::TargetLoweringBase::getPreferredVectorAction ( EVT  VT) const
inlinevirtual
unsigned llvm::TargetLoweringBase::getPrefFunctionAlignment ( ) const
inline

Return the preferred function alignment.

Definition at line 967 of file TargetLowering.h.

Referenced by llvm::MachineFunction::MachineFunction().

virtual unsigned llvm::TargetLoweringBase::getPrefLoopAlignment ( MachineLoop ML = nullptr) const
inlinevirtual

Return the preferred loop alignment.

Reimplemented in llvm::PPCTargetLowering.

Definition at line 972 of file TargetLowering.h.

Referenced by llvm::PPCTargetLowering::getPrefLoopAlignment().

virtual const TargetRegisterClass* llvm::TargetLoweringBase::getRegClassFor ( MVT  VT) const
inlinevirtual
MVT llvm::TargetLoweringBase::getRegisterType ( MVT  VT) const
inline
MVT llvm::TargetLoweringBase::getRegisterType ( LLVMContext Context,
EVT  VT 
) const
inline
virtual uint8_t llvm::TargetLoweringBase::getRepRegClassCostFor ( MVT  VT) const
inlinevirtual

Return the cost of the 'representative' register class for the specified value type.

Definition at line 396 of file TargetLowering.h.

References llvm::MVT::SimpleTy.

Referenced by GetCostForDef().

virtual const TargetRegisterClass* llvm::TargetLoweringBase::getRepRegClassFor ( MVT  VT) const
inlinevirtual

Return the 'representative' register class for the specified value type.

The 'representative' register class is the largest legal super-reg register class for the register class of the value type. For example, on i386 the rep register class for i8, i16, and i32 are GR32; while the rep register class is GR64 on x86_64.

Reimplemented in llvm::MipsSETargetLowering.

Definition at line 389 of file TargetLowering.h.

References llvm::MVT::SimpleTy.

Referenced by GetCostForDef(), and llvm::MipsSETargetLowering::getRepRegClassFor().

MVT TargetLoweringBase::getScalarShiftAmountTy ( const DataLayout DL,
EVT   
) const
virtual
virtual int llvm::TargetLoweringBase::getScalingFactorCost ( const DataLayout DL,
const AddrMode AM,
Type Ty,
unsigned  AS = 0 
) const
inlinevirtual

Return the cost of the scaling factor used in the addressing mode represented by AM for this target, for a load/store of the specified type.

If the AM is supported, the return value must be >= 0. If the AM is not supported, it returns a negative value. TODO: Handle pre/postinc as well. TODO: Remove default argument

Reimplemented in llvm::X86TargetLowering, and llvm::AArch64TargetLowering.

Definition at line 1477 of file TargetLowering.h.

References isLegalAddressingMode().

Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getScalingFactorCost().

Sched::Preference llvm::TargetLoweringBase::getSchedulingPreference ( ) const
inline

Return target scheduling preference.

Definition at line 363 of file TargetLowering.h.

Referenced by llvm::createDefaultScheduler(), llvm::PPCTargetLowering::getSchedulingPreference(), and llvm::ScheduleDAGSDNodes::newSUnit().

virtual Sched::Preference llvm::TargetLoweringBase::getSchedulingPreference ( SDNode ) const
inlinevirtual

Some scheduler, e.g.

hybrid, can switch to different scheduling heuristics for different nodes. This function returns the preference (or none) for the given node.

Reimplemented in llvm::PPCTargetLowering, and llvm::ARMTargetLowering.

Definition at line 370 of file TargetLowering.h.

References llvm::Sched::None.

EVT TargetLoweringBase::getSetCCResultType ( const DataLayout DL,
LLVMContext Context,
EVT  VT 
) const
virtual
EVT TargetLoweringBase::getShiftAmountTy ( EVT  LHSTy,
const DataLayout DL 
) const
MVT llvm::TargetLoweringBase::getSimpleValueType ( const DataLayout DL,
Type Ty,
bool  AllowUnknown = false 
) const
inline

Return the MVT corresponding to this LLVM type. See getValueType.

Definition at line 741 of file TargetLowering.h.

References llvm::EVT::getSimpleVT(), and getValueType().

Referenced by llvm::TargetLowering::ParseConstraints().

virtual bool llvm::TargetLoweringBase::getStackCookieLocation ( unsigned ,
unsigned  
) const
inlinevirtual

Return true if the target stores stack protector cookies at a fixed offset in some non-standard address space, and populates the address space and offset as appropriate.

Reimplemented in llvm::X86TargetLowering.

Definition at line 985 of file TargetLowering.h.

Referenced by CreatePrologue().

unsigned llvm::TargetLoweringBase::getStackPointerRegisterToSaveRestore ( ) const
inline

If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.

Definition at line 928 of file TargetLowering.h.

Referenced by llvm::RegsForValue::AddInlineAsmOperands(), and llvm::TargetInstrInfo::isSchedulingBoundary().

const TargetMachine& llvm::TargetLoweringBase::getTargetMachine ( ) const
inline
virtual bool llvm::TargetLoweringBase::getTgtMemIntrinsic ( IntrinsicInfo ,
const CallInst ,
unsigned   
) const
inlinevirtual

Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (touches memory).

If this is the case, it returns true and store the intrinsic information into the IntrinsicInfo that was passed to the function.

Reimplemented in llvm::PPCTargetLowering, llvm::NVPTXTargetLowering, llvm::ARMTargetLowering, and llvm::AArch64TargetLowering.

Definition at line 506 of file TargetLowering.h.

LegalizeAction llvm::TargetLoweringBase::getTruncStoreAction ( EVT  ValVT,
EVT  MemVT 
) const
inline

Return how this store with truncation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 614 of file TargetLowering.h.

References Expand, llvm::EVT::getSimpleVT(), llvm::EVT::isExtended(), llvm::MVT::LAST_VALUETYPE, and llvm::MVT::SimpleTy.

Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getMemoryOpCost(), and isTruncStoreLegal().

LegalizeTypeAction llvm::TargetLoweringBase::getTypeAction ( LLVMContext Context,
EVT  VT 
) const
inline

Return how we should legalize values of this type, either it is already legal (return 'Legal') or we need to promote it to a larger type (return 'Promote'), or we need to expand it into multiple registers of smaller integer type (return 'Expand').

'Custom' is not an option.

Definition at line 437 of file TargetLowering.h.

Referenced by FindMemType(), llvm::SelectionDAG::getConstant(), getTypeToExpandTo(), getVectorTypeBreakdown(), OptimizeNoopCopyExpression(), and shouldNormalizeToSelectSequence().

LegalizeTypeAction llvm::TargetLoweringBase::getTypeAction ( MVT  VT) const
inline
std::pair< unsigned, MVT > TargetLoweringBase::getTypeLegalizationCost ( const DataLayout DL,
Type Ty 
) const
EVT llvm::TargetLoweringBase::getTypeToExpandTo ( LLVMContext Context,
EVT  VT 
) const
inline

For types supported by the target, this is an identity function.

For types that must be expanded (i.e. integer types that are larger than the largest integer register or illegal floating point types), this returns the largest legal type it will be expanded to.

Definition at line 458 of file TargetLowering.h.

References getTypeAction(), getTypeToTransformTo(), llvm::EVT::isVector(), llvm_unreachable, TypeExpandInteger, and TypeLegal.

MVT llvm::TargetLoweringBase::getTypeToPromoteTo ( unsigned  Op,
MVT  VT 
) const
inline

If the action for this operation is to promote, this method returns the ValueType to promote to.

Definition at line 692 of file TargetLowering.h.

References getOperationAction(), llvm::MVT::isFloatingPoint(), llvm::MVT::isInteger(), isTypeLegal(), llvm::MVT::isVoid, Promote, and llvm::MVT::SimpleTy.

EVT llvm::TargetLoweringBase::getTypeToTransformTo ( LLVMContext Context,
EVT  VT 
) const
inline

For types supported by the target, this is an identity function.

For types that must be promoted to larger types, this returns the larger type to promote to. For integer types that are larger than the largest integer register, this contains one step in the expansion to get to the smaller register. For illegal floating point types, this returns the integer type to transform to.

Definition at line 450 of file TargetLowering.h.

Referenced by llvm::FunctionLoweringInfo::ComputePHILiveOutRegInfo(), llvm::SelectionDAG::getConstant(), getMemcpyLoadsAndStores(), llvm::SelectionDAG::getNode(), llvm::FastISel::getRegForValue(), getRegisterType(), llvm::SelectionDAG::GetSplitDestVTs(), getTypeToExpandTo(), getVectorTypeBreakdown(), OptimizeNoopCopyExpression(), and llvm::FastISel::selectBinaryOp().

EVT llvm::TargetLoweringBase::getValueType ( const DataLayout DL,
Type Ty,
bool  AllowUnknown = false 
) const
inline

Return the EVT corresponding to this LLVM type.

This is fixed by the LLVM operations except for the pointer size. If AllowUnknown is true, this will return MVT::Other for types with no EVT counterpart (e.g. structs), otherwise it will assert.

Definition at line 719 of file TargetLowering.h.

References llvm::Type::getContext(), llvm::SequentialType::getElementType(), llvm::EVT::getEVT(), llvm::VectorType::getNumElements(), getPointerTy(), llvm::EVT::getTypeForEVT(), llvm::EVT::getVectorVT(), and llvm::Type::isVectorTy().

Referenced by CompactSwizzlableVector(), llvm::ComputeValueVTs(), llvm::X86TTIImpl::getCastInstrCost(), llvm::ARMTTIImpl::getCastInstrCost(), llvm::AArch64TTIImpl::getCastInstrCost(), llvm::ARMTTIImpl::getCmpSelInstrCost(), llvm::AArch64TTIImpl::getCmpSelInstrCost(), llvm::X86TTIImpl::getMaskedMemoryOpCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getMemoryOpCost(), llvm::NVPTXTargetLowering::getPrototype(), llvm::FastISel::getRegForValue(), getSimpleValueType(), llvm::NVPTXTargetLowering::getTgtMemIntrinsic(), getTypeLegalizationCost(), llvm::SelectionDAGBuilder::getValueImpl(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::haveFastSqrt(), llvm::ARMTargetLowering::isLegalAddressingMode(), llvm::AArch64TargetLowering::isProfitableToHoist(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::isTypeLegal(), llvm::NVPTXTargetLowering::LowerCall(), llvm::TargetLowering::LowerCallTo(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::NVPTXTargetLowering::LowerReturn(), llvm::TargetLowering::makeLibCall(), OptimizeExtractBits(), OptimizeNoopCopyExpression(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::FastISel::selectBitCast(), llvm::FastISel::selectCast(), llvm::FastISel::selectExtractValue(), llvm::FastISel::selectFNeg(), llvm::FastISel::selectOperator(), and SinkShiftAndTruncate().

const ValueTypeActionImpl& llvm::TargetLoweringBase::getValueTypeActions ( ) const
inline

Definition at line 429 of file TargetLowering.h.

virtual MVT llvm::TargetLoweringBase::getVectorIdxTy ( const DataLayout DL) const
inlinevirtual
unsigned TargetLoweringBase::getVectorTypeBreakdown ( LLVMContext Context,
EVT  VT,
EVT IntermediateVT,
unsigned NumIntermediates,
MVT RegisterVT 
) const

Vector types are broken down into some number of legal first class types.

getVectorTypeBreakdown - Vector types are broken down into some number of legal first class types.

For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86.

This method returns the number of registers needed, and the VT for each register. It also returns the VT and quantity of the intermediate values before they are promoted/expanded.

For example, MVT::v8f32 maps to 2 MVT::v4f32 with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.

This method returns the number of registers needed, and the VT for each register. It also returns the VT and quantity of the intermediate values before they are promoted/expanded.

Definition at line 1408 of file TargetLoweringBase.cpp.

References getRegisterType(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), getTypeAction(), getTypeToTransformTo(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::isPowerOf2_32(), isTypeLegal(), llvm::NextPowerOf2(), llvm::X86II::TA, TypePromoteInteger, and TypeWidenVector.

Referenced by getCopyFromPartsVector(), getNumRegisters(), and getRegisterType().

bool llvm::TargetLoweringBase::hasBigEndianPartOrdering ( EVT  VT,
const DataLayout DL 
) const
inline

When splitting a value of the specified type into parts, does the Lo or Hi part come first? This usually follows the endianness, except for ppcf128, where the Hi part always comes first.

Definition at line 824 of file TargetLowering.h.

References llvm::DataLayout::isBigEndian(), and llvm::MVT::ppcf128.

Referenced by getCopyFromParts().

bool llvm::TargetLoweringBase::hasExtractBitsInsn ( ) const
inline

Return true if the target has BitExtract instructions.

Definition at line 200 of file TargetLowering.h.

bool llvm::TargetLoweringBase::hasFloatingPointExceptions ( ) const
inline

Return true if target supports floating point exceptions.

Definition at line 318 of file TargetLowering.h.

Referenced by llvm::SelectionDAG::getNode().

virtual bool llvm::TargetLoweringBase::hasLoadLinkedStoreConditional ( ) const
inlinevirtual

True if AtomicExpandPass should use emitLoadLinked/emitStoreConditional and expand AtomicCmpXchgInst.

Reimplemented in llvm::ARMTargetLowering, llvm::AArch64TargetLowering, and llvm::HexagonTargetLowering.

Definition at line 1023 of file TargetLowering.h.

bool llvm::TargetLoweringBase::hasMultipleConditionRegisters ( ) const
inline

Return true if multiple condition registers are available.

Definition at line 195 of file TargetLowering.h.

Referenced by shouldNormalizeToSelectSequence().

virtual bool llvm::TargetLoweringBase::hasPairedLoad ( Type ,
unsigned  
) const
inlinevirtual

Return true if the target supplies and combines to a paired load two loaded values of type LoadedType next to each other in memory.

RequiredAlignment gives the minimal alignment constraints that must be met to be able to select this paired load.

This information is not used to generate actual paired loads, but it is used to generate a sequence of loads that is easier to combine into a paired load. For instance, something like this: a = load i64* addr b = trunc i64 a to i32 c = lshr i64 a, 32 d = trunc i64 c to i32 will be optimized into: b = load i32* addr1 d = load i32* addr2 Where addr1 = addr2 +/- sizeof(i32).

In other words, unless the target performs a post-isel load combining, this information should not be provided because it will generate more loads.

Reimplemented in llvm::AArch64TargetLowering.

Definition at line 1593 of file TargetLowering.h.

virtual bool llvm::TargetLoweringBase::hasPairedLoad ( EVT  ,
unsigned  
) const
inlinevirtual

Reimplemented in llvm::AArch64TargetLowering.

Definition at line 1598 of file TargetLowering.h.

bool llvm::TargetLoweringBase::hasTargetDAGCombine ( ISD::NodeType  NT) const
inline

If true, the target has custom DAG combine transformations that it can perform for the specified node.

Definition at line 830 of file TargetLowering.h.

References llvm::array_lengthof().

void TargetLoweringBase::initActions ( )
protected
int TargetLoweringBase::InstructionOpcodeToISD ( unsigned  Opcode) const

Get the ISD node that corresponds to the Instruction class opcode.

Definition at line 1535 of file TargetLoweringBase.cpp.

References llvm::ISD::ADD, llvm::ISD::ADDRSPACECAST, llvm::ISD::AND, llvm::APIntOps::And(), llvm::ISD::BITCAST, llvm::Call, llvm::ISD::EXTRACT_VECTOR_ELT, ExtractElement(), llvm::ISD::FADD, llvm::ISD::FDIV, llvm::ISD::FMUL, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::ISD::FREM, llvm::ISD::FSUB, llvm::ISD::INSERT_VECTOR_ELT, llvm_unreachable, llvm::SPII::Load, llvm::ISD::LOAD, llvm::ISD::MERGE_VALUES, llvm::ISD::MUL, llvm::ISD::OR, llvm::APIntOps::Or(), llvm::TargetOpcode::PHI, llvm::MipsISD::Ret, llvm::ISD::SDIV, llvm::MCID::Select, llvm::ISD::SELECT, llvm::ISD::SETCC, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::SRA, llvm::ISD::SREM, llvm::ISD::SRL, llvm::SPII::Store, llvm::ISD::STORE, llvm::ISD::SUB, llvm::ISD::TRUNCATE, llvm::ISD::UDIV, llvm::ISD::UINT_TO_FP, llvm::ISD::UREM, llvm::ISD::VECTOR_SHUFFLE, llvm::ISD::XOR, llvm::APIntOps::Xor(), and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::NVPTXTTIImpl::getArithmeticInstrCost(), llvm::X86TTIImpl::getArithmeticInstrCost(), llvm::PPCTTIImpl::getArithmeticInstrCost(), llvm::AArch64TTIImpl::getArithmeticInstrCost(), llvm::ARMTTIImpl::getArithmeticInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getArithmeticInstrCost(), llvm::X86TTIImpl::getCastInstrCost(), llvm::PPCTTIImpl::getCastInstrCost(), llvm::ARMTTIImpl::getCastInstrCost(), llvm::AArch64TTIImpl::getCastInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCastInstrCost(), llvm::X86TTIImpl::getCmpSelInstrCost(), llvm::ARMTTIImpl::getCmpSelInstrCost(), llvm::AArch64TTIImpl::getCmpSelInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCmpSelInstrCost(), llvm::X86TTIImpl::getReductionCost(), llvm::PPCTTIImpl::getVectorInstrCost(), and SinkShiftAndTruncate().

virtual bool llvm::TargetLoweringBase::isCheapToSpeculateCtlz ( ) const
inlinevirtual

Return true if it is cheap to speculate a call to intrinsic ctlz.

Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, and llvm::AMDGPUTargetLowering.

Definition at line 285 of file TargetLowering.h.

virtual bool llvm::TargetLoweringBase::isCheapToSpeculateCttz ( ) const
inlinevirtual

Return true if it is cheap to speculate a call to intrinsic cttz.

Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, and llvm::AMDGPUTargetLowering.

Definition at line 280 of file TargetLowering.h.

bool llvm::TargetLoweringBase::isCondCodeLegal ( ISD::CondCode  CC,
MVT  VT 
) const
inline

Return true if the specified condition code is legal on this target.

Definition at line 683 of file TargetLowering.h.

References Custom, getCondCodeAction(), and Legal.

Referenced by llvm::SelectionDAG::FoldSetCC(), llvm::R600TargetLowering::PerformDAGCombine(), and llvm::TargetLowering::SimplifySetCC().

bool llvm::TargetLoweringBase::isExtFree ( const Instruction I) const
inline

Return true if the extension represented by I is free.

Unlikely the is[Z|FP]ExtFree family which is based on types, this method can use the context provided by I to decide whether or not I is free. This method extends the behavior of the is[Z|FP]ExtFree family. In other words, if is[Z|FP]Free returns true, then this method returns true as well. The converse is not true. The target can perform the adequate checks by overriding isExtFreeImpl.

Precondition
I must be a sign, zero, or fp extension.

Definition at line 1538 of file TargetLowering.h.

References llvm::EVT::getEVT(), llvm::Instruction::getOpcode(), llvm::User::getOperand(), llvm::Value::getType(), isExtFreeImpl(), isFPExtFree(), isZExtFree(), and llvm_unreachable.

virtual bool llvm::TargetLoweringBase::isExtFreeImpl ( const Instruction I) const
inlineprotectedvirtual

Return true if the extension represented by I is free.

Precondition
I is a sign, zero, or fp extension and is[Z|FP]ExtFree of the related types is not true.

Definition at line 1948 of file TargetLowering.h.

Referenced by isExtFree().

virtual bool llvm::TargetLoweringBase::isExtractSubvectorCheap ( EVT  ResVT,
unsigned  Index 
) const
inlinevirtual

Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index.

This is needed because EXTRACT_SUBVECTOR usually has custom lowering that depends on the index of the first element, and only the target knows which lowering is cheap.

Reimplemented in llvm::X86TargetLowering.

Definition at line 1698 of file TargetLowering.h.

virtual bool llvm::TargetLoweringBase::isFAbsFree ( EVT  VT) const
inlinevirtual

Return true if an fabs operation is free to the point where it is never worthwhile to replace it with a bitwise operation.

Reimplemented in llvm::AMDGPUTargetLowering.

Definition at line 1660 of file TargetLowering.h.

References llvm::EVT::isFloatingPoint().

virtual bool llvm::TargetLoweringBase::isFMAFasterThanFMulAndFAdd ( EVT  ) const
inlinevirtual

Return true if an FMA operation is faster than a pair of fmul and fadd instructions.

fmuladd intrinsics will be expanded to FMAs when this method returns true, otherwise fmuladd is expanded to fmul + fadd.

NOTE: This may be called before legalization on types for which FMAs are not legal, but should return true if those types will eventually legalize to types that support FMAs. After legalization, it will only be called on types that support FMAs (via Legal or Custom actions)

Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::NVPTXTargetLowering, llvm::SystemZTargetLowering, llvm::AArch64TargetLowering, and llvm::SITargetLowering.

Definition at line 1673 of file TargetLowering.h.

virtual bool llvm::TargetLoweringBase::isFNegFree ( EVT  VT) const
inlinevirtual

Return true if an fneg operation is free to the point where it is never worthwhile to replace it with a bitwise operation.

Reimplemented in llvm::AMDGPUTargetLowering.

Definition at line 1653 of file TargetLowering.h.

References llvm::EVT::isFloatingPoint().

virtual bool llvm::TargetLoweringBase::isFPExtFree ( EVT  VT) const
inlinevirtual

Return true if an fpext operation is free (for instance, because single-precision floating-point numbers are implicitly extended to double-precision).

Reimplemented in llvm::PPCTargetLowering.

Definition at line 1642 of file TargetLowering.h.

References llvm::EVT::isFloatingPoint().

Referenced by isExtFree().

virtual bool llvm::TargetLoweringBase::isFPImmLegal ( const APFloat ,
EVT   
) const
inlinevirtual

Returns true if the target can instruction select the specified FP immediate natively.

If false, the legalizer will materialize the FP immediate as a load from a constant pool.

Reimplemented in llvm::X86TargetLowering, llvm::ARMTargetLowering, llvm::SystemZTargetLowering, llvm::AArch64TargetLowering, llvm::HexagonTargetLowering, and llvm::AMDGPUTargetLowering.

Definition at line 514 of file TargetLowering.h.

bool llvm::TargetLoweringBase::isFsqrtCheap ( ) const
inline

Return true if sqrt(x) is as cheap or cheaper than 1 / rsqrt(x)

Definition at line 232 of file TargetLowering.h.

bool llvm::TargetLoweringBase::isIndexedLoadLegal ( unsigned  IdxMode,
EVT  VT 
) const
inline

Return true if the specified indexed load is legal on this target.

Definition at line 642 of file TargetLowering.h.

References Custom, getIndexedLoadAction(), llvm::EVT::getSimpleVT(), llvm::EVT::isSimple(), and Legal.

bool llvm::TargetLoweringBase::isIndexedStoreLegal ( unsigned  IdxMode,
EVT  VT 
) const
inline

Return true if the specified indexed load is legal on this target.

Definition at line 660 of file TargetLowering.h.

References Custom, getIndexedStoreAction(), llvm::EVT::getSimpleVT(), llvm::EVT::isSimple(), and Legal.

bool llvm::TargetLoweringBase::isIntDivCheap ( ) const
inline

Return true if integer divide is usually cheaper than a sequence of several shifts, adds, and multiplies for this target.

Definition at line 229 of file TargetLowering.h.

bool llvm::TargetLoweringBase::isJumpExpensive ( ) const
inline

Return true if Flow Control is an expensive operation that should be avoided.

Definition at line 250 of file TargetLowering.h.

virtual bool llvm::TargetLoweringBase::isLegalAddImmediate ( int64_t  ) const
inlinevirtual

Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register with the immediate without having to materialize the immediate into a register.

Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::SystemZTargetLowering, llvm::AArch64TargetLowering, and llvm::ARMTargetLowering.

Definition at line 1495 of file TargetLowering.h.

Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::isLegalAddImmediate().

bool TargetLoweringBase::isLegalAddressingMode ( const DataLayout DL,
const AddrMode AM,
Type Ty,
unsigned  AS 
) const
virtual

Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type.

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type.

The type may be VoidTy, in which case only return true if the addressing mode is legal for a load/store of any legal type. TODO: Handle pre/postinc as well.

If the address space cannot be determined, it will be -1.

TODO: Remove default argument

Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::NVPTXTargetLowering, llvm::SystemZTargetLowering, llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::HexagonTargetLowering, llvm::XCoreTargetLowering, and llvm::SITargetLowering.

Definition at line 1636 of file TargetLoweringBase.cpp.

References llvm::TargetLoweringBase::AddrMode::BaseGV, llvm::TargetLoweringBase::AddrMode::BaseOffs, llvm::TargetLoweringBase::AddrMode::HasBaseReg, and llvm::TargetLoweringBase::AddrMode::Scale.

Referenced by canFoldInAddressingMode(), getScalingFactorCost(), and llvm::BasicTTIImplBase< AMDGPUTTIImpl >::isLegalAddressingMode().

virtual bool llvm::TargetLoweringBase::isLegalICmpImmediate ( int64_t  ) const
inlinevirtual

Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register.

Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::SystemZTargetLowering, llvm::AArch64TargetLowering, llvm::ARMTargetLowering, and llvm::HexagonTargetLowering.

Definition at line 1488 of file TargetLowering.h.

Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::isLegalICmpImmediate(), and llvm::TargetLowering::SimplifySetCC().

bool TargetLoweringBase::isLegalRC ( const TargetRegisterClass RC) const
protected

Return true if the value types that can be represented by the specified register class are all legal.

isLegalRC - Return true if the value types that can be represented by the specified register class are all legal.

Definition at line 1099 of file TargetLoweringBase.cpp.

References I, isTypeLegal(), llvm::TargetRegisterClass::vt_begin(), and llvm::TargetRegisterClass::vt_end().

Referenced by findRepresentativeClass(), and llvm::TargetLowering::getRegForInlineAsmConstraint().

virtual bool llvm::TargetLoweringBase::isLoadBitCastBeneficial ( EVT  ,
EVT   
) const
inlinevirtual

isLoadBitCastBeneficial() - Return true if the following transform is beneficial.

fold (conv (load x)) -> (load (conv*)x) On architectures that don't natively support some vector loads efficiently, casting the load to a smaller vector of larger types and loading is more efficient, however, this can be undone by optimizations in dag combiner.

Reimplemented in llvm::AMDGPUTargetLowering.

Definition at line 265 of file TargetLowering.h.

bool llvm::TargetLoweringBase::isLoadExtLegal ( unsigned  ExtType,
EVT  ValVT,
EVT  MemVT 
) const
inline

Return true if the specified load with extension is legal on this target.

Definition at line 598 of file TargetLowering.h.

References getLoadExtAction(), llvm::EVT::isSimple(), and Legal.

bool llvm::TargetLoweringBase::isLoadExtLegalOrCustom ( unsigned  ExtType,
EVT  ValVT,
EVT  MemVT 
) const
inline

Return true if the specified load with extension is legal or custom on this target.

Definition at line 605 of file TargetLowering.h.

References Custom, getLoadExtAction(), llvm::EVT::isSimple(), and Legal.

bool llvm::TargetLoweringBase::isMaskAndBranchFoldingLegal ( ) const
inline

Return if the target supports combining a chain like:

%andResult = and %val1, #imm-with-one-bit-set;
%icmpResult = icmp %andResult, 0
br i1 %icmpResult, label %dest1, label %dest2

into a single machine instruction of a form like:

brOnBitSet %register, #bitNumber, dest

Definition at line 300 of file TargetLowering.h.

References MaskAndBranchFoldingIsLegal.

virtual bool llvm::TargetLoweringBase::isNarrowingProfitable ( EVT  ,
EVT   
) const
inlinevirtual

Return true if it's profitable to narrow operations of type VT1 to VT2.

e.g. on x86, it's profitable to narrow from i32 to i8 but not from i32 to i16.

Reimplemented in llvm::X86TargetLowering, and llvm::AMDGPUTargetLowering.

Definition at line 1680 of file TargetLowering.h.

virtual bool llvm::TargetLoweringBase::isNoopAddrSpaceCast ( unsigned  SrcAS,
unsigned  DestAS 
) const
inlinevirtual

Returns true if a cast between SrcAS and DestAS is a noop.

Reimplemented in llvm::X86TargetLowering, llvm::ARMTargetLowering, and llvm::AArch64TargetLowering.

Definition at line 991 of file TargetLowering.h.

bool llvm::TargetLoweringBase::isOperationExpand ( unsigned  Op,
EVT  VT 
) const
inline

Return true if the specified operation is illegal on this target or unlikely to be made legal with custom lowering.

This is used to help guide high-level lowering decisions.

Definition at line 574 of file TargetLowering.h.

References Expand, getOperationAction(), and isTypeLegal().

Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getArithmeticInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCastInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCmpSelInstrCost(), and llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getIntrinsicInstrCost().

bool llvm::TargetLoweringBase::isOperationLegal ( unsigned  Op,
EVT  VT 
) const
inline
bool llvm::TargetLoweringBase::isOperationLegalOrCustom ( unsigned  Op,
EVT  VT 
) const
inline
bool llvm::TargetLoweringBase::isOperationLegalOrPromote ( unsigned  Op,
EVT  VT 
) const
inline

Return true if the specified operation is legal on this target or can be made legal using promotion.

This is used to help guide high-level lowering decisions.

Definition at line 565 of file TargetLowering.h.

References getOperationAction(), isTypeLegal(), Legal, llvm::MVT::Other, and Promote.

Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getArithmeticInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCastInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getIntrinsicInstrCost(), and WidenMaskArithmetic().

bool llvm::TargetLoweringBase::isPow2SDivCheap ( ) const
inline

Return true if pow2 sdiv is cheaper than a chain of sra/srl/add/sra.

Definition at line 246 of file TargetLowering.h.

bool llvm::TargetLoweringBase::isPredictableSelectExpensive ( ) const
inline

Return true if selects are only cheaper than branches if the branch is unlikely to be predicted right.

Definition at line 254 of file TargetLowering.h.

References PredictableSelectIsExpensive.

virtual bool llvm::TargetLoweringBase::isProfitableToHoist ( Instruction I) const
inlinevirtual
virtual bool llvm::TargetLoweringBase::isSafeMemOpType ( MVT  ) const
inlinevirtual

Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline.

This is mostly true for all types except for some special cases. For example, on X86 targets without SSE2 f64 load / store are done with fldl / fstpl which also does type conversion. Note the specified type doesn't have to be legal as the hook is used before type legalization.

Reimplemented in llvm::X86TargetLowering.

Definition at line 908 of file TargetLowering.h.

Referenced by FindOptimalMemOpLowering().

bool llvm::TargetLoweringBase::isSelectExpensive ( ) const
inline

Return true if the select operation is expensive for this target.

Definition at line 188 of file TargetLowering.h.

virtual bool llvm::TargetLoweringBase::isSelectSupported ( SelectSupportKind  ) const
inlinevirtual

Reimplemented in llvm::ARMTargetLowering, and llvm::AMDGPUTargetLowering.

Definition at line 190 of file TargetLowering.h.

virtual bool llvm::TargetLoweringBase::isShuffleMaskLegal ( const SmallVectorImpl< int > &  ,
EVT   
) const
inlinevirtual

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks.

By default, if a target supports the VECTOR_SHUFFLE node, all mask values are assumed to be legal.

Reimplemented in llvm::X86TargetLowering, llvm::ARMTargetLowering, llvm::AArch64TargetLowering, llvm::SITargetLowering, and llvm::MipsSETargetLowering.

Definition at line 522 of file TargetLowering.h.

Referenced by ExpandBVWithShuffles(), and transformVSELECTtoBlendVECTOR_SHUFFLE().

bool llvm::TargetLoweringBase::isSlowDivBypassed ( ) const
inline

Returns true if target has indicated at least one type should be bypassed.

Definition at line 237 of file TargetLowering.h.

References llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::empty().

virtual bool llvm::TargetLoweringBase::isTruncateFree ( Type ,
Type  
) const
inlinevirtual
virtual bool llvm::TargetLoweringBase::isTruncateFree ( EVT  ,
EVT   
) const
inlinevirtual
bool llvm::TargetLoweringBase::isTruncStoreLegal ( EVT  ValVT,
EVT  MemVT 
) const
inline

Return true if the specified store with truncation is legal on this target.

Definition at line 625 of file TargetLowering.h.

References llvm::EVT::getSimpleVT(), getTruncStoreAction(), llvm::EVT::isSimple(), isTypeLegal(), and Legal.

bool llvm::TargetLoweringBase::isTypeLegal ( EVT  VT) const
inline

Return true if the target has native support for the specified value type.

This means that it has a register that directly holds it without promotions or expansions.

Definition at line 403 of file TargetLowering.h.

References llvm::array_lengthof(), llvm::EVT::getSimpleVT(), llvm::EVT::isSimple(), and llvm::MVT::SimpleTy.

Referenced by llvm::ARMTargetLowering::allowTruncateForTailCall(), llvm::X86TargetLowering::allowTruncateForTailCall(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), canOpTrap(), combineConcatVectorOfScalars(), computeRegisterProperties(), EltsFromConsecutiveLoads(), ExpandBITCAST(), ExpandUnalignedLoad(), ExpandUnalignedStore(), FindMemType(), FindOptimalMemOpLowering(), getCopyFromPartsVector(), getCopyToParts(), llvm::FastISel::getRegForValue(), getTypeToPromoteTo(), getVectorTypeBreakdown(), getVectorTypeBreakdownMVT(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::haveFastSqrt(), llvm::GenericScheduler::initPolicy(), isLegalRC(), isNoopBitcast(), isOperationExpand(), isOperationLegal(), isOperationLegalOrCustom(), isOperationLegalOrPromote(), llvm::X86TargetLowering::isShuffleMaskLegal(), isTruncStoreLegal(), llvm::X86TargetLowering::isTypeDesirableForOp(), llvm::TargetLowering::isTypeDesirableForOp(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::isTypeLegal(), llvm::NVPTXTargetLowering::isTypeSupportedInIntrinsic(), llvm::ARMTargetLowering::isVectorLoadExtDesirable(), LowerADDC_ADDE_SUBC_SUBE(), LowerATOMIC_STORE(), LowerExtendedLoad(), LowerFP_TO_SINT(), LowerFP_TO_UINT(), LowerSINT_TO_FP(), LowerUINT_TO_FP(), lowerVectorShuffle(), lowerVectorShuffleAsShift(), LowerXALUO(), OptimizeExtractBits(), PerformANDCombine(), performExtendCombine(), PerformExtendCombine(), PerformFMACombine(), PerformLOADCombine(), PerformMLOADCombine(), PerformMSTORECombine(), performORCombine(), PerformORCombine(), performSelectCombine(), PerformSELECTCombine(), PerformShiftCombine(), PerformShuffleCombine(), PerformSTORECombine(), PerformVECTOR_SHUFFLECombine(), PerformXORCombine(), llvm::ResourcePriorityQueue::rawRegPressureDelta(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::ResourcePriorityQueue::scheduledNode(), llvm::FastISel::selectBinaryOp(), llvm::FastISel::selectBitCast(), llvm::FastISel::selectCast(), llvm::FastISel::selectExtractValue(), llvm::FastISel::selectFNeg(), llvm::TargetLowering::SimplifySetCC(), llvm::SystemZTargetLowering::SystemZTargetLowering(), tryToFoldExtendOfConstant(), and llvm::SelectionDAGBuilder::visitBitTestHeader().

virtual bool llvm::TargetLoweringBase::isVectorClearMaskLegal ( const SmallVectorImpl< int > &  ,
EVT   
) const
inlinevirtual

Similar to isShuffleMaskLegal.

This is used by Targets can use this to indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a constant pool entry.

Reimplemented in llvm::X86TargetLowering.

Definition at line 536 of file TargetLowering.h.

virtual bool llvm::TargetLoweringBase::isVectorLoadExtDesirable ( SDValue  ExtVal) const
inlinevirtual

Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable.

Reimplemented in llvm::X86TargetLowering, and llvm::ARMTargetLowering.

Definition at line 1649 of file TargetLowering.h.

virtual bool llvm::TargetLoweringBase::isVectorShiftByScalarCheap ( Type Ty) const
inlinevirtual

Return true if it's significantly cheaper to shift a vector by a uniform scalar than by an amount which will vary across each lane.

On x86, for example, there is a "psllw" instruction for the former case, but no simple instruction for a general "a << b" operation on vectors.

Reimplemented in llvm::X86TargetLowering.

Definition at line 1503 of file TargetLowering.h.

virtual bool llvm::TargetLoweringBase::isZExtFree ( Type ,
Type  
) const
inlinevirtual

Return true if any actual instruction that defines a value of type Ty1 implicitly zero-extends the value to Ty2 in the result register.

This does not necessarily include registers defined in unknown ways, such as incoming arguments, or copies from unknown virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this does not necessarily apply to truncate instructions. e.g. on x86-64, all instructions that define 32-bit values implicit zero-extend the result out to 64 bits.

Reimplemented in llvm::X86TargetLowering, llvm::AArch64TargetLowering, llvm::AMDGPUTargetLowering, and llvm::MSP430TargetLowering.

Definition at line 1564 of file TargetLowering.h.

Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCastInstrCost(), llvm::RegsForValue::getCopyToRegs(), llvm::SelectionDAG::getNode(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getOperationCost(), hasSameExtUse(), isExtFree(), llvm::PPCTargetLowering::isZExtFree(), isZExtFree(), and llvm::TargetLowering::TargetLoweringOpt::ShrinkDemandedOp().

virtual bool llvm::TargetLoweringBase::isZExtFree ( EVT  ,
EVT   
) const
inlinevirtual
virtual bool llvm::TargetLoweringBase::isZExtFree ( SDValue  Val,
EVT  VT2 
) const
inlinevirtual

Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicitly zero-extended such as ARM ldrb / ldrh or because it's folded such as X86 zero-extending loads).

Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::AMDGPUTargetLowering, llvm::MSP430TargetLowering, and llvm::XCoreTargetLowering.

Definition at line 1635 of file TargetLowering.h.

References llvm::SDValue::getValueType(), and isZExtFree().

virtual LoadInst* llvm::TargetLoweringBase::lowerIdempotentRMWIntoFencedLoad ( AtomicRMWInst RMWI) const
inlinevirtual

On some platforms, an AtomicRMW that never actually modifies the value (such as fetch_add of 0) can be turned into a fence followed by an atomic load.

This may sound useless, but it makes it possible for the processor to keep the cacheline shared, dramatically improving performance. And such idempotent RMWs are useful for implementing some kinds of locks, see for example (justification + benchmarks): http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf This method tries doing that transformation, returning the atomic load if it succeeds, and nullptr otherwise. If shouldExpandAtomicLoadInIR returns true on that load, it will undergo another round of expansion.

Definition at line 1131 of file TargetLowering.h.

virtual bool llvm::TargetLoweringBase::lowerInterleavedLoad ( LoadInst LI,
ArrayRef< ShuffleVectorInst * >  Shuffles,
ArrayRef< unsigned Indices,
unsigned  Factor 
) const
inlinevirtual

Lower an interleaved load to target specific intrinsics.

Return true on success.

LI is the vector load instruction. Shuffles is the shufflevector list to DE-interleave the loaded vector. Indices is the corresponding indices for each shufflevector. Factor is the interleave factor.

Reimplemented in llvm::ARMTargetLowering, and llvm::AArch64TargetLowering.

Definition at line 1614 of file TargetLowering.h.

virtual bool llvm::TargetLoweringBase::lowerInterleavedStore ( StoreInst SI,
ShuffleVectorInst SVI,
unsigned  Factor 
) const
inlinevirtual

Lower an interleaved store to target specific intrinsics.

Return true on success.

SI is the vector store instruction. SVI is the shufflevector to RE-interleave the stored vector. Factor is the interleave factor.

Reimplemented in llvm::ARMTargetLowering, and llvm::AArch64TargetLowering.

Definition at line 1627 of file TargetLowering.h.

void llvm::TargetLoweringBase::setBooleanContents ( BooleanContent  Ty)
inlineprotected
void llvm::TargetLoweringBase::setBooleanContents ( BooleanContent  IntTy,
BooleanContent  FloatTy 
)
inlineprotected

Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type.

See getBooleanContents.

Definition at line 1167 of file TargetLowering.h.

void llvm::TargetLoweringBase::setBooleanVectorContents ( BooleanContent  Ty)
inlineprotected
void llvm::TargetLoweringBase::setCmpLibcallCC ( RTLIB::Libcall  Call,
ISD::CondCode  CC 
)
inline

Override the default CondCode to be used to test the result of the comparison libcall against zero.

Definition at line 1718 of file TargetLowering.h.

References llvm::Call.

Referenced by llvm::ARMTargetLowering::ARMTargetLowering().

void llvm::TargetLoweringBase::setCondCodeAction ( ISD::CondCode  CC,
MVT  VT,
LegalizeAction  Action 
)
inlineprotected

Indicate that the specified condition code is or isn't supported on the target and indicate what to do about it.

The lower 5 bits of the SimpleTy index into Nth 2bit set from the 32-bit value and the upper 27 bits index into the second dimension of the array to select what 32-bit value to use.

Definition at line 1355 of file TargetLowering.h.

References llvm::array_lengthof(), llvm::MVT::isValid(), and llvm::MVT::SimpleTy.

Referenced by llvm::MipsSETargetLowering::addMSAFloatType(), llvm::MipsSETargetLowering::addMSAIntType(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::MipsSETargetLowering::MipsSETargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::R600TargetLowering::R600TargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().

void llvm::TargetLoweringBase::setExceptionPointerRegister ( unsigned  R)
inlineprotected
void llvm::TargetLoweringBase::setExceptionSelectorRegister ( unsigned  R)
inlineprotected
void llvm::TargetLoweringBase::setFsqrtIsCheap ( bool  isCheap = true)
inlineprotected

Tells the code generator that fsqrt is cheap, and should not be replaced with an alternative sequence of instructions.

Definition at line 1254 of file TargetLowering.h.

Referenced by llvm::AMDGPUTargetLowering::AMDGPUTargetLowering().

void llvm::TargetLoweringBase::setHasExtractBitsInsn ( bool  hasExtractInsn = true)
inlineprotected

Tells the code generator that the target has BitExtract instructions.

The code generator will aggressively sink "shift"s into the blocks of their users if the users will generate "and" instructions which can be combined with "shift" to BitExtract instructions.

Definition at line 1238 of file TargetLowering.h.

Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering().

void llvm::TargetLoweringBase::setHasFloatingPointExceptions ( bool  FPExceptions = true)
inlineprotected

Tells the code generator that this target supports floating point exceptions and cares about preserving floating point exception behavior.

Definition at line 1258 of file TargetLowering.h.

Referenced by llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), and llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering().

void llvm::TargetLoweringBase::setHasMultipleConditionRegisters ( bool  hasManyRegs = true)
inlineprotected

Tells the code generator that the target has multiple (allocatable) condition registers that can be used to store the results of comparisons for use by selects and conditional branches.

With multiple condition registers, the code generator will not aggressively sink comparisons into the blocks of their users.

Definition at line 1230 of file TargetLowering.h.

Referenced by llvm::PPCTargetLowering::PPCTargetLowering().

void llvm::TargetLoweringBase::setIndexedLoadAction ( unsigned  IdxMode,
MVT  VT,
LegalizeAction  Action 
)
inlineprotected

Indicate that the specified indexed load does or does not work with the specified type and indicate what to do abort it.

NOTE: All indexed mode loads are initialized to Expand in TargetLowering.cpp

Definition at line 1330 of file TargetLowering.h.

References llvm::MVT::isValid(), llvm::ISD::LAST_INDEXED_MODE, and llvm::MVT::SimpleTy.

Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), initActions(), llvm::MSP430TargetLowering::MSP430TargetLowering(), and llvm::PPCTargetLowering::PPCTargetLowering().

void llvm::TargetLoweringBase::setIndexedStoreAction ( unsigned  IdxMode,
MVT  VT,
LegalizeAction  Action 
)
inlineprotected

Indicate that the specified indexed store does or does not work with the specified type and indicate what to do about it.

NOTE: All indexed mode stores are initialized to Expand in TargetLowering.cpp

Definition at line 1344 of file TargetLowering.h.

References llvm::MVT::isValid(), llvm::ISD::LAST_INDEXED_MODE, and llvm::MVT::SimpleTy.

Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), initActions(), and llvm::PPCTargetLowering::PPCTargetLowering().

void llvm::TargetLoweringBase::setInsertFencesForAtomic ( bool  fence)
inlineprotected
void llvm::TargetLoweringBase::setIntDivIsCheap ( bool  isCheap = true)
inlineprotected

Tells the code generator that integer divide is expensive, and if possible, should be replaced by an alternate sequence of instructions not containing an integer divide.

Definition at line 1250 of file TargetLowering.h.

Referenced by llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), llvm::MSP430TargetLowering::MSP430TargetLowering(), and llvm::XCoreTargetLowering::XCoreTargetLowering().

void llvm::TargetLoweringBase::setJumpBufAlignment ( unsigned  Align)
inlineprotected

Set the target's required jmp_buf buffer alignment (in bytes); default is 0.

Definition at line 1390 of file TargetLowering.h.

References Align().

void llvm::TargetLoweringBase::setJumpBufSize ( unsigned  Size)
inlineprotected

Set the target's required jmp_buf buffer size (in bytes); default is 200.

Definition at line 1384 of file TargetLowering.h.

void TargetLoweringBase::setJumpIsExpensive ( bool  isExpensive = true)
protected

Tells the code generator not to expand logic operations on comparison predicates into separate sequences that increase the amount of flow control.

Definition at line 911 of file TargetLoweringBase.cpp.

References JumpIsExpensiveOverride.

Referenced by llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), and llvm::PPCTargetLowering::PPCTargetLowering().

void llvm::TargetLoweringBase::setLibcallCallingConv ( RTLIB::Libcall  Call,
CallingConv::ID  CC 
)
inline

Set the CallingConv that should be used for the specified libcall.

Definition at line 1729 of file TargetLowering.h.

References llvm::Call.

Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().

void llvm::TargetLoweringBase::setLibcallName ( RTLIB::Libcall  Call,
const char *  Name 
)
inline
void llvm::TargetLoweringBase::setLoadExtAction ( unsigned  ExtType,
MVT  ValVT,
MVT  MemVT,
LegalizeAction  Action 
)
inlineprotected
void llvm::TargetLoweringBase::setMinFunctionAlignment ( unsigned  Align)
inlineprotected
void llvm::TargetLoweringBase::setMinimumJumpTableEntries ( int  Val)
inlineprotected

Indicate the number of blocks to generate jump tables rather than if sequence.

Definition at line 1197 of file TargetLowering.h.

Referenced by llvm::HexagonTargetLowering::HexagonTargetLowering().

void llvm::TargetLoweringBase::setMinStackArgumentAlignment ( unsigned  Align)
inlineprotected

Set the minimum stack alignment of an argument (in log2(bytes)).

Definition at line 1415 of file TargetLowering.h.

References Align().

Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), llvm::MipsTargetLowering::MipsTargetLowering(), and llvm::PPCTargetLowering::PPCTargetLowering().

void llvm::TargetLoweringBase::setOperationAction ( unsigned  Op,
MVT  VT,
LegalizeAction  Action 
)
inlineprotected
void llvm::TargetLoweringBase::setPow2SDivIsCheap ( bool  isCheap = true)
inlineprotected

Tells the code generator that it shouldn't generate sra/srl/add/sra for a signed divide by power of two; let the target handle it.

Definition at line 1269 of file TargetLowering.h.

Referenced by llvm::AMDGPUTargetLowering::AMDGPUTargetLowering().

void llvm::TargetLoweringBase::setPrefFunctionAlignment ( unsigned  Align)
inlineprotected

Set the target's preferred function alignment.

This should be set if there is a performance benefit to higher-than-minimum alignment (in log2(bytes))

Definition at line 1402 of file TargetLowering.h.

References Align().

Referenced by llvm::BPFTargetLowering::BPFTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::MSP430TargetLowering::MSP430TargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::X86TargetLowering::X86TargetLowering(), and llvm::XCoreTargetLowering::XCoreTargetLowering().

void llvm::TargetLoweringBase::setPrefLoopAlignment ( unsigned  Align)
inlineprotected

Set the target's preferred loop alignment.

Default alignment is zero, it means the target does not care about loop alignment. The alignment is specified in log2(bytes). The target may also override getPrefLoopAlignment to provide per-loop values.

Definition at line 1410 of file TargetLowering.h.

References Align().

Referenced by llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().

void llvm::TargetLoweringBase::setSchedulingPreference ( Sched::Preference  Pref)
inlineprotected
void llvm::TargetLoweringBase::setSelectIsExpensive ( bool  isExpensive = true)
inlineprotected

Tells the code generator not to expand operations into sequences that use the select operations if possible.

Definition at line 1221 of file TargetLowering.h.

Referenced by llvm::AMDGPUTargetLowering::AMDGPUTargetLowering().

void llvm::TargetLoweringBase::setStackPointerRegisterToSaveRestore ( unsigned  R)
inlineprotected
void llvm::TargetLoweringBase::setTargetDAGCombine ( ISD::NodeType  NT)
inlineprotected
void llvm::TargetLoweringBase::setTruncStoreAction ( MVT  ValVT,
MVT  MemVT,
LegalizeAction  Action 
)
inlineprotected
void llvm::TargetLoweringBase::setUseUnderscoreLongJmp ( bool  Val)
inlineprotected

Indicate whether this target prefers to use _longjmp to implement llvm.longjmp or the version without _.

Defaults to false.

Definition at line 1191 of file TargetLowering.h.

Referenced by llvm::PPCTargetLowering::PPCTargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().

void llvm::TargetLoweringBase::setUseUnderscoreSetJmp ( bool  Val)
inlineprotected

Indicate whether this target prefers to use _setjmp to implement llvm.setjmp or the version without _.

Defaults to false.

Definition at line 1185 of file TargetLowering.h.

Referenced by llvm::PPCTargetLowering::PPCTargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().

virtual bool llvm::TargetLoweringBase::shouldAlignPointerArgs ( CallInst ,
unsigned ,
unsigned  
) const
inlinevirtual

Return true if the pointer arguments to CI should be aligned by aligning the object whose address is being passed.

If so then MinSize is set to the minimum size the object must be to be aligned and PrefAlign is set to the preferred alignment.

Reimplemented in llvm::ARMTargetLowering.

Definition at line 999 of file TargetLowering.h.

virtual bool llvm::TargetLoweringBase::shouldConvertConstantLoadToIntImm ( const APInt Imm,
Type Ty 
) const
inlinevirtual

Return true if it is beneficial to convert a load of a constant to just the constant itself.

On some targets it might be more efficient to use a combination of arithmetic instructions to materialize the constant instead of loading it from a constant pool.

Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::ARMTargetLowering, llvm::AArch64TargetLowering, and llvm::SITargetLowering.

Definition at line 1689 of file TargetLowering.h.

Referenced by getMemsetStringVal().

virtual bool llvm::TargetLoweringBase::shouldExpandAtomicLoadInIR ( LoadInst LI) const
inlinevirtual

Returns true if the given (atomic) load should be expanded by the IR-level AtomicExpand pass into a load-linked instruction (through emitLoadLinked()).

Reimplemented in llvm::ARMTargetLowering, llvm::AArch64TargetLowering, and llvm::HexagonTargetLowering.

Definition at line 1110 of file TargetLowering.h.

virtual AtomicRMWExpansionKind llvm::TargetLoweringBase::shouldExpandAtomicRMWInIR ( AtomicRMWInst ) const
inlinevirtual

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.

Default is to never expand.

Reimplemented in llvm::ARMTargetLowering, llvm::AArch64TargetLowering, and llvm::HexagonTargetLowering.

Definition at line 1115 of file TargetLowering.h.

References None.

virtual bool llvm::TargetLoweringBase::shouldExpandAtomicStoreInIR ( StoreInst SI) const
inlinevirtual

Returns true if the given (atomic) store should be expanded by the IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.

Reimplemented in llvm::ARMTargetLowering, llvm::AArch64TargetLowering, and llvm::HexagonTargetLowering.

Definition at line 1098 of file TargetLowering.h.

virtual bool llvm::TargetLoweringBase::shouldExpandBuildVectorWithShuffles ( EVT  ,
unsigned  DefinedValues 
) const
inlinevirtual
virtual bool llvm::TargetLoweringBase::shouldNormalizeToSelectSequence ( LLVMContext Context,
EVT  VT 
) const
inlinevirtual

Returns true if we should normalize select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely that it saves us from materializing N0 and N1 in an integer register.

Targets that are able to perform and/or on flags should return false here.

Definition at line 1140 of file TargetLowering.h.

References getTypeAction(), hasMultipleConditionRegisters(), TypeExpandFloat, TypeExpandInteger, and TypeSplitVector.

virtual bool llvm::TargetLoweringBase::shouldReduceLoadWidth ( SDNode Load,
ISD::LoadExtType  ExtTy,
EVT  NewVT 
) const
inlinevirtual

Reimplemented in llvm::X86TargetLowering, and llvm::AMDGPUTargetLowering.

Definition at line 815 of file TargetLowering.h.

virtual bool llvm::TargetLoweringBase::ShouldShrinkFPConstant ( EVT  ) const
inlinevirtual

If true, then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime.

Reimplemented in llvm::X86TargetLowering, llvm::SparcTargetLowering, and llvm::AMDGPUTargetLowering.

Definition at line 809 of file TargetLowering.h.

virtual bool llvm::TargetLoweringBase::shouldSignExtendTypeInLibCall ( EVT  Type,
bool  IsSigned 
) const
inlinevirtual

Returns true if arguments should be sign-extended in lib calls.

Definition at line 1103 of file TargetLowering.h.

Referenced by llvm::TargetLowering::makeLibCall().

virtual bool llvm::TargetLoweringBase::storeOfVectorConstantIsCheap ( EVT  MemVT,
unsigned  NumElem,
unsigned  AddrSpace 
) const
inlinevirtual

Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the given size and type for the address space than to store the individual scalar element constants.

Reimplemented in llvm::AMDGPUTargetLowering.

Definition at line 273 of file TargetLowering.h.

virtual bool llvm::TargetLoweringBase::useSoftFloat ( ) const
inlinevirtual

Reimplemented in llvm::X86TargetLowering, and llvm::ARMTargetLowering.

Definition at line 165 of file TargetLowering.h.

bool llvm::TargetLoweringBase::usesUnderscoreLongJmp ( ) const
inline

Determine if we should use _longjmp or longjmp to implement llvm.longjmp.

Definition at line 916 of file TargetLowering.h.

bool llvm::TargetLoweringBase::usesUnderscoreSetJmp ( ) const
inline

Determine if we should use _setjmp or setjmp to implement llvm.setjmp.

Definition at line 911 of file TargetLowering.h.

Member Data Documentation

bool llvm::TargetLoweringBase::EnableExtLdPromotion
protected
bool llvm::TargetLoweringBase::MaskAndBranchFoldingIsLegal
protected

MaskAndBranchFoldingIsLegal - Indicates if the target supports folding a mask of a single bit, a compare, and a branch into a single instruction.

Definition at line 2005 of file TargetLowering.h.

Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), isMaskAndBranchFoldingLegal(), and TargetLoweringBase().

unsigned llvm::TargetLoweringBase::MaxStoresPerMemcpy
protected

Specify maximum bytes of store instructions per memcpy call.

When lowering @llvm.memcpy this field specifies the maximum number of store operations that may be substituted for a call to memcpy. Targets must set this value based on the cost threshold for that target. Targets should assume that the memcpy will be done using as many of the largest store operations first, followed by smaller ones, if necessary, per alignment restrictions. For example, storing 7 bytes on a 32-bit machine with 32-bit alignment would result in one 4-byte store, a one 2-byte store and one 1-byte store. This only applies to copying a constant array of constant size.

Definition at line 1977 of file TargetLowering.h.

Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::BPFTargetLowering::BPFTargetLowering(), getMaxStoresPerMemcpy(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::MipsTargetLowering::MipsTargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), TargetLoweringBase(), llvm::X86TargetLowering::X86TargetLowering(), and llvm::XCoreTargetLowering::XCoreTargetLowering().

unsigned llvm::TargetLoweringBase::MaxStoresPerMemcpyOptSize
protected
unsigned llvm::TargetLoweringBase::MaxStoresPerMemmove
protected

Specify maximum bytes of store instructions per memmove call.

When lowering @llvm.memmove this field specifies the maximum number of store instructions that may be substituted for a call to memmove. Targets must set this value based on the cost threshold for that target. Targets should assume that the memmove will be done using as many of the largest store operations first, followed by smaller ones, if necessary, per alignment restrictions. For example, moving 9 bytes on a 32-bit machine with 8-bit alignment would result in nine 1-byte stores. This only applies to copying a constant array of constant size.

Definition at line 1993 of file TargetLowering.h.

Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::BPFTargetLowering::BPFTargetLowering(), getMaxStoresPerMemmove(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), TargetLoweringBase(), llvm::X86TargetLowering::X86TargetLowering(), and llvm::XCoreTargetLowering::XCoreTargetLowering().

unsigned llvm::TargetLoweringBase::MaxStoresPerMemmoveOptSize
protected
unsigned llvm::TargetLoweringBase::MaxStoresPerMemset
protected

Specify maximum number of store instructions per memset call.

When lowering @llvm.memset this field specifies the maximum number of store operations that may be substituted for the call to memset. Targets must set this value based on the cost threshold for that target. Targets should assume that the memset will be done using as many of the largest store operations first, followed by smaller ones, if necessary, per alignment restrictions. For example, storing 9 bytes on a 32-bit machine with 16-bit alignment would result in four 2-byte stores and one 1-byte store. This only applies to setting a constant array of a constant size.

Definition at line 1960 of file TargetLowering.h.

Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::BPFTargetLowering::BPFTargetLowering(), getMaxStoresPerMemset(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), TargetLoweringBase(), llvm::X86TargetLowering::X86TargetLowering(), and llvm::XCoreTargetLowering::XCoreTargetLowering().

unsigned llvm::TargetLoweringBase::MaxStoresPerMemsetOptSize
protected
bool llvm::TargetLoweringBase::PredictableSelectIsExpensive
protected

The documentation for this class was generated from the following files: