25 #define DEBUG_TYPE "regalloc"
39 while (SegPos.valid()) {
40 SegPos.insert(RegPos->start, RegPos->end, &VirtReg);
41 if (++RegPos == RegEnd)
43 SegPos.advanceTo(RegPos->start);
50 SegPos.insert(RegEnd->start, RegEnd->end, &VirtReg);
51 for (; RegPos != RegEnd; ++RegPos, ++SegPos)
52 SegPos.insert(RegPos->start, RegPos->end, &VirtReg);
67 assert(SegPos.value() == &VirtReg &&
"Inconsistent LiveInterval");
73 RegPos = Range.
advanceTo(RegPos, SegPos.start());
77 SegPos.advanceTo(RegPos->start);
88 OS <<
" [" <<
SI.start() <<
' ' <<
SI.stop() <<
"):"
98 VisitedVRegs.
set(
SI.value()->reg);
106 std::find(InterferingVRegs.begin(), InterferingVRegs.end(), VirtReg);
107 return I != InterferingVRegs.end();
122 if (SeenAllInterferences || InterferingVRegs.size() >= MaxInterferingRegs)
123 return InterferingVRegs.size();
126 if (!CheckedFirstInterference) {
127 CheckedFirstInterference =
true;
130 if (VirtReg->empty() || LiveUnion->empty()) {
131 SeenAllInterferences =
true;
136 VirtRegI = VirtReg->begin();
137 LiveUnionI.setMap(LiveUnion->getMap());
138 LiveUnionI.find(VirtRegI->start);
143 while (LiveUnionI.valid()) {
144 assert(VirtRegI != VirtRegEnd &&
"Reached end of VirtReg");
147 while (VirtRegI->start < LiveUnionI.stop() &&
148 VirtRegI->end > LiveUnionI.start()) {
151 if (VReg != RecentReg && !isSeenInterference(VReg)) {
153 InterferingVRegs.push_back(VReg);
154 if (InterferingVRegs.size() >= MaxInterferingRegs)
155 return InterferingVRegs.
size();
158 if (!(++LiveUnionI).valid()) {
159 SeenAllInterferences =
true;
160 return InterferingVRegs.size();
166 assert(VirtRegI->end <= LiveUnionI.start() &&
"Expected non-overlap");
169 VirtRegI = VirtReg->advanceTo(VirtRegI, LiveUnionI.start());
170 if (VirtRegI == VirtRegEnd)
174 if (VirtRegI->start < LiveUnionI.stop())
178 LiveUnionI.advanceTo(VirtRegI->start);
180 SeenAllInterferences =
true;
181 return InterferingVRegs.size();
193 for (
unsigned i = 0; i != Size; ++i)
200 for (
unsigned i = 0; i != Size; ++i)
const_iterator begin() const
LiveIntervalUnion(Allocator &a)
LiveInterval - This class represents the liveness of a register, or stack slot.
iterator advanceTo(iterator I, SlotIndex Pos)
advanceTo - Advance the specified iterator to point to the Segment containing the specified position...
const_iterator find(KeyT x) const
find - Return an iterator pointing to the first interval ending at or after x, or end()...
friend class const_iterator
This class represents the liveness of a register, stack slot, etc.
RecyclingAllocator - This class wraps an Allocator, adding the functionality of recycling deleted obj...
PrintReg - Helper class for printing registers on a raw_ostream.
Union of live intervals that are strong candidates for coalescing into a single register (either phys...
void print(raw_ostream &OS, const TargetRegisterInfo *TRI) const
bool isSeenInterference(LiveInterval *VReg) const
NDEBUG.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void unify(LiveInterval &VirtReg, const LiveRange &Range)
void init(LiveIntervalUnion::Allocator &, unsigned Size)
LiveSegments::iterator SegmentIter
void verify(LiveVirtRegBitSet &VisitedVRegs)
unsigned collectInterferingVRegs(unsigned MaxInterferingRegs=UINT_MAX)
void extract(LiveInterval &VirtReg, const LiveRange &Range)
This class implements an extremely fast bulk output stream that can only output to a stream...