41 #define DEBUG_TYPE "nvptx-lower"
53 cl::desc(
"NVPTX Specific: FMA contraction (0: don't do it"
54 " 1: do it 2: do it aggressively"),
86 uint64_t StartingOffset = 0) {
91 for (
unsigned i = 0, e = TempVTs.
size(); i != e; ++i) {
93 uint64_t Off = TempOffsets[i];
289 return "NVPTXISD::CALL";
291 return "NVPTXISD::RET_FLAG";
293 return "NVPTXISD::LOAD_PARAM";
295 return "NVPTXISD::Wrapper";
297 return "NVPTXISD::DeclareParam";
299 return "NVPTXISD::DeclareScalarParam";
301 return "NVPTXISD::DeclareRet";
303 return "NVPTXISD::DeclareScalarRet";
305 return "NVPTXISD::DeclareRetParam";
307 return "NVPTXISD::PrintCall";
309 return "NVPTXISD::PrintCallUni";
311 return "NVPTXISD::LoadParam";
313 return "NVPTXISD::LoadParamV2";
315 return "NVPTXISD::LoadParamV4";
317 return "NVPTXISD::StoreParam";
319 return "NVPTXISD::StoreParamV2";
321 return "NVPTXISD::StoreParamV4";
323 return "NVPTXISD::StoreParamS32";
325 return "NVPTXISD::StoreParamU32";
327 return "NVPTXISD::CallArgBegin";
329 return "NVPTXISD::CallArg";
331 return "NVPTXISD::LastCallArg";
333 return "NVPTXISD::CallArgEnd";
335 return "NVPTXISD::CallVoid";
337 return "NVPTXISD::CallVal";
339 return "NVPTXISD::CallSymbol";
341 return "NVPTXISD::Prototype";
343 return "NVPTXISD::MoveParam";
345 return "NVPTXISD::StoreRetval";
347 return "NVPTXISD::StoreRetvalV2";
349 return "NVPTXISD::StoreRetvalV4";
351 return "NVPTXISD::PseudoUseParam";
353 return "NVPTXISD::RETURN";
355 return "NVPTXISD::CallSeqBegin";
357 return "NVPTXISD::CallSeqEnd";
359 return "NVPTXISD::CallPrototype";
361 return "NVPTXISD::LoadV2";
363 return "NVPTXISD::LoadV4";
365 return "NVPTXISD::LDGV2";
367 return "NVPTXISD::LDGV4";
369 return "NVPTXISD::LDUV2";
371 return "NVPTXISD::LDUV4";
373 return "NVPTXISD::StoreV2";
375 return "NVPTXISD::StoreV4";
377 return "NVPTXISD::FUN_SHFL_CLAMP";
379 return "NVPTXISD::FUN_SHFR_CLAMP";
381 return "NVPTXISD::IMAD";
383 return "NVPTXISD::Dummy";
385 return "NVPTXISD::MUL_WIDE_SIGNED";
387 return "NVPTXISD::MUL_WIDE_UNSIGNED";
391 return "NVPTXISD::Tex1DFloatFloatLevel";
393 return "NVPTXISD::Tex1DFloatFloatGrad";
397 return "NVPTXISD::Tex1DS32FloatLevel";
399 return "NVPTXISD::Tex1DS32FloatGrad";
403 return "NVPTXISD::Tex1DU32FloatLevel";
405 return "NVPTXISD::Tex1DU32FloatGrad";
409 return "NVPTXISD::Tex1DArrayFloatFloatLevel";
411 return "NVPTXISD::Tex1DArrayFloatFloatGrad";
415 return "NVPTXISD::Tex1DArrayS32FloatLevel";
417 return "NVPTXISD::Tex1DArrayS32FloatGrad";
421 return "NVPTXISD::Tex1DArrayU32FloatLevel";
423 return "NVPTXISD::Tex1DArrayU32FloatGrad";
427 return "NVPTXISD::Tex2DFloatFloatLevel";
429 return "NVPTXISD::Tex2DFloatFloatGrad";
433 return "NVPTXISD::Tex2DS32FloatLevel";
435 return "NVPTXISD::Tex2DS32FloatGrad";
439 return "NVPTXISD::Tex2DU32FloatLevel";
441 return "NVPTXISD::Tex2DU32FloatGrad";
445 return "NVPTXISD::Tex2DArrayFloatFloatLevel";
447 return "NVPTXISD::Tex2DArrayFloatFloatGrad";
451 return "NVPTXISD::Tex2DArrayS32FloatLevel";
453 return "NVPTXISD::Tex2DArrayS32FloatGrad";
457 return "NVPTXISD::Tex2DArrayU32FloatLevel";
459 return "NVPTXISD::Tex2DArrayU32FloatGrad";
463 return "NVPTXISD::Tex3DFloatFloatLevel";
465 return "NVPTXISD::Tex3DFloatFloatGrad";
469 return "NVPTXISD::Tex3DS32FloatLevel";
471 return "NVPTXISD::Tex3DS32FloatGrad";
475 return "NVPTXISD::Tex3DU32FloatLevel";
477 return "NVPTXISD::Tex3DU32FloatGrad";
480 return "NVPTXISD::TexCubeFloatFloatLevel";
483 return "NVPTXISD::TexCubeS32FloatLevel";
486 return "NVPTXISD::TexCubeU32FloatLevel";
488 return "NVPTXISD::TexCubeArrayFloatFloat";
490 return "NVPTXISD::TexCubeArrayFloatFloatLevel";
492 return "NVPTXISD::TexCubeArrayS32Float";
494 return "NVPTXISD::TexCubeArrayS32FloatLevel";
496 return "NVPTXISD::TexCubeArrayU32Float";
498 return "NVPTXISD::TexCubeArrayU32FloatLevel";
500 return "NVPTXISD::Tld4R2DFloatFloat";
502 return "NVPTXISD::Tld4G2DFloatFloat";
504 return "NVPTXISD::Tld4B2DFloatFloat";
506 return "NVPTXISD::Tld4A2DFloatFloat";
508 return "NVPTXISD::Tld4R2DS64Float";
510 return "NVPTXISD::Tld4G2DS64Float";
512 return "NVPTXISD::Tld4B2DS64Float";
514 return "NVPTXISD::Tld4A2DS64Float";
516 return "NVPTXISD::Tld4R2DU64Float";
518 return "NVPTXISD::Tld4G2DU64Float";
520 return "NVPTXISD::Tld4B2DU64Float";
522 return "NVPTXISD::Tld4A2DU64Float";
525 return "NVPTXISD::TexUnified1DFloatS32";
527 return "NVPTXISD::TexUnified1DFloatFloat";
529 return "NVPTXISD::TexUnified1DFloatFloatLevel";
531 return "NVPTXISD::TexUnified1DFloatFloatGrad";
533 return "NVPTXISD::TexUnified1DS32S32";
535 return "NVPTXISD::TexUnified1DS32Float";
537 return "NVPTXISD::TexUnified1DS32FloatLevel";
539 return "NVPTXISD::TexUnified1DS32FloatGrad";
541 return "NVPTXISD::TexUnified1DU32S32";
543 return "NVPTXISD::TexUnified1DU32Float";
545 return "NVPTXISD::TexUnified1DU32FloatLevel";
547 return "NVPTXISD::TexUnified1DU32FloatGrad";
549 return "NVPTXISD::TexUnified1DArrayFloatS32";
551 return "NVPTXISD::TexUnified1DArrayFloatFloat";
553 return "NVPTXISD::TexUnified1DArrayFloatFloatLevel";
555 return "NVPTXISD::TexUnified1DArrayFloatFloatGrad";
557 return "NVPTXISD::TexUnified1DArrayS32S32";
559 return "NVPTXISD::TexUnified1DArrayS32Float";
561 return "NVPTXISD::TexUnified1DArrayS32FloatLevel";
563 return "NVPTXISD::TexUnified1DArrayS32FloatGrad";
565 return "NVPTXISD::TexUnified1DArrayU32S32";
567 return "NVPTXISD::TexUnified1DArrayU32Float";
569 return "NVPTXISD::TexUnified1DArrayU32FloatLevel";
571 return "NVPTXISD::TexUnified1DArrayU32FloatGrad";
573 return "NVPTXISD::TexUnified2DFloatS32";
575 return "NVPTXISD::TexUnified2DFloatFloat";
577 return "NVPTXISD::TexUnified2DFloatFloatLevel";
579 return "NVPTXISD::TexUnified2DFloatFloatGrad";
581 return "NVPTXISD::TexUnified2DS32S32";
583 return "NVPTXISD::TexUnified2DS32Float";
585 return "NVPTXISD::TexUnified2DS32FloatLevel";
587 return "NVPTXISD::TexUnified2DS32FloatGrad";
589 return "NVPTXISD::TexUnified2DU32S32";
591 return "NVPTXISD::TexUnified2DU32Float";
593 return "NVPTXISD::TexUnified2DU32FloatLevel";
595 return "NVPTXISD::TexUnified2DU32FloatGrad";
597 return "NVPTXISD::TexUnified2DArrayFloatS32";
599 return "NVPTXISD::TexUnified2DArrayFloatFloat";
601 return "NVPTXISD::TexUnified2DArrayFloatFloatLevel";
603 return "NVPTXISD::TexUnified2DArrayFloatFloatGrad";
605 return "NVPTXISD::TexUnified2DArrayS32S32";
607 return "NVPTXISD::TexUnified2DArrayS32Float";
609 return "NVPTXISD::TexUnified2DArrayS32FloatLevel";
611 return "NVPTXISD::TexUnified2DArrayS32FloatGrad";
613 return "NVPTXISD::TexUnified2DArrayU32S32";
615 return "NVPTXISD::TexUnified2DArrayU32Float";
617 return "NVPTXISD::TexUnified2DArrayU32FloatLevel";
619 return "NVPTXISD::TexUnified2DArrayU32FloatGrad";
621 return "NVPTXISD::TexUnified3DFloatS32";
623 return "NVPTXISD::TexUnified3DFloatFloat";
625 return "NVPTXISD::TexUnified3DFloatFloatLevel";
627 return "NVPTXISD::TexUnified3DFloatFloatGrad";
629 return "NVPTXISD::TexUnified3DS32S32";
631 return "NVPTXISD::TexUnified3DS32Float";
633 return "NVPTXISD::TexUnified3DS32FloatLevel";
635 return "NVPTXISD::TexUnified3DS32FloatGrad";
637 return "NVPTXISD::TexUnified3DU32S32";
639 return "NVPTXISD::TexUnified3DU32Float";
641 return "NVPTXISD::TexUnified3DU32FloatLevel";
643 return "NVPTXISD::TexUnified3DU32FloatGrad";
645 return "NVPTXISD::TexUnifiedCubeFloatFloat";
647 return "NVPTXISD::TexUnifiedCubeFloatFloatLevel";
649 return "NVPTXISD::TexUnifiedCubeS32Float";
651 return "NVPTXISD::TexUnifiedCubeS32FloatLevel";
653 return "NVPTXISD::TexUnifiedCubeU32Float";
655 return "NVPTXISD::TexUnifiedCubeU32FloatLevel";
657 return "NVPTXISD::TexUnifiedCubeArrayFloatFloat";
659 return "NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel";
661 return "NVPTXISD::TexUnifiedCubeArrayS32Float";
663 return "NVPTXISD::TexUnifiedCubeArrayS32FloatLevel";
665 return "NVPTXISD::TexUnifiedCubeArrayU32Float";
667 return "NVPTXISD::TexUnifiedCubeArrayU32FloatLevel";
669 return "NVPTXISD::Tld4UnifiedR2DFloatFloat";
671 return "NVPTXISD::Tld4UnifiedG2DFloatFloat";
673 return "NVPTXISD::Tld4UnifiedB2DFloatFloat";
675 return "NVPTXISD::Tld4UnifiedA2DFloatFloat";
677 return "NVPTXISD::Tld4UnifiedR2DS64Float";
679 return "NVPTXISD::Tld4UnifiedG2DS64Float";
681 return "NVPTXISD::Tld4UnifiedB2DS64Float";
683 return "NVPTXISD::Tld4UnifiedA2DS64Float";
685 return "NVPTXISD::Tld4UnifiedR2DU64Float";
687 return "NVPTXISD::Tld4UnifiedG2DU64Float";
689 return "NVPTXISD::Tld4UnifiedB2DU64Float";
691 return "NVPTXISD::Tld4UnifiedA2DU64Float";
887 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
900 assert(isABI &&
"Non-ABI compilation is not supported");
913 if (
const IntegerType *ITy = dyn_cast<IntegerType>(retTy)) {
914 size = ITy->getBitWidth();
919 "Floating point type expected here");
923 O <<
".param .b" << size <<
" _";
924 }
else if (isa<PointerType>(retTy)) {
925 O <<
".param .b" << PtrVT.getSizeInBits() <<
" _";
927 isa<VectorType>(retTy)) {
929 O <<
".param .align " << retAlignment <<
" .b8 _["
941 for (
unsigned i = 0, e = Args.size(); i != e; ++i, ++OIdx) {
942 Type *Ty = Args[i].Ty;
948 if (!Outs[OIdx].
Flags.isByVal()) {
956 O <<
".param .align " << align <<
" .b8 ";
958 O <<
"[" << sz <<
"]";
962 if (
unsigned len = vtparts.
size())
969 "type mismatch between callee prototype and arguments");
972 if (isa<IntegerType>(Ty)) {
976 }
else if (isa<PointerType>(Ty))
977 sz = PtrVT.getSizeInBits();
980 O <<
".param .b" << sz <<
" ";
985 assert(PTy &&
"Param with byval attribute should be a pointer type");
988 unsigned align = Outs[OIdx].Flags.getByValAlign();
990 O <<
".param .align " << align <<
" .b8 ";
992 O <<
"[" << sz <<
"]";
999 NVPTXTargetLowering::getArgumentAlignment(
SDValue Callee,
1002 unsigned Idx)
const {
1006 if (!DirectCallee) {
1010 assert(CalleeI &&
"Call target is not a function or derived value?");
1013 if (isa<CallInst>(CalleeI)) {
1018 const Value *CalleeV = cast<CallInst>(CalleeI)->getCalledValue();
1020 while(isa<ConstantExpr>(CalleeV)) {
1025 CalleeV = cast<ConstantExpr>(CalleeV)->getOperand(0);
1030 if (isa<Function>(CalleeV))
1031 DirectCallee = CalleeV;
1044 return DL.getABITypeAlignment(Ty);
1062 assert(isABI &&
"Non-ABI compilation is not supported");
1075 unsigned paramCount = 0;
1088 for (
unsigned i = 0, e = Args.size(); i != e; ++i, ++OIdx) {
1089 EVT VT = Outs[OIdx].VT;
1090 Type *Ty = Args[i].Ty;
1092 if (!Outs[OIdx].
Flags.isByVal()) {
1100 unsigned align = getArgumentAlignment(Callee, CS, Ty, paramCount + 1);
1102 unsigned sz =
DL.getTypeAllocSize(Ty);
1112 for (
unsigned j = 0, je = vtparts.size(); j != je; ++j) {
1113 EVT elemtype = vtparts[j];
1117 SDValue StVal = OutVals[OIdx];
1122 SDValue CopyParamOps[] = { Chain,
1127 CopyParamVTs, CopyParamOps,
1133 if (vtparts.size() > 0)
1140 unsigned align = getArgumentAlignment(Callee, CS, Ty, paramCount + 1);
1142 unsigned sz =
DL.getTypeAllocSize(Ty);
1144 SDValue DeclareParamOps[] = { Chain,
1155 bool NeedExtend =
false;
1163 SDValue Elt = OutVals[OIdx++];
1168 SDValue CopyParamOps[] = { Chain,
1173 CopyParamVTs, CopyParamOps,
1176 }
else if (NumElts == 2) {
1177 SDValue Elt0 = OutVals[OIdx++];
1178 SDValue Elt1 = OutVals[OIdx++];
1185 SDValue CopyParamOps[] = { Chain,
1190 CopyParamVTs, CopyParamOps,
1194 unsigned curOffset = 0;
1205 unsigned VecSize = 4;
1213 for (
unsigned i = 0; i < NumElts; i += VecSize) {
1223 StoreVal = OutVals[OIdx++];
1228 if (i + 1 < NumElts) {
1229 StoreVal = OutVals[OIdx++];
1240 if (i + 2 < NumElts) {
1241 StoreVal = OutVals[OIdx++];
1250 if (i + 3 < NumElts) {
1251 StoreVal = OutVals[OIdx++];
1267 curOffset += PerStoreOffset;
1277 bool needExtend =
false;
1285 SDValue DeclareParamOps[] = { Chain,
1296 if (Outs[OIdx].
Flags.isSExt())
1301 SDValue CopyParamOps[] = { Chain,
1307 if (Outs[OIdx].
Flags.isZExt())
1309 else if (Outs[OIdx].
Flags.isSExt())
1322 assert(PTy &&
"Type of a byval parameter should be pointer");
1327 unsigned sz = Outs[OIdx].Flags.getByValSize();
1329 unsigned ArgAlign = Outs[OIdx].Flags.getByValAlign();
1341 for (
unsigned j = 0, je = vtparts.
size(); j != je; ++j) {
1342 EVT elemtype = vtparts[j];
1343 int curOffset = Offsets[j];
1355 SDValue CopyParamOps[] = { Chain,
1360 CopyParamOps, elemtype,
1369 unsigned retAlignment = 0;
1372 if (Ins.
size() > 0) {
1379 unsigned resultsz =
DL.getTypeAllocSizeInBits(retTy);
1397 retAlignment = getArgumentAlignment(Callee, CS, retTy, 0);
1399 SDValue DeclareRetOps[] = { Chain,
1420 const char *ProtoStr =
1434 dl, PrintCallVTs, PrintCallOps);
1439 SDValue CallVoidOps[] = { Chain, Callee, InFlag };
1445 SDValue CallArgBeginOps[] = { Chain, InFlag };
1450 for (
unsigned i = 0, e = paramCount; i != e; ++i) {
1459 Chain = DAG.
getNode(opcode, dl, CallArgVTs, CallArgOps);
1463 SDValue CallArgEndOps[] = { Chain,
1471 SDValue PrototypeOps[] = { Chain,
1479 if (Ins.
size() > 0) {
1485 ObjectVT) == NumElts &&
1486 "Vector was not scalarized");
1488 bool needTruncate = sz < 8;
1514 }
else if (NumElts == 2) {
1551 unsigned VecSize = 4;
1558 for (
unsigned i = 0; i < NumElts; i += VecSize) {
1565 for (
unsigned j = 0; j < VecSize; ++j)
1568 for (
unsigned j = 0; j < VecSize; ++j)
1586 for (
unsigned j = 0; j < VecSize; ++j) {
1587 if (i + j >= NumElts)
1601 assert(VTs.size() == Ins.
size() &&
"Bad value decomposition");
1602 unsigned RetAlign = getArgumentAlignment(Callee, CS, retTy, 0);
1603 for (
unsigned i = 0, e = Ins.
size(); i != e; ++i) {
1604 unsigned sz = VTs[i].getSizeInBits();
1606 bool needTruncate = sz < 8;
1607 if (VTs[i].isInteger() && (sz < 8))
1611 EVT TheLoadType = VTs[i];
1612 if (retTy->
isIntegerTy() &&
DL.getTypeAllocSizeInBits(retTy) < 32) {
1617 }
else if (sz < 16) {
1666 for (
unsigned i = 0; i < NumOperands; ++i) {
1671 for (
unsigned j = 0; j < NumSubElem; ++j) {
1753 unsigned VTBits = VT.getSizeInBits();
1819 return LowerCONCAT_VECTORS(Op, DAG);
1821 return LowerSTORE(Op, DAG);
1823 return LowerLOAD(Op, DAG);
1825 return LowerShiftLeftParts(Op, DAG);
1828 return LowerShiftRightParts(Op, DAG);
1830 return LowerSelect(Op, DAG);
1854 return LowerLOADi1(Op, DAG);
1869 "Custom lowering for i1 load only");
1885 return LowerSTOREi1(Op, DAG);
1887 return LowerSTOREVector(Op, DAG);
1926 unsigned PrefAlign =
1928 if (Align < PrefAlign) {
1937 unsigned Opcode = 0;
1944 bool NeedExt =
false;
1966 for (
unsigned i = 0; i < NumElts; ++i) {
2011 int idx,
EVT v)
const {
2013 std::stringstream suffix;
2015 *name += suffix.str();
2020 NVPTXTargetLowering::getParamSymbol(
SelectionDAG &DAG,
int idx,
EVT v)
const {
2021 std::string ParamSym;
2027 std::string *SavedStr =
2033 return getExtSymb(DAG,
".HLPPARAM", idx);
2039 static const char *
const specialTypes[] = {
"struct._image2d_t",
2040 "struct._image3d_t",
2041 "struct._sampler_t" };
2053 const std::string TypeName = STy && !STy->
isLiteral() ? STy->
getName() :
"";
2056 if (TypeName == specialTypes[i])
2075 std::vector<SDValue> OutChains;
2079 assert(isABI &&
"Non-ABI compilation is not supported");
2083 std::vector<Type *> argTypes;
2084 std::vector<const Argument *> theArgs;
2087 theArgs.push_back(
I);
2088 argTypes.push_back(
I->getType());
2099 unsigned InsIdx = 0;
2102 for (
unsigned i = 0, e = theArgs.size(); i != e; ++i, ++idx, ++InsIdx) {
2103 Type *Ty = argTypes[i];
2112 assert(isKernel &&
"Only kernels can have image/sampler params");
2117 if (theArgs[i]->use_empty()) {
2123 assert(vtparts.
size() > 0 &&
"empty aggregate type not expected");
2124 for (
unsigned parti = 0, parte = vtparts.
size(); parti != parte;
2129 if (vtparts.
size() > 0)
2136 for (
unsigned parti = 0; parti < NumRegs; ++parti) {
2162 assert(vtparts.size() > 0 &&
"empty aggregate type not expected");
2163 bool aggregateIsPacked =
false;
2164 if (
StructType *STy = llvm::dyn_cast<StructType>(Ty))
2165 aggregateIsPacked = STy->isPacked();
2167 SDValue Arg = getParamSymbol(DAG, idx, PtrVT);
2168 for (
unsigned parti = 0, parte = vtparts.size(); parti != parte;
2170 EVT partVT = vtparts[parti];
2177 unsigned partAlign = aggregateIsPacked
2182 if (Ins[InsIdx].VT.getSizeInBits() > partVT.
getSizeInBits()) {
2185 p = DAG.
getExtLoad(ExtOp, dl, Ins[InsIdx].VT, Root, srcAddr,
2187 false,
false, partAlign);
2189 p = DAG.
getLoad(partVT, dl, Root, srcAddr,
2198 if (vtparts.size() > 0)
2204 SDValue Arg = getParamSymbol(DAG, idx, PtrVT);
2207 "Vector was not scalarized");
2227 }
else if (NumElts == 2) {
2245 if (Ins[InsIdx].VT.getSizeInBits() > EltVT.
getSizeInBits()) {
2264 unsigned VecSize = 4;
2270 for (
unsigned i = 0; i < NumElts; i += VecSize) {
2283 for (
unsigned j = 0; j < VecSize; ++j) {
2284 if (i + j >= NumElts)
2304 SDValue Arg = getParamSymbol(DAG, idx, PtrVT);
2308 if (ObjectVT.
getSizeInBits() < Ins[InsIdx].VT.getSizeInBits()) {
2313 ObjectVT,
false,
false,
false,
2335 assert(ObjectVT == Ins[InsIdx].VT &&
2336 "Ins type did not match function type");
2337 SDValue Arg = getParamSymbol(DAG, idx, PtrVT);
2359 if (!OutChains.empty())
2378 assert(isABI &&
"Non-ABI compilation is not supported");
2382 if (
VectorType *VTy = dyn_cast<VectorType>(RetTy)) {
2385 unsigned NumElts = VTy->getNumElements();
2386 assert(NumElts == Outs.
size() &&
"Bad scalarization of return value");
2390 bool NeedExtend =
false;
2391 if (EltVT.getSizeInBits() < 16)
2396 SDValue StoreVal = OutVals[0];
2405 }
else if (NumElts == 2) {
2407 SDValue StoreVal0 = OutVals[0];
2408 SDValue StoreVal1 = OutVals[1];
2431 unsigned VecSize = 4;
2435 unsigned Offset = 0;
2439 unsigned PerStoreOffset =
2442 for (
unsigned i = 0; i < NumElts; i += VecSize) {
2451 StoreVal = OutVals[i];
2456 if (i + 1 < NumElts) {
2457 StoreVal = OutVals[i + 1];
2461 StoreVal = DAG.
getUNDEF(ExtendedVT);
2467 if (i + 2 < NumElts) {
2468 StoreVal = OutVals[i + 2];
2473 StoreVal = DAG.
getUNDEF(ExtendedVT);
2477 if (i + 3 < NumElts) {
2478 StoreVal = OutVals[i + 3];
2483 StoreVal = DAG.
getUNDEF(ExtendedVT);
2492 Offset += PerStoreOffset;
2499 assert(ValVTs.size() == OutVals.
size() &&
"Bad return value decomposition");
2501 for (
unsigned i = 0, e = Outs.
size(); i != e; ++i) {
2504 unsigned numElems = 1;
2507 for (
unsigned j = 0, je = numElems; j != je; ++j) {
2513 EVT TheStoreType = ValVTs[i];
2540 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
2542 if (Constraint.length() > 1)
2563 switch (Intrinsic) {
2567 case Intrinsic::nvvm_tex_1d_v4f32_s32:
2569 case Intrinsic::nvvm_tex_1d_v4f32_f32:
2571 case Intrinsic::nvvm_tex_1d_level_v4f32_f32:
2573 case Intrinsic::nvvm_tex_1d_grad_v4f32_f32:
2575 case Intrinsic::nvvm_tex_1d_v4s32_s32:
2577 case Intrinsic::nvvm_tex_1d_v4s32_f32:
2579 case Intrinsic::nvvm_tex_1d_level_v4s32_f32:
2581 case Intrinsic::nvvm_tex_1d_grad_v4s32_f32:
2583 case Intrinsic::nvvm_tex_1d_v4u32_s32:
2585 case Intrinsic::nvvm_tex_1d_v4u32_f32:
2587 case Intrinsic::nvvm_tex_1d_level_v4u32_f32:
2589 case Intrinsic::nvvm_tex_1d_grad_v4u32_f32:
2592 case Intrinsic::nvvm_tex_1d_array_v4f32_s32:
2594 case Intrinsic::nvvm_tex_1d_array_v4f32_f32:
2596 case Intrinsic::nvvm_tex_1d_array_level_v4f32_f32:
2598 case Intrinsic::nvvm_tex_1d_array_grad_v4f32_f32:
2600 case Intrinsic::nvvm_tex_1d_array_v4s32_s32:
2602 case Intrinsic::nvvm_tex_1d_array_v4s32_f32:
2604 case Intrinsic::nvvm_tex_1d_array_level_v4s32_f32:
2606 case Intrinsic::nvvm_tex_1d_array_grad_v4s32_f32:
2608 case Intrinsic::nvvm_tex_1d_array_v4u32_s32:
2610 case Intrinsic::nvvm_tex_1d_array_v4u32_f32:
2612 case Intrinsic::nvvm_tex_1d_array_level_v4u32_f32:
2614 case Intrinsic::nvvm_tex_1d_array_grad_v4u32_f32:
2617 case Intrinsic::nvvm_tex_2d_v4f32_s32:
2619 case Intrinsic::nvvm_tex_2d_v4f32_f32:
2621 case Intrinsic::nvvm_tex_2d_level_v4f32_f32:
2623 case Intrinsic::nvvm_tex_2d_grad_v4f32_f32:
2625 case Intrinsic::nvvm_tex_2d_v4s32_s32:
2627 case Intrinsic::nvvm_tex_2d_v4s32_f32:
2629 case Intrinsic::nvvm_tex_2d_level_v4s32_f32:
2631 case Intrinsic::nvvm_tex_2d_grad_v4s32_f32:
2633 case Intrinsic::nvvm_tex_2d_v4u32_s32:
2635 case Intrinsic::nvvm_tex_2d_v4u32_f32:
2637 case Intrinsic::nvvm_tex_2d_level_v4u32_f32:
2639 case Intrinsic::nvvm_tex_2d_grad_v4u32_f32:
2642 case Intrinsic::nvvm_tex_2d_array_v4f32_s32:
2644 case Intrinsic::nvvm_tex_2d_array_v4f32_f32:
2646 case Intrinsic::nvvm_tex_2d_array_level_v4f32_f32:
2648 case Intrinsic::nvvm_tex_2d_array_grad_v4f32_f32:
2650 case Intrinsic::nvvm_tex_2d_array_v4s32_s32:
2652 case Intrinsic::nvvm_tex_2d_array_v4s32_f32:
2654 case Intrinsic::nvvm_tex_2d_array_level_v4s32_f32:
2656 case Intrinsic::nvvm_tex_2d_array_grad_v4s32_f32:
2658 case Intrinsic::nvvm_tex_2d_array_v4u32_s32:
2660 case Intrinsic::nvvm_tex_2d_array_v4u32_f32:
2662 case Intrinsic::nvvm_tex_2d_array_level_v4u32_f32:
2664 case Intrinsic::nvvm_tex_2d_array_grad_v4u32_f32:
2667 case Intrinsic::nvvm_tex_3d_v4f32_s32:
2669 case Intrinsic::nvvm_tex_3d_v4f32_f32:
2671 case Intrinsic::nvvm_tex_3d_level_v4f32_f32:
2673 case Intrinsic::nvvm_tex_3d_grad_v4f32_f32:
2675 case Intrinsic::nvvm_tex_3d_v4s32_s32:
2677 case Intrinsic::nvvm_tex_3d_v4s32_f32:
2679 case Intrinsic::nvvm_tex_3d_level_v4s32_f32:
2681 case Intrinsic::nvvm_tex_3d_grad_v4s32_f32:
2683 case Intrinsic::nvvm_tex_3d_v4u32_s32:
2685 case Intrinsic::nvvm_tex_3d_v4u32_f32:
2687 case Intrinsic::nvvm_tex_3d_level_v4u32_f32:
2689 case Intrinsic::nvvm_tex_3d_grad_v4u32_f32:
2692 case Intrinsic::nvvm_tex_cube_v4f32_f32:
2694 case Intrinsic::nvvm_tex_cube_level_v4f32_f32:
2696 case Intrinsic::nvvm_tex_cube_v4s32_f32:
2698 case Intrinsic::nvvm_tex_cube_level_v4s32_f32:
2700 case Intrinsic::nvvm_tex_cube_v4u32_f32:
2702 case Intrinsic::nvvm_tex_cube_level_v4u32_f32:
2705 case Intrinsic::nvvm_tex_cube_array_v4f32_f32:
2707 case Intrinsic::nvvm_tex_cube_array_level_v4f32_f32:
2709 case Intrinsic::nvvm_tex_cube_array_v4s32_f32:
2711 case Intrinsic::nvvm_tex_cube_array_level_v4s32_f32:
2713 case Intrinsic::nvvm_tex_cube_array_v4u32_f32:
2715 case Intrinsic::nvvm_tex_cube_array_level_v4u32_f32:
2718 case Intrinsic::nvvm_tld4_r_2d_v4f32_f32:
2720 case Intrinsic::nvvm_tld4_g_2d_v4f32_f32:
2722 case Intrinsic::nvvm_tld4_b_2d_v4f32_f32:
2724 case Intrinsic::nvvm_tld4_a_2d_v4f32_f32:
2726 case Intrinsic::nvvm_tld4_r_2d_v4s32_f32:
2728 case Intrinsic::nvvm_tld4_g_2d_v4s32_f32:
2730 case Intrinsic::nvvm_tld4_b_2d_v4s32_f32:
2732 case Intrinsic::nvvm_tld4_a_2d_v4s32_f32:
2734 case Intrinsic::nvvm_tld4_r_2d_v4u32_f32:
2736 case Intrinsic::nvvm_tld4_g_2d_v4u32_f32:
2738 case Intrinsic::nvvm_tld4_b_2d_v4u32_f32:
2740 case Intrinsic::nvvm_tld4_a_2d_v4u32_f32:
2743 case Intrinsic::nvvm_tex_unified_1d_v4f32_s32:
2745 case Intrinsic::nvvm_tex_unified_1d_v4f32_f32:
2747 case Intrinsic::nvvm_tex_unified_1d_level_v4f32_f32:
2749 case Intrinsic::nvvm_tex_unified_1d_grad_v4f32_f32:
2751 case Intrinsic::nvvm_tex_unified_1d_v4s32_s32:
2753 case Intrinsic::nvvm_tex_unified_1d_v4s32_f32:
2755 case Intrinsic::nvvm_tex_unified_1d_level_v4s32_f32:
2757 case Intrinsic::nvvm_tex_unified_1d_grad_v4s32_f32:
2759 case Intrinsic::nvvm_tex_unified_1d_v4u32_s32:
2761 case Intrinsic::nvvm_tex_unified_1d_v4u32_f32:
2763 case Intrinsic::nvvm_tex_unified_1d_level_v4u32_f32:
2765 case Intrinsic::nvvm_tex_unified_1d_grad_v4u32_f32:
2768 case Intrinsic::nvvm_tex_unified_1d_array_v4f32_s32:
2770 case Intrinsic::nvvm_tex_unified_1d_array_v4f32_f32:
2772 case Intrinsic::nvvm_tex_unified_1d_array_level_v4f32_f32:
2774 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4f32_f32:
2776 case Intrinsic::nvvm_tex_unified_1d_array_v4s32_s32:
2778 case Intrinsic::nvvm_tex_unified_1d_array_v4s32_f32:
2780 case Intrinsic::nvvm_tex_unified_1d_array_level_v4s32_f32:
2782 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4s32_f32:
2784 case Intrinsic::nvvm_tex_unified_1d_array_v4u32_s32:
2786 case Intrinsic::nvvm_tex_unified_1d_array_v4u32_f32:
2788 case Intrinsic::nvvm_tex_unified_1d_array_level_v4u32_f32:
2790 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4u32_f32:
2793 case Intrinsic::nvvm_tex_unified_2d_v4f32_s32:
2795 case Intrinsic::nvvm_tex_unified_2d_v4f32_f32:
2797 case Intrinsic::nvvm_tex_unified_2d_level_v4f32_f32:
2799 case Intrinsic::nvvm_tex_unified_2d_grad_v4f32_f32:
2801 case Intrinsic::nvvm_tex_unified_2d_v4s32_s32:
2803 case Intrinsic::nvvm_tex_unified_2d_v4s32_f32:
2805 case Intrinsic::nvvm_tex_unified_2d_level_v4s32_f32:
2807 case Intrinsic::nvvm_tex_unified_2d_grad_v4s32_f32:
2809 case Intrinsic::nvvm_tex_unified_2d_v4u32_s32:
2811 case Intrinsic::nvvm_tex_unified_2d_v4u32_f32:
2813 case Intrinsic::nvvm_tex_unified_2d_level_v4u32_f32:
2815 case Intrinsic::nvvm_tex_unified_2d_grad_v4u32_f32:
2818 case Intrinsic::nvvm_tex_unified_2d_array_v4f32_s32:
2820 case Intrinsic::nvvm_tex_unified_2d_array_v4f32_f32:
2822 case Intrinsic::nvvm_tex_unified_2d_array_level_v4f32_f32:
2824 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4f32_f32:
2826 case Intrinsic::nvvm_tex_unified_2d_array_v4s32_s32:
2828 case Intrinsic::nvvm_tex_unified_2d_array_v4s32_f32:
2830 case Intrinsic::nvvm_tex_unified_2d_array_level_v4s32_f32:
2832 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4s32_f32:
2834 case Intrinsic::nvvm_tex_unified_2d_array_v4u32_s32:
2836 case Intrinsic::nvvm_tex_unified_2d_array_v4u32_f32:
2838 case Intrinsic::nvvm_tex_unified_2d_array_level_v4u32_f32:
2840 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4u32_f32:
2843 case Intrinsic::nvvm_tex_unified_3d_v4f32_s32:
2845 case Intrinsic::nvvm_tex_unified_3d_v4f32_f32:
2847 case Intrinsic::nvvm_tex_unified_3d_level_v4f32_f32:
2849 case Intrinsic::nvvm_tex_unified_3d_grad_v4f32_f32:
2851 case Intrinsic::nvvm_tex_unified_3d_v4s32_s32:
2853 case Intrinsic::nvvm_tex_unified_3d_v4s32_f32:
2855 case Intrinsic::nvvm_tex_unified_3d_level_v4s32_f32:
2857 case Intrinsic::nvvm_tex_unified_3d_grad_v4s32_f32:
2859 case Intrinsic::nvvm_tex_unified_3d_v4u32_s32:
2861 case Intrinsic::nvvm_tex_unified_3d_v4u32_f32:
2863 case Intrinsic::nvvm_tex_unified_3d_level_v4u32_f32:
2865 case Intrinsic::nvvm_tex_unified_3d_grad_v4u32_f32:
2868 case Intrinsic::nvvm_tex_unified_cube_v4f32_f32:
2870 case Intrinsic::nvvm_tex_unified_cube_level_v4f32_f32:
2872 case Intrinsic::nvvm_tex_unified_cube_v4s32_f32:
2874 case Intrinsic::nvvm_tex_unified_cube_level_v4s32_f32:
2876 case Intrinsic::nvvm_tex_unified_cube_v4u32_f32:
2878 case Intrinsic::nvvm_tex_unified_cube_level_v4u32_f32:
2881 case Intrinsic::nvvm_tex_unified_cube_array_v4f32_f32:
2883 case Intrinsic::nvvm_tex_unified_cube_array_level_v4f32_f32:
2885 case Intrinsic::nvvm_tex_unified_cube_array_v4s32_f32:
2887 case Intrinsic::nvvm_tex_unified_cube_array_level_v4s32_f32:
2889 case Intrinsic::nvvm_tex_unified_cube_array_v4u32_f32:
2891 case Intrinsic::nvvm_tex_unified_cube_array_level_v4u32_f32:
2894 case Intrinsic::nvvm_tld4_unified_r_2d_v4f32_f32:
2896 case Intrinsic::nvvm_tld4_unified_g_2d_v4f32_f32:
2898 case Intrinsic::nvvm_tld4_unified_b_2d_v4f32_f32:
2900 case Intrinsic::nvvm_tld4_unified_a_2d_v4f32_f32:
2902 case Intrinsic::nvvm_tld4_unified_r_2d_v4s32_f32:
2904 case Intrinsic::nvvm_tld4_unified_g_2d_v4s32_f32:
2906 case Intrinsic::nvvm_tld4_unified_b_2d_v4s32_f32:
2908 case Intrinsic::nvvm_tld4_unified_a_2d_v4s32_f32:
2910 case Intrinsic::nvvm_tld4_unified_r_2d_v4u32_f32:
2912 case Intrinsic::nvvm_tld4_unified_g_2d_v4u32_f32:
2914 case Intrinsic::nvvm_tld4_unified_b_2d_v4u32_f32:
2916 case Intrinsic::nvvm_tld4_unified_a_2d_v4u32_f32:
2922 switch (Intrinsic) {
2925 case Intrinsic::nvvm_suld_1d_i8_clamp:
2927 case Intrinsic::nvvm_suld_1d_i16_clamp:
2929 case Intrinsic::nvvm_suld_1d_i32_clamp:
2931 case Intrinsic::nvvm_suld_1d_i64_clamp:
2933 case Intrinsic::nvvm_suld_1d_v2i8_clamp:
2935 case Intrinsic::nvvm_suld_1d_v2i16_clamp:
2937 case Intrinsic::nvvm_suld_1d_v2i32_clamp:
2939 case Intrinsic::nvvm_suld_1d_v2i64_clamp:
2941 case Intrinsic::nvvm_suld_1d_v4i8_clamp:
2943 case Intrinsic::nvvm_suld_1d_v4i16_clamp:
2945 case Intrinsic::nvvm_suld_1d_v4i32_clamp:
2947 case Intrinsic::nvvm_suld_1d_array_i8_clamp:
2949 case Intrinsic::nvvm_suld_1d_array_i16_clamp:
2951 case Intrinsic::nvvm_suld_1d_array_i32_clamp:
2953 case Intrinsic::nvvm_suld_1d_array_i64_clamp:
2955 case Intrinsic::nvvm_suld_1d_array_v2i8_clamp:
2957 case Intrinsic::nvvm_suld_1d_array_v2i16_clamp:
2959 case Intrinsic::nvvm_suld_1d_array_v2i32_clamp:
2961 case Intrinsic::nvvm_suld_1d_array_v2i64_clamp:
2963 case Intrinsic::nvvm_suld_1d_array_v4i8_clamp:
2965 case Intrinsic::nvvm_suld_1d_array_v4i16_clamp:
2967 case Intrinsic::nvvm_suld_1d_array_v4i32_clamp:
2969 case Intrinsic::nvvm_suld_2d_i8_clamp:
2971 case Intrinsic::nvvm_suld_2d_i16_clamp:
2973 case Intrinsic::nvvm_suld_2d_i32_clamp:
2975 case Intrinsic::nvvm_suld_2d_i64_clamp:
2977 case Intrinsic::nvvm_suld_2d_v2i8_clamp:
2979 case Intrinsic::nvvm_suld_2d_v2i16_clamp:
2981 case Intrinsic::nvvm_suld_2d_v2i32_clamp:
2983 case Intrinsic::nvvm_suld_2d_v2i64_clamp:
2985 case Intrinsic::nvvm_suld_2d_v4i8_clamp:
2987 case Intrinsic::nvvm_suld_2d_v4i16_clamp:
2989 case Intrinsic::nvvm_suld_2d_v4i32_clamp:
2991 case Intrinsic::nvvm_suld_2d_array_i8_clamp:
2993 case Intrinsic::nvvm_suld_2d_array_i16_clamp:
2995 case Intrinsic::nvvm_suld_2d_array_i32_clamp:
2997 case Intrinsic::nvvm_suld_2d_array_i64_clamp:
2999 case Intrinsic::nvvm_suld_2d_array_v2i8_clamp:
3001 case Intrinsic::nvvm_suld_2d_array_v2i16_clamp:
3003 case Intrinsic::nvvm_suld_2d_array_v2i32_clamp:
3005 case Intrinsic::nvvm_suld_2d_array_v2i64_clamp:
3007 case Intrinsic::nvvm_suld_2d_array_v4i8_clamp:
3009 case Intrinsic::nvvm_suld_2d_array_v4i16_clamp:
3011 case Intrinsic::nvvm_suld_2d_array_v4i32_clamp:
3013 case Intrinsic::nvvm_suld_3d_i8_clamp:
3015 case Intrinsic::nvvm_suld_3d_i16_clamp:
3017 case Intrinsic::nvvm_suld_3d_i32_clamp:
3019 case Intrinsic::nvvm_suld_3d_i64_clamp:
3021 case Intrinsic::nvvm_suld_3d_v2i8_clamp:
3023 case Intrinsic::nvvm_suld_3d_v2i16_clamp:
3025 case Intrinsic::nvvm_suld_3d_v2i32_clamp:
3027 case Intrinsic::nvvm_suld_3d_v2i64_clamp:
3029 case Intrinsic::nvvm_suld_3d_v4i8_clamp:
3031 case Intrinsic::nvvm_suld_3d_v4i16_clamp:
3033 case Intrinsic::nvvm_suld_3d_v4i32_clamp:
3035 case Intrinsic::nvvm_suld_1d_i8_trap:
3037 case Intrinsic::nvvm_suld_1d_i16_trap:
3039 case Intrinsic::nvvm_suld_1d_i32_trap:
3041 case Intrinsic::nvvm_suld_1d_i64_trap:
3043 case Intrinsic::nvvm_suld_1d_v2i8_trap:
3045 case Intrinsic::nvvm_suld_1d_v2i16_trap:
3047 case Intrinsic::nvvm_suld_1d_v2i32_trap:
3049 case Intrinsic::nvvm_suld_1d_v2i64_trap:
3051 case Intrinsic::nvvm_suld_1d_v4i8_trap:
3053 case Intrinsic::nvvm_suld_1d_v4i16_trap:
3055 case Intrinsic::nvvm_suld_1d_v4i32_trap:
3057 case Intrinsic::nvvm_suld_1d_array_i8_trap:
3059 case Intrinsic::nvvm_suld_1d_array_i16_trap:
3061 case Intrinsic::nvvm_suld_1d_array_i32_trap:
3063 case Intrinsic::nvvm_suld_1d_array_i64_trap:
3065 case Intrinsic::nvvm_suld_1d_array_v2i8_trap:
3067 case Intrinsic::nvvm_suld_1d_array_v2i16_trap:
3069 case Intrinsic::nvvm_suld_1d_array_v2i32_trap:
3071 case Intrinsic::nvvm_suld_1d_array_v2i64_trap:
3073 case Intrinsic::nvvm_suld_1d_array_v4i8_trap:
3075 case Intrinsic::nvvm_suld_1d_array_v4i16_trap:
3077 case Intrinsic::nvvm_suld_1d_array_v4i32_trap:
3079 case Intrinsic::nvvm_suld_2d_i8_trap:
3081 case Intrinsic::nvvm_suld_2d_i16_trap:
3083 case Intrinsic::nvvm_suld_2d_i32_trap:
3085 case Intrinsic::nvvm_suld_2d_i64_trap:
3087 case Intrinsic::nvvm_suld_2d_v2i8_trap:
3089 case Intrinsic::nvvm_suld_2d_v2i16_trap:
3091 case Intrinsic::nvvm_suld_2d_v2i32_trap:
3093 case Intrinsic::nvvm_suld_2d_v2i64_trap:
3095 case Intrinsic::nvvm_suld_2d_v4i8_trap:
3097 case Intrinsic::nvvm_suld_2d_v4i16_trap:
3099 case Intrinsic::nvvm_suld_2d_v4i32_trap:
3101 case Intrinsic::nvvm_suld_2d_array_i8_trap:
3103 case Intrinsic::nvvm_suld_2d_array_i16_trap:
3105 case Intrinsic::nvvm_suld_2d_array_i32_trap:
3107 case Intrinsic::nvvm_suld_2d_array_i64_trap:
3109 case Intrinsic::nvvm_suld_2d_array_v2i8_trap:
3111 case Intrinsic::nvvm_suld_2d_array_v2i16_trap:
3113 case Intrinsic::nvvm_suld_2d_array_v2i32_trap:
3115 case Intrinsic::nvvm_suld_2d_array_v2i64_trap:
3117 case Intrinsic::nvvm_suld_2d_array_v4i8_trap:
3119 case Intrinsic::nvvm_suld_2d_array_v4i16_trap:
3121 case Intrinsic::nvvm_suld_2d_array_v4i32_trap:
3123 case Intrinsic::nvvm_suld_3d_i8_trap:
3125 case Intrinsic::nvvm_suld_3d_i16_trap:
3127 case Intrinsic::nvvm_suld_3d_i32_trap:
3129 case Intrinsic::nvvm_suld_3d_i64_trap:
3131 case Intrinsic::nvvm_suld_3d_v2i8_trap:
3133 case Intrinsic::nvvm_suld_3d_v2i16_trap:
3135 case Intrinsic::nvvm_suld_3d_v2i32_trap:
3137 case Intrinsic::nvvm_suld_3d_v2i64_trap:
3139 case Intrinsic::nvvm_suld_3d_v4i8_trap:
3141 case Intrinsic::nvvm_suld_3d_v4i16_trap:
3143 case Intrinsic::nvvm_suld_3d_v4i32_trap:
3145 case Intrinsic::nvvm_suld_1d_i8_zero:
3147 case Intrinsic::nvvm_suld_1d_i16_zero:
3149 case Intrinsic::nvvm_suld_1d_i32_zero:
3151 case Intrinsic::nvvm_suld_1d_i64_zero:
3153 case Intrinsic::nvvm_suld_1d_v2i8_zero:
3155 case Intrinsic::nvvm_suld_1d_v2i16_zero:
3157 case Intrinsic::nvvm_suld_1d_v2i32_zero:
3159 case Intrinsic::nvvm_suld_1d_v2i64_zero:
3161 case Intrinsic::nvvm_suld_1d_v4i8_zero:
3163 case Intrinsic::nvvm_suld_1d_v4i16_zero:
3165 case Intrinsic::nvvm_suld_1d_v4i32_zero:
3167 case Intrinsic::nvvm_suld_1d_array_i8_zero:
3169 case Intrinsic::nvvm_suld_1d_array_i16_zero:
3171 case Intrinsic::nvvm_suld_1d_array_i32_zero:
3173 case Intrinsic::nvvm_suld_1d_array_i64_zero:
3175 case Intrinsic::nvvm_suld_1d_array_v2i8_zero:
3177 case Intrinsic::nvvm_suld_1d_array_v2i16_zero:
3179 case Intrinsic::nvvm_suld_1d_array_v2i32_zero:
3181 case Intrinsic::nvvm_suld_1d_array_v2i64_zero:
3183 case Intrinsic::nvvm_suld_1d_array_v4i8_zero:
3185 case Intrinsic::nvvm_suld_1d_array_v4i16_zero:
3187 case Intrinsic::nvvm_suld_1d_array_v4i32_zero:
3189 case Intrinsic::nvvm_suld_2d_i8_zero:
3191 case Intrinsic::nvvm_suld_2d_i16_zero:
3193 case Intrinsic::nvvm_suld_2d_i32_zero:
3195 case Intrinsic::nvvm_suld_2d_i64_zero:
3197 case Intrinsic::nvvm_suld_2d_v2i8_zero:
3199 case Intrinsic::nvvm_suld_2d_v2i16_zero:
3201 case Intrinsic::nvvm_suld_2d_v2i32_zero:
3203 case Intrinsic::nvvm_suld_2d_v2i64_zero:
3205 case Intrinsic::nvvm_suld_2d_v4i8_zero:
3207 case Intrinsic::nvvm_suld_2d_v4i16_zero:
3209 case Intrinsic::nvvm_suld_2d_v4i32_zero:
3211 case Intrinsic::nvvm_suld_2d_array_i8_zero:
3213 case Intrinsic::nvvm_suld_2d_array_i16_zero:
3215 case Intrinsic::nvvm_suld_2d_array_i32_zero:
3217 case Intrinsic::nvvm_suld_2d_array_i64_zero:
3219 case Intrinsic::nvvm_suld_2d_array_v2i8_zero:
3221 case Intrinsic::nvvm_suld_2d_array_v2i16_zero:
3223 case Intrinsic::nvvm_suld_2d_array_v2i32_zero:
3225 case Intrinsic::nvvm_suld_2d_array_v2i64_zero:
3227 case Intrinsic::nvvm_suld_2d_array_v4i8_zero:
3229 case Intrinsic::nvvm_suld_2d_array_v4i16_zero:
3231 case Intrinsic::nvvm_suld_2d_array_v4i32_zero:
3233 case Intrinsic::nvvm_suld_3d_i8_zero:
3235 case Intrinsic::nvvm_suld_3d_i16_zero:
3237 case Intrinsic::nvvm_suld_3d_i32_zero:
3239 case Intrinsic::nvvm_suld_3d_i64_zero:
3241 case Intrinsic::nvvm_suld_3d_v2i8_zero:
3243 case Intrinsic::nvvm_suld_3d_v2i16_zero:
3245 case Intrinsic::nvvm_suld_3d_v2i32_zero:
3247 case Intrinsic::nvvm_suld_3d_v2i64_zero:
3249 case Intrinsic::nvvm_suld_3d_v4i8_zero:
3251 case Intrinsic::nvvm_suld_3d_v4i16_zero:
3253 case Intrinsic::nvvm_suld_3d_v4i32_zero:
3265 switch (Intrinsic) {
3269 case Intrinsic::nvvm_atomic_load_add_f32:
3280 case Intrinsic::nvvm_atomic_load_inc_32:
3281 case Intrinsic::nvvm_atomic_load_dec_32:
3292 case Intrinsic::nvvm_ldu_global_i:
3293 case Intrinsic::nvvm_ldu_global_f:
3294 case Intrinsic::nvvm_ldu_global_p: {
3297 if (Intrinsic == Intrinsic::nvvm_ldu_global_i)
3299 else if(Intrinsic == Intrinsic::nvvm_ldu_global_p)
3312 case Intrinsic::nvvm_ldg_global_i:
3313 case Intrinsic::nvvm_ldg_global_f:
3314 case Intrinsic::nvvm_ldg_global_p: {
3318 if (Intrinsic == Intrinsic::nvvm_ldg_global_i)
3320 else if(Intrinsic == Intrinsic::nvvm_ldg_global_p)
3334 case Intrinsic::nvvm_tex_1d_v4f32_s32:
3335 case Intrinsic::nvvm_tex_1d_v4f32_f32:
3336 case Intrinsic::nvvm_tex_1d_level_v4f32_f32:
3337 case Intrinsic::nvvm_tex_1d_grad_v4f32_f32:
3338 case Intrinsic::nvvm_tex_1d_array_v4f32_s32:
3339 case Intrinsic::nvvm_tex_1d_array_v4f32_f32:
3340 case Intrinsic::nvvm_tex_1d_array_level_v4f32_f32:
3341 case Intrinsic::nvvm_tex_1d_array_grad_v4f32_f32:
3342 case Intrinsic::nvvm_tex_2d_v4f32_s32:
3343 case Intrinsic::nvvm_tex_2d_v4f32_f32:
3344 case Intrinsic::nvvm_tex_2d_level_v4f32_f32:
3345 case Intrinsic::nvvm_tex_2d_grad_v4f32_f32:
3346 case Intrinsic::nvvm_tex_2d_array_v4f32_s32:
3347 case Intrinsic::nvvm_tex_2d_array_v4f32_f32:
3348 case Intrinsic::nvvm_tex_2d_array_level_v4f32_f32:
3349 case Intrinsic::nvvm_tex_2d_array_grad_v4f32_f32:
3350 case Intrinsic::nvvm_tex_3d_v4f32_s32:
3351 case Intrinsic::nvvm_tex_3d_v4f32_f32:
3352 case Intrinsic::nvvm_tex_3d_level_v4f32_f32:
3353 case Intrinsic::nvvm_tex_3d_grad_v4f32_f32:
3354 case Intrinsic::nvvm_tex_cube_v4f32_f32:
3355 case Intrinsic::nvvm_tex_cube_level_v4f32_f32:
3356 case Intrinsic::nvvm_tex_cube_array_v4f32_f32:
3357 case Intrinsic::nvvm_tex_cube_array_level_v4f32_f32:
3358 case Intrinsic::nvvm_tld4_r_2d_v4f32_f32:
3359 case Intrinsic::nvvm_tld4_g_2d_v4f32_f32:
3360 case Intrinsic::nvvm_tld4_b_2d_v4f32_f32:
3361 case Intrinsic::nvvm_tld4_a_2d_v4f32_f32:
3362 case Intrinsic::nvvm_tex_unified_1d_v4f32_s32:
3363 case Intrinsic::nvvm_tex_unified_1d_v4f32_f32:
3364 case Intrinsic::nvvm_tex_unified_1d_level_v4f32_f32:
3365 case Intrinsic::nvvm_tex_unified_1d_grad_v4f32_f32:
3366 case Intrinsic::nvvm_tex_unified_1d_array_v4f32_s32:
3367 case Intrinsic::nvvm_tex_unified_1d_array_v4f32_f32:
3368 case Intrinsic::nvvm_tex_unified_1d_array_level_v4f32_f32:
3369 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4f32_f32:
3370 case Intrinsic::nvvm_tex_unified_2d_v4f32_s32:
3371 case Intrinsic::nvvm_tex_unified_2d_v4f32_f32:
3372 case Intrinsic::nvvm_tex_unified_2d_level_v4f32_f32:
3373 case Intrinsic::nvvm_tex_unified_2d_grad_v4f32_f32:
3374 case Intrinsic::nvvm_tex_unified_2d_array_v4f32_s32:
3375 case Intrinsic::nvvm_tex_unified_2d_array_v4f32_f32:
3376 case Intrinsic::nvvm_tex_unified_2d_array_level_v4f32_f32:
3377 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4f32_f32:
3378 case Intrinsic::nvvm_tex_unified_3d_v4f32_s32:
3379 case Intrinsic::nvvm_tex_unified_3d_v4f32_f32:
3380 case Intrinsic::nvvm_tex_unified_3d_level_v4f32_f32:
3381 case Intrinsic::nvvm_tex_unified_3d_grad_v4f32_f32:
3382 case Intrinsic::nvvm_tex_unified_cube_v4f32_f32:
3383 case Intrinsic::nvvm_tex_unified_cube_level_v4f32_f32:
3384 case Intrinsic::nvvm_tex_unified_cube_array_v4f32_f32:
3385 case Intrinsic::nvvm_tex_unified_cube_array_level_v4f32_f32:
3386 case Intrinsic::nvvm_tld4_unified_r_2d_v4f32_f32:
3387 case Intrinsic::nvvm_tld4_unified_g_2d_v4f32_f32:
3388 case Intrinsic::nvvm_tld4_unified_b_2d_v4f32_f32:
3389 case Intrinsic::nvvm_tld4_unified_a_2d_v4f32_f32: {
3400 case Intrinsic::nvvm_tex_1d_v4s32_s32:
3401 case Intrinsic::nvvm_tex_1d_v4s32_f32:
3402 case Intrinsic::nvvm_tex_1d_level_v4s32_f32:
3403 case Intrinsic::nvvm_tex_1d_grad_v4s32_f32:
3404 case Intrinsic::nvvm_tex_1d_array_v4s32_s32:
3405 case Intrinsic::nvvm_tex_1d_array_v4s32_f32:
3406 case Intrinsic::nvvm_tex_1d_array_level_v4s32_f32:
3407 case Intrinsic::nvvm_tex_1d_array_grad_v4s32_f32:
3408 case Intrinsic::nvvm_tex_2d_v4s32_s32:
3409 case Intrinsic::nvvm_tex_2d_v4s32_f32:
3410 case Intrinsic::nvvm_tex_2d_level_v4s32_f32:
3411 case Intrinsic::nvvm_tex_2d_grad_v4s32_f32:
3412 case Intrinsic::nvvm_tex_2d_array_v4s32_s32:
3413 case Intrinsic::nvvm_tex_2d_array_v4s32_f32:
3414 case Intrinsic::nvvm_tex_2d_array_level_v4s32_f32:
3415 case Intrinsic::nvvm_tex_2d_array_grad_v4s32_f32:
3416 case Intrinsic::nvvm_tex_3d_v4s32_s32:
3417 case Intrinsic::nvvm_tex_3d_v4s32_f32:
3418 case Intrinsic::nvvm_tex_3d_level_v4s32_f32:
3419 case Intrinsic::nvvm_tex_3d_grad_v4s32_f32:
3420 case Intrinsic::nvvm_tex_cube_v4s32_f32:
3421 case Intrinsic::nvvm_tex_cube_level_v4s32_f32:
3422 case Intrinsic::nvvm_tex_cube_array_v4s32_f32:
3423 case Intrinsic::nvvm_tex_cube_array_level_v4s32_f32:
3424 case Intrinsic::nvvm_tex_cube_v4u32_f32:
3425 case Intrinsic::nvvm_tex_cube_level_v4u32_f32:
3426 case Intrinsic::nvvm_tex_cube_array_v4u32_f32:
3427 case Intrinsic::nvvm_tex_cube_array_level_v4u32_f32:
3428 case Intrinsic::nvvm_tex_1d_v4u32_s32:
3429 case Intrinsic::nvvm_tex_1d_v4u32_f32:
3430 case Intrinsic::nvvm_tex_1d_level_v4u32_f32:
3431 case Intrinsic::nvvm_tex_1d_grad_v4u32_f32:
3432 case Intrinsic::nvvm_tex_1d_array_v4u32_s32:
3433 case Intrinsic::nvvm_tex_1d_array_v4u32_f32:
3434 case Intrinsic::nvvm_tex_1d_array_level_v4u32_f32:
3435 case Intrinsic::nvvm_tex_1d_array_grad_v4u32_f32:
3436 case Intrinsic::nvvm_tex_2d_v4u32_s32:
3437 case Intrinsic::nvvm_tex_2d_v4u32_f32:
3438 case Intrinsic::nvvm_tex_2d_level_v4u32_f32:
3439 case Intrinsic::nvvm_tex_2d_grad_v4u32_f32:
3440 case Intrinsic::nvvm_tex_2d_array_v4u32_s32:
3441 case Intrinsic::nvvm_tex_2d_array_v4u32_f32:
3442 case Intrinsic::nvvm_tex_2d_array_level_v4u32_f32:
3443 case Intrinsic::nvvm_tex_2d_array_grad_v4u32_f32:
3444 case Intrinsic::nvvm_tex_3d_v4u32_s32:
3445 case Intrinsic::nvvm_tex_3d_v4u32_f32:
3446 case Intrinsic::nvvm_tex_3d_level_v4u32_f32:
3447 case Intrinsic::nvvm_tex_3d_grad_v4u32_f32:
3448 case Intrinsic::nvvm_tld4_r_2d_v4s32_f32:
3449 case Intrinsic::nvvm_tld4_g_2d_v4s32_f32:
3450 case Intrinsic::nvvm_tld4_b_2d_v4s32_f32:
3451 case Intrinsic::nvvm_tld4_a_2d_v4s32_f32:
3452 case Intrinsic::nvvm_tld4_r_2d_v4u32_f32:
3453 case Intrinsic::nvvm_tld4_g_2d_v4u32_f32:
3454 case Intrinsic::nvvm_tld4_b_2d_v4u32_f32:
3455 case Intrinsic::nvvm_tld4_a_2d_v4u32_f32:
3456 case Intrinsic::nvvm_tex_unified_1d_v4s32_s32:
3457 case Intrinsic::nvvm_tex_unified_1d_v4s32_f32:
3458 case Intrinsic::nvvm_tex_unified_1d_level_v4s32_f32:
3459 case Intrinsic::nvvm_tex_unified_1d_grad_v4s32_f32:
3460 case Intrinsic::nvvm_tex_unified_1d_array_v4s32_s32:
3461 case Intrinsic::nvvm_tex_unified_1d_array_v4s32_f32:
3462 case Intrinsic::nvvm_tex_unified_1d_array_level_v4s32_f32:
3463 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4s32_f32:
3464 case Intrinsic::nvvm_tex_unified_2d_v4s32_s32:
3465 case Intrinsic::nvvm_tex_unified_2d_v4s32_f32:
3466 case Intrinsic::nvvm_tex_unified_2d_level_v4s32_f32:
3467 case Intrinsic::nvvm_tex_unified_2d_grad_v4s32_f32:
3468 case Intrinsic::nvvm_tex_unified_2d_array_v4s32_s32:
3469 case Intrinsic::nvvm_tex_unified_2d_array_v4s32_f32:
3470 case Intrinsic::nvvm_tex_unified_2d_array_level_v4s32_f32:
3471 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4s32_f32:
3472 case Intrinsic::nvvm_tex_unified_3d_v4s32_s32:
3473 case Intrinsic::nvvm_tex_unified_3d_v4s32_f32:
3474 case Intrinsic::nvvm_tex_unified_3d_level_v4s32_f32:
3475 case Intrinsic::nvvm_tex_unified_3d_grad_v4s32_f32:
3476 case Intrinsic::nvvm_tex_unified_1d_v4u32_s32:
3477 case Intrinsic::nvvm_tex_unified_1d_v4u32_f32:
3478 case Intrinsic::nvvm_tex_unified_1d_level_v4u32_f32:
3479 case Intrinsic::nvvm_tex_unified_1d_grad_v4u32_f32:
3480 case Intrinsic::nvvm_tex_unified_1d_array_v4u32_s32:
3481 case Intrinsic::nvvm_tex_unified_1d_array_v4u32_f32:
3482 case Intrinsic::nvvm_tex_unified_1d_array_level_v4u32_f32:
3483 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4u32_f32:
3484 case Intrinsic::nvvm_tex_unified_2d_v4u32_s32:
3485 case Intrinsic::nvvm_tex_unified_2d_v4u32_f32:
3486 case Intrinsic::nvvm_tex_unified_2d_level_v4u32_f32:
3487 case Intrinsic::nvvm_tex_unified_2d_grad_v4u32_f32:
3488 case Intrinsic::nvvm_tex_unified_2d_array_v4u32_s32:
3489 case Intrinsic::nvvm_tex_unified_2d_array_v4u32_f32:
3490 case Intrinsic::nvvm_tex_unified_2d_array_level_v4u32_f32:
3491 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4u32_f32:
3492 case Intrinsic::nvvm_tex_unified_3d_v4u32_s32:
3493 case Intrinsic::nvvm_tex_unified_3d_v4u32_f32:
3494 case Intrinsic::nvvm_tex_unified_3d_level_v4u32_f32:
3495 case Intrinsic::nvvm_tex_unified_3d_grad_v4u32_f32:
3496 case Intrinsic::nvvm_tex_unified_cube_v4s32_f32:
3497 case Intrinsic::nvvm_tex_unified_cube_level_v4s32_f32:
3498 case Intrinsic::nvvm_tex_unified_cube_array_v4s32_f32:
3499 case Intrinsic::nvvm_tex_unified_cube_array_level_v4s32_f32:
3500 case Intrinsic::nvvm_tex_unified_cube_v4u32_f32:
3501 case Intrinsic::nvvm_tex_unified_cube_level_v4u32_f32:
3502 case Intrinsic::nvvm_tex_unified_cube_array_v4u32_f32:
3503 case Intrinsic::nvvm_tex_unified_cube_array_level_v4u32_f32:
3504 case Intrinsic::nvvm_tld4_unified_r_2d_v4s32_f32:
3505 case Intrinsic::nvvm_tld4_unified_g_2d_v4s32_f32:
3506 case Intrinsic::nvvm_tld4_unified_b_2d_v4s32_f32:
3507 case Intrinsic::nvvm_tld4_unified_a_2d_v4s32_f32:
3508 case Intrinsic::nvvm_tld4_unified_r_2d_v4u32_f32:
3509 case Intrinsic::nvvm_tld4_unified_g_2d_v4u32_f32:
3510 case Intrinsic::nvvm_tld4_unified_b_2d_v4u32_f32:
3511 case Intrinsic::nvvm_tld4_unified_a_2d_v4u32_f32: {
3522 case Intrinsic::nvvm_suld_1d_i8_clamp:
3523 case Intrinsic::nvvm_suld_1d_v2i8_clamp:
3524 case Intrinsic::nvvm_suld_1d_v4i8_clamp:
3525 case Intrinsic::nvvm_suld_1d_array_i8_clamp:
3526 case Intrinsic::nvvm_suld_1d_array_v2i8_clamp:
3527 case Intrinsic::nvvm_suld_1d_array_v4i8_clamp:
3528 case Intrinsic::nvvm_suld_2d_i8_clamp:
3529 case Intrinsic::nvvm_suld_2d_v2i8_clamp:
3530 case Intrinsic::nvvm_suld_2d_v4i8_clamp:
3531 case Intrinsic::nvvm_suld_2d_array_i8_clamp:
3532 case Intrinsic::nvvm_suld_2d_array_v2i8_clamp:
3533 case Intrinsic::nvvm_suld_2d_array_v4i8_clamp:
3534 case Intrinsic::nvvm_suld_3d_i8_clamp:
3535 case Intrinsic::nvvm_suld_3d_v2i8_clamp:
3536 case Intrinsic::nvvm_suld_3d_v4i8_clamp:
3537 case Intrinsic::nvvm_suld_1d_i8_trap:
3538 case Intrinsic::nvvm_suld_1d_v2i8_trap:
3539 case Intrinsic::nvvm_suld_1d_v4i8_trap:
3540 case Intrinsic::nvvm_suld_1d_array_i8_trap:
3541 case Intrinsic::nvvm_suld_1d_array_v2i8_trap:
3542 case Intrinsic::nvvm_suld_1d_array_v4i8_trap:
3543 case Intrinsic::nvvm_suld_2d_i8_trap:
3544 case Intrinsic::nvvm_suld_2d_v2i8_trap:
3545 case Intrinsic::nvvm_suld_2d_v4i8_trap:
3546 case Intrinsic::nvvm_suld_2d_array_i8_trap:
3547 case Intrinsic::nvvm_suld_2d_array_v2i8_trap:
3548 case Intrinsic::nvvm_suld_2d_array_v4i8_trap:
3549 case Intrinsic::nvvm_suld_3d_i8_trap:
3550 case Intrinsic::nvvm_suld_3d_v2i8_trap:
3551 case Intrinsic::nvvm_suld_3d_v4i8_trap:
3552 case Intrinsic::nvvm_suld_1d_i8_zero:
3553 case Intrinsic::nvvm_suld_1d_v2i8_zero:
3554 case Intrinsic::nvvm_suld_1d_v4i8_zero:
3555 case Intrinsic::nvvm_suld_1d_array_i8_zero:
3556 case Intrinsic::nvvm_suld_1d_array_v2i8_zero:
3557 case Intrinsic::nvvm_suld_1d_array_v4i8_zero:
3558 case Intrinsic::nvvm_suld_2d_i8_zero:
3559 case Intrinsic::nvvm_suld_2d_v2i8_zero:
3560 case Intrinsic::nvvm_suld_2d_v4i8_zero:
3561 case Intrinsic::nvvm_suld_2d_array_i8_zero:
3562 case Intrinsic::nvvm_suld_2d_array_v2i8_zero:
3563 case Intrinsic::nvvm_suld_2d_array_v4i8_zero:
3564 case Intrinsic::nvvm_suld_3d_i8_zero:
3565 case Intrinsic::nvvm_suld_3d_v2i8_zero:
3566 case Intrinsic::nvvm_suld_3d_v4i8_zero: {
3577 case Intrinsic::nvvm_suld_1d_i16_clamp:
3578 case Intrinsic::nvvm_suld_1d_v2i16_clamp:
3579 case Intrinsic::nvvm_suld_1d_v4i16_clamp:
3580 case Intrinsic::nvvm_suld_1d_array_i16_clamp:
3581 case Intrinsic::nvvm_suld_1d_array_v2i16_clamp:
3582 case Intrinsic::nvvm_suld_1d_array_v4i16_clamp:
3583 case Intrinsic::nvvm_suld_2d_i16_clamp:
3584 case Intrinsic::nvvm_suld_2d_v2i16_clamp:
3585 case Intrinsic::nvvm_suld_2d_v4i16_clamp:
3586 case Intrinsic::nvvm_suld_2d_array_i16_clamp:
3587 case Intrinsic::nvvm_suld_2d_array_v2i16_clamp:
3588 case Intrinsic::nvvm_suld_2d_array_v4i16_clamp:
3589 case Intrinsic::nvvm_suld_3d_i16_clamp:
3590 case Intrinsic::nvvm_suld_3d_v2i16_clamp:
3591 case Intrinsic::nvvm_suld_3d_v4i16_clamp:
3592 case Intrinsic::nvvm_suld_1d_i16_trap:
3593 case Intrinsic::nvvm_suld_1d_v2i16_trap:
3594 case Intrinsic::nvvm_suld_1d_v4i16_trap:
3595 case Intrinsic::nvvm_suld_1d_array_i16_trap:
3596 case Intrinsic::nvvm_suld_1d_array_v2i16_trap:
3597 case Intrinsic::nvvm_suld_1d_array_v4i16_trap:
3598 case Intrinsic::nvvm_suld_2d_i16_trap:
3599 case Intrinsic::nvvm_suld_2d_v2i16_trap:
3600 case Intrinsic::nvvm_suld_2d_v4i16_trap:
3601 case Intrinsic::nvvm_suld_2d_array_i16_trap:
3602 case Intrinsic::nvvm_suld_2d_array_v2i16_trap:
3603 case Intrinsic::nvvm_suld_2d_array_v4i16_trap:
3604 case Intrinsic::nvvm_suld_3d_i16_trap:
3605 case Intrinsic::nvvm_suld_3d_v2i16_trap:
3606 case Intrinsic::nvvm_suld_3d_v4i16_trap:
3607 case Intrinsic::nvvm_suld_1d_i16_zero:
3608 case Intrinsic::nvvm_suld_1d_v2i16_zero:
3609 case Intrinsic::nvvm_suld_1d_v4i16_zero:
3610 case Intrinsic::nvvm_suld_1d_array_i16_zero:
3611 case Intrinsic::nvvm_suld_1d_array_v2i16_zero:
3612 case Intrinsic::nvvm_suld_1d_array_v4i16_zero:
3613 case Intrinsic::nvvm_suld_2d_i16_zero:
3614 case Intrinsic::nvvm_suld_2d_v2i16_zero:
3615 case Intrinsic::nvvm_suld_2d_v4i16_zero:
3616 case Intrinsic::nvvm_suld_2d_array_i16_zero:
3617 case Intrinsic::nvvm_suld_2d_array_v2i16_zero:
3618 case Intrinsic::nvvm_suld_2d_array_v4i16_zero:
3619 case Intrinsic::nvvm_suld_3d_i16_zero:
3620 case Intrinsic::nvvm_suld_3d_v2i16_zero:
3621 case Intrinsic::nvvm_suld_3d_v4i16_zero: {
3632 case Intrinsic::nvvm_suld_1d_i32_clamp:
3633 case Intrinsic::nvvm_suld_1d_v2i32_clamp:
3634 case Intrinsic::nvvm_suld_1d_v4i32_clamp:
3635 case Intrinsic::nvvm_suld_1d_array_i32_clamp:
3636 case Intrinsic::nvvm_suld_1d_array_v2i32_clamp:
3637 case Intrinsic::nvvm_suld_1d_array_v4i32_clamp:
3638 case Intrinsic::nvvm_suld_2d_i32_clamp:
3639 case Intrinsic::nvvm_suld_2d_v2i32_clamp:
3640 case Intrinsic::nvvm_suld_2d_v4i32_clamp:
3641 case Intrinsic::nvvm_suld_2d_array_i32_clamp:
3642 case Intrinsic::nvvm_suld_2d_array_v2i32_clamp:
3643 case Intrinsic::nvvm_suld_2d_array_v4i32_clamp:
3644 case Intrinsic::nvvm_suld_3d_i32_clamp:
3645 case Intrinsic::nvvm_suld_3d_v2i32_clamp:
3646 case Intrinsic::nvvm_suld_3d_v4i32_clamp:
3647 case Intrinsic::nvvm_suld_1d_i32_trap:
3648 case Intrinsic::nvvm_suld_1d_v2i32_trap:
3649 case Intrinsic::nvvm_suld_1d_v4i32_trap:
3650 case Intrinsic::nvvm_suld_1d_array_i32_trap:
3651 case Intrinsic::nvvm_suld_1d_array_v2i32_trap:
3652 case Intrinsic::nvvm_suld_1d_array_v4i32_trap:
3653 case Intrinsic::nvvm_suld_2d_i32_trap:
3654 case Intrinsic::nvvm_suld_2d_v2i32_trap:
3655 case Intrinsic::nvvm_suld_2d_v4i32_trap:
3656 case Intrinsic::nvvm_suld_2d_array_i32_trap:
3657 case Intrinsic::nvvm_suld_2d_array_v2i32_trap:
3658 case Intrinsic::nvvm_suld_2d_array_v4i32_trap:
3659 case Intrinsic::nvvm_suld_3d_i32_trap:
3660 case Intrinsic::nvvm_suld_3d_v2i32_trap:
3661 case Intrinsic::nvvm_suld_3d_v4i32_trap:
3662 case Intrinsic::nvvm_suld_1d_i32_zero:
3663 case Intrinsic::nvvm_suld_1d_v2i32_zero:
3664 case Intrinsic::nvvm_suld_1d_v4i32_zero:
3665 case Intrinsic::nvvm_suld_1d_array_i32_zero:
3666 case Intrinsic::nvvm_suld_1d_array_v2i32_zero:
3667 case Intrinsic::nvvm_suld_1d_array_v4i32_zero:
3668 case Intrinsic::nvvm_suld_2d_i32_zero:
3669 case Intrinsic::nvvm_suld_2d_v2i32_zero:
3670 case Intrinsic::nvvm_suld_2d_v4i32_zero:
3671 case Intrinsic::nvvm_suld_2d_array_i32_zero:
3672 case Intrinsic::nvvm_suld_2d_array_v2i32_zero:
3673 case Intrinsic::nvvm_suld_2d_array_v4i32_zero:
3674 case Intrinsic::nvvm_suld_3d_i32_zero:
3675 case Intrinsic::nvvm_suld_3d_v2i32_zero:
3676 case Intrinsic::nvvm_suld_3d_v4i32_zero: {
3687 case Intrinsic::nvvm_suld_1d_i64_clamp:
3688 case Intrinsic::nvvm_suld_1d_v2i64_clamp:
3689 case Intrinsic::nvvm_suld_1d_array_i64_clamp:
3690 case Intrinsic::nvvm_suld_1d_array_v2i64_clamp:
3691 case Intrinsic::nvvm_suld_2d_i64_clamp:
3692 case Intrinsic::nvvm_suld_2d_v2i64_clamp:
3693 case Intrinsic::nvvm_suld_2d_array_i64_clamp:
3694 case Intrinsic::nvvm_suld_2d_array_v2i64_clamp:
3695 case Intrinsic::nvvm_suld_3d_i64_clamp:
3696 case Intrinsic::nvvm_suld_3d_v2i64_clamp:
3697 case Intrinsic::nvvm_suld_1d_i64_trap:
3698 case Intrinsic::nvvm_suld_1d_v2i64_trap:
3699 case Intrinsic::nvvm_suld_1d_array_i64_trap:
3700 case Intrinsic::nvvm_suld_1d_array_v2i64_trap:
3701 case Intrinsic::nvvm_suld_2d_i64_trap:
3702 case Intrinsic::nvvm_suld_2d_v2i64_trap:
3703 case Intrinsic::nvvm_suld_2d_array_i64_trap:
3704 case Intrinsic::nvvm_suld_2d_array_v2i64_trap:
3705 case Intrinsic::nvvm_suld_3d_i64_trap:
3706 case Intrinsic::nvvm_suld_3d_v2i64_trap:
3707 case Intrinsic::nvvm_suld_1d_i64_zero:
3708 case Intrinsic::nvvm_suld_1d_v2i64_zero:
3709 case Intrinsic::nvvm_suld_1d_array_i64_zero:
3710 case Intrinsic::nvvm_suld_1d_array_v2i64_zero:
3711 case Intrinsic::nvvm_suld_2d_i64_zero:
3712 case Intrinsic::nvvm_suld_2d_v2i64_zero:
3713 case Intrinsic::nvvm_suld_2d_array_i64_zero:
3714 case Intrinsic::nvvm_suld_2d_array_v2i64_zero:
3715 case Intrinsic::nvvm_suld_3d_i64_zero:
3716 case Intrinsic::nvvm_suld_3d_v2i64_zero: {
3738 unsigned AS)
const {
3778 if (Constraint.
size() == 1) {
3779 switch (Constraint[0]) {
3797 std::pair<unsigned, const TargetRegisterClass *>
3801 if (Constraint.
size() == 1) {
3802 switch (Constraint[0]) {
3804 return std::make_pair(0U, &NVPTX::Int1RegsRegClass);
3806 return std::make_pair(0U, &NVPTX::Int16RegsRegClass);
3808 return std::make_pair(0U, &NVPTX::Int16RegsRegClass);
3810 return std::make_pair(0U, &NVPTX::Int32RegsRegClass);
3813 return std::make_pair(0U, &NVPTX::Int64RegsRegClass);
3815 return std::make_pair(0U, &NVPTX::Float32RegsRegClass);
3817 return std::make_pair(0U, &NVPTX::Float64RegsRegClass);
3840 }
else if (OptLevel == 0) {
3904 int nonAddCount = 0;
3922 if (orderNo - orderNo2 < 500)
3927 bool opIsLive =
false;
3931 if (isa<ConstantSDNode>(left) || isa<ConstantSDNode>(right))
3938 if (orderNo3 > orderNo) {
3948 if (orderNo3 > orderNo) {
3995 if (isa<ConstantSDNode>(Val)) {
4019 if (MaskVal != 0xff) {
4110 IsSigned = (LHSSign ==
Signed);
4114 APInt Val = CI->getAPIntValue();
4116 if (Val.
isIntN(OptSize)) {
4131 if (LHSSign != RHSSign)
4156 if (isa<ConstantSDNode>(LHS)) {
4170 if (ShiftAmt.
sge(0) && ShiftAmt.
slt(BitWidth)) {
4171 APInt MulVal =
APInt(BitWidth, 1) << ShiftAmt;
4205 return DCI.
DAG.
getNode(Opc, DL, MulType, TruncLHS, TruncRHS);
4237 DAGCombinerInfo &DCI)
const {
4260 assert(ResVT.
isVector() &&
"Vector load must have vector type");
4265 assert(ResVT.
isSimple() &&
"Can only handle simple types");
4287 unsigned PrefAlign =
4289 if (Align < PrefAlign) {
4304 bool NeedTrunc =
false;
4310 unsigned Opcode = 0;
4341 for (
unsigned i = 0; i < NumElts; ++i) {
4363 unsigned IntrinNo = cast<ConstantSDNode>(Intrin.
getNode())->getZExtValue();
4367 case Intrinsic::nvvm_ldg_global_i:
4368 case Intrinsic::nvvm_ldg_global_f:
4369 case Intrinsic::nvvm_ldg_global_p:
4370 case Intrinsic::nvvm_ldu_global_i:
4371 case Intrinsic::nvvm_ldu_global_f:
4372 case Intrinsic::nvvm_ldu_global_p: {
4385 bool NeedTrunc =
false;
4391 unsigned Opcode = 0;
4401 case Intrinsic::nvvm_ldg_global_i:
4402 case Intrinsic::nvvm_ldg_global_f:
4403 case Intrinsic::nvvm_ldg_global_p:
4406 case Intrinsic::nvvm_ldu_global_i:
4407 case Intrinsic::nvvm_ldu_global_f:
4408 case Intrinsic::nvvm_ldu_global_p:
4418 case Intrinsic::nvvm_ldg_global_i:
4419 case Intrinsic::nvvm_ldg_global_f:
4420 case Intrinsic::nvvm_ldg_global_p:
4423 case Intrinsic::nvvm_ldu_global_i:
4424 case Intrinsic::nvvm_ldu_global_f:
4425 case Intrinsic::nvvm_ldu_global_p:
4452 for (
unsigned i = 0; i < NumElts; ++i) {
4470 "Custom handling of non-i8 ldu/ldg?");
4487 NewLD.getValue(0)));
4494 void NVPTXTargetLowering::ReplaceNodeResults(
4509 void NVPTXSection::anchor() {}
static unsigned getBitWidth(Type *Ty, const DataLayout &DL)
Returns the bitwidth of the given scalar or pointer type (if unknown returns 0).
SDValue getTruncStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT TVT, bool isNonTemporal, bool isVolatile, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes())
Instances of this class represent a uniqued identifier for a section in the current translation unit...
void push_back(const T &Elt)
A parsed version of the target data layout string in and methods for querying it. ...
SDValue getValue(unsigned R) const
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...
This SDNode is used for target intrinsics that touch memory and need an associated MachineMemOperand...
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
LLVMContext * getContext() const
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, SDLoc DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd)...
SDValue CombineTo(SDNode *N, ArrayRef< SDValue > To, bool AddTo=true)
uint64_t GreatestCommonDivisor64(uint64_t A, uint64_t B)
GreatestCommonDivisor64 - Return the greatest common divisor of the two values using Euclid's algorit...
size_t size() const
size - Get the string size.
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an vector value) starting with the ...
BR_CC - Conditional branch.
unsigned getNumRegisters(LLVMContext &Context, EVT VT) const
Return the number of registers that this ValueType will eventually require.
MCSection * DwarfPubTypesSection
bool hasOneUse() const
Return true if there is exactly one use of this node.
A Module instance is used to store all the information related to an LLVM module. ...
const TargetMachine & getTargetMachine() const
InstrTy * getInstruction() const
static cl::opt< unsigned > FMAContractLevelOpt("nvptx-fma-level", cl::ZeroOrMore, cl::Hidden, cl::desc("NVPTX Specific: FMA contraction (0: don't do it"" 1: do it 2: do it aggressively"), cl::init(2))
SDValue getMergeValues(ArrayRef< SDValue > Ops, SDLoc dl)
Create a MERGE_VALUES node from the given operands.
Carry-setting nodes for multiple precision addition and subtraction.
MCSection * TextSection
Section directive for standard text.
CallInst - This class represents a function call, abstracting a target machine's calling convention...
bool isImageOrSamplerVal(const Value *, const Module *)
static PointerType * get(Type *ElementType, unsigned AddressSpace)
PointerType::get - This constructs a pointer to an object of the specified type in a numbered address...
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
std::string getPrototype(const DataLayout &DL, Type *, const ArgListTy &, const SmallVectorImpl< ISD::OutputArg > &, unsigned retAlignment, const ImmutableCallSite *CS) const
static bool IsMulWideOperandDemotable(SDValue Op, unsigned OptSize, OperandSignedness &S)
IsMulWideOperandDemotable - Checks if the provided DAG node is an operand that can be demoted to OptS...
Type * getTypeForEVT(LLVMContext &Context) const
getTypeForEVT - This method returns an LLVM type corresponding to the specified EVT.
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
unsigned getNumOperands() const
Return the number of values used by this operation.
Type * getReturnType() const
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
MCSection * getDataSection() const
unsigned getNumOperands() const
bool isKernelFunction(const llvm::Function &)
const SDValue & getOperand(unsigned Num) const
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target...
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
FunTy * getCaller() const
getCaller - Return the caller function for this call site
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags=0)
const SDValue & setRoot(SDValue N)
Set the current root tag of the SelectionDAG.
bool hasAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return true if the attribute exists at the given index.
const SDValue & getBasePtr() const
SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag=true)
Reports a serious error, calling any installed error handler.
uint64_t getTypeAllocSizeInBits(Type *Ty) const
Returns the offset in bits between successive objects of the specified type, including alignment padd...
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
static Constant * getNullValue(Type *Ty)
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
bool isVector() const
isVector - Return true if this is a vector value type.
static unsigned int uniqueCallSite
static bool AreMulWideOperandsDemotable(SDValue LHS, SDValue RHS, unsigned OptSize, bool &IsSigned)
AreMulWideOperandsDemotable - Checks if the given LHS and RHS operands can be demoted to OptSize bits...
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
Shift and rotation operations.
static void ComputePTXValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputePTXValueVTs - For the given Type Ty, returns the set of primitive EVTs that compose it...
unsigned getFunctionAlignment(const Function *F) const
getFunctionAlignment - Return the Log2 alignment of this function.
StructType - Class to represent struct types.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
MachineFunction & getMachineFunction() const
MCSection * DwarfLineSection
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
SDValue getTargetGlobalAddress(const GlobalValue *GV, SDLoc DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
bool isLiteral() const
isLiteral - Return true if this type is uniqued by structural equivalence, false if it is a struct de...
MCSection * StaticDtorSection
This section contains the static destructor pointer list.
EVT getScalarType() const
getScalarType - If this is a vector type, return the element type, otherwise return this...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
bool isIntN(unsigned N) const
Check if this APInt has an N-bits unsigned integer value.
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG...
static void ReplaceLoadVector(SDNode *N, SelectionDAG &DAG, SmallVectorImpl< SDValue > &Results)
ReplaceVectorLoad - Convert vector loads into multi-output scalar loads.
void setJumpIsExpensive(bool isExpensive=true)
Tells the code generator not to expand logic operations on comparison predicates into separate sequen...
MCSection * DwarfFrameSection
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
bool isTypeSupportedInIntrinsic(MVT VT) const
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
SmallVector< ISD::InputArg, 32 > Ins
EVT getVectorElementType() const
getVectorElementType - Given a vector type, return the type of each element.
SDValue getCALLSEQ_START(SDValue Chain, SDValue Op, SDLoc DL)
Return a new CALLSEQ_START node, which always must have a glue result (to ensure it's not CSE'd)...
ConstantExpr - a constant value that is initialized with an expression using other constant values...
unsigned getIROrder() const
Return the node ordering.
const MCSection * DwarfDebugInlineSection
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
unsigned int getSmVersion() const
Simple integer binary arithmetic operators.
SmallVector< ISD::OutputArg, 32 > Outs
TypeID getTypeID() const
getTypeID - Return the type id for the type.
bool isFloatingPointTy() const
isFloatingPointTy - Return true if this is one of the six floating point types
const SDValue & getBasePtr() const
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
const APInt & getAPIntValue() const
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
EVT getMemoryVT() const
Return the type of the in-memory value.
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
static SDValue PerformADDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const NVPTXSubtarget &Subtarget, CodeGenOpt::Level OptLevel)
PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
void setIROrder(unsigned Order)
Set the node ordering.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
static SDValue PerformANDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
Type * getElementType() const
const DataLayout & getDataLayout() const
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
MCSection * DataSection
Section directive for standard data.
PointerType - Class to represent pointers.
UNDEF - An undefined node.
This class is used to represent ISD::STORE nodes.
static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI, const NVPTXSubtarget &Subtarget, CodeGenOpt::Level OptLevel)
PerformADDCombineWithOperands - Try DAG combinations for an ADD with operands N0 and N1...
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable...
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
SDNode * getNode() const
get the SDNode which holds the desired result
virtual ~NVPTXTargetObjectFile()
unsigned getStoreSize() const
getStoreSize - Return the number of bytes overwritten by a store of the specified value type...
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
initializer< Ty > init(const Ty &Val)
unsigned UnsafeFPMath
UnsafeFPMath - This flag is enabled when the -enable-unsafe-fp-math flag is specified on the command ...
unsigned getStoreSizeInBits() const
getStoreSizeInBits - Return the number of bits overwritten by a store of the specified value type...
FPOpFusion::FPOpFusionMode AllowFPOpFusion
AllowFPOpFusion - This flag is set by the -fuse-fp-ops=xxx option.
bool allowFMA(MachineFunction &MF, CodeGenOpt::Level OptLevel) const
MVT - Machine Value Type.
const SDValue & getOperand(unsigned i) const
The instances of the Type class are immutable: once they are created, they are never changed...
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
static cl::opt< bool > sched4reg("nvptx-sched4reg", cl::desc("NVPTX Specific: schedule for register pressue"), cl::init(false))
Simple binary floating point operators.
FunTy * getCalledFunction() const
getCalledFunction - Return the function being called if this is a direct call, otherwise return null ...
void setTargetDAGCombine(ISD::NodeType NT)
Targets should invoke this method for each target independent node that they want to provide a custom...
bool isNonTemporal() const
bool isVectorTy() const
isVectorTy - True if this is an instance of VectorType.
bool sge(const APInt &RHS) const
Signed greather or equal comparison.
bool isVector() const
isVector - Return true if this is a vector value type.
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
const NVPTXTargetLowering * getTargetLowering() const override
Carry-using nodes for multiple precision addition and subtraction.
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
MCSection * DwarfStrSection
static unsigned getOpcForSurfaceInstr(unsigned Intrinsic)
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
This class provides iterator support for SDUse operands that use a specific SDNode.
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
unsigned getOpcode() const
TRAP - Trapping instruction.
ManagedStringPool * getManagedStrPool() const
SectionKind - This is a simple POD value that classifies the properties of a section.
static mvt_range vector_valuetypes()
Class to represent integer types.
use_iterator use_begin() const
Provide iteration support to walk over all uses of an SDNode.
const SDValue & getValue() const
unsigned MaxStoresPerMemmove
Specify maximum bytes of store instructions per memmove call.
SDValue getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes())
Bit counting operators with an undefined result for zero inputs.
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
static void ReplaceINTRINSIC_W_CHAIN(SDNode *N, SelectionDAG &DAG, SmallVectorImpl< SDValue > &Results)
void append(in_iter in_start, in_iter in_end)
Add the specified range to the end of the SmallVector.
EVT - Extended Value Type.
bool isPointerTy() const
isPointerTy - True if this is an instance of PointerType.
std::vector< ArgListEntry > ArgListTy
static SDValue PerformSHLCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, CodeGenOpt::Level OptLevel)
PerformSHLCombine - Runs PTX-specific DAG combine patterns on SHL nodes.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
MCSection * DwarfInfoSection
MCSection * StaticCtorSection
This section contains the static constructor pointer list.
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements)
getVectorVT - Returns the EVT that represents a vector NumElements in length, where each element is o...
MachinePointerInfo - This class contains a discriminated union of information about pointers in memor...
static bool IsPTXVectorType(MVT VT)
const SDValue & getRoot() const
Return the root tag of the SelectionDAG.
MCSection * DwarfAbbrevSection
const MachinePointerInfo & getPointerInfo() const
static SDValue TryMULWIDECombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
TryMULWIDECombine - Attempt to replace a multiply of M bits with a multiply of M/2 bits that produces...
MCSection * EHFrameSection
EH frame section.
TokenFactor - This node takes multiple tokens as input and produces a single token result...
unsigned getABITypeAlignment(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT) const override
Return the preferred vector type legalization action.
SmallVectorImpl< T >::const_pointer c_str(SmallVectorImpl< T > &str)
bool slt(const APInt &RHS) const
Signed less than comparison.
std::string * getManagedString(const char *S)
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
uint64_t getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
MCSection * SelectSectionForGlobal(const GlobalValue *GV, SectionKind Kind, Mangler &Mang, const TargetMachine &TM) const override
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
const Module * getModule() const
Return the module owning the function this instruction belongs to or nullptr it the function does not...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Module.h This file contains the declarations for the Module class.
Type * getType() const
All values are typed, get the type of this value.
NVPTXTargetLowering(const NVPTXTargetMachine &TM, const NVPTXSubtarget &STI)
MCSection * DwarfRangesSection
bool getAlign(const llvm::Function &, unsigned index, unsigned &)
const SDValue & getChain() const
Byte Swap and Counting operators.
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
This is an abstract virtual class for memory operations.
MCSection * DwarfARangesSection
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
static mvt_range integer_valuetypes()
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Value * getArgOperand(unsigned i) const
getArgOperand/setArgOperand - Return/set the i-th call argument.
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
VectorType - Class to represent vector types.
Class for arbitrary precision integers.
bool isCast() const
Return true if this is a convert constant expression.
bool isSignedIntN(unsigned N) const
Check if this APInt has an N-bits signed integer value.
static SDValue PerformMULCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, CodeGenOpt::Level OptLevel)
PerformMULCombine - Runs PTX-specific DAG combine patterns on MUL nodes.
Select(COND, TRUEVAL, FALSEVAL).
op_iterator op_begin() const
bool isIntegerTy() const
isIntegerTy - True if this is an instance of IntegerType.
StringRef getName() const
getName - Return the name for this struct type if it has an identity.
static use_iterator use_end()
ZERO_EXTEND - Used for integer types, zeroing the new bits.
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
ANY_EXTEND - Used for integer types. The high bits are undefined.
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT) const
Return the preferred vector type legalization action.
BR_JT - Jumptable branch.
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, SDLoc dl, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array...
const DataLayout & getDataLayout() const
Get the data layout for the module's target platform.
SmallVector< SDValue, 32 > OutVals
MCSection * LSDASection
If exception handling is supported by the target, this is the section the Language Specific Data Area...
Bitwise operators - logical and, logical or, logical xor.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
bool isAggregateType() const
isAggregateType - Return true if the type is an aggregate type.
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
ImmutableCallSite - establish a view to a call site for examination.
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
op_iterator op_end() const
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
unsigned MaxStoresPerMemcpy
Specify maximum bytes of store instructions per memcpy call.
EVT getValueType() const
Return the ValueType of the referenced return value.
SDValue getConstant(uint64_t Val, SDLoc DL, EVT VT, bool isTarget=false, bool isOpaque=false)
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
StringRef getValueAsString() const
Return the attribute's value as a string.
const ARM::ArchExtKind Kind
bool isSimple() const
isSimple - Test if the given EVT is simple (as opposed to being extended).
A raw_ostream that writes to an std::string.
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
unsigned getPrimitiveSizeInBits() const LLVM_READONLY
getPrimitiveSizeInBits - Return the basic size of this type if it is a primitive type.
Module * getParent()
Get the module that this global value is contained inside of...
LLVM Value Representation.
FMA - Perform a * b + c with no intermediate rounding step.
static const Function * getParent(const Value *V)
const TargetLowering & getTargetLoweringInfo() const
Primary interface to the complete machine description for the target machine.
MCSection * BSSSection
Section that is default initialized to zero.
StringRef - Represent a constant reference to a string, i.e.
MCSection * ReadOnlySection
Section that is readonly and can contain arbitrary initialized data.
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
SDValue getSetCC(SDLoc DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MVT getVectorElementType() const
static bool isVolatile(Instruction *Inst)
TRUNCATE - Completely drop the high bits.
unsigned getAlignment() const
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
MCSection * DwarfLocSection
MVT getSimpleVT() const
getSimpleVT - Return the SimpleValueType held in the specified simple EVT.
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array...
SDValue getIntPtrConstant(uint64_t Val, SDLoc DL, bool isTarget=false)
SDValue getMemIntrinsicNode(unsigned Opcode, SDLoc dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, unsigned Align=0, bool Vol=false, bool ReadMem=true, bool WriteMem=true, unsigned Size=0)
Creates a MemIntrinsicNode that may produce a result and takes a list of operands.
static unsigned getOpcForTextureInstr(unsigned Intrinsic)
bool isMachineOpcode() const
Test if this node has a post-isel opcode, directly corresponding to a MachineInstr opcode...
unsigned getMachineOpcode() const
This may only be called if isMachineOpcode returns true.
const NVPTXRegisterInfo * getRegisterInfo() const override
uint64_t getZExtValue() const
unsigned getVectorNumElements() const
getVectorNumElements - Given a vector type, return the number of elements it contains.
This class is used to represent ISD::LOAD nodes.
const NVPTXTargetMachine * nvTM