LLVM  3.7.0
SparcInstrInfo.cpp
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1 //===-- SparcInstrInfo.cpp - Sparc Instruction Information ----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Sparc implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "SparcInstrInfo.h"
15 #include "Sparc.h"
17 #include "SparcSubtarget.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallVector.h"
26 
27 using namespace llvm;
28 
29 #define GET_INSTRINFO_CTOR_DTOR
30 #include "SparcGenInstrInfo.inc"
31 
32 // Pin the vtable to this file.
33 void SparcInstrInfo::anchor() {}
34 
36  : SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), RI(),
37  Subtarget(ST) {}
38 
39 /// isLoadFromStackSlot - If the specified machine instruction is a direct
40 /// load from a stack slot, return the virtual or physical register number of
41 /// the destination along with the FrameIndex of the loaded stack slot. If
42 /// not, return 0. This predicate must return 0 if the instruction has
43 /// any side effects other than loading from the stack slot.
45  int &FrameIndex) const {
46  if (MI->getOpcode() == SP::LDri ||
47  MI->getOpcode() == SP::LDXri ||
48  MI->getOpcode() == SP::LDFri ||
49  MI->getOpcode() == SP::LDDFri ||
50  MI->getOpcode() == SP::LDQFri) {
51  if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
52  MI->getOperand(2).getImm() == 0) {
53  FrameIndex = MI->getOperand(1).getIndex();
54  return MI->getOperand(0).getReg();
55  }
56  }
57  return 0;
58 }
59 
60 /// isStoreToStackSlot - If the specified machine instruction is a direct
61 /// store to a stack slot, return the virtual or physical register number of
62 /// the source reg along with the FrameIndex of the loaded stack slot. If
63 /// not, return 0. This predicate must return 0 if the instruction has
64 /// any side effects other than storing to the stack slot.
66  int &FrameIndex) const {
67  if (MI->getOpcode() == SP::STri ||
68  MI->getOpcode() == SP::STXri ||
69  MI->getOpcode() == SP::STFri ||
70  MI->getOpcode() == SP::STDFri ||
71  MI->getOpcode() == SP::STQFri) {
72  if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
73  MI->getOperand(1).getImm() == 0) {
74  FrameIndex = MI->getOperand(0).getIndex();
75  return MI->getOperand(2).getReg();
76  }
77  }
78  return 0;
79 }
80 
81 static bool IsIntegerCC(unsigned CC)
82 {
83  return (CC <= SPCC::ICC_VC);
84 }
85 
86 
88 {
89  switch(CC) {
90  case SPCC::ICC_A: return SPCC::ICC_N;
91  case SPCC::ICC_N: return SPCC::ICC_A;
92  case SPCC::ICC_NE: return SPCC::ICC_E;
93  case SPCC::ICC_E: return SPCC::ICC_NE;
94  case SPCC::ICC_G: return SPCC::ICC_LE;
95  case SPCC::ICC_LE: return SPCC::ICC_G;
96  case SPCC::ICC_GE: return SPCC::ICC_L;
97  case SPCC::ICC_L: return SPCC::ICC_GE;
98  case SPCC::ICC_GU: return SPCC::ICC_LEU;
99  case SPCC::ICC_LEU: return SPCC::ICC_GU;
100  case SPCC::ICC_CC: return SPCC::ICC_CS;
101  case SPCC::ICC_CS: return SPCC::ICC_CC;
102  case SPCC::ICC_POS: return SPCC::ICC_NEG;
103  case SPCC::ICC_NEG: return SPCC::ICC_POS;
104  case SPCC::ICC_VC: return SPCC::ICC_VS;
105  case SPCC::ICC_VS: return SPCC::ICC_VC;
106 
107  case SPCC::FCC_A: return SPCC::FCC_N;
108  case SPCC::FCC_N: return SPCC::FCC_A;
109  case SPCC::FCC_U: return SPCC::FCC_O;
110  case SPCC::FCC_O: return SPCC::FCC_U;
111  case SPCC::FCC_G: return SPCC::FCC_ULE;
112  case SPCC::FCC_LE: return SPCC::FCC_UG;
113  case SPCC::FCC_UG: return SPCC::FCC_LE;
114  case SPCC::FCC_ULE: return SPCC::FCC_G;
115  case SPCC::FCC_L: return SPCC::FCC_UGE;
116  case SPCC::FCC_GE: return SPCC::FCC_UL;
117  case SPCC::FCC_UL: return SPCC::FCC_GE;
118  case SPCC::FCC_UGE: return SPCC::FCC_L;
119  case SPCC::FCC_LG: return SPCC::FCC_UE;
120  case SPCC::FCC_UE: return SPCC::FCC_LG;
121  case SPCC::FCC_NE: return SPCC::FCC_E;
122  case SPCC::FCC_E: return SPCC::FCC_NE;
123  }
124  llvm_unreachable("Invalid cond code");
125 }
126 
128  MachineBasicBlock *&TBB,
129  MachineBasicBlock *&FBB,
131  bool AllowModify) const
132 {
133 
135  MachineBasicBlock::iterator UnCondBrIter = MBB.end();
136  while (I != MBB.begin()) {
137  --I;
138 
139  if (I->isDebugValue())
140  continue;
141 
142  // When we see a non-terminator, we are done.
143  if (!isUnpredicatedTerminator(I))
144  break;
145 
146  // Terminator is not a branch.
147  if (!I->isBranch())
148  return true;
149 
150  // Handle Unconditional branches.
151  if (I->getOpcode() == SP::BA) {
152  UnCondBrIter = I;
153 
154  if (!AllowModify) {
155  TBB = I->getOperand(0).getMBB();
156  continue;
157  }
158 
159  while (std::next(I) != MBB.end())
160  std::next(I)->eraseFromParent();
161 
162  Cond.clear();
163  FBB = nullptr;
164 
165  if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
166  TBB = nullptr;
167  I->eraseFromParent();
168  I = MBB.end();
169  UnCondBrIter = MBB.end();
170  continue;
171  }
172 
173  TBB = I->getOperand(0).getMBB();
174  continue;
175  }
176 
177  unsigned Opcode = I->getOpcode();
178  if (Opcode != SP::BCOND && Opcode != SP::FBCOND)
179  return true; // Unknown Opcode.
180 
181  SPCC::CondCodes BranchCode = (SPCC::CondCodes)I->getOperand(1).getImm();
182 
183  if (Cond.empty()) {
184  MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
185  if (AllowModify && UnCondBrIter != MBB.end() &&
186  MBB.isLayoutSuccessor(TargetBB)) {
187 
188  // Transform the code
189  //
190  // brCC L1
191  // ba L2
192  // L1:
193  // ..
194  // L2:
195  //
196  // into
197  //
198  // brnCC L2
199  // L1:
200  // ...
201  // L2:
202  //
203  BranchCode = GetOppositeBranchCondition(BranchCode);
204  MachineBasicBlock::iterator OldInst = I;
205  BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(Opcode))
206  .addMBB(UnCondBrIter->getOperand(0).getMBB()).addImm(BranchCode);
207  BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(SP::BA))
208  .addMBB(TargetBB);
209 
210  OldInst->eraseFromParent();
211  UnCondBrIter->eraseFromParent();
212 
213  UnCondBrIter = MBB.end();
214  I = MBB.end();
215  continue;
216  }
217  FBB = TBB;
218  TBB = I->getOperand(0).getMBB();
219  Cond.push_back(MachineOperand::CreateImm(BranchCode));
220  continue;
221  }
222  // FIXME: Handle subsequent conditional branches.
223  // For now, we can't handle multiple conditional branches.
224  return true;
225  }
226  return false;
227 }
228 
229 unsigned
231  MachineBasicBlock *FBB,
233  DebugLoc DL) const {
234  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
235  assert((Cond.size() == 1 || Cond.size() == 0) &&
236  "Sparc branch conditions should have one component!");
237 
238  if (Cond.empty()) {
239  assert(!FBB && "Unconditional branch with multiple successors!");
240  BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);
241  return 1;
242  }
243 
244  // Conditional branch
245  unsigned CC = Cond[0].getImm();
246 
247  if (IsIntegerCC(CC))
248  BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC);
249  else
250  BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC);
251  if (!FBB)
252  return 1;
253 
254  BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB);
255  return 2;
256 }
257 
259 {
261  unsigned Count = 0;
262  while (I != MBB.begin()) {
263  --I;
264 
265  if (I->isDebugValue())
266  continue;
267 
268  if (I->getOpcode() != SP::BA
269  && I->getOpcode() != SP::BCOND
270  && I->getOpcode() != SP::FBCOND)
271  break; // Not a branch
272 
273  I->eraseFromParent();
274  I = MBB.end();
275  ++Count;
276  }
277  return Count;
278 }
279 
282  unsigned DestReg, unsigned SrcReg,
283  bool KillSrc) const {
284  unsigned numSubRegs = 0;
285  unsigned movOpc = 0;
286  const unsigned *subRegIdx = nullptr;
287 
288  const unsigned DFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd };
289  const unsigned QFP_DFP_SubRegsIdx[] = { SP::sub_even64, SP::sub_odd64 };
290  const unsigned QFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd,
291  SP::sub_odd64_then_sub_even,
292  SP::sub_odd64_then_sub_odd };
293 
294  if (SP::IntRegsRegClass.contains(DestReg, SrcReg))
295  BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0)
296  .addReg(SrcReg, getKillRegState(KillSrc));
297  else if (SP::FPRegsRegClass.contains(DestReg, SrcReg))
298  BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
299  .addReg(SrcReg, getKillRegState(KillSrc));
300  else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) {
301  if (Subtarget.isV9()) {
302  BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg)
303  .addReg(SrcReg, getKillRegState(KillSrc));
304  } else {
305  // Use two FMOVS instructions.
306  subRegIdx = DFP_FP_SubRegsIdx;
307  numSubRegs = 2;
308  movOpc = SP::FMOVS;
309  }
310  } else if (SP::QFPRegsRegClass.contains(DestReg, SrcReg)) {
311  if (Subtarget.isV9()) {
312  if (Subtarget.hasHardQuad()) {
313  BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg)
314  .addReg(SrcReg, getKillRegState(KillSrc));
315  } else {
316  // Use two FMOVD instructions.
317  subRegIdx = QFP_DFP_SubRegsIdx;
318  numSubRegs = 2;
319  movOpc = SP::FMOVD;
320  }
321  } else {
322  // Use four FMOVS instructions.
323  subRegIdx = QFP_FP_SubRegsIdx;
324  numSubRegs = 4;
325  movOpc = SP::FMOVS;
326  }
327  } else if (SP::ASRRegsRegClass.contains(DestReg) &&
328  SP::IntRegsRegClass.contains(SrcReg)) {
329  BuildMI(MBB, I, DL, get(SP::WRASRrr), DestReg)
330  .addReg(SP::G0)
331  .addReg(SrcReg, getKillRegState(KillSrc));
332  } else if (SP::IntRegsRegClass.contains(DestReg) &&
333  SP::ASRRegsRegClass.contains(SrcReg)) {
334  BuildMI(MBB, I, DL, get(SP::RDASR), DestReg)
335  .addReg(SrcReg, getKillRegState(KillSrc));
336  } else
337  llvm_unreachable("Impossible reg-to-reg copy");
338 
339  if (numSubRegs == 0 || subRegIdx == nullptr || movOpc == 0)
340  return;
341 
342  const TargetRegisterInfo *TRI = &getRegisterInfo();
343  MachineInstr *MovMI = nullptr;
344 
345  for (unsigned i = 0; i != numSubRegs; ++i) {
346  unsigned Dst = TRI->getSubReg(DestReg, subRegIdx[i]);
347  unsigned Src = TRI->getSubReg(SrcReg, subRegIdx[i]);
348  assert(Dst && Src && "Bad sub-register");
349 
350  MovMI = BuildMI(MBB, I, DL, get(movOpc), Dst).addReg(Src);
351  }
352  // Add implicit super-register defs and kills to the last MovMI.
353  MovMI->addRegisterDefined(DestReg, TRI);
354  if (KillSrc)
355  MovMI->addRegisterKilled(SrcReg, TRI);
356 }
357 
358 void SparcInstrInfo::
360  unsigned SrcReg, bool isKill, int FI,
361  const TargetRegisterClass *RC,
362  const TargetRegisterInfo *TRI) const {
363  DebugLoc DL;
364  if (I != MBB.end()) DL = I->getDebugLoc();
365 
366  MachineFunction *MF = MBB.getParent();
367  const MachineFrameInfo &MFI = *MF->getFrameInfo();
368  MachineMemOperand *MMO =
371  MFI.getObjectSize(FI),
372  MFI.getObjectAlignment(FI));
373 
374  // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
375  if (RC == &SP::I64RegsRegClass)
376  BuildMI(MBB, I, DL, get(SP::STXri)).addFrameIndex(FI).addImm(0)
377  .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
378  else if (RC == &SP::IntRegsRegClass)
379  BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0)
380  .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
381  else if (RC == &SP::FPRegsRegClass)
382  BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0)
383  .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
384  else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
385  BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0)
386  .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
387  else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
388  // Use STQFri irrespective of its legality. If STQ is not legal, it will be
389  // lowered into two STDs in eliminateFrameIndex.
390  BuildMI(MBB, I, DL, get(SP::STQFri)).addFrameIndex(FI).addImm(0)
391  .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
392  else
393  llvm_unreachable("Can't store this register to stack slot");
394 }
395 
396 void SparcInstrInfo::
398  unsigned DestReg, int FI,
399  const TargetRegisterClass *RC,
400  const TargetRegisterInfo *TRI) const {
401  DebugLoc DL;
402  if (I != MBB.end()) DL = I->getDebugLoc();
403 
404  MachineFunction *MF = MBB.getParent();
405  const MachineFrameInfo &MFI = *MF->getFrameInfo();
406  MachineMemOperand *MMO =
409  MFI.getObjectSize(FI),
410  MFI.getObjectAlignment(FI));
411 
412  if (RC == &SP::I64RegsRegClass)
413  BuildMI(MBB, I, DL, get(SP::LDXri), DestReg).addFrameIndex(FI).addImm(0)
414  .addMemOperand(MMO);
415  else if (RC == &SP::IntRegsRegClass)
416  BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0)
417  .addMemOperand(MMO);
418  else if (RC == &SP::FPRegsRegClass)
419  BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0)
420  .addMemOperand(MMO);
421  else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
422  BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0)
423  .addMemOperand(MMO);
424  else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
425  // Use LDQFri irrespective of its legality. If LDQ is not legal, it will be
426  // lowered into two LDDs in eliminateFrameIndex.
427  BuildMI(MBB, I, DL, get(SP::LDQFri), DestReg).addFrameIndex(FI).addImm(0)
428  .addMemOperand(MMO);
429  else
430  llvm_unreachable("Can't load this register from stack slot");
431 }
432 
434 {
436  unsigned GlobalBaseReg = SparcFI->getGlobalBaseReg();
437  if (GlobalBaseReg != 0)
438  return GlobalBaseReg;
439 
440  // Insert the set of GlobalBaseReg into the first MBB of the function
441  MachineBasicBlock &FirstMBB = MF->front();
442  MachineBasicBlock::iterator MBBI = FirstMBB.begin();
443  MachineRegisterInfo &RegInfo = MF->getRegInfo();
444 
445  const TargetRegisterClass *PtrRC =
446  Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
447  GlobalBaseReg = RegInfo.createVirtualRegister(PtrRC);
448 
449  DebugLoc dl;
450 
451  BuildMI(FirstMBB, MBBI, dl, get(SP::GETPCX), GlobalBaseReg);
452  SparcFI->setGlobalBaseReg(GlobalBaseReg);
453  return GlobalBaseReg;
454 }
The memory access reads data.
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
The memory access writes data.
unsigned RemoveBranch(MachineBasicBlock &MBB) const override
unsigned getGlobalBaseReg(MachineFunction *MF) const
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
A debug info location.
Definition: DebugLoc.h:34
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, unsigned f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
getMachineMemOperand - Allocate a new MachineMemOperand.
static MachinePointerInfo getFixedStack(int FI, int64_t offset=0)
getFixedStack - Return a MachinePointerInfo record that refers to the the specified FrameIndex...
GlobalBaseReg - On Darwin, this node represents the result of the mflr at function entry...
void eraseFromParent()
eraseFromParent - This method unlinks 'this' from the containing function and deletes it...
MachineMemOperand - A description of a memory reference used in the backend.
unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const override
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot...
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APInt.h:33
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Definition: Value.cpp:317
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
static bool IsIntegerCC(unsigned CC)
const MachineBasicBlock & front() const
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Definition: SmallVector.h:57
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: ArrayRef.h:31
int64_t getImm() const
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:134
const SparcRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
unsigned getKillRegState(bool B)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:267
bundle_iterator< MachineInstr, instr_iterator > iterator
DebugLoc findDebugLoc(instr_iterator MBBI)
findDebugLoc - find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE instructions...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot...
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:129
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool hasHardQuad() const
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const MachineInstrBuilder & addFrameIndex(int Idx) const
void addRegisterDefined(unsigned Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, DebugLoc DL) const override
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:51
static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC)
CondCodes
Definition: Sparc.h:42
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
SparcInstrInfo(SparcSubtarget &ST)
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
static MachineOperand CreateImm(int64_t Val)
#define I(x, y, z)
Definition: MD5.cpp:54
bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
unsigned getReg() const
getReg - Returns the register number.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
bool isV9() const
bool is64Bit() const
bool addRegisterKilled(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
isLayoutSuccessor - Return true if the specified MBB will be emitted immediately after this block...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.