15 #ifndef LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
16 #define LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
25 class X86TargetMachine;
575 bool hasSymbolicDisplacement =
true);
581 bool is64Bit,
bool IsVarArg,
bool TailCallOpt);
618 unsigned JTI,
MCContext &Ctx)
const override;
639 bool IsMemset,
bool ZeroMemset,
bool MemcpyStrSrc,
653 bool *
Fast)
const override;
694 EVT VT)
const override;
702 unsigned Depth = 0)
const override;
707 unsigned Depth)
const override;
710 int64_t &Offset)
const override;
722 const char *constraint)
const override;
730 std::string &Constraint,
731 std::vector<SDValue> &Ops,
736 if (ConstraintCode ==
"i")
738 else if (ConstraintCode ==
"o")
740 else if (ConstraintCode ==
"v")
742 else if (ConstraintCode ==
"X")
751 std::pair<unsigned, const TargetRegisterClass *>
758 Type *Ty,
unsigned AS)
const override;
778 unsigned AS)
const override;
826 EVT VT)
const override;
832 EVT VT)
const override;
841 return !X86ScalarSSEf64 || VT ==
MVT::f80;
847 EVT NewVT)
const override;
852 return (VT ==
MVT::f64 && X86ScalarSSEf64) ||
853 (VT ==
MVT::f32 && X86ScalarSSEf32);
868 Type *Ty)
const override;
891 unsigned &Offset)
const override;
903 std::pair<const TargetRegisterClass *, uint8_t>
905 MVT VT)
const override;
916 bool X86ScalarSSEf32;
917 bool X86ScalarSSEf64;
920 std::vector<APFloat> LegalFPImmediates;
924 void addLegalFPImmediate(
const APFloat& Imm) {
925 LegalFPImmediates.push_back(Imm);
928 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
930 const SmallVectorImpl<ISD::InputArg> &
Ins,
931 SDLoc dl, SelectionDAG &DAG,
932 SmallVectorImpl<SDValue> &InVals)
const;
933 SDValue LowerMemArgument(SDValue Chain,
935 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
936 SDLoc dl, SelectionDAG &DAG,
937 const CCValAssign &VA, MachineFrameInfo *MFI,
939 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
940 SDLoc dl, SelectionDAG &DAG,
941 const CCValAssign &VA,
942 ISD::ArgFlagsTy
Flags)
const;
948 bool IsEligibleForTailCallOptimization(SDValue Callee,
951 bool isCalleeStructRet,
952 bool isCallerStructRet,
954 const SmallVectorImpl<ISD::OutputArg> &Outs,
955 const SmallVectorImpl<SDValue> &OutVals,
956 const SmallVectorImpl<ISD::InputArg> &
Ins,
957 SelectionDAG& DAG)
const;
959 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
960 SDValue Chain,
bool IsTailCall,
bool Is64Bit,
961 int FPDiff, SDLoc dl)
const;
963 unsigned GetAlignedArgumentStackSize(
unsigned StackSize,
964 SelectionDAG &DAG)
const;
966 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
968 bool isReplace)
const;
970 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG)
const;
971 SDValue LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG)
const;
972 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG)
const;
973 SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG)
const;
974 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG)
const;
975 SDValue ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG)
const;
976 SDValue InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG)
const;
978 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG)
const;
979 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG)
const;
980 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG)
const;
981 SDValue LowerGlobalAddress(
const GlobalValue *GV, SDLoc dl,
982 int64_t Offset, SelectionDAG &DAG)
const;
983 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG)
const;
984 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG)
const;
985 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG)
const;
986 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG)
const;
987 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG)
const;
988 SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG)
const;
989 SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG)
const;
990 SDValue lowerUINT_TO_FP_vec(SDValue Op, SelectionDAG &DAG)
const;
991 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG)
const;
992 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG)
const;
993 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG)
const;
995 SDLoc dl, SelectionDAG &DAG)
const;
996 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG)
const;
997 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG)
const;
998 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG)
const;
999 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG)
const;
1000 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG)
const;
1001 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG)
const;
1002 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG)
const;
1003 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG)
const;
1004 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG)
const;
1005 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG)
const;
1006 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG)
const;
1007 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
const;
1008 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG)
const;
1009 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG)
const;
1010 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG)
const;
1011 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG)
const;
1012 SDValue LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG)
const;
1013 SDValue LowerGC_TRANSITION_START(SDValue Op, SelectionDAG &DAG)
const;
1014 SDValue LowerGC_TRANSITION_END(SDValue Op, SelectionDAG &DAG)
const;
1017 LowerFormalArguments(SDValue Chain,
1019 const SmallVectorImpl<ISD::InputArg> &
Ins,
1020 SDLoc dl, SelectionDAG &DAG,
1021 SmallVectorImpl<SDValue> &InVals)
const override;
1022 SDValue LowerCall(CallLoweringInfo &CLI,
1023 SmallVectorImpl<SDValue> &InVals)
const override;
1025 SDValue LowerReturn(SDValue Chain,
1027 const SmallVectorImpl<ISD::OutputArg> &Outs,
1028 const SmallVectorImpl<SDValue> &OutVals,
1029 SDLoc dl, SelectionDAG &DAG)
const override;
1031 bool isUsedByReturnOnly(SDNode *
N, SDValue &Chain)
const override;
1033 bool mayBeEmittedAsTailCall(CallInst *CI)
const override;
1035 EVT getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1040 const SmallVectorImpl<ISD::OutputArg> &Outs,
1041 LLVMContext &Context)
const override;
1045 bool shouldExpandAtomicLoadInIR(LoadInst *
SI)
const override;
1046 bool shouldExpandAtomicStoreInIR(StoreInst *
SI)
const override;
1048 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI)
const override;
1051 lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI)
const override;
1053 bool needsCmpXchgNb(
const Type *MemType)
const;
1059 MachineBasicBlock *EmitAtomicLoadArith(MachineInstr *
MI,
1060 MachineBasicBlock *MBB)
const;
1064 MachineBasicBlock *EmitAtomicLoadArith6432(MachineInstr *
MI,
1065 MachineBasicBlock *MBB)
const;
1068 MachineBasicBlock *EmitVAARG64WithCustomInserter(
1070 MachineBasicBlock *MBB)
const;
1073 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter(
1074 MachineInstr *BInstr,
1075 MachineBasicBlock *BB)
const;
1077 MachineBasicBlock *EmitLoweredSelect(MachineInstr *
I,
1078 MachineBasicBlock *BB)
const;
1080 MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *
MI,
1081 MachineBasicBlock *BB)
const;
1083 MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *
MI,
1084 MachineBasicBlock *BB)
const;
1086 MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *
MI,
1087 MachineBasicBlock *BB)
const;
1089 MachineBasicBlock *emitLoweredTLSAddr(MachineInstr *
MI,
1090 MachineBasicBlock *BB)
const;
1092 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *
MI,
1093 MachineBasicBlock *MBB)
const;
1095 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *
MI,
1096 MachineBasicBlock *MBB)
const;
1098 MachineBasicBlock *emitFMA3Instr(MachineInstr *
MI,
1099 MachineBasicBlock *MBB)
const;
1103 SDValue EmitTest(SDValue Op0,
unsigned X86CC, SDLoc dl,
1104 SelectionDAG &DAG)
const;
1108 SDValue EmitCmp(SDValue Op0, SDValue Op1,
unsigned X86CC, SDLoc dl,
1109 SelectionDAG &DAG)
const;
1112 SDValue ConvertCmpIfNecessary(SDValue Cmp, SelectionDAG &DAG)
const;
1115 SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI,
1116 unsigned &RefinementSteps,
1117 bool &UseOneConstNR)
const override;
1120 SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI,
1121 unsigned &RefinementSteps)
const override;
1124 bool combineRepeatedFPDivisors(
unsigned NumUsers)
const override;
1129 const TargetLibraryInfo *libInfo);
1133 #endif // X86ISELLOWERING_H
bool isVINSERT128Index(SDNode *N)
Return true if the specified INSERT_SUBVECTOR operand specifies a subvector insert that is suitable f...
Double shift instructions.
const MCExpr * getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const override
This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase, but as an MCExpr.
Floating point horizontal sub.
BUILTIN_OP_END - This must be the last enum value in this list.
A parsed version of the target data layout string in and methods for querying it. ...
Vector comparison generating mask bits for fp and integer signed and unsigned data types...
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
Provide custom lowering hooks for some operations.
bool isVectorLoadExtDesirable(SDValue) const override
Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable...
Repeat move, corresponds to X86::REP_MOVSx.
void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
X86TargetLowering(const X86TargetMachine &TM, const X86Subtarget &STI)
Return with a flag operand.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
bool isVectorClearMaskLegal(const SmallVectorImpl< int > &Mask, EVT VT) const override
Similar to isShuffleMaskLegal.
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
bool isVEXTRACT128Index(SDNode *N)
Return true if the specified EXTRACT_SUBVECTOR operand specifies a vector extract that is suitable fo...
const char * LowerXConstraint(EVT ConstraintVT) const override
LowerXConstraint - try to replace an X constraint, which matches anything, with another that has more...
X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values, result in an integer GPR...
CallInst - This class represents a function call, abstracting a target machine's calling convention...
bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const override
Return true if the target has native support for the specified value type and it is 'desirable' to us...
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned uid, MCContext &Ctx) const override
unsigned getInsertVINSERT128Immediate(SDNode *N)
Return the appropriate immediate to insert at the specified INSERT_SUBVECTOR index with VINSERTF128...
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
SSE4A Extraction and Insertion.
bool isLegalICmpImmediate(int64_t Imm) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
Bitwise logical ANDNOT of floating point values.
bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const override
Return true if the target stores stack protector cookies at a fixed offset in some non-standard addre...
This operation implements the lowering for readcyclecounter.
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const override
Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index.
X86 compare and logical compare instructions.
AtomicRMWExpansionKind
Enum that specifies what a AtomicRMWInst is expanded to, if at all.
Extract an 8-bit value from a vector and zero extend it to i32, corresponds to X86::PEXTRB.
Bitwise Logical AND NOT of Packed FP values.
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const override
Return true if we believe it is correct and profitable to reduce the load node to a smaller type...
bool isVINSERT256Index(SDNode *N)
Return true if the specified INSERT_SUBVECTOR operand specifies a subvector insert that is suitable f...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Base class for the full range of assembler expressions which are needed for parsing.
int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override
Return the cost of the scaling factor used in the addressing mode represented by AM for this target...
This instruction implements SINT_TO_FP with the integer source in memory and FP reg result...
unsigned getExtractVEXTRACT128Immediate(SDNode *N)
Return the appropriate immediate to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Copies a 64-bit value from the low word of an XMM vector to an MMX vector.
Context object for machine code objects.
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Copies a 32-bit value from the low word of a MMX vector to a GPR.
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
bool isCheapToSpeculateCttz() const override
Return true if it is cheap to speculate a call to intrinsic cttz.
bool isSafeMemOpType(MVT VT) const override
Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline...
bool isIntegerTypeFTOL(EVT VT) const
Return true if the MSVC _ftol2 routine should be used for fptoui to the given type.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
Floating point horizontal add.
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align, bool *Fast) const override
Returns true if the target allows unaligned memory accesses of the specified type.
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
This method returns a target specific FastISel object, or null if the target does not support "fast" ...
Bitwise logical XOR of floating point values.
unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const override
Return the desired alignment for ByVal aggregate function arguments in the caller parameter area...
A self-contained host- and target-independent arbitrary-precision floating-point software implementat...
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the value type to use for ISD::SETCC.
unsigned getJumpTableEncoding() const override
Return the entry encoding for a jump table in the current function.
MVT - Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
Return true if it's free to truncate a value of type Ty1 to type Ty2.
This instruction implements an extending load to FP stack slots.
This is an important class for using LLVM in a threaded context.
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target...
EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, MachineFunction &MF) const override
Returns the target specific optimal type for load and store operations as a result of memset...
Insert any element of a 4 x float vector into any element of a destination 4 x floatvector.
Repeat fill, corresponds to X86::REP_STOSx.
static bool is64Bit(const char *name)
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
X86 conditional branches.
Insert the lower 16-bits of a 32-bit value to a vector, corresponds to X86::PINSRW.
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Commutative FMIN and FMAX.
On Darwin, this node represents the result of the popl at function entry, used for PIC code...
bool isLegalAddImmediate(int64_t Imm) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot, SelectionDAG &DAG) const
EVT - Extended Value Type.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
bool ExpandInlineAsm(CallInst *CI) const override
This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to...
Windows x64, Windows Itanium (IA-64)
bool isVEXTRACT256Index(SDNode *N)
Return true if the specified EXTRACT_SUBVECTOR operand specifies a vector extract that is suitable fo...
These operations represent an abstract X86 call instruction, which includes a bunch of information...
Floating point max and min.
bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override
Return true if the target has native support for the specified value type and it is 'desirable' to us...
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Copies a GPR into the low 32-bit word of a MMX vector and zero out the high word. ...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
Provides information about what library functions are available for the current target.
X86 Read Time-Stamp Counter and Processor ID.
bool isGAPlusOffset(SDNode *N, const GlobalValue *&GA, int64_t &Offset) const override
isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + o...
bool isShuffleMaskLegal(const SmallVectorImpl< int > &Mask, EVT VT) const override
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks.
bool isNarrowingProfitable(EVT VT1, EVT VT2) const override
Return true if it's profitable to narrow operations of type VT1 to VT2.
unsigned getExtractVEXTRACT256Immediate(SDNode *N)
Return the appropriate immediate to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64X4...
Floating point reciprocal-sqrt and reciprocal approximation.
bool useSoftFloat() const override
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Represents one node in the SelectionDAG.
X86 bit-test instructions.
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
Class for arbitrary precision integers.
bool isFPImmLegal(const APFloat &Imm, EVT VT) const override
Returns true if the target can instruction select the specified FP immediate natively.
AddrMode
ARM Addressing Modes.
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Returns true if it is beneficial to convert a load of a constant to just the constant itself...
This instruction implements FP_TO_SINT with the integer destination in memory and a FP reg source...
const char * getClearCacheBuiltinName() const override
Intel processors have a unified instruction and data cache.
APInt And(const APInt &LHS, const APInt &RHS)
Bitwise AND function for APInt.
bool ShouldShrinkFPConstant(EVT VT) const override
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
Representation of each machine instruction.
std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const override
Return the largest legal super-reg register class of the register class for the specified type and it...
unsigned getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const override
Return the register ID of the name passed in.
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
Replace the results of node with an illegal result type with new values built out of custom code...
SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const
Insert the lower 8-bits of a 32-bit value to a vector, corresponds to X86::PINSRB.
bool isTargetFTOL() const
Return true if the target uses the MSVC _ftol2 routine for fptoui.
A wrapper node for TargetConstantPool, TargetExternalSymbol, and TargetGlobalAddress.
Bitwise logical AND of floating point values.
Fast - This calling convention attempts to make calls as fast as possible (e.g.
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
LegalizeTypeAction getPreferredVectorAction(EVT VT) const override
Customize the preferred legalization strategy for certain types.
STATIC_ROUNDING
AVX512 static rounding constants.
bool isFMAFasterThanFMulAndFAdd(EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
Extract a 16-bit value from a vector and zero extend it to i32, corresponds to X86::PEXTRW.
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
unsigned getInsertVINSERT256Immediate(SDNode *N)
Return the appropriate immediate to insert at the specified INSERT_SUBVECTOR index with VINSERTF64x4...
Blend where the selector is an immediate.
bool isCalleePop(CallingConv::ID CallingConv, bool is64Bit, bool IsVarArg, bool TailCallOpt)
Determines whether the callee is required to pop its own arguments.
bool useLoadStackGuardNode() const override
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const SelectionDAG &DAG, unsigned Depth) const override
Determine the number of bits in the operation that are sign bits.
This instruction implements a truncating store to FP stack slots.
Combined add and sub on an FP vector.
This instruction grabs the address of the next argument from a va_list.
Bitwise logical OR of floating point values.
bool isZExtFree(Type *Ty1, Type *Ty2) const override
Return true if any actual instruction that defines a value of type Ty1 implicit zero-extends the valu...
Blend where the condition has been shrunk.
X86 Read Performance Monitoring Counters.
bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override
Return true if a truncation from Ty1 to Ty2 is permitted when deciding whether a call is in tail posi...
bool isZeroNode(SDValue Elt)
Returns true if Elt is a constant zero or floating point constant +0.0.
StringRef - Represent a constant reference to a string, i.e.
bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, bool hasSymbolicDisplacement=true)
Returns true of the given offset can be fit into displacement field of the instruction.
bool isVectorShiftByScalarCheap(Type *Ty) const override
Return true if it's significantly cheaper to shift a vector by a uniform scalar than by an amount whi...
Compute Sum of Absolute Differences.
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
bool isScalarFPTypeInSSEReg(EVT VT) const
Return true if the specified scalar FP type is computed in an SSE register, not on the X87 floating p...
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
Shuffle 16 8-bit values within a vector.
This file describes how to lower LLVM code to machine code.
Special wrapper used under X86-64 PIC mode for RIP relative displacements.