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LLVM
3.7.0
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#include <SIInstrInfo.h>
Static Public Member Functions | |
| static unsigned | getVALUOp (const MachineInstr &MI) |
Additional Inherited Members | |
Protected Member Functions inherited from llvm::AMDGPUInstrInfo | |
| MachineInstr * | foldMemoryOperandImpl (MachineFunction &MF, MachineInstr *MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex) const override |
| MachineInstr * | foldMemoryOperandImpl (MachineFunction &MF, MachineInstr *MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr *LoadMI) const override |
Protected Attributes inherited from llvm::AMDGPUInstrInfo | |
| const AMDGPUSubtarget & | ST |
Definition at line 25 of file SIInstrInfo.h.
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explicit |
Definition at line 30 of file SIInstrInfo.cpp.
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Definition at line 91 of file SIInstrInfo.cpp.
References llvm::dyn_cast(), findChainOperand(), llvm::SDNode::getMachineOpcode(), llvm::AMDGPU::getNamedOperandIdx(), getNumOperandsNoGlue(), llvm::SDNode::getOperand(), llvm::ConstantSDNode::getZExtValue(), isDS(), llvm::SDNode::isMachineOpcode(), isMTBUF(), isMUBUF(), isSMRD(), and nodesHaveSameOperandValue().
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Definition at line 1088 of file SIInstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::hasOrderedMemoryRef(), llvm::MachineInstr::hasUnmodeledSideEffects(), isDS(), isFLAT(), isMTBUF(), isMUBUF(), isSMRD(), llvm::MachineInstr::mayLoad(), and llvm::MachineInstr::mayStore().
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Build instruction(s) for an indirect register read.
Implements llvm::AMDGPUInstrInfo.
Definition at line 2714 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addOperand(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineBasicBlock::findDebugLoc(), llvm::AMDGPUInstrInfo::getIndirectIndexBegin(), and llvm::MachineBasicBlock::getParent().
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Build instruction(s) for an indirect register write.
Implements llvm::AMDGPUInstrInfo.
Definition at line 2696 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addOperand(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::RegState::Define, llvm::MachineBasicBlock::findDebugLoc(), llvm::AMDGPUInstrInfo::getIndirectIndexBegin(), and llvm::MachineBasicBlock::getParent().
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Build a MOV instruction.
Implements llvm::AMDGPUInstrInfo.
Definition at line 882 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), and llvm::MachineBasicBlock::findDebugLoc().
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Calculate the "Indirect Address" for the given RegIndex and Channel.
We model indirect addressing using a virtual address space that can be accesed with loads and stores. The "Indirect Address" is the memory address in this virtual address space that maps to the given RegIndex and Channel.
Implements llvm::AMDGPUInstrInfo.
Definition at line 2383 of file SIInstrInfo.cpp.
| unsigned SIInstrInfo::calculateLDSSpillAddress | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | MI, | ||
| RegScavenger * | RS, | ||
| unsigned | TmpReg, | ||
| unsigned | FrameOffset, | ||
| unsigned | Size | ||
| ) | const |
| @Offset | Offset in bytes of the FrameIndex being spilled |
Definition at line 576 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineBasicBlock::addLiveIn(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), ShaderType::COMPUTE, llvm::DL, llvm::RegScavenger::enterBasicBlock(), llvm::MachineBasicBlock::findDebugLoc(), llvm::SIRegisterInfo::findUnusedRegister(), llvm::MachineBasicBlock::front(), llvm::MachineFunction::front(), llvm::MachineFunction::getInfo(), llvm::SIMachineFunctionInfo::getMaximumWorkGroupSize(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::AMDGPUMachineFunction::getShaderType(), llvm::MachineFunction::getSubtarget(), llvm::SIMachineFunctionInfo::getTIDReg(), llvm::SIMachineFunctionInfo::hasCalculatedTID(), llvm::SIRegisterInfo::INPUT_PTR, llvm::MachineBasicBlock::isLiveIn(), llvm::AMDGPUMachineFunction::LDSSize, llvm::SI::KernelInputOffsets::NGROUPS_Y, llvm::SI::KernelInputOffsets::NGROUPS_Z, llvm::RegScavenger::scavengeRegister(), llvm::SIMachineFunctionInfo::setTIDReg(), llvm::AMDGPUInstrInfo::ST, llvm::SIRegisterInfo::TIDIG_X, llvm::SIRegisterInfo::TIDIG_Y, and llvm::SIRegisterInfo::TIDIG_Z.
| bool SIInstrInfo::canReadVGPR | ( | const MachineInstr & | MI, |
| unsigned | OpNo | ||
| ) | const |
OpNo to read a VGPR. Definition at line 1519 of file SIInstrInfo.cpp.
References llvm::TargetOpcode::COPY, llvm::MachineInstr::getOpcode(), getOpRegClass(), llvm::SIRegisterInfo::hasVGPRs(), llvm::TargetOpcode::INSERT_SUBREG, llvm::TargetOpcode::PHI, and llvm::TargetOpcode::REG_SEQUENCE.
Referenced by moveToVALU().
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Definition at line 767 of file SIInstrInfo.cpp.
References llvm::MachineOperand::ChangeToImmediate(), llvm::MachineOperand::ChangeToRegister(), llvm::TargetInstrInfo::commuteInstruction(), commuteOpcode(), llvm::MachineOperand::getImm(), getNamedOperand(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isImm(), isOperandLegal(), llvm::MachineOperand::isReg(), isVOP2(), isVOP3(), llvm_unreachable, llvm::AArch64CC::MI, llvm::MachineInstr::setDesc(), llvm::MachineOperand::setImm(), and llvm::MachineOperand::setSubReg().
Referenced by foldImmediates(), legalizeOperands(), and tryAddToFoldList().
| int SIInstrInfo::commuteOpcode | ( | const MachineInstr & | MI | ) | const |
Definition at line 442 of file SIInstrInfo.cpp.
References llvm::AMDGPU::getCommuteOrig(), llvm::AMDGPU::getCommuteRev(), llvm::MachineInstr::getOpcode(), and llvm::AMDGPUInstrInfo::pseudoToMCOpcode().
Referenced by commuteInstruction().
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Definition at line 1142 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addOperand(), llvm::BuildMI(), getNamedOperand(), llvm::MachineOperand::isImm(), and isInlineConstant().
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Definition at line 312 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), contains(), llvm::RegState::Define, llvm::getKillRegState(), llvm::RegState::Implicit, and llvm_unreachable.
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Definition at line 684 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::MachineInstrBuilder::addTargetIndex(), llvm::BuildMI(), llvm::RegState::Define, llvm::DL, llvm::MachineInstr::eraseFromParent(), llvm::AMDGPUInstrInfo::expandPostRAPseudo(), llvm::MachineBasicBlock::findDebugLoc(), llvm::MachineOperand::getImm(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::RegState::Implicit, llvm::MachineOperand::isFPImm(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), and llvm::AMDGPU::TI_CONSTDATA_START.
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Definition at line 847 of file SIInstrInfo.cpp.
References llvm::MachineInstr::getDesc(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), hasModifiersSet(), llvm::MCInstrDesc::isCommutable(), and llvm::MachineOperand::isReg().
Referenced by tryAddToFoldList().
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Definition at line 920 of file SIInstrInfo.cpp.
References llvm::MachineOperand::ChangeToImmediate(), llvm::MachineInstr::eraseFromParent(), llvm::MachineOperand::getImm(), getNamedOperand(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineOperand::getSubReg(), hasModifiersSet(), llvm::MachineRegisterInfo::hasOneNonDBGUse(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isKill(), llvm::MachineOperand::isReg(), llvm::SIRegisterInfo::isSGPRClass(), removeModOperands(), llvm::MachineInstr::RemoveOperand(), llvm::MachineInstr::setDesc(), llvm::MachineOperand::setIsKill(), llvm::MachineOperand::setReg(), llvm::MachineOperand::setSubReg(), and llvm::MachineInstr::untieRegOperand().
| uint64_t SIInstrInfo::getDefaultRsrcDataFormat | ( | ) | const |
Definition at line 2769 of file SIInstrInfo.cpp.
References llvm::AMDGPUSubtarget::getGeneration(), llvm::AMDGPUSubtarget::isAmdHsaOS(), llvm::AMDGPU::RSRC_DATA_FORMAT, llvm::AMDGPUInstrInfo::ST, and llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS.
Referenced by llvm::SITargetLowering::buildScratchRSRC(), legalizeOperands(), moveSMRDToVALU(), and llvm::SITargetLowering::wrapAddr64Rsrc().
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Implements llvm::AMDGPUInstrInfo.
Definition at line 2389 of file SIInstrInfo.cpp.
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Definition at line 145 of file SIInstrInfo.h.
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Definition at line 203 of file SIInstrInfo.cpp.
References addr, llvm::MachineOperand::getImm(), getNamedOperand(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineInstr::getOpcode(), getOpRegClass(), llvm::MachineOperand::getReg(), llvm::TargetRegisterClass::getSize(), isDS(), isMTBUF(), isMUBUF(), isSMRD(), isStride64(), llvm::MachineInstr::mayLoad(), and llvm::MachineInstr::mayStore().
| unsigned SIInstrInfo::getMovOpcode | ( | const TargetRegisterClass * | DstRC | ) | const |
Definition at line 462 of file SIInstrInfo.cpp.
References llvm::TargetOpcode::COPY, llvm::TargetRegisterClass::getSize(), and llvm::SIRegisterInfo::isSGPRClass().
| MachineOperand * SIInstrInfo::getNamedOperand | ( | MachineInstr & | MI, |
| unsigned | OperandName | ||
| ) | const |
Returns the operand named Op.
If MI does not have an operand named Op, this function returns nullptr.
Definition at line 2760 of file SIInstrInfo.cpp.
References llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineInstr::getOpcode(), and llvm::MachineInstr::getOperand().
Referenced by canShrink(), commuteInstruction(), convertToThreeAddress(), llvm::SIRegisterInfo::eliminateFrameIndex(), FoldImmediate(), getMemOpBaseRegImmOfs(), getNamedOperand(), hasModifiersSet(), legalizeOperands(), and splitSMRD().
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Definition at line 350 of file SIInstrInfo.h.
References getNamedOperand().
| const TargetRegisterClass * SIInstrInfo::getOpRegClass | ( | const MachineInstr & | MI, |
| unsigned | OpNo | ||
| ) | const |
Return the correct register class for OpNo.
For target-specific instructions, this will return the register class that has been defined in tablegen. For generic instructions, like REG_SEQUENCE it will return the register class of its machine operand. to infer the correct register class base on the other operands.
Definition at line 1502 of file SIInstrInfo.cpp.
References llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::SIRegisterInfo::getPhysRegClass(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::MachineInstr::isVariadic(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::MCInstrDesc::OpInfo, and llvm::MCOperandInfo::RegClass.
Referenced by canReadVGPR(), getMemOpBaseRegImmOfs(), getOpSize(), legalizeOperands(), and moveToVALU().
Return the size in bytes of the operand OpNo on the given.
Definition at line 267 of file SIInstrInfo.h.
References llvm::MCOI::OPERAND_IMMEDIATE, llvm::MCOperandInfo::OperandType, and llvm::MCOperandInfo::RegClass.
Referenced by foldImmediates(), isOperandLegal(), legalizeOperands(), and verifyInstruction().
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This form should usually be preferred since it handles operands with unknown register classes.
Definition at line 281 of file SIInstrInfo.h.
References getOpRegClass(), and llvm::TargetRegisterClass::getSize().
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Implements llvm::AMDGPUInstrInfo.
Definition at line 71 of file SIInstrInfo.h.
Referenced by foldImmediates().
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Definition at line 1441 of file SIInstrInfo.cpp.
References llvm::TargetOpcode::COPY, llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::TargetOpcode::INSERT_SUBREG, llvm::MachineOperand::isReg(), llvm::TargetOpcode::PHI, and llvm::TargetOpcode::REG_SEQUENCE.
Referenced by isSALUOpSupportedOnVALU(), moveSMRDToVALU(), and moveToVALU().
Return true if this instruction has any modifiers.
e.g. src[012]_mod, omod, clamp.
Definition at line 1276 of file SIInstrInfo.cpp.
References llvm::AMDGPU::getNamedOperandIdx().
| bool SIInstrInfo::hasModifiersSet | ( | const MachineInstr & | MI, |
| unsigned | OpName | ||
| ) | const |
Definition at line 1284 of file SIInstrInfo.cpp.
References llvm::MachineOperand::getImm(), and getNamedOperand().
Referenced by canShrink(), findCommutedOpIndices(), and FoldImmediate().
Return true if this 64-bit VALU instruction has a 32-bit encoding.
This function will return false if you pass it a 32-bit instruction.
Definition at line 1268 of file SIInstrInfo.cpp.
References llvm::AMDGPU::getVOPe32(), and llvm::AMDGPUInstrInfo::pseudoToMCOpcode().
| void SIInstrInfo::insertNOPs | ( | MachineBasicBlock::iterator | MI, |
| int | Count | ||
| ) | const |
Definition at line 670 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::BuildMI(), and llvm::AArch64CC::MI.
Referenced by llvm::SIRegisterInfo::eliminateFrameIndex().
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Definition at line 207 of file SIInstrInfo.h.
References llvm::DS.
Referenced by areLoadsFromSameBasePtr(), areMemAccessesTriviallyDisjoint(), getMemOpBaseRegImmOfs(), and shouldClusterLoads().
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Definition at line 215 of file SIInstrInfo.h.
References SIInstrFlags::FLAT.
Referenced by areMemAccessesTriviallyDisjoint().
| bool SIInstrInfo::isImmOperandLegal | ( | const MachineInstr * | MI, |
| unsigned | OpNo, | ||
| const MachineOperand & | MO | ||
| ) | const |
Definition at line 1249 of file SIInstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), isLiteralConstant(), llvm::MachineOperand::isTargetIndex(), llvm::SIRegisterInfo::opCanUseInlineConstant(), llvm::SIRegisterInfo::opCanUseLiteralConstant(), llvm::MCOI::OPERAND_IMMEDIATE, llvm::MCOperandInfo::OperandType, and llvm::MCOperandInfo::RegClass.
Referenced by llvm::SIRegisterInfo::eliminateFrameIndex(), and isOperandLegal().
Definition at line 1174 of file SIInstrInfo.cpp.
References llvm::DoubleToBits(), llvm::FloatToBits(), llvm::APInt::getBitWidth(), llvm::APInt::getSExtValue(), and llvm::APInt::getZExtValue().
Referenced by llvm::SITargetLowering::analyzeImmediate(), convertToThreeAddress(), isInlineConstant(), isLiteralConstant(), and llvm::SITargetLowering::shouldConvertConstantLoadToIntImm().
| bool SIInstrInfo::isInlineConstant | ( | const MachineOperand & | MO, |
| unsigned | OpSize | ||
| ) | const |
Definition at line 1213 of file SIInstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineOperand::isImm(), and isInlineConstant().
| bool SIInstrInfo::isLiteralConstant | ( | const MachineOperand & | MO, |
| unsigned | OpSize | ||
| ) | const |
Definition at line 1229 of file SIInstrInfo.cpp.
References llvm::MachineOperand::isImm(), and isInlineConstant().
Referenced by foldImmediates(), isImmOperandLegal(), legalizeOperands(), usesConstantBus(), and verifyInstruction().
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Definition at line 211 of file SIInstrInfo.h.
References SIInstrFlags::MIMG.
Referenced by llvm::SITargetLowering::AdjustInstrPostInstrSelection(), and llvm::SITargetLowering::PostISelFolding().
Implements llvm::AMDGPUInstrInfo.
Definition at line 890 of file SIInstrInfo.cpp.
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Definition at line 199 of file SIInstrInfo.h.
References SIInstrFlags::MTBUF.
Referenced by areLoadsFromSameBasePtr(), areMemAccessesTriviallyDisjoint(), getMemOpBaseRegImmOfs(), and shouldClusterLoads().
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Definition at line 195 of file SIInstrInfo.h.
References SIInstrFlags::MUBUF.
Referenced by areLoadsFromSameBasePtr(), areMemAccessesTriviallyDisjoint(), getMemOpBaseRegImmOfs(), and shouldClusterLoads().
| bool SIInstrInfo::isOperandLegal | ( | const MachineInstr * | MI, |
| unsigned | OpIdx, | ||
| const MachineOperand * | MO = nullptr |
||
| ) | const |
Check if MO is a legal operand if it was the OpIdx Operand for MI.
Definition at line 1646 of file SIInstrInfo.cpp.
References llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getOpSize(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::SIRegisterInfo::getPhysRegClass(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::TargetRegisterClass::getSize(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), isImmOperandLegal(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isTargetIndex(), isVALU(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::MCInstrDesc::Opcode, llvm::MCInstrDesc::OpInfo, llvm::MCOperandInfo::RegClass, and usesConstantBus().
Referenced by commuteInstruction(), legalizeOperands(), and tryAddToFoldList().
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Definition at line 77 of file SIInstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
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Definition at line 902 of file SIInstrInfo.cpp.
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Definition at line 151 of file SIInstrInfo.h.
References SIInstrFlags::SALU.
| bool SIInstrInfo::isSALUOpSupportedOnVALU | ( | const MachineInstr & | MI | ) | const |
Definition at line 1498 of file SIInstrInfo.cpp.
References getVALUOp().
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Definition at line 203 of file SIInstrInfo.h.
References SIInstrFlags::SMRD.
Referenced by areLoadsFromSameBasePtr(), areMemAccessesTriviallyDisjoint(), getMemOpBaseRegImmOfs(), moveToVALU(), and shouldClusterLoads().
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Definition at line 159 of file SIInstrInfo.h.
References SIInstrFlags::SOP1.
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Definition at line 163 of file SIInstrInfo.h.
References SIInstrFlags::SOP2.
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Definition at line 167 of file SIInstrInfo.h.
References SIInstrFlags::SOPC.
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Definition at line 171 of file SIInstrInfo.h.
References SIInstrFlags::SOPK.
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Definition at line 175 of file SIInstrInfo.h.
References SIInstrFlags::SOPP.
| bool SIInstrInfo::isTriviallyReMaterializable | ( | const MachineInstr * | MI, |
| AliasAnalysis * | AA = nullptr |
||
| ) | const |
Definition at line 1049 of file SIInstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::isImm().
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Definition at line 155 of file SIInstrInfo.h.
References SIInstrFlags::VALU.
Referenced by isOperandLegal().
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Definition at line 223 of file SIInstrInfo.h.
References SIInstrFlags::VGPRSpill.
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Definition at line 179 of file SIInstrInfo.h.
References SIInstrFlags::VOP1.
Referenced by foldImmediates(), and verifyInstruction().
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Definition at line 183 of file SIInstrInfo.h.
References SIInstrFlags::VOP2.
Referenced by commuteInstruction(), foldImmediates(), legalizeOperands(), and verifyInstruction().
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Definition at line 187 of file SIInstrInfo.h.
References SIInstrFlags::VOP3.
Referenced by commuteInstruction(), legalizeOperands(), and verifyInstruction().
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Definition at line 191 of file SIInstrInfo.h.
References SIInstrFlags::VOPC.
Referenced by foldImmediates(), and verifyInstruction().
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Definition at line 219 of file SIInstrInfo.h.
References SIInstrFlags::WQM.
| void SIInstrInfo::legalizeOperands | ( | MachineInstr * | MI | ) | const |
Legalize all operands in this instruction.
This function may create new instruction and insert them before MI.
Definition at line 1702 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addOperand(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), commuteInstruction(), llvm::TargetOpcode::COPY, llvm::MachineRegisterInfo::createVirtualRegister(), llvm::AMDGPU::getAddr64Inst(), llvm::MachineInstr::getDebugLoc(), getDefaultRsrcDataFormat(), llvm::SIRegisterInfo::getEquivalentVGPRClass(), llvm::MachineBasicBlock::getFirstTerminator(), llvm::MachineOperand::getMBB(), getNamedOperand(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getOpRegClass(), getOpSize(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::SIRegisterInfo::hasVGPRs(), llvm::RegState::Implicit, llvm::RegState::ImplicitDefine, llvm::TargetOpcode::INSERT_SUBREG, llvm::MachineInstr::isCommutable(), isLiteralConstant(), isOperandLegal(), llvm::MachineOperand::isReg(), llvm::SIRegisterInfo::isSGPRClass(), llvm::TargetRegisterInfo::isVirtualRegister(), isVOP2(), isVOP3(), legalizeOpWithMove(), llvm::AArch64CC::MI, llvm::TargetOpcode::PHI, llvm::TargetOpcode::REG_SEQUENCE, llvm::MachineInstr::removeFromParent(), and llvm::MachineOperand::setReg().
Referenced by llvm::SITargetLowering::AdjustInstrPostInstrSelection(), and moveToVALU().
| void SIInstrInfo::legalizeOpWithMove | ( | MachineInstr * | MI, |
| unsigned | OpIdx | ||
| ) | const |
Legalize the OpIndex operand of this instruction by inserting a MOV.
For example: ADD_I32_e32 VGPR0, 15 to MOV VGPR1, 15 ADD_I32_e32 VGPR0, VGPR1
If the operand being legalized is a register, then a COPY will be used instead of MOV.
Definition at line 1531 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addOperand(), llvm::BuildMI(), llvm::MachineOperand::ChangeToRegister(), llvm::TargetOpcode::COPY, llvm::MachineRegisterInfo::createVirtualRegister(), llvm::DL, llvm::MachineBasicBlock::findDebugLoc(), llvm::SIRegisterInfo::getEquivalentVGPRClass(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), I, llvm::MachineOperand::isReg(), llvm::SIRegisterInfo::isSGPRClass(), and llvm::AArch64CC::MI.
Referenced by legalizeOperands().
| void llvm::SIInstrInfo::LoadM0 | ( | MachineInstr * | MoveRel, |
| MachineBasicBlock::iterator | I, | ||
| unsigned | SavReg, | ||
| unsigned | IndexReg | ||
| ) | const |
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Definition at line 528 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::DL, llvm::LLVMContext::emitError(), llvm::MachineBasicBlock::findDebugLoc(), llvm::Function::getContext(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), llvm::MachineBasicBlock::getParent(), llvm::TargetRegisterClass::getSize(), llvm::SIRegisterInfo::hasVGPRs(), llvm::TargetOpcode::IMPLICIT_DEF, llvm::SIRegisterInfo::isSGPRClass(), llvm::AMDGPUSubtarget::isVGPRSpillingEnabled(), llvm::AMDGPUInstrInfo::ST, and llvm::RegState::Undef.
| void SIInstrInfo::moveSMRDToVALU | ( | MachineInstr * | MI, |
| MachineRegisterInfo & | MRI | ||
| ) | const |
Definition at line 2069 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstr::addOperand(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineOperand::ChangeToRegister(), llvm::MachineOperand::CreateImm(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MachineInstr::eraseFromParent(), llvm::MachineInstr::getDebugLoc(), getDefaultRsrcDataFormat(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getSubtarget(), getVALUOp(), llvm::MipsISD::Hi, llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), llvm::MipsISD::Lo, llvm::TargetOpcode::REG_SEQUENCE, llvm::MachineRegisterInfo::replaceRegWith(), llvm::AMDGPUSubtarget::SEA_ISLANDS, llvm::MachineInstr::setDesc(), llvm::MachineOperand::setReg(), and splitSMRD().
Referenced by moveToVALU().
| void SIInstrInfo::moveToVALU | ( | MachineInstr & | MI | ) | const |
Replace this instruction's opcode with the equivalent VALU opcode.
This function will also move the users of MI to the VALU if necessary.
Definition at line 2173 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addOperand(), llvm::MachineInstr::addOperand(), llvm::BuildMI(), canReadVGPR(), llvm::TargetOpcode::COPY, llvm::MachineOperand::CreateImm(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::SmallVectorBase::empty(), llvm::MachineInstr::eraseFromParent(), llvm::MachineInstr::getDebugLoc(), llvm::SIRegisterInfo::getEquivalentVGPRClass(), llvm::AMDGPUSubtarget::getGeneration(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getOpRegClass(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), getVALUOp(), llvm::SIRegisterInfo::hasVGPRs(), I, llvm::TargetOpcode::INSERT_SUBREG, llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), isSMRD(), legalizeOperands(), llvm_unreachable, moveSMRDToVALU(), llvm::TargetOpcode::PHI, llvm::SmallVectorImpl< T >::pop_back_val(), llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::TargetOpcode::REG_SEQUENCE, llvm::MachineInstr::RemoveOperand(), llvm::MachineRegisterInfo::replaceRegWith(), llvm::MachineInstr::setDesc(), llvm::AMDGPUInstrInfo::ST, llvm::MachineRegisterInfo::use_begin(), llvm::MachineRegisterInfo::use_end(), and llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS.
| void SIInstrInfo::reserveIndirectRegisters | ( | BitVector & | Reserved, |
| const MachineFunction & | MF | ||
| ) | const |
Definition at line 2732 of file SIInstrInfo.cpp.
References llvm::AMDGPUInstrInfo::getIndirectIndexBegin(), llvm::AMDGPUInstrInfo::getIndirectIndexEnd(), and llvm::BitVector::set().
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final |
Definition at line 289 of file SIInstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), isDS(), isMTBUF(), isMUBUF(), and isSMRD().
| void SIInstrInfo::splitSMRD | ( | MachineInstr * | MI, |
| const TargetRegisterClass * | HalfRC, | ||
| unsigned | HalfImmOp, | ||
| unsigned | HalfSGPROp, | ||
| MachineInstr *& | Lo, | ||
| MachineInstr *& | Hi | ||
| ) | const |
Split an SMRD instruction into two smaller loads of half the.
Definition at line 1975 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addOperand(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getImm(), llvm::getKillRegState(), getNamedOperand(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::TargetRegisterClass::getSize(), llvm::MachineOperand::getSubReg(), llvm::MachineFunction::getSubtarget(), llvm::MachineOperand::isKill(), llvm::isUInt< 8 >(), llvm_unreachable, llvm::TargetOpcode::REG_SEQUENCE, and llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS.
Referenced by moveSMRDToVALU().
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override |
Definition at line 474 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::DL, llvm::LLVMContext::emitError(), llvm::MachineBasicBlock::findDebugLoc(), llvm::Function::getContext(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), llvm::MachineBasicBlock::getParent(), llvm::TargetRegisterClass::getSize(), llvm::SIRegisterInfo::hasVGPRs(), llvm::SIRegisterInfo::isSGPRClass(), llvm::AMDGPUSubtarget::isVGPRSpillingEnabled(), llvm::TargetOpcode::KILL, llvm::SIMachineFunctionInfo::setHasSpilledVGPRs(), llvm::AMDGPUInstrInfo::ST, and llvm::RegState::Undef.
| bool SIInstrInfo::usesConstantBus | ( | const MachineRegisterInfo & | MRI, |
| const MachineOperand & | MO, | ||
| unsigned | OpSize | ||
| ) | const |
Returns true if this operand uses the constant bus.
Definition at line 1290 of file SIInstrInfo.cpp.
References contains(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineOperand::isImplicit(), isLiteralConstant(), llvm::MachineOperand::isReg(), llvm::SIRegisterInfo::isSGPRClass(), llvm::MachineOperand::isUse(), and llvm::TargetRegisterInfo::isVirtualRegister().
Referenced by isOperandLegal(), and verifyInstruction().
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override |
Definition at line 1322 of file SIInstrInfo.cpp.
References compareMachineOp(), llvm::TargetRegisterClass::contains(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineInstr::getNumExplicitOperands(), llvm::MCInstrDesc::getNumOperands(), llvm::MCInstrDesc::getOpcode(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getOpSize(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isFPImm(), llvm::MachineOperand::isImm(), isLiteralConstant(), llvm::MachineOperand::isReg(), llvm::MCInstrDesc::isVariadic(), llvm::TargetRegisterInfo::isVirtualRegister(), isVOP1(), isVOP2(), isVOP3(), isVOPC(), llvm::MCOI::OPERAND_IMMEDIATE, llvm::AMDGPU::OPERAND_REG_IMM32, llvm::AMDGPU::OPERAND_REG_INLINE_C, llvm::MCOI::OPERAND_REGISTER, llvm::MCOperandInfo::OperandType, llvm::MCInstrDesc::OpInfo, llvm::MCOperandInfo::RegClass, and usesConstantBus().
1.8.6