LLVM  3.7.0
MipsLongBranch.cpp
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1 //===-- MipsLongBranch.cpp - Emit long branches ---------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This pass expands a branch or jump instruction into a long branch if its
11 // offset is too large to fit into its immediate field.
12 //
13 // FIXME: Fix pc-region jump instructions which cross 256MB segment boundaries.
14 //===----------------------------------------------------------------------===//
15 
16 #include "Mips.h"
19 #include "MipsMachineFunction.h"
20 #include "MipsTargetMachine.h"
21 #include "llvm/ADT/Statistic.h"
24 #include "llvm/IR/Function.h"
30 
31 using namespace llvm;
32 
33 #define DEBUG_TYPE "mips-long-branch"
34 
35 STATISTIC(LongBranches, "Number of long branches.");
36 
38  "skip-mips-long-branch",
39  cl::init(false),
40  cl::desc("MIPS: Skip long branch pass."),
41  cl::Hidden);
42 
44  "force-mips-long-branch",
45  cl::init(false),
46  cl::desc("MIPS: Expand all branches to long format."),
47  cl::Hidden);
48 
49 namespace {
50  typedef MachineBasicBlock::iterator Iter;
51  typedef MachineBasicBlock::reverse_iterator ReverseIter;
52 
53  struct MBBInfo {
54  uint64_t Size, Address;
55  bool HasLongBranch;
56  MachineInstr *Br;
57 
58  MBBInfo() : Size(0), HasLongBranch(false), Br(nullptr) {}
59  };
60 
61  class MipsLongBranch : public MachineFunctionPass {
62 
63  public:
64  static char ID;
65  MipsLongBranch(TargetMachine &tm)
66  : MachineFunctionPass(ID), TM(tm),
67  IsPIC(TM.getRelocationModel() == Reloc::PIC_),
68  ABI(static_cast<const MipsTargetMachine &>(TM).getABI()) {}
69 
70  const char *getPassName() const override {
71  return "Mips Long Branch";
72  }
73 
74  bool runOnMachineFunction(MachineFunction &F) override;
75 
76  private:
77  void splitMBB(MachineBasicBlock *MBB);
78  void initMBBInfo();
79  int64_t computeOffset(const MachineInstr *Br);
80  void replaceBranch(MachineBasicBlock &MBB, Iter Br, DebugLoc DL,
81  MachineBasicBlock *MBBOpnd);
82  void expandToLongBranch(MBBInfo &Info);
83 
84  const TargetMachine &TM;
85  MachineFunction *MF;
86  SmallVector<MBBInfo, 16> MBBInfos;
87  bool IsPIC;
88  MipsABIInfo ABI;
89  unsigned LongBranchSeqSize;
90  };
91 
92  char MipsLongBranch::ID = 0;
93 } // end of anonymous namespace
94 
95 /// createMipsLongBranchPass - Returns a pass that converts branches to long
96 /// branches.
98  return new MipsLongBranch(tm);
99 }
100 
101 /// Iterate over list of Br's operands and search for a MachineBasicBlock
102 /// operand.
104  for (unsigned I = 0, E = Br.getDesc().getNumOperands(); I < E; ++I) {
105  const MachineOperand &MO = Br.getOperand(I);
106 
107  if (MO.isMBB())
108  return MO.getMBB();
109  }
110 
111  llvm_unreachable("This instruction does not have an MBB operand.");
112 }
113 
114 // Traverse the list of instructions backwards until a non-debug instruction is
115 // found or it reaches E.
116 static ReverseIter getNonDebugInstr(ReverseIter B, ReverseIter E) {
117  for (; B != E; ++B)
118  if (!B->isDebugValue())
119  return B;
120 
121  return E;
122 }
123 
124 // Split MBB if it has two direct jumps/branches.
125 void MipsLongBranch::splitMBB(MachineBasicBlock *MBB) {
126  ReverseIter End = MBB->rend();
127  ReverseIter LastBr = getNonDebugInstr(MBB->rbegin(), End);
128 
129  // Return if MBB has no branch instructions.
130  if ((LastBr == End) ||
131  (!LastBr->isConditionalBranch() && !LastBr->isUnconditionalBranch()))
132  return;
133 
134  ReverseIter FirstBr = getNonDebugInstr(std::next(LastBr), End);
135 
136  // MBB has only one branch instruction if FirstBr is not a branch
137  // instruction.
138  if ((FirstBr == End) ||
139  (!FirstBr->isConditionalBranch() && !FirstBr->isUnconditionalBranch()))
140  return;
141 
142  assert(!FirstBr->isIndirectBranch() && "Unexpected indirect branch found.");
143 
144  // Create a new MBB. Move instructions in MBB to the newly created MBB.
145  MachineBasicBlock *NewMBB =
146  MF->CreateMachineBasicBlock(MBB->getBasicBlock());
147 
148  // Insert NewMBB and fix control flow.
149  MachineBasicBlock *Tgt = getTargetMBB(*FirstBr);
150  NewMBB->transferSuccessors(MBB);
151  NewMBB->removeSuccessor(Tgt);
152  MBB->addSuccessor(NewMBB);
153  MBB->addSuccessor(Tgt);
154  MF->insert(std::next(MachineFunction::iterator(MBB)), NewMBB);
155 
156  NewMBB->splice(NewMBB->end(), MBB, (++LastBr).base(), MBB->end());
157 }
158 
159 // Fill MBBInfos.
160 void MipsLongBranch::initMBBInfo() {
161  // Split the MBBs if they have two branches. Each basic block should have at
162  // most one branch after this loop is executed.
163  for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E;)
164  splitMBB(I++);
165 
166  MF->RenumberBlocks();
167  MBBInfos.clear();
168  MBBInfos.resize(MF->size());
169 
170  const MipsInstrInfo *TII =
171  static_cast<const MipsInstrInfo *>(MF->getSubtarget().getInstrInfo());
172  for (unsigned I = 0, E = MBBInfos.size(); I < E; ++I) {
173  MachineBasicBlock *MBB = MF->getBlockNumbered(I);
174 
175  // Compute size of MBB.
177  MI != MBB->instr_end(); ++MI)
178  MBBInfos[I].Size += TII->GetInstSizeInBytes(&*MI);
179 
180  // Search for MBB's branch instruction.
181  ReverseIter End = MBB->rend();
182  ReverseIter Br = getNonDebugInstr(MBB->rbegin(), End);
183 
184  if ((Br != End) && !Br->isIndirectBranch() &&
185  (Br->isConditionalBranch() ||
186  (Br->isUnconditionalBranch() &&
187  TM.getRelocationModel() == Reloc::PIC_)))
188  MBBInfos[I].Br = (++Br).base();
189  }
190 }
191 
192 // Compute offset of branch in number of bytes.
193 int64_t MipsLongBranch::computeOffset(const MachineInstr *Br) {
194  int64_t Offset = 0;
195  int ThisMBB = Br->getParent()->getNumber();
196  int TargetMBB = getTargetMBB(*Br)->getNumber();
197 
198  // Compute offset of a forward branch.
199  if (ThisMBB < TargetMBB) {
200  for (int N = ThisMBB + 1; N < TargetMBB; ++N)
201  Offset += MBBInfos[N].Size;
202 
203  return Offset + 4;
204  }
205 
206  // Compute offset of a backward branch.
207  for (int N = ThisMBB; N >= TargetMBB; --N)
208  Offset += MBBInfos[N].Size;
209 
210  return -Offset + 4;
211 }
212 
213 // Replace Br with a branch which has the opposite condition code and a
214 // MachineBasicBlock operand MBBOpnd.
215 void MipsLongBranch::replaceBranch(MachineBasicBlock &MBB, Iter Br,
216  DebugLoc DL, MachineBasicBlock *MBBOpnd) {
217  const MipsInstrInfo *TII = static_cast<const MipsInstrInfo *>(
218  MBB.getParent()->getSubtarget().getInstrInfo());
219  unsigned NewOpc = TII->getOppositeBranchOpc(Br->getOpcode());
220  const MCInstrDesc &NewDesc = TII->get(NewOpc);
221 
222  MachineInstrBuilder MIB = BuildMI(MBB, Br, DL, NewDesc);
223 
224  for (unsigned I = 0, E = Br->getDesc().getNumOperands(); I < E; ++I) {
225  MachineOperand &MO = Br->getOperand(I);
226 
227  if (!MO.isReg()) {
228  assert(MO.isMBB() && "MBB operand expected.");
229  break;
230  }
231 
232  MIB.addReg(MO.getReg());
233  }
234 
235  MIB.addMBB(MBBOpnd);
236 
237  if (Br->hasDelaySlot()) {
238  // Bundle the instruction in the delay slot to the newly created branch
239  // and erase the original branch.
240  assert(Br->isBundledWithSucc());
242  MIBundleBuilder(&*MIB).append((++II)->removeFromBundle());
243  }
244  Br->eraseFromParent();
245 }
246 
247 // Expand branch instructions to long branches.
248 // TODO: This function has to be fixed for beqz16 and bnez16, because it
249 // currently assumes that all branches have 16-bit offsets, and will produce
250 // wrong code if branches whose allowed offsets are [-128, -126, ..., 126]
251 // are present.
252 void MipsLongBranch::expandToLongBranch(MBBInfo &I) {
254  MachineBasicBlock *MBB = I.Br->getParent(), *TgtMBB = getTargetMBB(*I.Br);
255  DebugLoc DL = I.Br->getDebugLoc();
256  const BasicBlock *BB = MBB->getBasicBlock();
258  MachineBasicBlock *LongBrMBB = MF->CreateMachineBasicBlock(BB);
259  const MipsSubtarget &Subtarget =
260  static_cast<const MipsSubtarget &>(MF->getSubtarget());
261  const MipsInstrInfo *TII =
262  static_cast<const MipsInstrInfo *>(Subtarget.getInstrInfo());
263 
264  MF->insert(FallThroughMBB, LongBrMBB);
265  MBB->removeSuccessor(TgtMBB);
266  MBB->addSuccessor(LongBrMBB);
267 
268  if (IsPIC) {
269  MachineBasicBlock *BalTgtMBB = MF->CreateMachineBasicBlock(BB);
270  MF->insert(FallThroughMBB, BalTgtMBB);
271  LongBrMBB->addSuccessor(BalTgtMBB);
272  BalTgtMBB->addSuccessor(TgtMBB);
273 
274  // We must select between the MIPS32r6/MIPS64r6 BAL (which is a normal
275  // instruction) and the pre-MIPS32r6/MIPS64r6 definition (which is an
276  // pseudo-instruction wrapping BGEZAL).
277  unsigned BalOp = Subtarget.hasMips32r6() ? Mips::BAL : Mips::BAL_BR;
278 
279  if (!ABI.IsN64()) {
280  // $longbr:
281  // addiu $sp, $sp, -8
282  // sw $ra, 0($sp)
283  // lui $at, %hi($tgt - $baltgt)
284  // bal $baltgt
285  // addiu $at, $at, %lo($tgt - $baltgt)
286  // $baltgt:
287  // addu $at, $ra, $at
288  // lw $ra, 0($sp)
289  // jr $at
290  // addiu $sp, $sp, 8
291  // $fallthrough:
292  //
293 
294  Pos = LongBrMBB->begin();
295 
296  BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
297  .addReg(Mips::SP).addImm(-8);
298  BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA)
299  .addReg(Mips::SP).addImm(0);
300 
301  // LUi and ADDiu instructions create 32-bit offset of the target basic
302  // block from the target of BAL instruction. We cannot use immediate
303  // value for this offset because it cannot be determined accurately when
304  // the program has inline assembly statements. We therefore use the
305  // relocation expressions %hi($tgt-$baltgt) and %lo($tgt-$baltgt) which
306  // are resolved during the fixup, so the values will always be correct.
307  //
308  // Since we cannot create %hi($tgt-$baltgt) and %lo($tgt-$baltgt)
309  // expressions at this point (it is possible only at the MC layer),
310  // we replace LUi and ADDiu with pseudo instructions
311  // LONG_BRANCH_LUi and LONG_BRANCH_ADDiu, and add both basic
312  // blocks as operands to these instructions. When lowering these pseudo
313  // instructions to LUi and ADDiu in the MC layer, we will create
314  // %hi($tgt-$baltgt) and %lo($tgt-$baltgt) expressions and add them as
315  // operands to lowered instructions.
316 
317  BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi), Mips::AT)
318  .addMBB(TgtMBB).addMBB(BalTgtMBB);
319  MIBundleBuilder(*LongBrMBB, Pos)
320  .append(BuildMI(*MF, DL, TII->get(BalOp)).addMBB(BalTgtMBB))
321  .append(BuildMI(*MF, DL, TII->get(Mips::LONG_BRANCH_ADDiu), Mips::AT)
322  .addReg(Mips::AT)
323  .addMBB(TgtMBB)
324  .addMBB(BalTgtMBB));
325 
326  Pos = BalTgtMBB->begin();
327 
328  BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::AT)
329  .addReg(Mips::RA).addReg(Mips::AT);
330  BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA)
331  .addReg(Mips::SP).addImm(0);
332 
333  if (!Subtarget.isTargetNaCl()) {
334  MIBundleBuilder(*BalTgtMBB, Pos)
335  .append(BuildMI(*MF, DL, TII->get(Mips::JR)).addReg(Mips::AT))
336  .append(BuildMI(*MF, DL, TII->get(Mips::ADDiu), Mips::SP)
337  .addReg(Mips::SP).addImm(8));
338  } else {
339  // In NaCl, modifying the sp is not allowed in branch delay slot.
340  BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
341  .addReg(Mips::SP).addImm(8);
342 
343  MIBundleBuilder(*BalTgtMBB, Pos)
344  .append(BuildMI(*MF, DL, TII->get(Mips::JR)).addReg(Mips::AT))
345  .append(BuildMI(*MF, DL, TII->get(Mips::NOP)));
346 
347  // Bundle-align the target of indirect branch JR.
348  TgtMBB->setAlignment(MIPS_NACL_BUNDLE_ALIGN);
349  }
350  } else {
351  // $longbr:
352  // daddiu $sp, $sp, -16
353  // sd $ra, 0($sp)
354  // daddiu $at, $zero, %hi($tgt - $baltgt)
355  // dsll $at, $at, 16
356  // bal $baltgt
357  // daddiu $at, $at, %lo($tgt - $baltgt)
358  // $baltgt:
359  // daddu $at, $ra, $at
360  // ld $ra, 0($sp)
361  // jr64 $at
362  // daddiu $sp, $sp, 16
363  // $fallthrough:
364  //
365 
366  // We assume the branch is within-function, and that offset is within
367  // +/- 2GB. High 32 bits will therefore always be zero.
368 
369  // Note that this will work even if the offset is negative, because
370  // of the +1 modification that's added in that case. For example, if the
371  // offset is -1MB (0xFFFFFFFFFFF00000), the computation for %higher is
372  //
373  // 0xFFFFFFFFFFF00000 + 0x80008000 = 0x000000007FF08000
374  //
375  // and the bits [47:32] are zero. For %highest
376  //
377  // 0xFFFFFFFFFFF00000 + 0x800080008000 = 0x000080007FF08000
378  //
379  // and the bits [63:48] are zero.
380 
381  Pos = LongBrMBB->begin();
382 
383  BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::SP_64)
384  .addReg(Mips::SP_64).addImm(-16);
385  BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SD)).addReg(Mips::RA_64)
386  .addReg(Mips::SP_64).addImm(0);
387  BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_DADDiu),
388  Mips::AT_64).addReg(Mips::ZERO_64)
389  .addMBB(TgtMBB, MipsII::MO_ABS_HI).addMBB(BalTgtMBB);
390  BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DSLL), Mips::AT_64)
391  .addReg(Mips::AT_64).addImm(16);
392 
393  MIBundleBuilder(*LongBrMBB, Pos)
394  .append(BuildMI(*MF, DL, TII->get(BalOp)).addMBB(BalTgtMBB))
395  .append(
396  BuildMI(*MF, DL, TII->get(Mips::LONG_BRANCH_DADDiu), Mips::AT_64)
397  .addReg(Mips::AT_64)
398  .addMBB(TgtMBB, MipsII::MO_ABS_LO)
399  .addMBB(BalTgtMBB));
400 
401  Pos = BalTgtMBB->begin();
402 
403  BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDu), Mips::AT_64)
404  .addReg(Mips::RA_64).addReg(Mips::AT_64);
405  BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LD), Mips::RA_64)
406  .addReg(Mips::SP_64).addImm(0);
407 
408  MIBundleBuilder(*BalTgtMBB, Pos)
409  .append(BuildMI(*MF, DL, TII->get(Mips::JR64)).addReg(Mips::AT_64))
410  .append(BuildMI(*MF, DL, TII->get(Mips::DADDiu), Mips::SP_64)
411  .addReg(Mips::SP_64).addImm(16));
412  }
413 
414  assert(LongBrMBB->size() + BalTgtMBB->size() == LongBranchSeqSize);
415  } else {
416  // $longbr:
417  // j $tgt
418  // nop
419  // $fallthrough:
420  //
421  Pos = LongBrMBB->begin();
422  LongBrMBB->addSuccessor(TgtMBB);
423  MIBundleBuilder(*LongBrMBB, Pos)
424  .append(BuildMI(*MF, DL, TII->get(Mips::J)).addMBB(TgtMBB))
425  .append(BuildMI(*MF, DL, TII->get(Mips::NOP)));
426 
427  assert(LongBrMBB->size() == LongBranchSeqSize);
428  }
429 
430  if (I.Br->isUnconditionalBranch()) {
431  // Change branch destination.
432  assert(I.Br->getDesc().getNumOperands() == 1);
433  I.Br->RemoveOperand(0);
434  I.Br->addOperand(MachineOperand::CreateMBB(LongBrMBB));
435  } else
436  // Change branch destination and reverse condition.
437  replaceBranch(*MBB, I.Br, DL, FallThroughMBB);
438 }
439 
440 static void emitGPDisp(MachineFunction &F, const MipsInstrInfo *TII) {
441  MachineBasicBlock &MBB = F.front();
443  DebugLoc DL = MBB.findDebugLoc(MBB.begin());
444  BuildMI(MBB, I, DL, TII->get(Mips::LUi), Mips::V0)
445  .addExternalSymbol("_gp_disp", MipsII::MO_ABS_HI);
446  BuildMI(MBB, I, DL, TII->get(Mips::ADDiu), Mips::V0)
447  .addReg(Mips::V0).addExternalSymbol("_gp_disp", MipsII::MO_ABS_LO);
448  MBB.removeLiveIn(Mips::V0);
449 }
450 
451 bool MipsLongBranch::runOnMachineFunction(MachineFunction &F) {
452  const MipsSubtarget &STI =
453  static_cast<const MipsSubtarget &>(F.getSubtarget());
454  const MipsInstrInfo *TII =
455  static_cast<const MipsInstrInfo *>(STI.getInstrInfo());
456  LongBranchSeqSize =
457  !IsPIC ? 2 : (ABI.IsN64() ? 10 : (!STI.isTargetNaCl() ? 9 : 10));
458 
459  if (STI.inMips16Mode() || !STI.enableLongBranchPass())
460  return false;
461  if ((TM.getRelocationModel() == Reloc::PIC_) &&
462  static_cast<const MipsTargetMachine &>(TM).getABI().IsO32() &&
463  F.getInfo<MipsFunctionInfo>()->globalBaseRegSet())
464  emitGPDisp(F, TII);
465 
466  if (SkipLongBranch)
467  return true;
468 
469  MF = &F;
470  initMBBInfo();
471 
472  SmallVectorImpl<MBBInfo>::iterator I, E = MBBInfos.end();
473  bool EverMadeChange = false, MadeChange = true;
474 
475  while (MadeChange) {
476  MadeChange = false;
477 
478  for (I = MBBInfos.begin(); I != E; ++I) {
479  // Skip if this MBB doesn't have a branch or the branch has already been
480  // converted to a long branch.
481  if (!I->Br || I->HasLongBranch)
482  continue;
483 
484  int ShVal = STI.inMicroMipsMode() ? 2 : 4;
485  int64_t Offset = computeOffset(I->Br) / ShVal;
486 
487  if (STI.isTargetNaCl()) {
488  // The offset calculation does not include sandboxing instructions
489  // that will be added later in the MC layer. Since at this point we
490  // don't know the exact amount of code that "sandboxing" will add, we
491  // conservatively estimate that code will not grow more than 100%.
492  Offset *= 2;
493  }
494 
495  // Check if offset fits into 16-bit immediate field of branches.
496  if (!ForceLongBranch && isInt<16>(Offset))
497  continue;
498 
499  I->HasLongBranch = true;
500  I->Size += LongBranchSeqSize * 4;
501  ++LongBranches;
502  EverMadeChange = MadeChange = true;
503  }
504  }
505 
506  if (!EverMadeChange)
507  return true;
508 
509  // Compute basic block addresses.
510  if (TM.getRelocationModel() == Reloc::PIC_) {
511  uint64_t Address = 0;
512 
513  for (I = MBBInfos.begin(); I != E; Address += I->Size, ++I)
514  I->Address = Address;
515  }
516 
517  // Do the expansion.
518  for (I = MBBInfos.begin(); I != E; ++I)
519  if (I->HasLongBranch)
520  expandToLongBranch(*I);
521 
522  MF->RenumberBlocks();
523 
524  return true;
525 }
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
instr_iterator instr_begin()
instr_iterator instr_end()
STATISTIC(NumFunctions,"Total number of functions")
MachineBasicBlock * getMBB() const
int getNumber() const
getNumber - MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a M...
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:138
void removeLiveIn(unsigned Reg)
removeLiveIn - Remove the specified register from the live in set.
const MipsInstrInfo * getInstrInfo() const override
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:264
A debug info location.
Definition: DebugLoc.h:34
F(f)
virtual unsigned getOppositeBranchOpc(unsigned Opc) const =0
Instructions::iterator instr_iterator
static void emitGPDisp(MachineFunction &F, const MipsInstrInfo *TII)
void append(SmallVectorImpl< char > &path, const Twine &a, const Twine &b="", const Twine &c="", const Twine &d="")
Append to path.
Definition: Path.cpp:443
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
bool isReg() const
isReg - Tests if this is a MO_Register operand.
#define false
Definition: ConvertUTF.c:65
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
MO_ABS_HI/LO - Represents the hi or low part of an absolute symbol address.
Definition: MipsBaseInfo.h:53
const MachineBasicBlock & front() const
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
reverse_iterator rend()
reverse_iterator rbegin()
const BasicBlock * getBasicBlock() const
getBasicBlock - Return the LLVM basic block that this instance corresponded to originally.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:120
bundle_iterator< MachineInstr, instr_iterator > iterator
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:325
LLVM Basic Block Representation.
Definition: BasicBlock.h:65
FunctionPass * createMipsLongBranchPass(MipsTargetMachine &TM)
createMipsLongBranchPass - Returns a pass that converts branches to long branches.
DebugLoc findDebugLoc(instr_iterator MBBI)
findDebugLoc - find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE instructions...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
static cl::opt< bool > SkipLongBranch("skip-mips-long-branch", cl::init(false), cl::desc("MIPS: Skip long branch pass."), cl::Hidden)
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:294
bool inMicroMipsMode() const
bool inMips16Mode() const
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
void removeSuccessor(MachineBasicBlock *succ)
removeSuccessor - Remove successor from the successors list of this MachineBasicBlock.
bool hasMips32r6() const
static ReverseIter getNonDebugInstr(ReverseIter B, ReverseIter E)
bool isTargetNaCl() const
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:861
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
static const unsigned MIPS_NACL_BUNDLE_ALIGN
Definition: MipsMCNaCl.h:18
Representation of each machine instruction.
Definition: MachineInstr.h:51
static MachineOperand CreateMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0)
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned char TargetFlags=0) const
#define I(x, y, z)
Definition: MD5.cpp:54
#define N
static cl::opt< bool > ForceLongBranch("force-mips-long-branch", cl::init(false), cl::desc("MIPS: Expand all branches to long format."), cl::Hidden)
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:272
bool enableLongBranchPass() const
unsigned getReg() const
getReg - Returns the register number.
MIBundleBuilder & append(MachineInstr *MI)
Insert MI into MBB by appending it to the instructions in the bundle.
aarch64 promote const
virtual const TargetInstrInfo * getInstrInfo() const
std::reverse_iterator< iterator > reverse_iterator
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:185
BasicBlockListType::iterator iterator
Primary interface to the complete machine description for the target machine.
unsigned GetInstSizeInBytes(const MachineInstr *MI) const
Return the number of bytes of code the specified instruction may be.
static MachineBasicBlock * getTargetMBB(const MachineInstr &Br)
Iterate over list of Br's operands and search for a MachineBasicBlock operand.
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
void addSuccessor(MachineBasicBlock *succ, uint32_t weight=0)
addSuccessor - Add succ as a successor of this MachineBasicBlock.
Helper class for constructing bundles of MachineInstrs.