LLVM  3.7.0
SIMachineFunctionInfo.cpp
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1 //===-- SIMachineFunctionInfo.cpp - SI Machine Function Info -------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 /// \file
9 //===----------------------------------------------------------------------===//
10 
11 
12 #include "SIMachineFunctionInfo.h"
13 #include "AMDGPUSubtarget.h"
14 #include "SIInstrInfo.h"
18 #include "llvm/IR/Function.h"
19 #include "llvm/IR/LLVMContext.h"
20 
21 #define MAX_LANES 64
22 
23 using namespace llvm;
24 
25 
26 // Pin the vtable to this file.
27 void SIMachineFunctionInfo::anchor() {}
28 
31  TIDReg(AMDGPU::NoRegister),
32  HasSpilledVGPRs(false),
33  PSInputAddr(0),
34  NumUserSGPRs(0),
35  LDSWaveSpillSize(0) { }
36 
38  MachineFunction *MF,
39  unsigned FrameIndex,
40  unsigned SubIdx) {
41  const MachineFrameInfo *FrameInfo = MF->getFrameInfo();
42  const SIRegisterInfo *TRI = static_cast<const SIRegisterInfo *>(
43  MF->getSubtarget<AMDGPUSubtarget>().getRegisterInfo());
44  MachineRegisterInfo &MRI = MF->getRegInfo();
45  int64_t Offset = FrameInfo->getObjectOffset(FrameIndex);
46  Offset += SubIdx * 4;
47 
48  unsigned LaneVGPRIdx = Offset / (64 * 4);
49  unsigned Lane = (Offset / 4) % 64;
50 
51  struct SpilledReg Spill;
52 
53  if (!LaneVGPRs.count(LaneVGPRIdx)) {
54  unsigned LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass);
55  LaneVGPRs[LaneVGPRIdx] = LaneVGPR;
56  MRI.setPhysRegUsed(LaneVGPR);
57 
58  // Add this register as live-in to all blocks to avoid machine verifer
59  // complaining about use of an undefined physical register.
60  for (MachineFunction::iterator BI = MF->begin(), BE = MF->end();
61  BI != BE; ++BI) {
62  BI->addLiveIn(LaneVGPR);
63  }
64  }
65 
66  Spill.VGPR = LaneVGPRs[LaneVGPRIdx];
67  Spill.Lane = Lane;
68  return Spill;
69 }
70 
72  const MachineFunction &MF) const {
74  // FIXME: We should get this information from kernel attributes if it
75  // is available.
76  return getShaderType() == ShaderType::COMPUTE ? 256 : ST.getWavefrontSize();
77 }
void setPhysRegUsed(unsigned Reg)
setPhysRegUsed - Mark the specified register used in this function.
AMDGPU specific subclass of TargetSubtarget.
SIMachineFunctionInfo(const MachineFunction &MF)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
#define false
Definition: ConvertUTF.c:65
unsigned getMaximumWorkGroupSize(const MachineFunction &MF) const
unsigned findUnusedRegister(const MachineRegisterInfo &MRI, const TargetRegisterClass *RC) const
Returns a register that is not used at any point in the function.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
SpilledReg getSpilledReg(MachineFunction *MF, unsigned FrameIndex, unsigned SubIdx)
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
std::map< unsigned, unsigned > LaneVGPRs
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Interface definition for SIInstrInfo.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
unsigned getWavefrontSize() const
BasicBlockListType::iterator iterator