37 #define DEBUG_TYPE "mips-isel"
46 void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(
bool IsDef,
MachineInstr &
MI,
53 MIB.addReg(Mips::DSPPos, Flag);
56 MIB.addReg(Mips::DSPSCount, Flag);
59 MIB.addReg(Mips::DSPCarry, Flag);
62 MIB.addReg(Mips::DSPOutFlag, Flag);
65 MIB.addReg(Mips::DSPCCond, Flag);
68 MIB.addReg(Mips::DSPEFI, Flag);
71 unsigned MipsSEDAGToDAGISel::getMSACtrlReg(
const SDValue RegIdx)
const {
72 switch (cast<ConstantSDNode>(RegIdx)->getZExtValue()) {
75 case 0:
return Mips::MSAIR;
76 case 1:
return Mips::MSACSR;
77 case 2:
return Mips::MSAAccess;
78 case 3:
return Mips::MSASave;
79 case 4:
return Mips::MSAModify;
80 case 5:
return Mips::MSARequest;
81 case 6:
return Mips::MSAMap;
82 case 7:
return Mips::MSAUnmap;
88 unsigned DstReg = 0, ZeroReg = 0;
96 }
else if ((MI.
getOpcode() == Mips::DADDiu) &&
100 ZeroReg = Mips::ZERO_64;
110 unsigned OpNo = U.getOperandNo();
138 RC = (ABI.
IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
153 BuildMI(MBB, I, DL, TII.
get(Mips::DADDu), V1).addReg(V0)
210 .addReg(Mips::V0).
addReg(Mips::T9);
213 void MipsSEDAGToDAGISel::processFunctionAfterISel(
MachineFunction &MF) {
214 initGlobalBaseReg(MF);
221 if (I->getOpcode() == Mips::RDDSP)
222 addDSPCtrlRegOperands(
false, *I, MF);
223 else if (I->getOpcode() == Mips::WRDSP)
224 addDSPCtrlRegOperands(
true, *I, MF);
226 replaceUsesWithZeroReg(MRI, *I);
230 SDNode *MipsSEDAGToDAGISel::selectAddESubE(
unsigned MOp,
SDValue InFlag,
233 unsigned Opc = InFlag.
getOpcode(); (void)Opc;
237 "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
239 unsigned SLTuOp = Mips::SLTu, ADDuOp = Mips::ADDu;
241 SLTuOp = Mips::SLTu64;
242 ADDuOp = Mips::DADDu;
274 bool MipsSEDAGToDAGISel::selectAddrFrameIndex(
SDValue Addr,
SDValue &Base,
287 bool MipsSEDAGToDAGISel::selectAddrFrameIndexOffset(
SDValue Addr,
SDValue &Base,
289 unsigned OffsetBits)
const {
312 bool MipsSEDAGToDAGISel::selectAddrRegImm(
SDValue Addr,
SDValue &Base,
315 if (selectAddrFrameIndex(Addr, Base, Offset))
332 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 16))
348 if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
349 isa<JumpTableSDNode>(Opnd0)) {
362 bool MipsSEDAGToDAGISel::selectAddrRegReg(
SDValue Addr,
SDValue &Base,
374 bool MipsSEDAGToDAGISel::selectAddrDefault(
SDValue Addr,
SDValue &Base,
381 bool MipsSEDAGToDAGISel::selectIntAddr(
SDValue Addr,
SDValue &Base,
383 return selectAddrRegImm(Addr, Base, Offset) ||
384 selectAddrDefault(Addr, Base, Offset);
387 bool MipsSEDAGToDAGISel::selectAddrRegImm9(
SDValue Addr,
SDValue &Base,
389 if (selectAddrFrameIndex(Addr, Base, Offset))
392 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 9))
398 bool MipsSEDAGToDAGISel::selectAddrRegImm10(
SDValue Addr,
SDValue &Base,
400 if (selectAddrFrameIndex(Addr, Base, Offset))
403 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10))
410 bool MipsSEDAGToDAGISel::selectAddrRegImm12(
SDValue Addr,
SDValue &Base,
412 if (selectAddrFrameIndex(Addr, Base, Offset))
415 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 12))
421 bool MipsSEDAGToDAGISel::selectAddrRegImm16(
SDValue Addr,
SDValue &Base,
423 if (selectAddrFrameIndex(Addr, Base, Offset))
426 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 16))
432 bool MipsSEDAGToDAGISel::selectIntAddrMM(
SDValue Addr,
SDValue &Base,
434 return selectAddrRegImm12(Addr, Base, Offset) ||
435 selectAddrDefault(Addr, Base, Offset);
438 bool MipsSEDAGToDAGISel::selectIntAddrLSL2MM(
SDValue Addr,
SDValue &Base,
440 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 7)) {
441 if (isa<FrameIndexSDNode>(Base))
446 return (CnstOff == (CnstOff & 0x3c));
454 if (selectAddrRegImm(Addr, Base, Offset))
457 return selectAddrDefault(Addr, Base, Offset);
460 bool MipsSEDAGToDAGISel::selectIntAddrMSA(
SDValue Addr,
SDValue &Base,
462 if (selectAddrRegImm10(Addr, Base, Offset))
465 if (selectAddrDefault(Addr, Base, Offset))
476 bool MipsSEDAGToDAGISel::selectVSplat(
SDNode *
N,
APInt &Imm,
477 unsigned MinSizeInBits)
const {
486 APInt SplatValue, SplatUndef;
487 unsigned SplatBitSize;
490 if (!Node->
isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
515 bool MipsSEDAGToDAGISel::
517 unsigned ImmBitSize)
const {
528 (!Signed && ImmValue.
isIntN(ImmBitSize))) {
538 bool MipsSEDAGToDAGISel::
540 return selectVSplatCommon(N, Imm,
false, 1);
543 bool MipsSEDAGToDAGISel::
545 return selectVSplatCommon(N, Imm,
false, 2);
548 bool MipsSEDAGToDAGISel::
550 return selectVSplatCommon(N, Imm,
false, 3);
554 bool MipsSEDAGToDAGISel::
556 return selectVSplatCommon(N, Imm,
false, 4);
560 bool MipsSEDAGToDAGISel::
562 return selectVSplatCommon(N, Imm,
false, 5);
566 bool MipsSEDAGToDAGISel::
568 return selectVSplatCommon(N, Imm,
false, 6);
572 bool MipsSEDAGToDAGISel::
574 return selectVSplatCommon(N, Imm,
false, 8);
578 bool MipsSEDAGToDAGISel::
580 return selectVSplatCommon(N, Imm,
true, 5);
593 bool MipsSEDAGToDAGISel::selectVSplatUimmPow2(
SDValue N,
SDValue &Imm)
const {
624 bool MipsSEDAGToDAGISel::selectVSplatMaskL(
SDValue N,
SDValue &Imm)
const {
636 if (ImmValue == ~(~ImmValue & ~(~ImmValue + 1))) {
658 bool MipsSEDAGToDAGISel::selectVSplatMaskR(
SDValue N,
SDValue &Imm)
const {
669 if (ImmValue == (ImmValue & ~(ImmValue + 1))) {
679 bool MipsSEDAGToDAGISel::selectVSplatUimmInvPow2(
SDValue N,
689 int32_t Log2 = (~ImmValue).exactLogBase2();
700 std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(
SDNode *Node) {
716 Result = selectAddESubE(Opc, InFlag, InFlag.
getOperand(0),
DL, Node);
717 return std::make_pair(
true, Result);
725 Result = selectAddESubE(Opc, InFlag, InFlag.
getValue(0),
DL, Node);
726 return std::make_pair(
true, Result);
748 return std::make_pair(
true, Result);
764 AnalyzeImm.
Analyze(Imm, Size,
false);
775 if (Inst->Opc == Mips::LUi64)
784 for (++Inst; Inst != Seq.
end(); ++Inst) {
791 return std::make_pair(
true, RegOpnd);
795 switch (cast<ConstantSDNode>(Node->
getOperand(1))->getZExtValue()) {
799 case Intrinsic::mips_cfcmsa: {
804 return std::make_pair(
true, Reg.
getNode());
811 switch (cast<ConstantSDNode>(Node->
getOperand(0))->getZExtValue()) {
815 case Intrinsic::mips_move_v:
818 return std::make_pair(
true,
827 switch (cast<ConstantSDNode>(Node->
getOperand(1))->getZExtValue()) {
831 case Intrinsic::mips_ctcmsa: {
836 getMSACtrlReg(RegIdx), Value);
837 return std::make_pair(
true, ChainOut.
getNode());
845 unsigned RdhwrOpc, DestReg;
848 RdhwrOpc = Mips::RDHWR;
851 RdhwrOpc = Mips::RDHWR64;
852 DestReg = Mips::V1_64;
863 return std::make_pair(
true, ResNode.
getNode());
880 APInt SplatValue, SplatUndef;
881 unsigned SplatBitSize;
888 return std::make_pair(
false,
nullptr);
893 return std::make_pair(
false,
nullptr);
895 switch (SplatBitSize) {
897 return std::make_pair(
false,
nullptr);
916 if (!SplatValue.isSignedIntN(10))
917 return std::make_pair(
false,
nullptr);
924 if (ResVecTy != ViaVecTy) {
938 return std::make_pair(
true, Res);
943 return std::make_pair(
false,
nullptr);
946 bool MipsSEDAGToDAGISel::
947 SelectInlineAsmMemoryOperand(
const SDValue &Op,
unsigned ConstraintID,
948 std::vector<SDValue> &OutOps) {
951 switch(ConstraintID) {
956 OutOps.push_back(Op);
960 if (selectAddrRegImm16(Op, Base, Offset)) {
961 OutOps.push_back(Base);
962 OutOps.push_back(Offset);
965 OutOps.push_back(Op);
974 if (selectAddrRegImm9(Op, Base, Offset)) {
975 OutOps.push_back(Base);
976 OutOps.push_back(Offset);
979 OutOps.push_back(Op);
987 if (selectAddrRegImm12(Op, Base, Offset)) {
988 OutOps.push_back(Base);
989 OutOps.push_back(Offset);
994 if (selectAddrRegImm9(Op, Base, Offset)) {
995 OutOps.push_back(Base);
996 OutOps.push_back(Offset);
999 }
else if (selectAddrRegImm16(Op, Base, Offset)) {
1001 OutOps.push_back(Base);
1002 OutOps.push_back(Offset);
1006 OutOps.push_back(Op);
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
unsigned getValueSizeInBits(unsigned ResNo) const
Returns MVT::getSizeInBits(getValueType(ResNo)).
SDValue getValue(unsigned R) const
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
bool isExactlyValue(double V) const
We don't rely on operator== working on double values, as it returns true for things that are clearly ...
SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N)
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
void ReplaceUses(SDValue F, SDValue T)
ReplaceUses - replace all uses of the old node F with the use of the new node T.
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
Carry-setting nodes for multiple precision addition and subtraction.
bool isPseudo(QueryType Type=IgnoreBundle) const
Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction...
const MipsInstrInfo * getInstrInfo() const override
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
void addLiveIn(unsigned Reg)
Adds the specified register as a live in.
unsigned getID() const
getID() - Return the register class ID number.
TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or anything else with this node...
const SDValue & getOperand(unsigned Num) const
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
GlobalBaseReg - On Darwin, this node represents the result of the mflr at function entry...
FunctionPass * createMipsSEISelDag(MipsTargetMachine &TM)
static use_iterator use_end()
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
const TargetLowering * TLI
const TargetLowering * getTargetLowering() const
Reg
All possible values of the reg field in the ModR/M byte.
bool isIntN(unsigned N) const
Check if this APInt has an N-bits unsigned integer value.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
MO_ABS_HI/LO - Represents the hi or low part of an absolute symbol address.
EVT getVectorElementType() const
getVectorElementType - Given a vector type, return the type of each element.
bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef, unsigned &SplatBitSize, bool &HasAnyUndefs, unsigned MinSplatBits=0, bool isBigEndian=false) const
Check if this is a constant splat, and if so, find the smallest element size that splats the vector...
const MachineBasicBlock & front() const
SDValue getTargetFrameIndex(int FI, EVT VT)
Simple integer binary arithmetic operators.
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
const DataLayout & getDataLayout() const
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Flag
These should be considered private to the implementation of the MCInstrDesc class.
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable...
TargetInstrInfo - Interface to description of machine instruction set.
MachineRegisterInfo * RegInfo
SDNode * getNode() const
get the SDNode which holds the desired result
bundle_iterator< MachineInstr, instr_iterator > iterator
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
const MipsSubtarget * Subtarget
Keep a pointer to the MipsSubtarget around so that we can make the right decision when generating cod...
MVT - Machine Value Type.
const SDValue & getOperand(unsigned i) const
const MachineOperand & getOperand(unsigned i) const
Carry-using nodes for multiple precision addition and subtraction.
SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT)
SDValue getTargetConstant(uint64_t Val, SDLoc DL, EVT VT, bool isOpaque=false)
unsigned getBitWidth() const
Return the number of bits in the APInt.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
unsigned getOpcode() const
FunctionPass class - This class is used to implement most global optimizations.
unsigned countPopulation() const
Count the number of bits set.
bool inMicroMipsMode() const
bool inMips16Mode() const
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
EVT - Extended Value Type.
bool isIntN(unsigned N, int64_t x)
isIntN - Checks if an signed integer fits into the given (dynamic) bit width.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
bool isBaseWithConstantOffset(SDValue Op) const
Return true if the specified operand is an ISD::ADD with a ConstantSDNode on the right-hand side...
unsigned getGlobalBaseReg()
double Log2(double Value)
Log2 - This function returns the log base 2 of the specified value.
SDNode * SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT)
These are used for target selectors to mutate the specified node to have the specified return type...
MachineOperand class - Representation of each machine instruction operand.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
int32_t exactLogBase2() const
Represents one node in the SelectionDAG.
Class for arbitrary precision integers.
bool isSignedIntN(unsigned N) const
Check if this APInt has an N-bits signed integer value.
A "pseudo-class" with methods for operating on BUILD_VECTORs.
int64_t getSExtValue() const
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
Return the register class that should be used for the specified value type.
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned char TargetFlags=0) const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
use_iterator use_begin(unsigned RegNo) const
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned char TargetFlags=0) const
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
void setReg(unsigned Reg)
Change the register this operand corresponds to.
COPY_TO_REGCLASS - This instruction is a placeholder for a plain register-to-register copy into a spe...
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
MachineSDNode * getMachineNode(unsigned Opcode, SDLoc dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s), MachineInstr opcode, and operands.
bool globalBaseRegSet() const
EVT getValueType() const
Return the ValueType of the referenced return value.
bool is128BitVector() const
is128BitVector - Return true if this is a 128-bit vector type.
unsigned getReg() const
getReg - Returns the register number.
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
LLVM Value Representation.
SDValue getRegister(unsigned Reg, EVT VT)
BasicBlockListType::iterator iterator
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except that the first operand is an imme...
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
const TargetInstrInfo * TII
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
MVT getSimpleVT() const
getSimpleVT - Return the SimpleValueType held in the specified simple EVT.
uint64_t getZExtValue() const