26 #define DEBUG_TYPE "aarch64-disassembler"
34 unsigned RegNo, uint64_t
Address,
56 unsigned RegNo, uint64_t
Address,
62 unsigned RegNo, uint64_t
Address,
90 uint64_t
Address,
const void *Decoder);
92 uint64_t
Address,
const void *Decoder);
94 uint64_t
Address,
const void *Decoder);
96 uint64_t
Address,
const void *Decoder);
100 const void *Decoder);
103 const void *Decoder);
107 const void *Decoder);
109 uint32_t insn, uint64_t
Address,
110 const void *Decoder);
114 const void *Decoder);
117 const void *Decoder);
119 uint32_t insn, uint64_t
Address,
120 const void *Decoder);
122 uint32_t insn, uint64_t
Address,
123 const void *Decoder);
126 const void *Decoder);
128 uint32_t insn, uint64_t
Address,
129 const void *Decoder);
131 uint64_t
Address,
const void *Decoder);
133 uint64_t
Address,
const void *Decoder);
136 const void *Decoder);
140 const void *Decoder);
142 uint64_t
Address,
const void *Decoder);
146 const void *Decoder);
148 uint64_t Addr,
const void *Decoder);
151 const void *Decoder);
153 uint64_t Addr,
const void *Decoder);
156 const void *Decoder);
158 uint64_t Addr,
const void *Decoder);
161 const void *Decoder);
163 uint64_t Addr,
const void *Decoder);
165 uint64_t Addr,
const void *Decoder);
167 uint64_t Addr,
const void *Decoder);
169 uint64_t Addr,
const void *Decoder);
171 uint64_t Addr,
const void *Decoder);
175 const void *Decoder);
179 const void *Decoder);
196 #include "AArch64GenDisassemblerTables.inc"
197 #include "AArch64GenInstrInfo.inc"
199 #define Success llvm::MCDisassembler::Success
200 #define Fail llvm::MCDisassembler::Fail
201 #define SoftFail llvm::MCDisassembler::SoftFail
218 if (Bytes.
size() < 4)
224 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
234 std::unique_ptr<MCRelocationInfo> &&RelInfo) {
236 SymbolLookUp, DisInfo);
256 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
257 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9,
258 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
259 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19,
260 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
261 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29,
262 AArch64::Q30, AArch64::Q31
267 const void *Decoder) {
278 const void *Decoder) {
285 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4,
286 AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9,
287 AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14,
288 AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19,
289 AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24,
290 AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29,
291 AArch64::D30, AArch64::D31
296 const void *Decoder) {
306 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4,
307 AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9,
308 AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14,
309 AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19,
310 AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24,
311 AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29,
312 AArch64::S30, AArch64::S31
317 const void *Decoder) {
327 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4,
328 AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9,
329 AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14,
330 AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19,
331 AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24,
332 AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29,
333 AArch64::H30, AArch64::H31
338 const void *Decoder) {
348 AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4,
349 AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9,
350 AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14,
351 AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19,
352 AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24,
353 AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29,
354 AArch64::B30, AArch64::B31
359 const void *Decoder) {
369 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4,
370 AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9,
371 AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14,
372 AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19,
373 AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24,
374 AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP,
375 AArch64::LR, AArch64::XZR
380 const void *Decoder) {
391 const void *Decoder) {
395 if (Register == AArch64::XZR)
396 Register = AArch64::SP;
402 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4,
403 AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9,
404 AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14,
405 AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19,
406 AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24,
407 AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29,
408 AArch64::W30, AArch64::WZR
413 const void *Decoder) {
424 const void *Decoder) {
429 if (Register == AArch64::WZR)
430 Register = AArch64::WSP;
436 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
437 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9,
438 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
439 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19,
440 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
441 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29,
442 AArch64::Q30, AArch64::Q31
447 const void *Decoder) {
457 AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4,
458 AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8,
459 AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12,
460 AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16,
461 AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20,
462 AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24,
463 AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28,
464 AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0
468 uint64_t Addr,
const void *Decoder) {
477 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4,
478 AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7,
479 AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10,
480 AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13,
481 AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16,
482 AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19,
483 AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22,
484 AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25,
485 AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28,
486 AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31,
487 AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1
491 uint64_t Addr,
const void *Decoder) {
500 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5,
501 AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8,
502 AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11,
503 AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14,
504 AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17,
505 AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20,
506 AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23,
507 AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26,
508 AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29,
509 AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0,
510 AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2
515 const void *Decoder) {
524 AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4,
525 AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8,
526 AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12,
527 AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16,
528 AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20,
529 AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24,
530 AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28,
531 AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0
535 uint64_t Addr,
const void *Decoder) {
544 AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4,
545 AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7,
546 AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10,
547 AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13,
548 AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16,
549 AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19,
550 AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22,
551 AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25,
552 AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28,
553 AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31,
554 AArch64::D30_D31_D0, AArch64::D31_D0_D1
558 uint64_t Addr,
const void *Decoder) {
567 AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5,
568 AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8,
569 AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11,
570 AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14,
571 AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17,
572 AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20,
573 AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23,
574 AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26,
575 AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29,
576 AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0,
577 AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2
582 const void *Decoder) {
592 const void *Decoder) {
601 const void *Decoder) {
607 uint64_t Addr,
const void *Decoder) {
608 int64_t ImmVal = Imm;
613 if (ImmVal & (1 << (19 - 1)))
614 ImmVal |= ~((1LL << 19) - 1);
617 Inst.
getOpcode() != AArch64::LDRXl, 0, 4))
623 uint64_t
Address,
const void *Decoder) {
631 const void *Decoder) {
641 const void *Decoder) {
649 const void *Decoder) {
652 unsigned Rd = fieldFromInstruction(Insn, 0, 5);
653 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
654 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
683 uint64_t Addr,
const void *Decoder) {
689 const void *Decoder) {
694 uint64_t Addr,
const void *Decoder) {
700 const void *Decoder) {
705 uint64_t Addr,
const void *Decoder) {
711 const void *Decoder) {
716 uint64_t Addr,
const void *Decoder) {
721 uint64_t Addr,
const void *Decoder) {
726 uint64_t Addr,
const void *Decoder) {
731 uint64_t Addr,
const void *Decoder) {
736 uint64_t Addr,
const void *Decoder) {
741 uint32_t insn, uint64_t Addr,
742 const void *Decoder) {
743 unsigned Rd = fieldFromInstruction(insn, 0, 5);
744 unsigned Rn = fieldFromInstruction(insn, 5, 5);
745 unsigned Rm = fieldFromInstruction(insn, 16, 5);
746 unsigned shiftHi = fieldFromInstruction(insn, 22, 2);
747 unsigned shiftLo = fieldFromInstruction(insn, 10, 6);
748 unsigned shift = (shiftHi << 6) | shiftLo;
752 case AArch64::ADDWrs:
753 case AArch64::ADDSWrs:
754 case AArch64::SUBWrs:
755 case AArch64::SUBSWrs:
760 case AArch64::ANDWrs:
761 case AArch64::ANDSWrs:
762 case AArch64::BICWrs:
763 case AArch64::BICSWrs:
764 case AArch64::ORRWrs:
765 case AArch64::ORNWrs:
766 case AArch64::EORWrs:
767 case AArch64::EONWrs: {
769 if (shiftLo >> 5 == 1)
776 case AArch64::ADDXrs:
777 case AArch64::ADDSXrs:
778 case AArch64::SUBXrs:
779 case AArch64::SUBSXrs:
784 case AArch64::ANDXrs:
785 case AArch64::ANDSXrs:
786 case AArch64::BICXrs:
787 case AArch64::BICSXrs:
788 case AArch64::ORRXrs:
789 case AArch64::ORNXrs:
790 case AArch64::EORXrs:
791 case AArch64::EONXrs:
804 const void *Decoder) {
805 unsigned Rd = fieldFromInstruction(insn, 0, 5);
806 unsigned imm = fieldFromInstruction(insn, 5, 16);
807 unsigned shift = fieldFromInstruction(insn, 21, 2);
812 case AArch64::MOVZWi:
813 case AArch64::MOVNWi:
814 case AArch64::MOVKWi:
815 if (shift & (1U << 5))
819 case AArch64::MOVZXi:
820 case AArch64::MOVNXi:
821 case AArch64::MOVKXi:
826 if (Inst.
getOpcode() == AArch64::MOVKWi ||
836 uint32_t insn, uint64_t Addr,
837 const void *Decoder) {
838 unsigned Rt = fieldFromInstruction(insn, 0, 5);
839 unsigned Rn = fieldFromInstruction(insn, 5, 5);
840 unsigned offset = fieldFromInstruction(insn, 10, 12);
847 case AArch64::PRFMui:
851 case AArch64::STRBBui:
852 case AArch64::LDRBBui:
853 case AArch64::LDRSBWui:
854 case AArch64::STRHHui:
855 case AArch64::LDRHHui:
856 case AArch64::LDRSHWui:
857 case AArch64::STRWui:
858 case AArch64::LDRWui:
861 case AArch64::LDRSBXui:
862 case AArch64::LDRSHXui:
863 case AArch64::LDRSWui:
864 case AArch64::STRXui:
865 case AArch64::LDRXui:
868 case AArch64::LDRQui:
869 case AArch64::STRQui:
872 case AArch64::LDRDui:
873 case AArch64::STRDui:
876 case AArch64::LDRSui:
877 case AArch64::STRSui:
880 case AArch64::LDRHui:
881 case AArch64::STRHui:
884 case AArch64::LDRBui:
885 case AArch64::STRBui:
897 uint32_t insn, uint64_t Addr,
898 const void *Decoder) {
899 unsigned Rt = fieldFromInstruction(insn, 0, 5);
900 unsigned Rn = fieldFromInstruction(insn, 5, 5);
901 int64_t offset = fieldFromInstruction(insn, 12, 9);
905 if (offset & (1 << (9 - 1)))
906 offset |= ~((1LL << 9) - 1);
912 case AArch64::LDRSBWpre:
913 case AArch64::LDRSHWpre:
914 case AArch64::STRBBpre:
915 case AArch64::LDRBBpre:
916 case AArch64::STRHHpre:
917 case AArch64::LDRHHpre:
918 case AArch64::STRWpre:
919 case AArch64::LDRWpre:
920 case AArch64::LDRSBWpost:
921 case AArch64::LDRSHWpost:
922 case AArch64::STRBBpost:
923 case AArch64::LDRBBpost:
924 case AArch64::STRHHpost:
925 case AArch64::LDRHHpost:
926 case AArch64::STRWpost:
927 case AArch64::LDRWpost:
928 case AArch64::LDRSBXpre:
929 case AArch64::LDRSHXpre:
930 case AArch64::STRXpre:
931 case AArch64::LDRSWpre:
932 case AArch64::LDRXpre:
933 case AArch64::LDRSBXpost:
934 case AArch64::LDRSHXpost:
935 case AArch64::STRXpost:
936 case AArch64::LDRSWpost:
937 case AArch64::LDRXpost:
938 case AArch64::LDRQpre:
939 case AArch64::STRQpre:
940 case AArch64::LDRQpost:
941 case AArch64::STRQpost:
942 case AArch64::LDRDpre:
943 case AArch64::STRDpre:
944 case AArch64::LDRDpost:
945 case AArch64::STRDpost:
946 case AArch64::LDRSpre:
947 case AArch64::STRSpre:
948 case AArch64::LDRSpost:
949 case AArch64::STRSpost:
950 case AArch64::LDRHpre:
951 case AArch64::STRHpre:
952 case AArch64::LDRHpost:
953 case AArch64::STRHpost:
954 case AArch64::LDRBpre:
955 case AArch64::STRBpre:
956 case AArch64::LDRBpost:
957 case AArch64::STRBpost:
965 case AArch64::PRFUMi:
969 case AArch64::STURBBi:
970 case AArch64::LDURBBi:
971 case AArch64::LDURSBWi:
972 case AArch64::STURHHi:
973 case AArch64::LDURHHi:
974 case AArch64::LDURSHWi:
975 case AArch64::STURWi:
976 case AArch64::LDURWi:
977 case AArch64::LDTRSBWi:
978 case AArch64::LDTRSHWi:
979 case AArch64::STTRWi:
980 case AArch64::LDTRWi:
981 case AArch64::STTRHi:
982 case AArch64::LDTRHi:
983 case AArch64::LDTRBi:
984 case AArch64::STTRBi:
985 case AArch64::LDRSBWpre:
986 case AArch64::LDRSHWpre:
987 case AArch64::STRBBpre:
988 case AArch64::LDRBBpre:
989 case AArch64::STRHHpre:
990 case AArch64::LDRHHpre:
991 case AArch64::STRWpre:
992 case AArch64::LDRWpre:
993 case AArch64::LDRSBWpost:
994 case AArch64::LDRSHWpost:
995 case AArch64::STRBBpost:
996 case AArch64::LDRBBpost:
997 case AArch64::STRHHpost:
998 case AArch64::LDRHHpost:
999 case AArch64::STRWpost:
1000 case AArch64::LDRWpost:
1003 case AArch64::LDURSBXi:
1004 case AArch64::LDURSHXi:
1005 case AArch64::LDURSWi:
1006 case AArch64::STURXi:
1007 case AArch64::LDURXi:
1008 case AArch64::LDTRSBXi:
1009 case AArch64::LDTRSHXi:
1010 case AArch64::LDTRSWi:
1011 case AArch64::STTRXi:
1012 case AArch64::LDTRXi:
1013 case AArch64::LDRSBXpre:
1014 case AArch64::LDRSHXpre:
1015 case AArch64::STRXpre:
1016 case AArch64::LDRSWpre:
1017 case AArch64::LDRXpre:
1018 case AArch64::LDRSBXpost:
1019 case AArch64::LDRSHXpost:
1020 case AArch64::STRXpost:
1021 case AArch64::LDRSWpost:
1022 case AArch64::LDRXpost:
1025 case AArch64::LDURQi:
1026 case AArch64::STURQi:
1027 case AArch64::LDRQpre:
1028 case AArch64::STRQpre:
1029 case AArch64::LDRQpost:
1030 case AArch64::STRQpost:
1033 case AArch64::LDURDi:
1034 case AArch64::STURDi:
1035 case AArch64::LDRDpre:
1036 case AArch64::STRDpre:
1037 case AArch64::LDRDpost:
1038 case AArch64::STRDpost:
1041 case AArch64::LDURSi:
1042 case AArch64::STURSi:
1043 case AArch64::LDRSpre:
1044 case AArch64::STRSpre:
1045 case AArch64::LDRSpost:
1046 case AArch64::STRSpost:
1049 case AArch64::LDURHi:
1050 case AArch64::STURHi:
1051 case AArch64::LDRHpre:
1052 case AArch64::STRHpre:
1053 case AArch64::LDRHpost:
1054 case AArch64::STRHpost:
1057 case AArch64::LDURBi:
1058 case AArch64::STURBi:
1059 case AArch64::LDRBpre:
1060 case AArch64::STRBpre:
1061 case AArch64::LDRBpost:
1062 case AArch64::STRBpost:
1070 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1071 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
1072 bool IsFP = fieldFromInstruction(insn, 26, 1);
1075 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
1082 uint32_t insn, uint64_t Addr,
1083 const void *Decoder) {
1084 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1085 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1086 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1087 unsigned Rs = fieldFromInstruction(insn, 16, 5);
1093 case AArch64::STLXRW:
1094 case AArch64::STLXRB:
1095 case AArch64::STLXRH:
1096 case AArch64::STXRW:
1097 case AArch64::STXRB:
1098 case AArch64::STXRH:
1101 case AArch64::LDARW:
1102 case AArch64::LDARB:
1103 case AArch64::LDARH:
1104 case AArch64::LDAXRW:
1105 case AArch64::LDAXRB:
1106 case AArch64::LDAXRH:
1107 case AArch64::LDXRW:
1108 case AArch64::LDXRB:
1109 case AArch64::LDXRH:
1110 case AArch64::STLRW:
1111 case AArch64::STLRB:
1112 case AArch64::STLRH:
1113 case AArch64::STLLRW:
1114 case AArch64::STLLRB:
1115 case AArch64::STLLRH:
1116 case AArch64::LDLARW:
1117 case AArch64::LDLARB:
1118 case AArch64::LDLARH:
1121 case AArch64::STLXRX:
1122 case AArch64::STXRX:
1125 case AArch64::LDARX:
1126 case AArch64::LDAXRX:
1127 case AArch64::LDXRX:
1128 case AArch64::STLRX:
1129 case AArch64::LDLARX:
1130 case AArch64::STLLRX:
1133 case AArch64::STLXPW:
1134 case AArch64::STXPW:
1137 case AArch64::LDAXPW:
1138 case AArch64::LDXPW:
1142 case AArch64::STLXPX:
1143 case AArch64::STXPX:
1146 case AArch64::LDAXPX:
1147 case AArch64::LDXPX:
1156 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW ||
1157 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) &&
1166 const void *Decoder) {
1167 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1168 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1169 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1170 int64_t offset = fieldFromInstruction(insn, 15, 7);
1171 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1175 if (offset & (1 << (7 - 1)))
1176 offset |= ~((1LL << 7) - 1);
1179 bool NeedsDisjointWritebackTransfer =
false;
1185 case AArch64::LDPXpost:
1186 case AArch64::STPXpost:
1187 case AArch64::LDPSWpost:
1188 case AArch64::LDPXpre:
1189 case AArch64::STPXpre:
1190 case AArch64::LDPSWpre:
1191 case AArch64::LDPWpost:
1192 case AArch64::STPWpost:
1193 case AArch64::LDPWpre:
1194 case AArch64::STPWpre:
1195 case AArch64::LDPQpost:
1196 case AArch64::STPQpost:
1197 case AArch64::LDPQpre:
1198 case AArch64::STPQpre:
1199 case AArch64::LDPDpost:
1200 case AArch64::STPDpost:
1201 case AArch64::LDPDpre:
1202 case AArch64::STPDpre:
1203 case AArch64::LDPSpost:
1204 case AArch64::STPSpost:
1205 case AArch64::LDPSpre:
1206 case AArch64::STPSpre:
1214 case AArch64::LDPXpost:
1215 case AArch64::STPXpost:
1216 case AArch64::LDPSWpost:
1217 case AArch64::LDPXpre:
1218 case AArch64::STPXpre:
1219 case AArch64::LDPSWpre:
1220 NeedsDisjointWritebackTransfer =
true;
1222 case AArch64::LDNPXi:
1223 case AArch64::STNPXi:
1224 case AArch64::LDPXi:
1225 case AArch64::STPXi:
1226 case AArch64::LDPSWi:
1230 case AArch64::LDPWpost:
1231 case AArch64::STPWpost:
1232 case AArch64::LDPWpre:
1233 case AArch64::STPWpre:
1234 NeedsDisjointWritebackTransfer =
true;
1236 case AArch64::LDNPWi:
1237 case AArch64::STNPWi:
1238 case AArch64::LDPWi:
1239 case AArch64::STPWi:
1243 case AArch64::LDNPQi:
1244 case AArch64::STNPQi:
1245 case AArch64::LDPQpost:
1246 case AArch64::STPQpost:
1247 case AArch64::LDPQi:
1248 case AArch64::STPQi:
1249 case AArch64::LDPQpre:
1250 case AArch64::STPQpre:
1254 case AArch64::LDNPDi:
1255 case AArch64::STNPDi:
1256 case AArch64::LDPDpost:
1257 case AArch64::STPDpost:
1258 case AArch64::LDPDi:
1259 case AArch64::STPDi:
1260 case AArch64::LDPDpre:
1261 case AArch64::STPDpre:
1265 case AArch64::LDNPSi:
1266 case AArch64::STNPSi:
1267 case AArch64::LDPSpost:
1268 case AArch64::STPSpost:
1269 case AArch64::LDPSi:
1270 case AArch64::STPSi:
1271 case AArch64::LDPSpre:
1272 case AArch64::STPSpre:
1282 if (IsLoad && Rt == Rt2)
1287 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn))
1294 uint32_t insn, uint64_t Addr,
1295 const void *Decoder) {
1296 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1297 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1298 unsigned Rm = fieldFromInstruction(insn, 16, 5);
1299 unsigned extend = fieldFromInstruction(insn, 10, 6);
1301 unsigned shift = extend & 0x7;
1308 case AArch64::ADDWrx:
1309 case AArch64::SUBWrx:
1314 case AArch64::ADDSWrx:
1315 case AArch64::SUBSWrx:
1320 case AArch64::ADDXrx:
1321 case AArch64::SUBXrx:
1326 case AArch64::ADDSXrx:
1327 case AArch64::SUBSXrx:
1332 case AArch64::ADDXrx64:
1333 case AArch64::SUBXrx64:
1338 case AArch64::SUBSXrx64:
1339 case AArch64::ADDSXrx64:
1351 uint32_t insn, uint64_t Addr,
1352 const void *Decoder) {
1353 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1354 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1355 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1359 if (Inst.
getOpcode() == AArch64::ANDSXri)
1364 imm = fieldFromInstruction(insn, 10, 13);
1368 if (Inst.
getOpcode() == AArch64::ANDSWri)
1373 imm = fieldFromInstruction(insn, 10, 12);
1383 const void *Decoder) {
1384 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1385 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1386 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1387 imm |= fieldFromInstruction(insn, 5, 5);
1399 case AArch64::MOVIv4i16:
1400 case AArch64::MOVIv8i16:
1401 case AArch64::MVNIv4i16:
1402 case AArch64::MVNIv8i16:
1403 case AArch64::MOVIv2i32:
1404 case AArch64::MOVIv4i32:
1405 case AArch64::MVNIv2i32:
1406 case AArch64::MVNIv4i32:
1409 case AArch64::MOVIv2s_msl:
1410 case AArch64::MOVIv4s_msl:
1411 case AArch64::MVNIv2s_msl:
1412 case AArch64::MVNIv4s_msl:
1421 uint32_t insn, uint64_t Addr,
1422 const void *Decoder) {
1423 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1424 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1425 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1426 imm |= fieldFromInstruction(insn, 5, 5);
1439 uint64_t Addr,
const void *Decoder) {
1440 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1441 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2;
1442 imm |= fieldFromInstruction(insn, 29, 2);
1447 if (imm & (1 << (21 - 1)))
1448 imm |= ~((1LL << 21) - 1);
1458 uint64_t Addr,
const void *Decoder) {
1459 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1460 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1461 unsigned Imm = fieldFromInstruction(insn, 10, 14);
1462 unsigned S = fieldFromInstruction(insn, 29, 1);
1463 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1465 unsigned ShifterVal = (Imm >> 12) & 3;
1466 unsigned ImmVal = Imm & 0xFFF;
1470 if (ShifterVal != 0 && ShifterVal != 1)
1495 const void *Decoder) {
1496 int64_t imm = fieldFromInstruction(insn, 0, 26);
1501 if (imm & (1 << (26 - 1)))
1502 imm |= ~((1LL << 26) - 1);
1511 uint32_t insn, uint64_t Addr,
1512 const void *Decoder) {
1513 uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1514 uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1515 uint64_t crm = fieldFromInstruction(insn, 8, 4);
1517 uint64_t pstate_field = (op1 << 3) | op2;
1532 uint64_t Addr,
const void *Decoder) {
1533 uint64_t Rt = fieldFromInstruction(insn, 0, 5);
1534 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5;
1535 bit |= fieldFromInstruction(insn, 19, 5);
1536 int64_t dst = fieldFromInstruction(insn, 5, 14);
1541 if (dst & (1 << (14 - 1)))
1542 dst |= ~((1LL << 14) - 1);
1544 if (fieldFromInstruction(insn, 31, 1) == 0)
1556 unsigned RegClassID,
1559 const void *Decoder) {
1564 unsigned Register = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo);
1572 const void *Decoder) {
1574 AArch64::WSeqPairsClassRegClassID,
1575 RegNo, Addr, Decoder);
1581 const void *Decoder) {
1583 AArch64::XSeqPairsClassRegClassID,
1584 RegNo, Addr, Decoder);
static const unsigned FPR32DecoderTable[]
static DecodeStatus DecodeModImmTiedInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeTestAndBranch(llvm::MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeLogicalImmInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVecShiftR16ImmNarrow(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
static DecodeStatus DecodeBaseAddSubImm(llvm::MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMoveImmInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeAdrInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
DecodeStatus
Ternary decode status.
Superclass for all disassemblers.
const char *(* LLVMSymbolLookupCallback)(void *DisInfo, uint64_t ReferenceValue, uint64_t *ReferenceType, uint64_t ReferencePC, const char **ReferenceName)
The type for the symbol lookup function.
raw_ostream * CommentStream
static DecodeStatus DecodeVecShiftL64Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
static DecodeStatus DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVecShiftR64Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder)
static DecodeStatus DecodeFPR128RegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static const unsigned QQQDecoderTable[]
static DecodeStatus DecodeExclusiveLdStInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
static const unsigned VectorDecoderTable[]
static const unsigned GPR64DecoderTable[]
llvm::MCDisassembler::DecodeStatus DecodeStatus
static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static MCOperand createReg(unsigned Reg)
static DecodeStatus DecodePairLdStInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder)
static const unsigned FPR128DecoderTable[]
static DecodeStatus DecodeVecShiftR64ImmNarrow(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
static DecodeStatus DecodeUnconditionalBranch(llvm::MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
Context object for machine code objects.
const MCSubtargetInfo & STI
int decodeInstruction(InternalInstruction *insn, byteReader_t reader, const void *readerArg, dlog_t logger, void *loggerArg, const void *miiArg, uint64_t startLoc, DisassemblerMode mode)
Decode one instruction and store the decoding results in a buffer provided by the consumer...
static DecodeStatus DecodeModImmInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
StringRef toString(uint32_t Value, const FeatureBitset &FeatureBits, bool &Valid) const
static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID, unsigned RegNo, uint64_t Addr, const void *Decoder)
void LLVMInitializeAArch64Disassembler()
static DecodeStatus DecodeVecShiftL16Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
static const unsigned FPR8DecoderTable[]
static DecodeStatus DecodeFixedPointScaleImm64(llvm::MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVecShiftLImm(llvm::MCInst &Inst, unsigned Imm, unsigned Add)
size_t size() const
size - Get the array size.
Instances of this class represent a single low-level machine instruction.
static DecodeStatus DecodeDDDDRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVecShiftL8Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
const MCSubtargetInfo & getSubtargetInfo() const
static DecodeStatus DecodeQQRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeDDRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static const unsigned QQQQDecoderTable[]
static const unsigned FPR16DecoderTable[]
static DecodeStatus DecodeDDDRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Symbolize and annotate disassembled instructions.
static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeUnsignedLdStInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSignedLdStInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
static const unsigned GPR32DecoderTable[]
static const unsigned FPR64DecoderTable[]
static DecodeStatus DecodeVecShiftR32Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
static DecodeStatus DecodeAddSubERegInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVecShiftR8Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
static DecodeStatus DecodePCRelLabel19(llvm::MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVecShiftRImm(llvm::MCInst &Inst, unsigned Imm, unsigned Add)
static DecodeStatus DecodeMRSSystemRegister(llvm::MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder)
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t InstSize) const
static DecodeStatus DecodeGPR32spRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Triple - Helper class for working with autoconf configuration names.
Target TheAArch64leTarget
static DecodeStatus DecodeFixedPointScaleImm32(llvm::MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder)
static const unsigned DDDDecoderTable[]
Target TheAArch64beTarget
MCDisassembler::DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &VStream, raw_ostream &CStream) const override
Returns the disassembly of a single instruction.
static DecodeStatus DecodeMemExtend(llvm::MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeFPR128_loRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static const unsigned DDDDDecoderTable[]
static MCSymbolizer * createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo)
static const unsigned QQDecoderTable[]
Promote Memory to Register
static DecodeStatus DecodeVecShiftR32ImmNarrow(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
static DecodeStatus DecodeVecShiftR16Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
static DecodeStatus DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
unsigned getOpcode() const
Target - Wrapper for Target specific information.
static DecodeStatus DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeQQQQRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static const unsigned DDDecoderTable[]
static DecodeStatus DecodeQQQRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
std::error_code Check(std::error_code Err)
static DecodeStatus DecodeGPR64spRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVecShiftL32Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
MCSubtargetInfo - Generic base class for all target subtargets.
static bool isValidDecodeLogicalImmediate(uint64_t val, unsigned regSize)
isValidDecodeLogicalImmediate - Check to see if the logical immediate value in the form "N:immr:imms"...
static void RegisterMCSymbolizer(Target &T, Target::MCSymbolizerCtorTy Fn)
RegisterMCSymbolizer - Register an MCSymbolizer implementation for the given target.
static DecodeStatus DecodeThreeAddrSRegInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
This class implements an extremely fast bulk output stream that can only output to a stream...
static MCDisassembler * createAArch64Disassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
void addOperand(const MCOperand &Op)
static DecodeStatus DecodeMSRSystemRegister(llvm::MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder)
int(* LLVMOpInfoCallback)(void *DisInfo, uint64_t PC, uint64_t Offset, uint64_t Size, int TagType, void *TagBuf)
The type for the operand information call back function.
static MCOperand createImm(int64_t Val)
const MCOperand & getOperand(unsigned i) const
static DecodeStatus DecodeSystemPStateInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder)