LLVM  3.7.0
MachineCSE.cpp
Go to the documentation of this file.
1 //===-- MachineCSE.cpp - Machine Common Subexpression Elimination Pass ----===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This pass performs global common subexpression elimination on machine
11 // instructions using a scoped hash table based value numbering scheme. It
12 // must be run while the machine function is still in SSA form.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/ADT/Statistic.h"
25 #include "llvm/Support/Debug.h"
30 using namespace llvm;
31 
32 #define DEBUG_TYPE "machine-cse"
33 
34 STATISTIC(NumCoalesces, "Number of copies coalesced");
35 STATISTIC(NumCSEs, "Number of common subexpression eliminated");
36 STATISTIC(NumPhysCSEs,
37  "Number of physreg referencing common subexpr eliminated");
38 STATISTIC(NumCrossBBCSEs,
39  "Number of cross-MBB physreg referencing CS eliminated");
40 STATISTIC(NumCommutes, "Number of copies coalesced after commuting");
41 
42 namespace {
43  class MachineCSE : public MachineFunctionPass {
44  const TargetInstrInfo *TII;
45  const TargetRegisterInfo *TRI;
46  AliasAnalysis *AA;
49  public:
50  static char ID; // Pass identification
51  MachineCSE() : MachineFunctionPass(ID), LookAheadLimit(0), CurrVN(0) {
53  }
54 
55  bool runOnMachineFunction(MachineFunction &MF) override;
56 
57  void getAnalysisUsage(AnalysisUsage &AU) const override {
58  AU.setPreservesCFG();
64  }
65 
66  void releaseMemory() override {
67  ScopeMap.clear();
68  Exps.clear();
69  }
70 
71  private:
72  unsigned LookAheadLimit;
76  MachineInstrExpressionTrait, AllocatorTy> ScopedHTType;
77  typedef ScopedHTType::ScopeTy ScopeType;
79  ScopedHTType VNT;
81  unsigned CurrVN;
82 
83  bool PerformTrivialCopyPropagation(MachineInstr *MI,
84  MachineBasicBlock *MBB);
85  bool isPhysDefTriviallyDead(unsigned Reg,
88  bool hasLivePhysRegDefUses(const MachineInstr *MI,
89  const MachineBasicBlock *MBB,
90  SmallSet<unsigned,8> &PhysRefs,
91  SmallVectorImpl<unsigned> &PhysDefs,
92  bool &PhysUseDef) const;
93  bool PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
94  SmallSet<unsigned,8> &PhysRefs,
95  SmallVectorImpl<unsigned> &PhysDefs,
96  bool &NonLocal) const;
97  bool isCSECandidate(MachineInstr *MI);
98  bool isProfitableToCSE(unsigned CSReg, unsigned Reg,
99  MachineInstr *CSMI, MachineInstr *MI);
100  void EnterScope(MachineBasicBlock *MBB);
101  void ExitScope(MachineBasicBlock *MBB);
102  bool ProcessBlock(MachineBasicBlock *MBB);
103  void ExitScopeIfDone(MachineDomTreeNode *Node,
105  bool PerformCSE(MachineDomTreeNode *Node);
106  };
107 } // end anonymous namespace
108 
109 char MachineCSE::ID = 0;
111 INITIALIZE_PASS_BEGIN(MachineCSE, "machine-cse",
112  "Machine Common Subexpression Elimination", false, false)
115 INITIALIZE_PASS_END(MachineCSE, "machine-cse",
116  "Machine Common Subexpression Elimination", false, false)
117 
118 /// The source register of a COPY machine instruction can be propagated to all
119 /// its users, and this propagation could increase the probability of finding
120 /// common subexpressions. If the COPY has only one user, the COPY itself can
121 /// be removed.
122 bool MachineCSE::PerformTrivialCopyPropagation(MachineInstr *MI,
123  MachineBasicBlock *MBB) {
124  bool Changed = false;
125  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
126  MachineOperand &MO = MI->getOperand(i);
127  if (!MO.isReg() || !MO.isUse())
128  continue;
129  unsigned Reg = MO.getReg();
131  continue;
132  bool OnlyOneUse = MRI->hasOneNonDBGUse(Reg);
133  MachineInstr *DefMI = MRI->getVRegDef(Reg);
134  if (!DefMI->isCopy())
135  continue;
136  unsigned SrcReg = DefMI->getOperand(1).getReg();
138  continue;
139  if (DefMI->getOperand(0).getSubReg())
140  continue;
141  // FIXME: We should trivially coalesce subregister copies to expose CSE
142  // opportunities on instructions with truncated operands (see
143  // cse-add-with-overflow.ll). This can be done here as follows:
144  // if (SrcSubReg)
145  // RC = TRI->getMatchingSuperRegClass(MRI->getRegClass(SrcReg), RC,
146  // SrcSubReg);
147  // MO.substVirtReg(SrcReg, SrcSubReg, *TRI);
148  //
149  // The 2-addr pass has been updated to handle coalesced subregs. However,
150  // some machine-specific code still can't handle it.
151  // To handle it properly we also need a way find a constrained subregister
152  // class given a super-reg class and subreg index.
153  if (DefMI->getOperand(1).getSubReg())
154  continue;
155  const TargetRegisterClass *RC = MRI->getRegClass(Reg);
156  if (!MRI->constrainRegClass(SrcReg, RC))
157  continue;
158  DEBUG(dbgs() << "Coalescing: " << *DefMI);
159  DEBUG(dbgs() << "*** to: " << *MI);
160  // Propagate SrcReg of copies to MI.
161  MO.setReg(SrcReg);
162  MRI->clearKillFlags(SrcReg);
163  // Coalesce single use copies.
164  if (OnlyOneUse) {
165  DefMI->eraseFromParent();
166  ++NumCoalesces;
167  }
168  Changed = true;
169  }
170 
171  return Changed;
172 }
173 
174 bool
175 MachineCSE::isPhysDefTriviallyDead(unsigned Reg,
178  unsigned LookAheadLeft = LookAheadLimit;
179  while (LookAheadLeft) {
180  // Skip over dbg_value's.
181  while (I != E && I->isDebugValue())
182  ++I;
183 
184  if (I == E)
185  // Reached end of block, register is obviously dead.
186  return true;
187 
188  bool SeenDef = false;
189  for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
190  const MachineOperand &MO = I->getOperand(i);
191  if (MO.isRegMask() && MO.clobbersPhysReg(Reg))
192  SeenDef = true;
193  if (!MO.isReg() || !MO.getReg())
194  continue;
195  if (!TRI->regsOverlap(MO.getReg(), Reg))
196  continue;
197  if (MO.isUse())
198  // Found a use!
199  return false;
200  SeenDef = true;
201  }
202  if (SeenDef)
203  // See a def of Reg (or an alias) before encountering any use, it's
204  // trivially dead.
205  return true;
206 
207  --LookAheadLeft;
208  ++I;
209  }
210  return false;
211 }
212 
213 /// hasLivePhysRegDefUses - Return true if the specified instruction read/write
214 /// physical registers (except for dead defs of physical registers). It also
215 /// returns the physical register def by reference if it's the only one and the
216 /// instruction does not uses a physical register.
217 bool MachineCSE::hasLivePhysRegDefUses(const MachineInstr *MI,
218  const MachineBasicBlock *MBB,
219  SmallSet<unsigned,8> &PhysRefs,
220  SmallVectorImpl<unsigned> &PhysDefs,
221  bool &PhysUseDef) const{
222  // First, add all uses to PhysRefs.
223  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
224  const MachineOperand &MO = MI->getOperand(i);
225  if (!MO.isReg() || MO.isDef())
226  continue;
227  unsigned Reg = MO.getReg();
228  if (!Reg)
229  continue;
231  continue;
232  // Reading constant physregs is ok.
233  if (!MRI->isConstantPhysReg(Reg, *MBB->getParent()))
234  for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
235  PhysRefs.insert(*AI);
236  }
237 
238  // Next, collect all defs into PhysDefs. If any is already in PhysRefs
239  // (which currently contains only uses), set the PhysUseDef flag.
240  PhysUseDef = false;
241  MachineBasicBlock::const_iterator I = MI; I = std::next(I);
242  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
243  const MachineOperand &MO = MI->getOperand(i);
244  if (!MO.isReg() || !MO.isDef())
245  continue;
246  unsigned Reg = MO.getReg();
247  if (!Reg)
248  continue;
250  continue;
251  // Check against PhysRefs even if the def is "dead".
252  if (PhysRefs.count(Reg))
253  PhysUseDef = true;
254  // If the def is dead, it's ok. But the def may not marked "dead". That's
255  // common since this pass is run before livevariables. We can scan
256  // forward a few instructions and check if it is obviously dead.
257  if (!MO.isDead() && !isPhysDefTriviallyDead(Reg, I, MBB->end()))
258  PhysDefs.push_back(Reg);
259  }
260 
261  // Finally, add all defs to PhysRefs as well.
262  for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i)
263  for (MCRegAliasIterator AI(PhysDefs[i], TRI, true); AI.isValid(); ++AI)
264  PhysRefs.insert(*AI);
265 
266  return !PhysRefs.empty();
267 }
268 
269 bool MachineCSE::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
270  SmallSet<unsigned,8> &PhysRefs,
271  SmallVectorImpl<unsigned> &PhysDefs,
272  bool &NonLocal) const {
273  // For now conservatively returns false if the common subexpression is
274  // not in the same basic block as the given instruction. The only exception
275  // is if the common subexpression is in the sole predecessor block.
276  const MachineBasicBlock *MBB = MI->getParent();
277  const MachineBasicBlock *CSMBB = CSMI->getParent();
278 
279  bool CrossMBB = false;
280  if (CSMBB != MBB) {
281  if (MBB->pred_size() != 1 || *MBB->pred_begin() != CSMBB)
282  return false;
283 
284  for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i) {
285  if (MRI->isAllocatable(PhysDefs[i]) || MRI->isReserved(PhysDefs[i]))
286  // Avoid extending live range of physical registers if they are
287  //allocatable or reserved.
288  return false;
289  }
290  CrossMBB = true;
291  }
292  MachineBasicBlock::const_iterator I = CSMI; I = std::next(I);
295  unsigned LookAheadLeft = LookAheadLimit;
296  while (LookAheadLeft) {
297  // Skip over dbg_value's.
298  while (I != E && I != EE && I->isDebugValue())
299  ++I;
300 
301  if (I == EE) {
302  assert(CrossMBB && "Reaching end-of-MBB without finding MI?");
303  (void)CrossMBB;
304  CrossMBB = false;
305  NonLocal = true;
306  I = MBB->begin();
307  EE = MBB->end();
308  continue;
309  }
310 
311  if (I == E)
312  return true;
313 
314  for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
315  const MachineOperand &MO = I->getOperand(i);
316  // RegMasks go on instructions like calls that clobber lots of physregs.
317  // Don't attempt to CSE across such an instruction.
318  if (MO.isRegMask())
319  return false;
320  if (!MO.isReg() || !MO.isDef())
321  continue;
322  unsigned MOReg = MO.getReg();
324  continue;
325  if (PhysRefs.count(MOReg))
326  return false;
327  }
328 
329  --LookAheadLeft;
330  ++I;
331  }
332 
333  return false;
334 }
335 
336 bool MachineCSE::isCSECandidate(MachineInstr *MI) {
337  if (MI->isPosition() || MI->isPHI() || MI->isImplicitDef() || MI->isKill() ||
338  MI->isInlineAsm() || MI->isDebugValue())
339  return false;
340 
341  // Ignore copies.
342  if (MI->isCopyLike())
343  return false;
344 
345  // Ignore stuff that we obviously can't move.
346  if (MI->mayStore() || MI->isCall() || MI->isTerminator() ||
348  return false;
349 
350  if (MI->mayLoad()) {
351  // Okay, this instruction does a load. As a refinement, we allow the target
352  // to decide whether the loaded value is actually a constant. If so, we can
353  // actually use it as a load.
354  if (!MI->isInvariantLoad(AA))
355  // FIXME: we should be able to hoist loads with no other side effects if
356  // there are no other instructions which can change memory in this loop.
357  // This is a trivial form of alias analysis.
358  return false;
359  }
360  return true;
361 }
362 
363 /// isProfitableToCSE - Return true if it's profitable to eliminate MI with a
364 /// common expression that defines Reg.
365 bool MachineCSE::isProfitableToCSE(unsigned CSReg, unsigned Reg,
366  MachineInstr *CSMI, MachineInstr *MI) {
367  // FIXME: Heuristics that works around the lack the live range splitting.
368 
369  // If CSReg is used at all uses of Reg, CSE should not increase register
370  // pressure of CSReg.
371  bool MayIncreasePressure = true;
374  MayIncreasePressure = false;
376  for (MachineInstr &MI : MRI->use_nodbg_instructions(CSReg)) {
377  CSUses.insert(&MI);
378  }
379  for (MachineInstr &MI : MRI->use_nodbg_instructions(Reg)) {
380  if (!CSUses.count(&MI)) {
381  MayIncreasePressure = true;
382  break;
383  }
384  }
385  }
386  if (!MayIncreasePressure) return true;
387 
388  // Heuristics #1: Don't CSE "cheap" computation if the def is not local or in
389  // an immediate predecessor. We don't want to increase register pressure and
390  // end up causing other computation to be spilled.
391  if (TII->isAsCheapAsAMove(MI)) {
392  MachineBasicBlock *CSBB = CSMI->getParent();
393  MachineBasicBlock *BB = MI->getParent();
394  if (CSBB != BB && !CSBB->isSuccessor(BB))
395  return false;
396  }
397 
398  // Heuristics #2: If the expression doesn't not use a vr and the only use
399  // of the redundant computation are copies, do not cse.
400  bool HasVRegUse = false;
401  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
402  const MachineOperand &MO = MI->getOperand(i);
403  if (MO.isReg() && MO.isUse() &&
405  HasVRegUse = true;
406  break;
407  }
408  }
409  if (!HasVRegUse) {
410  bool HasNonCopyUse = false;
411  for (MachineInstr &MI : MRI->use_nodbg_instructions(Reg)) {
412  // Ignore copies.
413  if (!MI.isCopyLike()) {
414  HasNonCopyUse = true;
415  break;
416  }
417  }
418  if (!HasNonCopyUse)
419  return false;
420  }
421 
422  // Heuristics #3: If the common subexpression is used by PHIs, do not reuse
423  // it unless the defined value is already used in the BB of the new use.
424  bool HasPHI = false;
426  for (MachineInstr &MI : MRI->use_nodbg_instructions(CSReg)) {
427  HasPHI |= MI.isPHI();
428  CSBBs.insert(MI.getParent());
429  }
430 
431  if (!HasPHI)
432  return true;
433  return CSBBs.count(MI->getParent());
434 }
435 
436 void MachineCSE::EnterScope(MachineBasicBlock *MBB) {
437  DEBUG(dbgs() << "Entering: " << MBB->getName() << '\n');
438  ScopeType *Scope = new ScopeType(VNT);
439  ScopeMap[MBB] = Scope;
440 }
441 
442 void MachineCSE::ExitScope(MachineBasicBlock *MBB) {
443  DEBUG(dbgs() << "Exiting: " << MBB->getName() << '\n');
445  assert(SI != ScopeMap.end());
446  delete SI->second;
447  ScopeMap.erase(SI);
448 }
449 
450 bool MachineCSE::ProcessBlock(MachineBasicBlock *MBB) {
451  bool Changed = false;
452 
454  SmallVector<unsigned, 2> ImplicitDefsToUpdate;
455  SmallVector<unsigned, 2> ImplicitDefs;
456  for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E; ) {
457  MachineInstr *MI = &*I;
458  ++I;
459 
460  if (!isCSECandidate(MI))
461  continue;
462 
463  bool FoundCSE = VNT.count(MI);
464  if (!FoundCSE) {
465  // Using trivial copy propagation to find more CSE opportunities.
466  if (PerformTrivialCopyPropagation(MI, MBB)) {
467  Changed = true;
468 
469  // After coalescing MI itself may become a copy.
470  if (MI->isCopyLike())
471  continue;
472 
473  // Try again to see if CSE is possible.
474  FoundCSE = VNT.count(MI);
475  }
476  }
477 
478  // Commute commutable instructions.
479  bool Commuted = false;
480  if (!FoundCSE && MI->isCommutable()) {
481  MachineInstr *NewMI = TII->commuteInstruction(MI);
482  if (NewMI) {
483  Commuted = true;
484  FoundCSE = VNT.count(NewMI);
485  if (NewMI != MI) {
486  // New instruction. It doesn't need to be kept.
487  NewMI->eraseFromParent();
488  Changed = true;
489  } else if (!FoundCSE)
490  // MI was changed but it didn't help, commute it back!
491  (void)TII->commuteInstruction(MI);
492  }
493  }
494 
495  // If the instruction defines physical registers and the values *may* be
496  // used, then it's not safe to replace it with a common subexpression.
497  // It's also not safe if the instruction uses physical registers.
498  bool CrossMBBPhysDef = false;
499  SmallSet<unsigned, 8> PhysRefs;
500  SmallVector<unsigned, 2> PhysDefs;
501  bool PhysUseDef = false;
502  if (FoundCSE && hasLivePhysRegDefUses(MI, MBB, PhysRefs,
503  PhysDefs, PhysUseDef)) {
504  FoundCSE = false;
505 
506  // ... Unless the CS is local or is in the sole predecessor block
507  // and it also defines the physical register which is not clobbered
508  // in between and the physical register uses were not clobbered.
509  // This can never be the case if the instruction both uses and
510  // defines the same physical register, which was detected above.
511  if (!PhysUseDef) {
512  unsigned CSVN = VNT.lookup(MI);
513  MachineInstr *CSMI = Exps[CSVN];
514  if (PhysRegDefsReach(CSMI, MI, PhysRefs, PhysDefs, CrossMBBPhysDef))
515  FoundCSE = true;
516  }
517  }
518 
519  if (!FoundCSE) {
520  VNT.insert(MI, CurrVN++);
521  Exps.push_back(MI);
522  continue;
523  }
524 
525  // Found a common subexpression, eliminate it.
526  unsigned CSVN = VNT.lookup(MI);
527  MachineInstr *CSMI = Exps[CSVN];
528  DEBUG(dbgs() << "Examining: " << *MI);
529  DEBUG(dbgs() << "*** Found a common subexpression: " << *CSMI);
530 
531  // Check if it's profitable to perform this CSE.
532  bool DoCSE = true;
533  unsigned NumDefs = MI->getDesc().getNumDefs() +
534  MI->getDesc().getNumImplicitDefs();
535 
536  for (unsigned i = 0, e = MI->getNumOperands(); NumDefs && i != e; ++i) {
537  MachineOperand &MO = MI->getOperand(i);
538  if (!MO.isReg() || !MO.isDef())
539  continue;
540  unsigned OldReg = MO.getReg();
541  unsigned NewReg = CSMI->getOperand(i).getReg();
542 
543  // Go through implicit defs of CSMI and MI, if a def is not dead at MI,
544  // we should make sure it is not dead at CSMI.
545  if (MO.isImplicit() && !MO.isDead() && CSMI->getOperand(i).isDead())
546  ImplicitDefsToUpdate.push_back(i);
547 
548  // Keep track of implicit defs of CSMI and MI, to clear possibly
549  // made-redundant kill flags.
550  if (MO.isImplicit() && !MO.isDead() && OldReg == NewReg)
551  ImplicitDefs.push_back(OldReg);
552 
553  if (OldReg == NewReg) {
554  --NumDefs;
555  continue;
556  }
557 
558  assert(TargetRegisterInfo::isVirtualRegister(OldReg) &&
560  "Do not CSE physical register defs!");
561 
562  if (!isProfitableToCSE(NewReg, OldReg, CSMI, MI)) {
563  DEBUG(dbgs() << "*** Not profitable, avoid CSE!\n");
564  DoCSE = false;
565  break;
566  }
567 
568  // Don't perform CSE if the result of the old instruction cannot exist
569  // within the register class of the new instruction.
570  const TargetRegisterClass *OldRC = MRI->getRegClass(OldReg);
571  if (!MRI->constrainRegClass(NewReg, OldRC)) {
572  DEBUG(dbgs() << "*** Not the same register class, avoid CSE!\n");
573  DoCSE = false;
574  break;
575  }
576 
577  CSEPairs.push_back(std::make_pair(OldReg, NewReg));
578  --NumDefs;
579  }
580 
581  // Actually perform the elimination.
582  if (DoCSE) {
583  for (unsigned i = 0, e = CSEPairs.size(); i != e; ++i) {
584  unsigned OldReg = CSEPairs[i].first;
585  unsigned NewReg = CSEPairs[i].second;
586  // OldReg may have been unused but is used now, clear the Dead flag
587  MachineInstr *Def = MRI->getUniqueVRegDef(NewReg);
588  assert(Def != nullptr && "CSEd register has no unique definition?");
589  Def->clearRegisterDeads(NewReg);
590  // Replace with NewReg and clear kill flags which may be wrong now.
591  MRI->replaceRegWith(OldReg, NewReg);
592  MRI->clearKillFlags(NewReg);
593  }
594 
595  // Go through implicit defs of CSMI and MI, if a def is not dead at MI,
596  // we should make sure it is not dead at CSMI.
597  for (unsigned i = 0, e = ImplicitDefsToUpdate.size(); i != e; ++i)
598  CSMI->getOperand(ImplicitDefsToUpdate[i]).setIsDead(false);
599 
600  // Go through implicit defs of CSMI and MI, and clear the kill flags on
601  // their uses in all the instructions between CSMI and MI.
602  // We might have made some of the kill flags redundant, consider:
603  // subs ... %NZCV<imp-def> <- CSMI
604  // csinc ... %NZCV<imp-use,kill> <- this kill flag isn't valid anymore
605  // subs ... %NZCV<imp-def> <- MI, to be eliminated
606  // csinc ... %NZCV<imp-use,kill>
607  // Since we eliminated MI, and reused a register imp-def'd by CSMI
608  // (here %NZCV), that register, if it was killed before MI, should have
609  // that kill flag removed, because it's lifetime was extended.
610  if (CSMI->getParent() == MI->getParent()) {
611  for (MachineBasicBlock::iterator II = CSMI, IE = MI; II != IE; ++II)
612  for (auto ImplicitDef : ImplicitDefs)
613  if (MachineOperand *MO = II->findRegisterUseOperand(
614  ImplicitDef, /*isKill=*/true, TRI))
615  MO->setIsKill(false);
616  } else {
617  // If the instructions aren't in the same BB, bail out and clear the
618  // kill flag on all uses of the imp-def'd register.
619  for (auto ImplicitDef : ImplicitDefs)
620  MRI->clearKillFlags(ImplicitDef);
621  }
622 
623  if (CrossMBBPhysDef) {
624  // Add physical register defs now coming in from a predecessor to MBB
625  // livein list.
626  while (!PhysDefs.empty()) {
627  unsigned LiveIn = PhysDefs.pop_back_val();
628  if (!MBB->isLiveIn(LiveIn))
629  MBB->addLiveIn(LiveIn);
630  }
631  ++NumCrossBBCSEs;
632  }
633 
634  MI->eraseFromParent();
635  ++NumCSEs;
636  if (!PhysRefs.empty())
637  ++NumPhysCSEs;
638  if (Commuted)
639  ++NumCommutes;
640  Changed = true;
641  } else {
642  VNT.insert(MI, CurrVN++);
643  Exps.push_back(MI);
644  }
645  CSEPairs.clear();
646  ImplicitDefsToUpdate.clear();
647  ImplicitDefs.clear();
648  }
649 
650  return Changed;
651 }
652 
653 /// ExitScopeIfDone - Destroy scope for the MBB that corresponds to the given
654 /// dominator tree node if its a leaf or all of its children are done. Walk
655 /// up the dominator tree to destroy ancestors which are now done.
656 void
657 MachineCSE::ExitScopeIfDone(MachineDomTreeNode *Node,
659  if (OpenChildren[Node])
660  return;
661 
662  // Pop scope.
663  ExitScope(Node->getBlock());
664 
665  // Now traverse upwards to pop ancestors whose offsprings are all done.
666  while (MachineDomTreeNode *Parent = Node->getIDom()) {
667  unsigned Left = --OpenChildren[Parent];
668  if (Left != 0)
669  break;
670  ExitScope(Parent->getBlock());
671  Node = Parent;
672  }
673 }
674 
675 bool MachineCSE::PerformCSE(MachineDomTreeNode *Node) {
679 
680  CurrVN = 0;
681 
682  // Perform a DFS walk to determine the order of visit.
683  WorkList.push_back(Node);
684  do {
685  Node = WorkList.pop_back_val();
686  Scopes.push_back(Node);
687  const std::vector<MachineDomTreeNode*> &Children = Node->getChildren();
688  unsigned NumChildren = Children.size();
689  OpenChildren[Node] = NumChildren;
690  for (unsigned i = 0; i != NumChildren; ++i) {
691  MachineDomTreeNode *Child = Children[i];
692  WorkList.push_back(Child);
693  }
694  } while (!WorkList.empty());
695 
696  // Now perform CSE.
697  bool Changed = false;
698  for (unsigned i = 0, e = Scopes.size(); i != e; ++i) {
699  MachineDomTreeNode *Node = Scopes[i];
700  MachineBasicBlock *MBB = Node->getBlock();
701  EnterScope(MBB);
702  Changed |= ProcessBlock(MBB);
703  // If it's a leaf node, it's done. Traverse upwards to pop ancestors.
704  ExitScopeIfDone(Node, OpenChildren);
705  }
706 
707  return Changed;
708 }
709 
710 bool MachineCSE::runOnMachineFunction(MachineFunction &MF) {
711  if (skipOptnoneFunction(*MF.getFunction()))
712  return false;
713 
714  TII = MF.getSubtarget().getInstrInfo();
715  TRI = MF.getSubtarget().getRegisterInfo();
716  MRI = &MF.getRegInfo();
717  AA = &getAnalysis<AliasAnalysis>();
718  DT = &getAnalysis<MachineDominatorTree>();
719  LookAheadLimit = TII->getMachineCSELookAheadLimit();
720  return PerformCSE(DT->getRootNode());
721 }
bool isImplicit() const
void push_back(const T &Elt)
Definition: SmallVector.h:222
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
STATISTIC(NumFunctions,"Total number of functions")
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
Definition: MCInstrDesc.h:500
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:191
void initializeMachineCSEPass(PassRegistry &)
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:579
bool isDead() const
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
size_type count(PtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
Definition: SmallPtrSet.h:276
void addLiveIn(unsigned Reg)
Adds the specified register as a live in.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:264
void setIsDead(bool Val=true)
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:419
Special DenseMapInfo traits to compare MachineInstr* by value of the instruction rather than by point...
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Definition: SmallSet.h:44
AnalysisUsage & addRequired()
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:70
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
bool isPHI() const
Definition: MachineInstr.h:757
T LLVM_ATTRIBUTE_UNUSED_RESULT pop_back_val()
Definition: SmallVector.h:406
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:75
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:566
Reg
All possible values of the reg field in the ModR/M byte.
RecyclingAllocator - This class wraps an Allocator, adding the functionality of recycling deleted obj...
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:271
char & MachineCSEID
MachineCSE - This pass performs global CSE on machine instructions.
Definition: MachineCSE.cpp:110
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Definition: SmallVector.h:57
machine cse
Definition: MachineCSE.cpp:115
Base class for the actual dominator tree node.
bool isCopyLike() const
Return true if the instruction behaves like a copy.
Definition: MachineInstr.h:790
AnalysisUsage & addPreservedID(const void *ID)
COFF::MachineTypes Machine
Definition: COFFYAML.cpp:301
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:120
TargetInstrInfo - Interface to description of machine instruction set.
bool isDebugValue() const
Definition: MachineInstr.h:748
bool isImplicitDef() const
Definition: MachineInstr.h:759
BumpPtrAllocatorImpl BumpPtrAllocator
The standard BumpPtrAllocator which just uses the default template paramaters.
Definition: Allocator.h:342
bundle_iterator< MachineInstr, instr_iterator > iterator
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
machine Machine Common Subexpression Elimination
Definition: MachineCSE.cpp:115
void clearRegisterDeads(unsigned Reg)
Clear all dead flags on operands defining register Reg.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:32
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:264
bool isCopy() const
Definition: MachineInstr.h:778
MCRegAliasIterator enumerates all registers aliasing Reg.
Represent the analysis usage information of a pass.
bool isPosition() const
Definition: MachineInstr.h:746
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore...
const std::vector< DomTreeNodeBase< NodeT > * > & getChildren() const
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:69
bool isInvariantLoad(AliasAnalysis *AA) const
Return true if this instruction is loading from a location whose value is invariant across the functi...
#define INITIALIZE_AG_DEPENDENCY(depName)
Definition: PassSupport.h:72
unsigned getSubReg() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void setIsKill(bool Val=true)
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:53
machine Machine Common Subexpression false
Definition: MachineCSE.cpp:115
DomTreeNodeBase< NodeT > * getIDom() const
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
Definition: SmallPtrSet.h:299
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:861
bool isInlineAsm() const
Definition: MachineInstr.h:760
bool isSuccessor(const MachineBasicBlock *MBB) const
isSuccessor - Return true if the specified MBB is a successor of this block.
bool isKill() const
Definition: MachineInstr.h:758
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:263
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:123
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
StringRef getName() const
getName - Return the name of the corresponding LLVM basic block, or "(null)".
NodeT * getBlock() const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:51
bundle_iterator< const MachineInstr, const_instr_iterator > const_iterator
bool isLiveIn(unsigned Reg) const
isLiveIn - Return true if the specified register is in the live in set.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
void setReg(unsigned Reg)
Change the register this operand corresponds to.
#define I(x, y, z)
Definition: MD5.cpp:54
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:403
unsigned getReg() const
getReg - Returns the register number.
bool isCommutable(QueryType Type=IgnoreBundle) const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged.
Definition: MachineInstr.h:607
virtual const TargetInstrInfo * getInstrInfo() const
#define DEBUG(X)
Definition: Debug.h:92
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
INITIALIZE_PASS_BEGIN(MachineCSE,"machine-cse","Machine Common Subexpression Elimination", false, false) INITIALIZE_PASS_END(MachineCSE
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
unsigned pred_size() const