10 #ifndef LLVM_LIB_TARGET_ARM_ARMASMBACKEND_H
11 #define LLVM_LIB_TARGET_ARM_ARMASMBACKEND_H
26 ARMAsmBackend(
const Target &
T,
const Triple &TT,
bool IsLittle)
28 isThumbMode(TT.getArchName().startswith(
"thumb")),
29 IsLittleEndian(IsLittle) {}
31 ~ARMAsmBackend()
override {
delete STI; }
33 unsigned getNumFixupKinds()
const override {
37 bool hasNOP()
const {
return STI->getFeatureBits()[ARM::HasV6T2Ops]; }
46 bool &IsResolved)
override;
49 uint64_t
Value,
bool IsPCRel)
const override;
53 bool mayNeedRelaxation(
const MCInst &Inst)
const override;
59 void relaxInstruction(
const MCInst &Inst,
MCInst &Res)
const override;
61 bool writeNopData(uint64_t Count,
MCObjectWriter *OW)
const override;
66 bool isThumb()
const {
return isThumbMode; }
67 void setIsThumb(
bool it) { isThumbMode = it; }
68 bool isLittle()
const {
return IsLittleEndian; }
This represents an "assembler immediate".
Defines the object file and target independent interfaces used by the assembler backend to write nati...
static bool isThumb(const MCSubtargetInfo &STI)
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Encapsulates the layout of an assembly file at a particular point in time.
static unsigned getRelaxedOpcode(unsigned Op)
static uint64_t getPointerSize(const Value *V, const DataLayout &DL, const TargetLibraryInfo *TLI)
Instances of this class represent a single low-level machine instruction.
Flag
These should be considered private to the implementation of the MCInstrDesc class.
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
MCFixupKind
Extensible enumeration to represent the type of a fixup.
MCSubtargetInfo * createARMMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Create a ARM MCSubtargetInfo instance.
Triple - Helper class for working with autoconf configuration names.
PowerPC TLS Dynamic Call Fixup
Target - Wrapper for Target specific information.
MCSubtargetInfo - Generic base class for all target subtargets.
Target independent information on a fixup kind.
const ARM::ArchExtKind Kind
LLVM Value Representation.
Generic interface to target specific assembler backends.