34 #define GET_REGINFO_TARGET_DESC
35 #include "AArch64GenRegisterInfo.inc"
39 cl::desc(
"Reserve X18, making it unavailable as GPR"));
46 assert(MF &&
"Invalid MachineFunction pointer.");
50 return CSR_AArch64_NoRegs_SaveList;
52 return CSR_AArch64_AllRegs_SaveList;
54 return CSR_AArch64_AAPCS_SaveList;
62 return CSR_AArch64_NoRegs_RegMask;
64 return CSR_AArch64_AllRegs_RegMask;
66 return CSR_AArch64_AAPCS_RegMask;
71 return CSR_AArch64_TLS_Darwin_RegMask;
74 return CSR_AArch64_TLS_ELF_RegMask;
88 return CSR_AArch64_AAPCS_ThisReturn_RegMask;
97 Reserved.
set(AArch64::SP);
98 Reserved.
set(AArch64::XZR);
99 Reserved.
set(AArch64::WSP);
100 Reserved.
set(AArch64::WZR);
103 Reserved.
set(AArch64::FP);
104 Reserved.
set(AArch64::W29);
108 Reserved.
set(AArch64::X18);
109 Reserved.
set(AArch64::W18);
113 Reserved.
set(AArch64::X19);
114 Reserved.
set(AArch64::W19);
121 unsigned Reg)
const {
148 unsigned Kind)
const {
149 return &AArch64::GPR64RegClass;
154 if (RC == &AArch64::CCRRegClass)
155 return &AArch64::GPR64RegClass;
204 bool requiresRealignment =
215 return TFI->
hasFP(MF) ? AArch64::FP : AArch64::SP;
257 int64_t Offset)
const {
259 assert(i < MI->getNumOperands() &&
260 "Instr doesn't have FrameIndex operand!");
286 int64_t FPOffset = Offset - 16 * 20;
318 int64_t Offset)
const {
319 assert(Offset <= INT_MAX &&
"Offset too big to fit in int.");
320 assert(MI &&
"Unable to get the legal offset for nil instruction.");
321 int SaveOffset = Offset;
330 int64_t Offset)
const {
333 if (Ins != MBB->
end())
334 DL = Ins->getDebugLoc();
338 const MCInstrDesc &MCID = TII->get(AArch64::ADDXri);
343 BuildMI(*MBB, Ins, DL, MCID, BaseReg)
350 int64_t Offset)
const {
356 assert(i < MI.
getNumOperands() &&
"Instr doesn't have FrameIndex operand!");
362 assert(Done &&
"Unable to resolve frame index!");
367 int SPAdj,
unsigned FIOperandNum,
369 assert(SPAdj == 0 &&
"Unexpected");
399 "Emergency spill slot is out of reach");
404 unsigned ScratchReg =
416 switch (RC->
getID()) {
419 case AArch64::GPR32RegClassID:
420 case AArch64::GPR32spRegClassID:
421 case AArch64::GPR32allRegClassID:
422 case AArch64::GPR64spRegClassID:
423 case AArch64::GPR64allRegClassID:
424 case AArch64::GPR64RegClassID:
425 case AArch64::GPR32commonRegClassID:
426 case AArch64::GPR64commonRegClassID:
431 case AArch64::FPR8RegClassID:
432 case AArch64::FPR16RegClassID:
433 case AArch64::FPR32RegClassID:
434 case AArch64::FPR64RegClassID:
435 case AArch64::FPR128RegClassID:
438 case AArch64::DDRegClassID:
439 case AArch64::DDDRegClassID:
440 case AArch64::DDDDRegClassID:
441 case AArch64::QQRegClassID:
442 case AArch64::QQQRegClassID:
443 case AArch64::QQQQRegClassID:
446 case AArch64::FPR128_loRegClassID:
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
bool isReservedReg(const MachineFunction &MF, unsigned Reg) const
Alignment of stack for function (3 bits) stored as log2 of alignment with +1 bias 0 means unaligned (...
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const override
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
int resolveFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg, bool PreferFP=false) const
static cl::opt< bool > ReserveX18("aarch64-reserve-x18", cl::Hidden, cl::desc("Reserve X18, making it unavailable as GPR"))
Describe properties that are true of each instruction in the target description file.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
A Stackmap instruction captures the location of live variables at its position in the instruction str...
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
unsigned getID() const
getID() - Return the register class ID number.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
needsFrameBaseReg - Returns true if the instruction's frame index reference would be better served by...
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
bool hasAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return true if the attribute exists at the given index.
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
const uint32_t * getThisReturnPreservedMask(const MachineFunction &MF, CallingConv::ID) const
getThisReturnPreservedMask - Returns a call preserved mask specific to the case that 'returned' is on...
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
int64_t getLocalFrameSize() const
Get the size of the local object blob.
bool canRealignStack(const MachineFunction &MF) const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const HexagonInstrInfo * TII
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
bool cannotEliminateFrame(const MachineFunction &MF) const
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
int isAArch64FrameOffsetLegal(const MachineInstr &MI, int &Offset, bool *OutUseUnscaledOp=nullptr, unsigned *OutUnscaledOp=nullptr, int *EmittableOffset=nullptr)
Check if the Offset is a valid frame offset for MI.
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
bool hasBasePointer(const MachineFunction &MF) const
BitVector getReservedRegs(const MachineFunction &MF) const override
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
static unsigned getShifterImm(AArch64_AM::ShiftExtendType ST, unsigned Imm)
getShifterImm - Encode the shift type and amount: imm: 6-bit shift amount shifter: 000 ==> lsl 001 ==...
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
const MachineBasicBlock * getParent() const
bool isDebugValue() const
bundle_iterator< MachineInstr, instr_iterator > iterator
Patchable call instruction - this instruction represents a call to a constant address, followed by a series of NOPs.
void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override
void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, int Offset, const TargetInstrInfo *TII, MachineInstr::MIFlag=MachineInstr::NoFlags, bool SetNZCV=false)
emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg plus Offset.
const MachineOperand & getOperand(unsigned i) const
bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const AArch64InstrInfo *TII)
rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the FP.
bool needsStackRealignment(const MachineFunction &MF) const override
unsigned getFrameRegister(const MachineFunction &MF) const override
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
const uint32_t * getTLSCallPreservedMask() const
Triple - Helper class for working with autoconf configuration names.
bool isScavengingFrameIndex(int FI) const
Query whether a frame index is a scavenging frame index.
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X or iOS).
bool hasCalls() const
Return true if the current function has any function calls.
bool requiresRegisterScavenging(const MachineFunction &MF) const override
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const MachineInstrBuilder & addFrameIndex(int Idx) const
AttributeSet getAttributes() const
Return the attribute list for this Function.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const override
Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx at the beginning of the basic ...
Representation of each machine instruction.
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
AArch64RegisterInfo(const Triple &TT)
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
const ARM::ArchExtKind Kind
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
unsigned getBaseRegister() const
bool useFPForScavengingIndex(const MachineFunction &MF) const override
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override