| addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) | llvm::TargetLoweringBase | inlineprotected |
| AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) | llvm::TargetLoweringBase | inlineprotected |
| addRegisterClass(MVT VT, const TargetRegisterClass *RC) | llvm::TargetLoweringBase | inlineprotected |
| AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const | llvm::TargetLowering | virtual |
| allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace=0, unsigned Align=1, bool *=nullptr) const | llvm::TargetLoweringBase | inlinevirtual |
| allowTruncateForTailCall(Type *, Type *) const | llvm::TargetLoweringBase | inlinevirtual |
| ArgListTy typedef | llvm::TargetLowering | |
| AsmOperandInfoVector typedef | llvm::TargetLowering | |
| AtomicRMWExpansionKind enum name | llvm::TargetLoweringBase | |
| BooleanContent enum name | llvm::TargetLoweringBase | |
| BuildSDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode * > *Created) const | llvm::TargetLowering | |
| BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, std::vector< SDNode * > *Created) const | llvm::TargetLowering | inlinevirtual |
| BuildUDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode * > *Created) const | llvm::TargetLowering | |
| C_Memory enum value | llvm::TargetLowering | |
| C_Other enum value | llvm::TargetLowering | |
| C_Register enum value | llvm::TargetLowering | |
| C_RegisterClass enum value | llvm::TargetLowering | |
| C_Unknown enum value | llvm::TargetLowering | |
| canCombineStoreAndExtract(Type *VectorTy, Value *Idx, unsigned &Cost) const | llvm::TargetLoweringBase | inlinevirtual |
| CanLowerReturn(CallingConv::ID, MachineFunction &, bool, const SmallVectorImpl< ISD::OutputArg > &, LLVMContext &) const | llvm::TargetLowering | inlinevirtual |
| canOpTrap(unsigned Op, EVT VT) const | llvm::TargetLoweringBase | virtual |
| clearOperationActions() | llvm::TargetLoweringBase | inlineprotected |
| clearRegisterClasses() | llvm::TargetLoweringBase | inlineprotected |
| combineRepeatedFPDivisors(unsigned NumUsers) const | llvm::TargetLowering | inlinevirtual |
| ComputeConstraintToUse(AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=nullptr) const | llvm::TargetLowering | virtual |
| computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth=0) const | llvm::TargetLowering | virtual |
| ComputeNumSignBitsForTargetNode(SDValue Op, const SelectionDAG &DAG, unsigned Depth=0) const | llvm::TargetLowering | virtual |
| computeRegisterProperties(const TargetRegisterInfo *TRI) | llvm::TargetLoweringBase | protected |
| ConstraintType enum name | llvm::TargetLowering | |
| ConstraintWeight enum name | llvm::TargetLowering | |
| createFastISel(FunctionLoweringInfo &, const TargetLibraryInfo *) const | llvm::TargetLowering | inlinevirtual |
| Custom enum value | llvm::TargetLoweringBase | |
| CW_Best enum value | llvm::TargetLowering | |
| CW_Better enum value | llvm::TargetLowering | |
| CW_Constant enum value | llvm::TargetLowering | |
| CW_Default enum value | llvm::TargetLowering | |
| CW_Good enum value | llvm::TargetLowering | |
| CW_Invalid enum value | llvm::TargetLowering | |
| CW_Memory enum value | llvm::TargetLowering | |
| CW_Okay enum value | llvm::TargetLowering | |
| CW_Register enum value | llvm::TargetLowering | |
| CW_SpecificReg enum value | llvm::TargetLowering | |
| EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *BB) const override | llvm::MSP430TargetLowering | virtual |
| emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord, bool IsStore, bool IsLoad) const | llvm::TargetLoweringBase | inlinevirtual |
| emitLoadLinked(IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const | llvm::TargetLoweringBase | inlinevirtual |
| emitPatchPoint(MachineInstr *MI, MachineBasicBlock *MBB) const | llvm::TargetLoweringBase | protected |
| EmitShiftInstr(MachineInstr *MI, MachineBasicBlock *BB) const | llvm::MSP430TargetLowering | |
| emitStoreConditional(IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const | llvm::TargetLoweringBase | inlinevirtual |
| emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord, bool IsStore, bool IsLoad) const | llvm::TargetLoweringBase | inlinevirtual |
| enableAggressiveFMAFusion(EVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
| EnableExtLdPromotion | llvm::TargetLoweringBase | protected |
| enableExtLdPromotion() const | llvm::TargetLoweringBase | inline |
| Expand enum value | llvm::TargetLoweringBase | |
| expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const | llvm::TargetLowering | |
| ExpandInlineAsm(CallInst *) const | llvm::TargetLowering | inlinevirtual |
| expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT, SelectionDAG &DAG, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) const | llvm::TargetLowering | |
| findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const | llvm::TargetLoweringBase | protectedvirtual |
| functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg) const | llvm::TargetLowering | inlinevirtual |
| GetAddrModeArguments(IntrinsicInst *, SmallVectorImpl< Value * > &, Type *&, unsigned AddrSpace=0) const | llvm::TargetLoweringBase | inlinevirtual |
| getBooleanContents(bool isVec, bool isFloat) const | llvm::TargetLoweringBase | inline |
| getBooleanContents(EVT Type) const | llvm::TargetLoweringBase | inline |
| getBypassSlowDivWidths() const | llvm::TargetLoweringBase | inline |
| getByValTypeAlignment(Type *Ty, const DataLayout &DL) const | llvm::TargetLoweringBase | virtual |
| getClearCacheBuiltinName() const | llvm::TargetLowering | inlinevirtual |
| getCmpLibcallCC(RTLIB::Libcall Call) const | llvm::TargetLoweringBase | inline |
| getCmpLibcallReturnType() const | llvm::TargetLoweringBase | virtual |
| getCondCodeAction(ISD::CondCode CC, MVT VT) const | llvm::TargetLoweringBase | inline |
| getConstraintType(StringRef Constraint) const override | llvm::MSP430TargetLowering | virtual |
| getExceptionPointerRegister() const | llvm::TargetLoweringBase | inline |
| getExceptionSelectorRegister() const | llvm::TargetLoweringBase | inline |
| getExtendForContent(BooleanContent Content) | llvm::TargetLoweringBase | inlinestatic |
| getIndexedLoadAction(unsigned IdxMode, MVT VT) const | llvm::TargetLoweringBase | inline |
| getIndexedStoreAction(unsigned IdxMode, MVT VT) const | llvm::TargetLoweringBase | inline |
| getInlineAsmMemConstraint(StringRef ConstraintCode) const | llvm::TargetLowering | inlinevirtual |
| getInsertFencesForAtomic() const | llvm::TargetLoweringBase | inline |
| getJumpBufAlignment() const | llvm::TargetLoweringBase | inline |
| getJumpBufSize() const | llvm::TargetLoweringBase | inline |
| getJumpTableEncoding() const | llvm::TargetLowering | virtual |
| getLibcallCallingConv(RTLIB::Libcall Call) const | llvm::TargetLoweringBase | inline |
| getLibcallName(RTLIB::Libcall Call) const | llvm::TargetLoweringBase | inline |
| getLoadExtAction(unsigned ExtType, EVT ValVT, EVT MemVT) const | llvm::TargetLoweringBase | inline |
| getMaxStoresPerMemcpy(bool OptSize) const | llvm::TargetLoweringBase | inline |
| getMaxStoresPerMemmove(bool OptSize) const | llvm::TargetLoweringBase | inline |
| getMaxStoresPerMemset(bool OptSize) const | llvm::TargetLoweringBase | inline |
| getMaxSupportedInterleaveFactor() const | llvm::TargetLoweringBase | inlinevirtual |
| getMinFunctionAlignment() const | llvm::TargetLoweringBase | inline |
| getMinimumJumpTableEntries() const | llvm::TargetLoweringBase | inline |
| getMinStackArgumentAlignment() const | llvm::TargetLoweringBase | inline |
| getMultipleConstraintMatchWeight(AsmOperandInfo &info, int maIndex) const | llvm::TargetLowering | virtual |
| getNumRegisters(LLVMContext &Context, EVT VT) const | llvm::TargetLoweringBase | inline |
| getOperationAction(unsigned Op, EVT VT) const | llvm::TargetLoweringBase | inline |
| getOptimalMemOpType(uint64_t, unsigned, unsigned, bool, bool, bool, MachineFunction &) const | llvm::TargetLoweringBase | inlinevirtual |
| getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const | llvm::TargetLowering | virtual |
| getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const | llvm::TargetLowering | virtual |
| getPointerTy(const DataLayout &DL, uint32_t AS=0) const | llvm::TargetLoweringBase | inline |
| getPreferredVectorAction(EVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
| getPrefFunctionAlignment() const | llvm::TargetLoweringBase | inline |
| getPrefLoopAlignment(MachineLoop *ML=nullptr) const | llvm::TargetLoweringBase | inlinevirtual |
| getPreIndexedAddressParts(SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const | llvm::TargetLowering | inlinevirtual |
| getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI, unsigned &RefinementSteps) const | llvm::TargetLowering | inlinevirtual |
| getRegClassFor(MVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
| getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override | llvm::MSP430TargetLowering | virtual |
| getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const | llvm::TargetLowering | inlinevirtual |
| getRegisterType(MVT VT) const | llvm::TargetLoweringBase | inline |
| getRegisterType(LLVMContext &Context, EVT VT) const | llvm::TargetLoweringBase | inline |
| getRepRegClassCostFor(MVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
| getRepRegClassFor(MVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
| getReturnAddressFrameIndex(SelectionDAG &DAG) const | llvm::MSP430TargetLowering | |
| getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI, unsigned &RefinementSteps, bool &UseOneConstNR) const | llvm::TargetLowering | inlinevirtual |
| getScalarShiftAmountTy(const DataLayout &, EVT) const override | llvm::MSP430TargetLowering | inlinevirtual |
| getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS=0) const | llvm::TargetLoweringBase | inlinevirtual |
| getSchedulingPreference() const | llvm::TargetLoweringBase | inline |
| getSchedulingPreference(SDNode *) const | llvm::TargetLoweringBase | inlinevirtual |
| getScratchRegisters(CallingConv::ID CC) const | llvm::TargetLowering | inlinevirtual |
| getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const | llvm::TargetLoweringBase | virtual |
| getShiftAmountTy(EVT LHSTy, const DataLayout &DL) const | llvm::TargetLoweringBase | |
| getSimpleValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const | llvm::TargetLoweringBase | inline |
| getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const | llvm::TargetLowering | virtual |
| getStackCookieLocation(unsigned &, unsigned &) const | llvm::TargetLoweringBase | inlinevirtual |
| getStackPointerRegisterToSaveRestore() const | llvm::TargetLoweringBase | inline |
| getTargetMachine() const | llvm::TargetLoweringBase | inline |
| getTargetNodeName(unsigned Opcode) const override | llvm::MSP430TargetLowering | virtual |
| getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, unsigned) const | llvm::TargetLoweringBase | inlinevirtual |
| getTruncStoreAction(EVT ValVT, EVT MemVT) const | llvm::TargetLoweringBase | inline |
| getTypeAction(LLVMContext &Context, EVT VT) const | llvm::TargetLoweringBase | inline |
| getTypeAction(MVT VT) const | llvm::TargetLoweringBase | inline |
| getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT, ISD::NodeType) const | llvm::TargetLowering | inlinevirtual |
| getTypeLegalizationCost(const DataLayout &DL, Type *Ty) const | llvm::TargetLoweringBase | |
| getTypeToExpandTo(LLVMContext &Context, EVT VT) const | llvm::TargetLoweringBase | inline |
| getTypeToPromoteTo(unsigned Op, MVT VT) const | llvm::TargetLoweringBase | inline |
| getTypeToTransformTo(LLVMContext &Context, EVT VT) const | llvm::TargetLoweringBase | inline |
| getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const | llvm::TargetLoweringBase | inline |
| getValueTypeActions() const | llvm::TargetLoweringBase | inline |
| getVectorIdxTy(const DataLayout &DL) const | llvm::TargetLoweringBase | inlinevirtual |
| getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const | llvm::TargetLoweringBase | |
| HandleByVal(CCState *, unsigned &, unsigned) const | llvm::TargetLowering | inlinevirtual |
| hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const | llvm::TargetLoweringBase | inline |
| hasExtractBitsInsn() const | llvm::TargetLoweringBase | inline |
| hasFloatingPointExceptions() const | llvm::TargetLoweringBase | inline |
| hasLoadLinkedStoreConditional() const | llvm::TargetLoweringBase | inlinevirtual |
| hasMultipleConditionRegisters() const | llvm::TargetLoweringBase | inline |
| hasPairedLoad(Type *, unsigned &) const | llvm::TargetLoweringBase | inlinevirtual |
| hasPairedLoad(EVT, unsigned &) const | llvm::TargetLoweringBase | inlinevirtual |
| hasTargetDAGCombine(ISD::NodeType NT) const | llvm::TargetLoweringBase | inline |
| initActions() | llvm::TargetLoweringBase | protected |
| InstructionOpcodeToISD(unsigned Opcode) const | llvm::TargetLoweringBase | |
| isCheapToSpeculateCtlz() const | llvm::TargetLoweringBase | inlinevirtual |
| isCheapToSpeculateCttz() const | llvm::TargetLoweringBase | inlinevirtual |
| isCondCodeLegal(ISD::CondCode CC, MVT VT) const | llvm::TargetLoweringBase | inline |
| isConstFalseVal(const SDNode *N) const | llvm::TargetLowering | |
| isConstTrueVal(const SDNode *N) const | llvm::TargetLowering | |
| isDesirableToCommuteWithShift(const SDNode *N) const | llvm::TargetLowering | inlinevirtual |
| IsDesirableToPromoteOp(SDValue, EVT &) const | llvm::TargetLowering | inlinevirtual |
| isDesirableToTransformToIntegerOp(unsigned, EVT) const | llvm::TargetLowering | inlinevirtual |
| isExtFree(const Instruction *I) const | llvm::TargetLoweringBase | inline |
| isExtFreeImpl(const Instruction *I) const | llvm::TargetLoweringBase | inlineprotectedvirtual |
| isExtractSubvectorCheap(EVT ResVT, unsigned Index) const | llvm::TargetLoweringBase | inlinevirtual |
| isFAbsFree(EVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
| isFMAFasterThanFMulAndFAdd(EVT) const | llvm::TargetLoweringBase | inlinevirtual |
| isFNegFree(EVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
| isFPExtFree(EVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
| isFPImmLegal(const APFloat &, EVT) const | llvm::TargetLoweringBase | inlinevirtual |
| isFsqrtCheap() const | llvm::TargetLoweringBase | inline |
| isGAPlusOffset(SDNode *N, const GlobalValue *&GA, int64_t &Offset) const | llvm::TargetLowering | virtual |
| isIndexedLoadLegal(unsigned IdxMode, EVT VT) const | llvm::TargetLoweringBase | inline |
| isIndexedStoreLegal(unsigned IdxMode, EVT VT) const | llvm::TargetLoweringBase | inline |
| isInTailCallPosition(SelectionDAG &DAG, SDNode *Node, SDValue &Chain) const | llvm::TargetLowering | |
| isIntDivCheap() const | llvm::TargetLoweringBase | inline |
| isJumpExpensive() const | llvm::TargetLoweringBase | inline |
| isLegalAddImmediate(int64_t) const | llvm::TargetLoweringBase | inlinevirtual |
| isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AddrSpace) const | llvm::TargetLoweringBase | virtual |
| isLegalICmpImmediate(int64_t) const | llvm::TargetLoweringBase | inlinevirtual |
| isLegalRC(const TargetRegisterClass *RC) const | llvm::TargetLoweringBase | protected |
| isLoadBitCastBeneficial(EVT, EVT) const | llvm::TargetLoweringBase | inlinevirtual |
| isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const | llvm::TargetLoweringBase | inline |
| isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const | llvm::TargetLoweringBase | inline |
| isMaskAndBranchFoldingLegal() const | llvm::TargetLoweringBase | inline |
| isNarrowingProfitable(EVT, EVT) const | llvm::TargetLoweringBase | inlinevirtual |
| isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const | llvm::TargetLoweringBase | inlinevirtual |
| isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const | llvm::TargetLowering | virtual |
| isOperationExpand(unsigned Op, EVT VT) const | llvm::TargetLoweringBase | inline |
| isOperationLegal(unsigned Op, EVT VT) const | llvm::TargetLoweringBase | inline |
| isOperationLegalOrCustom(unsigned Op, EVT VT) const | llvm::TargetLoweringBase | inline |
| isOperationLegalOrPromote(unsigned Op, EVT VT) const | llvm::TargetLoweringBase | inline |
| isPow2SDivCheap() const | llvm::TargetLoweringBase | inline |
| isPredictableSelectExpensive() const | llvm::TargetLoweringBase | inline |
| isProfitableToHoist(Instruction *I) const | llvm::TargetLoweringBase | inlinevirtual |
| isSafeMemOpType(MVT) const | llvm::TargetLoweringBase | inlinevirtual |
| isSelectExpensive() const | llvm::TargetLoweringBase | inline |
| isSelectSupported(SelectSupportKind) const | llvm::TargetLoweringBase | inlinevirtual |
| isShuffleMaskLegal(const SmallVectorImpl< int > &, EVT) const | llvm::TargetLoweringBase | inlinevirtual |
| isSlowDivBypassed() const | llvm::TargetLoweringBase | inline |
| isTruncateFree(Type *Ty1, Type *Ty2) const override | llvm::MSP430TargetLowering | virtual |
| isTruncateFree(EVT VT1, EVT VT2) const override | llvm::MSP430TargetLowering | virtual |
| isTruncStoreLegal(EVT ValVT, EVT MemVT) const | llvm::TargetLoweringBase | inline |
| isTypeDesirableForOp(unsigned, EVT VT) const | llvm::TargetLowering | inlinevirtual |
| isTypeLegal(EVT VT) const | llvm::TargetLoweringBase | inline |
| isUsedByReturnOnly(SDNode *, SDValue &) const | llvm::TargetLowering | inlinevirtual |
| isVectorClearMaskLegal(const SmallVectorImpl< int > &, EVT) const | llvm::TargetLoweringBase | inlinevirtual |
| isVectorLoadExtDesirable(SDValue ExtVal) const | llvm::TargetLoweringBase | inlinevirtual |
| isVectorShiftByScalarCheap(Type *Ty) const | llvm::TargetLoweringBase | inlinevirtual |
| isZExtFree(Type *Ty1, Type *Ty2) const override | llvm::MSP430TargetLowering | virtual |
| isZExtFree(EVT VT1, EVT VT2) const override | llvm::MSP430TargetLowering | virtual |
| isZExtFree(SDValue Val, EVT VT2) const override | llvm::MSP430TargetLowering | virtual |
| Legal enum value | llvm::TargetLoweringBase | |
| LegalizeAction enum name | llvm::TargetLoweringBase | |
| LegalizeKind typedef | llvm::TargetLoweringBase | |
| LegalizeTypeAction enum name | llvm::TargetLoweringBase | |
| LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const | llvm::TargetLowering | virtual |
| LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const | llvm::MSP430TargetLowering | |
| LowerBR_CC(SDValue Op, SelectionDAG &DAG) const | llvm::MSP430TargetLowering | |
| LowerCallTo(CallLoweringInfo &CLI) const | llvm::TargetLowering | |
| LowerCustomJumpTableEntry(const MachineJumpTableInfo *, const MachineBasicBlock *, unsigned, MCContext &) const | llvm::TargetLowering | inlinevirtual |
| LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const | llvm::MSP430TargetLowering | |
| LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const | llvm::MSP430TargetLowering | |
| LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const | llvm::MSP430TargetLowering | |
| lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) const | llvm::TargetLoweringBase | inlinevirtual |
| lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const | llvm::TargetLoweringBase | inlinevirtual |
| lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const | llvm::TargetLoweringBase | inlinevirtual |
| LowerJumpTable(SDValue Op, SelectionDAG &DAG) const | llvm::MSP430TargetLowering | |
| LowerOperation(SDValue Op, SelectionDAG &DAG) const override | llvm::MSP430TargetLowering | virtual |
| LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const | llvm::TargetLowering | virtual |
| LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const | llvm::MSP430TargetLowering | |
| LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const | llvm::MSP430TargetLowering | |
| LowerSETCC(SDValue Op, SelectionDAG &DAG) const | llvm::MSP430TargetLowering | |
| LowerShifts(SDValue Op, SelectionDAG &DAG) const | llvm::MSP430TargetLowering | |
| LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const | llvm::MSP430TargetLowering | |
| LowerVASTART(SDValue Op, SelectionDAG &DAG) const | llvm::MSP430TargetLowering | |
| LowerXConstraint(EVT ConstraintVT) const | llvm::TargetLowering | virtual |
| makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops, unsigned NumOps, bool isSigned, SDLoc dl, bool doesNotReturn=false, bool isReturnValueUsed=true) const | llvm::TargetLowering | |
| MaskAndBranchFoldingIsLegal | llvm::TargetLoweringBase | protected |
| MaxStoresPerMemcpy | llvm::TargetLoweringBase | protected |
| MaxStoresPerMemcpyOptSize | llvm::TargetLoweringBase | protected |
| MaxStoresPerMemmove | llvm::TargetLoweringBase | protected |
| MaxStoresPerMemmoveOptSize | llvm::TargetLoweringBase | protected |
| MaxStoresPerMemset | llvm::TargetLoweringBase | protected |
| MaxStoresPerMemsetOptSize | llvm::TargetLoweringBase | protected |
| mayBeEmittedAsTailCall(CallInst *) const | llvm::TargetLowering | inlinevirtual |
| MSP430TargetLowering(const TargetMachine &TM, const MSP430Subtarget &STI) | llvm::MSP430TargetLowering | explicit |
| ParseConstraints(const DataLayout &DL, const TargetRegisterInfo *TRI, ImmutableCallSite CS) const | llvm::TargetLowering | virtual |
| PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const | llvm::TargetLowering | virtual |
| PredictableSelectIsExpensive | llvm::TargetLoweringBase | protected |
| prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL, SelectionDAG &DAG) const | llvm::TargetLowering | inlinevirtual |
| Promote enum value | llvm::TargetLoweringBase | |
| ReplaceNodeResults(SDNode *, SmallVectorImpl< SDValue > &, SelectionDAG &) const | llvm::TargetLowering | inlinevirtual |
| ScalarCondVectorVal enum value | llvm::TargetLoweringBase | |
| ScalarValSelect enum value | llvm::TargetLoweringBase | |
| SelectSupportKind enum name | llvm::TargetLoweringBase | |
| setBooleanContents(BooleanContent Ty) | llvm::TargetLoweringBase | inlineprotected |
| setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy) | llvm::TargetLoweringBase | inlineprotected |
| setBooleanVectorContents(BooleanContent Ty) | llvm::TargetLoweringBase | inlineprotected |
| setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) | llvm::TargetLoweringBase | inline |
| setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
| setExceptionPointerRegister(unsigned R) | llvm::TargetLoweringBase | inlineprotected |
| setExceptionSelectorRegister(unsigned R) | llvm::TargetLoweringBase | inlineprotected |
| setFsqrtIsCheap(bool isCheap=true) | llvm::TargetLoweringBase | inlineprotected |
| setHasExtractBitsInsn(bool hasExtractInsn=true) | llvm::TargetLoweringBase | inlineprotected |
| setHasFloatingPointExceptions(bool FPExceptions=true) | llvm::TargetLoweringBase | inlineprotected |
| setHasMultipleConditionRegisters(bool hasManyRegs=true) | llvm::TargetLoweringBase | inlineprotected |
| setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
| setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
| setInsertFencesForAtomic(bool fence) | llvm::TargetLoweringBase | inlineprotected |
| setIntDivIsCheap(bool isCheap=true) | llvm::TargetLoweringBase | inlineprotected |
| setJumpBufAlignment(unsigned Align) | llvm::TargetLoweringBase | inlineprotected |
| setJumpBufSize(unsigned Size) | llvm::TargetLoweringBase | inlineprotected |
| setJumpIsExpensive(bool isExpensive=true) | llvm::TargetLoweringBase | protected |
| setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) | llvm::TargetLoweringBase | inline |
| setLibcallName(RTLIB::Libcall Call, const char *Name) | llvm::TargetLoweringBase | inline |
| setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
| setMinFunctionAlignment(unsigned Align) | llvm::TargetLoweringBase | inlineprotected |
| setMinimumJumpTableEntries(int Val) | llvm::TargetLoweringBase | inlineprotected |
| setMinStackArgumentAlignment(unsigned Align) | llvm::TargetLoweringBase | inlineprotected |
| setOperationAction(unsigned Op, MVT VT, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
| setPow2SDivIsCheap(bool isCheap=true) | llvm::TargetLoweringBase | inlineprotected |
| setPrefFunctionAlignment(unsigned Align) | llvm::TargetLoweringBase | inlineprotected |
| setPrefLoopAlignment(unsigned Align) | llvm::TargetLoweringBase | inlineprotected |
| setSchedulingPreference(Sched::Preference Pref) | llvm::TargetLoweringBase | inlineprotected |
| setSelectIsExpensive(bool isExpensive=true) | llvm::TargetLoweringBase | inlineprotected |
| setStackPointerRegisterToSaveRestore(unsigned R) | llvm::TargetLoweringBase | inlineprotected |
| setTargetDAGCombine(ISD::NodeType NT) | llvm::TargetLoweringBase | inlineprotected |
| setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
| setUseUnderscoreLongJmp(bool Val) | llvm::TargetLoweringBase | inlineprotected |
| setUseUnderscoreSetJmp(bool Val) | llvm::TargetLoweringBase | inlineprotected |
| shouldAlignPointerArgs(CallInst *, unsigned &, unsigned &) const | llvm::TargetLoweringBase | inlinevirtual |
| shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const | llvm::TargetLoweringBase | inlinevirtual |
| shouldExpandAtomicLoadInIR(LoadInst *LI) const | llvm::TargetLoweringBase | inlinevirtual |
| shouldExpandAtomicRMWInIR(AtomicRMWInst *) const | llvm::TargetLoweringBase | inlinevirtual |
| shouldExpandAtomicStoreInIR(StoreInst *SI) const | llvm::TargetLoweringBase | inlinevirtual |
| shouldExpandBuildVectorWithShuffles(EVT, unsigned DefinedValues) const | llvm::TargetLoweringBase | inlinevirtual |
| shouldNormalizeToSelectSequence(LLVMContext &Context, EVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
| shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const | llvm::TargetLoweringBase | inlinevirtual |
| ShouldShrinkFPConstant(EVT) const | llvm::TargetLoweringBase | inlinevirtual |
| shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const | llvm::TargetLoweringBase | inlinevirtual |
| SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, APInt &KnownZero, APInt &KnownOne, TargetLoweringOpt &TLO, unsigned Depth=0) const | llvm::TargetLowering | |
| SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, SDLoc dl) const | llvm::TargetLowering | |
| softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, SDLoc DL) const | llvm::TargetLowering | |
| storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem, unsigned AddrSpace) const | llvm::TargetLoweringBase | inlinevirtual |
| TargetLowering(const TargetMachine &TM) | llvm::TargetLowering | explicit |
| TargetLoweringBase(const TargetMachine &TM) | llvm::TargetLoweringBase | explicit |
| TypeExpandFloat enum value | llvm::TargetLoweringBase | |
| TypeExpandInteger enum value | llvm::TargetLoweringBase | |
| TypeLegal enum value | llvm::TargetLoweringBase | |
| TypePromoteFloat enum value | llvm::TargetLoweringBase | |
| TypePromoteInteger enum value | llvm::TargetLoweringBase | |
| TypeScalarizeVector enum value | llvm::TargetLoweringBase | |
| TypeSoftenFloat enum value | llvm::TargetLoweringBase | |
| TypeSplitVector enum value | llvm::TargetLoweringBase | |
| TypeWidenVector enum value | llvm::TargetLoweringBase | |
| UndefinedBooleanContent enum value | llvm::TargetLoweringBase | |
| useLoadStackGuardNode() const | llvm::TargetLowering | inlinevirtual |
| useSoftFloat() const | llvm::TargetLoweringBase | inlinevirtual |
| usesUnderscoreLongJmp() const | llvm::TargetLoweringBase | inline |
| usesUnderscoreSetJmp() const | llvm::TargetLoweringBase | inline |
| VectorMaskSelect enum value | llvm::TargetLoweringBase | |
| verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const | llvm::TargetLowering | |
| ZeroOrNegativeOneBooleanContent enum value | llvm::TargetLoweringBase | |
| ZeroOrOneBooleanContent enum value | llvm::TargetLoweringBase | |
| ~TargetLoweringBase() | llvm::TargetLoweringBase | inlinevirtual |