LLVM  3.7.0
MCSubtargetInfo.h
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1 //==-- llvm/MC/MCSubtargetInfo.h - Subtarget Information ---------*- C++ -*-==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file describes the subtarget options of a Target machine.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_MC_MCSUBTARGETINFO_H
15 #define LLVM_MC_MCSUBTARGETINFO_H
16 
19 #include <string>
20 
21 namespace llvm {
22 
23 class StringRef;
24 
25 //===----------------------------------------------------------------------===//
26 ///
27 /// MCSubtargetInfo - Generic base class for all target subtargets.
28 ///
30  Triple TargetTriple; // Target triple
31  std::string CPU; // CPU being targeted.
32  ArrayRef<SubtargetFeatureKV> ProcFeatures; // Processor feature list
33  ArrayRef<SubtargetFeatureKV> ProcDesc; // Processor descriptions
34 
35  // Scheduler machine model
36  const SubtargetInfoKV *ProcSchedModels;
37  const MCWriteProcResEntry *WriteProcResTable;
38  const MCWriteLatencyEntry *WriteLatencyTable;
39  const MCReadAdvanceEntry *ReadAdvanceTable;
40  const MCSchedModel *CPUSchedModel;
41 
42  const InstrStage *Stages; // Instruction itinerary stages
43  const unsigned *OperandCycles; // Itinerary operand cycles
44  const unsigned *ForwardingPaths; // Forwarding paths
45  FeatureBitset FeatureBits; // Feature bits for current CPU + FS
46 
47  MCSubtargetInfo() = delete;
48  MCSubtargetInfo &operator=(MCSubtargetInfo &&) = delete;
49  MCSubtargetInfo &operator=(const MCSubtargetInfo &) = delete;
50 
51 public:
52  MCSubtargetInfo(const MCSubtargetInfo &) = default;
56  const SubtargetInfoKV *ProcSched,
57  const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL,
58  const MCReadAdvanceEntry *RA, const InstrStage *IS,
59  const unsigned *OC, const unsigned *FP);
60 
61  /// getTargetTriple - Return the target triple string.
62  const Triple &getTargetTriple() const { return TargetTriple; }
63 
64  /// getCPU - Return the CPU string.
65  StringRef getCPU() const {
66  return CPU;
67  }
68 
69  /// getFeatureBits - Return the feature bits.
70  ///
71  const FeatureBitset& getFeatureBits() const {
72  return FeatureBits;
73  }
74 
75  /// setFeatureBits - Set the feature bits.
76  ///
77  void setFeatureBits(const FeatureBitset &FeatureBits_) {
78  FeatureBits = FeatureBits_;
79  }
80 
81 protected:
82  /// Initialize the scheduling model and feature bits.
83  ///
84  /// FIXME: Find a way to stick this in the constructor, since it should only
85  /// be called during initialization.
87 
88 public:
89  /// Set the features to the default for the given CPU.
90  void setDefaultFeatures(StringRef CPU);
91 
92  /// ToggleFeature - Toggle a feature and returns the re-computed feature
93  /// bits. This version does not change the implied bits.
94  FeatureBitset ToggleFeature(uint64_t FB);
95 
96  /// ToggleFeature - Toggle a feature and returns the re-computed feature
97  /// bits. This version does not change the implied bits.
99 
100  /// ToggleFeature - Toggle a set of features and returns the re-computed
101  /// feature bits. This version will also change all implied bits.
103 
104  /// Apply a feature flag and return the re-computed feature bits, including
105  /// all feature bits implied by the flag.
107 
108  /// getSchedModelForCPU - Get the machine model of a CPU.
109  ///
110  const MCSchedModel &getSchedModelForCPU(StringRef CPU) const;
111 
112  /// Get the machine model for this subtarget's CPU.
113  const MCSchedModel &getSchedModel() const { return *CPUSchedModel; }
114 
115  /// Return an iterator at the first process resource consumed by the given
116  /// scheduling class.
118  const MCSchedClassDesc *SC) const {
119  return &WriteProcResTable[SC->WriteProcResIdx];
120  }
122  const MCSchedClassDesc *SC) const {
124  }
125 
127  unsigned DefIdx) const {
128  assert(DefIdx < SC->NumWriteLatencyEntries &&
129  "MachineModel does not specify a WriteResource for DefIdx");
130 
131  return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx];
132  }
133 
134  int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx,
135  unsigned WriteResID) const {
136  // TODO: The number of read advance entries in a class can be significant
137  // (~50). Consider compressing the WriteID into a dense ID of those that are
138  // used by ReadAdvance and representing them as a bitset.
139  for (const MCReadAdvanceEntry *I = &ReadAdvanceTable[SC->ReadAdvanceIdx],
140  *E = I + SC->NumReadAdvanceEntries; I != E; ++I) {
141  if (I->UseIdx < UseIdx)
142  continue;
143  if (I->UseIdx > UseIdx)
144  break;
145  // Find the first WriteResIdx match, which has the highest cycle count.
146  if (!I->WriteResourceID || I->WriteResourceID == WriteResID) {
147  return I->Cycles;
148  }
149  }
150  return 0;
151  }
152 
153  /// getInstrItineraryForCPU - Get scheduling itinerary of a CPU.
154  ///
156 
157  /// Initialize an InstrItineraryData instance.
158  void initInstrItins(InstrItineraryData &InstrItins) const;
159 
160  /// Check whether the CPU string is valid.
161  bool isCPUStringValid(StringRef CPU) const {
162  auto Found = std::find_if(ProcDesc.begin(), ProcDesc.end(),
163  [=](const SubtargetFeatureKV &KV) {
164  return CPU == KV.Key;
165  });
166  return Found != ProcDesc.end();
167  }
168 };
169 
170 } // End llvm namespace
171 
172 #endif
unsigned NumWriteProcResEntries
Definition: MCSchedule.h:112
InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const
getInstrItineraryForCPU - Get scheduling itinerary of a CPU.
static void Found()
void setFeatureBits(const FeatureBitset &FeatureBits_)
setFeatureBits - Set the feature bits.
const MCWriteProcResEntry * getWriteProcResBegin(const MCSchedClassDesc *SC) const
Return an iterator at the first process resource consumed by the given scheduling class...
SubtargetInfoKV - Used to provide key value pairs for CPU and arbitrary pointers. ...
void initInstrItins(InstrItineraryData &InstrItins) const
Initialize an InstrItineraryData instance.
const MCWriteProcResEntry * getWriteProcResEnd(const MCSchedClassDesc *SC) const
const MCSchedModel & getSchedModelForCPU(StringRef CPU) const
getSchedModelForCPU - Get the machine model of a CPU.
int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx, unsigned WriteResID) const
StringRef getCPU() const
getCPU - Return the CPU string.
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget's CPU.
SubtargetFeatureKV - Used to provide key value pairs for feature and CPU bit flags.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: ArrayRef.h:31
void setDefaultFeatures(StringRef CPU)
Set the features to the default for the given CPU.
Itinerary data supplied by a subtarget to be used by a target.
void InitMCProcessorInfo(StringRef CPU, StringRef FS)
Initialize the scheduling model and feature bits.
unsigned NumReadAdvanceEntries
Definition: MCSchedule.h:116
FeatureBitset ToggleFeature(uint64_t FB)
ToggleFeature - Toggle a feature and returns the re-computed feature bits.
bool isCPUStringValid(StringRef CPU) const
Check whether the CPU string is valid.
Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...
Definition: MCSchedule.h:55
Summarize the scheduling resources required for an instruction of a particular scheduling class...
Definition: MCSchedule.h:101
const MCWriteLatencyEntry * getWriteLatencyEntry(const MCSchedClassDesc *SC, unsigned DefIdx) const
FeatureBitset ApplyFeatureFlag(StringRef FS)
Apply a feature flag and return the re-computed feature bits, including all feature bits implied by t...
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
Specify the latency in cpu cycles for a particular scheduling class and def index.
Definition: MCSchedule.h:69
CHAIN = SC CHAIN, Imm128 - System call.
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
Specify the number of cycles allowed after instruction issue before a particular use operand reads it...
Definition: MCSchedule.h:86
These values represent a non-pipelined step in the execution of an instruction.
#define I(x, y, z)
Definition: MD5.cpp:54
MCSubtargetInfo - Generic base class for all target subtargets.
const Triple & getTargetTriple() const
getTargetTriple - Return the target triple string.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:40
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:136