LLVM  3.7.0
ARMTargetTransformInfo.h
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1 //===-- ARMTargetTransformInfo.h - ARM specific TTI -------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file a TargetTransformInfo::Concept conforming object specific to the
11 /// ARM target machine. It uses the target's detailed information to
12 /// provide more precise answers to certain TTI queries, while letting the
13 /// target independent and default TTI implementations handle the rest.
14 ///
15 //===----------------------------------------------------------------------===//
16 
17 #ifndef LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H
18 #define LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H
19 
20 #include "ARM.h"
21 #include "ARMTargetMachine.h"
25 
26 namespace llvm {
27 
28 class ARMTTIImpl : public BasicTTIImplBase<ARMTTIImpl> {
30  typedef TargetTransformInfo TTI;
31  friend BaseT;
32 
33  const ARMSubtarget *ST;
34  const ARMTargetLowering *TLI;
35 
36  /// Estimate the overhead of scalarizing an instruction. Insert and Extract
37  /// are set if the result needs to be inserted and/or extracted from vectors.
38  unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract);
39 
40  const ARMSubtarget *getST() const { return ST; }
41  const ARMTargetLowering *getTLI() const { return TLI; }
42 
43 public:
45  : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
46  TLI(ST->getTargetLowering()) {}
47 
48  // Provide value semantics. MSVC requires that we spell all of these out.
49  ARMTTIImpl(const ARMTTIImpl &Arg)
50  : BaseT(static_cast<const BaseT &>(Arg)), ST(Arg.ST), TLI(Arg.TLI) {}
52  : BaseT(std::move(static_cast<BaseT &>(Arg))), ST(std::move(Arg.ST)),
53  TLI(std::move(Arg.TLI)) {}
54 
55  /// \name Scalar TTI Implementations
56  /// @{
57 
59  unsigned getIntImmCost(const APInt &Imm, Type *Ty);
60 
61  /// @}
62 
63  /// \name Vector TTI Implementations
64  /// @{
65 
66  unsigned getNumberOfRegisters(bool Vector) {
67  if (Vector) {
68  if (ST->hasNEON())
69  return 16;
70  return 0;
71  }
72 
73  if (ST->isThumb1Only())
74  return 8;
75  return 13;
76  }
77 
78  unsigned getRegisterBitWidth(bool Vector) {
79  if (Vector) {
80  if (ST->hasNEON())
81  return 128;
82  return 0;
83  }
84 
85  return 32;
86  }
87 
88  unsigned getMaxInterleaveFactor(unsigned VF) {
89  // These are out of order CPUs:
90  if (ST->isCortexA15() || ST->isSwift())
91  return 2;
92  return 1;
93  }
94 
95  unsigned getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index,
96  Type *SubTp);
97 
98  unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src);
99 
100  unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy);
101 
102  unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index);
103 
104  unsigned getAddressComputationCost(Type *Val, bool IsComplex);
105 
106  unsigned getFPOpCost(Type *Ty);
107 
108  unsigned getArithmeticInstrCost(
109  unsigned Opcode, Type *Ty,
114 
115  unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
116  unsigned AddressSpace);
117 
118  unsigned getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy,
119  unsigned Factor,
120  ArrayRef<unsigned> Indices,
121  unsigned Alignment,
122  unsigned AddressSpace);
123  /// @}
124 };
125 
126 } // end namespace llvm
127 
128 #endif
unsigned getRegisterBitWidth(bool Vector)
unsigned getFPOpCost(Type *Ty)
unsigned getMaxInterleaveFactor(unsigned VF)
unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, unsigned AddressSpace)
unsigned getAddressComputationCost(Type *Val, bool IsComplex)
F(f)
Base class which can be used to help build a TTI implementation.
Definition: BasicTTIImpl.h:40
bool isThumb1Only() const
Definition: ARMSubtarget.h:405
unsigned getIntImmCost(const APInt &Imm, Type *Ty)
ARMTTIImpl(const ARMBaseTargetMachine *TM, Function &F)
unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index)
unsigned getNumberOfRegisters(bool Vector)
bool hasNEON() const
Definition: ARMSubtarget.h:318
unsigned getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, Type *SubTp)
unsigned getIntImmCost(const APInt &Imm, Type *Ty)
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
bool isCortexA15() const
Definition: ARMSubtarget.h:305
This file provides a helper that implements much of the TTI interface in terms of the target-independ...
unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy)
OperandValueProperties
Additional properties of an operand's values.
ARMTTIImpl(ARMTTIImpl &&Arg)
bool isSwift() const
Definition: ARMSubtarget.h:306
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
unsigned getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, unsigned Alignment, unsigned AddressSpace)
ARMTTIImpl(const ARMTTIImpl &Arg)
AddressSpace
Definition: NVPTXBaseInfo.h:22
Class for arbitrary precision integers.
Definition: APInt.h:73
const DataLayout & getDataLayout() const
const ARM::ArchExtKind Kind
aarch64 promote const
static const Function * getParent(const Value *V)
unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::OperandValueKind Op1Info=TTI::OK_AnyValue, TTI::OperandValueKind Op2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None)
OperandValueKind
Additional information about an operand's possible values.
This pass exposes codegen information to IR-level passes.
unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src)
This file describes how to lower LLVM code to machine code.
ShuffleKind
The various kinds of shuffle patterns for vector queries.