LLVM  3.7.0
ARMTargetTransformInfo.cpp
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1 //===-- ARMTargetTransformInfo.cpp - ARM specific TTI ---------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "ARMTargetTransformInfo.h"
11 #include "llvm/Support/Debug.h"
12 #include "llvm/Target/CostTable.h"
14 using namespace llvm;
15 
16 #define DEBUG_TYPE "armtti"
17 
18 unsigned ARMTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) {
19  assert(Ty->isIntegerTy());
20 
21  unsigned Bits = Ty->getPrimitiveSizeInBits();
22  if (Bits == 0 || Bits > 32)
23  return 4;
24 
25  int32_t SImmVal = Imm.getSExtValue();
26  uint32_t ZImmVal = Imm.getZExtValue();
27  if (!ST->isThumb()) {
28  if ((SImmVal >= 0 && SImmVal < 65536) ||
29  (ARM_AM::getSOImmVal(ZImmVal) != -1) ||
30  (ARM_AM::getSOImmVal(~ZImmVal) != -1))
31  return 1;
32  return ST->hasV6T2Ops() ? 2 : 3;
33  }
34  if (ST->isThumb2()) {
35  if ((SImmVal >= 0 && SImmVal < 65536) ||
36  (ARM_AM::getT2SOImmVal(ZImmVal) != -1) ||
37  (ARM_AM::getT2SOImmVal(~ZImmVal) != -1))
38  return 1;
39  return ST->hasV6T2Ops() ? 2 : 3;
40  }
41  // Thumb1.
42  if (SImmVal >= 0 && SImmVal < 256)
43  return 1;
44  if ((~ZImmVal < 256) || ARM_AM::isThumbImmShiftedVal(ZImmVal))
45  return 2;
46  // Load from constantpool.
47  return 3;
48 }
49 
50 unsigned ARMTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) {
51  int ISD = TLI->InstructionOpcodeToISD(Opcode);
52  assert(ISD && "Invalid opcode");
53 
54  // Single to/from double precision conversions.
55  static const CostTblEntry<MVT::SimpleValueType> NEONFltDblTbl[] = {
56  // Vector fptrunc/fpext conversions.
57  { ISD::FP_ROUND, MVT::v2f64, 2 },
58  { ISD::FP_EXTEND, MVT::v2f32, 2 },
60  };
61 
62  if (Src->isVectorTy() && ST->hasNEON() && (ISD == ISD::FP_ROUND ||
63  ISD == ISD::FP_EXTEND)) {
64  std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(DL, Src);
65  int Idx = CostTableLookup(NEONFltDblTbl, ISD, LT.second);
66  if (Idx != -1)
67  return LT.first * NEONFltDblTbl[Idx].Cost;
68  }
69 
70  EVT SrcTy = TLI->getValueType(DL, Src);
71  EVT DstTy = TLI->getValueType(DL, Dst);
72 
73  if (!SrcTy.isSimple() || !DstTy.isSimple())
74  return BaseT::getCastInstrCost(Opcode, Dst, Src);
75 
76  // Some arithmetic, load and store operations have specific instructions
77  // to cast up/down their types automatically at no extra cost.
78  // TODO: Get these tables to know at least what the related operations are.
80  NEONVectorConversionTbl[] = {
87 
88  // The number of vmovl instructions for the extension.
99 
100  // Operations that we legalize using splitting.
103 
104  // Vector float <-> i32 conversions.
107 
128 
135 
136  // Vector double <-> i32 conversions.
139 
146 
153  };
154 
155  if (SrcTy.isVector() && ST->hasNEON()) {
156  int Idx = ConvertCostTableLookup(NEONVectorConversionTbl, ISD,
157  DstTy.getSimpleVT(), SrcTy.getSimpleVT());
158  if (Idx != -1)
159  return NEONVectorConversionTbl[Idx].Cost;
160  }
161 
162  // Scalar float to integer conversions.
164  NEONFloatConversionTbl[] = {
185  };
186  if (SrcTy.isFloatingPoint() && ST->hasNEON()) {
187  int Idx = ConvertCostTableLookup(NEONFloatConversionTbl, ISD,
188  DstTy.getSimpleVT(), SrcTy.getSimpleVT());
189  if (Idx != -1)
190  return NEONFloatConversionTbl[Idx].Cost;
191  }
192 
193  // Scalar integer to float conversions.
195  NEONIntegerConversionTbl[] = {
216  };
217 
218  if (SrcTy.isInteger() && ST->hasNEON()) {
219  int Idx = ConvertCostTableLookup(NEONIntegerConversionTbl, ISD,
220  DstTy.getSimpleVT(), SrcTy.getSimpleVT());
221  if (Idx != -1)
222  return NEONIntegerConversionTbl[Idx].Cost;
223  }
224 
225  // Scalar integer conversion costs.
227  ARMIntegerConversionTbl[] = {
228  // i16 -> i64 requires two dependent operations.
230 
231  // Truncates on i64 are assumed to be free.
234  { ISD::TRUNCATE, MVT::i8, MVT::i64, 0 },
236  };
237 
238  if (SrcTy.isInteger()) {
239  int Idx = ConvertCostTableLookup(ARMIntegerConversionTbl, ISD,
240  DstTy.getSimpleVT(), SrcTy.getSimpleVT());
241  if (Idx != -1)
242  return ARMIntegerConversionTbl[Idx].Cost;
243  }
244 
245  return BaseT::getCastInstrCost(Opcode, Dst, Src);
246 }
247 
248 unsigned ARMTTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy,
249  unsigned Index) {
250  // Penalize inserting into an D-subregister. We end up with a three times
251  // lower estimated throughput on swift.
252  if (ST->isSwift() &&
253  Opcode == Instruction::InsertElement &&
254  ValTy->isVectorTy() &&
255  ValTy->getScalarSizeInBits() <= 32)
256  return 3;
257 
258  // Cross-class copies are expensive on many microarchitectures,
259  // so assume they are expensive by default.
260  if ((Opcode == Instruction::InsertElement ||
261  Opcode == Instruction::ExtractElement) &&
262  ValTy->getVectorElementType()->isIntegerTy())
263  return 3;
264 
265  return BaseT::getVectorInstrCost(Opcode, ValTy, Index);
266 }
267 
268 unsigned ARMTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
269  Type *CondTy) {
270 
271  int ISD = TLI->InstructionOpcodeToISD(Opcode);
272  // On NEON a a vector select gets lowered to vbsl.
273  if (ST->hasNEON() && ValTy->isVectorTy() && ISD == ISD::SELECT) {
274  // Lowering of some vector selects is currently far from perfect.
276  NEONVectorSelectTbl[] = {
277  { ISD::SELECT, MVT::v16i1, MVT::v16i16, 2*16 + 1 + 3*1 + 4*1 },
278  { ISD::SELECT, MVT::v8i1, MVT::v8i32, 4*8 + 1*3 + 1*4 + 1*2 },
279  { ISD::SELECT, MVT::v16i1, MVT::v16i32, 4*16 + 1*6 + 1*8 + 1*4 },
280  { ISD::SELECT, MVT::v4i1, MVT::v4i64, 4*4 + 1*2 + 1 },
281  { ISD::SELECT, MVT::v8i1, MVT::v8i64, 50 },
283  };
284 
285  EVT SelCondTy = TLI->getValueType(DL, CondTy);
286  EVT SelValTy = TLI->getValueType(DL, ValTy);
287  if (SelCondTy.isSimple() && SelValTy.isSimple()) {
288  int Idx = ConvertCostTableLookup(NEONVectorSelectTbl, ISD,
289  SelCondTy.getSimpleVT(),
290  SelValTy.getSimpleVT());
291  if (Idx != -1)
292  return NEONVectorSelectTbl[Idx].Cost;
293  }
294 
295  std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy);
296  return LT.first;
297  }
298 
299  return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy);
300 }
301 
302 unsigned ARMTTIImpl::getAddressComputationCost(Type *Ty, bool IsComplex) {
303  // Address computations in vectorized code with non-consecutive addresses will
304  // likely result in more instructions compared to scalar code where the
305  // computation can more often be merged into the index mode. The resulting
306  // extra micro-ops can significantly decrease throughput.
307  unsigned NumVectorInstToHideOverhead = 10;
308 
309  if (Ty->isVectorTy() && IsComplex)
310  return NumVectorInstToHideOverhead;
311 
312  // In many cases the address computation is not merged into the instruction
313  // addressing mode.
314  return 1;
315 }
316 
318  // Use similar logic that's in ARMISelLowering:
319  // Any ARM CPU with VFP2 has floating point, but Thumb1 didn't have access
320  // to VFP.
321 
322  if (ST->hasVFP2() && !ST->isThumb1Only()) {
323  if (Ty->isFloatTy()) {
325  }
326 
327  if (Ty->isDoubleTy()) {
330  }
331  }
332 
334 }
335 
337  Type *SubTp) {
338  // We only handle costs of reverse and alternate shuffles for now.
339  if (Kind != TTI::SK_Reverse && Kind != TTI::SK_Alternate)
340  return BaseT::getShuffleCost(Kind, Tp, Index, SubTp);
341 
342  if (Kind == TTI::SK_Reverse) {
343  static const CostTblEntry<MVT::SimpleValueType> NEONShuffleTbl[] = {
344  // Reverse shuffle cost one instruction if we are shuffling within a
345  // double word (vrev) or two if we shuffle a quad word (vrev, vext).
350 
355 
356  std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp);
357 
358  int Idx = CostTableLookup(NEONShuffleTbl, ISD::VECTOR_SHUFFLE, LT.second);
359  if (Idx == -1)
360  return BaseT::getShuffleCost(Kind, Tp, Index, SubTp);
361 
362  return LT.first * NEONShuffleTbl[Idx].Cost;
363  }
364  if (Kind == TTI::SK_Alternate) {
365  static const CostTblEntry<MVT::SimpleValueType> NEONAltShuffleTbl[] = {
366  // Alt shuffle cost table for ARM. Cost is the number of instructions
367  // required to create the shuffled vector.
368 
373 
377 
379 
381 
382  std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp);
383  int Idx =
384  CostTableLookup(NEONAltShuffleTbl, ISD::VECTOR_SHUFFLE, LT.second);
385  if (Idx == -1)
386  return BaseT::getShuffleCost(Kind, Tp, Index, SubTp);
387  return LT.first * NEONAltShuffleTbl[Idx].Cost;
388  }
389  return BaseT::getShuffleCost(Kind, Tp, Index, SubTp);
390 }
391 
393  unsigned Opcode, Type *Ty, TTI::OperandValueKind Op1Info,
395  TTI::OperandValueProperties Opd2PropInfo) {
396 
397  int ISDOpcode = TLI->InstructionOpcodeToISD(Opcode);
398  std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty);
399 
400  const unsigned FunctionCallDivCost = 20;
401  const unsigned ReciprocalDivCost = 10;
402  static const CostTblEntry<MVT::SimpleValueType> CostTbl[] = {
403  // Division.
404  // These costs are somewhat random. Choose a cost of 20 to indicate that
405  // vectorizing devision (added function call) is going to be very expensive.
406  // Double registers types.
407  { ISD::SDIV, MVT::v1i64, 1 * FunctionCallDivCost},
408  { ISD::UDIV, MVT::v1i64, 1 * FunctionCallDivCost},
409  { ISD::SREM, MVT::v1i64, 1 * FunctionCallDivCost},
410  { ISD::UREM, MVT::v1i64, 1 * FunctionCallDivCost},
411  { ISD::SDIV, MVT::v2i32, 2 * FunctionCallDivCost},
412  { ISD::UDIV, MVT::v2i32, 2 * FunctionCallDivCost},
413  { ISD::SREM, MVT::v2i32, 2 * FunctionCallDivCost},
414  { ISD::UREM, MVT::v2i32, 2 * FunctionCallDivCost},
415  { ISD::SDIV, MVT::v4i16, ReciprocalDivCost},
416  { ISD::UDIV, MVT::v4i16, ReciprocalDivCost},
417  { ISD::SREM, MVT::v4i16, 4 * FunctionCallDivCost},
418  { ISD::UREM, MVT::v4i16, 4 * FunctionCallDivCost},
419  { ISD::SDIV, MVT::v8i8, ReciprocalDivCost},
420  { ISD::UDIV, MVT::v8i8, ReciprocalDivCost},
421  { ISD::SREM, MVT::v8i8, 8 * FunctionCallDivCost},
422  { ISD::UREM, MVT::v8i8, 8 * FunctionCallDivCost},
423  // Quad register types.
424  { ISD::SDIV, MVT::v2i64, 2 * FunctionCallDivCost},
425  { ISD::UDIV, MVT::v2i64, 2 * FunctionCallDivCost},
426  { ISD::SREM, MVT::v2i64, 2 * FunctionCallDivCost},
427  { ISD::UREM, MVT::v2i64, 2 * FunctionCallDivCost},
428  { ISD::SDIV, MVT::v4i32, 4 * FunctionCallDivCost},
429  { ISD::UDIV, MVT::v4i32, 4 * FunctionCallDivCost},
430  { ISD::SREM, MVT::v4i32, 4 * FunctionCallDivCost},
431  { ISD::UREM, MVT::v4i32, 4 * FunctionCallDivCost},
432  { ISD::SDIV, MVT::v8i16, 8 * FunctionCallDivCost},
433  { ISD::UDIV, MVT::v8i16, 8 * FunctionCallDivCost},
434  { ISD::SREM, MVT::v8i16, 8 * FunctionCallDivCost},
435  { ISD::UREM, MVT::v8i16, 8 * FunctionCallDivCost},
436  { ISD::SDIV, MVT::v16i8, 16 * FunctionCallDivCost},
437  { ISD::UDIV, MVT::v16i8, 16 * FunctionCallDivCost},
438  { ISD::SREM, MVT::v16i8, 16 * FunctionCallDivCost},
439  { ISD::UREM, MVT::v16i8, 16 * FunctionCallDivCost},
440  // Multiplication.
441  };
442 
443  int Idx = -1;
444 
445  if (ST->hasNEON())
446  Idx = CostTableLookup(CostTbl, ISDOpcode, LT.second);
447 
448  if (Idx != -1)
449  return LT.first * CostTbl[Idx].Cost;
450 
451  unsigned Cost = BaseT::getArithmeticInstrCost(Opcode, Ty, Op1Info, Op2Info,
452  Opd1PropInfo, Opd2PropInfo);
453 
454  // This is somewhat of a hack. The problem that we are facing is that SROA
455  // creates a sequence of shift, and, or instructions to construct values.
456  // These sequences are recognized by the ISel and have zero-cost. Not so for
457  // the vectorized code. Because we have support for v2i64 but not i64 those
458  // sequences look particularly beneficial to vectorize.
459  // To work around this we increase the cost of v2i64 operations to make them
460  // seem less beneficial.
461  if (LT.second == MVT::v2i64 &&
463  Cost += 4;
464 
465  return Cost;
466 }
467 
468 unsigned ARMTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src,
469  unsigned Alignment,
470  unsigned AddressSpace) {
471  std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(DL, Src);
472 
473  if (Src->isVectorTy() && Alignment != 16 &&
474  Src->getVectorElementType()->isDoubleTy()) {
475  // Unaligned loads/stores are extremely inefficient.
476  // We need 4 uops for vst.1/vld.1 vs 1uop for vldr/vstr.
477  return LT.first * 4;
478  }
479  return LT.first;
480 }
481 
482 unsigned ARMTTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy,
483  unsigned Factor,
484  ArrayRef<unsigned> Indices,
485  unsigned Alignment,
486  unsigned AddressSpace) {
487  assert(Factor >= 2 && "Invalid interleave factor");
488  assert(isa<VectorType>(VecTy) && "Expect a vector type");
489 
490  // vldN/vstN doesn't support vector types of i64/f64 element.
491  bool EltIs64Bits = DL.getTypeAllocSizeInBits(VecTy->getScalarType()) == 64;
492 
493  if (Factor <= TLI->getMaxSupportedInterleaveFactor() && !EltIs64Bits) {
494  unsigned NumElts = VecTy->getVectorNumElements();
495  Type *SubVecTy = VectorType::get(VecTy->getScalarType(), NumElts / Factor);
496  unsigned SubVecSize = DL.getTypeAllocSize(SubVecTy);
497 
498  // vldN/vstN only support legal vector types of size 64 or 128 in bits.
499  if (NumElts % Factor == 0 && (SubVecSize == 64 || SubVecSize == 128))
500  return Factor;
501  }
502 
503  return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
504  Alignment, AddressSpace);
505 }
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:450
bool isFPOnlySP() const
Definition: ARMSubtarget.h:337
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1327
unsigned getFPOpCost(Type *Ty)
Cost tables and simple lookup functions.
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
Definition: ISDOpcodes.h:301
unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, unsigned AddressSpace)
unsigned getAddressComputationCost(Type *Val, bool IsComplex)
int CostTableLookup(const CostTblEntry< TypeTy > *Tbl, unsigned len, int ISD, CompareTy Ty)
Find in cost table, TypeTy must be comparable to CompareTy by ==.
Definition: CostTable.h:30
bool isDoubleTy() const
isDoubleTy - Return true if this is 'double', a 64-bit IEEE fp type.
Definition: Type.h:146
Type Conversion Cost Table.
Definition: CostTable.h:49
bool hasV6T2Ops() const
Definition: ARMSubtarget.h:296
bool isThumb1Only() const
Definition: ARMSubtarget.h:405
Cost Table Entry.
Definition: CostTable.h:22
uint64_t getTypeAllocSizeInBits(Type *Ty) const
Returns the offset in bits between successive objects of the specified type, including alignment padd...
Definition: DataLayout.h:398
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:115
unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src)
Definition: BasicTTIImpl.h:342
static ConstantInt * ExtractElement(Constant *V, Constant *Idx)
Type * getVectorElementType() const
Definition: Type.h:364
bool isThumb() const
Definition: ARMSubtarget.h:404
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
Definition: ValueTypes.h:110
unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index)
int InstructionOpcodeToISD(unsigned Opcode) const
Get the ISD node that corresponds to the Instruction class opcode.
unsigned getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, unsigned Alignment, unsigned AddressSpace)
Definition: BasicTTIImpl.h:518
This file a TargetTransformInfo::Concept conforming object specific to the ARM target machine...
Choose alternate elements from vector.
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:393
static int getT2SOImmVal(unsigned Arg)
getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit into a Thumb-2 shifter_oper...
bool hasNEON() const
Definition: ARMSubtarget.h:318
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
Reverse the order of the vector.
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:436
static bool isThumbImmShiftedVal(unsigned V)
isThumbImmShiftedVal - Return true if the specified value can be obtained by left shifting a 8-bit im...
unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy)
Definition: BasicTTIImpl.h:440
unsigned getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, Type *SubTp)
unsigned getIntImmCost(const APInt &Imm, Type *Ty)
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
bool isVectorTy() const
isVectorTy - True if this is an instance of VectorType.
Definition: Type.h:226
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1339
bool isFloatTy() const
isFloatTy - Return true if this is 'float', a 32-bit IEEE fp type.
Definition: Type.h:143
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:468
EVT - Extended Value Type.
Definition: ValueTypes.h:31
unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy)
OperandValueProperties
Additional properties of an operand's values.
unsigned getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, Type *SubTp)
Definition: BasicTTIImpl.h:334
bool isSwift() const
Definition: ARMSubtarget.h:306
uint64_t getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:388
unsigned getVectorNumElements() const
Definition: Type.cpp:212
unsigned getScalarSizeInBits() const LLVM_READONLY
getScalarSizeInBits - If this is a vector type, return the getPrimitiveSizeInBits value for the eleme...
Definition: Type.cpp:139
unsigned getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, unsigned Alignment, unsigned AddressSpace)
AddressSpace
Definition: NVPTXBaseInfo.h:22
bool hasVFP2() const
Definition: ARMSubtarget.h:314
unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info=TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None)
Definition: BasicTTIImpl.h:285
Class for arbitrary precision integers.
Definition: APInt.h:73
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:342
bool isIntegerTy() const
isIntegerTy - True if this is an instance of IntegerType.
Definition: Type.h:193
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:383
static int getSOImmVal(unsigned Arg)
getSOImmVal - Given a 32-bit immediate, if it is something that can fit into an shifter_operand immed...
const Type * getScalarType() const LLVM_READONLY
getScalarType - If this is a vector type, return the element type, otherwise return 'this'...
Definition: Type.cpp:51
bool isThumb2() const
Definition: ARMSubtarget.h:406
unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index)
Definition: BasicTTIImpl.h:478
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
Definition: ValueTypes.h:105
The cost of a typical 'add' instruction.
const ARM::ArchExtKind Kind
bool isSimple() const
isSimple - Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:94
int ConvertCostTableLookup(const TypeConversionCostTblEntry< TypeTy > *Tbl, unsigned len, int ISD, CompareTy Dst, CompareTy Src)
Find in type conversion cost table, TypeTy must be comparable to CompareTy by ==. ...
Definition: CostTable.h:59
unsigned getPrimitiveSizeInBits() const LLVM_READONLY
getPrimitiveSizeInBits - Return the basic size of this type if it is a primitive type.
Definition: Type.cpp:121
static VectorType * get(Type *ElementType, unsigned NumElements)
VectorType::get - This static method is the primary way to construct an VectorType.
Definition: Type.cpp:713
unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::OperandValueKind Op1Info=TTI::OK_AnyValue, TTI::OperandValueKind Op2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None)
OperandValueKind
Additional information about an operand's possible values.
Conversion operators.
Definition: ISDOpcodes.h:380
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:389
std::pair< unsigned, MVT > getTypeLegalizationCost(const DataLayout &DL, Type *Ty) const
Estimate the cost of type-legalization and the legalized type.
The cost of a 'div' instruction on x86.
unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src)
MVT getSimpleVT() const
getSimpleVT - Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:203
This file describes how to lower LLVM code to machine code.
ShuffleKind
The various kinds of shuffle patterns for vector queries.