LLVM  3.7.0
PPCInstPrinter.cpp
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1 //===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This class prints an PPC MCInst to a .s file.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCInstPrinter.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstrInfo.h"
20 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/MC/MCSymbol.h"
26 using namespace llvm;
27 
28 #define DEBUG_TYPE "asm-printer"
29 
30 // FIXME: Once the integrated assembler supports full register names, tie this
31 // to the verbose-asm setting.
32 static cl::opt<bool>
33 FullRegNames("ppc-asm-full-reg-names", cl::Hidden, cl::init(false),
34  cl::desc("Use full register names when printing assembly"));
35 
36 #define PRINT_ALIAS_INSTR
37 #include "PPCGenAsmWriter.inc"
38 
39 void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
40  const char *RegName = getRegisterName(RegNo);
41  if (RegName[0] == 'q' /* QPX */) {
42  // The system toolchain on the BG/Q does not understand QPX register names
43  // in .cfi_* directives, so print the name of the floating-point
44  // subregister instead.
45  std::string RN(RegName);
46 
47  RN[0] = 'f';
48  OS << RN;
49 
50  return;
51  }
52 
53  OS << RegName;
54 }
55 
57  StringRef Annot, const MCSubtargetInfo &STI) {
58  // Check for slwi/srwi mnemonics.
59  if (MI->getOpcode() == PPC::RLWINM) {
60  unsigned char SH = MI->getOperand(2).getImm();
61  unsigned char MB = MI->getOperand(3).getImm();
62  unsigned char ME = MI->getOperand(4).getImm();
63  bool useSubstituteMnemonic = false;
64  if (SH <= 31 && MB == 0 && ME == (31-SH)) {
65  O << "\tslwi "; useSubstituteMnemonic = true;
66  }
67  if (SH <= 31 && MB == (32-SH) && ME == 31) {
68  O << "\tsrwi "; useSubstituteMnemonic = true;
69  SH = 32-SH;
70  }
71  if (useSubstituteMnemonic) {
72  printOperand(MI, 0, O);
73  O << ", ";
74  printOperand(MI, 1, O);
75  O << ", " << (unsigned int)SH;
76 
77  printAnnotation(O, Annot);
78  return;
79  }
80  }
81 
82  if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) &&
83  MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
84  O << "\tmr ";
85  printOperand(MI, 0, O);
86  O << ", ";
87  printOperand(MI, 1, O);
88  printAnnotation(O, Annot);
89  return;
90  }
91 
92  if (MI->getOpcode() == PPC::RLDICR) {
93  unsigned char SH = MI->getOperand(2).getImm();
94  unsigned char ME = MI->getOperand(3).getImm();
95  // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
96  if (63-SH == ME) {
97  O << "\tsldi ";
98  printOperand(MI, 0, O);
99  O << ", ";
100  printOperand(MI, 1, O);
101  O << ", " << (unsigned int)SH;
102  printAnnotation(O, Annot);
103  return;
104  }
105  }
106 
107  // dcbt[st] is printed manually here because:
108  // 1. The assembly syntax is different between embedded and server targets
109  // 2. We must print the short mnemonics for TH == 0 because the
110  // embedded/server syntax default will not be stable across assemblers
111  // The syntax for dcbt is:
112  // dcbt ra, rb, th [server]
113  // dcbt th, ra, rb [embedded]
114  // where th can be omitted when it is 0. dcbtst is the same.
115  if (MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) {
116  unsigned char TH = MI->getOperand(0).getImm();
117  O << "\tdcbt";
118  if (MI->getOpcode() == PPC::DCBTST)
119  O << "st";
120  if (TH == 16)
121  O << "t";
122  O << " ";
123 
124  bool IsBookE = STI.getFeatureBits()[PPC::FeatureBookE];
125  if (IsBookE && TH != 0 && TH != 16)
126  O << (unsigned int) TH << ", ";
127 
128  printOperand(MI, 1, O);
129  O << ", ";
130  printOperand(MI, 2, O);
131 
132  if (!IsBookE && TH != 0 && TH != 16)
133  O << ", " << (unsigned int) TH;
134 
135  printAnnotation(O, Annot);
136  return;
137  }
138 
139  // For fast-isel, a COPY_TO_REGCLASS may survive this long. This is
140  // used when converting a 32-bit float to a 64-bit float as part of
141  // conversion to an integer (see PPCFastISel.cpp:SelectFPToI()),
142  // as otherwise we have problems with incorrect register classes
143  // in machine instruction verification. For now, just avoid trying
144  // to print it as such an instruction has no effect (a 32-bit float
145  // in a register is already in 64-bit form, just with lower
146  // precision). FIXME: Is there a better solution?
148  return;
149 
150  if (!printAliasInstr(MI, O))
151  printInstruction(MI, O);
152  printAnnotation(O, Annot);
153 }
154 
155 
157  raw_ostream &O,
158  const char *Modifier) {
159  unsigned Code = MI->getOperand(OpNo).getImm();
160 
161  if (StringRef(Modifier) == "cc") {
162  switch ((PPC::Predicate)Code) {
163  case PPC::PRED_LT_MINUS:
164  case PPC::PRED_LT_PLUS:
165  case PPC::PRED_LT:
166  O << "lt";
167  return;
168  case PPC::PRED_LE_MINUS:
169  case PPC::PRED_LE_PLUS:
170  case PPC::PRED_LE:
171  O << "le";
172  return;
173  case PPC::PRED_EQ_MINUS:
174  case PPC::PRED_EQ_PLUS:
175  case PPC::PRED_EQ:
176  O << "eq";
177  return;
178  case PPC::PRED_GE_MINUS:
179  case PPC::PRED_GE_PLUS:
180  case PPC::PRED_GE:
181  O << "ge";
182  return;
183  case PPC::PRED_GT_MINUS:
184  case PPC::PRED_GT_PLUS:
185  case PPC::PRED_GT:
186  O << "gt";
187  return;
188  case PPC::PRED_NE_MINUS:
189  case PPC::PRED_NE_PLUS:
190  case PPC::PRED_NE:
191  O << "ne";
192  return;
193  case PPC::PRED_UN_MINUS:
194  case PPC::PRED_UN_PLUS:
195  case PPC::PRED_UN:
196  O << "un";
197  return;
198  case PPC::PRED_NU_MINUS:
199  case PPC::PRED_NU_PLUS:
200  case PPC::PRED_NU:
201  O << "nu";
202  return;
203  case PPC::PRED_BIT_SET:
204  case PPC::PRED_BIT_UNSET:
205  llvm_unreachable("Invalid use of bit predicate code");
206  }
207  llvm_unreachable("Invalid predicate code");
208  }
209 
210  if (StringRef(Modifier) == "pm") {
211  switch ((PPC::Predicate)Code) {
212  case PPC::PRED_LT:
213  case PPC::PRED_LE:
214  case PPC::PRED_EQ:
215  case PPC::PRED_GE:
216  case PPC::PRED_GT:
217  case PPC::PRED_NE:
218  case PPC::PRED_UN:
219  case PPC::PRED_NU:
220  return;
221  case PPC::PRED_LT_MINUS:
222  case PPC::PRED_LE_MINUS:
223  case PPC::PRED_EQ_MINUS:
224  case PPC::PRED_GE_MINUS:
225  case PPC::PRED_GT_MINUS:
226  case PPC::PRED_NE_MINUS:
227  case PPC::PRED_UN_MINUS:
228  case PPC::PRED_NU_MINUS:
229  O << "-";
230  return;
231  case PPC::PRED_LT_PLUS:
232  case PPC::PRED_LE_PLUS:
233  case PPC::PRED_EQ_PLUS:
234  case PPC::PRED_GE_PLUS:
235  case PPC::PRED_GT_PLUS:
236  case PPC::PRED_NE_PLUS:
237  case PPC::PRED_UN_PLUS:
238  case PPC::PRED_NU_PLUS:
239  O << "+";
240  return;
241  case PPC::PRED_BIT_SET:
242  case PPC::PRED_BIT_UNSET:
243  llvm_unreachable("Invalid use of bit predicate code");
244  }
245  llvm_unreachable("Invalid predicate code");
246  }
247 
248  assert(StringRef(Modifier) == "reg" &&
249  "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!");
250  printOperand(MI, OpNo+1, O);
251 }
252 
253 void PPCInstPrinter::printU1ImmOperand(const MCInst *MI, unsigned OpNo,
254  raw_ostream &O) {
255  unsigned int Value = MI->getOperand(OpNo).getImm();
256  assert(Value <= 1 && "Invalid u1imm argument!");
257  O << (unsigned int)Value;
258 }
259 
260 void PPCInstPrinter::printU2ImmOperand(const MCInst *MI, unsigned OpNo,
261  raw_ostream &O) {
262  unsigned int Value = MI->getOperand(OpNo).getImm();
263  assert(Value <= 3 && "Invalid u2imm argument!");
264  O << (unsigned int)Value;
265 }
266 
267 void PPCInstPrinter::printU3ImmOperand(const MCInst *MI, unsigned OpNo,
268  raw_ostream &O) {
269  unsigned int Value = MI->getOperand(OpNo).getImm();
270  assert(Value <= 8 && "Invalid u3imm argument!");
271  O << (unsigned int)Value;
272 }
273 
274 void PPCInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo,
275  raw_ostream &O) {
276  unsigned int Value = MI->getOperand(OpNo).getImm();
277  assert(Value <= 15 && "Invalid u4imm argument!");
278  O << (unsigned int)Value;
279 }
280 
281 void PPCInstPrinter::printS5ImmOperand(const MCInst *MI, unsigned OpNo,
282  raw_ostream &O) {
283  int Value = MI->getOperand(OpNo).getImm();
284  Value = SignExtend32<5>(Value);
285  O << (int)Value;
286 }
287 
288 void PPCInstPrinter::printU5ImmOperand(const MCInst *MI, unsigned OpNo,
289  raw_ostream &O) {
290  unsigned int Value = MI->getOperand(OpNo).getImm();
291  assert(Value <= 31 && "Invalid u5imm argument!");
292  O << (unsigned int)Value;
293 }
294 
295 void PPCInstPrinter::printU6ImmOperand(const MCInst *MI, unsigned OpNo,
296  raw_ostream &O) {
297  unsigned int Value = MI->getOperand(OpNo).getImm();
298  assert(Value <= 63 && "Invalid u6imm argument!");
299  O << (unsigned int)Value;
300 }
301 
302 void PPCInstPrinter::printU10ImmOperand(const MCInst *MI, unsigned OpNo,
303  raw_ostream &O) {
304  unsigned short Value = MI->getOperand(OpNo).getImm();
305  assert(Value <= 1023 && "Invalid u10imm argument!");
306  O << (unsigned short)Value;
307 }
308 
309 void PPCInstPrinter::printU12ImmOperand(const MCInst *MI, unsigned OpNo,
310  raw_ostream &O) {
311  unsigned short Value = MI->getOperand(OpNo).getImm();
312  assert(Value <= 4095 && "Invalid u12imm argument!");
313  O << (unsigned short)Value;
314 }
315 
316 void PPCInstPrinter::printS16ImmOperand(const MCInst *MI, unsigned OpNo,
317  raw_ostream &O) {
318  if (MI->getOperand(OpNo).isImm())
319  O << (short)MI->getOperand(OpNo).getImm();
320  else
321  printOperand(MI, OpNo, O);
322 }
323 
324 void PPCInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
325  raw_ostream &O) {
326  if (MI->getOperand(OpNo).isImm())
327  O << (unsigned short)MI->getOperand(OpNo).getImm();
328  else
329  printOperand(MI, OpNo, O);
330 }
331 
332 void PPCInstPrinter::printBranchOperand(const MCInst *MI, unsigned OpNo,
333  raw_ostream &O) {
334  if (!MI->getOperand(OpNo).isImm())
335  return printOperand(MI, OpNo, O);
336 
337  // Branches can take an immediate operand. This is used by the branch
338  // selection pass to print .+8, an eight byte displacement from the PC.
339  O << ".+";
340  printAbsBranchOperand(MI, OpNo, O);
341 }
342 
344  raw_ostream &O) {
345  if (!MI->getOperand(OpNo).isImm())
346  return printOperand(MI, OpNo, O);
347 
348  O << SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2);
349 }
350 
351 
352 void PPCInstPrinter::printcrbitm(const MCInst *MI, unsigned OpNo,
353  raw_ostream &O) {
354  unsigned CCReg = MI->getOperand(OpNo).getReg();
355  unsigned RegNo;
356  switch (CCReg) {
357  default: llvm_unreachable("Unknown CR register");
358  case PPC::CR0: RegNo = 0; break;
359  case PPC::CR1: RegNo = 1; break;
360  case PPC::CR2: RegNo = 2; break;
361  case PPC::CR3: RegNo = 3; break;
362  case PPC::CR4: RegNo = 4; break;
363  case PPC::CR5: RegNo = 5; break;
364  case PPC::CR6: RegNo = 6; break;
365  case PPC::CR7: RegNo = 7; break;
366  }
367  O << (0x80 >> RegNo);
368 }
369 
370 void PPCInstPrinter::printMemRegImm(const MCInst *MI, unsigned OpNo,
371  raw_ostream &O) {
372  printS16ImmOperand(MI, OpNo, O);
373  O << '(';
374  if (MI->getOperand(OpNo+1).getReg() == PPC::R0)
375  O << "0";
376  else
377  printOperand(MI, OpNo+1, O);
378  O << ')';
379 }
380 
381 void PPCInstPrinter::printMemRegReg(const MCInst *MI, unsigned OpNo,
382  raw_ostream &O) {
383  // When used as the base register, r0 reads constant zero rather than
384  // the value contained in the register. For this reason, the darwin
385  // assembler requires that we print r0 as 0 (no r) when used as the base.
386  if (MI->getOperand(OpNo).getReg() == PPC::R0)
387  O << "0";
388  else
389  printOperand(MI, OpNo, O);
390  O << ", ";
391  printOperand(MI, OpNo+1, O);
392 }
393 
394 void PPCInstPrinter::printTLSCall(const MCInst *MI, unsigned OpNo,
395  raw_ostream &O) {
396  // On PPC64, VariantKind is VK_None, but on PPC32, it's VK_PLT, and it must
397  // come at the _end_ of the expression.
398  const MCOperand &Op = MI->getOperand(OpNo);
399  const MCSymbolRefExpr &refExp = cast<MCSymbolRefExpr>(*Op.getExpr());
400  O << refExp.getSymbol().getName();
401  O << '(';
402  printOperand(MI, OpNo+1, O);
403  O << ')';
404  if (refExp.getKind() != MCSymbolRefExpr::VK_None)
405  O << '@' << MCSymbolRefExpr::getVariantKindName(refExp.getKind());
406 }
407 
408 
409 /// stripRegisterPrefix - This method strips the character prefix from a
410 /// register name so that only the number is left. Used by for linux asm.
411 static const char *stripRegisterPrefix(const char *RegName) {
412  if (FullRegNames)
413  return RegName;
414 
415  switch (RegName[0]) {
416  case 'r':
417  case 'f':
418  case 'q': // for QPX
419  case 'v':
420  if (RegName[1] == 's')
421  return RegName + 2;
422  return RegName + 1;
423  case 'c': if (RegName[1] == 'r') return RegName + 2;
424  }
425 
426  return RegName;
427 }
428 
429 void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
430  raw_ostream &O) {
431  const MCOperand &Op = MI->getOperand(OpNo);
432  if (Op.isReg()) {
433  const char *RegName = getRegisterName(Op.getReg());
434  // The linux and AIX assembler does not take register prefixes.
435  if (!isDarwinSyntax())
436  RegName = stripRegisterPrefix(RegName);
437 
438  O << RegName;
439  return;
440  }
441 
442  if (Op.isImm()) {
443  O << Op.getImm();
444  return;
445  }
446 
447  assert(Op.isExpr() && "unknown operand kind in printOperand");
448  Op.getExpr()->print(O, &MAI);
449 }
450 
void printS16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
void printU2ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
const MCSymbol & getSymbol() const
Definition: MCExpr.h:328
void printS5ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
void printU4ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
void printU16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
bool isReg() const
Definition: MCInst.h:56
void printRegName(raw_ostream &OS, unsigned RegNo) const override
Print the assembler register name.
bool isDarwinSyntax() const
void printcrbitm(const MCInst *MI, unsigned OpNo, raw_ostream &O)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
void printU1ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:159
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:63
void printU12ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
void printAbsBranchOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, const MCSubtargetInfo &STI) override
Print the specified MCInst to the specified raw_ostream.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:150
bool isImm() const
Definition: MCInst.h:57
const MCExpr * getExpr() const
Definition: MCInst.h:93
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:325
void print(raw_ostream &OS, const MCAsmInfo *MAI) const
Definition: MCExpr.cpp:33
static const char * getRegisterName(unsigned RegNo)
bool isExpr() const
Definition: MCInst.h:59
void printMemRegImm(const MCInst *MI, unsigned OpNo, raw_ostream &O)
void printU3ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
void printMemRegReg(const MCInst *MI, unsigned OpNo, raw_ostream &O)
void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
void printBranchOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
void printPredicateOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O, const char *Modifier=nullptr)
static const char * stripRegisterPrefix(const char *RegName)
stripRegisterPrefix - This method strips the character prefix from a register name so that only the n...
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:27
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
unsigned getOpcode() const
Definition: MCInst.h:159
void printTLSCall(const MCInst *MI, unsigned OpNo, raw_ostream &O)
void printU6ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
bool printAliasInstr(const MCInst *MI, raw_ostream &OS)
int64_t getImm() const
Definition: MCInst.h:74
void printInstruction(const MCInst *MI, raw_ostream &O)
const MCAsmInfo & MAI
Definition: MCInstPrinter.h:44
StringRef getName() const
getName - Get the symbol name.
Definition: MCSymbol.h:205
static cl::opt< bool > FullRegNames("ppc-asm-full-reg-names", cl::Hidden, cl::init(false), cl::desc("Use full register names when printing assembly"))
COPY_TO_REGCLASS - This instruction is a placeholder for a plain register-to-register copy into a spe...
Definition: TargetOpcodes.h:66
MCSubtargetInfo - Generic base class for all target subtargets.
void printU10ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
VariantKind getKind() const
Definition: MCExpr.h:330
LLVM Value Representation.
Definition: Value.h:69
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:38
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:40
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:33
static StringRef getVariantKindName(VariantKind Kind)
Definition: MCExpr.cpp:176
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:164
void printU5ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)