LLVM  3.7.0
ARMFastISel.cpp
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1 //===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the ARM-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // ARMGenFastISel.inc, which is #included here.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "ARM.h"
17 #include "ARMBaseRegisterInfo.h"
18 #include "ARMCallingConv.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMISelLowering.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMSubtarget.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/CodeGen/Analysis.h"
26 #include "llvm/CodeGen/FastISel.h"
34 #include "llvm/IR/CallSite.h"
35 #include "llvm/IR/CallingConv.h"
36 #include "llvm/IR/DataLayout.h"
37 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/GlobalVariable.h"
40 #include "llvm/IR/Instructions.h"
41 #include "llvm/IR/IntrinsicInst.h"
42 #include "llvm/IR/Module.h"
43 #include "llvm/IR/Operator.h"
50 using namespace llvm;
51 
52 namespace {
53 
54  // All possible address modes, plus some.
55  typedef struct Address {
56  enum {
57  RegBase,
58  FrameIndexBase
59  } BaseType;
60 
61  union {
62  unsigned Reg;
63  int FI;
64  } Base;
65 
66  int Offset;
67 
68  // Innocuous defaults for our address.
69  Address()
70  : BaseType(RegBase), Offset(0) {
71  Base.Reg = 0;
72  }
73  } Address;
74 
75 class ARMFastISel final : public FastISel {
76 
77  /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
78  /// make the right decision when generating code for different targets.
79  const ARMSubtarget *Subtarget;
80  Module &M;
81  const TargetMachine &TM;
82  const TargetInstrInfo &TII;
83  const TargetLowering &TLI;
84  ARMFunctionInfo *AFI;
85 
86  // Convenience variables to avoid some queries.
87  bool isThumb2;
88  LLVMContext *Context;
89 
90  public:
91  explicit ARMFastISel(FunctionLoweringInfo &funcInfo,
92  const TargetLibraryInfo *libInfo)
93  : FastISel(funcInfo, libInfo),
94  Subtarget(
95  &static_cast<const ARMSubtarget &>(funcInfo.MF->getSubtarget())),
96  M(const_cast<Module &>(*funcInfo.Fn->getParent())),
97  TM(funcInfo.MF->getTarget()), TII(*Subtarget->getInstrInfo()),
98  TLI(*Subtarget->getTargetLowering()) {
99  AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
100  isThumb2 = AFI->isThumbFunction();
101  Context = &funcInfo.Fn->getContext();
102  }
103 
104  // Code from FastISel.cpp.
105  private:
106  unsigned fastEmitInst_r(unsigned MachineInstOpcode,
107  const TargetRegisterClass *RC,
108  unsigned Op0, bool Op0IsKill);
109  unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
110  const TargetRegisterClass *RC,
111  unsigned Op0, bool Op0IsKill,
112  unsigned Op1, bool Op1IsKill);
113  unsigned fastEmitInst_rrr(unsigned MachineInstOpcode,
114  const TargetRegisterClass *RC,
115  unsigned Op0, bool Op0IsKill,
116  unsigned Op1, bool Op1IsKill,
117  unsigned Op2, bool Op2IsKill);
118  unsigned fastEmitInst_ri(unsigned MachineInstOpcode,
119  const TargetRegisterClass *RC,
120  unsigned Op0, bool Op0IsKill,
121  uint64_t Imm);
122  unsigned fastEmitInst_rri(unsigned MachineInstOpcode,
123  const TargetRegisterClass *RC,
124  unsigned Op0, bool Op0IsKill,
125  unsigned Op1, bool Op1IsKill,
126  uint64_t Imm);
127  unsigned fastEmitInst_i(unsigned MachineInstOpcode,
128  const TargetRegisterClass *RC,
129  uint64_t Imm);
130 
131  // Backend specific FastISel code.
132  private:
133  bool fastSelectInstruction(const Instruction *I) override;
134  unsigned fastMaterializeConstant(const Constant *C) override;
135  unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
136  bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
137  const LoadInst *LI) override;
138  bool fastLowerArguments() override;
139  private:
140  #include "ARMGenFastISel.inc"
141 
142  // Instruction selection routines.
143  private:
144  bool SelectLoad(const Instruction *I);
145  bool SelectStore(const Instruction *I);
146  bool SelectBranch(const Instruction *I);
147  bool SelectIndirectBr(const Instruction *I);
148  bool SelectCmp(const Instruction *I);
149  bool SelectFPExt(const Instruction *I);
150  bool SelectFPTrunc(const Instruction *I);
151  bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode);
152  bool SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode);
153  bool SelectIToFP(const Instruction *I, bool isSigned);
154  bool SelectFPToI(const Instruction *I, bool isSigned);
155  bool SelectDiv(const Instruction *I, bool isSigned);
156  bool SelectRem(const Instruction *I, bool isSigned);
157  bool SelectCall(const Instruction *I, const char *IntrMemName);
158  bool SelectIntrinsicCall(const IntrinsicInst &I);
159  bool SelectSelect(const Instruction *I);
160  bool SelectRet(const Instruction *I);
161  bool SelectTrunc(const Instruction *I);
162  bool SelectIntExt(const Instruction *I);
163  bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
164 
165  // Utility routines.
166  private:
167  bool isTypeLegal(Type *Ty, MVT &VT);
168  bool isLoadTypeLegal(Type *Ty, MVT &VT);
169  bool ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
170  bool isZExt);
171  bool ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
172  unsigned Alignment = 0, bool isZExt = true,
173  bool allocReg = true);
174  bool ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
175  unsigned Alignment = 0);
176  bool ARMComputeAddress(const Value *Obj, Address &Addr);
177  void ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3);
178  bool ARMIsMemCpySmall(uint64_t Len);
179  bool ARMTryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len,
180  unsigned Alignment);
181  unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
182  unsigned ARMMaterializeFP(const ConstantFP *CFP, MVT VT);
183  unsigned ARMMaterializeInt(const Constant *C, MVT VT);
184  unsigned ARMMaterializeGV(const GlobalValue *GV, MVT VT);
185  unsigned ARMMoveToFPReg(MVT VT, unsigned SrcReg);
186  unsigned ARMMoveToIntReg(MVT VT, unsigned SrcReg);
187  unsigned ARMSelectCallOp(bool UseReg);
188  unsigned ARMLowerPICELF(const GlobalValue *GV, unsigned Align, MVT VT);
189 
190  const TargetLowering *getTargetLowering() { return &TLI; }
191 
192  // Call handling routines.
193  private:
194  CCAssignFn *CCAssignFnForCall(CallingConv::ID CC,
195  bool Return,
196  bool isVarArg);
197  bool ProcessCallArgs(SmallVectorImpl<Value*> &Args,
198  SmallVectorImpl<unsigned> &ArgRegs,
199  SmallVectorImpl<MVT> &ArgVTs,
201  SmallVectorImpl<unsigned> &RegArgs,
202  CallingConv::ID CC,
203  unsigned &NumBytes,
204  bool isVarArg);
205  unsigned getLibcallReg(const Twine &Name);
206  bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
207  const Instruction *I, CallingConv::ID CC,
208  unsigned &NumBytes, bool isVarArg);
209  bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call);
210 
211  // OptionalDef handling routines.
212  private:
213  bool isARMNEONPred(const MachineInstr *MI);
214  bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
215  const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
216  void AddLoadStoreOperands(MVT VT, Address &Addr,
217  const MachineInstrBuilder &MIB,
218  unsigned Flags, bool useAM3);
219 };
220 
221 } // end anonymous namespace
222 
223 #include "ARMGenCallingConv.inc"
224 
225 // DefinesOptionalPredicate - This is different from DefinesPredicate in that
226 // we don't care about implicit defs here, just places we'll need to add a
227 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
228 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
229  if (!MI->hasOptionalDef())
230  return false;
231 
232  // Look to see if our OptionalDef is defining CPSR or CCR.
233  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
234  const MachineOperand &MO = MI->getOperand(i);
235  if (!MO.isReg() || !MO.isDef()) continue;
236  if (MO.getReg() == ARM::CPSR)
237  *CPSR = true;
238  }
239  return true;
240 }
241 
242 bool ARMFastISel::isARMNEONPred(const MachineInstr *MI) {
243  const MCInstrDesc &MCID = MI->getDesc();
244 
245  // If we're a thumb2 or not NEON function we'll be handled via isPredicable.
246  if ((MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainNEON ||
247  AFI->isThumb2Function())
248  return MI->isPredicable();
249 
250  for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i)
251  if (MCID.OpInfo[i].isPredicate())
252  return true;
253 
254  return false;
255 }
256 
257 // If the machine is predicable go ahead and add the predicate operands, if
258 // it needs default CC operands add those.
259 // TODO: If we want to support thumb1 then we'll need to deal with optional
260 // CPSR defs that need to be added before the remaining operands. See s_cc_out
261 // for descriptions why.
262 const MachineInstrBuilder &
263 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
264  MachineInstr *MI = &*MIB;
265 
266  // Do we use a predicate? or...
267  // Are we NEON in ARM mode and have a predicate operand? If so, I know
268  // we're not predicable but add it anyways.
269  if (isARMNEONPred(MI))
270  AddDefaultPred(MIB);
271 
272  // Do we optionally set a predicate? Preds is size > 0 iff the predicate
273  // defines CPSR. All other OptionalDefines in ARM are the CCR register.
274  bool CPSR = false;
275  if (DefinesOptionalPredicate(MI, &CPSR)) {
276  if (CPSR)
277  AddDefaultT1CC(MIB);
278  else
279  AddDefaultCC(MIB);
280  }
281  return MIB;
282 }
283 
284 unsigned ARMFastISel::fastEmitInst_r(unsigned MachineInstOpcode,
285  const TargetRegisterClass *RC,
286  unsigned Op0, bool Op0IsKill) {
287  unsigned ResultReg = createResultReg(RC);
288  const MCInstrDesc &II = TII.get(MachineInstOpcode);
289 
290  // Make sure the input operand is sufficiently constrained to be legal
291  // for this instruction.
292  Op0 = constrainOperandRegClass(II, Op0, 1);
293  if (II.getNumDefs() >= 1) {
294  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II,
295  ResultReg).addReg(Op0, Op0IsKill * RegState::Kill));
296  } else {
297  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
298  .addReg(Op0, Op0IsKill * RegState::Kill));
299  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
300  TII.get(TargetOpcode::COPY), ResultReg)
301  .addReg(II.ImplicitDefs[0]));
302  }
303  return ResultReg;
304 }
305 
306 unsigned ARMFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
307  const TargetRegisterClass *RC,
308  unsigned Op0, bool Op0IsKill,
309  unsigned Op1, bool Op1IsKill) {
310  unsigned ResultReg = createResultReg(RC);
311  const MCInstrDesc &II = TII.get(MachineInstOpcode);
312 
313  // Make sure the input operands are sufficiently constrained to be legal
314  // for this instruction.
315  Op0 = constrainOperandRegClass(II, Op0, 1);
316  Op1 = constrainOperandRegClass(II, Op1, 2);
317 
318  if (II.getNumDefs() >= 1) {
319  AddOptionalDefs(
320  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
321  .addReg(Op0, Op0IsKill * RegState::Kill)
322  .addReg(Op1, Op1IsKill * RegState::Kill));
323  } else {
324  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
325  .addReg(Op0, Op0IsKill * RegState::Kill)
326  .addReg(Op1, Op1IsKill * RegState::Kill));
327  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
328  TII.get(TargetOpcode::COPY), ResultReg)
329  .addReg(II.ImplicitDefs[0]));
330  }
331  return ResultReg;
332 }
333 
334 unsigned ARMFastISel::fastEmitInst_rrr(unsigned MachineInstOpcode,
335  const TargetRegisterClass *RC,
336  unsigned Op0, bool Op0IsKill,
337  unsigned Op1, bool Op1IsKill,
338  unsigned Op2, bool Op2IsKill) {
339  unsigned ResultReg = createResultReg(RC);
340  const MCInstrDesc &II = TII.get(MachineInstOpcode);
341 
342  // Make sure the input operands are sufficiently constrained to be legal
343  // for this instruction.
344  Op0 = constrainOperandRegClass(II, Op0, 1);
345  Op1 = constrainOperandRegClass(II, Op1, 2);
346  Op2 = constrainOperandRegClass(II, Op1, 3);
347 
348  if (II.getNumDefs() >= 1) {
349  AddOptionalDefs(
350  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
351  .addReg(Op0, Op0IsKill * RegState::Kill)
352  .addReg(Op1, Op1IsKill * RegState::Kill)
353  .addReg(Op2, Op2IsKill * RegState::Kill));
354  } else {
355  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
356  .addReg(Op0, Op0IsKill * RegState::Kill)
357  .addReg(Op1, Op1IsKill * RegState::Kill)
358  .addReg(Op2, Op2IsKill * RegState::Kill));
359  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
360  TII.get(TargetOpcode::COPY), ResultReg)
361  .addReg(II.ImplicitDefs[0]));
362  }
363  return ResultReg;
364 }
365 
366 unsigned ARMFastISel::fastEmitInst_ri(unsigned MachineInstOpcode,
367  const TargetRegisterClass *RC,
368  unsigned Op0, bool Op0IsKill,
369  uint64_t Imm) {
370  unsigned ResultReg = createResultReg(RC);
371  const MCInstrDesc &II = TII.get(MachineInstOpcode);
372 
373  // Make sure the input operand is sufficiently constrained to be legal
374  // for this instruction.
375  Op0 = constrainOperandRegClass(II, Op0, 1);
376  if (II.getNumDefs() >= 1) {
377  AddOptionalDefs(
378  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
379  .addReg(Op0, Op0IsKill * RegState::Kill)
380  .addImm(Imm));
381  } else {
382  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
383  .addReg(Op0, Op0IsKill * RegState::Kill)
384  .addImm(Imm));
385  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
386  TII.get(TargetOpcode::COPY), ResultReg)
387  .addReg(II.ImplicitDefs[0]));
388  }
389  return ResultReg;
390 }
391 
392 unsigned ARMFastISel::fastEmitInst_rri(unsigned MachineInstOpcode,
393  const TargetRegisterClass *RC,
394  unsigned Op0, bool Op0IsKill,
395  unsigned Op1, bool Op1IsKill,
396  uint64_t Imm) {
397  unsigned ResultReg = createResultReg(RC);
398  const MCInstrDesc &II = TII.get(MachineInstOpcode);
399 
400  // Make sure the input operands are sufficiently constrained to be legal
401  // for this instruction.
402  Op0 = constrainOperandRegClass(II, Op0, 1);
403  Op1 = constrainOperandRegClass(II, Op1, 2);
404  if (II.getNumDefs() >= 1) {
405  AddOptionalDefs(
406  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
407  .addReg(Op0, Op0IsKill * RegState::Kill)
408  .addReg(Op1, Op1IsKill * RegState::Kill)
409  .addImm(Imm));
410  } else {
411  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
412  .addReg(Op0, Op0IsKill * RegState::Kill)
413  .addReg(Op1, Op1IsKill * RegState::Kill)
414  .addImm(Imm));
415  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
416  TII.get(TargetOpcode::COPY), ResultReg)
417  .addReg(II.ImplicitDefs[0]));
418  }
419  return ResultReg;
420 }
421 
422 unsigned ARMFastISel::fastEmitInst_i(unsigned MachineInstOpcode,
423  const TargetRegisterClass *RC,
424  uint64_t Imm) {
425  unsigned ResultReg = createResultReg(RC);
426  const MCInstrDesc &II = TII.get(MachineInstOpcode);
427 
428  if (II.getNumDefs() >= 1) {
429  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II,
430  ResultReg).addImm(Imm));
431  } else {
432  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
433  .addImm(Imm));
434  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
435  TII.get(TargetOpcode::COPY), ResultReg)
436  .addReg(II.ImplicitDefs[0]));
437  }
438  return ResultReg;
439 }
440 
441 // TODO: Don't worry about 64-bit now, but when this is fixed remove the
442 // checks from the various callers.
443 unsigned ARMFastISel::ARMMoveToFPReg(MVT VT, unsigned SrcReg) {
444  if (VT == MVT::f64) return 0;
445 
446  unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
447  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
448  TII.get(ARM::VMOVSR), MoveReg)
449  .addReg(SrcReg));
450  return MoveReg;
451 }
452 
453 unsigned ARMFastISel::ARMMoveToIntReg(MVT VT, unsigned SrcReg) {
454  if (VT == MVT::i64) return 0;
455 
456  unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
457  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
458  TII.get(ARM::VMOVRS), MoveReg)
459  .addReg(SrcReg));
460  return MoveReg;
461 }
462 
463 // For double width floating point we need to materialize two constants
464 // (the high and the low) into integer registers then use a move to get
465 // the combined constant into an FP reg.
466 unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, MVT VT) {
467  const APFloat Val = CFP->getValueAPF();
468  bool is64bit = VT == MVT::f64;
469 
470  // This checks to see if we can use VFP3 instructions to materialize
471  // a constant, otherwise we have to go through the constant pool.
472  if (TLI.isFPImmLegal(Val, VT)) {
473  int Imm;
474  unsigned Opc;
475  if (is64bit) {
476  Imm = ARM_AM::getFP64Imm(Val);
477  Opc = ARM::FCONSTD;
478  } else {
479  Imm = ARM_AM::getFP32Imm(Val);
480  Opc = ARM::FCONSTS;
481  }
482  unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
483  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
484  TII.get(Opc), DestReg).addImm(Imm));
485  return DestReg;
486  }
487 
488  // Require VFP2 for loading fp constants.
489  if (!Subtarget->hasVFP2()) return false;
490 
491  // MachineConstantPool wants an explicit alignment.
492  unsigned Align = DL.getPrefTypeAlignment(CFP->getType());
493  if (Align == 0) {
494  // TODO: Figure out if this is correct.
495  Align = DL.getTypeAllocSize(CFP->getType());
496  }
497  unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
498  unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
499  unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
500 
501  // The extra reg is for addrmode5.
502  AddOptionalDefs(
503  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
504  .addConstantPoolIndex(Idx)
505  .addReg(0));
506  return DestReg;
507 }
508 
509 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, MVT VT) {
510 
511  if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
512  return 0;
513 
514  // If we can do this in a single instruction without a constant pool entry
515  // do so now.
516  const ConstantInt *CI = cast<ConstantInt>(C);
517  if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getZExtValue())) {
518  unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16;
519  const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass :
520  &ARM::GPRRegClass;
521  unsigned ImmReg = createResultReg(RC);
522  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
523  TII.get(Opc), ImmReg)
524  .addImm(CI->getZExtValue()));
525  return ImmReg;
526  }
527 
528  // Use MVN to emit negative constants.
529  if (VT == MVT::i32 && Subtarget->hasV6T2Ops() && CI->isNegative()) {
530  unsigned Imm = (unsigned)~(CI->getSExtValue());
531  bool UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
532  (ARM_AM::getSOImmVal(Imm) != -1);
533  if (UseImm) {
534  unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi;
535  const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass :
536  &ARM::GPRRegClass;
537  unsigned ImmReg = createResultReg(RC);
538  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
539  TII.get(Opc), ImmReg)
540  .addImm(Imm));
541  return ImmReg;
542  }
543  }
544 
545  unsigned ResultReg = 0;
546  if (Subtarget->useMovt(*FuncInfo.MF))
547  ResultReg = fastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
548 
549  if (ResultReg)
550  return ResultReg;
551 
552  // Load from constant pool. For now 32-bit only.
553  if (VT != MVT::i32)
554  return 0;
555 
556  // MachineConstantPool wants an explicit alignment.
557  unsigned Align = DL.getPrefTypeAlignment(C->getType());
558  if (Align == 0) {
559  // TODO: Figure out if this is correct.
560  Align = DL.getTypeAllocSize(C->getType());
561  }
562  unsigned Idx = MCP.getConstantPoolIndex(C, Align);
563  ResultReg = createResultReg(TLI.getRegClassFor(VT));
564  if (isThumb2)
565  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
566  TII.get(ARM::t2LDRpci), ResultReg)
567  .addConstantPoolIndex(Idx));
568  else {
569  // The extra immediate is for addrmode2.
570  ResultReg = constrainOperandRegClass(TII.get(ARM::LDRcp), ResultReg, 0);
571  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
572  TII.get(ARM::LDRcp), ResultReg)
573  .addConstantPoolIndex(Idx)
574  .addImm(0));
575  }
576  return ResultReg;
577 }
578 
579 unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, MVT VT) {
580  // For now 32-bit only.
581  if (VT != MVT::i32) return 0;
582 
583  Reloc::Model RelocM = TM.getRelocationModel();
584  bool IsIndirect = Subtarget->GVIsIndirectSymbol(GV, RelocM);
585  const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass
586  : &ARM::GPRRegClass;
587  unsigned DestReg = createResultReg(RC);
588 
589  // FastISel TLS support on non-MachO is broken, punt to SelectionDAG.
590  const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
591  bool IsThreadLocal = GVar && GVar->isThreadLocal();
592  if (!Subtarget->isTargetMachO() && IsThreadLocal) return 0;
593 
594  // Use movw+movt when possible, it avoids constant pool entries.
595  // Non-darwin targets only support static movt relocations in FastISel.
596  if (Subtarget->useMovt(*FuncInfo.MF) &&
597  (Subtarget->isTargetMachO() || RelocM == Reloc::Static)) {
598  unsigned Opc;
599  unsigned char TF = 0;
600  if (Subtarget->isTargetMachO())
601  TF = ARMII::MO_NONLAZY;
602 
603  switch (RelocM) {
604  case Reloc::PIC_:
605  Opc = isThumb2 ? ARM::t2MOV_ga_pcrel : ARM::MOV_ga_pcrel;
606  break;
607  default:
608  Opc = isThumb2 ? ARM::t2MOVi32imm : ARM::MOVi32imm;
609  break;
610  }
611  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
612  TII.get(Opc), DestReg).addGlobalAddress(GV, 0, TF));
613  } else {
614  // MachineConstantPool wants an explicit alignment.
615  unsigned Align = DL.getPrefTypeAlignment(GV->getType());
616  if (Align == 0) {
617  // TODO: Figure out if this is correct.
618  Align = DL.getTypeAllocSize(GV->getType());
619  }
620 
621  if (Subtarget->isTargetELF() && RelocM == Reloc::PIC_)
622  return ARMLowerPICELF(GV, Align, VT);
623 
624  // Grab index.
625  unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 :
626  (Subtarget->isThumb() ? 4 : 8);
627  unsigned Id = AFI->createPICLabelUId();
630  PCAdj);
631  unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
632 
633  // Load value.
635  if (isThumb2) {
636  unsigned Opc = (RelocM!=Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic;
637  MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
638  DestReg).addConstantPoolIndex(Idx);
639  if (RelocM == Reloc::PIC_)
640  MIB.addImm(Id);
641  AddOptionalDefs(MIB);
642  } else {
643  // The extra immediate is for addrmode2.
644  DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0);
645  MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
646  TII.get(ARM::LDRcp), DestReg)
647  .addConstantPoolIndex(Idx)
648  .addImm(0);
649  AddOptionalDefs(MIB);
650 
651  if (RelocM == Reloc::PIC_) {
652  unsigned Opc = IsIndirect ? ARM::PICLDR : ARM::PICADD;
653  unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
654 
655  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
656  DbgLoc, TII.get(Opc), NewDestReg)
657  .addReg(DestReg)
658  .addImm(Id);
659  AddOptionalDefs(MIB);
660  return NewDestReg;
661  }
662  }
663  }
664 
665  if (IsIndirect) {
667  unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
668  if (isThumb2)
669  MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
670  TII.get(ARM::t2LDRi12), NewDestReg)
671  .addReg(DestReg)
672  .addImm(0);
673  else
674  MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
675  TII.get(ARM::LDRi12), NewDestReg)
676  .addReg(DestReg)
677  .addImm(0);
678  DestReg = NewDestReg;
679  AddOptionalDefs(MIB);
680  }
681 
682  return DestReg;
683 }
684 
685 unsigned ARMFastISel::fastMaterializeConstant(const Constant *C) {
686  EVT CEVT = TLI.getValueType(DL, C->getType(), true);
687 
688  // Only handle simple types.
689  if (!CEVT.isSimple()) return 0;
690  MVT VT = CEVT.getSimpleVT();
691 
692  if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
693  return ARMMaterializeFP(CFP, VT);
694  else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
695  return ARMMaterializeGV(GV, VT);
696  else if (isa<ConstantInt>(C))
697  return ARMMaterializeInt(C, VT);
698 
699  return 0;
700 }
701 
702 // TODO: unsigned ARMFastISel::TargetMaterializeFloatZero(const ConstantFP *CF);
703 
704 unsigned ARMFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
705  // Don't handle dynamic allocas.
706  if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
707 
708  MVT VT;
709  if (!isLoadTypeLegal(AI->getType(), VT)) return 0;
710 
712  FuncInfo.StaticAllocaMap.find(AI);
713 
714  // This will get lowered later into the correct offsets and registers
715  // via rewriteXFrameIndex.
716  if (SI != FuncInfo.StaticAllocaMap.end()) {
717  unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
718  const TargetRegisterClass* RC = TLI.getRegClassFor(VT);
719  unsigned ResultReg = createResultReg(RC);
720  ResultReg = constrainOperandRegClass(TII.get(Opc), ResultReg, 0);
721 
722  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
723  TII.get(Opc), ResultReg)
724  .addFrameIndex(SI->second)
725  .addImm(0));
726  return ResultReg;
727  }
728 
729  return 0;
730 }
731 
732 bool ARMFastISel::isTypeLegal(Type *Ty, MVT &VT) {
733  EVT evt = TLI.getValueType(DL, Ty, true);
734 
735  // Only handle simple types.
736  if (evt == MVT::Other || !evt.isSimple()) return false;
737  VT = evt.getSimpleVT();
738 
739  // Handle all legal types, i.e. a register that will directly hold this
740  // value.
741  return TLI.isTypeLegal(VT);
742 }
743 
744 bool ARMFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
745  if (isTypeLegal(Ty, VT)) return true;
746 
747  // If this is a type than can be sign or zero-extended to a basic operation
748  // go ahead and accept it now.
749  if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
750  return true;
751 
752  return false;
753 }
754 
755 // Computes the address to get to an object.
756 bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) {
757  // Some boilerplate from the X86 FastISel.
758  const User *U = nullptr;
759  unsigned Opcode = Instruction::UserOp1;
760  if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
761  // Don't walk into other basic blocks unless the object is an alloca from
762  // another block, otherwise it may not have a virtual register assigned.
763  if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
764  FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
765  Opcode = I->getOpcode();
766  U = I;
767  }
768  } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
769  Opcode = C->getOpcode();
770  U = C;
771  }
772 
773  if (PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
774  if (Ty->getAddressSpace() > 255)
775  // Fast instruction selection doesn't support the special
776  // address spaces.
777  return false;
778 
779  switch (Opcode) {
780  default:
781  break;
782  case Instruction::BitCast:
783  // Look through bitcasts.
784  return ARMComputeAddress(U->getOperand(0), Addr);
785  case Instruction::IntToPtr:
786  // Look past no-op inttoptrs.
787  if (TLI.getValueType(DL, U->getOperand(0)->getType()) ==
788  TLI.getPointerTy(DL))
789  return ARMComputeAddress(U->getOperand(0), Addr);
790  break;
791  case Instruction::PtrToInt:
792  // Look past no-op ptrtoints.
793  if (TLI.getValueType(DL, U->getType()) == TLI.getPointerTy(DL))
794  return ARMComputeAddress(U->getOperand(0), Addr);
795  break;
796  case Instruction::GetElementPtr: {
797  Address SavedAddr = Addr;
798  int TmpOffset = Addr.Offset;
799 
800  // Iterate through the GEP folding the constants into offsets where
801  // we can.
803  for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
804  i != e; ++i, ++GTI) {
805  const Value *Op = *i;
806  if (StructType *STy = dyn_cast<StructType>(*GTI)) {
807  const StructLayout *SL = DL.getStructLayout(STy);
808  unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
809  TmpOffset += SL->getElementOffset(Idx);
810  } else {
811  uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
812  for (;;) {
813  if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
814  // Constant-offset addressing.
815  TmpOffset += CI->getSExtValue() * S;
816  break;
817  }
818  if (canFoldAddIntoGEP(U, Op)) {
819  // A compatible add with a constant operand. Fold the constant.
820  ConstantInt *CI =
821  cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
822  TmpOffset += CI->getSExtValue() * S;
823  // Iterate on the other operand.
824  Op = cast<AddOperator>(Op)->getOperand(0);
825  continue;
826  }
827  // Unsupported
828  goto unsupported_gep;
829  }
830  }
831  }
832 
833  // Try to grab the base operand now.
834  Addr.Offset = TmpOffset;
835  if (ARMComputeAddress(U->getOperand(0), Addr)) return true;
836 
837  // We failed, restore everything and try the other options.
838  Addr = SavedAddr;
839 
840  unsupported_gep:
841  break;
842  }
843  case Instruction::Alloca: {
844  const AllocaInst *AI = cast<AllocaInst>(Obj);
846  FuncInfo.StaticAllocaMap.find(AI);
847  if (SI != FuncInfo.StaticAllocaMap.end()) {
848  Addr.BaseType = Address::FrameIndexBase;
849  Addr.Base.FI = SI->second;
850  return true;
851  }
852  break;
853  }
854  }
855 
856  // Try to get this in a register if nothing else has worked.
857  if (Addr.Base.Reg == 0) Addr.Base.Reg = getRegForValue(Obj);
858  return Addr.Base.Reg != 0;
859 }
860 
861 void ARMFastISel::ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3) {
862  bool needsLowering = false;
863  switch (VT.SimpleTy) {
864  default: llvm_unreachable("Unhandled load/store type!");
865  case MVT::i1:
866  case MVT::i8:
867  case MVT::i16:
868  case MVT::i32:
869  if (!useAM3) {
870  // Integer loads/stores handle 12-bit offsets.
871  needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
872  // Handle negative offsets.
873  if (needsLowering && isThumb2)
874  needsLowering = !(Subtarget->hasV6T2Ops() && Addr.Offset < 0 &&
875  Addr.Offset > -256);
876  } else {
877  // ARM halfword load/stores and signed byte loads use +/-imm8 offsets.
878  needsLowering = (Addr.Offset > 255 || Addr.Offset < -255);
879  }
880  break;
881  case MVT::f32:
882  case MVT::f64:
883  // Floating point operands handle 8-bit offsets.
884  needsLowering = ((Addr.Offset & 0xff) != Addr.Offset);
885  break;
886  }
887 
888  // If this is a stack pointer and the offset needs to be simplified then
889  // put the alloca address into a register, set the base type back to
890  // register and continue. This should almost never happen.
891  if (needsLowering && Addr.BaseType == Address::FrameIndexBase) {
892  const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass
893  : &ARM::GPRRegClass;
894  unsigned ResultReg = createResultReg(RC);
895  unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
896  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
897  TII.get(Opc), ResultReg)
898  .addFrameIndex(Addr.Base.FI)
899  .addImm(0));
900  Addr.Base.Reg = ResultReg;
901  Addr.BaseType = Address::RegBase;
902  }
903 
904  // Since the offset is too large for the load/store instruction
905  // get the reg+offset into a register.
906  if (needsLowering) {
907  Addr.Base.Reg = fastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg,
908  /*Op0IsKill*/false, Addr.Offset, MVT::i32);
909  Addr.Offset = 0;
910  }
911 }
912 
913 void ARMFastISel::AddLoadStoreOperands(MVT VT, Address &Addr,
914  const MachineInstrBuilder &MIB,
915  unsigned Flags, bool useAM3) {
916  // addrmode5 output depends on the selection dag addressing dividing the
917  // offset by 4 that it then later multiplies. Do this here as well.
918  if (VT.SimpleTy == MVT::f32 || VT.SimpleTy == MVT::f64)
919  Addr.Offset /= 4;
920 
921  // Frame base works a bit differently. Handle it separately.
922  if (Addr.BaseType == Address::FrameIndexBase) {
923  int FI = Addr.Base.FI;
924  int Offset = Addr.Offset;
925  MachineMemOperand *MMO =
926  FuncInfo.MF->getMachineMemOperand(
928  Flags,
929  MFI.getObjectSize(FI),
930  MFI.getObjectAlignment(FI));
931  // Now add the rest of the operands.
932  MIB.addFrameIndex(FI);
933 
934  // ARM halfword load/stores and signed byte loads need an additional
935  // operand.
936  if (useAM3) {
937  signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
938  MIB.addReg(0);
939  MIB.addImm(Imm);
940  } else {
941  MIB.addImm(Addr.Offset);
942  }
943  MIB.addMemOperand(MMO);
944  } else {
945  // Now add the rest of the operands.
946  MIB.addReg(Addr.Base.Reg);
947 
948  // ARM halfword load/stores and signed byte loads need an additional
949  // operand.
950  if (useAM3) {
951  signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
952  MIB.addReg(0);
953  MIB.addImm(Imm);
954  } else {
955  MIB.addImm(Addr.Offset);
956  }
957  }
958  AddOptionalDefs(MIB);
959 }
960 
961 bool ARMFastISel::ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
962  unsigned Alignment, bool isZExt, bool allocReg) {
963  unsigned Opc;
964  bool useAM3 = false;
965  bool needVMOV = false;
966  const TargetRegisterClass *RC;
967  switch (VT.SimpleTy) {
968  // This is mostly going to be Neon/vector support.
969  default: return false;
970  case MVT::i1:
971  case MVT::i8:
972  if (isThumb2) {
973  if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
974  Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8;
975  else
976  Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12;
977  } else {
978  if (isZExt) {
979  Opc = ARM::LDRBi12;
980  } else {
981  Opc = ARM::LDRSB;
982  useAM3 = true;
983  }
984  }
985  RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
986  break;
987  case MVT::i16:
988  if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem())
989  return false;
990 
991  if (isThumb2) {
992  if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
993  Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8;
994  else
995  Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12;
996  } else {
997  Opc = isZExt ? ARM::LDRH : ARM::LDRSH;
998  useAM3 = true;
999  }
1000  RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
1001  break;
1002  case MVT::i32:
1003  if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem())
1004  return false;
1005 
1006  if (isThumb2) {
1007  if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1008  Opc = ARM::t2LDRi8;
1009  else
1010  Opc = ARM::t2LDRi12;
1011  } else {
1012  Opc = ARM::LDRi12;
1013  }
1014  RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
1015  break;
1016  case MVT::f32:
1017  if (!Subtarget->hasVFP2()) return false;
1018  // Unaligned loads need special handling. Floats require word-alignment.
1019  if (Alignment && Alignment < 4) {
1020  needVMOV = true;
1021  VT = MVT::i32;
1022  Opc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;
1023  RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
1024  } else {
1025  Opc = ARM::VLDRS;
1026  RC = TLI.getRegClassFor(VT);
1027  }
1028  break;
1029  case MVT::f64:
1030  if (!Subtarget->hasVFP2()) return false;
1031  // FIXME: Unaligned loads need special handling. Doublewords require
1032  // word-alignment.
1033  if (Alignment && Alignment < 4)
1034  return false;
1035 
1036  Opc = ARM::VLDRD;
1037  RC = TLI.getRegClassFor(VT);
1038  break;
1039  }
1040  // Simplify this down to something we can handle.
1041  ARMSimplifyAddress(Addr, VT, useAM3);
1042 
1043  // Create the base instruction, then add the operands.
1044  if (allocReg)
1045  ResultReg = createResultReg(RC);
1046  assert (ResultReg > 255 && "Expected an allocated virtual register.");
1047  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1048  TII.get(Opc), ResultReg);
1049  AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOLoad, useAM3);
1050 
1051  // If we had an unaligned load of a float we've converted it to an regular
1052  // load. Now we must move from the GRP to the FP register.
1053  if (needVMOV) {
1054  unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1055  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1056  TII.get(ARM::VMOVSR), MoveReg)
1057  .addReg(ResultReg));
1058  ResultReg = MoveReg;
1059  }
1060  return true;
1061 }
1062 
1063 bool ARMFastISel::SelectLoad(const Instruction *I) {
1064  // Atomic loads need special handling.
1065  if (cast<LoadInst>(I)->isAtomic())
1066  return false;
1067 
1068  // Verify we have a legal type before going any further.
1069  MVT VT;
1070  if (!isLoadTypeLegal(I->getType(), VT))
1071  return false;
1072 
1073  // See if we can handle this address.
1074  Address Addr;
1075  if (!ARMComputeAddress(I->getOperand(0), Addr)) return false;
1076 
1077  unsigned ResultReg;
1078  if (!ARMEmitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
1079  return false;
1080  updateValueMap(I, ResultReg);
1081  return true;
1082 }
1083 
1084 bool ARMFastISel::ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
1085  unsigned Alignment) {
1086  unsigned StrOpc;
1087  bool useAM3 = false;
1088  switch (VT.SimpleTy) {
1089  // This is mostly going to be Neon/vector support.
1090  default: return false;
1091  case MVT::i1: {
1092  unsigned Res = createResultReg(isThumb2 ? &ARM::tGPRRegClass
1093  : &ARM::GPRRegClass);
1094  unsigned Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
1095  SrcReg = constrainOperandRegClass(TII.get(Opc), SrcReg, 1);
1096  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1097  TII.get(Opc), Res)
1098  .addReg(SrcReg).addImm(1));
1099  SrcReg = Res;
1100  } // Fallthrough here.
1101  case MVT::i8:
1102  if (isThumb2) {
1103  if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1104  StrOpc = ARM::t2STRBi8;
1105  else
1106  StrOpc = ARM::t2STRBi12;
1107  } else {
1108  StrOpc = ARM::STRBi12;
1109  }
1110  break;
1111  case MVT::i16:
1112  if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem())
1113  return false;
1114 
1115  if (isThumb2) {
1116  if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1117  StrOpc = ARM::t2STRHi8;
1118  else
1119  StrOpc = ARM::t2STRHi12;
1120  } else {
1121  StrOpc = ARM::STRH;
1122  useAM3 = true;
1123  }
1124  break;
1125  case MVT::i32:
1126  if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem())
1127  return false;
1128 
1129  if (isThumb2) {
1130  if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1131  StrOpc = ARM::t2STRi8;
1132  else
1133  StrOpc = ARM::t2STRi12;
1134  } else {
1135  StrOpc = ARM::STRi12;
1136  }
1137  break;
1138  case MVT::f32:
1139  if (!Subtarget->hasVFP2()) return false;
1140  // Unaligned stores need special handling. Floats require word-alignment.
1141  if (Alignment && Alignment < 4) {
1142  unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::i32));
1143  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1144  TII.get(ARM::VMOVRS), MoveReg)
1145  .addReg(SrcReg));
1146  SrcReg = MoveReg;
1147  VT = MVT::i32;
1148  StrOpc = isThumb2 ? ARM::t2STRi12 : ARM::STRi12;
1149  } else {
1150  StrOpc = ARM::VSTRS;
1151  }
1152  break;
1153  case MVT::f64:
1154  if (!Subtarget->hasVFP2()) return false;
1155  // FIXME: Unaligned stores need special handling. Doublewords require
1156  // word-alignment.
1157  if (Alignment && Alignment < 4)
1158  return false;
1159 
1160  StrOpc = ARM::VSTRD;
1161  break;
1162  }
1163  // Simplify this down to something we can handle.
1164  ARMSimplifyAddress(Addr, VT, useAM3);
1165 
1166  // Create the base instruction, then add the operands.
1167  SrcReg = constrainOperandRegClass(TII.get(StrOpc), SrcReg, 0);
1168  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1169  TII.get(StrOpc))
1170  .addReg(SrcReg);
1171  AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOStore, useAM3);
1172  return true;
1173 }
1174 
1175 bool ARMFastISel::SelectStore(const Instruction *I) {
1176  Value *Op0 = I->getOperand(0);
1177  unsigned SrcReg = 0;
1178 
1179  // Atomic stores need special handling.
1180  if (cast<StoreInst>(I)->isAtomic())
1181  return false;
1182 
1183  // Verify we have a legal type before going any further.
1184  MVT VT;
1185  if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
1186  return false;
1187 
1188  // Get the value to be stored into a register.
1189  SrcReg = getRegForValue(Op0);
1190  if (SrcReg == 0) return false;
1191 
1192  // See if we can handle this address.
1193  Address Addr;
1194  if (!ARMComputeAddress(I->getOperand(1), Addr))
1195  return false;
1196 
1197  if (!ARMEmitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
1198  return false;
1199  return true;
1200 }
1201 
1203  switch (Pred) {
1204  // Needs two compares...
1205  case CmpInst::FCMP_ONE:
1206  case CmpInst::FCMP_UEQ:
1207  default:
1208  // AL is our "false" for now. The other two need more compares.
1209  return ARMCC::AL;
1210  case CmpInst::ICMP_EQ:
1211  case CmpInst::FCMP_OEQ:
1212  return ARMCC::EQ;
1213  case CmpInst::ICMP_SGT:
1214  case CmpInst::FCMP_OGT:
1215  return ARMCC::GT;
1216  case CmpInst::ICMP_SGE:
1217  case CmpInst::FCMP_OGE:
1218  return ARMCC::GE;
1219  case CmpInst::ICMP_UGT:
1220  case CmpInst::FCMP_UGT:
1221  return ARMCC::HI;
1222  case CmpInst::FCMP_OLT:
1223  return ARMCC::MI;
1224  case CmpInst::ICMP_ULE:
1225  case CmpInst::FCMP_OLE:
1226  return ARMCC::LS;
1227  case CmpInst::FCMP_ORD:
1228  return ARMCC::VC;
1229  case CmpInst::FCMP_UNO:
1230  return ARMCC::VS;
1231  case CmpInst::FCMP_UGE:
1232  return ARMCC::PL;
1233  case CmpInst::ICMP_SLT:
1234  case CmpInst::FCMP_ULT:
1235  return ARMCC::LT;
1236  case CmpInst::ICMP_SLE:
1237  case CmpInst::FCMP_ULE:
1238  return ARMCC::LE;
1239  case CmpInst::FCMP_UNE:
1240  case CmpInst::ICMP_NE:
1241  return ARMCC::NE;
1242  case CmpInst::ICMP_UGE:
1243  return ARMCC::HS;
1244  case CmpInst::ICMP_ULT:
1245  return ARMCC::LO;
1246  }
1247 }
1248 
1249 bool ARMFastISel::SelectBranch(const Instruction *I) {
1250  const BranchInst *BI = cast<BranchInst>(I);
1251  MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
1252  MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
1253 
1254  // Simple branch support.
1255 
1256  // If we can, avoid recomputing the compare - redoing it could lead to wonky
1257  // behavior.
1258  if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
1259  if (CI->hasOneUse() && (CI->getParent() == I->getParent())) {
1260 
1261  // Get the compare predicate.
1262  // Try to take advantage of fallthrough opportunities.
1263  CmpInst::Predicate Predicate = CI->getPredicate();
1264  if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1265  std::swap(TBB, FBB);
1266  Predicate = CmpInst::getInversePredicate(Predicate);
1267  }
1268 
1269  ARMCC::CondCodes ARMPred = getComparePred(Predicate);
1270 
1271  // We may not handle every CC for now.
1272  if (ARMPred == ARMCC::AL) return false;
1273 
1274  // Emit the compare.
1275  if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1276  return false;
1277 
1278  unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1279  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc))
1280  .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR);
1281  fastEmitBranch(FBB, DbgLoc);
1282  FuncInfo.MBB->addSuccessor(TBB);
1283  return true;
1284  }
1285  } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
1286  MVT SourceVT;
1287  if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
1288  (isLoadTypeLegal(TI->getOperand(0)->getType(), SourceVT))) {
1289  unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1290  unsigned OpReg = getRegForValue(TI->getOperand(0));
1291  OpReg = constrainOperandRegClass(TII.get(TstOpc), OpReg, 0);
1292  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1293  TII.get(TstOpc))
1294  .addReg(OpReg).addImm(1));
1295 
1296  unsigned CCMode = ARMCC::NE;
1297  if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1298  std::swap(TBB, FBB);
1299  CCMode = ARMCC::EQ;
1300  }
1301 
1302  unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1303  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc))
1304  .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1305 
1306  fastEmitBranch(FBB, DbgLoc);
1307  FuncInfo.MBB->addSuccessor(TBB);
1308  return true;
1309  }
1310  } else if (const ConstantInt *CI =
1311  dyn_cast<ConstantInt>(BI->getCondition())) {
1312  uint64_t Imm = CI->getZExtValue();
1313  MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
1314  fastEmitBranch(Target, DbgLoc);
1315  return true;
1316  }
1317 
1318  unsigned CmpReg = getRegForValue(BI->getCondition());
1319  if (CmpReg == 0) return false;
1320 
1321  // We've been divorced from our compare! Our block was split, and
1322  // now our compare lives in a predecessor block. We musn't
1323  // re-compare here, as the children of the compare aren't guaranteed
1324  // live across the block boundary (we *could* check for this).
1325  // Regardless, the compare has been done in the predecessor block,
1326  // and it left a value for us in a virtual register. Ergo, we test
1327  // the one-bit value left in the virtual register.
1328  unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1329  CmpReg = constrainOperandRegClass(TII.get(TstOpc), CmpReg, 0);
1330  AddOptionalDefs(
1331  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TstOpc))
1332  .addReg(CmpReg)
1333  .addImm(1));
1334 
1335  unsigned CCMode = ARMCC::NE;
1336  if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1337  std::swap(TBB, FBB);
1338  CCMode = ARMCC::EQ;
1339  }
1340 
1341  unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1342  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc))
1343  .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1344  fastEmitBranch(FBB, DbgLoc);
1345  FuncInfo.MBB->addSuccessor(TBB);
1346  return true;
1347 }
1348 
1349 bool ARMFastISel::SelectIndirectBr(const Instruction *I) {
1350  unsigned AddrReg = getRegForValue(I->getOperand(0));
1351  if (AddrReg == 0) return false;
1352 
1353  unsigned Opc = isThumb2 ? ARM::tBRIND : ARM::BX;
1354  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1355  TII.get(Opc)).addReg(AddrReg));
1356 
1357  const IndirectBrInst *IB = cast<IndirectBrInst>(I);
1358  for (unsigned i = 0, e = IB->getNumSuccessors(); i != e; ++i)
1359  FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[IB->getSuccessor(i)]);
1360 
1361  return true;
1362 }
1363 
1364 bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
1365  bool isZExt) {
1366  Type *Ty = Src1Value->getType();
1367  EVT SrcEVT = TLI.getValueType(DL, Ty, true);
1368  if (!SrcEVT.isSimple()) return false;
1369  MVT SrcVT = SrcEVT.getSimpleVT();
1370 
1371  bool isFloat = (Ty->isFloatTy() || Ty->isDoubleTy());
1372  if (isFloat && !Subtarget->hasVFP2())
1373  return false;
1374 
1375  // Check to see if the 2nd operand is a constant that we can encode directly
1376  // in the compare.
1377  int Imm = 0;
1378  bool UseImm = false;
1379  bool isNegativeImm = false;
1380  // FIXME: At -O0 we don't have anything that canonicalizes operand order.
1381  // Thus, Src1Value may be a ConstantInt, but we're missing it.
1382  if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(Src2Value)) {
1383  if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 ||
1384  SrcVT == MVT::i1) {
1385  const APInt &CIVal = ConstInt->getValue();
1386  Imm = (isZExt) ? (int)CIVal.getZExtValue() : (int)CIVal.getSExtValue();
1387  // For INT_MIN/LONG_MIN (i.e., 0x80000000) we need to use a cmp, rather
1388  // then a cmn, because there is no way to represent 2147483648 as a
1389  // signed 32-bit int.
1390  if (Imm < 0 && Imm != (int)0x80000000) {
1391  isNegativeImm = true;
1392  Imm = -Imm;
1393  }
1394  UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1395  (ARM_AM::getSOImmVal(Imm) != -1);
1396  }
1397  } else if (const ConstantFP *ConstFP = dyn_cast<ConstantFP>(Src2Value)) {
1398  if (SrcVT == MVT::f32 || SrcVT == MVT::f64)
1399  if (ConstFP->isZero() && !ConstFP->isNegative())
1400  UseImm = true;
1401  }
1402 
1403  unsigned CmpOpc;
1404  bool isICmp = true;
1405  bool needsExt = false;
1406  switch (SrcVT.SimpleTy) {
1407  default: return false;
1408  // TODO: Verify compares.
1409  case MVT::f32:
1410  isICmp = false;
1411  CmpOpc = UseImm ? ARM::VCMPEZS : ARM::VCMPES;
1412  break;
1413  case MVT::f64:
1414  isICmp = false;
1415  CmpOpc = UseImm ? ARM::VCMPEZD : ARM::VCMPED;
1416  break;
1417  case MVT::i1:
1418  case MVT::i8:
1419  case MVT::i16:
1420  needsExt = true;
1421  // Intentional fall-through.
1422  case MVT::i32:
1423  if (isThumb2) {
1424  if (!UseImm)
1425  CmpOpc = ARM::t2CMPrr;
1426  else
1427  CmpOpc = isNegativeImm ? ARM::t2CMNri : ARM::t2CMPri;
1428  } else {
1429  if (!UseImm)
1430  CmpOpc = ARM::CMPrr;
1431  else
1432  CmpOpc = isNegativeImm ? ARM::CMNri : ARM::CMPri;
1433  }
1434  break;
1435  }
1436 
1437  unsigned SrcReg1 = getRegForValue(Src1Value);
1438  if (SrcReg1 == 0) return false;
1439 
1440  unsigned SrcReg2 = 0;
1441  if (!UseImm) {
1442  SrcReg2 = getRegForValue(Src2Value);
1443  if (SrcReg2 == 0) return false;
1444  }
1445 
1446  // We have i1, i8, or i16, we need to either zero extend or sign extend.
1447  if (needsExt) {
1448  SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt);
1449  if (SrcReg1 == 0) return false;
1450  if (!UseImm) {
1451  SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt);
1452  if (SrcReg2 == 0) return false;
1453  }
1454  }
1455 
1456  const MCInstrDesc &II = TII.get(CmpOpc);
1457  SrcReg1 = constrainOperandRegClass(II, SrcReg1, 0);
1458  if (!UseImm) {
1459  SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1);
1460  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1461  .addReg(SrcReg1).addReg(SrcReg2));
1462  } else {
1463  MachineInstrBuilder MIB;
1464  MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1465  .addReg(SrcReg1);
1466 
1467  // Only add immediate for icmp as the immediate for fcmp is an implicit 0.0.
1468  if (isICmp)
1469  MIB.addImm(Imm);
1470  AddOptionalDefs(MIB);
1471  }
1472 
1473  // For floating point we need to move the result to a comparison register
1474  // that we can then use for branches.
1475  if (Ty->isFloatTy() || Ty->isDoubleTy())
1476  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1477  TII.get(ARM::FMSTAT)));
1478  return true;
1479 }
1480 
1481 bool ARMFastISel::SelectCmp(const Instruction *I) {
1482  const CmpInst *CI = cast<CmpInst>(I);
1483 
1484  // Get the compare predicate.
1485  ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
1486 
1487  // We may not handle every CC for now.
1488  if (ARMPred == ARMCC::AL) return false;
1489 
1490  // Emit the compare.
1491  if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1492  return false;
1493 
1494  // Now set a register based on the comparison. Explicitly set the predicates
1495  // here.
1496  unsigned MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1497  const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass
1498  : &ARM::GPRRegClass;
1499  unsigned DestReg = createResultReg(RC);
1500  Constant *Zero = ConstantInt::get(Type::getInt32Ty(*Context), 0);
1501  unsigned ZeroReg = fastMaterializeConstant(Zero);
1502  // ARMEmitCmp emits a FMSTAT when necessary, so it's always safe to use CPSR.
1503  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc), DestReg)
1504  .addReg(ZeroReg).addImm(1)
1505  .addImm(ARMPred).addReg(ARM::CPSR);
1506 
1507  updateValueMap(I, DestReg);
1508  return true;
1509 }
1510 
1511 bool ARMFastISel::SelectFPExt(const Instruction *I) {
1512  // Make sure we have VFP and that we're extending float to double.
1513  if (!Subtarget->hasVFP2()) return false;
1514 
1515  Value *V = I->getOperand(0);
1516  if (!I->getType()->isDoubleTy() ||
1517  !V->getType()->isFloatTy()) return false;
1518 
1519  unsigned Op = getRegForValue(V);
1520  if (Op == 0) return false;
1521 
1522  unsigned Result = createResultReg(&ARM::DPRRegClass);
1523  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1524  TII.get(ARM::VCVTDS), Result)
1525  .addReg(Op));
1526  updateValueMap(I, Result);
1527  return true;
1528 }
1529 
1530 bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
1531  // Make sure we have VFP and that we're truncating double to float.
1532  if (!Subtarget->hasVFP2()) return false;
1533 
1534  Value *V = I->getOperand(0);
1535  if (!(I->getType()->isFloatTy() &&
1536  V->getType()->isDoubleTy())) return false;
1537 
1538  unsigned Op = getRegForValue(V);
1539  if (Op == 0) return false;
1540 
1541  unsigned Result = createResultReg(&ARM::SPRRegClass);
1542  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1543  TII.get(ARM::VCVTSD), Result)
1544  .addReg(Op));
1545  updateValueMap(I, Result);
1546  return true;
1547 }
1548 
1549 bool ARMFastISel::SelectIToFP(const Instruction *I, bool isSigned) {
1550  // Make sure we have VFP.
1551  if (!Subtarget->hasVFP2()) return false;
1552 
1553  MVT DstVT;
1554  Type *Ty = I->getType();
1555  if (!isTypeLegal(Ty, DstVT))
1556  return false;
1557 
1558  Value *Src = I->getOperand(0);
1559  EVT SrcEVT = TLI.getValueType(DL, Src->getType(), true);
1560  if (!SrcEVT.isSimple())
1561  return false;
1562  MVT SrcVT = SrcEVT.getSimpleVT();
1563  if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1564  return false;
1565 
1566  unsigned SrcReg = getRegForValue(Src);
1567  if (SrcReg == 0) return false;
1568 
1569  // Handle sign-extension.
1570  if (SrcVT == MVT::i16 || SrcVT == MVT::i8) {
1571  SrcReg = ARMEmitIntExt(SrcVT, SrcReg, MVT::i32,
1572  /*isZExt*/!isSigned);
1573  if (SrcReg == 0) return false;
1574  }
1575 
1576  // The conversion routine works on fp-reg to fp-reg and the operand above
1577  // was an integer, move it to the fp registers if possible.
1578  unsigned FP = ARMMoveToFPReg(MVT::f32, SrcReg);
1579  if (FP == 0) return false;
1580 
1581  unsigned Opc;
1582  if (Ty->isFloatTy()) Opc = isSigned ? ARM::VSITOS : ARM::VUITOS;
1583  else if (Ty->isDoubleTy()) Opc = isSigned ? ARM::VSITOD : ARM::VUITOD;
1584  else return false;
1585 
1586  unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
1587  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1588  TII.get(Opc), ResultReg).addReg(FP));
1589  updateValueMap(I, ResultReg);
1590  return true;
1591 }
1592 
1593 bool ARMFastISel::SelectFPToI(const Instruction *I, bool isSigned) {
1594  // Make sure we have VFP.
1595  if (!Subtarget->hasVFP2()) return false;
1596 
1597  MVT DstVT;
1598  Type *RetTy = I->getType();
1599  if (!isTypeLegal(RetTy, DstVT))
1600  return false;
1601 
1602  unsigned Op = getRegForValue(I->getOperand(0));
1603  if (Op == 0) return false;
1604 
1605  unsigned Opc;
1606  Type *OpTy = I->getOperand(0)->getType();
1607  if (OpTy->isFloatTy()) Opc = isSigned ? ARM::VTOSIZS : ARM::VTOUIZS;
1608  else if (OpTy->isDoubleTy()) Opc = isSigned ? ARM::VTOSIZD : ARM::VTOUIZD;
1609  else return false;
1610 
1611  // f64->s32/u32 or f32->s32/u32 both need an intermediate f32 reg.
1612  unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1613  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1614  TII.get(Opc), ResultReg).addReg(Op));
1615 
1616  // This result needs to be in an integer register, but the conversion only
1617  // takes place in fp-regs.
1618  unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
1619  if (IntReg == 0) return false;
1620 
1621  updateValueMap(I, IntReg);
1622  return true;
1623 }
1624 
1625 bool ARMFastISel::SelectSelect(const Instruction *I) {
1626  MVT VT;
1627  if (!isTypeLegal(I->getType(), VT))
1628  return false;
1629 
1630  // Things need to be register sized for register moves.
1631  if (VT != MVT::i32) return false;
1632 
1633  unsigned CondReg = getRegForValue(I->getOperand(0));
1634  if (CondReg == 0) return false;
1635  unsigned Op1Reg = getRegForValue(I->getOperand(1));
1636  if (Op1Reg == 0) return false;
1637 
1638  // Check to see if we can use an immediate in the conditional move.
1639  int Imm = 0;
1640  bool UseImm = false;
1641  bool isNegativeImm = false;
1642  if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(I->getOperand(2))) {
1643  assert (VT == MVT::i32 && "Expecting an i32.");
1644  Imm = (int)ConstInt->getValue().getZExtValue();
1645  if (Imm < 0) {
1646  isNegativeImm = true;
1647  Imm = ~Imm;
1648  }
1649  UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1650  (ARM_AM::getSOImmVal(Imm) != -1);
1651  }
1652 
1653  unsigned Op2Reg = 0;
1654  if (!UseImm) {
1655  Op2Reg = getRegForValue(I->getOperand(2));
1656  if (Op2Reg == 0) return false;
1657  }
1658 
1659  unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1660  CondReg = constrainOperandRegClass(TII.get(TstOpc), CondReg, 0);
1661  AddOptionalDefs(
1662  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TstOpc))
1663  .addReg(CondReg)
1664  .addImm(1));
1665 
1666  unsigned MovCCOpc;
1667  const TargetRegisterClass *RC;
1668  if (!UseImm) {
1669  RC = isThumb2 ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
1670  MovCCOpc = isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr;
1671  } else {
1672  RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass;
1673  if (!isNegativeImm)
1674  MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1675  else
1676  MovCCOpc = isThumb2 ? ARM::t2MVNCCi : ARM::MVNCCi;
1677  }
1678  unsigned ResultReg = createResultReg(RC);
1679  if (!UseImm) {
1680  Op2Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op2Reg, 1);
1681  Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 2);
1682  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc),
1683  ResultReg)
1684  .addReg(Op2Reg)
1685  .addReg(Op1Reg)
1686  .addImm(ARMCC::NE)
1687  .addReg(ARM::CPSR);
1688  } else {
1689  Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 1);
1690  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc),
1691  ResultReg)
1692  .addReg(Op1Reg)
1693  .addImm(Imm)
1694  .addImm(ARMCC::EQ)
1695  .addReg(ARM::CPSR);
1696  }
1697  updateValueMap(I, ResultReg);
1698  return true;
1699 }
1700 
1701 bool ARMFastISel::SelectDiv(const Instruction *I, bool isSigned) {
1702  MVT VT;
1703  Type *Ty = I->getType();
1704  if (!isTypeLegal(Ty, VT))
1705  return false;
1706 
1707  // If we have integer div support we should have selected this automagically.
1708  // In case we have a real miss go ahead and return false and we'll pick
1709  // it up later.
1710  if (Subtarget->hasDivide()) return false;
1711 
1712  // Otherwise emit a libcall.
1714  if (VT == MVT::i8)
1715  LC = isSigned ? RTLIB::SDIV_I8 : RTLIB::UDIV_I8;
1716  else if (VT == MVT::i16)
1717  LC = isSigned ? RTLIB::SDIV_I16 : RTLIB::UDIV_I16;
1718  else if (VT == MVT::i32)
1719  LC = isSigned ? RTLIB::SDIV_I32 : RTLIB::UDIV_I32;
1720  else if (VT == MVT::i64)
1721  LC = isSigned ? RTLIB::SDIV_I64 : RTLIB::UDIV_I64;
1722  else if (VT == MVT::i128)
1723  LC = isSigned ? RTLIB::SDIV_I128 : RTLIB::UDIV_I128;
1724  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1725 
1726  return ARMEmitLibcall(I, LC);
1727 }
1728 
1729 bool ARMFastISel::SelectRem(const Instruction *I, bool isSigned) {
1730  MVT VT;
1731  Type *Ty = I->getType();
1732  if (!isTypeLegal(Ty, VT))
1733  return false;
1734 
1736  if (VT == MVT::i8)
1737  LC = isSigned ? RTLIB::SREM_I8 : RTLIB::UREM_I8;
1738  else if (VT == MVT::i16)
1739  LC = isSigned ? RTLIB::SREM_I16 : RTLIB::UREM_I16;
1740  else if (VT == MVT::i32)
1741  LC = isSigned ? RTLIB::SREM_I32 : RTLIB::UREM_I32;
1742  else if (VT == MVT::i64)
1743  LC = isSigned ? RTLIB::SREM_I64 : RTLIB::UREM_I64;
1744  else if (VT == MVT::i128)
1745  LC = isSigned ? RTLIB::SREM_I128 : RTLIB::UREM_I128;
1746  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1747 
1748  return ARMEmitLibcall(I, LC);
1749 }
1750 
1751 bool ARMFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) {
1752  EVT DestVT = TLI.getValueType(DL, I->getType(), true);
1753 
1754  // We can get here in the case when we have a binary operation on a non-legal
1755  // type and the target independent selector doesn't know how to handle it.
1756  if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1757  return false;
1758 
1759  unsigned Opc;
1760  switch (ISDOpcode) {
1761  default: return false;
1762  case ISD::ADD:
1763  Opc = isThumb2 ? ARM::t2ADDrr : ARM::ADDrr;
1764  break;
1765  case ISD::OR:
1766  Opc = isThumb2 ? ARM::t2ORRrr : ARM::ORRrr;
1767  break;
1768  case ISD::SUB:
1769  Opc = isThumb2 ? ARM::t2SUBrr : ARM::SUBrr;
1770  break;
1771  }
1772 
1773  unsigned SrcReg1 = getRegForValue(I->getOperand(0));
1774  if (SrcReg1 == 0) return false;
1775 
1776  // TODO: Often the 2nd operand is an immediate, which can be encoded directly
1777  // in the instruction, rather then materializing the value in a register.
1778  unsigned SrcReg2 = getRegForValue(I->getOperand(1));
1779  if (SrcReg2 == 0) return false;
1780 
1781  unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass);
1782  SrcReg1 = constrainOperandRegClass(TII.get(Opc), SrcReg1, 1);
1783  SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2);
1784  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1785  TII.get(Opc), ResultReg)
1786  .addReg(SrcReg1).addReg(SrcReg2));
1787  updateValueMap(I, ResultReg);
1788  return true;
1789 }
1790 
1791 bool ARMFastISel::SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode) {
1792  EVT FPVT = TLI.getValueType(DL, I->getType(), true);
1793  if (!FPVT.isSimple()) return false;
1794  MVT VT = FPVT.getSimpleVT();
1795 
1796  // FIXME: Support vector types where possible.
1797  if (VT.isVector())
1798  return false;
1799 
1800  // We can get here in the case when we want to use NEON for our fp
1801  // operations, but can't figure out how to. Just use the vfp instructions
1802  // if we have them.
1803  // FIXME: It'd be nice to use NEON instructions.
1804  Type *Ty = I->getType();
1805  bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
1806  if (isFloat && !Subtarget->hasVFP2())
1807  return false;
1808 
1809  unsigned Opc;
1810  bool is64bit = VT == MVT::f64 || VT == MVT::i64;
1811  switch (ISDOpcode) {
1812  default: return false;
1813  case ISD::FADD:
1814  Opc = is64bit ? ARM::VADDD : ARM::VADDS;
1815  break;
1816  case ISD::FSUB:
1817  Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
1818  break;
1819  case ISD::FMUL:
1820  Opc = is64bit ? ARM::VMULD : ARM::VMULS;
1821  break;
1822  }
1823  unsigned Op1 = getRegForValue(I->getOperand(0));
1824  if (Op1 == 0) return false;
1825 
1826  unsigned Op2 = getRegForValue(I->getOperand(1));
1827  if (Op2 == 0) return false;
1828 
1829  unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy));
1830  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1831  TII.get(Opc), ResultReg)
1832  .addReg(Op1).addReg(Op2));
1833  updateValueMap(I, ResultReg);
1834  return true;
1835 }
1836 
1837 // Call Handling Code
1838 
1839 // This is largely taken directly from CCAssignFnForNode
1840 // TODO: We may not support all of this.
1841 CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC,
1842  bool Return,
1843  bool isVarArg) {
1844  switch (CC) {
1845  default:
1846  llvm_unreachable("Unsupported calling convention");
1847  case CallingConv::Fast:
1848  if (Subtarget->hasVFP2() && !isVarArg) {
1849  if (!Subtarget->isAAPCS_ABI())
1850  return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1851  // For AAPCS ABI targets, just use VFP variant of the calling convention.
1852  return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1853  }
1854  // Fallthrough
1855  case CallingConv::C:
1856  // Use target triple & subtarget features to do actual dispatch.
1857  if (Subtarget->isAAPCS_ABI()) {
1858  if (Subtarget->hasVFP2() &&
1859  TM.Options.FloatABIType == FloatABI::Hard && !isVarArg)
1860  return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1861  else
1862  return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1863  } else
1864  return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1866  if (!isVarArg)
1867  return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1868  // Fall through to soft float variant, variadic functions don't
1869  // use hard floating point ABI.
1871  return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1872  case CallingConv::ARM_APCS:
1873  return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1874  case CallingConv::GHC:
1875  if (Return)
1876  llvm_unreachable("Can't return in GHC call convention");
1877  else
1878  return CC_ARM_APCS_GHC;
1879  }
1880 }
1881 
1882 bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
1883  SmallVectorImpl<unsigned> &ArgRegs,
1884  SmallVectorImpl<MVT> &ArgVTs,
1886  SmallVectorImpl<unsigned> &RegArgs,
1887  CallingConv::ID CC,
1888  unsigned &NumBytes,
1889  bool isVarArg) {
1891  CCState CCInfo(CC, isVarArg, *FuncInfo.MF, ArgLocs, *Context);
1892  CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags,
1893  CCAssignFnForCall(CC, false, isVarArg));
1894 
1895  // Check that we can handle all of the arguments. If we can't, then bail out
1896  // now before we add code to the MBB.
1897  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1898  CCValAssign &VA = ArgLocs[i];
1899  MVT ArgVT = ArgVTs[VA.getValNo()];
1900 
1901  // We don't handle NEON/vector parameters yet.
1902  if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64)
1903  return false;
1904 
1905  // Now copy/store arg to correct locations.
1906  if (VA.isRegLoc() && !VA.needsCustom()) {
1907  continue;
1908  } else if (VA.needsCustom()) {
1909  // TODO: We need custom lowering for vector (v2f64) args.
1910  if (VA.getLocVT() != MVT::f64 ||
1911  // TODO: Only handle register args for now.
1912  !VA.isRegLoc() || !ArgLocs[++i].isRegLoc())
1913  return false;
1914  } else {
1915  switch (ArgVT.SimpleTy) {
1916  default:
1917  return false;
1918  case MVT::i1:
1919  case MVT::i8:
1920  case MVT::i16:
1921  case MVT::i32:
1922  break;
1923  case MVT::f32:
1924  if (!Subtarget->hasVFP2())
1925  return false;
1926  break;
1927  case MVT::f64:
1928  if (!Subtarget->hasVFP2())
1929  return false;
1930  break;
1931  }
1932  }
1933  }
1934 
1935  // At the point, we are able to handle the call's arguments in fast isel.
1936 
1937  // Get a count of how many bytes are to be pushed on the stack.
1938  NumBytes = CCInfo.getNextStackOffset();
1939 
1940  // Issue CALLSEQ_START
1941  unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
1942  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1943  TII.get(AdjStackDown))
1944  .addImm(NumBytes));
1945 
1946  // Process the args.
1947  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1948  CCValAssign &VA = ArgLocs[i];
1949  const Value *ArgVal = Args[VA.getValNo()];
1950  unsigned Arg = ArgRegs[VA.getValNo()];
1951  MVT ArgVT = ArgVTs[VA.getValNo()];
1952 
1953  assert((!ArgVT.isVector() && ArgVT.getSizeInBits() <= 64) &&
1954  "We don't handle NEON/vector parameters yet.");
1955 
1956  // Handle arg promotion, etc.
1957  switch (VA.getLocInfo()) {
1958  case CCValAssign::Full: break;
1959  case CCValAssign::SExt: {
1960  MVT DestVT = VA.getLocVT();
1961  Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/false);
1962  assert (Arg != 0 && "Failed to emit a sext");
1963  ArgVT = DestVT;
1964  break;
1965  }
1966  case CCValAssign::AExt:
1967  // Intentional fall-through. Handle AExt and ZExt.
1968  case CCValAssign::ZExt: {
1969  MVT DestVT = VA.getLocVT();
1970  Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/true);
1971  assert (Arg != 0 && "Failed to emit a zext");
1972  ArgVT = DestVT;
1973  break;
1974  }
1975  case CCValAssign::BCvt: {
1976  unsigned BC = fastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg,
1977  /*TODO: Kill=*/false);
1978  assert(BC != 0 && "Failed to emit a bitcast!");
1979  Arg = BC;
1980  ArgVT = VA.getLocVT();
1981  break;
1982  }
1983  default: llvm_unreachable("Unknown arg promotion!");
1984  }
1985 
1986  // Now copy/store arg to correct locations.
1987  if (VA.isRegLoc() && !VA.needsCustom()) {
1988  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1989  TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(Arg);
1990  RegArgs.push_back(VA.getLocReg());
1991  } else if (VA.needsCustom()) {
1992  // TODO: We need custom lowering for vector (v2f64) args.
1993  assert(VA.getLocVT() == MVT::f64 &&
1994  "Custom lowering for v2f64 args not available");
1995 
1996  CCValAssign &NextVA = ArgLocs[++i];
1997 
1998  assert(VA.isRegLoc() && NextVA.isRegLoc() &&
1999  "We only handle register args!");
2000 
2001  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2002  TII.get(ARM::VMOVRRD), VA.getLocReg())
2003  .addReg(NextVA.getLocReg(), RegState::Define)
2004  .addReg(Arg));
2005  RegArgs.push_back(VA.getLocReg());
2006  RegArgs.push_back(NextVA.getLocReg());
2007  } else {
2008  assert(VA.isMemLoc());
2009  // Need to store on the stack.
2010 
2011  // Don't emit stores for undef values.
2012  if (isa<UndefValue>(ArgVal))
2013  continue;
2014 
2015  Address Addr;
2016  Addr.BaseType = Address::RegBase;
2017  Addr.Base.Reg = ARM::SP;
2018  Addr.Offset = VA.getLocMemOffset();
2019 
2020  bool EmitRet = ARMEmitStore(ArgVT, Arg, Addr); (void)EmitRet;
2021  assert(EmitRet && "Could not emit a store for argument!");
2022  }
2023  }
2024 
2025  return true;
2026 }
2027 
2028 bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
2029  const Instruction *I, CallingConv::ID CC,
2030  unsigned &NumBytes, bool isVarArg) {
2031  // Issue CALLSEQ_END
2032  unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
2033  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2034  TII.get(AdjStackUp))
2035  .addImm(NumBytes).addImm(0));
2036 
2037  // Now the return value.
2038  if (RetVT != MVT::isVoid) {
2040  CCState CCInfo(CC, isVarArg, *FuncInfo.MF, RVLocs, *Context);
2041  CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2042 
2043  // Copy all of the result registers out of their specified physreg.
2044  if (RVLocs.size() == 2 && RetVT == MVT::f64) {
2045  // For this move we copy into two registers and then move into the
2046  // double fp reg we want.
2047  MVT DestVT = RVLocs[0].getValVT();
2048  const TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT);
2049  unsigned ResultReg = createResultReg(DstRC);
2050  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2051  TII.get(ARM::VMOVDRR), ResultReg)
2052  .addReg(RVLocs[0].getLocReg())
2053  .addReg(RVLocs[1].getLocReg()));
2054 
2055  UsedRegs.push_back(RVLocs[0].getLocReg());
2056  UsedRegs.push_back(RVLocs[1].getLocReg());
2057 
2058  // Finally update the result.
2059  updateValueMap(I, ResultReg);
2060  } else {
2061  assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
2062  MVT CopyVT = RVLocs[0].getValVT();
2063 
2064  // Special handling for extended integers.
2065  if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
2066  CopyVT = MVT::i32;
2067 
2068  const TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
2069 
2070  unsigned ResultReg = createResultReg(DstRC);
2071  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2072  TII.get(TargetOpcode::COPY),
2073  ResultReg).addReg(RVLocs[0].getLocReg());
2074  UsedRegs.push_back(RVLocs[0].getLocReg());
2075 
2076  // Finally update the result.
2077  updateValueMap(I, ResultReg);
2078  }
2079  }
2080 
2081  return true;
2082 }
2083 
2084 bool ARMFastISel::SelectRet(const Instruction *I) {
2085  const ReturnInst *Ret = cast<ReturnInst>(I);
2086  const Function &F = *I->getParent()->getParent();
2087 
2088  if (!FuncInfo.CanLowerReturn)
2089  return false;
2090 
2091  // Build a list of return value registers.
2092  SmallVector<unsigned, 4> RetRegs;
2093 
2094  CallingConv::ID CC = F.getCallingConv();
2095  if (Ret->getNumOperands() > 0) {
2097  GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI, DL);
2098 
2099  // Analyze operands of the call, assigning locations to each operand.
2101  CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs, I->getContext());
2102  CCInfo.AnalyzeReturn(Outs, CCAssignFnForCall(CC, true /* is Ret */,
2103  F.isVarArg()));
2104 
2105  const Value *RV = Ret->getOperand(0);
2106  unsigned Reg = getRegForValue(RV);
2107  if (Reg == 0)
2108  return false;
2109 
2110  // Only handle a single return value for now.
2111  if (ValLocs.size() != 1)
2112  return false;
2113 
2114  CCValAssign &VA = ValLocs[0];
2115 
2116  // Don't bother handling odd stuff for now.
2117  if (VA.getLocInfo() != CCValAssign::Full)
2118  return false;
2119  // Only handle register returns for now.
2120  if (!VA.isRegLoc())
2121  return false;
2122 
2123  unsigned SrcReg = Reg + VA.getValNo();
2124  EVT RVEVT = TLI.getValueType(DL, RV->getType());
2125  if (!RVEVT.isSimple()) return false;
2126  MVT RVVT = RVEVT.getSimpleVT();
2127  MVT DestVT = VA.getValVT();
2128  // Special handling for extended integers.
2129  if (RVVT != DestVT) {
2130  if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
2131  return false;
2132 
2133  assert(DestVT == MVT::i32 && "ARM should always ext to i32");
2134 
2135  // Perform extension if flagged as either zext or sext. Otherwise, do
2136  // nothing.
2137  if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
2138  SrcReg = ARMEmitIntExt(RVVT, SrcReg, DestVT, Outs[0].Flags.isZExt());
2139  if (SrcReg == 0) return false;
2140  }
2141  }
2142 
2143  // Make the copy.
2144  unsigned DstReg = VA.getLocReg();
2145  const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
2146  // Avoid a cross-class copy. This is very unlikely.
2147  if (!SrcRC->contains(DstReg))
2148  return false;
2149  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2150  TII.get(TargetOpcode::COPY), DstReg).addReg(SrcReg);
2151 
2152  // Add register to return instruction.
2153  RetRegs.push_back(VA.getLocReg());
2154  }
2155 
2156  unsigned RetOpc = isThumb2 ? ARM::tBX_RET : ARM::BX_RET;
2157  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2158  TII.get(RetOpc));
2159  AddOptionalDefs(MIB);
2160  for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
2161  MIB.addReg(RetRegs[i], RegState::Implicit);
2162  return true;
2163 }
2164 
2165 unsigned ARMFastISel::ARMSelectCallOp(bool UseReg) {
2166  if (UseReg)
2167  return isThumb2 ? ARM::tBLXr : ARM::BLX;
2168  else
2169  return isThumb2 ? ARM::tBL : ARM::BL;
2170 }
2171 
2172 unsigned ARMFastISel::getLibcallReg(const Twine &Name) {
2173  // Manually compute the global's type to avoid building it when unnecessary.
2174  Type *GVTy = Type::getInt32PtrTy(*Context, /*AS=*/0);
2175  EVT LCREVT = TLI.getValueType(DL, GVTy);
2176  if (!LCREVT.isSimple()) return 0;
2177 
2178  GlobalValue *GV = new GlobalVariable(M, Type::getInt32Ty(*Context), false,
2180  Name);
2181  assert(GV->getType() == GVTy && "We miscomputed the type for the global!");
2182  return ARMMaterializeGV(GV, LCREVT.getSimpleVT());
2183 }
2184 
2185 // A quick function that will emit a call for a named libcall in F with the
2186 // vector of passed arguments for the Instruction in I. We can assume that we
2187 // can emit a call for any libcall we can produce. This is an abridged version
2188 // of the full call infrastructure since we won't need to worry about things
2189 // like computed function pointers or strange arguments at call sites.
2190 // TODO: Try to unify this and the normal call bits for ARM, then try to unify
2191 // with X86.
2192 bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
2193  CallingConv::ID CC = TLI.getLibcallCallingConv(Call);
2194 
2195  // Handle *simple* calls for now.
2196  Type *RetTy = I->getType();
2197  MVT RetVT;
2198  if (RetTy->isVoidTy())
2199  RetVT = MVT::isVoid;
2200  else if (!isTypeLegal(RetTy, RetVT))
2201  return false;
2202 
2203  // Can't handle non-double multi-reg retvals.
2204  if (RetVT != MVT::isVoid && RetVT != MVT::i32) {
2206  CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
2207  CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, false));
2208  if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2209  return false;
2210  }
2211 
2212  // Set up the argument vectors.
2214  SmallVector<unsigned, 8> ArgRegs;
2215  SmallVector<MVT, 8> ArgVTs;
2217  Args.reserve(I->getNumOperands());
2218  ArgRegs.reserve(I->getNumOperands());
2219  ArgVTs.reserve(I->getNumOperands());
2220  ArgFlags.reserve(I->getNumOperands());
2221  for (unsigned i = 0; i < I->getNumOperands(); ++i) {
2222  Value *Op = I->getOperand(i);
2223  unsigned Arg = getRegForValue(Op);
2224  if (Arg == 0) return false;
2225 
2226  Type *ArgTy = Op->getType();
2227  MVT ArgVT;
2228  if (!isTypeLegal(ArgTy, ArgVT)) return false;
2229 
2231  unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
2232  Flags.setOrigAlign(OriginalAlignment);
2233 
2234  Args.push_back(Op);
2235  ArgRegs.push_back(Arg);
2236  ArgVTs.push_back(ArgVT);
2237  ArgFlags.push_back(Flags);
2238  }
2239 
2240  // Handle the arguments now that we've gotten them.
2241  SmallVector<unsigned, 4> RegArgs;
2242  unsigned NumBytes;
2243  if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
2244  RegArgs, CC, NumBytes, false))
2245  return false;
2246 
2247  unsigned CalleeReg = 0;
2248  if (Subtarget->genLongCalls()) {
2249  CalleeReg = getLibcallReg(TLI.getLibcallName(Call));
2250  if (CalleeReg == 0) return false;
2251  }
2252 
2253  // Issue the call.
2254  unsigned CallOpc = ARMSelectCallOp(Subtarget->genLongCalls());
2255  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2256  DbgLoc, TII.get(CallOpc));
2257  // BL / BLX don't take a predicate, but tBL / tBLX do.
2258  if (isThumb2)
2259  AddDefaultPred(MIB);
2260  if (Subtarget->genLongCalls())
2261  MIB.addReg(CalleeReg);
2262  else
2263  MIB.addExternalSymbol(TLI.getLibcallName(Call));
2264 
2265  // Add implicit physical register uses to the call.
2266  for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
2267  MIB.addReg(RegArgs[i], RegState::Implicit);
2268 
2269  // Add a register mask with the call-preserved registers.
2270  // Proper defs for return values will be added by setPhysRegsDeadExcept().
2271  MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
2272 
2273  // Finish off the call including any return values.
2274  SmallVector<unsigned, 4> UsedRegs;
2275  if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, false)) return false;
2276 
2277  // Set all unused physreg defs as dead.
2278  static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2279 
2280  return true;
2281 }
2282 
2283 bool ARMFastISel::SelectCall(const Instruction *I,
2284  const char *IntrMemName = nullptr) {
2285  const CallInst *CI = cast<CallInst>(I);
2286  const Value *Callee = CI->getCalledValue();
2287 
2288  // Can't handle inline asm.
2289  if (isa<InlineAsm>(Callee)) return false;
2290 
2291  // Allow SelectionDAG isel to handle tail calls.
2292  if (CI->isTailCall()) return false;
2293 
2294  // Check the calling convention.
2295  ImmutableCallSite CS(CI);
2296  CallingConv::ID CC = CS.getCallingConv();
2297 
2298  // TODO: Avoid some calling conventions?
2299 
2300  PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
2301  FunctionType *FTy = cast<FunctionType>(PT->getElementType());
2302  bool isVarArg = FTy->isVarArg();
2303 
2304  // Handle *simple* calls for now.
2305  Type *RetTy = I->getType();
2306  MVT RetVT;
2307  if (RetTy->isVoidTy())
2308  RetVT = MVT::isVoid;
2309  else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 &&
2310  RetVT != MVT::i8 && RetVT != MVT::i1)
2311  return false;
2312 
2313  // Can't handle non-double multi-reg retvals.
2314  if (RetVT != MVT::isVoid && RetVT != MVT::i1 && RetVT != MVT::i8 &&
2315  RetVT != MVT::i16 && RetVT != MVT::i32) {
2317  CCState CCInfo(CC, isVarArg, *FuncInfo.MF, RVLocs, *Context);
2318  CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2319  if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2320  return false;
2321  }
2322 
2323  // Set up the argument vectors.
2325  SmallVector<unsigned, 8> ArgRegs;
2326  SmallVector<MVT, 8> ArgVTs;
2328  unsigned arg_size = CS.arg_size();
2329  Args.reserve(arg_size);
2330  ArgRegs.reserve(arg_size);
2331  ArgVTs.reserve(arg_size);
2332  ArgFlags.reserve(arg_size);
2333  for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
2334  i != e; ++i) {
2335  // If we're lowering a memory intrinsic instead of a regular call, skip the
2336  // last two arguments, which shouldn't be passed to the underlying function.
2337  if (IntrMemName && e-i <= 2)
2338  break;
2339 
2341  unsigned AttrInd = i - CS.arg_begin() + 1;
2342  if (CS.paramHasAttr(AttrInd, Attribute::SExt))
2343  Flags.setSExt();
2344  if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
2345  Flags.setZExt();
2346 
2347  // FIXME: Only handle *easy* calls for now.
2348  if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
2349  CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
2350  CS.paramHasAttr(AttrInd, Attribute::Nest) ||
2351  CS.paramHasAttr(AttrInd, Attribute::ByVal))
2352  return false;
2353 
2354  Type *ArgTy = (*i)->getType();
2355  MVT ArgVT;
2356  if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8 &&
2357  ArgVT != MVT::i1)
2358  return false;
2359 
2360  unsigned Arg = getRegForValue(*i);
2361  if (Arg == 0)
2362  return false;
2363 
2364  unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
2365  Flags.setOrigAlign(OriginalAlignment);
2366 
2367  Args.push_back(*i);
2368  ArgRegs.push_back(Arg);
2369  ArgVTs.push_back(ArgVT);
2370  ArgFlags.push_back(Flags);
2371  }
2372 
2373  // Handle the arguments now that we've gotten them.
2374  SmallVector<unsigned, 4> RegArgs;
2375  unsigned NumBytes;
2376  if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
2377  RegArgs, CC, NumBytes, isVarArg))
2378  return false;
2379 
2380  bool UseReg = false;
2381  const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
2382  if (!GV || Subtarget->genLongCalls()) UseReg = true;
2383 
2384  unsigned CalleeReg = 0;
2385  if (UseReg) {
2386  if (IntrMemName)
2387  CalleeReg = getLibcallReg(IntrMemName);
2388  else
2389  CalleeReg = getRegForValue(Callee);
2390 
2391  if (CalleeReg == 0) return false;
2392  }
2393 
2394  // Issue the call.
2395  unsigned CallOpc = ARMSelectCallOp(UseReg);
2396  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2397  DbgLoc, TII.get(CallOpc));
2398 
2399  unsigned char OpFlags = 0;
2400 
2401  // Add MO_PLT for global address or external symbol in the PIC relocation
2402  // model.
2403  if (Subtarget->isTargetELF() && TM.getRelocationModel() == Reloc::PIC_)
2404  OpFlags = ARMII::MO_PLT;
2405 
2406  // ARM calls don't take a predicate, but tBL / tBLX do.
2407  if(isThumb2)
2408  AddDefaultPred(MIB);
2409  if (UseReg)
2410  MIB.addReg(CalleeReg);
2411  else if (!IntrMemName)
2412  MIB.addGlobalAddress(GV, 0, OpFlags);
2413  else
2414  MIB.addExternalSymbol(IntrMemName, OpFlags);
2415 
2416  // Add implicit physical register uses to the call.
2417  for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
2418  MIB.addReg(RegArgs[i], RegState::Implicit);
2419 
2420  // Add a register mask with the call-preserved registers.
2421  // Proper defs for return values will be added by setPhysRegsDeadExcept().
2422  MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
2423 
2424  // Finish off the call including any return values.
2425  SmallVector<unsigned, 4> UsedRegs;
2426  if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, isVarArg))
2427  return false;
2428 
2429  // Set all unused physreg defs as dead.
2430  static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2431 
2432  return true;
2433 }
2434 
2435 bool ARMFastISel::ARMIsMemCpySmall(uint64_t Len) {
2436  return Len <= 16;
2437 }
2438 
2439 bool ARMFastISel::ARMTryEmitSmallMemCpy(Address Dest, Address Src,
2440  uint64_t Len, unsigned Alignment) {
2441  // Make sure we don't bloat code by inlining very large memcpy's.
2442  if (!ARMIsMemCpySmall(Len))
2443  return false;
2444 
2445  while (Len) {
2446  MVT VT;
2447  if (!Alignment || Alignment >= 4) {
2448  if (Len >= 4)
2449  VT = MVT::i32;
2450  else if (Len >= 2)
2451  VT = MVT::i16;
2452  else {
2453  assert (Len == 1 && "Expected a length of 1!");
2454  VT = MVT::i8;
2455  }
2456  } else {
2457  // Bound based on alignment.
2458  if (Len >= 2 && Alignment == 2)
2459  VT = MVT::i16;
2460  else {
2461  VT = MVT::i8;
2462  }
2463  }
2464 
2465  bool RV;
2466  unsigned ResultReg;
2467  RV = ARMEmitLoad(VT, ResultReg, Src);
2468  assert (RV == true && "Should be able to handle this load.");
2469  RV = ARMEmitStore(VT, ResultReg, Dest);
2470  assert (RV == true && "Should be able to handle this store.");
2471  (void)RV;
2472 
2473  unsigned Size = VT.getSizeInBits()/8;
2474  Len -= Size;
2475  Dest.Offset += Size;
2476  Src.Offset += Size;
2477  }
2478 
2479  return true;
2480 }
2481 
2482 bool ARMFastISel::SelectIntrinsicCall(const IntrinsicInst &I) {
2483  // FIXME: Handle more intrinsics.
2484  switch (I.getIntrinsicID()) {
2485  default: return false;
2486  case Intrinsic::frameaddress: {
2487  MachineFrameInfo *MFI = FuncInfo.MF->getFrameInfo();
2488  MFI->setFrameAddressIsTaken(true);
2489 
2490  unsigned LdrOpc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;
2491  const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass
2492  : &ARM::GPRRegClass;
2493 
2494  const ARMBaseRegisterInfo *RegInfo =
2495  static_cast<const ARMBaseRegisterInfo *>(Subtarget->getRegisterInfo());
2496  unsigned FramePtr = RegInfo->getFrameRegister(*(FuncInfo.MF));
2497  unsigned SrcReg = FramePtr;
2498 
2499  // Recursively load frame address
2500  // ldr r0 [fp]
2501  // ldr r0 [r0]
2502  // ldr r0 [r0]
2503  // ...
2504  unsigned DestReg;
2505  unsigned Depth = cast<ConstantInt>(I.getOperand(0))->getZExtValue();
2506  while (Depth--) {
2507  DestReg = createResultReg(RC);
2508  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2509  TII.get(LdrOpc), DestReg)
2510  .addReg(SrcReg).addImm(0));
2511  SrcReg = DestReg;
2512  }
2513  updateValueMap(&I, SrcReg);
2514  return true;
2515  }
2516  case Intrinsic::memcpy:
2517  case Intrinsic::memmove: {
2518  const MemTransferInst &MTI = cast<MemTransferInst>(I);
2519  // Don't handle volatile.
2520  if (MTI.isVolatile())
2521  return false;
2522 
2523  // Disable inlining for memmove before calls to ComputeAddress. Otherwise,
2524  // we would emit dead code because we don't currently handle memmoves.
2525  bool isMemCpy = (I.getIntrinsicID() == Intrinsic::memcpy);
2526  if (isa<ConstantInt>(MTI.getLength()) && isMemCpy) {
2527  // Small memcpy's are common enough that we want to do them without a call
2528  // if possible.
2529  uint64_t Len = cast<ConstantInt>(MTI.getLength())->getZExtValue();
2530  if (ARMIsMemCpySmall(Len)) {
2531  Address Dest, Src;
2532  if (!ARMComputeAddress(MTI.getRawDest(), Dest) ||
2533  !ARMComputeAddress(MTI.getRawSource(), Src))
2534  return false;
2535  unsigned Alignment = MTI.getAlignment();
2536  if (ARMTryEmitSmallMemCpy(Dest, Src, Len, Alignment))
2537  return true;
2538  }
2539  }
2540 
2541  if (!MTI.getLength()->getType()->isIntegerTy(32))
2542  return false;
2543 
2544  if (MTI.getSourceAddressSpace() > 255 || MTI.getDestAddressSpace() > 255)
2545  return false;
2546 
2547  const char *IntrMemName = isa<MemCpyInst>(I) ? "memcpy" : "memmove";
2548  return SelectCall(&I, IntrMemName);
2549  }
2550  case Intrinsic::memset: {
2551  const MemSetInst &MSI = cast<MemSetInst>(I);
2552  // Don't handle volatile.
2553  if (MSI.isVolatile())
2554  return false;
2555 
2556  if (!MSI.getLength()->getType()->isIntegerTy(32))
2557  return false;
2558 
2559  if (MSI.getDestAddressSpace() > 255)
2560  return false;
2561 
2562  return SelectCall(&I, "memset");
2563  }
2564  case Intrinsic::trap: {
2565  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(
2566  Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP));
2567  return true;
2568  }
2569  }
2570 }
2571 
2572 bool ARMFastISel::SelectTrunc(const Instruction *I) {
2573  // The high bits for a type smaller than the register size are assumed to be
2574  // undefined.
2575  Value *Op = I->getOperand(0);
2576 
2577  EVT SrcVT, DestVT;
2578  SrcVT = TLI.getValueType(DL, Op->getType(), true);
2579  DestVT = TLI.getValueType(DL, I->getType(), true);
2580 
2581  if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
2582  return false;
2583  if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
2584  return false;
2585 
2586  unsigned SrcReg = getRegForValue(Op);
2587  if (!SrcReg) return false;
2588 
2589  // Because the high bits are undefined, a truncate doesn't generate
2590  // any code.
2591  updateValueMap(I, SrcReg);
2592  return true;
2593 }
2594 
2595 unsigned ARMFastISel::ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
2596  bool isZExt) {
2597  if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
2598  return 0;
2599  if (SrcVT != MVT::i16 && SrcVT != MVT::i8 && SrcVT != MVT::i1)
2600  return 0;
2601 
2602  // Table of which combinations can be emitted as a single instruction,
2603  // and which will require two.
2604  static const uint8_t isSingleInstrTbl[3][2][2][2] = {
2605  // ARM Thumb
2606  // !hasV6Ops hasV6Ops !hasV6Ops hasV6Ops
2607  // ext: s z s z s z s z
2608  /* 1 */ { { { 0, 1 }, { 0, 1 } }, { { 0, 0 }, { 0, 1 } } },
2609  /* 8 */ { { { 0, 1 }, { 1, 1 } }, { { 0, 0 }, { 1, 1 } } },
2610  /* 16 */ { { { 0, 0 }, { 1, 1 } }, { { 0, 0 }, { 1, 1 } } }
2611  };
2612 
2613  // Target registers for:
2614  // - For ARM can never be PC.
2615  // - For 16-bit Thumb are restricted to lower 8 registers.
2616  // - For 32-bit Thumb are restricted to non-SP and non-PC.
2617  static const TargetRegisterClass *RCTbl[2][2] = {
2618  // Instructions: Two Single
2619  /* ARM */ { &ARM::GPRnopcRegClass, &ARM::GPRnopcRegClass },
2620  /* Thumb */ { &ARM::tGPRRegClass, &ARM::rGPRRegClass }
2621  };
2622 
2623  // Table governing the instruction(s) to be emitted.
2624  static const struct InstructionTable {
2625  uint32_t Opc : 16;
2626  uint32_t hasS : 1; // Some instructions have an S bit, always set it to 0.
2627  uint32_t Shift : 7; // For shift operand addressing mode, used by MOVsi.
2628  uint32_t Imm : 8; // All instructions have either a shift or a mask.
2629  } IT[2][2][3][2] = {
2630  { // Two instructions (first is left shift, second is in this table).
2631  { // ARM Opc S Shift Imm
2632  /* 1 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 31 },
2633  /* 1 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 31 } },
2634  /* 8 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 24 },
2635  /* 8 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 24 } },
2636  /* 16 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 16 },
2637  /* 16 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 16 } }
2638  },
2639  { // Thumb Opc S Shift Imm
2640  /* 1 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 31 },
2641  /* 1 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 31 } },
2642  /* 8 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 24 },
2643  /* 8 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 24 } },
2644  /* 16 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 16 },
2645  /* 16 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 16 } }
2646  }
2647  },
2648  { // Single instruction.
2649  { // ARM Opc S Shift Imm
2650  /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 },
2651  /* 1 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 1 } },
2652  /* 8 bit sext */ { { ARM::SXTB , 0, ARM_AM::no_shift, 0 },
2653  /* 8 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 255 } },
2654  /* 16 bit sext */ { { ARM::SXTH , 0, ARM_AM::no_shift, 0 },
2655  /* 16 bit zext */ { ARM::UXTH , 0, ARM_AM::no_shift, 0 } }
2656  },
2657  { // Thumb Opc S Shift Imm
2658  /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 },
2659  /* 1 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 1 } },
2660  /* 8 bit sext */ { { ARM::t2SXTB , 0, ARM_AM::no_shift, 0 },
2661  /* 8 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 255 } },
2662  /* 16 bit sext */ { { ARM::t2SXTH , 0, ARM_AM::no_shift, 0 },
2663  /* 16 bit zext */ { ARM::t2UXTH , 0, ARM_AM::no_shift, 0 } }
2664  }
2665  }
2666  };
2667 
2668  unsigned SrcBits = SrcVT.getSizeInBits();
2669  unsigned DestBits = DestVT.getSizeInBits();
2670  (void) DestBits;
2671  assert((SrcBits < DestBits) && "can only extend to larger types");
2672  assert((DestBits == 32 || DestBits == 16 || DestBits == 8) &&
2673  "other sizes unimplemented");
2674  assert((SrcBits == 16 || SrcBits == 8 || SrcBits == 1) &&
2675  "other sizes unimplemented");
2676 
2677  bool hasV6Ops = Subtarget->hasV6Ops();
2678  unsigned Bitness = SrcBits / 8; // {1,8,16}=>{0,1,2}
2679  assert((Bitness < 3) && "sanity-check table bounds");
2680 
2681  bool isSingleInstr = isSingleInstrTbl[Bitness][isThumb2][hasV6Ops][isZExt];
2682  const TargetRegisterClass *RC = RCTbl[isThumb2][isSingleInstr];
2683  const InstructionTable *ITP = &IT[isSingleInstr][isThumb2][Bitness][isZExt];
2684  unsigned Opc = ITP->Opc;
2685  assert(ARM::KILL != Opc && "Invalid table entry");
2686  unsigned hasS = ITP->hasS;
2687  ARM_AM::ShiftOpc Shift = (ARM_AM::ShiftOpc) ITP->Shift;
2688  assert(((Shift == ARM_AM::no_shift) == (Opc != ARM::MOVsi)) &&
2689  "only MOVsi has shift operand addressing mode");
2690  unsigned Imm = ITP->Imm;
2691 
2692  // 16-bit Thumb instructions always set CPSR (unless they're in an IT block).
2693  bool setsCPSR = &ARM::tGPRRegClass == RC;
2694  unsigned LSLOpc = isThumb2 ? ARM::tLSLri : ARM::MOVsi;
2695  unsigned ResultReg;
2696  // MOVsi encodes shift and immediate in shift operand addressing mode.
2697  // The following condition has the same value when emitting two
2698  // instruction sequences: both are shifts.
2699  bool ImmIsSO = (Shift != ARM_AM::no_shift);
2700 
2701  // Either one or two instructions are emitted.
2702  // They're always of the form:
2703  // dst = in OP imm
2704  // CPSR is set only by 16-bit Thumb instructions.
2705  // Predicate, if any, is AL.
2706  // S bit, if available, is always 0.
2707  // When two are emitted the first's result will feed as the second's input,
2708  // that value is then dead.
2709  unsigned NumInstrsEmitted = isSingleInstr ? 1 : 2;
2710  for (unsigned Instr = 0; Instr != NumInstrsEmitted; ++Instr) {
2711  ResultReg = createResultReg(RC);
2712  bool isLsl = (0 == Instr) && !isSingleInstr;
2713  unsigned Opcode = isLsl ? LSLOpc : Opc;
2714  ARM_AM::ShiftOpc ShiftAM = isLsl ? ARM_AM::lsl : Shift;
2715  unsigned ImmEnc = ImmIsSO ? ARM_AM::getSORegOpc(ShiftAM, Imm) : Imm;
2716  bool isKill = 1 == Instr;
2718  *FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opcode), ResultReg);
2719  if (setsCPSR)
2720  MIB.addReg(ARM::CPSR, RegState::Define);
2721  SrcReg = constrainOperandRegClass(TII.get(Opcode), SrcReg, 1 + setsCPSR);
2722  AddDefaultPred(MIB.addReg(SrcReg, isKill * RegState::Kill).addImm(ImmEnc));
2723  if (hasS)
2724  AddDefaultCC(MIB);
2725  // Second instruction consumes the first's result.
2726  SrcReg = ResultReg;
2727  }
2728 
2729  return ResultReg;
2730 }
2731 
2732 bool ARMFastISel::SelectIntExt(const Instruction *I) {
2733  // On ARM, in general, integer casts don't involve legal types; this code
2734  // handles promotable integers.
2735  Type *DestTy = I->getType();
2736  Value *Src = I->getOperand(0);
2737  Type *SrcTy = Src->getType();
2738 
2739  bool isZExt = isa<ZExtInst>(I);
2740  unsigned SrcReg = getRegForValue(Src);
2741  if (!SrcReg) return false;
2742 
2743  EVT SrcEVT, DestEVT;
2744  SrcEVT = TLI.getValueType(DL, SrcTy, true);
2745  DestEVT = TLI.getValueType(DL, DestTy, true);
2746  if (!SrcEVT.isSimple()) return false;
2747  if (!DestEVT.isSimple()) return false;
2748 
2749  MVT SrcVT = SrcEVT.getSimpleVT();
2750  MVT DestVT = DestEVT.getSimpleVT();
2751  unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
2752  if (ResultReg == 0) return false;
2753  updateValueMap(I, ResultReg);
2754  return true;
2755 }
2756 
2757 bool ARMFastISel::SelectShift(const Instruction *I,
2758  ARM_AM::ShiftOpc ShiftTy) {
2759  // We handle thumb2 mode by target independent selector
2760  // or SelectionDAG ISel.
2761  if (isThumb2)
2762  return false;
2763 
2764  // Only handle i32 now.
2765  EVT DestVT = TLI.getValueType(DL, I->getType(), true);
2766  if (DestVT != MVT::i32)
2767  return false;
2768 
2769  unsigned Opc = ARM::MOVsr;
2770  unsigned ShiftImm;
2771  Value *Src2Value = I->getOperand(1);
2772  if (const ConstantInt *CI = dyn_cast<ConstantInt>(Src2Value)) {
2773  ShiftImm = CI->getZExtValue();
2774 
2775  // Fall back to selection DAG isel if the shift amount
2776  // is zero or greater than the width of the value type.
2777  if (ShiftImm == 0 || ShiftImm >=32)
2778  return false;
2779 
2780  Opc = ARM::MOVsi;
2781  }
2782 
2783  Value *Src1Value = I->getOperand(0);
2784  unsigned Reg1 = getRegForValue(Src1Value);
2785  if (Reg1 == 0) return false;
2786 
2787  unsigned Reg2 = 0;
2788  if (Opc == ARM::MOVsr) {
2789  Reg2 = getRegForValue(Src2Value);
2790  if (Reg2 == 0) return false;
2791  }
2792 
2793  unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass);
2794  if(ResultReg == 0) return false;
2795 
2796  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2797  TII.get(Opc), ResultReg)
2798  .addReg(Reg1);
2799 
2800  if (Opc == ARM::MOVsi)
2801  MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm));
2802  else if (Opc == ARM::MOVsr) {
2803  MIB.addReg(Reg2);
2804  MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, 0));
2805  }
2806 
2807  AddOptionalDefs(MIB);
2808  updateValueMap(I, ResultReg);
2809  return true;
2810 }
2811 
2812 // TODO: SoftFP support.
2813 bool ARMFastISel::fastSelectInstruction(const Instruction *I) {
2814 
2815  switch (I->getOpcode()) {
2816  case Instruction::Load:
2817  return SelectLoad(I);
2818  case Instruction::Store:
2819  return SelectStore(I);
2820  case Instruction::Br:
2821  return SelectBranch(I);
2822  case Instruction::IndirectBr:
2823  return SelectIndirectBr(I);
2824  case Instruction::ICmp:
2825  case Instruction::FCmp:
2826  return SelectCmp(I);
2827  case Instruction::FPExt:
2828  return SelectFPExt(I);
2829  case Instruction::FPTrunc:
2830  return SelectFPTrunc(I);
2831  case Instruction::SIToFP:
2832  return SelectIToFP(I, /*isSigned*/ true);
2833  case Instruction::UIToFP:
2834  return SelectIToFP(I, /*isSigned*/ false);
2835  case Instruction::FPToSI:
2836  return SelectFPToI(I, /*isSigned*/ true);
2837  case Instruction::FPToUI:
2838  return SelectFPToI(I, /*isSigned*/ false);
2839  case Instruction::Add:
2840  return SelectBinaryIntOp(I, ISD::ADD);
2841  case Instruction::Or:
2842  return SelectBinaryIntOp(I, ISD::OR);
2843  case Instruction::Sub:
2844  return SelectBinaryIntOp(I, ISD::SUB);
2845  case Instruction::FAdd:
2846  return SelectBinaryFPOp(I, ISD::FADD);
2847  case Instruction::FSub:
2848  return SelectBinaryFPOp(I, ISD::FSUB);
2849  case Instruction::FMul:
2850  return SelectBinaryFPOp(I, ISD::FMUL);
2851  case Instruction::SDiv:
2852  return SelectDiv(I, /*isSigned*/ true);
2853  case Instruction::UDiv:
2854  return SelectDiv(I, /*isSigned*/ false);
2855  case Instruction::SRem:
2856  return SelectRem(I, /*isSigned*/ true);
2857  case Instruction::URem:
2858  return SelectRem(I, /*isSigned*/ false);
2859  case Instruction::Call:
2860  if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
2861  return SelectIntrinsicCall(*II);
2862  return SelectCall(I);
2863  case Instruction::Select:
2864  return SelectSelect(I);
2865  case Instruction::Ret:
2866  return SelectRet(I);
2867  case Instruction::Trunc:
2868  return SelectTrunc(I);
2869  case Instruction::ZExt:
2870  case Instruction::SExt:
2871  return SelectIntExt(I);
2872  case Instruction::Shl:
2873  return SelectShift(I, ARM_AM::lsl);
2874  case Instruction::LShr:
2875  return SelectShift(I, ARM_AM::lsr);
2876  case Instruction::AShr:
2877  return SelectShift(I, ARM_AM::asr);
2878  default: break;
2879  }
2880  return false;
2881 }
2882 
2883 namespace {
2884 // This table describes sign- and zero-extend instructions which can be
2885 // folded into a preceding load. All of these extends have an immediate
2886 // (sometimes a mask and sometimes a shift) that's applied after
2887 // extension.
2888 const struct FoldableLoadExtendsStruct {
2889  uint16_t Opc[2]; // ARM, Thumb.
2890  uint8_t ExpectedImm;
2891  uint8_t isZExt : 1;
2892  uint8_t ExpectedVT : 7;
2893 } FoldableLoadExtends[] = {
2894  { { ARM::SXTH, ARM::t2SXTH }, 0, 0, MVT::i16 },
2895  { { ARM::UXTH, ARM::t2UXTH }, 0, 1, MVT::i16 },
2896  { { ARM::ANDri, ARM::t2ANDri }, 255, 1, MVT::i8 },
2897  { { ARM::SXTB, ARM::t2SXTB }, 0, 0, MVT::i8 },
2898  { { ARM::UXTB, ARM::t2UXTB }, 0, 1, MVT::i8 }
2899 };
2900 }
2901 
2902 /// \brief The specified machine instr operand is a vreg, and that
2903 /// vreg is being provided by the specified load instruction. If possible,
2904 /// try to fold the load as an operand to the instruction, returning true if
2905 /// successful.
2906 bool ARMFastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
2907  const LoadInst *LI) {
2908  // Verify we have a legal type before going any further.
2909  MVT VT;
2910  if (!isLoadTypeLegal(LI->getType(), VT))
2911  return false;
2912 
2913  // Combine load followed by zero- or sign-extend.
2914  // ldrb r1, [r0] ldrb r1, [r0]
2915  // uxtb r2, r1 =>
2916  // mov r3, r2 mov r3, r1
2917  if (MI->getNumOperands() < 3 || !MI->getOperand(2).isImm())
2918  return false;
2919  const uint64_t Imm = MI->getOperand(2).getImm();
2920 
2921  bool Found = false;
2922  bool isZExt;
2923  for (unsigned i = 0, e = array_lengthof(FoldableLoadExtends);
2924  i != e; ++i) {
2925  if (FoldableLoadExtends[i].Opc[isThumb2] == MI->getOpcode() &&
2926  (uint64_t)FoldableLoadExtends[i].ExpectedImm == Imm &&
2927  MVT((MVT::SimpleValueType)FoldableLoadExtends[i].ExpectedVT) == VT) {
2928  Found = true;
2929  isZExt = FoldableLoadExtends[i].isZExt;
2930  }
2931  }
2932  if (!Found) return false;
2933 
2934  // See if we can handle this address.
2935  Address Addr;
2936  if (!ARMComputeAddress(LI->getOperand(0), Addr)) return false;
2937 
2938  unsigned ResultReg = MI->getOperand(0).getReg();
2939  if (!ARMEmitLoad(VT, ResultReg, Addr, LI->getAlignment(), isZExt, false))
2940  return false;
2941  MI->eraseFromParent();
2942  return true;
2943 }
2944 
2945 unsigned ARMFastISel::ARMLowerPICELF(const GlobalValue *GV,
2946  unsigned Align, MVT VT) {
2947  bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
2950  unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
2951 
2952  unsigned Opc;
2953  unsigned DestReg1 = createResultReg(TLI.getRegClassFor(VT));
2954  // Load value.
2955  if (isThumb2) {
2956  DestReg1 = constrainOperandRegClass(TII.get(ARM::t2LDRpci), DestReg1, 0);
2957  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2958  TII.get(ARM::t2LDRpci), DestReg1)
2959  .addConstantPoolIndex(Idx));
2960  Opc = UseGOTOFF ? ARM::t2ADDrr : ARM::t2LDRs;
2961  } else {
2962  // The extra immediate is for addrmode2.
2963  DestReg1 = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg1, 0);
2964  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2965  DbgLoc, TII.get(ARM::LDRcp), DestReg1)
2966  .addConstantPoolIndex(Idx).addImm(0));
2967  Opc = UseGOTOFF ? ARM::ADDrr : ARM::LDRrs;
2968  }
2969 
2970  unsigned GlobalBaseReg = AFI->getGlobalBaseReg();
2971  if (GlobalBaseReg == 0) {
2972  GlobalBaseReg = MRI.createVirtualRegister(TLI.getRegClassFor(VT));
2973  AFI->setGlobalBaseReg(GlobalBaseReg);
2974  }
2975 
2976  unsigned DestReg2 = createResultReg(TLI.getRegClassFor(VT));
2977  DestReg2 = constrainOperandRegClass(TII.get(Opc), DestReg2, 0);
2978  DestReg1 = constrainOperandRegClass(TII.get(Opc), DestReg1, 1);
2979  GlobalBaseReg = constrainOperandRegClass(TII.get(Opc), GlobalBaseReg, 2);
2980  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2981  DbgLoc, TII.get(Opc), DestReg2)
2982  .addReg(DestReg1)
2983  .addReg(GlobalBaseReg);
2984  if (!UseGOTOFF)
2985  MIB.addImm(0);
2986  AddOptionalDefs(MIB);
2987 
2988  return DestReg2;
2989 }
2990 
2991 bool ARMFastISel::fastLowerArguments() {
2992  if (!FuncInfo.CanLowerReturn)
2993  return false;
2994 
2995  const Function *F = FuncInfo.Fn;
2996  if (F->isVarArg())
2997  return false;
2998 
2999  CallingConv::ID CC = F->getCallingConv();
3000  switch (CC) {
3001  default:
3002  return false;
3003  case CallingConv::Fast:
3004  case CallingConv::C:
3007  case CallingConv::ARM_APCS:
3008  break;
3009  }
3010 
3011  // Only handle simple cases. i.e. Up to 4 i8/i16/i32 scalar arguments
3012  // which are passed in r0 - r3.
3013  unsigned Idx = 1;
3014  for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
3015  I != E; ++I, ++Idx) {
3016  if (Idx > 4)
3017  return false;
3018 
3019  if (F->getAttributes().hasAttribute(Idx, Attribute::InReg) ||
3022  return false;
3023 
3024  Type *ArgTy = I->getType();
3025  if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy())
3026  return false;
3027 
3028  EVT ArgVT = TLI.getValueType(DL, ArgTy);
3029  if (!ArgVT.isSimple()) return false;
3030  switch (ArgVT.getSimpleVT().SimpleTy) {
3031  case MVT::i8:
3032  case MVT::i16:
3033  case MVT::i32:
3034  break;
3035  default:
3036  return false;
3037  }
3038  }
3039 
3040 
3041  static const uint16_t GPRArgRegs[] = {
3042  ARM::R0, ARM::R1, ARM::R2, ARM::R3
3043  };
3044 
3045  const TargetRegisterClass *RC = &ARM::rGPRRegClass;
3046  Idx = 0;
3047  for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
3048  I != E; ++I, ++Idx) {
3049  unsigned SrcReg = GPRArgRegs[Idx];
3050  unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC);
3051  // FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
3052  // Without this, EmitLiveInCopies may eliminate the livein if its only
3053  // use is a bitcast (which isn't turned into an instruction).
3054  unsigned ResultReg = createResultReg(RC);
3055  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3056  TII.get(TargetOpcode::COPY),
3057  ResultReg).addReg(DstReg, getKillRegState(true));
3058  updateValueMap(I, ResultReg);
3059  }
3060 
3061  return true;
3062 }
3063 
3064 namespace llvm {
3066  const TargetLibraryInfo *libInfo) {
3067  if (funcInfo.MF->getSubtarget<ARMSubtarget>().useFastISel())
3068  return new ARMFastISel(funcInfo, libInfo);
3069 
3070  return nullptr;
3071  }
3072 }
unsigned getAlignment() const
void setFrameAddressIsTaken(bool T)
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:477
ReturnInst - Return a value (possibly void), from a function.
const Value * getCalledValue() const
getCalledValue - Get a pointer to the function that is invoked by this instruction.
void push_back(const T &Elt)
Definition: SmallVector.h:222
The memory access reads data.
This class is the base class for the comparison instructions.
Definition: InstrTypes.h:679
The memory access writes data.
MVT getValVT() const
bool isPredicate() const
Set if this is one of the operands that made up of the predicate operand that controls an isPredicabl...
Definition: MCInstrDesc.h:82
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:223
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1327
Sign extended before/after call.
Definition: Attributes.h:105
LocInfo getLocInfo() const
static void Found()
bool isVolatile() const
Force argument to be passed in register.
Definition: Attributes.h:78
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:114
ARM_APCS - ARM Procedure Calling Standard calling convention (obsolete, but still used on some target...
Definition: CallingConv.h:89
Intrinsic::ID getIntrinsicID() const
getIntrinsicID - Return the intrinsic ID of this intrinsic.
Definition: IntrinsicInst.h:44
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:191
static unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm)
unsigned getNumOperands() const
Definition: User.h:138
Nested function static chain.
Definition: Attributes.h:82
ARMConstantPoolValue - ARM specific constantpool value.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:138
CallInst - This class represents a function call, abstracting a target machine's calling convention...
static PointerType * getInt32PtrTy(LLVMContext &C, unsigned AS=0)
Definition: Type.cpp:291
Predicate getInversePredicate() const
For example, EQ -> NE, UGT -> ULE, SLT -> SGE, OEQ -> UNE, UGT -> OLE, OLT -> UGE, etc.
Definition: InstrTypes.h:783
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
bool isPredicable(QueryType Type=AllInBundle) const
Return true if this instruction has a predicate operand that controls execution.
Definition: MachineInstr.h:457
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
unsigned less or equal
Definition: InstrTypes.h:723
unsigned less than
Definition: InstrTypes.h:722
bool useFastISel() const
True if fast-isel is used.
0 1 0 0 True if ordered and less than
Definition: InstrTypes.h:703
unsigned getSizeInBits() const
Externally visible function.
Definition: GlobalValue.h:40
bool isDoubleTy() const
isDoubleTy - Return true if this is 'double', a 64-bit IEEE fp type.
Definition: Type.h:146
1 1 1 0 True if unordered or not equal
Definition: InstrTypes.h:713
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:264
MemSetInst - This class wraps the llvm.memset intrinsic.
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:111
arg_iterator arg_end()
Definition: Function.h:480
F(f)
LoadInst - an instruction for reading from memory.
Definition: Instructions.h:177
#define R2(n)
User::const_op_iterator arg_iterator
arg_iterator - The type of iterator to use when looping over actual arguments at this call site...
Definition: CallSite.h:147
MO_PLT - On a symbol operand, this represents an ELF PLT reference on a call operand.
Definition: ARMBaseInfo.h:294
void reserve(size_type N)
Definition: SmallVector.h:401
bool hasAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return true if the attribute exists at the given index.
Definition: Attributes.cpp:956
unsigned getValNo() const
op_iterator op_begin()
Definition: User.h:183
bool isRegLoc() const
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:172
static MachinePointerInfo getFixedStack(int FI, int64_t offset=0)
getFixedStack - Return a MachinePointerInfo record that refers to the the specified FrameIndex...
GlobalBaseReg - On Darwin, this node represents the result of the mflr at function entry...
COPY - Target-independent register copy.
Definition: TargetOpcodes.h:86
1 0 0 1 True if unordered or equal
Definition: InstrTypes.h:708
Used to lazily calculate structure layout information for a target machine, based on the DataLayout s...
Definition: DataLayout.h:475
1 0 0 0 True if unordered: isnan(X) | isnan(Y)
Definition: InstrTypes.h:707
MachineMemOperand - A description of a memory reference used in the backend.
static const MachineInstrBuilder & AddDefaultPred(const MachineInstrBuilder &MIB)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:79
const HexagonInstrInfo * TII
static cl::opt< ITMode > IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT), cl::ZeroOrMore, cl::values(clEnumValN(DefaultIT,"arm-default-it","Generate IT block based on arch"), clEnumValN(RestrictedIT,"arm-restrict-it","Disallow deprecated IT based on ARMv8"), clEnumValN(NoRestrictedIT,"arm-no-restrict-it","Allow IT blocks based on ARMv7"), clEnumValEnd))
StructType - Class to represent struct types.
Definition: DerivedTypes.h:191
static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred)
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
A Use represents the edge between a Value definition and its users.
Definition: Use.h:69
unsigned getFrameRegister(const MachineFunction &MF) const override
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APInt.h:33
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
Reg
All possible values of the reg field in the ModR/M byte.
0 1 0 1 True if ordered and less than or equal
Definition: InstrTypes.h:704
SimpleValueType SimpleTy
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Hidden pointer to structure to return.
Definition: Attributes.h:114
bool isNegative() const
Definition: Constants.h:156
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:271
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
Definition: Constants.h:117
unsigned getLocReg() const
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:30
FunctionType - Class to represent function types.
Definition: DerivedTypes.h:96
ConstantExpr - a constant value that is initialized with an expression using other constant values...
Definition: Constants.h:852
void GetReturnInfo(Type *ReturnType, AttributeSet attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags...
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:191
static int getT2SOImmVal(unsigned Arg)
getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit into a Thumb-2 shifter_oper...
BasicBlock * getSuccessor(unsigned i) const
Pass structure by value.
Definition: Attributes.h:73
bool isArrayTy() const
isArrayTy - True if this is an instance of ArrayType.
Definition: Type.h:213
static int getFP32Imm(const APInt &Imm)
getFP32Imm - Return an 8-bit floating-point version of the 32-bit floating-point value.
int64_t getImm() const
static const MCPhysReg GPRArgRegs[]
void setOrigAlign(unsigned A)
Type * getElementType() const
Definition: DerivedTypes.h:323
This class represents a truncation of integer types.
PointerType - Class to represent pointers.
Definition: DerivedTypes.h:449
unsigned getKillRegState(bool B)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:267
TargetInstrInfo - Interface to description of machine instruction set.
uint64_t getElementOffset(unsigned Idx) const
Definition: DataLayout.h:491
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:247
A self-contained host- and target-independent arbitrary-precision floating-point software implementat...
Definition: APFloat.h:122
MVT - Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:41
ARM_AAPCS_VFP - Same as ARM_AAPCS, but uses hard floating point ABI.
Definition: CallingConv.h:96
Simple binary floating point operators.
Definition: ISDOpcodes.h:237
BranchInst - Conditional or Unconditional Branch instruction.
bool isVectorTy() const
isVectorTy - True if this is an instance of VectorType.
Definition: Type.h:226
MVT getLocVT() const
This is an important base class in LLVM.
Definition: Constant.h:41
PointerType * getType() const
getType - Overload to return most specific pointer type
Definition: Instructions.h:115
bool isVector() const
isVector - Return true if this is a vector value type.
bool hasHiddenVisibility() const
Definition: GlobalValue.h:141
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1339
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
IndirectBrInst - Indirect Branch Instruction.
bool isFloatTy() const
isFloatTy - Return true if this is 'float', a 32-bit IEEE fp type.
Definition: Type.h:143
APInt Or(const APInt &LHS, const APInt &RHS)
Bitwise OR function for APInt.
Definition: APInt.h:1895
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:233
Value * getRawDest() const
op_iterator op_end()
Definition: User.h:185
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:697
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:644
Value * getOperand(unsigned i) const
Definition: User.h:118
Zero extended before/after call.
Definition: Attributes.h:119
0 1 1 1 True if ordered (no nans)
Definition: InstrTypes.h:706
arg_iterator arg_begin()
Definition: Function.h:472
Predicate getPredicate() const
Return the predicate for this instruction.
Definition: InstrTypes.h:760
bool isThreadLocal() const
If the value is "Thread Local", its value isn't shared by the threads.
Definition: GlobalValue.h:152
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
EVT - Extended Value Type.
Definition: ValueTypes.h:31
LLVMContext & getContext() const
All values hold a context through their type.
Definition: Value.cpp:519
static bool isAtomic(Instruction *I)
ARM_AAPCS - ARM Architecture Procedure Calling Standard calling convention (aka EABI).
Definition: CallingConv.h:93
1 1 0 1 True if unordered, less than, or equal
Definition: InstrTypes.h:712
signed greater than
Definition: InstrTypes.h:724
bool needsCustom() const
0 0 1 0 True if ordered and greater than
Definition: InstrTypes.h:701
ARMConstantPoolConstant - ARM-specific constant pool values for Constants, Functions, and BlockAddresses.
static const MachineInstrBuilder & AddDefaultCC(const MachineInstrBuilder &MIB)
static int getFP64Imm(const APInt &Imm)
getFP64Imm - Return an 8-bit floating-point version of the 64-bit floating-point value.
CCState - This class holds information needed while lowering arguments and return values...
This is the shared class of boolean and integer constants.
Definition: Constants.h:47
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:861
1 1 0 0 True if unordered or less than
Definition: InstrTypes.h:711
Module.h This file contains the declarations for the Module class.
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:222
Provides information about what library functions are available for the current target.
CCValAssign - Represent assignment of one arg/retval to a location.
signed less than
Definition: InstrTypes.h:726
Value * getLength() const
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:582
const MachineInstrBuilder & addFrameIndex(int Idx) const
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:576
AttributeSet getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:181
signed less or equal
Definition: InstrTypes.h:727
Target - Wrapper for Target specific information.
Class for arbitrary precision integers.
Definition: APInt.h:73
bool isIntegerTy() const
isIntegerTy - True if this is an instance of IntegerType.
Definition: Type.h:193
This file defines the FastISel class.
bool isMemLoc() const
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:285
KILL - This instruction is a noop that is used only to adjust the liveness of registers.
Definition: TargetOpcodes.h:35
static int getSOImmVal(unsigned Arg)
getSOImmVal - Given a 32-bit immediate, if it is something that can fit into an shifter_operand immed...
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned char TargetFlags=0) const
bool isStructTy() const
isStructTy - True if this is an instance of StructType.
Definition: Type.h:209
Representation of each machine instruction.
Definition: MachineInstr.h:51
PointerType * getType() const
Global values are always pointers.
Definition: GlobalValue.h:185
MemTransferInst - This class wraps the llvm.memcpy/memmove intrinsics.
Value * getCondition() const
static IntegerType * getInt32Ty(LLVMContext &C)
Definition: Type.cpp:239
unsigned greater or equal
Definition: InstrTypes.h:721
unsigned getAlignment() const
getAlignment - Return the alignment of the access that is being performed
Definition: Instructions.h:243
static unsigned UseReg(const MachineOperand &MO)
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned char TargetFlags=0) const
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
ImmutableCallSite - establish a view to a call site for examination.
Definition: CallSite.h:418
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
#define I(x, y, z)
Definition: MD5.cpp:54
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
bool hasOneUse() const
Return true if there is exactly one user of this value.
Definition: Value.h:311
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
bool isTailCall() const
0 1 1 0 True if ordered and operands are unequal
Definition: InstrTypes.h:705
1 0 1 0 True if unordered or greater than
Definition: InstrTypes.h:709
bool hasLocalLinkage() const
Definition: GlobalValue.h:280
const APFloat & getValueAPF() const
Definition: Constants.h:270
Value * getRawSource() const
get* - Return the arguments to the instruction.
unsigned getReg() const
getReg - Returns the register number.
bool isUnsigned() const
Determine if this instruction is using an unsigned comparison.
Definition: InstrTypes.h:832
const uint16_t * ImplicitDefs
Definition: MCInstrDesc.h:148
bool isFloat(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether it is a floating-point insn.
bool isSimple() const
isSimple - Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:94
aarch64 promote const
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
0 0 0 1 True if ordered and equal
Definition: InstrTypes.h:700
LLVM Value Representation.
Definition: Value.h:69
1 0 1 1 True if unordered, greater than, or equal
Definition: InstrTypes.h:710
unsigned getOpcode() const
getOpcode() returns a member of one of the enums like Instruction::Add.
Definition: Instruction.h:112
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:185
unsigned getDestAddressSpace() const
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:149
static const Function * getParent(const Value *V)
MO_NONLAZY - This is an independent flag, on a symbol operand "FOO" it represents a symbol which...
Definition: ARMBaseInfo.h:310
bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:298
static const unsigned FramePtr
Primary interface to the complete machine description for the target machine.
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
unsigned greater than
Definition: InstrTypes.h:720
bool hasOptionalDef(QueryType Type=IgnoreBundle) const
Set if this instruction has an optional definition, e.g.
Definition: MachineInstr.h:389
unsigned getLocMemOffset() const
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
int64_t getSExtValue() const
Return the constant as a 64-bit integer value after it has been sign extended as appropriate for the ...
Definition: Constants.h:125
0 0 1 1 True if ordered and greater than or equal
Definition: InstrTypes.h:702
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
unsigned getSourceAddressSpace() const
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Definition: Function.cpp:229
const BasicBlock * getParent() const
Definition: Instruction.h:72
static ARMConstantPoolConstant * Create(const Constant *C, unsigned ID)
MVT getSimpleVT() const
getSimpleVT - Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:203
static const MachineInstrBuilder & AddDefaultT1CC(const MachineInstrBuilder &MIB, bool isDead=false)
signed greater or equal
Definition: InstrTypes.h:725
IntrinsicInst - A useful wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:37
This file describes how to lower LLVM code to machine code.
bool isVoidTy() const
isVoidTy - Return true if this is 'void'.
Definition: Type.h:137
AllocaInst - an instruction to allocate memory on the stack.
Definition: Instructions.h:76
gep_type_iterator gep_type_begin(const User *GEP)
bool contains(unsigned Reg) const
contains - Return true if the specified register is included in this register class.