LLVM  3.7.0
MipsAsmBackend.cpp
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1 //===-- MipsAsmBackend.cpp - Mips Asm Backend ----------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the MipsAsmBackend class.
11 //
12 //===----------------------------------------------------------------------===//
13 //
14 
18 #include "llvm/MC/MCAsmBackend.h"
19 #include "llvm/MC/MCAssembler.h"
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/MC/MCDirectives.h"
24 #include "llvm/MC/MCObjectWriter.h"
29 
30 using namespace llvm;
31 
32 // Prepare value for the target space for it
33 static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
34  MCContext *Ctx = nullptr) {
35 
36  unsigned Kind = Fixup.getKind();
37 
38  // Add/subtract and shift
39  switch (Kind) {
40  default:
41  return 0;
42  case FK_Data_2:
43  case FK_GPRel_4:
44  case FK_Data_4:
45  case FK_Data_8:
60  break;
62  // The displacement is then divided by 4 to give us an 18 bit
63  // address range. Forcing a signed division because Value can be negative.
64  Value = (int64_t)Value / 4;
65  // We now check if Value can be encoded as a 16-bit signed immediate.
66  if (!isIntN(16, Value) && Ctx)
67  Ctx->reportFatalError(Fixup.getLoc(), "out of range PC16 fixup");
68  break;
70  // Forcing a signed division because Value can be negative.
71  Value = (int64_t)Value / 4;
72  // We now check if Value can be encoded as a 19-bit signed immediate.
73  if (!isIntN(19, Value) && Ctx)
74  Ctx->reportFatalError(Fixup.getLoc(), "out of range PC19 fixup");
75  break;
77  // So far we are only using this type for jumps.
78  // The displacement is then divided by 4 to give us an 28 bit
79  // address range.
80  Value >>= 2;
81  break;
88  // Get the 2nd 16-bits. Also add 1 if bit 15 is 1.
89  Value = ((Value + 0x8000) >> 16) & 0xffff;
90  break;
92  // Get the 3rd 16-bits.
93  Value = ((Value + 0x80008000LL) >> 32) & 0xffff;
94  break;
96  // Get the 4th 16-bits.
97  Value = ((Value + 0x800080008000LL) >> 48) & 0xffff;
98  break;
100  Value >>= 1;
101  break;
103  Value -= 4;
104  // Forcing a signed division because Value can be negative.
105  Value = (int64_t) Value / 2;
106  // We now check if Value can be encoded as a 7-bit signed immediate.
107  if (!isIntN(7, Value) && Ctx)
108  Ctx->reportFatalError(Fixup.getLoc(), "out of range PC7 fixup");
109  break;
111  Value -= 2;
112  // Forcing a signed division because Value can be negative.
113  Value = (int64_t) Value / 2;
114  // We now check if Value can be encoded as a 10-bit signed immediate.
115  if (!isIntN(10, Value) && Ctx)
116  Ctx->reportFatalError(Fixup.getLoc(), "out of range PC10 fixup");
117  break;
119  Value -= 4;
120  // Forcing a signed division because Value can be negative.
121  Value = (int64_t)Value / 2;
122  // We now check if Value can be encoded as a 16-bit signed immediate.
123  if (!isIntN(16, Value) && Ctx)
124  Ctx->reportFatalError(Fixup.getLoc(), "out of range PC16 fixup");
125  break;
127  // Forcing a signed division because Value can be negative.
128  Value = (int64_t)Value / 8;
129  // We now check if Value can be encoded as a 18-bit signed immediate.
130  if (!isIntN(18, Value) && Ctx)
131  Ctx->reportFatalError(Fixup.getLoc(), "out of range PC18 fixup");
132  break;
134  // Forcing a signed division because Value can be negative.
135  Value = (int64_t) Value / 4;
136  // We now check if Value can be encoded as a 21-bit signed immediate.
137  if (!isIntN(21, Value) && Ctx)
138  Ctx->reportFatalError(Fixup.getLoc(), "out of range PC21 fixup");
139  break;
141  // Forcing a signed division because Value can be negative.
142  Value = (int64_t) Value / 4;
143  // We now check if Value can be encoded as a 26-bit signed immediate.
144  if (!isIntN(26, Value) && Ctx)
145  Ctx->reportFatalError(Fixup.getLoc(), "out of range PC26 fixup");
146  break;
147  }
148 
149  return Value;
150 }
151 
154  return createMipsELFObjectWriter(OS,
155  MCELFObjectTargetWriter::getOSABI(OSType), IsLittle, Is64Bit);
156 }
157 
158 // Little-endian fixup data byte ordering:
159 // mips32r2: a | b | x | x
160 // microMIPS: x | x | a | b
161 
162 static bool needsMMLEByteOrder(unsigned Kind) {
163  return Kind != Mips::fixup_MICROMIPS_PC10_S1 &&
164  Kind >= Mips::fixup_MICROMIPS_26_S1 &&
166 }
167 
168 // Calculate index for microMIPS specific little endian byte order
169 static unsigned calculateMMLEIndex(unsigned i) {
170  assert(i <= 3 && "Index out of range!");
171 
172  return (1 - i / 2) * 2 + i % 2;
173 }
174 
175 /// ApplyFixup - Apply the \p Value for given \p Fixup into the provided
176 /// data fragment, at the offset specified by the fixup and following the
177 /// fixup kind as appropriate.
178 void MipsAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
179  unsigned DataSize, uint64_t Value,
180  bool IsPCRel) const {
181  MCFixupKind Kind = Fixup.getKind();
182  Value = adjustFixupValue(Fixup, Value);
183 
184  if (!Value)
185  return; // Doesn't change encoding.
186 
187  // Where do we start in the object
188  unsigned Offset = Fixup.getOffset();
189  // Number of bytes we need to fixup
190  unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8;
191  // Used to point to big endian bytes
192  unsigned FullSize;
193 
194  switch ((unsigned)Kind) {
195  case FK_Data_2:
196  case Mips::fixup_Mips_16:
198  FullSize = 2;
199  break;
200  case FK_Data_8:
201  case Mips::fixup_Mips_64:
202  FullSize = 8;
203  break;
204  case FK_Data_4:
205  default:
206  FullSize = 4;
207  break;
208  }
209 
210  // Grab current value, if any, from bits.
211  uint64_t CurVal = 0;
212 
213  bool microMipsLEByteOrder = needsMMLEByteOrder((unsigned) Kind);
214 
215  for (unsigned i = 0; i != NumBytes; ++i) {
216  unsigned Idx = IsLittle ? (microMipsLEByteOrder ? calculateMMLEIndex(i)
217  : i)
218  : (FullSize - 1 - i);
219  CurVal |= (uint64_t)((uint8_t)Data[Offset + Idx]) << (i*8);
220  }
221 
222  uint64_t Mask = ((uint64_t)(-1) >>
223  (64 - getFixupKindInfo(Kind).TargetSize));
224  CurVal |= Value & Mask;
225 
226  // Write out the fixed up bytes back to the code/data bits.
227  for (unsigned i = 0; i != NumBytes; ++i) {
228  unsigned Idx = IsLittle ? (microMipsLEByteOrder ? calculateMMLEIndex(i)
229  : i)
230  : (FullSize - 1 - i);
231  Data[Offset + Idx] = (uint8_t)((CurVal >> (i*8)) & 0xff);
232  }
233 }
234 
237  const static MCFixupKindInfo LittleEndianInfos[Mips::NumTargetFixupKinds] = {
238  // This table *must* be in same the order of fixup_* kinds in
239  // MipsFixupKinds.h.
240  //
241  // name offset bits flags
242  { "fixup_Mips_16", 0, 16, 0 },
243  { "fixup_Mips_32", 0, 32, 0 },
244  { "fixup_Mips_REL32", 0, 32, 0 },
245  { "fixup_Mips_26", 0, 26, 0 },
246  { "fixup_Mips_HI16", 0, 16, 0 },
247  { "fixup_Mips_LO16", 0, 16, 0 },
248  { "fixup_Mips_GPREL16", 0, 16, 0 },
249  { "fixup_Mips_LITERAL", 0, 16, 0 },
250  { "fixup_Mips_GOT_Global", 0, 16, 0 },
251  { "fixup_Mips_GOT_Local", 0, 16, 0 },
252  { "fixup_Mips_PC16", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
253  { "fixup_Mips_CALL16", 0, 16, 0 },
254  { "fixup_Mips_GPREL32", 0, 32, 0 },
255  { "fixup_Mips_SHIFT5", 6, 5, 0 },
256  { "fixup_Mips_SHIFT6", 6, 5, 0 },
257  { "fixup_Mips_64", 0, 64, 0 },
258  { "fixup_Mips_TLSGD", 0, 16, 0 },
259  { "fixup_Mips_GOTTPREL", 0, 16, 0 },
260  { "fixup_Mips_TPREL_HI", 0, 16, 0 },
261  { "fixup_Mips_TPREL_LO", 0, 16, 0 },
262  { "fixup_Mips_TLSLDM", 0, 16, 0 },
263  { "fixup_Mips_DTPREL_HI", 0, 16, 0 },
264  { "fixup_Mips_DTPREL_LO", 0, 16, 0 },
265  { "fixup_Mips_Branch_PCRel", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
266  { "fixup_Mips_GPOFF_HI", 0, 16, 0 },
267  { "fixup_Mips_GPOFF_LO", 0, 16, 0 },
268  { "fixup_Mips_GOT_PAGE", 0, 16, 0 },
269  { "fixup_Mips_GOT_OFST", 0, 16, 0 },
270  { "fixup_Mips_GOT_DISP", 0, 16, 0 },
271  { "fixup_Mips_HIGHER", 0, 16, 0 },
272  { "fixup_Mips_HIGHEST", 0, 16, 0 },
273  { "fixup_Mips_GOT_HI16", 0, 16, 0 },
274  { "fixup_Mips_GOT_LO16", 0, 16, 0 },
275  { "fixup_Mips_CALL_HI16", 0, 16, 0 },
276  { "fixup_Mips_CALL_LO16", 0, 16, 0 },
277  { "fixup_Mips_PC18_S3", 0, 18, MCFixupKindInfo::FKF_IsPCRel },
278  { "fixup_MIPS_PC19_S2", 0, 19, MCFixupKindInfo::FKF_IsPCRel },
279  { "fixup_MIPS_PC21_S2", 0, 21, MCFixupKindInfo::FKF_IsPCRel },
280  { "fixup_MIPS_PC26_S2", 0, 26, MCFixupKindInfo::FKF_IsPCRel },
281  { "fixup_MIPS_PCHI16", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
282  { "fixup_MIPS_PCLO16", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
283  { "fixup_MICROMIPS_26_S1", 0, 26, 0 },
284  { "fixup_MICROMIPS_HI16", 0, 16, 0 },
285  { "fixup_MICROMIPS_LO16", 0, 16, 0 },
286  { "fixup_MICROMIPS_GOT16", 0, 16, 0 },
287  { "fixup_MICROMIPS_PC7_S1", 0, 7, MCFixupKindInfo::FKF_IsPCRel },
288  { "fixup_MICROMIPS_PC10_S1", 0, 10, MCFixupKindInfo::FKF_IsPCRel },
289  { "fixup_MICROMIPS_PC16_S1", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
290  { "fixup_MICROMIPS_CALL16", 0, 16, 0 },
291  { "fixup_MICROMIPS_GOT_DISP", 0, 16, 0 },
292  { "fixup_MICROMIPS_GOT_PAGE", 0, 16, 0 },
293  { "fixup_MICROMIPS_GOT_OFST", 0, 16, 0 },
294  { "fixup_MICROMIPS_TLS_GD", 0, 16, 0 },
295  { "fixup_MICROMIPS_TLS_LDM", 0, 16, 0 },
296  { "fixup_MICROMIPS_TLS_DTPREL_HI16", 0, 16, 0 },
297  { "fixup_MICROMIPS_TLS_DTPREL_LO16", 0, 16, 0 },
298  { "fixup_MICROMIPS_TLS_TPREL_HI16", 0, 16, 0 },
299  { "fixup_MICROMIPS_TLS_TPREL_LO16", 0, 16, 0 }
300  };
301 
302  const static MCFixupKindInfo BigEndianInfos[Mips::NumTargetFixupKinds] = {
303  // This table *must* be in same the order of fixup_* kinds in
304  // MipsFixupKinds.h.
305  //
306  // name offset bits flags
307  { "fixup_Mips_16", 16, 16, 0 },
308  { "fixup_Mips_32", 0, 32, 0 },
309  { "fixup_Mips_REL32", 0, 32, 0 },
310  { "fixup_Mips_26", 6, 26, 0 },
311  { "fixup_Mips_HI16", 16, 16, 0 },
312  { "fixup_Mips_LO16", 16, 16, 0 },
313  { "fixup_Mips_GPREL16", 16, 16, 0 },
314  { "fixup_Mips_LITERAL", 16, 16, 0 },
315  { "fixup_Mips_GOT_Global", 16, 16, 0 },
316  { "fixup_Mips_GOT_Local", 16, 16, 0 },
317  { "fixup_Mips_PC16", 16, 16, MCFixupKindInfo::FKF_IsPCRel },
318  { "fixup_Mips_CALL16", 16, 16, 0 },
319  { "fixup_Mips_GPREL32", 0, 32, 0 },
320  { "fixup_Mips_SHIFT5", 21, 5, 0 },
321  { "fixup_Mips_SHIFT6", 21, 5, 0 },
322  { "fixup_Mips_64", 0, 64, 0 },
323  { "fixup_Mips_TLSGD", 16, 16, 0 },
324  { "fixup_Mips_GOTTPREL", 16, 16, 0 },
325  { "fixup_Mips_TPREL_HI", 16, 16, 0 },
326  { "fixup_Mips_TPREL_LO", 16, 16, 0 },
327  { "fixup_Mips_TLSLDM", 16, 16, 0 },
328  { "fixup_Mips_DTPREL_HI", 16, 16, 0 },
329  { "fixup_Mips_DTPREL_LO", 16, 16, 0 },
330  { "fixup_Mips_Branch_PCRel",16, 16, MCFixupKindInfo::FKF_IsPCRel },
331  { "fixup_Mips_GPOFF_HI", 16, 16, 0 },
332  { "fixup_Mips_GPOFF_LO", 16, 16, 0 },
333  { "fixup_Mips_GOT_PAGE", 16, 16, 0 },
334  { "fixup_Mips_GOT_OFST", 16, 16, 0 },
335  { "fixup_Mips_GOT_DISP", 16, 16, 0 },
336  { "fixup_Mips_HIGHER", 16, 16, 0 },
337  { "fixup_Mips_HIGHEST", 16, 16, 0 },
338  { "fixup_Mips_GOT_HI16", 16, 16, 0 },
339  { "fixup_Mips_GOT_LO16", 16, 16, 0 },
340  { "fixup_Mips_CALL_HI16", 16, 16, 0 },
341  { "fixup_Mips_CALL_LO16", 16, 16, 0 },
342  { "fixup_Mips_PC18_S3", 14, 18, MCFixupKindInfo::FKF_IsPCRel },
343  { "fixup_MIPS_PC19_S2", 13, 19, MCFixupKindInfo::FKF_IsPCRel },
344  { "fixup_MIPS_PC21_S2", 11, 21, MCFixupKindInfo::FKF_IsPCRel },
345  { "fixup_MIPS_PC26_S2", 6, 26, MCFixupKindInfo::FKF_IsPCRel },
346  { "fixup_MIPS_PCHI16", 16, 16, MCFixupKindInfo::FKF_IsPCRel },
347  { "fixup_MIPS_PCLO16", 16, 16, MCFixupKindInfo::FKF_IsPCRel },
348  { "fixup_MICROMIPS_26_S1", 6, 26, 0 },
349  { "fixup_MICROMIPS_HI16", 16, 16, 0 },
350  { "fixup_MICROMIPS_LO16", 16, 16, 0 },
351  { "fixup_MICROMIPS_GOT16", 16, 16, 0 },
352  { "fixup_MICROMIPS_PC7_S1", 9, 7, MCFixupKindInfo::FKF_IsPCRel },
353  { "fixup_MICROMIPS_PC10_S1", 6, 10, MCFixupKindInfo::FKF_IsPCRel },
354  { "fixup_MICROMIPS_PC16_S1",16, 16, MCFixupKindInfo::FKF_IsPCRel },
355  { "fixup_MICROMIPS_CALL16", 16, 16, 0 },
356  { "fixup_MICROMIPS_GOT_DISP", 16, 16, 0 },
357  { "fixup_MICROMIPS_GOT_PAGE", 16, 16, 0 },
358  { "fixup_MICROMIPS_GOT_OFST", 16, 16, 0 },
359  { "fixup_MICROMIPS_TLS_GD", 16, 16, 0 },
360  { "fixup_MICROMIPS_TLS_LDM", 16, 16, 0 },
361  { "fixup_MICROMIPS_TLS_DTPREL_HI16", 16, 16, 0 },
362  { "fixup_MICROMIPS_TLS_DTPREL_LO16", 16, 16, 0 },
363  { "fixup_MICROMIPS_TLS_TPREL_HI16", 16, 16, 0 },
364  { "fixup_MICROMIPS_TLS_TPREL_LO16", 16, 16, 0 }
365  };
366 
367  if (Kind < FirstTargetFixupKind)
368  return MCAsmBackend::getFixupKindInfo(Kind);
369 
370  assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
371  "Invalid kind!");
372 
373  if (IsLittle)
374  return LittleEndianInfos[Kind - FirstTargetFixupKind];
375  return BigEndianInfos[Kind - FirstTargetFixupKind];
376 }
377 
378 /// WriteNopData - Write an (optimal) nop sequence of Count bytes
379 /// to the given output. If the target cannot generate such a sequence,
380 /// it should return an error.
381 ///
382 /// \return - True on success.
383 bool MipsAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
384  // Check for a less than instruction size number of bytes
385  // FIXME: 16 bit instructions are not handled yet here.
386  // We shouldn't be using a hard coded number for instruction size.
387 
388  // If the count is not 4-byte aligned, we must be writing data into the text
389  // section (otherwise we have unaligned instructions, and thus have far
390  // bigger problems), so just write zeros instead.
391  OW->WriteZeros(Count);
392  return true;
393 }
394 
395 /// processFixupValue - Target hook to process the literal value of a fixup
396 /// if necessary.
398  const MCAsmLayout &Layout,
399  const MCFixup &Fixup,
400  const MCFragment *DF,
401  const MCValue &Target,
402  uint64_t &Value,
403  bool &IsResolved) {
404  // At this point we'll ignore the value returned by adjustFixupValue as
405  // we are only checking if the fixup can be applied correctly. We have
406  // access to MCContext from here which allows us to report a fatal error
407  // with *possibly* a source code location.
408  (void)adjustFixupValue(Fixup, Value, &Asm.getContext());
409 }
410 
411 // MCAsmBackend
413  const MCRegisterInfo &MRI,
414  const Triple &TT, StringRef CPU) {
415  return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ true,
416  /*Is64Bit*/ false);
417 }
418 
420  const MCRegisterInfo &MRI,
421  const Triple &TT, StringRef CPU) {
422  return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ false,
423  /*Is64Bit*/ false);
424 }
425 
427  const MCRegisterInfo &MRI,
428  const Triple &TT, StringRef CPU) {
429  return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ true, /*Is64Bit*/ true);
430 }
431 
433  const MCRegisterInfo &MRI,
434  const Triple &TT, StringRef CPU) {
435  return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ false,
436  /*Is64Bit*/ true);
437 }
OSType getOS() const
getOS - Get the parsed operating system type of this triple.
Definition: Triple.h:251
static bool needsMMLEByteOrder(unsigned Kind)
void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, uint64_t Value, bool IsPCRel) const override
ApplyFixup - Apply the Value for given Fixup into the provided data fragment, at the offset specified...
void WriteZeros(unsigned N)
SMLoc getLoc() const
Definition: MCFixup.h:108
This represents an "assembler immediate".
Definition: MCValue.h:44
static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value, MCContext *Ctx=nullptr)
MCAsmBackend * createMipsAsmBackendEL32(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU)
MCContext & getContext() const
Definition: MCAssembler.h:731
Defines the object file and target independent interfaces used by the assembler backend to write nati...
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:62
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...
void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout, const MCFixup &Fixup, const MCFragment *DF, const MCValue &Target, uint64_t &Value, bool &IsResolved) override
processFixupValue - Target hook to process the literal value of a fixup if necessary.
Encapsulates the layout of an assembly file at a particular point in time.
Definition: MCAsmLayout.h:29
const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const override
Get information on a fixup kind.
A four-byte fixup.
Definition: MCFixup.h:26
unsigned getNumFixupKinds() const override
Get the number of target specific fixup kinds.
Context object for machine code objects.
Definition: MCContext.h:48
A four-byte gp relative fixup.
Definition: MCFixup.h:34
bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override
WriteNopData - Write an (optimal) nop sequence of Count bytes to the given output.
MCAsmBackend * createMipsAsmBackendEB32(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU)
uint32_t getOffset() const
Definition: MCFixup.h:91
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
MCObjectWriter * createObjectWriter(raw_pwrite_stream &OS) const override
Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file...
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:23
bool isIntN(unsigned N, int64_t x)
isIntN - Checks if an signed integer fits into the given (dynamic) bit width.
Definition: MathExtras.h:321
MCFixupKind getKind() const
Definition: MCFixup.h:89
MCObjectWriter * createMipsELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI, bool IsLittleEndian, bool Is64Bit)
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
PowerPC TLS Dynamic Call Fixup
unsigned TargetSize
The number of bits written by this fixup.
MCAsmBackend * createMipsAsmBackendEL64(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU)
Target - Wrapper for Target specific information.
MCAsmBackend * createMipsAsmBackendEB64(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU)
A eight-byte fixup.
Definition: MCFixup.h:27
Target independent information on a fixup kind.
An abstract base class for streams implementations that also support a pwrite operation.
Definition: raw_ostream.h:321
const ARM::ArchExtKind Kind
LLVM Value Representation.
Definition: Value.h:69
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:34
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:40
static unsigned calculateMMLEIndex(unsigned i)
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
A two-byte fixup.
Definition: MCFixup.h:25