14 #ifndef LLVM_LIB_CODEGEN_SELECTIONDAG_SELECTIONDAGBUILDER_H
15 #define LLVM_LIB_CODEGEN_SELECTIONDAG_SELECTIONDAGBUILDER_H
32 class AddrSpaceCastInst;
40 class ExtractElementInst;
41 class ExtractValueInst;
48 class FunctionLoweringInfo;
49 class GetElementPtrInst;
55 class InsertElementInst;
56 class InsertValueInst;
59 class MachineBasicBlock;
61 class MachineRegisterInfo;
70 class ShuffleVectorInst;
75 class TargetLibraryInfo;
79 class UnreachableInst;
98 class DanglingDebugInfo {
101 unsigned SDNodeOrder;
103 DanglingDebugInfo() :
DI(
nullptr), dl(
DebugLoc()), SDNodeOrder(0) { }
105 DI(di), dl(DL), SDNodeOrder(SDNO) { }
136 unsigned SDNodeOrder;
138 enum CaseClusterKind {
150 CaseClusterKind
Kind;
154 unsigned JTCasesIndex;
155 unsigned BTCasesIndex;
159 static CaseCluster range(
const ConstantInt *Low,
const ConstantInt *High,
160 MachineBasicBlock *MBB, uint32_t Weight) {
170 static CaseCluster jumpTable(
const ConstantInt *Low,
171 const ConstantInt *High,
unsigned JTCasesIndex,
174 C.Kind = CC_JumpTable;
177 C.JTCasesIndex = JTCasesIndex;
182 static CaseCluster bitTests(
const ConstantInt *Low,
const ConstantInt *High,
183 unsigned BTCasesIndex, uint32_t Weight) {
185 C.Kind = CC_BitTests;
188 C.BTCasesIndex = BTCasesIndex;
194 typedef std::vector<CaseCluster> CaseClusterVector;
195 typedef CaseClusterVector::iterator CaseClusterIt;
199 MachineBasicBlock* BB;
201 uint32_t ExtraWeight;
203 CaseBits(uint64_t mask, MachineBasicBlock* bb,
unsigned bits,
205 Mask(mask), BB(bb),
Bits(bits), ExtraWeight(Weight) { }
207 CaseBits() : Mask(0), BB(nullptr),
Bits(0), ExtraWeight(0) {}
210 typedef std::vector<CaseBits> CaseBitsVector;
213 void sortAndRangeify(CaseClusterVector &Clusters);
219 CaseBlock(
ISD::CondCode cc,
const Value *cmplhs,
const Value *cmprhs,
220 const Value *cmpmiddle,
221 MachineBasicBlock *truebb, MachineBasicBlock *falsebb,
222 MachineBasicBlock *me,
223 uint32_t trueweight = 0, uint32_t falseweight = 0)
224 : CC(cc), CmpLHS(cmplhs), CmpMHS(cmpmiddle), CmpRHS(cmprhs),
225 TrueBB(truebb), FalseBB(falsebb), ThisBB(me),
226 TrueWeight(trueweight), FalseWeight(falseweight) { }
234 const Value *CmpLHS, *CmpMHS, *CmpRHS;
237 MachineBasicBlock *TrueBB, *FalseBB;
240 MachineBasicBlock *ThisBB;
243 uint32_t TrueWeight, FalseWeight;
247 JumpTable(
unsigned R,
unsigned J, MachineBasicBlock *M,
248 MachineBasicBlock *D):
Reg(R), JTI(J), MBB(M),
Default(D) {}
256 MachineBasicBlock *MBB;
261 struct JumpTableHeader {
262 JumpTableHeader(APInt
F, APInt L,
const Value *SV, MachineBasicBlock *
H,
264 First(F),
Last(L), SValue(SV), HeaderBB(H), Emitted(E) {}
268 MachineBasicBlock *HeaderBB;
271 typedef std::pair<JumpTableHeader, JumpTable> JumpTableBlock;
274 BitTestCase(uint64_t M, MachineBasicBlock*
T, MachineBasicBlock* Tr,
276 Mask(M), ThisBB(T), TargetBB(Tr), ExtraWeight(Weight) { }
278 MachineBasicBlock *ThisBB;
279 MachineBasicBlock *TargetBB;
280 uint32_t ExtraWeight;
283 typedef SmallVector<BitTestCase, 3> BitTestInfo;
285 struct BitTestBlock {
286 BitTestBlock(APInt
F, APInt R,
const Value* SV,
287 unsigned Rg, MVT RgVT,
bool E,
288 MachineBasicBlock*
P, MachineBasicBlock* D,
290 First(F), Range(R), SValue(SV),
Reg(Rg), RegVT(RgVT), Emitted(E),
291 Parent(P),
Default(D), Cases(std::move(C)) { }
298 MachineBasicBlock *Parent;
304 enum { MinJumpTableDensity = 40 };
307 bool isDense(
const CaseClusterVector &Clusters,
unsigned *TotalCases,
308 unsigned First,
unsigned Last);
312 bool buildJumpTable(CaseClusterVector &Clusters,
unsigned First,
313 unsigned Last,
const SwitchInst *
SI,
314 MachineBasicBlock *DefaultMBB, CaseCluster &JTCluster);
317 void findJumpTables(CaseClusterVector &Clusters,
const SwitchInst *
SI,
318 MachineBasicBlock *DefaultMBB);
321 bool rangeFitsInWord(
const APInt &Low,
const APInt &High);
325 bool isSuitableForBitTests(
unsigned NumDests,
unsigned NumCmps,
326 const APInt &Low,
const APInt &High);
330 bool buildBitTests(CaseClusterVector &Clusters,
unsigned First,
unsigned Last,
331 const SwitchInst *
SI, CaseCluster &BTCluster);
334 void findBitTestClusters(CaseClusterVector &Clusters,
const SwitchInst *
SI);
336 struct SwitchWorkListItem {
337 MachineBasicBlock *MBB;
338 CaseClusterIt FirstCluster;
339 CaseClusterIt LastCluster;
340 const ConstantInt *
GE;
341 const ConstantInt *
LT;
343 typedef SmallVector<SwitchWorkListItem, 4> SwitchWorkList;
347 static unsigned caseClusterRank(
const CaseCluster &CC, CaseClusterIt First,
351 void splitWorkItem(SwitchWorkList &WorkList,
const SwitchWorkListItem &W,
352 Value *Cond, MachineBasicBlock *SwitchMBB);
355 void lowerWorkItem(SwitchWorkListItem W, Value *Cond,
356 MachineBasicBlock *SwitchMBB,
357 MachineBasicBlock *DefaultMBB);
464 class StackProtectorDescriptor {
466 StackProtectorDescriptor() : ParentMBB(nullptr), SuccessMBB(nullptr),
467 FailureMBB(nullptr), Guard(nullptr),
472 bool shouldEmitStackProtector()
const {
473 return ParentMBB && SuccessMBB && FailureMBB && Guard;
479 MachineBasicBlock *MBB,
480 const CallInst &StackProtCheckCall) {
482 assert(!shouldEmitStackProtector() &&
"Stack Protector Descriptor is "
483 "already initialized!");
485 SuccessMBB = AddSuccessorMBB(BB, MBB,
true);
486 FailureMBB = AddSuccessorMBB(BB, MBB,
false, FailureMBB);
488 Guard = StackProtCheckCall.getArgOperand(0);
501 void resetPerBBState() {
503 SuccessMBB =
nullptr;
515 void resetPerFunctionState() {
516 FailureMBB =
nullptr;
520 MachineBasicBlock *getParentMBB() {
return ParentMBB; }
521 MachineBasicBlock *getSuccessMBB() {
return SuccessMBB; }
522 MachineBasicBlock *getFailureMBB() {
return FailureMBB; }
523 const Value *getGuard() {
return Guard; }
525 unsigned getGuardReg()
const {
return GuardReg; }
526 void setGuardReg(
unsigned R) { GuardReg = R; }
536 MachineBasicBlock *ParentMBB;
540 MachineBasicBlock *SuccessMBB;
544 MachineBasicBlock *FailureMBB;
556 MachineBasicBlock *AddSuccessorMBB(
const BasicBlock *BB,
557 MachineBasicBlock *ParentMBB,
559 MachineBasicBlock *SuccMBB =
nullptr);
563 const TargetMachine &TM;
653 return SDLoc(CurInst, SDNodeOrder);
683 assert(!N.
getNode() &&
"Already set a value for this node!");
689 assert(!N.
getNode() &&
"Already set a value for this node!");
696 uint32_t TW, uint32_t FW);
701 uint32_t TW, uint32_t FW);
716 bool IsPatchPoint =
false);
727 std::pair<SDValue, SDValue> lowerInvokable(
741 uint32_t Weight = 0);
751 uint32_t BranchWeightToNext,
764 void visitBinary(
const User &
I,
unsigned OpCode);
765 void visitShift(
const User &
I,
unsigned Opcode);
767 void visitFAdd(
const User &
I) { visitBinary(I,
ISD::FADD); }
768 void visitSub(
const User &
I) { visitBinary(I,
ISD::SUB); }
769 void visitFSub(
const User &
I);
770 void visitMul(
const User &
I) { visitBinary(I,
ISD::MUL); }
771 void visitFMul(
const User &
I) { visitBinary(I,
ISD::FMUL); }
772 void visitURem(
const User &
I) { visitBinary(I,
ISD::UREM); }
773 void visitSRem(
const User &
I) { visitBinary(I,
ISD::SREM); }
774 void visitFRem(
const User &
I) { visitBinary(I,
ISD::FREM); }
775 void visitUDiv(
const User &
I) { visitBinary(I,
ISD::UDIV); }
776 void visitSDiv(
const User &
I);
777 void visitFDiv(
const User &
I) { visitBinary(I,
ISD::FDIV); }
778 void visitAnd (
const User &
I) { visitBinary(I,
ISD::AND); }
779 void visitOr (
const User &
I) { visitBinary(I,
ISD::OR); }
780 void visitXor (
const User &
I) { visitBinary(I,
ISD::XOR); }
781 void visitShl (
const User &
I) { visitShift(I,
ISD::SHL); }
782 void visitLShr(
const User &
I) { visitShift(I,
ISD::SRL); }
783 void visitAShr(
const User &
I) { visitShift(I,
ISD::SRA); }
784 void visitICmp(
const User &
I);
785 void visitFCmp(
const User &
I);
787 void visitTrunc(
const User &
I);
788 void visitZExt(
const User &
I);
789 void visitSExt(
const User &
I);
790 void visitFPTrunc(
const User &
I);
791 void visitFPExt(
const User &
I);
792 void visitFPToUI(
const User &
I);
793 void visitFPToSI(
const User &
I);
794 void visitUIToFP(
const User &
I);
795 void visitSIToFP(
const User &
I);
796 void visitPtrToInt(
const User &
I);
797 void visitIntToPtr(
const User &
I);
798 void visitBitCast(
const User &
I);
799 void visitAddrSpaceCast(
const User &
I);
801 void visitExtractElement(
const User &
I);
802 void visitInsertElement(
const User &
I);
803 void visitShuffleVector(
const User &
I);
805 void visitExtractValue(
const ExtractValueInst &
I);
806 void visitInsertValue(
const InsertValueInst &
I);
807 void visitLandingPad(
const LandingPadInst &
I);
809 void visitGetElementPtr(
const User &
I);
810 void visitSelect(
const User &
I);
812 void visitAlloca(
const AllocaInst &
I);
813 void visitLoad(
const LoadInst &
I);
814 void visitStore(
const StoreInst &
I);
815 void visitMaskedLoad(
const CallInst &
I);
816 void visitMaskedStore(
const CallInst &
I);
817 void visitMaskedGather(
const CallInst &
I);
818 void visitMaskedScatter(
const CallInst &
I);
819 void visitAtomicCmpXchg(
const AtomicCmpXchgInst &
I);
820 void visitAtomicRMW(
const AtomicRMWInst &
I);
821 void visitFence(
const FenceInst &
I);
822 void visitPHI(
const PHINode &
I);
823 void visitCall(
const CallInst &
I);
824 bool visitMemCmpCall(
const CallInst &
I);
825 bool visitMemChrCall(
const CallInst &
I);
826 bool visitStrCpyCall(
const CallInst &
I,
bool isStpcpy);
827 bool visitStrCmpCall(
const CallInst &
I);
828 bool visitStrLenCall(
const CallInst &
I);
829 bool visitStrNLenCall(
const CallInst &
I);
830 bool visitUnaryFloatCall(
const CallInst &
I,
unsigned Opcode);
831 bool visitBinaryFloatCall(
const CallInst &
I,
unsigned Opcode);
832 void visitAtomicLoad(
const LoadInst &
I);
833 void visitAtomicStore(
const StoreInst &
I);
835 void visitInlineAsm(ImmutableCallSite
CS);
836 const char *visitIntrinsicCall(
const CallInst &
I,
unsigned Intrinsic);
837 void visitTargetIntrinsic(
const CallInst &
I,
unsigned Intrinsic);
839 void visitVAStart(
const CallInst &
I);
840 void visitVAArg(
const VAArgInst &
I);
841 void visitVAEnd(
const CallInst &
I);
842 void visitVACopy(
const CallInst &
I);
843 void visitStackmap(
const CallInst &
I);
844 void visitPatchpoint(ImmutableCallSite
CS,
845 MachineBasicBlock *LandingPad =
nullptr);
848 void visitStatepoint(
const CallInst &
I);
849 void visitGCRelocate(
const CallInst &
I);
850 void visitGCResult(
const CallInst &
I);
852 void visitUserOp1(
const Instruction &
I) {
853 llvm_unreachable(
"UserOp1 should not exist at instruction selection time!");
855 void visitUserOp2(
const Instruction &
I) {
856 llvm_unreachable(
"UserOp2 should not exist at instruction selection time!");
859 void processIntegerCallValue(
const Instruction &
I,
860 SDValue Value,
bool IsSigned);
862 void HandlePHINodesInSuccessorBlocks(
const BasicBlock *LLVMBB);
867 bool EmitFuncArgumentDbgValue(
const Value *V, DILocalVariable *Variable,
868 DIExpression *Expr, DILocation *
DL,
869 int64_t Offset,
bool IsIndirect,
873 MachineBasicBlock *NextBlock(MachineBasicBlock *MBB);
877 void updateDAGForMaybeTailCall(SDValue MaybeTC);
933 const Value *V =
nullptr)
const;
949 bool HasMatching,
unsigned MatchingIdx,
SDLoc dl,
951 std::vector<SDValue> &Ops)
const;
ReturnInst - Return a value (possibly void), from a function.
std::vector< BitTestBlock > BitTestCases
BitTestCases - Vector of BitTestBlock structures used to communicate SwitchInst code generation infor...
A parsed version of the target data layout string in and methods for querying it. ...
bool findValue(const Value *V) const
void ExportFromCurrentBlock(const Value *V)
ExportFromCurrentBlock - If this condition isn't known to be exported from the current basic block...
const TargetLibraryInfo * LibInfo
void LowerStatepoint(ImmutableStatepoint Statepoint, MachineBasicBlock *LandingPad=nullptr)
void CopyValueToVirtualRegister(const Value *V, unsigned Reg)
SelectionDAGBuilder - This is the common target-independent lowering implementation that is parameter...
A specialization of it's base class for read only access to a gc.statepoint.
SelectionDAGBuilder(SelectionDAG &dag, FunctionLoweringInfo &funcinfo, CodeGenOpt::Level ol)
void setValue(const Value *V, SDValue NewN)
void visitJumpTableHeader(JumpTable &JT, JumpTableHeader &JTH, MachineBasicBlock *SwitchBB)
visitJumpTableHeader - This function emits necessary code to produce index in the JumpTable from swit...
SDValue getValueImpl(const Value *V)
getValueImpl - Helper function for getValue and getNonRegisterValue.
DebugLoc getCurDebugLoc() const
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
void FindMergedConditions(const Value *Cond, MachineBasicBlock *TBB, MachineBasicBlock *FBB, MachineBasicBlock *CurBB, MachineBasicBlock *SwitchBB, unsigned Opc, uint32_t TW, uint32_t FW)
FindMergedConditions - If Cond is an expression like.
SDValue getValue(const Value *V)
getValue - Return an SDValue for the given Value.
StackProtectorDescriptor SPDescriptor
A StackProtectorDescriptor structure used to communicate stack protector information in between Selec...
void visitSPDescriptorParent(StackProtectorDescriptor &SPD, MachineBasicBlock *ParentBB)
Codegen a new tail for a stack protector check ParentMBB which has had its tail spliced into a stack ...
SDValue getRoot()
getRoot - Return the current virtual root of the Selection DAG, flushing any PendingLoad items...
unsigned getSDNodeOrder() const
void visitSwitchCase(CaseBlock &CB, MachineBasicBlock *SwitchBB)
visitSwitchCase - Emits the necessary code to represent a single node in the binary search tree resul...
Shift and rotation operations.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void visitJumpTable(JumpTable &JT)
visitJumpTable - Emit JumpTable node in the current MBB
SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, SDLoc dl, SDValue &Chain, SDValue *Flag, const Value *V=nullptr) const
getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from this value and returns the resu...
SmallVector< EVT, 4 > ValueVTs
ValueVTs - The value types of the values, which may not be legal, and may need be promoted or synthes...
Reg
All possible values of the reg field in the ModR/M byte.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This file implements a class to represent arbitrary precision integral constant values and operations...
Simple integer binary arithmetic operators.
SDValue getNonRegisterValue(const Value *V)
getNonRegisterValue - Return an SDValue for the given Value, but don't look in FuncInfo.ValueMap for a virtual register.
bool ShouldEmitAsBranches(const std::vector< CaseBlock > &Cases)
If the set of cases should be emitted as a series of branches, return true.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
void append(const RegsForValue &RHS)
append - Add the specified values to this one.
Flag
These should be considered private to the implementation of the MCInstrDesc class.
SDNode * getNode() const
get the SDNode which holds the desired result
bool HasTailCall
HasTailCall - This is set to true if a call in the current block has been translated as a tail call...
MVT - Machine Value Type.
LLVM Basic Block Representation.
The instances of the Type class are immutable: once they are created, they are never changed...
This is an important class for using LLVM in a threaded context.
void AddInlineAsmOperands(unsigned Kind, bool HasMatching, unsigned MatchingIdx, SDLoc dl, SelectionDAG &DAG, std::vector< SDValue > &Ops) const
AddInlineAsmOperands - Add this value to the specified inlineasm node operand list.
Simple binary floating point operators.
BranchInst - Conditional or Unconditional Branch instruction.
UnreachableInst - This function has undefined behavior.
ResumeInst - Resume the propagation of an exception.
This file contains the declarations for the subclasses of Constant, which represent the different fla...
IndirectBrInst - Indirect Branch Instruction.
void LowerCallTo(ImmutableCallSite CS, SDValue Callee, bool IsTailCall, MachineBasicBlock *LandingPad=nullptr)
const DebugLoc & getDebugLoc() const
getDebugLoc - Return the debug location for this node as a DebugLoc.
void visitBitTestCase(BitTestBlock &BB, MachineBasicBlock *NextMBB, uint32_t BranchWeightToNext, unsigned Reg, BitTestCase &B, MachineBasicBlock *SwitchBB)
visitBitTestCase - this function produces one "bit test"
void getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl, SDValue &Chain, SDValue *Flag, const Value *V=nullptr, ISD::NodeType PreferredExtendType=ISD::ANY_EXTEND) const
getCopyToRegs - Emit a series of CopyToReg nodes that copies the specified value into the registers s...
This class tracks both per-statepoint and per-selectiondag information.
A specialization of it's base class for read-write access to a gc.statepoint.
SDLoc getCurSDLoc() const
void append(in_iter in_start, in_iter in_end)
Add the specified range to the end of the SmallVector.
EVT - Extended Value Type.
static void initialize(TargetLibraryInfoImpl &TLI, const Triple &T, const char *const *StandardNames)
initialize - Initialize the set of available library functions based on the specified target triple...
void EmitBranchForMergedCondition(const Value *Cond, MachineBasicBlock *TBB, MachineBasicBlock *FBB, MachineBasicBlock *CurBB, MachineBasicBlock *SwitchBB, uint32_t TW, uint32_t FW)
EmitBranchForMergedCondition - Helper method for FindMergedConditions.
This structure contains all information that is necessary for lowering calls.
CodeGenOpt::Level OptLevel
OptLevel - What optimization level we're generating code for.
void CopyToExportRegsIfNeeded(const Value *V)
CopyToExportRegsIfNeeded - If the given value has virtual registers created for it, emit nodes to copy the value into the virtual registers.
void visitSPDescriptorFailure(StackProtectorDescriptor &SPD)
Codegen the failure basic block for a stack protector check.
This is the shared class of boolean and integer constants.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
RegsForValue - This struct represents the registers (physical or virtual) that a particular set of va...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Provides information about what library functions are available for the current target.
void clear()
clear - Clear out the current SelectionDAG and the associated state and prepare this SelectionDAGBuil...
void visit(const Instruction &I)
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
void UpdateSplitBlock(MachineBasicBlock *First, MachineBasicBlock *Last)
UpdateSplitBlock - When an MBB was split during scheduling, update the references that need to refer ...
GCFunctionInfo * GFI
GFI - Garbage collection metadata for the function.
std::vector< JumpTableBlock > JTCases
JTCases - Vector of JumpTable structures used to communicate SwitchInst code generation information...
ANY_EXTEND - Used for integer types. The high bits are undefined.
SmallVector< SDValue, 8 > PendingLoads
PendingLoads - Loads are not emitted to the program immediately.
Bitwise operators - logical and, logical or, logical xor.
DbgValueInst - This represents the llvm.dbg.value instruction.
ImmutableCallSite - establish a view to a call site for examination.
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
std::pair< SDValue, SDValue > lowerCallOperands(ImmutableCallSite CS, unsigned ArgIdx, unsigned NumArgs, SDValue Callee, Type *ReturnTy, MachineBasicBlock *LandingPad=nullptr, bool IsPatchPoint=false)
Lower an argument list according to the target calling convention.
StatepointLoweringState StatepointLowering
State used while lowering a statepoint sequence (gc_statepoint, gc_relocate, and gc_result).
SDValue getCopyFromRegs(const Value *V, Type *Ty)
getCopyFromRegs - If there was virtual register allocated for the value V emit CopyFromReg of the spe...
SwitchInst - Multiway switch.
FunctionLoweringInfo & FuncInfo
FuncInfo - Information about the function as a whole.
SmallVector< MVT, 4 > RegVTs
RegVTs - The value types of the registers.
const ARM::ArchExtKind Kind
void setUnusedArgValue(const Value *V, SDValue NewN)
LLVM Value Representation.
void init(GCFunctionInfo *gfi, AliasAnalysis &aa, const TargetLibraryInfo *li)
InvokeInst - Invoke instruction.
std::vector< CaseBlock > SwitchCases
SwitchCases - Vector of CaseBlock structures used to communicate SwitchInst code generation informati...
SDValue getControlRoot()
getControlRoot - Similar to getRoot, but instead of flushing all the PendingLoad items, flush all the PendingExports items.
Garbage collection metadata for a single function.
void clearDanglingDebugInfo()
clearDanglingDebugInfo - Clear the dangling debug information map.
DenseMap< MachineBasicBlock *, SmallVector< unsigned, 4 > > LPadToCallSiteMap
LPadToCallSiteMap - Map a landing pad to the call site indexes.
DenseMap< const Constant *, unsigned > ConstantsOut
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
bool isExportableFromCurrentBlock(const Value *V, const BasicBlock *FromBB)
SmallVector< unsigned, 4 > Regs
Regs - This list holds the registers assigned to the values.
void visitBitTestHeader(BitTestBlock &B, MachineBasicBlock *SwitchBB)
visitBitTestHeader - This function emits necessary code to produce value suitable for "bit tests" ...
static const unsigned LowestSDNodeOrder
Lowest valid SDNodeOrder.
void resolveDanglingDebugInfo(const Value *V, SDValue Val)
This file describes how to lower LLVM code to machine code.