LLVM  3.7.0
MipsISelLowering.h
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1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
16 #define LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
17 
20 #include "Mips.h"
23 #include "llvm/IR/Function.h"
25 #include <deque>
26 #include <string>
27 
28 namespace llvm {
29  namespace MipsISD {
30  enum NodeType : unsigned {
31  // Start the numbering from where ISD NodeType finishes.
33 
34  // Jump and link (call)
36 
37  // Tail call
39 
40  // Get the Higher 16 bits from a 32-bit immediate
41  // No relation with Mips Hi register
42  Hi,
43 
44  // Get the Lower 16 bits from a 32-bit immediate
45  // No relation with Mips Lo register
46  Lo,
47 
48  // Handle gp_rel (small data/bss sections) relocation.
50 
51  // Thread Pointer
53 
54  // Floating Point Branch Conditional
56 
57  // Floating Point Compare
59 
60  // Floating Point Conditional Moves
63 
64  // FP-to-int truncation node.
66 
67  // Return
68  Ret,
69 
71 
72  // Node used to extract integer from accumulator.
75 
76  // Node used to insert integers to accumulator.
78 
79  // Mult nodes.
82 
83  // MAdd/Sub nodes
88 
89  // DivRem(u)
94 
97 
99 
101 
103 
106 
107  // EXTR.W instrinsic nodes.
116 
117  // DPA.W intrinsic nodes.
140 
147 
148  // DSP shift nodes.
152 
153  // DSP setcc and select_cc nodes.
156 
157  // Vector comparisons.
158  // These take a vector and return a boolean.
163 
164  // These take a vector and return a vector bitmask.
170 
171  // Element-wise vector max/min.
176 
177  // Vector Shuffle with mask as an operand
178  VSHF, // Generic shuffle
179  SHF, // 4-element set shuffle.
180  ILVEV, // Interleave even elements
181  ILVOD, // Interleave odd elements
182  ILVL, // Interleave left elements
183  ILVR, // Interleave right elements
184  PCKEV, // Pack even elements
185  PCKOD, // Pack odd elements
186 
187  // Vector Lane Copy
188  INSVE, // Copy element from one vector to another
189 
190  // Combined (XOR (OR $a, $b), -1)
192 
193  // Extended vector element extraction
196 
197  // Load/Store Left/Right nodes.
206  };
207  }
208 
209  //===--------------------------------------------------------------------===//
210  // TargetLowering Implementation
211  //===--------------------------------------------------------------------===//
212  class MipsFunctionInfo;
213  class MipsSubtarget;
214  class MipsCCState;
215 
217  bool isMicroMips;
218  public:
219  explicit MipsTargetLowering(const MipsTargetMachine &TM,
220  const MipsSubtarget &STI);
221 
222  static const MipsTargetLowering *create(const MipsTargetMachine &TM,
223  const MipsSubtarget &STI);
224 
225  /// createFastISel - This method returns a target specific FastISel object,
226  /// or null if the target does not support "fast" ISel.
228  const TargetLibraryInfo *libInfo) const override;
229 
230  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
231  return MVT::i32;
232  }
233 
235  SmallVectorImpl<SDValue> &Results,
236  SelectionDAG &DAG) const override;
237 
238  /// LowerOperation - Provide custom lowering hooks for some operations.
239  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
240 
241  /// ReplaceNodeResults - Replace the results of node with an illegal result
242  /// type with new values built out of custom code.
243  ///
245  SelectionDAG &DAG) const override;
246 
247  /// getTargetNodeName - This method returns the name of a target specific
248  // DAG node.
249  const char *getTargetNodeName(unsigned Opcode) const override;
250 
251  /// getSetCCResultType - get the ISD::SETCC result ValueType
253  EVT VT) const override;
254 
255  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
256 
259  MachineBasicBlock *MBB) const override;
260 
261  struct LTStr {
262  bool operator()(const char *S1, const char *S2) const {
263  return strcmp(S1, S2) < 0;
264  }
265  };
266 
267  void HandleByVal(CCState *, unsigned &, unsigned) const override;
268 
269  unsigned getRegisterByName(const char* RegName, EVT VT,
270  SelectionDAG &DAG) const override;
271 
272  protected:
273  SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
274 
275  // This method creates the following nodes, which are necessary for
276  // computing a local symbol's address:
277  //
278  // (add (load (wrapper $gp, %got(sym)), %lo(sym))
279  template <class NodeTy>
281  bool IsN32OrN64) const {
282  unsigned GOTFlag = IsN32OrN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
283  SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
284  getTargetNode(N, Ty, DAG, GOTFlag));
285  SDValue Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
286  MachinePointerInfo::getGOT(), false, false,
287  false, 0);
288  unsigned LoFlag = IsN32OrN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
289  SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty,
290  getTargetNode(N, Ty, DAG, LoFlag));
291  return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
292  }
293 
294  // This method creates the following nodes, which are necessary for
295  // computing a global symbol's address:
296  //
297  // (load (wrapper $gp, %got(sym)))
298  template <class NodeTy>
300  unsigned Flag, SDValue Chain,
301  const MachinePointerInfo &PtrInfo) const {
302  SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
303  getTargetNode(N, Ty, DAG, Flag));
304  return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo, false, false, false, 0);
305  }
306 
307  // This method creates the following nodes, which are necessary for
308  // computing a global symbol's address in large-GOT mode:
309  //
310  // (load (wrapper (add %hi(sym), $gp), %lo(sym)))
311  template <class NodeTy>
313  SelectionDAG &DAG, unsigned HiFlag,
314  unsigned LoFlag, SDValue Chain,
315  const MachinePointerInfo &PtrInfo) const {
316  SDValue Hi =
317  DAG.getNode(MipsISD::Hi, DL, Ty, getTargetNode(N, Ty, DAG, HiFlag));
318  Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
319  SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
320  getTargetNode(N, Ty, DAG, LoFlag));
321  return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo, false, false, false,
322  0);
323  }
324 
325  // This method creates the following nodes, which are necessary for
326  // computing a symbol's address in non-PIC mode:
327  //
328  // (add %hi(sym), %lo(sym))
329  template <class NodeTy>
331  SelectionDAG &DAG) const {
332  SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
333  SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
334  return DAG.getNode(ISD::ADD, DL, Ty,
335  DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
336  DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
337  }
338 
339  // This method creates the following nodes, which are necessary for
340  // computing a symbol's address using gp-relative addressing:
341  //
342  // (add $gp, %gp_rel(sym))
343  template <class NodeTy>
344  SDValue getAddrGPRel(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG) const {
345  assert(Ty == MVT::i32);
346  SDValue GPRel = getTargetNode(N, Ty, DAG, MipsII::MO_GPREL);
347  return DAG.getNode(ISD::ADD, DL, Ty,
348  DAG.getRegister(Mips::GP, Ty),
349  DAG.getNode(MipsISD::GPRel, DL, DAG.getVTList(Ty),
350  GPRel));
351  }
352 
353  /// This function fills Ops, which is the list of operands that will later
354  /// be used when a function call node is created. It also generates
355  /// copyToReg nodes to set up argument registers.
356  virtual void
358  std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
359  bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
360  bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
361  SDValue Chain) const;
362 
363  protected:
364  SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
365  SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
366 
367  // Subtarget Info
369  // Cache the ABI from the TargetMachine, we use it everywhere.
370  const MipsABIInfo &ABI;
371 
372  private:
373  // Create a TargetGlobalAddress node.
374  SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
375  unsigned Flag) const;
376 
377  // Create a TargetExternalSymbol node.
378  SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG,
379  unsigned Flag) const;
380 
381  // Create a TargetBlockAddress node.
382  SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
383  unsigned Flag) const;
384 
385  // Create a TargetJumpTable node.
386  SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
387  unsigned Flag) const;
388 
389  // Create a TargetConstantPool node.
390  SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
391  unsigned Flag) const;
392 
393  // Lower Operand helpers
394  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
395  CallingConv::ID CallConv, bool isVarArg,
399 
400  // Lower Operand specifics
401  SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
402  SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
403  SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
404  SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
405  SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
406  SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
407  SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
408  SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
409  SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
410  SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
411  SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
412  SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const;
413  SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
414  SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
415  SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
416  SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
417  SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
418  SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
419  SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
420  SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
421  bool IsSRA) const;
422  SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const;
423  SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
424 
425  /// isEligibleForTailCallOptimization - Check whether the call is eligible
426  /// for tail call optimization.
427  virtual bool
428  isEligibleForTailCallOptimization(const CCState &CCInfo,
429  unsigned NextStackOffset,
430  const MipsFunctionInfo &FI) const = 0;
431 
432  /// copyByValArg - Copy argument registers which were used to pass a byval
433  /// argument to the stack. Create a stack frame object for the byval
434  /// argument.
435  void copyByValRegs(SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains,
436  SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,
437  SmallVectorImpl<SDValue> &InVals,
438  const Argument *FuncArg, unsigned FirstReg,
439  unsigned LastReg, const CCValAssign &VA,
440  MipsCCState &State) const;
441 
442  /// passByValArg - Pass a byval argument in registers or on stack.
443  void passByValArg(SDValue Chain, SDLoc DL,
444  std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
445  SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
446  MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
447  unsigned FirstReg, unsigned LastReg,
448  const ISD::ArgFlagsTy &Flags, bool isLittle,
449  const CCValAssign &VA) const;
450 
451  /// writeVarArgRegs - Write variable function arguments passed in registers
452  /// to the stack. Also create a stack frame object for the first variable
453  /// argument.
454  void writeVarArgRegs(std::vector<SDValue> &OutChains, SDValue Chain,
455  SDLoc DL, SelectionDAG &DAG, CCState &State) const;
456 
457  SDValue
458  LowerFormalArguments(SDValue Chain,
459  CallingConv::ID CallConv, bool isVarArg,
461  SDLoc dl, SelectionDAG &DAG,
462  SmallVectorImpl<SDValue> &InVals) const override;
463 
464  SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
465  SDValue Arg, SDLoc DL, bool IsTailCall,
466  SelectionDAG &DAG) const;
467 
469  SmallVectorImpl<SDValue> &InVals) const override;
470 
471  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
472  bool isVarArg,
474  LLVMContext &Context) const override;
475 
476  SDValue LowerReturn(SDValue Chain,
477  CallingConv::ID CallConv, bool isVarArg,
479  const SmallVectorImpl<SDValue> &OutVals,
480  SDLoc dl, SelectionDAG &DAG) const override;
481 
482  bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override;
483 
484  // Inline asm support
485  ConstraintType getConstraintType(StringRef Constraint) const override;
486 
487  /// Examine constraint string and operand type and determine a weight value.
488  /// The operand object must already have been set up with the operand type.
489  ConstraintWeight getSingleConstraintMatchWeight(
490  AsmOperandInfo &info, const char *constraint) const override;
491 
492  /// This function parses registers that appear in inline-asm constraints.
493  /// It returns pair (0, 0) on failure.
494  std::pair<unsigned, const TargetRegisterClass *>
495  parseRegForInlineAsmConstraint(StringRef C, MVT VT) const;
496 
497  std::pair<unsigned, const TargetRegisterClass *>
498  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
499  StringRef Constraint, MVT VT) const override;
500 
501  /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
502  /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
503  /// true it means one of the asm constraint of the inline asm instruction
504  /// being processed is 'm'.
505  void LowerAsmOperandForConstraint(SDValue Op,
506  std::string &Constraint,
507  std::vector<SDValue> &Ops,
508  SelectionDAG &DAG) const override;
509 
510  unsigned
511  getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
512  if (ConstraintCode == "R")
514  else if (ConstraintCode == "ZC")
516  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
517  }
518 
519  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
520  Type *Ty, unsigned AS) const override;
521 
522  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
523 
524  EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
525  unsigned SrcAlign,
526  bool IsMemset, bool ZeroMemset,
527  bool MemcpyStrSrc,
528  MachineFunction &MF) const override;
529 
530  /// isFPImmLegal - Returns true if the target can instruction select the
531  /// specified FP immediate natively. If false, the legalizer will
532  /// materialize the FP immediate as a load from a constant pool.
533  bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
534 
535  unsigned getJumpTableEncoding() const override;
536  bool useSoftFloat() const override;
537 
538  /// Emit a sign-extension using sll/sra, seb, or seh appropriately.
539  MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr *MI,
540  MachineBasicBlock *BB,
541  unsigned Size, unsigned DstReg,
542  unsigned SrcRec) const;
543 
544  MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
545  unsigned Size, unsigned BinOpcode, bool Nand = false) const;
546  MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI,
547  MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
548  bool Nand = false) const;
549  MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI,
550  MachineBasicBlock *BB, unsigned Size) const;
551  MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI,
552  MachineBasicBlock *BB, unsigned Size) const;
553  MachineBasicBlock *emitSEL_D(MachineInstr *MI, MachineBasicBlock *BB) const;
554  MachineBasicBlock *emitPseudoSELECT(MachineInstr *MI,
555  MachineBasicBlock *BB, bool isFPCmp,
556  unsigned Opc) const;
557  };
558 
559  /// Create MipsTargetLowering objects.
560  const MipsTargetLowering *
561  createMips16TargetLowering(const MipsTargetMachine &TM,
562  const MipsSubtarget &STI);
563  const MipsTargetLowering *
564  createMipsSETargetLowering(const MipsTargetMachine &TM,
565  const MipsSubtarget &STI);
566 
567  namespace Mips {
568  FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
569  const TargetLibraryInfo *libInfo);
570  }
571 }
572 
573 #endif
const MipsTargetLowering * createMipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:724
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:104
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
LLVM Argument representation.
Definition: Argument.h:35
const MipsSubtarget & Subtarget
const MipsTargetLowering * createMips16TargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
Create MipsTargetLowering objects.
MipsTargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
ReplaceNodeResults - Replace the results of node with an illegal result type with new values built ou...
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - get the ISD::SETCC result ValueType
void LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but leg...
lazy value info
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APInt.h:33
SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
MO_ABS_HI/LO - Represents the hi or low part of an absolute symbol address.
Definition: MipsBaseInfo.h:53
SDValue getAddrGlobalLargeGOT(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned HiFlag, unsigned LoFlag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:30
This contains information for each constraint that we are lowering.
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:191
unsigned getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const override
Return the register ID of the name passed in.
SDValue getAddrLocal(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, bool IsN32OrN64) const
SDValue getAddrGlobal(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
MO_GPREL - Represents the offset from the current gp value to be used for the relocatable object file...
Definition: MipsBaseInfo.h:49
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:97
A self-contained host- and target-independent arbitrary-precision floating-point software implementat...
Definition: APFloat.h:122
MVT - Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:41
bool operator()(const char *S1, const char *S2) const
SDValue getAddrNonPIC(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG) const
void HandleByVal(CCState *, unsigned &, unsigned) const override
Target-specific cleanup for formal ByVal parameters.
static const MipsTargetLowering * create(const MipsTargetMachine &TM, const MipsSubtarget &STI)
EVT - Extended Value Type.
Definition: ValueTypes.h:31
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
MachinePointerInfo - This class contains a discriminated union of information about pointers in memor...
CCState - This class holds information needed while lowering arguments and return values...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:179
SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
Provides information about what library functions are available for the current target.
CCValAssign - Represent assignment of one arg/retval to a location.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:731
Represents one node in the SelectionDAG.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
createFastISel - This method returns a target specific FastISel object, or null if the target does no...
AddrMode
ARM Addressing Modes.
Definition: ARMBaseInfo.h:235
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
static MachinePointerInfo getGOT()
getGOT - Return a MachinePointerInfo record that refers to a GOT entry.
Representation of each machine instruction.
Definition: MachineInstr.h:51
SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
#define N
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
virtual void getOpndList(SmallVectorImpl< SDValue > &Ops, std::deque< std::pair< unsigned, SDValue > > &RegsToPass, bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const
This function fills Ops, which is the list of operands that will later be used when a function call n...
SDValue getRegister(unsigned Reg, EVT VT)
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:40
const MipsABIInfo & ABI
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:338
const char * getTargetNodeName(unsigned Opcode) const override
getTargetNodeName - This method returns the name of a target specific
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
SDValue getAddrGPRel(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG) const
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
This file describes how to lower LLVM code to machine code.