LLVM  3.7.0
AArch64FrameLowering.cpp
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1 //===- AArch64FrameLowering.cpp - AArch64 Frame Lowering -------*- C++ -*-====//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the AArch64 implementation of TargetFrameLowering class.
11 //
12 // On AArch64, stack frames are structured as follows:
13 //
14 // The stack grows downward.
15 //
16 // All of the individual frame areas on the frame below are optional, i.e. it's
17 // possible to create a function so that the particular area isn't present
18 // in the frame.
19 //
20 // At function entry, the "frame" looks as follows:
21 //
22 // | | Higher address
23 // |-----------------------------------|
24 // | |
25 // | arguments passed on the stack |
26 // | |
27 // |-----------------------------------| <- sp
28 // | | Lower address
29 //
30 //
31 // After the prologue has run, the frame has the following general structure.
32 // Note that this doesn't depict the case where a red-zone is used. Also,
33 // technically the last frame area (VLAs) doesn't get created until in the
34 // main function body, after the prologue is run. However, it's depicted here
35 // for completeness.
36 //
37 // | | Higher address
38 // |-----------------------------------|
39 // | |
40 // | arguments passed on the stack |
41 // | |
42 // |-----------------------------------|
43 // | |
44 // | prev_fp, prev_lr |
45 // | (a.k.a. "frame record") |
46 // |-----------------------------------| <- fp(=x29)
47 // | |
48 // | other callee-saved registers |
49 // | |
50 // |-----------------------------------|
51 // |.empty.space.to.make.part.below....|
52 // |.aligned.in.case.it.needs.more.than| (size of this area is unknown at
53 // |.the.standard.16-byte.alignment....| compile time; if present)
54 // |-----------------------------------|
55 // | |
56 // | local variables of fixed size |
57 // | including spill slots |
58 // |-----------------------------------| <- bp(not defined by ABI,
59 // |.variable-sized.local.variables....| LLVM chooses X19)
60 // |.(VLAs)............................| (size of this area is unknown at
61 // |...................................| compile time)
62 // |-----------------------------------| <- sp
63 // | | Lower address
64 //
65 //
66 // To access the data in a frame, at-compile time, a constant offset must be
67 // computable from one of the pointers (fp, bp, sp) to access it. The size
68 // of the areas with a dotted background cannot be computed at compile-time
69 // if they are present, making it required to have all three of fp, bp and
70 // sp to be set up to be able to access all contents in the frame areas,
71 // assuming all of the frame areas are non-empty.
72 //
73 // For most functions, some of the frame areas are empty. For those functions,
74 // it may not be necessary to set up fp or bp:
75 // * A base pointer is definitly needed when there are both VLAs and local
76 // variables with more-than-default alignment requirements.
77 // * A frame pointer is definitly needed when there are local variables with
78 // more-than-default alignment requirements.
79 //
80 // In some cases when a base pointer is not strictly needed, it is generated
81 // anyway when offsets from the frame pointer to access local variables become
82 // so large that the offset can't be encoded in the immediate fields of loads
83 // or stores.
84 //
85 // FIXME: also explain the redzone concept.
86 // FIXME: also explain the concept of reserved call frames.
87 //
88 //===----------------------------------------------------------------------===//
89 
90 #include "AArch64FrameLowering.h"
91 #include "AArch64InstrInfo.h"
93 #include "AArch64Subtarget.h"
94 #include "AArch64TargetMachine.h"
95 #include "llvm/ADT/Statistic.h"
102 #include "llvm/IR/DataLayout.h"
103 #include "llvm/IR/Function.h"
105 #include "llvm/Support/Debug.h"
107 
108 using namespace llvm;
109 
110 #define DEBUG_TYPE "frame-info"
111 
112 static cl::opt<bool> EnableRedZone("aarch64-redzone",
113  cl::desc("enable use of redzone on AArch64"),
114  cl::init(false), cl::Hidden);
115 
116 STATISTIC(NumRedZoneFunctions, "Number of functions using red zone");
117 
119  if (!EnableRedZone)
120  return false;
121  // Don't use the red zone if the function explicitly asks us not to.
122  // This is typically used for kernel code.
124  return false;
125 
126  const MachineFrameInfo *MFI = MF.getFrameInfo();
128  unsigned NumBytes = AFI->getLocalStackSize();
129 
130  // Note: currently hasFP() is always true for hasCalls(), but that's an
131  // implementation detail of the current code, not a strict requirement,
132  // so stay safe here and check both.
133  if (MFI->hasCalls() || hasFP(MF) || NumBytes > 128)
134  return false;
135  return true;
136 }
137 
138 /// hasFP - Return true if the specified function should have a dedicated frame
139 /// pointer register.
141  const MachineFrameInfo *MFI = MF.getFrameInfo();
142  const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
143  return (MFI->hasCalls() || MFI->hasVarSizedObjects() ||
144  MFI->isFrameAddressTaken() || MFI->hasStackMap() ||
145  MFI->hasPatchPoint() || RegInfo->needsStackRealignment(MF));
146 }
147 
148 /// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
149 /// not required, we reserve argument space for call sites in the function
150 /// immediately on entry to the current function. This eliminates the need for
151 /// add/sub sp brackets around call sites. Returns true if the call frame is
152 /// included as part of the stack frame.
153 bool
155  return !MF.getFrameInfo()->hasVarSizedObjects();
156 }
157 
161  const AArch64InstrInfo *TII =
162  static_cast<const AArch64InstrInfo *>(MF.getSubtarget().getInstrInfo());
163  DebugLoc DL = I->getDebugLoc();
164  unsigned Opc = I->getOpcode();
165  bool IsDestroy = Opc == TII->getCallFrameDestroyOpcode();
166  uint64_t CalleePopAmount = IsDestroy ? I->getOperand(1).getImm() : 0;
167 
169  if (!TFI->hasReservedCallFrame(MF)) {
170  unsigned Align = getStackAlignment();
171 
172  int64_t Amount = I->getOperand(0).getImm();
173  Amount = RoundUpToAlignment(Amount, Align);
174  if (!IsDestroy)
175  Amount = -Amount;
176 
177  // N.b. if CalleePopAmount is valid but zero (i.e. callee would pop, but it
178  // doesn't have to pop anything), then the first operand will be zero too so
179  // this adjustment is a no-op.
180  if (CalleePopAmount == 0) {
181  // FIXME: in-function stack adjustment for calls is limited to 24-bits
182  // because there's no guaranteed temporary register available.
183  //
184  // ADD/SUB (immediate) has only LSL #0 and LSL #12 available.
185  // 1) For offset <= 12-bit, we use LSL #0
186  // 2) For 12-bit <= offset <= 24-bit, we use two instructions. One uses
187  // LSL #0, and the other uses LSL #12.
188  //
189  // Mostly call frames will be allocated at the start of a function so
190  // this is OK, but it is a limitation that needs dealing with.
191  assert(Amount > -0xffffff && Amount < 0xffffff && "call frame too large");
192  emitFrameOffset(MBB, I, DL, AArch64::SP, AArch64::SP, Amount, TII);
193  }
194  } else if (CalleePopAmount != 0) {
195  // If the calling convention demands that the callee pops arguments from the
196  // stack, we want to add it back if we have a reserved call frame.
197  assert(CalleePopAmount < 0xffffff && "call frame too large");
198  emitFrameOffset(MBB, I, DL, AArch64::SP, AArch64::SP, -CalleePopAmount,
199  TII);
200  }
201  MBB.erase(I);
202 }
203 
206  unsigned FramePtr) const {
207  MachineFunction &MF = *MBB.getParent();
208  MachineFrameInfo *MFI = MF.getFrameInfo();
209  MachineModuleInfo &MMI = MF.getMMI();
210  const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
212  DebugLoc DL = MBB.findDebugLoc(MBBI);
213 
214  // Add callee saved registers to move list.
215  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
216  if (CSI.empty())
217  return;
218 
219  const DataLayout *TD = MF.getTarget().getDataLayout();
220  bool HasFP = hasFP(MF);
221 
222  // Calculate amount of bytes used for return address storing.
223  int stackGrowth = -TD->getPointerSize(0);
224 
225  // Calculate offsets.
226  int64_t saveAreaOffset = (HasFP ? 2 : 1) * stackGrowth;
227  unsigned TotalSkipped = 0;
228  for (const auto &Info : CSI) {
229  unsigned Reg = Info.getReg();
230  int64_t Offset = MFI->getObjectOffset(Info.getFrameIdx()) -
231  getOffsetOfLocalArea() + saveAreaOffset;
232 
233  // Don't output a new CFI directive if we're re-saving the frame pointer or
234  // link register. This happens when the PrologEpilogInserter has inserted an
235  // extra "STP" of the frame pointer and link register -- the "emitPrologue"
236  // method automatically generates the directives when frame pointers are
237  // used. If we generate CFI directives for the extra "STP"s, the linker will
238  // lose track of the correct values for the frame pointer and link register.
239  if (HasFP && (FramePtr == Reg || Reg == AArch64::LR)) {
240  TotalSkipped += stackGrowth;
241  continue;
242  }
243 
244  unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
245  unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
246  nullptr, DwarfReg, Offset - TotalSkipped));
247  BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
248  .addCFIIndex(CFIIndex)
250  }
251 }
252 
253 /// Get FPOffset by analyzing the first instruction.
255  // First instruction must a) allocate the stack and b) have an immediate
256  // that is a multiple of -2.
257  assert(((MBBI->getOpcode() == AArch64::STPXpre ||
258  MBBI->getOpcode() == AArch64::STPDpre) &&
259  MBBI->getOperand(3).getReg() == AArch64::SP &&
260  MBBI->getOperand(4).getImm() < 0 &&
261  (MBBI->getOperand(4).getImm() & 1) == 0));
262 
263  // Frame pointer is fp = sp - 16. Since the STPXpre subtracts the space
264  // required for the callee saved register area we get the frame pointer
265  // by addding that offset - 16 = -getImm()*8 - 2*8 = -(getImm() + 2) * 8.
266  int FPOffset = -(MBBI->getOperand(4).getImm() + 2) * 8;
267  assert(FPOffset >= 0 && "Bad Framepointer Offset");
268  return FPOffset;
269 }
270 
271 static bool isCSSave(MachineInstr *MBBI) {
272  return MBBI->getOpcode() == AArch64::STPXi ||
273  MBBI->getOpcode() == AArch64::STPDi ||
274  MBBI->getOpcode() == AArch64::STPXpre ||
275  MBBI->getOpcode() == AArch64::STPDpre;
276 }
277 
279  MachineBasicBlock &MBB) const {
280  MachineBasicBlock::iterator MBBI = MBB.begin();
281  const MachineFrameInfo *MFI = MF.getFrameInfo();
282  const Function *Fn = MF.getFunction();
283  const AArch64RegisterInfo *RegInfo = static_cast<const AArch64RegisterInfo *>(
286  MachineModuleInfo &MMI = MF.getMMI();
288  bool needsFrameMoves = MMI.hasDebugInfo() || Fn->needsUnwindTableEntry();
289  bool HasFP = hasFP(MF);
290  DebugLoc DL = MBB.findDebugLoc(MBBI);
291 
292  // All calls are tail calls in GHC calling conv, and functions have no
293  // prologue/epilogue.
295  return;
296 
297  int NumBytes = (int)MFI->getStackSize();
298  if (!AFI->hasStackFrame()) {
299  assert(!HasFP && "unexpected function without stack frame but with FP");
300 
301  // All of the stack allocation is for locals.
302  AFI->setLocalStackSize(NumBytes);
303 
304  // Label used to tie together the PROLOG_LABEL and the MachineMoves.
305  MCSymbol *FrameLabel = MMI.getContext().createTempSymbol();
306 
307  // REDZONE: If the stack size is less than 128 bytes, we don't need
308  // to actually allocate.
309  if (NumBytes && !canUseRedZone(MF)) {
310  emitFrameOffset(MBB, MBBI, DL, AArch64::SP, AArch64::SP, -NumBytes, TII,
312 
313  // Encode the stack size of the leaf function.
314  unsigned CFIIndex = MMI.addFrameInst(
315  MCCFIInstruction::createDefCfaOffset(FrameLabel, -NumBytes));
316  BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
317  .addCFIIndex(CFIIndex)
319  } else if (NumBytes) {
320  ++NumRedZoneFunctions;
321  }
322 
323  return;
324  }
325 
326  // Only set up FP if we actually need to.
327  int FPOffset = 0;
328  if (HasFP)
329  FPOffset = getFPOffsetInPrologue(MBBI);
330 
331  // Move past the saves of the callee-saved registers.
332  while (isCSSave(MBBI)) {
333  ++MBBI;
334  NumBytes -= 16;
335  }
336  assert(NumBytes >= 0 && "Negative stack allocation size!?");
337  if (HasFP) {
338  // Issue sub fp, sp, FPOffset or
339  // mov fp,sp when FPOffset is zero.
340  // Note: All stores of callee-saved registers are marked as "FrameSetup".
341  // This code marks the instruction(s) that set the FP also.
342  emitFrameOffset(MBB, MBBI, DL, AArch64::FP, AArch64::SP, FPOffset, TII,
344  }
345 
346  // All of the remaining stack allocations are for locals.
347  AFI->setLocalStackSize(NumBytes);
348 
349  // Allocate space for the rest of the frame.
350 
351  const unsigned Alignment = MFI->getMaxAlignment();
352  const bool NeedsRealignment = RegInfo->needsStackRealignment(MF);
353  unsigned scratchSPReg = AArch64::SP;
354  if (NumBytes && NeedsRealignment) {
355  // Use the first callee-saved register as a scratch register.
356  scratchSPReg = AArch64::X9;
357  MF.getRegInfo().setPhysRegUsed(scratchSPReg);
358  }
359 
360  // If we're a leaf function, try using the red zone.
361  if (NumBytes && !canUseRedZone(MF))
362  // FIXME: in the case of dynamic re-alignment, NumBytes doesn't have
363  // the correct value here, as NumBytes also includes padding bytes,
364  // which shouldn't be counted here.
365  emitFrameOffset(MBB, MBBI, DL, scratchSPReg, AArch64::SP, -NumBytes, TII,
367 
368  if (NumBytes && NeedsRealignment) {
369  const unsigned NrBitsToZero = countTrailingZeros(Alignment);
370  assert(NrBitsToZero > 1);
371  assert(scratchSPReg != AArch64::SP);
372 
373  // SUB X9, SP, NumBytes
374  // -- X9 is temporary register, so shouldn't contain any live data here,
375  // -- free to use. This is already produced by emitFrameOffset above.
376  // AND SP, X9, 0b11111...0000
377  // The logical immediates have a non-trivial encoding. The following
378  // formula computes the encoded immediate with all ones but
379  // NrBitsToZero zero bits as least significant bits.
380  uint32_t andMaskEncoded =
381  (1 <<12) // = N
382  | ((64-NrBitsToZero) << 6) // immr
383  | ((64-NrBitsToZero-1) << 0) // imms
384  ;
385  BuildMI(MBB, MBBI, DL, TII->get(AArch64::ANDXri), AArch64::SP)
386  .addReg(scratchSPReg, RegState::Kill)
387  .addImm(andMaskEncoded);
388  }
389 
390  // If we need a base pointer, set it up here. It's whatever the value of the
391  // stack pointer is at this point. Any variable size objects will be allocated
392  // after this, so we can still use the base pointer to reference locals.
393  //
394  // FIXME: Clarify FrameSetup flags here.
395  // Note: Use emitFrameOffset() like above for FP if the FrameSetup flag is
396  // needed.
397  if (RegInfo->hasBasePointer(MF)) {
398  TII->copyPhysReg(MBB, MBBI, DL, RegInfo->getBaseRegister(), AArch64::SP,
399  false);
400  }
401 
402  if (needsFrameMoves) {
403  const DataLayout *TD = MF.getTarget().getDataLayout();
404  const int StackGrowth = -TD->getPointerSize(0);
405  unsigned FramePtr = RegInfo->getFrameRegister(MF);
406  // An example of the prologue:
407  //
408  // .globl __foo
409  // .align 2
410  // __foo:
411  // Ltmp0:
412  // .cfi_startproc
413  // .cfi_personality 155, ___gxx_personality_v0
414  // Leh_func_begin:
415  // .cfi_lsda 16, Lexception33
416  //
417  // stp xa,bx, [sp, -#offset]!
418  // ...
419  // stp x28, x27, [sp, #offset-32]
420  // stp fp, lr, [sp, #offset-16]
421  // add fp, sp, #offset - 16
422  // sub sp, sp, #1360
423  //
424  // The Stack:
425  // +-------------------------------------------+
426  // 10000 | ........ | ........ | ........ | ........ |
427  // 10004 | ........ | ........ | ........ | ........ |
428  // +-------------------------------------------+
429  // 10008 | ........ | ........ | ........ | ........ |
430  // 1000c | ........ | ........ | ........ | ........ |
431  // +===========================================+
432  // 10010 | X28 Register |
433  // 10014 | X28 Register |
434  // +-------------------------------------------+
435  // 10018 | X27 Register |
436  // 1001c | X27 Register |
437  // +===========================================+
438  // 10020 | Frame Pointer |
439  // 10024 | Frame Pointer |
440  // +-------------------------------------------+
441  // 10028 | Link Register |
442  // 1002c | Link Register |
443  // +===========================================+
444  // 10030 | ........ | ........ | ........ | ........ |
445  // 10034 | ........ | ........ | ........ | ........ |
446  // +-------------------------------------------+
447  // 10038 | ........ | ........ | ........ | ........ |
448  // 1003c | ........ | ........ | ........ | ........ |
449  // +-------------------------------------------+
450  //
451  // [sp] = 10030 :: >>initial value<<
452  // sp = 10020 :: stp fp, lr, [sp, #-16]!
453  // fp = sp == 10020 :: mov fp, sp
454  // [sp] == 10020 :: stp x28, x27, [sp, #-16]!
455  // sp == 10010 :: >>final value<<
456  //
457  // The frame pointer (w29) points to address 10020. If we use an offset of
458  // '16' from 'w29', we get the CFI offsets of -8 for w30, -16 for w29, -24
459  // for w27, and -32 for w28:
460  //
461  // Ltmp1:
462  // .cfi_def_cfa w29, 16
463  // Ltmp2:
464  // .cfi_offset w30, -8
465  // Ltmp3:
466  // .cfi_offset w29, -16
467  // Ltmp4:
468  // .cfi_offset w27, -24
469  // Ltmp5:
470  // .cfi_offset w28, -32
471 
472  if (HasFP) {
473  // Define the current CFA rule to use the provided FP.
474  unsigned Reg = RegInfo->getDwarfRegNum(FramePtr, true);
475  unsigned CFIIndex = MMI.addFrameInst(
476  MCCFIInstruction::createDefCfa(nullptr, Reg, 2 * StackGrowth));
477  BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
478  .addCFIIndex(CFIIndex)
480 
481  // Record the location of the stored LR
482  unsigned LR = RegInfo->getDwarfRegNum(AArch64::LR, true);
483  CFIIndex = MMI.addFrameInst(
484  MCCFIInstruction::createOffset(nullptr, LR, StackGrowth));
485  BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
486  .addCFIIndex(CFIIndex)
488 
489  // Record the location of the stored FP
490  CFIIndex = MMI.addFrameInst(
491  MCCFIInstruction::createOffset(nullptr, Reg, 2 * StackGrowth));
492  BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
493  .addCFIIndex(CFIIndex)
495  } else {
496  // Encode the stack size of the leaf function.
497  unsigned CFIIndex = MMI.addFrameInst(
499  BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
500  .addCFIIndex(CFIIndex)
502  }
503 
504  // Now emit the moves for whatever callee saved regs we have.
505  emitCalleeSavedFrameMoves(MBB, MBBI, FramePtr);
506  }
507 }
508 
509 static bool isCalleeSavedRegister(unsigned Reg, const MCPhysReg *CSRegs) {
510  for (unsigned i = 0; CSRegs[i]; ++i)
511  if (Reg == CSRegs[i])
512  return true;
513  return false;
514 }
515 
516 static bool isCSRestore(MachineInstr *MI, const MCPhysReg *CSRegs) {
517  unsigned RtIdx = 0;
518  if (MI->getOpcode() == AArch64::LDPXpost ||
519  MI->getOpcode() == AArch64::LDPDpost)
520  RtIdx = 1;
521 
522  if (MI->getOpcode() == AArch64::LDPXpost ||
523  MI->getOpcode() == AArch64::LDPDpost ||
524  MI->getOpcode() == AArch64::LDPXi || MI->getOpcode() == AArch64::LDPDi) {
525  if (!isCalleeSavedRegister(MI->getOperand(RtIdx).getReg(), CSRegs) ||
526  !isCalleeSavedRegister(MI->getOperand(RtIdx + 1).getReg(), CSRegs) ||
527  MI->getOperand(RtIdx + 2).getReg() != AArch64::SP)
528  return false;
529  return true;
530  }
531 
532  return false;
533 }
534 
536  MachineBasicBlock &MBB) const {
538  MachineFrameInfo *MFI = MF.getFrameInfo();
539  const AArch64InstrInfo *TII =
540  static_cast<const AArch64InstrInfo *>(MF.getSubtarget().getInstrInfo());
541  const AArch64RegisterInfo *RegInfo = static_cast<const AArch64RegisterInfo *>(
543  DebugLoc DL;
544  bool IsTailCallReturn = false;
545  if (MBB.end() != MBBI) {
546  DL = MBBI->getDebugLoc();
547  unsigned RetOpcode = MBBI->getOpcode();
548  IsTailCallReturn = RetOpcode == AArch64::TCRETURNdi ||
549  RetOpcode == AArch64::TCRETURNri;
550  }
551  int NumBytes = MFI->getStackSize();
553 
554  // All calls are tail calls in GHC calling conv, and functions have no
555  // prologue/epilogue.
557  return;
558 
559  // Initial and residual are named for consistency with the prologue. Note that
560  // in the epilogue, the residual adjustment is executed first.
561  uint64_t ArgumentPopSize = 0;
562  if (IsTailCallReturn) {
563  MachineOperand &StackAdjust = MBBI->getOperand(1);
564 
565  // For a tail-call in a callee-pops-arguments environment, some or all of
566  // the stack may actually be in use for the call's arguments, this is
567  // calculated during LowerCall and consumed here...
568  ArgumentPopSize = StackAdjust.getImm();
569  } else {
570  // ... otherwise the amount to pop is *all* of the argument space,
571  // conveniently stored in the MachineFunctionInfo by
572  // LowerFormalArguments. This will, of course, be zero for the C calling
573  // convention.
574  ArgumentPopSize = AFI->getArgumentStackToRestore();
575  }
576 
577  // The stack frame should be like below,
578  //
579  // ---------------------- ---
580  // | | |
581  // | BytesInStackArgArea| CalleeArgStackSize
582  // | (NumReusableBytes) | (of tail call)
583  // | | ---
584  // | | |
585  // ---------------------| --- |
586  // | | | |
587  // | CalleeSavedReg | | |
588  // | (NumRestores * 16) | | |
589  // | | | |
590  // ---------------------| | NumBytes
591  // | | StackSize (StackAdjustUp)
592  // | LocalStackSize | | |
593  // | (covering callee | | |
594  // | args) | | |
595  // | | | |
596  // ---------------------- --- ---
597  //
598  // So NumBytes = StackSize + BytesInStackArgArea - CalleeArgStackSize
599  // = StackSize + ArgumentPopSize
600  //
601  // AArch64TargetLowering::LowerCall figures out ArgumentPopSize and keeps
602  // it as the 2nd argument of AArch64ISD::TC_RETURN.
603  NumBytes += ArgumentPopSize;
604 
605  unsigned NumRestores = 0;
606  // Move past the restores of the callee-saved registers.
608  const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
609  if (LastPopI != MBB.begin()) {
610  do {
611  ++NumRestores;
612  --LastPopI;
613  } while (LastPopI != MBB.begin() && isCSRestore(LastPopI, CSRegs));
614  if (!isCSRestore(LastPopI, CSRegs)) {
615  ++LastPopI;
616  --NumRestores;
617  }
618  }
619  NumBytes -= NumRestores * 16;
620  assert(NumBytes >= 0 && "Negative stack allocation size!?");
621 
622  if (!hasFP(MF)) {
623  // If this was a redzone leaf function, we don't need to restore the
624  // stack pointer.
625  if (!canUseRedZone(MF))
626  emitFrameOffset(MBB, LastPopI, DL, AArch64::SP, AArch64::SP, NumBytes,
627  TII);
628  return;
629  }
630 
631  // Restore the original stack pointer.
632  // FIXME: Rather than doing the math here, we should instead just use
633  // non-post-indexed loads for the restores if we aren't actually going to
634  // be able to save any instructions.
635  if (NumBytes || MFI->hasVarSizedObjects())
636  emitFrameOffset(MBB, LastPopI, DL, AArch64::SP, AArch64::FP,
637  -(NumRestores - 1) * 16, TII, MachineInstr::NoFlags);
638 }
639 
640 /// getFrameIndexOffset - Returns the displacement from the frame register to
641 /// the stack frame of the specified index.
643  int FI) const {
644  unsigned FrameReg;
645  return getFrameIndexReference(MF, FI, FrameReg);
646 }
647 
648 /// getFrameIndexReference - Provide a base+offset reference to an FI slot for
649 /// debug info. It's the same as what we use for resolving the code-gen
650 /// references for now. FIXME: This can go wrong when references are
651 /// SP-relative and simple call frames aren't used.
653  int FI,
654  unsigned &FrameReg) const {
655  return resolveFrameIndexReference(MF, FI, FrameReg);
656 }
657 
659  int FI, unsigned &FrameReg,
660  bool PreferFP) const {
661  const MachineFrameInfo *MFI = MF.getFrameInfo();
662  const AArch64RegisterInfo *RegInfo = static_cast<const AArch64RegisterInfo *>(
665  int FPOffset = MFI->getObjectOffset(FI) + 16;
666  int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize();
667  bool isFixed = MFI->isFixedObjectIndex(FI);
668 
669  // Use frame pointer to reference fixed objects. Use it for locals if
670  // there are VLAs or a dynamically realigned SP (and thus the SP isn't
671  // reliable as a base). Make sure useFPForScavengingIndex() does the
672  // right thing for the emergency spill slot.
673  bool UseFP = false;
674  if (AFI->hasStackFrame()) {
675  // Note: Keeping the following as multiple 'if' statements rather than
676  // merging to a single expression for readability.
677  //
678  // Argument access should always use the FP.
679  if (isFixed) {
680  UseFP = hasFP(MF);
681  } else if (hasFP(MF) && !RegInfo->hasBasePointer(MF) &&
682  !RegInfo->needsStackRealignment(MF)) {
683  // Use SP or FP, whichever gives us the best chance of the offset
684  // being in range for direct access. If the FPOffset is positive,
685  // that'll always be best, as the SP will be even further away.
686  // If the FPOffset is negative, we have to keep in mind that the
687  // available offset range for negative offsets is smaller than for
688  // positive ones. If we have variable sized objects, we're stuck with
689  // using the FP regardless, though, as the SP offset is unknown
690  // and we don't have a base pointer available. If an offset is
691  // available via the FP and the SP, use whichever is closest.
692  if (PreferFP || MFI->hasVarSizedObjects() || FPOffset >= 0 ||
693  (FPOffset >= -256 && Offset > -FPOffset))
694  UseFP = true;
695  }
696  }
697 
698  assert((isFixed || !RegInfo->needsStackRealignment(MF) || !UseFP) &&
699  "In the presence of dynamic stack pointer realignment, "
700  "non-argument objects cannot be accessed through the frame pointer");
701 
702  if (UseFP) {
703  FrameReg = RegInfo->getFrameRegister(MF);
704  return FPOffset;
705  }
706 
707  // Use the base pointer if we have one.
708  if (RegInfo->hasBasePointer(MF))
709  FrameReg = RegInfo->getBaseRegister();
710  else {
711  FrameReg = AArch64::SP;
712  // If we're using the red zone for this function, the SP won't actually
713  // be adjusted, so the offsets will be negative. They're also all
714  // within range of the signed 9-bit immediate instructions.
715  if (canUseRedZone(MF))
716  Offset -= AFI->getLocalStackSize();
717  }
718 
719  return Offset;
720 }
721 
722 static unsigned getPrologueDeath(MachineFunction &MF, unsigned Reg) {
723  if (Reg != AArch64::LR)
724  return getKillRegState(true);
725 
726  // LR maybe referred to later by an @llvm.returnaddress intrinsic.
727  bool LRLiveIn = MF.getRegInfo().isLiveIn(AArch64::LR);
728  bool LRKill = !(LRLiveIn && MF.getFrameInfo()->isReturnAddressTaken());
729  return getKillRegState(LRKill);
730 }
731 
734  const std::vector<CalleeSavedInfo> &CSI,
735  const TargetRegisterInfo *TRI) const {
736  MachineFunction &MF = *MBB.getParent();
737  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
738  unsigned Count = CSI.size();
739  DebugLoc DL;
740  assert((Count & 1) == 0 && "Odd number of callee-saved regs to spill!");
741 
742  if (MI != MBB.end())
743  DL = MI->getDebugLoc();
744 
745  for (unsigned i = 0; i < Count; i += 2) {
746  unsigned idx = Count - i - 2;
747  unsigned Reg1 = CSI[idx].getReg();
748  unsigned Reg2 = CSI[idx + 1].getReg();
749  // GPRs and FPRs are saved in pairs of 64-bit regs. We expect the CSI
750  // list to come in sorted by frame index so that we can issue the store
751  // pair instructions directly. Assert if we see anything otherwise.
752  //
753  // The order of the registers in the list is controlled by
754  // getCalleeSavedRegs(), so they will always be in-order, as well.
755  assert(CSI[idx].getFrameIdx() + 1 == CSI[idx + 1].getFrameIdx() &&
756  "Out of order callee saved regs!");
757  unsigned StrOpc;
758  assert((Count & 1) == 0 && "Odd number of callee-saved regs to spill!");
759  assert((i & 1) == 0 && "Odd index for callee-saved reg spill!");
760  // Issue sequence of non-sp increment and pi sp spills for cs regs. The
761  // first spill is a pre-increment that allocates the stack.
762  // For example:
763  // stp x22, x21, [sp, #-48]! // addImm(-6)
764  // stp x20, x19, [sp, #16] // addImm(+2)
765  // stp fp, lr, [sp, #32] // addImm(+4)
766  // Rationale: This sequence saves uop updates compared to a sequence of
767  // pre-increment spills like stp xi,xj,[sp,#-16]!
768  // Note: Similar rational and sequence for restores in epilog.
769  if (AArch64::GPR64RegClass.contains(Reg1)) {
770  assert(AArch64::GPR64RegClass.contains(Reg2) &&
771  "Expected GPR64 callee-saved register pair!");
772  // For first spill use pre-increment store.
773  if (i == 0)
774  StrOpc = AArch64::STPXpre;
775  else
776  StrOpc = AArch64::STPXi;
777  } else if (AArch64::FPR64RegClass.contains(Reg1)) {
778  assert(AArch64::FPR64RegClass.contains(Reg2) &&
779  "Expected FPR64 callee-saved register pair!");
780  // For first spill use pre-increment store.
781  if (i == 0)
782  StrOpc = AArch64::STPDpre;
783  else
784  StrOpc = AArch64::STPDi;
785  } else
786  llvm_unreachable("Unexpected callee saved register!");
787  DEBUG(dbgs() << "CSR spill: (" << TRI->getName(Reg1) << ", "
788  << TRI->getName(Reg2) << ") -> fi#(" << CSI[idx].getFrameIdx()
789  << ", " << CSI[idx + 1].getFrameIdx() << ")\n");
790  // Compute offset: i = 0 => offset = -Count;
791  // i = 2 => offset = -(Count - 2) + Count = 2 = i; etc.
792  const int Offset = (i == 0) ? -Count : i;
793  assert((Offset >= -64 && Offset <= 63) &&
794  "Offset out of bounds for STP immediate");
795  MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc));
796  if (StrOpc == AArch64::STPDpre || StrOpc == AArch64::STPXpre)
797  MIB.addReg(AArch64::SP, RegState::Define);
798 
799  MBB.addLiveIn(Reg1);
800  MBB.addLiveIn(Reg2);
801  MIB.addReg(Reg2, getPrologueDeath(MF, Reg2))
802  .addReg(Reg1, getPrologueDeath(MF, Reg1))
803  .addReg(AArch64::SP)
804  .addImm(Offset) // [sp, #offset * 8], where factor * 8 is implicit
806  }
807  return true;
808 }
809 
812  const std::vector<CalleeSavedInfo> &CSI,
813  const TargetRegisterInfo *TRI) const {
814  MachineFunction &MF = *MBB.getParent();
815  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
816  unsigned Count = CSI.size();
817  DebugLoc DL;
818  assert((Count & 1) == 0 && "Odd number of callee-saved regs to spill!");
819 
820  if (MI != MBB.end())
821  DL = MI->getDebugLoc();
822 
823  for (unsigned i = 0; i < Count; i += 2) {
824  unsigned Reg1 = CSI[i].getReg();
825  unsigned Reg2 = CSI[i + 1].getReg();
826  // GPRs and FPRs are saved in pairs of 64-bit regs. We expect the CSI
827  // list to come in sorted by frame index so that we can issue the store
828  // pair instructions directly. Assert if we see anything otherwise.
829  assert(CSI[i].getFrameIdx() + 1 == CSI[i + 1].getFrameIdx() &&
830  "Out of order callee saved regs!");
831  // Issue sequence of non-sp increment and sp-pi restores for cs regs. Only
832  // the last load is sp-pi post-increment and de-allocates the stack:
833  // For example:
834  // ldp fp, lr, [sp, #32] // addImm(+4)
835  // ldp x20, x19, [sp, #16] // addImm(+2)
836  // ldp x22, x21, [sp], #48 // addImm(+6)
837  // Note: see comment in spillCalleeSavedRegisters()
838  unsigned LdrOpc;
839 
840  assert((Count & 1) == 0 && "Odd number of callee-saved regs to spill!");
841  assert((i & 1) == 0 && "Odd index for callee-saved reg spill!");
842  if (AArch64::GPR64RegClass.contains(Reg1)) {
843  assert(AArch64::GPR64RegClass.contains(Reg2) &&
844  "Expected GPR64 callee-saved register pair!");
845  if (i == Count - 2)
846  LdrOpc = AArch64::LDPXpost;
847  else
848  LdrOpc = AArch64::LDPXi;
849  } else if (AArch64::FPR64RegClass.contains(Reg1)) {
850  assert(AArch64::FPR64RegClass.contains(Reg2) &&
851  "Expected FPR64 callee-saved register pair!");
852  if (i == Count - 2)
853  LdrOpc = AArch64::LDPDpost;
854  else
855  LdrOpc = AArch64::LDPDi;
856  } else
857  llvm_unreachable("Unexpected callee saved register!");
858  DEBUG(dbgs() << "CSR restore: (" << TRI->getName(Reg1) << ", "
859  << TRI->getName(Reg2) << ") -> fi#(" << CSI[i].getFrameIdx()
860  << ", " << CSI[i + 1].getFrameIdx() << ")\n");
861 
862  // Compute offset: i = 0 => offset = Count - 2; i = 2 => offset = Count - 4;
863  // etc.
864  const int Offset = (i == Count - 2) ? Count : Count - i - 2;
865  assert((Offset >= -64 && Offset <= 63) &&
866  "Offset out of bounds for LDP immediate");
867  MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(LdrOpc));
868  if (LdrOpc == AArch64::LDPXpost || LdrOpc == AArch64::LDPDpost)
869  MIB.addReg(AArch64::SP, RegState::Define);
870 
871  MIB.addReg(Reg2, getDefRegState(true))
872  .addReg(Reg1, getDefRegState(true))
873  .addReg(AArch64::SP)
874  .addImm(Offset); // [sp], #offset * 8 or [sp, #offset * 8]
875  // where the factor * 8 is implicit
876  }
877  return true;
878 }
879 
881  BitVector &SavedRegs,
882  RegScavenger *RS) const {
883  // All calls are tail calls in GHC calling conv, and functions have no
884  // prologue/epilogue.
886  return;
887 
889  const AArch64RegisterInfo *RegInfo = static_cast<const AArch64RegisterInfo *>(
892  SmallVector<unsigned, 4> UnspilledCSGPRs;
893  SmallVector<unsigned, 4> UnspilledCSFPRs;
894 
895  // The frame record needs to be created by saving the appropriate registers
896  if (hasFP(MF)) {
897  SavedRegs.set(AArch64::FP);
898  SavedRegs.set(AArch64::LR);
899  }
900 
901  // Spill the BasePtr if it's used. Do this first thing so that the
902  // getCalleeSavedRegs() below will get the right answer.
903  if (RegInfo->hasBasePointer(MF))
904  SavedRegs.set(RegInfo->getBaseRegister());
905 
906  if (RegInfo->needsStackRealignment(MF) && !RegInfo->hasBasePointer(MF))
907  SavedRegs.set(AArch64::X9);
908 
909  // If any callee-saved registers are used, the frame cannot be eliminated.
910  unsigned NumGPRSpilled = 0;
911  unsigned NumFPRSpilled = 0;
912  bool ExtraCSSpill = false;
913  bool CanEliminateFrame = true;
914  DEBUG(dbgs() << "*** processFunctionBeforeCalleeSavedScan\nUsed CSRs:");
915  const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
916 
917  // Check pairs of consecutive callee-saved registers.
918  for (unsigned i = 0; CSRegs[i]; i += 2) {
919  assert(CSRegs[i + 1] && "Odd number of callee-saved registers!");
920 
921  const unsigned OddReg = CSRegs[i];
922  const unsigned EvenReg = CSRegs[i + 1];
923  assert((AArch64::GPR64RegClass.contains(OddReg) &&
924  AArch64::GPR64RegClass.contains(EvenReg)) ^
925  (AArch64::FPR64RegClass.contains(OddReg) &&
926  AArch64::FPR64RegClass.contains(EvenReg)) &&
927  "Register class mismatch!");
928 
929  const bool OddRegUsed = SavedRegs.test(OddReg);
930  const bool EvenRegUsed = SavedRegs.test(EvenReg);
931 
932  // Early exit if none of the registers in the register pair is actually
933  // used.
934  if (!OddRegUsed && !EvenRegUsed) {
935  if (AArch64::GPR64RegClass.contains(OddReg)) {
936  UnspilledCSGPRs.push_back(OddReg);
937  UnspilledCSGPRs.push_back(EvenReg);
938  } else {
939  UnspilledCSFPRs.push_back(OddReg);
940  UnspilledCSFPRs.push_back(EvenReg);
941  }
942  continue;
943  }
944 
945  unsigned Reg = AArch64::NoRegister;
946  // If only one of the registers of the register pair is used, make sure to
947  // mark the other one as used as well.
948  if (OddRegUsed ^ EvenRegUsed) {
949  // Find out which register is the additional spill.
950  Reg = OddRegUsed ? EvenReg : OddReg;
951  SavedRegs.set(Reg);
952  }
953 
954  DEBUG(dbgs() << ' ' << PrintReg(OddReg, RegInfo));
955  DEBUG(dbgs() << ' ' << PrintReg(EvenReg, RegInfo));
956 
957  assert(((OddReg == AArch64::LR && EvenReg == AArch64::FP) ||
958  (RegInfo->getEncodingValue(OddReg) + 1 ==
959  RegInfo->getEncodingValue(EvenReg))) &&
960  "Register pair of non-adjacent registers!");
961  if (AArch64::GPR64RegClass.contains(OddReg)) {
962  NumGPRSpilled += 2;
963  // If it's not a reserved register, we can use it in lieu of an
964  // emergency spill slot for the register scavenger.
965  // FIXME: It would be better to instead keep looking and choose another
966  // unspilled register that isn't reserved, if there is one.
967  if (Reg != AArch64::NoRegister && !RegInfo->isReservedReg(MF, Reg))
968  ExtraCSSpill = true;
969  } else
970  NumFPRSpilled += 2;
971 
972  CanEliminateFrame = false;
973  }
974 
975  // FIXME: Set BigStack if any stack slot references may be out of range.
976  // For now, just conservatively guestimate based on unscaled indexing
977  // range. We'll end up allocating an unnecessary spill slot a lot, but
978  // realistically that's not a big deal at this stage of the game.
979  // The CSR spill slots have not been allocated yet, so estimateStackSize
980  // won't include them.
981  MachineFrameInfo *MFI = MF.getFrameInfo();
982  unsigned CFSize =
983  MFI->estimateStackSize(MF) + 8 * (NumGPRSpilled + NumFPRSpilled);
984  DEBUG(dbgs() << "Estimated stack frame size: " << CFSize << " bytes.\n");
985  bool BigStack = (CFSize >= 256);
986  if (BigStack || !CanEliminateFrame || RegInfo->cannotEliminateFrame(MF))
987  AFI->setHasStackFrame(true);
988 
989  // Estimate if we might need to scavenge a register at some point in order
990  // to materialize a stack offset. If so, either spill one additional
991  // callee-saved register or reserve a special spill slot to facilitate
992  // register scavenging. If we already spilled an extra callee-saved register
993  // above to keep the number of spills even, we don't need to do anything else
994  // here.
995  if (BigStack && !ExtraCSSpill) {
996 
997  // If we're adding a register to spill here, we have to add two of them
998  // to keep the number of regs to spill even.
999  assert(((UnspilledCSGPRs.size() & 1) == 0) && "Odd number of registers!");
1000  unsigned Count = 0;
1001  while (!UnspilledCSGPRs.empty() && Count < 2) {
1002  unsigned Reg = UnspilledCSGPRs.back();
1003  UnspilledCSGPRs.pop_back();
1004  DEBUG(dbgs() << "Spilling " << PrintReg(Reg, RegInfo)
1005  << " to get a scratch register.\n");
1006  SavedRegs.set(Reg);
1007  ExtraCSSpill = true;
1008  ++Count;
1009  }
1010 
1011  // If we didn't find an extra callee-saved register to spill, create
1012  // an emergency spill slot.
1013  if (!ExtraCSSpill) {
1014  const TargetRegisterClass *RC = &AArch64::GPR64RegClass;
1015  int FI = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(), false);
1016  RS->addScavengingFrameIndex(FI);
1017  DEBUG(dbgs() << "No available CS registers, allocated fi#" << FI
1018  << " as the emergency spill slot.\n");
1019  }
1020  }
1021 }
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
void push_back(const T &Elt)
Definition: SmallVector.h:222
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:104
BitVector & set()
Definition: BitVector.h:218
void setPhysRegUsed(unsigned Reg)
setPhysRegUsed - Mark the specified register used in this function.
int getDwarfRegNum(unsigned RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
bool isReservedReg(const MachineFunction &MF, unsigned Reg) const
AArch64FunctionInfo - This class is derived from MachineFunctionInfo and contains private AArch64-spe...
STATISTIC(NumFunctions,"Total number of functions")
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:39
int resolveFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg, bool PreferFP=false) const
iterator getFirstTerminator()
getFirstTerminator - returns an iterator to the first terminator instruction of this basic block...
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
Definition: MCDwarf.h:381
static int getFPOffsetInPrologue(MachineInstr *MBBI)
Get FPOffset by analyzing the first instruction.
void addLiveIn(unsigned Reg)
Adds the specified register as a live in.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
bool isReturnAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
A debug info location.
Definition: DebugLoc.h:34
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
void emitCalleeSavedFrameMoves(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned FramePtr) const
static MCCFIInstruction createDefCfaOffset(MCSymbol *L, int Offset)
.cfi_def_cfa_offset modifies a rule for computing CFA.
Definition: MCDwarf.h:368
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:172
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
static unsigned getPrologueDeath(MachineFunction &MF, unsigned Reg)
unsigned getSize() const
getSize - Return the size of the register in bytes, which is also the size of a stack slot allocated ...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
const HexagonInstrInfo * TII
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required, we reserve argument space for call sites in the function immediately on entry to the current function.
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
int getFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg) const override
getFrameIndexReference - Provide a base+offset reference to an FI slot for debug info.
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
bool hasDebugInfo() const
hasDebugInfo - Returns true if valid debug info is present.
bool cannotEliminateFrame(const MachineFunction &MF) const
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Definition: Value.cpp:317
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
PrintReg - Helper class for printing registers on a raw_ostream.
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
bool isLiveIn(unsigned Reg) const
bool hasBasePointer(const MachineFunction &MF) const
unsigned LLVM_ATTRIBUTE_UNUSED_RESULT addFrameInst(const MCCFIInstruction &Inst)
iterator getLastNonDebugInstr()
getLastNonDebugInstr - returns an iterator to the last non-debug instruction in the basic block...
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
int64_t getImm() const
unsigned getKillRegState(bool B)
unsigned estimateStackSize(const MachineFunction &MF) const
Estimate and return the size of the stack frame.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:267
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
TargetInstrInfo - Interface to description of machine instruction set.
unsigned getDefRegState(bool B)
bundle_iterator< MachineInstr, instr_iterator > iterator
bool hasStackMap() const
This method may be called any time after instruction selection is complete to determine if there is a...
static bool isCalleeSavedRegister(unsigned Reg, const MCPhysReg *CSRegs)
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:325
MCSymbol * createTempSymbol(bool CanBeUnnamed=true)
Create and return a new assembler temporary symbol with a unique but unspecified name.
Definition: MCContext.cpp:222
std::size_t countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the least significant bit to the most stopping at the first 1...
Definition: MathExtras.h:109
static MCCFIInstruction createDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it...
Definition: MCDwarf.h:354
virtual bool needsStackRealignment(const MachineFunction &MF) const
needsStackRealignment - true if storage within the function requires the stack pointer to be aligned ...
void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, int Offset, const TargetInstrInfo *TII, MachineInstr::MIFlag=MachineInstr::NoFlags, bool SetNZCV=false)
emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg plus Offset.
unsigned getAlignment() const
getAlignment - Return the minimum required alignment for a register of this class.
DebugLoc findDebugLoc(instr_iterator MBBI)
findDebugLoc - find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE instructions...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
bool needsStackRealignment(const MachineFunction &MF) const override
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
unsigned getFrameRegister(const MachineFunction &MF) const override
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
static cl::opt< bool > EnableRedZone("aarch64-redzone", cl::desc("enable use of redzone on AArch64"), cl::init(false), cl::Hidden)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
void eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
eliminateCallFramePseudoInstr - This method is called during prolog/epilog code insertion to eliminat...
virtual bool hasReservedCallFrame(const MachineFunction &MF) const
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required, we reserve argument space for call sites in the function immediately on entry to the current function.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
int getFrameIndexOffset(const MachineFunction &MF, int FI) const override
getFrameIndexOffset - Returns the displacement from the frame register to the stack frame of the spec...
bool hasCalls() const
Return true if the current function has any function calls.
virtual const TargetFrameLowering * getFrameLowering() const
const MCContext & getContext() const
const DataLayout * getDataLayout() const
Deprecated in 3.7, will be removed in 3.8.
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
MachineOperand class - Representation of each machine instruction operand.
bool test(unsigned Idx) const
Definition: BitVector.h:322
int getOffsetOfLocalArea() const
getOffsetOfLocalArea - This method returns the offset of the local area from the stack pointer on ent...
Information about stack frame layout on the target.
bool needsUnwindTableEntry() const
True if this function needs an unwind table.
Definition: Function.h:354
static bool isCSRestore(MachineInstr *MI, const MCPhysReg *CSRegs)
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:123
static bool isCSSave(MachineInstr *MBBI)
virtual void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const
Emit instructions to copy a pair of physical registers.
uint64_t RoundUpToAlignment(uint64_t Value, uint64_t Align)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
Definition: MathExtras.h:609
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:227
Disable redzone.
Definition: Attributes.h:94
Representation of each machine instruction.
Definition: MachineInstr.h:51
bool hasPatchPoint() const
This method may be called any time after instruction selection is complete to determine if there is a...
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:217
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
#define I(x, y, z)
Definition: MD5.cpp:54
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSS, const AllocaInst *Alloca=nullptr)
Create a new statically sized stack object, returning a nonnegative identifier to represent it...
unsigned getReg() const
getReg - Returns the register number.
bool canUseRedZone(const MachineFunction &MF) const
Can this function use the red zone for local allocations.
virtual const TargetInstrInfo * getInstrInfo() const
static const unsigned FramePtr
#define DEBUG(X)
Definition: Debug.h:92
const char * getName(unsigned RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
MachineModuleInfo & getMMI() const
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
unsigned getPointerSize(unsigned AS=0) const
Layout pointer size FIXME: The defaults need to be removed once all of the backends/clients are updat...
Definition: DataLayout.cpp:593
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
MachineModuleInfo - This class contains meta information specific to a module.