44 #define DEBUG_TYPE "mips-lower"
46 STATISTIC(NumTailCalls,
"Number of tail calls");
54 cl::desc(
"MIPS: Don't trap on integer division by zero."),
58 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
59 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
81 unsigned Flag)
const {
87 unsigned Flag)
const {
93 unsigned Flag)
const {
99 unsigned Flag)
const {
105 unsigned Flag)
const {
479 unsigned LO = (Ty ==
MVT::i32) ? Mips::LO0 : Mips::LO0_64;
480 unsigned HI = (Ty ==
MVT::i32) ? Mips::HI0 : Mips::HI0_64;
543 "Illegal Condition Code");
684 return DAG.
getNode(Opc,
SDLoc(N), ValueIfFalse.getValueType(),
685 ValueIfFalse, FCC, ValueIfTrue, Glue);
698 unsigned ShiftRightOpc = ShiftRight.
getOpcode();
706 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.
getOperand(1))))
710 uint64_t SMPos, SMSize;
713 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
741 uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
748 if (!(CN = dyn_cast<ConstantSDNode>(And0.
getOperand(1))) ||
756 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
761 if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
768 if (!(CN = dyn_cast<ConstantSDNode>(Shl.
getOperand(1))))
776 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.
getSizeInBits()))
883 case ISD::ADD:
return lowerADD(Op, DAG);
938 case Mips::ATOMIC_LOAD_ADD_I8:
939 return emitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
940 case Mips::ATOMIC_LOAD_ADD_I16:
941 return emitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
942 case Mips::ATOMIC_LOAD_ADD_I32:
943 return emitAtomicBinary(MI, BB, 4, Mips::ADDu);
944 case Mips::ATOMIC_LOAD_ADD_I64:
945 return emitAtomicBinary(MI, BB, 8, Mips::DADDu);
947 case Mips::ATOMIC_LOAD_AND_I8:
948 return emitAtomicBinaryPartword(MI, BB, 1,
Mips::AND);
949 case Mips::ATOMIC_LOAD_AND_I16:
950 return emitAtomicBinaryPartword(MI, BB, 2,
Mips::AND);
951 case Mips::ATOMIC_LOAD_AND_I32:
952 return emitAtomicBinary(MI, BB, 4,
Mips::AND);
953 case Mips::ATOMIC_LOAD_AND_I64:
954 return emitAtomicBinary(MI, BB, 8, Mips::AND64);
956 case Mips::ATOMIC_LOAD_OR_I8:
957 return emitAtomicBinaryPartword(MI, BB, 1,
Mips::OR);
958 case Mips::ATOMIC_LOAD_OR_I16:
959 return emitAtomicBinaryPartword(MI, BB, 2,
Mips::OR);
960 case Mips::ATOMIC_LOAD_OR_I32:
961 return emitAtomicBinary(MI, BB, 4,
Mips::OR);
962 case Mips::ATOMIC_LOAD_OR_I64:
963 return emitAtomicBinary(MI, BB, 8, Mips::OR64);
965 case Mips::ATOMIC_LOAD_XOR_I8:
966 return emitAtomicBinaryPartword(MI, BB, 1,
Mips::XOR);
967 case Mips::ATOMIC_LOAD_XOR_I16:
968 return emitAtomicBinaryPartword(MI, BB, 2,
Mips::XOR);
969 case Mips::ATOMIC_LOAD_XOR_I32:
970 return emitAtomicBinary(MI, BB, 4,
Mips::XOR);
971 case Mips::ATOMIC_LOAD_XOR_I64:
972 return emitAtomicBinary(MI, BB, 8, Mips::XOR64);
974 case Mips::ATOMIC_LOAD_NAND_I8:
975 return emitAtomicBinaryPartword(MI, BB, 1, 0,
true);
976 case Mips::ATOMIC_LOAD_NAND_I16:
977 return emitAtomicBinaryPartword(MI, BB, 2, 0,
true);
978 case Mips::ATOMIC_LOAD_NAND_I32:
979 return emitAtomicBinary(MI, BB, 4, 0,
true);
980 case Mips::ATOMIC_LOAD_NAND_I64:
981 return emitAtomicBinary(MI, BB, 8, 0,
true);
983 case Mips::ATOMIC_LOAD_SUB_I8:
984 return emitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
985 case Mips::ATOMIC_LOAD_SUB_I16:
986 return emitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
987 case Mips::ATOMIC_LOAD_SUB_I32:
988 return emitAtomicBinary(MI, BB, 4, Mips::SUBu);
989 case Mips::ATOMIC_LOAD_SUB_I64:
990 return emitAtomicBinary(MI, BB, 8, Mips::DSUBu);
992 case Mips::ATOMIC_SWAP_I8:
993 return emitAtomicBinaryPartword(MI, BB, 1, 0);
994 case Mips::ATOMIC_SWAP_I16:
995 return emitAtomicBinaryPartword(MI, BB, 2, 0);
996 case Mips::ATOMIC_SWAP_I32:
997 return emitAtomicBinary(MI, BB, 4, 0);
998 case Mips::ATOMIC_SWAP_I64:
999 return emitAtomicBinary(MI, BB, 8, 0);
1001 case Mips::ATOMIC_CMP_SWAP_I8:
1002 return emitAtomicCmpSwapPartword(MI, BB, 1);
1003 case Mips::ATOMIC_CMP_SWAP_I16:
1004 return emitAtomicCmpSwapPartword(MI, BB, 2);
1005 case Mips::ATOMIC_CMP_SWAP_I32:
1006 return emitAtomicCmpSwap(MI, BB, 4);
1007 case Mips::ATOMIC_CMP_SWAP_I64:
1008 return emitAtomicCmpSwap(MI, BB, 8);
1009 case Mips::PseudoSDIV:
1010 case Mips::PseudoUDIV:
1016 case Mips::PseudoDSDIV:
1017 case Mips::PseudoDUDIV:
1024 return emitSEL_D(MI, BB);
1026 case Mips::PseudoSELECT_I:
1027 case Mips::PseudoSELECT_I64:
1028 case Mips::PseudoSELECT_S:
1029 case Mips::PseudoSELECT_D32:
1030 case Mips::PseudoSELECT_D64:
1031 return emitPseudoSELECT(MI, BB,
false, Mips::BNE);
1032 case Mips::PseudoSELECTFP_F_I:
1033 case Mips::PseudoSELECTFP_F_I64:
1034 case Mips::PseudoSELECTFP_F_S:
1035 case Mips::PseudoSELECTFP_F_D32:
1036 case Mips::PseudoSELECTFP_F_D64:
1037 return emitPseudoSELECT(MI, BB,
true, Mips::BC1F);
1038 case Mips::PseudoSELECTFP_T_I:
1039 case Mips::PseudoSELECTFP_T_I64:
1040 case Mips::PseudoSELECTFP_T_S:
1041 case Mips::PseudoSELECTFP_T_D32:
1042 case Mips::PseudoSELECTFP_T_D64:
1043 return emitPseudoSELECT(MI, BB,
true, Mips::BC1T);
1051 unsigned Size,
unsigned BinOpcode,
1053 assert((Size == 4 || Size == 8) &&
"Unsupported size for EmitAtomicBinary.");
1060 unsigned LL,
SC,
AND, NOR, ZERO, BEQ;
1079 ZERO = Mips::ZERO_64;
1124 }
else if (BinOpcode) {
1126 BuildMI(BB, DL, TII->
get(BinOpcode), StoreVal).addReg(OldVal).
addReg(Incr);
1140 unsigned SrcReg)
const {
1145 BuildMI(BB, DL, TII->
get(Mips::SEB), DstReg).addReg(SrcReg);
1150 BuildMI(BB, DL, TII->
get(Mips::SEH), DstReg).addReg(SrcReg);
1160 int64_t ShiftImm = 32 - (Size * 8);
1162 BuildMI(BB, DL, TII->
get(Mips::SLL), ScrReg).addReg(SrcReg).
addImm(ShiftImm);
1171 assert((Size == 1 || Size == 2) &&
1172 "Unsupported size for EmitAtomicBinaryPartial.");
1233 int64_t MaskImm = (Size == 1) ? 255 : 65535;
1234 BuildMI(BB, DL, TII->
get(Mips::ADDiu), MaskLSB2)
1235 .addReg(Mips::ZERO).
addImm(-4);
1237 .addReg(Ptr).
addReg(MaskLSB2);
1244 .addReg(PtrLSB2).
addImm((Size == 1) ? 3 : 2);
1247 BuildMI(BB, DL, TII->
get(Mips::ORi), MaskUpper)
1248 .addReg(Mips::ZERO).
addImm(MaskImm);
1250 .addReg(MaskUpper).
addReg(ShiftAmt);
1251 BuildMI(BB, DL, TII->
get(Mips::NOR), Mask2).addReg(Mips::ZERO).
addReg(Mask);
1252 BuildMI(BB, DL, TII->
get(Mips::SLLV), Incr2).addReg(Incr).
addReg(ShiftAmt);
1274 unsigned LL = isMicroMips ? Mips::LL_MM : Mips::LL;
1281 BuildMI(BB, DL, TII->
get(Mips::NOR), BinOpRes)
1282 .addReg(Mips::ZERO).
addReg(AndRes);
1284 }
else if (BinOpcode) {
1287 BuildMI(BB, DL, TII->
get(BinOpcode), BinOpRes).addReg(OldVal).
addReg(Incr2);
1295 .addReg(OldVal).
addReg(Mask2);
1297 .addReg(MaskedOldVal0).
addReg(NewVal);
1298 unsigned SC = isMicroMips ? Mips::SC_MM :
Mips::SC;
1311 .addReg(OldVal).
addReg(Mask);
1312 BuildMI(BB, DL, TII->
get(Mips::SRLV), SrlRes)
1313 .addReg(MaskedOldVal1).
addReg(ShiftAmt);
1314 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes);
1323 unsigned Size)
const {
1324 assert((Size == 4 || Size == 8) &&
"Unsupported size for EmitAtomicCmpSwap.");
1331 unsigned LL,
SC, ZERO, BNE, BEQ;
1334 LL = isMicroMips ? Mips::LL_MM : Mips::LL;
1335 SC = isMicroMips ? Mips::SC_MM :
Mips::SC;
1342 ZERO = Mips::ZERO_64;
1361 MF->
insert(It, loop1MBB);
1362 MF->
insert(It, loop2MBB);
1402 MipsTargetLowering::emitAtomicCmpSwapPartword(
MachineInstr *MI,
1404 unsigned Size)
const {
1405 assert((Size == 1 || Size == 2) &&
1406 "Unsupported size for EmitAtomicCmpSwapPartial.");
1445 MF->
insert(It, loop1MBB);
1446 MF->
insert(It, loop2MBB);
1475 int64_t MaskImm = (Size == 1) ? 255 : 65535;
1476 BuildMI(BB, DL, TII->
get(Mips::ADDiu), MaskLSB2)
1477 .addReg(Mips::ZERO).
addImm(-4);
1479 .addReg(Ptr).
addReg(MaskLSB2);
1486 .addReg(PtrLSB2).
addImm((Size == 1) ? 3 : 2);
1489 BuildMI(BB, DL, TII->
get(Mips::ORi), MaskUpper)
1490 .addReg(Mips::ZERO).
addImm(MaskImm);
1492 .addReg(MaskUpper).
addReg(ShiftAmt);
1493 BuildMI(BB, DL, TII->
get(Mips::NOR), Mask2).addReg(Mips::ZERO).
addReg(Mask);
1494 BuildMI(BB, DL, TII->
get(Mips::ANDi), MaskedCmpVal)
1495 .addReg(CmpVal).
addImm(MaskImm);
1496 BuildMI(BB, DL, TII->
get(Mips::SLLV), ShiftedCmpVal)
1497 .addReg(MaskedCmpVal).
addReg(ShiftAmt);
1498 BuildMI(BB, DL, TII->
get(Mips::ANDi), MaskedNewVal)
1499 .addReg(NewVal).
addImm(MaskImm);
1500 BuildMI(BB, DL, TII->
get(Mips::SLLV), ShiftedNewVal)
1501 .addReg(MaskedNewVal).
addReg(ShiftAmt);
1508 unsigned LL = isMicroMips ? Mips::LL_MM : Mips::LL;
1511 .addReg(OldVal).
addReg(Mask);
1513 .addReg(MaskedOldVal0).
addReg(ShiftedCmpVal).
addMBB(sinkMBB);
1522 .addReg(OldVal).
addReg(Mask2);
1524 .addReg(MaskedOldVal1).
addReg(ShiftedNewVal);
1525 unsigned SC = isMicroMips ? Mips::SC_MM :
Mips::SC;
1536 BuildMI(BB, DL, TII->
get(Mips::SRLV), SrlRes)
1537 .addReg(MaskedOldVal0).
addReg(ShiftAmt);
1538 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes);
1555 const auto &FGR64RegClass = TRI->
getRegClass(Mips::FGR64RegClassID);
1581 unsigned EntrySize =
1626 FCC0, Dest, CondRes);
1662 "Floating point operand expected.");
1689 if (GV->hasInternalLinkage() || (GV->hasLocalLinkage() && !isa<Function>(GV)))
1743 Entry.Node = Argument;
1745 Args.push_back(Entry);
1749 .setCallee(
CallingConv::C, PtrTy, TlsGetAddr, std::move(Args), 0);
1750 std::pair<SDValue, SDValue> CallResult =
LowerCallTo(CLI);
1774 Offset = DAG.
getLoad(PtrVT, DL,
1776 false,
false,
false, 0);
1847 const Value *SV = cast<SrcValueSDNode>(Node->
getOperand(2))->getValue();
1864 assert(((Align & (Align-1)) == 0) &&
"Expected Align to be a power of 2");
1876 unsigned ArgSizeInBytes =
1880 ArgSlotSizeInBytes),
1892 unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes;
1902 bool HasExtractInsert) {
1921 if (HasExtractInsert) {
1949 bool HasExtractInsert) {
1960 if (HasExtractInsert) {
1966 if (WidthX > WidthY)
1968 else if (WidthY > WidthX)
1987 if (WidthX > WidthY)
1989 else if (WidthY > WidthX)
2009 assert((cast<ConstantSDNode>(Op.
getOperand(0))->getZExtValue() == 0) &&
2010 "Frame address can only be determined for current frame.");
2027 assert((cast<ConstantSDNode>(Op.
getOperand(0))->getZExtValue() == 0) &&
2028 "Return address can be determined only for current frame.");
2033 unsigned RA =
ABI.
IsN64() ? Mips::RA_64 : Mips::RA;
2059 unsigned OffsetReg =
ABI.
IsN64() ? Mips::V1_64 : Mips::V1;
2060 unsigned AddrReg =
ABI.
IsN64() ? Mips::V0_64 : Mips::V0;
2145 IsSRA ? Ext : DAG.
getConstant(0, DL, VT), ShiftRightHi);
2163 SDValue Ops[] = { Chain, Ptr, Src };
2177 if ((LD->
getAlignment() >= MemVT.getSizeInBits() / 8) ||
2234 SDValue Chain,
unsigned Offset) {
2309 || cast<ConstantSDNode>
2362 static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 };
2363 static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 };
2375 else if (ArgFlags.
isZExt())
2387 else if (ArgFlags.
isZExt())
2398 bool AllocateFloatsInIntReg = State.
isVarArg() || ValNo > 1 ||
2401 bool isI64 = (ValVT ==
MVT::i32 && OrigAlign == 8);
2407 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
2410 }
else if (ValVT ==
MVT::f64 && AllocateFloatsInIntReg) {
2414 if (Reg == Mips::A1 || Reg == Mips::A3)
2428 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
2448 static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 };
2450 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2456 static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 };
2458 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2465 #include "MipsGenCallingConv.inc"
2473 assert((Reg == Mips::A0) || (Reg == Mips::A2));
2474 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
2478 MipsTargetLowering::passArgOnStack(
SDValue StackPtr,
unsigned Offset,
2498 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
2499 bool IsPICCall,
bool GlobalOrExternal,
bool InternalLinkage,
2512 if (IsPICCall && !InternalLinkage && IsCallReloc) {
2513 unsigned GPReg =
ABI.
IsN64() ? Mips::GP_64 : Mips::GP;
2515 RegsToPass.push_back(std::make_pair(GPReg,
getGlobalReg(CLI.
DAG, Ty)));
2524 for (
unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2526 RegsToPass[i].second, InFlag);
2532 for (
unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2534 RegsToPass[i].second.getValueType()));
2538 const uint32_t *Mask =
2540 assert(Mask &&
"Missing call preserved mask for calling convention");
2544 Function *
F =
G->getGlobal()->getParent()->getFunction(Sym);
2591 unsigned NextStackOffset = CCInfo.getNextStackOffset();
2595 IsTailCall = isEligibleForTailCallOptimization(
2600 "site marked musttail");
2620 std::deque< std::pair<unsigned, SDValue> > RegsToPass;
2623 CCInfo.rewindByValRegsInfo();
2626 for (
unsigned i = 0, e = ArgLocs.
size(); i != e; ++i) {
2631 bool UseUpperBits =
false;
2635 unsigned FirstByValReg, LastByValReg;
2636 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
2637 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
2640 "ByVal args of size 0 should have been ignored by front-end.");
2641 assert(ByValIdx < CCInfo.getInRegsParamsCount());
2642 assert(!IsTailCall &&
2643 "Do not tail-call optimize if there is a byval argument.");
2644 passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
2647 CCInfo.nextInRegsParam();
2670 RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
2671 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
2680 UseUpperBits =
true;
2686 UseUpperBits =
true;
2692 UseUpperBits =
true;
2700 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
2710 RegsToPass.push_back(std::make_pair(VA.
getLocReg(), Arg));
2720 Chain, Arg,
DL, IsTailCall, DAG));
2725 if (!MemOpChains.
empty())
2731 bool IsPICCall = (
ABI.
IsN64() || IsPIC);
2733 bool GlobalOrExternal =
false, InternalLinkage =
false, IsCallReloc =
false;
2742 if (InternalLinkage)
2758 GlobalOrExternal =
true;
2761 const char *Sym = S->getSymbol();
2777 GlobalOrExternal =
true;
2783 getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, InternalLinkage,
2784 IsCallReloc, CLI, Callee, Chain);
2799 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
2805 SDValue MipsTargetLowering::LowerCallResult(
2817 for (
unsigned i = 0; i != RVLocs.
size(); ++i) {
2819 assert(VA.
isRegLoc() &&
"Can only return in registers!");
2822 RVLocs[i].getLocVT(), InFlag);
2827 unsigned ValSizeInBits = Ins[i].ArgVT.getSizeInBits();
2928 MipsTargetLowering::LowerFormalArguments(
SDValue Chain,
2942 std::vector<SDValue> OutChains;
2952 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg);
2954 CCInfo.getInRegsParamsCount() > 0);
2956 unsigned CurArgIdx = 0;
2957 CCInfo.rewindByValRegsInfo();
2959 for (
unsigned i = 0, e = ArgLocs.
size(); i != e; ++i) {
2961 if (Ins[i].isOrigArg()) {
2962 std::advance(FuncArg, Ins[i].getOrigArgIndex() - CurArgIdx);
2963 CurArgIdx = Ins[i].getOrigArgIndex();
2970 assert(Ins[i].isOrigArg() &&
"Byval arguments cannot be implicit");
2971 unsigned FirstByValReg, LastByValReg;
2972 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
2973 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
2976 "ByVal args of size 0 should have been ignored by front-end.");
2977 assert(ByValIdx < CCInfo.getInRegsParamsCount());
2978 copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg,
2979 FirstByValReg, LastByValReg, VA, CCInfo);
2980 CCInfo.nextInRegsParam();
3011 ArgValue, ArgValue2);
3038 false,
false,
false, 0);
3039 OutChains.push_back(ArgValue.
getValue(1));
3047 for (
unsigned i = 0, e = ArgLocs.
size(); i != e; ++i) {
3051 if (Ins[i].Flags.
isSRet()) {
3065 writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo);
3069 if (!OutChains.empty()) {
3070 OutChains.push_back(Chain);
3087 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
3088 return CCInfo.CheckReturn(Outs, RetCC_Mips);
3092 MipsTargetLowering::shouldSignExtendTypeInLibCall(
EVT Type,
bool IsSigned)
const {
3101 MipsTargetLowering::LowerReturn(
SDValue Chain,
3121 for (
unsigned i = 0; i != RVLocs.
size(); ++i) {
3124 assert(VA.
isRegLoc() &&
"Can only return in registers!");
3125 bool UseUpperBits =
false;
3136 UseUpperBits =
true;
3142 UseUpperBits =
true;
3148 UseUpperBits =
true;
3156 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
3182 unsigned V0 =
ABI.
IsN64() ? Mips::V0_64 : Mips::V0;
3193 RetOps.push_back(Flag);
3206 MipsTargetLowering::getConstraintType(
StringRef Constraint)
const {
3218 if (Constraint.
size() == 1) {
3219 switch (Constraint[0]) {
3233 if (Constraint ==
"ZC")
3243 MipsTargetLowering::getSingleConstraintMatchWeight(
3244 AsmOperandInfo &
info,
const char *constraint)
const {
3246 Value *CallOperandVal = info.CallOperandVal;
3249 if (!CallOperandVal)
3251 Type *type = CallOperandVal->
getType();
3253 switch (*constraint) {
3282 if (isa<ConstantInt>(CallOperandVal))
3297 unsigned long long &Reg) {
3298 if (C.
front() !=
'{' || C.
back() !=
'}')
3299 return std::make_pair(
false,
false);
3303 I = std::find_if(B, E, std::ptr_fun(isdigit));
3309 return std::make_pair(
true,
false);
3316 std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering::
3317 parseRegForInlineAsmConstraint(
StringRef C,
MVT VT)
const {
3322 unsigned long long Reg;
3327 return std::make_pair(0U,
nullptr);
3329 if ((Prefix ==
"hi" || Prefix ==
"lo")) {
3332 return std::make_pair(0U,
nullptr);
3335 Mips::HI32RegClassID : Mips::LO32RegClassID);
3336 return std::make_pair(*(RC->
begin()), RC);
3342 return std::make_pair(0U,
nullptr);
3345 .Case(
"$msair", Mips::MSAIR)
3346 .
Case(
"$msacsr", Mips::MSACSR)
3347 .
Case(
"$msaaccess", Mips::MSAAccess)
3348 .
Case(
"$msasave", Mips::MSASave)
3349 .
Case(
"$msamodify", Mips::MSAModify)
3350 .
Case(
"$msarequest", Mips::MSARequest)
3351 .
Case(
"$msamap", Mips::MSAMap)
3352 .
Case(
"$msaunmap", Mips::MSAUnmap)
3356 return std::make_pair(0U,
nullptr);
3359 return std::make_pair(Reg, RC);
3363 return std::make_pair(0U,
nullptr);
3365 if (Prefix ==
"$f") {
3373 if (RC == &Mips::AFGR64RegClass) {
3374 assert(Reg % 2 == 0);
3377 }
else if (Prefix ==
"$fcc")
3379 else if (Prefix ==
"$w") {
3382 assert(Prefix ==
"$");
3386 assert(Reg < RC->getNumRegs());
3387 return std::make_pair(*(RC->
begin() +
Reg), RC);
3393 std::pair<unsigned, const TargetRegisterClass *>
3397 if (Constraint.
size() == 1) {
3398 switch (Constraint[0]) {
3404 return std::make_pair(0U, &Mips::CPU16RegsRegClass);
3405 return std::make_pair(0U, &Mips::GPR32RegClass);
3408 return std::make_pair(0U, &Mips::GPR32RegClass);
3410 return std::make_pair(0U, &Mips::GPR64RegClass);
3412 return std::make_pair(0U,
nullptr);
3415 return std::make_pair(0U, &Mips::MSA128BRegClass);
3417 return std::make_pair(0U, &Mips::MSA128HRegClass);
3419 return std::make_pair(0U, &Mips::MSA128WRegClass);
3421 return std::make_pair(0U, &Mips::MSA128DRegClass);
3423 return std::make_pair(0U, &Mips::FGR32RegClass);
3426 return std::make_pair(0U, &Mips::FGR64RegClass);
3427 return std::make_pair(0U, &Mips::AFGR64RegClass);
3432 return std::make_pair((
unsigned)Mips::T9, &Mips::GPR32RegClass);
3433 assert(VT ==
MVT::i64 &&
"Unexpected type.");
3434 return std::make_pair((
unsigned)Mips::T9_64, &Mips::GPR64RegClass);
3437 return std::make_pair((
unsigned)Mips::LO0, &Mips::LO32RegClass);
3438 return std::make_pair((
unsigned)Mips::LO0_64, &Mips::LO64RegClass);
3442 return std::make_pair(0U,
nullptr);
3446 std::pair<unsigned, const TargetRegisterClass *> R;
3447 R = parseRegForInlineAsmConstraint(Constraint, VT);
3457 void MipsTargetLowering::LowerAsmOperandForConstraint(
SDValue Op,
3458 std::string &Constraint,
3459 std::vector<SDValue>&Ops,
3465 if (Constraint.length() > 1)
return;
3467 char ConstraintLetter = Constraint[0];
3468 switch (ConstraintLetter) {
3474 int64_t Val = C->getSExtValue();
3484 int64_t Val = C->getZExtValue();
3494 uint64_t Val = (uint64_t)C->getZExtValue();
3504 int64_t Val = C->getSExtValue();
3505 if ((
isInt<32>(Val)) && ((Val & 0xffff) == 0)){
3514 int64_t Val = C->getSExtValue();
3515 if ((Val >= -65535) && (Val <= -1)) {
3524 int64_t Val = C->getSExtValue();
3525 if ((isInt<15>(Val))) {
3534 int64_t Val = C->getSExtValue();
3535 if ((Val <= 65535) && (Val >= 1)) {
3544 Ops.push_back(Result);
3551 bool MipsTargetLowering::isLegalAddressingMode(
const DataLayout &DL,
3553 unsigned AS)
const {
3578 EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size,
unsigned DstAlign,
3580 bool IsMemset,
bool ZeroMemset,
3589 bool MipsTargetLowering::isFPImmLegal(
const APFloat &Imm,
EVT VT)
const {
3597 unsigned MipsTargetLowering::getJumpTableEncoding()
const {
3604 bool MipsTargetLowering::useSoftFloat()
const {
3608 void MipsTargetLowering::copyByValRegs(
3611 const Argument *FuncArg,
unsigned FirstReg,
unsigned LastReg,
3616 unsigned NumRegs = LastReg - FirstReg;
3617 unsigned RegAreaSize = NumRegs * GPRSizeInBytes;
3618 unsigned FrameObjSize = std::max(Flags.
getByValSize(), RegAreaSize);
3625 (
int)((ByValArgRegs.
size() - FirstReg) * GPRSizeInBytes);
3642 for (
unsigned I = 0;
I < NumRegs; ++
I) {
3643 unsigned ArgReg = ByValArgRegs[FirstReg +
I];
3644 unsigned VReg =
addLiveIn(MF, ArgReg, RC);
3645 unsigned Offset =
I * GPRSizeInBytes;
3651 OutChains.push_back(Store);
3656 void MipsTargetLowering::passByValArg(
3658 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
3664 unsigned OffsetInBytes = 0;
3669 unsigned NumRegs = LastReg - FirstReg;
3673 bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes);
3677 for (; I < NumRegs - LeftoverBytes; ++
I, OffsetInBytes += RegSizeInBytes) {
3684 unsigned ArgReg = ArgRegs[FirstReg +
I];
3685 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal));
3689 if (ByValSizeInBytes == OffsetInBytes)
3693 if (LeftoverBytes) {
3696 for (
unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0;
3697 OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) {
3698 unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes;
3700 if (RemainingSizeInBytes < LoadSizeInBytes)
3717 Shamt = TotalBytesLoaded * 8;
3719 Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8;
3729 OffsetInBytes += LoadSizeInBytes;
3730 TotalBytesLoaded += LoadSizeInBytes;
3731 Alignment =
std::min(Alignment, LoadSizeInBytes);
3734 unsigned ArgReg = ArgRegs[FirstReg +
I];
3735 RegsToPass.push_back(std::make_pair(ArgReg, Val));
3741 unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes;
3746 Chain = DAG.
getMemcpy(Chain, DL, Dst, Src,
3748 Alignment,
false,
false,
3754 void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
3770 if (ArgRegs.
size() == Idx)
3776 (
int)(RegSizeInBytes * (ArgRegs.
size() - Idx));
3788 for (
unsigned I = Idx; I < ArgRegs.
size();
3789 ++
I, VaArgOffset += RegSizeInBytes) {
3790 unsigned Reg =
addLiveIn(MF, ArgRegs[I], RC);
3796 cast<StoreSDNode>(Store.
getNode())->getMemOperand()->setValue(
3798 OutChains.push_back(Store);
3803 unsigned Align)
const {
3806 assert(Size &&
"Byval argument's size shouldn't be 0.");
3810 unsigned FirstReg = 0;
3811 unsigned NumRegs = 0;
3822 assert(!(Align % RegSizeInBytes) &&
3823 "Byval argument's alignment should be a multiple of"
3832 if ((Align > RegSizeInBytes) && (FirstReg % 2)) {
3833 State->
AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]);
3839 for (
unsigned I = FirstReg; Size > 0 && (I < IntArgRegs.
size());
3840 Size -= RegSizeInBytes, ++
I, ++NumRegs)
3849 bool isFPCmp,
unsigned Opc)
const {
3851 "Subtarget already supports SELECT nodes with the use of"
3852 "conditional-move instructions.");
3932 .Case(
"$28", Mips::GP_64)
3938 .Case(
"$28", Mips::GP)
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
bool isInt< 32 >(int64_t x)
const MipsTargetLowering * createMipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
static unsigned getBitWidth(Type *Ty, const DataLayout &DL)
Returns the bitwidth of the given scalar or pointer type (if unknown returns 0).
void setFrameAddressIsTaken(bool T)
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasExtractInsert)
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
static MVT getIntegerVT(unsigned BitWidth)
void push_back(const T &Elt)
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
A parsed version of the target data layout string in and methods for querying it. ...
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
SDValue getValue(unsigned R) const
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
const char * getSymbol() const
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
unsigned GetCalleeAllocdArgSizeInBytes(CallingConv::ID CC) const
Obtain the size of the area allocated by the callee for arguments.
LLVMContext * getContext() const
LLVM Argument representation.
SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N)
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, SDLoc DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd)...
const MipsSubtarget & Subtarget
STATISTIC(NumFunctions,"Total number of functions")
size_t size() const
size - Get the string size.
static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA, EVT ArgVT, SDLoc DL, SelectionDAG &DAG)
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
BR_CC - Conditional branch.
LocInfo getLocInfo() const
static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG, bool IsLittle)
MO_TLSLDM - Represents the offset into the global offset table at which.
static MVT getVectorVT(MVT VT, unsigned NumElements)
const MipsTargetLowering * createMips16TargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
Create MipsTargetLowering objects.
static MachinePointerInfo getJumpTable()
getJumpTable - Return a MachinePointerInfo record that refers to a jump table entry.
unsigned EnableFastISel
EnableFastISel - This flag enables fast-path instruction selection which trades away generated code q...
const TargetMachine & getTargetMachine() const
static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
MO_GOT_HI16/LO16, MO_CALL_HI16/LO16 - Relocations used for large GOTs.
SDValue getMergeValues(ArrayRef< SDValue > Ops, SDLoc dl)
Create a MERGE_VALUES node from the given operands.
static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
MO_TLSGD - Represents the offset into the global offset table at which.
unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
bool getAsUnsignedInteger(StringRef Str, unsigned Radix, unsigned long long &Result)
Helper functions for StringRef::getAsInteger.
MipsTargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain...
const GlobalValue * getGlobal() const
CallingConv::ID getCallingConv() const
const MipsInstrInfo * getInstrInfo() const override
static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool HasExtractInsert)
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Type * getTypeForEVT(LLVMContext &Context) const
getTypeForEVT - This method returns an LLVM type corresponding to the specified EVT.
unsigned getSizeInBits() const
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
unsigned getByValSize() const
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
unsigned getValueSizeInBits() const
Returns the size of the value in bits.
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *fromMBB)
transferSuccessorsAndUpdatePHIs - Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor blocks which refer to fromMBB to refer to this.
const SDValue & getOperand(unsigned Num) const
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
void setVarArgsFrameIndex(int Index)
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags=0)
StringSwitch & Case(const char(&S)[N], const T &Value)
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
ReplaceNodeResults - Replace the results of node with an illegal result type with new values built ou...
const SDValue & getBasePtr() const
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - get the ISD::SETCC result ValueType
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
void LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but leg...
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag=true)
Reports a serious error, calling any installed error handler.
SDValue getExternalSymbol(const char *Sym, EVT VT)
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
SDValue getMemcpy(SDValue Chain, SDLoc dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
static MachinePointerInfo getFixedStack(int FI, int64_t offset=0)
getFixedStack - Return a MachinePointerInfo record that refers to the the specified FrameIndex...
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
APInt Not(const APInt &APIVal)
Bitwise complement function.
static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size)
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
bool isVector() const
isVector - Return true if this is a vector value type.
SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
const HexagonInstrInfo * TII
static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG)
unsigned getGPRSizeInBytes() const
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn, const TargetLowering::CallLoweringInfo &CLI)
Shift and rotation operations.
bool systemSupportsUnalignedAccess() const
Does the system support unaligned memory access.
static unsigned addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
const TargetRegisterClass * getRegClass(unsigned i) const
getRegClass - Returns the register class associated with the enumeration value.
unsigned getSRetReturnReg() const
bool hasInternalLinkage() const
MachineFunction & getMachineFunction() const
static void advance(T &it, size_t Val)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
SDValue getTargetGlobalAddress(const GlobalValue *GV, SDLoc DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
virtual TargetLoweringObjectFile * getObjFileLowering() const
void addLoc(const CCValAssign &V)
SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const
iterator begin() const
begin/end - Return all of the registers in this class.
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
Number of individual test Apply this number of consecutive mutations to each input exit after the first new interesting input is found the minimized corpus is saved into the first input directory Number of jobs to run If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
static std::pair< bool, bool > parsePhysicalReg(StringRef C, StringRef &Prefix, unsigned long long &Reg)
This is a helper function to parse a physical register string and split it into non-numeric and numer...
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
bool hasExtractInsert() const
Features related to the presence of specific instructions.
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG...
bool isUpperBitsInLoc() const
bool inMips16HardFloat() const
static Mips::CondCode condCodeToFCC(ISD::CondCode CC)
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
SDValue getAddrGlobalLargeGOT(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned HiFlag, unsigned LoFlag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
SmallVector< ISD::InputArg, 32 > Ins
STACKSAVE - STACKSAVE has one operand, an input chain.
FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to first (possible) on-stack ar...
MachineFunction & getMachineFunction() const
SDValue getCALLSEQ_START(SDValue Chain, SDValue Op, SDLoc DL)
Return a new CALLSEQ_START node, which always must have a glue result (to ensure it's not CSE'd)...
unsigned getLocReg() const
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
static const MCPhysReg Mips64DPRegs[8]
SDValue getRegisterMask(const uint32_t *RegMask)
bool hasStructRetAttr() const
Determine if the function returns a structure through first pointer argument.
static bool invertFPCondCodeUser(Mips::CondCode CC)
This function returns true if the floating point conditional branches and conditional moves which use...
Simple integer binary arithmetic operators.
void addInRegsParamInfo(unsigned RegBegin, unsigned RegEnd)
SmallVector< ISD::OutputArg, 32 > Outs
static SpecialCallingConvType getSpecialCallingConvForCallee(const SDNode *Callee, const MipsSubtarget &Subtarget)
Determine the SpecialCallingConvType for the given callee.
bool IsConstantInSmallSection(const Constant *CN, const TargetMachine &TM) const
Return true if this constant should be placed into small data section.
const MachineJumpTableInfo * getJumpTableInfo() const
getJumpTableInfo - Return the jump table info object for the current function.
unsigned getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const override
Return the register ID of the name passed in.
const SDValue & getBasePtr() const
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
EVT getMemoryVT() const
Return the type of the in-memory value.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
SDValue getAddrLocal(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, bool IsN32OrN64) const
SDValue getAddrGlobal(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
size_t size() const
size - Get the array size.
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
const DataLayout & getDataLayout() const
unsigned getKillRegState(bool B)
const BasicBlock * getBasicBlock() const
getBasicBlock - Return the LLVM basic block that this instance corresponded to originally.
This class is used to represent ISD::STORE nodes.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
static unsigned getNextIntArgReg(unsigned Reg)
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
const TargetFrameLowering * getFrameLowering() const override
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
Flag
These should be considered private to the implementation of the MCInstrDesc class.
TargetInstrInfo - Interface to description of machine instruction set.
SDNode * getNode() const
get the SDNode which holds the desired result
unsigned getEntrySize(const DataLayout &TD) const
getEntrySize - Return the size of each entry in the jump table.
bundle_iterator< MachineInstr, instr_iterator > iterator
A self-contained host- and target-independent arbitrary-precision floating-point software implementat...
A switch()-like statement whose cases are string literals.
EK_GPRel64BlockAddress - Each entry is an address of block, encoded with a relocation as gp-relative...
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set, or Regs.size() if they are all allocated.
initializer< Ty > init(const Ty &Val)
virtual FastISel * createFastISel(FunctionLoweringInfo &, const TargetLibraryInfo *) const
This method returns a target specific FastISel object, or null if the target does not support "fast" ...
static mvt_range fp_vector_valuetypes()
static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
MO_GOT_CALL - Represents the offset into the global offset table at which the address of a call site ...
std::size_t countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the least significant bit to the most stopping at the first 1...
MVT - Machine Value Type.
LLVM Basic Block Representation.
const SDValue & getOperand(unsigned i) const
The instances of the Type class are immutable: once they are created, they are never changed...
This is an important class for using LLVM in a threaded context.
void setTargetDAGCombine(ISD::NodeType NT)
Targets should invoke this method for each target independent node that they want to provide a custom...
bool isNonTemporal() const
bool isVectorTy() const
isVectorTy - True if this is an instance of VectorType.
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE...
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
const ArrayRef< MCPhysReg > GetByValArgRegs() const
The registers to use for byval arguments.
const Constant * getConstVal() const
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
const MachineOperand & getOperand(unsigned i) const
char back() const
back - Get the last character in the string.
bool isBeforeLegalizeOps() const
static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, SDValue Chain, unsigned Offset)
bool isFloatTy() const
isFloatTy - Return true if this is 'float', a 32-bit IEEE fp type.
SDValue getAddrNonPIC(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG) const
APInt Or(const APInt &LHS, const APInt &RHS)
Bitwise OR function for APInt.
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
void HandleByVal(CCState *, unsigned &, unsigned) const override
Target-specific cleanup for formal ByVal parameters.
static mvt_range fp_valuetypes()
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT)
#define LLVM_ATTRIBUTE_UNUSED
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang","erlang-compatible garbage collector")
static EVT getFloatingPointVT(unsigned BitWidth)
getFloatingPointVT - Returns the EVT that represents a floating point type with the given number of b...
SDValue getTargetConstant(uint64_t Val, SDLoc DL, EVT VT, bool isOpaque=false)
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
unsigned getOpcode() const
TRAP - Trapping instruction.
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Class to represent integer types.
bool useSoftFloat() const
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool Immutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
static const MipsTargetLowering * create(const MipsTargetMachine &TM, const MipsSubtarget &STI)
bool inMicroMipsMode() const
const SDValue & getValue() const
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
bool inMips16Mode() const
SDValue getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes())
Bit counting operators with an undefined result for zero inputs.
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
EVT - Extended Value Type.
std::vector< ArgListEntry > ArgListTy
unsigned getNextStackOffset() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
MachinePointerInfo - This class contains a discriminated union of information about pointers in memor...
uint64_t getConstantOperandVal(unsigned Num) const
Helper method returns the integer value of a ConstantSDNode operand.
virtual SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const
Returns relocation base for the given PIC jumptable.
MO_GOTTPREL - Represents the offset from the thread pointer (Initial.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
const BlockAddress * getBlockAddress() const
bool isShiftedMask_64(uint64_t Value)
isShiftedMask_64 - This function returns true if the argument contains a non-empty sequence of ones w...
const MachinePointerInfo & getPointerInfo() const
void setIsKill(bool Val=true)
unsigned getByValAlign() const
static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, SDValue Chain, SDValue Src, unsigned Offset)
SDValue getTargetConstantPool(const Constant *C, EVT VT, unsigned Align=0, int Offset=0, unsigned char TargetFlags=0)
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned char TargetFlags=0)
MO_GOT16 - Represents the offset into the global offset table at which the address the relocation ent...
TokenFactor - This node takes multiple tokens as input and produces a single token result...
bool isMustTailCall() const
Tests if this call site must be tail call optimized.
CCState - This class holds information needed while lowering arguments and return values...
const char * const_iterator
bool startswith(StringRef Prefix) const
Check if this string starts with the given Prefix.
unsigned countPopulation(T Value)
Count the number of set bits in a value.
virtual unsigned getJumpTableEncoding() const
Return the entry encoding for a jump table in the current function.
unsigned getGlobalBaseReg()
const MipsRegisterInfo * getRegisterInfo() const override
uint64_t getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
void setExceptionPointerRegister(unsigned R)
If set to a physical register, this sets the register that receives the exception address on entry to...
static MachineBasicBlock * insertDivByZeroTrap(MachineInstr *MI, MachineBasicBlock &MBB, const TargetInstrInfo &TII, bool Is64Bit)
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Type * getType() const
All values are typed, get the type of this value.
Provides information about what library functions are available for the current target.
static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, ArrayRef< MCPhysReg > F64Regs)
CCValAssign - Represent assignment of one arg/retval to a location.
const ArrayRef< MCPhysReg > GetVarArgRegs() const
The registers to use for the variable argument list.
BRCOND - Conditional branch.
Information about stack frame layout on the target.
static cl::opt< bool > NoZeroDivCheck("mno-check-zero-division", cl::Hidden, cl::desc("MIPS: Don't trap on integer division by zero."), cl::init(false))
const SDValue & getChain() const
Byte Swap and Counting operators.
FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions and truncation for half-preci...
CHAIN = SC CHAIN, Imm128 - System call.
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
static IntegerType * getIntNTy(LLVMContext &C, unsigned N)
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Represents one node in the SelectionDAG.
CondCode getSetCCInverse(CondCode Operation, bool isInteger)
getSetCCInverse - Return the operation corresponding to !(X op Y), where 'op' is a valid SetCC operat...
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
R Default(const T &Value) const
static mvt_range integer_valuetypes()
static bool CC_Mips(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State) LLVM_ATTRIBUTE_UNUSED
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
createFastISel - This method returns a target specific FastISel object, or null if the target does no...
void setExceptionSelectorRegister(unsigned R)
If set to a physical register, this sets the register that receives the exception typeid on entry to ...
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
getCallPreservedMask - Return a mask of call-preserved registers for the given calling convention on ...
Select(COND, TRUEVAL, FALSEVAL).
void setMinFunctionAlignment(unsigned Align)
Set the target's minimum function alignment (in log2(bytes))
int64_t getSExtValue() const
bool isIntegerTy() const
isIntegerTy - True if this is an instance of IntegerType.
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
Return the register class that should be used for the specified value type.
ZERO_EXTEND - Used for integer types, zeroing the new bits.
AddrMode
ARM Addressing Modes.
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
ANY_EXTEND - Used for integer types. The high bits are undefined.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
uint64_t RoundUpToAlignment(uint64_t Value, uint64_t Align)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op)
MO_TPREL_HI/LO - Represents the hi and low part of the offset from.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
BR_JT - Jumptable branch.
static MachinePointerInfo getGOT()
getGOT - Return a MachinePointerInfo record that refers to a GOT entry.
Representation of each machine instruction.
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the source.
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
static const uint32_t * getMips16RetHelperMask()
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned char TargetFlags=0)
SmallVector< SDValue, 32 > OutVals
bool isValid() const
isValid - Return true if this is a valid simple valuetype.
void setFormalArgInfo(unsigned Size, bool HasByval)
Bitwise operators - logical and, logical or, logical xor.
SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const
bool hasAnyUseOfValue(unsigned Value) const
Return true if there are any use of the indicated value.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static cl::opt< bool > LargeGOT("mxgot", cl::Hidden, cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false))
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
MachinePointerInfo callPtrInfo(StringRef Name)
Create a MachinePointerInfo that has a MipsCallEntr object representing a GOT entry for an external f...
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
bool isSingleFloat() const
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
void setReg(unsigned Reg)
Change the register this operand corresponds to.
Fast - This calling convention attempts to make calls as fast as possible (e.g.
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
bool IsGlobalInSmallSection(const GlobalValue *GV, const TargetMachine &TM, SectionKind Kind) const
Return true if this global address should be placed into small data/bss section.
void setSubReg(unsigned subReg)
void setStackPointerRegisterToSaveRestore(unsigned R)
If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
virtual void getOpndList(SmallVectorImpl< SDValue > &Ops, std::deque< std::pair< unsigned, SDValue > > &RegsToPass, bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const
This function fills Ops, which is the list of operands that will later be used when a function call n...
static CCValAssign getMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
FSINCOS - Compute both fsin and fcos as a single operation.
bool isInt< 16 >(int64_t x)
unsigned MaxStoresPerMemcpy
Specify maximum bytes of store instructions per memcpy call.
EVT getValueType() const
Return the ValueType of the referenced return value.
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 'eh_return' gcc dwarf builtin...
int getVarArgsFrameIndex() const
SDValue getConstant(uint64_t Val, SDLoc DL, EVT VT, bool isTarget=false, bool isOpaque=false)
TLSModel::Model getTLSModel(const GlobalValue *GV) const
Returns the TLS model which should be used for the given global variable.
unsigned getReg() const
getReg - Returns the register number.
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
char front() const
front - Get the first character in the string.
void insert(iterator MBBI, MachineBasicBlock *MBB)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
void setReturnAddressIsTaken(bool s)
unsigned getAlignment() const
void setMinStackArgumentAlignment(unsigned Align)
Set the minimum stack alignment of an argument (in log2(bytes)).
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
LLVM Value Representation.
FMA - Perform a * b + c with no intermediate rounding step.
SDValue getRegister(unsigned Reg, EVT VT)
bool isZero() const
Returns true if and only if the float is plus or minus zero.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
void setInsertFencesForAtomic(bool fence)
Set if the DAG builder should automatically insert fences and reduce the order of atomic memory opera...
bool isTruncatingStore() const
Return true if the op does a truncation before store.
SDValue getValueType(EVT)
bool isUInt< 16 >(uint64_t x)
BasicBlockListType::iterator iterator
void ReplaceAllUsesOfValueWith(SDValue From, SDValue To)
Replace any uses of From with To, leaving uses of other values produced by From.Val alone...
C - The default llvm calling convention, compatible with C.
StringRef - Represent a constant reference to a string, i.e.
SetCC operator - This evaluates to a true value iff the condition is true.
unsigned getOrigAlign() const
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml","ocaml 3.10-compatible collector")
unsigned getMinStackArgumentAlignment() const
Return the minimum stack alignment of an argument.
SDValue getSetCC(SDLoc DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except that the first operand is an imme...
unsigned getLocMemOffset() const
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val) This corresponds to "store atomic" instruction.
TRUNCATE - Completely drop the high bits.
const char * getTargetNodeName(unsigned Opcode) const override
getTargetNodeName - This method returns the name of a target specific
unsigned getAlignment() const
unsigned AllocateReg(unsigned Reg)
AllocateReg - Attempt to allocate one register.
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
Examine constraint string and operand type and determine a weight value.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, SDValue False, SDLoc DL)
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
getIntegerVT - Returns the EVT that represents an integer with the given number of bits...
unsigned AllocateStack(unsigned Size, unsigned Align)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
void addSuccessor(MachineBasicBlock *succ, uint32_t weight=0)
addSuccessor - Add succ as a successor of this MachineBasicBlock.
static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) This corresponds to "load atomic" instruction.
EVT changeVectorElementTypeToInteger() const
changeVectorElementTypeToInteger - Return a vector with the same number of elements as this vector...
SDValue getAddrGPRel(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG) const
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
SDValue getIntPtrConstant(uint64_t Val, SDLoc DL, bool isTarget=false)
SDValue getMemIntrinsicNode(unsigned Opcode, SDLoc dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, unsigned Align=0, bool Vol=false, bool ReadMem=true, bool WriteMem=true, unsigned Size=0)
Creates a MemIntrinsicNode that may produce a result and takes a list of operands.
void setSRetReturnReg(unsigned Reg)
uint64_t getZExtValue() const
This class is used to represent ISD::LOAD nodes.
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary...