31 #define GET_REGINFO_MC_DESC
32 #include "ARMGenRegisterInfo.inc"
44 Info =
"deprecated since v7, use 'isb'";
51 Info =
"deprecated since v7, use 'dsb'";
59 Info =
"deprecated since v7, use 'dmb'";
70 Info =
"applying IT instruction to more than one subsequent instruction is "
81 "cannot predicate thumb instructions");
88 Info =
"use of SP or PC in the list is deprecated";
98 "cannot predicate thumb instructions");
101 bool ListContainsPC =
false, ListContainsLR =
false;
108 ListContainsLR =
true;
111 ListContainsPC =
true;
114 Info =
"use of SP in the list is deprecated";
119 if (ListContainsPC && ListContainsLR) {
120 Info =
"use of LR and PC simultaneously in the list is deprecated";
127 #define GET_INSTRINFO_MC_DESC
128 #include "ARMGenInstrInfo.inc"
130 #define GET_SUBTARGETINFO_MC_DESC
131 #include "ARMGenSubtargetInfo.inc"
137 bool NoCPU = CPU ==
"generic" || CPU.
empty();
138 std::string ARMArchFeature;
147 ARMArchFeature =
"+v8,+db,+fp-armv8,+neon,+t2dsp,+mp,+hwdiv,+hwdiv-arm,"
148 "+trustzone,+t2xtpk,+crypto,+crc";
151 ARMArchFeature =
"+v8";
158 ARMArchFeature =
"+v8.1a,+db,+fp-armv8,+neon,+t2dsp,+mp,+hwdiv,+hwdiv-arm,"
159 "+trustzone,+t2xtpk,+crypto,+crc";
162 ARMArchFeature =
"+v8.1a";
168 ARMArchFeature =
"+v7,+noarm,+db,+hwdiv,+mclass";
171 ARMArchFeature =
"+v7";
177 ARMArchFeature =
"+v7,+noarm,+db,+hwdiv,+t2dsp,+t2xtpk,+mclass";
180 ARMArchFeature =
"+v7";
186 ARMArchFeature =
"+v7,+swift,+neon,+db,+t2dsp,+ras";
189 ARMArchFeature =
"+v7";
198 ARMArchFeature =
"+v7,+neon,+db,+t2dsp,+t2xtpk";
201 ARMArchFeature =
"+v7";
204 ARMArchFeature =
"+v6t2";
207 ARMArchFeature =
"+v6k";
213 ARMArchFeature =
"+v6m,+noarm,+mclass";
215 ARMArchFeature =
"+v6";
218 ARMArchFeature =
"+v6";
221 ARMArchFeature =
"+v5te";
224 ARMArchFeature =
"+v5t";
227 ARMArchFeature =
"+v4t";
234 if (ARMArchFeature.empty())
235 ARMArchFeature =
"+thumb-mode";
237 ARMArchFeature +=
",+thumb-mode";
241 if (ARMArchFeature.empty())
242 ARMArchFeature =
"+nacl-trap";
244 ARMArchFeature +=
",+nacl-trap";
247 return ARMArchFeature;
255 ArchFS = (
Twine(ArchFS) +
"," + FS).str();
260 return createARMMCSubtargetInfoImpl(TT, CPU, ArchFS);
265 InitARMMCInstrInfo(X);
271 InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
276 const Triple &TheTriple) {
315 bool DWARFMustBeAtTheEnd) {
320 unsigned SyntaxVariant,
324 if (SyntaxVariant == 0)
357 bool evaluateBranch(
const MCInst &Inst, uint64_t Addr,
358 uint64_t Size, uint64_t &
Target)
const override {
373 return new ARMMCInstrAnalysis(Info);
MCELFStreamer * createARMELFStreamer(MCContext &Context, MCAsmBackend &TAB, raw_pwrite_stream &OS, MCCodeEmitter *Emitter, bool RelaxAll, bool IsThumb)
static bool isUnconditionalBranch(unsigned int Opcode)
static MCStreamer * createARMMachOStreamer(MCContext &Ctx, MCAsmBackend &MAB, raw_pwrite_stream &OS, MCCodeEmitter *Emitter, bool RelaxAll, bool DWARFMustBeAtTheEnd)
int getDwarfRegNum(unsigned RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)
RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target...
static MCInstrInfo * createARMMCInstrInfo()
static bool getITDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info)
MCRelocationInfo * createARMMachORelocationInfo(MCContext &Ctx)
Construct ARM Mach-O relocation info.
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.
void LLVMInitializeARMTargetMC()
static bool isThumb(const MCSubtargetInfo &STI)
static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)
bool isOSWindows() const
Tests whether the OS is Windows.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
MCStreamer * createARMWinCOFFStreamer(MCContext &Context, MCAsmBackend &MAB, raw_pwrite_stream &OS, MCCodeEmitter *Emitter, bool RelaxAll)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Reg
All possible values of the reg field in the ModR/M byte.
static void RegisterCOFFStreamer(Target &T, Target::COFFStreamerCtorTy Fn)
static MCInstPrinter * createARMMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
bool isWindowsMSVCEnvironment() const
Context object for machine code objects.
MCAsmBackend * createARMLEAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU)
unsigned getReg() const
Returns the register number.
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
MCAsmBackend * createThumbBEAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU)
void addInitialFrameState(const MCCFIInstruction &Inst)
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
MCTargetStreamer * createARMTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, bool isVerboseAsm)
Instances of this class represent a single low-level machine instruction.
MCRelocationInfo * createMCRelocationInfo(const Triple &TT, MCContext &Ctx)
SubArchType getSubArch() const
getSubArch - get the parsed subarchitecture type for this triple.
virtual bool isUnconditionalBranch(const MCInst &Inst) const
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
This class is intended to be used as a base class for asm properties and features specific to the tar...
static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.
MCTargetStreamer * createARMObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
static MCRegisterInfo * createARMMCRegisterInfo(const Triple &Triple)
Streaming machine code generation interface.
static MCCFIInstruction createDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it...
static void RegisterMachOStreamer(Target &T, Target::MachOStreamerCtorTy Fn)
MCCodeEmitter - Generic instruction encoding interface.
Interface to description of machine instruction set.
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang","erlang-compatible garbage collector")
Create MCExprs from relocations found in an object file.
static void RegisterMCCodeGenInfo(Target &T, Target::MCCodeGenInfoCtorFnTy Fn)
RegisterMCCodeGenInfo - Register a MCCodeGenInfo implementation for the given target.
MCSubtargetInfo * createARMMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Create a ARM MCSubtargetInfo instance.
static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target...
static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)
static bool getARMLoadDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info)
Triple - Helper class for working with autoconf configuration names.
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X or iOS).
virtual bool isConditionalBranch(const MCInst &Inst) const
static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.
MCStreamer * createELFStreamer(MCContext &Ctx, MCAsmBackend &TAB, raw_pwrite_stream &OS, MCCodeEmitter *CE, bool RelaxAll)
Takes ownership of TAB and CE.
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.
unsigned getOpcode() const
Target - Wrapper for Target specific information.
static bool getMCRDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info)
static MCCodeGenInfo * createARMMCCodeGenInfo(const Triple &TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL)
MCCodeEmitter * createARMLEMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
RegisterMCAsmInfoFn - Helper template for registering a target assembly info implementation.
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
OperandType
Types of operands to CF instructions.
void initMCCodeGenInfo(Reloc::Model RM=Reloc::Default, CodeModel::Model CM=CodeModel::Default, CodeGenOpt::Level OL=CodeGenOpt::Default)
unsigned getNumOperands() const
static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)
RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target. ...
MCSubtargetInfo - Generic base class for all target subtargets.
static MCAsmInfo * createARMMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TheTriple)
static void RegisterELFStreamer(Target &T, Target::ELFStreamerCtorTy Fn)
static MCInstrAnalysis * createARMMCInstrAnalysis(const MCInstrInfo *Info)
An abstract base class for streams implementations that also support a pwrite operation.
MCTargetStreamer * createARMNullTargetStreamer(MCStreamer &S)
cl::opt< bool > RelaxAll("mc-relax-all", cl::desc("When used with filetype=obj, ""relax all fixups in the emitted object file"))
static bool isConditionalBranch(unsigned Opc)
MCStreamer * createMachOStreamer(MCContext &Ctx, MCAsmBackend &TAB, raw_pwrite_stream &OS, MCCodeEmitter *CE, bool RelaxAll, bool DWARFMustBeAtTheEnd, bool LabelSections=false)
MCAsmBackend * createThumbLEAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU)
static void RegisterNullTargetStreamer(Target &T, Target::NullTargetStreamerCtorTy Fn)
MCAsmBackend * createARMBEAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU)
Generic interface to target specific assembler backends.
std::string ParseARMTriple(const Triple &TT, StringRef CPU)
static void RegisterMCRelocationInfo(Target &T, Target::MCRelocationInfoCtorTy Fn)
RegisterMCRelocationInfo - Register an MCRelocationInfo implementation for the given target...
static MCRelocationInfo * createARMMCRelocationInfo(const Triple &TT, MCContext &Ctx)
StringRef - Represent a constant reference to a string, i.e.
static bool getARMStoreDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info)
MCCodeEmitter * createARMBEMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
const MCOperand & getOperand(unsigned i) const
bool empty() const
empty - Check if the string is empty.