22 #define DEBUG_TYPE "systemz-shorten-inst"
30 const char *getPassName()
const override {
31 return "SystemZ Instruction Shortening";
38 bool shortenIIF(
MachineInstr &
MI,
unsigned *GPRMap,
unsigned LiveOther,
39 unsigned LLIxL,
unsigned LLIxH);
49 unsigned LowGPRs[SystemZ::NUM_TARGET_REGS];
50 unsigned HighGPRs[SystemZ::NUM_TARGET_REGS];
57 return new SystemZShortenInst(TM);
63 for (
unsigned I = 0;
I < 16; ++
I) {
69 LowGPRs[GR128] |= 3 <<
I;
70 HighGPRs[GR128] |= 3 <<
I;
80 bool SystemZShortenInst::shortenIIF(
MachineInstr &
MI,
unsigned *GPRMap,
81 unsigned LiveOther,
unsigned LLIxL,
84 assert(Reg < SystemZ::NUM_TARGET_REGS &&
"Invalid register number");
85 unsigned GPRs = GPRMap[
Reg];
86 assert(GPRs != 0 &&
"Register must be a GPR");
106 bool SystemZShortenInst::shortenOn0(
MachineInstr &MI,
unsigned Opcode) {
116 bool SystemZShortenInst::shortenOn01(
MachineInstr &MI,
unsigned Opcode) {
127 bool SystemZShortenInst::shortenOn001(
MachineInstr &MI,
unsigned Opcode) {
141 bool SystemZShortenInst::shortenFPConv(
MachineInstr &MI,
unsigned Opcode) {
165 bool Changed =
false;
168 unsigned LiveLow = 0;
169 unsigned LiveHigh = 0;
171 for (
auto LI = (*SI)->livein_begin(),
LE = (*SI)->livein_end();
174 assert(Reg < SystemZ::NUM_TARGET_REGS &&
"Invalid register number");
175 LiveLow |= LowGPRs[
Reg];
176 LiveHigh |= HighGPRs[
Reg];
181 for (
auto MBBI = MBB.
rbegin(), MBBE = MBB.
rend(); MBBI != MBBE; ++MBBI) {
185 Changed |= shortenIIF(MI, LowGPRs, LiveHigh, SystemZ::LLILL,
190 Changed |= shortenIIF(MI, HighGPRs, LiveLow, SystemZ::LLIHL,
195 Changed |= shortenOn001(MI, SystemZ::ADBR);
199 Changed |= shortenOn001(MI, SystemZ::DDBR);
203 Changed |= shortenFPConv(MI, SystemZ::FIDBRA);
207 Changed |= shortenOn01(MI, SystemZ::LDEBR);
211 Changed |= shortenFPConv(MI, SystemZ::LEDBRA);
215 Changed |= shortenOn001(MI, SystemZ::MDBR);
218 case SystemZ::WFLCDB:
219 Changed |= shortenOn01(MI, SystemZ::LCDBR);
222 case SystemZ::WFLNDB:
223 Changed |= shortenOn01(MI, SystemZ::LNDBR);
226 case SystemZ::WFLPDB:
227 Changed |= shortenOn01(MI, SystemZ::LPDBR);
230 case SystemZ::WFSQDB:
231 Changed |= shortenOn01(MI, SystemZ::SQDBR);
235 Changed |= shortenOn001(MI, SystemZ::SDBR);
239 Changed |= shortenOn01(MI, SystemZ::CDBR);
244 Changed |= shortenOn0(MI, SystemZ::LDE32);
248 Changed |= shortenOn0(MI, SystemZ::STE);
256 Changed |= shortenOn0(MI, SystemZ::STD);
260 unsigned UsedLow = 0;
261 unsigned UsedHigh = 0;
266 if (
unsigned Reg = MO.
getReg()) {
267 assert(Reg < SystemZ::NUM_TARGET_REGS &&
"Invalid register number");
269 LiveLow &= ~LowGPRs[
Reg];
270 LiveHigh &= ~HighGPRs[
Reg];
272 UsedLow |= LowGPRs[
Reg];
273 UsedHigh |= HighGPRs[
Reg];
279 LiveHigh |= UsedHigh;
288 bool Changed =
false;
290 Changed |= processBlock(MBB);
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
mop_iterator operands_end()
const unsigned GR32Regs[16]
unsigned getFirstReg(unsigned Reg)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Reg
All possible values of the reg field in the ModR/M byte.
const unsigned GRH32Regs[16]
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
FunctionPass * createSystemZShortenInstPass(SystemZTargetMachine &TM)
reverse_iterator rbegin()
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineBasicBlock * getParent() const
const MachineOperand & getOperand(unsigned i) const
void setImm(int64_t immVal)
FunctionPass class - This class is used to implement most global optimizations.
succ_iterator succ_begin()
static bool isImmLH(uint64_t Val)
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
MachineOperand class - Representation of each machine instruction operand.
const unsigned GR128Regs[16]
unsigned getRegAsGR64(unsigned Reg)
const unsigned GR64Regs[16]
Representation of each machine instruction.
void setReg(unsigned Reg)
Change the register this operand corresponds to.
unsigned getReg() const
getReg - Returns the register number.
virtual const TargetInstrInfo * getInstrInfo() const
mop_iterator operands_begin()
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
static bool isImmLL(uint64_t Val)