LLVM  3.7.0
Public Types | Public Member Functions | List of all members
llvm::R600InstrInfo Class Reference

#include <R600InstrInfo.h>

Inheritance diagram for llvm::R600InstrInfo:
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Collaboration diagram for llvm::R600InstrInfo:
[legend]

Public Types

enum  BankSwizzle {
  ALU_VEC_012_SCL_210 = 0, ALU_VEC_021_SCL_122, ALU_VEC_120_SCL_212, ALU_VEC_102_SCL_221,
  ALU_VEC_201, ALU_VEC_210
}
 

Public Member Functions

 R600InstrInfo (const AMDGPUSubtarget &st)
 
const R600RegisterInfogetRegisterInfo () const override
 
void copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
 
bool isLegalToSplitMBBAt (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const override
 
bool isTrig (const MachineInstr &MI) const
 
bool isPlaceHolderOpcode (unsigned opcode) const
 
bool isReductionOp (unsigned opcode) const
 
bool isCubeOp (unsigned opcode) const
 
bool isALUInstr (unsigned Opcode) const
 
bool hasInstrModifiers (unsigned Opcode) const
 
bool isLDSInstr (unsigned Opcode) const
 
bool isLDSNoRetInstr (unsigned Opcode) const
 
bool isLDSRetInstr (unsigned Opcode) const
 
bool canBeConsideredALU (const MachineInstr *MI) const
 
bool isTransOnly (unsigned Opcode) const
 
bool isTransOnly (const MachineInstr *MI) const
 
bool isVectorOnly (unsigned Opcode) const
 
bool isVectorOnly (const MachineInstr *MI) const
 
bool isExport (unsigned Opcode) const
 
bool usesVertexCache (unsigned Opcode) const
 
bool usesVertexCache (const MachineInstr *MI) const
 
bool usesTextureCache (unsigned Opcode) const
 
bool usesTextureCache (const MachineInstr *MI) const
 
bool mustBeLastInClause (unsigned Opcode) const
 
bool usesAddressRegister (MachineInstr *MI) const
 
bool definesAddressRegister (MachineInstr *MI) const
 
bool readsLDSSrcReg (const MachineInstr *MI) const
 
int getSrcIdx (unsigned Opcode, unsigned SrcNum) const
 
int getSelIdx (unsigned Opcode, unsigned SrcIdx) const
 
SmallVector< std::pair
< MachineOperand *, int64_t >, 3 > 
getSrcs (MachineInstr *MI) const
 
unsigned isLegalUpTo (const std::vector< std::vector< std::pair< int, unsigned > > > &IGSrcs, const std::vector< R600InstrInfo::BankSwizzle > &Swz, const std::vector< std::pair< int, unsigned > > &TransSrcs, R600InstrInfo::BankSwizzle TransSwz) const
 returns how many MIs (whose inputs are represented by IGSrcs) can be packed in the same Instruction Group while meeting read port limitations given a Swz swizzle sequence. More...
 
bool FindSwizzleForVectorSlot (const std::vector< std::vector< std::pair< int, unsigned > > > &IGSrcs, std::vector< R600InstrInfo::BankSwizzle > &SwzCandidate, const std::vector< std::pair< int, unsigned > > &TransSrcs, R600InstrInfo::BankSwizzle TransSwz) const
 Enumerate all possible Swizzle sequence to find one that can meet all read port requirements. More...
 
bool fitsReadPortLimitations (const std::vector< MachineInstr * > &MIs, const DenseMap< unsigned, unsigned > &PV, std::vector< BankSwizzle > &BS, bool isLastAluTrans) const
 Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210 returns true and the first (in lexical order) BankSwizzle affectation starting from the one already provided in the Instruction Group MIs that fits Read Port limitations in BS if available. More...
 
bool fitsConstReadLimitations (const std::vector< MachineInstr * > &) const
 An instruction group can only access 2 channel pair (either [XY] or [ZW]) from KCache bank on R700+. More...
 
bool fitsConstReadLimitations (const std::vector< unsigned > &) const
 Same but using const index set instead of MI set. More...
 
bool isVector (const MachineInstr &MI) const
 Vector instructions are instructions that must fill all instruction slots within an instruction group. More...
 
bool isMov (unsigned Opcode) const override
 
DFAPacketizerCreateTargetScheduleState (const TargetSubtargetInfo &) const override
 
bool ReverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
 
bool AnalyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
 
unsigned InsertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, DebugLoc DL) const override
 
unsigned RemoveBranch (MachineBasicBlock &MBB) const override
 
bool isPredicated (const MachineInstr *MI) const override
 
bool isPredicable (MachineInstr *MI) const override
 
bool isProfitableToDupForIfCvt (MachineBasicBlock &MBB, unsigned NumCyles, const BranchProbability &Probability) const override
 
bool isProfitableToIfCvt (MachineBasicBlock &MBB, unsigned NumCyles, unsigned ExtraPredCycles, const BranchProbability &Probability) const override
 
bool isProfitableToIfCvt (MachineBasicBlock &TMBB, unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB, unsigned NumFCycles, unsigned ExtraFCycles, const BranchProbability &Probability) const override
 
bool DefinesPredicate (MachineInstr *MI, std::vector< MachineOperand > &Pred) const override
 
bool SubsumesPredicate (ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
 
bool isProfitableToUnpredicate (MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
 
bool PredicateInstruction (MachineInstr *MI, ArrayRef< MachineOperand > Pred) const override
 
unsigned int getPredicationCost (const MachineInstr *) const override
 
unsigned int getInstrLatency (const InstrItineraryData *ItinData, const MachineInstr *MI, unsigned *PredCost=nullptr) const override
 
int getInstrLatency (const InstrItineraryData *ItinData, SDNode *Node) const override
 
bool expandPostRAPseudo (MachineBasicBlock::iterator MI) const override
 
void reserveIndirectRegisters (BitVector &Reserved, const MachineFunction &MF) const
 Reserve the registers that may be accesed using indirect addressing. More...
 
unsigned calculateIndirectAddress (unsigned RegIndex, unsigned Channel) const override
 Calculate the "Indirect Address" for the given RegIndex and Channel. More...
 
const TargetRegisterClassgetIndirectAddrRegClass () const override
 
MachineInstrBuilder buildIndirectWrite (MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned ValueReg, unsigned Address, unsigned OffsetReg) const override
 Build instruction(s) for an indirect register write. More...
 
MachineInstrBuilder buildIndirectRead (MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned ValueReg, unsigned Address, unsigned OffsetReg) const override
 Build instruction(s) for an indirect register read. More...
 
unsigned getMaxAlusPerClause () const
 
MachineInstrBuilder buildDefaultInstruction (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned Opcode, unsigned DstReg, unsigned Src0Reg, unsigned Src1Reg=0) const
 buildDefaultInstruction - This function returns a MachineInstr with all the instruction modifiers initialized to their default values. More...
 
MachineInstrbuildSlotOfVectorInstruction (MachineBasicBlock &MBB, MachineInstr *MI, unsigned Slot, unsigned DstReg) const
 
MachineInstrbuildMovImm (MachineBasicBlock &BB, MachineBasicBlock::iterator I, unsigned DstReg, uint64_t Imm) const
 
MachineInstrbuildMovInstr (MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned DstReg, unsigned SrcReg) const override
 Build a MOV instruction. More...
 
int getOperandIdx (const MachineInstr &MI, unsigned Op) const
 Get the index of Op in the MachineInstr. More...
 
int getOperandIdx (unsigned Opcode, unsigned Op) const
 Get the index of Op for the given Opcode. More...
 
void setImmOperand (MachineInstr *MI, unsigned Op, int64_t Imm) const
 Helper function for setting instruction flag values. More...
 
bool hasFlagOperand (const MachineInstr &MI) const
 
void addFlag (MachineInstr *MI, unsigned Operand, unsigned Flag) const
 Add one of the MO_FLAG* flags to the specified Operand. More...
 
bool isFlagSet (const MachineInstr &MI, unsigned Operand, unsigned Flag) const
 Determine if the specified Flag is set on this Operand. More...
 
MachineOperandgetFlagOp (MachineInstr *MI, unsigned SrcIdx=0, unsigned Flag=0) const
 
void clearFlag (MachineInstr *MI, unsigned Operand, unsigned Flag) const
 Clear the specified flag on the instruction. More...
 
- Public Member Functions inherited from llvm::AMDGPUInstrInfo
 AMDGPUInstrInfo (const AMDGPUSubtarget &st)
 
bool isCoalescableExtInstr (const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override
 
unsigned isLoadFromStackSlot (const MachineInstr *MI, int &FrameIndex) const override
 
unsigned isLoadFromStackSlotPostFE (const MachineInstr *MI, int &FrameIndex) const override
 
bool hasLoadFromStackSlot (const MachineInstr *MI, const MachineMemOperand *&MMO, int &FrameIndex) const override
 
unsigned isStoreFromStackSlot (const MachineInstr *MI, int &FrameIndex) const
 
unsigned isStoreFromStackSlotPostFE (const MachineInstr *MI, int &FrameIndex) const
 
bool hasStoreFromStackSlot (const MachineInstr *MI, const MachineMemOperand *&MMO, int &FrameIndex) const
 
MachineInstrconvertToThreeAddress (MachineFunction::iterator &MFI, MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const override
 
bool expandPostRAPseudo (MachineBasicBlock::iterator MI) const override
 
void storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
 
void loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
 
int getIndirectIndexBegin (const MachineFunction &MF) const
 
int getIndirectIndexEnd (const MachineFunction &MF) const
 
bool canFoldMemoryOperand (const MachineInstr *MI, ArrayRef< unsigned > Ops) const override
 
bool unfoldMemoryOperand (MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const override
 
bool unfoldMemoryOperand (SelectionDAG &DAG, SDNode *N, SmallVectorImpl< SDNode * > &NewNodes) const override
 
unsigned getOpcodeAfterMemoryUnfold (unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const override
 
bool enableClusterLoads () const override
 
bool shouldScheduleLoadsNear (SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override
 
bool ReverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
 
void insertNoop (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
 
bool isPredicated (const MachineInstr *MI) const override
 
bool SubsumesPredicate (ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
 
bool DefinesPredicate (MachineInstr *MI, std::vector< MachineOperand > &Pred) const override
 
bool isPredicable (MachineInstr *MI) const override
 
bool isSafeToMoveRegClassDefs (const TargetRegisterClass *RC) const override
 
bool isRegisterStore (const MachineInstr &MI) const
 
bool isRegisterLoad (const MachineInstr &MI) const
 
int pseudoToMCOpcode (int Opcode) const
 Return a target-specific opcode if Opcode is a pseudo instruction. More...
 
const MCInstrDescgetMCOpcodeFromPseudo (unsigned Opcode) const
 Return the descriptor of the target-specific machine instruction that corresponds to the specified pseudo or native opcode. More...
 
int getMaskedMIMGOp (uint16_t Opcode, unsigned Channels) const
 Given a MIMG Opcode that writes all 4 channels, return the equivalent opcode that writes Channels Channels. More...
 

Additional Inherited Members

- Protected Member Functions inherited from llvm::AMDGPUInstrInfo
MachineInstrfoldMemoryOperandImpl (MachineFunction &MF, MachineInstr *MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex) const override
 
MachineInstrfoldMemoryOperandImpl (MachineFunction &MF, MachineInstr *MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr *LoadMI) const override
 
- Protected Attributes inherited from llvm::AMDGPUInstrInfo
const AMDGPUSubtargetST
 

Detailed Description

Definition at line 32 of file R600InstrInfo.h.

Member Enumeration Documentation

Enumerator
ALU_VEC_012_SCL_210 
ALU_VEC_021_SCL_122 
ALU_VEC_120_SCL_212 
ALU_VEC_102_SCL_221 
ALU_VEC_201 
ALU_VEC_210 

Definition at line 52 of file R600InstrInfo.h.

Constructor & Destructor Documentation

R600InstrInfo::R600InstrInfo ( const AMDGPUSubtarget st)
explicit

Definition at line 31 of file R600InstrInfo.cpp.

Member Function Documentation

void R600InstrInfo::addFlag ( MachineInstr MI,
unsigned  Operand,
unsigned  Flag 
) const
bool R600InstrInfo::AnalyzeBranch ( MachineBasicBlock MBB,
MachineBasicBlock *&  TBB,
MachineBasicBlock *&  FBB,
SmallVectorImpl< MachineOperand > &  Cond,
bool  AllowModify 
) const
override
MachineInstrBuilder R600InstrInfo::buildDefaultInstruction ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
unsigned  Opcode,
unsigned  DstReg,
unsigned  Src0Reg,
unsigned  Src1Reg = 0 
) const

buildDefaultInstruction - This function returns a MachineInstr with all the instruction modifiers initialized to their default values.

You can use this function to avoid manually specifying each instruction modifier operand when building a new instruction.

Returns
a MachineInstr with all the instruction modifiers initialized to their default values.

Definition at line 1175 of file R600InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), and llvm::MachineBasicBlock::findDebugLoc().

Referenced by buildMovImm(), buildMovInstr(), buildSlotOfVectorInstruction(), copyPhysReg(), and llvm::R600TargetLowering::EmitInstrWithCustomInserter().

MachineInstrBuilder R600InstrInfo::buildIndirectRead ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
unsigned  ValueReg,
unsigned  Address,
unsigned  OffsetReg 
) const
overridevirtual

Build instruction(s) for an indirect register read.

Returns
The instruction that performs the indirect register read

Implements llvm::AMDGPUInstrInfo.

Definition at line 1137 of file R600InstrInfo.cpp.

MachineInstrBuilder R600InstrInfo::buildIndirectWrite ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
unsigned  ValueReg,
unsigned  Address,
unsigned  OffsetReg 
) const
overridevirtual

Build instruction(s) for an indirect register write.

Returns
The instruction that performs the indirect register write

Implements llvm::AMDGPUInstrInfo.

Definition at line 1105 of file R600InstrInfo.cpp.

MachineInstr * R600InstrInfo::buildMovImm ( MachineBasicBlock BB,
MachineBasicBlock::iterator  I,
unsigned  DstReg,
uint64_t  Imm 
) const
MachineInstr * R600InstrInfo::buildMovInstr ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
unsigned  DstReg,
unsigned  SrcReg 
) const
overridevirtual

Build a MOV instruction.

Implements llvm::AMDGPUInstrInfo.

Definition at line 1312 of file R600InstrInfo.cpp.

References buildDefaultInstruction().

MachineInstr * R600InstrInfo::buildSlotOfVectorInstruction ( MachineBasicBlock MBB,
MachineInstr MI,
unsigned  Slot,
unsigned  DstReg 
) const
unsigned R600InstrInfo::calculateIndirectAddress ( unsigned  RegIndex,
unsigned  Channel 
) const
overridevirtual

Calculate the "Indirect Address" for the given RegIndex and Channel.

We model indirect addressing using a virtual address space that can be accesed with loads and stores. The "Indirect Address" is the memory address in this virtual address space that maps to the given RegIndex and Channel.

Implements llvm::AMDGPUInstrInfo.

Definition at line 1094 of file R600InstrInfo.cpp.

bool R600InstrInfo::canBeConsideredALU ( const MachineInstr MI) const
Returns
true if this Opcode represents an ALU instruction or an instruction that will be lowered in ExpandSpecialInstrs Pass.

Definition at line 161 of file R600InstrInfo.cpp.

References llvm::TargetOpcode::COPY, llvm::MachineInstr::getOpcode(), isALUInstr(), isCubeOp(), and isVector().

void R600InstrInfo::clearFlag ( MachineInstr MI,
unsigned  Operand,
unsigned  Flag 
) const

Clear the specified flag on the instruction.

Definition at line 1418 of file R600InstrInfo.cpp.

References getFlagOp(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), HAS_NATIVE_OPERANDS, NUM_MO_FLAGS, and llvm::MachineOperand::setImm().

Referenced by addFlag(), and RemoveBranch().

void R600InstrInfo::copyPhysReg ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
DebugLoc  DL,
unsigned  DestReg,
unsigned  SrcReg,
bool  KillSrc 
) const
override
DFAPacketizer * R600InstrInfo::CreateTargetScheduleState ( const TargetSubtargetInfo STI) const
override
bool R600InstrInfo::definesAddressRegister ( MachineInstr MI) const
bool R600InstrInfo::DefinesPredicate ( MachineInstr MI,
std::vector< MachineOperand > &  Pred 
) const
override

Definition at line 990 of file R600InstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), and isPredicateSetter().

bool R600InstrInfo::expandPostRAPseudo ( MachineBasicBlock::iterator  MI) const
override
bool R600InstrInfo::FindSwizzleForVectorSlot ( const std::vector< std::vector< std::pair< int, unsigned > > > &  IGSrcs,
std::vector< R600InstrInfo::BankSwizzle > &  SwzCandidate,
const std::vector< std::pair< int, unsigned > > &  TransSrcs,
R600InstrInfo::BankSwizzle  TransSwz 
) const

Enumerate all possible Swizzle sequence to find one that can meet all read port requirements.

Definition at line 511 of file R600InstrInfo.cpp.

References isLegalUpTo(), and NextPossibleSolution().

Referenced by fitsReadPortLimitations().

bool R600InstrInfo::fitsConstReadLimitations ( const std::vector< MachineInstr * > &  MIs) const

An instruction group can only access 2 channel pair (either [XY] or [ZW]) from KCache bank on R700+.

This function check if MI set in input meet this limitations

Definition at line 622 of file R600InstrInfo.cpp.

References contains(), llvm::R600RegisterInfo::getHWRegChan(), llvm::MachineInstr::getOpcode(), getSrcs(), llvm::SmallSet< T, N, C >::insert(), isALUInstr(), llvm::SmallSet< T, N, C >::size(), and llvm::ArrayRef< T >::size().

Referenced by FoldOperand().

bool R600InstrInfo::fitsConstReadLimitations ( const std::vector< unsigned > &  Consts) const

Same but using const index set instead of MI set.

Definition at line 597 of file R600InstrInfo.cpp.

bool R600InstrInfo::fitsReadPortLimitations ( const std::vector< MachineInstr * > &  MIs,
const DenseMap< unsigned, unsigned > &  PV,
std::vector< BankSwizzle > &  BS,
bool  isLastAluTrans 
) const

Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210 returns true and the first (in lexical order) BankSwizzle affectation starting from the one already provided in the Instruction Group MIs that fits Read Port limitations in BS if available.

Otherwise returns false and undefined content in BS. isLastAluTrans should be set if the last Alu of MIs will be executed on Trans ALU. In this case, ValidTSwizzle returns the BankSwizzle value to apply to the last instruction. PV holds GPR to PV registers in the Instruction Group MIs.

Definition at line 548 of file R600InstrInfo.cpp.

References ALU_VEC_012_SCL_210, ALU_VEC_021_SCL_122, ALU_VEC_102_SCL_221, ALU_VEC_120_SCL_212, FindSwizzleForVectorSlot(), getOperandIdx(), and isConstCompatible().

MachineOperand & R600InstrInfo::getFlagOp ( MachineInstr MI,
unsigned  SrcIdx = 0,
unsigned  Flag = 0 
) const
Parameters
SrcIdxThe register source to set the flag on (e.g src0, src1, src2)
FlagThe flag being set.
Returns
the operand containing the flags for this instruction.

Definition at line 1342 of file R600InstrInfo.cpp.

References GET_FLAG_OPERAND_IDX, llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getOperandIdx(), HAS_NATIVE_OPERANDS, llvm::MachineOperand::isImm(), MO_FLAG_ABS, MO_FLAG_CLAMP, MO_FLAG_LAST, MO_FLAG_MASK, MO_FLAG_NEG, MO_FLAG_NOT_LAST, R600_InstFlag::OP3, and llvm::support::endian::write().

Referenced by addFlag(), and clearFlag().

const TargetRegisterClass * R600InstrInfo::getIndirectAddrRegClass ( ) const
overridevirtual
Returns
The register class to be used for loading and storing values from an "Indirect Address" .

Implements llvm::AMDGPUInstrInfo.

Definition at line 1101 of file R600InstrInfo.cpp.

unsigned int R600InstrInfo::getInstrLatency ( const InstrItineraryData ItinData,
const MachineInstr MI,
unsigned PredCost = nullptr 
) const
override

Definition at line 1042 of file R600InstrInfo.cpp.

int llvm::R600InstrInfo::getInstrLatency ( const InstrItineraryData ItinData,
SDNode Node 
) const
inlineoverride

Definition at line 208 of file R600InstrInfo.h.

unsigned R600InstrInfo::getMaxAlusPerClause ( ) const

Definition at line 1171 of file R600InstrInfo.cpp.

int R600InstrInfo::getOperandIdx ( const MachineInstr MI,
unsigned  Op 
) const
int R600InstrInfo::getOperandIdx ( unsigned  Opcode,
unsigned  Op 
) const

Get the index of Op for the given Opcode.

Returns
-1 if the Instruction does not contain the specified Op.

Definition at line 1322 of file R600InstrInfo.cpp.

References llvm::AMDGPU::getNamedOperandIdx().

unsigned int R600InstrInfo::getPredicationCost ( const MachineInstr ) const
override

Definition at line 1038 of file R600InstrInfo.cpp.

const R600RegisterInfo & R600InstrInfo::getRegisterInfo ( ) const
overridevirtual

Implements llvm::AMDGPUInstrInfo.

Definition at line 34 of file R600InstrInfo.cpp.

Referenced by llvm::R600TargetLowering::LowerOperation().

int R600InstrInfo::getSelIdx ( unsigned  Opcode,
unsigned  SrcIdx 
) const
Returns
The operand Index for the Sel operand given an index to one of the instruction's src operands.

Definition at line 269 of file R600InstrInfo.cpp.

References getOperandIdx().

Referenced by FoldOperand().

int R600InstrInfo::getSrcIdx ( unsigned  Opcode,
unsigned  SrcNum 
) const
Returns
The operand index for the given source number. Legal values for SrcNum are 0, 1, and 2.

Definition at line 258 of file R600InstrInfo.cpp.

References getOperandIdx().

SmallVector< std::pair< MachineOperand *, int64_t >, 3 > R600InstrInfo::getSrcs ( MachineInstr MI) const
Returns
a pair for each src of an ALU instructions. The first member of a pair is the register id. If register is ALU_CONST, second member is SEL. If register is ALU_LITERAL, second member is IMM. Otherwise, second member value is undefined.

Definition at line 293 of file R600InstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getOperandIdx(), llvm::MachineOperand::getReg(), and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().

Referenced by fitsConstReadLimitations().

bool R600InstrInfo::hasFlagOperand ( const MachineInstr MI) const
Returns
true if this instruction has an operand for storing target flags.

Definition at line 1338 of file R600InstrInfo.cpp.

References GET_FLAG_OPERAND_IDX, and llvm::MachineInstr::getOpcode().

bool R600InstrInfo::hasInstrModifiers ( unsigned  Opcode) const

Definition at line 137 of file R600InstrInfo.cpp.

References R600_InstFlag::OP1, R600_InstFlag::OP2, and R600_InstFlag::OP3.

unsigned R600InstrInfo::InsertBranch ( MachineBasicBlock MBB,
MachineBasicBlock TBB,
MachineBasicBlock FBB,
ArrayRef< MachineOperand Cond,
DebugLoc  DL 
) const
override
bool R600InstrInfo::isALUInstr ( unsigned  Opcode) const
Returns
true if this Opcode represents an ALU instruction.

Definition at line 131 of file R600InstrInfo.cpp.

References R600_InstFlag::ALU_INST.

Referenced by canBeConsideredALU(), fitsConstReadLimitations(), and readsLDSSrcReg().

bool R600InstrInfo::isCubeOp ( unsigned  opcode) const

Definition at line 120 of file R600InstrInfo.cpp.

Referenced by canBeConsideredALU().

bool R600InstrInfo::isExport ( unsigned  Opcode) const

Definition at line 197 of file R600InstrInfo.cpp.

References R600_InstFlag::IS_EXPORT.

bool llvm::R600InstrInfo::isFlagSet ( const MachineInstr MI,
unsigned  Operand,
unsigned  Flag 
) const

Determine if the specified Flag is set on this Operand.

bool R600InstrInfo::isLDSInstr ( unsigned  Opcode) const
bool R600InstrInfo::isLDSNoRetInstr ( unsigned  Opcode) const

Definition at line 153 of file R600InstrInfo.cpp.

References getOperandIdx(), and isLDSInstr().

bool R600InstrInfo::isLDSRetInstr ( unsigned  Opcode) const
bool R600InstrInfo::isLegalToSplitMBBAt ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MBBI 
) const
override
Returns
true if MBBI can be moved into a new basic.

Definition at line 82 of file R600InstrInfo.cpp.

References I, llvm::R600RegisterInfo::isPhysRegLiveAcrossClauses(), and llvm::TargetRegisterInfo::isVirtualRegister().

unsigned R600InstrInfo::isLegalUpTo ( const std::vector< std::vector< std::pair< int, unsigned > > > &  IGSrcs,
const std::vector< R600InstrInfo::BankSwizzle > &  Swz,
const std::vector< std::pair< int, unsigned > > &  TransSrcs,
R600InstrInfo::BankSwizzle  TransSwz 
) const

returns how many MIs (whose inputs are represented by IGSrcs) can be packed in the same Instruction Group while meeting read port limitations given a Swz swizzle sequence.

Definition at line 442 of file R600InstrInfo.cpp.

References ALU_VEC_012_SCL_210, ALU_VEC_021_SCL_122, GET_REG_INDEX, getTransSwizzle(), and Swizzle().

Referenced by FindSwizzleForVectorSlot().

bool R600InstrInfo::isMov ( unsigned  Opcode) const
overridevirtual

Implements llvm::AMDGPUInstrInfo.

Definition at line 93 of file R600InstrInfo.cpp.

bool R600InstrInfo::isPlaceHolderOpcode ( unsigned  opcode) const

Definition at line 108 of file R600InstrInfo.cpp.

References llvm::NVPTXISD::RETURN.

bool R600InstrInfo::isPredicable ( MachineInstr MI) const
override
bool R600InstrInfo::isPredicated ( const MachineInstr MI) const
override
bool R600InstrInfo::isProfitableToDupForIfCvt ( MachineBasicBlock MBB,
unsigned  NumCyles,
const BranchProbability Probability 
) const
override

Definition at line 941 of file R600InstrInfo.cpp.

bool R600InstrInfo::isProfitableToIfCvt ( MachineBasicBlock MBB,
unsigned  NumCyles,
unsigned  ExtraPredCycles,
const BranchProbability Probability 
) const
override

Definition at line 922 of file R600InstrInfo.cpp.

bool R600InstrInfo::isProfitableToIfCvt ( MachineBasicBlock TMBB,
unsigned  NumTCycles,
unsigned  ExtraTCycles,
MachineBasicBlock FMBB,
unsigned  NumFCycles,
unsigned  ExtraFCycles,
const BranchProbability Probability 
) const
override

Definition at line 930 of file R600InstrInfo.cpp.

bool R600InstrInfo::isProfitableToUnpredicate ( MachineBasicBlock TMBB,
MachineBasicBlock FMBB 
) const
override

Definition at line 949 of file R600InstrInfo.cpp.

bool R600InstrInfo::isReductionOp ( unsigned  opcode) const

Definition at line 116 of file R600InstrInfo.cpp.

bool R600InstrInfo::isTransOnly ( unsigned  Opcode) const

Definition at line 179 of file R600InstrInfo.cpp.

References llvm::AMDGPUSubtarget::hasCaymanISA(), and llvm::AMDGPUInstrInfo::ST.

Referenced by isTransOnly().

bool R600InstrInfo::isTransOnly ( const MachineInstr MI) const

Definition at line 185 of file R600InstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), and isTransOnly().

bool R600InstrInfo::isTrig ( const MachineInstr MI) const

Definition at line 38 of file R600InstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), and R600_InstFlag::TRIG.

bool R600InstrInfo::isVector ( const MachineInstr MI) const

Vector instructions are instructions that must fill all instruction slots within an instruction group.

Definition at line 42 of file R600InstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), and R600_InstFlag::VECTOR.

Referenced by canBeConsideredALU(), and isPredicable().

bool R600InstrInfo::isVectorOnly ( unsigned  Opcode) const

Definition at line 189 of file R600InstrInfo.cpp.

Referenced by isVectorOnly().

bool R600InstrInfo::isVectorOnly ( const MachineInstr MI) const

Definition at line 193 of file R600InstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), and isVectorOnly().

bool R600InstrInfo::mustBeLastInClause ( unsigned  Opcode) const

Definition at line 224 of file R600InstrInfo.cpp.

bool R600InstrInfo::PredicateInstruction ( MachineInstr MI,
ArrayRef< MachineOperand Pred 
) const
override
bool R600InstrInfo::readsLDSSrcReg ( const MachineInstr MI) const
unsigned R600InstrInfo::RemoveBranch ( MachineBasicBlock MBB) const
override
void R600InstrInfo::reserveIndirectRegisters ( BitVector Reserved,
const MachineFunction MF 
) const
bool R600InstrInfo::ReverseBranchCondition ( SmallVectorImpl< MachineOperand > &  Cond) const
override
void R600InstrInfo::setImmOperand ( MachineInstr MI,
unsigned  Op,
int64_t  Imm 
) const
bool R600InstrInfo::SubsumesPredicate ( ArrayRef< MachineOperand Pred1,
ArrayRef< MachineOperand Pred2 
) const
override

Definition at line 997 of file R600InstrInfo.cpp.

bool R600InstrInfo::usesAddressRegister ( MachineInstr MI) const
bool R600InstrInfo::usesTextureCache ( unsigned  Opcode) const
bool R600InstrInfo::usesTextureCache ( const MachineInstr MI) const
bool R600InstrInfo::usesVertexCache ( unsigned  Opcode) const
bool R600InstrInfo::usesVertexCache ( const MachineInstr MI) const

The documentation for this class was generated from the following files: