LLVM  3.7.0
Public Member Functions | List of all members
llvm::AArch64InstrInfo Class Reference

#include <AArch64InstrInfo.h>

Inheritance diagram for llvm::AArch64InstrInfo:
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Collaboration diagram for llvm::AArch64InstrInfo:
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Public Member Functions

 AArch64InstrInfo (const AArch64Subtarget &STI)
 
const AArch64RegisterInfogetRegisterInfo () const
 getRegisterInfo - TargetInstrInfo is a superset of MRegister info. More...
 
unsigned GetInstSizeInBytes (const MachineInstr *MI) const
 GetInstSize - Return the number of bytes of code the specified instruction may be. More...
 
bool isAsCheapAsAMove (const MachineInstr *MI) const override
 
bool isCoalescableExtInstr (const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override
 
bool areMemAccessesTriviallyDisjoint (MachineInstr *MIa, MachineInstr *MIb, AliasAnalysis *AA=nullptr) const override
 
unsigned isLoadFromStackSlot (const MachineInstr *MI, int &FrameIndex) const override
 
unsigned isStoreToStackSlot (const MachineInstr *MI, int &FrameIndex) const override
 
bool hasShiftedReg (const MachineInstr *MI) const
 Returns true if there is a shiftable register and that the shift value is non-zero. More...
 
bool hasExtendedReg (const MachineInstr *MI) const
 Returns true if there is an extendable register and that the extending value is non-zero. More...
 
bool isGPRZero (const MachineInstr *MI) const
 Does this instruction set its full destination register to zero? More...
 
bool isGPRCopy (const MachineInstr *MI) const
 Does this instruction rename a GPR without modifying bits? More...
 
bool isFPRCopy (const MachineInstr *MI) const
 Does this instruction rename an FPR without modifying bits? More...
 
bool isScaledAddr (const MachineInstr *MI) const
 Return true if this is load/store scales or extends its register offset. More...
 
bool isLdStPairSuppressed (const MachineInstr *MI) const
 Return true if pairing the given load or store is hinted to be unprofitable. More...
 
void suppressLdStPair (MachineInstr *MI) const
 Hint that pairing the given load or store is unprofitable. More...
 
bool getMemOpBaseRegImmOfs (MachineInstr *LdSt, unsigned &BaseReg, unsigned &Offset, const TargetRegisterInfo *TRI) const override
 
bool getMemOpBaseRegImmOfsWidth (MachineInstr *LdSt, unsigned &BaseReg, int &Offset, int &Width, const TargetRegisterInfo *TRI) const
 
bool enableClusterLoads () const override
 
bool shouldClusterLoads (MachineInstr *FirstLdSt, MachineInstr *SecondLdSt, unsigned NumLoads) const override
 Detect opportunities for ldp/stp formation. More...
 
bool shouldScheduleAdjacent (MachineInstr *First, MachineInstr *Second) const override
 
MachineInstremitFrameIndexDebugValue (MachineFunction &MF, int FrameIx, uint64_t Offset, const MDNode *Var, const MDNode *Expr, DebugLoc DL) const
 
void copyPhysRegTuple (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc, unsigned Opcode, llvm::ArrayRef< unsigned > Indices) const
 
void copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
 
void storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
 
void loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
 
MachineInstrfoldMemoryOperandImpl (MachineFunction &MF, MachineInstr *MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex) const override
 
bool AnalyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
 
unsigned RemoveBranch (MachineBasicBlock &MBB) const override
 
unsigned InsertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, DebugLoc DL) const override
 
bool ReverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
 
bool canInsertSelect (const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override
 
void insertSelect (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
 
void getNoopForMachoTarget (MCInst &NopInst) const override
 
bool analyzeCompare (const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const override
 analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2, and the value it compares against in CmpValue. More...
 
bool optimizeCompareInstr (MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const override
 optimizeCompareInstr - Convert the instruction supplying the argument to the comparison into one that sets the zero bit in the flags register. More...
 
bool optimizeCondBranch (MachineInstr *MI) const override
 Replace csincr-branch sequence by simple conditional branch. More...
 
bool getMachineCombinerPatterns (MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern::MC_PATTERN > &Patterns) const override
 Return true when there is potentially a faster code sequence for an instruction chain ending in <Root>. More...
 
void genAlternativeCodeSequence (MachineInstr &Root, MachineCombinerPattern::MC_PATTERN Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
 When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could replace the original code sequence. More...
 
bool useMachineCombiner () const override
 useMachineCombiner - AArch64 supports MachineCombiner More...
 
bool expandPostRAPseudo (MachineBasicBlock::iterator MI) const override
 

Detailed Description

Definition at line 30 of file AArch64InstrInfo.h.

Constructor & Destructor Documentation

AArch64InstrInfo::AArch64InstrInfo ( const AArch64Subtarget STI)
explicit

Definition at line 32 of file AArch64InstrInfo.cpp.

Member Function Documentation

bool AArch64InstrInfo::AnalyzeBranch ( MachineBasicBlock MBB,
MachineBasicBlock *&  TBB,
MachineBasicBlock *&  FBB,
SmallVectorImpl< MachineOperand > &  Cond,
bool  AllowModify = false 
) const
override
bool AArch64InstrInfo::analyzeCompare ( const MachineInstr MI,
unsigned SrcReg,
unsigned SrcReg2,
int CmpMask,
int CmpValue 
) const
override

analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2, and the value it compares against in CmpValue.

Return true if the comparison instruction can be analyzed.

Definition at line 638 of file AArch64InstrInfo.cpp.

References llvm::AArch64_AM::decodeLogicalImmediate(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::getReg().

bool AArch64InstrInfo::areMemAccessesTriviallyDisjoint ( MachineInstr MIa,
MachineInstr MIb,
AliasAnalysis AA = nullptr 
) const
override
bool AArch64InstrInfo::canInsertSelect ( const MachineBasicBlock MBB,
ArrayRef< MachineOperand Cond,
unsigned  TrueReg,
unsigned  FalseReg,
int CondCycles,
int TrueCycles,
int FalseCycles 
) const
override
void AArch64InstrInfo::copyPhysReg ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
DebugLoc  DL,
unsigned  DestReg,
unsigned  SrcReg,
bool  KillSrc 
) const
override
void AArch64InstrInfo::copyPhysRegTuple ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
DebugLoc  DL,
unsigned  DestReg,
unsigned  SrcReg,
bool  KillSrc,
unsigned  Opcode,
llvm::ArrayRef< unsigned Indices 
) const
MachineInstr * AArch64InstrInfo::emitFrameIndexDebugValue ( MachineFunction MF,
int  FrameIx,
uint64_t  Offset,
const MDNode Var,
const MDNode Expr,
DebugLoc  DL 
) const
bool llvm::AArch64InstrInfo::enableClusterLoads ( ) const
inlineoverride

Definition at line 101 of file AArch64InstrInfo.h.

bool AArch64InstrInfo::expandPostRAPseudo ( MachineBasicBlock::iterator  MI) const
override
MachineInstr * AArch64InstrInfo::foldMemoryOperandImpl ( MachineFunction MF,
MachineInstr MI,
ArrayRef< unsigned Ops,
MachineBasicBlock::iterator  InsertPt,
int  FrameIndex 
) const
override
void AArch64InstrInfo::genAlternativeCodeSequence ( MachineInstr Root,
MachineCombinerPattern::MC_PATTERN  Pattern,
SmallVectorImpl< MachineInstr * > &  InsInstrs,
SmallVectorImpl< MachineInstr * > &  DelInstrs,
DenseMap< unsigned, unsigned > &  InstrIdxForVirtReg 
) const
override

When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could replace the original code sequence.

When getMachineCombinerPatterns() finds potential patterns, this function generates the instructions that could replace the original code sequence.

Definition at line 2663 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addOperand(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), genMadd(), genMaddR(), llvm::MCInstrInfo::get(), llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getImm(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::insert(), llvm::MachineOperand::isImm(), llvm::MachineCombinerPattern::MC_MULADDW_OP1, llvm::MachineCombinerPattern::MC_MULADDW_OP2, llvm::MachineCombinerPattern::MC_MULADDWI_OP1, llvm::MachineCombinerPattern::MC_MULADDX_OP1, llvm::MachineCombinerPattern::MC_MULADDX_OP2, llvm::MachineCombinerPattern::MC_MULADDXI_OP1, llvm::MachineCombinerPattern::MC_MULSUBW_OP1, llvm::MachineCombinerPattern::MC_MULSUBW_OP2, llvm::MachineCombinerPattern::MC_MULSUBWI_OP1, llvm::MachineCombinerPattern::MC_MULSUBX_OP1, llvm::MachineCombinerPattern::MC_MULSUBX_OP2, llvm::MachineCombinerPattern::MC_MULSUBXI_OP1, llvm::ISD::MUL, llvm::AArch64_AM::processLogicalImmediate(), and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().

unsigned AArch64InstrInfo::GetInstSizeInBytes ( const MachineInstr MI) const
bool AArch64InstrInfo::getMachineCombinerPatterns ( MachineInstr Root,
SmallVectorImpl< MachineCombinerPattern::MC_PATTERN > &  Patterns 
) const
override
bool AArch64InstrInfo::getMemOpBaseRegImmOfs ( MachineInstr LdSt,
unsigned BaseReg,
unsigned Offset,
const TargetRegisterInfo TRI 
) const
override
bool AArch64InstrInfo::getMemOpBaseRegImmOfsWidth ( MachineInstr LdSt,
unsigned BaseReg,
int Offset,
int Width,
const TargetRegisterInfo TRI 
) const
void AArch64InstrInfo::getNoopForMachoTarget ( MCInst NopInst) const
override
const AArch64RegisterInfo& llvm::AArch64InstrInfo::getRegisterInfo ( ) const
inline

getRegisterInfo - TargetInstrInfo is a superset of MRegister info.

As such, whenever a client has an instance of instruction info, it should always be able to get register info as well (through this method).

Definition at line 46 of file AArch64InstrInfo.h.

Referenced by areMemAccessesTriviallyDisjoint(), copyPhysReg(), copyPhysRegTuple(), llvm::AArch64Subtarget::getRegisterInfo(), optimizeCompareInstr(), and optimizeCondBranch().

bool AArch64InstrInfo::hasExtendedReg ( const MachineInstr MI) const

Returns true if there is an extendable register and that the extending value is non-zero.

Return true if this is this instruction has a non-zero immediate.

Definition at line 1069 of file AArch64InstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::isImm().

bool AArch64InstrInfo::hasShiftedReg ( const MachineInstr MI) const

Returns true if there is a shiftable register and that the shift value is non-zero.

Return true if this is this instruction has a non-zero immediate.

Definition at line 1023 of file AArch64InstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::isImm().

unsigned AArch64InstrInfo::InsertBranch ( MachineBasicBlock MBB,
MachineBasicBlock TBB,
MachineBasicBlock FBB,
ArrayRef< MachineOperand Cond,
DebugLoc  DL 
) const
override
void AArch64InstrInfo::insertSelect ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
DebugLoc  DL,
unsigned  DstReg,
ArrayRef< MachineOperand Cond,
unsigned  TrueReg,
unsigned  FalseReg 
) const
override
bool AArch64InstrInfo::isAsCheapAsAMove ( const MachineInstr MI) const
override
bool AArch64InstrInfo::isCoalescableExtInstr ( const MachineInstr MI,
unsigned SrcReg,
unsigned DstReg,
unsigned SubIdx 
) const
override
bool AArch64InstrInfo::isFPRCopy ( const MachineInstr MI) const
bool AArch64InstrInfo::isGPRCopy ( const MachineInstr MI) const
bool AArch64InstrInfo::isGPRZero ( const MachineInstr MI) const
bool AArch64InstrInfo::isLdStPairSuppressed ( const MachineInstr MI) const

Return true if pairing the given load or store is hinted to be unprofitable.

Check all MachineMemOperands for a hint to suppress pairing.

Definition at line 1279 of file AArch64InstrInfo.cpp.

References llvm::MachineInstr::memoperands(), llvm::MachineMemOperand::MOTargetNumBits, and llvm::MachineMemOperand::MOTargetStartBit.

unsigned AArch64InstrInfo::isLoadFromStackSlot ( const MachineInstr MI,
int FrameIndex 
) const
override
bool AArch64InstrInfo::isScaledAddr ( const MachineInstr MI) const

Return true if this is load/store scales or extends its register offset.

This refers to scaling a dynamic index as opposed to scaled immediates. MI should be a memory op that allows scaled addressing.

Definition at line 1220 of file AArch64InstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::AArch64_AM::getMemDoShift(), llvm::AArch64_AM::getMemExtendType(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::AArch64_AM::UXTX.

unsigned AArch64InstrInfo::isStoreToStackSlot ( const MachineInstr MI,
int FrameIndex 
) const
override
void AArch64InstrInfo::loadRegFromStackSlot ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MBBI,
unsigned  DestReg,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI 
) const
override
bool AArch64InstrInfo::optimizeCompareInstr ( MachineInstr CmpInstr,
unsigned  SrcReg,
unsigned  SrcReg2,
int  CmpMask,
int  CmpValue,
const MachineRegisterInfo MRI 
) const
override
bool AArch64InstrInfo::optimizeCondBranch ( MachineInstr MI) const
override

Replace csincr-branch sequence by simple conditional branch.

Examples: 1. csinc w9, wzr, wzr, <condition code>=""> tbnz w9, #0, 0x44 to b.<inverted condition="" code>="">

2. csinc w9, wzr, wzr, <condition code>=""> tbz w9, #0, 0x44 to b.<condition code>="">

Parameters
MIConditional Branch
Returns
True when the simple conditional branch is generated

Definition at line 2871 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::BuildMI(), llvm::MachineInstr::eraseFromParent(), llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getImm(), llvm::AArch64CC::getInvertedCondCode(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), getRegisterInfo(), llvm::MachineRegisterInfo::getVRegDef(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm_unreachable, modifiesConditionCode(), and llvm::AArch64SysReg::NZCV.

unsigned AArch64InstrInfo::RemoveBranch ( MachineBasicBlock MBB) const
override
bool AArch64InstrInfo::ReverseBranchCondition ( SmallVectorImpl< MachineOperand > &  Cond) const
override
bool AArch64InstrInfo::shouldClusterLoads ( MachineInstr FirstLdSt,
MachineInstr SecondLdSt,
unsigned  NumLoads 
) const
override

Detect opportunities for ldp/stp formation.

Only called for LdSt for which getMemOpBaseRegImmOfs returns true.

Definition at line 1428 of file AArch64InstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), and llvm::MachineInstr::getOperand().

bool AArch64InstrInfo::shouldScheduleAdjacent ( MachineInstr First,
MachineInstr Second 
) const
override

Definition at line 1446 of file AArch64InstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

void AArch64InstrInfo::storeRegToStackSlot ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MBBI,
unsigned  SrcReg,
bool  isKill,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI 
) const
override
void AArch64InstrInfo::suppressLdStPair ( MachineInstr MI) const

Hint that pairing the given load or store is unprofitable.

Set a flag on the first MachineMemOperand to suppress pairing.

Definition at line 1292 of file AArch64InstrInfo.cpp.

References llvm::MachineInstr::memoperands_begin(), llvm::MachineInstr::memoperands_empty(), llvm::MachineMemOperand::MOTargetNumBits, and llvm::MachineMemOperand::MOTargetStartBit.

bool AArch64InstrInfo::useMachineCombiner ( ) const
override

useMachineCombiner - AArch64 supports MachineCombiner

useMachineCombiner - return true when a target supports MachineCombiner

Definition at line 2359 of file AArch64InstrInfo.cpp.


The documentation for this class was generated from the following files: