38 cl::desc(
"Disable hazard detection during preRA scheduling"));
82 bool atInsnStart =
true;
88 if (atInsnStart && !std::isspace(static_cast<unsigned char>(*Str))) {
117 Tail->getDebugLoc());
132 assert(MI->
isCommutable() &&
"Precondition violation: MI must be commutable.");
137 "This only knows how to commute register operands so far");
152 if (HasDef && Reg0 == Reg1 &&
157 }
else if (HasDef && Reg0 == Reg2 &&
192 unsigned &SrcOpIdx2)
const {
194 "TargetInstrInfo::findCommutedOpIndices() can't handle bundles");
197 if (!MCID.isCommutable())
201 SrcOpIdx1 = MCID.getNumDefs();
202 SrcOpIdx2 = SrcOpIdx1 + 1;
225 bool MadeChange =
false;
228 "TargetInstrInfo::PredicateInstruction() can't handle bundles");
234 for (
unsigned j = 0, i = 0, e = MI->
getNumOperands(); i != e; ++i) {
235 if (MCID.OpInfo[i].isPredicate()) {
240 }
else if (MO.
isImm()) {
241 MO.
setImm(Pred[j].getImm());
243 }
else if (MO.
isMBB()) {
244 MO.
setMBB(Pred[j].getMBB());
260 if ((*o)->isLoad()) {
262 dyn_cast_or_null<FixedStackPseudoSourceValue>(
263 (*o)->getPseudoValue())) {
264 FrameIndex =
Value->getFrameIndex();
280 if ((*o)->isStore()) {
282 dyn_cast_or_null<FixedStackPseudoSourceValue>(
283 (*o)->getPseudoValue())) {
284 FrameIndex =
Value->getFrameIndex();
294 unsigned SubIdx,
unsigned &Size,
310 if (BitOffset < 0 || BitOffset % 8)
316 assert(RC->
getSize() >= (Offset + Size) &&
"bad subregister range");
319 Offset = RC->
getSize() - (Offset + Size);
345 "Instruction cannot be duplicated");
353 assert(MI->
isCopy() &&
"MI must be a COPY instruction");
356 assert(FoldIdx<2 &&
"FoldIdx refers no nonexistent operand");
364 unsigned FoldReg = FoldOp.
getReg();
365 unsigned LiveReg = LiveOp.
getReg();
368 "Cannot fold physregs");
395 unsigned StartIdx = 0;
412 for (
unsigned Op : Ops) {
422 for (
unsigned i = 0; i < StartIdx; ++i)
427 if (std::find(Ops.begin(), Ops.end(), i) != Ops.end()) {
429 unsigned SpillOffset;
458 for (
unsigned i = 0, e = Ops.
size(); i != e; ++i)
459 if (MI->getOperand(Ops[i]).isDef())
465 assert(MBB &&
"foldMemoryOperand needs an inserted instruction");
482 NewMI->
setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
486 "Folded a def to a non-store!");
489 "Folded a use to a non-load!");
502 if (!MI->isCopy() || Ops.
size() != 1)
528 for (
unsigned i = 0, e = Ops.
size(); i != e; ++i)
529 assert(MI->getOperand(Ops[i]).isUse() &&
"Folding load into def!");
544 NewMI = MBB.
insert(MI, NewMI);
550 if (!NewMI)
return nullptr;
553 if (MI->memoperands_empty()) {
560 MI->memoperands_end());
569 bool TargetInstrInfo::
614 if (!MO.
isReg())
continue;
636 if (MO.
isDef() && Reg != DefReg)
653 bool StackGrowsDown =
659 if (MI->
getOpcode() != FrameSetupOpcode &&
665 if ((!StackGrowsDown && MI->
getOpcode() == FrameSetupOpcode) ||
666 (StackGrowsDown && MI->
getOpcode() == FrameDestroyOpcode))
731 SDNode *DefNode,
unsigned DefIdx,
732 SDNode *UseNode,
unsigned UseIdx)
const {
733 if (!ItinData || ItinData->
isEmpty())
748 if (!ItinData || ItinData->
isEmpty())
764 if (!ItinData || ItinData->
isEmpty())
796 unsigned *PredCost)
const {
807 unsigned DefIdx)
const {
809 if (!ItinData || ItinData->
isEmpty())
814 return (DefCycle != -1 && DefCycle <= 1);
865 assert(ItinData && !ItinData->
isEmpty() &&
"computeDefOperandLatency fail");
874 if (OperLatency >= 0)
881 InstrLatency = std::max(InstrLatency,
897 assert(DefIdx == 0 &&
"REG_SEQUENCE only has one def");
898 for (
unsigned OpIdx = 1, EndOpIdx = MI.
getNumOperands(); OpIdx != EndOpIdx;
902 assert(MOSubIdx.
isImm() &&
903 "One of the subindex of the reg_sequence is not an immediate");
922 assert(DefIdx == 0 &&
"EXTRACT_SUBREG only has one def");
925 assert(MOSubIdx.
isImm() &&
926 "The subindex of the extract_subreg is not an immediate");
945 assert(DefIdx == 0 &&
"INSERT_SUBREG only has one def");
949 assert(MOSubIdx.
isImm() &&
950 "One of the subindex of the reg_sequence is not an immediate");
954 InsertedReg.
Reg = MOInsertedReg.
getReg();
bool isConstantPhysReg(unsigned PhysReg, const MachineFunction &MF) const
isConstantPhysReg - Returns true if PhysReg is unallocatable and constant throughout the function...
virtual MachineInstr * duplicate(MachineInstr *Orig, MachineFunction &MF) const
Create a duplicate of the Orig instruction in MF.
virtual ScheduleHazardRecognizer * CreateTargetMIHazardRecognizer(const InstrItineraryData *, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
void push_back(const T &Elt)
The memory access reads data.
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
The memory access writes data.
MachineInstr * CreateMachineInstr(const MCInstrDesc &MCID, DebugLoc DL, bool NoImp=false)
CreateMachineInstr - Allocate a new MachineInstr.
virtual bool hasStoreToStackSlot(const MachineInstr *MI, const MachineMemOperand *&MMO, int &FrameIndex) const
If the specified machine instruction has a store to a stack slot, return true along with the FrameInd...
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
unsigned computeOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const
Compute and return the latency of the given data dependent def and use when the operand indices are a...
virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx, unsigned &Size, unsigned &Offset, const MachineFunction &MF) const
Compute the size in bytes and offset within a stack slot of a spilled register or subregister...
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
virtual bool hasLoadFromStackSlot(const MachineInstr *MI, const MachineMemOperand *&MMO, int &FrameIndex) const
If the specified machine instruction has a load from a stack slot, return true along with the FrameIn...
bool usePreRAHazardRecognizer() const
Provide a global flag for disabling the PreRA hazard recognizer that targets may choose to honor...
bool hasSubClassEq(const TargetRegisterClass *RC) const
hasSubClassEq - Returns true if RC is a sub-class of or equal to this class.
Describe properties that are true of each instruction in the target description file.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
void setIsUndef(bool Val=true)
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
bool getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const
Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx.
A Stackmap instruction captures the location of live variables at its position in the instruction str...
bool isPredicable(QueryType Type=AllInBundle) const
Return true if this instruction has a predicate operand that controls execution.
bool readsVirtualRegister(unsigned Reg) const
Return true if the MachineInstr reads the specified virtual register.
virtual ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
static cl::opt< bool > DisableHazardRecognizer("disable-sched-hazard", cl::Hidden, cl::init(false), cl::desc("Disable hazard detection during preRA scheduling"))
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
virtual bool isSchedulingBoundary(const MachineInstr *MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const
Test if the given instruction should be considered a scheduling boundary.
virtual void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SubIdx, const MachineInstr *Orig, const TargetRegisterInfo &TRI) const
Re-issue the specified 'original' instruction at the specific location targeting a new destination re...
bool canFoldAsLoad(QueryType Type=IgnoreBundle) const
Return true for instructions that can be folded as memory operands in other instructions.
unsigned getVarIdx() const
Get the operand index of the variable list of non-argument operands.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, unsigned f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
getMachineMemOperand - Allocate a new MachineMemOperand.
bool isExtractSubreg() const
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag=true)
Reports a serious error, calling any installed error handler.
static MachinePointerInfo getFixedStack(int FI, int64_t offset=0)
getFixedStack - Return a MachinePointerInfo record that refers to the the specified FrameIndex...
int NumMicroOps
of micro-ops, -1 means it's variable
virtual unsigned getPredicationCost(const MachineInstr *MI) const
virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel, const MachineInstr *DefMI, unsigned DefIdx) const
Compute operand latency of a def of 'Reg'.
unsigned getSize() const
getSize - Return the size of the register in bytes, which is also the size of a stack slot allocated ...
int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const
Return the cycle for the given class and operand.
MachineMemOperand - A description of a memory reference used in the backend.
unsigned getCallFrameDestroyOpcode() const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
Provide an instruction scheduling machine model to CodeGen passes.
const HexagonInstrInfo * TII
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const InstrItinerary * Itineraries
Array of itineraries selected.
const TargetRegisterClass * getRegClass(unsigned i) const
getRegClass - Returns the register class associated with the enumeration value.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
const TargetRegisterClass * getRegClass(unsigned Reg) const
getRegClass - Return the register class of the specified virtual register.
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
static MachineInstr * foldPatchpoint(MachineFunction &MF, MachineInstr *MI, ArrayRef< unsigned > Ops, int FrameIndex, const TargetInstrInfo &TII)
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual bool produceSameValue(const MachineInstr *MI0, const MachineInstr *MI1, const MachineRegisterInfo *MRI=nullptr) const
Return true if two machine instructions would produce identical values.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
unsigned getCallFrameSetupOpcode() const
These methods return the opcode of the frame setup/destroy instructions if they exist (-1 otherwise)...
virtual MachineInstr * commuteInstruction(MachineInstr *MI, bool NewMI=false) const
If a target has any instructions that are commutable but require converting to different instructions...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
bool isLittleEndian() const
Layout endianness...
Itinerary data supplied by a subtarget to be used by a target.
bool isImmutableObjectIndex(int ObjectIdx) const
isImmutableObjectIndex - Returns true if the specified index corresponds to an immutable object...
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
size_t size() const
size - Get the array size.
virtual unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr *MI, unsigned *PredCost=nullptr) const
Compute the instruction latency of a given instruction.
Instances of this class represent a single low-level machine instruction.
bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const
Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineBasicBlock * getParent() const
TargetInstrInfo - Interface to description of machine instruction set.
This class is intended to be used as a base class for asm properties and features specific to the tar...
mmo_iterator memoperands_end() const
bool isInsertSubreg() const
bundle_iterator< MachineInstr, instr_iterator > iterator
initializer< Ty > init(const Ty &Val)
Patchable call instruction - this instruction represents a call to a constant address, followed by a series of NOPs.
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
const InstrItineraryData * getInstrItineraries() const
unsigned defaultDefLatency(const MCSchedModel &SchedModel, const MachineInstr *DefMI) const
Return the default expected latency for a def based on it's opcode.
const MachineOperand & getOperand(unsigned i) const
unsigned getStageLatency(unsigned ItinClassIndx) const
Return the total stage latency of the given class.
virtual int getSPAdjust(const MachineInstr *MI) const
Returns the actual stack pointer adjustment made by an instruction as part of a call sequence...
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Load the specified register of the given register class from the specified stack frame index...
void setMBB(MachineBasicBlock *MBB)
virtual bool getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const
Target-dependent implementation of getInsertSubregInputs.
void setImm(int64_t immVal)
void setIsInternalRead(bool Val=true)
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore...
MI-level patchpoint operands.
bool isInvariantLoad(AliasAnalysis *AA) const
Return true if this instruction is loading from a location whose value is invariant across the functi...
virtual void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Store the specified register of the given register class to the specified stack frame index...
unsigned getStackPointerRegisterToSaveRestore() const
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save...
succ_iterator succ_begin()
void removeSuccessor(MachineBasicBlock *succ)
removeSuccessor - Remove successor from the successors list of this MachineBasicBlock.
unsigned getSubReg() const
bool isNotDuplicable(QueryType Type=AnyInBundle) const
Return true if this instruction cannot be safely duplicated.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
void setIsKill(bool Val=true)
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
bool isInsertSubregLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions...
virtual const TargetFrameLowering * getFrameLowering() const
void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
virtual void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
Insert a noop into the instruction stream at the specified point.
virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const
If specified MI is commutable, return the two operand indices that would swap value.
bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const
Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx.
bool isIdenticalTo(const MachineInstr *Other, MICheckType Check=CheckDefs) const
Return true if this instruction is identical to (same opcode and same operands as) the specified inst...
MachineInstr * CloneMachineInstr(const MachineInstr *Orig)
CloneMachineInstr - Create a new MachineInstr which is a copy of the 'Orig' instruction, identical in all ways except the instruction has no parent, prev, or next.
const DataLayout * getDataLayout() const
Deprecated in 3.7, will be removed in 3.8.
virtual ~TargetInstrInfo()
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
A pair composed of a register and a sub-register index.
virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr *MI) const
Return the number of u-operations the given machine instruction will be decoded to on the target cpu...
virtual const TargetLowering * getTargetLowering() const
Information about stack frame layout on the target.
virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const
Returns true if the instruction is a terminator instruction that has not been predicated.
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Represents one node in the SelectionDAG.
const MachineInstrBuilder & addFrameIndex(int Idx) const
bool isTransient() const
Return true if this is a transient instruction that is either very likely to be eliminated during reg...
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
MachineInstr * foldMemoryOperand(MachineBasicBlock::iterator MI, ArrayRef< unsigned > Ops, int FrameIndex) const
Attempt to fold a load or store of the specified stack slot into the specified machine instruction fo...
bool isExtractSubregLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
int getOperandLatency(unsigned DefClass, unsigned DefIdx, unsigned UseClass, unsigned UseIdx) const
Compute and return the use operand latency of a given itinerary class and operand index if the value ...
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const
Target-dependent implementation of getExtractSubregInputs.
Representation of each machine instruction.
static bool isPhysicalRegister(unsigned Reg)
isPhysicalRegister - Return true if the specified register number is in the physical register namespa...
StackDirection getStackGrowthDirection() const
getStackGrowthDirection - Return the direction the stack grows
unsigned getSchedClass() const
Return the scheduling class for this instruction.
virtual unsigned getInlineAsmLength(const char *Str, const MCAsmInfo &MAI) const
Measure the specified inline asm to determine an approximation of its length.
MCSchedModel SchedModel
Basic machine properties.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
If the specified machine instruction is a direct load from a stack slot, return the virtual or physic...
const char * getSeparatorString() const
void setReg(unsigned Reg)
Change the register this operand corresponds to.
void setSubReg(unsigned subReg)
virtual bool getRegSequenceLikeInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const
Target-dependent implementation of getRegSequenceInputs.
virtual void getNoopForMachoTarget(MCInst &NopInst) const
Return the noop instruction to use for a noop.
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
virtual int getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const
bool isLookupPtrRegClass() const
Set if this operand is a pointer value and it requires a callback to look up its register class...
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, DebugLoc DL) const
Insert branch code into the end of the specified MachineBasicBlock.
virtual bool canFoldMemoryOperand(const MachineInstr *MI, ArrayRef< unsigned > Ops) const
Returns true for the specified load / store if folding is possible.
unsigned getSubRegIdxOffset(unsigned Idx) const
Get the offset of the bit range covered by a sub-register index.
static const TargetRegisterClass * canFoldCopy(const MachineInstr *MI, unsigned FoldIdx)
virtual ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
unsigned getReg() const
getReg - Returns the register number.
bool isCommutable(QueryType Type=IgnoreBundle) const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged.
virtual bool PredicateInstruction(MachineInstr *MI, ArrayRef< MachineOperand > Pred) const
Convert the instruction into a predicated instruction.
LLVM Value Representation.
unsigned getMaxInstLength() const
int computeDefOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI) const
If we can determine the operand latency from the def only, without itinerary lookup, do so.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
const MCOperandInfo * OpInfo
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
BasicBlockListType::iterator iterator
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex) const
Target-dependent implementation for foldMemoryOperand.
virtual bool isPredicated(const MachineInstr *MI) const
Returns true if the instruction is already predicated.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
const TargetRegisterClass * getRegClass(const MCInstrDesc &TID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum...
FixedStackPseudoSourceValue - A specialized PseudoSourceValue for holding FixedStack values...
virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const
Delete the instruction OldInst and everything after it, replacing it with an unconditional branch to ...
unsigned getSubRegIdxSize(unsigned Idx) const
Get the size of the bit range covered by a sub-register index.
bool isRegSequence() const
bool isRegSequenceLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions.
Machine model for scheduling, bundling, and heuristics.
bool isEmpty() const
Returns true if there are no itineraries.
const char * getCommentString() const
void addSuccessor(MachineBasicBlock *succ, uint32_t weight=0)
addSuccessor - Add succ as a successor of this MachineBasicBlock.
virtual const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const
getPointerRegClass - Returns a TargetRegisterClass used for pointer values.
void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd)
Assign this MachineInstr's memory reference descriptor list.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
virtual bool isHighLatencyDef(int opc) const
Return true if this opcode has high latency to its result.
bool isInternalRead() const
bool isMachineOpcode() const
Test if this node has a post-isel opcode, directly corresponding to a MachineInstr opcode...
This file describes how to lower LLVM code to machine code.
unsigned getMachineOpcode() const
This may only be called if isMachineOpcode returns true.
A pair composed of a pair of a register and a sub-register index, and another sub-register index...
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
bool contains(unsigned Reg) const
contains - Return true if the specified register is included in this register class.