LLVM  3.7.0
Mips16RegisterInfo.cpp
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1 //===-- Mips16RegisterInfo.cpp - MIPS16 Register Information --------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the MIPS16 implementation of the TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "Mips16RegisterInfo.h"
15 #include "Mips.h"
16 #include "Mips16InstrInfo.h"
17 #include "MipsAnalyzeImmediate.h"
18 #include "MipsInstrInfo.h"
19 #include "MipsMachineFunction.h"
20 #include "MipsSubtarget.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/STLExtras.h"
27 #include "llvm/IR/Constants.h"
28 #include "llvm/IR/DebugInfo.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/Type.h"
32 #include "llvm/Support/Debug.h"
39 
40 using namespace llvm;
41 
42 #define DEBUG_TYPE "mips16-registerinfo"
43 
45 
47  (const MachineFunction &MF) const {
48  return false;
49 }
51  (const MachineFunction &MF) const {
52  return false;
53 }
54 
56  (const MachineFunction &MF) const {
57  return false;
58 }
59 
64  const TargetRegisterClass *RC,
65  unsigned Reg) const {
66  DebugLoc DL;
68  TII.copyPhysReg(MBB, I, DL, Mips::T0, Reg, true);
69  TII.copyPhysReg(MBB, UseMI, DL, Reg, Mips::T0, true);
70  return true;
71 }
72 
73 const TargetRegisterClass *
74 Mips16RegisterInfo::intRegClass(unsigned Size) const {
75  assert(Size == 4);
76  return &Mips::CPU16RegsRegClass;
77 }
78 
79 void Mips16RegisterInfo::eliminateFI(MachineBasicBlock::iterator II,
80  unsigned OpNo, int FrameIndex,
81  uint64_t StackSize,
82  int64_t SPOffset) const {
83  MachineInstr &MI = *II;
84  MachineFunction &MF = *MI.getParent()->getParent();
85  MachineFrameInfo *MFI = MF.getFrameInfo();
86 
87  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
88  int MinCSFI = 0;
89  int MaxCSFI = -1;
90 
91  if (CSI.size()) {
92  MinCSFI = CSI[0].getFrameIdx();
93  MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
94  }
95 
96  // The following stack frame objects are always
97  // referenced relative to $sp:
98  // 1. Outgoing arguments.
99  // 2. Pointer to dynamically allocated stack space.
100  // 3. Locations for callee-saved registers.
101  // Everything else is referenced relative to whatever register
102  // getFrameRegister() returns.
103  unsigned FrameReg;
104 
105  if (FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI)
106  FrameReg = Mips::SP;
107  else {
109  if (TFI->hasFP(MF)) {
110  FrameReg = Mips::S0;
111  }
112  else {
113  if ((MI.getNumOperands()> OpNo+2) && MI.getOperand(OpNo+2).isReg())
114  FrameReg = MI.getOperand(OpNo+2).getReg();
115  else
116  FrameReg = Mips::SP;
117  }
118  }
119  // Calculate final offset.
120  // - There is no need to change the offset if the frame object
121  // is one of the
122  // following: an outgoing argument, pointer to a dynamically allocated
123  // stack space or a $gp restore location,
124  // - If the frame object is any of the following,
125  // its offset must be adjusted
126  // by adding the size of the stack:
127  // incoming argument, callee-saved register location or local variable.
128  int64_t Offset;
129  bool IsKill = false;
130  Offset = SPOffset + (int64_t)StackSize;
131  Offset += MI.getOperand(OpNo + 1).getImm();
132 
133 
134  DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n");
135 
136  if (!MI.isDebugValue() &&
137  !Mips16InstrInfo::validImmediate(MI.getOpcode(), FrameReg, Offset)) {
138  MachineBasicBlock &MBB = *MI.getParent();
139  DebugLoc DL = II->getDebugLoc();
140  unsigned NewImm;
141  const Mips16InstrInfo &TII =
142  *static_cast<const Mips16InstrInfo *>(MF.getSubtarget().getInstrInfo());
143  FrameReg = TII.loadImmediate(FrameReg, Offset, MBB, II, DL, NewImm);
144  Offset = SignExtend64<16>(NewImm);
145  IsKill = true;
146  }
147  MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
148  MI.getOperand(OpNo + 1).ChangeToImmediate(Offset);
149 
150 
151 }
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
bool useFPForScavengingIndex(const MachineFunction &MF) const override
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
unsigned loadImmediate(unsigned FrameReg, int64_t Imm, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, DebugLoc DL, unsigned &NewImm) const
Emit a series of instructions to load an immediate.
A debug info location.
Definition: DebugLoc.h:34
bool saveScavengerRegister(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, unsigned Reg) const override
bool requiresRegisterScavenging(const MachineFunction &MF) const override
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const HexagonInstrInfo * TII
virtual bool hasFP(const MachineFunction &MF) const =0
hasFP - Return true if the specified function should have a dedicated frame pointer register...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
static bool validImmediate(unsigned Opcode, unsigned Reg, int64_t Amount)
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:271
const TargetRegisterClass * intRegClass(unsigned Size) const override
Return GPR register class.
int64_t getImm() const
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:267
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:120
TargetInstrInfo - Interface to description of machine instruction set.
bool isDebugValue() const
Definition: MachineInstr.h:748
bundle_iterator< MachineInstr, instr_iterator > iterator
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
virtual const TargetFrameLowering * getFrameLowering() const
Information about stack frame layout on the target.
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
virtual void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const
Emit instructions to copy a pair of physical registers.
Representation of each machine instruction.
Definition: MachineInstr.h:51
#define I(x, y, z)
Definition: MD5.cpp:54
unsigned getReg() const
getReg - Returns the register number.
virtual const TargetInstrInfo * getInstrInfo() const
#define DEBUG(X)
Definition: Debug.h:92