28 #define DEBUG_TYPE "systemz-lower"
33 struct IPMConversion {
34 IPMConversion(
unsigned xorValue, int64_t addValue,
unsigned bit)
35 : XORValue(xorValue), AddValue(addValue),
Bit(bit) {}
45 : Op0(Op0In), Op1(Op1In), Opcode(0), ICmpType(0), CCValid(0), CCMask(0) {}
533 return FromBits > ToBits;
541 return FromBits > ToBits;
550 if (Constraint.
size() == 1) {
551 switch (Constraint[0]) {
582 const char *constraint)
const {
591 switch (*constraint) {
610 if (
auto *
C = dyn_cast<ConstantInt>(CallOperandVal))
616 if (
auto *
C = dyn_cast<ConstantInt>(CallOperandVal))
617 if (isUInt<12>(
C->getZExtValue()))
622 if (
auto *
C = dyn_cast<ConstantInt>(CallOperandVal))
628 if (
auto *
C = dyn_cast<ConstantInt>(CallOperandVal))
629 if (isInt<20>(
C->getSExtValue()))
634 if (
auto *
C = dyn_cast<ConstantInt>(CallOperandVal))
635 if (
C->getZExtValue() == 0x7fffffff)
645 static std::pair<unsigned, const TargetRegisterClass *>
647 const unsigned *Map) {
648 assert(*(Constraint.
end()-1) ==
'}' &&
"Missing '}'");
649 if (isdigit(Constraint[2])) {
652 Constraint.
slice(2, Constraint.
size() - 1).getAsInteger(10, Index);
653 if (!Failed && Index < 16 && Map[Index])
654 return std::make_pair(Map[Index], RC);
656 return std::make_pair(0U,
nullptr);
659 std::pair<unsigned, const TargetRegisterClass *>
662 if (Constraint.
size() == 1) {
664 switch (Constraint[0]) {
669 return std::make_pair(0U, &SystemZ::GR64BitRegClass);
671 return std::make_pair(0U, &SystemZ::GR128BitRegClass);
672 return std::make_pair(0U, &SystemZ::GR32BitRegClass);
676 return std::make_pair(0U, &SystemZ::ADDR64BitRegClass);
678 return std::make_pair(0U, &SystemZ::ADDR128BitRegClass);
679 return std::make_pair(0U, &SystemZ::ADDR32BitRegClass);
682 return std::make_pair(0U, &SystemZ::GRH32BitRegClass);
686 return std::make_pair(0U, &SystemZ::FP64BitRegClass);
688 return std::make_pair(0U, &SystemZ::FP128BitRegClass);
689 return std::make_pair(0U, &SystemZ::FP32BitRegClass);
692 if (Constraint.
size() > 0 && Constraint[0] ==
'{') {
697 if (Constraint[1] ==
'r') {
707 if (Constraint[1] ==
'f') {
723 std::vector<SDValue> &Ops,
726 if (Constraint.length() == 1) {
727 switch (Constraint[0]) {
729 if (
auto *
C = dyn_cast<ConstantSDNode>(Op))
736 if (
auto *
C = dyn_cast<ConstantSDNode>(Op))
737 if (isUInt<12>(
C->getZExtValue()))
743 if (
auto *
C = dyn_cast<ConstantSDNode>(Op))
750 if (
auto *
C = dyn_cast<ConstantSDNode>(Op))
751 if (isInt<20>(
C->getSExtValue()))
757 if (
auto *
C = dyn_cast<ConstantSDNode>(Op))
758 if (
C->getZExtValue() == 0x7fffffff)
771 #include "SystemZGenCallingConv.inc"
774 Type *ToType)
const {
793 for (
unsigned i = 0; i < Ins.
size(); ++i)
798 for (
unsigned i = 0; i < Outs.
size(); ++i)
884 unsigned NumFixedGPRs = 0;
885 unsigned NumFixedFPRs = 0;
886 for (
unsigned I = 0, E = ArgLocs.
size();
I != E; ++
I) {
899 RC = &SystemZ::GR32BitRegClass;
903 RC = &SystemZ::GR64BitRegClass;
907 RC = &SystemZ::FP32BitRegClass;
911 RC = &SystemZ::FP64BitRegClass;
919 RC = &SystemZ::VR128BitRegClass;
927 assert(VA.
isMemLoc() &&
"Argument not register or memory");
941 ArgValue = DAG.
getLoad(LocVT, DL, Chain, FIN,
943 false,
false,
false, 0);
958 int64_t StackSize = CCInfo.getNextStackOffset();
963 int64_t RegSaveOffset = TFL->getOffsetOfLocalArea();
976 &SystemZ::FP64BitRegClass);
986 SystemZ::NumArgFPRs-NumFixedFPRs));
997 for (
unsigned I = 0, E = ArgLocs.
size();
I != E; ++
I) {
1004 if (Reg == SystemZ::R6H || Reg == SystemZ::R6L || Reg == SystemZ::R6D)
1043 unsigned NumBytes = ArgCCInfo.getNextStackOffset();
1055 for (
unsigned I = 0, E = ArgLocs.
size();
I != E; ++
I) {
1062 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
1066 ArgValue = SpillSlot;
1074 assert(VA.
isMemLoc() &&
"Argument not register or memory");
1094 if (!MemOpChains.
empty())
1101 if (
auto *
G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1104 }
else if (
auto *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1107 }
else if (IsTailCall) {
1108 Chain = DAG.
getCopyToReg(Chain, DL, SystemZ::R1D, Callee, Glue);
1114 for (
unsigned I = 0, E = RegsToPass.
size();
I != E; ++
I) {
1116 RegsToPass[
I].second, Glue);
1127 for (
unsigned I = 0, E = RegsToPass.
size();
I != E; ++
I)
1129 RegsToPass[I].second.getValueType()));
1134 assert(Mask &&
"Missing call preserved mask for calling convention");
1161 for (
unsigned I = 0, E = RetLocs.
size(); I != E; ++
I) {
1188 CCState RetCCInfo(CallConv, isVarArg, MF, RetLocs, Context);
1189 return RetCCInfo.
CheckReturn(Outs, RetCC_SystemZ);
1210 if (RetLocs.
empty())
1217 for (
unsigned I = 0, E = RetLocs.
size();
I != E; ++
I) {
1222 assert(VA.
isRegLoc() &&
"Can only return in registers!");
1229 Chain = DAG.
getCopyToReg(Chain, DL, Reg, RetValue, Glue);
1251 unsigned &CCValid) {
1252 unsigned Id = cast<ConstantSDNode>(Op.
getOperand(1))->getZExtValue();
1254 case Intrinsic::s390_tbegin:
1259 case Intrinsic::s390_tbegin_nofloat:
1264 case Intrinsic::s390_tend:
1278 unsigned Id = cast<ConstantSDNode>(Op.
getOperand(0))->getZExtValue();
1280 case Intrinsic::s390_vpkshs:
1281 case Intrinsic::s390_vpksfs:
1282 case Intrinsic::s390_vpksgs:
1287 case Intrinsic::s390_vpklshs:
1288 case Intrinsic::s390_vpklsfs:
1289 case Intrinsic::s390_vpklsgs:
1294 case Intrinsic::s390_vceqbs:
1295 case Intrinsic::s390_vceqhs:
1296 case Intrinsic::s390_vceqfs:
1297 case Intrinsic::s390_vceqgs:
1302 case Intrinsic::s390_vchbs:
1303 case Intrinsic::s390_vchhs:
1304 case Intrinsic::s390_vchfs:
1305 case Intrinsic::s390_vchgs:
1310 case Intrinsic::s390_vchlbs:
1311 case Intrinsic::s390_vchlhs:
1312 case Intrinsic::s390_vchlfs:
1313 case Intrinsic::s390_vchlgs:
1318 case Intrinsic::s390_vtm:
1323 case Intrinsic::s390_vfaebs:
1324 case Intrinsic::s390_vfaehs:
1325 case Intrinsic::s390_vfaefs:
1330 case Intrinsic::s390_vfaezbs:
1331 case Intrinsic::s390_vfaezhs:
1332 case Intrinsic::s390_vfaezfs:
1337 case Intrinsic::s390_vfeebs:
1338 case Intrinsic::s390_vfeehs:
1339 case Intrinsic::s390_vfeefs:
1344 case Intrinsic::s390_vfeezbs:
1345 case Intrinsic::s390_vfeezhs:
1346 case Intrinsic::s390_vfeezfs:
1351 case Intrinsic::s390_vfenebs:
1352 case Intrinsic::s390_vfenehs:
1353 case Intrinsic::s390_vfenefs:
1358 case Intrinsic::s390_vfenezbs:
1359 case Intrinsic::s390_vfenezhs:
1360 case Intrinsic::s390_vfenezfs:
1365 case Intrinsic::s390_vistrbs:
1366 case Intrinsic::s390_vistrhs:
1367 case Intrinsic::s390_vistrfs:
1372 case Intrinsic::s390_vstrcbs:
1373 case Intrinsic::s390_vstrchs:
1374 case Intrinsic::s390_vstrcfs:
1379 case Intrinsic::s390_vstrczbs:
1380 case Intrinsic::s390_vstrczhs:
1381 case Intrinsic::s390_vstrczfs:
1386 case Intrinsic::s390_vfcedbs:
1391 case Intrinsic::s390_vfchdbs:
1396 case Intrinsic::s390_vfchedbs:
1401 case Intrinsic::s390_vftcidb:
1419 for (
unsigned I = 2;
I < NumOps; ++
I)
1422 assert(Op->
getNumValues() == 2 &&
"Expected only CC result and chain");
1438 for (
unsigned I = 1;
I < NumOps; ++
I)
1443 assert(Op->
getNumValues() == 2 &&
"Expected exactly one non-CC result");
1455 case ISD::SET##X: return SystemZ::CCMASK_CMP_##X; \
1456 case ISD::SETO##X: return SystemZ::CCMASK_CMP_##X; \
1457 case ISD::SETU##X: return SystemZ::CCMASK_CMP_UO | SystemZ::CCMASK_CMP_##X
1494 uint64_t TopBit = uint64_t(1) << 31;
1499 if (CCMask == (CCValid & (SystemZ::CCMASK_0
1507 | SystemZ::CCMASK_3)))
1519 if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_3)))
1530 if (CCMask == (CCValid & (SystemZ::CCMASK_0
1532 | SystemZ::CCMASK_3)))
1534 if (CCMask == (CCValid & (SystemZ::CCMASK_0
1536 | SystemZ::CCMASK_3)))
1553 int64_t
Value = ConstOp1->getSExtValue();
1559 C.Op1 = DAG.
getConstant(0, DL, C.Op1.getValueType());
1568 if (!C.Op0.hasOneUse() ||
1574 auto *
Load = cast<LoadSDNode>(C.Op0);
1575 unsigned NumBits =
Load->getMemoryVT().getStoreSizeInBits();
1576 if (NumBits != 8 && NumBits != 16)
1581 auto *ConstOp1 = cast<ConstantSDNode>(C.Op1);
1582 uint64_t
Value = ConstOp1->getZExtValue();
1583 uint64_t Mask = (1 << NumBits) - 1;
1586 int64_t SignedValue = ConstOp1->getSExtValue();
1587 if (uint64_t(SignedValue) + (uint64_t(1) << (NumBits - 1)) > Mask)
1593 }
else if (NumBits == 8) {
1611 "Signedness shouldn't matter here.");
1619 if (C.Op0.getValueType() !=
MVT::i32 ||
1620 Load->getExtensionType() != ExtType)
1622 Load->getChain(),
Load->getBasePtr(),
1623 Load->getPointerInfo(),
Load->getMemoryVT(),
1624 Load->isVolatile(),
Load->isNonTemporal(),
1625 Load->isInvariant(),
Load->getAlignment());
1628 if (C.Op1.getValueType() !=
MVT::i32 ||
1629 Value != ConstOp1->getZExtValue())
1642 switch (
Load->getExtensionType()) {
1665 if (isa<ConstantFPSDNode>(C.Op1))
1671 if (ConstOp1 && ConstOp1->getZExtValue() == 0)
1700 unsigned Opcode0 = C.Op0.getOpcode();
1708 cast<ConstantSDNode>(C.Op0.getOperand(1))->getZExtValue() == 0xffffffff)
1729 for (
auto I = C.Op0->use_begin(), E = C.Op0->use_end();
I != E; ++
I) {
1748 if (C1 && C1->isZero()) {
1749 for (
auto I = C.Op0->use_begin(), E = C.Op0->use_end();
I != E; ++
I) {
1768 if (C.Op0.getOpcode() ==
ISD::SHL &&
1769 C.Op0.getValueType() ==
MVT::i64 &&
1771 cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
1773 if (C1 && C1->getZExtValue() == 32) {
1774 SDValue ShlOp0 = C.Op0.getOperand(0);
1793 C.Op0.getOperand(0).getOpcode() ==
ISD::LOAD &&
1795 cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
1796 auto *L = cast<LoadSDNode>(C.Op0.getOperand(0));
1797 if (L->getMemoryVT().getStoreSizeInBits()
1798 <= C.Op0.getValueType().getSizeInBits()) {
1799 unsigned Type = L->getExtensionType();
1802 C.Op0 = C.Op0.getOperand(0);
1803 C.Op1 = DAG.
getConstant(0, DL, C.Op0.getValueType());
1831 uint64_t Mask, uint64_t CmpVal,
1832 unsigned ICmpType) {
1833 assert(Mask != 0 &&
"ANDs with zero should have been removed by now");
1842 uint64_t High = uint64_t(1) << HighShift;
1856 if (EffectivelyUnsigned && CmpVal <= Low) {
1862 if (EffectivelyUnsigned && CmpVal < Low) {
1870 if (CmpVal == Mask) {
1876 if (EffectivelyUnsigned && CmpVal >= Mask - Low && CmpVal < Mask) {
1882 if (EffectivelyUnsigned && CmpVal > Mask - Low && CmpVal <= Mask) {
1890 if (EffectivelyUnsigned && CmpVal >= Mask - High && CmpVal < High) {
1896 if (EffectivelyUnsigned && CmpVal > Mask - High && CmpVal <= High) {
1905 if (Mask == Low + High) {
1933 if (C.Op0.getOpcode() ==
ISD::AND) {
1934 NewC.Op0 = C.Op0.getOperand(0);
1935 NewC.Op1 = C.Op0.getOperand(1);
1944 if (NewC.Op0.getValueType() !=
MVT::i64 ||
1952 if (CmpVal == uint64_t(-1))
1959 MaskVal = -(CmpVal & -CmpVal);
1967 unsigned BitSize = NewC.Op0.getValueType().getSizeInBits();
1968 unsigned NewCCMask, ShiftVal;
1970 NewC.Op0.getOpcode() ==
ISD::SHL &&
1973 MaskVal >> ShiftVal,
1976 NewC.Op0 = NewC.Op0.getOperand(0);
1977 MaskVal >>= ShiftVal;
1979 NewC.Op0.getOpcode() ==
ISD::SRL &&
1982 MaskVal << ShiftVal,
1985 NewC.Op0 = NewC.Op0.getOperand(0);
1986 MaskVal <<= ShiftVal;
2000 C.Op1 = DAG.
getConstant(MaskVal, DL, C.Op0.getValueType());
2002 C.CCMask = NewCCMask;
2012 Comparison C(Call,
SDValue());
2014 C.CCValid = CCValid;
2017 C.CCMask = CC < 4 ? 1 << (3 - CC) : 0;
2020 C.CCMask = CC < 4 ? ~(1 << (3 - CC)) : -1;
2024 C.CCMask = CC < 4 ? ~0U << (4 - CC) : -1;
2027 C.CCMask = CC < 4 ? ~(~0U << (4 - CC)) : 0;
2031 C.CCMask = CC < 4 ? ~0U << (3 - CC) : -1;
2034 C.CCMask = CC < 4 ? ~(~0U << (3 - CC)) : 0;
2037 C.CCMask &= CCValid;
2045 uint64_t
Constant = cast<ConstantSDNode>(CmpOp1)->getZExtValue();
2046 unsigned Opcode, CCValid;
2056 Comparison C(CmpOp0, CmpOp1);
2058 if (C.Op0.getValueType().isFloatingPoint()) {
2097 if (!C.Op1.getNode()) {
2099 switch (C.Op0.getOpcode()) {
2144 unsigned Extend,
unsigned Opcode,
2159 unsigned CCValid,
unsigned CCMask) {
2163 if (Conversion.XORValue)
2167 if (Conversion.AddValue)
2174 if (Conversion.Bit != 31)
2229 int Mask[] = { Start, -1, Start + 1, -1 };
2249 return DAG.
getNode(Opcode, DL, VT, CmpOp0, CmpOp1);
2258 bool Invert =
false;
2265 assert(IsFP &&
"Unexpected integer comparison");
2276 assert(IsFP &&
"Unexpected integer comparison");
2288 Cmp =
getVectorCmp(DAG, Opcode, DL, VT, CmpOp0, CmpOp1);
2292 Cmp =
getVectorCmp(DAG, Opcode, DL, VT, CmpOp1, CmpOp0);
2317 Comparison
C(
getCmp(DAG, CmpOp0, CmpOp1, CC,
DL));
2329 Comparison
C(
getCmp(DAG, CmpOp0, CmpOp1, CC,
DL));
2341 cast<ConstantSDNode>(Neg.
getOperand(0))->getZExtValue() == 0 &&
2345 Pos.getOperand(0) == CmpOp)));
2367 Comparison
C(
getCmp(DAG, CmpOp0, CmpOp1, CC,
DL));
2376 cast<ConstantSDNode>(
C.Op1)->getZExtValue() == 0) {
2389 if (TrueC && FalseC) {
2391 int64_t FalseVal = FalseC->getSExtValue();
2392 if ((TrueVal == -1 && FalseVal == 0) || (TrueVal == 0 && FalseVal == -1)) {
2395 C.CCMask ^=
C.CCValid;
2427 uint64_t Anchor = Offset & ~uint64_t(0xfff);
2433 if (Offset != 0 && (Offset & 1) == 0) {
2467 Chain = DAG.
getCopyToReg(Chain,
DL, SystemZ::R2D, GOTOffset, Glue);
2484 const uint32_t *Mask =
2486 assert(Mask &&
"Missing call preserved mask for calling convention");
2494 Chain = DAG.
getNode(Opcode,
DL, NodeTys, Ops);
2534 false,
false,
false, 0);
2549 false,
false,
false, 0);
2567 false,
false,
false, 0);
2580 false,
false,
false, 0);
2592 false,
false,
false, 0);
2650 if (
auto *LoadN = dyn_cast<LoadSDNode>(In))
2651 return DAG.
getLoad(ResVT,
DL, LoadN->getChain(), LoadN->getBasePtr(),
2652 LoadN->getMemOperand());
2698 const unsigned NumFields = 4;
2708 unsigned Offset = 0;
2709 for (
unsigned I = 0;
I < NumFields; ++
I) {
2714 MemOps[
I] = DAG.
getStore(Chain,
DL, Fields[
I], FieldAddr,
2727 const Value *DstSV = cast<SrcValueSDNode>(Op.
getOperand(3))->getValue();
2728 const Value *SrcSV = cast<SrcValueSDNode>(Op.
getOperand(4))->getValue();
2737 SDValue SystemZTargetLowering::
2760 SDValue Ops[2] = { Result, Chain };
2797 LL, RL, Ops[1], Ops[0]);
2848 Op0, Op1, Ops[1], Ops[0]);
2875 APInt KnownZero[2], KnownOne[2];
2884 if ((Masks[0] >> 32) == 0xffffffff && uint32_t(Masks[1]) == 0xffffffff)
2886 else if ((Masks[1] >> 32) == 0xffffffff && uint32_t(Masks[0]) == 0xffffffff)
2901 int64_t
Value = int32_t(cast<ConstantSDNode>(LowOp)->getZExtValue());
2911 uint64_t Mask = cast<ConstantSDNode>(HighOp.
getOperand(1))->getZExtValue();
2967 APInt KnownZero, KnownOne;
2969 unsigned NumSignificantBits = (~KnownZero).getActiveBits();
2970 if (NumSignificantBits == 0)
2975 int64_t BitSize = (int64_t)1 <<
Log2_32_Ceil(NumSignificantBits);
2976 BitSize =
std::min(BitSize, OrigBitSize);
2985 for (int64_t I = BitSize / 2; I >= 8; I = I / 2) {
2987 if (BitSize != OrigBitSize)
3004 auto *Node = cast<AtomicSDNode>(Op.
getNode());
3006 Node->getChain(), Node->getBasePtr(),
3007 Node->getMemoryVT(), Node->getMemOperand());
3014 auto *Node = cast<AtomicSDNode>(Op.
getNode());
3016 Node->getBasePtr(), Node->getMemoryVT(),
3017 Node->getMemOperand());
3026 unsigned Opcode)
const {
3027 auto *Node = cast<AtomicSDNode>(Op.
getNode());
3030 EVT NarrowVT = Node->getMemoryVT();
3032 if (NarrowVT == WideVT)
3035 int64_t BitSize = NarrowVT.getSizeInBits();
3036 SDValue ChainIn = Node->getChain();
3037 SDValue Addr = Node->getBasePtr();
3038 SDValue Src2 = Node->getVal();
3045 if (
auto *Const = dyn_cast<ConstantSDNode>(Src2)) {
3080 SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift,
3100 auto *Node = cast<AtomicSDNode>(Op.
getNode());
3101 EVT MemVT = Node->getMemoryVT();
3104 assert(Op.
getValueType() == MemVT &&
"Mismatched VTs");
3105 SDValue Src2 = Node->getVal();
3109 if (
auto *Op2 = dyn_cast<ConstantSDNode>(Src2)) {
3112 int64_t Value = (-Op2->getAPIntValue()).getSExtValue();
3122 Node->getChain(), Node->getBasePtr(), NegSrc2,
3123 Node->getMemOperand(), Node->getOrdering(),
3124 Node->getSynchScope());
3137 auto *Node = cast<AtomicSDNode>(Op.
getNode());
3140 EVT NarrowVT = Node->getMemoryVT();
3142 if (NarrowVT == WideVT)
3145 int64_t BitSize = NarrowVT.getSizeInBits();
3171 SDValue Ops[] = { ChainIn, AlignedAddr, CmpVal, SwapVal, BitShift,
3174 VTList, Ops, NarrowVT, MMO);
3196 bool IsData = cast<ConstantSDNode>(Op.
getOperand(4))->getZExtValue();
3202 bool IsWrite = cast<ConstantSDNode>(Op.
getOperand(2))->getZExtValue();
3204 auto *Node = cast<MemIntrinsicSDNode>(Op.
getNode());
3212 Node->getMemoryVT(), Node->getMemOperand());
3226 SystemZTargetLowering::lowerINTRINSIC_W_CHAIN(
SDValue Op,
3228 unsigned Opcode, CCValid;
3230 assert(Op->
getNumValues() == 2 &&
"Expected only CC result and chain");
3241 SystemZTargetLowering::lowerINTRINSIC_WO_CHAIN(
SDValue Op,
3243 unsigned Opcode, CCValid;
3249 assert(Op->
getNumValues() == 2 &&
"Expected a CC and non-CC result");
3254 unsigned Id = cast<ConstantSDNode>(Op.
getOperand(0))->getZExtValue();
3256 case Intrinsic::s390_vpdi:
3260 case Intrinsic::s390_vperm:
3264 case Intrinsic::s390_vuphb:
3265 case Intrinsic::s390_vuphh:
3266 case Intrinsic::s390_vuphf:
3270 case Intrinsic::s390_vuplhb:
3271 case Intrinsic::s390_vuplhh:
3272 case Intrinsic::s390_vuplhf:
3276 case Intrinsic::s390_vuplb:
3277 case Intrinsic::s390_vuplhw:
3278 case Intrinsic::s390_vuplf:
3282 case Intrinsic::s390_vupllb:
3283 case Intrinsic::s390_vupllh:
3284 case Intrinsic::s390_vupllf:
3288 case Intrinsic::s390_vsumb:
3289 case Intrinsic::s390_vsumh:
3290 case Intrinsic::s390_vsumgh:
3291 case Intrinsic::s390_vsumgf:
3292 case Intrinsic::s390_vsumqf:
3293 case Intrinsic::s390_vsumqg:
3316 { 0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 23 } },
3319 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
3322 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
3325 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
3328 { 8, 9, 10, 11, 12, 13, 14, 15, 24, 25, 26, 27, 28, 29, 30, 31 } },
3331 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },
3334 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
3337 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
3340 { 4, 5, 6, 7, 12, 13, 14, 15, 20, 21, 22, 23, 28, 29, 30, 31 } },
3343 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
3346 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
3349 { 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 } },
3352 { 0, 1, 2, 3, 4, 5, 6, 7, 24, 25, 26, 27, 28, 29, 30, 31 } }
3366 OpNo0 = OpNo1 = OpNos[1];
3367 }
else if (OpNos[1] < 0) {
3368 OpNo0 = OpNo1 = OpNos[0];
3386 unsigned &OpNo0,
unsigned &OpNo1) {
3387 int OpNos[] = { -1, -1 };
3394 if ((Elt ^ P.Bytes[I]) & (SystemZ::VectorBytes - 1))
3400 if (OpNos[ModelOpNo] == 1 - RealOpNo)
3402 OpNos[ModelOpNo] = RealOpNo;
3410 unsigned &OpNo0,
unsigned &OpNo1) {
3411 for (
auto &
P : PermuteForms)
3427 int Elt = Bytes[From];
3430 Transform[From] = -1;
3432 while (P.Bytes[To] != Elt) {
3434 if (To == SystemZ::VectorBytes)
3437 Transform[From] = To;
3446 for (
auto &
P : PermuteForms)
3459 Bytes.
resize(NumElements * BytesPerElement, -1);
3460 for (
unsigned I = 0; I < NumElements; ++
I) {
3463 for (
unsigned J = 0; J < BytesPerElement; ++J)
3464 Bytes[I * BytesPerElement + J] = Index * BytesPerElement + J;
3473 unsigned BytesPerElement,
int &Base) {
3475 for (
unsigned I = 0; I < BytesPerElement; ++
I) {
3476 if (Bytes[Start + I] >= 0) {
3477 unsigned Elem = Bytes[Start +
I];
3481 if (
unsigned(Base) % Bytes.
size() + BytesPerElement > Bytes.
size())
3483 }
else if (
unsigned(Base) != Elem -
I)
3496 unsigned &StartIndex,
unsigned &OpNo0,
3498 int OpNos[] = { -1, -1 };
3500 for (
unsigned I = 0; I < 16; ++
I) {
3501 int Index = Bytes[
I];
3507 Shift = ExpectedShift;
3508 else if (Shift != ExpectedShift)
3512 if (OpNos[ModelOpNo] == 1 - RealOpNo)
3514 OpNos[ModelOpNo] = RealOpNo;
3544 Op = DAG.
getNode(P.Opcode, DL, InVT, Op0, Op1);
3554 for (
unsigned I = 0; I < 2; ++
I)
3558 unsigned StartIndex, OpNo0, OpNo1;
3576 struct GeneralShuffle {
3577 GeneralShuffle(
EVT vt) : VT(vt) {}
3596 void GeneralShuffle::addUndef() {
3598 for (
unsigned I = 0; I < BytesPerElement; ++
I)
3599 Bytes.push_back(-1);
3614 assert(FromBytesPerElement >= BytesPerElement &&
3615 "Invalid EXTRACT_VECTOR_ELT");
3617 (FromBytesPerElement - BytesPerElement));
3646 for (; OpNo < Ops.size(); ++OpNo)
3647 if (Ops[OpNo] == Op)
3649 if (OpNo == Ops.size())
3654 for (
unsigned I = 0; I < BytesPerElement; ++
I)
3655 Bytes.push_back(Base + I);
3662 if (Ops.size() == 0)
3666 if (Ops.size() == 1)
3678 unsigned Stride = 1;
3679 for (; Stride * 2 < Ops.size(); Stride *= 2) {
3680 for (
unsigned I = 0; I < Ops.size() - Stride; I += Stride * 2) {
3681 SDValue SubOps[] = { Ops[
I], Ops[I + Stride] };
3690 else if (OpNo == I + Stride)
3691 NewBytes[J] = SystemZ::VectorBytes + Byte;
3701 if (NewBytes[J] >= 0) {
3702 assert(
unsigned(NewBytesMap[J]) < SystemZ::VectorBytes &&
3703 "Invalid double permute");
3704 Bytes[J] = I * SystemZ::VectorBytes + NewBytesMap[J];
3706 assert(NewBytesMap[J] < 0 &&
"Invalid double permute");
3712 if (NewBytes[J] >= 0)
3713 Bytes[J] = I * SystemZ::VectorBytes + J;
3720 Ops[1] = Ops[Stride];
3722 if (Bytes[I] >=
int(SystemZ::VectorBytes))
3723 Bytes[
I] -= (Stride - 1) * SystemZ::VectorBytes;
3728 unsigned OpNo0, OpNo1;
3807 Value = dyn_cast<ConstantSDNode>(Op)->getZExtValue();
3809 Value = (dyn_cast<ConstantFPSDNode>(Op)->getValueAPF().bitcastToAPInt()
3813 for (
unsigned J = 0; J < BytesPerElement; ++J) {
3814 uint64_t Byte = (Value >> (J * 8)) & 0xff;
3816 Mask |= 1ULL << ((E - I - 1) * BytesPerElement + J);
3833 unsigned BitsPerElement) {
3835 int64_t SignedValue =
SignExtend64(Value, BitsPerElement);
3846 unsigned Start, End;
3847 if (TII->
isRxSBGMask(Value, BitsPerElement, Start, End)) {
3852 Start -= 64 - BitsPerElement;
3853 End -= 64 - BitsPerElement;
3877 GeneralShuffle
GS(VT);
3879 bool FoundOne =
false;
3880 for (
unsigned I = 0; I < NumElements; ++
I) {
3886 unsigned Elem = cast<ConstantSDNode>(Op.
getOperand(1))->getZExtValue();
3902 if (!ResidueOps.
empty()) {
3903 while (ResidueOps.
size() < NumElements)
3905 for (
auto &Op : GS.Ops) {
3912 return GS.getNode(DAG,
SDLoc(BVN));
3920 unsigned int NumElements = Elems.
size();
3921 unsigned int Count = 0;
3922 for (
auto Elem : Elems) {
3926 else if (Elem != Single) {
3951 return joinDwords(DAG, DL, Elems[0], Elems[1]);
3986 unsigned NumConstants = 0;
3987 for (
unsigned I = 0; I < NumElements; ++
I) {
3992 Constants[
I] = Elem;
4000 if (NumConstants > 0) {
4001 for (
unsigned I = 0; I < NumElements; ++
I)
4002 if (!Constants[I].getNode())
4003 Constants[I] = DAG.
getUNDEF(Elems[I].getValueType());
4010 unsigned I1 = NumElements / 2 - 1;
4011 unsigned I2 = NumElements - 1;
4012 bool Def1 = (Elems[I1].getOpcode() !=
ISD::UNDEF);
4013 bool Def2 = (Elems[I2].getOpcode() !=
ISD::UNDEF);
4015 SDValue Elem1 = Elems[Def1 ? I1 : I2];
4016 SDValue Elem2 = Elems[Def2 ? I2 : I1];
4026 for (
unsigned I = 0; I < NumElements; ++
I)
4027 if (!Done[I] && Elems[I].getOpcode() !=
ISD::UNDEF)
4037 auto *BVN = cast<BuildVectorSDNode>(Op.
getNode());
4041 if (BVN->isConstant()) {
4053 APInt SplatBits, SplatUndef;
4054 unsigned SplatBitSize;
4056 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs,
4058 SplatBitSize <= 64) {
4065 uint64_t Lower = (SplatUndefZ
4067 uint64_t Upper = (SplatUndefZ
4068 & ~((uint64_t(1) <<
findLastSet(SplatBitsZ)) - 1));
4069 uint64_t Value = SplatBitsZ | Upper | Lower;
4078 uint64_t Middle = SplatUndefZ & ~Upper & ~Lower;
4079 Value = SplatBitsZ | Middle;
4101 for (
unsigned I = 0; I < NumElements; ++
I)
4108 auto *VSN = cast<ShuffleVectorSDNode>(Op.
getNode());
4113 if (VSN->isSplat()) {
4115 unsigned Index = VSN->getSplatIndex();
4117 "Splat index should be defined and in first operand");
4127 GeneralShuffle
GS(VT);
4128 for (
unsigned I = 0; I < NumElements; ++
I) {
4129 int Elt = VSN->getMaskElt(I);
4136 return GS.getNode(DAG,
SDLoc(VSN));
4148 SDValue SystemZTargetLowering::lowerINSERT_VECTOR_ELT(
SDValue Op,
4180 SystemZTargetLowering::lowerEXTRACT_VECTOR_ELT(
SDValue Op,
4190 if (
auto *CIndexN = dyn_cast<ConstantSDNode>(Op1)) {
4191 uint64_t Index = CIndexN->getZExtValue();
4207 unsigned UnpackHigh)
const {
4217 PackedOp = DAG.
getNode(UnpackHigh,
SDLoc(PackedOp), OutVT, PackedOp);
4218 }
while (FromBits != ToBits);
4223 unsigned ByScalar)
const {
4232 if (
auto *BVN = dyn_cast<BuildVectorSDNode>(Op1)) {
4233 APInt SplatBits, SplatUndef;
4234 unsigned SplatBitSize;
4238 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs,
4239 ElemBitSize,
true) &&
4240 SplatBitSize == ElemBitSize) {
4243 return DAG.
getNode(ByScalar, DL, VT, Op0, Shift);
4247 SDValue Splat = BVN->getSplatValue(&UndefElements);
4252 return DAG.
getNode(ByScalar, DL, VT, Op0, Shift);
4258 if (
auto *VSN = dyn_cast<ShuffleVectorSDNode>(Op1)) {
4259 if (VSN->isSplat()) {
4261 unsigned Index = VSN->getSplatIndex();
4263 "Splat index should be defined and in first operand");
4270 return DAG.
getNode(ByScalar, DL, VT, Op0, Shift);
4283 return lowerBR_CC(Op, DAG);
4285 return lowerSELECT_CC(Op, DAG);
4287 return lowerSETCC(Op, DAG);
4289 return lowerGlobalAddress(cast<GlobalAddressSDNode>(Op), DAG);
4291 return lowerGlobalTLSAddress(cast<GlobalAddressSDNode>(Op), DAG);
4293 return lowerBlockAddress(cast<BlockAddressSDNode>(Op), DAG);
4295 return lowerJumpTable(cast<JumpTableSDNode>(Op), DAG);
4297 return lowerConstantPool(cast<ConstantPoolSDNode>(Op), DAG);
4299 return lowerBITCAST(Op, DAG);
4301 return lowerVASTART(Op, DAG);
4303 return lowerVACOPY(Op, DAG);
4305 return lowerDYNAMIC_STACKALLOC(Op, DAG);
4307 return lowerSMUL_LOHI(Op, DAG);
4309 return lowerUMUL_LOHI(Op, DAG);
4311 return lowerSDIVREM(Op, DAG);
4313 return lowerUDIVREM(Op, DAG);
4315 return lowerOR(Op, DAG);
4317 return lowerCTPOP(Op, DAG);
4327 return lowerATOMIC_STORE(Op, DAG);
4329 return lowerATOMIC_LOAD(Op, DAG);
4333 return lowerATOMIC_LOAD_SUB(Op, DAG);
4351 return lowerATOMIC_CMP_SWAP(Op, DAG);
4353 return lowerSTACKSAVE(Op, DAG);
4355 return lowerSTACKRESTORE(Op, DAG);
4357 return lowerPREFETCH(Op, DAG);
4359 return lowerINTRINSIC_W_CHAIN(Op, DAG);
4361 return lowerINTRINSIC_WO_CHAIN(Op, DAG);
4363 return lowerBUILD_VECTOR(Op, DAG);
4365 return lowerVECTOR_SHUFFLE(Op, DAG);
4367 return lowerSCALAR_TO_VECTOR(Op, DAG);
4369 return lowerINSERT_VECTOR_ELT(Op, DAG);
4371 return lowerEXTRACT_VECTOR_ELT(Op, DAG);
4388 #define OPCODE(NAME) case SystemZISD::NAME: return "SystemZISD::" #NAME
4507 DAGCombinerInfo &DCI,
4528 BytesPerElement, First))
4535 if (Byte % BytesPerElement != 0)
4538 Index = Byte / BytesPerElement;
4547 if (OpBytesPerElement < BytesPerElement)
4551 unsigned End = (Index + 1) * BytesPerElement;
4552 if (End % OpBytesPerElement != 0)
4555 Op = Op.
getOperand(End / OpBytesPerElement - 1);
4559 DCI.AddToWorklist(Op.getNode());
4564 DCI.AddToWorklist(Op.getNode());
4574 EVT ExtVT = Op.getValueType();
4575 EVT OpVT = Op.getOperand(0).getValueType();
4578 unsigned Byte = Index * BytesPerElement;
4579 unsigned SubByte = Byte % ExtBytesPerElement;
4580 unsigned MinSubByte = ExtBytesPerElement - OpBytesPerElement;
4581 if (SubByte < MinSubByte ||
4582 SubByte + BytesPerElement > ExtBytesPerElement)
4585 Byte = Byte / ExtBytesPerElement * OpBytesPerElement;
4587 Byte += SubByte - MinSubByte;
4588 if (Byte % BytesPerElement != 0)
4590 Op = Op.getOperand(0);
4591 Index = Byte / BytesPerElement;
4597 if (Op.getValueType() != VecVT) {
4599 DCI.AddToWorklist(Op.getNode());
4610 SystemZTargetLowering::combineTruncateExtract(
SDLoc DL,
EVT TruncVT,
SDValue Op,
4611 DAGCombinerInfo &DCI)
const {
4620 if (
auto *IndexN = dyn_cast<ConstantSDNode>(Op.
getOperand(1))) {
4623 if (BytesPerElement % TruncBytes == 0) {
4629 unsigned Scale = BytesPerElement / TruncBytes;
4630 unsigned NewIndex = (IndexN->getZExtValue() + 1) * Scale - 1;
4636 EVT ResVT = (TruncBytes < 4 ?
MVT::i32 : TruncVT);
4637 return combineExtract(DL, ResVT, VecVT, Vec, NewIndex, DCI,
true);
4658 if (SraAmt && Inner.hasOneUse() && Inner.getOpcode() ==
ISD::SHL) {
4659 if (
auto *ShlAmt = dyn_cast<ConstantSDNode>(Inner.getOperand(1))) {
4662 unsigned NewShlAmt = ShlAmt->getZExtValue() + Extra;
4663 unsigned NewSraAmt = SraAmt->getZExtValue() + Extra;
4666 Inner.getOperand(0));
4683 cast<ConstantSDNode>(Op0.
getOperand(0))->getZExtValue() == 0) {
4691 if (ElemBytes <= 4) {
4696 SystemZ::VectorBytes / ElemBytes / 2);
4712 auto *SN = cast<StoreSDNode>(
N);
4713 EVT MemVT = SN->getMemoryVT();
4714 if (MemVT.isInteger()) {
4715 SDValue Value = combineTruncateExtract(
SDLoc(N), MemVT,
4716 SN->getValue(), DCI);
4722 SN->getBasePtr(), SN->getMemoryVT(),
4723 SN->getMemOperand());
4729 if (
auto *IndexN = dyn_cast<ConstantSDNode>(N->
getOperand(1))) {
4733 IndexN->getZExtValue(), DCI,
false);
4754 cast<ConstantSDNode>(Op0.
getOperand(1))->getZExtValue() == 0) {
4756 for (
auto *U : Vec->
uses()) {
4760 U->getOperand(0) == Vec &&
4762 cast<ConstantSDNode>(U->getOperand(1))->getZExtValue() == 1) {
4857 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
4872 .addReg(TrueReg).
addMBB(StartMBB)
4886 unsigned StoreOpcode,
unsigned STOCOpcode,
4887 bool Invert)
const {
4907 BuildMI(*MBB, MI, DL, TII->get(STOCOpcode))
4926 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
4935 BuildMI(MBB, DL, TII->get(StoreOpcode))
4951 SystemZTargetLowering::emitAtomicLoadBinary(
MachineInstr *MI,
4955 bool Invert)
const {
4960 bool IsSubWord = (BitSize < 32);
4976 &SystemZ::GR32BitRegClass :
4977 &SystemZ::GR64BitRegClass);
4978 unsigned LOpcode = BitSize <= 32 ? SystemZ::L : SystemZ::LG;
4979 unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
4984 assert(LOpcode && CSOpcode &&
"Displacement out of range");
4989 unsigned NewVal = (BinOpcode || IsSubWord ?
5004 BuildMI(MBB, DL, TII->get(LOpcode), OrigVal)
5018 .addReg(OrigVal).
addMBB(StartMBB)
5021 BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
5026 BuildMI(MBB, DL, TII->get(BinOpcode), Tmp)
5030 BuildMI(MBB, DL, TII->get(SystemZ::XILF), RotatedNewVal)
5031 .addReg(Tmp).
addImm(-1U << (32 - BitSize));
5036 BuildMI(MBB, DL, TII->get(SystemZ::LCGR), Tmp2).addReg(Tmp);
5037 BuildMI(MBB, DL, TII->get(SystemZ::AGHI), RotatedNewVal)
5038 .addReg(Tmp2).
addImm(-1);
5040 }
else if (BinOpcode)
5042 BuildMI(MBB, DL, TII->get(BinOpcode), RotatedNewVal)
5047 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedNewVal)
5051 BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
5053 BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
5055 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5071 SystemZTargetLowering::emitAtomicLoadMinMax(
MachineInstr *MI,
5073 unsigned CompareOpcode,
5074 unsigned KeepOldMask,
5075 unsigned BitSize)
const {
5080 bool IsSubWord = (BitSize < 32);
5095 &SystemZ::GR32BitRegClass :
5096 &SystemZ::GR64BitRegClass);
5097 unsigned LOpcode = BitSize <= 32 ? SystemZ::L : SystemZ::LG;
5098 unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
5103 assert(LOpcode && CSOpcode &&
"Displacement out of range");
5125 BuildMI(MBB, DL, TII->get(LOpcode), OrigVal)
5136 .addReg(OrigVal).
addMBB(StartMBB)
5139 BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
5141 BuildMI(MBB, DL, TII->get(CompareOpcode))
5142 .addReg(RotatedOldVal).
addReg(Src2);
5143 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5153 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedAltVal)
5154 .addReg(RotatedOldVal).
addReg(Src2)
5167 .addReg(RotatedOldVal).
addMBB(LoopMBB)
5170 BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
5172 BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
5174 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5186 SystemZTargetLowering::emitAtomicCmpSwapW(
MachineInstr *MI,
5209 assert(LOpcode && CSOpcode &&
"Displacement out of range");
5232 BuildMI(MBB, DL, TII->get(LOpcode), OrigOldVal)
5252 .addReg(OrigOldVal).
addMBB(StartMBB)
5255 .addReg(OrigCmpVal).
addMBB(StartMBB)
5258 .addReg(OrigSwapVal).
addMBB(StartMBB)
5260 BuildMI(MBB, DL, TII->get(SystemZ::RLL), Dest)
5262 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetryCmpVal)
5264 BuildMI(MBB, DL, TII->get(SystemZ::CR))
5265 .addReg(Dest).
addReg(RetryCmpVal);
5266 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5282 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetrySwapVal)
5284 BuildMI(MBB, DL, TII->get(SystemZ::RLL), StoreVal)
5285 .addReg(RetrySwapVal).
addReg(NegBitShift).
addImm(-BitSize);
5286 BuildMI(MBB, DL, TII->get(CSOpcode), RetryOldVal)
5288 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5304 bool ClearEven,
unsigned SubReg)
const {
5320 BuildMI(*MBB, MI, DL, TII->get(SystemZ::LLILL), Zero64)
5323 .addReg(In128).
addReg(Zero64).
addImm(SystemZ::subreg_h64);
5334 SystemZTargetLowering::emitMemMemWrapper(
MachineInstr *MI,
5336 unsigned Opcode)
const {
5359 uint64_t StartSrcReg =
forceReg(MI, SrcBase, TII);
5360 uint64_t StartDestReg = (HaveSingleBase ? StartSrcReg :
5365 uint64_t ThisDestReg = (HaveSingleBase ? ThisSrcReg :
5368 uint64_t NextDestReg = (HaveSingleBase ? NextSrcReg :
5371 RC = &SystemZ::GR64BitRegClass;
5399 .addReg(StartDestReg).
addMBB(StartMBB)
5401 if (!HaveSingleBase)
5403 .addReg(StartSrcReg).
addMBB(StartMBB)
5406 .addReg(StartCountReg).
addMBB(StartMBB)
5409 BuildMI(MBB, DL, TII->get(SystemZ::PFD))
5412 BuildMI(MBB, DL, TII->get(Opcode))
5416 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5434 BuildMI(MBB, DL, TII->get(SystemZ::LA), NextDestReg)
5436 if (!HaveSingleBase)
5437 BuildMI(MBB, DL, TII->get(SystemZ::LA), NextSrcReg)
5439 BuildMI(MBB, DL, TII->get(SystemZ::AGHI), NextCountReg)
5440 .addReg(ThisCountReg).
addImm(-1);
5441 BuildMI(MBB, DL, TII->get(SystemZ::CGHI))
5442 .addReg(NextCountReg).
addImm(0);
5443 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5455 while (Length > 0) {
5456 uint64_t ThisLength =
std::min(Length, uint64_t(256));
5459 if (!isUInt<12>(DestDisp)) {
5466 if (!isUInt<12>(SrcDisp)) {
5473 BuildMI(*MBB, MI, DL, TII->get(Opcode))
5474 .addOperand(DestBase).
addImm(DestDisp).
addImm(ThisLength)
5476 DestDisp += ThisLength;
5477 SrcDisp += ThisLength;
5478 Length -= ThisLength;
5481 if (EndMBB && Length > 0) {
5483 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5504 SystemZTargetLowering::emitStringWrapper(
MachineInstr *MI,
5506 unsigned Opcode)
const {
5543 .addReg(Start1Reg).
addMBB(StartMBB)
5546 .addReg(Start2Reg).
addMBB(StartMBB)
5549 BuildMI(MBB, DL, TII->get(Opcode))
5552 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5565 SystemZTargetLowering::emitTransactionBegin(
MachineInstr *MI,
5568 bool NoFloat)
const {
5574 MI->
setDesc(TII->get(Opcode));
5579 static const unsigned GPRControlBit[16] = {
5580 0x8000, 0x8000, 0x4000, 0x4000, 0x2000, 0x2000, 0x1000, 0x1000,
5581 0x0800, 0x0800, 0x0400, 0x0400, 0x0200, 0x0200, 0x0100, 0x0100
5583 Control |= GPRControlBit[15];
5585 Control |= GPRControlBit[11];
5589 for (
int I = 0; I < 16; I++) {
5590 if ((Control & GPRControlBit[I]) == 0) {
5597 if (!NoFloat && (Control & 4) != 0) {
5599 for (
int I = 0; I < 32; I++) {
5604 for (
int I = 0; I < 16; I++) {
5617 case SystemZ::Select32Mux:
5618 case SystemZ::Select32:
5619 case SystemZ::SelectF32:
5620 case SystemZ::Select64:
5621 case SystemZ::SelectF64:
5622 case SystemZ::SelectF128:
5623 return emitSelect(MI, MBB);
5625 case SystemZ::CondStore8Mux:
5626 return emitCondStore(MI, MBB, SystemZ::STCMux, 0,
false);
5627 case SystemZ::CondStore8MuxInv:
5628 return emitCondStore(MI, MBB, SystemZ::STCMux, 0,
true);
5629 case SystemZ::CondStore16Mux:
5630 return emitCondStore(MI, MBB, SystemZ::STHMux, 0,
false);
5631 case SystemZ::CondStore16MuxInv:
5632 return emitCondStore(MI, MBB, SystemZ::STHMux, 0,
true);
5633 case SystemZ::CondStore8:
5634 return emitCondStore(MI, MBB, SystemZ::STC, 0,
false);
5635 case SystemZ::CondStore8Inv:
5636 return emitCondStore(MI, MBB, SystemZ::STC, 0,
true);
5637 case SystemZ::CondStore16:
5638 return emitCondStore(MI, MBB, SystemZ::STH, 0,
false);
5639 case SystemZ::CondStore16Inv:
5640 return emitCondStore(MI, MBB, SystemZ::STH, 0,
true);
5641 case SystemZ::CondStore32:
5642 return emitCondStore(MI, MBB,
SystemZ::ST, SystemZ::STOC,
false);
5643 case SystemZ::CondStore32Inv:
5644 return emitCondStore(MI, MBB,
SystemZ::ST, SystemZ::STOC,
true);
5645 case SystemZ::CondStore64:
5646 return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG,
false);
5647 case SystemZ::CondStore64Inv:
5648 return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG,
true);
5649 case SystemZ::CondStoreF32:
5650 return emitCondStore(MI, MBB, SystemZ::STE, 0,
false);
5651 case SystemZ::CondStoreF32Inv:
5652 return emitCondStore(MI, MBB, SystemZ::STE, 0,
true);
5653 case SystemZ::CondStoreF64:
5654 return emitCondStore(MI, MBB, SystemZ::STD, 0,
false);
5655 case SystemZ::CondStoreF64Inv:
5656 return emitCondStore(MI, MBB, SystemZ::STD, 0,
true);
5658 case SystemZ::AEXT128_64:
5659 return emitExt128(MI, MBB,
false, SystemZ::subreg_l64);
5660 case SystemZ::ZEXT128_32:
5661 return emitExt128(MI, MBB,
true, SystemZ::subreg_l32);
5662 case SystemZ::ZEXT128_64:
5663 return emitExt128(MI, MBB,
true, SystemZ::subreg_l64);
5666 return emitAtomicLoadBinary(MI, MBB, 0, 0);
5667 case SystemZ::ATOMIC_SWAP_32:
5668 return emitAtomicLoadBinary(MI, MBB, 0, 32);
5669 case SystemZ::ATOMIC_SWAP_64:
5670 return emitAtomicLoadBinary(MI, MBB, 0, 64);
5672 case SystemZ::ATOMIC_LOADW_AR:
5673 return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 0);
5674 case SystemZ::ATOMIC_LOADW_AFI:
5675 return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 0);
5676 case SystemZ::ATOMIC_LOAD_AR:
5677 return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 32);
5678 case SystemZ::ATOMIC_LOAD_AHI:
5679 return emitAtomicLoadBinary(MI, MBB, SystemZ::AHI, 32);
5680 case SystemZ::ATOMIC_LOAD_AFI:
5681 return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 32);
5682 case SystemZ::ATOMIC_LOAD_AGR:
5683 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGR, 64);
5684 case SystemZ::ATOMIC_LOAD_AGHI:
5685 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGHI, 64);
5686 case SystemZ::ATOMIC_LOAD_AGFI:
5687 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGFI, 64);
5689 case SystemZ::ATOMIC_LOADW_SR:
5690 return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 0);
5691 case SystemZ::ATOMIC_LOAD_SR:
5692 return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 32);
5693 case SystemZ::ATOMIC_LOAD_SGR:
5694 return emitAtomicLoadBinary(MI, MBB, SystemZ::SGR, 64);
5696 case SystemZ::ATOMIC_LOADW_NR:
5697 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0);
5698 case SystemZ::ATOMIC_LOADW_NILH:
5699 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 0);
5700 case SystemZ::ATOMIC_LOAD_NR:
5701 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32);
5702 case SystemZ::ATOMIC_LOAD_NILL:
5703 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 32);
5704 case SystemZ::ATOMIC_LOAD_NILH:
5705 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 32);
5706 case SystemZ::ATOMIC_LOAD_NILF:
5707 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 32);
5708 case SystemZ::ATOMIC_LOAD_NGR:
5709 return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64);
5710 case SystemZ::ATOMIC_LOAD_NILL64:
5711 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL64, 64);
5712 case SystemZ::ATOMIC_LOAD_NILH64:
5713 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH64, 64);
5714 case SystemZ::ATOMIC_LOAD_NIHL64:
5715 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL64, 64);
5716 case SystemZ::ATOMIC_LOAD_NIHH64:
5717 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH64, 64);
5718 case SystemZ::ATOMIC_LOAD_NILF64:
5719 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF64, 64);
5720 case SystemZ::ATOMIC_LOAD_NIHF64:
5721 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF64, 64);
5724 return emitAtomicLoadBinary(MI, MBB,
SystemZ::OR, 0);
5725 case SystemZ::ATOMIC_LOADW_OILH:
5726 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH, 0);
5728 return emitAtomicLoadBinary(MI, MBB,
SystemZ::OR, 32);
5729 case SystemZ::ATOMIC_LOAD_OILL:
5730 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL, 32);
5731 case SystemZ::ATOMIC_LOAD_OILH:
5732 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH, 32);
5733 case SystemZ::ATOMIC_LOAD_OILF:
5734 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF, 32);
5735 case SystemZ::ATOMIC_LOAD_OGR:
5736 return emitAtomicLoadBinary(MI, MBB, SystemZ::OGR, 64);
5737 case SystemZ::ATOMIC_LOAD_OILL64:
5738 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL64, 64);
5739 case SystemZ::ATOMIC_LOAD_OILH64:
5740 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH64, 64);
5741 case SystemZ::ATOMIC_LOAD_OIHL64:
5742 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHL64, 64);
5743 case SystemZ::ATOMIC_LOAD_OIHH64:
5744 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHH64, 64);
5745 case SystemZ::ATOMIC_LOAD_OILF64:
5746 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF64, 64);
5747 case SystemZ::ATOMIC_LOAD_OIHF64:
5748 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHF64, 64);
5750 case SystemZ::ATOMIC_LOADW_XR:
5751 return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 0);
5752 case SystemZ::ATOMIC_LOADW_XILF:
5753 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF, 0);
5754 case SystemZ::ATOMIC_LOAD_XR:
5755 return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 32);
5756 case SystemZ::ATOMIC_LOAD_XILF:
5757 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF, 32);
5758 case SystemZ::ATOMIC_LOAD_XGR:
5759 return emitAtomicLoadBinary(MI, MBB, SystemZ::XGR, 64);
5760 case SystemZ::ATOMIC_LOAD_XILF64:
5761 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF64, 64);
5762 case SystemZ::ATOMIC_LOAD_XIHF64:
5763 return emitAtomicLoadBinary(MI, MBB, SystemZ::XIHF64, 64);
5765 case SystemZ::ATOMIC_LOADW_NRi:
5766 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0,
true);
5767 case SystemZ::ATOMIC_LOADW_NILHi:
5768 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 0,
true);
5769 case SystemZ::ATOMIC_LOAD_NRi:
5770 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32,
true);
5771 case SystemZ::ATOMIC_LOAD_NILLi:
5772 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 32,
true);
5773 case SystemZ::ATOMIC_LOAD_NILHi:
5774 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 32,
true);
5775 case SystemZ::ATOMIC_LOAD_NILFi:
5776 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 32,
true);
5777 case SystemZ::ATOMIC_LOAD_NGRi:
5778 return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64,
true);
5779 case SystemZ::ATOMIC_LOAD_NILL64i:
5780 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL64, 64,
true);
5781 case SystemZ::ATOMIC_LOAD_NILH64i:
5782 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH64, 64,
true);
5783 case SystemZ::ATOMIC_LOAD_NIHL64i:
5784 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL64, 64,
true);
5785 case SystemZ::ATOMIC_LOAD_NIHH64i:
5786 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH64, 64,
true);
5787 case SystemZ::ATOMIC_LOAD_NILF64i:
5788 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF64, 64,
true);
5789 case SystemZ::ATOMIC_LOAD_NIHF64i:
5790 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF64, 64,
true);
5793 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
5795 case SystemZ::ATOMIC_LOAD_MIN_32:
5796 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
5798 case SystemZ::ATOMIC_LOAD_MIN_64:
5799 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
5803 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
5805 case SystemZ::ATOMIC_LOAD_MAX_32:
5806 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
5808 case SystemZ::ATOMIC_LOAD_MAX_64:
5809 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
5813 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
5815 case SystemZ::ATOMIC_LOAD_UMIN_32:
5816 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
5818 case SystemZ::ATOMIC_LOAD_UMIN_64:
5819 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
5823 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
5825 case SystemZ::ATOMIC_LOAD_UMAX_32:
5826 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
5828 case SystemZ::ATOMIC_LOAD_UMAX_64:
5829 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
5833 return emitAtomicCmpSwapW(MI, MBB);
5834 case SystemZ::MVCSequence:
5835 case SystemZ::MVCLoop:
5837 case SystemZ::NCSequence:
5838 case SystemZ::NCLoop:
5840 case SystemZ::OCSequence:
5841 case SystemZ::OCLoop:
5843 case SystemZ::XCSequence:
5844 case SystemZ::XCLoop:
5846 case SystemZ::CLCSequence:
5847 case SystemZ::CLCLoop:
5849 case SystemZ::CLSTLoop:
5850 return emitStringWrapper(MI, MBB, SystemZ::CLST);
5851 case SystemZ::MVSTLoop:
5852 return emitStringWrapper(MI, MBB, SystemZ::MVST);
5853 case SystemZ::SRSTLoop:
5854 return emitStringWrapper(MI, MBB, SystemZ::SRST);
5857 case SystemZ::TBEGIN_nofloat:
5859 case SystemZ::TBEGINC:
5860 return emitTransactionBegin(MI, MBB, SystemZ::TBEGINC,
true);
bool isInt< 32 >(int64_t x)
SDValue getTruncStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT TVT, bool isNonTemporal, bool isVolatile, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes())
static unsigned CCMaskForCondCode(ISD::CondCode CC)
bool isUInt< 8 >(uint64_t x)
const unsigned CCMASK_CMP_GT
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
static unsigned forceReg(MachineInstr *MI, MachineOperand &Base, const SystemZInstrInfo *TII)
static MVT getIntegerVT(unsigned BitWidth)
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...
void push_back(const T &Elt)
unsigned Log2_32_Ceil(uint32_t Value)
Log2_32_Ceil - This function returns the ceil log base 2 of the specified value, 32 if the value is z...
BUILTIN_OP_END - This must be the last enum value in this list.
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
A parsed version of the target data layout string in and methods for querying it. ...
static bool getShuffleInput(const SmallVectorImpl< int > &Bytes, unsigned Start, unsigned BytesPerElement, int &Base)
static SDValue getCCResult(SelectionDAG &DAG, SDNode *After)
SDValue getValue(unsigned R) const
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
static void VerifyVectorTypes(const SmallVectorImpl< ISD::InputArg > &Ins)
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
T findLastSet(T Val, ZeroBehavior ZB=ZB_Max)
Get the index of the last set bit starting from the least significant bit.
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
LLVMContext * getContext() const
unsigned getVarArgsFrameIndex() const
const unsigned GR32Regs[16]
static bool isIntrinsicWithCCAndChain(SDValue Op, unsigned &Opcode, unsigned &CCValid)
SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N)
uint64_t getZExtValue() const
Get zero extended value.
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, SDLoc DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd)...
const int64_t CallFrameSize
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &, EVT) const override
Return the ValueType of the result of SETCC operations.
size_t size() const
size - Get the string size.
static IPMConversion getIPMConversion(unsigned CCValid, unsigned CCMask)
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
BR_CC - Conditional branch.
static const Permute PermuteForms[]
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
LocInfo getLocInfo() const
static MVT getVectorVT(MVT VT, unsigned NumElements)
bool hasOneUse() const
Return true if there is exactly one use of this node.
const unsigned CCMASK_FCMP
const unsigned FP128Regs[16]
bool hasNUsesOfValue(unsigned NUses, unsigned Value) const
Return true if there are exactly NUSES uses of the indicated value.
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
unsigned odd128(bool Is32bit)
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
SDVTList getVTList() const
ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register zero-extension of the low ...
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
static bool isImmHH(uint64_t Val)
static SDValue tryBuildVectorShuffle(SelectionDAG &DAG, BuildVectorSDNode *BVN)
bool isPC32DBLSymbol(const GlobalValue *GV, Reloc::Model RM, CodeModel::Model CM) const
SDValue getMergeValues(ArrayRef< SDValue > Ops, SDLoc dl)
Create a MERGE_VALUES node from the given operands.
const TargetMachine & getTarget() const
static SDValue getAbsolute(SelectionDAG &DAG, SDLoc DL, SDValue Op, bool IsNegative)
unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain...
CallInst - This class represents a function call, abstracting a target machine's calling convention...
void computeKnownBits(SDValue Op, APInt &KnownZero, APInt &KnownOne, unsigned Depth=0) const
Determine which bits of Op are known to be either zero or one and return them in the KnownZero/KnownO...
const GlobalValue * getGlobal() const
bool mayBeEmittedAsTailCall(CallInst *CI) const override
Return true if the target may be able emit the call instruction as a tail call.
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
void addLiveIn(unsigned Reg)
Adds the specified register as a live in.
static bool canUseSiblingCall(const CCState &ArgCCInfo, SmallVectorImpl< CCValAssign > &ArgLocs)
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
bool hasInterlockedAccess1() const
static Comparison getIntrinsicCmp(SelectionDAG &DAG, unsigned Opcode, SDValue Call, unsigned CCValid, uint64_t CC, ISD::CondCode Cond)
unsigned getNumOperands() const
Return the number of values used by this operation.
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
unsigned getNumOperands() const
int64_t getOffset() const
bool isLegalAddImmediate(int64_t Imm) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *fromMBB)
transferSuccessorsAndUpdatePHIs - Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor blocks which refer to fromMBB to refer to this.
const SDValue & getOperand(unsigned Num) const
static void adjustForTestUnderMask(SelectionDAG &DAG, SDLoc DL, Comparison &C)
const unsigned FP32Regs[16]
SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register sign-extension of the low ...
static MachinePointerInfo getConstantPool()
getConstantPool - Return a MachinePointerInfo record that refers to the constant pool.
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags=0)
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, SDLoc DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array...
bool CheckReturn(const SmallVectorImpl< ISD::OutputArg > &ArgsFlags, CCAssignFn Fn)
CheckReturn - Analyze the return values of a function, returning true if the return can be performed ...
void reserve(size_type N)
Value * CallOperandVal
If this is the result output operand or a clobber, this is null, otherwise it is the incoming operand...
LegalizeAction getOperationAction(unsigned Op, EVT VT) const
Return how this operation should be treated: either it is legal, needs to be promoted to a larger siz...
static bool chooseShuffleOpNos(int *OpNos, unsigned &OpNo0, unsigned &OpNo1)
SDValue getConstantPool(const Constant *C, EVT VT, unsigned Align=0, int Offs=0, bool isT=false, unsigned char TargetFlags=0)
std::size_t countLeadingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the most significant bit to the least stopping at the first 1...
static bool shouldSwapCmpOperands(const Comparison &C)
const unsigned CCMASK_ICMP
TargetLowering::ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
unsigned getResNo() const
get the index which selects a specific result in the SDNode
static unsigned getVectorComparison(ISD::CondCode CC, bool IsFP)
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag=true)
Reports a serious error, calling any installed error handler.
This SDNode is used to implement the code generator support for the llvm IR shufflevector instruction...
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
SDValue getMemcpy(SDValue Chain, SDLoc dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
static MachinePointerInfo getFixedStack(int FI, int64_t offset=0)
getFixedStack - Return a MachinePointerInfo record that refers to the the specified FrameIndex...
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
static MachineBasicBlock * splitBlockAfter(MachineInstr *MI, MachineBasicBlock *MBB)
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
COPY - Target-independent register copy.
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
bool isVector() const
isVector - Return true if this is a vector value type.
bool hasLoadStoreOnCond() const
BlockAddress - The address of a basic block.
SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
MachineMemOperand - A description of a memory reference used in the backend.
static bool matchDoublePermute(const SmallVectorImpl< int > &Bytes, const Permute &P, SmallVectorImpl< int > &Transform)
int64_t getOffset() const
const HexagonInstrInfo * TII
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false)
Shift and rotation operations.
static bool isShlDoublePermute(const SmallVectorImpl< int > &Bytes, unsigned &StartIndex, unsigned &OpNo0, unsigned &OpNo1)
static void lowerMUL_LOHI32(SelectionDAG &DAG, SDLoc DL, unsigned Extend, SDValue Op0, SDValue Op1, SDValue &Hi, SDValue &Lo)
virtual bool hasFP(const MachineFunction &MF) const =0
hasFP - Return true if the specified function should have a dedicated frame pointer register...
const unsigned CCMASK_TM_MSB_0
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
void setVarArgsFirstGPR(unsigned GPR)
MachineFunction & getMachineFunction() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
SDValue getTargetGlobalAddress(const GlobalValue *GV, SDLoc DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
static SDValue emitCmp(SelectionDAG &DAG, SDLoc DL, Comparison &C)
Reg
All possible values of the reg field in the ModR/M byte.
static SDValue buildScalarToVector(SelectionDAG &DAG, SDLoc DL, EVT VT, SDValue Value)
EVT getScalarType() const
getScalarType - If this is a vector type, return the element type, otherwise return this...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) For double-word atomic operations: ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi) ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi) These correspond to the atomicrmw instruction.
Number of individual test Apply this number of consecutive mutations to each input exit after the first new interesting input is found the minimized corpus is saved into the first input directory Number of jobs to run If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
static SDValue convertLocVTToValVT(SelectionDAG &DAG, SDLoc DL, CCValAssign &VA, SDValue Chain, SDValue Value)
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
int getMaskElt(unsigned Idx) const
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
SmallVector< ISD::InputArg, 32 > Ins
STACKSAVE - STACKSAVE has one operand, an input chain.
static SDValue lowerVectorSETCC(SelectionDAG &DAG, SDLoc DL, EVT VT, ISD::CondCode CC, SDValue CmpOp0, SDValue CmpOp1)
EVT getVectorElementType() const
getVectorElementType - Given a vector type, return the type of each element.
static bool isScalarToVector(SDValue Op)
SDValue getCALLSEQ_START(SDValue Chain, SDValue Op, SDLoc DL)
Return a new CALLSEQ_START node, which always must have a glue result (to ensure it's not CSE'd)...
unsigned getLocReg() const
static SDValue getGeneralPermuteNode(SelectionDAG &DAG, SDLoc DL, SDValue *Ops, const SmallVectorImpl< int > &Bytes)
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
SDValue getRegisterMask(const uint32_t *RegMask)
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
bool isLegalICmpImmediate(int64_t Imm) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
This contains information for each constraint that we are lowering.
Simple integer binary arithmetic operators.
SDValue getVectorShuffle(EVT VT, SDLoc dl, SDValue N1, SDValue N2, const int *MaskElts)
Return an ISD::VECTOR_SHUFFLE node.
const unsigned CCMASK_TBEGIN
static bool add(uint64_t *dest, const uint64_t *x, const uint64_t *y, unsigned len)
This function adds the integer array x to the integer array Y and places the result in dest...
SmallVector< ISD::OutputArg, 32 > Outs
static SDValue convertValVTToLocVT(SelectionDAG &DAG, SDLoc DL, CCValAssign &VA, SDValue Value)
const unsigned NumArgFPRs
static bool matchPermute(const SmallVectorImpl< int > &Bytes, const Permute &P, unsigned &OpNo0, unsigned &OpNo1)
void incNumLocalDynamicTLSAccesses()
bool isFloatingPointTy() const
isFloatingPointTy - Return true if this is one of the six floating point types
MachineConstantPoolValue * getMachineCPVal() const
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
static mvt_range integer_vector_valuetypes()
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
const unsigned CCMASK_ANY
ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register any-extension of the low la...
const unsigned VectorBits
bool isTruncateFree(Type *, Type *) const override
Return true if it's free to truncate a value of type Ty1 to type Ty2.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
const unsigned CCMASK_CS_NE
const unsigned CCMASK_TM_SOME_0
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
const DataLayout & getDataLayout() const
const unsigned CCMASK_TM_ALL_1
SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
const BasicBlock * getBasicBlock() const
getBasicBlock - Return the LLVM basic block that this instance corresponded to originally.
UNDEF - An undefined node.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
const MachineBasicBlock * getParent() const
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable...
SystemZTargetLowering(const TargetMachine &TM, const SystemZSubtarget &STI)
SDNode * getNode() const
get the SDNode which holds the desired result
IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
static SDValue emitIntrinsicWithChainAndGlue(SelectionDAG &DAG, SDValue Op, unsigned Opcode)
bundle_iterator< MachineInstr, instr_iterator > iterator
A self-contained host- and target-independent arbitrary-precision floating-point software implementat...
unsigned getStoreSize() const
getStoreSize - Return the number of bytes overwritten by a store of the specified value type...
static void adjustForLTGFR(Comparison &C)
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset) const
static SDValue tryBuildVectorReplicate(SelectionDAG &DAG, const SystemZInstrInfo *TII, SDLoc DL, EVT VT, uint64_t Value, unsigned BitsPerElement)
std::size_t countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the least significant bit to the most stopping at the first 1...
bool isMachineConstantPoolEntry() const
CodeModel::Model getCodeModel() const
Returns the code model.
MVT - Machine Value Type.
static void getVPermMask(ShuffleVectorSDNode *VSN, SmallVectorImpl< int > &Bytes)
const unsigned CCMASK_VCMP
const SDValue & getOperand(unsigned i) const
The instances of the Type class are immutable: once they are created, they are never changed...
This is an important class for using LLVM in a threaded context.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
Simple binary floating point operators.
void setTargetDAGCombine(ISD::NodeType NT)
Targets should invoke this method for each target independent node that they want to provide a custom...
static bool isNaturalMemoryOperand(SDValue Op, unsigned ICmpType)
This is an important base class in LLVM.
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE...
bool isVector() const
isVector - Return true if this is a vector value type.
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL...
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, SDLoc DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array...
static std::pair< unsigned, const TargetRegisterClass * > parseRegisterNumber(StringRef Constraint, const TargetRegisterClass *RC, const unsigned *Map)
const Constant * getConstVal() const
const MachineOperand & getOperand(unsigned i) const
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
const unsigned CCMASK_CMP_LE
static void adjustSubwordCmp(SelectionDAG &DAG, SDLoc DL, Comparison &C)
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
INSERT_SUBREG - This instruction takes three operands: a register that has subregisters, a register providing an insert value, and a subregister index.
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
static void adjustForSubtraction(SelectionDAG &DAG, SDLoc DL, Comparison &C)
void AddToWorklist(SDNode *N)
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
static mvt_range fp_valuetypes()
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT)
SDValue getTargetConstant(uint64_t Val, SDLoc DL, EVT VT, bool isOpaque=false)
void setRegSaveFrameIndex(unsigned FI)
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
void setImm(int64_t immVal)
static SDValue getVectorCmp(SelectionDAG &DAG, unsigned Opcode, SDLoc DL, EVT VT, SDValue CmpOp0, SDValue CmpOp1)
unsigned getOpcode() const
const unsigned CCMASK_TM_MSB_1
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
const unsigned CCMASK_CMP_LT
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
static mvt_range vector_valuetypes()
CondCode getSetCCSwappedOperands(CondCode Operation)
getSetCCSwappedOperands - Return the operation corresponding to (Y op X) when given the operation for...
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool Immutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
use_iterator use_begin() const
Provide iteration support to walk over all uses of an SDNode.
SDValue getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes())
Bit counting operators with an undefined result for zero inputs.
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo...
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth=0) const
Return true if 'Op & Mask' is known to be zero.
bool isRxSBGMask(uint64_t Mask, unsigned BitSize, unsigned &Start, unsigned &End) const
unsigned getStackPointerRegisterToSaveRestore() const
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save...
static SDValue expandV4F32ToV2F64(SelectionDAG &DAG, int Start, SDLoc DL, SDValue Op)
EVT - Extended Value Type.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
static bool isImmLH(uint64_t Val)
T findFirstSet(T Val, ZeroBehavior ZB=ZB_Max)
Get the index of the first set bit starting from the least significant bit.
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align, bool *Fast) const override
Determine if the target supports unaligned memory accesses.
MachinePointerInfo - This class contains a discriminated union of information about pointers in memor...
const BlockAddress * getBlockAddress() const
SDValue CreateStackTemporary(EVT VT, unsigned minAlign=1)
Create a stack temporary, suitable for holding the specified value type.
const SystemZInstrInfo * getInstrInfo() const override
const unsigned CCMASK_TM_MIXED_MSB_0
bool allowTruncateForTailCall(Type *, Type *) const override
Return true if a truncation from Ty1 to Ty2 is permitted when deciding whether a call is in tail posi...
void setIsKill(bool Val=true)
bool hasPopulationCount() const
SDValue getTargetConstantPool(const Constant *C, EVT VT, unsigned Align=0, int Offset=0, unsigned char TargetFlags=0)
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned char TargetFlags=0)
static Comparison getCmp(SelectionDAG &DAG, SDValue CmpOp0, SDValue CmpOp1, ISD::CondCode Cond, SDLoc DL)
TokenFactor - This node takes multiple tokens as input and produces a single token result...
const TargetFrameLowering * getFrameLowering() const override
CCState - This class holds information needed while lowering arguments and return values...
TargetLowering::ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
int64_t SignExtend64(uint64_t x)
SignExtend64 - Sign extend B-bit number x to 64-bit int.
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
void setVarArgsFrameIndex(unsigned FI)
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
void setExceptionPointerRegister(unsigned R)
If set to a physical register, this sets the register that receives the exception address on entry to...
const DataLayout * getDataLayout() const
Deprecated in 3.7, will be removed in 3.8.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
SDValue getTargetInsertSubreg(int SRIdx, SDLoc DL, EVT VT, SDValue Operand, SDValue Subreg)
A convenience function for creating TargetInstrInfo::INSERT_SUBREG nodes.
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
const unsigned CCMASK_CMP_EQ
Type * getType() const
All values are typed, get the type of this value.
const unsigned ArgFPRs[NumArgFPRs]
static bool canTreatAsByteVector(EVT VT)
CCValAssign - Represent assignment of one arg/retval to a location.
const unsigned FP64Regs[16]
static bool isSimpleShift(SDValue N, unsigned &ShiftVal)
BRCOND - Conditional branch.
Information about stack frame layout on the target.
static bool tryBuildVectorByteMask(BuildVectorSDNode *BVN, uint64_t &Mask)
const unsigned CCMASK_CMP_O
const unsigned GR128Regs[16]
static SDValue joinDwords(SelectionDAG &DAG, SDLoc DL, SDValue Op0, SDValue Op1)
SDValue getAtomic(unsigned Opcode, SDLoc dl, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Val, const Value *PtrVal, unsigned Alignment, AtomicOrdering Ordering, SynchronizationScope SynchScope)
Gets a node for an atomic op, produces result (if relevant) and chain and takes 2 operands...
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
const unsigned CCMASK_CMP_NE
SDValue prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL, SelectionDAG &DAG) const override
This callback is used to prepare for a volatile or atomic load.
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Represents one node in the SelectionDAG.
CondCode getSetCCInverse(CondCode Operation, bool isInteger)
getSetCCInverse - Return the operation corresponding to !(X op Y), where 'op' is a valid SetCC operat...
const unsigned GR64Regs[16]
static mvt_range integer_valuetypes()
const unsigned CCMASK_TM_MIXED_MSB_1
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Class for arbitrary precision integers.
bool isUInt< 32 >(uint64_t x)
void setExceptionSelectorRegister(unsigned R)
If set to a physical register, this sets the register that receives the exception typeid on entry to ...
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
getCallPreservedMask - Return a mask of call-preserved registers for the given calling convention on ...
const unsigned VectorBytes
iterator_range< use_iterator > uses()
A "pseudo-class" with methods for operating on BUILD_VECTORs.
static SDValue emitSETCC(SelectionDAG &DAG, SDLoc DL, SDValue Glue, unsigned CCValid, unsigned CCMask)
Select(COND, TRUEVAL, FALSEVAL).
void setMinFunctionAlignment(unsigned Align)
Set the target's minimum function alignment (in log2(bytes))
int64_t getSExtValue() const
bool isIntegerTy() const
isIntegerTy - True if this is an instance of IntegerType.
void setVarArgsFirstFPR(unsigned FPR)
static use_iterator use_end()
ZERO_EXTEND - Used for integer types, zeroing the new bits.
static void VerifyVectorType(MVT VT, EVT ArgVT)
static SDValue getPermuteNode(SelectionDAG &DAG, SDLoc DL, const Permute &P, SDValue Op0, SDValue Op1)
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
ANY_EXTEND - Used for integer types. The high bits are undefined.
static void adjustICmpTruncate(SelectionDAG &DAG, SDLoc DL, Comparison &C)
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
const unsigned CCMASK_CMP_GE
static MachineOperand earlyUseOperand(MachineOperand Op)
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
static MachineBasicBlock * splitBlockBefore(MachineInstr *MI, MachineBasicBlock *MBB)
BR_JT - Jumptable branch.
Representation of each machine instruction.
static MachinePointerInfo getGOT()
getGOT - Return a MachinePointerInfo record that refers to a GOT entry.
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the source.
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned char TargetFlags=0)
SmallVector< SDValue, 32 > OutVals
static bool isAbsolute(SDValue CmpOp, SDValue Pos, SDValue Neg)
static void lowerGR128Binary(SelectionDAG &DAG, SDLoc DL, EVT VT, unsigned Extend, unsigned Opcode, SDValue Op0, SDValue Op1, SDValue &Even, SDValue &Odd)
static MachineBasicBlock * emitBlockAfter(MachineBasicBlock *MBB)
Bitwise operators - logical and, logical or, logical xor.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
static bool is32Bit(EVT VT)
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
Fast - This calling convention attempts to make calls as fast as possible (e.g.
unsigned MaxStoresPerMemcpyOptSize
Maximum number of store operations that may be substituted for a call to memcpy, used for functions w...
void setStackPointerRegisterToSaveRestore(unsigned R)
If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
MachineSDNode * getMachineNode(unsigned Opcode, SDLoc dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s), MachineInstr opcode, and operands.
bool isInt< 16 >(int64_t x)
unsigned MaxStoresPerMemcpy
Specify maximum bytes of store instructions per memcpy call.
static unsigned reverseCCMask(unsigned CCMask)
unsigned getRegSaveFrameIndex() const
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
EVT getValueType() const
Return the ValueType of the referenced return value.
static unsigned getTestUnderMaskCond(unsigned BitSize, unsigned CCMask, uint64_t Mask, uint64_t CmpVal, unsigned ICmpType)
SDValue getConstant(uint64_t Val, SDLoc DL, EVT VT, bool isTarget=false, bool isOpaque=false)
TLSModel::Model getTLSModel(const GlobalValue *GV) const
Returns the TLS model which should be used for the given global variable.
SDValue getGLOBAL_OFFSET_TABLE(EVT VT)
Return a GLOBAL_OFFSET_TABLE node. This does not have a useful SDLoc.
unsigned getReg() const
getReg - Returns the register number.
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
void insert(iterator MBBI, MachineBasicBlock *MBB)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
bool isSimple() const
isSimple - Test if the given EVT is simple (as opposed to being extended).
unsigned getAlignment() const
static void adjustZeroCmp(SelectionDAG &DAG, SDLoc DL, Comparison &C)
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
SDValue getTargetExtractSubreg(int SRIdx, SDLoc DL, EVT VT, SDValue Operand)
A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG nodes.
unsigned getPrimitiveSizeInBits() const LLVM_READONLY
getPrimitiveSizeInBits - Return the basic size of this type if it is a primitive type.
LLVM Value Representation.
FMA - Perform a * b + c with no intermediate rounding step.
SDValue getRegister(unsigned Reg, EVT VT)
unsigned even128(bool Is32bit)
bool isFPImmLegal(const APFloat &Imm, EVT VT) const override
Returns true if the target can instruction select the specified FP immediate natively.
unsigned getVarArgsFirstGPR() const
bool isZero() const
Returns true if and only if the float is plus or minus zero.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
SDValue getValueType(EVT)
PREFETCH - This corresponds to a prefetch intrinsic.
static bool isIntrinsicWithCC(SDValue Op, unsigned &Opcode, unsigned &CCValid)
bool isUInt< 16 >(uint64_t x)
unsigned ComputeNumSignBits(SDValue Op, unsigned Depth=0) const
Return the number of times the sign bit of the register is replicated into the other bits...
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
BasicBlockListType::iterator iterator
void ReplaceAllUsesOfValueWith(SDValue From, SDValue To)
Replace any uses of From with To, leaving uses of other values produced by From.Val alone...
static bool isImmLL(uint64_t Val)
Primary interface to the complete machine description for the target machine.
A SystemZ-specific constant pool value.
C - The default llvm calling convention, compatible with C.
StringRef - Represent a constant reference to a string, i.e.
SetCC operator - This evaluates to a true value iff the condition is true.
static SDValue emitIntrinsicWithGlue(SelectionDAG &DAG, SDValue Op, unsigned Opcode)
bool hasFPExtension() const
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
unsigned MaxStoresPerMemsetOptSize
Maximum number of stores operations that may be substituted for the call to memset, used for functions with OptSize attribute.
StringRef slice(size_t Start, size_t End) const
Return a reference to the substring from [Start, End).
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
unsigned getLocMemOffset() const
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
static void adjustForFNeg(Comparison &C)
OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val) This corresponds to "store atomic" instruction.
bool isIdenticalTo(const MachineOperand &Other) const
isIdenticalTo - Return true if this operand is identical to the specified operand.
const unsigned CCMASK_TM_ALL_0
bool SignBitIsZero(SDValue Op, unsigned Depth=0) const
Return true if the sign bit of Op is known to be zero.
TRUNCATE - Completely drop the high bits.
const unsigned CCMASK_TEND
static SDValue buildVector(SelectionDAG &DAG, SDLoc DL, EVT VT, SmallVectorImpl< SDValue > &Elems)
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
Examine constraint string and operand type and determine a weight value.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2, FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR - Perform various unary floating point operations.
void addSuccessor(MachineBasicBlock *succ, uint32_t weight=0)
addSuccessor - Add succ as a successor of this MachineBasicBlock.
const unsigned VR128Regs[32]
Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) This corresponds to "load atomic" instruction.
bool isFMAFasterThanFMulAndFAdd(EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
static SDValue buildMergeScalars(SelectionDAG &DAG, SDLoc DL, EVT VT, SDValue Op0, SDValue Op1)
static unsigned getVectorComparisonOrInvert(ISD::CondCode CC, bool IsFP, bool &Invert)
const SystemZRegisterInfo * getRegisterInfo() const override
SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a scalar value into element 0 of the...
EVT changeVectorElementTypeToInteger() const
changeVectorElementTypeToInteger - Return a vector with the same number of elements as this vector...
const unsigned CCMASK_TM_SOME_1
MVT getSimpleVT() const
getSimpleVT - Return the SimpleValueType held in the specified simple EVT.
SDValue getIntPtrConstant(uint64_t Val, SDLoc DL, bool isTarget=false)
unsigned getVarArgsFirstFPR() const
SDValue getMemIntrinsicNode(unsigned Opcode, SDLoc dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, unsigned Align=0, bool Vol=false, bool ReadMem=true, bool WriteMem=true, unsigned Size=0)
Creates a MemIntrinsicNode that may produce a result and takes a list of operands.
static SystemZConstantPoolValue * Create(const GlobalValue *GV, SystemZCP::SystemZCPModifier Modifier)
const unsigned CCMASK_CMP_UO
uint64_t getZExtValue() const
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
unsigned getVectorNumElements() const
getVectorNumElements - Given a vector type, return the number of elements it contains.
This class is used to represent ISD::LOAD nodes.
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary...
static bool isImmHL(uint64_t Val)