LLVM  3.7.0
AArch64RegisterInfo.cpp
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1 //===- AArch64RegisterInfo.cpp - AArch64 Register Information -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the AArch64 implementation of the TargetRegisterInfo
11 // class.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AArch64RegisterInfo.h"
16 #include "AArch64FrameLowering.h"
17 #include "AArch64InstrInfo.h"
18 #include "AArch64Subtarget.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/Triple.h"
26 #include "llvm/IR/Function.h"
31 
32 using namespace llvm;
33 
34 #define GET_REGINFO_TARGET_DESC
35 #include "AArch64GenRegisterInfo.inc"
36 
37 static cl::opt<bool>
38 ReserveX18("aarch64-reserve-x18", cl::Hidden,
39  cl::desc("Reserve X18, making it unavailable as GPR"));
40 
42  : AArch64GenRegisterInfo(AArch64::LR), TT(TT) {}
43 
44 const MCPhysReg *
46  assert(MF && "Invalid MachineFunction pointer.");
48  // GHC set of callee saved regs is empty as all those regs are
49  // used for passing STG regs around
50  return CSR_AArch64_NoRegs_SaveList;
52  return CSR_AArch64_AllRegs_SaveList;
53  else
54  return CSR_AArch64_AAPCS_SaveList;
55 }
56 
57 const uint32_t *
59  CallingConv::ID CC) const {
60  if (CC == CallingConv::GHC)
61  // This is academic becase all GHC calls are (supposed to be) tail calls
62  return CSR_AArch64_NoRegs_RegMask;
63  if (CC == CallingConv::AnyReg)
64  return CSR_AArch64_AllRegs_RegMask;
65  else
66  return CSR_AArch64_AAPCS_RegMask;
67 }
68 
70  if (TT.isOSDarwin())
71  return CSR_AArch64_TLS_Darwin_RegMask;
72 
73  assert(TT.isOSBinFormatELF() && "only expect Darwin or ELF TLS");
74  return CSR_AArch64_TLS_ELF_RegMask;
75 }
76 
77 const uint32_t *
79  CallingConv::ID CC) const {
80  // This should return a register mask that is the same as that returned by
81  // getCallPreservedMask but that additionally preserves the register used for
82  // the first i64 argument (which must also be the register used to return a
83  // single i64 return value)
84  //
85  // In case that the calling convention does not use the same register for
86  // both, the function should return NULL (does not currently apply)
87  assert(CC != CallingConv::GHC && "should not be GHC calling convention.");
88  return CSR_AArch64_AAPCS_ThisReturn_RegMask;
89 }
90 
93  const AArch64FrameLowering *TFI = getFrameLowering(MF);
94 
95  // FIXME: avoid re-calculating this every time.
96  BitVector Reserved(getNumRegs());
97  Reserved.set(AArch64::SP);
98  Reserved.set(AArch64::XZR);
99  Reserved.set(AArch64::WSP);
100  Reserved.set(AArch64::WZR);
101 
102  if (TFI->hasFP(MF) || TT.isOSDarwin()) {
103  Reserved.set(AArch64::FP);
104  Reserved.set(AArch64::W29);
105  }
106 
107  if (TT.isOSDarwin() || ReserveX18) {
108  Reserved.set(AArch64::X18); // Platform register
109  Reserved.set(AArch64::W18);
110  }
111 
112  if (hasBasePointer(MF)) {
113  Reserved.set(AArch64::X19);
114  Reserved.set(AArch64::W19);
115  }
116 
117  return Reserved;
118 }
119 
121  unsigned Reg) const {
122  const AArch64FrameLowering *TFI = getFrameLowering(MF);
123 
124  switch (Reg) {
125  default:
126  break;
127  case AArch64::SP:
128  case AArch64::XZR:
129  case AArch64::WSP:
130  case AArch64::WZR:
131  return true;
132  case AArch64::X18:
133  case AArch64::W18:
134  return TT.isOSDarwin() || ReserveX18;
135  case AArch64::FP:
136  case AArch64::W29:
137  return TFI->hasFP(MF) || TT.isOSDarwin();
138  case AArch64::W19:
139  case AArch64::X19:
140  return hasBasePointer(MF);
141  }
142 
143  return false;
144 }
145 
146 const TargetRegisterClass *
148  unsigned Kind) const {
149  return &AArch64::GPR64RegClass;
150 }
151 
152 const TargetRegisterClass *
154  if (RC == &AArch64::CCRRegClass)
155  return &AArch64::GPR64RegClass; // Only MSR & MRS copy NZCV.
156  return RC;
157 }
158 
159 unsigned AArch64RegisterInfo::getBaseRegister() const { return AArch64::X19; }
160 
162  const MachineFrameInfo *MFI = MF.getFrameInfo();
163 
164  // In the presence of variable sized objects, if the fixed stack size is
165  // large enough that referencing from the FP won't result in things being
166  // in range relatively often, we can use a base pointer to allow access
167  // from the other direction like the SP normally works.
168  // Furthermore, if both variable sized objects are present, and the
169  // stack needs to be dynamically re-aligned, the base pointer is the only
170  // reliable way to reference the locals.
171  if (MFI->hasVarSizedObjects()) {
172  if (needsStackRealignment(MF))
173  return true;
174  // Conservatively estimate whether the negative offset from the frame
175  // pointer will be sufficient to reach. If a function has a smallish
176  // frame, it's less likely to have lots of spills and callee saved
177  // space, so it's all more likely to be within range of the frame pointer.
178  // If it's wrong, we'll materialize the constant and still get to the
179  // object; it's just suboptimal. Negative offsets use the unscaled
180  // load/store instructions, which have a 9-bit signed immediate.
181  if (MFI->getLocalFrameSize() < 256)
182  return false;
183  return true;
184  }
185 
186  return false;
187 }
188 
190 
191  if (MF.getFunction()->hasFnAttribute("no-realign-stack"))
192  return false;
193 
194  return true;
195 }
196 
197 // FIXME: share this with other backends with identical implementation?
198 bool
200  const MachineFrameInfo *MFI = MF.getFrameInfo();
201  const AArch64FrameLowering *TFI = getFrameLowering(MF);
202  const Function *F = MF.getFunction();
203  unsigned StackAlign = TFI->getStackAlignment();
204  bool requiresRealignment =
205  ((MFI->getMaxAlignment() > StackAlign) ||
208 
209  return requiresRealignment && canRealignStack(MF);
210 }
211 
212 unsigned
214  const AArch64FrameLowering *TFI = getFrameLowering(MF);
215  return TFI->hasFP(MF) ? AArch64::FP : AArch64::SP;
216 }
217 
219  const MachineFunction &MF) const {
220  return true;
221 }
222 
224  const MachineFunction &MF) const {
225  return true;
226 }
227 
228 bool
230  const MachineFrameInfo *MFI = MF.getFrameInfo();
231  // AArch64FrameLowering::resolveFrameIndexReference() can always fall back
232  // to the stack pointer, so only put the emergency spill slot next to the
233  // FP when there's no better way to access it (SP or base pointer).
234  return MFI->hasVarSizedObjects() && !hasBasePointer(MF);
235 }
236 
238  const MachineFunction &MF) const {
239  return true;
240 }
241 
242 bool
244  const MachineFrameInfo *MFI = MF.getFrameInfo();
245  // Only consider eliminating leaf frames.
246  if (MFI->hasCalls() || (MF.getTarget().Options.DisableFramePointerElim(MF) &&
247  MFI->adjustsStack()))
248  return true;
249  return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken();
250 }
251 
252 /// needsFrameBaseReg - Returns true if the instruction's frame index
253 /// reference would be better served by a base register other than FP
254 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
255 /// references it should create new base registers for.
257  int64_t Offset) const {
258  for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i)
259  assert(i < MI->getNumOperands() &&
260  "Instr doesn't have FrameIndex operand!");
261 
262  // It's the load/store FI references that cause issues, as it can be difficult
263  // to materialize the offset if it won't fit in the literal field. Estimate
264  // based on the size of the local frame and some conservative assumptions
265  // about the rest of the stack frame (note, this is pre-regalloc, so
266  // we don't know everything for certain yet) whether this offset is likely
267  // to be out of range of the immediate. Return true if so.
268 
269  // We only generate virtual base registers for loads and stores, so
270  // return false for everything else.
271  if (!MI->mayLoad() && !MI->mayStore())
272  return false;
273 
274  // Without a virtual base register, if the function has variable sized
275  // objects, all fixed-size local references will be via the frame pointer,
276  // Approximate the offset and see if it's legal for the instruction.
277  // Note that the incoming offset is based on the SP value at function entry,
278  // so it'll be negative.
279  MachineFunction &MF = *MI->getParent()->getParent();
280  const AArch64FrameLowering *TFI = getFrameLowering(MF);
281  MachineFrameInfo *MFI = MF.getFrameInfo();
282 
283  // Estimate an offset from the frame pointer.
284  // Conservatively assume all GPR callee-saved registers get pushed.
285  // FP, LR, X19-X28, D8-D15. 64-bits each.
286  int64_t FPOffset = Offset - 16 * 20;
287  // Estimate an offset from the stack pointer.
288  // The incoming offset is relating to the SP at the start of the function,
289  // but when we access the local it'll be relative to the SP after local
290  // allocation, so adjust our SP-relative offset by that allocation size.
291  Offset += MFI->getLocalFrameSize();
292  // Assume that we'll have at least some spill slots allocated.
293  // FIXME: This is a total SWAG number. We should run some statistics
294  // and pick a real one.
295  Offset += 128; // 128 bytes of spill slots
296 
297  // If there is a frame pointer, try using it.
298  // The FP is only available if there is no dynamic realignment. We
299  // don't know for sure yet whether we'll need that, so we guess based
300  // on whether there are any local variables that would trigger it.
301  if (TFI->hasFP(MF) && isFrameOffsetLegal(MI, AArch64::FP, FPOffset))
302  return false;
303 
304  // If we can reference via the stack pointer or base pointer, try that.
305  // FIXME: This (and the code that resolves the references) can be improved
306  // to only disallow SP relative references in the live range of
307  // the VLA(s). In practice, it's unclear how much difference that
308  // would make, but it may be worth doing.
309  if (isFrameOffsetLegal(MI, AArch64::SP, Offset))
310  return false;
311 
312  // The offset likely isn't legal; we want to allocate a virtual base register.
313  return true;
314 }
315 
317  unsigned BaseReg,
318  int64_t Offset) const {
319  assert(Offset <= INT_MAX && "Offset too big to fit in int.");
320  assert(MI && "Unable to get the legal offset for nil instruction.");
321  int SaveOffset = Offset;
322  return isAArch64FrameOffsetLegal(*MI, SaveOffset) & AArch64FrameOffsetIsLegal;
323 }
324 
325 /// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx
326 /// at the beginning of the basic block.
328  unsigned BaseReg,
329  int FrameIdx,
330  int64_t Offset) const {
332  DebugLoc DL; // Defaults to "unknown"
333  if (Ins != MBB->end())
334  DL = Ins->getDebugLoc();
335  const MachineFunction &MF = *MBB->getParent();
336  const AArch64InstrInfo *TII =
337  MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
338  const MCInstrDesc &MCID = TII->get(AArch64::ADDXri);
339  MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
340  MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF));
341  unsigned Shifter = AArch64_AM::getShifterImm(AArch64_AM::LSL, 0);
342 
343  BuildMI(*MBB, Ins, DL, MCID, BaseReg)
344  .addFrameIndex(FrameIdx)
345  .addImm(Offset)
346  .addImm(Shifter);
347 }
348 
350  int64_t Offset) const {
351  int Off = Offset; // ARM doesn't need the general 64-bit offsets
352  unsigned i = 0;
353 
354  while (!MI.getOperand(i).isFI()) {
355  ++i;
356  assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
357  }
358  const MachineFunction *MF = MI.getParent()->getParent();
359  const AArch64InstrInfo *TII =
360  MF->getSubtarget<AArch64Subtarget>().getInstrInfo();
361  bool Done = rewriteAArch64FrameIndex(MI, i, BaseReg, Off, TII);
362  assert(Done && "Unable to resolve frame index!");
363  (void)Done;
364 }
365 
367  int SPAdj, unsigned FIOperandNum,
368  RegScavenger *RS) const {
369  assert(SPAdj == 0 && "Unexpected");
370 
371  MachineInstr &MI = *II;
372  MachineBasicBlock &MBB = *MI.getParent();
373  MachineFunction &MF = *MBB.getParent();
374  const AArch64InstrInfo *TII =
375  MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
376  const AArch64FrameLowering *TFI = getFrameLowering(MF);
377 
378  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
379  unsigned FrameReg;
380  int Offset;
381 
382  // Special handling of dbg_value, stackmap and patchpoint instructions.
383  if (MI.isDebugValue() || MI.getOpcode() == TargetOpcode::STACKMAP ||
385  Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg,
386  /*PreferFP=*/true);
387  Offset += MI.getOperand(FIOperandNum + 1).getImm();
388  MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
389  MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
390  return;
391  }
392 
393  // Modify MI as necessary to handle as much of 'Offset' as possible
394  Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg);
395  if (rewriteAArch64FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII))
396  return;
397 
398  assert((!RS || !RS->isScavengingFrameIndex(FrameIndex)) &&
399  "Emergency spill slot is out of reach");
400 
401  // If we get here, the immediate doesn't fit into the instruction. We folded
402  // as much as possible above. Handle the rest, providing a register that is
403  // SP+LargeImm.
404  unsigned ScratchReg =
405  MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);
406  emitFrameOffset(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, Offset, TII);
407  MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false, true);
408 }
409 
410 namespace llvm {
411 
413  MachineFunction &MF) const {
414  const AArch64FrameLowering *TFI = getFrameLowering(MF);
415 
416  switch (RC->getID()) {
417  default:
418  return 0;
419  case AArch64::GPR32RegClassID:
420  case AArch64::GPR32spRegClassID:
421  case AArch64::GPR32allRegClassID:
422  case AArch64::GPR64spRegClassID:
423  case AArch64::GPR64allRegClassID:
424  case AArch64::GPR64RegClassID:
425  case AArch64::GPR32commonRegClassID:
426  case AArch64::GPR64commonRegClassID:
427  return 32 - 1 // XZR/SP
428  - (TFI->hasFP(MF) || TT.isOSDarwin()) // FP
429  - (TT.isOSDarwin() || ReserveX18) // X18 reserved as platform register
430  - hasBasePointer(MF); // X19
431  case AArch64::FPR8RegClassID:
432  case AArch64::FPR16RegClassID:
433  case AArch64::FPR32RegClassID:
434  case AArch64::FPR64RegClassID:
435  case AArch64::FPR128RegClassID:
436  return 32;
437 
438  case AArch64::DDRegClassID:
439  case AArch64::DDDRegClassID:
440  case AArch64::DDDDRegClassID:
441  case AArch64::QQRegClassID:
442  case AArch64::QQQRegClassID:
443  case AArch64::QQQQRegClassID:
444  return 32;
445 
446  case AArch64::FPR128_loRegClassID:
447  return 16;
448  }
449 }
450 
451 } // namespace llvm
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
BitVector & set()
Definition: BitVector.h:218
bool isReservedReg(const MachineFunction &MF, unsigned Reg) const
Alignment of stack for function (3 bits) stored as log2 of alignment with +1 bias 0 means unaligned (...
Definition: Attributes.h:106
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const override
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
int resolveFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg, bool PreferFP=false) const
static cl::opt< bool > ReserveX18("aarch64-reserve-x18", cl::Hidden, cl::desc("Reserve X18, making it unavailable as GPR"))
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:138
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:579
A Stackmap instruction captures the location of live variables at its position in the instruction str...
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
unsigned getID() const
getID() - Return the register class ID number.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
needsFrameBaseReg - Returns true if the instruction's frame index reference would be better served by...
A debug info location.
Definition: DebugLoc.h:34
F(f)
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
bool hasAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return true if the attribute exists at the given index.
Definition: Attributes.cpp:956
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:172
const uint32_t * getThisReturnPreservedMask(const MachineFunction &MF, CallingConv::ID) const
getThisReturnPreservedMask - Returns a call preserved mask specific to the case that 'returned' is on...
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
int64_t getLocalFrameSize() const
Get the size of the local object blob.
bool canRealignStack(const MachineFunction &MF) const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const HexagonInstrInfo * TII
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:566
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
bool cannotEliminateFrame(const MachineFunction &MF) const
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:271
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
int isAArch64FrameOffsetLegal(const MachineInstr &MI, int &Offset, bool *OutUseUnscaledOp=nullptr, unsigned *OutUnscaledOp=nullptr, int *EmittableOffset=nullptr)
Check if the Offset is a valid frame offset for MI.
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
bool hasBasePointer(const MachineFunction &MF) const
BitVector getReservedRegs(const MachineFunction &MF) const override
int64_t getImm() const
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:267
static unsigned getShifterImm(AArch64_AM::ShiftExtendType ST, unsigned Imm)
getShifterImm - Encode the shift type and amount: imm: 6-bit shift amount shifter: 000 ==> lsl 001 ==...
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:120
bool isDebugValue() const
Definition: MachineInstr.h:748
bundle_iterator< MachineInstr, instr_iterator > iterator
Patchable call instruction - this instruction represents a call to a constant address, followed by a series of NOPs.
void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override
void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, int Offset, const TargetInstrInfo *TII, MachineInstr::MIFlag=MachineInstr::NoFlags, bool SetNZCV=false)
emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg plus Offset.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const AArch64InstrInfo *TII)
rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the FP.
bool needsStackRealignment(const MachineFunction &MF) const override
unsigned getFrameRegister(const MachineFunction &MF) const override
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
const uint32_t * getTLSCallPreservedMask() const
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool isScavengingFrameIndex(int FI) const
Query whether a frame index is a scavenging frame index.
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X or iOS).
Definition: Triple.h:404
bool hasCalls() const
Return true if the current function has any function calls.
bool requiresRegisterScavenging(const MachineFunction &MF) const override
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const MachineInstrBuilder & addFrameIndex(int Idx) const
AttributeSet getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:181
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:238
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const override
Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx at the beginning of the basic ...
Representation of each machine instruction.
Definition: MachineInstr.h:51
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:479
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:217
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
AArch64RegisterInfo(const Triple &TT)
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
const ARM::ArchExtKind Kind
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
bool useFPForScavengingIndex(const MachineFunction &MF) const override
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override