LLVM  3.7.0
MipsISelLowering.cpp
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1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 #include "MipsISelLowering.h"
17 #include "MipsCCState.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsSubtarget.h"
20 #include "MipsTargetMachine.h"
21 #include "MipsTargetObjectFile.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/ADT/StringSwitch.h"
33 #include "llvm/IR/CallingConv.h"
34 #include "llvm/IR/DerivedTypes.h"
35 #include "llvm/IR/GlobalVariable.h"
37 #include "llvm/Support/Debug.h"
40 #include <cctype>
41 
42 using namespace llvm;
43 
44 #define DEBUG_TYPE "mips-lower"
45 
46 STATISTIC(NumTailCalls, "Number of tail calls");
47 
48 static cl::opt<bool>
49 LargeGOT("mxgot", cl::Hidden,
50  cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false));
51 
52 static cl::opt<bool>
53 NoZeroDivCheck("mno-check-zero-division", cl::Hidden,
54  cl::desc("MIPS: Don't trap on integer division by zero."),
55  cl::init(false));
56 
57 static const MCPhysReg Mips64DPRegs[8] = {
58  Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
59  Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
60 };
61 
62 // If I is a shifted mask, set the size (Size) and the first bit of the
63 // mask (Pos), and return true.
64 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
65 static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
66  if (!isShiftedMask_64(I))
67  return false;
68 
69  Size = countPopulation(I);
70  Pos = countTrailingZeros(I);
71  return true;
72 }
73 
76  return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
77 }
78 
79 SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty,
80  SelectionDAG &DAG,
81  unsigned Flag) const {
82  return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag);
83 }
84 
85 SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty,
86  SelectionDAG &DAG,
87  unsigned Flag) const {
88  return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag);
89 }
90 
91 SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty,
92  SelectionDAG &DAG,
93  unsigned Flag) const {
94  return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag);
95 }
96 
97 SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty,
98  SelectionDAG &DAG,
99  unsigned Flag) const {
100  return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag);
101 }
102 
103 SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty,
104  SelectionDAG &DAG,
105  unsigned Flag) const {
106  return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(),
107  N->getOffset(), Flag);
108 }
109 
110 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
111  switch ((MipsISD::NodeType)Opcode) {
112  case MipsISD::FIRST_NUMBER: break;
113  case MipsISD::JmpLink: return "MipsISD::JmpLink";
114  case MipsISD::TailCall: return "MipsISD::TailCall";
115  case MipsISD::Hi: return "MipsISD::Hi";
116  case MipsISD::Lo: return "MipsISD::Lo";
117  case MipsISD::GPRel: return "MipsISD::GPRel";
118  case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer";
119  case MipsISD::Ret: return "MipsISD::Ret";
120  case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN";
121  case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
122  case MipsISD::FPCmp: return "MipsISD::FPCmp";
123  case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T";
124  case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F";
125  case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP";
126  case MipsISD::MFHI: return "MipsISD::MFHI";
127  case MipsISD::MFLO: return "MipsISD::MFLO";
128  case MipsISD::MTLOHI: return "MipsISD::MTLOHI";
129  case MipsISD::Mult: return "MipsISD::Mult";
130  case MipsISD::Multu: return "MipsISD::Multu";
131  case MipsISD::MAdd: return "MipsISD::MAdd";
132  case MipsISD::MAddu: return "MipsISD::MAddu";
133  case MipsISD::MSub: return "MipsISD::MSub";
134  case MipsISD::MSubu: return "MipsISD::MSubu";
135  case MipsISD::DivRem: return "MipsISD::DivRem";
136  case MipsISD::DivRemU: return "MipsISD::DivRemU";
137  case MipsISD::DivRem16: return "MipsISD::DivRem16";
138  case MipsISD::DivRemU16: return "MipsISD::DivRemU16";
139  case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
140  case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
141  case MipsISD::Wrapper: return "MipsISD::Wrapper";
142  case MipsISD::DynAlloc: return "MipsISD::DynAlloc";
143  case MipsISD::Sync: return "MipsISD::Sync";
144  case MipsISD::Ext: return "MipsISD::Ext";
145  case MipsISD::Ins: return "MipsISD::Ins";
146  case MipsISD::LWL: return "MipsISD::LWL";
147  case MipsISD::LWR: return "MipsISD::LWR";
148  case MipsISD::SWL: return "MipsISD::SWL";
149  case MipsISD::SWR: return "MipsISD::SWR";
150  case MipsISD::LDL: return "MipsISD::LDL";
151  case MipsISD::LDR: return "MipsISD::LDR";
152  case MipsISD::SDL: return "MipsISD::SDL";
153  case MipsISD::SDR: return "MipsISD::SDR";
154  case MipsISD::EXTP: return "MipsISD::EXTP";
155  case MipsISD::EXTPDP: return "MipsISD::EXTPDP";
156  case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H";
157  case MipsISD::EXTR_W: return "MipsISD::EXTR_W";
158  case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W";
159  case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W";
160  case MipsISD::SHILO: return "MipsISD::SHILO";
161  case MipsISD::MTHLIP: return "MipsISD::MTHLIP";
162  case MipsISD::MULSAQ_S_W_PH: return "MipsISD::MULSAQ_S_W_PH";
163  case MipsISD::MAQ_S_W_PHL: return "MipsISD::MAQ_S_W_PHL";
164  case MipsISD::MAQ_S_W_PHR: return "MipsISD::MAQ_S_W_PHR";
165  case MipsISD::MAQ_SA_W_PHL: return "MipsISD::MAQ_SA_W_PHL";
166  case MipsISD::MAQ_SA_W_PHR: return "MipsISD::MAQ_SA_W_PHR";
167  case MipsISD::DPAU_H_QBL: return "MipsISD::DPAU_H_QBL";
168  case MipsISD::DPAU_H_QBR: return "MipsISD::DPAU_H_QBR";
169  case MipsISD::DPSU_H_QBL: return "MipsISD::DPSU_H_QBL";
170  case MipsISD::DPSU_H_QBR: return "MipsISD::DPSU_H_QBR";
171  case MipsISD::DPAQ_S_W_PH: return "MipsISD::DPAQ_S_W_PH";
172  case MipsISD::DPSQ_S_W_PH: return "MipsISD::DPSQ_S_W_PH";
173  case MipsISD::DPAQ_SA_L_W: return "MipsISD::DPAQ_SA_L_W";
174  case MipsISD::DPSQ_SA_L_W: return "MipsISD::DPSQ_SA_L_W";
175  case MipsISD::DPA_W_PH: return "MipsISD::DPA_W_PH";
176  case MipsISD::DPS_W_PH: return "MipsISD::DPS_W_PH";
177  case MipsISD::DPAQX_S_W_PH: return "MipsISD::DPAQX_S_W_PH";
178  case MipsISD::DPAQX_SA_W_PH: return "MipsISD::DPAQX_SA_W_PH";
179  case MipsISD::DPAX_W_PH: return "MipsISD::DPAX_W_PH";
180  case MipsISD::DPSX_W_PH: return "MipsISD::DPSX_W_PH";
181  case MipsISD::DPSQX_S_W_PH: return "MipsISD::DPSQX_S_W_PH";
182  case MipsISD::DPSQX_SA_W_PH: return "MipsISD::DPSQX_SA_W_PH";
183  case MipsISD::MULSA_W_PH: return "MipsISD::MULSA_W_PH";
184  case MipsISD::MULT: return "MipsISD::MULT";
185  case MipsISD::MULTU: return "MipsISD::MULTU";
186  case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP";
187  case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP";
188  case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP";
189  case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP";
190  case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP";
191  case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP";
192  case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP";
193  case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP";
194  case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP";
195  case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO";
196  case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO";
197  case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO";
198  case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO";
199  case MipsISD::VCEQ: return "MipsISD::VCEQ";
200  case MipsISD::VCLE_S: return "MipsISD::VCLE_S";
201  case MipsISD::VCLE_U: return "MipsISD::VCLE_U";
202  case MipsISD::VCLT_S: return "MipsISD::VCLT_S";
203  case MipsISD::VCLT_U: return "MipsISD::VCLT_U";
204  case MipsISD::VSMAX: return "MipsISD::VSMAX";
205  case MipsISD::VSMIN: return "MipsISD::VSMIN";
206  case MipsISD::VUMAX: return "MipsISD::VUMAX";
207  case MipsISD::VUMIN: return "MipsISD::VUMIN";
208  case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT";
209  case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT";
210  case MipsISD::VNOR: return "MipsISD::VNOR";
211  case MipsISD::VSHF: return "MipsISD::VSHF";
212  case MipsISD::SHF: return "MipsISD::SHF";
213  case MipsISD::ILVEV: return "MipsISD::ILVEV";
214  case MipsISD::ILVOD: return "MipsISD::ILVOD";
215  case MipsISD::ILVL: return "MipsISD::ILVL";
216  case MipsISD::ILVR: return "MipsISD::ILVR";
217  case MipsISD::PCKEV: return "MipsISD::PCKEV";
218  case MipsISD::PCKOD: return "MipsISD::PCKOD";
219  case MipsISD::INSVE: return "MipsISD::INSVE";
220  }
221  return nullptr;
222 }
223 
225  const MipsSubtarget &STI)
226  : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) {
227  // Mips does not have i1 type, so use i32 for
228  // setcc operations results (slt, sgt, ...).
231  // The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA
232  // does. Integer booleans still use 0 and 1.
233  if (Subtarget.hasMips32r6())
236 
237  // Load extented operations for i1 types must be promoted
238  for (MVT VT : MVT::integer_valuetypes()) {
242  }
243 
244  // MIPS doesn't have extending float->double load/store. Set LoadExtAction
245  // for f32, f16
246  for (MVT VT : MVT::fp_valuetypes()) {
249  }
250 
251  // Set LoadExtAction for f16 vectors to Expand
252  for (MVT VT : MVT::fp_vector_valuetypes()) {
253  MVT F16VT = MVT::getVectorVT(MVT::f16, VT.getVectorNumElements());
254  if (F16VT.isValid())
255  setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand);
256  }
257 
260 
262 
263  // Used by legalize types to correctly generate the setcc result.
264  // Without this, every float setcc comes with a AND/OR with the result,
265  // we don't want this, since the fpcmp result goes to a flag register,
266  // which is used implicitly by brcond and select operations.
268 
269  // Mips Custom Operations
287 
288  if (Subtarget.isGP64bit()) {
301  }
302 
303  if (!Subtarget.isGP64bit()) {
307  }
308 
310  if (Subtarget.isGP64bit())
312 
321 
322  // Operations not directly supported by Mips.
334  if (Subtarget.hasCnMips()) {
337  } else {
340  }
351 
352  if (!Subtarget.hasMips32r2())
354 
355  if (!Subtarget.hasMips64r2())
357 
375 
376  // Lower f16 conversion operations into library calls
381 
383 
388 
389  // Use the default for now
392 
397 
399 
400  if (!Subtarget.hasMips32r2()) {
403  }
404 
405  // MIPS16 lacks MIPS32's clz and clo instructions.
408  if (!Subtarget.hasMips64())
410 
411  if (!Subtarget.hasMips32r2())
413  if (!Subtarget.hasMips64r2())
415 
416  if (Subtarget.isGP64bit()) {
421  }
422 
424 
431 
433 
434  // The arguments on the stack are defined in terms of 4-byte slots on O32
435  // and 8-byte slots on N32/N64.
436  setMinStackArgumentAlignment((ABI.IsN32() || ABI.IsN64()) ? 8 : 4);
437 
438  setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP);
439 
440  setExceptionPointerRegister(ABI.IsN64() ? Mips::A0_64 : Mips::A0);
441  setExceptionSelectorRegister(ABI.IsN64() ? Mips::A1_64 : Mips::A1);
442 
443  MaxStoresPerMemcpy = 16;
444 
445  isMicroMips = Subtarget.inMicroMipsMode();
446 }
447 
449  const MipsSubtarget &STI) {
450  if (STI.inMips16Mode())
451  return llvm::createMips16TargetLowering(TM, STI);
452 
453  return llvm::createMipsSETargetLowering(TM, STI);
454 }
455 
456 // Create a fast isel object.
457 FastISel *
459  const TargetLibraryInfo *libInfo) const {
460  if (!funcInfo.MF->getTarget().Options.EnableFastISel)
461  return TargetLowering::createFastISel(funcInfo, libInfo);
462  return Mips::createFastISel(funcInfo, libInfo);
463 }
464 
466  EVT VT) const {
467  if (!VT.isVector())
468  return MVT::i32;
470 }
471 
474  const MipsSubtarget &Subtarget) {
475  if (DCI.isBeforeLegalizeOps())
476  return SDValue();
477 
478  EVT Ty = N->getValueType(0);
479  unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64;
480  unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64;
481  unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 :
483  SDLoc DL(N);
484 
485  SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue,
486  N->getOperand(0), N->getOperand(1));
487  SDValue InChain = DAG.getEntryNode();
488  SDValue InGlue = DivRem;
489 
490  // insert MFLO
491  if (N->hasAnyUseOfValue(0)) {
492  SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty,
493  InGlue);
494  DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
495  InChain = CopyFromLo.getValue(1);
496  InGlue = CopyFromLo.getValue(2);
497  }
498 
499  // insert MFHI
500  if (N->hasAnyUseOfValue(1)) {
501  SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL,
502  HI, Ty, InGlue);
503  DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
504  }
505 
506  return SDValue();
507 }
508 
510  switch (CC) {
511  default: llvm_unreachable("Unknown fp condition code!");
512  case ISD::SETEQ:
513  case ISD::SETOEQ: return Mips::FCOND_OEQ;
514  case ISD::SETUNE: return Mips::FCOND_UNE;
515  case ISD::SETLT:
516  case ISD::SETOLT: return Mips::FCOND_OLT;
517  case ISD::SETGT:
518  case ISD::SETOGT: return Mips::FCOND_OGT;
519  case ISD::SETLE:
520  case ISD::SETOLE: return Mips::FCOND_OLE;
521  case ISD::SETGE:
522  case ISD::SETOGE: return Mips::FCOND_OGE;
523  case ISD::SETULT: return Mips::FCOND_ULT;
524  case ISD::SETULE: return Mips::FCOND_ULE;
525  case ISD::SETUGT: return Mips::FCOND_UGT;
526  case ISD::SETUGE: return Mips::FCOND_UGE;
527  case ISD::SETUO: return Mips::FCOND_UN;
528  case ISD::SETO: return Mips::FCOND_OR;
529  case ISD::SETNE:
530  case ISD::SETONE: return Mips::FCOND_ONE;
531  case ISD::SETUEQ: return Mips::FCOND_UEQ;
532  }
533 }
534 
535 
536 /// This function returns true if the floating point conditional branches and
537 /// conditional moves which use condition code CC should be inverted.
539  if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
540  return false;
541 
542  assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
543  "Illegal Condition Code");
544 
545  return true;
546 }
547 
548 // Creates and returns an FPCmp node from a setcc node.
549 // Returns Op if setcc is not a floating point comparison.
550 static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) {
551  // must be a SETCC node
552  if (Op.getOpcode() != ISD::SETCC)
553  return Op;
554 
555  SDValue LHS = Op.getOperand(0);
556 
557  if (!LHS.getValueType().isFloatingPoint())
558  return Op;
559 
560  SDValue RHS = Op.getOperand(1);
561  SDLoc DL(Op);
562 
563  // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
564  // node if necessary.
565  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
566 
567  return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS,
568  DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32));
569 }
570 
571 // Creates and returns a CMovFPT/F node.
573  SDValue False, SDLoc DL) {
574  ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2));
575  bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue());
576  SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
577 
578  return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
579  True.getValueType(), True, FCC0, False, Cond);
580 }
581 
584  const MipsSubtarget &Subtarget) {
585  if (DCI.isBeforeLegalizeOps())
586  return SDValue();
587 
588  SDValue SetCC = N->getOperand(0);
589 
590  if ((SetCC.getOpcode() != ISD::SETCC) ||
591  !SetCC.getOperand(0).getValueType().isInteger())
592  return SDValue();
593 
594  SDValue False = N->getOperand(2);
595  EVT FalseTy = False.getValueType();
596 
597  if (!FalseTy.isInteger())
598  return SDValue();
599 
600  ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False);
601 
602  // If the RHS (False) is 0, we swap the order of the operands
603  // of ISD::SELECT (obviously also inverting the condition) so that we can
604  // take advantage of conditional moves using the $0 register.
605  // Example:
606  // return (a != 0) ? x : 0;
607  // load $reg, x
608  // movz $reg, $0, a
609  if (!FalseC)
610  return SDValue();
611 
612  const SDLoc DL(N);
613 
614  if (!FalseC->getZExtValue()) {
615  ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
616  SDValue True = N->getOperand(1);
617 
618  SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
619  SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
620 
621  return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
622  }
623 
624  // If both operands are integer constants there's a possibility that we
625  // can do some interesting optimizations.
626  SDValue True = N->getOperand(1);
627  ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True);
628 
629  if (!TrueC || !True.getValueType().isInteger())
630  return SDValue();
631 
632  // We'll also ignore MVT::i64 operands as this optimizations proves
633  // to be ineffective because of the required sign extensions as the result
634  // of a SETCC operator is always MVT::i32 for non-vector types.
635  if (True.getValueType() == MVT::i64)
636  return SDValue();
637 
638  int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue();
639 
640  // 1) (a < x) ? y : y-1
641  // slti $reg1, a, x
642  // addiu $reg2, $reg1, y-1
643  if (Diff == 1)
644  return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False);
645 
646  // 2) (a < x) ? y-1 : y
647  // slti $reg1, a, x
648  // xor $reg1, $reg1, 1
649  // addiu $reg2, $reg1, y-1
650  if (Diff == -1) {
651  ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
652  SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
653  SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
654  return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True);
655  }
656 
657  // Couldn't optimize.
658  return SDValue();
659 }
660 
663  const MipsSubtarget &Subtarget) {
664  if (DCI.isBeforeLegalizeOps())
665  return SDValue();
666 
667  SDValue ValueIfTrue = N->getOperand(0), ValueIfFalse = N->getOperand(2);
668 
669  ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(ValueIfFalse);
670  if (!FalseC || FalseC->getZExtValue())
671  return SDValue();
672 
673  // Since RHS (False) is 0, we swap the order of the True/False operands
674  // (obviously also inverting the condition) so that we can
675  // take advantage of conditional moves using the $0 register.
676  // Example:
677  // return (a != 0) ? x : 0;
678  // load $reg, x
679  // movz $reg, $0, a
680  unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? MipsISD::CMovFP_F :
682 
683  SDValue FCC = N->getOperand(1), Glue = N->getOperand(3);
684  return DAG.getNode(Opc, SDLoc(N), ValueIfFalse.getValueType(),
685  ValueIfFalse, FCC, ValueIfTrue, Glue);
686 }
687 
690  const MipsSubtarget &Subtarget) {
691  // Pattern match EXT.
692  // $dst = and ((sra or srl) $src , pos), (2**size - 1)
693  // => ext $dst, $src, size, pos
694  if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert())
695  return SDValue();
696 
697  SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1);
698  unsigned ShiftRightOpc = ShiftRight.getOpcode();
699 
700  // Op's first operand must be a shift right.
701  if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
702  return SDValue();
703 
704  // The second operand of the shift must be an immediate.
705  ConstantSDNode *CN;
706  if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1))))
707  return SDValue();
708 
709  uint64_t Pos = CN->getZExtValue();
710  uint64_t SMPos, SMSize;
711 
712  // Op's second operand must be a shifted mask.
713  if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
714  !isShiftedMask(CN->getZExtValue(), SMPos, SMSize))
715  return SDValue();
716 
717  // Return if the shifted mask does not start at bit 0 or the sum of its size
718  // and Pos exceeds the word's size.
719  EVT ValTy = N->getValueType(0);
720  if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits())
721  return SDValue();
722 
723  SDLoc DL(N);
724  return DAG.getNode(MipsISD::Ext, DL, ValTy,
725  ShiftRight.getOperand(0),
726  DAG.getConstant(Pos, DL, MVT::i32),
727  DAG.getConstant(SMSize, DL, MVT::i32));
728 }
729 
732  const MipsSubtarget &Subtarget) {
733  // Pattern match INS.
734  // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
735  // where mask1 = (2**size - 1) << pos, mask0 = ~mask1
736  // => ins $dst, $src, size, pos, $src1
737  if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert())
738  return SDValue();
739 
740  SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
741  uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
742  ConstantSDNode *CN;
743 
744  // See if Op's first operand matches (and $src1 , mask0).
745  if (And0.getOpcode() != ISD::AND)
746  return SDValue();
747 
748  if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
749  !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
750  return SDValue();
751 
752  // See if Op's second operand matches (and (shl $src, pos), mask1).
753  if (And1.getOpcode() != ISD::AND)
754  return SDValue();
755 
756  if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
757  !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
758  return SDValue();
759 
760  // The shift masks must have the same position and size.
761  if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
762  return SDValue();
763 
764  SDValue Shl = And1.getOperand(0);
765  if (Shl.getOpcode() != ISD::SHL)
766  return SDValue();
767 
768  if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
769  return SDValue();
770 
771  unsigned Shamt = CN->getZExtValue();
772 
773  // Return if the shift amount and the first bit position of mask are not the
774  // same.
775  EVT ValTy = N->getValueType(0);
776  if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
777  return SDValue();
778 
779  SDLoc DL(N);
780  return DAG.getNode(MipsISD::Ins, DL, ValTy, Shl.getOperand(0),
781  DAG.getConstant(SMPos0, DL, MVT::i32),
782  DAG.getConstant(SMSize0, DL, MVT::i32),
783  And0.getOperand(0));
784 }
785 
788  const MipsSubtarget &Subtarget) {
789  // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
790 
791  if (DCI.isBeforeLegalizeOps())
792  return SDValue();
793 
794  SDValue Add = N->getOperand(1);
795 
796  if (Add.getOpcode() != ISD::ADD)
797  return SDValue();
798 
799  SDValue Lo = Add.getOperand(1);
800 
801  if ((Lo.getOpcode() != MipsISD::Lo) ||
803  return SDValue();
804 
805  EVT ValTy = N->getValueType(0);
806  SDLoc DL(N);
807 
808  SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
809  Add.getOperand(0));
810  return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
811 }
812 
814  const {
815  SelectionDAG &DAG = DCI.DAG;
816  unsigned Opc = N->getOpcode();
817 
818  switch (Opc) {
819  default: break;
820  case ISD::SDIVREM:
821  case ISD::UDIVREM:
822  return performDivRemCombine(N, DAG, DCI, Subtarget);
823  case ISD::SELECT:
824  return performSELECTCombine(N, DAG, DCI, Subtarget);
825  case MipsISD::CMovFP_F:
826  case MipsISD::CMovFP_T:
827  return performCMovFPCombine(N, DAG, DCI, Subtarget);
828  case ISD::AND:
829  return performANDCombine(N, DAG, DCI, Subtarget);
830  case ISD::OR:
831  return performORCombine(N, DAG, DCI, Subtarget);
832  case ISD::ADD:
833  return performADDCombine(N, DAG, DCI, Subtarget);
834  }
835 
836  return SDValue();
837 }
838 
839 void
841  SmallVectorImpl<SDValue> &Results,
842  SelectionDAG &DAG) const {
843  SDValue Res = LowerOperation(SDValue(N, 0), DAG);
844 
845  for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
846  Results.push_back(Res.getValue(I));
847 }
848 
849 void
851  SmallVectorImpl<SDValue> &Results,
852  SelectionDAG &DAG) const {
853  return LowerOperationWrapper(N, Results, DAG);
854 }
855 
858 {
859  switch (Op.getOpcode())
860  {
861  case ISD::BR_JT: return lowerBR_JT(Op, DAG);
862  case ISD::BRCOND: return lowerBRCOND(Op, DAG);
863  case ISD::ConstantPool: return lowerConstantPool(Op, DAG);
864  case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG);
865  case ISD::BlockAddress: return lowerBlockAddress(Op, DAG);
866  case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG);
867  case ISD::JumpTable: return lowerJumpTable(Op, DAG);
868  case ISD::SELECT: return lowerSELECT(Op, DAG);
869  case ISD::SELECT_CC: return lowerSELECT_CC(Op, DAG);
870  case ISD::SETCC: return lowerSETCC(Op, DAG);
871  case ISD::VASTART: return lowerVASTART(Op, DAG);
872  case ISD::VAARG: return lowerVAARG(Op, DAG);
873  case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG);
874  case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG);
875  case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG);
876  case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG);
877  case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG);
878  case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG);
879  case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true);
880  case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false);
881  case ISD::LOAD: return lowerLOAD(Op, DAG);
882  case ISD::STORE: return lowerSTORE(Op, DAG);
883  case ISD::ADD: return lowerADD(Op, DAG);
884  case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG);
885  }
886  return SDValue();
887 }
888 
889 //===----------------------------------------------------------------------===//
890 // Lower helper functions
891 //===----------------------------------------------------------------------===//
892 
893 // addLiveIn - This helper function adds the specified physical register to the
894 // MachineFunction as a live in value. It also creates a corresponding
895 // virtual register for it.
896 static unsigned
897 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
898 {
899  unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
900  MF.getRegInfo().addLiveIn(PReg, VReg);
901  return VReg;
902 }
903 
905  MachineBasicBlock &MBB,
906  const TargetInstrInfo &TII,
907  bool Is64Bit) {
908  if (NoZeroDivCheck)
909  return &MBB;
910 
911  // Insert instruction "teq $divisor_reg, $zero, 7".
914  MachineOperand &Divisor = MI->getOperand(2);
915  MIB = BuildMI(MBB, std::next(I), MI->getDebugLoc(), TII.get(Mips::TEQ))
916  .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill()))
917  .addReg(Mips::ZERO).addImm(7);
918 
919  // Use the 32-bit sub-register if this is a 64-bit division.
920  if (Is64Bit)
921  MIB->getOperand(0).setSubReg(Mips::sub_32);
922 
923  // Clear Divisor's kill flag.
924  Divisor.setIsKill(false);
925 
926  // We would normally delete the original instruction here but in this case
927  // we only needed to inject an additional instruction rather than replace it.
928 
929  return &MBB;
930 }
931 
934  MachineBasicBlock *BB) const {
935  switch (MI->getOpcode()) {
936  default:
937  llvm_unreachable("Unexpected instr type to insert");
938  case Mips::ATOMIC_LOAD_ADD_I8:
939  return emitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
940  case Mips::ATOMIC_LOAD_ADD_I16:
941  return emitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
942  case Mips::ATOMIC_LOAD_ADD_I32:
943  return emitAtomicBinary(MI, BB, 4, Mips::ADDu);
944  case Mips::ATOMIC_LOAD_ADD_I64:
945  return emitAtomicBinary(MI, BB, 8, Mips::DADDu);
946 
947  case Mips::ATOMIC_LOAD_AND_I8:
948  return emitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
949  case Mips::ATOMIC_LOAD_AND_I16:
950  return emitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
951  case Mips::ATOMIC_LOAD_AND_I32:
952  return emitAtomicBinary(MI, BB, 4, Mips::AND);
953  case Mips::ATOMIC_LOAD_AND_I64:
954  return emitAtomicBinary(MI, BB, 8, Mips::AND64);
955 
956  case Mips::ATOMIC_LOAD_OR_I8:
957  return emitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
958  case Mips::ATOMIC_LOAD_OR_I16:
959  return emitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
960  case Mips::ATOMIC_LOAD_OR_I32:
961  return emitAtomicBinary(MI, BB, 4, Mips::OR);
962  case Mips::ATOMIC_LOAD_OR_I64:
963  return emitAtomicBinary(MI, BB, 8, Mips::OR64);
964 
965  case Mips::ATOMIC_LOAD_XOR_I8:
966  return emitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
967  case Mips::ATOMIC_LOAD_XOR_I16:
968  return emitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
969  case Mips::ATOMIC_LOAD_XOR_I32:
970  return emitAtomicBinary(MI, BB, 4, Mips::XOR);
971  case Mips::ATOMIC_LOAD_XOR_I64:
972  return emitAtomicBinary(MI, BB, 8, Mips::XOR64);
973 
974  case Mips::ATOMIC_LOAD_NAND_I8:
975  return emitAtomicBinaryPartword(MI, BB, 1, 0, true);
976  case Mips::ATOMIC_LOAD_NAND_I16:
977  return emitAtomicBinaryPartword(MI, BB, 2, 0, true);
978  case Mips::ATOMIC_LOAD_NAND_I32:
979  return emitAtomicBinary(MI, BB, 4, 0, true);
980  case Mips::ATOMIC_LOAD_NAND_I64:
981  return emitAtomicBinary(MI, BB, 8, 0, true);
982 
983  case Mips::ATOMIC_LOAD_SUB_I8:
984  return emitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
985  case Mips::ATOMIC_LOAD_SUB_I16:
986  return emitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
987  case Mips::ATOMIC_LOAD_SUB_I32:
988  return emitAtomicBinary(MI, BB, 4, Mips::SUBu);
989  case Mips::ATOMIC_LOAD_SUB_I64:
990  return emitAtomicBinary(MI, BB, 8, Mips::DSUBu);
991 
992  case Mips::ATOMIC_SWAP_I8:
993  return emitAtomicBinaryPartword(MI, BB, 1, 0);
994  case Mips::ATOMIC_SWAP_I16:
995  return emitAtomicBinaryPartword(MI, BB, 2, 0);
996  case Mips::ATOMIC_SWAP_I32:
997  return emitAtomicBinary(MI, BB, 4, 0);
998  case Mips::ATOMIC_SWAP_I64:
999  return emitAtomicBinary(MI, BB, 8, 0);
1000 
1001  case Mips::ATOMIC_CMP_SWAP_I8:
1002  return emitAtomicCmpSwapPartword(MI, BB, 1);
1003  case Mips::ATOMIC_CMP_SWAP_I16:
1004  return emitAtomicCmpSwapPartword(MI, BB, 2);
1005  case Mips::ATOMIC_CMP_SWAP_I32:
1006  return emitAtomicCmpSwap(MI, BB, 4);
1007  case Mips::ATOMIC_CMP_SWAP_I64:
1008  return emitAtomicCmpSwap(MI, BB, 8);
1009  case Mips::PseudoSDIV:
1010  case Mips::PseudoUDIV:
1011  case Mips::DIV:
1012  case Mips::DIVU:
1013  case Mips::MOD:
1014  case Mips::MODU:
1015  return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false);
1016  case Mips::PseudoDSDIV:
1017  case Mips::PseudoDUDIV:
1018  case Mips::DDIV:
1019  case Mips::DDIVU:
1020  case Mips::DMOD:
1021  case Mips::DMODU:
1022  return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true);
1023  case Mips::SEL_D:
1024  return emitSEL_D(MI, BB);
1025 
1026  case Mips::PseudoSELECT_I:
1027  case Mips::PseudoSELECT_I64:
1028  case Mips::PseudoSELECT_S:
1029  case Mips::PseudoSELECT_D32:
1030  case Mips::PseudoSELECT_D64:
1031  return emitPseudoSELECT(MI, BB, false, Mips::BNE);
1032  case Mips::PseudoSELECTFP_F_I:
1033  case Mips::PseudoSELECTFP_F_I64:
1034  case Mips::PseudoSELECTFP_F_S:
1035  case Mips::PseudoSELECTFP_F_D32:
1036  case Mips::PseudoSELECTFP_F_D64:
1037  return emitPseudoSELECT(MI, BB, true, Mips::BC1F);
1038  case Mips::PseudoSELECTFP_T_I:
1039  case Mips::PseudoSELECTFP_T_I64:
1040  case Mips::PseudoSELECTFP_T_S:
1041  case Mips::PseudoSELECTFP_T_D32:
1042  case Mips::PseudoSELECTFP_T_D64:
1043  return emitPseudoSELECT(MI, BB, true, Mips::BC1T);
1044  }
1045 }
1046 
1047 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
1048 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
1050 MipsTargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
1051  unsigned Size, unsigned BinOpcode,
1052  bool Nand) const {
1053  assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary.");
1054 
1055  MachineFunction *MF = BB->getParent();
1056  MachineRegisterInfo &RegInfo = MF->getRegInfo();
1057  const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1059  DebugLoc DL = MI->getDebugLoc();
1060  unsigned LL, SC, AND, NOR, ZERO, BEQ;
1061 
1062  if (Size == 4) {
1063  if (isMicroMips) {
1064  LL = Mips::LL_MM;
1065  SC = Mips::SC_MM;
1066  } else {
1067  LL = Subtarget.hasMips32r6() ? Mips::LL_R6 : Mips::LL;
1068  SC = Subtarget.hasMips32r6() ? Mips::SC_R6 : Mips::SC;
1069  }
1070  AND = Mips::AND;
1071  NOR = Mips::NOR;
1072  ZERO = Mips::ZERO;
1073  BEQ = Mips::BEQ;
1074  } else {
1075  LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD;
1076  SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD;
1077  AND = Mips::AND64;
1078  NOR = Mips::NOR64;
1079  ZERO = Mips::ZERO_64;
1080  BEQ = Mips::BEQ64;
1081  }
1082 
1083  unsigned OldVal = MI->getOperand(0).getReg();
1084  unsigned Ptr = MI->getOperand(1).getReg();
1085  unsigned Incr = MI->getOperand(2).getReg();
1086 
1087  unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1088  unsigned AndRes = RegInfo.createVirtualRegister(RC);
1089  unsigned Success = RegInfo.createVirtualRegister(RC);
1090 
1091  // insert new blocks after the current block
1092  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1093  MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1094  MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1095  MachineFunction::iterator It = BB;
1096  ++It;
1097  MF->insert(It, loopMBB);
1098  MF->insert(It, exitMBB);
1099 
1100  // Transfer the remainder of BB and its successor edges to exitMBB.
1101  exitMBB->splice(exitMBB->begin(), BB,
1102  std::next(MachineBasicBlock::iterator(MI)), BB->end());
1103  exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1104 
1105  // thisMBB:
1106  // ...
1107  // fallthrough --> loopMBB
1108  BB->addSuccessor(loopMBB);
1109  loopMBB->addSuccessor(loopMBB);
1110  loopMBB->addSuccessor(exitMBB);
1111 
1112  // loopMBB:
1113  // ll oldval, 0(ptr)
1114  // <binop> storeval, oldval, incr
1115  // sc success, storeval, 0(ptr)
1116  // beq success, $0, loopMBB
1117  BB = loopMBB;
1118  BuildMI(BB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
1119  if (Nand) {
1120  // and andres, oldval, incr
1121  // nor storeval, $0, andres
1122  BuildMI(BB, DL, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr);
1123  BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes);
1124  } else if (BinOpcode) {
1125  // <binop> storeval, oldval, incr
1126  BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr);
1127  } else {
1128  StoreVal = Incr;
1129  }
1130  BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0);
1131  BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB);
1132 
1133  MI->eraseFromParent(); // The instruction is gone now.
1134 
1135  return exitMBB;
1136 }
1137 
1138 MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg(
1139  MachineInstr *MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg,
1140  unsigned SrcReg) const {
1141  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1142  DebugLoc DL = MI->getDebugLoc();
1143 
1144  if (Subtarget.hasMips32r2() && Size == 1) {
1145  BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg);
1146  return BB;
1147  }
1148 
1149  if (Subtarget.hasMips32r2() && Size == 2) {
1150  BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg);
1151  return BB;
1152  }
1153 
1154  MachineFunction *MF = BB->getParent();
1155  MachineRegisterInfo &RegInfo = MF->getRegInfo();
1157  unsigned ScrReg = RegInfo.createVirtualRegister(RC);
1158 
1159  assert(Size < 32);
1160  int64_t ShiftImm = 32 - (Size * 8);
1161 
1162  BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm);
1163  BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm);
1164 
1165  return BB;
1166 }
1167 
1168 MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword(
1169  MachineInstr *MI, MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
1170  bool Nand) const {
1171  assert((Size == 1 || Size == 2) &&
1172  "Unsupported size for EmitAtomicBinaryPartial.");
1173 
1174  MachineFunction *MF = BB->getParent();
1175  MachineRegisterInfo &RegInfo = MF->getRegInfo();
1177  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1178  DebugLoc DL = MI->getDebugLoc();
1179 
1180  unsigned Dest = MI->getOperand(0).getReg();
1181  unsigned Ptr = MI->getOperand(1).getReg();
1182  unsigned Incr = MI->getOperand(2).getReg();
1183 
1184  unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1185  unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1186  unsigned Mask = RegInfo.createVirtualRegister(RC);
1187  unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1188  unsigned NewVal = RegInfo.createVirtualRegister(RC);
1189  unsigned OldVal = RegInfo.createVirtualRegister(RC);
1190  unsigned Incr2 = RegInfo.createVirtualRegister(RC);
1191  unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1192  unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1193  unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1194  unsigned AndRes = RegInfo.createVirtualRegister(RC);
1195  unsigned BinOpRes = RegInfo.createVirtualRegister(RC);
1196  unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1197  unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1198  unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1199  unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1200  unsigned Success = RegInfo.createVirtualRegister(RC);
1201 
1202  // insert new blocks after the current block
1203  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1204  MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1205  MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1206  MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1207  MachineFunction::iterator It = BB;
1208  ++It;
1209  MF->insert(It, loopMBB);
1210  MF->insert(It, sinkMBB);
1211  MF->insert(It, exitMBB);
1212 
1213  // Transfer the remainder of BB and its successor edges to exitMBB.
1214  exitMBB->splice(exitMBB->begin(), BB,
1215  std::next(MachineBasicBlock::iterator(MI)), BB->end());
1216  exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1217 
1218  BB->addSuccessor(loopMBB);
1219  loopMBB->addSuccessor(loopMBB);
1220  loopMBB->addSuccessor(sinkMBB);
1221  sinkMBB->addSuccessor(exitMBB);
1222 
1223  // thisMBB:
1224  // addiu masklsb2,$0,-4 # 0xfffffffc
1225  // and alignedaddr,ptr,masklsb2
1226  // andi ptrlsb2,ptr,3
1227  // sll shiftamt,ptrlsb2,3
1228  // ori maskupper,$0,255 # 0xff
1229  // sll mask,maskupper,shiftamt
1230  // nor mask2,$0,mask
1231  // sll incr2,incr,shiftamt
1232 
1233  int64_t MaskImm = (Size == 1) ? 255 : 65535;
1234  BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
1235  .addReg(Mips::ZERO).addImm(-4);
1236  BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
1237  .addReg(Ptr).addReg(MaskLSB2);
1238  BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1239  if (Subtarget.isLittle()) {
1240  BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1241  } else {
1242  unsigned Off = RegInfo.createVirtualRegister(RC);
1243  BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1244  .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1245  BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1246  }
1247  BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1248  .addReg(Mips::ZERO).addImm(MaskImm);
1249  BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1250  .addReg(MaskUpper).addReg(ShiftAmt);
1251  BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1252  BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt);
1253 
1254  // atomic.load.binop
1255  // loopMBB:
1256  // ll oldval,0(alignedaddr)
1257  // binop binopres,oldval,incr2
1258  // and newval,binopres,mask
1259  // and maskedoldval0,oldval,mask2
1260  // or storeval,maskedoldval0,newval
1261  // sc success,storeval,0(alignedaddr)
1262  // beq success,$0,loopMBB
1263 
1264  // atomic.swap
1265  // loopMBB:
1266  // ll oldval,0(alignedaddr)
1267  // and newval,incr2,mask
1268  // and maskedoldval0,oldval,mask2
1269  // or storeval,maskedoldval0,newval
1270  // sc success,storeval,0(alignedaddr)
1271  // beq success,$0,loopMBB
1272 
1273  BB = loopMBB;
1274  unsigned LL = isMicroMips ? Mips::LL_MM : Mips::LL;
1275  BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1276  if (Nand) {
1277  // and andres, oldval, incr2
1278  // nor binopres, $0, andres
1279  // and newval, binopres, mask
1280  BuildMI(BB, DL, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2);
1281  BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes)
1282  .addReg(Mips::ZERO).addReg(AndRes);
1283  BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1284  } else if (BinOpcode) {
1285  // <binop> binopres, oldval, incr2
1286  // and newval, binopres, mask
1287  BuildMI(BB, DL, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2);
1288  BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1289  } else { // atomic.swap
1290  // and newval, incr2, mask
1291  BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
1292  }
1293 
1294  BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
1295  .addReg(OldVal).addReg(Mask2);
1296  BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
1297  .addReg(MaskedOldVal0).addReg(NewVal);
1298  unsigned SC = isMicroMips ? Mips::SC_MM : Mips::SC;
1299  BuildMI(BB, DL, TII->get(SC), Success)
1300  .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1301  BuildMI(BB, DL, TII->get(Mips::BEQ))
1302  .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
1303 
1304  // sinkMBB:
1305  // and maskedoldval1,oldval,mask
1306  // srl srlres,maskedoldval1,shiftamt
1307  // sign_extend dest,srlres
1308  BB = sinkMBB;
1309 
1310  BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
1311  .addReg(OldVal).addReg(Mask);
1312  BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
1313  .addReg(MaskedOldVal1).addReg(ShiftAmt);
1314  BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes);
1315 
1316  MI->eraseFromParent(); // The instruction is gone now.
1317 
1318  return exitMBB;
1319 }
1320 
1321 MachineBasicBlock * MipsTargetLowering::emitAtomicCmpSwap(MachineInstr *MI,
1322  MachineBasicBlock *BB,
1323  unsigned Size) const {
1324  assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap.");
1325 
1326  MachineFunction *MF = BB->getParent();
1327  MachineRegisterInfo &RegInfo = MF->getRegInfo();
1328  const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1329  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1330  DebugLoc DL = MI->getDebugLoc();
1331  unsigned LL, SC, ZERO, BNE, BEQ;
1332 
1333  if (Size == 4) {
1334  LL = isMicroMips ? Mips::LL_MM : Mips::LL;
1335  SC = isMicroMips ? Mips::SC_MM : Mips::SC;
1336  ZERO = Mips::ZERO;
1337  BNE = Mips::BNE;
1338  BEQ = Mips::BEQ;
1339  } else {
1340  LL = Mips::LLD;
1341  SC = Mips::SCD;
1342  ZERO = Mips::ZERO_64;
1343  BNE = Mips::BNE64;
1344  BEQ = Mips::BEQ64;
1345  }
1346 
1347  unsigned Dest = MI->getOperand(0).getReg();
1348  unsigned Ptr = MI->getOperand(1).getReg();
1349  unsigned OldVal = MI->getOperand(2).getReg();
1350  unsigned NewVal = MI->getOperand(3).getReg();
1351 
1352  unsigned Success = RegInfo.createVirtualRegister(RC);
1353 
1354  // insert new blocks after the current block
1355  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1356  MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1357  MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1358  MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1359  MachineFunction::iterator It = BB;
1360  ++It;
1361  MF->insert(It, loop1MBB);
1362  MF->insert(It, loop2MBB);
1363  MF->insert(It, exitMBB);
1364 
1365  // Transfer the remainder of BB and its successor edges to exitMBB.
1366  exitMBB->splice(exitMBB->begin(), BB,
1367  std::next(MachineBasicBlock::iterator(MI)), BB->end());
1368  exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1369 
1370  // thisMBB:
1371  // ...
1372  // fallthrough --> loop1MBB
1373  BB->addSuccessor(loop1MBB);
1374  loop1MBB->addSuccessor(exitMBB);
1375  loop1MBB->addSuccessor(loop2MBB);
1376  loop2MBB->addSuccessor(loop1MBB);
1377  loop2MBB->addSuccessor(exitMBB);
1378 
1379  // loop1MBB:
1380  // ll dest, 0(ptr)
1381  // bne dest, oldval, exitMBB
1382  BB = loop1MBB;
1383  BuildMI(BB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0);
1384  BuildMI(BB, DL, TII->get(BNE))
1385  .addReg(Dest).addReg(OldVal).addMBB(exitMBB);
1386 
1387  // loop2MBB:
1388  // sc success, newval, 0(ptr)
1389  // beq success, $0, loop1MBB
1390  BB = loop2MBB;
1391  BuildMI(BB, DL, TII->get(SC), Success)
1392  .addReg(NewVal).addReg(Ptr).addImm(0);
1393  BuildMI(BB, DL, TII->get(BEQ))
1394  .addReg(Success).addReg(ZERO).addMBB(loop1MBB);
1395 
1396  MI->eraseFromParent(); // The instruction is gone now.
1397 
1398  return exitMBB;
1399 }
1400 
1402 MipsTargetLowering::emitAtomicCmpSwapPartword(MachineInstr *MI,
1403  MachineBasicBlock *BB,
1404  unsigned Size) const {
1405  assert((Size == 1 || Size == 2) &&
1406  "Unsupported size for EmitAtomicCmpSwapPartial.");
1407 
1408  MachineFunction *MF = BB->getParent();
1409  MachineRegisterInfo &RegInfo = MF->getRegInfo();
1411  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1412  DebugLoc DL = MI->getDebugLoc();
1413 
1414  unsigned Dest = MI->getOperand(0).getReg();
1415  unsigned Ptr = MI->getOperand(1).getReg();
1416  unsigned CmpVal = MI->getOperand(2).getReg();
1417  unsigned NewVal = MI->getOperand(3).getReg();
1418 
1419  unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1420  unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1421  unsigned Mask = RegInfo.createVirtualRegister(RC);
1422  unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1423  unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
1424  unsigned OldVal = RegInfo.createVirtualRegister(RC);
1425  unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1426  unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
1427  unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1428  unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1429  unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1430  unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
1431  unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
1432  unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1433  unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1434  unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1435  unsigned Success = RegInfo.createVirtualRegister(RC);
1436 
1437  // insert new blocks after the current block
1438  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1439  MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1440  MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1441  MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1442  MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1443  MachineFunction::iterator It = BB;
1444  ++It;
1445  MF->insert(It, loop1MBB);
1446  MF->insert(It, loop2MBB);
1447  MF->insert(It, sinkMBB);
1448  MF->insert(It, exitMBB);
1449 
1450  // Transfer the remainder of BB and its successor edges to exitMBB.
1451  exitMBB->splice(exitMBB->begin(), BB,
1452  std::next(MachineBasicBlock::iterator(MI)), BB->end());
1453  exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1454 
1455  BB->addSuccessor(loop1MBB);
1456  loop1MBB->addSuccessor(sinkMBB);
1457  loop1MBB->addSuccessor(loop2MBB);
1458  loop2MBB->addSuccessor(loop1MBB);
1459  loop2MBB->addSuccessor(sinkMBB);
1460  sinkMBB->addSuccessor(exitMBB);
1461 
1462  // FIXME: computation of newval2 can be moved to loop2MBB.
1463  // thisMBB:
1464  // addiu masklsb2,$0,-4 # 0xfffffffc
1465  // and alignedaddr,ptr,masklsb2
1466  // andi ptrlsb2,ptr,3
1467  // sll shiftamt,ptrlsb2,3
1468  // ori maskupper,$0,255 # 0xff
1469  // sll mask,maskupper,shiftamt
1470  // nor mask2,$0,mask
1471  // andi maskedcmpval,cmpval,255
1472  // sll shiftedcmpval,maskedcmpval,shiftamt
1473  // andi maskednewval,newval,255
1474  // sll shiftednewval,maskednewval,shiftamt
1475  int64_t MaskImm = (Size == 1) ? 255 : 65535;
1476  BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
1477  .addReg(Mips::ZERO).addImm(-4);
1478  BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
1479  .addReg(Ptr).addReg(MaskLSB2);
1480  BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1481  if (Subtarget.isLittle()) {
1482  BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1483  } else {
1484  unsigned Off = RegInfo.createVirtualRegister(RC);
1485  BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1486  .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1487  BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1488  }
1489  BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1490  .addReg(Mips::ZERO).addImm(MaskImm);
1491  BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1492  .addReg(MaskUpper).addReg(ShiftAmt);
1493  BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1494  BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal)
1495  .addReg(CmpVal).addImm(MaskImm);
1496  BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal)
1497  .addReg(MaskedCmpVal).addReg(ShiftAmt);
1498  BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal)
1499  .addReg(NewVal).addImm(MaskImm);
1500  BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal)
1501  .addReg(MaskedNewVal).addReg(ShiftAmt);
1502 
1503  // loop1MBB:
1504  // ll oldval,0(alginedaddr)
1505  // and maskedoldval0,oldval,mask
1506  // bne maskedoldval0,shiftedcmpval,sinkMBB
1507  BB = loop1MBB;
1508  unsigned LL = isMicroMips ? Mips::LL_MM : Mips::LL;
1509  BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1510  BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
1511  .addReg(OldVal).addReg(Mask);
1512  BuildMI(BB, DL, TII->get(Mips::BNE))
1513  .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
1514 
1515  // loop2MBB:
1516  // and maskedoldval1,oldval,mask2
1517  // or storeval,maskedoldval1,shiftednewval
1518  // sc success,storeval,0(alignedaddr)
1519  // beq success,$0,loop1MBB
1520  BB = loop2MBB;
1521  BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
1522  .addReg(OldVal).addReg(Mask2);
1523  BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
1524  .addReg(MaskedOldVal1).addReg(ShiftedNewVal);
1525  unsigned SC = isMicroMips ? Mips::SC_MM : Mips::SC;
1526  BuildMI(BB, DL, TII->get(SC), Success)
1527  .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1528  BuildMI(BB, DL, TII->get(Mips::BEQ))
1529  .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
1530 
1531  // sinkMBB:
1532  // srl srlres,maskedoldval0,shiftamt
1533  // sign_extend dest,srlres
1534  BB = sinkMBB;
1535 
1536  BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
1537  .addReg(MaskedOldVal0).addReg(ShiftAmt);
1538  BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes);
1539 
1540  MI->eraseFromParent(); // The instruction is gone now.
1541 
1542  return exitMBB;
1543 }
1544 
1545 MachineBasicBlock *MipsTargetLowering::emitSEL_D(MachineInstr *MI,
1546  MachineBasicBlock *BB) const {
1547  MachineFunction *MF = BB->getParent();
1549  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1550  MachineRegisterInfo &RegInfo = MF->getRegInfo();
1551  DebugLoc DL = MI->getDebugLoc();
1553 
1554  unsigned Fc = MI->getOperand(1).getReg();
1555  const auto &FGR64RegClass = TRI->getRegClass(Mips::FGR64RegClassID);
1556 
1557  unsigned Fc2 = RegInfo.createVirtualRegister(FGR64RegClass);
1558 
1559  BuildMI(*BB, II, DL, TII->get(Mips::SUBREG_TO_REG), Fc2)
1560  .addImm(0)
1561  .addReg(Fc)
1562  .addImm(Mips::sub_lo);
1563 
1564  // We don't erase the original instruction, we just replace the condition
1565  // register with the 64-bit super-register.
1566  MI->getOperand(1).setReg(Fc2);
1567 
1568  return BB;
1569 }
1570 
1571 //===----------------------------------------------------------------------===//
1572 // Misc Lower Operation implementation
1573 //===----------------------------------------------------------------------===//
1574 SDValue MipsTargetLowering::lowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
1575  SDValue Chain = Op.getOperand(0);
1576  SDValue Table = Op.getOperand(1);
1577  SDValue Index = Op.getOperand(2);
1578  SDLoc DL(Op);
1579  auto &TD = DAG.getDataLayout();
1580  EVT PTy = getPointerTy(TD);
1581  unsigned EntrySize =
1583 
1584  Index = DAG.getNode(ISD::MUL, DL, PTy, Index,
1585  DAG.getConstant(EntrySize, DL, PTy));
1586  SDValue Addr = DAG.getNode(ISD::ADD, DL, PTy, Index, Table);
1587 
1588  EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
1589  Addr = DAG.getExtLoad(ISD::SEXTLOAD, DL, PTy, Chain, Addr,
1590  MachinePointerInfo::getJumpTable(), MemVT, false, false,
1591  false, 0);
1592  Chain = Addr.getValue(1);
1593 
1594  if ((getTargetMachine().getRelocationModel() == Reloc::PIC_) || ABI.IsN64()) {
1595  // For PIC, the sequence is:
1596  // BRIND(load(Jumptable + index) + RelocBase)
1597  // RelocBase can be JumpTable, GOT or some sort of global base.
1598  Addr = DAG.getNode(ISD::ADD, DL, PTy, Addr,
1599  getPICJumpTableRelocBase(Table, DAG));
1600  }
1601 
1602  return DAG.getNode(ISD::BRIND, DL, MVT::Other, Chain, Addr);
1603 }
1604 
1605 SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
1606  // The first operand is the chain, the second is the condition, the third is
1607  // the block to branch to if the condition is true.
1608  SDValue Chain = Op.getOperand(0);
1609  SDValue Dest = Op.getOperand(2);
1610  SDLoc DL(Op);
1611 
1612  assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
1613  SDValue CondRes = createFPCmp(DAG, Op.getOperand(1));
1614 
1615  // Return if flag is not set by a floating point comparison.
1616  if (CondRes.getOpcode() != MipsISD::FPCmp)
1617  return Op;
1618 
1619  SDValue CCNode = CondRes.getOperand(2);
1620  Mips::CondCode CC =
1621  (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
1622  unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T;
1623  SDValue BrCode = DAG.getConstant(Opc, DL, MVT::i32);
1624  SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
1625  return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode,
1626  FCC0, Dest, CondRes);
1627 }
1628 
1629 SDValue MipsTargetLowering::
1630 lowerSELECT(SDValue Op, SelectionDAG &DAG) const
1631 {
1632  assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
1633  SDValue Cond = createFPCmp(DAG, Op.getOperand(0));
1634 
1635  // Return if flag is not set by a floating point comparison.
1636  if (Cond.getOpcode() != MipsISD::FPCmp)
1637  return Op;
1638 
1639  return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
1640  SDLoc(Op));
1641 }
1642 
1643 SDValue MipsTargetLowering::
1644 lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
1645 {
1646  SDLoc DL(Op);
1647  EVT Ty = Op.getOperand(0).getValueType();
1648  SDValue Cond =
1650  *DAG.getContext(), Ty),
1651  Op.getOperand(0), Op.getOperand(1), Op.getOperand(4));
1652 
1653  return DAG.getNode(ISD::SELECT, DL, Op.getValueType(), Cond, Op.getOperand(2),
1654  Op.getOperand(3));
1655 }
1656 
1657 SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1658  assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
1659  SDValue Cond = createFPCmp(DAG, Op);
1660 
1661  assert(Cond.getOpcode() == MipsISD::FPCmp &&
1662  "Floating point operand expected.");
1663 
1664  SDLoc DL(Op);
1665  SDValue True = DAG.getConstant(1, DL, MVT::i32);
1666  SDValue False = DAG.getConstant(0, DL, MVT::i32);
1667 
1668  return createCMovFP(DAG, Cond, True, False, DL);
1669 }
1670 
1671 SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
1672  SelectionDAG &DAG) const {
1673  EVT Ty = Op.getValueType();
1674  GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
1675  const GlobalValue *GV = N->getGlobal();
1676 
1677  if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !ABI.IsN64()) {
1678  const MipsTargetObjectFile *TLOF =
1679  static_cast<const MipsTargetObjectFile *>(
1681  if (TLOF->IsGlobalInSmallSection(GV, getTargetMachine()))
1682  // %gp_rel relocation
1683  return getAddrGPRel(N, SDLoc(N), Ty, DAG);
1684 
1685  // %hi/%lo relocation
1686  return getAddrNonPIC(N, SDLoc(N), Ty, DAG);
1687  }
1688 
1689  if (GV->hasInternalLinkage() || (GV->hasLocalLinkage() && !isa<Function>(GV)))
1690  return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
1691 
1692  if (LargeGOT)
1693  return getAddrGlobalLargeGOT(N, SDLoc(N), Ty, DAG, MipsII::MO_GOT_HI16,
1694  MipsII::MO_GOT_LO16, DAG.getEntryNode(),
1696 
1697  return getAddrGlobal(N, SDLoc(N), Ty, DAG,
1699  : MipsII::MO_GOT16,
1700  DAG.getEntryNode(), MachinePointerInfo::getGOT());
1701 }
1702 
1703 SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op,
1704  SelectionDAG &DAG) const {
1705  BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op);
1706  EVT Ty = Op.getValueType();
1707 
1708  if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !ABI.IsN64())
1709  return getAddrNonPIC(N, SDLoc(N), Ty, DAG);
1710 
1711  return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
1712 }
1713 
1714 SDValue MipsTargetLowering::
1715 lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
1716 {
1717  // If the relocation model is PIC, use the General Dynamic TLS Model or
1718  // Local Dynamic TLS model, otherwise use the Initial Exec or
1719  // Local Exec TLS Model.
1720 
1721  GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1722  SDLoc DL(GA);
1723  const GlobalValue *GV = GA->getGlobal();
1724  EVT PtrVT = getPointerTy(DAG.getDataLayout());
1725 
1727 
1728  if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
1729  // General Dynamic and Local Dynamic TLS Model.
1730  unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM
1731  : MipsII::MO_TLSGD;
1732 
1733  SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag);
1734  SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT,
1735  getGlobalReg(DAG, PtrVT), TGA);
1736  unsigned PtrSize = PtrVT.getSizeInBits();
1737  IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize);
1738 
1739  SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT);
1740 
1741  ArgListTy Args;
1742  ArgListEntry Entry;
1743  Entry.Node = Argument;
1744  Entry.Ty = PtrTy;
1745  Args.push_back(Entry);
1746 
1748  CLI.setDebugLoc(DL).setChain(DAG.getEntryNode())
1749  .setCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args), 0);
1750  std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1751 
1752  SDValue Ret = CallResult.first;
1753 
1754  if (model != TLSModel::LocalDynamic)
1755  return Ret;
1756 
1757  SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1759  SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
1760  SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1762  SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
1763  SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret);
1764  return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo);
1765  }
1766 
1767  SDValue Offset;
1768  if (model == TLSModel::InitialExec) {
1769  // Initial Exec TLS Model
1770  SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1772  TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT),
1773  TGA);
1774  Offset = DAG.getLoad(PtrVT, DL,
1775  DAG.getEntryNode(), TGA, MachinePointerInfo(),
1776  false, false, false, 0);
1777  } else {
1778  // Local Exec TLS Model
1779  assert(model == TLSModel::LocalExec);
1780  SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1782  SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1784  SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
1785  SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
1786  Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1787  }
1788 
1790  return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset);
1791 }
1792 
1793 SDValue MipsTargetLowering::
1794 lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
1795 {
1796  JumpTableSDNode *N = cast<JumpTableSDNode>(Op);
1797  EVT Ty = Op.getValueType();
1798 
1799  if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !ABI.IsN64())
1800  return getAddrNonPIC(N, SDLoc(N), Ty, DAG);
1801 
1802  return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
1803 }
1804 
1805 SDValue MipsTargetLowering::
1806 lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
1807 {
1808  ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
1809  EVT Ty = Op.getValueType();
1810 
1811  if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !ABI.IsN64()) {
1812  const MipsTargetObjectFile *TLOF =
1813  static_cast<const MipsTargetObjectFile *>(
1815 
1817  // %gp_rel relocation
1818  return getAddrGPRel(N, SDLoc(N), Ty, DAG);
1819 
1820  return getAddrNonPIC(N, SDLoc(N), Ty, DAG);
1821  }
1822 
1823  return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
1824 }
1825 
1826 SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
1827  MachineFunction &MF = DAG.getMachineFunction();
1828  MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
1829 
1830  SDLoc DL(Op);
1831  SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1832  getPointerTy(MF.getDataLayout()));
1833 
1834  // vastart just stores the address of the VarArgsFrameIndex slot into the
1835  // memory location argument.
1836  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1837  return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
1838  MachinePointerInfo(SV), false, false, 0);
1839 }
1840 
1841 SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const {
1842  SDNode *Node = Op.getNode();
1843  EVT VT = Node->getValueType(0);
1844  SDValue Chain = Node->getOperand(0);
1845  SDValue VAListPtr = Node->getOperand(1);
1846  unsigned Align = Node->getConstantOperandVal(3);
1847  const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1848  SDLoc DL(Node);
1849  unsigned ArgSlotSizeInBytes = (ABI.IsN32() || ABI.IsN64()) ? 8 : 4;
1850 
1851  SDValue VAListLoad =
1852  DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL, Chain, VAListPtr,
1853  MachinePointerInfo(SV), false, false, false, 0);
1854  SDValue VAList = VAListLoad;
1855 
1856  // Re-align the pointer if necessary.
1857  // It should only ever be necessary for 64-bit types on O32 since the minimum
1858  // argument alignment is the same as the maximum type alignment for N32/N64.
1859  //
1860  // FIXME: We currently align too often. The code generator doesn't notice
1861  // when the pointer is still aligned from the last va_arg (or pair of
1862  // va_args for the i64 on O32 case).
1863  if (Align > getMinStackArgumentAlignment()) {
1864  assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
1865 
1866  VAList = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
1867  DAG.getConstant(Align - 1, DL, VAList.getValueType()));
1868 
1869  VAList = DAG.getNode(ISD::AND, DL, VAList.getValueType(), VAList,
1870  DAG.getConstant(-(int64_t)Align, DL,
1871  VAList.getValueType()));
1872  }
1873 
1874  // Increment the pointer, VAList, to the next vaarg.
1875  auto &TD = DAG.getDataLayout();
1876  unsigned ArgSizeInBytes =
1877  TD.getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext()));
1878  SDValue Tmp3 = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
1879  DAG.getConstant(RoundUpToAlignment(ArgSizeInBytes,
1880  ArgSlotSizeInBytes),
1881  DL, VAList.getValueType()));
1882  // Store the incremented VAList to the legalized pointer
1883  Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr,
1884  MachinePointerInfo(SV), false, false, 0);
1885 
1886  // In big-endian mode we must adjust the pointer when the load size is smaller
1887  // than the argument slot size. We must also reduce the known alignment to
1888  // match. For example in the N64 ABI, we must add 4 bytes to the offset to get
1889  // the correct half of the slot, and reduce the alignment from 8 (slot
1890  // alignment) down to 4 (type alignment).
1891  if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) {
1892  unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes;
1893  VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList,
1894  DAG.getIntPtrConstant(Adjustment, DL));
1895  }
1896  // Load the actual argument out of the pointer VAList
1897  return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo(), false, false,
1898  false, 0);
1899 }
1900 
1902  bool HasExtractInsert) {
1903  EVT TyX = Op.getOperand(0).getValueType();
1904  EVT TyY = Op.getOperand(1).getValueType();
1905  SDLoc DL(Op);
1906  SDValue Const1 = DAG.getConstant(1, DL, MVT::i32);
1907  SDValue Const31 = DAG.getConstant(31, DL, MVT::i32);
1908  SDValue Res;
1909 
1910  // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
1911  // to i32.
1912  SDValue X = (TyX == MVT::f32) ?
1913  DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
1915  Const1);
1916  SDValue Y = (TyY == MVT::f32) ?
1917  DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
1919  Const1);
1920 
1921  if (HasExtractInsert) {
1922  // ext E, Y, 31, 1 ; extract bit31 of Y
1923  // ins X, E, 31, 1 ; insert extracted bit at bit31 of X
1924  SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
1925  Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
1926  } else {
1927  // sll SllX, X, 1
1928  // srl SrlX, SllX, 1
1929  // srl SrlY, Y, 31
1930  // sll SllY, SrlX, 31
1931  // or Or, SrlX, SllY
1932  SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
1933  SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
1934  SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
1935  SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
1936  Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
1937  }
1938 
1939  if (TyX == MVT::f32)
1940  return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
1941 
1943  Op.getOperand(0),
1944  DAG.getConstant(0, DL, MVT::i32));
1945  return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
1946 }
1947 
1949  bool HasExtractInsert) {
1950  unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
1951  unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
1952  EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
1953  SDLoc DL(Op);
1954  SDValue Const1 = DAG.getConstant(1, DL, MVT::i32);
1955 
1956  // Bitcast to integer nodes.
1957  SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
1958  SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
1959 
1960  if (HasExtractInsert) {
1961  // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y
1962  // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X
1963  SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
1964  DAG.getConstant(WidthY - 1, DL, MVT::i32), Const1);
1965 
1966  if (WidthX > WidthY)
1967  E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
1968  else if (WidthY > WidthX)
1969  E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
1970 
1971  SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
1972  DAG.getConstant(WidthX - 1, DL, MVT::i32), Const1,
1973  X);
1974  return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
1975  }
1976 
1977  // (d)sll SllX, X, 1
1978  // (d)srl SrlX, SllX, 1
1979  // (d)srl SrlY, Y, width(Y)-1
1980  // (d)sll SllY, SrlX, width(Y)-1
1981  // or Or, SrlX, SllY
1982  SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
1983  SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
1984  SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
1985  DAG.getConstant(WidthY - 1, DL, MVT::i32));
1986 
1987  if (WidthX > WidthY)
1988  SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
1989  else if (WidthY > WidthX)
1990  SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
1991 
1992  SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
1993  DAG.getConstant(WidthX - 1, DL, MVT::i32));
1994  SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
1995  return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
1996 }
1997 
1998 SDValue
1999 MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2000  if (Subtarget.isGP64bit())
2001  return lowerFCOPYSIGN64(Op, DAG, Subtarget.hasExtractInsert());
2002 
2003  return lowerFCOPYSIGN32(Op, DAG, Subtarget.hasExtractInsert());
2004 }
2005 
2006 SDValue MipsTargetLowering::
2007 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2008  // check the depth
2009  assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
2010  "Frame address can only be determined for current frame.");
2011 
2013  MFI->setFrameAddressIsTaken(true);
2014  EVT VT = Op.getValueType();
2015  SDLoc DL(Op);
2016  SDValue FrameAddr = DAG.getCopyFromReg(
2017  DAG.getEntryNode(), DL, ABI.IsN64() ? Mips::FP_64 : Mips::FP, VT);
2018  return FrameAddr;
2019 }
2020 
2021 SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op,
2022  SelectionDAG &DAG) const {
2024  return SDValue();
2025 
2026  // check the depth
2027  assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
2028  "Return address can be determined only for current frame.");
2029 
2030  MachineFunction &MF = DAG.getMachineFunction();
2031  MachineFrameInfo *MFI = MF.getFrameInfo();
2032  MVT VT = Op.getSimpleValueType();
2033  unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA;
2034  MFI->setReturnAddressIsTaken(true);
2035 
2036  // Return RA, which contains the return address. Mark it an implicit live-in.
2037  unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
2038  return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT);
2039 }
2040 
2041 // An EH_RETURN is the result of lowering llvm.eh.return which in turn is
2042 // generated from __builtin_eh_return (offset, handler)
2043 // The effect of this is to adjust the stack pointer by "offset"
2044 // and then branch to "handler".
2045 SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
2046  const {
2047  MachineFunction &MF = DAG.getMachineFunction();
2048  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2049 
2050  MipsFI->setCallsEhReturn();
2051  SDValue Chain = Op.getOperand(0);
2052  SDValue Offset = Op.getOperand(1);
2053  SDValue Handler = Op.getOperand(2);
2054  SDLoc DL(Op);
2055  EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32;
2056 
2057  // Store stack offset in V1, store jump target in V0. Glue CopyToReg and
2058  // EH_RETURN nodes, so that instructions are emitted back-to-back.
2059  unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1;
2060  unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
2061  Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue());
2062  Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1));
2063  return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain,
2064  DAG.getRegister(OffsetReg, Ty),
2065  DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())),
2066  Chain.getValue(1));
2067 }
2068 
2069 SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op,
2070  SelectionDAG &DAG) const {
2071  // FIXME: Need pseudo-fence for 'singlethread' fences
2072  // FIXME: Set SType for weaker fences where supported/appropriate.
2073  unsigned SType = 0;
2074  SDLoc DL(Op);
2075  return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0),
2076  DAG.getConstant(SType, DL, MVT::i32));
2077 }
2078 
2079 SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,
2080  SelectionDAG &DAG) const {
2081  SDLoc DL(Op);
2083 
2084  SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2085  SDValue Shamt = Op.getOperand(2);
2086  // if shamt < (VT.bits):
2087  // lo = (shl lo, shamt)
2088  // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))
2089  // else:
2090  // lo = 0
2091  // hi = (shl lo, shamt[4:0])
2092  SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2093  DAG.getConstant(-1, DL, MVT::i32));
2094  SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo,
2095  DAG.getConstant(1, DL, VT));
2096  SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not);
2097  SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);
2098  SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2099  SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
2100  SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2101  DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
2102  Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2103  DAG.getConstant(0, DL, VT), ShiftLeftLo);
2104  Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or);
2105 
2106  SDValue Ops[2] = {Lo, Hi};
2107  return DAG.getMergeValues(Ops, DL);
2108 }
2109 
2110 SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
2111  bool IsSRA) const {
2112  SDLoc DL(Op);
2113  SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2114  SDValue Shamt = Op.getOperand(2);
2116 
2117  // if shamt < (VT.bits):
2118  // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))
2119  // if isSRA:
2120  // hi = (sra hi, shamt)
2121  // else:
2122  // hi = (srl hi, shamt)
2123  // else:
2124  // if isSRA:
2125  // lo = (sra hi, shamt[4:0])
2126  // hi = (sra hi, 31)
2127  // else:
2128  // lo = (srl hi, shamt[4:0])
2129  // hi = 0
2130  SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2131  DAG.getConstant(-1, DL, MVT::i32));
2132  SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi,
2133  DAG.getConstant(1, DL, VT));
2134  SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not);
2135  SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);
2136  SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2137  SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL,
2138  DL, VT, Hi, Shamt);
2139  SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2140  DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
2141  SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi,
2142  DAG.getConstant(VT.getSizeInBits() - 1, DL, VT));
2143  Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or);
2144  Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2145  IsSRA ? Ext : DAG.getConstant(0, DL, VT), ShiftRightHi);
2146 
2147  SDValue Ops[2] = {Lo, Hi};
2148  return DAG.getMergeValues(Ops, DL);
2149 }
2150 
2151 static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
2152  SDValue Chain, SDValue Src, unsigned Offset) {
2153  SDValue Ptr = LD->getBasePtr();
2154  EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
2155  EVT BasePtrVT = Ptr.getValueType();
2156  SDLoc DL(LD);
2157  SDVTList VTList = DAG.getVTList(VT, MVT::Other);
2158 
2159  if (Offset)
2160  Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2161  DAG.getConstant(Offset, DL, BasePtrVT));
2162 
2163  SDValue Ops[] = { Chain, Ptr, Src };
2164  return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2165  LD->getMemOperand());
2166 }
2167 
2168 // Expand an unaligned 32 or 64-bit integer load node.
2170  LoadSDNode *LD = cast<LoadSDNode>(Op);
2171  EVT MemVT = LD->getMemoryVT();
2172 
2174  return Op;
2175 
2176  // Return if load is aligned or if MemVT is neither i32 nor i64.
2177  if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
2178  ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2179  return SDValue();
2180 
2181  bool IsLittle = Subtarget.isLittle();
2182  EVT VT = Op.getValueType();
2183  ISD::LoadExtType ExtType = LD->getExtensionType();
2184  SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT);
2185 
2186  assert((VT == MVT::i32) || (VT == MVT::i64));
2187 
2188  // Expand
2189  // (set dst, (i64 (load baseptr)))
2190  // to
2191  // (set tmp, (ldl (add baseptr, 7), undef))
2192  // (set dst, (ldr baseptr, tmp))
2193  if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
2194  SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef,
2195  IsLittle ? 7 : 0);
2196  return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL,
2197  IsLittle ? 0 : 7);
2198  }
2199 
2200  SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef,
2201  IsLittle ? 3 : 0);
2202  SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL,
2203  IsLittle ? 0 : 3);
2204 
2205  // Expand
2206  // (set dst, (i32 (load baseptr))) or
2207  // (set dst, (i64 (sextload baseptr))) or
2208  // (set dst, (i64 (extload baseptr)))
2209  // to
2210  // (set tmp, (lwl (add baseptr, 3), undef))
2211  // (set dst, (lwr baseptr, tmp))
2212  if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) ||
2213  (ExtType == ISD::EXTLOAD))
2214  return LWR;
2215 
2216  assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD));
2217 
2218  // Expand
2219  // (set dst, (i64 (zextload baseptr)))
2220  // to
2221  // (set tmp0, (lwl (add baseptr, 3), undef))
2222  // (set tmp1, (lwr baseptr, tmp0))
2223  // (set tmp2, (shl tmp1, 32))
2224  // (set dst, (srl tmp2, 32))
2225  SDLoc DL(LD);
2226  SDValue Const32 = DAG.getConstant(32, DL, MVT::i32);
2227  SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
2228  SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
2229  SDValue Ops[] = { SRL, LWR.getValue(1) };
2230  return DAG.getMergeValues(Ops, DL);
2231 }
2232 
2233 static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD,
2234  SDValue Chain, unsigned Offset) {
2235  SDValue Ptr = SD->getBasePtr(), Value = SD->getValue();
2236  EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType();
2237  SDLoc DL(SD);
2238  SDVTList VTList = DAG.getVTList(MVT::Other);
2239 
2240  if (Offset)
2241  Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2242  DAG.getConstant(Offset, DL, BasePtrVT));
2243 
2244  SDValue Ops[] = { Chain, Value, Ptr };
2245  return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2246  SD->getMemOperand());
2247 }
2248 
2249 // Expand an unaligned 32 or 64-bit integer store node.
2251  bool IsLittle) {
2252  SDValue Value = SD->getValue(), Chain = SD->getChain();
2253  EVT VT = Value.getValueType();
2254 
2255  // Expand
2256  // (store val, baseptr) or
2257  // (truncstore val, baseptr)
2258  // to
2259  // (swl val, (add baseptr, 3))
2260  // (swr val, baseptr)
2261  if ((VT == MVT::i32) || SD->isTruncatingStore()) {
2262  SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain,
2263  IsLittle ? 3 : 0);
2264  return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3);
2265  }
2266 
2267  assert(VT == MVT::i64);
2268 
2269  // Expand
2270  // (store val, baseptr)
2271  // to
2272  // (sdl val, (add baseptr, 7))
2273  // (sdr val, baseptr)
2274  SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0);
2275  return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7);
2276 }
2277 
2278 // Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr).
2280  SDValue Val = SD->getValue();
2281 
2282  if (Val.getOpcode() != ISD::FP_TO_SINT)
2283  return SDValue();
2284 
2286  SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy,
2287  Val.getOperand(0));
2288 
2289  return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(),
2290  SD->getPointerInfo(), SD->isVolatile(),
2291  SD->isNonTemporal(), SD->getAlignment());
2292 }
2293 
2295  StoreSDNode *SD = cast<StoreSDNode>(Op);
2296  EVT MemVT = SD->getMemoryVT();
2297 
2298  // Lower unaligned integer stores.
2300  (SD->getAlignment() < MemVT.getSizeInBits() / 8) &&
2301  ((MemVT == MVT::i32) || (MemVT == MVT::i64)))
2302  return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle());
2303 
2304  return lowerFP_TO_SINT_STORE(SD, DAG);
2305 }
2306 
2307 SDValue MipsTargetLowering::lowerADD(SDValue Op, SelectionDAG &DAG) const {
2308  if (Op->getOperand(0).getOpcode() != ISD::FRAMEADDR
2309  || cast<ConstantSDNode>
2310  (Op->getOperand(0).getOperand(0))->getZExtValue() != 0
2312  return SDValue();
2313 
2314  // The pattern
2315  // (add (frameaddr 0), (frame_to_args_offset))
2316  // results from lowering llvm.eh.dwarf.cfa intrinsic. Transform it to
2317  // (add FrameObject, 0)
2318  // where FrameObject is a fixed StackObject with offset 0 which points to
2319  // the old stack pointer.
2321  EVT ValTy = Op->getValueType(0);
2322  int FI = MFI->CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false);
2323  SDValue InArgsAddr = DAG.getFrameIndex(FI, ValTy);
2324  SDLoc DL(Op);
2325  return DAG.getNode(ISD::ADD, DL, ValTy, InArgsAddr,
2326  DAG.getConstant(0, DL, ValTy));
2327 }
2328 
2329 SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op,
2330  SelectionDAG &DAG) const {
2332  SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy,
2333  Op.getOperand(0));
2334  return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc);
2335 }
2336 
2337 //===----------------------------------------------------------------------===//
2338 // Calling Convention Implementation
2339 //===----------------------------------------------------------------------===//
2340 
2341 //===----------------------------------------------------------------------===//
2342 // TODO: Implement a generic logic using tblgen that can support this.
2343 // Mips O32 ABI rules:
2344 // ---
2345 // i32 - Passed in A0, A1, A2, A3 and stack
2346 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
2347 // an argument. Otherwise, passed in A1, A2, A3 and stack.
2348 // f64 - Only passed in two aliased f32 registers if no int reg has been used
2349 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
2350 // not used, it must be shadowed. If only A3 is available, shadow it and
2351 // go to stack.
2352 //
2353 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
2354 //===----------------------------------------------------------------------===//
2355 
2356 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
2357  CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
2358  CCState &State, ArrayRef<MCPhysReg> F64Regs) {
2359  const MipsSubtarget &Subtarget = static_cast<const MipsSubtarget &>(
2360  State.getMachineFunction().getSubtarget());
2361 
2362  static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 };
2363  static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 };
2364 
2365  // Do not process byval args here.
2366  if (ArgFlags.isByVal())
2367  return true;
2368 
2369  // Promote i8 and i16
2370  if (ArgFlags.isInReg() && !Subtarget.isLittle()) {
2371  if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) {
2372  LocVT = MVT::i32;
2373  if (ArgFlags.isSExt())
2374  LocInfo = CCValAssign::SExtUpper;
2375  else if (ArgFlags.isZExt())
2376  LocInfo = CCValAssign::ZExtUpper;
2377  else
2378  LocInfo = CCValAssign::AExtUpper;
2379  }
2380  }
2381 
2382  // Promote i8 and i16
2383  if (LocVT == MVT::i8 || LocVT == MVT::i16) {
2384  LocVT = MVT::i32;
2385  if (ArgFlags.isSExt())
2386  LocInfo = CCValAssign::SExt;
2387  else if (ArgFlags.isZExt())
2388  LocInfo = CCValAssign::ZExt;
2389  else
2390  LocInfo = CCValAssign::AExt;
2391  }
2392 
2393  unsigned Reg;
2394 
2395  // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
2396  // is true: function is vararg, argument is 3rd or higher, there is previous
2397  // argument which is not f32 or f64.
2398  bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 ||
2399  State.getFirstUnallocated(F32Regs) != ValNo;
2400  unsigned OrigAlign = ArgFlags.getOrigAlign();
2401  bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
2402 
2403  if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
2404  Reg = State.AllocateReg(IntRegs);
2405  // If this is the first part of an i64 arg,
2406  // the allocated register must be either A0 or A2.
2407  if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
2408  Reg = State.AllocateReg(IntRegs);
2409  LocVT = MVT::i32;
2410  } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
2411  // Allocate int register and shadow next int register. If first
2412  // available register is Mips::A1 or Mips::A3, shadow it too.
2413  Reg = State.AllocateReg(IntRegs);
2414  if (Reg == Mips::A1 || Reg == Mips::A3)
2415  Reg = State.AllocateReg(IntRegs);
2416  State.AllocateReg(IntRegs);
2417  LocVT = MVT::i32;
2418  } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
2419  // we are guaranteed to find an available float register
2420  if (ValVT == MVT::f32) {
2421  Reg = State.AllocateReg(F32Regs);
2422  // Shadow int register
2423  State.AllocateReg(IntRegs);
2424  } else {
2425  Reg = State.AllocateReg(F64Regs);
2426  // Shadow int registers
2427  unsigned Reg2 = State.AllocateReg(IntRegs);
2428  if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
2429  State.AllocateReg(IntRegs);
2430  State.AllocateReg(IntRegs);
2431  }
2432  } else
2433  llvm_unreachable("Cannot handle this ValVT.");
2434 
2435  if (!Reg) {
2436  unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3,
2437  OrigAlign);
2438  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
2439  } else
2440  State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2441 
2442  return false;
2443 }
2444 
2445 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT,
2446  MVT LocVT, CCValAssign::LocInfo LocInfo,
2447  ISD::ArgFlagsTy ArgFlags, CCState &State) {
2448  static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 };
2449 
2450  return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2451 }
2452 
2453 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT,
2454  MVT LocVT, CCValAssign::LocInfo LocInfo,
2455  ISD::ArgFlagsTy ArgFlags, CCState &State) {
2456  static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 };
2457 
2458  return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2459 }
2460 
2461 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
2462  CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
2464 
2465 #include "MipsGenCallingConv.inc"
2466 
2467 //===----------------------------------------------------------------------===//
2468 // Call Calling Convention Implementation
2469 //===----------------------------------------------------------------------===//
2470 
2471 // Return next O32 integer argument register.
2472 static unsigned getNextIntArgReg(unsigned Reg) {
2473  assert((Reg == Mips::A0) || (Reg == Mips::A2));
2474  return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
2475 }
2476 
2477 SDValue
2478 MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset,
2479  SDValue Chain, SDValue Arg, SDLoc DL,
2480  bool IsTailCall, SelectionDAG &DAG) const {
2481  if (!IsTailCall) {
2482  SDValue PtrOff =
2483  DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr,
2484  DAG.getIntPtrConstant(Offset, DL));
2485  return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo(), false,
2486  false, 0);
2487  }
2488 
2490  int FI = MFI->CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false);
2491  SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2492  return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(),
2493  /*isVolatile=*/ true, false, 0);
2494 }
2495 
2498  std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
2499  bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
2500  bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
2501  SDValue Chain) const {
2502  // Insert node "GP copy globalreg" before call to function.
2503  //
2504  // R_MIPS_CALL* operators (emitted when non-internal functions are called
2505  // in PIC mode) allow symbols to be resolved via lazy binding.
2506  // The lazy binding stub requires GP to point to the GOT.
2507  // Note that we don't need GP to point to the GOT for indirect calls
2508  // (when R_MIPS_CALL* is not used for the call) because Mips linker generates
2509  // lazy binding stub for a function only when R_MIPS_CALL* are the only relocs
2510  // used for the function (that is, Mips linker doesn't generate lazy binding
2511  // stub for a function whose address is taken in the program).
2512  if (IsPICCall && !InternalLinkage && IsCallReloc) {
2513  unsigned GPReg = ABI.IsN64() ? Mips::GP_64 : Mips::GP;
2514  EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32;
2515  RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty)));
2516  }
2517 
2518  // Build a sequence of copy-to-reg nodes chained together with token
2519  // chain and flag operands which copy the outgoing args into registers.
2520  // The InFlag in necessary since all emitted instructions must be
2521  // stuck together.
2522  SDValue InFlag;
2523 
2524  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2525  Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first,
2526  RegsToPass[i].second, InFlag);
2527  InFlag = Chain.getValue(1);
2528  }
2529 
2530  // Add argument registers to the end of the list so that they are
2531  // known live into the call.
2532  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2533  Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first,
2534  RegsToPass[i].second.getValueType()));
2535 
2536  // Add a register mask operand representing the call-preserved registers.
2538  const uint32_t *Mask =
2540  assert(Mask && "Missing call preserved mask for calling convention");
2541  if (Subtarget.inMips16HardFloat()) {
2542  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) {
2543  llvm::StringRef Sym = G->getGlobal()->getName();
2544  Function *F = G->getGlobal()->getParent()->getFunction(Sym);
2545  if (F && F->hasFnAttribute("__Mips16RetHelper")) {
2547  }
2548  }
2549  }
2550  Ops.push_back(CLI.DAG.getRegisterMask(Mask));
2551 
2552  if (InFlag.getNode())
2553  Ops.push_back(InFlag);
2554 }
2555 
2556 /// LowerCall - functions arguments are copied from virtual regs to
2557 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
2558 SDValue
2559 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2560  SmallVectorImpl<SDValue> &InVals) const {
2561  SelectionDAG &DAG = CLI.DAG;
2562  SDLoc DL = CLI.DL;
2564  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2566  SDValue Chain = CLI.Chain;
2567  SDValue Callee = CLI.Callee;
2568  bool &IsTailCall = CLI.IsTailCall;
2569  CallingConv::ID CallConv = CLI.CallConv;
2570  bool IsVarArg = CLI.IsVarArg;
2571 
2572  MachineFunction &MF = DAG.getMachineFunction();
2573  MachineFrameInfo *MFI = MF.getFrameInfo();
2575  MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
2576  bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
2577 
2578  // Analyze operands of the call, assigning locations to each operand.
2580  MipsCCState CCInfo(
2581  CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(),
2583 
2584  // Allocate the reserved argument area. It seems strange to do this from the
2585  // caller side but removing it breaks the frame size calculation.
2586  CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1);
2587 
2588  CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(), Callee.getNode());
2589 
2590  // Get a count of how many bytes are to be pushed on the stack.
2591  unsigned NextStackOffset = CCInfo.getNextStackOffset();
2592 
2593  // Check if it's really possible to do a tail call.
2594  if (IsTailCall)
2595  IsTailCall = isEligibleForTailCallOptimization(
2596  CCInfo, NextStackOffset, *MF.getInfo<MipsFunctionInfo>());
2597 
2598  if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall())
2599  report_fatal_error("failed to perform tail call elimination on a call "
2600  "site marked musttail");
2601 
2602  if (IsTailCall)
2603  ++NumTailCalls;
2604 
2605  // Chain is the output chain of the last Load/Store or CopyToReg node.
2606  // ByValChain is the output chain of the last Memcpy node created for copying
2607  // byval arguments to the stack.
2608  unsigned StackAlignment = TFL->getStackAlignment();
2609  NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment);
2610  SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true);
2611 
2612  if (!IsTailCall)
2613  Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal, DL);
2614 
2615  SDValue StackPtr =
2616  DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP,
2617  getPointerTy(DAG.getDataLayout()));
2618 
2619  // With EABI is it possible to have 16 args on registers.
2620  std::deque< std::pair<unsigned, SDValue> > RegsToPass;
2621  SmallVector<SDValue, 8> MemOpChains;
2622 
2623  CCInfo.rewindByValRegsInfo();
2624 
2625  // Walk the register/memloc assignments, inserting copies/loads.
2626  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2627  SDValue Arg = OutVals[i];
2628  CCValAssign &VA = ArgLocs[i];
2629  MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
2630  ISD::ArgFlagsTy Flags = Outs[i].Flags;
2631  bool UseUpperBits = false;
2632 
2633  // ByVal Arg.
2634  if (Flags.isByVal()) {
2635  unsigned FirstByValReg, LastByValReg;
2636  unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
2637  CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
2638 
2639  assert(Flags.getByValSize() &&
2640  "ByVal args of size 0 should have been ignored by front-end.");
2641  assert(ByValIdx < CCInfo.getInRegsParamsCount());
2642  assert(!IsTailCall &&
2643  "Do not tail-call optimize if there is a byval argument.");
2644  passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
2645  FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(),
2646  VA);
2647  CCInfo.nextInRegsParam();
2648  continue;
2649  }
2650 
2651  // Promote the value if needed.
2652  switch (VA.getLocInfo()) {
2653  default:
2654  llvm_unreachable("Unknown loc info!");
2655  case CCValAssign::Full:
2656  if (VA.isRegLoc()) {
2657  if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
2658  (ValVT == MVT::f64 && LocVT == MVT::i64) ||
2659  (ValVT == MVT::i64 && LocVT == MVT::f64))
2660  Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
2661  else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
2663  Arg, DAG.getConstant(0, DL, MVT::i32));
2665  Arg, DAG.getConstant(1, DL, MVT::i32));
2666  if (!Subtarget.isLittle())
2667  std::swap(Lo, Hi);
2668  unsigned LocRegLo = VA.getLocReg();
2669  unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
2670  RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
2671  RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
2672  continue;
2673  }
2674  }
2675  break;
2676  case CCValAssign::BCvt:
2677  Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
2678  break;
2680  UseUpperBits = true;
2681  // Fallthrough
2682  case CCValAssign::SExt:
2683  Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg);
2684  break;
2686  UseUpperBits = true;
2687  // Fallthrough
2688  case CCValAssign::ZExt:
2689  Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg);
2690  break;
2692  UseUpperBits = true;
2693  // Fallthrough
2694  case CCValAssign::AExt:
2695  Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg);
2696  break;
2697  }
2698 
2699  if (UseUpperBits) {
2700  unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
2701  unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
2702  Arg = DAG.getNode(
2703  ISD::SHL, DL, VA.getLocVT(), Arg,
2704  DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
2705  }
2706 
2707  // Arguments that can be passed on register must be kept at
2708  // RegsToPass vector
2709  if (VA.isRegLoc()) {
2710  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2711  continue;
2712  }
2713 
2714  // Register can't get to this point...
2715  assert(VA.isMemLoc());
2716 
2717  // emit ISD::STORE whichs stores the
2718  // parameter value to a stack Location
2719  MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(),
2720  Chain, Arg, DL, IsTailCall, DAG));
2721  }
2722 
2723  // Transform all store nodes into one single node because all store
2724  // nodes are independent of each other.
2725  if (!MemOpChains.empty())
2726  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
2727 
2728  // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2729  // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2730  // node so that legalize doesn't hack it.
2731  bool IsPICCall = (ABI.IsN64() || IsPIC); // true if calls are translated to
2732  // jalr $25
2733  bool GlobalOrExternal = false, InternalLinkage = false, IsCallReloc = false;
2734  SDValue CalleeLo;
2735  EVT Ty = Callee.getValueType();
2736 
2737  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2738  if (IsPICCall) {
2739  const GlobalValue *Val = G->getGlobal();
2740  InternalLinkage = Val->hasInternalLinkage();
2741 
2742  if (InternalLinkage)
2743  Callee = getAddrLocal(G, DL, Ty, DAG, ABI.IsN32() || ABI.IsN64());
2744  else if (LargeGOT) {
2745  Callee = getAddrGlobalLargeGOT(G, DL, Ty, DAG, MipsII::MO_CALL_HI16,
2746  MipsII::MO_CALL_LO16, Chain,
2747  FuncInfo->callPtrInfo(Val));
2748  IsCallReloc = true;
2749  } else {
2750  Callee = getAddrGlobal(G, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
2751  FuncInfo->callPtrInfo(Val));
2752  IsCallReloc = true;
2753  }
2754  } else
2755  Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL,
2756  getPointerTy(DAG.getDataLayout()), 0,
2758  GlobalOrExternal = true;
2759  }
2760  else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2761  const char *Sym = S->getSymbol();
2762 
2763  if (!ABI.IsN64() && !IsPIC) // !N64 && static
2764  Callee = DAG.getTargetExternalSymbol(
2766  else if (LargeGOT) {
2767  Callee = getAddrGlobalLargeGOT(S, DL, Ty, DAG, MipsII::MO_CALL_HI16,
2768  MipsII::MO_CALL_LO16, Chain,
2769  FuncInfo->callPtrInfo(Sym));
2770  IsCallReloc = true;
2771  } else { // N64 || PIC
2772  Callee = getAddrGlobal(S, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
2773  FuncInfo->callPtrInfo(Sym));
2774  IsCallReloc = true;
2775  }
2776 
2777  GlobalOrExternal = true;
2778  }
2779 
2780  SmallVector<SDValue, 8> Ops(1, Chain);
2781  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2782 
2783  getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, InternalLinkage,
2784  IsCallReloc, CLI, Callee, Chain);
2785 
2786  if (IsTailCall)
2787  return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops);
2788 
2789  Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops);
2790  SDValue InFlag = Chain.getValue(1);
2791 
2792  // Create the CALLSEQ_END node.
2793  Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal,
2794  DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
2795  InFlag = Chain.getValue(1);
2796 
2797  // Handle result values, copying them out of physregs into vregs that we
2798  // return.
2799  return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
2800  InVals, CLI);
2801 }
2802 
2803 /// LowerCallResult - Lower the result values of a call into the
2804 /// appropriate copies out of appropriate physical registers.
2805 SDValue MipsTargetLowering::LowerCallResult(
2806  SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
2807  const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
2808  SmallVectorImpl<SDValue> &InVals,
2809  TargetLowering::CallLoweringInfo &CLI) const {
2810  // Assign locations to each value returned by this call.
2812  MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
2813  *DAG.getContext());
2814  CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI);
2815 
2816  // Copy all of the result registers out of their specified physreg.
2817  for (unsigned i = 0; i != RVLocs.size(); ++i) {
2818  CCValAssign &VA = RVLocs[i];
2819  assert(VA.isRegLoc() && "Can only return in registers!");
2820 
2821  SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(),
2822  RVLocs[i].getLocVT(), InFlag);
2823  Chain = Val.getValue(1);
2824  InFlag = Val.getValue(2);
2825 
2826  if (VA.isUpperBitsInLoc()) {
2827  unsigned ValSizeInBits = Ins[i].ArgVT.getSizeInBits();
2828  unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
2829  unsigned Shift =
2830  VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA;
2831  Val = DAG.getNode(
2832  Shift, DL, VA.getLocVT(), Val,
2833  DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
2834  }
2835 
2836  switch (VA.getLocInfo()) {
2837  default:
2838  llvm_unreachable("Unknown loc info!");
2839  case CCValAssign::Full:
2840  break;
2841  case CCValAssign::BCvt:
2842  Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
2843  break;
2844  case CCValAssign::AExt:
2846  Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2847  break;
2848  case CCValAssign::ZExt:
2850  Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val,
2851  DAG.getValueType(VA.getValVT()));
2852  Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2853  break;
2854  case CCValAssign::SExt:
2856  Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val,
2857  DAG.getValueType(VA.getValVT()));
2858  Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2859  break;
2860  }
2861 
2862  InVals.push_back(Val);
2863  }
2864 
2865  return Chain;
2866 }
2867 
2869  EVT ArgVT, SDLoc DL, SelectionDAG &DAG) {
2870  MVT LocVT = VA.getLocVT();
2871  EVT ValVT = VA.getValVT();
2872 
2873  // Shift into the upper bits if necessary.
2874  switch (VA.getLocInfo()) {
2875  default:
2876  break;
2879  case CCValAssign::ZExtUpper: {
2880  unsigned ValSizeInBits = ArgVT.getSizeInBits();
2881  unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
2882  unsigned Opcode =
2883  VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA;
2884  Val = DAG.getNode(
2885  Opcode, DL, VA.getLocVT(), Val,
2886  DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
2887  break;
2888  }
2889  }
2890 
2891  // If this is an value smaller than the argument slot size (32-bit for O32,
2892  // 64-bit for N32/N64), it has been promoted in some way to the argument slot
2893  // size. Extract the value and insert any appropriate assertions regarding
2894  // sign/zero extension.
2895  switch (VA.getLocInfo()) {
2896  default:
2897  llvm_unreachable("Unknown loc info!");
2898  case CCValAssign::Full:
2899  break;
2901  case CCValAssign::AExt:
2902  Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
2903  break;
2905  case CCValAssign::SExt:
2906  Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT));
2907  Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
2908  break;
2910  case CCValAssign::ZExt:
2911  Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT));
2912  Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
2913  break;
2914  case CCValAssign::BCvt:
2915  Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val);
2916  break;
2917  }
2918 
2919  return Val;
2920 }
2921 
2922 //===----------------------------------------------------------------------===//
2923 // Formal Arguments Calling Convention Implementation
2924 //===----------------------------------------------------------------------===//
2925 /// LowerFormalArguments - transform physical registers into virtual registers
2926 /// and generate load operations for arguments places on the stack.
2927 SDValue
2928 MipsTargetLowering::LowerFormalArguments(SDValue Chain,
2929  CallingConv::ID CallConv,
2930  bool IsVarArg,
2931  const SmallVectorImpl<ISD::InputArg> &Ins,
2932  SDLoc DL, SelectionDAG &DAG,
2933  SmallVectorImpl<SDValue> &InVals)
2934  const {
2935  MachineFunction &MF = DAG.getMachineFunction();
2936  MachineFrameInfo *MFI = MF.getFrameInfo();
2937  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2938 
2939  MipsFI->setVarArgsFrameIndex(0);
2940 
2941  // Used with vargs to acumulate store chains.
2942  std::vector<SDValue> OutChains;
2943 
2944  // Assign locations to all of the incoming arguments.
2946  MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
2947  *DAG.getContext());
2948  CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1);
2951 
2952  CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg);
2953  MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(),
2954  CCInfo.getInRegsParamsCount() > 0);
2955 
2956  unsigned CurArgIdx = 0;
2957  CCInfo.rewindByValRegsInfo();
2958 
2959  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2960  CCValAssign &VA = ArgLocs[i];
2961  if (Ins[i].isOrigArg()) {
2962  std::advance(FuncArg, Ins[i].getOrigArgIndex() - CurArgIdx);
2963  CurArgIdx = Ins[i].getOrigArgIndex();
2964  }
2965  EVT ValVT = VA.getValVT();
2966  ISD::ArgFlagsTy Flags = Ins[i].Flags;
2967  bool IsRegLoc = VA.isRegLoc();
2968 
2969  if (Flags.isByVal()) {
2970  assert(Ins[i].isOrigArg() && "Byval arguments cannot be implicit");
2971  unsigned FirstByValReg, LastByValReg;
2972  unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
2973  CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
2974 
2975  assert(Flags.getByValSize() &&
2976  "ByVal args of size 0 should have been ignored by front-end.");
2977  assert(ByValIdx < CCInfo.getInRegsParamsCount());
2978  copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg,
2979  FirstByValReg, LastByValReg, VA, CCInfo);
2980  CCInfo.nextInRegsParam();
2981  continue;
2982  }
2983 
2984  // Arguments stored on registers
2985  if (IsRegLoc) {
2986  MVT RegVT = VA.getLocVT();
2987  unsigned ArgReg = VA.getLocReg();
2988  const TargetRegisterClass *RC = getRegClassFor(RegVT);
2989 
2990  // Transform the arguments stored on
2991  // physical registers into virtual ones
2992  unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC);
2993  SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
2994 
2995  ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG);
2996 
2997  // Handle floating point arguments passed in integer registers and
2998  // long double arguments passed in floating point registers.
2999  if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
3000  (RegVT == MVT::i64 && ValVT == MVT::f64) ||
3001  (RegVT == MVT::f64 && ValVT == MVT::i64))
3002  ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue);
3003  else if (ABI.IsO32() && RegVT == MVT::i32 &&
3004  ValVT == MVT::f64) {
3005  unsigned Reg2 = addLiveIn(DAG.getMachineFunction(),
3006  getNextIntArgReg(ArgReg), RC);
3007  SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT);
3008  if (!Subtarget.isLittle())
3009  std::swap(ArgValue, ArgValue2);
3010  ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64,
3011  ArgValue, ArgValue2);
3012  }
3013 
3014  InVals.push_back(ArgValue);
3015  } else { // VA.isRegLoc()
3016  MVT LocVT = VA.getLocVT();
3017 
3018  if (ABI.IsO32()) {
3019  // We ought to be able to use LocVT directly but O32 sets it to i32
3020  // when allocating floating point values to integer registers.
3021  // This shouldn't influence how we load the value into registers unless
3022  // we are targetting softfloat.
3024  LocVT = VA.getValVT();
3025  }
3026 
3027  // sanity check
3028  assert(VA.isMemLoc());
3029 
3030  // The stack pointer offset is relative to the caller stack frame.
3031  int FI = MFI->CreateFixedObject(LocVT.getSizeInBits() / 8,
3032  VA.getLocMemOffset(), true);
3033 
3034  // Create load nodes to retrieve arguments from the stack
3035  SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3036  SDValue ArgValue = DAG.getLoad(LocVT, DL, Chain, FIN,
3038  false, false, false, 0);
3039  OutChains.push_back(ArgValue.getValue(1));
3040 
3041  ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG);
3042 
3043  InVals.push_back(ArgValue);
3044  }
3045  }
3046 
3047  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3048  // The mips ABIs for returning structs by value requires that we copy
3049  // the sret argument into $v0 for the return. Save the argument into
3050  // a virtual register so that we can access it from the return points.
3051  if (Ins[i].Flags.isSRet()) {
3052  unsigned Reg = MipsFI->getSRetReturnReg();
3053  if (!Reg) {
3054  Reg = MF.getRegInfo().createVirtualRegister(
3056  MipsFI->setSRetReturnReg(Reg);
3057  }
3058  SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]);
3059  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
3060  break;
3061  }
3062  }
3063 
3064  if (IsVarArg)
3065  writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo);
3066 
3067  // All stores are grouped in one node to allow the matching between
3068  // the size of Ins and InVals. This only happens when on varg functions
3069  if (!OutChains.empty()) {
3070  OutChains.push_back(Chain);
3071  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
3072  }
3073 
3074  return Chain;
3075 }
3076 
3077 //===----------------------------------------------------------------------===//
3078 // Return Value Calling Convention Implementation
3079 //===----------------------------------------------------------------------===//
3080 
3081 bool
3082 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
3083  MachineFunction &MF, bool IsVarArg,
3084  const SmallVectorImpl<ISD::OutputArg> &Outs,
3085  LLVMContext &Context) const {
3087  MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
3088  return CCInfo.CheckReturn(Outs, RetCC_Mips);
3089 }
3090 
3091 bool
3092 MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
3094  if (Type == MVT::i32)
3095  return true;
3096  }
3097  return IsSigned;
3098 }
3099 
3100 SDValue
3101 MipsTargetLowering::LowerReturn(SDValue Chain,
3102  CallingConv::ID CallConv, bool IsVarArg,
3103  const SmallVectorImpl<ISD::OutputArg> &Outs,
3104  const SmallVectorImpl<SDValue> &OutVals,
3105  SDLoc DL, SelectionDAG &DAG) const {
3106  // CCValAssign - represent the assignment of
3107  // the return value to a location
3109  MachineFunction &MF = DAG.getMachineFunction();
3110 
3111  // CCState - Info about the registers and stack slot.
3112  MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
3113 
3114  // Analyze return values.
3115  CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
3116 
3117  SDValue Flag;
3118  SmallVector<SDValue, 4> RetOps(1, Chain);
3119 
3120  // Copy the result values into the output registers.
3121  for (unsigned i = 0; i != RVLocs.size(); ++i) {
3122  SDValue Val = OutVals[i];
3123  CCValAssign &VA = RVLocs[i];
3124  assert(VA.isRegLoc() && "Can only return in registers!");
3125  bool UseUpperBits = false;
3126 
3127  switch (VA.getLocInfo()) {
3128  default:
3129  llvm_unreachable("Unknown loc info!");
3130  case CCValAssign::Full:
3131  break;
3132  case CCValAssign::BCvt:
3133  Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val);
3134  break;
3136  UseUpperBits = true;
3137  // Fallthrough
3138  case CCValAssign::AExt:
3139  Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val);
3140  break;
3142  UseUpperBits = true;
3143  // Fallthrough
3144  case CCValAssign::ZExt:
3145  Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val);
3146  break;
3148  UseUpperBits = true;
3149  // Fallthrough
3150  case CCValAssign::SExt:
3151  Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val);
3152  break;
3153  }
3154 
3155  if (UseUpperBits) {
3156  unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
3157  unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3158  Val = DAG.getNode(
3159  ISD::SHL, DL, VA.getLocVT(), Val,
3160  DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3161  }
3162 
3163  Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag);
3164 
3165  // Guarantee that all emitted copies are stuck together with flags.
3166  Flag = Chain.getValue(1);
3167  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3168  }
3169 
3170  // The mips ABIs for returning structs by value requires that we copy
3171  // the sret argument into $v0 for the return. We saved the argument into
3172  // a virtual register in the entry block, so now we copy the value out
3173  // and into $v0.
3174  if (MF.getFunction()->hasStructRetAttr()) {
3175  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3176  unsigned Reg = MipsFI->getSRetReturnReg();
3177 
3178  if (!Reg)
3179  llvm_unreachable("sret virtual register not created in the entry block");
3180  SDValue Val =
3181  DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout()));
3182  unsigned V0 = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
3183 
3184  Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag);
3185  Flag = Chain.getValue(1);
3186  RetOps.push_back(DAG.getRegister(V0, getPointerTy(DAG.getDataLayout())));
3187  }
3188 
3189  RetOps[0] = Chain; // Update chain.
3190 
3191  // Add the flag if we have it.
3192  if (Flag.getNode())
3193  RetOps.push_back(Flag);
3194 
3195  // Return on Mips is always a "jr $ra"
3196  return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps);
3197 }
3198 
3199 //===----------------------------------------------------------------------===//
3200 // Mips Inline Assembly Support
3201 //===----------------------------------------------------------------------===//
3202 
3203 /// getConstraintType - Given a constraint letter, return the type of
3204 /// constraint it is for this target.
3206 MipsTargetLowering::getConstraintType(StringRef Constraint) const {
3207  // Mips specific constraints
3208  // GCC config/mips/constraints.md
3209  //
3210  // 'd' : An address register. Equivalent to r
3211  // unless generating MIPS16 code.
3212  // 'y' : Equivalent to r; retained for
3213  // backwards compatibility.
3214  // 'c' : A register suitable for use in an indirect
3215  // jump. This will always be $25 for -mabicalls.
3216  // 'l' : The lo register. 1 word storage.
3217  // 'x' : The hilo register pair. Double word storage.
3218  if (Constraint.size() == 1) {
3219  switch (Constraint[0]) {
3220  default : break;
3221  case 'd':
3222  case 'y':
3223  case 'f':
3224  case 'c':
3225  case 'l':
3226  case 'x':
3227  return C_RegisterClass;
3228  case 'R':
3229  return C_Memory;
3230  }
3231  }
3232 
3233  if (Constraint == "ZC")
3234  return C_Memory;
3235 
3236  return TargetLowering::getConstraintType(Constraint);
3237 }
3238 
3239 /// Examine constraint type and operand type and determine a weight value.
3240 /// This object must already have been set up with the operand type
3241 /// and the current alternative constraint selected.
3243 MipsTargetLowering::getSingleConstraintMatchWeight(
3244  AsmOperandInfo &info, const char *constraint) const {
3245  ConstraintWeight weight = CW_Invalid;
3246  Value *CallOperandVal = info.CallOperandVal;
3247  // If we don't have a value, we can't do a match,
3248  // but allow it at the lowest weight.
3249  if (!CallOperandVal)
3250  return CW_Default;
3251  Type *type = CallOperandVal->getType();
3252  // Look at the constraint type.
3253  switch (*constraint) {
3254  default:
3255  weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3256  break;
3257  case 'd':
3258  case 'y':
3259  if (type->isIntegerTy())
3260  weight = CW_Register;
3261  break;
3262  case 'f': // FPU or MSA register
3263  if (Subtarget.hasMSA() && type->isVectorTy() &&
3264  cast<VectorType>(type)->getBitWidth() == 128)
3265  weight = CW_Register;
3266  else if (type->isFloatTy())
3267  weight = CW_Register;
3268  break;
3269  case 'c': // $25 for indirect jumps
3270  case 'l': // lo register
3271  case 'x': // hilo register pair
3272  if (type->isIntegerTy())
3273  weight = CW_SpecificReg;
3274  break;
3275  case 'I': // signed 16 bit immediate
3276  case 'J': // integer zero
3277  case 'K': // unsigned 16 bit immediate
3278  case 'L': // signed 32 bit immediate where lower 16 bits are 0
3279  case 'N': // immediate in the range of -65535 to -1 (inclusive)
3280  case 'O': // signed 15 bit immediate (+- 16383)
3281  case 'P': // immediate in the range of 65535 to 1 (inclusive)
3282  if (isa<ConstantInt>(CallOperandVal))
3283  weight = CW_Constant;
3284  break;
3285  case 'R':
3286  weight = CW_Memory;
3287  break;
3288  }
3289  return weight;
3290 }
3291 
3292 /// This is a helper function to parse a physical register string and split it
3293 /// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag
3294 /// that is returned indicates whether parsing was successful. The second flag
3295 /// is true if the numeric part exists.
3296 static std::pair<bool, bool> parsePhysicalReg(StringRef C, StringRef &Prefix,
3297  unsigned long long &Reg) {
3298  if (C.front() != '{' || C.back() != '}')
3299  return std::make_pair(false, false);
3300 
3301  // Search for the first numeric character.
3302  StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1;
3303  I = std::find_if(B, E, std::ptr_fun(isdigit));
3304 
3305  Prefix = StringRef(B, I - B);
3306 
3307  // The second flag is set to false if no numeric characters were found.
3308  if (I == E)
3309  return std::make_pair(true, false);
3310 
3311  // Parse the numeric characters.
3312  return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg),
3313  true);
3314 }
3315 
3316 std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering::
3317 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const {
3318  const TargetRegisterInfo *TRI =
3320  const TargetRegisterClass *RC;
3321  StringRef Prefix;
3322  unsigned long long Reg;
3323 
3324  std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg);
3325 
3326  if (!R.first)
3327  return std::make_pair(0U, nullptr);
3328 
3329  if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo.
3330  // No numeric characters follow "hi" or "lo".
3331  if (R.second)
3332  return std::make_pair(0U, nullptr);
3333 
3334  RC = TRI->getRegClass(Prefix == "hi" ?
3335  Mips::HI32RegClassID : Mips::LO32RegClassID);
3336  return std::make_pair(*(RC->begin()), RC);
3337  } else if (Prefix.startswith("$msa")) {
3338  // Parse $msa(ir|csr|access|save|modify|request|map|unmap)
3339 
3340  // No numeric characters follow the name.
3341  if (R.second)
3342  return std::make_pair(0U, nullptr);
3343 
3345  .Case("$msair", Mips::MSAIR)
3346  .Case("$msacsr", Mips::MSACSR)
3347  .Case("$msaaccess", Mips::MSAAccess)
3348  .Case("$msasave", Mips::MSASave)
3349  .Case("$msamodify", Mips::MSAModify)
3350  .Case("$msarequest", Mips::MSARequest)
3351  .Case("$msamap", Mips::MSAMap)
3352  .Case("$msaunmap", Mips::MSAUnmap)
3353  .Default(0);
3354 
3355  if (!Reg)
3356  return std::make_pair(0U, nullptr);
3357 
3358  RC = TRI->getRegClass(Mips::MSACtrlRegClassID);
3359  return std::make_pair(Reg, RC);
3360  }
3361 
3362  if (!R.second)
3363  return std::make_pair(0U, nullptr);
3364 
3365  if (Prefix == "$f") { // Parse $f0-$f31.
3366  // If the size of FP registers is 64-bit or Reg is an even number, select
3367  // the 64-bit register class. Otherwise, select the 32-bit register class.
3368  if (VT == MVT::Other)
3369  VT = (Subtarget.isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32;
3370 
3371  RC = getRegClassFor(VT);
3372 
3373  if (RC == &Mips::AFGR64RegClass) {
3374  assert(Reg % 2 == 0);
3375  Reg >>= 1;
3376  }
3377  } else if (Prefix == "$fcc") // Parse $fcc0-$fcc7.
3378  RC = TRI->getRegClass(Mips::FCCRegClassID);
3379  else if (Prefix == "$w") { // Parse $w0-$w31.
3380  RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT);
3381  } else { // Parse $0-$31.
3382  assert(Prefix == "$");
3383  RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT);
3384  }
3385 
3386  assert(Reg < RC->getNumRegs());
3387  return std::make_pair(*(RC->begin() + Reg), RC);
3388 }
3389 
3390 /// Given a register class constraint, like 'r', if this corresponds directly
3391 /// to an LLVM register class, return a register of 0 and the register class
3392 /// pointer.
3393 std::pair<unsigned, const TargetRegisterClass *>
3394 MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3395  StringRef Constraint,
3396  MVT VT) const {
3397  if (Constraint.size() == 1) {
3398  switch (Constraint[0]) {
3399  case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
3400  case 'y': // Same as 'r'. Exists for compatibility.
3401  case 'r':
3402  if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
3403  if (Subtarget.inMips16Mode())
3404  return std::make_pair(0U, &Mips::CPU16RegsRegClass);
3405  return std::make_pair(0U, &Mips::GPR32RegClass);
3406  }
3407  if (VT == MVT::i64 && !Subtarget.isGP64bit())
3408  return std::make_pair(0U, &Mips::GPR32RegClass);
3409  if (VT == MVT::i64 && Subtarget.isGP64bit())
3410  return std::make_pair(0U, &Mips::GPR64RegClass);
3411  // This will generate an error message
3412  return std::make_pair(0U, nullptr);
3413  case 'f': // FPU or MSA register
3414  if (VT == MVT::v16i8)
3415  return std::make_pair(0U, &Mips::MSA128BRegClass);
3416  else if (VT == MVT::v8i16 || VT == MVT::v8f16)
3417  return std::make_pair(0U, &Mips::MSA128HRegClass);
3418  else if (VT == MVT::v4i32 || VT == MVT::v4f32)
3419  return std::make_pair(0U, &Mips::MSA128WRegClass);
3420  else if (VT == MVT::v2i64 || VT == MVT::v2f64)
3421  return std::make_pair(0U, &Mips::MSA128DRegClass);
3422  else if (VT == MVT::f32)
3423  return std::make_pair(0U, &Mips::FGR32RegClass);
3424  else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) {
3425  if (Subtarget.isFP64bit())
3426  return std::make_pair(0U, &Mips::FGR64RegClass);
3427  return std::make_pair(0U, &Mips::AFGR64RegClass);
3428  }
3429  break;
3430  case 'c': // register suitable for indirect jump
3431  if (VT == MVT::i32)
3432  return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass);
3433  assert(VT == MVT::i64 && "Unexpected type.");
3434  return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass);
3435  case 'l': // register suitable for indirect jump
3436  if (VT == MVT::i32)
3437  return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass);
3438  return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass);
3439  case 'x': // register suitable for indirect jump
3440  // Fixme: Not triggering the use of both hi and low
3441  // This will generate an error message
3442  return std::make_pair(0U, nullptr);
3443  }
3444  }
3445 
3446  std::pair<unsigned, const TargetRegisterClass *> R;
3447  R = parseRegForInlineAsmConstraint(Constraint, VT);
3448 
3449  if (R.second)
3450  return R;
3451 
3452  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3453 }
3454 
3455 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3456 /// vector. If it is invalid, don't add anything to Ops.
3457 void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3458  std::string &Constraint,
3459  std::vector<SDValue>&Ops,
3460  SelectionDAG &DAG) const {
3461  SDLoc DL(Op);
3462  SDValue Result;
3463 
3464  // Only support length 1 constraints for now.
3465  if (Constraint.length() > 1) return;
3466 
3467  char ConstraintLetter = Constraint[0];
3468  switch (ConstraintLetter) {
3469  default: break; // This will fall through to the generic implementation
3470  case 'I': // Signed 16 bit constant
3471  // If this fails, the parent routine will give an error
3472  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3473  EVT Type = Op.getValueType();
3474  int64_t Val = C->getSExtValue();
3475  if (isInt<16>(Val)) {
3476  Result = DAG.getTargetConstant(Val, DL, Type);
3477  break;
3478  }
3479  }
3480  return;
3481  case 'J': // integer zero
3482  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3483  EVT Type = Op.getValueType();
3484  int64_t Val = C->getZExtValue();
3485  if (Val == 0) {
3486  Result = DAG.getTargetConstant(0, DL, Type);
3487  break;
3488  }
3489  }
3490  return;
3491  case 'K': // unsigned 16 bit immediate
3492  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3493  EVT Type = Op.getValueType();
3494  uint64_t Val = (uint64_t)C->getZExtValue();
3495  if (isUInt<16>(Val)) {
3496  Result = DAG.getTargetConstant(Val, DL, Type);
3497  break;
3498  }
3499  }
3500  return;
3501  case 'L': // signed 32 bit immediate where lower 16 bits are 0
3502  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3503  EVT Type = Op.getValueType();
3504  int64_t Val = C->getSExtValue();
3505  if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
3506  Result = DAG.getTargetConstant(Val, DL, Type);
3507  break;
3508  }
3509  }
3510  return;
3511  case 'N': // immediate in the range of -65535 to -1 (inclusive)
3512  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3513  EVT Type = Op.getValueType();
3514  int64_t Val = C->getSExtValue();
3515  if ((Val >= -65535) && (Val <= -1)) {
3516  Result = DAG.getTargetConstant(Val, DL, Type);
3517  break;
3518  }
3519  }
3520  return;
3521  case 'O': // signed 15 bit immediate
3522  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3523  EVT Type = Op.getValueType();
3524  int64_t Val = C->getSExtValue();
3525  if ((isInt<15>(Val))) {
3526  Result = DAG.getTargetConstant(Val, DL, Type);
3527  break;
3528  }
3529  }
3530  return;
3531  case 'P': // immediate in the range of 1 to 65535 (inclusive)
3532  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3533  EVT Type = Op.getValueType();
3534  int64_t Val = C->getSExtValue();
3535  if ((Val <= 65535) && (Val >= 1)) {
3536  Result = DAG.getTargetConstant(Val, DL, Type);
3537  break;
3538  }
3539  }
3540  return;
3541  }
3542 
3543  if (Result.getNode()) {
3544  Ops.push_back(Result);
3545  return;
3546  }
3547 
3548  TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3549 }
3550 
3551 bool MipsTargetLowering::isLegalAddressingMode(const DataLayout &DL,
3552  const AddrMode &AM, Type *Ty,
3553  unsigned AS) const {
3554  // No global is ever allowed as a base.
3555  if (AM.BaseGV)
3556  return false;
3557 
3558  switch (AM.Scale) {
3559  case 0: // "r+i" or just "i", depending on HasBaseReg.
3560  break;
3561  case 1:
3562  if (!AM.HasBaseReg) // allow "r+i".
3563  break;
3564  return false; // disallow "r+r" or "r+r+i".
3565  default:
3566  return false;
3567  }
3568 
3569  return true;
3570 }
3571 
3572 bool
3573 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
3574  // The Mips target isn't yet aware of offsets.
3575  return false;
3576 }
3577 
3578 EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
3579  unsigned SrcAlign,
3580  bool IsMemset, bool ZeroMemset,
3581  bool MemcpyStrSrc,
3582  MachineFunction &MF) const {
3583  if (Subtarget.hasMips64())
3584  return MVT::i64;
3585 
3586  return MVT::i32;
3587 }
3588 
3589 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3590  if (VT != MVT::f32 && VT != MVT::f64)
3591  return false;
3592  if (Imm.isNegZero())
3593  return false;
3594  return Imm.isZero();
3595 }
3596 
3597 unsigned MipsTargetLowering::getJumpTableEncoding() const {
3598  if (ABI.IsN64())
3600 
3602 }
3603 
3604 bool MipsTargetLowering::useSoftFloat() const {
3605  return Subtarget.useSoftFloat();
3606 }
3607 
3608 void MipsTargetLowering::copyByValRegs(
3609  SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains, SelectionDAG &DAG,
3610  const ISD::ArgFlagsTy &Flags, SmallVectorImpl<SDValue> &InVals,
3611  const Argument *FuncArg, unsigned FirstReg, unsigned LastReg,
3612  const CCValAssign &VA, MipsCCState &State) const {
3613  MachineFunction &MF = DAG.getMachineFunction();
3614  MachineFrameInfo *MFI = MF.getFrameInfo();
3615  unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes();
3616  unsigned NumRegs = LastReg - FirstReg;
3617  unsigned RegAreaSize = NumRegs * GPRSizeInBytes;
3618  unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize);
3619  int FrameObjOffset;
3620  ArrayRef<MCPhysReg> ByValArgRegs = ABI.GetByValArgRegs();
3621 
3622  if (RegAreaSize)
3623  FrameObjOffset =
3625  (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes);
3626  else
3627  FrameObjOffset = VA.getLocMemOffset();
3628 
3629  // Create frame object.
3630  EVT PtrTy = getPointerTy(DAG.getDataLayout());
3631  int FI = MFI->CreateFixedObject(FrameObjSize, FrameObjOffset, true);
3632  SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
3633  InVals.push_back(FIN);
3634 
3635  if (!NumRegs)
3636  return;
3637 
3638  // Copy arg registers.
3639  MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8);
3640  const TargetRegisterClass *RC = getRegClassFor(RegTy);
3641 
3642  for (unsigned I = 0; I < NumRegs; ++I) {
3643  unsigned ArgReg = ByValArgRegs[FirstReg + I];
3644  unsigned VReg = addLiveIn(MF, ArgReg, RC);
3645  unsigned Offset = I * GPRSizeInBytes;
3646  SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
3647  DAG.getConstant(Offset, DL, PtrTy));
3648  SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
3649  StorePtr, MachinePointerInfo(FuncArg, Offset),
3650  false, false, 0);
3651  OutChains.push_back(Store);
3652  }
3653 }
3654 
3655 // Copy byVal arg to registers and stack.
3656 void MipsTargetLowering::passByValArg(
3657  SDValue Chain, SDLoc DL,
3658  std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
3659  SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
3660  MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg,
3661  unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle,
3662  const CCValAssign &VA) const {
3663  unsigned ByValSizeInBytes = Flags.getByValSize();
3664  unsigned OffsetInBytes = 0; // From beginning of struct
3665  unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
3666  unsigned Alignment = std::min(Flags.getByValAlign(), RegSizeInBytes);
3667  EVT PtrTy = getPointerTy(DAG.getDataLayout()),
3668  RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
3669  unsigned NumRegs = LastReg - FirstReg;
3670 
3671  if (NumRegs) {
3672  const ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs();
3673  bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes);
3674  unsigned I = 0;
3675 
3676  // Copy words to registers.
3677  for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) {
3678  SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3679  DAG.getConstant(OffsetInBytes, DL, PtrTy));
3680  SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr,
3681  MachinePointerInfo(), false, false, false,
3682  Alignment);
3683  MemOpChains.push_back(LoadVal.getValue(1));
3684  unsigned ArgReg = ArgRegs[FirstReg + I];
3685  RegsToPass.push_back(std::make_pair(ArgReg, LoadVal));
3686  }
3687 
3688  // Return if the struct has been fully copied.
3689  if (ByValSizeInBytes == OffsetInBytes)
3690  return;
3691 
3692  // Copy the remainder of the byval argument with sub-word loads and shifts.
3693  if (LeftoverBytes) {
3694  SDValue Val;
3695 
3696  for (unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0;
3697  OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) {
3698  unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes;
3699 
3700  if (RemainingSizeInBytes < LoadSizeInBytes)
3701  continue;
3702 
3703  // Load subword.
3704  SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3705  DAG.getConstant(OffsetInBytes, DL,
3706  PtrTy));
3707  SDValue LoadVal = DAG.getExtLoad(
3708  ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(),
3709  MVT::getIntegerVT(LoadSizeInBytes * 8), false, false, false,
3710  Alignment);
3711  MemOpChains.push_back(LoadVal.getValue(1));
3712 
3713  // Shift the loaded value.
3714  unsigned Shamt;
3715 
3716  if (isLittle)
3717  Shamt = TotalBytesLoaded * 8;
3718  else
3719  Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8;
3720 
3721  SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal,
3722  DAG.getConstant(Shamt, DL, MVT::i32));
3723 
3724  if (Val.getNode())
3725  Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift);
3726  else
3727  Val = Shift;
3728 
3729  OffsetInBytes += LoadSizeInBytes;
3730  TotalBytesLoaded += LoadSizeInBytes;
3731  Alignment = std::min(Alignment, LoadSizeInBytes);
3732  }
3733 
3734  unsigned ArgReg = ArgRegs[FirstReg + I];
3735  RegsToPass.push_back(std::make_pair(ArgReg, Val));
3736  return;
3737  }
3738  }
3739 
3740  // Copy remainder of byval arg to it with memcpy.
3741  unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes;
3742  SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3743  DAG.getConstant(OffsetInBytes, DL, PtrTy));
3744  SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
3745  DAG.getIntPtrConstant(VA.getLocMemOffset(), DL));
3746  Chain = DAG.getMemcpy(Chain, DL, Dst, Src,
3747  DAG.getConstant(MemCpySize, DL, PtrTy),
3748  Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false,
3749  /*isTailCall=*/false,
3751  MemOpChains.push_back(Chain);
3752 }
3753 
3754 void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
3755  SDValue Chain, SDLoc DL,
3756  SelectionDAG &DAG,
3757  CCState &State) const {
3758  const ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs();
3759  unsigned Idx = State.getFirstUnallocated(ArgRegs);
3760  unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
3761  MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
3762  const TargetRegisterClass *RC = getRegClassFor(RegTy);
3763  MachineFunction &MF = DAG.getMachineFunction();
3764  MachineFrameInfo *MFI = MF.getFrameInfo();
3765  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3766 
3767  // Offset of the first variable argument from stack pointer.
3768  int VaArgOffset;
3769 
3770  if (ArgRegs.size() == Idx)
3771  VaArgOffset =
3772  RoundUpToAlignment(State.getNextStackOffset(), RegSizeInBytes);
3773  else {
3774  VaArgOffset =
3776  (int)(RegSizeInBytes * (ArgRegs.size() - Idx));
3777  }
3778 
3779  // Record the frame index of the first variable argument
3780  // which is a value necessary to VASTART.
3781  int FI = MFI->CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
3782  MipsFI->setVarArgsFrameIndex(FI);
3783 
3784  // Copy the integer registers that have not been used for argument passing
3785  // to the argument register save area. For O32, the save area is allocated
3786  // in the caller's stack frame, while for N32/64, it is allocated in the
3787  // callee's stack frame.
3788  for (unsigned I = Idx; I < ArgRegs.size();
3789  ++I, VaArgOffset += RegSizeInBytes) {
3790  unsigned Reg = addLiveIn(MF, ArgRegs[I], RC);
3791  SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy);
3792  FI = MFI->CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
3793  SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3794  SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff,
3795  MachinePointerInfo(), false, false, 0);
3796  cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(
3797  (Value *)nullptr);
3798  OutChains.push_back(Store);
3799  }
3800 }
3801 
3802 void MipsTargetLowering::HandleByVal(CCState *State, unsigned &Size,
3803  unsigned Align) const {
3805 
3806  assert(Size && "Byval argument's size shouldn't be 0.");
3807 
3808  Align = std::min(Align, TFL->getStackAlignment());
3809 
3810  unsigned FirstReg = 0;
3811  unsigned NumRegs = 0;
3812 
3813  if (State->getCallingConv() != CallingConv::Fast) {
3814  unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
3815  const ArrayRef<MCPhysReg> IntArgRegs = ABI.GetByValArgRegs();
3816  // FIXME: The O32 case actually describes no shadow registers.
3817  const MCPhysReg *ShadowRegs =
3818  ABI.IsO32() ? IntArgRegs.data() : Mips64DPRegs;
3819 
3820  // We used to check the size as well but we can't do that anymore since
3821  // CCState::HandleByVal() rounds up the size after calling this function.
3822  assert(!(Align % RegSizeInBytes) &&
3823  "Byval argument's alignment should be a multiple of"
3824  "RegSizeInBytes.");
3825 
3826  FirstReg = State->getFirstUnallocated(IntArgRegs);
3827 
3828  // If Align > RegSizeInBytes, the first arg register must be even.
3829  // FIXME: This condition happens to do the right thing but it's not the
3830  // right way to test it. We want to check that the stack frame offset
3831  // of the register is aligned.
3832  if ((Align > RegSizeInBytes) && (FirstReg % 2)) {
3833  State->AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]);
3834  ++FirstReg;
3835  }
3836 
3837  // Mark the registers allocated.
3838  Size = RoundUpToAlignment(Size, RegSizeInBytes);
3839  for (unsigned I = FirstReg; Size > 0 && (I < IntArgRegs.size());
3840  Size -= RegSizeInBytes, ++I, ++NumRegs)
3841  State->AllocateReg(IntArgRegs[I], ShadowRegs[I]);
3842  }
3843 
3844  State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs);
3845 }
3846 
3848 MipsTargetLowering::emitPseudoSELECT(MachineInstr *MI, MachineBasicBlock *BB,
3849  bool isFPCmp, unsigned Opc) const {
3850  assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) &&
3851  "Subtarget already supports SELECT nodes with the use of"
3852  "conditional-move instructions.");
3853 
3854  const TargetInstrInfo *TII =
3856  DebugLoc DL = MI->getDebugLoc();
3857 
3858  // To "insert" a SELECT instruction, we actually have to insert the
3859  // diamond control-flow pattern. The incoming instruction knows the
3860  // destination vreg to set, the condition code register to branch on, the
3861  // true/false values to select between, and a branch opcode to use.
3862  const BasicBlock *LLVM_BB = BB->getBasicBlock();
3863  MachineFunction::iterator It = BB;
3864  ++It;
3865 
3866  // thisMBB:
3867  // ...
3868  // TrueVal = ...
3869  // setcc r1, r2, r3
3870  // bNE r1, r0, copy1MBB
3871  // fallthrough --> copy0MBB
3872  MachineBasicBlock *thisMBB = BB;
3873  MachineFunction *F = BB->getParent();
3874  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
3875  MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
3876  F->insert(It, copy0MBB);
3877  F->insert(It, sinkMBB);
3878 
3879  // Transfer the remainder of BB and its successor edges to sinkMBB.
3880  sinkMBB->splice(sinkMBB->begin(), BB,
3881  std::next(MachineBasicBlock::iterator(MI)), BB->end());
3882  sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
3883 
3884  // Next, add the true and fallthrough blocks as its successors.
3885  BB->addSuccessor(copy0MBB);
3886  BB->addSuccessor(sinkMBB);
3887 
3888  if (isFPCmp) {
3889  // bc1[tf] cc, sinkMBB
3890  BuildMI(BB, DL, TII->get(Opc))
3891  .addReg(MI->getOperand(1).getReg())
3892  .addMBB(sinkMBB);
3893  } else {
3894  // bne rs, $0, sinkMBB
3895  BuildMI(BB, DL, TII->get(Opc))
3896  .addReg(MI->getOperand(1).getReg())
3897  .addReg(Mips::ZERO)
3898  .addMBB(sinkMBB);
3899  }
3900 
3901  // copy0MBB:
3902  // %FalseValue = ...
3903  // # fallthrough to sinkMBB
3904  BB = copy0MBB;
3905 
3906  // Update machine-CFG edges
3907  BB->addSuccessor(sinkMBB);
3908 
3909  // sinkMBB:
3910  // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
3911  // ...
3912  BB = sinkMBB;
3913 
3914  BuildMI(*BB, BB->begin(), DL,
3915  TII->get(Mips::PHI), MI->getOperand(0).getReg())
3916  .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB)
3917  .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB);
3918 
3919  MI->eraseFromParent(); // The pseudo instruction is gone now.
3920 
3921  return BB;
3922 }
3923 
3924 // FIXME? Maybe this could be a TableGen attribute on some registers and
3925 // this table could be generated automatically from RegInfo.
3926 unsigned MipsTargetLowering::getRegisterByName(const char* RegName, EVT VT,
3927  SelectionDAG &DAG) const {
3928  // Named registers is expected to be fairly rare. For now, just support $28
3929  // since the linux kernel uses it.
3930  if (Subtarget.isGP64bit()) {
3931  unsigned Reg = StringSwitch<unsigned>(RegName)
3932  .Case("$28", Mips::GP_64)
3933  .Default(0);
3934  if (Reg)
3935  return Reg;
3936  } else {
3937  unsigned Reg = StringSwitch<unsigned>(RegName)
3938  .Case("$28", Mips::GP)
3939  .Default(0);
3940  if (Reg)
3941  return Reg;
3942  }
3943  report_fatal_error("Invalid register name global variable");
3944 }
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:276
const MipsTargetLowering * createMipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
static unsigned getBitWidth(Type *Ty, const DataLayout &DL)
Returns the bitwidth of the given scalar or pointer type (if unknown returns 0).
void setFrameAddressIsTaken(bool T)
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasExtractInsert)
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:477
static MVT getIntegerVT(unsigned BitWidth)
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:104
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
SDValue getValue(unsigned R) const
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
MVT getValVT() const
const char * getSymbol() const
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
unsigned GetCalleeAllocdArgSizeInBytes(CallingConv::ID CC) const
Obtain the size of the area allocated by the callee for arguments.
Definition: MipsABIInfo.cpp:42
LLVMContext * getContext() const
Definition: SelectionDAG.h:289
LLVM Argument representation.
Definition: Argument.h:35
SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:522
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, SDLoc DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd)...
Definition: SelectionDAG.h:646
const MipsSubtarget & Subtarget
STATISTIC(NumFunctions,"Total number of functions")
size_t size() const
size - Get the string size.
Definition: StringRef.h:113
static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA, EVT ArgVT, SDLoc DL, SelectionDAG &DAG)
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:554
LocInfo getLocInfo() const
static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG, bool IsLittle)
MO_TLSLDM - Represents the offset into the global offset table at which.
Definition: MipsBaseInfo.h:64
static MVT getVectorVT(MVT VT, unsigned NumElements)
const MipsTargetLowering * createMips16TargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
Create MipsTargetLowering objects.
static MachinePointerInfo getJumpTable()
getJumpTable - Return a MachinePointerInfo record that refers to a jump table entry.
unsigned EnableFastISel
EnableFastISel - This flag enables fast-path instruction selection which trades away generated code q...
const TargetMachine & getTargetMachine() const
static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
MO_GOT_HI16/LO16, MO_CALL_HI16/LO16 - Relocations used for large GOTs.
Definition: MipsBaseInfo.h:90
SDValue getMergeValues(ArrayRef< SDValue > Ops, SDLoc dl)
Create a MERGE_VALUES node from the given operands.
static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
MO_TLSGD - Represents the offset into the global offset table at which.
Definition: MipsBaseInfo.h:59
unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
bool getAsUnsignedInteger(StringRef Str, unsigned Radix, unsigned long long &Result)
Helper functions for StringRef::getAsInteger.
Definition: StringRef.cpp:339
MipsTargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain...
Definition: ISDOpcodes.h:585
const GlobalValue * getGlobal() const
CallingConv::ID getCallingConv() const
const MipsInstrInfo * getInstrInfo() const override
static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool HasExtractInsert)
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Type * getTypeForEVT(LLVMContext &Context) const
getTypeForEVT - This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:181
unsigned getSizeInBits() const
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
unsigned getByValSize() const
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
unsigned getValueSizeInBits() const
Returns the size of the value in bits.
A debug info location.
Definition: DebugLoc.h:34
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *fromMBB)
transferSuccessorsAndUpdatePHIs - Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor blocks which refer to fromMBB to refer to this.
const SDValue & getOperand(unsigned Num) const
F(f)
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
void setVarArgsFrameIndex(int Index)
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags=0)
StringSwitch & Case(const char(&S)[N], const T &Value)
Definition: StringSwitch.h:55
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
ReplaceNodeResults - Replace the results of node with an illegal result type with new values built ou...
const SDValue & getBasePtr() const
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
Definition: ISDOpcodes.h:658
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - get the ISD::SETCC result ValueType
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:357
void LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but leg...
bool isRegLoc() const
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag=true)
Reports a serious error, calling any installed error handler.
SDValue getExternalSymbol(const char *Sym, EVT VT)
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
SDValue getMemcpy(SDValue Chain, SDLoc dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
static MachinePointerInfo getFixedStack(int FI, int64_t offset=0)
getFixedStack - Return a MachinePointerInfo record that refers to the the specified FrameIndex...
bool hasMips32() const
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:200
APInt Not(const APInt &APIVal)
Bitwise complement function.
Definition: APInt.h:1905
static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size)
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
Definition: ISDOpcodes.h:371
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:115
lazy value info
SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
const HexagonInstrInfo * TII
static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG)
unsigned getGPRSizeInBytes() const
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn, const TargetLowering::CallLoweringInfo &CLI)
Definition: MipsCCState.h:101
Shift and rotation operations.
Definition: ISDOpcodes.h:332
bool systemSupportsUnalignedAccess() const
Does the system support unaligned memory access.
static unsigned addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
const TargetRegisterClass * getRegClass(unsigned i) const
getRegClass - Returns the register class associated with the enumeration value.
unsigned getSRetReturnReg() const
bool hasInternalLinkage() const
Definition: GlobalValue.h:278
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:283
static void advance(T &it, size_t Val)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APInt.h:33
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
SDValue getTargetGlobalAddress(const GlobalValue *GV, SDLoc DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:467
virtual TargetLoweringObjectFile * getObjFileLowering() const
void addLoc(const CCValAssign &V)
SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const
iterator begin() const
begin/end - Return all of the registers in this class.
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
Number of individual test Apply this number of consecutive mutations to each input exit after the first new interesting input is found the minimized corpus is saved into the first input directory Number of jobs to run If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
static std::pair< bool, bool > parsePhysicalReg(StringRef C, StringRef &Prefix, unsigned long long &Reg)
This is a helper function to parse a physical register string and split it into non-numeric and numer...
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
bool hasExtractInsert() const
Features related to the presence of specific instructions.
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG...
Definition: ISDOpcodes.h:73
bool hasMSA() const
bool isUpperBitsInLoc() const
bool inMips16HardFloat() const
static Mips::CondCode condCodeToFCC(ISD::CondCode CC)
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
#define G(x, y, z)
Definition: MD5.cpp:52
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
Definition: ValueTypes.h:110
SDValue getAddrGlobalLargeGOT(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned HiFlag, unsigned LoFlag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
SmallVector< ISD::InputArg, 32 > Ins
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:581
FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to first (possible) on-stack ar...
Definition: ISDOpcodes.h:91
MachineFunction & getMachineFunction() const
bool hasMips64() const
SDValue getCALLSEQ_START(SDValue Chain, SDValue Op, SDLoc DL)
Return a new CALLSEQ_START node, which always must have a glue result (to ensure it's not CSE'd)...
Definition: SelectionDAG.h:637
unsigned getLocReg() const
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:30
bool isKill() const
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Definition: SmallVector.h:57
static const MCPhysReg Mips64DPRegs[8]
SDValue getRegisterMask(const uint32_t *RegMask)
bool hasStructRetAttr() const
Determine if the function returns a structure through first pointer argument.
Definition: Function.h:360
static bool invertFPCondCodeUser(Mips::CondCode CC)
This function returns true if the floating point conditional branches and conditional moves which use...
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:191
void addInRegsParamInfo(unsigned RegBegin, unsigned RegEnd)
SmallVector< ISD::OutputArg, 32 > Outs
static SpecialCallingConvType getSpecialCallingConvForCallee(const SDNode *Callee, const MipsSubtarget &Subtarget)
Determine the SpecialCallingConvType for the given callee.
Definition: MipsCCState.cpp:64
bool IsConstantInSmallSection(const Constant *CN, const TargetMachine &TM) const
Return true if this constant should be placed into small data section.
const MachineJumpTableInfo * getJumpTableInfo() const
getJumpTableInfo - Return the jump table info object for the current function.
unsigned getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const override
Return the register ID of the name passed in.
const SDValue & getBasePtr() const
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
Definition: SelectionDAG.h:659
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:804
EVT getMemoryVT() const
Return the type of the in-memory value.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
SDValue getAddrLocal(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, bool IsN32OrN64) const
SDValue getAddrGlobal(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:134
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:284
unsigned getKillRegState(bool B)
const BasicBlock * getBasicBlock() const
getBasicBlock - Return the LLVM basic block that this instance corresponded to originally.
This class is used to represent ISD::STORE nodes.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:267
static unsigned getNextIntArgReg(unsigned Reg)
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:436
const TargetFrameLowering * getFrameLowering() const override
iterator begin() const
Definition: StringRef.h:90
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:97
TargetInstrInfo - Interface to description of machine instruction set.
SDNode * getNode() const
get the SDNode which holds the desired result
unsigned getEntrySize(const DataLayout &TD) const
getEntrySize - Return the size of each entry in the jump table.
bundle_iterator< MachineInstr, instr_iterator > iterator
A self-contained host- and target-independent arbitrary-precision floating-point software implementat...
Definition: APFloat.h:122
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:42
EK_GPRel64BlockAddress - Each entry is an address of block, encoded with a relocation as gp-relative...
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set, or Regs.size() if they are all allocated.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:325
bool isNegZero() const
Definition: APFloat.h:439
virtual FastISel * createFastISel(FunctionLoweringInfo &, const TargetLibraryInfo *) const
This method returns a target specific FastISel object, or null if the target does not support "fast" ...
static mvt_range fp_vector_valuetypes()
static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
MO_GOT_CALL - Represents the offset into the global offset table at which the address of a call site ...
Definition: MipsBaseInfo.h:45
std::size_t countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the least significant bit to the most stopping at the first 1...
Definition: MathExtras.h:109
MVT - Machine Value Type.
LLVM Basic Block Representation.
Definition: BasicBlock.h:65
const SDValue & getOperand(unsigned i) const
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:41
void setTargetDAGCombine(ISD::NodeType NT)
Targets should invoke this method for each target independent node that they want to provide a custom...
bool isNonTemporal() const
bool isVectorTy() const
isVectorTy - True if this is an instance of VectorType.
Definition: Type.h:226
MVT getLocVT() const
bool hasMips64r2() const
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE...
Definition: ISDOpcodes.h:607
bool IsN32() const
Definition: MipsABIInfo.h:44
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:780
const ArrayRef< MCPhysReg > GetByValArgRegs() const
The registers to use for byval arguments.
Definition: MipsABIInfo.cpp:26
const Constant * getConstVal() const
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
char back() const
back - Get the last character in the string.
Definition: StringRef.h:122
static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, SDValue Chain, unsigned Offset)
bool isFloatTy() const
isFloatTy - Return true if this is 'float', a 32-bit IEEE fp type.
Definition: Type.h:143
SDValue getAddrNonPIC(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG) const
APInt Or(const APInt &LHS, const APInt &RHS)
Bitwise OR function for APInt.
Definition: APInt.h:1895
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
bool isVarArg() const
void HandleByVal(CCState *, unsigned &, unsigned) const override
Target-specific cleanup for formal ByVal parameters.
static mvt_range fp_valuetypes()
bool isFP64bit() const
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:547
bool IsN64() const
Definition: MipsABIInfo.h:45
#define LLVM_ATTRIBUTE_UNUSED
Definition: Compiler.h:142
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang","erlang-compatible garbage collector")
static EVT getFloatingPointVT(unsigned BitWidth)
getFloatingPointVT - Returns the EVT that represents a floating point type with the given number of b...
Definition: ValueTypes.h:55
SDValue getTargetConstant(uint64_t Val, SDLoc DL, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:436
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
unsigned getOpcode() const
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:644
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:57
arg_iterator arg_begin()
Definition: Function.h:472
Class to represent integer types.
Definition: DerivedTypes.h:37
bool useSoftFloat() const
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool Immutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:598
static const MipsTargetLowering * create(const MipsTargetMachine &TM, const MipsSubtarget &STI)
bool inMicroMipsMode() const
bool isVolatile() const
const SDValue & getValue() const
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
bool inMips16Mode() const
SDValue getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes())
Bit counting operators with an undefined result for zero inputs.
Definition: ISDOpcodes.h:338
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
EVT - Extended Value Type.
Definition: ValueTypes.h:31
bool hasMips32r6() const
std::vector< ArgListEntry > ArgListTy
unsigned getNextStackOffset() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
MachinePointerInfo - This class contains a discriminated union of information about pointers in memor...
uint64_t getConstantOperandVal(unsigned Num) const
Helper method returns the integer value of a ConstantSDNode operand.
virtual SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const
Returns relocation base for the given PIC jumptable.
MO_GOTTPREL - Represents the offset from the thread pointer (Initial.
Definition: MipsBaseInfo.h:70
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
const BlockAddress * getBlockAddress() const
bool isShiftedMask_64(uint64_t Value)
isShiftedMask_64 - This function returns true if the argument contains a non-empty sequence of ones w...
Definition: MathExtras.h:348
const MachinePointerInfo & getPointerInfo() const
void setIsKill(bool Val=true)
unsigned getByValAlign() const
static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, SDValue Chain, SDValue Src, unsigned Offset)
SDValue getTargetConstantPool(const Constant *C, EVT VT, unsigned Align=0, int Offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:484
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:478
MO_GOT16 - Represents the offset into the global offset table at which the address the relocation ent...
Definition: MipsBaseInfo.h:38
TokenFactor - This node takes multiple tokens as input and produces a single token result...
Definition: ISDOpcodes.h:50
bool isMustTailCall() const
Tests if this call site must be tail call optimized.
Definition: CallSite.h:174
CCState - This class holds information needed while lowering arguments and return values...
const char * const_iterator
Definition: StringRef.h:43
bool startswith(StringRef Prefix) const
Check if this string starts with the given Prefix.
Definition: StringRef.h:215
unsigned countPopulation(T Value)
Count the number of set bits in a value.
Definition: MathExtras.h:449
virtual unsigned getJumpTableEncoding() const
Return the entry encoding for a jump table in the current function.
bool IsO32() const
Definition: MipsABIInfo.h:43
const MipsRegisterInfo * getRegisterInfo() const override
uint64_t getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:388
void setExceptionPointerRegister(unsigned R)
If set to a physical register, this sets the register that receives the exception address on entry to...
static MachineBasicBlock * insertDivByZeroTrap(MachineInstr *MI, MachineBasicBlock &MBB, const TargetInstrInfo &TII, bool Is64Bit)
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:179
SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:861
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:222
Provides information about what library functions are available for the current target.
static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, ArrayRef< MCPhysReg > F64Regs)
CCValAssign - Represent assignment of one arg/retval to a location.
const ArrayRef< MCPhysReg > GetVarArgRegs() const
The registers to use for the variable argument list.
Definition: MipsABIInfo.cpp:34
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:548
Information about stack frame layout on the target.
static cl::opt< bool > NoZeroDivCheck("mno-check-zero-division", cl::Hidden, cl::desc("MIPS: Don't trap on integer division by zero."), cl::init(false))
const SDValue & getChain() const
bool isLittle() const
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:335
FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions and truncation for half-preci...
Definition: ISDOpcodes.h:500
CHAIN = SC CHAIN, Imm128 - System call.
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
static IntegerType * getIntNTy(LLVMContext &C, unsigned N)
Definition: Type.cpp:243
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Represents one node in the SelectionDAG.
CondCode getSetCCInverse(CondCode Operation, bool isInteger)
getSetCCInverse - Return the operation corresponding to !(X op Y), where 'op' is a valid SetCC operat...
bool hasMips64r6() const
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
R Default(const T &Value) const
Definition: StringSwitch.h:111
static mvt_range integer_valuetypes()
static bool CC_Mips(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State) LLVM_ATTRIBUTE_UNUSED
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:576
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
createFastISel - This method returns a target specific FastISel object, or null if the target does no...
void setExceptionSelectorRegister(unsigned R)
If set to a physical register, this sets the register that receives the exception typeid on entry to ...
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
getCallPreservedMask - Return a mask of call-preserved registers for the given calling convention on ...
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:342
void setMinFunctionAlignment(unsigned Align)
Set the target's minimum function alignment (in log2(bytes))
int64_t getSExtValue() const
bool isIntegerTy() const
isIntegerTy - True if this is an instance of IntegerType.
Definition: Type.h:193
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
Return the register class that should be used for the specified value type.
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:383
AddrMode
ARM Addressing Modes.
Definition: ARMBaseInfo.h:235
bool isMemLoc() const
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:285
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:386
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:238
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition: ISDOpcodes.h:250
bool isGP64bit() const
uint64_t RoundUpToAlignment(uint64_t Value, uint64_t Align)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
Definition: MathExtras.h:609
static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op)
MO_TPREL_HI/LO - Represents the hi and low part of the offset from.
Definition: MipsBaseInfo.h:74
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:542
static MachinePointerInfo getGOT()
getGOT - Return a MachinePointerInfo record that refers to a GOT entry.
Representation of each machine instruction.
Definition: MachineInstr.h:51
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the source.
Definition: ISDOpcodes.h:603
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
Definition: MipsCCState.h:110
static const uint32_t * getMips16RetHelperMask()
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:516
SmallVector< SDValue, 32 > OutVals
bool isValid() const
isValid - Return true if this is a valid simple valuetype.
void setFormalArgInfo(unsigned Size, bool HasByval)
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:321
SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const
bool hasAnyUseOfValue(unsigned Value) const
Return true if there are any use of the indicated value.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:217
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static cl::opt< bool > LargeGOT("mxgot", cl::Hidden, cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false))
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
MachinePointerInfo callPtrInfo(StringRef Name)
Create a MachinePointerInfo that has a MipsCallEntr object representing a GOT entry for an external f...
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
bool isSingleFloat() const
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:401
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:518
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:233
void setReg(unsigned Reg)
Change the register this operand corresponds to.
bool hasMips4() const
#define I(x, y, z)
Definition: MD5.cpp:54
#define N
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
bool IsGlobalInSmallSection(const GlobalValue *GV, const TargetMachine &TM, SectionKind Kind) const
Return true if this global address should be placed into small data/bss section.
void setSubReg(unsigned subReg)
void setStackPointerRegisterToSaveRestore(unsigned R)
If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
bool hasMips32r2() const
virtual void getOpndList(SmallVectorImpl< SDValue > &Ops, std::deque< std::pair< unsigned, SDValue > > &RegsToPass, bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const
This function fills Ops, which is the list of operands that will later be used when a function call n...
static CCValAssign getMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
FSINCOS - Compute both fsin and fcos as a single operation.
Definition: ISDOpcodes.h:512
bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:272
unsigned MaxStoresPerMemcpy
Specify maximum bytes of store instructions per memcpy call.
bool hasMips3() const
EVT getValueType() const
Return the ValueType of the referenced return value.
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 'eh_return' gcc dwarf builtin...
Definition: ISDOpcodes.h:97
SDValue getConstant(uint64_t Val, SDLoc DL, EVT VT, bool isTarget=false, bool isOpaque=false)
TLSModel::Model getTLSModel(const GlobalValue *GV) const
Returns the TLS model which should be used for the given global variable.
unsigned getReg() const
getReg - Returns the register number.
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
Definition: ValueTypes.h:105
char front() const
front - Get the first character in the string.
Definition: StringRef.h:116
void insert(iterator MBBI, MachineBasicBlock *MBB)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
void setReturnAddressIsTaken(bool s)
unsigned getAlignment() const
void setMinStackArgumentAlignment(unsigned Align)
Set the minimum stack alignment of an argument (in log2(bytes)).
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
bool hasCnMips() const
LLVM Value Representation.
Definition: Value.h:69
FMA - Perform a * b + c with no intermediate rounding step.
Definition: ISDOpcodes.h:240
SDValue getRegister(unsigned Reg, EVT VT)
bool isZero() const
Returns true if and only if the float is plus or minus zero.
Definition: APFloat.h:414
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
void setInsertFencesForAtomic(bool fence)
Set if the DAG builder should automatically insert fences and reduce the order of atomic memory opera...
bool isTruncatingStore() const
Return true if the op does a truncation before store.
SDValue getValueType(EVT)
bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:298
iterator end() const
Definition: StringRef.h:92
BasicBlockListType::iterator iterator
void ReplaceAllUsesOfValueWith(SDValue From, SDValue To)
Replace any uses of From with To, leaving uses of other values produced by From.Val alone...
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:40
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:365
unsigned getOrigAlign() const
const MipsABIInfo & ABI
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml","ocaml 3.10-compatible collector")
unsigned getMinStackArgumentAlignment() const
Return the minimum stack alignment of an argument.
SDValue getSetCC(SDLoc DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
Definition: SelectionDAG.h:726
SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except that the first operand is an imme...
Definition: TargetOpcodes.h:58
unsigned getLocMemOffset() const
Conversion operators.
Definition: ISDOpcodes.h:380
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:338
OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val) This corresponds to "store atomic" instruction.
Definition: ISDOpcodes.h:666
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:389
const char * getTargetNodeName(unsigned Opcode) const override
getTargetNodeName - This method returns the name of a target specific
unsigned getAlignment() const
unsigned AllocateReg(unsigned Reg)
AllocateReg - Attempt to allocate one register.
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
Examine constraint string and operand type and determine a weight value.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, SDValue False, SDLoc DL)
const T * data() const
Definition: ArrayRef.h:131
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
getIntegerVT - Returns the EVT that represents an integer with the given number of bits...
Definition: ValueTypes.h:61
unsigned AllocateStack(unsigned Size, unsigned Align)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
void addSuccessor(MachineBasicBlock *succ, uint32_t weight=0)
addSuccessor - Add succ as a successor of this MachineBasicBlock.
static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) This corresponds to "load atomic" instruction.
Definition: ISDOpcodes.h:662
EVT changeVectorElementTypeToInteger() const
changeVectorElementTypeToInteger - Return a vector with the same number of elements as this vector...
Definition: ValueTypes.h:80
SDValue getAddrGPRel(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG) const
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
SDValue getIntPtrConstant(uint64_t Val, SDLoc DL, bool isTarget=false)
SDValue getMemIntrinsicNode(unsigned Opcode, SDLoc dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, unsigned Align=0, bool Vol=false, bool ReadMem=true, bool WriteMem=true, unsigned Size=0)
Creates a MemIntrinsicNode that may produce a result and takes a list of operands.
void setSRetReturnReg(unsigned Reg)
uint64_t getZExtValue() const
BRIND - Indirect branch.
Definition: ISDOpcodes.h:538
This class is used to represent ISD::LOAD nodes.
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary...
Definition: ISDOpcodes.h:527