36 static std::pair<unsigned, unsigned> getMFHiLoOpc(
unsigned Src) {
37 if (Mips::ACC64RegClass.
contains(Src))
38 return std::make_pair((
unsigned)Mips::PseudoMFHI,
39 (
unsigned)Mips::PseudoMFLO);
41 if (Mips::ACC64DSPRegClass.
contains(Src))
42 return std::make_pair((
unsigned)Mips::MFHI_DSP, (
unsigned)Mips::MFLO_DSP);
44 if (Mips::ACC128RegClass.
contains(Src))
45 return std::make_pair((
unsigned)Mips::PseudoMFHI64,
46 (
unsigned)Mips::PseudoMFLO64);
48 return std::make_pair(0, 0);
63 unsigned MFLoOpc,
unsigned RegSize);
81 : MF(MF_), MRI(MF.getRegInfo()),
84 RegInfo(*Subtarget.getRegisterInfo()) {}
86 bool ExpandPseudo::expand() {
87 bool Expanded =
false;
91 for (Iter
I = BB->begin(), End = BB->end();
I != End;)
92 Expanded |= expandInstr(*BB,
I++);
98 switch(I->getOpcode()) {
99 case Mips::LOAD_CCOND_DSP:
100 expandLoadCCond(MBB, I);
102 case Mips::STORE_CCOND_DSP:
103 expandStoreCCond(MBB, I);
105 case Mips::LOAD_ACC64:
106 case Mips::LOAD_ACC64DSP:
107 expandLoadACC(MBB, I, 4);
109 case Mips::LOAD_ACC128:
110 expandLoadACC(MBB, I, 8);
112 case Mips::STORE_ACC64:
113 expandStoreACC(MBB, I, Mips::PseudoMFHI, Mips::PseudoMFLO, 4);
115 case Mips::STORE_ACC64DSP:
116 expandStoreACC(MBB, I, Mips::MFHI_DSP, Mips::MFLO_DSP, 4);
118 case Mips::STORE_ACC128:
119 expandStoreACC(MBB, I, Mips::PseudoMFHI64, Mips::PseudoMFLO64, 8);
122 if (expandBuildPairF64(MBB, I,
false))
125 case Mips::BuildPairF64_64:
126 if (expandBuildPairF64(MBB, I,
true))
130 if (expandExtractElementF64(MBB, I,
false))
133 case Mips::ExtractElementF64_64:
134 if (expandExtractElementF64(MBB, I,
true))
138 if (!expandCopy(MBB, I))
153 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
156 unsigned VR = MRI.createVirtualRegister(RC);
157 unsigned Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
159 TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0);
168 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
171 unsigned VR = MRI.createVirtualRegister(RC);
172 unsigned Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
176 TII.storeRegToStack(MBB, I, VR,
true, FI, RC, &RegInfo, 0);
186 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
189 unsigned VR0 = MRI.createVirtualRegister(RC);
190 unsigned VR1 = MRI.createVirtualRegister(RC);
191 unsigned Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
192 unsigned Lo = RegInfo.getSubReg(Dst, Mips::sub_lo);
193 unsigned Hi = RegInfo.getSubReg(Dst, Mips::sub_hi);
197 TII.loadRegFromStack(MBB, I, VR0, FI, RC, &RegInfo, 0);
199 TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize);
204 unsigned MFHiOpc,
unsigned MFLoOpc,
211 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
214 unsigned VR0 = MRI.createVirtualRegister(RC);
215 unsigned VR1 = MRI.createVirtualRegister(RC);
216 unsigned Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
220 BuildMI(MBB, I, DL,
TII.get(MFLoOpc), VR0).addReg(Src);
221 TII.storeRegToStack(MBB, I, VR0,
true, FI, RC, &RegInfo, 0);
222 BuildMI(MBB, I, DL,
TII.get(MFHiOpc), VR1).addReg(Src, SrcKill);
223 TII.storeRegToStack(MBB, I, VR1,
true, FI, RC, &RegInfo, RegSize);
227 unsigned Src = I->getOperand(1).getReg();
228 std::pair<unsigned, unsigned> Opcodes = getMFHiLoOpc(Src);
233 return expandCopyACC(MBB, I, Opcodes.first, Opcodes.second);
237 unsigned MFHiOpc,
unsigned MFLoOpc) {
243 unsigned Dst = I->getOperand(0).getReg(), Src = I->getOperand(1).getReg();
244 unsigned VRegSize = RegInfo.getMinimalPhysRegClass(Dst)->getSize() / 2;
246 unsigned VR0 = MRI.createVirtualRegister(RC);
247 unsigned VR1 = MRI.createVirtualRegister(RC);
249 unsigned DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo);
250 unsigned DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi);
253 BuildMI(MBB, I, DL,
TII.get(MFLoOpc), VR0).addReg(Src);
256 BuildMI(MBB, I, DL,
TII.get(MFHiOpc), VR1).addReg(Src, SrcKill);
282 if ((Subtarget.isABI_FPXX() && !Subtarget.hasMTHC1()) ||
283 (FP64 && !Subtarget.useOddSPReg())) {
284 unsigned DstReg = I->getOperand(0).getReg();
285 unsigned LoReg = I->getOperand(1).getReg();
286 unsigned HiReg = I->getOperand(2).getReg();
291 assert(Subtarget.isGP64bit() || Subtarget.hasMTHC1() ||
292 !Subtarget.isFP64bit());
296 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
301 if (!Subtarget.isLittle())
303 TII.storeRegToStack(MBB, I, LoReg, I->getOperand(1).isKill(), FI, RC,
305 TII.storeRegToStack(MBB, I, HiReg, I->getOperand(2).isKill(), FI, RC,
307 TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &RegInfo, 0);
335 if ((Subtarget.isABI_FPXX() && !Subtarget.hasMTHC1()) ||
336 (FP64 && !Subtarget.useOddSPReg())) {
337 unsigned DstReg = I->getOperand(0).getReg();
338 unsigned SrcReg = I->getOperand(1).getReg();
339 unsigned N = I->getOperand(2).getImm();
340 int64_t Offset = 4 * (Subtarget.isLittle() ? N : (1 -
N));
345 assert(Subtarget.isGP64bit() || Subtarget.hasMTHC1() ||
346 !Subtarget.isFP64bit());
349 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
355 TII.storeRegToStack(MBB, I, SrcReg, I->getOperand(1).isKill(), FI, RC,
357 TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &RegInfo, Offset);
369 assert(&MF.
front() == &MBB &&
"Shrink-wrapping not yet supported");
389 &Mips::GPR64RegClass : &Mips::GPR32RegClass;
392 uint64_t StackSize = MFI->getStackSize();
395 if (StackSize == 0 && !MFI->adjustsStack())
return;
402 TII.adjustStackPtr(SP, -StackSize, MBB, MBBI);
408 .addCFIIndex(CFIIndex);
410 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
415 for (
unsigned i = 0; i < CSI.size(); ++i)
420 for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
421 E = CSI.end(); I != E; ++
I) {
422 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
423 unsigned Reg = I->getReg();
427 if (Mips::AFGR64RegClass.
contains(Reg)) {
439 .addCFIIndex(CFIIndex);
444 .addCFIIndex(CFIIndex);
445 }
else if (Mips::FGR64RegClass.
contains(Reg)) {
455 .addCFIIndex(CFIIndex);
460 .addCFIIndex(CFIIndex);
466 .addCFIIndex(CFIIndex);
473 for (
int I = 0; I < 4; ++
I) {
476 TII.storeRegToStackSlot(MBB, MBBI, ABI.
GetEhDataReg(I),
false,
481 for (
int I = 0; I < 4; ++
I) {
487 .addCFIIndex(CFIIndex);
501 .addCFIIndex(CFIIndex);
507 assert(
isInt<16>(MFI->getMaxAlignment()) &&
508 "Function's alignment size requirement is not supported.");
509 int MaxAlign = - (signed) MFI->getMaxAlignment();
557 ABI.
ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
565 for (
int J = 0; J < 4; ++J) {
578 TII.adjustStackPtr(SP, StackSize, MBB, MBBI);
584 const std::vector<CalleeSavedInfo> &CSI,
590 for (
unsigned i = 0, e = CSI.size(); i != e; ++i) {
596 unsigned Reg = CSI[i].getReg();
597 bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA || Reg == Mips::RA_64)
599 if (!IsRAAndRetAddrIsTaken)
603 bool IsKill = !IsRAAndRetAddrIsTaken;
606 CSI[i].getFrameIdx(), RC, TRI);
638 unsigned BP = ABI.IsN64() ? Mips::S7_64 : Mips::S7;
653 if (ExpandPseudo(MF).expand()) {
657 &Mips::GPR64RegClass : &Mips::GPR32RegClass;
671 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
int getDwarfRegNum(unsigned RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
bool ArePtrs64bit() const
const MipsFrameLowering * createMipsSEFrameLowering(const MipsSubtarget &ST)
const MipsABIInfo & getABI() const
void setAliasRegs(MachineFunction &MF, BitVector &SavedRegs, unsigned Reg)
Mark Reg and all registers aliasing it in the bitset.
const MipsSubtarget & STI
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Describe properties that are true of each instruction in the target description file.
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
const MipsInstrInfo * getInstrInfo() const override
void addLiveIn(unsigned Reg)
Adds the specified register as a live in.
bool isReturnAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
static MCCFIInstruction createDefCfaOffset(MCSymbol *L, int Offset)
.cfi_def_cfa_offset modifies a rule for computing CFA.
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
COPY - Target-independent register copy.
unsigned getSize() const
getSize - Return the size of the register in bytes, which is also the size of a stack slot allocated ...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
DILocation * get() const
Get the underlying DILocation.
const HexagonInstrInfo * TII
void createEhDataRegsFI()
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
const MachineBasicBlock & front() const
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required, we reserve argument space for call sites in the function immediately on entry to the current function.
unsigned LLVM_ATTRIBUTE_UNUSED_RESULT addFrameInst(const MCCFIInstruction &Inst)
bool hasBP(const MachineFunction &MF) const
iterator getLastNonDebugInstr()
getLastNonDebugInstr - returns an iterator to the last non-debug instruction in the basic block...
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
unsigned getKillRegState(bool B)
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
TargetInstrInfo - Interface to description of machine instruction set.
bundle_iterator< MachineInstr, instr_iterator > iterator
unsigned getAlignment() const
getAlignment - Return the minimum required alignment for a register of this class.
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register)
.cfi_def_cfa_register modifies a rule for computing CFA.
MCRegAliasIterator enumerates all registers aliasing Reg.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
virtual void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Store the specified register of the given register class to the specified stack frame index...
int getEhDataRegFI(unsigned Reg) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
unsigned GetEhDataReg(unsigned I) const
unsigned GetStackPtr() const
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
unsigned GetNullPtr() const
const MipsRegisterInfo * getRegisterInfo() const override
const MCContext & getContext() const
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call...
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
getMinimalPhysRegClass - Returns the Register Class of a physical register of the given type...
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
const MCRegisterInfo * getRegisterInfo() const
bool callsEhReturn() const
bool needsStackRealignment(const MachineFunction &MF) const override
bool isLiveIn(unsigned Reg) const
isLiveIn - Return true if the specified register is in the live in set.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
MipsSEFrameLowering(const MipsSubtarget &STI)
unsigned GetFramePtr() const
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
bool isInt< 16 >(int64_t x)
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSS, const AllocaInst *Alloca=nullptr)
Create a new statically sized stack object, returning a nonnegative identifier to represent it...
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
unsigned GetPtrAdduOp() const
uint64_t estimateStackSize(const MachineFunction &MF) const
BasicBlockListType::iterator iterator
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
MachineModuleInfo & getMMI() const
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
unsigned GetPtrAddiuOp() const
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
MachineModuleInfo - This class contains meta information specific to a module.