LLVM  3.7.0
AMDGPUISelLowering.h
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1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief Interface definition of the TargetLowering class that is common
12 /// to all AMD GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_R600_AMDGPUISELLOWERING_H
17 #define LLVM_LIB_TARGET_R600_AMDGPUISELLOWERING_H
18 
20 
21 namespace llvm {
22 
23 class AMDGPUMachineFunction;
24 class AMDGPUSubtarget;
25 class MachineRegisterInfo;
26 
28 protected:
30 
31 private:
32  SDValue LowerConstantInitializer(const Constant* Init, const GlobalValue *GV,
33  const SDValue &InitPtr,
34  SDValue Chain,
35  SelectionDAG &DAG) const;
36  SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
37  SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
38  SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
39  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
40  /// \brief Lower vector stores by merging the vector elements into an integer
41  /// of the same bitwidth.
42  SDValue MergeVectorStore(const SDValue &Op, SelectionDAG &DAG) const;
43  /// \brief Split a vector store into multiple scalar stores.
44  /// \returns The resulting chain.
45 
46  SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
47  SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
48  SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
49  SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
50  SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
51 
52  SDValue LowerFROUND32(SDValue Op, SelectionDAG &DAG) const;
53  SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const;
54  SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
55  SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
56 
57  SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
58  SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
59  SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
60 
61  SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const;
62  SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
63  SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
64 
65  SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
66 
67  SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
68  SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
69  SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
70 
71 protected:
72  static EVT getEquivalentMemType(LLVMContext &Context, EVT VT);
73  static EVT getEquivalentLoadRegType(LLVMContext &Context, EVT VT);
74 
76  SelectionDAG &DAG) const;
77 
78  /// \brief Split a vector load into a scalar load of each component.
80 
81  /// \brief Split a vector load into 2 loads of half the vector.
83 
84  /// \brief Split a vector store into a scalar store of each component.
86 
87  /// \brief Split a vector store into 2 stores of half the vector.
89 
90  SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
91  SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
92  SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
93  SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
94  SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
95  void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
96  SmallVectorImpl<SDValue> &Results) const;
97  bool isHWTrueValue(SDValue Op) const;
98  bool isHWFalseValue(SDValue Op) const;
99 
100  /// The SelectionDAGBuilder will automatically promote function arguments
101  /// with illegal types. However, this does not work for the AMDGPU targets
102  /// since the function arguments are stored in memory as these illegal types.
103  /// In order to handle this properly we need to get the origianl types sizes
104  /// from the LLVM IR Function and fixup the ISD:InputArg values before
105  /// passing them to AnalyzeFormalArguments()
107  const Function *F,
109  SmallVectorImpl<ISD::InputArg> &OrigIns) const;
110  void AnalyzeFormalArguments(CCState &State,
111  const SmallVectorImpl<ISD::InputArg> &Ins) const;
112 
113 public:
115 
116  bool isFAbsFree(EVT VT) const override;
117  bool isFNegFree(EVT VT) const override;
118  bool isTruncateFree(EVT Src, EVT Dest) const override;
119  bool isTruncateFree(Type *Src, Type *Dest) const override;
120 
121  bool isZExtFree(Type *Src, Type *Dest) const override;
122  bool isZExtFree(EVT Src, EVT Dest) const override;
123  bool isZExtFree(SDValue Val, EVT VT2) const override;
124 
125  bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
126 
127  MVT getVectorIdxTy(const DataLayout &) const override;
128  bool isSelectSupported(SelectSupportKind) const override;
129 
130  bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
131  bool ShouldShrinkFPConstant(EVT VT) const override;
133  ISD::LoadExtType ExtType,
134  EVT ExtVT) const override;
135 
136  bool isLoadBitCastBeneficial(EVT, EVT) const override;
137 
139  unsigned NumElem,
140  unsigned AS) const override;
141  bool isCheapToSpeculateCttz() const override;
142  bool isCheapToSpeculateCtlz() const override;
143 
144  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
145  bool isVarArg,
147  const SmallVectorImpl<SDValue> &OutVals,
148  SDLoc DL, SelectionDAG &DAG) const override;
150  SmallVectorImpl<SDValue> &InVals) const override;
151 
152  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
153  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
154  void ReplaceNodeResults(SDNode * N,
155  SmallVectorImpl<SDValue> &Results,
156  SelectionDAG &DAG) const override;
157 
161  EVT VT,
162  SDValue LHS,
163  SDValue RHS,
164  SDValue True,
165  SDValue False,
166  SDValue CC,
167  DAGCombinerInfo &DCI) const;
169  EVT VT,
170  SDValue LHS,
171  SDValue RHS,
172  SDValue True,
173  SDValue False,
174  SDValue CC,
175  SelectionDAG &DAG) const;
176 
177  const char* getTargetNodeName(unsigned Opcode) const override;
178 
180  DAGCombinerInfo &DCI,
181  unsigned &RefinementSteps,
182  bool &UseOneConstNR) const override;
184  DAGCombinerInfo &DCI,
185  unsigned &RefinementSteps) const override;
186 
188  SelectionDAG &DAG) const {
189  return N;
190  }
191 
192  /// \brief Determine which of the bits specified in \p Mask are known to be
193  /// either zero or one and return them in the \p KnownZero and \p KnownOne
194  /// bitsets.
196  APInt &KnownZero,
197  APInt &KnownOne,
198  const SelectionDAG &DAG,
199  unsigned Depth = 0) const override;
200 
201  unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const SelectionDAG &DAG,
202  unsigned Depth = 0) const override;
203 
204  /// \brief Helper function that adds Reg to the LiveIn list of the DAG's
205  /// MachineFunction.
206  ///
207  /// \returns a RegisterSDNode representing Reg.
209  const TargetRegisterClass *RC,
210  unsigned Reg, EVT VT) const;
211 
215  };
216 
217  /// \brief Helper function that returns the byte offset of the given
218  /// type of implicit parameter.
220  const ImplicitParameter Param) const;
221 };
222 
223 namespace AMDGPUISD {
224 
225 enum NodeType : unsigned {
226  // AMDIL ISD Opcodes
228  CALL, // Function call based on a single integer
229  UMUL, // 32bit unsigned multiplication
232  // End AMDIL ISD Opcodes
236 
237  // SIN_HW, COS_HW - f32 for SI, 1 ULP max error, valid from -100 pi to 100 pi.
238  // Denormals handled on some parts.
253  TRIG_PREOP, // 1 ULP max error for f64
254 
255  // RCP, RSQ - For f32, 1 ULP max error, no denormal handling.
256  // For f64, max error 2^29 ULP, handles denormals.
266  BFE_U32, // Extract range of bits with zero extension to 32-bits.
267  BFE_I32, // Extract range of bits with sign extension to 32-bits.
268  BFI, // (src0 & src1) | (~src0 & src2)
269  BFM, // Insert a range of bits into a 32-bit word.
270  BREV, // Reverse bits.
285 
286  // These cvt_f32_ubyte* nodes need to remain consecutive and in order.
291  /// This node is for VLIW targets and it is used to represent a vector
292  /// that is stored in consecutive registers with the same channel.
293  /// For example:
294  /// |X |Y|Z|W|
295  /// T0|v.x| | | |
296  /// T1|v.y| | | |
297  /// T2|v.z| | | |
298  /// T3|v.w| | | |
300  /// Pointer to the start of the shader's constant data.
311 };
312 
313 
314 } // End namespace AMDGPUISD
315 
316 } // End namespace llvm
317 
318 #endif
AMDGPUTargetLowering(TargetMachine &TM, const AMDGPUSubtarget &STI)
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:724
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:104
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, SDLoc DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array...
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG, SmallVectorImpl< SDValue > &Results) const
bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtType, EVT ExtVT) const override
void AnalyzeFormalArguments(CCState &State, const SmallVectorImpl< ISD::InputArg > &Ins) const
virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, SelectionDAG &DAG) const
F(f)
SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
virtual SDNode * PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const
SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const
bool storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem, unsigned AS) const override
Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the give...
bool isCheapToSpeculateCttz() const override
Return true if it is cheap to speculate a call to intrinsic cttz.
SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI, unsigned &RefinementSteps, bool &UseOneConstNR) const override
Hooks for building estimates in place of slower divisions and square roots.
SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const
Pointer to the start of the shader's constant data.
SDValue ScalarizeVectorStore(SDValue Op, SelectionDAG &DAG) const
Split a vector store into a scalar store of each component.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APInt.h:33
virtual SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const
Helper function that adds Reg to the LiveIn list of the DAG's MachineFunction.
Reg
All possible values of the reg field in the ModR/M byte.
SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const
IABS(a) = SMAX(sub(0, a), a)
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const SelectionDAG &DAG, unsigned Depth=0) const override
This method can be implemented by targets that want to expose additional information about sign bits ...
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
const AMDGPUSubtarget * Subtarget
SDValue CombineIMinMax(SDLoc DL, EVT VT, SDValue LHS, SDValue RHS, SDValue True, SDValue False, SDValue CC, SelectionDAG &DAG) const
SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI, unsigned &RefinementSteps) const override
Return a reciprocal estimate value for the input operand.
bool isHWTrueValue(SDValue Op) const
This node is for VLIW targets and it is used to represent a vector that is stored in consecutive regi...
A self-contained host- and target-independent arbitrary-precision floating-point software implementat...
Definition: APFloat.h:122
MVT - Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:41
This is an important base class in LLVM.
Definition: Constant.h:41
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:780
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
bool isLoadBitCastBeneficial(EVT, EVT) const override
isLoadBitCastBeneficial() - Return true if the following transform is beneficial. ...
SDValue ScalarizeVectorLoad(SDValue Op, SelectionDAG &DAG) const
Split a vector load into a scalar load of each component.
SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const
Linear Interpolation LRP(a, b, c) = muladd(a, b, (1 - a) * c)
EVT - Extended Value Type.
Definition: ValueTypes.h:31
bool isHWFalseValue(SDValue Op) const
This structure contains all information that is necessary for lowering calls.
bool isFPImmLegal(const APFloat &Imm, EVT VT) const override
Returns true if the target can instruction select the specified FP immediate natively.
SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const
Split a vector store into 2 stores of half the vector.
void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
CCState - This class holds information needed while lowering arguments and return values...
SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const
Split a vector load into 2 loads of half the vector.
bool isFAbsFree(EVT VT) const override
Return true if an fabs operation is free to the point where it is never worthwhile to replace it with...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:179
An SDNode that represents everything that will be needed to construct a MachineInstr.
SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:731
Represents one node in the SelectionDAG.
Class for arbitrary precision integers.
Definition: APInt.h:73
static EVT getEquivalentLoadRegType(LLVMContext &Context, EVT VT)
bool isNarrowingProfitable(EVT VT1, EVT VT2) const override
Return true if it's profitable to narrow operations of type VT1 to VT2.
SelectSupportKind
Enum that describes what type of support for selects the target has.
#define N
bool isTruncateFree(EVT Src, EVT Dest) const override
SDValue CombineFMinMaxLegacy(SDLoc DL, EVT VT, SDValue LHS, SDValue RHS, SDValue True, SDValue False, SDValue CC, DAGCombinerInfo &DCI) const
Generate Min/Max node.
bool isFNegFree(EVT VT) const override
Return true if an fneg operation is free to the point where it is never worthwhile to replace it with...
void getOriginalFunctionArgs(SelectionDAG &DAG, const Function *F, const SmallVectorImpl< ISD::InputArg > &Ins, SmallVectorImpl< ISD::InputArg > &OrigIns) const
The SelectionDAGBuilder will automatically promote function arguments with illegal types...
static EVT getEquivalentMemType(LLVMContext &Context, EVT VT)
Primary interface to the complete machine description for the target machine.
bool isZExtFree(Type *Src, Type *Dest) const override
Return true if any actual instruction that defines a value of type Ty1 implicitly zero-extends the va...
unsigned getImplicitParameterOffset(const AMDGPUMachineFunction *MFI, const ImplicitParameter Param) const
Helper function that returns the byte offset of the given type of implicit parameter.
SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const
bool ShouldShrinkFPConstant(EVT VT) const override
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
MVT getVectorIdxTy(const DataLayout &) const override
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const
This file describes how to lower LLVM code to machine code.
bool isSelectSupported(SelectSupportKind) const override