LLVM  3.7.0
ARMSubtarget.h
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1 //===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file declares the ARM specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
15 #define LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
16 
17 
18 #include "ARMFrameLowering.h"
19 #include "ARMISelLowering.h"
20 #include "ARMInstrInfo.h"
21 #include "ARMSelectionDAGInfo.h"
22 #include "ARMSubtarget.h"
24 #include "Thumb1FrameLowering.h"
25 #include "Thumb1InstrInfo.h"
26 #include "Thumb2InstrInfo.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/IR/DataLayout.h"
31 #include <string>
32 
33 #define GET_SUBTARGETINFO_HEADER
34 #include "ARMGenSubtargetInfo.inc"
35 
36 namespace llvm {
37 class GlobalValue;
38 class StringRef;
39 class TargetOptions;
40 class ARMBaseTargetMachine;
41 
43 protected:
47  };
50  };
51 
52  /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
54 
55  /// ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
57 
58  /// HasV4TOps, HasV5TOps, HasV5TEOps,
59  /// HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops -
60  /// Specify whether target support specific ARM ISA variants.
61  bool HasV4TOps;
62  bool HasV5TOps;
63  bool HasV5TEOps;
64  bool HasV6Ops;
65  bool HasV6MOps;
66  bool HasV6KOps;
67  bool HasV6T2Ops;
68  bool HasV7Ops;
69  bool HasV8Ops;
71 
72  /// HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what
73  /// floating point ISAs are supported.
74  bool HasVFPv2;
75  bool HasVFPv3;
76  bool HasVFPv4;
77  bool HasFPARMv8;
78  bool HasNEON;
79 
80  /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
81  /// specified. Use the method useNEONForSinglePrecisionFP() to
82  /// determine if NEON should actually be used.
84 
85  /// UseMulOps - True if non-microcoded fused integer multiply-add and
86  /// multiply-subtract instructions should be used.
87  bool UseMulOps;
88 
89  /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
90  /// whether the FP VML[AS] instructions are slow (if so, don't use them).
91  bool SlowFPVMLx;
92 
93  /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
94  /// forwarding to allow mul + mla being issued back to back.
96 
97  /// SlowFPBrcc - True if floating point compare + branch is slow.
98  bool SlowFPBrcc;
99 
100  /// InThumbMode - True if compiling for Thumb, false for ARM.
102 
103  /// UseSoftFloat - True if we're using software floating point features.
105 
106  /// HasThumb2 - True if Thumb2 instructions are supported.
107  bool HasThumb2;
108 
109  /// NoARM - True if subtarget does not support ARM mode execution.
110  bool NoARM;
111 
112  /// IsR9Reserved - True if R9 is a not available as general purpose register.
114 
115  /// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit
116  /// imms (including global addresses).
117  bool UseMovt;
118 
119  /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
120  /// must be able to synthesize call stubs for interworking between ARM and
121  /// Thumb.
123 
124  /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF
125  /// only so far)
126  bool HasFP16;
127 
128  /// HasD16 - True if subtarget is limited to 16 double precision
129  /// FP registers for VFPv3.
130  bool HasD16;
131 
132  /// HasHardwareDivide - True if subtarget supports [su]div
134 
135  /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode
137 
138  /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
139  /// instructions.
141 
142  /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
143  /// instructions.
145 
146  /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
147  /// over 16-bit ones.
149 
150  /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
151  /// that partially update CPSR and add false dependency on the previous
152  /// CPSR setting instruction.
154 
155  /// AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting
156  /// movs with shifter operand (i.e. asr, lsl, lsr).
158 
159  /// HasRAS - Some processors perform return stack prediction. CodeGen should
160  /// avoid issue "normal" call instructions to callees which do not return.
161  bool HasRAS;
162 
163  /// HasMPExtension - True if the subtarget supports Multiprocessing
164  /// extension (ARMv7 only).
166 
167  /// HasVirtualization - True if the subtarget supports the Virtualization
168  /// extension.
170 
171  /// FPOnlySP - If true, the floating point unit only supports single
172  /// precision.
173  bool FPOnlySP;
174 
175  /// If true, the processor supports the Performance Monitor Extensions. These
176  /// include a generic cycle-counter as well as more fine-grained (often
177  /// implementation-specific) events.
179 
180  /// HasTrustZone - if true, processor supports TrustZone security extensions
182 
183  /// HasCrypto - if true, processor supports Cryptography extensions
184  bool HasCrypto;
185 
186  /// HasCRC - if true, processor supports CRC instructions
187  bool HasCRC;
188 
189  /// If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are
190  /// particularly effective at zeroing a VFP register.
192 
193  /// AllowsUnalignedMem - If true, the subtarget allows unaligned memory
194  /// accesses for some types. For details, see
195  /// ARMTargetLowering::allowsMisalignedMemoryAccesses().
197 
198  /// RestrictIT - If true, the subtarget disallows generation of deprecated IT
199  /// blocks to conform to ARMv8 rule.
201 
202  /// Thumb2DSP - If true, the subtarget supports the v7 DSP (saturating arith
203  /// and such) instructions in Thumb2 code.
204  bool Thumb2DSP;
205 
206  /// NaCl TRAP instruction is generated instead of the regular TRAP.
208 
209  /// Generate calls via indirect call instructions.
211 
212  /// Target machine allowed unsafe FP math (such as use of NEON fp)
214 
215  /// stackAlignment - The minimum alignment known to hold of the stack frame on
216  /// entry to the function and which must be maintained by every function.
217  unsigned stackAlignment;
218 
219  /// CPUString - String name of used CPU.
220  std::string CPUString;
221 
222  /// IsLittle - The target is Little Endian
223  bool IsLittle;
224 
225  /// TargetTriple - What processor and OS we're targeting.
227 
228  /// SchedModel - Processor specific instruction costs.
230 
231  /// Selected instruction itineraries (one entry per itinerary class.)
233 
234  /// Options passed via command line that could influence the target
236 
238 
239 public:
240  /// This constructor initializes the data members to match that
241  /// of the specified triple.
242  ///
243  ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
244  const ARMBaseTargetMachine &TM, bool IsLittle);
245 
246  /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
247  /// that still makes it profitable to inline the call.
248  unsigned getMaxInlineSizeThreshold() const {
249  return 64;
250  }
251  /// ParseSubtargetFeatures - Parses features string setting specified
252  /// subtarget options. Definition of function is auto generated by tblgen.
254 
255  /// initializeSubtargetDependencies - Initializes using a CPU and feature string
256  /// so that we can use initializer lists for subtarget initialization.
258 
259  const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
260  return &TSInfo;
261  }
262  const ARMBaseInstrInfo *getInstrInfo() const override {
263  return InstrInfo.get();
264  }
265  const ARMTargetLowering *getTargetLowering() const override {
266  return &TLInfo;
267  }
268  const ARMFrameLowering *getFrameLowering() const override {
269  return FrameLowering.get();
270  }
271  const ARMBaseRegisterInfo *getRegisterInfo() const override {
272  return &InstrInfo->getRegisterInfo();
273  }
274 
275 private:
276  ARMSelectionDAGInfo TSInfo;
277  // Either Thumb1FrameLowering or ARMFrameLowering.
278  std::unique_ptr<ARMFrameLowering> FrameLowering;
279  // Either Thumb1InstrInfo or Thumb2InstrInfo.
280  std::unique_ptr<ARMBaseInstrInfo> InstrInfo;
281  ARMTargetLowering TLInfo;
282 
283  void initializeEnvironment();
284  void initSubtargetFeatures(StringRef CPU, StringRef FS);
285  ARMFrameLowering *initializeFrameLowering(StringRef CPU, StringRef FS);
286 
287 public:
288  void computeIssueWidth();
289 
290  bool hasV4TOps() const { return HasV4TOps; }
291  bool hasV5TOps() const { return HasV5TOps; }
292  bool hasV5TEOps() const { return HasV5TEOps; }
293  bool hasV6Ops() const { return HasV6Ops; }
294  bool hasV6MOps() const { return HasV6MOps; }
295  bool hasV6KOps() const { return HasV6KOps; }
296  bool hasV6T2Ops() const { return HasV6T2Ops; }
297  bool hasV7Ops() const { return HasV7Ops; }
298  bool hasV8Ops() const { return HasV8Ops; }
299  bool hasV8_1aOps() const { return HasV8_1aOps; }
300 
301  bool isCortexA5() const { return ARMProcFamily == CortexA5; }
302  bool isCortexA7() const { return ARMProcFamily == CortexA7; }
303  bool isCortexA8() const { return ARMProcFamily == CortexA8; }
304  bool isCortexA9() const { return ARMProcFamily == CortexA9; }
305  bool isCortexA15() const { return ARMProcFamily == CortexA15; }
306  bool isSwift() const { return ARMProcFamily == Swift; }
307  bool isCortexM3() const { return CPUString == "cortex-m3"; }
308  bool isLikeA9() const { return isCortexA9() || isCortexA15() || isKrait(); }
309  bool isCortexR5() const { return ARMProcFamily == CortexR5; }
310  bool isKrait() const { return ARMProcFamily == Krait; }
311 
312  bool hasARMOps() const { return !NoARM; }
313 
314  bool hasVFP2() const { return HasVFPv2; }
315  bool hasVFP3() const { return HasVFPv3; }
316  bool hasVFP4() const { return HasVFPv4; }
317  bool hasFPARMv8() const { return HasFPARMv8; }
318  bool hasNEON() const { return HasNEON; }
319  bool hasCrypto() const { return HasCrypto; }
320  bool hasCRC() const { return HasCRC; }
321  bool hasVirtualization() const { return HasVirtualization; }
324  }
325 
326  bool hasDivide() const { return HasHardwareDivide; }
328  bool hasT2ExtractPack() const { return HasT2ExtractPack; }
329  bool hasDataBarrier() const { return HasDataBarrier; }
330  bool hasAnyDataBarrier() const {
331  return HasDataBarrier || (hasV6Ops() && !isThumb());
332  }
333  bool useMulOps() const { return UseMulOps; }
334  bool useFPVMLx() const { return !SlowFPVMLx; }
335  bool hasVMLxForwarding() const { return HasVMLxForwarding; }
336  bool isFPBrccSlow() const { return SlowFPBrcc; }
337  bool isFPOnlySP() const { return FPOnlySP; }
338  bool hasPerfMon() const { return HasPerfMon; }
339  bool hasTrustZone() const { return HasTrustZone; }
340  bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
341  bool prefers32BitThumb() const { return Pref32BitThumb; }
344  bool hasRAS() const { return HasRAS; }
345  bool hasMPExtension() const { return HasMPExtension; }
346  bool hasThumb2DSP() const { return Thumb2DSP; }
347  bool useNaClTrap() const { return UseNaClTrap; }
348  bool genLongCalls() const { return GenLongCalls; }
349 
350  bool hasFP16() const { return HasFP16; }
351  bool hasD16() const { return HasD16; }
352 
353  const Triple &getTargetTriple() const { return TargetTriple; }
354 
355  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
356  bool isTargetIOS() const { return TargetTriple.isiOS(); }
357  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
358  bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
359  bool isTargetNetBSD() const { return TargetTriple.isOSNetBSD(); }
360  bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
361 
362  bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
363  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
364  bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
365 
366  // ARM EABI is the bare-metal EABI described in ARM ABI documents and
367  // can be accessed via -target arm-none-eabi. This is NOT GNUEABI.
368  // FIXME: Add a flag for bare-metal for that target and set Triple::EABI
369  // even for GNUEABI, so we can make a distinction here and still conform to
370  // the EABI on GNU (and Android) mode. This requires change in Clang, too.
371  // FIXME: The Darwin exception is temporary, while we move users to
372  // "*-*-*-macho" triples as quickly as possible.
373  bool isTargetAEABI() const {
377  }
378 
379  // ARM Targets that support EHABI exception handling standard
380  // Darwin uses SjLj. Other targets might need more checks.
381  bool isTargetEHABICompatible() const {
388  }
389 
390  bool isTargetHardFloat() const {
391  // FIXME: this is invalid for WindowsCE
394  isTargetWindows();
395  }
396  bool isTargetAndroid() const {
398  }
399 
400  bool isAPCS_ABI() const;
401  bool isAAPCS_ABI() const;
402 
403  bool useSoftFloat() const { return UseSoftFloat; }
404  bool isThumb() const { return InThumbMode; }
405  bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
406  bool isThumb2() const { return InThumbMode && HasThumb2; }
407  bool hasThumb2() const { return HasThumb2; }
408  bool isMClass() const { return ARMProcClass == MClass; }
409  bool isRClass() const { return ARMProcClass == RClass; }
410  bool isAClass() const { return ARMProcClass == AClass; }
411 
412  bool isV6M() const {
413  return isThumb1Only() && isMClass();
414  }
415 
416  bool isR9Reserved() const { return IsR9Reserved; }
417 
418  bool useMovt(const MachineFunction &MF) const;
419 
420  bool supportsTailCall() const { return SupportsTailCall; }
421 
422  bool allowsUnalignedMem() const { return AllowsUnalignedMem; }
423 
424  bool restrictIT() const { return RestrictIT; }
425 
426  const std::string & getCPUString() const { return CPUString; }
427 
428  bool isLittle() const { return IsLittle; }
429 
430  unsigned getMispredictionPenalty() const;
431 
432  /// This function returns true if the target has sincos() routine in its
433  /// compiler runtime or math libraries.
434  bool hasSinCos() const;
435 
436  /// True for some subtargets at > -O0.
437  bool enablePostRAScheduler() const override;
438 
439  // enableAtomicExpand- True if we need to expand our atomics.
440  bool enableAtomicExpand() const override;
441 
442  /// getInstrItins - Return the instruction itineraries based on subtarget
443  /// selection.
444  const InstrItineraryData *getInstrItineraryData() const override {
445  return &InstrItins;
446  }
447 
448  /// getStackAlignment - Returns the minimum alignment known to hold of the
449  /// stack frame on entry to the function and which must be maintained by every
450  /// function for this subtarget.
451  unsigned getStackAlignment() const { return stackAlignment; }
452 
453  /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect
454  /// symbol.
455  bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
456 
457  /// True if fast-isel is used.
458  bool useFastISel() const;
459 };
460 } // End llvm namespace
461 
462 #endif // ARMSUBTARGET_H
bool hasV4TOps() const
Definition: ARMSubtarget.h:290
bool avoidCPSRPartialUpdate() const
Definition: ARMSubtarget.h:342
unsigned stackAlignment
stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and ...
Definition: ARMSubtarget.h:217
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
Definition: ARMSubtarget.h:226
bool isFPOnlySP() const
Definition: ARMSubtarget.h:337
bool avoidMOVsShifterOperand() const
Definition: ARMSubtarget.h:343
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:489
unsigned getMispredictionPenalty() const
bool hasV8_1aOps() const
Definition: ARMSubtarget.h:299
const std::string & getCPUString() const
Definition: ARMSubtarget.h:426
bool SlowFPVMLx
SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates whether the FP VML[AS] instruct...
Definition: ARMSubtarget.h:91
bool isCortexA8() const
Definition: ARMSubtarget.h:303
const ARMSelectionDAGInfo * getSelectionDAGInfo() const override
Definition: ARMSubtarget.h:259
bool isTargetEHABICompatible() const
Definition: ARMSubtarget.h:381
bool AllowsUnalignedMem
AllowsUnalignedMem - If true, the subtarget allows unaligned memory accesses for some types...
Definition: ARMSubtarget.h:196
bool isAClass() const
Definition: ARMSubtarget.h:410
const ARMTargetLowering * getTargetLowering() const override
Definition: ARMSubtarget.h:265
bool hasT2ExtractPack() const
Definition: ARMSubtarget.h:328
bool useFastISel() const
True if fast-isel is used.
bool HasVFPv2
HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what floating point ISAs are supported...
Definition: ARMSubtarget.h:74
bool hasV5TEOps() const
Definition: ARMSubtarget.h:292
bool hasV6Ops() const
Definition: ARMSubtarget.h:293
bool HasHardwareDivideInARM
HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode.
Definition: ARMSubtarget.h:136
bool hasV6T2Ops() const
Definition: ARMSubtarget.h:296
bool isThumb1Only() const
Definition: ARMSubtarget.h:405
const ARMBaseTargetMachine & TM
Definition: ARMSubtarget.h:237
bool hasDivide() const
Definition: ARMSubtarget.h:326
bool isCortexR5() const
Definition: ARMSubtarget.h:309
bool GenLongCalls
Generate calls via indirect call instructions.
Definition: ARMSubtarget.h:210
bool SupportsTailCall
SupportsTailCall - True if the OS supports tail call.
Definition: ARMSubtarget.h:122
bool restrictIT() const
Definition: ARMSubtarget.h:424
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:464
bool hasPerfMon() const
Definition: ARMSubtarget.h:338
bool hasV6MOps() const
Definition: ARMSubtarget.h:294
bool UseMulOps
UseMulOps - True if non-microcoded fused integer multiply-add and multiply-subtract instructions shou...
Definition: ARMSubtarget.h:87
const ARMBaseInstrInfo * getInstrInfo() const override
Definition: ARMSubtarget.h:262
bool isCortexA9() const
Definition: ARMSubtarget.h:304
bool isR9Reserved() const
Definition: ARMSubtarget.h:416
bool isTargetAEABI() const
Definition: ARMSubtarget.h:373
bool useSoftFloat() const
Definition: ARMSubtarget.h:403
bool hasV8Ops() const
Definition: ARMSubtarget.h:298
bool HasRAS
HasRAS - Some processors perform return stack prediction.
Definition: ARMSubtarget.h:161
bool hasVFP3() const
Definition: ARMSubtarget.h:315
bool hasThumb2() const
Definition: ARMSubtarget.h:407
bool isTargetELF() const
Definition: ARMSubtarget.h:363
bool isTargetDarwin() const
Definition: ARMSubtarget.h:355
bool HasZeroCycleZeroing
If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are particularly effective at zeroi...
Definition: ARMSubtarget.h:191
bool isRClass() const
Definition: ARMSubtarget.h:409
bool HasThumb2
HasThumb2 - True if Thumb2 instructions are supported.
Definition: ARMSubtarget.h:107
bool UnsafeFPMath
Target machine allowed unsafe FP math (such as use of NEON fp)
Definition: ARMSubtarget.h:213
bool isLittle() const
Definition: ARMSubtarget.h:428
bool hasMPExtension() const
Definition: ARMSubtarget.h:345
bool isFPBrccSlow() const
Definition: ARMSubtarget.h:336
bool isThumb() const
Definition: ARMSubtarget.h:404
bool hasV7Ops() const
Definition: ARMSubtarget.h:297
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:474
bool Pref32BitThumb
Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions over 16-bit ones...
Definition: ARMSubtarget.h:148
bool IsLittle
IsLittle - The target is Little Endian.
Definition: ARMSubtarget.h:223
const Triple & getTargetTriple() const
Definition: ARMSubtarget.h:353
bool isTargetCOFF() const
Definition: ARMSubtarget.h:362
bool enableAtomicExpand() const override
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
Definition: Triple.h:469
bool isTargetMachO() const
Definition: ARMSubtarget.h:364
bool NoARM
NoARM - True if subtarget does not support ARM mode execution.
Definition: ARMSubtarget.h:110
bool hasFPARMv8() const
Definition: ARMSubtarget.h:317
bool prefers32BitThumb() const
Definition: ARMSubtarget.h:341
bool hasCrypto() const
Definition: ARMSubtarget.h:319
bool hasNEON() const
Definition: ARMSubtarget.h:318
bool hasAnyDataBarrier() const
Definition: ARMSubtarget.h:330
Itinerary data supplied by a subtarget to be used by a target.
bool hasVFP4() const
Definition: ARMSubtarget.h:316
bool HasT2ExtractPack
HasT2ExtractPack - True if subtarget supports thumb2 extract/pack instructions.
Definition: ARMSubtarget.h:140
bool useMulOps() const
Definition: ARMSubtarget.h:333
bool hasARMOps() const
Definition: ARMSubtarget.h:312
bool HasPerfMon
If true, the processor supports the Performance Monitor Extensions.
Definition: ARMSubtarget.h:178
bool isOSNetBSD() const
Definition: Triple.h:408
bool isTargetIOS() const
Definition: ARMSubtarget.h:356
bool isTargetNetBSD() const
Definition: ARMSubtarget.h:359
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:399
bool AvoidMOVsShifterOperand
AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting movs with shifter operand ...
Definition: ARMSubtarget.h:157
bool HasCRC
HasCRC - if true, processor supports CRC instructions.
Definition: ARMSubtarget.h:187
bool HasVirtualization
HasVirtualization - True if the subtarget supports the Virtualization extension.
Definition: ARMSubtarget.h:169
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
Definition: ARMSubtarget.h:53
bool RestrictIT
RestrictIT - If true, the subtarget disallows generation of deprecated IT blocks to conform to ARMv8 ...
Definition: ARMSubtarget.h:200
bool isTargetHardFloat() const
Definition: ARMSubtarget.h:390
bool supportsTailCall() const
Definition: ARMSubtarget.h:420
bool isMClass() const
Definition: ARMSubtarget.h:408
bool UseMovt
UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit imms (including global add...
Definition: ARMSubtarget.h:117
bool hasVirtualization() const
Definition: ARMSubtarget.h:321
bool isCortexA5() const
Definition: ARMSubtarget.h:301
bool HasV4TOps
HasV4TOps, HasV5TOps, HasV5TEOps, HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops - Specify whether target support specific ARM ISA variants.
Definition: ARMSubtarget.h:61
bool HasVMLxForwarding
HasVMLxForwarding - If true, NEON has special multiplier accumulator forwarding to allow mul + mla be...
Definition: ARMSubtarget.h:95
bool isCortexM3() const
Definition: ARMSubtarget.h:307
bool HasCrypto
HasCrypto - if true, processor supports Cryptography extensions.
Definition: ARMSubtarget.h:184
bool Thumb2DSP
Thumb2DSP - If true, the subtarget supports the v7 DSP (saturating arith and such) instructions in Th...
Definition: ARMSubtarget.h:204
bool isKrait() const
Definition: ARMSubtarget.h:310
bool isCortexA15() const
Definition: ARMSubtarget.h:305
bool hasVMLxForwarding() const
Definition: ARMSubtarget.h:335
bool hasZeroCycleZeroing() const
Definition: ARMSubtarget.h:340
bool HasMPExtension
HasMPExtension - True if the subtarget supports Multiprocessing extension (ARMv7 only).
Definition: ARMSubtarget.h:165
bool useNEONForSinglePrecisionFP() const
Definition: ARMSubtarget.h:322
const ARMFrameLowering * getFrameLowering() const override
Definition: ARMSubtarget.h:268
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:484
unsigned getStackAlignment() const
getStackAlignment - Returns the minimum alignment known to hold of the stack frame on entry to the fu...
Definition: ARMSubtarget.h:451
bool hasSinCos() const
This function returns true if the target has sincos() routine in its compiler runtime or math librari...
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool HasFP16
HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF only so far) ...
Definition: ARMSubtarget.h:126
bool HasTrustZone
HasTrustZone - if true, processor supports TrustZone security extensions.
Definition: ARMSubtarget.h:181
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X or iOS).
Definition: Triple.h:404
bool genLongCalls() const
Definition: ARMSubtarget.h:348
bool InThumbMode
InThumbMode - True if compiling for Thumb, false for ARM.
Definition: ARMSubtarget.h:101
ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const ARMBaseTargetMachine &TM, bool IsLittle)
This constructor initializes the data members to match that of the specified triple.
bool hasV6KOps() const
Definition: ARMSubtarget.h:295
bool isTargetNaCl() const
Definition: ARMSubtarget.h:358
bool isSwift() const
Definition: ARMSubtarget.h:306
bool isV6M() const
Definition: ARMSubtarget.h:412
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const
GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
const InstrItineraryData * getInstrItineraryData() const override
getInstrItins - Return the instruction itineraries based on subtarget selection.
Definition: ARMSubtarget.h:444
bool FPOnlySP
FPOnlySP - If true, the floating point unit only supports single precision.
Definition: ARMSubtarget.h:173
ARMProcClassEnum ARMProcClass
ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
Definition: ARMSubtarget.h:56
bool hasVFP2() const
Definition: ARMSubtarget.h:314
bool isTargetAndroid() const
Definition: ARMSubtarget.h:396
bool UseNaClTrap
NaCl TRAP instruction is generated instead of the regular TRAP.
Definition: ARMSubtarget.h:207
unsigned getMaxInlineSizeThreshold() const
getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size that still makes it profitable t...
Definition: ARMSubtarget.h:248
MCSchedModel SchedModel
SchedModel - Processor specific instruction costs.
Definition: ARMSubtarget.h:229
bool isCortexA7() const
Definition: ARMSubtarget.h:302
const TargetOptions & Options
Options passed via command line that could influence the target.
Definition: ARMSubtarget.h:235
ARMSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
initializeSubtargetDependencies - Initializes using a CPU and feature string so that we can use initi...
bool UseSoftFloat
UseSoftFloat - True if we're using software floating point features.
Definition: ARMSubtarget.h:104
bool useNaClTrap() const
Definition: ARMSubtarget.h:347
bool IsR9Reserved
IsR9Reserved - True if R9 is a not available as general purpose register.
Definition: ARMSubtarget.h:113
bool isAPCS_ABI() const
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:479
bool isThumb2() const
Definition: ARMSubtarget.h:406
bool isAAPCS_ABI() const
bool hasV5TOps() const
Definition: ARMSubtarget.h:291
bool isTargetLinux() const
Definition: ARMSubtarget.h:357
InstrItineraryData InstrItins
Selected instruction itineraries (one entry per itinerary class.)
Definition: ARMSubtarget.h:232
bool UseNEONForSinglePrecisionFP
UseNEONForSinglePrecisionFP - if the NEONFP attribute has been specified.
Definition: ARMSubtarget.h:83
const ARMBaseRegisterInfo * getRegisterInfo() const override
Definition: ARMSubtarget.h:271
bool allowsUnalignedMem() const
Definition: ARMSubtarget.h:422
bool hasCRC() const
Definition: ARMSubtarget.h:320
bool useMovt(const MachineFunction &MF) const
EnvironmentType getEnvironment() const
getEnvironment - Get the parsed environment type of this triple.
Definition: Triple.h:260
bool hasTrustZone() const
Definition: ARMSubtarget.h:339
bool SlowFPBrcc
SlowFPBrcc - True if floating point compare + branch is slow.
Definition: ARMSubtarget.h:98
bool isLikeA9() const
Definition: ARMSubtarget.h:308
bool HasD16
HasD16 - True if subtarget is limited to 16 double precision FP registers for VFPv3.
Definition: ARMSubtarget.h:130
bool enablePostRAScheduler() const override
True for some subtargets at > -O0.
bool hasRAS() const
Definition: ARMSubtarget.h:344
bool AvoidCPSRPartialUpdate
AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions that partially update CPSR a...
Definition: ARMSubtarget.h:153
bool hasFP16() const
Definition: ARMSubtarget.h:350
bool hasDataBarrier() const
Definition: ARMSubtarget.h:329
std::string CPUString
CPUString - String name of used CPU.
Definition: ARMSubtarget.h:220
bool useFPVMLx() const
Definition: ARMSubtarget.h:334
bool hasDivideInARMMode() const
Definition: ARMSubtarget.h:327
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:40
bool hasD16() const
Definition: ARMSubtarget.h:351
bool HasDataBarrier
HasDataBarrier - True if the subtarget supports DMB / DSB data barrier instructions.
Definition: ARMSubtarget.h:144
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:136
bool hasThumb2DSP() const
Definition: ARMSubtarget.h:346
bool isTargetWindows() const
Definition: ARMSubtarget.h:360
bool HasHardwareDivide
HasHardwareDivide - True if subtarget supports [su]div.
Definition: ARMSubtarget.h:133