LLVM  3.7.0
SystemZISelLowering.h
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1 //===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that SystemZ uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
16 #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
17 
18 #include "SystemZ.h"
22 
23 namespace llvm {
24 namespace SystemZISD {
25 enum NodeType : unsigned {
27 
28  // Return with a flag operand. Operand 0 is the chain operand.
30 
31  // Calls a function. Operand 0 is the chain operand and operand 1
32  // is the target address. The arguments start at operand 2.
33  // There is an optional glue operand at the end.
36 
37  // TLS calls. Like regular calls, except operand 1 is the TLS symbol.
38  // (The call target is implicitly __tls_get_offset.)
41 
42  // Wraps a TargetGlobalAddress that should be loaded using PC-relative
43  // accesses (LARL). Operand 0 is the address.
45 
46  // Used in cases where an offset is applied to a TargetGlobalAddress.
47  // Operand 0 is the full TargetGlobalAddress and operand 1 is a
48  // PCREL_WRAPPER for an anchor point. This is used so that we can
49  // cheaply refer to either the full address or the anchor point
50  // as a register base.
52 
53  // Integer absolute.
55 
56  // Integer comparisons. There are three operands: the two values
57  // to compare, and an integer of type SystemZICMP.
59 
60  // Floating-point comparisons. The two operands are the values to compare.
62 
63  // Test under mask. The first operand is ANDed with the second operand
64  // and the condition codes are set on the result. The third operand is
65  // a boolean that is true if the condition codes need to distinguish
66  // between CCMASK_TM_MIXED_MSB_0 and CCMASK_TM_MIXED_MSB_1 (which the
67  // register forms do but the memory forms don't).
68  TM,
69 
70  // Branches if a condition is true. Operand 0 is the chain operand;
71  // operand 1 is the 4-bit condition-code mask, with bit N in
72  // big-endian order meaning "branch if CC=N"; operand 2 is the
73  // target block and operand 3 is the flag operand.
75 
76  // Selects between operand 0 and operand 1. Operand 2 is the
77  // mask of condition-code values for which operand 0 should be
78  // chosen over operand 1; it has the same form as BR_CCMASK.
79  // Operand 3 is the flag operand.
81 
82  // Evaluates to the gap between the stack pointer and the
83  // base of the dynamically-allocatable area.
85 
86  // Extracts the value of a 32-bit access register. Operand 0 is
87  // the number of the register.
89 
90  // Count number of bits set in operand 0 per byte.
92 
93  // Wrappers around the ISD opcodes of the same name. The output and
94  // first input operands are GR128s. The trailing numbers are the
95  // widths of the second operand in bits.
101 
102  // Use a series of MVCs to copy bytes from one memory location to another.
103  // The operands are:
104  // - the target address
105  // - the source address
106  // - the constant length
107  //
108  // This isn't a memory opcode because we'd need to attach two
109  // MachineMemOperands rather than one.
111 
112  // Like MVC, but implemented as a loop that handles X*256 bytes
113  // followed by straight-line code to handle the rest (if any).
114  // The value of X is passed as an additional operand.
116 
117  // Similar to MVC and MVC_LOOP, but for logic operations (AND, OR, XOR).
118  NC,
120  OC,
122  XC,
124 
125  // Use CLC to compare two blocks of memory, with the same comments
126  // as for MVC and MVC_LOOP.
129 
130  // Use an MVST-based sequence to implement stpcpy().
132 
133  // Use a CLST-based sequence to implement strcmp(). The two input operands
134  // are the addresses of the strings to compare.
136 
137  // Use an SRST-based sequence to search a block of memory. The first
138  // operand is the end address, the second is the start, and the third
139  // is the character to search for. CC is set to 1 on success and 2
140  // on failure.
142 
143  // Store the CC value in bits 29 and 28 of an integer.
145 
146  // Perform a serialization operation. (BCR 15,0 or BCR 14,0.)
148 
149  // Transaction begin. The first operand is the chain, the second
150  // the TDB pointer, and the third the immediate control field.
151  // Returns chain and glue.
154 
155  // Transaction end. Just the chain operand. Returns chain and glue.
157 
158  // Create a vector constant by filling byte N of the result with bit
159  // 15-N of the single operand.
161 
162  // Create a vector constant by replicating an element-sized RISBG-style mask.
163  // The first operand specifies the starting set bit and the second operand
164  // specifies the ending set bit. Both operands count from the MSB of the
165  // element.
167 
168  // Replicate a GPR scalar value into all elements of a vector.
170 
171  // Create a vector from two i64 GPRs.
173 
174  // Replicate one element of a vector into all elements. The first operand
175  // is the vector and the second is the index of the element to replicate.
177 
178  // Interleave elements from the high half of operand 0 and the high half
179  // of operand 1.
181 
182  // Likewise for the low halves.
184 
185  // Concatenate the vectors in the first two operands, shift them left
186  // by the third operand, and take the first half of the result.
188 
189  // Take one element of the first v2i64 operand and the one element of
190  // the second v2i64 operand and concatenate them to form a v2i64 result.
191  // The third operand is a 4-bit value of the form 0A0B, where A and B
192  // are the element selectors for the first operand and second operands
193  // respectively.
195 
196  // Perform a general vector permute on vector operands 0 and 1.
197  // Each byte of operand 2 controls the corresponding byte of the result,
198  // in the same way as a byte-level VECTOR_SHUFFLE mask.
200 
201  // Pack vector operands 0 and 1 into a single vector with half-sized elements.
203 
204  // Likewise, but saturate the result and set CC. PACKS_CC does signed
205  // saturation and PACKLS_CC does unsigned saturation.
208 
209  // Unpack the first half of vector operand 0 into double-sized elements.
210  // UNPACK_HIGH sign-extends and UNPACKL_HIGH zero-extends.
213 
214  // Likewise for the second half.
217 
218  // Shift each element of vector operand 0 by the number of bits specified
219  // by scalar operand 1.
223 
224  // For each element of the output type, sum across all sub-elements of
225  // operand 0 belonging to the corresponding element, and add in the
226  // rightmost sub-element of the corresponding element of operand 1.
228 
229  // Compare integer vector operands 0 and 1 to produce the usual 0/-1
230  // vector result. VICMPE is for equality, VICMPH for "signed greater than"
231  // and VICMPHL for "unsigned greater than".
235 
236  // Likewise, but also set the condition codes on the result.
240 
241  // Compare floating-point vector operands 0 and 1 to preoduce the usual 0/-1
242  // vector result. VFCMPE is for "ordered and equal", VFCMPH for "ordered and
243  // greater than" and VFCMPHE for "ordered and greater than or equal to".
247 
248  // Likewise, but also set the condition codes on the result.
252 
253  // Test floating-point data class for vectors.
255 
256  // Extend the even f32 elements of vector operand 0 to produce a vector
257  // of f64 elements.
259 
260  // Round the f64 elements of vector operand 0 to f32s and store them in the
261  // even elements of the result.
263 
264  // AND the two vector operands together and set CC based on the result.
266 
267  // String operations that set CC as a side-effect.
277 
278  // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or
279  // ATOMIC_LOAD_<op>.
280  //
281  // Operand 0: the address of the containing 32-bit-aligned field
282  // Operand 1: the second operand of <op>, in the high bits of an i32
283  // for everything except ATOMIC_SWAPW
284  // Operand 2: how many bits to rotate the i32 left to bring the first
285  // operand into the high bits
286  // Operand 3: the negative of operand 2, for rotating the other way
287  // Operand 4: the width of the field in bits (8 or 16)
299 
300  // A wrapper around the inner loop of an ATOMIC_CMP_SWAP.
301  //
302  // Operand 0: the address of the containing 32-bit-aligned field
303  // Operand 1: the compare value, in the low bits of an i32
304  // Operand 2: the swap value, in the low bits of an i32
305  // Operand 3: how many bits to rotate the i32 left to bring the first
306  // operand into the high bits
307  // Operand 4: the negative of operand 2, for rotating the other way
308  // Operand 5: the width of the field in bits (8 or 16)
310 
311  // Prefetch from the second operand using the 4-bit control code in
312  // the first operand. The code is 1 for a load prefetch and 2 for
313  // a store prefetch.
315 };
316 
317 // Return true if OPCODE is some kind of PC-relative address.
318 inline bool isPCREL(unsigned Opcode) {
319  return Opcode == PCREL_WRAPPER || Opcode == PCREL_OFFSET;
320 }
321 } // end namespace SystemZISD
322 
323 namespace SystemZICMP {
324 // Describes whether an integer comparison needs to be signed or unsigned,
325 // or whether either type is OK.
326 enum {
330 };
331 } // end namespace SystemZICMP
332 
333 class SystemZSubtarget;
334 class SystemZTargetMachine;
335 
337 public:
338  explicit SystemZTargetLowering(const TargetMachine &TM,
339  const SystemZSubtarget &STI);
340 
341  // Override TargetLowering.
342  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
343  return MVT::i32;
344  }
345  MVT getVectorIdxTy(const DataLayout &DL) const override {
346  // Only the lower 12 bits of an element index are used, so we don't
347  // want to clobber the upper 32 bits of a GPR unnecessarily.
348  return MVT::i32;
349  }
351  const override {
352  // Widen subvectors to the full width rather than promoting integer
353  // elements. This is better because:
354  //
355  // (a) it means that we can handle the ABI for passing and returning
356  // sub-128 vectors without having to handle them as legal types.
357  //
358  // (b) we don't have instructions to extend on load and truncate on store,
359  // so promoting the integers is less efficient.
360  //
361  // (c) there are no multiplication instructions for the widest integer
362  // type (v2i64).
363  if (VT.getVectorElementType().getSizeInBits() % 8 == 0)
364  return TypeWidenVector;
366  }
368  EVT) const override;
369  bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
370  bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
371  bool isLegalICmpImmediate(int64_t Imm) const override;
372  bool isLegalAddImmediate(int64_t Imm) const override;
373  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
374  unsigned AS) const override;
375  bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS,
376  unsigned Align,
377  bool *Fast) const override;
378  bool isTruncateFree(Type *, Type *) const override;
379  bool isTruncateFree(EVT, EVT) const override;
380  const char *getTargetNodeName(unsigned Opcode) const override;
381  std::pair<unsigned, const TargetRegisterClass *>
383  StringRef Constraint, MVT VT) const override;
385  getConstraintType(StringRef Constraint) const override;
387  getSingleConstraintMatchWeight(AsmOperandInfo &info,
388  const char *constraint) const override;
390  std::string &Constraint,
391  std::vector<SDValue> &Ops,
392  SelectionDAG &DAG) const override;
393 
394  unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
395  if (ConstraintCode.size() == 1) {
396  switch(ConstraintCode[0]) {
397  default:
398  break;
399  case 'Q':
401  case 'R':
403  case 'S':
405  case 'T':
407  }
408  }
409  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
410  }
411 
413  MachineBasicBlock *BB) const
414  override;
415  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
416  bool allowTruncateForTailCall(Type *, Type *) const override;
417  bool mayBeEmittedAsTailCall(CallInst *CI) const override;
419  bool isVarArg,
421  SDLoc DL, SelectionDAG &DAG,
422  SmallVectorImpl<SDValue> &InVals) const override;
423  SDValue LowerCall(CallLoweringInfo &CLI,
424  SmallVectorImpl<SDValue> &InVals) const override;
425 
427  bool isVarArg,
429  LLVMContext &Context) const override;
430  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
432  const SmallVectorImpl<SDValue> &OutVals,
433  SDLoc DL, SelectionDAG &DAG) const override;
435  SelectionDAG &DAG) const override;
436  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
437 
438 private:
439  const SystemZSubtarget &Subtarget;
440 
441  // Implement LowerOperation for individual opcodes.
442  SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
443  SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
444  SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
445  SDValue lowerGlobalAddress(GlobalAddressSDNode *Node,
446  SelectionDAG &DAG) const;
447  SDValue lowerTLSGetOffset(GlobalAddressSDNode *Node,
448  SelectionDAG &DAG, unsigned Opcode,
449  SDValue GOTOffset) const;
450  SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
451  SelectionDAG &DAG) const;
452  SDValue lowerBlockAddress(BlockAddressSDNode *Node,
453  SelectionDAG &DAG) const;
454  SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const;
455  SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const;
456  SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
457  SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
458  SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
459  SDValue lowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
460  SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
461  SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
462  SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
463  SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
464  SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const;
465  SDValue lowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
466  SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const;
467  SDValue lowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;
468  SDValue lowerATOMIC_LOAD_OP(SDValue Op, SelectionDAG &DAG,
469  unsigned Opcode) const;
470  SDValue lowerATOMIC_LOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
471  SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
472  SDValue lowerLOAD_SEQUENCE_POINT(SDValue Op, SelectionDAG &DAG) const;
473  SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
474  SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
475  SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
476  SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
477  SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
478  SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
479  SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
480  SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
481  SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
482  SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
483  SDValue lowerExtendVectorInreg(SDValue Op, SelectionDAG &DAG,
484  unsigned UnpackHigh) const;
485  SDValue lowerShift(SDValue Op, SelectionDAG &DAG, unsigned ByScalar) const;
486 
487  SDValue combineExtract(SDLoc DL, EVT ElemVT, EVT VecVT, SDValue OrigOp,
488  unsigned Index, DAGCombinerInfo &DCI,
489  bool Force) const;
490  SDValue combineTruncateExtract(SDLoc DL, EVT TruncVT, SDValue Op,
491  DAGCombinerInfo &DCI) const;
492 
493  // If the last instruction before MBBI in MBB was some form of COMPARE,
494  // try to replace it with a COMPARE AND BRANCH just before MBBI.
495  // CCMask and Target are the BRC-like operands for the branch.
496  // Return true if the change was made.
497  bool convertPrevCompareToBranch(MachineBasicBlock *MBB,
499  unsigned CCMask,
500  MachineBasicBlock *Target) const;
501 
502  // Implement EmitInstrWithCustomInserter for individual operation types.
503  MachineBasicBlock *emitSelect(MachineInstr *MI,
504  MachineBasicBlock *BB) const;
505  MachineBasicBlock *emitCondStore(MachineInstr *MI,
506  MachineBasicBlock *BB,
507  unsigned StoreOpcode, unsigned STOCOpcode,
508  bool Invert) const;
509  MachineBasicBlock *emitExt128(MachineInstr *MI,
510  MachineBasicBlock *MBB,
511  bool ClearEven, unsigned SubReg) const;
512  MachineBasicBlock *emitAtomicLoadBinary(MachineInstr *MI,
513  MachineBasicBlock *BB,
514  unsigned BinOpcode, unsigned BitSize,
515  bool Invert = false) const;
516  MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr *MI,
517  MachineBasicBlock *MBB,
518  unsigned CompareOpcode,
519  unsigned KeepOldMask,
520  unsigned BitSize) const;
521  MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr *MI,
522  MachineBasicBlock *BB) const;
523  MachineBasicBlock *emitMemMemWrapper(MachineInstr *MI,
524  MachineBasicBlock *BB,
525  unsigned Opcode) const;
526  MachineBasicBlock *emitStringWrapper(MachineInstr *MI,
527  MachineBasicBlock *BB,
528  unsigned Opcode) const;
529  MachineBasicBlock *emitTransactionBegin(MachineInstr *MI,
530  MachineBasicBlock *MBB,
531  unsigned Opcode,
532  bool NoFloat) const;
533 };
534 } // end namespace llvm
535 
536 #endif
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:724
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:104
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &, EVT) const override
Return the ValueType of the result of SETCC operations.
size_t size() const
size - Get the string size.
Definition: StringRef.h:113
CallInst - This class represents a function call, abstracting a target machine's calling convention...
bool mayBeEmittedAsTailCall(CallInst *CI) const override
Return true if the target may be able emit the call instruction as a tail call.
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
bool isLegalAddImmediate(int64_t Imm) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, SDLoc DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array...
TargetLowering::ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
MVT getVectorIdxTy(const DataLayout &DL) const override
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
lazy value info
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
EVT getVectorElementType() const
getVectorElementType - Given a vector type, return the type of each element.
Definition: ValueTypes.h:216
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
bool isLegalICmpImmediate(int64_t Imm) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
bool isTruncateFree(Type *, Type *) const override
Return true if it's free to truncate a value of type Ty1 to type Ty2.
SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
SystemZTargetLowering(const TargetMachine &TM, const SystemZSubtarget &STI)
A self-contained host- and target-independent arbitrary-precision floating-point software implementat...
Definition: APFloat.h:122
MVT - Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:41
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, SDLoc DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array...
bundle_iterator - MachineBasicBlock iterator that automatically skips over MIs that are inside bundle...
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
bool isPCREL(unsigned Opcode)
EVT - Extended Value Type.
Definition: ValueTypes.h:31
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align, bool *Fast) const override
Determine if the target supports unaligned memory accesses.
bool allowTruncateForTailCall(Type *, Type *) const override
Return true if a truncation from Ty1 to Ty2 is permitted when deciding whether a call is in tail posi...
TargetLowering::ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT) const override
Return the preferred vector type legalization action.
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:179
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
SDValue prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL, SelectionDAG &DAG) const override
This callback is used to prepare for a volatile or atomic load.
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:731
Represents one node in the SelectionDAG.
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
Target - Wrapper for Target specific information.
AddrMode
ARM Addressing Modes.
Definition: ARMBaseInfo.h:235
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT) const
Return the preferred vector type legalization action.
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
Representation of each machine instruction.
Definition: MachineInstr.h:51
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:233
#define N
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
bool isFPImmLegal(const APFloat &Imm, EVT VT) const override
Returns true if the target can instruction select the specified FP immediate natively.
Primary interface to the complete machine description for the target machine.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:40
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
bool isFMAFasterThanFMulAndFAdd(EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
This file describes how to lower LLVM code to machine code.