LLVM  3.7.0
PPCAsmParser.cpp
Go to the documentation of this file.
1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
11 #include "MCTargetDesc/PPCMCExpr.h"
12 #include "PPCTargetStreamer.h"
13 #include "llvm/ADT/STLExtras.h"
14 #include "llvm/ADT/SmallString.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringSwitch.h"
17 #include "llvm/ADT/Twine.h"
18 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
25 #include "llvm/MC/MCRegisterInfo.h"
26 #include "llvm/MC/MCStreamer.h"
27 #include "llvm/MC/MCSymbolELF.h"
30 #include "llvm/Support/SourceMgr.h"
33 
34 using namespace llvm;
35 
36 static const MCPhysReg RRegs[32] = {
37  PPC::R0, PPC::R1, PPC::R2, PPC::R3,
38  PPC::R4, PPC::R5, PPC::R6, PPC::R7,
39  PPC::R8, PPC::R9, PPC::R10, PPC::R11,
40  PPC::R12, PPC::R13, PPC::R14, PPC::R15,
41  PPC::R16, PPC::R17, PPC::R18, PPC::R19,
42  PPC::R20, PPC::R21, PPC::R22, PPC::R23,
43  PPC::R24, PPC::R25, PPC::R26, PPC::R27,
44  PPC::R28, PPC::R29, PPC::R30, PPC::R31
45 };
46 static const MCPhysReg RRegsNoR0[32] = {
47  PPC::ZERO,
48  PPC::R1, PPC::R2, PPC::R3,
49  PPC::R4, PPC::R5, PPC::R6, PPC::R7,
50  PPC::R8, PPC::R9, PPC::R10, PPC::R11,
51  PPC::R12, PPC::R13, PPC::R14, PPC::R15,
52  PPC::R16, PPC::R17, PPC::R18, PPC::R19,
53  PPC::R20, PPC::R21, PPC::R22, PPC::R23,
54  PPC::R24, PPC::R25, PPC::R26, PPC::R27,
55  PPC::R28, PPC::R29, PPC::R30, PPC::R31
56 };
57 static const MCPhysReg XRegs[32] = {
58  PPC::X0, PPC::X1, PPC::X2, PPC::X3,
59  PPC::X4, PPC::X5, PPC::X6, PPC::X7,
60  PPC::X8, PPC::X9, PPC::X10, PPC::X11,
61  PPC::X12, PPC::X13, PPC::X14, PPC::X15,
62  PPC::X16, PPC::X17, PPC::X18, PPC::X19,
63  PPC::X20, PPC::X21, PPC::X22, PPC::X23,
64  PPC::X24, PPC::X25, PPC::X26, PPC::X27,
65  PPC::X28, PPC::X29, PPC::X30, PPC::X31
66 };
67 static const MCPhysReg XRegsNoX0[32] = {
68  PPC::ZERO8,
69  PPC::X1, PPC::X2, PPC::X3,
70  PPC::X4, PPC::X5, PPC::X6, PPC::X7,
71  PPC::X8, PPC::X9, PPC::X10, PPC::X11,
72  PPC::X12, PPC::X13, PPC::X14, PPC::X15,
73  PPC::X16, PPC::X17, PPC::X18, PPC::X19,
74  PPC::X20, PPC::X21, PPC::X22, PPC::X23,
75  PPC::X24, PPC::X25, PPC::X26, PPC::X27,
76  PPC::X28, PPC::X29, PPC::X30, PPC::X31
77 };
78 static const MCPhysReg FRegs[32] = {
79  PPC::F0, PPC::F1, PPC::F2, PPC::F3,
80  PPC::F4, PPC::F5, PPC::F6, PPC::F7,
81  PPC::F8, PPC::F9, PPC::F10, PPC::F11,
82  PPC::F12, PPC::F13, PPC::F14, PPC::F15,
83  PPC::F16, PPC::F17, PPC::F18, PPC::F19,
84  PPC::F20, PPC::F21, PPC::F22, PPC::F23,
85  PPC::F24, PPC::F25, PPC::F26, PPC::F27,
86  PPC::F28, PPC::F29, PPC::F30, PPC::F31
87 };
88 static const MCPhysReg VRegs[32] = {
89  PPC::V0, PPC::V1, PPC::V2, PPC::V3,
90  PPC::V4, PPC::V5, PPC::V6, PPC::V7,
91  PPC::V8, PPC::V9, PPC::V10, PPC::V11,
92  PPC::V12, PPC::V13, PPC::V14, PPC::V15,
93  PPC::V16, PPC::V17, PPC::V18, PPC::V19,
94  PPC::V20, PPC::V21, PPC::V22, PPC::V23,
95  PPC::V24, PPC::V25, PPC::V26, PPC::V27,
96  PPC::V28, PPC::V29, PPC::V30, PPC::V31
97 };
98 static const MCPhysReg VSRegs[64] = {
99  PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3,
100  PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7,
101  PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11,
102  PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15,
103  PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19,
104  PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23,
105  PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27,
106  PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31,
107 
108  PPC::VSH0, PPC::VSH1, PPC::VSH2, PPC::VSH3,
109  PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7,
110  PPC::VSH8, PPC::VSH9, PPC::VSH10, PPC::VSH11,
111  PPC::VSH12, PPC::VSH13, PPC::VSH14, PPC::VSH15,
112  PPC::VSH16, PPC::VSH17, PPC::VSH18, PPC::VSH19,
113  PPC::VSH20, PPC::VSH21, PPC::VSH22, PPC::VSH23,
114  PPC::VSH24, PPC::VSH25, PPC::VSH26, PPC::VSH27,
115  PPC::VSH28, PPC::VSH29, PPC::VSH30, PPC::VSH31
116 };
117 static const MCPhysReg VSFRegs[64] = {
118  PPC::F0, PPC::F1, PPC::F2, PPC::F3,
119  PPC::F4, PPC::F5, PPC::F6, PPC::F7,
120  PPC::F8, PPC::F9, PPC::F10, PPC::F11,
121  PPC::F12, PPC::F13, PPC::F14, PPC::F15,
122  PPC::F16, PPC::F17, PPC::F18, PPC::F19,
123  PPC::F20, PPC::F21, PPC::F22, PPC::F23,
124  PPC::F24, PPC::F25, PPC::F26, PPC::F27,
125  PPC::F28, PPC::F29, PPC::F30, PPC::F31,
126 
127  PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3,
128  PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
129  PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11,
130  PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
131  PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
132  PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
133  PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
134  PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
135 };
136 static const MCPhysReg VSSRegs[64] = {
137  PPC::F0, PPC::F1, PPC::F2, PPC::F3,
138  PPC::F4, PPC::F5, PPC::F6, PPC::F7,
139  PPC::F8, PPC::F9, PPC::F10, PPC::F11,
140  PPC::F12, PPC::F13, PPC::F14, PPC::F15,
141  PPC::F16, PPC::F17, PPC::F18, PPC::F19,
142  PPC::F20, PPC::F21, PPC::F22, PPC::F23,
143  PPC::F24, PPC::F25, PPC::F26, PPC::F27,
144  PPC::F28, PPC::F29, PPC::F30, PPC::F31,
145 
146  PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3,
147  PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
148  PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11,
149  PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
150  PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
151  PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
152  PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
153  PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
154 };
155 static unsigned QFRegs[32] = {
156  PPC::QF0, PPC::QF1, PPC::QF2, PPC::QF3,
157  PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7,
158  PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11,
159  PPC::QF12, PPC::QF13, PPC::QF14, PPC::QF15,
160  PPC::QF16, PPC::QF17, PPC::QF18, PPC::QF19,
161  PPC::QF20, PPC::QF21, PPC::QF22, PPC::QF23,
162  PPC::QF24, PPC::QF25, PPC::QF26, PPC::QF27,
163  PPC::QF28, PPC::QF29, PPC::QF30, PPC::QF31
164 };
165 static const MCPhysReg CRBITRegs[32] = {
166  PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
167  PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
168  PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
169  PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
170  PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
171  PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
172  PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
173  PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
174 };
175 static const MCPhysReg CRRegs[8] = {
176  PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
177  PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
178 };
179 
180 // Evaluate an expression containing condition register
181 // or condition register field symbols. Returns positive
182 // value on success, or -1 on error.
183 static int64_t
185  switch (E->getKind()) {
186  case MCExpr::Target:
187  return -1;
188 
189  case MCExpr::Constant: {
190  int64_t Res = cast<MCConstantExpr>(E)->getValue();
191  return Res < 0 ? -1 : Res;
192  }
193 
194  case MCExpr::SymbolRef: {
195  const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
196  StringRef Name = SRE->getSymbol().getName();
197 
198  if (Name == "lt") return 0;
199  if (Name == "gt") return 1;
200  if (Name == "eq") return 2;
201  if (Name == "so") return 3;
202  if (Name == "un") return 3;
203 
204  if (Name == "cr0") return 0;
205  if (Name == "cr1") return 1;
206  if (Name == "cr2") return 2;
207  if (Name == "cr3") return 3;
208  if (Name == "cr4") return 4;
209  if (Name == "cr5") return 5;
210  if (Name == "cr6") return 6;
211  if (Name == "cr7") return 7;
212 
213  return -1;
214  }
215 
216  case MCExpr::Unary:
217  return -1;
218 
219  case MCExpr::Binary: {
220  const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
221  int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
222  int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
223  int64_t Res;
224 
225  if (LHSVal < 0 || RHSVal < 0)
226  return -1;
227 
228  switch (BE->getOpcode()) {
229  default: return -1;
230  case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
231  case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
232  }
233 
234  return Res < 0 ? -1 : Res;
235  }
236  }
237 
238  llvm_unreachable("Invalid expression kind!");
239 }
240 
241 namespace {
242 
243 struct PPCOperand;
244 
245 class PPCAsmParser : public MCTargetAsmParser {
246  MCSubtargetInfo &STI;
247  const MCInstrInfo &MII;
248  bool IsPPC64;
249  bool IsDarwin;
250 
251  void Warning(SMLoc L, const Twine &Msg) { getParser().Warning(L, Msg); }
252  bool Error(SMLoc L, const Twine &Msg) { return getParser().Error(L, Msg); }
253 
254  bool isPPC64() const { return IsPPC64; }
255  bool isDarwin() const { return IsDarwin; }
256 
257  bool MatchRegisterName(const AsmToken &Tok,
258  unsigned &RegNo, int64_t &IntVal);
259 
260  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
261 
262  const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
264  const MCExpr *FixupVariantKind(const MCExpr *E);
265  bool ParseExpression(const MCExpr *&EVal);
266  bool ParseDarwinExpression(const MCExpr *&EVal);
267 
268  bool ParseOperand(OperandVector &Operands);
269 
270  bool ParseDirectiveWord(unsigned Size, SMLoc L);
271  bool ParseDirectiveTC(unsigned Size, SMLoc L);
272  bool ParseDirectiveMachine(SMLoc L);
273  bool ParseDarwinDirectiveMachine(SMLoc L);
274  bool ParseDirectiveAbiVersion(SMLoc L);
275  bool ParseDirectiveLocalEntry(SMLoc L);
276 
277  bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
279  uint64_t &ErrorInfo,
280  bool MatchingInlineAsm) override;
281 
282  void ProcessInstruction(MCInst &Inst, const OperandVector &Ops);
283 
284  /// @name Auto-generated Match Functions
285  /// {
286 
287 #define GET_ASSEMBLER_HEADER
288 #include "PPCGenAsmMatcher.inc"
289 
290  /// }
291 
292 
293 public:
294  PPCAsmParser(MCSubtargetInfo &STI, MCAsmParser &, const MCInstrInfo &MII,
295  const MCTargetOptions &Options)
296  : MCTargetAsmParser(), STI(STI), MII(MII) {
297  // Check for 64-bit vs. 32-bit pointer mode.
298  Triple TheTriple(STI.getTargetTriple());
299  IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
300  TheTriple.getArch() == Triple::ppc64le);
301  IsDarwin = TheTriple.isMacOSX();
302  // Initialize the set of available features.
303  setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
304  }
305 
306  bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
307  SMLoc NameLoc, OperandVector &Operands) override;
308 
309  bool ParseDirective(AsmToken DirectiveID) override;
310 
311  unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
312  unsigned Kind) override;
313 
314  const MCExpr *applyModifierToExpr(const MCExpr *E,
316  MCContext &Ctx) override;
317 };
318 
319 /// PPCOperand - Instances of this class represent a parsed PowerPC machine
320 /// instruction.
321 struct PPCOperand : public MCParsedAsmOperand {
322  enum KindTy {
323  Token,
324  Immediate,
325  ContextImmediate,
326  Expression,
327  TLSRegister
328  } Kind;
329 
330  SMLoc StartLoc, EndLoc;
331  bool IsPPC64;
332 
333  struct TokOp {
334  const char *Data;
335  unsigned Length;
336  };
337 
338  struct ImmOp {
339  int64_t Val;
340  };
341 
342  struct ExprOp {
343  const MCExpr *Val;
344  int64_t CRVal; // Cached result of EvaluateCRExpr(Val)
345  };
346 
347  struct TLSRegOp {
348  const MCSymbolRefExpr *Sym;
349  };
350 
351  union {
352  struct TokOp Tok;
353  struct ImmOp Imm;
354  struct ExprOp Expr;
355  struct TLSRegOp TLSReg;
356  };
357 
358  PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
359 public:
360  PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
361  Kind = o.Kind;
362  StartLoc = o.StartLoc;
363  EndLoc = o.EndLoc;
364  IsPPC64 = o.IsPPC64;
365  switch (Kind) {
366  case Token:
367  Tok = o.Tok;
368  break;
369  case Immediate:
370  case ContextImmediate:
371  Imm = o.Imm;
372  break;
373  case Expression:
374  Expr = o.Expr;
375  break;
376  case TLSRegister:
377  TLSReg = o.TLSReg;
378  break;
379  }
380  }
381 
382  /// getStartLoc - Get the location of the first token of this operand.
383  SMLoc getStartLoc() const override { return StartLoc; }
384 
385  /// getEndLoc - Get the location of the last token of this operand.
386  SMLoc getEndLoc() const override { return EndLoc; }
387 
388  /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
389  bool isPPC64() const { return IsPPC64; }
390 
391  int64_t getImm() const {
392  assert(Kind == Immediate && "Invalid access!");
393  return Imm.Val;
394  }
395  int64_t getImmS16Context() const {
396  assert((Kind == Immediate || Kind == ContextImmediate) && "Invalid access!");
397  if (Kind == Immediate)
398  return Imm.Val;
399  return static_cast<int16_t>(Imm.Val);
400  }
401  int64_t getImmU16Context() const {
402  assert((Kind == Immediate || Kind == ContextImmediate) && "Invalid access!");
403  return Imm.Val;
404  }
405 
406  const MCExpr *getExpr() const {
407  assert(Kind == Expression && "Invalid access!");
408  return Expr.Val;
409  }
410 
411  int64_t getExprCRVal() const {
412  assert(Kind == Expression && "Invalid access!");
413  return Expr.CRVal;
414  }
415 
416  const MCExpr *getTLSReg() const {
417  assert(Kind == TLSRegister && "Invalid access!");
418  return TLSReg.Sym;
419  }
420 
421  unsigned getReg() const override {
422  assert(isRegNumber() && "Invalid access!");
423  return (unsigned) Imm.Val;
424  }
425 
426  unsigned getVSReg() const {
427  assert(isVSRegNumber() && "Invalid access!");
428  return (unsigned) Imm.Val;
429  }
430 
431  unsigned getCCReg() const {
432  assert(isCCRegNumber() && "Invalid access!");
433  return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
434  }
435 
436  unsigned getCRBit() const {
437  assert(isCRBitNumber() && "Invalid access!");
438  return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
439  }
440 
441  unsigned getCRBitMask() const {
442  assert(isCRBitMask() && "Invalid access!");
443  return 7 - countTrailingZeros<uint64_t>(Imm.Val);
444  }
445 
446  bool isToken() const override { return Kind == Token; }
447  bool isImm() const override { return Kind == Immediate || Kind == Expression; }
448  bool isU1Imm() const { return Kind == Immediate && isUInt<1>(getImm()); }
449  bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); }
450  bool isU3Imm() const { return Kind == Immediate && isUInt<3>(getImm()); }
451  bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); }
452  bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
453  bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
454  bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
455  bool isU6ImmX2() const { return Kind == Immediate &&
456  isUInt<6>(getImm()) &&
457  (getImm() & 1) == 0; }
458  bool isU7ImmX4() const { return Kind == Immediate &&
459  isUInt<7>(getImm()) &&
460  (getImm() & 3) == 0; }
461  bool isU8ImmX8() const { return Kind == Immediate &&
462  isUInt<8>(getImm()) &&
463  (getImm() & 7) == 0; }
464 
465  bool isU10Imm() const { return Kind == Immediate && isUInt<10>(getImm()); }
466  bool isU12Imm() const { return Kind == Immediate && isUInt<12>(getImm()); }
467  bool isU16Imm() const {
468  switch (Kind) {
469  case Expression:
470  return true;
471  case Immediate:
472  case ContextImmediate:
473  return isUInt<16>(getImmU16Context());
474  default:
475  return false;
476  }
477  }
478  bool isS16Imm() const {
479  switch (Kind) {
480  case Expression:
481  return true;
482  case Immediate:
483  case ContextImmediate:
484  return isInt<16>(getImmS16Context());
485  default:
486  return false;
487  }
488  }
489  bool isS16ImmX4() const { return Kind == Expression ||
490  (Kind == Immediate && isInt<16>(getImm()) &&
491  (getImm() & 3) == 0); }
492  bool isS17Imm() const {
493  switch (Kind) {
494  case Expression:
495  return true;
496  case Immediate:
497  case ContextImmediate:
498  return isInt<17>(getImmS16Context());
499  default:
500  return false;
501  }
502  }
503  bool isTLSReg() const { return Kind == TLSRegister; }
504  bool isDirectBr() const {
505  if (Kind == Expression)
506  return true;
507  if (Kind != Immediate)
508  return false;
509  // Operand must be 64-bit aligned, signed 27-bit immediate.
510  if ((getImm() & 3) != 0)
511  return false;
512  if (isInt<26>(getImm()))
513  return true;
514  if (!IsPPC64) {
515  // In 32-bit mode, large 32-bit quantities wrap around.
516  if (isUInt<32>(getImm()) && isInt<26>(static_cast<int32_t>(getImm())))
517  return true;
518  }
519  return false;
520  }
521  bool isCondBr() const { return Kind == Expression ||
522  (Kind == Immediate && isInt<16>(getImm()) &&
523  (getImm() & 3) == 0); }
524  bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
525  bool isVSRegNumber() const { return Kind == Immediate && isUInt<6>(getImm()); }
526  bool isCCRegNumber() const { return (Kind == Expression
527  && isUInt<3>(getExprCRVal())) ||
528  (Kind == Immediate
529  && isUInt<3>(getImm())); }
530  bool isCRBitNumber() const { return (Kind == Expression
531  && isUInt<5>(getExprCRVal())) ||
532  (Kind == Immediate
533  && isUInt<5>(getImm())); }
534  bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
535  isPowerOf2_32(getImm()); }
536  bool isMem() const override { return false; }
537  bool isReg() const override { return false; }
538 
539  void addRegOperands(MCInst &Inst, unsigned N) const {
540  llvm_unreachable("addRegOperands");
541  }
542 
543  void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
544  assert(N == 1 && "Invalid number of operands!");
546  }
547 
548  void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
549  assert(N == 1 && "Invalid number of operands!");
551  }
552 
553  void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
554  assert(N == 1 && "Invalid number of operands!");
556  }
557 
558  void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
559  assert(N == 1 && "Invalid number of operands!");
561  }
562 
563  void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
564  if (isPPC64())
565  addRegG8RCOperands(Inst, N);
566  else
567  addRegGPRCOperands(Inst, N);
568  }
569 
570  void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
571  if (isPPC64())
572  addRegG8RCNoX0Operands(Inst, N);
573  else
574  addRegGPRCNoR0Operands(Inst, N);
575  }
576 
577  void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
578  assert(N == 1 && "Invalid number of operands!");
580  }
581 
582  void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
583  assert(N == 1 && "Invalid number of operands!");
585  }
586 
587  void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
588  assert(N == 1 && "Invalid number of operands!");
590  }
591 
592  void addRegVSRCOperands(MCInst &Inst, unsigned N) const {
593  assert(N == 1 && "Invalid number of operands!");
594  Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()]));
595  }
596 
597  void addRegVSFRCOperands(MCInst &Inst, unsigned N) const {
598  assert(N == 1 && "Invalid number of operands!");
599  Inst.addOperand(MCOperand::createReg(VSFRegs[getVSReg()]));
600  }
601 
602  void addRegVSSRCOperands(MCInst &Inst, unsigned N) const {
603  assert(N == 1 && "Invalid number of operands!");
604  Inst.addOperand(MCOperand::createReg(VSSRegs[getVSReg()]));
605  }
606 
607  void addRegQFRCOperands(MCInst &Inst, unsigned N) const {
608  assert(N == 1 && "Invalid number of operands!");
610  }
611 
612  void addRegQSRCOperands(MCInst &Inst, unsigned N) const {
613  assert(N == 1 && "Invalid number of operands!");
615  }
616 
617  void addRegQBRCOperands(MCInst &Inst, unsigned N) const {
618  assert(N == 1 && "Invalid number of operands!");
620  }
621 
622  void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
623  assert(N == 1 && "Invalid number of operands!");
624  Inst.addOperand(MCOperand::createReg(CRBITRegs[getCRBit()]));
625  }
626 
627  void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
628  assert(N == 1 && "Invalid number of operands!");
629  Inst.addOperand(MCOperand::createReg(CRRegs[getCCReg()]));
630  }
631 
632  void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
633  assert(N == 1 && "Invalid number of operands!");
634  Inst.addOperand(MCOperand::createReg(CRRegs[getCRBitMask()]));
635  }
636 
637  void addImmOperands(MCInst &Inst, unsigned N) const {
638  assert(N == 1 && "Invalid number of operands!");
639  if (Kind == Immediate)
640  Inst.addOperand(MCOperand::createImm(getImm()));
641  else
642  Inst.addOperand(MCOperand::createExpr(getExpr()));
643  }
644 
645  void addS16ImmOperands(MCInst &Inst, unsigned N) const {
646  assert(N == 1 && "Invalid number of operands!");
647  switch (Kind) {
648  case Immediate:
649  Inst.addOperand(MCOperand::createImm(getImm()));
650  break;
651  case ContextImmediate:
652  Inst.addOperand(MCOperand::createImm(getImmS16Context()));
653  break;
654  default:
655  Inst.addOperand(MCOperand::createExpr(getExpr()));
656  break;
657  }
658  }
659 
660  void addU16ImmOperands(MCInst &Inst, unsigned N) const {
661  assert(N == 1 && "Invalid number of operands!");
662  switch (Kind) {
663  case Immediate:
664  Inst.addOperand(MCOperand::createImm(getImm()));
665  break;
666  case ContextImmediate:
667  Inst.addOperand(MCOperand::createImm(getImmU16Context()));
668  break;
669  default:
670  Inst.addOperand(MCOperand::createExpr(getExpr()));
671  break;
672  }
673  }
674 
675  void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
676  assert(N == 1 && "Invalid number of operands!");
677  if (Kind == Immediate)
678  Inst.addOperand(MCOperand::createImm(getImm() / 4));
679  else
680  Inst.addOperand(MCOperand::createExpr(getExpr()));
681  }
682 
683  void addTLSRegOperands(MCInst &Inst, unsigned N) const {
684  assert(N == 1 && "Invalid number of operands!");
685  Inst.addOperand(MCOperand::createExpr(getTLSReg()));
686  }
687 
688  StringRef getToken() const {
689  assert(Kind == Token && "Invalid access!");
690  return StringRef(Tok.Data, Tok.Length);
691  }
692 
693  void print(raw_ostream &OS) const override;
694 
695  static std::unique_ptr<PPCOperand> CreateToken(StringRef Str, SMLoc S,
696  bool IsPPC64) {
697  auto Op = make_unique<PPCOperand>(Token);
698  Op->Tok.Data = Str.data();
699  Op->Tok.Length = Str.size();
700  Op->StartLoc = S;
701  Op->EndLoc = S;
702  Op->IsPPC64 = IsPPC64;
703  return Op;
704  }
705 
706  static std::unique_ptr<PPCOperand>
707  CreateTokenWithStringCopy(StringRef Str, SMLoc S, bool IsPPC64) {
708  // Allocate extra memory for the string and copy it.
709  // FIXME: This is incorrect, Operands are owned by unique_ptr with a default
710  // deleter which will destroy them by simply using "delete", not correctly
711  // calling operator delete on this extra memory after calling the dtor
712  // explicitly.
713  void *Mem = ::operator new(sizeof(PPCOperand) + Str.size());
714  std::unique_ptr<PPCOperand> Op(new (Mem) PPCOperand(Token));
715  Op->Tok.Data = reinterpret_cast<const char *>(Op.get() + 1);
716  Op->Tok.Length = Str.size();
717  std::memcpy(const_cast<char *>(Op->Tok.Data), Str.data(), Str.size());
718  Op->StartLoc = S;
719  Op->EndLoc = S;
720  Op->IsPPC64 = IsPPC64;
721  return Op;
722  }
723 
724  static std::unique_ptr<PPCOperand> CreateImm(int64_t Val, SMLoc S, SMLoc E,
725  bool IsPPC64) {
726  auto Op = make_unique<PPCOperand>(Immediate);
727  Op->Imm.Val = Val;
728  Op->StartLoc = S;
729  Op->EndLoc = E;
730  Op->IsPPC64 = IsPPC64;
731  return Op;
732  }
733 
734  static std::unique_ptr<PPCOperand> CreateExpr(const MCExpr *Val, SMLoc S,
735  SMLoc E, bool IsPPC64) {
736  auto Op = make_unique<PPCOperand>(Expression);
737  Op->Expr.Val = Val;
738  Op->Expr.CRVal = EvaluateCRExpr(Val);
739  Op->StartLoc = S;
740  Op->EndLoc = E;
741  Op->IsPPC64 = IsPPC64;
742  return Op;
743  }
744 
745  static std::unique_ptr<PPCOperand>
746  CreateTLSReg(const MCSymbolRefExpr *Sym, SMLoc S, SMLoc E, bool IsPPC64) {
747  auto Op = make_unique<PPCOperand>(TLSRegister);
748  Op->TLSReg.Sym = Sym;
749  Op->StartLoc = S;
750  Op->EndLoc = E;
751  Op->IsPPC64 = IsPPC64;
752  return Op;
753  }
754 
755  static std::unique_ptr<PPCOperand>
756  CreateContextImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
757  auto Op = make_unique<PPCOperand>(ContextImmediate);
758  Op->Imm.Val = Val;
759  Op->StartLoc = S;
760  Op->EndLoc = E;
761  Op->IsPPC64 = IsPPC64;
762  return Op;
763  }
764 
765  static std::unique_ptr<PPCOperand>
766  CreateFromMCExpr(const MCExpr *Val, SMLoc S, SMLoc E, bool IsPPC64) {
767  if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
768  return CreateImm(CE->getValue(), S, E, IsPPC64);
769 
770  if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
771  if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS)
772  return CreateTLSReg(SRE, S, E, IsPPC64);
773 
774  if (const PPCMCExpr *TE = dyn_cast<PPCMCExpr>(Val)) {
775  int64_t Res;
776  if (TE->evaluateAsConstant(Res))
777  return CreateContextImm(Res, S, E, IsPPC64);
778  }
779 
780  return CreateExpr(Val, S, E, IsPPC64);
781  }
782 };
783 
784 } // end anonymous namespace.
785 
786 void PPCOperand::print(raw_ostream &OS) const {
787  switch (Kind) {
788  case Token:
789  OS << "'" << getToken() << "'";
790  break;
791  case Immediate:
792  case ContextImmediate:
793  OS << getImm();
794  break;
795  case Expression:
796  OS << *getExpr();
797  break;
798  case TLSRegister:
799  OS << *getTLSReg();
800  break;
801  }
802 }
803 
804 static void
806  if (Op.isImm()) {
808  return;
809  }
810  const MCExpr *Expr = Op.getExpr();
811  if (const MCUnaryExpr *UnExpr = dyn_cast<MCUnaryExpr>(Expr)) {
812  if (UnExpr->getOpcode() == MCUnaryExpr::Minus) {
813  Inst.addOperand(MCOperand::createExpr(UnExpr->getSubExpr()));
814  return;
815  }
816  } else if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Expr)) {
817  if (BinExpr->getOpcode() == MCBinaryExpr::Sub) {
818  const MCExpr *NE = MCBinaryExpr::createSub(BinExpr->getRHS(),
819  BinExpr->getLHS(), Ctx);
821  return;
822  }
823  }
825 }
826 
827 void PPCAsmParser::ProcessInstruction(MCInst &Inst,
828  const OperandVector &Operands) {
829  int Opcode = Inst.getOpcode();
830  switch (Opcode) {
831  case PPC::DCBTx:
832  case PPC::DCBTT:
833  case PPC::DCBTSTx:
834  case PPC::DCBTSTT: {
835  MCInst TmpInst;
836  TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ?
837  PPC::DCBT : PPC::DCBTST);
839  (Opcode == PPC::DCBTx || Opcode == PPC::DCBTSTx) ? 0 : 16));
840  TmpInst.addOperand(Inst.getOperand(0));
841  TmpInst.addOperand(Inst.getOperand(1));
842  Inst = TmpInst;
843  break;
844  }
845  case PPC::DCBTCT:
846  case PPC::DCBTDS: {
847  MCInst TmpInst;
848  TmpInst.setOpcode(PPC::DCBT);
849  TmpInst.addOperand(Inst.getOperand(2));
850  TmpInst.addOperand(Inst.getOperand(0));
851  TmpInst.addOperand(Inst.getOperand(1));
852  Inst = TmpInst;
853  break;
854  }
855  case PPC::DCBTSTCT:
856  case PPC::DCBTSTDS: {
857  MCInst TmpInst;
858  TmpInst.setOpcode(PPC::DCBTST);
859  TmpInst.addOperand(Inst.getOperand(2));
860  TmpInst.addOperand(Inst.getOperand(0));
861  TmpInst.addOperand(Inst.getOperand(1));
862  Inst = TmpInst;
863  break;
864  }
865  case PPC::LAx: {
866  MCInst TmpInst;
867  TmpInst.setOpcode(PPC::LA);
868  TmpInst.addOperand(Inst.getOperand(0));
869  TmpInst.addOperand(Inst.getOperand(2));
870  TmpInst.addOperand(Inst.getOperand(1));
871  Inst = TmpInst;
872  break;
873  }
874  case PPC::SUBI: {
875  MCInst TmpInst;
876  TmpInst.setOpcode(PPC::ADDI);
877  TmpInst.addOperand(Inst.getOperand(0));
878  TmpInst.addOperand(Inst.getOperand(1));
879  addNegOperand(TmpInst, Inst.getOperand(2), getContext());
880  Inst = TmpInst;
881  break;
882  }
883  case PPC::SUBIS: {
884  MCInst TmpInst;
885  TmpInst.setOpcode(PPC::ADDIS);
886  TmpInst.addOperand(Inst.getOperand(0));
887  TmpInst.addOperand(Inst.getOperand(1));
888  addNegOperand(TmpInst, Inst.getOperand(2), getContext());
889  Inst = TmpInst;
890  break;
891  }
892  case PPC::SUBIC: {
893  MCInst TmpInst;
894  TmpInst.setOpcode(PPC::ADDIC);
895  TmpInst.addOperand(Inst.getOperand(0));
896  TmpInst.addOperand(Inst.getOperand(1));
897  addNegOperand(TmpInst, Inst.getOperand(2), getContext());
898  Inst = TmpInst;
899  break;
900  }
901  case PPC::SUBICo: {
902  MCInst TmpInst;
903  TmpInst.setOpcode(PPC::ADDICo);
904  TmpInst.addOperand(Inst.getOperand(0));
905  TmpInst.addOperand(Inst.getOperand(1));
906  addNegOperand(TmpInst, Inst.getOperand(2), getContext());
907  Inst = TmpInst;
908  break;
909  }
910  case PPC::EXTLWI:
911  case PPC::EXTLWIo: {
912  MCInst TmpInst;
913  int64_t N = Inst.getOperand(2).getImm();
914  int64_t B = Inst.getOperand(3).getImm();
915  TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
916  TmpInst.addOperand(Inst.getOperand(0));
917  TmpInst.addOperand(Inst.getOperand(1));
918  TmpInst.addOperand(MCOperand::createImm(B));
919  TmpInst.addOperand(MCOperand::createImm(0));
920  TmpInst.addOperand(MCOperand::createImm(N - 1));
921  Inst = TmpInst;
922  break;
923  }
924  case PPC::EXTRWI:
925  case PPC::EXTRWIo: {
926  MCInst TmpInst;
927  int64_t N = Inst.getOperand(2).getImm();
928  int64_t B = Inst.getOperand(3).getImm();
929  TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
930  TmpInst.addOperand(Inst.getOperand(0));
931  TmpInst.addOperand(Inst.getOperand(1));
932  TmpInst.addOperand(MCOperand::createImm(B + N));
933  TmpInst.addOperand(MCOperand::createImm(32 - N));
934  TmpInst.addOperand(MCOperand::createImm(31));
935  Inst = TmpInst;
936  break;
937  }
938  case PPC::INSLWI:
939  case PPC::INSLWIo: {
940  MCInst TmpInst;
941  int64_t N = Inst.getOperand(2).getImm();
942  int64_t B = Inst.getOperand(3).getImm();
943  TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
944  TmpInst.addOperand(Inst.getOperand(0));
945  TmpInst.addOperand(Inst.getOperand(0));
946  TmpInst.addOperand(Inst.getOperand(1));
947  TmpInst.addOperand(MCOperand::createImm(32 - B));
948  TmpInst.addOperand(MCOperand::createImm(B));
949  TmpInst.addOperand(MCOperand::createImm((B + N) - 1));
950  Inst = TmpInst;
951  break;
952  }
953  case PPC::INSRWI:
954  case PPC::INSRWIo: {
955  MCInst TmpInst;
956  int64_t N = Inst.getOperand(2).getImm();
957  int64_t B = Inst.getOperand(3).getImm();
958  TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
959  TmpInst.addOperand(Inst.getOperand(0));
960  TmpInst.addOperand(Inst.getOperand(0));
961  TmpInst.addOperand(Inst.getOperand(1));
962  TmpInst.addOperand(MCOperand::createImm(32 - (B + N)));
963  TmpInst.addOperand(MCOperand::createImm(B));
964  TmpInst.addOperand(MCOperand::createImm((B + N) - 1));
965  Inst = TmpInst;
966  break;
967  }
968  case PPC::ROTRWI:
969  case PPC::ROTRWIo: {
970  MCInst TmpInst;
971  int64_t N = Inst.getOperand(2).getImm();
972  TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
973  TmpInst.addOperand(Inst.getOperand(0));
974  TmpInst.addOperand(Inst.getOperand(1));
975  TmpInst.addOperand(MCOperand::createImm(32 - N));
976  TmpInst.addOperand(MCOperand::createImm(0));
977  TmpInst.addOperand(MCOperand::createImm(31));
978  Inst = TmpInst;
979  break;
980  }
981  case PPC::SLWI:
982  case PPC::SLWIo: {
983  MCInst TmpInst;
984  int64_t N = Inst.getOperand(2).getImm();
985  TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
986  TmpInst.addOperand(Inst.getOperand(0));
987  TmpInst.addOperand(Inst.getOperand(1));
988  TmpInst.addOperand(MCOperand::createImm(N));
989  TmpInst.addOperand(MCOperand::createImm(0));
990  TmpInst.addOperand(MCOperand::createImm(31 - N));
991  Inst = TmpInst;
992  break;
993  }
994  case PPC::SRWI:
995  case PPC::SRWIo: {
996  MCInst TmpInst;
997  int64_t N = Inst.getOperand(2).getImm();
998  TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
999  TmpInst.addOperand(Inst.getOperand(0));
1000  TmpInst.addOperand(Inst.getOperand(1));
1001  TmpInst.addOperand(MCOperand::createImm(32 - N));
1002  TmpInst.addOperand(MCOperand::createImm(N));
1003  TmpInst.addOperand(MCOperand::createImm(31));
1004  Inst = TmpInst;
1005  break;
1006  }
1007  case PPC::CLRRWI:
1008  case PPC::CLRRWIo: {
1009  MCInst TmpInst;
1010  int64_t N = Inst.getOperand(2).getImm();
1011  TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
1012  TmpInst.addOperand(Inst.getOperand(0));
1013  TmpInst.addOperand(Inst.getOperand(1));
1014  TmpInst.addOperand(MCOperand::createImm(0));
1015  TmpInst.addOperand(MCOperand::createImm(0));
1016  TmpInst.addOperand(MCOperand::createImm(31 - N));
1017  Inst = TmpInst;
1018  break;
1019  }
1020  case PPC::CLRLSLWI:
1021  case PPC::CLRLSLWIo: {
1022  MCInst TmpInst;
1023  int64_t B = Inst.getOperand(2).getImm();
1024  int64_t N = Inst.getOperand(3).getImm();
1025  TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
1026  TmpInst.addOperand(Inst.getOperand(0));
1027  TmpInst.addOperand(Inst.getOperand(1));
1028  TmpInst.addOperand(MCOperand::createImm(N));
1029  TmpInst.addOperand(MCOperand::createImm(B - N));
1030  TmpInst.addOperand(MCOperand::createImm(31 - N));
1031  Inst = TmpInst;
1032  break;
1033  }
1034  case PPC::EXTLDI:
1035  case PPC::EXTLDIo: {
1036  MCInst TmpInst;
1037  int64_t N = Inst.getOperand(2).getImm();
1038  int64_t B = Inst.getOperand(3).getImm();
1039  TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
1040  TmpInst.addOperand(Inst.getOperand(0));
1041  TmpInst.addOperand(Inst.getOperand(1));
1042  TmpInst.addOperand(MCOperand::createImm(B));
1043  TmpInst.addOperand(MCOperand::createImm(N - 1));
1044  Inst = TmpInst;
1045  break;
1046  }
1047  case PPC::EXTRDI:
1048  case PPC::EXTRDIo: {
1049  MCInst TmpInst;
1050  int64_t N = Inst.getOperand(2).getImm();
1051  int64_t B = Inst.getOperand(3).getImm();
1052  TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
1053  TmpInst.addOperand(Inst.getOperand(0));
1054  TmpInst.addOperand(Inst.getOperand(1));
1055  TmpInst.addOperand(MCOperand::createImm(B + N));
1056  TmpInst.addOperand(MCOperand::createImm(64 - N));
1057  Inst = TmpInst;
1058  break;
1059  }
1060  case PPC::INSRDI:
1061  case PPC::INSRDIo: {
1062  MCInst TmpInst;
1063  int64_t N = Inst.getOperand(2).getImm();
1064  int64_t B = Inst.getOperand(3).getImm();
1065  TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
1066  TmpInst.addOperand(Inst.getOperand(0));
1067  TmpInst.addOperand(Inst.getOperand(0));
1068  TmpInst.addOperand(Inst.getOperand(1));
1069  TmpInst.addOperand(MCOperand::createImm(64 - (B + N)));
1070  TmpInst.addOperand(MCOperand::createImm(B));
1071  Inst = TmpInst;
1072  break;
1073  }
1074  case PPC::ROTRDI:
1075  case PPC::ROTRDIo: {
1076  MCInst TmpInst;
1077  int64_t N = Inst.getOperand(2).getImm();
1078  TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
1079  TmpInst.addOperand(Inst.getOperand(0));
1080  TmpInst.addOperand(Inst.getOperand(1));
1081  TmpInst.addOperand(MCOperand::createImm(64 - N));
1082  TmpInst.addOperand(MCOperand::createImm(0));
1083  Inst = TmpInst;
1084  break;
1085  }
1086  case PPC::SLDI:
1087  case PPC::SLDIo: {
1088  MCInst TmpInst;
1089  int64_t N = Inst.getOperand(2).getImm();
1090  TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
1091  TmpInst.addOperand(Inst.getOperand(0));
1092  TmpInst.addOperand(Inst.getOperand(1));
1093  TmpInst.addOperand(MCOperand::createImm(N));
1094  TmpInst.addOperand(MCOperand::createImm(63 - N));
1095  Inst = TmpInst;
1096  break;
1097  }
1098  case PPC::SRDI:
1099  case PPC::SRDIo: {
1100  MCInst TmpInst;
1101  int64_t N = Inst.getOperand(2).getImm();
1102  TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
1103  TmpInst.addOperand(Inst.getOperand(0));
1104  TmpInst.addOperand(Inst.getOperand(1));
1105  TmpInst.addOperand(MCOperand::createImm(64 - N));
1106  TmpInst.addOperand(MCOperand::createImm(N));
1107  Inst = TmpInst;
1108  break;
1109  }
1110  case PPC::CLRRDI:
1111  case PPC::CLRRDIo: {
1112  MCInst TmpInst;
1113  int64_t N = Inst.getOperand(2).getImm();
1114  TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
1115  TmpInst.addOperand(Inst.getOperand(0));
1116  TmpInst.addOperand(Inst.getOperand(1));
1117  TmpInst.addOperand(MCOperand::createImm(0));
1118  TmpInst.addOperand(MCOperand::createImm(63 - N));
1119  Inst = TmpInst;
1120  break;
1121  }
1122  case PPC::CLRLSLDI:
1123  case PPC::CLRLSLDIo: {
1124  MCInst TmpInst;
1125  int64_t B = Inst.getOperand(2).getImm();
1126  int64_t N = Inst.getOperand(3).getImm();
1127  TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
1128  TmpInst.addOperand(Inst.getOperand(0));
1129  TmpInst.addOperand(Inst.getOperand(1));
1130  TmpInst.addOperand(MCOperand::createImm(N));
1131  TmpInst.addOperand(MCOperand::createImm(B - N));
1132  Inst = TmpInst;
1133  break;
1134  }
1135  case PPC::RLWINMbm:
1136  case PPC::RLWINMobm: {
1137  unsigned MB, ME;
1138  int64_t BM = Inst.getOperand(3).getImm();
1139  if (!isRunOfOnes(BM, MB, ME))
1140  break;
1141 
1142  MCInst TmpInst;
1143  TmpInst.setOpcode(Opcode == PPC::RLWINMbm ? PPC::RLWINM : PPC::RLWINMo);
1144  TmpInst.addOperand(Inst.getOperand(0));
1145  TmpInst.addOperand(Inst.getOperand(1));
1146  TmpInst.addOperand(Inst.getOperand(2));
1147  TmpInst.addOperand(MCOperand::createImm(MB));
1148  TmpInst.addOperand(MCOperand::createImm(ME));
1149  Inst = TmpInst;
1150  break;
1151  }
1152  case PPC::RLWIMIbm:
1153  case PPC::RLWIMIobm: {
1154  unsigned MB, ME;
1155  int64_t BM = Inst.getOperand(3).getImm();
1156  if (!isRunOfOnes(BM, MB, ME))
1157  break;
1158 
1159  MCInst TmpInst;
1160  TmpInst.setOpcode(Opcode == PPC::RLWIMIbm ? PPC::RLWIMI : PPC::RLWIMIo);
1161  TmpInst.addOperand(Inst.getOperand(0));
1162  TmpInst.addOperand(Inst.getOperand(0)); // The tied operand.
1163  TmpInst.addOperand(Inst.getOperand(1));
1164  TmpInst.addOperand(Inst.getOperand(2));
1165  TmpInst.addOperand(MCOperand::createImm(MB));
1166  TmpInst.addOperand(MCOperand::createImm(ME));
1167  Inst = TmpInst;
1168  break;
1169  }
1170  case PPC::RLWNMbm:
1171  case PPC::RLWNMobm: {
1172  unsigned MB, ME;
1173  int64_t BM = Inst.getOperand(3).getImm();
1174  if (!isRunOfOnes(BM, MB, ME))
1175  break;
1176 
1177  MCInst TmpInst;
1178  TmpInst.setOpcode(Opcode == PPC::RLWNMbm ? PPC::RLWNM : PPC::RLWNMo);
1179  TmpInst.addOperand(Inst.getOperand(0));
1180  TmpInst.addOperand(Inst.getOperand(1));
1181  TmpInst.addOperand(Inst.getOperand(2));
1182  TmpInst.addOperand(MCOperand::createImm(MB));
1183  TmpInst.addOperand(MCOperand::createImm(ME));
1184  Inst = TmpInst;
1185  break;
1186  }
1187  case PPC::MFTB: {
1188  if (STI.getFeatureBits()[PPC::FeatureMFTB]) {
1189  assert(Inst.getNumOperands() == 2 && "Expecting two operands");
1190  Inst.setOpcode(PPC::MFSPR);
1191  }
1192  break;
1193  }
1194  }
1195 }
1196 
1197 bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1198  OperandVector &Operands,
1199  MCStreamer &Out, uint64_t &ErrorInfo,
1200  bool MatchingInlineAsm) {
1201  MCInst Inst;
1202 
1203  switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
1204  case Match_Success:
1205  // Post-process instructions (typically extended mnemonics)
1206  ProcessInstruction(Inst, Operands);
1207  Inst.setLoc(IDLoc);
1208  Out.EmitInstruction(Inst, STI);
1209  return false;
1210  case Match_MissingFeature:
1211  return Error(IDLoc, "instruction use requires an option to be enabled");
1212  case Match_MnemonicFail:
1213  return Error(IDLoc, "unrecognized instruction mnemonic");
1214  case Match_InvalidOperand: {
1215  SMLoc ErrorLoc = IDLoc;
1216  if (ErrorInfo != ~0ULL) {
1217  if (ErrorInfo >= Operands.size())
1218  return Error(IDLoc, "too few operands for instruction");
1219 
1220  ErrorLoc = ((PPCOperand &)*Operands[ErrorInfo]).getStartLoc();
1221  if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
1222  }
1223 
1224  return Error(ErrorLoc, "invalid operand for instruction");
1225  }
1226  }
1227 
1228  llvm_unreachable("Implement any new match types added!");
1229 }
1230 
1231 bool PPCAsmParser::
1232 MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) {
1233  if (Tok.is(AsmToken::Identifier)) {
1234  StringRef Name = Tok.getString();
1235 
1236  if (Name.equals_lower("lr")) {
1237  RegNo = isPPC64()? PPC::LR8 : PPC::LR;
1238  IntVal = 8;
1239  return false;
1240  } else if (Name.equals_lower("ctr")) {
1241  RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
1242  IntVal = 9;
1243  return false;
1244  } else if (Name.equals_lower("vrsave")) {
1245  RegNo = PPC::VRSAVE;
1246  IntVal = 256;
1247  return false;
1248  } else if (Name.startswith_lower("r") &&
1249  !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1250  RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
1251  return false;
1252  } else if (Name.startswith_lower("f") &&
1253  !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1254  RegNo = FRegs[IntVal];
1255  return false;
1256  } else if (Name.startswith_lower("vs") &&
1257  !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 64) {
1258  RegNo = VSRegs[IntVal];
1259  return false;
1260  } else if (Name.startswith_lower("v") &&
1261  !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1262  RegNo = VRegs[IntVal];
1263  return false;
1264  } else if (Name.startswith_lower("q") &&
1265  !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1266  RegNo = QFRegs[IntVal];
1267  return false;
1268  } else if (Name.startswith_lower("cr") &&
1269  !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
1270  RegNo = CRRegs[IntVal];
1271  return false;
1272  }
1273  }
1274 
1275  return true;
1276 }
1277 
1278 bool PPCAsmParser::
1279 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
1280  MCAsmParser &Parser = getParser();
1281  const AsmToken &Tok = Parser.getTok();
1282  StartLoc = Tok.getLoc();
1283  EndLoc = Tok.getEndLoc();
1284  RegNo = 0;
1285  int64_t IntVal;
1286 
1287  if (!MatchRegisterName(Tok, RegNo, IntVal)) {
1288  Parser.Lex(); // Eat identifier token.
1289  return false;
1290  }
1291 
1292  return Error(StartLoc, "invalid register name");
1293 }
1294 
1295 /// Extract \code @l/@ha \endcode modifier from expression. Recursively scan
1296 /// the expression and check for VK_PPC_LO/HI/HA
1297 /// symbol variants. If all symbols with modifier use the same
1298 /// variant, return the corresponding PPCMCExpr::VariantKind,
1299 /// and a modified expression using the default symbol variant.
1300 /// Otherwise, return NULL.
1301 const MCExpr *PPCAsmParser::
1302 ExtractModifierFromExpr(const MCExpr *E,
1304  MCContext &Context = getParser().getContext();
1305  Variant = PPCMCExpr::VK_PPC_None;
1306 
1307  switch (E->getKind()) {
1308  case MCExpr::Target:
1309  case MCExpr::Constant:
1310  return nullptr;
1311 
1312  case MCExpr::SymbolRef: {
1313  const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1314 
1315  switch (SRE->getKind()) {
1317  Variant = PPCMCExpr::VK_PPC_LO;
1318  break;
1320  Variant = PPCMCExpr::VK_PPC_HI;
1321  break;
1323  Variant = PPCMCExpr::VK_PPC_HA;
1324  break;
1326  Variant = PPCMCExpr::VK_PPC_HIGHER;
1327  break;
1329  Variant = PPCMCExpr::VK_PPC_HIGHERA;
1330  break;
1332  Variant = PPCMCExpr::VK_PPC_HIGHEST;
1333  break;
1335  Variant = PPCMCExpr::VK_PPC_HIGHESTA;
1336  break;
1337  default:
1338  return nullptr;
1339  }
1340 
1341  return MCSymbolRefExpr::create(&SRE->getSymbol(), Context);
1342  }
1343 
1344  case MCExpr::Unary: {
1345  const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1346  const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
1347  if (!Sub)
1348  return nullptr;
1349  return MCUnaryExpr::create(UE->getOpcode(), Sub, Context);
1350  }
1351 
1352  case MCExpr::Binary: {
1353  const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1354  PPCMCExpr::VariantKind LHSVariant, RHSVariant;
1355  const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
1356  const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
1357 
1358  if (!LHS && !RHS)
1359  return nullptr;
1360 
1361  if (!LHS) LHS = BE->getLHS();
1362  if (!RHS) RHS = BE->getRHS();
1363 
1364  if (LHSVariant == PPCMCExpr::VK_PPC_None)
1365  Variant = RHSVariant;
1366  else if (RHSVariant == PPCMCExpr::VK_PPC_None)
1367  Variant = LHSVariant;
1368  else if (LHSVariant == RHSVariant)
1369  Variant = LHSVariant;
1370  else
1371  return nullptr;
1372 
1373  return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context);
1374  }
1375  }
1376 
1377  llvm_unreachable("Invalid expression kind!");
1378 }
1379 
1380 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace
1381 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD. This is necessary to avoid having
1382 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT.
1383 /// FIXME: This is a hack.
1384 const MCExpr *PPCAsmParser::
1385 FixupVariantKind(const MCExpr *E) {
1386  MCContext &Context = getParser().getContext();
1387 
1388  switch (E->getKind()) {
1389  case MCExpr::Target:
1390  case MCExpr::Constant:
1391  return E;
1392 
1393  case MCExpr::SymbolRef: {
1394  const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1396 
1397  switch (SRE->getKind()) {
1400  break;
1403  break;
1404  default:
1405  return E;
1406  }
1407  return MCSymbolRefExpr::create(&SRE->getSymbol(), Variant, Context);
1408  }
1409 
1410  case MCExpr::Unary: {
1411  const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1412  const MCExpr *Sub = FixupVariantKind(UE->getSubExpr());
1413  if (Sub == UE->getSubExpr())
1414  return E;
1415  return MCUnaryExpr::create(UE->getOpcode(), Sub, Context);
1416  }
1417 
1418  case MCExpr::Binary: {
1419  const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1420  const MCExpr *LHS = FixupVariantKind(BE->getLHS());
1421  const MCExpr *RHS = FixupVariantKind(BE->getRHS());
1422  if (LHS == BE->getLHS() && RHS == BE->getRHS())
1423  return E;
1424  return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context);
1425  }
1426  }
1427 
1428  llvm_unreachable("Invalid expression kind!");
1429 }
1430 
1431 /// ParseExpression. This differs from the default "parseExpression" in that
1432 /// it handles modifiers.
1433 bool PPCAsmParser::
1434 ParseExpression(const MCExpr *&EVal) {
1435 
1436  if (isDarwin())
1437  return ParseDarwinExpression(EVal);
1438 
1439  // (ELF Platforms)
1440  // Handle \code @l/@ha \endcode
1441  if (getParser().parseExpression(EVal))
1442  return true;
1443 
1444  EVal = FixupVariantKind(EVal);
1445 
1446  PPCMCExpr::VariantKind Variant;
1447  const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1448  if (E)
1449  EVal = PPCMCExpr::create(Variant, E, false, getParser().getContext());
1450 
1451  return false;
1452 }
1453 
1454 /// ParseDarwinExpression. (MachO Platforms)
1455 /// This differs from the default "parseExpression" in that it handles detection
1456 /// of the \code hi16(), ha16() and lo16() \endcode modifiers. At present,
1457 /// parseExpression() doesn't recognise the modifiers when in the Darwin/MachO
1458 /// syntax form so it is done here. TODO: Determine if there is merit in arranging
1459 /// for this to be done at a higher level.
1460 bool PPCAsmParser::
1461 ParseDarwinExpression(const MCExpr *&EVal) {
1462  MCAsmParser &Parser = getParser();
1464  switch (getLexer().getKind()) {
1465  default:
1466  break;
1467  case AsmToken::Identifier:
1468  // Compiler-generated Darwin identifiers begin with L,l,_ or "; thus
1469  // something starting with any other char should be part of the
1470  // asm syntax. If handwritten asm includes an identifier like lo16,
1471  // then all bets are off - but no-one would do that, right?
1472  StringRef poss = Parser.getTok().getString();
1473  if (poss.equals_lower("lo16")) {
1474  Variant = PPCMCExpr::VK_PPC_LO;
1475  } else if (poss.equals_lower("hi16")) {
1476  Variant = PPCMCExpr::VK_PPC_HI;
1477  } else if (poss.equals_lower("ha16")) {
1478  Variant = PPCMCExpr::VK_PPC_HA;
1479  }
1480  if (Variant != PPCMCExpr::VK_PPC_None) {
1481  Parser.Lex(); // Eat the xx16
1482  if (getLexer().isNot(AsmToken::LParen))
1483  return Error(Parser.getTok().getLoc(), "expected '('");
1484  Parser.Lex(); // Eat the '('
1485  }
1486  break;
1487  }
1488 
1489  if (getParser().parseExpression(EVal))
1490  return true;
1491 
1492  if (Variant != PPCMCExpr::VK_PPC_None) {
1493  if (getLexer().isNot(AsmToken::RParen))
1494  return Error(Parser.getTok().getLoc(), "expected ')'");
1495  Parser.Lex(); // Eat the ')'
1496  EVal = PPCMCExpr::create(Variant, EVal, false, getParser().getContext());
1497  }
1498  return false;
1499 }
1500 
1501 /// ParseOperand
1502 /// This handles registers in the form 'NN', '%rNN' for ELF platforms and
1503 /// rNN for MachO.
1504 bool PPCAsmParser::ParseOperand(OperandVector &Operands) {
1505  MCAsmParser &Parser = getParser();
1506  SMLoc S = Parser.getTok().getLoc();
1507  SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1508  const MCExpr *EVal;
1509 
1510  // Attempt to parse the next token as an immediate
1511  switch (getLexer().getKind()) {
1512  // Special handling for register names. These are interpreted
1513  // as immediates corresponding to the register number.
1514  case AsmToken::Percent:
1515  Parser.Lex(); // Eat the '%'.
1516  unsigned RegNo;
1517  int64_t IntVal;
1518  if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1519  Parser.Lex(); // Eat the identifier token.
1520  Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1521  return false;
1522  }
1523  return Error(S, "invalid register name");
1524 
1525  case AsmToken::Identifier:
1526  // Note that non-register-name identifiers from the compiler will begin
1527  // with '_', 'L'/'l' or '"'. Of course, handwritten asm could include
1528  // identifiers like r31foo - so we fall through in the event that parsing
1529  // a register name fails.
1530  if (isDarwin()) {
1531  unsigned RegNo;
1532  int64_t IntVal;
1533  if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1534  Parser.Lex(); // Eat the identifier token.
1535  Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1536  return false;
1537  }
1538  }
1539  // Fall-through to process non-register-name identifiers as expression.
1540  // All other expressions
1541  case AsmToken::LParen:
1542  case AsmToken::Plus:
1543  case AsmToken::Minus:
1544  case AsmToken::Integer:
1545  case AsmToken::Dot:
1546  case AsmToken::Dollar:
1547  case AsmToken::Exclaim:
1548  case AsmToken::Tilde:
1549  if (!ParseExpression(EVal))
1550  break;
1551  /* fall through */
1552  default:
1553  return Error(S, "unknown operand");
1554  }
1555 
1556  // Push the parsed operand into the list of operands
1557  Operands.push_back(PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64()));
1558 
1559  // Check whether this is a TLS call expression
1560  bool TLSCall = false;
1561  if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
1562  TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
1563 
1564  if (TLSCall && getLexer().is(AsmToken::LParen)) {
1565  const MCExpr *TLSSym;
1566 
1567  Parser.Lex(); // Eat the '('.
1568  S = Parser.getTok().getLoc();
1569  if (ParseExpression(TLSSym))
1570  return Error(S, "invalid TLS call expression");
1571  if (getLexer().isNot(AsmToken::RParen))
1572  return Error(Parser.getTok().getLoc(), "missing ')'");
1573  E = Parser.getTok().getLoc();
1574  Parser.Lex(); // Eat the ')'.
1575 
1576  Operands.push_back(PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64()));
1577  }
1578 
1579  // Otherwise, check for D-form memory operands
1580  if (!TLSCall && getLexer().is(AsmToken::LParen)) {
1581  Parser.Lex(); // Eat the '('.
1582  S = Parser.getTok().getLoc();
1583 
1584  int64_t IntVal;
1585  switch (getLexer().getKind()) {
1586  case AsmToken::Percent:
1587  Parser.Lex(); // Eat the '%'.
1588  unsigned RegNo;
1589  if (MatchRegisterName(Parser.getTok(), RegNo, IntVal))
1590  return Error(S, "invalid register name");
1591  Parser.Lex(); // Eat the identifier token.
1592  break;
1593 
1594  case AsmToken::Integer:
1595  if (!isDarwin()) {
1596  if (getParser().parseAbsoluteExpression(IntVal) ||
1597  IntVal < 0 || IntVal > 31)
1598  return Error(S, "invalid register number");
1599  } else {
1600  return Error(S, "unexpected integer value");
1601  }
1602  break;
1603 
1604  case AsmToken::Identifier:
1605  if (isDarwin()) {
1606  unsigned RegNo;
1607  if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1608  Parser.Lex(); // Eat the identifier token.
1609  break;
1610  }
1611  }
1612  // Fall-through..
1613 
1614  default:
1615  return Error(S, "invalid memory operand");
1616  }
1617 
1618  if (getLexer().isNot(AsmToken::RParen))
1619  return Error(Parser.getTok().getLoc(), "missing ')'");
1620  E = Parser.getTok().getLoc();
1621  Parser.Lex(); // Eat the ')'.
1622 
1623  Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1624  }
1625 
1626  return false;
1627 }
1628 
1629 /// Parse an instruction mnemonic followed by its operands.
1630 bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
1631  SMLoc NameLoc, OperandVector &Operands) {
1632  // The first operand is the token for the instruction name.
1633  // If the next character is a '+' or '-', we need to add it to the
1634  // instruction name, to match what TableGen is doing.
1635  std::string NewOpcode;
1636  if (getLexer().is(AsmToken::Plus)) {
1637  getLexer().Lex();
1638  NewOpcode = Name;
1639  NewOpcode += '+';
1640  Name = NewOpcode;
1641  }
1642  if (getLexer().is(AsmToken::Minus)) {
1643  getLexer().Lex();
1644  NewOpcode = Name;
1645  NewOpcode += '-';
1646  Name = NewOpcode;
1647  }
1648  // If the instruction ends in a '.', we need to create a separate
1649  // token for it, to match what TableGen is doing.
1650  size_t Dot = Name.find('.');
1651  StringRef Mnemonic = Name.slice(0, Dot);
1652  if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1653  Operands.push_back(
1654  PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64()));
1655  else
1656  Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1657  if (Dot != StringRef::npos) {
1658  SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1659  StringRef DotStr = Name.slice(Dot, StringRef::npos);
1660  if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1661  Operands.push_back(
1662  PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64()));
1663  else
1664  Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1665  }
1666 
1667  // If there are no more operands then finish
1668  if (getLexer().is(AsmToken::EndOfStatement))
1669  return false;
1670 
1671  // Parse the first operand
1672  if (ParseOperand(Operands))
1673  return true;
1674 
1675  while (getLexer().isNot(AsmToken::EndOfStatement) &&
1676  getLexer().is(AsmToken::Comma)) {
1677  // Consume the comma token
1678  getLexer().Lex();
1679 
1680  // Parse the next operand
1681  if (ParseOperand(Operands))
1682  return true;
1683  }
1684 
1685  // We'll now deal with an unfortunate special case: the syntax for the dcbt
1686  // and dcbtst instructions differs for server vs. embedded cores.
1687  // The syntax for dcbt is:
1688  // dcbt ra, rb, th [server]
1689  // dcbt th, ra, rb [embedded]
1690  // where th can be omitted when it is 0. dcbtst is the same. We take the
1691  // server form to be the default, so swap the operands if we're parsing for
1692  // an embedded core (they'll be swapped again upon printing).
1693  if (STI.getFeatureBits()[PPC::FeatureBookE] &&
1694  Operands.size() == 4 &&
1695  (Name == "dcbt" || Name == "dcbtst")) {
1696  std::swap(Operands[1], Operands[3]);
1697  std::swap(Operands[2], Operands[1]);
1698  }
1699 
1700  return false;
1701 }
1702 
1703 /// ParseDirective parses the PPC specific directives
1704 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1705  StringRef IDVal = DirectiveID.getIdentifier();
1706  if (!isDarwin()) {
1707  if (IDVal == ".word")
1708  return ParseDirectiveWord(2, DirectiveID.getLoc());
1709  if (IDVal == ".llong")
1710  return ParseDirectiveWord(8, DirectiveID.getLoc());
1711  if (IDVal == ".tc")
1712  return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc());
1713  if (IDVal == ".machine")
1714  return ParseDirectiveMachine(DirectiveID.getLoc());
1715  if (IDVal == ".abiversion")
1716  return ParseDirectiveAbiVersion(DirectiveID.getLoc());
1717  if (IDVal == ".localentry")
1718  return ParseDirectiveLocalEntry(DirectiveID.getLoc());
1719  } else {
1720  if (IDVal == ".machine")
1721  return ParseDarwinDirectiveMachine(DirectiveID.getLoc());
1722  }
1723  return true;
1724 }
1725 
1726 /// ParseDirectiveWord
1727 /// ::= .word [ expression (, expression)* ]
1728 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1729  MCAsmParser &Parser = getParser();
1730  if (getLexer().isNot(AsmToken::EndOfStatement)) {
1731  for (;;) {
1732  const MCExpr *Value;
1733  if (getParser().parseExpression(Value))
1734  return false;
1735 
1736  getParser().getStreamer().EmitValue(Value, Size);
1737 
1738  if (getLexer().is(AsmToken::EndOfStatement))
1739  break;
1740 
1741  if (getLexer().isNot(AsmToken::Comma))
1742  return Error(L, "unexpected token in directive");
1743  Parser.Lex();
1744  }
1745  }
1746 
1747  Parser.Lex();
1748  return false;
1749 }
1750 
1751 /// ParseDirectiveTC
1752 /// ::= .tc [ symbol (, expression)* ]
1753 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) {
1754  MCAsmParser &Parser = getParser();
1755  // Skip TC symbol, which is only used with XCOFF.
1756  while (getLexer().isNot(AsmToken::EndOfStatement)
1757  && getLexer().isNot(AsmToken::Comma))
1758  Parser.Lex();
1759  if (getLexer().isNot(AsmToken::Comma)) {
1760  Error(L, "unexpected token in directive");
1761  return false;
1762  }
1763  Parser.Lex();
1764 
1765  // Align to word size.
1766  getParser().getStreamer().EmitValueToAlignment(Size);
1767 
1768  // Emit expressions.
1769  return ParseDirectiveWord(Size, L);
1770 }
1771 
1772 /// ParseDirectiveMachine (ELF platforms)
1773 /// ::= .machine [ cpu | "push" | "pop" ]
1774 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
1775  MCAsmParser &Parser = getParser();
1776  if (getLexer().isNot(AsmToken::Identifier) &&
1777  getLexer().isNot(AsmToken::String)) {
1778  Error(L, "unexpected token in directive");
1779  return false;
1780  }
1781 
1782  StringRef CPU = Parser.getTok().getIdentifier();
1783  Parser.Lex();
1784 
1785  // FIXME: Right now, the parser always allows any available
1786  // instruction, so the .machine directive is not useful.
1787  // Implement ".machine any" (by doing nothing) for the benefit
1788  // of existing assembler code. Likewise, we can then implement
1789  // ".machine push" and ".machine pop" as no-op.
1790  if (CPU != "any" && CPU != "push" && CPU != "pop") {
1791  Error(L, "unrecognized machine type");
1792  return false;
1793  }
1794 
1795  if (getLexer().isNot(AsmToken::EndOfStatement)) {
1796  Error(L, "unexpected token in directive");
1797  return false;
1798  }
1799  PPCTargetStreamer &TStreamer =
1800  *static_cast<PPCTargetStreamer *>(
1801  getParser().getStreamer().getTargetStreamer());
1802  TStreamer.emitMachine(CPU);
1803 
1804  return false;
1805 }
1806 
1807 /// ParseDarwinDirectiveMachine (Mach-o platforms)
1808 /// ::= .machine cpu-identifier
1809 bool PPCAsmParser::ParseDarwinDirectiveMachine(SMLoc L) {
1810  MCAsmParser &Parser = getParser();
1811  if (getLexer().isNot(AsmToken::Identifier) &&
1812  getLexer().isNot(AsmToken::String)) {
1813  Error(L, "unexpected token in directive");
1814  return false;
1815  }
1816 
1817  StringRef CPU = Parser.getTok().getIdentifier();
1818  Parser.Lex();
1819 
1820  // FIXME: this is only the 'default' set of cpu variants.
1821  // However we don't act on this information at present, this is simply
1822  // allowing parsing to proceed with minimal sanity checking.
1823  if (CPU != "ppc7400" && CPU != "ppc" && CPU != "ppc64") {
1824  Error(L, "unrecognized cpu type");
1825  return false;
1826  }
1827 
1828  if (isPPC64() && (CPU == "ppc7400" || CPU == "ppc")) {
1829  Error(L, "wrong cpu type specified for 64bit");
1830  return false;
1831  }
1832  if (!isPPC64() && CPU == "ppc64") {
1833  Error(L, "wrong cpu type specified for 32bit");
1834  return false;
1835  }
1836 
1837  if (getLexer().isNot(AsmToken::EndOfStatement)) {
1838  Error(L, "unexpected token in directive");
1839  return false;
1840  }
1841 
1842  return false;
1843 }
1844 
1845 /// ParseDirectiveAbiVersion
1846 /// ::= .abiversion constant-expression
1847 bool PPCAsmParser::ParseDirectiveAbiVersion(SMLoc L) {
1848  int64_t AbiVersion;
1849  if (getParser().parseAbsoluteExpression(AbiVersion)){
1850  Error(L, "expected constant expression");
1851  return false;
1852  }
1853  if (getLexer().isNot(AsmToken::EndOfStatement)) {
1854  Error(L, "unexpected token in directive");
1855  return false;
1856  }
1857 
1858  PPCTargetStreamer &TStreamer =
1859  *static_cast<PPCTargetStreamer *>(
1860  getParser().getStreamer().getTargetStreamer());
1861  TStreamer.emitAbiVersion(AbiVersion);
1862 
1863  return false;
1864 }
1865 
1866 /// ParseDirectiveLocalEntry
1867 /// ::= .localentry symbol, expression
1868 bool PPCAsmParser::ParseDirectiveLocalEntry(SMLoc L) {
1869  StringRef Name;
1870  if (getParser().parseIdentifier(Name)) {
1871  Error(L, "expected identifier in directive");
1872  return false;
1873  }
1874  MCSymbolELF *Sym = cast<MCSymbolELF>(getContext().getOrCreateSymbol(Name));
1875 
1876  if (getLexer().isNot(AsmToken::Comma)) {
1877  Error(L, "unexpected token in directive");
1878  return false;
1879  }
1880  Lex();
1881 
1882  const MCExpr *Expr;
1883  if (getParser().parseExpression(Expr)) {
1884  Error(L, "expected expression");
1885  return false;
1886  }
1887 
1888  if (getLexer().isNot(AsmToken::EndOfStatement)) {
1889  Error(L, "unexpected token in directive");
1890  return false;
1891  }
1892 
1893  PPCTargetStreamer &TStreamer =
1894  *static_cast<PPCTargetStreamer *>(
1895  getParser().getStreamer().getTargetStreamer());
1896  TStreamer.emitLocalEntry(Sym, Expr);
1897 
1898  return false;
1899 }
1900 
1901 
1902 
1903 /// Force static initialization.
1908 }
1909 
1910 #define GET_REGISTER_MATCHER
1911 #define GET_MATCHER_IMPLEMENTATION
1912 #include "PPCGenAsmMatcher.inc"
1913 
1914 // Define this matcher function after the auto-generated include so we
1915 // have the match class enum definitions.
1916 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
1917  unsigned Kind) {
1918  // If the kind is a token for a literal immediate, check if our asm
1919  // operand matches. This is for InstAliases which have a fixed-value
1920  // immediate in the syntax.
1921  int64_t ImmVal;
1922  switch (Kind) {
1923  case MCK_0: ImmVal = 0; break;
1924  case MCK_1: ImmVal = 1; break;
1925  case MCK_2: ImmVal = 2; break;
1926  case MCK_3: ImmVal = 3; break;
1927  case MCK_4: ImmVal = 4; break;
1928  case MCK_5: ImmVal = 5; break;
1929  case MCK_6: ImmVal = 6; break;
1930  case MCK_7: ImmVal = 7; break;
1931  default: return Match_InvalidOperand;
1932  }
1933 
1934  PPCOperand &Op = static_cast<PPCOperand &>(AsmOp);
1935  if (Op.isImm() && Op.getImm() == ImmVal)
1936  return Match_Success;
1937 
1938  return Match_InvalidOperand;
1939 }
1940 
1941 const MCExpr *
1942 PPCAsmParser::applyModifierToExpr(const MCExpr *E,
1944  MCContext &Ctx) {
1945  switch (Variant) {
1947  return PPCMCExpr::create(PPCMCExpr::VK_PPC_LO, E, false, Ctx);
1949  return PPCMCExpr::create(PPCMCExpr::VK_PPC_HI, E, false, Ctx);
1951  return PPCMCExpr::create(PPCMCExpr::VK_PPC_HA, E, false, Ctx);
1953  return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHER, E, false, Ctx);
1955  return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHERA, E, false, Ctx);
1957  return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHEST, E, false, Ctx);
1959  return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHESTA, E, false, Ctx);
1960  default:
1961  return nullptr;
1962  }
1963 }
static bool isReg(const MCInst &MI, unsigned OpNo)
bool isUInt< 8 >(uint64_t x)
Definition: MathExtras.h:294
std::enable_if< std::numeric_limits< T >::is_signed, bool >::type getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:347
static const MCPhysReg XRegsNoX0[32]
void push_back(const T &Elt)
Definition: SmallVector.h:222
static int64_t EvaluateCRExpr(const MCExpr *E)
static const MCUnaryExpr * create(Opcode Op, const MCExpr *Expr, MCContext &Ctx)
Definition: MCExpr.cpp:145
static const MCUnaryExpr * createMinus(const MCExpr *Expr, MCContext &Ctx)
Definition: MCExpr.h:377
#define R4(n)
const MCSymbol & getSymbol() const
Definition: MCExpr.h:328
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:315
const char * getPointer() const
Definition: SMLoc.h:33
size_t size() const
size - Get the string size.
Definition: StringRef.h:113
static unsigned MatchRegisterName(StringRef Name)
Generic assembler parser interface, for use by target specific assembly parsers.
Definition: MCAsmParser.h:64
static const PPCMCExpr * create(VariantKind Kind, const MCExpr *Expr, bool isDarwin, MCContext &Ctx)
Definition: PPCMCExpr.cpp:22
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:129
MCTargetAsmParser - Generic interface to target specific assembly parsers.
size_t find(char C, size_t From=0) const
Search for the first character C in the string.
Definition: StringRef.h:240
Multiplication.
Definition: MCExpr.h:423
ExprKind getKind() const
Definition: MCExpr.h:69
StringRef getString() const
Get the string for the current token, this includes all characters (for example, the quotes on string...
Definition: MCAsmLexer.h:100
StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition: StringRef.h:405
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
static const MCPhysReg VRegs[32]
static const MCPhysReg CRBITRegs[32]
virtual const AsmToken & Lex()=0
Get the next AsmToken in the stream, possibly handling file inclusion first.
static const MCPhysReg FRegs[32]
#define R2(n)
virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
Definition: MCStreamer.cpp:639
bool isMacOSX() const
isMacOSX - Is this a Mac OS X triple.
Definition: Triple.h:394
static const MCBinaryExpr * create(Opcode Op, const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.cpp:140
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:111
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:79
std::pair< StringRef, StringRef > getToken(StringRef Source, StringRef Delimiters=" \t\n\v\f\r")
getToken - This function extracts one token from source, ignoring any leading characters that appear ...
static const MCPhysReg VSSRegs[64]
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APInt.h:33
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:33
Target independent representation for an assembler token.
Definition: MCAsmLexer.h:22
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:159
Windows NT (Windows on ARM)
static const MCPhysReg CRRegs[8]
MCParsedAsmOperand - This abstract class represents a source-level assembly instruction operand...
static const MCPhysReg XRegs[32]
Context object for machine code objects.
Definition: MCContext.h:48
static unsigned QFRegs[32]
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:514
const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
Definition: StringRef.h:107
Unary assembler expressions.
Definition: MCExpr.h:352
virtual void emitLocalEntry(MCSymbolELF *S, const MCExpr *LocalOffset)=0
const AsmToken & getTok() const
Get the current AsmToken from the stream.
Definition: MCAsmParser.cpp:32
Unary expressions.
Definition: MCExpr.h:39
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:150
bool isImm() const
Definition: MCInst.h:57
const MCExpr * getExpr() const
Definition: MCInst.h:93
const MCExpr * getLHS() const
Get the left-hand side expression of the binary operator.
Definition: MCExpr.h:531
Streaming machine code generation interface.
Definition: MCStreamer.h:157
SMLoc getLoc() const
Definition: MCAsmLexer.cpp:26
virtual void emitAbiVersion(int AbiVersion)=0
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
void LLVMInitializePowerPCAsmParser()
Force static initialization.
SI Fold Operands
Binary assembler expressions.
Definition: MCExpr.h:405
void setLoc(SMLoc loc)
Definition: MCInst.h:161
static void addNegOperand(MCInst &Inst, MCOperand &Op, MCContext &Ctx)
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
void setOpcode(unsigned Op)
Definition: MCInst.h:158
#define R6(n)
Target ThePPC32Target
Target ThePPC64LETarget
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
bool is(TokenKind K) const
Definition: MCAsmLexer.h:72
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:576
unsigned getOpcode() const
Definition: MCInst.h:159
bool isUInt< 32 >(uint64_t x)
Definition: MathExtras.h:302
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
int64_t getImm() const
Definition: MCInst.h:74
static SMLoc getFromPointer(const char *Ptr)
Definition: SMLoc.h:35
const MCExpr * getRHS() const
Get the right-hand side expression of the binary operator.
Definition: MCExpr.h:534
StringRef getIdentifier() const
Get the identifier string for the current token, which should be an identifier or a string...
Definition: MCAsmLexer.h:89
static const MCPhysReg VSRegs[64]
const MCExpr * getSubExpr() const
Get the child of this unary expression.
Definition: MCExpr.h:395
RegisterMCAsmParser - Helper template for registering a target specific assembly parser, for use in the target machine initialization function.
StringRef getName() const
getName - Get the symbol name.
Definition: MCSymbol.h:205
static const size_t npos
Definition: StringRef.h:44
bool equals_lower(StringRef RHS) const
equals_lower - Check for string equality, ignoring case.
Definition: StringRef.h:142
unsigned getNumOperands() const
Definition: MCInst.h:166
#define N
Opcode getOpcode() const
Get the kind of this binary expression.
Definition: MCExpr.h:528
MCSubtargetInfo - Generic base class for all target subtargets.
References to labels and assigned expressions.
Definition: MCExpr.h:38
Unary minus.
Definition: MCExpr.h:356
static bool isMem(const MachineInstr *MI, unsigned Op)
Definition: X86InstrInfo.h:147
bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:272
const Triple & getTargetTriple() const
getTargetTriple - Return the target triple string.
static const MCPhysReg RRegs[32]
VariantKind getKind() const
Definition: MCExpr.h:330
const ARM::ArchExtKind Kind
static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME)
Returns true iff Val consists of one contiguous run of 1s with any number of 0s on either side...
LLVM Value Representation.
Definition: Value.h:69
SMLoc getEndLoc() const
Definition: MCAsmLexer.cpp:30
static const MCPhysReg VSFRegs[64]
Constant expressions.
Definition: MCExpr.h:37
Binary expressions.
Definition: MCExpr.h:36
bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:298
Target ThePPC64Target
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:38
Subtraction.
Definition: MCExpr.h:429
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
bool isPowerOf2_32(uint32_t Value)
isPowerOf2_32 - This function returns true if the argument is a power of two > 0. ...
Definition: MathExtras.h:354
void addOperand(const MCOperand &Op)
Definition: MCInst.h:168
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:40
Target specific expression.
Definition: MCExpr.h:40
StringRef slice(size_t Start, size_t End) const
Return a reference to the substring from [Start, End).
Definition: StringRef.h:434
virtual void emitMachine(StringRef CPU)=0
Represents a location in source code.
Definition: SMLoc.h:23
bool startswith_lower(StringRef Prefix) const
Check if this string starts with the given Prefix, ignoring case.
Definition: StringRef.cpp:61
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:33
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:117
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:164
static const MCPhysReg RRegsNoR0[32]
Opcode getOpcode() const
Get the kind of this unary expression.
Definition: MCExpr.h:392