28 #define DEBUG_TYPE "postrapseudos"
62 "Post-RA pseudo instruction expansion pass",
false,
false)
72 for (
unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
92 assert(SubIdx != 0 &&
"Invalid index for insert_subreg");
93 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
96 "Insert destination must be in a physical register");
98 "Inserted value must be in a physical register");
100 DEBUG(
dbgs() <<
"subreg: CONVERTING: " << *MI);
104 DEBUG(
dbgs() <<
"subreg: replaced by: " << *MI);
108 if (DstSubReg == InsReg) {
113 if (DstReg != InsReg) {
117 DEBUG(
dbgs() <<
"subreg: replace by: " << *MI);
128 CopyMI->addRegisterDefined(DstReg);
150 DEBUG(
dbgs() <<
"identity copy: " << *MI);
170 TransferImplicitDefs(MI);
173 dbgs() <<
"replaced by: " << *(--dMI);
184 <<
"********** EXPANDING POST-RA PSEUDO INSTRS **********\n"
185 <<
"********** Function: " << MF.
getName() <<
'\n');
189 bool MadeChange =
false;
192 mbbi != mbbe; ++mbbi) {
212 MadeChange |= LowerSubregToReg(MI);
215 MadeChange |= LowerCopy(MI);
char & MachineDominatorsID
MachineDominators - This pass is a machine dominators analysis pass.
bool isPseudo(QueryType Type=IgnoreBundle) const
Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction...
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
COPY - Target-independent register copy.
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false)
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
unsigned getNumOperands() const
Access to explicit operands of the instruction.
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
char & ExpandPostRAPseudosID
ExpandPostRAPseudos - This pass expands pseudo instructions after register allocation.
AnalysisUsage & addPreservedID(const void *ID)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineBasicBlock * getParent() const
TargetInstrInfo - Interface to description of machine instruction set.
DBG_VALUE - a mapping of the llvm.dbg.value intrinsic.
bundle_iterator< MachineInstr, instr_iterator > iterator
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
const MachineOperand & getOperand(unsigned i) const
INSERT_SUBREG - This instruction takes three operands: a register that has subregisters, a register providing an insert value, and a subregister index.
Represent the analysis usage information of a pass.
bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override
expandPostRAPseudo - This function is called for all pseudo instructions that remain after register a...
unsigned getSubReg() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
EXTRACT_SUBREG - This instruction takes two operands: a register that has subregisters, and a subregister index.
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
MachineOperand class - Representation of each machine instruction operand.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
INITIALIZE_PASS(ExpandPostRA,"postrapseudos","Post-RA pseudo instruction expansion pass", false, false) void ExpandPostRA
TransferImplicitDefs - MI is a pseudo-instruction, and the lowered replacement instructions immediate...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
KILL - This instruction is a noop that is used only to adjust the liveness of registers.
Representation of each machine instruction.
static bool isPhysicalRegister(unsigned Reg)
isPhysicalRegister - Return true if the specified register number is in the physical register namespa...
unsigned getReg() const
getReg - Returns the register number.
virtual const TargetInstrInfo * getInstrInfo() const
BasicBlockListType::iterator iterator
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except that the first operand is an imme...