LLVM  3.7.0
HexagonMachineFunctionInfo.h
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1 //=- HexagonMachineFunctionInfo.h - Hexagon machine function info -*- C++ -*-=//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINEFUNCTIONINFO_H
11 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINEFUNCTIONINFO_H
12 
14 #include <map>
15 
16 namespace llvm {
17 
18  namespace Hexagon {
19  const unsigned int StartPacket = 0x1;
20  const unsigned int EndPacket = 0x2;
21  }
22 
23 
24 /// Hexagon target-specific information for each MachineFunction.
26  // SRetReturnReg - Some subtargets require that sret lowering includes
27  // returning the value of the returned struct in a register. This field
28  // holds the virtual register into which the sret argument is passed.
29  unsigned SRetReturnReg;
30  unsigned StackAlignBaseReg;
31  std::vector<MachineInstr*> AllocaAdjustInsts;
32  int VarArgsFrameIndex;
33  bool HasClobberLR;
34  bool HasEHReturn;
35  std::map<const MachineInstr*, unsigned> PacketInfo;
36  virtual void anchor();
37 
38 public:
39  HexagonMachineFunctionInfo() : SRetReturnReg(0), StackAlignBaseReg(0),
40  HasClobberLR(0), HasEHReturn(false) {}
41 
43  StackAlignBaseReg(0),
44  HasClobberLR(0),
45  HasEHReturn(false) {}
46 
47  unsigned getSRetReturnReg() const { return SRetReturnReg; }
48  void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; }
49 
51  AllocaAdjustInsts.push_back(MI);
52  }
53  const std::vector<MachineInstr*>& getAllocaAdjustInsts() {
54  return AllocaAdjustInsts;
55  }
56 
57  void setVarArgsFrameIndex(int v) { VarArgsFrameIndex = v; }
58  int getVarArgsFrameIndex() { return VarArgsFrameIndex; }
59 
61  PacketInfo[MI] |= Hexagon::StartPacket;
62  }
64  PacketInfo[MI] |= Hexagon::EndPacket;
65  }
66  bool isStartPacket(const MachineInstr* MI) const {
67  return (PacketInfo.count(MI) &&
68  (PacketInfo.find(MI)->second & Hexagon::StartPacket));
69  }
70  bool isEndPacket(const MachineInstr* MI) const {
71  return (PacketInfo.count(MI) &&
72  (PacketInfo.find(MI)->second & Hexagon::EndPacket));
73  }
74  void setHasClobberLR(bool v) { HasClobberLR = v; }
75  bool hasClobberLR() const { return HasClobberLR; }
76 
77  bool hasEHReturn() const { return HasEHReturn; };
78  void setHasEHReturn(bool H = true) { HasEHReturn = H; };
79 
80  void setStackAlignBaseVReg(unsigned R) { StackAlignBaseReg = R; }
81  unsigned getStackAlignBaseVReg() const { return StackAlignBaseReg; }
82 };
83 } // End llvm namespace
84 
85 #endif
const unsigned int StartPacket
bool isEndPacket(const MachineInstr *MI) const
Hexagon target-specific information for each MachineFunction.
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
Reg
All possible values of the reg field in the ModR/M byte.
#define false
Definition: ConvertUTF.c:65
#define H(x, y, z)
Definition: MD5.cpp:53
const std::vector< MachineInstr * > & getAllocaAdjustInsts()
const unsigned int EndPacket
bool isStartPacket(const MachineInstr *MI) const
Representation of each machine instruction.
Definition: MachineInstr.h:51