LLVM  3.7.0
TargetSubtargetInfo.h
Go to the documentation of this file.
1 //==-- llvm/Target/TargetSubtargetInfo.h - Target Information ----*- C++ -*-==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file describes the subtarget options of a Target machine.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_TARGET_TARGETSUBTARGETINFO_H
15 #define LLVM_TARGET_TARGETSUBTARGETINFO_H
16 
19 #include "llvm/Support/CodeGen.h"
20 
21 namespace llvm {
22 
23 class DataLayout;
24 class MachineFunction;
25 class MachineInstr;
26 class SDep;
27 class SUnit;
28 class TargetFrameLowering;
29 class TargetInstrInfo;
30 class TargetLowering;
31 class TargetRegisterClass;
32 class TargetRegisterInfo;
33 class TargetSchedModel;
34 class TargetSelectionDAGInfo;
35 struct MachineSchedPolicy;
36 template <typename T> class SmallVectorImpl;
37 
38 //===----------------------------------------------------------------------===//
39 ///
40 /// TargetSubtargetInfo - Generic base class for all target subtargets. All
41 /// Target-specific options that control code generation and printing should
42 /// be exposed through a TargetSubtargetInfo-derived class.
43 ///
45  TargetSubtargetInfo(const TargetSubtargetInfo &) = delete;
46  void operator=(const TargetSubtargetInfo &) = delete;
47  TargetSubtargetInfo() = delete;
48 
49 protected: // Can only create subclasses...
53  const SubtargetInfoKV *ProcSched,
54  const MCWriteProcResEntry *WPR,
55  const MCWriteLatencyEntry *WL,
56  const MCReadAdvanceEntry *RA, const InstrStage *IS,
57  const unsigned *OC, const unsigned *FP);
58 
59 public:
60  // AntiDepBreakMode - Type of anti-dependence breaking that should
61  // be performed before post-RA scheduling.
64 
65  virtual ~TargetSubtargetInfo();
66 
67  // Interfaces to the major aspects of target machine information:
68  //
69  // -- Instruction opcode and operand information
70  // -- Pipelines and scheduling information
71  // -- Stack frame information
72  // -- Selection DAG lowering information
73  //
74  // N.B. These objects may change during compilation. It's not safe to cache
75  // them between functions.
76  virtual const TargetInstrInfo *getInstrInfo() const { return nullptr; }
77  virtual const TargetFrameLowering *getFrameLowering() const {
78  return nullptr;
79  }
80  virtual const TargetLowering *getTargetLowering() const { return nullptr; }
82  return nullptr;
83  }
84 
85  /// getRegisterInfo - If register information is available, return it. If
86  /// not, return null. This is kept separate from RegInfo until RegInfo has
87  /// details of graph coloring register allocation removed from it.
88  ///
89  virtual const TargetRegisterInfo *getRegisterInfo() const { return nullptr; }
90 
91  /// getInstrItineraryData - Returns instruction itinerary data for the target
92  /// or specific subtarget.
93  ///
94  virtual const InstrItineraryData *getInstrItineraryData() const {
95  return nullptr;
96  }
97 
98  /// Resolve a SchedClass at runtime, where SchedClass identifies an
99  /// MCSchedClassDesc with the isVariant property. This may return the ID of
100  /// another variant SchedClass, but repeated invocation must quickly terminate
101  /// in a nonvariant SchedClass.
102  virtual unsigned resolveSchedClass(unsigned SchedClass,
103  const MachineInstr *MI,
104  const TargetSchedModel *SchedModel) const {
105  return 0;
106  }
107 
108  /// \brief True if the subtarget should run MachineScheduler after aggressive
109  /// coalescing.
110  ///
111  /// This currently replaces the SelectionDAG scheduler with the "source" order
112  /// scheduler (though see below for an option to turn this off and use the
113  /// TargetLowering preference). It does not yet disable the postRA scheduler.
114  virtual bool enableMachineScheduler() const;
115 
116  /// \brief True if the machine scheduler should disable the TLI preference
117  /// for preRA scheduling with the source level scheduler.
118  virtual bool enableMachineSchedDefaultSched() const { return true; }
119 
120  /// \brief True if the subtarget should enable joining global copies.
121  ///
122  /// By default this is enabled if the machine scheduler is enabled, but
123  /// can be overridden.
124  virtual bool enableJoinGlobalCopies() const;
125 
126  /// True if the subtarget should run a scheduler after register allocation.
127  ///
128  /// By default this queries the PostRAScheduling bit in the scheduling model
129  /// which is the preferred way to influence this.
130  virtual bool enablePostRAScheduler() const;
131 
132  /// \brief True if the subtarget should run the atomic expansion pass.
133  virtual bool enableAtomicExpand() const;
134 
135  /// \brief Override generic scheduling policy within a region.
136  ///
137  /// This is a convenient way for targets that don't provide any custom
138  /// scheduling heuristics (no custom MachineSchedStrategy) to make
139  /// changes to the generic scheduling policy.
142  unsigned NumRegionInstrs) const {}
143 
144  // \brief Perform target specific adjustments to the latency of a schedule
145  // dependency.
146  virtual void adjustSchedDependency(SUnit *def, SUnit *use, SDep &dep) const {}
147 
148  // For use with PostRAScheduling: get the anti-dependence breaking that should
149  // be performed before post-RA scheduling.
151 
152  // For use with PostRAScheduling: in CriticalPathRCs, return any register
153  // classes that should only be considered for anti-dependence breaking if they
154  // are on the critical path.
155  virtual void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
156  return CriticalPathRCs.clear();
157  }
158 
159  // For use with PostRAScheduling: get the minimum optimization level needed
160  // to enable post-RA scheduling.
162  return CodeGenOpt::Default;
163  }
164 
165  /// \brief True if the subtarget should run the local reassignment
166  /// heuristic of the register allocator.
167  /// This heuristic may be compile time intensive, \p OptLevel provides
168  /// a finer grain to tune the register allocator.
169  virtual bool enableRALocalReassignment(CodeGenOpt::Level OptLevel) const;
170 
171  /// \brief Enable use of alias analysis during code generation (during MI
172  /// scheduling, DAGCombine, etc.).
173  virtual bool useAA() const;
174 
175  /// \brief Enable the use of the early if conversion pass.
176  virtual bool enableEarlyIfConversion() const { return false; }
177 
178  /// \brief Return PBQPConstraint(s) for the target.
179  ///
180  /// Override to provide custom PBQP constraints.
181  virtual std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const {
182  return nullptr;
183  }
184 
185  /// Enable tracking of subregister liveness in register allocator.
186  virtual bool enableSubRegLiveness() const { return false; }
187 };
188 
189 } // End llvm namespace
190 
191 #endif
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:240
virtual bool enableMachineScheduler() const
True if the subtarget should run MachineScheduler after aggressive coalescing.
virtual bool enableAtomicExpand() const
True if the subtarget should run the atomic expansion pass.
virtual bool enableSubRegLiveness() const
Enable tracking of subregister liveness in register allocator.
const_iterator begin(StringRef path)
Get begin iterator over path.
Definition: Path.cpp:232
virtual bool enablePostRAScheduler() const
True if the subtarget should run a scheduler after register allocation.
SubtargetInfoKV - Used to provide key value pairs for CPU and arbitrary pointers. ...
virtual CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const
virtual AntiDepBreakMode getAntiDepBreakMode() const
Provide an instruction scheduling machine model to CodeGen passes.
virtual std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints() const
Return PBQPConstraint(s) for the target.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APInt.h:33
virtual const InstrItineraryData * getInstrItineraryData() const
getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual bool enableJoinGlobalCopies() const
True if the subtarget should enable joining global copies.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: ArrayRef.h:31
virtual void adjustSchedDependency(SUnit *def, SUnit *use, SDep &dep) const
Itinerary data supplied by a subtarget to be used by a target.
TargetSelectionDAGInfo - Targets can subclass this to parameterize the SelectionDAG lowering and inst...
TargetInstrInfo - Interface to description of machine instruction set.
SDep - Scheduling dependency.
Definition: ScheduleDAG.h:45
virtual void overrideSchedPolicy(MachineSchedPolicy &Policy, MachineInstr *begin, MachineInstr *end, unsigned NumRegionInstrs) const
Override generic scheduling policy within a region.
Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...
Definition: MCSchedule.h:55
virtual bool enableEarlyIfConversion() const
Enable the use of the early if conversion pass.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual bool enableMachineSchedDefaultSched() const
True if the machine scheduler should disable the TLI preference for preRA scheduling with the source ...
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
virtual const TargetSelectionDAGInfo * getSelectionDAGInfo() const
virtual const TargetFrameLowering * getFrameLowering() const
Specify the latency in cpu cycles for a particular scheduling class and def index.
Definition: MCSchedule.h:69
virtual const TargetLowering * getTargetLowering() const
virtual unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const
Resolve a SchedClass at runtime, where SchedClass identifies an MCSchedClassDesc with the isVariant p...
Information about stack frame layout on the target.
Specify the number of cycles allowed after instruction issue before a particular use operand reads it...
Definition: MCSchedule.h:86
TargetSubtargetInfo - Generic base class for all target subtargets.
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.
Representation of each machine instruction.
Definition: MachineInstr.h:51
These values represent a non-pipelined step in the execution of an instruction.
MCSubtargetInfo - Generic base class for all target subtargets.
virtual bool enableRALocalReassignment(CodeGenOpt::Level OptLevel) const
True if the subtarget should run the local reassignment heuristic of the register allocator...
virtual void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const
virtual const TargetInstrInfo * getInstrInfo() const
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:40
SmallVectorImpl< const TargetRegisterClass * > RegClassVector
SUnit - Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:261
virtual bool useAA() const
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.).