27 #define DEBUG_TYPE "mips-mc-nacl"
31 const unsigned IndirectBranchMaskReg = Mips::T6;
32 const unsigned LoadStoreStackMaskReg = Mips::T7;
43 ~MipsNaClELFStreamer()
override {}
50 bool isIndirectJump(
const MCInst &
MI) {
60 bool isStackPointerFirstOperand(
const MCInst &MI) {
68 *IsIndirectCall =
false;
88 *IsIndirectCall =
true;
93 void emitMask(
unsigned AddrReg,
unsigned MaskReg,
108 EmitBundleLock(
false);
109 emitMask(AddrReg, IndirectBranchMaskReg, STI);
116 void sandboxLoadStoreStackChange(
const MCInst &MI,
unsigned AddrIdx,
119 EmitBundleLock(
false);
123 emitMask(BaseReg, LoadStoreStackMaskReg, STI);
129 assert((Mips::SP == SPReg) &&
"Unexpected stack-pointer register.");
130 emitMask(SPReg, LoadStoreStackMaskReg, STI);
138 void EmitInstruction(
const MCInst &Inst,
141 if (isIndirectJump(Inst)) {
144 sandboxIndirectJump(Inst, STI);
153 bool IsSPFirstOperand = isStackPointerFirstOperand(Inst);
154 if (IsMemAccess || IsSPFirstOperand) {
155 bool MaskBefore = (IsMemAccess
158 bool MaskAfter = IsSPFirstOperand && !IsStore;
159 if (MaskBefore || MaskAfter) {
162 sandboxLoadStoreStackChange(Inst, AddrIdx, STI, MaskBefore, MaskAfter);
171 if (isCall(Inst, &IsIndirectCall)) {
176 EmitBundleLock(
true);
177 if (IsIndirectCall) {
179 emitMask(TargetReg, IndirectBranchMaskReg, STI);
251 return Reg != Mips::SP && Reg !=
Mips::T8;
258 MipsNaClELFStreamer *S =
new MipsNaClELFStreamer(Context, TAB, OS, Emitter);
260 S->getAssembler().setRelaxAll(
true);
bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx, bool *IsStore=nullptr)
static bool IsIndirectCall(MachineInstr *MI)
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag=true)
Reports a serious error, calling any installed error handler.
static MCOperand createReg(unsigned Reg)
Reg
All possible values of the reg field in the ModR/M byte.
bool baseRegNeedsLoadStoreMask(unsigned Reg)
Context object for machine code objects.
unsigned getReg() const
Returns the register number.
Instances of this class represent a single low-level machine instruction.
MCCodeEmitter - Generic instruction encoding interface.
MCELFStreamer * createMipsNaClELFStreamer(MCContext &Context, MCAsmBackend &TAB, raw_pwrite_stream &OS, MCCodeEmitter *Emitter, bool RelaxAll)
void setOpcode(unsigned Op)
CHAIN = SC CHAIN, Imm128 - System call.
unsigned getOpcode() const
static const unsigned MIPS_NACL_BUNDLE_ALIGN
unsigned getNumOperands() const
MCSubtargetInfo - Generic base class for all target subtargets.
An abstract base class for streams implementations that also support a pwrite operation.
cl::opt< bool > RelaxAll("mc-relax-all", cl::desc("When used with filetype=obj, ""relax all fixups in the emitted object file"))
Generic interface to target specific assembler backends.
void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override
Overriding this function allows us to add arbitrary behaviour before the Inst is actually emitted...
void addOperand(const MCOperand &Op)
const MCOperand & getOperand(unsigned i) const