LLVM  3.7.0
MachineRegisterInfo.h
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1 //===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the MachineRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
15 #define LLVM_CODEGEN_MACHINEREGISTERINFO_H
16 
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/IndexedMap.h"
24 #include <vector>
25 
26 namespace llvm {
27 class PSetIterator;
28 
29 /// MachineRegisterInfo - Keep track of information for virtual and physical
30 /// registers, including vreg register classes, use/def chains for registers,
31 /// etc.
33 public:
34  class Delegate {
35  virtual void anchor();
36  public:
37  virtual void MRI_NoteNewVirtualRegister(unsigned Reg) = 0;
38 
39  virtual ~Delegate() {}
40  };
41 
42 private:
43  const MachineFunction *MF;
44  Delegate *TheDelegate;
45 
46  /// IsSSA - True when the machine function is in SSA form and virtual
47  /// registers have a single def.
48  bool IsSSA;
49 
50  /// TracksLiveness - True while register liveness is being tracked accurately.
51  /// Basic block live-in lists, kill flags, and implicit defs may not be
52  /// accurate when after this flag is cleared.
53  bool TracksLiveness;
54 
55  /// True if subregister liveness is tracked.
56  bool TracksSubRegLiveness;
57 
58  /// VRegInfo - Information we keep for each virtual register.
59  ///
60  /// Each element in this list contains the register class of the vreg and the
61  /// start of the use/def list for the register.
63  VirtReg2IndexFunctor> VRegInfo;
64 
65  /// RegAllocHints - This vector records register allocation hints for virtual
66  /// registers. For each virtual register, it keeps a register and hint type
67  /// pair making up the allocation hint. Hint type is target specific except
68  /// for the value 0 which means the second value of the pair is the preferred
69  /// register for allocation. For example, if the hint is <0, 1024>, it means
70  /// the allocator should prefer the physical register allocated to the virtual
71  /// register of the hint.
73 
74  /// PhysRegUseDefLists - This is an array of the head of the use/def list for
75  /// physical registers.
76  std::vector<MachineOperand *> PhysRegUseDefLists;
77 
78  /// getRegUseDefListHead - Return the head pointer for the register use/def
79  /// list for the specified virtual or physical register.
80  MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
82  return VRegInfo[RegNo].second;
83  return PhysRegUseDefLists[RegNo];
84  }
85 
86  MachineOperand *getRegUseDefListHead(unsigned RegNo) const {
88  return VRegInfo[RegNo].second;
89  return PhysRegUseDefLists[RegNo];
90  }
91 
92  /// Get the next element in the use-def chain.
93  static MachineOperand *getNextOperandForReg(const MachineOperand *MO) {
94  assert(MO && MO->isReg() && "This is not a register operand!");
95  return MO->Contents.Reg.Next;
96  }
97 
98  /// UsedRegUnits - This is a bit vector that is computed and set by the
99  /// register allocator, and must be kept up to date by passes that run after
100  /// register allocation (though most don't modify this). This is used
101  /// so that the code generator knows which callee save registers to save and
102  /// for other target specific uses.
103  /// This vector has bits set for register units that are modified in the
104  /// current function. It doesn't include registers clobbered by function
105  /// calls with register mask operands.
106  BitVector UsedRegUnits;
107 
108  /// UsedPhysRegMask - Additional used physregs including aliases.
109  /// This bit vector represents all the registers clobbered by function calls.
110  /// It can model things that UsedRegUnits can't, such as function calls that
111  /// clobber ymm7 but preserve the low half in xmm7.
112  BitVector UsedPhysRegMask;
113 
114  /// ReservedRegs - This is a bit vector of reserved registers. The target
115  /// may change its mind about which registers should be reserved. This
116  /// vector is the frozen set of reserved registers when register allocation
117  /// started.
118  BitVector ReservedRegs;
119 
120  /// Keep track of the physical registers that are live in to the function.
121  /// Live in values are typically arguments in registers. LiveIn values are
122  /// allowed to have virtual registers associated with them, stored in the
123  /// second element.
124  std::vector<std::pair<unsigned, unsigned> > LiveIns;
125 
126  MachineRegisterInfo(const MachineRegisterInfo&) = delete;
127  void operator=(const MachineRegisterInfo&) = delete;
128 public:
129  explicit MachineRegisterInfo(const MachineFunction *MF);
130 
132  return MF->getSubtarget().getRegisterInfo();
133  }
134 
135  void resetDelegate(Delegate *delegate) {
136  // Ensure another delegate does not take over unless the current
137  // delegate first unattaches itself. If we ever need to multicast
138  // notifications, we will need to change to using a list.
139  assert(TheDelegate == delegate &&
140  "Only the current delegate can perform reset!");
141  TheDelegate = nullptr;
142  }
143 
144  void setDelegate(Delegate *delegate) {
145  assert(delegate && !TheDelegate &&
146  "Attempted to set delegate to null, or to change it without "
147  "first resetting it!");
148 
149  TheDelegate = delegate;
150  }
151 
152  //===--------------------------------------------------------------------===//
153  // Function State
154  //===--------------------------------------------------------------------===//
155 
156  // isSSA - Returns true when the machine function is in SSA form. Early
157  // passes require the machine function to be in SSA form where every virtual
158  // register has a single defining instruction.
159  //
160  // The TwoAddressInstructionPass and PHIElimination passes take the machine
161  // function out of SSA form when they introduce multiple defs per virtual
162  // register.
163  bool isSSA() const { return IsSSA; }
164 
165  // leaveSSA - Indicates that the machine function is no longer in SSA form.
166  void leaveSSA() { IsSSA = false; }
167 
168  /// tracksLiveness - Returns true when tracking register liveness accurately.
169  ///
170  /// While this flag is true, register liveness information in basic block
171  /// live-in lists and machine instruction operands is accurate. This means it
172  /// can be used to change the code in ways that affect the values in
173  /// registers, for example by the register scavenger.
174  ///
175  /// When this flag is false, liveness is no longer reliable.
176  bool tracksLiveness() const { return TracksLiveness; }
177 
178  /// invalidateLiveness - Indicates that register liveness is no longer being
179  /// tracked accurately.
180  ///
181  /// This should be called by late passes that invalidate the liveness
182  /// information.
183  void invalidateLiveness() { TracksLiveness = false; }
184 
185  /// Returns true if liveness for register class @p RC should be tracked at
186  /// the subregister level.
189  }
190  bool shouldTrackSubRegLiveness(unsigned VReg) const {
191  assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Must pass a VReg");
192  return shouldTrackSubRegLiveness(*getRegClass(VReg));
193  }
194  bool subRegLivenessEnabled() const {
195  return TracksSubRegLiveness;
196  }
197 
198  void enableSubRegLiveness(bool Enable = true) {
199  TracksSubRegLiveness = Enable;
200  }
201 
202  //===--------------------------------------------------------------------===//
203  // Register Info
204  //===--------------------------------------------------------------------===//
205 
206  // Strictly for use by MachineInstr.cpp.
208 
209  // Strictly for use by MachineInstr.cpp.
211 
212  // Strictly for use by MachineInstr.cpp.
213  void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps);
214 
215  /// Verify the sanity of the use list for Reg.
216  void verifyUseList(unsigned Reg) const;
217 
218  /// Verify the use list of all registers.
219  void verifyUseLists() const;
220 
221  /// reg_begin/reg_end - Provide iteration support to walk over all definitions
222  /// and uses of a register within the MachineFunction that corresponds to this
223  /// MachineRegisterInfo object.
224  template<bool Uses, bool Defs, bool SkipDebug,
225  bool ByOperand, bool ByInstr, bool ByBundle>
227  template<bool Uses, bool Defs, bool SkipDebug,
228  bool ByOperand, bool ByInstr, bool ByBundle>
230 
231  // Make it a friend so it can access getNextOperandForReg().
232  template<bool, bool, bool, bool, bool, bool>
233  friend class defusechain_iterator;
234  template<bool, bool, bool, bool, bool, bool>
236 
237 
238 
239  /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
240  /// register.
243  reg_iterator reg_begin(unsigned RegNo) const {
244  return reg_iterator(getRegUseDefListHead(RegNo));
245  }
246  static reg_iterator reg_end() { return reg_iterator(nullptr); }
247 
250  }
251 
252  /// reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses
253  /// of the specified register, stepping by MachineInstr.
254  typedef defusechain_instr_iterator<true,true,false,false,true,false>
256  reg_instr_iterator reg_instr_begin(unsigned RegNo) const {
257  return reg_instr_iterator(getRegUseDefListHead(RegNo));
258  }
260  return reg_instr_iterator(nullptr);
261  }
262 
264  reg_instructions(unsigned Reg) const {
266  reg_instr_end());
267  }
268 
269  /// reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses
270  /// of the specified register, stepping by bundle.
271  typedef defusechain_instr_iterator<true,true,false,false,false,true>
273  reg_bundle_iterator reg_bundle_begin(unsigned RegNo) const {
274  return reg_bundle_iterator(getRegUseDefListHead(RegNo));
275  }
277  return reg_bundle_iterator(nullptr);
278  }
279 
282  reg_bundle_end());
283  }
284 
285  /// reg_empty - Return true if there are no instructions using or defining the
286  /// specified register (it may be live-in).
287  bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); }
288 
289  /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses
290  /// of the specified register, skipping those marked as Debug.
291  typedef defusechain_iterator<true,true,true,true,false,false>
293  reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const {
294  return reg_nodbg_iterator(getRegUseDefListHead(RegNo));
295  }
297  return reg_nodbg_iterator(nullptr);
298  }
299 
301  reg_nodbg_operands(unsigned Reg) const {
303  reg_nodbg_end());
304  }
305 
306  /// reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk
307  /// all defs and uses of the specified register, stepping by MachineInstr,
308  /// skipping those marked as Debug.
309  typedef defusechain_instr_iterator<true,true,true,false,true,false>
312  return reg_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
313  }
315  return reg_instr_nodbg_iterator(nullptr);
316  }
317 
319  reg_nodbg_instructions(unsigned Reg) const {
322  }
323 
324  /// reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk
325  /// all defs and uses of the specified register, stepping by bundle,
326  /// skipping those marked as Debug.
327  typedef defusechain_instr_iterator<true,true,true,false,false,true>
330  return reg_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
331  }
333  return reg_bundle_nodbg_iterator(nullptr);
334  }
335 
337  reg_nodbg_bundles(unsigned Reg) const {
340  }
341 
342  /// reg_nodbg_empty - Return true if the only instructions using or defining
343  /// Reg are Debug instructions.
344  bool reg_nodbg_empty(unsigned RegNo) const {
345  return reg_nodbg_begin(RegNo) == reg_nodbg_end();
346  }
347 
348  /// def_iterator/def_begin/def_end - Walk all defs of the specified register.
349  typedef defusechain_iterator<false,true,false,true,false,false>
351  def_iterator def_begin(unsigned RegNo) const {
352  return def_iterator(getRegUseDefListHead(RegNo));
353  }
354  static def_iterator def_end() { return def_iterator(nullptr); }
355 
358  }
359 
360  /// def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the
361  /// specified register, stepping by MachineInst.
362  typedef defusechain_instr_iterator<false,true,false,false,true,false>
364  def_instr_iterator def_instr_begin(unsigned RegNo) const {
365  return def_instr_iterator(getRegUseDefListHead(RegNo));
366  }
368  return def_instr_iterator(nullptr);
369  }
370 
372  def_instructions(unsigned Reg) const {
374  def_instr_end());
375  }
376 
377  /// def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the
378  /// specified register, stepping by bundle.
379  typedef defusechain_instr_iterator<false,true,false,false,false,true>
381  def_bundle_iterator def_bundle_begin(unsigned RegNo) const {
382  return def_bundle_iterator(getRegUseDefListHead(RegNo));
383  }
385  return def_bundle_iterator(nullptr);
386  }
387 
390  def_bundle_end());
391  }
392 
393  /// def_empty - Return true if there are no instructions defining the
394  /// specified register (it may be live-in).
395  bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); }
396 
397  /// hasOneDef - Return true if there is exactly one instruction defining the
398  /// specified register.
399  bool hasOneDef(unsigned RegNo) const {
400  def_iterator DI = def_begin(RegNo);
401  if (DI == def_end())
402  return false;
403  return ++DI == def_end();
404  }
405 
406  /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
407  typedef defusechain_iterator<true,false,false,true,false,false>
409  use_iterator use_begin(unsigned RegNo) const {
410  return use_iterator(getRegUseDefListHead(RegNo));
411  }
412  static use_iterator use_end() { return use_iterator(nullptr); }
413 
416  }
417 
418  /// use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the
419  /// specified register, stepping by MachineInstr.
420  typedef defusechain_instr_iterator<true,false,false,false,true,false>
422  use_instr_iterator use_instr_begin(unsigned RegNo) const {
423  return use_instr_iterator(getRegUseDefListHead(RegNo));
424  }
426  return use_instr_iterator(nullptr);
427  }
428 
430  use_instructions(unsigned Reg) const {
432  use_instr_end());
433  }
434 
435  /// use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the
436  /// specified register, stepping by bundle.
437  typedef defusechain_instr_iterator<true,false,false,false,false,true>
439  use_bundle_iterator use_bundle_begin(unsigned RegNo) const {
440  return use_bundle_iterator(getRegUseDefListHead(RegNo));
441  }
443  return use_bundle_iterator(nullptr);
444  }
445 
448  use_bundle_end());
449  }
450 
451  /// use_empty - Return true if there are no instructions using the specified
452  /// register.
453  bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); }
454 
455  /// hasOneUse - Return true if there is exactly one instruction using the
456  /// specified register.
457  bool hasOneUse(unsigned RegNo) const {
458  use_iterator UI = use_begin(RegNo);
459  if (UI == use_end())
460  return false;
461  return ++UI == use_end();
462  }
463 
464  /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the
465  /// specified register, skipping those marked as Debug.
466  typedef defusechain_iterator<true,false,true,true,false,false>
468  use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const {
469  return use_nodbg_iterator(getRegUseDefListHead(RegNo));
470  }
472  return use_nodbg_iterator(nullptr);
473  }
474 
476  use_nodbg_operands(unsigned Reg) const {
478  use_nodbg_end());
479  }
480 
481  /// use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk
482  /// all uses of the specified register, stepping by MachineInstr, skipping
483  /// those marked as Debug.
484  typedef defusechain_instr_iterator<true,false,true,false,true,false>
487  return use_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
488  }
490  return use_instr_nodbg_iterator(nullptr);
491  }
492 
494  use_nodbg_instructions(unsigned Reg) const {
497  }
498 
499  /// use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk
500  /// all uses of the specified register, stepping by bundle, skipping
501  /// those marked as Debug.
502  typedef defusechain_instr_iterator<true,false,true,false,false,true>
505  return use_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
506  }
508  return use_bundle_nodbg_iterator(nullptr);
509  }
510 
512  use_nodbg_bundles(unsigned Reg) const {
515  }
516 
517  /// use_nodbg_empty - Return true if there are no non-Debug instructions
518  /// using the specified register.
519  bool use_nodbg_empty(unsigned RegNo) const {
520  return use_nodbg_begin(RegNo) == use_nodbg_end();
521  }
522 
523  /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
524  /// instruction using the specified register.
525  bool hasOneNonDBGUse(unsigned RegNo) const;
526 
527  /// replaceRegWith - Replace all instances of FromReg with ToReg in the
528  /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
529  /// except that it also changes any definitions of the register as well.
530  ///
531  /// Note that it is usually necessary to first constrain ToReg's register
532  /// class to match the FromReg constraints using:
533  ///
534  /// constrainRegClass(ToReg, getRegClass(FromReg))
535  ///
536  /// That function will return NULL if the virtual registers have incompatible
537  /// constraints.
538  ///
539  /// Note that if ToReg is a physical register the function will replace and
540  /// apply sub registers to ToReg in order to obtain a final/proper physical
541  /// register.
542  void replaceRegWith(unsigned FromReg, unsigned ToReg);
543 
544  /// getVRegDef - Return the machine instr that defines the specified virtual
545  /// register or null if none is found. This assumes that the code is in SSA
546  /// form, so there should only be one definition.
547  MachineInstr *getVRegDef(unsigned Reg) const;
548 
549  /// getUniqueVRegDef - Return the unique machine instr that defines the
550  /// specified virtual register or null if none is found. If there are
551  /// multiple definitions or no definition, return null.
552  MachineInstr *getUniqueVRegDef(unsigned Reg) const;
553 
554  /// clearKillFlags - Iterate over all the uses of the given register and
555  /// clear the kill flag from the MachineOperand. This function is used by
556  /// optimization passes which extend register lifetimes and need only
557  /// preserve conservative kill flag information.
558  void clearKillFlags(unsigned Reg) const;
559 
560 #ifndef NDEBUG
561  void dumpUses(unsigned RegNo) const;
562 #endif
563 
564  /// isConstantPhysReg - Returns true if PhysReg is unallocatable and constant
565  /// throughout the function. It is safe to move instructions that read such
566  /// a physreg.
567  bool isConstantPhysReg(unsigned PhysReg, const MachineFunction &MF) const;
568 
569  /// Get an iterator over the pressure sets affected by the given physical or
570  /// virtual register. If RegUnit is physical, it must be a register unit (from
571  /// MCRegUnitIterator).
572  PSetIterator getPressureSets(unsigned RegUnit) const;
573 
574  //===--------------------------------------------------------------------===//
575  // Virtual Register Info
576  //===--------------------------------------------------------------------===//
577 
578  /// getRegClass - Return the register class of the specified virtual register.
579  ///
580  const TargetRegisterClass *getRegClass(unsigned Reg) const {
581  return VRegInfo[Reg].first;
582  }
583 
584  /// setRegClass - Set the register class of the specified virtual register.
585  ///
586  void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
587 
588  /// constrainRegClass - Constrain the register class of the specified virtual
589  /// register to be a common subclass of RC and the current register class,
590  /// but only if the new class has at least MinNumRegs registers. Return the
591  /// new register class, or NULL if no such class exists.
592  /// This should only be used when the constraint is known to be trivial, like
593  /// GR32 -> GR32_NOSP. Beware of increasing register pressure.
594  ///
595  const TargetRegisterClass *constrainRegClass(unsigned Reg,
596  const TargetRegisterClass *RC,
597  unsigned MinNumRegs = 0);
598 
599  /// recomputeRegClass - Try to find a legal super-class of Reg's register
600  /// class that still satisfies the constraints from the instructions using
601  /// Reg. Returns true if Reg was upgraded.
602  ///
603  /// This method can be used after constraints have been removed from a
604  /// virtual register, for example after removing instructions or splitting
605  /// the live range.
606  ///
607  bool recomputeRegClass(unsigned Reg);
608 
609  /// createVirtualRegister - Create and return a new virtual register in the
610  /// function with the specified register class.
611  ///
612  unsigned createVirtualRegister(const TargetRegisterClass *RegClass);
613 
614  /// getNumVirtRegs - Return the number of virtual registers created.
615  ///
616  unsigned getNumVirtRegs() const { return VRegInfo.size(); }
617 
618  /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
619  void clearVirtRegs();
620 
621  /// setRegAllocationHint - Specify a register allocation hint for the
622  /// specified virtual register.
623  void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg) {
625  RegAllocHints[VReg].first = Type;
626  RegAllocHints[VReg].second = PrefReg;
627  }
628 
629  /// getRegAllocationHint - Return the register allocation hint for the
630  /// specified virtual register.
631  std::pair<unsigned, unsigned>
632  getRegAllocationHint(unsigned VReg) const {
634  return RegAllocHints[VReg];
635  }
636 
637  /// getSimpleHint - Return the preferred register allocation hint, or 0 if a
638  /// standard simple hint (Type == 0) is not set.
639  unsigned getSimpleHint(unsigned VReg) const {
641  std::pair<unsigned, unsigned> Hint = getRegAllocationHint(VReg);
642  return Hint.first ? 0 : Hint.second;
643  }
644 
645  /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
646  /// specified register as undefined which causes the DBG_VALUE to be
647  /// deleted during LiveDebugVariables analysis.
648  void markUsesInDebugValueAsUndef(unsigned Reg) const;
649 
650  /// Return true if the specified register is modified in this function.
651  /// This checks that no defining machine operands exist for the register or
652  /// any of its aliases. Definitions found on functions marked noreturn are
653  /// ignored.
654  bool isPhysRegModified(unsigned PhysReg) const;
655 
656  //===--------------------------------------------------------------------===//
657  // Physical Register Use Info
658  //===--------------------------------------------------------------------===//
659 
660  /// isPhysRegUsed - Return true if the specified register is used in this
661  /// function. Also check for clobbered aliases and registers clobbered by
662  /// function calls with register mask operands.
663  ///
664  /// This only works after register allocation.
665  bool isPhysRegUsed(unsigned Reg) const {
666  if (UsedPhysRegMask.test(Reg))
667  return true;
668  for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
669  Units.isValid(); ++Units)
670  if (UsedRegUnits.test(*Units))
671  return true;
672  return false;
673  }
674 
675  /// Mark the specified register unit as used in this function.
676  /// This should only be called during and after register allocation.
677  void setRegUnitUsed(unsigned RegUnit) {
678  UsedRegUnits.set(RegUnit);
679  }
680 
681  /// setPhysRegUsed - Mark the specified register used in this function.
682  /// This should only be called during and after register allocation.
683  void setPhysRegUsed(unsigned Reg) {
684  for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
685  Units.isValid(); ++Units)
686  UsedRegUnits.set(*Units);
687  }
688 
689  /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
690  /// This corresponds to the bit mask attached to register mask operands.
691  void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) {
692  UsedPhysRegMask.setBitsNotInMask(RegMask);
693  }
694 
695  /// setPhysRegUnused - Mark the specified register unused in this function.
696  /// This should only be called during and after register allocation.
697  void setPhysRegUnused(unsigned Reg) {
698  UsedPhysRegMask.reset(Reg);
699  for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
700  Units.isValid(); ++Units)
701  UsedRegUnits.reset(*Units);
702  }
703 
704 
705  //===--------------------------------------------------------------------===//
706  // Reserved Register Info
707  //===--------------------------------------------------------------------===//
708  //
709  // The set of reserved registers must be invariant during register
710  // allocation. For example, the target cannot suddenly decide it needs a
711  // frame pointer when the register allocator has already used the frame
712  // pointer register for something else.
713  //
714  // These methods can be used by target hooks like hasFP() to avoid changing
715  // the reserved register set during register allocation.
716 
717  /// freezeReservedRegs - Called by the register allocator to freeze the set
718  /// of reserved registers before allocation begins.
719  void freezeReservedRegs(const MachineFunction&);
720 
721  /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called
722  /// to ensure the set of reserved registers stays constant.
723  bool reservedRegsFrozen() const {
724  return !ReservedRegs.empty();
725  }
726 
727  /// canReserveReg - Returns true if PhysReg can be used as a reserved
728  /// register. Any register can be reserved before freezeReservedRegs() is
729  /// called.
730  bool canReserveReg(unsigned PhysReg) const {
731  return !reservedRegsFrozen() || ReservedRegs.test(PhysReg);
732  }
733 
734  /// getReservedRegs - Returns a reference to the frozen set of reserved
735  /// registers. This method should always be preferred to calling
736  /// TRI::getReservedRegs() when possible.
737  const BitVector &getReservedRegs() const {
738  assert(reservedRegsFrozen() &&
739  "Reserved registers haven't been frozen yet. "
740  "Use TRI::getReservedRegs().");
741  return ReservedRegs;
742  }
743 
744  /// isReserved - Returns true when PhysReg is a reserved register.
745  ///
746  /// Reserved registers may belong to an allocatable register class, but the
747  /// target has explicitly requested that they are not used.
748  ///
749  bool isReserved(unsigned PhysReg) const {
750  return getReservedRegs().test(PhysReg);
751  }
752 
753  /// isAllocatable - Returns true when PhysReg belongs to an allocatable
754  /// register class and it hasn't been reserved.
755  ///
756  /// Allocatable registers may show up in the allocation order of some virtual
757  /// register, so a register allocator needs to track its liveness and
758  /// availability.
759  bool isAllocatable(unsigned PhysReg) const {
760  return getTargetRegisterInfo()->isInAllocatableClass(PhysReg) &&
761  !isReserved(PhysReg);
762  }
763 
764  //===--------------------------------------------------------------------===//
765  // LiveIn Management
766  //===--------------------------------------------------------------------===//
767 
768  /// addLiveIn - Add the specified register as a live-in. Note that it
769  /// is an error to add the same register to the same set more than once.
770  void addLiveIn(unsigned Reg, unsigned vreg = 0) {
771  LiveIns.push_back(std::make_pair(Reg, vreg));
772  }
773 
774  // Iteration support for the live-ins set. It's kept in sorted order
775  // by register number.
776  typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator
778  livein_iterator livein_begin() const { return LiveIns.begin(); }
779  livein_iterator livein_end() const { return LiveIns.end(); }
780  bool livein_empty() const { return LiveIns.empty(); }
781 
782  bool isLiveIn(unsigned Reg) const;
783 
784  /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
785  /// corresponding live-in physical register.
786  unsigned getLiveInPhysReg(unsigned VReg) const;
787 
788  /// getLiveInVirtReg - If PReg is a live-in physical register, return the
789  /// corresponding live-in physical register.
790  unsigned getLiveInVirtReg(unsigned PReg) const;
791 
792  /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
793  /// into the given entry block.
794  void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
795  const TargetRegisterInfo &TRI,
796  const TargetInstrInfo &TII);
797 
798  /// Returns a mask covering all bits that can appear in lane masks of
799  /// subregisters of the virtual register @p Reg.
800  unsigned getMaxLaneMaskForVReg(unsigned Reg) const;
801 
802  /// defusechain_iterator - This class provides iterator support for machine
803  /// operands in the function that use or define a specific register. If
804  /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
805  /// returns defs. If neither are true then you are silly and it always
806  /// returns end(). If SkipDebug is true it skips uses marked Debug
807  /// when incrementing.
808  template<bool ReturnUses, bool ReturnDefs, bool SkipDebug,
809  bool ByOperand, bool ByInstr, bool ByBundle>
811  : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
812  MachineOperand *Op;
813  explicit defusechain_iterator(MachineOperand *op) : Op(op) {
814  // If the first node isn't one we're interested in, advance to one that
815  // we are interested in.
816  if (op) {
817  if ((!ReturnUses && op->isUse()) ||
818  (!ReturnDefs && op->isDef()) ||
819  (SkipDebug && op->isDebug()))
820  advance();
821  }
822  }
823  friend class MachineRegisterInfo;
824 
825  void advance() {
826  assert(Op && "Cannot increment end iterator!");
827  Op = getNextOperandForReg(Op);
828 
829  // All defs come before the uses, so stop def_iterator early.
830  if (!ReturnUses) {
831  if (Op) {
832  if (Op->isUse())
833  Op = nullptr;
834  else
835  assert(!Op->isDebug() && "Can't have debug defs");
836  }
837  } else {
838  // If this is an operand we don't care about, skip it.
839  while (Op && ((!ReturnDefs && Op->isDef()) ||
840  (SkipDebug && Op->isDebug())))
841  Op = getNextOperandForReg(Op);
842  }
843  }
844  public:
845  typedef std::iterator<std::forward_iterator_tag,
847  typedef std::iterator<std::forward_iterator_tag,
849 
850  defusechain_iterator() : Op(nullptr) {}
851 
852  bool operator==(const defusechain_iterator &x) const {
853  return Op == x.Op;
854  }
855  bool operator!=(const defusechain_iterator &x) const {
856  return !operator==(x);
857  }
858 
859  /// atEnd - return true if this iterator is equal to reg_end() on the value.
860  bool atEnd() const { return Op == nullptr; }
861 
862  // Iterator traversal: forward iteration only
863  defusechain_iterator &operator++() { // Preincrement
864  assert(Op && "Cannot increment end iterator!");
865  if (ByOperand)
866  advance();
867  else if (ByInstr) {
868  MachineInstr *P = Op->getParent();
869  do {
870  advance();
871  } while (Op && Op->getParent() == P);
872  } else if (ByBundle) {
874  do {
875  advance();
876  } while (Op && getBundleStart(Op->getParent()) == P);
877  }
878 
879  return *this;
880  }
881  defusechain_iterator operator++(int) { // Postincrement
882  defusechain_iterator tmp = *this; ++*this; return tmp;
883  }
884 
885  /// getOperandNo - Return the operand # of this MachineOperand in its
886  /// MachineInstr.
887  unsigned getOperandNo() const {
888  assert(Op && "Cannot dereference end iterator!");
889  return Op - &Op->getParent()->getOperand(0);
890  }
891 
892  // Retrieve a reference to the current operand.
894  assert(Op && "Cannot dereference end iterator!");
895  return *Op;
896  }
897 
899  assert(Op && "Cannot dereference end iterator!");
900  return Op;
901  }
902  };
903 
904  /// defusechain_iterator - This class provides iterator support for machine
905  /// operands in the function that use or define a specific register. If
906  /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
907  /// returns defs. If neither are true then you are silly and it always
908  /// returns end(). If SkipDebug is true it skips uses marked Debug
909  /// when incrementing.
910  template<bool ReturnUses, bool ReturnDefs, bool SkipDebug,
911  bool ByOperand, bool ByInstr, bool ByBundle>
913  : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
914  MachineOperand *Op;
915  explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
916  // If the first node isn't one we're interested in, advance to one that
917  // we are interested in.
918  if (op) {
919  if ((!ReturnUses && op->isUse()) ||
920  (!ReturnDefs && op->isDef()) ||
921  (SkipDebug && op->isDebug()))
922  advance();
923  }
924  }
925  friend class MachineRegisterInfo;
926 
927  void advance() {
928  assert(Op && "Cannot increment end iterator!");
929  Op = getNextOperandForReg(Op);
930 
931  // All defs come before the uses, so stop def_iterator early.
932  if (!ReturnUses) {
933  if (Op) {
934  if (Op->isUse())
935  Op = nullptr;
936  else
937  assert(!Op->isDebug() && "Can't have debug defs");
938  }
939  } else {
940  // If this is an operand we don't care about, skip it.
941  while (Op && ((!ReturnDefs && Op->isDef()) ||
942  (SkipDebug && Op->isDebug())))
943  Op = getNextOperandForReg(Op);
944  }
945  }
946  public:
947  typedef std::iterator<std::forward_iterator_tag,
949  typedef std::iterator<std::forward_iterator_tag,
951 
952  defusechain_instr_iterator() : Op(nullptr) {}
953 
954  bool operator==(const defusechain_instr_iterator &x) const {
955  return Op == x.Op;
956  }
957  bool operator!=(const defusechain_instr_iterator &x) const {
958  return !operator==(x);
959  }
960 
961  /// atEnd - return true if this iterator is equal to reg_end() on the value.
962  bool atEnd() const { return Op == nullptr; }
963 
964  // Iterator traversal: forward iteration only
966  assert(Op && "Cannot increment end iterator!");
967  if (ByOperand)
968  advance();
969  else if (ByInstr) {
970  MachineInstr *P = Op->getParent();
971  do {
972  advance();
973  } while (Op && Op->getParent() == P);
974  } else if (ByBundle) {
976  do {
977  advance();
978  } while (Op && getBundleStart(Op->getParent()) == P);
979  }
980 
981  return *this;
982  }
983  defusechain_instr_iterator operator++(int) { // Postincrement
984  defusechain_instr_iterator tmp = *this; ++*this; return tmp;
985  }
986 
987  // Retrieve a reference to the current operand.
989  assert(Op && "Cannot dereference end iterator!");
990  if (ByBundle) return *(getBundleStart(Op->getParent()));
991  return *Op->getParent();
992  }
993 
995  assert(Op && "Cannot dereference end iterator!");
996  if (ByBundle) return getBundleStart(Op->getParent());
997  return Op->getParent();
998  }
999  };
1000 };
1001 
1002 /// Iterate over the pressure sets affected by the given physical or virtual
1003 /// register. If Reg is physical, it must be a register unit (from
1004 /// MCRegUnitIterator).
1006  const int *PSet;
1007  unsigned Weight;
1008 public:
1009  PSetIterator(): PSet(nullptr), Weight(0) {}
1010  PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI) {
1011  const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
1013  const TargetRegisterClass *RC = MRI->getRegClass(RegUnit);
1014  PSet = TRI->getRegClassPressureSets(RC);
1015  Weight = TRI->getRegClassWeight(RC).RegWeight;
1016  }
1017  else {
1018  PSet = TRI->getRegUnitPressureSets(RegUnit);
1019  Weight = TRI->getRegUnitWeight(RegUnit);
1020  }
1021  if (*PSet == -1)
1022  PSet = nullptr;
1023  }
1024  bool isValid() const { return PSet; }
1025 
1026  unsigned getWeight() const { return Weight; }
1027 
1028  unsigned operator*() const { return *PSet; }
1029 
1030  void operator++() {
1031  assert(isValid() && "Invalid PSetIterator.");
1032  ++PSet;
1033  if (*PSet == -1)
1034  PSet = nullptr;
1035  }
1036 };
1037 
1038 inline PSetIterator MachineRegisterInfo::
1039 getPressureSets(unsigned RegUnit) const {
1040  return PSetIterator(RegUnit, this);
1041 }
1042 
1043 } // End llvm namespace
1044 
1045 #endif
bool isConstantPhysReg(unsigned PhysReg, const MachineFunction &MF) const
isConstantPhysReg - Returns true if PhysReg is unallocatable and constant throughout the function...
iterator_range< reg_bundle_iterator > reg_bundles(unsigned Reg) const
defusechain_instr_iterator< true, false, false, false, true, false > use_instr_iterator
use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the specified register...
defusechain_instr_iterator< true, false, true, false, true, false > use_instr_nodbg_iterator
use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk all uses of the specified r...
BitVector & set()
Definition: BitVector.h:218
void setPhysRegUsed(unsigned Reg)
setPhysRegUsed - Mark the specified register used in this function.
void EmitLiveInCopies(MachineBasicBlock *EntryMBB, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII)
EmitLiveInCopies - Emit copies to initialize livein virtual registers into the given entry block...
std::iterator< std::forward_iterator_tag, MachineInstr, ptrdiff_t >::reference reference
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
reg_bundle_iterator reg_bundle_begin(unsigned RegNo) const
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
livein_iterator livein_end() const
bool atEnd() const
atEnd - return true if this iterator is equal to reg_end() on the value.
bool isPhysRegModified(unsigned PhysReg) const
Return true if the specified register is modified in this function.
unsigned getSimpleHint(unsigned VReg) const
getSimpleHint - Return the preferred register allocation hint, or 0 if a standard simple hint (Type =...
use_instr_nodbg_iterator use_instr_nodbg_begin(unsigned RegNo) const
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
iterator_range< use_iterator > use_operands(unsigned Reg) const
This provides a very simple, boring adaptor for a begin and end iterator into a range type...
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
iterator_range< reg_iterator > reg_operands(unsigned Reg) const
iterator_range< reg_bundle_nodbg_iterator > reg_nodbg_bundles(unsigned Reg) const
bool use_nodbg_empty(unsigned RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register...
void setBitsNotInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsNotInMask - Add a bit to this vector for every '0' bit in Mask.
Definition: BitVector.h:493
bool shouldTrackSubRegLiveness(unsigned VReg) const
defusechain_instr_iterator< true, true, false, false, false, true > reg_bundle_iterator
reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses of the specified registe...
virtual const int * getRegClassPressureSets(const TargetRegisterClass *RC) const =0
Get the dimensions of register pressure impacted by this register class.
#define op(i)
void markUsesInDebugValueAsUndef(unsigned Reg) const
markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the specified register as undefined wh...
static use_nodbg_iterator use_nodbg_end()
aarch64 collect AArch64 Collect Linker Optimization Hint(LOH)"
bool canReserveReg(unsigned PhysReg) const
canReserveReg - Returns true if PhysReg can be used as a reserved register.
void clearVirtRegs()
clearVirtRegs - Remove all virtual registers (after physreg assignment).
virtual unsigned getRegUnitWeight(unsigned RegUnit) const =0
Get the weight in units of pressure for this register unit.
const BitVector & getReservedRegs() const
getReservedRegs - Returns a reference to the frozen set of reserved registers.
unsigned getMaxLaneMaskForVReg(unsigned Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
static use_iterator use_end()
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const HexagonInstrInfo * TII
const TargetRegisterInfo * getTargetRegisterInfo() const
use_instr_iterator use_instr_begin(unsigned RegNo) const
iterator_range< use_bundle_iterator > use_bundles(unsigned Reg) const
static void advance(T &it, size_t Val)
const TargetRegisterClass * getRegClass(unsigned Reg) const
getRegClass - Return the register class of the specified virtual register.
void freezeReservedRegs(const MachineFunction &)
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
Reg
All possible values of the reg field in the ModR/M byte.
defusechain_iterator< true, true, false, true, false, false > reg_iterator
reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified register.
iterator_range< reg_instr_nodbg_iterator > reg_nodbg_instructions(unsigned Reg) const
def_bundle_iterator def_bundle_begin(unsigned RegNo) const
defusechain_instr_iterator< true, false, true, false, false, true > use_bundle_nodbg_iterator
use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk all uses of the specifie...
static reg_instr_iterator reg_instr_end()
defusechain_iterator - This class provides iterator support for machine operands in the function that...
reg_instr_nodbg_iterator reg_instr_nodbg_begin(unsigned RegNo) const
bool isLiveIn(unsigned Reg) const
static def_instr_iterator def_instr_end()
defusechain_instr_iterator< false, true, false, false, true, false > def_instr_iterator
def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the specified register...
PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI)
defusechain_instr_iterator< false, true, false, false, false, true > def_bundle_iterator
def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the specified register...
bool atEnd() const
atEnd - return true if this iterator is equal to reg_end() on the value.
defusechain_instr_iterator< true, true, true, false, false, true > reg_bundle_nodbg_iterator
reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk all defs and uses of the...
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
bool isInAllocatableClass(unsigned RegNo) const
isInAllocatableClass - Return true if the register is in the allocation of any register class...
defusechain_instr_iterator< true, false, false, false, false, true > use_bundle_iterator
use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the specified register...
TargetInstrInfo - Interface to description of machine instruction set.
iterator_range< def_iterator > def_operands(unsigned Reg) const
bool reservedRegsFrozen() const
reservedRegsFrozen - Returns true after freezeReservedRegs() was called to ensure the set of reserved...
std::iterator< std::forward_iterator_tag, MachineInstr, ptrdiff_t >::pointer pointer
#define P(N)
iterator_range< reg_instr_iterator > reg_instructions(unsigned Reg) const
bool operator!=(const defusechain_iterator &x) const
iterator_range< use_nodbg_iterator > use_nodbg_operands(unsigned Reg) const
use_bundle_iterator use_bundle_begin(unsigned RegNo) const
std::iterator< std::forward_iterator_tag, MachineInstr, ptrdiff_t >::reference reference
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
defusechain_iterator< false, true, false, true, false, false > def_iterator
def_iterator/def_begin/def_end - Walk all defs of the specified register.
std::iterator< std::forward_iterator_tag, MachineInstr, ptrdiff_t >::pointer pointer
bool isReserved(unsigned PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
bool empty() const
empty - Tests whether there are no bits in this bitvector.
Definition: BitVector.h:115
unsigned getLiveInVirtReg(unsigned PReg) const
getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in physical ...
unsigned getOperandNo() const
getOperandNo - Return the operand # of this MachineOperand in its MachineInstr.
iterator_range< use_bundle_nodbg_iterator > use_nodbg_bundles(unsigned Reg) const
iterator_range< def_bundle_iterator > def_bundles(unsigned Reg) const
bool tracksLiveness() const
tracksLiveness - Returns true when tracking register liveness accurately.
BitVector & reset()
Definition: BitVector.h:259
reg_instr_iterator reg_instr_begin(unsigned RegNo) const
defusechain_iterator< true, true, true, true, false, false > reg_nodbg_iterator
reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses of the specified register...
use_bundle_nodbg_iterator use_bundle_nodbg_begin(unsigned RegNo) const
reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(unsigned RegNo) const
iterator_range< use_instr_iterator > use_instructions(unsigned Reg) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const bool HasDisjunctSubRegs
Whether the class supports two (or more) disjunct subregister indices.
static use_bundle_nodbg_iterator use_bundle_nodbg_end()
defusechain_instr_iterator< true, true, true, false, true, false > reg_instr_nodbg_iterator
reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk all defs and uses of the sp...
MachineOperand class - Representation of each machine instruction operand.
virtual const RegClassWeight & getRegClassWeight(const TargetRegisterClass *RC) const =0
Get the weight in units of pressure for this register class.
void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg)
setRegAllocationHint - Specify a register allocation hint for the specified virtual register...
void setPhysRegUnused(unsigned Reg)
setPhysRegUnused - Mark the specified register unused in this function.
bool test(unsigned Idx) const
Definition: BitVector.h:322
static reg_bundle_iterator reg_bundle_end()
bool hasOneUse(unsigned RegNo) const
hasOneUse - Return true if there is exactly one instruction using the specified register.
unsigned getWeight() const
bool isAllocatable(unsigned PhysReg) const
isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn't been...
livein_iterator livein_begin() const
void invalidateLiveness()
invalidateLiveness - Indicates that register liveness is no longer being tracked accurately.
bool recomputeRegClass(unsigned Reg)
recomputeRegClass - Try to find a legal super-class of Reg's register class that still satisfies the ...
void resetDelegate(Delegate *delegate)
static reg_bundle_nodbg_iterator reg_bundle_nodbg_end()
A range adaptor for a pair of iterators.
defusechain_iterator< true, false, false, true, false, false > use_iterator
use_iterator/use_begin/use_end - Walk all uses of the specified register.
unsigned operator*() const
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
void replaceRegWith(unsigned FromReg, unsigned ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
MachineInstr * getBundleStart(MachineInstr *MI)
getBundleStart - Returns the first instruction in the bundle containing MI.
def_iterator def_begin(unsigned RegNo) const
bool operator==(const defusechain_instr_iterator &x) const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
void verifyUseList(unsigned Reg) const
Verify the sanity of the use list for Reg.
Representation of each machine instruction.
Definition: MachineInstr.h:51
bool hasOneDef(unsigned RegNo) const
hasOneDef - Return true if there is exactly one instruction defining the specified register...
defusechain_instr_iterator< true, true, false, false, true, false > reg_instr_iterator
reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses of the specified register...
static reg_instr_nodbg_iterator reg_instr_nodbg_end()
static use_bundle_iterator use_bundle_end()
def_instr_iterator def_instr_begin(unsigned RegNo) const
iterator_range< use_instr_nodbg_iterator > use_nodbg_instructions(unsigned Reg) const
Iterate over the pressure sets affected by the given physical or virtual register.
use_iterator use_begin(unsigned RegNo) const
bool operator==(const defusechain_iterator &x) const
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
PSetIterator getPressureSets(unsigned RegUnit) const
Get an iterator over the pressure sets affected by the given physical or virtual register.
void setRegUnitUsed(unsigned RegUnit)
Mark the specified register unit as used in this function.
virtual const int * getRegUnitPressureSets(unsigned RegUnit) const =0
Get the dimensions of register pressure impacted by this register unit.
void addPhysRegsUsedFromRegMask(const uint32_t *RegMask)
addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
void clearKillFlags(unsigned Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
void enableSubRegLiveness(bool Enable=true)
bool reg_empty(unsigned RegNo) const
reg_empty - Return true if there are no instructions using or defining the specified register (it may...
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
static reg_nodbg_iterator reg_nodbg_end()
std::vector< std::pair< unsigned, unsigned > >::const_iterator livein_iterator
iterator_range< reg_nodbg_iterator > reg_nodbg_operands(unsigned Reg) const
static use_instr_nodbg_iterator use_instr_nodbg_end()
void dumpUses(unsigned RegNo) const
static def_iterator def_end()
iterator_range< def_instr_iterator > def_instructions(unsigned Reg) const
void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps)
Move NumOps operands from Src to Dst, updating use-def lists as needed.
static use_instr_iterator use_instr_end()
bool isDebug() const
bool def_empty(unsigned RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
bool isPhysRegUsed(unsigned Reg) const
isPhysRegUsed - Return true if the specified register is used in this function.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
void setRegClass(unsigned Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
void setDelegate(Delegate *delegate)
reg_iterator reg_begin(unsigned RegNo) const
virtual void MRI_NoteNewVirtualRegister(unsigned Reg)=0
defusechain_iterator< true, false, true, true, false, false > use_nodbg_iterator
use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the specified register...
std::pair< unsigned, unsigned > getRegAllocationHint(unsigned VReg) const
getRegAllocationHint - Return the register allocation hint for the specified virtual register...
void verifyUseLists() const
Verify the use list of all registers.
reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const
static reg_iterator reg_end()
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
bool operator!=(const defusechain_instr_iterator &x) const
bool reg_nodbg_empty(unsigned RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions...
use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const
static def_bundle_iterator def_bundle_end()
bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const
Returns true if liveness for register class RC should be tracked at the subregister level...
unsigned getLiveInPhysReg(unsigned VReg) const
getLiveInPhysReg - If VReg is a live-in virtual register, return the corresponding live-in physical r...
bool use_empty(unsigned RegNo) const
use_empty - Return true if there are no instructions using the specified register.
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.