17 #ifndef LLVM_CODEGEN_LIVEINTERVALUNION_H
18 #define LLVM_CODEGEN_LIVEINTERVALUNION_H
25 class TargetRegisterInfo;
89 unify(VirtReg, VirtReg);
117 bool CheckedFirstInterference;
118 bool SeenAllInterferences;
119 bool SeenUnspillableVReg;
120 unsigned Tag, UserTag;
123 Query(): LiveUnion(), VirtReg(), Tag(0), UserTag(0) {}
126 LiveUnion(LIU), VirtReg(VReg), CheckedFirstInterference(
false),
127 SeenAllInterferences(
false), SeenUnspillableVReg(
false)
133 InterferingVRegs.clear();
134 CheckedFirstInterference =
false;
135 SeenAllInterferences =
false;
136 SeenUnspillableVReg =
false;
142 assert(VReg && LIU &&
"Invalid arguments");
143 if (UserTag == UTag && VirtReg == VReg &&
156 assert(VirtReg &&
"uninitialized");
178 return InterferingVRegs;
183 void operator=(
const Query&) =
delete;
198 unsigned size()
const {
return Size; }
203 assert(idx < Size &&
"idx out of bounds");
208 assert(Idx < Size &&
"Idx out of bounds");
216 #endif // !defined(LLVM_CODEGEN_LIVEINTERVALUNION_H)
bool seenAllInterferences() const
const_iterator begin() const
Segments::iterator iterator
LiveIntervalUnion(Allocator &a)
LiveInterval - This class represents the liveness of a register, or stack slot.
const_iterator find(KeyT x) const
find - Return an iterator pointing to the first interval ending at or after x, or end()...
KeyT stop() const
stop - Return the largest mapped key in a non-empty map.
const LiveIntervalUnion & operator[](unsigned Idx) const
This represents a simple continuous liveness interval for a value.
const_iterator end() const
Query(LiveInterval *VReg, LiveIntervalUnion *LIU)
void init(unsigned UTag, LiveInterval *VReg, LiveIntervalUnion *LIU)
This class represents the liveness of a register, stack slot, etc.
Query interferences between a single live virtual register and a live interval union.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
RecyclingAllocator - This class wraps an Allocator, adding the functionality of recycling deleted obj...
void unify(LiveInterval &VirtReg)
bool empty() const
empty - Return true when no intervals are mapped.
const SmallVectorImpl< LiveInterval * > & interferingVRegs() const
void clear()
clear - Remove all entries.
LiveSegments::Allocator Allocator
SegmentIter find(SlotIndex x)
unsigned getTag() const
getTag - Return an opaque tag representing the current state of the union.
Union of live intervals that are strong candidates for coalescing into a single register (either phys...
void print(raw_ostream &OS, const TargetRegisterInfo *TRI) const
bool overlap(const LiveInterval::Segment &VRSeg, const IntervalMap< SlotIndex, LiveInterval * >::const_iterator &LUSeg)
Compare a live virtual register segment to a LiveIntervalUnion segment.
bool isSeenInterference(LiveInterval *VReg) const
NDEBUG.
LiveIntervalUnion & operator[](unsigned idx)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void unify(LiveInterval &VirtReg, const LiveRange &Range)
KeyT start() const
start - Return the smallest mapped key in a non-empty map.
bool changedSince(unsigned tag) const
changedSince - Return true if the union change since getTag returned tag.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
void init(LiveIntervalUnion::Allocator &, unsigned Size)
bool seenUnspillableVReg() const
LiveSegments::iterator SegmentIter
void verify(LiveVirtRegBitSet &VisitedVRegs)
unsigned collectInterferingVRegs(unsigned MaxInterferingRegs=UINT_MAX)
void extract(LiveInterval &VirtReg)
void extract(LiveInterval &VirtReg, const LiveRange &Range)
SlotIndex startIndex() const
This class implements an extremely fast bulk output stream that can only output to a stream...
LiveInterval & virtReg() const
SlotIndex - An opaque wrapper around machine indexes.
SparseBitVector< 128 > LiveVirtRegBitSet