85 std::pair<SDValue, SDValue>
88 const SDValue *Ops,
unsigned NumOps,
89 bool isSigned,
SDLoc dl,
91 bool isReturnValueUsed)
const {
96 for (
unsigned i = 0; i != NumOps; ++i) {
101 Args.push_back(Entry);
126 &&
"Unsupported setcc type!");
204 SDValue Ops[2] = { NewLHS, NewRHS };
205 NewLHS =
makeLibCall(DAG, LC1, RetVT, Ops, 2,
false,
214 NewLHS =
makeLibCall(DAG, LC2, RetVT, Ops, 2,
false,
287 const APInt &Demanded) {
297 if (!C)
return false;
307 DAG.getConstant(Demanded &
310 return CombineTo(Op, New);
327 const APInt &Demanded,
330 "ShrinkDemandedOp only supports binary operators!");
332 "ShrinkDemandedOp only supports nodes with one result!");
347 unsigned SmallVTBits = DemandedSize;
350 for (; SmallVTBits < BitWidth; SmallVTBits =
NextPowerOf2(SmallVTBits)) {
360 bool NeedZext = DemandedSize > SmallVTBits;
363 return CombineTo(Op, Z);
377 const APInt &DemandedMask,
381 unsigned Depth)
const {
384 "Mask size mismatches value type size!");
385 APInt NewMask = DemandedMask;
390 KnownZero = KnownOne =
APInt(BitWidth, 0);
403 }
else if (DemandedMask == 0) {
408 }
else if (Depth == 6) {
412 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
416 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue();
417 KnownZero = ~KnownOne;
425 APInt LHSZero, LHSOne;
429 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
438 KnownOne, TLO, Depth+1))
440 assert((KnownZero & KnownOne) == 0 &&
"Bits known to be one AND zero?");
442 KnownZero2, KnownOne2, TLO, Depth+1))
444 assert((KnownZero2 & KnownOne2) == 0 &&
"Bits known to be one AND zero?");
448 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
450 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
453 if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
454 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, dl, Op.
getValueType()));
456 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
459 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
463 KnownOne &= KnownOne2;
465 KnownZero |= KnownZero2;
469 KnownOne, TLO, Depth+1))
471 assert((KnownZero & KnownOne) == 0 &&
"Bits known to be one AND zero?");
473 KnownZero2, KnownOne2, TLO, Depth+1))
475 assert((KnownZero2 & KnownOne2) == 0 &&
"Bits known to be one AND zero?");
479 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
481 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
485 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
487 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
490 if (TLO.ShrinkDemandedConstant(Op, NewMask))
493 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
497 KnownZero &= KnownZero2;
499 KnownOne |= KnownOne2;
503 KnownOne, TLO, Depth+1))
505 assert((KnownZero & KnownOne) == 0 &&
"Bits known to be one AND zero?");
507 KnownOne2, TLO, Depth+1))
509 assert((KnownZero2 & KnownOne2) == 0 &&
"Bits known to be one AND zero?");
513 if ((KnownZero & NewMask) == NewMask)
515 if ((KnownZero2 & NewMask) == NewMask)
518 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
524 if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
530 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
532 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
539 if ((NewMask & (KnownZero|KnownOne)) == NewMask) {
540 if (KnownOne == KnownOne2) {
542 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, dl, VT);
552 APInt Expanded =
C->getAPIntValue() | (~NewMask);
555 if (Expanded !=
C->getAPIntValue()) {
558 TLO.DAG.getConstant(Expanded, dl, VT));
559 return TLO.CombineTo(Op, New);
563 }
else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
568 KnownZero = KnownZeroOut;
569 KnownOne = KnownOneOut;
573 KnownOne, TLO, Depth+1))
576 KnownOne2, TLO, Depth+1))
578 assert((KnownZero & KnownOne) == 0 &&
"Bits known to be one AND zero?");
579 assert((KnownZero2 & KnownOne2) == 0 &&
"Bits known to be one AND zero?");
582 if (TLO.ShrinkDemandedConstant(Op, NewMask))
586 KnownOne &= KnownOne2;
587 KnownZero &= KnownZero2;
591 KnownOne, TLO, Depth+1))
594 KnownOne2, TLO, Depth+1))
596 assert((KnownZero & KnownOne) == 0 &&
"Bits known to be one AND zero?");
597 assert((KnownZero2 & KnownOne2) == 0 &&
"Bits known to be one AND zero?");
600 if (TLO.ShrinkDemandedConstant(Op, NewMask))
604 KnownOne &= KnownOne2;
605 KnownZero &= KnownZero2;
609 unsigned ShAmt = SA->getZExtValue();
613 if (ShAmt >= BitWidth)
622 unsigned C1= cast<ConstantSDNode>(InOp.
getOperand(1))->getZExtValue();
633 return TLO.CombineTo(Op, TLO.DAG.
getNode(Opc, dl, VT,
639 KnownZero, KnownOne, TLO, Depth+1))
648 if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 &&
655 TLO.DAG.getConstant(ShAmt, dl, ShTy));
670 uint64_t InnerShAmt = cast<ConstantSDNode>(InnerOp.
getOperand(1))
672 if (InnerShAmt < ShAmt &&
673 InnerShAmt < InnerBits &&
674 NewMask.lshr(InnerBits - InnerShAmt + ShAmt) == 0 &&
675 NewMask.trunc(ShAmt) == 0) {
677 TLO.DAG.getConstant(ShAmt - InnerShAmt, dl,
688 KnownZero <<= SA->getZExtValue();
689 KnownOne <<= SA->getZExtValue();
697 unsigned ShAmt = SA->getZExtValue();
702 if (ShAmt >= BitWidth)
705 APInt InDemandedMask = (NewMask << ShAmt);
709 if (cast<BinaryWithFlagsSDNode>(Op)->Flags.hasExact())
718 unsigned C1= cast<ConstantSDNode>(InOp.
getOperand(1))->getZExtValue();
728 return TLO.CombineTo(Op, TLO.DAG.
getNode(Opc, dl, VT,
735 KnownZero, KnownOne, TLO, Depth+1))
737 assert((KnownZero & KnownOne) == 0 &&
"Bits known to be one AND zero?");
738 KnownZero = KnownZero.lshr(ShAmt);
739 KnownOne = KnownOne.lshr(ShAmt);
742 KnownZero |= HighBits;
751 return TLO.CombineTo(Op,
757 unsigned ShAmt = SA->getZExtValue();
760 if (ShAmt >= BitWidth)
763 APInt InDemandedMask = (NewMask << ShAmt);
767 if (cast<BinaryWithFlagsSDNode>(Op)->Flags.hasExact())
777 KnownZero, KnownOne, TLO, Depth+1))
779 assert((KnownZero & KnownOne) == 0 &&
"Bits known to be one AND zero?");
780 KnownZero = KnownZero.lshr(ShAmt);
781 KnownOne = KnownOne.lshr(ShAmt);
788 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
791 return TLO.CombineTo(Op,
796 int Log2 = NewMask.exactLogBase2();
800 TLO.DAG.getConstant(BitWidth - 1 - Log2, dl,
806 if (KnownOne.intersects(SignBit))
808 KnownOne |= HighBits;
816 if (MsbMask == NewMask) {
820 bool AlreadySignExtended =
821 TLO.DAG.ComputeNumSignBits(InOp) >= VTBits-ShAmt+1;
824 if (!AlreadySignExtended) {
828 if (TLO.LegalTypes() && !ShiftAmtTy.
isVector())
831 SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, dl,
846 if ((NewBits & NewMask) == 0)
851 APInt InputDemandedBits =
858 InputDemandedBits |= InSignBit;
861 KnownZero, KnownOne, TLO, Depth+1))
863 assert((KnownZero & KnownOne) == 0 &&
"Bits known to be one AND zero?");
869 if (KnownZero.intersects(InSignBit))
870 return TLO.CombineTo(Op,
871 TLO.DAG.getZeroExtendInReg(Op.
getOperand(0),dl,ExVT));
873 if (KnownOne.intersects(InSignBit)) {
875 KnownZero &= ~NewBits;
877 KnownZero &= ~NewBits;
878 KnownOne &= ~NewBits;
889 APInt KnownZeroLo, KnownOneLo;
890 APInt KnownZeroHi, KnownOneHi;
893 KnownOneLo, TLO, Depth + 1))
897 KnownOneHi, TLO, Depth + 1))
900 KnownZero = KnownZeroLo.
zext(BitWidth) |
901 KnownZeroHi.
zext(BitWidth).
shl(HalfBitWidth);
903 KnownOne = KnownOneLo.
zext(BitWidth) |
904 KnownOneHi.
zext(BitWidth).
shl(HalfBitWidth);
908 unsigned OperandBitWidth =
910 APInt InMask = NewMask.
trunc(OperandBitWidth);
921 KnownZero, KnownOne, TLO, Depth+1))
923 assert((KnownZero & KnownOne) == 0 &&
"Bits known to be one AND zero?");
924 KnownZero = KnownZero.zext(BitWidth);
925 KnownOne = KnownOne.zext(BitWidth);
926 KnownZero |= NewBits;
934 APInt NewBits = ~InMask & NewMask;
944 APInt InDemandedBits = InMask & NewMask;
945 InDemandedBits |= InSignBit;
946 InDemandedBits = InDemandedBits.
trunc(InBits);
949 KnownOne, TLO, Depth+1))
951 KnownZero = KnownZero.
zext(BitWidth);
952 KnownOne = KnownOne.
zext(BitWidth);
955 if (KnownZero.intersects(InSignBit))
961 if (KnownOne.intersects(InSignBit)) {
963 assert((KnownZero & NewBits) == 0);
965 assert((KnownOne & NewBits) == 0);
966 assert((KnownZero & NewBits) == 0);
971 unsigned OperandBitWidth =
973 APInt InMask = NewMask.
trunc(OperandBitWidth);
975 KnownZero, KnownOne, TLO, Depth+1))
977 assert((KnownZero & KnownOne) == 0 &&
"Bits known to be one AND zero?");
978 KnownZero = KnownZero.zext(BitWidth);
979 KnownOne = KnownOne.zext(BitWidth);
985 unsigned OperandBitWidth =
987 APInt TruncMask = NewMask.
zext(OperandBitWidth);
989 KnownZero, KnownOne, TLO, Depth+1))
991 KnownZero = KnownZero.
trunc(BitWidth);
992 KnownOne = KnownOne.
trunc(BitWidth);
1003 if (TLO.LegalTypes() &&
1012 if (TLO.LegalTypes()) {
1014 Shift = TLO.DAG.getConstant(ShVal, dl,
1019 OperandBitWidth - BitWidth);
1022 if (ShAmt->
getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1037 assert((KnownZero & KnownOne) == 0 &&
"Bits known to be one AND zero?");
1047 KnownZero, KnownOne, TLO, Depth+1))
1049 assert((KnownZero & KnownOne) == 0 &&
"Bits known to be one AND zero?");
1051 KnownZero |= ~InMask & NewMask;
1057 if (!TLO.LegalOperations() &&
1070 if (!OpVTLegal && OpVTSizeInBits > 32)
1086 BitWidth - NewMask.countLeadingZeros());
1088 KnownOne2, TLO, Depth+1))
1091 KnownOne2, TLO, Depth+1))
1094 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1100 TLO.DAG.computeKnownBits(Op, KnownZero, KnownOne, Depth);
1106 if ((NewMask & (KnownZero|KnownOne)) == NewMask) {
1130 unsigned Depth)
const {
1135 "Should use MaskedValueIsZero if you don't know whether Op"
1136 " is a target node!");
1145 unsigned Depth)
const {
1150 "Should use ComputeNumSignBits if you don't know whether Op"
1151 " is a target node!");
1165 if (
C->getAPIntValue() == 1)
1173 if (
C->getAPIntValue().isSignBit())
1182 APInt KnownZero, KnownOne;
1202 if (!CN || UndefElements.
none())
1232 if (!CN || UndefElements.
none())
1268 if (isa<ConstantSDNode>(N0.
getNode()) &&
1271 return DAG.
getSetCC(dl, VT, N1, N0, SwappedCC);
1274 const APInt &C1 = N1C->getAPIntValue();
1283 = cast<ConstantSDNode>(N0.
getOperand(1))->getAPIntValue();
1334 MinBits = N0->getOperand(0).getValueSizeInBits();
1336 }
else if (N0->getOpcode() ==
ISD::AND) {
1339 if ((
C->getAPIntValue()+1).isPowerOf2()) {
1340 MinBits =
C->getAPIntValue().countTrailingOnes();
1345 MinBits = N0->getOperand(0).getValueSizeInBits();
1348 }
else if (
LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) {
1351 MinBits = LN0->getMemoryVT().getSizeInBits();
1355 MinBits = LN0->getMemoryVT().getSizeInBits();
1361 unsigned ReqdBits = Signed ?
1362 C1.getBitWidth() - C1.getNumSignBits() + 1 :
1367 MinBits < C1.getBitWidth() &&
1368 MinBits >= ReqdBits) {
1374 return DAG.
getSetCC(dl, VT, Trunc, C, Cond);
1384 N0.getOpcode() ==
ISD::AND && C1 == 0 &&
1385 N0.getNode()->hasOneUse() &&
1386 isa<LoadSDNode>(N0.getOperand(0)) &&
1387 N0.getOperand(0).getNode()->hasOneUse() &&
1388 isa<ConstantSDNode>(N0.getOperand(1))) {
1389 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
1391 unsigned bestWidth = 0, bestOffset = 0;
1393 unsigned origWidth = N0.getValueType().getSizeInBits();
1394 unsigned maskWidth = origWidth;
1400 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1401 for (
unsigned width = origWidth / 2; width>=8; width /= 2) {
1403 for (
unsigned offset=0; offset<origWidth/width; offset++) {
1404 if ((newMask & Mask) == Mask) {
1406 bestOffset = (origWidth/width - offset - 1) * (width/8);
1408 bestOffset = (uint64_t)offset * (width/8);
1409 bestMask = Mask.lshr(offset * (width/8) * 8);
1413 newMask = newMask << width;
1422 if (bestOffset != 0)
1428 false,
false,
false, NewAlign);
1445 C1.getBitWidth() - InSize))) {
1460 return DAG.
getConstant(C1.isNonNegative(), dl, VT);
1474 EVT newVT = N0.getOperand(0).getValueType();
1493 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
1495 EVT ExtDstTy = N0.getValueType();
1500 if (C1.getMinSignedBits() > ExtSrcTyBits)
1504 EVT Op0Ty = N0.getOperand(0).getValueType();
1505 if (Op0Ty == ExtSrcTy) {
1515 return DAG.
getSetCC(dl, VT, ZextOp,
1521 }
else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
1526 bool TrueWhenTrue = (Cond ==
ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
1530 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->
get();
1532 N0.getOperand(0).getValueType().isInteger());
1535 return DAG.
getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
1540 N0.getOperand(0).getOpcode() ==
ISD::XOR &&
1541 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
1542 isa<ConstantSDNode>(N0.getOperand(1)) &&
1543 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
1555 assert(N0.getOpcode() ==
ISD::AND &&
1556 N0.getOperand(0).getOpcode() ==
ISD::XOR);
1559 N0.getOperand(0).getOperand(0),
1563 return DAG.
getSetCC(dl, VT, Val, N1,
1566 }
else if (N1C->getAPIntValue() == 1 &&
1584 cast<ConstantSDNode>(Op0.
getOperand(1))->getAPIntValue() == 1) {
1607 APInt MinVal, MaxVal;
1608 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
1619 if (C1 == MinVal)
return DAG.
getConstant(1, dl, VT);
1625 (!N1C->isOpaque() || (N1C->isOpaque() && C.
getBitWidth() <= 64 &&
1634 if (C1 == MaxVal)
return DAG.
getConstant(1, dl, VT);
1640 (!N1C->isOpaque() || (N1C->isOpaque() && C.
getBitWidth() <= 64 &&
1696 (VT == N0.getValueType() ||
1701 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1707 if (AndRHS->getAPIntValue().isPowerOf2()) {
1710 DAG.
getConstant(AndRHS->getAPIntValue().logBase2(), dl,
1713 }
else if (Cond ==
ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
1716 if (C1.isPowerOf2()) {
1726 if (C1.getMinSignedBits() <= 64 &&
1730 N0.getOpcode() ==
ISD::AND && N0.hasOneUse()) {
1732 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1733 const APInt &AndRHSC = AndRHS->getAPIntValue();
1734 if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) {
1740 EVT CmpTy = N0.getValueType();
1745 return DAG.
getSetCC(dl, VT, Shift, CmpRHS, Cond);
1759 ShiftBits = C1.countTrailingOnes();
1763 ShiftBits = C1.countTrailingZeros();
1765 NewC = NewC.
lshr(ShiftBits);
1772 EVT CmpTy = N0.getValueType();
1776 return DAG.
getSetCC(dl, VT, Shift, CmpRHS, NewCond);
1782 if (isa<ConstantFPSDNode>(N0.
getNode())) {
1789 if (CFP->getValueAPF().isNaN()) {
1807 return DAG.
getSetCC(dl, VT, N0, N0, Cond);
1815 if (CFP->getValueAPF().isInfinity()) {
1816 if (CFP->getValueAPF().isNegative()) {
1875 return DAG.
getSetCC(dl, VT, N0, N1, NewCond);
1901 bool LegalRHSImm =
false;
1909 LHSR->getAPIntValue(),
1921 RHSC->getAPIntValue(),
1932 RHSC->getAPIntValue(),
1939 if (RHSC->getValueType(0).getSizeInBits() <= 64)
2007 return DAG.
getSetCC(dl, VT, N0, Zero, Cond);
2018 return DAG.
getSetCC(dl, VT, N1, Zero, Cond);
2081 int64_t &Offset)
const {
2082 if (isa<GlobalAddressSDNode>(N)) {
2123 unsigned S = Constraint.
size();
2126 switch (Constraint[0]) {
2154 if (S > 1 && Constraint[0] ==
'{' && Constraint[S-1] ==
'}') {
2155 if (S == 8 && Constraint.
substr(1, 6) ==
"memory")
2176 std::string &Constraint,
2177 std::vector<SDValue> &Ops,
2180 if (Constraint.length() > 1)
return;
2182 char ConstraintLetter = Constraint[0];
2183 switch (ConstraintLetter) {
2209 C =
nullptr, GA =
nullptr;
2215 if (ConstraintLetter !=
'n') {
2216 int64_t Offs = GA->getOffset();
2219 C ?
SDLoc(C) : SDLoc(),
2226 if (ConstraintLetter !=
's') {
2240 std::pair<unsigned, const TargetRegisterClass *>
2244 if (Constraint.
empty() || Constraint[0] !=
'{')
2245 return std::make_pair(0u, static_cast<TargetRegisterClass*>(
nullptr));
2246 assert(*(Constraint.
end()-1) ==
'}' &&
"Not a brace enclosed constraint?");
2251 std::pair<unsigned, const TargetRegisterClass*> R =
2252 std::make_pair(0u, static_cast<const TargetRegisterClass*>(
nullptr));
2266 if (RegName.equals_lower(RI->
getName(*
I))) {
2267 std::pair<unsigned, const TargetRegisterClass*> S =
2268 std::make_pair(*
I, RC);
2290 assert(!ConstraintCode.empty() &&
"No known constraint!");
2291 return isdigit(static_cast<unsigned char>(ConstraintCode[0]));
2297 assert(!ConstraintCode.empty() &&
"No known constraint!");
2298 return atoi(ConstraintCode.c_str());
2314 unsigned maCount = 0;
2322 ConstraintOperands.emplace_back(std::move(CI));
2332 switch (OpInfo.
Type) {
2348 assert(ResNo == 0 &&
"Asm only has one result!");
2371 if (
StructType *STy = dyn_cast<StructType>(OpTy))
2372 if (STy->getNumElements() == 1)
2373 OpTy = STy->getElementType(0);
2391 }
else if (
PointerType *PT = dyn_cast<PointerType>(OpTy)) {
2401 if (!ConstraintOperands.empty()) {
2403 unsigned bestMAIndex = 0;
2404 int bestWeight = -1;
2410 for (maIndex = 0; maIndex < maCount; ++maIndex) {
2412 for (
unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2413 cIndex != eIndex; ++cIndex) {
2439 weightSum += weight;
2442 if (weightSum > bestWeight) {
2443 bestWeight = weightSum;
2444 bestMAIndex = maIndex;
2449 for (
unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2450 cIndex != eIndex; ++cIndex) {
2460 for (
unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2461 cIndex != eIndex; ++cIndex) {
2472 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
2475 std::pair<unsigned, const TargetRegisterClass *> InputRC =
2480 (MatchRC.second != InputRC.second)) {
2482 " with a matching output constraint of"
2483 " incompatible type!");
2490 return ConstraintOperands;
2519 rCodes = &info.
Codes;
2525 for (
unsigned i = 0, e = rCodes->size(); i != e; ++i) {
2528 if (weight > BestWeight)
2529 BestWeight = weight;
2545 if (!CallOperandVal)
2548 switch (*constraint) {
2551 if (isa<ConstantInt>(CallOperandVal))
2555 if (isa<GlobalValue>(CallOperandVal))
2560 if (isa<ConstantFP>(CallOperandVal))
2607 assert(OpInfo.
Codes.size() > 1 &&
"Doesn't have multiple constraint options");
2608 unsigned BestIdx = 0;
2610 int BestGenerality = -1;
2613 for (
unsigned i = 0, e = OpInfo.
Codes.size(); i != e; ++i) {
2622 assert(OpInfo.
Codes[i].size() == 1 &&
2623 "Unhandled multi-letter 'other' constraint");
2624 std::vector<SDValue> ResultOps;
2627 if (!ResultOps.empty()) {
2641 if (Generality > BestGenerality) {
2644 BestGenerality = Generality;
2658 assert(!OpInfo.
Codes.empty() &&
"Must have at least one constraint");
2661 if (OpInfo.
Codes.size() == 1) {
2674 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
2692 std::vector<SDNode *> &Created) {
2693 assert(d != 0 &&
"Division by zero!");
2705 Created.push_back(Op1.
getNode());
2711 while ((t = d*xn) != 1)
2716 Created.push_back(Mul.
getNode());
2726 std::vector<SDNode *> *Created)
const {
2727 assert(Created &&
"No vector to hold sdiv ops.");
2738 if (cast<BinaryWithFlagsSDNode>(N)->
Flags.hasExact())
2749 DAG.getConstant(magics.
m, dl, VT));
2754 DAG.getConstant(magics.
m, dl, VT)).getNode(), 1);
2760 Created->push_back(Q.
getNode());
2765 Created->push_back(Q.
getNode());
2767 auto &
DL = DAG.getDataLayout();
2773 Created->push_back(Q.
getNode());
2780 Created->push_back(T.
getNode());
2781 return DAG.getNode(
ISD::ADD, dl, VT, Q, T);
2790 std::vector<SDNode *> *Created)
const {
2791 assert(Created &&
"No vector to hold udiv ops.");
2810 if (magics.
a != 0 && !Divisor[0]) {
2815 Created->push_back(Q.
getNode());
2819 assert(magics.
a == 0 &&
"Should use cheap fixup now");
2834 Created->push_back(Q.
getNode());
2836 if (magics.
a == 0) {
2838 "We shouldn't generate an undefined shift!");
2844 Created->push_back(NPQ.
getNode());
2848 Created->push_back(NPQ.
getNode());
2850 Created->push_back(NPQ.
getNode());
2860 if (!isa<ConstantSDNode>(Op.
getOperand(0))) {
2862 "be a constant integer");
2883 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
2920 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
3020 dl, Exponent, ExponentLoBit,
bool hasType(MVT vt) const
hasType - return true if this TargetRegisterClass has the ValueType vt.
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
APInt LLVM_ATTRIBUTE_UNUSED_RESULT ashr(unsigned shiftAmt) const
Arithmetic right-shift function.
static MVT getIntegerVT(unsigned BitWidth)
unsigned Log2_32_Ceil(uint32_t Value)
Log2_32_Ceil - This function returns the ceil log base 2 of the specified value, 32 if the value is z...
BUILTIN_OP_END - This must be the last enum value in this list.
A parsed version of the target data layout string in and methods for querying it. ...
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
mu magicu(unsigned LeadingZeros=0) const
Calculate the magic numbers required to implement an unsigned integer division by a constant as a seq...
SDValue getValue(unsigned R) const
static APInt getSignBit(unsigned BitWidth)
Get the SignBit for a specific bit width.
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT, SelectionDAG &DAG, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) const
Expand a MUL into two nodes.
static APInt getAllOnesValue(unsigned numBits)
Get the all-ones value.
LLVMContext * getContext() const
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
size_t size() const
size - Get the string size.
Sign extended before/after call.
bool none() const
none - Returns true if none of the bits are set.
SDValue getBoolExtOrTrunc(SDValue Op, SDLoc SL, EVT VT, EVT OpVT)
Convert Op, which must be of integer type, to the integer type VT, by using an extension appropriate ...
ValTy * getArgument(unsigned ArgNo) const
bool hasOneUse() const
Return true if there is exactly one use of this node.
Force argument to be passed in register.
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded)
Check to see if the specified operand of the specified instruction is a constant integer.
const TargetMachine & getTargetMachine() const
bool isCalledByLegalizer() const
CallLoweringInfo & setDebugLoc(SDLoc dl)
bool isConstTrueVal(const SDNode *N) const
Return if the N is a constant or constant vector equal to the true value from getBooleanContents().
Nested function static chain.
void computeKnownBits(SDValue Op, APInt &KnownZero, APInt &KnownOne, unsigned Depth=0) const
Determine which bits of Op are known to be either zero or one and return them in the KnownZero/KnownO...
MVT getSimpleValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the MVT corresponding to this LLVM type. See getValueType.
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Get a value with low bits set.
const GlobalValue * getGlobal() const
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
SDValue getSelectCC(SDLoc DL, SDValue LHS, SDValue RHS, SDValue True, SDValue False, ISD::CondCode Cond)
Helper function to make it easier to build SelectCC's if you just have an ISD::CondCode instead of an...
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Type * getTypeForEVT(LLVMContext &Context) const
getTypeForEVT - This method returns an LLVM type corresponding to the specified EVT.
unsigned getSizeInBits() const
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
bool isUnindexed() const
Return true if this is NOT a pre/post inc/dec load/store.
bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded, SDLoc dl)
Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free.
regclass_iterator regclass_end() const
virtual bool isLegalICmpImmediate(int64_t) const
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
unsigned getNumOperands() const
unsigned getValueSizeInBits() const
Returns the size of the value in bits.
virtual bool isZExtFree(Type *, Type *) const
Return true if any actual instruction that defines a value of type Ty1 implicitly zero-extends the va...
const SDValue & getOperand(unsigned Num) const
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
ms magic() const
Calculate the magic numbers required to implement a signed integer division by a constant as a sequen...
bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const
Expand float(f32) to SINT(i64) conversion.
static bool isCommutativeBinOp(unsigned Opcode)
Returns true if the opcode is a commutative binary operation.
ConstantSDNode * getConstantSplatNode(BitVector *UndefElements=nullptr) const
Returns the splatted constant or null if this is not a constant splat.
Value * CallOperandVal
If this is the result output operand or a clobber, this is null, otherwise it is the incoming operand...
bool hasAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return true if the attribute exists at the given index.
const MCPhysReg * iterator
bool isTrueWhenEqual(CondCode Cond)
isTrueWhenEqual - Return true if the specified condition returns true if the two operands to the cond...
const SDValue & getBasePtr() const
CallLoweringInfo & setDiscardResult(bool Value=true)
SDValue BuildUDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode * > *Created) const
Given an ISD::UDIV node expressing a divide by constant, return a DAG expression to select that will ...
Magic data for optimising unsigned division by a constant.
virtual bool isTypeDesirableForOp(unsigned, EVT VT) const
Return true if the target has native support for the specified value type and it is 'desirable' to us...
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
static APInt getSignedMaxValue(unsigned numBits)
Gets maximum signed value of APInt for a specific bit width.
bool bitsLT(EVT VT) const
bitsLT - Return true if this has less bits than VT.
bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, APInt &KnownZero, APInt &KnownOne, TargetLoweringOpt &TLO, unsigned Depth=0) const
Look at Op.
INT = FGETSIGN(FP) - Return the sign bit of the specified floating point value as an integer 0/1 valu...
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag=true)
Reports a serious error, calling any installed error handler.
bool isAllOnesValue() const
SDValue getExternalSymbol(const char *Sym, EVT VT)
ConstraintCodeVector Codes
Code - The constraint code, either the register name (in braces) or the constraint letter/number...
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
A convenience struct that encapsulates a DAG, and two SDValues for returning information from TargetL...
bool isSingleValueType() const
isSingleValueType - Return true if the type is a valid type for a register in codegen.
bool isNegative() const
Determine sign of this APInt.
bool isVector() const
isVector - Return true if this is a vector value type.
virtual const char * LowerXConstraint(EVT ConstraintVT) const
Try to replace an X constraint, which matches anything, with another that has more specific requireme...
void setAttributes(ImmutableCallSite *CS, unsigned AttrIdx)
Set CallLoweringInfo attribute flags based on a call instruction and called function attributes...
virtual const char * getTargetNodeName(unsigned Opcode) const
This method returns the name of a target specific DAG node.
bool isRound() const
isRound - Return true if the size is a power-of-two number of bytes.
virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const
This method will be invoked for all target nodes and for any target-independent nodes that the target...
int64_t getOffset() const
Shift and rotation operations.
StructType - Class to represent struct types.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
MachineFunction & getMachineFunction() const
std::pair< SDValue, SDValue > makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops, unsigned NumOps, bool isSigned, SDLoc dl, bool doesNotReturn=false, bool isReturnValueUsed=true) const
Returns a pair of (return value, chain).
TargetLowering::ConstraintType ConstraintType
Information about the constraint code, e.g.
virtual void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth=0) const
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
APInt LLVM_ATTRIBUTE_UNUSED_RESULT lshr(unsigned shiftAmt) const
Logical right-shift function.
CallLoweringInfo & setChain(SDValue InChain)
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
SDValue getTargetGlobalAddress(const GlobalValue *GV, SDLoc DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
Base class for the full range of assembler expressions which are needed for parsing.
iterator begin() const
begin/end - Return all of the registers in this class.
MachinePointerInfo getWithOffset(int64_t O) const
bool isSized(SmallPtrSetImpl< const Type * > *Visited=nullptr) const
isSized - Return true if it makes sense to take the size of this type.
EVT getScalarType() const
getScalarType - If this is a vector type, return the element type, otherwise return this...
bool isStrongDefinitionForLinker() const
Returns true if this global's definition will be the one chosen by the linker.
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
uint16_t getParamAlignment(uint16_t i) const
Extract the alignment for a call or parameter (0=unknown).
SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, SDLoc dl) const
Try to simplify a setcc built with the specified operands and cc.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Hidden pointer to structure to return.
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
Context object for machine code objects.
void emitError(unsigned LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
virtual bool isUsedByReturnOnly(SDNode *, SDValue &) const
Return true if result of the specified node is used by a return node only.
LLVMContext & getContext() const
getContext - Return the LLVMContext in which this type was uniqued.
static SDNodeIterator begin(const SDNode *N)
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
ValTy * getCalledValue() const
getCalledValue - Return the pointer to function that is being called.
EK_LabelDifference32 - Each entry is the address of the block minus the address of the jump table...
const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
This contains information for each constraint that we are lowering.
Simple integer binary arithmetic operators.
EK_BlockAddress - Each entry is a plain address of block, e.g.
CallLoweringInfo & setZExtResult(bool Value=true)
bool isLittleEndian() const
Layout endianness...
signed char MatchingInput
MatchingInput - If this is not -1, this is an output constraint where an input constraint is required...
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
const APInt & getAPIntValue() const
APInt LLVM_ATTRIBUTE_UNUSED_RESULT shl(unsigned shiftAmt) const
Left-shift function.
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
EVT getMemoryVT() const
Return the type of the in-memory value.
ConstraintPrefix Type
Type - The basic type of the constraint: input/output/clobber.
bool isSignedIntSetCC(CondCode Code)
isSignedIntSetCC - Return true if this is a setcc instruction that performs a signed comparison when ...
unsigned getMinSignedBits() const
Get the minimum bit size for this signed APInt.
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
Type * getElementType() const
Considered to not alias after call.
const DataLayout & getDataLayout() const
bool bitsLE(EVT VT) const
bitsLE - Return true if this has no more bits than VT.
bool isLegalRC(const TargetRegisterClass *RC) const
Return true if the value types that can be represented by the specified register class are all legal...
PointerType - Class to represent pointers.
UNDEF - An undefined node.
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Get a value with high bits set.
SDNode * getNode() const
get the SDNode which holds the desired result
unsigned getScalarSizeInBits() const
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
bool isMatchingInputConstraint() const
Return true of this is an input operand that is a matching constraint like "4".
EK_GPRel64BlockAddress - Each entry is an address of block, encoded with a relocation as gp-relative...
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
bool intersects(const APInt &RHS) const
This operation tests if there are any pairs of corresponding bits between this APInt and RHS that are...
regclass_iterator regclass_begin() const
Register class iterators.
APInt LLVM_ATTRIBUTE_UNUSED_RESULT trunc(unsigned width) const
Truncate to new width.
MVT - Machine Value Type.
const SDValue & getOperand(unsigned i) const
The instances of the Type class are immutable: once they are created, they are never changed...
bool isIndirect
isIndirect - True if this operand is an indirect operand.
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG)
ValueHasExactlyOneBitSet - Test if the given value is known to have exactly one bit set...
int64_t getSExtValue() const
Get sign extended value.
unsigned getMatchedOperand() const
If this is an input matching constraint, this method returns the output operand it matches...
bool isBeforeLegalizeOps() const
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, const TargetLowering &TLI, SDValue Op, SelectionDAG *DAG)
ChooseConstraint - If there are multiple different constraints that we could pick for this operand (e...
Return value is always equal to this argument.
void AddToWorklist(SDNode *N)
SubConstraintInfoVector multipleAlternatives
multipleAlternatives - If there are multiple alternative constraints, this array will contain them...
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
APInt getLoBits(unsigned numBits) const
Compute an APInt containing numBits lowbits from this APInt.
virtual bool isTruncateFree(Type *, Type *) const
Return true if it's free to truncate a value of type Ty1 to type Ty2.
Pass structure in an alloca.
SDValue getSExtOrTrunc(SDValue Op, SDLoc DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either sign-extending or trunca...
bool isBeforeLegalize() const
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang","erlang-compatible garbage collector")
SDValue getTargetConstant(uint64_t Val, SDLoc DL, EVT VT, bool isOpaque=false)
unsigned getBitWidth() const
Return the number of bits in the APInt.
bool CombineTo(SDValue O, SDValue N)
unsigned getOpcode() const
for(unsigned i=0, e=MI->getNumOperands();i!=e;++i)
Zero extended before/after call.
unsigned getUnorderedFlavor(CondCode Cond)
getUnorderedFlavor - This function returns 0 if the condition is always false if an operand is a NaN...
CondCode getSetCCSwappedOperands(CondCode Operation)
getSetCCSwappedOperands - Return the operation corresponding to (Y op X) when given the operation for...
static MVT getVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
unsigned countPopulation() const
Count the number of bits set.
bool isConstFalseVal(const SDNode *N) const
Return if the N is a constant or constant vector equal to the false value from getBooleanContents().
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth=0) const
Return true if 'Op & Mask' is known to be zero.
SDValue BuildSDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode * > *Created) const
Given an ISD::SDIV node expressing a divide by constant, return a DAG expression to select that will ...
EVT - Extended Value Type.
bool isIntN(unsigned N, int64_t x)
isIntN - Checks if an signed integer fits into the given (dynamic) bit width.
uint64_t NextPowerOf2(uint64_t A)
NextPowerOf2 - Returns the next power of two (in 64-bits) that is strictly greater than A...
std::vector< ArgListEntry > ArgListTy
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
For targets without i1 registers, this gives the nature of the high-bits of boolean values held in ty...
std::string ConstraintCode
This contains the actual string for the code, like "m".
virtual SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const
Returns relocation base for the given PIC jumptable.
virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=nullptr) const
Determines the constraint code and constraint type to use for the specific AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
const MachinePointerInfo & getPointerInfo() const
This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from ...
ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const
Get the CondCode that's to be used to test the result of the comparison libcall against zero...
bool bitsGT(EVT VT) const
bitsGT - Return true if this has more bits than VT.
unsigned countTrailingZeros() const
Count the number of trailing zero bits.
std::vector< AsmOperandInfo > AsmOperandInfoVector
static IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
std::vector< std::string > ConstraintCodeVector
SDValue getNOT(SDLoc DL, SDValue Val, EVT VT)
Create a bitwise NOT operation as (XOR Val, -1).
SmallVectorImpl< T >::const_pointer c_str(SmallVectorImpl< T > &str)
virtual unsigned getJumpTableEncoding() const
Return the entry encoding for a jump table in the current function.
APInt getHiBits(unsigned numBits) const
Compute an APInt containing numBits highbits from this APInt.
const char * getLibcallName(RTLIB::Libcall Call) const
Get the libcall routine name for the specified libcall.
bool paramHasAttr(unsigned i, Attribute::AttrKind A) const
Return true if the call or the callee has the given attribute.
double Log2(double Value)
Log2 - This function returns the log base 2 of the specified value.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Type * getType() const
All values are typed, get the type of this value.
virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const
Return the ValueType of the result of SETCC operations.
const SDValue & getChain() const
bool hasMatchingInput() const
hasMatchingInput - Return true if this is an output constraint that has a matching input constraint...
bool isStrictlyPositive() const
Determine if this APInt Value is positive.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static APInt getMinValue(unsigned numBits)
Gets minimum unsigned value of APInt for a specific bit width.
CallLoweringInfo & setSExtResult(bool Value=true)
virtual const MCExpr * getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const
This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase, but as an MCExpr.
virtual bool isGAPlusOffset(SDNode *N, const GlobalValue *&GA, int64_t &Offset) const
Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + offset...
Represents one node in the SelectionDAG.
CondCode getSetCCInverse(CondCode Operation, bool isInteger)
getSetCCInverse - Return the operation corresponding to !(X op Y), where 'op' is a valid SetCC operat...
virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const
Returns true if arguments should be sign-extended in lib calls.
virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const SelectionDAG &DAG, unsigned Depth=0) const
This method can be implemented by targets that want to expose additional information about sign bits ...
bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node, SDValue &Chain) const
Check whether a given call node is in tail position within its function.
unsigned Log2_32(uint32_t Value)
Log2_32 - This function returns the floor log base 2 of the specified value, -1 if the value is zero...
AttributeSet getAttributes() const
Return the attribute list for this Function.
MCSymbol * getJTISymbol(unsigned JTI, MCContext &Ctx, bool isLinkerPrivate=false) const
getJTISymbol - Return the MCSymbol for the specified non-empty jump table.
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
Class for arbitrary precision integers.
A "pseudo-class" with methods for operating on BUILD_VECTORs.
Select(COND, TRUEVAL, FALSEVAL).
int64_t getSExtValue() const
bool isIntegerTy() const
isIntegerTy - True if this is an instance of IntegerType.
ZERO_EXTEND - Used for integer types, zeroing the new bits.
static SDValue BuildExactSDIV(const TargetLowering &TLI, SDValue Op1, APInt d, SDLoc dl, SelectionDAG &DAG, std::vector< SDNode * > &Created)
Given an exact SDIV by a constant, create a multiplication with the multiplicative inverse of the con...
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
ANY_EXTEND - Used for integer types. The high bits are undefined.
static APInt getMaxValue(unsigned numBits)
Gets maximum unsigned value of APInt for specific bit width.
APInt And(const APInt &LHS, const APInt &RHS)
Bitwise AND function for APInt.
static APInt getBitsSet(unsigned numBits, unsigned loBit, unsigned hiBit)
Get a value with a block of bits set.
virtual MVT::SimpleValueType getCmpLibcallReturnType() const
Return the ValueType for comparison libcalls.
bool isAllOnesValue() const
Determine if all bits are set.
uint64_t MinAlign(uint64_t A, uint64_t B)
MinAlign - A and B are either alignments or offsets.
These are IR-level optimization flags that may be propagated to SDNodes.
Magic data for optimising signed division by a constant.
Bitwise operators - logical and, logical or, logical xor.
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
ImmutableCallSite - establish a view to a call site for examination.
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
SDValue FoldSetCC(EVT VT, SDValue N1, SDValue N2, ISD::CondCode Cond, SDLoc dl)
Constant fold a setcc to true or false.
static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT)
getConstraintGenerality - Return an integer indicating how general CT is.
EVT getValueType() const
Return the ValueType of the referenced return value.
SDValue getCondCode(ISD::CondCode Cond)
SDValue getConstant(uint64_t Val, SDLoc DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Type * getType() const
getType - Return the type of the instruction that generated this call site
SDValue getGLOBAL_OFFSET_TABLE(EVT VT)
Return a GLOBAL_OFFSET_TABLE node. This does not have a useful SDLoc.
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
static APInt getSignedMinValue(unsigned numBits)
Gets minimum signed value of APInt for a specific bit width.
bool isSimple() const
isSimple - Test if the given EVT is simple (as opposed to being extended).
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
SDValue getZExtOrTrunc(SDValue Op, SDLoc DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either zero-extending or trunca...
LLVM Value Representation.
static SDNodeIterator end(const SDNode *N)
unsigned ComputeNumSignBits(SDValue Op, unsigned Depth=0) const
Return the number of times the sign bit of the register is replicated into the other bits...
virtual ConstraintWeight getMultipleConstraintMatchWeight(AsmOperandInfo &info, int maIndex) const
Examine constraint type and operand type and determine a weight value.
uint64_t getTypeSizeInBits(Type *Ty) const
Size examples:
unsigned countLeadingZeros() const
The APInt version of the countLeadingZeros functions in MathExtras.h.
Primary interface to the complete machine description for the target machine.
const char * getName(unsigned RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register...
bool isPowerOf2_32(uint32_t Value)
isPowerOf2_32 - This function returns true if the argument is a power of two > 0. ...
StringRef - Represent a constant reference to a string, i.e.
APInt LLVM_ATTRIBUTE_UNUSED_RESULT zext(unsigned width) const
Zero extend to a new width.
SetCC operator - This evaluates to a true value iff the condition is true.
EK_GPRel32BlockAddress - Each entry is an address of block, encoded with a relocation as gp-relative...
virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const
Return true if folding a constant offset with the given GlobalAddress is legal.
MVT ConstraintVT
The ValueType for the operand value.
SDValue getSetCC(SDLoc DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
BooleanContent
Enum that describes how the target represents true/false values.
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
TRUNCATE - Completely drop the high bits.
EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL) const
unsigned getAlignment() const
bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const
Return true if the specified condition code is legal on this target.
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
Examine constraint string and operand type and determine a weight value.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
getIntegerVT - Returns the EVT that represents an integer with the given number of bits...
const TargetRegisterClass *const * regclass_iterator
virtual AsmOperandInfoVector ParseConstraints(const DataLayout &DL, const TargetRegisterInfo *TRI, ImmutableCallSite CS) const
Split up the constraint string from the inline assembly value into the specific constraints and their...
LegalizeAction getCondCodeAction(ISD::CondCode CC, MVT VT) const
Return how the condition code should be treated: either it is legal, needs to be expanded to some oth...
MVT getSimpleVT() const
getSimpleVT - Return the SimpleValueType held in the specified simple EVT.
static ConstraintInfoVector ParseConstraints(StringRef ConstraintString)
ParseConstraints - Split up the constraint string into the specific constraints and their prefixes...
This file describes how to lower LLVM code to machine code.
bool isVoidTy() const
isVoidTy - Return true if this is 'void'.
void selectAlternative(unsigned index)
selectAlternative - Point this constraint to the alternative constraint indicated by the index...
bool empty() const
empty - Check if the string is empty.
uint64_t getZExtValue() const
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, SDLoc DL) const
SoftenSetCCOperands - Soften the operands of a comparison.
This class is used to represent ISD::LOAD nodes.