LLVM  3.7.0
X86Subtarget.h
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1 //===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file declares the X86 specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_X86_X86SUBTARGET_H
15 #define LLVM_LIB_TARGET_X86_X86SUBTARGET_H
16 
17 #include "X86FrameLowering.h"
18 #include "X86ISelLowering.h"
19 #include "X86InstrInfo.h"
20 #include "X86SelectionDAGInfo.h"
21 #include "llvm/ADT/Triple.h"
22 #include "llvm/IR/CallingConv.h"
24 #include <string>
25 
26 #define GET_SUBTARGETINFO_HEADER
27 #include "X86GenSubtargetInfo.inc"
28 
29 namespace llvm {
30 class GlobalValue;
31 class StringRef;
32 class TargetMachine;
33 
34 /// The X86 backend supports a number of different styles of PIC.
35 ///
36 namespace PICStyles {
37 enum Style {
38  StubPIC, // Used on i386-darwin in -fPIC mode.
39  StubDynamicNoPIC, // Used on i386-darwin in -mdynamic-no-pic mode.
40  GOT, // Used on many 32-bit unices in -fPIC mode.
41  RIPRel, // Used on X86-64 when not in -static mode.
42  None // Set when in -static mode (not PIC or DynamicNoPIC mode).
43 };
44 }
45 
46 class X86Subtarget final : public X86GenSubtargetInfo {
47 
48 protected:
49  enum X86SSEEnum {
51  };
52 
53  enum X863DNowEnum {
55  };
56 
59  };
60 
61  /// X86 processor family: Intel Atom, and others
63 
64  /// Which PIC style to use
66 
67  /// MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
69 
70  /// 3DNow, 3DNow Athlon, or none supported.
72 
73  /// True if this processor has conditional move instructions
74  /// (generally pentium pro+).
75  bool HasCMov;
76 
77  /// True if the processor supports X86-64 instructions.
78  bool HasX86_64;
79 
80  /// True if the processor supports POPCNT.
81  bool HasPOPCNT;
82 
83  /// True if the processor supports SSE4A instructions.
84  bool HasSSE4A;
85 
86  /// Target has AES instructions
87  bool HasAES;
88 
89  /// Target has carry-less multiplication
90  bool HasPCLMUL;
91 
92  /// Target has 3-operand fused multiply-add
93  bool HasFMA;
94 
95  /// Target has 4-operand fused multiply-add
96  bool HasFMA4;
97 
98  /// Target has XOP instructions
99  bool HasXOP;
100 
101  /// Target has TBM instructions.
102  bool HasTBM;
103 
104  /// True if the processor has the MOVBE instruction.
105  bool HasMOVBE;
106 
107  /// True if the processor has the RDRAND instruction.
108  bool HasRDRAND;
109 
110  /// Processor has 16-bit floating point conversion instructions.
111  bool HasF16C;
112 
113  /// Processor has FS/GS base insturctions.
115 
116  /// Processor has LZCNT instruction.
117  bool HasLZCNT;
118 
119  /// Processor has BMI1 instructions.
120  bool HasBMI;
121 
122  /// Processor has BMI2 instructions.
123  bool HasBMI2;
124 
125  /// Processor has RTM instructions.
126  bool HasRTM;
127 
128  /// Processor has HLE.
129  bool HasHLE;
130 
131  /// Processor has ADX instructions.
132  bool HasADX;
133 
134  /// Processor has SHA instructions.
135  bool HasSHA;
136 
137  /// Processor has PRFCHW instructions.
138  bool HasPRFCHW;
139 
140  /// Processor has RDSEED instructions.
141  bool HasRDSEED;
142 
143  /// True if BT (bit test) of memory instructions are slow.
145 
146  /// True if SHLD instructions are slow.
148 
149  /// True if unaligned memory access is fast.
151 
152  /// True if unaligned 32-byte memory accesses are slow.
154 
155  /// True if SSE operations can have unaligned memory operands.
156  /// This may require setting a configuration bit in the processor.
158 
159  /// True if this processor has the CMPXCHG16B instruction;
160  /// this is true for most x86-64 chips, but not the first AMD chips.
162 
163  /// True if the LEA instruction should be used for adjusting
164  /// the stack pointer. This is an optimization for Intel Atom processors.
166 
167  /// True if 8-bit divisions are significantly faster than
168  /// 32-bit divisions and should be used when possible.
170 
171  /// True if 16-bit divides are significantly faster than
172  /// 64-bit divisions and should be used when possible.
174 
175  /// True if the short functions should be padded to prevent
176  /// a stall when returning too early.
178 
179  /// True if the Calls with memory reference should be converted
180  /// to a register-based indirect call.
182 
183  /// True if the LEA instruction inputs have to be ready at address generation
184  /// (AG) time.
185  bool LEAUsesAG;
186 
187  /// True if the LEA instruction with certain arguments is slow
188  bool SlowLEA;
189 
190  /// True if INC and DEC instructions are slow when writing to flags
192 
193  /// Processor has AVX-512 PreFetch Instructions
194  bool HasPFI;
195 
196  /// Processor has AVX-512 Exponential and Reciprocal Instructions
197  bool HasERI;
198 
199  /// Processor has AVX-512 Conflict Detection Instructions
200  bool HasCDI;
201 
202  /// Processor has AVX-512 Doubleword and Quadword instructions
203  bool HasDQI;
204 
205  /// Processor has AVX-512 Byte and Word instructions
206  bool HasBWI;
207 
208  /// Processor has AVX-512 Vector Length eXtenstions
209  bool HasVLX;
210 
211  /// Processot supports MPX - Memory Protection Extensions
212  bool HasMPX;
213 
214  /// Use software floating point for code generation.
216 
217  /// The minimum alignment known to hold of the stack frame on
218  /// entry to the function and which must be maintained by every function.
219  unsigned stackAlignment;
220 
221  /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
222  ///
224 
225  /// What processor and OS we're targeting.
227 
228  /// Instruction itineraries for scheduling
230 
231 private:
232 
233  /// Override the stack alignment.
234  unsigned StackAlignOverride;
235 
236  /// True if compiling for 64-bit, false for 16-bit or 32-bit.
237  bool In64BitMode;
238 
239  /// True if compiling for 32-bit, false for 16-bit or 64-bit.
240  bool In32BitMode;
241 
242  /// True if compiling for 16-bit, false for 32-bit or 64-bit.
243  bool In16BitMode;
244 
245  X86SelectionDAGInfo TSInfo;
246  // Ordering here is important. X86InstrInfo initializes X86RegisterInfo which
247  // X86TargetLowering needs.
248  X86InstrInfo InstrInfo;
249  X86TargetLowering TLInfo;
250  X86FrameLowering FrameLowering;
251 
252 public:
253  /// This constructor initializes the data members to match that
254  /// of the specified triple.
255  ///
256  X86Subtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
257  const X86TargetMachine &TM, unsigned StackAlignOverride);
258 
259  const X86TargetLowering *getTargetLowering() const override {
260  return &TLInfo;
261  }
262  const X86InstrInfo *getInstrInfo() const override { return &InstrInfo; }
263  const X86FrameLowering *getFrameLowering() const override {
264  return &FrameLowering;
265  }
266  const X86SelectionDAGInfo *getSelectionDAGInfo() const override {
267  return &TSInfo;
268  }
269  const X86RegisterInfo *getRegisterInfo() const override {
270  return &getInstrInfo()->getRegisterInfo();
271  }
272 
273  /// Returns the minimum alignment known to hold of the
274  /// stack frame on entry to the function and which must be maintained by every
275  /// function for this subtarget.
276  unsigned getStackAlignment() const { return stackAlignment; }
277 
278  /// Returns the maximum memset / memcpy size
279  /// that still makes it profitable to inline the call.
281 
282  /// ParseSubtargetFeatures - Parses features string setting specified
283  /// subtarget options. Definition of function is auto generated by tblgen.
285 
286 private:
287  /// Initialize the full set of dependencies so we can use an initializer
288  /// list for X86Subtarget.
289  X86Subtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
290  void initializeEnvironment();
291  void initSubtargetFeatures(StringRef CPU, StringRef FS);
292 public:
293  /// Is this x86_64? (disregarding specific ABI / programming model)
294  bool is64Bit() const {
295  return In64BitMode;
296  }
297 
298  bool is32Bit() const {
299  return In32BitMode;
300  }
301 
302  bool is16Bit() const {
303  return In16BitMode;
304  }
305 
306  /// Is this x86_64 with the ILP32 programming model (x32 ABI)?
307  bool isTarget64BitILP32() const {
308  return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32 ||
310  }
311 
312  /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
313  bool isTarget64BitLP64() const {
314  return In64BitMode && (TargetTriple.getEnvironment() != Triple::GNUX32 &&
316  }
317 
320 
321  bool hasCMov() const { return HasCMov; }
322  bool hasMMX() const { return X86SSELevel >= MMX; }
323  bool hasSSE1() const { return X86SSELevel >= SSE1; }
324  bool hasSSE2() const { return X86SSELevel >= SSE2; }
325  bool hasSSE3() const { return X86SSELevel >= SSE3; }
326  bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
327  bool hasSSE41() const { return X86SSELevel >= SSE41; }
328  bool hasSSE42() const { return X86SSELevel >= SSE42; }
329  bool hasAVX() const { return X86SSELevel >= AVX; }
330  bool hasAVX2() const { return X86SSELevel >= AVX2; }
331  bool hasAVX512() const { return X86SSELevel >= AVX512F; }
332  bool hasFp256() const { return hasAVX(); }
333  bool hasInt256() const { return hasAVX2(); }
334  bool hasSSE4A() const { return HasSSE4A; }
335  bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
336  bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
337  bool hasPOPCNT() const { return HasPOPCNT; }
338  bool hasAES() const { return HasAES; }
339  bool hasPCLMUL() const { return HasPCLMUL; }
340  bool hasFMA() const { return HasFMA; }
341  // FIXME: Favor FMA when both are enabled. Is this the right thing to do?
342  bool hasFMA4() const { return HasFMA4 && !HasFMA; }
343  bool hasXOP() const { return HasXOP; }
344  bool hasTBM() const { return HasTBM; }
345  bool hasMOVBE() const { return HasMOVBE; }
346  bool hasRDRAND() const { return HasRDRAND; }
347  bool hasF16C() const { return HasF16C; }
348  bool hasFSGSBase() const { return HasFSGSBase; }
349  bool hasLZCNT() const { return HasLZCNT; }
350  bool hasBMI() const { return HasBMI; }
351  bool hasBMI2() const { return HasBMI2; }
352  bool hasRTM() const { return HasRTM; }
353  bool hasHLE() const { return HasHLE; }
354  bool hasADX() const { return HasADX; }
355  bool hasSHA() const { return HasSHA; }
356  bool hasPRFCHW() const { return HasPRFCHW; }
357  bool hasRDSEED() const { return HasRDSEED; }
358  bool isBTMemSlow() const { return IsBTMemSlow; }
359  bool isSHLDSlow() const { return IsSHLDSlow; }
360  bool isUnalignedMemAccessFast() const { return IsUAMemFast; }
361  bool isUnalignedMem32Slow() const { return IsUAMem32Slow; }
362  bool hasSSEUnalignedMem() const { return HasSSEUnalignedMem; }
363  bool hasCmpxchg16b() const { return HasCmpxchg16b; }
364  bool useLeaForSP() const { return UseLeaForSP; }
365  bool hasSlowDivide32() const { return HasSlowDivide32; }
366  bool hasSlowDivide64() const { return HasSlowDivide64; }
367  bool padShortFunctions() const { return PadShortFunctions; }
368  bool callRegIndirect() const { return CallRegIndirect; }
369  bool LEAusesAG() const { return LEAUsesAG; }
370  bool slowLEA() const { return SlowLEA; }
371  bool slowIncDec() const { return SlowIncDec; }
372  bool hasCDI() const { return HasCDI; }
373  bool hasPFI() const { return HasPFI; }
374  bool hasERI() const { return HasERI; }
375  bool hasDQI() const { return HasDQI; }
376  bool hasBWI() const { return HasBWI; }
377  bool hasVLX() const { return HasVLX; }
378  bool hasMPX() const { return HasMPX; }
379 
380  bool isAtom() const { return X86ProcFamily == IntelAtom; }
381  bool isSLM() const { return X86ProcFamily == IntelSLM; }
382  bool useSoftFloat() const { return UseSoftFloat; }
383 
384  const Triple &getTargetTriple() const { return TargetTriple; }
385 
386  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
387  bool isTargetFreeBSD() const { return TargetTriple.isOSFreeBSD(); }
388  bool isTargetDragonFly() const { return TargetTriple.isOSDragonFly(); }
389  bool isTargetSolaris() const { return TargetTriple.isOSSolaris(); }
390  bool isTargetPS4() const { return TargetTriple.isPS4(); }
391 
392  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
393  bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
394  bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
395 
396  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
397  bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
398  bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
399  bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
400 
401  bool isTargetWindowsMSVC() const {
403  }
404 
407  }
408 
409  bool isTargetWindowsCygwin() const {
411  }
412 
413  bool isTargetWindowsGNU() const {
415  }
416 
417  bool isTargetWindowsItanium() const {
419  }
420 
421  bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
422 
423  bool isOSWindows() const { return TargetTriple.isOSWindows(); }
424 
425  bool isTargetWin64() const {
426  return In64BitMode && TargetTriple.isOSWindows();
427  }
428 
429  bool isTargetWin32() const {
430  return !In64BitMode && (isTargetCygMing() || isTargetKnownWindowsMSVC());
431  }
432 
433  bool isPICStyleSet() const { return PICStyle != PICStyles::None; }
434  bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
435  bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
436 
437  bool isPICStyleStubPIC() const {
438  return PICStyle == PICStyles::StubPIC;
439  }
440 
441  bool isPICStyleStubNoDynamic() const {
443  }
444  bool isPICStyleStubAny() const {
447  }
448 
450  switch (CC) {
451  // On Win64, all these conventions just use the default convention.
452  case CallingConv::C:
453  case CallingConv::Fast:
459  return isTargetWin64();
460  // This convention allows using the Win64 convention on other targets.
462  return true;
463  // This convention allows using the SysV convention on Windows targets.
465  return false;
466  // Otherwise, who knows what this is.
467  default:
468  return false;
469  }
470  }
471 
472  /// ClassifyGlobalReference - Classify a global variable reference for the
473  /// current subtarget according to how we should reference it in a non-pcrel
474  /// context.
475  unsigned char ClassifyGlobalReference(const GlobalValue *GV,
476  const TargetMachine &TM)const;
477 
478  /// Classify a blockaddress reference for the current subtarget according to
479  /// how we should reference it in a non-pcrel context.
480  unsigned char ClassifyBlockAddressReference() const;
481 
482  /// Return true if the subtarget allows calls to immediate address.
483  bool IsLegalToCallImmediateAddr(const TargetMachine &TM) const;
484 
485  /// This function returns the name of a function which has an interface
486  /// like the non-standard bzero function, if such a function exists on
487  /// the current subtarget and it is considered prefereable over
488  /// memset with zero passed as the second argument. Otherwise it
489  /// returns null.
490  const char *getBZeroEntry() const;
491 
492  /// This function returns true if the target has sincos() routine in its
493  /// compiler runtime or math libraries.
494  bool hasSinCos() const;
495 
496  /// Enable the MachineScheduler pass for all X86 subtargets.
497  bool enableMachineScheduler() const override { return true; }
498 
499  bool enableEarlyIfConversion() const override;
500 
501  /// Return the instruction itineraries based on the subtarget selection.
502  const InstrItineraryData *getInstrItineraryData() const override {
503  return &InstrItins;
504  }
505 
506  AntiDepBreakMode getAntiDepBreakMode() const override {
508  }
509 };
510 
511 } // End llvm namespace
512 
513 #endif
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
unsigned getMaxInlineSizeThreshold() const
Returns the maximum memset / memcpy size that still makes it profitable to inline the call...
Definition: X86Subtarget.h:280
bool HasPRFCHW
Processor has PRFCHW instructions.
Definition: X86Subtarget.h:138
const X86RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: X86InstrInfo.h:195
bool hasF16C() const
Definition: X86Subtarget.h:347
bool HasTBM
Target has TBM instructions.
Definition: X86Subtarget.h:102
bool hasDQI() const
Definition: X86Subtarget.h:375
Intel_OCL_BI - Calling conventions for Intel OpenCL built-ins.
Definition: CallingConv.h:133
bool HasBMI2
Processor has BMI2 instructions.
Definition: X86Subtarget.h:123
The C convention as specified in the x86-64 supplement to the System V ABI, used on most non-Windows ...
Definition: CallingConv.h:137
bool hasSSE3() const
Definition: X86Subtarget.h:325
bool isTargetWindowsCygwin() const
Definition: X86Subtarget.h:409
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:489
bool hasPFI() const
Definition: X86Subtarget.h:373
bool isTargetCygMing() const
Definition: X86Subtarget.h:421
const X86InstrInfo * getInstrInfo() const override
Definition: X86Subtarget.h:262
bool HasCDI
Processor has AVX-512 Conflict Detection Instructions.
Definition: X86Subtarget.h:200
bool slowIncDec() const
Definition: X86Subtarget.h:371
bool HasAES
Target has AES instructions.
Definition: X86Subtarget.h:87
bool isTargetMachO() const
Definition: X86Subtarget.h:394
const X86FrameLowering * getFrameLowering() const override
Definition: X86Subtarget.h:263
void setPICStyle(PICStyles::Style Style)
Definition: X86Subtarget.h:319
bool isTargetPS4() const
Definition: X86Subtarget.h:390
bool HasERI
Processor has AVX-512 Exponential and Reciprocal Instructions.
Definition: X86Subtarget.h:197
bool enableMachineScheduler() const override
Enable the MachineScheduler pass for all X86 subtargets.
Definition: X86Subtarget.h:497
bool hasFMA4() const
Definition: X86Subtarget.h:342
unsigned char ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const
ClassifyGlobalReference - Classify a global variable reference for the current subtarget according to...
bool hasFSGSBase() const
Definition: X86Subtarget.h:348
bool hasBMI() const
Definition: X86Subtarget.h:350
unsigned MaxInlineSizeThreshold
Max.
Definition: X86Subtarget.h:223
bool LEAUsesAG
True if the LEA instruction inputs have to be ready at address generation (AG) time.
Definition: X86Subtarget.h:185
bool hasVLX() const
Definition: X86Subtarget.h:377
bool isTargetKnownWindowsMSVC() const
Definition: X86Subtarget.h:405
bool hasSSE41() const
Definition: X86Subtarget.h:327
bool IsUAMem32Slow
True if unaligned 32-byte memory accesses are slow.
Definition: X86Subtarget.h:153
bool isOSDragonFly() const
Definition: Triple.h:420
bool HasRDRAND
True if the processor has the RDRAND instruction.
Definition: X86Subtarget.h:108
bool hasRDSEED() const
Definition: X86Subtarget.h:357
bool hasBWI() const
Definition: X86Subtarget.h:376
bool hasCmpxchg16b() const
Definition: X86Subtarget.h:363
bool hasPCLMUL() const
Definition: X86Subtarget.h:339
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:464
bool hasHLE() const
Definition: X86Subtarget.h:353
bool isOSCygMing() const
Tests for either Cygwin or MinGW OS.
Definition: Triple.h:453
bool HasFMA
Target has 3-operand fused multiply-add.
Definition: X86Subtarget.h:93
bool isTargetNaCl64() const
Definition: X86Subtarget.h:399
bool is16Bit() const
Definition: X86Subtarget.h:302
bool isTargetSolaris() const
Definition: X86Subtarget.h:389
const InstrItineraryData * getInstrItineraryData() const override
Return the instruction itineraries based on the subtarget selection.
Definition: X86Subtarget.h:502
PICStyles::Style getPICStyle() const
Definition: X86Subtarget.h:318
bool isTargetDarwin() const
Definition: X86Subtarget.h:386
bool HasPOPCNT
True if the processor supports POPCNT.
Definition: X86Subtarget.h:81
bool hasAES() const
Definition: X86Subtarget.h:338
bool hasMPX() const
Definition: X86Subtarget.h:378
bool hasSHA() const
Definition: X86Subtarget.h:355
const Triple & getTargetTriple() const
Definition: X86Subtarget.h:384
bool HasSlowDivide32
True if 8-bit divisions are significantly faster than 32-bit divisions and should be used when possib...
Definition: X86Subtarget.h:169
bool isTargetWindowsItanium() const
Definition: X86Subtarget.h:417
unsigned getStackAlignment() const
Returns the minimum alignment known to hold of the stack frame on entry to the function and which mus...
Definition: X86Subtarget.h:276
bool isWindowsMSVCEnvironment() const
Definition: Triple.h:430
bool hasMMX() const
Definition: X86Subtarget.h:322
bool hasADX() const
Definition: X86Subtarget.h:354
bool HasPFI
Processor has AVX-512 PreFetch Instructions.
Definition: X86Subtarget.h:194
bool hasLZCNT() const
Definition: X86Subtarget.h:349
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:474
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
Definition: Triple.h:469
bool hasTBM() const
Definition: X86Subtarget.h:344
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:294
bool HasCmpxchg16b
True if this processor has the CMPXCHG16B instruction; this is true for most x86-64 chips...
Definition: X86Subtarget.h:161
bool isTargetWindowsGNU() const
Definition: X86Subtarget.h:413
bool isPICStyleRIPRel() const
Definition: X86Subtarget.h:435
bool slowLEA() const
Definition: X86Subtarget.h:370
Itinerary data supplied by a subtarget to be used by a target.
bool isPICStyleStubAny() const
Definition: X86Subtarget.h:444
bool hasSSSE3() const
Definition: X86Subtarget.h:326
bool UseLeaForSP
True if the LEA instruction should be used for adjusting the stack pointer.
Definition: X86Subtarget.h:165
X863DNowEnum X863DNowLevel
3DNow, 3DNow Athlon, or none supported.
Definition: X86Subtarget.h:71
bool HasSSE4A
True if the processor supports SSE4A instructions.
Definition: X86Subtarget.h:84
bool CallRegIndirect
True if the Calls with memory reference should be converted to a register-based indirect call...
Definition: X86Subtarget.h:181
bool HasLZCNT
Processor has LZCNT instruction.
Definition: X86Subtarget.h:117
bool HasF16C
Processor has 16-bit floating point conversion instructions.
Definition: X86Subtarget.h:111
bool SlowIncDec
True if INC and DEC instructions are slow when writing to flags.
Definition: X86Subtarget.h:191
bool hasSSE2() const
Definition: X86Subtarget.h:324
unsigned char ClassifyBlockAddressReference() const
Classify a blockaddress reference for the current subtarget according to how we should reference it i...
const X86TargetLowering * getTargetLowering() const override
Definition: X86Subtarget.h:259
bool useSoftFloat() const
Definition: X86Subtarget.h:382
bool hasSSEUnalignedMem() const
Definition: X86Subtarget.h:362
bool isCallingConvWin64(CallingConv::ID CC) const
Definition: X86Subtarget.h:449
bool hasBMI2() const
Definition: X86Subtarget.h:351
bool isWindowsGNUEnvironment() const
Definition: Triple.h:448
bool isTargetCOFF() const
Definition: X86Subtarget.h:393
bool hasSinCos() const
This function returns true if the target has sincos() routine in its compiler runtime or math librari...
bool isPICStyleStubPIC() const
Definition: X86Subtarget.h:437
bool IsBTMemSlow
True if BT (bit test) of memory instructions are slow.
Definition: X86Subtarget.h:144
bool useLeaForSP() const
Definition: X86Subtarget.h:364
bool HasADX
Processor has ADX instructions.
Definition: X86Subtarget.h:132
bool HasBWI
Processor has AVX-512 Byte and Word instructions.
Definition: X86Subtarget.h:206
bool hasAVX2() const
Definition: X86Subtarget.h:330
bool isTargetWin32() const
Definition: X86Subtarget.h:429
X86_StdCall - stdcall is the calling conventions mostly used by the Win32 API.
Definition: CallingConv.h:80
bool hasSlowDivide64() const
Definition: X86Subtarget.h:366
bool hasMOVBE() const
Definition: X86Subtarget.h:345
bool IsLegalToCallImmediateAddr(const TargetMachine &TM) const
Return true if the subtarget allows calls to immediate address.
PICStyles::Style PICStyle
Which PIC style to use.
Definition: X86Subtarget.h:65
bool hasFp256() const
Definition: X86Subtarget.h:332
bool HasXOP
Target has XOP instructions.
Definition: X86Subtarget.h:99
bool SlowLEA
True if the LEA instruction with certain arguments is slow.
Definition: X86Subtarget.h:188
bool isPICStyleStubNoDynamic() const
Definition: X86Subtarget.h:441
bool HasDQI
Processor has AVX-512 Doubleword and Quadword instructions.
Definition: X86Subtarget.h:203
bool enableEarlyIfConversion() const override
bool has3DNowA() const
Definition: X86Subtarget.h:336
bool isSHLDSlow() const
Definition: X86Subtarget.h:359
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:484
bool isOSWindows() const
Definition: X86Subtarget.h:423
bool IsSHLDSlow
True if SHLD instructions are slow.
Definition: X86Subtarget.h:147
bool isPICStyleGOT() const
Definition: X86Subtarget.h:434
InstrItineraryData InstrItins
Instruction itineraries for scheduling.
Definition: X86Subtarget.h:229
bool isPICStyleSet() const
Definition: X86Subtarget.h:433
bool HasFSGSBase
Processor has FS/GS base insturctions.
Definition: X86Subtarget.h:114
bool hasRDRAND() const
Definition: X86Subtarget.h:346
bool isOSSolaris() const
Definition: Triple.h:422
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool hasXOP() const
Definition: X86Subtarget.h:343
const X86RegisterInfo * getRegisterInfo() const override
Definition: X86Subtarget.h:269
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X or iOS).
Definition: Triple.h:404
X86Subtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const X86TargetMachine &TM, unsigned StackAlignOverride)
This constructor initializes the data members to match that of the specified triple.
bool hasSSE4A() const
Definition: X86Subtarget.h:334
bool HasMPX
Processot supports MPX - Memory Protection Extensions.
Definition: X86Subtarget.h:212
X86ProcFamilyEnum X86ProcFamily
X86 processor family: Intel Atom, and others.
Definition: X86Subtarget.h:62
bool HasX86_64
True if the processor supports X86-64 instructions.
Definition: X86Subtarget.h:78
bool HasSSEUnalignedMem
True if SSE operations can have unaligned memory operands.
Definition: X86Subtarget.h:157
bool isTargetWindowsMSVC() const
Definition: X86Subtarget.h:401
bool isTarget64BitILP32() const
Is this x86_64 with the ILP32 programming model (x32 ABI)?
Definition: X86Subtarget.h:307
bool isTargetELF() const
Definition: X86Subtarget.h:392
bool HasSHA
Processor has SHA instructions.
Definition: X86Subtarget.h:135
bool HasBMI
Processor has BMI1 instructions.
Definition: X86Subtarget.h:120
bool isUnalignedMem32Slow() const
Definition: X86Subtarget.h:361
bool isTargetLinux() const
Definition: X86Subtarget.h:396
bool HasHLE
Processor has HLE.
Definition: X86Subtarget.h:129
X86_FastCall - 'fast' analog of X86_StdCall.
Definition: CallingConv.h:85
bool hasCDI() const
Definition: X86Subtarget.h:372
bool has3DNow() const
Definition: X86Subtarget.h:335
bool UseSoftFloat
Use software floating point for code generation.
Definition: X86Subtarget.h:215
bool hasInt256() const
Definition: X86Subtarget.h:333
bool isUnalignedMemAccessFast() const
Definition: X86Subtarget.h:360
bool hasCMov() const
Definition: X86Subtarget.h:321
bool isTargetDragonFly() const
Definition: X86Subtarget.h:388
bool hasPOPCNT() const
Definition: X86Subtarget.h:337
bool hasSSE1() const
Definition: X86Subtarget.h:323
bool HasPCLMUL
Target has carry-less multiplication.
Definition: X86Subtarget.h:90
bool hasPRFCHW() const
Definition: X86Subtarget.h:356
bool isAtom() const
Definition: X86Subtarget.h:380
bool is32Bit() const
Definition: X86Subtarget.h:298
bool isBTMemSlow() const
Definition: X86Subtarget.h:358
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:479
const X86SelectionDAGInfo * getSelectionDAGInfo() const override
Definition: X86Subtarget.h:266
bool hasSSE42() const
Definition: X86Subtarget.h:328
MSVC calling convention that passes vectors and vector aggregates in SSE registers.
Definition: CallingConv.h:147
bool isWindowsCygwinEnvironment() const
Definition: Triple.h:444
bool isTarget64BitLP64() const
Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
Definition: X86Subtarget.h:313
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
X86SSEEnum X86SSELevel
MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
Definition: X86Subtarget.h:68
bool hasAVX512() const
Definition: X86Subtarget.h:331
bool LEAusesAG() const
Definition: X86Subtarget.h:369
X86_ThisCall - Similar to X86_StdCall.
Definition: CallingConv.h:104
bool isOSFreeBSD() const
Definition: Triple.h:416
EnvironmentType getEnvironment() const
getEnvironment - Get the parsed environment type of this triple.
Definition: Triple.h:260
bool hasRTM() const
Definition: X86Subtarget.h:352
bool HasCMov
True if this processor has conditional move instructions (generally pentium pro+).
Definition: X86Subtarget.h:75
bool isTargetWin64() const
Definition: X86Subtarget.h:425
bool isSLM() const
Definition: X86Subtarget.h:381
bool isKnownWindowsMSVCEnvironment() const
Definition: Triple.h:436
bool HasFMA4
Target has 4-operand fused multiply-add.
Definition: X86Subtarget.h:96
bool HasRTM
Processor has RTM instructions.
Definition: X86Subtarget.h:126
bool isWindowsItaniumEnvironment() const
Definition: Triple.h:440
bool isTargetFreeBSD() const
Definition: X86Subtarget.h:387
The C convention as implemented on Windows/x86-64.
Definition: CallingConv.h:143
Primary interface to the complete machine description for the target machine.
bool HasVLX
Processor has AVX-512 Vector Length eXtenstions.
Definition: X86Subtarget.h:209
const char * getBZeroEntry() const
This function returns the name of a function which has an interface like the non-standard bzero funct...
bool padShortFunctions() const
Definition: X86Subtarget.h:367
bool hasERI() const
Definition: X86Subtarget.h:374
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
bool callRegIndirect() const
Definition: X86Subtarget.h:368
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:40
bool HasRDSEED
Processor has RDSEED instructions.
Definition: X86Subtarget.h:141
AntiDepBreakMode getAntiDepBreakMode() const override
Definition: X86Subtarget.h:506
unsigned stackAlignment
The minimum alignment known to hold of the stack frame on entry to the function and which must be mai...
Definition: X86Subtarget.h:219
bool hasFMA() const
Definition: X86Subtarget.h:340
bool isTargetNaCl32() const
Definition: X86Subtarget.h:398
bool isPS4() const
Tests whether the target is the PS4 platform.
Definition: Triple.h:501
Triple TargetTriple
What processor and OS we're targeting.
Definition: X86Subtarget.h:226
bool IsUAMemFast
True if unaligned memory access is fast.
Definition: X86Subtarget.h:150
bool HasMOVBE
True if the processor has the MOVBE instruction.
Definition: X86Subtarget.h:105
bool PadShortFunctions
True if the short functions should be padded to prevent a stall when returning too early...
Definition: X86Subtarget.h:177
bool hasAVX() const
Definition: X86Subtarget.h:329
bool hasSlowDivide32() const
Definition: X86Subtarget.h:365
bool isTargetNaCl() const
Definition: X86Subtarget.h:397
bool HasSlowDivide64
True if 16-bit divides are significantly faster than 64-bit divisions and should be used when possibl...
Definition: X86Subtarget.h:173