LLVM  3.7.0
llvm::MipsTargetLowering Member List

This is the complete list of members for llvm::MipsTargetLowering, including all inherited members.

ABIllvm::MipsTargetLoweringprotected
addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth)llvm::TargetLoweringBaseinlineprotected
AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)llvm::TargetLoweringBaseinlineprotected
addRegisterClass(MVT VT, const TargetRegisterClass *RC)llvm::TargetLoweringBaseinlineprotected
AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const llvm::TargetLoweringvirtual
allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace=0, unsigned Align=1, bool *=nullptr) const llvm::TargetLoweringBaseinlinevirtual
allowTruncateForTailCall(Type *, Type *) const llvm::TargetLoweringBaseinlinevirtual
ArgListTy typedefllvm::TargetLowering
AsmOperandInfoVector typedefllvm::TargetLowering
AtomicRMWExpansionKind enum namellvm::TargetLoweringBase
BooleanContent enum namellvm::TargetLoweringBase
BuildSDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode * > *Created) const llvm::TargetLowering
BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, std::vector< SDNode * > *Created) const llvm::TargetLoweringinlinevirtual
BuildUDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode * > *Created) const llvm::TargetLowering
C_Memory enum valuellvm::TargetLowering
C_Other enum valuellvm::TargetLowering
C_Register enum valuellvm::TargetLowering
C_RegisterClass enum valuellvm::TargetLowering
C_Unknown enum valuellvm::TargetLowering
canCombineStoreAndExtract(Type *VectorTy, Value *Idx, unsigned &Cost) const llvm::TargetLoweringBaseinlinevirtual
canOpTrap(unsigned Op, EVT VT) const llvm::TargetLoweringBasevirtual
clearOperationActions()llvm::TargetLoweringBaseinlineprotected
clearRegisterClasses()llvm::TargetLoweringBaseinlineprotected
combineRepeatedFPDivisors(unsigned NumUsers) const llvm::TargetLoweringinlinevirtual
ComputeConstraintToUse(AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=nullptr) const llvm::TargetLoweringvirtual
computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth=0) const llvm::TargetLoweringvirtual
ComputeNumSignBitsForTargetNode(SDValue Op, const SelectionDAG &DAG, unsigned Depth=0) const llvm::TargetLoweringvirtual
computeRegisterProperties(const TargetRegisterInfo *TRI)llvm::TargetLoweringBaseprotected
ConstraintType enum namellvm::TargetLowering
ConstraintWeight enum namellvm::TargetLowering
create(const MipsTargetMachine &TM, const MipsSubtarget &STI)llvm::MipsTargetLoweringstatic
createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const overridellvm::MipsTargetLoweringvirtual
Custom enum valuellvm::TargetLoweringBase
CW_Best enum valuellvm::TargetLowering
CW_Better enum valuellvm::TargetLowering
CW_Constant enum valuellvm::TargetLowering
CW_Default enum valuellvm::TargetLowering
CW_Good enum valuellvm::TargetLowering
CW_Invalid enum valuellvm::TargetLowering
CW_Memory enum valuellvm::TargetLowering
CW_Okay enum valuellvm::TargetLowering
CW_Register enum valuellvm::TargetLowering
CW_SpecificReg enum valuellvm::TargetLowering
EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const overridellvm::MipsTargetLoweringvirtual
emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord, bool IsStore, bool IsLoad) const llvm::TargetLoweringBaseinlinevirtual
emitLoadLinked(IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const llvm::TargetLoweringBaseinlinevirtual
emitPatchPoint(MachineInstr *MI, MachineBasicBlock *MBB) const llvm::TargetLoweringBaseprotected
emitStoreConditional(IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const llvm::TargetLoweringBaseinlinevirtual
emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord, bool IsStore, bool IsLoad) const llvm::TargetLoweringBaseinlinevirtual
enableAggressiveFMAFusion(EVT VT) const llvm::TargetLoweringBaseinlinevirtual
EnableExtLdPromotionllvm::TargetLoweringBaseprotected
enableExtLdPromotion() const llvm::TargetLoweringBaseinline
Expand enum valuellvm::TargetLoweringBase
expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const llvm::TargetLowering
ExpandInlineAsm(CallInst *) const llvm::TargetLoweringinlinevirtual
expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT, SelectionDAG &DAG, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) const llvm::TargetLowering
findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const llvm::TargetLoweringBaseprotectedvirtual
functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg) const llvm::TargetLoweringinlinevirtual
getAddrGlobal(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flag, SDValue Chain, const MachinePointerInfo &PtrInfo) const llvm::MipsTargetLoweringinlineprotected
getAddrGlobalLargeGOT(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned HiFlag, unsigned LoFlag, SDValue Chain, const MachinePointerInfo &PtrInfo) const llvm::MipsTargetLoweringinlineprotected
getAddrGPRel(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG) const llvm::MipsTargetLoweringinlineprotected
getAddrLocal(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, bool IsN32OrN64) const llvm::MipsTargetLoweringinlineprotected
GetAddrModeArguments(IntrinsicInst *, SmallVectorImpl< Value * > &, Type *&, unsigned AddrSpace=0) const llvm::TargetLoweringBaseinlinevirtual
getAddrNonPIC(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG) const llvm::MipsTargetLoweringinlineprotected
getBooleanContents(bool isVec, bool isFloat) const llvm::TargetLoweringBaseinline
getBooleanContents(EVT Type) const llvm::TargetLoweringBaseinline
getBypassSlowDivWidths() const llvm::TargetLoweringBaseinline
getByValTypeAlignment(Type *Ty, const DataLayout &DL) const llvm::TargetLoweringBasevirtual
getClearCacheBuiltinName() const llvm::TargetLoweringinlinevirtual
getCmpLibcallCC(RTLIB::Libcall Call) const llvm::TargetLoweringBaseinline
getCmpLibcallReturnType() const llvm::TargetLoweringBasevirtual
getCondCodeAction(ISD::CondCode CC, MVT VT) const llvm::TargetLoweringBaseinline
getExceptionPointerRegister() const llvm::TargetLoweringBaseinline
getExceptionSelectorRegister() const llvm::TargetLoweringBaseinline
getExtendForContent(BooleanContent Content)llvm::TargetLoweringBaseinlinestatic
getGlobalReg(SelectionDAG &DAG, EVT Ty) const llvm::MipsTargetLoweringprotected
getIndexedLoadAction(unsigned IdxMode, MVT VT) const llvm::TargetLoweringBaseinline
getIndexedStoreAction(unsigned IdxMode, MVT VT) const llvm::TargetLoweringBaseinline
getInsertFencesForAtomic() const llvm::TargetLoweringBaseinline
getJumpBufAlignment() const llvm::TargetLoweringBaseinline
getJumpBufSize() const llvm::TargetLoweringBaseinline
getLibcallCallingConv(RTLIB::Libcall Call) const llvm::TargetLoweringBaseinline
getLibcallName(RTLIB::Libcall Call) const llvm::TargetLoweringBaseinline
getLoadExtAction(unsigned ExtType, EVT ValVT, EVT MemVT) const llvm::TargetLoweringBaseinline
getMaxStoresPerMemcpy(bool OptSize) const llvm::TargetLoweringBaseinline
getMaxStoresPerMemmove(bool OptSize) const llvm::TargetLoweringBaseinline
getMaxStoresPerMemset(bool OptSize) const llvm::TargetLoweringBaseinline
getMaxSupportedInterleaveFactor() const llvm::TargetLoweringBaseinlinevirtual
getMinFunctionAlignment() const llvm::TargetLoweringBaseinline
getMinimumJumpTableEntries() const llvm::TargetLoweringBaseinline
getMinStackArgumentAlignment() const llvm::TargetLoweringBaseinline
getMultipleConstraintMatchWeight(AsmOperandInfo &info, int maIndex) const llvm::TargetLoweringvirtual
getNumRegisters(LLVMContext &Context, EVT VT) const llvm::TargetLoweringBaseinline
getOperationAction(unsigned Op, EVT VT) const llvm::TargetLoweringBaseinline
getOpndList(SmallVectorImpl< SDValue > &Ops, std::deque< std::pair< unsigned, SDValue > > &RegsToPass, bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const llvm::MipsTargetLoweringprotectedvirtual
getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const llvm::TargetLoweringvirtual
getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const llvm::TargetLoweringvirtual
getPointerTy(const DataLayout &DL, uint32_t AS=0) const llvm::TargetLoweringBaseinline
getPostIndexedAddressParts(SDNode *, SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const llvm::TargetLoweringinlinevirtual
getPreferredVectorAction(EVT VT) const llvm::TargetLoweringBaseinlinevirtual
getPrefFunctionAlignment() const llvm::TargetLoweringBaseinline
getPrefLoopAlignment(MachineLoop *ML=nullptr) const llvm::TargetLoweringBaseinlinevirtual
getPreIndexedAddressParts(SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const llvm::TargetLoweringinlinevirtual
getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI, unsigned &RefinementSteps) const llvm::TargetLoweringinlinevirtual
getRegClassFor(MVT VT) const llvm::TargetLoweringBaseinlinevirtual
getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const overridellvm::MipsTargetLoweringvirtual
getRegisterType(MVT VT) const llvm::TargetLoweringBaseinline
getRegisterType(LLVMContext &Context, EVT VT) const llvm::TargetLoweringBaseinline
getRepRegClassCostFor(MVT VT) const llvm::TargetLoweringBaseinlinevirtual
getRepRegClassFor(MVT VT) const llvm::TargetLoweringBaseinlinevirtual
getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI, unsigned &RefinementSteps, bool &UseOneConstNR) const llvm::TargetLoweringinlinevirtual
getScalarShiftAmountTy(const DataLayout &, EVT) const overridellvm::MipsTargetLoweringinlinevirtual
getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS=0) const llvm::TargetLoweringBaseinlinevirtual
getSchedulingPreference() const llvm::TargetLoweringBaseinline
getSchedulingPreference(SDNode *) const llvm::TargetLoweringBaseinlinevirtual
getScratchRegisters(CallingConv::ID CC) const llvm::TargetLoweringinlinevirtual
getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const overridellvm::MipsTargetLoweringvirtual
getShiftAmountTy(EVT LHSTy, const DataLayout &DL) const llvm::TargetLoweringBase
getSimpleValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const llvm::TargetLoweringBaseinline
getStackCookieLocation(unsigned &, unsigned &) const llvm::TargetLoweringBaseinlinevirtual
getStackPointerRegisterToSaveRestore() const llvm::TargetLoweringBaseinline
getTargetMachine() const llvm::TargetLoweringBaseinline
getTargetNodeName(unsigned Opcode) const overridellvm::MipsTargetLoweringvirtual
getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, unsigned) const llvm::TargetLoweringBaseinlinevirtual
getTruncStoreAction(EVT ValVT, EVT MemVT) const llvm::TargetLoweringBaseinline
getTypeAction(LLVMContext &Context, EVT VT) const llvm::TargetLoweringBaseinline
getTypeAction(MVT VT) const llvm::TargetLoweringBaseinline
getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT, ISD::NodeType) const llvm::TargetLoweringinlinevirtual
getTypeLegalizationCost(const DataLayout &DL, Type *Ty) const llvm::TargetLoweringBase
getTypeToExpandTo(LLVMContext &Context, EVT VT) const llvm::TargetLoweringBaseinline
getTypeToPromoteTo(unsigned Op, MVT VT) const llvm::TargetLoweringBaseinline
getTypeToTransformTo(LLVMContext &Context, EVT VT) const llvm::TargetLoweringBaseinline
getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const llvm::TargetLoweringBaseinline
getValueTypeActions() const llvm::TargetLoweringBaseinline
getVectorIdxTy(const DataLayout &DL) const llvm::TargetLoweringBaseinlinevirtual
getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const llvm::TargetLoweringBase
HandleByVal(CCState *, unsigned &, unsigned) const overridellvm::MipsTargetLoweringvirtual
hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const llvm::TargetLoweringBaseinline
hasExtractBitsInsn() const llvm::TargetLoweringBaseinline
hasFloatingPointExceptions() const llvm::TargetLoweringBaseinline
hasLoadLinkedStoreConditional() const llvm::TargetLoweringBaseinlinevirtual
hasMultipleConditionRegisters() const llvm::TargetLoweringBaseinline
hasPairedLoad(Type *, unsigned &) const llvm::TargetLoweringBaseinlinevirtual
hasPairedLoad(EVT, unsigned &) const llvm::TargetLoweringBaseinlinevirtual
hasTargetDAGCombine(ISD::NodeType NT) const llvm::TargetLoweringBaseinline
initActions()llvm::TargetLoweringBaseprotected
InstructionOpcodeToISD(unsigned Opcode) const llvm::TargetLoweringBase
isCheapToSpeculateCtlz() const llvm::TargetLoweringBaseinlinevirtual
isCheapToSpeculateCttz() const llvm::TargetLoweringBaseinlinevirtual
isCondCodeLegal(ISD::CondCode CC, MVT VT) const llvm::TargetLoweringBaseinline
isConstFalseVal(const SDNode *N) const llvm::TargetLowering
isConstTrueVal(const SDNode *N) const llvm::TargetLowering
isDesirableToCommuteWithShift(const SDNode *N) const llvm::TargetLoweringinlinevirtual
IsDesirableToPromoteOp(SDValue, EVT &) const llvm::TargetLoweringinlinevirtual
isDesirableToTransformToIntegerOp(unsigned, EVT) const llvm::TargetLoweringinlinevirtual
isExtFree(const Instruction *I) const llvm::TargetLoweringBaseinline
isExtFreeImpl(const Instruction *I) const llvm::TargetLoweringBaseinlineprotectedvirtual
isExtractSubvectorCheap(EVT ResVT, unsigned Index) const llvm::TargetLoweringBaseinlinevirtual
isFAbsFree(EVT VT) const llvm::TargetLoweringBaseinlinevirtual
isFMAFasterThanFMulAndFAdd(EVT) const llvm::TargetLoweringBaseinlinevirtual
isFNegFree(EVT VT) const llvm::TargetLoweringBaseinlinevirtual
isFPExtFree(EVT VT) const llvm::TargetLoweringBaseinlinevirtual
isFsqrtCheap() const llvm::TargetLoweringBaseinline
isGAPlusOffset(SDNode *N, const GlobalValue *&GA, int64_t &Offset) const llvm::TargetLoweringvirtual
isIndexedLoadLegal(unsigned IdxMode, EVT VT) const llvm::TargetLoweringBaseinline
isIndexedStoreLegal(unsigned IdxMode, EVT VT) const llvm::TargetLoweringBaseinline
isInTailCallPosition(SelectionDAG &DAG, SDNode *Node, SDValue &Chain) const llvm::TargetLowering
isIntDivCheap() const llvm::TargetLoweringBaseinline
isJumpExpensive() const llvm::TargetLoweringBaseinline
isLegalAddImmediate(int64_t) const llvm::TargetLoweringBaseinlinevirtual
isLegalICmpImmediate(int64_t) const llvm::TargetLoweringBaseinlinevirtual
isLegalRC(const TargetRegisterClass *RC) const llvm::TargetLoweringBaseprotected
isLoadBitCastBeneficial(EVT, EVT) const llvm::TargetLoweringBaseinlinevirtual
isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const llvm::TargetLoweringBaseinline
isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const llvm::TargetLoweringBaseinline
isMaskAndBranchFoldingLegal() const llvm::TargetLoweringBaseinline
isNarrowingProfitable(EVT, EVT) const llvm::TargetLoweringBaseinlinevirtual
isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const llvm::TargetLoweringBaseinlinevirtual
isOperationExpand(unsigned Op, EVT VT) const llvm::TargetLoweringBaseinline
isOperationLegal(unsigned Op, EVT VT) const llvm::TargetLoweringBaseinline
isOperationLegalOrCustom(unsigned Op, EVT VT) const llvm::TargetLoweringBaseinline
isOperationLegalOrPromote(unsigned Op, EVT VT) const llvm::TargetLoweringBaseinline
isPow2SDivCheap() const llvm::TargetLoweringBaseinline
isPredictableSelectExpensive() const llvm::TargetLoweringBaseinline
isProfitableToHoist(Instruction *I) const llvm::TargetLoweringBaseinlinevirtual
isSafeMemOpType(MVT) const llvm::TargetLoweringBaseinlinevirtual
isSelectExpensive() const llvm::TargetLoweringBaseinline
isSelectSupported(SelectSupportKind) const llvm::TargetLoweringBaseinlinevirtual
isShuffleMaskLegal(const SmallVectorImpl< int > &, EVT) const llvm::TargetLoweringBaseinlinevirtual
isSlowDivBypassed() const llvm::TargetLoweringBaseinline
isTruncateFree(Type *, Type *) const llvm::TargetLoweringBaseinlinevirtual
isTruncateFree(EVT, EVT) const llvm::TargetLoweringBaseinlinevirtual
isTruncStoreLegal(EVT ValVT, EVT MemVT) const llvm::TargetLoweringBaseinline
isTypeDesirableForOp(unsigned, EVT VT) const llvm::TargetLoweringinlinevirtual
isTypeLegal(EVT VT) const llvm::TargetLoweringBaseinline
isUsedByReturnOnly(SDNode *, SDValue &) const llvm::TargetLoweringinlinevirtual
isVectorClearMaskLegal(const SmallVectorImpl< int > &, EVT) const llvm::TargetLoweringBaseinlinevirtual
isVectorLoadExtDesirable(SDValue ExtVal) const llvm::TargetLoweringBaseinlinevirtual
isVectorShiftByScalarCheap(Type *Ty) const llvm::TargetLoweringBaseinlinevirtual
isZExtFree(Type *, Type *) const llvm::TargetLoweringBaseinlinevirtual
isZExtFree(EVT, EVT) const llvm::TargetLoweringBaseinlinevirtual
isZExtFree(SDValue Val, EVT VT2) const llvm::TargetLoweringBaseinlinevirtual
Legal enum valuellvm::TargetLoweringBase
LegalizeAction enum namellvm::TargetLoweringBase
LegalizeKind typedefllvm::TargetLoweringBase
LegalizeTypeAction enum namellvm::TargetLoweringBase
LowerCallTo(CallLoweringInfo &CLI) const llvm::TargetLowering
LowerCustomJumpTableEntry(const MachineJumpTableInfo *, const MachineBasicBlock *, unsigned, MCContext &) const llvm::TargetLoweringinlinevirtual
lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) const llvm::TargetLoweringBaseinlinevirtual
lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const llvm::TargetLoweringBaseinlinevirtual
lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const llvm::TargetLoweringBaseinlinevirtual
lowerLOAD(SDValue Op, SelectionDAG &DAG) const llvm::MipsTargetLoweringprotected
LowerOperation(SDValue Op, SelectionDAG &DAG) const overridellvm::MipsTargetLoweringvirtual
LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const overridellvm::MipsTargetLoweringvirtual
lowerSTORE(SDValue Op, SelectionDAG &DAG) const llvm::MipsTargetLoweringprotected
LowerXConstraint(EVT ConstraintVT) const llvm::TargetLoweringvirtual
makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops, unsigned NumOps, bool isSigned, SDLoc dl, bool doesNotReturn=false, bool isReturnValueUsed=true) const llvm::TargetLowering
MaskAndBranchFoldingIsLegalllvm::TargetLoweringBaseprotected
MaxStoresPerMemcpyllvm::TargetLoweringBaseprotected
MaxStoresPerMemcpyOptSizellvm::TargetLoweringBaseprotected
MaxStoresPerMemmovellvm::TargetLoweringBaseprotected
MaxStoresPerMemmoveOptSizellvm::TargetLoweringBaseprotected
MaxStoresPerMemsetllvm::TargetLoweringBaseprotected
MaxStoresPerMemsetOptSizellvm::TargetLoweringBaseprotected
mayBeEmittedAsTailCall(CallInst *) const llvm::TargetLoweringinlinevirtual
MipsTargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)llvm::MipsTargetLoweringexplicit
ParseConstraints(const DataLayout &DL, const TargetRegisterInfo *TRI, ImmutableCallSite CS) const llvm::TargetLoweringvirtual
PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const overridellvm::MipsTargetLoweringvirtual
PredictableSelectIsExpensivellvm::TargetLoweringBaseprotected
prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL, SelectionDAG &DAG) const llvm::TargetLoweringinlinevirtual
Promote enum valuellvm::TargetLoweringBase
ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const overridellvm::MipsTargetLoweringvirtual
ScalarCondVectorVal enum valuellvm::TargetLoweringBase
ScalarValSelect enum valuellvm::TargetLoweringBase
SelectSupportKind enum namellvm::TargetLoweringBase
setBooleanContents(BooleanContent Ty)llvm::TargetLoweringBaseinlineprotected
setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy)llvm::TargetLoweringBaseinlineprotected
setBooleanVectorContents(BooleanContent Ty)llvm::TargetLoweringBaseinlineprotected
setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC)llvm::TargetLoweringBaseinline
setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setExceptionPointerRegister(unsigned R)llvm::TargetLoweringBaseinlineprotected
setExceptionSelectorRegister(unsigned R)llvm::TargetLoweringBaseinlineprotected
setFsqrtIsCheap(bool isCheap=true)llvm::TargetLoweringBaseinlineprotected
setHasExtractBitsInsn(bool hasExtractInsn=true)llvm::TargetLoweringBaseinlineprotected
setHasFloatingPointExceptions(bool FPExceptions=true)llvm::TargetLoweringBaseinlineprotected
setHasMultipleConditionRegisters(bool hasManyRegs=true)llvm::TargetLoweringBaseinlineprotected
setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setInsertFencesForAtomic(bool fence)llvm::TargetLoweringBaseinlineprotected
setIntDivIsCheap(bool isCheap=true)llvm::TargetLoweringBaseinlineprotected
setJumpBufAlignment(unsigned Align)llvm::TargetLoweringBaseinlineprotected
setJumpBufSize(unsigned Size)llvm::TargetLoweringBaseinlineprotected
setJumpIsExpensive(bool isExpensive=true)llvm::TargetLoweringBaseprotected
setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)llvm::TargetLoweringBaseinline
setLibcallName(RTLIB::Libcall Call, const char *Name)llvm::TargetLoweringBaseinline
setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setMinFunctionAlignment(unsigned Align)llvm::TargetLoweringBaseinlineprotected
setMinimumJumpTableEntries(int Val)llvm::TargetLoweringBaseinlineprotected
setMinStackArgumentAlignment(unsigned Align)llvm::TargetLoweringBaseinlineprotected
setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setPow2SDivIsCheap(bool isCheap=true)llvm::TargetLoweringBaseinlineprotected
setPrefFunctionAlignment(unsigned Align)llvm::TargetLoweringBaseinlineprotected
setPrefLoopAlignment(unsigned Align)llvm::TargetLoweringBaseinlineprotected
setSchedulingPreference(Sched::Preference Pref)llvm::TargetLoweringBaseinlineprotected
setSelectIsExpensive(bool isExpensive=true)llvm::TargetLoweringBaseinlineprotected
setStackPointerRegisterToSaveRestore(unsigned R)llvm::TargetLoweringBaseinlineprotected
setTargetDAGCombine(ISD::NodeType NT)llvm::TargetLoweringBaseinlineprotected
setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setUseUnderscoreLongJmp(bool Val)llvm::TargetLoweringBaseinlineprotected
setUseUnderscoreSetJmp(bool Val)llvm::TargetLoweringBaseinlineprotected
shouldAlignPointerArgs(CallInst *, unsigned &, unsigned &) const llvm::TargetLoweringBaseinlinevirtual
shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const llvm::TargetLoweringBaseinlinevirtual
shouldExpandAtomicLoadInIR(LoadInst *LI) const llvm::TargetLoweringBaseinlinevirtual
shouldExpandAtomicRMWInIR(AtomicRMWInst *) const llvm::TargetLoweringBaseinlinevirtual
shouldExpandAtomicStoreInIR(StoreInst *SI) const llvm::TargetLoweringBaseinlinevirtual
shouldExpandBuildVectorWithShuffles(EVT, unsigned DefinedValues) const llvm::TargetLoweringBaseinlinevirtual
shouldNormalizeToSelectSequence(LLVMContext &Context, EVT VT) const llvm::TargetLoweringBaseinlinevirtual
shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const llvm::TargetLoweringBaseinlinevirtual
ShouldShrinkFPConstant(EVT) const llvm::TargetLoweringBaseinlinevirtual
SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, APInt &KnownZero, APInt &KnownOne, TargetLoweringOpt &TLO, unsigned Depth=0) const llvm::TargetLowering
SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, SDLoc dl) const llvm::TargetLowering
softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, SDLoc DL) const llvm::TargetLowering
storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem, unsigned AddrSpace) const llvm::TargetLoweringBaseinlinevirtual
Subtargetllvm::MipsTargetLoweringprotected
TargetLowering(const TargetMachine &TM)llvm::TargetLoweringexplicit
TargetLoweringBase(const TargetMachine &TM)llvm::TargetLoweringBaseexplicit
TypeExpandFloat enum valuellvm::TargetLoweringBase
TypeExpandInteger enum valuellvm::TargetLoweringBase
TypeLegal enum valuellvm::TargetLoweringBase
TypePromoteFloat enum valuellvm::TargetLoweringBase
TypePromoteInteger enum valuellvm::TargetLoweringBase
TypeScalarizeVector enum valuellvm::TargetLoweringBase
TypeSoftenFloat enum valuellvm::TargetLoweringBase
TypeSplitVector enum valuellvm::TargetLoweringBase
TypeWidenVector enum valuellvm::TargetLoweringBase
UndefinedBooleanContent enum valuellvm::TargetLoweringBase
useLoadStackGuardNode() const llvm::TargetLoweringinlinevirtual
usesUnderscoreLongJmp() const llvm::TargetLoweringBaseinline
usesUnderscoreSetJmp() const llvm::TargetLoweringBaseinline
VectorMaskSelect enum valuellvm::TargetLoweringBase
verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const llvm::TargetLowering
ZeroOrNegativeOneBooleanContent enum valuellvm::TargetLoweringBase
ZeroOrOneBooleanContent enum valuellvm::TargetLoweringBase
~TargetLoweringBase()llvm::TargetLoweringBaseinlinevirtual