LLVM  3.7.0
HexagonNewValueJump.cpp
Go to the documentation of this file.
1 //===----- HexagonNewValueJump.cpp - Hexagon Backend New Value Jump -------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This implements NewValueJump pass in Hexagon.
11 // Ideally, we should merge this as a Peephole pass prior to register
12 // allocation, but because we have a spill in between the feeder and new value
13 // jump instructions, we are forced to write after register allocation.
14 // Having said that, we should re-attempt to pull this earlier at some point
15 // in future.
16 
17 // The basic approach looks for sequence of predicated jump, compare instruciton
18 // that genereates the predicate and, the feeder to the predicate. Once it finds
19 // all, it collapses compare and jump instruction into a new valu jump
20 // intstructions.
21 //
22 //
23 //===----------------------------------------------------------------------===//
24 #include "llvm/PassSupport.h"
25 #include "Hexagon.h"
26 #include "HexagonInstrInfo.h"
28 #include "HexagonRegisterInfo.h"
29 #include "HexagonSubtarget.h"
30 #include "HexagonTargetMachine.h"
31 #include "llvm/ADT/DenseMap.h"
32 #include "llvm/ADT/Statistic.h"
38 #include "llvm/CodeGen/Passes.h"
41 #include "llvm/Support/Compiler.h"
42 #include "llvm/Support/Debug.h"
47 #include <map>
48 using namespace llvm;
49 
50 #define DEBUG_TYPE "hexagon-nvj"
51 
52 STATISTIC(NumNVJGenerated, "Number of New Value Jump Instructions created");
53 
54 static cl::opt<int>
55 DbgNVJCount("nvj-count", cl::init(-1), cl::Hidden, cl::desc(
56  "Maximum number of predicated jumps to be converted to New Value Jump"));
57 
58 static cl::opt<bool> DisableNewValueJumps("disable-nvjump", cl::Hidden,
59  cl::ZeroOrMore, cl::init(false),
60  cl::desc("Disable New Value Jumps"));
61 
62 namespace llvm {
65 }
66 
67 
68 namespace {
69  struct HexagonNewValueJump : public MachineFunctionPass {
70  const HexagonInstrInfo *QII;
71  const HexagonRegisterInfo *QRI;
72 
73  public:
74  static char ID;
75 
76  HexagonNewValueJump() : MachineFunctionPass(ID) {
78  }
79 
80  void getAnalysisUsage(AnalysisUsage &AU) const override {
83  }
84 
85  const char *getPassName() const override {
86  return "Hexagon NewValueJump";
87  }
88 
89  bool runOnMachineFunction(MachineFunction &Fn) override;
90 
91  private:
92  /// \brief A handle to the branch probability pass.
93  const MachineBranchProbabilityInfo *MBPI;
94 
95  };
96 
97 } // end of anonymous namespace
98 
100 
101 INITIALIZE_PASS_BEGIN(HexagonNewValueJump, "hexagon-nvj",
102  "Hexagon NewValueJump", false, false)
104 INITIALIZE_PASS_END(HexagonNewValueJump, "hexagon-nvj",
105  "Hexagon NewValueJump", false, false)
106 
107 
108 // We have identified this II could be feeder to NVJ,
109 // verify that it can be.
112  MachineBasicBlock::iterator II,
113  MachineBasicBlock::iterator end,
114  MachineBasicBlock::iterator skip,
115  MachineFunction &MF) {
116 
117  // Predicated instruction can not be feeder to NVJ.
118  if (QII->isPredicated(II))
119  return false;
120 
121  // Bail out if feederReg is a paired register (double regs in
122  // our case). One would think that we can check to see if a given
123  // register cmpReg1 or cmpReg2 is a sub register of feederReg
124  // using -- if (QRI->isSubRegister(feederReg, cmpReg1) logic
125  // before the callsite of this function
126  // But we can not as it comes in the following fashion.
127  // %D0<def> = Hexagon_S2_lsr_r_p %D0<kill>, %R2<kill>
128  // %R0<def> = KILL %R0, %D0<imp-use,kill>
129  // %P0<def> = CMPEQri %R0<kill>, 0
130  // Hence, we need to check if it's a KILL instruction.
131  if (II->getOpcode() == TargetOpcode::KILL)
132  return false;
133 
134 
135  // Make sure there there is no 'def' or 'use' of any of the uses of
136  // feeder insn between it's definition, this MI and jump, jmpInst
137  // skipping compare, cmpInst.
138  // Here's the example.
139  // r21=memub(r22+r24<<#0)
140  // p0 = cmp.eq(r21, #0)
141  // r4=memub(r3+r21<<#0)
142  // if (p0.new) jump:t .LBB29_45
143  // Without this check, it will be converted into
144  // r4=memub(r3+r21<<#0)
145  // r21=memub(r22+r24<<#0)
146  // p0 = cmp.eq(r21, #0)
147  // if (p0.new) jump:t .LBB29_45
148  // and result WAR hazards if converted to New Value Jump.
149 
150  for (unsigned i = 0; i < II->getNumOperands(); ++i) {
151  if (II->getOperand(i).isReg() &&
152  (II->getOperand(i).isUse() || II->getOperand(i).isDef())) {
153  MachineBasicBlock::iterator localII = II;
154  ++localII;
155  unsigned Reg = II->getOperand(i).getReg();
156  for (MachineBasicBlock::iterator localBegin = localII;
157  localBegin != end; ++localBegin) {
158  if (localBegin == skip ) continue;
159  // Check for Subregisters too.
160  if (localBegin->modifiesRegister(Reg, TRI) ||
161  localBegin->readsRegister(Reg, TRI))
162  return false;
163  }
164  }
165  }
166  return true;
167 }
168 
169 // These are the common checks that need to performed
170 // to determine if
171 // 1. compare instruction can be moved before jump.
172 // 2. feeder to the compare instruction can be moved before jump.
173 static bool commonChecksToProhibitNewValueJump(bool afterRA,
175 
176  // If store in path, bail out.
177  if (MII->getDesc().mayStore())
178  return false;
179 
180  // if call in path, bail out.
181  if (MII->getOpcode() == Hexagon::J2_call)
182  return false;
183 
184  // if NVJ is running prior to RA, do the following checks.
185  if (!afterRA) {
186  // The following Target Opcode instructions are spurious
187  // to new value jump. If they are in the path, bail out.
188  // KILL sets kill flag on the opcode. It also sets up a
189  // single register, out of pair.
190  // %D0<def> = Hexagon_S2_lsr_r_p %D0<kill>, %R2<kill>
191  // %R0<def> = KILL %R0, %D0<imp-use,kill>
192  // %P0<def> = CMPEQri %R0<kill>, 0
193  // PHI can be anything after RA.
194  // COPY can remateriaze things in between feeder, compare and nvj.
195  if (MII->getOpcode() == TargetOpcode::KILL ||
196  MII->getOpcode() == TargetOpcode::PHI ||
197  MII->getOpcode() == TargetOpcode::COPY)
198  return false;
199 
200  // The following pseudo Hexagon instructions sets "use" and "def"
201  // of registers by individual passes in the backend. At this time,
202  // we don't know the scope of usage and definitions of these
203  // instructions.
204  if (MII->getOpcode() == Hexagon::LDriw_pred ||
205  MII->getOpcode() == Hexagon::STriw_pred)
206  return false;
207  }
208 
209  return true;
210 }
211 
213  const TargetRegisterInfo *TRI,
215  unsigned pReg,
216  bool secondReg,
217  bool optLocation,
219  MachineFunction &MF) {
220 
221  MachineInstr *MI = II;
222 
223  // If the second operand of the compare is an imm, make sure it's in the
224  // range specified by the arch.
225  if (!secondReg) {
226  int64_t v = MI->getOperand(2).getImm();
227 
228  if (!(isUInt<5>(v) ||
229  ((MI->getOpcode() == Hexagon::C2_cmpeqi ||
230  MI->getOpcode() == Hexagon::C2_cmpgti) &&
231  (v == -1))))
232  return false;
233  }
234 
235  unsigned cmpReg1, cmpOp2 = 0; // cmpOp2 assignment silences compiler warning.
236  cmpReg1 = MI->getOperand(1).getReg();
237 
238  if (secondReg) {
239  cmpOp2 = MI->getOperand(2).getReg();
240 
241  // Make sure that that second register is not from COPY
242  // At machine code level, we don't need this, but if we decide
243  // to move new value jump prior to RA, we would be needing this.
244  MachineRegisterInfo &MRI = MF.getRegInfo();
245  if (secondReg && !TargetRegisterInfo::isPhysicalRegister(cmpOp2)) {
246  MachineInstr *def = MRI.getVRegDef(cmpOp2);
247  if (def->getOpcode() == TargetOpcode::COPY)
248  return false;
249  }
250  }
251 
252  // Walk the instructions after the compare (predicate def) to the jump,
253  // and satisfy the following conditions.
254  ++II ;
255  for (MachineBasicBlock::iterator localII = II; localII != end;
256  ++localII) {
257 
258  // Check 1.
259  // If "common" checks fail, bail out.
260  if (!commonChecksToProhibitNewValueJump(optLocation, localII))
261  return false;
262 
263  // Check 2.
264  // If there is a def or use of predicate (result of compare), bail out.
265  if (localII->modifiesRegister(pReg, TRI) ||
266  localII->readsRegister(pReg, TRI))
267  return false;
268 
269  // Check 3.
270  // If there is a def of any of the use of the compare (operands of compare),
271  // bail out.
272  // Eg.
273  // p0 = cmp.eq(r2, r0)
274  // r2 = r4
275  // if (p0.new) jump:t .LBB28_3
276  if (localII->modifiesRegister(cmpReg1, TRI) ||
277  (secondReg && localII->modifiesRegister(cmpOp2, TRI)))
278  return false;
279  }
280  return true;
281 }
282 
283 // Given a compare operator, return a matching New Value Jump
284 // compare operator. Make sure that MI here is included in
285 // HexagonInstrInfo.cpp::isNewValueJumpCandidate
286 static unsigned getNewValueJumpOpcode(MachineInstr *MI, int reg,
287  bool secondRegNewified,
288  MachineBasicBlock *jmpTarget,
290  *MBPI) {
291  bool taken = false;
292  MachineBasicBlock *Src = MI->getParent();
293  const BranchProbability Prediction =
294  MBPI->getEdgeProbability(Src, jmpTarget);
295 
296  if (Prediction >= BranchProbability(1,2))
297  taken = true;
298 
299  switch (MI->getOpcode()) {
300  case Hexagon::C2_cmpeq:
301  return taken ? Hexagon::J4_cmpeq_t_jumpnv_t
302  : Hexagon::J4_cmpeq_t_jumpnv_nt;
303 
304  case Hexagon::C2_cmpeqi: {
305  if (reg >= 0)
306  return taken ? Hexagon::J4_cmpeqi_t_jumpnv_t
307  : Hexagon::J4_cmpeqi_t_jumpnv_nt;
308  else
309  return taken ? Hexagon::J4_cmpeqn1_t_jumpnv_t
310  : Hexagon::J4_cmpeqn1_t_jumpnv_nt;
311  }
312 
313  case Hexagon::C2_cmpgt: {
314  if (secondRegNewified)
315  return taken ? Hexagon::J4_cmplt_t_jumpnv_t
316  : Hexagon::J4_cmplt_t_jumpnv_nt;
317  else
318  return taken ? Hexagon::J4_cmpgt_t_jumpnv_t
319  : Hexagon::J4_cmpgt_t_jumpnv_nt;
320  }
321 
322  case Hexagon::C2_cmpgti: {
323  if (reg >= 0)
324  return taken ? Hexagon::J4_cmpgti_t_jumpnv_t
325  : Hexagon::J4_cmpgti_t_jumpnv_nt;
326  else
327  return taken ? Hexagon::J4_cmpgtn1_t_jumpnv_t
328  : Hexagon::J4_cmpgtn1_t_jumpnv_nt;
329  }
330 
331  case Hexagon::C2_cmpgtu: {
332  if (secondRegNewified)
333  return taken ? Hexagon::J4_cmpltu_t_jumpnv_t
334  : Hexagon::J4_cmpltu_t_jumpnv_nt;
335  else
336  return taken ? Hexagon::J4_cmpgtu_t_jumpnv_t
337  : Hexagon::J4_cmpgtu_t_jumpnv_nt;
338  }
339 
340  case Hexagon::C2_cmpgtui:
341  return taken ? Hexagon::J4_cmpgtui_t_jumpnv_t
342  : Hexagon::J4_cmpgtui_t_jumpnv_nt;
343 
344  default:
345  llvm_unreachable("Could not find matching New Value Jump instruction.");
346  }
347  // return *some value* to avoid compiler warning
348  return 0;
349 }
350 
351 bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
352 
353  DEBUG(dbgs() << "********** Hexagon New Value Jump **********\n"
354  << "********** Function: "
355  << MF.getName() << "\n");
356 
357  // If we move NewValueJump before register allocation we'll need live variable
358  // analysis here too.
359 
360  QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo());
361  QRI = static_cast<const HexagonRegisterInfo *>(
363  MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
364 
365  if (DisableNewValueJumps) {
366  return false;
367  }
368 
369  int nvjCount = DbgNVJCount;
370  int nvjGenerated = 0;
371 
372  // Loop through all the bb's of the function
373  for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end();
374  MBBb != MBBe; ++MBBb) {
375  MachineBasicBlock* MBB = MBBb;
376 
377  DEBUG(dbgs() << "** dumping bb ** "
378  << MBB->getNumber() << "\n");
379  DEBUG(MBB->dump());
380  DEBUG(dbgs() << "\n" << "********** dumping instr bottom up **********\n");
381  bool foundJump = false;
382  bool foundCompare = false;
383  bool invertPredicate = false;
384  unsigned predReg = 0; // predicate reg of the jump.
385  unsigned cmpReg1 = 0;
386  int cmpOp2 = 0;
387  bool MO1IsKill = false;
388  bool MO2IsKill = false;
391  MachineInstr *cmpInstr = nullptr, *jmpInstr = nullptr;
392  MachineBasicBlock *jmpTarget = nullptr;
393  bool afterRA = false;
394  bool isSecondOpReg = false;
395  bool isSecondOpNewified = false;
396  // Traverse the basic block - bottom up
397  for (MachineBasicBlock::iterator MII = MBB->end(), E = MBB->begin();
398  MII != E;) {
399  MachineInstr *MI = --MII;
400  if (MI->isDebugValue()) {
401  continue;
402  }
403 
404  if ((nvjCount == 0) || (nvjCount > -1 && nvjCount <= nvjGenerated))
405  break;
406 
407  DEBUG(dbgs() << "Instr: "; MI->dump(); dbgs() << "\n");
408 
409  if (!foundJump &&
410  (MI->getOpcode() == Hexagon::J2_jumpt ||
411  MI->getOpcode() == Hexagon::J2_jumpf ||
412  MI->getOpcode() == Hexagon::J2_jumptnewpt ||
413  MI->getOpcode() == Hexagon::J2_jumptnew ||
414  MI->getOpcode() == Hexagon::J2_jumpfnewpt ||
415  MI->getOpcode() == Hexagon::J2_jumpfnew)) {
416  // This is where you would insert your compare and
417  // instr that feeds compare
418  jmpPos = MII;
419  jmpInstr = MI;
420  predReg = MI->getOperand(0).getReg();
421  afterRA = TargetRegisterInfo::isPhysicalRegister(predReg);
422 
423  // If ifconverter had not messed up with the kill flags of the
424  // operands, the following check on the kill flag would suffice.
425  // if(!jmpInstr->getOperand(0).isKill()) break;
426 
427  // This predicate register is live out out of BB
428  // this would only work if we can actually use Live
429  // variable analysis on phy regs - but LLVM does not
430  // provide LV analysis on phys regs.
431  //if(LVs.isLiveOut(predReg, *MBB)) break;
432 
433  // Get all the successors of this block - which will always
434  // be 2. Check if the predicate register is live in in those
435  // successor. If yes, we can not delete the predicate -
436  // I am doing this only because LLVM does not provide LiveOut
437  // at the BB level.
438  bool predLive = false;
440  SIE = MBB->succ_end(); SI != SIE; ++SI) {
441  MachineBasicBlock* succMBB = *SI;
442  if (succMBB->isLiveIn(predReg)) {
443  predLive = true;
444  }
445  }
446  if (predLive)
447  break;
448 
449  jmpTarget = MI->getOperand(1).getMBB();
450  foundJump = true;
451  if (MI->getOpcode() == Hexagon::J2_jumpf ||
452  MI->getOpcode() == Hexagon::J2_jumpfnewpt ||
453  MI->getOpcode() == Hexagon::J2_jumpfnew) {
454  invertPredicate = true;
455  }
456  continue;
457  }
458 
459  // No new value jump if there is a barrier. A barrier has to be in its
460  // own packet. A barrier has zero operands. We conservatively bail out
461  // here if we see any instruction with zero operands.
462  if (foundJump && MI->getNumOperands() == 0)
463  break;
464 
465  if (foundJump &&
466  !foundCompare &&
467  MI->getOperand(0).isReg() &&
468  MI->getOperand(0).getReg() == predReg) {
469 
470  // Not all compares can be new value compare. Arch Spec: 7.6.1.1
471  if (QII->isNewValueJumpCandidate(MI)) {
472 
473  assert((MI->getDesc().isCompare()) &&
474  "Only compare instruction can be collapsed into New Value Jump");
475  isSecondOpReg = MI->getOperand(2).isReg();
476 
477  if (!canCompareBeNewValueJump(QII, QRI, MII, predReg, isSecondOpReg,
478  afterRA, jmpPos, MF))
479  break;
480 
481  cmpInstr = MI;
482  cmpPos = MII;
483  foundCompare = true;
484 
485  // We need cmpReg1 and cmpOp2(imm or reg) while building
486  // new value jump instruction.
487  cmpReg1 = MI->getOperand(1).getReg();
488  if (MI->getOperand(1).isKill())
489  MO1IsKill = true;
490 
491  if (isSecondOpReg) {
492  cmpOp2 = MI->getOperand(2).getReg();
493  if (MI->getOperand(2).isKill())
494  MO2IsKill = true;
495  } else
496  cmpOp2 = MI->getOperand(2).getImm();
497  continue;
498  }
499  }
500 
501  if (foundCompare && foundJump) {
502 
503  // If "common" checks fail, bail out on this BB.
504  if (!commonChecksToProhibitNewValueJump(afterRA, MII))
505  break;
506 
507  bool foundFeeder = false;
508  MachineBasicBlock::iterator feederPos = MII;
509  if (MI->getOperand(0).isReg() &&
510  MI->getOperand(0).isDef() &&
511  (MI->getOperand(0).getReg() == cmpReg1 ||
512  (isSecondOpReg &&
513  MI->getOperand(0).getReg() == (unsigned) cmpOp2))) {
514 
515  unsigned feederReg = MI->getOperand(0).getReg();
516 
517  // First try to see if we can get the feeder from the first operand
518  // of the compare. If we can not, and if secondOpReg is true
519  // (second operand of the compare is also register), try that one.
520  // TODO: Try to come up with some heuristic to figure out which
521  // feeder would benefit.
522 
523  if (feederReg == cmpReg1) {
524  if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF)) {
525  if (!isSecondOpReg)
526  break;
527  else
528  continue;
529  } else
530  foundFeeder = true;
531  }
532 
533  if (!foundFeeder &&
534  isSecondOpReg &&
535  feederReg == (unsigned) cmpOp2)
536  if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF))
537  break;
538 
539  if (isSecondOpReg) {
540  // In case of CMPLT, or CMPLTU, or EQ with the second register
541  // to newify, swap the operands.
542  if (cmpInstr->getOpcode() == Hexagon::C2_cmpeq &&
543  feederReg == (unsigned) cmpOp2) {
544  unsigned tmp = cmpReg1;
545  bool tmpIsKill = MO1IsKill;
546  cmpReg1 = cmpOp2;
547  MO1IsKill = MO2IsKill;
548  cmpOp2 = tmp;
549  MO2IsKill = tmpIsKill;
550  }
551 
552  // Now we have swapped the operands, all we need to check is,
553  // if the second operand (after swap) is the feeder.
554  // And if it is, make a note.
555  if (feederReg == (unsigned)cmpOp2)
556  isSecondOpNewified = true;
557  }
558 
559  // Now that we are moving feeder close the jump,
560  // make sure we are respecting the kill values of
561  // the operands of the feeder.
562 
563  bool updatedIsKill = false;
564  for (unsigned i = 0; i < MI->getNumOperands(); i++) {
565  MachineOperand &MO = MI->getOperand(i);
566  if (MO.isReg() && MO.isUse()) {
567  unsigned feederReg = MO.getReg();
568  for (MachineBasicBlock::iterator localII = feederPos,
569  end = jmpPos; localII != end; localII++) {
570  MachineInstr *localMI = localII;
571  for (unsigned j = 0; j < localMI->getNumOperands(); j++) {
572  MachineOperand &localMO = localMI->getOperand(j);
573  if (localMO.isReg() && localMO.isUse() &&
574  localMO.isKill() && feederReg == localMO.getReg()) {
575  // We found that there is kill of a use register
576  // Set up a kill flag on the register
577  localMO.setIsKill(false);
578  MO.setIsKill();
579  updatedIsKill = true;
580  break;
581  }
582  }
583  if (updatedIsKill) break;
584  }
585  }
586  if (updatedIsKill) break;
587  }
588 
589  MBB->splice(jmpPos, MI->getParent(), MI);
590  MBB->splice(jmpPos, MI->getParent(), cmpInstr);
591  DebugLoc dl = MI->getDebugLoc();
592  MachineInstr *NewMI;
593 
594  assert((QII->isNewValueJumpCandidate(cmpInstr)) &&
595  "This compare is not a New Value Jump candidate.");
596  unsigned opc = getNewValueJumpOpcode(cmpInstr, cmpOp2,
597  isSecondOpNewified,
598  jmpTarget, MBPI);
599  if (invertPredicate)
600  opc = QII->getInvertedPredicatedOpcode(opc);
601 
602  if (isSecondOpReg)
603  NewMI = BuildMI(*MBB, jmpPos, dl,
604  QII->get(opc))
605  .addReg(cmpReg1, getKillRegState(MO1IsKill))
606  .addReg(cmpOp2, getKillRegState(MO2IsKill))
607  .addMBB(jmpTarget);
608 
609  else if ((cmpInstr->getOpcode() == Hexagon::C2_cmpeqi ||
610  cmpInstr->getOpcode() == Hexagon::C2_cmpgti) &&
611  cmpOp2 == -1 )
612  // Corresponding new-value compare jump instructions don't have the
613  // operand for -1 immediate value.
614  NewMI = BuildMI(*MBB, jmpPos, dl,
615  QII->get(opc))
616  .addReg(cmpReg1, getKillRegState(MO1IsKill))
617  .addMBB(jmpTarget);
618 
619  else
620  NewMI = BuildMI(*MBB, jmpPos, dl,
621  QII->get(opc))
622  .addReg(cmpReg1, getKillRegState(MO1IsKill))
623  .addImm(cmpOp2)
624  .addMBB(jmpTarget);
625 
626  assert(NewMI && "New Value Jump Instruction Not created!");
627  (void)NewMI;
628  if (cmpInstr->getOperand(0).isReg() &&
629  cmpInstr->getOperand(0).isKill())
630  cmpInstr->getOperand(0).setIsKill(false);
631  if (cmpInstr->getOperand(1).isReg() &&
632  cmpInstr->getOperand(1).isKill())
633  cmpInstr->getOperand(1).setIsKill(false);
634  cmpInstr->eraseFromParent();
635  jmpInstr->eraseFromParent();
636  ++nvjGenerated;
637  ++NumNVJGenerated;
638  break;
639  }
640  }
641  }
642  }
643 
644  return true;
645 
646 }
647 
649  return new HexagonNewValueJump();
650 }
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:240
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
STATISTIC(NumFunctions,"Total number of functions")
MachineBasicBlock * getMBB() const
int getNumber() const
getNumber - MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a M...
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:264
A debug info location.
Definition: DebugLoc.h:34
void skip(CollectionType &C)
Definition: YAMLParser.h:358
COPY - Target-independent register copy.
Definition: TargetOpcodes.h:86
AnalysisUsage & addRequired()
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:70
hexagon Hexagon false
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:75
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
Reg
All possible values of the reg field in the ModR/M byte.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:271
INITIALIZE_PASS_BEGIN(HexagonNewValueJump,"hexagon-nvj","Hexagon NewValueJump", false, false) INITIALIZE_PASS_END(HexagonNewValueJump
bool isKill() const
void initializeHexagonNewValueJumpPass(PassRegistry &)
int64_t getImm() const
static bool commonChecksToProhibitNewValueJump(bool afterRA, MachineBasicBlock::iterator MII)
unsigned getKillRegState(bool B)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:267
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:120
bool isDebugValue() const
Definition: MachineInstr.h:748
bundle_iterator< MachineInstr, instr_iterator > iterator
static unsigned getNewValueJumpOpcode(MachineInstr *MI, int reg, bool secondRegNewified, MachineBasicBlock *jmpTarget, const MachineBranchProbabilityInfo *MBPI)
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:325
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
bool isCompare() const
Return true if this instruction is a comparison.
Definition: MCInstrDesc.h:267
Represent the analysis usage information of a pass.
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:294
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
hexagon Hexagon static false bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII, const TargetRegisterInfo *TRI, MachineBasicBlock::iterator II, MachineBasicBlock::iterator end, MachineBasicBlock::iterator skip, MachineFunction &MF)
void setIsKill(bool Val=true)
FunctionPass * createHexagonNewValueJump()
MachineOperand class - Representation of each machine instruction operand.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:123
void dump() const
static cl::opt< int > DbgNVJCount("nvj-count", cl::init(-1), cl::Hidden, cl::desc("Maximum number of predicated jumps to be converted to New Value Jump"))
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:238
KILL - This instruction is a noop that is used only to adjust the liveness of registers.
Definition: TargetOpcodes.h:35
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)
Definition: Metadata.h:1030
Representation of each machine instruction.
Definition: MachineInstr.h:51
static bool isPhysicalRegister(unsigned Reg)
isPhysicalRegister - Return true if the specified register number is in the physical register namespa...
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
bool isLiveIn(unsigned Reg) const
isLiveIn - Return true if the specified register is in the live in set.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII, const TargetRegisterInfo *TRI, MachineBasicBlock::iterator II, unsigned pReg, bool secondReg, bool optLocation, MachineBasicBlock::iterator end, MachineFunction &MF)
hexagon Hexagon NewValueJump
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
unsigned getReg() const
getReg - Returns the register number.
std::vector< MachineBasicBlock * >::const_iterator const_succ_iterator
aarch64 promote const
virtual const TargetInstrInfo * getInstrInfo() const
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
BasicBlockListType::iterator iterator
#define DEBUG(X)
Definition: Debug.h:92
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:41
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
BranchProbability getEdgeProbability(const MachineBasicBlock *Src, const MachineBasicBlock *Dst) const
hexagon nvj
static cl::opt< bool > DisableNewValueJumps("disable-nvjump", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable New Value Jumps"))