28 #define DEBUG_TYPE "hexagon-isel"
34 cl::desc(
"Maximum number of uses of a global address such that we still us a"
35 "constant extended instruction"));
67 virtual void PreprocessISelDAG()
override;
68 virtual void EmitFunctionEntryCode()
override;
78 const char *getPassName()
const override {
79 return "Hexagon DAG->DAG Pattern Instruction Selection";
85 bool SelectInlineAsmMemoryOperand(
const SDValue &Op,
86 unsigned ConstraintID,
87 std::vector<SDValue> &OutOps)
override;
107 bool isConstExtProfitable(
SDNode *
N)
const;
115 assert(bitPos >= 0 && bitPos < 32 &&
116 "Constant out of range for 32 BitPos Memops");
117 return CurDAG->getTargetConstant(bitPos, DL,
MVT::i32);
123 return XformMskToBitPosU5Imm(Imm, DL);
129 return XformMskToBitPosU5Imm(Imm, DL);
134 bool ImmIsSingleBit(uint32_t v)
const {
142 assert( (Imm >= -31 && Imm <= -1) &&
"Constant out of range for Memops");
143 return CurDAG->getTargetConstant( - Imm, DL,
MVT::i32);
149 assert((Imm >= 1 && Imm <= 128) &&
"Constant out of range for cmpb op");
150 return CurDAG->getTargetConstant(Imm - 1, DL,
MVT::i8);
155 return CurDAG->getTargetConstant(Imm - 1, DL,
MVT::i32);
160 assert((Imm >= 1) &&
"Cannot decrement unsigned int less than 1");
161 return CurDAG->getTargetConstant(Imm - 1, DL,
MVT::i32);
166 return CurDAG->getTargetConstant(Imm - 2, DL,
MVT::i32);
171 return CurDAG->getTargetConstant(Imm - 3, DL,
MVT::i32);
175 #include "HexagonGenDAGISel.inc"
178 bool isValueExtension(
const SDValue &Val,
unsigned FromBits,
SDValue &Src);
189 return new HexagonDAGToDAGISel(TM, OptLevel);
194 const char *
Name =
"Hexagon DAG->DAG Pattern Instruction Selection";
211 case Intrinsic::hexagon_C2_cmpeq:
212 case Intrinsic::hexagon_C2_cmpgt:
213 case Intrinsic::hexagon_C2_cmpgtu:
214 case Intrinsic::hexagon_C2_cmpgtup:
215 case Intrinsic::hexagon_C2_cmpgtp:
216 case Intrinsic::hexagon_C2_cmpeqp:
217 case Intrinsic::hexagon_C2_bitsset:
218 case Intrinsic::hexagon_C2_bitsclr:
219 case Intrinsic::hexagon_C2_cmpeqi:
220 case Intrinsic::hexagon_C2_cmpgti:
221 case Intrinsic::hexagon_C2_cmpgtui:
222 case Intrinsic::hexagon_C2_cmpgei:
223 case Intrinsic::hexagon_C2_cmpgeui:
224 case Intrinsic::hexagon_C2_cmplt:
225 case Intrinsic::hexagon_C2_cmpltu:
226 case Intrinsic::hexagon_C2_bitsclri:
227 case Intrinsic::hexagon_C2_and:
228 case Intrinsic::hexagon_C2_or:
229 case Intrinsic::hexagon_C2_xor:
230 case Intrinsic::hexagon_C2_andn:
231 case Intrinsic::hexagon_C2_not:
232 case Intrinsic::hexagon_C2_orn:
233 case Intrinsic::hexagon_C2_pxfer_map:
234 case Intrinsic::hexagon_C2_any8:
235 case Intrinsic::hexagon_C2_all8:
236 case Intrinsic::hexagon_A2_vcmpbeq:
237 case Intrinsic::hexagon_A2_vcmpbgtu:
238 case Intrinsic::hexagon_A2_vcmpheq:
239 case Intrinsic::hexagon_A2_vcmphgt:
240 case Intrinsic::hexagon_A2_vcmphgtu:
241 case Intrinsic::hexagon_A2_vcmpweq:
242 case Intrinsic::hexagon_A2_vcmpwgt:
243 case Intrinsic::hexagon_A2_vcmpwgtu:
244 case Intrinsic::hexagon_C2_tfrrp:
245 case Intrinsic::hexagon_S2_tstbit_i:
246 case Intrinsic::hexagon_S2_tstbit_r:
259 int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
267 SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_sxtw, dl,
MVT::i64,
271 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
278 ReplaceUses(Froms, Tos, 3);
285 Base, TargetConst0, Chain);
286 SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_sxtw, dl,
MVT::i64,
288 SDNode* Result_3 = CurDAG->getMachineNode(Hexagon::A2_addi, dl,
MVT::i32,
289 Base, TargetConstVal,
293 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
300 ReplaceUses(Froms, Tos, 3);
313 int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
321 TargetConstVal, Chain);
322 SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A4_combineir, dl,
328 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
335 ReplaceUses(Froms, Tos, 3);
345 SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A4_combineir, dl,
350 SDNode* Result_3 = CurDAG->getMachineNode(Hexagon::A2_addi, dl,
MVT::i32,
351 Base, TargetConstVal,
355 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
362 ReplaceUses(Froms, Tos, 3);
373 int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
386 Opcode = Hexagon::L2_loadrd_pi;
388 Opcode = Hexagon::L2_loadrd_io;
391 Opcode = Hexagon::L2_loadri_pi;
393 Opcode = Hexagon::L2_loadri_io;
396 Opcode = IsZeroExt ? Hexagon::L2_loadruh_pi : Hexagon::L2_loadrh_pi;
398 Opcode = IsZeroExt ? Hexagon::L2_loadruh_io : Hexagon::L2_loadrh_io;
399 }
else if (LoadedVT ==
MVT::i8) {
401 Opcode = IsZeroExt ? Hexagon::L2_loadrub_pi : Hexagon::L2_loadrb_pi;
403 Opcode = IsZeroExt ? Hexagon::L2_loadrub_io : Hexagon::L2_loadrb_io;
409 return SelectIndexedLoadZeroExtend64(LD, Opcode, dl);
412 return SelectIndexedLoadSignExtend64(LD, Opcode, dl);
416 SDNode* Result = CurDAG->getMachineNode(Opcode, dl,
419 TargetConstVal, Chain);
422 cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
431 ReplaceUses(Froms, Tos, 3);
436 SDNode* Result_1 = CurDAG->getMachineNode(Opcode, dl,
440 SDNode* Result_2 = CurDAG->getMachineNode(Hexagon::A2_addi, dl,
MVT::i32,
441 Base, TargetConstVal,
445 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
454 ReplaceUses(Froms, Tos, 3);
468 result = SelectIndexedLoad(LD, dl);
470 result = SelectCode(LD);
484 int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
495 if (StoredVT ==
MVT::i64) Opcode = Hexagon::S2_storerd_pi;
496 else if (StoredVT ==
MVT::i32) Opcode = Hexagon::S2_storeri_pi;
497 else if (StoredVT ==
MVT::i16) Opcode = Hexagon::S2_storerh_pi;
498 else if (StoredVT ==
MVT::i8) Opcode = Hexagon::S2_storerb_pi;
502 assert(StoredVT.
getSizeInBits() < 64 &&
"Not a truncating store");
503 Value = CurDAG->getTargetExtractSubreg(Hexagon::subreg_loreg,
506 SDValue Ops[] = {Base, CurDAG->getTargetConstant(Val, dl,
MVT::i32), Value,
513 cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
515 ReplaceUses(ST, Result);
524 SDValue Ops[] = { Base, CurDAG->getTargetConstant(0, dl,
MVT::i32), Value,
529 if (StoredVT ==
MVT::i64) Opcode = Hexagon::S2_storerd_io;
530 else if (StoredVT ==
MVT::i32) Opcode = Hexagon::S2_storeri_io;
531 else if (StoredVT ==
MVT::i16) Opcode = Hexagon::S2_storerh_io;
532 else if (StoredVT ==
MVT::i8) Opcode = Hexagon::S2_storerb_io;
537 SDNode* Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
539 SDNode* Result_2 = CurDAG->getMachineNode(Hexagon::A2_addi, dl,
MVT::i32,
545 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
559 return SelectIndexedStore(ST, dl);
562 return SelectCode(ST);
590 return SelectCode(N);
599 return SelectCode(N);
604 OP0 =
SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl,
MVT::i32,
609 return SelectCode(N);
616 return SelectCode(N);
625 return SelectCode(N);
630 OP1 =
SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl,
MVT::i32,
635 return SelectCode(N);
639 SDNode *Result = CurDAG->getMachineNode(Hexagon::M2_dpmpyss_s0, dl,
MVT::i64,
641 ReplaceUses(N, Result);
645 return SelectCode(N);
661 cast<ConstantSDNode>(Shl_1.
getNode())->getSExtValue();
663 cast<ConstantSDNode>(Mul_1.
getNode())->getSExtValue();
664 int32_t ValConst = MulConst << ShlConst;
665 SDValue Val = CurDAG->getTargetConstant(ValConst, dl,
668 if (isInt<9>(CN->getSExtValue())) {
670 CurDAG->getMachineNode(Hexagon::M2_mpysmi, dl,
672 ReplaceUses(N, Result);
682 cast<ConstantSDNode>(Sub_0.
getNode())->getSExtValue();
689 cast<ConstantSDNode>(Shl_1.
getNode())->getSExtValue();
691 cast<ConstantSDNode>(Shl2_1.
getNode())->getSExtValue();
692 int32_t ValConst = 1 << (ShlConst+Shl2Const);
693 SDValue Val = CurDAG->getTargetConstant(-ValConst, dl,
696 dyn_cast<ConstantSDNode>(Val.
getNode()))
697 if (isInt<9>(CN->getSExtValue())) {
699 CurDAG->getMachineNode(Hexagon::M2_mpysmi, dl,
MVT::i32,
701 ReplaceUses(N, Result);
711 return SelectCode(N);
725 SDNode *HexagonDAGToDAGISel::SelectZeroExtend(
SDNode *N) {
734 SDNode *Mask = CurDAG->getMachineNode(Hexagon::C2_mask, dl,
MVT::i64, Op0);
738 uint64_t MV = 0,
Bit = 1;
739 for (
unsigned i = 0; i <
NE; ++i) {
744 SDNode *OnesReg = CurDAG->getMachineNode(Hexagon::CONST64_Int_Real, dl,
749 SDValue SubR = CurDAG->getTargetConstant(Hexagon::subreg_loreg, dl,
754 return CurDAG->getMachineNode(Hexagon::A2_andp, dl, ExVT,
761 cast<ConstantSDNode>(IsIntrinsic->
getOperand(0))->getZExtValue();
767 SDNode *Result_1 = CurDAG->getMachineNode(Hexagon::C2_tfrpr, dl,
770 SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl,
773 SDNode *Result_3 = CurDAG->getMachineNode(Hexagon::A2_combinew, dl,
777 ReplaceUses(N, Result_3);
782 SDNode* RsPd = CurDAG->getMachineNode(Hexagon::C2_tfrpr, dl,
785 ReplaceUses(N, RsPd);
791 return SelectCode(N);
798 SDNode *HexagonDAGToDAGISel::SelectIntrinsicWChain(
SDNode *N) {
799 unsigned IntNo = cast<ConstantSDNode>(N->
getOperand(1))->getZExtValue();
800 if (IntNo == Intrinsic::hexagon_circ_ldd ||
801 IntNo == Intrinsic::hexagon_circ_ldw ||
802 IntNo == Intrinsic::hexagon_circ_lduh ||
803 IntNo == Intrinsic::hexagon_circ_ldh ||
804 IntNo == Intrinsic::hexagon_circ_ldub ||
805 IntNo == Intrinsic::hexagon_circ_ldb) {
817 std::vector<EVT> ResTys;
819 unsigned memsize, align;
822 if (IntNo == Intrinsic::hexagon_circ_ldd) {
825 opc = Hexagon::L2_loadrd_pci_pseudo;
828 }
else if (IntNo == Intrinsic::hexagon_circ_ldw) {
831 opc = Hexagon::L2_loadri_pci_pseudo;
834 }
else if (IntNo == Intrinsic::hexagon_circ_ldh) {
837 opc = Hexagon::L2_loadrh_pci_pseudo;
841 }
else if (IntNo == Intrinsic::hexagon_circ_lduh) {
844 opc = Hexagon::L2_loadruh_pci_pseudo;
848 }
else if (IntNo == Intrinsic::hexagon_circ_ldb) {
851 opc = Hexagon::L2_loadrb_pci_pseudo;
855 }
else if (IntNo == Intrinsic::hexagon_circ_ldub) {
858 opc = Hexagon::L2_loadrub_pci_pseudo;
865 ResTys.push_back(MVT::Other);
872 int32_t Val = cast<ConstantSDNode>(Offset.
getNode())->getSExtValue();
875 SDNode* Result = CurDAG->getMachineNode(opc, dl, ResTys, Ops);
882 ST = CurDAG->getTruncStore(Chain, dl,
SDValue(Result, 1), Load,
885 ST = CurDAG->getStore(Chain, dl,
SDValue(Result, 1), Load, Mem);
893 ReplaceUses(Froms, Tos, 2);
897 if (IntNo == Intrinsic::hexagon_brev_ldd ||
898 IntNo == Intrinsic::hexagon_brev_ldw ||
899 IntNo == Intrinsic::hexagon_brev_ldh ||
900 IntNo == Intrinsic::hexagon_brev_lduh ||
901 IntNo == Intrinsic::hexagon_brev_ldb ||
902 IntNo == Intrinsic::hexagon_brev_ldub) {
911 std::vector<EVT> ResTys;
913 unsigned memsize, align;
916 if (IntNo == Intrinsic::hexagon_brev_ldd) {
919 opc = Hexagon::L2_loadrd_pbr_pseudo;
922 }
else if (IntNo == Intrinsic::hexagon_brev_ldw) {
925 opc = Hexagon::L2_loadri_pbr_pseudo;
928 }
else if (IntNo == Intrinsic::hexagon_brev_ldh) {
931 opc = Hexagon::L2_loadrh_pbr_pseudo;
935 }
else if (IntNo == Intrinsic::hexagon_brev_lduh) {
938 opc = Hexagon::L2_loadruh_pbr_pseudo;
942 }
else if (IntNo == Intrinsic::hexagon_brev_ldb) {
945 opc = Hexagon::L2_loadrb_pbr_pseudo;
949 }
else if (IntNo == Intrinsic::hexagon_brev_ldub) {
952 opc = Hexagon::L2_loadrub_pbr_pseudo;
959 ResTys.push_back(MVT::Other);
967 SDNode* Result = CurDAG->getMachineNode(opc, dl, ResTys, Ops);
973 ST = CurDAG->getTruncStore(Chain, dl,
SDValue(Result, 1), Load,
976 ST = CurDAG->getStore(Chain, dl,
SDValue(Result, 1), Load, Mem);
984 ReplaceUses(Froms, Tos, 2);
988 return SelectCode(N);
995 SDNode *HexagonDAGToDAGISel::SelectIntrinsicWOChain(
SDNode *N) {
996 unsigned IID = cast<ConstantSDNode>(N->
getOperand(0))->getZExtValue();
999 case Intrinsic::hexagon_S2_vsplatrb:
1002 case Intrinsic::hexagon_S2_vsplatrh:
1006 return SelectCode(N);
1011 if (isValueExtension(V, Bits, U)) {
1014 return SelectCode(R.
getNode());
1016 return SelectCode(N);
1022 SDNode *HexagonDAGToDAGISel::SelectConstantFP(
SDNode *N) {
1027 return CurDAG->getMachineNode(Hexagon::TFRI_f, dl,
MVT::f32,
1028 CurDAG->getTargetConstantFP(APF.convertToFloat(), dl,
MVT::f32));
1031 return CurDAG->getMachineNode(Hexagon::CONST64_Float_Real, dl,
MVT::f64,
1032 CurDAG->getTargetConstantFP(APF.convertToDouble(), dl,
MVT::f64));
1035 return SelectCode(N);
1041 SDNode *HexagonDAGToDAGISel::SelectConstant(
SDNode *N) {
1045 int32_t Val = cast<ConstantSDNode>(
N)->getSExtValue();
1047 Result = CurDAG->getMachineNode(Hexagon::TFR_PdTrue, dl,
MVT::i1);
1048 }
else if (Val == 0) {
1049 Result = CurDAG->getMachineNode(Hexagon::TFR_PdFalse, dl,
MVT::i1);
1052 ReplaceUses(N, Result);
1057 return SelectCode(N);
1067 return SelectCode(N);
1073 return SelectCode(N);
1078 SDNode* Result = CurDAG->getMachineNode(Hexagon::S2_asr_r_r_acc, dl,
MVT::i32,
1082 ReplaceUses(N, Result);
1100 return SelectCode(N);
1105 return SelectCode(N);
1110 Val = cast<ConstantSDNode>((N)->getOperand(1))->getSExtValue();
1112 return SelectCode(N);
1117 (!((Val & 0x80000000) || (Val & 0x7fffffff)))) ||
1119 (!((Val & 0x8000000000000000) || (Val & 0x7fffffff)))))
1121 return SelectCode(N);
1135 return SelectCode(N);
1140 unsigned bitpos = 0;
1144 return SelectCode(N);
1153 unsigned BitOpc = 0;
1156 default:
llvm_unreachable(
"Only bit-wise/abs/neg operations are allowed.");
1159 BitOpc = Hexagon::S2_clrbit_i;
1162 BitOpc = Hexagon::S2_setbit_i;
1166 BitOpc = Hexagon::S2_togglebit_i;
1175 Result = CurDAG->getMachineNode(BitOpc, dl, ValueVT,
1186 SDValue RegClass = CurDAG->getTargetConstant(Hexagon::DoubleRegsRegClassID,
1189 SDValue SubregHiIdx = CurDAG->getTargetConstant(Hexagon::subreg_hireg, dl,
1191 SDValue SubregLoIdx = CurDAG->getTargetConstant(Hexagon::subreg_loreg, dl,
1194 SDValue SubregHI = CurDAG->getTargetExtractSubreg(Hexagon::subreg_hireg, dl,
1197 SDValue SubregLO = CurDAG->getTargetExtractSubreg(Hexagon::subreg_loreg, dl,
1201 if (SubValueVT !=
MVT::f32 && bitpos < 32) {
1202 SDNode *Result0 = CurDAG->getMachineNode(BitOpc, dl, SubValueVT,
1204 const SDValue Ops[] = { RegClass, SubregHI, SubregHiIdx,
1205 SDValue(Result0, 0), SubregLoIdx };
1210 SDVal = CurDAG->getTargetConstant(bitpos - 32, dl,
MVT::i32);
1211 SDNode *Result0 = CurDAG->getMachineNode(BitOpc, dl, SubValueVT,
1213 const SDValue Ops[] = { RegClass,
SDValue(Result0, 0), SubregHiIdx,
1214 SubregLO, SubregLoIdx };
1220 ReplaceUses(N, Result);
1225 SDNode *HexagonDAGToDAGISel::SelectFrameIndex(
SDNode *N) {
1228 int FX = cast<FrameIndexSDNode>(
N)->getIndex();
1241 if (FX < 0 || MaxA <= StkA || !MFI->hasVarSizedObjects()) {
1242 R = CurDAG->getMachineNode(Hexagon::TFR_FI, DL,
MVT::i32, FI, Zero);
1247 SDValue Ops[] = { CurDAG->getCopyFromReg(CH, DL, AR,
MVT::i32), FI, Zero };
1248 R = CurDAG->getMachineNode(Hexagon::TFR_FIA, DL,
MVT::i32, Ops);
1265 return SelectConstant(N);
1268 return SelectConstantFP(N);
1271 return SelectFrameIndex(N);
1274 return SelectAdd(N);
1277 return SelectSHL(N);
1280 return SelectLoad(N);
1283 return SelectStore(N);
1286 return SelectMul(N);
1293 return SelectBitOp(N);
1296 return SelectZeroExtend(N);
1299 return SelectIntrinsicWChain(N);
1302 return SelectIntrinsicWOChain(N);
1305 return SelectCode(N);
1308 bool HexagonDAGToDAGISel::
1309 SelectInlineAsmMemoryOperand(
const SDValue &Op,
unsigned ConstraintID,
1310 std::vector<SDValue> &OutOps) {
1313 switch (ConstraintID) {
1320 if (SelectAddrFI(Inp, Res))
1321 OutOps.push_back(Res);
1323 OutOps.push_back(Inp);
1327 OutOps.push_back(CurDAG->getTargetConstant(0,
SDLoc(Op),
MVT::i32));
1331 bool HexagonDAGToDAGISel::isConstExtProfitable(
SDNode *N)
const {
1332 unsigned UseCount = 0;
1333 unsigned CallCount = 0;
1341 return (UseCount <= 1) || (CallCount > 1);
1345 void HexagonDAGToDAGISel::PreprocessISelDAG() {
1347 std::vector<SDNode*> Nodes;
1354 for (
auto I: Nodes) {
1358 auto IsZero = [] (
const SDValue &V) ->
bool {
1360 return SC->isNullValue();
1363 auto IsSelect0 = [IsZero] (
const SDValue &Op) ->
bool {
1369 SDValue N0 =
I->getOperand(0), N1 =
I->getOperand(1);
1370 EVT VT =
I->getValueType(0);
1371 bool SelN0 = IsSelect0(N0);
1372 SDValue SOp = SelN0 ? N0 : N1;
1373 SDValue VOp = SelN0 ? N1 : N0;
1384 }
else if (IsZero(SX)) {
1393 void HexagonDAGToDAGISel::EmitFunctionEntryCode() {
1395 auto &HFI = *HST.getFrameLowering();
1401 unsigned AR = FuncInfo->CreateReg(
MVT::i32);
1403 auto &HII = *HST.getInstrInfo();
1413 auto &HFI = *HST->getFrameLowering();
1415 int FX = cast<FrameIndexSDNode>(
N)->getIndex();
1418 R = CurDAG->getTargetFrameIndex(FX,
MVT::i32);
1422 inline bool HexagonDAGToDAGISel::SelectAddrGA(
SDValue &N,
SDValue &R) {
1423 return SelectGlobalAddress(N, R,
false);
1426 inline bool HexagonDAGToDAGISel::SelectAddrGP(
SDValue &N,
SDValue &R) {
1427 return SelectGlobalAddress(N, R,
true);
1430 bool HexagonDAGToDAGISel::SelectGlobalAddress(
SDValue &N,
SDValue &R,
1445 uint64_t NewOff = GA->getOffset() + (uint64_t)Const->getSExtValue();
1446 R = CurDAG->getTargetGlobalAddress(GA->getGlobal(),
SDLoc(Const),
1471 bool HexagonDAGToDAGISel::isValueExtension(
const SDValue &Val,
1472 unsigned FromBits,
SDValue &Src) {
1499 uint64_t FromMask = (1 << FromBits) - 1;
1501 if (
C->getZExtValue() == FromMask) {
1507 if (
C->getZExtValue() == FromMask) {
1517 uint64_t FromMask = (1 << FromBits) - 1;
1519 if ((
C->getZExtValue() & FromMask) == 0) {
1525 if ((
C->getZExtValue() & FromMask) == 0) {
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
void push_back(const T &Elt)
The memory access writes data.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
bool hasOneUse() const
Return true if there is exactly one use of this node.
unsigned getStackAlignBaseVReg() const
A global registry used in conjunction with static constructors to make pluggable components (like tar...
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
bool getHasDebugValue() const
Get this bit.
TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or anything else with this node...
Hexagon target-specific information for each MachineFunction.
const SDValue & getOperand(unsigned Num) const
void setNodeId(int Id)
Set unique node id.
const SDValue & getBasePtr() const
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
bool isVector() const
isVector - Return true if this is a vector value type.
MachineMemOperand - A description of a memory reference used in the backend.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
DILocation * get() const
Get the underlying DILocation.
const HexagonInstrInfo * TII
Shift and rotation operations.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
CopyToReg - This node has three operands: a chain, a register number to set to this value...
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
allnodes_const_iterator allnodes_end() const
This class is used to represent EVT's, which are used to parameterize some operations.
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
EVT getVectorElementType() const
getVectorElementType - Given a vector type, return the type of each element.
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Simple integer binary arithmetic operators.
const SDValue & getBasePtr() const
bool needsAligna(const MachineFunction &MF) const
EVT getMemoryVT() const
Return the type of the in-memory value.
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
This class is used to represent ISD::STORE nodes.
SDNode * getNode() const
get the SDNode which holds the desired result
A self-contained host- and target-independent arbitrary-precision floating-point software implementat...
initializer< Ty > init(const Ty &Val)
std::size_t countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the least significant bit to the most stopping at the first 1...
MVT - Machine Value Type.
const SDValue & getOperand(unsigned i) const
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
static void initializePassOnce(PassRegistry &Registry)
This class provides iterator support for SDUse operands that use a specific SDNode.
unsigned getOpcode() const
FunctionPass class - This class is used to implement most global optimizations.
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
use_iterator use_begin() const
Provide iteration support to walk over all uses of an SDNode.
const SDValue & getValue() const
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
PassInfo class - An instance of this class exists for every pass known by the system, and can be obtained from a live Pass by calling its getPassInfo() method.
EVT - Extended Value Type.
const APFloat & getValueAPF() const
ISD::MemIndexedMode getAddressingMode() const
Return the addressing mode for this load or store: unindexed, pre-inc, pre-dec, post-inc, or post-dec.
MachinePointerInfo - This class contains a discriminated union of information about pointers in memor...
REG_SEQUENCE - This variadic instruction is used to form a register that represents a consecutive seq...
const SDValue & getOffset() const
EXTRACT_SUBREG - This instruction takes two operands: a register that has subregisters, and a subregister index.
allnodes_const_iterator allnodes_begin() const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
const SDValue & getChain() const
CHAIN = SC CHAIN, Imm128 - System call.
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static unsigned doesIntrinsicReturnPredicate(unsigned ID)
Represents one node in the SelectionDAG.
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
unsigned Log2_32(uint32_t Value)
Log2_32 - This function returns the floor log base 2 of the specified value, -1 if the value is zero...
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
Select(COND, TRUEVAL, FALSEVAL).
static use_iterator use_end()
ZERO_EXTEND - Used for integer types, zeroing the new bits.
bool isPowerOf2_64(uint64_t Value)
isPowerOf2_64 - This function returns true if the argument is a power of two 0 (64 bit edition...
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
ANY_EXTEND - Used for integer types. The high bits are undefined.
APInt And(const APInt &LHS, const APInt &RHS)
Bitwise AND function for APInt.
Bitwise operators - logical and, logical or, logical xor.
bool isValidAutoIncImm(const EVT VT, const int Offset) const
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
void ReplaceAllUsesWith(SDValue From, SDValue Op)
Modify anything using 'From' to use 'To' instead.
void initializeHexagonDAGToDAGISelPass(PassRegistry &)
const SDValue & getOffset() const
FunctionPass * createHexagonISelDag(HexagonTargetMachine &TM, CodeGenOpt::Level OptLevel)
EVT getValueType() const
Return the ValueType of the referenced return value.
LLVM Value Representation.
#define CALL_ONCE_INITIALIZATION(function)
bool isTruncatingStore() const
Return true if the op does a truncation before store.
C - The default llvm calling convention, compatible with C.
bool isPowerOf2_32(uint32_t Value)
isPowerOf2_32 - This function returns true if the argument is a power of two > 0. ...
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
static cl::opt< unsigned > MaxNumOfUsesForConstExtenders("ga-max-num-uses-for-constant-extenders", cl::Hidden, cl::init(2), cl::desc("Maximum number of uses of a global address such that we still us a""constant extended instruction"))
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2, FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR - Perform various unary floating point operations.
void registerPass(const PassInfo &PI, bool ShouldFree=false)
registerPass - Register a pass (by means of its PassInfo) with the registry.
bool isMachineOpcode() const
Test if this node has a post-isel opcode, directly corresponding to a MachineInstr opcode...
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
unsigned getVectorNumElements() const
getVectorNumElements - Given a vector type, return the number of elements it contains.
This class is used to represent ISD::LOAD nodes.