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LLVM
3.7.0
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#include "AArch64InstrInfo.h"#include "AArch64MachineCombinerPattern.h"#include "AArch64Subtarget.h"#include "MCTargetDesc/AArch64AddressingModes.h"#include "llvm/CodeGen/MachineFrameInfo.h"#include "llvm/CodeGen/MachineInstrBuilder.h"#include "llvm/CodeGen/MachineMemOperand.h"#include "llvm/CodeGen/MachineRegisterInfo.h"#include "llvm/CodeGen/PseudoSourceValue.h"#include "llvm/MC/MCInst.h"#include "llvm/Support/ErrorHandling.h"#include "llvm/Support/TargetRegistry.h"#include "AArch64GenInstrInfo.inc"Go to the source code of this file.
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| #define | GET_INSTRINFO_CTOR_DTOR |
| #define GET_INSTRINFO_CTOR_DTOR |
Definition at line 29 of file AArch64InstrInfo.cpp.
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Definition at line 1479 of file AArch64InstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::MCRegisterInfo::getSubReg(), and llvm::TargetRegisterInfo::isPhysicalRegister().
Referenced by llvm::AArch64InstrInfo::copyPhysRegTuple().
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Definition at line 2426 of file AArch64InstrInfo.cpp.
References llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::MachineRegisterInfo::hasOneNonDBGUse(), llvm::MachineOperand::isReg(), llvm::TargetRegisterInfo::isVirtualRegister(), and llvm::AArch64CC::MI.
Referenced by llvm::AArch64InstrInfo::getMachineCombinerPatterns().
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Definition at line 297 of file AArch64InstrInfo.cpp.
References llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineRegisterInfo::getVRegDef(), llvm::MachineOperand::isImm(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::AArch64SysReg::NZCV, and removeCopies().
Referenced by llvm::AArch64InstrInfo::canInsertSelect(), and llvm::AArch64InstrInfo::insertSelect().
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Return the opcode that does not set flags when possible - otherwise return the original opcode.
The caller is responsible to do the actual substitution and legality checking.
Definition at line 734 of file AArch64InstrInfo.cpp.
References llvm::MachineInstr::definesRegister(), and llvm::MachineInstr::getOpcode().
Referenced by llvm::AArch64InstrInfo::getMachineCombinerPatterns(), and llvm::AArch64InstrInfo::optimizeCompareInstr().
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Definition at line 1491 of file AArch64InstrInfo.cpp.
Referenced by llvm::AArch64InstrInfo::copyPhysRegTuple().
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genMadd - Generate madd instruction and combine mul and add.
Example: MUL I=A,B,0 ADD R,I,C ==> MADD R,A,B,C
| Root | is the ADD instruction | |
| [out] | InsInstrs | is a vector of machine instructions and will contain the generated madd instruction |
| IdxMulOpd | is index of operand in Root that is the result of the MUL. In the example above IdxMulOpd is 1. | |
| MaddOpc | the opcode fo the madd instruction |
Definition at line 2576 of file AArch64InstrInfo.cpp.
References llvm::BuildMI(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::MCInstrInfo::get(), llvm::MachineInstr::getDebugLoc(), llvm::getKillRegState(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::MachineOperand::isKill(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::ISD::MUL, and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().
Referenced by llvm::AArch64InstrInfo::genAlternativeCodeSequence().
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genMaddR - Generate madd instruction and combine mul and add using an extra virtual register Example - an ADD intermediate needs to be stored in a register: MUL I=A,B,0 ADD R,I,Imm ==> ORR V, ZR, Imm ==> MADD R,A,B,V
| Root | is the ADD instruction | |
| [out] | InsInstrs | is a vector of machine instructions and will contain the generated madd instruction |
| IdxMulOpd | is index of operand in Root that is the result of the MUL. In the example above IdxMulOpd is 1. | |
| MaddOpc | the opcode fo the madd instruction | |
| VR | is a virtual register that holds the value of an ADD operand (V in the example above). |
Definition at line 2627 of file AArch64InstrInfo.cpp.
References llvm::BuildMI(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::MCInstrInfo::get(), llvm::MachineInstr::getDebugLoc(), llvm::getKillRegState(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::MachineOperand::isKill(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::ISD::MUL, and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().
Referenced by llvm::AArch64InstrInfo::genAlternativeCodeSequence().
Definition at line 2422 of file AArch64InstrInfo.cpp.
References isCombineInstrCandidate32(), and isCombineInstrCandidate64().
Referenced by llvm::AArch64InstrInfo::getMachineCombinerPatterns().
Definition at line 2384 of file AArch64InstrInfo.cpp.
Referenced by isCombineInstrCandidate().
Definition at line 2403 of file AArch64InstrInfo.cpp.
Referenced by isCombineInstrCandidate().
Definition at line 2365 of file AArch64InstrInfo.cpp.
Referenced by llvm::AArch64InstrInfo::getMachineCombinerPatterns().
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True when condition code could be modified on the instruction trace starting at from and ending at to.
Definition at line 781 of file AArch64InstrInfo.cpp.
References llvm::MachineBasicBlock::begin(), llvm::MachineInstr::getParent(), I, llvm::MachineInstr::modifiesRegister(), llvm::AArch64SysReg::NZCV, and llvm::MachineInstr::readsRegister().
Referenced by llvm::AArch64InstrInfo::optimizeCompareInstr(), and llvm::AArch64InstrInfo::optimizeCondBranch().
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Definition at line 61 of file AArch64InstrInfo.cpp.
References llvm::MachineOperand::CreateImm(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm_unreachable, and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().
Referenced by llvm::AArch64InstrInfo::AnalyzeBranch().
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Definition at line 284 of file AArch64InstrInfo.cpp.
References llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getVRegDef(), llvm::MachineInstr::isFullCopy(), and llvm::TargetRegisterInfo::isVirtualRegister().
Referenced by canFoldIntoCSel().
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Definition at line 693 of file AArch64InstrInfo.cpp.
References llvm::MachineRegisterInfo::constrainRegClass(), llvm::TargetRegisterClass::contains(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineInstr::getRegClassConstraint(), llvm::MachineFunction::getRegInfo(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::TargetRegisterClass::hasSubClassEq(), llvm::MachineOperand::isFI(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineOperand::isReg(), and TII.
Referenced by llvm::AArch64InstrInfo::optimizeCompareInstr().
1.8.6