LLVM  3.7.0
SIRegisterInfo.h
Go to the documentation of this file.
1 //===-- SIRegisterInfo.h - SI Register Info Interface ----------*- C++ -*--===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief Interface definition for SIRegisterInfo
12 //
13 //===----------------------------------------------------------------------===//
14 
15 
16 #ifndef LLVM_LIB_TARGET_R600_SIREGISTERINFO_H
17 #define LLVM_LIB_TARGET_R600_SIREGISTERINFO_H
18 
19 #include "AMDGPURegisterInfo.h"
20 #include "AMDGPUSubtarget.h"
21 #include "llvm/Support/Debug.h"
22 
23 namespace llvm {
24 
26 
28 
29  BitVector getReservedRegs(const MachineFunction &MF) const override;
30 
31  unsigned getRegPressureSetLimit(const MachineFunction &MF,
32  unsigned Idx) const override;
33 
34  bool requiresRegisterScavenging(const MachineFunction &Fn) const override;
35 
37  unsigned FIOperandNum,
38  RegScavenger *RS) const override;
39 
40  /// \brief get the register class of the specified type to use in the
41  /// CFGStructurizer
42  const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const override;
43 
44  unsigned getHWRegIndex(unsigned Reg) const override;
45 
46  /// \brief Return the 'base' register class for this register.
47  /// e.g. SGPR0 => SReg_32, VGPR => VGPR_32 SGPR0_SGPR1 -> SReg_32, etc.
48  const TargetRegisterClass *getPhysRegClass(unsigned Reg) const;
49 
50  /// \returns true if this class contains only SGPR registers
51  bool isSGPRClass(const TargetRegisterClass *RC) const {
52  if (!RC)
53  return false;
54 
55  return !hasVGPRs(RC);
56  }
57 
58  /// \returns true if this class ID contains only SGPR registers
59  bool isSGPRClassID(unsigned RCID) const {
60  if (static_cast<int>(RCID) == -1)
61  return false;
62 
63  return isSGPRClass(getRegClass(RCID));
64  }
65 
66  /// \returns true if this class contains VGPR registers.
67  bool hasVGPRs(const TargetRegisterClass *RC) const;
68 
69  /// \returns A VGPR reg class with the same width as \p SRC
71  const TargetRegisterClass *SRC) const;
72 
73  /// \returns The register class that is used for a sub-register of \p RC for
74  /// the given \p SubIdx. If \p SubIdx equals NoSubRegister, \p RC will
75  /// be returned.
77  unsigned SubIdx) const;
78 
79  /// \p Channel This is the register channel (e.g. a value from 0-16), not the
80  /// SubReg index.
81  /// \returns The sub-register of Reg that is in Channel.
82  unsigned getPhysRegSubReg(unsigned Reg, const TargetRegisterClass *SubRC,
83  unsigned Channel) const;
84 
85  /// \returns True if operands defined with this operand type can accept
86  /// a literal constant (i.e. any 32-bit immediate).
87  bool opCanUseLiteralConstant(unsigned OpType) const;
88 
89  /// \returns True if operands defined with this operand type can accept
90  /// an inline constant. i.e. An integer value in the range (-16, 64) or
91  /// -4.0f, -2.0f, -1.0f, -0.5f, 0.0f, 0.5f, 1.0f, 2.0f, 4.0f.
92  bool opCanUseInlineConstant(unsigned OpType) const;
93 
104  };
105 
106  /// \brief Returns the physical register that \p Value is stored in.
107  unsigned getPreloadedValue(const MachineFunction &MF,
108  enum PreloadedValue Value) const;
109 
110  /// \brief Give the maximum number of VGPRs that can be used by \p WaveCount
111  /// concurrent waves.
112  unsigned getNumVGPRsAllowed(unsigned WaveCount) const;
113 
114  /// \brief Give the maximum number of SGPRs that can be used by \p WaveCount
115  /// concurrent waves.
117  unsigned WaveCount) const;
118 
119  unsigned findUnusedRegister(const MachineRegisterInfo &MRI,
120  const TargetRegisterClass *RC) const;
121 
122 private:
123  void buildScratchLoadStore(MachineBasicBlock::iterator MI,
124  unsigned LoadStoreOp, unsigned Value,
125  unsigned ScratchRsrcReg, unsigned ScratchOffset,
126  int64_t Offset, RegScavenger *RS) const;
127 };
128 
129 } // End namespace llvm
130 
131 #endif
bool opCanUseInlineConstant(unsigned OpType) const
unsigned getPhysRegSubReg(unsigned Reg, const TargetRegisterClass *SubRC, unsigned Channel) const
Channel This is the register channel (e.g.
AMDGPU specific subclass of TargetSubtarget.
unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override
bool hasVGPRs(const TargetRegisterClass *RC) const
BitVector getReservedRegs(const MachineFunction &MF) const override
const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const override
get the register class of the specified type to use in the CFGStructurizer
bool isSGPRClass(const TargetRegisterClass *RC) const
Reg
All possible values of the reg field in the ModR/M byte.
bool requiresRegisterScavenging(const MachineFunction &Fn) const override
TargetRegisterInfo interface that is implemented by all hw codegen targets.
unsigned getHWRegIndex(unsigned Reg) const override
bundle_iterator< MachineInstr, instr_iterator > iterator
MVT - Machine Value Type.
unsigned getNumVGPRsAllowed(unsigned WaveCount) const
Give the maximum number of VGPRs that can be used by WaveCount concurrent waves.
bundle_iterator - MachineBasicBlock iterator that automatically skips over MIs that are inside bundle...
unsigned getPreloadedValue(const MachineFunction &MF, enum PreloadedValue Value) const
Returns the physical register that Value is stored in.
unsigned findUnusedRegister(const MachineRegisterInfo &MRI, const TargetRegisterClass *RC) const
Returns a register that is not used at any point in the function.
const TargetRegisterClass * getEquivalentVGPRClass(const TargetRegisterClass *SRC) const
static unsigned getRegClass(bool IsVgpr, unsigned RegWidth)
bool opCanUseLiteralConstant(unsigned OpType) const
unsigned getNumSGPRsAllowed(AMDGPUSubtarget::Generation gen, unsigned WaveCount) const
Give the maximum number of SGPRs that can be used by WaveCount concurrent waves.
bool isSGPRClassID(unsigned RCID) const
const TargetRegisterClass * getSubRegClass(const TargetRegisterClass *RC, unsigned SubIdx) const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
const TargetRegisterClass * getPhysRegClass(unsigned Reg) const
Return the 'base' register class for this register.
LLVM Value Representation.
Definition: Value.h:69
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const override