LLVM  3.7.0
ScheduleDAGSDNodes.cpp
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1 //===--- ScheduleDAGSDNodes.cpp - Implement the ScheduleDAGSDNodes class --===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This implements the ScheduleDAG class, which is a base class used by
11 // scheduling implementation classes.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "ScheduleDAGSDNodes.h"
16 #include "InstrEmitter.h"
17 #include "SDNodeDbgValue.h"
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/ADT/SmallPtrSet.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/ADT/Statistic.h"
28 #include "llvm/Support/Debug.h"
34 using namespace llvm;
35 
36 #define DEBUG_TYPE "pre-RA-sched"
37 
38 STATISTIC(LoadsClustered, "Number of loads clustered together");
39 
40 // This allows the latency-based scheduler to notice high latency instructions
41 // without a target itinerary. The choice of number here has more to do with
42 // balancing scheduler heuristics than with the actual machine latency.
44  "sched-high-latency-cycles", cl::Hidden, cl::init(10),
45  cl::desc("Roughly estimate the number of cycles that 'long latency'"
46  "instructions take for targets with no itinerary"));
47 
49  : ScheduleDAG(mf), BB(nullptr), DAG(nullptr),
50  InstrItins(mf.getSubtarget().getInstrItineraryData()) {}
51 
52 /// Run - perform scheduling.
53 ///
55  BB = bb;
56  DAG = dag;
57 
58  // Clear the scheduler's SUnit DAG.
60  Sequence.clear();
61 
62  // Invoke the target's selection of scheduler.
63  Schedule();
64 }
65 
66 /// NewSUnit - Creates a new SUnit and return a ptr to it.
67 ///
69 #ifndef NDEBUG
70  const SUnit *Addr = nullptr;
71  if (!SUnits.empty())
72  Addr = &SUnits[0];
73 #endif
74  SUnits.emplace_back(N, (unsigned)SUnits.size());
75  assert((Addr == nullptr || Addr == &SUnits[0]) &&
76  "SUnits std::vector reallocated on the fly!");
77  SUnits.back().OrigNode = &SUnits.back();
78  SUnit *SU = &SUnits.back();
80  if (!N ||
81  (N->isMachineOpcode() &&
84  else
86  return SU;
87 }
88 
90  SUnit *SU = newSUnit(Old->getNode());
91  SU->OrigNode = Old->OrigNode;
92  SU->Latency = Old->Latency;
93  SU->isVRegCycle = Old->isVRegCycle;
94  SU->isCall = Old->isCall;
95  SU->isCallOp = Old->isCallOp;
96  SU->isTwoAddress = Old->isTwoAddress;
97  SU->isCommutable = Old->isCommutable;
98  SU->hasPhysRegDefs = Old->hasPhysRegDefs;
100  SU->isScheduleHigh = Old->isScheduleHigh;
101  SU->isScheduleLow = Old->isScheduleLow;
102  SU->SchedulingPref = Old->SchedulingPref;
103  Old->isCloned = true;
104  return SU;
105 }
106 
107 /// CheckForPhysRegDependency - Check if the dependency between def and use of
108 /// a specified operand is a physical register dependency. If so, returns the
109 /// register and the cost of copying the register.
110 static void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op,
111  const TargetRegisterInfo *TRI,
112  const TargetInstrInfo *TII,
113  unsigned &PhysReg, int &Cost) {
114  if (Op != 2 || User->getOpcode() != ISD::CopyToReg)
115  return;
116 
117  unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
119  return;
120 
121  unsigned ResNo = User->getOperand(2).getResNo();
122  if (Def->getOpcode() == ISD::CopyFromReg &&
123  cast<RegisterSDNode>(Def->getOperand(1))->getReg() == Reg) {
124  PhysReg = Reg;
125  } else if (Def->isMachineOpcode()) {
126  const MCInstrDesc &II = TII->get(Def->getMachineOpcode());
127  if (ResNo >= II.getNumDefs() &&
128  II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg)
129  PhysReg = Reg;
130  }
131 
132  if (PhysReg != 0) {
133  const TargetRegisterClass *RC =
134  TRI->getMinimalPhysRegClass(Reg, Def->getSimpleValueType(ResNo));
135  Cost = RC->getCopyCost();
136  }
137 }
138 
139 // Helper for AddGlue to clone node operands.
141  SDValue ExtraOper = SDValue()) {
142  SmallVector<SDValue, 8> Ops(N->op_begin(), N->op_end());
143  if (ExtraOper.getNode())
144  Ops.push_back(ExtraOper);
145 
146  SDVTList VTList = DAG->getVTList(VTs);
147  MachineSDNode::mmo_iterator Begin = nullptr, End = nullptr;
149 
150  // Store memory references.
151  if (MN) {
152  Begin = MN->memoperands_begin();
153  End = MN->memoperands_end();
154  }
155 
156  DAG->MorphNodeTo(N, N->getOpcode(), VTList, Ops);
157 
158  // Reset the memory references
159  if (MN)
160  MN->setMemRefs(Begin, End);
161 }
162 
163 static bool AddGlue(SDNode *N, SDValue Glue, bool AddGlue, SelectionDAG *DAG) {
164  SDNode *GlueDestNode = Glue.getNode();
165 
166  // Don't add glue from a node to itself.
167  if (GlueDestNode == N) return false;
168 
169  // Don't add a glue operand to something that already uses glue.
170  if (GlueDestNode &&
171  N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue) {
172  return false;
173  }
174  // Don't add glue to something that already has a glue value.
175  if (N->getValueType(N->getNumValues() - 1) == MVT::Glue) return false;
176 
177  SmallVector<EVT, 4> VTs(N->value_begin(), N->value_end());
178  if (AddGlue)
179  VTs.push_back(MVT::Glue);
180 
181  CloneNodeWithValues(N, DAG, VTs, Glue);
182 
183  return true;
184 }
185 
186 // Cleanup after unsuccessful AddGlue. Use the standard method of morphing the
187 // node even though simply shrinking the value list is sufficient.
188 static void RemoveUnusedGlue(SDNode *N, SelectionDAG *DAG) {
189  assert((N->getValueType(N->getNumValues() - 1) == MVT::Glue &&
190  !N->hasAnyUseOfValue(N->getNumValues() - 1)) &&
191  "expected an unused glue value");
192 
193  CloneNodeWithValues(N, DAG,
194  makeArrayRef(N->value_begin(), N->getNumValues() - 1));
195 }
196 
197 /// ClusterNeighboringLoads - Force nearby loads together by "gluing" them.
198 /// This function finds loads of the same base and different offsets. If the
199 /// offsets are not far apart (target specific), it add MVT::Glue inputs and
200 /// outputs to ensure they are scheduled together and in order. This
201 /// optimization may benefit some targets by improving cache locality.
202 void ScheduleDAGSDNodes::ClusterNeighboringLoads(SDNode *Node) {
203  SDNode *Chain = nullptr;
204  unsigned NumOps = Node->getNumOperands();
205  if (Node->getOperand(NumOps-1).getValueType() == MVT::Other)
206  Chain = Node->getOperand(NumOps-1).getNode();
207  if (!Chain)
208  return;
209 
210  // Look for other loads of the same chain. Find loads that are loading from
211  // the same base pointer and different offsets.
212  SmallPtrSet<SDNode*, 16> Visited;
214  DenseMap<long long, SDNode*> O2SMap; // Map from offset to SDNode.
215  bool Cluster = false;
216  SDNode *Base = Node;
217  // This algorithm requires a reasonably low use count before finding a match
218  // to avoid uselessly blowing up compile time in large blocks.
219  unsigned UseCount = 0;
220  for (SDNode::use_iterator I = Chain->use_begin(), E = Chain->use_end();
221  I != E && UseCount < 100; ++I, ++UseCount) {
222  SDNode *User = *I;
223  if (User == Node || !Visited.insert(User).second)
224  continue;
225  int64_t Offset1, Offset2;
226  if (!TII->areLoadsFromSameBasePtr(Base, User, Offset1, Offset2) ||
227  Offset1 == Offset2)
228  // FIXME: Should be ok if they addresses are identical. But earlier
229  // optimizations really should have eliminated one of the loads.
230  continue;
231  if (O2SMap.insert(std::make_pair(Offset1, Base)).second)
232  Offsets.push_back(Offset1);
233  O2SMap.insert(std::make_pair(Offset2, User));
234  Offsets.push_back(Offset2);
235  if (Offset2 < Offset1)
236  Base = User;
237  Cluster = true;
238  // Reset UseCount to allow more matches.
239  UseCount = 0;
240  }
241 
242  if (!Cluster)
243  return;
244 
245  // Sort them in increasing order.
246  std::sort(Offsets.begin(), Offsets.end());
247 
248  // Check if the loads are close enough.
250  unsigned NumLoads = 0;
251  int64_t BaseOff = Offsets[0];
252  SDNode *BaseLoad = O2SMap[BaseOff];
253  Loads.push_back(BaseLoad);
254  for (unsigned i = 1, e = Offsets.size(); i != e; ++i) {
255  int64_t Offset = Offsets[i];
256  SDNode *Load = O2SMap[Offset];
257  if (!TII->shouldScheduleLoadsNear(BaseLoad, Load, BaseOff, Offset,NumLoads))
258  break; // Stop right here. Ignore loads that are further away.
259  Loads.push_back(Load);
260  ++NumLoads;
261  }
262 
263  if (NumLoads == 0)
264  return;
265 
266  // Cluster loads by adding MVT::Glue outputs and inputs. This also
267  // ensure they are scheduled in order of increasing addresses.
268  SDNode *Lead = Loads[0];
269  SDValue InGlue = SDValue(nullptr, 0);
270  if (AddGlue(Lead, InGlue, true, DAG))
271  InGlue = SDValue(Lead, Lead->getNumValues() - 1);
272  for (unsigned I = 1, E = Loads.size(); I != E; ++I) {
273  bool OutGlue = I < E - 1;
274  SDNode *Load = Loads[I];
275 
276  // If AddGlue fails, we could leave an unsused glue value. This should not
277  // cause any
278  if (AddGlue(Load, InGlue, OutGlue, DAG)) {
279  if (OutGlue)
280  InGlue = SDValue(Load, Load->getNumValues() - 1);
281 
282  ++LoadsClustered;
283  }
284  else if (!OutGlue && InGlue.getNode())
285  RemoveUnusedGlue(InGlue.getNode(), DAG);
286  }
287 }
288 
289 /// ClusterNodes - Cluster certain nodes which should be scheduled together.
290 ///
291 void ScheduleDAGSDNodes::ClusterNodes() {
292  for (SDNode &NI : DAG->allnodes()) {
293  SDNode *Node = &NI;
294  if (!Node || !Node->isMachineOpcode())
295  continue;
296 
297  unsigned Opc = Node->getMachineOpcode();
298  const MCInstrDesc &MCID = TII->get(Opc);
299  if (MCID.mayLoad())
300  // Cluster loads from "near" addresses into combined SUnits.
301  ClusterNeighboringLoads(Node);
302  }
303 }
304 
305 void ScheduleDAGSDNodes::BuildSchedUnits() {
306  // During scheduling, the NodeId field of SDNode is used to map SDNodes
307  // to their associated SUnits by holding SUnits table indices. A value
308  // of -1 means the SDNode does not yet have an associated SUnit.
309  unsigned NumNodes = 0;
310  for (SDNode &NI : DAG->allnodes()) {
311  NI.setNodeId(-1);
312  ++NumNodes;
313  }
314 
315  // Reserve entries in the vector for each of the SUnits we are creating. This
316  // ensure that reallocation of the vector won't happen, so SUnit*'s won't get
317  // invalidated.
318  // FIXME: Multiply by 2 because we may clone nodes during scheduling.
319  // This is a temporary workaround.
320  SUnits.reserve(NumNodes * 2);
321 
322  // Add all nodes in depth first order.
323  SmallVector<SDNode*, 64> Worklist;
324  SmallPtrSet<SDNode*, 64> Visited;
325  Worklist.push_back(DAG->getRoot().getNode());
326  Visited.insert(DAG->getRoot().getNode());
327 
328  SmallVector<SUnit*, 8> CallSUnits;
329  while (!Worklist.empty()) {
330  SDNode *NI = Worklist.pop_back_val();
331 
332  // Add all operands to the worklist unless they've already been added.
333  for (const SDValue &Op : NI->op_values())
334  if (Visited.insert(Op.getNode()).second)
335  Worklist.push_back(Op.getNode());
336 
337  if (isPassiveNode(NI)) // Leaf node, e.g. a TargetImmediate.
338  continue;
339 
340  // If this node has already been processed, stop now.
341  if (NI->getNodeId() != -1) continue;
342 
343  SUnit *NodeSUnit = newSUnit(NI);
344 
345  // See if anything is glued to this node, if so, add them to glued
346  // nodes. Nodes can have at most one glue input and one glue output. Glue
347  // is required to be the last operand and result of a node.
348 
349  // Scan up to find glued preds.
350  SDNode *N = NI;
351  while (N->getNumOperands() &&
352  N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue) {
353  N = N->getOperand(N->getNumOperands()-1).getNode();
354  assert(N->getNodeId() == -1 && "Node already inserted!");
355  N->setNodeId(NodeSUnit->NodeNum);
356  if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall())
357  NodeSUnit->isCall = true;
358  }
359 
360  // Scan down to find any glued succs.
361  N = NI;
362  while (N->getValueType(N->getNumValues()-1) == MVT::Glue) {
363  SDValue GlueVal(N, N->getNumValues()-1);
364 
365  // There are either zero or one users of the Glue result.
366  bool HasGlueUse = false;
367  for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
368  UI != E; ++UI)
369  if (GlueVal.isOperandOf(*UI)) {
370  HasGlueUse = true;
371  assert(N->getNodeId() == -1 && "Node already inserted!");
372  N->setNodeId(NodeSUnit->NodeNum);
373  N = *UI;
374  if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall())
375  NodeSUnit->isCall = true;
376  break;
377  }
378  if (!HasGlueUse) break;
379  }
380 
381  if (NodeSUnit->isCall)
382  CallSUnits.push_back(NodeSUnit);
383 
384  // Schedule zero-latency TokenFactor below any nodes that may increase the
385  // schedule height. Otherwise, ancestors of the TokenFactor may appear to
386  // have false stalls.
387  if (NI->getOpcode() == ISD::TokenFactor)
388  NodeSUnit->isScheduleLow = true;
389 
390  // If there are glue operands involved, N is now the bottom-most node
391  // of the sequence of nodes that are glued together.
392  // Update the SUnit.
393  NodeSUnit->setNode(N);
394  assert(N->getNodeId() == -1 && "Node already inserted!");
395  N->setNodeId(NodeSUnit->NodeNum);
396 
397  // Compute NumRegDefsLeft. This must be done before AddSchedEdges.
398  InitNumRegDefsLeft(NodeSUnit);
399 
400  // Assign the Latency field of NodeSUnit using target-provided information.
401  computeLatency(NodeSUnit);
402  }
403 
404  // Find all call operands.
405  while (!CallSUnits.empty()) {
406  SUnit *SU = CallSUnits.pop_back_val();
407  for (const SDNode *SUNode = SU->getNode(); SUNode;
408  SUNode = SUNode->getGluedNode()) {
409  if (SUNode->getOpcode() != ISD::CopyToReg)
410  continue;
411  SDNode *SrcN = SUNode->getOperand(2).getNode();
412  if (isPassiveNode(SrcN)) continue; // Not scheduled.
413  SUnit *SrcSU = &SUnits[SrcN->getNodeId()];
414  SrcSU->isCallOp = true;
415  }
416  }
417 }
418 
419 void ScheduleDAGSDNodes::AddSchedEdges() {
421 
422  // Check to see if the scheduler cares about latencies.
423  bool UnitLatencies = forceUnitLatencies();
424 
425  // Pass 2: add the preds, succs, etc.
426  for (unsigned su = 0, e = SUnits.size(); su != e; ++su) {
427  SUnit *SU = &SUnits[su];
428  SDNode *MainNode = SU->getNode();
429 
430  if (MainNode->isMachineOpcode()) {
431  unsigned Opc = MainNode->getMachineOpcode();
432  const MCInstrDesc &MCID = TII->get(Opc);
433  for (unsigned i = 0; i != MCID.getNumOperands(); ++i) {
434  if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) {
435  SU->isTwoAddress = true;
436  break;
437  }
438  }
439  if (MCID.isCommutable())
440  SU->isCommutable = true;
441  }
442 
443  // Find all predecessors and successors of the group.
444  for (SDNode *N = SU->getNode(); N; N = N->getGluedNode()) {
445  if (N->isMachineOpcode() &&
446  TII->get(N->getMachineOpcode()).getImplicitDefs()) {
447  SU->hasPhysRegClobbers = true;
448  unsigned NumUsed = InstrEmitter::CountResults(N);
449  while (NumUsed != 0 && !N->hasAnyUseOfValue(NumUsed - 1))
450  --NumUsed; // Skip over unused values at the end.
451  if (NumUsed > TII->get(N->getMachineOpcode()).getNumDefs())
452  SU->hasPhysRegDefs = true;
453  }
454 
455  for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
456  SDNode *OpN = N->getOperand(i).getNode();
457  if (isPassiveNode(OpN)) continue; // Not scheduled.
458  SUnit *OpSU = &SUnits[OpN->getNodeId()];
459  assert(OpSU && "Node has no SUnit!");
460  if (OpSU == SU) continue; // In the same group.
461 
462  EVT OpVT = N->getOperand(i).getValueType();
463  assert(OpVT != MVT::Glue && "Glued nodes should be in same sunit!");
464  bool isChain = OpVT == MVT::Other;
465 
466  unsigned PhysReg = 0;
467  int Cost = 1;
468  // Determine if this is a physical register dependency.
469  CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost);
470  assert((PhysReg == 0 || !isChain) &&
471  "Chain dependence via physreg data?");
472  // FIXME: See ScheduleDAGSDNodes::EmitCopyFromReg. For now, scheduler
473  // emits a copy from the physical register to a virtual register unless
474  // it requires a cross class copy (cost < 0). That means we are only
475  // treating "expensive to copy" register dependency as physical register
476  // dependency. This may change in the future though.
477  if (Cost >= 0 && !StressSched)
478  PhysReg = 0;
479 
480  // If this is a ctrl dep, latency is 1.
481  unsigned OpLatency = isChain ? 1 : OpSU->Latency;
482  // Special-case TokenFactor chains as zero-latency.
483  if(isChain && OpN->getOpcode() == ISD::TokenFactor)
484  OpLatency = 0;
485 
486  SDep Dep = isChain ? SDep(OpSU, SDep::Barrier)
487  : SDep(OpSU, SDep::Data, PhysReg);
488  Dep.setLatency(OpLatency);
489  if (!isChain && !UnitLatencies) {
490  computeOperandLatency(OpN, N, i, Dep);
491  ST.adjustSchedDependency(OpSU, SU, Dep);
492  }
493 
494  if (!SU->addPred(Dep) && !Dep.isCtrl() && OpSU->NumRegDefsLeft > 1) {
495  // Multiple register uses are combined in the same SUnit. For example,
496  // we could have a set of glued nodes with all their defs consumed by
497  // another set of glued nodes. Register pressure tracking sees this as
498  // a single use, so to keep pressure balanced we reduce the defs.
499  //
500  // We can't tell (without more book-keeping) if this results from
501  // glued nodes or duplicate operands. As long as we don't reduce
502  // NumRegDefsLeft to zero, we handle the common cases well.
503  --OpSU->NumRegDefsLeft;
504  }
505  }
506  }
507  }
508 }
509 
510 /// BuildSchedGraph - Build the SUnit graph from the selection dag that we
511 /// are input. This SUnit graph is similar to the SelectionDAG, but
512 /// excludes nodes that aren't interesting to scheduling, and represents
513 /// glued together nodes with a single SUnit.
515  // Cluster certain nodes which should be scheduled together.
516  ClusterNodes();
517  // Populate the SUnits array.
518  BuildSchedUnits();
519  // Compute all the scheduling dependencies between nodes.
520  AddSchedEdges();
521 }
522 
523 // Initialize NumNodeDefs for the current Node's opcode.
524 void ScheduleDAGSDNodes::RegDefIter::InitNodeNumDefs() {
525  // Check for phys reg copy.
526  if (!Node)
527  return;
528 
529  if (!Node->isMachineOpcode()) {
530  if (Node->getOpcode() == ISD::CopyFromReg)
531  NodeNumDefs = 1;
532  else
533  NodeNumDefs = 0;
534  return;
535  }
536  unsigned POpc = Node->getMachineOpcode();
537  if (POpc == TargetOpcode::IMPLICIT_DEF) {
538  // No register need be allocated for this.
539  NodeNumDefs = 0;
540  return;
541  }
542  if (POpc == TargetOpcode::PATCHPOINT &&
543  Node->getValueType(0) == MVT::Other) {
544  // PATCHPOINT is defined to have one result, but it might really have none
545  // if we're not using CallingConv::AnyReg. Don't mistake the chain for a
546  // real definition.
547  NodeNumDefs = 0;
548  return;
549  }
550  unsigned NRegDefs = SchedDAG->TII->get(Node->getMachineOpcode()).getNumDefs();
551  // Some instructions define regs that are not represented in the selection DAG
552  // (e.g. unused flags). See tMOVi8. Make sure we don't access past NumValues.
553  NodeNumDefs = std::min(Node->getNumValues(), NRegDefs);
554  DefIdx = 0;
555 }
556 
557 // Construct a RegDefIter for this SUnit and find the first valid value.
559  const ScheduleDAGSDNodes *SD)
560  : SchedDAG(SD), Node(SU->getNode()), DefIdx(0), NodeNumDefs(0) {
561  InitNodeNumDefs();
562  Advance();
563 }
564 
565 // Advance to the next valid value defined by the SUnit.
567  for (;Node;) { // Visit all glued nodes.
568  for (;DefIdx < NodeNumDefs; ++DefIdx) {
569  if (!Node->hasAnyUseOfValue(DefIdx))
570  continue;
571  ValueType = Node->getSimpleValueType(DefIdx);
572  ++DefIdx;
573  return; // Found a normal regdef.
574  }
575  Node = Node->getGluedNode();
576  if (!Node) {
577  return; // No values left to visit.
578  }
579  InitNodeNumDefs();
580  }
581 }
582 
584  assert(SU->NumRegDefsLeft == 0 && "expect a new node");
585  for (RegDefIter I(SU, this); I.IsValid(); I.Advance()) {
586  assert(SU->NumRegDefsLeft < USHRT_MAX && "overflow is ok but unexpected");
587  ++SU->NumRegDefsLeft;
588  }
589 }
590 
592  SDNode *N = SU->getNode();
593 
594  // TokenFactor operands are considered zero latency, and some schedulers
595  // (e.g. Top-Down list) may rely on the fact that operand latency is nonzero
596  // whenever node latency is nonzero.
597  if (N && N->getOpcode() == ISD::TokenFactor) {
598  SU->Latency = 0;
599  return;
600  }
601 
602  // Check to see if the scheduler cares about latencies.
603  if (forceUnitLatencies()) {
604  SU->Latency = 1;
605  return;
606  }
607 
608  if (!InstrItins || InstrItins->isEmpty()) {
609  if (N && N->isMachineOpcode() &&
612  else
613  SU->Latency = 1;
614  return;
615  }
616 
617  // Compute the latency for the node. We use the sum of the latencies for
618  // all nodes glued together into this SUnit.
619  SU->Latency = 0;
620  for (SDNode *N = SU->getNode(); N; N = N->getGluedNode())
621  if (N->isMachineOpcode())
623 }
624 
626  unsigned OpIdx, SDep& dep) const{
627  // Check to see if the scheduler cares about latencies.
628  if (forceUnitLatencies())
629  return;
630 
631  if (dep.getKind() != SDep::Data)
632  return;
633 
634  unsigned DefIdx = Use->getOperand(OpIdx).getResNo();
635  if (Use->isMachineOpcode())
636  // Adjust the use operand index by num of defs.
637  OpIdx += TII->get(Use->getMachineOpcode()).getNumDefs();
638  int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx);
639  if (Latency > 1 && Use->getOpcode() == ISD::CopyToReg &&
640  !BB->succ_empty()) {
641  unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
643  // This copy is a liveout value. It is likely coalesced, so reduce the
644  // latency so not to penalize the def.
645  // FIXME: need target specific adjustment here?
646  Latency = (Latency > 1) ? Latency - 1 : 1;
647  }
648  if (Latency >= 0)
649  dep.setLatency(Latency);
650 }
651 
652 void ScheduleDAGSDNodes::dumpNode(const SUnit *SU) const {
653 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
654  if (!SU->getNode()) {
655  dbgs() << "PHYS REG COPY\n";
656  return;
657  }
658 
659  SU->getNode()->dump(DAG);
660  dbgs() << "\n";
661  SmallVector<SDNode *, 4> GluedNodes;
662  for (SDNode *N = SU->getNode()->getGluedNode(); N; N = N->getGluedNode())
663  GluedNodes.push_back(N);
664  while (!GluedNodes.empty()) {
665  dbgs() << " ";
666  GluedNodes.back()->dump(DAG);
667  dbgs() << "\n";
668  GluedNodes.pop_back();
669  }
670 #endif
671 }
672 
673 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
675  for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
676  if (SUnit *SU = Sequence[i])
677  SU->dump(this);
678  else
679  dbgs() << "**** NOOP ****\n";
680  }
681 }
682 #endif
683 
684 #ifndef NDEBUG
685 /// VerifyScheduledSequence - Verify that all SUnits were scheduled and that
686 /// their state is consistent with the nodes listed in Sequence.
687 ///
689  unsigned ScheduledNodes = ScheduleDAG::VerifyScheduledDAG(isBottomUp);
690  unsigned Noops = 0;
691  for (unsigned i = 0, e = Sequence.size(); i != e; ++i)
692  if (!Sequence[i])
693  ++Noops;
694  assert(Sequence.size() - Noops == ScheduledNodes &&
695  "The number of nodes scheduled doesn't match the expected number!");
696 }
697 #endif // NDEBUG
698 
699 /// ProcessSDDbgValues - Process SDDbgValues associated with this node.
700 static void
702  SmallVectorImpl<std::pair<unsigned, MachineInstr*> > &Orders,
703  DenseMap<SDValue, unsigned> &VRBaseMap, unsigned Order) {
704  if (!N->getHasDebugValue())
705  return;
706 
707  // Opportunistically insert immediate dbg_value uses, i.e. those with source
708  // order number right after the N.
709  MachineBasicBlock *BB = Emitter.getBlock();
710  MachineBasicBlock::iterator InsertPos = Emitter.getInsertPos();
711  ArrayRef<SDDbgValue*> DVs = DAG->GetDbgValues(N);
712  for (unsigned i = 0, e = DVs.size(); i != e; ++i) {
713  if (DVs[i]->isInvalidated())
714  continue;
715  unsigned DVOrder = DVs[i]->getOrder();
716  if (!Order || DVOrder == ++Order) {
717  MachineInstr *DbgMI = Emitter.EmitDbgValue(DVs[i], VRBaseMap);
718  if (DbgMI) {
719  Orders.push_back(std::make_pair(DVOrder, DbgMI));
720  BB->insert(InsertPos, DbgMI);
721  }
722  DVs[i]->setIsInvalidated();
723  }
724  }
725 }
726 
727 // ProcessSourceNode - Process nodes with source order numbers. These are added
728 // to a vector which EmitSchedule uses to determine how to insert dbg_value
729 // instructions in the right order.
730 static void
732  DenseMap<SDValue, unsigned> &VRBaseMap,
733  SmallVectorImpl<std::pair<unsigned, MachineInstr*> > &Orders,
734  SmallSet<unsigned, 8> &Seen) {
735  unsigned Order = N->getIROrder();
736  if (!Order || !Seen.insert(Order).second) {
737  // Process any valid SDDbgValues even if node does not have any order
738  // assigned.
739  ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, 0);
740  return;
741  }
742 
743  MachineBasicBlock *BB = Emitter.getBlock();
744  if (Emitter.getInsertPos() == BB->begin() || BB->back().isPHI() ||
745  // Fast-isel may have inserted some instructions, in which case the
746  // BB->back().isPHI() test will not fire when we want it to.
747  std::prev(Emitter.getInsertPos())->isPHI()) {
748  // Did not insert any instruction.
749  Orders.push_back(std::make_pair(Order, (MachineInstr*)nullptr));
750  return;
751  }
752 
753  Orders.push_back(std::make_pair(Order, std::prev(Emitter.getInsertPos())));
754  ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, Order);
755 }
756 
757 void ScheduleDAGSDNodes::
758 EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap,
759  MachineBasicBlock::iterator InsertPos) {
760  for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
761  I != E; ++I) {
762  if (I->isCtrl()) continue; // ignore chain preds
763  if (I->getSUnit()->CopyDstRC) {
764  // Copy to physical register.
765  DenseMap<SUnit*, unsigned>::iterator VRI = VRBaseMap.find(I->getSUnit());
766  assert(VRI != VRBaseMap.end() && "Node emitted out of order - late");
767  // Find the destination physical register.
768  unsigned Reg = 0;
769  for (SUnit::const_succ_iterator II = SU->Succs.begin(),
770  EE = SU->Succs.end(); II != EE; ++II) {
771  if (II->isCtrl()) continue; // ignore chain preds
772  if (II->getReg()) {
773  Reg = II->getReg();
774  break;
775  }
776  }
777  BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), Reg)
778  .addReg(VRI->second);
779  } else {
780  // Copy from physical register.
781  assert(I->getReg() && "Unknown physical register!");
782  unsigned VRBase = MRI.createVirtualRegister(SU->CopyDstRC);
783  bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase)).second;
784  (void)isNew; // Silence compiler warning.
785  assert(isNew && "Node emitted out of order - early");
786  BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), VRBase)
787  .addReg(I->getReg());
788  }
789  break;
790  }
791 }
792 
793 /// EmitSchedule - Emit the machine code in scheduled order. Return the new
794 /// InsertPos and MachineBasicBlock that contains this insertion
795 /// point. ScheduleDAGSDNodes holds a BB pointer for convenience, but this does
796 /// not necessarily refer to returned BB. The emitter may split blocks.
799  InstrEmitter Emitter(BB, InsertPos);
800  DenseMap<SDValue, unsigned> VRBaseMap;
801  DenseMap<SUnit*, unsigned> CopyVRBaseMap;
804  bool HasDbg = DAG->hasDebugValues();
805 
806  // If this is the first BB, emit byval parameter dbg_value's.
807  if (HasDbg && BB->getParent()->begin() == MachineFunction::iterator(BB)) {
810  for (; PDI != PDE; ++PDI) {
811  MachineInstr *DbgMI= Emitter.EmitDbgValue(*PDI, VRBaseMap);
812  if (DbgMI)
813  BB->insert(InsertPos, DbgMI);
814  }
815  }
816 
817  for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
818  SUnit *SU = Sequence[i];
819  if (!SU) {
820  // Null SUnit* is a noop.
821  TII->insertNoop(*Emitter.getBlock(), InsertPos);
822  continue;
823  }
824 
825  // For pre-regalloc scheduling, create instructions corresponding to the
826  // SDNode and any glued SDNodes and append them to the block.
827  if (!SU->getNode()) {
828  // Emit a copy.
829  EmitPhysRegCopy(SU, CopyVRBaseMap, InsertPos);
830  continue;
831  }
832 
833  SmallVector<SDNode *, 4> GluedNodes;
834  for (SDNode *N = SU->getNode()->getGluedNode(); N; N = N->getGluedNode())
835  GluedNodes.push_back(N);
836  while (!GluedNodes.empty()) {
837  SDNode *N = GluedNodes.back();
838  Emitter.EmitNode(GluedNodes.back(), SU->OrigNode != SU, SU->isCloned,
839  VRBaseMap);
840  // Remember the source order of the inserted instruction.
841  if (HasDbg)
842  ProcessSourceNode(N, DAG, Emitter, VRBaseMap, Orders, Seen);
843  GluedNodes.pop_back();
844  }
845  Emitter.EmitNode(SU->getNode(), SU->OrigNode != SU, SU->isCloned,
846  VRBaseMap);
847  // Remember the source order of the inserted instruction.
848  if (HasDbg)
849  ProcessSourceNode(SU->getNode(), DAG, Emitter, VRBaseMap, Orders,
850  Seen);
851  }
852 
853  // Insert all the dbg_values which have not already been inserted in source
854  // order sequence.
855  if (HasDbg) {
857 
858  // Sort the source order instructions and use the order to insert debug
859  // values.
860  std::sort(Orders.begin(), Orders.end(), less_first());
861 
863  SDDbgInfo::DbgIterator DE = DAG->DbgEnd();
864  // Now emit the rest according to source order.
865  unsigned LastOrder = 0;
866  for (unsigned i = 0, e = Orders.size(); i != e && DI != DE; ++i) {
867  unsigned Order = Orders[i].first;
868  MachineInstr *MI = Orders[i].second;
869  // Insert all SDDbgValue's whose order(s) are before "Order".
870  if (!MI)
871  continue;
872  for (; DI != DE &&
873  (*DI)->getOrder() >= LastOrder && (*DI)->getOrder() < Order; ++DI) {
874  if ((*DI)->isInvalidated())
875  continue;
876  MachineInstr *DbgMI = Emitter.EmitDbgValue(*DI, VRBaseMap);
877  if (DbgMI) {
878  if (!LastOrder)
879  // Insert to start of the BB (after PHIs).
880  BB->insert(BBBegin, DbgMI);
881  else {
882  // Insert at the instruction, which may be in a different
883  // block, if the block was split by a custom inserter.
885  MI->getParent()->insert(Pos, DbgMI);
886  }
887  }
888  }
889  LastOrder = Order;
890  }
891  // Add trailing DbgValue's before the terminator. FIXME: May want to add
892  // some of them before one or more conditional branches?
894  while (DI != DE) {
895  if (!(*DI)->isInvalidated())
896  if (MachineInstr *DbgMI = Emitter.EmitDbgValue(*DI, VRBaseMap))
897  DbgMIs.push_back(DbgMI);
898  ++DI;
899  }
900 
901  MachineBasicBlock *InsertBB = Emitter.getBlock();
903  InsertBB->insert(Pos, DbgMIs.begin(), DbgMIs.end());
904  }
905 
906  InsertPos = Emitter.getInsertPos();
907  return Emitter.getBlock();
908 }
909 
910 /// Return the basic block label.
911 std::string ScheduleDAGSDNodes::getDAGName() const {
912  return "sunit-dag." + BB->getFullName();
913 }
SDNode * MorphNodeTo(SDNode *N, unsigned Opc, SDVTList VTs, ArrayRef< SDValue > Ops)
This mutates the specified node to have the specified return type, opcode, and operands.
value_iterator value_begin() const
void push_back(const T &Elt)
Definition: SmallVector.h:222
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
bool isCtrl() const
isCtrl - Shorthand for getKind() != SDep::Data.
Definition: ScheduleDAG.h:175
void dump() const
Dump this node, for debugging.
void setNode(SDNode *N)
setNode - Assign the representative SDNode for this SUnit.
Definition: ScheduleDAG.h:381
STATISTIC(NumFunctions,"Total number of functions")
bool hasDebugValues() const
Return true if there are any SDDbgValue nodes associated with this SelectionDAG.
void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd)
Assign this MachineSDNodes's memory reference descriptor list.
bool isCommutable() const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged.
Definition: MCInstrDesc.h:388
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:191
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
virtual void computeOperandLatency(SDNode *Def, SDNode *Use, unsigned OpIdx, SDep &dep) const
bool isTwoAddress
Definition: ScheduleDAG.h:296
iterator getFirstTerminator()
getFirstTerminator - returns an iterator to the first terminator instruction of this basic block...
SDNode * getGluedNode() const
If this node has a glue operand, return the node to which the glue operand points.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:138
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
bool getHasDebugValue() const
Get this bit.
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:378
static unsigned CountResults(SDNode *Node)
CountResults - The results of target nodes have register or immediate operands first, then an optional chain, and optional flag operands (which do not go into the machine instrs.)
unsigned getNumOperands() const
Return the number of values used by this operation.
A debug info location.
Definition: DebugLoc.h:34
const SDValue & getOperand(unsigned Num) const
mmo_iterator memoperands_end() const
virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const
This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePt...
void setNodeId(int Id)
Set unique node id.
const TargetRegisterClass * CopyDstRC
Definition: ScheduleDAG.h:320
unsigned getResNo() const
get the index which selects a specific result in the SDNode
SmallVector< SDep, 4 > Preds
Definition: ScheduleDAG.h:275
MachineBasicBlock * getBlock()
getBlock - Return the current basic block.
Definition: InstrEmitter.h:127
static void CloneNodeWithValues(SDNode *N, SelectionDAG *DAG, ArrayRef< EVT > VTs, SDValue ExtraOper=SDValue())
MachineFunction & MF
Definition: ScheduleDAG.h:563
COPY - Target-independent register copy.
Definition: TargetOpcodes.h:86
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Definition: DenseMap.h:169
SDDbgInfo::DbgIterator DbgBegin()
void InitNumRegDefsLeft(SUnit *SU)
InitNumRegDefsLeft - Determine the # of regs defined by this node.
static void ProcessSDDbgValues(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter, SmallVectorImpl< std::pair< unsigned, MachineInstr * > > &Orders, DenseMap< SDValue, unsigned > &VRBaseMap, unsigned Order)
ProcessSDDbgValues - Process SDDbgValues associated with this node.
MachineMemOperand - A description of a memory reference used in the backend.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
mmo_iterator memoperands_begin() const
const HexagonInstrInfo * TII
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:308
bool isPHI() const
Definition: MachineInstr.h:757
T LLVM_ATTRIBUTE_UNUSED_RESULT pop_back_val()
Definition: SmallVector.h:406
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
A Use represents the edge between a Value definition and its users.
Definition: Use.h:69
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APInt.h:33
Regular data dependence (aka true-dependence).
Definition: ScheduleDAG.h:49
CopyToReg - This node has three operands: a chain, a register number to set to this value...
Definition: ISDOpcodes.h:161
Reg
All possible values of the reg field in the ModR/M byte.
bool hasPhysRegDefs
Definition: ScheduleDAG.h:299
Number of individual test Apply this number of consecutive mutations to each input exit after the first new interesting input is found the minimized corpus is saved into the first input directory Number of jobs to run If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
ScheduleDAGSDNodes(MachineFunction &mf)
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Sched::Preference getSchedulingPreference() const
Return target scheduling preference.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
iterator_range< allnodes_iterator > allnodes()
Definition: SelectionDAG.h:326
load Combine Adjacent Loads
SUnit * OrigNode
Definition: ScheduleDAG.h:268
static cl::opt< int > HighLatencyCycles("sched-high-latency-cycles", cl::Hidden, cl::init(10), cl::desc("Roughly estimate the number of cycles that 'long latency'""instructions take for targets with no itinerary"))
unsigned getIROrder() const
Return the node ordering.
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Definition: SmallVector.h:57
static void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op, const TargetRegisterInfo *TRI, const TargetInstrInfo *TII, unsigned &PhysReg, int &Cost)
CheckForPhysRegDependency - Check if the dependency between def and use of a specified operand is a p...
value_iterator value_end() const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: ArrayRef.h:31
virtual void adjustSchedDependency(SUnit *def, SUnit *use, SDep &dep) const
std::string getDAGName() const override
Return the basic block label.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:134
virtual unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr *MI, unsigned *PredCost=nullptr) const
Compute the instruction latency of a given instruction.
SUnit * Clone(SUnit *N)
Clone - Creates a clone of the specified SUnit.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:120
void dumpNode(const SUnit *SU) const override
TargetInstrInfo - Interface to description of machine instruction set.
SDDbgInfo::DbgIterator ByvalParmDbgEnd()
SDep - Scheduling dependency.
Definition: ScheduleDAG.h:45
SDNode * getNode() const
get the SDNode which holds the desired result
IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
Definition: TargetOpcodes.h:52
bundle_iterator< MachineInstr, instr_iterator > iterator
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:325
Patchable call instruction - this instruction represents a call to a constant address, followed by a series of NOPs.
ScheduleDAGSDNodes - A ScheduleDAG for scheduling SDNode-based DAGs.
std::vector< SUnit * > Sequence
The schedule. Null SUnit*'s represent noop instructions.
SUnit * newSUnit(SDNode *N)
NewSUnit - Creates a new SUnit and return a ptr to it.
void clearDAG()
clearDAG - clear the DAG state (between regions).
Definition: ScheduleDAG.cpp:50
SDNode * getNode() const
getNode - Return the representative SDNode for this SUnit.
Definition: ScheduleDAG.h:388
unsigned short Latency
Definition: ScheduleDAG.h:292
virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const
This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base a...
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:32
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:264
const InstrItineraryData * InstrItins
bool isVRegCycle
Definition: ScheduleDAG.h:293
This class provides iterator support for SDUse operands that use a specific SDNode.
virtual void computeLatency(SUnit *SU)
computeLatency - Compute node latency.
ArrayRef< SDDbgValue * > GetDbgValues(const SDNode *SD)
Get the debug values which reference the given SDNode.
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:69
use_iterator use_begin() const
Provide iteration support to walk over all uses of an SDNode.
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
EVT - Extended Value Type.
Definition: ValueTypes.h:31
Sched::Preference SchedulingPref
Definition: ScheduleDAG.h:309
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
RegDefIter - In place iteration over the values defined by an SUnit.
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:162
const SDValue & getRoot() const
Return the root tag of the SelectionDAG.
Definition: SelectionDAG.h:335
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
An unknown scheduling barrier.
Definition: ScheduleDAG.h:65
std::string getFullName() const
getFullName - Return a formatted string to identify this block and its parent function.
static void RemoveUnusedGlue(SDNode *N, SelectionDAG *DAG)
TokenFactor - This node takes multiple tokens as input and produces a single token result...
Definition: ISDOpcodes.h:50
bool isScheduleHigh
Definition: ScheduleDAG.h:304
bool isCommutable
Definition: ScheduleDAG.h:297
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
Definition: SmallPtrSet.h:299
virtual void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
Insert a noop into the instruction stream at the specified point.
MachineBasicBlock * BB
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:179
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:861
SDDbgInfo::DbgIterator DbgEnd()
An SDNode that represents everything that will be needed to construct a MachineInstr.
bool mayLoad() const
Return true if this instruction could possibly read memory.
Definition: MCInstrDesc.h:350
Represents one node in the SelectionDAG.
SDDbgInfo::DbgIterator ByvalParmDbgBegin()
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:123
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
getMinimalPhysRegClass - Returns the Register Class of a physical register of the given type...
op_iterator op_begin() const
static use_iterator use_end()
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:285
iterator_range< value_op_iterator > op_values() const
void setLatency(unsigned Lat)
setLatency - Set the latency for this edge.
Definition: ScheduleDAG.h:155
static bool isPassiveNode(SDNode *Node)
isPassiveNode - Return true if the node is a non-scheduled leaf.
TargetSubtargetInfo - Generic base class for all target subtargets.
int getCopyCost() const
getCopyCost - Return the cost of copying a value between two registers in this class.
unsigned VerifyScheduledDAG(bool isBottomUp)
VerifyScheduledDAG - Verify that all SUnits were scheduled and that their state is consistent...
Representation of each machine instruction.
Definition: MachineInstr.h:51
const TargetRegisterInfo * TRI
Definition: ScheduleDAG.h:562
void EmitNode(SDNode *Node, bool IsClone, bool IsCloned, DenseMap< SDValue, unsigned > &VRBaseMap)
EmitNode - Generate machine code for a node and needed dependencies.
Definition: InstrEmitter.h:118
static void ProcessSourceNode(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter, DenseMap< SDValue, unsigned > &VRBaseMap, SmallVectorImpl< std::pair< unsigned, MachineInstr * > > &Orders, SmallSet< unsigned, 8 > &Seen)
bool hasAnyUseOfValue(unsigned Value) const
Return true if there are any use of the indicated value.
RegDefIter(const SUnit *SU, const ScheduleDAGSDNodes *SD)
void BuildSchedGraph(AliasAnalysis *AA)
BuildSchedGraph - Build the SUnit graph from the selection dag that we are input. ...
void push_back(MachineInstr *MI)
#define I(x, y, z)
Definition: MD5.cpp:54
#define N
unsigned short NumRegDefsLeft
Definition: ScheduleDAG.h:291
op_iterator op_end() const
virtual int getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const
Kind getKind() const
getKind - Return an enum value representing the kind of the dependence.
Definition: ScheduleDAG.h:170
void Run(SelectionDAG *dag, MachineBasicBlock *bb)
Run - perform scheduling.
iterator getFirstNonPHI()
Returns a pointer to the first instruction in this block that is not a PHINode instruction.
const TargetInstrInfo * TII
Definition: ScheduleDAG.h:561
int getNodeId() const
Return the unique node id.
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
Definition: ISDOpcodes.h:166
EVT getValueType() const
Return the ValueType of the referenced return value.
unsigned NodeNum
Definition: ScheduleDAG.h:283
const uint16_t * ImplicitDefs
Definition: MCInstrDesc.h:148
MachineInstr * EmitDbgValue(SDDbgValue *SD, DenseMap< SDValue, unsigned > &VRBaseMap)
EmitDbgValue - Generate machine instruction for a dbg_value node.
bool addPred(const SDep &D, bool Required=true)
addPred - This adds the specified edge as a pred of the current node if not already.
Definition: ScheduleDAG.cpp:65
MachineBasicBlock::iterator getInsertPos()
getInsertPos - Return the current insertion position.
Definition: InstrEmitter.h:130
virtual MachineBasicBlock * EmitSchedule(MachineBasicBlock::iterator &InsertPos)
EmitSchedule - Insert MachineInstrs into the MachineBasicBlock according to the order specified in Se...
SmallVector< SDep, 4 > Succs
Definition: ScheduleDAG.h:276
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:185
BasicBlockListType::iterator iterator
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:287
bool isScheduleLow
Definition: ScheduleDAG.h:305
virtual bool forceUnitLatencies() const
ForceUnitLatencies - Return true if all scheduling edges should be given a latency value of one...
MachineRegisterInfo & MRI
Definition: ScheduleDAG.h:564
std::vector< SUnit > SUnits
Definition: ScheduleDAG.h:565
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
bool hasPhysRegClobbers
Definition: ScheduleDAG.h:300
MVT getSimpleValueType(unsigned ResNo) const
Return the type of a specified result as a simple type.
bool isEmpty() const
Returns true if there are no itineraries.
virtual void Schedule()=0
Schedule - Order nodes according to selected style, filling in the Sequence member.
Function object to check whether the first component of a std::pair compares less than the first comp...
Definition: STLExtras.h:205
void dump(const ScheduleDAG *G) const
SUnit - Scheduling unit.
virtual bool isHighLatencyDef(int opc) const
Return true if this opcode has high latency to its result.
SUnit - Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:261
static bool AddGlue(SDNode *N, SDValue Glue, bool AddGlue, SelectionDAG *DAG)
bool isMachineOpcode() const
Test if this node has a post-isel opcode, directly corresponding to a MachineInstr opcode...
This file describes how to lower LLVM code to machine code.
void VerifyScheduledSequence(bool isBottomUp)
VerifyScheduledSequence - Verify that all SUnits are scheduled and consistent with the Sequence of sc...
unsigned getMachineOpcode() const
This may only be called if isMachineOpcode returns true.