LLVM  3.7.0
MipsDisassembler.cpp
Go to the documentation of this file.
1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file is part of the Mips Disassembler.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "Mips.h"
15 #include "MipsRegisterInfo.h"
16 #include "MipsSubtarget.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCDisassembler.h"
20 #include "llvm/MC/MCInst.h"
24 
25 using namespace llvm;
26 
27 #define DEBUG_TYPE "mips-disassembler"
28 
30 
31 namespace {
32 
33 class MipsDisassembler : public MCDisassembler {
34  bool IsMicroMips;
35  bool IsBigEndian;
36 public:
37  MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian)
38  : MCDisassembler(STI, Ctx),
39  IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]),
40  IsBigEndian(IsBigEndian) {}
41 
42  bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; }
43  bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; }
44  bool hasMips32r6() const {
45  return STI.getFeatureBits()[Mips::FeatureMips32r6];
46  }
47 
48  bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; }
49 
50  bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; }
51 
52  bool hasCOP3() const {
53  // Only present in MIPS-I and MIPS-II
54  return !hasMips32() && !hasMips3();
55  }
56 
57  DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
58  ArrayRef<uint8_t> Bytes, uint64_t Address,
59  raw_ostream &VStream,
60  raw_ostream &CStream) const override;
61 };
62 
63 } // end anonymous namespace
64 
65 // Forward declare these because the autogenerated code will reference them.
66 // Definitions are further down.
68  unsigned RegNo,
69  uint64_t Address,
70  const void *Decoder);
71 
73  unsigned RegNo,
74  uint64_t Address,
75  const void *Decoder);
76 
78  unsigned RegNo,
79  uint64_t Address,
80  const void *Decoder);
81 
83  unsigned RegNo,
84  uint64_t Address,
85  const void *Decoder);
86 
88  unsigned RegNo,
89  uint64_t Address,
90  const void *Decoder);
91 
93  unsigned RegNo,
94  uint64_t Address,
95  const void *Decoder);
96 
98  unsigned Insn,
99  uint64_t Address,
100  const void *Decoder);
101 
103  unsigned RegNo,
104  uint64_t Address,
105  const void *Decoder);
106 
108  unsigned RegNo,
109  uint64_t Address,
110  const void *Decoder);
111 
113  unsigned RegNo,
114  uint64_t Address,
115  const void *Decoder);
116 
118  unsigned RegNo,
119  uint64_t Address,
120  const void *Decoder);
121 
123  unsigned RegNo,
124  uint64_t Address,
125  const void *Decoder);
126 
127 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
128  uint64_t Address,
129  const void *Decoder);
130 
132  unsigned Insn,
133  uint64_t Address,
134  const void *Decoder);
135 
137  unsigned RegNo,
138  uint64_t Address,
139  const void *Decoder);
140 
142  unsigned RegNo,
143  uint64_t Address,
144  const void *Decoder);
145 
147  unsigned RegNo,
148  uint64_t Address,
149  const void *Decoder);
150 
152  unsigned RegNo,
153  uint64_t Address,
154  const void *Decoder);
155 
157  unsigned RegNo,
158  uint64_t Address,
159  const void *Decoder);
160 
162  unsigned RegNo,
163  uint64_t Address,
164  const void *Decoder);
165 
167  unsigned RegNo,
168  uint64_t Address,
169  const void *Decoder);
170 
172  unsigned RegNo,
173  uint64_t Address,
174  const void *Decoder);
175 
177  unsigned RegNo,
178  uint64_t Address,
179  const void *Decoder);
180 
182  unsigned RegNo,
183  uint64_t Address,
184  const void *Decoder);
185 
187  unsigned RegNo,
188  uint64_t Address,
189  const void *Decoder);
190 
192  unsigned Offset,
193  uint64_t Address,
194  const void *Decoder);
195 
197  unsigned Insn,
198  uint64_t Address,
199  const void *Decoder);
200 
202  unsigned Offset,
203  uint64_t Address,
204  const void *Decoder);
205 
207  unsigned Offset,
208  uint64_t Address,
209  const void *Decoder);
210 
211 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is
212 // shifted left by 1 bit.
214  unsigned Offset,
215  uint64_t Address,
216  const void *Decoder);
217 
218 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is
219 // shifted left by 1 bit.
221  unsigned Offset,
222  uint64_t Address,
223  const void *Decoder);
224 
225 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
226 // shifted left by 1 bit.
228  unsigned Offset,
229  uint64_t Address,
230  const void *Decoder);
231 
232 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
233 // shifted left by 1 bit.
235  unsigned Insn,
236  uint64_t Address,
237  const void *Decoder);
238 
239 static DecodeStatus DecodeMem(MCInst &Inst,
240  unsigned Insn,
241  uint64_t Address,
242  const void *Decoder);
243 
244 static DecodeStatus DecodeCacheOp(MCInst &Inst,
245  unsigned Insn,
246  uint64_t Address,
247  const void *Decoder);
248 
249 static DecodeStatus DecodeCacheOpR6(MCInst &Inst,
250  unsigned Insn,
251  uint64_t Address,
252  const void *Decoder);
253 
254 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
255  unsigned Insn,
256  uint64_t Address,
257  const void *Decoder);
258 
259 static DecodeStatus DecodeSyncI(MCInst &Inst,
260  unsigned Insn,
261  uint64_t Address,
262  const void *Decoder);
263 
264 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
265  uint64_t Address, const void *Decoder);
266 
267 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
268  unsigned Insn,
269  uint64_t Address,
270  const void *Decoder);
271 
273  unsigned Insn,
274  uint64_t Address,
275  const void *Decoder);
276 
278  unsigned Insn,
279  uint64_t Address,
280  const void *Decoder);
281 
283  unsigned Insn,
284  uint64_t Address,
285  const void *Decoder);
286 
288  unsigned Insn,
289  uint64_t Address,
290  const void *Decoder);
291 
293  unsigned Insn,
294  uint64_t Address,
295  const void *Decoder);
296 
297 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
298  uint64_t Address,
299  const void *Decoder);
300 
301 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn,
302  uint64_t Address,
303  const void *Decoder);
304 
305 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn,
306  uint64_t Address,
307  const void *Decoder);
308 
309 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn,
310  uint64_t Address,
311  const void *Decoder);
312 
314  unsigned Insn,
315  uint64_t Address,
316  const void *Decoder);
317 
319  unsigned Value,
320  uint64_t Address,
321  const void *Decoder);
322 
323 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
324  unsigned Value,
325  uint64_t Address,
326  const void *Decoder);
327 
328 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
329  unsigned Value,
330  uint64_t Address,
331  const void *Decoder);
332 
333 static DecodeStatus DecodeSimm4(MCInst &Inst,
334  unsigned Value,
335  uint64_t Address,
336  const void *Decoder);
337 
338 static DecodeStatus DecodeSimm16(MCInst &Inst,
339  unsigned Insn,
340  uint64_t Address,
341  const void *Decoder);
342 
343 // Decode the immediate field of an LSA instruction which
344 // is off by one.
345 static DecodeStatus DecodeLSAImm(MCInst &Inst,
346  unsigned Insn,
347  uint64_t Address,
348  const void *Decoder);
349 
350 static DecodeStatus DecodeInsSize(MCInst &Inst,
351  unsigned Insn,
352  uint64_t Address,
353  const void *Decoder);
354 
355 static DecodeStatus DecodeExtSize(MCInst &Inst,
356  unsigned Insn,
357  uint64_t Address,
358  const void *Decoder);
359 
360 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
361  uint64_t Address, const void *Decoder);
362 
363 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
364  uint64_t Address, const void *Decoder);
365 
366 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
367  uint64_t Address, const void *Decoder);
368 
369 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
370  uint64_t Address, const void *Decoder);
371 
372 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
373  uint64_t Address, const void *Decoder);
374 
375 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
376  uint64_t Address, const void *Decoder);
377 
378 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
379 /// handle.
380 template <typename InsnType>
381 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
382  const void *Decoder);
383 
384 template <typename InsnType>
385 static DecodeStatus
386 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
387  const void *Decoder);
388 
389 template <typename InsnType>
390 static DecodeStatus
391 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
392  const void *Decoder);
393 
394 template <typename InsnType>
395 static DecodeStatus
396 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
397  const void *Decoder);
398 
399 template <typename InsnType>
400 static DecodeStatus
401 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
402  const void *Decoder);
403 
404 template <typename InsnType>
405 static DecodeStatus
406 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
407  const void *Decoder);
408 
409 template <typename InsnType>
410 static DecodeStatus
411 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
412  const void *Decoder);
413 
414 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
415  uint64_t Address,
416  const void *Decoder);
417 
418 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
419  uint64_t Address,
420  const void *Decoder);
421 
422 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn,
423  uint64_t Address,
424  const void *Decoder);
425 
426 namespace llvm {
429 }
430 
432  const Target &T,
433  const MCSubtargetInfo &STI,
434  MCContext &Ctx) {
435  return new MipsDisassembler(STI, Ctx, true);
436 }
437 
439  const Target &T,
440  const MCSubtargetInfo &STI,
441  MCContext &Ctx) {
442  return new MipsDisassembler(STI, Ctx, false);
443 }
444 
446  // Register the disassembler.
455 }
456 
457 #include "MipsGenDisassemblerTables.inc"
458 
459 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
460  const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D);
461  const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
462  return *(RegInfo->getRegClass(RC).begin() + RegNo);
463 }
464 
465 template <typename InsnType>
466 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
467  const void *Decoder) {
468  typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
469  // The size of the n field depends on the element size
470  // The register class also depends on this.
471  InsnType tmp = fieldFromInstruction(insn, 17, 5);
472  unsigned NSize = 0;
473  DecodeFN RegDecoder = nullptr;
474  if ((tmp & 0x18) == 0x00) { // INSVE_B
475  NSize = 4;
476  RegDecoder = DecodeMSA128BRegisterClass;
477  } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
478  NSize = 3;
479  RegDecoder = DecodeMSA128HRegisterClass;
480  } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
481  NSize = 2;
482  RegDecoder = DecodeMSA128WRegisterClass;
483  } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
484  NSize = 1;
485  RegDecoder = DecodeMSA128DRegisterClass;
486  } else
487  llvm_unreachable("Invalid encoding");
488 
489  assert(NSize != 0 && RegDecoder != nullptr);
490 
491  // $wd
492  tmp = fieldFromInstruction(insn, 6, 5);
493  if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
494  return MCDisassembler::Fail;
495  // $wd_in
496  if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
497  return MCDisassembler::Fail;
498  // $n
499  tmp = fieldFromInstruction(insn, 16, NSize);
501  // $ws
502  tmp = fieldFromInstruction(insn, 11, 5);
503  if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
504  return MCDisassembler::Fail;
505  // $n2
507 
509 }
510 
511 template <typename InsnType>
513  uint64_t Address,
514  const void *Decoder) {
515  // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
516  // (otherwise we would have matched the ADDI instruction from the earlier
517  // ISA's instead).
518  //
519  // We have:
520  // 0b001000 sssss ttttt iiiiiiiiiiiiiiii
521  // BOVC if rs >= rt
522  // BEQZALC if rs == 0 && rt != 0
523  // BEQC if rs < rt && rs != 0
524 
525  InsnType Rs = fieldFromInstruction(insn, 21, 5);
526  InsnType Rt = fieldFromInstruction(insn, 16, 5);
527  InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
528  bool HasRs = false;
529 
530  if (Rs >= Rt) {
531  MI.setOpcode(Mips::BOVC);
532  HasRs = true;
533  } else if (Rs != 0 && Rs < Rt) {
534  MI.setOpcode(Mips::BEQC);
535  HasRs = true;
536  } else
537  MI.setOpcode(Mips::BEQZALC);
538 
539  if (HasRs)
540  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
541  Rs)));
542 
543  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
544  Rt)));
546 
548 }
549 
550 template <typename InsnType>
552  uint64_t Address,
553  const void *Decoder) {
554  // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
555  // (otherwise we would have matched the ADDI instruction from the earlier
556  // ISA's instead).
557  //
558  // We have:
559  // 0b011000 sssss ttttt iiiiiiiiiiiiiiii
560  // BNVC if rs >= rt
561  // BNEZALC if rs == 0 && rt != 0
562  // BNEC if rs < rt && rs != 0
563 
564  InsnType Rs = fieldFromInstruction(insn, 21, 5);
565  InsnType Rt = fieldFromInstruction(insn, 16, 5);
566  InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
567  bool HasRs = false;
568 
569  if (Rs >= Rt) {
570  MI.setOpcode(Mips::BNVC);
571  HasRs = true;
572  } else if (Rs != 0 && Rs < Rt) {
573  MI.setOpcode(Mips::BNEC);
574  HasRs = true;
575  } else
576  MI.setOpcode(Mips::BNEZALC);
577 
578  if (HasRs)
579  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
580  Rs)));
581 
582  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
583  Rt)));
585 
587 }
588 
589 template <typename InsnType>
591  uint64_t Address,
592  const void *Decoder) {
593  // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
594  // (otherwise we would have matched the BLEZL instruction from the earlier
595  // ISA's instead).
596  //
597  // We have:
598  // 0b010110 sssss ttttt iiiiiiiiiiiiiiii
599  // Invalid if rs == 0
600  // BLEZC if rs == 0 && rt != 0
601  // BGEZC if rs == rt && rt != 0
602  // BGEC if rs != rt && rs != 0 && rt != 0
603 
604  InsnType Rs = fieldFromInstruction(insn, 21, 5);
605  InsnType Rt = fieldFromInstruction(insn, 16, 5);
606  InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
607  bool HasRs = false;
608 
609  if (Rt == 0)
610  return MCDisassembler::Fail;
611  else if (Rs == 0)
612  MI.setOpcode(Mips::BLEZC);
613  else if (Rs == Rt)
614  MI.setOpcode(Mips::BGEZC);
615  else {
616  HasRs = true;
617  MI.setOpcode(Mips::BGEC);
618  }
619 
620  if (HasRs)
621  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
622  Rs)));
623 
624  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
625  Rt)));
626 
628 
630 }
631 
632 template <typename InsnType>
634  uint64_t Address,
635  const void *Decoder) {
636  // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
637  // (otherwise we would have matched the BGTZL instruction from the earlier
638  // ISA's instead).
639  //
640  // We have:
641  // 0b010111 sssss ttttt iiiiiiiiiiiiiiii
642  // Invalid if rs == 0
643  // BGTZC if rs == 0 && rt != 0
644  // BLTZC if rs == rt && rt != 0
645  // BLTC if rs != rt && rs != 0 && rt != 0
646 
647  bool HasRs = false;
648 
649  InsnType Rs = fieldFromInstruction(insn, 21, 5);
650  InsnType Rt = fieldFromInstruction(insn, 16, 5);
651  InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
652 
653  if (Rt == 0)
654  return MCDisassembler::Fail;
655  else if (Rs == 0)
656  MI.setOpcode(Mips::BGTZC);
657  else if (Rs == Rt)
658  MI.setOpcode(Mips::BLTZC);
659  else {
660  MI.setOpcode(Mips::BLTC);
661  HasRs = true;
662  }
663 
664  if (HasRs)
665  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
666  Rs)));
667 
668  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
669  Rt)));
670 
672 
674 }
675 
676 template <typename InsnType>
678  uint64_t Address,
679  const void *Decoder) {
680  // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
681  // (otherwise we would have matched the BGTZ instruction from the earlier
682  // ISA's instead).
683  //
684  // We have:
685  // 0b000111 sssss ttttt iiiiiiiiiiiiiiii
686  // BGTZ if rt == 0
687  // BGTZALC if rs == 0 && rt != 0
688  // BLTZALC if rs != 0 && rs == rt
689  // BLTUC if rs != 0 && rs != rt
690 
691  InsnType Rs = fieldFromInstruction(insn, 21, 5);
692  InsnType Rt = fieldFromInstruction(insn, 16, 5);
693  InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
694  bool HasRs = false;
695  bool HasRt = false;
696 
697  if (Rt == 0) {
698  MI.setOpcode(Mips::BGTZ);
699  HasRs = true;
700  } else if (Rs == 0) {
701  MI.setOpcode(Mips::BGTZALC);
702  HasRt = true;
703  } else if (Rs == Rt) {
704  MI.setOpcode(Mips::BLTZALC);
705  HasRs = true;
706  } else {
707  MI.setOpcode(Mips::BLTUC);
708  HasRs = true;
709  HasRt = true;
710  }
711 
712  if (HasRs)
713  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
714  Rs)));
715 
716  if (HasRt)
717  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
718  Rt)));
719 
721 
723 }
724 
725 template <typename InsnType>
727  uint64_t Address,
728  const void *Decoder) {
729  // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
730  // (otherwise we would have matched the BLEZL instruction from the earlier
731  // ISA's instead).
732  //
733  // We have:
734  // 0b000110 sssss ttttt iiiiiiiiiiiiiiii
735  // Invalid if rs == 0
736  // BLEZALC if rs == 0 && rt != 0
737  // BGEZALC if rs == rt && rt != 0
738  // BGEUC if rs != rt && rs != 0 && rt != 0
739 
740  InsnType Rs = fieldFromInstruction(insn, 21, 5);
741  InsnType Rt = fieldFromInstruction(insn, 16, 5);
742  InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
743  bool HasRs = false;
744 
745  if (Rt == 0)
746  return MCDisassembler::Fail;
747  else if (Rs == 0)
748  MI.setOpcode(Mips::BLEZALC);
749  else if (Rs == Rt)
750  MI.setOpcode(Mips::BGEZALC);
751  else {
752  HasRs = true;
753  MI.setOpcode(Mips::BGEUC);
754  }
755 
756  if (HasRs)
757  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
758  Rs)));
759  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
760  Rt)));
761 
763 
765 }
766 
767 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted
768 /// according to the given endianess.
770  uint64_t &Size, uint32_t &Insn,
771  bool IsBigEndian) {
772  // We want to read exactly 2 Bytes of data.
773  if (Bytes.size() < 2) {
774  Size = 0;
775  return MCDisassembler::Fail;
776  }
777 
778  if (IsBigEndian) {
779  Insn = (Bytes[0] << 8) | Bytes[1];
780  } else {
781  Insn = (Bytes[1] << 8) | Bytes[0];
782  }
783 
785 }
786 
787 /// Read four bytes from the ArrayRef and return 32 bit word sorted
788 /// according to the given endianess
790  uint64_t &Size, uint32_t &Insn,
791  bool IsBigEndian, bool IsMicroMips) {
792  // We want to read exactly 4 Bytes of data.
793  if (Bytes.size() < 4) {
794  Size = 0;
795  return MCDisassembler::Fail;
796  }
797 
798  // High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
799  // always precede the low 16 bits in the instruction stream (that is, they
800  // are placed at lower addresses in the instruction stream).
801  //
802  // microMIPS byte ordering:
803  // Big-endian: 0 | 1 | 2 | 3
804  // Little-endian: 1 | 0 | 3 | 2
805 
806  if (IsBigEndian) {
807  // Encoded as a big-endian 32-bit word in the stream.
808  Insn =
809  (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
810  } else {
811  if (IsMicroMips) {
812  Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
813  (Bytes[1] << 24);
814  } else {
815  Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
816  (Bytes[3] << 24);
817  }
818  }
819 
821 }
822 
823 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
824  ArrayRef<uint8_t> Bytes,
825  uint64_t Address,
826  raw_ostream &VStream,
827  raw_ostream &CStream) const {
828  uint32_t Insn;
829  DecodeStatus Result;
830 
831  if (IsMicroMips) {
832  Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
833 
834  DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n");
835  // Calling the auto-generated decoder function.
836  Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address,
837  this, STI);
838  if (Result != MCDisassembler::Fail) {
839  Size = 2;
840  return Result;
841  }
842 
843  Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true);
844  if (Result == MCDisassembler::Fail)
845  return MCDisassembler::Fail;
846 
847  if (hasMips32r6()) {
848  DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n");
849  // Calling the auto-generated decoder function.
850  Result = decodeInstruction(DecoderTableMicroMips32r632, Instr, Insn, Address,
851  this, STI);
852  } else {
853  DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
854  // Calling the auto-generated decoder function.
855  Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
856  this, STI);
857  }
858  if (Result != MCDisassembler::Fail) {
859  Size = 4;
860  return Result;
861  }
862  return MCDisassembler::Fail;
863  }
864 
865  Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
866  if (Result == MCDisassembler::Fail)
867  return MCDisassembler::Fail;
868 
869  if (hasCOP3()) {
870  DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
871  Result =
872  decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);
873  if (Result != MCDisassembler::Fail) {
874  Size = 4;
875  return Result;
876  }
877  }
878 
879  if (hasMips32r6() && isGP64()) {
880  DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
881  Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
882  Address, this, STI);
883  if (Result != MCDisassembler::Fail) {
884  Size = 4;
885  return Result;
886  }
887  }
888 
889  if (hasMips32r6()) {
890  DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
891  Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,
892  Address, this, STI);
893  if (Result != MCDisassembler::Fail) {
894  Size = 4;
895  return Result;
896  }
897  }
898 
899  if (hasCnMips()) {
900  DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n");
901  Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn,
902  Address, this, STI);
903  if (Result != MCDisassembler::Fail) {
904  Size = 4;
905  return Result;
906  }
907  }
908 
909  if (isGP64()) {
910  DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n");
911  Result = decodeInstruction(DecoderTableMips6432, Instr, Insn,
912  Address, this, STI);
913  if (Result != MCDisassembler::Fail) {
914  Size = 4;
915  return Result;
916  }
917  }
918 
919  DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
920  // Calling the auto-generated decoder function.
921  Result =
922  decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
923  if (Result != MCDisassembler::Fail) {
924  Size = 4;
925  return Result;
926  }
927 
928  return MCDisassembler::Fail;
929 }
930 
932  unsigned RegNo,
933  uint64_t Address,
934  const void *Decoder) {
935 
936  return MCDisassembler::Fail;
937 
938 }
939 
941  unsigned RegNo,
942  uint64_t Address,
943  const void *Decoder) {
944 
945  if (RegNo > 31)
946  return MCDisassembler::Fail;
947 
948  unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
949  Inst.addOperand(MCOperand::createReg(Reg));
951 }
952 
954  unsigned RegNo,
955  uint64_t Address,
956  const void *Decoder) {
957  if (RegNo > 7)
958  return MCDisassembler::Fail;
959  unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
960  Inst.addOperand(MCOperand::createReg(Reg));
962 }
963 
965  unsigned RegNo,
966  uint64_t Address,
967  const void *Decoder) {
968  if (RegNo > 7)
969  return MCDisassembler::Fail;
970  unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);
971  Inst.addOperand(MCOperand::createReg(Reg));
973 }
974 
976  unsigned RegNo,
977  uint64_t Address,
978  const void *Decoder) {
979  if (RegNo > 7)
980  return MCDisassembler::Fail;
981  unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo);
982  Inst.addOperand(MCOperand::createReg(Reg));
984 }
985 
987  unsigned RegNo,
988  uint64_t Address,
989  const void *Decoder) {
990  if (RegNo > 31)
991  return MCDisassembler::Fail;
992  unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
993  Inst.addOperand(MCOperand::createReg(Reg));
995 }
996 
998  unsigned RegNo,
999  uint64_t Address,
1000  const void *Decoder) {
1001  if (static_cast<const MipsDisassembler *>(Decoder)->isGP64())
1002  return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
1003 
1004  return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1005 }
1006 
1008  unsigned RegNo,
1009  uint64_t Address,
1010  const void *Decoder) {
1011  return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1012 }
1013 
1015  unsigned RegNo,
1016  uint64_t Address,
1017  const void *Decoder) {
1018  if (RegNo > 31)
1019  return MCDisassembler::Fail;
1020 
1021  unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
1022  Inst.addOperand(MCOperand::createReg(Reg));
1023  return MCDisassembler::Success;
1024 }
1025 
1027  unsigned RegNo,
1028  uint64_t Address,
1029  const void *Decoder) {
1030  if (RegNo > 31)
1031  return MCDisassembler::Fail;
1032 
1033  unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
1034  Inst.addOperand(MCOperand::createReg(Reg));
1035  return MCDisassembler::Success;
1036 }
1037 
1039  unsigned RegNo,
1040  uint64_t Address,
1041  const void *Decoder) {
1042  if (RegNo > 31)
1043  return MCDisassembler::Fail;
1044  unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
1045  Inst.addOperand(MCOperand::createReg(Reg));
1046  return MCDisassembler::Success;
1047 }
1048 
1050  unsigned RegNo,
1051  uint64_t Address,
1052  const void *Decoder) {
1053  if (RegNo > 7)
1054  return MCDisassembler::Fail;
1055  unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
1056  Inst.addOperand(MCOperand::createReg(Reg));
1057  return MCDisassembler::Success;
1058 }
1059 
1060 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
1061  uint64_t Address,
1062  const void *Decoder) {
1063  if (RegNo > 31)
1064  return MCDisassembler::Fail;
1065 
1066  unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
1067  Inst.addOperand(MCOperand::createReg(Reg));
1068  return MCDisassembler::Success;
1069 }
1070 
1072  unsigned Insn,
1073  uint64_t Address,
1074  const void *Decoder) {
1075  int Offset = SignExtend32<16>(Insn & 0xffff);
1076  unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1077  unsigned Base = fieldFromInstruction(Insn, 21, 5);
1078 
1079  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1080  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1081 
1082  if(Inst.getOpcode() == Mips::SC ||
1083  Inst.getOpcode() == Mips::SCD){
1084  Inst.addOperand(MCOperand::createReg(Reg));
1085  }
1086 
1087  Inst.addOperand(MCOperand::createReg(Reg));
1088  Inst.addOperand(MCOperand::createReg(Base));
1089  Inst.addOperand(MCOperand::createImm(Offset));
1090 
1091  return MCDisassembler::Success;
1092 }
1093 
1095  unsigned Insn,
1096  uint64_t Address,
1097  const void *Decoder) {
1098  int Offset = SignExtend32<16>(Insn & 0xffff);
1099  unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1100  unsigned Base = fieldFromInstruction(Insn, 21, 5);
1101 
1102  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1103 
1104  Inst.addOperand(MCOperand::createReg(Base));
1105  Inst.addOperand(MCOperand::createImm(Offset));
1106  Inst.addOperand(MCOperand::createImm(Hint));
1107 
1108  return MCDisassembler::Success;
1109 }
1110 
1112  unsigned Insn,
1113  uint64_t Address,
1114  const void *Decoder) {
1115  int Offset = SignExtend32<12>(Insn & 0xfff);
1116  unsigned Base = fieldFromInstruction(Insn, 16, 5);
1117  unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1118 
1119  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1120 
1121  Inst.addOperand(MCOperand::createReg(Base));
1122  Inst.addOperand(MCOperand::createImm(Offset));
1123  Inst.addOperand(MCOperand::createImm(Hint));
1124 
1125  return MCDisassembler::Success;
1126 }
1127 
1129  unsigned Insn,
1130  uint64_t Address,
1131  const void *Decoder) {
1132  int Offset = fieldFromInstruction(Insn, 7, 9);
1133  unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1134  unsigned Base = fieldFromInstruction(Insn, 21, 5);
1135 
1136  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1137 
1138  Inst.addOperand(MCOperand::createReg(Base));
1139  Inst.addOperand(MCOperand::createImm(Offset));
1140  Inst.addOperand(MCOperand::createImm(Hint));
1141 
1142  return MCDisassembler::Success;
1143 }
1144 
1146  unsigned Insn,
1147  uint64_t Address,
1148  const void *Decoder) {
1149  int Offset = SignExtend32<16>(Insn & 0xffff);
1150  unsigned Base = fieldFromInstruction(Insn, 21, 5);
1151 
1152  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1153 
1154  Inst.addOperand(MCOperand::createReg(Base));
1155  Inst.addOperand(MCOperand::createImm(Offset));
1156 
1157  return MCDisassembler::Success;
1158 }
1159 
1160 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
1161  uint64_t Address, const void *Decoder) {
1162  int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
1163  unsigned Reg = fieldFromInstruction(Insn, 6, 5);
1164  unsigned Base = fieldFromInstruction(Insn, 11, 5);
1165 
1166  Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
1167  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1168 
1169  Inst.addOperand(MCOperand::createReg(Reg));
1170  Inst.addOperand(MCOperand::createReg(Base));
1171 
1172  // The immediate field of an LD/ST instruction is scaled which means it must
1173  // be multiplied (when decoding) by the size (in bytes) of the instructions'
1174  // data format.
1175  // .b - 1 byte
1176  // .h - 2 bytes
1177  // .w - 4 bytes
1178  // .d - 8 bytes
1179  switch(Inst.getOpcode())
1180  {
1181  default:
1182  assert (0 && "Unexpected instruction");
1183  return MCDisassembler::Fail;
1184  break;
1185  case Mips::LD_B:
1186  case Mips::ST_B:
1187  Inst.addOperand(MCOperand::createImm(Offset));
1188  break;
1189  case Mips::LD_H:
1190  case Mips::ST_H:
1191  Inst.addOperand(MCOperand::createImm(Offset * 2));
1192  break;
1193  case Mips::LD_W:
1194  case Mips::ST_W:
1195  Inst.addOperand(MCOperand::createImm(Offset * 4));
1196  break;
1197  case Mips::LD_D:
1198  case Mips::ST_D:
1199  Inst.addOperand(MCOperand::createImm(Offset * 8));
1200  break;
1201  }
1202 
1203  return MCDisassembler::Success;
1204 }
1205 
1207  unsigned Insn,
1208  uint64_t Address,
1209  const void *Decoder) {
1210  unsigned Offset = Insn & 0xf;
1211  unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1212  unsigned Base = fieldFromInstruction(Insn, 4, 3);
1213 
1214  switch (Inst.getOpcode()) {
1215  case Mips::LBU16_MM:
1216  case Mips::LHU16_MM:
1217  case Mips::LW16_MM:
1218  if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)
1220  return MCDisassembler::Fail;
1221  break;
1222  case Mips::SB16_MM:
1223  case Mips::SH16_MM:
1224  case Mips::SW16_MM:
1225  if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)
1227  return MCDisassembler::Fail;
1228  break;
1229  }
1230 
1231  if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)
1233  return MCDisassembler::Fail;
1234 
1235  switch (Inst.getOpcode()) {
1236  case Mips::LBU16_MM:
1237  if (Offset == 0xf)
1238  Inst.addOperand(MCOperand::createImm(-1));
1239  else
1240  Inst.addOperand(MCOperand::createImm(Offset));
1241  break;
1242  case Mips::SB16_MM:
1243  Inst.addOperand(MCOperand::createImm(Offset));
1244  break;
1245  case Mips::LHU16_MM:
1246  case Mips::SH16_MM:
1247  Inst.addOperand(MCOperand::createImm(Offset << 1));
1248  break;
1249  case Mips::LW16_MM:
1250  case Mips::SW16_MM:
1251  Inst.addOperand(MCOperand::createImm(Offset << 2));
1252  break;
1253  }
1254 
1255  return MCDisassembler::Success;
1256 }
1257 
1259  unsigned Insn,
1260  uint64_t Address,
1261  const void *Decoder) {
1262  unsigned Offset = Insn & 0x1F;
1263  unsigned Reg = fieldFromInstruction(Insn, 5, 5);
1264 
1265  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1266 
1267  Inst.addOperand(MCOperand::createReg(Reg));
1268  Inst.addOperand(MCOperand::createReg(Mips::SP));
1269  Inst.addOperand(MCOperand::createImm(Offset << 2));
1270 
1271  return MCDisassembler::Success;
1272 }
1273 
1275  unsigned Insn,
1276  uint64_t Address,
1277  const void *Decoder) {
1278  unsigned Offset = Insn & 0x7F;
1279  unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1280 
1281  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1282 
1283  Inst.addOperand(MCOperand::createReg(Reg));
1284  Inst.addOperand(MCOperand::createReg(Mips::GP));
1285  Inst.addOperand(MCOperand::createImm(Offset << 2));
1286 
1287  return MCDisassembler::Success;
1288 }
1289 
1291  unsigned Insn,
1292  uint64_t Address,
1293  const void *Decoder) {
1294  int Offset = SignExtend32<4>(Insn & 0xf);
1295 
1296  if (DecodeRegListOperand16(Inst, Insn, Address, Decoder)
1298  return MCDisassembler::Fail;
1299 
1300  Inst.addOperand(MCOperand::createReg(Mips::SP));
1301  Inst.addOperand(MCOperand::createImm(Offset << 2));
1302 
1303  return MCDisassembler::Success;
1304 }
1305 
1307  unsigned Insn,
1308  uint64_t Address,
1309  const void *Decoder) {
1310  int Offset = SignExtend32<12>(Insn & 0x0fff);
1311  unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1312  unsigned Base = fieldFromInstruction(Insn, 16, 5);
1313 
1314  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1315  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1316 
1317  switch (Inst.getOpcode()) {
1318  case Mips::SWM32_MM:
1319  case Mips::LWM32_MM:
1320  if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
1322  return MCDisassembler::Fail;
1323  Inst.addOperand(MCOperand::createReg(Base));
1324  Inst.addOperand(MCOperand::createImm(Offset));
1325  break;
1326  case Mips::SC_MM:
1327  Inst.addOperand(MCOperand::createReg(Reg));
1328  // fallthrough
1329  default:
1330  Inst.addOperand(MCOperand::createReg(Reg));
1331  if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)
1332  Inst.addOperand(MCOperand::createReg(Reg+1));
1333 
1334  Inst.addOperand(MCOperand::createReg(Base));
1335  Inst.addOperand(MCOperand::createImm(Offset));
1336  }
1337 
1338  return MCDisassembler::Success;
1339 }
1340 
1342  unsigned Insn,
1343  uint64_t Address,
1344  const void *Decoder) {
1345  int Offset = SignExtend32<16>(Insn & 0xffff);
1346  unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1347  unsigned Base = fieldFromInstruction(Insn, 16, 5);
1348 
1349  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1350  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1351 
1352  Inst.addOperand(MCOperand::createReg(Reg));
1353  Inst.addOperand(MCOperand::createReg(Base));
1354  Inst.addOperand(MCOperand::createImm(Offset));
1355 
1356  return MCDisassembler::Success;
1357 }
1358 
1360  unsigned Insn,
1361  uint64_t Address,
1362  const void *Decoder) {
1363  int Offset = SignExtend32<16>(Insn & 0xffff);
1364  unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1365  unsigned Base = fieldFromInstruction(Insn, 21, 5);
1366 
1367  Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1368  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1369 
1370  Inst.addOperand(MCOperand::createReg(Reg));
1371  Inst.addOperand(MCOperand::createReg(Base));
1372  Inst.addOperand(MCOperand::createImm(Offset));
1373 
1374  return MCDisassembler::Success;
1375 }
1376 
1378  unsigned Insn,
1379  uint64_t Address,
1380  const void *Decoder) {
1381  int Offset = SignExtend32<16>(Insn & 0xffff);
1382  unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1383  unsigned Base = fieldFromInstruction(Insn, 21, 5);
1384 
1385  Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1386  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1387 
1388  Inst.addOperand(MCOperand::createReg(Reg));
1389  Inst.addOperand(MCOperand::createReg(Base));
1390  Inst.addOperand(MCOperand::createImm(Offset));
1391 
1392  return MCDisassembler::Success;
1393 }
1394 
1396  unsigned Insn,
1397  uint64_t Address,
1398  const void *Decoder) {
1399  int Offset = SignExtend32<16>(Insn & 0xffff);
1400  unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1401  unsigned Base = fieldFromInstruction(Insn, 21, 5);
1402 
1403  Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
1404  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1405 
1406  Inst.addOperand(MCOperand::createReg(Reg));
1407  Inst.addOperand(MCOperand::createReg(Base));
1408  Inst.addOperand(MCOperand::createImm(Offset));
1409 
1410  return MCDisassembler::Success;
1411 }
1412 
1414  unsigned Insn,
1415  uint64_t Address,
1416  const void *Decoder) {
1417  int Offset = SignExtend32<11>(Insn & 0x07ff);
1418  unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1419  unsigned Base = fieldFromInstruction(Insn, 11, 5);
1420 
1421  Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1422  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1423 
1424  Inst.addOperand(MCOperand::createReg(Reg));
1425  Inst.addOperand(MCOperand::createReg(Base));
1426  Inst.addOperand(MCOperand::createImm(Offset));
1427 
1428  return MCDisassembler::Success;
1429 }
1431  unsigned Insn,
1432  uint64_t Address,
1433  const void *Decoder) {
1434  int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
1435  unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1436  unsigned Base = fieldFromInstruction(Insn, 21, 5);
1437 
1438  Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
1439  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1440 
1441  if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
1442  Inst.addOperand(MCOperand::createReg(Rt));
1443  }
1444 
1445  Inst.addOperand(MCOperand::createReg(Rt));
1446  Inst.addOperand(MCOperand::createReg(Base));
1447  Inst.addOperand(MCOperand::createImm(Offset));
1448 
1449  return MCDisassembler::Success;
1450 }
1451 
1453  unsigned RegNo,
1454  uint64_t Address,
1455  const void *Decoder) {
1456  // Currently only hardware register 29 is supported.
1457  if (RegNo != 29)
1458  return MCDisassembler::Fail;
1459  Inst.addOperand(MCOperand::createReg(Mips::HWR29));
1460  return MCDisassembler::Success;
1461 }
1462 
1464  unsigned RegNo,
1465  uint64_t Address,
1466  const void *Decoder) {
1467  if (RegNo > 30 || RegNo %2)
1468  return MCDisassembler::Fail;
1469 
1470  ;
1471  unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
1472  Inst.addOperand(MCOperand::createReg(Reg));
1473  return MCDisassembler::Success;
1474 }
1475 
1477  unsigned RegNo,
1478  uint64_t Address,
1479  const void *Decoder) {
1480  if (RegNo >= 4)
1481  return MCDisassembler::Fail;
1482 
1483  unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
1484  Inst.addOperand(MCOperand::createReg(Reg));
1485  return MCDisassembler::Success;
1486 }
1487 
1489  unsigned RegNo,
1490  uint64_t Address,
1491  const void *Decoder) {
1492  if (RegNo >= 4)
1493  return MCDisassembler::Fail;
1494 
1495  unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
1496  Inst.addOperand(MCOperand::createReg(Reg));
1497  return MCDisassembler::Success;
1498 }
1499 
1501  unsigned RegNo,
1502  uint64_t Address,
1503  const void *Decoder) {
1504  if (RegNo >= 4)
1505  return MCDisassembler::Fail;
1506 
1507  unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
1508  Inst.addOperand(MCOperand::createReg(Reg));
1509  return MCDisassembler::Success;
1510 }
1511 
1513  unsigned RegNo,
1514  uint64_t Address,
1515  const void *Decoder) {
1516  if (RegNo > 31)
1517  return MCDisassembler::Fail;
1518 
1519  unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
1520  Inst.addOperand(MCOperand::createReg(Reg));
1521  return MCDisassembler::Success;
1522 }
1523 
1525  unsigned RegNo,
1526  uint64_t Address,
1527  const void *Decoder) {
1528  if (RegNo > 31)
1529  return MCDisassembler::Fail;
1530 
1531  unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
1532  Inst.addOperand(MCOperand::createReg(Reg));
1533  return MCDisassembler::Success;
1534 }
1535 
1537  unsigned RegNo,
1538  uint64_t Address,
1539  const void *Decoder) {
1540  if (RegNo > 31)
1541  return MCDisassembler::Fail;
1542 
1543  unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
1544  Inst.addOperand(MCOperand::createReg(Reg));
1545  return MCDisassembler::Success;
1546 }
1547 
1549  unsigned RegNo,
1550  uint64_t Address,
1551  const void *Decoder) {
1552  if (RegNo > 31)
1553  return MCDisassembler::Fail;
1554 
1555  unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
1556  Inst.addOperand(MCOperand::createReg(Reg));
1557  return MCDisassembler::Success;
1558 }
1559 
1561  unsigned RegNo,
1562  uint64_t Address,
1563  const void *Decoder) {
1564  if (RegNo > 7)
1565  return MCDisassembler::Fail;
1566 
1567  unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
1568  Inst.addOperand(MCOperand::createReg(Reg));
1569  return MCDisassembler::Success;
1570 }
1571 
1573  unsigned RegNo,
1574  uint64_t Address,
1575  const void *Decoder) {
1576  if (RegNo > 31)
1577  return MCDisassembler::Fail;
1578 
1579  unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo);
1580  Inst.addOperand(MCOperand::createReg(Reg));
1581  return MCDisassembler::Success;
1582 }
1583 
1585  unsigned RegNo,
1586  uint64_t Address,
1587  const void *Decoder) {
1588  if (RegNo > 31)
1589  return MCDisassembler::Fail;
1590 
1591  unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
1592  Inst.addOperand(MCOperand::createReg(Reg));
1593  return MCDisassembler::Success;
1594 }
1595 
1597  unsigned Offset,
1598  uint64_t Address,
1599  const void *Decoder) {
1600  int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
1601  Inst.addOperand(MCOperand::createImm(BranchOffset));
1602  return MCDisassembler::Success;
1603 }
1604 
1606  unsigned Insn,
1607  uint64_t Address,
1608  const void *Decoder) {
1609 
1610  unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1611  Inst.addOperand(MCOperand::createImm(JumpOffset));
1612  return MCDisassembler::Success;
1613 }
1614 
1616  unsigned Offset,
1617  uint64_t Address,
1618  const void *Decoder) {
1619  int32_t BranchOffset = SignExtend32<21>(Offset) * 4;
1620 
1621  Inst.addOperand(MCOperand::createImm(BranchOffset));
1622  return MCDisassembler::Success;
1623 }
1624 
1626  unsigned Offset,
1627  uint64_t Address,
1628  const void *Decoder) {
1629  int32_t BranchOffset = SignExtend32<26>(Offset) * 4;
1630 
1631  Inst.addOperand(MCOperand::createImm(BranchOffset));
1632  return MCDisassembler::Success;
1633 }
1634 
1636  unsigned Offset,
1637  uint64_t Address,
1638  const void *Decoder) {
1639  int32_t BranchOffset = SignExtend32<7>(Offset) << 1;
1640  Inst.addOperand(MCOperand::createImm(BranchOffset));
1641  return MCDisassembler::Success;
1642 }
1643 
1645  unsigned Offset,
1646  uint64_t Address,
1647  const void *Decoder) {
1648  int32_t BranchOffset = SignExtend32<10>(Offset) << 1;
1649  Inst.addOperand(MCOperand::createImm(BranchOffset));
1650  return MCDisassembler::Success;
1651 }
1652 
1654  unsigned Offset,
1655  uint64_t Address,
1656  const void *Decoder) {
1657  int32_t BranchOffset = SignExtend32<16>(Offset) * 2;
1658  Inst.addOperand(MCOperand::createImm(BranchOffset));
1659  return MCDisassembler::Success;
1660 }
1661 
1663  unsigned Insn,
1664  uint64_t Address,
1665  const void *Decoder) {
1666  unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1667  Inst.addOperand(MCOperand::createImm(JumpOffset));
1668  return MCDisassembler::Success;
1669 }
1670 
1672  unsigned Value,
1673  uint64_t Address,
1674  const void *Decoder) {
1675  if (Value == 0)
1677  else if (Value == 0x7)
1678  Inst.addOperand(MCOperand::createImm(-1));
1679  else
1680  Inst.addOperand(MCOperand::createImm(Value << 2));
1681  return MCDisassembler::Success;
1682 }
1683 
1685  unsigned Value,
1686  uint64_t Address,
1687  const void *Decoder) {
1688  Inst.addOperand(MCOperand::createImm(Value << 2));
1689  return MCDisassembler::Success;
1690 }
1691 
1693  unsigned Value,
1694  uint64_t Address,
1695  const void *Decoder) {
1696  if (Value == 0x7F)
1697  Inst.addOperand(MCOperand::createImm(-1));
1698  else
1699  Inst.addOperand(MCOperand::createImm(Value));
1700  return MCDisassembler::Success;
1701 }
1702 
1704  unsigned Value,
1705  uint64_t Address,
1706  const void *Decoder) {
1707  Inst.addOperand(MCOperand::createImm(SignExtend32<4>(Value)));
1708  return MCDisassembler::Success;
1709 }
1710 
1712  unsigned Insn,
1713  uint64_t Address,
1714  const void *Decoder) {
1715  Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Insn)));
1716  return MCDisassembler::Success;
1717 }
1718 
1720  unsigned Insn,
1721  uint64_t Address,
1722  const void *Decoder) {
1723  // We add one to the immediate field as it was encoded as 'imm - 1'.
1724  Inst.addOperand(MCOperand::createImm(Insn + 1));
1725  return MCDisassembler::Success;
1726 }
1727 
1729  unsigned Insn,
1730  uint64_t Address,
1731  const void *Decoder) {
1732  // First we need to grab the pos(lsb) from MCInst.
1733  int Pos = Inst.getOperand(2).getImm();
1734  int Size = (int) Insn - Pos + 1;
1735  Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
1736  return MCDisassembler::Success;
1737 }
1738 
1740  unsigned Insn,
1741  uint64_t Address,
1742  const void *Decoder) {
1743  int Size = (int) Insn + 1;
1744  Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
1745  return MCDisassembler::Success;
1746 }
1747 
1748 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1749  uint64_t Address, const void *Decoder) {
1750  Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4));
1751  return MCDisassembler::Success;
1752 }
1753 
1754 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1755  uint64_t Address, const void *Decoder) {
1756  Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8));
1757  return MCDisassembler::Success;
1758 }
1759 
1760 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
1761  uint64_t Address, const void *Decoder) {
1762  int32_t DecodedValue;
1763  switch (Insn) {
1764  case 0: DecodedValue = 256; break;
1765  case 1: DecodedValue = 257; break;
1766  case 510: DecodedValue = -258; break;
1767  case 511: DecodedValue = -257; break;
1768  default: DecodedValue = SignExtend32<9>(Insn); break;
1769  }
1770  Inst.addOperand(MCOperand::createImm(DecodedValue * 4));
1771  return MCDisassembler::Success;
1772 }
1773 
1774 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
1775  uint64_t Address, const void *Decoder) {
1776  // Insn must be >= 0, since it is unsigned that condition is always true.
1777  assert(Insn < 16);
1778  int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
1779  255, 32768, 65535};
1780  Inst.addOperand(MCOperand::createImm(DecodedValues[Insn]));
1781  return MCDisassembler::Success;
1782 }
1783 
1784 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
1785  uint64_t Address, const void *Decoder) {
1786  Inst.addOperand(MCOperand::createImm(Insn << 2));
1787  return MCDisassembler::Success;
1788 }
1789 
1791  unsigned Insn,
1792  uint64_t Address,
1793  const void *Decoder) {
1794  unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
1795  Mips::S6, Mips::FP};
1796  unsigned RegNum;
1797 
1798  unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
1799  // Empty register lists are not allowed.
1800  if (RegLst == 0)
1801  return MCDisassembler::Fail;
1802 
1803  RegNum = RegLst & 0xf;
1804  for (unsigned i = 0; i < RegNum; i++)
1805  Inst.addOperand(MCOperand::createReg(Regs[i]));
1806 
1807  if (RegLst & 0x10)
1808  Inst.addOperand(MCOperand::createReg(Mips::RA));
1809 
1810  return MCDisassembler::Success;
1811 }
1812 
1813 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
1814  uint64_t Address,
1815  const void *Decoder) {
1816  unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
1817  unsigned RegLst = fieldFromInstruction(Insn, 4, 2);
1818  unsigned RegNum = RegLst & 0x3;
1819 
1820  for (unsigned i = 0; i <= RegNum; i++)
1821  Inst.addOperand(MCOperand::createReg(Regs[i]));
1822 
1823  Inst.addOperand(MCOperand::createReg(Mips::RA));
1824 
1825  return MCDisassembler::Success;
1826 }
1827 
1828 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn,
1829  uint64_t Address, const void *Decoder) {
1830 
1831  unsigned RegPair = fieldFromInstruction(Insn, 7, 3);
1832 
1833  switch (RegPair) {
1834  default:
1835  return MCDisassembler::Fail;
1836  case 0:
1837  Inst.addOperand(MCOperand::createReg(Mips::A1));
1838  Inst.addOperand(MCOperand::createReg(Mips::A2));
1839  break;
1840  case 1:
1841  Inst.addOperand(MCOperand::createReg(Mips::A1));
1842  Inst.addOperand(MCOperand::createReg(Mips::A3));
1843  break;
1844  case 2:
1845  Inst.addOperand(MCOperand::createReg(Mips::A2));
1846  Inst.addOperand(MCOperand::createReg(Mips::A3));
1847  break;
1848  case 3:
1849  Inst.addOperand(MCOperand::createReg(Mips::A0));
1850  Inst.addOperand(MCOperand::createReg(Mips::S5));
1851  break;
1852  case 4:
1853  Inst.addOperand(MCOperand::createReg(Mips::A0));
1854  Inst.addOperand(MCOperand::createReg(Mips::S6));
1855  break;
1856  case 5:
1857  Inst.addOperand(MCOperand::createReg(Mips::A0));
1858  Inst.addOperand(MCOperand::createReg(Mips::A1));
1859  break;
1860  case 6:
1861  Inst.addOperand(MCOperand::createReg(Mips::A0));
1862  Inst.addOperand(MCOperand::createReg(Mips::A2));
1863  break;
1864  case 7:
1865  Inst.addOperand(MCOperand::createReg(Mips::A0));
1866  Inst.addOperand(MCOperand::createReg(Mips::A3));
1867  break;
1868  }
1869 
1870  return MCDisassembler::Success;
1871 }
1872 
1873 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
1874  uint64_t Address, const void *Decoder) {
1875  Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2)));
1876  return MCDisassembler::Success;
1877 }
static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSimm16(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBranchTarget21(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
INSVE_[BHWD] have an implicit operand that the generated decoder doesn't handle.
static DecodeStatus DecodeCacheOpR6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
DecodeStatus
Ternary decode status.
static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Superclass for all disassemblers.
static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBranchTarget(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSyncI(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static MCDisassembler * createMipsDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
aarch64 collect AArch64 Collect Linker Optimization Hint(LOH)"
static DecodeStatus DecodeMemMMImm4(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:111
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Reg
All possible values of the reg field in the ModR/M byte.
static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Context object for machine code objects.
Definition: MCContext.h:48
static DecodeStatus DecodeMemMMImm12(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
int decodeInstruction(InternalInstruction *insn, byteReader_t reader, const void *readerArg, dlog_t logger, void *loggerArg, const void *miiArg, uint64_t startLoc, DisassemblerMode mode)
Decode one instruction and store the decoding results in a buffer provided by the consumer...
Target TheMips64elTarget
static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:134
static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:150
Target TheMips64Target
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
static DecodeStatus DecodeExtSize(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static MCDisassembler * createMipselDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
void LLVMInitializeMipsDisassembler()
static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeCacheOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
void setOpcode(unsigned Op)
Definition: MCInst.h:158
int64_t SignExtend64(uint64_t x)
SignExtend64 - Sign extend B-bit number x to 64-bit int.
Definition: MathExtras.h:634
static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus readInstruction16(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsBigEndian)
Read two bytes from the ArrayRef and return 16 bit halfword sorted according to the given endianess...
static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
CHAIN = SC CHAIN, Imm128 - System call.
static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:123
unsigned getOpcode() const
Definition: MCInst.h:159
Target - Wrapper for Target specific information.
static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
static DecodeStatus DecodeSimm4(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder)
int64_t getImm() const
Definition: MCInst.h:74
static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
MCDisassembler::DecodeStatus DecodeStatus
static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeLSAImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
MCSubtargetInfo - Generic base class for all target subtargets.
Target TheMipselTarget
static DecodeStatus DecodeBranchTarget26(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
iterator begin() const
begin/end - Return all of the registers in this class.
static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
LLVM Value Representation.
Definition: Value.h:69
static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeJumpTarget(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:38
#define DEBUG(X)
Definition: Debug.h:92
static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
void addOperand(const MCOperand &Op)
Definition: MCInst.h:168
static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus readInstruction32(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsBigEndian, bool IsMicroMips)
Read four bytes from the ArrayRef and return 32 bit word sorted according to the given endianess...
static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:117
static DecodeStatus DecodeLiSimm7(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:164
Target TheMipsTarget
static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMemMMImm16(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder)