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LLVM
3.7.0
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This is the complete list of members for llvm::SIInstrInfo, including all inherited members.
| AMDGPUInstrInfo(const AMDGPUSubtarget &st) | llvm::AMDGPUInstrInfo | explicit |
| areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override | llvm::SIInstrInfo | |
| areMemAccessesTriviallyDisjoint(MachineInstr *MIa, MachineInstr *MIb, AliasAnalysis *AA=nullptr) const override | llvm::SIInstrInfo | |
| buildIndirectRead(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned ValueReg, unsigned Address, unsigned OffsetReg) const override | llvm::SIInstrInfo | virtual |
| buildIndirectWrite(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned ValueReg, unsigned Address, unsigned OffsetReg) const override | llvm::SIInstrInfo | virtual |
| buildMovInstr(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned DstReg, unsigned SrcReg) const override | llvm::SIInstrInfo | virtual |
| calculateIndirectAddress(unsigned RegIndex, unsigned Channel) const override | llvm::SIInstrInfo | virtual |
| calculateLDSSpillAddress(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, RegScavenger *RS, unsigned TmpReg, unsigned Offset, unsigned Size) const | llvm::SIInstrInfo | |
| canFoldMemoryOperand(const MachineInstr *MI, ArrayRef< unsigned > Ops) const override | llvm::AMDGPUInstrInfo | |
| canReadVGPR(const MachineInstr &MI, unsigned OpNo) const | llvm::SIInstrInfo | |
| commuteInstruction(MachineInstr *MI, bool NewMI=false) const override | llvm::SIInstrInfo | |
| commuteOpcode(const MachineInstr &MI) const | llvm::SIInstrInfo | |
| convertToThreeAddress(MachineFunction::iterator &MBB, MachineBasicBlock::iterator &MI, LiveVariables *LV) const override | llvm::SIInstrInfo | |
| copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override | llvm::SIInstrInfo | |
| DefinesPredicate(MachineInstr *MI, std::vector< MachineOperand > &Pred) const override | llvm::AMDGPUInstrInfo | |
| enableClusterLoads() const override | llvm::AMDGPUInstrInfo | |
| expandPostRAPseudo(MachineBasicBlock::iterator MI) const override | llvm::SIInstrInfo | |
| findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override | llvm::SIInstrInfo | |
| FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, unsigned Reg, MachineRegisterInfo *MRI) const final | llvm::SIInstrInfo | |
| foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex) const override | llvm::AMDGPUInstrInfo | protected |
| foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr *LoadMI) const override | llvm::AMDGPUInstrInfo | protected |
| getDefaultRsrcDataFormat() const | llvm::SIInstrInfo | |
| getIndirectAddrRegClass() const override | llvm::SIInstrInfo | virtual |
| getIndirectIndexBegin(const MachineFunction &MF) const | llvm::AMDGPUInstrInfo | |
| getIndirectIndexEnd(const MachineFunction &MF) const | llvm::AMDGPUInstrInfo | |
| getMachineCSELookAheadLimit() const override | llvm::SIInstrInfo | inline |
| getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const | llvm::AMDGPUInstrInfo | |
| getMCOpcodeFromPseudo(unsigned Opcode) const | llvm::AMDGPUInstrInfo | inline |
| getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg, unsigned &Offset, const TargetRegisterInfo *TRI) const final | llvm::SIInstrInfo | |
| getMovOpcode(const TargetRegisterClass *DstRC) const | llvm::SIInstrInfo | |
| getNamedOperand(MachineInstr &MI, unsigned OperandName) const | llvm::SIInstrInfo | |
| getNamedOperand(const MachineInstr &MI, unsigned OpName) const | llvm::SIInstrInfo | inline |
| getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const override | llvm::AMDGPUInstrInfo | |
| getOpRegClass(const MachineInstr &MI, unsigned OpNo) const | llvm::SIInstrInfo | |
| getOpSize(uint16_t Opcode, unsigned OpNo) const | llvm::SIInstrInfo | inline |
| getOpSize(const MachineInstr &MI, unsigned OpNo) const | llvm::SIInstrInfo | inline |
| getRegisterInfo() const override | llvm::SIInstrInfo | inlinevirtual |
| getVALUOp(const MachineInstr &MI) | llvm::SIInstrInfo | static |
| hasLoadFromStackSlot(const MachineInstr *MI, const MachineMemOperand *&MMO, int &FrameIndex) const override | llvm::AMDGPUInstrInfo | |
| hasModifiers(unsigned Opcode) const | llvm::SIInstrInfo | |
| hasModifiersSet(const MachineInstr &MI, unsigned OpName) const | llvm::SIInstrInfo | |
| hasStoreFromStackSlot(const MachineInstr *MI, const MachineMemOperand *&MMO, int &FrameIndex) const | llvm::AMDGPUInstrInfo | |
| hasVALU32BitEncoding(unsigned Opcode) const | llvm::SIInstrInfo | |
| insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override | llvm::AMDGPUInstrInfo | |
| insertNOPs(MachineBasicBlock::iterator MI, int Count) const | llvm::SIInstrInfo | |
| isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override | llvm::AMDGPUInstrInfo | |
| isDS(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| isFLAT(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| isImmOperandLegal(const MachineInstr *MI, unsigned OpNo, const MachineOperand &MO) const | llvm::SIInstrInfo | |
| isInlineConstant(const APInt &Imm) const | llvm::SIInstrInfo | |
| isInlineConstant(const MachineOperand &MO, unsigned OpSize) const | llvm::SIInstrInfo | |
| isLiteralConstant(const MachineOperand &MO, unsigned OpSize) const | llvm::SIInstrInfo | |
| isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const override | llvm::AMDGPUInstrInfo | |
| isLoadFromStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const override | llvm::AMDGPUInstrInfo | |
| isMIMG(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| isMov(unsigned Opcode) const override | llvm::SIInstrInfo | virtual |
| isMTBUF(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| isMUBUF(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| isOperandLegal(const MachineInstr *MI, unsigned OpIdx, const MachineOperand *MO=nullptr) const | llvm::SIInstrInfo | |
| isPredicable(MachineInstr *MI) const override | llvm::AMDGPUInstrInfo | |
| isPredicated(const MachineInstr *MI) const override | llvm::AMDGPUInstrInfo | |
| isReallyTriviallyReMaterializable(const MachineInstr *MI, AliasAnalysis *AA) const override | llvm::SIInstrInfo | |
| isRegisterLoad(const MachineInstr &MI) const | llvm::AMDGPUInstrInfo | |
| isRegisterStore(const MachineInstr &MI) const | llvm::AMDGPUInstrInfo | |
| isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override | llvm::SIInstrInfo | |
| isSALU(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| isSALUOpSupportedOnVALU(const MachineInstr &MI) const | llvm::SIInstrInfo | |
| isSMRD(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| isSOP1(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| isSOP2(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| isSOPC(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| isSOPK(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| isSOPP(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| isStoreFromStackSlot(const MachineInstr *MI, int &FrameIndex) const | llvm::AMDGPUInstrInfo | |
| isStoreFromStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const | llvm::AMDGPUInstrInfo | |
| isTriviallyReMaterializable(const MachineInstr *MI, AliasAnalysis *AA=nullptr) const | llvm::SIInstrInfo | |
| isVALU(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| isVGPRSpill(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| isVOP1(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| isVOP2(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| isVOP3(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| isVOPC(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| isWQM(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| legalizeOperands(MachineInstr *MI) const | llvm::SIInstrInfo | |
| legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const | llvm::SIInstrInfo | |
| LoadM0(MachineInstr *MoveRel, MachineBasicBlock::iterator I, unsigned SavReg, unsigned IndexReg) const | llvm::SIInstrInfo | |
| loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override | llvm::SIInstrInfo | |
| moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const | llvm::SIInstrInfo | |
| moveToVALU(MachineInstr &MI) const | llvm::SIInstrInfo | |
| pseudoToMCOpcode(int Opcode) const | llvm::AMDGPUInstrInfo | |
| reserveIndirectRegisters(BitVector &Reserved, const MachineFunction &MF) const | llvm::SIInstrInfo | |
| ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override | llvm::AMDGPUInstrInfo | |
| shouldClusterLoads(MachineInstr *FirstLdSt, MachineInstr *SecondLdSt, unsigned NumLoads) const final | llvm::SIInstrInfo | |
| shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override | llvm::AMDGPUInstrInfo | |
| SIInstrInfo(const AMDGPUSubtarget &st) | llvm::SIInstrInfo | explicit |
| splitSMRD(MachineInstr *MI, const TargetRegisterClass *HalfRC, unsigned HalfImmOp, unsigned HalfSGPROp, MachineInstr *&Lo, MachineInstr *&Hi) const | llvm::SIInstrInfo | |
| ST | llvm::AMDGPUInstrInfo | protected |
| storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override | llvm::SIInstrInfo | |
| SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override | llvm::AMDGPUInstrInfo | |
| unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const override | llvm::AMDGPUInstrInfo | |
| unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, SmallVectorImpl< SDNode * > &NewNodes) const override | llvm::AMDGPUInstrInfo | |
| usesConstantBus(const MachineRegisterInfo &MRI, const MachineOperand &MO, unsigned OpSize) const | llvm::SIInstrInfo | |
| verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const override | llvm::SIInstrInfo |
1.8.6