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LLVM
3.7.0
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#include <X86Subtarget.h>
Protected Types | |
| enum | X86SSEEnum { NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F } |
| enum | X863DNowEnum { NoThreeDNow, ThreeDNow, ThreeDNowA } |
| enum | X86ProcFamilyEnum { Others, IntelAtom, IntelSLM } |
Protected Attributes | |
| X86ProcFamilyEnum | X86ProcFamily |
| X86 processor family: Intel Atom, and others. More... | |
| PICStyles::Style | PICStyle |
| Which PIC style to use. More... | |
| X86SSEEnum | X86SSELevel |
| MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported. More... | |
| X863DNowEnum | X863DNowLevel |
| 3DNow, 3DNow Athlon, or none supported. More... | |
| bool | HasCMov |
| True if this processor has conditional move instructions (generally pentium pro+). More... | |
| bool | HasX86_64 |
| True if the processor supports X86-64 instructions. More... | |
| bool | HasPOPCNT |
| True if the processor supports POPCNT. More... | |
| bool | HasSSE4A |
| True if the processor supports SSE4A instructions. More... | |
| bool | HasAES |
| Target has AES instructions. More... | |
| bool | HasPCLMUL |
| Target has carry-less multiplication. More... | |
| bool | HasFMA |
| Target has 3-operand fused multiply-add. More... | |
| bool | HasFMA4 |
| Target has 4-operand fused multiply-add. More... | |
| bool | HasXOP |
| Target has XOP instructions. More... | |
| bool | HasTBM |
| Target has TBM instructions. More... | |
| bool | HasMOVBE |
| True if the processor has the MOVBE instruction. More... | |
| bool | HasRDRAND |
| True if the processor has the RDRAND instruction. More... | |
| bool | HasF16C |
| Processor has 16-bit floating point conversion instructions. More... | |
| bool | HasFSGSBase |
| Processor has FS/GS base insturctions. More... | |
| bool | HasLZCNT |
| Processor has LZCNT instruction. More... | |
| bool | HasBMI |
| Processor has BMI1 instructions. More... | |
| bool | HasBMI2 |
| Processor has BMI2 instructions. More... | |
| bool | HasRTM |
| Processor has RTM instructions. More... | |
| bool | HasHLE |
| Processor has HLE. More... | |
| bool | HasADX |
| Processor has ADX instructions. More... | |
| bool | HasSHA |
| Processor has SHA instructions. More... | |
| bool | HasPRFCHW |
| Processor has PRFCHW instructions. More... | |
| bool | HasRDSEED |
| Processor has RDSEED instructions. More... | |
| bool | IsBTMemSlow |
| True if BT (bit test) of memory instructions are slow. More... | |
| bool | IsSHLDSlow |
| True if SHLD instructions are slow. More... | |
| bool | IsUAMemFast |
| True if unaligned memory access is fast. More... | |
| bool | IsUAMem32Slow |
| True if unaligned 32-byte memory accesses are slow. More... | |
| bool | HasSSEUnalignedMem |
| True if SSE operations can have unaligned memory operands. More... | |
| bool | HasCmpxchg16b |
| True if this processor has the CMPXCHG16B instruction; this is true for most x86-64 chips, but not the first AMD chips. More... | |
| bool | UseLeaForSP |
| True if the LEA instruction should be used for adjusting the stack pointer. More... | |
| bool | HasSlowDivide32 |
| True if 8-bit divisions are significantly faster than 32-bit divisions and should be used when possible. More... | |
| bool | HasSlowDivide64 |
| True if 16-bit divides are significantly faster than 64-bit divisions and should be used when possible. More... | |
| bool | PadShortFunctions |
| True if the short functions should be padded to prevent a stall when returning too early. More... | |
| bool | CallRegIndirect |
| True if the Calls with memory reference should be converted to a register-based indirect call. More... | |
| bool | LEAUsesAG |
| True if the LEA instruction inputs have to be ready at address generation (AG) time. More... | |
| bool | SlowLEA |
| True if the LEA instruction with certain arguments is slow. More... | |
| bool | SlowIncDec |
| True if INC and DEC instructions are slow when writing to flags. More... | |
| bool | HasPFI |
| Processor has AVX-512 PreFetch Instructions. More... | |
| bool | HasERI |
| Processor has AVX-512 Exponential and Reciprocal Instructions. More... | |
| bool | HasCDI |
| Processor has AVX-512 Conflict Detection Instructions. More... | |
| bool | HasDQI |
| Processor has AVX-512 Doubleword and Quadword instructions. More... | |
| bool | HasBWI |
| Processor has AVX-512 Byte and Word instructions. More... | |
| bool | HasVLX |
| Processor has AVX-512 Vector Length eXtenstions. More... | |
| bool | HasMPX |
| Processot supports MPX - Memory Protection Extensions. More... | |
| bool | UseSoftFloat |
| Use software floating point for code generation. More... | |
| unsigned | stackAlignment |
| The minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function. More... | |
| unsigned | MaxInlineSizeThreshold |
| Max. More... | |
| Triple | TargetTriple |
| What processor and OS we're targeting. More... | |
| InstrItineraryData | InstrItins |
| Instruction itineraries for scheduling. More... | |
Definition at line 46 of file X86Subtarget.h.
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| Enumerator | |
|---|---|
| NoThreeDNow | |
| ThreeDNow | |
| ThreeDNowA | |
Definition at line 53 of file X86Subtarget.h.
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| Enumerator | |
|---|---|
| Others | |
| IntelAtom | |
| IntelSLM | |
Definition at line 57 of file X86Subtarget.h.
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| Enumerator | |
|---|---|
| NoMMXSSE | |
| MMX | |
| SSE1 | |
| SSE2 | |
| SSE3 | |
| SSSE3 | |
| SSE41 | |
| SSE42 | |
| AVX | |
| AVX2 | |
| AVX512F | |
Definition at line 49 of file X86Subtarget.h.
| X86Subtarget::X86Subtarget | ( | const Triple & | TT, |
| const std::string & | CPU, | ||
| const std::string & | FS, | ||
| const X86TargetMachine & | TM, | ||
| unsigned | StackAlignOverride | ||
| ) |
This constructor initializes the data members to match that of the specified triple.
Definition at line 286 of file X86Subtarget.cpp.
References llvm::Reloc::DynamicNoPIC, llvm::TargetMachine::getRelocationModel(), llvm::PICStyles::GOT, is64Bit(), isTargetCOFF(), isTargetDarwin(), isTargetELF(), llvm::PICStyles::None, llvm::Reloc::PIC_, llvm::PICStyles::RIPRel, setPICStyle(), llvm::Reloc::Static, llvm::PICStyles::StubDynamicNoPIC, llvm::PICStyles::StubPIC, and llvm::x86.
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Definition at line 368 of file X86Subtarget.h.
References CallRegIndirect.
Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl().
| unsigned char X86Subtarget::ClassifyBlockAddressReference | ( | ) | const |
Classify a blockaddress reference for the current subtarget according to how we should reference it in a non-pcrel context.
ClassifyBlockAddressReference - Classify a blockaddress reference for the current subtarget according to how we should reference it in a non-pcrel context.
Definition at line 50 of file X86Subtarget.cpp.
References isPICStyleGOT(), isPICStyleStubPIC(), llvm::X86II::MO_GOTOFF, llvm::X86II::MO_NO_FLAG, and llvm::X86II::MO_PIC_BASE_OFFSET.
| unsigned char X86Subtarget::ClassifyGlobalReference | ( | const GlobalValue * | GV, |
| const TargetMachine & | TM | ||
| ) | const |
ClassifyGlobalReference - Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context.
Definition at line 65 of file X86Subtarget.cpp.
References llvm::TargetMachine::getCodeModel(), llvm::GlobalValue::hasCommonLinkage(), llvm::GlobalValue::hasDefaultVisibility(), llvm::GlobalValue::hasDLLImportStorageClass(), llvm::GlobalValue::hasHiddenVisibility(), llvm::GlobalValue::hasLocalLinkage(), llvm::GlobalValue::isDeclarationForLinker(), isPICStyleGOT(), isPICStyleRIPRel(), isPICStyleStubNoDynamic(), isPICStyleStubPIC(), llvm::GlobalValue::isStrongDefinitionForLinker(), isTargetDarwin(), isTargetELF(), isTargetWin64(), llvm::CodeModel::Large, llvm::X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE, llvm::X86II::MO_DARWIN_NONLAZY, llvm::X86II::MO_DARWIN_NONLAZY_PIC_BASE, llvm::X86II::MO_DLLIMPORT, llvm::X86II::MO_GOT, llvm::X86II::MO_GOTOFF, llvm::X86II::MO_GOTPCREL, llvm::X86II::MO_NO_FLAG, and llvm::X86II::MO_PIC_BASE_OFFSET.
Referenced by llvm::X86TargetLowering::isLegalAddressingMode(), and llvm::X86TargetLowering::LowerAsmOperandForConstraint().
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Definition at line 320 of file X86Subtarget.cpp.
References hasCMov(), and X86EarlyIfConv.
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Enable the MachineScheduler pass for all X86 subtargets.
Definition at line 497 of file X86Subtarget.h.
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Definition at line 506 of file X86Subtarget.h.
References llvm::TargetSubtargetInfo::ANTIDEP_CRITICAL.
| const char * X86Subtarget::getBZeroEntry | ( | ) | const |
This function returns the name of a function which has an interface like the non-standard bzero function, if such a function exists on the current subtarget and it is considered prefereable over memset with zero passed as the second argument.
getBZeroEntry - This function returns the name of a function which has an interface like the non-standard bzero function, if such a function exists on the current subtarget and it is considered prefereable over memset with zero passed as the second argument.
Otherwise it returns null.
Definition at line 154 of file X86Subtarget.cpp.
References getTargetTriple().
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Definition at line 263 of file X86Subtarget.h.
Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl(), llvm::X86TargetLowering::getRegisterByName(), llvm::X86InstrInfo::loadRegFromStackSlot(), LowerSEHRESTOREFRAME(), and llvm::X86InstrInfo::storeRegToStackSlot().
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Definition at line 262 of file X86Subtarget.h.
Referenced by llvm::X86TargetLowering::EmitInstrWithCustomInserter(), EmitMonitor(), and getRegisterInfo().
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Return the instruction itineraries based on the subtarget selection.
Definition at line 502 of file X86Subtarget.h.
References InstrItins.
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Returns the maximum memset / memcpy size that still makes it profitable to inline the call.
Definition at line 280 of file X86Subtarget.h.
References MaxInlineSizeThreshold.
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Definition at line 318 of file X86Subtarget.h.
References PICStyle.
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Definition at line 269 of file X86Subtarget.h.
References getInstrInfo(), and llvm::X86InstrInfo::getRegisterInfo().
Referenced by llvm::X86TargetLowering::getRegisterByName(), llvm::X86TargetLowering::getReturnAddressFrameIndex(), LowerINTRINSIC_W_CHAIN(), LowerINTRINSIC_WO_CHAIN(), LowerSEHRESTOREFRAME(), and llvm::X86TargetLowering::X86TargetLowering().
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Definition at line 266 of file X86Subtarget.h.
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Returns the minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function for this subtarget.
Definition at line 276 of file X86Subtarget.h.
References stackAlignment.
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Definition at line 259 of file X86Subtarget.h.
Referenced by PerformSINT_TO_FPCombine().
Definition at line 384 of file X86Subtarget.h.
References TargetTriple.
Referenced by computeBytesPoppedByCallee(), getBZeroEntry(), and hasSinCos().
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Definition at line 335 of file X86Subtarget.h.
References ThreeDNow, and X863DNowLevel.
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Definition at line 336 of file X86Subtarget.h.
References ThreeDNowA, and X863DNowLevel.
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Definition at line 354 of file X86Subtarget.h.
References HasADX.
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Definition at line 338 of file X86Subtarget.h.
References HasAES.
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Definition at line 329 of file X86Subtarget.h.
References AVX, and X86SSELevel.
Referenced by llvm::X86InstrInfo::breakPartialRegDependency(), llvm::X86InstrInfo::copyPhysReg(), CopyToFromAsymmetricReg(), llvm::X86InstrInfo::expandPostRAPseudo(), llvm::X86TTIImpl::getArithmeticInstrCost(), llvm::X86RegisterInfo::getCalleeSavedRegs(), llvm::X86RegisterInfo::getCallPreservedMask(), llvm::X86TTIImpl::getCastInstrCost(), llvm::X86TTIImpl::getCmpSelInstrCost(), getLoadStoreRegOpcode(), llvm::X86TTIImpl::getMaxInterleaveFactor(), llvm::X86TTIImpl::getReductionCost(), llvm::X86TTIImpl::getRegisterBitWidth(), hasFp256(), LowerINSERT_SUBVECTOR(), LowerToAddSub(), LowerToHorizontalOp(), lowerV2F64VectorShuffle(), lowerV4F32VectorShuffle(), LowerVectorBroadcast(), lowerVectorShuffleAsBroadcast(), LowerVSETCC(), matchIntegerMINMAX(), PerformINTRINSIC_WO_CHAINCombine(), llvm::X86InstrInfo::shouldScheduleAdjacent(), and X86ChooseCmpOpcode().
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Definition at line 330 of file X86Subtarget.h.
References AVX2, and X86SSELevel.
Referenced by llvm::X86TTIImpl::getArithmeticInstrCost(), llvm::X86TTIImpl::getCastInstrCost(), llvm::X86TTIImpl::getCmpSelInstrCost(), llvm::X86InstrInfo::getExecutionDomain(), llvm::X86TTIImpl::getMemoryOpCost(), llvm::X86TTIImpl::getShuffleCost(), hasInt256(), Insert128BitVector(), llvm::X86TTIImpl::isLegalMaskedLoad(), lower256BitVectorShuffle(), LowerToHorizontalOp(), lowerV16I16VectorShuffle(), lowerV32I8VectorShuffle(), lowerV4F64VectorShuffle(), lowerV4I64VectorShuffle(), lowerV8F32VectorShuffle(), lowerV8I32VectorShuffle(), LowerVectorBroadcast(), lowerVectorShuffleAsBlend(), lowerVectorShuffleAsBroadcast(), matchIntegerMINMAX(), PerformINTRINSIC_WO_CHAINCombine(), PerformSELECTCombine(), and llvm::X86InstrInfo::setExecutionDomain().
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Definition at line 331 of file X86Subtarget.h.
References AVX512F, and X86SSELevel.
Referenced by CMPEQCombine(), llvm::X86InstrInfo::copyPhysReg(), CopyToFromAsymmetricReg(), llvm::X86TTIImpl::getArithmeticInstrCost(), llvm::X86RegisterInfo::getCalleeSavedRegs(), llvm::X86RegisterInfo::getCallPreservedMask(), llvm::X86TTIImpl::getCastInstrCost(), llvm::X86TTIImpl::getCmpSelInstrCost(), getLoadStoreRegOpcode(), llvm::X86TTIImpl::getMaskedMemoryOpCost(), llvm::X86TTIImpl::getNumberOfRegisters(), llvm::X86TTIImpl::getRegisterBitWidth(), llvm::X86RegisterInfo::getReservedRegs(), llvm::X86TargetLowering::getSetCCResultType(), llvm::X86TargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::X86TTIImpl::isLegalMaskedLoad(), lower512BitVectorShuffle(), LowerMGATHER(), LowerMSCATTER(), LowerVectorBroadcast(), LowerVSETCC(), matchIntegerMINMAX(), PerformFMACombine(), PerformSELECTCombine(), and llvm::X86TargetLowering::X86TargetLowering().
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Definition at line 350 of file X86Subtarget.h.
References HasBMI.
Referenced by llvm::X86TargetLowering::isCheapToSpeculateCttz(), PerformAndCombine(), and llvm::X86TargetLowering::X86TargetLowering().
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Definition at line 351 of file X86Subtarget.h.
References HasBMI2.
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Definition at line 376 of file X86Subtarget.h.
References HasBWI.
Referenced by llvm::X86TargetLowering::getSetCCResultType(), getZeroVector(), lower512BitVectorShuffle(), LowerSIGN_EXTEND_AVX512(), lowerV32I16VectorShuffle(), lowerV64I8VectorShuffle(), LowerVSETCC(), LowerZERO_EXTEND_AVX512(), matchIntegerMINMAX(), PerformSELECTCombine(), SupportedVectorShiftWithImm(), SupportedVectorVarShift(), and llvm::X86TargetLowering::X86TargetLowering().
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Definition at line 372 of file X86Subtarget.h.
References HasCDI.
Referenced by llvm::X86TargetLowering::X86TargetLowering().
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Definition at line 321 of file X86Subtarget.h.
References HasCMov.
Referenced by llvm::X86InstrInfo::canInsertSelect(), enableEarlyIfConversion(), and PerformXorCombine().
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Definition at line 363 of file X86Subtarget.h.
References HasCmpxchg16b.
Referenced by llvm::X86TargetLowering::X86TargetLowering().
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Definition at line 375 of file X86Subtarget.h.
References HasDQI.
Referenced by LowerSIGN_EXTEND_AVX512(), and llvm::X86TargetLowering::X86TargetLowering().
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Definition at line 374 of file X86Subtarget.h.
References HasERI.
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Definition at line 347 of file X86Subtarget.h.
References HasF16C.
Referenced by llvm::X86TargetLowering::X86TargetLowering().
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Definition at line 340 of file X86Subtarget.h.
References HasFMA.
Referenced by llvm::X86TargetLowering::isFMAFasterThanFMulAndFAdd(), PerformFMACombine(), and llvm::X86TargetLowering::X86TargetLowering().
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Definition at line 342 of file X86Subtarget.h.
References HasFMA, and HasFMA4.
Referenced by llvm::X86TargetLowering::isFMAFasterThanFMulAndFAdd(), PerformFMACombine(), and llvm::X86TargetLowering::X86TargetLowering().
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Definition at line 332 of file X86Subtarget.h.
References hasAVX().
Referenced by llvm::X86TargetLowering::getOptimalMemOpType(), llvm::X86TargetLowering::getSingleConstraintMatchWeight(), LowerANY_EXTEND(), LowerEXTRACT_SUBVECTOR(), LowerZERO_EXTEND(), PerformFADDCombine(), PerformFSUBCombine(), PerformSExtCombine(), PerformShuffleCombine(), and llvm::X86TargetLowering::X86TargetLowering().
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Definition at line 348 of file X86Subtarget.h.
References HasFSGSBase.
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Definition at line 353 of file X86Subtarget.h.
References HasHLE.
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Definition at line 333 of file X86Subtarget.h.
References hasAVX2().
Referenced by llvm::X86TargetLowering::getOptimalMemOpType(), getZeroVector(), llvm::X86TargetLowering::isVectorShiftByScalarCheap(), LowerAVXExtend(), LowerExtendedLoad(), LowerMUL(), LowerMUL_LOHI(), LowerScalarImmediateShift(), LowerShift(), LowerSIGN_EXTEND(), LowerVectorBroadcast(), LowerVectorCTPOP(), LowerVSETCC(), PerformAddCombine(), PerformOrCombine(), PerformSExtCombine(), performShiftToAllZeros(), PerformSIGN_EXTEND_INREGCombine(), PerformSubCombine(), SupportedVectorShiftWithImm(), SupportedVectorVarShift(), and llvm::X86TargetLowering::X86TargetLowering().
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Definition at line 349 of file X86Subtarget.h.
References HasLZCNT.
Referenced by llvm::X86TargetLowering::isCheapToSpeculateCtlz(), and llvm::X86TargetLowering::X86TargetLowering().
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Definition at line 322 of file X86Subtarget.h.
References MMX, and X86SSELevel.
Referenced by llvm::X86TargetLowering::getRegForInlineAsmConstraint(), llvm::X86TargetLowering::getSingleConstraintMatchWeight(), LowerBITCAST(), and llvm::X86TargetLowering::X86TargetLowering().
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Definition at line 345 of file X86Subtarget.h.
References HasMOVBE.
Referenced by llvm::X86TargetLowering::X86TargetLowering().
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Definition at line 378 of file X86Subtarget.h.
References HasMPX.
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Definition at line 339 of file X86Subtarget.h.
References HasPCLMUL.
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Definition at line 373 of file X86Subtarget.h.
References HasPFI.
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Definition at line 337 of file X86Subtarget.h.
References HasPOPCNT.
Referenced by llvm::X86TTIImpl::getPopcntSupport(), and llvm::X86TargetLowering::X86TargetLowering().
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Definition at line 356 of file X86Subtarget.h.
References HasPRFCHW.
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Definition at line 346 of file X86Subtarget.h.
References HasRDRAND.
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Definition at line 357 of file X86Subtarget.h.
References HasRDSEED.
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Definition at line 352 of file X86Subtarget.h.
References HasRTM.
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Definition at line 355 of file X86Subtarget.h.
References HasSHA.
| bool X86Subtarget::hasSinCos | ( | ) | const |
This function returns true if the target has sincos() routine in its compiler runtime or math libraries.
Definition at line 163 of file X86Subtarget.cpp.
References getTargetTriple(), is64Bit(), llvm::Triple::isMacOSX(), and llvm::Triple::isMacOSXVersionLT().
Referenced by llvm::X86TargetLowering::X86TargetLowering().
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Definition at line 365 of file X86Subtarget.h.
References HasSlowDivide32.
Referenced by llvm::X86TargetLowering::X86TargetLowering().
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Definition at line 366 of file X86Subtarget.h.
References HasSlowDivide64.
Referenced by llvm::X86TargetLowering::X86TargetLowering().
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Definition at line 323 of file X86Subtarget.h.
References SSE1, and X86SSELevel.
Referenced by get64BitArgumentXMMs(), llvm::X86TargetLowering::getByValTypeAlignment(), llvm::X86TTIImpl::getNumberOfRegisters(), llvm::X86TargetLowering::getOptimalMemOpType(), llvm::X86TargetLowering::getRegForInlineAsmConstraint(), llvm::X86TTIImpl::getRegisterBitWidth(), llvm::X86TargetLowering::getSingleConstraintMatchWeight(), llvm::X86TargetLowering::LowerXConstraint(), PerformSELECTCombine(), X86ChooseCmpOpcode(), and llvm::X86TargetLowering::X86TargetLowering().
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Definition at line 324 of file X86Subtarget.h.
References SSE2, and X86SSELevel.
Referenced by CMPEQCombine(), llvm::X86TTIImpl::getArithmeticInstrCost(), llvm::X86TTIImpl::getCastInstrCost(), llvm::X86TargetLowering::getOptimalMemOpType(), llvm::X86TargetLowering::getRegForInlineAsmConstraint(), getZeroVector(), hasMFENCE(), LowerBITCAST(), LowerExtendedLoad(), LowerMUL(), LowerMUL_LOHI(), LowerShift(), LowerVSETCC(), llvm::X86TargetLowering::LowerXConstraint(), matchIntegerMINMAX(), PerformSELECTCombine(), PerformSExtCombine(), PerformSTORECombine(), llvm::X86TargetLowering::ReplaceNodeResults(), X86ChooseCmpOpcode(), and llvm::X86TargetLowering::X86TargetLowering().
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Definition at line 325 of file X86Subtarget.h.
References SSE3, and X86SSELevel.
Referenced by llvm::X86TargetLowering::BuildFILD(), LowerToAddSub(), LowerToHorizontalOp(), lowerV2F64VectorShuffle(), lowerV4F32VectorShuffle(), PerformFADDCombine(), PerformFSUBCombine(), PerformShuffleCombine(), and llvm::X86TargetLowering::X86TargetLowering().
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Definition at line 327 of file X86Subtarget.h.
References SSE41, and X86SSELevel.
Referenced by llvm::X86TTIImpl::getArithmeticInstrCost(), getTargetVShiftNode(), LowerBuildVectorv16i8(), LowerBuildVectorv4x32(), LowerExtendedLoad(), LowerMUL(), LowerMUL_LOHI(), LowerShift(), LowerSIGN_EXTEND_VECTOR_INREG(), lowerUINT_TO_FP_vXi32(), lowerV16I8VectorShuffle(), lowerV2F64VectorShuffle(), lowerV2I64VectorShuffle(), lowerV4F32VectorShuffle(), lowerV4I32VectorShuffle(), lowerV8I16VectorShuffle(), LowerVectorAllZeroTest(), lowerVectorShuffleAsElementInsertion(), lowerVectorShuffleAsSpecificZeroOrAnyExtend(), LowerVSETCC(), matchIntegerMINMAX(), PerformINTRINSIC_WO_CHAINCombine(), PerformOrCombine(), PerformSELECTCombine(), and llvm::X86TargetLowering::X86TargetLowering().
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Definition at line 328 of file X86Subtarget.h.
References SSE42, and X86SSELevel.
Referenced by llvm::X86TargetLowering::EmitInstrWithCustomInserter(), llvm::X86TTIImpl::getCmpSelInstrCost(), llvm::X86TTIImpl::getReductionCost(), and LowerVSETCC().
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Definition at line 334 of file X86Subtarget.h.
References HasSSE4A.
Referenced by lowerV16I8VectorShuffle(), lowerV8I16VectorShuffle(), and lowerVectorShuffleAsSpecificZeroOrAnyExtend().
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Definition at line 362 of file X86Subtarget.h.
References HasSSEUnalignedMem.
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Definition at line 326 of file X86Subtarget.h.
References SSSE3, and X86SSELevel.
Referenced by LowerToHorizontalOp(), lowerV16I8VectorShuffle(), lowerV2I64VectorShuffle(), lowerV4I32VectorShuffle(), lowerV8I16VectorShuffle(), LowerVectorCTPOP(), lowerVectorShuffleAsByteRotate(), lowerVectorShuffleAsSpecificZeroOrAnyExtend(), PerformAddCombine(), PerformOrCombine(), and PerformSubCombine().
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Definition at line 344 of file X86Subtarget.h.
References HasTBM.
Referenced by PerformAndCombine().
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Definition at line 377 of file X86Subtarget.h.
References HasVLX.
Referenced by llvm::X86TargetLowering::getSetCCResultType(), getZeroVector(), LowerMGATHER(), LowerMSCATTER(), LowerSIGN_EXTEND_AVX512(), LowerVectorBroadcast(), LowerVSETCC(), matchIntegerMINMAX(), PerformSELECTCombine(), SupportedVectorShiftWithImm(), SupportedVectorVarShift(), and llvm::X86TargetLowering::X86TargetLowering().
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Definition at line 343 of file X86Subtarget.h.
References HasXOP.
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Definition at line 302 of file X86Subtarget.h.
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Definition at line 298 of file X86Subtarget.h.
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Is this x86_64? (disregarding specific ABI / programming model)
Definition at line 294 of file X86Subtarget.h.
Referenced by CMPEQCombine(), computeBytesPoppedByCallee(), llvm::X86InstrInfo::convertToThreeAddress(), llvm::X86InstrInfo::copyPhysReg(), EmitMonitor(), llvm::X86TargetLowering::findRepresentativeClass(), llvm::X86InstrInfo::foldMemoryOperandImpl(), get64BitArgumentGPRs(), get64BitArgumentXMMs(), llvm::X86TargetLowering::getByValTypeAlignment(), llvm::X86InstrInfo::getGlobalBaseReg(), getLoadStoreRegOpcode(), llvm::X86TTIImpl::getNumberOfRegisters(), llvm::X86TargetLowering::getOptimalMemOpType(), llvm::X86TargetLowering::getPICJumpTableRelocBase(), getReadPerformanceCounter(), getReadTimeStampCounter(), llvm::X86TargetLowering::getRegForInlineAsmConstraint(), llvm::X86TTIImpl::getRegisterBitWidth(), getRetOpcode(), llvm::X86TargetLowering::getStackCookieLocation(), hasMFENCE(), hasSinCos(), llvm::X86InstrInfo::isCoalescableExtInstr(), llvm::X86TargetLowering::isLegalAddressingMode(), llvm::X86TargetLowering::isTargetFTOL(), isTargetNaCl32(), isTargetNaCl64(), llvm::X86TargetLowering::isZExtFree(), llvm::X86TargetLowering::LowerAsmOperandForConstraint(), LowerBITCAST(), LowerCMP_SWAP(), LowerFSINCOS(), LowerScalarImmediateShift(), LowerScalarVariableShift(), LowerVACOPY(), PerformSINT_TO_FPCombine(), PerformSTORECombine(), printAsmMRegister(), llvm::X86FrameLowering::restoreCalleeSavedRegisters(), llvm::X86InstrInfo::shouldScheduleLoadsNear(), SimplifyShortMoveForm(), llvm::X86FrameLowering::spillCalleeSavedRegisters(), llvm::X86TargetLowering::useLoadStackGuardNode(), llvm::X86FrameLowering::X86FrameLowering(), X86Subtarget(), and llvm::X86TargetLowering::X86TargetLowering().
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Definition at line 380 of file X86Subtarget.h.
References IntelAtom, and X86ProcFamily.
Referenced by llvm::X86TTIImpl::getMaxInterleaveFactor(), and llvm::X86TargetLowering::X86TargetLowering().
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Definition at line 358 of file X86Subtarget.h.
References IsBTMemSlow.
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Definition at line 449 of file X86Subtarget.h.
References llvm::CallingConv::C, llvm::CallingConv::Fast, llvm::CallingConv::Intel_OCL_BI, isTargetWin64(), llvm::CallingConv::X86_64_SysV, llvm::CallingConv::X86_64_Win64, llvm::CallingConv::X86_FastCall, llvm::CallingConv::X86_StdCall, llvm::CallingConv::X86_ThisCall, and llvm::CallingConv::X86_VectorCall.
Referenced by llvm::X86FrameLowering::emitPrologue(), get64BitArgumentGPRs(), and get64BitArgumentXMMs().
| bool X86Subtarget::IsLegalToCallImmediateAddr | ( | const TargetMachine & | TM | ) | const |
Return true if the subtarget allows calls to immediate address.
IsLegalToCallImmediateAddr - Return true if the subtarget allows calls to immediate address.
Definition at line 171 of file X86Subtarget.cpp.
References llvm::TargetMachine::getRelocationModel(), isTargetELF(), isTargetWin32(), and llvm::Reloc::Static.
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Definition at line 423 of file X86Subtarget.h.
References llvm::Triple::isOSWindows(), and TargetTriple.
Referenced by llvm::X86FrameLowering::emitPrologue().
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Definition at line 434 of file X86Subtarget.h.
References llvm::PICStyles::GOT, and PICStyle.
Referenced by ClassifyBlockAddressReference(), ClassifyGlobalReference(), llvm::X86TargetLowering::getJumpTableEncoding(), llvm::X86TargetLowering::LowerAsmOperandForConstraint(), and llvm::X86TargetLowering::LowerCustomJumpTableEntry().
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Definition at line 435 of file X86Subtarget.h.
References PICStyle, and llvm::PICStyles::RIPRel.
Referenced by ClassifyGlobalReference(), llvm::X86TargetLowering::getPICJumpTableRelocBaseExpr(), and llvm::X86AsmPrinter::PrintAsmOperand().
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Definition at line 433 of file X86Subtarget.h.
References llvm::PICStyles::None, and PICStyle.
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Definition at line 444 of file X86Subtarget.h.
References PICStyle, llvm::PICStyles::StubDynamicNoPIC, and llvm::PICStyles::StubPIC.
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Definition at line 441 of file X86Subtarget.h.
References PICStyle, and llvm::PICStyles::StubDynamicNoPIC.
Referenced by ClassifyGlobalReference().
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Definition at line 437 of file X86Subtarget.h.
References PICStyle, and llvm::PICStyles::StubPIC.
Referenced by ClassifyBlockAddressReference(), ClassifyGlobalReference(), and llvm::X86TargetLowering::LowerAsmOperandForConstraint().
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Definition at line 359 of file X86Subtarget.h.
References IsSHLDSlow.
Referenced by PerformOrCombine().
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Definition at line 381 of file X86Subtarget.h.
References IntelSLM, and X86ProcFamily.
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Is this x86_64 with the ILP32 programming model (x32 ABI)?
Definition at line 307 of file X86Subtarget.h.
References llvm::Triple::getEnvironment(), llvm::Triple::GNUX32, llvm::Triple::isOSNaCl(), and TargetTriple.
Referenced by llvm::X86FrameLowering::emitEpilogue(), llvm::X86FrameLowering::emitPrologue(), and llvm::X86RegisterInfo::getPtrSizedFrameRegister().
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Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
Definition at line 313 of file X86Subtarget.h.
References llvm::Triple::getEnvironment(), llvm::Triple::GNUX32, llvm::Triple::isOSNaCl(), and TargetTriple.
Referenced by llvm::X86RegisterInfo::getPointerRegClass(), and llvm::X86FrameLowering::X86FrameLowering().
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Definition at line 393 of file X86Subtarget.h.
References llvm::Triple::isOSBinFormatCOFF(), and TargetTriple.
Referenced by llvm::X86AsmPrinter::runOnMachineFunction(), and X86Subtarget().
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Definition at line 421 of file X86Subtarget.h.
References llvm::Triple::isOSCygMing(), and TargetTriple.
Referenced by llvm::X86FrameLowering::emitStackProbeCall(), isTargetWin32(), and llvm::X86TargetLowering::X86TargetLowering().
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Definition at line 386 of file X86Subtarget.h.
References llvm::Triple::isOSDarwin(), and TargetTriple.
Referenced by llvm::X86FrameLowering::adjustForSegmentedStacks(), ClassifyGlobalReference(), LowerFSINCOS(), X86Subtarget(), and llvm::X86TargetLowering::X86TargetLowering().
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Definition at line 388 of file X86Subtarget.h.
References llvm::Triple::isOSDragonFly(), and TargetTriple.
Referenced by llvm::X86FrameLowering::adjustForSegmentedStacks().
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Definition at line 392 of file X86Subtarget.h.
References llvm::Triple::isOSBinFormatELF(), and TargetTriple.
Referenced by ClassifyGlobalReference(), IsLegalToCallImmediateAddr(), X86Subtarget(), and llvm::X86TargetLowering::X86TargetLowering().
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Definition at line 387 of file X86Subtarget.h.
References llvm::Triple::isOSFreeBSD(), and TargetTriple.
Referenced by llvm::X86FrameLowering::adjustForSegmentedStacks().
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Definition at line 405 of file X86Subtarget.h.
References llvm::Triple::isKnownWindowsMSVCEnvironment(), and TargetTriple.
Referenced by llvm::X86AsmPrinter::GetCPISymbol(), llvm::X86TargetLowering::isTargetFTOL(), isTargetWin32(), and llvm::X86TargetLowering::X86TargetLowering().
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Definition at line 396 of file X86Subtarget.h.
References llvm::Triple::isOSLinux(), and TargetTriple.
Referenced by llvm::X86FrameLowering::adjustForHiPEPrologue(), llvm::X86FrameLowering::adjustForSegmentedStacks(), and llvm::X86TargetLowering::getStackCookieLocation().
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Definition at line 394 of file X86Subtarget.h.
References llvm::Triple::isOSBinFormatMachO(), and TargetTriple.
Referenced by llvm::X86FrameLowering::emitPrologue(), and llvm::X86TargetLowering::useLoadStackGuardNode().
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Definition at line 397 of file X86Subtarget.h.
References llvm::Triple::isOSNaCl(), and TargetTriple.
Referenced by isTargetNaCl32(), and isTargetNaCl64().
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Definition at line 398 of file X86Subtarget.h.
References is64Bit(), and isTargetNaCl().
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Definition at line 399 of file X86Subtarget.h.
References is64Bit(), and isTargetNaCl().
Referenced by llvm::X86FrameLowering::X86FrameLowering().
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Definition at line 390 of file X86Subtarget.h.
References llvm::Triple::isPS4(), and TargetTriple.
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Definition at line 389 of file X86Subtarget.h.
References llvm::Triple::isOSSolaris(), and TargetTriple.
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Definition at line 429 of file X86Subtarget.h.
References isTargetCygMing(), and isTargetKnownWindowsMSVC().
Referenced by llvm::X86FrameLowering::adjustForSegmentedStacks(), and IsLegalToCallImmediateAddr().
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Definition at line 425 of file X86Subtarget.h.
References llvm::Triple::isOSWindows(), and TargetTriple.
Referenced by llvm::X86FrameLowering::adjustForSegmentedStacks(), ClassifyGlobalReference(), isCallingConvWin64(), llvm::X86TargetLowering::X86TargetLowering(), and llvm::X86TargetMachine::X86TargetMachine().
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Definition at line 409 of file X86Subtarget.h.
References llvm::Triple::isWindowsCygwinEnvironment(), and TargetTriple.
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Definition at line 413 of file X86Subtarget.h.
References llvm::Triple::isWindowsGNUEnvironment(), and TargetTriple.
Referenced by llvm::X86TargetLowering::X86TargetLowering().
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Definition at line 417 of file X86Subtarget.h.
References llvm::Triple::isWindowsItaniumEnvironment(), and TargetTriple.
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Definition at line 401 of file X86Subtarget.h.
References llvm::Triple::isWindowsMSVCEnvironment(), and TargetTriple.
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Definition at line 361 of file X86Subtarget.h.
References IsUAMem32Slow.
Referenced by LowerINSERT_SUBVECTOR(), PerformLOADCombine(), and PerformSTORECombine().
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Definition at line 360 of file X86Subtarget.h.
References IsUAMemFast.
Referenced by llvm::X86TargetLowering::allowsMisalignedMemoryAccesses(), llvm::X86TargetLowering::getOptimalMemOpType(), and llvm::X86InstrInfo::unfoldMemoryOperand().
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Definition at line 369 of file X86Subtarget.h.
References LEAUsesAG.
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Definition at line 367 of file X86Subtarget.h.
References PadShortFunctions.
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
Definition of function is auto generated by tblgen.
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Definition at line 371 of file X86Subtarget.h.
References SlowIncDec.
Referenced by getAtomicLoadArithTargetConstant().
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Definition at line 370 of file X86Subtarget.h.
References SlowLEA.
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Definition at line 364 of file X86Subtarget.h.
References UseLeaForSP.
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Definition at line 382 of file X86Subtarget.h.
References UseSoftFloat.
Referenced by get64BitArgumentXMMs(), PerformSTORECombine(), llvm::X86TargetLowering::useSoftFloat(), and llvm::X86TargetLowering::X86TargetLowering().
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True if the Calls with memory reference should be converted to a register-based indirect call.
Definition at line 181 of file X86Subtarget.h.
Referenced by callRegIndirect().
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Processor has ADX instructions.
Definition at line 132 of file X86Subtarget.h.
Referenced by hasADX().
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Processor has BMI1 instructions.
Definition at line 120 of file X86Subtarget.h.
Referenced by hasBMI().
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Processor has BMI2 instructions.
Definition at line 123 of file X86Subtarget.h.
Referenced by hasBMI2().
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Processor has AVX-512 Byte and Word instructions.
Definition at line 206 of file X86Subtarget.h.
Referenced by hasBWI().
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Processor has AVX-512 Conflict Detection Instructions.
Definition at line 200 of file X86Subtarget.h.
Referenced by hasCDI().
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True if this processor has conditional move instructions (generally pentium pro+).
Definition at line 75 of file X86Subtarget.h.
Referenced by hasCMov().
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True if this processor has the CMPXCHG16B instruction; this is true for most x86-64 chips, but not the first AMD chips.
Definition at line 161 of file X86Subtarget.h.
Referenced by hasCmpxchg16b().
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Processor has AVX-512 Doubleword and Quadword instructions.
Definition at line 203 of file X86Subtarget.h.
Referenced by hasDQI().
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Processor has AVX-512 Exponential and Reciprocal Instructions.
Definition at line 197 of file X86Subtarget.h.
Referenced by hasERI().
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Processor has 16-bit floating point conversion instructions.
Definition at line 111 of file X86Subtarget.h.
Referenced by hasF16C().
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Target has 3-operand fused multiply-add.
Definition at line 93 of file X86Subtarget.h.
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Target has 4-operand fused multiply-add.
Definition at line 96 of file X86Subtarget.h.
Referenced by hasFMA4().
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Processor has FS/GS base insturctions.
Definition at line 114 of file X86Subtarget.h.
Referenced by hasFSGSBase().
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Processor has LZCNT instruction.
Definition at line 117 of file X86Subtarget.h.
Referenced by hasLZCNT().
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True if the processor has the MOVBE instruction.
Definition at line 105 of file X86Subtarget.h.
Referenced by hasMOVBE().
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Processot supports MPX - Memory Protection Extensions.
Definition at line 212 of file X86Subtarget.h.
Referenced by hasMPX().
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Target has carry-less multiplication.
Definition at line 90 of file X86Subtarget.h.
Referenced by hasPCLMUL().
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Processor has AVX-512 PreFetch Instructions.
Definition at line 194 of file X86Subtarget.h.
Referenced by hasPFI().
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True if the processor supports POPCNT.
Definition at line 81 of file X86Subtarget.h.
Referenced by hasPOPCNT().
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Processor has PRFCHW instructions.
Definition at line 138 of file X86Subtarget.h.
Referenced by hasPRFCHW().
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True if the processor has the RDRAND instruction.
Definition at line 108 of file X86Subtarget.h.
Referenced by hasRDRAND().
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Processor has RDSEED instructions.
Definition at line 141 of file X86Subtarget.h.
Referenced by hasRDSEED().
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Processor has RTM instructions.
Definition at line 126 of file X86Subtarget.h.
Referenced by hasRTM().
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Processor has SHA instructions.
Definition at line 135 of file X86Subtarget.h.
Referenced by hasSHA().
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True if 8-bit divisions are significantly faster than 32-bit divisions and should be used when possible.
Definition at line 169 of file X86Subtarget.h.
Referenced by hasSlowDivide32().
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True if 16-bit divides are significantly faster than 64-bit divisions and should be used when possible.
Definition at line 173 of file X86Subtarget.h.
Referenced by hasSlowDivide64().
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True if the processor supports SSE4A instructions.
Definition at line 84 of file X86Subtarget.h.
Referenced by hasSSE4A().
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True if SSE operations can have unaligned memory operands.
This may require setting a configuration bit in the processor.
Definition at line 157 of file X86Subtarget.h.
Referenced by hasSSEUnalignedMem().
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Processor has AVX-512 Vector Length eXtenstions.
Definition at line 209 of file X86Subtarget.h.
Referenced by hasVLX().
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True if the processor supports X86-64 instructions.
Definition at line 78 of file X86Subtarget.h.
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Instruction itineraries for scheduling.
Definition at line 229 of file X86Subtarget.h.
Referenced by getInstrItineraryData().
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True if BT (bit test) of memory instructions are slow.
Definition at line 144 of file X86Subtarget.h.
Referenced by isBTMemSlow().
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True if SHLD instructions are slow.
Definition at line 147 of file X86Subtarget.h.
Referenced by isSHLDSlow().
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True if unaligned 32-byte memory accesses are slow.
Definition at line 153 of file X86Subtarget.h.
Referenced by isUnalignedMem32Slow().
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True if unaligned memory access is fast.
Definition at line 150 of file X86Subtarget.h.
Referenced by isUnalignedMemAccessFast().
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True if the LEA instruction inputs have to be ready at address generation (AG) time.
Definition at line 185 of file X86Subtarget.h.
Referenced by LEAusesAG().
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Max.
memset / memcpy size that is turned into rep/movs, rep/stos ops.
Definition at line 223 of file X86Subtarget.h.
Referenced by getMaxInlineSizeThreshold().
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True if the short functions should be padded to prevent a stall when returning too early.
Definition at line 177 of file X86Subtarget.h.
Referenced by padShortFunctions().
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Which PIC style to use.
Definition at line 65 of file X86Subtarget.h.
Referenced by getPICStyle(), isPICStyleGOT(), isPICStyleRIPRel(), isPICStyleSet(), isPICStyleStubAny(), isPICStyleStubNoDynamic(), isPICStyleStubPIC(), and setPICStyle().
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True if INC and DEC instructions are slow when writing to flags.
Definition at line 191 of file X86Subtarget.h.
Referenced by slowIncDec().
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True if the LEA instruction with certain arguments is slow.
Definition at line 188 of file X86Subtarget.h.
Referenced by slowLEA().
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The minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function.
Definition at line 219 of file X86Subtarget.h.
Referenced by getStackAlignment().
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What processor and OS we're targeting.
Definition at line 226 of file X86Subtarget.h.
Referenced by getTargetTriple(), isOSWindows(), isTarget64BitILP32(), isTarget64BitLP64(), isTargetCOFF(), isTargetCygMing(), isTargetDarwin(), isTargetDragonFly(), isTargetELF(), isTargetFreeBSD(), isTargetKnownWindowsMSVC(), isTargetLinux(), isTargetMachO(), isTargetNaCl(), isTargetPS4(), isTargetSolaris(), isTargetWin64(), isTargetWindowsCygwin(), isTargetWindowsGNU(), isTargetWindowsItanium(), and isTargetWindowsMSVC().
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True if the LEA instruction should be used for adjusting the stack pointer.
This is an optimization for Intel Atom processors.
Definition at line 165 of file X86Subtarget.h.
Referenced by useLeaForSP().
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Use software floating point for code generation.
Definition at line 215 of file X86Subtarget.h.
Referenced by useSoftFloat().
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3DNow, 3DNow Athlon, or none supported.
Definition at line 71 of file X86Subtarget.h.
Referenced by has3DNow(), and has3DNowA().
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X86 processor family: Intel Atom, and others.
Definition at line 62 of file X86Subtarget.h.
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MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
Definition at line 68 of file X86Subtarget.h.
Referenced by hasAVX(), hasAVX2(), hasAVX512(), hasMMX(), hasSSE1(), hasSSE2(), hasSSE3(), hasSSE41(), hasSSE42(), and hasSSSE3().
1.8.6