LLVM  3.7.0
AArch64MCTargetDesc.h
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1 //===-- AArch64MCTargetDesc.h - AArch64 Target Descriptions -----*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides AArch64 specific target descriptions.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64MCTARGETDESC_H
15 #define LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64MCTARGETDESC_H
16 
17 #include "llvm/Support/DataTypes.h"
18 #include <string>
19 
20 namespace llvm {
21 class formatted_raw_ostream;
22 class MCAsmBackend;
23 class MCCodeEmitter;
24 class MCContext;
25 class MCInstrInfo;
26 class MCInstPrinter;
27 class MCRegisterInfo;
28 class MCObjectWriter;
29 class MCStreamer;
30 class MCSubtargetInfo;
31 class MCTargetStreamer;
32 class StringRef;
33 class Target;
34 class Triple;
35 class raw_ostream;
36 class raw_pwrite_stream;
37 
38 extern Target TheAArch64leTarget;
39 extern Target TheAArch64beTarget;
40 extern Target TheARM64Target;
41 
42 MCCodeEmitter *createAArch64MCCodeEmitter(const MCInstrInfo &MCII,
43  const MCRegisterInfo &MRI,
44  MCContext &Ctx);
45 MCAsmBackend *createAArch64leAsmBackend(const Target &T,
46  const MCRegisterInfo &MRI,
47  const Triple &TT, StringRef CPU);
48 MCAsmBackend *createAArch64beAsmBackend(const Target &T,
49  const MCRegisterInfo &MRI,
50  const Triple &TT, StringRef CPU);
51 
52 MCObjectWriter *createAArch64ELFObjectWriter(raw_pwrite_stream &OS,
53  uint8_t OSABI,
54  bool IsLittleEndian);
55 
56 MCObjectWriter *createAArch64MachObjectWriter(raw_pwrite_stream &OS,
57  uint32_t CPUType,
58  uint32_t CPUSubtype);
59 
60 MCTargetStreamer *createAArch64AsmTargetStreamer(MCStreamer &S,
61  formatted_raw_ostream &OS,
62  MCInstPrinter *InstPrint,
63  bool isVerboseAsm);
64 
65 MCTargetStreamer *createAArch64ObjectTargetStreamer(MCStreamer &S,
66  const MCSubtargetInfo &STI);
67 
68 } // End llvm namespace
69 
70 // Defines symbolic names for AArch64 registers. This defines a mapping from
71 // register name to register number.
72 //
73 #define GET_REGINFO_ENUM
74 #include "AArch64GenRegisterInfo.inc"
75 
76 // Defines symbolic names for the AArch64 instructions.
77 //
78 #define GET_INSTRINFO_ENUM
79 #include "AArch64GenInstrInfo.inc"
80 
81 #define GET_SUBTARGETINFO_ENUM
82 #include "AArch64GenSubtargetInfo.inc"
83 
84 #endif
MCAsmBackend * createAArch64beAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU)
MCObjectWriter * createAArch64ELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI, bool IsLittleEndian)
Target TheARM64Target
MCObjectWriter * createAArch64MachObjectWriter(raw_pwrite_stream &OS, uint32_t CPUType, uint32_t CPUSubtype)
MCTargetStreamer * createAArch64ObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
Target TheAArch64leTarget
MCCodeEmitter * createAArch64MCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
Target TheAArch64beTarget
MCAsmBackend * createAArch64leAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU)
MCTargetStreamer * createAArch64AsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, bool isVerboseAsm)