15 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
16 #define LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
26 namespace AArch64ISD {
216 class AArch64Subtarget;
217 class AArch64TargetMachine;
220 bool RequireStrictAlign;
234 unsigned Depth = 0)
const override;
242 bool *
Fast =
nullptr)
const override {
243 if (RequireStrictAlign)
282 EVT VT)
const override;
294 unsigned Intrinsic)
const override;
306 unsigned &RequiredAligment)
const override;
307 bool hasPairedLoad(
EVT LoadedType,
unsigned &RequiredAligment)
const override;
314 unsigned Factor)
const override;
316 unsigned Factor)
const override;
322 bool IsMemset,
bool ZeroMemset,
bool MemcpyStrSrc,
328 unsigned AS)
const override;
336 unsigned AS)
const override;
352 Type *Ty)
const override;
376 void addTypeForNEON(
EVT VT,
EVT PromotedBitwiseVT);
377 void addDRTypeForNEON(
MVT VT);
378 void addQRTypeForNEON(
MVT VT);
386 SDValue LowerCall(CallLoweringInfo & ,
393 bool isThisReturn,
SDValue ThisVal)
const;
395 bool isEligibleForTailCallOptimization(
397 bool isCalleeStructRet,
bool isCallerStructRet,
408 bool DoesCalleeRestoreStack(
CallingConv::ID CallCC,
bool TailCallOpt)
const;
472 std::vector<SDNode *> *Created)
const override;
473 bool combineRepeatedFPDivisors(
unsigned NumUsers)
const override;
476 unsigned getRegisterByName(
const char* RegName,
EVT VT,
482 getSingleConstraintMatchWeight(AsmOperandInfo &
info,
483 const char *constraint)
const override;
485 std::pair<unsigned, const TargetRegisterClass *>
488 void LowerAsmOperandForConstraint(
SDValue Op, std::string &Constraint,
489 std::vector<SDValue> &Ops,
492 unsigned getInlineAsmMemConstraint(
StringRef ConstraintCode)
const override {
493 if (ConstraintCode ==
"Q")
501 bool isUsedByReturnOnly(SDNode *
N, SDValue &Chain)
const override;
502 bool mayBeEmittedAsTailCall(CallInst *CI)
const override;
503 bool getIndexedAddressParts(SDNode *Op, SDValue &Base, SDValue &Offset,
505 SelectionDAG &DAG)
const;
506 bool getPreIndexedAddressParts(SDNode *
N, SDValue &Base, SDValue &Offset,
508 SelectionDAG &DAG)
const override;
509 bool getPostIndexedAddressParts(SDNode *
N, SDNode *Op, SDValue &Base,
511 SelectionDAG &DAG)
const override;
513 void ReplaceNodeResults(SDNode *
N, SmallVectorImpl<SDValue> &Results,
514 SelectionDAG &DAG)
const override;
516 bool functionArgumentNeedsConsecutiveRegisters(
Type *Ty,
518 bool isVarArg)
const override;
unsigned getFunctionAlignment(const Function *F) const
getFunctionAlignment - Return the Log2 alignment of this function.
BUILTIN_OP_END - This must be the last enum value in this list.
A parsed version of the target data layout string in and methods for querying it. ...
const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const override
Returns a 0 terminated array of registers that can be safely used as scratch registers.
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT) const override
Return the preferred vector type legalization action.
CallInst - This class represents a function call, abstracting a target machine's calling convention...
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override
Return the cost of the scaling factor used in the addressing mode represented by AM for this target...
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
ShuffleVectorInst - This instruction constructs a fixed permutation of two input vectors.
LoadInst - an instruction for reading from memory.
AtomicRMWInst - an instruction that atomically reads a memory location, combines it with another valu...
MachineBasicBlock * EmitF128CSEL(MachineInstr *MI, MachineBasicBlock *BB) const
bool lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const override
Lower an interleaved load into a ldN intrinsic.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
AtomicRMWExpansionKind
Enum that specifies what a AtomicRMWInst is expanded to, if at all.
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - Return the ISD::SETCC ValueType
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace=0, unsigned Align=1, bool *Fast=nullptr) const override
allowsMisalignedMemoryAccesses - Returns true if the target allows unaligned memory accesses of the s...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
StoreInst - an instruction for storing to memory.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...
bool isFPImmLegal(const APFloat &Imm, EVT VT) const override
Returns true if the target can instruction select the specified FP immediate natively.
TargetLoweringBase::AtomicRMWExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all...
void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth=0) const override
computeKnownBitsForTargetNode - Determine which of the bits specified in Mask are known to be either ...
bool hasPairedLoad(Type *LoadedType, unsigned &RequiredAligment) const override
Return true if the target supplies and combines to a paired load two loaded values of type LoadedType...
bool isLegalICmpImmediate(int64_t) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
Return true if it's free to truncate a value of type Ty1 to type Ty2.
A self-contained host- and target-independent arbitrary-precision floating-point software implementat...
bool hasLoadLinkedStoreConditional() const override
True if AtomicExpandPass should use emitLoadLinked/emitStoreConditional and expand AtomicCmpXchgInst...
bool isZExtFree(Type *Ty1, Type *Ty2) const override
Return true if any actual instruction that defines a value of type Ty1 implicitly zero-extends the va...
MVT - Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
This is an important class for using LLVM in a threaded context.
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
bool isDesirableToCommuteWithShift(const SDNode *N) const override
Returns false if N is a bit extraction pattern of (X >> C) & Mask.
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Returns true if it is beneficial to convert a load of a constant to just the constant itself...
EVT - Extended Value Type.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
CCState - This class holds information needed while lowering arguments and return values...
EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, MachineFunction &MF) const override
Returns the target specific optimal type for load and store operations as a result of memset...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
AArch64TargetLowering(const TargetMachine &TM, const AArch64Subtarget &STI)
Provides information about what library functions are available for the current target.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Represents one node in the SelectionDAG.
bool isProfitableToHoist(Instruction *I) const override
Check if it is profitable to hoist instruction in then/else to if.
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const override
Lower an interleaved store into a stN intrinsic.
CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const
Selects the correct CCAssignFn for a given CallingConvention value.
bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override
Returns true if the given (atomic) store should be expanded by the IR-level AtomicExpand pass into an...
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Class for arbitrary precision integers.
AddrMode
ARM Addressing Modes.
Representation of each machine instruction.
bool shouldExpandAtomicLoadInIR(LoadInst *LI) const override
Returns true if the given (atomic) load should be expanded by the IR-level AtomicExpand pass into a l...
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
createFastISel - This method returns a target specific FastISel object, or null if the target does no...
Fast - This calling convention attempts to make calls as fast as possible (e.g.
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Value * emitLoadLinked(IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const override
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type...
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, unsigned Intrinsic) const override
getTgtMemIntrinsic - Represent NEON load and store intrinsics as MemIntrinsicNodes.
bool useLoadStackGuardNode() const override
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
bool isLegalAddImmediate(int64_t) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
LLVM Value Representation.
Value * emitStoreConditional(IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const override
Perform a store-conditional operation to Addr.
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
unsigned getMaxSupportedInterleaveFactor() const override
Get the maximum supported factor for interleaved memory accesses.
Primary interface to the complete machine description for the target machine.
StringRef - Represent a constant reference to a string, i.e.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
bool isShuffleMaskLegal(const SmallVectorImpl< int > &M, EVT VT) const override
isShuffleMaskLegal - Return true if the given shuffle mask can be codegen'd directly, or if it should be stack expanded.
This file describes how to lower LLVM code to machine code.
bool isFMAFasterThanFMulAndFAdd(EVT VT) const override
isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster than a pair of fmul and fadd i...
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.