LLVM  3.7.0
AArch64InstrInfo.h
Go to the documentation of this file.
1 //===- AArch64InstrInfo.h - AArch64 Instruction Information -----*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the AArch64 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
15 #define LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
16 
17 #include "AArch64.h"
18 #include "AArch64RegisterInfo.h"
21 
22 #define GET_INSTRINFO_HEADER
23 #include "AArch64GenInstrInfo.inc"
24 
25 namespace llvm {
26 
27 class AArch64Subtarget;
28 class AArch64TargetMachine;
29 
31  // Reserve bits in the MachineMemOperand target hint flags, starting at 1.
32  // They will be shifted into MOTargetHintStart when accessed.
33  enum TargetMemOperandFlags {
34  MOSuppressPair = 1
35  };
36 
37  const AArch64RegisterInfo RI;
38  const AArch64Subtarget &Subtarget;
39 
40 public:
41  explicit AArch64InstrInfo(const AArch64Subtarget &STI);
42 
43  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
44  /// such, whenever a client has an instance of instruction info, it should
45  /// always be able to get register info as well (through this method).
46  const AArch64RegisterInfo &getRegisterInfo() const { return RI; }
47 
48  unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
49 
50  bool isAsCheapAsAMove(const MachineInstr *MI) const override;
51 
52  bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
53  unsigned &DstReg, unsigned &SubIdx) const override;
54 
55  bool
57  AliasAnalysis *AA = nullptr) const override;
58 
59  unsigned isLoadFromStackSlot(const MachineInstr *MI,
60  int &FrameIndex) const override;
61  unsigned isStoreToStackSlot(const MachineInstr *MI,
62  int &FrameIndex) const override;
63 
64  /// Returns true if there is a shiftable register and that the shift value
65  /// is non-zero.
66  bool hasShiftedReg(const MachineInstr *MI) const;
67 
68  /// Returns true if there is an extendable register and that the extending
69  /// value is non-zero.
70  bool hasExtendedReg(const MachineInstr *MI) const;
71 
72  /// \brief Does this instruction set its full destination register to zero?
73  bool isGPRZero(const MachineInstr *MI) const;
74 
75  /// \brief Does this instruction rename a GPR without modifying bits?
76  bool isGPRCopy(const MachineInstr *MI) const;
77 
78  /// \brief Does this instruction rename an FPR without modifying bits?
79  bool isFPRCopy(const MachineInstr *MI) const;
80 
81  /// Return true if this is load/store scales or extends its register offset.
82  /// This refers to scaling a dynamic index as opposed to scaled immediates.
83  /// MI should be a memory op that allows scaled addressing.
84  bool isScaledAddr(const MachineInstr *MI) const;
85 
86  /// Return true if pairing the given load or store is hinted to be
87  /// unprofitable.
88  bool isLdStPairSuppressed(const MachineInstr *MI) const;
89 
90  /// Hint that pairing the given load or store is unprofitable.
91  void suppressLdStPair(MachineInstr *MI) const;
92 
93  bool getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
94  unsigned &Offset,
95  const TargetRegisterInfo *TRI) const override;
96 
97  bool getMemOpBaseRegImmOfsWidth(MachineInstr *LdSt, unsigned &BaseReg,
98  int &Offset, int &Width,
99  const TargetRegisterInfo *TRI) const;
100 
101  bool enableClusterLoads() const override { return true; }
102 
103  bool shouldClusterLoads(MachineInstr *FirstLdSt, MachineInstr *SecondLdSt,
104  unsigned NumLoads) const override;
105 
107  MachineInstr *Second) const override;
108 
110  uint64_t Offset, const MDNode *Var,
111  const MDNode *Expr, DebugLoc DL) const;
113  DebugLoc DL, unsigned DestReg, unsigned SrcReg,
114  bool KillSrc, unsigned Opcode,
115  llvm::ArrayRef<unsigned> Indices) const;
117  DebugLoc DL, unsigned DestReg, unsigned SrcReg,
118  bool KillSrc) const override;
119 
121  MachineBasicBlock::iterator MBBI, unsigned SrcReg,
122  bool isKill, int FrameIndex,
123  const TargetRegisterClass *RC,
124  const TargetRegisterInfo *TRI) const override;
125 
127  MachineBasicBlock::iterator MBBI, unsigned DestReg,
128  int FrameIndex, const TargetRegisterClass *RC,
129  const TargetRegisterInfo *TRI) const override;
130 
133  ArrayRef<unsigned> Ops,
135  int FrameIndex) const override;
136 
138  MachineBasicBlock *&FBB,
140  bool AllowModify = false) const override;
141  unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
144  DebugLoc DL) const override;
145  bool
148  unsigned, unsigned, int &, int &, int &) const override;
150  DebugLoc DL, unsigned DstReg, ArrayRef<MachineOperand> Cond,
151  unsigned TrueReg, unsigned FalseReg) const override;
152  void getNoopForMachoTarget(MCInst &NopInst) const override;
153 
154  /// analyzeCompare - For a comparison instruction, return the source registers
155  /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
156  /// Return true if the comparison instruction can be analyzed.
157  bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
158  unsigned &SrcReg2, int &CmpMask,
159  int &CmpValue) const override;
160  /// optimizeCompareInstr - Convert the instruction supplying the argument to
161  /// the comparison into one that sets the zero bit in the flags register.
162  bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
163  unsigned SrcReg2, int CmpMask, int CmpValue,
164  const MachineRegisterInfo *MRI) const override;
165  bool optimizeCondBranch(MachineInstr *MI) const override;
166  /// Return true when there is potentially a faster code sequence
167  /// for an instruction chain ending in <Root>. All potential patterns are
168  /// listed in the <Patterns> array.
171  const override;
172 
173  /// When getMachineCombinerPatterns() finds patterns, this function generates
174  /// the instructions that could replace the original code sequence
179  DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
180  /// useMachineCombiner - AArch64 supports MachineCombiner
181  bool useMachineCombiner() const override;
182 
184 private:
185  void instantiateCondBranch(MachineBasicBlock &MBB, DebugLoc DL,
186  MachineBasicBlock *TBB,
187  ArrayRef<MachineOperand> Cond) const;
188 };
189 
190 /// emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg
191 /// plus Offset. This is intended to be used from within the prolog/epilog
192 /// insertion (PEI) pass, where a virtual scratch register may be allocated
193 /// if necessary, to be replaced by the scavenger at the end of PEI.
194 void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
195  DebugLoc DL, unsigned DestReg, unsigned SrcReg, int Offset,
196  const TargetInstrInfo *TII,
198  bool SetNZCV = false);
199 
200 /// rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the
201 /// FP. Return false if the offset could not be handled directly in MI, and
202 /// return the left-over portion by reference.
203 bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
204  unsigned FrameReg, int &Offset,
205  const AArch64InstrInfo *TII);
206 
207 /// \brief Use to report the frame offset status in isAArch64FrameOffsetLegal.
209  AArch64FrameOffsetCannotUpdate = 0x0, ///< Offset cannot apply.
210  AArch64FrameOffsetIsLegal = 0x1, ///< Offset is legal.
211  AArch64FrameOffsetCanUpdate = 0x2 ///< Offset can apply, at least partly.
212 };
213 
214 /// \brief Check if the @p Offset is a valid frame offset for @p MI.
215 /// The returned value reports the validity of the frame offset for @p MI.
216 /// It uses the values defined by AArch64FrameOffsetStatus for that.
217 /// If result == AArch64FrameOffsetCannotUpdate, @p MI cannot be updated to
218 /// use an offset.eq
219 /// If result & AArch64FrameOffsetIsLegal, @p Offset can completely be
220 /// rewriten in @p MI.
221 /// If result & AArch64FrameOffsetCanUpdate, @p Offset contains the
222 /// amount that is off the limit of the legal offset.
223 /// If set, @p OutUseUnscaledOp will contain the whether @p MI should be
224 /// turned into an unscaled operator, which opcode is in @p OutUnscaledOp.
225 /// If set, @p EmittableOffset contains the amount that can be set in @p MI
226 /// (possibly with @p OutUnscaledOp if OutUseUnscaledOp is true) and that
227 /// is a legal offset.
228 int isAArch64FrameOffsetLegal(const MachineInstr &MI, int &Offset,
229  bool *OutUseUnscaledOp = nullptr,
230  unsigned *OutUnscaledOp = nullptr,
231  int *EmittableOffset = nullptr);
232 
233 static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; }
234 
235 static inline bool isCondBranchOpcode(int Opc) {
236  switch (Opc) {
237  case AArch64::Bcc:
238  case AArch64::CBZW:
239  case AArch64::CBZX:
240  case AArch64::CBNZW:
241  case AArch64::CBNZX:
242  case AArch64::TBZW:
243  case AArch64::TBZX:
244  case AArch64::TBNZW:
245  case AArch64::TBNZX:
246  return true;
247  default:
248  return false;
249  }
250 }
251 
252 static inline bool isIndirectBranchOpcode(int Opc) { return Opc == AArch64::BR; }
253 
254 } // end namespace llvm
255 
256 #endif
bool hasExtendedReg(const MachineInstr *MI) const
Returns true if there is an extendable register and that the extending value is non-zero.
unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const override
bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const override
optimizeCompareInstr - Convert the instruction supplying the argument to the comparison into one that...
const AArch64RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex) const override
bool getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg, unsigned &Offset, const TargetRegisterInfo *TRI) const override
Offset can apply, at least partly.
A debug info location.
Definition: DebugLoc.h:34
Metadata node.
Definition: Metadata.h:740
void getNoopForMachoTarget(MCInst &NopInst) const override
bool ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
bool optimizeCondBranch(MachineInstr *MI) const override
Replace csincr-branch sequence by simple conditional branch.
bool isLdStPairSuppressed(const MachineInstr *MI) const
Return true if pairing the given load or store is hinted to be unprofitable.
bool getMemOpBaseRegImmOfsWidth(MachineInstr *LdSt, unsigned &BaseReg, int &Offset, int &Width, const TargetRegisterInfo *TRI) const
const HexagonInstrInfo * TII
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APInt.h:33
bool useMachineCombiner() const override
useMachineCombiner - AArch64 supports MachineCombiner
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, DebugLoc DL) const override
int isAArch64FrameOffsetLegal(const MachineInstr &MI, int &Offset, bool *OutUseUnscaledOp=nullptr, unsigned *OutUnscaledOp=nullptr, int *EmittableOffset=nullptr)
Check if the Offset is a valid frame offset for MI.
AArch64InstrInfo(const AArch64Subtarget &STI)
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
MachineInstr * emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx, uint64_t Offset, const MDNode *Var, const MDNode *Expr, DebugLoc DL) const
bool isAsCheapAsAMove(const MachineInstr *MI) const override
bool enableClusterLoads() const override
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override
bool hasShiftedReg(const MachineInstr *MI) const
Returns true if there is a shiftable register and that the shift value is non-zero.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:150
static bool isCondBranchOpcode(int Opc)
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern::MC_PATTERN > &Patterns) const override
Return true when there is potentially a faster code sequence for an instruction chain ending in <Root...
bundle_iterator< MachineInstr, instr_iterator > iterator
unsigned RemoveBranch(MachineBasicBlock &MBB) const override
Control flow instructions. These all have token chains.
Definition: ISDOpcodes.h:533
void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, int Offset, const TargetInstrInfo *TII, MachineInstr::MIFlag=MachineInstr::NoFlags, bool SetNZCV=false)
emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg plus Offset.
bool isFPRCopy(const MachineInstr *MI) const
Does this instruction rename an FPR without modifying bits?
bundle_iterator - MachineBasicBlock iterator that automatically skips over MIs that are inside bundle...
bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const AArch64InstrInfo *TII)
rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the FP.
bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
bool isGPRZero(const MachineInstr *MI) const
Does this instruction set its full destination register to zero?
bool shouldScheduleAdjacent(MachineInstr *First, MachineInstr *Second) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override
AArch64FrameOffsetStatus
Use to report the frame offset status in isAArch64FrameOffsetLegal.
bool shouldClusterLoads(MachineInstr *FirstLdSt, MachineInstr *SecondLdSt, unsigned NumLoads) const override
Detect opportunities for ldp/stp formation.
static bool isIndirectBranchOpcode(int Opc)
void suppressLdStPair(MachineInstr *MI) const
Hint that pairing the given load or store is unprofitable.
unsigned GetInstSizeInBytes(const MachineInstr *MI) const
GetInstSize - Return the number of bytes of code the specified instruction may be.
static bool isUncondBranchOpcode(int Opc)
void copyPhysRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc, unsigned Opcode, llvm::ArrayRef< unsigned > Indices) const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:51
bool isGPRCopy(const MachineInstr *MI) const
Does this instruction rename a GPR without modifying bits?
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
#define I(x, y, z)
Definition: MD5.cpp:54
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
void genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern::MC_PATTERN Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could...
bool areMemAccessesTriviallyDisjoint(MachineInstr *MIa, MachineInstr *MIb, AliasAnalysis *AA=nullptr) const override
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex) const
Target-dependent implementation for foldMemoryOperand.
unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const override
bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const override
analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2...
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
bool isScaledAddr(const MachineInstr *MI) const
Return true if this is load/store scales or extends its register offset.
bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override