47 return R == Hexagon::R0 || R == Hexagon::R1 || R ==
Hexagon::R2 ||
48 R == Hexagon::R3 || R == Hexagon::D0 || R == Hexagon::D1;
52 return Hexagon::R16 <= Reg && Reg <= Hexagon::R27;
58 static const MCPhysReg CallerSavedRegsV4[] = {
60 Hexagon::R5,
Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9,
61 Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,
66 switch (HST.getHexagonArchVersion()) {
69 return CallerSavedRegsV4;
72 "Callee saved registers requested for unknown archtecture version");
78 static const MCPhysReg CalleeSavedRegsV3[] = {
79 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
80 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
81 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0
87 return CalleeSavedRegsV3;
89 llvm_unreachable(
"Callee saved registers requested for unknown architecture "
98 Reserved.
set(Hexagon::R29);
99 Reserved.
set(Hexagon::R30);
100 Reserved.
set(Hexagon::R31);
101 Reserved.
set(Hexagon::D14);
102 Reserved.
set(Hexagon::D15);
103 Reserved.
set(Hexagon::LC0);
104 Reserved.
set(Hexagon::LC1);
105 Reserved.
set(Hexagon::SA0);
106 Reserved.
set(Hexagon::SA1);
112 int SPAdj,
unsigned FIOp,
116 assert(SPAdj == 0 &&
"Unexpected");
125 auto &HFI = *HST.getFrameLowering();
135 if (!HFI.hasFP(MF)) {
136 assert(!HasAlloca && !HasAlign &&
"This function must have frame pointer");
144 AP = AI->getOperand(0).getReg();
154 bool UseFP =
false, UseAP =
false;
156 UseFP = HasAlloca || HasAlign;
167 bool ValidSP = HII.isValidOffset(Opc, FrameSize+Offset);
168 bool ValidFP = HII.isValidOffset(Opc, Offset);
171 int64_t RealOffset = Offset;
172 if (!UseFP && !UseAP)
173 RealOffset = FrameSize+Offset;
176 case Hexagon::TFR_FIA:
177 MI.
setDesc(HII.get(Hexagon::A2_addi));
181 case Hexagon::TFR_FI:
183 MI.
setDesc(HII.get(Hexagon::A2_addi));
208 dbgs() <<
"In function ";
210 else dbgs() <<
"<?>";
244 return TFI->
hasFP(MF);
260 #define GET_REGINFO_TARGET_DESC
261 #include "HexagonGenRegisterInfo.inc"
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
#define HEXAGON_RESERVED_REG_1
const HexagonArchEnum & getHexagonArchVersion() const
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
int getNumber() const
getNumber - MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a M...
unsigned getRARegister() const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
#define HEXAGON_RESERVED_REG_2
bool isObjectPreAllocated(int ObjectIdx) const
Return true if the object was pre-allocated into the local block.
StringRef getName() const
Return a constant reference to the value's name.
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
unsigned getFrameRegister() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
const MachineBasicBlock * getParent() const
const MCPhysReg * getCallerSavedRegs(const MachineFunction *MF) const
bool isDebugValue() const
unsigned getFirstCallerSavedNonParamReg() const
bundle_iterator< MachineInstr, instr_iterator > iterator
bool isEHReturnCalleeSaveReg(unsigned Reg) const
const MachineOperand & getOperand(unsigned i) const
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Representation of each machine instruction.
bool useFPForScavengingIndex(const MachineFunction &MF) const override
Returns true if the frame pointer is valid.
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
bool needsStackRealignment(const MachineFunction &MF) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
unsigned getStackRegister() const
const HexagonInstrInfo * getInstrInfo() const override
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
bool isCalleeSaveReg(unsigned Reg) const
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...