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LLVM
3.7.0
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#include <X86ISelLowering.h>
Public Member Functions | |
| X86TargetLowering (const X86TargetMachine &TM, const X86Subtarget &STI) | |
| unsigned | getJumpTableEncoding () const override |
| Return the entry encoding for a jump table in the current function. More... | |
| bool | useSoftFloat () const override |
| MVT | getScalarShiftAmountTy (const DataLayout &, EVT) const override |
| EVT is not used in-tree, but is used by out-of-tree target. More... | |
| const MCExpr * | LowerCustomJumpTableEntry (const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned uid, MCContext &Ctx) const override |
| SDValue | getPICJumpTableRelocBase (SDValue Table, SelectionDAG &DAG) const override |
| Returns relocation base for the given PIC jumptable. More... | |
| const MCExpr * | getPICJumpTableRelocBaseExpr (const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const override |
| This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase, but as an MCExpr. More... | |
| unsigned | getByValTypeAlignment (Type *Ty, const DataLayout &DL) const override |
| Return the desired alignment for ByVal aggregate function arguments in the caller parameter area. More... | |
| EVT | getOptimalMemOpType (uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, MachineFunction &MF) const override |
| Returns the target specific optimal type for load and store operations as a result of memset, memcpy, and memmove lowering. More... | |
| bool | isSafeMemOpType (MVT VT) const override |
| Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline. More... | |
| bool | allowsMisalignedMemoryAccesses (EVT VT, unsigned AS, unsigned Align, bool *Fast) const override |
| Returns true if the target allows unaligned memory accesses of the specified type. More... | |
| SDValue | LowerOperation (SDValue Op, SelectionDAG &DAG) const override |
| Provide custom lowering hooks for some operations. More... | |
| void | ReplaceNodeResults (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override |
| Replace the results of node with an illegal result type with new values built out of custom code. More... | |
| SDValue | PerformDAGCombine (SDNode *N, DAGCombinerInfo &DCI) const override |
| This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for. More... | |
| bool | isTypeDesirableForOp (unsigned Opc, EVT VT) const override |
| Return true if the target has native support for the specified value type and it is 'desirable' to use the type for the given node type. More... | |
| bool | IsDesirableToPromoteOp (SDValue Op, EVT &PVT) const override |
| Return true if the target has native support for the specified value type and it is 'desirable' to use the type. More... | |
| MachineBasicBlock * | EmitInstrWithCustomInserter (MachineInstr *MI, MachineBasicBlock *MBB) const override |
| This method should be implemented by targets that mark instructions with the 'usesCustomInserter' flag. More... | |
| const char * | getTargetNodeName (unsigned Opcode) const override |
| This method returns the name of a target specific DAG node. More... | |
| bool | isCheapToSpeculateCttz () const override |
| Return true if it is cheap to speculate a call to intrinsic cttz. More... | |
| bool | isCheapToSpeculateCtlz () const override |
| Return true if it is cheap to speculate a call to intrinsic ctlz. More... | |
| EVT | getSetCCResultType (const DataLayout &DL, LLVMContext &Context, EVT VT) const override |
| Return the value type to use for ISD::SETCC. More... | |
| void | computeKnownBitsForTargetNode (const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth=0) const override |
| Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets. More... | |
| unsigned | ComputeNumSignBitsForTargetNode (SDValue Op, const SelectionDAG &DAG, unsigned Depth) const override |
| Determine the number of bits in the operation that are sign bits. More... | |
| bool | isGAPlusOffset (SDNode *N, const GlobalValue *&GA, int64_t &Offset) const override |
| isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + offset. More... | |
| SDValue | getReturnAddressFrameIndex (SelectionDAG &DAG) const |
| bool | ExpandInlineAsm (CallInst *CI) const override |
| This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to. More... | |
| ConstraintType | getConstraintType (StringRef Constraint) const override |
| getConstraintType - Given a constraint letter, return the type of constraint it is for this target. More... | |
| ConstraintWeight | getSingleConstraintMatchWeight (AsmOperandInfo &info, const char *constraint) const override |
| Examine constraint string and operand type and determine a weight value. More... | |
| const char * | LowerXConstraint (EVT ConstraintVT) const override |
| LowerXConstraint - try to replace an X constraint, which matches anything, with another that has more specific requirements based on the type of the corresponding operand. More... | |
| void | LowerAsmOperandForConstraint (SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override |
| Lower the specified operand into the Ops vector. More... | |
| unsigned | getInlineAsmMemConstraint (StringRef ConstraintCode) const override |
| std::pair< unsigned, const TargetRegisterClass * > | getRegForInlineAsmConstraint (const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override |
| Given a physical register constraint (e.g. More... | |
| bool | isLegalAddressingMode (const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override |
| Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type. More... | |
| bool | isLegalICmpImmediate (int64_t Imm) const override |
| Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register. More... | |
| bool | isLegalAddImmediate (int64_t Imm) const override |
| Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register and the immediate without having to materialize the immediate into a register. More... | |
| int | getScalingFactorCost (const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override |
| Return the cost of the scaling factor used in the addressing mode represented by AM for this target, for a load/store of the specified type. More... | |
| bool | isVectorShiftByScalarCheap (Type *Ty) const override |
| Return true if it's significantly cheaper to shift a vector by a uniform scalar than by an amount which will vary across each lane. More... | |
| bool | isTruncateFree (Type *Ty1, Type *Ty2) const override |
| Return true if it's free to truncate a value of type Ty1 to type Ty2. More... | |
| bool | isTruncateFree (EVT VT1, EVT VT2) const override |
| bool | allowTruncateForTailCall (Type *Ty1, Type *Ty2) const override |
| Return true if a truncation from Ty1 to Ty2 is permitted when deciding whether a call is in tail position. More... | |
| bool | isZExtFree (Type *Ty1, Type *Ty2) const override |
| Return true if any actual instruction that defines a value of type Ty1 implicit zero-extends the value to Ty2 in the result register. More... | |
| bool | isZExtFree (EVT VT1, EVT VT2) const override |
| bool | isZExtFree (SDValue Val, EVT VT2) const override |
| Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicitly zero-extended such as ARM ldrb / ldrh or because it's folded such as X86 zero-extending loads). More... | |
| bool | isVectorLoadExtDesirable (SDValue) const override |
| Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable. More... | |
| bool | isFMAFasterThanFMulAndFAdd (EVT VT) const override |
| Return true if an FMA operation is faster than a pair of fmul and fadd instructions. More... | |
| bool | isNarrowingProfitable (EVT VT1, EVT VT2) const override |
| Return true if it's profitable to narrow operations of type VT1 to VT2. More... | |
| bool | isFPImmLegal (const APFloat &Imm, EVT VT) const override |
| Returns true if the target can instruction select the specified FP immediate natively. More... | |
| bool | isShuffleMaskLegal (const SmallVectorImpl< int > &Mask, EVT VT) const override |
| Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks. More... | |
| bool | isVectorClearMaskLegal (const SmallVectorImpl< int > &Mask, EVT VT) const override |
| Similar to isShuffleMaskLegal. More... | |
| bool | ShouldShrinkFPConstant (EVT VT) const override |
| If true, then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime. More... | |
| bool | shouldReduceLoadWidth (SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const override |
| Return true if we believe it is correct and profitable to reduce the load node to a smaller type. More... | |
| bool | isScalarFPTypeInSSEReg (EVT VT) const |
| Return true if the specified scalar FP type is computed in an SSE register, not on the X87 floating point stack. More... | |
| bool | isTargetFTOL () const |
| Return true if the target uses the MSVC _ftol2 routine for fptoui. More... | |
| bool | isIntegerTypeFTOL (EVT VT) const |
| Return true if the MSVC _ftol2 routine should be used for fptoui to the given type. More... | |
| bool | shouldConvertConstantLoadToIntImm (const APInt &Imm, Type *Ty) const override |
| Returns true if it is beneficial to convert a load of a constant to just the constant itself. More... | |
| bool | isExtractSubvectorCheap (EVT ResVT, unsigned Index) const override |
| Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index. More... | |
| const char * | getClearCacheBuiltinName () const override |
| Intel processors have a unified instruction and data cache. More... | |
| unsigned | getRegisterByName (const char *RegName, EVT VT, SelectionDAG &DAG) const override |
| Return the register ID of the name passed in. More... | |
| FastISel * | createFastISel (FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override |
| This method returns a target specific FastISel object, or null if the target does not support "fast" ISel. More... | |
| bool | getStackCookieLocation (unsigned &AddressSpace, unsigned &Offset) const override |
| Return true if the target stores stack protector cookies at a fixed offset in some non-standard address space, and populates the address space and offset as appropriate. More... | |
| SDValue | BuildFILD (SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot, SelectionDAG &DAG) const |
| bool | isNoopAddrSpaceCast (unsigned SrcAS, unsigned DestAS) const override |
| Returns true if a cast between SrcAS and DestAS is a noop. More... | |
| bool | useLoadStackGuardNode () const override |
| If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector. More... | |
| LegalizeTypeAction | getPreferredVectorAction (EVT VT) const override |
| Customize the preferred legalization strategy for certain types. More... | |
Public Member Functions inherited from llvm::TargetLowering | |
| TargetLowering (const TargetMachine &TM) | |
| NOTE: The TargetMachine owns TLOF. More... | |
| virtual bool | getPreIndexedAddressParts (SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const |
| Returns true by value, base pointer and offset pointer and addressing mode by reference if the node's address can be legally represented as pre-indexed load / store address. More... | |
| virtual bool | getPostIndexedAddressParts (SDNode *, SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const |
| Returns true by value, base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store. More... | |
| virtual bool | isOffsetFoldingLegal (const GlobalAddressSDNode *GA) const |
| Return true if folding a constant offset with the given GlobalAddress is legal. More... | |
| bool | isInTailCallPosition (SelectionDAG &DAG, SDNode *Node, SDValue &Chain) const |
| Check whether a given call node is in tail position within its function. More... | |
| void | softenSetCCOperands (SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, SDLoc DL) const |
| SoftenSetCCOperands - Soften the operands of a comparison. More... | |
| std::pair< SDValue, SDValue > | makeLibCall (SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops, unsigned NumOps, bool isSigned, SDLoc dl, bool doesNotReturn=false, bool isReturnValueUsed=true) const |
| Returns a pair of (return value, chain). More... | |
| bool | SimplifyDemandedBits (SDValue Op, const APInt &DemandedMask, APInt &KnownZero, APInt &KnownOne, TargetLoweringOpt &TLO, unsigned Depth=0) const |
| Look at Op. More... | |
| bool | isConstTrueVal (const SDNode *N) const |
| Return if the N is a constant or constant vector equal to the true value from getBooleanContents(). More... | |
| bool | isConstFalseVal (const SDNode *N) const |
| Return if the N is a constant or constant vector equal to the false value from getBooleanContents(). More... | |
| SDValue | SimplifySetCC (EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, SDLoc dl) const |
| Try to simplify a setcc built with the specified operands and cc. More... | |
| virtual bool | isDesirableToCommuteWithShift (const SDNode *N) const |
| Return true if it is profitable to move a following shift through this. More... | |
| virtual bool | isDesirableToTransformToIntegerOp (unsigned, EVT) const |
| Return true if it is profitable for dag combiner to transform a floating point op of specified opcode to a equivalent op of an integer type. More... | |
| std::pair< SDValue, SDValue > | LowerCallTo (CallLoweringInfo &CLI) const |
| This function lowers an abstract call to a function into an actual call. More... | |
| virtual void | HandleByVal (CCState *, unsigned &, unsigned) const |
| Target-specific cleanup for formal ByVal parameters. More... | |
| virtual bool | functionArgumentNeedsConsecutiveRegisters (Type *Ty, CallingConv::ID CallConv, bool isVarArg) const |
| For some targets, an LLVM struct type must be broken down into multiple simple types, but the calling convention specifies that the entire struct must be passed in a block of consecutive registers. More... | |
| virtual SDValue | prepareVolatileOrAtomicLoad (SDValue Chain, SDLoc DL, SelectionDAG &DAG) const |
| This callback is used to prepare for a volatile or atomic load. More... | |
| virtual void | LowerOperationWrapper (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const |
| This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but legal result types. More... | |
| bool | verifyReturnAddressArgumentIsConstant (SDValue Op, SelectionDAG &DAG) const |
| virtual AsmOperandInfoVector | ParseConstraints (const DataLayout &DL, const TargetRegisterInfo *TRI, ImmutableCallSite CS) const |
| Split up the constraint string from the inline assembly value into the specific constraints and their prefixes, and also tie in the associated operand values. More... | |
| virtual ConstraintWeight | getMultipleConstraintMatchWeight (AsmOperandInfo &info, int maIndex) const |
| Examine constraint type and operand type and determine a weight value. More... | |
| virtual void | ComputeConstraintToUse (AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=nullptr) const |
| Determines the constraint code and constraint type to use for the specific AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType. More... | |
| SDValue | BuildSDIV (SDNode *N, const APInt &Divisor, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode * > *Created) const |
| Given an ISD::SDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. More... | |
| SDValue | BuildUDIV (SDNode *N, const APInt &Divisor, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode * > *Created) const |
| Given an ISD::UDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. More... | |
| virtual SDValue | BuildSDIVPow2 (SDNode *N, const APInt &Divisor, SelectionDAG &DAG, std::vector< SDNode * > *Created) const |
| bool | expandMUL (SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT, SelectionDAG &DAG, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) const |
| Expand a MUL into two nodes. More... | |
| bool | expandFP_TO_SINT (SDNode *N, SDValue &Result, SelectionDAG &DAG) const |
| Expand float(f32) to SINT(i64) conversion. More... | |
| virtual void | AdjustInstrPostInstrSelection (MachineInstr *MI, SDNode *Node) const |
| This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag. More... | |
Public Member Functions inherited from llvm::TargetLoweringBase | |
| TargetLoweringBase (const TargetMachine &TM) | |
| NOTE: The TargetMachine owns TLOF. More... | |
| virtual | ~TargetLoweringBase () |
| const TargetMachine & | getTargetMachine () const |
| MVT | getPointerTy (const DataLayout &DL, uint32_t AS=0) const |
| Return the pointer type for the given address space, defaults to the pointer type from the data layout. More... | |
| EVT | getShiftAmountTy (EVT LHSTy, const DataLayout &DL) const |
| virtual MVT | getVectorIdxTy (const DataLayout &DL) const |
| Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR. More... | |
| bool | isSelectExpensive () const |
| Return true if the select operation is expensive for this target. More... | |
| virtual bool | isSelectSupported (SelectSupportKind) const |
| bool | hasMultipleConditionRegisters () const |
| Return true if multiple condition registers are available. More... | |
| bool | hasExtractBitsInsn () const |
| Return true if the target has BitExtract instructions. More... | |
| virtual bool | shouldExpandBuildVectorWithShuffles (EVT, unsigned DefinedValues) const |
| bool | isIntDivCheap () const |
| Return true if integer divide is usually cheaper than a sequence of several shifts, adds, and multiplies for this target. More... | |
| bool | isFsqrtCheap () const |
| Return true if sqrt(x) is as cheap or cheaper than 1 / rsqrt(x) More... | |
| bool | isSlowDivBypassed () const |
| Returns true if target has indicated at least one type should be bypassed. More... | |
| const DenseMap< unsigned int, unsigned int > & | getBypassSlowDivWidths () const |
| Returns map of slow types for division or remainder with corresponding fast types. More... | |
| bool | isPow2SDivCheap () const |
| Return true if pow2 sdiv is cheaper than a chain of sra/srl/add/sra. More... | |
| bool | isJumpExpensive () const |
| Return true if Flow Control is an expensive operation that should be avoided. More... | |
| bool | isPredictableSelectExpensive () const |
| Return true if selects are only cheaper than branches if the branch is unlikely to be predicted right. More... | |
| virtual bool | isLoadBitCastBeneficial (EVT, EVT) const |
| isLoadBitCastBeneficial() - Return true if the following transform is beneficial. More... | |
| virtual bool | storeOfVectorConstantIsCheap (EVT MemVT, unsigned NumElem, unsigned AddrSpace) const |
| Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the given size and type for the address space than to store the individual scalar element constants. More... | |
| bool | isMaskAndBranchFoldingLegal () const |
| Return if the target supports combining a chain like: More... | |
| bool | enableExtLdPromotion () const |
| Return true if the target wants to use the optimization that turns ext(promotableInst1(...(promotableInstN(load)))) into promotedInst1(...(promotedInstN(ext(load)))). More... | |
| virtual bool | canCombineStoreAndExtract (Type *VectorTy, Value *Idx, unsigned &Cost) const |
| Return true if the target can combine store(extractelement VectorTy, Idx). More... | |
| bool | hasFloatingPointExceptions () const |
| Return true if target supports floating point exceptions. More... | |
| virtual bool | enableAggressiveFMAFusion (EVT VT) const |
| Return true if target always beneficiates from combining into FMA for a given value type. More... | |
| virtual MVT::SimpleValueType | getCmpLibcallReturnType () const |
| Return the ValueType for comparison libcalls. More... | |
| BooleanContent | getBooleanContents (bool isVec, bool isFloat) const |
| For targets without i1 registers, this gives the nature of the high-bits of boolean values held in types wider than i1. More... | |
| BooleanContent | getBooleanContents (EVT Type) const |
| Sched::Preference | getSchedulingPreference () const |
| Return target scheduling preference. More... | |
| virtual Sched::Preference | getSchedulingPreference (SDNode *) const |
| Some scheduler, e.g. More... | |
| virtual const TargetRegisterClass * | getRegClassFor (MVT VT) const |
| Return the register class that should be used for the specified value type. More... | |
| virtual const TargetRegisterClass * | getRepRegClassFor (MVT VT) const |
| Return the 'representative' register class for the specified value type. More... | |
| virtual uint8_t | getRepRegClassCostFor (MVT VT) const |
| Return the cost of the 'representative' register class for the specified value type. More... | |
| bool | isTypeLegal (EVT VT) const |
| Return true if the target has native support for the specified value type. More... | |
| const ValueTypeActionImpl & | getValueTypeActions () const |
| LegalizeTypeAction | getTypeAction (LLVMContext &Context, EVT VT) const |
| Return how we should legalize values of this type, either it is already legal (return 'Legal') or we need to promote it to a larger type (return 'Promote'), or we need to expand it into multiple registers of smaller integer type (return 'Expand'). More... | |
| LegalizeTypeAction | getTypeAction (MVT VT) const |
| EVT | getTypeToTransformTo (LLVMContext &Context, EVT VT) const |
| For types supported by the target, this is an identity function. More... | |
| EVT | getTypeToExpandTo (LLVMContext &Context, EVT VT) const |
| For types supported by the target, this is an identity function. More... | |
| unsigned | getVectorTypeBreakdown (LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const |
| Vector types are broken down into some number of legal first class types. More... | |
| virtual bool | getTgtMemIntrinsic (IntrinsicInfo &, const CallInst &, unsigned) const |
| Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (touches memory). More... | |
| virtual bool | canOpTrap (unsigned Op, EVT VT) const |
| Returns true if the operation can trap for the value type. More... | |
| LegalizeAction | getOperationAction (unsigned Op, EVT VT) const |
| Return how this operation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More... | |
| bool | isOperationLegalOrCustom (unsigned Op, EVT VT) const |
| Return true if the specified operation is legal on this target or can be made legal with custom lowering. More... | |
| bool | isOperationLegalOrPromote (unsigned Op, EVT VT) const |
| Return true if the specified operation is legal on this target or can be made legal using promotion. More... | |
| bool | isOperationExpand (unsigned Op, EVT VT) const |
| Return true if the specified operation is illegal on this target or unlikely to be made legal with custom lowering. More... | |
| bool | isOperationLegal (unsigned Op, EVT VT) const |
| Return true if the specified operation is legal on this target. More... | |
| LegalizeAction | getLoadExtAction (unsigned ExtType, EVT ValVT, EVT MemVT) const |
| Return how this load with extension should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More... | |
| bool | isLoadExtLegal (unsigned ExtType, EVT ValVT, EVT MemVT) const |
| Return true if the specified load with extension is legal on this target. More... | |
| bool | isLoadExtLegalOrCustom (unsigned ExtType, EVT ValVT, EVT MemVT) const |
| Return true if the specified load with extension is legal or custom on this target. More... | |
| LegalizeAction | getTruncStoreAction (EVT ValVT, EVT MemVT) const |
| Return how this store with truncation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More... | |
| bool | isTruncStoreLegal (EVT ValVT, EVT MemVT) const |
| Return true if the specified store with truncation is legal on this target. More... | |
| LegalizeAction | getIndexedLoadAction (unsigned IdxMode, MVT VT) const |
| Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More... | |
| bool | isIndexedLoadLegal (unsigned IdxMode, EVT VT) const |
| Return true if the specified indexed load is legal on this target. More... | |
| LegalizeAction | getIndexedStoreAction (unsigned IdxMode, MVT VT) const |
| Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More... | |
| bool | isIndexedStoreLegal (unsigned IdxMode, EVT VT) const |
| Return true if the specified indexed load is legal on this target. More... | |
| LegalizeAction | getCondCodeAction (ISD::CondCode CC, MVT VT) const |
| Return how the condition code should be treated: either it is legal, needs to be expanded to some other code sequence, or the target has a custom expander for it. More... | |
| bool | isCondCodeLegal (ISD::CondCode CC, MVT VT) const |
| Return true if the specified condition code is legal on this target. More... | |
| MVT | getTypeToPromoteTo (unsigned Op, MVT VT) const |
| If the action for this operation is to promote, this method returns the ValueType to promote to. More... | |
| EVT | getValueType (const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const |
| Return the EVT corresponding to this LLVM type. More... | |
| MVT | getSimpleValueType (const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const |
| Return the MVT corresponding to this LLVM type. See getValueType. More... | |
| MVT | getRegisterType (MVT VT) const |
| Return the type of registers that this ValueType will eventually require. More... | |
| MVT | getRegisterType (LLVMContext &Context, EVT VT) const |
| Return the type of registers that this ValueType will eventually require. More... | |
| unsigned | getNumRegisters (LLVMContext &Context, EVT VT) const |
| Return the number of registers that this ValueType will eventually require. More... | |
| bool | hasBigEndianPartOrdering (EVT VT, const DataLayout &DL) const |
| When splitting a value of the specified type into parts, does the Lo or Hi part come first? This usually follows the endianness, except for ppcf128, where the Hi part always comes first. More... | |
| bool | hasTargetDAGCombine (ISD::NodeType NT) const |
| If true, the target has custom DAG combine transformations that it can perform for the specified node. More... | |
| unsigned | getMaxStoresPerMemset (bool OptSize) const |
| Get maximum # of store operations permitted for llvm.memset. More... | |
| unsigned | getMaxStoresPerMemcpy (bool OptSize) const |
| Get maximum # of store operations permitted for llvm.memcpy. More... | |
| unsigned | getMaxStoresPerMemmove (bool OptSize) const |
| Get maximum # of store operations permitted for llvm.memmove. More... | |
| bool | usesUnderscoreSetJmp () const |
| Determine if we should use _setjmp or setjmp to implement llvm.setjmp. More... | |
| bool | usesUnderscoreLongJmp () const |
| Determine if we should use _longjmp or longjmp to implement llvm.longjmp. More... | |
| int | getMinimumJumpTableEntries () const |
| Return integer threshold on number of blocks to use jump tables rather than if sequence. More... | |
| unsigned | getStackPointerRegisterToSaveRestore () const |
| If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore. More... | |
| unsigned | getExceptionPointerRegister () const |
| If a physical register, this returns the register that receives the exception address on entry to a landing pad. More... | |
| unsigned | getExceptionSelectorRegister () const |
| If a physical register, this returns the register that receives the exception typeid on entry to a landing pad. More... | |
| unsigned | getJumpBufSize () const |
| Returns the target's jmp_buf size in bytes (if never set, the default is 200) More... | |
| unsigned | getJumpBufAlignment () const |
| Returns the target's jmp_buf alignment in bytes (if never set, the default is 0) More... | |
| unsigned | getMinStackArgumentAlignment () const |
| Return the minimum stack alignment of an argument. More... | |
| unsigned | getMinFunctionAlignment () const |
| Return the minimum function alignment. More... | |
| unsigned | getPrefFunctionAlignment () const |
| Return the preferred function alignment. More... | |
| virtual unsigned | getPrefLoopAlignment (MachineLoop *ML=nullptr) const |
| Return the preferred loop alignment. More... | |
| bool | getInsertFencesForAtomic () const |
| Return whether the DAG builder should automatically insert fences and reduce ordering for atomics. More... | |
| virtual bool | shouldAlignPointerArgs (CallInst *, unsigned &, unsigned &) const |
| Return true if the pointer arguments to CI should be aligned by aligning the object whose address is being passed. More... | |
| virtual bool | shouldSignExtendTypeInLibCall (EVT Type, bool IsSigned) const |
| Returns true if arguments should be sign-extended in lib calls. More... | |
| virtual bool | shouldNormalizeToSelectSequence (LLVMContext &Context, EVT VT) const |
| Returns true if we should normalize select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely that it saves us from materializing N0 and N1 in an integer register. More... | |
| virtual bool | GetAddrModeArguments (IntrinsicInst *, SmallVectorImpl< Value * > &, Type *&, unsigned AddrSpace=0) const |
| CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the address. More... | |
| virtual bool | isProfitableToHoist (Instruction *I) const |
| bool | isExtFree (const Instruction *I) const |
Return true if the extension represented by I is free. More... | |
| virtual bool | hasPairedLoad (Type *, unsigned &) const |
| Return true if the target supplies and combines to a paired load two loaded values of type LoadedType next to each other in memory. More... | |
| virtual bool | hasPairedLoad (EVT, unsigned &) const |
| virtual unsigned | getMaxSupportedInterleaveFactor () const |
| Get the maximum supported factor for interleaved memory accesses. More... | |
| virtual bool | lowerInterleavedLoad (LoadInst *LI, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const |
| Lower an interleaved load to target specific intrinsics. More... | |
| virtual bool | lowerInterleavedStore (StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const |
| Lower an interleaved store to target specific intrinsics. More... | |
| virtual bool | isFPExtFree (EVT VT) const |
| Return true if an fpext operation is free (for instance, because single-precision floating-point numbers are implicitly extended to double-precision). More... | |
| virtual bool | isFNegFree (EVT VT) const |
| Return true if an fneg operation is free to the point where it is never worthwhile to replace it with a bitwise operation. More... | |
| virtual bool | isFAbsFree (EVT VT) const |
| Return true if an fabs operation is free to the point where it is never worthwhile to replace it with a bitwise operation. More... | |
| void | setLibcallName (RTLIB::Libcall Call, const char *Name) |
| Rename the default libcall routine name for the specified libcall. More... | |
| const char * | getLibcallName (RTLIB::Libcall Call) const |
| Get the libcall routine name for the specified libcall. More... | |
| void | setCmpLibcallCC (RTLIB::Libcall Call, ISD::CondCode CC) |
| Override the default CondCode to be used to test the result of the comparison libcall against zero. More... | |
| ISD::CondCode | getCmpLibcallCC (RTLIB::Libcall Call) const |
| Get the CondCode that's to be used to test the result of the comparison libcall against zero. More... | |
| void | setLibcallCallingConv (RTLIB::Libcall Call, CallingConv::ID CC) |
| Set the CallingConv that should be used for the specified libcall. More... | |
| CallingConv::ID | getLibcallCallingConv (RTLIB::Libcall Call) const |
| Get the CallingConv that should be used for the specified libcall. More... | |
| int | InstructionOpcodeToISD (unsigned Opcode) const |
| Get the ISD node that corresponds to the Instruction class opcode. More... | |
| std::pair< unsigned, MVT > | getTypeLegalizationCost (const DataLayout &DL, Type *Ty) const |
| Estimate the cost of type-legalization and the legalized type. More... | |
| virtual bool | hasLoadLinkedStoreConditional () const |
| True if AtomicExpandPass should use emitLoadLinked/emitStoreConditional and expand AtomicCmpXchgInst. More... | |
| virtual Value * | emitLoadLinked (IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const |
| Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type. More... | |
| virtual Value * | emitStoreConditional (IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const |
| Perform a store-conditional operation to Addr. More... | |
| virtual Instruction * | emitLeadingFence (IRBuilder<> &Builder, AtomicOrdering Ord, bool IsStore, bool IsLoad) const |
| Inserts in the IR a target-specific intrinsic specifying a fence. More... | |
| virtual Instruction * | emitTrailingFence (IRBuilder<> &Builder, AtomicOrdering Ord, bool IsStore, bool IsLoad) const |
Protected Member Functions | |
| std::pair< const TargetRegisterClass *, uint8_t > | findRepresentativeClass (const TargetRegisterInfo *TRI, MVT VT) const override |
| Return the largest legal super-reg register class of the register class for the specified type and its associated "cost". More... | |
Protected Member Functions inherited from llvm::TargetLoweringBase | |
| void | initActions () |
| Initialize all of the actions to default values. More... | |
| void | setBooleanContents (BooleanContent Ty) |
| Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type. More... | |
| void | setBooleanContents (BooleanContent IntTy, BooleanContent FloatTy) |
| Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type. More... | |
| void | setBooleanVectorContents (BooleanContent Ty) |
| Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider type. More... | |
| void | setSchedulingPreference (Sched::Preference Pref) |
| Specify the target scheduling preference. More... | |
| void | setUseUnderscoreSetJmp (bool Val) |
| Indicate whether this target prefers to use _setjmp to implement llvm.setjmp or the version without _. More... | |
| void | setUseUnderscoreLongJmp (bool Val) |
| Indicate whether this target prefers to use _longjmp to implement llvm.longjmp or the version without _. More... | |
| void | setMinimumJumpTableEntries (int Val) |
| Indicate the number of blocks to generate jump tables rather than if sequence. More... | |
| void | setStackPointerRegisterToSaveRestore (unsigned R) |
| If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore. More... | |
| void | setExceptionPointerRegister (unsigned R) |
| If set to a physical register, this sets the register that receives the exception address on entry to a landing pad. More... | |
| void | setExceptionSelectorRegister (unsigned R) |
| If set to a physical register, this sets the register that receives the exception typeid on entry to a landing pad. More... | |
| void | setSelectIsExpensive (bool isExpensive=true) |
| Tells the code generator not to expand operations into sequences that use the select operations if possible. More... | |
| void | setHasMultipleConditionRegisters (bool hasManyRegs=true) |
| Tells the code generator that the target has multiple (allocatable) condition registers that can be used to store the results of comparisons for use by selects and conditional branches. More... | |
| void | setHasExtractBitsInsn (bool hasExtractInsn=true) |
| Tells the code generator that the target has BitExtract instructions. More... | |
| void | setJumpIsExpensive (bool isExpensive=true) |
| Tells the code generator not to expand logic operations on comparison predicates into separate sequences that increase the amount of flow control. More... | |
| void | setIntDivIsCheap (bool isCheap=true) |
| Tells the code generator that integer divide is expensive, and if possible, should be replaced by an alternate sequence of instructions not containing an integer divide. More... | |
| void | setFsqrtIsCheap (bool isCheap=true) |
| Tells the code generator that fsqrt is cheap, and should not be replaced with an alternative sequence of instructions. More... | |
| void | setHasFloatingPointExceptions (bool FPExceptions=true) |
| Tells the code generator that this target supports floating point exceptions and cares about preserving floating point exception behavior. More... | |
| void | addBypassSlowDiv (unsigned int SlowBitWidth, unsigned int FastBitWidth) |
| Tells the code generator which bitwidths to bypass. More... | |
| void | setPow2SDivIsCheap (bool isCheap=true) |
| Tells the code generator that it shouldn't generate sra/srl/add/sra for a signed divide by power of two; let the target handle it. More... | |
| void | addRegisterClass (MVT VT, const TargetRegisterClass *RC) |
| Add the specified register class as an available regclass for the specified value type. More... | |
| void | clearRegisterClasses () |
| Remove all register classes. More... | |
| void | clearOperationActions () |
| Remove all operation actions. More... | |
| void | computeRegisterProperties (const TargetRegisterInfo *TRI) |
| Once all of the register classes are added, this allows us to compute derived properties we expose. More... | |
| void | setOperationAction (unsigned Op, MVT VT, LegalizeAction Action) |
| Indicate that the specified operation does not work with the specified type and indicate what to do about it. More... | |
| void | setLoadExtAction (unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action) |
| Indicate that the specified load with extension does not work with the specified type and indicate what to do about it. More... | |
| void | setTruncStoreAction (MVT ValVT, MVT MemVT, LegalizeAction Action) |
| Indicate that the specified truncating store does not work with the specified type and indicate what to do about it. More... | |
| void | setIndexedLoadAction (unsigned IdxMode, MVT VT, LegalizeAction Action) |
| Indicate that the specified indexed load does or does not work with the specified type and indicate what to do abort it. More... | |
| void | setIndexedStoreAction (unsigned IdxMode, MVT VT, LegalizeAction Action) |
| Indicate that the specified indexed store does or does not work with the specified type and indicate what to do about it. More... | |
| void | setCondCodeAction (ISD::CondCode CC, MVT VT, LegalizeAction Action) |
| Indicate that the specified condition code is or isn't supported on the target and indicate what to do about it. More... | |
| void | AddPromotedToType (unsigned Opc, MVT OrigVT, MVT DestVT) |
| If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/fp until it can find one that works. More... | |
| void | setTargetDAGCombine (ISD::NodeType NT) |
| Targets should invoke this method for each target independent node that they want to provide a custom DAG combiner for by implementing the PerformDAGCombine virtual method. More... | |
| void | setJumpBufSize (unsigned Size) |
| Set the target's required jmp_buf buffer size (in bytes); default is 200. More... | |
| void | setJumpBufAlignment (unsigned Align) |
| Set the target's required jmp_buf buffer alignment (in bytes); default is 0. More... | |
| void | setMinFunctionAlignment (unsigned Align) |
| Set the target's minimum function alignment (in log2(bytes)) More... | |
| void | setPrefFunctionAlignment (unsigned Align) |
| Set the target's preferred function alignment. More... | |
| void | setPrefLoopAlignment (unsigned Align) |
| Set the target's preferred loop alignment. More... | |
| void | setMinStackArgumentAlignment (unsigned Align) |
| Set the minimum stack alignment of an argument (in log2(bytes)). More... | |
| void | setInsertFencesForAtomic (bool fence) |
| Set if the DAG builder should automatically insert fences and reduce the order of atomic memory operations to Monotonic. More... | |
| virtual bool | isExtFreeImpl (const Instruction *I) const |
Return true if the extension represented by I is free. More... | |
| bool | isLegalRC (const TargetRegisterClass *RC) const |
| Return true if the value types that can be represented by the specified register class are all legal. More... | |
| MachineBasicBlock * | emitPatchPoint (MachineInstr *MI, MachineBasicBlock *MBB) const |
| Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that is recognized by PrologEpilogInserter. More... | |
Additional Inherited Members | |
Public Types inherited from llvm::TargetLowering | |
| enum | ConstraintType { C_Register, C_RegisterClass, C_Memory, C_Other, C_Unknown } |
| enum | ConstraintWeight { CW_Invalid = -1, CW_Okay = 0, CW_Good = 1, CW_Better = 2, CW_Best = 3, CW_SpecificReg = CW_Okay, CW_Register = CW_Good, CW_Memory = CW_Better, CW_Constant = CW_Best, CW_Default = CW_Okay } |
| typedef std::vector< ArgListEntry > | ArgListTy |
| typedef std::vector < AsmOperandInfo > | AsmOperandInfoVector |
Public Types inherited from llvm::TargetLoweringBase | |
| enum | LegalizeAction { Legal, Promote, Expand, Custom } |
| This enum indicates whether operations are valid for a target, and if not, what action should be used to make them valid. More... | |
| enum | LegalizeTypeAction { TypeLegal, TypePromoteInteger, TypeExpandInteger, TypeSoftenFloat, TypeExpandFloat, TypeScalarizeVector, TypeSplitVector, TypeWidenVector, TypePromoteFloat } |
| This enum indicates whether a types are legal for a target, and if not, what action should be used to make them valid. More... | |
| enum | BooleanContent { UndefinedBooleanContent, ZeroOrOneBooleanContent, ZeroOrNegativeOneBooleanContent } |
| Enum that describes how the target represents true/false values. More... | |
| enum | SelectSupportKind { ScalarValSelect, ScalarCondVectorVal, VectorMaskSelect } |
| Enum that describes what type of support for selects the target has. More... | |
| enum | AtomicRMWExpansionKind { AtomicRMWExpansionKind::None, AtomicRMWExpansionKind::LLSC, AtomicRMWExpansionKind::CmpXChg } |
| Enum that specifies what a AtomicRMWInst is expanded to, if at all. More... | |
| typedef std::pair < LegalizeTypeAction, EVT > | LegalizeKind |
| LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it. More... | |
Static Public Member Functions inherited from llvm::TargetLoweringBase | |
| static ISD::NodeType | getExtendForContent (BooleanContent Content) |
Protected Attributes inherited from llvm::TargetLoweringBase | |
| unsigned | MaxStoresPerMemset |
| Specify maximum number of store instructions per memset call. More... | |
| unsigned | MaxStoresPerMemsetOptSize |
| Maximum number of stores operations that may be substituted for the call to memset, used for functions with OptSize attribute. More... | |
| unsigned | MaxStoresPerMemcpy |
| Specify maximum bytes of store instructions per memcpy call. More... | |
| unsigned | MaxStoresPerMemcpyOptSize |
| Maximum number of store operations that may be substituted for a call to memcpy, used for functions with OptSize attribute. More... | |
| unsigned | MaxStoresPerMemmove |
| Specify maximum bytes of store instructions per memmove call. More... | |
| unsigned | MaxStoresPerMemmoveOptSize |
| Maximum number of store instructions that may be substituted for a call to memmove, used for functions with OpSize attribute. More... | |
| bool | PredictableSelectIsExpensive |
| Tells the code generator that select is more expensive than a branch if the branch is usually predicted right. More... | |
| bool | MaskAndBranchFoldingIsLegal |
| MaskAndBranchFoldingIsLegal - Indicates if the target supports folding a mask of a single bit, a compare, and a branch into a single instruction. More... | |
| bool | EnableExtLdPromotion |
Definition at line 596 of file X86ISelLowering.h.
|
explicit |
Definition at line 74 of file X86ISelLowering.cpp.
References llvm::ISD::ADD, llvm::TargetLoweringBase::addBypassSlowDiv(), llvm::ISD::ADDC, llvm::ISD::ADDE, llvm::TargetLoweringBase::AddPromotedToType(), llvm::TargetLoweringBase::addRegisterClass(), llvm::ISD::ADJUST_TRAMPOLINE, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::lltok::APFloat, llvm::array_lengthof(), llvm::ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, llvm::ISD::ATOMIC_FENCE, llvm::ISD::ATOMIC_LOAD_SUB, llvm::ISD::ATOMIC_STORE, llvm::ISD::BITCAST, llvm::ISD::BlockAddress, llvm::ISD::BR_CC, llvm::ISD::BR_JT, llvm::ISD::BRCOND, llvm::ISD::BSWAP, llvm::ISD::BUILD_VECTOR, llvm::APFloat::changeSign(), llvm::TargetLoweringBase::computeRegisterProperties(), llvm::ISD::CONCAT_VECTORS, llvm::ISD::ConstantPool, llvm::APFloat::convert(), llvm::ISD::CTLZ, llvm::ISD::CTLZ_ZERO_UNDEF, llvm::ISD::CTPOP, llvm::ISD::CTTZ, llvm::ISD::CTTZ_ZERO_UNDEF, llvm::TargetLoweringBase::Custom, llvm::ISD::DEBUGTRAP, llvm::CodeGenOpt::Default, llvm::ISD::DYNAMIC_STACKALLOC, llvm::ISD::EH_LABEL, llvm::ISD::EH_RETURN, llvm::ISD::EH_SJLJ_LONGJMP, llvm::ISD::EH_SJLJ_SETJMP, llvm::TargetLoweringBase::EnableExtLdPromotion, llvm::TargetLoweringBase::Expand, llvm::ISD::ExternalSymbol, llvm::ISD::EXTLOAD, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::MVT::f80, llvm::ISD::FABS, llvm::ISD::FADD, llvm::ISD::FCEIL, llvm::ISD::FCOPYSIGN, llvm::ISD::FCOS, llvm::ISD::FDIV, llvm::ISD::FEXP, llvm::ISD::FEXP2, llvm::ISD::FFLOOR, llvm::ISD::FGETSIGN, llvm::ISD::FLOG, llvm::ISD::FLOG10, llvm::ISD::FLOG2, llvm::ISD::FLT_ROUNDS_, llvm::ISD::FMA, llvm::ISD::FMAXNUM, llvm::ISD::FMINNUM, llvm::ISD::FMUL, llvm::ISD::FNEARBYINT, llvm::ISD::FNEG, llvm::ISD::FP16_TO_FP, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::ISD::FP_ROUND_INREG, llvm::ISD::FP_TO_FP16, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::MVT::fp_vector_valuetypes(), llvm::ISD::FPOW, llvm::ISD::FPOWI, llvm::RTLIB::FPTOUINT_F32_I32, llvm::RTLIB::FPTOUINT_F32_I64, llvm::RTLIB::FPTOUINT_F64_I32, llvm::RTLIB::FPTOUINT_F64_I64, llvm::ISD::FRAME_TO_ARGS_OFFSET, llvm::ISD::FREM, llvm::ISD::FRINT, llvm::ISD::FSIN, llvm::ISD::FSINCOS, llvm::ISD::FSQRT, llvm::ISD::FSUB, llvm::ISD::FTRUNC, llvm::ISD::GC_TRANSITION_END, llvm::ISD::GC_TRANSITION_START, llvm::TargetMachine::getDataLayout(), llvm::TargetMachine::getOptLevel(), llvm::TargetLoweringBase::getPointerTy(), llvm::X86Subtarget::getRegisterInfo(), llvm::MVT::getSizeInBits(), llvm::X86RegisterInfo::getStackRegister(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::APFloat::getZero(), llvm::ISD::GlobalAddress, llvm::ISD::GlobalTLSAddress, llvm::X86Subtarget::hasAVX512(), llvm::X86Subtarget::hasBMI(), llvm::X86Subtarget::hasBWI(), llvm::X86Subtarget::hasCDI(), llvm::X86Subtarget::hasCmpxchg16b(), llvm::X86Subtarget::hasDQI(), llvm::X86Subtarget::hasF16C(), llvm::X86Subtarget::hasFMA(), llvm::X86Subtarget::hasFMA4(), llvm::X86Subtarget::hasFp256(), llvm::X86Subtarget::hasInt256(), llvm::X86Subtarget::hasLZCNT(), llvm::X86Subtarget::hasMMX(), llvm::X86Subtarget::hasMOVBE(), llvm::X86Subtarget::hasPOPCNT(), llvm::X86Subtarget::hasSinCos(), llvm::X86Subtarget::hasSlowDivide32(), llvm::X86Subtarget::hasSlowDivide64(), llvm::X86Subtarget::hasSSE1(), llvm::X86Subtarget::hasSSE2(), llvm::X86Subtarget::hasSSE3(), llvm::X86Subtarget::hasSSE41(), llvm::X86Subtarget::hasVLX(), llvm::MVT::i1, llvm::MVT::i128, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::Sched::ILP, llvm::ISD::INIT_TRAMPOLINE, llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::INSERT_VECTOR_ELT, llvm::MVT::integer_valuetypes(), llvm::MVT::integer_vector_valuetypes(), llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::MVT::is128BitVector(), llvm::MVT::is256BitVector(), llvm::MVT::is512BitVector(), llvm::X86Subtarget::is64Bit(), llvm::X86Subtarget::isAtom(), llvm::isPowerOf2_32(), llvm::X86Subtarget::isTargetCygMing(), llvm::X86Subtarget::isTargetDarwin(), llvm::X86Subtarget::isTargetELF(), isTargetFTOL(), llvm::X86Subtarget::isTargetKnownWindowsMSVC(), llvm::X86Subtarget::isTargetWin64(), llvm::X86Subtarget::isTargetWindowsGNU(), llvm::ISD::JumpTable, llvm::TargetLoweringBase::Legal, llvm::ISD::LOAD, llvm::TargetLoweringBase::MaxStoresPerMemcpy, llvm::TargetLoweringBase::MaxStoresPerMemcpyOptSize, llvm::TargetLoweringBase::MaxStoresPerMemmove, llvm::TargetLoweringBase::MaxStoresPerMemmoveOptSize, llvm::TargetLoweringBase::MaxStoresPerMemset, llvm::TargetLoweringBase::MaxStoresPerMemsetOptSize, llvm::ISD::MGATHER, llvm::ISD::MLOAD, llvm::ISD::MSCATTER, llvm::ISD::MSTORE, llvm::ISD::MUL, llvm::RTLIB::MUL_I64, llvm::ISD::MULHS, llvm::ISD::MULHU, llvm::TargetMachine::Options, llvm::ISD::OR, llvm::MVT::Other, llvm::TargetLoweringBase::PredictableSelectIsExpensive, llvm::ISD::PREFETCH, llvm::TargetLoweringBase::Promote, llvm::ISD::READCYCLECOUNTER, llvm::Sched::RegPressure, llvm::APFloat::rmNearestTiesToEven, llvm::ISD::ROTL, llvm::ISD::ROTR, llvm::ISD::SADDO, llvm::ISD::SCALAR_TO_VECTOR, llvm::ISD::SDIV, llvm::RTLIB::SDIV_I64, llvm::ISD::SDIVREM, llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::TargetLoweringBase::setBooleanContents(), llvm::TargetLoweringBase::setBooleanVectorContents(), llvm::ISD::SETCC, llvm::TargetLoweringBase::setCondCodeAction(), llvm::TargetLoweringBase::setExceptionPointerRegister(), llvm::TargetLoweringBase::setExceptionSelectorRegister(), llvm::TargetLoweringBase::setLibcallCallingConv(), llvm::TargetLoweringBase::setLibcallName(), llvm::TargetLoweringBase::setLoadExtAction(), llvm::ISD::SETOEQ, llvm::TargetLoweringBase::setOperationAction(), llvm::TargetLoweringBase::setPrefFunctionAlignment(), llvm::TargetLoweringBase::setPrefLoopAlignment(), llvm::TargetLoweringBase::setSchedulingPreference(), llvm::TargetLoweringBase::setStackPointerRegisterToSaveRestore(), llvm::TargetLoweringBase::setTargetDAGCombine(), llvm::TargetLoweringBase::setTruncStoreAction(), llvm::ISD::SETUNE, llvm::TargetLoweringBase::setUseUnderscoreLongJmp(), llvm::TargetLoweringBase::setUseUnderscoreSetJmp(), llvm::ISD::SEXTLOAD, llvm::ISD::SHL, llvm::RTLIB::SHL_I128, llvm::ISD::SHL_PARTS, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SIGN_EXTEND_VECTOR_INREG, llvm::RTLIB::SINCOS_F32, llvm::RTLIB::SINCOS_F64, llvm::ISD::SINT_TO_FP, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::SMUL_LOHI, llvm::ISD::SMULO, llvm::ISD::SRA, llvm::RTLIB::SRA_I128, llvm::ISD::SRA_PARTS, llvm::ISD::SREM, llvm::RTLIB::SREM_I64, llvm::ISD::SRL, llvm::RTLIB::SRL_I128, llvm::ISD::SRL_PARTS, llvm::ISD::SSUBO, llvm::ISD::STACKRESTORE, llvm::ISD::STACKSAVE, llvm::ISD::STORE, llvm::ISD::SUB, llvm::ISD::SUBC, llvm::ISD::SUBE, llvm::ISD::TRAP, llvm::ISD::TRUNCATE, llvm::ISD::UADDO, llvm::ISD::UDIV, llvm::RTLIB::UDIV_I64, llvm::ISD::UDIVREM, llvm::ISD::UINT_TO_FP, llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::ISD::UMUL_LOHI, llvm::ISD::UMULO, llvm::ISD::UNDEF, llvm::TargetOptions::UnsafeFPMath, llvm::ISD::UREM, llvm::RTLIB::UREM_I64, llvm::X86Subtarget::useSoftFloat(), llvm::ISD::USUBO, llvm::MVT::v16f32, llvm::MVT::v16i1, llvm::MVT::v16i16, llvm::MVT::v16i32, llvm::MVT::v16i8, llvm::MVT::v1i64, llvm::MVT::v2f32, llvm::MVT::v2f64, llvm::MVT::v2i1, llvm::MVT::v2i16, llvm::MVT::v2i32, llvm::MVT::v2i64, llvm::MVT::v2i8, llvm::MVT::v32i1, llvm::MVT::v32i16, llvm::MVT::v32i8, llvm::MVT::v4f32, llvm::MVT::v4f64, llvm::MVT::v4i1, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v4i64, llvm::MVT::v4i8, llvm::MVT::v64i1, llvm::MVT::v64i8, llvm::MVT::v8f32, llvm::MVT::v8f64, llvm::MVT::v8i1, llvm::MVT::v8i16, llvm::MVT::v8i32, llvm::MVT::v8i64, llvm::MVT::v8i8, llvm::ISD::VAARG, llvm::ISD::VACOPY, llvm::ISD::VAEND, llvm::ISD::VASTART, llvm::ISD::VECTOR_SHUFFLE, llvm::MVT::vector_valuetypes(), llvm::verifyIntrinsicTables(), llvm::ISD::VSELECT, llvm::CallingConv::X86_StdCall, llvm::MVT::x86mmx, llvm::APFloat::x87DoubleExtended, llvm::ISD::XOR, llvm::ISD::ZERO_EXTEND, llvm::TargetLoweringBase::ZeroOrNegativeOneBooleanContent, llvm::TargetLoweringBase::ZeroOrOneBooleanContent, and llvm::ISD::ZEXTLOAD.
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Returns true if the target allows unaligned memory accesses of the specified type.
Returns whether it is "fast" in the last argument.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 1859 of file X86ISelLowering.cpp.
References llvm::X86Subtarget::isUnalignedMemAccessFast().
Return true if a truncation from Ty1 to Ty2 is permitted when deciding whether a call is in tail position.
Typically this means that both results would be assigned to the same register or stack slot, but it could mean the target performs adequate checks of its own before proceeding with the tail call.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 19123 of file X86ISelLowering.cpp.
References llvm::EVT::getEVT(), llvm::Type::getPrimitiveSizeInBits(), llvm::Type::isIntegerTy(), and llvm::TargetLoweringBase::isTypeLegal().
| SDValue X86TargetLowering::BuildFILD | ( | SDValue | Op, |
| EVT | SrcVT, | ||
| SDValue | Chain, | ||
| SDValue | StackSlot, | ||
| SelectionDAG & | DAG | ||
| ) | const |
Definition at line 11840 of file X86ISelLowering.cpp.
References llvm::lltok::APFloat, llvm::EVT::bitsGT(), llvm::EVT::bitsLT(), llvm::BitsToDouble(), llvm::MachineFrameInfo::CreateStackObject(), llvm::DL, llvm::dyn_cast(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f64, llvm::ISD::FADD, llvm::X86ISD::FHADD, llvm::X86ISD::FILD, llvm::X86ISD::FILD_FLAG, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::X86ISD::FST, llvm::ISD::FSUB, llvm::ConstantFP::get(), llvm::ConstantVector::get(), llvm::ConstantDataVector::get(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstantFP(), llvm::MachinePointerInfo::getConstantPool(), llvm::SelectionDAG::getConstantPool(), llvm::SelectionDAG::getContext(), llvm::MachineFunction::getDataLayout(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getEntryNode(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::FrameIndexSDNode::getIndex(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::TargetLoweringBase::getPointerTy(), getShuffleVectorZeroOrUndef(), llvm::EVT::getSizeInBits(), getTargetShuffleNode(), getUnpackl(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getValueType(), llvm::SelectionDAG::getVTList(), llvm::MVT::Glue, llvm::X86Subtarget::hasSSE3(), llvm::APFloat::IEEEdouble, isScalarFPTypeInSSEReg(), llvm::SPII::Load, llvm::MachineMemOperand::MOLoad, llvm::MachineMemOperand::MOStore, llvm::ISD::OR, llvm::APIntOps::Or(), llvm::MVT::Other, llvm::X86ISD::PSHUFD, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::ISD::SCALAR_TO_VECTOR, llvm::MVT::v2f64, llvm::MVT::v2i64, and llvm::MVT::v4i32.
Referenced by PerformSINT_TO_FPCombine().
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Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets.
Reimplemented from llvm::TargetLowering.
Definition at line 20694 of file X86ISelLowering.cpp.
References llvm::X86ISD::ADC, llvm::X86ISD::ADD, llvm::X86ISD::AND, llvm::ISD::BUILTIN_OP_END, llvm::X86ISD::DEC, llvm::APInt::getBitWidth(), llvm::APInt::getHighBitsSet(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getResNo(), llvm::X86ISD::INC, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm_unreachable, llvm::X86ISD::OR, llvm::X86ISD::SBB, llvm::X86ISD::SETCC, llvm::X86ISD::SMUL, llvm::X86ISD::SUB, llvm::X86ISD::UMUL, and llvm::X86ISD::XOR.
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Determine the number of bits in the operation that are sign bits.
Reimplemented from llvm::TargetLowering.
Definition at line 20761 of file X86ISelLowering.cpp.
References llvm::SDValue::getOpcode(), llvm::EVT::getScalarType(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), and llvm::X86ISD::SETCC_CARRY.
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This method returns a target specific FastISel object, or null if the target does not support "fast" ISel.
Reimplemented from llvm::TargetLowering.
Definition at line 3649 of file X86ISelLowering.cpp.
References llvm::X86::createFastISel().
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This method should be implemented by targets that mark instructions with the 'usesCustomInserter' flag.
These instructions are special in various ways, which require special support to insert. The specified MachineInstr is created but not inserted into any basic blocks, and this method is called to expand it into a sequence of instructions, potentially also creating new basic blocks and control flow. As long as the returned basic block is different (i.e., we created a new one), the custom inserter is free to modify the rest of MBB.
Reimplemented from llvm::TargetLowering.
Definition at line 20468 of file X86ISelLowering.cpp.
References llvm::addFrameReference(), llvm::addFullAddress(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::X86AddressMode::Base, llvm::X86AddressMode::BaseType, llvm::BuildMI(), llvm::MachineFrameInfo::CreateStackObject(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::X86AddressMode::Disp, EmitMonitor(), llvm::TargetLoweringBase::emitPatchPoint(), EmitPCMPSTRI(), EmitPCMPSTRM(), EmitXBegin(), llvm::MachineInstr::eraseFromParent(), llvm::X86ISD::FNSTCW16m, llvm::X86AddressMode::FrameIndex, llvm::X86AddressMode::FrameIndexBase, llvm::MCInstrInfo::get(), llvm::MachineInstr::getDebugLoc(), llvm::MachineFunction::getFrameInfo(), llvm::MachineOperand::getGlobal(), llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::X86Subtarget::getInstrInfo(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::X86AddressMode::GV, llvm::X86Subtarget::hasSSE42(), llvm::X86AddressMode::IndexReg, llvm::MachineOperand::isGlobal(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), llvm_unreachable, llvm::TargetOpcode::PATCHPOINT, llvm::X86AddressMode::Reg, llvm::X86AddressMode::RegBase, llvm::X86AddressMode::Scale, llvm::TargetOpcode::STACKMAP, llvm::TargetOpcode::STATEPOINT, llvm::X86ISD::VAARG_64, llvm::X86ISD::VASTART_SAVE_XMM_REGS, and llvm::X86ISD::WIN_ALLOCA.
This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to.
This is useful for turning simple inline asms into LLVM intrinsics, which gives the compiler more information about the behavior of the code.
Reimplemented from llvm::TargetLowering.
Definition at line 25570 of file X86ISelLowering.cpp.
References llvm::array_pod_sort(), llvm::SmallVectorTemplateCommon< T >::begin(), llvm::SmallVectorImpl< T >::clear(), clobbersFlagRegisters(), llvm::dyn_cast(), llvm::SmallVectorTemplateCommon< T >::end(), llvm::InlineAsm::getAsmString(), llvm::IntegerType::getBitWidth(), llvm::CallInst::getCalledValue(), llvm::InlineAsm::getConstraintString(), llvm::Value::getType(), llvm::Type::isIntegerTy(), llvm::IntrinsicLowering::LowerToByteSwap(), matchAsm(), llvm::InlineAsm::ParseConstraints(), llvm::SmallVectorTemplateCommon< T >::size(), and llvm::SplitString().
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Return the largest legal super-reg register class of the register class for the specified type and its associated "cost".
findRepresentativeClass - Return the largest legal super-reg register class of the register class for the specified type and its associated "cost".
Reimplemented from llvm::TargetLoweringBase.
Definition at line 1923 of file X86ISelLowering.cpp.
References llvm::MVT::f32, llvm::MVT::f64, llvm::TargetLoweringBase::findRepresentativeClass(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::X86Subtarget::is64Bit(), llvm::MSP430ISD::RRC, llvm::MVT::SimpleTy, llvm::MVT::v16i8, llvm::MVT::v2f64, llvm::MVT::v2i64, llvm::MVT::v32i8, llvm::MVT::v4f32, llvm::MVT::v4f64, llvm::MVT::v4i32, llvm::MVT::v4i64, llvm::MVT::v8f32, llvm::MVT::v8i16, llvm::MVT::v8i32, and llvm::MVT::x86mmx.
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Return the desired alignment for ByVal aggregate function arguments in the caller parameter area.
For X86, aggregates that contains are placed at 16-byte boundaries while the rest are at 4-byte boundaries.
For X86, aggregates that contain SSE vectors are placed at 16-byte boundaries while the rest are at 4-byte boundaries.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 1787 of file X86ISelLowering.cpp.
References Align(), llvm::DataLayout::getABITypeAlignment(), getMaxByValAlign(), llvm::X86Subtarget::hasSSE1(), and llvm::X86Subtarget::is64Bit().
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Intel processors have a unified instruction and data cache.
Reimplemented from llvm::TargetLowering.
Definition at line 875 of file X86ISelLowering.h.
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getConstraintType - Given a constraint letter, return the type of constraint it is for this target.
Reimplemented from llvm::TargetLowering.
Definition at line 25649 of file X86ISelLowering.cpp.
References llvm::TargetLowering::C_Other, llvm::TargetLowering::C_Register, llvm::TargetLowering::C_RegisterClass, llvm::TargetLowering::getConstraintType(), and llvm::StringRef::size().
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Reimplemented from llvm::TargetLowering.
Definition at line 735 of file X86ISelLowering.h.
References llvm::InlineAsm::Constraint_i, llvm::InlineAsm::Constraint_o, llvm::InlineAsm::Constraint_v, llvm::InlineAsm::Constraint_X, and llvm::TargetLowering::getInlineAsmMemConstraint().
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Return the entry encoding for a jump table in the current function.
The returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
Reimplemented from llvm::TargetLowering.
Definition at line 1871 of file X86ISelLowering.cpp.
References llvm::MachineJumpTableInfo::EK_Custom32, llvm::TargetLowering::getJumpTableEncoding(), llvm::TargetLoweringBase::getTargetMachine(), llvm::X86Subtarget::isPICStyleGOT(), and llvm::Reloc::PIC_.
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Returns the target specific optimal type for load and store operations as a result of memset, memcpy, and memmove lowering.
If DstAlign is zero that means it's safe to destination alignment can satisfy any constraint. Similarly if SrcAlign is zero it means there isn't a need to check it against alignment requirement, probably because the source does not need to be loaded. If 'IsMemset' is true, that means it's expanding a memset. If 'ZeroMemset' is true, that means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it does not need to be loaded. It returns EVT::Other if the type should be determined using generic target-independent logic.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 1815 of file X86ISelLowering.cpp.
References F(), llvm::MVT::f64, llvm::MachineFunction::getFunction(), llvm::Function::hasFnAttribute(), llvm::X86Subtarget::hasFp256(), llvm::X86Subtarget::hasInt256(), llvm::X86Subtarget::hasSSE1(), llvm::X86Subtarget::hasSSE2(), llvm::MVT::i32, llvm::MVT::i64, llvm::X86Subtarget::is64Bit(), llvm::X86Subtarget::isUnalignedMemAccessFast(), llvm::Attribute::NoImplicitFloat, llvm::MVT::v4f32, llvm::MVT::v4i32, llvm::MVT::v8f32, and llvm::MVT::v8i32.
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Returns relocation base for the given PIC jumptable.
Reimplemented from llvm::TargetLowering.
Definition at line 1899 of file X86ISelLowering.cpp.
References llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getPointerTy(), llvm::X86ISD::GlobalBaseReg, and llvm::X86Subtarget::is64Bit().
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This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase, but as an MCExpr.
Reimplemented from llvm::TargetLowering.
Definition at line 1912 of file X86ISelLowering.cpp.
References llvm::MCSymbolRefExpr::create(), llvm::MachineFunction::getPICBaseSymbol(), llvm::TargetLowering::getPICJumpTableRelocBaseExpr(), and llvm::X86Subtarget::isPICStyleRIPRel().
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Customize the preferred legalization strategy for certain types.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 1705 of file X86ISelLowering.cpp.
References ExperimentalVectorWideningLegalization, llvm::TargetLoweringBase::getPreferredVectorAction(), llvm::EVT::getSimpleVT(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::MVT::i1, and llvm::TargetLoweringBase::TypeWidenVector.
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Given a physical register constraint (e.g.
{edx}), return the register number and the register class for the register. This should only be used for C_Register constraints. On error, this returns a register number of 0.
Reimplemented from llvm::TargetLowering.
Definition at line 25980 of file X86ISelLowering.cpp.
References llvm::Class, llvm::StringRef::equals_lower(), llvm::MVT::f64, llvm::TargetLowering::getRegForInlineAsmConstraint(), llvm::MVT::getSizeInBits(), llvm::getX86SubSuperRegisterOrZero(), llvm::X86Subtarget::hasMMX(), llvm::X86Subtarget::hasSSE1(), llvm::X86Subtarget::hasSSE2(), llvm::MVT::i1, llvm::MVT::i64, llvm::MVT::i8, if(), llvm::X86Subtarget::is64Bit(), isScalarFPTypeInSSEReg(), llvm::MVT::Other, llvm::MVT::SimpleTy, llvm::StringRef::size(), llvm::MVT::v16f32, llvm::MVT::v16i16, llvm::MVT::v16i32, llvm::MVT::v16i8, llvm::MVT::v2f64, llvm::MVT::v2i64, llvm::MVT::v32i8, llvm::MVT::v4f32, llvm::MVT::v4f64, llvm::MVT::v4i32, llvm::MVT::v4i64, llvm::MVT::v8f32, llvm::MVT::v8f64, llvm::MVT::v8i16, llvm::MVT::v8i32, and llvm::MVT::v8i64.
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Return the register ID of the name passed in.
Used by named register global variables extension. There is no target-independent behaviour so the default action is to bail.
Reimplemented from llvm::TargetLowering.
Definition at line 16294 of file X86ISelLowering.cpp.
References llvm::StringSwitch< T, R >::Case(), llvm::StringSwitch< T, R >::Default(), llvm::X86Subtarget::getFrameLowering(), llvm::SelectionDAG::getMachineFunction(), llvm::X86RegisterInfo::getPtrSizedFrameRegister(), llvm::X86Subtarget::getRegisterInfo(), llvm::TargetFrameLowering::hasFP(), and llvm::report_fatal_error().
| SDValue X86TargetLowering::getReturnAddressFrameIndex | ( | SelectionDAG & | DAG | ) | const |
Definition at line 3727 of file X86ISelLowering.cpp.
References llvm::MachineFrameInfo::CreateFixedObject(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::TargetLoweringBase::getPointerTy(), llvm::X86MachineFunctionInfo::getRAIndex(), llvm::X86Subtarget::getRegisterInfo(), llvm::X86RegisterInfo::getSlotSize(), and llvm::X86MachineFunctionInfo::setRAIndex().
Referenced by LowerINTRINSIC_W_CHAIN().
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EVT is not used in-tree, but is used by out-of-tree target.
A documentation for this function would be nice...
Reimplemented from llvm::TargetLoweringBase.
Definition at line 604 of file X86ISelLowering.h.
References llvm::MVT::i8.
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Return the cost of the scaling factor used in the addressing mode represented by AM for this target, for a load/store of the specified type.
If the AM is supported, the return value must be >= 0. If the AM is not supported, it returns a negative value.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 26190 of file X86ISelLowering.cpp.
References isLegalAddressingMode(), and llvm::TargetLoweringBase::AddrMode::Scale.
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Return the value type to use for ISD::SETCC.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 1714 of file X86ISelLowering.cpp.
References llvm::EVT::changeVectorElementTypeToInteger(), llvm::MVT::f32, llvm::MVT::f64, llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::X86Subtarget::hasAVX512(), llvm::X86Subtarget::hasBWI(), llvm::X86Subtarget::hasVLX(), llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::EVT::is128BitVector(), llvm::EVT::is256BitVector(), llvm::EVT::is512BitVector(), llvm::EVT::isVector(), llvm::MVT::v16i1, llvm::MVT::v2i1, llvm::MVT::v32i1, llvm::MVT::v4i1, llvm::MVT::v64i1, and llvm::MVT::v8i1.
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Examine constraint string and operand type and determine a weight value.
Examine constraint type and operand type and determine a weight value.
The operand object must already have been set up with the operand type.
This object must already have been set up with the operand type and the current alternative constraint selected.
Reimplemented from llvm::TargetLowering.
Definition at line 25693 of file X86ISelLowering.cpp.
References llvm::TargetLowering::AsmOperandInfo::CallOperandVal, llvm::TargetLowering::CW_Constant, llvm::TargetLowering::CW_Default, llvm::TargetLowering::CW_Invalid, llvm::TargetLowering::CW_Register, llvm::TargetLowering::CW_SpecificReg, llvm::Type::getPrimitiveSizeInBits(), llvm::ConstantSDNode::getSExtValue(), llvm::TargetLowering::getSingleConstraintMatchWeight(), llvm::Value::getType(), llvm::ConstantSDNode::getZExtValue(), llvm::X86Subtarget::hasFp256(), llvm::X86Subtarget::hasMMX(), llvm::X86Subtarget::hasSSE1(), llvm::Type::isFloatingPointTy(), llvm::Type::isIntegerTy(), and llvm::Type::isX86_MMXTy().
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Return true if the target stores stack protector cookies at a fixed offset in some non-standard address space, and populates the address space and offset as appropriate.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 1947 of file X86ISelLowering.cpp.
References llvm::TargetMachine::getCodeModel(), llvm::TargetLoweringBase::getTargetMachine(), llvm::X86Subtarget::is64Bit(), llvm::X86Subtarget::isTargetLinux(), and llvm::CodeModel::Kernel.
This method returns the name of a target specific DAG node.
Reimplemented from llvm::TargetLowering.
Definition at line 18822 of file X86ISelLowering.cpp.
References llvm::X86ISD::ABS, llvm::X86ISD::ADC, llvm::X86ISD::ADD, llvm::X86ISD::ADDS, llvm::X86ISD::ADDSUB, llvm::X86ISD::ADDUS, llvm::X86ISD::AND, llvm::X86ISD::ANDNP, llvm::X86ISD::AVG, llvm::X86ISD::BEXTR, llvm::X86ISD::BLENDI, llvm::X86ISD::BRCOND, llvm::X86ISD::BSF, llvm::X86ISD::BSR, llvm::X86ISD::BT, llvm::X86ISD::CALL, llvm::X86ISD::CMOV, llvm::X86ISD::CMP, llvm::X86ISD::CMPM, llvm::X86ISD::CMPM_RND, llvm::X86ISD::CMPMU, llvm::X86ISD::CMPP, llvm::X86ISD::COMI, llvm::X86ISD::COMPRESS, llvm::X86ISD::CVTDQ2PD, llvm::X86ISD::CVTUDQ2PD, llvm::X86ISD::DEC, llvm::X86ISD::EH_RETURN, llvm::X86ISD::EH_SJLJ_LONGJMP, llvm::X86ISD::EH_SJLJ_SETJMP, llvm::X86ISD::EXP2, llvm::X86ISD::EXPAND, llvm::X86ISD::EXTRQI, llvm::X86ISD::FADD_RND, llvm::X86ISD::FAND, llvm::X86ISD::FANDN, llvm::X86ISD::FDIV_RND, llvm::X86ISD::FGETEXP_RND, llvm::X86ISD::FGETSIGNx86, llvm::X86ISD::FHADD, llvm::X86ISD::FHSUB, llvm::X86ISD::FILD_FLAG, llvm::X86ISD::FIRST_NUMBER, llvm::X86ISD::FLD, llvm::X86ISD::FMADD, llvm::X86ISD::FMADD_RND, llvm::X86ISD::FMADDSUB, llvm::X86ISD::FMADDSUB_RND, llvm::X86ISD::FMAX, llvm::X86ISD::FMAX_RND, llvm::X86ISD::FMAXC, llvm::X86ISD::FMIN, llvm::X86ISD::FMIN_RND, llvm::X86ISD::FMINC, llvm::X86ISD::FMSUB, llvm::X86ISD::FMSUB_RND, llvm::X86ISD::FMSUBADD, llvm::X86ISD::FMSUBADD_RND, llvm::X86ISD::FMUL_RND, llvm::X86ISD::FNMADD, llvm::X86ISD::FNMADD_RND, llvm::X86ISD::FNMSUB, llvm::X86ISD::FNMSUB_RND, llvm::X86ISD::FNSTCW16m, llvm::X86ISD::FNSTSW16r, llvm::X86ISD::FOR, llvm::X86ISD::FP_TO_INT16_IN_MEM, llvm::X86ISD::FP_TO_INT32_IN_MEM, llvm::X86ISD::FP_TO_INT64_IN_MEM, llvm::X86ISD::FP_TO_SINT_RND, llvm::X86ISD::FP_TO_UINT_RND, llvm::X86ISD::FRCP, llvm::X86ISD::FRSQRT, llvm::X86ISD::FSETCC, llvm::X86ISD::FSQRT_RND, llvm::X86ISD::FST, llvm::X86ISD::FSUB_RND, llvm::X86ISD::FXOR, llvm::X86ISD::GlobalBaseReg, llvm::X86ISD::HADD, llvm::X86ISD::HSUB, llvm::X86ISD::INC, llvm::X86ISD::INSERTPS, llvm::X86ISD::INSERTQI, llvm::X86ISD::KORTEST, llvm::X86ISD::LCMPXCHG16_DAG, llvm::X86ISD::LCMPXCHG8_DAG, llvm::X86ISD::LCMPXCHG_DAG, llvm::X86ISD::LFENCE, llvm::X86ISD::MEMBARRIER, llvm::X86ISD::MFENCE, llvm::X86ISD::MMX_MOVD2W, llvm::X86ISD::MMX_MOVW2D, llvm::X86ISD::MMX_PINSRW, llvm::X86ISD::MOVDDUP, llvm::X86ISD::MOVDQ2Q, llvm::X86ISD::MOVHLPS, llvm::X86ISD::MOVLHPD, llvm::X86ISD::MOVLHPS, llvm::X86ISD::MOVLPD, llvm::X86ISD::MOVLPS, llvm::X86ISD::MOVSD, llvm::X86ISD::MOVSHDUP, llvm::X86ISD::MOVSLDUP, llvm::X86ISD::MOVSS, llvm::X86ISD::MUL_IMM, llvm::X86ISD::MULHRS, llvm::X86ISD::OR, llvm::X86ISD::PACKSS, llvm::X86ISD::PACKUS, llvm::X86ISD::PALIGNR, llvm::X86ISD::PCMPEQ, llvm::X86ISD::PCMPEQM, llvm::X86ISD::PCMPESTRI, llvm::X86ISD::PCMPGT, llvm::X86ISD::PCMPGTM, llvm::X86ISD::PCMPISTRI, llvm::X86ISD::PEXTRB, llvm::X86ISD::PEXTRW, llvm::X86ISD::PINSRB, llvm::X86ISD::PINSRW, llvm::X86ISD::PMULDQ, llvm::X86ISD::PMULUDQ, llvm::X86ISD::PSADBW, llvm::X86ISD::PSHUFB, llvm::X86ISD::PSHUFD, llvm::X86ISD::PSHUFHW, llvm::X86ISD::PSHUFLW, llvm::X86ISD::PSIGN, llvm::X86ISD::PTEST, llvm::X86ISD::RCP28, llvm::X86ISD::RDPMC_DAG, llvm::X86ISD::RDRAND, llvm::X86ISD::RDSEED, llvm::X86ISD::RDTSC_DAG, llvm::X86ISD::RDTSCP_DAG, llvm::X86ISD::REP_MOVS, llvm::X86ISD::REP_STOS, llvm::X86ISD::RET_FLAG, llvm::X86ISD::RNDSCALE, llvm::X86ISD::RSQRT28, llvm::X86ISD::SAHF, llvm::X86ISD::SBB, llvm::X86ISD::SCALEF, llvm::X86ISD::SDIVREM8_SEXT_HREG, llvm::X86ISD::SEG_ALLOCA, llvm::X86ISD::SELECT, llvm::X86ISD::SETCC, llvm::X86ISD::SETCC_CARRY, llvm::X86ISD::SFENCE, llvm::X86ISD::SHLD, llvm::X86ISD::SHRD, llvm::X86ISD::SHRUNKBLEND, llvm::X86ISD::SHUF128, llvm::X86ISD::SHUFP, llvm::X86ISD::SINT_TO_FP_RND, llvm::X86ISD::SMUL, llvm::X86ISD::SMUL8, llvm::X86ISD::SUB, llvm::X86ISD::SUBS, llvm::X86ISD::SUBUS, llvm::X86ISD::SUBV_BROADCAST, llvm::X86ISD::TC_RETURN, llvm::X86ISD::TESTM, llvm::X86ISD::TESTNM, llvm::X86ISD::TESTP, llvm::X86ISD::TLSADDR, llvm::X86ISD::TLSBASEADDR, llvm::X86ISD::TLSCALL, llvm::X86ISD::UCOMI, llvm::X86ISD::UDIVREM8_ZEXT_HREG, llvm::X86ISD::UINT_TO_FP_RND, llvm::X86ISD::UMUL, llvm::X86ISD::UMUL8, llvm::X86ISD::UNPCKH, llvm::X86ISD::UNPCKL, llvm::X86ISD::VAARG_64, llvm::X86ISD::VALIGN, llvm::X86ISD::VASTART_SAVE_XMM_REGS, llvm::X86ISD::VBROADCAST, llvm::X86ISD::VEXTRACT, llvm::X86ISD::VFIXUPIMM, llvm::X86ISD::VFPEXT, llvm::X86ISD::VFPROUND, llvm::X86ISD::VINSERT, llvm::X86ISD::VPERM2X128, llvm::X86ISD::VPERMI, llvm::X86ISD::VPERMILPI, llvm::X86ISD::VPERMILPV, llvm::X86ISD::VPERMIV3, llvm::X86ISD::VPERMV, llvm::X86ISD::VPERMV3, llvm::X86ISD::VRANGE, llvm::X86ISD::VSEXT, llvm::X86ISD::VSHL, llvm::X86ISD::VSHLDQ, llvm::X86ISD::VSHLI, llvm::X86ISD::VSRA, llvm::X86ISD::VSRAI, llvm::X86ISD::VSRL, llvm::X86ISD::VSRLDQ, llvm::X86ISD::VSRLI, llvm::X86ISD::VTRUNC, llvm::X86ISD::VTRUNCM, llvm::X86ISD::VZEXT, llvm::X86ISD::VZEXT_LOAD, llvm::X86ISD::VZEXT_MOVL, llvm::X86ISD::WIN_ALLOCA, llvm::X86ISD::WIN_FTOL, llvm::X86ISD::Wrapper, llvm::X86ISD::WrapperRIP, llvm::X86ISD::XOR, and llvm::X86ISD::XTEST.
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Return true if it is cheap to speculate a call to intrinsic ctlz.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 3968 of file X86ISelLowering.cpp.
References llvm::X86Subtarget::hasLZCNT().
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Return true if it is cheap to speculate a call to intrinsic cttz.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 3963 of file X86ISelLowering.cpp.
References llvm::X86Subtarget::hasBMI().
Return true if the target has native support for the specified value type and it is 'desirable' to use the type.
IsDesirableToPromoteOp - This method query the target whether it is beneficial for dag combiner to promote the specified node.
e.g. On x86 i16 is legal, but undesirable since i16 instruction encodings are longer and some i16 instructions are slow.
If true, it should return the desired promotion type by reference.
Reimplemented from llvm::TargetLowering.
Definition at line 25466 of file X86ISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::ISD::CopyToReg, llvm::LoadSDNode::getExtensionType(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::MVT::i32, llvm::AArch64DB::LD, llvm::ISD::LOAD, MayFoldIntoStore(), MayFoldLoad(), llvm::ISD::MUL, llvm::ISD::NON_EXTLOAD, llvm::ISD::OR, llvm::TargetLoweringBase::Promote, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::ISD::SRL, llvm::ISD::SUB, llvm::SDNode::use_begin(), llvm::SDNode::use_end(), llvm::ISD::XOR, and llvm::ISD::ZERO_EXTEND.
Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 3955 of file X86ISelLowering.cpp.
References llvm::ISD::EXTRACT_SUBVECTOR, llvm::EVT::getVectorNumElements(), and llvm::TargetLoweringBase::isOperationLegalOrCustom().
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
fmuladd intrinsics will be expanded to FMAs when this method returns true, otherwise fmuladd is expanded to fmul + fadd.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 19191 of file X86ISelLowering.cpp.
References llvm::MVT::f64, llvm::EVT::getScalarType(), llvm::EVT::getSimpleVT(), llvm::X86Subtarget::hasAVX512(), llvm::X86Subtarget::hasFMA(), llvm::X86Subtarget::hasFMA4(), llvm::EVT::isSimple(), and llvm::MVT::SimpleTy.
Returns true if the target can instruction select the specified FP immediate natively.
isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively.
If false, the legalizer will materialize the FP immediate as a load from a constant pool.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 3923 of file X86ISelLowering.cpp.
References llvm::APFloat::bitwiseIsEqual().
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isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + offset.
Reimplemented from llvm::TargetLowering.
Definition at line 20775 of file X86ISelLowering.cpp.
References llvm::getOffset(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::TargetLowering::isGAPlusOffset(), and llvm::X86ISD::Wrapper.
Return true if the MSVC _ftol2 routine should be used for fptoui to the given type.
Definition at line 861 of file X86ISelLowering.h.
References llvm::MVT::i64, and isTargetFTOL().
Referenced by ReplaceNodeResults().
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Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register and the immediate without having to materialize the immediate into a register.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 19141 of file X86ISelLowering.cpp.
References llvm::isInt< 32 >().
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Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 19044 of file X86ISelLowering.cpp.
References llvm::TargetLoweringBase::AddrMode::BaseGV, llvm::TargetLoweringBase::AddrMode::BaseOffs, llvm::X86Subtarget::ClassifyGlobalReference(), llvm::TargetMachine::getCodeModel(), llvm::TargetMachine::getRelocationModel(), llvm::TargetLoweringBase::getTargetMachine(), llvm::TargetLoweringBase::AddrMode::HasBaseReg, llvm::X86Subtarget::is64Bit(), llvm::isGlobalRelativeToPICBase(), llvm::isGlobalStubReference(), llvm::X86::isOffsetSuitableForCodeModel(), llvm::TargetLoweringBase::AddrMode::Scale, llvm::CodeModel::Small, and llvm::Reloc::Static.
Referenced by getScalingFactorCost().
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Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 19137 of file X86ISelLowering.cpp.
References llvm::isInt< 32 >().
Return true if it's profitable to narrow operations of type VT1 to VT2.
e.g. on x86, it's profitable to narrow from i32 to i8 but not from i32 to i16.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 19211 of file X86ISelLowering.cpp.
References llvm::MVT::i16.
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Returns true if a cast between SrcAS and DestAS is a noop.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 1967 of file X86ISelLowering.cpp.
Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline.
This is mostly true for all types except for some special cases. For example, on X86 targets without SSE2 f64 load / store are done with fldl / fstpl which also does type conversion. Note the specified type doesn't have to be legal as the hook is used before type legalization.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 1850 of file X86ISelLowering.cpp.
References llvm::MVT::f32, and llvm::MVT::f64.
Return true if the specified scalar FP type is computed in an SSE register, not on the X87 floating point stack.
Definition at line 851 of file X86ISelLowering.h.
References llvm::MVT::f32, and llvm::MVT::f64.
Referenced by BuildFILD(), and getRegForInlineAsmConstraint().
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Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks.
isShuffleMaskLegal - Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks.
By default, if a target supports the VECTOR_SHUFFLE node, all mask values are assumed to be legal.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 19221 of file X86ISelLowering.cpp.
References llvm::EVT::getScalarType(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::MVT::i1, llvm::EVT::isSimple(), and llvm::TargetLoweringBase::isTypeLegal().
Referenced by isVectorClearMaskLegal().
| bool X86TargetLowering::isTargetFTOL | ( | ) | const |
Return true if the target uses the MSVC _ftol2 routine for fptoui.
Definition at line 26218 of file X86ISelLowering.cpp.
References llvm::X86Subtarget::is64Bit(), and llvm::X86Subtarget::isTargetKnownWindowsMSVC().
Referenced by isIntegerTypeFTOL(), and X86TargetLowering().
Return true if it's free to truncate a value of type Ty1 to type Ty2.
e.g. On x86 it's free to truncate a i32 value in register EAX to i16 by referencing its sub-register AX.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 19115 of file X86ISelLowering.cpp.
References llvm::Type::getPrimitiveSizeInBits(), and llvm::Type::isIntegerTy().
Reimplemented from llvm::TargetLoweringBase.
Definition at line 19146 of file X86ISelLowering.cpp.
References llvm::EVT::getSizeInBits(), and llvm::EVT::isInteger().
Return true if the target has native support for the specified value type and it is 'desirable' to use the type for the given node type.
isTypeDesirableForOp - Return true if the target has native support for the specified value type and it is 'desirable' to use the type for the given node type.
e.g. On x86 i16 is legal, but undesirable since i16 instruction encodings are longer and some i16 instructions are slow.
Reimplemented from llvm::TargetLowering.
Definition at line 25438 of file X86ISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::TargetLoweringBase::isTypeLegal(), llvm::ISD::LOAD, llvm::ISD::MUL, llvm::ISD::OR, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::ISD::SRL, llvm::ISD::SUB, llvm::ISD::XOR, and llvm::ISD::ZERO_EXTEND.
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Similar to isShuffleMaskLegal.
This is used by Targets can use this to indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a constant pool entry.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 19240 of file X86ISelLowering.cpp.
References isShuffleMaskLegal().
Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 19188 of file X86ISelLowering.cpp.
Return true if it's significantly cheaper to shift a vector by a uniform scalar than by an amount which will vary across each lane.
On x86, for example, there is a "psllw" instruction for the former case, but no simple instruction for a general "a << b" operation on vectors.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 19097 of file X86ISelLowering.cpp.
References llvm::tgtok::Bits, llvm::Type::getScalarSizeInBits(), and llvm::X86Subtarget::hasInt256().
Return true if any actual instruction that defines a value of type Ty1 implicit zero-extends the value to Ty2 in the result register.
This does not necessarily include registers defined in unknown ways, such as incoming arguments, or copies from unknown virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this does not necessarily apply to truncate instructions. e.g. on x86-64, all instructions that define 32-bit values implicit zero-extend the result out to 64 bits.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 19154 of file X86ISelLowering.cpp.
References llvm::X86Subtarget::is64Bit(), and llvm::Type::isIntegerTy().
Referenced by isZExtFree().
Reimplemented from llvm::TargetLoweringBase.
Definition at line 19159 of file X86ISelLowering.cpp.
References llvm::MVT::i64, and llvm::X86Subtarget::is64Bit().
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicitly zero-extended such as ARM ldrb / ldrh or because it's folded such as X86 zero-extending loads).
Reimplemented from llvm::TargetLoweringBase.
Definition at line 19164 of file X86ISelLowering.cpp.
References llvm::SDValue::getOpcode(), llvm::EVT::getSimpleVT(), llvm::SDValue::getValueType(), llvm::MVT::i8, llvm::EVT::isInteger(), llvm::EVT::isSimple(), isZExtFree(), llvm::ISD::LOAD, and llvm::MVT::SimpleTy.
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Lower the specified operand into the Ops vector.
LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector.
If it is invalid, don't add anything to Ops. If hasMemory is true it means one of the asm constraint of the inline asm instruction being processed is 'm'.
If it is invalid, don't add anything to Ops.
Reimplemented from llvm::TargetLowering.
Definition at line 25813 of file X86ISelLowering.cpp.
References llvm::ISD::ADD, llvm::X86Subtarget::ClassifyGlobalReference(), llvm::SelectionDAG::getContext(), llvm::GlobalAddressSDNode::getGlobal(), llvm::Type::getInt32Ty(), llvm::SDValue::getNode(), llvm::GlobalAddressSDNode::getOffset(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ConstantSDNode::getSExtValue(), llvm::SelectionDAG::getTarget(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetGlobalAddress(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::ConstantSDNode::getZExtValue(), llvm::MVT::i64, llvm::X86Subtarget::is64Bit(), llvm::isGlobalStubReference(), llvm::isInt< 8 >(), llvm::X86Subtarget::isPICStyleGOT(), llvm::X86Subtarget::isPICStyleStubPIC(), llvm::ConstantInt::isValueValidForType(), llvm::TargetLowering::LowerAsmOperandForConstraint(), and llvm::ISD::SUB.
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Reimplemented from llvm::TargetLowering.
Definition at line 1887 of file X86ISelLowering.cpp.
References llvm::MCSymbolRefExpr::create(), llvm::MachineBasicBlock::getParent(), llvm::TargetMachine::getRelocationModel(), llvm::MachineBasicBlock::getSymbol(), llvm::MachineFunction::getTarget(), llvm::X86Subtarget::isPICStyleGOT(), llvm::Reloc::PIC_, and llvm::MCSymbolRefExpr::VK_GOTOFF.
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Provide custom lowering hooks for some operations.
LowerOperation - Provide custom lowering hooks for some operations.
Reimplemented from llvm::TargetLowering.
Definition at line 18503 of file X86ISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::ADDC, llvm::ISD::ADDE, llvm::ISD::ADJUST_TRAMPOLINE, llvm::ISD::ANY_EXTEND, llvm::ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, llvm::ISD::ATOMIC_FENCE, llvm::ISD::ATOMIC_LOAD_SUB, llvm::ISD::ATOMIC_STORE, llvm::ISD::BITCAST, llvm::ISD::BlockAddress, llvm::ISD::BRCOND, llvm::ISD::BUILD_VECTOR, llvm::ISD::CONCAT_VECTORS, llvm::ISD::ConstantPool, llvm::ISD::CTLZ, llvm::ISD::CTLZ_ZERO_UNDEF, llvm::ISD::CTPOP, llvm::ISD::CTTZ, llvm::ISD::DYNAMIC_STACKALLOC, llvm::ISD::EH_RETURN, llvm::ISD::EH_SJLJ_LONGJMP, llvm::ISD::EH_SJLJ_SETJMP, llvm::ISD::ExternalSymbol, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FABS, llvm::ISD::FCOPYSIGN, llvm::ISD::FGETSIGN, llvm::ISD::FLT_ROUNDS_, llvm::ISD::FNEG, llvm::ISD::FP_EXTEND, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::ISD::FRAME_TO_ARGS_OFFSET, llvm::ISD::FRAMEADDR, llvm::ISD::FSINCOS, llvm::ISD::GC_TRANSITION_END, llvm::ISD::GC_TRANSITION_START, llvm::SDValue::getOpcode(), llvm::ISD::GlobalAddress, llvm::ISD::GlobalTLSAddress, llvm::ISD::INIT_TRAMPOLINE, llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::ISD::JumpTable, llvm_unreachable, llvm::ISD::LOAD, LowerADD(), LowerADDC_ADDE_SUBC_SUBE(), LowerADJUST_TRAMPOLINE(), LowerANY_EXTEND(), LowerATOMIC_FENCE(), LowerATOMIC_STORE(), LowerBITCAST(), LowerCMP_SWAP(), LowerCONCAT_VECTORS(), LowerCTLZ(), LowerCTLZ_ZERO_UNDEF(), LowerCTPOP(), LowerCTTZ(), LowerExtendedLoad(), LowerEXTRACT_SUBVECTOR(), LowerFABSorFNEG(), LowerFCOPYSIGN(), LowerFGETSIGN(), LowerFP_EXTEND(), LowerFSINCOS(), LowerINSERT_SUBVECTOR(), LowerINTRINSIC_W_CHAIN(), LowerINTRINSIC_WO_CHAIN(), LowerLOAD_SUB(), LowerMGATHER(), LowerMSCATTER(), LowerMUL(), LowerMUL_LOHI(), LowerREADCYCLECOUNTER(), LowerSCALAR_TO_VECTOR(), LowerShift(), LowerShiftParts(), LowerSIGN_EXTEND(), LowerSIGN_EXTEND_VECTOR_INREG(), LowerSUB(), LowerVACOPY(), lowerVectorShuffle(), LowerXALUO(), LowerZERO_EXTEND(), llvm::ISD::MGATHER, llvm::ISD::MSCATTER, llvm::ISD::MUL, llvm::ISD::READCYCLECOUNTER, llvm::ISD::RETURNADDR, llvm::ISD::SADDO, llvm::ISD::SCALAR_TO_VECTOR, llvm::ISD::SELECT, llvm::ISD::SETCC, llvm::ISD::SHL, llvm::ISD::SHL_PARTS, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_VECTOR_INREG, llvm::ISD::SINT_TO_FP, llvm::ISD::SMUL_LOHI, llvm::ISD::SMULO, llvm::ISD::SRA, llvm::ISD::SRA_PARTS, llvm::ISD::SRL, llvm::ISD::SRL_PARTS, llvm::ISD::SSUBO, llvm::ISD::SUB, llvm::ISD::SUBC, llvm::ISD::SUBE, llvm::ISD::TRUNCATE, llvm::ISD::UADDO, llvm::ISD::UINT_TO_FP, llvm::ISD::UMUL_LOHI, llvm::ISD::UMULO, llvm::ISD::USUBO, llvm::ISD::VAARG, llvm::ISD::VACOPY, llvm::ISD::VASTART, llvm::ISD::VECTOR_SHUFFLE, llvm::ISD::VSELECT, and llvm::ISD::ZERO_EXTEND.
LowerXConstraint - try to replace an X constraint, which matches anything, with another that has more specific requirements based on the type of the corresponding operand.
Reimplemented from llvm::TargetLowering.
Definition at line 25798 of file X86ISelLowering.cpp.
References llvm::X86Subtarget::hasSSE1(), llvm::X86Subtarget::hasSSE2(), llvm::EVT::isFloatingPoint(), and llvm::TargetLowering::LowerXConstraint().
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This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for.
The semantics are as follows: Return Value: SDValue.Val == 0 - No change was made SDValue.Val == N - N was replaced, is dead, and is already handled. otherwise - N should be replaced by the returned Operand.
In addition, methods provided by DAGCombinerInfo may be used to perform more complex transformations.
Reimplemented from llvm::TargetLowering.
Definition at line 25357 of file X86ISelLowering.cpp.
References llvm::X86ISD::ADC, llvm::ISD::ADD, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::ISD::BITCAST, llvm::X86ISD::BLENDI, llvm::X86ISD::BRCOND, llvm::X86ISD::BT, llvm::X86ISD::CMOV, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FADD, llvm::X86ISD::FAND, llvm::X86ISD::FANDN, llvm::ISD::FMA, llvm::X86ISD::FMAX, llvm::X86ISD::FMIN, llvm::X86ISD::FOR, llvm::ISD::FSUB, llvm::X86ISD::FXOR, llvm::SDNode::getOpcode(), llvm::TargetLoweringBase::getTargetMachine(), llvm::X86ISD::INSERTPS, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::ISD::LOAD, llvm::ISD::MLOAD, llvm::X86ISD::MOVHLPS, llvm::X86ISD::MOVLHPS, llvm::X86ISD::MOVSD, llvm::X86ISD::MOVSS, llvm::ISD::MSTORE, llvm::ISD::MUL, llvm::CodeGenOpt::None, llvm::ISD::OR, llvm::X86ISD::PALIGNR, PerformADCCombine(), PerformAddCombine(), PerformAndCombine(), PerformBITCASTCombine(), PerformBLENDICombine(), PerformBrCondCombine(), PerformBTCombine(), PerformCMOVCombine(), PerformEXTRACT_VECTOR_ELTCombine(), PerformFADDCombine(), PerformFANDCombine(), PerformFANDNCombine(), PerformFMACombine(), PerformFMinFMaxCombine(), PerformFORCombine(), PerformFSUBCombine(), PerformINSERTPSCombine(), PerformINTRINSIC_WO_CHAINCombine(), PerformISDSETCCCombine(), PerformLOADCombine(), PerformMLOADCombine(), PerformMSTORECombine(), PerformMulCombine(), PerformOrCombine(), PerformSELECTCombine(), PerformSETCCCombine(), PerformSExtCombine(), PerformShiftCombine(), PerformShuffleCombine(), PerformSIGN_EXTEND_INREGCombine(), PerformSINT_TO_FPCombine(), PerformSTORECombine(), PerformSubCombine(), PerformUINT_TO_FPCombine(), PerformVZEXT_MOVLCombine(), performVZEXTCombine(), PerformXorCombine(), PerformZExtCombine(), llvm::X86ISD::PSHUFB, llvm::X86ISD::PSHUFD, llvm::X86ISD::PSHUFHW, llvm::X86ISD::PSHUFLW, llvm::ISD::SELECT, llvm::X86ISD::SETCC, llvm::ISD::SETCC, llvm::ISD::SHL, llvm::X86ISD::SHRUNKBLEND, llvm::X86ISD::SHUFP, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SINT_TO_FP, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::STORE, llvm::ISD::SUB, llvm::ISD::UINT_TO_FP, llvm::X86ISD::UNPCKH, llvm::X86ISD::UNPCKL, llvm::ISD::VECTOR_SHUFFLE, llvm::X86ISD::VPERM2X128, llvm::X86ISD::VPERMILPI, llvm::ISD::VSELECT, llvm::X86ISD::VZEXT, llvm::X86ISD::VZEXT_MOVL, llvm::ISD::XOR, and llvm::ISD::ZERO_EXTEND.
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Replace the results of node with an illegal result type with new values built out of custom code.
ReplaceNodeResults - Replace a node with an illegal result type with a new node built out of custom code.
Reimplemented from llvm::TargetLowering.
Definition at line 18600 of file X86ISelLowering.cpp.
References llvm::ISD::ADDC, llvm::ISD::ADDE, llvm::ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, llvm::ISD::ATOMIC_LOAD, llvm::ISD::ATOMIC_LOAD_ADD, llvm::ISD::ATOMIC_LOAD_AND, llvm::ISD::ATOMIC_LOAD_MAX, llvm::ISD::ATOMIC_LOAD_MIN, llvm::ISD::ATOMIC_LOAD_NAND, llvm::ISD::ATOMIC_LOAD_OR, llvm::ISD::ATOMIC_LOAD_SUB, llvm::ISD::ATOMIC_LOAD_UMAX, llvm::ISD::ATOMIC_LOAD_UMIN, llvm::ISD::ATOMIC_LOAD_XOR, llvm::ISD::ATOMIC_SWAP, llvm::ISD::BITCAST, llvm::BitsToDouble(), llvm::ISD::BUILD_PAIR, llvm::ISD::BUILD_VECTOR, llvm::ISD::CONCAT_VECTORS, llvm::X86::COND_E, ExperimentalVectorWideningLegalization, llvm::ISD::EXTRACT_ELEMENT, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f16, llvm::MVT::f64, llvm::X86ISD::FMAX, llvm::X86ISD::FMAXC, llvm::X86ISD::FMIN, llvm::X86ISD::FMINC, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::ISD::FSUB, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getConstantFP(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getCopyToReg(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), getReadPerformanceCounter(), getReadTimeStampCounter(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::TargetLoweringBase::getValueType(), llvm::MVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::SelectionDAG::getVTList(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::MVT::Glue, llvm::X86Subtarget::hasSSE2(), llvm::MVT::i128, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::ISD::INTRINSIC_W_CHAIN, isIntegerTypeFTOL(), llvm::TargetLoweringBase::isTypeLegal(), llvm::X86ISD::LCMPXCHG16_DAG, llvm::X86ISD::LCMPXCHG8_DAG, llvm_unreachable, N, llvm::ISD::OR, llvm::APIntOps::Or(), llvm::MVT::Other, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::X86ISD::RDTSC_DAG, llvm::X86ISD::RDTSCP_DAG, llvm::ISD::READCYCLECOUNTER, llvm::ISD::SCALAR_TO_VECTOR, llvm::ISD::SDIV, llvm::ISD::SDIVREM, llvm::X86ISD::SETCC, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SREM, llvm::ISD::SUBC, llvm::ISD::SUBE, llvm::Success, llvm::ISD::UDIV, llvm::ISD::UDIVREM, llvm::ISD::UINT_TO_FP, llvm::ISD::UNDEF, llvm::ISD::UREM, llvm::MVT::v2f32, llvm::MVT::v2f64, llvm::MVT::v2i32, llvm::MVT::v2i64, llvm::MVT::v4f32, llvm::MVT::v4i16, llvm::MVT::v8i8, llvm::X86ISD::VFPROUND, and llvm::ISD::ZERO_EXTEND.
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Returns true if it is beneficial to convert a load of a constant to just the constant itself.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 3945 of file X86ISelLowering.cpp.
References llvm::Type::getPrimitiveSizeInBits(), and llvm::Type::isIntegerTy().
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Return true if we believe it is correct and profitable to reduce the load node to a smaller type.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 3931 of file X86ISelLowering.cpp.
References llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SPII::Load, llvm::X86II::MO_GOTTPOFF, and llvm::X86ISD::WrapperRIP.
If true, then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 837 of file X86ISelLowering.h.
References llvm::MVT::f80.
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If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
Reimplemented from llvm::TargetLowering.
Definition at line 1700 of file X86ISelLowering.cpp.
References llvm::X86Subtarget::is64Bit(), and llvm::X86Subtarget::isTargetMachO().
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Reimplemented from llvm::TargetLoweringBase.
Definition at line 1882 of file X86ISelLowering.cpp.
References llvm::X86Subtarget::useSoftFloat().
1.8.6