43 case AMDGPU::INTERP_PAIR_XY:
44 case AMDGPU::INTERP_PAIR_ZW:
45 case AMDGPU::INTERP_VEC_LOAD:
59 if(
TII->isVector(*MI) ||
64 unsigned NumLiteral = 0;
68 if (MO.
isReg() && MO.
getReg() == AMDGPU::ALU_LITERAL_X)
71 return 1 + NumLiteral;
81 case AMDGPU::INTERP_PAIR_XY:
82 case AMDGPU::INTERP_PAIR_ZW:
83 case AMDGPU::INTERP_VEC_LOAD:
103 std::pair<unsigned, unsigned> getAccessedBankLine(
unsigned Sel)
const {
107 return std::pair<unsigned, unsigned>(
108 ((Sel >> 2) - 512) >> 12,
114 ((((Sel >> 2) - 512) & 4095) >> 5) << 1);
118 std::vector<std::pair<unsigned, unsigned> > &CachedConsts,
119 bool UpdateInstr =
true)
const {
120 std::vector<std::pair<unsigned, unsigned> > UsedKCache;
128 MI->
getOpcode() == AMDGPU::DOT_4) &&
"Can't assign Const");
129 for (
unsigned i = 0, n = Consts.
size(); i < n; ++i) {
130 if (Consts[i].first->getReg() != AMDGPU::ALU_CONST)
132 unsigned Sel = Consts[i].second;
133 unsigned Chan = Sel & 3, Index = ((Sel >> 2) - 512) & 31;
134 unsigned KCacheIndex = Index * 4 + Chan;
135 const std::pair<unsigned, unsigned> &BankLine = getAccessedBankLine(Sel);
136 if (CachedConsts.empty()) {
137 CachedConsts.push_back(BankLine);
138 UsedKCache.push_back(std::pair<unsigned, unsigned>(0, KCacheIndex));
141 if (CachedConsts[0] == BankLine) {
142 UsedKCache.push_back(std::pair<unsigned, unsigned>(0, KCacheIndex));
145 if (CachedConsts.size() == 1) {
146 CachedConsts.push_back(BankLine);
147 UsedKCache.push_back(std::pair<unsigned, unsigned>(1, KCacheIndex));
150 if (CachedConsts[1] == BankLine) {
151 UsedKCache.push_back(std::pair<unsigned, unsigned>(1, KCacheIndex));
160 for (
unsigned i = 0, j = 0, n = Consts.
size(); i < n; ++i) {
161 if (Consts[i].first->getReg() != AMDGPU::ALU_CONST)
163 switch(UsedKCache[j].first) {
165 Consts[i].first->setReg(
166 AMDGPU::R600_KC0RegClass.getRegister(UsedKCache[j].second));
169 Consts[i].first->setReg(
170 AMDGPU::R600_KC1RegClass.getRegister(UsedKCache[j].second));
180 bool canClauseLocalKillFitInClause(
181 unsigned AluInstCount,
182 std::vector<std::pair<unsigned, unsigned> > KCacheBanks,
187 MOI = Def->operands_begin(),
188 MOE = Def->operands_end(); MOI != MOE; ++MOI) {
189 if (!MOI->isReg() || !MOI->isDef() ||
195 unsigned LastUseCount = 0;
197 AluInstCount += OccupiedDwords(UseI);
199 if (!SubstituteKCacheBank(UseI, KCacheBanks,
false))
205 if (AluInstCount >=
TII->getMaxAlusPerClause())
213 if (UseI->findRegisterUseOperandIdx(MOI->getReg()))
214 LastUseCount = AluInstCount;
216 if (UseI != Def && UseI->findRegisterDefOperandIdx(MOI->getReg()) != -1)
220 return LastUseCount <=
TII->getMaxAlusPerClause();
229 std::vector<std::pair<unsigned, unsigned> > KCacheBanks;
230 bool PushBeforeModifier =
false;
231 unsigned AluInstCount = 0;
233 if (IsTrivialInst(I))
237 if (AluInstCount >
TII->getMaxAlusPerClause())
239 if (I->getOpcode() == AMDGPU::PRED_X) {
246 if (AluInstCount > 0)
249 PushBeforeModifier =
true;
260 if (
TII->mustBeLastInClause(I->getOpcode())) {
267 if (!canClauseLocalKillFitInClause(AluInstCount, KCacheBanks, I, E))
270 if (!SubstituteKCacheBank(I, KCacheBanks))
272 AluInstCount += OccupiedDwords(I);
274 unsigned Opcode = PushBeforeModifier ?
275 AMDGPU::CF_ALU_PUSH_BEFORE : AMDGPU::CF_ALU;
282 .
addImm(KCacheBanks.empty()?0:KCacheBanks[0].first)
283 .addImm((KCacheBanks.size() < 2)?0:KCacheBanks[1].first)
284 .
addImm(KCacheBanks.empty()?0:2)
285 .addImm((KCacheBanks.size() < 2)?0:2)
286 .
addImm(KCacheBanks.empty()?0:KCacheBanks[0].second)
287 .addImm((KCacheBanks.size() < 2)?0:KCacheBanks[1].second)
307 if (I->getOpcode() == AMDGPU::CF_ALU)
311 I = MakeALUClause(MBB, I);
319 const char *getPassName()
const override {
320 return "R600 Emit Clause Markers Pass";
329 "R600 Emit Clause Markters",
false,
false)
334 return new R600EmitClauseMarkers();
mop_iterator operands_end()
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
AMDGPU specific subclass of TargetSubtarget.
Interface definition for R600InstrInfo.
void initializeR600EmitClauseMarkersPass(PassRegistry &)
Interface definition for R600RegisterInfo.
R600 Emit Clause Markters
COPY - Target-independent register copy.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
const HexagonRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
bundle_iterator< MachineInstr, instr_iterator > iterator
INITIALIZE_PASS_BEGIN(R600EmitClauseMarkers,"emitclausemarkers","R600 Emit Clause Markters", false, false) INITIALIZE_PASS_END(R600EmitClauseMarkers
DebugLoc findDebugLoc(instr_iterator MBBI)
findDebugLoc - find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE instructions...
FunctionPass class - This class is used to implement most global optimizations.
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
MachineOperand class - Representation of each machine instruction operand.
bool isPhysRegLiveAcrossClauses(unsigned Reg) const
KILL - This instruction is a noop that is used only to adjust the liveness of registers.
Representation of each machine instruction.
FunctionPass * createR600EmitClauseMarkers()
unsigned getReg() const
getReg - Returns the register number.
virtual const TargetInstrInfo * getInstrInfo() const
mop_iterator operands_begin()
BasicBlockListType::iterator iterator
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...