LLVM  3.7.0
HexagonTargetMachine.cpp
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1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Implements the info about Hexagon target spec.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "HexagonTargetMachine.h"
15 #include "Hexagon.h"
16 #include "HexagonISelLowering.h"
19 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/IR/Module.h"
25 #include "llvm/Transforms/Scalar.h"
26 
27 using namespace llvm;
28 
29 static cl:: opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
30  cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
31 
32 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
34  cl::desc("Disable Hexagon CFG Optimization"));
35 
36 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
38  cl::desc("Early expansion of MUX"));
39 
40 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
41  cl::Hidden, cl::desc("Generate \"insert\" instructions"));
42 
43 static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
44  cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
45 
46 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
47  cl::Hidden, cl::desc("Generate \"extract\" instructions"));
48 
49 static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
50  cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
51  "predicate instructions"));
52 
53 /// HexagonTargetMachineModule - Note that this is used on hosts that
54 /// cannot link in a library unless there are references into the
55 /// library. In particular, it seems that it is not possible to get
56 /// things to work on Win32 without this. Though it is unused, do not
57 /// remove it.
60 
61 extern "C" void LLVMInitializeHexagonTarget() {
62  // Register the target.
64 }
65 
67  return new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>());
68 }
69 
71 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
73 
74 namespace llvm {
86  CodeGenOpt::Level OptLevel);
92 } // end namespace llvm;
93 
94 /// HexagonTargetMachine ctor - Create an ILP32 architecture model.
95 ///
96 
97 /// Hexagon_TODO: Do I need an aggregate alignment?
98 ///
100  StringRef CPU, StringRef FS,
101  const TargetOptions &Options,
104  : LLVMTargetMachine(T, "e-m:e-p:32:32-i1:32-i64:64-a:0-n32", TT, CPU, FS,
105  Options, RM, CM, OL),
107  Subtarget(TT, CPU, FS, *this) {
108  initAsmInfo();
109 }
110 
112 
113 namespace {
114 /// Hexagon Code Generator Pass Configuration Options.
115 class HexagonPassConfig : public TargetPassConfig {
116 public:
117  HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM)
118  : TargetPassConfig(TM, PM) {
119  bool NoOpt = (TM->getOptLevel() == CodeGenOpt::None);
120  if (!NoOpt) {
121  if (EnableExpandCondsets) {
123  insertPass(&RegisterCoalescerID, IdentifyingPassPtr(Exp));
124  }
125  }
126  }
127 
128  HexagonTargetMachine &getHexagonTargetMachine() const {
129  return getTM<HexagonTargetMachine>();
130  }
131 
133  createMachineScheduler(MachineSchedContext *C) const override {
134  return createVLIWMachineSched(C);
135  }
136 
137  void addIRPasses() override;
138  bool addInstSelector() override;
139  void addPreRegAlloc() override;
140  void addPostRegAlloc() override;
141  void addPreSched2() override;
142  void addPreEmitPass() override;
143 };
144 } // namespace
145 
147  return new HexagonPassConfig(this, PM);
148 }
149 
150 void HexagonPassConfig::addIRPasses() {
152  bool NoOpt = (getOptLevel() == CodeGenOpt::None);
153 
154  addPass(createAtomicExpandPass(TM));
155  if (!NoOpt) {
156  if (EnableCommGEP)
157  addPass(createHexagonCommonGEP());
158  // Replace certain combinations of shifts and ands with extracts.
159  if (EnableGenExtract)
160  addPass(createHexagonGenExtract());
161  }
162 }
163 
164 bool HexagonPassConfig::addInstSelector() {
165  HexagonTargetMachine &TM = getHexagonTargetMachine();
166  bool NoOpt = (getOptLevel() == CodeGenOpt::None);
167 
168  if (!NoOpt)
169  addPass(createHexagonRemoveExtendArgs(TM));
170 
171  addPass(createHexagonISelDag(TM, getOptLevel()));
172 
173  if (!NoOpt) {
174  // Create logical operations on predicate registers.
175  if (EnableGenPred)
176  addPass(createHexagonGenPredicate(), false);
177  addPass(createHexagonPeephole());
178  printAndVerify("After hexagon peephole pass");
179  if (EnableGenInsert)
180  addPass(createHexagonGenInsert(), false);
181  }
182 
183  return false;
184 }
185 
186 void HexagonPassConfig::addPreRegAlloc() {
187  if (getOptLevel() != CodeGenOpt::None)
189  addPass(createHexagonHardwareLoops(), false);
190 }
191 
192 void HexagonPassConfig::addPostRegAlloc() {
193  if (getOptLevel() != CodeGenOpt::None)
195  addPass(createHexagonCFGOptimizer(), false);
196 }
197 
198 void HexagonPassConfig::addPreSched2() {
199  addPass(createHexagonCopyToCombine(), false);
200  if (getOptLevel() != CodeGenOpt::None)
201  addPass(&IfConverterID, false);
203 }
204 
205 void HexagonPassConfig::addPreEmitPass() {
206  bool NoOpt = (getOptLevel() == CodeGenOpt::None);
207 
208  if (!NoOpt)
209  addPass(createHexagonNewValueJump(), false);
210 
211  // Expand Spill code for predicate registers.
212  addPass(createHexagonExpandPredSpillCode(), false);
213 
214  // Create Packets.
215  if (!NoOpt) {
217  addPass(createHexagonFixupHwLoops(), false);
218  addPass(createHexagonPacketizer(), false);
219  }
220 }
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:82
FunctionPass * createHexagonCopyToCombine()
Extend the standard ScheduleDAGMI to provide more context and override the top-level schedule() drive...
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: Passes.cpp:377
HexagonTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL)
HexagonTargetMachine ctor - Create an ILP32 architecture model.
FunctionPass * createHexagonExpandCondsets()
char & RegisterCoalescerID
RegisterCoalescer - This pass merges live ranges to eliminate copies.
static MachineSchedRegistry SchedCustomRegistry("hexagon","Run Hexagon's custom scheduler", createVLIWMachineSched)
FunctionPass * createHexagonHardwareLoops()
MachineSchedRegistry provides a selection of available machine instruction schedulers.
FunctionPass * createHexagonGenPredicate()
FunctionPass * createHexagonCommonGEP()
FunctionPass * createAtomicExpandPass(const TargetMachine *TM)
Target-Independent Code Generator Pass Configuration Options.
static cl::opt< bool > EnableGenPred("hexagon-gen-pred", cl::init(true), cl::Hidden, cl::desc("Enable conversion of arithmetic operations to ""predicate instructions"))
static cl::opt< bool > EnableExpandCondsets("hexagon-expand-condsets", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("Early expansion of MUX"))
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
int HexagonTargetMachineModule
HexagonTargetMachineModule - Note that this is used on hosts that cannot link in a library unless the...
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:325
static ScheduleDAGInstrs * createVLIWMachineSched(MachineSchedContext *C)
std::enable_if<!std::is_array< T >::value, std::unique_ptr< T > >::type make_unique(Args &&...args)
Constructs a new T() with the given args and returns a unique_ptr<T> which owns the object...
Definition: STLExtras.h:354
FunctionPass * createHexagonPacketizer()
static cl::opt< bool > EnableCommGEP("hexagon-commgep", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"))
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang","erlang-compatible garbage collector")
This class describes a target machine that is implemented with the LLVM target-independent code gener...
static cl::opt< bool > DisableHexagonCFGOpt("disable-hexagon-cfgopt", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable Hexagon CFG Optimization"))
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:294
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
FunctionPass * createHexagonNewValueJump()
Module.h This file contains the declarations for the Module class.
FunctionPass * createHexagonPeephole()
FunctionPass * createHexagonRemoveExtendArgs(const HexagonTargetMachine &TM)
FunctionPass * createHexagonGenInsert()
Target - Wrapper for Target specific information.
Discriminated union of Pass ID types.
ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of MachineInstrs. ...
FunctionPass * createHexagonSplitConst32AndConst64()
FunctionPass * createHexagonFixupHwLoops()
char & IfConverterID
IfConverter - This pass performs machine code if conversion.
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
FunctionPass * createHexagonISelDag(HexagonTargetMachine &TM, CodeGenOpt::Level OptLevel)
FunctionPass * createHexagonExpandPredSpillCode()
RegisterTargetMachine - Helper template for registering a target machine implementation, for use in the target machine initialization function.
FunctionPass * createHexagonGenExtract()
static cl::opt< bool > DisableHardwareLoops("disable-hexagon-hwloops", cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"))
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:40
Target TheHexagonTarget
static cl::opt< bool > EnableGenExtract("hexagon-extract", cl::init(true), cl::Hidden, cl::desc("Generate \"extract\" instructions"))
static cl::opt< bool > EnableGenInsert("hexagon-insert", cl::init(true), cl::Hidden, cl::desc("Generate \"insert\" instructions"))
void LLVMInitializeHexagonTarget()
FunctionPass * createHexagonCFGOptimizer()