LLVM  3.7.0
LiveRangeEdit.cpp
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1 //===-- LiveRangeEdit.cpp - Basic tools for editing a register live range -===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // The LiveRangeEdit class represents changes done to a virtual register when it
11 // is spilled or split.
12 //===----------------------------------------------------------------------===//
13 
15 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Support/Debug.h"
23 
24 using namespace llvm;
25 
26 #define DEBUG_TYPE "regalloc"
27 
28 STATISTIC(NumDCEDeleted, "Number of instructions deleted by DCE");
29 STATISTIC(NumDCEFoldedLoads, "Number of single use loads folded after DCE");
30 STATISTIC(NumFracRanges, "Number of live ranges fractured by DCE");
31 
32 void LiveRangeEdit::Delegate::anchor() { }
33 
35  unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
36  if (VRM) {
37  VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg));
38  }
39  LiveInterval &LI = LIS.createEmptyInterval(VReg);
40  return LI;
41 }
42 
43 unsigned LiveRangeEdit::createFrom(unsigned OldReg) {
44  unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
45  if (VRM) {
46  VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg));
47  }
48  return VReg;
49 }
50 
52  const MachineInstr *DefMI,
53  AliasAnalysis *aa) {
54  assert(DefMI && "Missing instruction");
55  ScannedRemattable = true;
56  if (!TII.isTriviallyReMaterializable(DefMI, aa))
57  return false;
58  Remattable.insert(VNI);
59  return true;
60 }
61 
62 void LiveRangeEdit::scanRemattable(AliasAnalysis *aa) {
63  for (VNInfo *VNI : getParent().valnos) {
64  if (VNI->isUnused())
65  continue;
66  MachineInstr *DefMI = LIS.getInstructionFromIndex(VNI->def);
67  if (!DefMI)
68  continue;
69  checkRematerializable(VNI, DefMI, aa);
70  }
71  ScannedRemattable = true;
72 }
73 
75  if (!ScannedRemattable)
76  scanRemattable(aa);
77  return !Remattable.empty();
78 }
79 
80 /// allUsesAvailableAt - Return true if all registers used by OrigMI at
81 /// OrigIdx are also available with the same value at UseIdx.
82 bool LiveRangeEdit::allUsesAvailableAt(const MachineInstr *OrigMI,
83  SlotIndex OrigIdx,
84  SlotIndex UseIdx) const {
85  OrigIdx = OrigIdx.getRegSlot(true);
86  UseIdx = UseIdx.getRegSlot(true);
87  for (unsigned i = 0, e = OrigMI->getNumOperands(); i != e; ++i) {
88  const MachineOperand &MO = OrigMI->getOperand(i);
89  if (!MO.isReg() || !MO.getReg() || !MO.readsReg())
90  continue;
91 
92  // We can't remat physreg uses, unless it is a constant.
94  if (MRI.isConstantPhysReg(MO.getReg(), *OrigMI->getParent()->getParent()))
95  continue;
96  return false;
97  }
98 
99  LiveInterval &li = LIS.getInterval(MO.getReg());
100  const VNInfo *OVNI = li.getVNInfoAt(OrigIdx);
101  if (!OVNI)
102  continue;
103 
104  // Don't allow rematerialization immediately after the original def.
105  // It would be incorrect if OrigMI redefines the register.
106  // See PR14098.
107  if (SlotIndex::isSameInstr(OrigIdx, UseIdx))
108  return false;
109 
110  if (OVNI != li.getVNInfoAt(UseIdx))
111  return false;
112  }
113  return true;
114 }
115 
117  SlotIndex UseIdx,
118  bool cheapAsAMove) {
119  assert(ScannedRemattable && "Call anyRematerializable first");
120 
121  // Use scanRemattable info.
122  if (!Remattable.count(RM.ParentVNI))
123  return false;
124 
125  // No defining instruction provided.
126  SlotIndex DefIdx;
127  if (RM.OrigMI)
128  DefIdx = LIS.getInstructionIndex(RM.OrigMI);
129  else {
130  DefIdx = RM.ParentVNI->def;
131  RM.OrigMI = LIS.getInstructionFromIndex(DefIdx);
132  assert(RM.OrigMI && "No defining instruction for remattable value");
133  }
134 
135  // If only cheap remats were requested, bail out early.
136  if (cheapAsAMove && !TII.isAsCheapAsAMove(RM.OrigMI))
137  return false;
138 
139  // Verify that all used registers are available with the same values.
140  if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx))
141  return false;
142 
143  return true;
144 }
145 
148  unsigned DestReg,
149  const Remat &RM,
150  const TargetRegisterInfo &tri,
151  bool Late) {
152  assert(RM.OrigMI && "Invalid remat");
153  TII.reMaterialize(MBB, MI, DestReg, 0, RM.OrigMI, tri);
154  Rematted.insert(RM.ParentVNI);
155  return LIS.getSlotIndexes()->insertMachineInstrInMaps(--MI, Late)
156  .getRegSlot();
157 }
158 
160  if (TheDelegate && TheDelegate->LRE_CanEraseVirtReg(Reg))
161  LIS.removeInterval(Reg);
162 }
163 
164 bool LiveRangeEdit::foldAsLoad(LiveInterval *LI,
166  MachineInstr *DefMI = nullptr, *UseMI = nullptr;
167 
168  // Check that there is a single def and a single use.
169  for (MachineOperand &MO : MRI.reg_nodbg_operands(LI->reg)) {
170  MachineInstr *MI = MO.getParent();
171  if (MO.isDef()) {
172  if (DefMI && DefMI != MI)
173  return false;
174  if (!MI->canFoldAsLoad())
175  return false;
176  DefMI = MI;
177  } else if (!MO.isUndef()) {
178  if (UseMI && UseMI != MI)
179  return false;
180  // FIXME: Targets don't know how to fold subreg uses.
181  if (MO.getSubReg())
182  return false;
183  UseMI = MI;
184  }
185  }
186  if (!DefMI || !UseMI)
187  return false;
188 
189  // Since we're moving the DefMI load, make sure we're not extending any live
190  // ranges.
191  if (!allUsesAvailableAt(DefMI,
192  LIS.getInstructionIndex(DefMI),
193  LIS.getInstructionIndex(UseMI)))
194  return false;
195 
196  // We also need to make sure it is safe to move the load.
197  // Assume there are stores between DefMI and UseMI.
198  bool SawStore = true;
199  if (!DefMI->isSafeToMove(nullptr, SawStore))
200  return false;
201 
202  DEBUG(dbgs() << "Try to fold single def: " << *DefMI
203  << " into single use: " << *UseMI);
204 
206  if (UseMI->readsWritesVirtualRegister(LI->reg, &Ops).second)
207  return false;
208 
209  MachineInstr *FoldMI = TII.foldMemoryOperand(UseMI, Ops, DefMI);
210  if (!FoldMI)
211  return false;
212  DEBUG(dbgs() << " folded: " << *FoldMI);
213  LIS.ReplaceMachineInstrInMaps(UseMI, FoldMI);
214  UseMI->eraseFromParent();
215  DefMI->addRegisterDead(LI->reg, nullptr);
216  Dead.push_back(DefMI);
217  ++NumDCEFoldedLoads;
218  return true;
219 }
220 
221 bool LiveRangeEdit::useIsKill(const LiveInterval &LI,
222  const MachineOperand &MO) const {
223  const MachineInstr *MI = MO.getParent();
224  SlotIndex Idx = LIS.getInstructionIndex(MI).getRegSlot();
225  if (LI.Query(Idx).isKill())
226  return true;
227  const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
228  unsigned SubReg = MO.getSubReg();
229  unsigned LaneMask = TRI.getSubRegIndexLaneMask(SubReg);
230  for (const LiveInterval::SubRange &S : LI.subranges()) {
231  if ((S.LaneMask & LaneMask) != 0 && S.Query(Idx).isKill())
232  return true;
233  }
234  return false;
235 }
236 
237 /// Find all live intervals that need to shrink, then remove the instruction.
238 void LiveRangeEdit::eliminateDeadDef(MachineInstr *MI, ToShrinkSet &ToShrink) {
239  assert(MI->allDefsAreDead() && "Def isn't really dead");
240  SlotIndex Idx = LIS.getInstructionIndex(MI).getRegSlot();
241 
242  // Never delete a bundled instruction.
243  if (MI->isBundled()) {
244  return;
245  }
246  // Never delete inline asm.
247  if (MI->isInlineAsm()) {
248  DEBUG(dbgs() << "Won't delete: " << Idx << '\t' << *MI);
249  return;
250  }
251 
252  // Use the same criteria as DeadMachineInstructionElim.
253  bool SawStore = false;
254  if (!MI->isSafeToMove(nullptr, SawStore)) {
255  DEBUG(dbgs() << "Can't delete: " << Idx << '\t' << *MI);
256  return;
257  }
258 
259  DEBUG(dbgs() << "Deleting dead def " << Idx << '\t' << *MI);
260 
261  // Collect virtual registers to be erased after MI is gone.
262  SmallVector<unsigned, 8> RegsToErase;
263  bool ReadsPhysRegs = false;
264 
265  // Check for live intervals that may shrink
267  MOE = MI->operands_end(); MOI != MOE; ++MOI) {
268  if (!MOI->isReg())
269  continue;
270  unsigned Reg = MOI->getReg();
272  // Check if MI reads any unreserved physregs.
273  if (Reg && MOI->readsReg() && !MRI.isReserved(Reg))
274  ReadsPhysRegs = true;
275  else if (MOI->isDef())
276  LIS.removePhysRegDefAt(Reg, Idx);
277  continue;
278  }
279  LiveInterval &LI = LIS.getInterval(Reg);
280 
281  // Shrink read registers, unless it is likely to be expensive and
282  // unlikely to change anything. We typically don't want to shrink the
283  // PIC base register that has lots of uses everywhere.
284  // Always shrink COPY uses that probably come from live range splitting.
285  if ((MI->readsVirtualRegister(Reg) && (MI->isCopy() || MOI->isDef())) ||
286  (MOI->readsReg() && (MRI.hasOneNonDBGUse(Reg) || useIsKill(LI, *MOI))))
287  ToShrink.insert(&LI);
288 
289  // Remove defined value.
290  if (MOI->isDef()) {
291  if (TheDelegate && LI.getVNInfoAt(Idx) != nullptr)
292  TheDelegate->LRE_WillShrinkVirtReg(LI.reg);
293  LIS.removeVRegDefAt(LI, Idx);
294  if (LI.empty())
295  RegsToErase.push_back(Reg);
296  }
297  }
298 
299  // Currently, we don't support DCE of physreg live ranges. If MI reads
300  // any unreserved physregs, don't erase the instruction, but turn it into
301  // a KILL instead. This way, the physreg live ranges don't end up
302  // dangling.
303  // FIXME: It would be better to have something like shrinkToUses() for
304  // physregs. That could potentially enable more DCE and it would free up
305  // the physreg. It would not happen often, though.
306  if (ReadsPhysRegs) {
307  MI->setDesc(TII.get(TargetOpcode::KILL));
308  // Remove all operands that aren't physregs.
309  for (unsigned i = MI->getNumOperands(); i; --i) {
310  const MachineOperand &MO = MI->getOperand(i-1);
312  continue;
313  MI->RemoveOperand(i-1);
314  }
315  DEBUG(dbgs() << "Converted physregs to:\t" << *MI);
316  } else {
317  if (TheDelegate)
318  TheDelegate->LRE_WillEraseInstruction(MI);
320  MI->eraseFromParent();
321  ++NumDCEDeleted;
322  }
323 
324  // Erase any virtregs that are now empty and unused. There may be <undef>
325  // uses around. Keep the empty live range in that case.
326  for (unsigned i = 0, e = RegsToErase.size(); i != e; ++i) {
327  unsigned Reg = RegsToErase[i];
328  if (LIS.hasInterval(Reg) && MRI.reg_nodbg_empty(Reg)) {
329  ToShrink.remove(&LIS.getInterval(Reg));
330  eraseVirtReg(Reg);
331  }
332  }
333 }
334 
336  ArrayRef<unsigned> RegsBeingSpilled) {
337  ToShrinkSet ToShrink;
338 
339  for (;;) {
340  // Erase all dead defs.
341  while (!Dead.empty())
342  eliminateDeadDef(Dead.pop_back_val(), ToShrink);
343 
344  if (ToShrink.empty())
345  break;
346 
347  // Shrink just one live interval. Then delete new dead defs.
348  LiveInterval *LI = ToShrink.back();
349  ToShrink.pop_back();
350  if (foldAsLoad(LI, Dead))
351  continue;
352  if (TheDelegate)
353  TheDelegate->LRE_WillShrinkVirtReg(LI->reg);
354  if (!LIS.shrinkToUses(LI, &Dead))
355  continue;
356 
357  // Don't create new intervals for a register being spilled.
358  // The new intervals would have to be spilled anyway so its not worth it.
359  // Also they currently aren't spilled so creating them and not spilling
360  // them results in incorrect code.
361  bool BeingSpilled = false;
362  for (unsigned i = 0, e = RegsBeingSpilled.size(); i != e; ++i) {
363  if (LI->reg == RegsBeingSpilled[i]) {
364  BeingSpilled = true;
365  break;
366  }
367  }
368 
369  if (BeingSpilled) continue;
370 
371  // LI may have been separated, create new intervals.
372  LI->RenumberValues();
373  ConnectedVNInfoEqClasses ConEQ(LIS);
374  unsigned NumComp = ConEQ.Classify(LI);
375  if (NumComp <= 1)
376  continue;
377  ++NumFracRanges;
378  bool IsOriginal = VRM && VRM->getOriginal(LI->reg) == LI->reg;
379  DEBUG(dbgs() << NumComp << " components: " << *LI << '\n');
380  SmallVector<LiveInterval*, 8> Dups(1, LI);
381  for (unsigned i = 1; i != NumComp; ++i) {
383  // If LI is an original interval that hasn't been split yet, make the new
384  // intervals their own originals instead of referring to LI. The original
385  // interval must contain all the split products, and LI doesn't.
386  if (IsOriginal)
387  VRM->setIsSplitFromReg(Dups.back()->reg, 0);
388  if (TheDelegate)
389  TheDelegate->LRE_DidCloneVirtReg(Dups.back()->reg, LI->reg);
390  }
391  ConEQ.Distribute(&Dups[0], MRI);
392  DEBUG({
393  for (unsigned i = 0; i != NumComp; ++i)
394  dbgs() << '\t' << *Dups[i] << '\n';
395  });
396  }
397 }
398 
399 // Keep track of new virtual registers created via
400 // MachineRegisterInfo::createVirtualRegister.
401 void
402 LiveRangeEdit::MRI_NoteNewVirtualRegister(unsigned VReg)
403 {
404  if (VRM)
405  VRM->grow();
406 
407  NewRegs.push_back(VReg);
408 }
409 
410 void
412  const MachineLoopInfo &Loops,
413  const MachineBlockFrequencyInfo &MBFI) {
414  VirtRegAuxInfo VRAI(MF, LIS, Loops, MBFI);
415  for (unsigned I = 0, Size = size(); I < Size; ++I) {
416  LiveInterval &LI = LIS.getInterval(get(I));
417  if (MRI.recomputeRegClass(LI.reg))
418  DEBUG({
419  const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
420  dbgs() << "Inflated " << PrintReg(LI.reg) << " to "
421  << TRI->getRegClassName(MRI.getRegClass(LI.reg)) << '\n';
422  });
424  }
425 }
bool isConstantPhysReg(unsigned PhysReg, const MachineFunction &MF) const
isConstantPhysReg - Returns true if PhysReg is unallocatable and constant throughout the function...
void RenumberValues()
RenumberValues - Renumber all values in order of appearance and remove unused values.
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
mop_iterator operands_end()
Definition: MachineInstr.h:290
Calculate auxiliary information for a virtual register such as its spill weight and allocation hint...
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
const unsigned reg
Definition: LiveInterval.h:616
SlotIndex def
The index of the defining instruction.
Definition: LiveInterval.h:53
STATISTIC(NumFunctions,"Total number of functions")
bool anyRematerializable(AliasAnalysis *)
anyRematerializable - Return true if any parent values may be rematerializable.
void removePhysRegDefAt(unsigned Reg, SlotIndex Pos)
Remove value numbers and related live segments starting at position Pos that are part of any liverang...
bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:588
SlotIndex getInstructionIndex(const MachineInstr *instr) const
Returns the base index of the given instruction.
static bool isVirtualRegister(unsigned Reg)
isVirtualRegister - Return true if the specified register number is in the virtual register namespace...
bool readsVirtualRegister(unsigned Reg) const
Return true if the MachineInstr reads the specified virtual register.
Definition: MachineInstr.h:844
MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...
bool isKill() const
Return true if the live-in value is killed by this instruction.
Definition: LiveInterval.h:108
A live range for subregisters.
Definition: LiveInterval.h:595
virtual void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SubIdx, const MachineInstr *Orig, const TargetRegisterInfo &TRI) const
Re-issue the specified 'original' instruction at the specific location targeting a new destination re...
bool canFoldAsLoad(QueryType Type=IgnoreBundle) const
Return true for instructions that can be folded as memory operands in other instructions.
Definition: MachineInstr.h:512
VNInfo - Value Number Information.
Definition: LiveInterval.h:45
bool empty() const
Definition: LiveInterval.h:353
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
Definition: LiveInterval.h:392
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
bool checkRematerializable(VNInfo *VNI, const MachineInstr *DefMI, AliasAnalysis *)
checkRematerializable - Manually add VNI to the list of rematerializable values if DefMI may be remat...
Hexagon Hardware Loops
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const TargetRegisterInfo * getTargetRegisterInfo() const
globalsmodref aa
T LLVM_ATTRIBUTE_UNUSED_RESULT pop_back_val()
Definition: SmallVector.h:406
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APInt.h:33
bool isReg() const
isReg - Tests if this is a MO_Register operand.
iterator_range< subrange_iterator > subranges()
Definition: LiveInterval.h:670
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
const TargetRegisterClass * getRegClass(unsigned Reg) const
getRegClass - Return the register class of the specified virtual register.
Reg
All possible values of the reg field in the ModR/M byte.
bool isUndef() const
unsigned Classify(const LiveInterval *LI)
Classify - Classify the values in LI into connected components.
void pop_back()
Remove the last element of the SetVector.
Definition: SetVector.h:167
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:271
void Distribute(LiveInterval *LIV[], MachineRegisterInfo &MRI)
Distribute - Distribute values in LIV[0] into a separate LiveInterval for each connected component...
PrintReg - Helper class for printing registers on a raw_ostream.
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Definition: SmallVector.h:57
void setIsSplitFromReg(unsigned virtReg, unsigned SReg)
records virtReg is a split live interval from SReg.
Definition: VirtRegMap.h:138
bool isBundled() const
Return true if this instruction part of a bundle.
Definition: MachineInstr.h:211
bool shrinkToUses(LiveInterval *li, SmallVectorImpl< MachineInstr * > *dead=nullptr)
shrinkToUses - After removing some uses of a register, shrink its live range to just the remaining us...
bool empty() const
Determine if the SetVector is empty or not.
Definition: SetVector.h:59
const char * getRegClassName(const TargetRegisterClass *Class) const
getRegClassName - Returns the name of the register class.
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:134
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:120
bundle_iterator< MachineInstr, instr_iterator > iterator
void RemoveMachineInstrFromMaps(MachineInstr *MI)
unsigned createFrom(unsigned OldReg)
createFrom - Create a new virtual register based on OldReg.
SlotIndexes * getSlotIndexes() const
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
Definition: LiveInterval.h:493
void removeInterval(unsigned Reg)
virtual bool isAsCheapAsAMove(const MachineInstr *MI) const
Return true if the instruction is as cheap as a move instruction.
unsigned getSubRegIndexLaneMask(unsigned SubIdx) const
getSubRegIndexLaneMask - Return a bitmask representing the parts of a register that are covered by Su...
unsigned getOriginal(unsigned VirtReg) const
getOriginal - Return the original virtual register that VirtReg descends from through splitting...
Definition: VirtRegMap.h:151
bool isReserved(unsigned PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
bool isCopy() const
Definition: MachineInstr.h:778
virtual bool LRE_CanEraseVirtReg(unsigned)
Called when a virtual register is no longer used.
Definition: LiveRangeEdit.h:48
bool canRematerializeAt(Remat &RM, SlotIndex UseIdx, bool cheapAsAMove)
canRematerializeAt - Determine if ParentVNI can be rematerialized at UseIdx.
LiveInterval & getParent() const
virtual void LRE_WillEraseInstruction(MachineInstr *MI)
Called immediately before erasing a dead machine instruction.
Definition: LiveRangeEdit.h:44
unsigned getSubReg() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
Definition: SlotIndexes.h:206
ConnectedVNInfoEqClasses - Helper class that can divide VNInfos in a LiveInterval into equivalence cl...
Definition: LiveInterval.h:841
MachineOperand class - Representation of each machine instruction operand.
bool isInlineAsm() const
Definition: MachineInstr.h:760
void calculateSpillWeightAndHint(LiveInterval &li)
(re)compute li's spill weight and allocation hint.
bool isTriviallyReMaterializable(const MachineInstr *MI, AliasAnalysis *AA=nullptr) const
Return true if the instruction is trivially rematerializable, meaning it has no side effects and requ...
LiveInterval & getInterval(unsigned Reg)
bool recomputeRegClass(unsigned Reg)
recomputeRegClass - Try to find a legal super-class of Reg's register class that still satisfies the ...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:123
MachineInstr * foldMemoryOperand(MachineBasicBlock::iterator MI, ArrayRef< unsigned > Ops, int FrameIndex) const
Attempt to fold a load or store of the specified stack slot into the specified machine instruction fo...
LiveInterval & createEmptyInterval(unsigned Reg)
virtual void LRE_WillShrinkVirtReg(unsigned)
Called before shrinking the live range of a virtual register.
Definition: LiveRangeEdit.h:51
KILL - This instruction is a noop that is used only to adjust the liveness of registers.
Definition: TargetOpcodes.h:35
void ReplaceMachineInstrInMaps(MachineInstr *MI, MachineInstr *NewMI)
Representation of each machine instruction.
Definition: MachineInstr.h:51
static bool isPhysicalRegister(unsigned Reg)
isPhysicalRegister - Return true if the specified register number is in the physical register namespa...
SlotIndex rematerializeAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, const Remat &RM, const TargetRegisterInfo &, bool Late=false)
rematerializeAt - Rematerialize RM.ParentVNI into DestReg by inserting an instruction into MBB before...
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
#define I(x, y, z)
Definition: MD5.cpp:54
virtual void LRE_DidCloneVirtReg(unsigned New, unsigned Old)
Called after cloning a virtual register.
Definition: LiveRangeEdit.h:55
const T & back() const
Return the last element of the SetVector.
Definition: SetVector.h:89
bool hasInterval(unsigned Reg) const
Remat - Information needed to rematerialize at a specific location.
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def...
Definition: SlotIndexes.h:257
unsigned getReg() const
getReg - Returns the register number.
iterator_range< reg_nodbg_iterator > reg_nodbg_operands(unsigned Reg) const
void eliminateDeadDefs(SmallVectorImpl< MachineInstr * > &Dead, ArrayRef< unsigned > RegsBeingSpilled=None)
eliminateDeadDefs - Try to delete machine instructions that are now dead (allDefsAreDead returns true...
mop_iterator operands_begin()
Definition: MachineInstr.h:289
LiveInterval & createEmptyIntervalFrom(unsigned OldReg)
createEmptyIntervalFrom - Create a new empty interval based on OldReg.
A vector that has set insertion semantics.
Definition: SetVector.h:37
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
#define DEBUG(X)
Definition: Debug.h:92
void calculateRegClassAndHint(MachineFunction &, const MachineLoopInfo &, const MachineBlockFrequencyInfo &)
calculateRegClassAndHint - Recompute register class and hint for each new register.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
void eraseVirtReg(unsigned Reg)
eraseVirtReg - Notify the delegate that Reg is no longer in use, and try to erase it from LIS...
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register. ...
unsigned size() const
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:92
SlotIndex insertMachineInstrInMaps(MachineInstr *mi, bool Late=false)
Insert the given machine instruction into the mapping.
Definition: SlotIndexes.h:569
bool reg_nodbg_empty(unsigned RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions...
void removeVRegDefAt(LiveInterval &LI, SlotIndex Pos)
Remove value number and related live segments of LI and its subranges that start at position Pos...