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LLVM
3.7.0
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#include <AMDGPUInstrInfo.h>
Protected Member Functions | |
| MachineInstr * | foldMemoryOperandImpl (MachineFunction &MF, MachineInstr *MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex) const override |
| MachineInstr * | foldMemoryOperandImpl (MachineFunction &MF, MachineInstr *MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr *LoadMI) const override |
Protected Attributes | |
| const AMDGPUSubtarget & | ST |
Definition at line 40 of file AMDGPUInstrInfo.h.
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explicit |
Definition at line 33 of file AMDGPUInstrInfo.cpp.
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pure virtual |
Build instruction(s) for an indirect register read.
Implemented in llvm::SIInstrInfo, and llvm::R600InstrInfo.
Referenced by expandPostRAPseudo().
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pure virtual |
Build instruction(s) for an indirect register write.
Implemented in llvm::SIInstrInfo, and llvm::R600InstrInfo.
Referenced by expandPostRAPseudo().
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pure virtual |
Build a MOV instruction.
Implemented in llvm::R600InstrInfo, and llvm::SIInstrInfo.
Referenced by expandPostRAPseudo().
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pure virtual |
Calculate the "Indirect Address" for the given RegIndex and Channel.
We model indirect addressing using a virtual address space that can be accesed with loads and stores. The "Indirect Address" is the memory address in this virtual address space that maps to the given RegIndex and Channel.
Implemented in llvm::SIInstrInfo, and llvm::R600InstrInfo.
Referenced by expandPostRAPseudo().
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Definition at line 167 of file AMDGPUInstrInfo.cpp.
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override |
Definition at line 83 of file AMDGPUInstrInfo.cpp.
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Definition at line 244 of file AMDGPUInstrInfo.cpp.
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override |
Definition at line 196 of file AMDGPUInstrInfo.cpp.
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override |
Definition at line 109 of file AMDGPUInstrInfo.cpp.
References addr, llvm::dwarf::syntax::Address, buildIndirectRead(), buildIndirectWrite(), buildMovInstr(), calculateIndirectAddress(), llvm::MachineBasicBlock::erase(), getIndirectAddrRegClass(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineBasicBlock::getParent(), llvm::TargetRegisterClass::getRegister(), isRegisterLoad(), and isRegisterStore().
Referenced by llvm::SIInstrInfo::expandPostRAPseudo(), and llvm::R600InstrInfo::expandPostRAPseudo().
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overrideprotected |
Definition at line 155 of file AMDGPUInstrInfo.cpp.
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overrideprotected |
Definition at line 161 of file AMDGPUInstrInfo.cpp.
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pure virtual |
Implemented in llvm::SIInstrInfo, and llvm::R600InstrInfo.
Referenced by expandPostRAPseudo(), and getIndirectIndexBegin().
| int AMDGPUInstrInfo::getIndirectIndexBegin | ( | const MachineFunction & | MF | ) | const |
Definition at line 269 of file AMDGPUInstrInfo.cpp.
References llvm::TargetRegisterClass::contains(), llvm::MachineFunction::getFrameInfo(), getIndirectAddrRegClass(), llvm::MachineFrameInfo::getNumObjects(), llvm::TargetRegisterClass::getNumRegs(), llvm::MachineFunction::getRegInfo(), llvm::TargetRegisterClass::getRegister(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::AArch64CC::LE, llvm::MachineRegisterInfo::livein_begin(), llvm::MachineRegisterInfo::livein_empty(), and llvm::MachineRegisterInfo::livein_end().
Referenced by llvm::SIInstrInfo::buildIndirectRead(), llvm::SIInstrInfo::buildIndirectWrite(), getIndirectIndexEnd(), llvm::R600InstrInfo::reserveIndirectRegisters(), and llvm::SIInstrInfo::reserveIndirectRegisters().
| int AMDGPUInstrInfo::getIndirectIndexEnd | ( | const MachineFunction & | MF | ) | const |
Definition at line 304 of file AMDGPUInstrInfo.cpp.
References llvm::TargetFrameLowering::getFrameIndexOffset(), llvm::MachineFunction::getFrameInfo(), llvm::TargetSubtargetInfo::getFrameLowering(), getIndirectIndexBegin(), llvm::MachineFrameInfo::getNumObjects(), llvm::MachineFunction::getSubtarget(), and llvm::MachineFrameInfo::hasVarSizedObjects().
Referenced by llvm::R600InstrInfo::reserveIndirectRegisters(), and llvm::SIInstrInfo::reserveIndirectRegisters().
Given a MIMG Opcode that writes all 4 channels, return the equivalent opcode that writes Channels Channels.
Definition at line 320 of file AMDGPUInstrInfo.cpp.
Referenced by llvm::SITargetLowering::AdjustInstrPostInstrSelection().
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inline |
Return the descriptor of the target-specific machine instruction that corresponds to the specified pseudo or native opcode.
Definition at line 146 of file AMDGPUInstrInfo.h.
References pseudoToMCOpcode().
Referenced by llvm::SIRegisterInfo::eliminateFrameIndex().
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override |
Definition at line 189 of file AMDGPUInstrInfo.cpp.
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pure virtual |
Implemented in llvm::SIInstrInfo, and llvm::R600InstrInfo.
Definition at line 36 of file AMDGPUInstrInfo.cpp.
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override |
Definition at line 59 of file AMDGPUInstrInfo.cpp.
| bool AMDGPUInstrInfo::hasStoreFromStackSlot | ( | const MachineInstr * | MI, |
| const MachineMemOperand *& | MMO, | ||
| int & | FrameIndex | ||
| ) | const |
Definition at line 75 of file AMDGPUInstrInfo.cpp.
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Definition at line 228 of file AMDGPUInstrInfo.cpp.
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override |
Definition at line 40 of file AMDGPUInstrInfo.cpp.
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Definition at line 47 of file AMDGPUInstrInfo.cpp.
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Definition at line 53 of file AMDGPUInstrInfo.cpp.
Implemented in llvm::R600InstrInfo, and llvm::SIInstrInfo.
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override |
Definition at line 250 of file AMDGPUInstrInfo.cpp.
References llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::isPredicable().
Referenced by llvm::R600InstrInfo::isPredicable().
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override |
Definition at line 233 of file AMDGPUInstrInfo.cpp.
| bool AMDGPUInstrInfo::isRegisterLoad | ( | const MachineInstr & | MI | ) | const |
Definition at line 265 of file AMDGPUInstrInfo.cpp.
References AMDGPU_FLAG_REGISTER_LOAD, and llvm::MachineInstr::getOpcode().
Referenced by expandPostRAPseudo().
| bool AMDGPUInstrInfo::isRegisterStore | ( | const MachineInstr & | MI | ) | const |
Definition at line 261 of file AMDGPUInstrInfo.cpp.
References AMDGPU_FLAG_REGISTER_STORE, and llvm::MachineInstr::getOpcode().
Referenced by expandPostRAPseudo().
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override |
Definition at line 256 of file AMDGPUInstrInfo.cpp.
| unsigned AMDGPUInstrInfo::isStoreFromStackSlot | ( | const MachineInstr * | MI, |
| int & | FrameIndex | ||
| ) | const |
Definition at line 65 of file AMDGPUInstrInfo.cpp.
| unsigned AMDGPUInstrInfo::isStoreFromStackSlotPostFE | ( | const MachineInstr * | MI, |
| int & | FrameIndex | ||
| ) | const |
Definition at line 70 of file AMDGPUInstrInfo.cpp.
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override |
Definition at line 101 of file AMDGPUInstrInfo.cpp.
References llvm_unreachable.
Return a target-specific opcode if Opcode is a pseudo instruction.
Return -1 if the target-specific opcode for the pseudo instruction does not exist. If Opcode is not a pseudo instruction, this is identity.
Definition at line 355 of file AMDGPUInstrInfo.cpp.
References AMDGPUSubtargetToSISubtarget(), llvm::AMDGPUSubtarget::getGeneration(), llvm::AMDGPU::getMCOpcode(), and ST.
Referenced by llvm::SIInstrInfo::commuteOpcode(), getMCOpcodeFromPseudo(), llvm::SIInstrInfo::hasVALU32BitEncoding(), and llvm::AMDGPUMCInstLower::lower().
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Definition at line 223 of file AMDGPUInstrInfo.cpp.
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Definition at line 210 of file AMDGPUInstrInfo.cpp.
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Definition at line 91 of file AMDGPUInstrInfo.cpp.
References llvm_unreachable.
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Definition at line 238 of file AMDGPUInstrInfo.cpp.
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Definition at line 173 of file AMDGPUInstrInfo.cpp.
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override |
Definition at line 182 of file AMDGPUInstrInfo.cpp.
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protected |
Definition at line 45 of file AMDGPUInstrInfo.h.
Referenced by llvm::R600InstrInfo::buildSlotOfVectorInstruction(), llvm::SIInstrInfo::calculateLDSSpillAddress(), llvm::SIInstrInfo::getDefaultRsrcDataFormat(), llvm::R600InstrInfo::isTransOnly(), llvm::SIInstrInfo::loadRegFromStackSlot(), llvm::SIInstrInfo::moveToVALU(), pseudoToMCOpcode(), llvm::SIInstrInfo::storeRegToStackSlot(), llvm::R600InstrInfo::usesTextureCache(), and llvm::R600InstrInfo::usesVertexCache().
1.8.6