LLVM  3.7.0
HexagonVLIWPacketizer.cpp
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1 //===----- HexagonPacketizer.cpp - vliw packetizer ---------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This implements a simple VLIW packetizer using DFA. The packetizer works on
11 // machine basic blocks. For each instruction I in BB, the packetizer consults
12 // the DFA to see if machine resources are available to execute I. If so, the
13 // packetizer checks if I depends on any instruction J in the current packet.
14 // If no dependency is found, I is added to current packet and machine resource
15 // is marked as taken. If any dependency is found, a target API call is made to
16 // prune the dependence.
17 //
18 //===----------------------------------------------------------------------===//
20 #include "Hexagon.h"
22 #include "HexagonRegisterInfo.h"
23 #include "HexagonSubtarget.h"
24 #include "HexagonTargetMachine.h"
25 #include "llvm/ADT/DenseMap.h"
26 #include "llvm/ADT/Statistic.h"
35 #include "llvm/CodeGen/Passes.h"
42 #include "llvm/Support/Compiler.h"
43 #include "llvm/Support/Debug.h"
48 #include <map>
49 #include <vector>
50 
51 using namespace llvm;
52 
53 #define DEBUG_TYPE "packets"
54 
55 static cl::opt<bool> PacketizeVolatiles("hexagon-packetize-volatiles",
57  cl::desc("Allow non-solo packetization of volatile memory references"));
58 
59 namespace llvm {
62 }
63 
64 
65 namespace {
66  class HexagonPacketizer : public MachineFunctionPass {
67 
68  public:
69  static char ID;
70  HexagonPacketizer() : MachineFunctionPass(ID) {
72  }
73 
74  void getAnalysisUsage(AnalysisUsage &AU) const override {
75  AU.setPreservesCFG();
82  }
83 
84  const char *getPassName() const override {
85  return "Hexagon Packetizer";
86  }
87 
88  bool runOnMachineFunction(MachineFunction &Fn) override;
89  };
90  char HexagonPacketizer::ID = 0;
91 
92  class HexagonPacketizerList : public VLIWPacketizerList {
93 
94  private:
95 
96  // Has the instruction been promoted to a dot-new instruction.
97  bool PromotedToDotNew;
98 
99  // Has the instruction been glued to allocframe.
100  bool GlueAllocframeStore;
101 
102  // Has the feeder instruction been glued to new value jump.
103  bool GlueToNewValueJump;
104 
105  // Check if there is a dependence between some instruction already in this
106  // packet and this instruction.
107  bool Dependence;
108 
109  // Only check for dependence if there are resources available to
110  // schedule this instruction.
111  bool FoundSequentialDependence;
112 
113  /// \brief A handle to the branch probability pass.
114  const MachineBranchProbabilityInfo *MBPI;
115 
116  // Track MIs with ignored dependece.
117  std::vector<MachineInstr*> IgnoreDepMIs;
118 
119  public:
120  // Ctor.
121  HexagonPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI,
122  const MachineBranchProbabilityInfo *MBPI);
123 
124  // initPacketizerState - initialize some internal flags.
125  void initPacketizerState() override;
126 
127  // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
128  bool ignorePseudoInstruction(MachineInstr *MI,
129  MachineBasicBlock *MBB) override;
130 
131  // isSoloInstruction - return true if instruction MI can not be packetized
132  // with any other instruction, which means that MI itself is a packet.
133  bool isSoloInstruction(MachineInstr *MI) override;
134 
135  // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
136  // together.
137  bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) override;
138 
139  // isLegalToPruneDependencies - Is it legal to prune dependece between SUI
140  // and SUJ.
141  bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) override;
142 
143  MachineBasicBlock::iterator addToPacket(MachineInstr *MI) override;
144  private:
145  bool IsCallDependent(MachineInstr* MI, SDep::Kind DepType, unsigned DepReg);
146  bool PromoteToDotNew(MachineInstr* MI, SDep::Kind DepType,
148  const TargetRegisterClass* RC);
149  bool CanPromoteToDotNew(MachineInstr *MI, SUnit *PacketSU, unsigned DepReg,
150  const std::map<MachineInstr *, SUnit *> &MIToSUnit,
152  const TargetRegisterClass *RC);
153  bool
154  CanPromoteToNewValue(MachineInstr *MI, SUnit *PacketSU, unsigned DepReg,
155  const std::map<MachineInstr *, SUnit *> &MIToSUnit,
157  bool CanPromoteToNewValueStore(
158  MachineInstr *MI, MachineInstr *PacketMI, unsigned DepReg,
159  const std::map<MachineInstr *, SUnit *> &MIToSUnit);
160  bool DemoteToDotOld(MachineInstr *MI);
161  bool ArePredicatesComplements(
162  MachineInstr *MI1, MachineInstr *MI2,
163  const std::map<MachineInstr *, SUnit *> &MIToSUnit);
164  bool RestrictingDepExistInPacket(MachineInstr *, unsigned,
165  const std::map<MachineInstr *, SUnit *> &);
166  bool isNewifiable(MachineInstr* MI);
167  bool isCondInst(MachineInstr* MI);
168  bool tryAllocateResourcesForConstExt(MachineInstr* MI);
169  bool canReserveResourcesForConstExt(MachineInstr *MI);
170  void reserveResourcesForConstExt(MachineInstr* MI);
171  bool isNewValueInst(MachineInstr* MI);
172  };
173 }
174 
175 INITIALIZE_PASS_BEGIN(HexagonPacketizer, "packets", "Hexagon Packetizer",
176  false, false)
181 INITIALIZE_PASS_END(HexagonPacketizer, "packets", "Hexagon Packetizer",
182  false, false)
183 
184 
185 // HexagonPacketizerList Ctor.
186 HexagonPacketizerList::HexagonPacketizerList(
189  : VLIWPacketizerList(MF, MLI, true) {
190  this->MBPI = MBPI;
191 }
192 
193 bool HexagonPacketizer::runOnMachineFunction(MachineFunction &Fn) {
195  MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
196  const MachineBranchProbabilityInfo *MBPI =
197  &getAnalysis<MachineBranchProbabilityInfo>();
198  // Instantiate the packetizer.
199  HexagonPacketizerList Packetizer(Fn, MLI, MBPI);
200 
201  // DFA state table should not be empty.
202  assert(Packetizer.getResourceTracker() && "Empty DFA table!");
203 
204  //
205  // Loop over all basic blocks and remove KILL pseudo-instructions
206  // These instructions confuse the dependence analysis. Consider:
207  // D0 = ... (Insn 0)
208  // R0 = KILL R0, D0 (Insn 1)
209  // R0 = ... (Insn 2)
210  // Here, Insn 1 will result in the dependence graph not emitting an output
211  // dependence between Insn 0 and Insn 2. This can lead to incorrect
212  // packetization
213  //
214  for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
215  MBB != MBBe; ++MBB) {
216  MachineBasicBlock::iterator End = MBB->end();
217  MachineBasicBlock::iterator MI = MBB->begin();
218  while (MI != End) {
219  if (MI->isKill()) {
220  MachineBasicBlock::iterator DeleteMI = MI;
221  ++MI;
222  MBB->erase(DeleteMI);
223  End = MBB->end();
224  continue;
225  }
226  ++MI;
227  }
228  }
229 
230  // Loop over all of the basic blocks.
231  for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
232  MBB != MBBe; ++MBB) {
233  // Find scheduling regions and schedule / packetize each region.
234  unsigned RemainingCount = MBB->size();
235  for(MachineBasicBlock::iterator RegionEnd = MBB->end();
236  RegionEnd != MBB->begin();) {
237  // The next region starts above the previous region. Look backward in the
238  // instruction stream until we find the nearest boundary.
239  MachineBasicBlock::iterator I = RegionEnd;
240  for(;I != MBB->begin(); --I, --RemainingCount) {
241  if (TII->isSchedulingBoundary(std::prev(I), MBB, Fn))
242  break;
243  }
244  I = MBB->begin();
245 
246  // Skip empty scheduling regions.
247  if (I == RegionEnd) {
248  RegionEnd = std::prev(RegionEnd);
249  --RemainingCount;
250  continue;
251  }
252  // Skip regions with one instruction.
253  if (I == std::prev(RegionEnd)) {
254  RegionEnd = std::prev(RegionEnd);
255  continue;
256  }
257 
258  Packetizer.PacketizeMIs(MBB, I, RegionEnd);
259  RegionEnd = I;
260  }
261  }
262 
263  return true;
264 }
265 
266 
267 static bool IsIndirectCall(MachineInstr* MI) {
268  return MI->getOpcode() == Hexagon::J2_callr;
269 }
270 
271 // Reserve resources for constant extender. Trigure an assertion if
272 // reservation fail.
273 void HexagonPacketizerList::reserveResourcesForConstExt(MachineInstr* MI) {
274  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
275  MachineInstr *PseudoMI = MF.CreateMachineInstr(QII->get(Hexagon::A4_ext),
276  MI->getDebugLoc());
277 
278  if (ResourceTracker->canReserveResources(PseudoMI)) {
279  ResourceTracker->reserveResources(PseudoMI);
280  MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
281  } else {
282  MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
283  llvm_unreachable("can not reserve resources for constant extender.");
284  }
285  return;
286 }
287 
288 bool HexagonPacketizerList::canReserveResourcesForConstExt(MachineInstr *MI) {
289  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
290  assert((QII->isExtended(MI) || QII->isConstExtended(MI)) &&
291  "Should only be called for constant extended instructions");
292  MachineInstr *PseudoMI = MF.CreateMachineInstr(QII->get(Hexagon::A4_ext),
293  MI->getDebugLoc());
294  bool CanReserve = ResourceTracker->canReserveResources(PseudoMI);
295  MF.DeleteMachineInstr(PseudoMI);
296  return CanReserve;
297 }
298 
299 // Allocate resources (i.e. 4 bytes) for constant extender. If succeed, return
300 // true, otherwise, return false.
301 bool HexagonPacketizerList::tryAllocateResourcesForConstExt(MachineInstr* MI) {
302  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
303  MachineInstr *PseudoMI = MF.CreateMachineInstr(QII->get(Hexagon::A4_ext),
304  MI->getDebugLoc());
305 
306  if (ResourceTracker->canReserveResources(PseudoMI)) {
307  ResourceTracker->reserveResources(PseudoMI);
308  MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
309  return true;
310  } else {
311  MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
312  return false;
313  }
314 }
315 
316 
317 bool HexagonPacketizerList::IsCallDependent(MachineInstr* MI,
318  SDep::Kind DepType,
319  unsigned DepReg) {
320 
321  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
322  const HexagonRegisterInfo *QRI =
323  (const HexagonRegisterInfo *)MF.getSubtarget().getRegisterInfo();
324 
325  // Check for lr dependence
326  if (DepReg == QRI->getRARegister()) {
327  return true;
328  }
329 
330  if (QII->isDeallocRet(MI)) {
331  if (DepReg == QRI->getFrameRegister() ||
332  DepReg == QRI->getStackRegister())
333  return true;
334  }
335 
336  // Check if this is a predicate dependence
337  const TargetRegisterClass* RC = QRI->getMinimalPhysRegClass(DepReg);
338  if (RC == &Hexagon::PredRegsRegClass) {
339  return true;
340  }
341 
342  //
343  // Lastly check for an operand used in an indirect call
344  // If we had an attribute for checking if an instruction is an indirect call,
345  // then we could have avoided this relatively brittle implementation of
346  // IsIndirectCall()
347  //
348  // Assumes that the first operand of the CALLr is the function address
349  //
350  if (IsIndirectCall(MI) && (DepType == SDep::Data)) {
351  MachineOperand MO = MI->getOperand(0);
352  if (MO.isReg() && MO.isUse() && (MO.getReg() == DepReg)) {
353  return true;
354  }
355  }
356 
357  return false;
358 }
359 
360 static bool IsRegDependence(const SDep::Kind DepType) {
361  return (DepType == SDep::Data || DepType == SDep::Anti ||
362  DepType == SDep::Output);
363 }
364 
365 static bool IsDirectJump(MachineInstr* MI) {
366  return (MI->getOpcode() == Hexagon::J2_jump);
367 }
368 
369 static bool IsSchedBarrier(MachineInstr* MI) {
370  switch (MI->getOpcode()) {
371  case Hexagon::Y2_barrier:
372  return true;
373  }
374  return false;
375 }
376 
377 static bool IsControlFlow(MachineInstr* MI) {
378  return (MI->getDesc().isTerminator() || MI->getDesc().isCall());
379 }
380 
381 static bool IsLoopN(MachineInstr *MI) {
382  return (MI->getOpcode() == Hexagon::J2_loop0i ||
383  MI->getOpcode() == Hexagon::J2_loop0r);
384 }
385 
386 /// DoesModifyCalleeSavedReg - Returns true if the instruction modifies a
387 /// callee-saved register.
389  const TargetRegisterInfo *TRI) {
390  for (const MCPhysReg *CSR =
391  TRI->getCalleeSavedRegs(MI->getParent()->getParent());
392  *CSR; ++CSR) {
393  unsigned CalleeSavedReg = *CSR;
394  if (MI->modifiesRegister(CalleeSavedReg, TRI))
395  return true;
396  }
397  return false;
398 }
399 
400 // Returns true if an instruction can be promoted to .new predicate
401 // or new-value store.
402 bool HexagonPacketizerList::isNewifiable(MachineInstr* MI) {
403  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
404  return isCondInst(MI) || QII->mayBeNewStore(MI);
405 }
406 
407 bool HexagonPacketizerList::isCondInst (MachineInstr* MI) {
408  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
409  const MCInstrDesc& TID = MI->getDesc();
410  // bug 5670: until that is fixed,
411  // this portion is disabled.
412  if ( TID.isConditionalBranch() // && !IsRegisterJump(MI)) ||
413  || QII->isConditionalTransfer(MI)
414  || QII->isConditionalALU32(MI)
415  || QII->isConditionalLoad(MI)
416  || QII->isConditionalStore(MI)) {
417  return true;
418  }
419  return false;
420 }
421 
422 
423 // Promote an instructiont to its .new form.
424 // At this time, we have already made a call to CanPromoteToDotNew
425 // and made sure that it can *indeed* be promoted.
426 bool HexagonPacketizerList::PromoteToDotNew(MachineInstr* MI,
428  const TargetRegisterClass* RC) {
429 
430  assert (DepType == SDep::Data);
431  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
432 
433  int NewOpcode;
434  if (RC == &Hexagon::PredRegsRegClass)
435  NewOpcode = QII->GetDotNewPredOp(MI, MBPI);
436  else
437  NewOpcode = QII->GetDotNewOp(MI);
438  MI->setDesc(QII->get(NewOpcode));
439 
440  return true;
441 }
442 
443 bool HexagonPacketizerList::DemoteToDotOld(MachineInstr* MI) {
444  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
445  int NewOpcode = QII->GetDotOldOp(MI->getOpcode());
446  MI->setDesc(QII->get(NewOpcode));
447  return true;
448 }
449 
454 };
455 
456 /// Returns true if an instruction is predicated on p0 and false if it's
457 /// predicated on !p0.
459  const HexagonInstrInfo *QII) {
460  if (!QII->isPredicated(MI))
461  return PK_Unknown;
462 
463  if (QII->isPredicatedTrue(MI))
464  return PK_True;
465 
466  return PK_False;
467 }
468 
470  const HexagonInstrInfo *QII) {
471  assert(QII->isPostIncrement(MI) && "Not a post increment operation.");
472 #ifndef NDEBUG
473  // Post Increment means duplicates. Use dense map to find duplicates in the
474  // list. Caution: Densemap initializes with the minimum of 64 buckets,
475  // whereas there are at most 5 operands in the post increment.
476  DenseMap<unsigned, unsigned> DefRegsSet;
477  for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++)
478  if (MI->getOperand(opNum).isReg() &&
479  MI->getOperand(opNum).isDef()) {
480  DefRegsSet[MI->getOperand(opNum).getReg()] = 1;
481  }
482 
483  for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++)
484  if (MI->getOperand(opNum).isReg() &&
485  MI->getOperand(opNum).isUse()) {
486  if (DefRegsSet[MI->getOperand(opNum).getReg()]) {
487  return MI->getOperand(opNum);
488  }
489  }
490 #else
491  if (MI->getDesc().mayLoad()) {
492  // The 2nd operand is always the post increment operand in load.
493  assert(MI->getOperand(1).isReg() &&
494  "Post increment operand has be to a register.");
495  return (MI->getOperand(1));
496  }
497  if (MI->getDesc().mayStore()) {
498  // The 1st operand is always the post increment operand in store.
499  assert(MI->getOperand(0).isReg() &&
500  "Post increment operand has be to a register.");
501  return (MI->getOperand(0));
502  }
503 #endif
504  // we should never come here.
505  llvm_unreachable("mayLoad or mayStore not set for Post Increment operation");
506 }
507 
508 // get the value being stored
510  // value being stored is always the last operand.
511  return (MI->getOperand(MI->getNumOperands()-1));
512 }
513 
514 // can be new value store?
515 // Following restrictions are to be respected in convert a store into
516 // a new value store.
517 // 1. If an instruction uses auto-increment, its address register cannot
518 // be a new-value register. Arch Spec 5.4.2.1
519 // 2. If an instruction uses absolute-set addressing mode,
520 // its address register cannot be a new-value register.
521 // Arch Spec 5.4.2.1.TODO: This is not enabled as
522 // as absolute-set address mode patters are not implemented.
523 // 3. If an instruction produces a 64-bit result, its registers cannot be used
524 // as new-value registers. Arch Spec 5.4.2.2.
525 // 4. If the instruction that sets a new-value register is conditional, then
526 // the instruction that uses the new-value register must also be conditional,
527 // and both must always have their predicates evaluate identically.
528 // Arch Spec 5.4.2.3.
529 // 5. There is an implied restriction of a packet can not have another store,
530 // if there is a new value store in the packet. Corollary, if there is
531 // already a store in a packet, there can not be a new value store.
532 // Arch Spec: 3.4.4.2
533 bool HexagonPacketizerList::CanPromoteToNewValueStore(
534  MachineInstr *MI, MachineInstr *PacketMI, unsigned DepReg,
535  const std::map<MachineInstr *, SUnit *> &MIToSUnit) {
536  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
537  // Make sure we are looking at the store, that can be promoted.
538  if (!QII->mayBeNewStore(MI))
539  return false;
540 
541  // Make sure there is dependency and can be new value'ed
542  if (GetStoreValueOperand(MI).isReg() &&
543  GetStoreValueOperand(MI).getReg() != DepReg)
544  return false;
545 
546  const HexagonRegisterInfo *QRI =
547  (const HexagonRegisterInfo *)MF.getSubtarget().getRegisterInfo();
548  const MCInstrDesc& MCID = PacketMI->getDesc();
549  // first operand is always the result
550 
551  const TargetRegisterClass* PacketRC = QII->getRegClass(MCID, 0, QRI, MF);
552 
553  // if there is already an store in the packet, no can do new value store
554  // Arch Spec 3.4.4.2.
555  for (std::vector<MachineInstr*>::iterator VI = CurrentPacketMIs.begin(),
556  VE = CurrentPacketMIs.end();
557  (VI != VE); ++VI) {
558  SUnit *PacketSU = MIToSUnit.find(*VI)->second;
559  if (PacketSU->getInstr()->getDesc().mayStore() ||
560  // if we have mayStore = 1 set on ALLOCFRAME and DEALLOCFRAME,
561  // then we don't need this
562  PacketSU->getInstr()->getOpcode() == Hexagon::S2_allocframe ||
563  PacketSU->getInstr()->getOpcode() == Hexagon::L2_deallocframe)
564  return false;
565  }
566 
567  if (PacketRC == &Hexagon::DoubleRegsRegClass) {
568  // new value store constraint: double regs can not feed into new value store
569  // arch spec section: 5.4.2.2
570  return false;
571  }
572 
573  // Make sure it's NOT the post increment register that we are going to
574  // new value.
575  if (QII->isPostIncrement(MI) &&
576  MI->getDesc().mayStore() &&
577  GetPostIncrementOperand(MI, QII).getReg() == DepReg) {
578  return false;
579  }
580 
581  if (QII->isPostIncrement(PacketMI) &&
582  PacketMI->getDesc().mayLoad() &&
583  GetPostIncrementOperand(PacketMI, QII).getReg() == DepReg) {
584  // if source is post_inc, or absolute-set addressing,
585  // it can not feed into new value store
586  // r3 = memw(r2++#4)
587  // memw(r30 + #-1404) = r2.new -> can not be new value store
588  // arch spec section: 5.4.2.1
589  return false;
590  }
591 
592  // If the source that feeds the store is predicated, new value store must
593  // also be predicated.
594  if (QII->isPredicated(PacketMI)) {
595  if (!QII->isPredicated(MI))
596  return false;
597 
598  // Check to make sure that they both will have their predicates
599  // evaluate identically
600  unsigned predRegNumSrc = 0;
601  unsigned predRegNumDst = 0;
602  const TargetRegisterClass* predRegClass = nullptr;
603 
604  // Get predicate register used in the source instruction
605  for(unsigned opNum = 0; opNum < PacketMI->getNumOperands(); opNum++) {
606  if ( PacketMI->getOperand(opNum).isReg())
607  predRegNumSrc = PacketMI->getOperand(opNum).getReg();
608  predRegClass = QRI->getMinimalPhysRegClass(predRegNumSrc);
609  if (predRegClass == &Hexagon::PredRegsRegClass) {
610  break;
611  }
612  }
613  assert ((predRegClass == &Hexagon::PredRegsRegClass ) &&
614  ("predicate register not found in a predicated PacketMI instruction"));
615 
616  // Get predicate register used in new-value store instruction
617  for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++) {
618  if ( MI->getOperand(opNum).isReg())
619  predRegNumDst = MI->getOperand(opNum).getReg();
620  predRegClass = QRI->getMinimalPhysRegClass(predRegNumDst);
621  if (predRegClass == &Hexagon::PredRegsRegClass) {
622  break;
623  }
624  }
625  assert ((predRegClass == &Hexagon::PredRegsRegClass ) &&
626  ("predicate register not found in a predicated MI instruction"));
627 
628  // New-value register producer and user (store) need to satisfy these
629  // constraints:
630  // 1) Both instructions should be predicated on the same register.
631  // 2) If producer of the new-value register is .new predicated then store
632  // should also be .new predicated and if producer is not .new predicated
633  // then store should not be .new predicated.
634  // 3) Both new-value register producer and user should have same predicate
635  // sense, i.e, either both should be negated or both should be none negated.
636 
637  if (( predRegNumDst != predRegNumSrc) ||
638  QII->isDotNewInst(PacketMI) != QII->isDotNewInst(MI) ||
639  getPredicateSense(MI, QII) != getPredicateSense(PacketMI, QII)) {
640  return false;
641  }
642  }
643 
644  // Make sure that other than the new-value register no other store instruction
645  // register has been modified in the same packet. Predicate registers can be
646  // modified by they should not be modified between the producer and the store
647  // instruction as it will make them both conditional on different values.
648  // We already know this to be true for all the instructions before and
649  // including PacketMI. Howerver, we need to perform the check for the
650  // remaining instructions in the packet.
651 
652  std::vector<MachineInstr*>::iterator VI;
653  std::vector<MachineInstr*>::iterator VE;
654  unsigned StartCheck = 0;
655 
656  for (VI=CurrentPacketMIs.begin(), VE = CurrentPacketMIs.end();
657  (VI != VE); ++VI) {
658  SUnit *TempSU = MIToSUnit.find(*VI)->second;
659  MachineInstr* TempMI = TempSU->getInstr();
660 
661  // Following condition is true for all the instructions until PacketMI is
662  // reached (StartCheck is set to 0 before the for loop).
663  // StartCheck flag is 1 for all the instructions after PacketMI.
664  if (TempMI != PacketMI && !StartCheck) // start processing only after
665  continue; // encountering PacketMI
666 
667  StartCheck = 1;
668  if (TempMI == PacketMI) // We don't want to check PacketMI for dependence
669  continue;
670 
671  for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++) {
672  if (MI->getOperand(opNum).isReg() &&
673  TempSU->getInstr()->modifiesRegister(MI->getOperand(opNum).getReg(),
674  QRI))
675  return false;
676  }
677  }
678 
679  // Make sure that for non-POST_INC stores:
680  // 1. The only use of reg is DepReg and no other registers.
681  // This handles V4 base+index registers.
682  // The following store can not be dot new.
683  // Eg. r0 = add(r0, #3)a
684  // memw(r1+r0<<#2) = r0
685  if (!QII->isPostIncrement(MI) &&
686  GetStoreValueOperand(MI).isReg() &&
687  GetStoreValueOperand(MI).getReg() == DepReg) {
688  for(unsigned opNum = 0; opNum < MI->getNumOperands()-1; opNum++) {
689  if (MI->getOperand(opNum).isReg() &&
690  MI->getOperand(opNum).getReg() == DepReg) {
691  return false;
692  }
693  }
694  // 2. If data definition is because of implicit definition of the register,
695  // do not newify the store. Eg.
696  // %R9<def> = ZXTH %R12, %D6<imp-use>, %R12<imp-def>
697  // STrih_indexed %R8, 2, %R12<kill>; mem:ST2[%scevgep343]
698  for(unsigned opNum = 0; opNum < PacketMI->getNumOperands(); opNum++) {
699  if (PacketMI->getOperand(opNum).isReg() &&
700  PacketMI->getOperand(opNum).getReg() == DepReg &&
701  PacketMI->getOperand(opNum).isDef() &&
702  PacketMI->getOperand(opNum).isImplicit()) {
703  return false;
704  }
705  }
706  }
707 
708  // Can be dot new store.
709  return true;
710 }
711 
712 // can this MI to promoted to either
713 // new value store or new value jump
714 bool HexagonPacketizerList::CanPromoteToNewValue(
715  MachineInstr *MI, SUnit *PacketSU, unsigned DepReg,
716  const std::map<MachineInstr *, SUnit *> &MIToSUnit,
718 
719  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
720  if (!QII->mayBeNewStore(MI))
721  return false;
722 
723  MachineInstr *PacketMI = PacketSU->getInstr();
724 
725  // Check to see the store can be new value'ed.
726  if (CanPromoteToNewValueStore(MI, PacketMI, DepReg, MIToSUnit))
727  return true;
728 
729  // Check to see the compare/jump can be new value'ed.
730  // This is done as a pass on its own. Don't need to check it here.
731  return false;
732 }
733 
734 // Check to see if an instruction can be dot new
735 // There are three kinds.
736 // 1. dot new on predicate - V2/V3/V4
737 // 2. dot new on stores NV/ST - V4
738 // 3. dot new on jump NV/J - V4 -- This is generated in a pass.
739 bool HexagonPacketizerList::CanPromoteToDotNew(
740  MachineInstr *MI, SUnit *PacketSU, unsigned DepReg,
741  const std::map<MachineInstr *, SUnit *> &MIToSUnit,
743  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
744  // Already a dot new instruction.
745  if (QII->isDotNewInst(MI) && !QII->mayBeNewStore(MI))
746  return false;
747 
748  if (!isNewifiable(MI))
749  return false;
750 
751  // predicate .new
752  if (RC == &Hexagon::PredRegsRegClass && isCondInst(MI))
753  return true;
754  else if (RC != &Hexagon::PredRegsRegClass &&
755  !QII->mayBeNewStore(MI)) // MI is not a new-value store
756  return false;
757  else {
758  // Create a dot new machine instruction to see if resources can be
759  // allocated. If not, bail out now.
760  int NewOpcode = QII->GetDotNewOp(MI);
761  const MCInstrDesc &desc = QII->get(NewOpcode);
762  DebugLoc dl;
763  MachineInstr *NewMI =
764  MI->getParent()->getParent()->CreateMachineInstr(desc, dl);
765  bool ResourcesAvailable = ResourceTracker->canReserveResources(NewMI);
766  MI->getParent()->getParent()->DeleteMachineInstr(NewMI);
767 
768  if (!ResourcesAvailable)
769  return false;
770 
771  // new value store only
772  // new new value jump generated as a passes
773  if (!CanPromoteToNewValue(MI, PacketSU, DepReg, MIToSUnit, MII)) {
774  return false;
775  }
776  }
777  return true;
778 }
779 
780 // Go through the packet instructions and search for anti dependency
781 // between them and DepReg from MI
782 // Consider this case:
783 // Trying to add
784 // a) %R1<def> = TFRI_cdNotPt %P3, 2
785 // to this packet:
786 // {
787 // b) %P0<def> = OR_pp %P3<kill>, %P0<kill>
788 // c) %P3<def> = TFR_PdRs %R23
789 // d) %R1<def> = TFRI_cdnPt %P3, 4
790 // }
791 // The P3 from a) and d) will be complements after
792 // a)'s P3 is converted to .new form
793 // Anti Dep between c) and b) is irrelevant for this case
794 bool HexagonPacketizerList::RestrictingDepExistInPacket(
795  MachineInstr *MI, unsigned DepReg,
796  const std::map<MachineInstr *, SUnit *> &MIToSUnit) {
797 
798  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
799  SUnit *PacketSUDep = MIToSUnit.find(MI)->second;
800 
801  for (std::vector<MachineInstr*>::iterator VIN = CurrentPacketMIs.begin(),
802  VEN = CurrentPacketMIs.end(); (VIN != VEN); ++VIN) {
803 
804  // We only care for dependencies to predicated instructions
805  if(!QII->isPredicated(*VIN)) continue;
806 
807  // Scheduling Unit for current insn in the packet
808  SUnit *PacketSU = MIToSUnit.find(*VIN)->second;
809 
810  // Look at dependencies between current members of the packet
811  // and predicate defining instruction MI.
812  // Make sure that dependency is on the exact register
813  // we care about.
814  if (PacketSU->isSucc(PacketSUDep)) {
815  for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
816  if ((PacketSU->Succs[i].getSUnit() == PacketSUDep) &&
817  (PacketSU->Succs[i].getKind() == SDep::Anti) &&
818  (PacketSU->Succs[i].getReg() == DepReg)) {
819  return true;
820  }
821  }
822  }
823  }
824 
825  return false;
826 }
827 
828 
829 /// Gets the predicate register of a predicated instruction.
831  const HexagonInstrInfo *QII) {
832  /// We use the following rule: The first predicate register that is a use is
833  /// the predicate register of a predicated instruction.
834 
835  assert(QII->isPredicated(MI) && "Must be predicated instruction");
836 
838  OE = MI->operands_end(); OI != OE; ++OI) {
839  MachineOperand &Op = *OI;
840  if (Op.isReg() && Op.getReg() && Op.isUse() &&
841  Hexagon::PredRegsRegClass.contains(Op.getReg()))
842  return Op.getReg();
843  }
844 
845  llvm_unreachable("Unknown instruction operand layout");
846 
847  return 0;
848 }
849 
850 // Given two predicated instructions, this function detects whether
851 // the predicates are complements
852 bool HexagonPacketizerList::ArePredicatesComplements(
853  MachineInstr *MI1, MachineInstr *MI2,
854  const std::map<MachineInstr *, SUnit *> &MIToSUnit) {
855 
856  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
857 
858  // If we don't know the predicate sense of the instructions bail out early, we
859  // need it later.
860  if (getPredicateSense(MI1, QII) == PK_Unknown ||
861  getPredicateSense(MI2, QII) == PK_Unknown)
862  return false;
863 
864  // Scheduling unit for candidate
865  SUnit *SU = MIToSUnit.find(MI1)->second;
866 
867  // One corner case deals with the following scenario:
868  // Trying to add
869  // a) %R24<def> = TFR_cPt %P0, %R25
870  // to this packet:
871  //
872  // {
873  // b) %R25<def> = TFR_cNotPt %P0, %R24
874  // c) %P0<def> = CMPEQri %R26, 1
875  // }
876  //
877  // On general check a) and b) are complements, but
878  // presence of c) will convert a) to .new form, and
879  // then it is not a complement
880  // We attempt to detect it by analyzing existing
881  // dependencies in the packet
882 
883  // Analyze relationships between all existing members of the packet.
884  // Look for Anti dependecy on the same predicate reg
885  // as used in the candidate
886  for (std::vector<MachineInstr*>::iterator VIN = CurrentPacketMIs.begin(),
887  VEN = CurrentPacketMIs.end(); (VIN != VEN); ++VIN) {
888 
889  // Scheduling Unit for current insn in the packet
890  SUnit *PacketSU = MIToSUnit.find(*VIN)->second;
891 
892  // If this instruction in the packet is succeeded by the candidate...
893  if (PacketSU->isSucc(SU)) {
894  for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
895  // The corner case exist when there is true data
896  // dependency between candidate and one of current
897  // packet members, this dep is on predicate reg, and
898  // there already exist anti dep on the same pred in
899  // the packet.
900  if (PacketSU->Succs[i].getSUnit() == SU &&
901  PacketSU->Succs[i].getKind() == SDep::Data &&
902  Hexagon::PredRegsRegClass.contains(
903  PacketSU->Succs[i].getReg()) &&
904  // Here I know that *VIN is predicate setting instruction
905  // with true data dep to candidate on the register
906  // we care about - c) in the above example.
907  // Now I need to see if there is an anti dependency
908  // from c) to any other instruction in the
909  // same packet on the pred reg of interest
910  RestrictingDepExistInPacket(*VIN,PacketSU->Succs[i].getReg(),
911  MIToSUnit)) {
912  return false;
913  }
914  }
915  }
916  }
917 
918  // If the above case does not apply, check regular
919  // complement condition.
920  // Check that the predicate register is the same and
921  // that the predicate sense is different
922  // We also need to differentiate .old vs. .new:
923  // !p0 is not complimentary to p0.new
924  unsigned PReg1 = getPredicatedRegister(MI1, QII);
925  unsigned PReg2 = getPredicatedRegister(MI2, QII);
926  return ((PReg1 == PReg2) &&
927  Hexagon::PredRegsRegClass.contains(PReg1) &&
928  Hexagon::PredRegsRegClass.contains(PReg2) &&
929  (getPredicateSense(MI1, QII) != getPredicateSense(MI2, QII)) &&
930  (QII->isDotNewInst(MI1) == QII->isDotNewInst(MI2)));
931 }
932 
933 // initPacketizerState - Initialize packetizer flags
934 void HexagonPacketizerList::initPacketizerState() {
935 
936  Dependence = false;
937  PromotedToDotNew = false;
938  GlueToNewValueJump = false;
939  GlueAllocframeStore = false;
940  FoundSequentialDependence = false;
941 
942  return;
943 }
944 
945 // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
946 bool HexagonPacketizerList::ignorePseudoInstruction(MachineInstr *MI,
947  MachineBasicBlock *MBB) {
948  if (MI->isDebugValue())
949  return true;
950 
951  if (MI->isCFIInstruction())
952  return false;
953 
954  // We must print out inline assembly
955  if (MI->isInlineAsm())
956  return false;
957 
958  // We check if MI has any functional units mapped to it.
959  // If it doesn't, we ignore the instruction.
960  const MCInstrDesc& TID = MI->getDesc();
961  unsigned SchedClass = TID.getSchedClass();
962  const InstrStage* IS =
963  ResourceTracker->getInstrItins()->beginStage(SchedClass);
964  unsigned FuncUnits = IS->getUnits();
965  return !FuncUnits;
966 }
967 
968 // isSoloInstruction: - Returns true for instructions that must be
969 // scheduled in their own packet.
970 bool HexagonPacketizerList::isSoloInstruction(MachineInstr *MI) {
971  if (MI->isEHLabel() || MI->isCFIInstruction())
972  return true;
973 
974  if (MI->isInlineAsm())
975  return true;
976 
977  // From Hexagon V4 Programmer's Reference Manual 3.4.4 Grouping constraints:
978  // trap, pause, barrier, icinva, isync, and syncht are solo instructions.
979  // They must not be grouped with other instructions in a packet.
980  if (IsSchedBarrier(MI))
981  return true;
982 
983  return false;
984 }
985 
986 // isLegalToPacketizeTogether:
987 // SUI is the current instruction that is out side of the current packet.
988 // SUJ is the current instruction inside the current packet against which that
989 // SUI will be packetized.
990 bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
991  MachineInstr *I = SUI->getInstr();
992  MachineInstr *J = SUJ->getInstr();
993  assert(I && J && "Unable to packetize null instruction!");
994 
995  const MCInstrDesc &MCIDI = I->getDesc();
996  const MCInstrDesc &MCIDJ = J->getDesc();
997 
999 
1000  const unsigned FrameSize = MF.getFrameInfo()->getStackSize();
1001  const HexagonRegisterInfo *QRI =
1002  (const HexagonRegisterInfo *)MF.getSubtarget().getRegisterInfo();
1003  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
1004 
1005  // Inline asm cannot go in the packet.
1006  if (I->getOpcode() == Hexagon::INLINEASM)
1007  llvm_unreachable("Should not meet inline asm here!");
1008 
1009  if (isSoloInstruction(I))
1010  llvm_unreachable("Should not meet solo instr here!");
1011 
1012  // A save callee-save register function call can only be in a packet
1013  // with instructions that don't write to the callee-save registers.
1014  if ((QII->isSaveCalleeSavedRegsCall(I) &&
1015  DoesModifyCalleeSavedReg(J, QRI)) ||
1016  (QII->isSaveCalleeSavedRegsCall(J) &&
1017  DoesModifyCalleeSavedReg(I, QRI))) {
1018  Dependence = true;
1019  return false;
1020  }
1021 
1022  // Two control flow instructions cannot go in the same packet.
1023  if (IsControlFlow(I) && IsControlFlow(J)) {
1024  Dependence = true;
1025  return false;
1026  }
1027 
1028  // A LoopN instruction cannot appear in the same packet as a jump or call.
1029  if (IsLoopN(I) &&
1030  (IsDirectJump(J) || MCIDJ.isCall() || QII->isDeallocRet(J))) {
1031  Dependence = true;
1032  return false;
1033  }
1034  if (IsLoopN(J) &&
1035  (IsDirectJump(I) || MCIDI.isCall() || QII->isDeallocRet(I))) {
1036  Dependence = true;
1037  return false;
1038  }
1039 
1040  // dealloc_return cannot appear in the same packet as a conditional or
1041  // unconditional jump.
1042  if (QII->isDeallocRet(I) &&
1043  (MCIDJ.isBranch() || MCIDJ.isCall() || MCIDJ.isBarrier())) {
1044  Dependence = true;
1045  return false;
1046  }
1047 
1048 
1049  // V4 allows dual store. But does not allow second store, if the
1050  // first store is not in SLOT0. New value store, new value jump,
1051  // dealloc_return and memop always take SLOT0.
1052  // Arch spec 3.4.4.2
1053  if (MCIDI.mayStore() && MCIDJ.mayStore() &&
1054  (QII->isNewValueInst(J) || QII->isMemOp(J) || QII->isMemOp(I))) {
1055  Dependence = true;
1056  return false;
1057  }
1058 
1059  if ((QII->isMemOp(J) && MCIDI.mayStore())
1060  || (MCIDJ.mayStore() && QII->isMemOp(I))
1061  || (QII->isMemOp(J) && QII->isMemOp(I))) {
1062  Dependence = true;
1063  return false;
1064  }
1065 
1066  //if dealloc_return
1067  if (MCIDJ.mayStore() && QII->isDeallocRet(I)) {
1068  Dependence = true;
1069  return false;
1070  }
1071 
1072  // If an instruction feeds new value jump, glue it.
1073  MachineBasicBlock::iterator NextMII = I;
1074  ++NextMII;
1075  if (NextMII != I->getParent()->end() && QII->isNewValueJump(NextMII)) {
1076  MachineInstr *NextMI = NextMII;
1077 
1078  bool secondRegMatch = false;
1079  bool maintainNewValueJump = false;
1080 
1081  if (NextMI->getOperand(1).isReg() &&
1082  I->getOperand(0).getReg() == NextMI->getOperand(1).getReg()) {
1083  secondRegMatch = true;
1084  maintainNewValueJump = true;
1085  }
1086 
1087  if (!secondRegMatch &&
1088  I->getOperand(0).getReg() == NextMI->getOperand(0).getReg()) {
1089  maintainNewValueJump = true;
1090  }
1091 
1092  for (std::vector<MachineInstr*>::iterator
1093  VI = CurrentPacketMIs.begin(),
1094  VE = CurrentPacketMIs.end();
1095  (VI != VE && maintainNewValueJump); ++VI) {
1096  SUnit *PacketSU = MIToSUnit.find(*VI)->second;
1097 
1098  // NVJ can not be part of the dual jump - Arch Spec: section 7.8
1099  if (PacketSU->getInstr()->getDesc().isCall()) {
1100  Dependence = true;
1101  break;
1102  }
1103  // Validate
1104  // 1. Packet does not have a store in it.
1105  // 2. If the first operand of the nvj is newified, and the second
1106  // operand is also a reg, it (second reg) is not defined in
1107  // the same packet.
1108  // 3. If the second operand of the nvj is newified, (which means
1109  // first operand is also a reg), first reg is not defined in
1110  // the same packet.
1111  if (PacketSU->getInstr()->getDesc().mayStore() ||
1112  PacketSU->getInstr()->getOpcode() == Hexagon::S2_allocframe ||
1113  // Check #2.
1114  (!secondRegMatch && NextMI->getOperand(1).isReg() &&
1115  PacketSU->getInstr()->modifiesRegister(
1116  NextMI->getOperand(1).getReg(), QRI)) ||
1117  // Check #3.
1118  (secondRegMatch &&
1119  PacketSU->getInstr()->modifiesRegister(
1120  NextMI->getOperand(0).getReg(), QRI))) {
1121  Dependence = true;
1122  break;
1123  }
1124  }
1125  if (!Dependence)
1126  GlueToNewValueJump = true;
1127  else
1128  return false;
1129  }
1130 
1131  if (SUJ->isSucc(SUI)) {
1132  for (unsigned i = 0;
1133  (i < SUJ->Succs.size()) && !FoundSequentialDependence;
1134  ++i) {
1135 
1136  if (SUJ->Succs[i].getSUnit() != SUI) {
1137  continue;
1138  }
1139 
1140  SDep::Kind DepType = SUJ->Succs[i].getKind();
1141 
1142  // For direct calls:
1143  // Ignore register dependences for call instructions for
1144  // packetization purposes except for those due to r31 and
1145  // predicate registers.
1146  //
1147  // For indirect calls:
1148  // Same as direct calls + check for true dependences to the register
1149  // used in the indirect call.
1150  //
1151  // We completely ignore Order dependences for call instructions
1152  //
1153  // For returns:
1154  // Ignore register dependences for return instructions like jumpr,
1155  // dealloc return unless we have dependencies on the explicit uses
1156  // of the registers used by jumpr (like r31) or dealloc return
1157  // (like r29 or r30).
1158  //
1159  // TODO: Currently, jumpr is handling only return of r31. So, the
1160  // following logic (specificaly IsCallDependent) is working fine.
1161  // We need to enable jumpr for register other than r31 and then,
1162  // we need to rework the last part, where it handles indirect call
1163  // of that (IsCallDependent) function. Bug 6216 is opened for this.
1164  //
1165  unsigned DepReg = 0;
1166  const TargetRegisterClass* RC = nullptr;
1167  if (DepType == SDep::Data) {
1168  DepReg = SUJ->Succs[i].getReg();
1169  RC = QRI->getMinimalPhysRegClass(DepReg);
1170  }
1171  if ((MCIDI.isCall() || MCIDI.isReturn()) &&
1172  (!IsRegDependence(DepType) ||
1173  !IsCallDependent(I, DepType, SUJ->Succs[i].getReg()))) {
1174  /* do nothing */
1175  }
1176 
1177  // For instructions that can be promoted to dot-new, try to promote.
1178  else if ((DepType == SDep::Data) &&
1179  CanPromoteToDotNew(I, SUJ, DepReg, MIToSUnit, II, RC) &&
1180  PromoteToDotNew(I, DepType, II, RC)) {
1181  PromotedToDotNew = true;
1182  /* do nothing */
1183  }
1184 
1185  else if ((DepType == SDep::Data) &&
1186  (QII->isNewValueJump(I))) {
1187  /* do nothing */
1188  }
1189 
1190  // For predicated instructions, if the predicates are complements
1191  // then there can be no dependence.
1192  else if (QII->isPredicated(I) &&
1193  QII->isPredicated(J) &&
1194  ArePredicatesComplements(I, J, MIToSUnit)) {
1195  /* do nothing */
1196 
1197  }
1198  else if (IsDirectJump(I) &&
1199  !MCIDJ.isBranch() &&
1200  !MCIDJ.isCall() &&
1201  (DepType == SDep::Order)) {
1202  // Ignore Order dependences between unconditional direct branches
1203  // and non-control-flow instructions
1204  /* do nothing */
1205  }
1206  else if (MCIDI.isConditionalBranch() && (DepType != SDep::Data) &&
1207  (DepType != SDep::Output)) {
1208  // Ignore all dependences for jumps except for true and output
1209  // dependences
1210  /* do nothing */
1211  }
1212 
1213  // Ignore output dependences due to superregs. We can
1214  // write to two different subregisters of R1:0 for instance
1215  // in the same cycle
1216  //
1217 
1218  //
1219  // Let the
1220  // If neither I nor J defines DepReg, then this is a
1221  // superfluous output dependence. The dependence must be of the
1222  // form:
1223  // R0 = ...
1224  // R1 = ...
1225  // and there is an output dependence between the two instructions
1226  // with
1227  // DepReg = D0
1228  // We want to ignore these dependences.
1229  // Ideally, the dependence constructor should annotate such
1230  // dependences. We can then avoid this relatively expensive check.
1231  //
1232  else if (DepType == SDep::Output) {
1233  // DepReg is the register that's responsible for the dependence.
1234  unsigned DepReg = SUJ->Succs[i].getReg();
1235 
1236  // Check if I and J really defines DepReg.
1237  if (I->definesRegister(DepReg) ||
1238  J->definesRegister(DepReg)) {
1239  FoundSequentialDependence = true;
1240  break;
1241  }
1242  }
1243 
1244  // We ignore Order dependences for
1245  // 1. Two loads unless they are volatile.
1246  // 2. Two stores in V4 unless they are volatile.
1247  else if ((DepType == SDep::Order) &&
1248  !I->hasOrderedMemoryRef() &&
1249  !J->hasOrderedMemoryRef()) {
1250  if (MCIDI.mayStore() && MCIDJ.mayStore()) {
1251  /* do nothing */
1252  }
1253  // store followed by store-- not OK on V2
1254  // store followed by load -- not OK on all (OK if addresses
1255  // are not aliased)
1256  // load followed by store -- OK on all
1257  // load followed by load -- OK on all
1258  else if ( !MCIDJ.mayStore()) {
1259  /* do nothing */
1260  }
1261  else {
1262  FoundSequentialDependence = true;
1263  break;
1264  }
1265  }
1266 
1267  // For V4, special case ALLOCFRAME. Even though there is dependency
1268  // between ALLOCFRAME and subsequent store, allow it to be
1269  // packetized in a same packet. This implies that the store is using
1270  // caller's SP. Hence, offset needs to be updated accordingly.
1271  else if (DepType == SDep::Data
1272  && J->getOpcode() == Hexagon::S2_allocframe
1273  && (I->getOpcode() == Hexagon::S2_storerd_io
1274  || I->getOpcode() == Hexagon::S2_storeri_io
1275  || I->getOpcode() == Hexagon::S2_storerb_io)
1276  && I->getOperand(0).getReg() == QRI->getStackRegister()
1277  && QII->isValidOffset(I->getOpcode(),
1278  I->getOperand(1).getImm() -
1279  (FrameSize + HEXAGON_LRFP_SIZE)))
1280  {
1281  GlueAllocframeStore = true;
1282  // Since this store is to be glued with allocframe in the same
1283  // packet, it will use SP of the previous stack frame, i.e
1284  // caller's SP. Therefore, we need to recalculate offset according
1285  // to this change.
1286  I->getOperand(1).setImm(I->getOperand(1).getImm() -
1287  (FrameSize + HEXAGON_LRFP_SIZE));
1288  }
1289 
1290  //
1291  // Skip over anti-dependences. Two instructions that are
1292  // anti-dependent can share a packet
1293  //
1294  else if (DepType != SDep::Anti) {
1295  FoundSequentialDependence = true;
1296  break;
1297  }
1298  }
1299 
1300  if (FoundSequentialDependence) {
1301  Dependence = true;
1302  return false;
1303  }
1304  }
1305 
1306  return true;
1307 }
1308 
1309 // isLegalToPruneDependencies
1310 bool HexagonPacketizerList::isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) {
1311  MachineInstr *I = SUI->getInstr();
1312  assert(I && SUJ->getInstr() && "Unable to packetize null instruction!");
1313 
1314  const unsigned FrameSize = MF.getFrameInfo()->getStackSize();
1315 
1316  if (Dependence) {
1317 
1318  // Check if the instruction was promoted to a dot-new. If so, demote it
1319  // back into a dot-old.
1320  if (PromotedToDotNew) {
1321  DemoteToDotOld(I);
1322  }
1323 
1324  // Check if the instruction (must be a store) was glued with an Allocframe
1325  // instruction. If so, restore its offset to its original value, i.e. use
1326  // curent SP instead of caller's SP.
1327  if (GlueAllocframeStore) {
1328  I->getOperand(1).setImm(I->getOperand(1).getImm() +
1329  FrameSize + HEXAGON_LRFP_SIZE);
1330  }
1331 
1332  return false;
1333  }
1334  return true;
1335 }
1336 
1338 HexagonPacketizerList::addToPacket(MachineInstr *MI) {
1339 
1341  MachineBasicBlock *MBB = MI->getParent();
1342 
1343  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
1344 
1345  if (GlueToNewValueJump) {
1346 
1347  ++MII;
1348  MachineInstr *nvjMI = MII;
1349  assert(ResourceTracker->canReserveResources(MI));
1350  ResourceTracker->reserveResources(MI);
1351  if ((QII->isExtended(MI) || QII->isConstExtended(MI)) &&
1352  !tryAllocateResourcesForConstExt(MI)) {
1353  endPacket(MBB, MI);
1354  ResourceTracker->reserveResources(MI);
1355  assert(canReserveResourcesForConstExt(MI) &&
1356  "Ensure that there is a slot");
1357  reserveResourcesForConstExt(MI);
1358  // Reserve resources for new value jump constant extender.
1359  assert(canReserveResourcesForConstExt(MI) &&
1360  "Ensure that there is a slot");
1361  reserveResourcesForConstExt(nvjMI);
1362  assert(ResourceTracker->canReserveResources(nvjMI) &&
1363  "Ensure that there is a slot");
1364 
1365  } else if ( // Extended instruction takes two slots in the packet.
1366  // Try reserve and allocate 4-byte in the current packet first.
1367  (QII->isExtended(nvjMI)
1368  && (!tryAllocateResourcesForConstExt(nvjMI)
1369  || !ResourceTracker->canReserveResources(nvjMI)))
1370  || // For non-extended instruction, no need to allocate extra 4 bytes.
1371  (!QII->isExtended(nvjMI) &&
1372  !ResourceTracker->canReserveResources(nvjMI)))
1373  {
1374  endPacket(MBB, MI);
1375  // A new and empty packet starts.
1376  // We are sure that the resources requirements can be satisfied.
1377  // Therefore, do not need to call "canReserveResources" anymore.
1378  ResourceTracker->reserveResources(MI);
1379  if (QII->isExtended(nvjMI))
1380  reserveResourcesForConstExt(nvjMI);
1381  }
1382  // Here, we are sure that "reserveResources" would succeed.
1383  ResourceTracker->reserveResources(nvjMI);
1384  CurrentPacketMIs.push_back(MI);
1385  CurrentPacketMIs.push_back(nvjMI);
1386  } else {
1387  if ( (QII->isExtended(MI) || QII->isConstExtended(MI))
1388  && ( !tryAllocateResourcesForConstExt(MI)
1389  || !ResourceTracker->canReserveResources(MI)))
1390  {
1391  endPacket(MBB, MI);
1392  // Check if the instruction was promoted to a dot-new. If so, demote it
1393  // back into a dot-old
1394  if (PromotedToDotNew) {
1395  DemoteToDotOld(MI);
1396  }
1397  reserveResourcesForConstExt(MI);
1398  }
1399  // In case that "MI" is not an extended insn,
1400  // the resource availability has already been checked.
1401  ResourceTracker->reserveResources(MI);
1402  CurrentPacketMIs.push_back(MI);
1403  }
1404  return MII;
1405 }
1406 
1407 //===----------------------------------------------------------------------===//
1408 // Public Constructor Functions
1409 //===----------------------------------------------------------------------===//
1410 
1412  return new HexagonPacketizer();
1413 }
1414 
bool isImplicit() const
bool isConditionalLoad(const MachineInstr *MI) const
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
mop_iterator operands_end()
Definition: MachineInstr.h:290
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
MachineInstr * CreateMachineInstr(const MCInstrDesc &MCID, DebugLoc DL, bool NoImp=false)
CreateMachineInstr - Allocate a new MachineInstr.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
unsigned getFrameRegister(const MachineFunction &MF) const override
bool isSucc(SUnit *N)
isSucc - Test if node N is a successor of this node.
Definition: ScheduleDAG.h:466
static PredicateKind getPredicateSense(MachineInstr *MI, const HexagonInstrInfo *QII)
Returns true if an instruction is predicated on p0 and false if it's predicated on !p0...
static bool IsLoopN(MachineInstr *MI)
bool isReturn() const
Return true if the instruction is a return.
Definition: MCInstrDesc.h:211
Hexagon Packetizer
bool mayStore() const
Return true if this instruction could possibly modify memory.
Definition: MCInstrDesc.h:356
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:138
MachineInstr * getInstr() const
getInstr - Return the representative MachineInstr for this SUnit.
Definition: ScheduleDAG.h:406
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
static bool IsIndirectCall(MachineInstr *MI)
static bool IsControlFlow(MachineInstr *MI)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
static cl::opt< bool > PacketizeVolatiles("hexagon-packetize-volatiles", cl::ZeroOrMore, cl::Hidden, cl::init(true), cl::desc("Allow non-solo packetization of volatile memory references"))
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:264
virtual bool isSchedulingBoundary(const MachineInstr *MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const
Test if the given instruction should be considered a scheduling boundary.
bool isCFIInstruction() const
Definition: MachineInstr.h:741
A debug info location.
Definition: DebugLoc.h:34
static MachineOperand & GetStoreValueOperand(MachineInstr *MI)
Kind
Kind - These are the different kinds of scheduling dependencies.
Definition: ScheduleDAG.h:48
bool isPostIncrement(const MachineInstr *MI) const
A register anti-dependedence (aka WAR).
Definition: ScheduleDAG.h:50
bool isConditionalTransfer(const MachineInstr *MI) const
AnalysisUsage & addRequired()
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:70
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
bool isMemOp(const MachineInstr *MI) const
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
bool isPredicated(const MachineInstr *MI) const override
int GetDotOldOp(const int opc) const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MCInstrDesc.h:233
bool isCall() const
Return true if the instruction is a call.
Definition: MCInstrDesc.h:214
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:75
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Regular data dependence (aka true-dependence).
Definition: ScheduleDAG.h:49
unsigned getUnits() const
Returns the choice of FUs.
bool isTerminator() const
Returns true if this instruction part of the terminator for a basic block.
Definition: MCInstrDesc.h:227
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Definition: Value.cpp:317
static bool IsDirectJump(MachineInstr *MI)
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:571
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:271
Hexagon false
A register output-dependence (aka WAW).
Definition: ScheduleDAG.h:51
void initializeHexagonPacketizerPass(PassRegistry &)
bool isBarrier() const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MCInstrDesc.h:219
int64_t getImm() const
static unsigned getPredicatedRegister(MachineInstr *MI, const HexagonInstrInfo *QII)
Gets the predicate register of a predicated instruction.
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
getCalleeSavedRegs - Return a null-terminated list of all of the callee saved registers on this targe...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:267
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:120
TargetInstrInfo - Interface to description of machine instruction set.
bool isDebugValue() const
Definition: MachineInstr.h:748
#define true
Definition: ConvertUTF.c:66
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:325
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
FunctionPass * createHexagonPacketizer()
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
bundle_iterator - MachineBasicBlock iterator that automatically skips over MIs that are inside bundle...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
bool isSaveCalleeSavedRegsCall(const MachineInstr *MI) const
Represent the analysis usage information of a pass.
bool isDeallocRet(const MachineInstr *MI) const
static MachineOperand & GetPostIncrementOperand(MachineInstr *MI, const HexagonInstrInfo *QII)
bool isNewValueInst(const MachineInstr *MI) const
static bool IsSchedBarrier(MachineInstr *MI)
void setImm(int64_t immVal)
bool isPredicatedTrue(const MachineInstr *MI) const
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:294
bool isConstExtended(const MachineInstr *MI) const
bool isConditionalStore(const MachineInstr *MI) const
#define INITIALIZE_AG_DEPENDENCY(depName)
Definition: PassSupport.h:72
int GetDotNewOp(const MachineInstr *MI) const
void DeleteMachineInstr(MachineInstr *MI)
DeleteMachineInstr - Delete the given MachineInstr.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Any other ordering dependency.
Definition: ScheduleDAG.h:52
bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
Definition: MachineInstr.h:866
#define HEXAGON_LRFP_SIZE
Definition: Hexagon.h:27
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
MachineOperand class - Representation of each machine instruction operand.
bool isInlineAsm() const
Definition: MachineInstr.h:760
INITIALIZE_PASS_BEGIN(HexagonPacketizer,"packets","Hexagon Packetizer", false, false) INITIALIZE_PASS_END(HexagonPacketizer
bool mayLoad() const
Return true if this instruction could possibly read memory.
Definition: MCInstrDesc.h:350
static bool IsRegDependence(const SDep::Kind DepType)
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:263
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:238
int GetDotNewPredOp(MachineInstr *MI, const MachineBranchProbabilityInfo *MBPI) const
bool isExtended(const MachineInstr *MI) const
Representation of each machine instruction.
Definition: MachineInstr.h:51
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:528
These values represent a non-pipelined step in the execution of an instruction.
#define I(x, y, z)
Definition: MD5.cpp:54
bool isConditionalALU32(const MachineInstr *MI) const
bool isEHLabel() const
Definition: MachineInstr.h:736
unsigned getReg() const
getReg - Returns the register number.
aarch64 promote const
virtual const TargetInstrInfo * getInstrInfo() const
mop_iterator operands_begin()
Definition: MachineInstr.h:289
SmallVector< SDep, 4 > Succs
Definition: ScheduleDAG.h:276
bool isNewValueJump(const MachineInstr *MI) const
BasicBlockListType::iterator iterator
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:41
static bool DoesModifyCalleeSavedReg(MachineInstr *MI, const TargetRegisterInfo *TRI)
DoesModifyCalleeSavedReg - Returns true if the instruction modifies a callee-saved register...
Dependence - This class represents a dependence between two memory memory references in a function...
bool isValidOffset(unsigned Opcode, int Offset, bool Extend=true) const
bool isDotNewInst(const MachineInstr *MI) const
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
Definition: MachineInstr.h:874
bool isConditionalBranch() const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
Definition: MCInstrDesc.h:243
SUnit - Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:261
bool mayBeNewStore(const MachineInstr *MI) const