LLVM  3.7.0
MachineInstr.h
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1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
12 // the back end.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
18 
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/ADT/DenseMapInfo.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/ADT/ilist.h"
24 #include "llvm/ADT/ilist_node.h"
27 #include "llvm/IR/DebugInfo.h"
28 #include "llvm/IR/DebugLoc.h"
29 #include "llvm/IR/InlineAsm.h"
30 #include "llvm/MC/MCInstrDesc.h"
33 
34 namespace llvm {
35 
36 template <typename T> class SmallVectorImpl;
37 class AliasAnalysis;
38 class TargetInstrInfo;
39 class TargetRegisterClass;
40 class TargetRegisterInfo;
41 class MachineFunction;
42 class MachineMemOperand;
43 
44 //===----------------------------------------------------------------------===//
45 /// Representation of each machine instruction.
46 ///
47 /// This class isn't a POD type, but it must have a trivial destructor. When a
48 /// MachineFunction is deleted, all the contained MachineInstrs are deallocated
49 /// without having their destructor called.
50 ///
51 class MachineInstr : public ilist_node<MachineInstr> {
52 public:
54 
55  /// Flags to specify different kinds of comments to output in
56  /// assembly code. These flags carry semantic information not
57  /// otherwise easily derivable from the IR text.
58  ///
59  enum CommentFlag {
61  };
62 
63  enum MIFlag {
64  NoFlags = 0,
65  FrameSetup = 1 << 0, // Instruction is used as a part of
66  // function frame setup code.
67  BundledPred = 1 << 1, // Instruction has bundled predecessors.
68  BundledSucc = 1 << 2 // Instruction has bundled successors.
69  };
70 private:
71  const MCInstrDesc *MCID; // Instruction descriptor.
72  MachineBasicBlock *Parent; // Pointer to the owning basic block.
73 
74  // Operands are allocated by an ArrayRecycler.
75  MachineOperand *Operands; // Pointer to the first operand.
76  unsigned NumOperands; // Number of operands on instruction.
77  typedef ArrayRecycler<MachineOperand>::Capacity OperandCapacity;
78  OperandCapacity CapOperands; // Capacity of the Operands array.
79 
80  uint8_t Flags; // Various bits of additional
81  // information about machine
82  // instruction.
83 
84  uint8_t AsmPrinterFlags; // Various bits of information used by
85  // the AsmPrinter to emit helpful
86  // comments. This is *not* semantic
87  // information. Do not use this for
88  // anything other than to convey comment
89  // information to AsmPrinter.
90 
91  uint8_t NumMemRefs; // Information on memory references.
92  mmo_iterator MemRefs;
93 
94  DebugLoc debugLoc; // Source line information.
95 
96  MachineInstr(const MachineInstr&) = delete;
97  void operator=(const MachineInstr&) = delete;
98  // Use MachineFunction::DeleteMachineInstr() instead.
99  ~MachineInstr() = delete;
100 
101  // Intrusive list support
102  friend struct ilist_traits<MachineInstr>;
104  void setParent(MachineBasicBlock *P) { Parent = P; }
105 
106  /// This constructor creates a copy of the given
107  /// MachineInstr in the given MachineFunction.
109 
110  /// This constructor create a MachineInstr and add the implicit operands.
111  /// It reserves space for number of operands specified by
112  /// MCInstrDesc. An explicit DebugLoc is supplied.
114  bool NoImp = false);
115 
116  // MachineInstrs are pool-allocated and owned by MachineFunction.
117  friend class MachineFunction;
118 
119 public:
120  const MachineBasicBlock* getParent() const { return Parent; }
121  MachineBasicBlock* getParent() { return Parent; }
122 
123  /// Return the asm printer flags bitvector.
124  uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
125 
126  /// Clear the AsmPrinter bitvector.
127  void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
128 
129  /// Return whether an AsmPrinter flag is set.
131  return AsmPrinterFlags & Flag;
132  }
133 
134  /// Set a flag for the AsmPrinter.
136  AsmPrinterFlags |= (uint8_t)Flag;
137  }
138 
139  /// Clear specific AsmPrinter flags.
141  AsmPrinterFlags &= ~Flag;
142  }
143 
144  /// Return the MI flags bitvector.
145  uint8_t getFlags() const {
146  return Flags;
147  }
148 
149  /// Return whether an MI flag is set.
150  bool getFlag(MIFlag Flag) const {
151  return Flags & Flag;
152  }
153 
154  /// Set a MI flag.
156  Flags |= (uint8_t)Flag;
157  }
158 
159  void setFlags(unsigned flags) {
160  // Filter out the automatically maintained flags.
161  unsigned Mask = BundledPred | BundledSucc;
162  Flags = (Flags & Mask) | (flags & ~Mask);
163  }
164 
165  /// clearFlag - Clear a MI flag.
167  Flags &= ~((uint8_t)Flag);
168  }
169 
170  /// Return true if MI is in a bundle (but not the first MI in a bundle).
171  ///
172  /// A bundle looks like this before it's finalized:
173  /// ----------------
174  /// | MI |
175  /// ----------------
176  /// |
177  /// ----------------
178  /// | MI * |
179  /// ----------------
180  /// |
181  /// ----------------
182  /// | MI * |
183  /// ----------------
184  /// In this case, the first MI starts a bundle but is not inside a bundle, the
185  /// next 2 MIs are considered "inside" the bundle.
186  ///
187  /// After a bundle is finalized, it looks like this:
188  /// ----------------
189  /// | Bundle |
190  /// ----------------
191  /// |
192  /// ----------------
193  /// | MI * |
194  /// ----------------
195  /// |
196  /// ----------------
197  /// | MI * |
198  /// ----------------
199  /// |
200  /// ----------------
201  /// | MI * |
202  /// ----------------
203  /// The first instruction has the special opcode "BUNDLE". It's not "inside"
204  /// a bundle, but the next three MIs are.
205  bool isInsideBundle() const {
206  return getFlag(BundledPred);
207  }
208 
209  /// Return true if this instruction part of a bundle. This is true
210  /// if either itself or its following instruction is marked "InsideBundle".
211  bool isBundled() const {
212  return isBundledWithPred() || isBundledWithSucc();
213  }
214 
215  /// Return true if this instruction is part of a bundle, and it is not the
216  /// first instruction in the bundle.
217  bool isBundledWithPred() const { return getFlag(BundledPred); }
218 
219  /// Return true if this instruction is part of a bundle, and it is not the
220  /// last instruction in the bundle.
221  bool isBundledWithSucc() const { return getFlag(BundledSucc); }
222 
223  /// Bundle this instruction with its predecessor. This can be an unbundled
224  /// instruction, or it can be the first instruction in a bundle.
225  void bundleWithPred();
226 
227  /// Bundle this instruction with its successor. This can be an unbundled
228  /// instruction, or it can be the last instruction in a bundle.
229  void bundleWithSucc();
230 
231  /// Break bundle above this instruction.
232  void unbundleFromPred();
233 
234  /// Break bundle below this instruction.
235  void unbundleFromSucc();
236 
237  /// Returns the debug location id of this MachineInstr.
238  const DebugLoc &getDebugLoc() const { return debugLoc; }
239 
240  /// Return the debug variable referenced by
241  /// this DBG_VALUE instruction.
243  assert(isDebugValue() && "not a DBG_VALUE");
244  return cast<DILocalVariable>(getOperand(2).getMetadata());
245  }
246 
247  /// Return the complex address expression referenced by
248  /// this DBG_VALUE instruction.
250  assert(isDebugValue() && "not a DBG_VALUE");
251  return cast<DIExpression>(getOperand(3).getMetadata());
252  }
253 
254  /// Emit an error referring to the source location of this instruction.
255  /// This should only be used for inline assembly that is somehow
256  /// impossible to compile. Other errors should have been handled much
257  /// earlier.
258  ///
259  /// If this method returns, the caller should try to recover from the error.
260  ///
261  void emitError(StringRef Msg) const;
262 
263  /// Returns the target instruction descriptor of this MachineInstr.
264  const MCInstrDesc &getDesc() const { return *MCID; }
265 
266  /// Returns the opcode of this MachineInstr.
267  unsigned getOpcode() const { return MCID->Opcode; }
268 
269  /// Access to explicit operands of the instruction.
270  ///
271  unsigned getNumOperands() const { return NumOperands; }
272 
273  const MachineOperand& getOperand(unsigned i) const {
274  assert(i < getNumOperands() && "getOperand() out of range!");
275  return Operands[i];
276  }
277  MachineOperand& getOperand(unsigned i) {
278  assert(i < getNumOperands() && "getOperand() out of range!");
279  return Operands[i];
280  }
281 
282  /// Returns the number of non-implicit operands.
283  unsigned getNumExplicitOperands() const;
284 
285  /// iterator/begin/end - Iterate over all operands of a machine instruction.
288 
290  mop_iterator operands_end() { return Operands + NumOperands; }
291 
293  const_mop_iterator operands_end() const { return Operands + NumOperands; }
294 
297  }
300  }
304  }
308  }
311  operands_end());
312  }
315  operands_end());
316  }
320  }
324  }
328  }
332  }
333 
334  /// Returns the number of the operand iterator \p I points to.
336  return I - operands_begin();
337  }
338 
339  /// Access to memory operands of the instruction
340  mmo_iterator memoperands_begin() const { return MemRefs; }
341  mmo_iterator memoperands_end() const { return MemRefs + NumMemRefs; }
342  bool memoperands_empty() const { return NumMemRefs == 0; }
343 
346  }
349  }
350 
351  /// Return true if this instruction has exactly one MachineMemOperand.
352  bool hasOneMemOperand() const {
353  return NumMemRefs == 1;
354  }
355 
356  /// API for querying MachineInstr properties. They are the same as MCInstrDesc
357  /// queries but they are bundle aware.
358 
359  enum QueryType {
360  IgnoreBundle, // Ignore bundles
361  AnyInBundle, // Return true if any instruction in bundle has property
362  AllInBundle // Return true if all instructions in bundle have property
363  };
364 
365  /// Return true if the instruction (or in the case of a bundle,
366  /// the instructions inside the bundle) has the specified property.
367  /// The first argument is the property being queried.
368  /// The second argument indicates whether the query should look inside
369  /// instruction bundles.
370  bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
371  // Inline the fast path for unbundled or bundle-internal instructions.
372  if (Type == IgnoreBundle || !isBundled() || isBundledWithPred())
373  return getDesc().getFlags() & (1 << MCFlag);
374 
375  // If this is the first instruction in a bundle, take the slow path.
376  return hasPropertyInBundle(1 << MCFlag, Type);
377  }
378 
379  /// Return true if this instruction can have a variable number of operands.
380  /// In this case, the variable operands will be after the normal
381  /// operands but before the implicit definitions and uses (if any are
382  /// present).
385  }
386 
387  /// Set if this instruction has an optional definition, e.g.
388  /// ARM instructions which can set condition code if 's' bit is set.
391  }
392 
393  /// Return true if this is a pseudo instruction that doesn't
394  /// correspond to a real machine instruction.
396  return hasProperty(MCID::Pseudo, Type);
397  }
398 
400  return hasProperty(MCID::Return, Type);
401  }
402 
404  return hasProperty(MCID::Call, Type);
405  }
406 
407  /// Returns true if the specified instruction stops control flow
408  /// from executing the instruction immediately following it. Examples include
409  /// unconditional branches and return instructions.
411  return hasProperty(MCID::Barrier, Type);
412  }
413 
414  /// Returns true if this instruction part of the terminator for a basic block.
415  /// Typically this is things like return and branch instructions.
416  ///
417  /// Various passes use this to insert code into the bottom of a basic block,
418  /// but before control flow occurs.
421  }
422 
423  /// Returns true if this is a conditional, unconditional, or indirect branch.
424  /// Predicates below can be used to discriminate between
425  /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
426  /// get more information.
428  return hasProperty(MCID::Branch, Type);
429  }
430 
431  /// Return true if this is an indirect branch, such as a
432  /// branch through a register.
435  }
436 
437  /// Return true if this is a branch which may fall
438  /// through to the next instruction or may transfer control flow to some other
439  /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
440  /// information about this branch.
443  }
444 
445  /// Return true if this is a branch which always
446  /// transfers control flow to some other block. The
447  /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
448  /// about this branch.
451  }
452 
453  /// Return true if this instruction has a predicate operand that
454  /// controls execution. It may be set to 'always', or may be set to other
455  /// values. There are various methods in TargetInstrInfo that can be used to
456  /// control and modify the predicate in this instruction.
458  // If it's a bundle than all bundled instructions must be predicable for this
459  // to return true.
461  }
462 
463  /// Return true if this instruction is a comparison.
465  return hasProperty(MCID::Compare, Type);
466  }
467 
468  /// Return true if this instruction is a move immediate
469  /// (including conditional moves) instruction.
471  return hasProperty(MCID::MoveImm, Type);
472  }
473 
474  /// Return true if this instruction is a bitcast instruction.
476  return hasProperty(MCID::Bitcast, Type);
477  }
478 
479  /// Return true if this instruction is a select instruction.
481  return hasProperty(MCID::Select, Type);
482  }
483 
484  /// Return true if this instruction cannot be safely duplicated.
485  /// For example, if the instruction has a unique labels attached
486  /// to it, duplicating it would cause multiple definition errors.
489  }
490 
491  /// Return true if this instruction is convergent.
492  /// Convergent instructions can only be moved to locations that are
493  /// control-equivalent to their initial position.
496  }
497 
498  /// Returns true if the specified instruction has a delay slot
499  /// which must be filled by the code generator.
502  }
503 
504  /// Return true for instructions that can be folded as
505  /// memory operands in other instructions. The most common use for this
506  /// is instructions that are simple loads from memory that don't modify
507  /// the loaded value in any way, but it can also be used for instructions
508  /// that can be expressed as constant-pool loads, such as V_SETALLONES
509  /// on x86, to allow them to be folded when it is beneficial.
510  /// This should only be set on instructions that return a value in their
511  /// only virtual register definition.
514  }
515 
516  /// \brief Return true if this instruction behaves
517  /// the same way as the generic REG_SEQUENCE instructions.
518  /// E.g., on ARM,
519  /// dX VMOVDRR rY, rZ
520  /// is equivalent to
521  /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
522  ///
523  /// Note that for the optimizers to be able to take advantage of
524  /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
525  /// override accordingly.
528  }
529 
530  /// \brief Return true if this instruction behaves
531  /// the same way as the generic EXTRACT_SUBREG instructions.
532  /// E.g., on ARM,
533  /// rX, rY VMOVRRD dZ
534  /// is equivalent to two EXTRACT_SUBREG:
535  /// rX = EXTRACT_SUBREG dZ, ssub_0
536  /// rY = EXTRACT_SUBREG dZ, ssub_1
537  ///
538  /// Note that for the optimizers to be able to take advantage of
539  /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
540  /// override accordingly.
543  }
544 
545  /// \brief Return true if this instruction behaves
546  /// the same way as the generic INSERT_SUBREG instructions.
547  /// E.g., on ARM,
548  /// dX = VSETLNi32 dY, rZ, Imm
549  /// is equivalent to a INSERT_SUBREG:
550  /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
551  ///
552  /// Note that for the optimizers to be able to take advantage of
553  /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
554  /// override accordingly.
557  }
558 
559  //===--------------------------------------------------------------------===//
560  // Side Effect Analysis
561  //===--------------------------------------------------------------------===//
562 
563  /// Return true if this instruction could possibly read memory.
564  /// Instructions with this flag set are not necessarily simple load
565  /// instructions, they may load a value and modify it, for example.
567  if (isInlineAsm()) {
568  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
569  if (ExtraInfo & InlineAsm::Extra_MayLoad)
570  return true;
571  }
572  return hasProperty(MCID::MayLoad, Type);
573  }
574 
575  /// Return true if this instruction could possibly modify memory.
576  /// Instructions with this flag set are not necessarily simple store
577  /// instructions, they may store a modified value based on their operands, or
578  /// may not actually modify anything, for example.
580  if (isInlineAsm()) {
581  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
582  if (ExtraInfo & InlineAsm::Extra_MayStore)
583  return true;
584  }
586  }
587 
588  /// Return true if this instruction could possibly read or modify memory.
590  return mayLoad(Type) || mayStore(Type);
591  }
592 
593  //===--------------------------------------------------------------------===//
594  // Flags that indicate whether an instruction can be modified by a method.
595  //===--------------------------------------------------------------------===//
596 
597  /// Return true if this may be a 2- or 3-address
598  /// instruction (of the form "X = op Y, Z, ..."), which produces the same
599  /// result if Y and Z are exchanged. If this flag is set, then the
600  /// TargetInstrInfo::commuteInstruction method may be used to hack on the
601  /// instruction.
602  ///
603  /// Note that this flag may be set on instructions that are only commutable
604  /// sometimes. In these cases, the call to commuteInstruction will fail.
605  /// Also note that some instructions require non-trivial modification to
606  /// commute them.
609  }
610 
611  /// Return true if this is a 2-address instruction
612  /// which can be changed into a 3-address instruction if needed. Doing this
613  /// transformation can be profitable in the register allocator, because it
614  /// means that the instruction can use a 2-address form if possible, but
615  /// degrade into a less efficient form if the source and dest register cannot
616  /// be assigned to the same register. For example, this allows the x86
617  /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
618  /// is the same speed as the shift but has bigger code size.
619  ///
620  /// If this returns true, then the target must implement the
621  /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
622  /// is allowed to fail if the transformation isn't valid for this specific
623  /// instruction (e.g. shl reg, 4 on x86).
624  ///
627  }
628 
629  /// Return true if this instruction requires
630  /// custom insertion support when the DAG scheduler is inserting it into a
631  /// machine basic block. If this is true for the instruction, it basically
632  /// means that it is a pseudo instruction used at SelectionDAG time that is
633  /// expanded out into magic code by the target when MachineInstrs are formed.
634  ///
635  /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
636  /// is used to insert this into the MachineBasicBlock.
639  }
640 
641  /// Return true if this instruction requires *adjustment*
642  /// after instruction selection by calling a target hook. For example, this
643  /// can be used to fill in ARM 's' optional operand depending on whether
644  /// the conditional flag register is used.
647  }
648 
649  /// Returns true if this instruction is a candidate for remat.
650  /// This flag is deprecated, please don't use it anymore. If this
651  /// flag is set, the isReallyTriviallyReMaterializable() method is called to
652  /// verify the instruction is really rematable.
654  // It's only possible to re-mat a bundle if all bundled instructions are
655  // re-materializable.
657  }
658 
659  /// Returns true if this instruction has the same cost (or less) than a move
660  /// instruction. This is useful during certain types of optimizations
661  /// (e.g., remat during two-address conversion or machine licm)
662  /// where we would like to remat or hoist the instruction, but not if it costs
663  /// more than moving the instruction into the appropriate register. Note, we
664  /// are not marking copies from and to the same register class with this flag.
666  // Only returns true for a bundle if all bundled instructions are cheap.
668  }
669 
670  /// Returns true if this instruction source operands
671  /// have special register allocation requirements that are not captured by the
672  /// operand register classes. e.g. ARM::STRD's two source registers must be an
673  /// even / odd pair, ARM::STM registers have to be in ascending order.
674  /// Post-register allocation passes should not attempt to change allocations
675  /// for sources of instructions with this flag.
678  }
679 
680  /// Returns true if this instruction def operands
681  /// have special register allocation requirements that are not captured by the
682  /// operand register classes. e.g. ARM::LDRD's two def registers must be an
683  /// even / odd pair, ARM::LDM registers have to be in ascending order.
684  /// Post-register allocation passes should not attempt to change allocations
685  /// for definitions of instructions with this flag.
688  }
689 
690 
691  enum MICheckType {
692  CheckDefs, // Check all operands for equality
693  CheckKillDead, // Check all operands including kill / dead markers
694  IgnoreDefs, // Ignore all definitions
695  IgnoreVRegDefs // Ignore virtual register definitions
696  };
697 
698  /// Return true if this instruction is identical to (same
699  /// opcode and same operands as) the specified instruction.
700  bool isIdenticalTo(const MachineInstr *Other,
701  MICheckType Check = CheckDefs) const;
702 
703  /// Unlink 'this' from the containing basic block, and return it without
704  /// deleting it.
705  ///
706  /// This function can not be used on bundled instructions, use
707  /// removeFromBundle() to remove individual instructions from a bundle.
709 
710  /// Unlink this instruction from its basic block and return it without
711  /// deleting it.
712  ///
713  /// If the instruction is part of a bundle, the other instructions in the
714  /// bundle remain bundled.
716 
717  /// Unlink 'this' from the containing basic block and delete it.
718  ///
719  /// If this instruction is the header of a bundle, the whole bundle is erased.
720  /// This function can not be used for instructions inside a bundle, use
721  /// eraseFromBundle() to erase individual bundled instructions.
722  void eraseFromParent();
723 
724  /// Unlink 'this' from the containing basic block and delete it.
725  ///
726  /// For all definitions mark their uses in DBG_VALUE nodes
727  /// as undefined. Otherwise like eraseFromParent().
729 
730  /// Unlink 'this' form its basic block and delete it.
731  ///
732  /// If the instruction is part of a bundle, the other instructions in the
733  /// bundle remain bundled.
734  void eraseFromBundle();
735 
736  bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
737  bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
738 
739  /// Returns true if the MachineInstr represents a label.
740  bool isLabel() const { return isEHLabel() || isGCLabel(); }
741  bool isCFIInstruction() const {
743  }
744 
745  // True if the instruction represents a position in the function.
746  bool isPosition() const { return isLabel() || isCFIInstruction(); }
747 
748  bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
749  /// A DBG_VALUE is indirect iff the first operand is a register and
750  /// the second operand is an immediate.
751  bool isIndirectDebugValue() const {
752  return isDebugValue()
753  && getOperand(0).isReg()
754  && getOperand(1).isImm();
755  }
756 
757  bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
758  bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
760  bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
761  bool isMSInlineAsm() const {
763  }
764  bool isStackAligningInlineAsm() const;
766  bool isInsertSubreg() const {
768  }
769  bool isSubregToReg() const {
771  }
772  bool isRegSequence() const {
774  }
775  bool isBundle() const {
776  return getOpcode() == TargetOpcode::BUNDLE;
777  }
778  bool isCopy() const {
779  return getOpcode() == TargetOpcode::COPY;
780  }
781  bool isFullCopy() const {
782  return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
783  }
784  bool isExtractSubreg() const {
786  }
787 
788  /// Return true if the instruction behaves like a copy.
789  /// This does not include native copy instructions.
790  bool isCopyLike() const {
791  return isCopy() || isSubregToReg();
792  }
793 
794  /// Return true is the instruction is an identity copy.
795  bool isIdentityCopy() const {
796  return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
798  }
799 
800  /// Return true if this is a transient instruction that is
801  /// either very likely to be eliminated during register allocation (such as
802  /// copy-like instructions), or if this instruction doesn't have an
803  /// execution-time cost.
804  bool isTransient() const {
805  switch(getOpcode()) {
806  default: return false;
807  // Copy-like instructions are usually eliminated during register allocation.
808  case TargetOpcode::PHI:
809  case TargetOpcode::COPY:
813  // Pseudo-instructions that don't produce any real output.
815  case TargetOpcode::KILL:
820  return true;
821  }
822  }
823 
824  /// Return the number of instructions inside the MI bundle, excluding the
825  /// bundle header.
826  ///
827  /// This is the number of instructions that MachineBasicBlock::iterator
828  /// skips, 0 for unbundled instructions.
829  unsigned getBundleSize() const;
830 
831  /// Return true if the MachineInstr reads the specified register.
832  /// If TargetRegisterInfo is passed, then it also checks if there
833  /// is a read of a super-register.
834  /// This does not count partial redefines of virtual registers as reads:
835  /// %reg1024:6 = OP.
836  bool readsRegister(unsigned Reg,
837  const TargetRegisterInfo *TRI = nullptr) const {
838  return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
839  }
840 
841  /// Return true if the MachineInstr reads the specified virtual register.
842  /// Take into account that a partial define is a
843  /// read-modify-write operation.
844  bool readsVirtualRegister(unsigned Reg) const {
845  return readsWritesVirtualRegister(Reg).first;
846  }
847 
848  /// Return a pair of bools (reads, writes) indicating if this instruction
849  /// reads or writes Reg. This also considers partial defines.
850  /// If Ops is not null, all operand indices for Reg are added.
851  std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg,
852  SmallVectorImpl<unsigned> *Ops = nullptr) const;
853 
854  /// Return true if the MachineInstr kills the specified register.
855  /// If TargetRegisterInfo is passed, then it also checks if there is
856  /// a kill of a super-register.
857  bool killsRegister(unsigned Reg,
858  const TargetRegisterInfo *TRI = nullptr) const {
859  return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
860  }
861 
862  /// Return true if the MachineInstr fully defines the specified register.
863  /// If TargetRegisterInfo is passed, then it also checks
864  /// if there is a def of a super-register.
865  /// NOTE: It's ignoring subreg indices on virtual registers.
866  bool definesRegister(unsigned Reg,
867  const TargetRegisterInfo *TRI = nullptr) const {
868  return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
869  }
870 
871  /// Return true if the MachineInstr modifies (fully define or partially
872  /// define) the specified register.
873  /// NOTE: It's ignoring subreg indices on virtual registers.
874  bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
875  return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
876  }
877 
878  /// Returns true if the register is dead in this machine instruction.
879  /// If TargetRegisterInfo is passed, then it also checks
880  /// if there is a dead def of a super-register.
881  bool registerDefIsDead(unsigned Reg,
882  const TargetRegisterInfo *TRI = nullptr) const {
883  return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
884  }
885 
886  /// Returns the operand index that is a use of the specific register or -1
887  /// if it is not found. It further tightens the search criteria to a use
888  /// that kills the register if isKill is true.
889  int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
890  const TargetRegisterInfo *TRI = nullptr) const;
891 
892  /// Wrapper for findRegisterUseOperandIdx, it returns
893  /// a pointer to the MachineOperand rather than an index.
895  const TargetRegisterInfo *TRI = nullptr) {
896  int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
897  return (Idx == -1) ? nullptr : &getOperand(Idx);
898  }
899 
900  /// Returns the operand index that is a def of the specified register or
901  /// -1 if it is not found. If isDead is true, defs that are not dead are
902  /// skipped. If Overlap is true, then it also looks for defs that merely
903  /// overlap the specified register. If TargetRegisterInfo is non-null,
904  /// then it also checks if there is a def of a super-register.
905  /// This may also return a register mask operand when Overlap is true.
906  int findRegisterDefOperandIdx(unsigned Reg,
907  bool isDead = false, bool Overlap = false,
908  const TargetRegisterInfo *TRI = nullptr) const;
909 
910  /// Wrapper for findRegisterDefOperandIdx, it returns
911  /// a pointer to the MachineOperand rather than an index.
912  MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
913  const TargetRegisterInfo *TRI = nullptr) {
914  int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
915  return (Idx == -1) ? nullptr : &getOperand(Idx);
916  }
917 
918  /// Find the index of the first operand in the
919  /// operand list that is used to represent the predicate. It returns -1 if
920  /// none is found.
921  int findFirstPredOperandIdx() const;
922 
923  /// Find the index of the flag word operand that
924  /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
925  /// getOperand(OpIdx) does not belong to an inline asm operand group.
926  ///
927  /// If GroupNo is not NULL, it will receive the number of the operand group
928  /// containing OpIdx.
929  ///
930  /// The flag operand is an immediate that can be decoded with methods like
931  /// InlineAsm::hasRegClassConstraint().
932  ///
933  int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const;
934 
935  /// Compute the static register class constraint for operand OpIdx.
936  /// For normal instructions, this is derived from the MCInstrDesc.
937  /// For inline assembly it is derived from the flag words.
938  ///
939  /// Returns NULL if the static register class constraint cannot be
940  /// determined.
941  ///
942  const TargetRegisterClass*
943  getRegClassConstraint(unsigned OpIdx,
944  const TargetInstrInfo *TII,
945  const TargetRegisterInfo *TRI) const;
946 
947  /// \brief Applies the constraints (def/use) implied by this MI on \p Reg to
948  /// the given \p CurRC.
949  /// If \p ExploreBundle is set and MI is part of a bundle, all the
950  /// instructions inside the bundle will be taken into account. In other words,
951  /// this method accumulates all the constraints of the operand of this MI and
952  /// the related bundle if MI is a bundle or inside a bundle.
953  ///
954  /// Returns the register class that satisfies both \p CurRC and the
955  /// constraints set by MI. Returns NULL if such a register class does not
956  /// exist.
957  ///
958  /// \pre CurRC must not be NULL.
960  unsigned Reg, const TargetRegisterClass *CurRC,
961  const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
962  bool ExploreBundle = false) const;
963 
964  /// \brief Applies the constraints (def/use) implied by the \p OpIdx operand
965  /// to the given \p CurRC.
966  ///
967  /// Returns the register class that satisfies both \p CurRC and the
968  /// constraints set by \p OpIdx MI. Returns NULL if such a register class
969  /// does not exist.
970  ///
971  /// \pre CurRC must not be NULL.
972  /// \pre The operand at \p OpIdx must be a register.
973  const TargetRegisterClass *
974  getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC,
975  const TargetInstrInfo *TII,
976  const TargetRegisterInfo *TRI) const;
977 
978  /// Add a tie between the register operands at DefIdx and UseIdx.
979  /// The tie will cause the register allocator to ensure that the two
980  /// operands are assigned the same physical register.
981  ///
982  /// Tied operands are managed automatically for explicit operands in the
983  /// MCInstrDesc. This method is for exceptional cases like inline asm.
984  void tieOperands(unsigned DefIdx, unsigned UseIdx);
985 
986  /// Given the index of a tied register operand, find the
987  /// operand it is tied to. Defs are tied to uses and vice versa. Returns the
988  /// index of the tied operand which must exist.
989  unsigned findTiedOperandIdx(unsigned OpIdx) const;
990 
991  /// Given the index of a register def operand,
992  /// check if the register def is tied to a source operand, due to either
993  /// two-address elimination or inline assembly constraints. Returns the
994  /// first tied use operand index by reference if UseOpIdx is not null.
995  bool isRegTiedToUseOperand(unsigned DefOpIdx,
996  unsigned *UseOpIdx = nullptr) const {
997  const MachineOperand &MO = getOperand(DefOpIdx);
998  if (!MO.isReg() || !MO.isDef() || !MO.isTied())
999  return false;
1000  if (UseOpIdx)
1001  *UseOpIdx = findTiedOperandIdx(DefOpIdx);
1002  return true;
1003  }
1004 
1005  /// Return true if the use operand of the specified index is tied to a def
1006  /// operand. It also returns the def operand index by reference if DefOpIdx
1007  /// is not null.
1008  bool isRegTiedToDefOperand(unsigned UseOpIdx,
1009  unsigned *DefOpIdx = nullptr) const {
1010  const MachineOperand &MO = getOperand(UseOpIdx);
1011  if (!MO.isReg() || !MO.isUse() || !MO.isTied())
1012  return false;
1013  if (DefOpIdx)
1014  *DefOpIdx = findTiedOperandIdx(UseOpIdx);
1015  return true;
1016  }
1017 
1018  /// Clears kill flags on all operands.
1019  void clearKillInfo();
1020 
1021  /// Replace all occurrences of FromReg with ToReg:SubIdx,
1022  /// properly composing subreg indices where necessary.
1023  void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
1024  const TargetRegisterInfo &RegInfo);
1025 
1026  /// We have determined MI kills a register. Look for the
1027  /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
1028  /// add a implicit operand if it's not found. Returns true if the operand
1029  /// exists / is added.
1030  bool addRegisterKilled(unsigned IncomingReg,
1031  const TargetRegisterInfo *RegInfo,
1032  bool AddIfNotFound = false);
1033 
1034  /// Clear all kill flags affecting Reg. If RegInfo is
1035  /// provided, this includes super-register kills.
1036  void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo);
1037 
1038  /// We have determined MI defined a register without a use.
1039  /// Look for the operand that defines it and mark it as IsDead. If
1040  /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
1041  /// true if the operand exists / is added.
1042  bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo,
1043  bool AddIfNotFound = false);
1044 
1045  /// Clear all dead flags on operands defining register @p Reg.
1046  void clearRegisterDeads(unsigned Reg);
1047 
1048  /// Mark all subregister defs of register @p Reg with the undef flag.
1049  /// This function is used when we determined to have a subregister def in an
1050  /// otherwise undefined super register.
1051  void addRegisterDefReadUndef(unsigned Reg);
1052 
1053  /// We have determined MI defines a register. Make sure there is an operand
1054  /// defining Reg.
1055  void addRegisterDefined(unsigned Reg,
1056  const TargetRegisterInfo *RegInfo = nullptr);
1057 
1058  /// Mark every physreg used by this instruction as
1059  /// dead except those in the UsedRegs list.
1060  ///
1061  /// On instructions with register mask operands, also add implicit-def
1062  /// operands for all registers in UsedRegs.
1064  const TargetRegisterInfo &TRI);
1065 
1066  /// Return true if it is safe to move this instruction. If
1067  /// SawStore is set to true, it means that there is a store (or call) between
1068  /// the instruction's location and its intended destination.
1069  bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const;
1070 
1071  /// Return true if this instruction may have an ordered
1072  /// or volatile memory reference, or if the information describing the memory
1073  /// reference is not available. Return false if it is known to have no
1074  /// ordered or volatile memory references.
1075  bool hasOrderedMemoryRef() const;
1076 
1077  /// Return true if this instruction is loading from a
1078  /// location whose value is invariant across the function. For example,
1079  /// loading a value from the constant pool or from the argument area of
1080  /// a function if it does not change. This should only return true of *all*
1081  /// loads the instruction does are invariant (if it does multiple loads).
1082  bool isInvariantLoad(AliasAnalysis *AA) const;
1083 
1084  /// If the specified instruction is a PHI that always merges together the
1085  /// same virtual register, return the register, otherwise return 0.
1086  unsigned isConstantValuePHI() const;
1087 
1088  /// Return true if this instruction has side effects that are not modeled
1089  /// by mayLoad / mayStore, etc.
1090  /// For all instructions, the property is encoded in MCInstrDesc::Flags
1091  /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
1092  /// INLINEASM instruction, in which case the side effect property is encoded
1093  /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
1094  ///
1095  bool hasUnmodeledSideEffects() const;
1096 
1097  /// Return true if all the defs of this instruction are dead.
1098  bool allDefsAreDead() const;
1099 
1100  /// Copy implicit register operands from specified
1101  /// instruction to this instruction.
1102  void copyImplicitOps(MachineFunction &MF, const MachineInstr *MI);
1103 
1104  //
1105  // Debugging support
1106  //
1107  void print(raw_ostream &OS, bool SkipOpers = false) const;
1108  void print(raw_ostream &OS, ModuleSlotTracker &MST,
1109  bool SkipOpers = false) const;
1110  void dump() const;
1111 
1112  //===--------------------------------------------------------------------===//
1113  // Accessors used to build up machine instructions.
1114 
1115  /// Add the specified operand to the instruction. If it is an implicit
1116  /// operand, it is added to the end of the operand list. If it is an
1117  /// explicit operand it is added at the end of the explicit operand list
1118  /// (before the first implicit operand).
1119  ///
1120  /// MF must be the machine function that was used to allocate this
1121  /// instruction.
1122  ///
1123  /// MachineInstrBuilder provides a more convenient interface for creating
1124  /// instructions and adding operands.
1125  void addOperand(MachineFunction &MF, const MachineOperand &Op);
1126 
1127  /// Add an operand without providing an MF reference. This only works for
1128  /// instructions that are inserted in a basic block.
1129  ///
1130  /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be
1131  /// preferred.
1132  void addOperand(const MachineOperand &Op);
1133 
1134  /// Replace the instruction descriptor (thus opcode) of
1135  /// the current instruction with a new one.
1136  void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
1137 
1138  /// Replace current source information with new such.
1139  /// Avoid using this, the constructor argument is preferable.
1141  debugLoc = std::move(dl);
1142  assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
1143  }
1144 
1145  /// Erase an operand from an instruction, leaving it with one
1146  /// fewer operand than it started with.
1147  void RemoveOperand(unsigned i);
1148 
1149  /// Add a MachineMemOperand to the machine instruction.
1150  /// This function should be used only occasionally. The setMemRefs function
1151  /// is the primary method for setting up a MachineInstr's MemRefs list.
1153 
1154  /// Assign this MachineInstr's memory reference descriptor list.
1155  /// This does not transfer ownership.
1156  void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
1157  MemRefs = NewMemRefs;
1158  NumMemRefs = uint8_t(NewMemRefsEnd - NewMemRefs);
1159  assert(NumMemRefs == NewMemRefsEnd - NewMemRefs && "Too many memrefs");
1160  }
1161 
1162  /// Clear this MachineInstr's memory reference descriptor list.
1163  void clearMemRefs() {
1164  MemRefs = nullptr;
1165  NumMemRefs = 0;
1166  }
1167 
1168  /// Break any tie involving OpIdx.
1169  void untieRegOperand(unsigned OpIdx) {
1170  MachineOperand &MO = getOperand(OpIdx);
1171  if (MO.isReg() && MO.isTied()) {
1172  getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
1173  MO.TiedTo = 0;
1174  }
1175  }
1176 
1177 
1178 private:
1179  /// If this instruction is embedded into a MachineFunction, return the
1180  /// MachineRegisterInfo object for the current function, otherwise
1181  /// return null.
1182  MachineRegisterInfo *getRegInfo();
1183 
1184  /// Add all implicit def and use operands to this instruction.
1185  void addImplicitDefUseOperands(MachineFunction &MF);
1186 
1187  /// Unlink all of the register operands in this instruction from their
1188  /// respective use lists. This requires that the operands already be on their
1189  /// use lists.
1190  void RemoveRegOperandsFromUseLists(MachineRegisterInfo&);
1191 
1192  /// Add all of the register operands in this instruction from their
1193  /// respective use lists. This requires that the operands not be on their
1194  /// use lists yet.
1195  void AddRegOperandsToUseLists(MachineRegisterInfo&);
1196 
1197  /// Slow path for hasProperty when we're dealing with a bundle.
1198  bool hasPropertyInBundle(unsigned Mask, QueryType Type) const;
1199 
1200  /// \brief Implements the logic of getRegClassConstraintEffectForVReg for the
1201  /// this MI and the given operand index \p OpIdx.
1202  /// If the related operand does not constrained Reg, this returns CurRC.
1203  const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl(
1204  unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC,
1205  const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const;
1206 };
1207 
1208 /// Special DenseMapInfo traits to compare MachineInstr* by *value* of the
1209 /// instruction rather than by pointer value.
1210 /// The hashing and equality testing functions ignore definitions so this is
1211 /// useful for CSE, etc.
1213  static inline MachineInstr *getEmptyKey() {
1214  return nullptr;
1215  }
1216 
1217  static inline MachineInstr *getTombstoneKey() {
1218  return reinterpret_cast<MachineInstr*>(-1);
1219  }
1220 
1221  static unsigned getHashValue(const MachineInstr* const &MI);
1222 
1223  static bool isEqual(const MachineInstr* const &LHS,
1224  const MachineInstr* const &RHS) {
1225  if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
1226  LHS == getEmptyKey() || LHS == getTombstoneKey())
1227  return LHS == RHS;
1228  return LHS->isIdenticalTo(RHS, MachineInstr::IgnoreVRegDefs);
1229  }
1230 };
1231 
1232 //===----------------------------------------------------------------------===//
1233 // Debugging Support
1234 
1236  MI.print(OS);
1237  return OS;
1238 }
1239 
1240 } // End llvm namespace
1241 
1242 #endif
bool isInsideBundle() const
Return true if MI is in a bundle (but not the first MI in a bundle).
Definition: MachineInstr.h:205
bool isFullCopy() const
Definition: MachineInstr.h:781
void bundleWithPred()
Bundle this instruction with its predecessor.
mop_iterator operands_end()
Definition: MachineInstr.h:290
bool hasPostISelHook(QueryType Type=IgnoreBundle) const
Return true if this instruction requires adjustment after instruction selection by calling a target h...
Definition: MachineInstr.h:645
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:427
iterator_range< mop_iterator > uses()
Definition: MachineInstr.h:325
MachineOperand * findRegisterDefOperand(unsigned Reg, bool isDead=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
Definition: MachineInstr.h:912
iterator_range< mmo_iterator > memoperands() const
Definition: MachineInstr.h:347
iterator_range< const_mop_iterator > operands() const
Definition: MachineInstr.h:298
bool isConvertibleTo3Addr(QueryType Type=IgnoreBundle) const
Return true if this is a 2-address instruction which can be changed into a 3-address instruction if n...
Definition: MachineInstr.h:625
iterator_range< mop_iterator > explicit_operands()
Definition: MachineInstr.h:301
unsigned getFlags() const
Return flags of this instruction.
Definition: MCInstrDesc.h:194
bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:191
const DIExpression * getDebugExpression() const
Return the complex address expression referenced by this DBG_VALUE instruction.
Definition: MachineInstr.h:249
iterator_range< const_mop_iterator > defs() const
Definition: MachineInstr.h:321
bool isPseudo(QueryType Type=IgnoreBundle) const
Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction...
Definition: MachineInstr.h:395
This provides a very simple, boring adaptor for a begin and end iterator into a range type...
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:138
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:579
MachineOperand * findRegisterUseOperand(unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterUseOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
Definition: MachineInstr.h:894
unsigned getOperandNo(const_mop_iterator I) const
Returns the number of the operand iterator I points to.
Definition: MachineInstr.h:335
static bool isEqual(const MachineInstr *const &LHS, const MachineInstr *const &RHS)
bool isTied() const
bool isPredicable(QueryType Type=AllInBundle) const
Return true if this instruction has a predicate operand that controls execution.
Definition: MachineInstr.h:457
bool readsVirtualRegister(unsigned Reg) const
Return true if the MachineInstr reads the specified virtual register.
Definition: MachineInstr.h:844
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
void clearAsmPrinterFlag(CommentFlag Flag)
Clear specific AsmPrinter flags.
Definition: MachineInstr.h:140
Recycle small arrays allocated from a BumpPtrAllocator.
Definition: ArrayRecycler.h:30
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:264
bool isCFIInstruction() const
Definition: MachineInstr.h:741
A debug info location.
Definition: DebugLoc.h:34
Manage lifetime of a slot tracker for printing IR.
iterator_range< mmo_iterator > memoperands()
Definition: MachineInstr.h:344
MachineOperand & getOperand(unsigned i)
Definition: MachineInstr.h:277
bool canFoldAsLoad(QueryType Type=IgnoreBundle) const
Return true for instructions that can be folded as memory operands in other instructions.
Definition: MachineInstr.h:512
bool isConditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
Definition: MachineInstr.h:441
const MDNode * getMetadata() const
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:295
bool isExtractSubreg() const
Definition: MachineInstr.h:784
void setPhysRegsDeadExcept(ArrayRef< unsigned > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
bool isSelect(QueryType Type=IgnoreBundle) const
Return true if this instruction is a select instruction.
Definition: MachineInstr.h:480
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:419
const_mop_iterator operands_end() const
Definition: MachineInstr.h:293
Special DenseMapInfo traits to compare MachineInstr* by value of the instruction rather than by point...
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
const TargetRegisterClass * getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.
COPY - Target-independent register copy.
Definition: TargetOpcodes.h:86
void clearKillInfo()
Clears kill flags on all operands.
unsigned getBundleSize() const
Return the number of instructions inside the MI bundle, excluding the bundle header.
MachineMemOperand - A description of a memory reference used in the backend.
bool getAsmPrinterFlag(CommentFlag Flag) const
Return whether an AsmPrinter flag is set.
Definition: MachineInstr.h:130
iterator_range< const_mop_iterator > implicit_operands() const
Definition: MachineInstr.h:313
const HexagonInstrInfo * TII
bool isPHI() const
Definition: MachineInstr.h:757
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
std::pair< bool, bool > readsWritesVirtualRegister(unsigned Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:566
void addRegisterDefReadUndef(unsigned Reg)
Mark all subregister defs of register Reg with the undef flag.
Reg
All possible values of the reg field in the ModR/M byte.
MachineMemOperand ** mmo_iterator
Definition: MachineInstr.h:53
void bundleWithSucc()
Bundle this instruction with its successor.
ELFYAML::ELF_STO Other
Definition: ELFYAML.cpp:591
void eraseFromParentAndMarkDBGValuesForRemoval()
Unlink 'this' from the containing basic block and delete it.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:271
bool isBundledWithSucc() const
Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle...
Definition: MachineInstr.h:221
void unbundleFromPred()
Break bundle above this instruction.
bool hasTrivialDestructor() const
Check whether this has a trivial destructor.
Definition: DebugLoc.h:80
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
void clearMemRefs()
Clear this MachineInstr's memory reference descriptor list.
bool hasDelaySlot(QueryType Type=AnyInBundle) const
Returns true if the specified instruction has a delay slot which must be filled by the code generator...
Definition: MachineInstr.h:500
uint8_t getAsmPrinterFlags() const
Return the asm printer flags bitvector.
Definition: MachineInstr.h:124
bool isBundled() const
Return true if this instruction part of a bundle.
Definition: MachineInstr.h:211
bool hasExtraSrcRegAllocReq(QueryType Type=AnyInBundle) const
Returns true if this instruction source operands have special register allocation requirements that a...
Definition: MachineInstr.h:676
bool isBitcast(QueryType Type=IgnoreBundle) const
Return true if this instruction is a bitcast instruction.
Definition: MachineInstr.h:475
static MachineInstr * getEmptyKey()
bool isCopyLike() const
Return true if the instruction behaves like a copy.
Definition: MachineInstr.h:790
MachineBasicBlock * getParent()
Definition: MachineInstr.h:121
void untieRegOperand(unsigned OpIdx)
Break any tie involving OpIdx.
int64_t getImm() const
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
iterator_range< const_mop_iterator > uses() const
Definition: MachineInstr.h:329
bool isConvergent(QueryType Type=AnyInBundle) const
Return true if this instruction is convergent.
Definition: MachineInstr.h:494
void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo)
Clear all kill flags affecting Reg.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:267
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:97
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:120
TargetInstrInfo - Interface to description of machine instruction set.
bool isDebugValue() const
Definition: MachineInstr.h:748
bool isImplicitDef() const
Definition: MachineInstr.h:759
mmo_iterator memoperands_end() const
Definition: MachineInstr.h:341
bool isInsertSubreg() const
Definition: MachineInstr.h:766
DBG_VALUE - a mapping of the llvm.dbg.value intrinsic.
Definition: TargetOpcodes.h:69
bool isBundle() const
Definition: MachineInstr.h:775
IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
Definition: TargetOpcodes.h:52
unsigned findTiedOperandIdx(unsigned OpIdx) const
Given the index of a tied register operand, find the operand it is tied to.
static MachineInstr * getTombstoneKey()
#define P(N)
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:399
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
void print(raw_ostream &OS, bool SkipOpers=false) const
void clearRegisterDeads(unsigned Reg)
Clear all dead flags on operands defining register Reg.
int findRegisterDefOperandIdx(unsigned Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a def of the specified register or -1 if it is not found...
bool isAsCheapAsAMove(QueryType Type=AllInBundle) const
Returns true if this instruction has the same cost (or less) than a move instruction.
Definition: MachineInstr.h:665
bool isIndirectDebugValue() const
A DBG_VALUE is indirect iff the first operand is a register and the second operand is an immediate...
Definition: MachineInstr.h:751
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:273
bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx=nullptr) const
Given the index of a register def operand, check if the register def is tied to a source operand...
Definition: MachineInstr.h:995
INSERT_SUBREG - This instruction takes three operands: a register that has subregisters, a register providing an insert value, and a subregister index.
Definition: TargetOpcodes.h:49
bool isIndirectBranch(QueryType Type=AnyInBundle) const
Return true if this is an indirect branch, such as a branch through a register.
Definition: MachineInstr.h:433
bool isCopy() const
Definition: MachineInstr.h:778
void setFlag(MIFlag Flag)
Set a MI flag.
Definition: MachineInstr.h:155
void clearFlag(MIFlag Flag)
clearFlag - Clear a MI flag.
Definition: MachineInstr.h:166
int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo=nullptr) const
Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instructio...
bool isGCLabel() const
Definition: MachineInstr.h:737
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
bool isPosition() const
Definition: MachineInstr.h:746
bool isVariadic(QueryType Type=IgnoreBundle) const
Return true if this instruction can have a variable number of operands.
Definition: MachineInstr.h:383
iterator_range< mop_iterator > defs()
Definition: MachineInstr.h:317
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:150
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
Definition: MachineInstr.h:352
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore...
bool registerDefIsDead(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Returns true if the register is dead in this machine instruction.
Definition: MachineInstr.h:881
SI Fold Operands
bool isBundledWithPred() const
Return true if this instruction is part of a bundle, and it is not the first instruction in the bundl...
Definition: MachineInstr.h:217
bool isInvariantLoad(AliasAnalysis *AA) const
Return true if this instruction is loading from a location whose value is invariant across the functi...
bool isLabel() const
Returns true if the MachineInstr represents a label.
Definition: MachineInstr.h:740
unsigned getSubReg() const
static unsigned getHashValue(const MachineInstr *const &MI)
bool isNotDuplicable(QueryType Type=AnyInBundle) const
Return true if this instruction cannot be safely duplicated.
Definition: MachineInstr.h:487
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void emitError(StringRef Msg) const
Emit an error referring to the source location of this instruction.
bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
Definition: MachineInstr.h:866
void eraseFromBundle()
Unlink 'this' form its basic block and delete it.
REG_SEQUENCE - This variadic instruction is used to form a register that represents a consecutive seq...
Definition: TargetOpcodes.h:82
bool isInsertSubregLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions...
Definition: MachineInstr.h:555
bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
const_mop_iterator operands_begin() const
Definition: MachineInstr.h:292
bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
Definition: MachineInstr.h:836
int findRegisterUseOperandIdx(unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a use of the specific register or -1 if it is not found...
MachineInstr * removeFromBundle()
Unlink this instruction from its basic block and return it without deleting it.
bool memoperands_empty() const
Definition: MachineInstr.h:342
EXTRACT_SUBREG - This instruction takes two operands: a register that has subregisters, and a subregister index.
Definition: TargetOpcodes.h:41
const DILocalVariable * getDebugVariable() const
Return the debug variable referenced by this DBG_VALUE instruction.
Definition: MachineInstr.h:242
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
bool isMSInlineAsm() const
Definition: MachineInstr.h:761
bool isIdenticalTo(const MachineInstr *Other, MICheckType Check=CheckDefs) const
Return true if this instruction is identical to (same opcode and same operands as) the specified inst...
void setFlags(unsigned flags)
Definition: MachineInstr.h:159
MachineOperand class - Representation of each machine instruction operand.
bool isInlineAsm() const
Definition: MachineInstr.h:760
bool hasExtraDefRegAllocReq(QueryType Type=AnyInBundle) const
Returns true if this instruction def operands have special register allocation requirements that are ...
Definition: MachineInstr.h:686
MachineOperand * mop_iterator
iterator/begin/end - Iterate over all operands of a machine instruction.
Definition: MachineInstr.h:286
bool isIdentityCopy() const
Return true is the instruction is an identity copy.
Definition: MachineInstr.h:795
bool isKill() const
Definition: MachineInstr.h:758
bool isTransient() const
Return true if this is a transient instruction that is either very likely to be eliminated during reg...
Definition: MachineInstr.h:804
bool isCompare(QueryType Type=IgnoreBundle) const
Return true if this instruction is a comparison.
Definition: MachineInstr.h:464
DWARF expression.
unsigned short Opcode
Definition: MCInstrDesc.h:140
BUNDLE - This instruction represents an instruction bundle.
Definition: TargetOpcodes.h:91
void dump() const
void addRegisterDefined(unsigned Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
A range adaptor for a pair of iterators.
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
void setDebugLoc(DebugLoc dl)
Replace current source information with new such.
bool isSubregToReg() const
Definition: MachineInstr.h:769
iterator_range< mop_iterator > implicit_operands()
Definition: MachineInstr.h:309
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
bool isExtractSubregLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions...
Definition: MachineInstr.h:541
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:238
KILL - This instruction is a noop that is used only to adjust the liveness of registers.
Definition: TargetOpcodes.h:35
QueryType
API for querying MachineInstr properties.
Definition: MachineInstr.h:359
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
bool hasProperty(unsigned MCFlag, QueryType Type=AnyInBundle) const
Return true if the instruction (or in the case of a bundle, the instructions inside the bundle) has t...
Definition: MachineInstr.h:370
Representation of each machine instruction.
Definition: MachineInstr.h:51
void copyImplicitOps(MachineFunction &MF, const MachineInstr *MI)
Copy implicit register operands from specified instruction to this instruction.
ilist_node - Base class that provides next/prev services for nodes that use ilist_nextprev_traits or ...
Definition: ilist_node.h:43
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
Definition: MachineInstr.h:589
std::error_code Check(std::error_code Err)
#define I(x, y, z)
Definition: MD5.cpp:54
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:403
bool usesCustomInsertionHook(QueryType Type=IgnoreBundle) const
Return true if this instruction requires custom insertion support when the DAG scheduler is inserting...
Definition: MachineInstr.h:637
uint8_t getFlags() const
Return the MI flags bitvector.
Definition: MachineInstr.h:145
bool isEHLabel() const
Definition: MachineInstr.h:736
const TargetRegisterClass * getRegClassConstraintEffectForVReg(unsigned Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ExploreBundle=false) const
Applies the constraints (def/use) implied by this MI on Reg to the given CurRC.
raw_ostream & operator<<(raw_ostream &OS, const APInt &I)
Definition: APInt.h:1738
MachineInstr * removeFromParent()
Unlink 'this' from the containing basic block, and return it without deleting it. ...
iterator_range< const_mop_iterator > explicit_operands() const
Definition: MachineInstr.h:305
unsigned getReg() const
getReg - Returns the register number.
bool isCommutable(QueryType Type=IgnoreBundle) const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged.
Definition: MachineInstr.h:607
bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr kills the specified register.
Definition: MachineInstr.h:857
void clearAsmPrinterFlags()
Clear the AsmPrinter bitvector.
Definition: MachineInstr.h:127
void unbundleFromSucc()
Break bundle below this instruction.
unsigned isConstantValuePHI() const
If the specified instruction is a PHI that always merges together the same virtual register...
bool isRematerializable(QueryType Type=AllInBundle) const
Returns true if this instruction is a candidate for remat.
Definition: MachineInstr.h:653
mop_iterator operands_begin()
Definition: MachineInstr.h:289
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:38
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
bool addRegisterKilled(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:40
CommentFlag
Flags to specify different kinds of comments to output in assembly code.
Definition: MachineInstr.h:59
bool hasOptionalDef(QueryType Type=IgnoreBundle) const
Set if this instruction has an optional definition, e.g.
Definition: MachineInstr.h:389
SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except that the first operand is an imme...
Definition: TargetOpcodes.h:58
bool isStackAligningInlineAsm() const
void setAsmPrinterFlag(CommentFlag Flag)
Set a flag for the AsmPrinter.
Definition: MachineInstr.h:135
bool isRegSequence() const
Definition: MachineInstr.h:772
bool isMoveImmediate(QueryType Type=IgnoreBundle) const
Return true if this instruction is a move immediate (including conditional moves) instruction...
Definition: MachineInstr.h:470
bool isRegSequenceLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions.
Definition: MachineInstr.h:526
InlineAsm::AsmDialect getInlineAsmDialect() const
void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd)
Assign this MachineInstr's memory reference descriptor list.
const MachineOperand * const_mop_iterator
Definition: MachineInstr.h:287
bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
Definition: MachineInstr.h:874
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:410
bool isUnconditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which always transfers control flow to some other block...
Definition: MachineInstr.h:449
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:340
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.