LLVM  3.7.0
TargetLowering.cpp
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1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This implements the TargetLowering class.
11 //
12 //===----------------------------------------------------------------------===//
13 
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/CodeGen/Analysis.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/IR/DerivedTypes.h"
24 #include "llvm/IR/GlobalVariable.h"
25 #include "llvm/IR/LLVMContext.h"
26 #include "llvm/MC/MCAsmInfo.h"
27 #include "llvm/MC/MCExpr.h"
35 #include <cctype>
36 using namespace llvm;
37 
38 /// NOTE: The TargetMachine owns TLOF.
39 TargetLowering::TargetLowering(const TargetMachine &tm)
40  : TargetLoweringBase(tm) {}
41 
42 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
43  return nullptr;
44 }
45 
46 /// Check whether a given call node is in tail position within its function. If
47 /// so, it sets Chain to the input chain of the tail call.
49  SDValue &Chain) const {
50  const Function *F = DAG.getMachineFunction().getFunction();
51 
52  // Conservatively require the attributes of the call to match those of
53  // the return. Ignore noalias because it doesn't affect the call sequence.
54  AttributeSet CallerAttrs = F->getAttributes();
55  if (AttrBuilder(CallerAttrs, AttributeSet::ReturnIndex)
56  .removeAttribute(Attribute::NoAlias).hasAttributes())
57  return false;
58 
59  // It's not safe to eliminate the sign / zero extension of the return value.
62  return false;
63 
64  // Check if the only use is a function return node.
65  return isUsedByReturnOnly(Node, Chain);
66 }
67 
68 /// \brief Set CallLoweringInfo attribute flags based on a call instruction
69 /// and called function attributes.
71  unsigned AttrIdx) {
72  isSExt = CS->paramHasAttr(AttrIdx, Attribute::SExt);
73  isZExt = CS->paramHasAttr(AttrIdx, Attribute::ZExt);
74  isInReg = CS->paramHasAttr(AttrIdx, Attribute::InReg);
76  isNest = CS->paramHasAttr(AttrIdx, Attribute::Nest);
77  isByVal = CS->paramHasAttr(AttrIdx, Attribute::ByVal);
80  Alignment = CS->getParamAlignment(AttrIdx);
81 }
82 
83 /// Generate a libcall taking the given operands as arguments and returning a
84 /// result of type RetVT.
85 std::pair<SDValue, SDValue>
87  RTLIB::Libcall LC, EVT RetVT,
88  const SDValue *Ops, unsigned NumOps,
89  bool isSigned, SDLoc dl,
90  bool doesNotReturn,
91  bool isReturnValueUsed) const {
93  Args.reserve(NumOps);
94 
96  for (unsigned i = 0; i != NumOps; ++i) {
97  Entry.Node = Ops[i];
98  Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
99  Entry.isSExt = shouldSignExtendTypeInLibCall(Ops[i].getValueType(), isSigned);
100  Entry.isZExt = !shouldSignExtendTypeInLibCall(Ops[i].getValueType(), isSigned);
101  Args.push_back(Entry);
102  }
103  if (LC == RTLIB::UNKNOWN_LIBCALL)
104  report_fatal_error("Unsupported library call operation!");
105  SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
106  getPointerTy(DAG.getDataLayout()));
107 
108  Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
110  bool signExtend = shouldSignExtendTypeInLibCall(RetVT, isSigned);
111  CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
112  .setCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
113  .setNoReturn(doesNotReturn).setDiscardResult(!isReturnValueUsed)
114  .setSExtResult(signExtend).setZExtResult(!signExtend);
115  return LowerCallTo(CLI);
116 }
117 
118 
119 /// SoftenSetCCOperands - Soften the operands of a comparison. This code is
120 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
122  SDValue &NewLHS, SDValue &NewRHS,
123  ISD::CondCode &CCCode,
124  SDLoc dl) const {
125  assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128)
126  && "Unsupported setcc type!");
127 
128  // Expand into one or more soft-fp libcall(s).
130  switch (CCCode) {
131  case ISD::SETEQ:
132  case ISD::SETOEQ:
133  LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
135  break;
136  case ISD::SETNE:
137  case ISD::SETUNE:
138  LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 :
140  break;
141  case ISD::SETGE:
142  case ISD::SETOGE:
143  LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
145  break;
146  case ISD::SETLT:
147  case ISD::SETOLT:
148  LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
150  break;
151  case ISD::SETLE:
152  case ISD::SETOLE:
153  LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
155  break;
156  case ISD::SETGT:
157  case ISD::SETOGT:
158  LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
160  break;
161  case ISD::SETUO:
162  LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
164  break;
165  case ISD::SETO:
166  LC1 = (VT == MVT::f32) ? RTLIB::O_F32 :
167  (VT == MVT::f64) ? RTLIB::O_F64 : RTLIB::O_F128;
168  break;
169  default:
170  LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
172  switch (CCCode) {
173  case ISD::SETONE:
174  // SETONE = SETOLT | SETOGT
175  LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
177  // Fallthrough
178  case ISD::SETUGT:
179  LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
181  break;
182  case ISD::SETUGE:
183  LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
185  break;
186  case ISD::SETULT:
187  LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
189  break;
190  case ISD::SETULE:
191  LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
193  break;
194  case ISD::SETUEQ:
195  LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
197  break;
198  default: llvm_unreachable("Do not know how to soften this setcc!");
199  }
200  }
201 
202  // Use the target specific return value for comparions lib calls.
203  EVT RetVT = getCmpLibcallReturnType();
204  SDValue Ops[2] = { NewLHS, NewRHS };
205  NewLHS = makeLibCall(DAG, LC1, RetVT, Ops, 2, false/*sign irrelevant*/,
206  dl).first;
207  NewRHS = DAG.getConstant(0, dl, RetVT);
208  CCCode = getCmpLibcallCC(LC1);
209  if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
210  SDValue Tmp = DAG.getNode(
211  ISD::SETCC, dl,
212  getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), RetVT),
213  NewLHS, NewRHS, DAG.getCondCode(CCCode));
214  NewLHS = makeLibCall(DAG, LC2, RetVT, Ops, 2, false/*sign irrelevant*/,
215  dl).first;
216  NewLHS = DAG.getNode(
217  ISD::SETCC, dl,
218  getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), RetVT),
219  NewLHS, NewRHS, DAG.getCondCode(getCmpLibcallCC(LC2)));
220  NewLHS = DAG.getNode(ISD::OR, dl, Tmp.getValueType(), Tmp, NewLHS);
221  NewRHS = SDValue();
222  }
223 }
224 
225 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
226 /// current function. The returned value is a member of the
227 /// MachineJumpTableInfo::JTEntryKind enum.
229  // In non-pic modes, just use the address of a block.
230  if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
232 
233  // In PIC mode, if the target supports a GPRel32 directive, use it.
234  if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != nullptr)
236 
237  // Otherwise, use a label difference.
239 }
240 
242  SelectionDAG &DAG) const {
243  // If our PIC model is GP relative, use the global offset table as the base.
244  unsigned JTEncoding = getJumpTableEncoding();
245 
246  if ((JTEncoding == MachineJumpTableInfo::EK_GPRel64BlockAddress) ||
249 
250  return Table;
251 }
252 
253 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
254 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
255 /// MCExpr.
256 const MCExpr *
258  unsigned JTI,MCContext &Ctx) const{
259  // The normal PIC reloc base is the label at the start of the jump table.
260  return MCSymbolRefExpr::create(MF->getJTISymbol(JTI, Ctx), Ctx);
261 }
262 
263 bool
265  // Assume that everything is safe in static mode.
266  if (getTargetMachine().getRelocationModel() == Reloc::Static)
267  return true;
268 
269  // In dynamic-no-pic mode, assume that known defined values are safe.
270  if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
271  GA && GA->getGlobal()->isStrongDefinitionForLinker())
272  return true;
273 
274  // Otherwise assume nothing is safe.
275  return false;
276 }
277 
278 //===----------------------------------------------------------------------===//
279 // Optimization Methods
280 //===----------------------------------------------------------------------===//
281 
282 /// ShrinkDemandedConstant - Check to see if the specified operand of the
283 /// specified instruction is a constant integer. If so, check to see if there
284 /// are any bits set in the constant that are not demanded. If so, shrink the
285 /// constant and return true.
287  const APInt &Demanded) {
288  SDLoc dl(Op);
289 
290  // FIXME: ISD::SELECT, ISD::SELECT_CC
291  switch (Op.getOpcode()) {
292  default: break;
293  case ISD::XOR:
294  case ISD::AND:
295  case ISD::OR: {
297  if (!C) return false;
298 
299  if (Op.getOpcode() == ISD::XOR &&
300  (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
301  return false;
302 
303  // if we can expand it to have all bits set, do it
304  if (C->getAPIntValue().intersects(~Demanded)) {
305  EVT VT = Op.getValueType();
306  SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
307  DAG.getConstant(Demanded &
308  C->getAPIntValue(),
309  dl, VT));
310  return CombineTo(Op, New);
311  }
312 
313  break;
314  }
315  }
316 
317  return false;
318 }
319 
320 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
321 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
322 /// cast, but it could be generalized for targets with other types of
323 /// implicit widening casts.
324 bool
326  unsigned BitWidth,
327  const APInt &Demanded,
328  SDLoc dl) {
329  assert(Op.getNumOperands() == 2 &&
330  "ShrinkDemandedOp only supports binary operators!");
331  assert(Op.getNode()->getNumValues() == 1 &&
332  "ShrinkDemandedOp only supports nodes with one result!");
333 
334  // Early return, as this function cannot handle vector types.
335  if (Op.getValueType().isVector())
336  return false;
337 
338  // Don't do this if the node has another user, which may require the
339  // full value.
340  if (!Op.getNode()->hasOneUse())
341  return false;
342 
343  // Search for the smallest integer type with free casts to and from
344  // Op's type. For expedience, just check power-of-2 integer types.
345  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
346  unsigned DemandedSize = BitWidth - Demanded.countLeadingZeros();
347  unsigned SmallVTBits = DemandedSize;
348  if (!isPowerOf2_32(SmallVTBits))
349  SmallVTBits = NextPowerOf2(SmallVTBits);
350  for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
351  EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
352  if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
353  TLI.isZExtFree(SmallVT, Op.getValueType())) {
354  // We found a type with free casts.
355  SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
356  DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
357  Op.getNode()->getOperand(0)),
358  DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
359  Op.getNode()->getOperand(1)));
360  bool NeedZext = DemandedSize > SmallVTBits;
361  SDValue Z = DAG.getNode(NeedZext ? ISD::ZERO_EXTEND : ISD::ANY_EXTEND,
362  dl, Op.getValueType(), X);
363  return CombineTo(Op, Z);
364  }
365  }
366  return false;
367 }
368 
369 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
370 /// DemandedMask bits of the result of Op are ever used downstream. If we can
371 /// use this information to simplify Op, create a new simplified DAG node and
372 /// return true, returning the original and new nodes in Old and New. Otherwise,
373 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
374 /// the expression (used to simplify the caller). The KnownZero/One bits may
375 /// only be accurate for those bits in the DemandedMask.
377  const APInt &DemandedMask,
378  APInt &KnownZero,
379  APInt &KnownOne,
380  TargetLoweringOpt &TLO,
381  unsigned Depth) const {
382  unsigned BitWidth = DemandedMask.getBitWidth();
383  assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
384  "Mask size mismatches value type size!");
385  APInt NewMask = DemandedMask;
386  SDLoc dl(Op);
387  auto &DL = TLO.DAG.getDataLayout();
388 
389  // Don't know anything.
390  KnownZero = KnownOne = APInt(BitWidth, 0);
391 
392  // Other users may use these bits.
393  if (!Op.getNode()->hasOneUse()) {
394  if (Depth != 0) {
395  // If not at the root, Just compute the KnownZero/KnownOne bits to
396  // simplify things downstream.
397  TLO.DAG.computeKnownBits(Op, KnownZero, KnownOne, Depth);
398  return false;
399  }
400  // If this is the root being simplified, allow it to have multiple uses,
401  // just set the NewMask to all bits.
402  NewMask = APInt::getAllOnesValue(BitWidth);
403  } else if (DemandedMask == 0) {
404  // Not demanding any bits from Op.
405  if (Op.getOpcode() != ISD::UNDEF)
406  return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
407  return false;
408  } else if (Depth == 6) { // Limit search depth.
409  return false;
410  }
411 
412  APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
413  switch (Op.getOpcode()) {
414  case ISD::Constant:
415  // We know all of the bits for a constant!
416  KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue();
417  KnownZero = ~KnownOne;
418  return false; // Don't fall through, will infinitely loop.
419  case ISD::AND:
420  // If the RHS is a constant, check to see if the LHS would be zero without
421  // using the bits from the RHS. Below, we use knowledge about the RHS to
422  // simplify the LHS, here we're using information from the LHS to simplify
423  // the RHS.
424  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
425  APInt LHSZero, LHSOne;
426  // Do not increment Depth here; that can cause an infinite loop.
427  TLO.DAG.computeKnownBits(Op.getOperand(0), LHSZero, LHSOne, Depth);
428  // If the LHS already has zeros where RHSC does, this and is dead.
429  if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
430  return TLO.CombineTo(Op, Op.getOperand(0));
431  // If any of the set bits in the RHS are known zero on the LHS, shrink
432  // the constant.
433  if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
434  return true;
435  }
436 
437  if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
438  KnownOne, TLO, Depth+1))
439  return true;
440  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
441  if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
442  KnownZero2, KnownOne2, TLO, Depth+1))
443  return true;
444  assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
445 
446  // If all of the demanded bits are known one on one side, return the other.
447  // These bits cannot contribute to the result of the 'and'.
448  if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
449  return TLO.CombineTo(Op, Op.getOperand(0));
450  if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
451  return TLO.CombineTo(Op, Op.getOperand(1));
452  // If all of the demanded bits in the inputs are known zeros, return zero.
453  if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
454  return TLO.CombineTo(Op, TLO.DAG.getConstant(0, dl, Op.getValueType()));
455  // If the RHS is a constant, see if we can simplify it.
456  if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
457  return true;
458  // If the operation can be done in a smaller type, do so.
459  if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
460  return true;
461 
462  // Output known-1 bits are only known if set in both the LHS & RHS.
463  KnownOne &= KnownOne2;
464  // Output known-0 are known to be clear if zero in either the LHS | RHS.
465  KnownZero |= KnownZero2;
466  break;
467  case ISD::OR:
468  if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
469  KnownOne, TLO, Depth+1))
470  return true;
471  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
472  if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
473  KnownZero2, KnownOne2, TLO, Depth+1))
474  return true;
475  assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
476 
477  // If all of the demanded bits are known zero on one side, return the other.
478  // These bits cannot contribute to the result of the 'or'.
479  if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
480  return TLO.CombineTo(Op, Op.getOperand(0));
481  if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
482  return TLO.CombineTo(Op, Op.getOperand(1));
483  // If all of the potentially set bits on one side are known to be set on
484  // the other side, just use the 'other' side.
485  if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
486  return TLO.CombineTo(Op, Op.getOperand(0));
487  if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
488  return TLO.CombineTo(Op, Op.getOperand(1));
489  // If the RHS is a constant, see if we can simplify it.
490  if (TLO.ShrinkDemandedConstant(Op, NewMask))
491  return true;
492  // If the operation can be done in a smaller type, do so.
493  if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
494  return true;
495 
496  // Output known-0 bits are only known if clear in both the LHS & RHS.
497  KnownZero &= KnownZero2;
498  // Output known-1 are known to be set if set in either the LHS | RHS.
499  KnownOne |= KnownOne2;
500  break;
501  case ISD::XOR:
502  if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
503  KnownOne, TLO, Depth+1))
504  return true;
505  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
506  if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
507  KnownOne2, TLO, Depth+1))
508  return true;
509  assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
510 
511  // If all of the demanded bits are known zero on one side, return the other.
512  // These bits cannot contribute to the result of the 'xor'.
513  if ((KnownZero & NewMask) == NewMask)
514  return TLO.CombineTo(Op, Op.getOperand(0));
515  if ((KnownZero2 & NewMask) == NewMask)
516  return TLO.CombineTo(Op, Op.getOperand(1));
517  // If the operation can be done in a smaller type, do so.
518  if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
519  return true;
520 
521  // If all of the unknown bits are known to be zero on one side or the other
522  // (but not both) turn this into an *inclusive* or.
523  // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
524  if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
525  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
526  Op.getOperand(0),
527  Op.getOperand(1)));
528 
529  // Output known-0 bits are known if clear or set in both the LHS & RHS.
530  KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
531  // Output known-1 are known to be set if set in only one of the LHS, RHS.
532  KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
533 
534  // If all of the demanded bits on one side are known, and all of the set
535  // bits on that side are also known to be set on the other side, turn this
536  // into an AND, as we know the bits will be cleared.
537  // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
538  // NB: it is okay if more bits are known than are requested
539  if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known on one side
540  if (KnownOne == KnownOne2) { // set bits are the same on both sides
541  EVT VT = Op.getValueType();
542  SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, dl, VT);
543  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
544  Op.getOperand(0), ANDC));
545  }
546  }
547 
548  // If the RHS is a constant, see if we can simplify it.
549  // for XOR, we prefer to force bits to 1 if they will make a -1.
550  // if we can't force bits, try to shrink constant
551  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
552  APInt Expanded = C->getAPIntValue() | (~NewMask);
553  // if we can expand it to have all bits set, do it
554  if (Expanded.isAllOnesValue()) {
555  if (Expanded != C->getAPIntValue()) {
556  EVT VT = Op.getValueType();
557  SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
558  TLO.DAG.getConstant(Expanded, dl, VT));
559  return TLO.CombineTo(Op, New);
560  }
561  // if it already has all the bits set, nothing to change
562  // but don't shrink either!
563  } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
564  return true;
565  }
566  }
567 
568  KnownZero = KnownZeroOut;
569  KnownOne = KnownOneOut;
570  break;
571  case ISD::SELECT:
572  if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
573  KnownOne, TLO, Depth+1))
574  return true;
575  if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
576  KnownOne2, TLO, Depth+1))
577  return true;
578  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
579  assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
580 
581  // If the operands are constants, see if we can simplify them.
582  if (TLO.ShrinkDemandedConstant(Op, NewMask))
583  return true;
584 
585  // Only known if known in both the LHS and RHS.
586  KnownOne &= KnownOne2;
587  KnownZero &= KnownZero2;
588  break;
589  case ISD::SELECT_CC:
590  if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
591  KnownOne, TLO, Depth+1))
592  return true;
593  if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
594  KnownOne2, TLO, Depth+1))
595  return true;
596  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
597  assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
598 
599  // If the operands are constants, see if we can simplify them.
600  if (TLO.ShrinkDemandedConstant(Op, NewMask))
601  return true;
602 
603  // Only known if known in both the LHS and RHS.
604  KnownOne &= KnownOne2;
605  KnownZero &= KnownZero2;
606  break;
607  case ISD::SHL:
608  if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
609  unsigned ShAmt = SA->getZExtValue();
610  SDValue InOp = Op.getOperand(0);
611 
612  // If the shift count is an invalid immediate, don't do anything.
613  if (ShAmt >= BitWidth)
614  break;
615 
616  // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
617  // single shift. We can do this if the bottom bits (which are shifted
618  // out) are never demanded.
619  if (InOp.getOpcode() == ISD::SRL &&
620  isa<ConstantSDNode>(InOp.getOperand(1))) {
621  if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
622  unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
623  unsigned Opc = ISD::SHL;
624  int Diff = ShAmt-C1;
625  if (Diff < 0) {
626  Diff = -Diff;
627  Opc = ISD::SRL;
628  }
629 
630  SDValue NewSA =
631  TLO.DAG.getConstant(Diff, dl, Op.getOperand(1).getValueType());
632  EVT VT = Op.getValueType();
633  return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
634  InOp.getOperand(0), NewSA));
635  }
636  }
637 
638  if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
639  KnownZero, KnownOne, TLO, Depth+1))
640  return true;
641 
642  // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
643  // are not demanded. This will likely allow the anyext to be folded away.
644  if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
645  SDValue InnerOp = InOp.getNode()->getOperand(0);
646  EVT InnerVT = InnerOp.getValueType();
647  unsigned InnerBits = InnerVT.getSizeInBits();
648  if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 &&
649  isTypeDesirableForOp(ISD::SHL, InnerVT)) {
650  EVT ShTy = getShiftAmountTy(InnerVT, DL);
651  if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
652  ShTy = InnerVT;
653  SDValue NarrowShl =
654  TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
655  TLO.DAG.getConstant(ShAmt, dl, ShTy));
656  return
657  TLO.CombineTo(Op,
658  TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
659  NarrowShl));
660  }
661  // Repeat the SHL optimization above in cases where an extension
662  // intervenes: (shl (anyext (shr x, c1)), c2) to
663  // (shl (anyext x), c2-c1). This requires that the bottom c1 bits
664  // aren't demanded (as above) and that the shifted upper c1 bits of
665  // x aren't demanded.
666  if (InOp.hasOneUse() &&
667  InnerOp.getOpcode() == ISD::SRL &&
668  InnerOp.hasOneUse() &&
669  isa<ConstantSDNode>(InnerOp.getOperand(1))) {
670  uint64_t InnerShAmt = cast<ConstantSDNode>(InnerOp.getOperand(1))
671  ->getZExtValue();
672  if (InnerShAmt < ShAmt &&
673  InnerShAmt < InnerBits &&
674  NewMask.lshr(InnerBits - InnerShAmt + ShAmt) == 0 &&
675  NewMask.trunc(ShAmt) == 0) {
676  SDValue NewSA =
677  TLO.DAG.getConstant(ShAmt - InnerShAmt, dl,
678  Op.getOperand(1).getValueType());
679  EVT VT = Op.getValueType();
680  SDValue NewExt = TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT,
681  InnerOp.getOperand(0));
682  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, VT,
683  NewExt, NewSA));
684  }
685  }
686  }
687 
688  KnownZero <<= SA->getZExtValue();
689  KnownOne <<= SA->getZExtValue();
690  // low bits known zero.
691  KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
692  }
693  break;
694  case ISD::SRL:
695  if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
696  EVT VT = Op.getValueType();
697  unsigned ShAmt = SA->getZExtValue();
698  unsigned VTSize = VT.getSizeInBits();
699  SDValue InOp = Op.getOperand(0);
700 
701  // If the shift count is an invalid immediate, don't do anything.
702  if (ShAmt >= BitWidth)
703  break;
704 
705  APInt InDemandedMask = (NewMask << ShAmt);
706 
707  // If the shift is exact, then it does demand the low bits (and knows that
708  // they are zero).
709  if (cast<BinaryWithFlagsSDNode>(Op)->Flags.hasExact())
710  InDemandedMask |= APInt::getLowBitsSet(BitWidth, ShAmt);
711 
712  // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
713  // single shift. We can do this if the top bits (which are shifted out)
714  // are never demanded.
715  if (InOp.getOpcode() == ISD::SHL &&
716  isa<ConstantSDNode>(InOp.getOperand(1))) {
717  if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
718  unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
719  unsigned Opc = ISD::SRL;
720  int Diff = ShAmt-C1;
721  if (Diff < 0) {
722  Diff = -Diff;
723  Opc = ISD::SHL;
724  }
725 
726  SDValue NewSA =
727  TLO.DAG.getConstant(Diff, dl, Op.getOperand(1).getValueType());
728  return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
729  InOp.getOperand(0), NewSA));
730  }
731  }
732 
733  // Compute the new bits that are at the top now.
734  if (SimplifyDemandedBits(InOp, InDemandedMask,
735  KnownZero, KnownOne, TLO, Depth+1))
736  return true;
737  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
738  KnownZero = KnownZero.lshr(ShAmt);
739  KnownOne = KnownOne.lshr(ShAmt);
740 
741  APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
742  KnownZero |= HighBits; // High bits known zero.
743  }
744  break;
745  case ISD::SRA:
746  // If this is an arithmetic shift right and only the low-bit is set, we can
747  // always convert this into a logical shr, even if the shift amount is
748  // variable. The low bit of the shift cannot be an input sign bit unless
749  // the shift amount is >= the size of the datatype, which is undefined.
750  if (NewMask == 1)
751  return TLO.CombineTo(Op,
752  TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
753  Op.getOperand(0), Op.getOperand(1)));
754 
755  if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
756  EVT VT = Op.getValueType();
757  unsigned ShAmt = SA->getZExtValue();
758 
759  // If the shift count is an invalid immediate, don't do anything.
760  if (ShAmt >= BitWidth)
761  break;
762 
763  APInt InDemandedMask = (NewMask << ShAmt);
764 
765  // If the shift is exact, then it does demand the low bits (and knows that
766  // they are zero).
767  if (cast<BinaryWithFlagsSDNode>(Op)->Flags.hasExact())
768  InDemandedMask |= APInt::getLowBitsSet(BitWidth, ShAmt);
769 
770  // If any of the demanded bits are produced by the sign extension, we also
771  // demand the input sign bit.
772  APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
773  if (HighBits.intersects(NewMask))
774  InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
775 
776  if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
777  KnownZero, KnownOne, TLO, Depth+1))
778  return true;
779  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
780  KnownZero = KnownZero.lshr(ShAmt);
781  KnownOne = KnownOne.lshr(ShAmt);
782 
783  // Handle the sign bit, adjusted to where it is now in the mask.
784  APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
785 
786  // If the input sign bit is known to be zero, or if none of the top bits
787  // are demanded, turn this into an unsigned shift right.
788  if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
790  Flags.setExact(cast<BinaryWithFlagsSDNode>(Op)->Flags.hasExact());
791  return TLO.CombineTo(Op,
792  TLO.DAG.getNode(ISD::SRL, dl, VT, Op.getOperand(0),
793  Op.getOperand(1), &Flags));
794  }
795 
796  int Log2 = NewMask.exactLogBase2();
797  if (Log2 >= 0) {
798  // The bit must come from the sign.
799  SDValue NewSA =
800  TLO.DAG.getConstant(BitWidth - 1 - Log2, dl,
801  Op.getOperand(1).getValueType());
802  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
803  Op.getOperand(0), NewSA));
804  }
805 
806  if (KnownOne.intersects(SignBit))
807  // New bits are known one.
808  KnownOne |= HighBits;
809  }
810  break;
811  case ISD::SIGN_EXTEND_INREG: {
812  EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
813 
814  APInt MsbMask = APInt::getHighBitsSet(BitWidth, 1);
815  // If we only care about the highest bit, don't bother shifting right.
816  if (MsbMask == NewMask) {
817  unsigned ShAmt = ExVT.getScalarType().getSizeInBits();
818  SDValue InOp = Op.getOperand(0);
819  unsigned VTBits = Op->getValueType(0).getScalarType().getSizeInBits();
820  bool AlreadySignExtended =
821  TLO.DAG.ComputeNumSignBits(InOp) >= VTBits-ShAmt+1;
822  // However if the input is already sign extended we expect the sign
823  // extension to be dropped altogether later and do not simplify.
824  if (!AlreadySignExtended) {
825  // Compute the correct shift amount type, which must be getShiftAmountTy
826  // for scalar types after legalization.
827  EVT ShiftAmtTy = Op.getValueType();
828  if (TLO.LegalTypes() && !ShiftAmtTy.isVector())
829  ShiftAmtTy = getShiftAmountTy(ShiftAmtTy, DL);
830 
831  SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, dl,
832  ShiftAmtTy);
833  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
834  Op.getValueType(), InOp,
835  ShiftAmt));
836  }
837  }
838 
839  // Sign extension. Compute the demanded bits in the result that are not
840  // present in the input.
841  APInt NewBits =
842  APInt::getHighBitsSet(BitWidth,
843  BitWidth - ExVT.getScalarType().getSizeInBits());
844 
845  // If none of the extended bits are demanded, eliminate the sextinreg.
846  if ((NewBits & NewMask) == 0)
847  return TLO.CombineTo(Op, Op.getOperand(0));
848 
849  APInt InSignBit =
850  APInt::getSignBit(ExVT.getScalarType().getSizeInBits()).zext(BitWidth);
851  APInt InputDemandedBits =
852  APInt::getLowBitsSet(BitWidth,
853  ExVT.getScalarType().getSizeInBits()) &
854  NewMask;
855 
856  // Since the sign extended bits are demanded, we know that the sign
857  // bit is demanded.
858  InputDemandedBits |= InSignBit;
859 
860  if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
861  KnownZero, KnownOne, TLO, Depth+1))
862  return true;
863  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
864 
865  // If the sign bit of the input is known set or clear, then we know the
866  // top bits of the result.
867 
868  // If the input sign bit is known zero, convert this into a zero extension.
869  if (KnownZero.intersects(InSignBit))
870  return TLO.CombineTo(Op,
871  TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,ExVT));
872 
873  if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
874  KnownOne |= NewBits;
875  KnownZero &= ~NewBits;
876  } else { // Input sign bit unknown
877  KnownZero &= ~NewBits;
878  KnownOne &= ~NewBits;
879  }
880  break;
881  }
882  case ISD::BUILD_PAIR: {
883  EVT HalfVT = Op.getOperand(0).getValueType();
884  unsigned HalfBitWidth = HalfVT.getScalarSizeInBits();
885 
886  APInt MaskLo = NewMask.getLoBits(HalfBitWidth).trunc(HalfBitWidth);
887  APInt MaskHi = NewMask.getHiBits(HalfBitWidth).trunc(HalfBitWidth);
888 
889  APInt KnownZeroLo, KnownOneLo;
890  APInt KnownZeroHi, KnownOneHi;
891 
892  if (SimplifyDemandedBits(Op.getOperand(0), MaskLo, KnownZeroLo,
893  KnownOneLo, TLO, Depth + 1))
894  return true;
895 
896  if (SimplifyDemandedBits(Op.getOperand(1), MaskHi, KnownZeroHi,
897  KnownOneHi, TLO, Depth + 1))
898  return true;
899 
900  KnownZero = KnownZeroLo.zext(BitWidth) |
901  KnownZeroHi.zext(BitWidth).shl(HalfBitWidth);
902 
903  KnownOne = KnownOneLo.zext(BitWidth) |
904  KnownOneHi.zext(BitWidth).shl(HalfBitWidth);
905  break;
906  }
907  case ISD::ZERO_EXTEND: {
908  unsigned OperandBitWidth =
910  APInt InMask = NewMask.trunc(OperandBitWidth);
911 
912  // If none of the top bits are demanded, convert this into an any_extend.
913  APInt NewBits =
914  APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
915  if (!NewBits.intersects(NewMask))
916  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
917  Op.getValueType(),
918  Op.getOperand(0)));
919 
920  if (SimplifyDemandedBits(Op.getOperand(0), InMask,
921  KnownZero, KnownOne, TLO, Depth+1))
922  return true;
923  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
924  KnownZero = KnownZero.zext(BitWidth);
925  KnownOne = KnownOne.zext(BitWidth);
926  KnownZero |= NewBits;
927  break;
928  }
929  case ISD::SIGN_EXTEND: {
930  EVT InVT = Op.getOperand(0).getValueType();
931  unsigned InBits = InVT.getScalarType().getSizeInBits();
932  APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
933  APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
934  APInt NewBits = ~InMask & NewMask;
935 
936  // If none of the top bits are demanded, convert this into an any_extend.
937  if (NewBits == 0)
938  return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
939  Op.getValueType(),
940  Op.getOperand(0)));
941 
942  // Since some of the sign extended bits are demanded, we know that the sign
943  // bit is demanded.
944  APInt InDemandedBits = InMask & NewMask;
945  InDemandedBits |= InSignBit;
946  InDemandedBits = InDemandedBits.trunc(InBits);
947 
948  if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
949  KnownOne, TLO, Depth+1))
950  return true;
951  KnownZero = KnownZero.zext(BitWidth);
952  KnownOne = KnownOne.zext(BitWidth);
953 
954  // If the sign bit is known zero, convert this to a zero extend.
955  if (KnownZero.intersects(InSignBit))
956  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
957  Op.getValueType(),
958  Op.getOperand(0)));
959 
960  // If the sign bit is known one, the top bits match.
961  if (KnownOne.intersects(InSignBit)) {
962  KnownOne |= NewBits;
963  assert((KnownZero & NewBits) == 0);
964  } else { // Otherwise, top bits aren't known.
965  assert((KnownOne & NewBits) == 0);
966  assert((KnownZero & NewBits) == 0);
967  }
968  break;
969  }
970  case ISD::ANY_EXTEND: {
971  unsigned OperandBitWidth =
973  APInt InMask = NewMask.trunc(OperandBitWidth);
974  if (SimplifyDemandedBits(Op.getOperand(0), InMask,
975  KnownZero, KnownOne, TLO, Depth+1))
976  return true;
977  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
978  KnownZero = KnownZero.zext(BitWidth);
979  KnownOne = KnownOne.zext(BitWidth);
980  break;
981  }
982  case ISD::TRUNCATE: {
983  // Simplify the input, using demanded bit information, and compute the known
984  // zero/one bits live out.
985  unsigned OperandBitWidth =
987  APInt TruncMask = NewMask.zext(OperandBitWidth);
988  if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
989  KnownZero, KnownOne, TLO, Depth+1))
990  return true;
991  KnownZero = KnownZero.trunc(BitWidth);
992  KnownOne = KnownOne.trunc(BitWidth);
993 
994  // If the input is only used by this truncate, see if we can shrink it based
995  // on the known demanded bits.
996  if (Op.getOperand(0).getNode()->hasOneUse()) {
997  SDValue In = Op.getOperand(0);
998  switch (In.getOpcode()) {
999  default: break;
1000  case ISD::SRL:
1001  // Shrink SRL by a constant if none of the high bits shifted in are
1002  // demanded.
1003  if (TLO.LegalTypes() &&
1005  // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
1006  // undesirable.
1007  break;
1009  if (!ShAmt)
1010  break;
1011  SDValue Shift = In.getOperand(1);
1012  if (TLO.LegalTypes()) {
1013  uint64_t ShVal = ShAmt->getZExtValue();
1014  Shift = TLO.DAG.getConstant(ShVal, dl,
1016  }
1017 
1018  APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
1019  OperandBitWidth - BitWidth);
1020  HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth);
1021 
1022  if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1023  // None of the shifted in bits are needed. Add a truncate of the
1024  // shift input, then shift it.
1025  SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
1026  Op.getValueType(),
1027  In.getOperand(0));
1028  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1029  Op.getValueType(),
1030  NewTrunc,
1031  Shift));
1032  }
1033  break;
1034  }
1035  }
1036 
1037  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1038  break;
1039  }
1040  case ISD::AssertZext: {
1041  // AssertZext demands all of the high bits, plus any of the low bits
1042  // demanded by its users.
1043  EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1044  APInt InMask = APInt::getLowBitsSet(BitWidth,
1045  VT.getSizeInBits());
1046  if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask,
1047  KnownZero, KnownOne, TLO, Depth+1))
1048  return true;
1049  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1050 
1051  KnownZero |= ~InMask & NewMask;
1052  break;
1053  }
1054  case ISD::BITCAST:
1055  // If this is an FP->Int bitcast and if the sign bit is the only
1056  // thing demanded, turn this into a FGETSIGN.
1057  if (!TLO.LegalOperations() &&
1058  !Op.getValueType().isVector() &&
1059  !Op.getOperand(0).getValueType().isVector() &&
1060  NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) &&
1062  bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType());
1064  if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) {
1065  EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32;
1066  // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1067  // place. We expect the SHL to be eliminated by other optimizations.
1068  SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
1069  unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits();
1070  if (!OpVTLegal && OpVTSizeInBits > 32)
1071  Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign);
1072  unsigned ShVal = Op.getValueType().getSizeInBits()-1;
1073  SDValue ShAmt = TLO.DAG.getConstant(ShVal, dl, Op.getValueType());
1074  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1075  Op.getValueType(),
1076  Sign, ShAmt));
1077  }
1078  }
1079  break;
1080  case ISD::ADD:
1081  case ISD::MUL:
1082  case ISD::SUB: {
1083  // Add, Sub, and Mul don't demand any bits in positions beyond that
1084  // of the highest bit demanded of them.
1085  APInt LoMask = APInt::getLowBitsSet(BitWidth,
1086  BitWidth - NewMask.countLeadingZeros());
1087  if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1088  KnownOne2, TLO, Depth+1))
1089  return true;
1090  if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1091  KnownOne2, TLO, Depth+1))
1092  return true;
1093  // See if the operation should be performed at a smaller bit width.
1094  if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1095  return true;
1096  }
1097  // FALL THROUGH
1098  default:
1099  // Just use computeKnownBits to compute output bits.
1100  TLO.DAG.computeKnownBits(Op, KnownZero, KnownOne, Depth);
1101  break;
1102  }
1103 
1104  // If we know the value of all of the demanded bits, return this as a
1105  // constant.
1106  if ((NewMask & (KnownZero|KnownOne)) == NewMask) {
1107  // Avoid folding to a constant if any OpaqueConstant is involved.
1108  const SDNode *N = Op.getNode();
1110  E = SDNodeIterator::end(N); I != E; ++I) {
1111  SDNode *Op = *I;
1112  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
1113  if (C->isOpaque())
1114  return false;
1115  }
1116  return TLO.CombineTo(Op,
1117  TLO.DAG.getConstant(KnownOne, dl, Op.getValueType()));
1118  }
1119 
1120  return false;
1121 }
1122 
1123 /// computeKnownBitsForTargetNode - Determine which of the bits specified
1124 /// in Mask are known to be either zero or one and return them in the
1125 /// KnownZero/KnownOne bitsets.
1127  APInt &KnownZero,
1128  APInt &KnownOne,
1129  const SelectionDAG &DAG,
1130  unsigned Depth) const {
1131  assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1134  Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1135  "Should use MaskedValueIsZero if you don't know whether Op"
1136  " is a target node!");
1137  KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0);
1138 }
1139 
1140 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
1141 /// targets that want to expose additional information about sign bits to the
1142 /// DAG Combiner.
1144  const SelectionDAG &,
1145  unsigned Depth) const {
1146  assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1149  Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1150  "Should use ComputeNumSignBits if you don't know whether Op"
1151  " is a target node!");
1152  return 1;
1153 }
1154 
1155 /// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1156 /// one bit set. This differs from computeKnownBits in that it doesn't need to
1157 /// determine which bit is set.
1158 ///
1159 static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
1160  // A left-shift of a constant one will have exactly one bit set, because
1161  // shifting the bit off the end is undefined.
1162  if (Val.getOpcode() == ISD::SHL)
1163  if (ConstantSDNode *C =
1164  dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1165  if (C->getAPIntValue() == 1)
1166  return true;
1167 
1168  // Similarly, a right-shift of a constant sign-bit will have exactly
1169  // one bit set.
1170  if (Val.getOpcode() == ISD::SRL)
1171  if (ConstantSDNode *C =
1172  dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1173  if (C->getAPIntValue().isSignBit())
1174  return true;
1175 
1176  // More could be done here, though the above checks are enough
1177  // to handle some common cases.
1178 
1179  // Fall back to computeKnownBits to catch other known cases.
1180  EVT OpVT = Val.getValueType();
1181  unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
1182  APInt KnownZero, KnownOne;
1183  DAG.computeKnownBits(Val, KnownZero, KnownOne);
1184  return (KnownZero.countPopulation() == BitWidth - 1) &&
1185  (KnownOne.countPopulation() == 1);
1186 }
1187 
1189  if (!N)
1190  return false;
1191 
1192  const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
1193  if (!CN) {
1195  if (!BV)
1196  return false;
1197 
1198  BitVector UndefElements;
1199  CN = BV->getConstantSplatNode(&UndefElements);
1200  // Only interested in constant splats, and we don't try to handle undef
1201  // elements in identifying boolean constants.
1202  if (!CN || UndefElements.none())
1203  return false;
1204  }
1205 
1206  switch (getBooleanContents(N->getValueType(0))) {
1208  return CN->getAPIntValue()[0];
1210  return CN->isOne();
1212  return CN->isAllOnesValue();
1213  }
1214 
1215  llvm_unreachable("Invalid boolean contents");
1216 }
1217 
1219  if (!N)
1220  return false;
1221 
1222  const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
1223  if (!CN) {
1225  if (!BV)
1226  return false;
1227 
1228  BitVector UndefElements;
1229  CN = BV->getConstantSplatNode(&UndefElements);
1230  // Only interested in constant splats, and we don't try to handle undef
1231  // elements in identifying boolean constants.
1232  if (!CN || UndefElements.none())
1233  return false;
1234  }
1235 
1237  return !CN->getAPIntValue()[0];
1238 
1239  return CN->isNullValue();
1240 }
1241 
1242 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
1243 /// and cc. If it is unable to simplify it, return a null SDValue.
1244 SDValue
1246  ISD::CondCode Cond, bool foldBooleans,
1247  DAGCombinerInfo &DCI, SDLoc dl) const {
1248  SelectionDAG &DAG = DCI.DAG;
1249 
1250  // These setcc operations always fold.
1251  switch (Cond) {
1252  default: break;
1253  case ISD::SETFALSE:
1254  case ISD::SETFALSE2: return DAG.getConstant(0, dl, VT);
1255  case ISD::SETTRUE:
1256  case ISD::SETTRUE2: {
1259  return DAG.getConstant(
1260  Cnt == TargetLowering::ZeroOrNegativeOneBooleanContent ? -1ULL : 1, dl,
1261  VT);
1262  }
1263  }
1264 
1265  // Ensure that the constant occurs on the RHS, and fold constant
1266  // comparisons.
1267  ISD::CondCode SwappedCC = ISD::getSetCCSwappedOperands(Cond);
1268  if (isa<ConstantSDNode>(N0.getNode()) &&
1269  (DCI.isBeforeLegalizeOps() ||
1270  isCondCodeLegal(SwappedCC, N0.getSimpleValueType())))
1271  return DAG.getSetCC(dl, VT, N1, N0, SwappedCC);
1272 
1273  if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1274  const APInt &C1 = N1C->getAPIntValue();
1275 
1276  // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1277  // equality comparison, then we're just comparing whether X itself is
1278  // zero.
1279  if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1280  N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1281  N0.getOperand(1).getOpcode() == ISD::Constant) {
1282  const APInt &ShAmt
1283  = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1284  if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1285  ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1286  if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1287  // (srl (ctlz x), 5) == 0 -> X != 0
1288  // (srl (ctlz x), 5) != 1 -> X != 0
1289  Cond = ISD::SETNE;
1290  } else {
1291  // (srl (ctlz x), 5) != 0 -> X == 0
1292  // (srl (ctlz x), 5) == 1 -> X == 0
1293  Cond = ISD::SETEQ;
1294  }
1295  SDValue Zero = DAG.getConstant(0, dl, N0.getValueType());
1296  return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1297  Zero, Cond);
1298  }
1299  }
1300 
1301  SDValue CTPOP = N0;
1302  // Look through truncs that don't change the value of a ctpop.
1303  if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
1304  CTPOP = N0.getOperand(0);
1305 
1306  if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
1307  (N0 == CTPOP || N0.getValueType().getSizeInBits() >
1308  Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) {
1309  EVT CTVT = CTPOP.getValueType();
1310  SDValue CTOp = CTPOP.getOperand(0);
1311 
1312  // (ctpop x) u< 2 -> (x & x-1) == 0
1313  // (ctpop x) u> 1 -> (x & x-1) != 0
1314  if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
1315  SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
1316  DAG.getConstant(1, dl, CTVT));
1317  SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
1319  return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, dl, CTVT), CC);
1320  }
1321 
1322  // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal.
1323  }
1324 
1325  // (zext x) == C --> x == (trunc C)
1326  // (sext x) == C --> x == (trunc C)
1327  if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1328  DCI.isBeforeLegalize() && N0->hasOneUse()) {
1329  unsigned MinBits = N0.getValueSizeInBits();
1330  SDValue PreExt;
1331  bool Signed = false;
1332  if (N0->getOpcode() == ISD::ZERO_EXTEND) {
1333  // ZExt
1334  MinBits = N0->getOperand(0).getValueSizeInBits();
1335  PreExt = N0->getOperand(0);
1336  } else if (N0->getOpcode() == ISD::AND) {
1337  // DAGCombine turns costly ZExts into ANDs
1338  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
1339  if ((C->getAPIntValue()+1).isPowerOf2()) {
1340  MinBits = C->getAPIntValue().countTrailingOnes();
1341  PreExt = N0->getOperand(0);
1342  }
1343  } else if (N0->getOpcode() == ISD::SIGN_EXTEND) {
1344  // SExt
1345  MinBits = N0->getOperand(0).getValueSizeInBits();
1346  PreExt = N0->getOperand(0);
1347  Signed = true;
1348  } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) {
1349  // ZEXTLOAD / SEXTLOAD
1350  if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
1351  MinBits = LN0->getMemoryVT().getSizeInBits();
1352  PreExt = N0;
1353  } else if (LN0->getExtensionType() == ISD::SEXTLOAD) {
1354  Signed = true;
1355  MinBits = LN0->getMemoryVT().getSizeInBits();
1356  PreExt = N0;
1357  }
1358  }
1359 
1360  // Figure out how many bits we need to preserve this constant.
1361  unsigned ReqdBits = Signed ?
1362  C1.getBitWidth() - C1.getNumSignBits() + 1 :
1363  C1.getActiveBits();
1364 
1365  // Make sure we're not losing bits from the constant.
1366  if (MinBits > 0 &&
1367  MinBits < C1.getBitWidth() &&
1368  MinBits >= ReqdBits) {
1369  EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
1370  if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
1371  // Will get folded away.
1372  SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreExt);
1373  SDValue C = DAG.getConstant(C1.trunc(MinBits), dl, MinVT);
1374  return DAG.getSetCC(dl, VT, Trunc, C, Cond);
1375  }
1376  }
1377  }
1378 
1379  // If the LHS is '(and load, const)', the RHS is 0,
1380  // the test is for equality or unsigned, and all 1 bits of the const are
1381  // in the same partial word, see if we can shorten the load.
1382  if (DCI.isBeforeLegalize() &&
1383  !ISD::isSignedIntSetCC(Cond) &&
1384  N0.getOpcode() == ISD::AND && C1 == 0 &&
1385  N0.getNode()->hasOneUse() &&
1386  isa<LoadSDNode>(N0.getOperand(0)) &&
1387  N0.getOperand(0).getNode()->hasOneUse() &&
1388  isa<ConstantSDNode>(N0.getOperand(1))) {
1389  LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
1390  APInt bestMask;
1391  unsigned bestWidth = 0, bestOffset = 0;
1392  if (!Lod->isVolatile() && Lod->isUnindexed()) {
1393  unsigned origWidth = N0.getValueType().getSizeInBits();
1394  unsigned maskWidth = origWidth;
1395  // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
1396  // 8 bits, but have to be careful...
1397  if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
1398  origWidth = Lod->getMemoryVT().getSizeInBits();
1399  const APInt &Mask =
1400  cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1401  for (unsigned width = origWidth / 2; width>=8; width /= 2) {
1402  APInt newMask = APInt::getLowBitsSet(maskWidth, width);
1403  for (unsigned offset=0; offset<origWidth/width; offset++) {
1404  if ((newMask & Mask) == Mask) {
1405  if (!DAG.getDataLayout().isLittleEndian())
1406  bestOffset = (origWidth/width - offset - 1) * (width/8);
1407  else
1408  bestOffset = (uint64_t)offset * (width/8);
1409  bestMask = Mask.lshr(offset * (width/8) * 8);
1410  bestWidth = width;
1411  break;
1412  }
1413  newMask = newMask << width;
1414  }
1415  }
1416  }
1417  if (bestWidth) {
1418  EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth);
1419  if (newVT.isRound()) {
1420  EVT PtrType = Lod->getOperand(1).getValueType();
1421  SDValue Ptr = Lod->getBasePtr();
1422  if (bestOffset != 0)
1423  Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
1424  DAG.getConstant(bestOffset, dl, PtrType));
1425  unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
1426  SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
1427  Lod->getPointerInfo().getWithOffset(bestOffset),
1428  false, false, false, NewAlign);
1429  return DAG.getSetCC(dl, VT,
1430  DAG.getNode(ISD::AND, dl, newVT, NewLoad,
1431  DAG.getConstant(bestMask.trunc(bestWidth),
1432  dl, newVT)),
1433  DAG.getConstant(0LL, dl, newVT), Cond);
1434  }
1435  }
1436  }
1437 
1438  // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1439  if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1440  unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
1441 
1442  // If the comparison constant has bits in the upper part, the
1443  // zero-extended value could never match.
1444  if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
1445  C1.getBitWidth() - InSize))) {
1446  switch (Cond) {
1447  case ISD::SETUGT:
1448  case ISD::SETUGE:
1449  case ISD::SETEQ: return DAG.getConstant(0, dl, VT);
1450  case ISD::SETULT:
1451  case ISD::SETULE:
1452  case ISD::SETNE: return DAG.getConstant(1, dl, VT);
1453  case ISD::SETGT:
1454  case ISD::SETGE:
1455  // True if the sign bit of C1 is set.
1456  return DAG.getConstant(C1.isNegative(), dl, VT);
1457  case ISD::SETLT:
1458  case ISD::SETLE:
1459  // True if the sign bit of C1 isn't set.
1460  return DAG.getConstant(C1.isNonNegative(), dl, VT);
1461  default:
1462  break;
1463  }
1464  }
1465 
1466  // Otherwise, we can perform the comparison with the low bits.
1467  switch (Cond) {
1468  case ISD::SETEQ:
1469  case ISD::SETNE:
1470  case ISD::SETUGT:
1471  case ISD::SETUGE:
1472  case ISD::SETULT:
1473  case ISD::SETULE: {
1474  EVT newVT = N0.getOperand(0).getValueType();
1475  if (DCI.isBeforeLegalizeOps() ||
1476  (isOperationLegal(ISD::SETCC, newVT) &&
1477  getCondCodeAction(Cond, newVT.getSimpleVT()) == Legal)) {
1478  EVT NewSetCCVT =
1479  getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), newVT);
1480  SDValue NewConst = DAG.getConstant(C1.trunc(InSize), dl, newVT);
1481 
1482  SDValue NewSetCC = DAG.getSetCC(dl, NewSetCCVT, N0.getOperand(0),
1483  NewConst, Cond);
1484  return DAG.getBoolExtOrTrunc(NewSetCC, dl, VT, N0.getValueType());
1485  }
1486  break;
1487  }
1488  default:
1489  break; // todo, be more careful with signed comparisons
1490  }
1491  } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1492  (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1493  EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
1494  unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
1495  EVT ExtDstTy = N0.getValueType();
1496  unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
1497 
1498  // If the constant doesn't fit into the number of bits for the source of
1499  // the sign extension, it is impossible for both sides to be equal.
1500  if (C1.getMinSignedBits() > ExtSrcTyBits)
1501  return DAG.getConstant(Cond == ISD::SETNE, dl, VT);
1502 
1503  SDValue ZextOp;
1504  EVT Op0Ty = N0.getOperand(0).getValueType();
1505  if (Op0Ty == ExtSrcTy) {
1506  ZextOp = N0.getOperand(0);
1507  } else {
1508  APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
1509  ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
1510  DAG.getConstant(Imm, dl, Op0Ty));
1511  }
1512  if (!DCI.isCalledByLegalizer())
1513  DCI.AddToWorklist(ZextOp.getNode());
1514  // Otherwise, make this a use of a zext.
1515  return DAG.getSetCC(dl, VT, ZextOp,
1517  ExtDstTyBits,
1518  ExtSrcTyBits),
1519  dl, ExtDstTy),
1520  Cond);
1521  } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
1522  (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1523  // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
1524  if (N0.getOpcode() == ISD::SETCC &&
1525  isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
1526  bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
1527  if (TrueWhenTrue)
1528  return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
1529  // Invert the condition.
1530  ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
1531  CC = ISD::getSetCCInverse(CC,
1532  N0.getOperand(0).getValueType().isInteger());
1533  if (DCI.isBeforeLegalizeOps() ||
1534  isCondCodeLegal(CC, N0.getOperand(0).getSimpleValueType()))
1535  return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
1536  }
1537 
1538  if ((N0.getOpcode() == ISD::XOR ||
1539  (N0.getOpcode() == ISD::AND &&
1540  N0.getOperand(0).getOpcode() == ISD::XOR &&
1541  N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
1542  isa<ConstantSDNode>(N0.getOperand(1)) &&
1543  cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
1544  // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
1545  // can only do this if the top bits are known zero.
1546  unsigned BitWidth = N0.getValueSizeInBits();
1547  if (DAG.MaskedValueIsZero(N0,
1548  APInt::getHighBitsSet(BitWidth,
1549  BitWidth-1))) {
1550  // Okay, get the un-inverted input value.
1551  SDValue Val;
1552  if (N0.getOpcode() == ISD::XOR)
1553  Val = N0.getOperand(0);
1554  else {
1555  assert(N0.getOpcode() == ISD::AND &&
1556  N0.getOperand(0).getOpcode() == ISD::XOR);
1557  // ((X^1)&1)^1 -> X & 1
1558  Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
1559  N0.getOperand(0).getOperand(0),
1560  N0.getOperand(1));
1561  }
1562 
1563  return DAG.getSetCC(dl, VT, Val, N1,
1564  Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1565  }
1566  } else if (N1C->getAPIntValue() == 1 &&
1567  (VT == MVT::i1 ||
1568  getBooleanContents(N0->getValueType(0)) ==
1570  SDValue Op0 = N0;
1571  if (Op0.getOpcode() == ISD::TRUNCATE)
1572  Op0 = Op0.getOperand(0);
1573 
1574  if ((Op0.getOpcode() == ISD::XOR) &&
1575  Op0.getOperand(0).getOpcode() == ISD::SETCC &&
1576  Op0.getOperand(1).getOpcode() == ISD::SETCC) {
1577  // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
1578  Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
1579  return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
1580  Cond);
1581  }
1582  if (Op0.getOpcode() == ISD::AND &&
1583  isa<ConstantSDNode>(Op0.getOperand(1)) &&
1584  cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
1585  // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
1586  if (Op0.getValueType().bitsGT(VT))
1587  Op0 = DAG.getNode(ISD::AND, dl, VT,
1588  DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
1589  DAG.getConstant(1, dl, VT));
1590  else if (Op0.getValueType().bitsLT(VT))
1591  Op0 = DAG.getNode(ISD::AND, dl, VT,
1592  DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
1593  DAG.getConstant(1, dl, VT));
1594 
1595  return DAG.getSetCC(dl, VT, Op0,
1596  DAG.getConstant(0, dl, Op0.getValueType()),
1597  Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1598  }
1599  if (Op0.getOpcode() == ISD::AssertZext &&
1600  cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1)
1601  return DAG.getSetCC(dl, VT, Op0,
1602  DAG.getConstant(0, dl, Op0.getValueType()),
1603  Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1604  }
1605  }
1606 
1607  APInt MinVal, MaxVal;
1608  unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
1609  if (ISD::isSignedIntSetCC(Cond)) {
1610  MinVal = APInt::getSignedMinValue(OperandBitSize);
1611  MaxVal = APInt::getSignedMaxValue(OperandBitSize);
1612  } else {
1613  MinVal = APInt::getMinValue(OperandBitSize);
1614  MaxVal = APInt::getMaxValue(OperandBitSize);
1615  }
1616 
1617  // Canonicalize GE/LE comparisons to use GT/LT comparisons.
1618  if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1619  if (C1 == MinVal) return DAG.getConstant(1, dl, VT); // X >= MIN --> true
1620  // X >= C0 --> X > (C0 - 1)
1621  APInt C = C1 - 1;
1622  ISD::CondCode NewCC = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT;
1623  if ((DCI.isBeforeLegalizeOps() ||
1624  isCondCodeLegal(NewCC, VT.getSimpleVT())) &&
1625  (!N1C->isOpaque() || (N1C->isOpaque() && C.getBitWidth() <= 64 &&
1627  return DAG.getSetCC(dl, VT, N0,
1628  DAG.getConstant(C, dl, N1.getValueType()),
1629  NewCC);
1630  }
1631  }
1632 
1633  if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1634  if (C1 == MaxVal) return DAG.getConstant(1, dl, VT); // X <= MAX --> true
1635  // X <= C0 --> X < (C0 + 1)
1636  APInt C = C1 + 1;
1637  ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT;
1638  if ((DCI.isBeforeLegalizeOps() ||
1639  isCondCodeLegal(NewCC, VT.getSimpleVT())) &&
1640  (!N1C->isOpaque() || (N1C->isOpaque() && C.getBitWidth() <= 64 &&
1642  return DAG.getSetCC(dl, VT, N0,
1643  DAG.getConstant(C, dl, N1.getValueType()),
1644  NewCC);
1645  }
1646  }
1647 
1648  if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1649  return DAG.getConstant(0, dl, VT); // X < MIN --> false
1650  if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
1651  return DAG.getConstant(1, dl, VT); // X >= MIN --> true
1652  if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
1653  return DAG.getConstant(0, dl, VT); // X > MAX --> false
1654  if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
1655  return DAG.getConstant(1, dl, VT); // X <= MAX --> true
1656 
1657  // Canonicalize setgt X, Min --> setne X, Min
1658  if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1659  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1660  // Canonicalize setlt X, Max --> setne X, Max
1661  if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
1662  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1663 
1664  // If we have setult X, 1, turn it into seteq X, 0
1665  if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1666  return DAG.getSetCC(dl, VT, N0,
1667  DAG.getConstant(MinVal, dl, N0.getValueType()),
1668  ISD::SETEQ);
1669  // If we have setugt X, Max-1, turn it into seteq X, Max
1670  if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1671  return DAG.getSetCC(dl, VT, N0,
1672  DAG.getConstant(MaxVal, dl, N0.getValueType()),
1673  ISD::SETEQ);
1674 
1675  // If we have "setcc X, C0", check to see if we can shrink the immediate
1676  // by changing cc.
1677 
1678  // SETUGT X, SINTMAX -> SETLT X, 0
1679  if (Cond == ISD::SETUGT &&
1680  C1 == APInt::getSignedMaxValue(OperandBitSize))
1681  return DAG.getSetCC(dl, VT, N0,
1682  DAG.getConstant(0, dl, N1.getValueType()),
1683  ISD::SETLT);
1684 
1685  // SETULT X, SINTMIN -> SETGT X, -1
1686  if (Cond == ISD::SETULT &&
1687  C1 == APInt::getSignedMinValue(OperandBitSize)) {
1688  SDValue ConstMinusOne =
1689  DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), dl,
1690  N1.getValueType());
1691  return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
1692  }
1693 
1694  // Fold bit comparisons when we can.
1695  if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1696  (VT == N0.getValueType() ||
1697  (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
1698  N0.getOpcode() == ISD::AND) {
1699  auto &DL = DAG.getDataLayout();
1700  if (ConstantSDNode *AndRHS =
1701  dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1702  EVT ShiftTy = DCI.isBeforeLegalize()
1703  ? getPointerTy(DL)
1704  : getShiftAmountTy(N0.getValueType(), DL);
1705  if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
1706  // Perform the xform if the AND RHS is a single bit.
1707  if (AndRHS->getAPIntValue().isPowerOf2()) {
1708  return DAG.getNode(ISD::TRUNCATE, dl, VT,
1709  DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1710  DAG.getConstant(AndRHS->getAPIntValue().logBase2(), dl,
1711  ShiftTy)));
1712  }
1713  } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
1714  // (X & 8) == 8 --> (X & 8) >> 3
1715  // Perform the xform if C1 is a single bit.
1716  if (C1.isPowerOf2()) {
1717  return DAG.getNode(ISD::TRUNCATE, dl, VT,
1718  DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1719  DAG.getConstant(C1.logBase2(), dl,
1720  ShiftTy)));
1721  }
1722  }
1723  }
1724  }
1725 
1726  if (C1.getMinSignedBits() <= 64 &&
1727  !isLegalICmpImmediate(C1.getSExtValue())) {
1728  // (X & -256) == 256 -> (X >> 8) == 1
1729  if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1730  N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
1731  if (ConstantSDNode *AndRHS =
1732  dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1733  const APInt &AndRHSC = AndRHS->getAPIntValue();
1734  if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) {
1735  unsigned ShiftBits = AndRHSC.countTrailingZeros();
1736  auto &DL = DAG.getDataLayout();
1737  EVT ShiftTy = DCI.isBeforeLegalize()
1738  ? getPointerTy(DL)
1739  : getShiftAmountTy(N0.getValueType(), DL);
1740  EVT CmpTy = N0.getValueType();
1741  SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0),
1742  DAG.getConstant(ShiftBits, dl,
1743  ShiftTy));
1744  SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), dl, CmpTy);
1745  return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond);
1746  }
1747  }
1748  } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE ||
1749  Cond == ISD::SETULE || Cond == ISD::SETUGT) {
1750  bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT);
1751  // X < 0x100000000 -> (X >> 32) < 1
1752  // X >= 0x100000000 -> (X >> 32) >= 1
1753  // X <= 0x0ffffffff -> (X >> 32) < 1
1754  // X > 0x0ffffffff -> (X >> 32) >= 1
1755  unsigned ShiftBits;
1756  APInt NewC = C1;
1757  ISD::CondCode NewCond = Cond;
1758  if (AdjOne) {
1759  ShiftBits = C1.countTrailingOnes();
1760  NewC = NewC + 1;
1761  NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1762  } else {
1763  ShiftBits = C1.countTrailingZeros();
1764  }
1765  NewC = NewC.lshr(ShiftBits);
1766  if (ShiftBits && NewC.getMinSignedBits() <= 64 &&
1768  auto &DL = DAG.getDataLayout();
1769  EVT ShiftTy = DCI.isBeforeLegalize()
1770  ? getPointerTy(DL)
1771  : getShiftAmountTy(N0.getValueType(), DL);
1772  EVT CmpTy = N0.getValueType();
1773  SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0,
1774  DAG.getConstant(ShiftBits, dl, ShiftTy));
1775  SDValue CmpRHS = DAG.getConstant(NewC, dl, CmpTy);
1776  return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond);
1777  }
1778  }
1779  }
1780  }
1781 
1782  if (isa<ConstantFPSDNode>(N0.getNode())) {
1783  // Constant fold or commute setcc.
1784  SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
1785  if (O.getNode()) return O;
1786  } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
1787  // If the RHS of an FP comparison is a constant, simplify it away in
1788  // some cases.
1789  if (CFP->getValueAPF().isNaN()) {
1790  // If an operand is known to be a nan, we can fold it.
1791  switch (ISD::getUnorderedFlavor(Cond)) {
1792  default: llvm_unreachable("Unknown flavor!");
1793  case 0: // Known false.
1794  return DAG.getConstant(0, dl, VT);
1795  case 1: // Known true.
1796  return DAG.getConstant(1, dl, VT);
1797  case 2: // Undefined.
1798  return DAG.getUNDEF(VT);
1799  }
1800  }
1801 
1802  // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
1803  // constant if knowing that the operand is non-nan is enough. We prefer to
1804  // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
1805  // materialize 0.0.
1806  if (Cond == ISD::SETO || Cond == ISD::SETUO)
1807  return DAG.getSetCC(dl, VT, N0, N0, Cond);
1808 
1809  // If the condition is not legal, see if we can find an equivalent one
1810  // which is legal.
1811  if (!isCondCodeLegal(Cond, N0.getSimpleValueType())) {
1812  // If the comparison was an awkward floating-point == or != and one of
1813  // the comparison operands is infinity or negative infinity, convert the
1814  // condition to a less-awkward <= or >=.
1815  if (CFP->getValueAPF().isInfinity()) {
1816  if (CFP->getValueAPF().isNegative()) {
1817  if (Cond == ISD::SETOEQ &&
1819  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
1820  if (Cond == ISD::SETUEQ &&
1822  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
1823  if (Cond == ISD::SETUNE &&
1825  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
1826  if (Cond == ISD::SETONE &&
1828  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
1829  } else {
1830  if (Cond == ISD::SETOEQ &&
1832  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
1833  if (Cond == ISD::SETUEQ &&
1835  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
1836  if (Cond == ISD::SETUNE &&
1838  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
1839  if (Cond == ISD::SETONE &&
1841  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
1842  }
1843  }
1844  }
1845  }
1846 
1847  if (N0 == N1) {
1848  // The sext(setcc()) => setcc() optimization relies on the appropriate
1849  // constant being emitted.
1850  uint64_t EqVal = 0;
1851  switch (getBooleanContents(N0.getValueType())) {
1854  EqVal = ISD::isTrueWhenEqual(Cond);
1855  break;
1857  EqVal = ISD::isTrueWhenEqual(Cond) ? -1 : 0;
1858  break;
1859  }
1860 
1861  // We can always fold X == X for integer setcc's.
1862  if (N0.getValueType().isInteger()) {
1863  return DAG.getConstant(EqVal, dl, VT);
1864  }
1865  unsigned UOF = ISD::getUnorderedFlavor(Cond);
1866  if (UOF == 2) // FP operators that are undefined on NaNs.
1867  return DAG.getConstant(EqVal, dl, VT);
1868  if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
1869  return DAG.getConstant(EqVal, dl, VT);
1870  // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
1871  // if it is not already.
1872  ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
1873  if (NewCond != Cond && (DCI.isBeforeLegalizeOps() ||
1874  getCondCodeAction(NewCond, N0.getSimpleValueType()) == Legal))
1875  return DAG.getSetCC(dl, VT, N0, N1, NewCond);
1876  }
1877 
1878  if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1879  N0.getValueType().isInteger()) {
1880  if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
1881  N0.getOpcode() == ISD::XOR) {
1882  // Simplify (X+Y) == (X+Z) --> Y == Z
1883  if (N0.getOpcode() == N1.getOpcode()) {
1884  if (N0.getOperand(0) == N1.getOperand(0))
1885  return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
1886  if (N0.getOperand(1) == N1.getOperand(1))
1887  return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
1888  if (DAG.isCommutativeBinOp(N0.getOpcode())) {
1889  // If X op Y == Y op X, try other combinations.
1890  if (N0.getOperand(0) == N1.getOperand(1))
1891  return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
1892  Cond);
1893  if (N0.getOperand(1) == N1.getOperand(0))
1894  return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
1895  Cond);
1896  }
1897  }
1898 
1899  // If RHS is a legal immediate value for a compare instruction, we need
1900  // to be careful about increasing register pressure needlessly.
1901  bool LegalRHSImm = false;
1902 
1903  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
1904  if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1905  // Turn (X+C1) == C2 --> X == C2-C1
1906  if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
1907  return DAG.getSetCC(dl, VT, N0.getOperand(0),
1908  DAG.getConstant(RHSC->getAPIntValue()-
1909  LHSR->getAPIntValue(),
1910  dl, N0.getValueType()), Cond);
1911  }
1912 
1913  // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
1914  if (N0.getOpcode() == ISD::XOR)
1915  // If we know that all of the inverted bits are zero, don't bother
1916  // performing the inversion.
1917  if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
1918  return
1919  DAG.getSetCC(dl, VT, N0.getOperand(0),
1920  DAG.getConstant(LHSR->getAPIntValue() ^
1921  RHSC->getAPIntValue(),
1922  dl, N0.getValueType()),
1923  Cond);
1924  }
1925 
1926  // Turn (C1-X) == C2 --> X == C1-C2
1927  if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
1928  if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
1929  return
1930  DAG.getSetCC(dl, VT, N0.getOperand(1),
1931  DAG.getConstant(SUBC->getAPIntValue() -
1932  RHSC->getAPIntValue(),
1933  dl, N0.getValueType()),
1934  Cond);
1935  }
1936  }
1937 
1938  // Could RHSC fold directly into a compare?
1939  if (RHSC->getValueType(0).getSizeInBits() <= 64)
1940  LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue());
1941  }
1942 
1943  // Simplify (X+Z) == X --> Z == 0
1944  // Don't do this if X is an immediate that can fold into a cmp
1945  // instruction and X+Z has other uses. It could be an induction variable
1946  // chain, and the transform would increase register pressure.
1947  if (!LegalRHSImm || N0.getNode()->hasOneUse()) {
1948  if (N0.getOperand(0) == N1)
1949  return DAG.getSetCC(dl, VT, N0.getOperand(1),
1950  DAG.getConstant(0, dl, N0.getValueType()), Cond);
1951  if (N0.getOperand(1) == N1) {
1952  if (DAG.isCommutativeBinOp(N0.getOpcode()))
1953  return DAG.getSetCC(dl, VT, N0.getOperand(0),
1954  DAG.getConstant(0, dl, N0.getValueType()),
1955  Cond);
1956  if (N0.getNode()->hasOneUse()) {
1957  assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
1958  auto &DL = DAG.getDataLayout();
1959  // (Z-X) == X --> Z == X<<1
1960  SDValue SH = DAG.getNode(
1961  ISD::SHL, dl, N1.getValueType(), N1,
1962  DAG.getConstant(1, dl,
1963  getShiftAmountTy(N1.getValueType(), DL)));
1964  if (!DCI.isCalledByLegalizer())
1965  DCI.AddToWorklist(SH.getNode());
1966  return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
1967  }
1968  }
1969  }
1970  }
1971 
1972  if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
1973  N1.getOpcode() == ISD::XOR) {
1974  // Simplify X == (X+Z) --> Z == 0
1975  if (N1.getOperand(0) == N0)
1976  return DAG.getSetCC(dl, VT, N1.getOperand(1),
1977  DAG.getConstant(0, dl, N1.getValueType()), Cond);
1978  if (N1.getOperand(1) == N0) {
1979  if (DAG.isCommutativeBinOp(N1.getOpcode()))
1980  return DAG.getSetCC(dl, VT, N1.getOperand(0),
1981  DAG.getConstant(0, dl, N1.getValueType()), Cond);
1982  if (N1.getNode()->hasOneUse()) {
1983  assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
1984  auto &DL = DAG.getDataLayout();
1985  // X == (Z-X) --> X<<1 == Z
1986  SDValue SH = DAG.getNode(
1987  ISD::SHL, dl, N1.getValueType(), N0,
1988  DAG.getConstant(1, dl, getShiftAmountTy(N0.getValueType(), DL)));
1989  if (!DCI.isCalledByLegalizer())
1990  DCI.AddToWorklist(SH.getNode());
1991  return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
1992  }
1993  }
1994  }
1995 
1996  // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
1997  // Note that where y is variable and is known to have at most
1998  // one bit set (for example, if it is z&1) we cannot do this;
1999  // the expressions are not equivalent when y==0.
2000  if (N0.getOpcode() == ISD::AND)
2001  if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
2002  if (ValueHasExactlyOneBitSet(N1, DAG)) {
2003  Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2004  if (DCI.isBeforeLegalizeOps() ||
2005  isCondCodeLegal(Cond, N0.getSimpleValueType())) {
2006  SDValue Zero = DAG.getConstant(0, dl, N1.getValueType());
2007  return DAG.getSetCC(dl, VT, N0, Zero, Cond);
2008  }
2009  }
2010  }
2011  if (N1.getOpcode() == ISD::AND)
2012  if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
2013  if (ValueHasExactlyOneBitSet(N0, DAG)) {
2014  Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2015  if (DCI.isBeforeLegalizeOps() ||
2016  isCondCodeLegal(Cond, N1.getSimpleValueType())) {
2017  SDValue Zero = DAG.getConstant(0, dl, N0.getValueType());
2018  return DAG.getSetCC(dl, VT, N1, Zero, Cond);
2019  }
2020  }
2021  }
2022  }
2023 
2024  // Fold away ALL boolean setcc's.
2025  SDValue Temp;
2026  if (N0.getValueType() == MVT::i1 && foldBooleans) {
2027  switch (Cond) {
2028  default: llvm_unreachable("Unknown integer setcc!");
2029  case ISD::SETEQ: // X == Y -> ~(X^Y)
2030  Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2031  N0 = DAG.getNOT(dl, Temp, MVT::i1);
2032  if (!DCI.isCalledByLegalizer())
2033  DCI.AddToWorklist(Temp.getNode());
2034  break;
2035  case ISD::SETNE: // X != Y --> (X^Y)
2036  N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2037  break;
2038  case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
2039  case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
2040  Temp = DAG.getNOT(dl, N0, MVT::i1);
2041  N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
2042  if (!DCI.isCalledByLegalizer())
2043  DCI.AddToWorklist(Temp.getNode());
2044  break;
2045  case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
2046  case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
2047  Temp = DAG.getNOT(dl, N1, MVT::i1);
2048  N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
2049  if (!DCI.isCalledByLegalizer())
2050  DCI.AddToWorklist(Temp.getNode());
2051  break;
2052  case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
2053  case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
2054  Temp = DAG.getNOT(dl, N0, MVT::i1);
2055  N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
2056  if (!DCI.isCalledByLegalizer())
2057  DCI.AddToWorklist(Temp.getNode());
2058  break;
2059  case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
2060  case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
2061  Temp = DAG.getNOT(dl, N1, MVT::i1);
2062  N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
2063  break;
2064  }
2065  if (VT != MVT::i1) {
2066  if (!DCI.isCalledByLegalizer())
2067  DCI.AddToWorklist(N0.getNode());
2068  // FIXME: If running after legalize, we probably can't do this.
2069  N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
2070  }
2071  return N0;
2072  }
2073 
2074  // Could not fold it.
2075  return SDValue();
2076 }
2077 
2078 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2079 /// node is a GlobalAddress + offset.
2081  int64_t &Offset) const {
2082  if (isa<GlobalAddressSDNode>(N)) {
2083  GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2084  GA = GASD->getGlobal();
2085  Offset += GASD->getOffset();
2086  return true;
2087  }
2088 
2089  if (N->getOpcode() == ISD::ADD) {
2090  SDValue N1 = N->getOperand(0);
2091  SDValue N2 = N->getOperand(1);
2092  if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
2094  if (V) {
2095  Offset += V->getSExtValue();
2096  return true;
2097  }
2098  } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
2100  if (V) {
2101  Offset += V->getSExtValue();
2102  return true;
2103  }
2104  }
2105  }
2106 
2107  return false;
2108 }
2109 
2110 
2113  // Default implementation: no optimization.
2114  return SDValue();
2115 }
2116 
2117 //===----------------------------------------------------------------------===//
2118 // Inline Assembler Implementation Methods
2119 //===----------------------------------------------------------------------===//
2120 
2123  unsigned S = Constraint.size();
2124 
2125  if (S == 1) {
2126  switch (Constraint[0]) {
2127  default: break;
2128  case 'r': return C_RegisterClass;
2129  case 'm': // memory
2130  case 'o': // offsetable
2131  case 'V': // not offsetable
2132  return C_Memory;
2133  case 'i': // Simple Integer or Relocatable Constant
2134  case 'n': // Simple Integer
2135  case 'E': // Floating Point Constant
2136  case 'F': // Floating Point Constant
2137  case 's': // Relocatable Constant
2138  case 'p': // Address.
2139  case 'X': // Allow ANY value.
2140  case 'I': // Target registers.
2141  case 'J':
2142  case 'K':
2143  case 'L':
2144  case 'M':
2145  case 'N':
2146  case 'O':
2147  case 'P':
2148  case '<':
2149  case '>':
2150  return C_Other;
2151  }
2152  }
2153 
2154  if (S > 1 && Constraint[0] == '{' && Constraint[S-1] == '}') {
2155  if (S == 8 && Constraint.substr(1, 6) == "memory") // "{memory}"
2156  return C_Memory;
2157  return C_Register;
2158  }
2159  return C_Unknown;
2160 }
2161 
2162 /// LowerXConstraint - try to replace an X constraint, which matches anything,
2163 /// with another that has more specific requirements based on the type of the
2164 /// corresponding operand.
2165 const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
2166  if (ConstraintVT.isInteger())
2167  return "r";
2168  if (ConstraintVT.isFloatingPoint())
2169  return "f"; // works for many targets
2170  return nullptr;
2171 }
2172 
2173 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2174 /// vector. If it is invalid, don't add anything to Ops.
2176  std::string &Constraint,
2177  std::vector<SDValue> &Ops,
2178  SelectionDAG &DAG) const {
2179 
2180  if (Constraint.length() > 1) return;
2181 
2182  char ConstraintLetter = Constraint[0];
2183  switch (ConstraintLetter) {
2184  default: break;
2185  case 'X': // Allows any operand; labels (basic block) use this.
2186  if (Op.getOpcode() == ISD::BasicBlock) {
2187  Ops.push_back(Op);
2188  return;
2189  }
2190  // fall through
2191  case 'i': // Simple Integer or Relocatable Constant
2192  case 'n': // Simple Integer
2193  case 's': { // Relocatable Constant
2194  // These operands are interested in values of the form (GV+C), where C may
2195  // be folded in as an offset of GV, or it may be explicitly added. Also, it
2196  // is possible and fine if either GV or C are missing.
2199 
2200  // If we have "(add GV, C)", pull out GV/C
2201  if (Op.getOpcode() == ISD::ADD) {
2202  C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2204  if (!C || !GA) {
2205  C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2207  }
2208  if (!C || !GA)
2209  C = nullptr, GA = nullptr;
2210  }
2211 
2212  // If we find a valid operand, map to the TargetXXX version so that the
2213  // value itself doesn't get selected.
2214  if (GA) { // Either &GV or &GV+C
2215  if (ConstraintLetter != 'n') {
2216  int64_t Offs = GA->getOffset();
2217  if (C) Offs += C->getZExtValue();
2218  Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
2219  C ? SDLoc(C) : SDLoc(),
2220  Op.getValueType(), Offs));
2221  }
2222  return;
2223  }
2224  if (C) { // just C, no GV.
2225  // Simple constants are not allowed for 's'.
2226  if (ConstraintLetter != 's') {
2227  // gcc prints these as sign extended. Sign extend value to 64 bits
2228  // now; without this it would get ZExt'd later in
2229  // ScheduleDAGSDNodes::EmitNode, which is very generic.
2230  Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
2231  SDLoc(C), MVT::i64));
2232  }
2233  return;
2234  }
2235  break;
2236  }
2237  }
2238 }
2239 
2240 std::pair<unsigned, const TargetRegisterClass *>
2242  StringRef Constraint,
2243  MVT VT) const {
2244  if (Constraint.empty() || Constraint[0] != '{')
2245  return std::make_pair(0u, static_cast<TargetRegisterClass*>(nullptr));
2246  assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2247 
2248  // Remove the braces from around the name.
2249  StringRef RegName(Constraint.data()+1, Constraint.size()-2);
2250 
2251  std::pair<unsigned, const TargetRegisterClass*> R =
2252  std::make_pair(0u, static_cast<const TargetRegisterClass*>(nullptr));
2253 
2254  // Figure out which register class contains this reg.
2256  E = RI->regclass_end(); RCI != E; ++RCI) {
2257  const TargetRegisterClass *RC = *RCI;
2258 
2259  // If none of the value types for this register class are valid, we
2260  // can't use it. For example, 64-bit reg classes on 32-bit targets.
2261  if (!isLegalRC(RC))
2262  continue;
2263 
2264  for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
2265  I != E; ++I) {
2266  if (RegName.equals_lower(RI->getName(*I))) {
2267  std::pair<unsigned, const TargetRegisterClass*> S =
2268  std::make_pair(*I, RC);
2269 
2270  // If this register class has the requested value type, return it,
2271  // otherwise keep searching and return the first class found
2272  // if no other is found which explicitly has the requested type.
2273  if (RC->hasType(VT))
2274  return S;
2275  else if (!R.second)
2276  R = S;
2277  }
2278  }
2279  }
2280 
2281  return R;
2282 }
2283 
2284 //===----------------------------------------------------------------------===//
2285 // Constraint Selection.
2286 
2287 /// isMatchingInputConstraint - Return true of this is an input operand that is
2288 /// a matching constraint like "4".
2290  assert(!ConstraintCode.empty() && "No known constraint!");
2291  return isdigit(static_cast<unsigned char>(ConstraintCode[0]));
2292 }
2293 
2294 /// getMatchedOperand - If this is an input matching constraint, this method
2295 /// returns the output operand it matches.
2297  assert(!ConstraintCode.empty() && "No known constraint!");
2298  return atoi(ConstraintCode.c_str());
2299 }
2300 
2301 
2302 /// ParseConstraints - Split up the constraint string from the inline
2303 /// assembly value into the specific constraints and their prefixes,
2304 /// and also tie in the associated operand values.
2305 /// If this returns an empty vector, and if the constraint string itself
2306 /// isn't empty, there was an error parsing.
2309  const TargetRegisterInfo *TRI,
2310  ImmutableCallSite CS) const {
2311  /// ConstraintOperands - Information about all of the constraints.
2312  AsmOperandInfoVector ConstraintOperands;
2313  const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
2314  unsigned maCount = 0; // Largest number of multiple alternative constraints.
2315 
2316  // Do a prepass over the constraints, canonicalizing them, and building up the
2317  // ConstraintOperands list.
2318  unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
2319  unsigned ResNo = 0; // ResNo - The result number of the next output.
2320 
2321  for (InlineAsm::ConstraintInfo &CI : IA->ParseConstraints()) {
2322  ConstraintOperands.emplace_back(std::move(CI));
2323  AsmOperandInfo &OpInfo = ConstraintOperands.back();
2324 
2325  // Update multiple alternative constraint count.
2326  if (OpInfo.multipleAlternatives.size() > maCount)
2327  maCount = OpInfo.multipleAlternatives.size();
2328 
2329  OpInfo.ConstraintVT = MVT::Other;
2330 
2331  // Compute the value type for each operand.
2332  switch (OpInfo.Type) {
2333  case InlineAsm::isOutput:
2334  // Indirect outputs just consume an argument.
2335  if (OpInfo.isIndirect) {
2336  OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2337  break;
2338  }
2339 
2340  // The return value of the call is this value. As such, there is no
2341  // corresponding argument.
2342  assert(!CS.getType()->isVoidTy() &&
2343  "Bad inline asm!");
2344  if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
2345  OpInfo.ConstraintVT =
2346  getSimpleValueType(DL, STy->getElementType(ResNo));
2347  } else {
2348  assert(ResNo == 0 && "Asm only has one result!");
2349  OpInfo.ConstraintVT = getSimpleValueType(DL, CS.getType());
2350  }
2351  ++ResNo;
2352  break;
2353  case InlineAsm::isInput:
2354  OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2355  break;
2356  case InlineAsm::isClobber:
2357  // Nothing to do.
2358  break;
2359  }
2360 
2361  if (OpInfo.CallOperandVal) {
2362  llvm::Type *OpTy = OpInfo.CallOperandVal->getType();
2363  if (OpInfo.isIndirect) {
2364  llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
2365  if (!PtrTy)
2366  report_fatal_error("Indirect operand for inline asm not a pointer!");
2367  OpTy = PtrTy->getElementType();
2368  }
2369 
2370  // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
2371  if (StructType *STy = dyn_cast<StructType>(OpTy))
2372  if (STy->getNumElements() == 1)
2373  OpTy = STy->getElementType(0);
2374 
2375  // If OpTy is not a single value, it may be a struct/union that we
2376  // can tile with integers.
2377  if (!OpTy->isSingleValueType() && OpTy->isSized()) {
2378  unsigned BitSize = DL.getTypeSizeInBits(OpTy);
2379  switch (BitSize) {
2380  default: break;
2381  case 1:
2382  case 8:
2383  case 16:
2384  case 32:
2385  case 64:
2386  case 128:
2387  OpInfo.ConstraintVT =
2388  MVT::getVT(IntegerType::get(OpTy->getContext(), BitSize), true);
2389  break;
2390  }
2391  } else if (PointerType *PT = dyn_cast<PointerType>(OpTy)) {
2392  unsigned PtrSize = DL.getPointerSizeInBits(PT->getAddressSpace());
2393  OpInfo.ConstraintVT = MVT::getIntegerVT(PtrSize);
2394  } else {
2395  OpInfo.ConstraintVT = MVT::getVT(OpTy, true);
2396  }
2397  }
2398  }
2399 
2400  // If we have multiple alternative constraints, select the best alternative.
2401  if (!ConstraintOperands.empty()) {
2402  if (maCount) {
2403  unsigned bestMAIndex = 0;
2404  int bestWeight = -1;
2405  // weight: -1 = invalid match, and 0 = so-so match to 5 = good match.
2406  int weight = -1;
2407  unsigned maIndex;
2408  // Compute the sums of the weights for each alternative, keeping track
2409  // of the best (highest weight) one so far.
2410  for (maIndex = 0; maIndex < maCount; ++maIndex) {
2411  int weightSum = 0;
2412  for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2413  cIndex != eIndex; ++cIndex) {
2414  AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2415  if (OpInfo.Type == InlineAsm::isClobber)
2416  continue;
2417 
2418  // If this is an output operand with a matching input operand,
2419  // look up the matching input. If their types mismatch, e.g. one
2420  // is an integer, the other is floating point, or their sizes are
2421  // different, flag it as an maCantMatch.
2422  if (OpInfo.hasMatchingInput()) {
2423  AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2424  if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2425  if ((OpInfo.ConstraintVT.isInteger() !=
2426  Input.ConstraintVT.isInteger()) ||
2427  (OpInfo.ConstraintVT.getSizeInBits() !=
2428  Input.ConstraintVT.getSizeInBits())) {
2429  weightSum = -1; // Can't match.
2430  break;
2431  }
2432  }
2433  }
2434  weight = getMultipleConstraintMatchWeight(OpInfo, maIndex);
2435  if (weight == -1) {
2436  weightSum = -1;
2437  break;
2438  }
2439  weightSum += weight;
2440  }
2441  // Update best.
2442  if (weightSum > bestWeight) {
2443  bestWeight = weightSum;
2444  bestMAIndex = maIndex;
2445  }
2446  }
2447 
2448  // Now select chosen alternative in each constraint.
2449  for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2450  cIndex != eIndex; ++cIndex) {
2451  AsmOperandInfo& cInfo = ConstraintOperands[cIndex];
2452  if (cInfo.Type == InlineAsm::isClobber)
2453  continue;
2454  cInfo.selectAlternative(bestMAIndex);
2455  }
2456  }
2457  }
2458 
2459  // Check and hook up tied operands, choose constraint code to use.
2460  for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2461  cIndex != eIndex; ++cIndex) {
2462  AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2463 
2464  // If this is an output operand with a matching input operand, look up the
2465  // matching input. If their types mismatch, e.g. one is an integer, the
2466  // other is floating point, or their sizes are different, flag it as an
2467  // error.
2468  if (OpInfo.hasMatchingInput()) {
2469  AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2470 
2471  if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2472  std::pair<unsigned, const TargetRegisterClass *> MatchRC =
2474  OpInfo.ConstraintVT);
2475  std::pair<unsigned, const TargetRegisterClass *> InputRC =
2477  Input.ConstraintVT);
2478  if ((OpInfo.ConstraintVT.isInteger() !=
2479  Input.ConstraintVT.isInteger()) ||
2480  (MatchRC.second != InputRC.second)) {
2481  report_fatal_error("Unsupported asm: input constraint"
2482  " with a matching output constraint of"
2483  " incompatible type!");
2484  }
2485  }
2486 
2487  }
2488  }
2489 
2490  return ConstraintOperands;
2491 }
2492 
2493 
2494 /// getConstraintGenerality - Return an integer indicating how general CT
2495 /// is.
2497  switch (CT) {
2500  return 0;
2502  return 1;
2504  return 2;
2506  return 3;
2507  }
2508  llvm_unreachable("Invalid constraint type");
2509 }
2510 
2511 /// Examine constraint type and operand type and determine a weight value.
2512 /// This object must already have been set up with the operand type
2513 /// and the current alternative constraint selected.
2516  AsmOperandInfo &info, int maIndex) const {
2518  if (maIndex >= (int)info.multipleAlternatives.size())
2519  rCodes = &info.Codes;
2520  else
2521  rCodes = &info.multipleAlternatives[maIndex].Codes;
2522  ConstraintWeight BestWeight = CW_Invalid;
2523 
2524  // Loop over the options, keeping track of the most general one.
2525  for (unsigned i = 0, e = rCodes->size(); i != e; ++i) {
2526  ConstraintWeight weight =
2527  getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
2528  if (weight > BestWeight)
2529  BestWeight = weight;
2530  }
2531 
2532  return BestWeight;
2533 }
2534 
2535 /// Examine constraint type and operand type and determine a weight value.
2536 /// This object must already have been set up with the operand type
2537 /// and the current alternative constraint selected.
2540  AsmOperandInfo &info, const char *constraint) const {
2541  ConstraintWeight weight = CW_Invalid;
2542  Value *CallOperandVal = info.CallOperandVal;
2543  // If we don't have a value, we can't do a match,
2544  // but allow it at the lowest weight.
2545  if (!CallOperandVal)
2546  return CW_Default;
2547  // Look at the constraint type.
2548  switch (*constraint) {
2549  case 'i': // immediate integer.
2550  case 'n': // immediate integer with a known value.
2551  if (isa<ConstantInt>(CallOperandVal))
2552  weight = CW_Constant;
2553  break;
2554  case 's': // non-explicit intregal immediate.
2555  if (isa<GlobalValue>(CallOperandVal))
2556  weight = CW_Constant;
2557  break;
2558  case 'E': // immediate float if host format.
2559  case 'F': // immediate float.
2560  if (isa<ConstantFP>(CallOperandVal))
2561  weight = CW_Constant;
2562  break;
2563  case '<': // memory operand with autodecrement.
2564  case '>': // memory operand with autoincrement.
2565  case 'm': // memory operand.
2566  case 'o': // offsettable memory operand
2567  case 'V': // non-offsettable memory operand
2568  weight = CW_Memory;
2569  break;
2570  case 'r': // general register.
2571  case 'g': // general register, memory operand or immediate integer.
2572  // note: Clang converts "g" to "imr".
2573  if (CallOperandVal->getType()->isIntegerTy())
2574  weight = CW_Register;
2575  break;
2576  case 'X': // any operand.
2577  default:
2578  weight = CW_Default;
2579  break;
2580  }
2581  return weight;
2582 }
2583 
2584 /// ChooseConstraint - If there are multiple different constraints that we
2585 /// could pick for this operand (e.g. "imr") try to pick the 'best' one.
2586 /// This is somewhat tricky: constraints fall into four classes:
2587 /// Other -> immediates and magic values
2588 /// Register -> one specific register
2589 /// RegisterClass -> a group of regs
2590 /// Memory -> memory
2591 /// Ideally, we would pick the most specific constraint possible: if we have
2592 /// something that fits into a register, we would pick it. The problem here
2593 /// is that if we have something that could either be in a register or in
2594 /// memory that use of the register could cause selection of *other*
2595 /// operands to fail: they might only succeed if we pick memory. Because of
2596 /// this the heuristic we use is:
2597 ///
2598 /// 1) If there is an 'other' constraint, and if the operand is valid for
2599 /// that constraint, use it. This makes us take advantage of 'i'
2600 /// constraints when available.
2601 /// 2) Otherwise, pick the most general constraint present. This prefers
2602 /// 'm' over 'r', for example.
2603 ///
2605  const TargetLowering &TLI,
2606  SDValue Op, SelectionDAG *DAG) {
2607  assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
2608  unsigned BestIdx = 0;
2610  int BestGenerality = -1;
2611 
2612  // Loop over the options, keeping track of the most general one.
2613  for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
2615  TLI.getConstraintType(OpInfo.Codes[i]);
2616 
2617  // If this is an 'other' constraint, see if the operand is valid for it.
2618  // For example, on X86 we might have an 'rI' constraint. If the operand
2619  // is an integer in the range [0..31] we want to use I (saving a load
2620  // of a register), otherwise we must use 'r'.
2621  if (CType == TargetLowering::C_Other && Op.getNode()) {
2622  assert(OpInfo.Codes[i].size() == 1 &&
2623  "Unhandled multi-letter 'other' constraint");
2624  std::vector<SDValue> ResultOps;
2625  TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i],
2626  ResultOps, *DAG);
2627  if (!ResultOps.empty()) {
2628  BestType = CType;
2629  BestIdx = i;
2630  break;
2631  }
2632  }
2633 
2634  // Things with matching constraints can only be registers, per gcc
2635  // documentation. This mainly affects "g" constraints.
2636  if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
2637  continue;
2638 
2639  // This constraint letter is more general than the previous one, use it.
2640  int Generality = getConstraintGenerality(CType);
2641  if (Generality > BestGenerality) {
2642  BestType = CType;
2643  BestIdx = i;
2644  BestGenerality = Generality;
2645  }
2646  }
2647 
2648  OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
2649  OpInfo.ConstraintType = BestType;
2650 }
2651 
2652 /// ComputeConstraintToUse - Determines the constraint code and constraint
2653 /// type to use for the specific AsmOperandInfo, setting
2654 /// OpInfo.ConstraintCode and OpInfo.ConstraintType.
2656  SDValue Op,
2657  SelectionDAG *DAG) const {
2658  assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
2659 
2660  // Single-letter constraints ('r') are very common.
2661  if (OpInfo.Codes.size() == 1) {
2662  OpInfo.ConstraintCode = OpInfo.Codes[0];
2664  } else {
2665  ChooseConstraint(OpInfo, *this, Op, DAG);
2666  }
2667 
2668  // 'X' matches anything.
2669  if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
2670  // Labels and constants are handled elsewhere ('X' is the only thing
2671  // that matches labels). For Functions, the type here is the type of
2672  // the result, which is not what we want to look at; leave them alone.
2673  Value *v = OpInfo.CallOperandVal;
2674  if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
2675  OpInfo.CallOperandVal = v;
2676  return;
2677  }
2678 
2679  // Otherwise, try to resolve it to something we know about by looking at
2680  // the actual operand type.
2681  if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
2682  OpInfo.ConstraintCode = Repl;
2684  }
2685  }
2686 }
2687 
2688 /// \brief Given an exact SDIV by a constant, create a multiplication
2689 /// with the multiplicative inverse of the constant.
2691  SDLoc dl, SelectionDAG &DAG,
2692  std::vector<SDNode *> &Created) {
2693  assert(d != 0 && "Division by zero!");
2694 
2695  // Shift the value upfront if it is even, so the LSB is one.
2696  unsigned ShAmt = d.countTrailingZeros();
2697  if (ShAmt) {
2698  // TODO: For UDIV use SRL instead of SRA.
2699  SDValue Amt =
2700  DAG.getConstant(ShAmt, dl, TLI.getShiftAmountTy(Op1.getValueType(),
2701  DAG.getDataLayout()));
2703  Flags.setExact(true);
2704  Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt, &Flags);
2705  Created.push_back(Op1.getNode());
2706  d = d.ashr(ShAmt);
2707  }
2708 
2709  // Calculate the multiplicative inverse, using Newton's method.
2710  APInt t, xn = d;
2711  while ((t = d*xn) != 1)
2712  xn *= APInt(d.getBitWidth(), 2) - t;
2713 
2714  SDValue Op2 = DAG.getConstant(xn, dl, Op1.getValueType());
2715  SDValue Mul = DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2);
2716  Created.push_back(Mul.getNode());
2717  return Mul;
2718 }
2719 
2720 /// \brief Given an ISD::SDIV node expressing a divide by constant,
2721 /// return a DAG expression to select that will generate the same value by
2722 /// multiplying by a magic number.
2723 /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
2725  SelectionDAG &DAG, bool IsAfterLegalization,
2726  std::vector<SDNode *> *Created) const {
2727  assert(Created && "No vector to hold sdiv ops.");
2728 
2729  EVT VT = N->getValueType(0);
2730  SDLoc dl(N);
2731 
2732  // Check to see if we can do this.
2733  // FIXME: We should be more aggressive here.
2734  if (!isTypeLegal(VT))
2735  return SDValue();
2736 
2737  // If the sdiv has an 'exact' bit we can use a simpler lowering.
2738  if (cast<BinaryWithFlagsSDNode>(N)->Flags.hasExact())
2739  return BuildExactSDIV(*this, N->getOperand(0), Divisor, dl, DAG, *Created);
2740 
2741  APInt::ms magics = Divisor.magic();
2742 
2743  // Multiply the numerator (operand 0) by the magic value
2744  // FIXME: We should support doing a MUL in a wider type
2745  SDValue Q;
2746  if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) :
2748  Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
2749  DAG.getConstant(magics.m, dl, VT));
2750  else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) :
2752  Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
2753  N->getOperand(0),
2754  DAG.getConstant(magics.m, dl, VT)).getNode(), 1);
2755  else
2756  return SDValue(); // No mulhs or equvialent
2757  // If d > 0 and m < 0, add the numerator
2758  if (Divisor.isStrictlyPositive() && magics.m.isNegative()) {
2759  Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
2760  Created->push_back(Q.getNode());
2761  }
2762  // If d < 0 and m > 0, subtract the numerator.
2763  if (Divisor.isNegative() && magics.m.isStrictlyPositive()) {
2764  Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
2765  Created->push_back(Q.getNode());
2766  }
2767  auto &DL = DAG.getDataLayout();
2768  // Shift right algebraic if shift value is nonzero
2769  if (magics.s > 0) {
2770  Q = DAG.getNode(
2771  ISD::SRA, dl, VT, Q,
2772  DAG.getConstant(magics.s, dl, getShiftAmountTy(Q.getValueType(), DL)));
2773  Created->push_back(Q.getNode());
2774  }
2775  // Extract the sign bit and add it to the quotient
2776  SDValue T =
2777  DAG.getNode(ISD::SRL, dl, VT, Q,
2778  DAG.getConstant(VT.getScalarSizeInBits() - 1, dl,
2780  Created->push_back(T.getNode());
2781  return DAG.getNode(ISD::ADD, dl, VT, Q, T);
2782 }
2783 
2784 /// \brief Given an ISD::UDIV node expressing a divide by constant,
2785 /// return a DAG expression to select that will generate the same value by
2786 /// multiplying by a magic number.
2787 /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
2789  SelectionDAG &DAG, bool IsAfterLegalization,
2790  std::vector<SDNode *> *Created) const {
2791  assert(Created && "No vector to hold udiv ops.");
2792 
2793  EVT VT = N->getValueType(0);
2794  SDLoc dl(N);
2795  auto &DL = DAG.getDataLayout();
2796 
2797  // Check to see if we can do this.
2798  // FIXME: We should be more aggressive here.
2799  if (!isTypeLegal(VT))
2800  return SDValue();
2801 
2802  // FIXME: We should use a narrower constant when the upper
2803  // bits are known to be zero.
2804  APInt::mu magics = Divisor.magicu();
2805 
2806  SDValue Q = N->getOperand(0);
2807 
2808  // If the divisor is even, we can avoid using the expensive fixup by shifting
2809  // the divided value upfront.
2810  if (magics.a != 0 && !Divisor[0]) {
2811  unsigned Shift = Divisor.countTrailingZeros();
2812  Q = DAG.getNode(
2813  ISD::SRL, dl, VT, Q,
2814  DAG.getConstant(Shift, dl, getShiftAmountTy(Q.getValueType(), DL)));
2815  Created->push_back(Q.getNode());
2816 
2817  // Get magic number for the shifted divisor.
2818  magics = Divisor.lshr(Shift).magicu(Shift);
2819  assert(magics.a == 0 && "Should use cheap fixup now");
2820  }
2821 
2822  // Multiply the numerator (operand 0) by the magic value
2823  // FIXME: We should support doing a MUL in a wider type
2824  if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) :
2826  Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, dl, VT));
2827  else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) :
2829  Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q,
2830  DAG.getConstant(magics.m, dl, VT)).getNode(), 1);
2831  else
2832  return SDValue(); // No mulhu or equvialent
2833 
2834  Created->push_back(Q.getNode());
2835 
2836  if (magics.a == 0) {
2837  assert(magics.s < Divisor.getBitWidth() &&
2838  "We shouldn't generate an undefined shift!");
2839  return DAG.getNode(
2840  ISD::SRL, dl, VT, Q,
2841  DAG.getConstant(magics.s, dl, getShiftAmountTy(Q.getValueType(), DL)));
2842  } else {
2843  SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
2844  Created->push_back(NPQ.getNode());
2845  NPQ = DAG.getNode(
2846  ISD::SRL, dl, VT, NPQ,
2847  DAG.getConstant(1, dl, getShiftAmountTy(NPQ.getValueType(), DL)));
2848  Created->push_back(NPQ.getNode());
2849  NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
2850  Created->push_back(NPQ.getNode());
2851  return DAG.getNode(
2852  ISD::SRL, dl, VT, NPQ,
2853  DAG.getConstant(magics.s - 1, dl,
2854  getShiftAmountTy(NPQ.getValueType(), DL)));
2855  }
2856 }
2857 
2858 bool TargetLowering::
2860  if (!isa<ConstantSDNode>(Op.getOperand(0))) {
2861  DAG.getContext()->emitError("argument to '__builtin_return_address' must "
2862  "be a constant integer");
2863  return true;
2864  }
2865 
2866  return false;
2867 }
2868 
2869 //===----------------------------------------------------------------------===//
2870 // Legalization Utilities
2871 //===----------------------------------------------------------------------===//
2872 
2874  SelectionDAG &DAG, SDValue LL, SDValue LH,
2875  SDValue RL, SDValue RH) const {
2876  EVT VT = N->getValueType(0);
2877  SDLoc dl(N);
2878 
2879  bool HasMULHS = isOperationLegalOrCustom(ISD::MULHS, HiLoVT);
2880  bool HasMULHU = isOperationLegalOrCustom(ISD::MULHU, HiLoVT);
2881  bool HasSMUL_LOHI = isOperationLegalOrCustom(ISD::SMUL_LOHI, HiLoVT);
2882  bool HasUMUL_LOHI = isOperationLegalOrCustom(ISD::UMUL_LOHI, HiLoVT);
2883  if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
2884  unsigned OuterBitSize = VT.getSizeInBits();
2885  unsigned InnerBitSize = HiLoVT.getSizeInBits();
2886  unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
2887  unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
2888 
2889  // LL, LH, RL, and RH must be either all NULL or all set to a value.
2890  assert((LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) ||
2891  (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode()));
2892 
2893  if (!LL.getNode() && !RL.getNode() &&
2895  LL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, N->getOperand(0));
2896  RL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, N->getOperand(1));
2897  }
2898 
2899  if (!LL.getNode())
2900  return false;
2901 
2902  APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
2903  if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
2904  DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
2905  // The inputs are both zero-extended.
2906  if (HasUMUL_LOHI) {
2907  // We can emit a umul_lohi.
2908  Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(HiLoVT, HiLoVT), LL,
2909  RL);
2910  Hi = SDValue(Lo.getNode(), 1);
2911  return true;
2912  }
2913  if (HasMULHU) {
2914  // We can emit a mulhu+mul.
2915  Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2916  Hi = DAG.getNode(ISD::MULHU, dl, HiLoVT, LL, RL);
2917  return true;
2918  }
2919  }
2920  if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
2921  // The input values are both sign-extended.
2922  if (HasSMUL_LOHI) {
2923  // We can emit a smul_lohi.
2924  Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(HiLoVT, HiLoVT), LL,
2925  RL);
2926  Hi = SDValue(Lo.getNode(), 1);
2927  return true;
2928  }
2929  if (HasMULHS) {
2930  // We can emit a mulhs+mul.
2931  Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2932  Hi = DAG.getNode(ISD::MULHS, dl, HiLoVT, LL, RL);
2933  return true;
2934  }
2935  }
2936 
2937  if (!LH.getNode() && !RH.getNode() &&
2940  auto &DL = DAG.getDataLayout();
2941  unsigned ShiftAmt = VT.getSizeInBits() - HiLoVT.getSizeInBits();
2942  SDValue Shift = DAG.getConstant(ShiftAmt, dl, getShiftAmountTy(VT, DL));
2943  LH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(0), Shift);
2944  LH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LH);
2945  RH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(1), Shift);
2946  RH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RH);
2947  }
2948 
2949  if (!LH.getNode())
2950  return false;
2951 
2952  if (HasUMUL_LOHI) {
2953  // Lo,Hi = umul LHS, RHS.
2954  SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
2955  DAG.getVTList(HiLoVT, HiLoVT), LL, RL);
2956  Lo = UMulLOHI;
2957  Hi = UMulLOHI.getValue(1);
2958  RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH);
2959  LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL);
2960  Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH);
2961  Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH);
2962  return true;
2963  }
2964  if (HasMULHU) {
2965  Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2966  Hi = DAG.getNode(ISD::MULHU, dl, HiLoVT, LL, RL);
2967  RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH);
2968  LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL);
2969  Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH);
2970  Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH);
2971  return true;
2972  }
2973  }
2974  return false;
2975 }
2976 
2978  SelectionDAG &DAG) const {
2979  EVT VT = Node->getOperand(0).getValueType();
2980  EVT NVT = Node->getValueType(0);
2981  SDLoc dl(SDValue(Node, 0));
2982 
2983  // FIXME: Only f32 to i64 conversions are supported.
2984  if (VT != MVT::f32 || NVT != MVT::i64)
2985  return false;
2986 
2987  // Expand f32 -> i64 conversion
2988  // This algorithm comes from compiler-rt's implementation of fixsfdi:
2989  // https://github.com/llvm-mirror/compiler-rt/blob/master/lib/builtins/fixsfdi.c
2990  EVT IntVT = EVT::getIntegerVT(*DAG.getContext(),
2991  VT.getSizeInBits());
2992  SDValue ExponentMask = DAG.getConstant(0x7F800000, dl, IntVT);
2993  SDValue ExponentLoBit = DAG.getConstant(23, dl, IntVT);
2994  SDValue Bias = DAG.getConstant(127, dl, IntVT);
2995  SDValue SignMask = DAG.getConstant(APInt::getSignBit(VT.getSizeInBits()), dl,
2996  IntVT);
2997  SDValue SignLowBit = DAG.getConstant(VT.getSizeInBits() - 1, dl, IntVT);
2998  SDValue MantissaMask = DAG.getConstant(0x007FFFFF, dl, IntVT);
2999 
3000  SDValue Bits = DAG.getNode(ISD::BITCAST, dl, IntVT, Node->getOperand(0));
3001 
3002  auto &DL = DAG.getDataLayout();
3003  SDValue ExponentBits = DAG.getNode(
3004  ISD::SRL, dl, IntVT, DAG.getNode(ISD::AND, dl, IntVT, Bits, ExponentMask),
3005  DAG.getZExtOrTrunc(ExponentLoBit, dl, getShiftAmountTy(IntVT, DL)));
3006  SDValue Exponent = DAG.getNode(ISD::SUB, dl, IntVT, ExponentBits, Bias);
3007 
3008  SDValue Sign = DAG.getNode(
3009  ISD::SRA, dl, IntVT, DAG.getNode(ISD::AND, dl, IntVT, Bits, SignMask),
3010  DAG.getZExtOrTrunc(SignLowBit, dl, getShiftAmountTy(IntVT, DL)));
3011  Sign = DAG.getSExtOrTrunc(Sign, dl, NVT);
3012 
3013  SDValue R = DAG.getNode(ISD::OR, dl, IntVT,
3014  DAG.getNode(ISD::AND, dl, IntVT, Bits, MantissaMask),
3015  DAG.getConstant(0x00800000, dl, IntVT));
3016 
3017  R = DAG.getZExtOrTrunc(R, dl, NVT);
3018 
3019  R = DAG.getSelectCC(
3020  dl, Exponent, ExponentLoBit,
3021  DAG.getNode(ISD::SHL, dl, NVT, R,
3022  DAG.getZExtOrTrunc(
3023  DAG.getNode(ISD::SUB, dl, IntVT, Exponent, ExponentLoBit),
3024  dl, getShiftAmountTy(IntVT, DL))),
3025  DAG.getNode(ISD::SRL, dl, NVT, R,
3026  DAG.getZExtOrTrunc(
3027  DAG.getNode(ISD::SUB, dl, IntVT, ExponentLoBit, Exponent),
3028  dl, getShiftAmountTy(IntVT, DL))),
3029  ISD::SETGT);
3030 
3031  SDValue Ret = DAG.getNode(ISD::SUB, dl, NVT,
3032  DAG.getNode(ISD::XOR, dl, NVT, R, Sign),
3033  Sign);
3034 
3035  Result = DAG.getSelectCC(dl, Exponent, DAG.getConstant(0, dl, IntVT),
3036  DAG.getConstant(0, dl, NVT), Ret, ISD::SETLT);
3037  return true;
3038 }
bool hasType(MVT vt) const
hasType - return true if this TargetRegisterClass has the ValueType vt.
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:477
APInt LLVM_ATTRIBUTE_UNUSED_RESULT ashr(unsigned shiftAmt) const
Arithmetic right-shift function.
Definition: APInt.cpp:1051
static MVT getIntegerVT(unsigned BitWidth)
unsigned Log2_32_Ceil(uint32_t Value)
Log2_32_Ceil - This function returns the ceil log base 2 of the specified value, 32 if the value is z...
Definition: MathExtras.h:481
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:724
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:104
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
mu magicu(unsigned LeadingZeros=0) const
Calculate the magic numbers required to implement an unsigned integer division by a constant as a seq...
Definition: APInt.cpp:1461
SDValue getValue(unsigned R) const
static APInt getSignBit(unsigned BitWidth)
Get the SignBit for a specific bit width.
Definition: APInt.h:446
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT, SelectionDAG &DAG, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) const
Expand a MUL into two nodes.
static APInt getAllOnesValue(unsigned numBits)
Get the all-ones value.
Definition: APInt.h:453
LLVMContext * getContext() const
Definition: SelectionDAG.h:289
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:315
size_t size() const
size - Get the string size.
Definition: StringRef.h:113
Sign extended before/after call.
Definition: Attributes.h:105
bool none() const
none - Returns true if none of the bits are set.
Definition: BitVector.h:150
Various leaf nodes.
Definition: ISDOpcodes.h:60
SDValue getBoolExtOrTrunc(SDValue Op, SDLoc SL, EVT VT, EVT OpVT)
Convert Op, which must be of integer type, to the integer type VT, by using an extension appropriate ...
ValTy * getArgument(unsigned ArgNo) const
Definition: CallSite.h:119
bool hasOneUse() const
Return true if there is exactly one use of this node.
Force argument to be passed in register.
Definition: Attributes.h:78
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded)
Check to see if the specified operand of the specified instruction is a constant integer.
const TargetMachine & getTargetMachine() const
CallLoweringInfo & setDebugLoc(SDLoc dl)
bool isConstTrueVal(const SDNode *N) const
Return if the N is a constant or constant vector equal to the true value from getBooleanContents().
Nested function static chain.
Definition: Attributes.h:82
unsigned s
shift amount
Definition: APInt.h:1724
void computeKnownBits(SDValue Op, APInt &KnownZero, APInt &KnownOne, unsigned Depth=0) const
Determine which bits of Op are known to be either zero or one and return them in the KnownZero/KnownO...
MVT getSimpleValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the MVT corresponding to this LLVM type. See getValueType.
bool hasExact() const
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Get a value with low bits set.
Definition: APInt.h:531
const GlobalValue * getGlobal() const
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
SDValue getSelectCC(SDLoc DL, SDValue LHS, SDValue RHS, SDValue True, SDValue False, ISD::CondCode Cond)
Helper function to make it easier to build SelectCC's if you just have an ISD::CondCode instead of an...
Definition: SelectionDAG.h:752
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition: StringRef.h:405
Type * getTypeForEVT(LLVMContext &Context) const
getTypeForEVT - This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:181
unsigned getSizeInBits() const
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
bool isUnindexed() const
Return true if this is NOT a pre/post inc/dec load/store.
bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded, SDLoc dl)
Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free.
regclass_iterator regclass_end() const
virtual bool isLegalICmpImmediate(int64_t) const
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
unsigned getNumOperands() const
unsigned getValueSizeInBits() const
Returns the size of the value in bits.
virtual bool isZExtFree(Type *, Type *) const
Return true if any actual instruction that defines a value of type Ty1 implicitly zero-extends the va...
const SDValue & getOperand(unsigned Num) const
F(f)
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
ms magic() const
Calculate the magic numbers required to implement a signed integer division by a constant as a sequen...
Definition: APInt.cpp:1417
bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const
Expand float(f32) to SINT(i64) conversion.
static bool isCommutativeBinOp(unsigned Opcode)
Returns true if the opcode is a commutative binary operation.
ConstantSDNode * getConstantSplatNode(BitVector *UndefElements=nullptr) const
Returns the splatted constant or null if this is not a constant splat.
Value * CallOperandVal
If this is the result output operand or a clobber, this is null, otherwise it is the incoming operand...
bool hasAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return true if the attribute exists at the given index.
Definition: Attributes.cpp:956
bool isTrueWhenEqual(CondCode Cond)
isTrueWhenEqual - Return true if the specified condition returns true if the two operands to the cond...
Definition: ISDOpcodes.h:850
const SDValue & getBasePtr() const
CallLoweringInfo & setDiscardResult(bool Value=true)
SDValue BuildUDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode * > *Created) const
Given an ISD::UDIV node expressing a divide by constant, return a DAG expression to select that will ...
Magic data for optimising unsigned division by a constant.
Definition: APInt.h:1728
virtual bool isTypeDesirableForOp(unsigned, EVT VT) const
Return true if the target has native support for the specified value type and it is 'desirable' to us...
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:357
static APInt getSignedMaxValue(unsigned numBits)
Gets maximum signed value of APInt for a specific bit width.
Definition: APInt.h:426
bool bitsLT(EVT VT) const
bitsLT - Return true if this has less bits than VT.
Definition: ValueTypes.h:189
bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, APInt &KnownZero, APInt &KnownOne, TargetLoweringOpt &TLO, unsigned Depth=0) const
Look at Op.
INT = FGETSIGN(FP) - Return the sign bit of the specified floating point value as an integer 0/1 valu...
Definition: ISDOpcodes.h:254
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag=true)
Reports a serious error, calling any installed error handler.
bool isAllOnesValue() const
SDValue getExternalSymbol(const char *Sym, EVT VT)
ConstraintCodeVector Codes
Code - The constraint code, either the register name (in braces) or the constraint letter/number...
Definition: InlineAsm.h:148
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
Definition: ISDOpcodes.h:150
A convenience struct that encapsulates a DAG, and two SDValues for returning information from TargetL...
bool isSingleValueType() const
isSingleValueType - Return true if the type is a valid type for a register in codegen.
Definition: Type.h:250
bool isNegative() const
Determine sign of this APInt.
Definition: APInt.h:319
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:115
virtual const char * LowerXConstraint(EVT ConstraintVT) const
Try to replace an X constraint, which matches anything, with another that has more specific requireme...
lazy value info
void setAttributes(ImmutableCallSite *CS, unsigned AttrIdx)
Set CallLoweringInfo attribute flags based on a call instruction and called function attributes...
virtual const char * getTargetNodeName(unsigned Opcode) const
This method returns the name of a target specific DAG node.
bool isRound() const
isRound - Return true if the size is a power-of-two number of bytes.
Definition: ValueTypes.h:165
virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Shift and rotation operations.
Definition: ISDOpcodes.h:332
StructType - Class to represent struct types.
Definition: DerivedTypes.h:191
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:98
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:283
std::pair< SDValue, SDValue > makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops, unsigned NumOps, bool isSigned, SDLoc dl, bool doesNotReturn=false, bool isReturnValueUsed=true) const
Returns a pair of (return value, chain).
TargetLowering::ConstraintType ConstraintType
Information about the constraint code, e.g.
virtual void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth=0) const
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
APInt LLVM_ATTRIBUTE_UNUSED_RESULT lshr(unsigned shiftAmt) const
Logical right-shift function.
Definition: APInt.cpp:1142
CallLoweringInfo & setChain(SDValue InChain)
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
Definition: ISDOpcodes.h:181
SDValue getTargetGlobalAddress(const GlobalValue *GV, SDLoc DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:467
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:33
iterator begin() const
begin/end - Return all of the registers in this class.
MachinePointerInfo getWithOffset(int64_t O) const
bool isSized(SmallPtrSetImpl< const Type * > *Visited=nullptr) const
isSized - Return true if it makes sense to take the size of this type.
Definition: Type.h:268
EVT getScalarType() const
getScalarType - If this is a vector type, return the element type, otherwise return this...
Definition: ValueTypes.h:210
bool isStrongDefinitionForLinker() const
Returns true if this global's definition will be the one chosen by the linker.
Definition: GlobalValue.h:353
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
uint16_t getParamAlignment(uint16_t i) const
Extract the alignment for a call or parameter (0=unknown).
Definition: CallSite.h:247
SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, SDLoc dl) const
Try to simplify a setcc built with the specified operands and cc.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Hidden pointer to structure to return.
Definition: Attributes.h:114
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
Definition: ValueTypes.h:110
Context object for machine code objects.
Definition: MCContext.h:48
void emitError(unsigned LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
virtual bool isUsedByReturnOnly(SDNode *, SDValue &) const
Return true if result of the specified node is used by a return node only.
LLVMContext & getContext() const
getContext - Return the LLVMContext in which this type was uniqued.
Definition: Type.h:125
static SDNodeIterator begin(const SDNode *N)
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
ValTy * getCalledValue() const
getCalledValue - Return the pointer to function that is being called.
Definition: CallSite.h:91
EK_LabelDifference32 - Each entry is the address of the block minus the address of the jump table...
const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
Definition: StringRef.h:107
This contains information for each constraint that we are lowering.
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:191
EK_BlockAddress - Each entry is a plain address of block, e.g.
CallLoweringInfo & setZExtResult(bool Value=true)
bool isLittleEndian() const
Layout endianness...
Definition: DataLayout.h:217
signed char MatchingInput
MatchingInput - If this is not -1, this is an output constraint where an input constraint is required...
Definition: InlineAsm.h:130
Pass structure by value.
Definition: Attributes.h:73
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
Definition: SelectionDAG.h:659
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:804
const APInt & getAPIntValue() const
APInt LLVM_ATTRIBUTE_UNUSED_RESULT shl(unsigned shiftAmt) const
Left-shift function.
Definition: APInt.h:868
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
EVT getMemoryVT() const
Return the type of the in-memory value.
ConstraintPrefix Type
Type - The basic type of the constraint: input/output/clobber.
Definition: InlineAsm.h:120
bool isSignedIntSetCC(CondCode Code)
isSignedIntSetCC - Return true if this is a setcc instruction that performs a signed comparison when ...
Definition: ISDOpcodes.h:837
unsigned getMinSignedBits() const
Get the minimum bit size for this signed APInt.
Definition: APInt.h:1316
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
Definition: ISDOpcodes.h:142
Type * getElementType() const
Definition: DerivedTypes.h:323
Considered to not alias after call.
Definition: Attributes.h:83
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:284
bool bitsLE(EVT VT) const
bitsLE - Return true if this has no more bits than VT.
Definition: ValueTypes.h:195
bool isLegalRC(const TargetRegisterClass *RC) const
Return true if the value types that can be represented by the specified register class are all legal...
PointerType - Class to represent pointers.
Definition: DerivedTypes.h:449
UNDEF - An undefined node.
Definition: ISDOpcodes.h:169
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Get a value with high bits set.
Definition: APInt.h:513
SDNode * getNode() const
get the SDNode which holds the desired result
unsigned getScalarSizeInBits() const
Definition: ValueTypes.h:239
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
bool isMatchingInputConstraint() const
Return true of this is an input operand that is a matching constraint like "4".
EK_GPRel64BlockAddress - Each entry is an address of block, encoded with a relocation as gp-relative...
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
Definition: ISDOpcodes.h:157
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
bool intersects(const APInt &RHS) const
This operation tests if there are any pairs of corresponding bits between this APInt and RHS that are...
Definition: APInt.h:1165
regclass_iterator regclass_begin() const
Register class iterators.
APInt LLVM_ATTRIBUTE_UNUSED_RESULT trunc(unsigned width) const
Truncate to new width.
Definition: APInt.cpp:932
MVT - Machine Value Type.
const SDValue & getOperand(unsigned i) const
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
bool isIndirect
isIndirect - True if this operand is an indirect operand.
Definition: InlineAsm.h:144
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG)
ValueHasExactlyOneBitSet - Test if the given value is known to have exactly one bit set...
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1339
unsigned getMatchedOperand() const
If this is an input matching constraint, this method returns the output operand it matches...
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, const TargetLowering &TLI, SDValue Op, SelectionDAG *DAG)
ChooseConstraint - If there are multiple different constraints that we could pick for this operand (e...
Return value is always equal to this argument.
Definition: Attributes.h:103
SubConstraintInfoVector multipleAlternatives
multipleAlternatives - If there are multiple alternative constraints, this array will contain them...
Definition: InlineAsm.h:155
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
APInt getLoBits(unsigned numBits) const
Compute an APInt containing numBits lowbits from this APInt.
Definition: APInt.cpp:689
virtual bool isTruncateFree(Type *, Type *) const
Return true if it's free to truncate a value of type Ty1 to type Ty2.
Pass structure in an alloca.
Definition: Attributes.h:74
SDValue getSExtOrTrunc(SDValue Op, SDLoc DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either sign-extending or trunca...
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang","erlang-compatible garbage collector")
SDValue getTargetConstant(uint64_t Val, SDLoc DL, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:436
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1273
bool CombineTo(SDValue O, SDValue N)
unsigned getOpcode() const
for(unsigned i=0, e=MI->getNumOperands();i!=e;++i)
Zero extended before/after call.
Definition: Attributes.h:119
unsigned getUnorderedFlavor(CondCode Cond)
getUnorderedFlavor - This function returns 0 if the condition is always false if an operand is a NaN...
Definition: ISDOpcodes.h:858
CondCode getSetCCSwappedOperands(CondCode Operation)
getSetCCSwappedOperands - Return the operation corresponding to (Y op X) when given the operation for...
static MVT getVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
Definition: ValueTypes.cpp:249
unsigned countPopulation() const
Count the number of bits set.
Definition: APInt.h:1415
bool isVolatile() const
bool isConstFalseVal(const SDNode *N) const
Return if the N is a constant or constant vector equal to the false value from getBooleanContents().
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth=0) const
Return true if 'Op & Mask' is known to be zero.
SDValue BuildSDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode * > *Created) const
Given an ISD::SDIV node expressing a divide by constant, return a DAG expression to select that will ...
EVT - Extended Value Type.
Definition: ValueTypes.h:31
bool isIntN(unsigned N, int64_t x)
isIntN - Checks if an signed integer fits into the given (dynamic) bit width.
Definition: MathExtras.h:321
uint64_t NextPowerOf2(uint64_t A)
NextPowerOf2 - Returns the next power of two (in 64-bits) that is strictly greater than A...
Definition: MathExtras.h:582
std::vector< ArgListEntry > ArgListTy
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
For targets without i1 registers, this gives the nature of the high-bits of boolean values held in ty...
std::string ConstraintCode
This contains the actual string for the code, like "m".
virtual SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const
Returns relocation base for the given PIC jumptable.
virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=nullptr) const
Determines the constraint code and constraint type to use for the specific AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
const MachinePointerInfo & getPointerInfo() const
This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from ...
ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const
Get the CondCode that's to be used to test the result of the comparison libcall against zero...
bool bitsGT(EVT VT) const
bitsGT - Return true if this has more bits than VT.
Definition: ValueTypes.h:177
unsigned countTrailingZeros() const
Count the number of trailing zero bits.
Definition: APInt.cpp:749
std::vector< AsmOperandInfo > AsmOperandInfoVector
static IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
Definition: Type.cpp:304
std::vector< std::string > ConstraintCodeVector
Definition: InlineAsm.h:98
SDValue getNOT(SDLoc DL, SDValue Val, EVT VT)
Create a bitwise NOT operation as (XOR Val, -1).
SmallVectorImpl< T >::const_pointer c_str(SmallVectorImpl< T > &str)
virtual unsigned getJumpTableEncoding() const
Return the entry encoding for a jump table in the current function.
APInt getHiBits(unsigned numBits) const
Compute an APInt containing numBits highbits from this APInt.
Definition: APInt.cpp:684
const char * getLibcallName(RTLIB::Libcall Call) const
Get the libcall routine name for the specified libcall.
bool paramHasAttr(unsigned i, Attribute::AttrKind A) const
Return true if the call or the callee has the given attribute.
Definition: CallSite.h:242
double Log2(double Value)
Log2 - This function returns the log base 2 of the specified value.
Definition: MathExtras.h:457
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:179
APInt m
magic number
Definition: APInt.h:1729
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:222
virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const
Return the ValueType of the result of SETCC operations.
const SDValue & getChain() const
bool hasMatchingInput() const
hasMatchingInput - Return true if this is an output constraint that has a matching input constraint...
Definition: InlineAsm.h:134
bool isStrictlyPositive() const
Determine if this APInt Value is positive.
Definition: APInt.h:332
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static APInt getMinValue(unsigned numBits)
Gets minimum unsigned value of APInt for a specific bit width.
Definition: APInt.h:433
CallLoweringInfo & setSExtResult(bool Value=true)
virtual const MCExpr * getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const
This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase, but as an MCExpr.
virtual bool isGAPlusOffset(SDNode *N, const GlobalValue *&GA, int64_t &Offset) const
Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + offset...
Represents one node in the SelectionDAG.
CondCode getSetCCInverse(CondCode Operation, bool isInteger)
getSetCCInverse - Return the operation corresponding to !(X op Y), where 'op' is a valid SetCC operat...
virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const
Returns true if arguments should be sign-extended in lib calls.
virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const SelectionDAG &DAG, unsigned Depth=0) const
This method can be implemented by targets that want to expose additional information about sign bits ...
bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node, SDValue &Chain) const
Check whether a given call node is in tail position within its function.
unsigned Log2_32(uint32_t Value)
Log2_32 - This function returns the floor log base 2 of the specified value, -1 if the value is zero...
Definition: MathExtras.h:468
AttributeSet getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:181
MCSymbol * getJTISymbol(unsigned JTI, MCContext &Ctx, bool isLinkerPrivate=false) const
getJTISymbol - Return the MCSymbol for the specified non-empty jump table.
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
Class for arbitrary precision integers.
Definition: APInt.h:73
A "pseudo-class" with methods for operating on BUILD_VECTORs.
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:342
int64_t getSExtValue() const
bool isIntegerTy() const
isIntegerTy - True if this is an instance of IntegerType.
Definition: Type.h:193
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:383
static SDValue BuildExactSDIV(const TargetLowering &TLI, SDValue Op1, APInt d, SDLoc dl, SelectionDAG &DAG, std::vector< SDNode * > &Created)
Given an exact SDIV by a constant, create a multiplication with the multiplicative inverse of the con...
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:285
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:386
static APInt getMaxValue(unsigned numBits)
Gets maximum unsigned value of APInt for specific bit width.
Definition: APInt.h:421
APInt And(const APInt &LHS, const APInt &RHS)
Bitwise AND function for APInt.
Definition: APInt.h:1890
static APInt getBitsSet(unsigned numBits, unsigned loBit, unsigned hiBit)
Get a value with a block of bits set.
Definition: APInt.h:498
virtual MVT::SimpleValueType getCmpLibcallReturnType() const
Return the ValueType for comparison libcalls.
bool isAllOnesValue() const
Determine if all bits are set.
Definition: APInt.h:337
uint64_t MinAlign(uint64_t A, uint64_t B)
MinAlign - A and B are either alignments or offsets.
Definition: MathExtras.h:552
These are IR-level optimization flags that may be propagated to SDNodes.
Magic data for optimising signed division by a constant.
Definition: APInt.h:1722
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:321
unsigned s
shift amount
Definition: APInt.h:1731
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:196
APInt m
magic number
Definition: APInt.h:1723
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:401
ImmutableCallSite - establish a view to a call site for examination.
Definition: CallSite.h:418
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:233
#define I(x, y, z)
Definition: MD5.cpp:54
#define N
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:329
SDValue FoldSetCC(EVT VT, SDValue N1, SDValue N2, ISD::CondCode Cond, SDLoc dl)
Constant fold a setcc to true or false.
static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT)
getConstraintGenerality - Return an integer indicating how general CT is.
EVT getValueType() const
Return the ValueType of the referenced return value.
SDValue getCondCode(ISD::CondCode Cond)
SDValue getConstant(uint64_t Val, SDLoc DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Type * getType() const
getType - Return the type of the instruction that generated this call site
Definition: CallSite.h:166
SDValue getGLOBAL_OFFSET_TABLE(EVT VT)
Return a GLOBAL_OFFSET_TABLE node. This does not have a useful SDLoc.
Definition: SelectionDAG.h:664
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
Definition: ValueTypes.h:105
static APInt getSignedMinValue(unsigned numBits)
Gets minimum signed value of APInt for a specific bit width.
Definition: APInt.h:436
bool isSimple() const
isSimple - Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:94
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
SDValue getZExtOrTrunc(SDValue Op, SDLoc DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either zero-extending or trunca...
LLVM Value Representation.
Definition: Value.h:69
static SDNodeIterator end(const SDNode *N)
unsigned ComputeNumSignBits(SDValue Op, unsigned Depth=0) const
Return the number of times the sign bit of the register is replicated into the other bits...
virtual ConstraintWeight getMultipleConstraintMatchWeight(AsmOperandInfo &info, int maIndex) const
Examine constraint type and operand type and determine a weight value.
iterator end() const
Definition: StringRef.h:92
uint64_t getTypeSizeInBits(Type *Ty) const
Size examples:
Definition: DataLayout.h:507
unsigned countLeadingZeros() const
The APInt version of the countLeadingZeros functions in MathExtras.h.
Definition: APInt.h:1361
Primary interface to the complete machine description for the target machine.
const char * getName(unsigned RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register...
bool isPowerOf2_32(uint32_t Value)
isPowerOf2_32 - This function returns true if the argument is a power of two > 0. ...
Definition: MathExtras.h:354
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:40
APInt LLVM_ATTRIBUTE_UNUSED_RESULT zext(unsigned width) const
Zero extend to a new width.
Definition: APInt.cpp:996
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:365
EK_GPRel32BlockAddress - Each entry is an address of block, encoded with a relocation as gp-relative...
virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const
Return true if folding a constant offset with the given GlobalAddress is legal.
MVT ConstraintVT
The ValueType for the operand value.
SDValue getSetCC(SDLoc DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
Definition: SelectionDAG.h:726
Conversion operators.
Definition: ISDOpcodes.h:380
BooleanContent
Enum that describes how the target represents true/false values.
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:338
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:389
EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL) const
unsigned getAlignment() const
bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const
Return true if the specified condition code is legal on this target.
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
Examine constraint string and operand type and determine a weight value.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
getIntegerVT - Returns the EVT that represents an integer with the given number of bits...
Definition: ValueTypes.h:61
const TargetRegisterClass *const * regclass_iterator
virtual AsmOperandInfoVector ParseConstraints(const DataLayout &DL, const TargetRegisterInfo *TRI, ImmutableCallSite CS) const
Split up the constraint string from the inline assembly value into the specific constraints and their...
LegalizeAction getCondCodeAction(ISD::CondCode CC, MVT VT) const
Return how the condition code should be treated: either it is legal, needs to be expanded to some oth...
MVT getSimpleVT() const
getSimpleVT - Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:203
static ConstraintInfoVector ParseConstraints(StringRef ConstraintString)
ParseConstraints - Split up the constraint string into the specific constraints and their prefixes...
Definition: InlineAsm.cpp:209
bool a
add indicator
Definition: APInt.h:1730
This file describes how to lower LLVM code to machine code.
bool isVoidTy() const
isVoidTy - Return true if this is 'void'.
Definition: Type.h:137
void selectAlternative(unsigned index)
selectAlternative - Point this constraint to the alternative constraint indicated by the index...
Definition: InlineAsm.cpp:198
bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:110
uint64_t getZExtValue() const
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:314
void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, SDLoc DL) const
SoftenSetCCOperands - Soften the operands of a comparison.
This class is used to represent ISD::LOAD nodes.