LLVM  3.7.0
Public Member Functions | Protected Member Functions | List of all members
llvm::ARMTargetLowering Class Reference

#include <ARMISelLowering.h>

Inheritance diagram for llvm::ARMTargetLowering:
[legend]
Collaboration diagram for llvm::ARMTargetLowering:
[legend]

Public Member Functions

 ARMTargetLowering (const TargetMachine &TM, const ARMSubtarget &STI)
 
unsigned getJumpTableEncoding () const override
 Return the entry encoding for a jump table in the current function. More...
 
bool useSoftFloat () const override
 
SDValue LowerOperation (SDValue Op, SelectionDAG &DAG) const override
 This callback is invoked for operations that are unsupported by the target, which are registered to use 'custom' lowering, and whose defined values are all legal. More...
 
void ReplaceNodeResults (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
 ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code. More...
 
const char * getTargetNodeName (unsigned Opcode) const override
 This method returns the name of a target specific DAG node. More...
 
bool isSelectSupported (SelectSupportKind Kind) const override
 
EVT getSetCCResultType (const DataLayout &DL, LLVMContext &Context, EVT VT) const override
 getSetCCResultType - Return the value type to use for ISD::SETCC. More...
 
MachineBasicBlockEmitInstrWithCustomInserter (MachineInstr *MI, MachineBasicBlock *MBB) const override
 This method should be implemented by targets that mark instructions with the 'usesCustomInserter' flag. More...
 
void AdjustInstrPostInstrSelection (MachineInstr *MI, SDNode *Node) const override
 This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag. More...
 
SDValue PerformCMOVCombine (SDNode *N, SelectionDAG &DAG) const
 PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV. More...
 
SDValue PerformDAGCombine (SDNode *N, DAGCombinerInfo &DCI) const override
 This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for. More...
 
bool isDesirableToTransformToIntegerOp (unsigned Opc, EVT VT) const override
 Return true if it is profitable for dag combiner to transform a floating point op of specified opcode to a equivalent op of an integer type. More...
 
bool allowsMisalignedMemoryAccesses (EVT VT, unsigned AddrSpace, unsigned Align, bool *Fast) const override
 allowsMisalignedMemoryAccesses - Returns true if the target allows unaligned memory accesses of the specified type. More...
 
EVT getOptimalMemOpType (uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, MachineFunction &MF) const override
 Returns the target specific optimal type for load and store operations as a result of memset, memcpy, and memmove lowering. More...
 
bool isZExtFree (SDValue Val, EVT VT2) const override
 Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicitly zero-extended such as ARM ldrb / ldrh or because it's folded such as X86 zero-extending loads). More...
 
bool isVectorLoadExtDesirable (SDValue ExtVal) const override
 Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable. More...
 
bool allowTruncateForTailCall (Type *Ty1, Type *Ty2) const override
 Return true if a truncation from Ty1 to Ty2 is permitted when deciding whether a call is in tail position. More...
 
bool isLegalAddressingMode (const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override
 isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type. More...
 
bool isLegalT2ScaledAddressingMode (const AddrMode &AM, EVT VT) const
 
bool isLegalICmpImmediate (int64_t Imm) const override
 isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register. More...
 
bool isLegalAddImmediate (int64_t Imm) const override
 isLegalAddImmediate - Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register and the immediate without having to materialize the immediate into a register. More...
 
bool getPreIndexedAddressParts (SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
 getPreIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mode by reference if the node's address can be legally represented as pre-indexed load / store address. More...
 
bool getPostIndexedAddressParts (SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
 getPostIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store. More...
 
void computeKnownBitsForTargetNode (const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth) const override
 Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets. More...
 
bool ExpandInlineAsm (CallInst *CI) const override
 This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to. More...
 
ConstraintType getConstraintType (StringRef Constraint) const override
 getConstraintType - Given a constraint letter, return the type of constraint it is for this target. More...
 
ConstraintWeight getSingleConstraintMatchWeight (AsmOperandInfo &info, const char *constraint) const override
 Examine constraint string and operand type and determine a weight value. More...
 
std::pair< unsigned, const
TargetRegisterClass * > 
getRegForInlineAsmConstraint (const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
 Given a physical register constraint (e.g. More...
 
void LowerAsmOperandForConstraint (SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
 LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector. More...
 
unsigned getInlineAsmMemConstraint (StringRef ConstraintCode) const override
 
const ARMSubtargetgetSubtarget () const
 
const TargetRegisterClassgetRegClassFor (MVT VT) const override
 getRegClassFor - Return the register class that should be used for the specified value type. More...
 
bool isNoopAddrSpaceCast (unsigned SrcAS, unsigned DestAS) const override
 Returns true if a cast between SrcAS and DestAS is a noop. More...
 
bool shouldAlignPointerArgs (CallInst *CI, unsigned &MinSize, unsigned &PrefAlign) const override
 Return true if the pointer arguments to CI should be aligned by aligning the object whose address is being passed. More...
 
FastISelcreateFastISel (FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
 createFastISel - This method returns a target specific FastISel object, or null if the target does not support "fast" ISel. More...
 
Sched::Preference getSchedulingPreference (SDNode *N) const override
 Some scheduler, e.g. More...
 
bool isShuffleMaskLegal (const SmallVectorImpl< int > &M, EVT VT) const override
 isShuffleMaskLegal - Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks. More...
 
bool isOffsetFoldingLegal (const GlobalAddressSDNode *GA) const override
 Return true if folding a constant offset with the given GlobalAddress is legal. More...
 
bool isFPImmLegal (const APFloat &Imm, EVT VT) const override
 isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively. More...
 
bool getTgtMemIntrinsic (IntrinsicInfo &Info, const CallInst &I, unsigned Intrinsic) const override
 getTgtMemIntrinsic - Represent NEON load and store intrinsics as MemIntrinsicNodes. More...
 
bool shouldConvertConstantLoadToIntImm (const APInt &Imm, Type *Ty) const override
 Returns true if it is beneficial to convert a load of a constant to just the constant itself. More...
 
bool functionArgumentNeedsConsecutiveRegisters (Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override
 Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calling convention CallConv. More...
 
bool hasLoadLinkedStoreConditional () const override
 True if AtomicExpandPass should use emitLoadLinked/emitStoreConditional and expand AtomicCmpXchgInst. More...
 
InstructionmakeDMB (IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) const
 
ValueemitLoadLinked (IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const override
 Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type. More...
 
ValueemitStoreConditional (IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const override
 Perform a store-conditional operation to Addr. More...
 
InstructionemitLeadingFence (IRBuilder<> &Builder, AtomicOrdering Ord, bool IsStore, bool IsLoad) const override
 Inserts in the IR a target-specific intrinsic specifying a fence. More...
 
InstructionemitTrailingFence (IRBuilder<> &Builder, AtomicOrdering Ord, bool IsStore, bool IsLoad) const override
 
unsigned getMaxSupportedInterleaveFactor () const override
 Get the maximum supported factor for interleaved memory accesses. More...
 
bool lowerInterleavedLoad (LoadInst *LI, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const override
 Lower an interleaved load into a vldN intrinsic. More...
 
bool lowerInterleavedStore (StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const override
 Lower an interleaved store into a vstN intrinsic. More...
 
bool shouldExpandAtomicLoadInIR (LoadInst *LI) const override
 Returns true if the given (atomic) load should be expanded by the IR-level AtomicExpand pass into a load-linked instruction (through emitLoadLinked()). More...
 
bool shouldExpandAtomicStoreInIR (StoreInst *SI) const override
 Returns true if the given (atomic) store should be expanded by the IR-level AtomicExpand pass into an "atomic xchg" which ignores its input. More...
 
TargetLoweringBase::AtomicRMWExpansionKind shouldExpandAtomicRMWInIR (AtomicRMWInst *AI) const override
 Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all. More...
 
bool useLoadStackGuardNode () const override
 If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector. More...
 
bool canCombineStoreAndExtract (Type *VectorTy, Value *Idx, unsigned &Cost) const override
 Return true if the target can combine store(extractelement VectorTy, Idx). More...
 
- Public Member Functions inherited from llvm::TargetLowering
 TargetLowering (const TargetMachine &TM)
 NOTE: The TargetMachine owns TLOF. More...
 
virtual const MCExprLowerCustomJumpTableEntry (const MachineJumpTableInfo *, const MachineBasicBlock *, unsigned, MCContext &) const
 
virtual SDValue getPICJumpTableRelocBase (SDValue Table, SelectionDAG &DAG) const
 Returns relocation base for the given PIC jumptable. More...
 
virtual const MCExprgetPICJumpTableRelocBaseExpr (const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const
 This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase, but as an MCExpr. More...
 
bool isInTailCallPosition (SelectionDAG &DAG, SDNode *Node, SDValue &Chain) const
 Check whether a given call node is in tail position within its function. More...
 
void softenSetCCOperands (SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, SDLoc DL) const
 SoftenSetCCOperands - Soften the operands of a comparison. More...
 
std::pair< SDValue, SDValuemakeLibCall (SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops, unsigned NumOps, bool isSigned, SDLoc dl, bool doesNotReturn=false, bool isReturnValueUsed=true) const
 Returns a pair of (return value, chain). More...
 
bool SimplifyDemandedBits (SDValue Op, const APInt &DemandedMask, APInt &KnownZero, APInt &KnownOne, TargetLoweringOpt &TLO, unsigned Depth=0) const
 Look at Op. More...
 
virtual unsigned ComputeNumSignBitsForTargetNode (SDValue Op, const SelectionDAG &DAG, unsigned Depth=0) const
 This method can be implemented by targets that want to expose additional information about sign bits to the DAG Combiner. More...
 
bool isConstTrueVal (const SDNode *N) const
 Return if the N is a constant or constant vector equal to the true value from getBooleanContents(). More...
 
bool isConstFalseVal (const SDNode *N) const
 Return if the N is a constant or constant vector equal to the false value from getBooleanContents(). More...
 
SDValue SimplifySetCC (EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, SDLoc dl) const
 Try to simplify a setcc built with the specified operands and cc. More...
 
virtual bool isGAPlusOffset (SDNode *N, const GlobalValue *&GA, int64_t &Offset) const
 Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + offset. More...
 
virtual bool isDesirableToCommuteWithShift (const SDNode *N) const
 Return true if it is profitable to move a following shift through this. More...
 
virtual bool isTypeDesirableForOp (unsigned, EVT VT) const
 Return true if the target has native support for the specified value type and it is 'desirable' to use the type for the given node type. More...
 
virtual bool IsDesirableToPromoteOp (SDValue, EVT &) const
 This method query the target whether it is beneficial for dag combiner to promote the specified node. More...
 
std::pair< SDValue, SDValueLowerCallTo (CallLoweringInfo &CLI) const
 This function lowers an abstract call to a function into an actual call. More...
 
virtual const char * getClearCacheBuiltinName () const
 Return the builtin name for the __builtin___clear_cache intrinsic Default is to invoke the clear cache library call. More...
 
virtual EVT getTypeForExtArgOrReturn (LLVMContext &Context, EVT VT, ISD::NodeType) const
 Return the type that should be used to zero or sign extend a zeroext/signext integer argument or return value. More...
 
virtual const MCPhysReggetScratchRegisters (CallingConv::ID CC) const
 Returns a 0 terminated array of registers that can be safely used as scratch registers. More...
 
virtual SDValue prepareVolatileOrAtomicLoad (SDValue Chain, SDLoc DL, SelectionDAG &DAG) const
 This callback is used to prepare for a volatile or atomic load. More...
 
virtual void LowerOperationWrapper (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const
 This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but legal result types. More...
 
bool verifyReturnAddressArgumentIsConstant (SDValue Op, SelectionDAG &DAG) const
 
virtual AsmOperandInfoVector ParseConstraints (const DataLayout &DL, const TargetRegisterInfo *TRI, ImmutableCallSite CS) const
 Split up the constraint string from the inline assembly value into the specific constraints and their prefixes, and also tie in the associated operand values. More...
 
virtual ConstraintWeight getMultipleConstraintMatchWeight (AsmOperandInfo &info, int maIndex) const
 Examine constraint type and operand type and determine a weight value. More...
 
virtual void ComputeConstraintToUse (AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=nullptr) const
 Determines the constraint code and constraint type to use for the specific AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType. More...
 
virtual const char * LowerXConstraint (EVT ConstraintVT) const
 Try to replace an X constraint, which matches anything, with another that has more specific requirements based on the type of the corresponding operand. More...
 
SDValue BuildSDIV (SDNode *N, const APInt &Divisor, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode * > *Created) const
 Given an ISD::SDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. More...
 
SDValue BuildUDIV (SDNode *N, const APInt &Divisor, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode * > *Created) const
 Given an ISD::UDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. More...
 
virtual SDValue BuildSDIVPow2 (SDNode *N, const APInt &Divisor, SelectionDAG &DAG, std::vector< SDNode * > *Created) const
 
virtual bool combineRepeatedFPDivisors (unsigned NumUsers) const
 Indicate whether this target prefers to combine the given number of FDIVs with the same divisor. More...
 
virtual SDValue getRsqrtEstimate (SDValue Operand, DAGCombinerInfo &DCI, unsigned &RefinementSteps, bool &UseOneConstNR) const
 Hooks for building estimates in place of slower divisions and square roots. More...
 
virtual SDValue getRecipEstimate (SDValue Operand, DAGCombinerInfo &DCI, unsigned &RefinementSteps) const
 Return a reciprocal estimate value for the input operand. More...
 
bool expandMUL (SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT, SelectionDAG &DAG, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) const
 Expand a MUL into two nodes. More...
 
bool expandFP_TO_SINT (SDNode *N, SDValue &Result, SelectionDAG &DAG) const
 Expand float(f32) to SINT(i64) conversion. More...
 
- Public Member Functions inherited from llvm::TargetLoweringBase
 TargetLoweringBase (const TargetMachine &TM)
 NOTE: The TargetMachine owns TLOF. More...
 
virtual ~TargetLoweringBase ()
 
const TargetMachinegetTargetMachine () const
 
MVT getPointerTy (const DataLayout &DL, uint32_t AS=0) const
 Return the pointer type for the given address space, defaults to the pointer type from the data layout. More...
 
virtual MVT getScalarShiftAmountTy (const DataLayout &, EVT) const
 EVT is not used in-tree, but is used by out-of-tree target. More...
 
EVT getShiftAmountTy (EVT LHSTy, const DataLayout &DL) const
 
virtual MVT getVectorIdxTy (const DataLayout &DL) const
 Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR. More...
 
bool isSelectExpensive () const
 Return true if the select operation is expensive for this target. More...
 
bool hasMultipleConditionRegisters () const
 Return true if multiple condition registers are available. More...
 
bool hasExtractBitsInsn () const
 Return true if the target has BitExtract instructions. More...
 
virtual
TargetLoweringBase::LegalizeTypeAction 
getPreferredVectorAction (EVT VT) const
 Return the preferred vector type legalization action. More...
 
virtual bool shouldExpandBuildVectorWithShuffles (EVT, unsigned DefinedValues) const
 
bool isIntDivCheap () const
 Return true if integer divide is usually cheaper than a sequence of several shifts, adds, and multiplies for this target. More...
 
bool isFsqrtCheap () const
 Return true if sqrt(x) is as cheap or cheaper than 1 / rsqrt(x) More...
 
bool isSlowDivBypassed () const
 Returns true if target has indicated at least one type should be bypassed. More...
 
const DenseMap< unsigned int,
unsigned int > & 
getBypassSlowDivWidths () const
 Returns map of slow types for division or remainder with corresponding fast types. More...
 
bool isPow2SDivCheap () const
 Return true if pow2 sdiv is cheaper than a chain of sra/srl/add/sra. More...
 
bool isJumpExpensive () const
 Return true if Flow Control is an expensive operation that should be avoided. More...
 
bool isPredictableSelectExpensive () const
 Return true if selects are only cheaper than branches if the branch is unlikely to be predicted right. More...
 
virtual bool isLoadBitCastBeneficial (EVT, EVT) const
 isLoadBitCastBeneficial() - Return true if the following transform is beneficial. More...
 
virtual bool storeOfVectorConstantIsCheap (EVT MemVT, unsigned NumElem, unsigned AddrSpace) const
 Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the given size and type for the address space than to store the individual scalar element constants. More...
 
virtual bool isCheapToSpeculateCttz () const
 Return true if it is cheap to speculate a call to intrinsic cttz. More...
 
virtual bool isCheapToSpeculateCtlz () const
 Return true if it is cheap to speculate a call to intrinsic ctlz. More...
 
bool isMaskAndBranchFoldingLegal () const
 Return if the target supports combining a chain like: More...
 
bool enableExtLdPromotion () const
 Return true if the target wants to use the optimization that turns ext(promotableInst1(...(promotableInstN(load)))) into promotedInst1(...(promotedInstN(ext(load)))). More...
 
bool hasFloatingPointExceptions () const
 Return true if target supports floating point exceptions. More...
 
virtual bool enableAggressiveFMAFusion (EVT VT) const
 Return true if target always beneficiates from combining into FMA for a given value type. More...
 
virtual MVT::SimpleValueType getCmpLibcallReturnType () const
 Return the ValueType for comparison libcalls. More...
 
BooleanContent getBooleanContents (bool isVec, bool isFloat) const
 For targets without i1 registers, this gives the nature of the high-bits of boolean values held in types wider than i1. More...
 
BooleanContent getBooleanContents (EVT Type) const
 
Sched::Preference getSchedulingPreference () const
 Return target scheduling preference. More...
 
virtual const TargetRegisterClassgetRepRegClassFor (MVT VT) const
 Return the 'representative' register class for the specified value type. More...
 
virtual uint8_t getRepRegClassCostFor (MVT VT) const
 Return the cost of the 'representative' register class for the specified value type. More...
 
bool isTypeLegal (EVT VT) const
 Return true if the target has native support for the specified value type. More...
 
const ValueTypeActionImplgetValueTypeActions () const
 
LegalizeTypeAction getTypeAction (LLVMContext &Context, EVT VT) const
 Return how we should legalize values of this type, either it is already legal (return 'Legal') or we need to promote it to a larger type (return 'Promote'), or we need to expand it into multiple registers of smaller integer type (return 'Expand'). More...
 
LegalizeTypeAction getTypeAction (MVT VT) const
 
EVT getTypeToTransformTo (LLVMContext &Context, EVT VT) const
 For types supported by the target, this is an identity function. More...
 
EVT getTypeToExpandTo (LLVMContext &Context, EVT VT) const
 For types supported by the target, this is an identity function. More...
 
unsigned getVectorTypeBreakdown (LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
 Vector types are broken down into some number of legal first class types. More...
 
virtual bool canOpTrap (unsigned Op, EVT VT) const
 Returns true if the operation can trap for the value type. More...
 
virtual bool isVectorClearMaskLegal (const SmallVectorImpl< int > &, EVT) const
 Similar to isShuffleMaskLegal. More...
 
LegalizeAction getOperationAction (unsigned Op, EVT VT) const
 Return how this operation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More...
 
bool isOperationLegalOrCustom (unsigned Op, EVT VT) const
 Return true if the specified operation is legal on this target or can be made legal with custom lowering. More...
 
bool isOperationLegalOrPromote (unsigned Op, EVT VT) const
 Return true if the specified operation is legal on this target or can be made legal using promotion. More...
 
bool isOperationExpand (unsigned Op, EVT VT) const
 Return true if the specified operation is illegal on this target or unlikely to be made legal with custom lowering. More...
 
bool isOperationLegal (unsigned Op, EVT VT) const
 Return true if the specified operation is legal on this target. More...
 
LegalizeAction getLoadExtAction (unsigned ExtType, EVT ValVT, EVT MemVT) const
 Return how this load with extension should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More...
 
bool isLoadExtLegal (unsigned ExtType, EVT ValVT, EVT MemVT) const
 Return true if the specified load with extension is legal on this target. More...
 
bool isLoadExtLegalOrCustom (unsigned ExtType, EVT ValVT, EVT MemVT) const
 Return true if the specified load with extension is legal or custom on this target. More...
 
LegalizeAction getTruncStoreAction (EVT ValVT, EVT MemVT) const
 Return how this store with truncation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More...
 
bool isTruncStoreLegal (EVT ValVT, EVT MemVT) const
 Return true if the specified store with truncation is legal on this target. More...
 
LegalizeAction getIndexedLoadAction (unsigned IdxMode, MVT VT) const
 Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More...
 
bool isIndexedLoadLegal (unsigned IdxMode, EVT VT) const
 Return true if the specified indexed load is legal on this target. More...
 
LegalizeAction getIndexedStoreAction (unsigned IdxMode, MVT VT) const
 Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More...
 
bool isIndexedStoreLegal (unsigned IdxMode, EVT VT) const
 Return true if the specified indexed load is legal on this target. More...
 
LegalizeAction getCondCodeAction (ISD::CondCode CC, MVT VT) const
 Return how the condition code should be treated: either it is legal, needs to be expanded to some other code sequence, or the target has a custom expander for it. More...
 
bool isCondCodeLegal (ISD::CondCode CC, MVT VT) const
 Return true if the specified condition code is legal on this target. More...
 
MVT getTypeToPromoteTo (unsigned Op, MVT VT) const
 If the action for this operation is to promote, this method returns the ValueType to promote to. More...
 
EVT getValueType (const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
 Return the EVT corresponding to this LLVM type. More...
 
MVT getSimpleValueType (const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
 Return the MVT corresponding to this LLVM type. See getValueType. More...
 
virtual unsigned getByValTypeAlignment (Type *Ty, const DataLayout &DL) const
 Return the desired alignment for ByVal or InAlloca aggregate function arguments in the caller parameter area. More...
 
MVT getRegisterType (MVT VT) const
 Return the type of registers that this ValueType will eventually require. More...
 
MVT getRegisterType (LLVMContext &Context, EVT VT) const
 Return the type of registers that this ValueType will eventually require. More...
 
unsigned getNumRegisters (LLVMContext &Context, EVT VT) const
 Return the number of registers that this ValueType will eventually require. More...
 
virtual bool ShouldShrinkFPConstant (EVT) const
 If true, then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime. More...
 
virtual bool shouldReduceLoadWidth (SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const
 
bool hasBigEndianPartOrdering (EVT VT, const DataLayout &DL) const
 When splitting a value of the specified type into parts, does the Lo or Hi part come first? This usually follows the endianness, except for ppcf128, where the Hi part always comes first. More...
 
bool hasTargetDAGCombine (ISD::NodeType NT) const
 If true, the target has custom DAG combine transformations that it can perform for the specified node. More...
 
unsigned getMaxStoresPerMemset (bool OptSize) const
 Get maximum # of store operations permitted for llvm.memset. More...
 
unsigned getMaxStoresPerMemcpy (bool OptSize) const
 Get maximum # of store operations permitted for llvm.memcpy. More...
 
unsigned getMaxStoresPerMemmove (bool OptSize) const
 Get maximum # of store operations permitted for llvm.memmove. More...
 
virtual bool isSafeMemOpType (MVT) const
 Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline. More...
 
bool usesUnderscoreSetJmp () const
 Determine if we should use _setjmp or setjmp to implement llvm.setjmp. More...
 
bool usesUnderscoreLongJmp () const
 Determine if we should use _longjmp or longjmp to implement llvm.longjmp. More...
 
int getMinimumJumpTableEntries () const
 Return integer threshold on number of blocks to use jump tables rather than if sequence. More...
 
unsigned getStackPointerRegisterToSaveRestore () const
 If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore. More...
 
unsigned getExceptionPointerRegister () const
 If a physical register, this returns the register that receives the exception address on entry to a landing pad. More...
 
unsigned getExceptionSelectorRegister () const
 If a physical register, this returns the register that receives the exception typeid on entry to a landing pad. More...
 
unsigned getJumpBufSize () const
 Returns the target's jmp_buf size in bytes (if never set, the default is 200) More...
 
unsigned getJumpBufAlignment () const
 Returns the target's jmp_buf alignment in bytes (if never set, the default is 0) More...
 
unsigned getMinStackArgumentAlignment () const
 Return the minimum stack alignment of an argument. More...
 
unsigned getMinFunctionAlignment () const
 Return the minimum function alignment. More...
 
unsigned getPrefFunctionAlignment () const
 Return the preferred function alignment. More...
 
virtual unsigned getPrefLoopAlignment (MachineLoop *ML=nullptr) const
 Return the preferred loop alignment. More...
 
bool getInsertFencesForAtomic () const
 Return whether the DAG builder should automatically insert fences and reduce ordering for atomics. More...
 
virtual bool getStackCookieLocation (unsigned &, unsigned &) const
 Return true if the target stores stack protector cookies at a fixed offset in some non-standard address space, and populates the address space and offset as appropriate. More...
 
virtual bool shouldSignExtendTypeInLibCall (EVT Type, bool IsSigned) const
 Returns true if arguments should be sign-extended in lib calls. More...
 
virtual LoadInstlowerIdempotentRMWIntoFencedLoad (AtomicRMWInst *RMWI) const
 On some platforms, an AtomicRMW that never actually modifies the value (such as fetch_add of 0) can be turned into a fence followed by an atomic load. More...
 
virtual bool shouldNormalizeToSelectSequence (LLVMContext &Context, EVT VT) const
 Returns true if we should normalize select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely that it saves us from materializing N0 and N1 in an integer register. More...
 
virtual bool GetAddrModeArguments (IntrinsicInst *, SmallVectorImpl< Value * > &, Type *&, unsigned AddrSpace=0) const
 CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the address. More...
 
virtual int getScalingFactorCost (const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS=0) const
 Return the cost of the scaling factor used in the addressing mode represented by AM for this target, for a load/store of the specified type. More...
 
virtual bool isVectorShiftByScalarCheap (Type *Ty) const
 Return true if it's significantly cheaper to shift a vector by a uniform scalar than by an amount which will vary across each lane. More...
 
virtual bool isTruncateFree (Type *, Type *) const
 Return true if it's free to truncate a value of type Ty1 to type Ty2. More...
 
virtual bool isTruncateFree (EVT, EVT) const
 
virtual bool isProfitableToHoist (Instruction *I) const
 
bool isExtFree (const Instruction *I) const
 Return true if the extension represented by I is free. More...
 
virtual bool isZExtFree (Type *, Type *) const
 Return true if any actual instruction that defines a value of type Ty1 implicitly zero-extends the value to Ty2 in the result register. More...
 
virtual bool isZExtFree (EVT, EVT) const
 
virtual bool hasPairedLoad (Type *, unsigned &) const
 Return true if the target supplies and combines to a paired load two loaded values of type LoadedType next to each other in memory. More...
 
virtual bool hasPairedLoad (EVT, unsigned &) const
 
virtual bool isFPExtFree (EVT VT) const
 Return true if an fpext operation is free (for instance, because single-precision floating-point numbers are implicitly extended to double-precision). More...
 
virtual bool isFNegFree (EVT VT) const
 Return true if an fneg operation is free to the point where it is never worthwhile to replace it with a bitwise operation. More...
 
virtual bool isFAbsFree (EVT VT) const
 Return true if an fabs operation is free to the point where it is never worthwhile to replace it with a bitwise operation. More...
 
virtual bool isNarrowingProfitable (EVT, EVT) const
 Return true if it's profitable to narrow operations of type VT1 to VT2. More...
 
virtual bool isExtractSubvectorCheap (EVT ResVT, unsigned Index) const
 Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index. More...
 
void setLibcallName (RTLIB::Libcall Call, const char *Name)
 Rename the default libcall routine name for the specified libcall. More...
 
const char * getLibcallName (RTLIB::Libcall Call) const
 Get the libcall routine name for the specified libcall. More...
 
void setCmpLibcallCC (RTLIB::Libcall Call, ISD::CondCode CC)
 Override the default CondCode to be used to test the result of the comparison libcall against zero. More...
 
ISD::CondCode getCmpLibcallCC (RTLIB::Libcall Call) const
 Get the CondCode that's to be used to test the result of the comparison libcall against zero. More...
 
void setLibcallCallingConv (RTLIB::Libcall Call, CallingConv::ID CC)
 Set the CallingConv that should be used for the specified libcall. More...
 
CallingConv::ID getLibcallCallingConv (RTLIB::Libcall Call) const
 Get the CallingConv that should be used for the specified libcall. More...
 
int InstructionOpcodeToISD (unsigned Opcode) const
 Get the ISD node that corresponds to the Instruction class opcode. More...
 
std::pair< unsigned, MVTgetTypeLegalizationCost (const DataLayout &DL, Type *Ty) const
 Estimate the cost of type-legalization and the legalized type. More...
 

Protected Member Functions

std::pair< const
TargetRegisterClass *, uint8_t > 
findRepresentativeClass (const TargetRegisterInfo *TRI, MVT VT) const override
 Return the largest legal super-reg register class of the register class for the specified type and its associated "cost". More...
 
- Protected Member Functions inherited from llvm::TargetLoweringBase
void initActions ()
 Initialize all of the actions to default values. More...
 
void setBooleanContents (BooleanContent Ty)
 Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type. More...
 
void setBooleanContents (BooleanContent IntTy, BooleanContent FloatTy)
 Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type. More...
 
void setBooleanVectorContents (BooleanContent Ty)
 Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider type. More...
 
void setSchedulingPreference (Sched::Preference Pref)
 Specify the target scheduling preference. More...
 
void setUseUnderscoreSetJmp (bool Val)
 Indicate whether this target prefers to use _setjmp to implement llvm.setjmp or the version without _. More...
 
void setUseUnderscoreLongJmp (bool Val)
 Indicate whether this target prefers to use _longjmp to implement llvm.longjmp or the version without _. More...
 
void setMinimumJumpTableEntries (int Val)
 Indicate the number of blocks to generate jump tables rather than if sequence. More...
 
void setStackPointerRegisterToSaveRestore (unsigned R)
 If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore. More...
 
void setExceptionPointerRegister (unsigned R)
 If set to a physical register, this sets the register that receives the exception address on entry to a landing pad. More...
 
void setExceptionSelectorRegister (unsigned R)
 If set to a physical register, this sets the register that receives the exception typeid on entry to a landing pad. More...
 
void setSelectIsExpensive (bool isExpensive=true)
 Tells the code generator not to expand operations into sequences that use the select operations if possible. More...
 
void setHasMultipleConditionRegisters (bool hasManyRegs=true)
 Tells the code generator that the target has multiple (allocatable) condition registers that can be used to store the results of comparisons for use by selects and conditional branches. More...
 
void setHasExtractBitsInsn (bool hasExtractInsn=true)
 Tells the code generator that the target has BitExtract instructions. More...
 
void setJumpIsExpensive (bool isExpensive=true)
 Tells the code generator not to expand logic operations on comparison predicates into separate sequences that increase the amount of flow control. More...
 
void setIntDivIsCheap (bool isCheap=true)
 Tells the code generator that integer divide is expensive, and if possible, should be replaced by an alternate sequence of instructions not containing an integer divide. More...
 
void setFsqrtIsCheap (bool isCheap=true)
 Tells the code generator that fsqrt is cheap, and should not be replaced with an alternative sequence of instructions. More...
 
void setHasFloatingPointExceptions (bool FPExceptions=true)
 Tells the code generator that this target supports floating point exceptions and cares about preserving floating point exception behavior. More...
 
void addBypassSlowDiv (unsigned int SlowBitWidth, unsigned int FastBitWidth)
 Tells the code generator which bitwidths to bypass. More...
 
void setPow2SDivIsCheap (bool isCheap=true)
 Tells the code generator that it shouldn't generate sra/srl/add/sra for a signed divide by power of two; let the target handle it. More...
 
void addRegisterClass (MVT VT, const TargetRegisterClass *RC)
 Add the specified register class as an available regclass for the specified value type. More...
 
void clearRegisterClasses ()
 Remove all register classes. More...
 
void clearOperationActions ()
 Remove all operation actions. More...
 
void computeRegisterProperties (const TargetRegisterInfo *TRI)
 Once all of the register classes are added, this allows us to compute derived properties we expose. More...
 
void setOperationAction (unsigned Op, MVT VT, LegalizeAction Action)
 Indicate that the specified operation does not work with the specified type and indicate what to do about it. More...
 
void setLoadExtAction (unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
 Indicate that the specified load with extension does not work with the specified type and indicate what to do about it. More...
 
void setTruncStoreAction (MVT ValVT, MVT MemVT, LegalizeAction Action)
 Indicate that the specified truncating store does not work with the specified type and indicate what to do about it. More...
 
void setIndexedLoadAction (unsigned IdxMode, MVT VT, LegalizeAction Action)
 Indicate that the specified indexed load does or does not work with the specified type and indicate what to do abort it. More...
 
void setIndexedStoreAction (unsigned IdxMode, MVT VT, LegalizeAction Action)
 Indicate that the specified indexed store does or does not work with the specified type and indicate what to do about it. More...
 
void setCondCodeAction (ISD::CondCode CC, MVT VT, LegalizeAction Action)
 Indicate that the specified condition code is or isn't supported on the target and indicate what to do about it. More...
 
void AddPromotedToType (unsigned Opc, MVT OrigVT, MVT DestVT)
 If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/fp until it can find one that works. More...
 
void setTargetDAGCombine (ISD::NodeType NT)
 Targets should invoke this method for each target independent node that they want to provide a custom DAG combiner for by implementing the PerformDAGCombine virtual method. More...
 
void setJumpBufSize (unsigned Size)
 Set the target's required jmp_buf buffer size (in bytes); default is 200. More...
 
void setJumpBufAlignment (unsigned Align)
 Set the target's required jmp_buf buffer alignment (in bytes); default is 0. More...
 
void setMinFunctionAlignment (unsigned Align)
 Set the target's minimum function alignment (in log2(bytes)) More...
 
void setPrefFunctionAlignment (unsigned Align)
 Set the target's preferred function alignment. More...
 
void setPrefLoopAlignment (unsigned Align)
 Set the target's preferred loop alignment. More...
 
void setMinStackArgumentAlignment (unsigned Align)
 Set the minimum stack alignment of an argument (in log2(bytes)). More...
 
void setInsertFencesForAtomic (bool fence)
 Set if the DAG builder should automatically insert fences and reduce the order of atomic memory operations to Monotonic. More...
 
virtual bool isExtFreeImpl (const Instruction *I) const
 Return true if the extension represented by I is free. More...
 
bool isLegalRC (const TargetRegisterClass *RC) const
 Return true if the value types that can be represented by the specified register class are all legal. More...
 
MachineBasicBlockemitPatchPoint (MachineInstr *MI, MachineBasicBlock *MBB) const
 Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that is recognized by PrologEpilogInserter. More...
 

Additional Inherited Members

- Public Types inherited from llvm::TargetLowering
enum  ConstraintType {
  C_Register, C_RegisterClass, C_Memory, C_Other,
  C_Unknown
}
 
enum  ConstraintWeight {
  CW_Invalid = -1, CW_Okay = 0, CW_Good = 1, CW_Better = 2,
  CW_Best = 3, CW_SpecificReg = CW_Okay, CW_Register = CW_Good, CW_Memory = CW_Better,
  CW_Constant = CW_Best, CW_Default = CW_Okay
}
 
typedef std::vector< ArgListEntryArgListTy
 
typedef std::vector
< AsmOperandInfo
AsmOperandInfoVector
 
- Public Types inherited from llvm::TargetLoweringBase
enum  LegalizeAction { Legal, Promote, Expand, Custom }
 This enum indicates whether operations are valid for a target, and if not, what action should be used to make them valid. More...
 
enum  LegalizeTypeAction {
  TypeLegal, TypePromoteInteger, TypeExpandInteger, TypeSoftenFloat,
  TypeExpandFloat, TypeScalarizeVector, TypeSplitVector, TypeWidenVector,
  TypePromoteFloat
}
 This enum indicates whether a types are legal for a target, and if not, what action should be used to make them valid. More...
 
enum  BooleanContent { UndefinedBooleanContent, ZeroOrOneBooleanContent, ZeroOrNegativeOneBooleanContent }
 Enum that describes how the target represents true/false values. More...
 
enum  SelectSupportKind { ScalarValSelect, ScalarCondVectorVal, VectorMaskSelect }
 Enum that describes what type of support for selects the target has. More...
 
enum  AtomicRMWExpansionKind { AtomicRMWExpansionKind::None, AtomicRMWExpansionKind::LLSC, AtomicRMWExpansionKind::CmpXChg }
 Enum that specifies what a AtomicRMWInst is expanded to, if at all. More...
 
typedef std::pair
< LegalizeTypeAction, EVT
LegalizeKind
 LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it. More...
 
- Static Public Member Functions inherited from llvm::TargetLoweringBase
static ISD::NodeType getExtendForContent (BooleanContent Content)
 
- Protected Attributes inherited from llvm::TargetLoweringBase
unsigned MaxStoresPerMemset
 Specify maximum number of store instructions per memset call. More...
 
unsigned MaxStoresPerMemsetOptSize
 Maximum number of stores operations that may be substituted for the call to memset, used for functions with OptSize attribute. More...
 
unsigned MaxStoresPerMemcpy
 Specify maximum bytes of store instructions per memcpy call. More...
 
unsigned MaxStoresPerMemcpyOptSize
 Maximum number of store operations that may be substituted for a call to memcpy, used for functions with OptSize attribute. More...
 
unsigned MaxStoresPerMemmove
 Specify maximum bytes of store instructions per memmove call. More...
 
unsigned MaxStoresPerMemmoveOptSize
 Maximum number of store instructions that may be substituted for a call to memmove, used for functions with OpSize attribute. More...
 
bool PredictableSelectIsExpensive
 Tells the code generator that select is more expensive than a branch if the branch is usually predicted right. More...
 
bool MaskAndBranchFoldingIsLegal
 MaskAndBranchFoldingIsLegal - Indicates if the target supports folding a mask of a single bit, a compare, and a branch into a single instruction. More...
 
bool EnableExtLdPromotion
 

Detailed Description

Definition at line 228 of file ARMISelLowering.h.

Constructor & Destructor Documentation

ARMTargetLowering::ARMTargetLowering ( const TargetMachine TM,
const ARMSubtarget STI 
)
explicit

Definition at line 157 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::RTLIB::ADD_F32, llvm::RTLIB::ADD_F64, llvm::ISD::ADDC, llvm::ISD::ADDE, llvm::TargetLoweringBase::addRegisterClass(), llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::CallingConv::ARM_AAPCS, llvm::CallingConv::ARM_AAPCS_VFP, llvm::CallingConv::ARM_APCS, llvm::ISD::ATOMIC_CMP_SWAP, llvm::ISD::ATOMIC_FENCE, llvm::ISD::ATOMIC_LOAD, llvm::ISD::ATOMIC_LOAD_ADD, llvm::ISD::ATOMIC_LOAD_AND, llvm::ISD::ATOMIC_LOAD_MAX, llvm::ISD::ATOMIC_LOAD_MIN, llvm::ISD::ATOMIC_LOAD_NAND, llvm::ISD::ATOMIC_LOAD_OR, llvm::ISD::ATOMIC_LOAD_SUB, llvm::ISD::ATOMIC_LOAD_UMAX, llvm::ISD::ATOMIC_LOAD_UMIN, llvm::ISD::ATOMIC_LOAD_XOR, llvm::ISD::ATOMIC_STORE, llvm::ISD::ATOMIC_SWAP, llvm::ISD::BITCAST, llvm::ISD::BlockAddress, llvm::ISD::BR_CC, llvm::ISD::BR_JT, llvm::ISD::BRCOND, llvm::ISD::BSWAP, llvm::ISD::BUILD_VECTOR, llvm::TargetLoweringBase::computeRegisterProperties(), llvm::ISD::ConstantFP, llvm::ISD::ConstantPool, llvm::ISD::CTLZ, llvm::ISD::CTLZ_ZERO_UNDEF, llvm::ISD::CTPOP, llvm::ISD::CTTZ, llvm::ISD::CTTZ_ZERO_UNDEF, llvm::TargetLoweringBase::Custom, llvm::RTLIB::DIV_F32, llvm::RTLIB::DIV_F64, llvm::ISD::DYNAMIC_STACKALLOC, llvm::ISD::EH_SJLJ_LONGJMP, llvm::ISD::EH_SJLJ_SETJMP, llvm::TargetLoweringBase::Expand, llvm::ISD::EXTLOAD, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::ISD::FABS, llvm::ISD::FADD, llvm::ISD::FCEIL, llvm::ISD::FCOPYSIGN, llvm::ISD::FCOS, llvm::ISD::FDIV, llvm::ISD::FEXP, llvm::ISD::FEXP2, llvm::ISD::FFLOOR, llvm::ISD::FGETSIGN, llvm::ISD::FLOG, llvm::ISD::FLOG10, llvm::ISD::FLOG2, llvm::ISD::FLT_ROUNDS_, llvm::ISD::FMA, llvm::ISD::FMUL, llvm::ISD::FNEARBYINT, llvm::ISD::FNEG, llvm::ISD::FP16_TO_FP, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::ISD::FP_TO_FP16, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::MVT::fp_valuetypes(), llvm::RTLIB::FPEXT_F16_F32, llvm::RTLIB::FPEXT_F32_F64, llvm::ISD::FPOW, llvm::ISD::FPOWI, llvm::RTLIB::FPROUND_F32_F16, llvm::RTLIB::FPROUND_F64_F16, llvm::RTLIB::FPROUND_F64_F32, llvm::RTLIB::FPTOSINT_F32_I32, llvm::RTLIB::FPTOSINT_F32_I64, llvm::RTLIB::FPTOSINT_F64_I32, llvm::RTLIB::FPTOSINT_F64_I64, llvm::RTLIB::FPTOUINT_F32_I32, llvm::RTLIB::FPTOUINT_F32_I64, llvm::RTLIB::FPTOUINT_F64_I32, llvm::RTLIB::FPTOUINT_F64_I64, llvm::ISD::FREM, llvm::ISD::FRINT, llvm::ISD::FROUND, llvm::ISD::FSIN, llvm::ISD::FSINCOS, llvm::ISD::FSQRT, llvm::ISD::FSUB, llvm::ISD::FTRUNC, llvm::ARMSubtarget::getInstrItineraryData(), llvm::ARMSubtarget::getRegisterInfo(), llvm::ARMSubtarget::getTargetTriple(), llvm::ISD::GLOBAL_OFFSET_TABLE, llvm::ISD::GlobalAddress, llvm::ISD::GlobalTLSAddress, llvm::ARMSubtarget::hasAnyDataBarrier(), llvm::ARMSubtarget::hasARMOps(), llvm::ARMSubtarget::hasDivide(), llvm::ARMSubtarget::hasDivideInARMMode(), llvm::ARMSubtarget::hasFP16(), llvm::ARMSubtarget::hasFPARMv8(), llvm::ARMSubtarget::hasNEON(), llvm::ARMSubtarget::hasSinCos(), llvm::ARMSubtarget::hasThumb2DSP(), llvm::ARMSubtarget::hasV5TOps(), llvm::ARMSubtarget::hasV6Ops(), llvm::ARMSubtarget::hasV8Ops(), llvm::ARMSubtarget::hasVFP2(), llvm::ARMSubtarget::hasVFP4(), llvm::Sched::Hybrid, llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, im, llvm::ISD::INSERT_VECTOR_ELT, llvm::MVT::integer_valuetypes(), llvm::MVT::integer_vector_valuetypes(), llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::ARMSubtarget::isAAPCS_ABI(), llvm::ARMSubtarget::isFPOnlySP(), llvm::Triple::isiOS(), llvm::ARMSubtarget::isLikeA9(), llvm::Triple::isOSVersionLT(), llvm::ARMSubtarget::isTargetAEABI(), llvm::ARMSubtarget::isTargetDarwin(), llvm::ARMSubtarget::isTargetMachO(), llvm::ARMSubtarget::isTargetWindows(), llvm::ARMSubtarget::isThumb(), llvm::ARMSubtarget::isThumb1Only(), llvm::ARMSubtarget::isThumb2(), llvm::Triple::isWindowsItaniumEnvironment(), llvm::ISD::LAST_INDEXED_MODE, llvm::TargetLoweringBase::Legal, llvm::ISD::LOAD, llvm::TargetLoweringBase::MaxStoresPerMemcpy, llvm::TargetLoweringBase::MaxStoresPerMemcpyOptSize, llvm::TargetLoweringBase::MaxStoresPerMemmove, llvm::TargetLoweringBase::MaxStoresPerMemmoveOptSize, llvm::TargetLoweringBase::MaxStoresPerMemset, llvm::TargetLoweringBase::MaxStoresPerMemsetOptSize, llvm::RTLIB::MEMCPY, llvm::RTLIB::MEMMOVE, llvm::RTLIB::MEMSET, llvm::ISD::MUL, llvm::RTLIB::MUL_F32, llvm::RTLIB::MUL_F64, llvm::RTLIB::MUL_I64, llvm::ISD::MULHS, llvm::ISD::MULHU, llvm::RTLIB::O_F32, llvm::RTLIB::O_F64, llvm::RTLIB::OEQ_F32, llvm::RTLIB::OEQ_F64, llvm::RTLIB::OGE_F32, llvm::RTLIB::OGE_F64, llvm::RTLIB::OGT_F32, llvm::RTLIB::OGT_F64, llvm::RTLIB::OLE_F32, llvm::RTLIB::OLE_F64, llvm::RTLIB::OLT_F32, llvm::RTLIB::OLT_F64, llvm::TargetMachine::Options, llvm::ISD::OR, llvm::MVT::Other, llvm::ISD::PRE_INC, llvm::TargetLoweringBase::PredictableSelectIsExpensive, llvm::ISD::PREFETCH, llvm::TargetLoweringBase::Promote, llvm::ISD::READ_REGISTER, llvm::ISD::READCYCLECOUNTER, llvm::Sched::RegPressure, llvm::ISD::ROTL, llvm::ISD::SADDO, llvm::ISD::SDIV, llvm::RTLIB::SDIV_I16, llvm::RTLIB::SDIV_I32, llvm::RTLIB::SDIV_I64, llvm::RTLIB::SDIV_I8, llvm::ISD::SDIVREM, llvm::RTLIB::SDIVREM_I16, llvm::RTLIB::SDIVREM_I32, llvm::RTLIB::SDIVREM_I64, llvm::RTLIB::SDIVREM_I8, llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::TargetLoweringBase::setBooleanVectorContents(), llvm::ISD::SETCC, llvm::ISD::SETCC_INVALID, llvm::TargetLoweringBase::setCmpLibcallCC(), llvm::ISD::SETEQ, llvm::TargetLoweringBase::setExceptionPointerRegister(), llvm::TargetLoweringBase::setExceptionSelectorRegister(), llvm::TargetLoweringBase::setIndexedLoadAction(), llvm::TargetLoweringBase::setIndexedStoreAction(), llvm::TargetLoweringBase::setInsertFencesForAtomic(), llvm::TargetLoweringBase::setLibcallCallingConv(), llvm::TargetLoweringBase::setLibcallName(), llvm::TargetLoweringBase::setLoadExtAction(), llvm::TargetLoweringBase::setMinFunctionAlignment(), llvm::TargetLoweringBase::setMinStackArgumentAlignment(), llvm::ISD::SETNE, llvm::TargetLoweringBase::setOperationAction(), llvm::TargetLoweringBase::setSchedulingPreference(), llvm::TargetLoweringBase::setStackPointerRegisterToSaveRestore(), llvm::TargetLoweringBase::setTargetDAGCombine(), llvm::TargetLoweringBase::setTruncStoreAction(), llvm::ISD::SEXTLOAD, llvm::ISD::SHL, llvm::RTLIB::SHL_I128, llvm::RTLIB::SHL_I64, llvm::ISD::SHL_PARTS, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::RTLIB::SINCOS_F32, llvm::RTLIB::SINCOS_F64, llvm::ThreadModel::Single, llvm::ISD::SINT_TO_FP, llvm::RTLIB::SINTTOFP_I32_F32, llvm::RTLIB::SINTTOFP_I32_F64, llvm::RTLIB::SINTTOFP_I64_F32, llvm::RTLIB::SINTTOFP_I64_F64, llvm::ISD::SMUL_LOHI, llvm::ISD::SRA, llvm::RTLIB::SRA_I128, llvm::RTLIB::SRA_I64, llvm::ISD::SRA_PARTS, llvm::ISD::SREM, llvm::ISD::SRL, llvm::RTLIB::SRL_I128, llvm::RTLIB::SRL_I64, llvm::ISD::SRL_PARTS, llvm::ISD::SSUBO, llvm::ISD::STACKRESTORE, llvm::ISD::STACKSAVE, llvm::ISD::STORE, llvm::ISD::SUB, llvm::RTLIB::SUB_F32, llvm::RTLIB::SUB_F64, llvm::ISD::SUBC, llvm::ISD::SUBE, llvm::TargetOptions::ThreadModel, llvm::ISD::TRAP, llvm::ISD::UADDO, llvm::ISD::UDIV, llvm::RTLIB::UDIV_I16, llvm::RTLIB::UDIV_I32, llvm::RTLIB::UDIV_I64, llvm::RTLIB::UDIV_I8, llvm::ISD::UDIVREM, llvm::RTLIB::UDIVREM_I16, llvm::RTLIB::UDIVREM_I32, llvm::RTLIB::UDIVREM_I64, llvm::RTLIB::UDIVREM_I8, llvm::ISD::UINT_TO_FP, llvm::RTLIB::UINTTOFP_I32_F32, llvm::RTLIB::UINTTOFP_I32_F64, llvm::RTLIB::UINTTOFP_I64_F32, llvm::RTLIB::UINTTOFP_I64_F64, llvm::ISD::UMUL_LOHI, llvm::RTLIB::UNE_F32, llvm::RTLIB::UNE_F64, llvm::RTLIB::UNWIND_RESUME, llvm::RTLIB::UO_F32, llvm::RTLIB::UO_F64, llvm::ISD::UREM, llvm::ARMSubtarget::useSoftFloat(), llvm::ISD::USUBO, llvm::MVT::v16i8, llvm::MVT::v1i64, llvm::MVT::v2f32, llvm::MVT::v2f64, llvm::MVT::v2i16, llvm::MVT::v2i32, llvm::MVT::v2i64, llvm::MVT::v2i8, llvm::MVT::v4f32, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v4i8, llvm::MVT::v8i16, llvm::MVT::v8i8, llvm::ISD::VAARG, llvm::ISD::VACOPY, llvm::ISD::VAEND, llvm::ISD::VASTART, llvm::ISD::VECTOR_SHUFFLE, llvm::MVT::vector_valuetypes(), llvm::ISD::WRITE_REGISTER, llvm::ISD::XOR, llvm::ISD::ZERO_EXTEND, llvm::TargetLoweringBase::ZeroOrNegativeOneBooleanContent, and llvm::ISD::ZEXTLOAD.

Member Function Documentation

void ARMTargetLowering::AdjustInstrPostInstrSelection ( MachineInstr MI,
SDNode Node 
) const
overridevirtual
bool ARMTargetLowering::allowsMisalignedMemoryAccesses ( EVT  VT,
unsigned  AddrSpace,
unsigned  Align,
bool Fast 
) const
overridevirtual

allowsMisalignedMemoryAccesses - Returns true if the target allows unaligned memory accesses of the specified type.

Returns whether it is "fast" by reference in the second argument.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 10159 of file ARMISelLowering.cpp.

References llvm::ARMSubtarget::allowsUnalignedMem(), llvm::MVT::f64, llvm::EVT::getSimpleVT(), llvm::ARMSubtarget::hasNEON(), llvm::ARMSubtarget::hasV7Ops(), llvm::MVT::i16, llvm::MVT::i8, llvm::ARMSubtarget::isLittle(), llvm::MVT::SimpleTy, and llvm::MVT::v2f64.

Referenced by getOptimalMemOpType().

bool ARMTargetLowering::allowTruncateForTailCall ( Type ,
Type  
) const
overridevirtual

Return true if a truncation from Ty1 to Ty2 is permitted when deciding whether a call is in tail position.

Typically this means that both results would be assigned to the same register or stack slot, but it could mean the target performs adequate checks of its own before proceeding with the tail call.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 10277 of file ARMISelLowering.cpp.

References llvm::EVT::getEVT(), llvm::Type::getPrimitiveSizeInBits(), llvm::Type::isIntegerTy(), and llvm::TargetLoweringBase::isTypeLegal().

bool ARMTargetLowering::canCombineStoreAndExtract ( Type VectorTy,
Value Idx,
unsigned Cost 
) const
overridevirtual

Return true if the target can combine store(extractelement VectorTy, Idx).

Cost[out] gives the cost of that transformation when this is true.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 11415 of file ARMISelLowering.cpp.

References getBitWidth(), llvm::ARMSubtarget::hasNEON(), llvm::Type::isFPOrFPVectorTy(), and llvm::Type::isVectorTy().

void ARMTargetLowering::computeKnownBitsForTargetNode ( const SDValue  Op,
APInt KnownZero,
APInt KnownOne,
const SelectionDAG DAG,
unsigned  Depth 
) const
overridevirtual

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets.

computeKnownBitsForTargetNode - Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets.

Reimplemented from llvm::TargetLowering.

Definition at line 10687 of file ARMISelLowering.cpp.

References llvm::ARMISD::ADDC, llvm::ARMISD::ADDE, llvm::ARMISD::CMOV, llvm::SelectionDAG::computeKnownBits(), llvm::APInt::getBitWidth(), llvm::APInt::getHighBitsSet(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getResNo(), llvm::EVT::getScalarType(), llvm::EVT::getSizeInBits(), llvm::ConstantSDNode::getZExtValue(), llvm::ISD::INTRINSIC_W_CHAIN, llvm::ARMISD::SUBC, and llvm::ARMISD::SUBE.

FastISel * ARMTargetLowering::createFastISel ( FunctionLoweringInfo funcInfo,
const TargetLibraryInfo libInfo 
) const
overridevirtual

createFastISel - This method returns a target specific FastISel object, or null if the target does not support "fast" ISel.

Reimplemented from llvm::TargetLowering.

Definition at line 1206 of file ARMISelLowering.cpp.

References llvm::ARM::createFastISel().

MachineBasicBlock * ARMTargetLowering::EmitInstrWithCustomInserter ( MachineInstr MI,
MachineBasicBlock MBB 
) const
overridevirtual

This method should be implemented by targets that mark instructions with the 'usesCustomInserter' flag.

These instructions are special in various ways, which require special support to insert. The specified MachineInstr is created but not inserted into any basic blocks, and this method is called to expand it into a sequence of instructions, potentially also creating new basic blocks and control flow. As long as the returned basic block is different (i.e., we created a new one), the custom inserter is free to modify the rest of MBB.

Reimplemented from llvm::TargetLowering.

Definition at line 7577 of file ARMISelLowering.cpp.

References SISrcMods::ABS, llvm::AddDefaultPred(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addOperand(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::ARMCC::AL, llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MachineFunction::CreateMachineBasicBlock(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::ARMCC::EQ, llvm::MachineInstr::eraseFromParent(), llvm::MCInstrInfo::get(), llvm::ARM_AM::getAM2Offset(), llvm::ARM_AM::getAM2Op(), llvm::ARMSubtarget::getInstrInfo(), llvm::SDNode::getOperand(), llvm::ARMCC::getOppositeCondition(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::insert(), llvm::ARMSubtarget::isThumb2(), llvm::RegState::Kill, llvm_unreachable, llvm::ARMCC::MI, llvm::ARMCC::NE, OtherSucc(), llvm::TargetOpcode::PHI, llvm::MachineBasicBlock::splice(), llvm::ARM_AM::sub, std::swap(), llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs(), and llvm::ARMISD::WIN__CHKSTK.

Instruction * ARMTargetLowering::emitLeadingFence ( IRBuilder<> &  Builder,
AtomicOrdering  Ord,
bool  IsStore,
bool  IsLoad 
) const
overridevirtual

Inserts in the IR a target-specific intrinsic specifying a fence.

It is called by AtomicExpandPass before expanding an AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad. RMW and CmpXchg set both IsStore and IsLoad to true. This function should either return a nullptr, or a pointer to an IR-level Instruction*. Even complex fence sequences can be represented by a single Instruction* through an intrinsic to be lowered later. Backends with !getInsertFencesForAtomic() should keep a no-op here. Backends should override this method to produce target-specific intrinsic for their fences. FIXME: Please note that the default implementation here in terms of IR-level fences exists for historical/compatibility reasons and is unsound ! Fences cannot, in general, be used to restore sequential consistency. For example, consider the following example: atomic<int> x = y = 0; int r1, r2, r3, r4; Thread 0: x.store(1); Thread 1: y.store(1); Thread 2: r1 = x.load(); r2 = y.load(); Thread 3: r3 = y.load(); r4 = x.load(); r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all seq_cst. But if they are lowered to monotonic accesses, no amount of IR-level fences can prevent it.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 11330 of file ARMISelLowering.cpp.

References llvm::Acquire, llvm::AcquireRelease, llvm::TargetLoweringBase::getInsertFencesForAtomic(), llvm::ARM_MB::ISH, llvm::ARM_MB::ISHST, llvm::ARMSubtarget::isSwift(), llvm_unreachable, makeDMB(), llvm::Monotonic, llvm::NotAtomic, llvm::Release, llvm::SequentiallyConsistent, and llvm::Unordered.

Value * ARMTargetLowering::emitLoadLinked ( IRBuilder<> &  Builder,
Value Addr,
AtomicOrdering  Ord 
) const
overridevirtual
Value * ARMTargetLowering::emitStoreConditional ( IRBuilder<> &  Builder,
Value Val,
Value Addr,
AtomicOrdering  Ord 
) const
overridevirtual
Instruction * ARMTargetLowering::emitTrailingFence ( IRBuilder<> &  Builder,
AtomicOrdering  Ord,
bool  IsStore,
bool  IsLoad 
) const
overridevirtual
bool ARMTargetLowering::ExpandInlineAsm ( CallInst ) const
overridevirtual

This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to.

This is useful for turning simple inline asms into LLVM intrinsics, which gives the compiler more information about the behavior of the code.

Reimplemented from llvm::TargetLowering.

Definition at line 10737 of file ARMISelLowering.cpp.

References llvm::SmallVectorImpl< T >::clear(), llvm::dyn_cast(), llvm::InlineAsm::getAsmString(), llvm::IntegerType::getBitWidth(), llvm::CallInst::getCalledValue(), llvm::InlineAsm::getConstraintString(), llvm::Value::getType(), llvm::ARMSubtarget::hasV6Ops(), llvm::IntrinsicLowering::LowerToByteSwap(), llvm::SmallVectorTemplateCommon< T >::size(), and llvm::SplitString().

std::pair< const TargetRegisterClass *, uint8_t > ARMTargetLowering::findRepresentativeClass ( const TargetRegisterInfo TRI,
MVT  VT 
) const
overrideprotectedvirtual

Return the largest legal super-reg register class of the register class for the specified type and its associated "cost".

findRepresentativeClass - Return the largest legal super-reg register class of the register class for the specified type and its associated "cost".

Reimplemented from llvm::TargetLoweringBase.

Definition at line 993 of file ARMISelLowering.cpp.

References llvm::MVT::f32, llvm::MVT::f64, llvm::TargetLoweringBase::findRepresentativeClass(), llvm::MSP430ISD::RRC, llvm::MVT::SimpleTy, llvm::ARMSubtarget::useNEONForSinglePrecisionFP(), llvm::MVT::v16i8, llvm::MVT::v1i64, llvm::MVT::v2f32, llvm::MVT::v2f64, llvm::MVT::v2i32, llvm::MVT::v2i64, llvm::MVT::v4f32, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v4i64, llvm::MVT::v8i16, llvm::MVT::v8i64, and llvm::MVT::v8i8.

bool ARMTargetLowering::functionArgumentNeedsConsecutiveRegisters ( Type Ty,
CallingConv::ID  CallConv,
bool  isVarArg 
) const
overridevirtual

Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calling convention CallConv.

Return true if a type is an AAPCS-VFP homogeneous aggregate or one of [N x i32] or [N x i64].

This allows front-ends to skip emitting padding when passing according to AAPCS rules.

Reimplemented from llvm::TargetLowering.

Definition at line 11736 of file ARMISelLowering.cpp.

References llvm::CallingConv::ARM_AAPCS_VFP, llvm::dbgs(), DEBUG, llvm::Type::dump(), llvm::Type::getArrayElementType(), HA_UNKNOWN, llvm::Type::isArrayTy(), isHomogeneousAggregate(), and llvm::Type::isIntegerTy().

ARMTargetLowering::ConstraintType ARMTargetLowering::getConstraintType ( StringRef  Constraint) const
overridevirtual

getConstraintType - Given a constraint letter, return the type of constraint it is for this target.

Reimplemented from llvm::TargetLowering.

Definition at line 10771 of file ARMISelLowering.cpp.

References llvm::TargetLowering::C_Memory, llvm::TargetLowering::C_Other, llvm::TargetLowering::C_RegisterClass, llvm::TargetLowering::getConstraintType(), and llvm::StringRef::size().

unsigned llvm::ARMTargetLowering::getInlineAsmMemConstraint ( StringRef  ConstraintCode) const
inlineoverridevirtual
unsigned ARMTargetLowering::getJumpTableEncoding ( ) const
overridevirtual

Return the entry encoding for a jump table in the current function.

getJumpTableEncoding - Return the entry encoding for a jump table in the current function.

The returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.

Reimplemented from llvm::TargetLowering.

Definition at line 2445 of file ARMISelLowering.cpp.

References llvm::MachineJumpTableInfo::EK_Inline.

unsigned llvm::ARMTargetLowering::getMaxSupportedInterleaveFactor ( ) const
inlineoverridevirtual

Get the maximum supported factor for interleaved memory accesses.

Default to be the minimum interleave factor: 2.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 435 of file ARMISelLowering.h.

Referenced by lowerInterleavedLoad(), and lowerInterleavedStore().

EVT ARMTargetLowering::getOptimalMemOpType ( uint64_t  ,
unsigned  ,
unsigned  ,
bool  ,
bool  ,
bool  ,
MachineFunction  
) const
overridevirtual

Returns the target specific optimal type for load and store operations as a result of memset, memcpy, and memmove lowering.

If DstAlign is zero that means it's safe to destination alignment can satisfy any constraint. Similarly if SrcAlign is zero it means there isn't a need to check it against alignment requirement, probably because the source does not need to be loaded. If 'IsMemset' is true, that means it's expanding a memset. If 'ZeroMemset' is true, that means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it does not need to be loaded. It returns EVT::Other if the type should be determined using generic target-independent logic.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 10201 of file ARMISelLowering.cpp.

References allowsMisalignedMemoryAccesses(), llvm::MVT::f64, llvm::CallingConv::Fast, llvm::MachineFunction::getFunction(), llvm::Function::hasFnAttribute(), llvm::ARMSubtarget::hasNEON(), llvm::MVT::i16, llvm::MVT::i32, memOpAlign(), llvm::Attribute::NoImplicitFloat, llvm::MVT::Other, and llvm::MVT::v2f64.

bool ARMTargetLowering::getPostIndexedAddressParts ( SDNode N,
SDNode Op,
SDValue Base,
SDValue Offset,
ISD::MemIndexedMode AM,
SelectionDAG DAG 
) const
overridevirtual

getPostIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store.

Reimplemented from llvm::TargetLowering.

Definition at line 10639 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, getARMIndexedAddressParts(), llvm::SDNode::getOpcode(), getT2IndexedAddressParts(), llvm::ISD::isSEXTLoad(), llvm::ARMSubtarget::isThumb1Only(), llvm::ARMSubtarget::isThumb2(), llvm::AArch64DB::LD, llvm::ISD::POST_DEC, llvm::ISD::POST_INC, llvm::ISD::SEXTLOAD, and std::swap().

bool ARMTargetLowering::getPreIndexedAddressParts ( SDNode N,
SDValue Base,
SDValue Offset,
ISD::MemIndexedMode AM,
SelectionDAG DAG 
) const
overridevirtual

getPreIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mode by reference if the node's address can be legally represented as pre-indexed load / store address.

Reimplemented from llvm::TargetLowering.

Definition at line 10601 of file ARMISelLowering.cpp.

References getARMIndexedAddressParts(), llvm::SDValue::getNode(), getT2IndexedAddressParts(), llvm::ISD::isSEXTLoad(), llvm::ARMSubtarget::isThumb1Only(), llvm::ARMSubtarget::isThumb2(), llvm::AArch64DB::LD, llvm::ISD::PRE_DEC, llvm::ISD::PRE_INC, and llvm::ISD::SEXTLOAD.

const TargetRegisterClass * ARMTargetLowering::getRegClassFor ( MVT  VT) const
overridevirtual

getRegClassFor - Return the register class that should be used for the specified value type.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 1177 of file ARMISelLowering.cpp.

References llvm::TargetLoweringBase::getRegClassFor(), llvm::ARMSubtarget::hasNEON(), llvm::MVT::v4i64, and llvm::MVT::v8i64.

RCPair ARMTargetLowering::getRegForInlineAsmConstraint ( const TargetRegisterInfo TRI,
StringRef  Constraint,
MVT  VT 
) const
overridevirtual

Given a physical register constraint (e.g.

{edx}), return the register number and the register class for the register.

Given a register class constraint, like 'r', if this corresponds directly to an LLVM register class, return a register of 0 and the register class pointer.

This should only be used for C_Register constraints. On error, this returns a register number of 0 and a null register class pointer.

Reimplemented from llvm::TargetLowering.

Definition at line 10830 of file ARMISelLowering.cpp.

References llvm::MVT::f32, llvm::TargetLowering::getRegForInlineAsmConstraint(), llvm::MVT::getSizeInBits(), llvm::ARMSubtarget::isThumb(), llvm::ARMSubtarget::isThumb1Only(), llvm::MVT::Other, and llvm::StringRef::size().

Sched::Preference ARMTargetLowering::getSchedulingPreference ( SDNode ) const
overridevirtual
EVT ARMTargetLowering::getSetCCResultType ( const DataLayout DL,
LLVMContext Context,
EVT  VT 
) const
overridevirtual

getSetCCResultType - Return the value type to use for ISD::SETCC.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 1168 of file ARMISelLowering.cpp.

References llvm::EVT::changeVectorElementTypeToInteger(), llvm::TargetLoweringBase::getPointerTy(), and llvm::EVT::isVector().

TargetLowering::ConstraintWeight ARMTargetLowering::getSingleConstraintMatchWeight ( AsmOperandInfo info,
const char *  constraint 
) const
overridevirtual

Examine constraint string and operand type and determine a weight value.

Examine constraint type and operand type and determine a weight value.

The operand object must already have been set up with the operand type.

This object must already have been set up with the operand type and the current alternative constraint selected.

Reimplemented from llvm::TargetLowering.

Definition at line 10799 of file ARMISelLowering.cpp.

References llvm::TargetLowering::AsmOperandInfo::CallOperandVal, llvm::TargetLowering::CW_Default, llvm::TargetLowering::CW_Invalid, llvm::TargetLowering::CW_Register, llvm::TargetLowering::CW_SpecificReg, llvm::TargetLowering::getSingleConstraintMatchWeight(), llvm::Value::getType(), llvm::Type::isFloatingPointTy(), llvm::Type::isIntegerTy(), and llvm::ARMSubtarget::isThumb().

const ARMSubtarget* llvm::ARMTargetLowering::getSubtarget ( ) const
inline

Definition at line 376 of file ARMISelLowering.h.

const char * ARMTargetLowering::getTargetNodeName ( unsigned  Opcode) const
overridevirtual

This method returns the name of a target specific DAG node.

Reimplemented from llvm::TargetLowering.

Definition at line 1030 of file ARMISelLowering.cpp.

References llvm::ARMISD::ADDC, llvm::ARMISD::ADDE, llvm::ARMISD::BCC_i64, llvm::ARMISD::BFI, llvm::ARMISD::BR2_JT, llvm::ARMISD::BR_JT, llvm::ARMISD::BRCOND, llvm::ARMISD::BUILD_VECTOR, llvm::ARMISD::CALL, llvm::ARMISD::CALL_NOLINK, llvm::ARMISD::CALL_PRED, llvm::ARMISD::CMN, llvm::ARMISD::CMOV, llvm::ARMISD::CMP, llvm::ARMISD::CMPFP, llvm::ARMISD::CMPFPw0, llvm::ARMISD::CMPZ, llvm::ARMISD::COPY_STRUCT_BYVAL, llvm::ARMISD::DYN_ALLOC, llvm::ARMISD::EH_SJLJ_LONGJMP, llvm::ARMISD::EH_SJLJ_SETJMP, llvm::ARMISD::FIRST_NUMBER, llvm::ARMISD::FMAX, llvm::ARMISD::FMIN, llvm::ARMISD::FMSTAT, llvm::ARMISD::INTRET_FLAG, llvm::ARMISD::MEMBARRIER_MCR, llvm::ARMISD::PIC_ADD, llvm::ARMISD::PRELOAD, llvm::ARMISD::RBIT, llvm::ARMISD::RET_FLAG, llvm::ARMISD::RRX, llvm::ARMISD::SMLAL, llvm::ARMISD::SRA_FLAG, llvm::ARMISD::SRL_FLAG, llvm::ARMISD::SUBC, llvm::ARMISD::SUBE, llvm::ARMISD::TC_RETURN, llvm::ARMISD::tCALL, llvm::ARMISD::THREAD_POINTER, llvm::ARMISD::UMLAL, llvm::ARMISD::VBICIMM, llvm::ARMISD::VBSL, llvm::ARMISD::VCEQ, llvm::ARMISD::VCEQZ, llvm::ARMISD::VCGE, llvm::ARMISD::VCGEU, llvm::ARMISD::VCGEZ, llvm::ARMISD::VCGT, llvm::ARMISD::VCGTU, llvm::ARMISD::VCGTZ, llvm::ARMISD::VCLEZ, llvm::ARMISD::VCLTZ, llvm::ARMISD::VDUP, llvm::ARMISD::VDUPLANE, llvm::ARMISD::VEXT, llvm::ARMISD::VGETLANEs, llvm::ARMISD::VGETLANEu, llvm::ARMISD::VLD1_UPD, llvm::ARMISD::VLD2_UPD, llvm::ARMISD::VLD2DUP, llvm::ARMISD::VLD2DUP_UPD, llvm::ARMISD::VLD2LN_UPD, llvm::ARMISD::VLD3_UPD, llvm::ARMISD::VLD3DUP, llvm::ARMISD::VLD3DUP_UPD, llvm::ARMISD::VLD3LN_UPD, llvm::ARMISD::VLD4_UPD, llvm::ARMISD::VLD4DUP, llvm::ARMISD::VLD4DUP_UPD, llvm::ARMISD::VLD4LN_UPD, llvm::ARMISD::VMAXNM, llvm::ARMISD::VMINNM, llvm::ARMISD::VMOVDRR, llvm::ARMISD::VMOVFPIMM, llvm::ARMISD::VMOVIMM, llvm::ARMISD::VMOVRRD, llvm::ARMISD::VMULLs, llvm::ARMISD::VMULLu, llvm::ARMISD::VMVNIMM, llvm::ARMISD::VORRIMM, llvm::ARMISD::VQRSHRNs, llvm::ARMISD::VQRSHRNsu, llvm::ARMISD::VQRSHRNu, llvm::ARMISD::VQSHLs, llvm::ARMISD::VQSHLsu, llvm::ARMISD::VQSHLu, llvm::ARMISD::VQSHRNs, llvm::ARMISD::VQSHRNsu, llvm::ARMISD::VQSHRNu, llvm::ARMISD::VREV16, llvm::ARMISD::VREV32, llvm::ARMISD::VREV64, llvm::ARMISD::VRSHRN, llvm::ARMISD::VRSHRs, llvm::ARMISD::VRSHRu, llvm::ARMISD::VSHL, llvm::ARMISD::VSHRs, llvm::ARMISD::VSHRu, llvm::ARMISD::VSLI, llvm::ARMISD::VSRI, llvm::ARMISD::VST1_UPD, llvm::ARMISD::VST2_UPD, llvm::ARMISD::VST2LN_UPD, llvm::ARMISD::VST3_UPD, llvm::ARMISD::VST3LN_UPD, llvm::ARMISD::VST4_UPD, llvm::ARMISD::VST4LN_UPD, llvm::ARMISD::VTBL1, llvm::ARMISD::VTBL2, llvm::ARMISD::VTRN, llvm::ARMISD::VTST, llvm::ARMISD::VUZP, llvm::ARMISD::VZIP, llvm::ARMISD::WIN__CHKSTK, llvm::ARMISD::Wrapper, llvm::ARMISD::WrapperJT, and llvm::ARMISD::WrapperPIC.

bool ARMTargetLowering::getTgtMemIntrinsic ( IntrinsicInfo Info,
const CallInst I,
unsigned  Intrinsic 
) const
overridevirtual
bool ARMTargetLowering::hasLoadLinkedStoreConditional ( ) const
overridevirtual

True if AtomicExpandPass should use emitLoadLinked/emitStoreConditional and expand AtomicCmpXchgInst.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 11298 of file ARMISelLowering.cpp.

bool ARMTargetLowering::isDesirableToTransformToIntegerOp ( unsigned  ,
EVT   
) const
overridevirtual

Return true if it is profitable for dag combiner to transform a floating point op of specified opcode to a equivalent op of an integer type.

e.g. f32 load -> i32 load can be profitable on ARM.

Reimplemented from llvm::TargetLowering.

Definition at line 10154 of file ARMISelLowering.cpp.

References llvm::MVT::f32, llvm::ISD::LOAD, and llvm::ISD::STORE.

bool ARMTargetLowering::isFPImmLegal ( const APFloat Imm,
EVT  VT 
) const
overridevirtual

isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively.

If false, the legalizer will materialize the FP immediate as a load from a constant pool.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 11162 of file ARMISelLowering.cpp.

References llvm::MVT::f32, llvm::MVT::f64, llvm::ARM_AM::getFP32Imm(), llvm::ARMSubtarget::hasVFP3(), and llvm::ARMSubtarget::isFPOnlySP().

bool ARMTargetLowering::isLegalAddImmediate ( int64_t  Imm) const
overridevirtual

isLegalAddImmediate - Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register and the immediate without having to materialize the immediate into a register.

isLegalAddImmediate - Return true if the specified immediate is a legal add or sub immediate, that is the target has add or sub instructions which can add a register with the immediate without having to materialize the immediate into a register.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 10502 of file ARMISelLowering.cpp.

References llvm::abs(), llvm::ARM_AM::getSOImmVal(), llvm::ARM_AM::getT2SOImmVal(), llvm::ARMSubtarget::isThumb(), and llvm::ARMSubtarget::isThumb2().

bool ARMTargetLowering::isLegalAddressingMode ( const DataLayout DL,
const AddrMode AM,
Type Ty,
unsigned  AS 
) const
overridevirtual
bool ARMTargetLowering::isLegalICmpImmediate ( int64_t  Imm) const
overridevirtual

isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 10488 of file ARMISelLowering.cpp.

References llvm::abs(), llvm::ARM_AM::getSOImmVal(), llvm::ARM_AM::getT2SOImmVal(), llvm::ARMSubtarget::isThumb(), and llvm::ARMSubtarget::isThumb2().

bool ARMTargetLowering::isLegalT2ScaledAddressingMode ( const AddrMode AM,
EVT  VT 
) const
bool llvm::ARMTargetLowering::isNoopAddrSpaceCast ( unsigned  SrcAS,
unsigned  DestAS 
) const
inlineoverridevirtual

Returns true if a cast between SrcAS and DestAS is a noop.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 385 of file ARMISelLowering.h.

bool ARMTargetLowering::isOffsetFoldingLegal ( const GlobalAddressSDNode GA) const
overridevirtual

Return true if folding a constant offset with the given GlobalAddress is legal.

It is frequently not legal in PIC relocation models.

Reimplemented from llvm::TargetLowering.

Definition at line 11145 of file ARMISelLowering.cpp.

bool llvm::ARMTargetLowering::isSelectSupported ( SelectSupportKind  Kind) const
inlineoverridevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 246 of file ARMISelLowering.h.

References llvm::TargetLoweringBase::ScalarCondVectorVal.

bool ARMTargetLowering::isShuffleMaskLegal ( const SmallVectorImpl< int > &  M,
EVT  VT 
) const
overridevirtual

isShuffleMaskLegal - Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks.

By default, if a target supports the VECTOR_SHUFFLE node, all mask values are assumed to be legal.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 5584 of file ARMISelLowering.cpp.

References llvm::EVT::getSizeInBits(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::is128BitVector(), llvm::EVT::is64BitVector(), isNEONTwoResultShuffleMask(), isReverseMask(), llvm::ShuffleVectorSDNode::isSplatMask(), isVEXTMask(), isVREVMask(), isVTBLMask(), PerfectShuffleTable, llvm::MVT::v16i8, and llvm::MVT::v8i16.

bool ARMTargetLowering::isVectorLoadExtDesirable ( SDValue  ExtVal) const
overridevirtual
bool ARMTargetLowering::isZExtFree ( SDValue  Val,
EVT  VT2 
) const
overridevirtual

Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicitly zero-extended such as ARM ldrb / ldrh or because it's folded such as X86 zero-extending loads).

Reimplemented from llvm::TargetLoweringBase.

Definition at line 10234 of file ARMISelLowering.cpp.

References llvm::SDValue::getOpcode(), llvm::EVT::getSimpleVT(), llvm::SDValue::getValueType(), llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i8, llvm::EVT::isInteger(), llvm::EVT::isSimple(), llvm::ISD::LOAD, and llvm::MVT::SimpleTy.

void ARMTargetLowering::LowerAsmOperandForConstraint ( SDValue  Op,
std::string &  Constraint,
std::vector< SDValue > &  Ops,
SelectionDAG DAG 
) const
overridevirtual

LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector.

If it is invalid, don't add anything to Ops. If hasMemory is true it means one of the asm constraint of the inline asm instruction being processed is 'm'.

If it is invalid, don't add anything to Ops.

Reimplemented from llvm::TargetLowering.

Definition at line 10881 of file ARMISelLowering.cpp.

References llvm::dyn_cast(), llvm::SDValue::getNode(), llvm::ConstantSDNode::getSExtValue(), llvm::ARM_AM::getSOImmVal(), llvm::ARM_AM::getT2SOImmVal(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValueType(), llvm::ARMSubtarget::hasV6T2Ops(), llvm::ARMSubtarget::isThumb(), llvm::ARMSubtarget::isThumb1Only(), llvm::ARMSubtarget::isThumb2(), llvm::ARM_AM::isThumbImmShiftedVal(), and llvm::TargetLowering::LowerAsmOperandForConstraint().

bool ARMTargetLowering::lowerInterleavedLoad ( LoadInst LI,
ArrayRef< ShuffleVectorInst * >  Shuffles,
ArrayRef< unsigned Indices,
unsigned  Factor 
) const
overridevirtual

Lower an interleaved load into a vldN intrinsic.

E.g. Lower an interleaved load (Factor = 2): wide.vec = load <8 x i32>, <8 x i32>* ptr, align 4 v0 = shuffle wide.vec, undef, <0, 2, 4, 6> ; Extract even elements v1 = shuffle wide.vec, undef, <1, 3, 5, 7> ; Extract odd elements

Into: vld2 = { <4 x i32>, <4 x i32> } call llvm.arm.neon.vld2(ptr, 4) vec0 = extractelement { <4 x i32>, <4 x i32> } vld2, i32 0 vec1 = extractelement { <4 x i32>, <4 x i32> } vld2, i32 1

Reimplemented from llvm::TargetLoweringBase.

Definition at line 11524 of file ARMISelLowering.cpp.

References llvm::ArrayRef< T >::empty(), llvm::VectorType::get(), llvm::LoadInst::getAlignment(), llvm::Module::getDataLayout(), llvm::Intrinsic::getDeclaration(), llvm::Type::getInt8PtrTy(), llvm::DataLayout::getIntPtrType(), getMaxSupportedInterleaveFactor(), llvm::Instruction::getModule(), llvm::LoadInst::getPointerAddressSpace(), llvm::LoadInst::getPointerOperand(), llvm::ShuffleVectorInst::getType(), llvm::DataLayout::getTypeAllocSizeInBits(), llvm::Type::getVectorElementType(), llvm::Type::getVectorNumElements(), llvm::Type::isPointerTy(), llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::Value::replaceAllUsesWith(), and llvm::ArrayRef< T >::size().

bool ARMTargetLowering::lowerInterleavedStore ( StoreInst SI,
ShuffleVectorInst SVI,
unsigned  Factor 
) const
overridevirtual

Lower an interleaved store into a vstN intrinsic.

E.g. Lower an interleaved store (Factor = 3): i.vec = shuffle <8 x i32> v0, <8 x i32> v1, <0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11> store <12 x i32> i.vec, <12 x i32>* ptr, align 4

Into: sub.v0 = shuffle <8 x i32> v0, <8 x i32> v1, <0, 1, 2, 3> sub.v1 = shuffle <8 x i32> v0, <8 x i32> v1, <4, 5, 6, 7> sub.v2 = shuffle <8 x i32> v0, <8 x i32> v1, <8, 9, 10, 11> call void llvm.arm.neon.vst3(ptr, sub.v0, sub.v1, sub.v2, 4)

Note that the new shufflevectors will be removed and we'll only generate one vst3 instruction in CodeGen.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 11612 of file ARMISelLowering.cpp.

References llvm::IRBuilder< preserveNames, T, Inserter >::CreateBitCast(), llvm::IRBuilder< preserveNames, T, Inserter >::CreateCall(), llvm::IRBuilder< preserveNames, T, Inserter >::CreatePtrToInt(), llvm::IRBuilder< preserveNames, T, Inserter >::CreateShuffleVector(), llvm::VectorType::get(), llvm::StoreInst::getAlignment(), llvm::Module::getDataLayout(), llvm::Intrinsic::getDeclaration(), llvm::IRBuilderBase::getInt32(), llvm::IRBuilderBase::getInt8PtrTy(), llvm::DataLayout::getIntPtrType(), getMaxSupportedInterleaveFactor(), llvm::Instruction::getModule(), llvm::User::getOperand(), llvm::StoreInst::getPointerAddressSpace(), llvm::StoreInst::getPointerOperand(), getSequentialMask(), llvm::Value::getType(), llvm::ShuffleVectorInst::getType(), llvm::DataLayout::getTypeAllocSizeInBits(), llvm::Type::getVectorElementType(), llvm::Type::getVectorNumElements(), and llvm::Type::isPointerTy().

SDValue ARMTargetLowering::LowerOperation ( SDValue  Op,
SelectionDAG DAG 
) const
overridevirtual

This callback is invoked for operations that are unsupported by the target, which are registered to use 'custom' lowering, and whose defined values are all legal.

If the target has no operations that require custom lowering, it need not implement this. The default implementation of this aborts.

Reimplemented from llvm::TargetLowering.

Definition at line 6548 of file ARMISelLowering.cpp.

References llvm::ISD::ADDC, llvm::ISD::ADDE, llvm::ISD::ATOMIC_FENCE, llvm::ISD::ATOMIC_LOAD, llvm::ISD::ATOMIC_STORE, llvm::ISD::BITCAST, llvm::ISD::BlockAddress, llvm::ISD::BR_CC, llvm::ISD::BR_JT, llvm::ISD::BUILD_VECTOR, llvm::Triple::COFF, llvm::ISD::CONCAT_VECTORS, llvm::ISD::ConstantFP, llvm::ISD::ConstantPool, llvm::ISD::CTPOP, llvm::ISD::CTTZ, llvm::ISD::CTTZ_ZERO_UNDEF, llvm::ISD::DYNAMIC_STACKALLOC, llvm::ISD::EH_SJLJ_LONGJMP, llvm::ISD::EH_SJLJ_SETJMP, llvm::Triple::ELF, ExpandBITCAST(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FCOPYSIGN, llvm::ISD::FLT_ROUNDS_, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::ISD::FRAMEADDR, llvm::ISD::FSINCOS, llvm::SDValue::getNode(), llvm::Triple::getObjectFormat(), llvm::SDValue::getOpcode(), llvm::ARMSubtarget::getTargetTriple(), llvm::ISD::GLOBAL_OFFSET_TABLE, llvm::ISD::GlobalAddress, llvm::ISD::GlobalTLSAddress, llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::Triple::isWindowsItaniumEnvironment(), llvm_unreachable, LowerADDC_ADDE_SUBC_SUBE(), LowerATOMIC_FENCE(), LowerAtomicLoadStore(), LowerCONCAT_VECTORS(), LowerConstantPool(), LowerCTPOP(), LowerCTTZ(), LowerEXTRACT_VECTOR_ELT(), LowerINSERT_VECTOR_ELT(), LowerMUL(), LowerPREFETCH(), LowerSDIV(), LowerShift(), LowerUDIV(), LowerVASTART(), LowerVECTOR_SHUFFLE(), LowerVSETCC(), LowerWRITE_REGISTER(), llvm::Triple::MachO, llvm::ISD::MUL, llvm::ISD::PREFETCH, llvm::ISD::RETURNADDR, llvm::ISD::SADDO, llvm::ISD::SDIV, llvm::ISD::SDIVREM, llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::ISD::SETCC, llvm::ISD::SHL, llvm::ISD::SHL_PARTS, llvm::ISD::SINT_TO_FP, llvm::ISD::SRA, llvm::ISD::SRA_PARTS, llvm::ISD::SRL, llvm::ISD::SRL_PARTS, llvm::ISD::SSUBO, llvm::ISD::SUBC, llvm::ISD::SUBE, llvm::ISD::UADDO, llvm::ISD::UDIV, llvm::ISD::UDIVREM, llvm::ISD::UINT_TO_FP, llvm::ISD::USUBO, llvm::ISD::VASTART, llvm::ISD::VECTOR_SHUFFLE, and llvm::ISD::WRITE_REGISTER.

Instruction * ARMTargetLowering::makeDMB ( IRBuilder<> &  Builder,
ARM_MB::MemBOpt  Domain 
) const
SDValue ARMTargetLowering::PerformCMOVCombine ( SDNode N,
SelectionDAG DAG 
) const
SDValue ARMTargetLowering::PerformDAGCombine ( SDNode N,
DAGCombinerInfo DCI 
) const
overridevirtual

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for.

The semantics are as follows: Return Value: SDValue.Val == 0 - No change was made SDValue.Val == N - N was replaced, is dead, and is already handled. otherwise - N should be replaced by the returned Operand.

In addition, methods provided by DAGCombinerInfo may be used to perform more complex transformations.

Reimplemented from llvm::TargetLowering.

Definition at line 10091 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::ADDC, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::ARMISD::BFI, llvm::ARMISD::BUILD_VECTOR, llvm::ISD::BUILD_VECTOR, llvm::ARMISD::CMOV, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::ISD::FDIV, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::ISD::LOAD, llvm::ISD::MUL, llvm::ISD::OR, PerformADDCCombine(), PerformADDCombine(), PerformANDCombine(), PerformARMBUILD_VECTORCombine(), PerformBFICombine(), PerformBUILD_VECTORCombine(), PerformCMOVCombine(), PerformExtendCombine(), PerformInsertEltCombine(), PerformIntrinsicCombine(), PerformLOADCombine(), PerformMULCombine(), PerformORCombine(), PerformSELECT_CCCombine(), PerformShiftCombine(), PerformSTORECombine(), PerformSUBCombine(), PerformVCVTCombine(), PerformVDIVCombine(), PerformVDUPLANECombine(), PerformVECTOR_SHUFFLECombine(), PerformVLDCombine(), PerformVMOVDRRCombine(), PerformVMOVRRDCombine(), PerformXORCombine(), llvm::ISD::SELECT_CC, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::STORE, llvm::ISD::SUB, llvm::ARMISD::VDUPLANE, llvm::ISD::VECTOR_SHUFFLE, llvm::ARMISD::VLD2DUP, llvm::ARMISD::VLD3DUP, llvm::ARMISD::VLD4DUP, llvm::ARMISD::VMOVDRR, llvm::ARMISD::VMOVRRD, llvm::ISD::XOR, and llvm::ISD::ZERO_EXTEND.

void ARMTargetLowering::ReplaceNodeResults ( SDNode N,
SmallVectorImpl< SDValue > &  Results,
SelectionDAG DAG 
) const
overridevirtual
bool ARMTargetLowering::shouldAlignPointerArgs ( CallInst ,
unsigned ,
unsigned  
) const
overridevirtual

Return true if the pointer arguments to CI should be aligned by aligning the object whose address is being passed.

If so then MinSize is set to the minimum size the object must be to be aligned and PrefAlign is set to the preferred alignment.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 1193 of file ARMISelLowering.cpp.

References llvm::ARMSubtarget::hasV6Ops(), and llvm::ARMSubtarget::isMClass().

bool ARMTargetLowering::shouldConvertConstantLoadToIntImm ( const APInt Imm,
Type Ty 
) const
overridevirtual

Returns true if it is beneficial to convert a load of a constant to just the constant itself.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 11288 of file ARMISelLowering.cpp.

References llvm::tgtok::Bits, llvm::Type::getPrimitiveSizeInBits(), and llvm::Type::isIntegerTy().

bool ARMTargetLowering::shouldExpandAtomicLoadInIR ( LoadInst LI) const
overridevirtual

Returns true if the given (atomic) load should be expanded by the IR-level AtomicExpand pass into a load-linked instruction (through emitLoadLinked()).

Reimplemented from llvm::TargetLoweringBase.

Definition at line 11395 of file ARMISelLowering.cpp.

References llvm::Type::getPrimitiveSizeInBits(), llvm::Value::getType(), and llvm::ARMSubtarget::isMClass().

TargetLoweringBase::AtomicRMWExpansionKind ARMTargetLowering::shouldExpandAtomicRMWInIR ( AtomicRMWInst ) const
overridevirtual

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.

Default is to never expand.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 11403 of file ARMISelLowering.cpp.

References llvm::Type::getPrimitiveSizeInBits(), llvm::Value::getType(), llvm::ARMSubtarget::isMClass(), llvm::TargetLoweringBase::LLSC, and llvm::TargetLoweringBase::None.

bool ARMTargetLowering::shouldExpandAtomicStoreInIR ( StoreInst SI) const
overridevirtual

Returns true if the given (atomic) store should be expanded by the IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 11383 of file ARMISelLowering.cpp.

References llvm::Type::getPrimitiveSizeInBits(), llvm::Value::getType(), llvm::StoreInst::getValueOperand(), and llvm::ARMSubtarget::isMClass().

bool ARMTargetLowering::useLoadStackGuardNode ( ) const
overridevirtual

If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.

Reimplemented from llvm::TargetLowering.

Definition at line 11411 of file ARMISelLowering.cpp.

References llvm::ARMSubtarget::isTargetMachO().

bool ARMTargetLowering::useSoftFloat ( ) const
overridevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 978 of file ARMISelLowering.cpp.

References llvm::ARMSubtarget::useSoftFloat().


The documentation for this class was generated from the following files: