27 #define GET_INSTRINFO_CTOR_DTOR
28 #include "MipsGenInstrInfo.inc"
31 void MipsInstrInfo::anchor() {}
35 Subtarget(STI), UncondBrOpc(UncondBr) {}
54 BuildMI(MBB, MI, DL,
get(Mips::NOP));
58 unsigned Flag)
const {
71 void MipsInstrInfo::AnalyzeCondBr(
const MachineInstr *Inst,
unsigned Opc,
74 assert(getAnalyzableBrOpc(Opc) &&
"Not an analyzable branch");
82 for (
int i=0; i<NumOp-1; i++)
90 bool AllowModify)
const {
100 unsigned Opc = Cond[0].getImm();
104 for (
unsigned i = 1; i < Cond.
size(); ++i) {
106 MIB.
addReg(Cond[i].getReg());
107 else if (Cond[i].isImm())
108 MIB.
addImm(Cond[i].getImm());
110 assert(
true &&
"Cannot copy operand");
119 assert(TBB &&
"InsertBranch must not be told to insert a fallthrough");
126 assert((Cond.
size() <= 3) &&
127 "# of Mips branch conditions must be <= 3!");
131 BuildCondBr(MBB, TBB, DL, Cond);
141 BuildCondBr(MBB, TBB, DL, Cond);
151 while (I != REnd && I->isDebugValue())
158 for (removed = 0; I != REnd && removed < 2; ++
I, ++removed)
159 if (!getAnalyzableBrOpc(I->getOpcode()))
162 MBB.
erase(I.base(), FirstBr.base());
171 assert( (Cond.
size() && Cond.
size() <= 3) &&
172 "Invalid Mips branch condition!");
185 while (I != REnd && I->isDebugValue())
188 if (I == REnd || !isUnpredicatedTerminator(&*I)) {
196 unsigned LastOpc = LastInst->
getOpcode();
200 if (!getAnalyzableBrOpc(LastOpc))
204 unsigned SecondLastOpc = 0;
208 SecondLastInst = &*
I;
209 SecondLastOpc = getAnalyzableBrOpc(SecondLastInst->
getOpcode());
212 if (isUnpredicatedTerminator(SecondLastInst) && !SecondLastOpc)
217 if (!SecondLastOpc) {
225 AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
231 if (++I != REnd && isUnpredicatedTerminator(&*I))
234 BranchInstrs.
insert(BranchInstrs.
begin(), SecondLastInst);
254 AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);
270 case Mips::CONSTPOOL_ENTRY:
281 MIB =
BuildMI(*I->getParent(),
I, I->getDebugLoc(),
get(NewOpc));
283 for (
unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J)
286 MIB.
setMemRefs(I->memoperands_begin(), I->memoperands_end());
static bool isReg(const MCInst &MI, unsigned OpNo)
bool isZeroImm(const MachineOperand &op) const
void push_back(const T &Elt)
const MachineFunction * getParent() const
getParent - Return the MachineFunction containing this basic block.
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, DebugLoc DL) const override
MachineBasicBlock * getMBB() const
Describe properties that are true of each instruction in the target description file.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
const char * getSymbolName() const
virtual unsigned getOppositeBranchOpc(unsigned Opc) const =0
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
Insert nop instruction when hazard condition is found.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, unsigned f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
getMachineMemOperand - Allocate a new MachineMemOperand.
static MachinePointerInfo getFixedStack(int FI, int64_t offset=0)
getFixedStack - Return a MachinePointerInfo record that refers to the the specified FrameIndex...
bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Branch Analysis.
MachineMemOperand - A description of a memory reference used in the backend.
MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBrOpc)
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
const MachineInstrBuilder & addImm(int64_t Val) const
addImm - Add a new immediate operand.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
size_t size() const
size - Get the array size.
reverse_iterator rbegin()
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Flag
These should be considered private to the implementation of the MCInstrDesc class.
const MachineBasicBlock * getParent() const
bundle_iterator< MachineInstr, instr_iterator > iterator
const MachineInstrBuilder & setMemRefs(MachineInstr::mmo_iterator b, MachineInstr::mmo_iterator e) const
const MipsInstrInfo * createMips16InstrInfo(const MipsSubtarget &STI)
Create MipsInstrInfo objects.
const MachineOperand & getOperand(unsigned i) const
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
bool isIndirectBranch(QueryType Type=AnyInBundle) const
Return true if this is an indirect branch, such as a branch through a register.
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
bool ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
ReverseBranchCondition - Return the inverse opcode of the specified Branch instruction.
bool empty() const
empty - Check if the array is empty.
bool inMips16Mode() const
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
BuildMI - Builder interface.
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
MachineFrameInfo * getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
unsigned RemoveBranch(MachineBasicBlock &MBB) const override
iterator insert(iterator I, T &&Elt)
Representation of each machine instruction.
static MachineOperand CreateImm(int64_t Val)
const MipsInstrInfo * createMipsSEInstrInfo(const MipsSubtarget &STI)
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
std::reverse_iterator< iterator > reverse_iterator
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
unsigned GetInstSizeInBytes(const MachineInstr *MI) const
Return the number of bytes of code the specified instruction may be.
MachineMemOperand * GetMemOperand(MachineBasicBlock &MBB, int FI, unsigned Flag) const
static const MipsInstrInfo * create(MipsSubtarget &STI)
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
addReg - Add a new virtual register operand...
MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc, MachineBasicBlock::iterator I) const
Create an instruction which has the same operands and memory operands as MI but has a new opcode...
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.